1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
5 Free Software Foundation, Inc.
6 Contributed by A. Lichnewsky, lich@inria.inria.fr.
7 Changes by Michael Meissner, meissner@osf.org.
8 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
9 Brendan Eich, brendan@microunity.com.
11 This file is part of GCC.
13 GCC is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GCC is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GCC; see the file COPYING3. If not see
25 <http://www.gnu.org/licenses/>. */
29 #include "coretypes.h"
33 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
36 #include "insn-attr.h"
52 #include "target-def.h"
53 #include "langhooks.h"
54 #include "cfglayout.h"
55 #include "sched-int.h"
58 #include "diagnostic.h"
59 #include "target-globals.h"
62 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
63 #define UNSPEC_ADDRESS_P(X) \
64 (GET_CODE (X) == UNSPEC \
65 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
66 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
68 /* Extract the symbol or label from UNSPEC wrapper X. */
69 #define UNSPEC_ADDRESS(X) \
72 /* Extract the symbol type from UNSPEC wrapper X. */
73 #define UNSPEC_ADDRESS_TYPE(X) \
74 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
76 /* The maximum distance between the top of the stack frame and the
77 value $sp has when we save and restore registers.
79 The value for normal-mode code must be a SMALL_OPERAND and must
80 preserve the maximum stack alignment. We therefore use a value
81 of 0x7ff0 in this case.
83 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
84 up to 0x7f8 bytes and can usually save or restore all the registers
85 that we need to save or restore. (Note that we can only use these
86 instructions for o32, for which the stack alignment is 8 bytes.)
88 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
89 RESTORE are not available. We can then use unextended instructions
90 to save and restore registers, and to allocate and deallocate the top
92 #define MIPS_MAX_FIRST_STACK_STEP \
93 (!TARGET_MIPS16 ? 0x7ff0 \
94 : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
95 : TARGET_64BIT ? 0x100 : 0x400)
97 /* True if INSN is a mips.md pattern or asm statement. */
98 #define USEFUL_INSN_P(INSN) \
99 (NONDEBUG_INSN_P (INSN) \
100 && GET_CODE (PATTERN (INSN)) != USE \
101 && GET_CODE (PATTERN (INSN)) != CLOBBER \
102 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
103 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
105 /* If INSN is a delayed branch sequence, return the first instruction
106 in the sequence, otherwise return INSN itself. */
107 #define SEQ_BEGIN(INSN) \
108 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
109 ? XVECEXP (PATTERN (INSN), 0, 0) \
112 /* Likewise for the last instruction in a delayed branch sequence. */
113 #define SEQ_END(INSN) \
114 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
115 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
118 /* Execute the following loop body with SUBINSN set to each instruction
119 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
120 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
121 for ((SUBINSN) = SEQ_BEGIN (INSN); \
122 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
123 (SUBINSN) = NEXT_INSN (SUBINSN))
125 /* True if bit BIT is set in VALUE. */
126 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
128 /* Return the opcode for a ptr_mode load of the form:
130 l[wd] DEST, OFFSET(BASE). */
131 #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \
132 (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \
137 /* Return the opcode to move register SRC into register DEST. */
138 #define MIPS_MOVE(DEST, SRC) \
139 ((TARGET_64BIT ? 0x2d : 0x21) \
143 /* Return the opcode for:
146 #define MIPS_LUI(DEST, VALUE) \
147 ((0xf << 26) | ((DEST) << 16) | (VALUE))
149 /* Return the opcode to jump to register DEST. */
150 #define MIPS_JR(DEST) \
151 (((DEST) << 21) | 0x8)
153 /* Return the opcode for:
155 bal . + (1 + OFFSET) * 4. */
156 #define MIPS_BAL(OFFSET) \
157 ((0x1 << 26) | (0x11 << 16) | (OFFSET))
159 /* Return the usual opcode for a nop. */
162 /* Classifies an address.
165 A natural register + offset address. The register satisfies
166 mips_valid_base_register_p and the offset is a const_arith_operand.
169 A LO_SUM rtx. The first operand is a valid base register and
170 the second operand is a symbolic address.
173 A signed 16-bit constant address.
176 A constant symbolic address. */
177 enum mips_address_type {
184 /* Macros to create an enumeration identifier for a function prototype. */
185 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
186 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
187 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
188 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
190 /* Classifies the prototype of a built-in function. */
191 enum mips_function_type {
192 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
193 #include "config/mips/mips-ftypes.def"
194 #undef DEF_MIPS_FTYPE
198 /* Specifies how a built-in function should be converted into rtl. */
199 enum mips_builtin_type {
200 /* The function corresponds directly to an .md pattern. The return
201 value is mapped to operand 0 and the arguments are mapped to
202 operands 1 and above. */
205 /* The function corresponds directly to an .md pattern. There is no return
206 value and the arguments are mapped to operands 0 and above. */
207 MIPS_BUILTIN_DIRECT_NO_TARGET,
209 /* The function corresponds to a comparison instruction followed by
210 a mips_cond_move_tf_ps pattern. The first two arguments are the
211 values to compare and the second two arguments are the vector
212 operands for the movt.ps or movf.ps instruction (in assembly order). */
216 /* The function corresponds to a V2SF comparison instruction. Operand 0
217 of this instruction is the result of the comparison, which has mode
218 CCV2 or CCV4. The function arguments are mapped to operands 1 and
219 above. The function's return value is an SImode boolean that is
220 true under the following conditions:
222 MIPS_BUILTIN_CMP_ANY: one of the registers is true
223 MIPS_BUILTIN_CMP_ALL: all of the registers are true
224 MIPS_BUILTIN_CMP_LOWER: the first register is true
225 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
226 MIPS_BUILTIN_CMP_ANY,
227 MIPS_BUILTIN_CMP_ALL,
228 MIPS_BUILTIN_CMP_UPPER,
229 MIPS_BUILTIN_CMP_LOWER,
231 /* As above, but the instruction only sets a single $fcc register. */
232 MIPS_BUILTIN_CMP_SINGLE,
234 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
235 MIPS_BUILTIN_BPOSGE32
238 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
239 #define MIPS_FP_CONDITIONS(MACRO) \
257 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
258 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
259 enum mips_fp_condition {
260 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
263 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
264 #define STRINGIFY(X) #X
265 static const char *const mips_fp_conditions[] = {
266 MIPS_FP_CONDITIONS (STRINGIFY)
269 /* Information about a function's frame layout. */
270 struct GTY(()) mips_frame_info {
271 /* The size of the frame in bytes. */
272 HOST_WIDE_INT total_size;
274 /* The number of bytes allocated to variables. */
275 HOST_WIDE_INT var_size;
277 /* The number of bytes allocated to outgoing function arguments. */
278 HOST_WIDE_INT args_size;
280 /* The number of bytes allocated to the .cprestore slot, or 0 if there
282 HOST_WIDE_INT cprestore_size;
284 /* Bit X is set if the function saves or restores GPR X. */
287 /* Likewise FPR X. */
290 /* Likewise doubleword accumulator X ($acX). */
291 unsigned int acc_mask;
293 /* The number of GPRs, FPRs, doubleword accumulators and COP0
297 unsigned int num_acc;
298 unsigned int num_cop0_regs;
300 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
301 save slots from the top of the frame, or zero if no such slots are
303 HOST_WIDE_INT gp_save_offset;
304 HOST_WIDE_INT fp_save_offset;
305 HOST_WIDE_INT acc_save_offset;
306 HOST_WIDE_INT cop0_save_offset;
308 /* Likewise, but giving offsets from the bottom of the frame. */
309 HOST_WIDE_INT gp_sp_offset;
310 HOST_WIDE_INT fp_sp_offset;
311 HOST_WIDE_INT acc_sp_offset;
312 HOST_WIDE_INT cop0_sp_offset;
314 /* Similar, but the value passed to _mcount. */
315 HOST_WIDE_INT ra_fp_offset;
317 /* The offset of arg_pointer_rtx from the bottom of the frame. */
318 HOST_WIDE_INT arg_pointer_offset;
320 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
321 HOST_WIDE_INT hard_frame_pointer_offset;
324 struct GTY(()) machine_function {
325 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
326 rtx mips16_gp_pseudo_rtx;
328 /* The number of extra stack bytes taken up by register varargs.
329 This area is allocated by the callee at the very top of the frame. */
332 /* The current frame information, calculated by mips_compute_frame_info. */
333 struct mips_frame_info frame;
335 /* The register to use as the function's global pointer, or INVALID_REGNUM
336 if the function doesn't need one. */
337 unsigned int global_pointer;
339 /* How many instructions it takes to load a label into $AT, or 0 if
340 this property hasn't yet been calculated. */
341 unsigned int load_label_num_insns;
343 /* True if mips_adjust_insn_length should ignore an instruction's
345 bool ignore_hazard_length_p;
347 /* True if the whole function is suitable for .set noreorder and
349 bool all_noreorder_p;
351 /* True if the function has "inflexible" and "flexible" references
352 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
353 and mips_cfun_has_flexible_gp_ref_p for details. */
354 bool has_inflexible_gp_insn_p;
355 bool has_flexible_gp_insn_p;
357 /* True if the function's prologue must load the global pointer
358 value into pic_offset_table_rtx and store the same value in
359 the function's cprestore slot (if any). Even if this value
360 is currently false, we may decide to set it to true later;
361 see mips_must_initialize_gp_p () for details. */
362 bool must_initialize_gp_p;
364 /* True if the current function must restore $gp after any potential
365 clobber. This value is only meaningful during the first post-epilogue
366 split_insns pass; see mips_must_initialize_gp_p () for details. */
367 bool must_restore_gp_when_clobbered_p;
369 /* True if this is an interrupt handler. */
370 bool interrupt_handler_p;
372 /* True if this is an interrupt handler that uses shadow registers. */
373 bool use_shadow_register_set_p;
375 /* True if this is an interrupt handler that should keep interrupts
377 bool keep_interrupts_masked_p;
379 /* True if this is an interrupt handler that should use DERET
381 bool use_debug_exception_return_p;
384 /* Information about a single argument. */
385 struct mips_arg_info {
386 /* True if the argument is passed in a floating-point register, or
387 would have been if we hadn't run out of registers. */
390 /* The number of words passed in registers, rounded up. */
391 unsigned int reg_words;
393 /* For EABI, the offset of the first register from GP_ARG_FIRST or
394 FP_ARG_FIRST. For other ABIs, the offset of the first register from
395 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
396 comment for details).
398 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
400 unsigned int reg_offset;
402 /* The number of words that must be passed on the stack, rounded up. */
403 unsigned int stack_words;
405 /* The offset from the start of the stack overflow area of the argument's
406 first stack word. Only meaningful when STACK_WORDS is nonzero. */
407 unsigned int stack_offset;
410 /* Information about an address described by mips_address_type.
416 REG is the base register and OFFSET is the constant offset.
419 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
420 is the type of symbol it references.
423 SYMBOL_TYPE is the type of symbol that the address references. */
424 struct mips_address_info {
425 enum mips_address_type type;
428 enum mips_symbol_type symbol_type;
431 /* One stage in a constant building sequence. These sequences have
435 A = A CODE[1] VALUE[1]
436 A = A CODE[2] VALUE[2]
439 where A is an accumulator, each CODE[i] is a binary rtl operation
440 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
441 struct mips_integer_op {
443 unsigned HOST_WIDE_INT value;
446 /* The largest number of operations needed to load an integer constant.
447 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
448 When the lowest bit is clear, we can try, but reject a sequence with
449 an extra SLL at the end. */
450 #define MIPS_MAX_INTEGER_OPS 7
452 /* Information about a MIPS16e SAVE or RESTORE instruction. */
453 struct mips16e_save_restore_info {
454 /* The number of argument registers saved by a SAVE instruction.
455 0 for RESTORE instructions. */
458 /* Bit X is set if the instruction saves or restores GPR X. */
461 /* The total number of bytes to allocate. */
465 /* Costs of various operations on the different architectures. */
467 struct mips_rtx_cost_data
469 unsigned short fp_add;
470 unsigned short fp_mult_sf;
471 unsigned short fp_mult_df;
472 unsigned short fp_div_sf;
473 unsigned short fp_div_df;
474 unsigned short int_mult_si;
475 unsigned short int_mult_di;
476 unsigned short int_div_si;
477 unsigned short int_div_di;
478 unsigned short branch_cost;
479 unsigned short memory_latency;
482 /* Global variables for machine-dependent things. */
484 /* The -G setting, or the configuration's default small-data limit if
485 no -G option is given. */
486 static unsigned int mips_small_data_threshold;
488 /* The number of file directives written by mips_output_filename. */
489 int num_source_filenames;
491 /* The name that appeared in the last .file directive written by
492 mips_output_filename, or "" if mips_output_filename hasn't
493 written anything yet. */
494 const char *current_function_file = "";
496 /* Arrays that map GCC register numbers to debugger register numbers. */
497 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
498 int mips_dwarf_regno[FIRST_PSEUDO_REGISTER];
500 /* Information about the current function's epilogue, used only while
503 /* A list of queued REG_CFA_RESTORE notes. */
506 /* The CFA is currently defined as CFA_REG + CFA_OFFSET. */
508 HOST_WIDE_INT cfa_offset;
510 /* The offset of the CFA from the stack pointer while restoring
512 HOST_WIDE_INT cfa_restore_sp_offset;
515 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
516 struct mips_asm_switch mips_noreorder = { "reorder", 0 };
517 struct mips_asm_switch mips_nomacro = { "macro", 0 };
518 struct mips_asm_switch mips_noat = { "at", 0 };
520 /* True if we're writing out a branch-likely instruction rather than a
522 static bool mips_branch_likely;
524 /* The current instruction-set architecture. */
525 enum processor mips_arch;
526 const struct mips_cpu_info *mips_arch_info;
528 /* The processor that we should tune the code for. */
529 enum processor mips_tune;
530 const struct mips_cpu_info *mips_tune_info;
532 /* The ISA level associated with mips_arch. */
535 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
536 static const struct mips_cpu_info *mips_isa_option_info;
538 /* Which cost information to use. */
539 static const struct mips_rtx_cost_data *mips_cost;
541 /* The ambient target flags, excluding MASK_MIPS16. */
542 static int mips_base_target_flags;
544 /* True if MIPS16 is the default mode. */
545 bool mips_base_mips16;
547 /* The ambient values of other global variables. */
548 static int mips_base_schedule_insns; /* flag_schedule_insns */
549 static int mips_base_reorder_blocks_and_partition; /* flag_reorder... */
550 static int mips_base_move_loop_invariants; /* flag_move_loop_invariants */
551 static int mips_base_align_loops; /* align_loops */
552 static int mips_base_align_jumps; /* align_jumps */
553 static int mips_base_align_functions; /* align_functions */
555 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
556 bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
558 /* Index C is true if character C is a valid PRINT_OPERAND punctation
560 static bool mips_print_operand_punct[256];
562 static GTY (()) int mips_output_filename_first_time = 1;
564 /* mips_split_p[X] is true if symbols of type X can be split by
565 mips_split_symbol. */
566 bool mips_split_p[NUM_SYMBOL_TYPES];
568 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
569 can be split by mips_split_symbol. */
570 bool mips_split_hi_p[NUM_SYMBOL_TYPES];
572 /* mips_use_pcrel_pool_p[X] is true if symbols of type X should be
573 forced into a PC-relative constant pool. */
574 bool mips_use_pcrel_pool_p[NUM_SYMBOL_TYPES];
576 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
577 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
578 if they are matched by a special .md file pattern. */
579 const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
581 /* Likewise for HIGHs. */
582 const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
584 /* Target state for MIPS16. */
585 struct target_globals *mips16_globals;
587 /* Cached value of can_issue_more. This is cached in mips_variable_issue hook
588 and returned from mips_sched_reorder2. */
589 static int cached_can_issue_more;
591 /* True if the output uses __mips16_rdhwr. */
592 static bool mips_need_mips16_rdhwr_p;
594 /* Index R is the smallest register class that contains register R. */
595 const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = {
596 LEA_REGS, LEA_REGS, M16_REGS, V1_REG,
597 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
598 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
599 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
600 M16_REGS, M16_REGS, LEA_REGS, LEA_REGS,
601 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
602 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
603 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
604 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
605 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
606 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
607 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
608 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
609 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
610 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
611 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
612 MD0_REG, MD1_REG, NO_REGS, ST_REGS,
613 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
614 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
615 NO_REGS, FRAME_REGS, FRAME_REGS, NO_REGS,
616 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
617 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
618 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
619 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
620 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
621 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
622 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
623 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
624 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
625 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
626 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
627 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
628 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
629 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
630 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
631 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
632 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
633 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
634 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
635 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
636 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
637 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
638 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
639 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
640 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
641 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
642 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
645 /* The value of TARGET_ATTRIBUTE_TABLE. */
646 static const struct attribute_spec mips_attribute_table[] = {
647 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
649 { "long_call", 0, 0, false, true, true, NULL, false },
650 { "far", 0, 0, false, true, true, NULL, false },
651 { "near", 0, 0, false, true, true, NULL, false },
652 /* We would really like to treat "mips16" and "nomips16" as type
653 attributes, but GCC doesn't provide the hooks we need to support
654 the right conversion rules. As declaration attributes, they affect
655 code generation but don't carry other semantics. */
656 { "mips16", 0, 0, true, false, false, NULL, false },
657 { "nomips16", 0, 0, true, false, false, NULL, false },
658 /* Allow functions to be specified as interrupt handlers */
659 { "interrupt", 0, 0, false, true, true, NULL, false },
660 { "use_shadow_register_set", 0, 0, false, true, true, NULL, false },
661 { "keep_interrupts_masked", 0, 0, false, true, true, NULL, false },
662 { "use_debug_exception_return", 0, 0, false, true, true, NULL, false },
663 { NULL, 0, 0, false, false, false, NULL, false }
666 /* A table describing all the processors GCC knows about; see
667 mips-cpus.def for details. */
668 static const struct mips_cpu_info mips_cpu_info_table[] = {
669 #define MIPS_CPU(NAME, CPU, ISA, FLAGS) \
670 { NAME, CPU, ISA, FLAGS },
671 #include "mips-cpus.def"
675 /* Default costs. If these are used for a processor we should look
676 up the actual costs. */
677 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
678 COSTS_N_INSNS (7), /* fp_mult_sf */ \
679 COSTS_N_INSNS (8), /* fp_mult_df */ \
680 COSTS_N_INSNS (23), /* fp_div_sf */ \
681 COSTS_N_INSNS (36), /* fp_div_df */ \
682 COSTS_N_INSNS (10), /* int_mult_si */ \
683 COSTS_N_INSNS (10), /* int_mult_di */ \
684 COSTS_N_INSNS (69), /* int_div_si */ \
685 COSTS_N_INSNS (69), /* int_div_di */ \
686 2, /* branch_cost */ \
687 4 /* memory_latency */
689 /* Floating-point costs for processors without an FPU. Just assume that
690 all floating-point libcalls are very expensive. */
691 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
692 COSTS_N_INSNS (256), /* fp_mult_sf */ \
693 COSTS_N_INSNS (256), /* fp_mult_df */ \
694 COSTS_N_INSNS (256), /* fp_div_sf */ \
695 COSTS_N_INSNS (256) /* fp_div_df */
697 /* Costs to use when optimizing for size. */
698 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size = {
699 COSTS_N_INSNS (1), /* fp_add */
700 COSTS_N_INSNS (1), /* fp_mult_sf */
701 COSTS_N_INSNS (1), /* fp_mult_df */
702 COSTS_N_INSNS (1), /* fp_div_sf */
703 COSTS_N_INSNS (1), /* fp_div_df */
704 COSTS_N_INSNS (1), /* int_mult_si */
705 COSTS_N_INSNS (1), /* int_mult_di */
706 COSTS_N_INSNS (1), /* int_div_si */
707 COSTS_N_INSNS (1), /* int_div_di */
709 4 /* memory_latency */
712 /* Costs to use when optimizing for speed, indexed by processor. */
713 static const struct mips_rtx_cost_data
714 mips_rtx_cost_data[NUM_PROCESSOR_VALUES] = {
716 COSTS_N_INSNS (2), /* fp_add */
717 COSTS_N_INSNS (4), /* fp_mult_sf */
718 COSTS_N_INSNS (5), /* fp_mult_df */
719 COSTS_N_INSNS (12), /* fp_div_sf */
720 COSTS_N_INSNS (19), /* fp_div_df */
721 COSTS_N_INSNS (12), /* int_mult_si */
722 COSTS_N_INSNS (12), /* int_mult_di */
723 COSTS_N_INSNS (35), /* int_div_si */
724 COSTS_N_INSNS (35), /* int_div_di */
726 4 /* memory_latency */
730 COSTS_N_INSNS (6), /* int_mult_si */
731 COSTS_N_INSNS (6), /* int_mult_di */
732 COSTS_N_INSNS (36), /* int_div_si */
733 COSTS_N_INSNS (36), /* int_div_di */
735 4 /* memory_latency */
739 COSTS_N_INSNS (36), /* int_mult_si */
740 COSTS_N_INSNS (36), /* int_mult_di */
741 COSTS_N_INSNS (37), /* int_div_si */
742 COSTS_N_INSNS (37), /* int_div_di */
744 4 /* memory_latency */
748 COSTS_N_INSNS (4), /* int_mult_si */
749 COSTS_N_INSNS (11), /* int_mult_di */
750 COSTS_N_INSNS (36), /* int_div_si */
751 COSTS_N_INSNS (68), /* int_div_di */
753 4 /* memory_latency */
756 COSTS_N_INSNS (4), /* fp_add */
757 COSTS_N_INSNS (4), /* fp_mult_sf */
758 COSTS_N_INSNS (5), /* fp_mult_df */
759 COSTS_N_INSNS (17), /* fp_div_sf */
760 COSTS_N_INSNS (32), /* fp_div_df */
761 COSTS_N_INSNS (4), /* int_mult_si */
762 COSTS_N_INSNS (11), /* int_mult_di */
763 COSTS_N_INSNS (36), /* int_div_si */
764 COSTS_N_INSNS (68), /* int_div_di */
766 4 /* memory_latency */
769 COSTS_N_INSNS (4), /* fp_add */
770 COSTS_N_INSNS (4), /* fp_mult_sf */
771 COSTS_N_INSNS (5), /* fp_mult_df */
772 COSTS_N_INSNS (17), /* fp_div_sf */
773 COSTS_N_INSNS (32), /* fp_div_df */
774 COSTS_N_INSNS (4), /* int_mult_si */
775 COSTS_N_INSNS (7), /* int_mult_di */
776 COSTS_N_INSNS (42), /* int_div_si */
777 COSTS_N_INSNS (72), /* int_div_di */
779 4 /* memory_latency */
783 COSTS_N_INSNS (5), /* int_mult_si */
784 COSTS_N_INSNS (5), /* int_mult_di */
785 COSTS_N_INSNS (41), /* int_div_si */
786 COSTS_N_INSNS (41), /* int_div_di */
788 4 /* memory_latency */
791 COSTS_N_INSNS (8), /* fp_add */
792 COSTS_N_INSNS (8), /* fp_mult_sf */
793 COSTS_N_INSNS (10), /* fp_mult_df */
794 COSTS_N_INSNS (34), /* fp_div_sf */
795 COSTS_N_INSNS (64), /* fp_div_df */
796 COSTS_N_INSNS (5), /* int_mult_si */
797 COSTS_N_INSNS (5), /* int_mult_di */
798 COSTS_N_INSNS (41), /* int_div_si */
799 COSTS_N_INSNS (41), /* int_div_di */
801 4 /* memory_latency */
804 COSTS_N_INSNS (4), /* fp_add */
805 COSTS_N_INSNS (4), /* fp_mult_sf */
806 COSTS_N_INSNS (5), /* fp_mult_df */
807 COSTS_N_INSNS (17), /* fp_div_sf */
808 COSTS_N_INSNS (32), /* fp_div_df */
809 COSTS_N_INSNS (5), /* int_mult_si */
810 COSTS_N_INSNS (5), /* int_mult_di */
811 COSTS_N_INSNS (41), /* int_div_si */
812 COSTS_N_INSNS (41), /* int_div_di */
814 4 /* memory_latency */
818 COSTS_N_INSNS (5), /* int_mult_si */
819 COSTS_N_INSNS (5), /* int_mult_di */
820 COSTS_N_INSNS (41), /* int_div_si */
821 COSTS_N_INSNS (41), /* int_div_di */
823 4 /* memory_latency */
826 COSTS_N_INSNS (8), /* fp_add */
827 COSTS_N_INSNS (8), /* fp_mult_sf */
828 COSTS_N_INSNS (10), /* fp_mult_df */
829 COSTS_N_INSNS (34), /* fp_div_sf */
830 COSTS_N_INSNS (64), /* fp_div_df */
831 COSTS_N_INSNS (5), /* int_mult_si */
832 COSTS_N_INSNS (5), /* int_mult_di */
833 COSTS_N_INSNS (41), /* int_div_si */
834 COSTS_N_INSNS (41), /* int_div_di */
836 4 /* memory_latency */
839 COSTS_N_INSNS (4), /* fp_add */
840 COSTS_N_INSNS (4), /* fp_mult_sf */
841 COSTS_N_INSNS (5), /* fp_mult_df */
842 COSTS_N_INSNS (17), /* fp_div_sf */
843 COSTS_N_INSNS (32), /* fp_div_df */
844 COSTS_N_INSNS (5), /* int_mult_si */
845 COSTS_N_INSNS (5), /* int_mult_di */
846 COSTS_N_INSNS (41), /* int_div_si */
847 COSTS_N_INSNS (41), /* int_div_di */
849 4 /* memory_latency */
852 COSTS_N_INSNS (6), /* fp_add */
853 COSTS_N_INSNS (6), /* fp_mult_sf */
854 COSTS_N_INSNS (7), /* fp_mult_df */
855 COSTS_N_INSNS (25), /* fp_div_sf */
856 COSTS_N_INSNS (48), /* fp_div_df */
857 COSTS_N_INSNS (5), /* int_mult_si */
858 COSTS_N_INSNS (5), /* int_mult_di */
859 COSTS_N_INSNS (41), /* int_div_si */
860 COSTS_N_INSNS (41), /* int_div_di */
862 4 /* memory_latency */
879 COSTS_N_INSNS (5), /* int_mult_si */
880 COSTS_N_INSNS (5), /* int_mult_di */
881 COSTS_N_INSNS (72), /* int_div_si */
882 COSTS_N_INSNS (72), /* int_div_di */
884 4 /* memory_latency */
889 COSTS_N_INSNS (6), /* int_mult_si */
890 COSTS_N_INSNS (6), /* int_mult_di */
891 COSTS_N_INSNS (18), /* int_div_si */
892 COSTS_N_INSNS (35), /* int_div_di */
894 4 /* memory_latency */
897 COSTS_N_INSNS (2), /* fp_add */
898 COSTS_N_INSNS (4), /* fp_mult_sf */
899 COSTS_N_INSNS (5), /* fp_mult_df */
900 COSTS_N_INSNS (12), /* fp_div_sf */
901 COSTS_N_INSNS (19), /* fp_div_df */
902 COSTS_N_INSNS (2), /* int_mult_si */
903 COSTS_N_INSNS (2), /* int_mult_di */
904 COSTS_N_INSNS (35), /* int_div_si */
905 COSTS_N_INSNS (35), /* int_div_di */
907 4 /* memory_latency */
910 COSTS_N_INSNS (3), /* fp_add */
911 COSTS_N_INSNS (5), /* fp_mult_sf */
912 COSTS_N_INSNS (6), /* fp_mult_df */
913 COSTS_N_INSNS (15), /* fp_div_sf */
914 COSTS_N_INSNS (16), /* fp_div_df */
915 COSTS_N_INSNS (17), /* int_mult_si */
916 COSTS_N_INSNS (17), /* int_mult_di */
917 COSTS_N_INSNS (38), /* int_div_si */
918 COSTS_N_INSNS (38), /* int_div_di */
920 6 /* memory_latency */
923 COSTS_N_INSNS (6), /* fp_add */
924 COSTS_N_INSNS (7), /* fp_mult_sf */
925 COSTS_N_INSNS (8), /* fp_mult_df */
926 COSTS_N_INSNS (23), /* fp_div_sf */
927 COSTS_N_INSNS (36), /* fp_div_df */
928 COSTS_N_INSNS (10), /* int_mult_si */
929 COSTS_N_INSNS (10), /* int_mult_di */
930 COSTS_N_INSNS (69), /* int_div_si */
931 COSTS_N_INSNS (69), /* int_div_di */
933 6 /* memory_latency */
945 /* The only costs that appear to be updated here are
946 integer multiplication. */
948 COSTS_N_INSNS (4), /* int_mult_si */
949 COSTS_N_INSNS (6), /* int_mult_di */
950 COSTS_N_INSNS (69), /* int_div_si */
951 COSTS_N_INSNS (69), /* int_div_di */
953 4 /* memory_latency */
968 COSTS_N_INSNS (6), /* fp_add */
969 COSTS_N_INSNS (4), /* fp_mult_sf */
970 COSTS_N_INSNS (5), /* fp_mult_df */
971 COSTS_N_INSNS (23), /* fp_div_sf */
972 COSTS_N_INSNS (36), /* fp_div_df */
973 COSTS_N_INSNS (5), /* int_mult_si */
974 COSTS_N_INSNS (5), /* int_mult_di */
975 COSTS_N_INSNS (36), /* int_div_si */
976 COSTS_N_INSNS (36), /* int_div_di */
978 4 /* memory_latency */
981 COSTS_N_INSNS (6), /* fp_add */
982 COSTS_N_INSNS (5), /* fp_mult_sf */
983 COSTS_N_INSNS (6), /* fp_mult_df */
984 COSTS_N_INSNS (30), /* fp_div_sf */
985 COSTS_N_INSNS (59), /* fp_div_df */
986 COSTS_N_INSNS (3), /* int_mult_si */
987 COSTS_N_INSNS (4), /* int_mult_di */
988 COSTS_N_INSNS (42), /* int_div_si */
989 COSTS_N_INSNS (74), /* int_div_di */
991 4 /* memory_latency */
994 COSTS_N_INSNS (6), /* fp_add */
995 COSTS_N_INSNS (5), /* fp_mult_sf */
996 COSTS_N_INSNS (6), /* fp_mult_df */
997 COSTS_N_INSNS (30), /* fp_div_sf */
998 COSTS_N_INSNS (59), /* fp_div_df */
999 COSTS_N_INSNS (5), /* int_mult_si */
1000 COSTS_N_INSNS (9), /* int_mult_di */
1001 COSTS_N_INSNS (42), /* int_div_si */
1002 COSTS_N_INSNS (74), /* int_div_di */
1003 1, /* branch_cost */
1004 4 /* memory_latency */
1007 /* The only costs that are changed here are
1008 integer multiplication. */
1009 COSTS_N_INSNS (6), /* fp_add */
1010 COSTS_N_INSNS (7), /* fp_mult_sf */
1011 COSTS_N_INSNS (8), /* fp_mult_df */
1012 COSTS_N_INSNS (23), /* fp_div_sf */
1013 COSTS_N_INSNS (36), /* fp_div_df */
1014 COSTS_N_INSNS (5), /* int_mult_si */
1015 COSTS_N_INSNS (9), /* int_mult_di */
1016 COSTS_N_INSNS (69), /* int_div_si */
1017 COSTS_N_INSNS (69), /* int_div_di */
1018 1, /* branch_cost */
1019 4 /* memory_latency */
1025 /* The only costs that are changed here are
1026 integer multiplication. */
1027 COSTS_N_INSNS (6), /* fp_add */
1028 COSTS_N_INSNS (7), /* fp_mult_sf */
1029 COSTS_N_INSNS (8), /* fp_mult_df */
1030 COSTS_N_INSNS (23), /* fp_div_sf */
1031 COSTS_N_INSNS (36), /* fp_div_df */
1032 COSTS_N_INSNS (3), /* int_mult_si */
1033 COSTS_N_INSNS (8), /* int_mult_di */
1034 COSTS_N_INSNS (69), /* int_div_si */
1035 COSTS_N_INSNS (69), /* int_div_di */
1036 1, /* branch_cost */
1037 4 /* memory_latency */
1040 COSTS_N_INSNS (2), /* fp_add */
1041 COSTS_N_INSNS (2), /* fp_mult_sf */
1042 COSTS_N_INSNS (2), /* fp_mult_df */
1043 COSTS_N_INSNS (12), /* fp_div_sf */
1044 COSTS_N_INSNS (19), /* fp_div_df */
1045 COSTS_N_INSNS (5), /* int_mult_si */
1046 COSTS_N_INSNS (9), /* int_mult_di */
1047 COSTS_N_INSNS (34), /* int_div_si */
1048 COSTS_N_INSNS (66), /* int_div_di */
1049 1, /* branch_cost */
1050 4 /* memory_latency */
1053 /* These costs are the same as the SB-1A below. */
1054 COSTS_N_INSNS (4), /* fp_add */
1055 COSTS_N_INSNS (4), /* fp_mult_sf */
1056 COSTS_N_INSNS (4), /* fp_mult_df */
1057 COSTS_N_INSNS (24), /* fp_div_sf */
1058 COSTS_N_INSNS (32), /* fp_div_df */
1059 COSTS_N_INSNS (3), /* int_mult_si */
1060 COSTS_N_INSNS (4), /* int_mult_di */
1061 COSTS_N_INSNS (36), /* int_div_si */
1062 COSTS_N_INSNS (68), /* int_div_di */
1063 1, /* branch_cost */
1064 4 /* memory_latency */
1067 /* These costs are the same as the SB-1 above. */
1068 COSTS_N_INSNS (4), /* fp_add */
1069 COSTS_N_INSNS (4), /* fp_mult_sf */
1070 COSTS_N_INSNS (4), /* fp_mult_df */
1071 COSTS_N_INSNS (24), /* fp_div_sf */
1072 COSTS_N_INSNS (32), /* fp_div_df */
1073 COSTS_N_INSNS (3), /* int_mult_si */
1074 COSTS_N_INSNS (4), /* int_mult_di */
1075 COSTS_N_INSNS (36), /* int_div_si */
1076 COSTS_N_INSNS (68), /* int_div_di */
1077 1, /* branch_cost */
1078 4 /* memory_latency */
1085 COSTS_N_INSNS (8), /* int_mult_si */
1086 COSTS_N_INSNS (8), /* int_mult_di */
1087 COSTS_N_INSNS (72), /* int_div_si */
1088 COSTS_N_INSNS (72), /* int_div_di */
1089 1, /* branch_cost */
1090 4 /* memory_latency */
1093 /* These costs are the same as 5KF above. */
1094 COSTS_N_INSNS (4), /* fp_add */
1095 COSTS_N_INSNS (4), /* fp_mult_sf */
1096 COSTS_N_INSNS (5), /* fp_mult_df */
1097 COSTS_N_INSNS (17), /* fp_div_sf */
1098 COSTS_N_INSNS (32), /* fp_div_df */
1099 COSTS_N_INSNS (4), /* int_mult_si */
1100 COSTS_N_INSNS (11), /* int_mult_di */
1101 COSTS_N_INSNS (36), /* int_div_si */
1102 COSTS_N_INSNS (68), /* int_div_di */
1103 1, /* branch_cost */
1104 4 /* memory_latency */
1108 static rtx mips_find_pic_call_symbol (rtx, rtx, bool);
1109 static int mips_register_move_cost (enum machine_mode, reg_class_t,
1111 static unsigned int mips_function_arg_boundary (enum machine_mode, const_tree);
1113 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1114 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1115 struct GTY (()) mflip_mips16_entry {
1119 static GTY ((param_is (struct mflip_mips16_entry))) htab_t mflip_mips16_htab;
1121 /* Hash table callbacks for mflip_mips16_htab. */
1124 mflip_mips16_htab_hash (const void *entry)
1126 return htab_hash_string (((const struct mflip_mips16_entry *) entry)->name);
1130 mflip_mips16_htab_eq (const void *entry, const void *name)
1132 return strcmp (((const struct mflip_mips16_entry *) entry)->name,
1133 (const char *) name) == 0;
1136 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1137 mode, false if it should next add an attribute for the opposite mode. */
1138 static GTY(()) bool mips16_flipper;
1140 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1141 for -mflip-mips16. Return true if it should use "mips16" and false if
1142 it should use "nomips16". */
1145 mflip_mips16_use_mips16_p (tree decl)
1147 struct mflip_mips16_entry *entry;
1152 /* Use the opposite of the command-line setting for anonymous decls. */
1153 if (!DECL_NAME (decl))
1154 return !mips_base_mips16;
1156 if (!mflip_mips16_htab)
1157 mflip_mips16_htab = htab_create_ggc (37, mflip_mips16_htab_hash,
1158 mflip_mips16_htab_eq, NULL);
1160 name = IDENTIFIER_POINTER (DECL_NAME (decl));
1161 hash = htab_hash_string (name);
1162 slot = htab_find_slot_with_hash (mflip_mips16_htab, name, hash, INSERT);
1163 entry = (struct mflip_mips16_entry *) *slot;
1166 mips16_flipper = !mips16_flipper;
1167 entry = ggc_alloc_mflip_mips16_entry ();
1169 entry->mips16_p = mips16_flipper ? !mips_base_mips16 : mips_base_mips16;
1172 return entry->mips16_p;
1175 /* Predicates to test for presence of "near" and "far"/"long_call"
1176 attributes on the given TYPE. */
1179 mips_near_type_p (const_tree type)
1181 return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL;
1185 mips_far_type_p (const_tree type)
1187 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL
1188 || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL);
1191 /* Similar predicates for "mips16"/"nomips16" function attributes. */
1194 mips_mips16_decl_p (const_tree decl)
1196 return lookup_attribute ("mips16", DECL_ATTRIBUTES (decl)) != NULL;
1200 mips_nomips16_decl_p (const_tree decl)
1202 return lookup_attribute ("nomips16", DECL_ATTRIBUTES (decl)) != NULL;
1205 /* Check if the interrupt attribute is set for a function. */
1208 mips_interrupt_type_p (tree type)
1210 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type)) != NULL;
1213 /* Check if the attribute to use shadow register set is set for a function. */
1216 mips_use_shadow_register_set_p (tree type)
1218 return lookup_attribute ("use_shadow_register_set",
1219 TYPE_ATTRIBUTES (type)) != NULL;
1222 /* Check if the attribute to keep interrupts masked is set for a function. */
1225 mips_keep_interrupts_masked_p (tree type)
1227 return lookup_attribute ("keep_interrupts_masked",
1228 TYPE_ATTRIBUTES (type)) != NULL;
1231 /* Check if the attribute to use debug exception return is set for
1235 mips_use_debug_exception_return_p (tree type)
1237 return lookup_attribute ("use_debug_exception_return",
1238 TYPE_ATTRIBUTES (type)) != NULL;
1241 /* Return true if function DECL is a MIPS16 function. Return the ambient
1242 setting if DECL is null. */
1245 mips_use_mips16_mode_p (tree decl)
1249 /* Nested functions must use the same frame pointer as their
1250 parent and must therefore use the same ISA mode. */
1251 tree parent = decl_function_context (decl);
1254 if (mips_mips16_decl_p (decl))
1256 if (mips_nomips16_decl_p (decl))
1259 return mips_base_mips16;
1262 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1265 mips_comp_type_attributes (const_tree type1, const_tree type2)
1267 /* Disallow mixed near/far attributes. */
1268 if (mips_far_type_p (type1) && mips_near_type_p (type2))
1270 if (mips_near_type_p (type1) && mips_far_type_p (type2))
1275 /* Implement TARGET_INSERT_ATTRIBUTES. */
1278 mips_insert_attributes (tree decl, tree *attributes)
1281 bool mips16_p, nomips16_p;
1283 /* Check for "mips16" and "nomips16" attributes. */
1284 mips16_p = lookup_attribute ("mips16", *attributes) != NULL;
1285 nomips16_p = lookup_attribute ("nomips16", *attributes) != NULL;
1286 if (TREE_CODE (decl) != FUNCTION_DECL)
1289 error ("%qs attribute only applies to functions", "mips16");
1291 error ("%qs attribute only applies to functions", "nomips16");
1295 mips16_p |= mips_mips16_decl_p (decl);
1296 nomips16_p |= mips_nomips16_decl_p (decl);
1297 if (mips16_p || nomips16_p)
1299 /* DECL cannot be simultaneously "mips16" and "nomips16". */
1300 if (mips16_p && nomips16_p)
1301 error ("%qE cannot have both %<mips16%> and "
1302 "%<nomips16%> attributes",
1305 else if (TARGET_FLIP_MIPS16 && !DECL_ARTIFICIAL (decl))
1307 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1308 "mips16" attribute, arbitrarily pick one. We must pick the same
1309 setting for duplicate declarations of a function. */
1310 name = mflip_mips16_use_mips16_p (decl) ? "mips16" : "nomips16";
1311 *attributes = tree_cons (get_identifier (name), NULL, *attributes);
1316 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1319 mips_merge_decl_attributes (tree olddecl, tree newdecl)
1321 /* The decls' "mips16" and "nomips16" attributes must match exactly. */
1322 if (mips_mips16_decl_p (olddecl) != mips_mips16_decl_p (newdecl))
1323 error ("%qE redeclared with conflicting %qs attributes",
1324 DECL_NAME (newdecl), "mips16");
1325 if (mips_nomips16_decl_p (olddecl) != mips_nomips16_decl_p (newdecl))
1326 error ("%qE redeclared with conflicting %qs attributes",
1327 DECL_NAME (newdecl), "nomips16");
1329 return merge_attributes (DECL_ATTRIBUTES (olddecl),
1330 DECL_ATTRIBUTES (newdecl));
1333 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1334 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1337 mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr)
1339 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
1341 *base_ptr = XEXP (x, 0);
1342 *offset_ptr = INTVAL (XEXP (x, 1));
1351 static unsigned int mips_build_integer (struct mips_integer_op *,
1352 unsigned HOST_WIDE_INT);
1354 /* A subroutine of mips_build_integer, with the same interface.
1355 Assume that the final action in the sequence should be a left shift. */
1358 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1360 unsigned int i, shift;
1362 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1363 since signed numbers are easier to load than unsigned ones. */
1365 while ((value & 1) == 0)
1366 value /= 2, shift++;
1368 i = mips_build_integer (codes, value);
1369 codes[i].code = ASHIFT;
1370 codes[i].value = shift;
1374 /* As for mips_build_shift, but assume that the final action will be
1375 an IOR or PLUS operation. */
1378 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1380 unsigned HOST_WIDE_INT high;
1383 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1384 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
1386 /* The constant is too complex to load with a simple LUI/ORI pair,
1387 so we want to give the recursive call as many trailing zeros as
1388 possible. In this case, we know bit 16 is set and that the
1389 low 16 bits form a negative number. If we subtract that number
1390 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1391 i = mips_build_integer (codes, CONST_HIGH_PART (value));
1392 codes[i].code = PLUS;
1393 codes[i].value = CONST_LOW_PART (value);
1397 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1398 bits gives a value with at least 17 trailing zeros. */
1399 i = mips_build_integer (codes, high);
1400 codes[i].code = IOR;
1401 codes[i].value = value & 0xffff;
1406 /* Fill CODES with a sequence of rtl operations to load VALUE.
1407 Return the number of operations needed. */
1410 mips_build_integer (struct mips_integer_op *codes,
1411 unsigned HOST_WIDE_INT value)
1413 if (SMALL_OPERAND (value)
1414 || SMALL_OPERAND_UNSIGNED (value)
1415 || LUI_OPERAND (value))
1417 /* The value can be loaded with a single instruction. */
1418 codes[0].code = UNKNOWN;
1419 codes[0].value = value;
1422 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
1424 /* Either the constant is a simple LUI/ORI combination or its
1425 lowest bit is set. We don't want to shift in this case. */
1426 return mips_build_lower (codes, value);
1428 else if ((value & 0xffff) == 0)
1430 /* The constant will need at least three actions. The lowest
1431 16 bits are clear, so the final action will be a shift. */
1432 return mips_build_shift (codes, value);
1436 /* The final action could be a shift, add or inclusive OR.
1437 Rather than use a complex condition to select the best
1438 approach, try both mips_build_shift and mips_build_lower
1439 and pick the one that gives the shortest sequence.
1440 Note that this case is only used once per constant. */
1441 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1442 unsigned int cost, alt_cost;
1444 cost = mips_build_shift (codes, value);
1445 alt_cost = mips_build_lower (alt_codes, value);
1446 if (alt_cost < cost)
1448 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
1455 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
1458 mips_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
1460 return mips_const_insns (x) > 0;
1463 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
1466 mips16_stub_function (const char *name)
1470 x = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
1471 SYMBOL_REF_FLAGS (x) |= (SYMBOL_FLAG_EXTERNAL | SYMBOL_FLAG_FUNCTION);
1475 /* Return true if symbols of type TYPE require a GOT access. */
1478 mips_got_symbol_type_p (enum mips_symbol_type type)
1482 case SYMBOL_GOT_PAGE_OFST:
1483 case SYMBOL_GOT_DISP:
1491 /* Return true if X is a thread-local symbol. */
1494 mips_tls_symbol_p (rtx x)
1496 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1499 /* Return true if SYMBOL_REF X is associated with a global symbol
1500 (in the STB_GLOBAL sense). */
1503 mips_global_symbol_p (const_rtx x)
1505 const_tree decl = SYMBOL_REF_DECL (x);
1508 return !SYMBOL_REF_LOCAL_P (x) || SYMBOL_REF_EXTERNAL_P (x);
1510 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1511 or weak symbols. Relocations in the object file will be against
1512 the target symbol, so it's that symbol's binding that matters here. */
1513 return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl));
1516 /* Return true if function X is a libgcc MIPS16 stub function. */
1519 mips16_stub_function_p (const_rtx x)
1521 return (GET_CODE (x) == SYMBOL_REF
1522 && strncmp (XSTR (x, 0), "__mips16_", 9) == 0);
1525 /* Return true if function X is a locally-defined and locally-binding
1529 mips16_local_function_p (const_rtx x)
1531 return (GET_CODE (x) == SYMBOL_REF
1532 && SYMBOL_REF_LOCAL_P (x)
1533 && !SYMBOL_REF_EXTERNAL_P (x)
1534 && mips_use_mips16_mode_p (SYMBOL_REF_DECL (x)));
1537 /* Return true if SYMBOL_REF X binds locally. */
1540 mips_symbol_binds_local_p (const_rtx x)
1542 return (SYMBOL_REF_DECL (x)
1543 ? targetm.binds_local_p (SYMBOL_REF_DECL (x))
1544 : SYMBOL_REF_LOCAL_P (x));
1547 /* Return true if rtx constants of mode MODE should be put into a small
1551 mips_rtx_constant_in_small_data_p (enum machine_mode mode)
1553 return (!TARGET_EMBEDDED_DATA
1554 && TARGET_LOCAL_SDATA
1555 && GET_MODE_SIZE (mode) <= mips_small_data_threshold);
1558 /* Return true if X should not be moved directly into register $25.
1559 We need this because many versions of GAS will treat "la $25,foo" as
1560 part of a call sequence and so allow a global "foo" to be lazily bound. */
1563 mips_dangerous_for_la25_p (rtx x)
1565 return (!TARGET_EXPLICIT_RELOCS
1567 && GET_CODE (x) == SYMBOL_REF
1568 && mips_global_symbol_p (x));
1571 /* Return true if calls to X might need $25 to be valid on entry. */
1574 mips_use_pic_fn_addr_reg_p (const_rtx x)
1576 if (!TARGET_USE_PIC_FN_ADDR_REG)
1579 /* MIPS16 stub functions are guaranteed not to use $25. */
1580 if (mips16_stub_function_p (x))
1583 if (GET_CODE (x) == SYMBOL_REF)
1585 /* If PLTs and copy relocations are available, the static linker
1586 will make sure that $25 is valid on entry to the target function. */
1587 if (TARGET_ABICALLS_PIC0)
1590 /* Locally-defined functions use absolute accesses to set up
1591 the global pointer. */
1592 if (TARGET_ABSOLUTE_ABICALLS
1593 && mips_symbol_binds_local_p (x)
1594 && !SYMBOL_REF_EXTERNAL_P (x))
1601 /* Return the method that should be used to access SYMBOL_REF or
1602 LABEL_REF X in context CONTEXT. */
1604 static enum mips_symbol_type
1605 mips_classify_symbol (const_rtx x, enum mips_symbol_context context)
1608 return SYMBOL_GOT_DISP;
1610 if (GET_CODE (x) == LABEL_REF)
1612 /* Only return SYMBOL_PC_RELATIVE if we are generating MIPS16
1613 code and if we know that the label is in the current function's
1614 text section. LABEL_REFs are used for jump tables as well as
1615 text labels, so we must check whether jump tables live in the
1617 if (TARGET_MIPS16_SHORT_JUMP_TABLES
1618 && !LABEL_REF_NONLOCAL_P (x))
1619 return SYMBOL_PC_RELATIVE;
1621 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1622 return SYMBOL_GOT_PAGE_OFST;
1624 return SYMBOL_ABSOLUTE;
1627 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1629 if (SYMBOL_REF_TLS_MODEL (x))
1632 if (CONSTANT_POOL_ADDRESS_P (x))
1634 if (TARGET_MIPS16_TEXT_LOADS)
1635 return SYMBOL_PC_RELATIVE;
1637 if (TARGET_MIPS16_PCREL_LOADS && context == SYMBOL_CONTEXT_MEM)
1638 return SYMBOL_PC_RELATIVE;
1640 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x)))
1641 return SYMBOL_GP_RELATIVE;
1644 /* Do not use small-data accesses for weak symbols; they may end up
1646 if (TARGET_GPOPT && SYMBOL_REF_SMALL_P (x) && !SYMBOL_REF_WEAK (x))
1647 return SYMBOL_GP_RELATIVE;
1649 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1651 if (TARGET_ABICALLS_PIC2
1652 && !(TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x)))
1654 /* There are three cases to consider:
1656 - o32 PIC (either with or without explicit relocs)
1657 - n32/n64 PIC without explicit relocs
1658 - n32/n64 PIC with explicit relocs
1660 In the first case, both local and global accesses will use an
1661 R_MIPS_GOT16 relocation. We must correctly predict which of
1662 the two semantics (local or global) the assembler and linker
1663 will apply. The choice depends on the symbol's binding rather
1664 than its visibility.
1666 In the second case, the assembler will not use R_MIPS_GOT16
1667 relocations, but it chooses between local and global accesses
1668 in the same way as for o32 PIC.
1670 In the third case we have more freedom since both forms of
1671 access will work for any kind of symbol. However, there seems
1672 little point in doing things differently. */
1673 if (mips_global_symbol_p (x))
1674 return SYMBOL_GOT_DISP;
1676 return SYMBOL_GOT_PAGE_OFST;
1679 return SYMBOL_ABSOLUTE;
1682 /* Classify the base of symbolic expression X, given that X appears in
1685 static enum mips_symbol_type
1686 mips_classify_symbolic_expression (rtx x, enum mips_symbol_context context)
1690 split_const (x, &x, &offset);
1691 if (UNSPEC_ADDRESS_P (x))
1692 return UNSPEC_ADDRESS_TYPE (x);
1694 return mips_classify_symbol (x, context);
1697 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1698 is the alignment in bytes of SYMBOL_REF X. */
1701 mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset)
1703 HOST_WIDE_INT align;
1705 align = SYMBOL_REF_DECL (x) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x)) : 1;
1706 return IN_RANGE (offset, 0, align - 1);
1709 /* Return true if X is a symbolic constant that can be used in context
1710 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1713 mips_symbolic_constant_p (rtx x, enum mips_symbol_context context,
1714 enum mips_symbol_type *symbol_type)
1718 split_const (x, &x, &offset);
1719 if (UNSPEC_ADDRESS_P (x))
1721 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1722 x = UNSPEC_ADDRESS (x);
1724 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1726 *symbol_type = mips_classify_symbol (x, context);
1727 if (*symbol_type == SYMBOL_TLS)
1733 if (offset == const0_rtx)
1736 /* Check whether a nonzero offset is valid for the underlying
1738 switch (*symbol_type)
1740 case SYMBOL_ABSOLUTE:
1741 case SYMBOL_64_HIGH:
1744 /* If the target has 64-bit pointers and the object file only
1745 supports 32-bit symbols, the values of those symbols will be
1746 sign-extended. In this case we can't allow an arbitrary offset
1747 in case the 32-bit value X + OFFSET has a different sign from X. */
1748 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1749 return offset_within_block_p (x, INTVAL (offset));
1751 /* In other cases the relocations can handle any offset. */
1754 case SYMBOL_PC_RELATIVE:
1755 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1756 In this case, we no longer have access to the underlying constant,
1757 but the original symbol-based access was known to be valid. */
1758 if (GET_CODE (x) == LABEL_REF)
1763 case SYMBOL_GP_RELATIVE:
1764 /* Make sure that the offset refers to something within the
1765 same object block. This should guarantee that the final
1766 PC- or GP-relative offset is within the 16-bit limit. */
1767 return offset_within_block_p (x, INTVAL (offset));
1769 case SYMBOL_GOT_PAGE_OFST:
1770 case SYMBOL_GOTOFF_PAGE:
1771 /* If the symbol is global, the GOT entry will contain the symbol's
1772 address, and we will apply a 16-bit offset after loading it.
1773 If the symbol is local, the linker should provide enough local
1774 GOT entries for a 16-bit offset, but larger offsets may lead
1776 return SMALL_INT (offset);
1780 /* There is no carry between the HI and LO REL relocations, so the
1781 offset is only valid if we know it won't lead to such a carry. */
1782 return mips_offset_within_alignment_p (x, INTVAL (offset));
1784 case SYMBOL_GOT_DISP:
1785 case SYMBOL_GOTOFF_DISP:
1786 case SYMBOL_GOTOFF_CALL:
1787 case SYMBOL_GOTOFF_LOADGP:
1790 case SYMBOL_GOTTPREL:
1798 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
1799 single instruction. We rely on the fact that, in the worst case,
1800 all instructions involved in a MIPS16 address calculation are usually
1804 mips_symbol_insns_1 (enum mips_symbol_type type, enum machine_mode mode)
1806 if (mips_use_pcrel_pool_p[(int) type])
1808 if (mode == MAX_MACHINE_MODE)
1809 /* LEAs will be converted into constant-pool references by
1811 type = SYMBOL_PC_RELATIVE;
1813 /* The constant must be loaded and then dereferenced. */
1819 case SYMBOL_ABSOLUTE:
1820 /* When using 64-bit symbols, we need 5 preparatory instructions,
1823 lui $at,%highest(symbol)
1824 daddiu $at,$at,%higher(symbol)
1826 daddiu $at,$at,%hi(symbol)
1829 The final address is then $at + %lo(symbol). With 32-bit
1830 symbols we just need a preparatory LUI for normal mode and
1831 a preparatory LI and SLL for MIPS16. */
1832 return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2;
1834 case SYMBOL_GP_RELATIVE:
1835 /* Treat GP-relative accesses as taking a single instruction on
1836 MIPS16 too; the copy of $gp can often be shared. */
1839 case SYMBOL_PC_RELATIVE:
1840 /* PC-relative constants can be only be used with ADDIUPC,
1841 DADDIUPC, LWPC and LDPC. */
1842 if (mode == MAX_MACHINE_MODE
1843 || GET_MODE_SIZE (mode) == 4
1844 || GET_MODE_SIZE (mode) == 8)
1847 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
1850 case SYMBOL_GOT_DISP:
1851 /* The constant will have to be loaded from the GOT before it
1852 is used in an address. */
1853 if (mode != MAX_MACHINE_MODE)
1858 case SYMBOL_GOT_PAGE_OFST:
1859 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
1860 local/global classification is accurate. The worst cases are:
1862 (1) For local symbols when generating o32 or o64 code. The assembler
1868 ...and the final address will be $at + %lo(symbol).
1870 (2) For global symbols when -mxgot. The assembler will use:
1872 lui $at,%got_hi(symbol)
1875 ...and the final address will be $at + %got_lo(symbol). */
1878 case SYMBOL_GOTOFF_PAGE:
1879 case SYMBOL_GOTOFF_DISP:
1880 case SYMBOL_GOTOFF_CALL:
1881 case SYMBOL_GOTOFF_LOADGP:
1882 case SYMBOL_64_HIGH:
1888 case SYMBOL_GOTTPREL:
1891 /* A 16-bit constant formed by a single relocation, or a 32-bit
1892 constant formed from a high 16-bit relocation and a low 16-bit
1893 relocation. Use mips_split_p to determine which. 32-bit
1894 constants need an "lui; addiu" sequence for normal mode and
1895 an "li; sll; addiu" sequence for MIPS16 mode. */
1896 return !mips_split_p[type] ? 1 : TARGET_MIPS16 ? 3 : 2;
1899 /* We don't treat a bare TLS symbol as a constant. */
1905 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
1906 to load symbols of type TYPE into a register. Return 0 if the given
1907 type of symbol cannot be used as an immediate operand.
1909 Otherwise, return the number of instructions needed to load or store
1910 values of mode MODE to or from addresses of type TYPE. Return 0 if
1911 the given type of symbol is not valid in addresses.
1913 In both cases, treat extended MIPS16 instructions as two instructions. */
1916 mips_symbol_insns (enum mips_symbol_type type, enum machine_mode mode)
1918 return mips_symbol_insns_1 (type, mode) * (TARGET_MIPS16 ? 2 : 1);
1921 /* A for_each_rtx callback. Stop the search if *X references a
1922 thread-local symbol. */
1925 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1927 return mips_tls_symbol_p (*x);
1930 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1933 mips_cannot_force_const_mem (enum machine_mode mode, rtx x)
1935 enum mips_symbol_type type;
1938 /* There is no assembler syntax for expressing an address-sized
1940 if (GET_CODE (x) == HIGH)
1943 /* As an optimization, reject constants that mips_legitimize_move
1946 Suppose we have a multi-instruction sequence that loads constant C
1947 into register R. If R does not get allocated a hard register, and
1948 R is used in an operand that allows both registers and memory
1949 references, reload will consider forcing C into memory and using
1950 one of the instruction's memory alternatives. Returning false
1951 here will force it to use an input reload instead. */
1952 if (CONST_INT_P (x) && mips_legitimate_constant_p (mode, x))
1955 split_const (x, &base, &offset);
1956 if (mips_symbolic_constant_p (base, SYMBOL_CONTEXT_LEA, &type))
1958 /* See whether we explicitly want these symbols in the pool. */
1959 if (mips_use_pcrel_pool_p[(int) type])
1962 /* The same optimization as for CONST_INT. */
1963 if (SMALL_INT (offset) && mips_symbol_insns (type, MAX_MACHINE_MODE) > 0)
1966 /* If MIPS16 constant pools live in the text section, they should
1967 not refer to anything that might need run-time relocation. */
1968 if (TARGET_MIPS16_PCREL_LOADS && mips_got_symbol_type_p (type))
1972 /* TLS symbols must be computed by mips_legitimize_move. */
1973 if (for_each_rtx (&x, &mips_tls_symbol_ref_1, NULL))
1979 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
1980 constants when we're using a per-function constant pool. */
1983 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
1984 const_rtx x ATTRIBUTE_UNUSED)
1986 return !TARGET_MIPS16_PCREL_LOADS;
1989 /* Return true if register REGNO is a valid base register for mode MODE.
1990 STRICT_P is true if REG_OK_STRICT is in effect. */
1993 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode,
1996 if (!HARD_REGISTER_NUM_P (regno))
2000 regno = reg_renumber[regno];
2003 /* These fake registers will be eliminated to either the stack or
2004 hard frame pointer, both of which are usually valid base registers.
2005 Reload deals with the cases where the eliminated form isn't valid. */
2006 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
2009 /* In MIPS16 mode, the stack pointer can only address word and doubleword
2010 values, nothing smaller. There are two problems here:
2012 (a) Instantiating virtual registers can introduce new uses of the
2013 stack pointer. If these virtual registers are valid addresses,
2014 the stack pointer should be too.
2016 (b) Most uses of the stack pointer are not made explicit until
2017 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
2018 We don't know until that stage whether we'll be eliminating to the
2019 stack pointer (which needs the restriction) or the hard frame
2020 pointer (which doesn't).
2022 All in all, it seems more consistent to only enforce this restriction
2023 during and after reload. */
2024 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
2025 return !strict_p || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
2027 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
2030 /* Return true if X is a valid base register for mode MODE.
2031 STRICT_P is true if REG_OK_STRICT is in effect. */
2034 mips_valid_base_register_p (rtx x, enum machine_mode mode, bool strict_p)
2036 if (!strict_p && GET_CODE (x) == SUBREG)
2040 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p));
2043 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2044 can address a value of mode MODE. */
2047 mips_valid_offset_p (rtx x, enum machine_mode mode)
2049 /* Check that X is a signed 16-bit number. */
2050 if (!const_arith_operand (x, Pmode))
2053 /* We may need to split multiword moves, so make sure that every word
2055 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2056 && !SMALL_OPERAND (INTVAL (x) + GET_MODE_SIZE (mode) - UNITS_PER_WORD))
2062 /* Return true if a LO_SUM can address a value of mode MODE when the
2063 LO_SUM symbol has type SYMBOL_TYPE. */
2066 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type, enum machine_mode mode)
2068 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2070 if (mips_symbol_insns (symbol_type, mode) == 0)
2073 /* Check that there is a known low-part relocation. */
2074 if (mips_lo_relocs[symbol_type] == NULL)
2077 /* We may need to split multiword moves, so make sure that each word
2078 can be accessed without inducing a carry. This is mainly needed
2079 for o64, which has historically only guaranteed 64-bit alignment
2080 for 128-bit types. */
2081 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2082 && GET_MODE_BITSIZE (mode) > GET_MODE_ALIGNMENT (mode))
2088 /* Return true if X is a valid address for machine mode MODE. If it is,
2089 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2093 mips_classify_address (struct mips_address_info *info, rtx x,
2094 enum machine_mode mode, bool strict_p)
2096 switch (GET_CODE (x))
2100 info->type = ADDRESS_REG;
2102 info->offset = const0_rtx;
2103 return mips_valid_base_register_p (info->reg, mode, strict_p);
2106 info->type = ADDRESS_REG;
2107 info->reg = XEXP (x, 0);
2108 info->offset = XEXP (x, 1);
2109 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2110 && mips_valid_offset_p (info->offset, mode));
2113 info->type = ADDRESS_LO_SUM;
2114 info->reg = XEXP (x, 0);
2115 info->offset = XEXP (x, 1);
2116 /* We have to trust the creator of the LO_SUM to do something vaguely
2117 sane. Target-independent code that creates a LO_SUM should also
2118 create and verify the matching HIGH. Target-independent code that
2119 adds an offset to a LO_SUM must prove that the offset will not
2120 induce a carry. Failure to do either of these things would be
2121 a bug, and we are not required to check for it here. The MIPS
2122 backend itself should only create LO_SUMs for valid symbolic
2123 constants, with the high part being either a HIGH or a copy
2126 = mips_classify_symbolic_expression (info->offset, SYMBOL_CONTEXT_MEM);
2127 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2128 && mips_valid_lo_sum_p (info->symbol_type, mode));
2131 /* Small-integer addresses don't occur very often, but they
2132 are legitimate if $0 is a valid base register. */
2133 info->type = ADDRESS_CONST_INT;
2134 return !TARGET_MIPS16 && SMALL_INT (x);
2139 info->type = ADDRESS_SYMBOLIC;
2140 return (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_MEM,
2142 && mips_symbol_insns (info->symbol_type, mode) > 0
2143 && !mips_split_p[info->symbol_type]);
2150 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2153 mips_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
2155 struct mips_address_info addr;
2157 return mips_classify_address (&addr, x, mode, strict_p);
2160 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
2163 mips_stack_address_p (rtx x, enum machine_mode mode)
2165 struct mips_address_info addr;
2167 return (mips_classify_address (&addr, x, mode, false)
2168 && addr.type == ADDRESS_REG
2169 && addr.reg == stack_pointer_rtx);
2172 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2173 address instruction. Note that such addresses are not considered
2174 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2175 is so restricted. */
2178 mips_lwxs_address_p (rtx addr)
2181 && GET_CODE (addr) == PLUS
2182 && REG_P (XEXP (addr, 1)))
2184 rtx offset = XEXP (addr, 0);
2185 if (GET_CODE (offset) == MULT
2186 && REG_P (XEXP (offset, 0))
2187 && CONST_INT_P (XEXP (offset, 1))
2188 && INTVAL (XEXP (offset, 1)) == 4)
2194 /* Return true if ADDR matches the pattern for the L{B,H,W,D}{,U}X load
2195 indexed address instruction. Note that such addresses are
2196 not considered legitimate in the TARGET_LEGITIMATE_ADDRESS_P
2197 sense, because their use is so restricted. */
2200 mips_lx_address_p (rtx addr, enum machine_mode mode)
2202 if (GET_CODE (addr) != PLUS
2203 || !REG_P (XEXP (addr, 0))
2204 || !REG_P (XEXP (addr, 1)))
2206 if (ISA_HAS_LBX && mode == QImode)
2208 if (ISA_HAS_LHX && mode == HImode)
2210 if (ISA_HAS_LWX && mode == SImode)
2212 if (ISA_HAS_LDX && mode == DImode)
2217 /* Return true if a value at OFFSET bytes from base register BASE can be
2218 accessed using an unextended MIPS16 instruction. MODE is the mode of
2221 Usually the offset in an unextended instruction is a 5-bit field.
2222 The offset is unsigned and shifted left once for LH and SH, twice
2223 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2224 an 8-bit immediate field that's shifted left twice. */
2227 mips16_unextended_reference_p (enum machine_mode mode, rtx base,
2228 unsigned HOST_WIDE_INT offset)
2230 if (mode != BLKmode && offset % GET_MODE_SIZE (mode) == 0)
2232 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
2233 return offset < 256U * GET_MODE_SIZE (mode);
2234 return offset < 32U * GET_MODE_SIZE (mode);
2239 /* Return the number of instructions needed to load or store a value
2240 of mode MODE at address X. Return 0 if X isn't valid for MODE.
2241 Assume that multiword moves may need to be split into word moves
2242 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2245 For MIPS16 code, count extended instructions as two instructions. */
2248 mips_address_insns (rtx x, enum machine_mode mode, bool might_split_p)
2250 struct mips_address_info addr;
2253 /* BLKmode is used for single unaligned loads and stores and should
2254 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2255 meaningless, so we have to single it out as a special case one way
2257 if (mode != BLKmode && might_split_p)
2258 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2262 if (mips_classify_address (&addr, x, mode, false))
2267 && !mips16_unextended_reference_p (mode, addr.reg,
2268 UINTVAL (addr.offset)))
2272 case ADDRESS_LO_SUM:
2273 return TARGET_MIPS16 ? factor * 2 : factor;
2275 case ADDRESS_CONST_INT:
2278 case ADDRESS_SYMBOLIC:
2279 return factor * mips_symbol_insns (addr.symbol_type, mode);
2284 /* Return the number of instructions needed to load constant X.
2285 Return 0 if X isn't a valid constant. */
2288 mips_const_insns (rtx x)
2290 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2291 enum mips_symbol_type symbol_type;
2294 switch (GET_CODE (x))
2297 if (!mips_symbolic_constant_p (XEXP (x, 0), SYMBOL_CONTEXT_LEA,
2299 || !mips_split_p[symbol_type])
2302 /* This is simply an LUI for normal mode. It is an extended
2303 LI followed by an extended SLL for MIPS16. */
2304 return TARGET_MIPS16 ? 4 : 1;
2308 /* Unsigned 8-bit constants can be loaded using an unextended
2309 LI instruction. Unsigned 16-bit constants can be loaded
2310 using an extended LI. Negative constants must be loaded
2311 using LI and then negated. */
2312 return (IN_RANGE (INTVAL (x), 0, 255) ? 1
2313 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
2314 : IN_RANGE (-INTVAL (x), 0, 255) ? 2
2315 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
2318 return mips_build_integer (codes, INTVAL (x));
2322 /* Allow zeros for normal mode, where we can use $0. */
2323 return !TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0;
2329 /* See if we can refer to X directly. */
2330 if (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_LEA, &symbol_type))
2331 return mips_symbol_insns (symbol_type, MAX_MACHINE_MODE);
2333 /* Otherwise try splitting the constant into a base and offset.
2334 If the offset is a 16-bit value, we can load the base address
2335 into a register and then use (D)ADDIU to add in the offset.
2336 If the offset is larger, we can load the base and offset
2337 into separate registers and add them together with (D)ADDU.
2338 However, the latter is only possible before reload; during
2339 and after reload, we must have the option of forcing the
2340 constant into the pool instead. */
2341 split_const (x, &x, &offset);
2344 int n = mips_const_insns (x);
2347 if (SMALL_INT (offset))
2349 else if (!targetm.cannot_force_const_mem (GET_MODE (x), x))
2350 return n + 1 + mips_build_integer (codes, INTVAL (offset));
2357 return mips_symbol_insns (mips_classify_symbol (x, SYMBOL_CONTEXT_LEA),
2365 /* X is a doubleword constant that can be handled by splitting it into
2366 two words and loading each word separately. Return the number of
2367 instructions required to do this. */
2370 mips_split_const_insns (rtx x)
2372 unsigned int low, high;
2374 low = mips_const_insns (mips_subword (x, false));
2375 high = mips_const_insns (mips_subword (x, true));
2376 gcc_assert (low > 0 && high > 0);
2380 /* Return the number of instructions needed to implement INSN,
2381 given that it loads from or stores to MEM. Count extended
2382 MIPS16 instructions as two instructions. */
2385 mips_load_store_insns (rtx mem, rtx insn)
2387 enum machine_mode mode;
2391 gcc_assert (MEM_P (mem));
2392 mode = GET_MODE (mem);
2394 /* Try to prove that INSN does not need to be split. */
2395 might_split_p = true;
2396 if (GET_MODE_BITSIZE (mode) == 64)
2398 set = single_set (insn);
2399 if (set && !mips_split_64bit_move_p (SET_DEST (set), SET_SRC (set)))
2400 might_split_p = false;
2403 return mips_address_insns (XEXP (mem, 0), mode, might_split_p);
2406 /* Return the number of instructions needed for an integer division. */
2409 mips_idiv_insns (void)
2414 if (TARGET_CHECK_ZERO_DIV)
2416 if (GENERATE_DIVIDE_TRAPS)
2422 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
2427 /* Emit a move from SRC to DEST. Assume that the move expanders can
2428 handle all moves if !can_create_pseudo_p (). The distinction is
2429 important because, unlike emit_move_insn, the move expanders know
2430 how to force Pmode objects into the constant pool even when the
2431 constant pool address is not itself legitimate. */
2434 mips_emit_move (rtx dest, rtx src)
2436 return (can_create_pseudo_p ()
2437 ? emit_move_insn (dest, src)
2438 : emit_move_insn_1 (dest, src));
2441 /* Emit an instruction of the form (set TARGET (CODE OP0)). */
2444 mips_emit_unary (enum rtx_code code, rtx target, rtx op0)
2446 emit_insn (gen_rtx_SET (VOIDmode, target,
2447 gen_rtx_fmt_e (code, GET_MODE (op0), op0)));
2450 /* Compute (CODE OP0) and store the result in a new register of mode MODE.
2451 Return that new register. */
2454 mips_force_unary (enum machine_mode mode, enum rtx_code code, rtx op0)
2458 reg = gen_reg_rtx (mode);
2459 mips_emit_unary (code, reg, op0);
2463 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2466 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
2468 emit_insn (gen_rtx_SET (VOIDmode, target,
2469 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
2472 /* Compute (CODE OP0 OP1) and store the result in a new register
2473 of mode MODE. Return that new register. */
2476 mips_force_binary (enum machine_mode mode, enum rtx_code code, rtx op0, rtx op1)
2480 reg = gen_reg_rtx (mode);
2481 mips_emit_binary (code, reg, op0, op1);
2485 /* Copy VALUE to a register and return that register. If new pseudos
2486 are allowed, copy it into a new register, otherwise use DEST. */
2489 mips_force_temporary (rtx dest, rtx value)
2491 if (can_create_pseudo_p ())
2492 return force_reg (Pmode, value);
2495 mips_emit_move (dest, value);
2500 /* Emit a call sequence with call pattern PATTERN and return the call
2501 instruction itself (which is not necessarily the last instruction
2502 emitted). ORIG_ADDR is the original, unlegitimized address,
2503 ADDR is the legitimized form, and LAZY_P is true if the call
2504 address is lazily-bound. */
2507 mips_emit_call_insn (rtx pattern, rtx orig_addr, rtx addr, bool lazy_p)
2511 insn = emit_call_insn (pattern);
2513 if (TARGET_MIPS16 && mips_use_pic_fn_addr_reg_p (orig_addr))
2515 /* MIPS16 JALRs only take MIPS16 registers. If the target
2516 function requires $25 to be valid on entry, we must copy it
2517 there separately. The move instruction can be put in the
2518 call's delay slot. */
2519 reg = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
2520 emit_insn_before (gen_move_insn (reg, addr), insn);
2521 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
2525 /* Lazy-binding stubs require $gp to be valid on entry. */
2526 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
2530 /* See the comment above load_call<mode> for details. */
2531 use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
2532 gen_rtx_REG (Pmode, GOT_VERSION_REGNUM));
2533 emit_insn (gen_update_got_version ());
2538 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2539 then add CONST_INT OFFSET to the result. */
2542 mips_unspec_address_offset (rtx base, rtx offset,
2543 enum mips_symbol_type symbol_type)
2545 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
2546 UNSPEC_ADDRESS_FIRST + symbol_type);
2547 if (offset != const0_rtx)
2548 base = gen_rtx_PLUS (Pmode, base, offset);
2549 return gen_rtx_CONST (Pmode, base);
2552 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2553 type SYMBOL_TYPE. */
2556 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
2560 split_const (address, &base, &offset);
2561 return mips_unspec_address_offset (base, offset, symbol_type);
2564 /* If OP is an UNSPEC address, return the address to which it refers,
2565 otherwise return OP itself. */
2568 mips_strip_unspec_address (rtx op)
2572 split_const (op, &base, &offset);
2573 if (UNSPEC_ADDRESS_P (base))
2574 op = plus_constant (Pmode, UNSPEC_ADDRESS (base), INTVAL (offset));
2578 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2579 high part to BASE and return the result. Just return BASE otherwise.
2580 TEMP is as for mips_force_temporary.
2582 The returned expression can be used as the first operand to a LO_SUM. */
2585 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
2586 enum mips_symbol_type symbol_type)
2588 if (mips_split_p[symbol_type])
2590 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
2591 addr = mips_force_temporary (temp, addr);
2592 base = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
2597 /* Return an instruction that copies $gp into register REG. We want
2598 GCC to treat the register's value as constant, so that its value
2599 can be rematerialized on demand. */
2602 gen_load_const_gp (rtx reg)
2604 return PMODE_INSN (gen_load_const_gp, (reg));
2607 /* Return a pseudo register that contains the value of $gp throughout
2608 the current function. Such registers are needed by MIPS16 functions,
2609 for which $gp itself is not a valid base register or addition operand. */
2612 mips16_gp_pseudo_reg (void)
2614 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
2618 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
2620 push_topmost_sequence ();
2622 scan = get_insns ();
2623 while (NEXT_INSN (scan) && !INSN_P (NEXT_INSN (scan)))
2624 scan = NEXT_INSN (scan);
2626 insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
2627 insn = emit_insn_after (insn, scan);
2628 INSN_LOCATOR (insn) = 0;
2630 pop_topmost_sequence ();
2633 return cfun->machine->mips16_gp_pseudo_rtx;
2636 /* Return a base register that holds pic_offset_table_rtx.
2637 TEMP, if nonnull, is a scratch Pmode base register. */
2640 mips_pic_base_register (rtx temp)
2643 return pic_offset_table_rtx;
2645 if (currently_expanding_to_rtl)
2646 return mips16_gp_pseudo_reg ();
2648 if (can_create_pseudo_p ())
2649 temp = gen_reg_rtx (Pmode);
2652 /* The first post-reload split exposes all references to $gp
2653 (both uses and definitions). All references must remain
2654 explicit after that point.
2656 It is safe to introduce uses of $gp at any time, so for
2657 simplicity, we do that before the split too. */
2658 mips_emit_move (temp, pic_offset_table_rtx);
2660 emit_insn (gen_load_const_gp (temp));
2664 /* Return the RHS of a load_call<mode> insn. */
2667 mips_unspec_call (rtx reg, rtx symbol)
2671 vec = gen_rtvec (3, reg, symbol, gen_rtx_REG (SImode, GOT_VERSION_REGNUM));
2672 return gen_rtx_UNSPEC (Pmode, vec, UNSPEC_LOAD_CALL);
2675 /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol
2676 reference. Return NULL_RTX otherwise. */
2679 mips_strip_unspec_call (rtx src)
2681 if (GET_CODE (src) == UNSPEC && XINT (src, 1) == UNSPEC_LOAD_CALL)
2682 return mips_strip_unspec_address (XVECEXP (src, 0, 1));
2686 /* Create and return a GOT reference of type TYPE for address ADDR.
2687 TEMP, if nonnull, is a scratch Pmode base register. */
2690 mips_got_load (rtx temp, rtx addr, enum mips_symbol_type type)
2692 rtx base, high, lo_sum_symbol;
2694 base = mips_pic_base_register (temp);
2696 /* If we used the temporary register to load $gp, we can't use
2697 it for the high part as well. */
2698 if (temp != NULL && reg_overlap_mentioned_p (base, temp))
2701 high = mips_unspec_offset_high (temp, base, addr, type);
2702 lo_sum_symbol = mips_unspec_address (addr, type);
2704 if (type == SYMBOL_GOTOFF_CALL)
2705 return mips_unspec_call (high, lo_sum_symbol);
2707 return PMODE_INSN (gen_unspec_got, (high, lo_sum_symbol));
2710 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2711 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2712 constant in that context and can be split into high and low parts.
2713 If so, and if LOW_OUT is nonnull, emit the high part and store the
2714 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
2716 TEMP is as for mips_force_temporary and is used to load the high
2717 part into a register.
2719 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
2720 a legitimize SET_SRC for an .md pattern, otherwise the low part
2721 is guaranteed to be a legitimate address for mode MODE. */
2724 mips_split_symbol (rtx temp, rtx addr, enum machine_mode mode, rtx *low_out)
2726 enum mips_symbol_context context;
2727 enum mips_symbol_type symbol_type;
2730 context = (mode == MAX_MACHINE_MODE
2731 ? SYMBOL_CONTEXT_LEA
2732 : SYMBOL_CONTEXT_MEM);
2733 if (GET_CODE (addr) == HIGH && context == SYMBOL_CONTEXT_LEA)
2735 addr = XEXP (addr, 0);
2736 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2737 && mips_symbol_insns (symbol_type, mode) > 0
2738 && mips_split_hi_p[symbol_type])
2741 switch (symbol_type)
2743 case SYMBOL_GOT_PAGE_OFST:
2744 /* The high part of a page/ofst pair is loaded from the GOT. */
2745 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_PAGE);
2756 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2757 && mips_symbol_insns (symbol_type, mode) > 0
2758 && mips_split_p[symbol_type])
2761 switch (symbol_type)
2763 case SYMBOL_GOT_DISP:
2764 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
2765 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_DISP);
2768 case SYMBOL_GP_RELATIVE:
2769 high = mips_pic_base_register (temp);
2770 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2774 high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
2775 high = mips_force_temporary (temp, high);
2776 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2785 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2786 mips_force_temporary; it is only needed when OFFSET is not a
2790 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
2792 if (!SMALL_OPERAND (offset))
2798 /* Load the full offset into a register so that we can use
2799 an unextended instruction for the address itself. */
2800 high = GEN_INT (offset);
2805 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
2806 The addition inside the macro CONST_HIGH_PART may cause an
2807 overflow, so we need to force a sign-extension check. */
2808 high = gen_int_mode (CONST_HIGH_PART (offset), Pmode);
2809 offset = CONST_LOW_PART (offset);
2811 high = mips_force_temporary (temp, high);
2812 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
2814 return plus_constant (Pmode, reg, offset);
2817 /* The __tls_get_attr symbol. */
2818 static GTY(()) rtx mips_tls_symbol;
2820 /* Return an instruction sequence that calls __tls_get_addr. SYM is
2821 the TLS symbol we are referencing and TYPE is the symbol type to use
2822 (either global dynamic or local dynamic). V0 is an RTX for the
2823 return value location. */
2826 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
2830 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
2832 if (!mips_tls_symbol)
2833 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
2835 loc = mips_unspec_address (sym, type);
2839 emit_insn (gen_rtx_SET (Pmode, a0,
2840 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
2841 insn = mips_expand_call (MIPS_CALL_NORMAL, v0, mips_tls_symbol,
2842 const0_rtx, NULL_RTX, false);
2843 RTL_CONST_CALL_P (insn) = 1;
2844 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
2845 insn = get_insns ();
2852 /* Return a pseudo register that contains the current thread pointer. */
2859 tp = gen_reg_rtx (Pmode);
2862 mips_need_mips16_rdhwr_p = true;
2863 fn = mips16_stub_function ("__mips16_rdhwr");
2864 SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_LOCAL;
2865 if (!call_insn_operand (fn, VOIDmode))
2866 fn = force_reg (Pmode, fn);
2867 emit_insn (PMODE_INSN (gen_tls_get_tp_mips16, (tp, fn)));
2870 emit_insn (PMODE_INSN (gen_tls_get_tp, (tp)));
2874 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
2875 its address. The return value will be both a valid address and a valid
2876 SET_SRC (either a REG or a LO_SUM). */
2879 mips_legitimize_tls_address (rtx loc)
2881 rtx dest, insn, v0, tp, tmp1, tmp2, eqv, offset;
2882 enum tls_model model;
2884 model = SYMBOL_REF_TLS_MODEL (loc);
2885 /* Only TARGET_ABICALLS code can have more than one module; other
2886 code must be be static and should not use a GOT. All TLS models
2887 reduce to local exec in this situation. */
2888 if (!TARGET_ABICALLS)
2889 model = TLS_MODEL_LOCAL_EXEC;
2893 case TLS_MODEL_GLOBAL_DYNAMIC:
2894 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2895 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
2896 dest = gen_reg_rtx (Pmode);
2897 emit_libcall_block (insn, dest, v0, loc);
2900 case TLS_MODEL_LOCAL_DYNAMIC:
2901 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2902 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
2903 tmp1 = gen_reg_rtx (Pmode);
2905 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2906 share the LDM result with other LD model accesses. */
2907 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2909 emit_libcall_block (insn, tmp1, v0, eqv);
2911 offset = mips_unspec_address (loc, SYMBOL_DTPREL);
2912 if (mips_split_p[SYMBOL_DTPREL])
2914 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
2915 dest = gen_rtx_LO_SUM (Pmode, tmp2, offset);
2918 dest = expand_binop (Pmode, add_optab, tmp1, offset,
2919 0, 0, OPTAB_DIRECT);
2922 case TLS_MODEL_INITIAL_EXEC:
2923 tp = mips_get_tp ();
2924 tmp1 = gen_reg_rtx (Pmode);
2925 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
2926 if (Pmode == DImode)
2927 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
2929 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
2930 dest = gen_reg_rtx (Pmode);
2931 emit_insn (gen_add3_insn (dest, tmp1, tp));
2934 case TLS_MODEL_LOCAL_EXEC:
2935 tmp1 = mips_get_tp ();
2936 offset = mips_unspec_address (loc, SYMBOL_TPREL);
2937 if (mips_split_p[SYMBOL_TPREL])
2939 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_TPREL);
2940 dest = gen_rtx_LO_SUM (Pmode, tmp2, offset);
2943 dest = expand_binop (Pmode, add_optab, tmp1, offset,
2944 0, 0, OPTAB_DIRECT);
2953 /* If X is not a valid address for mode MODE, force it into a register. */
2956 mips_force_address (rtx x, enum machine_mode mode)
2958 if (!mips_legitimate_address_p (mode, x, false))
2959 x = force_reg (Pmode, x);
2963 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
2964 be legitimized in a way that the generic machinery might not expect,
2965 return a new address, otherwise return NULL. MODE is the mode of
2966 the memory being accessed. */
2969 mips_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
2970 enum machine_mode mode)
2973 HOST_WIDE_INT offset;
2975 if (mips_tls_symbol_p (x))
2976 return mips_legitimize_tls_address (x);
2978 /* See if the address can split into a high part and a LO_SUM. */
2979 if (mips_split_symbol (NULL, x, mode, &addr))
2980 return mips_force_address (addr, mode);
2982 /* Handle BASE + OFFSET using mips_add_offset. */
2983 mips_split_plus (x, &base, &offset);
2986 if (!mips_valid_base_register_p (base, mode, false))
2987 base = copy_to_mode_reg (Pmode, base);
2988 addr = mips_add_offset (NULL, base, offset);
2989 return mips_force_address (addr, mode);
2995 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
2998 mips_move_integer (rtx temp, rtx dest, unsigned HOST_WIDE_INT value)
3000 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
3001 enum machine_mode mode;
3002 unsigned int i, num_ops;
3005 mode = GET_MODE (dest);
3006 num_ops = mips_build_integer (codes, value);
3008 /* Apply each binary operation to X. Invariant: X is a legitimate
3009 source operand for a SET pattern. */
3010 x = GEN_INT (codes[0].value);
3011 for (i = 1; i < num_ops; i++)
3013 if (!can_create_pseudo_p ())
3015 emit_insn (gen_rtx_SET (VOIDmode, temp, x));
3019 x = force_reg (mode, x);
3020 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
3023 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
3026 /* Subroutine of mips_legitimize_move. Move constant SRC into register
3027 DEST given that SRC satisfies immediate_operand but doesn't satisfy
3031 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
3035 /* Split moves of big integers into smaller pieces. */
3036 if (splittable_const_int_operand (src, mode))
3038 mips_move_integer (dest, dest, INTVAL (src));
3042 /* Split moves of symbolic constants into high/low pairs. */
3043 if (mips_split_symbol (dest, src, MAX_MACHINE_MODE, &src))
3045 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
3049 /* Generate the appropriate access sequences for TLS symbols. */
3050 if (mips_tls_symbol_p (src))
3052 mips_emit_move (dest, mips_legitimize_tls_address (src));
3056 /* If we have (const (plus symbol offset)), and that expression cannot
3057 be forced into memory, load the symbol first and add in the offset.
3058 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
3059 forced into memory, as it usually produces better code. */
3060 split_const (src, &base, &offset);
3061 if (offset != const0_rtx
3062 && (targetm.cannot_force_const_mem (mode, src)
3063 || (!TARGET_MIPS16 && can_create_pseudo_p ())))
3065 base = mips_force_temporary (dest, base);
3066 mips_emit_move (dest, mips_add_offset (NULL, base, INTVAL (offset)));
3070 src = force_const_mem (mode, src);
3072 /* When using explicit relocs, constant pool references are sometimes
3073 not legitimate addresses. */
3074 mips_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0));
3075 mips_emit_move (dest, src);
3078 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
3079 sequence that is valid. */
3082 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
3084 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
3086 mips_emit_move (dest, force_reg (mode, src));
3090 /* We need to deal with constants that would be legitimate
3091 immediate_operands but aren't legitimate move_operands. */
3092 if (CONSTANT_P (src) && !move_operand (src, mode))
3094 mips_legitimize_const_move (mode, dest, src);
3095 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
3101 /* Return true if value X in context CONTEXT is a small-data address
3102 that can be rewritten as a LO_SUM. */
3105 mips_rewrite_small_data_p (rtx x, enum mips_symbol_context context)
3107 enum mips_symbol_type symbol_type;
3109 return (mips_lo_relocs[SYMBOL_GP_RELATIVE]
3110 && !mips_split_p[SYMBOL_GP_RELATIVE]
3111 && mips_symbolic_constant_p (x, context, &symbol_type)
3112 && symbol_type == SYMBOL_GP_RELATIVE);
3115 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
3116 containing MEM, or null if none. */
3119 mips_small_data_pattern_1 (rtx *loc, void *data)
3121 enum mips_symbol_context context;
3123 /* Ignore things like "g" constraints in asms. We make no particular
3124 guarantee about which symbolic constants are acceptable as asm operands
3125 versus which must be forced into a GPR. */
3126 if (GET_CODE (*loc) == LO_SUM || GET_CODE (*loc) == ASM_OPERANDS)
3131 if (for_each_rtx (&XEXP (*loc, 0), mips_small_data_pattern_1, *loc))
3136 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3137 return mips_rewrite_small_data_p (*loc, context);
3140 /* Return true if OP refers to small data symbols directly, not through
3144 mips_small_data_pattern_p (rtx op)
3146 return for_each_rtx (&op, mips_small_data_pattern_1, NULL);
3149 /* A for_each_rtx callback, used by mips_rewrite_small_data.
3150 DATA is the containing MEM, or null if none. */
3153 mips_rewrite_small_data_1 (rtx *loc, void *data)
3155 enum mips_symbol_context context;
3159 for_each_rtx (&XEXP (*loc, 0), mips_rewrite_small_data_1, *loc);
3163 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3164 if (mips_rewrite_small_data_p (*loc, context))
3165 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
3167 if (GET_CODE (*loc) == LO_SUM)
3173 /* Rewrite instruction pattern PATTERN so that it refers to small data
3174 using explicit relocations. */
3177 mips_rewrite_small_data (rtx pattern)
3179 pattern = copy_insn (pattern);
3180 for_each_rtx (&pattern, mips_rewrite_small_data_1, NULL);
3184 /* We need a lot of little routines to check the range of MIPS16 immediate
3188 m16_check_op (rtx op, int low, int high, int mask)
3190 return (CONST_INT_P (op)
3191 && IN_RANGE (INTVAL (op), low, high)
3192 && (INTVAL (op) & mask) == 0);
3196 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3198 return m16_check_op (op, 0x1, 0x8, 0);
3202 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3204 return m16_check_op (op, -0x8, 0x7, 0);
3208 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3210 return m16_check_op (op, -0x7, 0x8, 0);
3214 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3216 return m16_check_op (op, -0x10, 0xf, 0);
3220 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3222 return m16_check_op (op, -0xf, 0x10, 0);
3226 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3228 return m16_check_op (op, -0x10 << 2, 0xf << 2, 3);
3232 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3234 return m16_check_op (op, -0xf << 2, 0x10 << 2, 3);
3238 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3240 return m16_check_op (op, -0x80, 0x7f, 0);
3244 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3246 return m16_check_op (op, -0x7f, 0x80, 0);
3250 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3252 return m16_check_op (op, 0x0, 0xff, 0);
3256 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3258 return m16_check_op (op, -0xff, 0x0, 0);
3262 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3264 return m16_check_op (op, -0x1, 0xfe, 0);
3268 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3270 return m16_check_op (op, 0x0, 0xff << 2, 3);
3274 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3276 return m16_check_op (op, -0xff << 2, 0x0, 3);
3280 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3282 return m16_check_op (op, -0x80 << 3, 0x7f << 3, 7);
3286 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3288 return m16_check_op (op, -0x7f << 3, 0x80 << 3, 7);
3291 /* The cost of loading values from the constant pool. It should be
3292 larger than the cost of any constant we want to synthesize inline. */
3293 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3295 /* Return the cost of X when used as an operand to the MIPS16 instruction
3296 that implements CODE. Return -1 if there is no such instruction, or if
3297 X is not a valid immediate operand for it. */
3300 mips16_constant_cost (int code, HOST_WIDE_INT x)
3307 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3308 other shifts are extended. The shift patterns truncate the shift
3309 count to the right size, so there are no out-of-range values. */
3310 if (IN_RANGE (x, 1, 8))
3312 return COSTS_N_INSNS (1);
3315 if (IN_RANGE (x, -128, 127))
3317 if (SMALL_OPERAND (x))
3318 return COSTS_N_INSNS (1);
3322 /* Like LE, but reject the always-true case. */
3326 /* We add 1 to the immediate and use SLT. */
3329 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3332 if (IN_RANGE (x, 0, 255))
3334 if (SMALL_OPERAND_UNSIGNED (x))
3335 return COSTS_N_INSNS (1);
3340 /* Equality comparisons with 0 are cheap. */
3350 /* Return true if there is a non-MIPS16 instruction that implements CODE
3351 and if that instruction accepts X as an immediate operand. */
3354 mips_immediate_operand_p (int code, HOST_WIDE_INT x)
3361 /* All shift counts are truncated to a valid constant. */
3366 /* Likewise rotates, if the target supports rotates at all. */
3372 /* These instructions take 16-bit unsigned immediates. */
3373 return SMALL_OPERAND_UNSIGNED (x);
3378 /* These instructions take 16-bit signed immediates. */
3379 return SMALL_OPERAND (x);
3385 /* The "immediate" forms of these instructions are really
3386 implemented as comparisons with register 0. */
3391 /* Likewise, meaning that the only valid immediate operand is 1. */
3395 /* We add 1 to the immediate and use SLT. */
3396 return SMALL_OPERAND (x + 1);
3399 /* Likewise SLTU, but reject the always-true case. */
3400 return SMALL_OPERAND (x + 1) && x + 1 != 0;
3404 /* The bit position and size are immediate operands. */
3405 return ISA_HAS_EXT_INS;
3408 /* By default assume that $0 can be used for 0. */
3413 /* Return the cost of binary operation X, given that the instruction
3414 sequence for a word-sized or smaller operation has cost SINGLE_COST
3415 and that the sequence of a double-word operation has cost DOUBLE_COST.
3416 If SPEED is true, optimize for speed otherwise optimize for size. */
3419 mips_binary_cost (rtx x, int single_cost, int double_cost, bool speed)
3423 if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2)
3428 + set_src_cost (XEXP (x, 0), speed)
3429 + rtx_cost (XEXP (x, 1), GET_CODE (x), 1, speed));
3432 /* Return the cost of floating-point multiplications of mode MODE. */
3435 mips_fp_mult_cost (enum machine_mode mode)
3437 return mode == DFmode ? mips_cost->fp_mult_df : mips_cost->fp_mult_sf;
3440 /* Return the cost of floating-point divisions of mode MODE. */
3443 mips_fp_div_cost (enum machine_mode mode)
3445 return mode == DFmode ? mips_cost->fp_div_df : mips_cost->fp_div_sf;
3448 /* Return the cost of sign-extending OP to mode MODE, not including the
3449 cost of OP itself. */
3452 mips_sign_extend_cost (enum machine_mode mode, rtx op)
3455 /* Extended loads are as cheap as unextended ones. */
3458 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3459 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3462 if (ISA_HAS_SEB_SEH || GENERATE_MIPS16E)
3463 /* We can use SEB or SEH. */
3464 return COSTS_N_INSNS (1);
3466 /* We need to use a shift left and a shift right. */
3467 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3470 /* Return the cost of zero-extending OP to mode MODE, not including the
3471 cost of OP itself. */
3474 mips_zero_extend_cost (enum machine_mode mode, rtx op)
3477 /* Extended loads are as cheap as unextended ones. */
3480 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3481 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3482 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3484 if (GENERATE_MIPS16E)
3485 /* We can use ZEB or ZEH. */
3486 return COSTS_N_INSNS (1);
3489 /* We need to load 0xff or 0xffff into a register and use AND. */
3490 return COSTS_N_INSNS (GET_MODE (op) == QImode ? 2 : 3);
3492 /* We can use ANDI. */
3493 return COSTS_N_INSNS (1);
3496 /* Return the cost of moving between two registers of mode MODE,
3497 assuming that the move will be in pieces of at most UNITS bytes. */
3500 mips_set_reg_reg_piece_cost (enum machine_mode mode, unsigned int units)
3502 return COSTS_N_INSNS ((GET_MODE_SIZE (mode) + units - 1) / units);
3505 /* Return the cost of moving between two registers of mode MODE. */
3508 mips_set_reg_reg_cost (enum machine_mode mode)
3510 switch (GET_MODE_CLASS (mode))
3513 return mips_set_reg_reg_piece_cost (mode, GET_MODE_SIZE (CCmode));
3516 case MODE_COMPLEX_FLOAT:
3517 case MODE_VECTOR_FLOAT:
3518 if (TARGET_HARD_FLOAT)
3519 return mips_set_reg_reg_piece_cost (mode, UNITS_PER_HWFPVALUE);
3523 return mips_set_reg_reg_piece_cost (mode, UNITS_PER_WORD);
3527 /* Implement TARGET_RTX_COSTS. */
3530 mips_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
3531 int *total, bool speed)
3533 enum machine_mode mode = GET_MODE (x);
3534 bool float_mode_p = FLOAT_MODE_P (mode);
3538 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3539 appear in the instruction stream, and the cost of a comparison is
3540 really the cost of the branch or scc condition. At the time of
3541 writing, GCC only uses an explicit outer COMPARE code when optabs
3542 is testing whether a constant is expensive enough to force into a
3543 register. We want optabs to pass such constants through the MIPS
3544 expanders instead, so make all constants very cheap here. */
3545 if (outer_code == COMPARE)
3547 gcc_assert (CONSTANT_P (x));
3555 /* Treat *clear_upper32-style ANDs as having zero cost in the
3556 second operand. The cost is entirely in the first operand.
3558 ??? This is needed because we would otherwise try to CSE
3559 the constant operand. Although that's the right thing for
3560 instructions that continue to be a register operation throughout
3561 compilation, it is disastrous for instructions that could
3562 later be converted into a memory operation. */
3564 && outer_code == AND
3565 && UINTVAL (x) == 0xffffffff)
3573 cost = mips16_constant_cost (outer_code, INTVAL (x));
3582 /* When not optimizing for size, we care more about the cost
3583 of hot code, and hot code is often in a loop. If a constant
3584 operand needs to be forced into a register, we will often be
3585 able to hoist the constant load out of the loop, so the load
3586 should not contribute to the cost. */
3587 if (speed || mips_immediate_operand_p (outer_code, INTVAL (x)))
3599 if (force_to_mem_operand (x, VOIDmode))
3601 *total = COSTS_N_INSNS (1);
3604 cost = mips_const_insns (x);
3607 /* If the constant is likely to be stored in a GPR, SETs of
3608 single-insn constants are as cheap as register sets; we
3609 never want to CSE them.
3611 Don't reduce the cost of storing a floating-point zero in
3612 FPRs. If we have a zero in an FPR for other reasons, we
3613 can get better cfg-cleanup and delayed-branch results by
3614 using it consistently, rather than using $0 sometimes and
3615 an FPR at other times. Also, moves between floating-point
3616 registers are sometimes cheaper than (D)MTC1 $0. */
3618 && outer_code == SET
3619 && !(float_mode_p && TARGET_HARD_FLOAT))
3621 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3622 want to CSE the constant itself. It is usually better to
3623 have N copies of the last operation in the sequence and one
3624 shared copy of the other operations. (Note that this is
3625 not true for MIPS16 code, where the final operation in the
3626 sequence is often an extended instruction.)
3628 Also, if we have a CONST_INT, we don't know whether it is
3629 for a word or doubleword operation, so we cannot rely on
3630 the result of mips_build_integer. */
3631 else if (!TARGET_MIPS16
3632 && (outer_code == SET || mode == VOIDmode))
3634 *total = COSTS_N_INSNS (cost);
3637 /* The value will need to be fetched from the constant pool. */
3638 *total = CONSTANT_POOL_COST;
3642 /* If the address is legitimate, return the number of
3643 instructions it needs. */
3645 cost = mips_address_insns (addr, mode, true);
3648 *total = COSTS_N_INSNS (cost + 1);
3651 /* Check for a scaled indexed address. */
3652 if (mips_lwxs_address_p (addr)
3653 || mips_lx_address_p (addr, mode))
3655 *total = COSTS_N_INSNS (2);
3658 /* Otherwise use the default handling. */
3662 *total = COSTS_N_INSNS (6);
3666 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1);
3670 /* Check for a *clear_upper32 pattern and treat it like a zero
3671 extension. See the pattern's comment for details. */
3674 && CONST_INT_P (XEXP (x, 1))
3675 && UINTVAL (XEXP (x, 1)) == 0xffffffff)
3677 *total = (mips_zero_extend_cost (mode, XEXP (x, 0))
3678 + set_src_cost (XEXP (x, 0), speed));
3685 /* Double-word operations use two single-word operations. */
3686 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (2),
3695 if (CONSTANT_P (XEXP (x, 1)))
3696 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3699 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (12),
3705 *total = mips_cost->fp_add;
3707 *total = COSTS_N_INSNS (4);
3711 /* Low-part immediates need an extended MIPS16 instruction. */
3712 *total = (COSTS_N_INSNS (TARGET_MIPS16 ? 2 : 1)
3713 + set_src_cost (XEXP (x, 0), speed));
3728 /* Branch comparisons have VOIDmode, so use the first operand's
3730 mode = GET_MODE (XEXP (x, 0));
3731 if (FLOAT_MODE_P (mode))
3733 *total = mips_cost->fp_add;
3736 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3742 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3743 && TARGET_FUSED_MADD
3744 && !HONOR_NANS (mode)
3745 && !HONOR_SIGNED_ZEROS (mode))
3747 /* See if we can use NMADD or NMSUB. See mips.md for the
3748 associated patterns. */
3749 rtx op0 = XEXP (x, 0);
3750 rtx op1 = XEXP (x, 1);
3751 if (GET_CODE (op0) == MULT && GET_CODE (XEXP (op0, 0)) == NEG)
3753 *total = (mips_fp_mult_cost (mode)
3754 + set_src_cost (XEXP (XEXP (op0, 0), 0), speed)
3755 + set_src_cost (XEXP (op0, 1), speed)
3756 + set_src_cost (op1, speed));
3759 if (GET_CODE (op1) == MULT)
3761 *total = (mips_fp_mult_cost (mode)
3762 + set_src_cost (op0, speed)
3763 + set_src_cost (XEXP (op1, 0), speed)
3764 + set_src_cost (XEXP (op1, 1), speed));
3773 /* If this is part of a MADD or MSUB, treat the PLUS as
3776 && TARGET_FUSED_MADD
3777 && GET_CODE (XEXP (x, 0)) == MULT)
3780 *total = mips_cost->fp_add;
3784 /* Double-word operations require three single-word operations and
3785 an SLTU. The MIPS16 version then needs to move the result of
3786 the SLTU from $24 to a MIPS16 register. */
3787 *total = mips_binary_cost (x, COSTS_N_INSNS (1),
3788 COSTS_N_INSNS (TARGET_MIPS16 ? 5 : 4),
3794 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3795 && TARGET_FUSED_MADD
3796 && !HONOR_NANS (mode)
3797 && HONOR_SIGNED_ZEROS (mode))
3799 /* See if we can use NMADD or NMSUB. See mips.md for the
3800 associated patterns. */
3801 rtx op = XEXP (x, 0);
3802 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
3803 && GET_CODE (XEXP (op, 0)) == MULT)
3805 *total = (mips_fp_mult_cost (mode)
3806 + set_src_cost (XEXP (XEXP (op, 0), 0), speed)
3807 + set_src_cost (XEXP (XEXP (op, 0), 1), speed)
3808 + set_src_cost (XEXP (op, 1), speed));
3814 *total = mips_cost->fp_add;
3816 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1);
3821 *total = mips_fp_mult_cost (mode);
3822 else if (mode == DImode && !TARGET_64BIT)
3823 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
3824 where the mulsidi3 always includes an MFHI and an MFLO. */
3826 ? mips_cost->int_mult_si * 3 + 6
3827 : COSTS_N_INSNS (ISA_HAS_MUL3 ? 7 : 9));
3829 *total = (ISA_HAS_MUL3 ? 1 : 2);
3830 else if (mode == DImode)
3831 *total = mips_cost->int_mult_di;
3833 *total = mips_cost->int_mult_si;
3837 /* Check for a reciprocal. */
3840 && flag_unsafe_math_optimizations
3841 && XEXP (x, 0) == CONST1_RTX (mode))
3843 if (outer_code == SQRT || GET_CODE (XEXP (x, 1)) == SQRT)
3844 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
3845 division as being free. */
3846 *total = set_src_cost (XEXP (x, 1), speed);
3848 *total = (mips_fp_div_cost (mode)
3849 + set_src_cost (XEXP (x, 1), speed));
3858 *total = mips_fp_div_cost (mode);
3867 /* It is our responsibility to make division by a power of 2
3868 as cheap as 2 register additions if we want the division
3869 expanders to be used for such operations; see the setting
3870 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
3871 should always produce shorter code than using
3872 expand_sdiv2_pow2. */
3874 && CONST_INT_P (XEXP (x, 1))
3875 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
3877 *total = COSTS_N_INSNS (2) + set_src_cost (XEXP (x, 0), speed);
3880 *total = COSTS_N_INSNS (mips_idiv_insns ());
3882 else if (mode == DImode)
3883 *total = mips_cost->int_div_di;
3885 *total = mips_cost->int_div_si;
3889 *total = mips_sign_extend_cost (mode, XEXP (x, 0));
3893 if (outer_code == SET
3895 && (GET_CODE (XEXP (x, 0)) == TRUNCATE
3896 || GET_CODE (XEXP (x, 0)) == SUBREG)
3897 && GET_MODE (XEXP (x, 0)) == QImode
3898 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
3900 *total = set_src_cost (XEXP (XEXP (x, 0), 0), speed);
3903 *total = mips_zero_extend_cost (mode, XEXP (x, 0));
3907 case UNSIGNED_FLOAT:
3910 case FLOAT_TRUNCATE:
3911 *total = mips_cost->fp_add;
3915 if (register_operand (SET_DEST (x), VOIDmode)
3916 && reg_or_0_operand (SET_SRC (x), VOIDmode))
3918 *total = mips_set_reg_reg_cost (GET_MODE (SET_DEST (x)));
3928 /* Implement TARGET_ADDRESS_COST. */
3931 mips_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED)
3933 return mips_address_insns (addr, SImode, false);
3936 /* Information about a single instruction in a multi-instruction
3938 struct mips_multi_member {
3939 /* True if this is a label, false if it is code. */
3942 /* The output_asm_insn format of the instruction. */
3945 /* The operands to the instruction. */
3946 rtx operands[MAX_RECOG_OPERANDS];
3948 typedef struct mips_multi_member mips_multi_member;
3950 /* Vector definitions for the above. */
3951 DEF_VEC_O(mips_multi_member);
3952 DEF_VEC_ALLOC_O(mips_multi_member, heap);
3954 /* The instructions that make up the current multi-insn sequence. */
3955 static VEC (mips_multi_member, heap) *mips_multi_members;
3957 /* How many instructions (as opposed to labels) are in the current
3958 multi-insn sequence. */
3959 static unsigned int mips_multi_num_insns;
3961 /* Start a new multi-insn sequence. */
3964 mips_multi_start (void)
3966 VEC_truncate (mips_multi_member, mips_multi_members, 0);
3967 mips_multi_num_insns = 0;
3970 /* Add a new, uninitialized member to the current multi-insn sequence. */
3972 static struct mips_multi_member *
3973 mips_multi_add (void)
3975 return VEC_safe_push (mips_multi_member, heap, mips_multi_members, 0);
3978 /* Add a normal insn with the given asm format to the current multi-insn
3979 sequence. The other arguments are a null-terminated list of operands. */
3982 mips_multi_add_insn (const char *format, ...)
3984 struct mips_multi_member *member;
3989 member = mips_multi_add ();
3990 member->is_label_p = false;
3991 member->format = format;
3992 va_start (ap, format);
3994 while ((op = va_arg (ap, rtx)))
3995 member->operands[i++] = op;
3997 mips_multi_num_insns++;
4000 /* Add the given label definition to the current multi-insn sequence.
4001 The definition should include the colon. */
4004 mips_multi_add_label (const char *label)
4006 struct mips_multi_member *member;
4008 member = mips_multi_add ();
4009 member->is_label_p = true;
4010 member->format = label;
4013 /* Return the index of the last member of the current multi-insn sequence. */
4016 mips_multi_last_index (void)
4018 return VEC_length (mips_multi_member, mips_multi_members) - 1;
4021 /* Add a copy of an existing instruction to the current multi-insn
4022 sequence. I is the index of the instruction that should be copied. */
4025 mips_multi_copy_insn (unsigned int i)
4027 struct mips_multi_member *member;
4029 member = mips_multi_add ();
4030 memcpy (member, VEC_index (mips_multi_member, mips_multi_members, i),
4032 gcc_assert (!member->is_label_p);
4035 /* Change the operand of an existing instruction in the current
4036 multi-insn sequence. I is the index of the instruction,
4037 OP is the index of the operand, and X is the new value. */
4040 mips_multi_set_operand (unsigned int i, unsigned int op, rtx x)
4042 VEC_index (mips_multi_member, mips_multi_members, i)->operands[op] = x;
4045 /* Write out the asm code for the current multi-insn sequence. */
4048 mips_multi_write (void)
4050 struct mips_multi_member *member;
4053 FOR_EACH_VEC_ELT (mips_multi_member, mips_multi_members, i, member)
4054 if (member->is_label_p)
4055 fprintf (asm_out_file, "%s\n", member->format);
4057 output_asm_insn (member->format, member->operands);
4060 /* Return one word of double-word value OP, taking into account the fixed
4061 endianness of certain registers. HIGH_P is true to select the high part,
4062 false to select the low part. */
4065 mips_subword (rtx op, bool high_p)
4067 unsigned int byte, offset;
4068 enum machine_mode mode;
4070 mode = GET_MODE (op);
4071 if (mode == VOIDmode)
4072 mode = TARGET_64BIT ? TImode : DImode;
4074 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
4075 byte = UNITS_PER_WORD;
4079 if (FP_REG_RTX_P (op))
4081 /* Paired FPRs are always ordered little-endian. */
4082 offset = (UNITS_PER_WORD < UNITS_PER_HWFPVALUE ? high_p : byte != 0);
4083 return gen_rtx_REG (word_mode, REGNO (op) + offset);
4087 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
4089 return simplify_gen_subreg (word_mode, op, mode, byte);
4092 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
4095 mips_split_64bit_move_p (rtx dest, rtx src)
4100 /* FPR-to-FPR moves can be done in a single instruction, if they're
4102 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
4105 /* Check for floating-point loads and stores. */
4106 if (ISA_HAS_LDC1_SDC1)
4108 if (FP_REG_RTX_P (dest) && MEM_P (src))
4110 if (FP_REG_RTX_P (src) && MEM_P (dest))
4116 /* Split a doubleword move from SRC to DEST. On 32-bit targets,
4117 this function handles 64-bit moves for which mips_split_64bit_move_p
4118 holds. For 64-bit targets, this function handles 128-bit moves. */
4121 mips_split_doubleword_move (rtx dest, rtx src)
4125 if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src))
4127 if (!TARGET_64BIT && GET_MODE (dest) == DImode)
4128 emit_insn (gen_move_doubleword_fprdi (dest, src));
4129 else if (!TARGET_64BIT && GET_MODE (dest) == DFmode)
4130 emit_insn (gen_move_doubleword_fprdf (dest, src));
4131 else if (!TARGET_64BIT && GET_MODE (dest) == V2SFmode)
4132 emit_insn (gen_move_doubleword_fprv2sf (dest, src));
4133 else if (!TARGET_64BIT && GET_MODE (dest) == V2SImode)
4134 emit_insn (gen_move_doubleword_fprv2si (dest, src));
4135 else if (!TARGET_64BIT && GET_MODE (dest) == V4HImode)
4136 emit_insn (gen_move_doubleword_fprv4hi (dest, src));
4137 else if (!TARGET_64BIT && GET_MODE (dest) == V8QImode)
4138 emit_insn (gen_move_doubleword_fprv8qi (dest, src));
4139 else if (TARGET_64BIT && GET_MODE (dest) == TFmode)
4140 emit_insn (gen_move_doubleword_fprtf (dest, src));
4144 else if (REG_P (dest) && REGNO (dest) == MD_REG_FIRST)
4146 low_dest = mips_subword (dest, false);
4147 mips_emit_move (low_dest, mips_subword (src, false));
4149 emit_insn (gen_mthidi_ti (dest, mips_subword (src, true), low_dest));
4151 emit_insn (gen_mthisi_di (dest, mips_subword (src, true), low_dest));
4153 else if (REG_P (src) && REGNO (src) == MD_REG_FIRST)
4155 mips_emit_move (mips_subword (dest, false), mips_subword (src, false));
4157 emit_insn (gen_mfhidi_ti (mips_subword (dest, true), src));
4159 emit_insn (gen_mfhisi_di (mips_subword (dest, true), src));
4163 /* The operation can be split into two normal moves. Decide in
4164 which order to do them. */
4165 low_dest = mips_subword (dest, false);
4166 if (REG_P (low_dest)
4167 && reg_overlap_mentioned_p (low_dest, src))
4169 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4170 mips_emit_move (low_dest, mips_subword (src, false));
4174 mips_emit_move (low_dest, mips_subword (src, false));
4175 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4180 /* Return the appropriate instructions to move SRC into DEST. Assume
4181 that SRC is operand 1 and DEST is operand 0. */
4184 mips_output_move (rtx dest, rtx src)
4186 enum rtx_code dest_code, src_code;
4187 enum machine_mode mode;
4188 enum mips_symbol_type symbol_type;
4191 dest_code = GET_CODE (dest);
4192 src_code = GET_CODE (src);
4193 mode = GET_MODE (dest);
4194 dbl_p = (GET_MODE_SIZE (mode) == 8);
4196 if (dbl_p && mips_split_64bit_move_p (dest, src))
4199 if ((src_code == REG && GP_REG_P (REGNO (src)))
4200 || (!TARGET_MIPS16 && src == CONST0_RTX (mode)))
4202 if (dest_code == REG)
4204 if (GP_REG_P (REGNO (dest)))
4205 return "move\t%0,%z1";
4207 /* Moves to HI are handled by special .md insns. */
4208 if (REGNO (dest) == LO_REGNUM)
4211 if (DSP_ACC_REG_P (REGNO (dest)))
4213 static char retval[] = "mt__\t%z1,%q0";
4215 retval[2] = reg_names[REGNO (dest)][4];
4216 retval[3] = reg_names[REGNO (dest)][5];
4220 if (FP_REG_P (REGNO (dest)))
4221 return dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
4223 if (ALL_COP_REG_P (REGNO (dest)))
4225 static char retval[] = "dmtc_\t%z1,%0";
4227 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4228 return dbl_p ? retval : retval + 1;
4231 if (dest_code == MEM)
4232 switch (GET_MODE_SIZE (mode))
4234 case 1: return "sb\t%z1,%0";
4235 case 2: return "sh\t%z1,%0";
4236 case 4: return "sw\t%z1,%0";
4237 case 8: return "sd\t%z1,%0";
4240 if (dest_code == REG && GP_REG_P (REGNO (dest)))
4242 if (src_code == REG)
4244 /* Moves from HI are handled by special .md insns. */
4245 if (REGNO (src) == LO_REGNUM)
4247 /* When generating VR4120 or VR4130 code, we use MACC and
4248 DMACC instead of MFLO. This avoids both the normal
4249 MIPS III HI/LO hazards and the errata related to
4252 return dbl_p ? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
4256 if (DSP_ACC_REG_P (REGNO (src)))
4258 static char retval[] = "mf__\t%0,%q1";
4260 retval[2] = reg_names[REGNO (src)][4];
4261 retval[3] = reg_names[REGNO (src)][5];
4265 if (FP_REG_P (REGNO (src)))
4266 return dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
4268 if (ALL_COP_REG_P (REGNO (src)))
4270 static char retval[] = "dmfc_\t%0,%1";
4272 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4273 return dbl_p ? retval : retval + 1;
4276 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
4277 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
4280 if (src_code == MEM)
4281 switch (GET_MODE_SIZE (mode))
4283 case 1: return "lbu\t%0,%1";
4284 case 2: return "lhu\t%0,%1";
4285 case 4: return "lw\t%0,%1";
4286 case 8: return "ld\t%0,%1";
4289 if (src_code == CONST_INT)
4291 /* Don't use the X format for the operand itself, because that
4292 will give out-of-range numbers for 64-bit hosts and 32-bit
4295 return "li\t%0,%1\t\t\t# %X1";
4297 if (SMALL_OPERAND_UNSIGNED (INTVAL (src)))
4300 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src)))
4304 if (src_code == HIGH)
4305 return TARGET_MIPS16 ? "#" : "lui\t%0,%h1";
4307 if (CONST_GP_P (src))
4308 return "move\t%0,%1";
4310 if (mips_symbolic_constant_p (src, SYMBOL_CONTEXT_LEA, &symbol_type)
4311 && mips_lo_relocs[symbol_type] != 0)
4313 /* A signed 16-bit constant formed by applying a relocation
4314 operator to a symbolic address. */
4315 gcc_assert (!mips_split_p[symbol_type]);
4316 return "li\t%0,%R1";
4319 if (symbolic_operand (src, VOIDmode))
4321 gcc_assert (TARGET_MIPS16
4322 ? TARGET_MIPS16_TEXT_LOADS
4323 : !TARGET_EXPLICIT_RELOCS);
4324 return dbl_p ? "dla\t%0,%1" : "la\t%0,%1";
4327 if (src_code == REG && FP_REG_P (REGNO (src)))
4329 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4331 if (GET_MODE (dest) == V2SFmode)
4332 return "mov.ps\t%0,%1";
4334 return dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1";
4337 if (dest_code == MEM)
4338 return dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0";
4340 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4342 if (src_code == MEM)
4343 return dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1";
4345 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
4347 static char retval[] = "l_c_\t%0,%1";
4349 retval[1] = (dbl_p ? 'd' : 'w');
4350 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4353 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
4355 static char retval[] = "s_c_\t%1,%0";
4357 retval[1] = (dbl_p ? 'd' : 'w');
4358 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4364 /* Return true if CMP1 is a suitable second operand for integer ordering
4365 test CODE. See also the *sCC patterns in mips.md. */
4368 mips_int_order_operand_ok_p (enum rtx_code code, rtx cmp1)
4374 return reg_or_0_operand (cmp1, VOIDmode);
4378 return !TARGET_MIPS16 && cmp1 == const1_rtx;
4382 return arith_operand (cmp1, VOIDmode);
4385 return sle_operand (cmp1, VOIDmode);
4388 return sleu_operand (cmp1, VOIDmode);
4395 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4396 integer ordering test *CODE, or if an equivalent combination can
4397 be formed by adjusting *CODE and *CMP1. When returning true, update
4398 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4402 mips_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1,
4403 enum machine_mode mode)
4405 HOST_WIDE_INT plus_one;
4407 if (mips_int_order_operand_ok_p (*code, *cmp1))
4410 if (CONST_INT_P (*cmp1))
4414 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4415 if (INTVAL (*cmp1) < plus_one)
4418 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4424 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4428 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4439 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4440 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4441 is nonnull, it's OK to set TARGET to the inverse of the result and
4442 flip *INVERT_PTR instead. */
4445 mips_emit_int_order_test (enum rtx_code code, bool *invert_ptr,
4446 rtx target, rtx cmp0, rtx cmp1)
4448 enum machine_mode mode;
4450 /* First see if there is a MIPS instruction that can do this operation.
4451 If not, try doing the same for the inverse operation. If that also
4452 fails, force CMP1 into a register and try again. */
4453 mode = GET_MODE (cmp0);
4454 if (mips_canonicalize_int_order_test (&code, &cmp1, mode))
4455 mips_emit_binary (code, target, cmp0, cmp1);
4458 enum rtx_code inv_code = reverse_condition (code);
4459 if (!mips_canonicalize_int_order_test (&inv_code, &cmp1, mode))
4461 cmp1 = force_reg (mode, cmp1);
4462 mips_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1);
4464 else if (invert_ptr == 0)
4468 inv_target = mips_force_binary (GET_MODE (target),
4469 inv_code, cmp0, cmp1);
4470 mips_emit_binary (XOR, target, inv_target, const1_rtx);
4474 *invert_ptr = !*invert_ptr;
4475 mips_emit_binary (inv_code, target, cmp0, cmp1);
4480 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4481 The register will have the same mode as CMP0. */
4484 mips_zero_if_equal (rtx cmp0, rtx cmp1)
4486 if (cmp1 == const0_rtx)
4489 if (uns_arith_operand (cmp1, VOIDmode))
4490 return expand_binop (GET_MODE (cmp0), xor_optab,
4491 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4493 return expand_binop (GET_MODE (cmp0), sub_optab,
4494 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4497 /* Convert *CODE into a code that can be used in a floating-point
4498 scc instruction (C.cond.fmt). Return true if the values of
4499 the condition code registers will be inverted, with 0 indicating
4500 that the condition holds. */
4503 mips_reversed_fp_cond (enum rtx_code *code)
4510 *code = reverse_condition_maybe_unordered (*code);
4518 /* Convert a comparison into something that can be used in a branch or
4519 conditional move. On entry, *OP0 and *OP1 are the values being
4520 compared and *CODE is the code used to compare them.
4522 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
4523 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
4524 otherwise any standard branch condition can be used. The standard branch
4527 - EQ or NE between two registers.
4528 - any comparison between a register and zero. */
4531 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
4536 if (GET_MODE_CLASS (GET_MODE (*op0)) == MODE_INT)
4538 if (!need_eq_ne_p && *op1 == const0_rtx)
4540 else if (*code == EQ || *code == NE)
4544 *op0 = mips_zero_if_equal (cmp_op0, cmp_op1);
4548 *op1 = force_reg (GET_MODE (cmp_op0), cmp_op1);
4552 /* The comparison needs a separate scc instruction. Store the
4553 result of the scc in *OP0 and compare it against zero. */
4554 bool invert = false;
4555 *op0 = gen_reg_rtx (GET_MODE (cmp_op0));
4556 mips_emit_int_order_test (*code, &invert, *op0, cmp_op0, cmp_op1);
4557 *code = (invert ? EQ : NE);
4561 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0)))
4563 *op0 = gen_rtx_REG (CCDSPmode, CCDSP_CC_REGNUM);
4564 mips_emit_binary (*code, *op0, cmp_op0, cmp_op1);
4570 enum rtx_code cmp_code;
4572 /* Floating-point tests use a separate C.cond.fmt comparison to
4573 set a condition code register. The branch or conditional move
4574 will then compare that register against zero.
4576 Set CMP_CODE to the code of the comparison instruction and
4577 *CODE to the code that the branch or move should use. */
4579 *code = mips_reversed_fp_cond (&cmp_code) ? EQ : NE;
4581 ? gen_reg_rtx (CCmode)
4582 : gen_rtx_REG (CCmode, FPSW_REGNUM));
4584 mips_emit_binary (cmp_code, *op0, cmp_op0, cmp_op1);
4588 /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2]
4589 and OPERAND[3]. Store the result in OPERANDS[0].
4591 On 64-bit targets, the mode of the comparison and target will always be
4592 SImode, thus possibly narrower than that of the comparison's operands. */
4595 mips_expand_scc (rtx operands[])
4597 rtx target = operands[0];
4598 enum rtx_code code = GET_CODE (operands[1]);
4599 rtx op0 = operands[2];
4600 rtx op1 = operands[3];
4602 gcc_assert (GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT);
4604 if (code == EQ || code == NE)
4607 && reg_imm10_operand (op1, GET_MODE (op1)))
4608 mips_emit_binary (code, target, op0, op1);
4611 rtx zie = mips_zero_if_equal (op0, op1);
4612 mips_emit_binary (code, target, zie, const0_rtx);
4616 mips_emit_int_order_test (code, 0, target, op0, op1);
4619 /* Compare OPERANDS[1] with OPERANDS[2] using comparison code
4620 CODE and jump to OPERANDS[3] if the condition holds. */
4623 mips_expand_conditional_branch (rtx *operands)
4625 enum rtx_code code = GET_CODE (operands[0]);
4626 rtx op0 = operands[1];
4627 rtx op1 = operands[2];
4630 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
4631 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
4632 emit_jump_insn (gen_condjump (condition, operands[3]));
4637 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
4638 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
4641 mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
4642 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
4647 reversed_p = mips_reversed_fp_cond (&cond);
4648 cmp_result = gen_reg_rtx (CCV2mode);
4649 emit_insn (gen_scc_ps (cmp_result,
4650 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
4652 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
4655 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
4659 /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0]
4660 if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
4663 mips_expand_conditional_move (rtx *operands)
4666 enum rtx_code code = GET_CODE (operands[1]);
4667 rtx op0 = XEXP (operands[1], 0);
4668 rtx op1 = XEXP (operands[1], 1);
4670 mips_emit_compare (&code, &op0, &op1, true);
4671 cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
4672 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
4673 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), cond,
4674 operands[2], operands[3])));
4677 /* Perform the comparison in COMPARISON, then trap if the condition holds. */
4680 mips_expand_conditional_trap (rtx comparison)
4683 enum machine_mode mode;
4686 /* MIPS conditional trap instructions don't have GT or LE flavors,
4687 so we must swap the operands and convert to LT and GE respectively. */
4688 code = GET_CODE (comparison);
4695 code = swap_condition (code);
4696 op0 = XEXP (comparison, 1);
4697 op1 = XEXP (comparison, 0);
4701 op0 = XEXP (comparison, 0);
4702 op1 = XEXP (comparison, 1);
4706 mode = GET_MODE (XEXP (comparison, 0));
4707 op0 = force_reg (mode, op0);
4708 if (!arith_operand (op1, mode))
4709 op1 = force_reg (mode, op1);
4711 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
4712 gen_rtx_fmt_ee (code, mode, op0, op1),
4716 /* Initialize *CUM for a call to a function of type FNTYPE. */
4719 mips_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype)
4721 memset (cum, 0, sizeof (*cum));
4722 cum->prototype = (fntype && prototype_p (fntype));
4723 cum->gp_reg_found = (cum->prototype && stdarg_p (fntype));
4726 /* Fill INFO with information about a single argument. CUM is the
4727 cumulative state for earlier arguments. MODE is the mode of this
4728 argument and TYPE is its type (if known). NAMED is true if this
4729 is a named (fixed) argument rather than a variable one. */
4732 mips_get_arg_info (struct mips_arg_info *info, const CUMULATIVE_ARGS *cum,
4733 enum machine_mode mode, const_tree type, bool named)
4735 bool doubleword_aligned_p;
4736 unsigned int num_bytes, num_words, max_regs;
4738 /* Work out the size of the argument. */
4739 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
4740 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4742 /* Decide whether it should go in a floating-point register, assuming
4743 one is free. Later code checks for availability.
4745 The checks against UNITS_PER_FPVALUE handle the soft-float and
4746 single-float cases. */
4750 /* The EABI conventions have traditionally been defined in terms
4751 of TYPE_MODE, regardless of the actual type. */
4752 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
4753 || mode == V2SFmode)
4754 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4759 /* Only leading floating-point scalars are passed in
4760 floating-point registers. We also handle vector floats the same
4761 say, which is OK because they are not covered by the standard ABI. */
4762 info->fpr_p = (!cum->gp_reg_found
4763 && cum->arg_number < 2
4765 || SCALAR_FLOAT_TYPE_P (type)
4766 || VECTOR_FLOAT_TYPE_P (type))
4767 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4768 || mode == V2SFmode)
4769 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4774 /* Scalar, complex and vector floating-point types are passed in
4775 floating-point registers, as long as this is a named rather
4776 than a variable argument. */
4777 info->fpr_p = (named
4778 && (type == 0 || FLOAT_TYPE_P (type))
4779 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4780 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4781 || mode == V2SFmode)
4782 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
4784 /* ??? According to the ABI documentation, the real and imaginary
4785 parts of complex floats should be passed in individual registers.
4786 The real and imaginary parts of stack arguments are supposed
4787 to be contiguous and there should be an extra word of padding
4790 This has two problems. First, it makes it impossible to use a
4791 single "void *" va_list type, since register and stack arguments
4792 are passed differently. (At the time of writing, MIPSpro cannot
4793 handle complex float varargs correctly.) Second, it's unclear
4794 what should happen when there is only one register free.
4796 For now, we assume that named complex floats should go into FPRs
4797 if there are two FPRs free, otherwise they should be passed in the
4798 same way as a struct containing two floats. */
4800 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4801 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
4803 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
4804 info->fpr_p = false;
4814 /* See whether the argument has doubleword alignment. */
4815 doubleword_aligned_p = (mips_function_arg_boundary (mode, type)
4818 /* Set REG_OFFSET to the register count we're interested in.
4819 The EABI allocates the floating-point registers separately,
4820 but the other ABIs allocate them like integer registers. */
4821 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
4825 /* Advance to an even register if the argument is doubleword-aligned. */
4826 if (doubleword_aligned_p)
4827 info->reg_offset += info->reg_offset & 1;
4829 /* Work out the offset of a stack argument. */
4830 info->stack_offset = cum->stack_words;
4831 if (doubleword_aligned_p)
4832 info->stack_offset += info->stack_offset & 1;
4834 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
4836 /* Partition the argument between registers and stack. */
4837 info->reg_words = MIN (num_words, max_regs);
4838 info->stack_words = num_words - info->reg_words;
4841 /* INFO describes a register argument that has the normal format for the
4842 argument's mode. Return the register it uses, assuming that FPRs are
4843 available if HARD_FLOAT_P. */
4846 mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p)
4848 if (!info->fpr_p || !hard_float_p)
4849 return GP_ARG_FIRST + info->reg_offset;
4850 else if (mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info->reg_offset > 0)
4851 /* In o32, the second argument is always passed in $f14
4852 for TARGET_DOUBLE_FLOAT, regardless of whether the
4853 first argument was a word or doubleword. */
4854 return FP_ARG_FIRST + 2;
4856 return FP_ARG_FIRST + info->reg_offset;
4859 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
4862 mips_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED)
4864 return !TARGET_OLDABI;
4867 /* Implement TARGET_FUNCTION_ARG. */
4870 mips_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
4871 const_tree type, bool named)
4873 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
4874 struct mips_arg_info info;
4876 /* We will be called with a mode of VOIDmode after the last argument
4877 has been seen. Whatever we return will be passed to the call expander.
4878 If we need a MIPS16 fp_code, return a REG with the code stored as
4880 if (mode == VOIDmode)
4882 if (TARGET_MIPS16 && cum->fp_code != 0)
4883 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
4888 mips_get_arg_info (&info, cum, mode, type, named);
4890 /* Return straight away if the whole argument is passed on the stack. */
4891 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
4894 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
4895 contains a double in its entirety, then that 64-bit chunk is passed
4896 in a floating-point register. */
4898 && TARGET_HARD_FLOAT
4901 && TREE_CODE (type) == RECORD_TYPE
4902 && TYPE_SIZE_UNIT (type)
4903 && host_integerp (TYPE_SIZE_UNIT (type), 1))
4907 /* First check to see if there is any such field. */
4908 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
4909 if (TREE_CODE (field) == FIELD_DECL
4910 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
4911 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
4912 && host_integerp (bit_position (field), 0)
4913 && int_bit_position (field) % BITS_PER_WORD == 0)
4918 /* Now handle the special case by returning a PARALLEL
4919 indicating where each 64-bit chunk goes. INFO.REG_WORDS
4920 chunks are passed in registers. */
4922 HOST_WIDE_INT bitpos;
4925 /* assign_parms checks the mode of ENTRY_PARM, so we must
4926 use the actual mode here. */
4927 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
4930 field = TYPE_FIELDS (type);
4931 for (i = 0; i < info.reg_words; i++)
4935 for (; field; field = DECL_CHAIN (field))
4936 if (TREE_CODE (field) == FIELD_DECL
4937 && int_bit_position (field) >= bitpos)
4941 && int_bit_position (field) == bitpos
4942 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
4943 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
4944 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
4946 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
4949 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4950 GEN_INT (bitpos / BITS_PER_UNIT));
4952 bitpos += BITS_PER_WORD;
4958 /* Handle the n32/n64 conventions for passing complex floating-point
4959 arguments in FPR pairs. The real part goes in the lower register
4960 and the imaginary part goes in the upper register. */
4963 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4966 enum machine_mode inner;
4969 inner = GET_MODE_INNER (mode);
4970 regno = FP_ARG_FIRST + info.reg_offset;
4971 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
4973 /* Real part in registers, imaginary part on stack. */
4974 gcc_assert (info.stack_words == info.reg_words);
4975 return gen_rtx_REG (inner, regno);
4979 gcc_assert (info.stack_words == 0);
4980 real = gen_rtx_EXPR_LIST (VOIDmode,
4981 gen_rtx_REG (inner, regno),
4983 imag = gen_rtx_EXPR_LIST (VOIDmode,
4985 regno + info.reg_words / 2),
4986 GEN_INT (GET_MODE_SIZE (inner)));
4987 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
4991 return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT));
4994 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
4997 mips_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
4998 const_tree type, bool named)
5000 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
5001 struct mips_arg_info info;
5003 mips_get_arg_info (&info, cum, mode, type, named);
5006 cum->gp_reg_found = true;
5008 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
5009 an explanation of what this code does. It assumes that we're using
5010 either the o32 or the o64 ABI, both of which pass at most 2 arguments
5012 if (cum->arg_number < 2 && info.fpr_p)
5013 cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2);
5015 /* Advance the register count. This has the effect of setting
5016 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
5017 argument required us to skip the final GPR and pass the whole
5018 argument on the stack. */
5019 if (mips_abi != ABI_EABI || !info.fpr_p)
5020 cum->num_gprs = info.reg_offset + info.reg_words;
5021 else if (info.reg_words > 0)
5022 cum->num_fprs += MAX_FPRS_PER_FMT;
5024 /* Advance the stack word count. */
5025 if (info.stack_words > 0)
5026 cum->stack_words = info.stack_offset + info.stack_words;
5031 /* Implement TARGET_ARG_PARTIAL_BYTES. */
5034 mips_arg_partial_bytes (cumulative_args_t cum,
5035 enum machine_mode mode, tree type, bool named)
5037 struct mips_arg_info info;
5039 mips_get_arg_info (&info, get_cumulative_args (cum), mode, type, named);
5040 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
5043 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
5044 least PARM_BOUNDARY bits of alignment, but will be given anything up
5045 to STACK_BOUNDARY bits if the type requires it. */
5048 mips_function_arg_boundary (enum machine_mode mode, const_tree type)
5050 unsigned int alignment;
5052 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
5053 if (alignment < PARM_BOUNDARY)
5054 alignment = PARM_BOUNDARY;
5055 if (alignment > STACK_BOUNDARY)
5056 alignment = STACK_BOUNDARY;
5060 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
5061 upward rather than downward. In other words, return true if the
5062 first byte of the stack slot has useful data, false if the last
5066 mips_pad_arg_upward (enum machine_mode mode, const_tree type)
5068 /* On little-endian targets, the first byte of every stack argument
5069 is passed in the first byte of the stack slot. */
5070 if (!BYTES_BIG_ENDIAN)
5073 /* Otherwise, integral types are padded downward: the last byte of a
5074 stack argument is passed in the last byte of the stack slot. */
5076 ? (INTEGRAL_TYPE_P (type)
5077 || POINTER_TYPE_P (type)
5078 || FIXED_POINT_TYPE_P (type))
5079 : (SCALAR_INT_MODE_P (mode)
5080 || ALL_SCALAR_FIXED_POINT_MODE_P (mode)))
5083 /* Big-endian o64 pads floating-point arguments downward. */
5084 if (mips_abi == ABI_O64)
5085 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
5088 /* Other types are padded upward for o32, o64, n32 and n64. */
5089 if (mips_abi != ABI_EABI)
5092 /* Arguments smaller than a stack slot are padded downward. */
5093 if (mode != BLKmode)
5094 return GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY;
5096 return int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT);
5099 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
5100 if the least significant byte of the register has useful data. Return
5101 the opposite if the most significant byte does. */
5104 mips_pad_reg_upward (enum machine_mode mode, tree type)
5106 /* No shifting is required for floating-point arguments. */
5107 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
5108 return !BYTES_BIG_ENDIAN;
5110 /* Otherwise, apply the same padding to register arguments as we do
5111 to stack arguments. */
5112 return mips_pad_arg_upward (mode, type);
5115 /* Return nonzero when an argument must be passed by reference. */
5118 mips_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
5119 enum machine_mode mode, const_tree type,
5120 bool named ATTRIBUTE_UNUSED)
5122 if (mips_abi == ABI_EABI)
5126 /* ??? How should SCmode be handled? */
5127 if (mode == DImode || mode == DFmode
5128 || mode == DQmode || mode == UDQmode
5129 || mode == DAmode || mode == UDAmode)
5132 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
5133 return size == -1 || size > UNITS_PER_WORD;
5137 /* If we have a variable-sized parameter, we have no choice. */
5138 return targetm.calls.must_pass_in_stack (mode, type);
5142 /* Implement TARGET_CALLEE_COPIES. */
5145 mips_callee_copies (cumulative_args_t cum ATTRIBUTE_UNUSED,
5146 enum machine_mode mode ATTRIBUTE_UNUSED,
5147 const_tree type ATTRIBUTE_UNUSED, bool named)
5149 return mips_abi == ABI_EABI && named;
5152 /* See whether VALTYPE is a record whose fields should be returned in
5153 floating-point registers. If so, return the number of fields and
5154 list them in FIELDS (which should have two elements). Return 0
5157 For n32 & n64, a structure with one or two fields is returned in
5158 floating-point registers as long as every field has a floating-point
5162 mips_fpr_return_fields (const_tree valtype, tree *fields)
5170 if (TREE_CODE (valtype) != RECORD_TYPE)
5174 for (field = TYPE_FIELDS (valtype); field != 0; field = DECL_CHAIN (field))
5176 if (TREE_CODE (field) != FIELD_DECL)
5179 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)))
5185 fields[i++] = field;
5190 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
5191 a value in the most significant part of $2/$3 if:
5193 - the target is big-endian;
5195 - the value has a structure or union type (we generalize this to
5196 cover aggregates from other languages too); and
5198 - the structure is not returned in floating-point registers. */
5201 mips_return_in_msb (const_tree valtype)
5205 return (TARGET_NEWABI
5206 && TARGET_BIG_ENDIAN
5207 && AGGREGATE_TYPE_P (valtype)
5208 && mips_fpr_return_fields (valtype, fields) == 0);
5211 /* Return true if the function return value MODE will get returned in a
5212 floating-point register. */
5215 mips_return_mode_in_fpr_p (enum machine_mode mode)
5217 return ((GET_MODE_CLASS (mode) == MODE_FLOAT
5219 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5220 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE);
5223 /* Return the representation of an FPR return register when the
5224 value being returned in FP_RETURN has mode VALUE_MODE and the
5225 return type itself has mode TYPE_MODE. On NewABI targets,
5226 the two modes may be different for structures like:
5228 struct __attribute__((packed)) foo { float f; }
5230 where we return the SFmode value of "f" in FP_RETURN, but where
5231 the structure itself has mode BLKmode. */
5234 mips_return_fpr_single (enum machine_mode type_mode,
5235 enum machine_mode value_mode)
5239 x = gen_rtx_REG (value_mode, FP_RETURN);
5240 if (type_mode != value_mode)
5242 x = gen_rtx_EXPR_LIST (VOIDmode, x, const0_rtx);
5243 x = gen_rtx_PARALLEL (type_mode, gen_rtvec (1, x));
5248 /* Return a composite value in a pair of floating-point registers.
5249 MODE1 and OFFSET1 are the mode and byte offset for the first value,
5250 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
5253 For n32 & n64, $f0 always holds the first value and $f2 the second.
5254 Otherwise the values are packed together as closely as possible. */
5257 mips_return_fpr_pair (enum machine_mode mode,
5258 enum machine_mode mode1, HOST_WIDE_INT offset1,
5259 enum machine_mode mode2, HOST_WIDE_INT offset2)
5263 inc = (TARGET_NEWABI ? 2 : MAX_FPRS_PER_FMT);
5264 return gen_rtx_PARALLEL
5267 gen_rtx_EXPR_LIST (VOIDmode,
5268 gen_rtx_REG (mode1, FP_RETURN),
5270 gen_rtx_EXPR_LIST (VOIDmode,
5271 gen_rtx_REG (mode2, FP_RETURN + inc),
5272 GEN_INT (offset2))));
5276 /* Implement TARGET_FUNCTION_VALUE and TARGET_LIBCALL_VALUE.
5277 For normal calls, VALTYPE is the return type and MODE is VOIDmode.
5278 For libcalls, VALTYPE is null and MODE is the mode of the return value. */
5281 mips_function_value_1 (const_tree valtype, const_tree fn_decl_or_type,
5282 enum machine_mode mode)
5290 if (fn_decl_or_type && DECL_P (fn_decl_or_type))
5291 func = fn_decl_or_type;
5295 mode = TYPE_MODE (valtype);
5296 unsigned_p = TYPE_UNSIGNED (valtype);
5298 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
5299 return values, promote the mode here too. */
5300 mode = promote_function_mode (valtype, mode, &unsigned_p, func, 1);
5302 /* Handle structures whose fields are returned in $f0/$f2. */
5303 switch (mips_fpr_return_fields (valtype, fields))
5306 return mips_return_fpr_single (mode,
5307 TYPE_MODE (TREE_TYPE (fields[0])));
5310 return mips_return_fpr_pair (mode,
5311 TYPE_MODE (TREE_TYPE (fields[0])),
5312 int_byte_position (fields[0]),
5313 TYPE_MODE (TREE_TYPE (fields[1])),
5314 int_byte_position (fields[1]));
5317 /* If a value is passed in the most significant part of a register, see
5318 whether we have to round the mode up to a whole number of words. */
5319 if (mips_return_in_msb (valtype))
5321 HOST_WIDE_INT size = int_size_in_bytes (valtype);
5322 if (size % UNITS_PER_WORD != 0)
5324 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
5325 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
5329 /* For EABI, the class of return register depends entirely on MODE.
5330 For example, "struct { some_type x; }" and "union { some_type x; }"
5331 are returned in the same way as a bare "some_type" would be.
5332 Other ABIs only use FPRs for scalar, complex or vector types. */
5333 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
5334 return gen_rtx_REG (mode, GP_RETURN);
5339 /* Handle long doubles for n32 & n64. */
5341 return mips_return_fpr_pair (mode,
5343 DImode, GET_MODE_SIZE (mode) / 2);
5345 if (mips_return_mode_in_fpr_p (mode))
5347 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5348 return mips_return_fpr_pair (mode,
5349 GET_MODE_INNER (mode), 0,
5350 GET_MODE_INNER (mode),
5351 GET_MODE_SIZE (mode) / 2);
5353 return gen_rtx_REG (mode, FP_RETURN);
5357 return gen_rtx_REG (mode, GP_RETURN);
5360 /* Implement TARGET_FUNCTION_VALUE. */
5363 mips_function_value (const_tree valtype, const_tree fn_decl_or_type,
5364 bool outgoing ATTRIBUTE_UNUSED)
5366 return mips_function_value_1 (valtype, fn_decl_or_type, VOIDmode);
5369 /* Implement TARGET_LIBCALL_VALUE. */
5372 mips_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
5374 return mips_function_value_1 (NULL_TREE, NULL_TREE, mode);
5377 /* Implement TARGET_FUNCTION_VALUE_REGNO_P.
5379 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
5380 Currently, R2 and F0 are only implemented here (C has no complex type). */
5383 mips_function_value_regno_p (const unsigned int regno)
5385 if (regno == GP_RETURN
5386 || regno == FP_RETURN
5387 || (LONG_DOUBLE_TYPE_SIZE == 128
5388 && FP_RETURN != GP_RETURN
5389 && regno == FP_RETURN + 2))
5395 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
5396 all BLKmode objects are returned in memory. Under the n32, n64
5397 and embedded ABIs, small structures are returned in a register.
5398 Objects with varying size must still be returned in memory, of
5402 mips_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
5404 return (TARGET_OLDABI
5405 ? TYPE_MODE (type) == BLKmode
5406 : !IN_RANGE (int_size_in_bytes (type), 0, 2 * UNITS_PER_WORD));
5409 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
5412 mips_setup_incoming_varargs (cumulative_args_t cum, enum machine_mode mode,
5413 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5416 CUMULATIVE_ARGS local_cum;
5417 int gp_saved, fp_saved;
5419 /* The caller has advanced CUM up to, but not beyond, the last named
5420 argument. Advance a local copy of CUM past the last "real" named
5421 argument, to find out how many registers are left over. */
5422 local_cum = *get_cumulative_args (cum);
5423 mips_function_arg_advance (pack_cumulative_args (&local_cum), mode, type,
5426 /* Found out how many registers we need to save. */
5427 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
5428 fp_saved = (EABI_FLOAT_VARARGS_P
5429 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
5438 ptr = plus_constant (Pmode, virtual_incoming_args_rtx,
5439 REG_PARM_STACK_SPACE (cfun->decl)
5440 - gp_saved * UNITS_PER_WORD);
5441 mem = gen_frame_mem (BLKmode, ptr);
5442 set_mem_alias_set (mem, get_varargs_alias_set ());
5444 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
5449 /* We can't use move_block_from_reg, because it will use
5451 enum machine_mode mode;
5454 /* Set OFF to the offset from virtual_incoming_args_rtx of
5455 the first float register. The FP save area lies below
5456 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
5457 off = (-gp_saved * UNITS_PER_WORD) & -UNITS_PER_FPVALUE;
5458 off -= fp_saved * UNITS_PER_FPREG;
5460 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
5462 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS;
5463 i += MAX_FPRS_PER_FMT)
5467 ptr = plus_constant (Pmode, virtual_incoming_args_rtx, off);
5468 mem = gen_frame_mem (mode, ptr);
5469 set_mem_alias_set (mem, get_varargs_alias_set ());
5470 mips_emit_move (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
5471 off += UNITS_PER_HWFPVALUE;
5475 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
5476 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
5477 + fp_saved * UNITS_PER_FPREG);
5480 /* Implement TARGET_BUILTIN_VA_LIST. */
5483 mips_build_builtin_va_list (void)
5485 if (EABI_FLOAT_VARARGS_P)
5487 /* We keep 3 pointers, and two offsets.
5489 Two pointers are to the overflow area, which starts at the CFA.
5490 One of these is constant, for addressing into the GPR save area
5491 below it. The other is advanced up the stack through the
5494 The third pointer is to the bottom of the GPR save area.
5495 Since the FPR save area is just below it, we can address
5496 FPR slots off this pointer.
5498 We also keep two one-byte offsets, which are to be subtracted
5499 from the constant pointers to yield addresses in the GPR and
5500 FPR save areas. These are downcounted as float or non-float
5501 arguments are used, and when they get to zero, the argument
5502 must be obtained from the overflow region. */
5503 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
5506 record = lang_hooks.types.make_type (RECORD_TYPE);
5508 f_ovfl = build_decl (BUILTINS_LOCATION,
5509 FIELD_DECL, get_identifier ("__overflow_argptr"),
5511 f_gtop = build_decl (BUILTINS_LOCATION,
5512 FIELD_DECL, get_identifier ("__gpr_top"),
5514 f_ftop = build_decl (BUILTINS_LOCATION,
5515 FIELD_DECL, get_identifier ("__fpr_top"),
5517 f_goff = build_decl (BUILTINS_LOCATION,
5518 FIELD_DECL, get_identifier ("__gpr_offset"),
5519 unsigned_char_type_node);
5520 f_foff = build_decl (BUILTINS_LOCATION,
5521 FIELD_DECL, get_identifier ("__fpr_offset"),
5522 unsigned_char_type_node);
5523 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
5524 warn on every user file. */
5525 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
5526 array = build_array_type (unsigned_char_type_node,
5527 build_index_type (index));
5528 f_res = build_decl (BUILTINS_LOCATION,
5529 FIELD_DECL, get_identifier ("__reserved"), array);
5531 DECL_FIELD_CONTEXT (f_ovfl) = record;
5532 DECL_FIELD_CONTEXT (f_gtop) = record;
5533 DECL_FIELD_CONTEXT (f_ftop) = record;
5534 DECL_FIELD_CONTEXT (f_goff) = record;
5535 DECL_FIELD_CONTEXT (f_foff) = record;
5536 DECL_FIELD_CONTEXT (f_res) = record;
5538 TYPE_FIELDS (record) = f_ovfl;
5539 DECL_CHAIN (f_ovfl) = f_gtop;
5540 DECL_CHAIN (f_gtop) = f_ftop;
5541 DECL_CHAIN (f_ftop) = f_goff;
5542 DECL_CHAIN (f_goff) = f_foff;
5543 DECL_CHAIN (f_foff) = f_res;
5545 layout_type (record);
5549 /* Otherwise, we use 'void *'. */
5550 return ptr_type_node;
5553 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
5556 mips_va_start (tree valist, rtx nextarg)
5558 if (EABI_FLOAT_VARARGS_P)
5560 const CUMULATIVE_ARGS *cum;
5561 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5562 tree ovfl, gtop, ftop, goff, foff;
5564 int gpr_save_area_size;
5565 int fpr_save_area_size;
5568 cum = &crtl->args.info;
5570 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
5572 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
5574 f_ovfl = TYPE_FIELDS (va_list_type_node);
5575 f_gtop = DECL_CHAIN (f_ovfl);
5576 f_ftop = DECL_CHAIN (f_gtop);
5577 f_goff = DECL_CHAIN (f_ftop);
5578 f_foff = DECL_CHAIN (f_goff);
5580 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5582 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
5584 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
5586 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
5588 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
5591 /* Emit code to initialize OVFL, which points to the next varargs
5592 stack argument. CUM->STACK_WORDS gives the number of stack
5593 words used by named arguments. */
5594 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
5595 if (cum->stack_words > 0)
5596 t = fold_build_pointer_plus_hwi (t, cum->stack_words * UNITS_PER_WORD);
5597 t = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
5598 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5600 /* Emit code to initialize GTOP, the top of the GPR save area. */
5601 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
5602 t = build2 (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
5603 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5605 /* Emit code to initialize FTOP, the top of the FPR save area.
5606 This address is gpr_save_area_bytes below GTOP, rounded
5607 down to the next fp-aligned boundary. */
5608 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
5609 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
5610 fpr_offset &= -UNITS_PER_FPVALUE;
5612 t = fold_build_pointer_plus_hwi (t, -fpr_offset);
5613 t = build2 (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
5614 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5616 /* Emit code to initialize GOFF, the offset from GTOP of the
5617 next GPR argument. */
5618 t = build2 (MODIFY_EXPR, TREE_TYPE (goff), goff,
5619 build_int_cst (TREE_TYPE (goff), gpr_save_area_size));
5620 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5622 /* Likewise emit code to initialize FOFF, the offset from FTOP
5623 of the next FPR argument. */
5624 t = build2 (MODIFY_EXPR, TREE_TYPE (foff), foff,
5625 build_int_cst (TREE_TYPE (foff), fpr_save_area_size));
5626 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5630 nextarg = plus_constant (Pmode, nextarg, -cfun->machine->varargs_size);
5631 std_expand_builtin_va_start (valist, nextarg);
5635 /* Like std_gimplify_va_arg_expr, but apply alignment to zero-sized
5639 mips_std_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
5642 tree addr, t, type_size, rounded_size, valist_tmp;
5643 unsigned HOST_WIDE_INT align, boundary;
5646 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, false);
5648 type = build_pointer_type (type);
5650 align = PARM_BOUNDARY / BITS_PER_UNIT;
5651 boundary = targetm.calls.function_arg_boundary (TYPE_MODE (type), type);
5653 /* When we align parameter on stack for caller, if the parameter
5654 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
5655 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
5656 here with caller. */
5657 if (boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
5658 boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
5660 boundary /= BITS_PER_UNIT;
5662 /* Hoist the valist value into a temporary for the moment. */
5663 valist_tmp = get_initialized_tmp_var (valist, pre_p, NULL);
5665 /* va_list pointer is aligned to PARM_BOUNDARY. If argument actually
5666 requires greater alignment, we must perform dynamic alignment. */
5667 if (boundary > align)
5669 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
5670 fold_build_pointer_plus_hwi (valist_tmp, boundary - 1));
5671 gimplify_and_add (t, pre_p);
5673 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
5674 fold_build2 (BIT_AND_EXPR, TREE_TYPE (valist),
5676 build_int_cst (TREE_TYPE (valist), -boundary)));
5677 gimplify_and_add (t, pre_p);
5682 /* If the actual alignment is less than the alignment of the type,
5683 adjust the type accordingly so that we don't assume strict alignment
5684 when dereferencing the pointer. */
5685 boundary *= BITS_PER_UNIT;
5686 if (boundary < TYPE_ALIGN (type))
5688 type = build_variant_type_copy (type);
5689 TYPE_ALIGN (type) = boundary;
5692 /* Compute the rounded size of the type. */
5693 type_size = size_in_bytes (type);
5694 rounded_size = round_up (type_size, align);
5696 /* Reduce rounded_size so it's sharable with the postqueue. */
5697 gimplify_expr (&rounded_size, pre_p, post_p, is_gimple_val, fb_rvalue);
5701 if (PAD_VARARGS_DOWN && !integer_zerop (rounded_size))
5703 /* Small args are padded downward. */
5704 t = fold_build2_loc (input_location, GT_EXPR, sizetype,
5705 rounded_size, size_int (align));
5706 t = fold_build3 (COND_EXPR, sizetype, t, size_zero_node,
5707 size_binop (MINUS_EXPR, rounded_size, type_size));
5708 addr = fold_build_pointer_plus (addr, t);
5711 /* Compute new value for AP. */
5712 t = fold_build_pointer_plus (valist_tmp, rounded_size);
5713 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
5714 gimplify_and_add (t, pre_p);
5716 addr = fold_convert (build_pointer_type (type), addr);
5719 addr = build_va_arg_indirect_ref (addr);
5721 return build_va_arg_indirect_ref (addr);
5724 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
5727 mips_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
5733 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
5735 type = build_pointer_type (type);
5737 if (!EABI_FLOAT_VARARGS_P)
5738 addr = mips_std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5741 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5742 tree ovfl, top, off, align;
5743 HOST_WIDE_INT size, rsize, osize;
5746 f_ovfl = TYPE_FIELDS (va_list_type_node);
5747 f_gtop = DECL_CHAIN (f_ovfl);
5748 f_ftop = DECL_CHAIN (f_gtop);
5749 f_goff = DECL_CHAIN (f_ftop);
5750 f_foff = DECL_CHAIN (f_goff);
5754 TOP be the top of the GPR or FPR save area;
5755 OFF be the offset from TOP of the next register;
5756 ADDR_RTX be the address of the argument;
5757 SIZE be the number of bytes in the argument type;
5758 RSIZE be the number of bytes used to store the argument
5759 when it's in the register save area; and
5760 OSIZE be the number of bytes used to store it when it's
5761 in the stack overflow area.
5763 The code we want is:
5765 1: off &= -rsize; // round down
5768 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
5773 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
5774 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
5778 [1] and [9] can sometimes be optimized away. */
5780 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5782 size = int_size_in_bytes (type);
5784 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
5785 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
5787 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop),
5788 unshare_expr (valist), f_ftop, NULL_TREE);
5789 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff),
5790 unshare_expr (valist), f_foff, NULL_TREE);
5792 /* When va_start saves FPR arguments to the stack, each slot
5793 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
5794 argument's precision. */
5795 rsize = UNITS_PER_HWFPVALUE;
5797 /* Overflow arguments are padded to UNITS_PER_WORD bytes
5798 (= PARM_BOUNDARY bits). This can be different from RSIZE
5801 (1) On 32-bit targets when TYPE is a structure such as:
5803 struct s { float f; };
5805 Such structures are passed in paired FPRs, so RSIZE
5806 will be 8 bytes. However, the structure only takes
5807 up 4 bytes of memory, so OSIZE will only be 4.
5809 (2) In combinations such as -mgp64 -msingle-float
5810 -fshort-double. Doubles passed in registers will then take
5811 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
5812 stack take up UNITS_PER_WORD bytes. */
5813 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
5817 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop),
5818 unshare_expr (valist), f_gtop, NULL_TREE);
5819 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff),
5820 unshare_expr (valist), f_goff, NULL_TREE);
5821 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
5822 if (rsize > UNITS_PER_WORD)
5824 /* [1] Emit code for: off &= -rsize. */
5825 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), unshare_expr (off),
5826 build_int_cst (TREE_TYPE (off), -rsize));
5827 gimplify_assign (unshare_expr (off), t, pre_p);
5832 /* [2] Emit code to branch if off == 0. */
5833 t = build2 (NE_EXPR, boolean_type_node, unshare_expr (off),
5834 build_int_cst (TREE_TYPE (off), 0));
5835 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
5837 /* [5] Emit code for: off -= rsize. We do this as a form of
5838 post-decrement not available to C. */
5839 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
5840 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
5842 /* [4] Emit code for:
5843 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
5844 t = fold_convert (sizetype, t);
5845 t = fold_build1 (NEGATE_EXPR, sizetype, t);
5846 t = fold_build_pointer_plus (top, t);
5847 if (BYTES_BIG_ENDIAN && rsize > size)
5848 t = fold_build_pointer_plus_hwi (t, rsize - size);
5849 COND_EXPR_THEN (addr) = t;
5851 if (osize > UNITS_PER_WORD)
5853 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
5854 t = fold_build_pointer_plus_hwi (unshare_expr (ovfl), osize - 1);
5855 u = build_int_cst (TREE_TYPE (t), -osize);
5856 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t, u);
5857 align = build2 (MODIFY_EXPR, TREE_TYPE (ovfl),
5858 unshare_expr (ovfl), t);
5863 /* [10, 11] Emit code for:
5864 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
5866 u = fold_convert (TREE_TYPE (ovfl), build_int_cst (NULL_TREE, osize));
5867 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
5868 if (BYTES_BIG_ENDIAN && osize > size)
5869 t = fold_build_pointer_plus_hwi (t, osize - size);
5871 /* String [9] and [10, 11] together. */
5873 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
5874 COND_EXPR_ELSE (addr) = t;
5876 addr = fold_convert (build_pointer_type (type), addr);
5877 addr = build_va_arg_indirect_ref (addr);
5881 addr = build_va_arg_indirect_ref (addr);
5886 /* Declare a unique, locally-binding function called NAME, then start
5890 mips_start_unique_function (const char *name)
5894 decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
5895 get_identifier (name),
5896 build_function_type_list (void_type_node, NULL_TREE));
5897 DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
5898 NULL_TREE, void_type_node);
5899 TREE_PUBLIC (decl) = 1;
5900 TREE_STATIC (decl) = 1;
5902 DECL_COMDAT_GROUP (decl) = DECL_ASSEMBLER_NAME (decl);
5904 targetm.asm_out.unique_section (decl, 0);
5905 switch_to_section (get_named_section (decl, NULL, 0));
5907 targetm.asm_out.globalize_label (asm_out_file, name);
5908 fputs ("\t.hidden\t", asm_out_file);
5909 assemble_name (asm_out_file, name);
5910 putc ('\n', asm_out_file);
5913 /* Start a definition of function NAME. MIPS16_P indicates whether the
5914 function contains MIPS16 code. */
5917 mips_start_function_definition (const char *name, bool mips16_p)
5920 fprintf (asm_out_file, "\t.set\tmips16\n");
5922 fprintf (asm_out_file, "\t.set\tnomips16\n");
5924 if (!flag_inhibit_size_directive)
5926 fputs ("\t.ent\t", asm_out_file);
5927 assemble_name (asm_out_file, name);
5928 fputs ("\n", asm_out_file);
5931 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, name, "function");
5933 /* Start the definition proper. */
5934 assemble_name (asm_out_file, name);
5935 fputs (":\n", asm_out_file);
5938 /* End a function definition started by mips_start_function_definition. */
5941 mips_end_function_definition (const char *name)
5943 if (!flag_inhibit_size_directive)
5945 fputs ("\t.end\t", asm_out_file);
5946 assemble_name (asm_out_file, name);
5947 fputs ("\n", asm_out_file);
5951 /* Output a definition of the __mips16_rdhwr function. */
5954 mips_output_mips16_rdhwr (void)
5958 name = "__mips16_rdhwr";
5959 mips_start_unique_function (name);
5960 mips_start_function_definition (name, false);
5961 fprintf (asm_out_file,
5963 "\t.set\tmips32r2\n"
5964 "\t.set\tnoreorder\n"
5968 mips_end_function_definition (name);
5971 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
5974 mips_ok_for_lazy_binding_p (rtx x)
5976 return (TARGET_USE_GOT
5977 && GET_CODE (x) == SYMBOL_REF
5978 && !SYMBOL_REF_BIND_NOW_P (x)
5979 && !mips_symbol_binds_local_p (x));
5982 /* Load function address ADDR into register DEST. TYPE is as for
5983 mips_expand_call. Return true if we used an explicit lazy-binding
5987 mips_load_call_address (enum mips_call_type type, rtx dest, rtx addr)
5989 /* If we're generating PIC, and this call is to a global function,
5990 try to allow its address to be resolved lazily. This isn't
5991 possible for sibcalls when $gp is call-saved because the value
5992 of $gp on entry to the stub would be our caller's gp, not ours. */
5993 if (TARGET_EXPLICIT_RELOCS
5994 && !(type == MIPS_CALL_SIBCALL && TARGET_CALL_SAVED_GP)
5995 && mips_ok_for_lazy_binding_p (addr))
5997 addr = mips_got_load (dest, addr, SYMBOL_GOTOFF_CALL);
5998 emit_insn (gen_rtx_SET (VOIDmode, dest, addr));
6003 mips_emit_move (dest, addr);
6008 /* Each locally-defined hard-float MIPS16 function has a local symbol
6009 associated with it. This hash table maps the function symbol (FUNC)
6010 to the local symbol (LOCAL). */
6011 struct GTY(()) mips16_local_alias {
6015 static GTY ((param_is (struct mips16_local_alias))) htab_t mips16_local_aliases;
6017 /* Hash table callbacks for mips16_local_aliases. */
6020 mips16_local_aliases_hash (const void *entry)
6022 const struct mips16_local_alias *alias;
6024 alias = (const struct mips16_local_alias *) entry;
6025 return htab_hash_string (XSTR (alias->func, 0));
6029 mips16_local_aliases_eq (const void *entry1, const void *entry2)
6031 const struct mips16_local_alias *alias1, *alias2;
6033 alias1 = (const struct mips16_local_alias *) entry1;
6034 alias2 = (const struct mips16_local_alias *) entry2;
6035 return rtx_equal_p (alias1->func, alias2->func);
6038 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
6039 Return a local alias for it, creating a new one if necessary. */
6042 mips16_local_alias (rtx func)
6044 struct mips16_local_alias *alias, tmp_alias;
6047 /* Create the hash table if this is the first call. */
6048 if (mips16_local_aliases == NULL)
6049 mips16_local_aliases = htab_create_ggc (37, mips16_local_aliases_hash,
6050 mips16_local_aliases_eq, NULL);
6052 /* Look up the function symbol, creating a new entry if need be. */
6053 tmp_alias.func = func;
6054 slot = htab_find_slot (mips16_local_aliases, &tmp_alias, INSERT);
6055 gcc_assert (slot != NULL);
6057 alias = (struct mips16_local_alias *) *slot;
6060 const char *func_name, *local_name;
6063 /* Create a new SYMBOL_REF for the local symbol. The choice of
6064 __fn_local_* is based on the __fn_stub_* names that we've
6065 traditionally used for the non-MIPS16 stub. */
6066 func_name = targetm.strip_name_encoding (XSTR (func, 0));
6067 local_name = ACONCAT (("__fn_local_", func_name, NULL));
6068 local = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (local_name));
6069 SYMBOL_REF_FLAGS (local) = SYMBOL_REF_FLAGS (func) | SYMBOL_FLAG_LOCAL;
6071 /* Create a new structure to represent the mapping. */
6072 alias = ggc_alloc_mips16_local_alias ();
6074 alias->local = local;
6077 return alias->local;
6080 /* A chained list of functions for which mips16_build_call_stub has already
6081 generated a stub. NAME is the name of the function and FP_RET_P is true
6082 if the function returns a value in floating-point registers. */
6083 struct mips16_stub {
6084 struct mips16_stub *next;
6088 static struct mips16_stub *mips16_stubs;
6090 /* Return the two-character string that identifies floating-point
6091 return mode MODE in the name of a MIPS16 function stub. */
6094 mips16_call_stub_mode_suffix (enum machine_mode mode)
6098 else if (mode == DFmode)
6100 else if (mode == SCmode)
6102 else if (mode == DCmode)
6104 else if (mode == V2SFmode)
6110 /* Write instructions to move a 32-bit value between general register
6111 GPREG and floating-point register FPREG. DIRECTION is 't' to move
6112 from GPREG to FPREG and 'f' to move in the opposite direction. */
6115 mips_output_32bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
6117 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6118 reg_names[gpreg], reg_names[fpreg]);
6121 /* Likewise for 64-bit values. */
6124 mips_output_64bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
6127 fprintf (asm_out_file, "\tdm%cc1\t%s,%s\n", direction,
6128 reg_names[gpreg], reg_names[fpreg]);
6129 else if (TARGET_FLOAT64)
6131 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6132 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
6133 fprintf (asm_out_file, "\tm%chc1\t%s,%s\n", direction,
6134 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg]);
6138 /* Move the least-significant word. */
6139 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6140 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
6141 /* ...then the most significant word. */
6142 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6143 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg + 1]);
6147 /* Write out code to move floating-point arguments into or out of
6148 general registers. FP_CODE is the code describing which arguments
6149 are present (see the comment above the definition of CUMULATIVE_ARGS
6150 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
6153 mips_output_args_xfer (int fp_code, char direction)
6155 unsigned int gparg, fparg, f;
6156 CUMULATIVE_ARGS cum;
6158 /* This code only works for o32 and o64. */
6159 gcc_assert (TARGET_OLDABI);
6161 mips_init_cumulative_args (&cum, NULL);
6163 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
6165 enum machine_mode mode;
6166 struct mips_arg_info info;
6170 else if ((f & 3) == 2)
6175 mips_get_arg_info (&info, &cum, mode, NULL, true);
6176 gparg = mips_arg_regno (&info, false);
6177 fparg = mips_arg_regno (&info, true);
6180 mips_output_32bit_xfer (direction, gparg, fparg);
6182 mips_output_64bit_xfer (direction, gparg, fparg);
6184 mips_function_arg_advance (pack_cumulative_args (&cum), mode, NULL, true);
6188 /* Write a MIPS16 stub for the current function. This stub is used
6189 for functions which take arguments in the floating-point registers.
6190 It is normal-mode code that moves the floating-point arguments
6191 into the general registers and then jumps to the MIPS16 code. */
6194 mips16_build_function_stub (void)
6196 const char *fnname, *alias_name, *separator;
6197 char *secname, *stubname;
6202 /* Create the name of the stub, and its unique section. */
6203 symbol = XEXP (DECL_RTL (current_function_decl), 0);
6204 alias = mips16_local_alias (symbol);
6206 fnname = targetm.strip_name_encoding (XSTR (symbol, 0));
6207 alias_name = targetm.strip_name_encoding (XSTR (alias, 0));
6208 secname = ACONCAT ((".mips16.fn.", fnname, NULL));
6209 stubname = ACONCAT (("__fn_stub_", fnname, NULL));
6211 /* Build a decl for the stub. */
6212 stubdecl = build_decl (BUILTINS_LOCATION,
6213 FUNCTION_DECL, get_identifier (stubname),
6214 build_function_type_list (void_type_node, NULL_TREE));
6215 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
6216 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
6217 RESULT_DECL, NULL_TREE, void_type_node);
6219 /* Output a comment. */
6220 fprintf (asm_out_file, "\t# Stub function for %s (",
6221 current_function_name ());
6223 for (f = (unsigned int) crtl->args.info.fp_code; f != 0; f >>= 2)
6225 fprintf (asm_out_file, "%s%s", separator,
6226 (f & 3) == 1 ? "float" : "double");
6229 fprintf (asm_out_file, ")\n");
6231 /* Start the function definition. */
6232 assemble_start_function (stubdecl, stubname);
6233 mips_start_function_definition (stubname, false);
6235 /* If generating pic2 code, either set up the global pointer or
6237 if (TARGET_ABICALLS_PIC2)
6239 if (TARGET_ABSOLUTE_ABICALLS)
6240 fprintf (asm_out_file, "\t.option\tpic0\n");
6243 output_asm_insn ("%(.cpload\t%^%)", NULL);
6244 /* Emit an R_MIPS_NONE relocation to tell the linker what the
6245 target function is. Use a local GOT access when loading the
6246 symbol, to cut down on the number of unnecessary GOT entries
6247 for stubs that aren't needed. */
6248 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol);
6253 /* Load the address of the MIPS16 function into $25. Do this first so
6254 that targets with coprocessor interlocks can use an MFC1 to fill the
6256 output_asm_insn ("la\t%^,%0", &symbol);
6258 /* Move the arguments from floating-point registers to general registers. */
6259 mips_output_args_xfer (crtl->args.info.fp_code, 'f');
6261 /* Jump to the MIPS16 function. */
6262 output_asm_insn ("jr\t%^", NULL);
6264 if (TARGET_ABICALLS_PIC2 && TARGET_ABSOLUTE_ABICALLS)
6265 fprintf (asm_out_file, "\t.option\tpic2\n");
6267 mips_end_function_definition (stubname);
6269 /* If the linker needs to create a dynamic symbol for the target
6270 function, it will associate the symbol with the stub (which,
6271 unlike the target function, follows the proper calling conventions).
6272 It is therefore useful to have a local alias for the target function,
6273 so that it can still be identified as MIPS16 code. As an optimization,
6274 this symbol can also be used for indirect MIPS16 references from
6275 within this file. */
6276 ASM_OUTPUT_DEF (asm_out_file, alias_name, fnname);
6278 switch_to_section (function_section (current_function_decl));
6281 /* The current function is a MIPS16 function that returns a value in an FPR.
6282 Copy the return value from its soft-float to its hard-float location.
6283 libgcc2 has special non-MIPS16 helper functions for each case. */
6286 mips16_copy_fpr_return_value (void)
6288 rtx fn, insn, retval;
6290 enum machine_mode return_mode;
6293 return_type = DECL_RESULT (current_function_decl);
6294 return_mode = DECL_MODE (return_type);
6296 name = ACONCAT (("__mips16_ret_",
6297 mips16_call_stub_mode_suffix (return_mode),
6299 fn = mips16_stub_function (name);
6301 /* The function takes arguments in $2 (and possibly $3), so calls
6302 to it cannot be lazily bound. */
6303 SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_BIND_NOW;
6305 /* Model the call as something that takes the GPR return value as
6306 argument and returns an "updated" value. */
6307 retval = gen_rtx_REG (return_mode, GP_RETURN);
6308 insn = mips_expand_call (MIPS_CALL_EPILOGUE, retval, fn,
6309 const0_rtx, NULL_RTX, false);
6310 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), retval);
6313 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
6314 RETVAL is the location of the return value, or null if this is
6315 a "call" rather than a "call_value". ARGS_SIZE is the size of the
6316 arguments and FP_CODE is the code built by mips_function_arg;
6317 see the comment before the fp_code field in CUMULATIVE_ARGS for details.
6319 There are three alternatives:
6321 - If a stub was needed, emit the call and return the call insn itself.
6323 - If we can avoid using a stub by redirecting the call, set *FN_PTR
6324 to the new target and return null.
6326 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
6329 A stub is needed for calls to functions that, in normal mode,
6330 receive arguments in FPRs or return values in FPRs. The stub
6331 copies the arguments from their soft-float positions to their
6332 hard-float positions, calls the real function, then copies the
6333 return value from its hard-float position to its soft-float
6336 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
6337 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
6338 automatically redirects the JAL to the stub, otherwise the JAL
6339 continues to call FN directly. */
6342 mips16_build_call_stub (rtx retval, rtx *fn_ptr, rtx args_size, int fp_code)
6346 struct mips16_stub *l;
6349 /* We don't need to do anything if we aren't in MIPS16 mode, or if
6350 we were invoked with the -msoft-float option. */
6351 if (!TARGET_MIPS16 || TARGET_SOFT_FLOAT_ABI)
6354 /* Figure out whether the value might come back in a floating-point
6356 fp_ret_p = retval && mips_return_mode_in_fpr_p (GET_MODE (retval));
6358 /* We don't need to do anything if there were no floating-point
6359 arguments and the value will not be returned in a floating-point
6361 if (fp_code == 0 && !fp_ret_p)
6364 /* We don't need to do anything if this is a call to a special
6365 MIPS16 support function. */
6367 if (mips16_stub_function_p (fn))
6370 /* If we're calling a locally-defined MIPS16 function, we know that
6371 it will return values in both the "soft-float" and "hard-float"
6372 registers. There is no need to use a stub to move the latter
6374 if (fp_code == 0 && mips16_local_function_p (fn))
6377 /* This code will only work for o32 and o64 abis. The other ABI's
6378 require more sophisticated support. */
6379 gcc_assert (TARGET_OLDABI);
6381 /* If we're calling via a function pointer, use one of the magic
6382 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
6383 Each stub expects the function address to arrive in register $2. */
6384 if (GET_CODE (fn) != SYMBOL_REF
6385 || !call_insn_operand (fn, VOIDmode))
6388 rtx stub_fn, insn, addr;
6391 /* If this is a locally-defined and locally-binding function,
6392 avoid the stub by calling the local alias directly. */
6393 if (mips16_local_function_p (fn))
6395 *fn_ptr = mips16_local_alias (fn);
6399 /* Create a SYMBOL_REF for the libgcc.a function. */
6401 sprintf (buf, "__mips16_call_stub_%s_%d",
6402 mips16_call_stub_mode_suffix (GET_MODE (retval)),
6405 sprintf (buf, "__mips16_call_stub_%d", fp_code);
6406 stub_fn = mips16_stub_function (buf);
6408 /* The function uses $2 as an argument, so calls to it
6409 cannot be lazily bound. */
6410 SYMBOL_REF_FLAGS (stub_fn) |= SYMBOL_FLAG_BIND_NOW;
6412 /* Load the target function into $2. */
6413 addr = gen_rtx_REG (Pmode, GP_REG_FIRST + 2);
6414 lazy_p = mips_load_call_address (MIPS_CALL_NORMAL, addr, fn);
6416 /* Emit the call. */
6417 insn = mips_expand_call (MIPS_CALL_NORMAL, retval, stub_fn,
6418 args_size, NULL_RTX, lazy_p);
6420 /* Tell GCC that this call does indeed use the value of $2. */
6421 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), addr);
6423 /* If we are handling a floating-point return value, we need to
6424 save $18 in the function prologue. Putting a note on the
6425 call will mean that df_regs_ever_live_p ($18) will be true if the
6426 call is not eliminated, and we can check that in the prologue
6429 CALL_INSN_FUNCTION_USAGE (insn) =
6430 gen_rtx_EXPR_LIST (VOIDmode,
6431 gen_rtx_CLOBBER (VOIDmode,
6432 gen_rtx_REG (word_mode, 18)),
6433 CALL_INSN_FUNCTION_USAGE (insn));
6438 /* We know the function we are going to call. If we have already
6439 built a stub, we don't need to do anything further. */
6440 fnname = targetm.strip_name_encoding (XSTR (fn, 0));
6441 for (l = mips16_stubs; l != NULL; l = l->next)
6442 if (strcmp (l->name, fnname) == 0)
6447 const char *separator;
6448 char *secname, *stubname;
6449 tree stubid, stubdecl;
6452 /* If the function does not return in FPRs, the special stub
6456 If the function does return in FPRs, the stub section is named
6457 .mips16.call.fp.FNNAME
6459 Build a decl for the stub. */
6460 secname = ACONCAT ((".mips16.call.", fp_ret_p ? "fp." : "",
6462 stubname = ACONCAT (("__call_stub_", fp_ret_p ? "fp_" : "",
6464 stubid = get_identifier (stubname);
6465 stubdecl = build_decl (BUILTINS_LOCATION,
6466 FUNCTION_DECL, stubid,
6467 build_function_type_list (void_type_node,
6469 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
6470 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
6471 RESULT_DECL, NULL_TREE,
6474 /* Output a comment. */
6475 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
6477 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
6481 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
6483 fprintf (asm_out_file, "%s%s", separator,
6484 (f & 3) == 1 ? "float" : "double");
6487 fprintf (asm_out_file, ")\n");
6489 /* Start the function definition. */
6490 assemble_start_function (stubdecl, stubname);
6491 mips_start_function_definition (stubname, false);
6495 fprintf (asm_out_file, "\t.cfi_startproc\n");
6497 /* Create a fake CFA 4 bytes below the stack pointer.
6498 This works around unwinders (like libgcc's) that expect
6499 the CFA for non-signal frames to be unique. */
6500 fprintf (asm_out_file, "\t.cfi_def_cfa 29,-4\n");
6502 /* "Save" $sp in itself so we don't use the fake CFA.
6503 This is: DW_CFA_val_expression r29, { DW_OP_reg29 }. */
6504 fprintf (asm_out_file, "\t.cfi_escape 0x16,29,1,0x6d\n");
6508 /* Load the address of the MIPS16 function into $25. Do this
6509 first so that targets with coprocessor interlocks can use
6510 an MFC1 to fill the delay slot. */
6511 if (TARGET_EXPLICIT_RELOCS)
6513 output_asm_insn ("lui\t%^,%%hi(%0)", &fn);
6514 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn);
6517 output_asm_insn ("la\t%^,%0", &fn);
6520 /* Move the arguments from general registers to floating-point
6522 mips_output_args_xfer (fp_code, 't');
6526 /* Save the return address in $18 and call the non-MIPS16 function.
6527 The stub's caller knows that $18 might be clobbered, even though
6528 $18 is usually a call-saved register. */
6529 fprintf (asm_out_file, "\tmove\t%s,%s\n",
6530 reg_names[GP_REG_FIRST + 18], reg_names[RETURN_ADDR_REGNUM]);
6531 output_asm_insn (MIPS_CALL ("jal", &fn, 0, -1), &fn);
6532 fprintf (asm_out_file, "\t.cfi_register 31,18\n");
6534 /* Move the result from floating-point registers to
6535 general registers. */
6536 switch (GET_MODE (retval))
6539 mips_output_32bit_xfer ('f', GP_RETURN + TARGET_BIG_ENDIAN,
6541 ? FP_REG_FIRST + MAX_FPRS_PER_FMT
6543 mips_output_32bit_xfer ('f', GP_RETURN + TARGET_LITTLE_ENDIAN,
6544 TARGET_LITTLE_ENDIAN
6545 ? FP_REG_FIRST + MAX_FPRS_PER_FMT
6547 if (GET_MODE (retval) == SCmode && TARGET_64BIT)
6549 /* On 64-bit targets, complex floats are returned in
6550 a single GPR, such that "sd" on a suitably-aligned
6551 target would store the value correctly. */
6552 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
6553 reg_names[GP_RETURN + TARGET_BIG_ENDIAN],
6554 reg_names[GP_RETURN + TARGET_BIG_ENDIAN]);
6555 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
6556 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN],
6557 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN]);
6558 fprintf (asm_out_file, "\tdsrl\t%s,%s,32\n",
6559 reg_names[GP_RETURN + TARGET_BIG_ENDIAN],
6560 reg_names[GP_RETURN + TARGET_BIG_ENDIAN]);
6561 fprintf (asm_out_file, "\tor\t%s,%s,%s\n",
6562 reg_names[GP_RETURN],
6563 reg_names[GP_RETURN],
6564 reg_names[GP_RETURN + 1]);
6569 mips_output_32bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6573 mips_output_64bit_xfer ('f', GP_RETURN + (8 / UNITS_PER_WORD),
6574 FP_REG_FIRST + MAX_FPRS_PER_FMT);
6578 mips_output_64bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6584 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 18]);
6585 fprintf (asm_out_file, "\t.cfi_endproc\n");
6589 /* Jump to the previously-loaded address. */
6590 output_asm_insn ("jr\t%^", NULL);
6593 #ifdef ASM_DECLARE_FUNCTION_SIZE
6594 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
6597 mips_end_function_definition (stubname);
6599 /* Record this stub. */
6600 l = XNEW (struct mips16_stub);
6601 l->name = xstrdup (fnname);
6602 l->fp_ret_p = fp_ret_p;
6603 l->next = mips16_stubs;
6607 /* If we expect a floating-point return value, but we've built a
6608 stub which does not expect one, then we're in trouble. We can't
6609 use the existing stub, because it won't handle the floating-point
6610 value. We can't build a new stub, because the linker won't know
6611 which stub to use for the various calls in this object file.
6612 Fortunately, this case is illegal, since it means that a function
6613 was declared in two different ways in a single compilation. */
6614 if (fp_ret_p && !l->fp_ret_p)
6615 error ("cannot handle inconsistent calls to %qs", fnname);
6617 if (retval == NULL_RTX)
6618 insn = gen_call_internal_direct (fn, args_size);
6620 insn = gen_call_value_internal_direct (retval, fn, args_size);
6621 insn = mips_emit_call_insn (insn, fn, fn, false);
6623 /* If we are calling a stub which handles a floating-point return
6624 value, we need to arrange to save $18 in the prologue. We do this
6625 by marking the function call as using the register. The prologue
6626 will later see that it is used, and emit code to save it. */
6628 CALL_INSN_FUNCTION_USAGE (insn) =
6629 gen_rtx_EXPR_LIST (VOIDmode,
6630 gen_rtx_CLOBBER (VOIDmode,
6631 gen_rtx_REG (word_mode, 18)),
6632 CALL_INSN_FUNCTION_USAGE (insn));
6637 /* Expand a call of type TYPE. RESULT is where the result will go (null
6638 for "call"s and "sibcall"s), ADDR is the address of the function,
6639 ARGS_SIZE is the size of the arguments and AUX is the value passed
6640 to us by mips_function_arg. LAZY_P is true if this call already
6641 involves a lazily-bound function address (such as when calling
6642 functions through a MIPS16 hard-float stub).
6644 Return the call itself. */
6647 mips_expand_call (enum mips_call_type type, rtx result, rtx addr,
6648 rtx args_size, rtx aux, bool lazy_p)
6650 rtx orig_addr, pattern, insn;
6653 fp_code = aux == 0 ? 0 : (int) GET_MODE (aux);
6654 insn = mips16_build_call_stub (result, &addr, args_size, fp_code);
6657 gcc_assert (!lazy_p && type == MIPS_CALL_NORMAL);
6662 if (!call_insn_operand (addr, VOIDmode))
6664 if (type == MIPS_CALL_EPILOGUE)
6665 addr = MIPS_EPILOGUE_TEMP (Pmode);
6667 addr = gen_reg_rtx (Pmode);
6668 lazy_p |= mips_load_call_address (type, addr, orig_addr);
6673 rtx (*fn) (rtx, rtx);
6675 if (type == MIPS_CALL_SIBCALL)
6676 fn = gen_sibcall_internal;
6678 fn = gen_call_internal;
6680 pattern = fn (addr, args_size);
6682 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
6684 /* Handle return values created by mips_return_fpr_pair. */
6685 rtx (*fn) (rtx, rtx, rtx, rtx);
6688 if (type == MIPS_CALL_SIBCALL)
6689 fn = gen_sibcall_value_multiple_internal;
6691 fn = gen_call_value_multiple_internal;
6693 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
6694 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
6695 pattern = fn (reg1, addr, args_size, reg2);
6699 rtx (*fn) (rtx, rtx, rtx);
6701 if (type == MIPS_CALL_SIBCALL)
6702 fn = gen_sibcall_value_internal;
6704 fn = gen_call_value_internal;
6706 /* Handle return values created by mips_return_fpr_single. */
6707 if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 1)
6708 result = XEXP (XVECEXP (result, 0, 0), 0);
6709 pattern = fn (result, addr, args_size);
6712 return mips_emit_call_insn (pattern, orig_addr, addr, lazy_p);
6715 /* Split call instruction INSN into a $gp-clobbering call and
6716 (where necessary) an instruction to restore $gp from its save slot.
6717 CALL_PATTERN is the pattern of the new call. */
6720 mips_split_call (rtx insn, rtx call_pattern)
6722 emit_call_insn (call_pattern);
6723 if (!find_reg_note (insn, REG_NORETURN, 0))
6724 /* Pick a temporary register that is suitable for both MIPS16 and
6725 non-MIPS16 code. $4 and $5 are used for returning complex double
6726 values in soft-float code, so $6 is the first suitable candidate. */
6727 mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode, GP_ARG_FIRST + 2));
6730 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
6733 mips_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
6735 if (!TARGET_SIBCALLS)
6738 /* Interrupt handlers need special epilogue code and therefore can't
6740 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
6743 /* We can't do a sibcall if the called function is a MIPS16 function
6744 because there is no direct "jx" instruction equivalent to "jalx" to
6745 switch the ISA mode. We only care about cases where the sibling
6746 and normal calls would both be direct. */
6748 && mips_use_mips16_mode_p (decl)
6749 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
6752 /* When -minterlink-mips16 is in effect, assume that non-locally-binding
6753 functions could be MIPS16 ones unless an attribute explicitly tells
6755 if (TARGET_INTERLINK_MIPS16
6757 && (DECL_EXTERNAL (decl) || !targetm.binds_local_p (decl))
6758 && !mips_nomips16_decl_p (decl)
6759 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
6766 /* Emit code to move general operand SRC into condition-code
6767 register DEST given that SCRATCH is a scratch TFmode FPR.
6774 where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */
6777 mips_expand_fcc_reload (rtx dest, rtx src, rtx scratch)
6781 /* Change the source to SFmode. */
6783 src = adjust_address (src, SFmode, 0);
6784 else if (REG_P (src) || GET_CODE (src) == SUBREG)
6785 src = gen_rtx_REG (SFmode, true_regnum (src));
6787 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
6788 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + MAX_FPRS_PER_FMT);
6790 mips_emit_move (copy_rtx (fp1), src);
6791 mips_emit_move (copy_rtx (fp2), CONST0_RTX (SFmode));
6792 emit_insn (gen_slt_sf (dest, fp2, fp1));
6795 /* Implement MOVE_BY_PIECES_P. */
6798 mips_move_by_pieces_p (unsigned HOST_WIDE_INT size, unsigned int align)
6802 /* movmemsi is meant to generate code that is at least as good as
6803 move_by_pieces. However, movmemsi effectively uses a by-pieces
6804 implementation both for moves smaller than a word and for
6805 word-aligned moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT
6806 bytes. We should allow the tree-level optimisers to do such
6807 moves by pieces, as it often exposes other optimization
6808 opportunities. We might as well continue to use movmemsi at
6809 the rtl level though, as it produces better code when
6810 scheduling is disabled (such as at -O). */
6811 if (currently_expanding_to_rtl)
6813 if (align < BITS_PER_WORD)
6814 return size < UNITS_PER_WORD;
6815 return size <= MIPS_MAX_MOVE_BYTES_STRAIGHT;
6817 /* The default value. If this becomes a target hook, we should
6818 call the default definition instead. */
6819 return (move_by_pieces_ninsns (size, align, MOVE_MAX_PIECES + 1)
6820 < (unsigned int) MOVE_RATIO (optimize_insn_for_speed_p ()));
6823 /* Implement STORE_BY_PIECES_P. */
6826 mips_store_by_pieces_p (unsigned HOST_WIDE_INT size, unsigned int align)
6828 /* Storing by pieces involves moving constants into registers
6829 of size MIN (ALIGN, BITS_PER_WORD), then storing them.
6830 We need to decide whether it is cheaper to load the address of
6831 constant data into a register and use a block move instead. */
6833 /* If the data is only byte aligned, then:
6835 (a1) A block move of less than 4 bytes would involve three 3 LBs and
6836 3 SBs. We might as well use 3 single-instruction LIs and 3 SBs
6839 (a2) A block move of 4 bytes from aligned source data can use an
6840 LW/SWL/SWR sequence. This is often better than the 4 LIs and
6841 4 SBs that we would generate when storing by pieces. */
6842 if (align <= BITS_PER_UNIT)
6845 /* If the data is 2-byte aligned, then:
6847 (b1) A block move of less than 4 bytes would use a combination of LBs,
6848 LHs, SBs and SHs. We get better code by using single-instruction
6849 LIs, SBs and SHs instead.
6851 (b2) A block move of 4 bytes from aligned source data would again use
6852 an LW/SWL/SWR sequence. In most cases, loading the address of
6853 the source data would require at least one extra instruction.
6854 It is often more efficient to use 2 single-instruction LIs and
6857 (b3) A block move of up to 3 additional bytes would be like (b1).
6859 (b4) A block move of 8 bytes from aligned source data can use two
6860 LW/SWL/SWR sequences or a single LD/SDL/SDR sequence. Both
6861 sequences are better than the 4 LIs and 4 SHs that we'd generate
6862 when storing by pieces.
6864 The reasoning for higher alignments is similar:
6866 (c1) A block move of less than 4 bytes would be the same as (b1).
6868 (c2) A block move of 4 bytes would use an LW/SW sequence. Again,
6869 loading the address of the source data would typically require
6870 at least one extra instruction. It is generally better to use
6873 (c3) A block move of up to 3 additional bytes would be like (b1).
6875 (c4) A block move of 8 bytes can use two LW/SW sequences or a single
6876 LD/SD sequence, and in these cases we've traditionally preferred
6877 the memory copy over the more bulky constant moves. */
6881 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
6882 Assume that the areas do not overlap. */
6885 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
6887 HOST_WIDE_INT offset, delta;
6888 unsigned HOST_WIDE_INT bits;
6890 enum machine_mode mode;
6893 /* Work out how many bits to move at a time. If both operands have
6894 half-word alignment, it is usually better to move in half words.
6895 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
6896 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
6897 Otherwise move word-sized chunks. */
6898 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
6899 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
6900 bits = BITS_PER_WORD / 2;
6902 bits = BITS_PER_WORD;
6904 mode = mode_for_size (bits, MODE_INT, 0);
6905 delta = bits / BITS_PER_UNIT;
6907 /* Allocate a buffer for the temporary registers. */
6908 regs = XALLOCAVEC (rtx, length / delta);
6910 /* Load as many BITS-sized chunks as possible. Use a normal load if
6911 the source has enough alignment, otherwise use left/right pairs. */
6912 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
6914 regs[i] = gen_reg_rtx (mode);
6915 if (MEM_ALIGN (src) >= bits)
6916 mips_emit_move (regs[i], adjust_address (src, mode, offset));
6919 rtx part = adjust_address (src, BLKmode, offset);
6920 if (!mips_expand_ext_as_unaligned_load (regs[i], part, bits, 0))
6925 /* Copy the chunks to the destination. */
6926 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
6927 if (MEM_ALIGN (dest) >= bits)
6928 mips_emit_move (adjust_address (dest, mode, offset), regs[i]);
6931 rtx part = adjust_address (dest, BLKmode, offset);
6932 if (!mips_expand_ins_as_unaligned_store (part, regs[i], bits, 0))
6936 /* Mop up any left-over bytes. */
6937 if (offset < length)
6939 src = adjust_address (src, BLKmode, offset);
6940 dest = adjust_address (dest, BLKmode, offset);
6941 move_by_pieces (dest, src, length - offset,
6942 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
6946 /* Helper function for doing a loop-based block operation on memory
6947 reference MEM. Each iteration of the loop will operate on LENGTH
6950 Create a new base register for use within the loop and point it to
6951 the start of MEM. Create a new memory reference that uses this
6952 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
6955 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
6956 rtx *loop_reg, rtx *loop_mem)
6958 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
6960 /* Although the new mem does not refer to a known location,
6961 it does keep up to LENGTH bytes of alignment. */
6962 *loop_mem = change_address (mem, BLKmode, *loop_reg);
6963 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
6966 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
6967 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
6968 the memory regions do not overlap. */
6971 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length,
6972 HOST_WIDE_INT bytes_per_iter)
6974 rtx label, src_reg, dest_reg, final_src, test;
6975 HOST_WIDE_INT leftover;
6977 leftover = length % bytes_per_iter;
6980 /* Create registers and memory references for use within the loop. */
6981 mips_adjust_block_mem (src, bytes_per_iter, &src_reg, &src);
6982 mips_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest);
6984 /* Calculate the value that SRC_REG should have after the last iteration
6986 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
6989 /* Emit the start of the loop. */
6990 label = gen_label_rtx ();
6993 /* Emit the loop body. */
6994 mips_block_move_straight (dest, src, bytes_per_iter);
6996 /* Move on to the next block. */
6997 mips_emit_move (src_reg, plus_constant (Pmode, src_reg, bytes_per_iter));
6998 mips_emit_move (dest_reg, plus_constant (Pmode, dest_reg, bytes_per_iter));
7000 /* Emit the loop condition. */
7001 test = gen_rtx_NE (VOIDmode, src_reg, final_src);
7002 if (Pmode == DImode)
7003 emit_jump_insn (gen_cbranchdi4 (test, src_reg, final_src, label));
7005 emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label));
7007 /* Mop up any left-over bytes. */
7009 mips_block_move_straight (dest, src, leftover);
7012 /* Expand a movmemsi instruction, which copies LENGTH bytes from
7013 memory reference SRC to memory reference DEST. */
7016 mips_expand_block_move (rtx dest, rtx src, rtx length)
7018 if (CONST_INT_P (length))
7020 if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)
7022 mips_block_move_straight (dest, src, INTVAL (length));
7027 mips_block_move_loop (dest, src, INTVAL (length),
7028 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER);
7035 /* Expand a loop of synci insns for the address range [BEGIN, END). */
7038 mips_expand_synci_loop (rtx begin, rtx end)
7040 rtx inc, label, end_label, cmp_result, mask, length;
7042 /* Create end_label. */
7043 end_label = gen_label_rtx ();
7045 /* Check if begin equals end. */
7046 cmp_result = gen_rtx_EQ (VOIDmode, begin, end);
7047 emit_jump_insn (gen_condjump (cmp_result, end_label));
7049 /* Load INC with the cache line size (rdhwr INC,$1). */
7050 inc = gen_reg_rtx (Pmode);
7051 emit_insn (PMODE_INSN (gen_rdhwr_synci_step, (inc)));
7053 /* Check if inc is 0. */
7054 cmp_result = gen_rtx_EQ (VOIDmode, inc, const0_rtx);
7055 emit_jump_insn (gen_condjump (cmp_result, end_label));
7057 /* Calculate mask. */
7058 mask = mips_force_unary (Pmode, NEG, inc);
7060 /* Mask out begin by mask. */
7061 begin = mips_force_binary (Pmode, AND, begin, mask);
7063 /* Calculate length. */
7064 length = mips_force_binary (Pmode, MINUS, end, begin);
7066 /* Loop back to here. */
7067 label = gen_label_rtx ();
7070 emit_insn (gen_synci (begin));
7072 /* Update length. */
7073 mips_emit_binary (MINUS, length, length, inc);
7076 mips_emit_binary (PLUS, begin, begin, inc);
7078 /* Check if length is greater than 0. */
7079 cmp_result = gen_rtx_GT (VOIDmode, length, const0_rtx);
7080 emit_jump_insn (gen_condjump (cmp_result, label));
7082 emit_label (end_label);
7085 /* Expand a QI or HI mode atomic memory operation.
7087 GENERATOR contains a pointer to the gen_* function that generates
7088 the SI mode underlying atomic operation using masks that we
7091 RESULT is the return register for the operation. Its value is NULL
7094 MEM is the location of the atomic access.
7096 OLDVAL is the first operand for the operation.
7098 NEWVAL is the optional second operand for the operation. Its value
7099 is NULL if unused. */
7102 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator,
7103 rtx result, rtx mem, rtx oldval, rtx newval)
7105 rtx orig_addr, memsi_addr, memsi, shift, shiftsi, unshifted_mask;
7106 rtx unshifted_mask_reg, mask, inverted_mask, si_op;
7108 enum machine_mode mode;
7110 mode = GET_MODE (mem);
7112 /* Compute the address of the containing SImode value. */
7113 orig_addr = force_reg (Pmode, XEXP (mem, 0));
7114 memsi_addr = mips_force_binary (Pmode, AND, orig_addr,
7115 force_reg (Pmode, GEN_INT (-4)));
7117 /* Create a memory reference for it. */
7118 memsi = gen_rtx_MEM (SImode, memsi_addr);
7119 set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER);
7120 MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem);
7122 /* Work out the byte offset of the QImode or HImode value,
7123 counting from the least significant byte. */
7124 shift = mips_force_binary (Pmode, AND, orig_addr, GEN_INT (3));
7125 if (TARGET_BIG_ENDIAN)
7126 mips_emit_binary (XOR, shift, shift, GEN_INT (mode == QImode ? 3 : 2));
7128 /* Multiply by eight to convert the shift value from bytes to bits. */
7129 mips_emit_binary (ASHIFT, shift, shift, GEN_INT (3));
7131 /* Make the final shift an SImode value, so that it can be used in
7132 SImode operations. */
7133 shiftsi = force_reg (SImode, gen_lowpart (SImode, shift));
7135 /* Set MASK to an inclusive mask of the QImode or HImode value. */
7136 unshifted_mask = GEN_INT (GET_MODE_MASK (mode));
7137 unshifted_mask_reg = force_reg (SImode, unshifted_mask);
7138 mask = mips_force_binary (SImode, ASHIFT, unshifted_mask_reg, shiftsi);
7140 /* Compute the equivalent exclusive mask. */
7141 inverted_mask = gen_reg_rtx (SImode);
7142 emit_insn (gen_rtx_SET (VOIDmode, inverted_mask,
7143 gen_rtx_NOT (SImode, mask)));
7145 /* Shift the old value into place. */
7146 if (oldval != const0_rtx)
7148 oldval = convert_modes (SImode, mode, oldval, true);
7149 oldval = force_reg (SImode, oldval);
7150 oldval = mips_force_binary (SImode, ASHIFT, oldval, shiftsi);
7153 /* Do the same for the new value. */
7154 if (newval && newval != const0_rtx)
7156 newval = convert_modes (SImode, mode, newval, true);
7157 newval = force_reg (SImode, newval);
7158 newval = mips_force_binary (SImode, ASHIFT, newval, shiftsi);
7161 /* Do the SImode atomic access. */
7163 res = gen_reg_rtx (SImode);
7165 si_op = generator.fn_6 (res, memsi, mask, inverted_mask, oldval, newval);
7167 si_op = generator.fn_5 (res, memsi, mask, inverted_mask, oldval);
7169 si_op = generator.fn_4 (memsi, mask, inverted_mask, oldval);
7175 /* Shift and convert the result. */
7176 mips_emit_binary (AND, res, res, mask);
7177 mips_emit_binary (LSHIFTRT, res, res, shiftsi);
7178 mips_emit_move (result, gen_lowpart (GET_MODE (result), res));
7182 /* Return true if it is possible to use left/right accesses for a
7183 bitfield of WIDTH bits starting BITPOS bits into *OP. When
7184 returning true, update *OP, *LEFT and *RIGHT as follows:
7186 *OP is a BLKmode reference to the whole field.
7188 *LEFT is a QImode reference to the first byte if big endian or
7189 the last byte if little endian. This address can be used in the
7190 left-side instructions (LWL, SWL, LDL, SDL).
7192 *RIGHT is a QImode reference to the opposite end of the field and
7193 can be used in the patterning right-side instruction. */
7196 mips_get_unaligned_mem (rtx *op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos,
7197 rtx *left, rtx *right)
7201 /* Check that the operand really is a MEM. Not all the extv and
7202 extzv predicates are checked. */
7206 /* Check that the size is valid. */
7207 if (width != 32 && (!TARGET_64BIT || width != 64))
7210 /* We can only access byte-aligned values. Since we are always passed
7211 a reference to the first byte of the field, it is not necessary to
7212 do anything with BITPOS after this check. */
7213 if (bitpos % BITS_PER_UNIT != 0)
7216 /* Reject aligned bitfields: we want to use a normal load or store
7217 instead of a left/right pair. */
7218 if (MEM_ALIGN (*op) >= width)
7221 /* Adjust *OP to refer to the whole field. This also has the effect
7222 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
7223 *op = adjust_address (*op, BLKmode, 0);
7224 set_mem_size (*op, width / BITS_PER_UNIT);
7226 /* Get references to both ends of the field. We deliberately don't
7227 use the original QImode *OP for FIRST since the new BLKmode one
7228 might have a simpler address. */
7229 first = adjust_address (*op, QImode, 0);
7230 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
7232 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
7233 correspond to the MSB and RIGHT to the LSB. */
7234 if (TARGET_BIG_ENDIAN)
7235 *left = first, *right = last;
7237 *left = last, *right = first;
7242 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
7243 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
7244 the operation is the equivalent of:
7246 (set DEST (*_extract SRC WIDTH BITPOS))
7248 Return true on success. */
7251 mips_expand_ext_as_unaligned_load (rtx dest, rtx src, HOST_WIDE_INT width,
7252 HOST_WIDE_INT bitpos)
7254 rtx left, right, temp;
7256 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
7257 be a paradoxical word_mode subreg. This is the only case in which
7258 we allow the destination to be larger than the source. */
7259 if (GET_CODE (dest) == SUBREG
7260 && GET_MODE (dest) == DImode
7261 && GET_MODE (SUBREG_REG (dest)) == SImode)
7262 dest = SUBREG_REG (dest);
7264 /* After the above adjustment, the destination must be the same
7265 width as the source. */
7266 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
7269 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
7272 temp = gen_reg_rtx (GET_MODE (dest));
7273 if (GET_MODE (dest) == DImode)
7275 emit_insn (gen_mov_ldl (temp, src, left));
7276 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
7280 emit_insn (gen_mov_lwl (temp, src, left));
7281 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
7286 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
7287 BITPOS and SRC are the operands passed to the expander; the operation
7288 is the equivalent of:
7290 (set (zero_extract DEST WIDTH BITPOS) SRC)
7292 Return true on success. */
7295 mips_expand_ins_as_unaligned_store (rtx dest, rtx src, HOST_WIDE_INT width,
7296 HOST_WIDE_INT bitpos)
7299 enum machine_mode mode;
7301 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
7304 mode = mode_for_size (width, MODE_INT, 0);
7305 src = gen_lowpart (mode, src);
7308 emit_insn (gen_mov_sdl (dest, src, left));
7309 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
7313 emit_insn (gen_mov_swl (dest, src, left));
7314 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
7319 /* Return true if X is a MEM with the same size as MODE. */
7322 mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
7325 && MEM_SIZE_KNOWN_P (x)
7326 && MEM_SIZE (x) == GET_MODE_SIZE (mode));
7329 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
7330 source of an "ext" instruction or the destination of an "ins"
7331 instruction. OP must be a register operand and the following
7332 conditions must hold:
7334 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
7335 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7336 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7338 Also reject lengths equal to a word as they are better handled
7339 by the move patterns. */
7342 mips_use_ins_ext_p (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos)
7344 if (!ISA_HAS_EXT_INS
7345 || !register_operand (op, VOIDmode)
7346 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
7349 if (!IN_RANGE (width, 1, GET_MODE_BITSIZE (GET_MODE (op)) - 1))
7352 if (bitpos < 0 || bitpos + width > GET_MODE_BITSIZE (GET_MODE (op)))
7358 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
7359 operation if MAXLEN is the maxium length of consecutive bits that
7360 can make up MASK. MODE is the mode of the operation. See
7361 mask_low_and_shift_len for the actual definition. */
7364 mask_low_and_shift_p (enum machine_mode mode, rtx mask, rtx shift, int maxlen)
7366 return IN_RANGE (mask_low_and_shift_len (mode, mask, shift), 1, maxlen);
7369 /* Return true iff OP1 and OP2 are valid operands together for the
7370 *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider,
7371 see the table in the comment before the pattern. */
7374 and_operands_ok (enum machine_mode mode, rtx op1, rtx op2)
7376 return (memory_operand (op1, mode)
7377 ? and_load_operand (op2, mode)
7378 : and_reg_operand (op2, mode));
7381 /* The canonical form of a mask-low-and-shift-left operation is
7382 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
7383 cleared. Thus we need to shift MASK to the right before checking if it
7384 is a valid mask value. MODE is the mode of the operation. If true
7385 return the length of the mask, otherwise return -1. */
7388 mask_low_and_shift_len (enum machine_mode mode, rtx mask, rtx shift)
7390 HOST_WIDE_INT shval;
7392 shval = INTVAL (shift) & (GET_MODE_BITSIZE (mode) - 1);
7393 return exact_log2 ((UINTVAL (mask) >> shval) + 1);
7396 /* Return true if -msplit-addresses is selected and should be honored.
7398 -msplit-addresses is a half-way house between explicit relocations
7399 and the traditional assembler macros. It can split absolute 32-bit
7400 symbolic constants into a high/lo_sum pair but uses macros for other
7403 Like explicit relocation support for REL targets, it relies
7404 on GNU extensions in the assembler and the linker.
7406 Although this code should work for -O0, it has traditionally
7407 been treated as an optimization. */
7410 mips_split_addresses_p (void)
7412 return (TARGET_SPLIT_ADDRESSES
7416 && !ABI_HAS_64BIT_SYMBOLS);
7419 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
7422 mips_init_relocs (void)
7424 memset (mips_split_p, '\0', sizeof (mips_split_p));
7425 memset (mips_split_hi_p, '\0', sizeof (mips_split_hi_p));
7426 memset (mips_use_pcrel_pool_p, '\0', sizeof (mips_use_pcrel_pool_p));
7427 memset (mips_hi_relocs, '\0', sizeof (mips_hi_relocs));
7428 memset (mips_lo_relocs, '\0', sizeof (mips_lo_relocs));
7430 if (TARGET_MIPS16_PCREL_LOADS)
7431 mips_use_pcrel_pool_p[SYMBOL_ABSOLUTE] = true;
7434 if (ABI_HAS_64BIT_SYMBOLS)
7436 if (TARGET_EXPLICIT_RELOCS)
7438 mips_split_p[SYMBOL_64_HIGH] = true;
7439 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
7440 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
7442 mips_split_p[SYMBOL_64_MID] = true;
7443 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
7444 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
7446 mips_split_p[SYMBOL_64_LOW] = true;
7447 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
7448 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
7450 mips_split_p[SYMBOL_ABSOLUTE] = true;
7451 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
7456 if (TARGET_EXPLICIT_RELOCS
7457 || mips_split_addresses_p ()
7460 mips_split_p[SYMBOL_ABSOLUTE] = true;
7461 mips_hi_relocs[SYMBOL_ABSOLUTE] = "%hi(";
7462 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
7469 /* The high part is provided by a pseudo copy of $gp. */
7470 mips_split_p[SYMBOL_GP_RELATIVE] = true;
7471 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gprel(";
7473 else if (TARGET_EXPLICIT_RELOCS)
7474 /* Small data constants are kept whole until after reload,
7475 then lowered by mips_rewrite_small_data. */
7476 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gp_rel(";
7478 if (TARGET_EXPLICIT_RELOCS)
7480 mips_split_p[SYMBOL_GOT_PAGE_OFST] = true;
7483 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
7484 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%got_ofst(";
7488 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
7489 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%lo(";
7492 /* Expose the use of $28 as soon as possible. */
7493 mips_split_hi_p[SYMBOL_GOT_PAGE_OFST] = true;
7497 /* The HIGH and LO_SUM are matched by special .md patterns. */
7498 mips_split_p[SYMBOL_GOT_DISP] = true;
7500 mips_split_p[SYMBOL_GOTOFF_DISP] = true;
7501 mips_hi_relocs[SYMBOL_GOTOFF_DISP] = "%got_hi(";
7502 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_lo(";
7504 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
7505 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
7506 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
7511 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_disp(";
7513 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got(";
7514 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
7516 /* Expose the use of $28 as soon as possible. */
7517 mips_split_p[SYMBOL_GOT_DISP] = true;
7523 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
7524 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
7525 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
7528 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
7529 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
7531 if (TARGET_MIPS16_PCREL_LOADS)
7533 mips_use_pcrel_pool_p[SYMBOL_DTPREL] = true;
7534 mips_use_pcrel_pool_p[SYMBOL_TPREL] = true;
7538 mips_split_p[SYMBOL_DTPREL] = true;
7539 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
7540 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
7542 mips_split_p[SYMBOL_TPREL] = true;
7543 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
7544 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
7547 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
7548 mips_lo_relocs[SYMBOL_HALF] = "%half(";
7551 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
7552 in context CONTEXT. RELOCS is the array of relocations to use. */
7555 mips_print_operand_reloc (FILE *file, rtx op, enum mips_symbol_context context,
7556 const char **relocs)
7558 enum mips_symbol_type symbol_type;
7561 symbol_type = mips_classify_symbolic_expression (op, context);
7562 gcc_assert (relocs[symbol_type]);
7564 fputs (relocs[symbol_type], file);
7565 output_addr_const (file, mips_strip_unspec_address (op));
7566 for (p = relocs[symbol_type]; *p != 0; p++)
7571 /* Start a new block with the given asm switch enabled. If we need
7572 to print a directive, emit PREFIX before it and SUFFIX after it. */
7575 mips_push_asm_switch_1 (struct mips_asm_switch *asm_switch,
7576 const char *prefix, const char *suffix)
7578 if (asm_switch->nesting_level == 0)
7579 fprintf (asm_out_file, "%s.set\tno%s%s", prefix, asm_switch->name, suffix);
7580 asm_switch->nesting_level++;
7583 /* Likewise, but end a block. */
7586 mips_pop_asm_switch_1 (struct mips_asm_switch *asm_switch,
7587 const char *prefix, const char *suffix)
7589 gcc_assert (asm_switch->nesting_level);
7590 asm_switch->nesting_level--;
7591 if (asm_switch->nesting_level == 0)
7592 fprintf (asm_out_file, "%s.set\t%s%s", prefix, asm_switch->name, suffix);
7595 /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1
7596 that either print a complete line or print nothing. */
7599 mips_push_asm_switch (struct mips_asm_switch *asm_switch)
7601 mips_push_asm_switch_1 (asm_switch, "\t", "\n");
7605 mips_pop_asm_switch (struct mips_asm_switch *asm_switch)
7607 mips_pop_asm_switch_1 (asm_switch, "\t", "\n");
7610 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
7611 The punctuation characters are:
7613 '(' Start a nested ".set noreorder" block.
7614 ')' End a nested ".set noreorder" block.
7615 '[' Start a nested ".set noat" block.
7616 ']' End a nested ".set noat" block.
7617 '<' Start a nested ".set nomacro" block.
7618 '>' End a nested ".set nomacro" block.
7619 '*' Behave like %(%< if generating a delayed-branch sequence.
7620 '#' Print a nop if in a ".set noreorder" block.
7621 '/' Like '#', but do nothing within a delayed-branch sequence.
7622 '?' Print "l" if mips_branch_likely is true
7623 '~' Print a nop if mips_branch_likely is true
7624 '.' Print the name of the register with a hard-wired zero (zero or $0).
7625 '@' Print the name of the assembler temporary register (at or $1).
7626 '^' Print the name of the pic call-through register (t9 or $25).
7627 '+' Print the name of the gp register (usually gp or $28).
7628 '$' Print the name of the stack pointer register (sp or $29).
7630 See also mips_init_print_operand_pucnt. */
7633 mips_print_operand_punctuation (FILE *file, int ch)
7638 mips_push_asm_switch_1 (&mips_noreorder, "", "\n\t");
7642 mips_pop_asm_switch_1 (&mips_noreorder, "\n\t", "");
7646 mips_push_asm_switch_1 (&mips_noat, "", "\n\t");
7650 mips_pop_asm_switch_1 (&mips_noat, "\n\t", "");
7654 mips_push_asm_switch_1 (&mips_nomacro, "", "\n\t");
7658 mips_pop_asm_switch_1 (&mips_nomacro, "\n\t", "");
7662 if (final_sequence != 0)
7664 mips_print_operand_punctuation (file, '(');
7665 mips_print_operand_punctuation (file, '<');
7670 if (mips_noreorder.nesting_level > 0)
7671 fputs ("\n\tnop", file);
7675 /* Print an extra newline so that the delayed insn is separated
7676 from the following ones. This looks neater and is consistent
7677 with non-nop delayed sequences. */
7678 if (mips_noreorder.nesting_level > 0 && final_sequence == 0)
7679 fputs ("\n\tnop\n", file);
7683 if (mips_branch_likely)
7688 if (mips_branch_likely)
7689 fputs ("\n\tnop", file);
7693 fputs (reg_names[GP_REG_FIRST + 0], file);
7697 fputs (reg_names[AT_REGNUM], file);
7701 fputs (reg_names[PIC_FUNCTION_ADDR_REGNUM], file);
7705 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
7709 fputs (reg_names[STACK_POINTER_REGNUM], file);
7718 /* Initialize mips_print_operand_punct. */
7721 mips_init_print_operand_punct (void)
7725 for (p = "()[]<>*#/?~.@^+$"; *p; p++)
7726 mips_print_operand_punct[(unsigned char) *p] = true;
7729 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
7730 associated with condition CODE. Print the condition part of the
7734 mips_print_int_branch_condition (FILE *file, enum rtx_code code, int letter)
7748 /* Conveniently, the MIPS names for these conditions are the same
7749 as their RTL equivalents. */
7750 fputs (GET_RTX_NAME (code), file);
7754 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
7759 /* Likewise floating-point branches. */
7762 mips_print_float_branch_condition (FILE *file, enum rtx_code code, int letter)
7767 fputs ("c1f", file);
7771 fputs ("c1t", file);
7775 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
7780 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
7783 mips_print_operand_punct_valid_p (unsigned char code)
7785 return mips_print_operand_punct[code];
7788 /* Implement TARGET_PRINT_OPERAND. The MIPS-specific operand codes are:
7790 'X' Print CONST_INT OP in hexadecimal format.
7791 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
7792 'd' Print CONST_INT OP in decimal.
7793 'm' Print one less than CONST_INT OP in decimal.
7794 'h' Print the high-part relocation associated with OP, after stripping
7796 'R' Print the low-part relocation associated with OP.
7797 'C' Print the integer branch condition for comparison OP.
7798 'N' Print the inverse of the integer branch condition for comparison OP.
7799 'F' Print the FPU branch condition for comparison OP.
7800 'W' Print the inverse of the FPU branch condition for comparison OP.
7801 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
7802 'z' for (eq:?I ...), 'n' for (ne:?I ...).
7803 't' Like 'T', but with the EQ/NE cases reversed
7804 'Y' Print mips_fp_conditions[INTVAL (OP)]
7805 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
7806 'q' Print a DSP accumulator register.
7807 'D' Print the second part of a double-word register or memory operand.
7808 'L' Print the low-order register in a double-word register operand.
7809 'M' Print high-order register in a double-word register operand.
7810 'z' Print $0 if OP is zero, otherwise print OP normally. */
7813 mips_print_operand (FILE *file, rtx op, int letter)
7817 if (mips_print_operand_punct_valid_p (letter))
7819 mips_print_operand_punctuation (file, letter);
7824 code = GET_CODE (op);
7829 if (CONST_INT_P (op))
7830 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
7832 output_operand_lossage ("invalid use of '%%%c'", letter);
7836 if (CONST_INT_P (op))
7837 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op) & 0xffff);
7839 output_operand_lossage ("invalid use of '%%%c'", letter);
7843 if (CONST_INT_P (op))
7844 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op));
7846 output_operand_lossage ("invalid use of '%%%c'", letter);
7850 if (CONST_INT_P (op))
7851 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op) - 1);
7853 output_operand_lossage ("invalid use of '%%%c'", letter);
7859 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_hi_relocs);
7863 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_lo_relocs);
7867 mips_print_int_branch_condition (file, code, letter);
7871 mips_print_int_branch_condition (file, reverse_condition (code), letter);
7875 mips_print_float_branch_condition (file, code, letter);
7879 mips_print_float_branch_condition (file, reverse_condition (code),
7886 int truth = (code == NE) == (letter == 'T');
7887 fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
7892 if (code == CONST_INT && UINTVAL (op) < ARRAY_SIZE (mips_fp_conditions))
7893 fputs (mips_fp_conditions[UINTVAL (op)], file);
7895 output_operand_lossage ("'%%%c' is not a valid operand prefix",
7902 mips_print_operand (file, op, 0);
7908 if (code == REG && MD_REG_P (REGNO (op)))
7909 fprintf (file, "$ac0");
7910 else if (code == REG && DSP_ACC_REG_P (REGNO (op)))
7911 fprintf (file, "$ac%c", reg_names[REGNO (op)][3]);
7913 output_operand_lossage ("invalid use of '%%%c'", letter);
7921 unsigned int regno = REGNO (op);
7922 if ((letter == 'M' && TARGET_LITTLE_ENDIAN)
7923 || (letter == 'L' && TARGET_BIG_ENDIAN)
7926 else if (letter && letter != 'z' && letter != 'M' && letter != 'L')
7927 output_operand_lossage ("invalid use of '%%%c'", letter);
7928 /* We need to print $0 .. $31 for COP0 registers. */
7929 if (COP0_REG_P (regno))
7930 fprintf (file, "$%s", ®_names[regno][4]);
7932 fprintf (file, "%s", reg_names[regno]);
7938 output_address (plus_constant (Pmode, XEXP (op, 0), 4));
7939 else if (letter && letter != 'z')
7940 output_operand_lossage ("invalid use of '%%%c'", letter);
7942 output_address (XEXP (op, 0));
7946 if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
7947 fputs (reg_names[GP_REG_FIRST], file);
7948 else if (letter && letter != 'z')
7949 output_operand_lossage ("invalid use of '%%%c'", letter);
7950 else if (CONST_GP_P (op))
7951 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
7953 output_addr_const (file, mips_strip_unspec_address (op));
7959 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
7962 mips_print_operand_address (FILE *file, rtx x)
7964 struct mips_address_info addr;
7966 if (mips_classify_address (&addr, x, word_mode, true))
7970 mips_print_operand (file, addr.offset, 0);
7971 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
7974 case ADDRESS_LO_SUM:
7975 mips_print_operand_reloc (file, addr.offset, SYMBOL_CONTEXT_MEM,
7977 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
7980 case ADDRESS_CONST_INT:
7981 output_addr_const (file, x);
7982 fprintf (file, "(%s)", reg_names[GP_REG_FIRST]);
7985 case ADDRESS_SYMBOLIC:
7986 output_addr_const (file, mips_strip_unspec_address (x));
7992 /* Implement TARGET_ENCODE_SECTION_INFO. */
7995 mips_encode_section_info (tree decl, rtx rtl, int first)
7997 default_encode_section_info (decl, rtl, first);
7999 if (TREE_CODE (decl) == FUNCTION_DECL)
8001 rtx symbol = XEXP (rtl, 0);
8002 tree type = TREE_TYPE (decl);
8004 /* Encode whether the symbol is short or long. */
8005 if ((TARGET_LONG_CALLS && !mips_near_type_p (type))
8006 || mips_far_type_p (type))
8007 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
8011 /* Implement TARGET_SELECT_RTX_SECTION. */
8014 mips_select_rtx_section (enum machine_mode mode, rtx x,
8015 unsigned HOST_WIDE_INT align)
8017 /* ??? Consider using mergeable small data sections. */
8018 if (mips_rtx_constant_in_small_data_p (mode))
8019 return get_named_section (NULL, ".sdata", 0);
8021 return default_elf_select_rtx_section (mode, x, align);
8024 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
8026 The complication here is that, with the combination TARGET_ABICALLS
8027 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
8028 absolute addresses, and should therefore not be included in the
8029 read-only part of a DSO. Handle such cases by selecting a normal
8030 data section instead of a read-only one. The logic apes that in
8031 default_function_rodata_section. */
8034 mips_function_rodata_section (tree decl)
8036 if (!TARGET_ABICALLS || TARGET_ABSOLUTE_ABICALLS || TARGET_GPWORD)
8037 return default_function_rodata_section (decl);
8039 if (decl && DECL_SECTION_NAME (decl))
8041 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
8042 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
8044 char *rname = ASTRDUP (name);
8046 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
8048 else if (flag_function_sections
8049 && flag_data_sections
8050 && strncmp (name, ".text.", 6) == 0)
8052 char *rname = ASTRDUP (name);
8053 memcpy (rname + 1, "data", 4);
8054 return get_section (rname, SECTION_WRITE, decl);
8057 return data_section;
8060 /* Implement TARGET_IN_SMALL_DATA_P. */
8063 mips_in_small_data_p (const_tree decl)
8065 unsigned HOST_WIDE_INT size;
8067 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
8070 /* We don't yet generate small-data references for -mabicalls
8071 or VxWorks RTP code. See the related -G handling in
8072 mips_option_override. */
8073 if (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
8076 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
8080 /* Reject anything that isn't in a known small-data section. */
8081 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
8082 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
8085 /* If a symbol is defined externally, the assembler will use the
8086 usual -G rules when deciding how to implement macros. */
8087 if (mips_lo_relocs[SYMBOL_GP_RELATIVE] || !DECL_EXTERNAL (decl))
8090 else if (TARGET_EMBEDDED_DATA)
8092 /* Don't put constants into the small data section: we want them
8093 to be in ROM rather than RAM. */
8094 if (TREE_CODE (decl) != VAR_DECL)
8097 if (TREE_READONLY (decl)
8098 && !TREE_SIDE_EFFECTS (decl)
8099 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
8103 /* Enforce -mlocal-sdata. */
8104 if (!TARGET_LOCAL_SDATA && !TREE_PUBLIC (decl))
8107 /* Enforce -mextern-sdata. */
8108 if (!TARGET_EXTERN_SDATA && DECL_P (decl))
8110 if (DECL_EXTERNAL (decl))
8112 if (DECL_COMMON (decl) && DECL_INITIAL (decl) == NULL)
8116 /* We have traditionally not treated zero-sized objects as small data,
8117 so this is now effectively part of the ABI. */
8118 size = int_size_in_bytes (TREE_TYPE (decl));
8119 return size > 0 && size <= mips_small_data_threshold;
8122 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
8123 anchors for small data: the GP register acts as an anchor in that
8124 case. We also don't want to use them for PC-relative accesses,
8125 where the PC acts as an anchor. */
8128 mips_use_anchors_for_symbol_p (const_rtx symbol)
8130 switch (mips_classify_symbol (symbol, SYMBOL_CONTEXT_MEM))
8132 case SYMBOL_PC_RELATIVE:
8133 case SYMBOL_GP_RELATIVE:
8137 return default_use_anchors_for_symbol_p (symbol);
8141 /* The MIPS debug format wants all automatic variables and arguments
8142 to be in terms of the virtual frame pointer (stack pointer before
8143 any adjustment in the function), while the MIPS 3.0 linker wants
8144 the frame pointer to be the stack pointer after the initial
8145 adjustment. So, we do the adjustment here. The arg pointer (which
8146 is eliminated) points to the virtual frame pointer, while the frame
8147 pointer (which may be eliminated) points to the stack pointer after
8148 the initial adjustments. */
8151 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
8153 rtx offset2 = const0_rtx;
8154 rtx reg = eliminate_constant_term (addr, &offset2);
8157 offset = INTVAL (offset2);
8159 if (reg == stack_pointer_rtx
8160 || reg == frame_pointer_rtx
8161 || reg == hard_frame_pointer_rtx)
8163 offset -= cfun->machine->frame.total_size;
8164 if (reg == hard_frame_pointer_rtx)
8165 offset += cfun->machine->frame.hard_frame_pointer_offset;
8171 /* Implement ASM_OUTPUT_EXTERNAL. */
8174 mips_output_external (FILE *file, tree decl, const char *name)
8176 default_elf_asm_output_external (file, decl, name);
8178 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
8179 set in order to avoid putting out names that are never really
8181 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
8183 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
8185 /* When using assembler macros, emit .extern directives for
8186 all small-data externs so that the assembler knows how
8189 In most cases it would be safe (though pointless) to emit
8190 .externs for other symbols too. One exception is when an
8191 object is within the -G limit but declared by the user to
8192 be in a section other than .sbss or .sdata. */
8193 fputs ("\t.extern\t", file);
8194 assemble_name (file, name);
8195 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n",
8196 int_size_in_bytes (TREE_TYPE (decl)));
8201 /* Implement TARGET_ASM_OUTPUT_SOURCE_FILENAME. */
8204 mips_output_filename (FILE *stream, const char *name)
8206 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
8208 if (write_symbols == DWARF2_DEBUG)
8210 else if (mips_output_filename_first_time)
8212 mips_output_filename_first_time = 0;
8213 num_source_filenames += 1;
8214 current_function_file = name;
8215 fprintf (stream, "\t.file\t%d ", num_source_filenames);
8216 output_quoted_string (stream, name);
8217 putc ('\n', stream);
8219 /* If we are emitting stabs, let dbxout.c handle this (except for
8220 the mips_output_filename_first_time case). */
8221 else if (write_symbols == DBX_DEBUG)
8223 else if (name != current_function_file
8224 && strcmp (name, current_function_file) != 0)
8226 num_source_filenames += 1;
8227 current_function_file = name;
8228 fprintf (stream, "\t.file\t%d ", num_source_filenames);
8229 output_quoted_string (stream, name);
8230 putc ('\n', stream);
8234 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
8236 static void ATTRIBUTE_UNUSED
8237 mips_output_dwarf_dtprel (FILE *file, int size, rtx x)
8242 fputs ("\t.dtprelword\t", file);
8246 fputs ("\t.dtpreldword\t", file);
8252 output_addr_const (file, x);
8253 fputs ("+0x8000", file);
8256 /* Implement TARGET_DWARF_REGISTER_SPAN. */
8259 mips_dwarf_register_span (rtx reg)
8262 enum machine_mode mode;
8264 /* By default, GCC maps increasing register numbers to increasing
8265 memory locations, but paired FPRs are always little-endian,
8266 regardless of the prevailing endianness. */
8267 mode = GET_MODE (reg);
8268 if (FP_REG_P (REGNO (reg))
8269 && TARGET_BIG_ENDIAN
8270 && MAX_FPRS_PER_FMT > 1
8271 && GET_MODE_SIZE (mode) > UNITS_PER_FPREG)
8273 gcc_assert (GET_MODE_SIZE (mode) == UNITS_PER_HWFPVALUE);
8274 high = mips_subword (reg, true);
8275 low = mips_subword (reg, false);
8276 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, high, low));
8282 /* Implement ASM_OUTPUT_ASCII. */
8285 mips_output_ascii (FILE *stream, const char *string, size_t len)
8291 fprintf (stream, "\t.ascii\t\"");
8292 for (i = 0; i < len; i++)
8296 c = (unsigned char) string[i];
8299 if (c == '\\' || c == '\"')
8301 putc ('\\', stream);
8309 fprintf (stream, "\\%03o", c);
8313 if (cur_pos > 72 && i+1 < len)
8316 fprintf (stream, "\"\n\t.ascii\t\"");
8319 fprintf (stream, "\"\n");
8322 /* Return the pseudo-op for full SYMBOL_(D)TPREL address *ADDR.
8323 Update *ADDR with the operand that should be printed. */
8326 mips_output_tls_reloc_directive (rtx *addr)
8328 enum mips_symbol_type type;
8330 type = mips_classify_symbolic_expression (*addr, SYMBOL_CONTEXT_LEA);
8331 *addr = mips_strip_unspec_address (*addr);
8335 return Pmode == SImode ? ".dtprelword\t%0" : ".dtpreldword\t%0";
8338 return Pmode == SImode ? ".tprelword\t%0" : ".tpreldword\t%0";
8345 /* Emit either a label, .comm, or .lcomm directive. When using assembler
8346 macros, mark the symbol as written so that mips_asm_output_external
8347 won't emit an .extern for it. STREAM is the output file, NAME is the
8348 name of the symbol, INIT_STRING is the string that should be written
8349 before the symbol and FINAL_STRING is the string that should be
8350 written after it. FINAL_STRING is a printf format that consumes the
8351 remaining arguments. */
8354 mips_declare_object (FILE *stream, const char *name, const char *init_string,
8355 const char *final_string, ...)
8359 fputs (init_string, stream);
8360 assemble_name (stream, name);
8361 va_start (ap, final_string);
8362 vfprintf (stream, final_string, ap);
8365 if (!TARGET_EXPLICIT_RELOCS)
8367 tree name_tree = get_identifier (name);
8368 TREE_ASM_WRITTEN (name_tree) = 1;
8372 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
8373 NAME is the name of the object and ALIGN is the required alignment
8374 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
8375 alignment argument. */
8378 mips_declare_common_object (FILE *stream, const char *name,
8379 const char *init_string,
8380 unsigned HOST_WIDE_INT size,
8381 unsigned int align, bool takes_alignment_p)
8383 if (!takes_alignment_p)
8385 size += (align / BITS_PER_UNIT) - 1;
8386 size -= size % (align / BITS_PER_UNIT);
8387 mips_declare_object (stream, name, init_string,
8388 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
8391 mips_declare_object (stream, name, init_string,
8392 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
8393 size, align / BITS_PER_UNIT);
8396 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
8397 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
8400 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
8401 unsigned HOST_WIDE_INT size,
8404 /* If the target wants uninitialized const declarations in
8405 .rdata then don't put them in .comm. */
8406 if (TARGET_EMBEDDED_DATA
8407 && TARGET_UNINIT_CONST_IN_RODATA
8408 && TREE_CODE (decl) == VAR_DECL
8409 && TREE_READONLY (decl)
8410 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
8412 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
8413 targetm.asm_out.globalize_label (stream, name);
8415 switch_to_section (readonly_data_section);
8416 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
8417 mips_declare_object (stream, name, "",
8418 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
8422 mips_declare_common_object (stream, name, "\n\t.comm\t",
8426 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8427 extern int size_directive_output;
8429 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
8430 definitions except that it uses mips_declare_object to emit the label. */
8433 mips_declare_object_name (FILE *stream, const char *name,
8434 tree decl ATTRIBUTE_UNUSED)
8436 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8437 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
8440 size_directive_output = 0;
8441 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
8445 size_directive_output = 1;
8446 size = int_size_in_bytes (TREE_TYPE (decl));
8447 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8450 mips_declare_object (stream, name, "", ":\n");
8453 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
8456 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
8460 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
8461 if (!flag_inhibit_size_directive
8462 && DECL_SIZE (decl) != 0
8465 && DECL_INITIAL (decl) == error_mark_node
8466 && !size_directive_output)
8470 size_directive_output = 1;
8471 size = int_size_in_bytes (TREE_TYPE (decl));
8472 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8477 /* Return the FOO in the name of the ".mdebug.FOO" section associated
8478 with the current ABI. */
8481 mips_mdebug_abi_name (void)
8494 return TARGET_64BIT ? "eabi64" : "eabi32";
8500 /* Implement TARGET_ASM_FILE_START. */
8503 mips_file_start (void)
8505 default_file_start ();
8507 /* Generate a special section to describe the ABI switches used to
8508 produce the resultant binary. */
8510 /* Record the ABI itself. Modern versions of binutils encode
8511 this information in the ELF header flags, but GDB needs the
8512 information in order to correctly debug binaries produced by
8513 older binutils. See the function mips_gdbarch_init in
8515 fprintf (asm_out_file, "\t.section .mdebug.%s\n\t.previous\n",
8516 mips_mdebug_abi_name ());
8518 /* There is no ELF header flag to distinguish long32 forms of the
8519 EABI from long64 forms. Emit a special section to help tools
8520 such as GDB. Do the same for o64, which is sometimes used with
8522 if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
8523 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n"
8524 "\t.previous\n", TARGET_LONG64 ? 64 : 32);
8526 #ifdef HAVE_AS_GNU_ATTRIBUTE
8530 /* No floating-point operations, -mno-float. */
8531 if (TARGET_NO_FLOAT)
8533 /* Soft-float code, -msoft-float. */
8534 else if (!TARGET_HARD_FLOAT_ABI)
8536 /* Single-float code, -msingle-float. */
8537 else if (!TARGET_DOUBLE_FLOAT)
8539 /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64. */
8540 else if (!TARGET_64BIT && TARGET_FLOAT64)
8542 /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */
8546 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n", attr);
8550 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
8551 if (TARGET_ABICALLS)
8553 fprintf (asm_out_file, "\t.abicalls\n");
8554 if (TARGET_ABICALLS_PIC0)
8555 fprintf (asm_out_file, "\t.option\tpic0\n");
8558 if (flag_verbose_asm)
8559 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
8561 mips_small_data_threshold, mips_arch_info->name, mips_isa);
8564 /* Implement TARGET_ASM_CODE_END. */
8567 mips_code_end (void)
8569 if (mips_need_mips16_rdhwr_p)
8570 mips_output_mips16_rdhwr ();
8573 /* Make the last instruction frame-related and note that it performs
8574 the operation described by FRAME_PATTERN. */
8577 mips_set_frame_expr (rtx frame_pattern)
8581 insn = get_last_insn ();
8582 RTX_FRAME_RELATED_P (insn) = 1;
8583 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
8588 /* Return a frame-related rtx that stores REG at MEM.
8589 REG must be a single register. */
8592 mips_frame_set (rtx mem, rtx reg)
8596 set = gen_rtx_SET (VOIDmode, mem, reg);
8597 RTX_FRAME_RELATED_P (set) = 1;
8602 /* Record that the epilogue has restored call-saved register REG. */
8605 mips_add_cfa_restore (rtx reg)
8607 mips_epilogue.cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg,
8608 mips_epilogue.cfa_restores);
8611 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
8612 mips16e_s2_s8_regs[X], it must also save the registers in indexes
8613 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
8614 static const unsigned char mips16e_s2_s8_regs[] = {
8615 30, 23, 22, 21, 20, 19, 18
8617 static const unsigned char mips16e_a0_a3_regs[] = {
8621 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
8622 ordered from the uppermost in memory to the lowest in memory. */
8623 static const unsigned char mips16e_save_restore_regs[] = {
8624 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
8627 /* Return the index of the lowest X in the range [0, SIZE) for which
8628 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
8631 mips16e_find_first_register (unsigned int mask, const unsigned char *regs,
8636 for (i = 0; i < size; i++)
8637 if (BITSET_P (mask, regs[i]))
8643 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
8644 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
8645 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
8646 is true for all indexes (X, SIZE). */
8649 mips16e_mask_registers (unsigned int *mask_ptr, const unsigned char *regs,
8650 unsigned int size, unsigned int *num_regs_ptr)
8654 i = mips16e_find_first_register (*mask_ptr, regs, size);
8655 for (i++; i < size; i++)
8656 if (!BITSET_P (*mask_ptr, regs[i]))
8659 *mask_ptr |= 1 << regs[i];
8663 /* Return a simplified form of X using the register values in REG_VALUES.
8664 REG_VALUES[R] is the last value assigned to hard register R, or null
8665 if R has not been modified.
8667 This function is rather limited, but is good enough for our purposes. */
8670 mips16e_collect_propagate_value (rtx x, rtx *reg_values)
8672 x = avoid_constant_pool_reference (x);
8676 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
8677 return simplify_gen_unary (GET_CODE (x), GET_MODE (x),
8678 x0, GET_MODE (XEXP (x, 0)));
8681 if (ARITHMETIC_P (x))
8683 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
8684 rtx x1 = mips16e_collect_propagate_value (XEXP (x, 1), reg_values);
8685 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), x0, x1);
8689 && reg_values[REGNO (x)]
8690 && !rtx_unstable_p (reg_values[REGNO (x)]))
8691 return reg_values[REGNO (x)];
8696 /* Return true if (set DEST SRC) stores an argument register into its
8697 caller-allocated save slot, storing the number of that argument
8698 register in *REGNO_PTR if so. REG_VALUES is as for
8699 mips16e_collect_propagate_value. */
8702 mips16e_collect_argument_save_p (rtx dest, rtx src, rtx *reg_values,
8703 unsigned int *regno_ptr)
8705 unsigned int argno, regno;
8706 HOST_WIDE_INT offset, required_offset;
8709 /* Check that this is a word-mode store. */
8710 if (!MEM_P (dest) || !REG_P (src) || GET_MODE (dest) != word_mode)
8713 /* Check that the register being saved is an unmodified argument
8715 regno = REGNO (src);
8716 if (!IN_RANGE (regno, GP_ARG_FIRST, GP_ARG_LAST) || reg_values[regno])
8718 argno = regno - GP_ARG_FIRST;
8720 /* Check whether the address is an appropriate stack-pointer or
8721 frame-pointer access. */
8722 addr = mips16e_collect_propagate_value (XEXP (dest, 0), reg_values);
8723 mips_split_plus (addr, &base, &offset);
8724 required_offset = cfun->machine->frame.total_size + argno * UNITS_PER_WORD;
8725 if (base == hard_frame_pointer_rtx)
8726 required_offset -= cfun->machine->frame.hard_frame_pointer_offset;
8727 else if (base != stack_pointer_rtx)
8729 if (offset != required_offset)
8736 /* A subroutine of mips_expand_prologue, called only when generating
8737 MIPS16e SAVE instructions. Search the start of the function for any
8738 instructions that save argument registers into their caller-allocated
8739 save slots. Delete such instructions and return a value N such that
8740 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
8741 instructions redundant. */
8744 mips16e_collect_argument_saves (void)
8746 rtx reg_values[FIRST_PSEUDO_REGISTER];
8747 rtx insn, next, set, dest, src;
8748 unsigned int nargs, regno;
8750 push_topmost_sequence ();
8752 memset (reg_values, 0, sizeof (reg_values));
8753 for (insn = get_insns (); insn; insn = next)
8755 next = NEXT_INSN (insn);
8756 if (NOTE_P (insn) || DEBUG_INSN_P (insn))
8762 set = PATTERN (insn);
8763 if (GET_CODE (set) != SET)
8766 dest = SET_DEST (set);
8767 src = SET_SRC (set);
8768 if (mips16e_collect_argument_save_p (dest, src, reg_values, ®no))
8770 if (!BITSET_P (cfun->machine->frame.mask, regno))
8773 nargs = MAX (nargs, (regno - GP_ARG_FIRST) + 1);
8776 else if (REG_P (dest) && GET_MODE (dest) == word_mode)
8777 reg_values[REGNO (dest)]
8778 = mips16e_collect_propagate_value (src, reg_values);
8782 pop_topmost_sequence ();
8787 /* Return a move between register REGNO and memory location SP + OFFSET.
8788 REG_PARM_P is true if SP + OFFSET belongs to REG_PARM_STACK_SPACE.
8789 Make the move a load if RESTORE_P, otherwise make it a store. */
8792 mips16e_save_restore_reg (bool restore_p, bool reg_parm_p,
8793 HOST_WIDE_INT offset, unsigned int regno)
8797 mem = gen_frame_mem (SImode, plus_constant (Pmode, stack_pointer_rtx,
8799 reg = gen_rtx_REG (SImode, regno);
8802 mips_add_cfa_restore (reg);
8803 return gen_rtx_SET (VOIDmode, reg, mem);
8806 return gen_rtx_SET (VOIDmode, mem, reg);
8807 return mips_frame_set (mem, reg);
8810 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
8811 The instruction must:
8813 - Allocate or deallocate SIZE bytes in total; SIZE is known
8816 - Save or restore as many registers in *MASK_PTR as possible.
8817 The instruction saves the first registers at the top of the
8818 allocated area, with the other registers below it.
8820 - Save NARGS argument registers above the allocated area.
8822 (NARGS is always zero if RESTORE_P.)
8824 The SAVE and RESTORE instructions cannot save and restore all general
8825 registers, so there may be some registers left over for the caller to
8826 handle. Destructively modify *MASK_PTR so that it contains the registers
8827 that still need to be saved or restored. The caller can save these
8828 registers in the memory immediately below *OFFSET_PTR, which is a
8829 byte offset from the bottom of the allocated stack area. */
8832 mips16e_build_save_restore (bool restore_p, unsigned int *mask_ptr,
8833 HOST_WIDE_INT *offset_ptr, unsigned int nargs,
8837 HOST_WIDE_INT offset, top_offset;
8838 unsigned int i, regno;
8841 gcc_assert (cfun->machine->frame.num_fp == 0);
8843 /* Calculate the number of elements in the PARALLEL. We need one element
8844 for the stack adjustment, one for each argument register save, and one
8845 for each additional register move. */
8847 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
8848 if (BITSET_P (*mask_ptr, mips16e_save_restore_regs[i]))
8851 /* Create the final PARALLEL. */
8852 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (n));
8855 /* Add the stack pointer adjustment. */
8856 set = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8857 plus_constant (Pmode, stack_pointer_rtx,
8858 restore_p ? size : -size));
8859 RTX_FRAME_RELATED_P (set) = 1;
8860 XVECEXP (pattern, 0, n++) = set;
8862 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8863 top_offset = restore_p ? size : 0;
8865 /* Save the arguments. */
8866 for (i = 0; i < nargs; i++)
8868 offset = top_offset + i * UNITS_PER_WORD;
8869 set = mips16e_save_restore_reg (restore_p, true, offset,
8871 XVECEXP (pattern, 0, n++) = set;
8874 /* Then fill in the other register moves. */
8875 offset = top_offset;
8876 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
8878 regno = mips16e_save_restore_regs[i];
8879 if (BITSET_P (*mask_ptr, regno))
8881 offset -= UNITS_PER_WORD;
8882 set = mips16e_save_restore_reg (restore_p, false, offset, regno);
8883 XVECEXP (pattern, 0, n++) = set;
8884 *mask_ptr &= ~(1 << regno);
8888 /* Tell the caller what offset it should use for the remaining registers. */
8889 *offset_ptr = size + (offset - top_offset);
8891 gcc_assert (n == XVECLEN (pattern, 0));
8896 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
8897 pointer. Return true if PATTERN matches the kind of instruction
8898 generated by mips16e_build_save_restore. If INFO is nonnull,
8899 initialize it when returning true. */
8902 mips16e_save_restore_pattern_p (rtx pattern, HOST_WIDE_INT adjust,
8903 struct mips16e_save_restore_info *info)
8905 unsigned int i, nargs, mask, extra;
8906 HOST_WIDE_INT top_offset, save_offset, offset;
8907 rtx set, reg, mem, base;
8910 if (!GENERATE_MIPS16E_SAVE_RESTORE)
8913 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8914 top_offset = adjust > 0 ? adjust : 0;
8916 /* Interpret all other members of the PARALLEL. */
8917 save_offset = top_offset - UNITS_PER_WORD;
8921 for (n = 1; n < XVECLEN (pattern, 0); n++)
8923 /* Check that we have a SET. */
8924 set = XVECEXP (pattern, 0, n);
8925 if (GET_CODE (set) != SET)
8928 /* Check that the SET is a load (if restoring) or a store
8930 mem = adjust > 0 ? SET_SRC (set) : SET_DEST (set);
8934 /* Check that the address is the sum of the stack pointer and a
8935 possibly-zero constant offset. */
8936 mips_split_plus (XEXP (mem, 0), &base, &offset);
8937 if (base != stack_pointer_rtx)
8940 /* Check that SET's other operand is a register. */
8941 reg = adjust > 0 ? SET_DEST (set) : SET_SRC (set);
8945 /* Check for argument saves. */
8946 if (offset == top_offset + nargs * UNITS_PER_WORD
8947 && REGNO (reg) == GP_ARG_FIRST + nargs)
8949 else if (offset == save_offset)
8951 while (mips16e_save_restore_regs[i++] != REGNO (reg))
8952 if (i == ARRAY_SIZE (mips16e_save_restore_regs))
8955 mask |= 1 << REGNO (reg);
8956 save_offset -= UNITS_PER_WORD;
8962 /* Check that the restrictions on register ranges are met. */
8964 mips16e_mask_registers (&mask, mips16e_s2_s8_regs,
8965 ARRAY_SIZE (mips16e_s2_s8_regs), &extra);
8966 mips16e_mask_registers (&mask, mips16e_a0_a3_regs,
8967 ARRAY_SIZE (mips16e_a0_a3_regs), &extra);
8971 /* Make sure that the topmost argument register is not saved twice.
8972 The checks above ensure that the same is then true for the other
8973 argument registers. */
8974 if (nargs > 0 && BITSET_P (mask, GP_ARG_FIRST + nargs - 1))
8977 /* Pass back information, if requested. */
8980 info->nargs = nargs;
8982 info->size = (adjust > 0 ? adjust : -adjust);
8988 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
8989 for the register range [MIN_REG, MAX_REG]. Return a pointer to
8990 the null terminator. */
8993 mips16e_add_register_range (char *s, unsigned int min_reg,
8994 unsigned int max_reg)
8996 if (min_reg != max_reg)
8997 s += sprintf (s, ",%s-%s", reg_names[min_reg], reg_names[max_reg]);
8999 s += sprintf (s, ",%s", reg_names[min_reg]);
9003 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
9004 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
9007 mips16e_output_save_restore (rtx pattern, HOST_WIDE_INT adjust)
9009 static char buffer[300];
9011 struct mips16e_save_restore_info info;
9012 unsigned int i, end;
9015 /* Parse the pattern. */
9016 if (!mips16e_save_restore_pattern_p (pattern, adjust, &info))
9019 /* Add the mnemonic. */
9020 s = strcpy (buffer, adjust > 0 ? "restore\t" : "save\t");
9023 /* Save the arguments. */
9025 s += sprintf (s, "%s-%s,", reg_names[GP_ARG_FIRST],
9026 reg_names[GP_ARG_FIRST + info.nargs - 1]);
9027 else if (info.nargs == 1)
9028 s += sprintf (s, "%s,", reg_names[GP_ARG_FIRST]);
9030 /* Emit the amount of stack space to allocate or deallocate. */
9031 s += sprintf (s, "%d", (int) info.size);
9033 /* Save or restore $16. */
9034 if (BITSET_P (info.mask, 16))
9035 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 16]);
9037 /* Save or restore $17. */
9038 if (BITSET_P (info.mask, 17))
9039 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 17]);
9041 /* Save or restore registers in the range $s2...$s8, which
9042 mips16e_s2_s8_regs lists in decreasing order. Note that this
9043 is a software register range; the hardware registers are not
9044 numbered consecutively. */
9045 end = ARRAY_SIZE (mips16e_s2_s8_regs);
9046 i = mips16e_find_first_register (info.mask, mips16e_s2_s8_regs, end);
9048 s = mips16e_add_register_range (s, mips16e_s2_s8_regs[end - 1],
9049 mips16e_s2_s8_regs[i]);
9051 /* Save or restore registers in the range $a0...$a3. */
9052 end = ARRAY_SIZE (mips16e_a0_a3_regs);
9053 i = mips16e_find_first_register (info.mask, mips16e_a0_a3_regs, end);
9055 s = mips16e_add_register_range (s, mips16e_a0_a3_regs[i],
9056 mips16e_a0_a3_regs[end - 1]);
9058 /* Save or restore $31. */
9059 if (BITSET_P (info.mask, RETURN_ADDR_REGNUM))
9060 s += sprintf (s, ",%s", reg_names[RETURN_ADDR_REGNUM]);
9065 /* Return true if the current function returns its value in a floating-point
9066 register in MIPS16 mode. */
9069 mips16_cfun_returns_in_fpr_p (void)
9071 tree return_type = DECL_RESULT (current_function_decl);
9072 return (TARGET_MIPS16
9073 && TARGET_HARD_FLOAT_ABI
9074 && !aggregate_value_p (return_type, current_function_decl)
9075 && mips_return_mode_in_fpr_p (DECL_MODE (return_type)));
9078 /* Return true if predicate PRED is true for at least one instruction.
9079 Cache the result in *CACHE, and assume that the result is true
9080 if *CACHE is already true. */
9083 mips_find_gp_ref (bool *cache, bool (*pred) (rtx))
9089 push_topmost_sequence ();
9090 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9091 if (USEFUL_INSN_P (insn) && pred (insn))
9096 pop_topmost_sequence ();
9101 /* Return true if INSN refers to the global pointer in an "inflexible" way.
9102 See mips_cfun_has_inflexible_gp_ref_p for details. */
9105 mips_insn_has_inflexible_gp_ref_p (rtx insn)
9107 /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE
9108 indicate that the target could be a traditional MIPS
9109 lazily-binding stub. */
9110 return find_reg_fusage (insn, USE, pic_offset_table_rtx);
9113 /* Return true if the current function refers to the global pointer
9114 in a way that forces $28 to be valid. This means that we can't
9115 change the choice of global pointer, even for NewABI code.
9117 One example of this (and one which needs several checks) is that
9118 $28 must be valid when calling traditional MIPS lazy-binding stubs.
9119 (This restriction does not apply to PLTs.) */
9122 mips_cfun_has_inflexible_gp_ref_p (void)
9124 /* If the function has a nonlocal goto, $28 must hold the correct
9125 global pointer for the target function. That is, the target
9126 of the goto implicitly uses $28. */
9127 if (crtl->has_nonlocal_goto)
9130 if (TARGET_ABICALLS_PIC2)
9132 /* Symbolic accesses implicitly use the global pointer unless
9133 -mexplicit-relocs is in effect. JAL macros to symbolic addresses
9134 might go to traditional MIPS lazy-binding stubs. */
9135 if (!TARGET_EXPLICIT_RELOCS)
9138 /* FUNCTION_PROFILER includes a JAL to _mcount, which again
9139 can be lazily-bound. */
9143 /* MIPS16 functions that return in FPRs need to call an
9144 external libgcc routine. This call is only made explict
9145 during mips_expand_epilogue, and it too might be lazily bound. */
9146 if (mips16_cfun_returns_in_fpr_p ())
9150 return mips_find_gp_ref (&cfun->machine->has_inflexible_gp_insn_p,
9151 mips_insn_has_inflexible_gp_ref_p);
9154 /* Return true if INSN refers to the global pointer in a "flexible" way.
9155 See mips_cfun_has_flexible_gp_ref_p for details. */
9158 mips_insn_has_flexible_gp_ref_p (rtx insn)
9160 return (get_attr_got (insn) != GOT_UNSET
9161 || mips_small_data_pattern_p (PATTERN (insn))
9162 || reg_overlap_mentioned_p (pic_offset_table_rtx, PATTERN (insn)));
9165 /* Return true if the current function references the global pointer,
9166 but if those references do not inherently require the global pointer
9167 to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */
9170 mips_cfun_has_flexible_gp_ref_p (void)
9172 /* Reload can sometimes introduce constant pool references
9173 into a function that otherwise didn't need them. For example,
9174 suppose we have an instruction like:
9176 (set (reg:DF R1) (float:DF (reg:SI R2)))
9178 If R2 turns out to be a constant such as 1, the instruction may
9179 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
9180 the option of using this constant if R2 doesn't get allocated
9183 In cases like these, reload will have added the constant to the
9184 pool but no instruction will yet refer to it. */
9185 if (TARGET_ABICALLS_PIC2 && !reload_completed && crtl->uses_const_pool)
9188 return mips_find_gp_ref (&cfun->machine->has_flexible_gp_insn_p,
9189 mips_insn_has_flexible_gp_ref_p);
9192 /* Return the register that should be used as the global pointer
9193 within this function. Return INVALID_REGNUM if the function
9194 doesn't need a global pointer. */
9197 mips_global_pointer (void)
9201 /* $gp is always available unless we're using a GOT. */
9202 if (!TARGET_USE_GOT)
9203 return GLOBAL_POINTER_REGNUM;
9205 /* If there are inflexible references to $gp, we must use the
9206 standard register. */
9207 if (mips_cfun_has_inflexible_gp_ref_p ())
9208 return GLOBAL_POINTER_REGNUM;
9210 /* If there are no current references to $gp, then the only uses
9211 we can introduce later are those involved in long branches. */
9212 if (TARGET_ABSOLUTE_JUMPS && !mips_cfun_has_flexible_gp_ref_p ())
9213 return INVALID_REGNUM;
9215 /* If the global pointer is call-saved, try to use a call-clobbered
9217 if (TARGET_CALL_SAVED_GP && current_function_is_leaf)
9218 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
9219 if (!df_regs_ever_live_p (regno)
9220 && call_really_used_regs[regno]
9221 && !fixed_regs[regno]
9222 && regno != PIC_FUNCTION_ADDR_REGNUM)
9225 return GLOBAL_POINTER_REGNUM;
9228 /* Return true if the current function's prologue must load the global
9229 pointer value into pic_offset_table_rtx and store the same value in
9230 the function's cprestore slot (if any).
9232 One problem we have to deal with is that, when emitting GOT-based
9233 position independent code, long-branch sequences will need to load
9234 the address of the branch target from the GOT. We don't know until
9235 the very end of compilation whether (and where) the function needs
9236 long branches, so we must ensure that _any_ branch can access the
9237 global pointer in some form. However, we do not want to pessimize
9238 the usual case in which all branches are short.
9240 We handle this as follows:
9242 (1) During reload, we set cfun->machine->global_pointer to
9243 INVALID_REGNUM if we _know_ that the current function
9244 doesn't need a global pointer. This is only valid if
9245 long branches don't need the GOT.
9247 Otherwise, we assume that we might need a global pointer
9248 and pick an appropriate register.
9250 (2) If cfun->machine->global_pointer != INVALID_REGNUM,
9251 we ensure that the global pointer is available at every
9252 block boundary bar entry and exit. We do this in one of two ways:
9254 - If the function has a cprestore slot, we ensure that this
9255 slot is valid at every branch. However, as explained in
9256 point (6) below, there is no guarantee that pic_offset_table_rtx
9257 itself is valid if new uses of the global pointer are introduced
9258 after the first post-epilogue split.
9260 We guarantee that the cprestore slot is valid by loading it
9261 into a fake register, CPRESTORE_SLOT_REGNUM. We then make
9262 this register live at every block boundary bar function entry
9263 and exit. It is then invalid to move the load (and thus the
9264 preceding store) across a block boundary.
9266 - If the function has no cprestore slot, we guarantee that
9267 pic_offset_table_rtx itself is valid at every branch.
9269 See mips_eh_uses for the handling of the register liveness.
9271 (3) During prologue and epilogue generation, we emit "ghost"
9272 placeholder instructions to manipulate the global pointer.
9274 (4) During prologue generation, we set cfun->machine->must_initialize_gp_p
9275 and cfun->machine->must_restore_gp_when_clobbered_p if we already know
9276 that the function needs a global pointer. (There is no need to set
9277 them earlier than this, and doing it as late as possible leads to
9278 fewer false positives.)
9280 (5) If cfun->machine->must_initialize_gp_p is true during a
9281 split_insns pass, we split the ghost instructions into real
9282 instructions. These split instructions can then be optimized in
9283 the usual way. Otherwise, we keep the ghost instructions intact,
9284 and optimize for the case where they aren't needed. We still
9285 have the option of splitting them later, if we need to introduce
9286 new uses of the global pointer.
9288 For example, the scheduler ignores a ghost instruction that
9289 stores $28 to the stack, but it handles the split form of
9290 the ghost instruction as an ordinary store.
9292 (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p
9293 is true during the first post-epilogue split_insns pass, we split
9294 calls and restore_gp patterns into instructions that explicitly
9295 load pic_offset_table_rtx from the cprestore slot. Otherwise,
9296 we split these patterns into instructions that _don't_ load from
9299 If cfun->machine->must_restore_gp_when_clobbered_p is true at the
9300 time of the split, then any instructions that exist at that time
9301 can make free use of pic_offset_table_rtx. However, if we want
9302 to introduce new uses of the global pointer after the split,
9303 we must explicitly load the value from the cprestore slot, since
9304 pic_offset_table_rtx itself might not be valid at a given point
9307 The idea is that we want to be able to delete redundant
9308 loads from the cprestore slot in the usual case where no
9309 long branches are needed.
9311 (7) If cfun->machine->must_initialize_gp_p is still false at the end
9312 of md_reorg, we decide whether the global pointer is needed for
9313 long branches. If so, we set cfun->machine->must_initialize_gp_p
9314 to true and split the ghost instructions into real instructions
9317 Note that the ghost instructions must have a zero length for three reasons:
9319 - Giving the length of the underlying $gp sequence might cause
9320 us to use long branches in cases where they aren't really needed.
9322 - They would perturb things like alignment calculations.
9324 - More importantly, the hazard detection in md_reorg relies on
9325 empty instructions having a zero length.
9327 If we find a long branch and split the ghost instructions at the
9328 end of md_reorg, the split could introduce more long branches.
9329 That isn't a problem though, because we still do the split before
9330 the final shorten_branches pass.
9332 This is extremely ugly, but it seems like the best compromise between
9333 correctness and efficiency. */
9336 mips_must_initialize_gp_p (void)
9338 return cfun->machine->must_initialize_gp_p;
9341 /* Return true if REGNO is a register that is ordinarily call-clobbered
9342 but must nevertheless be preserved by an interrupt handler. */
9345 mips_interrupt_extra_call_saved_reg_p (unsigned int regno)
9347 if (MD_REG_P (regno))
9350 if (TARGET_DSP && DSP_ACC_REG_P (regno))
9353 if (GP_REG_P (regno) && !cfun->machine->use_shadow_register_set_p)
9355 /* $0 is hard-wired. */
9356 if (regno == GP_REG_FIRST)
9359 /* The interrupt handler can treat kernel registers as
9360 scratch registers. */
9361 if (KERNEL_REG_P (regno))
9364 /* The function will return the stack pointer to its original value
9366 if (regno == STACK_POINTER_REGNUM)
9369 /* Otherwise, return true for registers that aren't ordinarily
9371 return call_really_used_regs[regno];
9377 /* Return true if the current function should treat register REGNO
9381 mips_cfun_call_saved_reg_p (unsigned int regno)
9383 /* If the user makes an ordinarily-call-saved register global,
9384 that register is no longer call-saved. */
9385 if (global_regs[regno])
9388 /* Interrupt handlers need to save extra registers. */
9389 if (cfun->machine->interrupt_handler_p
9390 && mips_interrupt_extra_call_saved_reg_p (regno))
9393 /* call_insns preserve $28 unless they explicitly say otherwise,
9394 so call_really_used_regs[] treats $28 as call-saved. However,
9395 we want the ABI property rather than the default call_insn
9397 return (regno == GLOBAL_POINTER_REGNUM
9398 ? TARGET_CALL_SAVED_GP
9399 : !call_really_used_regs[regno]);
9402 /* Return true if the function body might clobber register REGNO.
9403 We know that REGNO is call-saved. */
9406 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno)
9408 /* Some functions should be treated as clobbering all call-saved
9410 if (crtl->saves_all_registers)
9413 /* DF handles cases where a register is explicitly referenced in
9414 the rtl. Incoming values are passed in call-clobbered registers,
9415 so we can assume that any live call-saved register is set within
9417 if (df_regs_ever_live_p (regno))
9420 /* Check for registers that are clobbered by FUNCTION_PROFILER.
9421 These clobbers are not explicit in the rtl. */
9422 if (crtl->profile && MIPS_SAVE_REG_FOR_PROFILING_P (regno))
9425 /* If we're using a call-saved global pointer, the function's
9426 prologue will need to set it up. */
9427 if (cfun->machine->global_pointer == regno)
9430 /* The function's prologue will need to set the frame pointer if
9431 frame_pointer_needed. */
9432 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
9435 /* If a MIPS16 function returns a value in FPRs, its epilogue
9436 will need to call an external libgcc routine. This yet-to-be
9437 generated call_insn will clobber $31. */
9438 if (regno == RETURN_ADDR_REGNUM && mips16_cfun_returns_in_fpr_p ())
9441 /* If REGNO is ordinarily call-clobbered, we must assume that any
9442 called function could modify it. */
9443 if (cfun->machine->interrupt_handler_p
9444 && !current_function_is_leaf
9445 && mips_interrupt_extra_call_saved_reg_p (regno))
9451 /* Return true if the current function must save register REGNO. */
9454 mips_save_reg_p (unsigned int regno)
9456 if (mips_cfun_call_saved_reg_p (regno))
9458 if (mips_cfun_might_clobber_call_saved_reg_p (regno))
9461 /* Save both registers in an FPR pair if either one is used. This is
9462 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
9463 register to be used without the even register. */
9464 if (FP_REG_P (regno)
9465 && MAX_FPRS_PER_FMT == 2
9466 && mips_cfun_might_clobber_call_saved_reg_p (regno + 1))
9470 /* We need to save the incoming return address if __builtin_eh_return
9471 is being used to set a different return address. */
9472 if (regno == RETURN_ADDR_REGNUM && crtl->calls_eh_return)
9478 /* Populate the current function's mips_frame_info structure.
9480 MIPS stack frames look like:
9482 +-------------------------------+
9484 | incoming stack arguments |
9486 +-------------------------------+
9488 | caller-allocated save area |
9489 A | for register arguments |
9491 +-------------------------------+ <-- incoming stack pointer
9493 | callee-allocated save area |
9494 B | for arguments that are |
9495 | split between registers and |
9498 +-------------------------------+ <-- arg_pointer_rtx
9500 C | callee-allocated save area |
9501 | for register varargs |
9503 +-------------------------------+ <-- frame_pointer_rtx
9504 | | + cop0_sp_offset
9505 | COP0 reg save area | + UNITS_PER_WORD
9507 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
9508 | | + UNITS_PER_WORD
9509 | accumulator save area |
9511 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
9512 | | + UNITS_PER_HWFPVALUE
9515 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset
9516 | | + UNITS_PER_WORD
9519 +-------------------------------+ <-- frame_pointer_rtx with
9520 | | \ -fstack-protector
9521 | local variables | | var_size
9523 +-------------------------------+
9525 | $gp save area | | cprestore_size
9527 P +-------------------------------+ <-- hard_frame_pointer_rtx for
9529 | outgoing stack arguments | |
9531 +-------------------------------+ | args_size
9533 | caller-allocated save area | |
9534 | for register arguments | |
9536 +-------------------------------+ <-- stack_pointer_rtx
9537 frame_pointer_rtx without
9539 hard_frame_pointer_rtx for
9542 At least two of A, B and C will be empty.
9544 Dynamic stack allocations such as alloca insert data at point P.
9545 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
9546 hard_frame_pointer_rtx unchanged. */
9549 mips_compute_frame_info (void)
9551 struct mips_frame_info *frame;
9552 HOST_WIDE_INT offset, size;
9553 unsigned int regno, i;
9555 /* Set this function's interrupt properties. */
9556 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
9559 error ("the %<interrupt%> attribute requires a MIPS32r2 processor");
9560 else if (TARGET_HARD_FLOAT)
9561 error ("the %<interrupt%> attribute requires %<-msoft-float%>");
9562 else if (TARGET_MIPS16)
9563 error ("interrupt handlers cannot be MIPS16 functions");
9566 cfun->machine->interrupt_handler_p = true;
9567 cfun->machine->use_shadow_register_set_p =
9568 mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl));
9569 cfun->machine->keep_interrupts_masked_p =
9570 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl));
9571 cfun->machine->use_debug_exception_return_p =
9572 mips_use_debug_exception_return_p (TREE_TYPE
9573 (current_function_decl));
9577 frame = &cfun->machine->frame;
9578 memset (frame, 0, sizeof (*frame));
9579 size = get_frame_size ();
9581 cfun->machine->global_pointer = mips_global_pointer ();
9583 /* The first two blocks contain the outgoing argument area and the $gp save
9584 slot. This area isn't needed in leaf functions, but if the
9585 target-independent frame size is nonzero, we have already committed to
9586 allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */
9587 if ((size == 0 || FRAME_GROWS_DOWNWARD) && current_function_is_leaf)
9589 /* The MIPS 3.0 linker does not like functions that dynamically
9590 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
9591 looks like we are trying to create a second frame pointer to the
9592 function, so allocate some stack space to make it happy. */
9593 if (cfun->calls_alloca)
9594 frame->args_size = REG_PARM_STACK_SPACE (cfun->decl);
9596 frame->args_size = 0;
9597 frame->cprestore_size = 0;
9601 frame->args_size = crtl->outgoing_args_size;
9602 frame->cprestore_size = MIPS_GP_SAVE_AREA_SIZE;
9604 offset = frame->args_size + frame->cprestore_size;
9606 /* Move above the local variables. */
9607 frame->var_size = MIPS_STACK_ALIGN (size);
9608 offset += frame->var_size;
9610 /* Find out which GPRs we need to save. */
9611 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
9612 if (mips_save_reg_p (regno))
9615 frame->mask |= 1 << (regno - GP_REG_FIRST);
9618 /* If this function calls eh_return, we must also save and restore the
9619 EH data registers. */
9620 if (crtl->calls_eh_return)
9621 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; i++)
9624 frame->mask |= 1 << (EH_RETURN_DATA_REGNO (i) - GP_REG_FIRST);
9627 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
9628 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
9629 save all later registers too. */
9630 if (GENERATE_MIPS16E_SAVE_RESTORE)
9632 mips16e_mask_registers (&frame->mask, mips16e_s2_s8_regs,
9633 ARRAY_SIZE (mips16e_s2_s8_regs), &frame->num_gp);
9634 mips16e_mask_registers (&frame->mask, mips16e_a0_a3_regs,
9635 ARRAY_SIZE (mips16e_a0_a3_regs), &frame->num_gp);
9638 /* Move above the GPR save area. */
9639 if (frame->num_gp > 0)
9641 offset += MIPS_STACK_ALIGN (frame->num_gp * UNITS_PER_WORD);
9642 frame->gp_sp_offset = offset - UNITS_PER_WORD;
9645 /* Find out which FPRs we need to save. This loop must iterate over
9646 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
9647 if (TARGET_HARD_FLOAT)
9648 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += MAX_FPRS_PER_FMT)
9649 if (mips_save_reg_p (regno))
9651 frame->num_fp += MAX_FPRS_PER_FMT;
9652 frame->fmask |= ~(~0 << MAX_FPRS_PER_FMT) << (regno - FP_REG_FIRST);
9655 /* Move above the FPR save area. */
9656 if (frame->num_fp > 0)
9658 offset += MIPS_STACK_ALIGN (frame->num_fp * UNITS_PER_FPREG);
9659 frame->fp_sp_offset = offset - UNITS_PER_HWFPVALUE;
9662 /* Add in space for the interrupt context information. */
9663 if (cfun->machine->interrupt_handler_p)
9666 if (mips_save_reg_p (LO_REGNUM) || mips_save_reg_p (HI_REGNUM))
9669 frame->acc_mask |= (1 << 0);
9672 /* Check accumulators 1, 2, 3. */
9673 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
9674 if (mips_save_reg_p (i) || mips_save_reg_p (i + 1))
9677 frame->acc_mask |= 1 << (((i - DSP_ACC_REG_FIRST) / 2) + 1);
9680 /* All interrupt context functions need space to preserve STATUS. */
9681 frame->num_cop0_regs++;
9683 /* If we don't keep interrupts masked, we need to save EPC. */
9684 if (!cfun->machine->keep_interrupts_masked_p)
9685 frame->num_cop0_regs++;
9688 /* Move above the accumulator save area. */
9689 if (frame->num_acc > 0)
9691 /* Each accumulator needs 2 words. */
9692 offset += frame->num_acc * 2 * UNITS_PER_WORD;
9693 frame->acc_sp_offset = offset - UNITS_PER_WORD;
9696 /* Move above the COP0 register save area. */
9697 if (frame->num_cop0_regs > 0)
9699 offset += frame->num_cop0_regs * UNITS_PER_WORD;
9700 frame->cop0_sp_offset = offset - UNITS_PER_WORD;
9703 /* Move above the callee-allocated varargs save area. */
9704 offset += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
9705 frame->arg_pointer_offset = offset;
9707 /* Move above the callee-allocated area for pretend stack arguments. */
9708 offset += crtl->args.pretend_args_size;
9709 frame->total_size = offset;
9711 /* Work out the offsets of the save areas from the top of the frame. */
9712 if (frame->gp_sp_offset > 0)
9713 frame->gp_save_offset = frame->gp_sp_offset - offset;
9714 if (frame->fp_sp_offset > 0)
9715 frame->fp_save_offset = frame->fp_sp_offset - offset;
9716 if (frame->acc_sp_offset > 0)
9717 frame->acc_save_offset = frame->acc_sp_offset - offset;
9718 if (frame->num_cop0_regs > 0)
9719 frame->cop0_save_offset = frame->cop0_sp_offset - offset;
9721 /* MIPS16 code offsets the frame pointer by the size of the outgoing
9722 arguments. This tends to increase the chances of using unextended
9723 instructions for local variables and incoming arguments. */
9725 frame->hard_frame_pointer_offset = frame->args_size;
9728 /* Return the style of GP load sequence that is being used for the
9729 current function. */
9731 enum mips_loadgp_style
9732 mips_current_loadgp_style (void)
9734 if (!TARGET_USE_GOT || cfun->machine->global_pointer == INVALID_REGNUM)
9740 if (TARGET_ABSOLUTE_ABICALLS)
9741 return LOADGP_ABSOLUTE;
9743 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
9746 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
9749 mips_frame_pointer_required (void)
9751 /* If the function contains dynamic stack allocations, we need to
9752 use the frame pointer to access the static parts of the frame. */
9753 if (cfun->calls_alloca)
9756 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
9757 reload may be unable to compute the address of a local variable,
9758 since there is no way to add a large constant to the stack pointer
9759 without using a second temporary register. */
9762 mips_compute_frame_info ();
9763 if (!SMALL_OPERAND (cfun->machine->frame.total_size))
9770 /* Make sure that we're not trying to eliminate to the wrong hard frame
9774 mips_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
9776 return (to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM);
9779 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
9780 or argument pointer. TO is either the stack pointer or hard frame
9784 mips_initial_elimination_offset (int from, int to)
9786 HOST_WIDE_INT offset;
9788 mips_compute_frame_info ();
9790 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */
9793 case FRAME_POINTER_REGNUM:
9794 if (FRAME_GROWS_DOWNWARD)
9795 offset = (cfun->machine->frame.args_size
9796 + cfun->machine->frame.cprestore_size
9797 + cfun->machine->frame.var_size);
9802 case ARG_POINTER_REGNUM:
9803 offset = cfun->machine->frame.arg_pointer_offset;
9810 if (to == HARD_FRAME_POINTER_REGNUM)
9811 offset -= cfun->machine->frame.hard_frame_pointer_offset;
9816 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
9819 mips_extra_live_on_entry (bitmap regs)
9823 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
9824 the global pointer. */
9825 if (!TARGET_ABSOLUTE_ABICALLS)
9826 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
9828 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
9829 the global pointer. */
9831 bitmap_set_bit (regs, MIPS16_PIC_TEMP_REGNUM);
9833 /* See the comment above load_call<mode> for details. */
9834 bitmap_set_bit (regs, GOT_VERSION_REGNUM);
9838 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
9842 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
9847 return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);
9850 /* Emit code to change the current function's return address to
9851 ADDRESS. SCRATCH is available as a scratch register, if needed.
9852 ADDRESS and SCRATCH are both word-mode GPRs. */
9855 mips_set_return_address (rtx address, rtx scratch)
9859 gcc_assert (BITSET_P (cfun->machine->frame.mask, RETURN_ADDR_REGNUM));
9860 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
9861 cfun->machine->frame.gp_sp_offset);
9862 mips_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address);
9865 /* Return true if the current function has a cprestore slot. */
9868 mips_cfun_has_cprestore_slot_p (void)
9870 return (cfun->machine->global_pointer != INVALID_REGNUM
9871 && cfun->machine->frame.cprestore_size > 0);
9874 /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the
9875 cprestore slot. LOAD_P is true if the caller wants to load from
9876 the cprestore slot; it is false if the caller wants to store to
9880 mips_get_cprestore_base_and_offset (rtx *base, HOST_WIDE_INT *offset,
9883 const struct mips_frame_info *frame;
9885 frame = &cfun->machine->frame;
9886 /* .cprestore always uses the stack pointer instead of the frame pointer.
9887 We have a free choice for direct stores for non-MIPS16 functions,
9888 and for MIPS16 functions whose cprestore slot is in range of the
9889 stack pointer. Using the stack pointer would sometimes give more
9890 (early) scheduling freedom, but using the frame pointer would
9891 sometimes give more (late) scheduling freedom. It's hard to
9892 predict which applies to a given function, so let's keep things
9895 Loads must always use the frame pointer in functions that call
9896 alloca, and there's little benefit to using the stack pointer
9898 if (frame_pointer_needed && !(TARGET_CPRESTORE_DIRECTIVE && !load_p))
9900 *base = hard_frame_pointer_rtx;
9901 *offset = frame->args_size - frame->hard_frame_pointer_offset;
9905 *base = stack_pointer_rtx;
9906 *offset = frame->args_size;
9910 /* Return true if X is the load or store address of the cprestore slot;
9911 LOAD_P says which. */
9914 mips_cprestore_address_p (rtx x, bool load_p)
9916 rtx given_base, required_base;
9917 HOST_WIDE_INT given_offset, required_offset;
9919 mips_split_plus (x, &given_base, &given_offset);
9920 mips_get_cprestore_base_and_offset (&required_base, &required_offset, load_p);
9921 return given_base == required_base && given_offset == required_offset;
9924 /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are
9925 going to load from it, false if we are going to store to it.
9926 Use TEMP as a temporary register if need be. */
9929 mips_cprestore_slot (rtx temp, bool load_p)
9932 HOST_WIDE_INT offset;
9934 mips_get_cprestore_base_and_offset (&base, &offset, load_p);
9935 return gen_frame_mem (Pmode, mips_add_offset (temp, base, offset));
9938 /* Emit instructions to save global pointer value GP into cprestore
9939 slot MEM. OFFSET is the offset that MEM applies to the base register.
9941 MEM may not be a legitimate address. If it isn't, TEMP is a
9942 temporary register that can be used, otherwise it is a SCRATCH. */
9945 mips_save_gp_to_cprestore_slot (rtx mem, rtx offset, rtx gp, rtx temp)
9947 if (TARGET_CPRESTORE_DIRECTIVE)
9949 gcc_assert (gp == pic_offset_table_rtx);
9950 emit_insn (PMODE_INSN (gen_cprestore, (mem, offset)));
9953 mips_emit_move (mips_cprestore_slot (temp, false), gp);
9956 /* Restore $gp from its save slot, using TEMP as a temporary base register
9957 if need be. This function is for o32 and o64 abicalls only.
9959 See mips_must_initialize_gp_p for details about how we manage the
9963 mips_restore_gp_from_cprestore_slot (rtx temp)
9965 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI && epilogue_completed);
9967 if (!cfun->machine->must_restore_gp_when_clobbered_p)
9969 emit_note (NOTE_INSN_DELETED);
9975 mips_emit_move (temp, mips_cprestore_slot (temp, true));
9976 mips_emit_move (pic_offset_table_rtx, temp);
9979 mips_emit_move (pic_offset_table_rtx, mips_cprestore_slot (temp, true));
9980 if (!TARGET_EXPLICIT_RELOCS)
9981 emit_insn (gen_blockage ());
9984 /* A function to save or store a register. The first argument is the
9985 register and the second is the stack slot. */
9986 typedef void (*mips_save_restore_fn) (rtx, rtx);
9988 /* Use FN to save or restore register REGNO. MODE is the register's
9989 mode and OFFSET is the offset of its save slot from the current
9993 mips_save_restore_reg (enum machine_mode mode, int regno,
9994 HOST_WIDE_INT offset, mips_save_restore_fn fn)
9998 mem = gen_frame_mem (mode, plus_constant (Pmode, stack_pointer_rtx,
10000 fn (gen_rtx_REG (mode, regno), mem);
10003 /* Call FN for each accumlator that is saved by the current function.
10004 SP_OFFSET is the offset of the current stack pointer from the start
10008 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
10010 HOST_WIDE_INT offset;
10013 offset = cfun->machine->frame.acc_sp_offset - sp_offset;
10014 if (BITSET_P (cfun->machine->frame.acc_mask, 0))
10016 mips_save_restore_reg (word_mode, LO_REGNUM, offset, fn);
10017 offset -= UNITS_PER_WORD;
10018 mips_save_restore_reg (word_mode, HI_REGNUM, offset, fn);
10019 offset -= UNITS_PER_WORD;
10022 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
10023 if (BITSET_P (cfun->machine->frame.acc_mask,
10024 ((regno - DSP_ACC_REG_FIRST) / 2) + 1))
10026 mips_save_restore_reg (word_mode, regno, offset, fn);
10027 offset -= UNITS_PER_WORD;
10031 /* Call FN for each register that is saved by the current function.
10032 SP_OFFSET is the offset of the current stack pointer from the start
10036 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset,
10037 mips_save_restore_fn fn)
10039 enum machine_mode fpr_mode;
10040 HOST_WIDE_INT offset;
10043 /* Save registers starting from high to low. The debuggers prefer at least
10044 the return register be stored at func+4, and also it allows us not to
10045 need a nop in the epilogue if at least one register is reloaded in
10046 addition to return address. */
10047 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
10048 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
10049 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
10051 /* Record the ra offset for use by mips_function_profiler. */
10052 if (regno == RETURN_ADDR_REGNUM)
10053 cfun->machine->frame.ra_fp_offset = offset + sp_offset;
10054 mips_save_restore_reg (word_mode, regno, offset, fn);
10055 offset -= UNITS_PER_WORD;
10058 /* This loop must iterate over the same space as its companion in
10059 mips_compute_frame_info. */
10060 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
10061 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
10062 for (regno = FP_REG_LAST - MAX_FPRS_PER_FMT + 1;
10063 regno >= FP_REG_FIRST;
10064 regno -= MAX_FPRS_PER_FMT)
10065 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
10067 mips_save_restore_reg (fpr_mode, regno, offset, fn);
10068 offset -= GET_MODE_SIZE (fpr_mode);
10072 /* Return true if a move between register REGNO and its save slot (MEM)
10073 can be done in a single move. LOAD_P is true if we are loading
10074 from the slot, false if we are storing to it. */
10077 mips_direct_save_slot_move_p (unsigned int regno, rtx mem, bool load_p)
10079 /* There is a specific MIPS16 instruction for saving $31 to the stack. */
10080 if (TARGET_MIPS16 && !load_p && regno == RETURN_ADDR_REGNUM)
10083 return mips_secondary_reload_class (REGNO_REG_CLASS (regno),
10084 GET_MODE (mem), mem, load_p) == NO_REGS;
10087 /* Emit a move from SRC to DEST, given that one of them is a register
10088 save slot and that the other is a register. TEMP is a temporary
10089 GPR of the same mode that is available if need be. */
10092 mips_emit_save_slot_move (rtx dest, rtx src, rtx temp)
10094 unsigned int regno;
10099 regno = REGNO (src);
10104 regno = REGNO (dest);
10108 if (regno == cfun->machine->global_pointer && !mips_must_initialize_gp_p ())
10110 /* We don't yet know whether we'll need this instruction or not.
10111 Postpone the decision by emitting a ghost move. This move
10112 is specifically not frame-related; only the split version is. */
10114 emit_insn (gen_move_gpdi (dest, src));
10116 emit_insn (gen_move_gpsi (dest, src));
10120 if (regno == HI_REGNUM)
10124 mips_emit_move (temp, src);
10126 emit_insn (gen_mthisi_di (gen_rtx_REG (TImode, MD_REG_FIRST),
10127 temp, gen_rtx_REG (DImode, LO_REGNUM)));
10129 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode, MD_REG_FIRST),
10130 temp, gen_rtx_REG (SImode, LO_REGNUM)));
10135 emit_insn (gen_mfhidi_ti (temp,
10136 gen_rtx_REG (TImode, MD_REG_FIRST)));
10138 emit_insn (gen_mfhisi_di (temp,
10139 gen_rtx_REG (DImode, MD_REG_FIRST)));
10140 mips_emit_move (dest, temp);
10143 else if (mips_direct_save_slot_move_p (regno, mem, mem == src))
10144 mips_emit_move (dest, src);
10147 gcc_assert (!reg_overlap_mentioned_p (dest, temp));
10148 mips_emit_move (temp, src);
10149 mips_emit_move (dest, temp);
10152 mips_set_frame_expr (mips_frame_set (dest, src));
10155 /* If we're generating n32 or n64 abicalls, and the current function
10156 does not use $28 as its global pointer, emit a cplocal directive.
10157 Use pic_offset_table_rtx as the argument to the directive. */
10160 mips_output_cplocal (void)
10162 if (!TARGET_EXPLICIT_RELOCS
10163 && mips_must_initialize_gp_p ()
10164 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
10165 output_asm_insn (".cplocal %+", 0);
10168 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
10171 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
10173 const char *fnname;
10175 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
10176 floating-point arguments. */
10178 && TARGET_HARD_FLOAT_ABI
10179 && crtl->args.info.fp_code != 0)
10180 mips16_build_function_stub ();
10182 /* Get the function name the same way that toplev.c does before calling
10183 assemble_start_function. This is needed so that the name used here
10184 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10185 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
10186 mips_start_function_definition (fnname, TARGET_MIPS16);
10188 /* Output MIPS-specific frame information. */
10189 if (!flag_inhibit_size_directive)
10191 const struct mips_frame_info *frame;
10193 frame = &cfun->machine->frame;
10195 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
10197 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
10198 "# vars= " HOST_WIDE_INT_PRINT_DEC
10200 ", args= " HOST_WIDE_INT_PRINT_DEC
10201 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
10202 reg_names[frame_pointer_needed
10203 ? HARD_FRAME_POINTER_REGNUM
10204 : STACK_POINTER_REGNUM],
10205 (frame_pointer_needed
10206 ? frame->total_size - frame->hard_frame_pointer_offset
10207 : frame->total_size),
10208 reg_names[RETURN_ADDR_REGNUM],
10210 frame->num_gp, frame->num_fp,
10212 frame->cprestore_size);
10214 /* .mask MASK, OFFSET. */
10215 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
10216 frame->mask, frame->gp_save_offset);
10218 /* .fmask MASK, OFFSET. */
10219 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
10220 frame->fmask, frame->fp_save_offset);
10223 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
10224 Also emit the ".set noreorder; .set nomacro" sequence for functions
10226 if (mips_must_initialize_gp_p ()
10227 && mips_current_loadgp_style () == LOADGP_OLDABI)
10231 /* This is a fixed-form sequence. The position of the
10232 first two instructions is important because of the
10233 way _gp_disp is defined. */
10234 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
10235 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
10236 output_asm_insn ("sll\t$2,16", 0);
10237 output_asm_insn ("addu\t$2,$3", 0);
10241 /* .cpload must be in a .set noreorder but not a
10242 .set nomacro block. */
10243 mips_push_asm_switch (&mips_noreorder);
10244 output_asm_insn (".cpload\t%^", 0);
10245 if (!cfun->machine->all_noreorder_p)
10246 mips_pop_asm_switch (&mips_noreorder);
10248 mips_push_asm_switch (&mips_nomacro);
10251 else if (cfun->machine->all_noreorder_p)
10253 mips_push_asm_switch (&mips_noreorder);
10254 mips_push_asm_switch (&mips_nomacro);
10257 /* Tell the assembler which register we're using as the global
10258 pointer. This is needed for thunks, since they can use either
10259 explicit relocs or assembler macros. */
10260 mips_output_cplocal ();
10263 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
10266 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
10267 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
10269 const char *fnname;
10271 /* Reinstate the normal $gp. */
10272 SET_REGNO (pic_offset_table_rtx, GLOBAL_POINTER_REGNUM);
10273 mips_output_cplocal ();
10275 if (cfun->machine->all_noreorder_p)
10277 mips_pop_asm_switch (&mips_nomacro);
10278 mips_pop_asm_switch (&mips_noreorder);
10281 /* Get the function name the same way that toplev.c does before calling
10282 assemble_start_function. This is needed so that the name used here
10283 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10284 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
10285 mips_end_function_definition (fnname);
10288 /* Emit an optimisation barrier for accesses to the current frame. */
10291 mips_frame_barrier (void)
10293 emit_clobber (gen_frame_mem (BLKmode, stack_pointer_rtx));
10296 /* Save register REG to MEM. Make the instruction frame-related. */
10299 mips_save_reg (rtx reg, rtx mem)
10301 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
10305 if (mips_split_64bit_move_p (mem, reg))
10306 mips_split_doubleword_move (mem, reg);
10308 mips_emit_move (mem, reg);
10310 x1 = mips_frame_set (mips_subword (mem, false),
10311 mips_subword (reg, false));
10312 x2 = mips_frame_set (mips_subword (mem, true),
10313 mips_subword (reg, true));
10314 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
10317 mips_emit_save_slot_move (mem, reg, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
10320 /* The __gnu_local_gp symbol. */
10322 static GTY(()) rtx mips_gnu_local_gp;
10324 /* If we're generating n32 or n64 abicalls, emit instructions
10325 to set up the global pointer. */
10328 mips_emit_loadgp (void)
10330 rtx addr, offset, incoming_address, base, index, pic_reg;
10332 pic_reg = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
10333 switch (mips_current_loadgp_style ())
10335 case LOADGP_ABSOLUTE:
10336 if (mips_gnu_local_gp == NULL)
10338 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
10339 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
10341 emit_insn (PMODE_INSN (gen_loadgp_absolute,
10342 (pic_reg, mips_gnu_local_gp)));
10345 case LOADGP_OLDABI:
10346 /* Added by mips_output_function_prologue. */
10349 case LOADGP_NEWABI:
10350 addr = XEXP (DECL_RTL (current_function_decl), 0);
10351 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
10352 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
10353 emit_insn (PMODE_INSN (gen_loadgp_newabi,
10354 (pic_reg, offset, incoming_address)));
10358 base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE));
10359 index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX));
10360 emit_insn (PMODE_INSN (gen_loadgp_rtp, (pic_reg, base, index)));
10368 emit_insn (PMODE_INSN (gen_copygp_mips16,
10369 (pic_offset_table_rtx, pic_reg)));
10371 /* Emit a blockage if there are implicit uses of the GP register.
10372 This includes profiled functions, because FUNCTION_PROFILE uses
10374 if (!TARGET_EXPLICIT_RELOCS || crtl->profile)
10375 emit_insn (gen_loadgp_blockage ());
10378 /* A for_each_rtx callback. Stop the search if *X is a kernel register. */
10381 mips_kernel_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
10383 return REG_P (*x) && KERNEL_REG_P (REGNO (*x));
10386 /* Expand the "prologue" pattern. */
10389 mips_expand_prologue (void)
10391 const struct mips_frame_info *frame;
10392 HOST_WIDE_INT size;
10393 unsigned int nargs;
10396 if (cfun->machine->global_pointer != INVALID_REGNUM)
10398 /* Check whether an insn uses pic_offset_table_rtx, either explicitly
10399 or implicitly. If so, we can commit to using a global pointer
10400 straight away, otherwise we need to defer the decision. */
10401 if (mips_cfun_has_inflexible_gp_ref_p ()
10402 || mips_cfun_has_flexible_gp_ref_p ())
10404 cfun->machine->must_initialize_gp_p = true;
10405 cfun->machine->must_restore_gp_when_clobbered_p = true;
10408 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
10411 frame = &cfun->machine->frame;
10412 size = frame->total_size;
10414 if (flag_stack_usage_info)
10415 current_function_static_stack_size = size;
10417 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
10418 bytes beforehand; this is enough to cover the register save area
10419 without going out of range. */
10420 if (((frame->mask | frame->fmask | frame->acc_mask) != 0)
10421 || frame->num_cop0_regs > 0)
10423 HOST_WIDE_INT step1;
10425 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
10426 if (GENERATE_MIPS16E_SAVE_RESTORE)
10428 HOST_WIDE_INT offset;
10429 unsigned int mask, regno;
10431 /* Try to merge argument stores into the save instruction. */
10432 nargs = mips16e_collect_argument_saves ();
10434 /* Build the save instruction. */
10435 mask = frame->mask;
10436 insn = mips16e_build_save_restore (false, &mask, &offset,
10438 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10439 mips_frame_barrier ();
10442 /* Check if we need to save other registers. */
10443 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
10444 if (BITSET_P (mask, regno - GP_REG_FIRST))
10446 offset -= UNITS_PER_WORD;
10447 mips_save_restore_reg (word_mode, regno,
10448 offset, mips_save_reg);
10453 if (cfun->machine->interrupt_handler_p)
10455 HOST_WIDE_INT offset;
10458 /* If this interrupt is using a shadow register set, we need to
10459 get the stack pointer from the previous register set. */
10460 if (cfun->machine->use_shadow_register_set_p)
10461 emit_insn (gen_mips_rdpgpr (stack_pointer_rtx,
10462 stack_pointer_rtx));
10464 if (!cfun->machine->keep_interrupts_masked_p)
10466 /* Move from COP0 Cause to K0. */
10467 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K0_REG_NUM),
10468 gen_rtx_REG (SImode,
10469 COP0_CAUSE_REG_NUM)));
10470 /* Move from COP0 EPC to K1. */
10471 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
10472 gen_rtx_REG (SImode,
10473 COP0_EPC_REG_NUM)));
10476 /* Allocate the first part of the frame. */
10477 insn = gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx,
10479 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10480 mips_frame_barrier ();
10483 /* Start at the uppermost location for saving. */
10484 offset = frame->cop0_sp_offset - size;
10485 if (!cfun->machine->keep_interrupts_masked_p)
10487 /* Push EPC into its stack slot. */
10488 mem = gen_frame_mem (word_mode,
10489 plus_constant (Pmode, stack_pointer_rtx,
10491 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
10492 offset -= UNITS_PER_WORD;
10495 /* Move from COP0 Status to K1. */
10496 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
10497 gen_rtx_REG (SImode,
10498 COP0_STATUS_REG_NUM)));
10500 /* Right justify the RIPL in k0. */
10501 if (!cfun->machine->keep_interrupts_masked_p)
10502 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode, K0_REG_NUM),
10503 gen_rtx_REG (SImode, K0_REG_NUM),
10504 GEN_INT (CAUSE_IPL)));
10506 /* Push Status into its stack slot. */
10507 mem = gen_frame_mem (word_mode,
10508 plus_constant (Pmode, stack_pointer_rtx,
10510 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
10511 offset -= UNITS_PER_WORD;
10513 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
10514 if (!cfun->machine->keep_interrupts_masked_p)
10515 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
10518 gen_rtx_REG (SImode, K0_REG_NUM)));
10520 if (!cfun->machine->keep_interrupts_masked_p)
10521 /* Enable interrupts by clearing the KSU ERL and EXL bits.
10522 IE is already the correct value, so we don't have to do
10523 anything explicit. */
10524 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
10527 gen_rtx_REG (SImode, GP_REG_FIRST)));
10529 /* Disable interrupts by clearing the KSU, ERL, EXL,
10531 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
10534 gen_rtx_REG (SImode, GP_REG_FIRST)));
10538 insn = gen_add3_insn (stack_pointer_rtx,
10541 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10542 mips_frame_barrier ();
10545 mips_for_each_saved_acc (size, mips_save_reg);
10546 mips_for_each_saved_gpr_and_fpr (size, mips_save_reg);
10550 /* Allocate the rest of the frame. */
10553 if (SMALL_OPERAND (-size))
10554 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
10556 GEN_INT (-size)))) = 1;
10559 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
10562 /* There are no instructions to add or subtract registers
10563 from the stack pointer, so use the frame pointer as a
10564 temporary. We should always be using a frame pointer
10565 in this case anyway. */
10566 gcc_assert (frame_pointer_needed);
10567 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
10568 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
10569 hard_frame_pointer_rtx,
10570 MIPS_PROLOGUE_TEMP (Pmode)));
10571 mips_emit_move (stack_pointer_rtx, hard_frame_pointer_rtx);
10574 emit_insn (gen_sub3_insn (stack_pointer_rtx,
10576 MIPS_PROLOGUE_TEMP (Pmode)));
10578 /* Describe the combined effect of the previous instructions. */
10579 mips_set_frame_expr
10580 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
10581 plus_constant (Pmode, stack_pointer_rtx, -size)));
10583 mips_frame_barrier ();
10586 /* Set up the frame pointer, if we're using one. */
10587 if (frame_pointer_needed)
10589 HOST_WIDE_INT offset;
10591 offset = frame->hard_frame_pointer_offset;
10594 insn = mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
10595 RTX_FRAME_RELATED_P (insn) = 1;
10597 else if (SMALL_OPERAND (offset))
10599 insn = gen_add3_insn (hard_frame_pointer_rtx,
10600 stack_pointer_rtx, GEN_INT (offset));
10601 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10605 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (offset));
10606 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
10607 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
10608 hard_frame_pointer_rtx,
10609 MIPS_PROLOGUE_TEMP (Pmode)));
10610 mips_set_frame_expr
10611 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
10612 plus_constant (Pmode, stack_pointer_rtx, offset)));
10616 mips_emit_loadgp ();
10618 /* Initialize the $gp save slot. */
10619 if (mips_cfun_has_cprestore_slot_p ())
10621 rtx base, mem, gp, temp;
10622 HOST_WIDE_INT offset;
10624 mips_get_cprestore_base_and_offset (&base, &offset, false);
10625 mem = gen_frame_mem (Pmode, plus_constant (Pmode, base, offset));
10626 gp = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
10627 temp = (SMALL_OPERAND (offset)
10628 ? gen_rtx_SCRATCH (Pmode)
10629 : MIPS_PROLOGUE_TEMP (Pmode));
10630 emit_insn (PMODE_INSN (gen_potential_cprestore,
10631 (mem, GEN_INT (offset), gp, temp)));
10633 mips_get_cprestore_base_and_offset (&base, &offset, true);
10634 mem = gen_frame_mem (Pmode, plus_constant (Pmode, base, offset));
10635 emit_insn (PMODE_INSN (gen_use_cprestore, (mem)));
10638 /* We need to search back to the last use of K0 or K1. */
10639 if (cfun->machine->interrupt_handler_p)
10641 for (insn = get_last_insn (); insn != NULL_RTX; insn = PREV_INSN (insn))
10643 && for_each_rtx (&PATTERN (insn), mips_kernel_reg_p, NULL))
10645 /* Emit a move from K1 to COP0 Status after insn. */
10646 gcc_assert (insn != NULL_RTX);
10647 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
10648 gen_rtx_REG (SImode, K1_REG_NUM)),
10652 /* If we are profiling, make sure no instructions are scheduled before
10653 the call to mcount. */
10655 emit_insn (gen_blockage ());
10658 /* Attach all pending register saves to the previous instruction.
10659 Return that instruction. */
10662 mips_epilogue_emit_cfa_restores (void)
10666 insn = get_last_insn ();
10667 gcc_assert (insn && !REG_NOTES (insn));
10668 if (mips_epilogue.cfa_restores)
10670 RTX_FRAME_RELATED_P (insn) = 1;
10671 REG_NOTES (insn) = mips_epilogue.cfa_restores;
10672 mips_epilogue.cfa_restores = 0;
10677 /* Like mips_epilogue_emit_cfa_restores, but also record that the CFA is
10678 now at REG + OFFSET. */
10681 mips_epilogue_set_cfa (rtx reg, HOST_WIDE_INT offset)
10685 insn = mips_epilogue_emit_cfa_restores ();
10686 if (reg != mips_epilogue.cfa_reg || offset != mips_epilogue.cfa_offset)
10688 RTX_FRAME_RELATED_P (insn) = 1;
10689 REG_NOTES (insn) = alloc_reg_note (REG_CFA_DEF_CFA,
10690 plus_constant (Pmode, reg, offset),
10692 mips_epilogue.cfa_reg = reg;
10693 mips_epilogue.cfa_offset = offset;
10697 /* Emit instructions to restore register REG from slot MEM. Also update
10698 the cfa_restores list. */
10701 mips_restore_reg (rtx reg, rtx mem)
10703 /* There's no MIPS16 instruction to load $31 directly. Load into
10704 $7 instead and adjust the return insn appropriately. */
10705 if (TARGET_MIPS16 && REGNO (reg) == RETURN_ADDR_REGNUM)
10706 reg = gen_rtx_REG (GET_MODE (reg), GP_REG_FIRST + 7);
10707 else if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
10709 mips_add_cfa_restore (mips_subword (reg, true));
10710 mips_add_cfa_restore (mips_subword (reg, false));
10713 mips_add_cfa_restore (reg);
10715 mips_emit_save_slot_move (reg, mem, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
10716 if (REGNO (reg) == REGNO (mips_epilogue.cfa_reg))
10717 /* The CFA is currently defined in terms of the register whose
10718 value we have just restored. Redefine the CFA in terms of
10719 the stack pointer. */
10720 mips_epilogue_set_cfa (stack_pointer_rtx,
10721 mips_epilogue.cfa_restore_sp_offset);
10724 /* Emit code to set the stack pointer to BASE + OFFSET, given that
10725 BASE + OFFSET is NEW_FRAME_SIZE bytes below the top of the frame.
10726 BASE, if not the stack pointer, is available as a temporary. */
10729 mips_deallocate_stack (rtx base, rtx offset, HOST_WIDE_INT new_frame_size)
10731 if (base == stack_pointer_rtx && offset == const0_rtx)
10734 mips_frame_barrier ();
10735 if (offset == const0_rtx)
10737 emit_move_insn (stack_pointer_rtx, base);
10738 mips_epilogue_set_cfa (stack_pointer_rtx, new_frame_size);
10740 else if (TARGET_MIPS16 && base != stack_pointer_rtx)
10742 emit_insn (gen_add3_insn (base, base, offset));
10743 mips_epilogue_set_cfa (base, new_frame_size);
10744 emit_move_insn (stack_pointer_rtx, base);
10748 emit_insn (gen_add3_insn (stack_pointer_rtx, base, offset));
10749 mips_epilogue_set_cfa (stack_pointer_rtx, new_frame_size);
10753 /* Emit any instructions needed before a return. */
10756 mips_expand_before_return (void)
10758 /* When using a call-clobbered gp, we start out with unified call
10759 insns that include instructions to restore the gp. We then split
10760 these unified calls after reload. These split calls explicitly
10761 clobber gp, so there is no need to define
10762 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
10764 For consistency, we should also insert an explicit clobber of $28
10765 before return insns, so that the post-reload optimizers know that
10766 the register is not live on exit. */
10767 if (TARGET_CALL_CLOBBERED_GP)
10768 emit_clobber (pic_offset_table_rtx);
10771 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
10775 mips_expand_epilogue (bool sibcall_p)
10777 const struct mips_frame_info *frame;
10778 HOST_WIDE_INT step1, step2;
10779 rtx base, adjust, insn;
10781 if (!sibcall_p && mips_can_use_return_insn ())
10783 emit_jump_insn (gen_return ());
10787 /* In MIPS16 mode, if the return value should go into a floating-point
10788 register, we need to call a helper routine to copy it over. */
10789 if (mips16_cfun_returns_in_fpr_p ())
10790 mips16_copy_fpr_return_value ();
10792 /* Split the frame into two. STEP1 is the amount of stack we should
10793 deallocate before restoring the registers. STEP2 is the amount we
10794 should deallocate afterwards.
10796 Start off by assuming that no registers need to be restored. */
10797 frame = &cfun->machine->frame;
10798 step1 = frame->total_size;
10801 /* Work out which register holds the frame address. */
10802 if (!frame_pointer_needed)
10803 base = stack_pointer_rtx;
10806 base = hard_frame_pointer_rtx;
10807 step1 -= frame->hard_frame_pointer_offset;
10809 mips_epilogue.cfa_reg = base;
10810 mips_epilogue.cfa_offset = step1;
10811 mips_epilogue.cfa_restores = NULL_RTX;
10813 /* If we need to restore registers, deallocate as much stack as
10814 possible in the second step without going out of range. */
10815 if ((frame->mask | frame->fmask | frame->acc_mask) != 0
10816 || frame->num_cop0_regs > 0)
10818 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
10822 /* Get an rtx for STEP1 that we can add to BASE. */
10823 adjust = GEN_INT (step1);
10824 if (!SMALL_OPERAND (step1))
10826 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), adjust);
10827 adjust = MIPS_EPILOGUE_TEMP (Pmode);
10829 mips_deallocate_stack (base, adjust, step2);
10831 /* If we're using addressing macros, $gp is implicitly used by all
10832 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
10834 if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS)
10835 emit_insn (gen_blockage ());
10837 mips_epilogue.cfa_restore_sp_offset = step2;
10838 if (GENERATE_MIPS16E_SAVE_RESTORE && frame->mask != 0)
10840 unsigned int regno, mask;
10841 HOST_WIDE_INT offset;
10844 /* Generate the restore instruction. */
10845 mask = frame->mask;
10846 restore = mips16e_build_save_restore (true, &mask, &offset, 0, step2);
10848 /* Restore any other registers manually. */
10849 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
10850 if (BITSET_P (mask, regno - GP_REG_FIRST))
10852 offset -= UNITS_PER_WORD;
10853 mips_save_restore_reg (word_mode, regno, offset, mips_restore_reg);
10856 /* Restore the remaining registers and deallocate the final bit
10858 mips_frame_barrier ();
10859 emit_insn (restore);
10860 mips_epilogue_set_cfa (stack_pointer_rtx, 0);
10864 /* Restore the registers. */
10865 mips_for_each_saved_acc (frame->total_size - step2, mips_restore_reg);
10866 mips_for_each_saved_gpr_and_fpr (frame->total_size - step2,
10869 if (cfun->machine->interrupt_handler_p)
10871 HOST_WIDE_INT offset;
10874 offset = frame->cop0_sp_offset - (frame->total_size - step2);
10875 if (!cfun->machine->keep_interrupts_masked_p)
10877 /* Restore the original EPC. */
10878 mem = gen_frame_mem (word_mode,
10879 plus_constant (Pmode, stack_pointer_rtx,
10881 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
10882 offset -= UNITS_PER_WORD;
10884 /* Move to COP0 EPC. */
10885 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_EPC_REG_NUM),
10886 gen_rtx_REG (SImode, K0_REG_NUM)));
10889 /* Restore the original Status. */
10890 mem = gen_frame_mem (word_mode,
10891 plus_constant (Pmode, stack_pointer_rtx,
10893 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
10894 offset -= UNITS_PER_WORD;
10896 /* If we don't use shoadow register set, we need to update SP. */
10897 if (!cfun->machine->use_shadow_register_set_p)
10898 mips_deallocate_stack (stack_pointer_rtx, GEN_INT (step2), 0);
10900 /* The choice of position is somewhat arbitrary in this case. */
10901 mips_epilogue_emit_cfa_restores ();
10903 /* Move to COP0 Status. */
10904 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
10905 gen_rtx_REG (SImode, K0_REG_NUM)));
10908 /* Deallocate the final bit of the frame. */
10909 mips_deallocate_stack (stack_pointer_rtx, GEN_INT (step2), 0);
10911 gcc_assert (!mips_epilogue.cfa_restores);
10913 /* Add in the __builtin_eh_return stack adjustment. We need to
10914 use a temporary in MIPS16 code. */
10915 if (crtl->calls_eh_return)
10919 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
10920 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
10921 MIPS_EPILOGUE_TEMP (Pmode),
10922 EH_RETURN_STACKADJ_RTX));
10923 mips_emit_move (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
10926 emit_insn (gen_add3_insn (stack_pointer_rtx,
10928 EH_RETURN_STACKADJ_RTX));
10933 mips_expand_before_return ();
10934 if (cfun->machine->interrupt_handler_p)
10936 /* Interrupt handlers generate eret or deret. */
10937 if (cfun->machine->use_debug_exception_return_p)
10938 emit_jump_insn (gen_mips_deret ());
10940 emit_jump_insn (gen_mips_eret ());
10946 /* When generating MIPS16 code, the normal
10947 mips_for_each_saved_gpr_and_fpr path will restore the return
10948 address into $7 rather than $31. */
10950 && !GENERATE_MIPS16E_SAVE_RESTORE
10951 && BITSET_P (frame->mask, RETURN_ADDR_REGNUM))
10953 /* simple_returns cannot rely on values that are only available
10954 on paths through the epilogue (because return paths that do
10955 not pass through the epilogue may nevertheless reuse a
10956 simple_return that occurs at the end of the epilogue).
10957 Use a normal return here instead. */
10958 rtx reg = gen_rtx_REG (Pmode, GP_REG_FIRST + 7);
10959 pat = gen_return_internal (reg);
10963 rtx reg = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
10964 pat = gen_simple_return_internal (reg);
10966 emit_jump_insn (pat);
10970 /* Search from the beginning to the first use of K0 or K1. */
10971 if (cfun->machine->interrupt_handler_p
10972 && !cfun->machine->keep_interrupts_masked_p)
10974 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
10976 && for_each_rtx (&PATTERN(insn), mips_kernel_reg_p, NULL))
10978 gcc_assert (insn != NULL_RTX);
10979 /* Insert disable interrupts before the first use of K0 or K1. */
10980 emit_insn_before (gen_mips_di (), insn);
10981 emit_insn_before (gen_mips_ehb (), insn);
10985 /* Return nonzero if this function is known to have a null epilogue.
10986 This allows the optimizer to omit jumps to jumps if no stack
10990 mips_can_use_return_insn (void)
10992 /* Interrupt handlers need to go through the epilogue. */
10993 if (cfun->machine->interrupt_handler_p)
10996 if (!reload_completed)
11002 /* In MIPS16 mode, a function that returns a floating-point value
11003 needs to arrange to copy the return value into the floating-point
11005 if (mips16_cfun_returns_in_fpr_p ())
11008 return cfun->machine->frame.total_size == 0;
11011 /* Return true if register REGNO can store a value of mode MODE.
11012 The result of this function is cached in mips_hard_regno_mode_ok. */
11015 mips_hard_regno_mode_ok_p (unsigned int regno, enum machine_mode mode)
11018 enum mode_class mclass;
11020 if (mode == CCV2mode)
11021 return (ISA_HAS_8CC
11022 && ST_REG_P (regno)
11023 && (regno - ST_REG_FIRST) % 2 == 0);
11025 if (mode == CCV4mode)
11026 return (ISA_HAS_8CC
11027 && ST_REG_P (regno)
11028 && (regno - ST_REG_FIRST) % 4 == 0);
11030 if (mode == CCmode)
11033 return regno == FPSW_REGNUM;
11035 return (ST_REG_P (regno)
11036 || GP_REG_P (regno)
11037 || FP_REG_P (regno));
11040 size = GET_MODE_SIZE (mode);
11041 mclass = GET_MODE_CLASS (mode);
11043 if (GP_REG_P (regno))
11044 return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD;
11046 if (FP_REG_P (regno)
11047 && (((regno - FP_REG_FIRST) % MAX_FPRS_PER_FMT) == 0
11048 || (MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG)))
11050 /* Allow TFmode for CCmode reloads. */
11051 if (mode == TFmode && ISA_HAS_8CC)
11054 /* Allow 64-bit vector modes for Loongson-2E/2F. */
11055 if (TARGET_LOONGSON_VECTORS
11056 && (mode == V2SImode
11057 || mode == V4HImode
11058 || mode == V8QImode
11059 || mode == DImode))
11062 if (mclass == MODE_FLOAT
11063 || mclass == MODE_COMPLEX_FLOAT
11064 || mclass == MODE_VECTOR_FLOAT)
11065 return size <= UNITS_PER_FPVALUE;
11067 /* Allow integer modes that fit into a single register. We need
11068 to put integers into FPRs when using instructions like CVT
11069 and TRUNC. There's no point allowing sizes smaller than a word,
11070 because the FPU has no appropriate load/store instructions. */
11071 if (mclass == MODE_INT)
11072 return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG;
11075 if (ACC_REG_P (regno)
11076 && (INTEGRAL_MODE_P (mode) || ALL_FIXED_POINT_MODE_P (mode)))
11078 if (MD_REG_P (regno))
11080 /* After a multiplication or division, clobbering HI makes
11081 the value of LO unpredictable, and vice versa. This means
11082 that, for all interesting cases, HI and LO are effectively
11085 We model this by requiring that any value that uses HI
11087 if (size <= UNITS_PER_WORD * 2)
11088 return regno == (size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST);
11092 /* DSP accumulators do not have the same restrictions as
11093 HI and LO, so we can treat them as normal doubleword
11095 if (size <= UNITS_PER_WORD)
11098 if (size <= UNITS_PER_WORD * 2
11099 && ((regno - DSP_ACC_REG_FIRST) & 1) == 0)
11104 if (ALL_COP_REG_P (regno))
11105 return mclass == MODE_INT && size <= UNITS_PER_WORD;
11107 if (regno == GOT_VERSION_REGNUM)
11108 return mode == SImode;
11113 /* Implement HARD_REGNO_NREGS. */
11116 mips_hard_regno_nregs (int regno, enum machine_mode mode)
11118 if (ST_REG_P (regno))
11119 /* The size of FP status registers is always 4, because they only hold
11120 CCmode values, and CCmode is always considered to be 4 bytes wide. */
11121 return (GET_MODE_SIZE (mode) + 3) / 4;
11123 if (FP_REG_P (regno))
11124 return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG;
11126 /* All other registers are word-sized. */
11127 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
11130 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
11131 in mips_hard_regno_nregs. */
11134 mips_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
11140 COPY_HARD_REG_SET (left, reg_class_contents[(int) rclass]);
11141 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS]))
11143 if (HARD_REGNO_MODE_OK (ST_REG_FIRST, mode))
11144 size = MIN (size, 4);
11145 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) ST_REGS]);
11147 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS]))
11149 if (HARD_REGNO_MODE_OK (FP_REG_FIRST, mode))
11150 size = MIN (size, UNITS_PER_FPREG);
11151 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]);
11153 if (!hard_reg_set_empty_p (left))
11154 size = MIN (size, UNITS_PER_WORD);
11155 return (GET_MODE_SIZE (mode) + size - 1) / size;
11158 /* Implement CANNOT_CHANGE_MODE_CLASS. */
11161 mips_cannot_change_mode_class (enum machine_mode from,
11162 enum machine_mode to,
11163 enum reg_class rclass)
11165 /* Allow conversions between different Loongson integer vectors,
11166 and between those vectors and DImode. */
11167 if (GET_MODE_SIZE (from) == 8 && GET_MODE_SIZE (to) == 8
11168 && INTEGRAL_MODE_P (from) && INTEGRAL_MODE_P (to))
11171 /* Otherwise, there are several problems with changing the modes of
11172 values in floating-point registers:
11174 - When a multi-word value is stored in paired floating-point
11175 registers, the first register always holds the low word. We
11176 therefore can't allow FPRs to change between single-word and
11177 multi-word modes on big-endian targets.
11179 - GCC assumes that each word of a multiword register can be
11180 accessed individually using SUBREGs. This is not true for
11181 floating-point registers if they are bigger than a word.
11183 - Loading a 32-bit value into a 64-bit floating-point register
11184 will not sign-extend the value, despite what LOAD_EXTEND_OP
11185 says. We can't allow FPRs to change from SImode to a wider
11186 mode on 64-bit targets.
11188 - If the FPU has already interpreted a value in one format, we
11189 must not ask it to treat the value as having a different
11192 We therefore disallow all mode changes involving FPRs. */
11194 return reg_classes_intersect_p (FP_REGS, rclass);
11197 /* Implement target hook small_register_classes_for_mode_p. */
11200 mips_small_register_classes_for_mode_p (enum machine_mode mode
11203 return TARGET_MIPS16;
11206 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
11209 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode)
11214 return TARGET_HARD_FLOAT;
11217 return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT;
11220 return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT;
11227 /* Implement MODES_TIEABLE_P. */
11230 mips_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
11232 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
11233 prefer to put one of them in FPRs. */
11234 return (mode1 == mode2
11235 || (!mips_mode_ok_for_mov_fmt_p (mode1)
11236 && !mips_mode_ok_for_mov_fmt_p (mode2)));
11239 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
11242 mips_preferred_reload_class (rtx x, reg_class_t rclass)
11244 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, rclass))
11247 if (reg_class_subset_p (FP_REGS, rclass)
11248 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x)))
11251 if (reg_class_subset_p (GR_REGS, rclass))
11254 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, rclass))
11260 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
11261 Return a "canonical" class to represent it in later calculations. */
11264 mips_canonicalize_move_class (reg_class_t rclass)
11266 /* All moves involving accumulator registers have the same cost. */
11267 if (reg_class_subset_p (rclass, ACC_REGS))
11270 /* Likewise promote subclasses of general registers to the most
11271 interesting containing class. */
11272 if (TARGET_MIPS16 && reg_class_subset_p (rclass, M16_REGS))
11274 else if (reg_class_subset_p (rclass, GENERAL_REGS))
11275 rclass = GENERAL_REGS;
11280 /* Return the cost of moving a value of mode MODE from a register of
11281 class FROM to a GPR. Return 0 for classes that are unions of other
11282 classes handled by this function. */
11285 mips_move_to_gpr_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
11291 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
11295 /* MFLO and MFHI. */
11303 /* LUI followed by MOVF. */
11309 /* This choice of value is historical. */
11317 /* Return the cost of moving a value of mode MODE from a GPR to a
11318 register of class TO. Return 0 for classes that are unions of
11319 other classes handled by this function. */
11322 mips_move_from_gpr_cost (enum machine_mode mode, reg_class_t to)
11327 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
11331 /* MTLO and MTHI. */
11339 /* A secondary reload through an FPR scratch. */
11340 return (mips_register_move_cost (mode, GENERAL_REGS, FP_REGS)
11341 + mips_register_move_cost (mode, FP_REGS, ST_REGS));
11346 /* This choice of value is historical. */
11354 /* Implement TARGET_REGISTER_MOVE_COST. Return 0 for classes that are the
11355 maximum of the move costs for subclasses; regclass will work out
11356 the maximum for us. */
11359 mips_register_move_cost (enum machine_mode mode,
11360 reg_class_t from, reg_class_t to)
11365 from = mips_canonicalize_move_class (from);
11366 to = mips_canonicalize_move_class (to);
11368 /* Handle moves that can be done without using general-purpose registers. */
11369 if (from == FP_REGS)
11371 if (to == FP_REGS && mips_mode_ok_for_mov_fmt_p (mode))
11375 /* The sequence generated by mips_expand_fcc_reload. */
11379 /* Handle cases in which only one class deviates from the ideal. */
11380 dregs = TARGET_MIPS16 ? M16_REGS : GENERAL_REGS;
11382 return mips_move_from_gpr_cost (mode, to);
11384 return mips_move_to_gpr_cost (mode, from);
11386 /* Handles cases that require a GPR temporary. */
11387 cost1 = mips_move_to_gpr_cost (mode, from);
11390 cost2 = mips_move_from_gpr_cost (mode, to);
11392 return cost1 + cost2;
11398 /* Implement TARGET_MEMORY_MOVE_COST. */
11401 mips_memory_move_cost (enum machine_mode mode, reg_class_t rclass, bool in)
11403 return (mips_cost->memory_latency
11404 + memory_move_secondary_cost (mode, rclass, in));
11407 /* Return the register class required for a secondary register when
11408 copying between one of the registers in RCLASS and value X, which
11409 has mode MODE. X is the source of the move if IN_P, otherwise it
11410 is the destination. Return NO_REGS if no secondary register is
11414 mips_secondary_reload_class (enum reg_class rclass,
11415 enum machine_mode mode, rtx x, bool in_p)
11419 /* If X is a constant that cannot be loaded into $25, it must be loaded
11420 into some other GPR. No other register class allows a direct move. */
11421 if (mips_dangerous_for_la25_p (x))
11422 return reg_class_subset_p (rclass, LEA_REGS) ? NO_REGS : LEA_REGS;
11424 regno = true_regnum (x);
11427 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
11428 if (!reg_class_subset_p (rclass, M16_REGS) && !M16_REG_P (regno))
11434 /* Copying from accumulator registers to anywhere other than a general
11435 register requires a temporary general register. */
11436 if (reg_class_subset_p (rclass, ACC_REGS))
11437 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
11438 if (ACC_REG_P (regno))
11439 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
11441 /* We can only copy a value to a condition code register from a
11442 floating-point register, and even then we require a scratch
11443 floating-point register. We can only copy a value out of a
11444 condition-code register into a general register. */
11445 if (reg_class_subset_p (rclass, ST_REGS))
11449 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
11451 if (ST_REG_P (regno))
11455 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
11458 if (reg_class_subset_p (rclass, FP_REGS))
11461 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8))
11462 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
11463 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
11466 if (GP_REG_P (regno) || x == CONST0_RTX (mode))
11467 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
11470 if (CONSTANT_P (x) && !targetm.cannot_force_const_mem (mode, x))
11471 /* We can force the constant to memory and use lwc1
11472 and ldc1. As above, we will use pairs of lwc1s if
11473 ldc1 is not supported. */
11476 if (FP_REG_P (regno) && mips_mode_ok_for_mov_fmt_p (mode))
11477 /* In this case we can use mov.fmt. */
11480 /* Otherwise, we need to reload through an integer register. */
11483 if (FP_REG_P (regno))
11484 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
11489 /* Implement TARGET_MODE_REP_EXTENDED. */
11492 mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
11494 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
11495 if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
11496 return SIGN_EXTEND;
11501 /* Implement TARGET_VALID_POINTER_MODE. */
11504 mips_valid_pointer_mode (enum machine_mode mode)
11506 return mode == SImode || (TARGET_64BIT && mode == DImode);
11509 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
11512 mips_vector_mode_supported_p (enum machine_mode mode)
11517 return TARGET_PAIRED_SINGLE_FLOAT;
11532 return TARGET_LOONGSON_VECTORS;
11539 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
11542 mips_scalar_mode_supported_p (enum machine_mode mode)
11544 if (ALL_FIXED_POINT_MODE_P (mode)
11545 && GET_MODE_PRECISION (mode) <= 2 * BITS_PER_WORD)
11548 return default_scalar_mode_supported_p (mode);
11551 /* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
11553 static enum machine_mode
11554 mips_preferred_simd_mode (enum machine_mode mode ATTRIBUTE_UNUSED)
11556 if (TARGET_PAIRED_SINGLE_FLOAT
11562 /* Implement TARGET_INIT_LIBFUNCS. */
11565 mips_init_libfuncs (void)
11567 if (TARGET_FIX_VR4120)
11569 /* Register the special divsi3 and modsi3 functions needed to work
11570 around VR4120 division errata. */
11571 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
11572 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
11575 if (TARGET_MIPS16 && TARGET_HARD_FLOAT_ABI)
11577 /* Register the MIPS16 -mhard-float stubs. */
11578 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
11579 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
11580 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
11581 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
11583 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
11584 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
11585 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
11586 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
11587 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
11588 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
11589 set_optab_libfunc (unord_optab, SFmode, "__mips16_unordsf2");
11591 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
11592 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
11593 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__mips16_floatunsisf");
11595 if (TARGET_DOUBLE_FLOAT)
11597 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
11598 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
11599 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
11600 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
11602 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
11603 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
11604 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
11605 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
11606 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
11607 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
11608 set_optab_libfunc (unord_optab, DFmode, "__mips16_unorddf2");
11610 set_conv_libfunc (sext_optab, DFmode, SFmode,
11611 "__mips16_extendsfdf2");
11612 set_conv_libfunc (trunc_optab, SFmode, DFmode,
11613 "__mips16_truncdfsf2");
11614 set_conv_libfunc (sfix_optab, SImode, DFmode,
11615 "__mips16_fix_truncdfsi");
11616 set_conv_libfunc (sfloat_optab, DFmode, SImode,
11617 "__mips16_floatsidf");
11618 set_conv_libfunc (ufloat_optab, DFmode, SImode,
11619 "__mips16_floatunsidf");
11623 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
11624 on an external non-MIPS16 routine to implement __sync_synchronize.
11625 Similarly for the rest of the ll/sc libfuncs. */
11628 synchronize_libfunc = init_one_libfunc ("__sync_synchronize");
11629 init_sync_libfuncs (UNITS_PER_WORD);
11633 /* Build up a multi-insn sequence that loads label TARGET into $AT. */
11636 mips_process_load_label (rtx target)
11638 rtx base, gp, intop;
11639 HOST_WIDE_INT offset;
11641 mips_multi_start ();
11645 mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target, 0);
11646 mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target, 0);
11650 mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target, 0);
11651 mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target, 0);
11655 gp = pic_offset_table_rtx;
11656 if (mips_cfun_has_cprestore_slot_p ())
11658 gp = gen_rtx_REG (Pmode, AT_REGNUM);
11659 mips_get_cprestore_base_and_offset (&base, &offset, true);
11660 if (!SMALL_OPERAND (offset))
11662 intop = GEN_INT (CONST_HIGH_PART (offset));
11663 mips_multi_add_insn ("lui\t%0,%1", gp, intop, 0);
11664 mips_multi_add_insn ("addu\t%0,%0,%1", gp, base, 0);
11667 offset = CONST_LOW_PART (offset);
11669 intop = GEN_INT (offset);
11670 if (ISA_HAS_LOAD_DELAY)
11671 mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp, intop, base, 0);
11673 mips_multi_add_insn ("lw\t%0,%1(%2)", gp, intop, base, 0);
11675 if (ISA_HAS_LOAD_DELAY)
11676 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target, gp, 0);
11678 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target, gp, 0);
11679 mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target, 0);
11684 /* Return the number of instructions needed to load a label into $AT. */
11686 static unsigned int
11687 mips_load_label_num_insns (void)
11689 if (cfun->machine->load_label_num_insns == 0)
11691 mips_process_load_label (pc_rtx);
11692 cfun->machine->load_label_num_insns = mips_multi_num_insns;
11694 return cfun->machine->load_label_num_insns;
11697 /* Emit an asm sequence to start a noat block and load the address
11698 of a label into $1. */
11701 mips_output_load_label (rtx target)
11703 mips_push_asm_switch (&mips_noat);
11704 if (TARGET_EXPLICIT_RELOCS)
11706 mips_process_load_label (target);
11707 mips_multi_write ();
11711 if (Pmode == DImode)
11712 output_asm_insn ("dla\t%@,%0", &target);
11714 output_asm_insn ("la\t%@,%0", &target);
11718 /* Return the length of INSN. LENGTH is the initial length computed by
11719 attributes in the machine-description file. */
11722 mips_adjust_insn_length (rtx insn, int length)
11724 /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length
11725 of a PIC long-branch sequence. Substitute the correct value. */
11726 if (length == MAX_PIC_BRANCH_LENGTH
11727 && INSN_CODE (insn) >= 0
11728 && get_attr_type (insn) == TYPE_BRANCH)
11730 /* Add the branch-over instruction and its delay slot, if this
11731 is a conditional branch. */
11732 length = simplejump_p (insn) ? 0 : 8;
11734 /* Load the label into $AT and jump to it. Ignore the delay
11735 slot of the jump. */
11736 length += 4 * mips_load_label_num_insns() + 4;
11739 /* A unconditional jump has an unfilled delay slot if it is not part
11740 of a sequence. A conditional jump normally has a delay slot, but
11741 does not on MIPS16. */
11742 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
11745 /* See how many nops might be needed to avoid hardware hazards. */
11746 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
11747 switch (get_attr_hazard (insn))
11761 /* In order to make it easier to share MIPS16 and non-MIPS16 patterns,
11762 the .md file length attributes are 4-based for both modes.
11763 Adjust the MIPS16 ones here. */
11770 /* Return the assembly code for INSN, which has the operands given by
11771 OPERANDS, and which branches to OPERANDS[0] if some condition is true.
11772 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0]
11773 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
11774 version of BRANCH_IF_TRUE. */
11777 mips_output_conditional_branch (rtx insn, rtx *operands,
11778 const char *branch_if_true,
11779 const char *branch_if_false)
11781 unsigned int length;
11782 rtx taken, not_taken;
11784 gcc_assert (LABEL_P (operands[0]));
11786 length = get_attr_length (insn);
11789 /* Just a simple conditional branch. */
11790 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
11791 return branch_if_true;
11794 /* Generate a reversed branch around a direct jump. This fallback does
11795 not use branch-likely instructions. */
11796 mips_branch_likely = false;
11797 not_taken = gen_label_rtx ();
11798 taken = operands[0];
11800 /* Generate the reversed branch to NOT_TAKEN. */
11801 operands[0] = not_taken;
11802 output_asm_insn (branch_if_false, operands);
11804 /* If INSN has a delay slot, we must provide delay slots for both the
11805 branch to NOT_TAKEN and the conditional jump. We must also ensure
11806 that INSN's delay slot is executed in the appropriate cases. */
11807 if (final_sequence)
11809 /* This first delay slot will always be executed, so use INSN's
11810 delay slot if is not annulled. */
11811 if (!INSN_ANNULLED_BRANCH_P (insn))
11813 final_scan_insn (XVECEXP (final_sequence, 0, 1),
11814 asm_out_file, optimize, 1, NULL);
11815 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
11818 output_asm_insn ("nop", 0);
11819 fprintf (asm_out_file, "\n");
11822 /* Output the unconditional branch to TAKEN. */
11823 if (TARGET_ABSOLUTE_JUMPS)
11824 output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken);
11827 mips_output_load_label (taken);
11828 output_asm_insn ("jr\t%@%]%/", 0);
11831 /* Now deal with its delay slot; see above. */
11832 if (final_sequence)
11834 /* This delay slot will only be executed if the branch is taken.
11835 Use INSN's delay slot if is annulled. */
11836 if (INSN_ANNULLED_BRANCH_P (insn))
11838 final_scan_insn (XVECEXP (final_sequence, 0, 1),
11839 asm_out_file, optimize, 1, NULL);
11840 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
11843 output_asm_insn ("nop", 0);
11844 fprintf (asm_out_file, "\n");
11847 /* Output NOT_TAKEN. */
11848 targetm.asm_out.internal_label (asm_out_file, "L",
11849 CODE_LABEL_NUMBER (not_taken));
11853 /* Return the assembly code for INSN, which branches to OPERANDS[0]
11854 if some ordering condition is true. The condition is given by
11855 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
11856 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
11857 its second is always zero. */
11860 mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
11862 const char *branch[2];
11864 /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true.
11865 Make BRANCH[0] branch on the inverse condition. */
11866 switch (GET_CODE (operands[1]))
11868 /* These cases are equivalent to comparisons against zero. */
11870 inverted_p = !inverted_p;
11871 /* Fall through. */
11873 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%0");
11874 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%0");
11877 /* These cases are always true or always false. */
11879 inverted_p = !inverted_p;
11880 /* Fall through. */
11882 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%0");
11883 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%0");
11887 branch[!inverted_p] = MIPS_BRANCH ("b%C1z", "%2,%0");
11888 branch[inverted_p] = MIPS_BRANCH ("b%N1z", "%2,%0");
11891 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
11894 /* Start a block of code that needs access to the LL, SC and SYNC
11898 mips_start_ll_sc_sync_block (void)
11900 if (!ISA_HAS_LL_SC)
11902 output_asm_insn (".set\tpush", 0);
11903 output_asm_insn (".set\tmips2", 0);
11907 /* End a block started by mips_start_ll_sc_sync_block. */
11910 mips_end_ll_sc_sync_block (void)
11912 if (!ISA_HAS_LL_SC)
11913 output_asm_insn (".set\tpop", 0);
11916 /* Output and/or return the asm template for a sync instruction. */
11919 mips_output_sync (void)
11921 mips_start_ll_sc_sync_block ();
11922 output_asm_insn ("sync", 0);
11923 mips_end_ll_sc_sync_block ();
11927 /* Return the asm template associated with sync_insn1 value TYPE.
11928 IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */
11930 static const char *
11931 mips_sync_insn1_template (enum attr_sync_insn1 type, bool is_64bit_p)
11935 case SYNC_INSN1_MOVE:
11936 return "move\t%0,%z2";
11937 case SYNC_INSN1_LI:
11938 return "li\t%0,%2";
11939 case SYNC_INSN1_ADDU:
11940 return is_64bit_p ? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2";
11941 case SYNC_INSN1_ADDIU:
11942 return is_64bit_p ? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2";
11943 case SYNC_INSN1_SUBU:
11944 return is_64bit_p ? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2";
11945 case SYNC_INSN1_AND:
11946 return "and\t%0,%1,%z2";
11947 case SYNC_INSN1_ANDI:
11948 return "andi\t%0,%1,%2";
11949 case SYNC_INSN1_OR:
11950 return "or\t%0,%1,%z2";
11951 case SYNC_INSN1_ORI:
11952 return "ori\t%0,%1,%2";
11953 case SYNC_INSN1_XOR:
11954 return "xor\t%0,%1,%z2";
11955 case SYNC_INSN1_XORI:
11956 return "xori\t%0,%1,%2";
11958 gcc_unreachable ();
11961 /* Return the asm template associated with sync_insn2 value TYPE. */
11963 static const char *
11964 mips_sync_insn2_template (enum attr_sync_insn2 type)
11968 case SYNC_INSN2_NOP:
11969 gcc_unreachable ();
11970 case SYNC_INSN2_AND:
11971 return "and\t%0,%1,%z2";
11972 case SYNC_INSN2_XOR:
11973 return "xor\t%0,%1,%z2";
11974 case SYNC_INSN2_NOT:
11975 return "nor\t%0,%1,%.";
11977 gcc_unreachable ();
11980 /* OPERANDS are the operands to a sync loop instruction and INDEX is
11981 the value of the one of the sync_* attributes. Return the operand
11982 referred to by the attribute, or DEFAULT_VALUE if the insn doesn't
11983 have the associated attribute. */
11986 mips_get_sync_operand (rtx *operands, int index, rtx default_value)
11989 default_value = operands[index - 1];
11990 return default_value;
11993 /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn
11994 sequence for it. */
11997 mips_process_sync_loop (rtx insn, rtx *operands)
11999 rtx at, mem, oldval, newval, inclusive_mask, exclusive_mask;
12000 rtx required_oldval, insn1_op2, tmp1, tmp2, tmp3;
12001 unsigned int tmp3_insn;
12002 enum attr_sync_insn1 insn1;
12003 enum attr_sync_insn2 insn2;
12006 /* Read an operand from the sync_WHAT attribute and store it in
12007 variable WHAT. DEFAULT is the default value if no attribute
12009 #define READ_OPERAND(WHAT, DEFAULT) \
12010 WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \
12013 /* Read the memory. */
12014 READ_OPERAND (mem, 0);
12016 is_64bit_p = (GET_MODE_BITSIZE (GET_MODE (mem)) == 64);
12018 /* Read the other attributes. */
12019 at = gen_rtx_REG (GET_MODE (mem), AT_REGNUM);
12020 READ_OPERAND (oldval, at);
12021 READ_OPERAND (newval, at);
12022 READ_OPERAND (inclusive_mask, 0);
12023 READ_OPERAND (exclusive_mask, 0);
12024 READ_OPERAND (required_oldval, 0);
12025 READ_OPERAND (insn1_op2, 0);
12026 insn1 = get_attr_sync_insn1 (insn);
12027 insn2 = get_attr_sync_insn2 (insn);
12029 mips_multi_start ();
12031 /* Output the release side of the memory barrier. */
12032 if (get_attr_sync_release_barrier (insn) == SYNC_RELEASE_BARRIER_YES)
12034 if (required_oldval == 0 && TARGET_OCTEON)
12036 /* Octeon doesn't reorder reads, so a full barrier can be
12037 created by using SYNCW to order writes combined with the
12038 write from the following SC. When the SC successfully
12039 completes, we know that all preceding writes are also
12040 committed to the coherent memory system. It is possible
12041 for a single SYNCW to fail, but a pair of them will never
12042 fail, so we use two. */
12043 mips_multi_add_insn ("syncw", NULL);
12044 mips_multi_add_insn ("syncw", NULL);
12047 mips_multi_add_insn ("sync", NULL);
12050 /* Output the branch-back label. */
12051 mips_multi_add_label ("1:");
12053 /* OLDVAL = *MEM. */
12054 mips_multi_add_insn (is_64bit_p ? "lld\t%0,%1" : "ll\t%0,%1",
12055 oldval, mem, NULL);
12057 /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */
12058 if (required_oldval)
12060 if (inclusive_mask == 0)
12064 gcc_assert (oldval != at);
12065 mips_multi_add_insn ("and\t%0,%1,%2",
12066 at, oldval, inclusive_mask, NULL);
12069 mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1, required_oldval, NULL);
12072 /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */
12073 if (exclusive_mask == 0)
12077 gcc_assert (oldval != at);
12078 mips_multi_add_insn ("and\t%0,%1,%z2",
12079 at, oldval, exclusive_mask, NULL);
12083 /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2).
12085 We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit
12086 at least one instruction in that case. */
12087 if (insn1 == SYNC_INSN1_MOVE
12088 && (tmp1 != const0_rtx || insn2 != SYNC_INSN2_NOP))
12092 mips_multi_add_insn (mips_sync_insn1_template (insn1, is_64bit_p),
12093 newval, oldval, insn1_op2, NULL);
12097 /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */
12098 if (insn2 == SYNC_INSN2_NOP)
12102 mips_multi_add_insn (mips_sync_insn2_template (insn2),
12103 newval, tmp2, inclusive_mask, NULL);
12106 tmp3_insn = mips_multi_last_index ();
12108 /* $AT = $TMP1 | $TMP3. */
12109 if (tmp1 == const0_rtx || tmp3 == const0_rtx)
12111 mips_multi_set_operand (tmp3_insn, 0, at);
12116 gcc_assert (tmp1 != tmp3);
12117 mips_multi_add_insn ("or\t%0,%1,%2", at, tmp1, tmp3, NULL);
12120 /* if (!commit (*MEM = $AT)) goto 1.
12122 This will sometimes be a delayed branch; see the write code below
12124 mips_multi_add_insn (is_64bit_p ? "scd\t%0,%1" : "sc\t%0,%1", at, mem, NULL);
12125 mips_multi_add_insn ("beq%?\t%0,%.,1b", at, NULL);
12127 /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */
12128 if (insn1 != SYNC_INSN1_MOVE && insn1 != SYNC_INSN1_LI && tmp3 != newval)
12130 mips_multi_copy_insn (tmp3_insn);
12131 mips_multi_set_operand (mips_multi_last_index (), 0, newval);
12134 mips_multi_add_insn ("nop", NULL);
12136 /* Output the acquire side of the memory barrier. */
12137 if (TARGET_SYNC_AFTER_SC)
12138 mips_multi_add_insn ("sync", NULL);
12140 /* Output the exit label, if needed. */
12141 if (required_oldval)
12142 mips_multi_add_label ("2:");
12144 #undef READ_OPERAND
12147 /* Output and/or return the asm template for sync loop INSN, which has
12148 the operands given by OPERANDS. */
12151 mips_output_sync_loop (rtx insn, rtx *operands)
12153 mips_process_sync_loop (insn, operands);
12155 /* Use branch-likely instructions to work around the LL/SC R10000
12157 mips_branch_likely = TARGET_FIX_R10000;
12159 mips_push_asm_switch (&mips_noreorder);
12160 mips_push_asm_switch (&mips_nomacro);
12161 mips_push_asm_switch (&mips_noat);
12162 mips_start_ll_sc_sync_block ();
12164 mips_multi_write ();
12166 mips_end_ll_sc_sync_block ();
12167 mips_pop_asm_switch (&mips_noat);
12168 mips_pop_asm_switch (&mips_nomacro);
12169 mips_pop_asm_switch (&mips_noreorder);
12174 /* Return the number of individual instructions in sync loop INSN,
12175 which has the operands given by OPERANDS. */
12178 mips_sync_loop_insns (rtx insn, rtx *operands)
12180 mips_process_sync_loop (insn, operands);
12181 return mips_multi_num_insns;
12184 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
12185 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
12187 When working around R4000 and R4400 errata, we need to make sure that
12188 the division is not immediately followed by a shift[1][2]. We also
12189 need to stop the division from being put into a branch delay slot[3].
12190 The easiest way to avoid both problems is to add a nop after the
12191 division. When a divide-by-zero check is needed, this nop can be
12192 used to fill the branch delay slot.
12194 [1] If a double-word or a variable shift executes immediately
12195 after starting an integer division, the shift may give an
12196 incorrect result. See quotations of errata #16 and #28 from
12197 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
12198 in mips.md for details.
12200 [2] A similar bug to [1] exists for all revisions of the
12201 R4000 and the R4400 when run in an MC configuration.
12202 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
12204 "19. In this following sequence:
12206 ddiv (or ddivu or div or divu)
12207 dsll32 (or dsrl32, dsra32)
12209 if an MPT stall occurs, while the divide is slipping the cpu
12210 pipeline, then the following double shift would end up with an
12213 Workaround: The compiler needs to avoid generating any
12214 sequence with divide followed by extended double shift."
12216 This erratum is also present in "MIPS R4400MC Errata, Processor
12217 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
12218 & 3.0" as errata #10 and #4, respectively.
12220 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
12221 (also valid for MIPS R4000MC processors):
12223 "52. R4000SC: This bug does not apply for the R4000PC.
12225 There are two flavors of this bug:
12227 1) If the instruction just after divide takes an RF exception
12228 (tlb-refill, tlb-invalid) and gets an instruction cache
12229 miss (both primary and secondary) and the line which is
12230 currently in secondary cache at this index had the first
12231 data word, where the bits 5..2 are set, then R4000 would
12232 get a wrong result for the div.
12237 ------------------- # end-of page. -tlb-refill
12242 ------------------- # end-of page. -tlb-invalid
12245 2) If the divide is in the taken branch delay slot, where the
12246 target takes RF exception and gets an I-cache miss for the
12247 exception vector or where I-cache miss occurs for the
12248 target address, under the above mentioned scenarios, the
12249 div would get wrong results.
12252 j r2 # to next page mapped or unmapped
12253 div r8,r9 # this bug would be there as long
12254 # as there is an ICache miss and
12255 nop # the "data pattern" is present
12258 beq r0, r0, NextPage # to Next page
12262 This bug is present for div, divu, ddiv, and ddivu
12265 Workaround: For item 1), OS could make sure that the next page
12266 after the divide instruction is also mapped. For item 2), the
12267 compiler could make sure that the divide instruction is not in
12268 the branch delay slot."
12270 These processors have PRId values of 0x00004220 and 0x00004300 for
12271 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
12274 mips_output_division (const char *division, rtx *operands)
12279 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
12281 output_asm_insn (s, operands);
12284 if (TARGET_CHECK_ZERO_DIV)
12288 output_asm_insn (s, operands);
12289 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
12291 else if (GENERATE_DIVIDE_TRAPS)
12293 /* Avoid long replay penalty on load miss by putting the trap before
12296 output_asm_insn ("teq\t%2,%.,7", operands);
12299 output_asm_insn (s, operands);
12300 s = "teq\t%2,%.,7";
12305 output_asm_insn ("%(bne\t%2,%.,1f", operands);
12306 output_asm_insn (s, operands);
12307 s = "break\t7%)\n1:";
12313 /* Return true if IN_INSN is a multiply-add or multiply-subtract
12314 instruction and if OUT_INSN assigns to the accumulator operand. */
12317 mips_linked_madd_p (rtx out_insn, rtx in_insn)
12321 x = single_set (in_insn);
12327 if (GET_CODE (x) == PLUS
12328 && GET_CODE (XEXP (x, 0)) == MULT
12329 && reg_set_p (XEXP (x, 1), out_insn))
12332 if (GET_CODE (x) == MINUS
12333 && GET_CODE (XEXP (x, 1)) == MULT
12334 && reg_set_p (XEXP (x, 0), out_insn))
12340 /* True if the dependency between OUT_INSN and IN_INSN is on the store
12341 data rather than the address. We need this because the cprestore
12342 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
12343 which causes the default routine to abort. We just return false
12347 mips_store_data_bypass_p (rtx out_insn, rtx in_insn)
12349 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
12352 return !store_data_bypass_p (out_insn, in_insn);
12356 /* Variables and flags used in scheduler hooks when tuning for
12360 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
12363 /* If true, then next ALU1/2 instruction will go to ALU1. */
12366 /* If true, then next FALU1/2 unstruction will go to FALU1. */
12369 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
12370 int alu1_core_unit_code;
12371 int alu2_core_unit_code;
12372 int falu1_core_unit_code;
12373 int falu2_core_unit_code;
12375 /* True if current cycle has a multi instruction.
12376 This flag is used in mips_ls2_dfa_post_advance_cycle. */
12377 bool cycle_has_multi_p;
12379 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
12380 These are used in mips_ls2_dfa_post_advance_cycle to initialize
12382 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
12383 instruction to go ALU1. */
12384 rtx alu1_turn_enabled_insn;
12385 rtx alu2_turn_enabled_insn;
12386 rtx falu1_turn_enabled_insn;
12387 rtx falu2_turn_enabled_insn;
12390 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
12391 dependencies have no cost, except on the 20Kc where output-dependence
12392 is treated like input-dependence. */
12395 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
12396 rtx dep ATTRIBUTE_UNUSED, int cost)
12398 if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT
12401 if (REG_NOTE_KIND (link) != 0)
12406 /* Return the number of instructions that can be issued per cycle. */
12409 mips_issue_rate (void)
12413 case PROCESSOR_74KC:
12414 case PROCESSOR_74KF2_1:
12415 case PROCESSOR_74KF1_1:
12416 case PROCESSOR_74KF3_2:
12417 /* The 74k is not strictly quad-issue cpu, but can be seen as one
12418 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
12419 but in reality only a maximum of 3 insns can be issued as
12420 floating-point loads and stores also require a slot in the
12422 case PROCESSOR_R10000:
12423 /* All R10K Processors are quad-issue (being the first MIPS
12424 processors to support this feature). */
12427 case PROCESSOR_20KC:
12428 case PROCESSOR_R4130:
12429 case PROCESSOR_R5400:
12430 case PROCESSOR_R5500:
12431 case PROCESSOR_R7000:
12432 case PROCESSOR_R9000:
12433 case PROCESSOR_OCTEON:
12434 case PROCESSOR_OCTEON2:
12437 case PROCESSOR_SB1:
12438 case PROCESSOR_SB1A:
12439 /* This is actually 4, but we get better performance if we claim 3.
12440 This is partly because of unwanted speculative code motion with the
12441 larger number, and partly because in most common cases we can't
12442 reach the theoretical max of 4. */
12445 case PROCESSOR_LOONGSON_2E:
12446 case PROCESSOR_LOONGSON_2F:
12447 case PROCESSOR_LOONGSON_3A:
12455 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
12458 mips_ls2_init_dfa_post_cycle_insn (void)
12461 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
12462 mips_ls2.alu1_turn_enabled_insn = get_insns ();
12466 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
12467 mips_ls2.alu2_turn_enabled_insn = get_insns ();
12471 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
12472 mips_ls2.falu1_turn_enabled_insn = get_insns ();
12476 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
12477 mips_ls2.falu2_turn_enabled_insn = get_insns ();
12480 mips_ls2.alu1_core_unit_code = get_cpu_unit_code ("ls2_alu1_core");
12481 mips_ls2.alu2_core_unit_code = get_cpu_unit_code ("ls2_alu2_core");
12482 mips_ls2.falu1_core_unit_code = get_cpu_unit_code ("ls2_falu1_core");
12483 mips_ls2.falu2_core_unit_code = get_cpu_unit_code ("ls2_falu2_core");
12486 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
12487 Init data used in mips_dfa_post_advance_cycle. */
12490 mips_init_dfa_post_cycle_insn (void)
12492 if (TUNE_LOONGSON_2EF)
12493 mips_ls2_init_dfa_post_cycle_insn ();
12496 /* Initialize STATE when scheduling for Loongson 2E/2F.
12497 Support round-robin dispatch scheme by enabling only one of
12498 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
12502 mips_ls2_dfa_post_advance_cycle (state_t state)
12504 if (cpu_unit_reservation_p (state, mips_ls2.alu1_core_unit_code))
12506 /* Though there are no non-pipelined ALU1 insns,
12507 we can get an instruction of type 'multi' before reload. */
12508 gcc_assert (mips_ls2.cycle_has_multi_p);
12509 mips_ls2.alu1_turn_p = false;
12512 mips_ls2.cycle_has_multi_p = false;
12514 if (cpu_unit_reservation_p (state, mips_ls2.alu2_core_unit_code))
12515 /* We have a non-pipelined alu instruction in the core,
12516 adjust round-robin counter. */
12517 mips_ls2.alu1_turn_p = true;
12519 if (mips_ls2.alu1_turn_p)
12521 if (state_transition (state, mips_ls2.alu1_turn_enabled_insn) >= 0)
12522 gcc_unreachable ();
12526 if (state_transition (state, mips_ls2.alu2_turn_enabled_insn) >= 0)
12527 gcc_unreachable ();
12530 if (cpu_unit_reservation_p (state, mips_ls2.falu1_core_unit_code))
12532 /* There are no non-pipelined FALU1 insns. */
12533 gcc_unreachable ();
12534 mips_ls2.falu1_turn_p = false;
12537 if (cpu_unit_reservation_p (state, mips_ls2.falu2_core_unit_code))
12538 /* We have a non-pipelined falu instruction in the core,
12539 adjust round-robin counter. */
12540 mips_ls2.falu1_turn_p = true;
12542 if (mips_ls2.falu1_turn_p)
12544 if (state_transition (state, mips_ls2.falu1_turn_enabled_insn) >= 0)
12545 gcc_unreachable ();
12549 if (state_transition (state, mips_ls2.falu2_turn_enabled_insn) >= 0)
12550 gcc_unreachable ();
12554 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
12555 This hook is being called at the start of each cycle. */
12558 mips_dfa_post_advance_cycle (void)
12560 if (TUNE_LOONGSON_2EF)
12561 mips_ls2_dfa_post_advance_cycle (curr_state);
12564 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
12565 be as wide as the scheduling freedom in the DFA. */
12568 mips_multipass_dfa_lookahead (void)
12570 /* Can schedule up to 4 of the 6 function units in any one cycle. */
12574 if (TUNE_LOONGSON_2EF || TUNE_LOONGSON_3A)
12583 /* Remove the instruction at index LOWER from ready queue READY and
12584 reinsert it in front of the instruction at index HIGHER. LOWER must
12588 mips_promote_ready (rtx *ready, int lower, int higher)
12593 new_head = ready[lower];
12594 for (i = lower; i < higher; i++)
12595 ready[i] = ready[i + 1];
12596 ready[i] = new_head;
12599 /* If the priority of the instruction at POS2 in the ready queue READY
12600 is within LIMIT units of that of the instruction at POS1, swap the
12601 instructions if POS2 is not already less than POS1. */
12604 mips_maybe_swap_ready (rtx *ready, int pos1, int pos2, int limit)
12607 && INSN_PRIORITY (ready[pos1]) + limit >= INSN_PRIORITY (ready[pos2]))
12611 temp = ready[pos1];
12612 ready[pos1] = ready[pos2];
12613 ready[pos2] = temp;
12617 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
12618 that may clobber hi or lo. */
12619 static rtx mips_macc_chains_last_hilo;
12621 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
12622 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
12625 mips_macc_chains_record (rtx insn)
12627 if (get_attr_may_clobber_hilo (insn))
12628 mips_macc_chains_last_hilo = insn;
12631 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
12632 has NREADY elements, looking for a multiply-add or multiply-subtract
12633 instruction that is cumulative with mips_macc_chains_last_hilo.
12634 If there is one, promote it ahead of anything else that might
12635 clobber hi or lo. */
12638 mips_macc_chains_reorder (rtx *ready, int nready)
12642 if (mips_macc_chains_last_hilo != 0)
12643 for (i = nready - 1; i >= 0; i--)
12644 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
12646 for (j = nready - 1; j > i; j--)
12647 if (recog_memoized (ready[j]) >= 0
12648 && get_attr_may_clobber_hilo (ready[j]))
12650 mips_promote_ready (ready, i, j);
12657 /* The last instruction to be scheduled. */
12658 static rtx vr4130_last_insn;
12660 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
12661 points to an rtx that is initially an instruction. Nullify the rtx
12662 if the instruction uses the value of register X. */
12665 vr4130_true_reg_dependence_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
12670 insn_ptr = (rtx *) data;
12673 && reg_referenced_p (x, PATTERN (*insn_ptr)))
12677 /* Return true if there is true register dependence between vr4130_last_insn
12681 vr4130_true_reg_dependence_p (rtx insn)
12683 note_stores (PATTERN (vr4130_last_insn),
12684 vr4130_true_reg_dependence_p_1, &insn);
12688 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
12689 the ready queue and that INSN2 is the instruction after it, return
12690 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
12691 in which INSN1 and INSN2 can probably issue in parallel, but for
12692 which (INSN2, INSN1) should be less sensitive to instruction
12693 alignment than (INSN1, INSN2). See 4130.md for more details. */
12696 vr4130_swap_insns_p (rtx insn1, rtx insn2)
12698 sd_iterator_def sd_it;
12701 /* Check for the following case:
12703 1) there is some other instruction X with an anti dependence on INSN1;
12704 2) X has a higher priority than INSN2; and
12705 3) X is an arithmetic instruction (and thus has no unit restrictions).
12707 If INSN1 is the last instruction blocking X, it would better to
12708 choose (INSN1, X) over (INSN2, INSN1). */
12709 FOR_EACH_DEP (insn1, SD_LIST_FORW, sd_it, dep)
12710 if (DEP_TYPE (dep) == REG_DEP_ANTI
12711 && INSN_PRIORITY (DEP_CON (dep)) > INSN_PRIORITY (insn2)
12712 && recog_memoized (DEP_CON (dep)) >= 0
12713 && get_attr_vr4130_class (DEP_CON (dep)) == VR4130_CLASS_ALU)
12716 if (vr4130_last_insn != 0
12717 && recog_memoized (insn1) >= 0
12718 && recog_memoized (insn2) >= 0)
12720 /* See whether INSN1 and INSN2 use different execution units,
12721 or if they are both ALU-type instructions. If so, they can
12722 probably execute in parallel. */
12723 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
12724 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
12725 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
12727 /* If only one of the instructions has a dependence on
12728 vr4130_last_insn, prefer to schedule the other one first. */
12729 bool dep1_p = vr4130_true_reg_dependence_p (insn1);
12730 bool dep2_p = vr4130_true_reg_dependence_p (insn2);
12731 if (dep1_p != dep2_p)
12734 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
12735 is not an ALU-type instruction and if INSN1 uses the same
12736 execution unit. (Note that if this condition holds, we already
12737 know that INSN2 uses a different execution unit.) */
12738 if (class1 != VR4130_CLASS_ALU
12739 && recog_memoized (vr4130_last_insn) >= 0
12740 && class1 == get_attr_vr4130_class (vr4130_last_insn))
12747 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
12748 queue with at least two instructions. Swap the first two if
12749 vr4130_swap_insns_p says that it could be worthwhile. */
12752 vr4130_reorder (rtx *ready, int nready)
12754 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
12755 mips_promote_ready (ready, nready - 2, nready - 1);
12758 /* Record whether last 74k AGEN instruction was a load or store. */
12759 static enum attr_type mips_last_74k_agen_insn = TYPE_UNKNOWN;
12761 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
12762 resets to TYPE_UNKNOWN state. */
12765 mips_74k_agen_init (rtx insn)
12767 if (!insn || CALL_P (insn) || JUMP_P (insn))
12768 mips_last_74k_agen_insn = TYPE_UNKNOWN;
12771 enum attr_type type = get_attr_type (insn);
12772 if (type == TYPE_LOAD || type == TYPE_STORE)
12773 mips_last_74k_agen_insn = type;
12777 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
12778 loads to be grouped together, and multiple stores to be grouped
12779 together. Swap things around in the ready queue to make this happen. */
12782 mips_74k_agen_reorder (rtx *ready, int nready)
12785 int store_pos, load_pos;
12790 for (i = nready - 1; i >= 0; i--)
12792 rtx insn = ready[i];
12793 if (USEFUL_INSN_P (insn))
12794 switch (get_attr_type (insn))
12797 if (store_pos == -1)
12802 if (load_pos == -1)
12811 if (load_pos == -1 || store_pos == -1)
12814 switch (mips_last_74k_agen_insn)
12817 /* Prefer to schedule loads since they have a higher latency. */
12819 /* Swap loads to the front of the queue. */
12820 mips_maybe_swap_ready (ready, load_pos, store_pos, 4);
12823 /* Swap stores to the front of the queue. */
12824 mips_maybe_swap_ready (ready, store_pos, load_pos, 4);
12831 /* Implement TARGET_SCHED_INIT. */
12834 mips_sched_init (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12835 int max_ready ATTRIBUTE_UNUSED)
12837 mips_macc_chains_last_hilo = 0;
12838 vr4130_last_insn = 0;
12839 mips_74k_agen_init (NULL_RTX);
12841 /* When scheduling for Loongson2, branch instructions go to ALU1,
12842 therefore basic block is most likely to start with round-robin counter
12843 pointed to ALU2. */
12844 mips_ls2.alu1_turn_p = false;
12845 mips_ls2.falu1_turn_p = true;
12848 /* Subroutine used by TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
12851 mips_sched_reorder_1 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12852 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
12854 if (!reload_completed
12855 && TUNE_MACC_CHAINS
12857 mips_macc_chains_reorder (ready, *nreadyp);
12859 if (reload_completed
12861 && !TARGET_VR4130_ALIGN
12863 vr4130_reorder (ready, *nreadyp);
12866 mips_74k_agen_reorder (ready, *nreadyp);
12869 /* Implement TARGET_SCHED_REORDER. */
12872 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12873 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
12875 mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle);
12876 return mips_issue_rate ();
12879 /* Implement TARGET_SCHED_REORDER2. */
12882 mips_sched_reorder2 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12883 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
12885 mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle);
12886 return cached_can_issue_more;
12889 /* Update round-robin counters for ALU1/2 and FALU1/2. */
12892 mips_ls2_variable_issue (rtx insn)
12894 if (mips_ls2.alu1_turn_p)
12896 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu1_core_unit_code))
12897 mips_ls2.alu1_turn_p = false;
12901 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu2_core_unit_code))
12902 mips_ls2.alu1_turn_p = true;
12905 if (mips_ls2.falu1_turn_p)
12907 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu1_core_unit_code))
12908 mips_ls2.falu1_turn_p = false;
12912 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu2_core_unit_code))
12913 mips_ls2.falu1_turn_p = true;
12916 if (recog_memoized (insn) >= 0)
12917 mips_ls2.cycle_has_multi_p |= (get_attr_type (insn) == TYPE_MULTI);
12920 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
12923 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12924 rtx insn, int more)
12926 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
12927 if (USEFUL_INSN_P (insn))
12929 if (get_attr_type (insn) != TYPE_GHOST)
12931 if (!reload_completed && TUNE_MACC_CHAINS)
12932 mips_macc_chains_record (insn);
12933 vr4130_last_insn = insn;
12935 mips_74k_agen_init (insn);
12936 else if (TUNE_LOONGSON_2EF)
12937 mips_ls2_variable_issue (insn);
12940 /* Instructions of type 'multi' should all be split before
12941 the second scheduling pass. */
12942 gcc_assert (!reload_completed
12943 || recog_memoized (insn) < 0
12944 || get_attr_type (insn) != TYPE_MULTI);
12946 cached_can_issue_more = more;
12950 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
12951 return the first operand of the associated PREF or PREFX insn. */
12954 mips_prefetch_cookie (rtx write, rtx locality)
12956 /* store_streamed / load_streamed. */
12957 if (INTVAL (locality) <= 0)
12958 return GEN_INT (INTVAL (write) + 4);
12960 /* store / load. */
12961 if (INTVAL (locality) <= 2)
12964 /* store_retained / load_retained. */
12965 return GEN_INT (INTVAL (write) + 6);
12968 /* Flags that indicate when a built-in function is available.
12970 BUILTIN_AVAIL_NON_MIPS16
12971 The function is available on the current target, but only
12972 in non-MIPS16 mode. */
12973 #define BUILTIN_AVAIL_NON_MIPS16 1
12975 /* Declare an availability predicate for built-in functions that
12976 require non-MIPS16 mode and also require COND to be true.
12977 NAME is the main part of the predicate's name. */
12978 #define AVAIL_NON_MIPS16(NAME, COND) \
12979 static unsigned int \
12980 mips_builtin_avail_##NAME (void) \
12982 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
12985 /* This structure describes a single built-in function. */
12986 struct mips_builtin_description {
12987 /* The code of the main .md file instruction. See mips_builtin_type
12988 for more information. */
12989 enum insn_code icode;
12991 /* The floating-point comparison code to use with ICODE, if any. */
12992 enum mips_fp_condition cond;
12994 /* The name of the built-in function. */
12997 /* Specifies how the function should be expanded. */
12998 enum mips_builtin_type builtin_type;
13000 /* The function's prototype. */
13001 enum mips_function_type function_type;
13003 /* Whether the function is available. */
13004 unsigned int (*avail) (void);
13007 AVAIL_NON_MIPS16 (paired_single, TARGET_PAIRED_SINGLE_FLOAT)
13008 AVAIL_NON_MIPS16 (sb1_paired_single, TARGET_SB1 && TARGET_PAIRED_SINGLE_FLOAT)
13009 AVAIL_NON_MIPS16 (mips3d, TARGET_MIPS3D)
13010 AVAIL_NON_MIPS16 (dsp, TARGET_DSP)
13011 AVAIL_NON_MIPS16 (dspr2, TARGET_DSPR2)
13012 AVAIL_NON_MIPS16 (dsp_32, !TARGET_64BIT && TARGET_DSP)
13013 AVAIL_NON_MIPS16 (dsp_64, TARGET_64BIT && TARGET_DSP)
13014 AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2)
13015 AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS)
13016 AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
13018 /* Construct a mips_builtin_description from the given arguments.
13020 INSN is the name of the associated instruction pattern, without the
13021 leading CODE_FOR_mips_.
13023 CODE is the floating-point condition code associated with the
13024 function. It can be 'f' if the field is not applicable.
13026 NAME is the name of the function itself, without the leading
13029 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
13031 AVAIL is the name of the availability predicate, without the leading
13032 mips_builtin_avail_. */
13033 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
13034 FUNCTION_TYPE, AVAIL) \
13035 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
13036 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
13037 mips_builtin_avail_ ## AVAIL }
13039 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
13040 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
13041 are as for MIPS_BUILTIN. */
13042 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
13043 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
13045 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
13046 are subject to mips_builtin_avail_<AVAIL>. */
13047 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
13048 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
13049 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
13050 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
13051 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
13053 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
13054 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
13055 while the any and all forms are subject to mips_builtin_avail_mips3d. */
13056 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
13057 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
13058 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
13060 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
13061 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
13063 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
13064 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
13066 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
13067 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
13070 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
13071 are subject to mips_builtin_avail_mips3d. */
13072 #define CMP_4S_BUILTINS(INSN, COND) \
13073 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
13074 MIPS_BUILTIN_CMP_ANY, \
13075 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
13076 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
13077 MIPS_BUILTIN_CMP_ALL, \
13078 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
13080 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
13081 instruction requires mips_builtin_avail_<AVAIL>. */
13082 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
13083 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
13084 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
13086 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
13087 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
13090 /* Define all the built-in functions related to C.cond.fmt condition COND. */
13091 #define CMP_BUILTINS(COND) \
13092 MOVTF_BUILTINS (c, COND, paired_single), \
13093 MOVTF_BUILTINS (cabs, COND, mips3d), \
13094 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
13095 CMP_PS_BUILTINS (c, COND, paired_single), \
13096 CMP_PS_BUILTINS (cabs, COND, mips3d), \
13097 CMP_4S_BUILTINS (c, COND), \
13098 CMP_4S_BUILTINS (cabs, COND)
13100 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
13101 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
13102 and AVAIL are as for MIPS_BUILTIN. */
13103 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
13104 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
13105 FUNCTION_TYPE, AVAIL)
13107 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
13108 branch instruction. AVAIL is as for MIPS_BUILTIN. */
13109 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
13110 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
13111 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
13113 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
13114 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
13115 builtin_description field. */
13116 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
13117 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
13118 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
13119 FUNCTION_TYPE, mips_builtin_avail_loongson }
13121 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
13122 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
13123 builtin_description field. */
13124 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
13125 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
13127 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
13128 We use functions of this form when the same insn can be usefully applied
13129 to more than one datatype. */
13130 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
13131 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
13133 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
13134 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
13135 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
13136 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
13137 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
13138 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
13139 #define CODE_FOR_mips_mult CODE_FOR_mulsidi3_32bit
13140 #define CODE_FOR_mips_multu CODE_FOR_umulsidi3_32bit
13142 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
13143 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
13144 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
13145 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
13146 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
13147 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
13148 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
13149 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
13150 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
13151 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
13152 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
13153 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
13154 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
13155 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
13156 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
13157 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
13158 #define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3
13159 #define CODE_FOR_loongson_psllh CODE_FOR_ashlv4hi3
13160 #define CODE_FOR_loongson_psllw CODE_FOR_ashlv2si3
13161 #define CODE_FOR_loongson_psrlh CODE_FOR_lshrv4hi3
13162 #define CODE_FOR_loongson_psrlw CODE_FOR_lshrv2si3
13163 #define CODE_FOR_loongson_psrah CODE_FOR_ashrv4hi3
13164 #define CODE_FOR_loongson_psraw CODE_FOR_ashrv2si3
13165 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
13166 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
13167 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
13168 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
13169 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
13170 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
13171 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
13173 static const struct mips_builtin_description mips_builtins[] = {
13174 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13175 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13176 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13177 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13178 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, paired_single),
13179 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, paired_single),
13180 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, paired_single),
13181 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, paired_single),
13183 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT, paired_single),
13184 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13185 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13186 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
13187 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, mips3d),
13189 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, mips3d),
13190 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, mips3d),
13191 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
13192 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
13193 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
13194 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13196 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, mips3d),
13197 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, mips3d),
13198 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
13199 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
13200 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
13201 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13203 MIPS_FP_CONDITIONS (CMP_BUILTINS),
13205 /* Built-in functions for the SB-1 processor. */
13206 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, sb1_paired_single),
13208 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
13209 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13210 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13211 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
13212 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13213 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13214 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13215 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13216 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
13217 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13218 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13219 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, dsp),
13220 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, dsp),
13221 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, dsp),
13222 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, dsp),
13223 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, dsp),
13224 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, dsp),
13225 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
13226 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
13227 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
13228 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
13229 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, dsp),
13230 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, dsp),
13231 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
13232 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
13233 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
13234 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
13235 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
13236 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
13237 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
13238 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
13239 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
13240 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
13241 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
13242 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
13243 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
13244 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
13245 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
13246 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, dsp),
13247 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
13248 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
13249 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13250 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
13251 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
13252 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, dsp),
13253 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, dsp),
13254 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, dsp),
13255 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, dsp),
13256 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
13257 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
13258 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
13259 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
13260 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
13261 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
13262 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
13263 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
13264 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
13265 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13266 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13267 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13268 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, dsp),
13269 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, dsp),
13270 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_POINTER_SI, dsp),
13271 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_POINTER_SI, dsp),
13272 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_POINTER_SI, dsp),
13273 BPOSGE_BUILTIN (32, dsp),
13275 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
13276 DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, dspr2),
13277 DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13278 DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13279 DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
13280 DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
13281 DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
13282 DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
13283 DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
13284 DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
13285 DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
13286 DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13287 DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13288 DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13289 DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13290 DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13291 DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dspr2),
13292 DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
13293 DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
13294 DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
13295 DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
13296 DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
13297 DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, dspr2),
13298 DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13299 DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13300 DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
13301 DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
13302 DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13303 DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13304 DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13305 DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13306 DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13307 DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13308 DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13309 DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13311 /* Built-in functions for the DSP ASE (32-bit only). */
13312 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
13313 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
13314 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
13315 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
13316 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13317 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13318 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13319 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
13320 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
13321 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13322 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13323 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13324 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13325 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
13326 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
13327 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
13328 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, dsp_32),
13329 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, dsp_32),
13330 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, dsp_32),
13331 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, dsp_32),
13332 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, dsp_32),
13333 DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
13334 DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32),
13335 DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
13336 DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32),
13337 DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, dsp_32),
13338 DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, dsp_32),
13340 /* Built-in functions for the DSP ASE (64-bit only). */
13341 DIRECT_BUILTIN (ldx, MIPS_DI_FTYPE_POINTER_SI, dsp_64),
13343 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
13344 DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13345 DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13346 DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13347 DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13348 DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13349 DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13350 DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13351 DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13352 DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13354 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
13355 LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI),
13356 LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI),
13357 LOONGSON_BUILTIN (packushb, MIPS_UV8QI_FTYPE_UV4HI_UV4HI),
13358 LOONGSON_BUILTIN_SUFFIX (paddw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13359 LOONGSON_BUILTIN_SUFFIX (paddh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13360 LOONGSON_BUILTIN_SUFFIX (paddb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13361 LOONGSON_BUILTIN_SUFFIX (paddw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13362 LOONGSON_BUILTIN_SUFFIX (paddh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13363 LOONGSON_BUILTIN_SUFFIX (paddb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13364 LOONGSON_BUILTIN_SUFFIX (paddd, u, MIPS_UDI_FTYPE_UDI_UDI),
13365 LOONGSON_BUILTIN_SUFFIX (paddd, s, MIPS_DI_FTYPE_DI_DI),
13366 LOONGSON_BUILTIN (paddsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13367 LOONGSON_BUILTIN (paddsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
13368 LOONGSON_BUILTIN (paddush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13369 LOONGSON_BUILTIN (paddusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13370 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_ud, MIPS_UDI_FTYPE_UDI_UDI),
13371 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_uw, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13372 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_uh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13373 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_ub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13374 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_sd, MIPS_DI_FTYPE_DI_DI),
13375 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_sw, MIPS_V2SI_FTYPE_V2SI_V2SI),
13376 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_sh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13377 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_sb, MIPS_V8QI_FTYPE_V8QI_V8QI),
13378 LOONGSON_BUILTIN (pavgh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13379 LOONGSON_BUILTIN (pavgb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13380 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13381 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13382 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13383 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13384 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13385 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13386 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13387 LOONGSON_BUILTIN_SUFFIX (pcmpgth, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13388 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13389 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13390 LOONGSON_BUILTIN_SUFFIX (pcmpgth, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13391 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13392 LOONGSON_BUILTIN_SUFFIX (pextrh, u, MIPS_UV4HI_FTYPE_UV4HI_USI),
13393 LOONGSON_BUILTIN_SUFFIX (pextrh, s, MIPS_V4HI_FTYPE_V4HI_USI),
13394 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13395 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13396 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13397 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13398 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13399 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13400 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13401 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13402 LOONGSON_BUILTIN (pmaddhw, MIPS_V2SI_FTYPE_V4HI_V4HI),
13403 LOONGSON_BUILTIN (pmaxsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13404 LOONGSON_BUILTIN (pmaxub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13405 LOONGSON_BUILTIN (pminsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13406 LOONGSON_BUILTIN (pminub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13407 LOONGSON_BUILTIN_SUFFIX (pmovmskb, u, MIPS_UV8QI_FTYPE_UV8QI),
13408 LOONGSON_BUILTIN_SUFFIX (pmovmskb, s, MIPS_V8QI_FTYPE_V8QI),
13409 LOONGSON_BUILTIN (pmulhuh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13410 LOONGSON_BUILTIN (pmulhh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13411 LOONGSON_BUILTIN (pmullh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13412 LOONGSON_BUILTIN (pmuluw, MIPS_UDI_FTYPE_UV2SI_UV2SI),
13413 LOONGSON_BUILTIN (pasubub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13414 LOONGSON_BUILTIN (biadd, MIPS_UV4HI_FTYPE_UV8QI),
13415 LOONGSON_BUILTIN (psadbh, MIPS_UV4HI_FTYPE_UV8QI_UV8QI),
13416 LOONGSON_BUILTIN_SUFFIX (pshufh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
13417 LOONGSON_BUILTIN_SUFFIX (pshufh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
13418 LOONGSON_BUILTIN_SUFFIX (psllh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
13419 LOONGSON_BUILTIN_SUFFIX (psllh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
13420 LOONGSON_BUILTIN_SUFFIX (psllw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
13421 LOONGSON_BUILTIN_SUFFIX (psllw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
13422 LOONGSON_BUILTIN_SUFFIX (psrah, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
13423 LOONGSON_BUILTIN_SUFFIX (psrah, s, MIPS_V4HI_FTYPE_V4HI_UQI),
13424 LOONGSON_BUILTIN_SUFFIX (psraw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
13425 LOONGSON_BUILTIN_SUFFIX (psraw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
13426 LOONGSON_BUILTIN_SUFFIX (psrlh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
13427 LOONGSON_BUILTIN_SUFFIX (psrlh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
13428 LOONGSON_BUILTIN_SUFFIX (psrlw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
13429 LOONGSON_BUILTIN_SUFFIX (psrlw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
13430 LOONGSON_BUILTIN_SUFFIX (psubw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13431 LOONGSON_BUILTIN_SUFFIX (psubh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13432 LOONGSON_BUILTIN_SUFFIX (psubb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13433 LOONGSON_BUILTIN_SUFFIX (psubw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13434 LOONGSON_BUILTIN_SUFFIX (psubh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13435 LOONGSON_BUILTIN_SUFFIX (psubb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13436 LOONGSON_BUILTIN_SUFFIX (psubd, u, MIPS_UDI_FTYPE_UDI_UDI),
13437 LOONGSON_BUILTIN_SUFFIX (psubd, s, MIPS_DI_FTYPE_DI_DI),
13438 LOONGSON_BUILTIN (psubsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13439 LOONGSON_BUILTIN (psubsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
13440 LOONGSON_BUILTIN (psubush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13441 LOONGSON_BUILTIN (psubusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13442 LOONGSON_BUILTIN_SUFFIX (punpckhbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13443 LOONGSON_BUILTIN_SUFFIX (punpckhhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13444 LOONGSON_BUILTIN_SUFFIX (punpckhwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13445 LOONGSON_BUILTIN_SUFFIX (punpckhbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13446 LOONGSON_BUILTIN_SUFFIX (punpckhhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13447 LOONGSON_BUILTIN_SUFFIX (punpckhwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13448 LOONGSON_BUILTIN_SUFFIX (punpcklbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13449 LOONGSON_BUILTIN_SUFFIX (punpcklhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13450 LOONGSON_BUILTIN_SUFFIX (punpcklwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13451 LOONGSON_BUILTIN_SUFFIX (punpcklbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13452 LOONGSON_BUILTIN_SUFFIX (punpcklhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13453 LOONGSON_BUILTIN_SUFFIX (punpcklwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13455 /* Sundry other built-in functions. */
13456 DIRECT_NO_TARGET_BUILTIN (cache, MIPS_VOID_FTYPE_SI_CVPOINTER, cache)
13459 /* Index I is the function declaration for mips_builtins[I], or null if the
13460 function isn't defined on this target. */
13461 static GTY(()) tree mips_builtin_decls[ARRAY_SIZE (mips_builtins)];
13463 /* MODE is a vector mode whose elements have type TYPE. Return the type
13464 of the vector itself. */
13467 mips_builtin_vector_type (tree type, enum machine_mode mode)
13469 static tree types[2 * (int) MAX_MACHINE_MODE];
13472 mode_index = (int) mode;
13474 if (TREE_CODE (type) == INTEGER_TYPE && TYPE_UNSIGNED (type))
13475 mode_index += MAX_MACHINE_MODE;
13477 if (types[mode_index] == NULL_TREE)
13478 types[mode_index] = build_vector_type_for_mode (type, mode);
13479 return types[mode_index];
13482 /* Return a type for 'const volatile void *'. */
13485 mips_build_cvpointer_type (void)
13489 if (cache == NULL_TREE)
13490 cache = build_pointer_type (build_qualified_type
13492 TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE));
13496 /* Source-level argument types. */
13497 #define MIPS_ATYPE_VOID void_type_node
13498 #define MIPS_ATYPE_INT integer_type_node
13499 #define MIPS_ATYPE_POINTER ptr_type_node
13500 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
13502 /* Standard mode-based argument types. */
13503 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
13504 #define MIPS_ATYPE_SI intSI_type_node
13505 #define MIPS_ATYPE_USI unsigned_intSI_type_node
13506 #define MIPS_ATYPE_DI intDI_type_node
13507 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
13508 #define MIPS_ATYPE_SF float_type_node
13509 #define MIPS_ATYPE_DF double_type_node
13511 /* Vector argument types. */
13512 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
13513 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
13514 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
13515 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
13516 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
13517 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
13518 #define MIPS_ATYPE_UV2SI \
13519 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
13520 #define MIPS_ATYPE_UV4HI \
13521 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
13522 #define MIPS_ATYPE_UV8QI \
13523 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
13525 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
13526 their associated MIPS_ATYPEs. */
13527 #define MIPS_FTYPE_ATYPES1(A, B) \
13528 MIPS_ATYPE_##A, MIPS_ATYPE_##B
13530 #define MIPS_FTYPE_ATYPES2(A, B, C) \
13531 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
13533 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
13534 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
13536 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
13537 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
13540 /* Return the function type associated with function prototype TYPE. */
13543 mips_build_function_type (enum mips_function_type type)
13545 static tree types[(int) MIPS_MAX_FTYPE_MAX];
13547 if (types[(int) type] == NULL_TREE)
13550 #define DEF_MIPS_FTYPE(NUM, ARGS) \
13551 case MIPS_FTYPE_NAME##NUM ARGS: \
13552 types[(int) type] \
13553 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
13556 #include "config/mips/mips-ftypes.def"
13557 #undef DEF_MIPS_FTYPE
13559 gcc_unreachable ();
13562 return types[(int) type];
13565 /* Implement TARGET_INIT_BUILTINS. */
13568 mips_init_builtins (void)
13570 const struct mips_builtin_description *d;
13573 /* Iterate through all of the bdesc arrays, initializing all of the
13574 builtin functions. */
13575 for (i = 0; i < ARRAY_SIZE (mips_builtins); i++)
13577 d = &mips_builtins[i];
13579 mips_builtin_decls[i]
13580 = add_builtin_function (d->name,
13581 mips_build_function_type (d->function_type),
13582 i, BUILT_IN_MD, NULL, NULL);
13586 /* Implement TARGET_BUILTIN_DECL. */
13589 mips_builtin_decl (unsigned int code, bool initialize_p ATTRIBUTE_UNUSED)
13591 if (code >= ARRAY_SIZE (mips_builtins))
13592 return error_mark_node;
13593 return mips_builtin_decls[code];
13596 /* Take argument ARGNO from EXP's argument list and convert it into
13597 an expand operand. Store the operand in *OP. */
13600 mips_prepare_builtin_arg (struct expand_operand *op, tree exp,
13601 unsigned int argno)
13606 arg = CALL_EXPR_ARG (exp, argno);
13607 value = expand_normal (arg);
13608 create_input_operand (op, value, TYPE_MODE (TREE_TYPE (arg)));
13611 /* Expand instruction ICODE as part of a built-in function sequence.
13612 Use the first NOPS elements of OPS as the instruction's operands.
13613 HAS_TARGET_P is true if operand 0 is a target; it is false if the
13614 instruction has no target.
13616 Return the target rtx if HAS_TARGET_P, otherwise return const0_rtx. */
13619 mips_expand_builtin_insn (enum insn_code icode, unsigned int nops,
13620 struct expand_operand *ops, bool has_target_p)
13622 if (!maybe_expand_insn (icode, nops, ops))
13624 error ("invalid argument to built-in function");
13625 return has_target_p ? gen_reg_rtx (ops[0].mode) : const0_rtx;
13627 return has_target_p ? ops[0].value : const0_rtx;
13630 /* Expand a floating-point comparison for built-in function call EXP.
13631 The first NARGS arguments are the values to be compared. ICODE is
13632 the .md pattern that does the comparison and COND is the condition
13633 that is being tested. Return an rtx for the result. */
13636 mips_expand_builtin_compare_1 (enum insn_code icode,
13637 enum mips_fp_condition cond,
13638 tree exp, int nargs)
13640 struct expand_operand ops[MAX_RECOG_OPERANDS];
13643 /* The instruction should have a target operand, an operand for each
13644 argument, and an operand for COND. */
13645 gcc_assert (nargs + 2 == insn_data[(int) icode].n_generator_args);
13648 create_output_operand (&ops[opno++], NULL_RTX,
13649 insn_data[(int) icode].operand[0].mode);
13650 for (argno = 0; argno < nargs; argno++)
13651 mips_prepare_builtin_arg (&ops[opno++], exp, argno);
13652 create_integer_operand (&ops[opno++], (int) cond);
13653 return mips_expand_builtin_insn (icode, opno, ops, true);
13656 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
13657 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
13658 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
13659 suggests a good place to put the result. */
13662 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
13665 struct expand_operand ops[MAX_RECOG_OPERANDS];
13668 /* Map any target to operand 0. */
13671 create_output_operand (&ops[opno++], target, TYPE_MODE (TREE_TYPE (exp)));
13673 /* Map the arguments to the other operands. */
13674 gcc_assert (opno + call_expr_nargs (exp)
13675 == insn_data[icode].n_generator_args);
13676 for (argno = 0; argno < call_expr_nargs (exp); argno++)
13677 mips_prepare_builtin_arg (&ops[opno++], exp, argno);
13679 return mips_expand_builtin_insn (icode, opno, ops, has_target_p);
13682 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
13683 function; TYPE says which. EXP is the CALL_EXPR that calls the
13684 function, ICODE is the instruction that should be used to compare
13685 the first two arguments, and COND is the condition it should test.
13686 TARGET, if nonnull, suggests a good place to put the result. */
13689 mips_expand_builtin_movtf (enum mips_builtin_type type,
13690 enum insn_code icode, enum mips_fp_condition cond,
13691 rtx target, tree exp)
13693 struct expand_operand ops[4];
13696 cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp, 2);
13697 create_output_operand (&ops[0], target, TYPE_MODE (TREE_TYPE (exp)));
13698 if (type == MIPS_BUILTIN_MOVT)
13700 mips_prepare_builtin_arg (&ops[2], exp, 2);
13701 mips_prepare_builtin_arg (&ops[1], exp, 3);
13705 mips_prepare_builtin_arg (&ops[1], exp, 2);
13706 mips_prepare_builtin_arg (&ops[2], exp, 3);
13708 create_fixed_operand (&ops[3], cmp_result);
13709 return mips_expand_builtin_insn (CODE_FOR_mips_cond_move_tf_ps,
13713 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
13714 into TARGET otherwise. Return TARGET. */
13717 mips_builtin_branch_and_move (rtx condition, rtx target,
13718 rtx value_if_true, rtx value_if_false)
13720 rtx true_label, done_label;
13722 true_label = gen_label_rtx ();
13723 done_label = gen_label_rtx ();
13725 /* First assume that CONDITION is false. */
13726 mips_emit_move (target, value_if_false);
13728 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
13729 emit_jump_insn (gen_condjump (condition, true_label));
13730 emit_jump_insn (gen_jump (done_label));
13733 /* Fix TARGET if CONDITION is true. */
13734 emit_label (true_label);
13735 mips_emit_move (target, value_if_true);
13737 emit_label (done_label);
13741 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
13742 the CALL_EXPR that calls the function, ICODE is the code of the
13743 comparison instruction, and COND is the condition it should test.
13744 TARGET, if nonnull, suggests a good place to put the boolean result. */
13747 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
13748 enum insn_code icode, enum mips_fp_condition cond,
13749 rtx target, tree exp)
13751 rtx offset, condition, cmp_result;
13753 if (target == 0 || GET_MODE (target) != SImode)
13754 target = gen_reg_rtx (SImode);
13755 cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp,
13756 call_expr_nargs (exp));
13758 /* If the comparison sets more than one register, we define the result
13759 to be 0 if all registers are false and -1 if all registers are true.
13760 The value of the complete result is indeterminate otherwise. */
13761 switch (builtin_type)
13763 case MIPS_BUILTIN_CMP_ALL:
13764 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
13765 return mips_builtin_branch_and_move (condition, target,
13766 const0_rtx, const1_rtx);
13768 case MIPS_BUILTIN_CMP_UPPER:
13769 case MIPS_BUILTIN_CMP_LOWER:
13770 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
13771 condition = gen_single_cc (cmp_result, offset);
13772 return mips_builtin_branch_and_move (condition, target,
13773 const1_rtx, const0_rtx);
13776 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
13777 return mips_builtin_branch_and_move (condition, target,
13778 const1_rtx, const0_rtx);
13782 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
13783 if nonnull, suggests a good place to put the boolean result. */
13786 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
13788 rtx condition, cmp_result;
13791 if (target == 0 || GET_MODE (target) != SImode)
13792 target = gen_reg_rtx (SImode);
13794 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
13796 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
13801 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
13802 return mips_builtin_branch_and_move (condition, target,
13803 const1_rtx, const0_rtx);
13806 /* Implement TARGET_EXPAND_BUILTIN. */
13809 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
13810 enum machine_mode mode, int ignore)
13813 unsigned int fcode, avail;
13814 const struct mips_builtin_description *d;
13816 fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
13817 fcode = DECL_FUNCTION_CODE (fndecl);
13818 gcc_assert (fcode < ARRAY_SIZE (mips_builtins));
13819 d = &mips_builtins[fcode];
13820 avail = d->avail ();
13821 gcc_assert (avail != 0);
13824 error ("built-in function %qE not supported for MIPS16",
13825 DECL_NAME (fndecl));
13826 return ignore ? const0_rtx : CONST0_RTX (mode);
13828 switch (d->builtin_type)
13830 case MIPS_BUILTIN_DIRECT:
13831 return mips_expand_builtin_direct (d->icode, target, exp, true);
13833 case MIPS_BUILTIN_DIRECT_NO_TARGET:
13834 return mips_expand_builtin_direct (d->icode, target, exp, false);
13836 case MIPS_BUILTIN_MOVT:
13837 case MIPS_BUILTIN_MOVF:
13838 return mips_expand_builtin_movtf (d->builtin_type, d->icode,
13839 d->cond, target, exp);
13841 case MIPS_BUILTIN_CMP_ANY:
13842 case MIPS_BUILTIN_CMP_ALL:
13843 case MIPS_BUILTIN_CMP_UPPER:
13844 case MIPS_BUILTIN_CMP_LOWER:
13845 case MIPS_BUILTIN_CMP_SINGLE:
13846 return mips_expand_builtin_compare (d->builtin_type, d->icode,
13847 d->cond, target, exp);
13849 case MIPS_BUILTIN_BPOSGE32:
13850 return mips_expand_builtin_bposge (d->builtin_type, target);
13852 gcc_unreachable ();
13855 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
13856 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
13857 struct mips16_constant {
13858 struct mips16_constant *next;
13861 enum machine_mode mode;
13864 /* Information about an incomplete MIPS16 constant pool. FIRST is the
13865 first constant, HIGHEST_ADDRESS is the highest address that the first
13866 byte of the pool can have, and INSN_ADDRESS is the current instruction
13868 struct mips16_constant_pool {
13869 struct mips16_constant *first;
13870 int highest_address;
13874 /* Add constant VALUE to POOL and return its label. MODE is the
13875 value's mode (used for CONST_INTs, etc.). */
13878 mips16_add_constant (struct mips16_constant_pool *pool,
13879 rtx value, enum machine_mode mode)
13881 struct mips16_constant **p, *c;
13882 bool first_of_size_p;
13884 /* See whether the constant is already in the pool. If so, return the
13885 existing label, otherwise leave P pointing to the place where the
13886 constant should be added.
13888 Keep the pool sorted in increasing order of mode size so that we can
13889 reduce the number of alignments needed. */
13890 first_of_size_p = true;
13891 for (p = &pool->first; *p != 0; p = &(*p)->next)
13893 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
13894 return (*p)->label;
13895 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
13897 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
13898 first_of_size_p = false;
13901 /* In the worst case, the constant needed by the earliest instruction
13902 will end up at the end of the pool. The entire pool must then be
13903 accessible from that instruction.
13905 When adding the first constant, set the pool's highest address to
13906 the address of the first out-of-range byte. Adjust this address
13907 downwards each time a new constant is added. */
13908 if (pool->first == 0)
13909 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
13910 of the instruction with the lowest two bits clear. The base PC
13911 value for LDPC has the lowest three bits clear. Assume the worst
13912 case here; namely that the PC-relative instruction occupies the
13913 last 2 bytes in an aligned word. */
13914 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
13915 pool->highest_address -= GET_MODE_SIZE (mode);
13916 if (first_of_size_p)
13917 /* Take into account the worst possible padding due to alignment. */
13918 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
13920 /* Create a new entry. */
13921 c = XNEW (struct mips16_constant);
13924 c->label = gen_label_rtx ();
13931 /* Output constant VALUE after instruction INSN and return the last
13932 instruction emitted. MODE is the mode of the constant. */
13935 mips16_emit_constants_1 (enum machine_mode mode, rtx value, rtx insn)
13937 if (SCALAR_INT_MODE_P (mode) || ALL_SCALAR_FIXED_POINT_MODE_P (mode))
13939 rtx size = GEN_INT (GET_MODE_SIZE (mode));
13940 return emit_insn_after (gen_consttable_int (value, size), insn);
13943 if (SCALAR_FLOAT_MODE_P (mode))
13944 return emit_insn_after (gen_consttable_float (value), insn);
13946 if (VECTOR_MODE_P (mode))
13950 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
13951 insn = mips16_emit_constants_1 (GET_MODE_INNER (mode),
13952 CONST_VECTOR_ELT (value, i), insn);
13956 gcc_unreachable ();
13959 /* Dump out the constants in CONSTANTS after INSN. */
13962 mips16_emit_constants (struct mips16_constant *constants, rtx insn)
13964 struct mips16_constant *c, *next;
13968 for (c = constants; c != NULL; c = next)
13970 /* If necessary, increase the alignment of PC. */
13971 if (align < GET_MODE_SIZE (c->mode))
13973 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
13974 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
13976 align = GET_MODE_SIZE (c->mode);
13978 insn = emit_label_after (c->label, insn);
13979 insn = mips16_emit_constants_1 (c->mode, c->value, insn);
13985 emit_barrier_after (insn);
13988 /* Return the length of instruction INSN. */
13991 mips16_insn_length (rtx insn)
13995 rtx body = PATTERN (insn);
13996 if (GET_CODE (body) == ADDR_VEC)
13997 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
13998 if (GET_CODE (body) == ADDR_DIFF_VEC)
13999 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
14001 return get_attr_length (insn);
14004 /* If *X is a symbolic constant that refers to the constant pool, add
14005 the constant to POOL and rewrite *X to use the constant's label. */
14008 mips16_rewrite_pool_constant (struct mips16_constant_pool *pool, rtx *x)
14010 rtx base, offset, label;
14012 split_const (*x, &base, &offset);
14013 if (GET_CODE (base) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (base))
14015 label = mips16_add_constant (pool, get_pool_constant (base),
14016 get_pool_mode (base));
14017 base = gen_rtx_LABEL_REF (Pmode, label);
14018 *x = mips_unspec_address_offset (base, offset, SYMBOL_PC_RELATIVE);
14022 /* This structure is used to communicate with mips16_rewrite_pool_refs.
14023 INSN is the instruction we're rewriting and POOL points to the current
14025 struct mips16_rewrite_pool_refs_info {
14027 struct mips16_constant_pool *pool;
14030 /* Rewrite *X so that constant pool references refer to the constant's
14031 label instead. DATA points to a mips16_rewrite_pool_refs_info
14035 mips16_rewrite_pool_refs (rtx *x, void *data)
14037 struct mips16_rewrite_pool_refs_info *info =
14038 (struct mips16_rewrite_pool_refs_info *) data;
14040 if (force_to_mem_operand (*x, Pmode))
14042 rtx mem = force_const_mem (GET_MODE (*x), *x);
14043 validate_change (info->insn, x, mem, false);
14048 mips16_rewrite_pool_constant (info->pool, &XEXP (*x, 0));
14052 /* Don't rewrite the __mips16_rdwr symbol. */
14053 if (GET_CODE (*x) == UNSPEC && XINT (*x, 1) == UNSPEC_TLS_GET_TP)
14056 if (TARGET_MIPS16_TEXT_LOADS)
14057 mips16_rewrite_pool_constant (info->pool, x);
14059 return GET_CODE (*x) == CONST ? -1 : 0;
14062 /* Return whether CFG is used in mips_reorg. */
14065 mips_cfg_in_reorg (void)
14067 return (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
14068 || TARGET_RELAX_PIC_CALLS);
14071 /* Build MIPS16 constant pools. */
14074 mips16_lay_out_constants (void)
14076 struct mips16_constant_pool pool;
14077 struct mips16_rewrite_pool_refs_info info;
14080 if (!TARGET_MIPS16_PCREL_LOADS)
14083 if (mips_cfg_in_reorg ())
14084 split_all_insns ();
14086 split_all_insns_noflow ();
14088 memset (&pool, 0, sizeof (pool));
14089 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
14091 /* Rewrite constant pool references in INSN. */
14092 if (USEFUL_INSN_P (insn))
14096 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &info);
14099 pool.insn_address += mips16_insn_length (insn);
14101 if (pool.first != NULL)
14103 /* If there are no natural barriers between the first user of
14104 the pool and the highest acceptable address, we'll need to
14105 create a new instruction to jump around the constant pool.
14106 In the worst case, this instruction will be 4 bytes long.
14108 If it's too late to do this transformation after INSN,
14109 do it immediately before INSN. */
14110 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
14114 label = gen_label_rtx ();
14116 jump = emit_jump_insn_before (gen_jump (label), insn);
14117 JUMP_LABEL (jump) = label;
14118 LABEL_NUSES (label) = 1;
14119 barrier = emit_barrier_after (jump);
14121 emit_label_after (label, barrier);
14122 pool.insn_address += 4;
14125 /* See whether the constant pool is now out of range of the first
14126 user. If so, output the constants after the previous barrier.
14127 Note that any instructions between BARRIER and INSN (inclusive)
14128 will use negative offsets to refer to the pool. */
14129 if (pool.insn_address > pool.highest_address)
14131 mips16_emit_constants (pool.first, barrier);
14135 else if (BARRIER_P (insn))
14139 mips16_emit_constants (pool.first, get_last_insn ());
14142 /* Return true if it is worth r10k_simplify_address's while replacing
14143 an address with X. We are looking for constants, and for addresses
14144 at a known offset from the incoming stack pointer. */
14147 r10k_simplified_address_p (rtx x)
14149 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
14151 return x == virtual_incoming_args_rtx || CONSTANT_P (x);
14154 /* X is an expression that appears in INSN. Try to use the UD chains
14155 to simplify it, returning the simplified form on success and the
14156 original form otherwise. Replace the incoming value of $sp with
14157 virtual_incoming_args_rtx (which should never occur in X otherwise). */
14160 r10k_simplify_address (rtx x, rtx insn)
14162 rtx newx, op0, op1, set, def_insn, note;
14164 struct df_link *defs;
14169 op0 = r10k_simplify_address (XEXP (x, 0), insn);
14170 if (op0 != XEXP (x, 0))
14171 newx = simplify_gen_unary (GET_CODE (x), GET_MODE (x),
14172 op0, GET_MODE (XEXP (x, 0)));
14174 else if (BINARY_P (x))
14176 op0 = r10k_simplify_address (XEXP (x, 0), insn);
14177 op1 = r10k_simplify_address (XEXP (x, 1), insn);
14178 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
14179 newx = simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
14181 else if (GET_CODE (x) == LO_SUM)
14183 /* LO_SUMs can be offset from HIGHs, if we know they won't
14184 overflow. See mips_classify_address for the rationale behind
14186 op0 = r10k_simplify_address (XEXP (x, 0), insn);
14187 if (GET_CODE (op0) == HIGH)
14188 newx = XEXP (x, 1);
14190 else if (REG_P (x))
14192 /* Uses are recorded by regno_reg_rtx, not X itself. */
14193 use = df_find_use (insn, regno_reg_rtx[REGNO (x)]);
14195 defs = DF_REF_CHAIN (use);
14197 /* Require a single definition. */
14198 if (defs && defs->next == NULL)
14201 if (DF_REF_IS_ARTIFICIAL (def))
14203 /* Replace the incoming value of $sp with
14204 virtual_incoming_args_rtx. */
14205 if (x == stack_pointer_rtx
14206 && DF_REF_BB (def) == ENTRY_BLOCK_PTR)
14207 newx = virtual_incoming_args_rtx;
14209 else if (dominated_by_p (CDI_DOMINATORS, DF_REF_BB (use),
14212 /* Make sure that DEF_INSN is a single set of REG. */
14213 def_insn = DF_REF_INSN (def);
14214 if (NONJUMP_INSN_P (def_insn))
14216 set = single_set (def_insn);
14217 if (set && rtx_equal_p (SET_DEST (set), x))
14219 /* Prefer to use notes, since the def-use chains
14220 are often shorter. */
14221 note = find_reg_equal_equiv_note (def_insn);
14223 newx = XEXP (note, 0);
14225 newx = SET_SRC (set);
14226 newx = r10k_simplify_address (newx, def_insn);
14232 if (newx && r10k_simplified_address_p (newx))
14237 /* Return true if ADDRESS is known to be an uncached address
14238 on R10K systems. */
14241 r10k_uncached_address_p (unsigned HOST_WIDE_INT address)
14243 unsigned HOST_WIDE_INT upper;
14245 /* Check for KSEG1. */
14246 if (address + 0x60000000 < 0x20000000)
14249 /* Check for uncached XKPHYS addresses. */
14250 if (Pmode == DImode)
14252 upper = (address >> 40) & 0xf9ffff;
14253 if (upper == 0x900000 || upper == 0xb80000)
14259 /* Return true if we can prove that an access to address X in instruction
14260 INSN would be safe from R10K speculation. This X is a general
14261 expression; it might not be a legitimate address. */
14264 r10k_safe_address_p (rtx x, rtx insn)
14267 HOST_WIDE_INT offset_val;
14269 x = r10k_simplify_address (x, insn);
14271 /* Check for references to the stack frame. It doesn't really matter
14272 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
14273 allows us to assume that accesses to any part of the eventual frame
14274 is safe from speculation at any point in the function. */
14275 mips_split_plus (x, &base, &offset_val);
14276 if (base == virtual_incoming_args_rtx
14277 && offset_val >= -cfun->machine->frame.total_size
14278 && offset_val < cfun->machine->frame.args_size)
14281 /* Check for uncached addresses. */
14282 if (CONST_INT_P (x))
14283 return r10k_uncached_address_p (INTVAL (x));
14285 /* Check for accesses to a static object. */
14286 split_const (x, &base, &offset);
14287 return offset_within_block_p (base, INTVAL (offset));
14290 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
14291 an in-range access to an automatic variable, or to an object with
14292 a link-time-constant address. */
14295 r10k_safe_mem_expr_p (tree expr, HOST_WIDE_INT offset)
14297 if (offset < 0 || offset >= int_size_in_bytes (TREE_TYPE (expr)))
14300 while (TREE_CODE (expr) == COMPONENT_REF)
14302 expr = TREE_OPERAND (expr, 0);
14303 if (expr == NULL_TREE)
14307 return DECL_P (expr);
14310 /* A for_each_rtx callback for which DATA points to the instruction
14311 containing *X. Stop the search if we find a MEM that is not safe
14312 from R10K speculation. */
14315 r10k_needs_protection_p_1 (rtx *loc, void *data)
14324 && MEM_OFFSET_KNOWN_P (mem)
14325 && r10k_safe_mem_expr_p (MEM_EXPR (mem), MEM_OFFSET (mem)))
14328 if (r10k_safe_address_p (XEXP (mem, 0), (rtx) data))
14334 /* A note_stores callback for which DATA points to an instruction pointer.
14335 If *DATA is nonnull, make it null if it X contains a MEM that is not
14336 safe from R10K speculation. */
14339 r10k_needs_protection_p_store (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
14344 insn_ptr = (rtx *) data;
14345 if (*insn_ptr && for_each_rtx (&x, r10k_needs_protection_p_1, *insn_ptr))
14346 *insn_ptr = NULL_RTX;
14349 /* A for_each_rtx callback that iterates over the pattern of a CALL_INSN.
14350 Return nonzero if the call is not to a declared function. */
14353 r10k_needs_protection_p_call (rtx *loc, void *data ATTRIBUTE_UNUSED)
14362 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DECL (x))
14368 /* Return true if instruction INSN needs to be protected by an R10K
14372 r10k_needs_protection_p (rtx insn)
14375 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_call, NULL);
14377 if (mips_r10k_cache_barrier == R10K_CACHE_BARRIER_STORE)
14379 note_stores (PATTERN (insn), r10k_needs_protection_p_store, &insn);
14380 return insn == NULL_RTX;
14383 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_1, insn);
14386 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
14387 edge is unconditional. */
14390 r10k_protected_bb_p (basic_block bb, sbitmap protected_bbs)
14395 FOR_EACH_EDGE (e, ei, bb->preds)
14396 if (!single_succ_p (e->src)
14397 || !TEST_BIT (protected_bbs, e->src->index)
14398 || (e->flags & EDGE_COMPLEX) != 0)
14403 /* Implement -mr10k-cache-barrier= for the current function. */
14406 r10k_insert_cache_barriers (void)
14408 int *rev_post_order;
14411 sbitmap protected_bbs;
14412 rtx insn, end, unprotected_region;
14416 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
14420 /* Calculate dominators. */
14421 calculate_dominance_info (CDI_DOMINATORS);
14423 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
14424 X is protected by a cache barrier. */
14425 protected_bbs = sbitmap_alloc (last_basic_block);
14426 sbitmap_zero (protected_bbs);
14428 /* Iterate over the basic blocks in reverse post-order. */
14429 rev_post_order = XNEWVEC (int, last_basic_block);
14430 n = pre_and_rev_post_order_compute (NULL, rev_post_order, false);
14431 for (i = 0; i < n; i++)
14433 bb = BASIC_BLOCK (rev_post_order[i]);
14435 /* If this block is only reached by unconditional edges, and if the
14436 source of every edge is protected, the beginning of the block is
14438 if (r10k_protected_bb_p (bb, protected_bbs))
14439 unprotected_region = NULL_RTX;
14441 unprotected_region = pc_rtx;
14442 end = NEXT_INSN (BB_END (bb));
14444 /* UNPROTECTED_REGION is:
14446 - null if we are processing a protected region,
14447 - pc_rtx if we are processing an unprotected region but have
14448 not yet found the first instruction in it
14449 - the first instruction in an unprotected region otherwise. */
14450 for (insn = BB_HEAD (bb); insn != end; insn = NEXT_INSN (insn))
14452 if (unprotected_region && USEFUL_INSN_P (insn))
14454 if (recog_memoized (insn) == CODE_FOR_mips_cache)
14455 /* This CACHE instruction protects the following code. */
14456 unprotected_region = NULL_RTX;
14459 /* See if INSN is the first instruction in this
14460 unprotected region. */
14461 if (unprotected_region == pc_rtx)
14462 unprotected_region = insn;
14464 /* See if INSN needs to be protected. If so,
14465 we must insert a cache barrier somewhere between
14466 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
14467 clear which position is better performance-wise,
14468 but as a tie-breaker, we assume that it is better
14469 to allow delay slots to be back-filled where
14470 possible, and that it is better not to insert
14471 barriers in the middle of already-scheduled code.
14472 We therefore insert the barrier at the beginning
14474 if (r10k_needs_protection_p (insn))
14476 emit_insn_before (gen_r10k_cache_barrier (),
14477 unprotected_region);
14478 unprotected_region = NULL_RTX;
14484 /* The called function is not required to protect the exit path.
14485 The code that follows a call is therefore unprotected. */
14486 unprotected_region = pc_rtx;
14489 /* Record whether the end of this block is protected. */
14490 if (unprotected_region == NULL_RTX)
14491 SET_BIT (protected_bbs, bb->index);
14493 XDELETEVEC (rev_post_order);
14495 sbitmap_free (protected_bbs);
14497 free_dominance_info (CDI_DOMINATORS);
14500 /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX
14501 otherwise. If INSN has two call rtx, then store the second one in
14505 mips_call_expr_from_insn (rtx insn, rtx *second_call)
14510 if (!CALL_P (insn))
14513 x = PATTERN (insn);
14514 if (GET_CODE (x) == PARALLEL)
14516 /* Calls returning complex values have two CALL rtx. Look for the second
14517 one here, and return it via the SECOND_CALL arg. */
14518 x2 = XVECEXP (x, 0, 1);
14519 if (GET_CODE (x2) == SET)
14521 if (GET_CODE (x2) == CALL)
14524 x = XVECEXP (x, 0, 0);
14526 if (GET_CODE (x) == SET)
14528 gcc_assert (GET_CODE (x) == CALL);
14533 /* REG is set in DEF. See if the definition is one of the ways we load a
14534 register with a symbol address for a mips_use_pic_fn_addr_reg_p call.
14535 If it is, return the symbol reference of the function, otherwise return
14538 If RECURSE_P is true, use mips_find_pic_call_symbol to interpret
14539 the values of source registers, otherwise treat such registers as
14540 having an unknown value. */
14543 mips_pic_call_symbol_from_set (df_ref def, rtx reg, bool recurse_p)
14547 if (DF_REF_IS_ARTIFICIAL (def))
14550 def_insn = DF_REF_INSN (def);
14551 set = single_set (def_insn);
14552 if (set && rtx_equal_p (SET_DEST (set), reg))
14554 rtx note, src, symbol;
14556 /* First, look at REG_EQUAL/EQUIV notes. */
14557 note = find_reg_equal_equiv_note (def_insn);
14558 if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF)
14559 return XEXP (note, 0);
14561 /* For %call16 references we don't have REG_EQUAL. */
14562 src = SET_SRC (set);
14563 symbol = mips_strip_unspec_call (src);
14566 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
14570 /* Follow at most one simple register copy. Such copies are
14571 interesting in cases like:
14575 locally_binding_fn (...);
14580 locally_binding_fn (...);
14582 locally_binding_fn (...);
14584 where the load of locally_binding_fn can legitimately be
14585 hoisted or shared. However, we do not expect to see complex
14586 chains of copies, so a full worklist solution to the problem
14587 would probably be overkill. */
14588 if (recurse_p && REG_P (src))
14589 return mips_find_pic_call_symbol (def_insn, src, false);
14595 /* Find the definition of the use of REG in INSN. See if the definition
14596 is one of the ways we load a register with a symbol address for a
14597 mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference
14598 of the function, otherwise return NULL_RTX. RECURSE_P is as for
14599 mips_pic_call_symbol_from_set. */
14602 mips_find_pic_call_symbol (rtx insn, rtx reg, bool recurse_p)
14605 struct df_link *defs;
14608 use = df_find_use (insn, regno_reg_rtx[REGNO (reg)]);
14611 defs = DF_REF_CHAIN (use);
14614 symbol = mips_pic_call_symbol_from_set (defs->ref, reg, recurse_p);
14618 /* If we have more than one definition, they need to be identical. */
14619 for (defs = defs->next; defs; defs = defs->next)
14623 other = mips_pic_call_symbol_from_set (defs->ref, reg, recurse_p);
14624 if (!rtx_equal_p (symbol, other))
14631 /* Replace the args_size operand of the call expression CALL with the
14632 call-attribute UNSPEC and fill in SYMBOL as the function symbol. */
14635 mips_annotate_pic_call_expr (rtx call, rtx symbol)
14639 args_size = XEXP (call, 1);
14640 XEXP (call, 1) = gen_rtx_UNSPEC (GET_MODE (args_size),
14641 gen_rtvec (2, args_size, symbol),
14645 /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See
14646 if instead of the arg_size argument it contains the call attributes. If
14647 yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function
14648 symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is
14652 mips_get_pic_call_symbol (rtx *operands, int args_size_opno)
14654 rtx args_size, symbol;
14656 if (!TARGET_RELAX_PIC_CALLS || args_size_opno == -1)
14659 args_size = operands[args_size_opno];
14660 if (GET_CODE (args_size) != UNSPEC)
14662 gcc_assert (XINT (args_size, 1) == UNSPEC_CALL_ATTR);
14664 symbol = XVECEXP (args_size, 0, 1);
14665 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
14667 operands[args_size_opno] = symbol;
14671 /* Use DF to annotate PIC indirect calls with the function symbol they
14675 mips_annotate_pic_calls (void)
14681 FOR_BB_INSNS (bb, insn)
14683 rtx call, reg, symbol, second_call;
14686 call = mips_call_expr_from_insn (insn, &second_call);
14689 gcc_assert (MEM_P (XEXP (call, 0)));
14690 reg = XEXP (XEXP (call, 0), 0);
14694 symbol = mips_find_pic_call_symbol (insn, reg, true);
14697 mips_annotate_pic_call_expr (call, symbol);
14699 mips_annotate_pic_call_expr (second_call, symbol);
14704 /* A temporary variable used by for_each_rtx callbacks, etc. */
14705 static rtx mips_sim_insn;
14707 /* A structure representing the state of the processor pipeline.
14708 Used by the mips_sim_* family of functions. */
14710 /* The maximum number of instructions that can be issued in a cycle.
14711 (Caches mips_issue_rate.) */
14712 unsigned int issue_rate;
14714 /* The current simulation time. */
14717 /* How many more instructions can be issued in the current cycle. */
14718 unsigned int insns_left;
14720 /* LAST_SET[X].INSN is the last instruction to set register X.
14721 LAST_SET[X].TIME is the time at which that instruction was issued.
14722 INSN is null if no instruction has yet set register X. */
14726 } last_set[FIRST_PSEUDO_REGISTER];
14728 /* The pipeline's current DFA state. */
14732 /* Reset STATE to the initial simulation state. */
14735 mips_sim_reset (struct mips_sim *state)
14738 state->insns_left = state->issue_rate;
14739 memset (&state->last_set, 0, sizeof (state->last_set));
14740 state_reset (state->dfa_state);
14743 /* Initialize STATE before its first use. DFA_STATE points to an
14744 allocated but uninitialized DFA state. */
14747 mips_sim_init (struct mips_sim *state, state_t dfa_state)
14749 state->issue_rate = mips_issue_rate ();
14750 state->dfa_state = dfa_state;
14751 mips_sim_reset (state);
14754 /* Advance STATE by one clock cycle. */
14757 mips_sim_next_cycle (struct mips_sim *state)
14760 state->insns_left = state->issue_rate;
14761 state_transition (state->dfa_state, 0);
14764 /* Advance simulation state STATE until instruction INSN can read
14768 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
14770 unsigned int regno, end_regno;
14772 end_regno = END_REGNO (reg);
14773 for (regno = REGNO (reg); regno < end_regno; regno++)
14774 if (state->last_set[regno].insn != 0)
14778 t = (state->last_set[regno].time
14779 + insn_latency (state->last_set[regno].insn, insn));
14780 while (state->time < t)
14781 mips_sim_next_cycle (state);
14785 /* A for_each_rtx callback. If *X is a register, advance simulation state
14786 DATA until mips_sim_insn can read the register's value. */
14789 mips_sim_wait_regs_2 (rtx *x, void *data)
14792 mips_sim_wait_reg ((struct mips_sim *) data, mips_sim_insn, *x);
14796 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
14799 mips_sim_wait_regs_1 (rtx *x, void *data)
14801 for_each_rtx (x, mips_sim_wait_regs_2, data);
14804 /* Advance simulation state STATE until all of INSN's register
14805 dependencies are satisfied. */
14808 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
14810 mips_sim_insn = insn;
14811 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
14814 /* Advance simulation state STATE until the units required by
14815 instruction INSN are available. */
14818 mips_sim_wait_units (struct mips_sim *state, rtx insn)
14822 tmp_state = alloca (state_size ());
14823 while (state->insns_left == 0
14824 || (memcpy (tmp_state, state->dfa_state, state_size ()),
14825 state_transition (tmp_state, insn) >= 0))
14826 mips_sim_next_cycle (state);
14829 /* Advance simulation state STATE until INSN is ready to issue. */
14832 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
14834 mips_sim_wait_regs (state, insn);
14835 mips_sim_wait_units (state, insn);
14838 /* mips_sim_insn has just set X. Update the LAST_SET array
14839 in simulation state DATA. */
14842 mips_sim_record_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
14844 struct mips_sim *state;
14846 state = (struct mips_sim *) data;
14849 unsigned int regno, end_regno;
14851 end_regno = END_REGNO (x);
14852 for (regno = REGNO (x); regno < end_regno; regno++)
14854 state->last_set[regno].insn = mips_sim_insn;
14855 state->last_set[regno].time = state->time;
14860 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
14861 can issue immediately (i.e., that mips_sim_wait_insn has already
14865 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
14867 state_transition (state->dfa_state, insn);
14868 state->insns_left--;
14870 mips_sim_insn = insn;
14871 note_stores (PATTERN (insn), mips_sim_record_set, state);
14874 /* Simulate issuing a NOP in state STATE. */
14877 mips_sim_issue_nop (struct mips_sim *state)
14879 if (state->insns_left == 0)
14880 mips_sim_next_cycle (state);
14881 state->insns_left--;
14884 /* Update simulation state STATE so that it's ready to accept the instruction
14885 after INSN. INSN should be part of the main rtl chain, not a member of a
14889 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
14891 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
14893 mips_sim_issue_nop (state);
14895 switch (GET_CODE (SEQ_BEGIN (insn)))
14899 /* We can't predict the processor state after a call or label. */
14900 mips_sim_reset (state);
14904 /* The delay slots of branch likely instructions are only executed
14905 when the branch is taken. Therefore, if the caller has simulated
14906 the delay slot instruction, STATE does not really reflect the state
14907 of the pipeline for the instruction after the delay slot. Also,
14908 branch likely instructions tend to incur a penalty when not taken,
14909 so there will probably be an extra delay between the branch and
14910 the instruction after the delay slot. */
14911 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
14912 mips_sim_reset (state);
14920 /* The VR4130 pipeline issues aligned pairs of instructions together,
14921 but it stalls the second instruction if it depends on the first.
14922 In order to cut down the amount of logic required, this dependence
14923 check is not based on a full instruction decode. Instead, any non-SPECIAL
14924 instruction is assumed to modify the register specified by bits 20-16
14925 (which is usually the "rt" field).
14927 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
14928 input, so we can end up with a false dependence between the branch
14929 and its delay slot. If this situation occurs in instruction INSN,
14930 try to avoid it by swapping rs and rt. */
14933 vr4130_avoid_branch_rt_conflict (rtx insn)
14937 first = SEQ_BEGIN (insn);
14938 second = SEQ_END (insn);
14940 && NONJUMP_INSN_P (second)
14941 && GET_CODE (PATTERN (first)) == SET
14942 && GET_CODE (SET_DEST (PATTERN (first))) == PC
14943 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
14945 /* Check for the right kind of condition. */
14946 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
14947 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
14948 && REG_P (XEXP (cond, 0))
14949 && REG_P (XEXP (cond, 1))
14950 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
14951 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
14953 /* SECOND mentions the rt register but not the rs register. */
14954 rtx tmp = XEXP (cond, 0);
14955 XEXP (cond, 0) = XEXP (cond, 1);
14956 XEXP (cond, 1) = tmp;
14961 /* Implement -mvr4130-align. Go through each basic block and simulate the
14962 processor pipeline. If we find that a pair of instructions could execute
14963 in parallel, and the first of those instructions is not 8-byte aligned,
14964 insert a nop to make it aligned. */
14967 vr4130_align_insns (void)
14969 struct mips_sim state;
14970 rtx insn, subinsn, last, last2, next;
14975 /* LAST is the last instruction before INSN to have a nonzero length.
14976 LAST2 is the last such instruction before LAST. */
14980 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
14983 mips_sim_init (&state, alloca (state_size ()));
14984 for (insn = get_insns (); insn != 0; insn = next)
14986 unsigned int length;
14988 next = NEXT_INSN (insn);
14990 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
14991 This isn't really related to the alignment pass, but we do it on
14992 the fly to avoid a separate instruction walk. */
14993 vr4130_avoid_branch_rt_conflict (insn);
14995 if (USEFUL_INSN_P (insn))
14996 FOR_EACH_SUBINSN (subinsn, insn)
14998 mips_sim_wait_insn (&state, subinsn);
15000 /* If we want this instruction to issue in parallel with the
15001 previous one, make sure that the previous instruction is
15002 aligned. There are several reasons why this isn't worthwhile
15003 when the second instruction is a call:
15005 - Calls are less likely to be performance critical,
15006 - There's a good chance that the delay slot can execute
15007 in parallel with the call.
15008 - The return address would then be unaligned.
15010 In general, if we're going to insert a nop between instructions
15011 X and Y, it's better to insert it immediately after X. That
15012 way, if the nop makes Y aligned, it will also align any labels
15013 between X and Y. */
15014 if (state.insns_left != state.issue_rate
15015 && !CALL_P (subinsn))
15017 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
15019 /* SUBINSN is the first instruction in INSN and INSN is
15020 aligned. We want to align the previous instruction
15021 instead, so insert a nop between LAST2 and LAST.
15023 Note that LAST could be either a single instruction
15024 or a branch with a delay slot. In the latter case,
15025 LAST, like INSN, is already aligned, but the delay
15026 slot must have some extra delay that stops it from
15027 issuing at the same time as the branch. We therefore
15028 insert a nop before the branch in order to align its
15030 emit_insn_after (gen_nop (), last2);
15033 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
15035 /* SUBINSN is the delay slot of INSN, but INSN is
15036 currently unaligned. Insert a nop between
15037 LAST and INSN to align it. */
15038 emit_insn_after (gen_nop (), last);
15042 mips_sim_issue_insn (&state, subinsn);
15044 mips_sim_finish_insn (&state, insn);
15046 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
15047 length = get_attr_length (insn);
15050 /* If the instruction is an asm statement or multi-instruction
15051 mips.md patern, the length is only an estimate. Insert an
15052 8 byte alignment after it so that the following instructions
15053 can be handled correctly. */
15054 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
15055 && (recog_memoized (insn) < 0 || length >= 8))
15057 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
15058 next = NEXT_INSN (next);
15059 mips_sim_next_cycle (&state);
15062 else if (length & 4)
15063 aligned_p = !aligned_p;
15068 /* See whether INSN is an aligned label. */
15069 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
15075 /* This structure records that the current function has a LO_SUM
15076 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
15077 the largest offset applied to BASE by all such LO_SUMs. */
15078 struct mips_lo_sum_offset {
15080 HOST_WIDE_INT offset;
15083 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
15086 mips_hash_base (rtx base)
15088 int do_not_record_p;
15090 return hash_rtx (base, GET_MODE (base), &do_not_record_p, NULL, false);
15093 /* Hash-table callbacks for mips_lo_sum_offsets. */
15096 mips_lo_sum_offset_hash (const void *entry)
15098 return mips_hash_base (((const struct mips_lo_sum_offset *) entry)->base);
15102 mips_lo_sum_offset_eq (const void *entry, const void *value)
15104 return rtx_equal_p (((const struct mips_lo_sum_offset *) entry)->base,
15105 (const_rtx) value);
15108 /* Look up symbolic constant X in HTAB, which is a hash table of
15109 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
15110 paired with a recorded LO_SUM, otherwise record X in the table. */
15113 mips_lo_sum_offset_lookup (htab_t htab, rtx x, enum insert_option option)
15117 struct mips_lo_sum_offset *entry;
15119 /* Split X into a base and offset. */
15120 split_const (x, &base, &offset);
15121 if (UNSPEC_ADDRESS_P (base))
15122 base = UNSPEC_ADDRESS (base);
15124 /* Look up the base in the hash table. */
15125 slot = htab_find_slot_with_hash (htab, base, mips_hash_base (base), option);
15129 entry = (struct mips_lo_sum_offset *) *slot;
15130 if (option == INSERT)
15134 entry = XNEW (struct mips_lo_sum_offset);
15135 entry->base = base;
15136 entry->offset = INTVAL (offset);
15141 if (INTVAL (offset) > entry->offset)
15142 entry->offset = INTVAL (offset);
15145 return INTVAL (offset) <= entry->offset;
15148 /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table.
15149 Record every LO_SUM in *LOC. */
15152 mips_record_lo_sum (rtx *loc, void *data)
15154 if (GET_CODE (*loc) == LO_SUM)
15155 mips_lo_sum_offset_lookup ((htab_t) data, XEXP (*loc, 1), INSERT);
15159 /* Return true if INSN is a SET of an orphaned high-part relocation.
15160 HTAB is a hash table of mips_lo_sum_offsets that describes all the
15161 LO_SUMs in the current function. */
15164 mips_orphaned_high_part_p (htab_t htab, rtx insn)
15166 enum mips_symbol_type type;
15169 set = single_set (insn);
15172 /* Check for %his. */
15174 if (GET_CODE (x) == HIGH
15175 && absolute_symbolic_operand (XEXP (x, 0), VOIDmode))
15176 return !mips_lo_sum_offset_lookup (htab, XEXP (x, 0), NO_INSERT);
15178 /* Check for local %gots (and %got_pages, which is redundant but OK). */
15179 if (GET_CODE (x) == UNSPEC
15180 && XINT (x, 1) == UNSPEC_LOAD_GOT
15181 && mips_symbolic_constant_p (XVECEXP (x, 0, 1),
15182 SYMBOL_CONTEXT_LEA, &type)
15183 && type == SYMBOL_GOTOFF_PAGE)
15184 return !mips_lo_sum_offset_lookup (htab, XVECEXP (x, 0, 1), NO_INSERT);
15189 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
15190 INSN and a previous instruction, avoid it by inserting nops after
15193 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
15194 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
15195 before using the value of that register. *HILO_DELAY counts the
15196 number of instructions since the last hilo hazard (that is,
15197 the number of instructions since the last MFLO or MFHI).
15199 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
15200 for the next instruction.
15202 LO_REG is an rtx for the LO register, used in dependence checking. */
15205 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
15206 rtx *delayed_reg, rtx lo_reg)
15211 pattern = PATTERN (insn);
15213 /* Do not put the whole function in .set noreorder if it contains
15214 an asm statement. We don't know whether there will be hazards
15215 between the asm statement and the gcc-generated code. */
15216 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
15217 cfun->machine->all_noreorder_p = false;
15219 /* Ignore zero-length instructions (barriers and the like). */
15220 ninsns = get_attr_length (insn) / 4;
15224 /* Work out how many nops are needed. Note that we only care about
15225 registers that are explicitly mentioned in the instruction's pattern.
15226 It doesn't matter that calls use the argument registers or that they
15227 clobber hi and lo. */
15228 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
15229 nops = 2 - *hilo_delay;
15230 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
15235 /* Insert the nops between this instruction and the previous one.
15236 Each new nop takes us further from the last hilo hazard. */
15237 *hilo_delay += nops;
15239 emit_insn_after (gen_hazard_nop (), after);
15241 /* Set up the state for the next instruction. */
15242 *hilo_delay += ninsns;
15244 if (INSN_CODE (insn) >= 0)
15245 switch (get_attr_hazard (insn))
15255 set = single_set (insn);
15257 *delayed_reg = SET_DEST (set);
15262 /* Go through the instruction stream and insert nops where necessary.
15263 Also delete any high-part relocations whose partnering low parts
15264 are now all dead. See if the whole function can then be put into
15265 .set noreorder and .set nomacro. */
15268 mips_reorg_process_insns (void)
15270 rtx insn, last_insn, subinsn, next_insn, lo_reg, delayed_reg;
15274 /* Force all instructions to be split into their final form. */
15275 split_all_insns_noflow ();
15277 /* Recalculate instruction lengths without taking nops into account. */
15278 cfun->machine->ignore_hazard_length_p = true;
15279 shorten_branches (get_insns ());
15281 cfun->machine->all_noreorder_p = true;
15283 /* We don't track MIPS16 PC-relative offsets closely enough to make
15284 a good job of "set .noreorder" code in MIPS16 mode. */
15286 cfun->machine->all_noreorder_p = false;
15288 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
15289 if (!TARGET_EXPLICIT_RELOCS)
15290 cfun->machine->all_noreorder_p = false;
15292 /* Profiled functions can't be all noreorder because the profiler
15293 support uses assembler macros. */
15295 cfun->machine->all_noreorder_p = false;
15297 /* Code compiled with -mfix-vr4120 or -mfix-24k can't be all noreorder
15298 because we rely on the assembler to work around some errata. */
15299 if (TARGET_FIX_VR4120 || TARGET_FIX_24K)
15300 cfun->machine->all_noreorder_p = false;
15302 /* The same is true for -mfix-vr4130 if we might generate MFLO or
15303 MFHI instructions. Note that we avoid using MFLO and MFHI if
15304 the VR4130 MACC and DMACC instructions are available instead;
15305 see the *mfhilo_{si,di}_macc patterns. */
15306 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
15307 cfun->machine->all_noreorder_p = false;
15309 htab = htab_create (37, mips_lo_sum_offset_hash,
15310 mips_lo_sum_offset_eq, free);
15312 /* Make a first pass over the instructions, recording all the LO_SUMs. */
15313 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
15314 FOR_EACH_SUBINSN (subinsn, insn)
15315 if (USEFUL_INSN_P (subinsn))
15316 for_each_rtx (&PATTERN (subinsn), mips_record_lo_sum, htab);
15321 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
15323 /* Make a second pass over the instructions. Delete orphaned
15324 high-part relocations or turn them into NOPs. Avoid hazards
15325 by inserting NOPs. */
15326 for (insn = get_insns (); insn != 0; insn = next_insn)
15328 next_insn = NEXT_INSN (insn);
15329 if (USEFUL_INSN_P (insn))
15331 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
15333 /* If we find an orphaned high-part relocation in a delay
15334 slot, it's easier to turn that instruction into a NOP than
15335 to delete it. The delay slot will be a NOP either way. */
15336 FOR_EACH_SUBINSN (subinsn, insn)
15337 if (INSN_P (subinsn))
15339 if (mips_orphaned_high_part_p (htab, subinsn))
15341 PATTERN (subinsn) = gen_nop ();
15342 INSN_CODE (subinsn) = CODE_FOR_nop;
15344 mips_avoid_hazard (last_insn, subinsn, &hilo_delay,
15345 &delayed_reg, lo_reg);
15351 /* INSN is a single instruction. Delete it if it's an
15352 orphaned high-part relocation. */
15353 if (mips_orphaned_high_part_p (htab, insn))
15354 delete_insn (insn);
15355 /* Also delete cache barriers if the last instruction
15356 was an annulled branch. INSN will not be speculatively
15358 else if (recog_memoized (insn) == CODE_FOR_r10k_cache_barrier
15360 && JUMP_P (SEQ_BEGIN (last_insn))
15361 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn)))
15362 delete_insn (insn);
15365 mips_avoid_hazard (last_insn, insn, &hilo_delay,
15366 &delayed_reg, lo_reg);
15373 htab_delete (htab);
15376 /* If we are using a GOT, but have not decided to use a global pointer yet,
15377 see whether we need one to implement long branches. Convert the ghost
15378 global-pointer instructions into real ones if so. */
15381 mips_expand_ghost_gp_insns (void)
15386 /* Quick exit if we already know that we will or won't need a
15388 if (!TARGET_USE_GOT
15389 || cfun->machine->global_pointer == INVALID_REGNUM
15390 || mips_must_initialize_gp_p ())
15393 shorten_branches (get_insns ());
15395 /* Look for a branch that is longer than normal. The normal length for
15396 non-MIPS16 branches is 8, because the length includes the delay slot.
15397 It is 4 for MIPS16, because MIPS16 branches are extended instructions,
15398 but they have no delay slot. */
15399 normal_length = (TARGET_MIPS16 ? 4 : 8);
15400 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
15402 && USEFUL_INSN_P (insn)
15403 && get_attr_length (insn) > normal_length)
15406 if (insn == NULL_RTX)
15409 /* We've now established that we need $gp. */
15410 cfun->machine->must_initialize_gp_p = true;
15411 split_all_insns_noflow ();
15416 /* Subroutine of mips_reorg to manage passes that require DF. */
15419 mips_df_reorg (void)
15421 /* Create def-use chains. */
15422 df_set_flags (DF_EQ_NOTES);
15423 df_chain_add_problem (DF_UD_CHAIN);
15426 if (TARGET_RELAX_PIC_CALLS)
15427 mips_annotate_pic_calls ();
15429 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE)
15430 r10k_insert_cache_barriers ();
15432 df_finish_pass (false);
15435 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
15440 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during
15441 insn splitting in mips16_lay_out_constants, DF insn info is only kept up
15442 to date if the CFG is available. */
15443 if (mips_cfg_in_reorg ())
15444 compute_bb_for_insn ();
15445 mips16_lay_out_constants ();
15446 if (mips_cfg_in_reorg ())
15449 free_bb_for_insn ();
15452 if (optimize > 0 && flag_delayed_branch)
15453 dbr_schedule (get_insns ());
15454 mips_reorg_process_insns ();
15456 && TARGET_EXPLICIT_RELOCS
15458 && TARGET_VR4130_ALIGN)
15459 vr4130_align_insns ();
15460 if (mips_expand_ghost_gp_insns ())
15461 /* The expansion could invalidate some of the VR4130 alignment
15462 optimizations, but this should be an extremely rare case anyhow. */
15463 mips_reorg_process_insns ();
15466 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
15467 in order to avoid duplicating too much logic from elsewhere. */
15470 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
15471 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
15474 rtx this_rtx, temp1, temp2, insn, fnaddr;
15475 bool use_sibcall_p;
15477 /* Pretend to be a post-reload pass while generating rtl. */
15478 reload_completed = 1;
15480 /* Mark the end of the (empty) prologue. */
15481 emit_note (NOTE_INSN_PROLOGUE_END);
15483 /* Determine if we can use a sibcall to call FUNCTION directly. */
15484 fnaddr = XEXP (DECL_RTL (function), 0);
15485 use_sibcall_p = (mips_function_ok_for_sibcall (function, NULL)
15486 && const_call_insn_operand (fnaddr, Pmode));
15488 /* Determine if we need to load FNADDR from the GOT. */
15490 && (mips_got_symbol_type_p
15491 (mips_classify_symbol (fnaddr, SYMBOL_CONTEXT_LEA))))
15493 /* Pick a global pointer. Use a call-clobbered register if
15494 TARGET_CALL_SAVED_GP. */
15495 cfun->machine->global_pointer
15496 = TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM;
15497 cfun->machine->must_initialize_gp_p = true;
15498 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
15500 /* Set up the global pointer for n32 or n64 abicalls. */
15501 mips_emit_loadgp ();
15504 /* We need two temporary registers in some cases. */
15505 temp1 = gen_rtx_REG (Pmode, 2);
15506 temp2 = gen_rtx_REG (Pmode, 3);
15508 /* Find out which register contains the "this" pointer. */
15509 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
15510 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
15512 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST);
15514 /* Add DELTA to THIS_RTX. */
15517 rtx offset = GEN_INT (delta);
15518 if (!SMALL_OPERAND (delta))
15520 mips_emit_move (temp1, offset);
15523 emit_insn (gen_add3_insn (this_rtx, this_rtx, offset));
15526 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
15527 if (vcall_offset != 0)
15531 /* Set TEMP1 to *THIS_RTX. */
15532 mips_emit_move (temp1, gen_rtx_MEM (Pmode, this_rtx));
15534 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
15535 addr = mips_add_offset (temp2, temp1, vcall_offset);
15537 /* Load the offset and add it to THIS_RTX. */
15538 mips_emit_move (temp1, gen_rtx_MEM (Pmode, addr));
15539 emit_insn (gen_add3_insn (this_rtx, this_rtx, temp1));
15542 /* Jump to the target function. Use a sibcall if direct jumps are
15543 allowed, otherwise load the address into a register first. */
15546 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
15547 SIBLING_CALL_P (insn) = 1;
15551 /* This is messy. GAS treats "la $25,foo" as part of a call
15552 sequence and may allow a global "foo" to be lazily bound.
15553 The general move patterns therefore reject this combination.
15555 In this context, lazy binding would actually be OK
15556 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
15557 TARGET_CALL_SAVED_GP; see mips_load_call_address.
15558 We must therefore load the address via a temporary
15559 register if mips_dangerous_for_la25_p.
15561 If we jump to the temporary register rather than $25,
15562 the assembler can use the move insn to fill the jump's
15565 We can use the same technique for MIPS16 code, where $25
15566 is not a valid JR register. */
15567 if (TARGET_USE_PIC_FN_ADDR_REG
15569 && !mips_dangerous_for_la25_p (fnaddr))
15570 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
15571 mips_load_call_address (MIPS_CALL_SIBCALL, temp1, fnaddr);
15573 if (TARGET_USE_PIC_FN_ADDR_REG
15574 && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
15575 mips_emit_move (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
15576 emit_jump_insn (gen_indirect_jump (temp1));
15579 /* Run just enough of rest_of_compilation. This sequence was
15580 "borrowed" from alpha.c. */
15581 insn = get_insns ();
15582 insn_locators_alloc ();
15583 split_all_insns_noflow ();
15584 mips16_lay_out_constants ();
15585 shorten_branches (insn);
15586 final_start_function (insn, file, 1);
15587 final (insn, file, 1);
15588 final_end_function ();
15590 /* Clean up the vars set above. Note that final_end_function resets
15591 the global pointer for us. */
15592 reload_completed = 0;
15595 /* The last argument passed to mips_set_mips16_mode, or negative if the
15596 function hasn't been called yet. */
15597 static int was_mips16_p = -1;
15599 /* Set up the target-dependent global state so that it matches the
15600 current function's ISA mode. */
15603 mips_set_mips16_mode (int mips16_p)
15605 if (mips16_p == was_mips16_p)
15608 /* Restore base settings of various flags. */
15609 target_flags = mips_base_target_flags;
15610 flag_schedule_insns = mips_base_schedule_insns;
15611 flag_reorder_blocks_and_partition = mips_base_reorder_blocks_and_partition;
15612 flag_move_loop_invariants = mips_base_move_loop_invariants;
15613 align_loops = mips_base_align_loops;
15614 align_jumps = mips_base_align_jumps;
15615 align_functions = mips_base_align_functions;
15619 /* Switch to MIPS16 mode. */
15620 target_flags |= MASK_MIPS16;
15622 /* Don't run the scheduler before reload, since it tends to
15623 increase register pressure. */
15624 flag_schedule_insns = 0;
15626 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
15627 the whole function to be in a single section. */
15628 flag_reorder_blocks_and_partition = 0;
15630 /* Don't move loop invariants, because it tends to increase
15631 register pressure. It also introduces an extra move in cases
15632 where the constant is the first operand in a two-operand binary
15633 instruction, or when it forms a register argument to a functon
15635 flag_move_loop_invariants = 0;
15637 target_flags |= MASK_EXPLICIT_RELOCS;
15639 /* Experiments suggest we get the best overall section-anchor
15640 results from using the range of an unextended LW or SW. Code
15641 that makes heavy use of byte or short accesses can do better
15642 with ranges of 0...31 and 0...63 respectively, but most code is
15643 sensitive to the range of LW and SW instead. */
15644 targetm.min_anchor_offset = 0;
15645 targetm.max_anchor_offset = 127;
15647 targetm.const_anchor = 0;
15649 /* MIPS16 has no BAL instruction. */
15650 target_flags &= ~MASK_RELAX_PIC_CALLS;
15652 /* The R4000 errata don't apply to any known MIPS16 cores.
15653 It's simpler to make the R4000 fixes and MIPS16 mode
15654 mutually exclusive. */
15655 target_flags &= ~MASK_FIX_R4000;
15657 if (flag_pic && !TARGET_OLDABI)
15658 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
15661 sorry ("MIPS16 -mxgot code");
15663 if (TARGET_HARD_FLOAT_ABI && !TARGET_OLDABI)
15664 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
15668 /* Switch to normal (non-MIPS16) mode. */
15669 target_flags &= ~MASK_MIPS16;
15671 /* Provide default values for align_* for 64-bit targets. */
15674 if (align_loops == 0)
15676 if (align_jumps == 0)
15678 if (align_functions == 0)
15679 align_functions = 8;
15682 targetm.min_anchor_offset = -32768;
15683 targetm.max_anchor_offset = 32767;
15685 targetm.const_anchor = 0x8000;
15688 /* (Re)initialize MIPS target internals for new ISA. */
15689 mips_init_relocs ();
15693 if (!mips16_globals)
15694 mips16_globals = save_target_globals ();
15696 restore_target_globals (mips16_globals);
15699 restore_target_globals (&default_target_globals);
15701 was_mips16_p = mips16_p;
15704 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
15705 function should use the MIPS16 ISA and switch modes accordingly. */
15708 mips_set_current_function (tree fndecl)
15710 mips_set_mips16_mode (mips_use_mips16_mode_p (fndecl));
15713 /* Allocate a chunk of memory for per-function machine-dependent data. */
15715 static struct machine_function *
15716 mips_init_machine_status (void)
15718 return ggc_alloc_cleared_machine_function ();
15721 /* Return the processor associated with the given ISA level, or null
15722 if the ISA isn't valid. */
15724 static const struct mips_cpu_info *
15725 mips_cpu_info_from_isa (int isa)
15729 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
15730 if (mips_cpu_info_table[i].isa == isa)
15731 return mips_cpu_info_table + i;
15736 /* Return a mips_cpu_info entry determined by an option valued
15739 static const struct mips_cpu_info *
15740 mips_cpu_info_from_opt (int opt)
15744 case MIPS_ARCH_OPTION_FROM_ABI:
15745 /* 'from-abi' selects the most compatible architecture for the
15746 given ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit
15747 ABIs. For the EABIs, we have to decide whether we're using
15748 the 32-bit or 64-bit version. */
15749 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
15750 : ABI_NEEDS_64BIT_REGS ? 3
15751 : (TARGET_64BIT ? 3 : 1));
15753 case MIPS_ARCH_OPTION_NATIVE:
15754 gcc_unreachable ();
15757 return &mips_cpu_info_table[opt];
15761 /* Return a default mips_cpu_info entry, given that no -march= option
15762 was explicitly specified. */
15764 static const struct mips_cpu_info *
15765 mips_default_arch (void)
15767 #if defined (MIPS_CPU_STRING_DEFAULT)
15769 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
15770 if (strcmp (mips_cpu_info_table[i].name, MIPS_CPU_STRING_DEFAULT) == 0)
15771 return mips_cpu_info_table + i;
15772 gcc_unreachable ();
15773 #elif defined (MIPS_ISA_DEFAULT)
15774 return mips_cpu_info_from_isa (MIPS_ISA_DEFAULT);
15776 /* 'from-abi' makes a good default: you get whatever the ABI
15778 return mips_cpu_info_from_opt (MIPS_ARCH_OPTION_FROM_ABI);
15782 /* Set up globals to generate code for the ISA or processor
15783 described by INFO. */
15786 mips_set_architecture (const struct mips_cpu_info *info)
15790 mips_arch_info = info;
15791 mips_arch = info->cpu;
15792 mips_isa = info->isa;
15796 /* Likewise for tuning. */
15799 mips_set_tune (const struct mips_cpu_info *info)
15803 mips_tune_info = info;
15804 mips_tune = info->cpu;
15808 /* Implement TARGET_OPTION_OVERRIDE. */
15811 mips_option_override (void)
15813 int i, start, regno, mode;
15815 if (global_options_set.x_mips_isa_option)
15816 mips_isa_option_info = &mips_cpu_info_table[mips_isa_option];
15818 /* Process flags as though we were generating non-MIPS16 code. */
15819 mips_base_mips16 = TARGET_MIPS16;
15820 target_flags &= ~MASK_MIPS16;
15822 #ifdef SUBTARGET_OVERRIDE_OPTIONS
15823 SUBTARGET_OVERRIDE_OPTIONS;
15826 /* -mno-float overrides -mhard-float and -msoft-float. */
15827 if (TARGET_NO_FLOAT)
15829 target_flags |= MASK_SOFT_FLOAT_ABI;
15830 target_flags_explicit |= MASK_SOFT_FLOAT_ABI;
15833 if (TARGET_FLIP_MIPS16)
15834 TARGET_INTERLINK_MIPS16 = 1;
15836 /* Set the small data limit. */
15837 mips_small_data_threshold = (global_options_set.x_g_switch_value
15839 : MIPS_DEFAULT_GVALUE);
15841 /* The following code determines the architecture and register size.
15842 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
15843 The GAS and GCC code should be kept in sync as much as possible. */
15845 if (global_options_set.x_mips_arch_option)
15846 mips_set_architecture (mips_cpu_info_from_opt (mips_arch_option));
15848 if (mips_isa_option_info != 0)
15850 if (mips_arch_info == 0)
15851 mips_set_architecture (mips_isa_option_info);
15852 else if (mips_arch_info->isa != mips_isa_option_info->isa)
15853 error ("%<-%s%> conflicts with the other architecture options, "
15854 "which specify a %s processor",
15855 mips_isa_option_info->name,
15856 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
15859 if (mips_arch_info == 0)
15860 mips_set_architecture (mips_default_arch ());
15862 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
15863 error ("%<-march=%s%> is not compatible with the selected ABI",
15864 mips_arch_info->name);
15866 /* Optimize for mips_arch, unless -mtune selects a different processor. */
15867 if (global_options_set.x_mips_tune_option)
15868 mips_set_tune (mips_cpu_info_from_opt (mips_tune_option));
15870 if (mips_tune_info == 0)
15871 mips_set_tune (mips_arch_info);
15873 if ((target_flags_explicit & MASK_64BIT) != 0)
15875 /* The user specified the size of the integer registers. Make sure
15876 it agrees with the ABI and ISA. */
15877 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
15878 error ("%<-mgp64%> used with a 32-bit processor");
15879 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
15880 error ("%<-mgp32%> used with a 64-bit ABI");
15881 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
15882 error ("%<-mgp64%> used with a 32-bit ABI");
15886 /* Infer the integer register size from the ABI and processor.
15887 Restrict ourselves to 32-bit registers if that's all the
15888 processor has, or if the ABI cannot handle 64-bit registers. */
15889 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
15890 target_flags &= ~MASK_64BIT;
15892 target_flags |= MASK_64BIT;
15895 if ((target_flags_explicit & MASK_FLOAT64) != 0)
15897 if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
15898 error ("unsupported combination: %s", "-mfp64 -msingle-float");
15899 else if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
15900 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
15901 else if (!TARGET_64BIT && TARGET_FLOAT64)
15903 if (!ISA_HAS_MXHC1)
15904 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
15905 " the target supports the mfhc1 and mthc1 instructions");
15906 else if (mips_abi != ABI_32)
15907 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
15913 /* -msingle-float selects 32-bit float registers. Otherwise the
15914 float registers should be the same size as the integer ones. */
15915 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
15916 target_flags |= MASK_FLOAT64;
15918 target_flags &= ~MASK_FLOAT64;
15921 /* End of code shared with GAS. */
15923 /* If a -mlong* option was given, check that it matches the ABI,
15924 otherwise infer the -mlong* setting from the other options. */
15925 if ((target_flags_explicit & MASK_LONG64) != 0)
15929 if (mips_abi == ABI_N32)
15930 error ("%qs is incompatible with %qs", "-mabi=n32", "-mlong64");
15931 else if (mips_abi == ABI_32)
15932 error ("%qs is incompatible with %qs", "-mabi=32", "-mlong64");
15933 else if (mips_abi == ABI_O64 && TARGET_ABICALLS)
15934 /* We have traditionally allowed non-abicalls code to use
15935 an LP64 form of o64. However, it would take a bit more
15936 effort to support the combination of 32-bit GOT entries
15937 and 64-bit pointers, so we treat the abicalls case as
15939 error ("the combination of %qs and %qs is incompatible with %qs",
15940 "-mabi=o64", "-mabicalls", "-mlong64");
15944 if (mips_abi == ABI_64)
15945 error ("%qs is incompatible with %qs", "-mabi=64", "-mlong32");
15950 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
15951 target_flags |= MASK_LONG64;
15953 target_flags &= ~MASK_LONG64;
15956 if (!TARGET_OLDABI)
15957 flag_pcc_struct_return = 0;
15959 /* Decide which rtx_costs structure to use. */
15961 mips_cost = &mips_rtx_cost_optimize_size;
15963 mips_cost = &mips_rtx_cost_data[mips_tune];
15965 /* If the user hasn't specified a branch cost, use the processor's
15967 if (mips_branch_cost == 0)
15968 mips_branch_cost = mips_cost->branch_cost;
15970 /* If neither -mbranch-likely nor -mno-branch-likely was given
15971 on the command line, set MASK_BRANCHLIKELY based on the target
15972 architecture and tuning flags. Annulled delay slots are a
15973 size win, so we only consider the processor-specific tuning
15974 for !optimize_size. */
15975 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
15977 if (ISA_HAS_BRANCHLIKELY
15979 || (mips_tune_info->tune_flags & PTF_AVOID_BRANCHLIKELY) == 0))
15980 target_flags |= MASK_BRANCHLIKELY;
15982 target_flags &= ~MASK_BRANCHLIKELY;
15984 else if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
15985 warning (0, "the %qs architecture does not support branch-likely"
15986 " instructions", mips_arch_info->name);
15988 /* The effect of -mabicalls isn't defined for the EABI. */
15989 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
15991 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
15992 target_flags &= ~MASK_ABICALLS;
15995 if (TARGET_ABICALLS_PIC2)
15996 /* We need to set flag_pic for executables as well as DSOs
15997 because we may reference symbols that are not defined in
15998 the final executable. (MIPS does not use things like
15999 copy relocs, for example.)
16001 There is a body of code that uses __PIC__ to distinguish
16002 between -mabicalls and -mno-abicalls code. The non-__PIC__
16003 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
16004 long as any indirect jumps use $25. */
16007 /* -mvr4130-align is a "speed over size" optimization: it usually produces
16008 faster code, but at the expense of more nops. Enable it at -O3 and
16010 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
16011 target_flags |= MASK_VR4130_ALIGN;
16013 /* Prefer a call to memcpy over inline code when optimizing for size,
16014 though see MOVE_RATIO in mips.h. */
16015 if (optimize_size && (target_flags_explicit & MASK_MEMCPY) == 0)
16016 target_flags |= MASK_MEMCPY;
16018 /* If we have a nonzero small-data limit, check that the -mgpopt
16019 setting is consistent with the other target flags. */
16020 if (mips_small_data_threshold > 0)
16024 if (!TARGET_EXPLICIT_RELOCS)
16025 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
16027 TARGET_LOCAL_SDATA = false;
16028 TARGET_EXTERN_SDATA = false;
16032 if (TARGET_VXWORKS_RTP)
16033 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
16035 if (TARGET_ABICALLS)
16036 warning (0, "cannot use small-data accesses for %qs",
16041 /* Make sure that the user didn't turn off paired single support when
16042 MIPS-3D support is requested. */
16044 && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
16045 && !TARGET_PAIRED_SINGLE_FLOAT)
16046 error ("%<-mips3d%> requires %<-mpaired-single%>");
16048 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
16050 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
16052 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
16053 and TARGET_HARD_FLOAT_ABI are both true. */
16054 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT_ABI))
16055 error ("%qs must be used with %qs",
16056 TARGET_MIPS3D ? "-mips3d" : "-mpaired-single",
16057 TARGET_HARD_FLOAT_ABI ? "-mfp64" : "-mhard-float");
16059 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
16061 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_HAS_PAIRED_SINGLE)
16062 warning (0, "the %qs architecture does not support paired-single"
16063 " instructions", mips_arch_info->name);
16065 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
16066 && !TARGET_CACHE_BUILTIN)
16068 error ("%qs requires a target that provides the %qs instruction",
16069 "-mr10k-cache-barrier", "cache");
16070 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE;
16073 /* If TARGET_DSPR2, enable MASK_DSP. */
16075 target_flags |= MASK_DSP;
16077 /* .eh_frame addresses should be the same width as a C pointer.
16078 Most MIPS ABIs support only one pointer size, so the assembler
16079 will usually know exactly how big an .eh_frame address is.
16081 Unfortunately, this is not true of the 64-bit EABI. The ABI was
16082 originally defined to use 64-bit pointers (i.e. it is LP64), and
16083 this is still the default mode. However, we also support an n32-like
16084 ILP32 mode, which is selected by -mlong32. The problem is that the
16085 assembler has traditionally not had an -mlong option, so it has
16086 traditionally not known whether we're using the ILP32 or LP64 form.
16088 As it happens, gas versions up to and including 2.19 use _32-bit_
16089 addresses for EABI64 .cfi_* directives. This is wrong for the
16090 default LP64 mode, so we can't use the directives by default.
16091 Moreover, since gas's current behavior is at odds with gcc's
16092 default behavior, it seems unwise to rely on future versions
16093 of gas behaving the same way. We therefore avoid using .cfi
16094 directives for -mlong32 as well. */
16095 if (mips_abi == ABI_EABI && TARGET_64BIT)
16096 flag_dwarf2_cfi_asm = 0;
16098 /* .cfi_* directives generate a read-only section, so fall back on
16099 manual .eh_frame creation if we need the section to be writable. */
16100 if (TARGET_WRITABLE_EH_FRAME)
16101 flag_dwarf2_cfi_asm = 0;
16103 mips_init_print_operand_punct ();
16105 /* Set up array to map GCC register number to debug register number.
16106 Ignore the special purpose register numbers. */
16108 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
16110 mips_dbx_regno[i] = INVALID_REGNUM;
16111 if (GP_REG_P (i) || FP_REG_P (i) || ALL_COP_REG_P (i))
16112 mips_dwarf_regno[i] = i;
16114 mips_dwarf_regno[i] = INVALID_REGNUM;
16117 start = GP_DBX_FIRST - GP_REG_FIRST;
16118 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
16119 mips_dbx_regno[i] = i + start;
16121 start = FP_DBX_FIRST - FP_REG_FIRST;
16122 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
16123 mips_dbx_regno[i] = i + start;
16125 /* Accumulator debug registers use big-endian ordering. */
16126 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
16127 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
16128 mips_dwarf_regno[HI_REGNUM] = MD_REG_FIRST + 0;
16129 mips_dwarf_regno[LO_REGNUM] = MD_REG_FIRST + 1;
16130 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
16132 mips_dwarf_regno[i + TARGET_LITTLE_ENDIAN] = i;
16133 mips_dwarf_regno[i + TARGET_BIG_ENDIAN] = i + 1;
16136 /* Set up mips_hard_regno_mode_ok. */
16137 for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
16138 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
16139 mips_hard_regno_mode_ok[mode][regno]
16140 = mips_hard_regno_mode_ok_p (regno, (enum machine_mode) mode);
16142 /* Function to allocate machine-dependent function status. */
16143 init_machine_status = &mips_init_machine_status;
16145 /* Default to working around R4000 errata only if the processor
16146 was selected explicitly. */
16147 if ((target_flags_explicit & MASK_FIX_R4000) == 0
16148 && strcmp (mips_arch_info->name, "r4000") == 0)
16149 target_flags |= MASK_FIX_R4000;
16151 /* Default to working around R4400 errata only if the processor
16152 was selected explicitly. */
16153 if ((target_flags_explicit & MASK_FIX_R4400) == 0
16154 && strcmp (mips_arch_info->name, "r4400") == 0)
16155 target_flags |= MASK_FIX_R4400;
16157 /* Default to working around R10000 errata only if the processor
16158 was selected explicitly. */
16159 if ((target_flags_explicit & MASK_FIX_R10000) == 0
16160 && strcmp (mips_arch_info->name, "r10000") == 0)
16161 target_flags |= MASK_FIX_R10000;
16163 /* Make sure that branch-likely instructions available when using
16164 -mfix-r10000. The instructions are not available if either:
16166 1. -mno-branch-likely was passed.
16167 2. The selected ISA does not support branch-likely and
16168 the command line does not include -mbranch-likely. */
16169 if (TARGET_FIX_R10000
16170 && ((target_flags_explicit & MASK_BRANCHLIKELY) == 0
16171 ? !ISA_HAS_BRANCHLIKELY
16172 : !TARGET_BRANCHLIKELY))
16173 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
16175 if (TARGET_SYNCI && !ISA_HAS_SYNCI)
16177 warning (0, "the %qs architecture does not support the synci "
16178 "instruction", mips_arch_info->name);
16179 target_flags &= ~MASK_SYNCI;
16182 /* Only optimize PIC indirect calls if they are actually required. */
16183 if (!TARGET_USE_GOT || !TARGET_EXPLICIT_RELOCS)
16184 target_flags &= ~MASK_RELAX_PIC_CALLS;
16186 /* Save base state of options. */
16187 mips_base_target_flags = target_flags;
16188 mips_base_schedule_insns = flag_schedule_insns;
16189 mips_base_reorder_blocks_and_partition = flag_reorder_blocks_and_partition;
16190 mips_base_move_loop_invariants = flag_move_loop_invariants;
16191 mips_base_align_loops = align_loops;
16192 mips_base_align_jumps = align_jumps;
16193 mips_base_align_functions = align_functions;
16195 /* Now select the ISA mode.
16197 Do all CPP-sensitive stuff in non-MIPS16 mode; we'll switch to
16198 MIPS16 mode afterwards if need be. */
16199 mips_set_mips16_mode (false);
16202 /* Swap the register information for registers I and I + 1, which
16203 currently have the wrong endianness. Note that the registers'
16204 fixedness and call-clobberedness might have been set on the
16208 mips_swap_registers (unsigned int i)
16213 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
16214 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
16216 SWAP_INT (fixed_regs[i], fixed_regs[i + 1]);
16217 SWAP_INT (call_used_regs[i], call_used_regs[i + 1]);
16218 SWAP_INT (call_really_used_regs[i], call_really_used_regs[i + 1]);
16219 SWAP_STRING (reg_names[i], reg_names[i + 1]);
16225 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
16228 mips_conditional_register_usage (void)
16233 /* These DSP control register fields are global. */
16234 global_regs[CCDSP_PO_REGNUM] = 1;
16235 global_regs[CCDSP_SC_REGNUM] = 1;
16238 AND_COMPL_HARD_REG_SET (accessible_reg_set,
16239 reg_class_contents[(int) DSP_ACC_REGS]);
16241 if (!TARGET_HARD_FLOAT)
16243 AND_COMPL_HARD_REG_SET (accessible_reg_set,
16244 reg_class_contents[(int) FP_REGS]);
16245 AND_COMPL_HARD_REG_SET (accessible_reg_set,
16246 reg_class_contents[(int) ST_REGS]);
16248 else if (!ISA_HAS_8CC)
16250 /* We only have a single condition-code register. We implement
16251 this by fixing all the condition-code registers and generating
16252 RTL that refers directly to ST_REG_FIRST. */
16253 AND_COMPL_HARD_REG_SET (accessible_reg_set,
16254 reg_class_contents[(int) ST_REGS]);
16255 SET_HARD_REG_BIT (accessible_reg_set, FPSW_REGNUM);
16256 fixed_regs[FPSW_REGNUM] = call_used_regs[FPSW_REGNUM] = 1;
16260 /* In MIPS16 mode, we permit the $t temporary registers to be used
16261 for reload. We prohibit the unused $s registers, since they
16262 are call-saved, and saving them via a MIPS16 register would
16263 probably waste more time than just reloading the value. */
16264 fixed_regs[18] = call_used_regs[18] = 1;
16265 fixed_regs[19] = call_used_regs[19] = 1;
16266 fixed_regs[20] = call_used_regs[20] = 1;
16267 fixed_regs[21] = call_used_regs[21] = 1;
16268 fixed_regs[22] = call_used_regs[22] = 1;
16269 fixed_regs[23] = call_used_regs[23] = 1;
16270 fixed_regs[26] = call_used_regs[26] = 1;
16271 fixed_regs[27] = call_used_regs[27] = 1;
16272 fixed_regs[30] = call_used_regs[30] = 1;
16274 /* Do not allow HI and LO to be treated as register operands.
16275 There are no MTHI or MTLO instructions (or any real need
16276 for them) and one-way registers cannot easily be reloaded. */
16277 AND_COMPL_HARD_REG_SET (operand_reg_set,
16278 reg_class_contents[(int) MD_REGS]);
16280 /* $f20-$f23 are call-clobbered for n64. */
16281 if (mips_abi == ABI_64)
16284 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
16285 call_really_used_regs[regno] = call_used_regs[regno] = 1;
16287 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
16289 if (mips_abi == ABI_N32)
16292 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
16293 call_really_used_regs[regno] = call_used_regs[regno] = 1;
16295 /* Make sure that double-register accumulator values are correctly
16296 ordered for the current endianness. */
16297 if (TARGET_LITTLE_ENDIAN)
16299 unsigned int regno;
16301 mips_swap_registers (MD_REG_FIRST);
16302 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno += 2)
16303 mips_swap_registers (regno);
16307 /* When generating MIPS16 code, we want to allocate $24 (T_REG) before
16308 other registers for instructions for which it is possible. This
16309 encourages the compiler to use CMP in cases where an XOR would
16310 require some register shuffling. */
16313 mips_order_regs_for_local_alloc (void)
16317 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
16318 reg_alloc_order[i] = i;
16322 /* It really doesn't matter where we put register 0, since it is
16323 a fixed register anyhow. */
16324 reg_alloc_order[0] = 24;
16325 reg_alloc_order[24] = 0;
16329 /* Implement EH_USES. */
16332 mips_eh_uses (unsigned int regno)
16334 if (reload_completed && !TARGET_ABSOLUTE_JUMPS)
16336 /* We need to force certain registers to be live in order to handle
16337 PIC long branches correctly. See mips_must_initialize_gp_p for
16339 if (mips_cfun_has_cprestore_slot_p ())
16341 if (regno == CPRESTORE_SLOT_REGNUM)
16346 if (cfun->machine->global_pointer == regno)
16354 /* Implement EPILOGUE_USES. */
16357 mips_epilogue_uses (unsigned int regno)
16359 /* Say that the epilogue uses the return address register. Note that
16360 in the case of sibcalls, the values "used by the epilogue" are
16361 considered live at the start of the called function. */
16362 if (regno == RETURN_ADDR_REGNUM)
16365 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
16366 See the comment above load_call<mode> for details. */
16367 if (TARGET_USE_GOT && (regno) == GOT_VERSION_REGNUM)
16370 /* An interrupt handler must preserve some registers that are
16371 ordinarily call-clobbered. */
16372 if (cfun->machine->interrupt_handler_p
16373 && mips_interrupt_extra_call_saved_reg_p (regno))
16379 /* A for_each_rtx callback. Stop the search if *X is an AT register. */
16382 mips_at_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
16384 return REG_P (*x) && REGNO (*x) == AT_REGNUM;
16387 /* Return true if INSN needs to be wrapped in ".set noat".
16388 INSN has NOPERANDS operands, stored in OPVEC. */
16391 mips_need_noat_wrapper_p (rtx insn, rtx *opvec, int noperands)
16395 if (recog_memoized (insn) >= 0)
16396 for (i = 0; i < noperands; i++)
16397 if (for_each_rtx (&opvec[i], mips_at_reg_p, NULL))
16402 /* Implement FINAL_PRESCAN_INSN. */
16405 mips_final_prescan_insn (rtx insn, rtx *opvec, int noperands)
16407 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
16408 mips_push_asm_switch (&mips_noat);
16411 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */
16414 mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED, rtx insn,
16415 rtx *opvec, int noperands)
16417 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
16418 mips_pop_asm_switch (&mips_noat);
16421 /* Return the function that is used to expand the <u>mulsidi3 pattern.
16422 EXT_CODE is the code of the extension used. Return NULL if widening
16423 multiplication shouldn't be used. */
16426 mips_mulsidi3_gen_fn (enum rtx_code ext_code)
16430 signed_p = ext_code == SIGN_EXTEND;
16433 /* Don't use widening multiplication with MULT when we have DMUL. Even
16434 with the extension of its input operands DMUL is faster. Note that
16435 the extension is not needed for signed multiplication. In order to
16436 ensure that we always remove the redundant sign-extension in this
16437 case we still expand mulsidi3 for DMUL. */
16439 return signed_p ? gen_mulsidi3_64bit_dmul : NULL;
16442 ? gen_mulsidi3_64bit_mips16
16443 : gen_umulsidi3_64bit_mips16);
16444 if (TARGET_FIX_R4000)
16446 return signed_p ? gen_mulsidi3_64bit : gen_umulsidi3_64bit;
16452 ? gen_mulsidi3_32bit_mips16
16453 : gen_umulsidi3_32bit_mips16);
16454 if (TARGET_FIX_R4000 && !ISA_HAS_DSP)
16455 return signed_p ? gen_mulsidi3_32bit_r4000 : gen_umulsidi3_32bit_r4000;
16456 return signed_p ? gen_mulsidi3_32bit : gen_umulsidi3_32bit;
16460 /* Return the size in bytes of the trampoline code, padded to
16461 TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target
16462 function address immediately follow. */
16465 mips_trampoline_code_size (void)
16467 if (TARGET_USE_PIC_FN_ADDR_REG)
16469 else if (ptr_mode == DImode)
16471 else if (ISA_HAS_LOAD_DELAY)
16477 /* Implement TARGET_TRAMPOLINE_INIT. */
16480 mips_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
16482 rtx addr, end_addr, high, low, opcode, mem;
16485 HOST_WIDE_INT end_addr_offset, static_chain_offset, target_function_offset;
16487 /* Work out the offsets of the pointers from the start of the
16488 trampoline code. */
16489 end_addr_offset = mips_trampoline_code_size ();
16490 static_chain_offset = end_addr_offset;
16491 target_function_offset = static_chain_offset + GET_MODE_SIZE (ptr_mode);
16493 /* Get pointers to the beginning and end of the code block. */
16494 addr = force_reg (Pmode, XEXP (m_tramp, 0));
16495 end_addr = mips_force_binary (Pmode, PLUS, addr, GEN_INT (end_addr_offset));
16497 #define OP(X) gen_int_mode (X, SImode)
16499 /* Build up the code in TRAMPOLINE. */
16501 if (TARGET_USE_PIC_FN_ADDR_REG)
16503 /* $25 contains the address of the trampoline. Emit code of the form:
16505 l[wd] $1, target_function_offset($25)
16506 l[wd] $static_chain, static_chain_offset($25)
16509 trampoline[i++] = OP (MIPS_LOAD_PTR (AT_REGNUM,
16510 target_function_offset,
16511 PIC_FUNCTION_ADDR_REGNUM));
16512 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
16513 static_chain_offset,
16514 PIC_FUNCTION_ADDR_REGNUM));
16515 trampoline[i++] = OP (MIPS_JR (AT_REGNUM));
16516 trampoline[i++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM, AT_REGNUM));
16518 else if (ptr_mode == DImode)
16520 /* It's too cumbersome to create the full 64-bit address, so let's
16526 1: l[wd] $25, target_function_offset - 12($31)
16527 l[wd] $static_chain, static_chain_offset - 12($31)
16531 where 12 is the offset of "1:" from the start of the code block. */
16532 trampoline[i++] = OP (MIPS_MOVE (AT_REGNUM, RETURN_ADDR_REGNUM));
16533 trampoline[i++] = OP (MIPS_BAL (1));
16534 trampoline[i++] = OP (MIPS_NOP);
16535 trampoline[i++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
16536 target_function_offset - 12,
16537 RETURN_ADDR_REGNUM));
16538 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
16539 static_chain_offset - 12,
16540 RETURN_ADDR_REGNUM));
16541 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
16542 trampoline[i++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM, AT_REGNUM));
16546 /* If the target has load delays, emit:
16548 lui $1, %hi(end_addr)
16549 lw $25, %lo(end_addr + ...)($1)
16550 lw $static_chain, %lo(end_addr + ...)($1)
16556 lui $1, %hi(end_addr)
16557 lw $25, %lo(end_addr + ...)($1)
16559 lw $static_chain, %lo(end_addr + ...)($1). */
16561 /* Split END_ADDR into %hi and %lo values. Trampolines are aligned
16562 to 64 bits, so the %lo value will have the bottom 3 bits clear. */
16563 high = expand_simple_binop (SImode, PLUS, end_addr, GEN_INT (0x8000),
16564 NULL, false, OPTAB_WIDEN);
16565 high = expand_simple_binop (SImode, LSHIFTRT, high, GEN_INT (16),
16566 NULL, false, OPTAB_WIDEN);
16567 low = convert_to_mode (SImode, gen_lowpart (HImode, end_addr), true);
16569 /* Emit the LUI. */
16570 opcode = OP (MIPS_LUI (AT_REGNUM, 0));
16571 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, high,
16572 NULL, false, OPTAB_WIDEN);
16574 /* Emit the load of the target function. */
16575 opcode = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
16576 target_function_offset - end_addr_offset,
16578 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
16579 NULL, false, OPTAB_WIDEN);
16581 /* Emit the JR here, if we can. */
16582 if (!ISA_HAS_LOAD_DELAY)
16583 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
16585 /* Emit the load of the static chain register. */
16586 opcode = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
16587 static_chain_offset - end_addr_offset,
16589 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
16590 NULL, false, OPTAB_WIDEN);
16592 /* Emit the JR, if we couldn't above. */
16593 if (ISA_HAS_LOAD_DELAY)
16595 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
16596 trampoline[i++] = OP (MIPS_NOP);
16602 /* Copy the trampoline code. Leave any padding uninitialized. */
16603 for (j = 0; j < i; j++)
16605 mem = adjust_address (m_tramp, SImode, j * GET_MODE_SIZE (SImode));
16606 mips_emit_move (mem, trampoline[j]);
16609 /* Set up the static chain pointer field. */
16610 mem = adjust_address (m_tramp, ptr_mode, static_chain_offset);
16611 mips_emit_move (mem, chain_value);
16613 /* Set up the target function field. */
16614 mem = adjust_address (m_tramp, ptr_mode, target_function_offset);
16615 mips_emit_move (mem, XEXP (DECL_RTL (fndecl), 0));
16617 /* Flush the code part of the trampoline. */
16618 emit_insn (gen_add3_insn (end_addr, addr, GEN_INT (TRAMPOLINE_SIZE)));
16619 emit_insn (gen_clear_cache (addr, end_addr));
16622 /* Implement FUNCTION_PROFILER. */
16624 void mips_function_profiler (FILE *file)
16627 sorry ("mips16 function profiling");
16628 if (TARGET_LONG_CALLS)
16630 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */
16631 if (Pmode == DImode)
16632 fprintf (file, "\tdla\t%s,_mcount\n", reg_names[3]);
16634 fprintf (file, "\tla\t%s,_mcount\n", reg_names[3]);
16636 mips_push_asm_switch (&mips_noat);
16637 fprintf (file, "\tmove\t%s,%s\t\t# save current return address\n",
16638 reg_names[AT_REGNUM], reg_names[RETURN_ADDR_REGNUM]);
16639 /* _mcount treats $2 as the static chain register. */
16640 if (cfun->static_chain_decl != NULL)
16641 fprintf (file, "\tmove\t%s,%s\n", reg_names[2],
16642 reg_names[STATIC_CHAIN_REGNUM]);
16643 if (TARGET_MCOUNT_RA_ADDRESS)
16645 /* If TARGET_MCOUNT_RA_ADDRESS load $12 with the address of the
16646 ra save location. */
16647 if (cfun->machine->frame.ra_fp_offset == 0)
16648 /* ra not saved, pass zero. */
16649 fprintf (file, "\tmove\t%s,%s\n", reg_names[12], reg_names[0]);
16651 fprintf (file, "\t%s\t%s," HOST_WIDE_INT_PRINT_DEC "(%s)\n",
16652 Pmode == DImode ? "dla" : "la", reg_names[12],
16653 cfun->machine->frame.ra_fp_offset,
16654 reg_names[STACK_POINTER_REGNUM]);
16656 if (!TARGET_NEWABI)
16658 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n",
16659 TARGET_64BIT ? "dsubu" : "subu",
16660 reg_names[STACK_POINTER_REGNUM],
16661 reg_names[STACK_POINTER_REGNUM],
16662 Pmode == DImode ? 16 : 8);
16664 if (TARGET_LONG_CALLS)
16665 fprintf (file, "\tjalr\t%s\n", reg_names[3]);
16667 fprintf (file, "\tjal\t_mcount\n");
16668 mips_pop_asm_switch (&mips_noat);
16669 /* _mcount treats $2 as the static chain register. */
16670 if (cfun->static_chain_decl != NULL)
16671 fprintf (file, "\tmove\t%s,%s\n", reg_names[STATIC_CHAIN_REGNUM],
16675 /* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default
16676 behaviour of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even
16677 when TARGET_LOONGSON_VECTORS is true. */
16679 static unsigned HOST_WIDE_INT
16680 mips_shift_truncation_mask (enum machine_mode mode)
16682 if (TARGET_LOONGSON_VECTORS && VECTOR_MODE_P (mode))
16685 return GET_MODE_BITSIZE (mode) - 1;
16688 /* Implement TARGET_PREPARE_PCH_SAVE. */
16691 mips_prepare_pch_save (void)
16693 /* We are called in a context where the current MIPS16 vs. non-MIPS16
16694 setting should be irrelevant. The question then is: which setting
16695 makes most sense at load time?
16697 The PCH is loaded before the first token is read. We should never
16698 have switched into MIPS16 mode by that point, and thus should not
16699 have populated mips16_globals. Nor can we load the entire contents
16700 of mips16_globals from the PCH file, because mips16_globals contains
16701 a combination of GGC and non-GGC data.
16703 There is therefore no point in trying save the GGC part of
16704 mips16_globals to the PCH file, or to preserve MIPS16ness across
16705 the PCH save and load. The loading compiler would not have access
16706 to the non-GGC parts of mips16_globals (either from the PCH file,
16707 or from a copy that the loading compiler generated itself) and would
16708 have to call target_reinit anyway.
16710 It therefore seems best to switch back to non-MIPS16 mode at
16711 save time, and to ensure that mips16_globals remains null after
16713 mips_set_mips16_mode (false);
16714 mips16_globals = 0;
16717 /* Generate or test for an insn that supports a constant permutation. */
16719 #define MAX_VECT_LEN 8
16721 struct expand_vec_perm_d
16723 rtx target, op0, op1;
16724 unsigned char perm[MAX_VECT_LEN];
16725 enum machine_mode vmode;
16726 unsigned char nelt;
16731 /* Construct (set target (vec_select op0 (parallel perm))) and
16732 return true if that's a valid instruction in the active ISA. */
16735 mips_expand_vselect (rtx target, rtx op0,
16736 const unsigned char *perm, unsigned nelt)
16738 rtx rperm[MAX_VECT_LEN], x;
16741 for (i = 0; i < nelt; ++i)
16742 rperm[i] = GEN_INT (perm[i]);
16744 x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (nelt, rperm));
16745 x = gen_rtx_VEC_SELECT (GET_MODE (target), op0, x);
16746 x = gen_rtx_SET (VOIDmode, target, x);
16749 if (recog_memoized (x) < 0)
16757 /* Similar, but generate a vec_concat from op0 and op1 as well. */
16760 mips_expand_vselect_vconcat (rtx target, rtx op0, rtx op1,
16761 const unsigned char *perm, unsigned nelt)
16763 enum machine_mode v2mode;
16766 v2mode = GET_MODE_2XWIDER_MODE (GET_MODE (op0));
16767 x = gen_rtx_VEC_CONCAT (v2mode, op0, op1);
16768 return mips_expand_vselect (target, x, perm, nelt);
16771 /* Recognize patterns for even-odd extraction. */
16774 mips_expand_vpc_loongson_even_odd (struct expand_vec_perm_d *d)
16776 unsigned i, odd, nelt = d->nelt;
16777 rtx t0, t1, t2, t3;
16779 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
16781 /* Even-odd for V2SI/V2SFmode is matched by interleave directly. */
16788 for (i = 1; i < nelt; ++i)
16789 if (d->perm[i] != i * 2 + odd)
16795 /* We need 2*log2(N)-1 operations to achieve odd/even with interleave. */
16796 t0 = gen_reg_rtx (d->vmode);
16797 t1 = gen_reg_rtx (d->vmode);
16801 emit_insn (gen_loongson_punpckhhw (t0, d->op0, d->op1));
16802 emit_insn (gen_loongson_punpcklhw (t1, d->op0, d->op1));
16804 emit_insn (gen_loongson_punpckhhw (d->target, t1, t0));
16806 emit_insn (gen_loongson_punpcklhw (d->target, t1, t0));
16810 t2 = gen_reg_rtx (d->vmode);
16811 t3 = gen_reg_rtx (d->vmode);
16812 emit_insn (gen_loongson_punpckhbh (t0, d->op0, d->op1));
16813 emit_insn (gen_loongson_punpcklbh (t1, d->op0, d->op1));
16814 emit_insn (gen_loongson_punpckhbh (t2, t1, t0));
16815 emit_insn (gen_loongson_punpcklbh (t3, t1, t0));
16817 emit_insn (gen_loongson_punpckhbh (d->target, t3, t2));
16819 emit_insn (gen_loongson_punpcklbh (d->target, t3, t2));
16823 gcc_unreachable ();
16828 /* Recognize patterns for the Loongson PSHUFH instruction. */
16831 mips_expand_vpc_loongson_pshufh (struct expand_vec_perm_d *d)
16836 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
16838 if (d->vmode != V4HImode)
16843 /* Convert the selector into the packed 8-bit form for pshufh. */
16844 /* Recall that loongson is little-endian only. No big-endian
16845 adjustment required. */
16846 for (i = mask = 0; i < 4; i++)
16847 mask |= (d->perm[i] & 3) << (i * 2);
16848 rmask = force_reg (SImode, GEN_INT (mask));
16850 if (d->one_vector_p)
16851 emit_insn (gen_loongson_pshufh (d->target, d->op0, rmask));
16854 rtx t0, t1, x, merge, rmerge[4];
16856 t0 = gen_reg_rtx (V4HImode);
16857 t1 = gen_reg_rtx (V4HImode);
16858 emit_insn (gen_loongson_pshufh (t1, d->op1, rmask));
16859 emit_insn (gen_loongson_pshufh (t0, d->op0, rmask));
16861 for (i = 0; i < 4; ++i)
16862 rmerge[i] = (d->perm[i] & 4 ? constm1_rtx : const0_rtx);
16863 merge = gen_rtx_CONST_VECTOR (V4HImode, gen_rtvec_v (4, rmerge));
16864 merge = force_reg (V4HImode, merge);
16866 x = gen_rtx_AND (V4HImode, merge, t1);
16867 emit_insn (gen_rtx_SET (VOIDmode, t1, x));
16869 x = gen_rtx_NOT (V4HImode, merge);
16870 x = gen_rtx_AND (V4HImode, x, t0);
16871 emit_insn (gen_rtx_SET (VOIDmode, t0, x));
16873 x = gen_rtx_IOR (V4HImode, t0, t1);
16874 emit_insn (gen_rtx_SET (VOIDmode, d->target, x));
16880 /* Recognize broadcast patterns for the Loongson. */
16883 mips_expand_vpc_loongson_bcast (struct expand_vec_perm_d *d)
16888 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
16890 /* Note that we've already matched V2SI via punpck and V4HI via pshufh. */
16891 if (d->vmode != V8QImode)
16893 if (!d->one_vector_p)
16897 for (i = 1; i < 8; ++i)
16898 if (d->perm[i] != elt)
16904 /* With one interleave we put two of the desired element adjacent. */
16905 t0 = gen_reg_rtx (V8QImode);
16907 emit_insn (gen_loongson_punpcklbh (t0, d->op0, d->op0));
16909 emit_insn (gen_loongson_punpckhbh (t0, d->op0, d->op0));
16911 /* Shuffle that one HImode element into all locations. */
16914 t1 = gen_reg_rtx (V4HImode);
16915 emit_insn (gen_loongson_pshufh (t1, gen_lowpart (V4HImode, t0),
16916 force_reg (SImode, GEN_INT (elt))));
16918 emit_move_insn (d->target, gen_lowpart (V8QImode, t1));
16923 mips_expand_vec_perm_const_1 (struct expand_vec_perm_d *d)
16925 unsigned int i, nelt = d->nelt;
16926 unsigned char perm2[MAX_VECT_LEN];
16928 if (d->one_vector_p)
16930 /* Try interleave with alternating operands. */
16931 memcpy (perm2, d->perm, sizeof(perm2));
16932 for (i = 1; i < nelt; i += 2)
16934 if (mips_expand_vselect_vconcat (d->target, d->op0, d->op1, perm2, nelt))
16939 if (mips_expand_vselect_vconcat (d->target, d->op0, d->op1,
16943 /* Try again with swapped operands. */
16944 for (i = 0; i < nelt; ++i)
16945 perm2[i] = (d->perm[i] + nelt) & (2 * nelt - 1);
16946 if (mips_expand_vselect_vconcat (d->target, d->op1, d->op0, perm2, nelt))
16950 if (mips_expand_vpc_loongson_even_odd (d))
16952 if (mips_expand_vpc_loongson_pshufh (d))
16954 if (mips_expand_vpc_loongson_bcast (d))
16959 /* Expand a vec_perm_const pattern. */
16962 mips_expand_vec_perm_const (rtx operands[4])
16964 struct expand_vec_perm_d d;
16965 int i, nelt, which;
16966 unsigned char orig_perm[MAX_VECT_LEN];
16970 d.target = operands[0];
16971 d.op0 = operands[1];
16972 d.op1 = operands[2];
16975 d.vmode = GET_MODE (d.target);
16976 gcc_assert (VECTOR_MODE_P (d.vmode));
16977 d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
16978 d.testing_p = false;
16980 for (i = which = 0; i < nelt; ++i)
16982 rtx e = XVECEXP (sel, 0, i);
16983 int ei = INTVAL (e) & (2 * nelt - 1);
16984 which |= (ei < nelt ? 1 : 2);
16987 memcpy (d.perm, orig_perm, MAX_VECT_LEN);
16995 d.one_vector_p = false;
16996 if (!rtx_equal_p (d.op0, d.op1))
17001 for (i = 0; i < nelt; ++i)
17002 d.perm[i] &= nelt - 1;
17004 d.one_vector_p = true;
17009 d.one_vector_p = true;
17013 ok = mips_expand_vec_perm_const_1 (&d);
17015 /* If we were given a two-vector permutation which just happened to
17016 have both input vectors equal, we folded this into a one-vector
17017 permutation. There are several loongson patterns that are matched
17018 via direct vec_select+vec_concat expansion, but we do not have
17019 support in mips_expand_vec_perm_const_1 to guess the adjustment
17020 that should be made for a single operand. Just try again with
17021 the original permutation. */
17022 if (!ok && which == 3)
17024 d.op0 = operands[1];
17025 d.op1 = operands[2];
17026 d.one_vector_p = false;
17027 memcpy (d.perm, orig_perm, MAX_VECT_LEN);
17028 ok = mips_expand_vec_perm_const_1 (&d);
17034 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST_OK. */
17037 mips_vectorize_vec_perm_const_ok (enum machine_mode vmode,
17038 const unsigned char *sel)
17040 struct expand_vec_perm_d d;
17041 unsigned int i, nelt, which;
17045 d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
17046 d.testing_p = true;
17047 memcpy (d.perm, sel, nelt);
17049 /* Categorize the set of elements in the selector. */
17050 for (i = which = 0; i < nelt; ++i)
17052 unsigned char e = d.perm[i];
17053 gcc_assert (e < 2 * nelt);
17054 which |= (e < nelt ? 1 : 2);
17057 /* For all elements from second vector, fold the elements to first. */
17059 for (i = 0; i < nelt; ++i)
17062 /* Check whether the mask can be applied to the vector type. */
17063 d.one_vector_p = (which != 3);
17065 d.target = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 1);
17066 d.op1 = d.op0 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 2);
17067 if (!d.one_vector_p)
17068 d.op1 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 3);
17071 ret = mips_expand_vec_perm_const_1 (&d);
17077 /* Expand an integral vector unpack operation. */
17080 mips_expand_vec_unpack (rtx operands[2], bool unsigned_p, bool high_p)
17082 enum machine_mode imode = GET_MODE (operands[1]);
17083 rtx (*unpack) (rtx, rtx, rtx);
17084 rtx (*cmpgt) (rtx, rtx, rtx);
17085 rtx tmp, dest, zero;
17091 unpack = gen_loongson_punpckhbh;
17093 unpack = gen_loongson_punpcklbh;
17094 cmpgt = gen_loongson_pcmpgtb;
17098 unpack = gen_loongson_punpckhhw;
17100 unpack = gen_loongson_punpcklhw;
17101 cmpgt = gen_loongson_pcmpgth;
17104 gcc_unreachable ();
17107 zero = force_reg (imode, CONST0_RTX (imode));
17112 tmp = gen_reg_rtx (imode);
17113 emit_insn (cmpgt (tmp, zero, operands[1]));
17116 dest = gen_reg_rtx (imode);
17117 emit_insn (unpack (dest, operands[1], tmp));
17119 emit_move_insn (operands[0], gen_lowpart (GET_MODE (operands[0]), dest));
17122 /* A subroutine of mips_expand_vec_init, match constant vector elements. */
17125 mips_constant_elt_p (rtx x)
17127 return CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE;
17130 /* A subroutine of mips_expand_vec_init, expand via broadcast. */
17133 mips_expand_vi_broadcast (enum machine_mode vmode, rtx target, rtx elt)
17135 struct expand_vec_perm_d d;
17139 if (elt != const0_rtx)
17140 elt = force_reg (GET_MODE_INNER (vmode), elt);
17142 elt = gen_lowpart (DImode, elt);
17144 t1 = gen_reg_rtx (vmode);
17148 emit_insn (gen_loongson_vec_init1_v8qi (t1, elt));
17151 emit_insn (gen_loongson_vec_init1_v4hi (t1, elt));
17154 gcc_unreachable ();
17157 memset (&d, 0, sizeof (d));
17162 d.nelt = GET_MODE_NUNITS (vmode);
17163 d.one_vector_p = true;
17165 ok = mips_expand_vec_perm_const_1 (&d);
17169 /* A subroutine of mips_expand_vec_init, replacing all of the non-constant
17170 elements of VALS with zeros, copy the constant vector to TARGET. */
17173 mips_expand_vi_constant (enum machine_mode vmode, unsigned nelt,
17174 rtx target, rtx vals)
17176 rtvec vec = shallow_copy_rtvec (XVEC (vals, 0));
17179 for (i = 0; i < nelt; ++i)
17181 if (!mips_constant_elt_p (RTVEC_ELT (vec, i)))
17182 RTVEC_ELT (vec, i) = const0_rtx;
17185 emit_move_insn (target, gen_rtx_CONST_VECTOR (vmode, vec));
17189 /* A subroutine of mips_expand_vec_init, expand via pinsrh. */
17192 mips_expand_vi_loongson_one_pinsrh (rtx target, rtx vals, unsigned one_var)
17194 mips_expand_vi_constant (V4HImode, 4, target, vals);
17196 emit_insn (gen_vec_setv4hi (target, target, XVECEXP (vals, 0, one_var),
17197 GEN_INT (one_var)));
17200 /* A subroutine of mips_expand_vec_init, expand anything via memory. */
17203 mips_expand_vi_general (enum machine_mode vmode, enum machine_mode imode,
17204 unsigned nelt, unsigned nvar, rtx target, rtx vals)
17206 rtx mem = assign_stack_temp (vmode, GET_MODE_SIZE (vmode));
17207 unsigned int i, isize = GET_MODE_SIZE (imode);
17210 mips_expand_vi_constant (vmode, nelt, mem, vals);
17212 for (i = 0; i < nelt; ++i)
17214 rtx x = XVECEXP (vals, 0, i);
17215 if (!mips_constant_elt_p (x))
17216 emit_move_insn (adjust_address (mem, imode, i * isize), x);
17219 emit_move_insn (target, mem);
17222 /* Expand a vector initialization. */
17225 mips_expand_vector_init (rtx target, rtx vals)
17227 enum machine_mode vmode = GET_MODE (target);
17228 enum machine_mode imode = GET_MODE_INNER (vmode);
17229 unsigned i, nelt = GET_MODE_NUNITS (vmode);
17230 unsigned nvar = 0, one_var = -1u;
17231 bool all_same = true;
17234 for (i = 0; i < nelt; ++i)
17236 x = XVECEXP (vals, 0, i);
17237 if (!mips_constant_elt_p (x))
17238 nvar++, one_var = i;
17239 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
17243 /* Load constants from the pool, or whatever's handy. */
17246 emit_move_insn (target, gen_rtx_CONST_VECTOR (vmode, XVEC (vals, 0)));
17250 /* For two-part initialization, always use CONCAT. */
17253 rtx op0 = force_reg (imode, XVECEXP (vals, 0, 0));
17254 rtx op1 = force_reg (imode, XVECEXP (vals, 0, 1));
17255 x = gen_rtx_VEC_CONCAT (vmode, op0, op1);
17256 emit_insn (gen_rtx_SET (VOIDmode, target, x));
17260 /* Loongson is the only cpu with vectors with more elements. */
17261 gcc_assert (TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS);
17263 /* If all values are identical, broadcast the value. */
17266 mips_expand_vi_broadcast (vmode, target, XVECEXP (vals, 0, 0));
17270 /* If we've only got one non-variable V4HImode, use PINSRH. */
17271 if (nvar == 1 && vmode == V4HImode)
17273 mips_expand_vi_loongson_one_pinsrh (target, vals, one_var);
17277 mips_expand_vi_general (vmode, imode, nelt, nvar, target, vals);
17280 /* Expand a vector reduction. */
17283 mips_expand_vec_reduc (rtx target, rtx in, rtx (*gen)(rtx, rtx, rtx))
17285 enum machine_mode vmode = GET_MODE (in);
17286 unsigned char perm2[2];
17287 rtx last, next, fold, x;
17291 fold = gen_reg_rtx (vmode);
17295 /* Use PUL/PLU to produce { L, H } op { H, L }.
17296 By reversing the pair order, rather than a pure interleave high,
17297 we avoid erroneous exceptional conditions that we might otherwise
17298 produce from the computation of H op H. */
17301 ok = mips_expand_vselect_vconcat (fold, last, last, perm2, 2);
17306 /* Use interleave to produce { H, L } op { H, H }. */
17307 emit_insn (gen_loongson_punpckhwd (fold, last, last));
17311 /* Perform the first reduction with interleave,
17312 and subsequent reductions with shifts. */
17313 emit_insn (gen_loongson_punpckhwd_hi (fold, last, last));
17315 next = gen_reg_rtx (vmode);
17316 emit_insn (gen (next, last, fold));
17319 fold = gen_reg_rtx (vmode);
17320 x = force_reg (SImode, GEN_INT (16));
17321 emit_insn (gen_vec_shr_v4hi (fold, last, x));
17325 emit_insn (gen_loongson_punpckhwd_qi (fold, last, last));
17327 next = gen_reg_rtx (vmode);
17328 emit_insn (gen (next, last, fold));
17331 fold = gen_reg_rtx (vmode);
17332 x = force_reg (SImode, GEN_INT (16));
17333 emit_insn (gen_vec_shr_v8qi (fold, last, x));
17335 next = gen_reg_rtx (vmode);
17336 emit_insn (gen (next, last, fold));
17339 fold = gen_reg_rtx (vmode);
17340 x = force_reg (SImode, GEN_INT (8));
17341 emit_insn (gen_vec_shr_v8qi (fold, last, x));
17345 gcc_unreachable ();
17348 emit_insn (gen (target, last, fold));
17351 /* Expand a vector minimum/maximum. */
17354 mips_expand_vec_minmax (rtx target, rtx op0, rtx op1,
17355 rtx (*cmp) (rtx, rtx, rtx), bool min_p)
17357 enum machine_mode vmode = GET_MODE (target);
17360 tc = gen_reg_rtx (vmode);
17361 t0 = gen_reg_rtx (vmode);
17362 t1 = gen_reg_rtx (vmode);
17365 emit_insn (cmp (tc, op0, op1));
17367 x = gen_rtx_AND (vmode, tc, (min_p ? op1 : op0));
17368 emit_insn (gen_rtx_SET (VOIDmode, t0, x));
17370 x = gen_rtx_NOT (vmode, tc);
17371 x = gen_rtx_AND (vmode, x, (min_p ? op0 : op1));
17372 emit_insn (gen_rtx_SET (VOIDmode, t1, x));
17374 x = gen_rtx_IOR (vmode, t0, t1);
17375 emit_insn (gen_rtx_SET (VOIDmode, target, x));
17378 /* Initialize the GCC target structure. */
17379 #undef TARGET_ASM_ALIGNED_HI_OP
17380 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
17381 #undef TARGET_ASM_ALIGNED_SI_OP
17382 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
17383 #undef TARGET_ASM_ALIGNED_DI_OP
17384 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
17386 #undef TARGET_OPTION_OVERRIDE
17387 #define TARGET_OPTION_OVERRIDE mips_option_override
17389 #undef TARGET_LEGITIMIZE_ADDRESS
17390 #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
17392 #undef TARGET_ASM_FUNCTION_PROLOGUE
17393 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
17394 #undef TARGET_ASM_FUNCTION_EPILOGUE
17395 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
17396 #undef TARGET_ASM_SELECT_RTX_SECTION
17397 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
17398 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
17399 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
17401 #undef TARGET_SCHED_INIT
17402 #define TARGET_SCHED_INIT mips_sched_init
17403 #undef TARGET_SCHED_REORDER
17404 #define TARGET_SCHED_REORDER mips_sched_reorder
17405 #undef TARGET_SCHED_REORDER2
17406 #define TARGET_SCHED_REORDER2 mips_sched_reorder2
17407 #undef TARGET_SCHED_VARIABLE_ISSUE
17408 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
17409 #undef TARGET_SCHED_ADJUST_COST
17410 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
17411 #undef TARGET_SCHED_ISSUE_RATE
17412 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
17413 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
17414 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
17415 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
17416 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
17417 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
17418 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
17419 mips_multipass_dfa_lookahead
17420 #undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
17421 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
17422 mips_small_register_classes_for_mode_p
17424 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
17425 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
17427 #undef TARGET_INSERT_ATTRIBUTES
17428 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
17429 #undef TARGET_MERGE_DECL_ATTRIBUTES
17430 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
17431 #undef TARGET_SET_CURRENT_FUNCTION
17432 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
17434 #undef TARGET_VALID_POINTER_MODE
17435 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
17436 #undef TARGET_REGISTER_MOVE_COST
17437 #define TARGET_REGISTER_MOVE_COST mips_register_move_cost
17438 #undef TARGET_MEMORY_MOVE_COST
17439 #define TARGET_MEMORY_MOVE_COST mips_memory_move_cost
17440 #undef TARGET_RTX_COSTS
17441 #define TARGET_RTX_COSTS mips_rtx_costs
17442 #undef TARGET_ADDRESS_COST
17443 #define TARGET_ADDRESS_COST mips_address_cost
17445 #undef TARGET_IN_SMALL_DATA_P
17446 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
17448 #undef TARGET_MACHINE_DEPENDENT_REORG
17449 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
17451 #undef TARGET_PREFERRED_RELOAD_CLASS
17452 #define TARGET_PREFERRED_RELOAD_CLASS mips_preferred_reload_class
17454 #undef TARGET_ASM_FILE_START
17455 #define TARGET_ASM_FILE_START mips_file_start
17456 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
17457 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
17458 #undef TARGET_ASM_CODE_END
17459 #define TARGET_ASM_CODE_END mips_code_end
17461 #undef TARGET_INIT_LIBFUNCS
17462 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
17464 #undef TARGET_BUILD_BUILTIN_VA_LIST
17465 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
17466 #undef TARGET_EXPAND_BUILTIN_VA_START
17467 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
17468 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
17469 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
17471 #undef TARGET_PROMOTE_FUNCTION_MODE
17472 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
17473 #undef TARGET_PROMOTE_PROTOTYPES
17474 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
17476 #undef TARGET_FUNCTION_VALUE
17477 #define TARGET_FUNCTION_VALUE mips_function_value
17478 #undef TARGET_LIBCALL_VALUE
17479 #define TARGET_LIBCALL_VALUE mips_libcall_value
17480 #undef TARGET_FUNCTION_VALUE_REGNO_P
17481 #define TARGET_FUNCTION_VALUE_REGNO_P mips_function_value_regno_p
17482 #undef TARGET_RETURN_IN_MEMORY
17483 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
17484 #undef TARGET_RETURN_IN_MSB
17485 #define TARGET_RETURN_IN_MSB mips_return_in_msb
17487 #undef TARGET_ASM_OUTPUT_MI_THUNK
17488 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
17489 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
17490 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
17492 #undef TARGET_PRINT_OPERAND
17493 #define TARGET_PRINT_OPERAND mips_print_operand
17494 #undef TARGET_PRINT_OPERAND_ADDRESS
17495 #define TARGET_PRINT_OPERAND_ADDRESS mips_print_operand_address
17496 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
17497 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mips_print_operand_punct_valid_p
17499 #undef TARGET_SETUP_INCOMING_VARARGS
17500 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
17501 #undef TARGET_STRICT_ARGUMENT_NAMING
17502 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
17503 #undef TARGET_MUST_PASS_IN_STACK
17504 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
17505 #undef TARGET_PASS_BY_REFERENCE
17506 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
17507 #undef TARGET_CALLEE_COPIES
17508 #define TARGET_CALLEE_COPIES mips_callee_copies
17509 #undef TARGET_ARG_PARTIAL_BYTES
17510 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
17511 #undef TARGET_FUNCTION_ARG
17512 #define TARGET_FUNCTION_ARG mips_function_arg
17513 #undef TARGET_FUNCTION_ARG_ADVANCE
17514 #define TARGET_FUNCTION_ARG_ADVANCE mips_function_arg_advance
17515 #undef TARGET_FUNCTION_ARG_BOUNDARY
17516 #define TARGET_FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
17518 #undef TARGET_MODE_REP_EXTENDED
17519 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
17521 #undef TARGET_VECTOR_MODE_SUPPORTED_P
17522 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
17524 #undef TARGET_SCALAR_MODE_SUPPORTED_P
17525 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
17527 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
17528 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE mips_preferred_simd_mode
17530 #undef TARGET_INIT_BUILTINS
17531 #define TARGET_INIT_BUILTINS mips_init_builtins
17532 #undef TARGET_BUILTIN_DECL
17533 #define TARGET_BUILTIN_DECL mips_builtin_decl
17534 #undef TARGET_EXPAND_BUILTIN
17535 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
17537 #undef TARGET_HAVE_TLS
17538 #define TARGET_HAVE_TLS HAVE_AS_TLS
17540 #undef TARGET_CANNOT_FORCE_CONST_MEM
17541 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
17543 #undef TARGET_LEGITIMATE_CONSTANT_P
17544 #define TARGET_LEGITIMATE_CONSTANT_P mips_legitimate_constant_p
17546 #undef TARGET_ENCODE_SECTION_INFO
17547 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
17549 #undef TARGET_ATTRIBUTE_TABLE
17550 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
17551 /* All our function attributes are related to how out-of-line copies should
17552 be compiled or called. They don't in themselves prevent inlining. */
17553 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
17554 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
17556 #undef TARGET_EXTRA_LIVE_ON_ENTRY
17557 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
17559 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
17560 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
17561 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
17562 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
17564 #undef TARGET_COMP_TYPE_ATTRIBUTES
17565 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
17567 #ifdef HAVE_AS_DTPRELWORD
17568 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
17569 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
17571 #undef TARGET_DWARF_REGISTER_SPAN
17572 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
17574 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
17575 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
17577 #undef TARGET_LEGITIMATE_ADDRESS_P
17578 #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p
17580 #undef TARGET_FRAME_POINTER_REQUIRED
17581 #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required
17583 #undef TARGET_CAN_ELIMINATE
17584 #define TARGET_CAN_ELIMINATE mips_can_eliminate
17586 #undef TARGET_CONDITIONAL_REGISTER_USAGE
17587 #define TARGET_CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage
17589 #undef TARGET_TRAMPOLINE_INIT
17590 #define TARGET_TRAMPOLINE_INIT mips_trampoline_init
17592 #undef TARGET_ASM_OUTPUT_SOURCE_FILENAME
17593 #define TARGET_ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
17595 #undef TARGET_SHIFT_TRUNCATION_MASK
17596 #define TARGET_SHIFT_TRUNCATION_MASK mips_shift_truncation_mask
17598 #undef TARGET_PREPARE_PCH_SAVE
17599 #define TARGET_PREPARE_PCH_SAVE mips_prepare_pch_save
17601 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
17602 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK mips_vectorize_vec_perm_const_ok
17604 struct gcc_target targetm = TARGET_INITIALIZER;
17606 #include "gt-mips.h"