1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989-2014 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky, lich@inria.inria.fr.
4 Changes by Michael Meissner, meissner@osf.org.
5 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 Brendan Eich, brendan@microunity.com.
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
30 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
38 #include "stringpool.h"
39 #include "stor-layout.h"
50 #include "hash-table.h"
53 #include "target-def.h"
54 #include "common/common-target.h"
55 #include "langhooks.h"
56 #include "sched-int.h"
57 #include "pointer-set.h"
59 #include "basic-block.h"
60 #include "tree-ssa-alias.h"
61 #include "internal-fn.h"
62 #include "gimple-fold.h"
64 #include "gimple-expr.h"
69 #include "diagnostic.h"
70 #include "target-globals.h"
72 #include "tree-pass.h"
75 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
76 #define UNSPEC_ADDRESS_P(X) \
77 (GET_CODE (X) == UNSPEC \
78 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
79 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
81 /* Extract the symbol or label from UNSPEC wrapper X. */
82 #define UNSPEC_ADDRESS(X) \
85 /* Extract the symbol type from UNSPEC wrapper X. */
86 #define UNSPEC_ADDRESS_TYPE(X) \
87 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
89 /* The maximum distance between the top of the stack frame and the
90 value $sp has when we save and restore registers.
92 The value for normal-mode code must be a SMALL_OPERAND and must
93 preserve the maximum stack alignment. We therefore use a value
94 of 0x7ff0 in this case.
96 microMIPS LWM and SWM support 12-bit offsets (from -0x800 to 0x7ff),
97 so we use a maximum of 0x7f0 for TARGET_MICROMIPS.
99 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
100 up to 0x7f8 bytes and can usually save or restore all the registers
101 that we need to save or restore. (Note that we can only use these
102 instructions for o32, for which the stack alignment is 8 bytes.)
104 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
105 RESTORE are not available. We can then use unextended instructions
106 to save and restore registers, and to allocate and deallocate the top
107 part of the frame. */
108 #define MIPS_MAX_FIRST_STACK_STEP \
109 (!TARGET_COMPRESSION ? 0x7ff0 \
110 : TARGET_MICROMIPS || GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
111 : TARGET_64BIT ? 0x100 : 0x400)
113 /* True if INSN is a mips.md pattern or asm statement. */
114 /* ??? This test exists through the compiler, perhaps it should be
116 #define USEFUL_INSN_P(INSN) \
117 (NONDEBUG_INSN_P (INSN) \
118 && GET_CODE (PATTERN (INSN)) != USE \
119 && GET_CODE (PATTERN (INSN)) != CLOBBER)
121 /* If INSN is a delayed branch sequence, return the first instruction
122 in the sequence, otherwise return INSN itself. */
123 #define SEQ_BEGIN(INSN) \
124 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
125 ? XVECEXP (PATTERN (INSN), 0, 0) \
128 /* Likewise for the last instruction in a delayed branch sequence. */
129 #define SEQ_END(INSN) \
130 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
131 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
134 /* Execute the following loop body with SUBINSN set to each instruction
135 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
136 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
137 for ((SUBINSN) = SEQ_BEGIN (INSN); \
138 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
139 (SUBINSN) = NEXT_INSN (SUBINSN))
141 /* True if bit BIT is set in VALUE. */
142 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
144 /* Return the opcode for a ptr_mode load of the form:
146 l[wd] DEST, OFFSET(BASE). */
147 #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \
148 (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \
153 /* Return the opcode to move register SRC into register DEST. */
154 #define MIPS_MOVE(DEST, SRC) \
155 ((TARGET_64BIT ? 0x2d : 0x21) \
159 /* Return the opcode for:
162 #define MIPS_LUI(DEST, VALUE) \
163 ((0xf << 26) | ((DEST) << 16) | (VALUE))
165 /* Return the opcode to jump to register DEST. */
166 #define MIPS_JR(DEST) \
167 (((DEST) << 21) | 0x8)
169 /* Return the opcode for:
171 bal . + (1 + OFFSET) * 4. */
172 #define MIPS_BAL(OFFSET) \
173 ((0x1 << 26) | (0x11 << 16) | (OFFSET))
175 /* Return the usual opcode for a nop. */
178 /* Classifies an address.
181 A natural register + offset address. The register satisfies
182 mips_valid_base_register_p and the offset is a const_arith_operand.
185 A LO_SUM rtx. The first operand is a valid base register and
186 the second operand is a symbolic address.
189 A signed 16-bit constant address.
192 A constant symbolic address. */
193 enum mips_address_type {
200 /* Macros to create an enumeration identifier for a function prototype. */
201 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
202 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
203 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
204 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
206 /* Classifies the prototype of a built-in function. */
207 enum mips_function_type {
208 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
209 #include "config/mips/mips-ftypes.def"
210 #undef DEF_MIPS_FTYPE
214 /* Specifies how a built-in function should be converted into rtl. */
215 enum mips_builtin_type {
216 /* The function corresponds directly to an .md pattern. The return
217 value is mapped to operand 0 and the arguments are mapped to
218 operands 1 and above. */
221 /* The function corresponds directly to an .md pattern. There is no return
222 value and the arguments are mapped to operands 0 and above. */
223 MIPS_BUILTIN_DIRECT_NO_TARGET,
225 /* The function corresponds to a comparison instruction followed by
226 a mips_cond_move_tf_ps pattern. The first two arguments are the
227 values to compare and the second two arguments are the vector
228 operands for the movt.ps or movf.ps instruction (in assembly order). */
232 /* The function corresponds to a V2SF comparison instruction. Operand 0
233 of this instruction is the result of the comparison, which has mode
234 CCV2 or CCV4. The function arguments are mapped to operands 1 and
235 above. The function's return value is an SImode boolean that is
236 true under the following conditions:
238 MIPS_BUILTIN_CMP_ANY: one of the registers is true
239 MIPS_BUILTIN_CMP_ALL: all of the registers are true
240 MIPS_BUILTIN_CMP_LOWER: the first register is true
241 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
242 MIPS_BUILTIN_CMP_ANY,
243 MIPS_BUILTIN_CMP_ALL,
244 MIPS_BUILTIN_CMP_UPPER,
245 MIPS_BUILTIN_CMP_LOWER,
247 /* As above, but the instruction only sets a single $fcc register. */
248 MIPS_BUILTIN_CMP_SINGLE,
250 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
251 MIPS_BUILTIN_BPOSGE32
254 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
255 #define MIPS_FP_CONDITIONS(MACRO) \
273 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
274 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
275 enum mips_fp_condition {
276 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
279 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
280 #define STRINGIFY(X) #X
281 static const char *const mips_fp_conditions[] = {
282 MIPS_FP_CONDITIONS (STRINGIFY)
285 /* Tuning information that is automatically derived from other sources
286 (such as the scheduler). */
288 /* The architecture and tuning settings that this structure describes. */
292 /* True if this structure describes MIPS16 settings. */
295 /* True if the structure has been initialized. */
298 /* True if "MULT $0, $0" is preferable to "MTLO $0; MTHI $0"
299 when optimizing for speed. */
300 bool fast_mult_zero_zero_p;
303 /* Information about a function's frame layout. */
304 struct GTY(()) mips_frame_info {
305 /* The size of the frame in bytes. */
306 HOST_WIDE_INT total_size;
308 /* The number of bytes allocated to variables. */
309 HOST_WIDE_INT var_size;
311 /* The number of bytes allocated to outgoing function arguments. */
312 HOST_WIDE_INT args_size;
314 /* The number of bytes allocated to the .cprestore slot, or 0 if there
316 HOST_WIDE_INT cprestore_size;
318 /* Bit X is set if the function saves or restores GPR X. */
321 /* Likewise FPR X. */
324 /* Likewise doubleword accumulator X ($acX). */
325 unsigned int acc_mask;
327 /* The number of GPRs, FPRs, doubleword accumulators and COP0
331 unsigned int num_acc;
332 unsigned int num_cop0_regs;
334 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
335 save slots from the top of the frame, or zero if no such slots are
337 HOST_WIDE_INT gp_save_offset;
338 HOST_WIDE_INT fp_save_offset;
339 HOST_WIDE_INT acc_save_offset;
340 HOST_WIDE_INT cop0_save_offset;
342 /* Likewise, but giving offsets from the bottom of the frame. */
343 HOST_WIDE_INT gp_sp_offset;
344 HOST_WIDE_INT fp_sp_offset;
345 HOST_WIDE_INT acc_sp_offset;
346 HOST_WIDE_INT cop0_sp_offset;
348 /* Similar, but the value passed to _mcount. */
349 HOST_WIDE_INT ra_fp_offset;
351 /* The offset of arg_pointer_rtx from the bottom of the frame. */
352 HOST_WIDE_INT arg_pointer_offset;
354 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
355 HOST_WIDE_INT hard_frame_pointer_offset;
358 struct GTY(()) machine_function {
359 /* The next floating-point condition-code register to allocate
360 for ISA_HAS_8CC targets, relative to ST_REG_FIRST. */
361 unsigned int next_fcc;
363 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
364 rtx mips16_gp_pseudo_rtx;
366 /* The number of extra stack bytes taken up by register varargs.
367 This area is allocated by the callee at the very top of the frame. */
370 /* The current frame information, calculated by mips_compute_frame_info. */
371 struct mips_frame_info frame;
373 /* The register to use as the function's global pointer, or INVALID_REGNUM
374 if the function doesn't need one. */
375 unsigned int global_pointer;
377 /* How many instructions it takes to load a label into $AT, or 0 if
378 this property hasn't yet been calculated. */
379 unsigned int load_label_num_insns;
381 /* True if mips_adjust_insn_length should ignore an instruction's
383 bool ignore_hazard_length_p;
385 /* True if the whole function is suitable for .set noreorder and
387 bool all_noreorder_p;
389 /* True if the function has "inflexible" and "flexible" references
390 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
391 and mips_cfun_has_flexible_gp_ref_p for details. */
392 bool has_inflexible_gp_insn_p;
393 bool has_flexible_gp_insn_p;
395 /* True if the function's prologue must load the global pointer
396 value into pic_offset_table_rtx and store the same value in
397 the function's cprestore slot (if any). Even if this value
398 is currently false, we may decide to set it to true later;
399 see mips_must_initialize_gp_p () for details. */
400 bool must_initialize_gp_p;
402 /* True if the current function must restore $gp after any potential
403 clobber. This value is only meaningful during the first post-epilogue
404 split_insns pass; see mips_must_initialize_gp_p () for details. */
405 bool must_restore_gp_when_clobbered_p;
407 /* True if this is an interrupt handler. */
408 bool interrupt_handler_p;
410 /* True if this is an interrupt handler that uses shadow registers. */
411 bool use_shadow_register_set_p;
413 /* True if this is an interrupt handler that should keep interrupts
415 bool keep_interrupts_masked_p;
417 /* True if this is an interrupt handler that should use DERET
419 bool use_debug_exception_return_p;
422 /* Information about a single argument. */
423 struct mips_arg_info {
424 /* True if the argument is passed in a floating-point register, or
425 would have been if we hadn't run out of registers. */
428 /* The number of words passed in registers, rounded up. */
429 unsigned int reg_words;
431 /* For EABI, the offset of the first register from GP_ARG_FIRST or
432 FP_ARG_FIRST. For other ABIs, the offset of the first register from
433 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
434 comment for details).
436 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
438 unsigned int reg_offset;
440 /* The number of words that must be passed on the stack, rounded up. */
441 unsigned int stack_words;
443 /* The offset from the start of the stack overflow area of the argument's
444 first stack word. Only meaningful when STACK_WORDS is nonzero. */
445 unsigned int stack_offset;
448 /* Information about an address described by mips_address_type.
454 REG is the base register and OFFSET is the constant offset.
457 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
458 is the type of symbol it references.
461 SYMBOL_TYPE is the type of symbol that the address references. */
462 struct mips_address_info {
463 enum mips_address_type type;
466 enum mips_symbol_type symbol_type;
469 /* One stage in a constant building sequence. These sequences have
473 A = A CODE[1] VALUE[1]
474 A = A CODE[2] VALUE[2]
477 where A is an accumulator, each CODE[i] is a binary rtl operation
478 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
479 struct mips_integer_op {
481 unsigned HOST_WIDE_INT value;
484 /* The largest number of operations needed to load an integer constant.
485 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
486 When the lowest bit is clear, we can try, but reject a sequence with
487 an extra SLL at the end. */
488 #define MIPS_MAX_INTEGER_OPS 7
490 /* Information about a MIPS16e SAVE or RESTORE instruction. */
491 struct mips16e_save_restore_info {
492 /* The number of argument registers saved by a SAVE instruction.
493 0 for RESTORE instructions. */
496 /* Bit X is set if the instruction saves or restores GPR X. */
499 /* The total number of bytes to allocate. */
503 /* Costs of various operations on the different architectures. */
505 struct mips_rtx_cost_data
507 unsigned short fp_add;
508 unsigned short fp_mult_sf;
509 unsigned short fp_mult_df;
510 unsigned short fp_div_sf;
511 unsigned short fp_div_df;
512 unsigned short int_mult_si;
513 unsigned short int_mult_di;
514 unsigned short int_div_si;
515 unsigned short int_div_di;
516 unsigned short branch_cost;
517 unsigned short memory_latency;
520 /* Global variables for machine-dependent things. */
522 /* The -G setting, or the configuration's default small-data limit if
523 no -G option is given. */
524 static unsigned int mips_small_data_threshold;
526 /* The number of file directives written by mips_output_filename. */
527 int num_source_filenames;
529 /* The name that appeared in the last .file directive written by
530 mips_output_filename, or "" if mips_output_filename hasn't
531 written anything yet. */
532 const char *current_function_file = "";
534 /* Arrays that map GCC register numbers to debugger register numbers. */
535 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
536 int mips_dwarf_regno[FIRST_PSEUDO_REGISTER];
538 /* Information about the current function's epilogue, used only while
541 /* A list of queued REG_CFA_RESTORE notes. */
544 /* The CFA is currently defined as CFA_REG + CFA_OFFSET. */
546 HOST_WIDE_INT cfa_offset;
548 /* The offset of the CFA from the stack pointer while restoring
550 HOST_WIDE_INT cfa_restore_sp_offset;
553 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
554 struct mips_asm_switch mips_noreorder = { "reorder", 0 };
555 struct mips_asm_switch mips_nomacro = { "macro", 0 };
556 struct mips_asm_switch mips_noat = { "at", 0 };
558 /* True if we're writing out a branch-likely instruction rather than a
560 static bool mips_branch_likely;
562 /* The current instruction-set architecture. */
563 enum processor mips_arch;
564 const struct mips_cpu_info *mips_arch_info;
566 /* The processor that we should tune the code for. */
567 enum processor mips_tune;
568 const struct mips_cpu_info *mips_tune_info;
570 /* The ISA level associated with mips_arch. */
573 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
574 static const struct mips_cpu_info *mips_isa_option_info;
576 /* Which cost information to use. */
577 static const struct mips_rtx_cost_data *mips_cost;
579 /* The ambient target flags, excluding MASK_MIPS16. */
580 static int mips_base_target_flags;
582 /* The default compression mode. */
583 unsigned int mips_base_compression_flags;
585 /* The ambient values of other global variables. */
586 static int mips_base_schedule_insns; /* flag_schedule_insns */
587 static int mips_base_reorder_blocks_and_partition; /* flag_reorder... */
588 static int mips_base_move_loop_invariants; /* flag_move_loop_invariants */
589 static int mips_base_align_loops; /* align_loops */
590 static int mips_base_align_jumps; /* align_jumps */
591 static int mips_base_align_functions; /* align_functions */
593 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
594 bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
596 /* Index C is true if character C is a valid PRINT_OPERAND punctation
598 static bool mips_print_operand_punct[256];
600 static GTY (()) int mips_output_filename_first_time = 1;
602 /* mips_split_p[X] is true if symbols of type X can be split by
603 mips_split_symbol. */
604 bool mips_split_p[NUM_SYMBOL_TYPES];
606 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
607 can be split by mips_split_symbol. */
608 bool mips_split_hi_p[NUM_SYMBOL_TYPES];
610 /* mips_use_pcrel_pool_p[X] is true if symbols of type X should be
611 forced into a PC-relative constant pool. */
612 bool mips_use_pcrel_pool_p[NUM_SYMBOL_TYPES];
614 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
615 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
616 if they are matched by a special .md file pattern. */
617 const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
619 /* Likewise for HIGHs. */
620 const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
622 /* Target state for MIPS16. */
623 struct target_globals *mips16_globals;
625 /* Cached value of can_issue_more. This is cached in mips_variable_issue hook
626 and returned from mips_sched_reorder2. */
627 static int cached_can_issue_more;
629 /* True if the output uses __mips16_rdhwr. */
630 static bool mips_need_mips16_rdhwr_p;
632 /* Index R is the smallest register class that contains register R. */
633 const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = {
634 LEA_REGS, LEA_REGS, M16_REGS, V1_REG,
635 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
636 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
637 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
638 M16_REGS, M16_REGS, LEA_REGS, LEA_REGS,
639 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
640 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
641 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
642 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
643 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
644 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
645 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
646 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
647 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
648 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
649 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
650 MD0_REG, MD1_REG, NO_REGS, ST_REGS,
651 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
652 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
653 NO_REGS, FRAME_REGS, FRAME_REGS, NO_REGS,
654 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
655 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
656 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
657 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
658 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
659 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
660 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
661 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
662 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
663 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
664 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
665 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
666 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
667 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
668 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
669 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
670 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
671 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
672 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
673 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
674 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
675 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
676 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
677 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
678 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
679 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
680 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
683 /* The value of TARGET_ATTRIBUTE_TABLE. */
684 static const struct attribute_spec mips_attribute_table[] = {
685 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
687 { "long_call", 0, 0, false, true, true, NULL, false },
688 { "far", 0, 0, false, true, true, NULL, false },
689 { "near", 0, 0, false, true, true, NULL, false },
690 /* We would really like to treat "mips16" and "nomips16" as type
691 attributes, but GCC doesn't provide the hooks we need to support
692 the right conversion rules. As declaration attributes, they affect
693 code generation but don't carry other semantics. */
694 { "mips16", 0, 0, true, false, false, NULL, false },
695 { "nomips16", 0, 0, true, false, false, NULL, false },
696 { "micromips", 0, 0, true, false, false, NULL, false },
697 { "nomicromips", 0, 0, true, false, false, NULL, false },
698 { "nocompression", 0, 0, true, false, false, NULL, false },
699 /* Allow functions to be specified as interrupt handlers */
700 { "interrupt", 0, 0, false, true, true, NULL, false },
701 { "use_shadow_register_set", 0, 0, false, true, true, NULL, false },
702 { "keep_interrupts_masked", 0, 0, false, true, true, NULL, false },
703 { "use_debug_exception_return", 0, 0, false, true, true, NULL, false },
704 { NULL, 0, 0, false, false, false, NULL, false }
707 /* A table describing all the processors GCC knows about; see
708 mips-cpus.def for details. */
709 static const struct mips_cpu_info mips_cpu_info_table[] = {
710 #define MIPS_CPU(NAME, CPU, ISA, FLAGS) \
711 { NAME, CPU, ISA, FLAGS },
712 #include "mips-cpus.def"
716 /* Default costs. If these are used for a processor we should look
717 up the actual costs. */
718 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
719 COSTS_N_INSNS (7), /* fp_mult_sf */ \
720 COSTS_N_INSNS (8), /* fp_mult_df */ \
721 COSTS_N_INSNS (23), /* fp_div_sf */ \
722 COSTS_N_INSNS (36), /* fp_div_df */ \
723 COSTS_N_INSNS (10), /* int_mult_si */ \
724 COSTS_N_INSNS (10), /* int_mult_di */ \
725 COSTS_N_INSNS (69), /* int_div_si */ \
726 COSTS_N_INSNS (69), /* int_div_di */ \
727 2, /* branch_cost */ \
728 4 /* memory_latency */
730 /* Floating-point costs for processors without an FPU. Just assume that
731 all floating-point libcalls are very expensive. */
732 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
733 COSTS_N_INSNS (256), /* fp_mult_sf */ \
734 COSTS_N_INSNS (256), /* fp_mult_df */ \
735 COSTS_N_INSNS (256), /* fp_div_sf */ \
736 COSTS_N_INSNS (256) /* fp_div_df */
738 /* Costs to use when optimizing for size. */
739 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size = {
740 COSTS_N_INSNS (1), /* fp_add */
741 COSTS_N_INSNS (1), /* fp_mult_sf */
742 COSTS_N_INSNS (1), /* fp_mult_df */
743 COSTS_N_INSNS (1), /* fp_div_sf */
744 COSTS_N_INSNS (1), /* fp_div_df */
745 COSTS_N_INSNS (1), /* int_mult_si */
746 COSTS_N_INSNS (1), /* int_mult_di */
747 COSTS_N_INSNS (1), /* int_div_si */
748 COSTS_N_INSNS (1), /* int_div_di */
750 4 /* memory_latency */
753 /* Costs to use when optimizing for speed, indexed by processor. */
754 static const struct mips_rtx_cost_data
755 mips_rtx_cost_data[NUM_PROCESSOR_VALUES] = {
757 COSTS_N_INSNS (2), /* fp_add */
758 COSTS_N_INSNS (4), /* fp_mult_sf */
759 COSTS_N_INSNS (5), /* fp_mult_df */
760 COSTS_N_INSNS (12), /* fp_div_sf */
761 COSTS_N_INSNS (19), /* fp_div_df */
762 COSTS_N_INSNS (12), /* int_mult_si */
763 COSTS_N_INSNS (12), /* int_mult_di */
764 COSTS_N_INSNS (35), /* int_div_si */
765 COSTS_N_INSNS (35), /* int_div_di */
767 4 /* memory_latency */
771 COSTS_N_INSNS (6), /* int_mult_si */
772 COSTS_N_INSNS (6), /* int_mult_di */
773 COSTS_N_INSNS (36), /* int_div_si */
774 COSTS_N_INSNS (36), /* int_div_di */
776 4 /* memory_latency */
780 COSTS_N_INSNS (36), /* int_mult_si */
781 COSTS_N_INSNS (36), /* int_mult_di */
782 COSTS_N_INSNS (37), /* int_div_si */
783 COSTS_N_INSNS (37), /* int_div_di */
785 4 /* memory_latency */
789 COSTS_N_INSNS (4), /* int_mult_si */
790 COSTS_N_INSNS (11), /* int_mult_di */
791 COSTS_N_INSNS (36), /* int_div_si */
792 COSTS_N_INSNS (68), /* int_div_di */
794 4 /* memory_latency */
797 COSTS_N_INSNS (4), /* fp_add */
798 COSTS_N_INSNS (4), /* fp_mult_sf */
799 COSTS_N_INSNS (5), /* fp_mult_df */
800 COSTS_N_INSNS (17), /* fp_div_sf */
801 COSTS_N_INSNS (32), /* fp_div_df */
802 COSTS_N_INSNS (4), /* int_mult_si */
803 COSTS_N_INSNS (11), /* int_mult_di */
804 COSTS_N_INSNS (36), /* int_div_si */
805 COSTS_N_INSNS (68), /* int_div_di */
807 4 /* memory_latency */
810 COSTS_N_INSNS (4), /* fp_add */
811 COSTS_N_INSNS (4), /* fp_mult_sf */
812 COSTS_N_INSNS (5), /* fp_mult_df */
813 COSTS_N_INSNS (17), /* fp_div_sf */
814 COSTS_N_INSNS (32), /* fp_div_df */
815 COSTS_N_INSNS (4), /* int_mult_si */
816 COSTS_N_INSNS (7), /* int_mult_di */
817 COSTS_N_INSNS (42), /* int_div_si */
818 COSTS_N_INSNS (72), /* int_div_di */
820 4 /* memory_latency */
824 COSTS_N_INSNS (5), /* int_mult_si */
825 COSTS_N_INSNS (5), /* int_mult_di */
826 COSTS_N_INSNS (41), /* int_div_si */
827 COSTS_N_INSNS (41), /* int_div_di */
829 4 /* memory_latency */
832 COSTS_N_INSNS (8), /* fp_add */
833 COSTS_N_INSNS (8), /* fp_mult_sf */
834 COSTS_N_INSNS (10), /* fp_mult_df */
835 COSTS_N_INSNS (34), /* fp_div_sf */
836 COSTS_N_INSNS (64), /* fp_div_df */
837 COSTS_N_INSNS (5), /* int_mult_si */
838 COSTS_N_INSNS (5), /* int_mult_di */
839 COSTS_N_INSNS (41), /* int_div_si */
840 COSTS_N_INSNS (41), /* int_div_di */
842 4 /* memory_latency */
845 COSTS_N_INSNS (4), /* fp_add */
846 COSTS_N_INSNS (4), /* fp_mult_sf */
847 COSTS_N_INSNS (5), /* fp_mult_df */
848 COSTS_N_INSNS (17), /* fp_div_sf */
849 COSTS_N_INSNS (32), /* fp_div_df */
850 COSTS_N_INSNS (5), /* int_mult_si */
851 COSTS_N_INSNS (5), /* int_mult_di */
852 COSTS_N_INSNS (41), /* int_div_si */
853 COSTS_N_INSNS (41), /* int_div_di */
855 4 /* memory_latency */
859 COSTS_N_INSNS (5), /* int_mult_si */
860 COSTS_N_INSNS (5), /* int_mult_di */
861 COSTS_N_INSNS (41), /* int_div_si */
862 COSTS_N_INSNS (41), /* int_div_di */
864 4 /* memory_latency */
867 COSTS_N_INSNS (8), /* fp_add */
868 COSTS_N_INSNS (8), /* fp_mult_sf */
869 COSTS_N_INSNS (10), /* fp_mult_df */
870 COSTS_N_INSNS (34), /* fp_div_sf */
871 COSTS_N_INSNS (64), /* fp_div_df */
872 COSTS_N_INSNS (5), /* int_mult_si */
873 COSTS_N_INSNS (5), /* int_mult_di */
874 COSTS_N_INSNS (41), /* int_div_si */
875 COSTS_N_INSNS (41), /* int_div_di */
877 4 /* memory_latency */
880 COSTS_N_INSNS (4), /* fp_add */
881 COSTS_N_INSNS (4), /* fp_mult_sf */
882 COSTS_N_INSNS (5), /* fp_mult_df */
883 COSTS_N_INSNS (17), /* fp_div_sf */
884 COSTS_N_INSNS (32), /* fp_div_df */
885 COSTS_N_INSNS (5), /* int_mult_si */
886 COSTS_N_INSNS (5), /* int_mult_di */
887 COSTS_N_INSNS (41), /* int_div_si */
888 COSTS_N_INSNS (41), /* int_div_di */
890 4 /* memory_latency */
893 COSTS_N_INSNS (6), /* fp_add */
894 COSTS_N_INSNS (6), /* fp_mult_sf */
895 COSTS_N_INSNS (7), /* fp_mult_df */
896 COSTS_N_INSNS (25), /* fp_div_sf */
897 COSTS_N_INSNS (48), /* fp_div_df */
898 COSTS_N_INSNS (5), /* int_mult_si */
899 COSTS_N_INSNS (5), /* int_mult_di */
900 COSTS_N_INSNS (41), /* int_div_si */
901 COSTS_N_INSNS (41), /* int_div_di */
903 4 /* memory_latency */
920 COSTS_N_INSNS (5), /* int_mult_si */
921 COSTS_N_INSNS (5), /* int_mult_di */
922 COSTS_N_INSNS (72), /* int_div_si */
923 COSTS_N_INSNS (72), /* int_div_di */
925 4 /* memory_latency */
930 COSTS_N_INSNS (6), /* int_mult_si */
931 COSTS_N_INSNS (6), /* int_mult_di */
932 COSTS_N_INSNS (18), /* int_div_si */
933 COSTS_N_INSNS (35), /* int_div_di */
935 4 /* memory_latency */
938 COSTS_N_INSNS (2), /* fp_add */
939 COSTS_N_INSNS (4), /* fp_mult_sf */
940 COSTS_N_INSNS (5), /* fp_mult_df */
941 COSTS_N_INSNS (12), /* fp_div_sf */
942 COSTS_N_INSNS (19), /* fp_div_df */
943 COSTS_N_INSNS (2), /* int_mult_si */
944 COSTS_N_INSNS (2), /* int_mult_di */
945 COSTS_N_INSNS (35), /* int_div_si */
946 COSTS_N_INSNS (35), /* int_div_di */
948 4 /* memory_latency */
951 COSTS_N_INSNS (3), /* fp_add */
952 COSTS_N_INSNS (5), /* fp_mult_sf */
953 COSTS_N_INSNS (6), /* fp_mult_df */
954 COSTS_N_INSNS (15), /* fp_div_sf */
955 COSTS_N_INSNS (16), /* fp_div_df */
956 COSTS_N_INSNS (17), /* int_mult_si */
957 COSTS_N_INSNS (17), /* int_mult_di */
958 COSTS_N_INSNS (38), /* int_div_si */
959 COSTS_N_INSNS (38), /* int_div_di */
961 6 /* memory_latency */
964 COSTS_N_INSNS (6), /* fp_add */
965 COSTS_N_INSNS (7), /* fp_mult_sf */
966 COSTS_N_INSNS (8), /* fp_mult_df */
967 COSTS_N_INSNS (23), /* fp_div_sf */
968 COSTS_N_INSNS (36), /* fp_div_df */
969 COSTS_N_INSNS (10), /* int_mult_si */
970 COSTS_N_INSNS (10), /* int_mult_di */
971 COSTS_N_INSNS (69), /* int_div_si */
972 COSTS_N_INSNS (69), /* int_div_di */
974 6 /* memory_latency */
986 /* The only costs that appear to be updated here are
987 integer multiplication. */
989 COSTS_N_INSNS (4), /* int_mult_si */
990 COSTS_N_INSNS (6), /* int_mult_di */
991 COSTS_N_INSNS (69), /* int_div_si */
992 COSTS_N_INSNS (69), /* int_div_di */
994 4 /* memory_latency */
1009 COSTS_N_INSNS (6), /* fp_add */
1010 COSTS_N_INSNS (4), /* fp_mult_sf */
1011 COSTS_N_INSNS (5), /* fp_mult_df */
1012 COSTS_N_INSNS (23), /* fp_div_sf */
1013 COSTS_N_INSNS (36), /* fp_div_df */
1014 COSTS_N_INSNS (5), /* int_mult_si */
1015 COSTS_N_INSNS (5), /* int_mult_di */
1016 COSTS_N_INSNS (36), /* int_div_si */
1017 COSTS_N_INSNS (36), /* int_div_di */
1018 1, /* branch_cost */
1019 4 /* memory_latency */
1022 COSTS_N_INSNS (6), /* fp_add */
1023 COSTS_N_INSNS (5), /* fp_mult_sf */
1024 COSTS_N_INSNS (6), /* fp_mult_df */
1025 COSTS_N_INSNS (30), /* fp_div_sf */
1026 COSTS_N_INSNS (59), /* fp_div_df */
1027 COSTS_N_INSNS (3), /* int_mult_si */
1028 COSTS_N_INSNS (4), /* int_mult_di */
1029 COSTS_N_INSNS (42), /* int_div_si */
1030 COSTS_N_INSNS (74), /* int_div_di */
1031 1, /* branch_cost */
1032 4 /* memory_latency */
1035 COSTS_N_INSNS (6), /* fp_add */
1036 COSTS_N_INSNS (5), /* fp_mult_sf */
1037 COSTS_N_INSNS (6), /* fp_mult_df */
1038 COSTS_N_INSNS (30), /* fp_div_sf */
1039 COSTS_N_INSNS (59), /* fp_div_df */
1040 COSTS_N_INSNS (5), /* int_mult_si */
1041 COSTS_N_INSNS (9), /* int_mult_di */
1042 COSTS_N_INSNS (42), /* int_div_si */
1043 COSTS_N_INSNS (74), /* int_div_di */
1044 1, /* branch_cost */
1045 4 /* memory_latency */
1048 COSTS_N_INSNS (4), /* fp_add */
1049 COSTS_N_INSNS (4), /* fp_mult_sf */
1050 COSTS_N_INSNS (256), /* fp_mult_df */
1051 COSTS_N_INSNS (8), /* fp_div_sf */
1052 COSTS_N_INSNS (256), /* fp_div_df */
1053 COSTS_N_INSNS (4), /* int_mult_si */
1054 COSTS_N_INSNS (256), /* int_mult_di */
1055 COSTS_N_INSNS (37), /* int_div_si */
1056 COSTS_N_INSNS (256), /* int_div_di */
1057 1, /* branch_cost */
1058 4 /* memory_latency */
1061 /* The only costs that are changed here are
1062 integer multiplication. */
1063 COSTS_N_INSNS (6), /* fp_add */
1064 COSTS_N_INSNS (7), /* fp_mult_sf */
1065 COSTS_N_INSNS (8), /* fp_mult_df */
1066 COSTS_N_INSNS (23), /* fp_div_sf */
1067 COSTS_N_INSNS (36), /* fp_div_df */
1068 COSTS_N_INSNS (5), /* int_mult_si */
1069 COSTS_N_INSNS (9), /* int_mult_di */
1070 COSTS_N_INSNS (69), /* int_div_si */
1071 COSTS_N_INSNS (69), /* int_div_di */
1072 1, /* branch_cost */
1073 4 /* memory_latency */
1079 /* The only costs that are changed here are
1080 integer multiplication. */
1081 COSTS_N_INSNS (6), /* fp_add */
1082 COSTS_N_INSNS (7), /* fp_mult_sf */
1083 COSTS_N_INSNS (8), /* fp_mult_df */
1084 COSTS_N_INSNS (23), /* fp_div_sf */
1085 COSTS_N_INSNS (36), /* fp_div_df */
1086 COSTS_N_INSNS (3), /* int_mult_si */
1087 COSTS_N_INSNS (8), /* int_mult_di */
1088 COSTS_N_INSNS (69), /* int_div_si */
1089 COSTS_N_INSNS (69), /* int_div_di */
1090 1, /* branch_cost */
1091 4 /* memory_latency */
1094 COSTS_N_INSNS (2), /* fp_add */
1095 COSTS_N_INSNS (2), /* fp_mult_sf */
1096 COSTS_N_INSNS (2), /* fp_mult_df */
1097 COSTS_N_INSNS (12), /* fp_div_sf */
1098 COSTS_N_INSNS (19), /* fp_div_df */
1099 COSTS_N_INSNS (5), /* int_mult_si */
1100 COSTS_N_INSNS (9), /* int_mult_di */
1101 COSTS_N_INSNS (34), /* int_div_si */
1102 COSTS_N_INSNS (66), /* int_div_di */
1103 1, /* branch_cost */
1104 4 /* memory_latency */
1107 /* These costs are the same as the SB-1A below. */
1108 COSTS_N_INSNS (4), /* fp_add */
1109 COSTS_N_INSNS (4), /* fp_mult_sf */
1110 COSTS_N_INSNS (4), /* fp_mult_df */
1111 COSTS_N_INSNS (24), /* fp_div_sf */
1112 COSTS_N_INSNS (32), /* fp_div_df */
1113 COSTS_N_INSNS (3), /* int_mult_si */
1114 COSTS_N_INSNS (4), /* int_mult_di */
1115 COSTS_N_INSNS (36), /* int_div_si */
1116 COSTS_N_INSNS (68), /* int_div_di */
1117 1, /* branch_cost */
1118 4 /* memory_latency */
1121 /* These costs are the same as the SB-1 above. */
1122 COSTS_N_INSNS (4), /* fp_add */
1123 COSTS_N_INSNS (4), /* fp_mult_sf */
1124 COSTS_N_INSNS (4), /* fp_mult_df */
1125 COSTS_N_INSNS (24), /* fp_div_sf */
1126 COSTS_N_INSNS (32), /* fp_div_df */
1127 COSTS_N_INSNS (3), /* int_mult_si */
1128 COSTS_N_INSNS (4), /* int_mult_di */
1129 COSTS_N_INSNS (36), /* int_div_si */
1130 COSTS_N_INSNS (68), /* int_div_di */
1131 1, /* branch_cost */
1132 4 /* memory_latency */
1139 COSTS_N_INSNS (8), /* int_mult_si */
1140 COSTS_N_INSNS (8), /* int_mult_di */
1141 COSTS_N_INSNS (72), /* int_div_si */
1142 COSTS_N_INSNS (72), /* int_div_di */
1143 1, /* branch_cost */
1144 4 /* memory_latency */
1147 /* These costs are the same as 5KF above. */
1148 COSTS_N_INSNS (4), /* fp_add */
1149 COSTS_N_INSNS (4), /* fp_mult_sf */
1150 COSTS_N_INSNS (5), /* fp_mult_df */
1151 COSTS_N_INSNS (17), /* fp_div_sf */
1152 COSTS_N_INSNS (32), /* fp_div_df */
1153 COSTS_N_INSNS (4), /* int_mult_si */
1154 COSTS_N_INSNS (11), /* int_mult_di */
1155 COSTS_N_INSNS (36), /* int_div_si */
1156 COSTS_N_INSNS (68), /* int_div_di */
1157 1, /* branch_cost */
1158 4 /* memory_latency */
1162 static rtx mips_find_pic_call_symbol (rtx, rtx, bool);
1163 static int mips_register_move_cost (enum machine_mode, reg_class_t,
1165 static unsigned int mips_function_arg_boundary (enum machine_mode, const_tree);
1167 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1168 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1169 struct GTY (()) mflip_mips16_entry {
1173 static GTY ((param_is (struct mflip_mips16_entry))) htab_t mflip_mips16_htab;
1175 /* Hash table callbacks for mflip_mips16_htab. */
1178 mflip_mips16_htab_hash (const void *entry)
1180 return htab_hash_string (((const struct mflip_mips16_entry *) entry)->name);
1184 mflip_mips16_htab_eq (const void *entry, const void *name)
1186 return strcmp (((const struct mflip_mips16_entry *) entry)->name,
1187 (const char *) name) == 0;
1190 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1191 mode, false if it should next add an attribute for the opposite mode. */
1192 static GTY(()) bool mips16_flipper;
1194 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1195 for -mflip-mips16. Return true if it should use "mips16" and false if
1196 it should use "nomips16". */
1199 mflip_mips16_use_mips16_p (tree decl)
1201 struct mflip_mips16_entry *entry;
1205 bool base_is_mips16 = (mips_base_compression_flags & MASK_MIPS16) != 0;
1207 /* Use the opposite of the command-line setting for anonymous decls. */
1208 if (!DECL_NAME (decl))
1209 return !base_is_mips16;
1211 if (!mflip_mips16_htab)
1212 mflip_mips16_htab = htab_create_ggc (37, mflip_mips16_htab_hash,
1213 mflip_mips16_htab_eq, NULL);
1215 name = IDENTIFIER_POINTER (DECL_NAME (decl));
1216 hash = htab_hash_string (name);
1217 slot = htab_find_slot_with_hash (mflip_mips16_htab, name, hash, INSERT);
1218 entry = (struct mflip_mips16_entry *) *slot;
1221 mips16_flipper = !mips16_flipper;
1222 entry = ggc_alloc_mflip_mips16_entry ();
1224 entry->mips16_p = mips16_flipper ? !base_is_mips16 : base_is_mips16;
1227 return entry->mips16_p;
1230 /* Predicates to test for presence of "near" and "far"/"long_call"
1231 attributes on the given TYPE. */
1234 mips_near_type_p (const_tree type)
1236 return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL;
1240 mips_far_type_p (const_tree type)
1242 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL
1243 || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL);
1247 /* Check if the interrupt attribute is set for a function. */
1250 mips_interrupt_type_p (tree type)
1252 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type)) != NULL;
1255 /* Check if the attribute to use shadow register set is set for a function. */
1258 mips_use_shadow_register_set_p (tree type)
1260 return lookup_attribute ("use_shadow_register_set",
1261 TYPE_ATTRIBUTES (type)) != NULL;
1264 /* Check if the attribute to keep interrupts masked is set for a function. */
1267 mips_keep_interrupts_masked_p (tree type)
1269 return lookup_attribute ("keep_interrupts_masked",
1270 TYPE_ATTRIBUTES (type)) != NULL;
1273 /* Check if the attribute to use debug exception return is set for
1277 mips_use_debug_exception_return_p (tree type)
1279 return lookup_attribute ("use_debug_exception_return",
1280 TYPE_ATTRIBUTES (type)) != NULL;
1283 /* Return the set of compression modes that are explicitly required
1284 by the attributes in ATTRIBUTES. */
1287 mips_get_compress_on_flags (tree attributes)
1289 unsigned int flags = 0;
1291 if (lookup_attribute ("mips16", attributes) != NULL)
1292 flags |= MASK_MIPS16;
1294 if (lookup_attribute ("micromips", attributes) != NULL)
1295 flags |= MASK_MICROMIPS;
1300 /* Return the set of compression modes that are explicitly forbidden
1301 by the attributes in ATTRIBUTES. */
1304 mips_get_compress_off_flags (tree attributes)
1306 unsigned int flags = 0;
1308 if (lookup_attribute ("nocompression", attributes) != NULL)
1309 flags |= MASK_MIPS16 | MASK_MICROMIPS;
1311 if (lookup_attribute ("nomips16", attributes) != NULL)
1312 flags |= MASK_MIPS16;
1314 if (lookup_attribute ("nomicromips", attributes) != NULL)
1315 flags |= MASK_MICROMIPS;
1320 /* Return the compression mode that should be used for function DECL.
1321 Return the ambient setting if DECL is null. */
1324 mips_get_compress_mode (tree decl)
1326 unsigned int flags, force_on;
1328 flags = mips_base_compression_flags;
1331 /* Nested functions must use the same frame pointer as their
1332 parent and must therefore use the same ISA mode. */
1333 tree parent = decl_function_context (decl);
1336 force_on = mips_get_compress_on_flags (DECL_ATTRIBUTES (decl));
1339 flags &= ~mips_get_compress_off_flags (DECL_ATTRIBUTES (decl));
1344 /* Return the attribute name associated with MASK_MIPS16 and MASK_MICROMIPS
1348 mips_get_compress_on_name (unsigned int flags)
1350 if (flags == MASK_MIPS16)
1355 /* Return the attribute name that forbids MASK_MIPS16 and MASK_MICROMIPS
1359 mips_get_compress_off_name (unsigned int flags)
1361 if (flags == MASK_MIPS16)
1363 if (flags == MASK_MICROMIPS)
1364 return "nomicromips";
1365 return "nocompression";
1368 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1371 mips_comp_type_attributes (const_tree type1, const_tree type2)
1373 /* Disallow mixed near/far attributes. */
1374 if (mips_far_type_p (type1) && mips_near_type_p (type2))
1376 if (mips_near_type_p (type1) && mips_far_type_p (type2))
1381 /* Implement TARGET_INSERT_ATTRIBUTES. */
1384 mips_insert_attributes (tree decl, tree *attributes)
1387 unsigned int compression_flags, nocompression_flags;
1389 /* Check for "mips16" and "nomips16" attributes. */
1390 compression_flags = mips_get_compress_on_flags (*attributes);
1391 nocompression_flags = mips_get_compress_off_flags (*attributes);
1393 if (TREE_CODE (decl) != FUNCTION_DECL)
1395 if (nocompression_flags)
1396 error ("%qs attribute only applies to functions",
1397 mips_get_compress_off_name (nocompression_flags));
1399 if (compression_flags)
1400 error ("%qs attribute only applies to functions",
1401 mips_get_compress_on_name (nocompression_flags));
1405 compression_flags |= mips_get_compress_on_flags (DECL_ATTRIBUTES (decl));
1406 nocompression_flags |=
1407 mips_get_compress_off_flags (DECL_ATTRIBUTES (decl));
1409 if (compression_flags && nocompression_flags)
1410 error ("%qE cannot have both %qs and %qs attributes",
1411 DECL_NAME (decl), mips_get_compress_on_name (compression_flags),
1412 mips_get_compress_off_name (nocompression_flags));
1414 if (compression_flags & MASK_MIPS16
1415 && compression_flags & MASK_MICROMIPS)
1416 error ("%qE cannot have both %qs and %qs attributes",
1417 DECL_NAME (decl), "mips16", "micromips");
1419 if (TARGET_FLIP_MIPS16
1420 && !DECL_ARTIFICIAL (decl)
1421 && compression_flags == 0
1422 && nocompression_flags == 0)
1424 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1425 "mips16" attribute, arbitrarily pick one. We must pick the same
1426 setting for duplicate declarations of a function. */
1427 name = mflip_mips16_use_mips16_p (decl) ? "mips16" : "nomips16";
1428 *attributes = tree_cons (get_identifier (name), NULL, *attributes);
1429 name = "nomicromips";
1430 *attributes = tree_cons (get_identifier (name), NULL, *attributes);
1435 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1438 mips_merge_decl_attributes (tree olddecl, tree newdecl)
1442 diff = (mips_get_compress_on_flags (DECL_ATTRIBUTES (olddecl))
1443 ^ mips_get_compress_on_flags (DECL_ATTRIBUTES (newdecl)));
1445 error ("%qE redeclared with conflicting %qs attributes",
1446 DECL_NAME (newdecl), mips_get_compress_on_name (diff));
1448 diff = (mips_get_compress_off_flags (DECL_ATTRIBUTES (olddecl))
1449 ^ mips_get_compress_off_flags (DECL_ATTRIBUTES (newdecl)));
1451 error ("%qE redeclared with conflicting %qs attributes",
1452 DECL_NAME (newdecl), mips_get_compress_off_name (diff));
1454 return merge_attributes (DECL_ATTRIBUTES (olddecl),
1455 DECL_ATTRIBUTES (newdecl));
1458 /* Implement TARGET_CAN_INLINE_P. */
1461 mips_can_inline_p (tree caller, tree callee)
1463 if (mips_get_compress_mode (callee) != mips_get_compress_mode (caller))
1465 return default_target_can_inline_p (caller, callee);
1468 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1469 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1472 mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr)
1474 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
1476 *base_ptr = XEXP (x, 0);
1477 *offset_ptr = INTVAL (XEXP (x, 1));
1486 static unsigned int mips_build_integer (struct mips_integer_op *,
1487 unsigned HOST_WIDE_INT);
1489 /* A subroutine of mips_build_integer, with the same interface.
1490 Assume that the final action in the sequence should be a left shift. */
1493 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1495 unsigned int i, shift;
1497 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1498 since signed numbers are easier to load than unsigned ones. */
1500 while ((value & 1) == 0)
1501 value /= 2, shift++;
1503 i = mips_build_integer (codes, value);
1504 codes[i].code = ASHIFT;
1505 codes[i].value = shift;
1509 /* As for mips_build_shift, but assume that the final action will be
1510 an IOR or PLUS operation. */
1513 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1515 unsigned HOST_WIDE_INT high;
1518 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1519 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
1521 /* The constant is too complex to load with a simple LUI/ORI pair,
1522 so we want to give the recursive call as many trailing zeros as
1523 possible. In this case, we know bit 16 is set and that the
1524 low 16 bits form a negative number. If we subtract that number
1525 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1526 i = mips_build_integer (codes, CONST_HIGH_PART (value));
1527 codes[i].code = PLUS;
1528 codes[i].value = CONST_LOW_PART (value);
1532 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1533 bits gives a value with at least 17 trailing zeros. */
1534 i = mips_build_integer (codes, high);
1535 codes[i].code = IOR;
1536 codes[i].value = value & 0xffff;
1541 /* Fill CODES with a sequence of rtl operations to load VALUE.
1542 Return the number of operations needed. */
1545 mips_build_integer (struct mips_integer_op *codes,
1546 unsigned HOST_WIDE_INT value)
1548 if (SMALL_OPERAND (value)
1549 || SMALL_OPERAND_UNSIGNED (value)
1550 || LUI_OPERAND (value))
1552 /* The value can be loaded with a single instruction. */
1553 codes[0].code = UNKNOWN;
1554 codes[0].value = value;
1557 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
1559 /* Either the constant is a simple LUI/ORI combination or its
1560 lowest bit is set. We don't want to shift in this case. */
1561 return mips_build_lower (codes, value);
1563 else if ((value & 0xffff) == 0)
1565 /* The constant will need at least three actions. The lowest
1566 16 bits are clear, so the final action will be a shift. */
1567 return mips_build_shift (codes, value);
1571 /* The final action could be a shift, add or inclusive OR.
1572 Rather than use a complex condition to select the best
1573 approach, try both mips_build_shift and mips_build_lower
1574 and pick the one that gives the shortest sequence.
1575 Note that this case is only used once per constant. */
1576 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1577 unsigned int cost, alt_cost;
1579 cost = mips_build_shift (codes, value);
1580 alt_cost = mips_build_lower (alt_codes, value);
1581 if (alt_cost < cost)
1583 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
1590 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
1593 mips_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
1595 return mips_const_insns (x) > 0;
1598 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
1601 mips16_stub_function (const char *name)
1605 x = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
1606 SYMBOL_REF_FLAGS (x) |= (SYMBOL_FLAG_EXTERNAL | SYMBOL_FLAG_FUNCTION);
1610 /* Return true if symbols of type TYPE require a GOT access. */
1613 mips_got_symbol_type_p (enum mips_symbol_type type)
1617 case SYMBOL_GOT_PAGE_OFST:
1618 case SYMBOL_GOT_DISP:
1626 /* Return true if X is a thread-local symbol. */
1629 mips_tls_symbol_p (rtx x)
1631 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1634 /* Return true if SYMBOL_REF X is associated with a global symbol
1635 (in the STB_GLOBAL sense). */
1638 mips_global_symbol_p (const_rtx x)
1640 const_tree decl = SYMBOL_REF_DECL (x);
1643 return !SYMBOL_REF_LOCAL_P (x) || SYMBOL_REF_EXTERNAL_P (x);
1645 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1646 or weak symbols. Relocations in the object file will be against
1647 the target symbol, so it's that symbol's binding that matters here. */
1648 return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl));
1651 /* Return true if function X is a libgcc MIPS16 stub function. */
1654 mips16_stub_function_p (const_rtx x)
1656 return (GET_CODE (x) == SYMBOL_REF
1657 && strncmp (XSTR (x, 0), "__mips16_", 9) == 0);
1660 /* Return true if function X is a locally-defined and locally-binding
1664 mips16_local_function_p (const_rtx x)
1666 return (GET_CODE (x) == SYMBOL_REF
1667 && SYMBOL_REF_LOCAL_P (x)
1668 && !SYMBOL_REF_EXTERNAL_P (x)
1669 && (mips_get_compress_mode (SYMBOL_REF_DECL (x)) & MASK_MIPS16));
1672 /* Return true if SYMBOL_REF X binds locally. */
1675 mips_symbol_binds_local_p (const_rtx x)
1677 return (SYMBOL_REF_DECL (x)
1678 ? targetm.binds_local_p (SYMBOL_REF_DECL (x))
1679 : SYMBOL_REF_LOCAL_P (x));
1682 /* Return true if rtx constants of mode MODE should be put into a small
1686 mips_rtx_constant_in_small_data_p (enum machine_mode mode)
1688 return (!TARGET_EMBEDDED_DATA
1689 && TARGET_LOCAL_SDATA
1690 && GET_MODE_SIZE (mode) <= mips_small_data_threshold);
1693 /* Return true if X should not be moved directly into register $25.
1694 We need this because many versions of GAS will treat "la $25,foo" as
1695 part of a call sequence and so allow a global "foo" to be lazily bound. */
1698 mips_dangerous_for_la25_p (rtx x)
1700 return (!TARGET_EXPLICIT_RELOCS
1702 && GET_CODE (x) == SYMBOL_REF
1703 && mips_global_symbol_p (x));
1706 /* Return true if calls to X might need $25 to be valid on entry. */
1709 mips_use_pic_fn_addr_reg_p (const_rtx x)
1711 if (!TARGET_USE_PIC_FN_ADDR_REG)
1714 /* MIPS16 stub functions are guaranteed not to use $25. */
1715 if (mips16_stub_function_p (x))
1718 if (GET_CODE (x) == SYMBOL_REF)
1720 /* If PLTs and copy relocations are available, the static linker
1721 will make sure that $25 is valid on entry to the target function. */
1722 if (TARGET_ABICALLS_PIC0)
1725 /* Locally-defined functions use absolute accesses to set up
1726 the global pointer. */
1727 if (TARGET_ABSOLUTE_ABICALLS
1728 && mips_symbol_binds_local_p (x)
1729 && !SYMBOL_REF_EXTERNAL_P (x))
1736 /* Return the method that should be used to access SYMBOL_REF or
1737 LABEL_REF X in context CONTEXT. */
1739 static enum mips_symbol_type
1740 mips_classify_symbol (const_rtx x, enum mips_symbol_context context)
1743 return SYMBOL_GOT_DISP;
1745 if (GET_CODE (x) == LABEL_REF)
1747 /* Only return SYMBOL_PC_RELATIVE if we are generating MIPS16
1748 code and if we know that the label is in the current function's
1749 text section. LABEL_REFs are used for jump tables as well as
1750 text labels, so we must check whether jump tables live in the
1752 if (TARGET_MIPS16_SHORT_JUMP_TABLES
1753 && !LABEL_REF_NONLOCAL_P (x))
1754 return SYMBOL_PC_RELATIVE;
1756 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1757 return SYMBOL_GOT_PAGE_OFST;
1759 return SYMBOL_ABSOLUTE;
1762 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1764 if (SYMBOL_REF_TLS_MODEL (x))
1767 if (CONSTANT_POOL_ADDRESS_P (x))
1769 if (TARGET_MIPS16_TEXT_LOADS)
1770 return SYMBOL_PC_RELATIVE;
1772 if (TARGET_MIPS16_PCREL_LOADS && context == SYMBOL_CONTEXT_MEM)
1773 return SYMBOL_PC_RELATIVE;
1775 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x)))
1776 return SYMBOL_GP_RELATIVE;
1779 /* Do not use small-data accesses for weak symbols; they may end up
1781 if (TARGET_GPOPT && SYMBOL_REF_SMALL_P (x) && !SYMBOL_REF_WEAK (x))
1782 return SYMBOL_GP_RELATIVE;
1784 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1786 if (TARGET_ABICALLS_PIC2
1787 && !(TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x)))
1789 /* There are three cases to consider:
1791 - o32 PIC (either with or without explicit relocs)
1792 - n32/n64 PIC without explicit relocs
1793 - n32/n64 PIC with explicit relocs
1795 In the first case, both local and global accesses will use an
1796 R_MIPS_GOT16 relocation. We must correctly predict which of
1797 the two semantics (local or global) the assembler and linker
1798 will apply. The choice depends on the symbol's binding rather
1799 than its visibility.
1801 In the second case, the assembler will not use R_MIPS_GOT16
1802 relocations, but it chooses between local and global accesses
1803 in the same way as for o32 PIC.
1805 In the third case we have more freedom since both forms of
1806 access will work for any kind of symbol. However, there seems
1807 little point in doing things differently. */
1808 if (mips_global_symbol_p (x))
1809 return SYMBOL_GOT_DISP;
1811 return SYMBOL_GOT_PAGE_OFST;
1814 return SYMBOL_ABSOLUTE;
1817 /* Classify the base of symbolic expression X, given that X appears in
1820 static enum mips_symbol_type
1821 mips_classify_symbolic_expression (rtx x, enum mips_symbol_context context)
1825 split_const (x, &x, &offset);
1826 if (UNSPEC_ADDRESS_P (x))
1827 return UNSPEC_ADDRESS_TYPE (x);
1829 return mips_classify_symbol (x, context);
1832 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1833 is the alignment in bytes of SYMBOL_REF X. */
1836 mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset)
1838 HOST_WIDE_INT align;
1840 align = SYMBOL_REF_DECL (x) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x)) : 1;
1841 return IN_RANGE (offset, 0, align - 1);
1844 /* Return true if X is a symbolic constant that can be used in context
1845 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1848 mips_symbolic_constant_p (rtx x, enum mips_symbol_context context,
1849 enum mips_symbol_type *symbol_type)
1853 split_const (x, &x, &offset);
1854 if (UNSPEC_ADDRESS_P (x))
1856 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1857 x = UNSPEC_ADDRESS (x);
1859 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1861 *symbol_type = mips_classify_symbol (x, context);
1862 if (*symbol_type == SYMBOL_TLS)
1868 if (offset == const0_rtx)
1871 /* Check whether a nonzero offset is valid for the underlying
1873 switch (*symbol_type)
1875 case SYMBOL_ABSOLUTE:
1876 case SYMBOL_64_HIGH:
1879 /* If the target has 64-bit pointers and the object file only
1880 supports 32-bit symbols, the values of those symbols will be
1881 sign-extended. In this case we can't allow an arbitrary offset
1882 in case the 32-bit value X + OFFSET has a different sign from X. */
1883 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1884 return offset_within_block_p (x, INTVAL (offset));
1886 /* In other cases the relocations can handle any offset. */
1889 case SYMBOL_PC_RELATIVE:
1890 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1891 In this case, we no longer have access to the underlying constant,
1892 but the original symbol-based access was known to be valid. */
1893 if (GET_CODE (x) == LABEL_REF)
1898 case SYMBOL_GP_RELATIVE:
1899 /* Make sure that the offset refers to something within the
1900 same object block. This should guarantee that the final
1901 PC- or GP-relative offset is within the 16-bit limit. */
1902 return offset_within_block_p (x, INTVAL (offset));
1904 case SYMBOL_GOT_PAGE_OFST:
1905 case SYMBOL_GOTOFF_PAGE:
1906 /* If the symbol is global, the GOT entry will contain the symbol's
1907 address, and we will apply a 16-bit offset after loading it.
1908 If the symbol is local, the linker should provide enough local
1909 GOT entries for a 16-bit offset, but larger offsets may lead
1911 return SMALL_INT (offset);
1915 /* There is no carry between the HI and LO REL relocations, so the
1916 offset is only valid if we know it won't lead to such a carry. */
1917 return mips_offset_within_alignment_p (x, INTVAL (offset));
1919 case SYMBOL_GOT_DISP:
1920 case SYMBOL_GOTOFF_DISP:
1921 case SYMBOL_GOTOFF_CALL:
1922 case SYMBOL_GOTOFF_LOADGP:
1925 case SYMBOL_GOTTPREL:
1933 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
1934 single instruction. We rely on the fact that, in the worst case,
1935 all instructions involved in a MIPS16 address calculation are usually
1939 mips_symbol_insns_1 (enum mips_symbol_type type, enum machine_mode mode)
1941 if (mips_use_pcrel_pool_p[(int) type])
1943 if (mode == MAX_MACHINE_MODE)
1944 /* LEAs will be converted into constant-pool references by
1946 type = SYMBOL_PC_RELATIVE;
1948 /* The constant must be loaded and then dereferenced. */
1954 case SYMBOL_ABSOLUTE:
1955 /* When using 64-bit symbols, we need 5 preparatory instructions,
1958 lui $at,%highest(symbol)
1959 daddiu $at,$at,%higher(symbol)
1961 daddiu $at,$at,%hi(symbol)
1964 The final address is then $at + %lo(symbol). With 32-bit
1965 symbols we just need a preparatory LUI for normal mode and
1966 a preparatory LI and SLL for MIPS16. */
1967 return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2;
1969 case SYMBOL_GP_RELATIVE:
1970 /* Treat GP-relative accesses as taking a single instruction on
1971 MIPS16 too; the copy of $gp can often be shared. */
1974 case SYMBOL_PC_RELATIVE:
1975 /* PC-relative constants can be only be used with ADDIUPC,
1976 DADDIUPC, LWPC and LDPC. */
1977 if (mode == MAX_MACHINE_MODE
1978 || GET_MODE_SIZE (mode) == 4
1979 || GET_MODE_SIZE (mode) == 8)
1982 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
1985 case SYMBOL_GOT_DISP:
1986 /* The constant will have to be loaded from the GOT before it
1987 is used in an address. */
1988 if (mode != MAX_MACHINE_MODE)
1993 case SYMBOL_GOT_PAGE_OFST:
1994 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
1995 local/global classification is accurate. The worst cases are:
1997 (1) For local symbols when generating o32 or o64 code. The assembler
2003 ...and the final address will be $at + %lo(symbol).
2005 (2) For global symbols when -mxgot. The assembler will use:
2007 lui $at,%got_hi(symbol)
2010 ...and the final address will be $at + %got_lo(symbol). */
2013 case SYMBOL_GOTOFF_PAGE:
2014 case SYMBOL_GOTOFF_DISP:
2015 case SYMBOL_GOTOFF_CALL:
2016 case SYMBOL_GOTOFF_LOADGP:
2017 case SYMBOL_64_HIGH:
2023 case SYMBOL_GOTTPREL:
2026 /* A 16-bit constant formed by a single relocation, or a 32-bit
2027 constant formed from a high 16-bit relocation and a low 16-bit
2028 relocation. Use mips_split_p to determine which. 32-bit
2029 constants need an "lui; addiu" sequence for normal mode and
2030 an "li; sll; addiu" sequence for MIPS16 mode. */
2031 return !mips_split_p[type] ? 1 : TARGET_MIPS16 ? 3 : 2;
2034 /* We don't treat a bare TLS symbol as a constant. */
2040 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
2041 to load symbols of type TYPE into a register. Return 0 if the given
2042 type of symbol cannot be used as an immediate operand.
2044 Otherwise, return the number of instructions needed to load or store
2045 values of mode MODE to or from addresses of type TYPE. Return 0 if
2046 the given type of symbol is not valid in addresses.
2048 In both cases, instruction counts are based off BASE_INSN_LENGTH. */
2051 mips_symbol_insns (enum mips_symbol_type type, enum machine_mode mode)
2053 return mips_symbol_insns_1 (type, mode) * (TARGET_MIPS16 ? 2 : 1);
2056 /* A for_each_rtx callback. Stop the search if *X references a
2057 thread-local symbol. */
2060 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
2062 return mips_tls_symbol_p (*x);
2065 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
2068 mips_cannot_force_const_mem (enum machine_mode mode, rtx x)
2070 enum mips_symbol_type type;
2073 /* There is no assembler syntax for expressing an address-sized
2075 if (GET_CODE (x) == HIGH)
2078 /* As an optimization, reject constants that mips_legitimize_move
2081 Suppose we have a multi-instruction sequence that loads constant C
2082 into register R. If R does not get allocated a hard register, and
2083 R is used in an operand that allows both registers and memory
2084 references, reload will consider forcing C into memory and using
2085 one of the instruction's memory alternatives. Returning false
2086 here will force it to use an input reload instead. */
2087 if (CONST_INT_P (x) && mips_legitimate_constant_p (mode, x))
2090 split_const (x, &base, &offset);
2091 if (mips_symbolic_constant_p (base, SYMBOL_CONTEXT_LEA, &type))
2093 /* See whether we explicitly want these symbols in the pool. */
2094 if (mips_use_pcrel_pool_p[(int) type])
2097 /* The same optimization as for CONST_INT. */
2098 if (SMALL_INT (offset) && mips_symbol_insns (type, MAX_MACHINE_MODE) > 0)
2101 /* If MIPS16 constant pools live in the text section, they should
2102 not refer to anything that might need run-time relocation. */
2103 if (TARGET_MIPS16_PCREL_LOADS && mips_got_symbol_type_p (type))
2107 /* TLS symbols must be computed by mips_legitimize_move. */
2108 if (for_each_rtx (&x, &mips_tls_symbol_ref_1, NULL))
2114 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
2115 constants when we're using a per-function constant pool. */
2118 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
2119 const_rtx x ATTRIBUTE_UNUSED)
2121 return !TARGET_MIPS16_PCREL_LOADS;
2124 /* Return true if register REGNO is a valid base register for mode MODE.
2125 STRICT_P is true if REG_OK_STRICT is in effect. */
2128 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode,
2131 if (!HARD_REGISTER_NUM_P (regno))
2135 regno = reg_renumber[regno];
2138 /* These fake registers will be eliminated to either the stack or
2139 hard frame pointer, both of which are usually valid base registers.
2140 Reload deals with the cases where the eliminated form isn't valid. */
2141 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
2144 /* In MIPS16 mode, the stack pointer can only address word and doubleword
2145 values, nothing smaller. There are two problems here:
2147 (a) Instantiating virtual registers can introduce new uses of the
2148 stack pointer. If these virtual registers are valid addresses,
2149 the stack pointer should be too.
2151 (b) Most uses of the stack pointer are not made explicit until
2152 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
2153 We don't know until that stage whether we'll be eliminating to the
2154 stack pointer (which needs the restriction) or the hard frame
2155 pointer (which doesn't).
2157 All in all, it seems more consistent to only enforce this restriction
2158 during and after reload. */
2159 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
2160 return !strict_p || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
2162 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
2165 /* Return true if X is a valid base register for mode MODE.
2166 STRICT_P is true if REG_OK_STRICT is in effect. */
2169 mips_valid_base_register_p (rtx x, enum machine_mode mode, bool strict_p)
2171 if (!strict_p && GET_CODE (x) == SUBREG)
2175 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p));
2178 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2179 can address a value of mode MODE. */
2182 mips_valid_offset_p (rtx x, enum machine_mode mode)
2184 /* Check that X is a signed 16-bit number. */
2185 if (!const_arith_operand (x, Pmode))
2188 /* We may need to split multiword moves, so make sure that every word
2190 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2191 && !SMALL_OPERAND (INTVAL (x) + GET_MODE_SIZE (mode) - UNITS_PER_WORD))
2197 /* Return true if a LO_SUM can address a value of mode MODE when the
2198 LO_SUM symbol has type SYMBOL_TYPE. */
2201 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type, enum machine_mode mode)
2203 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2205 if (mips_symbol_insns (symbol_type, mode) == 0)
2208 /* Check that there is a known low-part relocation. */
2209 if (mips_lo_relocs[symbol_type] == NULL)
2212 /* We may need to split multiword moves, so make sure that each word
2213 can be accessed without inducing a carry. This is mainly needed
2214 for o64, which has historically only guaranteed 64-bit alignment
2215 for 128-bit types. */
2216 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2217 && GET_MODE_BITSIZE (mode) > GET_MODE_ALIGNMENT (mode))
2223 /* Return true if X is a valid address for machine mode MODE. If it is,
2224 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2228 mips_classify_address (struct mips_address_info *info, rtx x,
2229 enum machine_mode mode, bool strict_p)
2231 switch (GET_CODE (x))
2235 info->type = ADDRESS_REG;
2237 info->offset = const0_rtx;
2238 return mips_valid_base_register_p (info->reg, mode, strict_p);
2241 info->type = ADDRESS_REG;
2242 info->reg = XEXP (x, 0);
2243 info->offset = XEXP (x, 1);
2244 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2245 && mips_valid_offset_p (info->offset, mode));
2248 info->type = ADDRESS_LO_SUM;
2249 info->reg = XEXP (x, 0);
2250 info->offset = XEXP (x, 1);
2251 /* We have to trust the creator of the LO_SUM to do something vaguely
2252 sane. Target-independent code that creates a LO_SUM should also
2253 create and verify the matching HIGH. Target-independent code that
2254 adds an offset to a LO_SUM must prove that the offset will not
2255 induce a carry. Failure to do either of these things would be
2256 a bug, and we are not required to check for it here. The MIPS
2257 backend itself should only create LO_SUMs for valid symbolic
2258 constants, with the high part being either a HIGH or a copy
2261 = mips_classify_symbolic_expression (info->offset, SYMBOL_CONTEXT_MEM);
2262 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2263 && mips_valid_lo_sum_p (info->symbol_type, mode));
2266 /* Small-integer addresses don't occur very often, but they
2267 are legitimate if $0 is a valid base register. */
2268 info->type = ADDRESS_CONST_INT;
2269 return !TARGET_MIPS16 && SMALL_INT (x);
2274 info->type = ADDRESS_SYMBOLIC;
2275 return (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_MEM,
2277 && mips_symbol_insns (info->symbol_type, mode) > 0
2278 && !mips_split_p[info->symbol_type]);
2285 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2288 mips_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
2290 struct mips_address_info addr;
2292 return mips_classify_address (&addr, x, mode, strict_p);
2295 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
2298 mips_stack_address_p (rtx x, enum machine_mode mode)
2300 struct mips_address_info addr;
2302 return (mips_classify_address (&addr, x, mode, false)
2303 && addr.type == ADDRESS_REG
2304 && addr.reg == stack_pointer_rtx);
2307 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2308 address instruction. Note that such addresses are not considered
2309 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2310 is so restricted. */
2313 mips_lwxs_address_p (rtx addr)
2316 && GET_CODE (addr) == PLUS
2317 && REG_P (XEXP (addr, 1)))
2319 rtx offset = XEXP (addr, 0);
2320 if (GET_CODE (offset) == MULT
2321 && REG_P (XEXP (offset, 0))
2322 && CONST_INT_P (XEXP (offset, 1))
2323 && INTVAL (XEXP (offset, 1)) == 4)
2329 /* Return true if ADDR matches the pattern for the L{B,H,W,D}{,U}X load
2330 indexed address instruction. Note that such addresses are
2331 not considered legitimate in the TARGET_LEGITIMATE_ADDRESS_P
2332 sense, because their use is so restricted. */
2335 mips_lx_address_p (rtx addr, enum machine_mode mode)
2337 if (GET_CODE (addr) != PLUS
2338 || !REG_P (XEXP (addr, 0))
2339 || !REG_P (XEXP (addr, 1)))
2341 if (ISA_HAS_LBX && mode == QImode)
2343 if (ISA_HAS_LHX && mode == HImode)
2345 if (ISA_HAS_LWX && mode == SImode)
2347 if (ISA_HAS_LDX && mode == DImode)
2352 /* Return true if a value at OFFSET bytes from base register BASE can be
2353 accessed using an unextended MIPS16 instruction. MODE is the mode of
2356 Usually the offset in an unextended instruction is a 5-bit field.
2357 The offset is unsigned and shifted left once for LH and SH, twice
2358 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2359 an 8-bit immediate field that's shifted left twice. */
2362 mips16_unextended_reference_p (enum machine_mode mode, rtx base,
2363 unsigned HOST_WIDE_INT offset)
2365 if (mode != BLKmode && offset % GET_MODE_SIZE (mode) == 0)
2367 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
2368 return offset < 256U * GET_MODE_SIZE (mode);
2369 return offset < 32U * GET_MODE_SIZE (mode);
2374 /* Return the number of instructions needed to load or store a value
2375 of mode MODE at address X, assuming that BASE_INSN_LENGTH is the
2376 length of one instruction. Return 0 if X isn't valid for MODE.
2377 Assume that multiword moves may need to be split into word moves
2378 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2382 mips_address_insns (rtx x, enum machine_mode mode, bool might_split_p)
2384 struct mips_address_info addr;
2387 /* BLKmode is used for single unaligned loads and stores and should
2388 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2389 meaningless, so we have to single it out as a special case one way
2391 if (mode != BLKmode && might_split_p)
2392 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2396 if (mips_classify_address (&addr, x, mode, false))
2401 && !mips16_unextended_reference_p (mode, addr.reg,
2402 UINTVAL (addr.offset)))
2406 case ADDRESS_LO_SUM:
2407 return TARGET_MIPS16 ? factor * 2 : factor;
2409 case ADDRESS_CONST_INT:
2412 case ADDRESS_SYMBOLIC:
2413 return factor * mips_symbol_insns (addr.symbol_type, mode);
2418 /* Return true if X fits within an unsigned field of BITS bits that is
2419 shifted left SHIFT bits before being used. */
2422 mips_unsigned_immediate_p (unsigned HOST_WIDE_INT x, int bits, int shift = 0)
2424 return (x & ((1 << shift) - 1)) == 0 && x < ((unsigned) 1 << (shift + bits));
2427 /* Return true if X fits within a signed field of BITS bits that is
2428 shifted left SHIFT bits before being used. */
2431 mips_signed_immediate_p (unsigned HOST_WIDE_INT x, int bits, int shift = 0)
2433 x += 1 << (bits + shift - 1);
2434 return mips_unsigned_immediate_p (x, bits, shift);
2437 /* Return true if X is legitimate for accessing values of mode MODE,
2438 if it is based on a MIPS16 register, and if the offset satisfies
2439 OFFSET_PREDICATE. */
2442 m16_based_address_p (rtx x, enum machine_mode mode,
2443 insn_operand_predicate_fn offset_predicate)
2445 struct mips_address_info addr;
2447 return (mips_classify_address (&addr, x, mode, false)
2448 && addr.type == ADDRESS_REG
2449 && M16_REG_P (REGNO (addr.reg))
2450 && offset_predicate (addr.offset, mode));
2453 /* Return true if X is a legitimate address that conforms to the requirements
2454 for a microMIPS LWSP or SWSP insn. */
2457 lwsp_swsp_address_p (rtx x, enum machine_mode mode)
2459 struct mips_address_info addr;
2461 return (mips_classify_address (&addr, x, mode, false)
2462 && addr.type == ADDRESS_REG
2463 && REGNO (addr.reg) == STACK_POINTER_REGNUM
2464 && uw5_operand (addr.offset, mode));
2467 /* Return true if X is a legitimate address with a 12-bit offset.
2468 MODE is the mode of the value being accessed. */
2471 umips_12bit_offset_address_p (rtx x, enum machine_mode mode)
2473 struct mips_address_info addr;
2475 return (mips_classify_address (&addr, x, mode, false)
2476 && addr.type == ADDRESS_REG
2477 && CONST_INT_P (addr.offset)
2478 && UMIPS_12BIT_OFFSET_P (INTVAL (addr.offset)));
2481 /* Return the number of instructions needed to load constant X,
2482 assuming that BASE_INSN_LENGTH is the length of one instruction.
2483 Return 0 if X isn't a valid constant. */
2486 mips_const_insns (rtx x)
2488 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2489 enum mips_symbol_type symbol_type;
2492 switch (GET_CODE (x))
2495 if (!mips_symbolic_constant_p (XEXP (x, 0), SYMBOL_CONTEXT_LEA,
2497 || !mips_split_p[symbol_type])
2500 /* This is simply an LUI for normal mode. It is an extended
2501 LI followed by an extended SLL for MIPS16. */
2502 return TARGET_MIPS16 ? 4 : 1;
2506 /* Unsigned 8-bit constants can be loaded using an unextended
2507 LI instruction. Unsigned 16-bit constants can be loaded
2508 using an extended LI. Negative constants must be loaded
2509 using LI and then negated. */
2510 return (IN_RANGE (INTVAL (x), 0, 255) ? 1
2511 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
2512 : IN_RANGE (-INTVAL (x), 0, 255) ? 2
2513 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
2516 return mips_build_integer (codes, INTVAL (x));
2520 /* Allow zeros for normal mode, where we can use $0. */
2521 return !TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0;
2527 /* See if we can refer to X directly. */
2528 if (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_LEA, &symbol_type))
2529 return mips_symbol_insns (symbol_type, MAX_MACHINE_MODE);
2531 /* Otherwise try splitting the constant into a base and offset.
2532 If the offset is a 16-bit value, we can load the base address
2533 into a register and then use (D)ADDIU to add in the offset.
2534 If the offset is larger, we can load the base and offset
2535 into separate registers and add them together with (D)ADDU.
2536 However, the latter is only possible before reload; during
2537 and after reload, we must have the option of forcing the
2538 constant into the pool instead. */
2539 split_const (x, &x, &offset);
2542 int n = mips_const_insns (x);
2545 if (SMALL_INT (offset))
2547 else if (!targetm.cannot_force_const_mem (GET_MODE (x), x))
2548 return n + 1 + mips_build_integer (codes, INTVAL (offset));
2555 return mips_symbol_insns (mips_classify_symbol (x, SYMBOL_CONTEXT_LEA),
2563 /* X is a doubleword constant that can be handled by splitting it into
2564 two words and loading each word separately. Return the number of
2565 instructions required to do this, assuming that BASE_INSN_LENGTH
2566 is the length of one instruction. */
2569 mips_split_const_insns (rtx x)
2571 unsigned int low, high;
2573 low = mips_const_insns (mips_subword (x, false));
2574 high = mips_const_insns (mips_subword (x, true));
2575 gcc_assert (low > 0 && high > 0);
2579 /* Return the number of instructions needed to implement INSN,
2580 given that it loads from or stores to MEM. Assume that
2581 BASE_INSN_LENGTH is the length of one instruction. */
2584 mips_load_store_insns (rtx mem, rtx insn)
2586 enum machine_mode mode;
2590 gcc_assert (MEM_P (mem));
2591 mode = GET_MODE (mem);
2593 /* Try to prove that INSN does not need to be split. */
2594 might_split_p = GET_MODE_SIZE (mode) > UNITS_PER_WORD;
2597 set = single_set (insn);
2598 if (set && !mips_split_move_insn_p (SET_DEST (set), SET_SRC (set), insn))
2599 might_split_p = false;
2602 return mips_address_insns (XEXP (mem, 0), mode, might_split_p);
2605 /* Return the number of instructions needed for an integer division,
2606 assuming that BASE_INSN_LENGTH is the length of one instruction. */
2609 mips_idiv_insns (void)
2614 if (TARGET_CHECK_ZERO_DIV)
2616 if (GENERATE_DIVIDE_TRAPS)
2622 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
2627 /* Emit a move from SRC to DEST. Assume that the move expanders can
2628 handle all moves if !can_create_pseudo_p (). The distinction is
2629 important because, unlike emit_move_insn, the move expanders know
2630 how to force Pmode objects into the constant pool even when the
2631 constant pool address is not itself legitimate. */
2634 mips_emit_move (rtx dest, rtx src)
2636 return (can_create_pseudo_p ()
2637 ? emit_move_insn (dest, src)
2638 : emit_move_insn_1 (dest, src));
2641 /* Emit a move from SRC to DEST, splitting compound moves into individual
2642 instructions. SPLIT_TYPE is the type of split to perform. */
2645 mips_emit_move_or_split (rtx dest, rtx src, enum mips_split_type split_type)
2647 if (mips_split_move_p (dest, src, split_type))
2648 mips_split_move (dest, src, split_type);
2650 mips_emit_move (dest, src);
2653 /* Emit an instruction of the form (set TARGET (CODE OP0)). */
2656 mips_emit_unary (enum rtx_code code, rtx target, rtx op0)
2658 emit_insn (gen_rtx_SET (VOIDmode, target,
2659 gen_rtx_fmt_e (code, GET_MODE (op0), op0)));
2662 /* Compute (CODE OP0) and store the result in a new register of mode MODE.
2663 Return that new register. */
2666 mips_force_unary (enum machine_mode mode, enum rtx_code code, rtx op0)
2670 reg = gen_reg_rtx (mode);
2671 mips_emit_unary (code, reg, op0);
2675 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2678 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
2680 emit_insn (gen_rtx_SET (VOIDmode, target,
2681 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
2684 /* Compute (CODE OP0 OP1) and store the result in a new register
2685 of mode MODE. Return that new register. */
2688 mips_force_binary (enum machine_mode mode, enum rtx_code code, rtx op0, rtx op1)
2692 reg = gen_reg_rtx (mode);
2693 mips_emit_binary (code, reg, op0, op1);
2697 /* Copy VALUE to a register and return that register. If new pseudos
2698 are allowed, copy it into a new register, otherwise use DEST. */
2701 mips_force_temporary (rtx dest, rtx value)
2703 if (can_create_pseudo_p ())
2704 return force_reg (Pmode, value);
2707 mips_emit_move (dest, value);
2712 /* Emit a call sequence with call pattern PATTERN and return the call
2713 instruction itself (which is not necessarily the last instruction
2714 emitted). ORIG_ADDR is the original, unlegitimized address,
2715 ADDR is the legitimized form, and LAZY_P is true if the call
2716 address is lazily-bound. */
2719 mips_emit_call_insn (rtx pattern, rtx orig_addr, rtx addr, bool lazy_p)
2723 insn = emit_call_insn (pattern);
2725 if (TARGET_MIPS16 && mips_use_pic_fn_addr_reg_p (orig_addr))
2727 /* MIPS16 JALRs only take MIPS16 registers. If the target
2728 function requires $25 to be valid on entry, we must copy it
2729 there separately. The move instruction can be put in the
2730 call's delay slot. */
2731 reg = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
2732 emit_insn_before (gen_move_insn (reg, addr), insn);
2733 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
2737 /* Lazy-binding stubs require $gp to be valid on entry. */
2738 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
2742 /* See the comment above load_call<mode> for details. */
2743 use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
2744 gen_rtx_REG (Pmode, GOT_VERSION_REGNUM));
2745 emit_insn (gen_update_got_version ());
2750 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2751 then add CONST_INT OFFSET to the result. */
2754 mips_unspec_address_offset (rtx base, rtx offset,
2755 enum mips_symbol_type symbol_type)
2757 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
2758 UNSPEC_ADDRESS_FIRST + symbol_type);
2759 if (offset != const0_rtx)
2760 base = gen_rtx_PLUS (Pmode, base, offset);
2761 return gen_rtx_CONST (Pmode, base);
2764 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2765 type SYMBOL_TYPE. */
2768 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
2772 split_const (address, &base, &offset);
2773 return mips_unspec_address_offset (base, offset, symbol_type);
2776 /* If OP is an UNSPEC address, return the address to which it refers,
2777 otherwise return OP itself. */
2780 mips_strip_unspec_address (rtx op)
2784 split_const (op, &base, &offset);
2785 if (UNSPEC_ADDRESS_P (base))
2786 op = plus_constant (Pmode, UNSPEC_ADDRESS (base), INTVAL (offset));
2790 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2791 high part to BASE and return the result. Just return BASE otherwise.
2792 TEMP is as for mips_force_temporary.
2794 The returned expression can be used as the first operand to a LO_SUM. */
2797 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
2798 enum mips_symbol_type symbol_type)
2800 if (mips_split_p[symbol_type])
2802 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
2803 addr = mips_force_temporary (temp, addr);
2804 base = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
2809 /* Return an instruction that copies $gp into register REG. We want
2810 GCC to treat the register's value as constant, so that its value
2811 can be rematerialized on demand. */
2814 gen_load_const_gp (rtx reg)
2816 return PMODE_INSN (gen_load_const_gp, (reg));
2819 /* Return a pseudo register that contains the value of $gp throughout
2820 the current function. Such registers are needed by MIPS16 functions,
2821 for which $gp itself is not a valid base register or addition operand. */
2824 mips16_gp_pseudo_reg (void)
2826 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
2830 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
2832 push_topmost_sequence ();
2834 scan = get_insns ();
2835 while (NEXT_INSN (scan) && !INSN_P (NEXT_INSN (scan)))
2836 scan = NEXT_INSN (scan);
2838 insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
2839 insn = emit_insn_after (insn, scan);
2840 INSN_LOCATION (insn) = 0;
2842 pop_topmost_sequence ();
2845 return cfun->machine->mips16_gp_pseudo_rtx;
2848 /* Return a base register that holds pic_offset_table_rtx.
2849 TEMP, if nonnull, is a scratch Pmode base register. */
2852 mips_pic_base_register (rtx temp)
2855 return pic_offset_table_rtx;
2857 if (currently_expanding_to_rtl)
2858 return mips16_gp_pseudo_reg ();
2860 if (can_create_pseudo_p ())
2861 temp = gen_reg_rtx (Pmode);
2864 /* The first post-reload split exposes all references to $gp
2865 (both uses and definitions). All references must remain
2866 explicit after that point.
2868 It is safe to introduce uses of $gp at any time, so for
2869 simplicity, we do that before the split too. */
2870 mips_emit_move (temp, pic_offset_table_rtx);
2872 emit_insn (gen_load_const_gp (temp));
2876 /* Return the RHS of a load_call<mode> insn. */
2879 mips_unspec_call (rtx reg, rtx symbol)
2883 vec = gen_rtvec (3, reg, symbol, gen_rtx_REG (SImode, GOT_VERSION_REGNUM));
2884 return gen_rtx_UNSPEC (Pmode, vec, UNSPEC_LOAD_CALL);
2887 /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol
2888 reference. Return NULL_RTX otherwise. */
2891 mips_strip_unspec_call (rtx src)
2893 if (GET_CODE (src) == UNSPEC && XINT (src, 1) == UNSPEC_LOAD_CALL)
2894 return mips_strip_unspec_address (XVECEXP (src, 0, 1));
2898 /* Create and return a GOT reference of type TYPE for address ADDR.
2899 TEMP, if nonnull, is a scratch Pmode base register. */
2902 mips_got_load (rtx temp, rtx addr, enum mips_symbol_type type)
2904 rtx base, high, lo_sum_symbol;
2906 base = mips_pic_base_register (temp);
2908 /* If we used the temporary register to load $gp, we can't use
2909 it for the high part as well. */
2910 if (temp != NULL && reg_overlap_mentioned_p (base, temp))
2913 high = mips_unspec_offset_high (temp, base, addr, type);
2914 lo_sum_symbol = mips_unspec_address (addr, type);
2916 if (type == SYMBOL_GOTOFF_CALL)
2917 return mips_unspec_call (high, lo_sum_symbol);
2919 return PMODE_INSN (gen_unspec_got, (high, lo_sum_symbol));
2922 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2923 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2924 constant in that context and can be split into high and low parts.
2925 If so, and if LOW_OUT is nonnull, emit the high part and store the
2926 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
2928 TEMP is as for mips_force_temporary and is used to load the high
2929 part into a register.
2931 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
2932 a legitimize SET_SRC for an .md pattern, otherwise the low part
2933 is guaranteed to be a legitimate address for mode MODE. */
2936 mips_split_symbol (rtx temp, rtx addr, enum machine_mode mode, rtx *low_out)
2938 enum mips_symbol_context context;
2939 enum mips_symbol_type symbol_type;
2942 context = (mode == MAX_MACHINE_MODE
2943 ? SYMBOL_CONTEXT_LEA
2944 : SYMBOL_CONTEXT_MEM);
2945 if (GET_CODE (addr) == HIGH && context == SYMBOL_CONTEXT_LEA)
2947 addr = XEXP (addr, 0);
2948 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2949 && mips_symbol_insns (symbol_type, mode) > 0
2950 && mips_split_hi_p[symbol_type])
2953 switch (symbol_type)
2955 case SYMBOL_GOT_PAGE_OFST:
2956 /* The high part of a page/ofst pair is loaded from the GOT. */
2957 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_PAGE);
2968 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2969 && mips_symbol_insns (symbol_type, mode) > 0
2970 && mips_split_p[symbol_type])
2973 switch (symbol_type)
2975 case SYMBOL_GOT_DISP:
2976 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
2977 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_DISP);
2980 case SYMBOL_GP_RELATIVE:
2981 high = mips_pic_base_register (temp);
2982 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2986 high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
2987 high = mips_force_temporary (temp, high);
2988 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2997 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2998 mips_force_temporary; it is only needed when OFFSET is not a
3002 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
3004 if (!SMALL_OPERAND (offset))
3010 /* Load the full offset into a register so that we can use
3011 an unextended instruction for the address itself. */
3012 high = GEN_INT (offset);
3017 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
3018 The addition inside the macro CONST_HIGH_PART may cause an
3019 overflow, so we need to force a sign-extension check. */
3020 high = gen_int_mode (CONST_HIGH_PART (offset), Pmode);
3021 offset = CONST_LOW_PART (offset);
3023 high = mips_force_temporary (temp, high);
3024 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
3026 return plus_constant (Pmode, reg, offset);
3029 /* The __tls_get_attr symbol. */
3030 static GTY(()) rtx mips_tls_symbol;
3032 /* Return an instruction sequence that calls __tls_get_addr. SYM is
3033 the TLS symbol we are referencing and TYPE is the symbol type to use
3034 (either global dynamic or local dynamic). V0 is an RTX for the
3035 return value location. */
3038 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
3042 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
3044 if (!mips_tls_symbol)
3045 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
3047 loc = mips_unspec_address (sym, type);
3051 emit_insn (gen_rtx_SET (Pmode, a0,
3052 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
3053 insn = mips_expand_call (MIPS_CALL_NORMAL, v0, mips_tls_symbol,
3054 const0_rtx, NULL_RTX, false);
3055 RTL_CONST_CALL_P (insn) = 1;
3056 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
3057 insn = get_insns ();
3064 /* Return a pseudo register that contains the current thread pointer. */
3067 mips_expand_thread_pointer (rtx tp)
3073 mips_need_mips16_rdhwr_p = true;
3074 fn = mips16_stub_function ("__mips16_rdhwr");
3075 SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_LOCAL;
3076 if (!call_insn_operand (fn, VOIDmode))
3077 fn = force_reg (Pmode, fn);
3078 emit_insn (PMODE_INSN (gen_tls_get_tp_mips16, (tp, fn)));
3081 emit_insn (PMODE_INSN (gen_tls_get_tp, (tp)));
3088 return mips_expand_thread_pointer (gen_reg_rtx (Pmode));
3091 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
3092 its address. The return value will be both a valid address and a valid
3093 SET_SRC (either a REG or a LO_SUM). */
3096 mips_legitimize_tls_address (rtx loc)
3098 rtx dest, insn, v0, tp, tmp1, tmp2, eqv, offset;
3099 enum tls_model model;
3101 model = SYMBOL_REF_TLS_MODEL (loc);
3102 /* Only TARGET_ABICALLS code can have more than one module; other
3103 code must be be static and should not use a GOT. All TLS models
3104 reduce to local exec in this situation. */
3105 if (!TARGET_ABICALLS)
3106 model = TLS_MODEL_LOCAL_EXEC;
3110 case TLS_MODEL_GLOBAL_DYNAMIC:
3111 v0 = gen_rtx_REG (Pmode, GP_RETURN);
3112 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
3113 dest = gen_reg_rtx (Pmode);
3114 emit_libcall_block (insn, dest, v0, loc);
3117 case TLS_MODEL_LOCAL_DYNAMIC:
3118 v0 = gen_rtx_REG (Pmode, GP_RETURN);
3119 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
3120 tmp1 = gen_reg_rtx (Pmode);
3122 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
3123 share the LDM result with other LD model accesses. */
3124 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3126 emit_libcall_block (insn, tmp1, v0, eqv);
3128 offset = mips_unspec_address (loc, SYMBOL_DTPREL);
3129 if (mips_split_p[SYMBOL_DTPREL])
3131 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
3132 dest = gen_rtx_LO_SUM (Pmode, tmp2, offset);
3135 dest = expand_binop (Pmode, add_optab, tmp1, offset,
3136 0, 0, OPTAB_DIRECT);
3139 case TLS_MODEL_INITIAL_EXEC:
3140 tp = mips_get_tp ();
3141 tmp1 = gen_reg_rtx (Pmode);
3142 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
3143 if (Pmode == DImode)
3144 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
3146 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
3147 dest = gen_reg_rtx (Pmode);
3148 emit_insn (gen_add3_insn (dest, tmp1, tp));
3151 case TLS_MODEL_LOCAL_EXEC:
3152 tmp1 = mips_get_tp ();
3153 offset = mips_unspec_address (loc, SYMBOL_TPREL);
3154 if (mips_split_p[SYMBOL_TPREL])
3156 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_TPREL);
3157 dest = gen_rtx_LO_SUM (Pmode, tmp2, offset);
3160 dest = expand_binop (Pmode, add_optab, tmp1, offset,
3161 0, 0, OPTAB_DIRECT);
3170 /* If X is not a valid address for mode MODE, force it into a register. */
3173 mips_force_address (rtx x, enum machine_mode mode)
3175 if (!mips_legitimate_address_p (mode, x, false))
3176 x = force_reg (Pmode, x);
3180 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
3181 be legitimized in a way that the generic machinery might not expect,
3182 return a new address, otherwise return NULL. MODE is the mode of
3183 the memory being accessed. */
3186 mips_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3187 enum machine_mode mode)
3190 HOST_WIDE_INT offset;
3192 if (mips_tls_symbol_p (x))
3193 return mips_legitimize_tls_address (x);
3195 /* See if the address can split into a high part and a LO_SUM. */
3196 if (mips_split_symbol (NULL, x, mode, &addr))
3197 return mips_force_address (addr, mode);
3199 /* Handle BASE + OFFSET using mips_add_offset. */
3200 mips_split_plus (x, &base, &offset);
3203 if (!mips_valid_base_register_p (base, mode, false))
3204 base = copy_to_mode_reg (Pmode, base);
3205 addr = mips_add_offset (NULL, base, offset);
3206 return mips_force_address (addr, mode);
3212 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
3215 mips_move_integer (rtx temp, rtx dest, unsigned HOST_WIDE_INT value)
3217 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
3218 enum machine_mode mode;
3219 unsigned int i, num_ops;
3222 mode = GET_MODE (dest);
3223 num_ops = mips_build_integer (codes, value);
3225 /* Apply each binary operation to X. Invariant: X is a legitimate
3226 source operand for a SET pattern. */
3227 x = GEN_INT (codes[0].value);
3228 for (i = 1; i < num_ops; i++)
3230 if (!can_create_pseudo_p ())
3232 emit_insn (gen_rtx_SET (VOIDmode, temp, x));
3236 x = force_reg (mode, x);
3237 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
3240 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
3243 /* Subroutine of mips_legitimize_move. Move constant SRC into register
3244 DEST given that SRC satisfies immediate_operand but doesn't satisfy
3248 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
3252 /* Split moves of big integers into smaller pieces. */
3253 if (splittable_const_int_operand (src, mode))
3255 mips_move_integer (dest, dest, INTVAL (src));
3259 /* Split moves of symbolic constants into high/low pairs. */
3260 if (mips_split_symbol (dest, src, MAX_MACHINE_MODE, &src))
3262 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
3266 /* Generate the appropriate access sequences for TLS symbols. */
3267 if (mips_tls_symbol_p (src))
3269 mips_emit_move (dest, mips_legitimize_tls_address (src));
3273 /* If we have (const (plus symbol offset)), and that expression cannot
3274 be forced into memory, load the symbol first and add in the offset.
3275 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
3276 forced into memory, as it usually produces better code. */
3277 split_const (src, &base, &offset);
3278 if (offset != const0_rtx
3279 && (targetm.cannot_force_const_mem (mode, src)
3280 || (!TARGET_MIPS16 && can_create_pseudo_p ())))
3282 base = mips_force_temporary (dest, base);
3283 mips_emit_move (dest, mips_add_offset (NULL, base, INTVAL (offset)));
3287 src = force_const_mem (mode, src);
3289 /* When using explicit relocs, constant pool references are sometimes
3290 not legitimate addresses. */
3291 mips_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0));
3292 mips_emit_move (dest, src);
3295 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
3296 sequence that is valid. */
3299 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
3301 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
3303 mips_emit_move (dest, force_reg (mode, src));
3307 /* We need to deal with constants that would be legitimate
3308 immediate_operands but aren't legitimate move_operands. */
3309 if (CONSTANT_P (src) && !move_operand (src, mode))
3311 mips_legitimize_const_move (mode, dest, src);
3312 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
3318 /* Return true if value X in context CONTEXT is a small-data address
3319 that can be rewritten as a LO_SUM. */
3322 mips_rewrite_small_data_p (rtx x, enum mips_symbol_context context)
3324 enum mips_symbol_type symbol_type;
3326 return (mips_lo_relocs[SYMBOL_GP_RELATIVE]
3327 && !mips_split_p[SYMBOL_GP_RELATIVE]
3328 && mips_symbolic_constant_p (x, context, &symbol_type)
3329 && symbol_type == SYMBOL_GP_RELATIVE);
3332 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
3333 containing MEM, or null if none. */
3336 mips_small_data_pattern_1 (rtx *loc, void *data)
3338 enum mips_symbol_context context;
3340 /* Ignore things like "g" constraints in asms. We make no particular
3341 guarantee about which symbolic constants are acceptable as asm operands
3342 versus which must be forced into a GPR. */
3343 if (GET_CODE (*loc) == LO_SUM || GET_CODE (*loc) == ASM_OPERANDS)
3348 if (for_each_rtx (&XEXP (*loc, 0), mips_small_data_pattern_1, *loc))
3353 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3354 return mips_rewrite_small_data_p (*loc, context);
3357 /* Return true if OP refers to small data symbols directly, not through
3361 mips_small_data_pattern_p (rtx op)
3363 return for_each_rtx (&op, mips_small_data_pattern_1, NULL);
3366 /* A for_each_rtx callback, used by mips_rewrite_small_data.
3367 DATA is the containing MEM, or null if none. */
3370 mips_rewrite_small_data_1 (rtx *loc, void *data)
3372 enum mips_symbol_context context;
3376 for_each_rtx (&XEXP (*loc, 0), mips_rewrite_small_data_1, *loc);
3380 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3381 if (mips_rewrite_small_data_p (*loc, context))
3382 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
3384 if (GET_CODE (*loc) == LO_SUM)
3390 /* Rewrite instruction pattern PATTERN so that it refers to small data
3391 using explicit relocations. */
3394 mips_rewrite_small_data (rtx pattern)
3396 pattern = copy_insn (pattern);
3397 for_each_rtx (&pattern, mips_rewrite_small_data_1, NULL);
3401 /* The cost of loading values from the constant pool. It should be
3402 larger than the cost of any constant we want to synthesize inline. */
3403 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3405 /* Return the cost of X when used as an operand to the MIPS16 instruction
3406 that implements CODE. Return -1 if there is no such instruction, or if
3407 X is not a valid immediate operand for it. */
3410 mips16_constant_cost (int code, HOST_WIDE_INT x)
3417 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3418 other shifts are extended. The shift patterns truncate the shift
3419 count to the right size, so there are no out-of-range values. */
3420 if (IN_RANGE (x, 1, 8))
3422 return COSTS_N_INSNS (1);
3425 if (IN_RANGE (x, -128, 127))
3427 if (SMALL_OPERAND (x))
3428 return COSTS_N_INSNS (1);
3432 /* Like LE, but reject the always-true case. */
3436 /* We add 1 to the immediate and use SLT. */
3439 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3442 if (IN_RANGE (x, 0, 255))
3444 if (SMALL_OPERAND_UNSIGNED (x))
3445 return COSTS_N_INSNS (1);
3450 /* Equality comparisons with 0 are cheap. */
3460 /* Return true if there is a non-MIPS16 instruction that implements CODE
3461 and if that instruction accepts X as an immediate operand. */
3464 mips_immediate_operand_p (int code, HOST_WIDE_INT x)
3471 /* All shift counts are truncated to a valid constant. */
3476 /* Likewise rotates, if the target supports rotates at all. */
3482 /* These instructions take 16-bit unsigned immediates. */
3483 return SMALL_OPERAND_UNSIGNED (x);
3488 /* These instructions take 16-bit signed immediates. */
3489 return SMALL_OPERAND (x);
3495 /* The "immediate" forms of these instructions are really
3496 implemented as comparisons with register 0. */
3501 /* Likewise, meaning that the only valid immediate operand is 1. */
3505 /* We add 1 to the immediate and use SLT. */
3506 return SMALL_OPERAND (x + 1);
3509 /* Likewise SLTU, but reject the always-true case. */
3510 return SMALL_OPERAND (x + 1) && x + 1 != 0;
3514 /* The bit position and size are immediate operands. */
3515 return ISA_HAS_EXT_INS;
3518 /* By default assume that $0 can be used for 0. */
3523 /* Return the cost of binary operation X, given that the instruction
3524 sequence for a word-sized or smaller operation has cost SINGLE_COST
3525 and that the sequence of a double-word operation has cost DOUBLE_COST.
3526 If SPEED is true, optimize for speed otherwise optimize for size. */
3529 mips_binary_cost (rtx x, int single_cost, int double_cost, bool speed)
3533 if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2)
3538 + set_src_cost (XEXP (x, 0), speed)
3539 + rtx_cost (XEXP (x, 1), GET_CODE (x), 1, speed));
3542 /* Return the cost of floating-point multiplications of mode MODE. */
3545 mips_fp_mult_cost (enum machine_mode mode)
3547 return mode == DFmode ? mips_cost->fp_mult_df : mips_cost->fp_mult_sf;
3550 /* Return the cost of floating-point divisions of mode MODE. */
3553 mips_fp_div_cost (enum machine_mode mode)
3555 return mode == DFmode ? mips_cost->fp_div_df : mips_cost->fp_div_sf;
3558 /* Return the cost of sign-extending OP to mode MODE, not including the
3559 cost of OP itself. */
3562 mips_sign_extend_cost (enum machine_mode mode, rtx op)
3565 /* Extended loads are as cheap as unextended ones. */
3568 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3569 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3572 if (ISA_HAS_SEB_SEH || GENERATE_MIPS16E)
3573 /* We can use SEB or SEH. */
3574 return COSTS_N_INSNS (1);
3576 /* We need to use a shift left and a shift right. */
3577 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3580 /* Return the cost of zero-extending OP to mode MODE, not including the
3581 cost of OP itself. */
3584 mips_zero_extend_cost (enum machine_mode mode, rtx op)
3587 /* Extended loads are as cheap as unextended ones. */
3590 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3591 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3592 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3594 if (GENERATE_MIPS16E)
3595 /* We can use ZEB or ZEH. */
3596 return COSTS_N_INSNS (1);
3599 /* We need to load 0xff or 0xffff into a register and use AND. */
3600 return COSTS_N_INSNS (GET_MODE (op) == QImode ? 2 : 3);
3602 /* We can use ANDI. */
3603 return COSTS_N_INSNS (1);
3606 /* Return the cost of moving between two registers of mode MODE,
3607 assuming that the move will be in pieces of at most UNITS bytes. */
3610 mips_set_reg_reg_piece_cost (enum machine_mode mode, unsigned int units)
3612 return COSTS_N_INSNS ((GET_MODE_SIZE (mode) + units - 1) / units);
3615 /* Return the cost of moving between two registers of mode MODE. */
3618 mips_set_reg_reg_cost (enum machine_mode mode)
3620 switch (GET_MODE_CLASS (mode))
3623 return mips_set_reg_reg_piece_cost (mode, GET_MODE_SIZE (CCmode));
3626 case MODE_COMPLEX_FLOAT:
3627 case MODE_VECTOR_FLOAT:
3628 if (TARGET_HARD_FLOAT)
3629 return mips_set_reg_reg_piece_cost (mode, UNITS_PER_HWFPVALUE);
3633 return mips_set_reg_reg_piece_cost (mode, UNITS_PER_WORD);
3637 /* Implement TARGET_RTX_COSTS. */
3640 mips_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
3641 int *total, bool speed)
3643 enum machine_mode mode = GET_MODE (x);
3644 bool float_mode_p = FLOAT_MODE_P (mode);
3648 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3649 appear in the instruction stream, and the cost of a comparison is
3650 really the cost of the branch or scc condition. At the time of
3651 writing, GCC only uses an explicit outer COMPARE code when optabs
3652 is testing whether a constant is expensive enough to force into a
3653 register. We want optabs to pass such constants through the MIPS
3654 expanders instead, so make all constants very cheap here. */
3655 if (outer_code == COMPARE)
3657 gcc_assert (CONSTANT_P (x));
3665 /* Treat *clear_upper32-style ANDs as having zero cost in the
3666 second operand. The cost is entirely in the first operand.
3668 ??? This is needed because we would otherwise try to CSE
3669 the constant operand. Although that's the right thing for
3670 instructions that continue to be a register operation throughout
3671 compilation, it is disastrous for instructions that could
3672 later be converted into a memory operation. */
3674 && outer_code == AND
3675 && UINTVAL (x) == 0xffffffff)
3683 cost = mips16_constant_cost (outer_code, INTVAL (x));
3692 /* When not optimizing for size, we care more about the cost
3693 of hot code, and hot code is often in a loop. If a constant
3694 operand needs to be forced into a register, we will often be
3695 able to hoist the constant load out of the loop, so the load
3696 should not contribute to the cost. */
3697 if (speed || mips_immediate_operand_p (outer_code, INTVAL (x)))
3709 if (force_to_mem_operand (x, VOIDmode))
3711 *total = COSTS_N_INSNS (1);
3714 cost = mips_const_insns (x);
3717 /* If the constant is likely to be stored in a GPR, SETs of
3718 single-insn constants are as cheap as register sets; we
3719 never want to CSE them.
3721 Don't reduce the cost of storing a floating-point zero in
3722 FPRs. If we have a zero in an FPR for other reasons, we
3723 can get better cfg-cleanup and delayed-branch results by
3724 using it consistently, rather than using $0 sometimes and
3725 an FPR at other times. Also, moves between floating-point
3726 registers are sometimes cheaper than (D)MTC1 $0. */
3728 && outer_code == SET
3729 && !(float_mode_p && TARGET_HARD_FLOAT))
3731 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3732 want to CSE the constant itself. It is usually better to
3733 have N copies of the last operation in the sequence and one
3734 shared copy of the other operations. (Note that this is
3735 not true for MIPS16 code, where the final operation in the
3736 sequence is often an extended instruction.)
3738 Also, if we have a CONST_INT, we don't know whether it is
3739 for a word or doubleword operation, so we cannot rely on
3740 the result of mips_build_integer. */
3741 else if (!TARGET_MIPS16
3742 && (outer_code == SET || mode == VOIDmode))
3744 *total = COSTS_N_INSNS (cost);
3747 /* The value will need to be fetched from the constant pool. */
3748 *total = CONSTANT_POOL_COST;
3752 /* If the address is legitimate, return the number of
3753 instructions it needs. */
3755 cost = mips_address_insns (addr, mode, true);
3758 *total = COSTS_N_INSNS (cost + 1);
3761 /* Check for a scaled indexed address. */
3762 if (mips_lwxs_address_p (addr)
3763 || mips_lx_address_p (addr, mode))
3765 *total = COSTS_N_INSNS (2);
3768 /* Otherwise use the default handling. */
3772 *total = COSTS_N_INSNS (6);
3776 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1);
3780 /* Check for a *clear_upper32 pattern and treat it like a zero
3781 extension. See the pattern's comment for details. */
3784 && CONST_INT_P (XEXP (x, 1))
3785 && UINTVAL (XEXP (x, 1)) == 0xffffffff)
3787 *total = (mips_zero_extend_cost (mode, XEXP (x, 0))
3788 + set_src_cost (XEXP (x, 0), speed));
3791 if (ISA_HAS_CINS && CONST_INT_P (XEXP (x, 1)))
3793 rtx op = XEXP (x, 0);
3794 if (GET_CODE (op) == ASHIFT
3795 && CONST_INT_P (XEXP (op, 1))
3796 && mask_low_and_shift_p (mode, XEXP (x, 1), XEXP (op, 1), 32))
3798 *total = COSTS_N_INSNS (1) + set_src_cost (XEXP (op, 0), speed);
3802 /* (AND (NOT op0) (NOT op1) is a nor operation that can be done in
3803 a single instruction. */
3805 && GET_CODE (XEXP (x, 0)) == NOT
3806 && GET_CODE (XEXP (x, 1)) == NOT)
3808 cost = GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1;
3809 *total = (COSTS_N_INSNS (cost)
3810 + set_src_cost (XEXP (XEXP (x, 0), 0), speed)
3811 + set_src_cost (XEXP (XEXP (x, 1), 0), speed));
3819 /* Double-word operations use two single-word operations. */
3820 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (2),
3829 if (CONSTANT_P (XEXP (x, 1)))
3830 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3833 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (12),
3839 *total = mips_cost->fp_add;
3841 *total = COSTS_N_INSNS (4);
3845 /* Low-part immediates need an extended MIPS16 instruction. */
3846 *total = (COSTS_N_INSNS (TARGET_MIPS16 ? 2 : 1)
3847 + set_src_cost (XEXP (x, 0), speed));
3862 /* Branch comparisons have VOIDmode, so use the first operand's
3864 mode = GET_MODE (XEXP (x, 0));
3865 if (FLOAT_MODE_P (mode))
3867 *total = mips_cost->fp_add;
3870 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3876 && (ISA_HAS_NMADD4_NMSUB4 || ISA_HAS_NMADD3_NMSUB3)
3877 && TARGET_FUSED_MADD
3878 && !HONOR_NANS (mode)
3879 && !HONOR_SIGNED_ZEROS (mode))
3881 /* See if we can use NMADD or NMSUB. See mips.md for the
3882 associated patterns. */
3883 rtx op0 = XEXP (x, 0);
3884 rtx op1 = XEXP (x, 1);
3885 if (GET_CODE (op0) == MULT && GET_CODE (XEXP (op0, 0)) == NEG)
3887 *total = (mips_fp_mult_cost (mode)
3888 + set_src_cost (XEXP (XEXP (op0, 0), 0), speed)
3889 + set_src_cost (XEXP (op0, 1), speed)
3890 + set_src_cost (op1, speed));
3893 if (GET_CODE (op1) == MULT)
3895 *total = (mips_fp_mult_cost (mode)
3896 + set_src_cost (op0, speed)
3897 + set_src_cost (XEXP (op1, 0), speed)
3898 + set_src_cost (XEXP (op1, 1), speed));
3907 /* If this is part of a MADD or MSUB, treat the PLUS as
3909 if ((ISA_HAS_FP_MADD4_MSUB4 || ISA_HAS_FP_MADD3_MSUB3)
3910 && TARGET_FUSED_MADD
3911 && GET_CODE (XEXP (x, 0)) == MULT)
3914 *total = mips_cost->fp_add;
3918 /* Double-word operations require three single-word operations and
3919 an SLTU. The MIPS16 version then needs to move the result of
3920 the SLTU from $24 to a MIPS16 register. */
3921 *total = mips_binary_cost (x, COSTS_N_INSNS (1),
3922 COSTS_N_INSNS (TARGET_MIPS16 ? 5 : 4),
3928 && (ISA_HAS_NMADD4_NMSUB4 || ISA_HAS_NMADD3_NMSUB3)
3929 && TARGET_FUSED_MADD
3930 && !HONOR_NANS (mode)
3931 && HONOR_SIGNED_ZEROS (mode))
3933 /* See if we can use NMADD or NMSUB. See mips.md for the
3934 associated patterns. */
3935 rtx op = XEXP (x, 0);
3936 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
3937 && GET_CODE (XEXP (op, 0)) == MULT)
3939 *total = (mips_fp_mult_cost (mode)
3940 + set_src_cost (XEXP (XEXP (op, 0), 0), speed)
3941 + set_src_cost (XEXP (XEXP (op, 0), 1), speed)
3942 + set_src_cost (XEXP (op, 1), speed));
3948 *total = mips_cost->fp_add;
3950 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1);
3955 *total = mips_fp_mult_cost (mode);
3956 else if (mode == DImode && !TARGET_64BIT)
3957 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
3958 where the mulsidi3 always includes an MFHI and an MFLO. */
3960 ? mips_cost->int_mult_si * 3 + 6
3961 : COSTS_N_INSNS (ISA_HAS_MUL3 ? 7 : 9));
3963 *total = COSTS_N_INSNS (ISA_HAS_MUL3 ? 1 : 2) + 1;
3964 else if (mode == DImode)
3965 *total = mips_cost->int_mult_di;
3967 *total = mips_cost->int_mult_si;
3971 /* Check for a reciprocal. */
3973 && ISA_HAS_FP_RECIP_RSQRT (mode)
3974 && flag_unsafe_math_optimizations
3975 && XEXP (x, 0) == CONST1_RTX (mode))
3977 if (outer_code == SQRT || GET_CODE (XEXP (x, 1)) == SQRT)
3978 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
3979 division as being free. */
3980 *total = set_src_cost (XEXP (x, 1), speed);
3982 *total = (mips_fp_div_cost (mode)
3983 + set_src_cost (XEXP (x, 1), speed));
3992 *total = mips_fp_div_cost (mode);
4001 /* It is our responsibility to make division by a power of 2
4002 as cheap as 2 register additions if we want the division
4003 expanders to be used for such operations; see the setting
4004 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
4005 should always produce shorter code than using
4006 expand_sdiv2_pow2. */
4008 && CONST_INT_P (XEXP (x, 1))
4009 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
4011 *total = COSTS_N_INSNS (2) + set_src_cost (XEXP (x, 0), speed);
4014 *total = COSTS_N_INSNS (mips_idiv_insns ());
4016 else if (mode == DImode)
4017 *total = mips_cost->int_div_di;
4019 *total = mips_cost->int_div_si;
4023 *total = mips_sign_extend_cost (mode, XEXP (x, 0));
4027 if (outer_code == SET
4029 && (GET_CODE (XEXP (x, 0)) == TRUNCATE
4030 || GET_CODE (XEXP (x, 0)) == SUBREG)
4031 && GET_MODE (XEXP (x, 0)) == QImode
4032 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
4034 *total = set_src_cost (XEXP (XEXP (x, 0), 0), speed);
4037 *total = mips_zero_extend_cost (mode, XEXP (x, 0));
4041 case UNSIGNED_FLOAT:
4044 case FLOAT_TRUNCATE:
4045 *total = mips_cost->fp_add;
4049 if (register_operand (SET_DEST (x), VOIDmode)
4050 && reg_or_0_operand (SET_SRC (x), VOIDmode))
4052 *total = mips_set_reg_reg_cost (GET_MODE (SET_DEST (x)));
4062 /* Implement TARGET_ADDRESS_COST. */
4065 mips_address_cost (rtx addr, enum machine_mode mode,
4066 addr_space_t as ATTRIBUTE_UNUSED,
4067 bool speed ATTRIBUTE_UNUSED)
4069 return mips_address_insns (addr, mode, false);
4072 /* Information about a single instruction in a multi-instruction
4074 struct mips_multi_member {
4075 /* True if this is a label, false if it is code. */
4078 /* The output_asm_insn format of the instruction. */
4081 /* The operands to the instruction. */
4082 rtx operands[MAX_RECOG_OPERANDS];
4084 typedef struct mips_multi_member mips_multi_member;
4086 /* The instructions that make up the current multi-insn sequence. */
4087 static vec<mips_multi_member> mips_multi_members;
4089 /* How many instructions (as opposed to labels) are in the current
4090 multi-insn sequence. */
4091 static unsigned int mips_multi_num_insns;
4093 /* Start a new multi-insn sequence. */
4096 mips_multi_start (void)
4098 mips_multi_members.truncate (0);
4099 mips_multi_num_insns = 0;
4102 /* Add a new, uninitialized member to the current multi-insn sequence. */
4104 static struct mips_multi_member *
4105 mips_multi_add (void)
4107 mips_multi_member empty;
4108 return mips_multi_members.safe_push (empty);
4111 /* Add a normal insn with the given asm format to the current multi-insn
4112 sequence. The other arguments are a null-terminated list of operands. */
4115 mips_multi_add_insn (const char *format, ...)
4117 struct mips_multi_member *member;
4122 member = mips_multi_add ();
4123 member->is_label_p = false;
4124 member->format = format;
4125 va_start (ap, format);
4127 while ((op = va_arg (ap, rtx)))
4128 member->operands[i++] = op;
4130 mips_multi_num_insns++;
4133 /* Add the given label definition to the current multi-insn sequence.
4134 The definition should include the colon. */
4137 mips_multi_add_label (const char *label)
4139 struct mips_multi_member *member;
4141 member = mips_multi_add ();
4142 member->is_label_p = true;
4143 member->format = label;
4146 /* Return the index of the last member of the current multi-insn sequence. */
4149 mips_multi_last_index (void)
4151 return mips_multi_members.length () - 1;
4154 /* Add a copy of an existing instruction to the current multi-insn
4155 sequence. I is the index of the instruction that should be copied. */
4158 mips_multi_copy_insn (unsigned int i)
4160 struct mips_multi_member *member;
4162 member = mips_multi_add ();
4163 memcpy (member, &mips_multi_members[i], sizeof (*member));
4164 gcc_assert (!member->is_label_p);
4167 /* Change the operand of an existing instruction in the current
4168 multi-insn sequence. I is the index of the instruction,
4169 OP is the index of the operand, and X is the new value. */
4172 mips_multi_set_operand (unsigned int i, unsigned int op, rtx x)
4174 mips_multi_members[i].operands[op] = x;
4177 /* Write out the asm code for the current multi-insn sequence. */
4180 mips_multi_write (void)
4182 struct mips_multi_member *member;
4185 FOR_EACH_VEC_ELT (mips_multi_members, i, member)
4186 if (member->is_label_p)
4187 fprintf (asm_out_file, "%s\n", member->format);
4189 output_asm_insn (member->format, member->operands);
4192 /* Return one word of double-word value OP, taking into account the fixed
4193 endianness of certain registers. HIGH_P is true to select the high part,
4194 false to select the low part. */
4197 mips_subword (rtx op, bool high_p)
4199 unsigned int byte, offset;
4200 enum machine_mode mode;
4202 mode = GET_MODE (op);
4203 if (mode == VOIDmode)
4204 mode = TARGET_64BIT ? TImode : DImode;
4206 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
4207 byte = UNITS_PER_WORD;
4211 if (FP_REG_RTX_P (op))
4213 /* Paired FPRs are always ordered little-endian. */
4214 offset = (UNITS_PER_WORD < UNITS_PER_HWFPVALUE ? high_p : byte != 0);
4215 return gen_rtx_REG (word_mode, REGNO (op) + offset);
4219 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
4221 return simplify_gen_subreg (word_mode, op, mode, byte);
4224 /* Return true if SRC should be moved into DEST using "MULT $0, $0".
4225 SPLIT_TYPE is the condition under which moves should be split. */
4228 mips_mult_move_p (rtx dest, rtx src, enum mips_split_type split_type)
4230 return ((split_type != SPLIT_FOR_SPEED
4231 || mips_tuning_info.fast_mult_zero_zero_p)
4232 && src == const0_rtx
4234 && GET_MODE_SIZE (GET_MODE (dest)) == 2 * UNITS_PER_WORD
4235 && (ISA_HAS_DSP_MULT
4236 ? ACC_REG_P (REGNO (dest))
4237 : MD_REG_P (REGNO (dest))));
4240 /* Return true if a move from SRC to DEST should be split into two.
4241 SPLIT_TYPE describes the split condition. */
4244 mips_split_move_p (rtx dest, rtx src, enum mips_split_type split_type)
4246 /* Check whether the move can be done using some variant of MULT $0,$0. */
4247 if (mips_mult_move_p (dest, src, split_type))
4250 /* FPR-to-FPR moves can be done in a single instruction, if they're
4252 unsigned int size = GET_MODE_SIZE (GET_MODE (dest));
4253 if (size == 8 && FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
4256 /* Check for floating-point loads and stores. */
4257 if (size == 8 && ISA_HAS_LDC1_SDC1)
4259 if (FP_REG_RTX_P (dest) && MEM_P (src))
4261 if (FP_REG_RTX_P (src) && MEM_P (dest))
4265 /* Otherwise split all multiword moves. */
4266 return size > UNITS_PER_WORD;
4269 /* Split a move from SRC to DEST, given that mips_split_move_p holds.
4270 SPLIT_TYPE describes the split condition. */
4273 mips_split_move (rtx dest, rtx src, enum mips_split_type split_type)
4277 gcc_checking_assert (mips_split_move_p (dest, src, split_type));
4278 if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src))
4280 if (!TARGET_64BIT && GET_MODE (dest) == DImode)
4281 emit_insn (gen_move_doubleword_fprdi (dest, src));
4282 else if (!TARGET_64BIT && GET_MODE (dest) == DFmode)
4283 emit_insn (gen_move_doubleword_fprdf (dest, src));
4284 else if (!TARGET_64BIT && GET_MODE (dest) == V2SFmode)
4285 emit_insn (gen_move_doubleword_fprv2sf (dest, src));
4286 else if (!TARGET_64BIT && GET_MODE (dest) == V2SImode)
4287 emit_insn (gen_move_doubleword_fprv2si (dest, src));
4288 else if (!TARGET_64BIT && GET_MODE (dest) == V4HImode)
4289 emit_insn (gen_move_doubleword_fprv4hi (dest, src));
4290 else if (!TARGET_64BIT && GET_MODE (dest) == V8QImode)
4291 emit_insn (gen_move_doubleword_fprv8qi (dest, src));
4292 else if (TARGET_64BIT && GET_MODE (dest) == TFmode)
4293 emit_insn (gen_move_doubleword_fprtf (dest, src));
4297 else if (REG_P (dest) && REGNO (dest) == MD_REG_FIRST)
4299 low_dest = mips_subword (dest, false);
4300 mips_emit_move (low_dest, mips_subword (src, false));
4302 emit_insn (gen_mthidi_ti (dest, mips_subword (src, true), low_dest));
4304 emit_insn (gen_mthisi_di (dest, mips_subword (src, true), low_dest));
4306 else if (REG_P (src) && REGNO (src) == MD_REG_FIRST)
4308 mips_emit_move (mips_subword (dest, false), mips_subword (src, false));
4310 emit_insn (gen_mfhidi_ti (mips_subword (dest, true), src));
4312 emit_insn (gen_mfhisi_di (mips_subword (dest, true), src));
4316 /* The operation can be split into two normal moves. Decide in
4317 which order to do them. */
4318 low_dest = mips_subword (dest, false);
4319 if (REG_P (low_dest)
4320 && reg_overlap_mentioned_p (low_dest, src))
4322 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4323 mips_emit_move (low_dest, mips_subword (src, false));
4327 mips_emit_move (low_dest, mips_subword (src, false));
4328 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4333 /* Return the split type for instruction INSN. */
4335 static enum mips_split_type
4336 mips_insn_split_type (rtx insn)
4338 basic_block bb = BLOCK_FOR_INSN (insn);
4341 if (optimize_bb_for_speed_p (bb))
4342 return SPLIT_FOR_SPEED;
4344 return SPLIT_FOR_SIZE;
4346 /* Once CFG information has been removed, we should trust the optimization
4347 decisions made by previous passes and only split where necessary. */
4348 return SPLIT_IF_NECESSARY;
4351 /* Return true if a move from SRC to DEST in INSN should be split. */
4354 mips_split_move_insn_p (rtx dest, rtx src, rtx insn)
4356 return mips_split_move_p (dest, src, mips_insn_split_type (insn));
4359 /* Split a move from SRC to DEST in INSN, given that mips_split_move_insn_p
4363 mips_split_move_insn (rtx dest, rtx src, rtx insn)
4365 mips_split_move (dest, src, mips_insn_split_type (insn));
4368 /* Return the appropriate instructions to move SRC into DEST. Assume
4369 that SRC is operand 1 and DEST is operand 0. */
4372 mips_output_move (rtx dest, rtx src)
4374 enum rtx_code dest_code, src_code;
4375 enum machine_mode mode;
4376 enum mips_symbol_type symbol_type;
4379 dest_code = GET_CODE (dest);
4380 src_code = GET_CODE (src);
4381 mode = GET_MODE (dest);
4382 dbl_p = (GET_MODE_SIZE (mode) == 8);
4384 if (mips_split_move_p (dest, src, SPLIT_IF_NECESSARY))
4387 if ((src_code == REG && GP_REG_P (REGNO (src)))
4388 || (!TARGET_MIPS16 && src == CONST0_RTX (mode)))
4390 if (dest_code == REG)
4392 if (GP_REG_P (REGNO (dest)))
4393 return "move\t%0,%z1";
4395 if (mips_mult_move_p (dest, src, SPLIT_IF_NECESSARY))
4397 if (ISA_HAS_DSP_MULT)
4398 return "mult\t%q0,%.,%.";
4400 return "mult\t%.,%.";
4403 /* Moves to HI are handled by special .md insns. */
4404 if (REGNO (dest) == LO_REGNUM)
4407 if (DSP_ACC_REG_P (REGNO (dest)))
4409 static char retval[] = "mt__\t%z1,%q0";
4411 retval[2] = reg_names[REGNO (dest)][4];
4412 retval[3] = reg_names[REGNO (dest)][5];
4416 if (FP_REG_P (REGNO (dest)))
4417 return dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
4419 if (ALL_COP_REG_P (REGNO (dest)))
4421 static char retval[] = "dmtc_\t%z1,%0";
4423 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4424 return dbl_p ? retval : retval + 1;
4427 if (dest_code == MEM)
4428 switch (GET_MODE_SIZE (mode))
4430 case 1: return "sb\t%z1,%0";
4431 case 2: return "sh\t%z1,%0";
4432 case 4: return "sw\t%z1,%0";
4433 case 8: return "sd\t%z1,%0";
4436 if (dest_code == REG && GP_REG_P (REGNO (dest)))
4438 if (src_code == REG)
4440 /* Moves from HI are handled by special .md insns. */
4441 if (REGNO (src) == LO_REGNUM)
4443 /* When generating VR4120 or VR4130 code, we use MACC and
4444 DMACC instead of MFLO. This avoids both the normal
4445 MIPS III HI/LO hazards and the errata related to
4448 return dbl_p ? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
4452 if (DSP_ACC_REG_P (REGNO (src)))
4454 static char retval[] = "mf__\t%0,%q1";
4456 retval[2] = reg_names[REGNO (src)][4];
4457 retval[3] = reg_names[REGNO (src)][5];
4461 if (FP_REG_P (REGNO (src)))
4462 return dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
4464 if (ALL_COP_REG_P (REGNO (src)))
4466 static char retval[] = "dmfc_\t%0,%1";
4468 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4469 return dbl_p ? retval : retval + 1;
4473 if (src_code == MEM)
4474 switch (GET_MODE_SIZE (mode))
4476 case 1: return "lbu\t%0,%1";
4477 case 2: return "lhu\t%0,%1";
4478 case 4: return "lw\t%0,%1";
4479 case 8: return "ld\t%0,%1";
4482 if (src_code == CONST_INT)
4484 /* Don't use the X format for the operand itself, because that
4485 will give out-of-range numbers for 64-bit hosts and 32-bit
4488 return "li\t%0,%1\t\t\t# %X1";
4490 if (SMALL_OPERAND_UNSIGNED (INTVAL (src)))
4493 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src)))
4497 if (src_code == HIGH)
4498 return TARGET_MIPS16 ? "#" : "lui\t%0,%h1";
4500 if (CONST_GP_P (src))
4501 return "move\t%0,%1";
4503 if (mips_symbolic_constant_p (src, SYMBOL_CONTEXT_LEA, &symbol_type)
4504 && mips_lo_relocs[symbol_type] != 0)
4506 /* A signed 16-bit constant formed by applying a relocation
4507 operator to a symbolic address. */
4508 gcc_assert (!mips_split_p[symbol_type]);
4509 return "li\t%0,%R1";
4512 if (symbolic_operand (src, VOIDmode))
4514 gcc_assert (TARGET_MIPS16
4515 ? TARGET_MIPS16_TEXT_LOADS
4516 : !TARGET_EXPLICIT_RELOCS);
4517 return dbl_p ? "dla\t%0,%1" : "la\t%0,%1";
4520 if (src_code == REG && FP_REG_P (REGNO (src)))
4522 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4524 if (GET_MODE (dest) == V2SFmode)
4525 return "mov.ps\t%0,%1";
4527 return dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1";
4530 if (dest_code == MEM)
4531 return dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0";
4533 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4535 if (src_code == MEM)
4536 return dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1";
4538 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
4540 static char retval[] = "l_c_\t%0,%1";
4542 retval[1] = (dbl_p ? 'd' : 'w');
4543 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4546 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
4548 static char retval[] = "s_c_\t%1,%0";
4550 retval[1] = (dbl_p ? 'd' : 'w');
4551 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4557 /* Return true if CMP1 is a suitable second operand for integer ordering
4558 test CODE. See also the *sCC patterns in mips.md. */
4561 mips_int_order_operand_ok_p (enum rtx_code code, rtx cmp1)
4567 return reg_or_0_operand (cmp1, VOIDmode);
4571 return !TARGET_MIPS16 && cmp1 == const1_rtx;
4575 return arith_operand (cmp1, VOIDmode);
4578 return sle_operand (cmp1, VOIDmode);
4581 return sleu_operand (cmp1, VOIDmode);
4588 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4589 integer ordering test *CODE, or if an equivalent combination can
4590 be formed by adjusting *CODE and *CMP1. When returning true, update
4591 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4595 mips_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1,
4596 enum machine_mode mode)
4598 HOST_WIDE_INT plus_one;
4600 if (mips_int_order_operand_ok_p (*code, *cmp1))
4603 if (CONST_INT_P (*cmp1))
4607 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4608 if (INTVAL (*cmp1) < plus_one)
4611 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4617 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4621 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4632 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4633 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4634 is nonnull, it's OK to set TARGET to the inverse of the result and
4635 flip *INVERT_PTR instead. */
4638 mips_emit_int_order_test (enum rtx_code code, bool *invert_ptr,
4639 rtx target, rtx cmp0, rtx cmp1)
4641 enum machine_mode mode;
4643 /* First see if there is a MIPS instruction that can do this operation.
4644 If not, try doing the same for the inverse operation. If that also
4645 fails, force CMP1 into a register and try again. */
4646 mode = GET_MODE (cmp0);
4647 if (mips_canonicalize_int_order_test (&code, &cmp1, mode))
4648 mips_emit_binary (code, target, cmp0, cmp1);
4651 enum rtx_code inv_code = reverse_condition (code);
4652 if (!mips_canonicalize_int_order_test (&inv_code, &cmp1, mode))
4654 cmp1 = force_reg (mode, cmp1);
4655 mips_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1);
4657 else if (invert_ptr == 0)
4661 inv_target = mips_force_binary (GET_MODE (target),
4662 inv_code, cmp0, cmp1);
4663 mips_emit_binary (XOR, target, inv_target, const1_rtx);
4667 *invert_ptr = !*invert_ptr;
4668 mips_emit_binary (inv_code, target, cmp0, cmp1);
4673 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4674 The register will have the same mode as CMP0. */
4677 mips_zero_if_equal (rtx cmp0, rtx cmp1)
4679 if (cmp1 == const0_rtx)
4682 if (uns_arith_operand (cmp1, VOIDmode))
4683 return expand_binop (GET_MODE (cmp0), xor_optab,
4684 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4686 return expand_binop (GET_MODE (cmp0), sub_optab,
4687 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4690 /* Convert *CODE into a code that can be used in a floating-point
4691 scc instruction (C.cond.fmt). Return true if the values of
4692 the condition code registers will be inverted, with 0 indicating
4693 that the condition holds. */
4696 mips_reversed_fp_cond (enum rtx_code *code)
4703 *code = reverse_condition_maybe_unordered (*code);
4711 /* Allocate a floating-point condition-code register of mode MODE.
4713 These condition code registers are used for certain kinds
4714 of compound operation, such as compare and branches, vconds,
4715 and built-in functions. At expand time, their use is entirely
4716 controlled by MIPS-specific code and is entirely internal
4717 to these compound operations.
4719 We could (and did in the past) expose condition-code values
4720 as pseudo registers and leave the register allocator to pick
4721 appropriate registers. The problem is that it is not practically
4722 possible for the rtl optimizers to guarantee that no spills will
4723 be needed, even when AVOID_CCMODE_COPIES is defined. We would
4724 therefore need spill and reload sequences to handle the worst case.
4726 Although such sequences do exist, they are very expensive and are
4727 not something we'd want to use. This is especially true of CCV2 and
4728 CCV4, where all the shuffling would greatly outweigh whatever benefit
4729 the vectorization itself provides.
4731 The main benefit of having more than one condition-code register
4732 is to allow the pipelining of operations, especially those involving
4733 comparisons and conditional moves. We don't really expect the
4734 registers to be live for long periods, and certainly never want
4735 them to be live across calls.
4737 Also, there should be no penalty attached to using all the available
4738 registers. They are simply bits in the same underlying FPU control
4741 We therefore expose the hardware registers from the outset and use
4742 a simple round-robin allocation scheme. */
4745 mips_allocate_fcc (enum machine_mode mode)
4747 unsigned int regno, count;
4749 gcc_assert (TARGET_HARD_FLOAT && ISA_HAS_8CC);
4753 else if (mode == CCV2mode)
4755 else if (mode == CCV4mode)
4760 cfun->machine->next_fcc += -cfun->machine->next_fcc & (count - 1);
4761 if (cfun->machine->next_fcc > ST_REG_LAST - ST_REG_FIRST)
4762 cfun->machine->next_fcc = 0;
4763 regno = ST_REG_FIRST + cfun->machine->next_fcc;
4764 cfun->machine->next_fcc += count;
4765 return gen_rtx_REG (mode, regno);
4768 /* Convert a comparison into something that can be used in a branch or
4769 conditional move. On entry, *OP0 and *OP1 are the values being
4770 compared and *CODE is the code used to compare them.
4772 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
4773 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
4774 otherwise any standard branch condition can be used. The standard branch
4777 - EQ or NE between two registers.
4778 - any comparison between a register and zero. */
4781 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
4786 if (GET_MODE_CLASS (GET_MODE (*op0)) == MODE_INT)
4788 if (!need_eq_ne_p && *op1 == const0_rtx)
4790 else if (*code == EQ || *code == NE)
4794 *op0 = mips_zero_if_equal (cmp_op0, cmp_op1);
4798 *op1 = force_reg (GET_MODE (cmp_op0), cmp_op1);
4802 /* The comparison needs a separate scc instruction. Store the
4803 result of the scc in *OP0 and compare it against zero. */
4804 bool invert = false;
4805 *op0 = gen_reg_rtx (GET_MODE (cmp_op0));
4806 mips_emit_int_order_test (*code, &invert, *op0, cmp_op0, cmp_op1);
4807 *code = (invert ? EQ : NE);
4811 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0)))
4813 *op0 = gen_rtx_REG (CCDSPmode, CCDSP_CC_REGNUM);
4814 mips_emit_binary (*code, *op0, cmp_op0, cmp_op1);
4820 enum rtx_code cmp_code;
4822 /* Floating-point tests use a separate C.cond.fmt comparison to
4823 set a condition code register. The branch or conditional move
4824 will then compare that register against zero.
4826 Set CMP_CODE to the code of the comparison instruction and
4827 *CODE to the code that the branch or move should use. */
4829 *code = mips_reversed_fp_cond (&cmp_code) ? EQ : NE;
4831 ? mips_allocate_fcc (CCmode)
4832 : gen_rtx_REG (CCmode, FPSW_REGNUM));
4834 mips_emit_binary (cmp_code, *op0, cmp_op0, cmp_op1);
4838 /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2]
4839 and OPERAND[3]. Store the result in OPERANDS[0].
4841 On 64-bit targets, the mode of the comparison and target will always be
4842 SImode, thus possibly narrower than that of the comparison's operands. */
4845 mips_expand_scc (rtx operands[])
4847 rtx target = operands[0];
4848 enum rtx_code code = GET_CODE (operands[1]);
4849 rtx op0 = operands[2];
4850 rtx op1 = operands[3];
4852 gcc_assert (GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT);
4854 if (code == EQ || code == NE)
4857 && reg_imm10_operand (op1, GET_MODE (op1)))
4858 mips_emit_binary (code, target, op0, op1);
4861 rtx zie = mips_zero_if_equal (op0, op1);
4862 mips_emit_binary (code, target, zie, const0_rtx);
4866 mips_emit_int_order_test (code, 0, target, op0, op1);
4869 /* Compare OPERANDS[1] with OPERANDS[2] using comparison code
4870 CODE and jump to OPERANDS[3] if the condition holds. */
4873 mips_expand_conditional_branch (rtx *operands)
4875 enum rtx_code code = GET_CODE (operands[0]);
4876 rtx op0 = operands[1];
4877 rtx op1 = operands[2];
4880 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
4881 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
4882 emit_jump_insn (gen_condjump (condition, operands[3]));
4887 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
4888 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
4891 mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
4892 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
4897 reversed_p = mips_reversed_fp_cond (&cond);
4898 cmp_result = mips_allocate_fcc (CCV2mode);
4899 emit_insn (gen_scc_ps (cmp_result,
4900 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
4902 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
4905 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
4909 /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0]
4910 if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
4913 mips_expand_conditional_move (rtx *operands)
4916 enum rtx_code code = GET_CODE (operands[1]);
4917 rtx op0 = XEXP (operands[1], 0);
4918 rtx op1 = XEXP (operands[1], 1);
4920 mips_emit_compare (&code, &op0, &op1, true);
4921 cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
4922 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
4923 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), cond,
4924 operands[2], operands[3])));
4927 /* Perform the comparison in COMPARISON, then trap if the condition holds. */
4930 mips_expand_conditional_trap (rtx comparison)
4933 enum machine_mode mode;
4936 /* MIPS conditional trap instructions don't have GT or LE flavors,
4937 so we must swap the operands and convert to LT and GE respectively. */
4938 code = GET_CODE (comparison);
4945 code = swap_condition (code);
4946 op0 = XEXP (comparison, 1);
4947 op1 = XEXP (comparison, 0);
4951 op0 = XEXP (comparison, 0);
4952 op1 = XEXP (comparison, 1);
4956 mode = GET_MODE (XEXP (comparison, 0));
4957 op0 = force_reg (mode, op0);
4958 if (!arith_operand (op1, mode))
4959 op1 = force_reg (mode, op1);
4961 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
4962 gen_rtx_fmt_ee (code, mode, op0, op1),
4966 /* Initialize *CUM for a call to a function of type FNTYPE. */
4969 mips_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype)
4971 memset (cum, 0, sizeof (*cum));
4972 cum->prototype = (fntype && prototype_p (fntype));
4973 cum->gp_reg_found = (cum->prototype && stdarg_p (fntype));
4976 /* Fill INFO with information about a single argument. CUM is the
4977 cumulative state for earlier arguments. MODE is the mode of this
4978 argument and TYPE is its type (if known). NAMED is true if this
4979 is a named (fixed) argument rather than a variable one. */
4982 mips_get_arg_info (struct mips_arg_info *info, const CUMULATIVE_ARGS *cum,
4983 enum machine_mode mode, const_tree type, bool named)
4985 bool doubleword_aligned_p;
4986 unsigned int num_bytes, num_words, max_regs;
4988 /* Work out the size of the argument. */
4989 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
4990 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4992 /* Decide whether it should go in a floating-point register, assuming
4993 one is free. Later code checks for availability.
4995 The checks against UNITS_PER_FPVALUE handle the soft-float and
4996 single-float cases. */
5000 /* The EABI conventions have traditionally been defined in terms
5001 of TYPE_MODE, regardless of the actual type. */
5002 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
5003 || mode == V2SFmode)
5004 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
5009 /* Only leading floating-point scalars are passed in
5010 floating-point registers. We also handle vector floats the same
5011 say, which is OK because they are not covered by the standard ABI. */
5012 info->fpr_p = (!cum->gp_reg_found
5013 && cum->arg_number < 2
5015 || SCALAR_FLOAT_TYPE_P (type)
5016 || VECTOR_FLOAT_TYPE_P (type))
5017 && (GET_MODE_CLASS (mode) == MODE_FLOAT
5018 || mode == V2SFmode)
5019 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
5024 /* Scalar, complex and vector floating-point types are passed in
5025 floating-point registers, as long as this is a named rather
5026 than a variable argument. */
5027 info->fpr_p = (named
5028 && (type == 0 || FLOAT_TYPE_P (type))
5029 && (GET_MODE_CLASS (mode) == MODE_FLOAT
5030 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5031 || mode == V2SFmode)
5032 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
5034 /* ??? According to the ABI documentation, the real and imaginary
5035 parts of complex floats should be passed in individual registers.
5036 The real and imaginary parts of stack arguments are supposed
5037 to be contiguous and there should be an extra word of padding
5040 This has two problems. First, it makes it impossible to use a
5041 single "void *" va_list type, since register and stack arguments
5042 are passed differently. (At the time of writing, MIPSpro cannot
5043 handle complex float varargs correctly.) Second, it's unclear
5044 what should happen when there is only one register free.
5046 For now, we assume that named complex floats should go into FPRs
5047 if there are two FPRs free, otherwise they should be passed in the
5048 same way as a struct containing two floats. */
5050 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5051 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
5053 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
5054 info->fpr_p = false;
5064 /* See whether the argument has doubleword alignment. */
5065 doubleword_aligned_p = (mips_function_arg_boundary (mode, type)
5068 /* Set REG_OFFSET to the register count we're interested in.
5069 The EABI allocates the floating-point registers separately,
5070 but the other ABIs allocate them like integer registers. */
5071 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
5075 /* Advance to an even register if the argument is doubleword-aligned. */
5076 if (doubleword_aligned_p)
5077 info->reg_offset += info->reg_offset & 1;
5079 /* Work out the offset of a stack argument. */
5080 info->stack_offset = cum->stack_words;
5081 if (doubleword_aligned_p)
5082 info->stack_offset += info->stack_offset & 1;
5084 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
5086 /* Partition the argument between registers and stack. */
5087 info->reg_words = MIN (num_words, max_regs);
5088 info->stack_words = num_words - info->reg_words;
5091 /* INFO describes a register argument that has the normal format for the
5092 argument's mode. Return the register it uses, assuming that FPRs are
5093 available if HARD_FLOAT_P. */
5096 mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p)
5098 if (!info->fpr_p || !hard_float_p)
5099 return GP_ARG_FIRST + info->reg_offset;
5100 else if (mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info->reg_offset > 0)
5101 /* In o32, the second argument is always passed in $f14
5102 for TARGET_DOUBLE_FLOAT, regardless of whether the
5103 first argument was a word or doubleword. */
5104 return FP_ARG_FIRST + 2;
5106 return FP_ARG_FIRST + info->reg_offset;
5109 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
5112 mips_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED)
5114 return !TARGET_OLDABI;
5117 /* Implement TARGET_FUNCTION_ARG. */
5120 mips_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
5121 const_tree type, bool named)
5123 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
5124 struct mips_arg_info info;
5126 /* We will be called with a mode of VOIDmode after the last argument
5127 has been seen. Whatever we return will be passed to the call expander.
5128 If we need a MIPS16 fp_code, return a REG with the code stored as
5130 if (mode == VOIDmode)
5132 if (TARGET_MIPS16 && cum->fp_code != 0)
5133 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
5138 mips_get_arg_info (&info, cum, mode, type, named);
5140 /* Return straight away if the whole argument is passed on the stack. */
5141 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
5144 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
5145 contains a double in its entirety, then that 64-bit chunk is passed
5146 in a floating-point register. */
5148 && TARGET_HARD_FLOAT
5151 && TREE_CODE (type) == RECORD_TYPE
5152 && TYPE_SIZE_UNIT (type)
5153 && tree_fits_uhwi_p (TYPE_SIZE_UNIT (type)))
5157 /* First check to see if there is any such field. */
5158 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
5159 if (TREE_CODE (field) == FIELD_DECL
5160 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
5161 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
5162 && tree_fits_shwi_p (bit_position (field))
5163 && int_bit_position (field) % BITS_PER_WORD == 0)
5168 /* Now handle the special case by returning a PARALLEL
5169 indicating where each 64-bit chunk goes. INFO.REG_WORDS
5170 chunks are passed in registers. */
5172 HOST_WIDE_INT bitpos;
5175 /* assign_parms checks the mode of ENTRY_PARM, so we must
5176 use the actual mode here. */
5177 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
5180 field = TYPE_FIELDS (type);
5181 for (i = 0; i < info.reg_words; i++)
5185 for (; field; field = DECL_CHAIN (field))
5186 if (TREE_CODE (field) == FIELD_DECL
5187 && int_bit_position (field) >= bitpos)
5191 && int_bit_position (field) == bitpos
5192 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
5193 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
5194 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
5196 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
5199 = gen_rtx_EXPR_LIST (VOIDmode, reg,
5200 GEN_INT (bitpos / BITS_PER_UNIT));
5202 bitpos += BITS_PER_WORD;
5208 /* Handle the n32/n64 conventions for passing complex floating-point
5209 arguments in FPR pairs. The real part goes in the lower register
5210 and the imaginary part goes in the upper register. */
5213 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5216 enum machine_mode inner;
5219 inner = GET_MODE_INNER (mode);
5220 regno = FP_ARG_FIRST + info.reg_offset;
5221 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
5223 /* Real part in registers, imaginary part on stack. */
5224 gcc_assert (info.stack_words == info.reg_words);
5225 return gen_rtx_REG (inner, regno);
5229 gcc_assert (info.stack_words == 0);
5230 real = gen_rtx_EXPR_LIST (VOIDmode,
5231 gen_rtx_REG (inner, regno),
5233 imag = gen_rtx_EXPR_LIST (VOIDmode,
5235 regno + info.reg_words / 2),
5236 GEN_INT (GET_MODE_SIZE (inner)));
5237 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
5241 return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT));
5244 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
5247 mips_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
5248 const_tree type, bool named)
5250 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
5251 struct mips_arg_info info;
5253 mips_get_arg_info (&info, cum, mode, type, named);
5256 cum->gp_reg_found = true;
5258 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
5259 an explanation of what this code does. It assumes that we're using
5260 either the o32 or the o64 ABI, both of which pass at most 2 arguments
5262 if (cum->arg_number < 2 && info.fpr_p)
5263 cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2);
5265 /* Advance the register count. This has the effect of setting
5266 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
5267 argument required us to skip the final GPR and pass the whole
5268 argument on the stack. */
5269 if (mips_abi != ABI_EABI || !info.fpr_p)
5270 cum->num_gprs = info.reg_offset + info.reg_words;
5271 else if (info.reg_words > 0)
5272 cum->num_fprs += MAX_FPRS_PER_FMT;
5274 /* Advance the stack word count. */
5275 if (info.stack_words > 0)
5276 cum->stack_words = info.stack_offset + info.stack_words;
5281 /* Implement TARGET_ARG_PARTIAL_BYTES. */
5284 mips_arg_partial_bytes (cumulative_args_t cum,
5285 enum machine_mode mode, tree type, bool named)
5287 struct mips_arg_info info;
5289 mips_get_arg_info (&info, get_cumulative_args (cum), mode, type, named);
5290 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
5293 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
5294 least PARM_BOUNDARY bits of alignment, but will be given anything up
5295 to STACK_BOUNDARY bits if the type requires it. */
5298 mips_function_arg_boundary (enum machine_mode mode, const_tree type)
5300 unsigned int alignment;
5302 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
5303 if (alignment < PARM_BOUNDARY)
5304 alignment = PARM_BOUNDARY;
5305 if (alignment > STACK_BOUNDARY)
5306 alignment = STACK_BOUNDARY;
5310 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
5311 upward rather than downward. In other words, return true if the
5312 first byte of the stack slot has useful data, false if the last
5316 mips_pad_arg_upward (enum machine_mode mode, const_tree type)
5318 /* On little-endian targets, the first byte of every stack argument
5319 is passed in the first byte of the stack slot. */
5320 if (!BYTES_BIG_ENDIAN)
5323 /* Otherwise, integral types are padded downward: the last byte of a
5324 stack argument is passed in the last byte of the stack slot. */
5326 ? (INTEGRAL_TYPE_P (type)
5327 || POINTER_TYPE_P (type)
5328 || FIXED_POINT_TYPE_P (type))
5329 : (SCALAR_INT_MODE_P (mode)
5330 || ALL_SCALAR_FIXED_POINT_MODE_P (mode)))
5333 /* Big-endian o64 pads floating-point arguments downward. */
5334 if (mips_abi == ABI_O64)
5335 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
5338 /* Other types are padded upward for o32, o64, n32 and n64. */
5339 if (mips_abi != ABI_EABI)
5342 /* Arguments smaller than a stack slot are padded downward. */
5343 if (mode != BLKmode)
5344 return GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY;
5346 return int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT);
5349 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
5350 if the least significant byte of the register has useful data. Return
5351 the opposite if the most significant byte does. */
5354 mips_pad_reg_upward (enum machine_mode mode, tree type)
5356 /* No shifting is required for floating-point arguments. */
5357 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
5358 return !BYTES_BIG_ENDIAN;
5360 /* Otherwise, apply the same padding to register arguments as we do
5361 to stack arguments. */
5362 return mips_pad_arg_upward (mode, type);
5365 /* Return nonzero when an argument must be passed by reference. */
5368 mips_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
5369 enum machine_mode mode, const_tree type,
5370 bool named ATTRIBUTE_UNUSED)
5372 if (mips_abi == ABI_EABI)
5376 /* ??? How should SCmode be handled? */
5377 if (mode == DImode || mode == DFmode
5378 || mode == DQmode || mode == UDQmode
5379 || mode == DAmode || mode == UDAmode)
5382 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
5383 return size == -1 || size > UNITS_PER_WORD;
5387 /* If we have a variable-sized parameter, we have no choice. */
5388 return targetm.calls.must_pass_in_stack (mode, type);
5392 /* Implement TARGET_CALLEE_COPIES. */
5395 mips_callee_copies (cumulative_args_t cum ATTRIBUTE_UNUSED,
5396 enum machine_mode mode ATTRIBUTE_UNUSED,
5397 const_tree type ATTRIBUTE_UNUSED, bool named)
5399 return mips_abi == ABI_EABI && named;
5402 /* See whether VALTYPE is a record whose fields should be returned in
5403 floating-point registers. If so, return the number of fields and
5404 list them in FIELDS (which should have two elements). Return 0
5407 For n32 & n64, a structure with one or two fields is returned in
5408 floating-point registers as long as every field has a floating-point
5412 mips_fpr_return_fields (const_tree valtype, tree *fields)
5420 if (TREE_CODE (valtype) != RECORD_TYPE)
5424 for (field = TYPE_FIELDS (valtype); field != 0; field = DECL_CHAIN (field))
5426 if (TREE_CODE (field) != FIELD_DECL)
5429 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)))
5435 fields[i++] = field;
5440 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
5441 a value in the most significant part of $2/$3 if:
5443 - the target is big-endian;
5445 - the value has a structure or union type (we generalize this to
5446 cover aggregates from other languages too); and
5448 - the structure is not returned in floating-point registers. */
5451 mips_return_in_msb (const_tree valtype)
5455 return (TARGET_NEWABI
5456 && TARGET_BIG_ENDIAN
5457 && AGGREGATE_TYPE_P (valtype)
5458 && mips_fpr_return_fields (valtype, fields) == 0);
5461 /* Return true if the function return value MODE will get returned in a
5462 floating-point register. */
5465 mips_return_mode_in_fpr_p (enum machine_mode mode)
5467 return ((GET_MODE_CLASS (mode) == MODE_FLOAT
5469 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5470 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE);
5473 /* Return the representation of an FPR return register when the
5474 value being returned in FP_RETURN has mode VALUE_MODE and the
5475 return type itself has mode TYPE_MODE. On NewABI targets,
5476 the two modes may be different for structures like:
5478 struct __attribute__((packed)) foo { float f; }
5480 where we return the SFmode value of "f" in FP_RETURN, but where
5481 the structure itself has mode BLKmode. */
5484 mips_return_fpr_single (enum machine_mode type_mode,
5485 enum machine_mode value_mode)
5489 x = gen_rtx_REG (value_mode, FP_RETURN);
5490 if (type_mode != value_mode)
5492 x = gen_rtx_EXPR_LIST (VOIDmode, x, const0_rtx);
5493 x = gen_rtx_PARALLEL (type_mode, gen_rtvec (1, x));
5498 /* Return a composite value in a pair of floating-point registers.
5499 MODE1 and OFFSET1 are the mode and byte offset for the first value,
5500 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
5503 For n32 & n64, $f0 always holds the first value and $f2 the second.
5504 Otherwise the values are packed together as closely as possible. */
5507 mips_return_fpr_pair (enum machine_mode mode,
5508 enum machine_mode mode1, HOST_WIDE_INT offset1,
5509 enum machine_mode mode2, HOST_WIDE_INT offset2)
5513 inc = (TARGET_NEWABI ? 2 : MAX_FPRS_PER_FMT);
5514 return gen_rtx_PARALLEL
5517 gen_rtx_EXPR_LIST (VOIDmode,
5518 gen_rtx_REG (mode1, FP_RETURN),
5520 gen_rtx_EXPR_LIST (VOIDmode,
5521 gen_rtx_REG (mode2, FP_RETURN + inc),
5522 GEN_INT (offset2))));
5526 /* Implement TARGET_FUNCTION_VALUE and TARGET_LIBCALL_VALUE.
5527 For normal calls, VALTYPE is the return type and MODE is VOIDmode.
5528 For libcalls, VALTYPE is null and MODE is the mode of the return value. */
5531 mips_function_value_1 (const_tree valtype, const_tree fn_decl_or_type,
5532 enum machine_mode mode)
5540 if (fn_decl_or_type && DECL_P (fn_decl_or_type))
5541 func = fn_decl_or_type;
5545 mode = TYPE_MODE (valtype);
5546 unsigned_p = TYPE_UNSIGNED (valtype);
5548 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
5549 return values, promote the mode here too. */
5550 mode = promote_function_mode (valtype, mode, &unsigned_p, func, 1);
5552 /* Handle structures whose fields are returned in $f0/$f2. */
5553 switch (mips_fpr_return_fields (valtype, fields))
5556 return mips_return_fpr_single (mode,
5557 TYPE_MODE (TREE_TYPE (fields[0])));
5560 return mips_return_fpr_pair (mode,
5561 TYPE_MODE (TREE_TYPE (fields[0])),
5562 int_byte_position (fields[0]),
5563 TYPE_MODE (TREE_TYPE (fields[1])),
5564 int_byte_position (fields[1]));
5567 /* If a value is passed in the most significant part of a register, see
5568 whether we have to round the mode up to a whole number of words. */
5569 if (mips_return_in_msb (valtype))
5571 HOST_WIDE_INT size = int_size_in_bytes (valtype);
5572 if (size % UNITS_PER_WORD != 0)
5574 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
5575 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
5579 /* For EABI, the class of return register depends entirely on MODE.
5580 For example, "struct { some_type x; }" and "union { some_type x; }"
5581 are returned in the same way as a bare "some_type" would be.
5582 Other ABIs only use FPRs for scalar, complex or vector types. */
5583 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
5584 return gen_rtx_REG (mode, GP_RETURN);
5589 /* Handle long doubles for n32 & n64. */
5591 return mips_return_fpr_pair (mode,
5593 DImode, GET_MODE_SIZE (mode) / 2);
5595 if (mips_return_mode_in_fpr_p (mode))
5597 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5598 return mips_return_fpr_pair (mode,
5599 GET_MODE_INNER (mode), 0,
5600 GET_MODE_INNER (mode),
5601 GET_MODE_SIZE (mode) / 2);
5603 return gen_rtx_REG (mode, FP_RETURN);
5607 return gen_rtx_REG (mode, GP_RETURN);
5610 /* Implement TARGET_FUNCTION_VALUE. */
5613 mips_function_value (const_tree valtype, const_tree fn_decl_or_type,
5614 bool outgoing ATTRIBUTE_UNUSED)
5616 return mips_function_value_1 (valtype, fn_decl_or_type, VOIDmode);
5619 /* Implement TARGET_LIBCALL_VALUE. */
5622 mips_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
5624 return mips_function_value_1 (NULL_TREE, NULL_TREE, mode);
5627 /* Implement TARGET_FUNCTION_VALUE_REGNO_P.
5629 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
5630 Currently, R2 and F0 are only implemented here (C has no complex type). */
5633 mips_function_value_regno_p (const unsigned int regno)
5635 if (regno == GP_RETURN
5636 || regno == FP_RETURN
5637 || (LONG_DOUBLE_TYPE_SIZE == 128
5638 && FP_RETURN != GP_RETURN
5639 && regno == FP_RETURN + 2))
5645 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
5646 all BLKmode objects are returned in memory. Under the n32, n64
5647 and embedded ABIs, small structures are returned in a register.
5648 Objects with varying size must still be returned in memory, of
5652 mips_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
5654 return (TARGET_OLDABI
5655 ? TYPE_MODE (type) == BLKmode
5656 : !IN_RANGE (int_size_in_bytes (type), 0, 2 * UNITS_PER_WORD));
5659 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
5662 mips_setup_incoming_varargs (cumulative_args_t cum, enum machine_mode mode,
5663 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5666 CUMULATIVE_ARGS local_cum;
5667 int gp_saved, fp_saved;
5669 /* The caller has advanced CUM up to, but not beyond, the last named
5670 argument. Advance a local copy of CUM past the last "real" named
5671 argument, to find out how many registers are left over. */
5672 local_cum = *get_cumulative_args (cum);
5673 mips_function_arg_advance (pack_cumulative_args (&local_cum), mode, type,
5676 /* Found out how many registers we need to save. */
5677 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
5678 fp_saved = (EABI_FLOAT_VARARGS_P
5679 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
5688 ptr = plus_constant (Pmode, virtual_incoming_args_rtx,
5689 REG_PARM_STACK_SPACE (cfun->decl)
5690 - gp_saved * UNITS_PER_WORD);
5691 mem = gen_frame_mem (BLKmode, ptr);
5692 set_mem_alias_set (mem, get_varargs_alias_set ());
5694 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
5699 /* We can't use move_block_from_reg, because it will use
5701 enum machine_mode mode;
5704 /* Set OFF to the offset from virtual_incoming_args_rtx of
5705 the first float register. The FP save area lies below
5706 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
5707 off = (-gp_saved * UNITS_PER_WORD) & -UNITS_PER_FPVALUE;
5708 off -= fp_saved * UNITS_PER_FPREG;
5710 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
5712 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS;
5713 i += MAX_FPRS_PER_FMT)
5717 ptr = plus_constant (Pmode, virtual_incoming_args_rtx, off);
5718 mem = gen_frame_mem (mode, ptr);
5719 set_mem_alias_set (mem, get_varargs_alias_set ());
5720 mips_emit_move (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
5721 off += UNITS_PER_HWFPVALUE;
5725 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
5726 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
5727 + fp_saved * UNITS_PER_FPREG);
5730 /* Implement TARGET_BUILTIN_VA_LIST. */
5733 mips_build_builtin_va_list (void)
5735 if (EABI_FLOAT_VARARGS_P)
5737 /* We keep 3 pointers, and two offsets.
5739 Two pointers are to the overflow area, which starts at the CFA.
5740 One of these is constant, for addressing into the GPR save area
5741 below it. The other is advanced up the stack through the
5744 The third pointer is to the bottom of the GPR save area.
5745 Since the FPR save area is just below it, we can address
5746 FPR slots off this pointer.
5748 We also keep two one-byte offsets, which are to be subtracted
5749 from the constant pointers to yield addresses in the GPR and
5750 FPR save areas. These are downcounted as float or non-float
5751 arguments are used, and when they get to zero, the argument
5752 must be obtained from the overflow region. */
5753 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
5756 record = lang_hooks.types.make_type (RECORD_TYPE);
5758 f_ovfl = build_decl (BUILTINS_LOCATION,
5759 FIELD_DECL, get_identifier ("__overflow_argptr"),
5761 f_gtop = build_decl (BUILTINS_LOCATION,
5762 FIELD_DECL, get_identifier ("__gpr_top"),
5764 f_ftop = build_decl (BUILTINS_LOCATION,
5765 FIELD_DECL, get_identifier ("__fpr_top"),
5767 f_goff = build_decl (BUILTINS_LOCATION,
5768 FIELD_DECL, get_identifier ("__gpr_offset"),
5769 unsigned_char_type_node);
5770 f_foff = build_decl (BUILTINS_LOCATION,
5771 FIELD_DECL, get_identifier ("__fpr_offset"),
5772 unsigned_char_type_node);
5773 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
5774 warn on every user file. */
5775 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
5776 array = build_array_type (unsigned_char_type_node,
5777 build_index_type (index));
5778 f_res = build_decl (BUILTINS_LOCATION,
5779 FIELD_DECL, get_identifier ("__reserved"), array);
5781 DECL_FIELD_CONTEXT (f_ovfl) = record;
5782 DECL_FIELD_CONTEXT (f_gtop) = record;
5783 DECL_FIELD_CONTEXT (f_ftop) = record;
5784 DECL_FIELD_CONTEXT (f_goff) = record;
5785 DECL_FIELD_CONTEXT (f_foff) = record;
5786 DECL_FIELD_CONTEXT (f_res) = record;
5788 TYPE_FIELDS (record) = f_ovfl;
5789 DECL_CHAIN (f_ovfl) = f_gtop;
5790 DECL_CHAIN (f_gtop) = f_ftop;
5791 DECL_CHAIN (f_ftop) = f_goff;
5792 DECL_CHAIN (f_goff) = f_foff;
5793 DECL_CHAIN (f_foff) = f_res;
5795 layout_type (record);
5799 /* Otherwise, we use 'void *'. */
5800 return ptr_type_node;
5803 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
5806 mips_va_start (tree valist, rtx nextarg)
5808 if (EABI_FLOAT_VARARGS_P)
5810 const CUMULATIVE_ARGS *cum;
5811 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5812 tree ovfl, gtop, ftop, goff, foff;
5814 int gpr_save_area_size;
5815 int fpr_save_area_size;
5818 cum = &crtl->args.info;
5820 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
5822 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
5824 f_ovfl = TYPE_FIELDS (va_list_type_node);
5825 f_gtop = DECL_CHAIN (f_ovfl);
5826 f_ftop = DECL_CHAIN (f_gtop);
5827 f_goff = DECL_CHAIN (f_ftop);
5828 f_foff = DECL_CHAIN (f_goff);
5830 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5832 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
5834 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
5836 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
5838 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
5841 /* Emit code to initialize OVFL, which points to the next varargs
5842 stack argument. CUM->STACK_WORDS gives the number of stack
5843 words used by named arguments. */
5844 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
5845 if (cum->stack_words > 0)
5846 t = fold_build_pointer_plus_hwi (t, cum->stack_words * UNITS_PER_WORD);
5847 t = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
5848 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5850 /* Emit code to initialize GTOP, the top of the GPR save area. */
5851 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
5852 t = build2 (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
5853 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5855 /* Emit code to initialize FTOP, the top of the FPR save area.
5856 This address is gpr_save_area_bytes below GTOP, rounded
5857 down to the next fp-aligned boundary. */
5858 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
5859 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
5860 fpr_offset &= -UNITS_PER_FPVALUE;
5862 t = fold_build_pointer_plus_hwi (t, -fpr_offset);
5863 t = build2 (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
5864 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5866 /* Emit code to initialize GOFF, the offset from GTOP of the
5867 next GPR argument. */
5868 t = build2 (MODIFY_EXPR, TREE_TYPE (goff), goff,
5869 build_int_cst (TREE_TYPE (goff), gpr_save_area_size));
5870 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5872 /* Likewise emit code to initialize FOFF, the offset from FTOP
5873 of the next FPR argument. */
5874 t = build2 (MODIFY_EXPR, TREE_TYPE (foff), foff,
5875 build_int_cst (TREE_TYPE (foff), fpr_save_area_size));
5876 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5880 nextarg = plus_constant (Pmode, nextarg, -cfun->machine->varargs_size);
5881 std_expand_builtin_va_start (valist, nextarg);
5885 /* Like std_gimplify_va_arg_expr, but apply alignment to zero-sized
5889 mips_std_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
5892 tree addr, t, type_size, rounded_size, valist_tmp;
5893 unsigned HOST_WIDE_INT align, boundary;
5896 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, false);
5898 type = build_pointer_type (type);
5900 align = PARM_BOUNDARY / BITS_PER_UNIT;
5901 boundary = targetm.calls.function_arg_boundary (TYPE_MODE (type), type);
5903 /* When we align parameter on stack for caller, if the parameter
5904 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
5905 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
5906 here with caller. */
5907 if (boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
5908 boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
5910 boundary /= BITS_PER_UNIT;
5912 /* Hoist the valist value into a temporary for the moment. */
5913 valist_tmp = get_initialized_tmp_var (valist, pre_p, NULL);
5915 /* va_list pointer is aligned to PARM_BOUNDARY. If argument actually
5916 requires greater alignment, we must perform dynamic alignment. */
5917 if (boundary > align)
5919 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
5920 fold_build_pointer_plus_hwi (valist_tmp, boundary - 1));
5921 gimplify_and_add (t, pre_p);
5923 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
5924 fold_build2 (BIT_AND_EXPR, TREE_TYPE (valist),
5926 build_int_cst (TREE_TYPE (valist), -boundary)));
5927 gimplify_and_add (t, pre_p);
5932 /* If the actual alignment is less than the alignment of the type,
5933 adjust the type accordingly so that we don't assume strict alignment
5934 when dereferencing the pointer. */
5935 boundary *= BITS_PER_UNIT;
5936 if (boundary < TYPE_ALIGN (type))
5938 type = build_variant_type_copy (type);
5939 TYPE_ALIGN (type) = boundary;
5942 /* Compute the rounded size of the type. */
5943 type_size = size_in_bytes (type);
5944 rounded_size = round_up (type_size, align);
5946 /* Reduce rounded_size so it's sharable with the postqueue. */
5947 gimplify_expr (&rounded_size, pre_p, post_p, is_gimple_val, fb_rvalue);
5951 if (PAD_VARARGS_DOWN && !integer_zerop (rounded_size))
5953 /* Small args are padded downward. */
5954 t = fold_build2_loc (input_location, GT_EXPR, sizetype,
5955 rounded_size, size_int (align));
5956 t = fold_build3 (COND_EXPR, sizetype, t, size_zero_node,
5957 size_binop (MINUS_EXPR, rounded_size, type_size));
5958 addr = fold_build_pointer_plus (addr, t);
5961 /* Compute new value for AP. */
5962 t = fold_build_pointer_plus (valist_tmp, rounded_size);
5963 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
5964 gimplify_and_add (t, pre_p);
5966 addr = fold_convert (build_pointer_type (type), addr);
5969 addr = build_va_arg_indirect_ref (addr);
5971 return build_va_arg_indirect_ref (addr);
5974 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
5977 mips_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
5983 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
5985 type = build_pointer_type (type);
5987 if (!EABI_FLOAT_VARARGS_P)
5988 addr = mips_std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5991 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5992 tree ovfl, top, off, align;
5993 HOST_WIDE_INT size, rsize, osize;
5996 f_ovfl = TYPE_FIELDS (va_list_type_node);
5997 f_gtop = DECL_CHAIN (f_ovfl);
5998 f_ftop = DECL_CHAIN (f_gtop);
5999 f_goff = DECL_CHAIN (f_ftop);
6000 f_foff = DECL_CHAIN (f_goff);
6004 TOP be the top of the GPR or FPR save area;
6005 OFF be the offset from TOP of the next register;
6006 ADDR_RTX be the address of the argument;
6007 SIZE be the number of bytes in the argument type;
6008 RSIZE be the number of bytes used to store the argument
6009 when it's in the register save area; and
6010 OSIZE be the number of bytes used to store it when it's
6011 in the stack overflow area.
6013 The code we want is:
6015 1: off &= -rsize; // round down
6018 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
6023 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
6024 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
6028 [1] and [9] can sometimes be optimized away. */
6030 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
6032 size = int_size_in_bytes (type);
6034 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
6035 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
6037 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop),
6038 unshare_expr (valist), f_ftop, NULL_TREE);
6039 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff),
6040 unshare_expr (valist), f_foff, NULL_TREE);
6042 /* When va_start saves FPR arguments to the stack, each slot
6043 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
6044 argument's precision. */
6045 rsize = UNITS_PER_HWFPVALUE;
6047 /* Overflow arguments are padded to UNITS_PER_WORD bytes
6048 (= PARM_BOUNDARY bits). This can be different from RSIZE
6051 (1) On 32-bit targets when TYPE is a structure such as:
6053 struct s { float f; };
6055 Such structures are passed in paired FPRs, so RSIZE
6056 will be 8 bytes. However, the structure only takes
6057 up 4 bytes of memory, so OSIZE will only be 4.
6059 (2) In combinations such as -mgp64 -msingle-float
6060 -fshort-double. Doubles passed in registers will then take
6061 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
6062 stack take up UNITS_PER_WORD bytes. */
6063 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
6067 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop),
6068 unshare_expr (valist), f_gtop, NULL_TREE);
6069 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff),
6070 unshare_expr (valist), f_goff, NULL_TREE);
6071 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
6072 if (rsize > UNITS_PER_WORD)
6074 /* [1] Emit code for: off &= -rsize. */
6075 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), unshare_expr (off),
6076 build_int_cst (TREE_TYPE (off), -rsize));
6077 gimplify_assign (unshare_expr (off), t, pre_p);
6082 /* [2] Emit code to branch if off == 0. */
6083 t = build2 (NE_EXPR, boolean_type_node, unshare_expr (off),
6084 build_int_cst (TREE_TYPE (off), 0));
6085 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
6087 /* [5] Emit code for: off -= rsize. We do this as a form of
6088 post-decrement not available to C. */
6089 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
6090 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
6092 /* [4] Emit code for:
6093 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
6094 t = fold_convert (sizetype, t);
6095 t = fold_build1 (NEGATE_EXPR, sizetype, t);
6096 t = fold_build_pointer_plus (top, t);
6097 if (BYTES_BIG_ENDIAN && rsize > size)
6098 t = fold_build_pointer_plus_hwi (t, rsize - size);
6099 COND_EXPR_THEN (addr) = t;
6101 if (osize > UNITS_PER_WORD)
6103 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
6104 t = fold_build_pointer_plus_hwi (unshare_expr (ovfl), osize - 1);
6105 u = build_int_cst (TREE_TYPE (t), -osize);
6106 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t, u);
6107 align = build2 (MODIFY_EXPR, TREE_TYPE (ovfl),
6108 unshare_expr (ovfl), t);
6113 /* [10, 11] Emit code for:
6114 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
6116 u = fold_convert (TREE_TYPE (ovfl), build_int_cst (NULL_TREE, osize));
6117 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
6118 if (BYTES_BIG_ENDIAN && osize > size)
6119 t = fold_build_pointer_plus_hwi (t, osize - size);
6121 /* String [9] and [10, 11] together. */
6123 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
6124 COND_EXPR_ELSE (addr) = t;
6126 addr = fold_convert (build_pointer_type (type), addr);
6127 addr = build_va_arg_indirect_ref (addr);
6131 addr = build_va_arg_indirect_ref (addr);
6136 /* Declare a unique, locally-binding function called NAME, then start
6140 mips_start_unique_function (const char *name)
6144 decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
6145 get_identifier (name),
6146 build_function_type_list (void_type_node, NULL_TREE));
6147 DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
6148 NULL_TREE, void_type_node);
6149 TREE_PUBLIC (decl) = 1;
6150 TREE_STATIC (decl) = 1;
6152 DECL_COMDAT_GROUP (decl) = DECL_ASSEMBLER_NAME (decl);
6154 targetm.asm_out.unique_section (decl, 0);
6155 switch_to_section (get_named_section (decl, NULL, 0));
6157 targetm.asm_out.globalize_label (asm_out_file, name);
6158 fputs ("\t.hidden\t", asm_out_file);
6159 assemble_name (asm_out_file, name);
6160 putc ('\n', asm_out_file);
6163 /* Start a definition of function NAME. MIPS16_P indicates whether the
6164 function contains MIPS16 code. */
6167 mips_start_function_definition (const char *name, bool mips16_p)
6170 fprintf (asm_out_file, "\t.set\tmips16\n");
6172 fprintf (asm_out_file, "\t.set\tnomips16\n");
6174 if (TARGET_MICROMIPS)
6175 fprintf (asm_out_file, "\t.set\tmicromips\n");
6176 #ifdef HAVE_GAS_MICROMIPS
6178 fprintf (asm_out_file, "\t.set\tnomicromips\n");
6181 if (!flag_inhibit_size_directive)
6183 fputs ("\t.ent\t", asm_out_file);
6184 assemble_name (asm_out_file, name);
6185 fputs ("\n", asm_out_file);
6188 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, name, "function");
6190 /* Start the definition proper. */
6191 assemble_name (asm_out_file, name);
6192 fputs (":\n", asm_out_file);
6195 /* End a function definition started by mips_start_function_definition. */
6198 mips_end_function_definition (const char *name)
6200 if (!flag_inhibit_size_directive)
6202 fputs ("\t.end\t", asm_out_file);
6203 assemble_name (asm_out_file, name);
6204 fputs ("\n", asm_out_file);
6208 /* Output a definition of the __mips16_rdhwr function. */
6211 mips_output_mips16_rdhwr (void)
6215 name = "__mips16_rdhwr";
6216 mips_start_unique_function (name);
6217 mips_start_function_definition (name, false);
6218 fprintf (asm_out_file,
6220 "\t.set\tmips32r2\n"
6221 "\t.set\tnoreorder\n"
6225 mips_end_function_definition (name);
6228 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
6231 mips_ok_for_lazy_binding_p (rtx x)
6233 return (TARGET_USE_GOT
6234 && GET_CODE (x) == SYMBOL_REF
6235 && !SYMBOL_REF_BIND_NOW_P (x)
6236 && !mips_symbol_binds_local_p (x));
6239 /* Load function address ADDR into register DEST. TYPE is as for
6240 mips_expand_call. Return true if we used an explicit lazy-binding
6244 mips_load_call_address (enum mips_call_type type, rtx dest, rtx addr)
6246 /* If we're generating PIC, and this call is to a global function,
6247 try to allow its address to be resolved lazily. This isn't
6248 possible for sibcalls when $gp is call-saved because the value
6249 of $gp on entry to the stub would be our caller's gp, not ours. */
6250 if (TARGET_EXPLICIT_RELOCS
6251 && !(type == MIPS_CALL_SIBCALL && TARGET_CALL_SAVED_GP)
6252 && mips_ok_for_lazy_binding_p (addr))
6254 addr = mips_got_load (dest, addr, SYMBOL_GOTOFF_CALL);
6255 emit_insn (gen_rtx_SET (VOIDmode, dest, addr));
6260 mips_emit_move (dest, addr);
6265 /* Each locally-defined hard-float MIPS16 function has a local symbol
6266 associated with it. This hash table maps the function symbol (FUNC)
6267 to the local symbol (LOCAL). */
6268 struct GTY(()) mips16_local_alias {
6272 static GTY ((param_is (struct mips16_local_alias))) htab_t mips16_local_aliases;
6274 /* Hash table callbacks for mips16_local_aliases. */
6277 mips16_local_aliases_hash (const void *entry)
6279 const struct mips16_local_alias *alias;
6281 alias = (const struct mips16_local_alias *) entry;
6282 return htab_hash_string (XSTR (alias->func, 0));
6286 mips16_local_aliases_eq (const void *entry1, const void *entry2)
6288 const struct mips16_local_alias *alias1, *alias2;
6290 alias1 = (const struct mips16_local_alias *) entry1;
6291 alias2 = (const struct mips16_local_alias *) entry2;
6292 return rtx_equal_p (alias1->func, alias2->func);
6295 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
6296 Return a local alias for it, creating a new one if necessary. */
6299 mips16_local_alias (rtx func)
6301 struct mips16_local_alias *alias, tmp_alias;
6304 /* Create the hash table if this is the first call. */
6305 if (mips16_local_aliases == NULL)
6306 mips16_local_aliases = htab_create_ggc (37, mips16_local_aliases_hash,
6307 mips16_local_aliases_eq, NULL);
6309 /* Look up the function symbol, creating a new entry if need be. */
6310 tmp_alias.func = func;
6311 slot = htab_find_slot (mips16_local_aliases, &tmp_alias, INSERT);
6312 gcc_assert (slot != NULL);
6314 alias = (struct mips16_local_alias *) *slot;
6317 const char *func_name, *local_name;
6320 /* Create a new SYMBOL_REF for the local symbol. The choice of
6321 __fn_local_* is based on the __fn_stub_* names that we've
6322 traditionally used for the non-MIPS16 stub. */
6323 func_name = targetm.strip_name_encoding (XSTR (func, 0));
6324 local_name = ACONCAT (("__fn_local_", func_name, NULL));
6325 local = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (local_name));
6326 SYMBOL_REF_FLAGS (local) = SYMBOL_REF_FLAGS (func) | SYMBOL_FLAG_LOCAL;
6328 /* Create a new structure to represent the mapping. */
6329 alias = ggc_alloc_mips16_local_alias ();
6331 alias->local = local;
6334 return alias->local;
6337 /* A chained list of functions for which mips16_build_call_stub has already
6338 generated a stub. NAME is the name of the function and FP_RET_P is true
6339 if the function returns a value in floating-point registers. */
6340 struct mips16_stub {
6341 struct mips16_stub *next;
6345 static struct mips16_stub *mips16_stubs;
6347 /* Return the two-character string that identifies floating-point
6348 return mode MODE in the name of a MIPS16 function stub. */
6351 mips16_call_stub_mode_suffix (enum machine_mode mode)
6355 else if (mode == DFmode)
6357 else if (mode == SCmode)
6359 else if (mode == DCmode)
6361 else if (mode == V2SFmode)
6367 /* Write instructions to move a 32-bit value between general register
6368 GPREG and floating-point register FPREG. DIRECTION is 't' to move
6369 from GPREG to FPREG and 'f' to move in the opposite direction. */
6372 mips_output_32bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
6374 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6375 reg_names[gpreg], reg_names[fpreg]);
6378 /* Likewise for 64-bit values. */
6381 mips_output_64bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
6384 fprintf (asm_out_file, "\tdm%cc1\t%s,%s\n", direction,
6385 reg_names[gpreg], reg_names[fpreg]);
6386 else if (TARGET_FLOAT64)
6388 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6389 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
6390 fprintf (asm_out_file, "\tm%chc1\t%s,%s\n", direction,
6391 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg]);
6395 /* Move the least-significant word. */
6396 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6397 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
6398 /* ...then the most significant word. */
6399 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6400 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg + 1]);
6404 /* Write out code to move floating-point arguments into or out of
6405 general registers. FP_CODE is the code describing which arguments
6406 are present (see the comment above the definition of CUMULATIVE_ARGS
6407 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
6410 mips_output_args_xfer (int fp_code, char direction)
6412 unsigned int gparg, fparg, f;
6413 CUMULATIVE_ARGS cum;
6415 /* This code only works for o32 and o64. */
6416 gcc_assert (TARGET_OLDABI);
6418 mips_init_cumulative_args (&cum, NULL);
6420 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
6422 enum machine_mode mode;
6423 struct mips_arg_info info;
6427 else if ((f & 3) == 2)
6432 mips_get_arg_info (&info, &cum, mode, NULL, true);
6433 gparg = mips_arg_regno (&info, false);
6434 fparg = mips_arg_regno (&info, true);
6437 mips_output_32bit_xfer (direction, gparg, fparg);
6439 mips_output_64bit_xfer (direction, gparg, fparg);
6441 mips_function_arg_advance (pack_cumulative_args (&cum), mode, NULL, true);
6445 /* Write a MIPS16 stub for the current function. This stub is used
6446 for functions which take arguments in the floating-point registers.
6447 It is normal-mode code that moves the floating-point arguments
6448 into the general registers and then jumps to the MIPS16 code. */
6451 mips16_build_function_stub (void)
6453 const char *fnname, *alias_name, *separator;
6454 char *secname, *stubname;
6459 /* Create the name of the stub, and its unique section. */
6460 symbol = XEXP (DECL_RTL (current_function_decl), 0);
6461 alias = mips16_local_alias (symbol);
6463 fnname = targetm.strip_name_encoding (XSTR (symbol, 0));
6464 alias_name = targetm.strip_name_encoding (XSTR (alias, 0));
6465 secname = ACONCAT ((".mips16.fn.", fnname, NULL));
6466 stubname = ACONCAT (("__fn_stub_", fnname, NULL));
6468 /* Build a decl for the stub. */
6469 stubdecl = build_decl (BUILTINS_LOCATION,
6470 FUNCTION_DECL, get_identifier (stubname),
6471 build_function_type_list (void_type_node, NULL_TREE));
6472 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
6473 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
6474 RESULT_DECL, NULL_TREE, void_type_node);
6476 /* Output a comment. */
6477 fprintf (asm_out_file, "\t# Stub function for %s (",
6478 current_function_name ());
6480 for (f = (unsigned int) crtl->args.info.fp_code; f != 0; f >>= 2)
6482 fprintf (asm_out_file, "%s%s", separator,
6483 (f & 3) == 1 ? "float" : "double");
6486 fprintf (asm_out_file, ")\n");
6488 /* Start the function definition. */
6489 assemble_start_function (stubdecl, stubname);
6490 mips_start_function_definition (stubname, false);
6492 /* If generating pic2 code, either set up the global pointer or
6494 if (TARGET_ABICALLS_PIC2)
6496 if (TARGET_ABSOLUTE_ABICALLS)
6497 fprintf (asm_out_file, "\t.option\tpic0\n");
6500 output_asm_insn ("%(.cpload\t%^%)", NULL);
6501 /* Emit an R_MIPS_NONE relocation to tell the linker what the
6502 target function is. Use a local GOT access when loading the
6503 symbol, to cut down on the number of unnecessary GOT entries
6504 for stubs that aren't needed. */
6505 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol);
6510 /* Load the address of the MIPS16 function into $25. Do this first so
6511 that targets with coprocessor interlocks can use an MFC1 to fill the
6513 output_asm_insn ("la\t%^,%0", &symbol);
6515 /* Move the arguments from floating-point registers to general registers. */
6516 mips_output_args_xfer (crtl->args.info.fp_code, 'f');
6518 /* Jump to the MIPS16 function. */
6519 output_asm_insn ("jr\t%^", NULL);
6521 if (TARGET_ABICALLS_PIC2 && TARGET_ABSOLUTE_ABICALLS)
6522 fprintf (asm_out_file, "\t.option\tpic2\n");
6524 mips_end_function_definition (stubname);
6526 /* If the linker needs to create a dynamic symbol for the target
6527 function, it will associate the symbol with the stub (which,
6528 unlike the target function, follows the proper calling conventions).
6529 It is therefore useful to have a local alias for the target function,
6530 so that it can still be identified as MIPS16 code. As an optimization,
6531 this symbol can also be used for indirect MIPS16 references from
6532 within this file. */
6533 ASM_OUTPUT_DEF (asm_out_file, alias_name, fnname);
6535 switch_to_section (function_section (current_function_decl));
6538 /* The current function is a MIPS16 function that returns a value in an FPR.
6539 Copy the return value from its soft-float to its hard-float location.
6540 libgcc2 has special non-MIPS16 helper functions for each case. */
6543 mips16_copy_fpr_return_value (void)
6545 rtx fn, insn, retval;
6547 enum machine_mode return_mode;
6550 return_type = DECL_RESULT (current_function_decl);
6551 return_mode = DECL_MODE (return_type);
6553 name = ACONCAT (("__mips16_ret_",
6554 mips16_call_stub_mode_suffix (return_mode),
6556 fn = mips16_stub_function (name);
6558 /* The function takes arguments in $2 (and possibly $3), so calls
6559 to it cannot be lazily bound. */
6560 SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_BIND_NOW;
6562 /* Model the call as something that takes the GPR return value as
6563 argument and returns an "updated" value. */
6564 retval = gen_rtx_REG (return_mode, GP_RETURN);
6565 insn = mips_expand_call (MIPS_CALL_EPILOGUE, retval, fn,
6566 const0_rtx, NULL_RTX, false);
6567 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), retval);
6570 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
6571 RETVAL is the location of the return value, or null if this is
6572 a "call" rather than a "call_value". ARGS_SIZE is the size of the
6573 arguments and FP_CODE is the code built by mips_function_arg;
6574 see the comment before the fp_code field in CUMULATIVE_ARGS for details.
6576 There are three alternatives:
6578 - If a stub was needed, emit the call and return the call insn itself.
6580 - If we can avoid using a stub by redirecting the call, set *FN_PTR
6581 to the new target and return null.
6583 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
6586 A stub is needed for calls to functions that, in normal mode,
6587 receive arguments in FPRs or return values in FPRs. The stub
6588 copies the arguments from their soft-float positions to their
6589 hard-float positions, calls the real function, then copies the
6590 return value from its hard-float position to its soft-float
6593 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
6594 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
6595 automatically redirects the JAL to the stub, otherwise the JAL
6596 continues to call FN directly. */
6599 mips16_build_call_stub (rtx retval, rtx *fn_ptr, rtx args_size, int fp_code)
6603 struct mips16_stub *l;
6606 /* We don't need to do anything if we aren't in MIPS16 mode, or if
6607 we were invoked with the -msoft-float option. */
6608 if (!TARGET_MIPS16 || TARGET_SOFT_FLOAT_ABI)
6611 /* Figure out whether the value might come back in a floating-point
6613 fp_ret_p = retval && mips_return_mode_in_fpr_p (GET_MODE (retval));
6615 /* We don't need to do anything if there were no floating-point
6616 arguments and the value will not be returned in a floating-point
6618 if (fp_code == 0 && !fp_ret_p)
6621 /* We don't need to do anything if this is a call to a special
6622 MIPS16 support function. */
6624 if (mips16_stub_function_p (fn))
6627 /* If we're calling a locally-defined MIPS16 function, we know that
6628 it will return values in both the "soft-float" and "hard-float"
6629 registers. There is no need to use a stub to move the latter
6631 if (fp_code == 0 && mips16_local_function_p (fn))
6634 /* This code will only work for o32 and o64 abis. The other ABI's
6635 require more sophisticated support. */
6636 gcc_assert (TARGET_OLDABI);
6638 /* If we're calling via a function pointer, use one of the magic
6639 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
6640 Each stub expects the function address to arrive in register $2. */
6641 if (GET_CODE (fn) != SYMBOL_REF
6642 || !call_insn_operand (fn, VOIDmode))
6645 rtx stub_fn, insn, addr;
6648 /* If this is a locally-defined and locally-binding function,
6649 avoid the stub by calling the local alias directly. */
6650 if (mips16_local_function_p (fn))
6652 *fn_ptr = mips16_local_alias (fn);
6656 /* Create a SYMBOL_REF for the libgcc.a function. */
6658 sprintf (buf, "__mips16_call_stub_%s_%d",
6659 mips16_call_stub_mode_suffix (GET_MODE (retval)),
6662 sprintf (buf, "__mips16_call_stub_%d", fp_code);
6663 stub_fn = mips16_stub_function (buf);
6665 /* The function uses $2 as an argument, so calls to it
6666 cannot be lazily bound. */
6667 SYMBOL_REF_FLAGS (stub_fn) |= SYMBOL_FLAG_BIND_NOW;
6669 /* Load the target function into $2. */
6670 addr = gen_rtx_REG (Pmode, GP_REG_FIRST + 2);
6671 lazy_p = mips_load_call_address (MIPS_CALL_NORMAL, addr, fn);
6673 /* Emit the call. */
6674 insn = mips_expand_call (MIPS_CALL_NORMAL, retval, stub_fn,
6675 args_size, NULL_RTX, lazy_p);
6677 /* Tell GCC that this call does indeed use the value of $2. */
6678 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), addr);
6680 /* If we are handling a floating-point return value, we need to
6681 save $18 in the function prologue. Putting a note on the
6682 call will mean that df_regs_ever_live_p ($18) will be true if the
6683 call is not eliminated, and we can check that in the prologue
6686 CALL_INSN_FUNCTION_USAGE (insn) =
6687 gen_rtx_EXPR_LIST (VOIDmode,
6688 gen_rtx_CLOBBER (VOIDmode,
6689 gen_rtx_REG (word_mode, 18)),
6690 CALL_INSN_FUNCTION_USAGE (insn));
6695 /* We know the function we are going to call. If we have already
6696 built a stub, we don't need to do anything further. */
6697 fnname = targetm.strip_name_encoding (XSTR (fn, 0));
6698 for (l = mips16_stubs; l != NULL; l = l->next)
6699 if (strcmp (l->name, fnname) == 0)
6704 const char *separator;
6705 char *secname, *stubname;
6706 tree stubid, stubdecl;
6709 /* If the function does not return in FPRs, the special stub
6713 If the function does return in FPRs, the stub section is named
6714 .mips16.call.fp.FNNAME
6716 Build a decl for the stub. */
6717 secname = ACONCAT ((".mips16.call.", fp_ret_p ? "fp." : "",
6719 stubname = ACONCAT (("__call_stub_", fp_ret_p ? "fp_" : "",
6721 stubid = get_identifier (stubname);
6722 stubdecl = build_decl (BUILTINS_LOCATION,
6723 FUNCTION_DECL, stubid,
6724 build_function_type_list (void_type_node,
6726 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
6727 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
6728 RESULT_DECL, NULL_TREE,
6731 /* Output a comment. */
6732 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
6734 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
6738 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
6740 fprintf (asm_out_file, "%s%s", separator,
6741 (f & 3) == 1 ? "float" : "double");
6744 fprintf (asm_out_file, ")\n");
6746 /* Start the function definition. */
6747 assemble_start_function (stubdecl, stubname);
6748 mips_start_function_definition (stubname, false);
6752 fprintf (asm_out_file, "\t.cfi_startproc\n");
6754 /* Create a fake CFA 4 bytes below the stack pointer.
6755 This works around unwinders (like libgcc's) that expect
6756 the CFA for non-signal frames to be unique. */
6757 fprintf (asm_out_file, "\t.cfi_def_cfa 29,-4\n");
6759 /* "Save" $sp in itself so we don't use the fake CFA.
6760 This is: DW_CFA_val_expression r29, { DW_OP_reg29 }. */
6761 fprintf (asm_out_file, "\t.cfi_escape 0x16,29,1,0x6d\n");
6765 /* Load the address of the MIPS16 function into $25. Do this
6766 first so that targets with coprocessor interlocks can use
6767 an MFC1 to fill the delay slot. */
6768 if (TARGET_EXPLICIT_RELOCS)
6770 output_asm_insn ("lui\t%^,%%hi(%0)", &fn);
6771 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn);
6774 output_asm_insn ("la\t%^,%0", &fn);
6777 /* Move the arguments from general registers to floating-point
6779 mips_output_args_xfer (fp_code, 't');
6783 /* Save the return address in $18 and call the non-MIPS16 function.
6784 The stub's caller knows that $18 might be clobbered, even though
6785 $18 is usually a call-saved register. */
6786 fprintf (asm_out_file, "\tmove\t%s,%s\n",
6787 reg_names[GP_REG_FIRST + 18], reg_names[RETURN_ADDR_REGNUM]);
6788 output_asm_insn (MIPS_CALL ("jal", &fn, 0, -1), &fn);
6789 fprintf (asm_out_file, "\t.cfi_register 31,18\n");
6791 /* Move the result from floating-point registers to
6792 general registers. */
6793 switch (GET_MODE (retval))
6796 mips_output_32bit_xfer ('f', GP_RETURN + TARGET_BIG_ENDIAN,
6798 ? FP_REG_FIRST + MAX_FPRS_PER_FMT
6800 mips_output_32bit_xfer ('f', GP_RETURN + TARGET_LITTLE_ENDIAN,
6801 TARGET_LITTLE_ENDIAN
6802 ? FP_REG_FIRST + MAX_FPRS_PER_FMT
6804 if (GET_MODE (retval) == SCmode && TARGET_64BIT)
6806 /* On 64-bit targets, complex floats are returned in
6807 a single GPR, such that "sd" on a suitably-aligned
6808 target would store the value correctly. */
6809 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
6810 reg_names[GP_RETURN + TARGET_BIG_ENDIAN],
6811 reg_names[GP_RETURN + TARGET_BIG_ENDIAN]);
6812 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
6813 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN],
6814 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN]);
6815 fprintf (asm_out_file, "\tdsrl\t%s,%s,32\n",
6816 reg_names[GP_RETURN + TARGET_BIG_ENDIAN],
6817 reg_names[GP_RETURN + TARGET_BIG_ENDIAN]);
6818 fprintf (asm_out_file, "\tor\t%s,%s,%s\n",
6819 reg_names[GP_RETURN],
6820 reg_names[GP_RETURN],
6821 reg_names[GP_RETURN + 1]);
6826 mips_output_32bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6830 mips_output_64bit_xfer ('f', GP_RETURN + (8 / UNITS_PER_WORD),
6831 FP_REG_FIRST + MAX_FPRS_PER_FMT);
6835 mips_output_64bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6841 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 18]);
6842 fprintf (asm_out_file, "\t.cfi_endproc\n");
6846 /* Jump to the previously-loaded address. */
6847 output_asm_insn ("jr\t%^", NULL);
6850 #ifdef ASM_DECLARE_FUNCTION_SIZE
6851 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
6854 mips_end_function_definition (stubname);
6856 /* Record this stub. */
6857 l = XNEW (struct mips16_stub);
6858 l->name = xstrdup (fnname);
6859 l->fp_ret_p = fp_ret_p;
6860 l->next = mips16_stubs;
6864 /* If we expect a floating-point return value, but we've built a
6865 stub which does not expect one, then we're in trouble. We can't
6866 use the existing stub, because it won't handle the floating-point
6867 value. We can't build a new stub, because the linker won't know
6868 which stub to use for the various calls in this object file.
6869 Fortunately, this case is illegal, since it means that a function
6870 was declared in two different ways in a single compilation. */
6871 if (fp_ret_p && !l->fp_ret_p)
6872 error ("cannot handle inconsistent calls to %qs", fnname);
6874 if (retval == NULL_RTX)
6875 insn = gen_call_internal_direct (fn, args_size);
6877 insn = gen_call_value_internal_direct (retval, fn, args_size);
6878 insn = mips_emit_call_insn (insn, fn, fn, false);
6880 /* If we are calling a stub which handles a floating-point return
6881 value, we need to arrange to save $18 in the prologue. We do this
6882 by marking the function call as using the register. The prologue
6883 will later see that it is used, and emit code to save it. */
6885 CALL_INSN_FUNCTION_USAGE (insn) =
6886 gen_rtx_EXPR_LIST (VOIDmode,
6887 gen_rtx_CLOBBER (VOIDmode,
6888 gen_rtx_REG (word_mode, 18)),
6889 CALL_INSN_FUNCTION_USAGE (insn));
6894 /* Expand a call of type TYPE. RESULT is where the result will go (null
6895 for "call"s and "sibcall"s), ADDR is the address of the function,
6896 ARGS_SIZE is the size of the arguments and AUX is the value passed
6897 to us by mips_function_arg. LAZY_P is true if this call already
6898 involves a lazily-bound function address (such as when calling
6899 functions through a MIPS16 hard-float stub).
6901 Return the call itself. */
6904 mips_expand_call (enum mips_call_type type, rtx result, rtx addr,
6905 rtx args_size, rtx aux, bool lazy_p)
6907 rtx orig_addr, pattern, insn;
6910 fp_code = aux == 0 ? 0 : (int) GET_MODE (aux);
6911 insn = mips16_build_call_stub (result, &addr, args_size, fp_code);
6914 gcc_assert (!lazy_p && type == MIPS_CALL_NORMAL);
6919 if (!call_insn_operand (addr, VOIDmode))
6921 if (type == MIPS_CALL_EPILOGUE)
6922 addr = MIPS_EPILOGUE_TEMP (Pmode);
6924 addr = gen_reg_rtx (Pmode);
6925 lazy_p |= mips_load_call_address (type, addr, orig_addr);
6930 rtx (*fn) (rtx, rtx);
6932 if (type == MIPS_CALL_SIBCALL)
6933 fn = gen_sibcall_internal;
6935 fn = gen_call_internal;
6937 pattern = fn (addr, args_size);
6939 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
6941 /* Handle return values created by mips_return_fpr_pair. */
6942 rtx (*fn) (rtx, rtx, rtx, rtx);
6945 if (type == MIPS_CALL_SIBCALL)
6946 fn = gen_sibcall_value_multiple_internal;
6948 fn = gen_call_value_multiple_internal;
6950 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
6951 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
6952 pattern = fn (reg1, addr, args_size, reg2);
6956 rtx (*fn) (rtx, rtx, rtx);
6958 if (type == MIPS_CALL_SIBCALL)
6959 fn = gen_sibcall_value_internal;
6961 fn = gen_call_value_internal;
6963 /* Handle return values created by mips_return_fpr_single. */
6964 if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 1)
6965 result = XEXP (XVECEXP (result, 0, 0), 0);
6966 pattern = fn (result, addr, args_size);
6969 return mips_emit_call_insn (pattern, orig_addr, addr, lazy_p);
6972 /* Split call instruction INSN into a $gp-clobbering call and
6973 (where necessary) an instruction to restore $gp from its save slot.
6974 CALL_PATTERN is the pattern of the new call. */
6977 mips_split_call (rtx insn, rtx call_pattern)
6979 emit_call_insn (call_pattern);
6980 if (!find_reg_note (insn, REG_NORETURN, 0))
6981 /* Pick a temporary register that is suitable for both MIPS16 and
6982 non-MIPS16 code. $4 and $5 are used for returning complex double
6983 values in soft-float code, so $6 is the first suitable candidate. */
6984 mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode, GP_ARG_FIRST + 2));
6987 /* Return true if a call to DECL may need to use JALX. */
6990 mips_call_may_need_jalx_p (tree decl)
6992 /* If the current translation unit would use a different mode for DECL,
6993 assume that the call needs JALX. */
6994 if (mips_get_compress_mode (decl) != TARGET_COMPRESSION)
6997 /* mips_get_compress_mode is always accurate for locally-binding
6998 functions in the current translation unit. */
6999 if (!DECL_EXTERNAL (decl) && targetm.binds_local_p (decl))
7002 /* When -minterlink-compressed is in effect, assume that functions
7003 could use a different encoding mode unless an attribute explicitly
7004 tells us otherwise. */
7005 if (TARGET_INTERLINK_COMPRESSED)
7007 if (!TARGET_COMPRESSION
7008 && mips_get_compress_off_flags (DECL_ATTRIBUTES (decl)) ==0)
7010 if (TARGET_COMPRESSION
7011 && mips_get_compress_on_flags (DECL_ATTRIBUTES (decl)) == 0)
7018 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
7021 mips_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
7023 if (!TARGET_SIBCALLS)
7026 /* Interrupt handlers need special epilogue code and therefore can't
7028 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
7031 /* Direct Js are only possible to functions that use the same ISA encoding.
7032 There is no JX counterpoart of JALX. */
7034 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode)
7035 && mips_call_may_need_jalx_p (decl))
7038 /* Sibling calls should not prevent lazy binding. Lazy-binding stubs
7039 require $gp to be valid on entry, so sibcalls can only use stubs
7040 if $gp is call-clobbered. */
7042 && TARGET_CALL_SAVED_GP
7043 && !TARGET_ABICALLS_PIC0
7044 && !targetm.binds_local_p (decl))
7051 /* Emit code to move general operand SRC into condition-code
7052 register DEST given that SCRATCH is a scratch TFmode FPR.
7059 where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */
7062 mips_expand_fcc_reload (rtx dest, rtx src, rtx scratch)
7066 /* Change the source to SFmode. */
7068 src = adjust_address (src, SFmode, 0);
7069 else if (REG_P (src) || GET_CODE (src) == SUBREG)
7070 src = gen_rtx_REG (SFmode, true_regnum (src));
7072 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
7073 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + MAX_FPRS_PER_FMT);
7075 mips_emit_move (copy_rtx (fp1), src);
7076 mips_emit_move (copy_rtx (fp2), CONST0_RTX (SFmode));
7077 emit_insn (gen_slt_sf (dest, fp2, fp1));
7080 /* Implement MOVE_BY_PIECES_P. */
7083 mips_move_by_pieces_p (unsigned HOST_WIDE_INT size, unsigned int align)
7087 /* movmemsi is meant to generate code that is at least as good as
7088 move_by_pieces. However, movmemsi effectively uses a by-pieces
7089 implementation both for moves smaller than a word and for
7090 word-aligned moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT
7091 bytes. We should allow the tree-level optimisers to do such
7092 moves by pieces, as it often exposes other optimization
7093 opportunities. We might as well continue to use movmemsi at
7094 the rtl level though, as it produces better code when
7095 scheduling is disabled (such as at -O). */
7096 if (currently_expanding_to_rtl)
7098 if (align < BITS_PER_WORD)
7099 return size < UNITS_PER_WORD;
7100 return size <= MIPS_MAX_MOVE_BYTES_STRAIGHT;
7102 /* The default value. If this becomes a target hook, we should
7103 call the default definition instead. */
7104 return (move_by_pieces_ninsns (size, align, MOVE_MAX_PIECES + 1)
7105 < (unsigned int) MOVE_RATIO (optimize_insn_for_speed_p ()));
7108 /* Implement STORE_BY_PIECES_P. */
7111 mips_store_by_pieces_p (unsigned HOST_WIDE_INT size, unsigned int align)
7113 /* Storing by pieces involves moving constants into registers
7114 of size MIN (ALIGN, BITS_PER_WORD), then storing them.
7115 We need to decide whether it is cheaper to load the address of
7116 constant data into a register and use a block move instead. */
7118 /* If the data is only byte aligned, then:
7120 (a1) A block move of less than 4 bytes would involve three 3 LBs and
7121 3 SBs. We might as well use 3 single-instruction LIs and 3 SBs
7124 (a2) A block move of 4 bytes from aligned source data can use an
7125 LW/SWL/SWR sequence. This is often better than the 4 LIs and
7126 4 SBs that we would generate when storing by pieces. */
7127 if (align <= BITS_PER_UNIT)
7130 /* If the data is 2-byte aligned, then:
7132 (b1) A block move of less than 4 bytes would use a combination of LBs,
7133 LHs, SBs and SHs. We get better code by using single-instruction
7134 LIs, SBs and SHs instead.
7136 (b2) A block move of 4 bytes from aligned source data would again use
7137 an LW/SWL/SWR sequence. In most cases, loading the address of
7138 the source data would require at least one extra instruction.
7139 It is often more efficient to use 2 single-instruction LIs and
7142 (b3) A block move of up to 3 additional bytes would be like (b1).
7144 (b4) A block move of 8 bytes from aligned source data can use two
7145 LW/SWL/SWR sequences or a single LD/SDL/SDR sequence. Both
7146 sequences are better than the 4 LIs and 4 SHs that we'd generate
7147 when storing by pieces.
7149 The reasoning for higher alignments is similar:
7151 (c1) A block move of less than 4 bytes would be the same as (b1).
7153 (c2) A block move of 4 bytes would use an LW/SW sequence. Again,
7154 loading the address of the source data would typically require
7155 at least one extra instruction. It is generally better to use
7158 (c3) A block move of up to 3 additional bytes would be like (b1).
7160 (c4) A block move of 8 bytes can use two LW/SW sequences or a single
7161 LD/SD sequence, and in these cases we've traditionally preferred
7162 the memory copy over the more bulky constant moves. */
7166 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
7167 Assume that the areas do not overlap. */
7170 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
7172 HOST_WIDE_INT offset, delta;
7173 unsigned HOST_WIDE_INT bits;
7175 enum machine_mode mode;
7178 /* Work out how many bits to move at a time. If both operands have
7179 half-word alignment, it is usually better to move in half words.
7180 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
7181 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
7182 Otherwise move word-sized chunks. */
7183 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
7184 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
7185 bits = BITS_PER_WORD / 2;
7187 bits = BITS_PER_WORD;
7189 mode = mode_for_size (bits, MODE_INT, 0);
7190 delta = bits / BITS_PER_UNIT;
7192 /* Allocate a buffer for the temporary registers. */
7193 regs = XALLOCAVEC (rtx, length / delta);
7195 /* Load as many BITS-sized chunks as possible. Use a normal load if
7196 the source has enough alignment, otherwise use left/right pairs. */
7197 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
7199 regs[i] = gen_reg_rtx (mode);
7200 if (MEM_ALIGN (src) >= bits)
7201 mips_emit_move (regs[i], adjust_address (src, mode, offset));
7204 rtx part = adjust_address (src, BLKmode, offset);
7205 set_mem_size (part, delta);
7206 if (!mips_expand_ext_as_unaligned_load (regs[i], part, bits, 0, 0))
7211 /* Copy the chunks to the destination. */
7212 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
7213 if (MEM_ALIGN (dest) >= bits)
7214 mips_emit_move (adjust_address (dest, mode, offset), regs[i]);
7217 rtx part = adjust_address (dest, BLKmode, offset);
7218 set_mem_size (part, delta);
7219 if (!mips_expand_ins_as_unaligned_store (part, regs[i], bits, 0))
7223 /* Mop up any left-over bytes. */
7224 if (offset < length)
7226 src = adjust_address (src, BLKmode, offset);
7227 dest = adjust_address (dest, BLKmode, offset);
7228 move_by_pieces (dest, src, length - offset,
7229 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
7233 /* Helper function for doing a loop-based block operation on memory
7234 reference MEM. Each iteration of the loop will operate on LENGTH
7237 Create a new base register for use within the loop and point it to
7238 the start of MEM. Create a new memory reference that uses this
7239 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
7242 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
7243 rtx *loop_reg, rtx *loop_mem)
7245 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
7247 /* Although the new mem does not refer to a known location,
7248 it does keep up to LENGTH bytes of alignment. */
7249 *loop_mem = change_address (mem, BLKmode, *loop_reg);
7250 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
7253 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
7254 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
7255 the memory regions do not overlap. */
7258 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length,
7259 HOST_WIDE_INT bytes_per_iter)
7261 rtx label, src_reg, dest_reg, final_src, test;
7262 HOST_WIDE_INT leftover;
7264 leftover = length % bytes_per_iter;
7267 /* Create registers and memory references for use within the loop. */
7268 mips_adjust_block_mem (src, bytes_per_iter, &src_reg, &src);
7269 mips_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest);
7271 /* Calculate the value that SRC_REG should have after the last iteration
7273 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
7276 /* Emit the start of the loop. */
7277 label = gen_label_rtx ();
7280 /* Emit the loop body. */
7281 mips_block_move_straight (dest, src, bytes_per_iter);
7283 /* Move on to the next block. */
7284 mips_emit_move (src_reg, plus_constant (Pmode, src_reg, bytes_per_iter));
7285 mips_emit_move (dest_reg, plus_constant (Pmode, dest_reg, bytes_per_iter));
7287 /* Emit the loop condition. */
7288 test = gen_rtx_NE (VOIDmode, src_reg, final_src);
7289 if (Pmode == DImode)
7290 emit_jump_insn (gen_cbranchdi4 (test, src_reg, final_src, label));
7292 emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label));
7294 /* Mop up any left-over bytes. */
7296 mips_block_move_straight (dest, src, leftover);
7299 /* Expand a movmemsi instruction, which copies LENGTH bytes from
7300 memory reference SRC to memory reference DEST. */
7303 mips_expand_block_move (rtx dest, rtx src, rtx length)
7305 if (CONST_INT_P (length))
7307 if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)
7309 mips_block_move_straight (dest, src, INTVAL (length));
7314 mips_block_move_loop (dest, src, INTVAL (length),
7315 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER);
7322 /* Expand a loop of synci insns for the address range [BEGIN, END). */
7325 mips_expand_synci_loop (rtx begin, rtx end)
7327 rtx inc, label, end_label, cmp_result, mask, length;
7329 /* Create end_label. */
7330 end_label = gen_label_rtx ();
7332 /* Check if begin equals end. */
7333 cmp_result = gen_rtx_EQ (VOIDmode, begin, end);
7334 emit_jump_insn (gen_condjump (cmp_result, end_label));
7336 /* Load INC with the cache line size (rdhwr INC,$1). */
7337 inc = gen_reg_rtx (Pmode);
7338 emit_insn (PMODE_INSN (gen_rdhwr_synci_step, (inc)));
7340 /* Check if inc is 0. */
7341 cmp_result = gen_rtx_EQ (VOIDmode, inc, const0_rtx);
7342 emit_jump_insn (gen_condjump (cmp_result, end_label));
7344 /* Calculate mask. */
7345 mask = mips_force_unary (Pmode, NEG, inc);
7347 /* Mask out begin by mask. */
7348 begin = mips_force_binary (Pmode, AND, begin, mask);
7350 /* Calculate length. */
7351 length = mips_force_binary (Pmode, MINUS, end, begin);
7353 /* Loop back to here. */
7354 label = gen_label_rtx ();
7357 emit_insn (gen_synci (begin));
7359 /* Update length. */
7360 mips_emit_binary (MINUS, length, length, inc);
7363 mips_emit_binary (PLUS, begin, begin, inc);
7365 /* Check if length is greater than 0. */
7366 cmp_result = gen_rtx_GT (VOIDmode, length, const0_rtx);
7367 emit_jump_insn (gen_condjump (cmp_result, label));
7369 emit_label (end_label);
7372 /* Expand a QI or HI mode atomic memory operation.
7374 GENERATOR contains a pointer to the gen_* function that generates
7375 the SI mode underlying atomic operation using masks that we
7378 RESULT is the return register for the operation. Its value is NULL
7381 MEM is the location of the atomic access.
7383 OLDVAL is the first operand for the operation.
7385 NEWVAL is the optional second operand for the operation. Its value
7386 is NULL if unused. */
7389 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator,
7390 rtx result, rtx mem, rtx oldval, rtx newval)
7392 rtx orig_addr, memsi_addr, memsi, shift, shiftsi, unshifted_mask;
7393 rtx unshifted_mask_reg, mask, inverted_mask, si_op;
7395 enum machine_mode mode;
7397 mode = GET_MODE (mem);
7399 /* Compute the address of the containing SImode value. */
7400 orig_addr = force_reg (Pmode, XEXP (mem, 0));
7401 memsi_addr = mips_force_binary (Pmode, AND, orig_addr,
7402 force_reg (Pmode, GEN_INT (-4)));
7404 /* Create a memory reference for it. */
7405 memsi = gen_rtx_MEM (SImode, memsi_addr);
7406 set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER);
7407 MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem);
7409 /* Work out the byte offset of the QImode or HImode value,
7410 counting from the least significant byte. */
7411 shift = mips_force_binary (Pmode, AND, orig_addr, GEN_INT (3));
7412 if (TARGET_BIG_ENDIAN)
7413 mips_emit_binary (XOR, shift, shift, GEN_INT (mode == QImode ? 3 : 2));
7415 /* Multiply by eight to convert the shift value from bytes to bits. */
7416 mips_emit_binary (ASHIFT, shift, shift, GEN_INT (3));
7418 /* Make the final shift an SImode value, so that it can be used in
7419 SImode operations. */
7420 shiftsi = force_reg (SImode, gen_lowpart (SImode, shift));
7422 /* Set MASK to an inclusive mask of the QImode or HImode value. */
7423 unshifted_mask = GEN_INT (GET_MODE_MASK (mode));
7424 unshifted_mask_reg = force_reg (SImode, unshifted_mask);
7425 mask = mips_force_binary (SImode, ASHIFT, unshifted_mask_reg, shiftsi);
7427 /* Compute the equivalent exclusive mask. */
7428 inverted_mask = gen_reg_rtx (SImode);
7429 emit_insn (gen_rtx_SET (VOIDmode, inverted_mask,
7430 gen_rtx_NOT (SImode, mask)));
7432 /* Shift the old value into place. */
7433 if (oldval != const0_rtx)
7435 oldval = convert_modes (SImode, mode, oldval, true);
7436 oldval = force_reg (SImode, oldval);
7437 oldval = mips_force_binary (SImode, ASHIFT, oldval, shiftsi);
7440 /* Do the same for the new value. */
7441 if (newval && newval != const0_rtx)
7443 newval = convert_modes (SImode, mode, newval, true);
7444 newval = force_reg (SImode, newval);
7445 newval = mips_force_binary (SImode, ASHIFT, newval, shiftsi);
7448 /* Do the SImode atomic access. */
7450 res = gen_reg_rtx (SImode);
7452 si_op = generator.fn_6 (res, memsi, mask, inverted_mask, oldval, newval);
7454 si_op = generator.fn_5 (res, memsi, mask, inverted_mask, oldval);
7456 si_op = generator.fn_4 (memsi, mask, inverted_mask, oldval);
7462 /* Shift and convert the result. */
7463 mips_emit_binary (AND, res, res, mask);
7464 mips_emit_binary (LSHIFTRT, res, res, shiftsi);
7465 mips_emit_move (result, gen_lowpart (GET_MODE (result), res));
7469 /* Return true if it is possible to use left/right accesses for a
7470 bitfield of WIDTH bits starting BITPOS bits into BLKmode memory OP.
7471 When returning true, update *LEFT and *RIGHT as follows:
7473 *LEFT is a QImode reference to the first byte if big endian or
7474 the last byte if little endian. This address can be used in the
7475 left-side instructions (LWL, SWL, LDL, SDL).
7477 *RIGHT is a QImode reference to the opposite end of the field and
7478 can be used in the patterning right-side instruction. */
7481 mips_get_unaligned_mem (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos,
7482 rtx *left, rtx *right)
7486 /* Check that the size is valid. */
7487 if (width != 32 && (!TARGET_64BIT || width != 64))
7490 /* We can only access byte-aligned values. Since we are always passed
7491 a reference to the first byte of the field, it is not necessary to
7492 do anything with BITPOS after this check. */
7493 if (bitpos % BITS_PER_UNIT != 0)
7496 /* Reject aligned bitfields: we want to use a normal load or store
7497 instead of a left/right pair. */
7498 if (MEM_ALIGN (op) >= width)
7501 /* Get references to both ends of the field. */
7502 first = adjust_address (op, QImode, 0);
7503 last = adjust_address (op, QImode, width / BITS_PER_UNIT - 1);
7505 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
7506 correspond to the MSB and RIGHT to the LSB. */
7507 if (TARGET_BIG_ENDIAN)
7508 *left = first, *right = last;
7510 *left = last, *right = first;
7515 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
7516 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
7517 the operation is the equivalent of:
7519 (set DEST (*_extract SRC WIDTH BITPOS))
7521 Return true on success. */
7524 mips_expand_ext_as_unaligned_load (rtx dest, rtx src, HOST_WIDE_INT width,
7525 HOST_WIDE_INT bitpos, bool unsigned_p)
7527 rtx left, right, temp;
7528 rtx dest1 = NULL_RTX;
7530 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
7531 be a DImode, create a new temp and emit a zero extend at the end. */
7532 if (GET_MODE (dest) == DImode
7534 && GET_MODE_BITSIZE (SImode) == width)
7537 dest = gen_reg_rtx (SImode);
7540 if (!mips_get_unaligned_mem (src, width, bitpos, &left, &right))
7543 temp = gen_reg_rtx (GET_MODE (dest));
7544 if (GET_MODE (dest) == DImode)
7546 emit_insn (gen_mov_ldl (temp, src, left));
7547 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
7551 emit_insn (gen_mov_lwl (temp, src, left));
7552 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
7555 /* If we were loading 32bits and the original register was DI then
7556 sign/zero extend into the orignal dest. */
7560 emit_insn (gen_zero_extendsidi2 (dest1, dest));
7562 emit_insn (gen_extendsidi2 (dest1, dest));
7567 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
7568 BITPOS and SRC are the operands passed to the expander; the operation
7569 is the equivalent of:
7571 (set (zero_extract DEST WIDTH BITPOS) SRC)
7573 Return true on success. */
7576 mips_expand_ins_as_unaligned_store (rtx dest, rtx src, HOST_WIDE_INT width,
7577 HOST_WIDE_INT bitpos)
7580 enum machine_mode mode;
7582 if (!mips_get_unaligned_mem (dest, width, bitpos, &left, &right))
7585 mode = mode_for_size (width, MODE_INT, 0);
7586 src = gen_lowpart (mode, src);
7589 emit_insn (gen_mov_sdl (dest, src, left));
7590 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
7594 emit_insn (gen_mov_swl (dest, src, left));
7595 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
7600 /* Return true if X is a MEM with the same size as MODE. */
7603 mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
7606 && MEM_SIZE_KNOWN_P (x)
7607 && MEM_SIZE (x) == GET_MODE_SIZE (mode));
7610 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
7611 source of an "ext" instruction or the destination of an "ins"
7612 instruction. OP must be a register operand and the following
7613 conditions must hold:
7615 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
7616 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7617 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7619 Also reject lengths equal to a word as they are better handled
7620 by the move patterns. */
7623 mips_use_ins_ext_p (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos)
7625 if (!ISA_HAS_EXT_INS
7626 || !register_operand (op, VOIDmode)
7627 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
7630 if (!IN_RANGE (width, 1, GET_MODE_BITSIZE (GET_MODE (op)) - 1))
7633 if (bitpos < 0 || bitpos + width > GET_MODE_BITSIZE (GET_MODE (op)))
7639 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
7640 operation if MAXLEN is the maxium length of consecutive bits that
7641 can make up MASK. MODE is the mode of the operation. See
7642 mask_low_and_shift_len for the actual definition. */
7645 mask_low_and_shift_p (enum machine_mode mode, rtx mask, rtx shift, int maxlen)
7647 return IN_RANGE (mask_low_and_shift_len (mode, mask, shift), 1, maxlen);
7650 /* Return true iff OP1 and OP2 are valid operands together for the
7651 *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider,
7652 see the table in the comment before the pattern. */
7655 and_operands_ok (enum machine_mode mode, rtx op1, rtx op2)
7657 return (memory_operand (op1, mode)
7658 ? and_load_operand (op2, mode)
7659 : and_reg_operand (op2, mode));
7662 /* The canonical form of a mask-low-and-shift-left operation is
7663 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
7664 cleared. Thus we need to shift MASK to the right before checking if it
7665 is a valid mask value. MODE is the mode of the operation. If true
7666 return the length of the mask, otherwise return -1. */
7669 mask_low_and_shift_len (enum machine_mode mode, rtx mask, rtx shift)
7671 HOST_WIDE_INT shval;
7673 shval = INTVAL (shift) & (GET_MODE_BITSIZE (mode) - 1);
7674 return exact_log2 ((UINTVAL (mask) >> shval) + 1);
7677 /* Return true if -msplit-addresses is selected and should be honored.
7679 -msplit-addresses is a half-way house between explicit relocations
7680 and the traditional assembler macros. It can split absolute 32-bit
7681 symbolic constants into a high/lo_sum pair but uses macros for other
7684 Like explicit relocation support for REL targets, it relies
7685 on GNU extensions in the assembler and the linker.
7687 Although this code should work for -O0, it has traditionally
7688 been treated as an optimization. */
7691 mips_split_addresses_p (void)
7693 return (TARGET_SPLIT_ADDRESSES
7697 && !ABI_HAS_64BIT_SYMBOLS);
7700 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
7703 mips_init_relocs (void)
7705 memset (mips_split_p, '\0', sizeof (mips_split_p));
7706 memset (mips_split_hi_p, '\0', sizeof (mips_split_hi_p));
7707 memset (mips_use_pcrel_pool_p, '\0', sizeof (mips_use_pcrel_pool_p));
7708 memset (mips_hi_relocs, '\0', sizeof (mips_hi_relocs));
7709 memset (mips_lo_relocs, '\0', sizeof (mips_lo_relocs));
7711 if (TARGET_MIPS16_PCREL_LOADS)
7712 mips_use_pcrel_pool_p[SYMBOL_ABSOLUTE] = true;
7715 if (ABI_HAS_64BIT_SYMBOLS)
7717 if (TARGET_EXPLICIT_RELOCS)
7719 mips_split_p[SYMBOL_64_HIGH] = true;
7720 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
7721 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
7723 mips_split_p[SYMBOL_64_MID] = true;
7724 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
7725 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
7727 mips_split_p[SYMBOL_64_LOW] = true;
7728 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
7729 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
7731 mips_split_p[SYMBOL_ABSOLUTE] = true;
7732 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
7737 if (TARGET_EXPLICIT_RELOCS
7738 || mips_split_addresses_p ()
7741 mips_split_p[SYMBOL_ABSOLUTE] = true;
7742 mips_hi_relocs[SYMBOL_ABSOLUTE] = "%hi(";
7743 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
7750 /* The high part is provided by a pseudo copy of $gp. */
7751 mips_split_p[SYMBOL_GP_RELATIVE] = true;
7752 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gprel(";
7754 else if (TARGET_EXPLICIT_RELOCS)
7755 /* Small data constants are kept whole until after reload,
7756 then lowered by mips_rewrite_small_data. */
7757 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gp_rel(";
7759 if (TARGET_EXPLICIT_RELOCS)
7761 mips_split_p[SYMBOL_GOT_PAGE_OFST] = true;
7764 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
7765 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%got_ofst(";
7769 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
7770 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%lo(";
7773 /* Expose the use of $28 as soon as possible. */
7774 mips_split_hi_p[SYMBOL_GOT_PAGE_OFST] = true;
7778 /* The HIGH and LO_SUM are matched by special .md patterns. */
7779 mips_split_p[SYMBOL_GOT_DISP] = true;
7781 mips_split_p[SYMBOL_GOTOFF_DISP] = true;
7782 mips_hi_relocs[SYMBOL_GOTOFF_DISP] = "%got_hi(";
7783 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_lo(";
7785 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
7786 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
7787 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
7792 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_disp(";
7794 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got(";
7795 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
7797 /* Expose the use of $28 as soon as possible. */
7798 mips_split_p[SYMBOL_GOT_DISP] = true;
7804 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
7805 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
7806 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
7809 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
7810 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
7812 if (TARGET_MIPS16_PCREL_LOADS)
7814 mips_use_pcrel_pool_p[SYMBOL_DTPREL] = true;
7815 mips_use_pcrel_pool_p[SYMBOL_TPREL] = true;
7819 mips_split_p[SYMBOL_DTPREL] = true;
7820 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
7821 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
7823 mips_split_p[SYMBOL_TPREL] = true;
7824 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
7825 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
7828 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
7829 mips_lo_relocs[SYMBOL_HALF] = "%half(";
7832 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
7833 in context CONTEXT. RELOCS is the array of relocations to use. */
7836 mips_print_operand_reloc (FILE *file, rtx op, enum mips_symbol_context context,
7837 const char **relocs)
7839 enum mips_symbol_type symbol_type;
7842 symbol_type = mips_classify_symbolic_expression (op, context);
7843 gcc_assert (relocs[symbol_type]);
7845 fputs (relocs[symbol_type], file);
7846 output_addr_const (file, mips_strip_unspec_address (op));
7847 for (p = relocs[symbol_type]; *p != 0; p++)
7852 /* Start a new block with the given asm switch enabled. If we need
7853 to print a directive, emit PREFIX before it and SUFFIX after it. */
7856 mips_push_asm_switch_1 (struct mips_asm_switch *asm_switch,
7857 const char *prefix, const char *suffix)
7859 if (asm_switch->nesting_level == 0)
7860 fprintf (asm_out_file, "%s.set\tno%s%s", prefix, asm_switch->name, suffix);
7861 asm_switch->nesting_level++;
7864 /* Likewise, but end a block. */
7867 mips_pop_asm_switch_1 (struct mips_asm_switch *asm_switch,
7868 const char *prefix, const char *suffix)
7870 gcc_assert (asm_switch->nesting_level);
7871 asm_switch->nesting_level--;
7872 if (asm_switch->nesting_level == 0)
7873 fprintf (asm_out_file, "%s.set\t%s%s", prefix, asm_switch->name, suffix);
7876 /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1
7877 that either print a complete line or print nothing. */
7880 mips_push_asm_switch (struct mips_asm_switch *asm_switch)
7882 mips_push_asm_switch_1 (asm_switch, "\t", "\n");
7886 mips_pop_asm_switch (struct mips_asm_switch *asm_switch)
7888 mips_pop_asm_switch_1 (asm_switch, "\t", "\n");
7891 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
7892 The punctuation characters are:
7894 '(' Start a nested ".set noreorder" block.
7895 ')' End a nested ".set noreorder" block.
7896 '[' Start a nested ".set noat" block.
7897 ']' End a nested ".set noat" block.
7898 '<' Start a nested ".set nomacro" block.
7899 '>' End a nested ".set nomacro" block.
7900 '*' Behave like %(%< if generating a delayed-branch sequence.
7901 '#' Print a nop if in a ".set noreorder" block.
7902 '/' Like '#', but do nothing within a delayed-branch sequence.
7903 '?' Print "l" if mips_branch_likely is true
7904 '~' Print a nop if mips_branch_likely is true
7905 '.' Print the name of the register with a hard-wired zero (zero or $0).
7906 '@' Print the name of the assembler temporary register (at or $1).
7907 '^' Print the name of the pic call-through register (t9 or $25).
7908 '+' Print the name of the gp register (usually gp or $28).
7909 '$' Print the name of the stack pointer register (sp or $29).
7910 ':' Print "c" to use the compact version if the delay slot is a nop.
7911 '!' Print "s" to use the short version if the delay slot contains a
7914 See also mips_init_print_operand_pucnt. */
7917 mips_print_operand_punctuation (FILE *file, int ch)
7922 mips_push_asm_switch_1 (&mips_noreorder, "", "\n\t");
7926 mips_pop_asm_switch_1 (&mips_noreorder, "\n\t", "");
7930 mips_push_asm_switch_1 (&mips_noat, "", "\n\t");
7934 mips_pop_asm_switch_1 (&mips_noat, "\n\t", "");
7938 mips_push_asm_switch_1 (&mips_nomacro, "", "\n\t");
7942 mips_pop_asm_switch_1 (&mips_nomacro, "\n\t", "");
7946 if (final_sequence != 0)
7948 mips_print_operand_punctuation (file, '(');
7949 mips_print_operand_punctuation (file, '<');
7954 if (mips_noreorder.nesting_level > 0)
7955 fputs ("\n\tnop", file);
7959 /* Print an extra newline so that the delayed insn is separated
7960 from the following ones. This looks neater and is consistent
7961 with non-nop delayed sequences. */
7962 if (mips_noreorder.nesting_level > 0 && final_sequence == 0)
7963 fputs ("\n\tnop\n", file);
7967 if (mips_branch_likely)
7972 if (mips_branch_likely)
7973 fputs ("\n\tnop", file);
7977 fputs (reg_names[GP_REG_FIRST + 0], file);
7981 fputs (reg_names[AT_REGNUM], file);
7985 fputs (reg_names[PIC_FUNCTION_ADDR_REGNUM], file);
7989 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
7993 fputs (reg_names[STACK_POINTER_REGNUM], file);
7997 /* When final_sequence is 0, the delay slot will be a nop. We can
7998 use the compact version for microMIPS. */
7999 if (final_sequence == 0)
8004 /* If the delay slot instruction is short, then use the
8006 if (final_sequence == 0
8007 || get_attr_length (XVECEXP (final_sequence, 0, 1)) == 2)
8017 /* Initialize mips_print_operand_punct. */
8020 mips_init_print_operand_punct (void)
8024 for (p = "()[]<>*#/?~.@^+$:!"; *p; p++)
8025 mips_print_operand_punct[(unsigned char) *p] = true;
8028 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
8029 associated with condition CODE. Print the condition part of the
8033 mips_print_int_branch_condition (FILE *file, enum rtx_code code, int letter)
8047 /* Conveniently, the MIPS names for these conditions are the same
8048 as their RTL equivalents. */
8049 fputs (GET_RTX_NAME (code), file);
8053 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
8058 /* Likewise floating-point branches. */
8061 mips_print_float_branch_condition (FILE *file, enum rtx_code code, int letter)
8066 fputs ("c1f", file);
8070 fputs ("c1t", file);
8074 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
8079 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
8082 mips_print_operand_punct_valid_p (unsigned char code)
8084 return mips_print_operand_punct[code];
8087 /* Implement TARGET_PRINT_OPERAND. The MIPS-specific operand codes are:
8089 'X' Print CONST_INT OP in hexadecimal format.
8090 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
8091 'd' Print CONST_INT OP in decimal.
8092 'm' Print one less than CONST_INT OP in decimal.
8093 'h' Print the high-part relocation associated with OP, after stripping
8095 'R' Print the low-part relocation associated with OP.
8096 'C' Print the integer branch condition for comparison OP.
8097 'N' Print the inverse of the integer branch condition for comparison OP.
8098 'F' Print the FPU branch condition for comparison OP.
8099 'W' Print the inverse of the FPU branch condition for comparison OP.
8100 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
8101 'z' for (eq:?I ...), 'n' for (ne:?I ...).
8102 't' Like 'T', but with the EQ/NE cases reversed
8103 'Y' Print mips_fp_conditions[INTVAL (OP)]
8104 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
8105 'q' Print a DSP accumulator register.
8106 'D' Print the second part of a double-word register or memory operand.
8107 'L' Print the low-order register in a double-word register operand.
8108 'M' Print high-order register in a double-word register operand.
8109 'z' Print $0 if OP is zero, otherwise print OP normally.
8110 'b' Print the address of a memory operand, without offset. */
8113 mips_print_operand (FILE *file, rtx op, int letter)
8117 if (mips_print_operand_punct_valid_p (letter))
8119 mips_print_operand_punctuation (file, letter);
8124 code = GET_CODE (op);
8129 if (CONST_INT_P (op))
8130 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
8132 output_operand_lossage ("invalid use of '%%%c'", letter);
8136 if (CONST_INT_P (op))
8137 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op) & 0xffff);
8139 output_operand_lossage ("invalid use of '%%%c'", letter);
8143 if (CONST_INT_P (op))
8144 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op));
8146 output_operand_lossage ("invalid use of '%%%c'", letter);
8150 if (CONST_INT_P (op))
8151 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op) - 1);
8153 output_operand_lossage ("invalid use of '%%%c'", letter);
8159 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_hi_relocs);
8163 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_lo_relocs);
8167 mips_print_int_branch_condition (file, code, letter);
8171 mips_print_int_branch_condition (file, reverse_condition (code), letter);
8175 mips_print_float_branch_condition (file, code, letter);
8179 mips_print_float_branch_condition (file, reverse_condition (code),
8186 int truth = (code == NE) == (letter == 'T');
8187 fputc ("zfnt"[truth * 2 + ST_REG_P (REGNO (XEXP (op, 0)))], file);
8192 if (code == CONST_INT && UINTVAL (op) < ARRAY_SIZE (mips_fp_conditions))
8193 fputs (mips_fp_conditions[UINTVAL (op)], file);
8195 output_operand_lossage ("'%%%c' is not a valid operand prefix",
8202 mips_print_operand (file, op, 0);
8208 if (code == REG && MD_REG_P (REGNO (op)))
8209 fprintf (file, "$ac0");
8210 else if (code == REG && DSP_ACC_REG_P (REGNO (op)))
8211 fprintf (file, "$ac%c", reg_names[REGNO (op)][3]);
8213 output_operand_lossage ("invalid use of '%%%c'", letter);
8221 unsigned int regno = REGNO (op);
8222 if ((letter == 'M' && TARGET_LITTLE_ENDIAN)
8223 || (letter == 'L' && TARGET_BIG_ENDIAN)
8226 else if (letter && letter != 'z' && letter != 'M' && letter != 'L')
8227 output_operand_lossage ("invalid use of '%%%c'", letter);
8228 /* We need to print $0 .. $31 for COP0 registers. */
8229 if (COP0_REG_P (regno))
8230 fprintf (file, "$%s", ®_names[regno][4]);
8232 fprintf (file, "%s", reg_names[regno]);
8238 output_address (plus_constant (Pmode, XEXP (op, 0), 4));
8239 else if (letter == 'b')
8241 gcc_assert (REG_P (XEXP (op, 0)));
8242 mips_print_operand (file, XEXP (op, 0), 0);
8244 else if (letter && letter != 'z')
8245 output_operand_lossage ("invalid use of '%%%c'", letter);
8247 output_address (XEXP (op, 0));
8251 if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
8252 fputs (reg_names[GP_REG_FIRST], file);
8253 else if (letter && letter != 'z')
8254 output_operand_lossage ("invalid use of '%%%c'", letter);
8255 else if (CONST_GP_P (op))
8256 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
8258 output_addr_const (file, mips_strip_unspec_address (op));
8264 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
8267 mips_print_operand_address (FILE *file, rtx x)
8269 struct mips_address_info addr;
8271 if (mips_classify_address (&addr, x, word_mode, true))
8275 mips_print_operand (file, addr.offset, 0);
8276 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
8279 case ADDRESS_LO_SUM:
8280 mips_print_operand_reloc (file, addr.offset, SYMBOL_CONTEXT_MEM,
8282 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
8285 case ADDRESS_CONST_INT:
8286 output_addr_const (file, x);
8287 fprintf (file, "(%s)", reg_names[GP_REG_FIRST]);
8290 case ADDRESS_SYMBOLIC:
8291 output_addr_const (file, mips_strip_unspec_address (x));
8297 /* Implement TARGET_ENCODE_SECTION_INFO. */
8300 mips_encode_section_info (tree decl, rtx rtl, int first)
8302 default_encode_section_info (decl, rtl, first);
8304 if (TREE_CODE (decl) == FUNCTION_DECL)
8306 rtx symbol = XEXP (rtl, 0);
8307 tree type = TREE_TYPE (decl);
8309 /* Encode whether the symbol is short or long. */
8310 if ((TARGET_LONG_CALLS && !mips_near_type_p (type))
8311 || mips_far_type_p (type))
8312 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
8316 /* Implement TARGET_SELECT_RTX_SECTION. */
8319 mips_select_rtx_section (enum machine_mode mode, rtx x,
8320 unsigned HOST_WIDE_INT align)
8322 /* ??? Consider using mergeable small data sections. */
8323 if (mips_rtx_constant_in_small_data_p (mode))
8324 return get_named_section (NULL, ".sdata", 0);
8326 return default_elf_select_rtx_section (mode, x, align);
8329 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
8331 The complication here is that, with the combination TARGET_ABICALLS
8332 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
8333 absolute addresses, and should therefore not be included in the
8334 read-only part of a DSO. Handle such cases by selecting a normal
8335 data section instead of a read-only one. The logic apes that in
8336 default_function_rodata_section. */
8339 mips_function_rodata_section (tree decl)
8341 if (!TARGET_ABICALLS || TARGET_ABSOLUTE_ABICALLS || TARGET_GPWORD)
8342 return default_function_rodata_section (decl);
8344 if (decl && DECL_SECTION_NAME (decl))
8346 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
8347 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
8349 char *rname = ASTRDUP (name);
8351 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
8353 else if (flag_function_sections
8354 && flag_data_sections
8355 && strncmp (name, ".text.", 6) == 0)
8357 char *rname = ASTRDUP (name);
8358 memcpy (rname + 1, "data", 4);
8359 return get_section (rname, SECTION_WRITE, decl);
8362 return data_section;
8365 /* Implement TARGET_IN_SMALL_DATA_P. */
8368 mips_in_small_data_p (const_tree decl)
8370 unsigned HOST_WIDE_INT size;
8372 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
8375 /* We don't yet generate small-data references for -mabicalls
8376 or VxWorks RTP code. See the related -G handling in
8377 mips_option_override. */
8378 if (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
8381 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
8385 /* Reject anything that isn't in a known small-data section. */
8386 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
8387 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
8390 /* If a symbol is defined externally, the assembler will use the
8391 usual -G rules when deciding how to implement macros. */
8392 if (mips_lo_relocs[SYMBOL_GP_RELATIVE] || !DECL_EXTERNAL (decl))
8395 else if (TARGET_EMBEDDED_DATA)
8397 /* Don't put constants into the small data section: we want them
8398 to be in ROM rather than RAM. */
8399 if (TREE_CODE (decl) != VAR_DECL)
8402 if (TREE_READONLY (decl)
8403 && !TREE_SIDE_EFFECTS (decl)
8404 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
8408 /* Enforce -mlocal-sdata. */
8409 if (!TARGET_LOCAL_SDATA && !TREE_PUBLIC (decl))
8412 /* Enforce -mextern-sdata. */
8413 if (!TARGET_EXTERN_SDATA && DECL_P (decl))
8415 if (DECL_EXTERNAL (decl))
8417 if (DECL_COMMON (decl) && DECL_INITIAL (decl) == NULL)
8421 /* We have traditionally not treated zero-sized objects as small data,
8422 so this is now effectively part of the ABI. */
8423 size = int_size_in_bytes (TREE_TYPE (decl));
8424 return size > 0 && size <= mips_small_data_threshold;
8427 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
8428 anchors for small data: the GP register acts as an anchor in that
8429 case. We also don't want to use them for PC-relative accesses,
8430 where the PC acts as an anchor. */
8433 mips_use_anchors_for_symbol_p (const_rtx symbol)
8435 switch (mips_classify_symbol (symbol, SYMBOL_CONTEXT_MEM))
8437 case SYMBOL_PC_RELATIVE:
8438 case SYMBOL_GP_RELATIVE:
8442 return default_use_anchors_for_symbol_p (symbol);
8446 /* The MIPS debug format wants all automatic variables and arguments
8447 to be in terms of the virtual frame pointer (stack pointer before
8448 any adjustment in the function), while the MIPS 3.0 linker wants
8449 the frame pointer to be the stack pointer after the initial
8450 adjustment. So, we do the adjustment here. The arg pointer (which
8451 is eliminated) points to the virtual frame pointer, while the frame
8452 pointer (which may be eliminated) points to the stack pointer after
8453 the initial adjustments. */
8456 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
8458 rtx offset2 = const0_rtx;
8459 rtx reg = eliminate_constant_term (addr, &offset2);
8462 offset = INTVAL (offset2);
8464 if (reg == stack_pointer_rtx
8465 || reg == frame_pointer_rtx
8466 || reg == hard_frame_pointer_rtx)
8468 offset -= cfun->machine->frame.total_size;
8469 if (reg == hard_frame_pointer_rtx)
8470 offset += cfun->machine->frame.hard_frame_pointer_offset;
8476 /* Implement ASM_OUTPUT_EXTERNAL. */
8479 mips_output_external (FILE *file, tree decl, const char *name)
8481 default_elf_asm_output_external (file, decl, name);
8483 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
8484 set in order to avoid putting out names that are never really
8486 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
8488 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
8490 /* When using assembler macros, emit .extern directives for
8491 all small-data externs so that the assembler knows how
8494 In most cases it would be safe (though pointless) to emit
8495 .externs for other symbols too. One exception is when an
8496 object is within the -G limit but declared by the user to
8497 be in a section other than .sbss or .sdata. */
8498 fputs ("\t.extern\t", file);
8499 assemble_name (file, name);
8500 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n",
8501 int_size_in_bytes (TREE_TYPE (decl)));
8506 /* Implement TARGET_ASM_OUTPUT_SOURCE_FILENAME. */
8509 mips_output_filename (FILE *stream, const char *name)
8511 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
8513 if (write_symbols == DWARF2_DEBUG)
8515 else if (mips_output_filename_first_time)
8517 mips_output_filename_first_time = 0;
8518 num_source_filenames += 1;
8519 current_function_file = name;
8520 fprintf (stream, "\t.file\t%d ", num_source_filenames);
8521 output_quoted_string (stream, name);
8522 putc ('\n', stream);
8524 /* If we are emitting stabs, let dbxout.c handle this (except for
8525 the mips_output_filename_first_time case). */
8526 else if (write_symbols == DBX_DEBUG)
8528 else if (name != current_function_file
8529 && strcmp (name, current_function_file) != 0)
8531 num_source_filenames += 1;
8532 current_function_file = name;
8533 fprintf (stream, "\t.file\t%d ", num_source_filenames);
8534 output_quoted_string (stream, name);
8535 putc ('\n', stream);
8539 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
8541 static void ATTRIBUTE_UNUSED
8542 mips_output_dwarf_dtprel (FILE *file, int size, rtx x)
8547 fputs ("\t.dtprelword\t", file);
8551 fputs ("\t.dtpreldword\t", file);
8557 output_addr_const (file, x);
8558 fputs ("+0x8000", file);
8561 /* Implement TARGET_DWARF_REGISTER_SPAN. */
8564 mips_dwarf_register_span (rtx reg)
8567 enum machine_mode mode;
8569 /* By default, GCC maps increasing register numbers to increasing
8570 memory locations, but paired FPRs are always little-endian,
8571 regardless of the prevailing endianness. */
8572 mode = GET_MODE (reg);
8573 if (FP_REG_P (REGNO (reg))
8574 && TARGET_BIG_ENDIAN
8575 && MAX_FPRS_PER_FMT > 1
8576 && GET_MODE_SIZE (mode) > UNITS_PER_FPREG)
8578 gcc_assert (GET_MODE_SIZE (mode) == UNITS_PER_HWFPVALUE);
8579 high = mips_subword (reg, true);
8580 low = mips_subword (reg, false);
8581 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, high, low));
8587 /* DSP ALU can bypass data with no delays for the following pairs. */
8588 enum insn_code dspalu_bypass_table[][2] =
8590 {CODE_FOR_mips_addsc, CODE_FOR_mips_addwc},
8591 {CODE_FOR_mips_cmpu_eq_qb, CODE_FOR_mips_pick_qb},
8592 {CODE_FOR_mips_cmpu_lt_qb, CODE_FOR_mips_pick_qb},
8593 {CODE_FOR_mips_cmpu_le_qb, CODE_FOR_mips_pick_qb},
8594 {CODE_FOR_mips_cmp_eq_ph, CODE_FOR_mips_pick_ph},
8595 {CODE_FOR_mips_cmp_lt_ph, CODE_FOR_mips_pick_ph},
8596 {CODE_FOR_mips_cmp_le_ph, CODE_FOR_mips_pick_ph},
8597 {CODE_FOR_mips_wrdsp, CODE_FOR_mips_insv}
8601 mips_dspalu_bypass_p (rtx out_insn, rtx in_insn)
8604 int num_bypass = ARRAY_SIZE (dspalu_bypass_table);
8605 enum insn_code out_icode = (enum insn_code) INSN_CODE (out_insn);
8606 enum insn_code in_icode = (enum insn_code) INSN_CODE (in_insn);
8608 for (i = 0; i < num_bypass; i++)
8610 if (out_icode == dspalu_bypass_table[i][0]
8611 && in_icode == dspalu_bypass_table[i][1])
8617 /* Implement ASM_OUTPUT_ASCII. */
8620 mips_output_ascii (FILE *stream, const char *string, size_t len)
8626 fprintf (stream, "\t.ascii\t\"");
8627 for (i = 0; i < len; i++)
8631 c = (unsigned char) string[i];
8634 if (c == '\\' || c == '\"')
8636 putc ('\\', stream);
8644 fprintf (stream, "\\%03o", c);
8648 if (cur_pos > 72 && i+1 < len)
8651 fprintf (stream, "\"\n\t.ascii\t\"");
8654 fprintf (stream, "\"\n");
8657 /* Return the pseudo-op for full SYMBOL_(D)TPREL address *ADDR.
8658 Update *ADDR with the operand that should be printed. */
8661 mips_output_tls_reloc_directive (rtx *addr)
8663 enum mips_symbol_type type;
8665 type = mips_classify_symbolic_expression (*addr, SYMBOL_CONTEXT_LEA);
8666 *addr = mips_strip_unspec_address (*addr);
8670 return Pmode == SImode ? ".dtprelword\t%0" : ".dtpreldword\t%0";
8673 return Pmode == SImode ? ".tprelword\t%0" : ".tpreldword\t%0";
8680 /* Emit either a label, .comm, or .lcomm directive. When using assembler
8681 macros, mark the symbol as written so that mips_asm_output_external
8682 won't emit an .extern for it. STREAM is the output file, NAME is the
8683 name of the symbol, INIT_STRING is the string that should be written
8684 before the symbol and FINAL_STRING is the string that should be
8685 written after it. FINAL_STRING is a printf format that consumes the
8686 remaining arguments. */
8689 mips_declare_object (FILE *stream, const char *name, const char *init_string,
8690 const char *final_string, ...)
8694 fputs (init_string, stream);
8695 assemble_name (stream, name);
8696 va_start (ap, final_string);
8697 vfprintf (stream, final_string, ap);
8700 if (!TARGET_EXPLICIT_RELOCS)
8702 tree name_tree = get_identifier (name);
8703 TREE_ASM_WRITTEN (name_tree) = 1;
8707 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
8708 NAME is the name of the object and ALIGN is the required alignment
8709 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
8710 alignment argument. */
8713 mips_declare_common_object (FILE *stream, const char *name,
8714 const char *init_string,
8715 unsigned HOST_WIDE_INT size,
8716 unsigned int align, bool takes_alignment_p)
8718 if (!takes_alignment_p)
8720 size += (align / BITS_PER_UNIT) - 1;
8721 size -= size % (align / BITS_PER_UNIT);
8722 mips_declare_object (stream, name, init_string,
8723 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
8726 mips_declare_object (stream, name, init_string,
8727 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
8728 size, align / BITS_PER_UNIT);
8731 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
8732 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
8735 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
8736 unsigned HOST_WIDE_INT size,
8739 /* If the target wants uninitialized const declarations in
8740 .rdata then don't put them in .comm. */
8741 if (TARGET_EMBEDDED_DATA
8742 && TARGET_UNINIT_CONST_IN_RODATA
8743 && TREE_CODE (decl) == VAR_DECL
8744 && TREE_READONLY (decl)
8745 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
8747 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
8748 targetm.asm_out.globalize_label (stream, name);
8750 switch_to_section (readonly_data_section);
8751 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
8752 mips_declare_object (stream, name, "",
8753 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
8757 mips_declare_common_object (stream, name, "\n\t.comm\t",
8761 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8762 extern int size_directive_output;
8764 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
8765 definitions except that it uses mips_declare_object to emit the label. */
8768 mips_declare_object_name (FILE *stream, const char *name,
8769 tree decl ATTRIBUTE_UNUSED)
8771 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8772 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
8775 size_directive_output = 0;
8776 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
8780 size_directive_output = 1;
8781 size = int_size_in_bytes (TREE_TYPE (decl));
8782 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8785 mips_declare_object (stream, name, "", ":\n");
8788 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
8791 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
8795 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
8796 if (!flag_inhibit_size_directive
8797 && DECL_SIZE (decl) != 0
8800 && DECL_INITIAL (decl) == error_mark_node
8801 && !size_directive_output)
8805 size_directive_output = 1;
8806 size = int_size_in_bytes (TREE_TYPE (decl));
8807 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8812 /* Return the FOO in the name of the ".mdebug.FOO" section associated
8813 with the current ABI. */
8816 mips_mdebug_abi_name (void)
8829 return TARGET_64BIT ? "eabi64" : "eabi32";
8835 /* Implement TARGET_ASM_FILE_START. */
8838 mips_file_start (void)
8840 default_file_start ();
8842 /* Generate a special section to describe the ABI switches used to
8843 produce the resultant binary. */
8845 /* Record the ABI itself. Modern versions of binutils encode
8846 this information in the ELF header flags, but GDB needs the
8847 information in order to correctly debug binaries produced by
8848 older binutils. See the function mips_gdbarch_init in
8850 fprintf (asm_out_file, "\t.section .mdebug.%s\n\t.previous\n",
8851 mips_mdebug_abi_name ());
8853 /* There is no ELF header flag to distinguish long32 forms of the
8854 EABI from long64 forms. Emit a special section to help tools
8855 such as GDB. Do the same for o64, which is sometimes used with
8857 if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
8858 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n"
8859 "\t.previous\n", TARGET_LONG64 ? 64 : 32);
8861 /* Record the NaN encoding. */
8862 if (HAVE_AS_NAN || mips_nan != MIPS_IEEE_754_DEFAULT)
8863 fprintf (asm_out_file, "\t.nan\t%s\n",
8864 mips_nan == MIPS_IEEE_754_2008 ? "2008" : "legacy");
8866 #ifdef HAVE_AS_GNU_ATTRIBUTE
8870 /* No floating-point operations, -mno-float. */
8871 if (TARGET_NO_FLOAT)
8873 /* Soft-float code, -msoft-float. */
8874 else if (!TARGET_HARD_FLOAT_ABI)
8876 /* Single-float code, -msingle-float. */
8877 else if (!TARGET_DOUBLE_FLOAT)
8879 /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64. */
8880 else if (!TARGET_64BIT && TARGET_FLOAT64)
8882 /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */
8886 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n", attr);
8890 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
8891 if (TARGET_ABICALLS)
8893 fprintf (asm_out_file, "\t.abicalls\n");
8894 if (TARGET_ABICALLS_PIC0)
8895 fprintf (asm_out_file, "\t.option\tpic0\n");
8898 if (flag_verbose_asm)
8899 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
8901 mips_small_data_threshold, mips_arch_info->name, mips_isa);
8904 /* Implement TARGET_ASM_CODE_END. */
8907 mips_code_end (void)
8909 if (mips_need_mips16_rdhwr_p)
8910 mips_output_mips16_rdhwr ();
8913 /* Make the last instruction frame-related and note that it performs
8914 the operation described by FRAME_PATTERN. */
8917 mips_set_frame_expr (rtx frame_pattern)
8921 insn = get_last_insn ();
8922 RTX_FRAME_RELATED_P (insn) = 1;
8923 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
8928 /* Return a frame-related rtx that stores REG at MEM.
8929 REG must be a single register. */
8932 mips_frame_set (rtx mem, rtx reg)
8936 set = gen_rtx_SET (VOIDmode, mem, reg);
8937 RTX_FRAME_RELATED_P (set) = 1;
8942 /* Record that the epilogue has restored call-saved register REG. */
8945 mips_add_cfa_restore (rtx reg)
8947 mips_epilogue.cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg,
8948 mips_epilogue.cfa_restores);
8951 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
8952 mips16e_s2_s8_regs[X], it must also save the registers in indexes
8953 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
8954 static const unsigned char mips16e_s2_s8_regs[] = {
8955 30, 23, 22, 21, 20, 19, 18
8957 static const unsigned char mips16e_a0_a3_regs[] = {
8961 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
8962 ordered from the uppermost in memory to the lowest in memory. */
8963 static const unsigned char mips16e_save_restore_regs[] = {
8964 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
8967 /* Return the index of the lowest X in the range [0, SIZE) for which
8968 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
8971 mips16e_find_first_register (unsigned int mask, const unsigned char *regs,
8976 for (i = 0; i < size; i++)
8977 if (BITSET_P (mask, regs[i]))
8983 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
8984 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
8985 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
8986 is true for all indexes (X, SIZE). */
8989 mips16e_mask_registers (unsigned int *mask_ptr, const unsigned char *regs,
8990 unsigned int size, unsigned int *num_regs_ptr)
8994 i = mips16e_find_first_register (*mask_ptr, regs, size);
8995 for (i++; i < size; i++)
8996 if (!BITSET_P (*mask_ptr, regs[i]))
8999 *mask_ptr |= 1 << regs[i];
9003 /* Return a simplified form of X using the register values in REG_VALUES.
9004 REG_VALUES[R] is the last value assigned to hard register R, or null
9005 if R has not been modified.
9007 This function is rather limited, but is good enough for our purposes. */
9010 mips16e_collect_propagate_value (rtx x, rtx *reg_values)
9012 x = avoid_constant_pool_reference (x);
9016 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
9017 return simplify_gen_unary (GET_CODE (x), GET_MODE (x),
9018 x0, GET_MODE (XEXP (x, 0)));
9021 if (ARITHMETIC_P (x))
9023 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
9024 rtx x1 = mips16e_collect_propagate_value (XEXP (x, 1), reg_values);
9025 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), x0, x1);
9029 && reg_values[REGNO (x)]
9030 && !rtx_unstable_p (reg_values[REGNO (x)]))
9031 return reg_values[REGNO (x)];
9036 /* Return true if (set DEST SRC) stores an argument register into its
9037 caller-allocated save slot, storing the number of that argument
9038 register in *REGNO_PTR if so. REG_VALUES is as for
9039 mips16e_collect_propagate_value. */
9042 mips16e_collect_argument_save_p (rtx dest, rtx src, rtx *reg_values,
9043 unsigned int *regno_ptr)
9045 unsigned int argno, regno;
9046 HOST_WIDE_INT offset, required_offset;
9049 /* Check that this is a word-mode store. */
9050 if (!MEM_P (dest) || !REG_P (src) || GET_MODE (dest) != word_mode)
9053 /* Check that the register being saved is an unmodified argument
9055 regno = REGNO (src);
9056 if (!IN_RANGE (regno, GP_ARG_FIRST, GP_ARG_LAST) || reg_values[regno])
9058 argno = regno - GP_ARG_FIRST;
9060 /* Check whether the address is an appropriate stack-pointer or
9061 frame-pointer access. */
9062 addr = mips16e_collect_propagate_value (XEXP (dest, 0), reg_values);
9063 mips_split_plus (addr, &base, &offset);
9064 required_offset = cfun->machine->frame.total_size + argno * UNITS_PER_WORD;
9065 if (base == hard_frame_pointer_rtx)
9066 required_offset -= cfun->machine->frame.hard_frame_pointer_offset;
9067 else if (base != stack_pointer_rtx)
9069 if (offset != required_offset)
9076 /* A subroutine of mips_expand_prologue, called only when generating
9077 MIPS16e SAVE instructions. Search the start of the function for any
9078 instructions that save argument registers into their caller-allocated
9079 save slots. Delete such instructions and return a value N such that
9080 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
9081 instructions redundant. */
9084 mips16e_collect_argument_saves (void)
9086 rtx reg_values[FIRST_PSEUDO_REGISTER];
9087 rtx insn, next, set, dest, src;
9088 unsigned int nargs, regno;
9090 push_topmost_sequence ();
9092 memset (reg_values, 0, sizeof (reg_values));
9093 for (insn = get_insns (); insn; insn = next)
9095 next = NEXT_INSN (insn);
9096 if (NOTE_P (insn) || DEBUG_INSN_P (insn))
9102 set = PATTERN (insn);
9103 if (GET_CODE (set) != SET)
9106 dest = SET_DEST (set);
9107 src = SET_SRC (set);
9108 if (mips16e_collect_argument_save_p (dest, src, reg_values, ®no))
9110 if (!BITSET_P (cfun->machine->frame.mask, regno))
9113 nargs = MAX (nargs, (regno - GP_ARG_FIRST) + 1);
9116 else if (REG_P (dest) && GET_MODE (dest) == word_mode)
9117 reg_values[REGNO (dest)]
9118 = mips16e_collect_propagate_value (src, reg_values);
9122 pop_topmost_sequence ();
9127 /* Return a move between register REGNO and memory location SP + OFFSET.
9128 REG_PARM_P is true if SP + OFFSET belongs to REG_PARM_STACK_SPACE.
9129 Make the move a load if RESTORE_P, otherwise make it a store. */
9132 mips16e_save_restore_reg (bool restore_p, bool reg_parm_p,
9133 HOST_WIDE_INT offset, unsigned int regno)
9137 mem = gen_frame_mem (SImode, plus_constant (Pmode, stack_pointer_rtx,
9139 reg = gen_rtx_REG (SImode, regno);
9142 mips_add_cfa_restore (reg);
9143 return gen_rtx_SET (VOIDmode, reg, mem);
9146 return gen_rtx_SET (VOIDmode, mem, reg);
9147 return mips_frame_set (mem, reg);
9150 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
9151 The instruction must:
9153 - Allocate or deallocate SIZE bytes in total; SIZE is known
9156 - Save or restore as many registers in *MASK_PTR as possible.
9157 The instruction saves the first registers at the top of the
9158 allocated area, with the other registers below it.
9160 - Save NARGS argument registers above the allocated area.
9162 (NARGS is always zero if RESTORE_P.)
9164 The SAVE and RESTORE instructions cannot save and restore all general
9165 registers, so there may be some registers left over for the caller to
9166 handle. Destructively modify *MASK_PTR so that it contains the registers
9167 that still need to be saved or restored. The caller can save these
9168 registers in the memory immediately below *OFFSET_PTR, which is a
9169 byte offset from the bottom of the allocated stack area. */
9172 mips16e_build_save_restore (bool restore_p, unsigned int *mask_ptr,
9173 HOST_WIDE_INT *offset_ptr, unsigned int nargs,
9177 HOST_WIDE_INT offset, top_offset;
9178 unsigned int i, regno;
9181 gcc_assert (cfun->machine->frame.num_fp == 0);
9183 /* Calculate the number of elements in the PARALLEL. We need one element
9184 for the stack adjustment, one for each argument register save, and one
9185 for each additional register move. */
9187 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
9188 if (BITSET_P (*mask_ptr, mips16e_save_restore_regs[i]))
9191 /* Create the final PARALLEL. */
9192 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (n));
9195 /* Add the stack pointer adjustment. */
9196 set = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
9197 plus_constant (Pmode, stack_pointer_rtx,
9198 restore_p ? size : -size));
9199 RTX_FRAME_RELATED_P (set) = 1;
9200 XVECEXP (pattern, 0, n++) = set;
9202 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
9203 top_offset = restore_p ? size : 0;
9205 /* Save the arguments. */
9206 for (i = 0; i < nargs; i++)
9208 offset = top_offset + i * UNITS_PER_WORD;
9209 set = mips16e_save_restore_reg (restore_p, true, offset,
9211 XVECEXP (pattern, 0, n++) = set;
9214 /* Then fill in the other register moves. */
9215 offset = top_offset;
9216 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
9218 regno = mips16e_save_restore_regs[i];
9219 if (BITSET_P (*mask_ptr, regno))
9221 offset -= UNITS_PER_WORD;
9222 set = mips16e_save_restore_reg (restore_p, false, offset, regno);
9223 XVECEXP (pattern, 0, n++) = set;
9224 *mask_ptr &= ~(1 << regno);
9228 /* Tell the caller what offset it should use for the remaining registers. */
9229 *offset_ptr = size + (offset - top_offset);
9231 gcc_assert (n == XVECLEN (pattern, 0));
9236 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
9237 pointer. Return true if PATTERN matches the kind of instruction
9238 generated by mips16e_build_save_restore. If INFO is nonnull,
9239 initialize it when returning true. */
9242 mips16e_save_restore_pattern_p (rtx pattern, HOST_WIDE_INT adjust,
9243 struct mips16e_save_restore_info *info)
9245 unsigned int i, nargs, mask, extra;
9246 HOST_WIDE_INT top_offset, save_offset, offset;
9247 rtx set, reg, mem, base;
9250 if (!GENERATE_MIPS16E_SAVE_RESTORE)
9253 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
9254 top_offset = adjust > 0 ? adjust : 0;
9256 /* Interpret all other members of the PARALLEL. */
9257 save_offset = top_offset - UNITS_PER_WORD;
9261 for (n = 1; n < XVECLEN (pattern, 0); n++)
9263 /* Check that we have a SET. */
9264 set = XVECEXP (pattern, 0, n);
9265 if (GET_CODE (set) != SET)
9268 /* Check that the SET is a load (if restoring) or a store
9270 mem = adjust > 0 ? SET_SRC (set) : SET_DEST (set);
9274 /* Check that the address is the sum of the stack pointer and a
9275 possibly-zero constant offset. */
9276 mips_split_plus (XEXP (mem, 0), &base, &offset);
9277 if (base != stack_pointer_rtx)
9280 /* Check that SET's other operand is a register. */
9281 reg = adjust > 0 ? SET_DEST (set) : SET_SRC (set);
9285 /* Check for argument saves. */
9286 if (offset == top_offset + nargs * UNITS_PER_WORD
9287 && REGNO (reg) == GP_ARG_FIRST + nargs)
9289 else if (offset == save_offset)
9291 while (mips16e_save_restore_regs[i++] != REGNO (reg))
9292 if (i == ARRAY_SIZE (mips16e_save_restore_regs))
9295 mask |= 1 << REGNO (reg);
9296 save_offset -= UNITS_PER_WORD;
9302 /* Check that the restrictions on register ranges are met. */
9304 mips16e_mask_registers (&mask, mips16e_s2_s8_regs,
9305 ARRAY_SIZE (mips16e_s2_s8_regs), &extra);
9306 mips16e_mask_registers (&mask, mips16e_a0_a3_regs,
9307 ARRAY_SIZE (mips16e_a0_a3_regs), &extra);
9311 /* Make sure that the topmost argument register is not saved twice.
9312 The checks above ensure that the same is then true for the other
9313 argument registers. */
9314 if (nargs > 0 && BITSET_P (mask, GP_ARG_FIRST + nargs - 1))
9317 /* Pass back information, if requested. */
9320 info->nargs = nargs;
9322 info->size = (adjust > 0 ? adjust : -adjust);
9328 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
9329 for the register range [MIN_REG, MAX_REG]. Return a pointer to
9330 the null terminator. */
9333 mips16e_add_register_range (char *s, unsigned int min_reg,
9334 unsigned int max_reg)
9336 if (min_reg != max_reg)
9337 s += sprintf (s, ",%s-%s", reg_names[min_reg], reg_names[max_reg]);
9339 s += sprintf (s, ",%s", reg_names[min_reg]);
9343 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
9344 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
9347 mips16e_output_save_restore (rtx pattern, HOST_WIDE_INT adjust)
9349 static char buffer[300];
9351 struct mips16e_save_restore_info info;
9352 unsigned int i, end;
9355 /* Parse the pattern. */
9356 if (!mips16e_save_restore_pattern_p (pattern, adjust, &info))
9359 /* Add the mnemonic. */
9360 s = strcpy (buffer, adjust > 0 ? "restore\t" : "save\t");
9363 /* Save the arguments. */
9365 s += sprintf (s, "%s-%s,", reg_names[GP_ARG_FIRST],
9366 reg_names[GP_ARG_FIRST + info.nargs - 1]);
9367 else if (info.nargs == 1)
9368 s += sprintf (s, "%s,", reg_names[GP_ARG_FIRST]);
9370 /* Emit the amount of stack space to allocate or deallocate. */
9371 s += sprintf (s, "%d", (int) info.size);
9373 /* Save or restore $16. */
9374 if (BITSET_P (info.mask, 16))
9375 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 16]);
9377 /* Save or restore $17. */
9378 if (BITSET_P (info.mask, 17))
9379 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 17]);
9381 /* Save or restore registers in the range $s2...$s8, which
9382 mips16e_s2_s8_regs lists in decreasing order. Note that this
9383 is a software register range; the hardware registers are not
9384 numbered consecutively. */
9385 end = ARRAY_SIZE (mips16e_s2_s8_regs);
9386 i = mips16e_find_first_register (info.mask, mips16e_s2_s8_regs, end);
9388 s = mips16e_add_register_range (s, mips16e_s2_s8_regs[end - 1],
9389 mips16e_s2_s8_regs[i]);
9391 /* Save or restore registers in the range $a0...$a3. */
9392 end = ARRAY_SIZE (mips16e_a0_a3_regs);
9393 i = mips16e_find_first_register (info.mask, mips16e_a0_a3_regs, end);
9395 s = mips16e_add_register_range (s, mips16e_a0_a3_regs[i],
9396 mips16e_a0_a3_regs[end - 1]);
9398 /* Save or restore $31. */
9399 if (BITSET_P (info.mask, RETURN_ADDR_REGNUM))
9400 s += sprintf (s, ",%s", reg_names[RETURN_ADDR_REGNUM]);
9405 /* Return true if the current function returns its value in a floating-point
9406 register in MIPS16 mode. */
9409 mips16_cfun_returns_in_fpr_p (void)
9411 tree return_type = DECL_RESULT (current_function_decl);
9412 return (TARGET_MIPS16
9413 && TARGET_HARD_FLOAT_ABI
9414 && !aggregate_value_p (return_type, current_function_decl)
9415 && mips_return_mode_in_fpr_p (DECL_MODE (return_type)));
9418 /* Return true if predicate PRED is true for at least one instruction.
9419 Cache the result in *CACHE, and assume that the result is true
9420 if *CACHE is already true. */
9423 mips_find_gp_ref (bool *cache, bool (*pred) (rtx))
9429 push_topmost_sequence ();
9430 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9431 if (USEFUL_INSN_P (insn) && pred (insn))
9436 pop_topmost_sequence ();
9441 /* Return true if INSN refers to the global pointer in an "inflexible" way.
9442 See mips_cfun_has_inflexible_gp_ref_p for details. */
9445 mips_insn_has_inflexible_gp_ref_p (rtx insn)
9447 /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE
9448 indicate that the target could be a traditional MIPS
9449 lazily-binding stub. */
9450 return find_reg_fusage (insn, USE, pic_offset_table_rtx);
9453 /* Return true if the current function refers to the global pointer
9454 in a way that forces $28 to be valid. This means that we can't
9455 change the choice of global pointer, even for NewABI code.
9457 One example of this (and one which needs several checks) is that
9458 $28 must be valid when calling traditional MIPS lazy-binding stubs.
9459 (This restriction does not apply to PLTs.) */
9462 mips_cfun_has_inflexible_gp_ref_p (void)
9464 /* If the function has a nonlocal goto, $28 must hold the correct
9465 global pointer for the target function. That is, the target
9466 of the goto implicitly uses $28. */
9467 if (crtl->has_nonlocal_goto)
9470 if (TARGET_ABICALLS_PIC2)
9472 /* Symbolic accesses implicitly use the global pointer unless
9473 -mexplicit-relocs is in effect. JAL macros to symbolic addresses
9474 might go to traditional MIPS lazy-binding stubs. */
9475 if (!TARGET_EXPLICIT_RELOCS)
9478 /* FUNCTION_PROFILER includes a JAL to _mcount, which again
9479 can be lazily-bound. */
9483 /* MIPS16 functions that return in FPRs need to call an
9484 external libgcc routine. This call is only made explict
9485 during mips_expand_epilogue, and it too might be lazily bound. */
9486 if (mips16_cfun_returns_in_fpr_p ())
9490 return mips_find_gp_ref (&cfun->machine->has_inflexible_gp_insn_p,
9491 mips_insn_has_inflexible_gp_ref_p);
9494 /* Return true if INSN refers to the global pointer in a "flexible" way.
9495 See mips_cfun_has_flexible_gp_ref_p for details. */
9498 mips_insn_has_flexible_gp_ref_p (rtx insn)
9500 return (get_attr_got (insn) != GOT_UNSET
9501 || mips_small_data_pattern_p (PATTERN (insn))
9502 || reg_overlap_mentioned_p (pic_offset_table_rtx, PATTERN (insn)));
9505 /* Return true if the current function references the global pointer,
9506 but if those references do not inherently require the global pointer
9507 to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */
9510 mips_cfun_has_flexible_gp_ref_p (void)
9512 /* Reload can sometimes introduce constant pool references
9513 into a function that otherwise didn't need them. For example,
9514 suppose we have an instruction like:
9516 (set (reg:DF R1) (float:DF (reg:SI R2)))
9518 If R2 turns out to be a constant such as 1, the instruction may
9519 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
9520 the option of using this constant if R2 doesn't get allocated
9523 In cases like these, reload will have added the constant to the
9524 pool but no instruction will yet refer to it. */
9525 if (TARGET_ABICALLS_PIC2 && !reload_completed && crtl->uses_const_pool)
9528 return mips_find_gp_ref (&cfun->machine->has_flexible_gp_insn_p,
9529 mips_insn_has_flexible_gp_ref_p);
9532 /* Return the register that should be used as the global pointer
9533 within this function. Return INVALID_REGNUM if the function
9534 doesn't need a global pointer. */
9537 mips_global_pointer (void)
9541 /* $gp is always available unless we're using a GOT. */
9542 if (!TARGET_USE_GOT)
9543 return GLOBAL_POINTER_REGNUM;
9545 /* If there are inflexible references to $gp, we must use the
9546 standard register. */
9547 if (mips_cfun_has_inflexible_gp_ref_p ())
9548 return GLOBAL_POINTER_REGNUM;
9550 /* If there are no current references to $gp, then the only uses
9551 we can introduce later are those involved in long branches. */
9552 if (TARGET_ABSOLUTE_JUMPS && !mips_cfun_has_flexible_gp_ref_p ())
9553 return INVALID_REGNUM;
9555 /* If the global pointer is call-saved, try to use a call-clobbered
9557 if (TARGET_CALL_SAVED_GP && crtl->is_leaf)
9558 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
9559 if (!df_regs_ever_live_p (regno)
9560 && call_really_used_regs[regno]
9561 && !fixed_regs[regno]
9562 && regno != PIC_FUNCTION_ADDR_REGNUM)
9565 return GLOBAL_POINTER_REGNUM;
9568 /* Return true if the current function's prologue must load the global
9569 pointer value into pic_offset_table_rtx and store the same value in
9570 the function's cprestore slot (if any).
9572 One problem we have to deal with is that, when emitting GOT-based
9573 position independent code, long-branch sequences will need to load
9574 the address of the branch target from the GOT. We don't know until
9575 the very end of compilation whether (and where) the function needs
9576 long branches, so we must ensure that _any_ branch can access the
9577 global pointer in some form. However, we do not want to pessimize
9578 the usual case in which all branches are short.
9580 We handle this as follows:
9582 (1) During reload, we set cfun->machine->global_pointer to
9583 INVALID_REGNUM if we _know_ that the current function
9584 doesn't need a global pointer. This is only valid if
9585 long branches don't need the GOT.
9587 Otherwise, we assume that we might need a global pointer
9588 and pick an appropriate register.
9590 (2) If cfun->machine->global_pointer != INVALID_REGNUM,
9591 we ensure that the global pointer is available at every
9592 block boundary bar entry and exit. We do this in one of two ways:
9594 - If the function has a cprestore slot, we ensure that this
9595 slot is valid at every branch. However, as explained in
9596 point (6) below, there is no guarantee that pic_offset_table_rtx
9597 itself is valid if new uses of the global pointer are introduced
9598 after the first post-epilogue split.
9600 We guarantee that the cprestore slot is valid by loading it
9601 into a fake register, CPRESTORE_SLOT_REGNUM. We then make
9602 this register live at every block boundary bar function entry
9603 and exit. It is then invalid to move the load (and thus the
9604 preceding store) across a block boundary.
9606 - If the function has no cprestore slot, we guarantee that
9607 pic_offset_table_rtx itself is valid at every branch.
9609 See mips_eh_uses for the handling of the register liveness.
9611 (3) During prologue and epilogue generation, we emit "ghost"
9612 placeholder instructions to manipulate the global pointer.
9614 (4) During prologue generation, we set cfun->machine->must_initialize_gp_p
9615 and cfun->machine->must_restore_gp_when_clobbered_p if we already know
9616 that the function needs a global pointer. (There is no need to set
9617 them earlier than this, and doing it as late as possible leads to
9618 fewer false positives.)
9620 (5) If cfun->machine->must_initialize_gp_p is true during a
9621 split_insns pass, we split the ghost instructions into real
9622 instructions. These split instructions can then be optimized in
9623 the usual way. Otherwise, we keep the ghost instructions intact,
9624 and optimize for the case where they aren't needed. We still
9625 have the option of splitting them later, if we need to introduce
9626 new uses of the global pointer.
9628 For example, the scheduler ignores a ghost instruction that
9629 stores $28 to the stack, but it handles the split form of
9630 the ghost instruction as an ordinary store.
9632 (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p
9633 is true during the first post-epilogue split_insns pass, we split
9634 calls and restore_gp patterns into instructions that explicitly
9635 load pic_offset_table_rtx from the cprestore slot. Otherwise,
9636 we split these patterns into instructions that _don't_ load from
9639 If cfun->machine->must_restore_gp_when_clobbered_p is true at the
9640 time of the split, then any instructions that exist at that time
9641 can make free use of pic_offset_table_rtx. However, if we want
9642 to introduce new uses of the global pointer after the split,
9643 we must explicitly load the value from the cprestore slot, since
9644 pic_offset_table_rtx itself might not be valid at a given point
9647 The idea is that we want to be able to delete redundant
9648 loads from the cprestore slot in the usual case where no
9649 long branches are needed.
9651 (7) If cfun->machine->must_initialize_gp_p is still false at the end
9652 of md_reorg, we decide whether the global pointer is needed for
9653 long branches. If so, we set cfun->machine->must_initialize_gp_p
9654 to true and split the ghost instructions into real instructions
9657 Note that the ghost instructions must have a zero length for three reasons:
9659 - Giving the length of the underlying $gp sequence might cause
9660 us to use long branches in cases where they aren't really needed.
9662 - They would perturb things like alignment calculations.
9664 - More importantly, the hazard detection in md_reorg relies on
9665 empty instructions having a zero length.
9667 If we find a long branch and split the ghost instructions at the
9668 end of md_reorg, the split could introduce more long branches.
9669 That isn't a problem though, because we still do the split before
9670 the final shorten_branches pass.
9672 This is extremely ugly, but it seems like the best compromise between
9673 correctness and efficiency. */
9676 mips_must_initialize_gp_p (void)
9678 return cfun->machine->must_initialize_gp_p;
9681 /* Return true if REGNO is a register that is ordinarily call-clobbered
9682 but must nevertheless be preserved by an interrupt handler. */
9685 mips_interrupt_extra_call_saved_reg_p (unsigned int regno)
9687 if (MD_REG_P (regno))
9690 if (TARGET_DSP && DSP_ACC_REG_P (regno))
9693 if (GP_REG_P (regno) && !cfun->machine->use_shadow_register_set_p)
9695 /* $0 is hard-wired. */
9696 if (regno == GP_REG_FIRST)
9699 /* The interrupt handler can treat kernel registers as
9700 scratch registers. */
9701 if (KERNEL_REG_P (regno))
9704 /* The function will return the stack pointer to its original value
9706 if (regno == STACK_POINTER_REGNUM)
9709 /* Otherwise, return true for registers that aren't ordinarily
9711 return call_really_used_regs[regno];
9717 /* Return true if the current function should treat register REGNO
9721 mips_cfun_call_saved_reg_p (unsigned int regno)
9723 /* If the user makes an ordinarily-call-saved register global,
9724 that register is no longer call-saved. */
9725 if (global_regs[regno])
9728 /* Interrupt handlers need to save extra registers. */
9729 if (cfun->machine->interrupt_handler_p
9730 && mips_interrupt_extra_call_saved_reg_p (regno))
9733 /* call_insns preserve $28 unless they explicitly say otherwise,
9734 so call_really_used_regs[] treats $28 as call-saved. However,
9735 we want the ABI property rather than the default call_insn
9737 return (regno == GLOBAL_POINTER_REGNUM
9738 ? TARGET_CALL_SAVED_GP
9739 : !call_really_used_regs[regno]);
9742 /* Return true if the function body might clobber register REGNO.
9743 We know that REGNO is call-saved. */
9746 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno)
9748 /* Some functions should be treated as clobbering all call-saved
9750 if (crtl->saves_all_registers)
9753 /* DF handles cases where a register is explicitly referenced in
9754 the rtl. Incoming values are passed in call-clobbered registers,
9755 so we can assume that any live call-saved register is set within
9757 if (df_regs_ever_live_p (regno))
9760 /* Check for registers that are clobbered by FUNCTION_PROFILER.
9761 These clobbers are not explicit in the rtl. */
9762 if (crtl->profile && MIPS_SAVE_REG_FOR_PROFILING_P (regno))
9765 /* If we're using a call-saved global pointer, the function's
9766 prologue will need to set it up. */
9767 if (cfun->machine->global_pointer == regno)
9770 /* The function's prologue will need to set the frame pointer if
9771 frame_pointer_needed. */
9772 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
9775 /* If a MIPS16 function returns a value in FPRs, its epilogue
9776 will need to call an external libgcc routine. This yet-to-be
9777 generated call_insn will clobber $31. */
9778 if (regno == RETURN_ADDR_REGNUM && mips16_cfun_returns_in_fpr_p ())
9781 /* If REGNO is ordinarily call-clobbered, we must assume that any
9782 called function could modify it. */
9783 if (cfun->machine->interrupt_handler_p
9785 && mips_interrupt_extra_call_saved_reg_p (regno))
9791 /* Return true if the current function must save register REGNO. */
9794 mips_save_reg_p (unsigned int regno)
9796 if (mips_cfun_call_saved_reg_p (regno))
9798 if (mips_cfun_might_clobber_call_saved_reg_p (regno))
9801 /* Save both registers in an FPR pair if either one is used. This is
9802 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
9803 register to be used without the even register. */
9804 if (FP_REG_P (regno)
9805 && MAX_FPRS_PER_FMT == 2
9806 && mips_cfun_might_clobber_call_saved_reg_p (regno + 1))
9810 /* We need to save the incoming return address if __builtin_eh_return
9811 is being used to set a different return address. */
9812 if (regno == RETURN_ADDR_REGNUM && crtl->calls_eh_return)
9818 /* Populate the current function's mips_frame_info structure.
9820 MIPS stack frames look like:
9822 +-------------------------------+
9824 | incoming stack arguments |
9826 +-------------------------------+
9828 | caller-allocated save area |
9829 A | for register arguments |
9831 +-------------------------------+ <-- incoming stack pointer
9833 | callee-allocated save area |
9834 B | for arguments that are |
9835 | split between registers and |
9838 +-------------------------------+ <-- arg_pointer_rtx
9840 C | callee-allocated save area |
9841 | for register varargs |
9843 +-------------------------------+ <-- frame_pointer_rtx
9844 | | + cop0_sp_offset
9845 | COP0 reg save area | + UNITS_PER_WORD
9847 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
9848 | | + UNITS_PER_WORD
9849 | accumulator save area |
9851 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
9852 | | + UNITS_PER_HWFPVALUE
9855 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset
9856 | | + UNITS_PER_WORD
9859 +-------------------------------+ <-- frame_pointer_rtx with
9860 | | \ -fstack-protector
9861 | local variables | | var_size
9863 +-------------------------------+
9865 | $gp save area | | cprestore_size
9867 P +-------------------------------+ <-- hard_frame_pointer_rtx for
9869 | outgoing stack arguments | |
9871 +-------------------------------+ | args_size
9873 | caller-allocated save area | |
9874 | for register arguments | |
9876 +-------------------------------+ <-- stack_pointer_rtx
9877 frame_pointer_rtx without
9879 hard_frame_pointer_rtx for
9882 At least two of A, B and C will be empty.
9884 Dynamic stack allocations such as alloca insert data at point P.
9885 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
9886 hard_frame_pointer_rtx unchanged. */
9889 mips_compute_frame_info (void)
9891 struct mips_frame_info *frame;
9892 HOST_WIDE_INT offset, size;
9893 unsigned int regno, i;
9895 /* Set this function's interrupt properties. */
9896 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
9899 error ("the %<interrupt%> attribute requires a MIPS32r2 processor");
9900 else if (TARGET_HARD_FLOAT)
9901 error ("the %<interrupt%> attribute requires %<-msoft-float%>");
9902 else if (TARGET_MIPS16)
9903 error ("interrupt handlers cannot be MIPS16 functions");
9906 cfun->machine->interrupt_handler_p = true;
9907 cfun->machine->use_shadow_register_set_p =
9908 mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl));
9909 cfun->machine->keep_interrupts_masked_p =
9910 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl));
9911 cfun->machine->use_debug_exception_return_p =
9912 mips_use_debug_exception_return_p (TREE_TYPE
9913 (current_function_decl));
9917 frame = &cfun->machine->frame;
9918 memset (frame, 0, sizeof (*frame));
9919 size = get_frame_size ();
9921 cfun->machine->global_pointer = mips_global_pointer ();
9923 /* The first two blocks contain the outgoing argument area and the $gp save
9924 slot. This area isn't needed in leaf functions, but if the
9925 target-independent frame size is nonzero, we have already committed to
9926 allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */
9927 if ((size == 0 || FRAME_GROWS_DOWNWARD) && crtl->is_leaf)
9929 /* The MIPS 3.0 linker does not like functions that dynamically
9930 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
9931 looks like we are trying to create a second frame pointer to the
9932 function, so allocate some stack space to make it happy. */
9933 if (cfun->calls_alloca)
9934 frame->args_size = REG_PARM_STACK_SPACE (cfun->decl);
9936 frame->args_size = 0;
9937 frame->cprestore_size = 0;
9941 frame->args_size = crtl->outgoing_args_size;
9942 frame->cprestore_size = MIPS_GP_SAVE_AREA_SIZE;
9944 offset = frame->args_size + frame->cprestore_size;
9946 /* Move above the local variables. */
9947 frame->var_size = MIPS_STACK_ALIGN (size);
9948 offset += frame->var_size;
9950 /* Find out which GPRs we need to save. */
9951 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
9952 if (mips_save_reg_p (regno))
9955 frame->mask |= 1 << (regno - GP_REG_FIRST);
9958 /* If this function calls eh_return, we must also save and restore the
9959 EH data registers. */
9960 if (crtl->calls_eh_return)
9961 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; i++)
9964 frame->mask |= 1 << (EH_RETURN_DATA_REGNO (i) - GP_REG_FIRST);
9967 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
9968 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
9969 save all later registers too. */
9970 if (GENERATE_MIPS16E_SAVE_RESTORE)
9972 mips16e_mask_registers (&frame->mask, mips16e_s2_s8_regs,
9973 ARRAY_SIZE (mips16e_s2_s8_regs), &frame->num_gp);
9974 mips16e_mask_registers (&frame->mask, mips16e_a0_a3_regs,
9975 ARRAY_SIZE (mips16e_a0_a3_regs), &frame->num_gp);
9978 /* Move above the GPR save area. */
9979 if (frame->num_gp > 0)
9981 offset += MIPS_STACK_ALIGN (frame->num_gp * UNITS_PER_WORD);
9982 frame->gp_sp_offset = offset - UNITS_PER_WORD;
9985 /* Find out which FPRs we need to save. This loop must iterate over
9986 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
9987 if (TARGET_HARD_FLOAT)
9988 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += MAX_FPRS_PER_FMT)
9989 if (mips_save_reg_p (regno))
9991 frame->num_fp += MAX_FPRS_PER_FMT;
9992 frame->fmask |= ~(~0 << MAX_FPRS_PER_FMT) << (regno - FP_REG_FIRST);
9995 /* Move above the FPR save area. */
9996 if (frame->num_fp > 0)
9998 offset += MIPS_STACK_ALIGN (frame->num_fp * UNITS_PER_FPREG);
9999 frame->fp_sp_offset = offset - UNITS_PER_HWFPVALUE;
10002 /* Add in space for the interrupt context information. */
10003 if (cfun->machine->interrupt_handler_p)
10006 if (mips_save_reg_p (LO_REGNUM) || mips_save_reg_p (HI_REGNUM))
10009 frame->acc_mask |= (1 << 0);
10012 /* Check accumulators 1, 2, 3. */
10013 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
10014 if (mips_save_reg_p (i) || mips_save_reg_p (i + 1))
10017 frame->acc_mask |= 1 << (((i - DSP_ACC_REG_FIRST) / 2) + 1);
10020 /* All interrupt context functions need space to preserve STATUS. */
10021 frame->num_cop0_regs++;
10023 /* If we don't keep interrupts masked, we need to save EPC. */
10024 if (!cfun->machine->keep_interrupts_masked_p)
10025 frame->num_cop0_regs++;
10028 /* Move above the accumulator save area. */
10029 if (frame->num_acc > 0)
10031 /* Each accumulator needs 2 words. */
10032 offset += frame->num_acc * 2 * UNITS_PER_WORD;
10033 frame->acc_sp_offset = offset - UNITS_PER_WORD;
10036 /* Move above the COP0 register save area. */
10037 if (frame->num_cop0_regs > 0)
10039 offset += frame->num_cop0_regs * UNITS_PER_WORD;
10040 frame->cop0_sp_offset = offset - UNITS_PER_WORD;
10043 /* Move above the callee-allocated varargs save area. */
10044 offset += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
10045 frame->arg_pointer_offset = offset;
10047 /* Move above the callee-allocated area for pretend stack arguments. */
10048 offset += crtl->args.pretend_args_size;
10049 frame->total_size = offset;
10051 /* Work out the offsets of the save areas from the top of the frame. */
10052 if (frame->gp_sp_offset > 0)
10053 frame->gp_save_offset = frame->gp_sp_offset - offset;
10054 if (frame->fp_sp_offset > 0)
10055 frame->fp_save_offset = frame->fp_sp_offset - offset;
10056 if (frame->acc_sp_offset > 0)
10057 frame->acc_save_offset = frame->acc_sp_offset - offset;
10058 if (frame->num_cop0_regs > 0)
10059 frame->cop0_save_offset = frame->cop0_sp_offset - offset;
10061 /* MIPS16 code offsets the frame pointer by the size of the outgoing
10062 arguments. This tends to increase the chances of using unextended
10063 instructions for local variables and incoming arguments. */
10065 frame->hard_frame_pointer_offset = frame->args_size;
10068 /* Return the style of GP load sequence that is being used for the
10069 current function. */
10071 enum mips_loadgp_style
10072 mips_current_loadgp_style (void)
10074 if (!TARGET_USE_GOT || cfun->machine->global_pointer == INVALID_REGNUM)
10075 return LOADGP_NONE;
10077 if (TARGET_RTP_PIC)
10080 if (TARGET_ABSOLUTE_ABICALLS)
10081 return LOADGP_ABSOLUTE;
10083 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
10086 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
10089 mips_frame_pointer_required (void)
10091 /* If the function contains dynamic stack allocations, we need to
10092 use the frame pointer to access the static parts of the frame. */
10093 if (cfun->calls_alloca)
10096 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
10097 reload may be unable to compute the address of a local variable,
10098 since there is no way to add a large constant to the stack pointer
10099 without using a second temporary register. */
10102 mips_compute_frame_info ();
10103 if (!SMALL_OPERAND (cfun->machine->frame.total_size))
10110 /* Make sure that we're not trying to eliminate to the wrong hard frame
10114 mips_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
10116 return (to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM);
10119 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
10120 or argument pointer. TO is either the stack pointer or hard frame
10124 mips_initial_elimination_offset (int from, int to)
10126 HOST_WIDE_INT offset;
10128 mips_compute_frame_info ();
10130 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */
10133 case FRAME_POINTER_REGNUM:
10134 if (FRAME_GROWS_DOWNWARD)
10135 offset = (cfun->machine->frame.args_size
10136 + cfun->machine->frame.cprestore_size
10137 + cfun->machine->frame.var_size);
10142 case ARG_POINTER_REGNUM:
10143 offset = cfun->machine->frame.arg_pointer_offset;
10147 gcc_unreachable ();
10150 if (to == HARD_FRAME_POINTER_REGNUM)
10151 offset -= cfun->machine->frame.hard_frame_pointer_offset;
10156 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
10159 mips_extra_live_on_entry (bitmap regs)
10161 if (TARGET_USE_GOT)
10163 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
10164 the global pointer. */
10165 if (!TARGET_ABSOLUTE_ABICALLS)
10166 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
10168 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
10169 the global pointer. */
10171 bitmap_set_bit (regs, MIPS16_PIC_TEMP_REGNUM);
10173 /* See the comment above load_call<mode> for details. */
10174 bitmap_set_bit (regs, GOT_VERSION_REGNUM);
10178 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
10182 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
10187 return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);
10190 /* Emit code to change the current function's return address to
10191 ADDRESS. SCRATCH is available as a scratch register, if needed.
10192 ADDRESS and SCRATCH are both word-mode GPRs. */
10195 mips_set_return_address (rtx address, rtx scratch)
10199 gcc_assert (BITSET_P (cfun->machine->frame.mask, RETURN_ADDR_REGNUM));
10200 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
10201 cfun->machine->frame.gp_sp_offset);
10202 mips_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address);
10205 /* Return true if the current function has a cprestore slot. */
10208 mips_cfun_has_cprestore_slot_p (void)
10210 return (cfun->machine->global_pointer != INVALID_REGNUM
10211 && cfun->machine->frame.cprestore_size > 0);
10214 /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the
10215 cprestore slot. LOAD_P is true if the caller wants to load from
10216 the cprestore slot; it is false if the caller wants to store to
10220 mips_get_cprestore_base_and_offset (rtx *base, HOST_WIDE_INT *offset,
10223 const struct mips_frame_info *frame;
10225 frame = &cfun->machine->frame;
10226 /* .cprestore always uses the stack pointer instead of the frame pointer.
10227 We have a free choice for direct stores for non-MIPS16 functions,
10228 and for MIPS16 functions whose cprestore slot is in range of the
10229 stack pointer. Using the stack pointer would sometimes give more
10230 (early) scheduling freedom, but using the frame pointer would
10231 sometimes give more (late) scheduling freedom. It's hard to
10232 predict which applies to a given function, so let's keep things
10235 Loads must always use the frame pointer in functions that call
10236 alloca, and there's little benefit to using the stack pointer
10238 if (frame_pointer_needed && !(TARGET_CPRESTORE_DIRECTIVE && !load_p))
10240 *base = hard_frame_pointer_rtx;
10241 *offset = frame->args_size - frame->hard_frame_pointer_offset;
10245 *base = stack_pointer_rtx;
10246 *offset = frame->args_size;
10250 /* Return true if X is the load or store address of the cprestore slot;
10251 LOAD_P says which. */
10254 mips_cprestore_address_p (rtx x, bool load_p)
10256 rtx given_base, required_base;
10257 HOST_WIDE_INT given_offset, required_offset;
10259 mips_split_plus (x, &given_base, &given_offset);
10260 mips_get_cprestore_base_and_offset (&required_base, &required_offset, load_p);
10261 return given_base == required_base && given_offset == required_offset;
10264 /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are
10265 going to load from it, false if we are going to store to it.
10266 Use TEMP as a temporary register if need be. */
10269 mips_cprestore_slot (rtx temp, bool load_p)
10272 HOST_WIDE_INT offset;
10274 mips_get_cprestore_base_and_offset (&base, &offset, load_p);
10275 return gen_frame_mem (Pmode, mips_add_offset (temp, base, offset));
10278 /* Emit instructions to save global pointer value GP into cprestore
10279 slot MEM. OFFSET is the offset that MEM applies to the base register.
10281 MEM may not be a legitimate address. If it isn't, TEMP is a
10282 temporary register that can be used, otherwise it is a SCRATCH. */
10285 mips_save_gp_to_cprestore_slot (rtx mem, rtx offset, rtx gp, rtx temp)
10287 if (TARGET_CPRESTORE_DIRECTIVE)
10289 gcc_assert (gp == pic_offset_table_rtx);
10290 emit_insn (PMODE_INSN (gen_cprestore, (mem, offset)));
10293 mips_emit_move (mips_cprestore_slot (temp, false), gp);
10296 /* Restore $gp from its save slot, using TEMP as a temporary base register
10297 if need be. This function is for o32 and o64 abicalls only.
10299 See mips_must_initialize_gp_p for details about how we manage the
10303 mips_restore_gp_from_cprestore_slot (rtx temp)
10305 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI && epilogue_completed);
10307 if (!cfun->machine->must_restore_gp_when_clobbered_p)
10309 emit_note (NOTE_INSN_DELETED);
10315 mips_emit_move (temp, mips_cprestore_slot (temp, true));
10316 mips_emit_move (pic_offset_table_rtx, temp);
10319 mips_emit_move (pic_offset_table_rtx, mips_cprestore_slot (temp, true));
10320 if (!TARGET_EXPLICIT_RELOCS)
10321 emit_insn (gen_blockage ());
10324 /* A function to save or store a register. The first argument is the
10325 register and the second is the stack slot. */
10326 typedef void (*mips_save_restore_fn) (rtx, rtx);
10328 /* Use FN to save or restore register REGNO. MODE is the register's
10329 mode and OFFSET is the offset of its save slot from the current
10333 mips_save_restore_reg (enum machine_mode mode, int regno,
10334 HOST_WIDE_INT offset, mips_save_restore_fn fn)
10338 mem = gen_frame_mem (mode, plus_constant (Pmode, stack_pointer_rtx,
10340 fn (gen_rtx_REG (mode, regno), mem);
10343 /* Call FN for each accumlator that is saved by the current function.
10344 SP_OFFSET is the offset of the current stack pointer from the start
10348 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
10350 HOST_WIDE_INT offset;
10353 offset = cfun->machine->frame.acc_sp_offset - sp_offset;
10354 if (BITSET_P (cfun->machine->frame.acc_mask, 0))
10356 mips_save_restore_reg (word_mode, LO_REGNUM, offset, fn);
10357 offset -= UNITS_PER_WORD;
10358 mips_save_restore_reg (word_mode, HI_REGNUM, offset, fn);
10359 offset -= UNITS_PER_WORD;
10362 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
10363 if (BITSET_P (cfun->machine->frame.acc_mask,
10364 ((regno - DSP_ACC_REG_FIRST) / 2) + 1))
10366 mips_save_restore_reg (word_mode, regno, offset, fn);
10367 offset -= UNITS_PER_WORD;
10371 /* Save register REG to MEM. Make the instruction frame-related. */
10374 mips_save_reg (rtx reg, rtx mem)
10376 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
10380 mips_emit_move_or_split (mem, reg, SPLIT_IF_NECESSARY);
10382 x1 = mips_frame_set (mips_subword (mem, false),
10383 mips_subword (reg, false));
10384 x2 = mips_frame_set (mips_subword (mem, true),
10385 mips_subword (reg, true));
10386 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
10389 mips_emit_save_slot_move (mem, reg, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
10392 /* Capture the register combinations that are allowed in a SWM or LWM
10393 instruction. The entries are ordered by number of registers set in
10394 the mask. We also ignore the single register encodings because a
10395 normal SW/LW is preferred. */
10397 static const unsigned int umips_swm_mask[17] = {
10398 0xc0ff0000, 0x80ff0000, 0x40ff0000, 0x807f0000,
10399 0x00ff0000, 0x803f0000, 0x007f0000, 0x801f0000,
10400 0x003f0000, 0x800f0000, 0x001f0000, 0x80070000,
10401 0x000f0000, 0x80030000, 0x00070000, 0x80010000,
10405 static const unsigned int umips_swm_encoding[17] = {
10406 25, 24, 9, 23, 8, 22, 7, 21, 6, 20, 5, 19, 4, 18, 3, 17, 2
10409 /* Try to use a microMIPS LWM or SWM instruction to save or restore
10410 as many GPRs in *MASK as possible. *OFFSET is the offset from the
10411 stack pointer of the topmost save slot.
10413 Remove from *MASK all registers that were handled using LWM and SWM.
10414 Update *OFFSET so that it points to the first unused save slot. */
10417 umips_build_save_restore (mips_save_restore_fn fn,
10418 unsigned *mask, HOST_WIDE_INT *offset)
10422 rtx pattern, set, reg, mem;
10423 HOST_WIDE_INT this_offset;
10426 /* Try matching $16 to $31 (s0 to ra). */
10427 for (i = 0; i < ARRAY_SIZE (umips_swm_mask); i++)
10428 if ((*mask & 0xffff0000) == umips_swm_mask[i])
10431 if (i == ARRAY_SIZE (umips_swm_mask))
10434 /* Get the offset of the lowest save slot. */
10435 nregs = (umips_swm_encoding[i] & 0xf) + (umips_swm_encoding[i] >> 4);
10436 this_offset = *offset - UNITS_PER_WORD * (nregs - 1);
10438 /* LWM/SWM can only support offsets from -2048 to 2047. */
10439 if (!UMIPS_12BIT_OFFSET_P (this_offset))
10442 /* Create the final PARALLEL. */
10443 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nregs));
10444 this_base = stack_pointer_rtx;
10446 /* For registers $16-$23 and $30. */
10447 for (j = 0; j < (umips_swm_encoding[i] & 0xf); j++)
10449 HOST_WIDE_INT offset = this_offset + j * UNITS_PER_WORD;
10450 mem = gen_frame_mem (SImode, plus_constant (Pmode, this_base, offset));
10451 unsigned int regno = (j != 8) ? 16 + j : 30;
10452 *mask &= ~(1 << regno);
10453 reg = gen_rtx_REG (SImode, regno);
10454 if (fn == mips_save_reg)
10455 set = mips_frame_set (mem, reg);
10458 set = gen_rtx_SET (VOIDmode, reg, mem);
10459 mips_add_cfa_restore (reg);
10461 XVECEXP (pattern, 0, j) = set;
10464 /* For register $31. */
10465 if (umips_swm_encoding[i] >> 4)
10467 HOST_WIDE_INT offset = this_offset + j * UNITS_PER_WORD;
10468 *mask &= ~(1 << 31);
10469 mem = gen_frame_mem (SImode, plus_constant (Pmode, this_base, offset));
10470 reg = gen_rtx_REG (SImode, 31);
10471 if (fn == mips_save_reg)
10472 set = mips_frame_set (mem, reg);
10475 set = gen_rtx_SET (VOIDmode, reg, mem);
10476 mips_add_cfa_restore (reg);
10478 XVECEXP (pattern, 0, j) = set;
10481 pattern = emit_insn (pattern);
10482 if (fn == mips_save_reg)
10483 RTX_FRAME_RELATED_P (pattern) = 1;
10485 /* Adjust the last offset. */
10486 *offset -= UNITS_PER_WORD * nregs;
10491 /* Call FN for each register that is saved by the current function.
10492 SP_OFFSET is the offset of the current stack pointer from the start
10496 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset,
10497 mips_save_restore_fn fn)
10499 enum machine_mode fpr_mode;
10501 const struct mips_frame_info *frame = &cfun->machine->frame;
10502 HOST_WIDE_INT offset;
10505 /* Save registers starting from high to low. The debuggers prefer at least
10506 the return register be stored at func+4, and also it allows us not to
10507 need a nop in the epilogue if at least one register is reloaded in
10508 addition to return address. */
10509 offset = frame->gp_sp_offset - sp_offset;
10510 mask = frame->mask;
10512 if (TARGET_MICROMIPS)
10513 umips_build_save_restore (fn, &mask, &offset);
10515 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
10516 if (BITSET_P (mask, regno - GP_REG_FIRST))
10518 /* Record the ra offset for use by mips_function_profiler. */
10519 if (regno == RETURN_ADDR_REGNUM)
10520 cfun->machine->frame.ra_fp_offset = offset + sp_offset;
10521 mips_save_restore_reg (word_mode, regno, offset, fn);
10522 offset -= UNITS_PER_WORD;
10525 /* This loop must iterate over the same space as its companion in
10526 mips_compute_frame_info. */
10527 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
10528 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
10529 for (regno = FP_REG_LAST - MAX_FPRS_PER_FMT + 1;
10530 regno >= FP_REG_FIRST;
10531 regno -= MAX_FPRS_PER_FMT)
10532 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
10534 mips_save_restore_reg (fpr_mode, regno, offset, fn);
10535 offset -= GET_MODE_SIZE (fpr_mode);
10539 /* Return true if a move between register REGNO and its save slot (MEM)
10540 can be done in a single move. LOAD_P is true if we are loading
10541 from the slot, false if we are storing to it. */
10544 mips_direct_save_slot_move_p (unsigned int regno, rtx mem, bool load_p)
10546 /* There is a specific MIPS16 instruction for saving $31 to the stack. */
10547 if (TARGET_MIPS16 && !load_p && regno == RETURN_ADDR_REGNUM)
10550 return mips_secondary_reload_class (REGNO_REG_CLASS (regno),
10551 GET_MODE (mem), mem, load_p) == NO_REGS;
10554 /* Emit a move from SRC to DEST, given that one of them is a register
10555 save slot and that the other is a register. TEMP is a temporary
10556 GPR of the same mode that is available if need be. */
10559 mips_emit_save_slot_move (rtx dest, rtx src, rtx temp)
10561 unsigned int regno;
10566 regno = REGNO (src);
10571 regno = REGNO (dest);
10575 if (regno == cfun->machine->global_pointer && !mips_must_initialize_gp_p ())
10577 /* We don't yet know whether we'll need this instruction or not.
10578 Postpone the decision by emitting a ghost move. This move
10579 is specifically not frame-related; only the split version is. */
10581 emit_insn (gen_move_gpdi (dest, src));
10583 emit_insn (gen_move_gpsi (dest, src));
10587 if (regno == HI_REGNUM)
10591 mips_emit_move (temp, src);
10593 emit_insn (gen_mthisi_di (gen_rtx_REG (TImode, MD_REG_FIRST),
10594 temp, gen_rtx_REG (DImode, LO_REGNUM)));
10596 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode, MD_REG_FIRST),
10597 temp, gen_rtx_REG (SImode, LO_REGNUM)));
10602 emit_insn (gen_mfhidi_ti (temp,
10603 gen_rtx_REG (TImode, MD_REG_FIRST)));
10605 emit_insn (gen_mfhisi_di (temp,
10606 gen_rtx_REG (DImode, MD_REG_FIRST)));
10607 mips_emit_move (dest, temp);
10610 else if (mips_direct_save_slot_move_p (regno, mem, mem == src))
10611 mips_emit_move (dest, src);
10614 gcc_assert (!reg_overlap_mentioned_p (dest, temp));
10615 mips_emit_move (temp, src);
10616 mips_emit_move (dest, temp);
10619 mips_set_frame_expr (mips_frame_set (dest, src));
10622 /* If we're generating n32 or n64 abicalls, and the current function
10623 does not use $28 as its global pointer, emit a cplocal directive.
10624 Use pic_offset_table_rtx as the argument to the directive. */
10627 mips_output_cplocal (void)
10629 if (!TARGET_EXPLICIT_RELOCS
10630 && mips_must_initialize_gp_p ()
10631 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
10632 output_asm_insn (".cplocal %+", 0);
10635 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
10638 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
10640 const char *fnname;
10642 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
10643 floating-point arguments. */
10645 && TARGET_HARD_FLOAT_ABI
10646 && crtl->args.info.fp_code != 0)
10647 mips16_build_function_stub ();
10649 /* Get the function name the same way that toplev.c does before calling
10650 assemble_start_function. This is needed so that the name used here
10651 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10652 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
10653 mips_start_function_definition (fnname, TARGET_MIPS16);
10655 /* Output MIPS-specific frame information. */
10656 if (!flag_inhibit_size_directive)
10658 const struct mips_frame_info *frame;
10660 frame = &cfun->machine->frame;
10662 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
10664 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
10665 "# vars= " HOST_WIDE_INT_PRINT_DEC
10667 ", args= " HOST_WIDE_INT_PRINT_DEC
10668 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
10669 reg_names[frame_pointer_needed
10670 ? HARD_FRAME_POINTER_REGNUM
10671 : STACK_POINTER_REGNUM],
10672 (frame_pointer_needed
10673 ? frame->total_size - frame->hard_frame_pointer_offset
10674 : frame->total_size),
10675 reg_names[RETURN_ADDR_REGNUM],
10677 frame->num_gp, frame->num_fp,
10679 frame->cprestore_size);
10681 /* .mask MASK, OFFSET. */
10682 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
10683 frame->mask, frame->gp_save_offset);
10685 /* .fmask MASK, OFFSET. */
10686 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
10687 frame->fmask, frame->fp_save_offset);
10690 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
10691 Also emit the ".set noreorder; .set nomacro" sequence for functions
10693 if (mips_must_initialize_gp_p ()
10694 && mips_current_loadgp_style () == LOADGP_OLDABI)
10698 /* This is a fixed-form sequence. The position of the
10699 first two instructions is important because of the
10700 way _gp_disp is defined. */
10701 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
10702 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
10703 output_asm_insn ("sll\t$2,16", 0);
10704 output_asm_insn ("addu\t$2,$3", 0);
10708 /* .cpload must be in a .set noreorder but not a
10709 .set nomacro block. */
10710 mips_push_asm_switch (&mips_noreorder);
10711 output_asm_insn (".cpload\t%^", 0);
10712 if (!cfun->machine->all_noreorder_p)
10713 mips_pop_asm_switch (&mips_noreorder);
10715 mips_push_asm_switch (&mips_nomacro);
10718 else if (cfun->machine->all_noreorder_p)
10720 mips_push_asm_switch (&mips_noreorder);
10721 mips_push_asm_switch (&mips_nomacro);
10724 /* Tell the assembler which register we're using as the global
10725 pointer. This is needed for thunks, since they can use either
10726 explicit relocs or assembler macros. */
10727 mips_output_cplocal ();
10730 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
10733 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
10734 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
10736 const char *fnname;
10738 /* Reinstate the normal $gp. */
10739 SET_REGNO (pic_offset_table_rtx, GLOBAL_POINTER_REGNUM);
10740 mips_output_cplocal ();
10742 if (cfun->machine->all_noreorder_p)
10744 mips_pop_asm_switch (&mips_nomacro);
10745 mips_pop_asm_switch (&mips_noreorder);
10748 /* Get the function name the same way that toplev.c does before calling
10749 assemble_start_function. This is needed so that the name used here
10750 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10751 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
10752 mips_end_function_definition (fnname);
10755 /* Emit an optimisation barrier for accesses to the current frame. */
10758 mips_frame_barrier (void)
10760 emit_clobber (gen_frame_mem (BLKmode, stack_pointer_rtx));
10764 /* The __gnu_local_gp symbol. */
10766 static GTY(()) rtx mips_gnu_local_gp;
10768 /* If we're generating n32 or n64 abicalls, emit instructions
10769 to set up the global pointer. */
10772 mips_emit_loadgp (void)
10774 rtx addr, offset, incoming_address, base, index, pic_reg;
10776 pic_reg = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
10777 switch (mips_current_loadgp_style ())
10779 case LOADGP_ABSOLUTE:
10780 if (mips_gnu_local_gp == NULL)
10782 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
10783 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
10785 emit_insn (PMODE_INSN (gen_loadgp_absolute,
10786 (pic_reg, mips_gnu_local_gp)));
10789 case LOADGP_OLDABI:
10790 /* Added by mips_output_function_prologue. */
10793 case LOADGP_NEWABI:
10794 addr = XEXP (DECL_RTL (current_function_decl), 0);
10795 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
10796 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
10797 emit_insn (PMODE_INSN (gen_loadgp_newabi,
10798 (pic_reg, offset, incoming_address)));
10802 base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE));
10803 index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX));
10804 emit_insn (PMODE_INSN (gen_loadgp_rtp, (pic_reg, base, index)));
10812 emit_insn (PMODE_INSN (gen_copygp_mips16,
10813 (pic_offset_table_rtx, pic_reg)));
10815 /* Emit a blockage if there are implicit uses of the GP register.
10816 This includes profiled functions, because FUNCTION_PROFILE uses
10818 if (!TARGET_EXPLICIT_RELOCS || crtl->profile)
10819 emit_insn (gen_loadgp_blockage ());
10822 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
10824 #if PROBE_INTERVAL > 32768
10825 #error Cannot use indexed addressing mode for stack probing
10828 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
10829 inclusive. These are offsets from the current stack pointer. */
10832 mips_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size)
10835 sorry ("-fstack-check=specific not implemented for MIPS16");
10837 /* See if we have a constant small number of probes to generate. If so,
10838 that's the easy case. */
10839 if (first + size <= 32768)
10843 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
10844 it exceeds SIZE. If only one probe is needed, this will not
10845 generate any code. Then probe at FIRST + SIZE. */
10846 for (i = PROBE_INTERVAL; i < size; i += PROBE_INTERVAL)
10847 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
10850 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
10854 /* Otherwise, do the same as above, but in a loop. Note that we must be
10855 extra careful with variables wrapping around because we might be at
10856 the very top (or the very bottom) of the address space and we have
10857 to be able to handle this case properly; in particular, we use an
10858 equality test for the loop condition. */
10861 HOST_WIDE_INT rounded_size;
10862 rtx r3 = MIPS_PROLOGUE_TEMP (Pmode);
10863 rtx r12 = MIPS_PROLOGUE_TEMP2 (Pmode);
10865 /* Sanity check for the addressing mode we're going to use. */
10866 gcc_assert (first <= 32768);
10869 /* Step 1: round SIZE to the previous multiple of the interval. */
10871 rounded_size = size & -PROBE_INTERVAL;
10874 /* Step 2: compute initial and final value of the loop counter. */
10876 /* TEST_ADDR = SP + FIRST. */
10877 emit_insn (gen_rtx_SET (VOIDmode, r3,
10878 plus_constant (Pmode, stack_pointer_rtx,
10881 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
10882 if (rounded_size > 32768)
10884 emit_move_insn (r12, GEN_INT (rounded_size));
10885 emit_insn (gen_rtx_SET (VOIDmode, r12,
10886 gen_rtx_MINUS (Pmode, r3, r12)));
10889 emit_insn (gen_rtx_SET (VOIDmode, r12,
10890 plus_constant (Pmode, r3, -rounded_size)));
10893 /* Step 3: the loop
10895 while (TEST_ADDR != LAST_ADDR)
10897 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
10901 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
10902 until it is equal to ROUNDED_SIZE. */
10904 emit_insn (PMODE_INSN (gen_probe_stack_range, (r3, r3, r12)));
10907 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
10908 that SIZE is equal to ROUNDED_SIZE. */
10910 if (size != rounded_size)
10911 emit_stack_probe (plus_constant (Pmode, r12, rounded_size - size));
10914 /* Make sure nothing is scheduled before we are done. */
10915 emit_insn (gen_blockage ());
10918 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
10919 absolute addresses. */
10922 mips_output_probe_stack_range (rtx reg1, rtx reg2)
10924 static int labelno = 0;
10925 char loop_lab[32], end_lab[32], tmp[64];
10928 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno);
10929 ASM_GENERATE_INTERNAL_LABEL (end_lab, "LPSRE", labelno++);
10931 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
10933 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
10936 strcpy (tmp, "%(%<beq\t%0,%1,");
10937 output_asm_insn (strcat (tmp, &end_lab[1]), xops);
10939 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
10940 xops[1] = GEN_INT (-PROBE_INTERVAL);
10941 if (TARGET_64BIT && TARGET_LONG64)
10942 output_asm_insn ("daddiu\t%0,%0,%1", xops);
10944 output_asm_insn ("addiu\t%0,%0,%1", xops);
10946 /* Probe at TEST_ADDR and branch. */
10947 fprintf (asm_out_file, "\tb\t");
10948 assemble_name_raw (asm_out_file, loop_lab);
10949 fputc ('\n', asm_out_file);
10951 output_asm_insn ("sd\t$0,0(%0)%)", xops);
10953 output_asm_insn ("sw\t$0,0(%0)%)", xops);
10955 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, end_lab);
10960 /* A for_each_rtx callback. Stop the search if *X is a kernel register. */
10963 mips_kernel_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
10965 return REG_P (*x) && KERNEL_REG_P (REGNO (*x));
10968 /* Expand the "prologue" pattern. */
10971 mips_expand_prologue (void)
10973 const struct mips_frame_info *frame;
10974 HOST_WIDE_INT size;
10975 unsigned int nargs;
10978 if (cfun->machine->global_pointer != INVALID_REGNUM)
10980 /* Check whether an insn uses pic_offset_table_rtx, either explicitly
10981 or implicitly. If so, we can commit to using a global pointer
10982 straight away, otherwise we need to defer the decision. */
10983 if (mips_cfun_has_inflexible_gp_ref_p ()
10984 || mips_cfun_has_flexible_gp_ref_p ())
10986 cfun->machine->must_initialize_gp_p = true;
10987 cfun->machine->must_restore_gp_when_clobbered_p = true;
10990 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
10993 frame = &cfun->machine->frame;
10994 size = frame->total_size;
10996 if (flag_stack_usage_info)
10997 current_function_static_stack_size = size;
10999 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK)
11001 if (crtl->is_leaf && !cfun->calls_alloca)
11003 if (size > PROBE_INTERVAL && size > STACK_CHECK_PROTECT)
11004 mips_emit_probe_stack_range (STACK_CHECK_PROTECT,
11005 size - STACK_CHECK_PROTECT);
11008 mips_emit_probe_stack_range (STACK_CHECK_PROTECT, size);
11011 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
11012 bytes beforehand; this is enough to cover the register save area
11013 without going out of range. */
11014 if (((frame->mask | frame->fmask | frame->acc_mask) != 0)
11015 || frame->num_cop0_regs > 0)
11017 HOST_WIDE_INT step1;
11019 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
11020 if (GENERATE_MIPS16E_SAVE_RESTORE)
11022 HOST_WIDE_INT offset;
11023 unsigned int mask, regno;
11025 /* Try to merge argument stores into the save instruction. */
11026 nargs = mips16e_collect_argument_saves ();
11028 /* Build the save instruction. */
11029 mask = frame->mask;
11030 insn = mips16e_build_save_restore (false, &mask, &offset,
11032 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
11033 mips_frame_barrier ();
11036 /* Check if we need to save other registers. */
11037 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
11038 if (BITSET_P (mask, regno - GP_REG_FIRST))
11040 offset -= UNITS_PER_WORD;
11041 mips_save_restore_reg (word_mode, regno,
11042 offset, mips_save_reg);
11047 if (cfun->machine->interrupt_handler_p)
11049 HOST_WIDE_INT offset;
11052 /* If this interrupt is using a shadow register set, we need to
11053 get the stack pointer from the previous register set. */
11054 if (cfun->machine->use_shadow_register_set_p)
11055 emit_insn (gen_mips_rdpgpr (stack_pointer_rtx,
11056 stack_pointer_rtx));
11058 if (!cfun->machine->keep_interrupts_masked_p)
11060 /* Move from COP0 Cause to K0. */
11061 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K0_REG_NUM),
11062 gen_rtx_REG (SImode,
11063 COP0_CAUSE_REG_NUM)));
11064 /* Move from COP0 EPC to K1. */
11065 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
11066 gen_rtx_REG (SImode,
11067 COP0_EPC_REG_NUM)));
11070 /* Allocate the first part of the frame. */
11071 insn = gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx,
11073 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
11074 mips_frame_barrier ();
11077 /* Start at the uppermost location for saving. */
11078 offset = frame->cop0_sp_offset - size;
11079 if (!cfun->machine->keep_interrupts_masked_p)
11081 /* Push EPC into its stack slot. */
11082 mem = gen_frame_mem (word_mode,
11083 plus_constant (Pmode, stack_pointer_rtx,
11085 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
11086 offset -= UNITS_PER_WORD;
11089 /* Move from COP0 Status to K1. */
11090 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
11091 gen_rtx_REG (SImode,
11092 COP0_STATUS_REG_NUM)));
11094 /* Right justify the RIPL in k0. */
11095 if (!cfun->machine->keep_interrupts_masked_p)
11096 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode, K0_REG_NUM),
11097 gen_rtx_REG (SImode, K0_REG_NUM),
11098 GEN_INT (CAUSE_IPL)));
11100 /* Push Status into its stack slot. */
11101 mem = gen_frame_mem (word_mode,
11102 plus_constant (Pmode, stack_pointer_rtx,
11104 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
11105 offset -= UNITS_PER_WORD;
11107 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
11108 if (!cfun->machine->keep_interrupts_masked_p)
11109 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
11112 gen_rtx_REG (SImode, K0_REG_NUM)));
11114 if (!cfun->machine->keep_interrupts_masked_p)
11115 /* Enable interrupts by clearing the KSU ERL and EXL bits.
11116 IE is already the correct value, so we don't have to do
11117 anything explicit. */
11118 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
11121 gen_rtx_REG (SImode, GP_REG_FIRST)));
11123 /* Disable interrupts by clearing the KSU, ERL, EXL,
11125 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
11128 gen_rtx_REG (SImode, GP_REG_FIRST)));
11132 insn = gen_add3_insn (stack_pointer_rtx,
11135 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
11136 mips_frame_barrier ();
11139 mips_for_each_saved_acc (size, mips_save_reg);
11140 mips_for_each_saved_gpr_and_fpr (size, mips_save_reg);
11144 /* Allocate the rest of the frame. */
11147 if (SMALL_OPERAND (-size))
11148 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
11150 GEN_INT (-size)))) = 1;
11153 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
11156 /* There are no instructions to add or subtract registers
11157 from the stack pointer, so use the frame pointer as a
11158 temporary. We should always be using a frame pointer
11159 in this case anyway. */
11160 gcc_assert (frame_pointer_needed);
11161 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
11162 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
11163 hard_frame_pointer_rtx,
11164 MIPS_PROLOGUE_TEMP (Pmode)));
11165 mips_emit_move (stack_pointer_rtx, hard_frame_pointer_rtx);
11168 emit_insn (gen_sub3_insn (stack_pointer_rtx,
11170 MIPS_PROLOGUE_TEMP (Pmode)));
11172 /* Describe the combined effect of the previous instructions. */
11173 mips_set_frame_expr
11174 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
11175 plus_constant (Pmode, stack_pointer_rtx, -size)));
11177 mips_frame_barrier ();
11180 /* Set up the frame pointer, if we're using one. */
11181 if (frame_pointer_needed)
11183 HOST_WIDE_INT offset;
11185 offset = frame->hard_frame_pointer_offset;
11188 insn = mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
11189 RTX_FRAME_RELATED_P (insn) = 1;
11191 else if (SMALL_OPERAND (offset))
11193 insn = gen_add3_insn (hard_frame_pointer_rtx,
11194 stack_pointer_rtx, GEN_INT (offset));
11195 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
11199 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (offset));
11200 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
11201 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
11202 hard_frame_pointer_rtx,
11203 MIPS_PROLOGUE_TEMP (Pmode)));
11204 mips_set_frame_expr
11205 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
11206 plus_constant (Pmode, stack_pointer_rtx, offset)));
11210 mips_emit_loadgp ();
11212 /* Initialize the $gp save slot. */
11213 if (mips_cfun_has_cprestore_slot_p ())
11215 rtx base, mem, gp, temp;
11216 HOST_WIDE_INT offset;
11218 mips_get_cprestore_base_and_offset (&base, &offset, false);
11219 mem = gen_frame_mem (Pmode, plus_constant (Pmode, base, offset));
11220 gp = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
11221 temp = (SMALL_OPERAND (offset)
11222 ? gen_rtx_SCRATCH (Pmode)
11223 : MIPS_PROLOGUE_TEMP (Pmode));
11224 emit_insn (PMODE_INSN (gen_potential_cprestore,
11225 (mem, GEN_INT (offset), gp, temp)));
11227 mips_get_cprestore_base_and_offset (&base, &offset, true);
11228 mem = gen_frame_mem (Pmode, plus_constant (Pmode, base, offset));
11229 emit_insn (PMODE_INSN (gen_use_cprestore, (mem)));
11232 /* We need to search back to the last use of K0 or K1. */
11233 if (cfun->machine->interrupt_handler_p)
11235 for (insn = get_last_insn (); insn != NULL_RTX; insn = PREV_INSN (insn))
11237 && for_each_rtx (&PATTERN (insn), mips_kernel_reg_p, NULL))
11239 /* Emit a move from K1 to COP0 Status after insn. */
11240 gcc_assert (insn != NULL_RTX);
11241 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
11242 gen_rtx_REG (SImode, K1_REG_NUM)),
11246 /* If we are profiling, make sure no instructions are scheduled before
11247 the call to mcount. */
11249 emit_insn (gen_blockage ());
11252 /* Attach all pending register saves to the previous instruction.
11253 Return that instruction. */
11256 mips_epilogue_emit_cfa_restores (void)
11260 insn = get_last_insn ();
11261 gcc_assert (insn && !REG_NOTES (insn));
11262 if (mips_epilogue.cfa_restores)
11264 RTX_FRAME_RELATED_P (insn) = 1;
11265 REG_NOTES (insn) = mips_epilogue.cfa_restores;
11266 mips_epilogue.cfa_restores = 0;
11271 /* Like mips_epilogue_emit_cfa_restores, but also record that the CFA is
11272 now at REG + OFFSET. */
11275 mips_epilogue_set_cfa (rtx reg, HOST_WIDE_INT offset)
11279 insn = mips_epilogue_emit_cfa_restores ();
11280 if (reg != mips_epilogue.cfa_reg || offset != mips_epilogue.cfa_offset)
11282 RTX_FRAME_RELATED_P (insn) = 1;
11283 REG_NOTES (insn) = alloc_reg_note (REG_CFA_DEF_CFA,
11284 plus_constant (Pmode, reg, offset),
11286 mips_epilogue.cfa_reg = reg;
11287 mips_epilogue.cfa_offset = offset;
11291 /* Emit instructions to restore register REG from slot MEM. Also update
11292 the cfa_restores list. */
11295 mips_restore_reg (rtx reg, rtx mem)
11297 /* There's no MIPS16 instruction to load $31 directly. Load into
11298 $7 instead and adjust the return insn appropriately. */
11299 if (TARGET_MIPS16 && REGNO (reg) == RETURN_ADDR_REGNUM)
11300 reg = gen_rtx_REG (GET_MODE (reg), GP_REG_FIRST + 7);
11301 else if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
11303 mips_add_cfa_restore (mips_subword (reg, true));
11304 mips_add_cfa_restore (mips_subword (reg, false));
11307 mips_add_cfa_restore (reg);
11309 mips_emit_save_slot_move (reg, mem, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
11310 if (REGNO (reg) == REGNO (mips_epilogue.cfa_reg))
11311 /* The CFA is currently defined in terms of the register whose
11312 value we have just restored. Redefine the CFA in terms of
11313 the stack pointer. */
11314 mips_epilogue_set_cfa (stack_pointer_rtx,
11315 mips_epilogue.cfa_restore_sp_offset);
11318 /* Emit code to set the stack pointer to BASE + OFFSET, given that
11319 BASE + OFFSET is NEW_FRAME_SIZE bytes below the top of the frame.
11320 BASE, if not the stack pointer, is available as a temporary. */
11323 mips_deallocate_stack (rtx base, rtx offset, HOST_WIDE_INT new_frame_size)
11325 if (base == stack_pointer_rtx && offset == const0_rtx)
11328 mips_frame_barrier ();
11329 if (offset == const0_rtx)
11331 emit_move_insn (stack_pointer_rtx, base);
11332 mips_epilogue_set_cfa (stack_pointer_rtx, new_frame_size);
11334 else if (TARGET_MIPS16 && base != stack_pointer_rtx)
11336 emit_insn (gen_add3_insn (base, base, offset));
11337 mips_epilogue_set_cfa (base, new_frame_size);
11338 emit_move_insn (stack_pointer_rtx, base);
11342 emit_insn (gen_add3_insn (stack_pointer_rtx, base, offset));
11343 mips_epilogue_set_cfa (stack_pointer_rtx, new_frame_size);
11347 /* Emit any instructions needed before a return. */
11350 mips_expand_before_return (void)
11352 /* When using a call-clobbered gp, we start out with unified call
11353 insns that include instructions to restore the gp. We then split
11354 these unified calls after reload. These split calls explicitly
11355 clobber gp, so there is no need to define
11356 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
11358 For consistency, we should also insert an explicit clobber of $28
11359 before return insns, so that the post-reload optimizers know that
11360 the register is not live on exit. */
11361 if (TARGET_CALL_CLOBBERED_GP)
11362 emit_clobber (pic_offset_table_rtx);
11365 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
11369 mips_expand_epilogue (bool sibcall_p)
11371 const struct mips_frame_info *frame;
11372 HOST_WIDE_INT step1, step2;
11373 rtx base, adjust, insn;
11374 bool use_jraddiusp_p = false;
11376 if (!sibcall_p && mips_can_use_return_insn ())
11378 emit_jump_insn (gen_return ());
11382 /* In MIPS16 mode, if the return value should go into a floating-point
11383 register, we need to call a helper routine to copy it over. */
11384 if (mips16_cfun_returns_in_fpr_p ())
11385 mips16_copy_fpr_return_value ();
11387 /* Split the frame into two. STEP1 is the amount of stack we should
11388 deallocate before restoring the registers. STEP2 is the amount we
11389 should deallocate afterwards.
11391 Start off by assuming that no registers need to be restored. */
11392 frame = &cfun->machine->frame;
11393 step1 = frame->total_size;
11396 /* Work out which register holds the frame address. */
11397 if (!frame_pointer_needed)
11398 base = stack_pointer_rtx;
11401 base = hard_frame_pointer_rtx;
11402 step1 -= frame->hard_frame_pointer_offset;
11404 mips_epilogue.cfa_reg = base;
11405 mips_epilogue.cfa_offset = step1;
11406 mips_epilogue.cfa_restores = NULL_RTX;
11408 /* If we need to restore registers, deallocate as much stack as
11409 possible in the second step without going out of range. */
11410 if ((frame->mask | frame->fmask | frame->acc_mask) != 0
11411 || frame->num_cop0_regs > 0)
11413 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
11417 /* Get an rtx for STEP1 that we can add to BASE. */
11418 adjust = GEN_INT (step1);
11419 if (!SMALL_OPERAND (step1))
11421 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), adjust);
11422 adjust = MIPS_EPILOGUE_TEMP (Pmode);
11424 mips_deallocate_stack (base, adjust, step2);
11426 /* If we're using addressing macros, $gp is implicitly used by all
11427 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
11429 if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS)
11430 emit_insn (gen_blockage ());
11432 mips_epilogue.cfa_restore_sp_offset = step2;
11433 if (GENERATE_MIPS16E_SAVE_RESTORE && frame->mask != 0)
11435 unsigned int regno, mask;
11436 HOST_WIDE_INT offset;
11439 /* Generate the restore instruction. */
11440 mask = frame->mask;
11441 restore = mips16e_build_save_restore (true, &mask, &offset, 0, step2);
11443 /* Restore any other registers manually. */
11444 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
11445 if (BITSET_P (mask, regno - GP_REG_FIRST))
11447 offset -= UNITS_PER_WORD;
11448 mips_save_restore_reg (word_mode, regno, offset, mips_restore_reg);
11451 /* Restore the remaining registers and deallocate the final bit
11453 mips_frame_barrier ();
11454 emit_insn (restore);
11455 mips_epilogue_set_cfa (stack_pointer_rtx, 0);
11459 /* Restore the registers. */
11460 mips_for_each_saved_acc (frame->total_size - step2, mips_restore_reg);
11461 mips_for_each_saved_gpr_and_fpr (frame->total_size - step2,
11464 if (cfun->machine->interrupt_handler_p)
11466 HOST_WIDE_INT offset;
11469 offset = frame->cop0_sp_offset - (frame->total_size - step2);
11470 if (!cfun->machine->keep_interrupts_masked_p)
11472 /* Restore the original EPC. */
11473 mem = gen_frame_mem (word_mode,
11474 plus_constant (Pmode, stack_pointer_rtx,
11476 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
11477 offset -= UNITS_PER_WORD;
11479 /* Move to COP0 EPC. */
11480 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_EPC_REG_NUM),
11481 gen_rtx_REG (SImode, K0_REG_NUM)));
11484 /* Restore the original Status. */
11485 mem = gen_frame_mem (word_mode,
11486 plus_constant (Pmode, stack_pointer_rtx,
11488 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
11489 offset -= UNITS_PER_WORD;
11491 /* If we don't use shadow register set, we need to update SP. */
11492 if (!cfun->machine->use_shadow_register_set_p)
11493 mips_deallocate_stack (stack_pointer_rtx, GEN_INT (step2), 0);
11495 /* The choice of position is somewhat arbitrary in this case. */
11496 mips_epilogue_emit_cfa_restores ();
11498 /* Move to COP0 Status. */
11499 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
11500 gen_rtx_REG (SImode, K0_REG_NUM)));
11502 else if (TARGET_MICROMIPS
11503 && !crtl->calls_eh_return
11506 && mips_unsigned_immediate_p (step2, 5, 2))
11507 use_jraddiusp_p = true;
11509 /* Deallocate the final bit of the frame. */
11510 mips_deallocate_stack (stack_pointer_rtx, GEN_INT (step2), 0);
11513 if (!use_jraddiusp_p)
11514 gcc_assert (!mips_epilogue.cfa_restores);
11516 /* Add in the __builtin_eh_return stack adjustment. We need to
11517 use a temporary in MIPS16 code. */
11518 if (crtl->calls_eh_return)
11522 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
11523 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
11524 MIPS_EPILOGUE_TEMP (Pmode),
11525 EH_RETURN_STACKADJ_RTX));
11526 mips_emit_move (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
11529 emit_insn (gen_add3_insn (stack_pointer_rtx,
11531 EH_RETURN_STACKADJ_RTX));
11536 mips_expand_before_return ();
11537 if (cfun->machine->interrupt_handler_p)
11539 /* Interrupt handlers generate eret or deret. */
11540 if (cfun->machine->use_debug_exception_return_p)
11541 emit_jump_insn (gen_mips_deret ());
11543 emit_jump_insn (gen_mips_eret ());
11549 /* When generating MIPS16 code, the normal
11550 mips_for_each_saved_gpr_and_fpr path will restore the return
11551 address into $7 rather than $31. */
11553 && !GENERATE_MIPS16E_SAVE_RESTORE
11554 && BITSET_P (frame->mask, RETURN_ADDR_REGNUM))
11556 /* simple_returns cannot rely on values that are only available
11557 on paths through the epilogue (because return paths that do
11558 not pass through the epilogue may nevertheless reuse a
11559 simple_return that occurs at the end of the epilogue).
11560 Use a normal return here instead. */
11561 rtx reg = gen_rtx_REG (Pmode, GP_REG_FIRST + 7);
11562 pat = gen_return_internal (reg);
11564 else if (use_jraddiusp_p)
11565 pat = gen_jraddiusp (GEN_INT (step2));
11568 rtx reg = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
11569 pat = gen_simple_return_internal (reg);
11571 emit_jump_insn (pat);
11572 if (use_jraddiusp_p)
11573 mips_epilogue_set_cfa (stack_pointer_rtx, step2);
11577 /* Search from the beginning to the first use of K0 or K1. */
11578 if (cfun->machine->interrupt_handler_p
11579 && !cfun->machine->keep_interrupts_masked_p)
11581 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
11583 && for_each_rtx (&PATTERN(insn), mips_kernel_reg_p, NULL))
11585 gcc_assert (insn != NULL_RTX);
11586 /* Insert disable interrupts before the first use of K0 or K1. */
11587 emit_insn_before (gen_mips_di (), insn);
11588 emit_insn_before (gen_mips_ehb (), insn);
11592 /* Return nonzero if this function is known to have a null epilogue.
11593 This allows the optimizer to omit jumps to jumps if no stack
11597 mips_can_use_return_insn (void)
11599 /* Interrupt handlers need to go through the epilogue. */
11600 if (cfun->machine->interrupt_handler_p)
11603 if (!reload_completed)
11609 /* In MIPS16 mode, a function that returns a floating-point value
11610 needs to arrange to copy the return value into the floating-point
11612 if (mips16_cfun_returns_in_fpr_p ())
11615 return cfun->machine->frame.total_size == 0;
11618 /* Return true if register REGNO can store a value of mode MODE.
11619 The result of this function is cached in mips_hard_regno_mode_ok. */
11622 mips_hard_regno_mode_ok_p (unsigned int regno, enum machine_mode mode)
11625 enum mode_class mclass;
11627 if (mode == CCV2mode)
11628 return (ISA_HAS_8CC
11629 && ST_REG_P (regno)
11630 && (regno - ST_REG_FIRST) % 2 == 0);
11632 if (mode == CCV4mode)
11633 return (ISA_HAS_8CC
11634 && ST_REG_P (regno)
11635 && (regno - ST_REG_FIRST) % 4 == 0);
11637 if (mode == CCmode)
11638 return ISA_HAS_8CC ? ST_REG_P (regno) : regno == FPSW_REGNUM;
11640 size = GET_MODE_SIZE (mode);
11641 mclass = GET_MODE_CLASS (mode);
11643 if (GP_REG_P (regno))
11644 return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD;
11646 if (FP_REG_P (regno)
11647 && (((regno - FP_REG_FIRST) % MAX_FPRS_PER_FMT) == 0
11648 || (MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG)))
11650 /* Allow 64-bit vector modes for Loongson-2E/2F. */
11651 if (TARGET_LOONGSON_VECTORS
11652 && (mode == V2SImode
11653 || mode == V4HImode
11654 || mode == V8QImode
11655 || mode == DImode))
11658 if (mclass == MODE_FLOAT
11659 || mclass == MODE_COMPLEX_FLOAT
11660 || mclass == MODE_VECTOR_FLOAT)
11661 return size <= UNITS_PER_FPVALUE;
11663 /* Allow integer modes that fit into a single register. We need
11664 to put integers into FPRs when using instructions like CVT
11665 and TRUNC. There's no point allowing sizes smaller than a word,
11666 because the FPU has no appropriate load/store instructions. */
11667 if (mclass == MODE_INT)
11668 return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG;
11671 if (ACC_REG_P (regno)
11672 && (INTEGRAL_MODE_P (mode) || ALL_FIXED_POINT_MODE_P (mode)))
11674 if (MD_REG_P (regno))
11676 /* After a multiplication or division, clobbering HI makes
11677 the value of LO unpredictable, and vice versa. This means
11678 that, for all interesting cases, HI and LO are effectively
11681 We model this by requiring that any value that uses HI
11683 if (size <= UNITS_PER_WORD * 2)
11684 return regno == (size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST);
11688 /* DSP accumulators do not have the same restrictions as
11689 HI and LO, so we can treat them as normal doubleword
11691 if (size <= UNITS_PER_WORD)
11694 if (size <= UNITS_PER_WORD * 2
11695 && ((regno - DSP_ACC_REG_FIRST) & 1) == 0)
11700 if (ALL_COP_REG_P (regno))
11701 return mclass == MODE_INT && size <= UNITS_PER_WORD;
11703 if (regno == GOT_VERSION_REGNUM)
11704 return mode == SImode;
11709 /* Implement HARD_REGNO_NREGS. */
11712 mips_hard_regno_nregs (int regno, enum machine_mode mode)
11714 if (ST_REG_P (regno))
11715 /* The size of FP status registers is always 4, because they only hold
11716 CCmode values, and CCmode is always considered to be 4 bytes wide. */
11717 return (GET_MODE_SIZE (mode) + 3) / 4;
11719 if (FP_REG_P (regno))
11720 return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG;
11722 /* All other registers are word-sized. */
11723 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
11726 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
11727 in mips_hard_regno_nregs. */
11730 mips_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
11736 COPY_HARD_REG_SET (left, reg_class_contents[(int) rclass]);
11737 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS]))
11739 if (HARD_REGNO_MODE_OK (ST_REG_FIRST, mode))
11740 size = MIN (size, 4);
11741 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) ST_REGS]);
11743 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS]))
11745 if (HARD_REGNO_MODE_OK (FP_REG_FIRST, mode))
11746 size = MIN (size, UNITS_PER_FPREG);
11747 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]);
11749 if (!hard_reg_set_empty_p (left))
11750 size = MIN (size, UNITS_PER_WORD);
11751 return (GET_MODE_SIZE (mode) + size - 1) / size;
11754 /* Implement CANNOT_CHANGE_MODE_CLASS. */
11757 mips_cannot_change_mode_class (enum machine_mode from,
11758 enum machine_mode to,
11759 enum reg_class rclass)
11761 /* Allow conversions between different Loongson integer vectors,
11762 and between those vectors and DImode. */
11763 if (GET_MODE_SIZE (from) == 8 && GET_MODE_SIZE (to) == 8
11764 && INTEGRAL_MODE_P (from) && INTEGRAL_MODE_P (to))
11767 /* Otherwise, there are several problems with changing the modes of
11768 values in floating-point registers:
11770 - When a multi-word value is stored in paired floating-point
11771 registers, the first register always holds the low word. We
11772 therefore can't allow FPRs to change between single-word and
11773 multi-word modes on big-endian targets.
11775 - GCC assumes that each word of a multiword register can be
11776 accessed individually using SUBREGs. This is not true for
11777 floating-point registers if they are bigger than a word.
11779 - Loading a 32-bit value into a 64-bit floating-point register
11780 will not sign-extend the value, despite what LOAD_EXTEND_OP
11781 says. We can't allow FPRs to change from SImode to a wider
11782 mode on 64-bit targets.
11784 - If the FPU has already interpreted a value in one format, we
11785 must not ask it to treat the value as having a different
11788 We therefore disallow all mode changes involving FPRs. */
11790 return reg_classes_intersect_p (FP_REGS, rclass);
11793 /* Implement target hook small_register_classes_for_mode_p. */
11796 mips_small_register_classes_for_mode_p (enum machine_mode mode
11799 return TARGET_MIPS16;
11802 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
11805 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode)
11810 return TARGET_HARD_FLOAT;
11813 return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT;
11816 return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT;
11823 /* Implement MODES_TIEABLE_P. */
11826 mips_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
11828 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
11829 prefer to put one of them in FPRs. */
11830 return (mode1 == mode2
11831 || (!mips_mode_ok_for_mov_fmt_p (mode1)
11832 && !mips_mode_ok_for_mov_fmt_p (mode2)));
11835 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
11838 mips_preferred_reload_class (rtx x, reg_class_t rclass)
11840 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, rclass))
11843 if (reg_class_subset_p (FP_REGS, rclass)
11844 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x)))
11847 if (reg_class_subset_p (GR_REGS, rclass))
11850 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, rclass))
11856 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
11857 Return a "canonical" class to represent it in later calculations. */
11860 mips_canonicalize_move_class (reg_class_t rclass)
11862 /* All moves involving accumulator registers have the same cost. */
11863 if (reg_class_subset_p (rclass, ACC_REGS))
11866 /* Likewise promote subclasses of general registers to the most
11867 interesting containing class. */
11868 if (TARGET_MIPS16 && reg_class_subset_p (rclass, M16_REGS))
11870 else if (reg_class_subset_p (rclass, GENERAL_REGS))
11871 rclass = GENERAL_REGS;
11876 /* Return the cost of moving a value of mode MODE from a register of
11877 class FROM to a GPR. Return 0 for classes that are unions of other
11878 classes handled by this function. */
11881 mips_move_to_gpr_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
11888 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
11892 /* MFLO and MFHI. */
11900 /* LUI followed by MOVF. */
11906 /* This choice of value is historical. */
11914 /* Return the cost of moving a value of mode MODE from a GPR to a
11915 register of class TO. Return 0 for classes that are unions of
11916 other classes handled by this function. */
11919 mips_move_from_gpr_cost (enum machine_mode mode, reg_class_t to)
11925 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
11929 /* MTLO and MTHI. */
11937 /* A secondary reload through an FPR scratch. */
11938 return (mips_register_move_cost (mode, GENERAL_REGS, FP_REGS)
11939 + mips_register_move_cost (mode, FP_REGS, ST_REGS));
11944 /* This choice of value is historical. */
11952 /* Implement TARGET_REGISTER_MOVE_COST. Return 0 for classes that are the
11953 maximum of the move costs for subclasses; regclass will work out
11954 the maximum for us. */
11957 mips_register_move_cost (enum machine_mode mode,
11958 reg_class_t from, reg_class_t to)
11963 from = mips_canonicalize_move_class (from);
11964 to = mips_canonicalize_move_class (to);
11966 /* Handle moves that can be done without using general-purpose registers. */
11967 if (from == FP_REGS)
11969 if (to == FP_REGS && mips_mode_ok_for_mov_fmt_p (mode))
11973 /* The sequence generated by mips_expand_fcc_reload. */
11977 /* Handle cases in which only one class deviates from the ideal. */
11978 dregs = TARGET_MIPS16 ? M16_REGS : GENERAL_REGS;
11980 return mips_move_from_gpr_cost (mode, to);
11982 return mips_move_to_gpr_cost (mode, from);
11984 /* Handles cases that require a GPR temporary. */
11985 cost1 = mips_move_to_gpr_cost (mode, from);
11988 cost2 = mips_move_from_gpr_cost (mode, to);
11990 return cost1 + cost2;
11996 /* Implement TARGET_MEMORY_MOVE_COST. */
11999 mips_memory_move_cost (enum machine_mode mode, reg_class_t rclass, bool in)
12001 return (mips_cost->memory_latency
12002 + memory_move_secondary_cost (mode, rclass, in));
12005 /* Return the register class required for a secondary register when
12006 copying between one of the registers in RCLASS and value X, which
12007 has mode MODE. X is the source of the move if IN_P, otherwise it
12008 is the destination. Return NO_REGS if no secondary register is
12012 mips_secondary_reload_class (enum reg_class rclass,
12013 enum machine_mode mode, rtx x, bool in_p)
12017 /* If X is a constant that cannot be loaded into $25, it must be loaded
12018 into some other GPR. No other register class allows a direct move. */
12019 if (mips_dangerous_for_la25_p (x))
12020 return reg_class_subset_p (rclass, LEA_REGS) ? NO_REGS : LEA_REGS;
12022 regno = true_regnum (x);
12025 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
12026 if (!reg_class_subset_p (rclass, M16_REGS) && !M16_REG_P (regno))
12032 /* Copying from accumulator registers to anywhere other than a general
12033 register requires a temporary general register. */
12034 if (reg_class_subset_p (rclass, ACC_REGS))
12035 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
12036 if (ACC_REG_P (regno))
12037 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
12039 /* We can only copy a value to a condition code register from a
12040 floating-point register, and even then we require a scratch
12041 floating-point register. We can only copy a value out of a
12042 condition-code register into a general register. */
12043 if (reg_class_subset_p (rclass, ST_REGS))
12047 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
12049 if (ST_REG_P (regno))
12053 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
12056 if (reg_class_subset_p (rclass, FP_REGS))
12059 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8))
12060 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
12061 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
12064 if (GP_REG_P (regno) || x == CONST0_RTX (mode))
12065 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
12068 if (CONSTANT_P (x) && !targetm.cannot_force_const_mem (mode, x))
12069 /* We can force the constant to memory and use lwc1
12070 and ldc1. As above, we will use pairs of lwc1s if
12071 ldc1 is not supported. */
12074 if (FP_REG_P (regno) && mips_mode_ok_for_mov_fmt_p (mode))
12075 /* In this case we can use mov.fmt. */
12078 /* Otherwise, we need to reload through an integer register. */
12081 if (FP_REG_P (regno))
12082 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
12087 /* Implement TARGET_MODE_REP_EXTENDED. */
12090 mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
12092 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
12093 if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
12094 return SIGN_EXTEND;
12099 /* Implement TARGET_VALID_POINTER_MODE. */
12102 mips_valid_pointer_mode (enum machine_mode mode)
12104 return mode == SImode || (TARGET_64BIT && mode == DImode);
12107 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
12110 mips_vector_mode_supported_p (enum machine_mode mode)
12115 return TARGET_PAIRED_SINGLE_FLOAT;
12130 return TARGET_LOONGSON_VECTORS;
12137 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
12140 mips_scalar_mode_supported_p (enum machine_mode mode)
12142 if (ALL_FIXED_POINT_MODE_P (mode)
12143 && GET_MODE_PRECISION (mode) <= 2 * BITS_PER_WORD)
12146 return default_scalar_mode_supported_p (mode);
12149 /* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
12151 static enum machine_mode
12152 mips_preferred_simd_mode (enum machine_mode mode ATTRIBUTE_UNUSED)
12154 if (TARGET_PAIRED_SINGLE_FLOAT
12160 /* Implement TARGET_INIT_LIBFUNCS. */
12163 mips_init_libfuncs (void)
12165 if (TARGET_FIX_VR4120)
12167 /* Register the special divsi3 and modsi3 functions needed to work
12168 around VR4120 division errata. */
12169 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
12170 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
12173 if (TARGET_MIPS16 && TARGET_HARD_FLOAT_ABI)
12175 /* Register the MIPS16 -mhard-float stubs. */
12176 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
12177 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
12178 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
12179 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
12181 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
12182 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
12183 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
12184 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
12185 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
12186 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
12187 set_optab_libfunc (unord_optab, SFmode, "__mips16_unordsf2");
12189 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
12190 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
12191 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__mips16_floatunsisf");
12193 if (TARGET_DOUBLE_FLOAT)
12195 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
12196 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
12197 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
12198 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
12200 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
12201 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
12202 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
12203 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
12204 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
12205 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
12206 set_optab_libfunc (unord_optab, DFmode, "__mips16_unorddf2");
12208 set_conv_libfunc (sext_optab, DFmode, SFmode,
12209 "__mips16_extendsfdf2");
12210 set_conv_libfunc (trunc_optab, SFmode, DFmode,
12211 "__mips16_truncdfsf2");
12212 set_conv_libfunc (sfix_optab, SImode, DFmode,
12213 "__mips16_fix_truncdfsi");
12214 set_conv_libfunc (sfloat_optab, DFmode, SImode,
12215 "__mips16_floatsidf");
12216 set_conv_libfunc (ufloat_optab, DFmode, SImode,
12217 "__mips16_floatunsidf");
12221 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
12222 on an external non-MIPS16 routine to implement __sync_synchronize.
12223 Similarly for the rest of the ll/sc libfuncs. */
12226 synchronize_libfunc = init_one_libfunc ("__sync_synchronize");
12227 init_sync_libfuncs (UNITS_PER_WORD);
12231 /* Build up a multi-insn sequence that loads label TARGET into $AT. */
12234 mips_process_load_label (rtx target)
12236 rtx base, gp, intop;
12237 HOST_WIDE_INT offset;
12239 mips_multi_start ();
12243 mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target, 0);
12244 mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target, 0);
12248 mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target, 0);
12249 mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target, 0);
12253 gp = pic_offset_table_rtx;
12254 if (mips_cfun_has_cprestore_slot_p ())
12256 gp = gen_rtx_REG (Pmode, AT_REGNUM);
12257 mips_get_cprestore_base_and_offset (&base, &offset, true);
12258 if (!SMALL_OPERAND (offset))
12260 intop = GEN_INT (CONST_HIGH_PART (offset));
12261 mips_multi_add_insn ("lui\t%0,%1", gp, intop, 0);
12262 mips_multi_add_insn ("addu\t%0,%0,%1", gp, base, 0);
12265 offset = CONST_LOW_PART (offset);
12267 intop = GEN_INT (offset);
12268 if (ISA_HAS_LOAD_DELAY)
12269 mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp, intop, base, 0);
12271 mips_multi_add_insn ("lw\t%0,%1(%2)", gp, intop, base, 0);
12273 if (ISA_HAS_LOAD_DELAY)
12274 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target, gp, 0);
12276 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target, gp, 0);
12277 mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target, 0);
12282 /* Return the number of instructions needed to load a label into $AT. */
12284 static unsigned int
12285 mips_load_label_num_insns (void)
12287 if (cfun->machine->load_label_num_insns == 0)
12289 mips_process_load_label (pc_rtx);
12290 cfun->machine->load_label_num_insns = mips_multi_num_insns;
12292 return cfun->machine->load_label_num_insns;
12295 /* Emit an asm sequence to start a noat block and load the address
12296 of a label into $1. */
12299 mips_output_load_label (rtx target)
12301 mips_push_asm_switch (&mips_noat);
12302 if (TARGET_EXPLICIT_RELOCS)
12304 mips_process_load_label (target);
12305 mips_multi_write ();
12309 if (Pmode == DImode)
12310 output_asm_insn ("dla\t%@,%0", &target);
12312 output_asm_insn ("la\t%@,%0", &target);
12316 /* Return the length of INSN. LENGTH is the initial length computed by
12317 attributes in the machine-description file. */
12320 mips_adjust_insn_length (rtx insn, int length)
12322 /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length
12323 of a PIC long-branch sequence. Substitute the correct value. */
12324 if (length == MAX_PIC_BRANCH_LENGTH
12326 && INSN_CODE (insn) >= 0
12327 && get_attr_type (insn) == TYPE_BRANCH)
12329 /* Add the branch-over instruction and its delay slot, if this
12330 is a conditional branch. */
12331 length = simplejump_p (insn) ? 0 : 8;
12333 /* Add the size of a load into $AT. */
12334 length += BASE_INSN_LENGTH * mips_load_label_num_insns ();
12336 /* Add the length of an indirect jump, ignoring the delay slot. */
12337 length += TARGET_COMPRESSION ? 2 : 4;
12340 /* A unconditional jump has an unfilled delay slot if it is not part
12341 of a sequence. A conditional jump normally has a delay slot, but
12342 does not on MIPS16. */
12343 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
12344 length += TARGET_MIPS16 ? 2 : 4;
12346 /* See how many nops might be needed to avoid hardware hazards. */
12347 if (!cfun->machine->ignore_hazard_length_p
12349 && INSN_CODE (insn) >= 0)
12350 switch (get_attr_hazard (insn))
12356 length += NOP_INSN_LENGTH;
12360 length += NOP_INSN_LENGTH * 2;
12367 /* Return the assembly code for INSN, which has the operands given by
12368 OPERANDS, and which branches to OPERANDS[0] if some condition is true.
12369 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0]
12370 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
12371 version of BRANCH_IF_TRUE. */
12374 mips_output_conditional_branch (rtx insn, rtx *operands,
12375 const char *branch_if_true,
12376 const char *branch_if_false)
12378 unsigned int length;
12379 rtx taken, not_taken;
12381 gcc_assert (LABEL_P (operands[0]));
12383 length = get_attr_length (insn);
12386 /* Just a simple conditional branch. */
12387 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
12388 return branch_if_true;
12391 /* Generate a reversed branch around a direct jump. This fallback does
12392 not use branch-likely instructions. */
12393 mips_branch_likely = false;
12394 not_taken = gen_label_rtx ();
12395 taken = operands[0];
12397 /* Generate the reversed branch to NOT_TAKEN. */
12398 operands[0] = not_taken;
12399 output_asm_insn (branch_if_false, operands);
12401 /* If INSN has a delay slot, we must provide delay slots for both the
12402 branch to NOT_TAKEN and the conditional jump. We must also ensure
12403 that INSN's delay slot is executed in the appropriate cases. */
12404 if (final_sequence)
12406 /* This first delay slot will always be executed, so use INSN's
12407 delay slot if is not annulled. */
12408 if (!INSN_ANNULLED_BRANCH_P (insn))
12410 final_scan_insn (XVECEXP (final_sequence, 0, 1),
12411 asm_out_file, optimize, 1, NULL);
12412 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
12415 output_asm_insn ("nop", 0);
12416 fprintf (asm_out_file, "\n");
12419 /* Output the unconditional branch to TAKEN. */
12420 if (TARGET_ABSOLUTE_JUMPS)
12421 output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken);
12424 mips_output_load_label (taken);
12425 output_asm_insn ("jr\t%@%]%/", 0);
12428 /* Now deal with its delay slot; see above. */
12429 if (final_sequence)
12431 /* This delay slot will only be executed if the branch is taken.
12432 Use INSN's delay slot if is annulled. */
12433 if (INSN_ANNULLED_BRANCH_P (insn))
12435 final_scan_insn (XVECEXP (final_sequence, 0, 1),
12436 asm_out_file, optimize, 1, NULL);
12437 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
12440 output_asm_insn ("nop", 0);
12441 fprintf (asm_out_file, "\n");
12444 /* Output NOT_TAKEN. */
12445 targetm.asm_out.internal_label (asm_out_file, "L",
12446 CODE_LABEL_NUMBER (not_taken));
12450 /* Return the assembly code for INSN, which branches to OPERANDS[0]
12451 if some ordering condition is true. The condition is given by
12452 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
12453 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
12454 its second is always zero. */
12457 mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
12459 const char *branch[2];
12461 /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true.
12462 Make BRANCH[0] branch on the inverse condition. */
12463 switch (GET_CODE (operands[1]))
12465 /* These cases are equivalent to comparisons against zero. */
12467 inverted_p = !inverted_p;
12468 /* Fall through. */
12470 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%0");
12471 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%0");
12474 /* These cases are always true or always false. */
12476 inverted_p = !inverted_p;
12477 /* Fall through. */
12479 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%0");
12480 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%0");
12484 branch[!inverted_p] = MIPS_BRANCH ("b%C1z", "%2,%0");
12485 branch[inverted_p] = MIPS_BRANCH ("b%N1z", "%2,%0");
12488 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
12491 /* Start a block of code that needs access to the LL, SC and SYNC
12495 mips_start_ll_sc_sync_block (void)
12497 if (!ISA_HAS_LL_SC)
12499 output_asm_insn (".set\tpush", 0);
12501 output_asm_insn (".set\tmips3", 0);
12503 output_asm_insn (".set\tmips2", 0);
12507 /* End a block started by mips_start_ll_sc_sync_block. */
12510 mips_end_ll_sc_sync_block (void)
12512 if (!ISA_HAS_LL_SC)
12513 output_asm_insn (".set\tpop", 0);
12516 /* Output and/or return the asm template for a sync instruction. */
12519 mips_output_sync (void)
12521 mips_start_ll_sc_sync_block ();
12522 output_asm_insn ("sync", 0);
12523 mips_end_ll_sc_sync_block ();
12527 /* Return the asm template associated with sync_insn1 value TYPE.
12528 IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */
12530 static const char *
12531 mips_sync_insn1_template (enum attr_sync_insn1 type, bool is_64bit_p)
12535 case SYNC_INSN1_MOVE:
12536 return "move\t%0,%z2";
12537 case SYNC_INSN1_LI:
12538 return "li\t%0,%2";
12539 case SYNC_INSN1_ADDU:
12540 return is_64bit_p ? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2";
12541 case SYNC_INSN1_ADDIU:
12542 return is_64bit_p ? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2";
12543 case SYNC_INSN1_SUBU:
12544 return is_64bit_p ? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2";
12545 case SYNC_INSN1_AND:
12546 return "and\t%0,%1,%z2";
12547 case SYNC_INSN1_ANDI:
12548 return "andi\t%0,%1,%2";
12549 case SYNC_INSN1_OR:
12550 return "or\t%0,%1,%z2";
12551 case SYNC_INSN1_ORI:
12552 return "ori\t%0,%1,%2";
12553 case SYNC_INSN1_XOR:
12554 return "xor\t%0,%1,%z2";
12555 case SYNC_INSN1_XORI:
12556 return "xori\t%0,%1,%2";
12558 gcc_unreachable ();
12561 /* Return the asm template associated with sync_insn2 value TYPE. */
12563 static const char *
12564 mips_sync_insn2_template (enum attr_sync_insn2 type)
12568 case SYNC_INSN2_NOP:
12569 gcc_unreachable ();
12570 case SYNC_INSN2_AND:
12571 return "and\t%0,%1,%z2";
12572 case SYNC_INSN2_XOR:
12573 return "xor\t%0,%1,%z2";
12574 case SYNC_INSN2_NOT:
12575 return "nor\t%0,%1,%.";
12577 gcc_unreachable ();
12580 /* OPERANDS are the operands to a sync loop instruction and INDEX is
12581 the value of the one of the sync_* attributes. Return the operand
12582 referred to by the attribute, or DEFAULT_VALUE if the insn doesn't
12583 have the associated attribute. */
12586 mips_get_sync_operand (rtx *operands, int index, rtx default_value)
12589 default_value = operands[index - 1];
12590 return default_value;
12593 /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn
12594 sequence for it. */
12597 mips_process_sync_loop (rtx insn, rtx *operands)
12599 rtx at, mem, oldval, newval, inclusive_mask, exclusive_mask;
12600 rtx required_oldval, insn1_op2, tmp1, tmp2, tmp3, cmp;
12601 unsigned int tmp3_insn;
12602 enum attr_sync_insn1 insn1;
12603 enum attr_sync_insn2 insn2;
12606 enum memmodel model;
12608 /* Read an operand from the sync_WHAT attribute and store it in
12609 variable WHAT. DEFAULT is the default value if no attribute
12611 #define READ_OPERAND(WHAT, DEFAULT) \
12612 WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \
12615 /* Read the memory. */
12616 READ_OPERAND (mem, 0);
12618 is_64bit_p = (GET_MODE_BITSIZE (GET_MODE (mem)) == 64);
12620 /* Read the other attributes. */
12621 at = gen_rtx_REG (GET_MODE (mem), AT_REGNUM);
12622 READ_OPERAND (oldval, at);
12623 READ_OPERAND (cmp, 0);
12624 READ_OPERAND (newval, at);
12625 READ_OPERAND (inclusive_mask, 0);
12626 READ_OPERAND (exclusive_mask, 0);
12627 READ_OPERAND (required_oldval, 0);
12628 READ_OPERAND (insn1_op2, 0);
12629 insn1 = get_attr_sync_insn1 (insn);
12630 insn2 = get_attr_sync_insn2 (insn);
12632 /* Don't bother setting CMP result that is never used. */
12633 if (cmp && find_reg_note (insn, REG_UNUSED, cmp))
12636 memmodel_attr = get_attr_sync_memmodel (insn);
12637 switch (memmodel_attr)
12640 model = MEMMODEL_ACQ_REL;
12643 model = MEMMODEL_ACQUIRE;
12646 model = (enum memmodel) INTVAL (operands[memmodel_attr]);
12649 mips_multi_start ();
12651 /* Output the release side of the memory barrier. */
12652 if (need_atomic_barrier_p (model, true))
12654 if (required_oldval == 0 && TARGET_OCTEON)
12656 /* Octeon doesn't reorder reads, so a full barrier can be
12657 created by using SYNCW to order writes combined with the
12658 write from the following SC. When the SC successfully
12659 completes, we know that all preceding writes are also
12660 committed to the coherent memory system. It is possible
12661 for a single SYNCW to fail, but a pair of them will never
12662 fail, so we use two. */
12663 mips_multi_add_insn ("syncw", NULL);
12664 mips_multi_add_insn ("syncw", NULL);
12667 mips_multi_add_insn ("sync", NULL);
12670 /* Output the branch-back label. */
12671 mips_multi_add_label ("1:");
12673 /* OLDVAL = *MEM. */
12674 mips_multi_add_insn (is_64bit_p ? "lld\t%0,%1" : "ll\t%0,%1",
12675 oldval, mem, NULL);
12677 /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */
12678 if (required_oldval)
12680 if (inclusive_mask == 0)
12684 gcc_assert (oldval != at);
12685 mips_multi_add_insn ("and\t%0,%1,%2",
12686 at, oldval, inclusive_mask, NULL);
12689 mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1, required_oldval, NULL);
12691 /* CMP = 0 [delay slot]. */
12693 mips_multi_add_insn ("li\t%0,0", cmp, NULL);
12696 /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */
12697 if (exclusive_mask == 0)
12701 gcc_assert (oldval != at);
12702 mips_multi_add_insn ("and\t%0,%1,%z2",
12703 at, oldval, exclusive_mask, NULL);
12707 /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2).
12709 We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit
12710 at least one instruction in that case. */
12711 if (insn1 == SYNC_INSN1_MOVE
12712 && (tmp1 != const0_rtx || insn2 != SYNC_INSN2_NOP))
12716 mips_multi_add_insn (mips_sync_insn1_template (insn1, is_64bit_p),
12717 newval, oldval, insn1_op2, NULL);
12721 /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */
12722 if (insn2 == SYNC_INSN2_NOP)
12726 mips_multi_add_insn (mips_sync_insn2_template (insn2),
12727 newval, tmp2, inclusive_mask, NULL);
12730 tmp3_insn = mips_multi_last_index ();
12732 /* $AT = $TMP1 | $TMP3. */
12733 if (tmp1 == const0_rtx || tmp3 == const0_rtx)
12735 mips_multi_set_operand (tmp3_insn, 0, at);
12740 gcc_assert (tmp1 != tmp3);
12741 mips_multi_add_insn ("or\t%0,%1,%2", at, tmp1, tmp3, NULL);
12744 /* if (!commit (*MEM = $AT)) goto 1.
12746 This will sometimes be a delayed branch; see the write code below
12748 mips_multi_add_insn (is_64bit_p ? "scd\t%0,%1" : "sc\t%0,%1", at, mem, NULL);
12749 mips_multi_add_insn ("beq%?\t%0,%.,1b", at, NULL);
12751 /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */
12752 if (insn1 != SYNC_INSN1_MOVE && insn1 != SYNC_INSN1_LI && tmp3 != newval)
12754 mips_multi_copy_insn (tmp3_insn);
12755 mips_multi_set_operand (mips_multi_last_index (), 0, newval);
12757 else if (!(required_oldval && cmp))
12758 mips_multi_add_insn ("nop", NULL);
12760 /* CMP = 1 -- either standalone or in a delay slot. */
12761 if (required_oldval && cmp)
12762 mips_multi_add_insn ("li\t%0,1", cmp, NULL);
12764 /* Output the acquire side of the memory barrier. */
12765 if (TARGET_SYNC_AFTER_SC && need_atomic_barrier_p (model, false))
12766 mips_multi_add_insn ("sync", NULL);
12768 /* Output the exit label, if needed. */
12769 if (required_oldval)
12770 mips_multi_add_label ("2:");
12772 #undef READ_OPERAND
12775 /* Output and/or return the asm template for sync loop INSN, which has
12776 the operands given by OPERANDS. */
12779 mips_output_sync_loop (rtx insn, rtx *operands)
12781 mips_process_sync_loop (insn, operands);
12783 /* Use branch-likely instructions to work around the LL/SC R10000
12785 mips_branch_likely = TARGET_FIX_R10000;
12787 mips_push_asm_switch (&mips_noreorder);
12788 mips_push_asm_switch (&mips_nomacro);
12789 mips_push_asm_switch (&mips_noat);
12790 mips_start_ll_sc_sync_block ();
12792 mips_multi_write ();
12794 mips_end_ll_sc_sync_block ();
12795 mips_pop_asm_switch (&mips_noat);
12796 mips_pop_asm_switch (&mips_nomacro);
12797 mips_pop_asm_switch (&mips_noreorder);
12802 /* Return the number of individual instructions in sync loop INSN,
12803 which has the operands given by OPERANDS. */
12806 mips_sync_loop_insns (rtx insn, rtx *operands)
12808 mips_process_sync_loop (insn, operands);
12809 return mips_multi_num_insns;
12812 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
12813 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
12815 When working around R4000 and R4400 errata, we need to make sure that
12816 the division is not immediately followed by a shift[1][2]. We also
12817 need to stop the division from being put into a branch delay slot[3].
12818 The easiest way to avoid both problems is to add a nop after the
12819 division. When a divide-by-zero check is needed, this nop can be
12820 used to fill the branch delay slot.
12822 [1] If a double-word or a variable shift executes immediately
12823 after starting an integer division, the shift may give an
12824 incorrect result. See quotations of errata #16 and #28 from
12825 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
12826 in mips.md for details.
12828 [2] A similar bug to [1] exists for all revisions of the
12829 R4000 and the R4400 when run in an MC configuration.
12830 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
12832 "19. In this following sequence:
12834 ddiv (or ddivu or div or divu)
12835 dsll32 (or dsrl32, dsra32)
12837 if an MPT stall occurs, while the divide is slipping the cpu
12838 pipeline, then the following double shift would end up with an
12841 Workaround: The compiler needs to avoid generating any
12842 sequence with divide followed by extended double shift."
12844 This erratum is also present in "MIPS R4400MC Errata, Processor
12845 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
12846 & 3.0" as errata #10 and #4, respectively.
12848 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
12849 (also valid for MIPS R4000MC processors):
12851 "52. R4000SC: This bug does not apply for the R4000PC.
12853 There are two flavors of this bug:
12855 1) If the instruction just after divide takes an RF exception
12856 (tlb-refill, tlb-invalid) and gets an instruction cache
12857 miss (both primary and secondary) and the line which is
12858 currently in secondary cache at this index had the first
12859 data word, where the bits 5..2 are set, then R4000 would
12860 get a wrong result for the div.
12865 ------------------- # end-of page. -tlb-refill
12870 ------------------- # end-of page. -tlb-invalid
12873 2) If the divide is in the taken branch delay slot, where the
12874 target takes RF exception and gets an I-cache miss for the
12875 exception vector or where I-cache miss occurs for the
12876 target address, under the above mentioned scenarios, the
12877 div would get wrong results.
12880 j r2 # to next page mapped or unmapped
12881 div r8,r9 # this bug would be there as long
12882 # as there is an ICache miss and
12883 nop # the "data pattern" is present
12886 beq r0, r0, NextPage # to Next page
12890 This bug is present for div, divu, ddiv, and ddivu
12893 Workaround: For item 1), OS could make sure that the next page
12894 after the divide instruction is also mapped. For item 2), the
12895 compiler could make sure that the divide instruction is not in
12896 the branch delay slot."
12898 These processors have PRId values of 0x00004220 and 0x00004300 for
12899 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
12902 mips_output_division (const char *division, rtx *operands)
12907 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
12909 output_asm_insn (s, operands);
12912 if (TARGET_CHECK_ZERO_DIV)
12916 output_asm_insn (s, operands);
12917 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
12919 else if (GENERATE_DIVIDE_TRAPS)
12921 /* Avoid long replay penalty on load miss by putting the trap before
12924 output_asm_insn ("teq\t%2,%.,7", operands);
12927 output_asm_insn (s, operands);
12928 s = "teq\t%2,%.,7";
12933 output_asm_insn ("%(bne\t%2,%.,1f", operands);
12934 output_asm_insn (s, operands);
12935 s = "break\t7%)\n1:";
12941 /* Return true if IN_INSN is a multiply-add or multiply-subtract
12942 instruction and if OUT_INSN assigns to the accumulator operand. */
12945 mips_linked_madd_p (rtx out_insn, rtx in_insn)
12947 enum attr_accum_in accum_in;
12948 int accum_in_opnum;
12951 if (recog_memoized (in_insn) < 0)
12954 accum_in = get_attr_accum_in (in_insn);
12955 if (accum_in == ACCUM_IN_NONE)
12958 accum_in_opnum = accum_in - ACCUM_IN_0;
12960 extract_insn (in_insn);
12961 gcc_assert (accum_in_opnum < recog_data.n_operands);
12962 accum_in_op = recog_data.operand[accum_in_opnum];
12964 return reg_set_p (accum_in_op, out_insn);
12967 /* True if the dependency between OUT_INSN and IN_INSN is on the store
12968 data rather than the address. We need this because the cprestore
12969 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
12970 which causes the default routine to abort. We just return false
12974 mips_store_data_bypass_p (rtx out_insn, rtx in_insn)
12976 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
12979 return !store_data_bypass_p (out_insn, in_insn);
12983 /* Variables and flags used in scheduler hooks when tuning for
12987 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
12990 /* If true, then next ALU1/2 instruction will go to ALU1. */
12993 /* If true, then next FALU1/2 unstruction will go to FALU1. */
12996 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
12997 int alu1_core_unit_code;
12998 int alu2_core_unit_code;
12999 int falu1_core_unit_code;
13000 int falu2_core_unit_code;
13002 /* True if current cycle has a multi instruction.
13003 This flag is used in mips_ls2_dfa_post_advance_cycle. */
13004 bool cycle_has_multi_p;
13006 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
13007 These are used in mips_ls2_dfa_post_advance_cycle to initialize
13009 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
13010 instruction to go ALU1. */
13011 rtx alu1_turn_enabled_insn;
13012 rtx alu2_turn_enabled_insn;
13013 rtx falu1_turn_enabled_insn;
13014 rtx falu2_turn_enabled_insn;
13017 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
13018 dependencies have no cost, except on the 20Kc where output-dependence
13019 is treated like input-dependence. */
13022 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
13023 rtx dep ATTRIBUTE_UNUSED, int cost)
13025 if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT
13028 if (REG_NOTE_KIND (link) != 0)
13033 /* Return the number of instructions that can be issued per cycle. */
13036 mips_issue_rate (void)
13040 case PROCESSOR_74KC:
13041 case PROCESSOR_74KF2_1:
13042 case PROCESSOR_74KF1_1:
13043 case PROCESSOR_74KF3_2:
13044 /* The 74k is not strictly quad-issue cpu, but can be seen as one
13045 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
13046 but in reality only a maximum of 3 insns can be issued as
13047 floating-point loads and stores also require a slot in the
13049 case PROCESSOR_R10000:
13050 /* All R10K Processors are quad-issue (being the first MIPS
13051 processors to support this feature). */
13054 case PROCESSOR_20KC:
13055 case PROCESSOR_R4130:
13056 case PROCESSOR_R5400:
13057 case PROCESSOR_R5500:
13058 case PROCESSOR_R5900:
13059 case PROCESSOR_R7000:
13060 case PROCESSOR_R9000:
13061 case PROCESSOR_OCTEON:
13062 case PROCESSOR_OCTEON2:
13065 case PROCESSOR_SB1:
13066 case PROCESSOR_SB1A:
13067 /* This is actually 4, but we get better performance if we claim 3.
13068 This is partly because of unwanted speculative code motion with the
13069 larger number, and partly because in most common cases we can't
13070 reach the theoretical max of 4. */
13073 case PROCESSOR_LOONGSON_2E:
13074 case PROCESSOR_LOONGSON_2F:
13075 case PROCESSOR_LOONGSON_3A:
13078 case PROCESSOR_XLP:
13079 return (reload_completed ? 4 : 3);
13086 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
13089 mips_ls2_init_dfa_post_cycle_insn (void)
13092 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
13093 mips_ls2.alu1_turn_enabled_insn = get_insns ();
13097 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
13098 mips_ls2.alu2_turn_enabled_insn = get_insns ();
13102 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
13103 mips_ls2.falu1_turn_enabled_insn = get_insns ();
13107 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
13108 mips_ls2.falu2_turn_enabled_insn = get_insns ();
13111 mips_ls2.alu1_core_unit_code = get_cpu_unit_code ("ls2_alu1_core");
13112 mips_ls2.alu2_core_unit_code = get_cpu_unit_code ("ls2_alu2_core");
13113 mips_ls2.falu1_core_unit_code = get_cpu_unit_code ("ls2_falu1_core");
13114 mips_ls2.falu2_core_unit_code = get_cpu_unit_code ("ls2_falu2_core");
13117 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
13118 Init data used in mips_dfa_post_advance_cycle. */
13121 mips_init_dfa_post_cycle_insn (void)
13123 if (TUNE_LOONGSON_2EF)
13124 mips_ls2_init_dfa_post_cycle_insn ();
13127 /* Initialize STATE when scheduling for Loongson 2E/2F.
13128 Support round-robin dispatch scheme by enabling only one of
13129 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
13133 mips_ls2_dfa_post_advance_cycle (state_t state)
13135 if (cpu_unit_reservation_p (state, mips_ls2.alu1_core_unit_code))
13137 /* Though there are no non-pipelined ALU1 insns,
13138 we can get an instruction of type 'multi' before reload. */
13139 gcc_assert (mips_ls2.cycle_has_multi_p);
13140 mips_ls2.alu1_turn_p = false;
13143 mips_ls2.cycle_has_multi_p = false;
13145 if (cpu_unit_reservation_p (state, mips_ls2.alu2_core_unit_code))
13146 /* We have a non-pipelined alu instruction in the core,
13147 adjust round-robin counter. */
13148 mips_ls2.alu1_turn_p = true;
13150 if (mips_ls2.alu1_turn_p)
13152 if (state_transition (state, mips_ls2.alu1_turn_enabled_insn) >= 0)
13153 gcc_unreachable ();
13157 if (state_transition (state, mips_ls2.alu2_turn_enabled_insn) >= 0)
13158 gcc_unreachable ();
13161 if (cpu_unit_reservation_p (state, mips_ls2.falu1_core_unit_code))
13163 /* There are no non-pipelined FALU1 insns. */
13164 gcc_unreachable ();
13165 mips_ls2.falu1_turn_p = false;
13168 if (cpu_unit_reservation_p (state, mips_ls2.falu2_core_unit_code))
13169 /* We have a non-pipelined falu instruction in the core,
13170 adjust round-robin counter. */
13171 mips_ls2.falu1_turn_p = true;
13173 if (mips_ls2.falu1_turn_p)
13175 if (state_transition (state, mips_ls2.falu1_turn_enabled_insn) >= 0)
13176 gcc_unreachable ();
13180 if (state_transition (state, mips_ls2.falu2_turn_enabled_insn) >= 0)
13181 gcc_unreachable ();
13185 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
13186 This hook is being called at the start of each cycle. */
13189 mips_dfa_post_advance_cycle (void)
13191 if (TUNE_LOONGSON_2EF)
13192 mips_ls2_dfa_post_advance_cycle (curr_state);
13195 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
13196 be as wide as the scheduling freedom in the DFA. */
13199 mips_multipass_dfa_lookahead (void)
13201 /* Can schedule up to 4 of the 6 function units in any one cycle. */
13205 if (TUNE_LOONGSON_2EF || TUNE_LOONGSON_3A)
13214 /* Remove the instruction at index LOWER from ready queue READY and
13215 reinsert it in front of the instruction at index HIGHER. LOWER must
13219 mips_promote_ready (rtx *ready, int lower, int higher)
13224 new_head = ready[lower];
13225 for (i = lower; i < higher; i++)
13226 ready[i] = ready[i + 1];
13227 ready[i] = new_head;
13230 /* If the priority of the instruction at POS2 in the ready queue READY
13231 is within LIMIT units of that of the instruction at POS1, swap the
13232 instructions if POS2 is not already less than POS1. */
13235 mips_maybe_swap_ready (rtx *ready, int pos1, int pos2, int limit)
13238 && INSN_PRIORITY (ready[pos1]) + limit >= INSN_PRIORITY (ready[pos2]))
13242 temp = ready[pos1];
13243 ready[pos1] = ready[pos2];
13244 ready[pos2] = temp;
13248 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
13249 that may clobber hi or lo. */
13250 static rtx mips_macc_chains_last_hilo;
13252 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
13253 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
13256 mips_macc_chains_record (rtx insn)
13258 if (get_attr_may_clobber_hilo (insn))
13259 mips_macc_chains_last_hilo = insn;
13262 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
13263 has NREADY elements, looking for a multiply-add or multiply-subtract
13264 instruction that is cumulative with mips_macc_chains_last_hilo.
13265 If there is one, promote it ahead of anything else that might
13266 clobber hi or lo. */
13269 mips_macc_chains_reorder (rtx *ready, int nready)
13273 if (mips_macc_chains_last_hilo != 0)
13274 for (i = nready - 1; i >= 0; i--)
13275 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
13277 for (j = nready - 1; j > i; j--)
13278 if (recog_memoized (ready[j]) >= 0
13279 && get_attr_may_clobber_hilo (ready[j]))
13281 mips_promote_ready (ready, i, j);
13288 /* The last instruction to be scheduled. */
13289 static rtx vr4130_last_insn;
13291 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
13292 points to an rtx that is initially an instruction. Nullify the rtx
13293 if the instruction uses the value of register X. */
13296 vr4130_true_reg_dependence_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
13301 insn_ptr = (rtx *) data;
13304 && reg_referenced_p (x, PATTERN (*insn_ptr)))
13308 /* Return true if there is true register dependence between vr4130_last_insn
13312 vr4130_true_reg_dependence_p (rtx insn)
13314 note_stores (PATTERN (vr4130_last_insn),
13315 vr4130_true_reg_dependence_p_1, &insn);
13319 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
13320 the ready queue and that INSN2 is the instruction after it, return
13321 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
13322 in which INSN1 and INSN2 can probably issue in parallel, but for
13323 which (INSN2, INSN1) should be less sensitive to instruction
13324 alignment than (INSN1, INSN2). See 4130.md for more details. */
13327 vr4130_swap_insns_p (rtx insn1, rtx insn2)
13329 sd_iterator_def sd_it;
13332 /* Check for the following case:
13334 1) there is some other instruction X with an anti dependence on INSN1;
13335 2) X has a higher priority than INSN2; and
13336 3) X is an arithmetic instruction (and thus has no unit restrictions).
13338 If INSN1 is the last instruction blocking X, it would better to
13339 choose (INSN1, X) over (INSN2, INSN1). */
13340 FOR_EACH_DEP (insn1, SD_LIST_FORW, sd_it, dep)
13341 if (DEP_TYPE (dep) == REG_DEP_ANTI
13342 && INSN_PRIORITY (DEP_CON (dep)) > INSN_PRIORITY (insn2)
13343 && recog_memoized (DEP_CON (dep)) >= 0
13344 && get_attr_vr4130_class (DEP_CON (dep)) == VR4130_CLASS_ALU)
13347 if (vr4130_last_insn != 0
13348 && recog_memoized (insn1) >= 0
13349 && recog_memoized (insn2) >= 0)
13351 /* See whether INSN1 and INSN2 use different execution units,
13352 or if they are both ALU-type instructions. If so, they can
13353 probably execute in parallel. */
13354 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
13355 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
13356 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
13358 /* If only one of the instructions has a dependence on
13359 vr4130_last_insn, prefer to schedule the other one first. */
13360 bool dep1_p = vr4130_true_reg_dependence_p (insn1);
13361 bool dep2_p = vr4130_true_reg_dependence_p (insn2);
13362 if (dep1_p != dep2_p)
13365 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
13366 is not an ALU-type instruction and if INSN1 uses the same
13367 execution unit. (Note that if this condition holds, we already
13368 know that INSN2 uses a different execution unit.) */
13369 if (class1 != VR4130_CLASS_ALU
13370 && recog_memoized (vr4130_last_insn) >= 0
13371 && class1 == get_attr_vr4130_class (vr4130_last_insn))
13378 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
13379 queue with at least two instructions. Swap the first two if
13380 vr4130_swap_insns_p says that it could be worthwhile. */
13383 vr4130_reorder (rtx *ready, int nready)
13385 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
13386 mips_promote_ready (ready, nready - 2, nready - 1);
13389 /* Record whether last 74k AGEN instruction was a load or store. */
13390 static enum attr_type mips_last_74k_agen_insn = TYPE_UNKNOWN;
13392 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
13393 resets to TYPE_UNKNOWN state. */
13396 mips_74k_agen_init (rtx insn)
13398 if (!insn || CALL_P (insn) || JUMP_P (insn))
13399 mips_last_74k_agen_insn = TYPE_UNKNOWN;
13402 enum attr_type type = get_attr_type (insn);
13403 if (type == TYPE_LOAD || type == TYPE_STORE)
13404 mips_last_74k_agen_insn = type;
13408 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
13409 loads to be grouped together, and multiple stores to be grouped
13410 together. Swap things around in the ready queue to make this happen. */
13413 mips_74k_agen_reorder (rtx *ready, int nready)
13416 int store_pos, load_pos;
13421 for (i = nready - 1; i >= 0; i--)
13423 rtx insn = ready[i];
13424 if (USEFUL_INSN_P (insn))
13425 switch (get_attr_type (insn))
13428 if (store_pos == -1)
13433 if (load_pos == -1)
13442 if (load_pos == -1 || store_pos == -1)
13445 switch (mips_last_74k_agen_insn)
13448 /* Prefer to schedule loads since they have a higher latency. */
13450 /* Swap loads to the front of the queue. */
13451 mips_maybe_swap_ready (ready, load_pos, store_pos, 4);
13454 /* Swap stores to the front of the queue. */
13455 mips_maybe_swap_ready (ready, store_pos, load_pos, 4);
13462 /* Implement TARGET_SCHED_INIT. */
13465 mips_sched_init (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13466 int max_ready ATTRIBUTE_UNUSED)
13468 mips_macc_chains_last_hilo = 0;
13469 vr4130_last_insn = 0;
13470 mips_74k_agen_init (NULL_RTX);
13472 /* When scheduling for Loongson2, branch instructions go to ALU1,
13473 therefore basic block is most likely to start with round-robin counter
13474 pointed to ALU2. */
13475 mips_ls2.alu1_turn_p = false;
13476 mips_ls2.falu1_turn_p = true;
13479 /* Subroutine used by TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
13482 mips_sched_reorder_1 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13483 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
13485 if (!reload_completed
13486 && TUNE_MACC_CHAINS
13488 mips_macc_chains_reorder (ready, *nreadyp);
13490 if (reload_completed
13492 && !TARGET_VR4130_ALIGN
13494 vr4130_reorder (ready, *nreadyp);
13497 mips_74k_agen_reorder (ready, *nreadyp);
13500 /* Implement TARGET_SCHED_REORDER. */
13503 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13504 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
13506 mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle);
13507 return mips_issue_rate ();
13510 /* Implement TARGET_SCHED_REORDER2. */
13513 mips_sched_reorder2 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13514 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
13516 mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle);
13517 return cached_can_issue_more;
13520 /* Update round-robin counters for ALU1/2 and FALU1/2. */
13523 mips_ls2_variable_issue (rtx insn)
13525 if (mips_ls2.alu1_turn_p)
13527 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu1_core_unit_code))
13528 mips_ls2.alu1_turn_p = false;
13532 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu2_core_unit_code))
13533 mips_ls2.alu1_turn_p = true;
13536 if (mips_ls2.falu1_turn_p)
13538 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu1_core_unit_code))
13539 mips_ls2.falu1_turn_p = false;
13543 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu2_core_unit_code))
13544 mips_ls2.falu1_turn_p = true;
13547 if (recog_memoized (insn) >= 0)
13548 mips_ls2.cycle_has_multi_p |= (get_attr_type (insn) == TYPE_MULTI);
13551 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
13554 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13555 rtx insn, int more)
13557 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
13558 if (USEFUL_INSN_P (insn))
13560 if (get_attr_type (insn) != TYPE_GHOST)
13562 if (!reload_completed && TUNE_MACC_CHAINS)
13563 mips_macc_chains_record (insn);
13564 vr4130_last_insn = insn;
13566 mips_74k_agen_init (insn);
13567 else if (TUNE_LOONGSON_2EF)
13568 mips_ls2_variable_issue (insn);
13571 /* Instructions of type 'multi' should all be split before
13572 the second scheduling pass. */
13573 gcc_assert (!reload_completed
13574 || recog_memoized (insn) < 0
13575 || get_attr_type (insn) != TYPE_MULTI);
13577 cached_can_issue_more = more;
13581 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
13582 return the first operand of the associated PREF or PREFX insn. */
13585 mips_prefetch_cookie (rtx write, rtx locality)
13587 /* store_streamed / load_streamed. */
13588 if (INTVAL (locality) <= 0)
13589 return GEN_INT (INTVAL (write) + 4);
13591 /* store / load. */
13592 if (INTVAL (locality) <= 2)
13595 /* store_retained / load_retained. */
13596 return GEN_INT (INTVAL (write) + 6);
13599 /* Flags that indicate when a built-in function is available.
13601 BUILTIN_AVAIL_NON_MIPS16
13602 The function is available on the current target, but only
13603 in non-MIPS16 mode. */
13604 #define BUILTIN_AVAIL_NON_MIPS16 1
13606 /* Declare an availability predicate for built-in functions that
13607 require non-MIPS16 mode and also require COND to be true.
13608 NAME is the main part of the predicate's name. */
13609 #define AVAIL_NON_MIPS16(NAME, COND) \
13610 static unsigned int \
13611 mips_builtin_avail_##NAME (void) \
13613 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
13616 /* This structure describes a single built-in function. */
13617 struct mips_builtin_description {
13618 /* The code of the main .md file instruction. See mips_builtin_type
13619 for more information. */
13620 enum insn_code icode;
13622 /* The floating-point comparison code to use with ICODE, if any. */
13623 enum mips_fp_condition cond;
13625 /* The name of the built-in function. */
13628 /* Specifies how the function should be expanded. */
13629 enum mips_builtin_type builtin_type;
13631 /* The function's prototype. */
13632 enum mips_function_type function_type;
13634 /* Whether the function is available. */
13635 unsigned int (*avail) (void);
13638 AVAIL_NON_MIPS16 (paired_single, TARGET_PAIRED_SINGLE_FLOAT)
13639 AVAIL_NON_MIPS16 (sb1_paired_single, TARGET_SB1 && TARGET_PAIRED_SINGLE_FLOAT)
13640 AVAIL_NON_MIPS16 (mips3d, TARGET_MIPS3D)
13641 AVAIL_NON_MIPS16 (dsp, TARGET_DSP)
13642 AVAIL_NON_MIPS16 (dspr2, TARGET_DSPR2)
13643 AVAIL_NON_MIPS16 (dsp_32, !TARGET_64BIT && TARGET_DSP)
13644 AVAIL_NON_MIPS16 (dsp_64, TARGET_64BIT && TARGET_DSP)
13645 AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2)
13646 AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS)
13647 AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
13649 /* Construct a mips_builtin_description from the given arguments.
13651 INSN is the name of the associated instruction pattern, without the
13652 leading CODE_FOR_mips_.
13654 CODE is the floating-point condition code associated with the
13655 function. It can be 'f' if the field is not applicable.
13657 NAME is the name of the function itself, without the leading
13660 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
13662 AVAIL is the name of the availability predicate, without the leading
13663 mips_builtin_avail_. */
13664 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
13665 FUNCTION_TYPE, AVAIL) \
13666 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
13667 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
13668 mips_builtin_avail_ ## AVAIL }
13670 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
13671 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
13672 are as for MIPS_BUILTIN. */
13673 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
13674 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
13676 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
13677 are subject to mips_builtin_avail_<AVAIL>. */
13678 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
13679 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
13680 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
13681 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
13682 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
13684 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
13685 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
13686 while the any and all forms are subject to mips_builtin_avail_mips3d. */
13687 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
13688 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
13689 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
13691 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
13692 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
13694 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
13695 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
13697 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
13698 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
13701 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
13702 are subject to mips_builtin_avail_mips3d. */
13703 #define CMP_4S_BUILTINS(INSN, COND) \
13704 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
13705 MIPS_BUILTIN_CMP_ANY, \
13706 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
13707 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
13708 MIPS_BUILTIN_CMP_ALL, \
13709 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
13711 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
13712 instruction requires mips_builtin_avail_<AVAIL>. */
13713 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
13714 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
13715 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
13717 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
13718 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
13721 /* Define all the built-in functions related to C.cond.fmt condition COND. */
13722 #define CMP_BUILTINS(COND) \
13723 MOVTF_BUILTINS (c, COND, paired_single), \
13724 MOVTF_BUILTINS (cabs, COND, mips3d), \
13725 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
13726 CMP_PS_BUILTINS (c, COND, paired_single), \
13727 CMP_PS_BUILTINS (cabs, COND, mips3d), \
13728 CMP_4S_BUILTINS (c, COND), \
13729 CMP_4S_BUILTINS (cabs, COND)
13731 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
13732 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
13733 and AVAIL are as for MIPS_BUILTIN. */
13734 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
13735 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
13736 FUNCTION_TYPE, AVAIL)
13738 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
13739 branch instruction. AVAIL is as for MIPS_BUILTIN. */
13740 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
13741 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
13742 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
13744 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
13745 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
13746 builtin_description field. */
13747 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
13748 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
13749 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
13750 FUNCTION_TYPE, mips_builtin_avail_loongson }
13752 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
13753 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
13754 builtin_description field. */
13755 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
13756 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
13758 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
13759 We use functions of this form when the same insn can be usefully applied
13760 to more than one datatype. */
13761 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
13762 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
13764 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
13765 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
13766 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
13767 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
13768 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
13769 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
13770 #define CODE_FOR_mips_mult CODE_FOR_mulsidi3_32bit
13771 #define CODE_FOR_mips_multu CODE_FOR_umulsidi3_32bit
13773 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
13774 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
13775 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
13776 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
13777 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
13778 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
13779 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
13780 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
13781 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
13782 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
13783 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
13784 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
13785 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
13786 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
13787 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
13788 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
13789 #define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3
13790 #define CODE_FOR_loongson_psllh CODE_FOR_ashlv4hi3
13791 #define CODE_FOR_loongson_psllw CODE_FOR_ashlv2si3
13792 #define CODE_FOR_loongson_psrlh CODE_FOR_lshrv4hi3
13793 #define CODE_FOR_loongson_psrlw CODE_FOR_lshrv2si3
13794 #define CODE_FOR_loongson_psrah CODE_FOR_ashrv4hi3
13795 #define CODE_FOR_loongson_psraw CODE_FOR_ashrv2si3
13796 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
13797 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
13798 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
13799 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
13800 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
13801 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
13802 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
13804 static const struct mips_builtin_description mips_builtins[] = {
13805 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13806 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13807 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13808 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13809 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, paired_single),
13810 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, paired_single),
13811 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, paired_single),
13812 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, paired_single),
13814 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT, paired_single),
13815 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13816 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13817 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
13818 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, mips3d),
13820 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, mips3d),
13821 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, mips3d),
13822 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
13823 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
13824 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
13825 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13827 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, mips3d),
13828 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, mips3d),
13829 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
13830 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
13831 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
13832 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13834 MIPS_FP_CONDITIONS (CMP_BUILTINS),
13836 /* Built-in functions for the SB-1 processor. */
13837 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, sb1_paired_single),
13839 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
13840 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13841 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13842 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
13843 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13844 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13845 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13846 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13847 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
13848 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13849 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13850 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, dsp),
13851 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, dsp),
13852 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, dsp),
13853 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, dsp),
13854 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, dsp),
13855 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, dsp),
13856 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
13857 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
13858 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
13859 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
13860 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, dsp),
13861 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, dsp),
13862 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
13863 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
13864 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
13865 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
13866 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
13867 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
13868 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
13869 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
13870 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
13871 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
13872 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
13873 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
13874 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
13875 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
13876 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
13877 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, dsp),
13878 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
13879 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
13880 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13881 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
13882 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
13883 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, dsp),
13884 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, dsp),
13885 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, dsp),
13886 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, dsp),
13887 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
13888 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
13889 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
13890 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
13891 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
13892 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
13893 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
13894 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
13895 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
13896 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13897 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13898 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13899 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, dsp),
13900 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, dsp),
13901 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_POINTER_SI, dsp),
13902 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_POINTER_SI, dsp),
13903 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_POINTER_SI, dsp),
13904 BPOSGE_BUILTIN (32, dsp),
13906 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
13907 DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, dspr2),
13908 DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13909 DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13910 DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
13911 DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
13912 DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
13913 DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
13914 DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
13915 DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
13916 DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
13917 DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13918 DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13919 DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13920 DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13921 DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13922 DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dspr2),
13923 DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
13924 DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
13925 DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
13926 DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
13927 DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
13928 DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, dspr2),
13929 DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13930 DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13931 DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
13932 DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
13933 DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13934 DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13935 DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13936 DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13937 DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13938 DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13939 DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13940 DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13942 /* Built-in functions for the DSP ASE (32-bit only). */
13943 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
13944 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
13945 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
13946 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
13947 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13948 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13949 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13950 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
13951 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
13952 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13953 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13954 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13955 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13956 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
13957 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
13958 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
13959 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, dsp_32),
13960 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, dsp_32),
13961 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, dsp_32),
13962 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, dsp_32),
13963 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, dsp_32),
13964 DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
13965 DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32),
13966 DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
13967 DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32),
13968 DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, dsp_32),
13969 DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, dsp_32),
13971 /* Built-in functions for the DSP ASE (64-bit only). */
13972 DIRECT_BUILTIN (ldx, MIPS_DI_FTYPE_POINTER_SI, dsp_64),
13974 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
13975 DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13976 DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13977 DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13978 DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13979 DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13980 DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13981 DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13982 DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13983 DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13985 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
13986 LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI),
13987 LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI),
13988 LOONGSON_BUILTIN (packushb, MIPS_UV8QI_FTYPE_UV4HI_UV4HI),
13989 LOONGSON_BUILTIN_SUFFIX (paddw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13990 LOONGSON_BUILTIN_SUFFIX (paddh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13991 LOONGSON_BUILTIN_SUFFIX (paddb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13992 LOONGSON_BUILTIN_SUFFIX (paddw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13993 LOONGSON_BUILTIN_SUFFIX (paddh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13994 LOONGSON_BUILTIN_SUFFIX (paddb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13995 LOONGSON_BUILTIN_SUFFIX (paddd, u, MIPS_UDI_FTYPE_UDI_UDI),
13996 LOONGSON_BUILTIN_SUFFIX (paddd, s, MIPS_DI_FTYPE_DI_DI),
13997 LOONGSON_BUILTIN (paddsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13998 LOONGSON_BUILTIN (paddsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
13999 LOONGSON_BUILTIN (paddush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14000 LOONGSON_BUILTIN (paddusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14001 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_ud, MIPS_UDI_FTYPE_UDI_UDI),
14002 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_uw, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14003 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_uh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14004 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_ub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14005 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_sd, MIPS_DI_FTYPE_DI_DI),
14006 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_sw, MIPS_V2SI_FTYPE_V2SI_V2SI),
14007 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_sh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14008 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_sb, MIPS_V8QI_FTYPE_V8QI_V8QI),
14009 LOONGSON_BUILTIN (pavgh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14010 LOONGSON_BUILTIN (pavgb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14011 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14012 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14013 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14014 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14015 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14016 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14017 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14018 LOONGSON_BUILTIN_SUFFIX (pcmpgth, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14019 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14020 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14021 LOONGSON_BUILTIN_SUFFIX (pcmpgth, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14022 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14023 LOONGSON_BUILTIN_SUFFIX (pextrh, u, MIPS_UV4HI_FTYPE_UV4HI_USI),
14024 LOONGSON_BUILTIN_SUFFIX (pextrh, s, MIPS_V4HI_FTYPE_V4HI_USI),
14025 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14026 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14027 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14028 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14029 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14030 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14031 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14032 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14033 LOONGSON_BUILTIN (pmaddhw, MIPS_V2SI_FTYPE_V4HI_V4HI),
14034 LOONGSON_BUILTIN (pmaxsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14035 LOONGSON_BUILTIN (pmaxub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14036 LOONGSON_BUILTIN (pminsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14037 LOONGSON_BUILTIN (pminub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14038 LOONGSON_BUILTIN_SUFFIX (pmovmskb, u, MIPS_UV8QI_FTYPE_UV8QI),
14039 LOONGSON_BUILTIN_SUFFIX (pmovmskb, s, MIPS_V8QI_FTYPE_V8QI),
14040 LOONGSON_BUILTIN (pmulhuh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14041 LOONGSON_BUILTIN (pmulhh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14042 LOONGSON_BUILTIN (pmullh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14043 LOONGSON_BUILTIN (pmuluw, MIPS_UDI_FTYPE_UV2SI_UV2SI),
14044 LOONGSON_BUILTIN (pasubub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14045 LOONGSON_BUILTIN (biadd, MIPS_UV4HI_FTYPE_UV8QI),
14046 LOONGSON_BUILTIN (psadbh, MIPS_UV4HI_FTYPE_UV8QI_UV8QI),
14047 LOONGSON_BUILTIN_SUFFIX (pshufh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
14048 LOONGSON_BUILTIN_SUFFIX (pshufh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
14049 LOONGSON_BUILTIN_SUFFIX (psllh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
14050 LOONGSON_BUILTIN_SUFFIX (psllh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
14051 LOONGSON_BUILTIN_SUFFIX (psllw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
14052 LOONGSON_BUILTIN_SUFFIX (psllw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
14053 LOONGSON_BUILTIN_SUFFIX (psrah, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
14054 LOONGSON_BUILTIN_SUFFIX (psrah, s, MIPS_V4HI_FTYPE_V4HI_UQI),
14055 LOONGSON_BUILTIN_SUFFIX (psraw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
14056 LOONGSON_BUILTIN_SUFFIX (psraw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
14057 LOONGSON_BUILTIN_SUFFIX (psrlh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
14058 LOONGSON_BUILTIN_SUFFIX (psrlh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
14059 LOONGSON_BUILTIN_SUFFIX (psrlw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
14060 LOONGSON_BUILTIN_SUFFIX (psrlw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
14061 LOONGSON_BUILTIN_SUFFIX (psubw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14062 LOONGSON_BUILTIN_SUFFIX (psubh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14063 LOONGSON_BUILTIN_SUFFIX (psubb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14064 LOONGSON_BUILTIN_SUFFIX (psubw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14065 LOONGSON_BUILTIN_SUFFIX (psubh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14066 LOONGSON_BUILTIN_SUFFIX (psubb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14067 LOONGSON_BUILTIN_SUFFIX (psubd, u, MIPS_UDI_FTYPE_UDI_UDI),
14068 LOONGSON_BUILTIN_SUFFIX (psubd, s, MIPS_DI_FTYPE_DI_DI),
14069 LOONGSON_BUILTIN (psubsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14070 LOONGSON_BUILTIN (psubsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
14071 LOONGSON_BUILTIN (psubush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14072 LOONGSON_BUILTIN (psubusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14073 LOONGSON_BUILTIN_SUFFIX (punpckhbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14074 LOONGSON_BUILTIN_SUFFIX (punpckhhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14075 LOONGSON_BUILTIN_SUFFIX (punpckhwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14076 LOONGSON_BUILTIN_SUFFIX (punpckhbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14077 LOONGSON_BUILTIN_SUFFIX (punpckhhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14078 LOONGSON_BUILTIN_SUFFIX (punpckhwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14079 LOONGSON_BUILTIN_SUFFIX (punpcklbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14080 LOONGSON_BUILTIN_SUFFIX (punpcklhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14081 LOONGSON_BUILTIN_SUFFIX (punpcklwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14082 LOONGSON_BUILTIN_SUFFIX (punpcklbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14083 LOONGSON_BUILTIN_SUFFIX (punpcklhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14084 LOONGSON_BUILTIN_SUFFIX (punpcklwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14086 /* Sundry other built-in functions. */
14087 DIRECT_NO_TARGET_BUILTIN (cache, MIPS_VOID_FTYPE_SI_CVPOINTER, cache)
14090 /* Index I is the function declaration for mips_builtins[I], or null if the
14091 function isn't defined on this target. */
14092 static GTY(()) tree mips_builtin_decls[ARRAY_SIZE (mips_builtins)];
14094 /* MODE is a vector mode whose elements have type TYPE. Return the type
14095 of the vector itself. */
14098 mips_builtin_vector_type (tree type, enum machine_mode mode)
14100 static tree types[2 * (int) MAX_MACHINE_MODE];
14103 mode_index = (int) mode;
14105 if (TREE_CODE (type) == INTEGER_TYPE && TYPE_UNSIGNED (type))
14106 mode_index += MAX_MACHINE_MODE;
14108 if (types[mode_index] == NULL_TREE)
14109 types[mode_index] = build_vector_type_for_mode (type, mode);
14110 return types[mode_index];
14113 /* Return a type for 'const volatile void *'. */
14116 mips_build_cvpointer_type (void)
14120 if (cache == NULL_TREE)
14121 cache = build_pointer_type (build_qualified_type
14123 TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE));
14127 /* Source-level argument types. */
14128 #define MIPS_ATYPE_VOID void_type_node
14129 #define MIPS_ATYPE_INT integer_type_node
14130 #define MIPS_ATYPE_POINTER ptr_type_node
14131 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
14133 /* Standard mode-based argument types. */
14134 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
14135 #define MIPS_ATYPE_SI intSI_type_node
14136 #define MIPS_ATYPE_USI unsigned_intSI_type_node
14137 #define MIPS_ATYPE_DI intDI_type_node
14138 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
14139 #define MIPS_ATYPE_SF float_type_node
14140 #define MIPS_ATYPE_DF double_type_node
14142 /* Vector argument types. */
14143 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
14144 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
14145 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
14146 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
14147 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
14148 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
14149 #define MIPS_ATYPE_UV2SI \
14150 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
14151 #define MIPS_ATYPE_UV4HI \
14152 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
14153 #define MIPS_ATYPE_UV8QI \
14154 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
14156 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
14157 their associated MIPS_ATYPEs. */
14158 #define MIPS_FTYPE_ATYPES1(A, B) \
14159 MIPS_ATYPE_##A, MIPS_ATYPE_##B
14161 #define MIPS_FTYPE_ATYPES2(A, B, C) \
14162 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
14164 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
14165 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
14167 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
14168 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
14171 /* Return the function type associated with function prototype TYPE. */
14174 mips_build_function_type (enum mips_function_type type)
14176 static tree types[(int) MIPS_MAX_FTYPE_MAX];
14178 if (types[(int) type] == NULL_TREE)
14181 #define DEF_MIPS_FTYPE(NUM, ARGS) \
14182 case MIPS_FTYPE_NAME##NUM ARGS: \
14183 types[(int) type] \
14184 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
14187 #include "config/mips/mips-ftypes.def"
14188 #undef DEF_MIPS_FTYPE
14190 gcc_unreachable ();
14193 return types[(int) type];
14196 /* Implement TARGET_INIT_BUILTINS. */
14199 mips_init_builtins (void)
14201 const struct mips_builtin_description *d;
14204 /* Iterate through all of the bdesc arrays, initializing all of the
14205 builtin functions. */
14206 for (i = 0; i < ARRAY_SIZE (mips_builtins); i++)
14208 d = &mips_builtins[i];
14210 mips_builtin_decls[i]
14211 = add_builtin_function (d->name,
14212 mips_build_function_type (d->function_type),
14213 i, BUILT_IN_MD, NULL, NULL);
14217 /* Implement TARGET_BUILTIN_DECL. */
14220 mips_builtin_decl (unsigned int code, bool initialize_p ATTRIBUTE_UNUSED)
14222 if (code >= ARRAY_SIZE (mips_builtins))
14223 return error_mark_node;
14224 return mips_builtin_decls[code];
14227 /* Take argument ARGNO from EXP's argument list and convert it into
14228 an expand operand. Store the operand in *OP. */
14231 mips_prepare_builtin_arg (struct expand_operand *op, tree exp,
14232 unsigned int argno)
14237 arg = CALL_EXPR_ARG (exp, argno);
14238 value = expand_normal (arg);
14239 create_input_operand (op, value, TYPE_MODE (TREE_TYPE (arg)));
14242 /* Expand instruction ICODE as part of a built-in function sequence.
14243 Use the first NOPS elements of OPS as the instruction's operands.
14244 HAS_TARGET_P is true if operand 0 is a target; it is false if the
14245 instruction has no target.
14247 Return the target rtx if HAS_TARGET_P, otherwise return const0_rtx. */
14250 mips_expand_builtin_insn (enum insn_code icode, unsigned int nops,
14251 struct expand_operand *ops, bool has_target_p)
14253 if (!maybe_expand_insn (icode, nops, ops))
14255 error ("invalid argument to built-in function");
14256 return has_target_p ? gen_reg_rtx (ops[0].mode) : const0_rtx;
14258 return has_target_p ? ops[0].value : const0_rtx;
14261 /* Expand a floating-point comparison for built-in function call EXP.
14262 The first NARGS arguments are the values to be compared. ICODE is
14263 the .md pattern that does the comparison and COND is the condition
14264 that is being tested. Return an rtx for the result. */
14267 mips_expand_builtin_compare_1 (enum insn_code icode,
14268 enum mips_fp_condition cond,
14269 tree exp, int nargs)
14271 struct expand_operand ops[MAX_RECOG_OPERANDS];
14275 /* The instruction should have a target operand, an operand for each
14276 argument, and an operand for COND. */
14277 gcc_assert (nargs + 2 == insn_data[(int) icode].n_generator_args);
14279 output = mips_allocate_fcc (insn_data[(int) icode].operand[0].mode);
14281 create_fixed_operand (&ops[opno++], output);
14282 for (argno = 0; argno < nargs; argno++)
14283 mips_prepare_builtin_arg (&ops[opno++], exp, argno);
14284 create_integer_operand (&ops[opno++], (int) cond);
14285 return mips_expand_builtin_insn (icode, opno, ops, true);
14288 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
14289 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
14290 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
14291 suggests a good place to put the result. */
14294 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
14297 struct expand_operand ops[MAX_RECOG_OPERANDS];
14300 /* Map any target to operand 0. */
14303 create_output_operand (&ops[opno++], target, TYPE_MODE (TREE_TYPE (exp)));
14305 /* Map the arguments to the other operands. */
14306 gcc_assert (opno + call_expr_nargs (exp)
14307 == insn_data[icode].n_generator_args);
14308 for (argno = 0; argno < call_expr_nargs (exp); argno++)
14309 mips_prepare_builtin_arg (&ops[opno++], exp, argno);
14311 return mips_expand_builtin_insn (icode, opno, ops, has_target_p);
14314 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
14315 function; TYPE says which. EXP is the CALL_EXPR that calls the
14316 function, ICODE is the instruction that should be used to compare
14317 the first two arguments, and COND is the condition it should test.
14318 TARGET, if nonnull, suggests a good place to put the result. */
14321 mips_expand_builtin_movtf (enum mips_builtin_type type,
14322 enum insn_code icode, enum mips_fp_condition cond,
14323 rtx target, tree exp)
14325 struct expand_operand ops[4];
14328 cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp, 2);
14329 create_output_operand (&ops[0], target, TYPE_MODE (TREE_TYPE (exp)));
14330 if (type == MIPS_BUILTIN_MOVT)
14332 mips_prepare_builtin_arg (&ops[2], exp, 2);
14333 mips_prepare_builtin_arg (&ops[1], exp, 3);
14337 mips_prepare_builtin_arg (&ops[1], exp, 2);
14338 mips_prepare_builtin_arg (&ops[2], exp, 3);
14340 create_fixed_operand (&ops[3], cmp_result);
14341 return mips_expand_builtin_insn (CODE_FOR_mips_cond_move_tf_ps,
14345 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
14346 into TARGET otherwise. Return TARGET. */
14349 mips_builtin_branch_and_move (rtx condition, rtx target,
14350 rtx value_if_true, rtx value_if_false)
14352 rtx true_label, done_label;
14354 true_label = gen_label_rtx ();
14355 done_label = gen_label_rtx ();
14357 /* First assume that CONDITION is false. */
14358 mips_emit_move (target, value_if_false);
14360 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
14361 emit_jump_insn (gen_condjump (condition, true_label));
14362 emit_jump_insn (gen_jump (done_label));
14365 /* Fix TARGET if CONDITION is true. */
14366 emit_label (true_label);
14367 mips_emit_move (target, value_if_true);
14369 emit_label (done_label);
14373 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
14374 the CALL_EXPR that calls the function, ICODE is the code of the
14375 comparison instruction, and COND is the condition it should test.
14376 TARGET, if nonnull, suggests a good place to put the boolean result. */
14379 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
14380 enum insn_code icode, enum mips_fp_condition cond,
14381 rtx target, tree exp)
14383 rtx offset, condition, cmp_result;
14385 if (target == 0 || GET_MODE (target) != SImode)
14386 target = gen_reg_rtx (SImode);
14387 cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp,
14388 call_expr_nargs (exp));
14390 /* If the comparison sets more than one register, we define the result
14391 to be 0 if all registers are false and -1 if all registers are true.
14392 The value of the complete result is indeterminate otherwise. */
14393 switch (builtin_type)
14395 case MIPS_BUILTIN_CMP_ALL:
14396 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
14397 return mips_builtin_branch_and_move (condition, target,
14398 const0_rtx, const1_rtx);
14400 case MIPS_BUILTIN_CMP_UPPER:
14401 case MIPS_BUILTIN_CMP_LOWER:
14402 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
14403 condition = gen_single_cc (cmp_result, offset);
14404 return mips_builtin_branch_and_move (condition, target,
14405 const1_rtx, const0_rtx);
14408 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
14409 return mips_builtin_branch_and_move (condition, target,
14410 const1_rtx, const0_rtx);
14414 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
14415 if nonnull, suggests a good place to put the boolean result. */
14418 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
14420 rtx condition, cmp_result;
14423 if (target == 0 || GET_MODE (target) != SImode)
14424 target = gen_reg_rtx (SImode);
14426 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
14428 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
14433 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
14434 return mips_builtin_branch_and_move (condition, target,
14435 const1_rtx, const0_rtx);
14438 /* Implement TARGET_EXPAND_BUILTIN. */
14441 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
14442 enum machine_mode mode, int ignore)
14445 unsigned int fcode, avail;
14446 const struct mips_builtin_description *d;
14448 fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
14449 fcode = DECL_FUNCTION_CODE (fndecl);
14450 gcc_assert (fcode < ARRAY_SIZE (mips_builtins));
14451 d = &mips_builtins[fcode];
14452 avail = d->avail ();
14453 gcc_assert (avail != 0);
14456 error ("built-in function %qE not supported for MIPS16",
14457 DECL_NAME (fndecl));
14458 return ignore ? const0_rtx : CONST0_RTX (mode);
14460 switch (d->builtin_type)
14462 case MIPS_BUILTIN_DIRECT:
14463 return mips_expand_builtin_direct (d->icode, target, exp, true);
14465 case MIPS_BUILTIN_DIRECT_NO_TARGET:
14466 return mips_expand_builtin_direct (d->icode, target, exp, false);
14468 case MIPS_BUILTIN_MOVT:
14469 case MIPS_BUILTIN_MOVF:
14470 return mips_expand_builtin_movtf (d->builtin_type, d->icode,
14471 d->cond, target, exp);
14473 case MIPS_BUILTIN_CMP_ANY:
14474 case MIPS_BUILTIN_CMP_ALL:
14475 case MIPS_BUILTIN_CMP_UPPER:
14476 case MIPS_BUILTIN_CMP_LOWER:
14477 case MIPS_BUILTIN_CMP_SINGLE:
14478 return mips_expand_builtin_compare (d->builtin_type, d->icode,
14479 d->cond, target, exp);
14481 case MIPS_BUILTIN_BPOSGE32:
14482 return mips_expand_builtin_bposge (d->builtin_type, target);
14484 gcc_unreachable ();
14487 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
14488 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
14489 struct mips16_constant {
14490 struct mips16_constant *next;
14493 enum machine_mode mode;
14496 /* Information about an incomplete MIPS16 constant pool. FIRST is the
14497 first constant, HIGHEST_ADDRESS is the highest address that the first
14498 byte of the pool can have, and INSN_ADDRESS is the current instruction
14500 struct mips16_constant_pool {
14501 struct mips16_constant *first;
14502 int highest_address;
14506 /* Add constant VALUE to POOL and return its label. MODE is the
14507 value's mode (used for CONST_INTs, etc.). */
14510 mips16_add_constant (struct mips16_constant_pool *pool,
14511 rtx value, enum machine_mode mode)
14513 struct mips16_constant **p, *c;
14514 bool first_of_size_p;
14516 /* See whether the constant is already in the pool. If so, return the
14517 existing label, otherwise leave P pointing to the place where the
14518 constant should be added.
14520 Keep the pool sorted in increasing order of mode size so that we can
14521 reduce the number of alignments needed. */
14522 first_of_size_p = true;
14523 for (p = &pool->first; *p != 0; p = &(*p)->next)
14525 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
14526 return (*p)->label;
14527 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
14529 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
14530 first_of_size_p = false;
14533 /* In the worst case, the constant needed by the earliest instruction
14534 will end up at the end of the pool. The entire pool must then be
14535 accessible from that instruction.
14537 When adding the first constant, set the pool's highest address to
14538 the address of the first out-of-range byte. Adjust this address
14539 downwards each time a new constant is added. */
14540 if (pool->first == 0)
14541 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
14542 of the instruction with the lowest two bits clear. The base PC
14543 value for LDPC has the lowest three bits clear. Assume the worst
14544 case here; namely that the PC-relative instruction occupies the
14545 last 2 bytes in an aligned word. */
14546 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
14547 pool->highest_address -= GET_MODE_SIZE (mode);
14548 if (first_of_size_p)
14549 /* Take into account the worst possible padding due to alignment. */
14550 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
14552 /* Create a new entry. */
14553 c = XNEW (struct mips16_constant);
14556 c->label = gen_label_rtx ();
14563 /* Output constant VALUE after instruction INSN and return the last
14564 instruction emitted. MODE is the mode of the constant. */
14567 mips16_emit_constants_1 (enum machine_mode mode, rtx value, rtx insn)
14569 if (SCALAR_INT_MODE_P (mode) || ALL_SCALAR_FIXED_POINT_MODE_P (mode))
14571 rtx size = GEN_INT (GET_MODE_SIZE (mode));
14572 return emit_insn_after (gen_consttable_int (value, size), insn);
14575 if (SCALAR_FLOAT_MODE_P (mode))
14576 return emit_insn_after (gen_consttable_float (value), insn);
14578 if (VECTOR_MODE_P (mode))
14582 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
14583 insn = mips16_emit_constants_1 (GET_MODE_INNER (mode),
14584 CONST_VECTOR_ELT (value, i), insn);
14588 gcc_unreachable ();
14591 /* Dump out the constants in CONSTANTS after INSN. */
14594 mips16_emit_constants (struct mips16_constant *constants, rtx insn)
14596 struct mips16_constant *c, *next;
14600 for (c = constants; c != NULL; c = next)
14602 /* If necessary, increase the alignment of PC. */
14603 if (align < GET_MODE_SIZE (c->mode))
14605 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
14606 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
14608 align = GET_MODE_SIZE (c->mode);
14610 insn = emit_label_after (c->label, insn);
14611 insn = mips16_emit_constants_1 (c->mode, c->value, insn);
14617 emit_barrier_after (insn);
14620 /* Return the length of instruction INSN. */
14623 mips16_insn_length (rtx insn)
14625 if (JUMP_TABLE_DATA_P (insn))
14627 rtx body = PATTERN (insn);
14628 if (GET_CODE (body) == ADDR_VEC)
14629 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
14630 else if (GET_CODE (body) == ADDR_DIFF_VEC)
14631 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
14633 gcc_unreachable ();
14635 return get_attr_length (insn);
14638 /* If *X is a symbolic constant that refers to the constant pool, add
14639 the constant to POOL and rewrite *X to use the constant's label. */
14642 mips16_rewrite_pool_constant (struct mips16_constant_pool *pool, rtx *x)
14644 rtx base, offset, label;
14646 split_const (*x, &base, &offset);
14647 if (GET_CODE (base) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (base))
14649 label = mips16_add_constant (pool, copy_rtx (get_pool_constant (base)),
14650 get_pool_mode (base));
14651 base = gen_rtx_LABEL_REF (Pmode, label);
14652 *x = mips_unspec_address_offset (base, offset, SYMBOL_PC_RELATIVE);
14656 /* This structure is used to communicate with mips16_rewrite_pool_refs.
14657 INSN is the instruction we're rewriting and POOL points to the current
14659 struct mips16_rewrite_pool_refs_info {
14661 struct mips16_constant_pool *pool;
14664 /* Rewrite *X so that constant pool references refer to the constant's
14665 label instead. DATA points to a mips16_rewrite_pool_refs_info
14669 mips16_rewrite_pool_refs (rtx *x, void *data)
14671 struct mips16_rewrite_pool_refs_info *info =
14672 (struct mips16_rewrite_pool_refs_info *) data;
14674 if (force_to_mem_operand (*x, Pmode))
14676 rtx mem = force_const_mem (GET_MODE (*x), *x);
14677 validate_change (info->insn, x, mem, false);
14682 mips16_rewrite_pool_constant (info->pool, &XEXP (*x, 0));
14686 /* Don't rewrite the __mips16_rdwr symbol. */
14687 if (GET_CODE (*x) == UNSPEC && XINT (*x, 1) == UNSPEC_TLS_GET_TP)
14690 if (TARGET_MIPS16_TEXT_LOADS)
14691 mips16_rewrite_pool_constant (info->pool, x);
14693 return GET_CODE (*x) == CONST ? -1 : 0;
14696 /* Return whether CFG is used in mips_reorg. */
14699 mips_cfg_in_reorg (void)
14701 return (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
14702 || TARGET_RELAX_PIC_CALLS);
14705 /* Build MIPS16 constant pools. Split the instructions if SPLIT_P,
14706 otherwise assume that they are already split. */
14709 mips16_lay_out_constants (bool split_p)
14711 struct mips16_constant_pool pool;
14712 struct mips16_rewrite_pool_refs_info info;
14715 if (!TARGET_MIPS16_PCREL_LOADS)
14720 if (mips_cfg_in_reorg ())
14721 split_all_insns ();
14723 split_all_insns_noflow ();
14726 memset (&pool, 0, sizeof (pool));
14727 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
14729 /* Rewrite constant pool references in INSN. */
14730 if (USEFUL_INSN_P (insn))
14734 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &info);
14737 pool.insn_address += mips16_insn_length (insn);
14739 if (pool.first != NULL)
14741 /* If there are no natural barriers between the first user of
14742 the pool and the highest acceptable address, we'll need to
14743 create a new instruction to jump around the constant pool.
14744 In the worst case, this instruction will be 4 bytes long.
14746 If it's too late to do this transformation after INSN,
14747 do it immediately before INSN. */
14748 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
14752 label = gen_label_rtx ();
14754 jump = emit_jump_insn_before (gen_jump (label), insn);
14755 JUMP_LABEL (jump) = label;
14756 LABEL_NUSES (label) = 1;
14757 barrier = emit_barrier_after (jump);
14759 emit_label_after (label, barrier);
14760 pool.insn_address += 4;
14763 /* See whether the constant pool is now out of range of the first
14764 user. If so, output the constants after the previous barrier.
14765 Note that any instructions between BARRIER and INSN (inclusive)
14766 will use negative offsets to refer to the pool. */
14767 if (pool.insn_address > pool.highest_address)
14769 mips16_emit_constants (pool.first, barrier);
14773 else if (BARRIER_P (insn))
14777 mips16_emit_constants (pool.first, get_last_insn ());
14780 /* Return true if it is worth r10k_simplify_address's while replacing
14781 an address with X. We are looking for constants, and for addresses
14782 at a known offset from the incoming stack pointer. */
14785 r10k_simplified_address_p (rtx x)
14787 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
14789 return x == virtual_incoming_args_rtx || CONSTANT_P (x);
14792 /* X is an expression that appears in INSN. Try to use the UD chains
14793 to simplify it, returning the simplified form on success and the
14794 original form otherwise. Replace the incoming value of $sp with
14795 virtual_incoming_args_rtx (which should never occur in X otherwise). */
14798 r10k_simplify_address (rtx x, rtx insn)
14800 rtx newx, op0, op1, set, def_insn, note;
14802 struct df_link *defs;
14807 op0 = r10k_simplify_address (XEXP (x, 0), insn);
14808 if (op0 != XEXP (x, 0))
14809 newx = simplify_gen_unary (GET_CODE (x), GET_MODE (x),
14810 op0, GET_MODE (XEXP (x, 0)));
14812 else if (BINARY_P (x))
14814 op0 = r10k_simplify_address (XEXP (x, 0), insn);
14815 op1 = r10k_simplify_address (XEXP (x, 1), insn);
14816 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
14817 newx = simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
14819 else if (GET_CODE (x) == LO_SUM)
14821 /* LO_SUMs can be offset from HIGHs, if we know they won't
14822 overflow. See mips_classify_address for the rationale behind
14824 op0 = r10k_simplify_address (XEXP (x, 0), insn);
14825 if (GET_CODE (op0) == HIGH)
14826 newx = XEXP (x, 1);
14828 else if (REG_P (x))
14830 /* Uses are recorded by regno_reg_rtx, not X itself. */
14831 use = df_find_use (insn, regno_reg_rtx[REGNO (x)]);
14833 defs = DF_REF_CHAIN (use);
14835 /* Require a single definition. */
14836 if (defs && defs->next == NULL)
14839 if (DF_REF_IS_ARTIFICIAL (def))
14841 /* Replace the incoming value of $sp with
14842 virtual_incoming_args_rtx. */
14843 if (x == stack_pointer_rtx
14844 && DF_REF_BB (def) == ENTRY_BLOCK_PTR_FOR_FN (cfun))
14845 newx = virtual_incoming_args_rtx;
14847 else if (dominated_by_p (CDI_DOMINATORS, DF_REF_BB (use),
14850 /* Make sure that DEF_INSN is a single set of REG. */
14851 def_insn = DF_REF_INSN (def);
14852 if (NONJUMP_INSN_P (def_insn))
14854 set = single_set (def_insn);
14855 if (set && rtx_equal_p (SET_DEST (set), x))
14857 /* Prefer to use notes, since the def-use chains
14858 are often shorter. */
14859 note = find_reg_equal_equiv_note (def_insn);
14861 newx = XEXP (note, 0);
14863 newx = SET_SRC (set);
14864 newx = r10k_simplify_address (newx, def_insn);
14870 if (newx && r10k_simplified_address_p (newx))
14875 /* Return true if ADDRESS is known to be an uncached address
14876 on R10K systems. */
14879 r10k_uncached_address_p (unsigned HOST_WIDE_INT address)
14881 unsigned HOST_WIDE_INT upper;
14883 /* Check for KSEG1. */
14884 if (address + 0x60000000 < 0x20000000)
14887 /* Check for uncached XKPHYS addresses. */
14888 if (Pmode == DImode)
14890 upper = (address >> 40) & 0xf9ffff;
14891 if (upper == 0x900000 || upper == 0xb80000)
14897 /* Return true if we can prove that an access to address X in instruction
14898 INSN would be safe from R10K speculation. This X is a general
14899 expression; it might not be a legitimate address. */
14902 r10k_safe_address_p (rtx x, rtx insn)
14905 HOST_WIDE_INT offset_val;
14907 x = r10k_simplify_address (x, insn);
14909 /* Check for references to the stack frame. It doesn't really matter
14910 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
14911 allows us to assume that accesses to any part of the eventual frame
14912 is safe from speculation at any point in the function. */
14913 mips_split_plus (x, &base, &offset_val);
14914 if (base == virtual_incoming_args_rtx
14915 && offset_val >= -cfun->machine->frame.total_size
14916 && offset_val < cfun->machine->frame.args_size)
14919 /* Check for uncached addresses. */
14920 if (CONST_INT_P (x))
14921 return r10k_uncached_address_p (INTVAL (x));
14923 /* Check for accesses to a static object. */
14924 split_const (x, &base, &offset);
14925 return offset_within_block_p (base, INTVAL (offset));
14928 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
14929 an in-range access to an automatic variable, or to an object with
14930 a link-time-constant address. */
14933 r10k_safe_mem_expr_p (tree expr, unsigned HOST_WIDE_INT offset)
14935 HOST_WIDE_INT bitoffset, bitsize;
14936 tree inner, var_offset;
14937 enum machine_mode mode;
14938 int unsigned_p, volatile_p;
14940 inner = get_inner_reference (expr, &bitsize, &bitoffset, &var_offset, &mode,
14941 &unsigned_p, &volatile_p, false);
14942 if (!DECL_P (inner) || !DECL_SIZE_UNIT (inner) || var_offset)
14945 offset += bitoffset / BITS_PER_UNIT;
14946 return offset < tree_to_uhwi (DECL_SIZE_UNIT (inner));
14949 /* A for_each_rtx callback for which DATA points to the instruction
14950 containing *X. Stop the search if we find a MEM that is not safe
14951 from R10K speculation. */
14954 r10k_needs_protection_p_1 (rtx *loc, void *data)
14963 && MEM_OFFSET_KNOWN_P (mem)
14964 && r10k_safe_mem_expr_p (MEM_EXPR (mem), MEM_OFFSET (mem)))
14967 if (r10k_safe_address_p (XEXP (mem, 0), (rtx) data))
14973 /* A note_stores callback for which DATA points to an instruction pointer.
14974 If *DATA is nonnull, make it null if it X contains a MEM that is not
14975 safe from R10K speculation. */
14978 r10k_needs_protection_p_store (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
14983 insn_ptr = (rtx *) data;
14984 if (*insn_ptr && for_each_rtx (&x, r10k_needs_protection_p_1, *insn_ptr))
14985 *insn_ptr = NULL_RTX;
14988 /* A for_each_rtx callback that iterates over the pattern of a CALL_INSN.
14989 Return nonzero if the call is not to a declared function. */
14992 r10k_needs_protection_p_call (rtx *loc, void *data ATTRIBUTE_UNUSED)
15001 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DECL (x))
15007 /* Return true if instruction INSN needs to be protected by an R10K
15011 r10k_needs_protection_p (rtx insn)
15014 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_call, NULL);
15016 if (mips_r10k_cache_barrier == R10K_CACHE_BARRIER_STORE)
15018 note_stores (PATTERN (insn), r10k_needs_protection_p_store, &insn);
15019 return insn == NULL_RTX;
15022 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_1, insn);
15025 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
15026 edge is unconditional. */
15029 r10k_protected_bb_p (basic_block bb, sbitmap protected_bbs)
15034 FOR_EACH_EDGE (e, ei, bb->preds)
15035 if (!single_succ_p (e->src)
15036 || !bitmap_bit_p (protected_bbs, e->src->index)
15037 || (e->flags & EDGE_COMPLEX) != 0)
15042 /* Implement -mr10k-cache-barrier= for the current function. */
15045 r10k_insert_cache_barriers (void)
15047 int *rev_post_order;
15050 sbitmap protected_bbs;
15051 rtx insn, end, unprotected_region;
15055 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
15059 /* Calculate dominators. */
15060 calculate_dominance_info (CDI_DOMINATORS);
15062 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
15063 X is protected by a cache barrier. */
15064 protected_bbs = sbitmap_alloc (last_basic_block_for_fn (cfun));
15065 bitmap_clear (protected_bbs);
15067 /* Iterate over the basic blocks in reverse post-order. */
15068 rev_post_order = XNEWVEC (int, last_basic_block_for_fn (cfun));
15069 n = pre_and_rev_post_order_compute (NULL, rev_post_order, false);
15070 for (i = 0; i < n; i++)
15072 bb = BASIC_BLOCK_FOR_FN (cfun, rev_post_order[i]);
15074 /* If this block is only reached by unconditional edges, and if the
15075 source of every edge is protected, the beginning of the block is
15077 if (r10k_protected_bb_p (bb, protected_bbs))
15078 unprotected_region = NULL_RTX;
15080 unprotected_region = pc_rtx;
15081 end = NEXT_INSN (BB_END (bb));
15083 /* UNPROTECTED_REGION is:
15085 - null if we are processing a protected region,
15086 - pc_rtx if we are processing an unprotected region but have
15087 not yet found the first instruction in it
15088 - the first instruction in an unprotected region otherwise. */
15089 for (insn = BB_HEAD (bb); insn != end; insn = NEXT_INSN (insn))
15091 if (unprotected_region && USEFUL_INSN_P (insn))
15093 if (recog_memoized (insn) == CODE_FOR_mips_cache)
15094 /* This CACHE instruction protects the following code. */
15095 unprotected_region = NULL_RTX;
15098 /* See if INSN is the first instruction in this
15099 unprotected region. */
15100 if (unprotected_region == pc_rtx)
15101 unprotected_region = insn;
15103 /* See if INSN needs to be protected. If so,
15104 we must insert a cache barrier somewhere between
15105 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
15106 clear which position is better performance-wise,
15107 but as a tie-breaker, we assume that it is better
15108 to allow delay slots to be back-filled where
15109 possible, and that it is better not to insert
15110 barriers in the middle of already-scheduled code.
15111 We therefore insert the barrier at the beginning
15113 if (r10k_needs_protection_p (insn))
15115 emit_insn_before (gen_r10k_cache_barrier (),
15116 unprotected_region);
15117 unprotected_region = NULL_RTX;
15123 /* The called function is not required to protect the exit path.
15124 The code that follows a call is therefore unprotected. */
15125 unprotected_region = pc_rtx;
15128 /* Record whether the end of this block is protected. */
15129 if (unprotected_region == NULL_RTX)
15130 bitmap_set_bit (protected_bbs, bb->index);
15132 XDELETEVEC (rev_post_order);
15134 sbitmap_free (protected_bbs);
15136 free_dominance_info (CDI_DOMINATORS);
15139 /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX
15140 otherwise. If INSN has two call rtx, then store the second one in
15144 mips_call_expr_from_insn (rtx insn, rtx *second_call)
15149 if (!CALL_P (insn))
15152 x = PATTERN (insn);
15153 if (GET_CODE (x) == PARALLEL)
15155 /* Calls returning complex values have two CALL rtx. Look for the second
15156 one here, and return it via the SECOND_CALL arg. */
15157 x2 = XVECEXP (x, 0, 1);
15158 if (GET_CODE (x2) == SET)
15160 if (GET_CODE (x2) == CALL)
15163 x = XVECEXP (x, 0, 0);
15165 if (GET_CODE (x) == SET)
15167 gcc_assert (GET_CODE (x) == CALL);
15172 /* REG is set in DEF. See if the definition is one of the ways we load a
15173 register with a symbol address for a mips_use_pic_fn_addr_reg_p call.
15174 If it is, return the symbol reference of the function, otherwise return
15177 If RECURSE_P is true, use mips_find_pic_call_symbol to interpret
15178 the values of source registers, otherwise treat such registers as
15179 having an unknown value. */
15182 mips_pic_call_symbol_from_set (df_ref def, rtx reg, bool recurse_p)
15186 if (DF_REF_IS_ARTIFICIAL (def))
15189 def_insn = DF_REF_INSN (def);
15190 set = single_set (def_insn);
15191 if (set && rtx_equal_p (SET_DEST (set), reg))
15193 rtx note, src, symbol;
15195 /* First see whether the source is a plain symbol. This is used
15196 when calling symbols that are not lazily bound. */
15197 src = SET_SRC (set);
15198 if (GET_CODE (src) == SYMBOL_REF)
15201 /* Handle %call16 references. */
15202 symbol = mips_strip_unspec_call (src);
15205 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
15209 /* If we have something more complicated, look for a
15210 REG_EQUAL or REG_EQUIV note. */
15211 note = find_reg_equal_equiv_note (def_insn);
15212 if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF)
15213 return XEXP (note, 0);
15215 /* Follow at most one simple register copy. Such copies are
15216 interesting in cases like:
15220 locally_binding_fn (...);
15225 locally_binding_fn (...);
15227 locally_binding_fn (...);
15229 where the load of locally_binding_fn can legitimately be
15230 hoisted or shared. However, we do not expect to see complex
15231 chains of copies, so a full worklist solution to the problem
15232 would probably be overkill. */
15233 if (recurse_p && REG_P (src))
15234 return mips_find_pic_call_symbol (def_insn, src, false);
15240 /* Find the definition of the use of REG in INSN. See if the definition
15241 is one of the ways we load a register with a symbol address for a
15242 mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference
15243 of the function, otherwise return NULL_RTX. RECURSE_P is as for
15244 mips_pic_call_symbol_from_set. */
15247 mips_find_pic_call_symbol (rtx insn, rtx reg, bool recurse_p)
15250 struct df_link *defs;
15253 use = df_find_use (insn, regno_reg_rtx[REGNO (reg)]);
15256 defs = DF_REF_CHAIN (use);
15259 symbol = mips_pic_call_symbol_from_set (defs->ref, reg, recurse_p);
15263 /* If we have more than one definition, they need to be identical. */
15264 for (defs = defs->next; defs; defs = defs->next)
15268 other = mips_pic_call_symbol_from_set (defs->ref, reg, recurse_p);
15269 if (!rtx_equal_p (symbol, other))
15276 /* Replace the args_size operand of the call expression CALL with the
15277 call-attribute UNSPEC and fill in SYMBOL as the function symbol. */
15280 mips_annotate_pic_call_expr (rtx call, rtx symbol)
15284 args_size = XEXP (call, 1);
15285 XEXP (call, 1) = gen_rtx_UNSPEC (GET_MODE (args_size),
15286 gen_rtvec (2, args_size, symbol),
15290 /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See
15291 if instead of the arg_size argument it contains the call attributes. If
15292 yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function
15293 symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is
15297 mips_get_pic_call_symbol (rtx *operands, int args_size_opno)
15299 rtx args_size, symbol;
15301 if (!TARGET_RELAX_PIC_CALLS || args_size_opno == -1)
15304 args_size = operands[args_size_opno];
15305 if (GET_CODE (args_size) != UNSPEC)
15307 gcc_assert (XINT (args_size, 1) == UNSPEC_CALL_ATTR);
15309 symbol = XVECEXP (args_size, 0, 1);
15310 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
15312 operands[args_size_opno] = symbol;
15316 /* Use DF to annotate PIC indirect calls with the function symbol they
15320 mips_annotate_pic_calls (void)
15325 FOR_EACH_BB_FN (bb, cfun)
15326 FOR_BB_INSNS (bb, insn)
15328 rtx call, reg, symbol, second_call;
15331 call = mips_call_expr_from_insn (insn, &second_call);
15334 gcc_assert (MEM_P (XEXP (call, 0)));
15335 reg = XEXP (XEXP (call, 0), 0);
15339 symbol = mips_find_pic_call_symbol (insn, reg, true);
15342 mips_annotate_pic_call_expr (call, symbol);
15344 mips_annotate_pic_call_expr (second_call, symbol);
15349 /* A temporary variable used by for_each_rtx callbacks, etc. */
15350 static rtx mips_sim_insn;
15352 /* A structure representing the state of the processor pipeline.
15353 Used by the mips_sim_* family of functions. */
15355 /* The maximum number of instructions that can be issued in a cycle.
15356 (Caches mips_issue_rate.) */
15357 unsigned int issue_rate;
15359 /* The current simulation time. */
15362 /* How many more instructions can be issued in the current cycle. */
15363 unsigned int insns_left;
15365 /* LAST_SET[X].INSN is the last instruction to set register X.
15366 LAST_SET[X].TIME is the time at which that instruction was issued.
15367 INSN is null if no instruction has yet set register X. */
15371 } last_set[FIRST_PSEUDO_REGISTER];
15373 /* The pipeline's current DFA state. */
15377 /* Reset STATE to the initial simulation state. */
15380 mips_sim_reset (struct mips_sim *state)
15382 curr_state = state->dfa_state;
15385 state->insns_left = state->issue_rate;
15386 memset (&state->last_set, 0, sizeof (state->last_set));
15387 state_reset (curr_state);
15389 targetm.sched.init (0, false, 0);
15390 advance_state (curr_state);
15393 /* Initialize STATE before its first use. DFA_STATE points to an
15394 allocated but uninitialized DFA state. */
15397 mips_sim_init (struct mips_sim *state, state_t dfa_state)
15399 if (targetm.sched.init_dfa_pre_cycle_insn)
15400 targetm.sched.init_dfa_pre_cycle_insn ();
15402 if (targetm.sched.init_dfa_post_cycle_insn)
15403 targetm.sched.init_dfa_post_cycle_insn ();
15405 state->issue_rate = mips_issue_rate ();
15406 state->dfa_state = dfa_state;
15407 mips_sim_reset (state);
15410 /* Advance STATE by one clock cycle. */
15413 mips_sim_next_cycle (struct mips_sim *state)
15415 curr_state = state->dfa_state;
15418 state->insns_left = state->issue_rate;
15419 advance_state (curr_state);
15422 /* Advance simulation state STATE until instruction INSN can read
15426 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
15428 unsigned int regno, end_regno;
15430 end_regno = END_REGNO (reg);
15431 for (regno = REGNO (reg); regno < end_regno; regno++)
15432 if (state->last_set[regno].insn != 0)
15436 t = (state->last_set[regno].time
15437 + insn_latency (state->last_set[regno].insn, insn));
15438 while (state->time < t)
15439 mips_sim_next_cycle (state);
15443 /* A for_each_rtx callback. If *X is a register, advance simulation state
15444 DATA until mips_sim_insn can read the register's value. */
15447 mips_sim_wait_regs_2 (rtx *x, void *data)
15450 mips_sim_wait_reg ((struct mips_sim *) data, mips_sim_insn, *x);
15454 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
15457 mips_sim_wait_regs_1 (rtx *x, void *data)
15459 for_each_rtx (x, mips_sim_wait_regs_2, data);
15462 /* Advance simulation state STATE until all of INSN's register
15463 dependencies are satisfied. */
15466 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
15468 mips_sim_insn = insn;
15469 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
15472 /* Advance simulation state STATE until the units required by
15473 instruction INSN are available. */
15476 mips_sim_wait_units (struct mips_sim *state, rtx insn)
15480 tmp_state = alloca (state_size ());
15481 while (state->insns_left == 0
15482 || (memcpy (tmp_state, state->dfa_state, state_size ()),
15483 state_transition (tmp_state, insn) >= 0))
15484 mips_sim_next_cycle (state);
15487 /* Advance simulation state STATE until INSN is ready to issue. */
15490 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
15492 mips_sim_wait_regs (state, insn);
15493 mips_sim_wait_units (state, insn);
15496 /* mips_sim_insn has just set X. Update the LAST_SET array
15497 in simulation state DATA. */
15500 mips_sim_record_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
15502 struct mips_sim *state;
15504 state = (struct mips_sim *) data;
15507 unsigned int regno, end_regno;
15509 end_regno = END_REGNO (x);
15510 for (regno = REGNO (x); regno < end_regno; regno++)
15512 state->last_set[regno].insn = mips_sim_insn;
15513 state->last_set[regno].time = state->time;
15518 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
15519 can issue immediately (i.e., that mips_sim_wait_insn has already
15523 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
15525 curr_state = state->dfa_state;
15527 state_transition (curr_state, insn);
15528 state->insns_left = targetm.sched.variable_issue (0, false, insn,
15529 state->insns_left);
15531 mips_sim_insn = insn;
15532 note_stores (PATTERN (insn), mips_sim_record_set, state);
15535 /* Simulate issuing a NOP in state STATE. */
15538 mips_sim_issue_nop (struct mips_sim *state)
15540 if (state->insns_left == 0)
15541 mips_sim_next_cycle (state);
15542 state->insns_left--;
15545 /* Update simulation state STATE so that it's ready to accept the instruction
15546 after INSN. INSN should be part of the main rtl chain, not a member of a
15550 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
15552 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
15554 mips_sim_issue_nop (state);
15556 switch (GET_CODE (SEQ_BEGIN (insn)))
15560 /* We can't predict the processor state after a call or label. */
15561 mips_sim_reset (state);
15565 /* The delay slots of branch likely instructions are only executed
15566 when the branch is taken. Therefore, if the caller has simulated
15567 the delay slot instruction, STATE does not really reflect the state
15568 of the pipeline for the instruction after the delay slot. Also,
15569 branch likely instructions tend to incur a penalty when not taken,
15570 so there will probably be an extra delay between the branch and
15571 the instruction after the delay slot. */
15572 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
15573 mips_sim_reset (state);
15581 /* Use simulator state STATE to calculate the execution time of
15582 instruction sequence SEQ. */
15584 static unsigned int
15585 mips_seq_time (struct mips_sim *state, rtx seq)
15587 mips_sim_reset (state);
15588 for (rtx insn = seq; insn; insn = NEXT_INSN (insn))
15590 mips_sim_wait_insn (state, insn);
15591 mips_sim_issue_insn (state, insn);
15593 return state->time;
15596 /* Return the execution-time cost of mips_tuning_info.fast_mult_zero_zero_p
15597 setting SETTING, using STATE to simulate instruction sequences. */
15599 static unsigned int
15600 mips_mult_zero_zero_cost (struct mips_sim *state, bool setting)
15602 mips_tuning_info.fast_mult_zero_zero_p = setting;
15605 enum machine_mode dword_mode = TARGET_64BIT ? TImode : DImode;
15606 rtx hilo = gen_rtx_REG (dword_mode, MD_REG_FIRST);
15607 mips_emit_move_or_split (hilo, const0_rtx, SPLIT_FOR_SPEED);
15609 /* If the target provides mulsidi3_32bit then that's the most likely
15610 consumer of the result. Test for bypasses. */
15611 if (dword_mode == DImode && HAVE_maddsidi4)
15613 rtx gpr = gen_rtx_REG (SImode, GP_REG_FIRST + 4);
15614 emit_insn (gen_maddsidi4 (hilo, gpr, gpr, hilo));
15617 unsigned int time = mips_seq_time (state, get_insns ());
15622 /* Check the relative speeds of "MULT $0,$0" and "MTLO $0; MTHI $0"
15623 and set up mips_tuning_info.fast_mult_zero_zero_p accordingly.
15624 Prefer MULT -- which is shorter -- in the event of a tie. */
15627 mips_set_fast_mult_zero_zero_p (struct mips_sim *state)
15630 /* No MTLO or MTHI available. */
15631 mips_tuning_info.fast_mult_zero_zero_p = true;
15634 unsigned int true_time = mips_mult_zero_zero_cost (state, true);
15635 unsigned int false_time = mips_mult_zero_zero_cost (state, false);
15636 mips_tuning_info.fast_mult_zero_zero_p = (true_time <= false_time);
15640 /* Set up costs based on the current architecture and tuning settings. */
15643 mips_set_tuning_info (void)
15645 if (mips_tuning_info.initialized_p
15646 && mips_tuning_info.arch == mips_arch
15647 && mips_tuning_info.tune == mips_tune
15648 && mips_tuning_info.mips16_p == TARGET_MIPS16)
15651 mips_tuning_info.arch = mips_arch;
15652 mips_tuning_info.tune = mips_tune;
15653 mips_tuning_info.mips16_p = TARGET_MIPS16;
15654 mips_tuning_info.initialized_p = true;
15658 struct mips_sim state;
15659 mips_sim_init (&state, alloca (state_size ()));
15661 mips_set_fast_mult_zero_zero_p (&state);
15666 /* Implement TARGET_EXPAND_TO_RTL_HOOK. */
15669 mips_expand_to_rtl_hook (void)
15671 /* We need to call this at a point where we can safely create sequences
15672 of instructions, so TARGET_OVERRIDE_OPTIONS is too early. We also
15673 need to call it at a point where the DFA infrastructure is not
15674 already in use, so we can't just call it lazily on demand.
15676 At present, mips_tuning_info is only needed during post-expand
15677 RTL passes such as split_insns, so this hook should be early enough.
15678 We may need to move the call elsewhere if mips_tuning_info starts
15679 to be used for other things (such as rtx_costs, or expanders that
15680 could be called during gimple optimization). */
15681 mips_set_tuning_info ();
15684 /* The VR4130 pipeline issues aligned pairs of instructions together,
15685 but it stalls the second instruction if it depends on the first.
15686 In order to cut down the amount of logic required, this dependence
15687 check is not based on a full instruction decode. Instead, any non-SPECIAL
15688 instruction is assumed to modify the register specified by bits 20-16
15689 (which is usually the "rt" field).
15691 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
15692 input, so we can end up with a false dependence between the branch
15693 and its delay slot. If this situation occurs in instruction INSN,
15694 try to avoid it by swapping rs and rt. */
15697 vr4130_avoid_branch_rt_conflict (rtx insn)
15701 first = SEQ_BEGIN (insn);
15702 second = SEQ_END (insn);
15704 && NONJUMP_INSN_P (second)
15705 && GET_CODE (PATTERN (first)) == SET
15706 && GET_CODE (SET_DEST (PATTERN (first))) == PC
15707 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
15709 /* Check for the right kind of condition. */
15710 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
15711 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
15712 && REG_P (XEXP (cond, 0))
15713 && REG_P (XEXP (cond, 1))
15714 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
15715 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
15717 /* SECOND mentions the rt register but not the rs register. */
15718 rtx tmp = XEXP (cond, 0);
15719 XEXP (cond, 0) = XEXP (cond, 1);
15720 XEXP (cond, 1) = tmp;
15725 /* Implement -mvr4130-align. Go through each basic block and simulate the
15726 processor pipeline. If we find that a pair of instructions could execute
15727 in parallel, and the first of those instructions is not 8-byte aligned,
15728 insert a nop to make it aligned. */
15731 vr4130_align_insns (void)
15733 struct mips_sim state;
15734 rtx insn, subinsn, last, last2, next;
15739 /* LAST is the last instruction before INSN to have a nonzero length.
15740 LAST2 is the last such instruction before LAST. */
15744 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
15747 mips_sim_init (&state, alloca (state_size ()));
15748 for (insn = get_insns (); insn != 0; insn = next)
15750 unsigned int length;
15752 next = NEXT_INSN (insn);
15754 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
15755 This isn't really related to the alignment pass, but we do it on
15756 the fly to avoid a separate instruction walk. */
15757 vr4130_avoid_branch_rt_conflict (insn);
15759 length = get_attr_length (insn);
15760 if (length > 0 && USEFUL_INSN_P (insn))
15761 FOR_EACH_SUBINSN (subinsn, insn)
15763 mips_sim_wait_insn (&state, subinsn);
15765 /* If we want this instruction to issue in parallel with the
15766 previous one, make sure that the previous instruction is
15767 aligned. There are several reasons why this isn't worthwhile
15768 when the second instruction is a call:
15770 - Calls are less likely to be performance critical,
15771 - There's a good chance that the delay slot can execute
15772 in parallel with the call.
15773 - The return address would then be unaligned.
15775 In general, if we're going to insert a nop between instructions
15776 X and Y, it's better to insert it immediately after X. That
15777 way, if the nop makes Y aligned, it will also align any labels
15778 between X and Y. */
15779 if (state.insns_left != state.issue_rate
15780 && !CALL_P (subinsn))
15782 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
15784 /* SUBINSN is the first instruction in INSN and INSN is
15785 aligned. We want to align the previous instruction
15786 instead, so insert a nop between LAST2 and LAST.
15788 Note that LAST could be either a single instruction
15789 or a branch with a delay slot. In the latter case,
15790 LAST, like INSN, is already aligned, but the delay
15791 slot must have some extra delay that stops it from
15792 issuing at the same time as the branch. We therefore
15793 insert a nop before the branch in order to align its
15795 gcc_assert (last2);
15796 emit_insn_after (gen_nop (), last2);
15799 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
15801 /* SUBINSN is the delay slot of INSN, but INSN is
15802 currently unaligned. Insert a nop between
15803 LAST and INSN to align it. */
15805 emit_insn_after (gen_nop (), last);
15809 mips_sim_issue_insn (&state, subinsn);
15811 mips_sim_finish_insn (&state, insn);
15813 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
15814 length = get_attr_length (insn);
15817 /* If the instruction is an asm statement or multi-instruction
15818 mips.md patern, the length is only an estimate. Insert an
15819 8 byte alignment after it so that the following instructions
15820 can be handled correctly. */
15821 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
15822 && (recog_memoized (insn) < 0 || length >= 8))
15824 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
15825 next = NEXT_INSN (next);
15826 mips_sim_next_cycle (&state);
15829 else if (length & 4)
15830 aligned_p = !aligned_p;
15835 /* See whether INSN is an aligned label. */
15836 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
15842 /* This structure records that the current function has a LO_SUM
15843 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
15844 the largest offset applied to BASE by all such LO_SUMs. */
15845 struct mips_lo_sum_offset {
15847 HOST_WIDE_INT offset;
15850 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
15853 mips_hash_base (rtx base)
15855 int do_not_record_p;
15857 return hash_rtx (base, GET_MODE (base), &do_not_record_p, NULL, false);
15860 /* Hashtable helpers. */
15862 struct mips_lo_sum_offset_hasher : typed_free_remove <mips_lo_sum_offset>
15864 typedef mips_lo_sum_offset value_type;
15865 typedef rtx_def compare_type;
15866 static inline hashval_t hash (const value_type *);
15867 static inline bool equal (const value_type *, const compare_type *);
15870 /* Hash-table callbacks for mips_lo_sum_offsets. */
15873 mips_lo_sum_offset_hasher::hash (const value_type *entry)
15875 return mips_hash_base (entry->base);
15879 mips_lo_sum_offset_hasher::equal (const value_type *entry,
15880 const compare_type *value)
15882 return rtx_equal_p (entry->base, value);
15885 typedef hash_table <mips_lo_sum_offset_hasher> mips_offset_table;
15887 /* Look up symbolic constant X in HTAB, which is a hash table of
15888 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
15889 paired with a recorded LO_SUM, otherwise record X in the table. */
15892 mips_lo_sum_offset_lookup (mips_offset_table htab, rtx x,
15893 enum insert_option option)
15896 mips_lo_sum_offset **slot;
15897 struct mips_lo_sum_offset *entry;
15899 /* Split X into a base and offset. */
15900 split_const (x, &base, &offset);
15901 if (UNSPEC_ADDRESS_P (base))
15902 base = UNSPEC_ADDRESS (base);
15904 /* Look up the base in the hash table. */
15905 slot = htab.find_slot_with_hash (base, mips_hash_base (base), option);
15909 entry = (struct mips_lo_sum_offset *) *slot;
15910 if (option == INSERT)
15914 entry = XNEW (struct mips_lo_sum_offset);
15915 entry->base = base;
15916 entry->offset = INTVAL (offset);
15921 if (INTVAL (offset) > entry->offset)
15922 entry->offset = INTVAL (offset);
15925 return INTVAL (offset) <= entry->offset;
15928 /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table.
15929 Record every LO_SUM in *LOC. */
15932 mips_record_lo_sum (rtx *loc, void *data)
15934 if (GET_CODE (*loc) == LO_SUM)
15935 mips_lo_sum_offset_lookup (*(mips_offset_table*) data,
15936 XEXP (*loc, 1), INSERT);
15940 /* Return true if INSN is a SET of an orphaned high-part relocation.
15941 HTAB is a hash table of mips_lo_sum_offsets that describes all the
15942 LO_SUMs in the current function. */
15945 mips_orphaned_high_part_p (mips_offset_table htab, rtx insn)
15947 enum mips_symbol_type type;
15950 set = single_set (insn);
15953 /* Check for %his. */
15955 if (GET_CODE (x) == HIGH
15956 && absolute_symbolic_operand (XEXP (x, 0), VOIDmode))
15957 return !mips_lo_sum_offset_lookup (htab, XEXP (x, 0), NO_INSERT);
15959 /* Check for local %gots (and %got_pages, which is redundant but OK). */
15960 if (GET_CODE (x) == UNSPEC
15961 && XINT (x, 1) == UNSPEC_LOAD_GOT
15962 && mips_symbolic_constant_p (XVECEXP (x, 0, 1),
15963 SYMBOL_CONTEXT_LEA, &type)
15964 && type == SYMBOL_GOTOFF_PAGE)
15965 return !mips_lo_sum_offset_lookup (htab, XVECEXP (x, 0, 1), NO_INSERT);
15970 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
15971 INSN and a previous instruction, avoid it by inserting nops after
15974 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
15975 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
15976 before using the value of that register. *HILO_DELAY counts the
15977 number of instructions since the last hilo hazard (that is,
15978 the number of instructions since the last MFLO or MFHI).
15980 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
15981 for the next instruction.
15983 LO_REG is an rtx for the LO register, used in dependence checking. */
15986 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
15987 rtx *delayed_reg, rtx lo_reg)
15992 pattern = PATTERN (insn);
15994 /* Do not put the whole function in .set noreorder if it contains
15995 an asm statement. We don't know whether there will be hazards
15996 between the asm statement and the gcc-generated code. */
15997 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
15998 cfun->machine->all_noreorder_p = false;
16000 /* Ignore zero-length instructions (barriers and the like). */
16001 ninsns = get_attr_length (insn) / 4;
16005 /* Work out how many nops are needed. Note that we only care about
16006 registers that are explicitly mentioned in the instruction's pattern.
16007 It doesn't matter that calls use the argument registers or that they
16008 clobber hi and lo. */
16009 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
16010 nops = 2 - *hilo_delay;
16011 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
16016 /* Insert the nops between this instruction and the previous one.
16017 Each new nop takes us further from the last hilo hazard. */
16018 *hilo_delay += nops;
16020 emit_insn_after (gen_hazard_nop (), after);
16022 /* Set up the state for the next instruction. */
16023 *hilo_delay += ninsns;
16025 if (INSN_CODE (insn) >= 0)
16026 switch (get_attr_hazard (insn))
16036 set = single_set (insn);
16038 *delayed_reg = SET_DEST (set);
16043 /* Go through the instruction stream and insert nops where necessary.
16044 Also delete any high-part relocations whose partnering low parts
16045 are now all dead. See if the whole function can then be put into
16046 .set noreorder and .set nomacro. */
16049 mips_reorg_process_insns (void)
16051 rtx insn, last_insn, subinsn, next_insn, lo_reg, delayed_reg;
16053 mips_offset_table htab;
16055 /* Force all instructions to be split into their final form. */
16056 split_all_insns_noflow ();
16058 /* Recalculate instruction lengths without taking nops into account. */
16059 cfun->machine->ignore_hazard_length_p = true;
16060 shorten_branches (get_insns ());
16062 cfun->machine->all_noreorder_p = true;
16064 /* We don't track MIPS16 PC-relative offsets closely enough to make
16065 a good job of "set .noreorder" code in MIPS16 mode. */
16067 cfun->machine->all_noreorder_p = false;
16069 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
16070 if (!TARGET_EXPLICIT_RELOCS)
16071 cfun->machine->all_noreorder_p = false;
16073 /* Profiled functions can't be all noreorder because the profiler
16074 support uses assembler macros. */
16076 cfun->machine->all_noreorder_p = false;
16078 /* Code compiled with -mfix-vr4120, -mfix-rm7000 or -mfix-24k can't be
16079 all noreorder because we rely on the assembler to work around some
16080 errata. The R5900 too has several bugs. */
16081 if (TARGET_FIX_VR4120
16082 || TARGET_FIX_RM7000
16084 || TARGET_MIPS5900)
16085 cfun->machine->all_noreorder_p = false;
16087 /* The same is true for -mfix-vr4130 if we might generate MFLO or
16088 MFHI instructions. Note that we avoid using MFLO and MFHI if
16089 the VR4130 MACC and DMACC instructions are available instead;
16090 see the *mfhilo_{si,di}_macc patterns. */
16091 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
16092 cfun->machine->all_noreorder_p = false;
16096 /* Make a first pass over the instructions, recording all the LO_SUMs. */
16097 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
16098 FOR_EACH_SUBINSN (subinsn, insn)
16099 if (USEFUL_INSN_P (subinsn))
16100 for_each_rtx (&PATTERN (subinsn), mips_record_lo_sum, &htab);
16105 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
16107 /* Make a second pass over the instructions. Delete orphaned
16108 high-part relocations or turn them into NOPs. Avoid hazards
16109 by inserting NOPs. */
16110 for (insn = get_insns (); insn != 0; insn = next_insn)
16112 next_insn = NEXT_INSN (insn);
16113 if (USEFUL_INSN_P (insn))
16115 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
16117 /* If we find an orphaned high-part relocation in a delay
16118 slot, it's easier to turn that instruction into a NOP than
16119 to delete it. The delay slot will be a NOP either way. */
16120 FOR_EACH_SUBINSN (subinsn, insn)
16121 if (INSN_P (subinsn))
16123 if (mips_orphaned_high_part_p (htab, subinsn))
16125 PATTERN (subinsn) = gen_nop ();
16126 INSN_CODE (subinsn) = CODE_FOR_nop;
16128 mips_avoid_hazard (last_insn, subinsn, &hilo_delay,
16129 &delayed_reg, lo_reg);
16135 /* INSN is a single instruction. Delete it if it's an
16136 orphaned high-part relocation. */
16137 if (mips_orphaned_high_part_p (htab, insn))
16138 delete_insn (insn);
16139 /* Also delete cache barriers if the last instruction
16140 was an annulled branch. INSN will not be speculatively
16142 else if (recog_memoized (insn) == CODE_FOR_r10k_cache_barrier
16144 && JUMP_P (SEQ_BEGIN (last_insn))
16145 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn)))
16146 delete_insn (insn);
16149 mips_avoid_hazard (last_insn, insn, &hilo_delay,
16150 &delayed_reg, lo_reg);
16160 /* Return true if the function has a long branch instruction. */
16163 mips_has_long_branch_p (void)
16168 /* We need up-to-date instruction lengths. */
16169 shorten_branches (get_insns ());
16171 /* Look for a branch that is longer than normal. The normal length for
16172 non-MIPS16 branches is 8, because the length includes the delay slot.
16173 It is 4 for MIPS16, because MIPS16 branches are extended instructions,
16174 but they have no delay slot. */
16175 normal_length = (TARGET_MIPS16 ? 4 : 8);
16176 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
16177 FOR_EACH_SUBINSN (subinsn, insn)
16178 if (JUMP_P (subinsn)
16179 && get_attr_length (subinsn) > normal_length
16180 && (any_condjump_p (subinsn) || any_uncondjump_p (subinsn)))
16186 /* If we are using a GOT, but have not decided to use a global pointer yet,
16187 see whether we need one to implement long branches. Convert the ghost
16188 global-pointer instructions into real ones if so. */
16191 mips_expand_ghost_gp_insns (void)
16193 /* Quick exit if we already know that we will or won't need a
16195 if (!TARGET_USE_GOT
16196 || cfun->machine->global_pointer == INVALID_REGNUM
16197 || mips_must_initialize_gp_p ())
16200 /* Run a full check for long branches. */
16201 if (!mips_has_long_branch_p ())
16204 /* We've now established that we need $gp. */
16205 cfun->machine->must_initialize_gp_p = true;
16206 split_all_insns_noflow ();
16211 /* Subroutine of mips_reorg to manage passes that require DF. */
16214 mips_df_reorg (void)
16216 /* Create def-use chains. */
16217 df_set_flags (DF_EQ_NOTES);
16218 df_chain_add_problem (DF_UD_CHAIN);
16221 if (TARGET_RELAX_PIC_CALLS)
16222 mips_annotate_pic_calls ();
16224 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE)
16225 r10k_insert_cache_barriers ();
16227 df_finish_pass (false);
16230 /* Emit code to load LABEL_REF SRC into MIPS16 register DEST. This is
16231 called very late in mips_reorg, but the caller is required to run
16232 mips16_lay_out_constants on the result. */
16235 mips16_load_branch_target (rtx dest, rtx src)
16237 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
16241 if (mips_cfun_has_cprestore_slot_p ())
16242 mips_emit_move (dest, mips_cprestore_slot (dest, true));
16244 mips_emit_move (dest, pic_offset_table_rtx);
16245 page = mips_unspec_address (src, SYMBOL_GOTOFF_PAGE);
16246 low = mips_unspec_address (src, SYMBOL_GOT_PAGE_OFST);
16247 emit_insn (gen_rtx_SET (VOIDmode, dest,
16248 PMODE_INSN (gen_unspec_got, (dest, page))));
16249 emit_insn (gen_rtx_SET (VOIDmode, dest,
16250 gen_rtx_LO_SUM (Pmode, dest, low)));
16254 src = mips_unspec_address (src, SYMBOL_ABSOLUTE);
16255 mips_emit_move (dest, src);
16259 /* If we're compiling a MIPS16 function, look for and split any long branches.
16260 This must be called after all other instruction modifications in
16264 mips16_split_long_branches (void)
16266 bool something_changed;
16268 if (!TARGET_MIPS16)
16271 /* Loop until the alignments for all targets are sufficient. */
16276 shorten_branches (get_insns ());
16277 something_changed = false;
16278 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
16280 && get_attr_length (insn) > 4
16281 && (any_condjump_p (insn) || any_uncondjump_p (insn)))
16283 rtx old_label, new_label, temp, saved_temp;
16284 rtx target, jump, jump_sequence;
16288 /* Free up a MIPS16 register by saving it in $1. */
16289 saved_temp = gen_rtx_REG (Pmode, AT_REGNUM);
16290 temp = gen_rtx_REG (Pmode, GP_REG_FIRST + 2);
16291 emit_move_insn (saved_temp, temp);
16293 /* Load the branch target into TEMP. */
16294 old_label = JUMP_LABEL (insn);
16295 target = gen_rtx_LABEL_REF (Pmode, old_label);
16296 mips16_load_branch_target (temp, target);
16298 /* Jump to the target and restore the register's
16300 jump = emit_jump_insn (PMODE_INSN (gen_indirect_jump_and_restore,
16301 (temp, temp, saved_temp)));
16302 JUMP_LABEL (jump) = old_label;
16303 LABEL_NUSES (old_label)++;
16305 /* Rewrite any symbolic references that are supposed to use
16306 a PC-relative constant pool. */
16307 mips16_lay_out_constants (false);
16309 if (simplejump_p (insn))
16310 /* We're going to replace INSN with a longer form. */
16311 new_label = NULL_RTX;
16314 /* Create a branch-around label for the original
16316 new_label = gen_label_rtx ();
16317 emit_label (new_label);
16320 jump_sequence = get_insns ();
16323 emit_insn_after (jump_sequence, insn);
16325 invert_jump (insn, new_label, false);
16327 delete_insn (insn);
16328 something_changed = true;
16331 while (something_changed);
16334 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
16339 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during
16340 insn splitting in mips16_lay_out_constants, DF insn info is only kept up
16341 to date if the CFG is available. */
16342 if (mips_cfg_in_reorg ())
16343 compute_bb_for_insn ();
16344 mips16_lay_out_constants (true);
16345 if (mips_cfg_in_reorg ())
16348 free_bb_for_insn ();
16352 /* We use a machine specific pass to do a second machine dependent reorg
16353 pass after delay branch scheduling. */
16355 static unsigned int
16356 mips_machine_reorg2 (void)
16358 mips_reorg_process_insns ();
16360 && TARGET_EXPLICIT_RELOCS
16362 && TARGET_VR4130_ALIGN)
16363 vr4130_align_insns ();
16364 if (mips_expand_ghost_gp_insns ())
16365 /* The expansion could invalidate some of the VR4130 alignment
16366 optimizations, but this should be an extremely rare case anyhow. */
16367 mips_reorg_process_insns ();
16368 mips16_split_long_branches ();
16374 const pass_data pass_data_mips_machine_reorg2 =
16376 RTL_PASS, /* type */
16377 "mach2", /* name */
16378 OPTGROUP_NONE, /* optinfo_flags */
16379 false, /* has_gate */
16380 true, /* has_execute */
16381 TV_MACH_DEP, /* tv_id */
16382 0, /* properties_required */
16383 0, /* properties_provided */
16384 0, /* properties_destroyed */
16385 0, /* todo_flags_start */
16386 TODO_verify_rtl_sharing, /* todo_flags_finish */
16389 class pass_mips_machine_reorg2 : public rtl_opt_pass
16392 pass_mips_machine_reorg2(gcc::context *ctxt)
16393 : rtl_opt_pass(pass_data_mips_machine_reorg2, ctxt)
16396 /* opt_pass methods: */
16397 unsigned int execute () { return mips_machine_reorg2 (); }
16399 }; // class pass_mips_machine_reorg2
16401 } // anon namespace
16404 make_pass_mips_machine_reorg2 (gcc::context *ctxt)
16406 return new pass_mips_machine_reorg2 (ctxt);
16410 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
16411 in order to avoid duplicating too much logic from elsewhere. */
16414 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
16415 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
16418 rtx this_rtx, temp1, temp2, insn, fnaddr;
16419 bool use_sibcall_p;
16421 /* Pretend to be a post-reload pass while generating rtl. */
16422 reload_completed = 1;
16424 /* Mark the end of the (empty) prologue. */
16425 emit_note (NOTE_INSN_PROLOGUE_END);
16427 /* Determine if we can use a sibcall to call FUNCTION directly. */
16428 fnaddr = XEXP (DECL_RTL (function), 0);
16429 use_sibcall_p = (mips_function_ok_for_sibcall (function, NULL)
16430 && const_call_insn_operand (fnaddr, Pmode));
16432 /* Determine if we need to load FNADDR from the GOT. */
16434 && (mips_got_symbol_type_p
16435 (mips_classify_symbol (fnaddr, SYMBOL_CONTEXT_LEA))))
16437 /* Pick a global pointer. Use a call-clobbered register if
16438 TARGET_CALL_SAVED_GP. */
16439 cfun->machine->global_pointer
16440 = TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM;
16441 cfun->machine->must_initialize_gp_p = true;
16442 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
16444 /* Set up the global pointer for n32 or n64 abicalls. */
16445 mips_emit_loadgp ();
16448 /* We need two temporary registers in some cases. */
16449 temp1 = gen_rtx_REG (Pmode, 2);
16450 temp2 = gen_rtx_REG (Pmode, 3);
16452 /* Find out which register contains the "this" pointer. */
16453 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
16454 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
16456 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST);
16458 /* Add DELTA to THIS_RTX. */
16461 rtx offset = GEN_INT (delta);
16462 if (!SMALL_OPERAND (delta))
16464 mips_emit_move (temp1, offset);
16467 emit_insn (gen_add3_insn (this_rtx, this_rtx, offset));
16470 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
16471 if (vcall_offset != 0)
16475 /* Set TEMP1 to *THIS_RTX. */
16476 mips_emit_move (temp1, gen_rtx_MEM (Pmode, this_rtx));
16478 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
16479 addr = mips_add_offset (temp2, temp1, vcall_offset);
16481 /* Load the offset and add it to THIS_RTX. */
16482 mips_emit_move (temp1, gen_rtx_MEM (Pmode, addr));
16483 emit_insn (gen_add3_insn (this_rtx, this_rtx, temp1));
16486 /* Jump to the target function. Use a sibcall if direct jumps are
16487 allowed, otherwise load the address into a register first. */
16490 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
16491 SIBLING_CALL_P (insn) = 1;
16495 /* This is messy. GAS treats "la $25,foo" as part of a call
16496 sequence and may allow a global "foo" to be lazily bound.
16497 The general move patterns therefore reject this combination.
16499 In this context, lazy binding would actually be OK
16500 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
16501 TARGET_CALL_SAVED_GP; see mips_load_call_address.
16502 We must therefore load the address via a temporary
16503 register if mips_dangerous_for_la25_p.
16505 If we jump to the temporary register rather than $25,
16506 the assembler can use the move insn to fill the jump's
16509 We can use the same technique for MIPS16 code, where $25
16510 is not a valid JR register. */
16511 if (TARGET_USE_PIC_FN_ADDR_REG
16513 && !mips_dangerous_for_la25_p (fnaddr))
16514 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
16515 mips_load_call_address (MIPS_CALL_SIBCALL, temp1, fnaddr);
16517 if (TARGET_USE_PIC_FN_ADDR_REG
16518 && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
16519 mips_emit_move (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
16520 emit_jump_insn (gen_indirect_jump (temp1));
16523 /* Run just enough of rest_of_compilation. This sequence was
16524 "borrowed" from alpha.c. */
16525 insn = get_insns ();
16526 split_all_insns_noflow ();
16527 mips16_lay_out_constants (true);
16528 shorten_branches (insn);
16529 final_start_function (insn, file, 1);
16530 final (insn, file, 1);
16531 final_end_function ();
16533 /* Clean up the vars set above. Note that final_end_function resets
16534 the global pointer for us. */
16535 reload_completed = 0;
16539 /* The last argument passed to mips_set_compression_mode,
16540 or negative if the function hasn't been called yet. */
16541 static unsigned int old_compression_mode = -1;
16543 /* Set up the target-dependent global state for ISA mode COMPRESSION_MODE,
16544 which is either MASK_MIPS16 or MASK_MICROMIPS. */
16547 mips_set_compression_mode (unsigned int compression_mode)
16550 if (compression_mode == old_compression_mode)
16553 /* Restore base settings of various flags. */
16554 target_flags = mips_base_target_flags;
16555 flag_schedule_insns = mips_base_schedule_insns;
16556 flag_reorder_blocks_and_partition = mips_base_reorder_blocks_and_partition;
16557 flag_move_loop_invariants = mips_base_move_loop_invariants;
16558 align_loops = mips_base_align_loops;
16559 align_jumps = mips_base_align_jumps;
16560 align_functions = mips_base_align_functions;
16561 target_flags &= ~(MASK_MIPS16 | MASK_MICROMIPS);
16562 target_flags |= compression_mode;
16564 if (compression_mode & MASK_MIPS16)
16566 /* Switch to MIPS16 mode. */
16567 target_flags |= MASK_MIPS16;
16569 /* Turn off SYNCI if it was on, MIPS16 doesn't support it. */
16570 target_flags &= ~MASK_SYNCI;
16572 /* Don't run the scheduler before reload, since it tends to
16573 increase register pressure. */
16574 flag_schedule_insns = 0;
16576 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
16577 the whole function to be in a single section. */
16578 flag_reorder_blocks_and_partition = 0;
16580 /* Don't move loop invariants, because it tends to increase
16581 register pressure. It also introduces an extra move in cases
16582 where the constant is the first operand in a two-operand binary
16583 instruction, or when it forms a register argument to a functon
16585 flag_move_loop_invariants = 0;
16587 target_flags |= MASK_EXPLICIT_RELOCS;
16589 /* Experiments suggest we get the best overall section-anchor
16590 results from using the range of an unextended LW or SW. Code
16591 that makes heavy use of byte or short accesses can do better
16592 with ranges of 0...31 and 0...63 respectively, but most code is
16593 sensitive to the range of LW and SW instead. */
16594 targetm.min_anchor_offset = 0;
16595 targetm.max_anchor_offset = 127;
16597 targetm.const_anchor = 0;
16599 /* MIPS16 has no BAL instruction. */
16600 target_flags &= ~MASK_RELAX_PIC_CALLS;
16602 /* The R4000 errata don't apply to any known MIPS16 cores.
16603 It's simpler to make the R4000 fixes and MIPS16 mode
16604 mutually exclusive. */
16605 target_flags &= ~MASK_FIX_R4000;
16607 if (flag_pic && !TARGET_OLDABI)
16608 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
16611 sorry ("MIPS16 -mxgot code");
16613 if (TARGET_HARD_FLOAT_ABI && !TARGET_OLDABI)
16614 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
16618 /* Switch to microMIPS or the standard encoding. */
16620 if (TARGET_MICROMIPS)
16621 /* Avoid branch likely. */
16622 target_flags &= ~MASK_BRANCHLIKELY;
16624 /* Provide default values for align_* for 64-bit targets. */
16627 if (align_loops == 0)
16629 if (align_jumps == 0)
16631 if (align_functions == 0)
16632 align_functions = 8;
16635 targetm.min_anchor_offset = -32768;
16636 targetm.max_anchor_offset = 32767;
16638 targetm.const_anchor = 0x8000;
16641 /* (Re)initialize MIPS target internals for new ISA. */
16642 mips_init_relocs ();
16644 if (compression_mode & MASK_MIPS16)
16646 if (!mips16_globals)
16647 mips16_globals = save_target_globals_default_opts ();
16649 restore_target_globals (mips16_globals);
16652 restore_target_globals (&default_target_globals);
16654 old_compression_mode = compression_mode;
16657 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
16658 function should use the MIPS16 or microMIPS ISA and switch modes
16662 mips_set_current_function (tree fndecl)
16664 mips_set_compression_mode (mips_get_compress_mode (fndecl));
16667 /* Allocate a chunk of memory for per-function machine-dependent data. */
16669 static struct machine_function *
16670 mips_init_machine_status (void)
16672 return ggc_alloc_cleared_machine_function ();
16675 /* Return the processor associated with the given ISA level, or null
16676 if the ISA isn't valid. */
16678 static const struct mips_cpu_info *
16679 mips_cpu_info_from_isa (int isa)
16683 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
16684 if (mips_cpu_info_table[i].isa == isa)
16685 return mips_cpu_info_table + i;
16690 /* Return a mips_cpu_info entry determined by an option valued
16693 static const struct mips_cpu_info *
16694 mips_cpu_info_from_opt (int opt)
16698 case MIPS_ARCH_OPTION_FROM_ABI:
16699 /* 'from-abi' selects the most compatible architecture for the
16700 given ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit
16701 ABIs. For the EABIs, we have to decide whether we're using
16702 the 32-bit or 64-bit version. */
16703 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
16704 : ABI_NEEDS_64BIT_REGS ? 3
16705 : (TARGET_64BIT ? 3 : 1));
16707 case MIPS_ARCH_OPTION_NATIVE:
16708 gcc_unreachable ();
16711 return &mips_cpu_info_table[opt];
16715 /* Return a default mips_cpu_info entry, given that no -march= option
16716 was explicitly specified. */
16718 static const struct mips_cpu_info *
16719 mips_default_arch (void)
16721 #if defined (MIPS_CPU_STRING_DEFAULT)
16723 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
16724 if (strcmp (mips_cpu_info_table[i].name, MIPS_CPU_STRING_DEFAULT) == 0)
16725 return mips_cpu_info_table + i;
16726 gcc_unreachable ();
16727 #elif defined (MIPS_ISA_DEFAULT)
16728 return mips_cpu_info_from_isa (MIPS_ISA_DEFAULT);
16730 /* 'from-abi' makes a good default: you get whatever the ABI
16732 return mips_cpu_info_from_opt (MIPS_ARCH_OPTION_FROM_ABI);
16736 /* Set up globals to generate code for the ISA or processor
16737 described by INFO. */
16740 mips_set_architecture (const struct mips_cpu_info *info)
16744 mips_arch_info = info;
16745 mips_arch = info->cpu;
16746 mips_isa = info->isa;
16750 /* Likewise for tuning. */
16753 mips_set_tune (const struct mips_cpu_info *info)
16757 mips_tune_info = info;
16758 mips_tune = info->cpu;
16762 /* Implement TARGET_OPTION_OVERRIDE. */
16765 mips_option_override (void)
16767 int i, start, regno, mode;
16769 if (global_options_set.x_mips_isa_option)
16770 mips_isa_option_info = &mips_cpu_info_table[mips_isa_option];
16772 #ifdef SUBTARGET_OVERRIDE_OPTIONS
16773 SUBTARGET_OVERRIDE_OPTIONS;
16776 /* MIPS16 and microMIPS cannot coexist. */
16777 if (TARGET_MICROMIPS && TARGET_MIPS16)
16778 error ("unsupported combination: %s", "-mips16 -mmicromips");
16780 /* Save the base compression state and process flags as though we
16781 were generating uncompressed code. */
16782 mips_base_compression_flags = TARGET_COMPRESSION;
16783 target_flags &= ~TARGET_COMPRESSION;
16785 /* -mno-float overrides -mhard-float and -msoft-float. */
16786 if (TARGET_NO_FLOAT)
16788 target_flags |= MASK_SOFT_FLOAT_ABI;
16789 target_flags_explicit |= MASK_SOFT_FLOAT_ABI;
16792 if (TARGET_FLIP_MIPS16)
16793 TARGET_INTERLINK_COMPRESSED = 1;
16795 /* Set the small data limit. */
16796 mips_small_data_threshold = (global_options_set.x_g_switch_value
16798 : MIPS_DEFAULT_GVALUE);
16800 /* The following code determines the architecture and register size.
16801 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
16802 The GAS and GCC code should be kept in sync as much as possible. */
16804 if (global_options_set.x_mips_arch_option)
16805 mips_set_architecture (mips_cpu_info_from_opt (mips_arch_option));
16807 if (mips_isa_option_info != 0)
16809 if (mips_arch_info == 0)
16810 mips_set_architecture (mips_isa_option_info);
16811 else if (mips_arch_info->isa != mips_isa_option_info->isa)
16812 error ("%<-%s%> conflicts with the other architecture options, "
16813 "which specify a %s processor",
16814 mips_isa_option_info->name,
16815 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
16818 if (mips_arch_info == 0)
16819 mips_set_architecture (mips_default_arch ());
16821 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
16822 error ("%<-march=%s%> is not compatible with the selected ABI",
16823 mips_arch_info->name);
16825 /* Optimize for mips_arch, unless -mtune selects a different processor. */
16826 if (global_options_set.x_mips_tune_option)
16827 mips_set_tune (mips_cpu_info_from_opt (mips_tune_option));
16829 if (mips_tune_info == 0)
16830 mips_set_tune (mips_arch_info);
16832 if ((target_flags_explicit & MASK_64BIT) != 0)
16834 /* The user specified the size of the integer registers. Make sure
16835 it agrees with the ABI and ISA. */
16836 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
16837 error ("%<-mgp64%> used with a 32-bit processor");
16838 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
16839 error ("%<-mgp32%> used with a 64-bit ABI");
16840 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
16841 error ("%<-mgp64%> used with a 32-bit ABI");
16845 /* Infer the integer register size from the ABI and processor.
16846 Restrict ourselves to 32-bit registers if that's all the
16847 processor has, or if the ABI cannot handle 64-bit registers. */
16848 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
16849 target_flags &= ~MASK_64BIT;
16851 target_flags |= MASK_64BIT;
16854 if ((target_flags_explicit & MASK_FLOAT64) != 0)
16856 if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
16857 error ("unsupported combination: %s", "-mfp64 -msingle-float");
16858 else if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
16859 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
16860 else if (!TARGET_64BIT && TARGET_FLOAT64)
16862 if (!ISA_HAS_MXHC1)
16863 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
16864 " the target supports the mfhc1 and mthc1 instructions");
16865 else if (mips_abi != ABI_32)
16866 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
16872 /* -msingle-float selects 32-bit float registers. Otherwise the
16873 float registers should be the same size as the integer ones. */
16874 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
16875 target_flags |= MASK_FLOAT64;
16877 target_flags &= ~MASK_FLOAT64;
16880 /* End of code shared with GAS. */
16882 /* The R5900 FPU only supports single precision. */
16883 if (TARGET_MIPS5900 && TARGET_HARD_FLOAT_ABI && TARGET_DOUBLE_FLOAT)
16884 error ("unsupported combination: %s",
16885 "-march=r5900 -mhard-float -mdouble-float");
16887 /* If a -mlong* option was given, check that it matches the ABI,
16888 otherwise infer the -mlong* setting from the other options. */
16889 if ((target_flags_explicit & MASK_LONG64) != 0)
16893 if (mips_abi == ABI_N32)
16894 error ("%qs is incompatible with %qs", "-mabi=n32", "-mlong64");
16895 else if (mips_abi == ABI_32)
16896 error ("%qs is incompatible with %qs", "-mabi=32", "-mlong64");
16897 else if (mips_abi == ABI_O64 && TARGET_ABICALLS)
16898 /* We have traditionally allowed non-abicalls code to use
16899 an LP64 form of o64. However, it would take a bit more
16900 effort to support the combination of 32-bit GOT entries
16901 and 64-bit pointers, so we treat the abicalls case as
16903 error ("the combination of %qs and %qs is incompatible with %qs",
16904 "-mabi=o64", "-mabicalls", "-mlong64");
16908 if (mips_abi == ABI_64)
16909 error ("%qs is incompatible with %qs", "-mabi=64", "-mlong32");
16914 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
16915 target_flags |= MASK_LONG64;
16917 target_flags &= ~MASK_LONG64;
16920 if (!TARGET_OLDABI)
16921 flag_pcc_struct_return = 0;
16923 /* Decide which rtx_costs structure to use. */
16925 mips_cost = &mips_rtx_cost_optimize_size;
16927 mips_cost = &mips_rtx_cost_data[mips_tune];
16929 /* If the user hasn't specified a branch cost, use the processor's
16931 if (mips_branch_cost == 0)
16932 mips_branch_cost = mips_cost->branch_cost;
16934 /* If neither -mbranch-likely nor -mno-branch-likely was given
16935 on the command line, set MASK_BRANCHLIKELY based on the target
16936 architecture and tuning flags. Annulled delay slots are a
16937 size win, so we only consider the processor-specific tuning
16938 for !optimize_size. */
16939 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
16941 if (ISA_HAS_BRANCHLIKELY
16943 || (mips_tune_info->tune_flags & PTF_AVOID_BRANCHLIKELY) == 0))
16944 target_flags |= MASK_BRANCHLIKELY;
16946 target_flags &= ~MASK_BRANCHLIKELY;
16948 else if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
16949 warning (0, "the %qs architecture does not support branch-likely"
16950 " instructions", mips_arch_info->name);
16952 /* If the user hasn't specified -mimadd or -mno-imadd set
16953 MASK_IMADD based on the target architecture and tuning
16955 if ((target_flags_explicit & MASK_IMADD) == 0)
16957 if (ISA_HAS_MADD_MSUB &&
16958 (mips_tune_info->tune_flags & PTF_AVOID_IMADD) == 0)
16959 target_flags |= MASK_IMADD;
16961 target_flags &= ~MASK_IMADD;
16963 else if (TARGET_IMADD && !ISA_HAS_MADD_MSUB)
16964 warning (0, "the %qs architecture does not support madd or msub"
16965 " instructions", mips_arch_info->name);
16967 /* The effect of -mabicalls isn't defined for the EABI. */
16968 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
16970 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
16971 target_flags &= ~MASK_ABICALLS;
16974 /* PIC requires -mabicalls. */
16977 if (mips_abi == ABI_EABI)
16978 error ("cannot generate position-independent code for %qs",
16980 else if (!TARGET_ABICALLS)
16981 error ("position-independent code requires %qs", "-mabicalls");
16984 if (TARGET_ABICALLS_PIC2)
16985 /* We need to set flag_pic for executables as well as DSOs
16986 because we may reference symbols that are not defined in
16987 the final executable. (MIPS does not use things like
16988 copy relocs, for example.)
16990 There is a body of code that uses __PIC__ to distinguish
16991 between -mabicalls and -mno-abicalls code. The non-__PIC__
16992 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
16993 long as any indirect jumps use $25. */
16996 /* -mvr4130-align is a "speed over size" optimization: it usually produces
16997 faster code, but at the expense of more nops. Enable it at -O3 and
16999 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
17000 target_flags |= MASK_VR4130_ALIGN;
17002 /* Prefer a call to memcpy over inline code when optimizing for size,
17003 though see MOVE_RATIO in mips.h. */
17004 if (optimize_size && (target_flags_explicit & MASK_MEMCPY) == 0)
17005 target_flags |= MASK_MEMCPY;
17007 /* If we have a nonzero small-data limit, check that the -mgpopt
17008 setting is consistent with the other target flags. */
17009 if (mips_small_data_threshold > 0)
17013 if (!TARGET_EXPLICIT_RELOCS)
17014 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
17016 TARGET_LOCAL_SDATA = false;
17017 TARGET_EXTERN_SDATA = false;
17021 if (TARGET_VXWORKS_RTP)
17022 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
17024 if (TARGET_ABICALLS)
17025 warning (0, "cannot use small-data accesses for %qs",
17030 /* Pre-IEEE 754-2008 MIPS hardware has a quirky almost-IEEE format
17031 for all its floating point. */
17032 if (mips_nan != MIPS_IEEE_754_2008)
17034 REAL_MODE_FORMAT (SFmode) = &mips_single_format;
17035 REAL_MODE_FORMAT (DFmode) = &mips_double_format;
17036 REAL_MODE_FORMAT (TFmode) = &mips_quad_format;
17039 /* Make sure that the user didn't turn off paired single support when
17040 MIPS-3D support is requested. */
17042 && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
17043 && !TARGET_PAIRED_SINGLE_FLOAT)
17044 error ("%<-mips3d%> requires %<-mpaired-single%>");
17046 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
17048 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
17050 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
17051 and TARGET_HARD_FLOAT_ABI are both true. */
17052 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT_ABI))
17053 error ("%qs must be used with %qs",
17054 TARGET_MIPS3D ? "-mips3d" : "-mpaired-single",
17055 TARGET_HARD_FLOAT_ABI ? "-mfp64" : "-mhard-float");
17057 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
17059 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_HAS_PAIRED_SINGLE)
17060 warning (0, "the %qs architecture does not support paired-single"
17061 " instructions", mips_arch_info->name);
17063 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
17064 && !TARGET_CACHE_BUILTIN)
17066 error ("%qs requires a target that provides the %qs instruction",
17067 "-mr10k-cache-barrier", "cache");
17068 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE;
17071 /* If TARGET_DSPR2, enable MASK_DSP. */
17073 target_flags |= MASK_DSP;
17075 /* .eh_frame addresses should be the same width as a C pointer.
17076 Most MIPS ABIs support only one pointer size, so the assembler
17077 will usually know exactly how big an .eh_frame address is.
17079 Unfortunately, this is not true of the 64-bit EABI. The ABI was
17080 originally defined to use 64-bit pointers (i.e. it is LP64), and
17081 this is still the default mode. However, we also support an n32-like
17082 ILP32 mode, which is selected by -mlong32. The problem is that the
17083 assembler has traditionally not had an -mlong option, so it has
17084 traditionally not known whether we're using the ILP32 or LP64 form.
17086 As it happens, gas versions up to and including 2.19 use _32-bit_
17087 addresses for EABI64 .cfi_* directives. This is wrong for the
17088 default LP64 mode, so we can't use the directives by default.
17089 Moreover, since gas's current behavior is at odds with gcc's
17090 default behavior, it seems unwise to rely on future versions
17091 of gas behaving the same way. We therefore avoid using .cfi
17092 directives for -mlong32 as well. */
17093 if (mips_abi == ABI_EABI && TARGET_64BIT)
17094 flag_dwarf2_cfi_asm = 0;
17096 /* .cfi_* directives generate a read-only section, so fall back on
17097 manual .eh_frame creation if we need the section to be writable. */
17098 if (TARGET_WRITABLE_EH_FRAME)
17099 flag_dwarf2_cfi_asm = 0;
17101 mips_init_print_operand_punct ();
17103 /* Set up array to map GCC register number to debug register number.
17104 Ignore the special purpose register numbers. */
17106 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
17108 mips_dbx_regno[i] = IGNORED_DWARF_REGNUM;
17109 if (GP_REG_P (i) || FP_REG_P (i) || ALL_COP_REG_P (i))
17110 mips_dwarf_regno[i] = i;
17112 mips_dwarf_regno[i] = INVALID_REGNUM;
17115 start = GP_DBX_FIRST - GP_REG_FIRST;
17116 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
17117 mips_dbx_regno[i] = i + start;
17119 start = FP_DBX_FIRST - FP_REG_FIRST;
17120 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
17121 mips_dbx_regno[i] = i + start;
17123 /* Accumulator debug registers use big-endian ordering. */
17124 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
17125 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
17126 mips_dwarf_regno[HI_REGNUM] = MD_REG_FIRST + 0;
17127 mips_dwarf_regno[LO_REGNUM] = MD_REG_FIRST + 1;
17128 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
17130 mips_dwarf_regno[i + TARGET_LITTLE_ENDIAN] = i;
17131 mips_dwarf_regno[i + TARGET_BIG_ENDIAN] = i + 1;
17134 /* Set up mips_hard_regno_mode_ok. */
17135 for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
17136 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
17137 mips_hard_regno_mode_ok[mode][regno]
17138 = mips_hard_regno_mode_ok_p (regno, (enum machine_mode) mode);
17140 /* Function to allocate machine-dependent function status. */
17141 init_machine_status = &mips_init_machine_status;
17143 /* Default to working around R4000 errata only if the processor
17144 was selected explicitly. */
17145 if ((target_flags_explicit & MASK_FIX_R4000) == 0
17146 && strcmp (mips_arch_info->name, "r4000") == 0)
17147 target_flags |= MASK_FIX_R4000;
17149 /* Default to working around R4400 errata only if the processor
17150 was selected explicitly. */
17151 if ((target_flags_explicit & MASK_FIX_R4400) == 0
17152 && strcmp (mips_arch_info->name, "r4400") == 0)
17153 target_flags |= MASK_FIX_R4400;
17155 /* Default to working around R10000 errata only if the processor
17156 was selected explicitly. */
17157 if ((target_flags_explicit & MASK_FIX_R10000) == 0
17158 && strcmp (mips_arch_info->name, "r10000") == 0)
17159 target_flags |= MASK_FIX_R10000;
17161 /* Make sure that branch-likely instructions available when using
17162 -mfix-r10000. The instructions are not available if either:
17164 1. -mno-branch-likely was passed.
17165 2. The selected ISA does not support branch-likely and
17166 the command line does not include -mbranch-likely. */
17167 if (TARGET_FIX_R10000
17168 && ((target_flags_explicit & MASK_BRANCHLIKELY) == 0
17169 ? !ISA_HAS_BRANCHLIKELY
17170 : !TARGET_BRANCHLIKELY))
17171 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
17173 if (TARGET_SYNCI && !ISA_HAS_SYNCI)
17175 warning (0, "the %qs architecture does not support the synci "
17176 "instruction", mips_arch_info->name);
17177 target_flags &= ~MASK_SYNCI;
17180 /* Only optimize PIC indirect calls if they are actually required. */
17181 if (!TARGET_USE_GOT || !TARGET_EXPLICIT_RELOCS)
17182 target_flags &= ~MASK_RELAX_PIC_CALLS;
17184 /* Save base state of options. */
17185 mips_base_target_flags = target_flags;
17186 mips_base_schedule_insns = flag_schedule_insns;
17187 mips_base_reorder_blocks_and_partition = flag_reorder_blocks_and_partition;
17188 mips_base_move_loop_invariants = flag_move_loop_invariants;
17189 mips_base_align_loops = align_loops;
17190 mips_base_align_jumps = align_jumps;
17191 mips_base_align_functions = align_functions;
17193 /* Now select the ISA mode.
17195 Do all CPP-sensitive stuff in uncompressed mode; we'll switch modes
17196 later if required. */
17197 mips_set_compression_mode (0);
17199 /* We register a second machine specific reorg pass after delay slot
17200 filling. Registering the pass must be done at start up. It's
17201 convenient to do it here. */
17202 opt_pass *new_pass = make_pass_mips_machine_reorg2 (g);
17203 struct register_pass_info insert_pass_mips_machine_reorg2 =
17205 new_pass, /* pass */
17206 "dbr", /* reference_pass_name */
17207 1, /* ref_pass_instance_number */
17208 PASS_POS_INSERT_AFTER /* po_op */
17210 register_pass (&insert_pass_mips_machine_reorg2);
17212 if (TARGET_HARD_FLOAT_ABI && TARGET_MIPS5900)
17213 REAL_MODE_FORMAT (SFmode) = &spu_single_format;
17216 /* Swap the register information for registers I and I + 1, which
17217 currently have the wrong endianness. Note that the registers'
17218 fixedness and call-clobberedness might have been set on the
17222 mips_swap_registers (unsigned int i)
17227 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
17228 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
17230 SWAP_INT (fixed_regs[i], fixed_regs[i + 1]);
17231 SWAP_INT (call_used_regs[i], call_used_regs[i + 1]);
17232 SWAP_INT (call_really_used_regs[i], call_really_used_regs[i + 1]);
17233 SWAP_STRING (reg_names[i], reg_names[i + 1]);
17239 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
17242 mips_conditional_register_usage (void)
17247 /* These DSP control register fields are global. */
17248 global_regs[CCDSP_PO_REGNUM] = 1;
17249 global_regs[CCDSP_SC_REGNUM] = 1;
17252 AND_COMPL_HARD_REG_SET (accessible_reg_set,
17253 reg_class_contents[(int) DSP_ACC_REGS]);
17255 if (!TARGET_HARD_FLOAT)
17257 AND_COMPL_HARD_REG_SET (accessible_reg_set,
17258 reg_class_contents[(int) FP_REGS]);
17259 AND_COMPL_HARD_REG_SET (accessible_reg_set,
17260 reg_class_contents[(int) ST_REGS]);
17262 else if (!ISA_HAS_8CC)
17264 /* We only have a single condition-code register. We implement
17265 this by fixing all the condition-code registers and generating
17266 RTL that refers directly to ST_REG_FIRST. */
17267 AND_COMPL_HARD_REG_SET (accessible_reg_set,
17268 reg_class_contents[(int) ST_REGS]);
17269 SET_HARD_REG_BIT (accessible_reg_set, FPSW_REGNUM);
17270 fixed_regs[FPSW_REGNUM] = call_used_regs[FPSW_REGNUM] = 1;
17274 /* In MIPS16 mode, we prohibit the unused $s registers, since they
17275 are call-saved, and saving them via a MIPS16 register would
17276 probably waste more time than just reloading the value.
17278 We permit the $t temporary registers when optimizing for speed
17279 but not when optimizing for space because using them results in
17280 code that is larger (but faster) then not using them. We do
17281 allow $24 (t8) because it is used in CMP and CMPI instructions
17282 and $25 (t9) because it is used as the function call address in
17285 fixed_regs[18] = call_used_regs[18] = 1;
17286 fixed_regs[19] = call_used_regs[19] = 1;
17287 fixed_regs[20] = call_used_regs[20] = 1;
17288 fixed_regs[21] = call_used_regs[21] = 1;
17289 fixed_regs[22] = call_used_regs[22] = 1;
17290 fixed_regs[23] = call_used_regs[23] = 1;
17291 fixed_regs[26] = call_used_regs[26] = 1;
17292 fixed_regs[27] = call_used_regs[27] = 1;
17293 fixed_regs[30] = call_used_regs[30] = 1;
17296 fixed_regs[8] = call_used_regs[8] = 1;
17297 fixed_regs[9] = call_used_regs[9] = 1;
17298 fixed_regs[10] = call_used_regs[10] = 1;
17299 fixed_regs[11] = call_used_regs[11] = 1;
17300 fixed_regs[12] = call_used_regs[12] = 1;
17301 fixed_regs[13] = call_used_regs[13] = 1;
17302 fixed_regs[14] = call_used_regs[14] = 1;
17303 fixed_regs[15] = call_used_regs[15] = 1;
17306 /* Do not allow HI and LO to be treated as register operands.
17307 There are no MTHI or MTLO instructions (or any real need
17308 for them) and one-way registers cannot easily be reloaded. */
17309 AND_COMPL_HARD_REG_SET (operand_reg_set,
17310 reg_class_contents[(int) MD_REGS]);
17312 /* $f20-$f23 are call-clobbered for n64. */
17313 if (mips_abi == ABI_64)
17316 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
17317 call_really_used_regs[regno] = call_used_regs[regno] = 1;
17319 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
17321 if (mips_abi == ABI_N32)
17324 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
17325 call_really_used_regs[regno] = call_used_regs[regno] = 1;
17327 /* Make sure that double-register accumulator values are correctly
17328 ordered for the current endianness. */
17329 if (TARGET_LITTLE_ENDIAN)
17331 unsigned int regno;
17333 mips_swap_registers (MD_REG_FIRST);
17334 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno += 2)
17335 mips_swap_registers (regno);
17339 /* When generating MIPS16 code, we want to allocate $24 (T_REG) before
17340 other registers for instructions for which it is possible. This
17341 encourages the compiler to use CMP in cases where an XOR would
17342 require some register shuffling. */
17345 mips_order_regs_for_local_alloc (void)
17349 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
17350 reg_alloc_order[i] = i;
17354 /* It really doesn't matter where we put register 0, since it is
17355 a fixed register anyhow. */
17356 reg_alloc_order[0] = 24;
17357 reg_alloc_order[24] = 0;
17361 /* Implement EH_USES. */
17364 mips_eh_uses (unsigned int regno)
17366 if (reload_completed && !TARGET_ABSOLUTE_JUMPS)
17368 /* We need to force certain registers to be live in order to handle
17369 PIC long branches correctly. See mips_must_initialize_gp_p for
17371 if (mips_cfun_has_cprestore_slot_p ())
17373 if (regno == CPRESTORE_SLOT_REGNUM)
17378 if (cfun->machine->global_pointer == regno)
17386 /* Implement EPILOGUE_USES. */
17389 mips_epilogue_uses (unsigned int regno)
17391 /* Say that the epilogue uses the return address register. Note that
17392 in the case of sibcalls, the values "used by the epilogue" are
17393 considered live at the start of the called function. */
17394 if (regno == RETURN_ADDR_REGNUM)
17397 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
17398 See the comment above load_call<mode> for details. */
17399 if (TARGET_USE_GOT && (regno) == GOT_VERSION_REGNUM)
17402 /* An interrupt handler must preserve some registers that are
17403 ordinarily call-clobbered. */
17404 if (cfun->machine->interrupt_handler_p
17405 && mips_interrupt_extra_call_saved_reg_p (regno))
17411 /* A for_each_rtx callback. Stop the search if *X is an AT register. */
17414 mips_at_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
17416 return REG_P (*x) && REGNO (*x) == AT_REGNUM;
17419 /* Return true if INSN needs to be wrapped in ".set noat".
17420 INSN has NOPERANDS operands, stored in OPVEC. */
17423 mips_need_noat_wrapper_p (rtx insn, rtx *opvec, int noperands)
17427 if (recog_memoized (insn) >= 0)
17428 for (i = 0; i < noperands; i++)
17429 if (for_each_rtx (&opvec[i], mips_at_reg_p, NULL))
17434 /* Implement FINAL_PRESCAN_INSN. */
17437 mips_final_prescan_insn (rtx insn, rtx *opvec, int noperands)
17439 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
17440 mips_push_asm_switch (&mips_noat);
17443 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */
17446 mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED, rtx insn,
17447 rtx *opvec, int noperands)
17449 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
17450 mips_pop_asm_switch (&mips_noat);
17453 /* Return the function that is used to expand the <u>mulsidi3 pattern.
17454 EXT_CODE is the code of the extension used. Return NULL if widening
17455 multiplication shouldn't be used. */
17458 mips_mulsidi3_gen_fn (enum rtx_code ext_code)
17462 signed_p = ext_code == SIGN_EXTEND;
17465 /* Don't use widening multiplication with MULT when we have DMUL. Even
17466 with the extension of its input operands DMUL is faster. Note that
17467 the extension is not needed for signed multiplication. In order to
17468 ensure that we always remove the redundant sign-extension in this
17469 case we still expand mulsidi3 for DMUL. */
17471 return signed_p ? gen_mulsidi3_64bit_dmul : NULL;
17474 ? gen_mulsidi3_64bit_mips16
17475 : gen_umulsidi3_64bit_mips16);
17476 if (TARGET_FIX_R4000)
17478 return signed_p ? gen_mulsidi3_64bit : gen_umulsidi3_64bit;
17484 ? gen_mulsidi3_32bit_mips16
17485 : gen_umulsidi3_32bit_mips16);
17486 if (TARGET_FIX_R4000 && !ISA_HAS_DSP)
17487 return signed_p ? gen_mulsidi3_32bit_r4000 : gen_umulsidi3_32bit_r4000;
17488 return signed_p ? gen_mulsidi3_32bit : gen_umulsidi3_32bit;
17492 /* Return true if PATTERN matches the kind of instruction generated by
17493 umips_build_save_restore. SAVE_P is true for store. */
17496 umips_save_restore_pattern_p (bool save_p, rtx pattern)
17500 HOST_WIDE_INT first_offset = 0;
17501 rtx first_base = 0;
17502 unsigned int regmask = 0;
17504 for (n = 0; n < XVECLEN (pattern, 0); n++)
17506 rtx set, reg, mem, this_base;
17507 HOST_WIDE_INT this_offset;
17509 /* Check that we have a SET. */
17510 set = XVECEXP (pattern, 0, n);
17511 if (GET_CODE (set) != SET)
17514 /* Check that the SET is a load (if restoring) or a store
17516 mem = save_p ? SET_DEST (set) : SET_SRC (set);
17517 if (!MEM_P (mem) || MEM_VOLATILE_P (mem))
17520 /* Check that the address is the sum of base and a possibly-zero
17521 constant offset. Determine if the offset is in range. */
17522 mips_split_plus (XEXP (mem, 0), &this_base, &this_offset);
17523 if (!REG_P (this_base))
17528 if (!UMIPS_12BIT_OFFSET_P (this_offset))
17530 first_base = this_base;
17531 first_offset = this_offset;
17535 /* Check that the save slots are consecutive. */
17536 if (REGNO (this_base) != REGNO (first_base)
17537 || this_offset != first_offset + UNITS_PER_WORD * n)
17541 /* Check that SET's other operand is a register. */
17542 reg = save_p ? SET_SRC (set) : SET_DEST (set);
17546 regmask |= 1 << REGNO (reg);
17549 for (i = 0; i < ARRAY_SIZE (umips_swm_mask); i++)
17550 if (regmask == umips_swm_mask[i])
17556 /* Return the assembly instruction for microMIPS LWM or SWM.
17557 SAVE_P and PATTERN are as for umips_save_restore_pattern_p. */
17560 umips_output_save_restore (bool save_p, rtx pattern)
17562 static char buffer[300];
17565 HOST_WIDE_INT offset;
17566 rtx base, mem, set, last_set, last_reg;
17568 /* Parse the pattern. */
17569 gcc_assert (umips_save_restore_pattern_p (save_p, pattern));
17571 s = strcpy (buffer, save_p ? "swm\t" : "lwm\t");
17573 n = XVECLEN (pattern, 0);
17575 set = XVECEXP (pattern, 0, 0);
17576 mem = save_p ? SET_DEST (set) : SET_SRC (set);
17577 mips_split_plus (XEXP (mem, 0), &base, &offset);
17579 last_set = XVECEXP (pattern, 0, n - 1);
17580 last_reg = save_p ? SET_SRC (last_set) : SET_DEST (last_set);
17582 if (REGNO (last_reg) == 31)
17585 gcc_assert (n <= 9);
17589 s += sprintf (s, "%s,", reg_names[16]);
17591 s += sprintf (s, "%s-%s,", reg_names[16], reg_names[15 + n]);
17593 s += sprintf (s, "%s-%s,%s,", reg_names[16], reg_names[23],
17596 if (REGNO (last_reg) == 31)
17597 s += sprintf (s, "%s,", reg_names[31]);
17599 s += sprintf (s, "%d(%s)", (int)offset, reg_names[REGNO (base)]);
17603 /* Return true if MEM1 and MEM2 use the same base register, and the
17604 offset of MEM2 equals the offset of MEM1 plus 4. FIRST_REG is the
17605 register into (from) which the contents of MEM1 will be loaded
17606 (stored), depending on the value of LOAD_P.
17607 SWAP_P is true when the 1st and 2nd instructions are swapped. */
17610 umips_load_store_pair_p_1 (bool load_p, bool swap_p,
17611 rtx first_reg, rtx mem1, rtx mem2)
17614 HOST_WIDE_INT offset1, offset2;
17616 if (!MEM_P (mem1) || !MEM_P (mem2))
17619 mips_split_plus (XEXP (mem1, 0), &base1, &offset1);
17620 mips_split_plus (XEXP (mem2, 0), &base2, &offset2);
17622 if (!REG_P (base1) || !rtx_equal_p (base1, base2))
17625 /* Avoid invalid load pair instructions. */
17626 if (load_p && REGNO (first_reg) == REGNO (base1))
17629 /* We must avoid this case for anti-dependence.
17632 first_reg is $2, but the base is $3. */
17635 && REGNO (first_reg) + 1 == REGNO (base1))
17638 if (offset2 != offset1 + 4)
17641 if (!UMIPS_12BIT_OFFSET_P (offset1))
17647 /* OPERANDS describes the operands to a pair of SETs, in the order
17648 dest1, src1, dest2, src2. Return true if the operands can be used
17649 in an LWP or SWP instruction; LOAD_P says which. */
17652 umips_load_store_pair_p (bool load_p, rtx *operands)
17654 rtx reg1, reg2, mem1, mem2;
17658 reg1 = operands[0];
17659 reg2 = operands[2];
17660 mem1 = operands[1];
17661 mem2 = operands[3];
17665 reg1 = operands[1];
17666 reg2 = operands[3];
17667 mem1 = operands[0];
17668 mem2 = operands[2];
17671 if (REGNO (reg2) == REGNO (reg1) + 1)
17672 return umips_load_store_pair_p_1 (load_p, false, reg1, mem1, mem2);
17674 if (REGNO (reg1) == REGNO (reg2) + 1)
17675 return umips_load_store_pair_p_1 (load_p, true, reg2, mem2, mem1);
17680 /* Return the assembly instruction for a microMIPS LWP or SWP in which
17681 the first register is REG and the first memory slot is MEM.
17682 LOAD_P is true for LWP. */
17685 umips_output_load_store_pair_1 (bool load_p, rtx reg, rtx mem)
17687 rtx ops[] = {reg, mem};
17690 output_asm_insn ("lwp\t%0,%1", ops);
17692 output_asm_insn ("swp\t%0,%1", ops);
17695 /* Output the assembly instruction for a microMIPS LWP or SWP instruction.
17696 LOAD_P and OPERANDS are as for umips_load_store_pair_p. */
17699 umips_output_load_store_pair (bool load_p, rtx *operands)
17701 rtx reg1, reg2, mem1, mem2;
17704 reg1 = operands[0];
17705 reg2 = operands[2];
17706 mem1 = operands[1];
17707 mem2 = operands[3];
17711 reg1 = operands[1];
17712 reg2 = operands[3];
17713 mem1 = operands[0];
17714 mem2 = operands[2];
17717 if (REGNO (reg2) == REGNO (reg1) + 1)
17719 umips_output_load_store_pair_1 (load_p, reg1, mem1);
17723 gcc_assert (REGNO (reg1) == REGNO (reg2) + 1);
17724 umips_output_load_store_pair_1 (load_p, reg2, mem2);
17727 /* Return true if REG1 and REG2 match the criteria for a movep insn. */
17730 umips_movep_target_p (rtx reg1, rtx reg2)
17732 int regno1, regno2, pair;
17734 static const int match[8] = {
17735 0x00000060, /* 5, 6 */
17736 0x000000a0, /* 5, 7 */
17737 0x000000c0, /* 6, 7 */
17738 0x00200010, /* 4, 21 */
17739 0x00400010, /* 4, 22 */
17740 0x00000030, /* 4, 5 */
17741 0x00000050, /* 4, 6 */
17742 0x00000090 /* 4, 7 */
17745 if (!REG_P (reg1) || !REG_P (reg2))
17748 regno1 = REGNO (reg1);
17749 regno2 = REGNO (reg2);
17751 if (!GP_REG_P (regno1) || !GP_REG_P (regno2))
17754 pair = (1 << regno1) | (1 << regno2);
17756 for (i = 0; i < ARRAY_SIZE (match); i++)
17757 if (pair == match[i])
17763 /* Return the size in bytes of the trampoline code, padded to
17764 TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target
17765 function address immediately follow. */
17768 mips_trampoline_code_size (void)
17770 if (TARGET_USE_PIC_FN_ADDR_REG)
17772 else if (ptr_mode == DImode)
17774 else if (ISA_HAS_LOAD_DELAY)
17780 /* Implement TARGET_TRAMPOLINE_INIT. */
17783 mips_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
17785 rtx addr, end_addr, high, low, opcode, mem;
17788 HOST_WIDE_INT end_addr_offset, static_chain_offset, target_function_offset;
17790 /* Work out the offsets of the pointers from the start of the
17791 trampoline code. */
17792 end_addr_offset = mips_trampoline_code_size ();
17793 static_chain_offset = end_addr_offset;
17794 target_function_offset = static_chain_offset + GET_MODE_SIZE (ptr_mode);
17796 /* Get pointers to the beginning and end of the code block. */
17797 addr = force_reg (Pmode, XEXP (m_tramp, 0));
17798 end_addr = mips_force_binary (Pmode, PLUS, addr, GEN_INT (end_addr_offset));
17800 #define OP(X) gen_int_mode (X, SImode)
17802 /* Build up the code in TRAMPOLINE. */
17804 if (TARGET_USE_PIC_FN_ADDR_REG)
17806 /* $25 contains the address of the trampoline. Emit code of the form:
17808 l[wd] $1, target_function_offset($25)
17809 l[wd] $static_chain, static_chain_offset($25)
17812 trampoline[i++] = OP (MIPS_LOAD_PTR (AT_REGNUM,
17813 target_function_offset,
17814 PIC_FUNCTION_ADDR_REGNUM));
17815 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
17816 static_chain_offset,
17817 PIC_FUNCTION_ADDR_REGNUM));
17818 trampoline[i++] = OP (MIPS_JR (AT_REGNUM));
17819 trampoline[i++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM, AT_REGNUM));
17821 else if (ptr_mode == DImode)
17823 /* It's too cumbersome to create the full 64-bit address, so let's
17829 1: l[wd] $25, target_function_offset - 12($31)
17830 l[wd] $static_chain, static_chain_offset - 12($31)
17834 where 12 is the offset of "1:" from the start of the code block. */
17835 trampoline[i++] = OP (MIPS_MOVE (AT_REGNUM, RETURN_ADDR_REGNUM));
17836 trampoline[i++] = OP (MIPS_BAL (1));
17837 trampoline[i++] = OP (MIPS_NOP);
17838 trampoline[i++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
17839 target_function_offset - 12,
17840 RETURN_ADDR_REGNUM));
17841 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
17842 static_chain_offset - 12,
17843 RETURN_ADDR_REGNUM));
17844 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
17845 trampoline[i++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM, AT_REGNUM));
17849 /* If the target has load delays, emit:
17851 lui $1, %hi(end_addr)
17852 lw $25, %lo(end_addr + ...)($1)
17853 lw $static_chain, %lo(end_addr + ...)($1)
17859 lui $1, %hi(end_addr)
17860 lw $25, %lo(end_addr + ...)($1)
17862 lw $static_chain, %lo(end_addr + ...)($1). */
17864 /* Split END_ADDR into %hi and %lo values. Trampolines are aligned
17865 to 64 bits, so the %lo value will have the bottom 3 bits clear. */
17866 high = expand_simple_binop (SImode, PLUS, end_addr, GEN_INT (0x8000),
17867 NULL, false, OPTAB_WIDEN);
17868 high = expand_simple_binop (SImode, LSHIFTRT, high, GEN_INT (16),
17869 NULL, false, OPTAB_WIDEN);
17870 low = convert_to_mode (SImode, gen_lowpart (HImode, end_addr), true);
17872 /* Emit the LUI. */
17873 opcode = OP (MIPS_LUI (AT_REGNUM, 0));
17874 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, high,
17875 NULL, false, OPTAB_WIDEN);
17877 /* Emit the load of the target function. */
17878 opcode = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
17879 target_function_offset - end_addr_offset,
17881 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
17882 NULL, false, OPTAB_WIDEN);
17884 /* Emit the JR here, if we can. */
17885 if (!ISA_HAS_LOAD_DELAY)
17886 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
17888 /* Emit the load of the static chain register. */
17889 opcode = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
17890 static_chain_offset - end_addr_offset,
17892 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
17893 NULL, false, OPTAB_WIDEN);
17895 /* Emit the JR, if we couldn't above. */
17896 if (ISA_HAS_LOAD_DELAY)
17898 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
17899 trampoline[i++] = OP (MIPS_NOP);
17905 /* Copy the trampoline code. Leave any padding uninitialized. */
17906 for (j = 0; j < i; j++)
17908 mem = adjust_address (m_tramp, SImode, j * GET_MODE_SIZE (SImode));
17909 mips_emit_move (mem, trampoline[j]);
17912 /* Set up the static chain pointer field. */
17913 mem = adjust_address (m_tramp, ptr_mode, static_chain_offset);
17914 mips_emit_move (mem, chain_value);
17916 /* Set up the target function field. */
17917 mem = adjust_address (m_tramp, ptr_mode, target_function_offset);
17918 mips_emit_move (mem, XEXP (DECL_RTL (fndecl), 0));
17920 /* Flush the code part of the trampoline. */
17921 emit_insn (gen_add3_insn (end_addr, addr, GEN_INT (TRAMPOLINE_SIZE)));
17922 emit_insn (gen_clear_cache (addr, end_addr));
17925 /* Implement FUNCTION_PROFILER. */
17927 void mips_function_profiler (FILE *file)
17930 sorry ("mips16 function profiling");
17931 if (TARGET_LONG_CALLS)
17933 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */
17934 if (Pmode == DImode)
17935 fprintf (file, "\tdla\t%s,_mcount\n", reg_names[3]);
17937 fprintf (file, "\tla\t%s,_mcount\n", reg_names[3]);
17939 mips_push_asm_switch (&mips_noat);
17940 fprintf (file, "\tmove\t%s,%s\t\t# save current return address\n",
17941 reg_names[AT_REGNUM], reg_names[RETURN_ADDR_REGNUM]);
17942 /* _mcount treats $2 as the static chain register. */
17943 if (cfun->static_chain_decl != NULL)
17944 fprintf (file, "\tmove\t%s,%s\n", reg_names[2],
17945 reg_names[STATIC_CHAIN_REGNUM]);
17946 if (TARGET_MCOUNT_RA_ADDRESS)
17948 /* If TARGET_MCOUNT_RA_ADDRESS load $12 with the address of the
17949 ra save location. */
17950 if (cfun->machine->frame.ra_fp_offset == 0)
17951 /* ra not saved, pass zero. */
17952 fprintf (file, "\tmove\t%s,%s\n", reg_names[12], reg_names[0]);
17954 fprintf (file, "\t%s\t%s," HOST_WIDE_INT_PRINT_DEC "(%s)\n",
17955 Pmode == DImode ? "dla" : "la", reg_names[12],
17956 cfun->machine->frame.ra_fp_offset,
17957 reg_names[STACK_POINTER_REGNUM]);
17959 if (!TARGET_NEWABI)
17961 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n",
17962 TARGET_64BIT ? "dsubu" : "subu",
17963 reg_names[STACK_POINTER_REGNUM],
17964 reg_names[STACK_POINTER_REGNUM],
17965 Pmode == DImode ? 16 : 8);
17967 if (TARGET_LONG_CALLS)
17968 fprintf (file, "\tjalr\t%s\n", reg_names[3]);
17970 fprintf (file, "\tjal\t_mcount\n");
17971 mips_pop_asm_switch (&mips_noat);
17972 /* _mcount treats $2 as the static chain register. */
17973 if (cfun->static_chain_decl != NULL)
17974 fprintf (file, "\tmove\t%s,%s\n", reg_names[STATIC_CHAIN_REGNUM],
17978 /* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default
17979 behaviour of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even
17980 when TARGET_LOONGSON_VECTORS is true. */
17982 static unsigned HOST_WIDE_INT
17983 mips_shift_truncation_mask (enum machine_mode mode)
17985 if (TARGET_LOONGSON_VECTORS && VECTOR_MODE_P (mode))
17988 return GET_MODE_BITSIZE (mode) - 1;
17991 /* Implement TARGET_PREPARE_PCH_SAVE. */
17994 mips_prepare_pch_save (void)
17996 /* We are called in a context where the current MIPS16 vs. non-MIPS16
17997 setting should be irrelevant. The question then is: which setting
17998 makes most sense at load time?
18000 The PCH is loaded before the first token is read. We should never
18001 have switched into MIPS16 mode by that point, and thus should not
18002 have populated mips16_globals. Nor can we load the entire contents
18003 of mips16_globals from the PCH file, because mips16_globals contains
18004 a combination of GGC and non-GGC data.
18006 There is therefore no point in trying save the GGC part of
18007 mips16_globals to the PCH file, or to preserve MIPS16ness across
18008 the PCH save and load. The loading compiler would not have access
18009 to the non-GGC parts of mips16_globals (either from the PCH file,
18010 or from a copy that the loading compiler generated itself) and would
18011 have to call target_reinit anyway.
18013 It therefore seems best to switch back to non-MIPS16 mode at
18014 save time, and to ensure that mips16_globals remains null after
18016 mips_set_compression_mode (0);
18017 mips16_globals = 0;
18020 /* Generate or test for an insn that supports a constant permutation. */
18022 #define MAX_VECT_LEN 8
18024 struct expand_vec_perm_d
18026 rtx target, op0, op1;
18027 unsigned char perm[MAX_VECT_LEN];
18028 enum machine_mode vmode;
18029 unsigned char nelt;
18034 /* Construct (set target (vec_select op0 (parallel perm))) and
18035 return true if that's a valid instruction in the active ISA. */
18038 mips_expand_vselect (rtx target, rtx op0,
18039 const unsigned char *perm, unsigned nelt)
18041 rtx rperm[MAX_VECT_LEN], x;
18044 for (i = 0; i < nelt; ++i)
18045 rperm[i] = GEN_INT (perm[i]);
18047 x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (nelt, rperm));
18048 x = gen_rtx_VEC_SELECT (GET_MODE (target), op0, x);
18049 x = gen_rtx_SET (VOIDmode, target, x);
18052 if (recog_memoized (x) < 0)
18060 /* Similar, but generate a vec_concat from op0 and op1 as well. */
18063 mips_expand_vselect_vconcat (rtx target, rtx op0, rtx op1,
18064 const unsigned char *perm, unsigned nelt)
18066 enum machine_mode v2mode;
18069 v2mode = GET_MODE_2XWIDER_MODE (GET_MODE (op0));
18070 x = gen_rtx_VEC_CONCAT (v2mode, op0, op1);
18071 return mips_expand_vselect (target, x, perm, nelt);
18074 /* Recognize patterns for even-odd extraction. */
18077 mips_expand_vpc_loongson_even_odd (struct expand_vec_perm_d *d)
18079 unsigned i, odd, nelt = d->nelt;
18080 rtx t0, t1, t2, t3;
18082 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
18084 /* Even-odd for V2SI/V2SFmode is matched by interleave directly. */
18091 for (i = 1; i < nelt; ++i)
18092 if (d->perm[i] != i * 2 + odd)
18098 /* We need 2*log2(N)-1 operations to achieve odd/even with interleave. */
18099 t0 = gen_reg_rtx (d->vmode);
18100 t1 = gen_reg_rtx (d->vmode);
18104 emit_insn (gen_loongson_punpckhhw (t0, d->op0, d->op1));
18105 emit_insn (gen_loongson_punpcklhw (t1, d->op0, d->op1));
18107 emit_insn (gen_loongson_punpckhhw (d->target, t1, t0));
18109 emit_insn (gen_loongson_punpcklhw (d->target, t1, t0));
18113 t2 = gen_reg_rtx (d->vmode);
18114 t3 = gen_reg_rtx (d->vmode);
18115 emit_insn (gen_loongson_punpckhbh (t0, d->op0, d->op1));
18116 emit_insn (gen_loongson_punpcklbh (t1, d->op0, d->op1));
18117 emit_insn (gen_loongson_punpckhbh (t2, t1, t0));
18118 emit_insn (gen_loongson_punpcklbh (t3, t1, t0));
18120 emit_insn (gen_loongson_punpckhbh (d->target, t3, t2));
18122 emit_insn (gen_loongson_punpcklbh (d->target, t3, t2));
18126 gcc_unreachable ();
18131 /* Recognize patterns for the Loongson PSHUFH instruction. */
18134 mips_expand_vpc_loongson_pshufh (struct expand_vec_perm_d *d)
18139 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
18141 if (d->vmode != V4HImode)
18146 /* Convert the selector into the packed 8-bit form for pshufh. */
18147 /* Recall that loongson is little-endian only. No big-endian
18148 adjustment required. */
18149 for (i = mask = 0; i < 4; i++)
18150 mask |= (d->perm[i] & 3) << (i * 2);
18151 rmask = force_reg (SImode, GEN_INT (mask));
18153 if (d->one_vector_p)
18154 emit_insn (gen_loongson_pshufh (d->target, d->op0, rmask));
18157 rtx t0, t1, x, merge, rmerge[4];
18159 t0 = gen_reg_rtx (V4HImode);
18160 t1 = gen_reg_rtx (V4HImode);
18161 emit_insn (gen_loongson_pshufh (t1, d->op1, rmask));
18162 emit_insn (gen_loongson_pshufh (t0, d->op0, rmask));
18164 for (i = 0; i < 4; ++i)
18165 rmerge[i] = (d->perm[i] & 4 ? constm1_rtx : const0_rtx);
18166 merge = gen_rtx_CONST_VECTOR (V4HImode, gen_rtvec_v (4, rmerge));
18167 merge = force_reg (V4HImode, merge);
18169 x = gen_rtx_AND (V4HImode, merge, t1);
18170 emit_insn (gen_rtx_SET (VOIDmode, t1, x));
18172 x = gen_rtx_NOT (V4HImode, merge);
18173 x = gen_rtx_AND (V4HImode, x, t0);
18174 emit_insn (gen_rtx_SET (VOIDmode, t0, x));
18176 x = gen_rtx_IOR (V4HImode, t0, t1);
18177 emit_insn (gen_rtx_SET (VOIDmode, d->target, x));
18183 /* Recognize broadcast patterns for the Loongson. */
18186 mips_expand_vpc_loongson_bcast (struct expand_vec_perm_d *d)
18191 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
18193 /* Note that we've already matched V2SI via punpck and V4HI via pshufh. */
18194 if (d->vmode != V8QImode)
18196 if (!d->one_vector_p)
18200 for (i = 1; i < 8; ++i)
18201 if (d->perm[i] != elt)
18207 /* With one interleave we put two of the desired element adjacent. */
18208 t0 = gen_reg_rtx (V8QImode);
18210 emit_insn (gen_loongson_punpcklbh (t0, d->op0, d->op0));
18212 emit_insn (gen_loongson_punpckhbh (t0, d->op0, d->op0));
18214 /* Shuffle that one HImode element into all locations. */
18217 t1 = gen_reg_rtx (V4HImode);
18218 emit_insn (gen_loongson_pshufh (t1, gen_lowpart (V4HImode, t0),
18219 force_reg (SImode, GEN_INT (elt))));
18221 emit_move_insn (d->target, gen_lowpart (V8QImode, t1));
18226 mips_expand_vec_perm_const_1 (struct expand_vec_perm_d *d)
18228 unsigned int i, nelt = d->nelt;
18229 unsigned char perm2[MAX_VECT_LEN];
18231 if (d->one_vector_p)
18233 /* Try interleave with alternating operands. */
18234 memcpy (perm2, d->perm, sizeof(perm2));
18235 for (i = 1; i < nelt; i += 2)
18237 if (mips_expand_vselect_vconcat (d->target, d->op0, d->op1, perm2, nelt))
18242 if (mips_expand_vselect_vconcat (d->target, d->op0, d->op1,
18246 /* Try again with swapped operands. */
18247 for (i = 0; i < nelt; ++i)
18248 perm2[i] = (d->perm[i] + nelt) & (2 * nelt - 1);
18249 if (mips_expand_vselect_vconcat (d->target, d->op1, d->op0, perm2, nelt))
18253 if (mips_expand_vpc_loongson_even_odd (d))
18255 if (mips_expand_vpc_loongson_pshufh (d))
18257 if (mips_expand_vpc_loongson_bcast (d))
18262 /* Expand a vec_perm_const pattern. */
18265 mips_expand_vec_perm_const (rtx operands[4])
18267 struct expand_vec_perm_d d;
18268 int i, nelt, which;
18269 unsigned char orig_perm[MAX_VECT_LEN];
18273 d.target = operands[0];
18274 d.op0 = operands[1];
18275 d.op1 = operands[2];
18278 d.vmode = GET_MODE (d.target);
18279 gcc_assert (VECTOR_MODE_P (d.vmode));
18280 d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
18281 d.testing_p = false;
18283 for (i = which = 0; i < nelt; ++i)
18285 rtx e = XVECEXP (sel, 0, i);
18286 int ei = INTVAL (e) & (2 * nelt - 1);
18287 which |= (ei < nelt ? 1 : 2);
18290 memcpy (d.perm, orig_perm, MAX_VECT_LEN);
18298 d.one_vector_p = false;
18299 if (!rtx_equal_p (d.op0, d.op1))
18304 for (i = 0; i < nelt; ++i)
18305 d.perm[i] &= nelt - 1;
18307 d.one_vector_p = true;
18312 d.one_vector_p = true;
18316 ok = mips_expand_vec_perm_const_1 (&d);
18318 /* If we were given a two-vector permutation which just happened to
18319 have both input vectors equal, we folded this into a one-vector
18320 permutation. There are several loongson patterns that are matched
18321 via direct vec_select+vec_concat expansion, but we do not have
18322 support in mips_expand_vec_perm_const_1 to guess the adjustment
18323 that should be made for a single operand. Just try again with
18324 the original permutation. */
18325 if (!ok && which == 3)
18327 d.op0 = operands[1];
18328 d.op1 = operands[2];
18329 d.one_vector_p = false;
18330 memcpy (d.perm, orig_perm, MAX_VECT_LEN);
18331 ok = mips_expand_vec_perm_const_1 (&d);
18337 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST_OK. */
18340 mips_vectorize_vec_perm_const_ok (enum machine_mode vmode,
18341 const unsigned char *sel)
18343 struct expand_vec_perm_d d;
18344 unsigned int i, nelt, which;
18348 d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
18349 d.testing_p = true;
18350 memcpy (d.perm, sel, nelt);
18352 /* Categorize the set of elements in the selector. */
18353 for (i = which = 0; i < nelt; ++i)
18355 unsigned char e = d.perm[i];
18356 gcc_assert (e < 2 * nelt);
18357 which |= (e < nelt ? 1 : 2);
18360 /* For all elements from second vector, fold the elements to first. */
18362 for (i = 0; i < nelt; ++i)
18365 /* Check whether the mask can be applied to the vector type. */
18366 d.one_vector_p = (which != 3);
18368 d.target = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 1);
18369 d.op1 = d.op0 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 2);
18370 if (!d.one_vector_p)
18371 d.op1 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 3);
18374 ret = mips_expand_vec_perm_const_1 (&d);
18380 /* Expand an integral vector unpack operation. */
18383 mips_expand_vec_unpack (rtx operands[2], bool unsigned_p, bool high_p)
18385 enum machine_mode imode = GET_MODE (operands[1]);
18386 rtx (*unpack) (rtx, rtx, rtx);
18387 rtx (*cmpgt) (rtx, rtx, rtx);
18388 rtx tmp, dest, zero;
18394 unpack = gen_loongson_punpckhbh;
18396 unpack = gen_loongson_punpcklbh;
18397 cmpgt = gen_loongson_pcmpgtb;
18401 unpack = gen_loongson_punpckhhw;
18403 unpack = gen_loongson_punpcklhw;
18404 cmpgt = gen_loongson_pcmpgth;
18407 gcc_unreachable ();
18410 zero = force_reg (imode, CONST0_RTX (imode));
18415 tmp = gen_reg_rtx (imode);
18416 emit_insn (cmpgt (tmp, zero, operands[1]));
18419 dest = gen_reg_rtx (imode);
18420 emit_insn (unpack (dest, operands[1], tmp));
18422 emit_move_insn (operands[0], gen_lowpart (GET_MODE (operands[0]), dest));
18425 /* A subroutine of mips_expand_vec_init, match constant vector elements. */
18428 mips_constant_elt_p (rtx x)
18430 return CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE;
18433 /* A subroutine of mips_expand_vec_init, expand via broadcast. */
18436 mips_expand_vi_broadcast (enum machine_mode vmode, rtx target, rtx elt)
18438 struct expand_vec_perm_d d;
18442 if (elt != const0_rtx)
18443 elt = force_reg (GET_MODE_INNER (vmode), elt);
18445 elt = gen_lowpart (DImode, elt);
18447 t1 = gen_reg_rtx (vmode);
18451 emit_insn (gen_loongson_vec_init1_v8qi (t1, elt));
18454 emit_insn (gen_loongson_vec_init1_v4hi (t1, elt));
18457 gcc_unreachable ();
18460 memset (&d, 0, sizeof (d));
18465 d.nelt = GET_MODE_NUNITS (vmode);
18466 d.one_vector_p = true;
18468 ok = mips_expand_vec_perm_const_1 (&d);
18472 /* A subroutine of mips_expand_vec_init, replacing all of the non-constant
18473 elements of VALS with zeros, copy the constant vector to TARGET. */
18476 mips_expand_vi_constant (enum machine_mode vmode, unsigned nelt,
18477 rtx target, rtx vals)
18479 rtvec vec = shallow_copy_rtvec (XVEC (vals, 0));
18482 for (i = 0; i < nelt; ++i)
18484 if (!mips_constant_elt_p (RTVEC_ELT (vec, i)))
18485 RTVEC_ELT (vec, i) = const0_rtx;
18488 emit_move_insn (target, gen_rtx_CONST_VECTOR (vmode, vec));
18492 /* A subroutine of mips_expand_vec_init, expand via pinsrh. */
18495 mips_expand_vi_loongson_one_pinsrh (rtx target, rtx vals, unsigned one_var)
18497 mips_expand_vi_constant (V4HImode, 4, target, vals);
18499 emit_insn (gen_vec_setv4hi (target, target, XVECEXP (vals, 0, one_var),
18500 GEN_INT (one_var)));
18503 /* A subroutine of mips_expand_vec_init, expand anything via memory. */
18506 mips_expand_vi_general (enum machine_mode vmode, enum machine_mode imode,
18507 unsigned nelt, unsigned nvar, rtx target, rtx vals)
18509 rtx mem = assign_stack_temp (vmode, GET_MODE_SIZE (vmode));
18510 unsigned int i, isize = GET_MODE_SIZE (imode);
18513 mips_expand_vi_constant (vmode, nelt, mem, vals);
18515 for (i = 0; i < nelt; ++i)
18517 rtx x = XVECEXP (vals, 0, i);
18518 if (!mips_constant_elt_p (x))
18519 emit_move_insn (adjust_address (mem, imode, i * isize), x);
18522 emit_move_insn (target, mem);
18525 /* Expand a vector initialization. */
18528 mips_expand_vector_init (rtx target, rtx vals)
18530 enum machine_mode vmode = GET_MODE (target);
18531 enum machine_mode imode = GET_MODE_INNER (vmode);
18532 unsigned i, nelt = GET_MODE_NUNITS (vmode);
18533 unsigned nvar = 0, one_var = -1u;
18534 bool all_same = true;
18537 for (i = 0; i < nelt; ++i)
18539 x = XVECEXP (vals, 0, i);
18540 if (!mips_constant_elt_p (x))
18541 nvar++, one_var = i;
18542 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
18546 /* Load constants from the pool, or whatever's handy. */
18549 emit_move_insn (target, gen_rtx_CONST_VECTOR (vmode, XVEC (vals, 0)));
18553 /* For two-part initialization, always use CONCAT. */
18556 rtx op0 = force_reg (imode, XVECEXP (vals, 0, 0));
18557 rtx op1 = force_reg (imode, XVECEXP (vals, 0, 1));
18558 x = gen_rtx_VEC_CONCAT (vmode, op0, op1);
18559 emit_insn (gen_rtx_SET (VOIDmode, target, x));
18563 /* Loongson is the only cpu with vectors with more elements. */
18564 gcc_assert (TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS);
18566 /* If all values are identical, broadcast the value. */
18569 mips_expand_vi_broadcast (vmode, target, XVECEXP (vals, 0, 0));
18573 /* If we've only got one non-variable V4HImode, use PINSRH. */
18574 if (nvar == 1 && vmode == V4HImode)
18576 mips_expand_vi_loongson_one_pinsrh (target, vals, one_var);
18580 mips_expand_vi_general (vmode, imode, nelt, nvar, target, vals);
18583 /* Expand a vector reduction. */
18586 mips_expand_vec_reduc (rtx target, rtx in, rtx (*gen)(rtx, rtx, rtx))
18588 enum machine_mode vmode = GET_MODE (in);
18589 unsigned char perm2[2];
18590 rtx last, next, fold, x;
18594 fold = gen_reg_rtx (vmode);
18598 /* Use PUL/PLU to produce { L, H } op { H, L }.
18599 By reversing the pair order, rather than a pure interleave high,
18600 we avoid erroneous exceptional conditions that we might otherwise
18601 produce from the computation of H op H. */
18604 ok = mips_expand_vselect_vconcat (fold, last, last, perm2, 2);
18609 /* Use interleave to produce { H, L } op { H, H }. */
18610 emit_insn (gen_loongson_punpckhwd (fold, last, last));
18614 /* Perform the first reduction with interleave,
18615 and subsequent reductions with shifts. */
18616 emit_insn (gen_loongson_punpckhwd_hi (fold, last, last));
18618 next = gen_reg_rtx (vmode);
18619 emit_insn (gen (next, last, fold));
18622 fold = gen_reg_rtx (vmode);
18623 x = force_reg (SImode, GEN_INT (16));
18624 emit_insn (gen_vec_shr_v4hi (fold, last, x));
18628 emit_insn (gen_loongson_punpckhwd_qi (fold, last, last));
18630 next = gen_reg_rtx (vmode);
18631 emit_insn (gen (next, last, fold));
18634 fold = gen_reg_rtx (vmode);
18635 x = force_reg (SImode, GEN_INT (16));
18636 emit_insn (gen_vec_shr_v8qi (fold, last, x));
18638 next = gen_reg_rtx (vmode);
18639 emit_insn (gen (next, last, fold));
18642 fold = gen_reg_rtx (vmode);
18643 x = force_reg (SImode, GEN_INT (8));
18644 emit_insn (gen_vec_shr_v8qi (fold, last, x));
18648 gcc_unreachable ();
18651 emit_insn (gen (target, last, fold));
18654 /* Expand a vector minimum/maximum. */
18657 mips_expand_vec_minmax (rtx target, rtx op0, rtx op1,
18658 rtx (*cmp) (rtx, rtx, rtx), bool min_p)
18660 enum machine_mode vmode = GET_MODE (target);
18663 tc = gen_reg_rtx (vmode);
18664 t0 = gen_reg_rtx (vmode);
18665 t1 = gen_reg_rtx (vmode);
18668 emit_insn (cmp (tc, op0, op1));
18670 x = gen_rtx_AND (vmode, tc, (min_p ? op1 : op0));
18671 emit_insn (gen_rtx_SET (VOIDmode, t0, x));
18673 x = gen_rtx_NOT (vmode, tc);
18674 x = gen_rtx_AND (vmode, x, (min_p ? op0 : op1));
18675 emit_insn (gen_rtx_SET (VOIDmode, t1, x));
18677 x = gen_rtx_IOR (vmode, t0, t1);
18678 emit_insn (gen_rtx_SET (VOIDmode, target, x));
18681 /* Implement TARGET_CASE_VALUES_THRESHOLD. */
18684 mips_case_values_threshold (void)
18686 /* In MIPS16 mode using a larger case threshold generates smaller code. */
18687 if (TARGET_MIPS16 && optimize_size)
18690 return default_case_values_threshold ();
18693 /* Initialize the GCC target structure. */
18694 #undef TARGET_ASM_ALIGNED_HI_OP
18695 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
18696 #undef TARGET_ASM_ALIGNED_SI_OP
18697 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
18698 #undef TARGET_ASM_ALIGNED_DI_OP
18699 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
18701 #undef TARGET_OPTION_OVERRIDE
18702 #define TARGET_OPTION_OVERRIDE mips_option_override
18704 #undef TARGET_LEGITIMIZE_ADDRESS
18705 #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
18707 #undef TARGET_ASM_FUNCTION_PROLOGUE
18708 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
18709 #undef TARGET_ASM_FUNCTION_EPILOGUE
18710 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
18711 #undef TARGET_ASM_SELECT_RTX_SECTION
18712 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
18713 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
18714 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
18716 #undef TARGET_SCHED_INIT
18717 #define TARGET_SCHED_INIT mips_sched_init
18718 #undef TARGET_SCHED_REORDER
18719 #define TARGET_SCHED_REORDER mips_sched_reorder
18720 #undef TARGET_SCHED_REORDER2
18721 #define TARGET_SCHED_REORDER2 mips_sched_reorder2
18722 #undef TARGET_SCHED_VARIABLE_ISSUE
18723 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
18724 #undef TARGET_SCHED_ADJUST_COST
18725 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
18726 #undef TARGET_SCHED_ISSUE_RATE
18727 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
18728 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
18729 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
18730 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
18731 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
18732 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
18733 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
18734 mips_multipass_dfa_lookahead
18735 #undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
18736 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
18737 mips_small_register_classes_for_mode_p
18739 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
18740 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
18742 #undef TARGET_INSERT_ATTRIBUTES
18743 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
18744 #undef TARGET_MERGE_DECL_ATTRIBUTES
18745 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
18746 #undef TARGET_CAN_INLINE_P
18747 #define TARGET_CAN_INLINE_P mips_can_inline_p
18748 #undef TARGET_SET_CURRENT_FUNCTION
18749 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
18751 #undef TARGET_VALID_POINTER_MODE
18752 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
18753 #undef TARGET_REGISTER_MOVE_COST
18754 #define TARGET_REGISTER_MOVE_COST mips_register_move_cost
18755 #undef TARGET_MEMORY_MOVE_COST
18756 #define TARGET_MEMORY_MOVE_COST mips_memory_move_cost
18757 #undef TARGET_RTX_COSTS
18758 #define TARGET_RTX_COSTS mips_rtx_costs
18759 #undef TARGET_ADDRESS_COST
18760 #define TARGET_ADDRESS_COST mips_address_cost
18762 #undef TARGET_IN_SMALL_DATA_P
18763 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
18765 #undef TARGET_MACHINE_DEPENDENT_REORG
18766 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
18768 #undef TARGET_PREFERRED_RELOAD_CLASS
18769 #define TARGET_PREFERRED_RELOAD_CLASS mips_preferred_reload_class
18771 #undef TARGET_EXPAND_TO_RTL_HOOK
18772 #define TARGET_EXPAND_TO_RTL_HOOK mips_expand_to_rtl_hook
18773 #undef TARGET_ASM_FILE_START
18774 #define TARGET_ASM_FILE_START mips_file_start
18775 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
18776 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
18777 #undef TARGET_ASM_CODE_END
18778 #define TARGET_ASM_CODE_END mips_code_end
18780 #undef TARGET_INIT_LIBFUNCS
18781 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
18783 #undef TARGET_BUILD_BUILTIN_VA_LIST
18784 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
18785 #undef TARGET_EXPAND_BUILTIN_VA_START
18786 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
18787 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
18788 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
18790 #undef TARGET_PROMOTE_FUNCTION_MODE
18791 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
18792 #undef TARGET_PROMOTE_PROTOTYPES
18793 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
18795 #undef TARGET_FUNCTION_VALUE
18796 #define TARGET_FUNCTION_VALUE mips_function_value
18797 #undef TARGET_LIBCALL_VALUE
18798 #define TARGET_LIBCALL_VALUE mips_libcall_value
18799 #undef TARGET_FUNCTION_VALUE_REGNO_P
18800 #define TARGET_FUNCTION_VALUE_REGNO_P mips_function_value_regno_p
18801 #undef TARGET_RETURN_IN_MEMORY
18802 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
18803 #undef TARGET_RETURN_IN_MSB
18804 #define TARGET_RETURN_IN_MSB mips_return_in_msb
18806 #undef TARGET_ASM_OUTPUT_MI_THUNK
18807 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
18808 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
18809 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
18811 #undef TARGET_PRINT_OPERAND
18812 #define TARGET_PRINT_OPERAND mips_print_operand
18813 #undef TARGET_PRINT_OPERAND_ADDRESS
18814 #define TARGET_PRINT_OPERAND_ADDRESS mips_print_operand_address
18815 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
18816 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mips_print_operand_punct_valid_p
18818 #undef TARGET_SETUP_INCOMING_VARARGS
18819 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
18820 #undef TARGET_STRICT_ARGUMENT_NAMING
18821 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
18822 #undef TARGET_MUST_PASS_IN_STACK
18823 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
18824 #undef TARGET_PASS_BY_REFERENCE
18825 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
18826 #undef TARGET_CALLEE_COPIES
18827 #define TARGET_CALLEE_COPIES mips_callee_copies
18828 #undef TARGET_ARG_PARTIAL_BYTES
18829 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
18830 #undef TARGET_FUNCTION_ARG
18831 #define TARGET_FUNCTION_ARG mips_function_arg
18832 #undef TARGET_FUNCTION_ARG_ADVANCE
18833 #define TARGET_FUNCTION_ARG_ADVANCE mips_function_arg_advance
18834 #undef TARGET_FUNCTION_ARG_BOUNDARY
18835 #define TARGET_FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
18837 #undef TARGET_MODE_REP_EXTENDED
18838 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
18840 #undef TARGET_VECTOR_MODE_SUPPORTED_P
18841 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
18843 #undef TARGET_SCALAR_MODE_SUPPORTED_P
18844 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
18846 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
18847 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE mips_preferred_simd_mode
18849 #undef TARGET_INIT_BUILTINS
18850 #define TARGET_INIT_BUILTINS mips_init_builtins
18851 #undef TARGET_BUILTIN_DECL
18852 #define TARGET_BUILTIN_DECL mips_builtin_decl
18853 #undef TARGET_EXPAND_BUILTIN
18854 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
18856 #undef TARGET_HAVE_TLS
18857 #define TARGET_HAVE_TLS HAVE_AS_TLS
18859 #undef TARGET_CANNOT_FORCE_CONST_MEM
18860 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
18862 #undef TARGET_LEGITIMATE_CONSTANT_P
18863 #define TARGET_LEGITIMATE_CONSTANT_P mips_legitimate_constant_p
18865 #undef TARGET_ENCODE_SECTION_INFO
18866 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
18868 #undef TARGET_ATTRIBUTE_TABLE
18869 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
18870 /* All our function attributes are related to how out-of-line copies should
18871 be compiled or called. They don't in themselves prevent inlining. */
18872 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
18873 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
18875 #undef TARGET_EXTRA_LIVE_ON_ENTRY
18876 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
18878 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
18879 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
18880 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
18881 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
18883 #undef TARGET_COMP_TYPE_ATTRIBUTES
18884 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
18886 #ifdef HAVE_AS_DTPRELWORD
18887 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
18888 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
18890 #undef TARGET_DWARF_REGISTER_SPAN
18891 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
18893 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
18894 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
18896 #undef TARGET_LEGITIMATE_ADDRESS_P
18897 #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p
18899 #undef TARGET_FRAME_POINTER_REQUIRED
18900 #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required
18902 #undef TARGET_CAN_ELIMINATE
18903 #define TARGET_CAN_ELIMINATE mips_can_eliminate
18905 #undef TARGET_CONDITIONAL_REGISTER_USAGE
18906 #define TARGET_CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage
18908 #undef TARGET_TRAMPOLINE_INIT
18909 #define TARGET_TRAMPOLINE_INIT mips_trampoline_init
18911 #undef TARGET_ASM_OUTPUT_SOURCE_FILENAME
18912 #define TARGET_ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
18914 #undef TARGET_SHIFT_TRUNCATION_MASK
18915 #define TARGET_SHIFT_TRUNCATION_MASK mips_shift_truncation_mask
18917 #undef TARGET_PREPARE_PCH_SAVE
18918 #define TARGET_PREPARE_PCH_SAVE mips_prepare_pch_save
18920 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
18921 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK mips_vectorize_vec_perm_const_ok
18923 #undef TARGET_CASE_VALUES_THRESHOLD
18924 #define TARGET_CASE_VALUES_THRESHOLD mips_case_values_threshold
18926 struct gcc_target targetm = TARGET_INITIALIZER;
18928 #include "gt-mips.h"