1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
5 Free Software Foundation, Inc.
6 Contributed by A. Lichnewsky, lich@inria.inria.fr.
7 Changes by Michael Meissner, meissner@osf.org.
8 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
9 Brendan Eich, brendan@microunity.com.
11 This file is part of GCC.
13 GCC is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GCC is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GCC; see the file COPYING3. If not see
25 <http://www.gnu.org/licenses/>. */
29 #include "coretypes.h"
33 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
36 #include "insn-attr.h"
52 #include "target-def.h"
53 #include "integrate.h"
54 #include "langhooks.h"
55 #include "cfglayout.h"
56 #include "sched-int.h"
59 #include "diagnostic.h"
60 #include "target-globals.h"
63 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
64 #define UNSPEC_ADDRESS_P(X) \
65 (GET_CODE (X) == UNSPEC \
66 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
67 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
69 /* Extract the symbol or label from UNSPEC wrapper X. */
70 #define UNSPEC_ADDRESS(X) \
73 /* Extract the symbol type from UNSPEC wrapper X. */
74 #define UNSPEC_ADDRESS_TYPE(X) \
75 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
77 /* The maximum distance between the top of the stack frame and the
78 value $sp has when we save and restore registers.
80 The value for normal-mode code must be a SMALL_OPERAND and must
81 preserve the maximum stack alignment. We therefore use a value
82 of 0x7ff0 in this case.
84 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
85 up to 0x7f8 bytes and can usually save or restore all the registers
86 that we need to save or restore. (Note that we can only use these
87 instructions for o32, for which the stack alignment is 8 bytes.)
89 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
90 RESTORE are not available. We can then use unextended instructions
91 to save and restore registers, and to allocate and deallocate the top
93 #define MIPS_MAX_FIRST_STACK_STEP \
94 (!TARGET_MIPS16 ? 0x7ff0 \
95 : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
96 : TARGET_64BIT ? 0x100 : 0x400)
98 /* True if INSN is a mips.md pattern or asm statement. */
99 #define USEFUL_INSN_P(INSN) \
100 (NONDEBUG_INSN_P (INSN) \
101 && GET_CODE (PATTERN (INSN)) != USE \
102 && GET_CODE (PATTERN (INSN)) != CLOBBER \
103 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
104 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
106 /* If INSN is a delayed branch sequence, return the first instruction
107 in the sequence, otherwise return INSN itself. */
108 #define SEQ_BEGIN(INSN) \
109 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
110 ? XVECEXP (PATTERN (INSN), 0, 0) \
113 /* Likewise for the last instruction in a delayed branch sequence. */
114 #define SEQ_END(INSN) \
115 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
116 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
119 /* Execute the following loop body with SUBINSN set to each instruction
120 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
121 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
122 for ((SUBINSN) = SEQ_BEGIN (INSN); \
123 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
124 (SUBINSN) = NEXT_INSN (SUBINSN))
126 /* True if bit BIT is set in VALUE. */
127 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
129 /* Return the opcode for a ptr_mode load of the form:
131 l[wd] DEST, OFFSET(BASE). */
132 #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \
133 (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \
138 /* Return the opcode to move register SRC into register DEST. */
139 #define MIPS_MOVE(DEST, SRC) \
140 ((TARGET_64BIT ? 0x2d : 0x21) \
144 /* Return the opcode for:
147 #define MIPS_LUI(DEST, VALUE) \
148 ((0xf << 26) | ((DEST) << 16) | (VALUE))
150 /* Return the opcode to jump to register DEST. */
151 #define MIPS_JR(DEST) \
152 (((DEST) << 21) | 0x8)
154 /* Return the opcode for:
156 bal . + (1 + OFFSET) * 4. */
157 #define MIPS_BAL(OFFSET) \
158 ((0x1 << 26) | (0x11 << 16) | (OFFSET))
160 /* Return the usual opcode for a nop. */
163 /* Classifies an address.
166 A natural register + offset address. The register satisfies
167 mips_valid_base_register_p and the offset is a const_arith_operand.
170 A LO_SUM rtx. The first operand is a valid base register and
171 the second operand is a symbolic address.
174 A signed 16-bit constant address.
177 A constant symbolic address. */
178 enum mips_address_type {
185 /* Macros to create an enumeration identifier for a function prototype. */
186 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
187 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
188 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
189 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
191 /* Classifies the prototype of a built-in function. */
192 enum mips_function_type {
193 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
194 #include "config/mips/mips-ftypes.def"
195 #undef DEF_MIPS_FTYPE
199 /* Specifies how a built-in function should be converted into rtl. */
200 enum mips_builtin_type {
201 /* The function corresponds directly to an .md pattern. The return
202 value is mapped to operand 0 and the arguments are mapped to
203 operands 1 and above. */
206 /* The function corresponds directly to an .md pattern. There is no return
207 value and the arguments are mapped to operands 0 and above. */
208 MIPS_BUILTIN_DIRECT_NO_TARGET,
210 /* The function corresponds to a comparison instruction followed by
211 a mips_cond_move_tf_ps pattern. The first two arguments are the
212 values to compare and the second two arguments are the vector
213 operands for the movt.ps or movf.ps instruction (in assembly order). */
217 /* The function corresponds to a V2SF comparison instruction. Operand 0
218 of this instruction is the result of the comparison, which has mode
219 CCV2 or CCV4. The function arguments are mapped to operands 1 and
220 above. The function's return value is an SImode boolean that is
221 true under the following conditions:
223 MIPS_BUILTIN_CMP_ANY: one of the registers is true
224 MIPS_BUILTIN_CMP_ALL: all of the registers are true
225 MIPS_BUILTIN_CMP_LOWER: the first register is true
226 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
227 MIPS_BUILTIN_CMP_ANY,
228 MIPS_BUILTIN_CMP_ALL,
229 MIPS_BUILTIN_CMP_UPPER,
230 MIPS_BUILTIN_CMP_LOWER,
232 /* As above, but the instruction only sets a single $fcc register. */
233 MIPS_BUILTIN_CMP_SINGLE,
235 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
236 MIPS_BUILTIN_BPOSGE32
239 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
240 #define MIPS_FP_CONDITIONS(MACRO) \
258 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
259 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
260 enum mips_fp_condition {
261 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
264 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
265 #define STRINGIFY(X) #X
266 static const char *const mips_fp_conditions[] = {
267 MIPS_FP_CONDITIONS (STRINGIFY)
270 /* Information about a function's frame layout. */
271 struct GTY(()) mips_frame_info {
272 /* The size of the frame in bytes. */
273 HOST_WIDE_INT total_size;
275 /* The number of bytes allocated to variables. */
276 HOST_WIDE_INT var_size;
278 /* The number of bytes allocated to outgoing function arguments. */
279 HOST_WIDE_INT args_size;
281 /* The number of bytes allocated to the .cprestore slot, or 0 if there
283 HOST_WIDE_INT cprestore_size;
285 /* Bit X is set if the function saves or restores GPR X. */
288 /* Likewise FPR X. */
291 /* Likewise doubleword accumulator X ($acX). */
292 unsigned int acc_mask;
294 /* The number of GPRs, FPRs, doubleword accumulators and COP0
298 unsigned int num_acc;
299 unsigned int num_cop0_regs;
301 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
302 save slots from the top of the frame, or zero if no such slots are
304 HOST_WIDE_INT gp_save_offset;
305 HOST_WIDE_INT fp_save_offset;
306 HOST_WIDE_INT acc_save_offset;
307 HOST_WIDE_INT cop0_save_offset;
309 /* Likewise, but giving offsets from the bottom of the frame. */
310 HOST_WIDE_INT gp_sp_offset;
311 HOST_WIDE_INT fp_sp_offset;
312 HOST_WIDE_INT acc_sp_offset;
313 HOST_WIDE_INT cop0_sp_offset;
315 /* Similar, but the value passed to _mcount. */
316 HOST_WIDE_INT ra_fp_offset;
318 /* The offset of arg_pointer_rtx from the bottom of the frame. */
319 HOST_WIDE_INT arg_pointer_offset;
321 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
322 HOST_WIDE_INT hard_frame_pointer_offset;
325 struct GTY(()) machine_function {
326 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
327 rtx mips16_gp_pseudo_rtx;
329 /* The number of extra stack bytes taken up by register varargs.
330 This area is allocated by the callee at the very top of the frame. */
333 /* The current frame information, calculated by mips_compute_frame_info. */
334 struct mips_frame_info frame;
336 /* The register to use as the function's global pointer, or INVALID_REGNUM
337 if the function doesn't need one. */
338 unsigned int global_pointer;
340 /* How many instructions it takes to load a label into $AT, or 0 if
341 this property hasn't yet been calculated. */
342 unsigned int load_label_num_insns;
344 /* True if mips_adjust_insn_length should ignore an instruction's
346 bool ignore_hazard_length_p;
348 /* True if the whole function is suitable for .set noreorder and
350 bool all_noreorder_p;
352 /* True if the function has "inflexible" and "flexible" references
353 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
354 and mips_cfun_has_flexible_gp_ref_p for details. */
355 bool has_inflexible_gp_insn_p;
356 bool has_flexible_gp_insn_p;
358 /* True if the function's prologue must load the global pointer
359 value into pic_offset_table_rtx and store the same value in
360 the function's cprestore slot (if any). Even if this value
361 is currently false, we may decide to set it to true later;
362 see mips_must_initialize_gp_p () for details. */
363 bool must_initialize_gp_p;
365 /* True if the current function must restore $gp after any potential
366 clobber. This value is only meaningful during the first post-epilogue
367 split_insns pass; see mips_must_initialize_gp_p () for details. */
368 bool must_restore_gp_when_clobbered_p;
370 /* True if this is an interrupt handler. */
371 bool interrupt_handler_p;
373 /* True if this is an interrupt handler that uses shadow registers. */
374 bool use_shadow_register_set_p;
376 /* True if this is an interrupt handler that should keep interrupts
378 bool keep_interrupts_masked_p;
380 /* True if this is an interrupt handler that should use DERET
382 bool use_debug_exception_return_p;
385 /* Information about a single argument. */
386 struct mips_arg_info {
387 /* True if the argument is passed in a floating-point register, or
388 would have been if we hadn't run out of registers. */
391 /* The number of words passed in registers, rounded up. */
392 unsigned int reg_words;
394 /* For EABI, the offset of the first register from GP_ARG_FIRST or
395 FP_ARG_FIRST. For other ABIs, the offset of the first register from
396 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
397 comment for details).
399 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
401 unsigned int reg_offset;
403 /* The number of words that must be passed on the stack, rounded up. */
404 unsigned int stack_words;
406 /* The offset from the start of the stack overflow area of the argument's
407 first stack word. Only meaningful when STACK_WORDS is nonzero. */
408 unsigned int stack_offset;
411 /* Information about an address described by mips_address_type.
417 REG is the base register and OFFSET is the constant offset.
420 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
421 is the type of symbol it references.
424 SYMBOL_TYPE is the type of symbol that the address references. */
425 struct mips_address_info {
426 enum mips_address_type type;
429 enum mips_symbol_type symbol_type;
432 /* One stage in a constant building sequence. These sequences have
436 A = A CODE[1] VALUE[1]
437 A = A CODE[2] VALUE[2]
440 where A is an accumulator, each CODE[i] is a binary rtl operation
441 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
442 struct mips_integer_op {
444 unsigned HOST_WIDE_INT value;
447 /* The largest number of operations needed to load an integer constant.
448 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
449 When the lowest bit is clear, we can try, but reject a sequence with
450 an extra SLL at the end. */
451 #define MIPS_MAX_INTEGER_OPS 7
453 /* Information about a MIPS16e SAVE or RESTORE instruction. */
454 struct mips16e_save_restore_info {
455 /* The number of argument registers saved by a SAVE instruction.
456 0 for RESTORE instructions. */
459 /* Bit X is set if the instruction saves or restores GPR X. */
462 /* The total number of bytes to allocate. */
466 /* Costs of various operations on the different architectures. */
468 struct mips_rtx_cost_data
470 unsigned short fp_add;
471 unsigned short fp_mult_sf;
472 unsigned short fp_mult_df;
473 unsigned short fp_div_sf;
474 unsigned short fp_div_df;
475 unsigned short int_mult_si;
476 unsigned short int_mult_di;
477 unsigned short int_div_si;
478 unsigned short int_div_di;
479 unsigned short branch_cost;
480 unsigned short memory_latency;
483 /* Global variables for machine-dependent things. */
485 /* The -G setting, or the configuration's default small-data limit if
486 no -G option is given. */
487 static unsigned int mips_small_data_threshold;
489 /* The number of file directives written by mips_output_filename. */
490 int num_source_filenames;
492 /* The name that appeared in the last .file directive written by
493 mips_output_filename, or "" if mips_output_filename hasn't
494 written anything yet. */
495 const char *current_function_file = "";
497 /* Arrays that map GCC register numbers to debugger register numbers. */
498 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
499 int mips_dwarf_regno[FIRST_PSEUDO_REGISTER];
501 /* Information about the current function's epilogue, used only while
504 /* A list of queued REG_CFA_RESTORE notes. */
507 /* The CFA is currently defined as CFA_REG + CFA_OFFSET. */
509 HOST_WIDE_INT cfa_offset;
511 /* The offset of the CFA from the stack pointer while restoring
513 HOST_WIDE_INT cfa_restore_sp_offset;
516 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
517 struct mips_asm_switch mips_noreorder = { "reorder", 0 };
518 struct mips_asm_switch mips_nomacro = { "macro", 0 };
519 struct mips_asm_switch mips_noat = { "at", 0 };
521 /* True if we're writing out a branch-likely instruction rather than a
523 static bool mips_branch_likely;
525 /* The current instruction-set architecture. */
526 enum processor mips_arch;
527 const struct mips_cpu_info *mips_arch_info;
529 /* The processor that we should tune the code for. */
530 enum processor mips_tune;
531 const struct mips_cpu_info *mips_tune_info;
533 /* The ISA level associated with mips_arch. */
536 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
537 static const struct mips_cpu_info *mips_isa_option_info;
539 /* Which cost information to use. */
540 static const struct mips_rtx_cost_data *mips_cost;
542 /* The ambient target flags, excluding MASK_MIPS16. */
543 static int mips_base_target_flags;
545 /* True if MIPS16 is the default mode. */
546 bool mips_base_mips16;
548 /* The ambient values of other global variables. */
549 static int mips_base_schedule_insns; /* flag_schedule_insns */
550 static int mips_base_reorder_blocks_and_partition; /* flag_reorder... */
551 static int mips_base_move_loop_invariants; /* flag_move_loop_invariants */
552 static int mips_base_align_loops; /* align_loops */
553 static int mips_base_align_jumps; /* align_jumps */
554 static int mips_base_align_functions; /* align_functions */
556 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
557 bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
559 /* Index C is true if character C is a valid PRINT_OPERAND punctation
561 static bool mips_print_operand_punct[256];
563 static GTY (()) int mips_output_filename_first_time = 1;
565 /* mips_split_p[X] is true if symbols of type X can be split by
566 mips_split_symbol. */
567 bool mips_split_p[NUM_SYMBOL_TYPES];
569 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
570 can be split by mips_split_symbol. */
571 bool mips_split_hi_p[NUM_SYMBOL_TYPES];
573 /* mips_use_pcrel_pool_p[X] is true if symbols of type X should be
574 forced into a PC-relative constant pool. */
575 bool mips_use_pcrel_pool_p[NUM_SYMBOL_TYPES];
577 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
578 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
579 if they are matched by a special .md file pattern. */
580 const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
582 /* Likewise for HIGHs. */
583 const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
585 /* Target state for MIPS16. */
586 struct target_globals *mips16_globals;
588 /* Cached value of can_issue_more. This is cached in mips_variable_issue hook
589 and returned from mips_sched_reorder2. */
590 static int cached_can_issue_more;
592 /* True if the output uses __mips16_rdhwr. */
593 static bool mips_need_mips16_rdhwr_p;
595 /* Index R is the smallest register class that contains register R. */
596 const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = {
597 LEA_REGS, LEA_REGS, M16_REGS, V1_REG,
598 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
599 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
600 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
601 M16_REGS, M16_REGS, LEA_REGS, LEA_REGS,
602 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
603 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
604 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
605 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
606 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
607 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
608 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
609 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
610 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
611 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
612 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
613 MD0_REG, MD1_REG, NO_REGS, ST_REGS,
614 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
615 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
616 NO_REGS, FRAME_REGS, FRAME_REGS, NO_REGS,
617 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
618 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
619 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
620 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
621 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
622 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
623 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
624 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
625 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
626 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
627 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
628 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
629 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
630 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
631 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
632 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
633 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
634 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
635 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
636 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
637 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
638 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
639 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
640 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
641 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
642 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
643 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
646 /* The value of TARGET_ATTRIBUTE_TABLE. */
647 static const struct attribute_spec mips_attribute_table[] = {
648 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
650 { "long_call", 0, 0, false, true, true, NULL, false },
651 { "far", 0, 0, false, true, true, NULL, false },
652 { "near", 0, 0, false, true, true, NULL, false },
653 /* We would really like to treat "mips16" and "nomips16" as type
654 attributes, but GCC doesn't provide the hooks we need to support
655 the right conversion rules. As declaration attributes, they affect
656 code generation but don't carry other semantics. */
657 { "mips16", 0, 0, true, false, false, NULL, false },
658 { "nomips16", 0, 0, true, false, false, NULL, false },
659 /* Allow functions to be specified as interrupt handlers */
660 { "interrupt", 0, 0, false, true, true, NULL, false },
661 { "use_shadow_register_set", 0, 0, false, true, true, NULL, false },
662 { "keep_interrupts_masked", 0, 0, false, true, true, NULL, false },
663 { "use_debug_exception_return", 0, 0, false, true, true, NULL, false },
664 { NULL, 0, 0, false, false, false, NULL, false }
667 /* A table describing all the processors GCC knows about; see
668 mips-cpus.def for details. */
669 static const struct mips_cpu_info mips_cpu_info_table[] = {
670 #define MIPS_CPU(NAME, CPU, ISA, FLAGS) \
671 { NAME, CPU, ISA, FLAGS },
672 #include "mips-cpus.def"
676 /* Default costs. If these are used for a processor we should look
677 up the actual costs. */
678 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
679 COSTS_N_INSNS (7), /* fp_mult_sf */ \
680 COSTS_N_INSNS (8), /* fp_mult_df */ \
681 COSTS_N_INSNS (23), /* fp_div_sf */ \
682 COSTS_N_INSNS (36), /* fp_div_df */ \
683 COSTS_N_INSNS (10), /* int_mult_si */ \
684 COSTS_N_INSNS (10), /* int_mult_di */ \
685 COSTS_N_INSNS (69), /* int_div_si */ \
686 COSTS_N_INSNS (69), /* int_div_di */ \
687 2, /* branch_cost */ \
688 4 /* memory_latency */
690 /* Floating-point costs for processors without an FPU. Just assume that
691 all floating-point libcalls are very expensive. */
692 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
693 COSTS_N_INSNS (256), /* fp_mult_sf */ \
694 COSTS_N_INSNS (256), /* fp_mult_df */ \
695 COSTS_N_INSNS (256), /* fp_div_sf */ \
696 COSTS_N_INSNS (256) /* fp_div_df */
698 /* Costs to use when optimizing for size. */
699 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size = {
700 COSTS_N_INSNS (1), /* fp_add */
701 COSTS_N_INSNS (1), /* fp_mult_sf */
702 COSTS_N_INSNS (1), /* fp_mult_df */
703 COSTS_N_INSNS (1), /* fp_div_sf */
704 COSTS_N_INSNS (1), /* fp_div_df */
705 COSTS_N_INSNS (1), /* int_mult_si */
706 COSTS_N_INSNS (1), /* int_mult_di */
707 COSTS_N_INSNS (1), /* int_div_si */
708 COSTS_N_INSNS (1), /* int_div_di */
710 4 /* memory_latency */
713 /* Costs to use when optimizing for speed, indexed by processor. */
714 static const struct mips_rtx_cost_data
715 mips_rtx_cost_data[NUM_PROCESSOR_VALUES] = {
717 COSTS_N_INSNS (2), /* fp_add */
718 COSTS_N_INSNS (4), /* fp_mult_sf */
719 COSTS_N_INSNS (5), /* fp_mult_df */
720 COSTS_N_INSNS (12), /* fp_div_sf */
721 COSTS_N_INSNS (19), /* fp_div_df */
722 COSTS_N_INSNS (12), /* int_mult_si */
723 COSTS_N_INSNS (12), /* int_mult_di */
724 COSTS_N_INSNS (35), /* int_div_si */
725 COSTS_N_INSNS (35), /* int_div_di */
727 4 /* memory_latency */
731 COSTS_N_INSNS (6), /* int_mult_si */
732 COSTS_N_INSNS (6), /* int_mult_di */
733 COSTS_N_INSNS (36), /* int_div_si */
734 COSTS_N_INSNS (36), /* int_div_di */
736 4 /* memory_latency */
740 COSTS_N_INSNS (36), /* int_mult_si */
741 COSTS_N_INSNS (36), /* int_mult_di */
742 COSTS_N_INSNS (37), /* int_div_si */
743 COSTS_N_INSNS (37), /* int_div_di */
745 4 /* memory_latency */
749 COSTS_N_INSNS (4), /* int_mult_si */
750 COSTS_N_INSNS (11), /* int_mult_di */
751 COSTS_N_INSNS (36), /* int_div_si */
752 COSTS_N_INSNS (68), /* int_div_di */
754 4 /* memory_latency */
757 COSTS_N_INSNS (4), /* fp_add */
758 COSTS_N_INSNS (4), /* fp_mult_sf */
759 COSTS_N_INSNS (5), /* fp_mult_df */
760 COSTS_N_INSNS (17), /* fp_div_sf */
761 COSTS_N_INSNS (32), /* fp_div_df */
762 COSTS_N_INSNS (4), /* int_mult_si */
763 COSTS_N_INSNS (11), /* int_mult_di */
764 COSTS_N_INSNS (36), /* int_div_si */
765 COSTS_N_INSNS (68), /* int_div_di */
767 4 /* memory_latency */
770 COSTS_N_INSNS (4), /* fp_add */
771 COSTS_N_INSNS (4), /* fp_mult_sf */
772 COSTS_N_INSNS (5), /* fp_mult_df */
773 COSTS_N_INSNS (17), /* fp_div_sf */
774 COSTS_N_INSNS (32), /* fp_div_df */
775 COSTS_N_INSNS (4), /* int_mult_si */
776 COSTS_N_INSNS (7), /* int_mult_di */
777 COSTS_N_INSNS (42), /* int_div_si */
778 COSTS_N_INSNS (72), /* int_div_di */
780 4 /* memory_latency */
784 COSTS_N_INSNS (5), /* int_mult_si */
785 COSTS_N_INSNS (5), /* int_mult_di */
786 COSTS_N_INSNS (41), /* int_div_si */
787 COSTS_N_INSNS (41), /* int_div_di */
789 4 /* memory_latency */
792 COSTS_N_INSNS (8), /* fp_add */
793 COSTS_N_INSNS (8), /* fp_mult_sf */
794 COSTS_N_INSNS (10), /* fp_mult_df */
795 COSTS_N_INSNS (34), /* fp_div_sf */
796 COSTS_N_INSNS (64), /* fp_div_df */
797 COSTS_N_INSNS (5), /* int_mult_si */
798 COSTS_N_INSNS (5), /* int_mult_di */
799 COSTS_N_INSNS (41), /* int_div_si */
800 COSTS_N_INSNS (41), /* int_div_di */
802 4 /* memory_latency */
805 COSTS_N_INSNS (4), /* fp_add */
806 COSTS_N_INSNS (4), /* fp_mult_sf */
807 COSTS_N_INSNS (5), /* fp_mult_df */
808 COSTS_N_INSNS (17), /* fp_div_sf */
809 COSTS_N_INSNS (32), /* fp_div_df */
810 COSTS_N_INSNS (5), /* int_mult_si */
811 COSTS_N_INSNS (5), /* int_mult_di */
812 COSTS_N_INSNS (41), /* int_div_si */
813 COSTS_N_INSNS (41), /* int_div_di */
815 4 /* memory_latency */
819 COSTS_N_INSNS (5), /* int_mult_si */
820 COSTS_N_INSNS (5), /* int_mult_di */
821 COSTS_N_INSNS (41), /* int_div_si */
822 COSTS_N_INSNS (41), /* int_div_di */
824 4 /* memory_latency */
827 COSTS_N_INSNS (8), /* fp_add */
828 COSTS_N_INSNS (8), /* fp_mult_sf */
829 COSTS_N_INSNS (10), /* fp_mult_df */
830 COSTS_N_INSNS (34), /* fp_div_sf */
831 COSTS_N_INSNS (64), /* fp_div_df */
832 COSTS_N_INSNS (5), /* int_mult_si */
833 COSTS_N_INSNS (5), /* int_mult_di */
834 COSTS_N_INSNS (41), /* int_div_si */
835 COSTS_N_INSNS (41), /* int_div_di */
837 4 /* memory_latency */
840 COSTS_N_INSNS (4), /* fp_add */
841 COSTS_N_INSNS (4), /* fp_mult_sf */
842 COSTS_N_INSNS (5), /* fp_mult_df */
843 COSTS_N_INSNS (17), /* fp_div_sf */
844 COSTS_N_INSNS (32), /* fp_div_df */
845 COSTS_N_INSNS (5), /* int_mult_si */
846 COSTS_N_INSNS (5), /* int_mult_di */
847 COSTS_N_INSNS (41), /* int_div_si */
848 COSTS_N_INSNS (41), /* int_div_di */
850 4 /* memory_latency */
853 COSTS_N_INSNS (6), /* fp_add */
854 COSTS_N_INSNS (6), /* fp_mult_sf */
855 COSTS_N_INSNS (7), /* fp_mult_df */
856 COSTS_N_INSNS (25), /* fp_div_sf */
857 COSTS_N_INSNS (48), /* fp_div_df */
858 COSTS_N_INSNS (5), /* int_mult_si */
859 COSTS_N_INSNS (5), /* int_mult_di */
860 COSTS_N_INSNS (41), /* int_div_si */
861 COSTS_N_INSNS (41), /* int_div_di */
863 4 /* memory_latency */
880 COSTS_N_INSNS (5), /* int_mult_si */
881 COSTS_N_INSNS (5), /* int_mult_di */
882 COSTS_N_INSNS (72), /* int_div_si */
883 COSTS_N_INSNS (72), /* int_div_di */
885 4 /* memory_latency */
890 COSTS_N_INSNS (6), /* int_mult_si */
891 COSTS_N_INSNS (6), /* int_mult_di */
892 COSTS_N_INSNS (18), /* int_div_si */
893 COSTS_N_INSNS (35), /* int_div_di */
895 4 /* memory_latency */
898 COSTS_N_INSNS (2), /* fp_add */
899 COSTS_N_INSNS (4), /* fp_mult_sf */
900 COSTS_N_INSNS (5), /* fp_mult_df */
901 COSTS_N_INSNS (12), /* fp_div_sf */
902 COSTS_N_INSNS (19), /* fp_div_df */
903 COSTS_N_INSNS (2), /* int_mult_si */
904 COSTS_N_INSNS (2), /* int_mult_di */
905 COSTS_N_INSNS (35), /* int_div_si */
906 COSTS_N_INSNS (35), /* int_div_di */
908 4 /* memory_latency */
911 COSTS_N_INSNS (3), /* fp_add */
912 COSTS_N_INSNS (5), /* fp_mult_sf */
913 COSTS_N_INSNS (6), /* fp_mult_df */
914 COSTS_N_INSNS (15), /* fp_div_sf */
915 COSTS_N_INSNS (16), /* fp_div_df */
916 COSTS_N_INSNS (17), /* int_mult_si */
917 COSTS_N_INSNS (17), /* int_mult_di */
918 COSTS_N_INSNS (38), /* int_div_si */
919 COSTS_N_INSNS (38), /* int_div_di */
921 6 /* memory_latency */
924 COSTS_N_INSNS (6), /* fp_add */
925 COSTS_N_INSNS (7), /* fp_mult_sf */
926 COSTS_N_INSNS (8), /* fp_mult_df */
927 COSTS_N_INSNS (23), /* fp_div_sf */
928 COSTS_N_INSNS (36), /* fp_div_df */
929 COSTS_N_INSNS (10), /* int_mult_si */
930 COSTS_N_INSNS (10), /* int_mult_di */
931 COSTS_N_INSNS (69), /* int_div_si */
932 COSTS_N_INSNS (69), /* int_div_di */
934 6 /* memory_latency */
946 /* The only costs that appear to be updated here are
947 integer multiplication. */
949 COSTS_N_INSNS (4), /* int_mult_si */
950 COSTS_N_INSNS (6), /* int_mult_di */
951 COSTS_N_INSNS (69), /* int_div_si */
952 COSTS_N_INSNS (69), /* int_div_di */
954 4 /* memory_latency */
966 COSTS_N_INSNS (6), /* fp_add */
967 COSTS_N_INSNS (4), /* fp_mult_sf */
968 COSTS_N_INSNS (5), /* fp_mult_df */
969 COSTS_N_INSNS (23), /* fp_div_sf */
970 COSTS_N_INSNS (36), /* fp_div_df */
971 COSTS_N_INSNS (5), /* int_mult_si */
972 COSTS_N_INSNS (5), /* int_mult_di */
973 COSTS_N_INSNS (36), /* int_div_si */
974 COSTS_N_INSNS (36), /* int_div_di */
976 4 /* memory_latency */
979 COSTS_N_INSNS (6), /* fp_add */
980 COSTS_N_INSNS (5), /* fp_mult_sf */
981 COSTS_N_INSNS (6), /* fp_mult_df */
982 COSTS_N_INSNS (30), /* fp_div_sf */
983 COSTS_N_INSNS (59), /* fp_div_df */
984 COSTS_N_INSNS (3), /* int_mult_si */
985 COSTS_N_INSNS (4), /* int_mult_di */
986 COSTS_N_INSNS (42), /* int_div_si */
987 COSTS_N_INSNS (74), /* int_div_di */
989 4 /* memory_latency */
992 COSTS_N_INSNS (6), /* fp_add */
993 COSTS_N_INSNS (5), /* fp_mult_sf */
994 COSTS_N_INSNS (6), /* fp_mult_df */
995 COSTS_N_INSNS (30), /* fp_div_sf */
996 COSTS_N_INSNS (59), /* fp_div_df */
997 COSTS_N_INSNS (5), /* int_mult_si */
998 COSTS_N_INSNS (9), /* int_mult_di */
999 COSTS_N_INSNS (42), /* int_div_si */
1000 COSTS_N_INSNS (74), /* int_div_di */
1001 1, /* branch_cost */
1002 4 /* memory_latency */
1005 /* The only costs that are changed here are
1006 integer multiplication. */
1007 COSTS_N_INSNS (6), /* fp_add */
1008 COSTS_N_INSNS (7), /* fp_mult_sf */
1009 COSTS_N_INSNS (8), /* fp_mult_df */
1010 COSTS_N_INSNS (23), /* fp_div_sf */
1011 COSTS_N_INSNS (36), /* fp_div_df */
1012 COSTS_N_INSNS (5), /* int_mult_si */
1013 COSTS_N_INSNS (9), /* int_mult_di */
1014 COSTS_N_INSNS (69), /* int_div_si */
1015 COSTS_N_INSNS (69), /* int_div_di */
1016 1, /* branch_cost */
1017 4 /* memory_latency */
1023 /* The only costs that are changed here are
1024 integer multiplication. */
1025 COSTS_N_INSNS (6), /* fp_add */
1026 COSTS_N_INSNS (7), /* fp_mult_sf */
1027 COSTS_N_INSNS (8), /* fp_mult_df */
1028 COSTS_N_INSNS (23), /* fp_div_sf */
1029 COSTS_N_INSNS (36), /* fp_div_df */
1030 COSTS_N_INSNS (3), /* int_mult_si */
1031 COSTS_N_INSNS (8), /* int_mult_di */
1032 COSTS_N_INSNS (69), /* int_div_si */
1033 COSTS_N_INSNS (69), /* int_div_di */
1034 1, /* branch_cost */
1035 4 /* memory_latency */
1038 COSTS_N_INSNS (2), /* fp_add */
1039 COSTS_N_INSNS (2), /* fp_mult_sf */
1040 COSTS_N_INSNS (2), /* fp_mult_df */
1041 COSTS_N_INSNS (12), /* fp_div_sf */
1042 COSTS_N_INSNS (19), /* fp_div_df */
1043 COSTS_N_INSNS (5), /* int_mult_si */
1044 COSTS_N_INSNS (9), /* int_mult_di */
1045 COSTS_N_INSNS (34), /* int_div_si */
1046 COSTS_N_INSNS (66), /* int_div_di */
1047 1, /* branch_cost */
1048 4 /* memory_latency */
1051 /* These costs are the same as the SB-1A below. */
1052 COSTS_N_INSNS (4), /* fp_add */
1053 COSTS_N_INSNS (4), /* fp_mult_sf */
1054 COSTS_N_INSNS (4), /* fp_mult_df */
1055 COSTS_N_INSNS (24), /* fp_div_sf */
1056 COSTS_N_INSNS (32), /* fp_div_df */
1057 COSTS_N_INSNS (3), /* int_mult_si */
1058 COSTS_N_INSNS (4), /* int_mult_di */
1059 COSTS_N_INSNS (36), /* int_div_si */
1060 COSTS_N_INSNS (68), /* int_div_di */
1061 1, /* branch_cost */
1062 4 /* memory_latency */
1065 /* These costs are the same as the SB-1 above. */
1066 COSTS_N_INSNS (4), /* fp_add */
1067 COSTS_N_INSNS (4), /* fp_mult_sf */
1068 COSTS_N_INSNS (4), /* fp_mult_df */
1069 COSTS_N_INSNS (24), /* fp_div_sf */
1070 COSTS_N_INSNS (32), /* fp_div_df */
1071 COSTS_N_INSNS (3), /* int_mult_si */
1072 COSTS_N_INSNS (4), /* int_mult_di */
1073 COSTS_N_INSNS (36), /* int_div_si */
1074 COSTS_N_INSNS (68), /* int_div_di */
1075 1, /* branch_cost */
1076 4 /* memory_latency */
1083 COSTS_N_INSNS (8), /* int_mult_si */
1084 COSTS_N_INSNS (8), /* int_mult_di */
1085 COSTS_N_INSNS (72), /* int_div_si */
1086 COSTS_N_INSNS (72), /* int_div_di */
1087 1, /* branch_cost */
1088 4 /* memory_latency */
1092 static rtx mips_find_pic_call_symbol (rtx, rtx, bool);
1093 static int mips_register_move_cost (enum machine_mode, reg_class_t,
1095 static unsigned int mips_function_arg_boundary (enum machine_mode, const_tree);
1097 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1098 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1099 struct GTY (()) mflip_mips16_entry {
1103 static GTY ((param_is (struct mflip_mips16_entry))) htab_t mflip_mips16_htab;
1105 /* Hash table callbacks for mflip_mips16_htab. */
1108 mflip_mips16_htab_hash (const void *entry)
1110 return htab_hash_string (((const struct mflip_mips16_entry *) entry)->name);
1114 mflip_mips16_htab_eq (const void *entry, const void *name)
1116 return strcmp (((const struct mflip_mips16_entry *) entry)->name,
1117 (const char *) name) == 0;
1120 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1121 mode, false if it should next add an attribute for the opposite mode. */
1122 static GTY(()) bool mips16_flipper;
1124 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1125 for -mflip-mips16. Return true if it should use "mips16" and false if
1126 it should use "nomips16". */
1129 mflip_mips16_use_mips16_p (tree decl)
1131 struct mflip_mips16_entry *entry;
1136 /* Use the opposite of the command-line setting for anonymous decls. */
1137 if (!DECL_NAME (decl))
1138 return !mips_base_mips16;
1140 if (!mflip_mips16_htab)
1141 mflip_mips16_htab = htab_create_ggc (37, mflip_mips16_htab_hash,
1142 mflip_mips16_htab_eq, NULL);
1144 name = IDENTIFIER_POINTER (DECL_NAME (decl));
1145 hash = htab_hash_string (name);
1146 slot = htab_find_slot_with_hash (mflip_mips16_htab, name, hash, INSERT);
1147 entry = (struct mflip_mips16_entry *) *slot;
1150 mips16_flipper = !mips16_flipper;
1151 entry = ggc_alloc_mflip_mips16_entry ();
1153 entry->mips16_p = mips16_flipper ? !mips_base_mips16 : mips_base_mips16;
1156 return entry->mips16_p;
1159 /* Predicates to test for presence of "near" and "far"/"long_call"
1160 attributes on the given TYPE. */
1163 mips_near_type_p (const_tree type)
1165 return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL;
1169 mips_far_type_p (const_tree type)
1171 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL
1172 || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL);
1175 /* Similar predicates for "mips16"/"nomips16" function attributes. */
1178 mips_mips16_decl_p (const_tree decl)
1180 return lookup_attribute ("mips16", DECL_ATTRIBUTES (decl)) != NULL;
1184 mips_nomips16_decl_p (const_tree decl)
1186 return lookup_attribute ("nomips16", DECL_ATTRIBUTES (decl)) != NULL;
1189 /* Check if the interrupt attribute is set for a function. */
1192 mips_interrupt_type_p (tree type)
1194 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type)) != NULL;
1197 /* Check if the attribute to use shadow register set is set for a function. */
1200 mips_use_shadow_register_set_p (tree type)
1202 return lookup_attribute ("use_shadow_register_set",
1203 TYPE_ATTRIBUTES (type)) != NULL;
1206 /* Check if the attribute to keep interrupts masked is set for a function. */
1209 mips_keep_interrupts_masked_p (tree type)
1211 return lookup_attribute ("keep_interrupts_masked",
1212 TYPE_ATTRIBUTES (type)) != NULL;
1215 /* Check if the attribute to use debug exception return is set for
1219 mips_use_debug_exception_return_p (tree type)
1221 return lookup_attribute ("use_debug_exception_return",
1222 TYPE_ATTRIBUTES (type)) != NULL;
1225 /* Return true if function DECL is a MIPS16 function. Return the ambient
1226 setting if DECL is null. */
1229 mips_use_mips16_mode_p (tree decl)
1233 /* Nested functions must use the same frame pointer as their
1234 parent and must therefore use the same ISA mode. */
1235 tree parent = decl_function_context (decl);
1238 if (mips_mips16_decl_p (decl))
1240 if (mips_nomips16_decl_p (decl))
1243 return mips_base_mips16;
1246 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1249 mips_comp_type_attributes (const_tree type1, const_tree type2)
1251 /* Disallow mixed near/far attributes. */
1252 if (mips_far_type_p (type1) && mips_near_type_p (type2))
1254 if (mips_near_type_p (type1) && mips_far_type_p (type2))
1259 /* Implement TARGET_INSERT_ATTRIBUTES. */
1262 mips_insert_attributes (tree decl, tree *attributes)
1265 bool mips16_p, nomips16_p;
1267 /* Check for "mips16" and "nomips16" attributes. */
1268 mips16_p = lookup_attribute ("mips16", *attributes) != NULL;
1269 nomips16_p = lookup_attribute ("nomips16", *attributes) != NULL;
1270 if (TREE_CODE (decl) != FUNCTION_DECL)
1273 error ("%qs attribute only applies to functions", "mips16");
1275 error ("%qs attribute only applies to functions", "nomips16");
1279 mips16_p |= mips_mips16_decl_p (decl);
1280 nomips16_p |= mips_nomips16_decl_p (decl);
1281 if (mips16_p || nomips16_p)
1283 /* DECL cannot be simultaneously "mips16" and "nomips16". */
1284 if (mips16_p && nomips16_p)
1285 error ("%qE cannot have both %<mips16%> and "
1286 "%<nomips16%> attributes",
1289 else if (TARGET_FLIP_MIPS16 && !DECL_ARTIFICIAL (decl))
1291 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1292 "mips16" attribute, arbitrarily pick one. We must pick the same
1293 setting for duplicate declarations of a function. */
1294 name = mflip_mips16_use_mips16_p (decl) ? "mips16" : "nomips16";
1295 *attributes = tree_cons (get_identifier (name), NULL, *attributes);
1300 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1303 mips_merge_decl_attributes (tree olddecl, tree newdecl)
1305 /* The decls' "mips16" and "nomips16" attributes must match exactly. */
1306 if (mips_mips16_decl_p (olddecl) != mips_mips16_decl_p (newdecl))
1307 error ("%qE redeclared with conflicting %qs attributes",
1308 DECL_NAME (newdecl), "mips16");
1309 if (mips_nomips16_decl_p (olddecl) != mips_nomips16_decl_p (newdecl))
1310 error ("%qE redeclared with conflicting %qs attributes",
1311 DECL_NAME (newdecl), "nomips16");
1313 return merge_attributes (DECL_ATTRIBUTES (olddecl),
1314 DECL_ATTRIBUTES (newdecl));
1317 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1318 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1321 mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr)
1323 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
1325 *base_ptr = XEXP (x, 0);
1326 *offset_ptr = INTVAL (XEXP (x, 1));
1335 static unsigned int mips_build_integer (struct mips_integer_op *,
1336 unsigned HOST_WIDE_INT);
1338 /* A subroutine of mips_build_integer, with the same interface.
1339 Assume that the final action in the sequence should be a left shift. */
1342 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1344 unsigned int i, shift;
1346 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1347 since signed numbers are easier to load than unsigned ones. */
1349 while ((value & 1) == 0)
1350 value /= 2, shift++;
1352 i = mips_build_integer (codes, value);
1353 codes[i].code = ASHIFT;
1354 codes[i].value = shift;
1358 /* As for mips_build_shift, but assume that the final action will be
1359 an IOR or PLUS operation. */
1362 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1364 unsigned HOST_WIDE_INT high;
1367 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1368 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
1370 /* The constant is too complex to load with a simple LUI/ORI pair,
1371 so we want to give the recursive call as many trailing zeros as
1372 possible. In this case, we know bit 16 is set and that the
1373 low 16 bits form a negative number. If we subtract that number
1374 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1375 i = mips_build_integer (codes, CONST_HIGH_PART (value));
1376 codes[i].code = PLUS;
1377 codes[i].value = CONST_LOW_PART (value);
1381 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1382 bits gives a value with at least 17 trailing zeros. */
1383 i = mips_build_integer (codes, high);
1384 codes[i].code = IOR;
1385 codes[i].value = value & 0xffff;
1390 /* Fill CODES with a sequence of rtl operations to load VALUE.
1391 Return the number of operations needed. */
1394 mips_build_integer (struct mips_integer_op *codes,
1395 unsigned HOST_WIDE_INT value)
1397 if (SMALL_OPERAND (value)
1398 || SMALL_OPERAND_UNSIGNED (value)
1399 || LUI_OPERAND (value))
1401 /* The value can be loaded with a single instruction. */
1402 codes[0].code = UNKNOWN;
1403 codes[0].value = value;
1406 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
1408 /* Either the constant is a simple LUI/ORI combination or its
1409 lowest bit is set. We don't want to shift in this case. */
1410 return mips_build_lower (codes, value);
1412 else if ((value & 0xffff) == 0)
1414 /* The constant will need at least three actions. The lowest
1415 16 bits are clear, so the final action will be a shift. */
1416 return mips_build_shift (codes, value);
1420 /* The final action could be a shift, add or inclusive OR.
1421 Rather than use a complex condition to select the best
1422 approach, try both mips_build_shift and mips_build_lower
1423 and pick the one that gives the shortest sequence.
1424 Note that this case is only used once per constant. */
1425 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1426 unsigned int cost, alt_cost;
1428 cost = mips_build_shift (codes, value);
1429 alt_cost = mips_build_lower (alt_codes, value);
1430 if (alt_cost < cost)
1432 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
1439 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
1442 mips_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
1444 return mips_const_insns (x) > 0;
1447 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
1450 mips16_stub_function (const char *name)
1454 x = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
1455 SYMBOL_REF_FLAGS (x) |= (SYMBOL_FLAG_EXTERNAL | SYMBOL_FLAG_FUNCTION);
1459 /* Return true if symbols of type TYPE require a GOT access. */
1462 mips_got_symbol_type_p (enum mips_symbol_type type)
1466 case SYMBOL_GOT_PAGE_OFST:
1467 case SYMBOL_GOT_DISP:
1475 /* Return true if X is a thread-local symbol. */
1478 mips_tls_symbol_p (rtx x)
1480 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1483 /* Return true if SYMBOL_REF X is associated with a global symbol
1484 (in the STB_GLOBAL sense). */
1487 mips_global_symbol_p (const_rtx x)
1489 const_tree decl = SYMBOL_REF_DECL (x);
1492 return !SYMBOL_REF_LOCAL_P (x) || SYMBOL_REF_EXTERNAL_P (x);
1494 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1495 or weak symbols. Relocations in the object file will be against
1496 the target symbol, so it's that symbol's binding that matters here. */
1497 return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl));
1500 /* Return true if function X is a libgcc MIPS16 stub function. */
1503 mips16_stub_function_p (const_rtx x)
1505 return (GET_CODE (x) == SYMBOL_REF
1506 && strncmp (XSTR (x, 0), "__mips16_", 9) == 0);
1509 /* Return true if function X is a locally-defined and locally-binding
1513 mips16_local_function_p (const_rtx x)
1515 return (GET_CODE (x) == SYMBOL_REF
1516 && SYMBOL_REF_LOCAL_P (x)
1517 && !SYMBOL_REF_EXTERNAL_P (x)
1518 && mips_use_mips16_mode_p (SYMBOL_REF_DECL (x)));
1521 /* Return true if SYMBOL_REF X binds locally. */
1524 mips_symbol_binds_local_p (const_rtx x)
1526 return (SYMBOL_REF_DECL (x)
1527 ? targetm.binds_local_p (SYMBOL_REF_DECL (x))
1528 : SYMBOL_REF_LOCAL_P (x));
1531 /* Return true if rtx constants of mode MODE should be put into a small
1535 mips_rtx_constant_in_small_data_p (enum machine_mode mode)
1537 return (!TARGET_EMBEDDED_DATA
1538 && TARGET_LOCAL_SDATA
1539 && GET_MODE_SIZE (mode) <= mips_small_data_threshold);
1542 /* Return true if X should not be moved directly into register $25.
1543 We need this because many versions of GAS will treat "la $25,foo" as
1544 part of a call sequence and so allow a global "foo" to be lazily bound. */
1547 mips_dangerous_for_la25_p (rtx x)
1549 return (!TARGET_EXPLICIT_RELOCS
1551 && GET_CODE (x) == SYMBOL_REF
1552 && mips_global_symbol_p (x));
1555 /* Return true if calls to X might need $25 to be valid on entry. */
1558 mips_use_pic_fn_addr_reg_p (const_rtx x)
1560 if (!TARGET_USE_PIC_FN_ADDR_REG)
1563 /* MIPS16 stub functions are guaranteed not to use $25. */
1564 if (mips16_stub_function_p (x))
1567 if (GET_CODE (x) == SYMBOL_REF)
1569 /* If PLTs and copy relocations are available, the static linker
1570 will make sure that $25 is valid on entry to the target function. */
1571 if (TARGET_ABICALLS_PIC0)
1574 /* Locally-defined functions use absolute accesses to set up
1575 the global pointer. */
1576 if (TARGET_ABSOLUTE_ABICALLS
1577 && mips_symbol_binds_local_p (x)
1578 && !SYMBOL_REF_EXTERNAL_P (x))
1585 /* Return the method that should be used to access SYMBOL_REF or
1586 LABEL_REF X in context CONTEXT. */
1588 static enum mips_symbol_type
1589 mips_classify_symbol (const_rtx x, enum mips_symbol_context context)
1592 return SYMBOL_GOT_DISP;
1594 if (GET_CODE (x) == LABEL_REF)
1596 /* Only return SYMBOL_PC_RELATIVE if we are generating MIPS16
1597 code and if we know that the label is in the current function's
1598 text section. LABEL_REFs are used for jump tables as well as
1599 text labels, so we must check whether jump tables live in the
1601 if (TARGET_MIPS16_SHORT_JUMP_TABLES
1602 && !LABEL_REF_NONLOCAL_P (x))
1603 return SYMBOL_PC_RELATIVE;
1605 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1606 return SYMBOL_GOT_PAGE_OFST;
1608 return SYMBOL_ABSOLUTE;
1611 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1613 if (SYMBOL_REF_TLS_MODEL (x))
1616 if (CONSTANT_POOL_ADDRESS_P (x))
1618 if (TARGET_MIPS16_TEXT_LOADS)
1619 return SYMBOL_PC_RELATIVE;
1621 if (TARGET_MIPS16_PCREL_LOADS && context == SYMBOL_CONTEXT_MEM)
1622 return SYMBOL_PC_RELATIVE;
1624 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x)))
1625 return SYMBOL_GP_RELATIVE;
1628 /* Do not use small-data accesses for weak symbols; they may end up
1630 if (TARGET_GPOPT && SYMBOL_REF_SMALL_P (x) && !SYMBOL_REF_WEAK (x))
1631 return SYMBOL_GP_RELATIVE;
1633 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1635 if (TARGET_ABICALLS_PIC2
1636 && !(TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x)))
1638 /* There are three cases to consider:
1640 - o32 PIC (either with or without explicit relocs)
1641 - n32/n64 PIC without explicit relocs
1642 - n32/n64 PIC with explicit relocs
1644 In the first case, both local and global accesses will use an
1645 R_MIPS_GOT16 relocation. We must correctly predict which of
1646 the two semantics (local or global) the assembler and linker
1647 will apply. The choice depends on the symbol's binding rather
1648 than its visibility.
1650 In the second case, the assembler will not use R_MIPS_GOT16
1651 relocations, but it chooses between local and global accesses
1652 in the same way as for o32 PIC.
1654 In the third case we have more freedom since both forms of
1655 access will work for any kind of symbol. However, there seems
1656 little point in doing things differently. */
1657 if (mips_global_symbol_p (x))
1658 return SYMBOL_GOT_DISP;
1660 return SYMBOL_GOT_PAGE_OFST;
1663 return SYMBOL_ABSOLUTE;
1666 /* Classify the base of symbolic expression X, given that X appears in
1669 static enum mips_symbol_type
1670 mips_classify_symbolic_expression (rtx x, enum mips_symbol_context context)
1674 split_const (x, &x, &offset);
1675 if (UNSPEC_ADDRESS_P (x))
1676 return UNSPEC_ADDRESS_TYPE (x);
1678 return mips_classify_symbol (x, context);
1681 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1682 is the alignment in bytes of SYMBOL_REF X. */
1685 mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset)
1687 HOST_WIDE_INT align;
1689 align = SYMBOL_REF_DECL (x) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x)) : 1;
1690 return IN_RANGE (offset, 0, align - 1);
1693 /* Return true if X is a symbolic constant that can be used in context
1694 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1697 mips_symbolic_constant_p (rtx x, enum mips_symbol_context context,
1698 enum mips_symbol_type *symbol_type)
1702 split_const (x, &x, &offset);
1703 if (UNSPEC_ADDRESS_P (x))
1705 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1706 x = UNSPEC_ADDRESS (x);
1708 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1710 *symbol_type = mips_classify_symbol (x, context);
1711 if (*symbol_type == SYMBOL_TLS)
1717 if (offset == const0_rtx)
1720 /* Check whether a nonzero offset is valid for the underlying
1722 switch (*symbol_type)
1724 case SYMBOL_ABSOLUTE:
1725 case SYMBOL_64_HIGH:
1728 /* If the target has 64-bit pointers and the object file only
1729 supports 32-bit symbols, the values of those symbols will be
1730 sign-extended. In this case we can't allow an arbitrary offset
1731 in case the 32-bit value X + OFFSET has a different sign from X. */
1732 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1733 return offset_within_block_p (x, INTVAL (offset));
1735 /* In other cases the relocations can handle any offset. */
1738 case SYMBOL_PC_RELATIVE:
1739 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1740 In this case, we no longer have access to the underlying constant,
1741 but the original symbol-based access was known to be valid. */
1742 if (GET_CODE (x) == LABEL_REF)
1747 case SYMBOL_GP_RELATIVE:
1748 /* Make sure that the offset refers to something within the
1749 same object block. This should guarantee that the final
1750 PC- or GP-relative offset is within the 16-bit limit. */
1751 return offset_within_block_p (x, INTVAL (offset));
1753 case SYMBOL_GOT_PAGE_OFST:
1754 case SYMBOL_GOTOFF_PAGE:
1755 /* If the symbol is global, the GOT entry will contain the symbol's
1756 address, and we will apply a 16-bit offset after loading it.
1757 If the symbol is local, the linker should provide enough local
1758 GOT entries for a 16-bit offset, but larger offsets may lead
1760 return SMALL_INT (offset);
1764 /* There is no carry between the HI and LO REL relocations, so the
1765 offset is only valid if we know it won't lead to such a carry. */
1766 return mips_offset_within_alignment_p (x, INTVAL (offset));
1768 case SYMBOL_GOT_DISP:
1769 case SYMBOL_GOTOFF_DISP:
1770 case SYMBOL_GOTOFF_CALL:
1771 case SYMBOL_GOTOFF_LOADGP:
1774 case SYMBOL_GOTTPREL:
1782 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
1783 single instruction. We rely on the fact that, in the worst case,
1784 all instructions involved in a MIPS16 address calculation are usually
1788 mips_symbol_insns_1 (enum mips_symbol_type type, enum machine_mode mode)
1790 if (mips_use_pcrel_pool_p[(int) type])
1792 if (mode == MAX_MACHINE_MODE)
1793 /* LEAs will be converted into constant-pool references by
1795 type = SYMBOL_PC_RELATIVE;
1797 /* The constant must be loaded and then dereferenced. */
1803 case SYMBOL_ABSOLUTE:
1804 /* When using 64-bit symbols, we need 5 preparatory instructions,
1807 lui $at,%highest(symbol)
1808 daddiu $at,$at,%higher(symbol)
1810 daddiu $at,$at,%hi(symbol)
1813 The final address is then $at + %lo(symbol). With 32-bit
1814 symbols we just need a preparatory LUI for normal mode and
1815 a preparatory LI and SLL for MIPS16. */
1816 return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2;
1818 case SYMBOL_GP_RELATIVE:
1819 /* Treat GP-relative accesses as taking a single instruction on
1820 MIPS16 too; the copy of $gp can often be shared. */
1823 case SYMBOL_PC_RELATIVE:
1824 /* PC-relative constants can be only be used with ADDIUPC,
1825 DADDIUPC, LWPC and LDPC. */
1826 if (mode == MAX_MACHINE_MODE
1827 || GET_MODE_SIZE (mode) == 4
1828 || GET_MODE_SIZE (mode) == 8)
1831 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
1834 case SYMBOL_GOT_DISP:
1835 /* The constant will have to be loaded from the GOT before it
1836 is used in an address. */
1837 if (mode != MAX_MACHINE_MODE)
1842 case SYMBOL_GOT_PAGE_OFST:
1843 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
1844 local/global classification is accurate. The worst cases are:
1846 (1) For local symbols when generating o32 or o64 code. The assembler
1852 ...and the final address will be $at + %lo(symbol).
1854 (2) For global symbols when -mxgot. The assembler will use:
1856 lui $at,%got_hi(symbol)
1859 ...and the final address will be $at + %got_lo(symbol). */
1862 case SYMBOL_GOTOFF_PAGE:
1863 case SYMBOL_GOTOFF_DISP:
1864 case SYMBOL_GOTOFF_CALL:
1865 case SYMBOL_GOTOFF_LOADGP:
1866 case SYMBOL_64_HIGH:
1872 case SYMBOL_GOTTPREL:
1875 /* A 16-bit constant formed by a single relocation, or a 32-bit
1876 constant formed from a high 16-bit relocation and a low 16-bit
1877 relocation. Use mips_split_p to determine which. 32-bit
1878 constants need an "lui; addiu" sequence for normal mode and
1879 an "li; sll; addiu" sequence for MIPS16 mode. */
1880 return !mips_split_p[type] ? 1 : TARGET_MIPS16 ? 3 : 2;
1883 /* We don't treat a bare TLS symbol as a constant. */
1889 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
1890 to load symbols of type TYPE into a register. Return 0 if the given
1891 type of symbol cannot be used as an immediate operand.
1893 Otherwise, return the number of instructions needed to load or store
1894 values of mode MODE to or from addresses of type TYPE. Return 0 if
1895 the given type of symbol is not valid in addresses.
1897 In both cases, treat extended MIPS16 instructions as two instructions. */
1900 mips_symbol_insns (enum mips_symbol_type type, enum machine_mode mode)
1902 return mips_symbol_insns_1 (type, mode) * (TARGET_MIPS16 ? 2 : 1);
1905 /* A for_each_rtx callback. Stop the search if *X references a
1906 thread-local symbol. */
1909 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1911 return mips_tls_symbol_p (*x);
1914 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1917 mips_cannot_force_const_mem (enum machine_mode mode, rtx x)
1919 enum mips_symbol_type type;
1922 /* There is no assembler syntax for expressing an address-sized
1924 if (GET_CODE (x) == HIGH)
1927 /* As an optimization, reject constants that mips_legitimize_move
1930 Suppose we have a multi-instruction sequence that loads constant C
1931 into register R. If R does not get allocated a hard register, and
1932 R is used in an operand that allows both registers and memory
1933 references, reload will consider forcing C into memory and using
1934 one of the instruction's memory alternatives. Returning false
1935 here will force it to use an input reload instead. */
1936 if (CONST_INT_P (x) && mips_legitimate_constant_p (mode, x))
1939 split_const (x, &base, &offset);
1940 if (mips_symbolic_constant_p (base, SYMBOL_CONTEXT_LEA, &type))
1942 /* See whether we explicitly want these symbols in the pool. */
1943 if (mips_use_pcrel_pool_p[(int) type])
1946 /* The same optimization as for CONST_INT. */
1947 if (SMALL_INT (offset) && mips_symbol_insns (type, MAX_MACHINE_MODE) > 0)
1950 /* If MIPS16 constant pools live in the text section, they should
1951 not refer to anything that might need run-time relocation. */
1952 if (TARGET_MIPS16_PCREL_LOADS && mips_got_symbol_type_p (type))
1956 /* TLS symbols must be computed by mips_legitimize_move. */
1957 if (for_each_rtx (&x, &mips_tls_symbol_ref_1, NULL))
1963 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
1964 constants when we're using a per-function constant pool. */
1967 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
1968 const_rtx x ATTRIBUTE_UNUSED)
1970 return !TARGET_MIPS16_PCREL_LOADS;
1973 /* Return true if register REGNO is a valid base register for mode MODE.
1974 STRICT_P is true if REG_OK_STRICT is in effect. */
1977 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode,
1980 if (!HARD_REGISTER_NUM_P (regno))
1984 regno = reg_renumber[regno];
1987 /* These fake registers will be eliminated to either the stack or
1988 hard frame pointer, both of which are usually valid base registers.
1989 Reload deals with the cases where the eliminated form isn't valid. */
1990 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
1993 /* In MIPS16 mode, the stack pointer can only address word and doubleword
1994 values, nothing smaller. There are two problems here:
1996 (a) Instantiating virtual registers can introduce new uses of the
1997 stack pointer. If these virtual registers are valid addresses,
1998 the stack pointer should be too.
2000 (b) Most uses of the stack pointer are not made explicit until
2001 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
2002 We don't know until that stage whether we'll be eliminating to the
2003 stack pointer (which needs the restriction) or the hard frame
2004 pointer (which doesn't).
2006 All in all, it seems more consistent to only enforce this restriction
2007 during and after reload. */
2008 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
2009 return !strict_p || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
2011 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
2014 /* Return true if X is a valid base register for mode MODE.
2015 STRICT_P is true if REG_OK_STRICT is in effect. */
2018 mips_valid_base_register_p (rtx x, enum machine_mode mode, bool strict_p)
2020 if (!strict_p && GET_CODE (x) == SUBREG)
2024 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p));
2027 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2028 can address a value of mode MODE. */
2031 mips_valid_offset_p (rtx x, enum machine_mode mode)
2033 /* Check that X is a signed 16-bit number. */
2034 if (!const_arith_operand (x, Pmode))
2037 /* We may need to split multiword moves, so make sure that every word
2039 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2040 && !SMALL_OPERAND (INTVAL (x) + GET_MODE_SIZE (mode) - UNITS_PER_WORD))
2046 /* Return true if a LO_SUM can address a value of mode MODE when the
2047 LO_SUM symbol has type SYMBOL_TYPE. */
2050 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type, enum machine_mode mode)
2052 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2054 if (mips_symbol_insns (symbol_type, mode) == 0)
2057 /* Check that there is a known low-part relocation. */
2058 if (mips_lo_relocs[symbol_type] == NULL)
2061 /* We may need to split multiword moves, so make sure that each word
2062 can be accessed without inducing a carry. This is mainly needed
2063 for o64, which has historically only guaranteed 64-bit alignment
2064 for 128-bit types. */
2065 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2066 && GET_MODE_BITSIZE (mode) > GET_MODE_ALIGNMENT (mode))
2072 /* Return true if X is a valid address for machine mode MODE. If it is,
2073 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2077 mips_classify_address (struct mips_address_info *info, rtx x,
2078 enum machine_mode mode, bool strict_p)
2080 switch (GET_CODE (x))
2084 info->type = ADDRESS_REG;
2086 info->offset = const0_rtx;
2087 return mips_valid_base_register_p (info->reg, mode, strict_p);
2090 info->type = ADDRESS_REG;
2091 info->reg = XEXP (x, 0);
2092 info->offset = XEXP (x, 1);
2093 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2094 && mips_valid_offset_p (info->offset, mode));
2097 info->type = ADDRESS_LO_SUM;
2098 info->reg = XEXP (x, 0);
2099 info->offset = XEXP (x, 1);
2100 /* We have to trust the creator of the LO_SUM to do something vaguely
2101 sane. Target-independent code that creates a LO_SUM should also
2102 create and verify the matching HIGH. Target-independent code that
2103 adds an offset to a LO_SUM must prove that the offset will not
2104 induce a carry. Failure to do either of these things would be
2105 a bug, and we are not required to check for it here. The MIPS
2106 backend itself should only create LO_SUMs for valid symbolic
2107 constants, with the high part being either a HIGH or a copy
2110 = mips_classify_symbolic_expression (info->offset, SYMBOL_CONTEXT_MEM);
2111 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2112 && mips_valid_lo_sum_p (info->symbol_type, mode));
2115 /* Small-integer addresses don't occur very often, but they
2116 are legitimate if $0 is a valid base register. */
2117 info->type = ADDRESS_CONST_INT;
2118 return !TARGET_MIPS16 && SMALL_INT (x);
2123 info->type = ADDRESS_SYMBOLIC;
2124 return (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_MEM,
2126 && mips_symbol_insns (info->symbol_type, mode) > 0
2127 && !mips_split_p[info->symbol_type]);
2134 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2137 mips_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
2139 struct mips_address_info addr;
2141 return mips_classify_address (&addr, x, mode, strict_p);
2144 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
2147 mips_stack_address_p (rtx x, enum machine_mode mode)
2149 struct mips_address_info addr;
2151 return (mips_classify_address (&addr, x, mode, false)
2152 && addr.type == ADDRESS_REG
2153 && addr.reg == stack_pointer_rtx);
2156 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2157 address instruction. Note that such addresses are not considered
2158 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2159 is so restricted. */
2162 mips_lwxs_address_p (rtx addr)
2165 && GET_CODE (addr) == PLUS
2166 && REG_P (XEXP (addr, 1)))
2168 rtx offset = XEXP (addr, 0);
2169 if (GET_CODE (offset) == MULT
2170 && REG_P (XEXP (offset, 0))
2171 && CONST_INT_P (XEXP (offset, 1))
2172 && INTVAL (XEXP (offset, 1)) == 4)
2178 /* Return true if ADDR matches the pattern for the L{B,H,W,D}{,U}X load
2179 indexed address instruction. Note that such addresses are
2180 not considered legitimate in the TARGET_LEGITIMATE_ADDRESS_P
2181 sense, because their use is so restricted. */
2184 mips_lx_address_p (rtx addr, enum machine_mode mode)
2186 if (GET_CODE (addr) != PLUS
2187 || !REG_P (XEXP (addr, 0))
2188 || !REG_P (XEXP (addr, 1)))
2190 if (ISA_HAS_LBX && mode == QImode)
2192 if (ISA_HAS_LHX && mode == HImode)
2194 if (ISA_HAS_LWX && mode == SImode)
2196 if (ISA_HAS_LDX && mode == DImode)
2201 /* Return true if a value at OFFSET bytes from base register BASE can be
2202 accessed using an unextended MIPS16 instruction. MODE is the mode of
2205 Usually the offset in an unextended instruction is a 5-bit field.
2206 The offset is unsigned and shifted left once for LH and SH, twice
2207 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2208 an 8-bit immediate field that's shifted left twice. */
2211 mips16_unextended_reference_p (enum machine_mode mode, rtx base,
2212 unsigned HOST_WIDE_INT offset)
2214 if (mode != BLKmode && offset % GET_MODE_SIZE (mode) == 0)
2216 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
2217 return offset < 256U * GET_MODE_SIZE (mode);
2218 return offset < 32U * GET_MODE_SIZE (mode);
2223 /* Return the number of instructions needed to load or store a value
2224 of mode MODE at address X. Return 0 if X isn't valid for MODE.
2225 Assume that multiword moves may need to be split into word moves
2226 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2229 For MIPS16 code, count extended instructions as two instructions. */
2232 mips_address_insns (rtx x, enum machine_mode mode, bool might_split_p)
2234 struct mips_address_info addr;
2237 /* BLKmode is used for single unaligned loads and stores and should
2238 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2239 meaningless, so we have to single it out as a special case one way
2241 if (mode != BLKmode && might_split_p)
2242 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2246 if (mips_classify_address (&addr, x, mode, false))
2251 && !mips16_unextended_reference_p (mode, addr.reg,
2252 UINTVAL (addr.offset)))
2256 case ADDRESS_LO_SUM:
2257 return TARGET_MIPS16 ? factor * 2 : factor;
2259 case ADDRESS_CONST_INT:
2262 case ADDRESS_SYMBOLIC:
2263 return factor * mips_symbol_insns (addr.symbol_type, mode);
2268 /* Return the number of instructions needed to load constant X.
2269 Return 0 if X isn't a valid constant. */
2272 mips_const_insns (rtx x)
2274 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2275 enum mips_symbol_type symbol_type;
2278 switch (GET_CODE (x))
2281 if (!mips_symbolic_constant_p (XEXP (x, 0), SYMBOL_CONTEXT_LEA,
2283 || !mips_split_p[symbol_type])
2286 /* This is simply an LUI for normal mode. It is an extended
2287 LI followed by an extended SLL for MIPS16. */
2288 return TARGET_MIPS16 ? 4 : 1;
2292 /* Unsigned 8-bit constants can be loaded using an unextended
2293 LI instruction. Unsigned 16-bit constants can be loaded
2294 using an extended LI. Negative constants must be loaded
2295 using LI and then negated. */
2296 return (IN_RANGE (INTVAL (x), 0, 255) ? 1
2297 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
2298 : IN_RANGE (-INTVAL (x), 0, 255) ? 2
2299 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
2302 return mips_build_integer (codes, INTVAL (x));
2306 /* Allow zeros for normal mode, where we can use $0. */
2307 return !TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0;
2313 /* See if we can refer to X directly. */
2314 if (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_LEA, &symbol_type))
2315 return mips_symbol_insns (symbol_type, MAX_MACHINE_MODE);
2317 /* Otherwise try splitting the constant into a base and offset.
2318 If the offset is a 16-bit value, we can load the base address
2319 into a register and then use (D)ADDIU to add in the offset.
2320 If the offset is larger, we can load the base and offset
2321 into separate registers and add them together with (D)ADDU.
2322 However, the latter is only possible before reload; during
2323 and after reload, we must have the option of forcing the
2324 constant into the pool instead. */
2325 split_const (x, &x, &offset);
2328 int n = mips_const_insns (x);
2331 if (SMALL_INT (offset))
2333 else if (!targetm.cannot_force_const_mem (GET_MODE (x), x))
2334 return n + 1 + mips_build_integer (codes, INTVAL (offset));
2341 return mips_symbol_insns (mips_classify_symbol (x, SYMBOL_CONTEXT_LEA),
2349 /* X is a doubleword constant that can be handled by splitting it into
2350 two words and loading each word separately. Return the number of
2351 instructions required to do this. */
2354 mips_split_const_insns (rtx x)
2356 unsigned int low, high;
2358 low = mips_const_insns (mips_subword (x, false));
2359 high = mips_const_insns (mips_subword (x, true));
2360 gcc_assert (low > 0 && high > 0);
2364 /* Return the number of instructions needed to implement INSN,
2365 given that it loads from or stores to MEM. Count extended
2366 MIPS16 instructions as two instructions. */
2369 mips_load_store_insns (rtx mem, rtx insn)
2371 enum machine_mode mode;
2375 gcc_assert (MEM_P (mem));
2376 mode = GET_MODE (mem);
2378 /* Try to prove that INSN does not need to be split. */
2379 might_split_p = true;
2380 if (GET_MODE_BITSIZE (mode) == 64)
2382 set = single_set (insn);
2383 if (set && !mips_split_64bit_move_p (SET_DEST (set), SET_SRC (set)))
2384 might_split_p = false;
2387 return mips_address_insns (XEXP (mem, 0), mode, might_split_p);
2390 /* Return the number of instructions needed for an integer division. */
2393 mips_idiv_insns (void)
2398 if (TARGET_CHECK_ZERO_DIV)
2400 if (GENERATE_DIVIDE_TRAPS)
2406 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
2411 /* Emit a move from SRC to DEST. Assume that the move expanders can
2412 handle all moves if !can_create_pseudo_p (). The distinction is
2413 important because, unlike emit_move_insn, the move expanders know
2414 how to force Pmode objects into the constant pool even when the
2415 constant pool address is not itself legitimate. */
2418 mips_emit_move (rtx dest, rtx src)
2420 return (can_create_pseudo_p ()
2421 ? emit_move_insn (dest, src)
2422 : emit_move_insn_1 (dest, src));
2425 /* Emit an instruction of the form (set TARGET (CODE OP0)). */
2428 mips_emit_unary (enum rtx_code code, rtx target, rtx op0)
2430 emit_insn (gen_rtx_SET (VOIDmode, target,
2431 gen_rtx_fmt_e (code, GET_MODE (op0), op0)));
2434 /* Compute (CODE OP0) and store the result in a new register of mode MODE.
2435 Return that new register. */
2438 mips_force_unary (enum machine_mode mode, enum rtx_code code, rtx op0)
2442 reg = gen_reg_rtx (mode);
2443 mips_emit_unary (code, reg, op0);
2447 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2450 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
2452 emit_insn (gen_rtx_SET (VOIDmode, target,
2453 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
2456 /* Compute (CODE OP0 OP1) and store the result in a new register
2457 of mode MODE. Return that new register. */
2460 mips_force_binary (enum machine_mode mode, enum rtx_code code, rtx op0, rtx op1)
2464 reg = gen_reg_rtx (mode);
2465 mips_emit_binary (code, reg, op0, op1);
2469 /* Copy VALUE to a register and return that register. If new pseudos
2470 are allowed, copy it into a new register, otherwise use DEST. */
2473 mips_force_temporary (rtx dest, rtx value)
2475 if (can_create_pseudo_p ())
2476 return force_reg (Pmode, value);
2479 mips_emit_move (dest, value);
2484 /* Emit a call sequence with call pattern PATTERN and return the call
2485 instruction itself (which is not necessarily the last instruction
2486 emitted). ORIG_ADDR is the original, unlegitimized address,
2487 ADDR is the legitimized form, and LAZY_P is true if the call
2488 address is lazily-bound. */
2491 mips_emit_call_insn (rtx pattern, rtx orig_addr, rtx addr, bool lazy_p)
2495 insn = emit_call_insn (pattern);
2497 if (TARGET_MIPS16 && mips_use_pic_fn_addr_reg_p (orig_addr))
2499 /* MIPS16 JALRs only take MIPS16 registers. If the target
2500 function requires $25 to be valid on entry, we must copy it
2501 there separately. The move instruction can be put in the
2502 call's delay slot. */
2503 reg = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
2504 emit_insn_before (gen_move_insn (reg, addr), insn);
2505 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
2509 /* Lazy-binding stubs require $gp to be valid on entry. */
2510 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
2514 /* See the comment above load_call<mode> for details. */
2515 use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
2516 gen_rtx_REG (Pmode, GOT_VERSION_REGNUM));
2517 emit_insn (gen_update_got_version ());
2522 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2523 then add CONST_INT OFFSET to the result. */
2526 mips_unspec_address_offset (rtx base, rtx offset,
2527 enum mips_symbol_type symbol_type)
2529 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
2530 UNSPEC_ADDRESS_FIRST + symbol_type);
2531 if (offset != const0_rtx)
2532 base = gen_rtx_PLUS (Pmode, base, offset);
2533 return gen_rtx_CONST (Pmode, base);
2536 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2537 type SYMBOL_TYPE. */
2540 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
2544 split_const (address, &base, &offset);
2545 return mips_unspec_address_offset (base, offset, symbol_type);
2548 /* If OP is an UNSPEC address, return the address to which it refers,
2549 otherwise return OP itself. */
2552 mips_strip_unspec_address (rtx op)
2556 split_const (op, &base, &offset);
2557 if (UNSPEC_ADDRESS_P (base))
2558 op = plus_constant (UNSPEC_ADDRESS (base), INTVAL (offset));
2562 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2563 high part to BASE and return the result. Just return BASE otherwise.
2564 TEMP is as for mips_force_temporary.
2566 The returned expression can be used as the first operand to a LO_SUM. */
2569 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
2570 enum mips_symbol_type symbol_type)
2572 if (mips_split_p[symbol_type])
2574 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
2575 addr = mips_force_temporary (temp, addr);
2576 base = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
2581 /* Return an instruction that copies $gp into register REG. We want
2582 GCC to treat the register's value as constant, so that its value
2583 can be rematerialized on demand. */
2586 gen_load_const_gp (rtx reg)
2588 return PMODE_INSN (gen_load_const_gp, (reg));
2591 /* Return a pseudo register that contains the value of $gp throughout
2592 the current function. Such registers are needed by MIPS16 functions,
2593 for which $gp itself is not a valid base register or addition operand. */
2596 mips16_gp_pseudo_reg (void)
2598 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
2602 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
2604 push_topmost_sequence ();
2606 scan = get_insns ();
2607 while (NEXT_INSN (scan) && !INSN_P (NEXT_INSN (scan)))
2608 scan = NEXT_INSN (scan);
2610 insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
2611 emit_insn_after (insn, scan);
2613 pop_topmost_sequence ();
2616 return cfun->machine->mips16_gp_pseudo_rtx;
2619 /* Return a base register that holds pic_offset_table_rtx.
2620 TEMP, if nonnull, is a scratch Pmode base register. */
2623 mips_pic_base_register (rtx temp)
2626 return pic_offset_table_rtx;
2628 if (currently_expanding_to_rtl)
2629 return mips16_gp_pseudo_reg ();
2631 if (can_create_pseudo_p ())
2632 temp = gen_reg_rtx (Pmode);
2635 /* The first post-reload split exposes all references to $gp
2636 (both uses and definitions). All references must remain
2637 explicit after that point.
2639 It is safe to introduce uses of $gp at any time, so for
2640 simplicity, we do that before the split too. */
2641 mips_emit_move (temp, pic_offset_table_rtx);
2643 emit_insn (gen_load_const_gp (temp));
2647 /* Return the RHS of a load_call<mode> insn. */
2650 mips_unspec_call (rtx reg, rtx symbol)
2654 vec = gen_rtvec (3, reg, symbol, gen_rtx_REG (SImode, GOT_VERSION_REGNUM));
2655 return gen_rtx_UNSPEC (Pmode, vec, UNSPEC_LOAD_CALL);
2658 /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol
2659 reference. Return NULL_RTX otherwise. */
2662 mips_strip_unspec_call (rtx src)
2664 if (GET_CODE (src) == UNSPEC && XINT (src, 1) == UNSPEC_LOAD_CALL)
2665 return mips_strip_unspec_address (XVECEXP (src, 0, 1));
2669 /* Create and return a GOT reference of type TYPE for address ADDR.
2670 TEMP, if nonnull, is a scratch Pmode base register. */
2673 mips_got_load (rtx temp, rtx addr, enum mips_symbol_type type)
2675 rtx base, high, lo_sum_symbol;
2677 base = mips_pic_base_register (temp);
2679 /* If we used the temporary register to load $gp, we can't use
2680 it for the high part as well. */
2681 if (temp != NULL && reg_overlap_mentioned_p (base, temp))
2684 high = mips_unspec_offset_high (temp, base, addr, type);
2685 lo_sum_symbol = mips_unspec_address (addr, type);
2687 if (type == SYMBOL_GOTOFF_CALL)
2688 return mips_unspec_call (high, lo_sum_symbol);
2690 return PMODE_INSN (gen_unspec_got, (high, lo_sum_symbol));
2693 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2694 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2695 constant in that context and can be split into high and low parts.
2696 If so, and if LOW_OUT is nonnull, emit the high part and store the
2697 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
2699 TEMP is as for mips_force_temporary and is used to load the high
2700 part into a register.
2702 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
2703 a legitimize SET_SRC for an .md pattern, otherwise the low part
2704 is guaranteed to be a legitimate address for mode MODE. */
2707 mips_split_symbol (rtx temp, rtx addr, enum machine_mode mode, rtx *low_out)
2709 enum mips_symbol_context context;
2710 enum mips_symbol_type symbol_type;
2713 context = (mode == MAX_MACHINE_MODE
2714 ? SYMBOL_CONTEXT_LEA
2715 : SYMBOL_CONTEXT_MEM);
2716 if (GET_CODE (addr) == HIGH && context == SYMBOL_CONTEXT_LEA)
2718 addr = XEXP (addr, 0);
2719 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2720 && mips_symbol_insns (symbol_type, mode) > 0
2721 && mips_split_hi_p[symbol_type])
2724 switch (symbol_type)
2726 case SYMBOL_GOT_PAGE_OFST:
2727 /* The high part of a page/ofst pair is loaded from the GOT. */
2728 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_PAGE);
2739 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2740 && mips_symbol_insns (symbol_type, mode) > 0
2741 && mips_split_p[symbol_type])
2744 switch (symbol_type)
2746 case SYMBOL_GOT_DISP:
2747 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
2748 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_DISP);
2751 case SYMBOL_GP_RELATIVE:
2752 high = mips_pic_base_register (temp);
2753 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2757 high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
2758 high = mips_force_temporary (temp, high);
2759 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2768 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2769 mips_force_temporary; it is only needed when OFFSET is not a
2773 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
2775 if (!SMALL_OPERAND (offset))
2781 /* Load the full offset into a register so that we can use
2782 an unextended instruction for the address itself. */
2783 high = GEN_INT (offset);
2788 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
2789 The addition inside the macro CONST_HIGH_PART may cause an
2790 overflow, so we need to force a sign-extension check. */
2791 high = gen_int_mode (CONST_HIGH_PART (offset), Pmode);
2792 offset = CONST_LOW_PART (offset);
2794 high = mips_force_temporary (temp, high);
2795 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
2797 return plus_constant (reg, offset);
2800 /* The __tls_get_attr symbol. */
2801 static GTY(()) rtx mips_tls_symbol;
2803 /* Return an instruction sequence that calls __tls_get_addr. SYM is
2804 the TLS symbol we are referencing and TYPE is the symbol type to use
2805 (either global dynamic or local dynamic). V0 is an RTX for the
2806 return value location. */
2809 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
2813 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
2815 if (!mips_tls_symbol)
2816 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
2818 loc = mips_unspec_address (sym, type);
2822 emit_insn (gen_rtx_SET (Pmode, a0,
2823 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
2824 insn = mips_expand_call (MIPS_CALL_NORMAL, v0, mips_tls_symbol,
2825 const0_rtx, NULL_RTX, false);
2826 RTL_CONST_CALL_P (insn) = 1;
2827 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
2828 insn = get_insns ();
2835 /* Return a pseudo register that contains the current thread pointer. */
2842 tp = gen_reg_rtx (Pmode);
2845 mips_need_mips16_rdhwr_p = true;
2846 fn = mips16_stub_function ("__mips16_rdhwr");
2847 SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_LOCAL;
2848 if (!call_insn_operand (fn, VOIDmode))
2849 fn = force_reg (Pmode, fn);
2850 emit_insn (PMODE_INSN (gen_tls_get_tp_mips16, (tp, fn)));
2853 emit_insn (PMODE_INSN (gen_tls_get_tp, (tp)));
2857 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
2858 its address. The return value will be both a valid address and a valid
2859 SET_SRC (either a REG or a LO_SUM). */
2862 mips_legitimize_tls_address (rtx loc)
2864 rtx dest, insn, v0, tp, tmp1, tmp2, eqv, offset;
2865 enum tls_model model;
2867 model = SYMBOL_REF_TLS_MODEL (loc);
2868 /* Only TARGET_ABICALLS code can have more than one module; other
2869 code must be be static and should not use a GOT. All TLS models
2870 reduce to local exec in this situation. */
2871 if (!TARGET_ABICALLS)
2872 model = TLS_MODEL_LOCAL_EXEC;
2876 case TLS_MODEL_GLOBAL_DYNAMIC:
2877 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2878 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
2879 dest = gen_reg_rtx (Pmode);
2880 emit_libcall_block (insn, dest, v0, loc);
2883 case TLS_MODEL_LOCAL_DYNAMIC:
2884 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2885 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
2886 tmp1 = gen_reg_rtx (Pmode);
2888 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2889 share the LDM result with other LD model accesses. */
2890 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2892 emit_libcall_block (insn, tmp1, v0, eqv);
2894 offset = mips_unspec_address (loc, SYMBOL_DTPREL);
2895 if (mips_split_p[SYMBOL_DTPREL])
2897 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
2898 dest = gen_rtx_LO_SUM (Pmode, tmp2, offset);
2901 dest = expand_binop (Pmode, add_optab, tmp1, offset,
2902 0, 0, OPTAB_DIRECT);
2905 case TLS_MODEL_INITIAL_EXEC:
2906 tp = mips_get_tp ();
2907 tmp1 = gen_reg_rtx (Pmode);
2908 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
2909 if (Pmode == DImode)
2910 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
2912 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
2913 dest = gen_reg_rtx (Pmode);
2914 emit_insn (gen_add3_insn (dest, tmp1, tp));
2917 case TLS_MODEL_LOCAL_EXEC:
2918 tmp1 = mips_get_tp ();
2919 offset = mips_unspec_address (loc, SYMBOL_TPREL);
2920 if (mips_split_p[SYMBOL_TPREL])
2922 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_TPREL);
2923 dest = gen_rtx_LO_SUM (Pmode, tmp2, offset);
2926 dest = expand_binop (Pmode, add_optab, tmp1, offset,
2927 0, 0, OPTAB_DIRECT);
2936 /* If X is not a valid address for mode MODE, force it into a register. */
2939 mips_force_address (rtx x, enum machine_mode mode)
2941 if (!mips_legitimate_address_p (mode, x, false))
2942 x = force_reg (Pmode, x);
2946 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
2947 be legitimized in a way that the generic machinery might not expect,
2948 return a new address, otherwise return NULL. MODE is the mode of
2949 the memory being accessed. */
2952 mips_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
2953 enum machine_mode mode)
2956 HOST_WIDE_INT offset;
2958 if (mips_tls_symbol_p (x))
2959 return mips_legitimize_tls_address (x);
2961 /* See if the address can split into a high part and a LO_SUM. */
2962 if (mips_split_symbol (NULL, x, mode, &addr))
2963 return mips_force_address (addr, mode);
2965 /* Handle BASE + OFFSET using mips_add_offset. */
2966 mips_split_plus (x, &base, &offset);
2969 if (!mips_valid_base_register_p (base, mode, false))
2970 base = copy_to_mode_reg (Pmode, base);
2971 addr = mips_add_offset (NULL, base, offset);
2972 return mips_force_address (addr, mode);
2978 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
2981 mips_move_integer (rtx temp, rtx dest, unsigned HOST_WIDE_INT value)
2983 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2984 enum machine_mode mode;
2985 unsigned int i, num_ops;
2988 mode = GET_MODE (dest);
2989 num_ops = mips_build_integer (codes, value);
2991 /* Apply each binary operation to X. Invariant: X is a legitimate
2992 source operand for a SET pattern. */
2993 x = GEN_INT (codes[0].value);
2994 for (i = 1; i < num_ops; i++)
2996 if (!can_create_pseudo_p ())
2998 emit_insn (gen_rtx_SET (VOIDmode, temp, x));
3002 x = force_reg (mode, x);
3003 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
3006 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
3009 /* Subroutine of mips_legitimize_move. Move constant SRC into register
3010 DEST given that SRC satisfies immediate_operand but doesn't satisfy
3014 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
3018 /* Split moves of big integers into smaller pieces. */
3019 if (splittable_const_int_operand (src, mode))
3021 mips_move_integer (dest, dest, INTVAL (src));
3025 /* Split moves of symbolic constants into high/low pairs. */
3026 if (mips_split_symbol (dest, src, MAX_MACHINE_MODE, &src))
3028 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
3032 /* Generate the appropriate access sequences for TLS symbols. */
3033 if (mips_tls_symbol_p (src))
3035 mips_emit_move (dest, mips_legitimize_tls_address (src));
3039 /* If we have (const (plus symbol offset)), and that expression cannot
3040 be forced into memory, load the symbol first and add in the offset.
3041 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
3042 forced into memory, as it usually produces better code. */
3043 split_const (src, &base, &offset);
3044 if (offset != const0_rtx
3045 && (targetm.cannot_force_const_mem (mode, src)
3046 || (!TARGET_MIPS16 && can_create_pseudo_p ())))
3048 base = mips_force_temporary (dest, base);
3049 mips_emit_move (dest, mips_add_offset (NULL, base, INTVAL (offset)));
3053 src = force_const_mem (mode, src);
3055 /* When using explicit relocs, constant pool references are sometimes
3056 not legitimate addresses. */
3057 mips_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0));
3058 mips_emit_move (dest, src);
3061 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
3062 sequence that is valid. */
3065 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
3067 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
3069 mips_emit_move (dest, force_reg (mode, src));
3073 /* We need to deal with constants that would be legitimate
3074 immediate_operands but aren't legitimate move_operands. */
3075 if (CONSTANT_P (src) && !move_operand (src, mode))
3077 mips_legitimize_const_move (mode, dest, src);
3078 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
3084 /* Return true if value X in context CONTEXT is a small-data address
3085 that can be rewritten as a LO_SUM. */
3088 mips_rewrite_small_data_p (rtx x, enum mips_symbol_context context)
3090 enum mips_symbol_type symbol_type;
3092 return (mips_lo_relocs[SYMBOL_GP_RELATIVE]
3093 && !mips_split_p[SYMBOL_GP_RELATIVE]
3094 && mips_symbolic_constant_p (x, context, &symbol_type)
3095 && symbol_type == SYMBOL_GP_RELATIVE);
3098 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
3099 containing MEM, or null if none. */
3102 mips_small_data_pattern_1 (rtx *loc, void *data)
3104 enum mips_symbol_context context;
3106 /* Ignore things like "g" constraints in asms. We make no particular
3107 guarantee about which symbolic constants are acceptable as asm operands
3108 versus which must be forced into a GPR. */
3109 if (GET_CODE (*loc) == LO_SUM || GET_CODE (*loc) == ASM_OPERANDS)
3114 if (for_each_rtx (&XEXP (*loc, 0), mips_small_data_pattern_1, *loc))
3119 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3120 return mips_rewrite_small_data_p (*loc, context);
3123 /* Return true if OP refers to small data symbols directly, not through
3127 mips_small_data_pattern_p (rtx op)
3129 return for_each_rtx (&op, mips_small_data_pattern_1, NULL);
3132 /* A for_each_rtx callback, used by mips_rewrite_small_data.
3133 DATA is the containing MEM, or null if none. */
3136 mips_rewrite_small_data_1 (rtx *loc, void *data)
3138 enum mips_symbol_context context;
3142 for_each_rtx (&XEXP (*loc, 0), mips_rewrite_small_data_1, *loc);
3146 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3147 if (mips_rewrite_small_data_p (*loc, context))
3148 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
3150 if (GET_CODE (*loc) == LO_SUM)
3156 /* Rewrite instruction pattern PATTERN so that it refers to small data
3157 using explicit relocations. */
3160 mips_rewrite_small_data (rtx pattern)
3162 pattern = copy_insn (pattern);
3163 for_each_rtx (&pattern, mips_rewrite_small_data_1, NULL);
3167 /* We need a lot of little routines to check the range of MIPS16 immediate
3171 m16_check_op (rtx op, int low, int high, int mask)
3173 return (CONST_INT_P (op)
3174 && IN_RANGE (INTVAL (op), low, high)
3175 && (INTVAL (op) & mask) == 0);
3179 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3181 return m16_check_op (op, 0x1, 0x8, 0);
3185 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3187 return m16_check_op (op, -0x8, 0x7, 0);
3191 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3193 return m16_check_op (op, -0x7, 0x8, 0);
3197 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3199 return m16_check_op (op, -0x10, 0xf, 0);
3203 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3205 return m16_check_op (op, -0xf, 0x10, 0);
3209 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3211 return m16_check_op (op, -0x10 << 2, 0xf << 2, 3);
3215 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3217 return m16_check_op (op, -0xf << 2, 0x10 << 2, 3);
3221 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3223 return m16_check_op (op, -0x80, 0x7f, 0);
3227 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3229 return m16_check_op (op, -0x7f, 0x80, 0);
3233 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3235 return m16_check_op (op, 0x0, 0xff, 0);
3239 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3241 return m16_check_op (op, -0xff, 0x0, 0);
3245 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3247 return m16_check_op (op, -0x1, 0xfe, 0);
3251 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3253 return m16_check_op (op, 0x0, 0xff << 2, 3);
3257 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3259 return m16_check_op (op, -0xff << 2, 0x0, 3);
3263 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3265 return m16_check_op (op, -0x80 << 3, 0x7f << 3, 7);
3269 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3271 return m16_check_op (op, -0x7f << 3, 0x80 << 3, 7);
3274 /* The cost of loading values from the constant pool. It should be
3275 larger than the cost of any constant we want to synthesize inline. */
3276 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3278 /* Return the cost of X when used as an operand to the MIPS16 instruction
3279 that implements CODE. Return -1 if there is no such instruction, or if
3280 X is not a valid immediate operand for it. */
3283 mips16_constant_cost (int code, HOST_WIDE_INT x)
3290 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3291 other shifts are extended. The shift patterns truncate the shift
3292 count to the right size, so there are no out-of-range values. */
3293 if (IN_RANGE (x, 1, 8))
3295 return COSTS_N_INSNS (1);
3298 if (IN_RANGE (x, -128, 127))
3300 if (SMALL_OPERAND (x))
3301 return COSTS_N_INSNS (1);
3305 /* Like LE, but reject the always-true case. */
3309 /* We add 1 to the immediate and use SLT. */
3312 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3315 if (IN_RANGE (x, 0, 255))
3317 if (SMALL_OPERAND_UNSIGNED (x))
3318 return COSTS_N_INSNS (1);
3323 /* Equality comparisons with 0 are cheap. */
3333 /* Return true if there is a non-MIPS16 instruction that implements CODE
3334 and if that instruction accepts X as an immediate operand. */
3337 mips_immediate_operand_p (int code, HOST_WIDE_INT x)
3344 /* All shift counts are truncated to a valid constant. */
3349 /* Likewise rotates, if the target supports rotates at all. */
3355 /* These instructions take 16-bit unsigned immediates. */
3356 return SMALL_OPERAND_UNSIGNED (x);
3361 /* These instructions take 16-bit signed immediates. */
3362 return SMALL_OPERAND (x);
3368 /* The "immediate" forms of these instructions are really
3369 implemented as comparisons with register 0. */
3374 /* Likewise, meaning that the only valid immediate operand is 1. */
3378 /* We add 1 to the immediate and use SLT. */
3379 return SMALL_OPERAND (x + 1);
3382 /* Likewise SLTU, but reject the always-true case. */
3383 return SMALL_OPERAND (x + 1) && x + 1 != 0;
3387 /* The bit position and size are immediate operands. */
3388 return ISA_HAS_EXT_INS;
3391 /* By default assume that $0 can be used for 0. */
3396 /* Return the cost of binary operation X, given that the instruction
3397 sequence for a word-sized or smaller operation has cost SINGLE_COST
3398 and that the sequence of a double-word operation has cost DOUBLE_COST.
3399 If SPEED is true, optimize for speed otherwise optimize for size. */
3402 mips_binary_cost (rtx x, int single_cost, int double_cost, bool speed)
3406 if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2)
3411 + set_src_cost (XEXP (x, 0), speed)
3412 + rtx_cost (XEXP (x, 1), GET_CODE (x), 1, speed));
3415 /* Return the cost of floating-point multiplications of mode MODE. */
3418 mips_fp_mult_cost (enum machine_mode mode)
3420 return mode == DFmode ? mips_cost->fp_mult_df : mips_cost->fp_mult_sf;
3423 /* Return the cost of floating-point divisions of mode MODE. */
3426 mips_fp_div_cost (enum machine_mode mode)
3428 return mode == DFmode ? mips_cost->fp_div_df : mips_cost->fp_div_sf;
3431 /* Return the cost of sign-extending OP to mode MODE, not including the
3432 cost of OP itself. */
3435 mips_sign_extend_cost (enum machine_mode mode, rtx op)
3438 /* Extended loads are as cheap as unextended ones. */
3441 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3442 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3445 if (ISA_HAS_SEB_SEH || GENERATE_MIPS16E)
3446 /* We can use SEB or SEH. */
3447 return COSTS_N_INSNS (1);
3449 /* We need to use a shift left and a shift right. */
3450 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3453 /* Return the cost of zero-extending OP to mode MODE, not including the
3454 cost of OP itself. */
3457 mips_zero_extend_cost (enum machine_mode mode, rtx op)
3460 /* Extended loads are as cheap as unextended ones. */
3463 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3464 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3465 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3467 if (GENERATE_MIPS16E)
3468 /* We can use ZEB or ZEH. */
3469 return COSTS_N_INSNS (1);
3472 /* We need to load 0xff or 0xffff into a register and use AND. */
3473 return COSTS_N_INSNS (GET_MODE (op) == QImode ? 2 : 3);
3475 /* We can use ANDI. */
3476 return COSTS_N_INSNS (1);
3479 /* Implement TARGET_RTX_COSTS. */
3482 mips_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
3483 int *total, bool speed)
3485 enum machine_mode mode = GET_MODE (x);
3486 bool float_mode_p = FLOAT_MODE_P (mode);
3490 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3491 appear in the instruction stream, and the cost of a comparison is
3492 really the cost of the branch or scc condition. At the time of
3493 writing, GCC only uses an explicit outer COMPARE code when optabs
3494 is testing whether a constant is expensive enough to force into a
3495 register. We want optabs to pass such constants through the MIPS
3496 expanders instead, so make all constants very cheap here. */
3497 if (outer_code == COMPARE)
3499 gcc_assert (CONSTANT_P (x));
3507 /* Treat *clear_upper32-style ANDs as having zero cost in the
3508 second operand. The cost is entirely in the first operand.
3510 ??? This is needed because we would otherwise try to CSE
3511 the constant operand. Although that's the right thing for
3512 instructions that continue to be a register operation throughout
3513 compilation, it is disastrous for instructions that could
3514 later be converted into a memory operation. */
3516 && outer_code == AND
3517 && UINTVAL (x) == 0xffffffff)
3525 cost = mips16_constant_cost (outer_code, INTVAL (x));
3534 /* When not optimizing for size, we care more about the cost
3535 of hot code, and hot code is often in a loop. If a constant
3536 operand needs to be forced into a register, we will often be
3537 able to hoist the constant load out of the loop, so the load
3538 should not contribute to the cost. */
3539 if (speed || mips_immediate_operand_p (outer_code, INTVAL (x)))
3551 if (force_to_mem_operand (x, VOIDmode))
3553 *total = COSTS_N_INSNS (1);
3556 cost = mips_const_insns (x);
3559 /* If the constant is likely to be stored in a GPR, SETs of
3560 single-insn constants are as cheap as register sets; we
3561 never want to CSE them.
3563 Don't reduce the cost of storing a floating-point zero in
3564 FPRs. If we have a zero in an FPR for other reasons, we
3565 can get better cfg-cleanup and delayed-branch results by
3566 using it consistently, rather than using $0 sometimes and
3567 an FPR at other times. Also, moves between floating-point
3568 registers are sometimes cheaper than (D)MTC1 $0. */
3570 && outer_code == SET
3571 && !(float_mode_p && TARGET_HARD_FLOAT))
3573 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3574 want to CSE the constant itself. It is usually better to
3575 have N copies of the last operation in the sequence and one
3576 shared copy of the other operations. (Note that this is
3577 not true for MIPS16 code, where the final operation in the
3578 sequence is often an extended instruction.)
3580 Also, if we have a CONST_INT, we don't know whether it is
3581 for a word or doubleword operation, so we cannot rely on
3582 the result of mips_build_integer. */
3583 else if (!TARGET_MIPS16
3584 && (outer_code == SET || mode == VOIDmode))
3586 *total = COSTS_N_INSNS (cost);
3589 /* The value will need to be fetched from the constant pool. */
3590 *total = CONSTANT_POOL_COST;
3594 /* If the address is legitimate, return the number of
3595 instructions it needs. */
3597 cost = mips_address_insns (addr, mode, true);
3600 *total = COSTS_N_INSNS (cost + 1);
3603 /* Check for a scaled indexed address. */
3604 if (mips_lwxs_address_p (addr)
3605 || mips_lx_address_p (addr, mode))
3607 *total = COSTS_N_INSNS (2);
3610 /* Otherwise use the default handling. */
3614 *total = COSTS_N_INSNS (6);
3618 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1);
3622 /* Check for a *clear_upper32 pattern and treat it like a zero
3623 extension. See the pattern's comment for details. */
3626 && CONST_INT_P (XEXP (x, 1))
3627 && UINTVAL (XEXP (x, 1)) == 0xffffffff)
3629 *total = (mips_zero_extend_cost (mode, XEXP (x, 0))
3630 + set_src_cost (XEXP (x, 0), speed));
3637 /* Double-word operations use two single-word operations. */
3638 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (2),
3647 if (CONSTANT_P (XEXP (x, 1)))
3648 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3651 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (12),
3657 *total = mips_cost->fp_add;
3659 *total = COSTS_N_INSNS (4);
3663 /* Low-part immediates need an extended MIPS16 instruction. */
3664 *total = (COSTS_N_INSNS (TARGET_MIPS16 ? 2 : 1)
3665 + set_src_cost (XEXP (x, 0), speed));
3680 /* Branch comparisons have VOIDmode, so use the first operand's
3682 mode = GET_MODE (XEXP (x, 0));
3683 if (FLOAT_MODE_P (mode))
3685 *total = mips_cost->fp_add;
3688 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3694 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3695 && TARGET_FUSED_MADD
3696 && !HONOR_NANS (mode)
3697 && !HONOR_SIGNED_ZEROS (mode))
3699 /* See if we can use NMADD or NMSUB. See mips.md for the
3700 associated patterns. */
3701 rtx op0 = XEXP (x, 0);
3702 rtx op1 = XEXP (x, 1);
3703 if (GET_CODE (op0) == MULT && GET_CODE (XEXP (op0, 0)) == NEG)
3705 *total = (mips_fp_mult_cost (mode)
3706 + set_src_cost (XEXP (XEXP (op0, 0), 0), speed)
3707 + set_src_cost (XEXP (op0, 1), speed)
3708 + set_src_cost (op1, speed));
3711 if (GET_CODE (op1) == MULT)
3713 *total = (mips_fp_mult_cost (mode)
3714 + set_src_cost (op0, speed)
3715 + set_src_cost (XEXP (op1, 0), speed)
3716 + set_src_cost (XEXP (op1, 1), speed));
3725 /* If this is part of a MADD or MSUB, treat the PLUS as
3728 && TARGET_FUSED_MADD
3729 && GET_CODE (XEXP (x, 0)) == MULT)
3732 *total = mips_cost->fp_add;
3736 /* Double-word operations require three single-word operations and
3737 an SLTU. The MIPS16 version then needs to move the result of
3738 the SLTU from $24 to a MIPS16 register. */
3739 *total = mips_binary_cost (x, COSTS_N_INSNS (1),
3740 COSTS_N_INSNS (TARGET_MIPS16 ? 5 : 4),
3746 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3747 && TARGET_FUSED_MADD
3748 && !HONOR_NANS (mode)
3749 && HONOR_SIGNED_ZEROS (mode))
3751 /* See if we can use NMADD or NMSUB. See mips.md for the
3752 associated patterns. */
3753 rtx op = XEXP (x, 0);
3754 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
3755 && GET_CODE (XEXP (op, 0)) == MULT)
3757 *total = (mips_fp_mult_cost (mode)
3758 + set_src_cost (XEXP (XEXP (op, 0), 0), speed)
3759 + set_src_cost (XEXP (XEXP (op, 0), 1), speed)
3760 + set_src_cost (XEXP (op, 1), speed));
3766 *total = mips_cost->fp_add;
3768 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1);
3773 *total = mips_fp_mult_cost (mode);
3774 else if (mode == DImode && !TARGET_64BIT)
3775 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
3776 where the mulsidi3 always includes an MFHI and an MFLO. */
3778 ? mips_cost->int_mult_si * 3 + 6
3779 : COSTS_N_INSNS (ISA_HAS_MUL3 ? 7 : 9));
3781 *total = (ISA_HAS_MUL3 ? 1 : 2);
3782 else if (mode == DImode)
3783 *total = mips_cost->int_mult_di;
3785 *total = mips_cost->int_mult_si;
3789 /* Check for a reciprocal. */
3792 && flag_unsafe_math_optimizations
3793 && XEXP (x, 0) == CONST1_RTX (mode))
3795 if (outer_code == SQRT || GET_CODE (XEXP (x, 1)) == SQRT)
3796 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
3797 division as being free. */
3798 *total = set_src_cost (XEXP (x, 1), speed);
3800 *total = (mips_fp_div_cost (mode)
3801 + set_src_cost (XEXP (x, 1), speed));
3810 *total = mips_fp_div_cost (mode);
3819 /* It is our responsibility to make division by a power of 2
3820 as cheap as 2 register additions if we want the division
3821 expanders to be used for such operations; see the setting
3822 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
3823 should always produce shorter code than using
3824 expand_sdiv2_pow2. */
3826 && CONST_INT_P (XEXP (x, 1))
3827 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
3829 *total = COSTS_N_INSNS (2) + set_src_cost (XEXP (x, 0), speed);
3832 *total = COSTS_N_INSNS (mips_idiv_insns ());
3834 else if (mode == DImode)
3835 *total = mips_cost->int_div_di;
3837 *total = mips_cost->int_div_si;
3841 *total = mips_sign_extend_cost (mode, XEXP (x, 0));
3845 if (outer_code == SET
3847 && (GET_CODE (XEXP (x, 0)) == TRUNCATE
3848 || GET_CODE (XEXP (x, 0)) == SUBREG)
3849 && GET_MODE (XEXP (x, 0)) == QImode
3850 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
3852 *total = set_src_cost (XEXP (XEXP (x, 0), 0), speed);
3855 *total = mips_zero_extend_cost (mode, XEXP (x, 0));
3859 case UNSIGNED_FLOAT:
3862 case FLOAT_TRUNCATE:
3863 *total = mips_cost->fp_add;
3871 /* Implement TARGET_ADDRESS_COST. */
3874 mips_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED)
3876 return mips_address_insns (addr, SImode, false);
3879 /* Information about a single instruction in a multi-instruction
3881 struct mips_multi_member {
3882 /* True if this is a label, false if it is code. */
3885 /* The output_asm_insn format of the instruction. */
3888 /* The operands to the instruction. */
3889 rtx operands[MAX_RECOG_OPERANDS];
3891 typedef struct mips_multi_member mips_multi_member;
3893 /* Vector definitions for the above. */
3894 DEF_VEC_O(mips_multi_member);
3895 DEF_VEC_ALLOC_O(mips_multi_member, heap);
3897 /* The instructions that make up the current multi-insn sequence. */
3898 static VEC (mips_multi_member, heap) *mips_multi_members;
3900 /* How many instructions (as opposed to labels) are in the current
3901 multi-insn sequence. */
3902 static unsigned int mips_multi_num_insns;
3904 /* Start a new multi-insn sequence. */
3907 mips_multi_start (void)
3909 VEC_truncate (mips_multi_member, mips_multi_members, 0);
3910 mips_multi_num_insns = 0;
3913 /* Add a new, uninitialized member to the current multi-insn sequence. */
3915 static struct mips_multi_member *
3916 mips_multi_add (void)
3918 return VEC_safe_push (mips_multi_member, heap, mips_multi_members, 0);
3921 /* Add a normal insn with the given asm format to the current multi-insn
3922 sequence. The other arguments are a null-terminated list of operands. */
3925 mips_multi_add_insn (const char *format, ...)
3927 struct mips_multi_member *member;
3932 member = mips_multi_add ();
3933 member->is_label_p = false;
3934 member->format = format;
3935 va_start (ap, format);
3937 while ((op = va_arg (ap, rtx)))
3938 member->operands[i++] = op;
3940 mips_multi_num_insns++;
3943 /* Add the given label definition to the current multi-insn sequence.
3944 The definition should include the colon. */
3947 mips_multi_add_label (const char *label)
3949 struct mips_multi_member *member;
3951 member = mips_multi_add ();
3952 member->is_label_p = true;
3953 member->format = label;
3956 /* Return the index of the last member of the current multi-insn sequence. */
3959 mips_multi_last_index (void)
3961 return VEC_length (mips_multi_member, mips_multi_members) - 1;
3964 /* Add a copy of an existing instruction to the current multi-insn
3965 sequence. I is the index of the instruction that should be copied. */
3968 mips_multi_copy_insn (unsigned int i)
3970 struct mips_multi_member *member;
3972 member = mips_multi_add ();
3973 memcpy (member, VEC_index (mips_multi_member, mips_multi_members, i),
3975 gcc_assert (!member->is_label_p);
3978 /* Change the operand of an existing instruction in the current
3979 multi-insn sequence. I is the index of the instruction,
3980 OP is the index of the operand, and X is the new value. */
3983 mips_multi_set_operand (unsigned int i, unsigned int op, rtx x)
3985 VEC_index (mips_multi_member, mips_multi_members, i)->operands[op] = x;
3988 /* Write out the asm code for the current multi-insn sequence. */
3991 mips_multi_write (void)
3993 struct mips_multi_member *member;
3996 FOR_EACH_VEC_ELT (mips_multi_member, mips_multi_members, i, member)
3997 if (member->is_label_p)
3998 fprintf (asm_out_file, "%s\n", member->format);
4000 output_asm_insn (member->format, member->operands);
4003 /* Return one word of double-word value OP, taking into account the fixed
4004 endianness of certain registers. HIGH_P is true to select the high part,
4005 false to select the low part. */
4008 mips_subword (rtx op, bool high_p)
4010 unsigned int byte, offset;
4011 enum machine_mode mode;
4013 mode = GET_MODE (op);
4014 if (mode == VOIDmode)
4015 mode = TARGET_64BIT ? TImode : DImode;
4017 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
4018 byte = UNITS_PER_WORD;
4022 if (FP_REG_RTX_P (op))
4024 /* Paired FPRs are always ordered little-endian. */
4025 offset = (UNITS_PER_WORD < UNITS_PER_HWFPVALUE ? high_p : byte != 0);
4026 return gen_rtx_REG (word_mode, REGNO (op) + offset);
4030 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
4032 return simplify_gen_subreg (word_mode, op, mode, byte);
4035 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
4038 mips_split_64bit_move_p (rtx dest, rtx src)
4043 /* FPR-to-FPR moves can be done in a single instruction, if they're
4045 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
4048 /* Check for floating-point loads and stores. */
4049 if (ISA_HAS_LDC1_SDC1)
4051 if (FP_REG_RTX_P (dest) && MEM_P (src))
4053 if (FP_REG_RTX_P (src) && MEM_P (dest))
4059 /* Split a doubleword move from SRC to DEST. On 32-bit targets,
4060 this function handles 64-bit moves for which mips_split_64bit_move_p
4061 holds. For 64-bit targets, this function handles 128-bit moves. */
4064 mips_split_doubleword_move (rtx dest, rtx src)
4068 if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src))
4070 if (!TARGET_64BIT && GET_MODE (dest) == DImode)
4071 emit_insn (gen_move_doubleword_fprdi (dest, src));
4072 else if (!TARGET_64BIT && GET_MODE (dest) == DFmode)
4073 emit_insn (gen_move_doubleword_fprdf (dest, src));
4074 else if (!TARGET_64BIT && GET_MODE (dest) == V2SFmode)
4075 emit_insn (gen_move_doubleword_fprv2sf (dest, src));
4076 else if (!TARGET_64BIT && GET_MODE (dest) == V2SImode)
4077 emit_insn (gen_move_doubleword_fprv2si (dest, src));
4078 else if (!TARGET_64BIT && GET_MODE (dest) == V4HImode)
4079 emit_insn (gen_move_doubleword_fprv4hi (dest, src));
4080 else if (!TARGET_64BIT && GET_MODE (dest) == V8QImode)
4081 emit_insn (gen_move_doubleword_fprv8qi (dest, src));
4082 else if (TARGET_64BIT && GET_MODE (dest) == TFmode)
4083 emit_insn (gen_move_doubleword_fprtf (dest, src));
4087 else if (REG_P (dest) && REGNO (dest) == MD_REG_FIRST)
4089 low_dest = mips_subword (dest, false);
4090 mips_emit_move (low_dest, mips_subword (src, false));
4092 emit_insn (gen_mthidi_ti (dest, mips_subword (src, true), low_dest));
4094 emit_insn (gen_mthisi_di (dest, mips_subword (src, true), low_dest));
4096 else if (REG_P (src) && REGNO (src) == MD_REG_FIRST)
4098 mips_emit_move (mips_subword (dest, false), mips_subword (src, false));
4100 emit_insn (gen_mfhidi_ti (mips_subword (dest, true), src));
4102 emit_insn (gen_mfhisi_di (mips_subword (dest, true), src));
4106 /* The operation can be split into two normal moves. Decide in
4107 which order to do them. */
4108 low_dest = mips_subword (dest, false);
4109 if (REG_P (low_dest)
4110 && reg_overlap_mentioned_p (low_dest, src))
4112 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4113 mips_emit_move (low_dest, mips_subword (src, false));
4117 mips_emit_move (low_dest, mips_subword (src, false));
4118 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4123 /* Return the appropriate instructions to move SRC into DEST. Assume
4124 that SRC is operand 1 and DEST is operand 0. */
4127 mips_output_move (rtx dest, rtx src)
4129 enum rtx_code dest_code, src_code;
4130 enum machine_mode mode;
4131 enum mips_symbol_type symbol_type;
4134 dest_code = GET_CODE (dest);
4135 src_code = GET_CODE (src);
4136 mode = GET_MODE (dest);
4137 dbl_p = (GET_MODE_SIZE (mode) == 8);
4139 if (dbl_p && mips_split_64bit_move_p (dest, src))
4142 if ((src_code == REG && GP_REG_P (REGNO (src)))
4143 || (!TARGET_MIPS16 && src == CONST0_RTX (mode)))
4145 if (dest_code == REG)
4147 if (GP_REG_P (REGNO (dest)))
4148 return "move\t%0,%z1";
4150 /* Moves to HI are handled by special .md insns. */
4151 if (REGNO (dest) == LO_REGNUM)
4154 if (DSP_ACC_REG_P (REGNO (dest)))
4156 static char retval[] = "mt__\t%z1,%q0";
4158 retval[2] = reg_names[REGNO (dest)][4];
4159 retval[3] = reg_names[REGNO (dest)][5];
4163 if (FP_REG_P (REGNO (dest)))
4164 return dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
4166 if (ALL_COP_REG_P (REGNO (dest)))
4168 static char retval[] = "dmtc_\t%z1,%0";
4170 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4171 return dbl_p ? retval : retval + 1;
4174 if (dest_code == MEM)
4175 switch (GET_MODE_SIZE (mode))
4177 case 1: return "sb\t%z1,%0";
4178 case 2: return "sh\t%z1,%0";
4179 case 4: return "sw\t%z1,%0";
4180 case 8: return "sd\t%z1,%0";
4183 if (dest_code == REG && GP_REG_P (REGNO (dest)))
4185 if (src_code == REG)
4187 /* Moves from HI are handled by special .md insns. */
4188 if (REGNO (src) == LO_REGNUM)
4190 /* When generating VR4120 or VR4130 code, we use MACC and
4191 DMACC instead of MFLO. This avoids both the normal
4192 MIPS III HI/LO hazards and the errata related to
4195 return dbl_p ? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
4199 if (DSP_ACC_REG_P (REGNO (src)))
4201 static char retval[] = "mf__\t%0,%q1";
4203 retval[2] = reg_names[REGNO (src)][4];
4204 retval[3] = reg_names[REGNO (src)][5];
4208 if (FP_REG_P (REGNO (src)))
4209 return dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
4211 if (ALL_COP_REG_P (REGNO (src)))
4213 static char retval[] = "dmfc_\t%0,%1";
4215 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4216 return dbl_p ? retval : retval + 1;
4219 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
4220 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
4223 if (src_code == MEM)
4224 switch (GET_MODE_SIZE (mode))
4226 case 1: return "lbu\t%0,%1";
4227 case 2: return "lhu\t%0,%1";
4228 case 4: return "lw\t%0,%1";
4229 case 8: return "ld\t%0,%1";
4232 if (src_code == CONST_INT)
4234 /* Don't use the X format for the operand itself, because that
4235 will give out-of-range numbers for 64-bit hosts and 32-bit
4238 return "li\t%0,%1\t\t\t# %X1";
4240 if (SMALL_OPERAND_UNSIGNED (INTVAL (src)))
4243 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src)))
4247 if (src_code == HIGH)
4248 return TARGET_MIPS16 ? "#" : "lui\t%0,%h1";
4250 if (CONST_GP_P (src))
4251 return "move\t%0,%1";
4253 if (mips_symbolic_constant_p (src, SYMBOL_CONTEXT_LEA, &symbol_type)
4254 && mips_lo_relocs[symbol_type] != 0)
4256 /* A signed 16-bit constant formed by applying a relocation
4257 operator to a symbolic address. */
4258 gcc_assert (!mips_split_p[symbol_type]);
4259 return "li\t%0,%R1";
4262 if (symbolic_operand (src, VOIDmode))
4264 gcc_assert (TARGET_MIPS16
4265 ? TARGET_MIPS16_TEXT_LOADS
4266 : !TARGET_EXPLICIT_RELOCS);
4267 return dbl_p ? "dla\t%0,%1" : "la\t%0,%1";
4270 if (src_code == REG && FP_REG_P (REGNO (src)))
4272 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4274 if (GET_MODE (dest) == V2SFmode)
4275 return "mov.ps\t%0,%1";
4277 return dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1";
4280 if (dest_code == MEM)
4281 return dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0";
4283 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4285 if (src_code == MEM)
4286 return dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1";
4288 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
4290 static char retval[] = "l_c_\t%0,%1";
4292 retval[1] = (dbl_p ? 'd' : 'w');
4293 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4296 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
4298 static char retval[] = "s_c_\t%1,%0";
4300 retval[1] = (dbl_p ? 'd' : 'w');
4301 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4307 /* Return true if CMP1 is a suitable second operand for integer ordering
4308 test CODE. See also the *sCC patterns in mips.md. */
4311 mips_int_order_operand_ok_p (enum rtx_code code, rtx cmp1)
4317 return reg_or_0_operand (cmp1, VOIDmode);
4321 return !TARGET_MIPS16 && cmp1 == const1_rtx;
4325 return arith_operand (cmp1, VOIDmode);
4328 return sle_operand (cmp1, VOIDmode);
4331 return sleu_operand (cmp1, VOIDmode);
4338 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4339 integer ordering test *CODE, or if an equivalent combination can
4340 be formed by adjusting *CODE and *CMP1. When returning true, update
4341 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4345 mips_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1,
4346 enum machine_mode mode)
4348 HOST_WIDE_INT plus_one;
4350 if (mips_int_order_operand_ok_p (*code, *cmp1))
4353 if (CONST_INT_P (*cmp1))
4357 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4358 if (INTVAL (*cmp1) < plus_one)
4361 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4367 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4371 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4382 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4383 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4384 is nonnull, it's OK to set TARGET to the inverse of the result and
4385 flip *INVERT_PTR instead. */
4388 mips_emit_int_order_test (enum rtx_code code, bool *invert_ptr,
4389 rtx target, rtx cmp0, rtx cmp1)
4391 enum machine_mode mode;
4393 /* First see if there is a MIPS instruction that can do this operation.
4394 If not, try doing the same for the inverse operation. If that also
4395 fails, force CMP1 into a register and try again. */
4396 mode = GET_MODE (cmp0);
4397 if (mips_canonicalize_int_order_test (&code, &cmp1, mode))
4398 mips_emit_binary (code, target, cmp0, cmp1);
4401 enum rtx_code inv_code = reverse_condition (code);
4402 if (!mips_canonicalize_int_order_test (&inv_code, &cmp1, mode))
4404 cmp1 = force_reg (mode, cmp1);
4405 mips_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1);
4407 else if (invert_ptr == 0)
4411 inv_target = mips_force_binary (GET_MODE (target),
4412 inv_code, cmp0, cmp1);
4413 mips_emit_binary (XOR, target, inv_target, const1_rtx);
4417 *invert_ptr = !*invert_ptr;
4418 mips_emit_binary (inv_code, target, cmp0, cmp1);
4423 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4424 The register will have the same mode as CMP0. */
4427 mips_zero_if_equal (rtx cmp0, rtx cmp1)
4429 if (cmp1 == const0_rtx)
4432 if (uns_arith_operand (cmp1, VOIDmode))
4433 return expand_binop (GET_MODE (cmp0), xor_optab,
4434 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4436 return expand_binop (GET_MODE (cmp0), sub_optab,
4437 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4440 /* Convert *CODE into a code that can be used in a floating-point
4441 scc instruction (C.cond.fmt). Return true if the values of
4442 the condition code registers will be inverted, with 0 indicating
4443 that the condition holds. */
4446 mips_reversed_fp_cond (enum rtx_code *code)
4453 *code = reverse_condition_maybe_unordered (*code);
4461 /* Convert a comparison into something that can be used in a branch or
4462 conditional move. On entry, *OP0 and *OP1 are the values being
4463 compared and *CODE is the code used to compare them.
4465 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
4466 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
4467 otherwise any standard branch condition can be used. The standard branch
4470 - EQ or NE between two registers.
4471 - any comparison between a register and zero. */
4474 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
4479 if (GET_MODE_CLASS (GET_MODE (*op0)) == MODE_INT)
4481 if (!need_eq_ne_p && *op1 == const0_rtx)
4483 else if (*code == EQ || *code == NE)
4487 *op0 = mips_zero_if_equal (cmp_op0, cmp_op1);
4491 *op1 = force_reg (GET_MODE (cmp_op0), cmp_op1);
4495 /* The comparison needs a separate scc instruction. Store the
4496 result of the scc in *OP0 and compare it against zero. */
4497 bool invert = false;
4498 *op0 = gen_reg_rtx (GET_MODE (cmp_op0));
4499 mips_emit_int_order_test (*code, &invert, *op0, cmp_op0, cmp_op1);
4500 *code = (invert ? EQ : NE);
4504 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0)))
4506 *op0 = gen_rtx_REG (CCDSPmode, CCDSP_CC_REGNUM);
4507 mips_emit_binary (*code, *op0, cmp_op0, cmp_op1);
4513 enum rtx_code cmp_code;
4515 /* Floating-point tests use a separate C.cond.fmt comparison to
4516 set a condition code register. The branch or conditional move
4517 will then compare that register against zero.
4519 Set CMP_CODE to the code of the comparison instruction and
4520 *CODE to the code that the branch or move should use. */
4522 *code = mips_reversed_fp_cond (&cmp_code) ? EQ : NE;
4524 ? gen_reg_rtx (CCmode)
4525 : gen_rtx_REG (CCmode, FPSW_REGNUM));
4527 mips_emit_binary (cmp_code, *op0, cmp_op0, cmp_op1);
4531 /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2]
4532 and OPERAND[3]. Store the result in OPERANDS[0].
4534 On 64-bit targets, the mode of the comparison and target will always be
4535 SImode, thus possibly narrower than that of the comparison's operands. */
4538 mips_expand_scc (rtx operands[])
4540 rtx target = operands[0];
4541 enum rtx_code code = GET_CODE (operands[1]);
4542 rtx op0 = operands[2];
4543 rtx op1 = operands[3];
4545 gcc_assert (GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT);
4547 if (code == EQ || code == NE)
4550 && reg_imm10_operand (op1, GET_MODE (op1)))
4551 mips_emit_binary (code, target, op0, op1);
4554 rtx zie = mips_zero_if_equal (op0, op1);
4555 mips_emit_binary (code, target, zie, const0_rtx);
4559 mips_emit_int_order_test (code, 0, target, op0, op1);
4562 /* Compare OPERANDS[1] with OPERANDS[2] using comparison code
4563 CODE and jump to OPERANDS[3] if the condition holds. */
4566 mips_expand_conditional_branch (rtx *operands)
4568 enum rtx_code code = GET_CODE (operands[0]);
4569 rtx op0 = operands[1];
4570 rtx op1 = operands[2];
4573 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
4574 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
4575 emit_jump_insn (gen_condjump (condition, operands[3]));
4580 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
4581 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
4584 mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
4585 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
4590 reversed_p = mips_reversed_fp_cond (&cond);
4591 cmp_result = gen_reg_rtx (CCV2mode);
4592 emit_insn (gen_scc_ps (cmp_result,
4593 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
4595 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
4598 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
4602 /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0]
4603 if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
4606 mips_expand_conditional_move (rtx *operands)
4609 enum rtx_code code = GET_CODE (operands[1]);
4610 rtx op0 = XEXP (operands[1], 0);
4611 rtx op1 = XEXP (operands[1], 1);
4613 mips_emit_compare (&code, &op0, &op1, true);
4614 cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
4615 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
4616 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), cond,
4617 operands[2], operands[3])));
4620 /* Perform the comparison in COMPARISON, then trap if the condition holds. */
4623 mips_expand_conditional_trap (rtx comparison)
4626 enum machine_mode mode;
4629 /* MIPS conditional trap instructions don't have GT or LE flavors,
4630 so we must swap the operands and convert to LT and GE respectively. */
4631 code = GET_CODE (comparison);
4638 code = swap_condition (code);
4639 op0 = XEXP (comparison, 1);
4640 op1 = XEXP (comparison, 0);
4644 op0 = XEXP (comparison, 0);
4645 op1 = XEXP (comparison, 1);
4649 mode = GET_MODE (XEXP (comparison, 0));
4650 op0 = force_reg (mode, op0);
4651 if (!arith_operand (op1, mode))
4652 op1 = force_reg (mode, op1);
4654 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
4655 gen_rtx_fmt_ee (code, mode, op0, op1),
4659 /* Initialize *CUM for a call to a function of type FNTYPE. */
4662 mips_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype)
4664 memset (cum, 0, sizeof (*cum));
4665 cum->prototype = (fntype && prototype_p (fntype));
4666 cum->gp_reg_found = (cum->prototype && stdarg_p (fntype));
4669 /* Fill INFO with information about a single argument. CUM is the
4670 cumulative state for earlier arguments. MODE is the mode of this
4671 argument and TYPE is its type (if known). NAMED is true if this
4672 is a named (fixed) argument rather than a variable one. */
4675 mips_get_arg_info (struct mips_arg_info *info, const CUMULATIVE_ARGS *cum,
4676 enum machine_mode mode, const_tree type, bool named)
4678 bool doubleword_aligned_p;
4679 unsigned int num_bytes, num_words, max_regs;
4681 /* Work out the size of the argument. */
4682 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
4683 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4685 /* Decide whether it should go in a floating-point register, assuming
4686 one is free. Later code checks for availability.
4688 The checks against UNITS_PER_FPVALUE handle the soft-float and
4689 single-float cases. */
4693 /* The EABI conventions have traditionally been defined in terms
4694 of TYPE_MODE, regardless of the actual type. */
4695 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
4696 || mode == V2SFmode)
4697 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4702 /* Only leading floating-point scalars are passed in
4703 floating-point registers. We also handle vector floats the same
4704 say, which is OK because they are not covered by the standard ABI. */
4705 info->fpr_p = (!cum->gp_reg_found
4706 && cum->arg_number < 2
4708 || SCALAR_FLOAT_TYPE_P (type)
4709 || VECTOR_FLOAT_TYPE_P (type))
4710 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4711 || mode == V2SFmode)
4712 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4717 /* Scalar, complex and vector floating-point types are passed in
4718 floating-point registers, as long as this is a named rather
4719 than a variable argument. */
4720 info->fpr_p = (named
4721 && (type == 0 || FLOAT_TYPE_P (type))
4722 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4723 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4724 || mode == V2SFmode)
4725 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
4727 /* ??? According to the ABI documentation, the real and imaginary
4728 parts of complex floats should be passed in individual registers.
4729 The real and imaginary parts of stack arguments are supposed
4730 to be contiguous and there should be an extra word of padding
4733 This has two problems. First, it makes it impossible to use a
4734 single "void *" va_list type, since register and stack arguments
4735 are passed differently. (At the time of writing, MIPSpro cannot
4736 handle complex float varargs correctly.) Second, it's unclear
4737 what should happen when there is only one register free.
4739 For now, we assume that named complex floats should go into FPRs
4740 if there are two FPRs free, otherwise they should be passed in the
4741 same way as a struct containing two floats. */
4743 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4744 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
4746 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
4747 info->fpr_p = false;
4757 /* See whether the argument has doubleword alignment. */
4758 doubleword_aligned_p = (mips_function_arg_boundary (mode, type)
4761 /* Set REG_OFFSET to the register count we're interested in.
4762 The EABI allocates the floating-point registers separately,
4763 but the other ABIs allocate them like integer registers. */
4764 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
4768 /* Advance to an even register if the argument is doubleword-aligned. */
4769 if (doubleword_aligned_p)
4770 info->reg_offset += info->reg_offset & 1;
4772 /* Work out the offset of a stack argument. */
4773 info->stack_offset = cum->stack_words;
4774 if (doubleword_aligned_p)
4775 info->stack_offset += info->stack_offset & 1;
4777 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
4779 /* Partition the argument between registers and stack. */
4780 info->reg_words = MIN (num_words, max_regs);
4781 info->stack_words = num_words - info->reg_words;
4784 /* INFO describes a register argument that has the normal format for the
4785 argument's mode. Return the register it uses, assuming that FPRs are
4786 available if HARD_FLOAT_P. */
4789 mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p)
4791 if (!info->fpr_p || !hard_float_p)
4792 return GP_ARG_FIRST + info->reg_offset;
4793 else if (mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info->reg_offset > 0)
4794 /* In o32, the second argument is always passed in $f14
4795 for TARGET_DOUBLE_FLOAT, regardless of whether the
4796 first argument was a word or doubleword. */
4797 return FP_ARG_FIRST + 2;
4799 return FP_ARG_FIRST + info->reg_offset;
4802 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
4805 mips_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED)
4807 return !TARGET_OLDABI;
4810 /* Implement TARGET_FUNCTION_ARG. */
4813 mips_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
4814 const_tree type, bool named)
4816 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
4817 struct mips_arg_info info;
4819 /* We will be called with a mode of VOIDmode after the last argument
4820 has been seen. Whatever we return will be passed to the call expander.
4821 If we need a MIPS16 fp_code, return a REG with the code stored as
4823 if (mode == VOIDmode)
4825 if (TARGET_MIPS16 && cum->fp_code != 0)
4826 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
4831 mips_get_arg_info (&info, cum, mode, type, named);
4833 /* Return straight away if the whole argument is passed on the stack. */
4834 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
4837 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
4838 contains a double in its entirety, then that 64-bit chunk is passed
4839 in a floating-point register. */
4841 && TARGET_HARD_FLOAT
4844 && TREE_CODE (type) == RECORD_TYPE
4845 && TYPE_SIZE_UNIT (type)
4846 && host_integerp (TYPE_SIZE_UNIT (type), 1))
4850 /* First check to see if there is any such field. */
4851 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
4852 if (TREE_CODE (field) == FIELD_DECL
4853 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
4854 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
4855 && host_integerp (bit_position (field), 0)
4856 && int_bit_position (field) % BITS_PER_WORD == 0)
4861 /* Now handle the special case by returning a PARALLEL
4862 indicating where each 64-bit chunk goes. INFO.REG_WORDS
4863 chunks are passed in registers. */
4865 HOST_WIDE_INT bitpos;
4868 /* assign_parms checks the mode of ENTRY_PARM, so we must
4869 use the actual mode here. */
4870 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
4873 field = TYPE_FIELDS (type);
4874 for (i = 0; i < info.reg_words; i++)
4878 for (; field; field = DECL_CHAIN (field))
4879 if (TREE_CODE (field) == FIELD_DECL
4880 && int_bit_position (field) >= bitpos)
4884 && int_bit_position (field) == bitpos
4885 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
4886 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
4887 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
4889 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
4892 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4893 GEN_INT (bitpos / BITS_PER_UNIT));
4895 bitpos += BITS_PER_WORD;
4901 /* Handle the n32/n64 conventions for passing complex floating-point
4902 arguments in FPR pairs. The real part goes in the lower register
4903 and the imaginary part goes in the upper register. */
4906 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4909 enum machine_mode inner;
4912 inner = GET_MODE_INNER (mode);
4913 regno = FP_ARG_FIRST + info.reg_offset;
4914 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
4916 /* Real part in registers, imaginary part on stack. */
4917 gcc_assert (info.stack_words == info.reg_words);
4918 return gen_rtx_REG (inner, regno);
4922 gcc_assert (info.stack_words == 0);
4923 real = gen_rtx_EXPR_LIST (VOIDmode,
4924 gen_rtx_REG (inner, regno),
4926 imag = gen_rtx_EXPR_LIST (VOIDmode,
4928 regno + info.reg_words / 2),
4929 GEN_INT (GET_MODE_SIZE (inner)));
4930 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
4934 return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT));
4937 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
4940 mips_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
4941 const_tree type, bool named)
4943 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
4944 struct mips_arg_info info;
4946 mips_get_arg_info (&info, cum, mode, type, named);
4949 cum->gp_reg_found = true;
4951 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
4952 an explanation of what this code does. It assumes that we're using
4953 either the o32 or the o64 ABI, both of which pass at most 2 arguments
4955 if (cum->arg_number < 2 && info.fpr_p)
4956 cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2);
4958 /* Advance the register count. This has the effect of setting
4959 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
4960 argument required us to skip the final GPR and pass the whole
4961 argument on the stack. */
4962 if (mips_abi != ABI_EABI || !info.fpr_p)
4963 cum->num_gprs = info.reg_offset + info.reg_words;
4964 else if (info.reg_words > 0)
4965 cum->num_fprs += MAX_FPRS_PER_FMT;
4967 /* Advance the stack word count. */
4968 if (info.stack_words > 0)
4969 cum->stack_words = info.stack_offset + info.stack_words;
4974 /* Implement TARGET_ARG_PARTIAL_BYTES. */
4977 mips_arg_partial_bytes (cumulative_args_t cum,
4978 enum machine_mode mode, tree type, bool named)
4980 struct mips_arg_info info;
4982 mips_get_arg_info (&info, get_cumulative_args (cum), mode, type, named);
4983 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
4986 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
4987 least PARM_BOUNDARY bits of alignment, but will be given anything up
4988 to STACK_BOUNDARY bits if the type requires it. */
4991 mips_function_arg_boundary (enum machine_mode mode, const_tree type)
4993 unsigned int alignment;
4995 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
4996 if (alignment < PARM_BOUNDARY)
4997 alignment = PARM_BOUNDARY;
4998 if (alignment > STACK_BOUNDARY)
4999 alignment = STACK_BOUNDARY;
5003 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
5004 upward rather than downward. In other words, return true if the
5005 first byte of the stack slot has useful data, false if the last
5009 mips_pad_arg_upward (enum machine_mode mode, const_tree type)
5011 /* On little-endian targets, the first byte of every stack argument
5012 is passed in the first byte of the stack slot. */
5013 if (!BYTES_BIG_ENDIAN)
5016 /* Otherwise, integral types are padded downward: the last byte of a
5017 stack argument is passed in the last byte of the stack slot. */
5019 ? (INTEGRAL_TYPE_P (type)
5020 || POINTER_TYPE_P (type)
5021 || FIXED_POINT_TYPE_P (type))
5022 : (SCALAR_INT_MODE_P (mode)
5023 || ALL_SCALAR_FIXED_POINT_MODE_P (mode)))
5026 /* Big-endian o64 pads floating-point arguments downward. */
5027 if (mips_abi == ABI_O64)
5028 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
5031 /* Other types are padded upward for o32, o64, n32 and n64. */
5032 if (mips_abi != ABI_EABI)
5035 /* Arguments smaller than a stack slot are padded downward. */
5036 if (mode != BLKmode)
5037 return GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY;
5039 return int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT);
5042 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
5043 if the least significant byte of the register has useful data. Return
5044 the opposite if the most significant byte does. */
5047 mips_pad_reg_upward (enum machine_mode mode, tree type)
5049 /* No shifting is required for floating-point arguments. */
5050 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
5051 return !BYTES_BIG_ENDIAN;
5053 /* Otherwise, apply the same padding to register arguments as we do
5054 to stack arguments. */
5055 return mips_pad_arg_upward (mode, type);
5058 /* Return nonzero when an argument must be passed by reference. */
5061 mips_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
5062 enum machine_mode mode, const_tree type,
5063 bool named ATTRIBUTE_UNUSED)
5065 if (mips_abi == ABI_EABI)
5069 /* ??? How should SCmode be handled? */
5070 if (mode == DImode || mode == DFmode
5071 || mode == DQmode || mode == UDQmode
5072 || mode == DAmode || mode == UDAmode)
5075 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
5076 return size == -1 || size > UNITS_PER_WORD;
5080 /* If we have a variable-sized parameter, we have no choice. */
5081 return targetm.calls.must_pass_in_stack (mode, type);
5085 /* Implement TARGET_CALLEE_COPIES. */
5088 mips_callee_copies (cumulative_args_t cum ATTRIBUTE_UNUSED,
5089 enum machine_mode mode ATTRIBUTE_UNUSED,
5090 const_tree type ATTRIBUTE_UNUSED, bool named)
5092 return mips_abi == ABI_EABI && named;
5095 /* See whether VALTYPE is a record whose fields should be returned in
5096 floating-point registers. If so, return the number of fields and
5097 list them in FIELDS (which should have two elements). Return 0
5100 For n32 & n64, a structure with one or two fields is returned in
5101 floating-point registers as long as every field has a floating-point
5105 mips_fpr_return_fields (const_tree valtype, tree *fields)
5113 if (TREE_CODE (valtype) != RECORD_TYPE)
5117 for (field = TYPE_FIELDS (valtype); field != 0; field = DECL_CHAIN (field))
5119 if (TREE_CODE (field) != FIELD_DECL)
5122 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)))
5128 fields[i++] = field;
5133 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
5134 a value in the most significant part of $2/$3 if:
5136 - the target is big-endian;
5138 - the value has a structure or union type (we generalize this to
5139 cover aggregates from other languages too); and
5141 - the structure is not returned in floating-point registers. */
5144 mips_return_in_msb (const_tree valtype)
5148 return (TARGET_NEWABI
5149 && TARGET_BIG_ENDIAN
5150 && AGGREGATE_TYPE_P (valtype)
5151 && mips_fpr_return_fields (valtype, fields) == 0);
5154 /* Return true if the function return value MODE will get returned in a
5155 floating-point register. */
5158 mips_return_mode_in_fpr_p (enum machine_mode mode)
5160 return ((GET_MODE_CLASS (mode) == MODE_FLOAT
5162 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5163 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE);
5166 /* Return the representation of an FPR return register when the
5167 value being returned in FP_RETURN has mode VALUE_MODE and the
5168 return type itself has mode TYPE_MODE. On NewABI targets,
5169 the two modes may be different for structures like:
5171 struct __attribute__((packed)) foo { float f; }
5173 where we return the SFmode value of "f" in FP_RETURN, but where
5174 the structure itself has mode BLKmode. */
5177 mips_return_fpr_single (enum machine_mode type_mode,
5178 enum machine_mode value_mode)
5182 x = gen_rtx_REG (value_mode, FP_RETURN);
5183 if (type_mode != value_mode)
5185 x = gen_rtx_EXPR_LIST (VOIDmode, x, const0_rtx);
5186 x = gen_rtx_PARALLEL (type_mode, gen_rtvec (1, x));
5191 /* Return a composite value in a pair of floating-point registers.
5192 MODE1 and OFFSET1 are the mode and byte offset for the first value,
5193 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
5196 For n32 & n64, $f0 always holds the first value and $f2 the second.
5197 Otherwise the values are packed together as closely as possible. */
5200 mips_return_fpr_pair (enum machine_mode mode,
5201 enum machine_mode mode1, HOST_WIDE_INT offset1,
5202 enum machine_mode mode2, HOST_WIDE_INT offset2)
5206 inc = (TARGET_NEWABI ? 2 : MAX_FPRS_PER_FMT);
5207 return gen_rtx_PARALLEL
5210 gen_rtx_EXPR_LIST (VOIDmode,
5211 gen_rtx_REG (mode1, FP_RETURN),
5213 gen_rtx_EXPR_LIST (VOIDmode,
5214 gen_rtx_REG (mode2, FP_RETURN + inc),
5215 GEN_INT (offset2))));
5219 /* Implement TARGET_FUNCTION_VALUE and TARGET_LIBCALL_VALUE.
5220 For normal calls, VALTYPE is the return type and MODE is VOIDmode.
5221 For libcalls, VALTYPE is null and MODE is the mode of the return value. */
5224 mips_function_value_1 (const_tree valtype, const_tree fn_decl_or_type,
5225 enum machine_mode mode)
5233 if (fn_decl_or_type && DECL_P (fn_decl_or_type))
5234 func = fn_decl_or_type;
5238 mode = TYPE_MODE (valtype);
5239 unsigned_p = TYPE_UNSIGNED (valtype);
5241 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
5242 return values, promote the mode here too. */
5243 mode = promote_function_mode (valtype, mode, &unsigned_p, func, 1);
5245 /* Handle structures whose fields are returned in $f0/$f2. */
5246 switch (mips_fpr_return_fields (valtype, fields))
5249 return mips_return_fpr_single (mode,
5250 TYPE_MODE (TREE_TYPE (fields[0])));
5253 return mips_return_fpr_pair (mode,
5254 TYPE_MODE (TREE_TYPE (fields[0])),
5255 int_byte_position (fields[0]),
5256 TYPE_MODE (TREE_TYPE (fields[1])),
5257 int_byte_position (fields[1]));
5260 /* If a value is passed in the most significant part of a register, see
5261 whether we have to round the mode up to a whole number of words. */
5262 if (mips_return_in_msb (valtype))
5264 HOST_WIDE_INT size = int_size_in_bytes (valtype);
5265 if (size % UNITS_PER_WORD != 0)
5267 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
5268 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
5272 /* For EABI, the class of return register depends entirely on MODE.
5273 For example, "struct { some_type x; }" and "union { some_type x; }"
5274 are returned in the same way as a bare "some_type" would be.
5275 Other ABIs only use FPRs for scalar, complex or vector types. */
5276 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
5277 return gen_rtx_REG (mode, GP_RETURN);
5282 /* Handle long doubles for n32 & n64. */
5284 return mips_return_fpr_pair (mode,
5286 DImode, GET_MODE_SIZE (mode) / 2);
5288 if (mips_return_mode_in_fpr_p (mode))
5290 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5291 return mips_return_fpr_pair (mode,
5292 GET_MODE_INNER (mode), 0,
5293 GET_MODE_INNER (mode),
5294 GET_MODE_SIZE (mode) / 2);
5296 return gen_rtx_REG (mode, FP_RETURN);
5300 return gen_rtx_REG (mode, GP_RETURN);
5303 /* Implement TARGET_FUNCTION_VALUE. */
5306 mips_function_value (const_tree valtype, const_tree fn_decl_or_type,
5307 bool outgoing ATTRIBUTE_UNUSED)
5309 return mips_function_value_1 (valtype, fn_decl_or_type, VOIDmode);
5312 /* Implement TARGET_LIBCALL_VALUE. */
5315 mips_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
5317 return mips_function_value_1 (NULL_TREE, NULL_TREE, mode);
5320 /* Implement TARGET_FUNCTION_VALUE_REGNO_P.
5322 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
5323 Currently, R2 and F0 are only implemented here (C has no complex type). */
5326 mips_function_value_regno_p (const unsigned int regno)
5328 if (regno == GP_RETURN
5329 || regno == FP_RETURN
5330 || (LONG_DOUBLE_TYPE_SIZE == 128
5331 && FP_RETURN != GP_RETURN
5332 && regno == FP_RETURN + 2))
5338 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
5339 all BLKmode objects are returned in memory. Under the n32, n64
5340 and embedded ABIs, small structures are returned in a register.
5341 Objects with varying size must still be returned in memory, of
5345 mips_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
5347 return (TARGET_OLDABI
5348 ? TYPE_MODE (type) == BLKmode
5349 : !IN_RANGE (int_size_in_bytes (type), 0, 2 * UNITS_PER_WORD));
5352 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
5355 mips_setup_incoming_varargs (cumulative_args_t cum, enum machine_mode mode,
5356 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5359 CUMULATIVE_ARGS local_cum;
5360 int gp_saved, fp_saved;
5362 /* The caller has advanced CUM up to, but not beyond, the last named
5363 argument. Advance a local copy of CUM past the last "real" named
5364 argument, to find out how many registers are left over. */
5365 local_cum = *get_cumulative_args (cum);
5366 mips_function_arg_advance (pack_cumulative_args (&local_cum), mode, type,
5369 /* Found out how many registers we need to save. */
5370 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
5371 fp_saved = (EABI_FLOAT_VARARGS_P
5372 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
5381 ptr = plus_constant (virtual_incoming_args_rtx,
5382 REG_PARM_STACK_SPACE (cfun->decl)
5383 - gp_saved * UNITS_PER_WORD);
5384 mem = gen_frame_mem (BLKmode, ptr);
5385 set_mem_alias_set (mem, get_varargs_alias_set ());
5387 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
5392 /* We can't use move_block_from_reg, because it will use
5394 enum machine_mode mode;
5397 /* Set OFF to the offset from virtual_incoming_args_rtx of
5398 the first float register. The FP save area lies below
5399 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
5400 off = (-gp_saved * UNITS_PER_WORD) & -UNITS_PER_FPVALUE;
5401 off -= fp_saved * UNITS_PER_FPREG;
5403 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
5405 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS;
5406 i += MAX_FPRS_PER_FMT)
5410 ptr = plus_constant (virtual_incoming_args_rtx, off);
5411 mem = gen_frame_mem (mode, ptr);
5412 set_mem_alias_set (mem, get_varargs_alias_set ());
5413 mips_emit_move (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
5414 off += UNITS_PER_HWFPVALUE;
5418 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
5419 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
5420 + fp_saved * UNITS_PER_FPREG);
5423 /* Implement TARGET_BUILTIN_VA_LIST. */
5426 mips_build_builtin_va_list (void)
5428 if (EABI_FLOAT_VARARGS_P)
5430 /* We keep 3 pointers, and two offsets.
5432 Two pointers are to the overflow area, which starts at the CFA.
5433 One of these is constant, for addressing into the GPR save area
5434 below it. The other is advanced up the stack through the
5437 The third pointer is to the bottom of the GPR save area.
5438 Since the FPR save area is just below it, we can address
5439 FPR slots off this pointer.
5441 We also keep two one-byte offsets, which are to be subtracted
5442 from the constant pointers to yield addresses in the GPR and
5443 FPR save areas. These are downcounted as float or non-float
5444 arguments are used, and when they get to zero, the argument
5445 must be obtained from the overflow region. */
5446 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
5449 record = lang_hooks.types.make_type (RECORD_TYPE);
5451 f_ovfl = build_decl (BUILTINS_LOCATION,
5452 FIELD_DECL, get_identifier ("__overflow_argptr"),
5454 f_gtop = build_decl (BUILTINS_LOCATION,
5455 FIELD_DECL, get_identifier ("__gpr_top"),
5457 f_ftop = build_decl (BUILTINS_LOCATION,
5458 FIELD_DECL, get_identifier ("__fpr_top"),
5460 f_goff = build_decl (BUILTINS_LOCATION,
5461 FIELD_DECL, get_identifier ("__gpr_offset"),
5462 unsigned_char_type_node);
5463 f_foff = build_decl (BUILTINS_LOCATION,
5464 FIELD_DECL, get_identifier ("__fpr_offset"),
5465 unsigned_char_type_node);
5466 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
5467 warn on every user file. */
5468 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
5469 array = build_array_type (unsigned_char_type_node,
5470 build_index_type (index));
5471 f_res = build_decl (BUILTINS_LOCATION,
5472 FIELD_DECL, get_identifier ("__reserved"), array);
5474 DECL_FIELD_CONTEXT (f_ovfl) = record;
5475 DECL_FIELD_CONTEXT (f_gtop) = record;
5476 DECL_FIELD_CONTEXT (f_ftop) = record;
5477 DECL_FIELD_CONTEXT (f_goff) = record;
5478 DECL_FIELD_CONTEXT (f_foff) = record;
5479 DECL_FIELD_CONTEXT (f_res) = record;
5481 TYPE_FIELDS (record) = f_ovfl;
5482 DECL_CHAIN (f_ovfl) = f_gtop;
5483 DECL_CHAIN (f_gtop) = f_ftop;
5484 DECL_CHAIN (f_ftop) = f_goff;
5485 DECL_CHAIN (f_goff) = f_foff;
5486 DECL_CHAIN (f_foff) = f_res;
5488 layout_type (record);
5491 else if (TARGET_IRIX6)
5492 /* On IRIX 6, this type is 'char *'. */
5493 return build_pointer_type (char_type_node);
5495 /* Otherwise, we use 'void *'. */
5496 return ptr_type_node;
5499 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
5502 mips_va_start (tree valist, rtx nextarg)
5504 if (EABI_FLOAT_VARARGS_P)
5506 const CUMULATIVE_ARGS *cum;
5507 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5508 tree ovfl, gtop, ftop, goff, foff;
5510 int gpr_save_area_size;
5511 int fpr_save_area_size;
5514 cum = &crtl->args.info;
5516 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
5518 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
5520 f_ovfl = TYPE_FIELDS (va_list_type_node);
5521 f_gtop = DECL_CHAIN (f_ovfl);
5522 f_ftop = DECL_CHAIN (f_gtop);
5523 f_goff = DECL_CHAIN (f_ftop);
5524 f_foff = DECL_CHAIN (f_goff);
5526 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5528 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
5530 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
5532 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
5534 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
5537 /* Emit code to initialize OVFL, which points to the next varargs
5538 stack argument. CUM->STACK_WORDS gives the number of stack
5539 words used by named arguments. */
5540 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
5541 if (cum->stack_words > 0)
5542 t = fold_build_pointer_plus_hwi (t, cum->stack_words * UNITS_PER_WORD);
5543 t = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
5544 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5546 /* Emit code to initialize GTOP, the top of the GPR save area. */
5547 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
5548 t = build2 (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
5549 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5551 /* Emit code to initialize FTOP, the top of the FPR save area.
5552 This address is gpr_save_area_bytes below GTOP, rounded
5553 down to the next fp-aligned boundary. */
5554 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
5555 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
5556 fpr_offset &= -UNITS_PER_FPVALUE;
5558 t = fold_build_pointer_plus_hwi (t, -fpr_offset);
5559 t = build2 (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
5560 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5562 /* Emit code to initialize GOFF, the offset from GTOP of the
5563 next GPR argument. */
5564 t = build2 (MODIFY_EXPR, TREE_TYPE (goff), goff,
5565 build_int_cst (TREE_TYPE (goff), gpr_save_area_size));
5566 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5568 /* Likewise emit code to initialize FOFF, the offset from FTOP
5569 of the next FPR argument. */
5570 t = build2 (MODIFY_EXPR, TREE_TYPE (foff), foff,
5571 build_int_cst (TREE_TYPE (foff), fpr_save_area_size));
5572 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5576 nextarg = plus_constant (nextarg, -cfun->machine->varargs_size);
5577 std_expand_builtin_va_start (valist, nextarg);
5581 /* Like std_gimplify_va_arg_expr, but apply alignment to zero-sized
5585 mips_std_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
5588 tree addr, t, type_size, rounded_size, valist_tmp;
5589 unsigned HOST_WIDE_INT align, boundary;
5592 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, false);
5594 type = build_pointer_type (type);
5596 align = PARM_BOUNDARY / BITS_PER_UNIT;
5597 boundary = targetm.calls.function_arg_boundary (TYPE_MODE (type), type);
5599 /* When we align parameter on stack for caller, if the parameter
5600 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
5601 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
5602 here with caller. */
5603 if (boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
5604 boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
5606 boundary /= BITS_PER_UNIT;
5608 /* Hoist the valist value into a temporary for the moment. */
5609 valist_tmp = get_initialized_tmp_var (valist, pre_p, NULL);
5611 /* va_list pointer is aligned to PARM_BOUNDARY. If argument actually
5612 requires greater alignment, we must perform dynamic alignment. */
5613 if (boundary > align)
5615 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
5616 fold_build_pointer_plus_hwi (valist_tmp, boundary - 1));
5617 gimplify_and_add (t, pre_p);
5619 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
5620 fold_build2 (BIT_AND_EXPR, TREE_TYPE (valist),
5622 build_int_cst (TREE_TYPE (valist), -boundary)));
5623 gimplify_and_add (t, pre_p);
5628 /* If the actual alignment is less than the alignment of the type,
5629 adjust the type accordingly so that we don't assume strict alignment
5630 when dereferencing the pointer. */
5631 boundary *= BITS_PER_UNIT;
5632 if (boundary < TYPE_ALIGN (type))
5634 type = build_variant_type_copy (type);
5635 TYPE_ALIGN (type) = boundary;
5638 /* Compute the rounded size of the type. */
5639 type_size = size_in_bytes (type);
5640 rounded_size = round_up (type_size, align);
5642 /* Reduce rounded_size so it's sharable with the postqueue. */
5643 gimplify_expr (&rounded_size, pre_p, post_p, is_gimple_val, fb_rvalue);
5647 if (PAD_VARARGS_DOWN && !integer_zerop (rounded_size))
5649 /* Small args are padded downward. */
5650 t = fold_build2_loc (input_location, GT_EXPR, sizetype,
5651 rounded_size, size_int (align));
5652 t = fold_build3 (COND_EXPR, sizetype, t, size_zero_node,
5653 size_binop (MINUS_EXPR, rounded_size, type_size));
5654 addr = fold_build_pointer_plus (addr, t);
5657 /* Compute new value for AP. */
5658 t = fold_build_pointer_plus (valist_tmp, rounded_size);
5659 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
5660 gimplify_and_add (t, pre_p);
5662 addr = fold_convert (build_pointer_type (type), addr);
5665 addr = build_va_arg_indirect_ref (addr);
5667 return build_va_arg_indirect_ref (addr);
5670 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
5673 mips_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
5679 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
5681 type = build_pointer_type (type);
5683 if (!EABI_FLOAT_VARARGS_P)
5684 addr = mips_std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5687 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5688 tree ovfl, top, off, align;
5689 HOST_WIDE_INT size, rsize, osize;
5692 f_ovfl = TYPE_FIELDS (va_list_type_node);
5693 f_gtop = DECL_CHAIN (f_ovfl);
5694 f_ftop = DECL_CHAIN (f_gtop);
5695 f_goff = DECL_CHAIN (f_ftop);
5696 f_foff = DECL_CHAIN (f_goff);
5700 TOP be the top of the GPR or FPR save area;
5701 OFF be the offset from TOP of the next register;
5702 ADDR_RTX be the address of the argument;
5703 SIZE be the number of bytes in the argument type;
5704 RSIZE be the number of bytes used to store the argument
5705 when it's in the register save area; and
5706 OSIZE be the number of bytes used to store it when it's
5707 in the stack overflow area.
5709 The code we want is:
5711 1: off &= -rsize; // round down
5714 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
5719 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
5720 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
5724 [1] and [9] can sometimes be optimized away. */
5726 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5728 size = int_size_in_bytes (type);
5730 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
5731 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
5733 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop),
5734 unshare_expr (valist), f_ftop, NULL_TREE);
5735 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff),
5736 unshare_expr (valist), f_foff, NULL_TREE);
5738 /* When va_start saves FPR arguments to the stack, each slot
5739 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
5740 argument's precision. */
5741 rsize = UNITS_PER_HWFPVALUE;
5743 /* Overflow arguments are padded to UNITS_PER_WORD bytes
5744 (= PARM_BOUNDARY bits). This can be different from RSIZE
5747 (1) On 32-bit targets when TYPE is a structure such as:
5749 struct s { float f; };
5751 Such structures are passed in paired FPRs, so RSIZE
5752 will be 8 bytes. However, the structure only takes
5753 up 4 bytes of memory, so OSIZE will only be 4.
5755 (2) In combinations such as -mgp64 -msingle-float
5756 -fshort-double. Doubles passed in registers will then take
5757 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
5758 stack take up UNITS_PER_WORD bytes. */
5759 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
5763 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop),
5764 unshare_expr (valist), f_gtop, NULL_TREE);
5765 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff),
5766 unshare_expr (valist), f_goff, NULL_TREE);
5767 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
5768 if (rsize > UNITS_PER_WORD)
5770 /* [1] Emit code for: off &= -rsize. */
5771 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), unshare_expr (off),
5772 build_int_cst (TREE_TYPE (off), -rsize));
5773 gimplify_assign (unshare_expr (off), t, pre_p);
5778 /* [2] Emit code to branch if off == 0. */
5779 t = build2 (NE_EXPR, boolean_type_node, unshare_expr (off),
5780 build_int_cst (TREE_TYPE (off), 0));
5781 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
5783 /* [5] Emit code for: off -= rsize. We do this as a form of
5784 post-decrement not available to C. */
5785 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
5786 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
5788 /* [4] Emit code for:
5789 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
5790 t = fold_convert (sizetype, t);
5791 t = fold_build1 (NEGATE_EXPR, sizetype, t);
5792 t = fold_build_pointer_plus (top, t);
5793 if (BYTES_BIG_ENDIAN && rsize > size)
5794 t = fold_build_pointer_plus_hwi (t, rsize - size);
5795 COND_EXPR_THEN (addr) = t;
5797 if (osize > UNITS_PER_WORD)
5799 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
5800 t = fold_build_pointer_plus_hwi (unshare_expr (ovfl), osize - 1);
5801 u = build_int_cst (TREE_TYPE (t), -osize);
5802 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t, u);
5803 align = build2 (MODIFY_EXPR, TREE_TYPE (ovfl),
5804 unshare_expr (ovfl), t);
5809 /* [10, 11] Emit code for:
5810 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
5812 u = fold_convert (TREE_TYPE (ovfl), build_int_cst (NULL_TREE, osize));
5813 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
5814 if (BYTES_BIG_ENDIAN && osize > size)
5815 t = fold_build_pointer_plus_hwi (t, osize - size);
5817 /* String [9] and [10, 11] together. */
5819 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
5820 COND_EXPR_ELSE (addr) = t;
5822 addr = fold_convert (build_pointer_type (type), addr);
5823 addr = build_va_arg_indirect_ref (addr);
5827 addr = build_va_arg_indirect_ref (addr);
5832 /* Declare a unique, locally-binding function called NAME, then start
5836 mips_start_unique_function (const char *name)
5840 decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
5841 get_identifier (name),
5842 build_function_type_list (void_type_node, NULL_TREE));
5843 DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
5844 NULL_TREE, void_type_node);
5845 TREE_PUBLIC (decl) = 1;
5846 TREE_STATIC (decl) = 1;
5848 DECL_COMDAT_GROUP (decl) = DECL_ASSEMBLER_NAME (decl);
5850 targetm.asm_out.unique_section (decl, 0);
5851 switch_to_section (get_named_section (decl, NULL, 0));
5853 targetm.asm_out.globalize_label (asm_out_file, name);
5854 fputs ("\t.hidden\t", asm_out_file);
5855 assemble_name (asm_out_file, name);
5856 putc ('\n', asm_out_file);
5859 /* Start a definition of function NAME. MIPS16_P indicates whether the
5860 function contains MIPS16 code. */
5863 mips_start_function_definition (const char *name, bool mips16_p)
5866 fprintf (asm_out_file, "\t.set\tmips16\n");
5868 fprintf (asm_out_file, "\t.set\tnomips16\n");
5870 if (!flag_inhibit_size_directive)
5872 fputs ("\t.ent\t", asm_out_file);
5873 assemble_name (asm_out_file, name);
5874 fputs ("\n", asm_out_file);
5877 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, name, "function");
5879 /* Start the definition proper. */
5880 assemble_name (asm_out_file, name);
5881 fputs (":\n", asm_out_file);
5884 /* End a function definition started by mips_start_function_definition. */
5887 mips_end_function_definition (const char *name)
5889 if (!flag_inhibit_size_directive)
5891 fputs ("\t.end\t", asm_out_file);
5892 assemble_name (asm_out_file, name);
5893 fputs ("\n", asm_out_file);
5897 /* Output a definition of the __mips16_rdhwr function. */
5900 mips_output_mips16_rdhwr (void)
5904 name = "__mips16_rdhwr";
5905 mips_start_unique_function (name);
5906 mips_start_function_definition (name, false);
5907 fprintf (asm_out_file,
5909 "\t.set\tmips32r2\n"
5910 "\t.set\tnoreorder\n"
5914 mips_end_function_definition (name);
5917 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
5920 mips_ok_for_lazy_binding_p (rtx x)
5922 return (TARGET_USE_GOT
5923 && GET_CODE (x) == SYMBOL_REF
5924 && !SYMBOL_REF_BIND_NOW_P (x)
5925 && !mips_symbol_binds_local_p (x));
5928 /* Load function address ADDR into register DEST. TYPE is as for
5929 mips_expand_call. Return true if we used an explicit lazy-binding
5933 mips_load_call_address (enum mips_call_type type, rtx dest, rtx addr)
5935 /* If we're generating PIC, and this call is to a global function,
5936 try to allow its address to be resolved lazily. This isn't
5937 possible for sibcalls when $gp is call-saved because the value
5938 of $gp on entry to the stub would be our caller's gp, not ours. */
5939 if (TARGET_EXPLICIT_RELOCS
5940 && !(type == MIPS_CALL_SIBCALL && TARGET_CALL_SAVED_GP)
5941 && mips_ok_for_lazy_binding_p (addr))
5943 addr = mips_got_load (dest, addr, SYMBOL_GOTOFF_CALL);
5944 emit_insn (gen_rtx_SET (VOIDmode, dest, addr));
5949 mips_emit_move (dest, addr);
5954 /* Each locally-defined hard-float MIPS16 function has a local symbol
5955 associated with it. This hash table maps the function symbol (FUNC)
5956 to the local symbol (LOCAL). */
5957 struct GTY(()) mips16_local_alias {
5961 static GTY ((param_is (struct mips16_local_alias))) htab_t mips16_local_aliases;
5963 /* Hash table callbacks for mips16_local_aliases. */
5966 mips16_local_aliases_hash (const void *entry)
5968 const struct mips16_local_alias *alias;
5970 alias = (const struct mips16_local_alias *) entry;
5971 return htab_hash_string (XSTR (alias->func, 0));
5975 mips16_local_aliases_eq (const void *entry1, const void *entry2)
5977 const struct mips16_local_alias *alias1, *alias2;
5979 alias1 = (const struct mips16_local_alias *) entry1;
5980 alias2 = (const struct mips16_local_alias *) entry2;
5981 return rtx_equal_p (alias1->func, alias2->func);
5984 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
5985 Return a local alias for it, creating a new one if necessary. */
5988 mips16_local_alias (rtx func)
5990 struct mips16_local_alias *alias, tmp_alias;
5993 /* Create the hash table if this is the first call. */
5994 if (mips16_local_aliases == NULL)
5995 mips16_local_aliases = htab_create_ggc (37, mips16_local_aliases_hash,
5996 mips16_local_aliases_eq, NULL);
5998 /* Look up the function symbol, creating a new entry if need be. */
5999 tmp_alias.func = func;
6000 slot = htab_find_slot (mips16_local_aliases, &tmp_alias, INSERT);
6001 gcc_assert (slot != NULL);
6003 alias = (struct mips16_local_alias *) *slot;
6006 const char *func_name, *local_name;
6009 /* Create a new SYMBOL_REF for the local symbol. The choice of
6010 __fn_local_* is based on the __fn_stub_* names that we've
6011 traditionally used for the non-MIPS16 stub. */
6012 func_name = targetm.strip_name_encoding (XSTR (func, 0));
6013 local_name = ACONCAT (("__fn_local_", func_name, NULL));
6014 local = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (local_name));
6015 SYMBOL_REF_FLAGS (local) = SYMBOL_REF_FLAGS (func) | SYMBOL_FLAG_LOCAL;
6017 /* Create a new structure to represent the mapping. */
6018 alias = ggc_alloc_mips16_local_alias ();
6020 alias->local = local;
6023 return alias->local;
6026 /* A chained list of functions for which mips16_build_call_stub has already
6027 generated a stub. NAME is the name of the function and FP_RET_P is true
6028 if the function returns a value in floating-point registers. */
6029 struct mips16_stub {
6030 struct mips16_stub *next;
6034 static struct mips16_stub *mips16_stubs;
6036 /* Return the two-character string that identifies floating-point
6037 return mode MODE in the name of a MIPS16 function stub. */
6040 mips16_call_stub_mode_suffix (enum machine_mode mode)
6044 else if (mode == DFmode)
6046 else if (mode == SCmode)
6048 else if (mode == DCmode)
6050 else if (mode == V2SFmode)
6056 /* Write instructions to move a 32-bit value between general register
6057 GPREG and floating-point register FPREG. DIRECTION is 't' to move
6058 from GPREG to FPREG and 'f' to move in the opposite direction. */
6061 mips_output_32bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
6063 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6064 reg_names[gpreg], reg_names[fpreg]);
6067 /* Likewise for 64-bit values. */
6070 mips_output_64bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
6073 fprintf (asm_out_file, "\tdm%cc1\t%s,%s\n", direction,
6074 reg_names[gpreg], reg_names[fpreg]);
6075 else if (TARGET_FLOAT64)
6077 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6078 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
6079 fprintf (asm_out_file, "\tm%chc1\t%s,%s\n", direction,
6080 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg]);
6084 /* Move the least-significant word. */
6085 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6086 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
6087 /* ...then the most significant word. */
6088 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6089 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg + 1]);
6093 /* Write out code to move floating-point arguments into or out of
6094 general registers. FP_CODE is the code describing which arguments
6095 are present (see the comment above the definition of CUMULATIVE_ARGS
6096 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
6099 mips_output_args_xfer (int fp_code, char direction)
6101 unsigned int gparg, fparg, f;
6102 CUMULATIVE_ARGS cum;
6104 /* This code only works for o32 and o64. */
6105 gcc_assert (TARGET_OLDABI);
6107 mips_init_cumulative_args (&cum, NULL);
6109 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
6111 enum machine_mode mode;
6112 struct mips_arg_info info;
6116 else if ((f & 3) == 2)
6121 mips_get_arg_info (&info, &cum, mode, NULL, true);
6122 gparg = mips_arg_regno (&info, false);
6123 fparg = mips_arg_regno (&info, true);
6126 mips_output_32bit_xfer (direction, gparg, fparg);
6128 mips_output_64bit_xfer (direction, gparg, fparg);
6130 mips_function_arg_advance (pack_cumulative_args (&cum), mode, NULL, true);
6134 /* Write a MIPS16 stub for the current function. This stub is used
6135 for functions which take arguments in the floating-point registers.
6136 It is normal-mode code that moves the floating-point arguments
6137 into the general registers and then jumps to the MIPS16 code. */
6140 mips16_build_function_stub (void)
6142 const char *fnname, *alias_name, *separator;
6143 char *secname, *stubname;
6148 /* Create the name of the stub, and its unique section. */
6149 symbol = XEXP (DECL_RTL (current_function_decl), 0);
6150 alias = mips16_local_alias (symbol);
6152 fnname = targetm.strip_name_encoding (XSTR (symbol, 0));
6153 alias_name = targetm.strip_name_encoding (XSTR (alias, 0));
6154 secname = ACONCAT ((".mips16.fn.", fnname, NULL));
6155 stubname = ACONCAT (("__fn_stub_", fnname, NULL));
6157 /* Build a decl for the stub. */
6158 stubdecl = build_decl (BUILTINS_LOCATION,
6159 FUNCTION_DECL, get_identifier (stubname),
6160 build_function_type_list (void_type_node, NULL_TREE));
6161 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
6162 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
6163 RESULT_DECL, NULL_TREE, void_type_node);
6165 /* Output a comment. */
6166 fprintf (asm_out_file, "\t# Stub function for %s (",
6167 current_function_name ());
6169 for (f = (unsigned int) crtl->args.info.fp_code; f != 0; f >>= 2)
6171 fprintf (asm_out_file, "%s%s", separator,
6172 (f & 3) == 1 ? "float" : "double");
6175 fprintf (asm_out_file, ")\n");
6177 /* Start the function definition. */
6178 assemble_start_function (stubdecl, stubname);
6179 mips_start_function_definition (stubname, false);
6181 /* If generating pic2 code, either set up the global pointer or
6183 if (TARGET_ABICALLS_PIC2)
6185 if (TARGET_ABSOLUTE_ABICALLS)
6186 fprintf (asm_out_file, "\t.option\tpic0\n");
6189 output_asm_insn ("%(.cpload\t%^%)", NULL);
6190 /* Emit an R_MIPS_NONE relocation to tell the linker what the
6191 target function is. Use a local GOT access when loading the
6192 symbol, to cut down on the number of unnecessary GOT entries
6193 for stubs that aren't needed. */
6194 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol);
6199 /* Load the address of the MIPS16 function into $25. Do this first so
6200 that targets with coprocessor interlocks can use an MFC1 to fill the
6202 output_asm_insn ("la\t%^,%0", &symbol);
6204 /* Move the arguments from floating-point registers to general registers. */
6205 mips_output_args_xfer (crtl->args.info.fp_code, 'f');
6207 /* Jump to the MIPS16 function. */
6208 output_asm_insn ("jr\t%^", NULL);
6210 if (TARGET_ABICALLS_PIC2 && TARGET_ABSOLUTE_ABICALLS)
6211 fprintf (asm_out_file, "\t.option\tpic2\n");
6213 mips_end_function_definition (stubname);
6215 /* If the linker needs to create a dynamic symbol for the target
6216 function, it will associate the symbol with the stub (which,
6217 unlike the target function, follows the proper calling conventions).
6218 It is therefore useful to have a local alias for the target function,
6219 so that it can still be identified as MIPS16 code. As an optimization,
6220 this symbol can also be used for indirect MIPS16 references from
6221 within this file. */
6222 ASM_OUTPUT_DEF (asm_out_file, alias_name, fnname);
6224 switch_to_section (function_section (current_function_decl));
6227 /* The current function is a MIPS16 function that returns a value in an FPR.
6228 Copy the return value from its soft-float to its hard-float location.
6229 libgcc2 has special non-MIPS16 helper functions for each case. */
6232 mips16_copy_fpr_return_value (void)
6234 rtx fn, insn, retval;
6236 enum machine_mode return_mode;
6239 return_type = DECL_RESULT (current_function_decl);
6240 return_mode = DECL_MODE (return_type);
6242 name = ACONCAT (("__mips16_ret_",
6243 mips16_call_stub_mode_suffix (return_mode),
6245 fn = mips16_stub_function (name);
6247 /* The function takes arguments in $2 (and possibly $3), so calls
6248 to it cannot be lazily bound. */
6249 SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_BIND_NOW;
6251 /* Model the call as something that takes the GPR return value as
6252 argument and returns an "updated" value. */
6253 retval = gen_rtx_REG (return_mode, GP_RETURN);
6254 insn = mips_expand_call (MIPS_CALL_EPILOGUE, retval, fn,
6255 const0_rtx, NULL_RTX, false);
6256 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), retval);
6259 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
6260 RETVAL is the location of the return value, or null if this is
6261 a "call" rather than a "call_value". ARGS_SIZE is the size of the
6262 arguments and FP_CODE is the code built by mips_function_arg;
6263 see the comment before the fp_code field in CUMULATIVE_ARGS for details.
6265 There are three alternatives:
6267 - If a stub was needed, emit the call and return the call insn itself.
6269 - If we can avoid using a stub by redirecting the call, set *FN_PTR
6270 to the new target and return null.
6272 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
6275 A stub is needed for calls to functions that, in normal mode,
6276 receive arguments in FPRs or return values in FPRs. The stub
6277 copies the arguments from their soft-float positions to their
6278 hard-float positions, calls the real function, then copies the
6279 return value from its hard-float position to its soft-float
6282 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
6283 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
6284 automatically redirects the JAL to the stub, otherwise the JAL
6285 continues to call FN directly. */
6288 mips16_build_call_stub (rtx retval, rtx *fn_ptr, rtx args_size, int fp_code)
6292 struct mips16_stub *l;
6295 /* We don't need to do anything if we aren't in MIPS16 mode, or if
6296 we were invoked with the -msoft-float option. */
6297 if (!TARGET_MIPS16 || TARGET_SOFT_FLOAT_ABI)
6300 /* Figure out whether the value might come back in a floating-point
6302 fp_ret_p = retval && mips_return_mode_in_fpr_p (GET_MODE (retval));
6304 /* We don't need to do anything if there were no floating-point
6305 arguments and the value will not be returned in a floating-point
6307 if (fp_code == 0 && !fp_ret_p)
6310 /* We don't need to do anything if this is a call to a special
6311 MIPS16 support function. */
6313 if (mips16_stub_function_p (fn))
6316 /* If we're calling a locally-defined MIPS16 function, we know that
6317 it will return values in both the "soft-float" and "hard-float"
6318 registers. There is no need to use a stub to move the latter
6320 if (fp_code == 0 && mips16_local_function_p (fn))
6323 /* This code will only work for o32 and o64 abis. The other ABI's
6324 require more sophisticated support. */
6325 gcc_assert (TARGET_OLDABI);
6327 /* If we're calling via a function pointer, use one of the magic
6328 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
6329 Each stub expects the function address to arrive in register $2. */
6330 if (GET_CODE (fn) != SYMBOL_REF
6331 || !call_insn_operand (fn, VOIDmode))
6334 rtx stub_fn, insn, addr;
6337 /* If this is a locally-defined and locally-binding function,
6338 avoid the stub by calling the local alias directly. */
6339 if (mips16_local_function_p (fn))
6341 *fn_ptr = mips16_local_alias (fn);
6345 /* Create a SYMBOL_REF for the libgcc.a function. */
6347 sprintf (buf, "__mips16_call_stub_%s_%d",
6348 mips16_call_stub_mode_suffix (GET_MODE (retval)),
6351 sprintf (buf, "__mips16_call_stub_%d", fp_code);
6352 stub_fn = mips16_stub_function (buf);
6354 /* The function uses $2 as an argument, so calls to it
6355 cannot be lazily bound. */
6356 SYMBOL_REF_FLAGS (stub_fn) |= SYMBOL_FLAG_BIND_NOW;
6358 /* Load the target function into $2. */
6359 addr = gen_rtx_REG (Pmode, GP_REG_FIRST + 2);
6360 lazy_p = mips_load_call_address (MIPS_CALL_NORMAL, addr, fn);
6362 /* Emit the call. */
6363 insn = mips_expand_call (MIPS_CALL_NORMAL, retval, stub_fn,
6364 args_size, NULL_RTX, lazy_p);
6366 /* Tell GCC that this call does indeed use the value of $2. */
6367 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), addr);
6369 /* If we are handling a floating-point return value, we need to
6370 save $18 in the function prologue. Putting a note on the
6371 call will mean that df_regs_ever_live_p ($18) will be true if the
6372 call is not eliminated, and we can check that in the prologue
6375 CALL_INSN_FUNCTION_USAGE (insn) =
6376 gen_rtx_EXPR_LIST (VOIDmode,
6377 gen_rtx_CLOBBER (VOIDmode,
6378 gen_rtx_REG (word_mode, 18)),
6379 CALL_INSN_FUNCTION_USAGE (insn));
6384 /* We know the function we are going to call. If we have already
6385 built a stub, we don't need to do anything further. */
6386 fnname = targetm.strip_name_encoding (XSTR (fn, 0));
6387 for (l = mips16_stubs; l != NULL; l = l->next)
6388 if (strcmp (l->name, fnname) == 0)
6393 const char *separator;
6394 char *secname, *stubname;
6395 tree stubid, stubdecl;
6398 /* If the function does not return in FPRs, the special stub
6402 If the function does return in FPRs, the stub section is named
6403 .mips16.call.fp.FNNAME
6405 Build a decl for the stub. */
6406 secname = ACONCAT ((".mips16.call.", fp_ret_p ? "fp." : "",
6408 stubname = ACONCAT (("__call_stub_", fp_ret_p ? "fp_" : "",
6410 stubid = get_identifier (stubname);
6411 stubdecl = build_decl (BUILTINS_LOCATION,
6412 FUNCTION_DECL, stubid,
6413 build_function_type_list (void_type_node,
6415 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
6416 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
6417 RESULT_DECL, NULL_TREE,
6420 /* Output a comment. */
6421 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
6423 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
6427 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
6429 fprintf (asm_out_file, "%s%s", separator,
6430 (f & 3) == 1 ? "float" : "double");
6433 fprintf (asm_out_file, ")\n");
6435 /* Start the function definition. */
6436 assemble_start_function (stubdecl, stubname);
6437 mips_start_function_definition (stubname, false);
6441 fprintf (asm_out_file, "\t.cfi_startproc\n");
6443 /* Create a fake CFA 4 bytes below the stack pointer.
6444 This works around unwinders (like libgcc's) that expect
6445 the CFA for non-signal frames to be unique. */
6446 fprintf (asm_out_file, "\t.cfi_def_cfa 29,-4\n");
6448 /* "Save" $sp in itself so we don't use the fake CFA.
6449 This is: DW_CFA_val_expression r29, { DW_OP_reg29 }. */
6450 fprintf (asm_out_file, "\t.cfi_escape 0x16,29,1,0x6d\n");
6454 /* Load the address of the MIPS16 function into $25. Do this
6455 first so that targets with coprocessor interlocks can use
6456 an MFC1 to fill the delay slot. */
6457 if (TARGET_EXPLICIT_RELOCS)
6459 output_asm_insn ("lui\t%^,%%hi(%0)", &fn);
6460 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn);
6463 output_asm_insn ("la\t%^,%0", &fn);
6466 /* Move the arguments from general registers to floating-point
6468 mips_output_args_xfer (fp_code, 't');
6472 /* Save the return address in $18 and call the non-MIPS16 function.
6473 The stub's caller knows that $18 might be clobbered, even though
6474 $18 is usually a call-saved register. */
6475 fprintf (asm_out_file, "\tmove\t%s,%s\n",
6476 reg_names[GP_REG_FIRST + 18], reg_names[RETURN_ADDR_REGNUM]);
6477 output_asm_insn (MIPS_CALL ("jal", &fn, 0, -1), &fn);
6478 fprintf (asm_out_file, "\t.cfi_register 31,18\n");
6480 /* Move the result from floating-point registers to
6481 general registers. */
6482 switch (GET_MODE (retval))
6485 mips_output_32bit_xfer ('f', GP_RETURN + TARGET_BIG_ENDIAN,
6487 ? FP_REG_FIRST + MAX_FPRS_PER_FMT
6489 mips_output_32bit_xfer ('f', GP_RETURN + TARGET_LITTLE_ENDIAN,
6490 TARGET_LITTLE_ENDIAN
6491 ? FP_REG_FIRST + MAX_FPRS_PER_FMT
6493 if (GET_MODE (retval) == SCmode && TARGET_64BIT)
6495 /* On 64-bit targets, complex floats are returned in
6496 a single GPR, such that "sd" on a suitably-aligned
6497 target would store the value correctly. */
6498 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
6499 reg_names[GP_RETURN + TARGET_BIG_ENDIAN],
6500 reg_names[GP_RETURN + TARGET_BIG_ENDIAN]);
6501 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
6502 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN],
6503 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN]);
6504 fprintf (asm_out_file, "\tdsrl\t%s,%s,32\n",
6505 reg_names[GP_RETURN + TARGET_BIG_ENDIAN],
6506 reg_names[GP_RETURN + TARGET_BIG_ENDIAN]);
6507 fprintf (asm_out_file, "\tor\t%s,%s,%s\n",
6508 reg_names[GP_RETURN],
6509 reg_names[GP_RETURN],
6510 reg_names[GP_RETURN + 1]);
6515 mips_output_32bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6519 mips_output_64bit_xfer ('f', GP_RETURN + (8 / UNITS_PER_WORD),
6520 FP_REG_FIRST + MAX_FPRS_PER_FMT);
6524 mips_output_64bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6530 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 18]);
6531 fprintf (asm_out_file, "\t.cfi_endproc\n");
6535 /* Jump to the previously-loaded address. */
6536 output_asm_insn ("jr\t%^", NULL);
6539 #ifdef ASM_DECLARE_FUNCTION_SIZE
6540 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
6543 mips_end_function_definition (stubname);
6545 /* Record this stub. */
6546 l = XNEW (struct mips16_stub);
6547 l->name = xstrdup (fnname);
6548 l->fp_ret_p = fp_ret_p;
6549 l->next = mips16_stubs;
6553 /* If we expect a floating-point return value, but we've built a
6554 stub which does not expect one, then we're in trouble. We can't
6555 use the existing stub, because it won't handle the floating-point
6556 value. We can't build a new stub, because the linker won't know
6557 which stub to use for the various calls in this object file.
6558 Fortunately, this case is illegal, since it means that a function
6559 was declared in two different ways in a single compilation. */
6560 if (fp_ret_p && !l->fp_ret_p)
6561 error ("cannot handle inconsistent calls to %qs", fnname);
6563 if (retval == NULL_RTX)
6564 insn = gen_call_internal_direct (fn, args_size);
6566 insn = gen_call_value_internal_direct (retval, fn, args_size);
6567 insn = mips_emit_call_insn (insn, fn, fn, false);
6569 /* If we are calling a stub which handles a floating-point return
6570 value, we need to arrange to save $18 in the prologue. We do this
6571 by marking the function call as using the register. The prologue
6572 will later see that it is used, and emit code to save it. */
6574 CALL_INSN_FUNCTION_USAGE (insn) =
6575 gen_rtx_EXPR_LIST (VOIDmode,
6576 gen_rtx_CLOBBER (VOIDmode,
6577 gen_rtx_REG (word_mode, 18)),
6578 CALL_INSN_FUNCTION_USAGE (insn));
6583 /* Expand a call of type TYPE. RESULT is where the result will go (null
6584 for "call"s and "sibcall"s), ADDR is the address of the function,
6585 ARGS_SIZE is the size of the arguments and AUX is the value passed
6586 to us by mips_function_arg. LAZY_P is true if this call already
6587 involves a lazily-bound function address (such as when calling
6588 functions through a MIPS16 hard-float stub).
6590 Return the call itself. */
6593 mips_expand_call (enum mips_call_type type, rtx result, rtx addr,
6594 rtx args_size, rtx aux, bool lazy_p)
6596 rtx orig_addr, pattern, insn;
6599 fp_code = aux == 0 ? 0 : (int) GET_MODE (aux);
6600 insn = mips16_build_call_stub (result, &addr, args_size, fp_code);
6603 gcc_assert (!lazy_p && type == MIPS_CALL_NORMAL);
6608 if (!call_insn_operand (addr, VOIDmode))
6610 if (type == MIPS_CALL_EPILOGUE)
6611 addr = MIPS_EPILOGUE_TEMP (Pmode);
6613 addr = gen_reg_rtx (Pmode);
6614 lazy_p |= mips_load_call_address (type, addr, orig_addr);
6619 rtx (*fn) (rtx, rtx);
6621 if (type == MIPS_CALL_SIBCALL)
6622 fn = gen_sibcall_internal;
6624 fn = gen_call_internal;
6626 pattern = fn (addr, args_size);
6628 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
6630 /* Handle return values created by mips_return_fpr_pair. */
6631 rtx (*fn) (rtx, rtx, rtx, rtx);
6634 if (type == MIPS_CALL_SIBCALL)
6635 fn = gen_sibcall_value_multiple_internal;
6637 fn = gen_call_value_multiple_internal;
6639 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
6640 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
6641 pattern = fn (reg1, addr, args_size, reg2);
6645 rtx (*fn) (rtx, rtx, rtx);
6647 if (type == MIPS_CALL_SIBCALL)
6648 fn = gen_sibcall_value_internal;
6650 fn = gen_call_value_internal;
6652 /* Handle return values created by mips_return_fpr_single. */
6653 if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 1)
6654 result = XEXP (XVECEXP (result, 0, 0), 0);
6655 pattern = fn (result, addr, args_size);
6658 return mips_emit_call_insn (pattern, orig_addr, addr, lazy_p);
6661 /* Split call instruction INSN into a $gp-clobbering call and
6662 (where necessary) an instruction to restore $gp from its save slot.
6663 CALL_PATTERN is the pattern of the new call. */
6666 mips_split_call (rtx insn, rtx call_pattern)
6668 emit_call_insn (call_pattern);
6669 if (!find_reg_note (insn, REG_NORETURN, 0))
6670 /* Pick a temporary register that is suitable for both MIPS16 and
6671 non-MIPS16 code. $4 and $5 are used for returning complex double
6672 values in soft-float code, so $6 is the first suitable candidate. */
6673 mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode, GP_ARG_FIRST + 2));
6676 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
6679 mips_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
6681 if (!TARGET_SIBCALLS)
6684 /* Interrupt handlers need special epilogue code and therefore can't
6686 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
6689 /* We can't do a sibcall if the called function is a MIPS16 function
6690 because there is no direct "jx" instruction equivalent to "jalx" to
6691 switch the ISA mode. We only care about cases where the sibling
6692 and normal calls would both be direct. */
6694 && mips_use_mips16_mode_p (decl)
6695 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
6698 /* When -minterlink-mips16 is in effect, assume that non-locally-binding
6699 functions could be MIPS16 ones unless an attribute explicitly tells
6701 if (TARGET_INTERLINK_MIPS16
6703 && (DECL_EXTERNAL (decl) || !targetm.binds_local_p (decl))
6704 && !mips_nomips16_decl_p (decl)
6705 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
6712 /* Emit code to move general operand SRC into condition-code
6713 register DEST given that SCRATCH is a scratch TFmode FPR.
6720 where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */
6723 mips_expand_fcc_reload (rtx dest, rtx src, rtx scratch)
6727 /* Change the source to SFmode. */
6729 src = adjust_address (src, SFmode, 0);
6730 else if (REG_P (src) || GET_CODE (src) == SUBREG)
6731 src = gen_rtx_REG (SFmode, true_regnum (src));
6733 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
6734 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + MAX_FPRS_PER_FMT);
6736 mips_emit_move (copy_rtx (fp1), src);
6737 mips_emit_move (copy_rtx (fp2), CONST0_RTX (SFmode));
6738 emit_insn (gen_slt_sf (dest, fp2, fp1));
6741 /* Implement MOVE_BY_PIECES_P. */
6744 mips_move_by_pieces_p (unsigned HOST_WIDE_INT size, unsigned int align)
6748 /* movmemsi is meant to generate code that is at least as good as
6749 move_by_pieces. However, movmemsi effectively uses a by-pieces
6750 implementation both for moves smaller than a word and for
6751 word-aligned moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT
6752 bytes. We should allow the tree-level optimisers to do such
6753 moves by pieces, as it often exposes other optimization
6754 opportunities. We might as well continue to use movmemsi at
6755 the rtl level though, as it produces better code when
6756 scheduling is disabled (such as at -O). */
6757 if (currently_expanding_to_rtl)
6759 if (align < BITS_PER_WORD)
6760 return size < UNITS_PER_WORD;
6761 return size <= MIPS_MAX_MOVE_BYTES_STRAIGHT;
6763 /* The default value. If this becomes a target hook, we should
6764 call the default definition instead. */
6765 return (move_by_pieces_ninsns (size, align, MOVE_MAX_PIECES + 1)
6766 < (unsigned int) MOVE_RATIO (optimize_insn_for_speed_p ()));
6769 /* Implement STORE_BY_PIECES_P. */
6772 mips_store_by_pieces_p (unsigned HOST_WIDE_INT size, unsigned int align)
6774 /* Storing by pieces involves moving constants into registers
6775 of size MIN (ALIGN, BITS_PER_WORD), then storing them.
6776 We need to decide whether it is cheaper to load the address of
6777 constant data into a register and use a block move instead. */
6779 /* If the data is only byte aligned, then:
6781 (a1) A block move of less than 4 bytes would involve three 3 LBs and
6782 3 SBs. We might as well use 3 single-instruction LIs and 3 SBs
6785 (a2) A block move of 4 bytes from aligned source data can use an
6786 LW/SWL/SWR sequence. This is often better than the 4 LIs and
6787 4 SBs that we would generate when storing by pieces. */
6788 if (align <= BITS_PER_UNIT)
6791 /* If the data is 2-byte aligned, then:
6793 (b1) A block move of less than 4 bytes would use a combination of LBs,
6794 LHs, SBs and SHs. We get better code by using single-instruction
6795 LIs, SBs and SHs instead.
6797 (b2) A block move of 4 bytes from aligned source data would again use
6798 an LW/SWL/SWR sequence. In most cases, loading the address of
6799 the source data would require at least one extra instruction.
6800 It is often more efficient to use 2 single-instruction LIs and
6803 (b3) A block move of up to 3 additional bytes would be like (b1).
6805 (b4) A block move of 8 bytes from aligned source data can use two
6806 LW/SWL/SWR sequences or a single LD/SDL/SDR sequence. Both
6807 sequences are better than the 4 LIs and 4 SHs that we'd generate
6808 when storing by pieces.
6810 The reasoning for higher alignments is similar:
6812 (c1) A block move of less than 4 bytes would be the same as (b1).
6814 (c2) A block move of 4 bytes would use an LW/SW sequence. Again,
6815 loading the address of the source data would typically require
6816 at least one extra instruction. It is generally better to use
6819 (c3) A block move of up to 3 additional bytes would be like (b1).
6821 (c4) A block move of 8 bytes can use two LW/SW sequences or a single
6822 LD/SD sequence, and in these cases we've traditionally preferred
6823 the memory copy over the more bulky constant moves. */
6827 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
6828 Assume that the areas do not overlap. */
6831 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
6833 HOST_WIDE_INT offset, delta;
6834 unsigned HOST_WIDE_INT bits;
6836 enum machine_mode mode;
6839 /* Work out how many bits to move at a time. If both operands have
6840 half-word alignment, it is usually better to move in half words.
6841 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
6842 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
6843 Otherwise move word-sized chunks. */
6844 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
6845 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
6846 bits = BITS_PER_WORD / 2;
6848 bits = BITS_PER_WORD;
6850 mode = mode_for_size (bits, MODE_INT, 0);
6851 delta = bits / BITS_PER_UNIT;
6853 /* Allocate a buffer for the temporary registers. */
6854 regs = XALLOCAVEC (rtx, length / delta);
6856 /* Load as many BITS-sized chunks as possible. Use a normal load if
6857 the source has enough alignment, otherwise use left/right pairs. */
6858 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
6860 regs[i] = gen_reg_rtx (mode);
6861 if (MEM_ALIGN (src) >= bits)
6862 mips_emit_move (regs[i], adjust_address (src, mode, offset));
6865 rtx part = adjust_address (src, BLKmode, offset);
6866 if (!mips_expand_ext_as_unaligned_load (regs[i], part, bits, 0))
6871 /* Copy the chunks to the destination. */
6872 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
6873 if (MEM_ALIGN (dest) >= bits)
6874 mips_emit_move (adjust_address (dest, mode, offset), regs[i]);
6877 rtx part = adjust_address (dest, BLKmode, offset);
6878 if (!mips_expand_ins_as_unaligned_store (part, regs[i], bits, 0))
6882 /* Mop up any left-over bytes. */
6883 if (offset < length)
6885 src = adjust_address (src, BLKmode, offset);
6886 dest = adjust_address (dest, BLKmode, offset);
6887 move_by_pieces (dest, src, length - offset,
6888 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
6892 /* Helper function for doing a loop-based block operation on memory
6893 reference MEM. Each iteration of the loop will operate on LENGTH
6896 Create a new base register for use within the loop and point it to
6897 the start of MEM. Create a new memory reference that uses this
6898 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
6901 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
6902 rtx *loop_reg, rtx *loop_mem)
6904 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
6906 /* Although the new mem does not refer to a known location,
6907 it does keep up to LENGTH bytes of alignment. */
6908 *loop_mem = change_address (mem, BLKmode, *loop_reg);
6909 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
6912 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
6913 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
6914 the memory regions do not overlap. */
6917 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length,
6918 HOST_WIDE_INT bytes_per_iter)
6920 rtx label, src_reg, dest_reg, final_src, test;
6921 HOST_WIDE_INT leftover;
6923 leftover = length % bytes_per_iter;
6926 /* Create registers and memory references for use within the loop. */
6927 mips_adjust_block_mem (src, bytes_per_iter, &src_reg, &src);
6928 mips_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest);
6930 /* Calculate the value that SRC_REG should have after the last iteration
6932 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
6935 /* Emit the start of the loop. */
6936 label = gen_label_rtx ();
6939 /* Emit the loop body. */
6940 mips_block_move_straight (dest, src, bytes_per_iter);
6942 /* Move on to the next block. */
6943 mips_emit_move (src_reg, plus_constant (src_reg, bytes_per_iter));
6944 mips_emit_move (dest_reg, plus_constant (dest_reg, bytes_per_iter));
6946 /* Emit the loop condition. */
6947 test = gen_rtx_NE (VOIDmode, src_reg, final_src);
6948 if (Pmode == DImode)
6949 emit_jump_insn (gen_cbranchdi4 (test, src_reg, final_src, label));
6951 emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label));
6953 /* Mop up any left-over bytes. */
6955 mips_block_move_straight (dest, src, leftover);
6958 /* Expand a movmemsi instruction, which copies LENGTH bytes from
6959 memory reference SRC to memory reference DEST. */
6962 mips_expand_block_move (rtx dest, rtx src, rtx length)
6964 if (CONST_INT_P (length))
6966 if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)
6968 mips_block_move_straight (dest, src, INTVAL (length));
6973 mips_block_move_loop (dest, src, INTVAL (length),
6974 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER);
6981 /* Expand a loop of synci insns for the address range [BEGIN, END). */
6984 mips_expand_synci_loop (rtx begin, rtx end)
6986 rtx inc, label, end_label, cmp_result, mask, length;
6988 /* Create end_label. */
6989 end_label = gen_label_rtx ();
6991 /* Check if begin equals end. */
6992 cmp_result = gen_rtx_EQ (VOIDmode, begin, end);
6993 emit_jump_insn (gen_condjump (cmp_result, end_label));
6995 /* Load INC with the cache line size (rdhwr INC,$1). */
6996 inc = gen_reg_rtx (Pmode);
6997 emit_insn (PMODE_INSN (gen_rdhwr_synci_step, (inc)));
6999 /* Check if inc is 0. */
7000 cmp_result = gen_rtx_EQ (VOIDmode, inc, const0_rtx);
7001 emit_jump_insn (gen_condjump (cmp_result, end_label));
7003 /* Calculate mask. */
7004 mask = mips_force_unary (Pmode, NEG, inc);
7006 /* Mask out begin by mask. */
7007 begin = mips_force_binary (Pmode, AND, begin, mask);
7009 /* Calculate length. */
7010 length = mips_force_binary (Pmode, MINUS, end, begin);
7012 /* Loop back to here. */
7013 label = gen_label_rtx ();
7016 emit_insn (gen_synci (begin));
7018 /* Update length. */
7019 mips_emit_binary (MINUS, length, length, inc);
7022 mips_emit_binary (PLUS, begin, begin, inc);
7024 /* Check if length is greater than 0. */
7025 cmp_result = gen_rtx_GT (VOIDmode, length, const0_rtx);
7026 emit_jump_insn (gen_condjump (cmp_result, label));
7028 emit_label (end_label);
7031 /* Expand a QI or HI mode atomic memory operation.
7033 GENERATOR contains a pointer to the gen_* function that generates
7034 the SI mode underlying atomic operation using masks that we
7037 RESULT is the return register for the operation. Its value is NULL
7040 MEM is the location of the atomic access.
7042 OLDVAL is the first operand for the operation.
7044 NEWVAL is the optional second operand for the operation. Its value
7045 is NULL if unused. */
7048 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator,
7049 rtx result, rtx mem, rtx oldval, rtx newval)
7051 rtx orig_addr, memsi_addr, memsi, shift, shiftsi, unshifted_mask;
7052 rtx unshifted_mask_reg, mask, inverted_mask, si_op;
7054 enum machine_mode mode;
7056 mode = GET_MODE (mem);
7058 /* Compute the address of the containing SImode value. */
7059 orig_addr = force_reg (Pmode, XEXP (mem, 0));
7060 memsi_addr = mips_force_binary (Pmode, AND, orig_addr,
7061 force_reg (Pmode, GEN_INT (-4)));
7063 /* Create a memory reference for it. */
7064 memsi = gen_rtx_MEM (SImode, memsi_addr);
7065 set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER);
7066 MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem);
7068 /* Work out the byte offset of the QImode or HImode value,
7069 counting from the least significant byte. */
7070 shift = mips_force_binary (Pmode, AND, orig_addr, GEN_INT (3));
7071 if (TARGET_BIG_ENDIAN)
7072 mips_emit_binary (XOR, shift, shift, GEN_INT (mode == QImode ? 3 : 2));
7074 /* Multiply by eight to convert the shift value from bytes to bits. */
7075 mips_emit_binary (ASHIFT, shift, shift, GEN_INT (3));
7077 /* Make the final shift an SImode value, so that it can be used in
7078 SImode operations. */
7079 shiftsi = force_reg (SImode, gen_lowpart (SImode, shift));
7081 /* Set MASK to an inclusive mask of the QImode or HImode value. */
7082 unshifted_mask = GEN_INT (GET_MODE_MASK (mode));
7083 unshifted_mask_reg = force_reg (SImode, unshifted_mask);
7084 mask = mips_force_binary (SImode, ASHIFT, unshifted_mask_reg, shiftsi);
7086 /* Compute the equivalent exclusive mask. */
7087 inverted_mask = gen_reg_rtx (SImode);
7088 emit_insn (gen_rtx_SET (VOIDmode, inverted_mask,
7089 gen_rtx_NOT (SImode, mask)));
7091 /* Shift the old value into place. */
7092 if (oldval != const0_rtx)
7094 oldval = convert_modes (SImode, mode, oldval, true);
7095 oldval = force_reg (SImode, oldval);
7096 oldval = mips_force_binary (SImode, ASHIFT, oldval, shiftsi);
7099 /* Do the same for the new value. */
7100 if (newval && newval != const0_rtx)
7102 newval = convert_modes (SImode, mode, newval, true);
7103 newval = force_reg (SImode, newval);
7104 newval = mips_force_binary (SImode, ASHIFT, newval, shiftsi);
7107 /* Do the SImode atomic access. */
7109 res = gen_reg_rtx (SImode);
7111 si_op = generator.fn_6 (res, memsi, mask, inverted_mask, oldval, newval);
7113 si_op = generator.fn_5 (res, memsi, mask, inverted_mask, oldval);
7115 si_op = generator.fn_4 (memsi, mask, inverted_mask, oldval);
7121 /* Shift and convert the result. */
7122 mips_emit_binary (AND, res, res, mask);
7123 mips_emit_binary (LSHIFTRT, res, res, shiftsi);
7124 mips_emit_move (result, gen_lowpart (GET_MODE (result), res));
7128 /* Return true if it is possible to use left/right accesses for a
7129 bitfield of WIDTH bits starting BITPOS bits into *OP. When
7130 returning true, update *OP, *LEFT and *RIGHT as follows:
7132 *OP is a BLKmode reference to the whole field.
7134 *LEFT is a QImode reference to the first byte if big endian or
7135 the last byte if little endian. This address can be used in the
7136 left-side instructions (LWL, SWL, LDL, SDL).
7138 *RIGHT is a QImode reference to the opposite end of the field and
7139 can be used in the patterning right-side instruction. */
7142 mips_get_unaligned_mem (rtx *op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos,
7143 rtx *left, rtx *right)
7147 /* Check that the operand really is a MEM. Not all the extv and
7148 extzv predicates are checked. */
7152 /* Check that the size is valid. */
7153 if (width != 32 && (!TARGET_64BIT || width != 64))
7156 /* We can only access byte-aligned values. Since we are always passed
7157 a reference to the first byte of the field, it is not necessary to
7158 do anything with BITPOS after this check. */
7159 if (bitpos % BITS_PER_UNIT != 0)
7162 /* Reject aligned bitfields: we want to use a normal load or store
7163 instead of a left/right pair. */
7164 if (MEM_ALIGN (*op) >= width)
7167 /* Adjust *OP to refer to the whole field. This also has the effect
7168 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
7169 *op = adjust_address (*op, BLKmode, 0);
7170 set_mem_size (*op, width / BITS_PER_UNIT);
7172 /* Get references to both ends of the field. We deliberately don't
7173 use the original QImode *OP for FIRST since the new BLKmode one
7174 might have a simpler address. */
7175 first = adjust_address (*op, QImode, 0);
7176 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
7178 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
7179 correspond to the MSB and RIGHT to the LSB. */
7180 if (TARGET_BIG_ENDIAN)
7181 *left = first, *right = last;
7183 *left = last, *right = first;
7188 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
7189 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
7190 the operation is the equivalent of:
7192 (set DEST (*_extract SRC WIDTH BITPOS))
7194 Return true on success. */
7197 mips_expand_ext_as_unaligned_load (rtx dest, rtx src, HOST_WIDE_INT width,
7198 HOST_WIDE_INT bitpos)
7200 rtx left, right, temp;
7202 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
7203 be a paradoxical word_mode subreg. This is the only case in which
7204 we allow the destination to be larger than the source. */
7205 if (GET_CODE (dest) == SUBREG
7206 && GET_MODE (dest) == DImode
7207 && GET_MODE (SUBREG_REG (dest)) == SImode)
7208 dest = SUBREG_REG (dest);
7210 /* After the above adjustment, the destination must be the same
7211 width as the source. */
7212 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
7215 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
7218 temp = gen_reg_rtx (GET_MODE (dest));
7219 if (GET_MODE (dest) == DImode)
7221 emit_insn (gen_mov_ldl (temp, src, left));
7222 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
7226 emit_insn (gen_mov_lwl (temp, src, left));
7227 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
7232 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
7233 BITPOS and SRC are the operands passed to the expander; the operation
7234 is the equivalent of:
7236 (set (zero_extract DEST WIDTH BITPOS) SRC)
7238 Return true on success. */
7241 mips_expand_ins_as_unaligned_store (rtx dest, rtx src, HOST_WIDE_INT width,
7242 HOST_WIDE_INT bitpos)
7245 enum machine_mode mode;
7247 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
7250 mode = mode_for_size (width, MODE_INT, 0);
7251 src = gen_lowpart (mode, src);
7254 emit_insn (gen_mov_sdl (dest, src, left));
7255 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
7259 emit_insn (gen_mov_swl (dest, src, left));
7260 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
7265 /* Return true if X is a MEM with the same size as MODE. */
7268 mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
7271 && MEM_SIZE_KNOWN_P (x)
7272 && MEM_SIZE (x) == GET_MODE_SIZE (mode));
7275 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
7276 source of an "ext" instruction or the destination of an "ins"
7277 instruction. OP must be a register operand and the following
7278 conditions must hold:
7280 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
7281 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7282 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7284 Also reject lengths equal to a word as they are better handled
7285 by the move patterns. */
7288 mips_use_ins_ext_p (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos)
7290 if (!ISA_HAS_EXT_INS
7291 || !register_operand (op, VOIDmode)
7292 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
7295 if (!IN_RANGE (width, 1, GET_MODE_BITSIZE (GET_MODE (op)) - 1))
7298 if (bitpos < 0 || bitpos + width > GET_MODE_BITSIZE (GET_MODE (op)))
7304 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
7305 operation if MAXLEN is the maxium length of consecutive bits that
7306 can make up MASK. MODE is the mode of the operation. See
7307 mask_low_and_shift_len for the actual definition. */
7310 mask_low_and_shift_p (enum machine_mode mode, rtx mask, rtx shift, int maxlen)
7312 return IN_RANGE (mask_low_and_shift_len (mode, mask, shift), 1, maxlen);
7315 /* Return true iff OP1 and OP2 are valid operands together for the
7316 *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider,
7317 see the table in the comment before the pattern. */
7320 and_operands_ok (enum machine_mode mode, rtx op1, rtx op2)
7322 return (memory_operand (op1, mode)
7323 ? and_load_operand (op2, mode)
7324 : and_reg_operand (op2, mode));
7327 /* The canonical form of a mask-low-and-shift-left operation is
7328 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
7329 cleared. Thus we need to shift MASK to the right before checking if it
7330 is a valid mask value. MODE is the mode of the operation. If true
7331 return the length of the mask, otherwise return -1. */
7334 mask_low_and_shift_len (enum machine_mode mode, rtx mask, rtx shift)
7336 HOST_WIDE_INT shval;
7338 shval = INTVAL (shift) & (GET_MODE_BITSIZE (mode) - 1);
7339 return exact_log2 ((UINTVAL (mask) >> shval) + 1);
7342 /* Return true if -msplit-addresses is selected and should be honored.
7344 -msplit-addresses is a half-way house between explicit relocations
7345 and the traditional assembler macros. It can split absolute 32-bit
7346 symbolic constants into a high/lo_sum pair but uses macros for other
7349 Like explicit relocation support for REL targets, it relies
7350 on GNU extensions in the assembler and the linker.
7352 Although this code should work for -O0, it has traditionally
7353 been treated as an optimization. */
7356 mips_split_addresses_p (void)
7358 return (TARGET_SPLIT_ADDRESSES
7362 && !ABI_HAS_64BIT_SYMBOLS);
7365 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
7368 mips_init_relocs (void)
7370 memset (mips_split_p, '\0', sizeof (mips_split_p));
7371 memset (mips_split_hi_p, '\0', sizeof (mips_split_hi_p));
7372 memset (mips_use_pcrel_pool_p, '\0', sizeof (mips_use_pcrel_pool_p));
7373 memset (mips_hi_relocs, '\0', sizeof (mips_hi_relocs));
7374 memset (mips_lo_relocs, '\0', sizeof (mips_lo_relocs));
7376 if (TARGET_MIPS16_PCREL_LOADS)
7377 mips_use_pcrel_pool_p[SYMBOL_ABSOLUTE] = true;
7380 if (ABI_HAS_64BIT_SYMBOLS)
7382 if (TARGET_EXPLICIT_RELOCS)
7384 mips_split_p[SYMBOL_64_HIGH] = true;
7385 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
7386 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
7388 mips_split_p[SYMBOL_64_MID] = true;
7389 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
7390 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
7392 mips_split_p[SYMBOL_64_LOW] = true;
7393 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
7394 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
7396 mips_split_p[SYMBOL_ABSOLUTE] = true;
7397 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
7402 if (TARGET_EXPLICIT_RELOCS
7403 || mips_split_addresses_p ()
7406 mips_split_p[SYMBOL_ABSOLUTE] = true;
7407 mips_hi_relocs[SYMBOL_ABSOLUTE] = "%hi(";
7408 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
7415 /* The high part is provided by a pseudo copy of $gp. */
7416 mips_split_p[SYMBOL_GP_RELATIVE] = true;
7417 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gprel(";
7419 else if (TARGET_EXPLICIT_RELOCS)
7420 /* Small data constants are kept whole until after reload,
7421 then lowered by mips_rewrite_small_data. */
7422 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gp_rel(";
7424 if (TARGET_EXPLICIT_RELOCS)
7426 mips_split_p[SYMBOL_GOT_PAGE_OFST] = true;
7429 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
7430 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%got_ofst(";
7434 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
7435 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%lo(";
7438 /* Expose the use of $28 as soon as possible. */
7439 mips_split_hi_p[SYMBOL_GOT_PAGE_OFST] = true;
7443 /* The HIGH and LO_SUM are matched by special .md patterns. */
7444 mips_split_p[SYMBOL_GOT_DISP] = true;
7446 mips_split_p[SYMBOL_GOTOFF_DISP] = true;
7447 mips_hi_relocs[SYMBOL_GOTOFF_DISP] = "%got_hi(";
7448 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_lo(";
7450 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
7451 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
7452 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
7457 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_disp(";
7459 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got(";
7460 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
7462 /* Expose the use of $28 as soon as possible. */
7463 mips_split_p[SYMBOL_GOT_DISP] = true;
7469 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
7470 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
7471 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
7474 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
7475 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
7477 if (TARGET_MIPS16_PCREL_LOADS)
7479 mips_use_pcrel_pool_p[SYMBOL_DTPREL] = true;
7480 mips_use_pcrel_pool_p[SYMBOL_TPREL] = true;
7484 mips_split_p[SYMBOL_DTPREL] = true;
7485 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
7486 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
7488 mips_split_p[SYMBOL_TPREL] = true;
7489 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
7490 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
7493 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
7494 mips_lo_relocs[SYMBOL_HALF] = "%half(";
7497 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
7498 in context CONTEXT. RELOCS is the array of relocations to use. */
7501 mips_print_operand_reloc (FILE *file, rtx op, enum mips_symbol_context context,
7502 const char **relocs)
7504 enum mips_symbol_type symbol_type;
7507 symbol_type = mips_classify_symbolic_expression (op, context);
7508 gcc_assert (relocs[symbol_type]);
7510 fputs (relocs[symbol_type], file);
7511 output_addr_const (file, mips_strip_unspec_address (op));
7512 for (p = relocs[symbol_type]; *p != 0; p++)
7517 /* Start a new block with the given asm switch enabled. If we need
7518 to print a directive, emit PREFIX before it and SUFFIX after it. */
7521 mips_push_asm_switch_1 (struct mips_asm_switch *asm_switch,
7522 const char *prefix, const char *suffix)
7524 if (asm_switch->nesting_level == 0)
7525 fprintf (asm_out_file, "%s.set\tno%s%s", prefix, asm_switch->name, suffix);
7526 asm_switch->nesting_level++;
7529 /* Likewise, but end a block. */
7532 mips_pop_asm_switch_1 (struct mips_asm_switch *asm_switch,
7533 const char *prefix, const char *suffix)
7535 gcc_assert (asm_switch->nesting_level);
7536 asm_switch->nesting_level--;
7537 if (asm_switch->nesting_level == 0)
7538 fprintf (asm_out_file, "%s.set\t%s%s", prefix, asm_switch->name, suffix);
7541 /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1
7542 that either print a complete line or print nothing. */
7545 mips_push_asm_switch (struct mips_asm_switch *asm_switch)
7547 mips_push_asm_switch_1 (asm_switch, "\t", "\n");
7551 mips_pop_asm_switch (struct mips_asm_switch *asm_switch)
7553 mips_pop_asm_switch_1 (asm_switch, "\t", "\n");
7556 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
7557 The punctuation characters are:
7559 '(' Start a nested ".set noreorder" block.
7560 ')' End a nested ".set noreorder" block.
7561 '[' Start a nested ".set noat" block.
7562 ']' End a nested ".set noat" block.
7563 '<' Start a nested ".set nomacro" block.
7564 '>' End a nested ".set nomacro" block.
7565 '*' Behave like %(%< if generating a delayed-branch sequence.
7566 '#' Print a nop if in a ".set noreorder" block.
7567 '/' Like '#', but do nothing within a delayed-branch sequence.
7568 '?' Print "l" if mips_branch_likely is true
7569 '~' Print a nop if mips_branch_likely is true
7570 '.' Print the name of the register with a hard-wired zero (zero or $0).
7571 '@' Print the name of the assembler temporary register (at or $1).
7572 '^' Print the name of the pic call-through register (t9 or $25).
7573 '+' Print the name of the gp register (usually gp or $28).
7574 '$' Print the name of the stack pointer register (sp or $29).
7576 See also mips_init_print_operand_pucnt. */
7579 mips_print_operand_punctuation (FILE *file, int ch)
7584 mips_push_asm_switch_1 (&mips_noreorder, "", "\n\t");
7588 mips_pop_asm_switch_1 (&mips_noreorder, "\n\t", "");
7592 mips_push_asm_switch_1 (&mips_noat, "", "\n\t");
7596 mips_pop_asm_switch_1 (&mips_noat, "\n\t", "");
7600 mips_push_asm_switch_1 (&mips_nomacro, "", "\n\t");
7604 mips_pop_asm_switch_1 (&mips_nomacro, "\n\t", "");
7608 if (final_sequence != 0)
7610 mips_print_operand_punctuation (file, '(');
7611 mips_print_operand_punctuation (file, '<');
7616 if (mips_noreorder.nesting_level > 0)
7617 fputs ("\n\tnop", file);
7621 /* Print an extra newline so that the delayed insn is separated
7622 from the following ones. This looks neater and is consistent
7623 with non-nop delayed sequences. */
7624 if (mips_noreorder.nesting_level > 0 && final_sequence == 0)
7625 fputs ("\n\tnop\n", file);
7629 if (mips_branch_likely)
7634 if (mips_branch_likely)
7635 fputs ("\n\tnop", file);
7639 fputs (reg_names[GP_REG_FIRST + 0], file);
7643 fputs (reg_names[AT_REGNUM], file);
7647 fputs (reg_names[PIC_FUNCTION_ADDR_REGNUM], file);
7651 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
7655 fputs (reg_names[STACK_POINTER_REGNUM], file);
7664 /* Initialize mips_print_operand_punct. */
7667 mips_init_print_operand_punct (void)
7671 for (p = "()[]<>*#/?~.@^+$"; *p; p++)
7672 mips_print_operand_punct[(unsigned char) *p] = true;
7675 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
7676 associated with condition CODE. Print the condition part of the
7680 mips_print_int_branch_condition (FILE *file, enum rtx_code code, int letter)
7694 /* Conveniently, the MIPS names for these conditions are the same
7695 as their RTL equivalents. */
7696 fputs (GET_RTX_NAME (code), file);
7700 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
7705 /* Likewise floating-point branches. */
7708 mips_print_float_branch_condition (FILE *file, enum rtx_code code, int letter)
7713 fputs ("c1f", file);
7717 fputs ("c1t", file);
7721 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
7726 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
7729 mips_print_operand_punct_valid_p (unsigned char code)
7731 return mips_print_operand_punct[code];
7734 /* Implement TARGET_PRINT_OPERAND. The MIPS-specific operand codes are:
7736 'X' Print CONST_INT OP in hexadecimal format.
7737 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
7738 'd' Print CONST_INT OP in decimal.
7739 'm' Print one less than CONST_INT OP in decimal.
7740 'h' Print the high-part relocation associated with OP, after stripping
7742 'R' Print the low-part relocation associated with OP.
7743 'C' Print the integer branch condition for comparison OP.
7744 'N' Print the inverse of the integer branch condition for comparison OP.
7745 'F' Print the FPU branch condition for comparison OP.
7746 'W' Print the inverse of the FPU branch condition for comparison OP.
7747 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
7748 'z' for (eq:?I ...), 'n' for (ne:?I ...).
7749 't' Like 'T', but with the EQ/NE cases reversed
7750 'Y' Print mips_fp_conditions[INTVAL (OP)]
7751 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
7752 'q' Print a DSP accumulator register.
7753 'D' Print the second part of a double-word register or memory operand.
7754 'L' Print the low-order register in a double-word register operand.
7755 'M' Print high-order register in a double-word register operand.
7756 'z' Print $0 if OP is zero, otherwise print OP normally. */
7759 mips_print_operand (FILE *file, rtx op, int letter)
7763 if (mips_print_operand_punct_valid_p (letter))
7765 mips_print_operand_punctuation (file, letter);
7770 code = GET_CODE (op);
7775 if (CONST_INT_P (op))
7776 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
7778 output_operand_lossage ("invalid use of '%%%c'", letter);
7782 if (CONST_INT_P (op))
7783 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op) & 0xffff);
7785 output_operand_lossage ("invalid use of '%%%c'", letter);
7789 if (CONST_INT_P (op))
7790 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op));
7792 output_operand_lossage ("invalid use of '%%%c'", letter);
7796 if (CONST_INT_P (op))
7797 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op) - 1);
7799 output_operand_lossage ("invalid use of '%%%c'", letter);
7805 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_hi_relocs);
7809 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_lo_relocs);
7813 mips_print_int_branch_condition (file, code, letter);
7817 mips_print_int_branch_condition (file, reverse_condition (code), letter);
7821 mips_print_float_branch_condition (file, code, letter);
7825 mips_print_float_branch_condition (file, reverse_condition (code),
7832 int truth = (code == NE) == (letter == 'T');
7833 fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
7838 if (code == CONST_INT && UINTVAL (op) < ARRAY_SIZE (mips_fp_conditions))
7839 fputs (mips_fp_conditions[UINTVAL (op)], file);
7841 output_operand_lossage ("'%%%c' is not a valid operand prefix",
7848 mips_print_operand (file, op, 0);
7854 if (code == REG && MD_REG_P (REGNO (op)))
7855 fprintf (file, "$ac0");
7856 else if (code == REG && DSP_ACC_REG_P (REGNO (op)))
7857 fprintf (file, "$ac%c", reg_names[REGNO (op)][3]);
7859 output_operand_lossage ("invalid use of '%%%c'", letter);
7867 unsigned int regno = REGNO (op);
7868 if ((letter == 'M' && TARGET_LITTLE_ENDIAN)
7869 || (letter == 'L' && TARGET_BIG_ENDIAN)
7872 else if (letter && letter != 'z' && letter != 'M' && letter != 'L')
7873 output_operand_lossage ("invalid use of '%%%c'", letter);
7874 /* We need to print $0 .. $31 for COP0 registers. */
7875 if (COP0_REG_P (regno))
7876 fprintf (file, "$%s", ®_names[regno][4]);
7878 fprintf (file, "%s", reg_names[regno]);
7884 output_address (plus_constant (XEXP (op, 0), 4));
7885 else if (letter && letter != 'z')
7886 output_operand_lossage ("invalid use of '%%%c'", letter);
7888 output_address (XEXP (op, 0));
7892 if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
7893 fputs (reg_names[GP_REG_FIRST], file);
7894 else if (letter && letter != 'z')
7895 output_operand_lossage ("invalid use of '%%%c'", letter);
7896 else if (CONST_GP_P (op))
7897 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
7899 output_addr_const (file, mips_strip_unspec_address (op));
7905 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
7908 mips_print_operand_address (FILE *file, rtx x)
7910 struct mips_address_info addr;
7912 if (mips_classify_address (&addr, x, word_mode, true))
7916 mips_print_operand (file, addr.offset, 0);
7917 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
7920 case ADDRESS_LO_SUM:
7921 mips_print_operand_reloc (file, addr.offset, SYMBOL_CONTEXT_MEM,
7923 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
7926 case ADDRESS_CONST_INT:
7927 output_addr_const (file, x);
7928 fprintf (file, "(%s)", reg_names[GP_REG_FIRST]);
7931 case ADDRESS_SYMBOLIC:
7932 output_addr_const (file, mips_strip_unspec_address (x));
7938 /* Implement TARGET_ENCODE_SECTION_INFO. */
7941 mips_encode_section_info (tree decl, rtx rtl, int first)
7943 default_encode_section_info (decl, rtl, first);
7945 if (TREE_CODE (decl) == FUNCTION_DECL)
7947 rtx symbol = XEXP (rtl, 0);
7948 tree type = TREE_TYPE (decl);
7950 /* Encode whether the symbol is short or long. */
7951 if ((TARGET_LONG_CALLS && !mips_near_type_p (type))
7952 || mips_far_type_p (type))
7953 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
7957 /* Implement TARGET_SELECT_RTX_SECTION. */
7960 mips_select_rtx_section (enum machine_mode mode, rtx x,
7961 unsigned HOST_WIDE_INT align)
7963 /* ??? Consider using mergeable small data sections. */
7964 if (mips_rtx_constant_in_small_data_p (mode))
7965 return get_named_section (NULL, ".sdata", 0);
7967 return default_elf_select_rtx_section (mode, x, align);
7970 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
7972 The complication here is that, with the combination TARGET_ABICALLS
7973 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
7974 absolute addresses, and should therefore not be included in the
7975 read-only part of a DSO. Handle such cases by selecting a normal
7976 data section instead of a read-only one. The logic apes that in
7977 default_function_rodata_section. */
7980 mips_function_rodata_section (tree decl)
7982 if (!TARGET_ABICALLS || TARGET_ABSOLUTE_ABICALLS || TARGET_GPWORD)
7983 return default_function_rodata_section (decl);
7985 if (decl && DECL_SECTION_NAME (decl))
7987 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7988 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
7990 char *rname = ASTRDUP (name);
7992 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
7994 else if (flag_function_sections
7995 && flag_data_sections
7996 && strncmp (name, ".text.", 6) == 0)
7998 char *rname = ASTRDUP (name);
7999 memcpy (rname + 1, "data", 4);
8000 return get_section (rname, SECTION_WRITE, decl);
8003 return data_section;
8006 /* Implement TARGET_IN_SMALL_DATA_P. */
8009 mips_in_small_data_p (const_tree decl)
8011 unsigned HOST_WIDE_INT size;
8013 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
8016 /* We don't yet generate small-data references for -mabicalls
8017 or VxWorks RTP code. See the related -G handling in
8018 mips_option_override. */
8019 if (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
8022 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
8026 /* Reject anything that isn't in a known small-data section. */
8027 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
8028 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
8031 /* If a symbol is defined externally, the assembler will use the
8032 usual -G rules when deciding how to implement macros. */
8033 if (mips_lo_relocs[SYMBOL_GP_RELATIVE] || !DECL_EXTERNAL (decl))
8036 else if (TARGET_EMBEDDED_DATA)
8038 /* Don't put constants into the small data section: we want them
8039 to be in ROM rather than RAM. */
8040 if (TREE_CODE (decl) != VAR_DECL)
8043 if (TREE_READONLY (decl)
8044 && !TREE_SIDE_EFFECTS (decl)
8045 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
8049 /* Enforce -mlocal-sdata. */
8050 if (!TARGET_LOCAL_SDATA && !TREE_PUBLIC (decl))
8053 /* Enforce -mextern-sdata. */
8054 if (!TARGET_EXTERN_SDATA && DECL_P (decl))
8056 if (DECL_EXTERNAL (decl))
8058 if (DECL_COMMON (decl) && DECL_INITIAL (decl) == NULL)
8062 /* We have traditionally not treated zero-sized objects as small data,
8063 so this is now effectively part of the ABI. */
8064 size = int_size_in_bytes (TREE_TYPE (decl));
8065 return size > 0 && size <= mips_small_data_threshold;
8068 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
8069 anchors for small data: the GP register acts as an anchor in that
8070 case. We also don't want to use them for PC-relative accesses,
8071 where the PC acts as an anchor. */
8074 mips_use_anchors_for_symbol_p (const_rtx symbol)
8076 switch (mips_classify_symbol (symbol, SYMBOL_CONTEXT_MEM))
8078 case SYMBOL_PC_RELATIVE:
8079 case SYMBOL_GP_RELATIVE:
8083 return default_use_anchors_for_symbol_p (symbol);
8087 /* The MIPS debug format wants all automatic variables and arguments
8088 to be in terms of the virtual frame pointer (stack pointer before
8089 any adjustment in the function), while the MIPS 3.0 linker wants
8090 the frame pointer to be the stack pointer after the initial
8091 adjustment. So, we do the adjustment here. The arg pointer (which
8092 is eliminated) points to the virtual frame pointer, while the frame
8093 pointer (which may be eliminated) points to the stack pointer after
8094 the initial adjustments. */
8097 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
8099 rtx offset2 = const0_rtx;
8100 rtx reg = eliminate_constant_term (addr, &offset2);
8103 offset = INTVAL (offset2);
8105 if (reg == stack_pointer_rtx
8106 || reg == frame_pointer_rtx
8107 || reg == hard_frame_pointer_rtx)
8109 offset -= cfun->machine->frame.total_size;
8110 if (reg == hard_frame_pointer_rtx)
8111 offset += cfun->machine->frame.hard_frame_pointer_offset;
8117 /* Implement ASM_OUTPUT_EXTERNAL. */
8120 mips_output_external (FILE *file, tree decl, const char *name)
8122 default_elf_asm_output_external (file, decl, name);
8124 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
8125 set in order to avoid putting out names that are never really
8127 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
8129 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
8131 /* When using assembler macros, emit .extern directives for
8132 all small-data externs so that the assembler knows how
8135 In most cases it would be safe (though pointless) to emit
8136 .externs for other symbols too. One exception is when an
8137 object is within the -G limit but declared by the user to
8138 be in a section other than .sbss or .sdata. */
8139 fputs ("\t.extern\t", file);
8140 assemble_name (file, name);
8141 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n",
8142 int_size_in_bytes (TREE_TYPE (decl)));
8147 /* Implement TARGET_ASM_OUTPUT_SOURCE_FILENAME. */
8150 mips_output_filename (FILE *stream, const char *name)
8152 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
8154 if (write_symbols == DWARF2_DEBUG)
8156 else if (mips_output_filename_first_time)
8158 mips_output_filename_first_time = 0;
8159 num_source_filenames += 1;
8160 current_function_file = name;
8161 fprintf (stream, "\t.file\t%d ", num_source_filenames);
8162 output_quoted_string (stream, name);
8163 putc ('\n', stream);
8165 /* If we are emitting stabs, let dbxout.c handle this (except for
8166 the mips_output_filename_first_time case). */
8167 else if (write_symbols == DBX_DEBUG)
8169 else if (name != current_function_file
8170 && strcmp (name, current_function_file) != 0)
8172 num_source_filenames += 1;
8173 current_function_file = name;
8174 fprintf (stream, "\t.file\t%d ", num_source_filenames);
8175 output_quoted_string (stream, name);
8176 putc ('\n', stream);
8180 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
8182 static void ATTRIBUTE_UNUSED
8183 mips_output_dwarf_dtprel (FILE *file, int size, rtx x)
8188 fputs ("\t.dtprelword\t", file);
8192 fputs ("\t.dtpreldword\t", file);
8198 output_addr_const (file, x);
8199 fputs ("+0x8000", file);
8202 /* Implement TARGET_DWARF_REGISTER_SPAN. */
8205 mips_dwarf_register_span (rtx reg)
8208 enum machine_mode mode;
8210 /* By default, GCC maps increasing register numbers to increasing
8211 memory locations, but paired FPRs are always little-endian,
8212 regardless of the prevailing endianness. */
8213 mode = GET_MODE (reg);
8214 if (FP_REG_P (REGNO (reg))
8215 && TARGET_BIG_ENDIAN
8216 && MAX_FPRS_PER_FMT > 1
8217 && GET_MODE_SIZE (mode) > UNITS_PER_FPREG)
8219 gcc_assert (GET_MODE_SIZE (mode) == UNITS_PER_HWFPVALUE);
8220 high = mips_subword (reg, true);
8221 low = mips_subword (reg, false);
8222 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, high, low));
8228 /* Implement ASM_OUTPUT_ASCII. */
8231 mips_output_ascii (FILE *stream, const char *string, size_t len)
8237 fprintf (stream, "\t.ascii\t\"");
8238 for (i = 0; i < len; i++)
8242 c = (unsigned char) string[i];
8245 if (c == '\\' || c == '\"')
8247 putc ('\\', stream);
8255 fprintf (stream, "\\%03o", c);
8259 if (cur_pos > 72 && i+1 < len)
8262 fprintf (stream, "\"\n\t.ascii\t\"");
8265 fprintf (stream, "\"\n");
8268 /* Return the pseudo-op for full SYMBOL_(D)TPREL address *ADDR.
8269 Update *ADDR with the operand that should be printed. */
8272 mips_output_tls_reloc_directive (rtx *addr)
8274 enum mips_symbol_type type;
8276 type = mips_classify_symbolic_expression (*addr, SYMBOL_CONTEXT_LEA);
8277 *addr = mips_strip_unspec_address (*addr);
8281 return Pmode == SImode ? ".dtprelword\t%0" : ".dtpreldword\t%0";
8284 return Pmode == SImode ? ".tprelword\t%0" : ".tpreldword\t%0";
8291 /* Emit either a label, .comm, or .lcomm directive. When using assembler
8292 macros, mark the symbol as written so that mips_asm_output_external
8293 won't emit an .extern for it. STREAM is the output file, NAME is the
8294 name of the symbol, INIT_STRING is the string that should be written
8295 before the symbol and FINAL_STRING is the string that should be
8296 written after it. FINAL_STRING is a printf format that consumes the
8297 remaining arguments. */
8300 mips_declare_object (FILE *stream, const char *name, const char *init_string,
8301 const char *final_string, ...)
8305 fputs (init_string, stream);
8306 assemble_name (stream, name);
8307 va_start (ap, final_string);
8308 vfprintf (stream, final_string, ap);
8311 if (!TARGET_EXPLICIT_RELOCS)
8313 tree name_tree = get_identifier (name);
8314 TREE_ASM_WRITTEN (name_tree) = 1;
8318 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
8319 NAME is the name of the object and ALIGN is the required alignment
8320 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
8321 alignment argument. */
8324 mips_declare_common_object (FILE *stream, const char *name,
8325 const char *init_string,
8326 unsigned HOST_WIDE_INT size,
8327 unsigned int align, bool takes_alignment_p)
8329 if (!takes_alignment_p)
8331 size += (align / BITS_PER_UNIT) - 1;
8332 size -= size % (align / BITS_PER_UNIT);
8333 mips_declare_object (stream, name, init_string,
8334 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
8337 mips_declare_object (stream, name, init_string,
8338 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
8339 size, align / BITS_PER_UNIT);
8342 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
8343 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
8346 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
8347 unsigned HOST_WIDE_INT size,
8350 /* If the target wants uninitialized const declarations in
8351 .rdata then don't put them in .comm. */
8352 if (TARGET_EMBEDDED_DATA
8353 && TARGET_UNINIT_CONST_IN_RODATA
8354 && TREE_CODE (decl) == VAR_DECL
8355 && TREE_READONLY (decl)
8356 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
8358 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
8359 targetm.asm_out.globalize_label (stream, name);
8361 switch_to_section (readonly_data_section);
8362 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
8363 mips_declare_object (stream, name, "",
8364 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
8368 mips_declare_common_object (stream, name, "\n\t.comm\t",
8372 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8373 extern int size_directive_output;
8375 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
8376 definitions except that it uses mips_declare_object to emit the label. */
8379 mips_declare_object_name (FILE *stream, const char *name,
8380 tree decl ATTRIBUTE_UNUSED)
8382 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8383 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
8386 size_directive_output = 0;
8387 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
8391 size_directive_output = 1;
8392 size = int_size_in_bytes (TREE_TYPE (decl));
8393 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8396 mips_declare_object (stream, name, "", ":\n");
8399 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
8402 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
8406 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
8407 if (!flag_inhibit_size_directive
8408 && DECL_SIZE (decl) != 0
8411 && DECL_INITIAL (decl) == error_mark_node
8412 && !size_directive_output)
8416 size_directive_output = 1;
8417 size = int_size_in_bytes (TREE_TYPE (decl));
8418 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8423 /* Return the FOO in the name of the ".mdebug.FOO" section associated
8424 with the current ABI. */
8427 mips_mdebug_abi_name (void)
8440 return TARGET_64BIT ? "eabi64" : "eabi32";
8446 /* Implement TARGET_ASM_FILE_START. */
8449 mips_file_start (void)
8451 default_file_start ();
8453 /* Generate a special section to describe the ABI switches used to
8454 produce the resultant binary. This is unnecessary on IRIX and
8455 causes unwanted warnings from the native linker. */
8458 /* Record the ABI itself. Modern versions of binutils encode
8459 this information in the ELF header flags, but GDB needs the
8460 information in order to correctly debug binaries produced by
8461 older binutils. See the function mips_gdbarch_init in
8463 fprintf (asm_out_file, "\t.section .mdebug.%s\n\t.previous\n",
8464 mips_mdebug_abi_name ());
8466 /* There is no ELF header flag to distinguish long32 forms of the
8467 EABI from long64 forms. Emit a special section to help tools
8468 such as GDB. Do the same for o64, which is sometimes used with
8470 if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
8471 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n"
8472 "\t.previous\n", TARGET_LONG64 ? 64 : 32);
8474 #ifdef HAVE_AS_GNU_ATTRIBUTE
8478 /* No floating-point operations, -mno-float. */
8479 if (TARGET_NO_FLOAT)
8481 /* Soft-float code, -msoft-float. */
8482 else if (!TARGET_HARD_FLOAT_ABI)
8484 /* Single-float code, -msingle-float. */
8485 else if (!TARGET_DOUBLE_FLOAT)
8487 /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64. */
8488 else if (!TARGET_64BIT && TARGET_FLOAT64)
8490 /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */
8494 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n", attr);
8499 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
8500 if (TARGET_ABICALLS)
8502 fprintf (asm_out_file, "\t.abicalls\n");
8503 if (TARGET_ABICALLS_PIC0)
8504 fprintf (asm_out_file, "\t.option\tpic0\n");
8507 if (flag_verbose_asm)
8508 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
8510 mips_small_data_threshold, mips_arch_info->name, mips_isa);
8513 /* Implement TARGET_ASM_CODE_END. */
8516 mips_code_end (void)
8518 if (mips_need_mips16_rdhwr_p)
8519 mips_output_mips16_rdhwr ();
8522 /* Make the last instruction frame-related and note that it performs
8523 the operation described by FRAME_PATTERN. */
8526 mips_set_frame_expr (rtx frame_pattern)
8530 insn = get_last_insn ();
8531 RTX_FRAME_RELATED_P (insn) = 1;
8532 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
8537 /* Return a frame-related rtx that stores REG at MEM.
8538 REG must be a single register. */
8541 mips_frame_set (rtx mem, rtx reg)
8545 set = gen_rtx_SET (VOIDmode, mem, reg);
8546 RTX_FRAME_RELATED_P (set) = 1;
8551 /* Record that the epilogue has restored call-saved register REG. */
8554 mips_add_cfa_restore (rtx reg)
8556 mips_epilogue.cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg,
8557 mips_epilogue.cfa_restores);
8560 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
8561 mips16e_s2_s8_regs[X], it must also save the registers in indexes
8562 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
8563 static const unsigned char mips16e_s2_s8_regs[] = {
8564 30, 23, 22, 21, 20, 19, 18
8566 static const unsigned char mips16e_a0_a3_regs[] = {
8570 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
8571 ordered from the uppermost in memory to the lowest in memory. */
8572 static const unsigned char mips16e_save_restore_regs[] = {
8573 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
8576 /* Return the index of the lowest X in the range [0, SIZE) for which
8577 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
8580 mips16e_find_first_register (unsigned int mask, const unsigned char *regs,
8585 for (i = 0; i < size; i++)
8586 if (BITSET_P (mask, regs[i]))
8592 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
8593 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
8594 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
8595 is true for all indexes (X, SIZE). */
8598 mips16e_mask_registers (unsigned int *mask_ptr, const unsigned char *regs,
8599 unsigned int size, unsigned int *num_regs_ptr)
8603 i = mips16e_find_first_register (*mask_ptr, regs, size);
8604 for (i++; i < size; i++)
8605 if (!BITSET_P (*mask_ptr, regs[i]))
8608 *mask_ptr |= 1 << regs[i];
8612 /* Return a simplified form of X using the register values in REG_VALUES.
8613 REG_VALUES[R] is the last value assigned to hard register R, or null
8614 if R has not been modified.
8616 This function is rather limited, but is good enough for our purposes. */
8619 mips16e_collect_propagate_value (rtx x, rtx *reg_values)
8621 x = avoid_constant_pool_reference (x);
8625 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
8626 return simplify_gen_unary (GET_CODE (x), GET_MODE (x),
8627 x0, GET_MODE (XEXP (x, 0)));
8630 if (ARITHMETIC_P (x))
8632 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
8633 rtx x1 = mips16e_collect_propagate_value (XEXP (x, 1), reg_values);
8634 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), x0, x1);
8638 && reg_values[REGNO (x)]
8639 && !rtx_unstable_p (reg_values[REGNO (x)]))
8640 return reg_values[REGNO (x)];
8645 /* Return true if (set DEST SRC) stores an argument register into its
8646 caller-allocated save slot, storing the number of that argument
8647 register in *REGNO_PTR if so. REG_VALUES is as for
8648 mips16e_collect_propagate_value. */
8651 mips16e_collect_argument_save_p (rtx dest, rtx src, rtx *reg_values,
8652 unsigned int *regno_ptr)
8654 unsigned int argno, regno;
8655 HOST_WIDE_INT offset, required_offset;
8658 /* Check that this is a word-mode store. */
8659 if (!MEM_P (dest) || !REG_P (src) || GET_MODE (dest) != word_mode)
8662 /* Check that the register being saved is an unmodified argument
8664 regno = REGNO (src);
8665 if (!IN_RANGE (regno, GP_ARG_FIRST, GP_ARG_LAST) || reg_values[regno])
8667 argno = regno - GP_ARG_FIRST;
8669 /* Check whether the address is an appropriate stack-pointer or
8670 frame-pointer access. */
8671 addr = mips16e_collect_propagate_value (XEXP (dest, 0), reg_values);
8672 mips_split_plus (addr, &base, &offset);
8673 required_offset = cfun->machine->frame.total_size + argno * UNITS_PER_WORD;
8674 if (base == hard_frame_pointer_rtx)
8675 required_offset -= cfun->machine->frame.hard_frame_pointer_offset;
8676 else if (base != stack_pointer_rtx)
8678 if (offset != required_offset)
8685 /* A subroutine of mips_expand_prologue, called only when generating
8686 MIPS16e SAVE instructions. Search the start of the function for any
8687 instructions that save argument registers into their caller-allocated
8688 save slots. Delete such instructions and return a value N such that
8689 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
8690 instructions redundant. */
8693 mips16e_collect_argument_saves (void)
8695 rtx reg_values[FIRST_PSEUDO_REGISTER];
8696 rtx insn, next, set, dest, src;
8697 unsigned int nargs, regno;
8699 push_topmost_sequence ();
8701 memset (reg_values, 0, sizeof (reg_values));
8702 for (insn = get_insns (); insn; insn = next)
8704 next = NEXT_INSN (insn);
8705 if (NOTE_P (insn) || DEBUG_INSN_P (insn))
8711 set = PATTERN (insn);
8712 if (GET_CODE (set) != SET)
8715 dest = SET_DEST (set);
8716 src = SET_SRC (set);
8717 if (mips16e_collect_argument_save_p (dest, src, reg_values, ®no))
8719 if (!BITSET_P (cfun->machine->frame.mask, regno))
8722 nargs = MAX (nargs, (regno - GP_ARG_FIRST) + 1);
8725 else if (REG_P (dest) && GET_MODE (dest) == word_mode)
8726 reg_values[REGNO (dest)]
8727 = mips16e_collect_propagate_value (src, reg_values);
8731 pop_topmost_sequence ();
8736 /* Return a move between register REGNO and memory location SP + OFFSET.
8737 REG_PARM_P is true if SP + OFFSET belongs to REG_PARM_STACK_SPACE.
8738 Make the move a load if RESTORE_P, otherwise make it a store. */
8741 mips16e_save_restore_reg (bool restore_p, bool reg_parm_p,
8742 HOST_WIDE_INT offset, unsigned int regno)
8746 mem = gen_frame_mem (SImode, plus_constant (stack_pointer_rtx, offset));
8747 reg = gen_rtx_REG (SImode, regno);
8750 mips_add_cfa_restore (reg);
8751 return gen_rtx_SET (VOIDmode, reg, mem);
8754 return gen_rtx_SET (VOIDmode, mem, reg);
8755 return mips_frame_set (mem, reg);
8758 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
8759 The instruction must:
8761 - Allocate or deallocate SIZE bytes in total; SIZE is known
8764 - Save or restore as many registers in *MASK_PTR as possible.
8765 The instruction saves the first registers at the top of the
8766 allocated area, with the other registers below it.
8768 - Save NARGS argument registers above the allocated area.
8770 (NARGS is always zero if RESTORE_P.)
8772 The SAVE and RESTORE instructions cannot save and restore all general
8773 registers, so there may be some registers left over for the caller to
8774 handle. Destructively modify *MASK_PTR so that it contains the registers
8775 that still need to be saved or restored. The caller can save these
8776 registers in the memory immediately below *OFFSET_PTR, which is a
8777 byte offset from the bottom of the allocated stack area. */
8780 mips16e_build_save_restore (bool restore_p, unsigned int *mask_ptr,
8781 HOST_WIDE_INT *offset_ptr, unsigned int nargs,
8785 HOST_WIDE_INT offset, top_offset;
8786 unsigned int i, regno;
8789 gcc_assert (cfun->machine->frame.num_fp == 0);
8791 /* Calculate the number of elements in the PARALLEL. We need one element
8792 for the stack adjustment, one for each argument register save, and one
8793 for each additional register move. */
8795 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
8796 if (BITSET_P (*mask_ptr, mips16e_save_restore_regs[i]))
8799 /* Create the final PARALLEL. */
8800 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (n));
8803 /* Add the stack pointer adjustment. */
8804 set = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8805 plus_constant (stack_pointer_rtx,
8806 restore_p ? size : -size));
8807 RTX_FRAME_RELATED_P (set) = 1;
8808 XVECEXP (pattern, 0, n++) = set;
8810 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8811 top_offset = restore_p ? size : 0;
8813 /* Save the arguments. */
8814 for (i = 0; i < nargs; i++)
8816 offset = top_offset + i * UNITS_PER_WORD;
8817 set = mips16e_save_restore_reg (restore_p, true, offset,
8819 XVECEXP (pattern, 0, n++) = set;
8822 /* Then fill in the other register moves. */
8823 offset = top_offset;
8824 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
8826 regno = mips16e_save_restore_regs[i];
8827 if (BITSET_P (*mask_ptr, regno))
8829 offset -= UNITS_PER_WORD;
8830 set = mips16e_save_restore_reg (restore_p, false, offset, regno);
8831 XVECEXP (pattern, 0, n++) = set;
8832 *mask_ptr &= ~(1 << regno);
8836 /* Tell the caller what offset it should use for the remaining registers. */
8837 *offset_ptr = size + (offset - top_offset);
8839 gcc_assert (n == XVECLEN (pattern, 0));
8844 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
8845 pointer. Return true if PATTERN matches the kind of instruction
8846 generated by mips16e_build_save_restore. If INFO is nonnull,
8847 initialize it when returning true. */
8850 mips16e_save_restore_pattern_p (rtx pattern, HOST_WIDE_INT adjust,
8851 struct mips16e_save_restore_info *info)
8853 unsigned int i, nargs, mask, extra;
8854 HOST_WIDE_INT top_offset, save_offset, offset;
8855 rtx set, reg, mem, base;
8858 if (!GENERATE_MIPS16E_SAVE_RESTORE)
8861 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8862 top_offset = adjust > 0 ? adjust : 0;
8864 /* Interpret all other members of the PARALLEL. */
8865 save_offset = top_offset - UNITS_PER_WORD;
8869 for (n = 1; n < XVECLEN (pattern, 0); n++)
8871 /* Check that we have a SET. */
8872 set = XVECEXP (pattern, 0, n);
8873 if (GET_CODE (set) != SET)
8876 /* Check that the SET is a load (if restoring) or a store
8878 mem = adjust > 0 ? SET_SRC (set) : SET_DEST (set);
8882 /* Check that the address is the sum of the stack pointer and a
8883 possibly-zero constant offset. */
8884 mips_split_plus (XEXP (mem, 0), &base, &offset);
8885 if (base != stack_pointer_rtx)
8888 /* Check that SET's other operand is a register. */
8889 reg = adjust > 0 ? SET_DEST (set) : SET_SRC (set);
8893 /* Check for argument saves. */
8894 if (offset == top_offset + nargs * UNITS_PER_WORD
8895 && REGNO (reg) == GP_ARG_FIRST + nargs)
8897 else if (offset == save_offset)
8899 while (mips16e_save_restore_regs[i++] != REGNO (reg))
8900 if (i == ARRAY_SIZE (mips16e_save_restore_regs))
8903 mask |= 1 << REGNO (reg);
8904 save_offset -= UNITS_PER_WORD;
8910 /* Check that the restrictions on register ranges are met. */
8912 mips16e_mask_registers (&mask, mips16e_s2_s8_regs,
8913 ARRAY_SIZE (mips16e_s2_s8_regs), &extra);
8914 mips16e_mask_registers (&mask, mips16e_a0_a3_regs,
8915 ARRAY_SIZE (mips16e_a0_a3_regs), &extra);
8919 /* Make sure that the topmost argument register is not saved twice.
8920 The checks above ensure that the same is then true for the other
8921 argument registers. */
8922 if (nargs > 0 && BITSET_P (mask, GP_ARG_FIRST + nargs - 1))
8925 /* Pass back information, if requested. */
8928 info->nargs = nargs;
8930 info->size = (adjust > 0 ? adjust : -adjust);
8936 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
8937 for the register range [MIN_REG, MAX_REG]. Return a pointer to
8938 the null terminator. */
8941 mips16e_add_register_range (char *s, unsigned int min_reg,
8942 unsigned int max_reg)
8944 if (min_reg != max_reg)
8945 s += sprintf (s, ",%s-%s", reg_names[min_reg], reg_names[max_reg]);
8947 s += sprintf (s, ",%s", reg_names[min_reg]);
8951 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
8952 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
8955 mips16e_output_save_restore (rtx pattern, HOST_WIDE_INT adjust)
8957 static char buffer[300];
8959 struct mips16e_save_restore_info info;
8960 unsigned int i, end;
8963 /* Parse the pattern. */
8964 if (!mips16e_save_restore_pattern_p (pattern, adjust, &info))
8967 /* Add the mnemonic. */
8968 s = strcpy (buffer, adjust > 0 ? "restore\t" : "save\t");
8971 /* Save the arguments. */
8973 s += sprintf (s, "%s-%s,", reg_names[GP_ARG_FIRST],
8974 reg_names[GP_ARG_FIRST + info.nargs - 1]);
8975 else if (info.nargs == 1)
8976 s += sprintf (s, "%s,", reg_names[GP_ARG_FIRST]);
8978 /* Emit the amount of stack space to allocate or deallocate. */
8979 s += sprintf (s, "%d", (int) info.size);
8981 /* Save or restore $16. */
8982 if (BITSET_P (info.mask, 16))
8983 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 16]);
8985 /* Save or restore $17. */
8986 if (BITSET_P (info.mask, 17))
8987 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 17]);
8989 /* Save or restore registers in the range $s2...$s8, which
8990 mips16e_s2_s8_regs lists in decreasing order. Note that this
8991 is a software register range; the hardware registers are not
8992 numbered consecutively. */
8993 end = ARRAY_SIZE (mips16e_s2_s8_regs);
8994 i = mips16e_find_first_register (info.mask, mips16e_s2_s8_regs, end);
8996 s = mips16e_add_register_range (s, mips16e_s2_s8_regs[end - 1],
8997 mips16e_s2_s8_regs[i]);
8999 /* Save or restore registers in the range $a0...$a3. */
9000 end = ARRAY_SIZE (mips16e_a0_a3_regs);
9001 i = mips16e_find_first_register (info.mask, mips16e_a0_a3_regs, end);
9003 s = mips16e_add_register_range (s, mips16e_a0_a3_regs[i],
9004 mips16e_a0_a3_regs[end - 1]);
9006 /* Save or restore $31. */
9007 if (BITSET_P (info.mask, RETURN_ADDR_REGNUM))
9008 s += sprintf (s, ",%s", reg_names[RETURN_ADDR_REGNUM]);
9013 /* Return true if the current function returns its value in a floating-point
9014 register in MIPS16 mode. */
9017 mips16_cfun_returns_in_fpr_p (void)
9019 tree return_type = DECL_RESULT (current_function_decl);
9020 return (TARGET_MIPS16
9021 && TARGET_HARD_FLOAT_ABI
9022 && !aggregate_value_p (return_type, current_function_decl)
9023 && mips_return_mode_in_fpr_p (DECL_MODE (return_type)));
9026 /* Return true if predicate PRED is true for at least one instruction.
9027 Cache the result in *CACHE, and assume that the result is true
9028 if *CACHE is already true. */
9031 mips_find_gp_ref (bool *cache, bool (*pred) (rtx))
9037 push_topmost_sequence ();
9038 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9039 if (USEFUL_INSN_P (insn) && pred (insn))
9044 pop_topmost_sequence ();
9049 /* Return true if INSN refers to the global pointer in an "inflexible" way.
9050 See mips_cfun_has_inflexible_gp_ref_p for details. */
9053 mips_insn_has_inflexible_gp_ref_p (rtx insn)
9055 /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE
9056 indicate that the target could be a traditional MIPS
9057 lazily-binding stub. */
9058 return find_reg_fusage (insn, USE, pic_offset_table_rtx);
9061 /* Return true if the current function refers to the global pointer
9062 in a way that forces $28 to be valid. This means that we can't
9063 change the choice of global pointer, even for NewABI code.
9065 One example of this (and one which needs several checks) is that
9066 $28 must be valid when calling traditional MIPS lazy-binding stubs.
9067 (This restriction does not apply to PLTs.) */
9070 mips_cfun_has_inflexible_gp_ref_p (void)
9072 /* If the function has a nonlocal goto, $28 must hold the correct
9073 global pointer for the target function. That is, the target
9074 of the goto implicitly uses $28. */
9075 if (crtl->has_nonlocal_goto)
9078 if (TARGET_ABICALLS_PIC2)
9080 /* Symbolic accesses implicitly use the global pointer unless
9081 -mexplicit-relocs is in effect. JAL macros to symbolic addresses
9082 might go to traditional MIPS lazy-binding stubs. */
9083 if (!TARGET_EXPLICIT_RELOCS)
9086 /* FUNCTION_PROFILER includes a JAL to _mcount, which again
9087 can be lazily-bound. */
9091 /* MIPS16 functions that return in FPRs need to call an
9092 external libgcc routine. This call is only made explict
9093 during mips_expand_epilogue, and it too might be lazily bound. */
9094 if (mips16_cfun_returns_in_fpr_p ())
9098 return mips_find_gp_ref (&cfun->machine->has_inflexible_gp_insn_p,
9099 mips_insn_has_inflexible_gp_ref_p);
9102 /* Return true if INSN refers to the global pointer in a "flexible" way.
9103 See mips_cfun_has_flexible_gp_ref_p for details. */
9106 mips_insn_has_flexible_gp_ref_p (rtx insn)
9108 return (get_attr_got (insn) != GOT_UNSET
9109 || mips_small_data_pattern_p (PATTERN (insn))
9110 || reg_overlap_mentioned_p (pic_offset_table_rtx, PATTERN (insn)));
9113 /* Return true if the current function references the global pointer,
9114 but if those references do not inherently require the global pointer
9115 to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */
9118 mips_cfun_has_flexible_gp_ref_p (void)
9120 /* Reload can sometimes introduce constant pool references
9121 into a function that otherwise didn't need them. For example,
9122 suppose we have an instruction like:
9124 (set (reg:DF R1) (float:DF (reg:SI R2)))
9126 If R2 turns out to be a constant such as 1, the instruction may
9127 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
9128 the option of using this constant if R2 doesn't get allocated
9131 In cases like these, reload will have added the constant to the
9132 pool but no instruction will yet refer to it. */
9133 if (TARGET_ABICALLS_PIC2 && !reload_completed && crtl->uses_const_pool)
9136 return mips_find_gp_ref (&cfun->machine->has_flexible_gp_insn_p,
9137 mips_insn_has_flexible_gp_ref_p);
9140 /* Return the register that should be used as the global pointer
9141 within this function. Return INVALID_REGNUM if the function
9142 doesn't need a global pointer. */
9145 mips_global_pointer (void)
9149 /* $gp is always available unless we're using a GOT. */
9150 if (!TARGET_USE_GOT)
9151 return GLOBAL_POINTER_REGNUM;
9153 /* If there are inflexible references to $gp, we must use the
9154 standard register. */
9155 if (mips_cfun_has_inflexible_gp_ref_p ())
9156 return GLOBAL_POINTER_REGNUM;
9158 /* If there are no current references to $gp, then the only uses
9159 we can introduce later are those involved in long branches. */
9160 if (TARGET_ABSOLUTE_JUMPS && !mips_cfun_has_flexible_gp_ref_p ())
9161 return INVALID_REGNUM;
9163 /* If the global pointer is call-saved, try to use a call-clobbered
9165 if (TARGET_CALL_SAVED_GP && current_function_is_leaf)
9166 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
9167 if (!df_regs_ever_live_p (regno)
9168 && call_really_used_regs[regno]
9169 && !fixed_regs[regno]
9170 && regno != PIC_FUNCTION_ADDR_REGNUM)
9173 return GLOBAL_POINTER_REGNUM;
9176 /* Return true if the current function's prologue must load the global
9177 pointer value into pic_offset_table_rtx and store the same value in
9178 the function's cprestore slot (if any).
9180 One problem we have to deal with is that, when emitting GOT-based
9181 position independent code, long-branch sequences will need to load
9182 the address of the branch target from the GOT. We don't know until
9183 the very end of compilation whether (and where) the function needs
9184 long branches, so we must ensure that _any_ branch can access the
9185 global pointer in some form. However, we do not want to pessimize
9186 the usual case in which all branches are short.
9188 We handle this as follows:
9190 (1) During reload, we set cfun->machine->global_pointer to
9191 INVALID_REGNUM if we _know_ that the current function
9192 doesn't need a global pointer. This is only valid if
9193 long branches don't need the GOT.
9195 Otherwise, we assume that we might need a global pointer
9196 and pick an appropriate register.
9198 (2) If cfun->machine->global_pointer != INVALID_REGNUM,
9199 we ensure that the global pointer is available at every
9200 block boundary bar entry and exit. We do this in one of two ways:
9202 - If the function has a cprestore slot, we ensure that this
9203 slot is valid at every branch. However, as explained in
9204 point (6) below, there is no guarantee that pic_offset_table_rtx
9205 itself is valid if new uses of the global pointer are introduced
9206 after the first post-epilogue split.
9208 We guarantee that the cprestore slot is valid by loading it
9209 into a fake register, CPRESTORE_SLOT_REGNUM. We then make
9210 this register live at every block boundary bar function entry
9211 and exit. It is then invalid to move the load (and thus the
9212 preceding store) across a block boundary.
9214 - If the function has no cprestore slot, we guarantee that
9215 pic_offset_table_rtx itself is valid at every branch.
9217 See mips_eh_uses for the handling of the register liveness.
9219 (3) During prologue and epilogue generation, we emit "ghost"
9220 placeholder instructions to manipulate the global pointer.
9222 (4) During prologue generation, we set cfun->machine->must_initialize_gp_p
9223 and cfun->machine->must_restore_gp_when_clobbered_p if we already know
9224 that the function needs a global pointer. (There is no need to set
9225 them earlier than this, and doing it as late as possible leads to
9226 fewer false positives.)
9228 (5) If cfun->machine->must_initialize_gp_p is true during a
9229 split_insns pass, we split the ghost instructions into real
9230 instructions. These split instructions can then be optimized in
9231 the usual way. Otherwise, we keep the ghost instructions intact,
9232 and optimize for the case where they aren't needed. We still
9233 have the option of splitting them later, if we need to introduce
9234 new uses of the global pointer.
9236 For example, the scheduler ignores a ghost instruction that
9237 stores $28 to the stack, but it handles the split form of
9238 the ghost instruction as an ordinary store.
9240 (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p
9241 is true during the first post-epilogue split_insns pass, we split
9242 calls and restore_gp patterns into instructions that explicitly
9243 load pic_offset_table_rtx from the cprestore slot. Otherwise,
9244 we split these patterns into instructions that _don't_ load from
9247 If cfun->machine->must_restore_gp_when_clobbered_p is true at the
9248 time of the split, then any instructions that exist at that time
9249 can make free use of pic_offset_table_rtx. However, if we want
9250 to introduce new uses of the global pointer after the split,
9251 we must explicitly load the value from the cprestore slot, since
9252 pic_offset_table_rtx itself might not be valid at a given point
9255 The idea is that we want to be able to delete redundant
9256 loads from the cprestore slot in the usual case where no
9257 long branches are needed.
9259 (7) If cfun->machine->must_initialize_gp_p is still false at the end
9260 of md_reorg, we decide whether the global pointer is needed for
9261 long branches. If so, we set cfun->machine->must_initialize_gp_p
9262 to true and split the ghost instructions into real instructions
9265 Note that the ghost instructions must have a zero length for three reasons:
9267 - Giving the length of the underlying $gp sequence might cause
9268 us to use long branches in cases where they aren't really needed.
9270 - They would perturb things like alignment calculations.
9272 - More importantly, the hazard detection in md_reorg relies on
9273 empty instructions having a zero length.
9275 If we find a long branch and split the ghost instructions at the
9276 end of md_reorg, the split could introduce more long branches.
9277 That isn't a problem though, because we still do the split before
9278 the final shorten_branches pass.
9280 This is extremely ugly, but it seems like the best compromise between
9281 correctness and efficiency. */
9284 mips_must_initialize_gp_p (void)
9286 return cfun->machine->must_initialize_gp_p;
9289 /* Return true if REGNO is a register that is ordinarily call-clobbered
9290 but must nevertheless be preserved by an interrupt handler. */
9293 mips_interrupt_extra_call_saved_reg_p (unsigned int regno)
9295 if (MD_REG_P (regno))
9298 if (TARGET_DSP && DSP_ACC_REG_P (regno))
9301 if (GP_REG_P (regno) && !cfun->machine->use_shadow_register_set_p)
9303 /* $0 is hard-wired. */
9304 if (regno == GP_REG_FIRST)
9307 /* The interrupt handler can treat kernel registers as
9308 scratch registers. */
9309 if (KERNEL_REG_P (regno))
9312 /* The function will return the stack pointer to its original value
9314 if (regno == STACK_POINTER_REGNUM)
9317 /* Otherwise, return true for registers that aren't ordinarily
9319 return call_really_used_regs[regno];
9325 /* Return true if the current function should treat register REGNO
9329 mips_cfun_call_saved_reg_p (unsigned int regno)
9331 /* If the user makes an ordinarily-call-saved register global,
9332 that register is no longer call-saved. */
9333 if (global_regs[regno])
9336 /* Interrupt handlers need to save extra registers. */
9337 if (cfun->machine->interrupt_handler_p
9338 && mips_interrupt_extra_call_saved_reg_p (regno))
9341 /* call_insns preserve $28 unless they explicitly say otherwise,
9342 so call_really_used_regs[] treats $28 as call-saved. However,
9343 we want the ABI property rather than the default call_insn
9345 return (regno == GLOBAL_POINTER_REGNUM
9346 ? TARGET_CALL_SAVED_GP
9347 : !call_really_used_regs[regno]);
9350 /* Return true if the function body might clobber register REGNO.
9351 We know that REGNO is call-saved. */
9354 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno)
9356 /* Some functions should be treated as clobbering all call-saved
9358 if (crtl->saves_all_registers)
9361 /* DF handles cases where a register is explicitly referenced in
9362 the rtl. Incoming values are passed in call-clobbered registers,
9363 so we can assume that any live call-saved register is set within
9365 if (df_regs_ever_live_p (regno))
9368 /* Check for registers that are clobbered by FUNCTION_PROFILER.
9369 These clobbers are not explicit in the rtl. */
9370 if (crtl->profile && MIPS_SAVE_REG_FOR_PROFILING_P (regno))
9373 /* If we're using a call-saved global pointer, the function's
9374 prologue will need to set it up. */
9375 if (cfun->machine->global_pointer == regno)
9378 /* The function's prologue will need to set the frame pointer if
9379 frame_pointer_needed. */
9380 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
9383 /* If a MIPS16 function returns a value in FPRs, its epilogue
9384 will need to call an external libgcc routine. This yet-to-be
9385 generated call_insn will clobber $31. */
9386 if (regno == RETURN_ADDR_REGNUM && mips16_cfun_returns_in_fpr_p ())
9389 /* If REGNO is ordinarily call-clobbered, we must assume that any
9390 called function could modify it. */
9391 if (cfun->machine->interrupt_handler_p
9392 && !current_function_is_leaf
9393 && mips_interrupt_extra_call_saved_reg_p (regno))
9399 /* Return true if the current function must save register REGNO. */
9402 mips_save_reg_p (unsigned int regno)
9404 if (mips_cfun_call_saved_reg_p (regno))
9406 if (mips_cfun_might_clobber_call_saved_reg_p (regno))
9409 /* Save both registers in an FPR pair if either one is used. This is
9410 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
9411 register to be used without the even register. */
9412 if (FP_REG_P (regno)
9413 && MAX_FPRS_PER_FMT == 2
9414 && mips_cfun_might_clobber_call_saved_reg_p (regno + 1))
9418 /* We need to save the incoming return address if __builtin_eh_return
9419 is being used to set a different return address. */
9420 if (regno == RETURN_ADDR_REGNUM && crtl->calls_eh_return)
9426 /* Populate the current function's mips_frame_info structure.
9428 MIPS stack frames look like:
9430 +-------------------------------+
9432 | incoming stack arguments |
9434 +-------------------------------+
9436 | caller-allocated save area |
9437 A | for register arguments |
9439 +-------------------------------+ <-- incoming stack pointer
9441 | callee-allocated save area |
9442 B | for arguments that are |
9443 | split between registers and |
9446 +-------------------------------+ <-- arg_pointer_rtx
9448 C | callee-allocated save area |
9449 | for register varargs |
9451 +-------------------------------+ <-- frame_pointer_rtx
9452 | | + cop0_sp_offset
9453 | COP0 reg save area | + UNITS_PER_WORD
9455 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
9456 | | + UNITS_PER_WORD
9457 | accumulator save area |
9459 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
9460 | | + UNITS_PER_HWFPVALUE
9463 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset
9464 | | + UNITS_PER_WORD
9467 +-------------------------------+ <-- frame_pointer_rtx with
9468 | | \ -fstack-protector
9469 | local variables | | var_size
9471 +-------------------------------+
9473 | $gp save area | | cprestore_size
9475 P +-------------------------------+ <-- hard_frame_pointer_rtx for
9477 | outgoing stack arguments | |
9479 +-------------------------------+ | args_size
9481 | caller-allocated save area | |
9482 | for register arguments | |
9484 +-------------------------------+ <-- stack_pointer_rtx
9485 frame_pointer_rtx without
9487 hard_frame_pointer_rtx for
9490 At least two of A, B and C will be empty.
9492 Dynamic stack allocations such as alloca insert data at point P.
9493 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
9494 hard_frame_pointer_rtx unchanged. */
9497 mips_compute_frame_info (void)
9499 struct mips_frame_info *frame;
9500 HOST_WIDE_INT offset, size;
9501 unsigned int regno, i;
9503 /* Set this function's interrupt properties. */
9504 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
9507 error ("the %<interrupt%> attribute requires a MIPS32r2 processor");
9508 else if (TARGET_HARD_FLOAT)
9509 error ("the %<interrupt%> attribute requires %<-msoft-float%>");
9510 else if (TARGET_MIPS16)
9511 error ("interrupt handlers cannot be MIPS16 functions");
9514 cfun->machine->interrupt_handler_p = true;
9515 cfun->machine->use_shadow_register_set_p =
9516 mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl));
9517 cfun->machine->keep_interrupts_masked_p =
9518 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl));
9519 cfun->machine->use_debug_exception_return_p =
9520 mips_use_debug_exception_return_p (TREE_TYPE
9521 (current_function_decl));
9525 frame = &cfun->machine->frame;
9526 memset (frame, 0, sizeof (*frame));
9527 size = get_frame_size ();
9529 cfun->machine->global_pointer = mips_global_pointer ();
9531 /* The first two blocks contain the outgoing argument area and the $gp save
9532 slot. This area isn't needed in leaf functions, but if the
9533 target-independent frame size is nonzero, we have already committed to
9534 allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */
9535 if ((size == 0 || FRAME_GROWS_DOWNWARD) && current_function_is_leaf)
9537 /* The MIPS 3.0 linker does not like functions that dynamically
9538 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
9539 looks like we are trying to create a second frame pointer to the
9540 function, so allocate some stack space to make it happy. */
9541 if (cfun->calls_alloca)
9542 frame->args_size = REG_PARM_STACK_SPACE (cfun->decl);
9544 frame->args_size = 0;
9545 frame->cprestore_size = 0;
9549 frame->args_size = crtl->outgoing_args_size;
9550 frame->cprestore_size = MIPS_GP_SAVE_AREA_SIZE;
9552 offset = frame->args_size + frame->cprestore_size;
9554 /* Move above the local variables. */
9555 frame->var_size = MIPS_STACK_ALIGN (size);
9556 offset += frame->var_size;
9558 /* Find out which GPRs we need to save. */
9559 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
9560 if (mips_save_reg_p (regno))
9563 frame->mask |= 1 << (regno - GP_REG_FIRST);
9566 /* If this function calls eh_return, we must also save and restore the
9567 EH data registers. */
9568 if (crtl->calls_eh_return)
9569 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; i++)
9572 frame->mask |= 1 << (EH_RETURN_DATA_REGNO (i) - GP_REG_FIRST);
9575 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
9576 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
9577 save all later registers too. */
9578 if (GENERATE_MIPS16E_SAVE_RESTORE)
9580 mips16e_mask_registers (&frame->mask, mips16e_s2_s8_regs,
9581 ARRAY_SIZE (mips16e_s2_s8_regs), &frame->num_gp);
9582 mips16e_mask_registers (&frame->mask, mips16e_a0_a3_regs,
9583 ARRAY_SIZE (mips16e_a0_a3_regs), &frame->num_gp);
9586 /* Move above the GPR save area. */
9587 if (frame->num_gp > 0)
9589 offset += MIPS_STACK_ALIGN (frame->num_gp * UNITS_PER_WORD);
9590 frame->gp_sp_offset = offset - UNITS_PER_WORD;
9593 /* Find out which FPRs we need to save. This loop must iterate over
9594 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
9595 if (TARGET_HARD_FLOAT)
9596 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += MAX_FPRS_PER_FMT)
9597 if (mips_save_reg_p (regno))
9599 frame->num_fp += MAX_FPRS_PER_FMT;
9600 frame->fmask |= ~(~0 << MAX_FPRS_PER_FMT) << (regno - FP_REG_FIRST);
9603 /* Move above the FPR save area. */
9604 if (frame->num_fp > 0)
9606 offset += MIPS_STACK_ALIGN (frame->num_fp * UNITS_PER_FPREG);
9607 frame->fp_sp_offset = offset - UNITS_PER_HWFPVALUE;
9610 /* Add in space for the interrupt context information. */
9611 if (cfun->machine->interrupt_handler_p)
9614 if (mips_save_reg_p (LO_REGNUM) || mips_save_reg_p (HI_REGNUM))
9617 frame->acc_mask |= (1 << 0);
9620 /* Check accumulators 1, 2, 3. */
9621 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
9622 if (mips_save_reg_p (i) || mips_save_reg_p (i + 1))
9625 frame->acc_mask |= 1 << (((i - DSP_ACC_REG_FIRST) / 2) + 1);
9628 /* All interrupt context functions need space to preserve STATUS. */
9629 frame->num_cop0_regs++;
9631 /* If we don't keep interrupts masked, we need to save EPC. */
9632 if (!cfun->machine->keep_interrupts_masked_p)
9633 frame->num_cop0_regs++;
9636 /* Move above the accumulator save area. */
9637 if (frame->num_acc > 0)
9639 /* Each accumulator needs 2 words. */
9640 offset += frame->num_acc * 2 * UNITS_PER_WORD;
9641 frame->acc_sp_offset = offset - UNITS_PER_WORD;
9644 /* Move above the COP0 register save area. */
9645 if (frame->num_cop0_regs > 0)
9647 offset += frame->num_cop0_regs * UNITS_PER_WORD;
9648 frame->cop0_sp_offset = offset - UNITS_PER_WORD;
9651 /* Move above the callee-allocated varargs save area. */
9652 offset += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
9653 frame->arg_pointer_offset = offset;
9655 /* Move above the callee-allocated area for pretend stack arguments. */
9656 offset += crtl->args.pretend_args_size;
9657 frame->total_size = offset;
9659 /* Work out the offsets of the save areas from the top of the frame. */
9660 if (frame->gp_sp_offset > 0)
9661 frame->gp_save_offset = frame->gp_sp_offset - offset;
9662 if (frame->fp_sp_offset > 0)
9663 frame->fp_save_offset = frame->fp_sp_offset - offset;
9664 if (frame->acc_sp_offset > 0)
9665 frame->acc_save_offset = frame->acc_sp_offset - offset;
9666 if (frame->num_cop0_regs > 0)
9667 frame->cop0_save_offset = frame->cop0_sp_offset - offset;
9669 /* MIPS16 code offsets the frame pointer by the size of the outgoing
9670 arguments. This tends to increase the chances of using unextended
9671 instructions for local variables and incoming arguments. */
9673 frame->hard_frame_pointer_offset = frame->args_size;
9676 /* Return the style of GP load sequence that is being used for the
9677 current function. */
9679 enum mips_loadgp_style
9680 mips_current_loadgp_style (void)
9682 if (!TARGET_USE_GOT || cfun->machine->global_pointer == INVALID_REGNUM)
9688 if (TARGET_ABSOLUTE_ABICALLS)
9689 return LOADGP_ABSOLUTE;
9691 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
9694 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
9697 mips_frame_pointer_required (void)
9699 /* If the function contains dynamic stack allocations, we need to
9700 use the frame pointer to access the static parts of the frame. */
9701 if (cfun->calls_alloca)
9704 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
9705 reload may be unable to compute the address of a local variable,
9706 since there is no way to add a large constant to the stack pointer
9707 without using a second temporary register. */
9710 mips_compute_frame_info ();
9711 if (!SMALL_OPERAND (cfun->machine->frame.total_size))
9718 /* Make sure that we're not trying to eliminate to the wrong hard frame
9722 mips_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
9724 return (to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM);
9727 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
9728 or argument pointer. TO is either the stack pointer or hard frame
9732 mips_initial_elimination_offset (int from, int to)
9734 HOST_WIDE_INT offset;
9736 mips_compute_frame_info ();
9738 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */
9741 case FRAME_POINTER_REGNUM:
9742 if (FRAME_GROWS_DOWNWARD)
9743 offset = (cfun->machine->frame.args_size
9744 + cfun->machine->frame.cprestore_size
9745 + cfun->machine->frame.var_size);
9750 case ARG_POINTER_REGNUM:
9751 offset = cfun->machine->frame.arg_pointer_offset;
9758 if (to == HARD_FRAME_POINTER_REGNUM)
9759 offset -= cfun->machine->frame.hard_frame_pointer_offset;
9764 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
9767 mips_extra_live_on_entry (bitmap regs)
9771 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
9772 the global pointer. */
9773 if (!TARGET_ABSOLUTE_ABICALLS)
9774 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
9776 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
9777 the global pointer. */
9779 bitmap_set_bit (regs, MIPS16_PIC_TEMP_REGNUM);
9781 /* See the comment above load_call<mode> for details. */
9782 bitmap_set_bit (regs, GOT_VERSION_REGNUM);
9786 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
9790 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
9795 return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);
9798 /* Emit code to change the current function's return address to
9799 ADDRESS. SCRATCH is available as a scratch register, if needed.
9800 ADDRESS and SCRATCH are both word-mode GPRs. */
9803 mips_set_return_address (rtx address, rtx scratch)
9807 gcc_assert (BITSET_P (cfun->machine->frame.mask, RETURN_ADDR_REGNUM));
9808 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
9809 cfun->machine->frame.gp_sp_offset);
9810 mips_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address);
9813 /* Return true if the current function has a cprestore slot. */
9816 mips_cfun_has_cprestore_slot_p (void)
9818 return (cfun->machine->global_pointer != INVALID_REGNUM
9819 && cfun->machine->frame.cprestore_size > 0);
9822 /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the
9823 cprestore slot. LOAD_P is true if the caller wants to load from
9824 the cprestore slot; it is false if the caller wants to store to
9828 mips_get_cprestore_base_and_offset (rtx *base, HOST_WIDE_INT *offset,
9831 const struct mips_frame_info *frame;
9833 frame = &cfun->machine->frame;
9834 /* .cprestore always uses the stack pointer instead of the frame pointer.
9835 We have a free choice for direct stores for non-MIPS16 functions,
9836 and for MIPS16 functions whose cprestore slot is in range of the
9837 stack pointer. Using the stack pointer would sometimes give more
9838 (early) scheduling freedom, but using the frame pointer would
9839 sometimes give more (late) scheduling freedom. It's hard to
9840 predict which applies to a given function, so let's keep things
9843 Loads must always use the frame pointer in functions that call
9844 alloca, and there's little benefit to using the stack pointer
9846 if (frame_pointer_needed && !(TARGET_CPRESTORE_DIRECTIVE && !load_p))
9848 *base = hard_frame_pointer_rtx;
9849 *offset = frame->args_size - frame->hard_frame_pointer_offset;
9853 *base = stack_pointer_rtx;
9854 *offset = frame->args_size;
9858 /* Return true if X is the load or store address of the cprestore slot;
9859 LOAD_P says which. */
9862 mips_cprestore_address_p (rtx x, bool load_p)
9864 rtx given_base, required_base;
9865 HOST_WIDE_INT given_offset, required_offset;
9867 mips_split_plus (x, &given_base, &given_offset);
9868 mips_get_cprestore_base_and_offset (&required_base, &required_offset, load_p);
9869 return given_base == required_base && given_offset == required_offset;
9872 /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are
9873 going to load from it, false if we are going to store to it.
9874 Use TEMP as a temporary register if need be. */
9877 mips_cprestore_slot (rtx temp, bool load_p)
9880 HOST_WIDE_INT offset;
9882 mips_get_cprestore_base_and_offset (&base, &offset, load_p);
9883 return gen_frame_mem (Pmode, mips_add_offset (temp, base, offset));
9886 /* Emit instructions to save global pointer value GP into cprestore
9887 slot MEM. OFFSET is the offset that MEM applies to the base register.
9889 MEM may not be a legitimate address. If it isn't, TEMP is a
9890 temporary register that can be used, otherwise it is a SCRATCH. */
9893 mips_save_gp_to_cprestore_slot (rtx mem, rtx offset, rtx gp, rtx temp)
9895 if (TARGET_CPRESTORE_DIRECTIVE)
9897 gcc_assert (gp == pic_offset_table_rtx);
9898 emit_insn (PMODE_INSN (gen_cprestore, (mem, offset)));
9901 mips_emit_move (mips_cprestore_slot (temp, false), gp);
9904 /* Restore $gp from its save slot, using TEMP as a temporary base register
9905 if need be. This function is for o32 and o64 abicalls only.
9907 See mips_must_initialize_gp_p for details about how we manage the
9911 mips_restore_gp_from_cprestore_slot (rtx temp)
9913 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI && epilogue_completed);
9915 if (!cfun->machine->must_restore_gp_when_clobbered_p)
9917 emit_note (NOTE_INSN_DELETED);
9923 mips_emit_move (temp, mips_cprestore_slot (temp, true));
9924 mips_emit_move (pic_offset_table_rtx, temp);
9927 mips_emit_move (pic_offset_table_rtx, mips_cprestore_slot (temp, true));
9928 if (!TARGET_EXPLICIT_RELOCS)
9929 emit_insn (gen_blockage ());
9932 /* A function to save or store a register. The first argument is the
9933 register and the second is the stack slot. */
9934 typedef void (*mips_save_restore_fn) (rtx, rtx);
9936 /* Use FN to save or restore register REGNO. MODE is the register's
9937 mode and OFFSET is the offset of its save slot from the current
9941 mips_save_restore_reg (enum machine_mode mode, int regno,
9942 HOST_WIDE_INT offset, mips_save_restore_fn fn)
9946 mem = gen_frame_mem (mode, plus_constant (stack_pointer_rtx, offset));
9947 fn (gen_rtx_REG (mode, regno), mem);
9950 /* Call FN for each accumlator that is saved by the current function.
9951 SP_OFFSET is the offset of the current stack pointer from the start
9955 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
9957 HOST_WIDE_INT offset;
9960 offset = cfun->machine->frame.acc_sp_offset - sp_offset;
9961 if (BITSET_P (cfun->machine->frame.acc_mask, 0))
9963 mips_save_restore_reg (word_mode, LO_REGNUM, offset, fn);
9964 offset -= UNITS_PER_WORD;
9965 mips_save_restore_reg (word_mode, HI_REGNUM, offset, fn);
9966 offset -= UNITS_PER_WORD;
9969 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
9970 if (BITSET_P (cfun->machine->frame.acc_mask,
9971 ((regno - DSP_ACC_REG_FIRST) / 2) + 1))
9973 mips_save_restore_reg (word_mode, regno, offset, fn);
9974 offset -= UNITS_PER_WORD;
9978 /* Call FN for each register that is saved by the current function.
9979 SP_OFFSET is the offset of the current stack pointer from the start
9983 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset,
9984 mips_save_restore_fn fn)
9986 enum machine_mode fpr_mode;
9987 HOST_WIDE_INT offset;
9990 /* Save registers starting from high to low. The debuggers prefer at least
9991 the return register be stored at func+4, and also it allows us not to
9992 need a nop in the epilogue if at least one register is reloaded in
9993 addition to return address. */
9994 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
9995 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
9996 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
9998 /* Record the ra offset for use by mips_function_profiler. */
9999 if (regno == RETURN_ADDR_REGNUM)
10000 cfun->machine->frame.ra_fp_offset = offset + sp_offset;
10001 mips_save_restore_reg (word_mode, regno, offset, fn);
10002 offset -= UNITS_PER_WORD;
10005 /* This loop must iterate over the same space as its companion in
10006 mips_compute_frame_info. */
10007 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
10008 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
10009 for (regno = FP_REG_LAST - MAX_FPRS_PER_FMT + 1;
10010 regno >= FP_REG_FIRST;
10011 regno -= MAX_FPRS_PER_FMT)
10012 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
10014 mips_save_restore_reg (fpr_mode, regno, offset, fn);
10015 offset -= GET_MODE_SIZE (fpr_mode);
10019 /* Return true if a move between register REGNO and its save slot (MEM)
10020 can be done in a single move. LOAD_P is true if we are loading
10021 from the slot, false if we are storing to it. */
10024 mips_direct_save_slot_move_p (unsigned int regno, rtx mem, bool load_p)
10026 /* There is a specific MIPS16 instruction for saving $31 to the stack. */
10027 if (TARGET_MIPS16 && !load_p && regno == RETURN_ADDR_REGNUM)
10030 return mips_secondary_reload_class (REGNO_REG_CLASS (regno),
10031 GET_MODE (mem), mem, load_p) == NO_REGS;
10034 /* Emit a move from SRC to DEST, given that one of them is a register
10035 save slot and that the other is a register. TEMP is a temporary
10036 GPR of the same mode that is available if need be. */
10039 mips_emit_save_slot_move (rtx dest, rtx src, rtx temp)
10041 unsigned int regno;
10046 regno = REGNO (src);
10051 regno = REGNO (dest);
10055 if (regno == cfun->machine->global_pointer && !mips_must_initialize_gp_p ())
10057 /* We don't yet know whether we'll need this instruction or not.
10058 Postpone the decision by emitting a ghost move. This move
10059 is specifically not frame-related; only the split version is. */
10061 emit_insn (gen_move_gpdi (dest, src));
10063 emit_insn (gen_move_gpsi (dest, src));
10067 if (regno == HI_REGNUM)
10071 mips_emit_move (temp, src);
10073 emit_insn (gen_mthisi_di (gen_rtx_REG (TImode, MD_REG_FIRST),
10074 temp, gen_rtx_REG (DImode, LO_REGNUM)));
10076 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode, MD_REG_FIRST),
10077 temp, gen_rtx_REG (SImode, LO_REGNUM)));
10082 emit_insn (gen_mfhidi_ti (temp,
10083 gen_rtx_REG (TImode, MD_REG_FIRST)));
10085 emit_insn (gen_mfhisi_di (temp,
10086 gen_rtx_REG (DImode, MD_REG_FIRST)));
10087 mips_emit_move (dest, temp);
10090 else if (mips_direct_save_slot_move_p (regno, mem, mem == src))
10091 mips_emit_move (dest, src);
10094 gcc_assert (!reg_overlap_mentioned_p (dest, temp));
10095 mips_emit_move (temp, src);
10096 mips_emit_move (dest, temp);
10099 mips_set_frame_expr (mips_frame_set (dest, src));
10102 /* If we're generating n32 or n64 abicalls, and the current function
10103 does not use $28 as its global pointer, emit a cplocal directive.
10104 Use pic_offset_table_rtx as the argument to the directive. */
10107 mips_output_cplocal (void)
10109 if (!TARGET_EXPLICIT_RELOCS
10110 && mips_must_initialize_gp_p ()
10111 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
10112 output_asm_insn (".cplocal %+", 0);
10115 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
10118 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
10120 const char *fnname;
10122 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
10123 floating-point arguments. */
10125 && TARGET_HARD_FLOAT_ABI
10126 && crtl->args.info.fp_code != 0)
10127 mips16_build_function_stub ();
10129 /* Get the function name the same way that toplev.c does before calling
10130 assemble_start_function. This is needed so that the name used here
10131 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10132 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
10133 mips_start_function_definition (fnname, TARGET_MIPS16);
10135 /* Output MIPS-specific frame information. */
10136 if (!flag_inhibit_size_directive)
10138 const struct mips_frame_info *frame;
10140 frame = &cfun->machine->frame;
10142 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
10144 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
10145 "# vars= " HOST_WIDE_INT_PRINT_DEC
10147 ", args= " HOST_WIDE_INT_PRINT_DEC
10148 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
10149 reg_names[frame_pointer_needed
10150 ? HARD_FRAME_POINTER_REGNUM
10151 : STACK_POINTER_REGNUM],
10152 (frame_pointer_needed
10153 ? frame->total_size - frame->hard_frame_pointer_offset
10154 : frame->total_size),
10155 reg_names[RETURN_ADDR_REGNUM],
10157 frame->num_gp, frame->num_fp,
10159 frame->cprestore_size);
10161 /* .mask MASK, OFFSET. */
10162 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
10163 frame->mask, frame->gp_save_offset);
10165 /* .fmask MASK, OFFSET. */
10166 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
10167 frame->fmask, frame->fp_save_offset);
10170 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
10171 Also emit the ".set noreorder; .set nomacro" sequence for functions
10173 if (mips_must_initialize_gp_p ()
10174 && mips_current_loadgp_style () == LOADGP_OLDABI)
10178 /* This is a fixed-form sequence. The position of the
10179 first two instructions is important because of the
10180 way _gp_disp is defined. */
10181 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
10182 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
10183 output_asm_insn ("sll\t$2,16", 0);
10184 output_asm_insn ("addu\t$2,$3", 0);
10188 /* .cpload must be in a .set noreorder but not a
10189 .set nomacro block. */
10190 mips_push_asm_switch (&mips_noreorder);
10191 output_asm_insn (".cpload\t%^", 0);
10192 if (!cfun->machine->all_noreorder_p)
10193 mips_pop_asm_switch (&mips_noreorder);
10195 mips_push_asm_switch (&mips_nomacro);
10198 else if (cfun->machine->all_noreorder_p)
10200 mips_push_asm_switch (&mips_noreorder);
10201 mips_push_asm_switch (&mips_nomacro);
10204 /* Tell the assembler which register we're using as the global
10205 pointer. This is needed for thunks, since they can use either
10206 explicit relocs or assembler macros. */
10207 mips_output_cplocal ();
10210 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
10213 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
10214 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
10216 const char *fnname;
10218 /* Reinstate the normal $gp. */
10219 SET_REGNO (pic_offset_table_rtx, GLOBAL_POINTER_REGNUM);
10220 mips_output_cplocal ();
10222 if (cfun->machine->all_noreorder_p)
10224 mips_pop_asm_switch (&mips_nomacro);
10225 mips_pop_asm_switch (&mips_noreorder);
10228 /* Get the function name the same way that toplev.c does before calling
10229 assemble_start_function. This is needed so that the name used here
10230 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10231 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
10232 mips_end_function_definition (fnname);
10235 /* Emit an optimisation barrier for accesses to the current frame. */
10238 mips_frame_barrier (void)
10240 emit_clobber (gen_frame_mem (BLKmode, stack_pointer_rtx));
10243 /* Save register REG to MEM. Make the instruction frame-related. */
10246 mips_save_reg (rtx reg, rtx mem)
10248 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
10252 if (mips_split_64bit_move_p (mem, reg))
10253 mips_split_doubleword_move (mem, reg);
10255 mips_emit_move (mem, reg);
10257 x1 = mips_frame_set (mips_subword (mem, false),
10258 mips_subword (reg, false));
10259 x2 = mips_frame_set (mips_subword (mem, true),
10260 mips_subword (reg, true));
10261 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
10264 mips_emit_save_slot_move (mem, reg, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
10267 /* The __gnu_local_gp symbol. */
10269 static GTY(()) rtx mips_gnu_local_gp;
10271 /* If we're generating n32 or n64 abicalls, emit instructions
10272 to set up the global pointer. */
10275 mips_emit_loadgp (void)
10277 rtx addr, offset, incoming_address, base, index, pic_reg;
10279 pic_reg = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
10280 switch (mips_current_loadgp_style ())
10282 case LOADGP_ABSOLUTE:
10283 if (mips_gnu_local_gp == NULL)
10285 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
10286 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
10288 emit_insn (PMODE_INSN (gen_loadgp_absolute,
10289 (pic_reg, mips_gnu_local_gp)));
10292 case LOADGP_OLDABI:
10293 /* Added by mips_output_function_prologue. */
10296 case LOADGP_NEWABI:
10297 addr = XEXP (DECL_RTL (current_function_decl), 0);
10298 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
10299 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
10300 emit_insn (PMODE_INSN (gen_loadgp_newabi,
10301 (pic_reg, offset, incoming_address)));
10305 base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE));
10306 index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX));
10307 emit_insn (PMODE_INSN (gen_loadgp_rtp, (pic_reg, base, index)));
10315 emit_insn (PMODE_INSN (gen_copygp_mips16,
10316 (pic_offset_table_rtx, pic_reg)));
10318 /* Emit a blockage if there are implicit uses of the GP register.
10319 This includes profiled functions, because FUNCTION_PROFILE uses
10321 if (!TARGET_EXPLICIT_RELOCS || crtl->profile)
10322 emit_insn (gen_loadgp_blockage ());
10325 /* A for_each_rtx callback. Stop the search if *X is a kernel register. */
10328 mips_kernel_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
10330 return REG_P (*x) && KERNEL_REG_P (REGNO (*x));
10333 /* Expand the "prologue" pattern. */
10336 mips_expand_prologue (void)
10338 const struct mips_frame_info *frame;
10339 HOST_WIDE_INT size;
10340 unsigned int nargs;
10343 if (cfun->machine->global_pointer != INVALID_REGNUM)
10345 /* Check whether an insn uses pic_offset_table_rtx, either explicitly
10346 or implicitly. If so, we can commit to using a global pointer
10347 straight away, otherwise we need to defer the decision. */
10348 if (mips_cfun_has_inflexible_gp_ref_p ()
10349 || mips_cfun_has_flexible_gp_ref_p ())
10351 cfun->machine->must_initialize_gp_p = true;
10352 cfun->machine->must_restore_gp_when_clobbered_p = true;
10355 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
10358 frame = &cfun->machine->frame;
10359 size = frame->total_size;
10361 if (flag_stack_usage_info)
10362 current_function_static_stack_size = size;
10364 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
10365 bytes beforehand; this is enough to cover the register save area
10366 without going out of range. */
10367 if (((frame->mask | frame->fmask | frame->acc_mask) != 0)
10368 || frame->num_cop0_regs > 0)
10370 HOST_WIDE_INT step1;
10372 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
10373 if (GENERATE_MIPS16E_SAVE_RESTORE)
10375 HOST_WIDE_INT offset;
10376 unsigned int mask, regno;
10378 /* Try to merge argument stores into the save instruction. */
10379 nargs = mips16e_collect_argument_saves ();
10381 /* Build the save instruction. */
10382 mask = frame->mask;
10383 insn = mips16e_build_save_restore (false, &mask, &offset,
10385 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10386 mips_frame_barrier ();
10389 /* Check if we need to save other registers. */
10390 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
10391 if (BITSET_P (mask, regno - GP_REG_FIRST))
10393 offset -= UNITS_PER_WORD;
10394 mips_save_restore_reg (word_mode, regno,
10395 offset, mips_save_reg);
10400 if (cfun->machine->interrupt_handler_p)
10402 HOST_WIDE_INT offset;
10405 /* If this interrupt is using a shadow register set, we need to
10406 get the stack pointer from the previous register set. */
10407 if (cfun->machine->use_shadow_register_set_p)
10408 emit_insn (gen_mips_rdpgpr (stack_pointer_rtx,
10409 stack_pointer_rtx));
10411 if (!cfun->machine->keep_interrupts_masked_p)
10413 /* Move from COP0 Cause to K0. */
10414 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K0_REG_NUM),
10415 gen_rtx_REG (SImode,
10416 COP0_CAUSE_REG_NUM)));
10417 /* Move from COP0 EPC to K1. */
10418 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
10419 gen_rtx_REG (SImode,
10420 COP0_EPC_REG_NUM)));
10423 /* Allocate the first part of the frame. */
10424 insn = gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx,
10426 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10427 mips_frame_barrier ();
10430 /* Start at the uppermost location for saving. */
10431 offset = frame->cop0_sp_offset - size;
10432 if (!cfun->machine->keep_interrupts_masked_p)
10434 /* Push EPC into its stack slot. */
10435 mem = gen_frame_mem (word_mode,
10436 plus_constant (stack_pointer_rtx,
10438 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
10439 offset -= UNITS_PER_WORD;
10442 /* Move from COP0 Status to K1. */
10443 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
10444 gen_rtx_REG (SImode,
10445 COP0_STATUS_REG_NUM)));
10447 /* Right justify the RIPL in k0. */
10448 if (!cfun->machine->keep_interrupts_masked_p)
10449 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode, K0_REG_NUM),
10450 gen_rtx_REG (SImode, K0_REG_NUM),
10451 GEN_INT (CAUSE_IPL)));
10453 /* Push Status into its stack slot. */
10454 mem = gen_frame_mem (word_mode,
10455 plus_constant (stack_pointer_rtx, offset));
10456 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
10457 offset -= UNITS_PER_WORD;
10459 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
10460 if (!cfun->machine->keep_interrupts_masked_p)
10461 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
10464 gen_rtx_REG (SImode, K0_REG_NUM)));
10466 if (!cfun->machine->keep_interrupts_masked_p)
10467 /* Enable interrupts by clearing the KSU ERL and EXL bits.
10468 IE is already the correct value, so we don't have to do
10469 anything explicit. */
10470 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
10473 gen_rtx_REG (SImode, GP_REG_FIRST)));
10475 /* Disable interrupts by clearing the KSU, ERL, EXL,
10477 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
10480 gen_rtx_REG (SImode, GP_REG_FIRST)));
10484 insn = gen_add3_insn (stack_pointer_rtx,
10487 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10488 mips_frame_barrier ();
10491 mips_for_each_saved_acc (size, mips_save_reg);
10492 mips_for_each_saved_gpr_and_fpr (size, mips_save_reg);
10496 /* Allocate the rest of the frame. */
10499 if (SMALL_OPERAND (-size))
10500 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
10502 GEN_INT (-size)))) = 1;
10505 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
10508 /* There are no instructions to add or subtract registers
10509 from the stack pointer, so use the frame pointer as a
10510 temporary. We should always be using a frame pointer
10511 in this case anyway. */
10512 gcc_assert (frame_pointer_needed);
10513 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
10514 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
10515 hard_frame_pointer_rtx,
10516 MIPS_PROLOGUE_TEMP (Pmode)));
10517 mips_emit_move (stack_pointer_rtx, hard_frame_pointer_rtx);
10520 emit_insn (gen_sub3_insn (stack_pointer_rtx,
10522 MIPS_PROLOGUE_TEMP (Pmode)));
10524 /* Describe the combined effect of the previous instructions. */
10525 mips_set_frame_expr
10526 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
10527 plus_constant (stack_pointer_rtx, -size)));
10529 mips_frame_barrier ();
10532 /* Set up the frame pointer, if we're using one. */
10533 if (frame_pointer_needed)
10535 HOST_WIDE_INT offset;
10537 offset = frame->hard_frame_pointer_offset;
10540 insn = mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
10541 RTX_FRAME_RELATED_P (insn) = 1;
10543 else if (SMALL_OPERAND (offset))
10545 insn = gen_add3_insn (hard_frame_pointer_rtx,
10546 stack_pointer_rtx, GEN_INT (offset));
10547 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10551 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (offset));
10552 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
10553 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
10554 hard_frame_pointer_rtx,
10555 MIPS_PROLOGUE_TEMP (Pmode)));
10556 mips_set_frame_expr
10557 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
10558 plus_constant (stack_pointer_rtx, offset)));
10562 mips_emit_loadgp ();
10564 /* Initialize the $gp save slot. */
10565 if (mips_cfun_has_cprestore_slot_p ())
10567 rtx base, mem, gp, temp;
10568 HOST_WIDE_INT offset;
10570 mips_get_cprestore_base_and_offset (&base, &offset, false);
10571 mem = gen_frame_mem (Pmode, plus_constant (base, offset));
10572 gp = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
10573 temp = (SMALL_OPERAND (offset)
10574 ? gen_rtx_SCRATCH (Pmode)
10575 : MIPS_PROLOGUE_TEMP (Pmode));
10576 emit_insn (PMODE_INSN (gen_potential_cprestore,
10577 (mem, GEN_INT (offset), gp, temp)));
10579 mips_get_cprestore_base_and_offset (&base, &offset, true);
10580 mem = gen_frame_mem (Pmode, plus_constant (base, offset));
10581 emit_insn (PMODE_INSN (gen_use_cprestore, (mem)));
10584 /* We need to search back to the last use of K0 or K1. */
10585 if (cfun->machine->interrupt_handler_p)
10587 for (insn = get_last_insn (); insn != NULL_RTX; insn = PREV_INSN (insn))
10589 && for_each_rtx (&PATTERN (insn), mips_kernel_reg_p, NULL))
10591 /* Emit a move from K1 to COP0 Status after insn. */
10592 gcc_assert (insn != NULL_RTX);
10593 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
10594 gen_rtx_REG (SImode, K1_REG_NUM)),
10598 /* If we are profiling, make sure no instructions are scheduled before
10599 the call to mcount. */
10601 emit_insn (gen_blockage ());
10604 /* Attach all pending register saves to the previous instruction.
10605 Return that instruction. */
10608 mips_epilogue_emit_cfa_restores (void)
10612 insn = get_last_insn ();
10613 gcc_assert (insn && !REG_NOTES (insn));
10614 if (mips_epilogue.cfa_restores)
10616 RTX_FRAME_RELATED_P (insn) = 1;
10617 REG_NOTES (insn) = mips_epilogue.cfa_restores;
10618 mips_epilogue.cfa_restores = 0;
10623 /* Like mips_epilogue_emit_cfa_restores, but also record that the CFA is
10624 now at REG + OFFSET. */
10627 mips_epilogue_set_cfa (rtx reg, HOST_WIDE_INT offset)
10631 insn = mips_epilogue_emit_cfa_restores ();
10632 if (reg != mips_epilogue.cfa_reg || offset != mips_epilogue.cfa_offset)
10634 RTX_FRAME_RELATED_P (insn) = 1;
10635 REG_NOTES (insn) = alloc_reg_note (REG_CFA_DEF_CFA,
10636 plus_constant (reg, offset),
10638 mips_epilogue.cfa_reg = reg;
10639 mips_epilogue.cfa_offset = offset;
10643 /* Emit instructions to restore register REG from slot MEM. Also update
10644 the cfa_restores list. */
10647 mips_restore_reg (rtx reg, rtx mem)
10649 /* There's no MIPS16 instruction to load $31 directly. Load into
10650 $7 instead and adjust the return insn appropriately. */
10651 if (TARGET_MIPS16 && REGNO (reg) == RETURN_ADDR_REGNUM)
10652 reg = gen_rtx_REG (GET_MODE (reg), GP_REG_FIRST + 7);
10653 else if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
10655 mips_add_cfa_restore (mips_subword (reg, true));
10656 mips_add_cfa_restore (mips_subword (reg, false));
10659 mips_add_cfa_restore (reg);
10661 mips_emit_save_slot_move (reg, mem, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
10662 if (REGNO (reg) == REGNO (mips_epilogue.cfa_reg))
10663 /* The CFA is currently defined in terms of the register whose
10664 value we have just restored. Redefine the CFA in terms of
10665 the stack pointer. */
10666 mips_epilogue_set_cfa (stack_pointer_rtx,
10667 mips_epilogue.cfa_restore_sp_offset);
10670 /* Emit code to set the stack pointer to BASE + OFFSET, given that
10671 BASE + OFFSET is NEW_FRAME_SIZE bytes below the top of the frame.
10672 BASE, if not the stack pointer, is available as a temporary. */
10675 mips_deallocate_stack (rtx base, rtx offset, HOST_WIDE_INT new_frame_size)
10677 if (base == stack_pointer_rtx && offset == const0_rtx)
10680 mips_frame_barrier ();
10681 if (offset == const0_rtx)
10683 emit_move_insn (stack_pointer_rtx, base);
10684 mips_epilogue_set_cfa (stack_pointer_rtx, new_frame_size);
10686 else if (TARGET_MIPS16 && base != stack_pointer_rtx)
10688 emit_insn (gen_add3_insn (base, base, offset));
10689 mips_epilogue_set_cfa (base, new_frame_size);
10690 emit_move_insn (stack_pointer_rtx, base);
10694 emit_insn (gen_add3_insn (stack_pointer_rtx, base, offset));
10695 mips_epilogue_set_cfa (stack_pointer_rtx, new_frame_size);
10699 /* Emit any instructions needed before a return. */
10702 mips_expand_before_return (void)
10704 /* When using a call-clobbered gp, we start out with unified call
10705 insns that include instructions to restore the gp. We then split
10706 these unified calls after reload. These split calls explicitly
10707 clobber gp, so there is no need to define
10708 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
10710 For consistency, we should also insert an explicit clobber of $28
10711 before return insns, so that the post-reload optimizers know that
10712 the register is not live on exit. */
10713 if (TARGET_CALL_CLOBBERED_GP)
10714 emit_clobber (pic_offset_table_rtx);
10717 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
10721 mips_expand_epilogue (bool sibcall_p)
10723 const struct mips_frame_info *frame;
10724 HOST_WIDE_INT step1, step2;
10725 rtx base, adjust, insn;
10727 if (!sibcall_p && mips_can_use_return_insn ())
10729 emit_jump_insn (gen_return ());
10733 /* In MIPS16 mode, if the return value should go into a floating-point
10734 register, we need to call a helper routine to copy it over. */
10735 if (mips16_cfun_returns_in_fpr_p ())
10736 mips16_copy_fpr_return_value ();
10738 /* Split the frame into two. STEP1 is the amount of stack we should
10739 deallocate before restoring the registers. STEP2 is the amount we
10740 should deallocate afterwards.
10742 Start off by assuming that no registers need to be restored. */
10743 frame = &cfun->machine->frame;
10744 step1 = frame->total_size;
10747 /* Work out which register holds the frame address. */
10748 if (!frame_pointer_needed)
10749 base = stack_pointer_rtx;
10752 base = hard_frame_pointer_rtx;
10753 step1 -= frame->hard_frame_pointer_offset;
10755 mips_epilogue.cfa_reg = base;
10756 mips_epilogue.cfa_offset = step1;
10757 mips_epilogue.cfa_restores = NULL_RTX;
10759 /* If we need to restore registers, deallocate as much stack as
10760 possible in the second step without going out of range. */
10761 if ((frame->mask | frame->fmask | frame->acc_mask) != 0
10762 || frame->num_cop0_regs > 0)
10764 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
10768 /* Get an rtx for STEP1 that we can add to BASE. */
10769 adjust = GEN_INT (step1);
10770 if (!SMALL_OPERAND (step1))
10772 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), adjust);
10773 adjust = MIPS_EPILOGUE_TEMP (Pmode);
10775 mips_deallocate_stack (base, adjust, step2);
10777 /* If we're using addressing macros, $gp is implicitly used by all
10778 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
10780 if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS)
10781 emit_insn (gen_blockage ());
10783 mips_epilogue.cfa_restore_sp_offset = step2;
10784 if (GENERATE_MIPS16E_SAVE_RESTORE && frame->mask != 0)
10786 unsigned int regno, mask;
10787 HOST_WIDE_INT offset;
10790 /* Generate the restore instruction. */
10791 mask = frame->mask;
10792 restore = mips16e_build_save_restore (true, &mask, &offset, 0, step2);
10794 /* Restore any other registers manually. */
10795 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
10796 if (BITSET_P (mask, regno - GP_REG_FIRST))
10798 offset -= UNITS_PER_WORD;
10799 mips_save_restore_reg (word_mode, regno, offset, mips_restore_reg);
10802 /* Restore the remaining registers and deallocate the final bit
10804 mips_frame_barrier ();
10805 emit_insn (restore);
10806 mips_epilogue_set_cfa (stack_pointer_rtx, 0);
10810 /* Restore the registers. */
10811 mips_for_each_saved_acc (frame->total_size - step2, mips_restore_reg);
10812 mips_for_each_saved_gpr_and_fpr (frame->total_size - step2,
10815 if (cfun->machine->interrupt_handler_p)
10817 HOST_WIDE_INT offset;
10820 offset = frame->cop0_sp_offset - (frame->total_size - step2);
10821 if (!cfun->machine->keep_interrupts_masked_p)
10823 /* Restore the original EPC. */
10824 mem = gen_frame_mem (word_mode,
10825 plus_constant (stack_pointer_rtx, offset));
10826 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
10827 offset -= UNITS_PER_WORD;
10829 /* Move to COP0 EPC. */
10830 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_EPC_REG_NUM),
10831 gen_rtx_REG (SImode, K0_REG_NUM)));
10834 /* Restore the original Status. */
10835 mem = gen_frame_mem (word_mode,
10836 plus_constant (stack_pointer_rtx, offset));
10837 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
10838 offset -= UNITS_PER_WORD;
10840 /* If we don't use shoadow register set, we need to update SP. */
10841 if (!cfun->machine->use_shadow_register_set_p)
10842 mips_deallocate_stack (stack_pointer_rtx, GEN_INT (step2), 0);
10844 /* The choice of position is somewhat arbitrary in this case. */
10845 mips_epilogue_emit_cfa_restores ();
10847 /* Move to COP0 Status. */
10848 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
10849 gen_rtx_REG (SImode, K0_REG_NUM)));
10852 /* Deallocate the final bit of the frame. */
10853 mips_deallocate_stack (stack_pointer_rtx, GEN_INT (step2), 0);
10855 gcc_assert (!mips_epilogue.cfa_restores);
10857 /* Add in the __builtin_eh_return stack adjustment. We need to
10858 use a temporary in MIPS16 code. */
10859 if (crtl->calls_eh_return)
10863 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
10864 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
10865 MIPS_EPILOGUE_TEMP (Pmode),
10866 EH_RETURN_STACKADJ_RTX));
10867 mips_emit_move (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
10870 emit_insn (gen_add3_insn (stack_pointer_rtx,
10872 EH_RETURN_STACKADJ_RTX));
10877 mips_expand_before_return ();
10878 if (cfun->machine->interrupt_handler_p)
10880 /* Interrupt handlers generate eret or deret. */
10881 if (cfun->machine->use_debug_exception_return_p)
10882 emit_jump_insn (gen_mips_deret ());
10884 emit_jump_insn (gen_mips_eret ());
10890 /* When generating MIPS16 code, the normal
10891 mips_for_each_saved_gpr_and_fpr path will restore the return
10892 address into $7 rather than $31. */
10894 && !GENERATE_MIPS16E_SAVE_RESTORE
10895 && BITSET_P (frame->mask, RETURN_ADDR_REGNUM))
10897 /* simple_returns cannot rely on values that are only available
10898 on paths through the epilogue (because return paths that do
10899 not pass through the epilogue may nevertheless reuse a
10900 simple_return that occurs at the end of the epilogue).
10901 Use a normal return here instead. */
10902 rtx reg = gen_rtx_REG (Pmode, GP_REG_FIRST + 7);
10903 pat = gen_return_internal (reg);
10907 rtx reg = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
10908 pat = gen_simple_return_internal (reg);
10910 emit_jump_insn (pat);
10914 /* Search from the beginning to the first use of K0 or K1. */
10915 if (cfun->machine->interrupt_handler_p
10916 && !cfun->machine->keep_interrupts_masked_p)
10918 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
10920 && for_each_rtx (&PATTERN(insn), mips_kernel_reg_p, NULL))
10922 gcc_assert (insn != NULL_RTX);
10923 /* Insert disable interrupts before the first use of K0 or K1. */
10924 emit_insn_before (gen_mips_di (), insn);
10925 emit_insn_before (gen_mips_ehb (), insn);
10929 /* Return nonzero if this function is known to have a null epilogue.
10930 This allows the optimizer to omit jumps to jumps if no stack
10934 mips_can_use_return_insn (void)
10936 /* Interrupt handlers need to go through the epilogue. */
10937 if (cfun->machine->interrupt_handler_p)
10940 if (!reload_completed)
10946 /* In MIPS16 mode, a function that returns a floating-point value
10947 needs to arrange to copy the return value into the floating-point
10949 if (mips16_cfun_returns_in_fpr_p ())
10952 return cfun->machine->frame.total_size == 0;
10955 /* Return true if register REGNO can store a value of mode MODE.
10956 The result of this function is cached in mips_hard_regno_mode_ok. */
10959 mips_hard_regno_mode_ok_p (unsigned int regno, enum machine_mode mode)
10962 enum mode_class mclass;
10964 if (mode == CCV2mode)
10965 return (ISA_HAS_8CC
10966 && ST_REG_P (regno)
10967 && (regno - ST_REG_FIRST) % 2 == 0);
10969 if (mode == CCV4mode)
10970 return (ISA_HAS_8CC
10971 && ST_REG_P (regno)
10972 && (regno - ST_REG_FIRST) % 4 == 0);
10974 if (mode == CCmode)
10977 return regno == FPSW_REGNUM;
10979 return (ST_REG_P (regno)
10980 || GP_REG_P (regno)
10981 || FP_REG_P (regno));
10984 size = GET_MODE_SIZE (mode);
10985 mclass = GET_MODE_CLASS (mode);
10987 if (GP_REG_P (regno))
10988 return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD;
10990 if (FP_REG_P (regno)
10991 && (((regno - FP_REG_FIRST) % MAX_FPRS_PER_FMT) == 0
10992 || (MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG)))
10994 /* Allow TFmode for CCmode reloads. */
10995 if (mode == TFmode && ISA_HAS_8CC)
10998 /* Allow 64-bit vector modes for Loongson-2E/2F. */
10999 if (TARGET_LOONGSON_VECTORS
11000 && (mode == V2SImode
11001 || mode == V4HImode
11002 || mode == V8QImode
11003 || mode == DImode))
11006 if (mclass == MODE_FLOAT
11007 || mclass == MODE_COMPLEX_FLOAT
11008 || mclass == MODE_VECTOR_FLOAT)
11009 return size <= UNITS_PER_FPVALUE;
11011 /* Allow integer modes that fit into a single register. We need
11012 to put integers into FPRs when using instructions like CVT
11013 and TRUNC. There's no point allowing sizes smaller than a word,
11014 because the FPU has no appropriate load/store instructions. */
11015 if (mclass == MODE_INT)
11016 return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG;
11019 if (ACC_REG_P (regno)
11020 && (INTEGRAL_MODE_P (mode) || ALL_FIXED_POINT_MODE_P (mode)))
11022 if (MD_REG_P (regno))
11024 /* After a multiplication or division, clobbering HI makes
11025 the value of LO unpredictable, and vice versa. This means
11026 that, for all interesting cases, HI and LO are effectively
11029 We model this by requiring that any value that uses HI
11031 if (size <= UNITS_PER_WORD * 2)
11032 return regno == (size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST);
11036 /* DSP accumulators do not have the same restrictions as
11037 HI and LO, so we can treat them as normal doubleword
11039 if (size <= UNITS_PER_WORD)
11042 if (size <= UNITS_PER_WORD * 2
11043 && ((regno - DSP_ACC_REG_FIRST) & 1) == 0)
11048 if (ALL_COP_REG_P (regno))
11049 return mclass == MODE_INT && size <= UNITS_PER_WORD;
11051 if (regno == GOT_VERSION_REGNUM)
11052 return mode == SImode;
11057 /* Implement HARD_REGNO_NREGS. */
11060 mips_hard_regno_nregs (int regno, enum machine_mode mode)
11062 if (ST_REG_P (regno))
11063 /* The size of FP status registers is always 4, because they only hold
11064 CCmode values, and CCmode is always considered to be 4 bytes wide. */
11065 return (GET_MODE_SIZE (mode) + 3) / 4;
11067 if (FP_REG_P (regno))
11068 return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG;
11070 /* All other registers are word-sized. */
11071 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
11074 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
11075 in mips_hard_regno_nregs. */
11078 mips_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
11084 COPY_HARD_REG_SET (left, reg_class_contents[(int) rclass]);
11085 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS]))
11087 if (HARD_REGNO_MODE_OK (ST_REG_FIRST, mode))
11088 size = MIN (size, 4);
11089 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) ST_REGS]);
11091 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS]))
11093 if (HARD_REGNO_MODE_OK (FP_REG_FIRST, mode))
11094 size = MIN (size, UNITS_PER_FPREG);
11095 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]);
11097 if (!hard_reg_set_empty_p (left))
11098 size = MIN (size, UNITS_PER_WORD);
11099 return (GET_MODE_SIZE (mode) + size - 1) / size;
11102 /* Implement CANNOT_CHANGE_MODE_CLASS. */
11105 mips_cannot_change_mode_class (enum machine_mode from,
11106 enum machine_mode to,
11107 enum reg_class rclass)
11109 /* Allow conversions between different Loongson integer vectors,
11110 and between those vectors and DImode. */
11111 if (GET_MODE_SIZE (from) == 8 && GET_MODE_SIZE (to) == 8
11112 && INTEGRAL_MODE_P (from) && INTEGRAL_MODE_P (to))
11115 /* Otherwise, there are several problems with changing the modes of
11116 values in floating-point registers:
11118 - When a multi-word value is stored in paired floating-point
11119 registers, the first register always holds the low word. We
11120 therefore can't allow FPRs to change between single-word and
11121 multi-word modes on big-endian targets.
11123 - GCC assumes that each word of a multiword register can be
11124 accessed individually using SUBREGs. This is not true for
11125 floating-point registers if they are bigger than a word.
11127 - Loading a 32-bit value into a 64-bit floating-point register
11128 will not sign-extend the value, despite what LOAD_EXTEND_OP
11129 says. We can't allow FPRs to change from SImode to a wider
11130 mode on 64-bit targets.
11132 - If the FPU has already interpreted a value in one format, we
11133 must not ask it to treat the value as having a different
11136 We therefore disallow all mode changes involving FPRs. */
11138 return reg_classes_intersect_p (FP_REGS, rclass);
11141 /* Implement target hook small_register_classes_for_mode_p. */
11144 mips_small_register_classes_for_mode_p (enum machine_mode mode
11147 return TARGET_MIPS16;
11150 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
11153 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode)
11158 return TARGET_HARD_FLOAT;
11161 return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT;
11164 return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT;
11171 /* Implement MODES_TIEABLE_P. */
11174 mips_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
11176 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
11177 prefer to put one of them in FPRs. */
11178 return (mode1 == mode2
11179 || (!mips_mode_ok_for_mov_fmt_p (mode1)
11180 && !mips_mode_ok_for_mov_fmt_p (mode2)));
11183 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
11186 mips_preferred_reload_class (rtx x, reg_class_t rclass)
11188 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, rclass))
11191 if (reg_class_subset_p (FP_REGS, rclass)
11192 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x)))
11195 if (reg_class_subset_p (GR_REGS, rclass))
11198 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, rclass))
11204 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
11205 Return a "canonical" class to represent it in later calculations. */
11208 mips_canonicalize_move_class (reg_class_t rclass)
11210 /* All moves involving accumulator registers have the same cost. */
11211 if (reg_class_subset_p (rclass, ACC_REGS))
11214 /* Likewise promote subclasses of general registers to the most
11215 interesting containing class. */
11216 if (TARGET_MIPS16 && reg_class_subset_p (rclass, M16_REGS))
11218 else if (reg_class_subset_p (rclass, GENERAL_REGS))
11219 rclass = GENERAL_REGS;
11224 /* Return the cost of moving a value of mode MODE from a register of
11225 class FROM to a GPR. Return 0 for classes that are unions of other
11226 classes handled by this function. */
11229 mips_move_to_gpr_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
11235 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
11239 /* MFLO and MFHI. */
11247 /* LUI followed by MOVF. */
11253 /* This choice of value is historical. */
11261 /* Return the cost of moving a value of mode MODE from a GPR to a
11262 register of class TO. Return 0 for classes that are unions of
11263 other classes handled by this function. */
11266 mips_move_from_gpr_cost (enum machine_mode mode, reg_class_t to)
11271 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
11275 /* MTLO and MTHI. */
11283 /* A secondary reload through an FPR scratch. */
11284 return (mips_register_move_cost (mode, GENERAL_REGS, FP_REGS)
11285 + mips_register_move_cost (mode, FP_REGS, ST_REGS));
11290 /* This choice of value is historical. */
11298 /* Implement TARGET_REGISTER_MOVE_COST. Return 0 for classes that are the
11299 maximum of the move costs for subclasses; regclass will work out
11300 the maximum for us. */
11303 mips_register_move_cost (enum machine_mode mode,
11304 reg_class_t from, reg_class_t to)
11309 from = mips_canonicalize_move_class (from);
11310 to = mips_canonicalize_move_class (to);
11312 /* Handle moves that can be done without using general-purpose registers. */
11313 if (from == FP_REGS)
11315 if (to == FP_REGS && mips_mode_ok_for_mov_fmt_p (mode))
11319 /* The sequence generated by mips_expand_fcc_reload. */
11323 /* Handle cases in which only one class deviates from the ideal. */
11324 dregs = TARGET_MIPS16 ? M16_REGS : GENERAL_REGS;
11326 return mips_move_from_gpr_cost (mode, to);
11328 return mips_move_to_gpr_cost (mode, from);
11330 /* Handles cases that require a GPR temporary. */
11331 cost1 = mips_move_to_gpr_cost (mode, from);
11334 cost2 = mips_move_from_gpr_cost (mode, to);
11336 return cost1 + cost2;
11342 /* Implement TARGET_MEMORY_MOVE_COST. */
11345 mips_memory_move_cost (enum machine_mode mode, reg_class_t rclass, bool in)
11347 return (mips_cost->memory_latency
11348 + memory_move_secondary_cost (mode, rclass, in));
11351 /* Return the register class required for a secondary register when
11352 copying between one of the registers in RCLASS and value X, which
11353 has mode MODE. X is the source of the move if IN_P, otherwise it
11354 is the destination. Return NO_REGS if no secondary register is
11358 mips_secondary_reload_class (enum reg_class rclass,
11359 enum machine_mode mode, rtx x, bool in_p)
11363 /* If X is a constant that cannot be loaded into $25, it must be loaded
11364 into some other GPR. No other register class allows a direct move. */
11365 if (mips_dangerous_for_la25_p (x))
11366 return reg_class_subset_p (rclass, LEA_REGS) ? NO_REGS : LEA_REGS;
11368 regno = true_regnum (x);
11371 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
11372 if (!reg_class_subset_p (rclass, M16_REGS) && !M16_REG_P (regno))
11378 /* Copying from accumulator registers to anywhere other than a general
11379 register requires a temporary general register. */
11380 if (reg_class_subset_p (rclass, ACC_REGS))
11381 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
11382 if (ACC_REG_P (regno))
11383 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
11385 /* We can only copy a value to a condition code register from a
11386 floating-point register, and even then we require a scratch
11387 floating-point register. We can only copy a value out of a
11388 condition-code register into a general register. */
11389 if (reg_class_subset_p (rclass, ST_REGS))
11393 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
11395 if (ST_REG_P (regno))
11399 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
11402 if (reg_class_subset_p (rclass, FP_REGS))
11405 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8))
11406 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
11407 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
11410 if (GP_REG_P (regno) || x == CONST0_RTX (mode))
11411 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
11414 if (CONSTANT_P (x) && !targetm.cannot_force_const_mem (mode, x))
11415 /* We can force the constant to memory and use lwc1
11416 and ldc1. As above, we will use pairs of lwc1s if
11417 ldc1 is not supported. */
11420 if (FP_REG_P (regno) && mips_mode_ok_for_mov_fmt_p (mode))
11421 /* In this case we can use mov.fmt. */
11424 /* Otherwise, we need to reload through an integer register. */
11427 if (FP_REG_P (regno))
11428 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
11433 /* Implement TARGET_MODE_REP_EXTENDED. */
11436 mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
11438 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
11439 if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
11440 return SIGN_EXTEND;
11445 /* Implement TARGET_VALID_POINTER_MODE. */
11448 mips_valid_pointer_mode (enum machine_mode mode)
11450 return mode == SImode || (TARGET_64BIT && mode == DImode);
11453 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
11456 mips_vector_mode_supported_p (enum machine_mode mode)
11461 return TARGET_PAIRED_SINGLE_FLOAT;
11476 return TARGET_LOONGSON_VECTORS;
11483 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
11486 mips_scalar_mode_supported_p (enum machine_mode mode)
11488 if (ALL_FIXED_POINT_MODE_P (mode)
11489 && GET_MODE_PRECISION (mode) <= 2 * BITS_PER_WORD)
11492 return default_scalar_mode_supported_p (mode);
11495 /* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
11497 static enum machine_mode
11498 mips_preferred_simd_mode (enum machine_mode mode ATTRIBUTE_UNUSED)
11500 if (TARGET_PAIRED_SINGLE_FLOAT
11506 /* Implement TARGET_INIT_LIBFUNCS. */
11509 mips_init_libfuncs (void)
11511 if (TARGET_FIX_VR4120)
11513 /* Register the special divsi3 and modsi3 functions needed to work
11514 around VR4120 division errata. */
11515 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
11516 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
11519 if (TARGET_MIPS16 && TARGET_HARD_FLOAT_ABI)
11521 /* Register the MIPS16 -mhard-float stubs. */
11522 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
11523 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
11524 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
11525 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
11527 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
11528 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
11529 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
11530 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
11531 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
11532 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
11533 set_optab_libfunc (unord_optab, SFmode, "__mips16_unordsf2");
11535 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
11536 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
11537 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__mips16_floatunsisf");
11539 if (TARGET_DOUBLE_FLOAT)
11541 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
11542 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
11543 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
11544 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
11546 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
11547 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
11548 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
11549 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
11550 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
11551 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
11552 set_optab_libfunc (unord_optab, DFmode, "__mips16_unorddf2");
11554 set_conv_libfunc (sext_optab, DFmode, SFmode,
11555 "__mips16_extendsfdf2");
11556 set_conv_libfunc (trunc_optab, SFmode, DFmode,
11557 "__mips16_truncdfsf2");
11558 set_conv_libfunc (sfix_optab, SImode, DFmode,
11559 "__mips16_fix_truncdfsi");
11560 set_conv_libfunc (sfloat_optab, DFmode, SImode,
11561 "__mips16_floatsidf");
11562 set_conv_libfunc (ufloat_optab, DFmode, SImode,
11563 "__mips16_floatunsidf");
11567 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
11568 on an external non-MIPS16 routine to implement __sync_synchronize.
11569 Similarly for the rest of the ll/sc libfuncs. */
11572 synchronize_libfunc = init_one_libfunc ("__sync_synchronize");
11573 init_sync_libfuncs (UNITS_PER_WORD);
11577 /* Build up a multi-insn sequence that loads label TARGET into $AT. */
11580 mips_process_load_label (rtx target)
11582 rtx base, gp, intop;
11583 HOST_WIDE_INT offset;
11585 mips_multi_start ();
11589 mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target, 0);
11590 mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target, 0);
11594 mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target, 0);
11595 mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target, 0);
11599 gp = pic_offset_table_rtx;
11600 if (mips_cfun_has_cprestore_slot_p ())
11602 gp = gen_rtx_REG (Pmode, AT_REGNUM);
11603 mips_get_cprestore_base_and_offset (&base, &offset, true);
11604 if (!SMALL_OPERAND (offset))
11606 intop = GEN_INT (CONST_HIGH_PART (offset));
11607 mips_multi_add_insn ("lui\t%0,%1", gp, intop, 0);
11608 mips_multi_add_insn ("addu\t%0,%0,%1", gp, base, 0);
11611 offset = CONST_LOW_PART (offset);
11613 intop = GEN_INT (offset);
11614 if (ISA_HAS_LOAD_DELAY)
11615 mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp, intop, base, 0);
11617 mips_multi_add_insn ("lw\t%0,%1(%2)", gp, intop, base, 0);
11619 if (ISA_HAS_LOAD_DELAY)
11620 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target, gp, 0);
11622 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target, gp, 0);
11623 mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target, 0);
11628 /* Return the number of instructions needed to load a label into $AT. */
11630 static unsigned int
11631 mips_load_label_num_insns (void)
11633 if (cfun->machine->load_label_num_insns == 0)
11635 mips_process_load_label (pc_rtx);
11636 cfun->machine->load_label_num_insns = mips_multi_num_insns;
11638 return cfun->machine->load_label_num_insns;
11641 /* Emit an asm sequence to start a noat block and load the address
11642 of a label into $1. */
11645 mips_output_load_label (rtx target)
11647 mips_push_asm_switch (&mips_noat);
11648 if (TARGET_EXPLICIT_RELOCS)
11650 mips_process_load_label (target);
11651 mips_multi_write ();
11655 if (Pmode == DImode)
11656 output_asm_insn ("dla\t%@,%0", &target);
11658 output_asm_insn ("la\t%@,%0", &target);
11662 /* Return the length of INSN. LENGTH is the initial length computed by
11663 attributes in the machine-description file. */
11666 mips_adjust_insn_length (rtx insn, int length)
11668 /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length
11669 of a PIC long-branch sequence. Substitute the correct value. */
11670 if (length == MAX_PIC_BRANCH_LENGTH
11671 && INSN_CODE (insn) >= 0
11672 && get_attr_type (insn) == TYPE_BRANCH)
11674 /* Add the branch-over instruction and its delay slot, if this
11675 is a conditional branch. */
11676 length = simplejump_p (insn) ? 0 : 8;
11678 /* Load the label into $AT and jump to it. Ignore the delay
11679 slot of the jump. */
11680 length += 4 * mips_load_label_num_insns() + 4;
11683 /* A unconditional jump has an unfilled delay slot if it is not part
11684 of a sequence. A conditional jump normally has a delay slot, but
11685 does not on MIPS16. */
11686 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
11689 /* See how many nops might be needed to avoid hardware hazards. */
11690 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
11691 switch (get_attr_hazard (insn))
11705 /* In order to make it easier to share MIPS16 and non-MIPS16 patterns,
11706 the .md file length attributes are 4-based for both modes.
11707 Adjust the MIPS16 ones here. */
11714 /* Return the assembly code for INSN, which has the operands given by
11715 OPERANDS, and which branches to OPERANDS[0] if some condition is true.
11716 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0]
11717 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
11718 version of BRANCH_IF_TRUE. */
11721 mips_output_conditional_branch (rtx insn, rtx *operands,
11722 const char *branch_if_true,
11723 const char *branch_if_false)
11725 unsigned int length;
11726 rtx taken, not_taken;
11728 gcc_assert (LABEL_P (operands[0]));
11730 length = get_attr_length (insn);
11733 /* Just a simple conditional branch. */
11734 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
11735 return branch_if_true;
11738 /* Generate a reversed branch around a direct jump. This fallback does
11739 not use branch-likely instructions. */
11740 mips_branch_likely = false;
11741 not_taken = gen_label_rtx ();
11742 taken = operands[0];
11744 /* Generate the reversed branch to NOT_TAKEN. */
11745 operands[0] = not_taken;
11746 output_asm_insn (branch_if_false, operands);
11748 /* If INSN has a delay slot, we must provide delay slots for both the
11749 branch to NOT_TAKEN and the conditional jump. We must also ensure
11750 that INSN's delay slot is executed in the appropriate cases. */
11751 if (final_sequence)
11753 /* This first delay slot will always be executed, so use INSN's
11754 delay slot if is not annulled. */
11755 if (!INSN_ANNULLED_BRANCH_P (insn))
11757 final_scan_insn (XVECEXP (final_sequence, 0, 1),
11758 asm_out_file, optimize, 1, NULL);
11759 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
11762 output_asm_insn ("nop", 0);
11763 fprintf (asm_out_file, "\n");
11766 /* Output the unconditional branch to TAKEN. */
11767 if (TARGET_ABSOLUTE_JUMPS)
11768 output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken);
11771 mips_output_load_label (taken);
11772 output_asm_insn ("jr\t%@%]%/", 0);
11775 /* Now deal with its delay slot; see above. */
11776 if (final_sequence)
11778 /* This delay slot will only be executed if the branch is taken.
11779 Use INSN's delay slot if is annulled. */
11780 if (INSN_ANNULLED_BRANCH_P (insn))
11782 final_scan_insn (XVECEXP (final_sequence, 0, 1),
11783 asm_out_file, optimize, 1, NULL);
11784 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
11787 output_asm_insn ("nop", 0);
11788 fprintf (asm_out_file, "\n");
11791 /* Output NOT_TAKEN. */
11792 targetm.asm_out.internal_label (asm_out_file, "L",
11793 CODE_LABEL_NUMBER (not_taken));
11797 /* Return the assembly code for INSN, which branches to OPERANDS[0]
11798 if some ordering condition is true. The condition is given by
11799 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
11800 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
11801 its second is always zero. */
11804 mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
11806 const char *branch[2];
11808 /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true.
11809 Make BRANCH[0] branch on the inverse condition. */
11810 switch (GET_CODE (operands[1]))
11812 /* These cases are equivalent to comparisons against zero. */
11814 inverted_p = !inverted_p;
11815 /* Fall through. */
11817 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%0");
11818 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%0");
11821 /* These cases are always true or always false. */
11823 inverted_p = !inverted_p;
11824 /* Fall through. */
11826 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%0");
11827 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%0");
11831 branch[!inverted_p] = MIPS_BRANCH ("b%C1z", "%2,%0");
11832 branch[inverted_p] = MIPS_BRANCH ("b%N1z", "%2,%0");
11835 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
11838 /* Start a block of code that needs access to the LL, SC and SYNC
11842 mips_start_ll_sc_sync_block (void)
11844 if (!ISA_HAS_LL_SC)
11846 output_asm_insn (".set\tpush", 0);
11847 output_asm_insn (".set\tmips2", 0);
11851 /* End a block started by mips_start_ll_sc_sync_block. */
11854 mips_end_ll_sc_sync_block (void)
11856 if (!ISA_HAS_LL_SC)
11857 output_asm_insn (".set\tpop", 0);
11860 /* Output and/or return the asm template for a sync instruction. */
11863 mips_output_sync (void)
11865 mips_start_ll_sc_sync_block ();
11866 output_asm_insn ("sync", 0);
11867 mips_end_ll_sc_sync_block ();
11871 /* Return the asm template associated with sync_insn1 value TYPE.
11872 IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */
11874 static const char *
11875 mips_sync_insn1_template (enum attr_sync_insn1 type, bool is_64bit_p)
11879 case SYNC_INSN1_MOVE:
11880 return "move\t%0,%z2";
11881 case SYNC_INSN1_LI:
11882 return "li\t%0,%2";
11883 case SYNC_INSN1_ADDU:
11884 return is_64bit_p ? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2";
11885 case SYNC_INSN1_ADDIU:
11886 return is_64bit_p ? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2";
11887 case SYNC_INSN1_SUBU:
11888 return is_64bit_p ? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2";
11889 case SYNC_INSN1_AND:
11890 return "and\t%0,%1,%z2";
11891 case SYNC_INSN1_ANDI:
11892 return "andi\t%0,%1,%2";
11893 case SYNC_INSN1_OR:
11894 return "or\t%0,%1,%z2";
11895 case SYNC_INSN1_ORI:
11896 return "ori\t%0,%1,%2";
11897 case SYNC_INSN1_XOR:
11898 return "xor\t%0,%1,%z2";
11899 case SYNC_INSN1_XORI:
11900 return "xori\t%0,%1,%2";
11902 gcc_unreachable ();
11905 /* Return the asm template associated with sync_insn2 value TYPE. */
11907 static const char *
11908 mips_sync_insn2_template (enum attr_sync_insn2 type)
11912 case SYNC_INSN2_NOP:
11913 gcc_unreachable ();
11914 case SYNC_INSN2_AND:
11915 return "and\t%0,%1,%z2";
11916 case SYNC_INSN2_XOR:
11917 return "xor\t%0,%1,%z2";
11918 case SYNC_INSN2_NOT:
11919 return "nor\t%0,%1,%.";
11921 gcc_unreachable ();
11924 /* OPERANDS are the operands to a sync loop instruction and INDEX is
11925 the value of the one of the sync_* attributes. Return the operand
11926 referred to by the attribute, or DEFAULT_VALUE if the insn doesn't
11927 have the associated attribute. */
11930 mips_get_sync_operand (rtx *operands, int index, rtx default_value)
11933 default_value = operands[index - 1];
11934 return default_value;
11937 /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn
11938 sequence for it. */
11941 mips_process_sync_loop (rtx insn, rtx *operands)
11943 rtx at, mem, oldval, newval, inclusive_mask, exclusive_mask;
11944 rtx required_oldval, insn1_op2, tmp1, tmp2, tmp3;
11945 unsigned int tmp3_insn;
11946 enum attr_sync_insn1 insn1;
11947 enum attr_sync_insn2 insn2;
11950 /* Read an operand from the sync_WHAT attribute and store it in
11951 variable WHAT. DEFAULT is the default value if no attribute
11953 #define READ_OPERAND(WHAT, DEFAULT) \
11954 WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \
11957 /* Read the memory. */
11958 READ_OPERAND (mem, 0);
11960 is_64bit_p = (GET_MODE_BITSIZE (GET_MODE (mem)) == 64);
11962 /* Read the other attributes. */
11963 at = gen_rtx_REG (GET_MODE (mem), AT_REGNUM);
11964 READ_OPERAND (oldval, at);
11965 READ_OPERAND (newval, at);
11966 READ_OPERAND (inclusive_mask, 0);
11967 READ_OPERAND (exclusive_mask, 0);
11968 READ_OPERAND (required_oldval, 0);
11969 READ_OPERAND (insn1_op2, 0);
11970 insn1 = get_attr_sync_insn1 (insn);
11971 insn2 = get_attr_sync_insn2 (insn);
11973 mips_multi_start ();
11975 /* Output the release side of the memory barrier. */
11976 if (get_attr_sync_release_barrier (insn) == SYNC_RELEASE_BARRIER_YES)
11978 if (required_oldval == 0 && TARGET_OCTEON)
11980 /* Octeon doesn't reorder reads, so a full barrier can be
11981 created by using SYNCW to order writes combined with the
11982 write from the following SC. When the SC successfully
11983 completes, we know that all preceding writes are also
11984 committed to the coherent memory system. It is possible
11985 for a single SYNCW to fail, but a pair of them will never
11986 fail, so we use two. */
11987 mips_multi_add_insn ("syncw", NULL);
11988 mips_multi_add_insn ("syncw", NULL);
11991 mips_multi_add_insn ("sync", NULL);
11994 /* Output the branch-back label. */
11995 mips_multi_add_label ("1:");
11997 /* OLDVAL = *MEM. */
11998 mips_multi_add_insn (is_64bit_p ? "lld\t%0,%1" : "ll\t%0,%1",
11999 oldval, mem, NULL);
12001 /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */
12002 if (required_oldval)
12004 if (inclusive_mask == 0)
12008 gcc_assert (oldval != at);
12009 mips_multi_add_insn ("and\t%0,%1,%2",
12010 at, oldval, inclusive_mask, NULL);
12013 mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1, required_oldval, NULL);
12016 /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */
12017 if (exclusive_mask == 0)
12021 gcc_assert (oldval != at);
12022 mips_multi_add_insn ("and\t%0,%1,%z2",
12023 at, oldval, exclusive_mask, NULL);
12027 /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2).
12029 We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit
12030 at least one instruction in that case. */
12031 if (insn1 == SYNC_INSN1_MOVE
12032 && (tmp1 != const0_rtx || insn2 != SYNC_INSN2_NOP))
12036 mips_multi_add_insn (mips_sync_insn1_template (insn1, is_64bit_p),
12037 newval, oldval, insn1_op2, NULL);
12041 /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */
12042 if (insn2 == SYNC_INSN2_NOP)
12046 mips_multi_add_insn (mips_sync_insn2_template (insn2),
12047 newval, tmp2, inclusive_mask, NULL);
12050 tmp3_insn = mips_multi_last_index ();
12052 /* $AT = $TMP1 | $TMP3. */
12053 if (tmp1 == const0_rtx || tmp3 == const0_rtx)
12055 mips_multi_set_operand (tmp3_insn, 0, at);
12060 gcc_assert (tmp1 != tmp3);
12061 mips_multi_add_insn ("or\t%0,%1,%2", at, tmp1, tmp3, NULL);
12064 /* if (!commit (*MEM = $AT)) goto 1.
12066 This will sometimes be a delayed branch; see the write code below
12068 mips_multi_add_insn (is_64bit_p ? "scd\t%0,%1" : "sc\t%0,%1", at, mem, NULL);
12069 mips_multi_add_insn ("beq%?\t%0,%.,1b", at, NULL);
12071 /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */
12072 if (insn1 != SYNC_INSN1_MOVE && insn1 != SYNC_INSN1_LI && tmp3 != newval)
12074 mips_multi_copy_insn (tmp3_insn);
12075 mips_multi_set_operand (mips_multi_last_index (), 0, newval);
12078 mips_multi_add_insn ("nop", NULL);
12080 /* Output the acquire side of the memory barrier. */
12081 if (TARGET_SYNC_AFTER_SC)
12082 mips_multi_add_insn ("sync", NULL);
12084 /* Output the exit label, if needed. */
12085 if (required_oldval)
12086 mips_multi_add_label ("2:");
12088 #undef READ_OPERAND
12091 /* Output and/or return the asm template for sync loop INSN, which has
12092 the operands given by OPERANDS. */
12095 mips_output_sync_loop (rtx insn, rtx *operands)
12097 mips_process_sync_loop (insn, operands);
12099 /* Use branch-likely instructions to work around the LL/SC R10000
12101 mips_branch_likely = TARGET_FIX_R10000;
12103 mips_push_asm_switch (&mips_noreorder);
12104 mips_push_asm_switch (&mips_nomacro);
12105 mips_push_asm_switch (&mips_noat);
12106 mips_start_ll_sc_sync_block ();
12108 mips_multi_write ();
12110 mips_end_ll_sc_sync_block ();
12111 mips_pop_asm_switch (&mips_noat);
12112 mips_pop_asm_switch (&mips_nomacro);
12113 mips_pop_asm_switch (&mips_noreorder);
12118 /* Return the number of individual instructions in sync loop INSN,
12119 which has the operands given by OPERANDS. */
12122 mips_sync_loop_insns (rtx insn, rtx *operands)
12124 mips_process_sync_loop (insn, operands);
12125 return mips_multi_num_insns;
12128 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
12129 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
12131 When working around R4000 and R4400 errata, we need to make sure that
12132 the division is not immediately followed by a shift[1][2]. We also
12133 need to stop the division from being put into a branch delay slot[3].
12134 The easiest way to avoid both problems is to add a nop after the
12135 division. When a divide-by-zero check is needed, this nop can be
12136 used to fill the branch delay slot.
12138 [1] If a double-word or a variable shift executes immediately
12139 after starting an integer division, the shift may give an
12140 incorrect result. See quotations of errata #16 and #28 from
12141 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
12142 in mips.md for details.
12144 [2] A similar bug to [1] exists for all revisions of the
12145 R4000 and the R4400 when run in an MC configuration.
12146 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
12148 "19. In this following sequence:
12150 ddiv (or ddivu or div or divu)
12151 dsll32 (or dsrl32, dsra32)
12153 if an MPT stall occurs, while the divide is slipping the cpu
12154 pipeline, then the following double shift would end up with an
12157 Workaround: The compiler needs to avoid generating any
12158 sequence with divide followed by extended double shift."
12160 This erratum is also present in "MIPS R4400MC Errata, Processor
12161 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
12162 & 3.0" as errata #10 and #4, respectively.
12164 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
12165 (also valid for MIPS R4000MC processors):
12167 "52. R4000SC: This bug does not apply for the R4000PC.
12169 There are two flavors of this bug:
12171 1) If the instruction just after divide takes an RF exception
12172 (tlb-refill, tlb-invalid) and gets an instruction cache
12173 miss (both primary and secondary) and the line which is
12174 currently in secondary cache at this index had the first
12175 data word, where the bits 5..2 are set, then R4000 would
12176 get a wrong result for the div.
12181 ------------------- # end-of page. -tlb-refill
12186 ------------------- # end-of page. -tlb-invalid
12189 2) If the divide is in the taken branch delay slot, where the
12190 target takes RF exception and gets an I-cache miss for the
12191 exception vector or where I-cache miss occurs for the
12192 target address, under the above mentioned scenarios, the
12193 div would get wrong results.
12196 j r2 # to next page mapped or unmapped
12197 div r8,r9 # this bug would be there as long
12198 # as there is an ICache miss and
12199 nop # the "data pattern" is present
12202 beq r0, r0, NextPage # to Next page
12206 This bug is present for div, divu, ddiv, and ddivu
12209 Workaround: For item 1), OS could make sure that the next page
12210 after the divide instruction is also mapped. For item 2), the
12211 compiler could make sure that the divide instruction is not in
12212 the branch delay slot."
12214 These processors have PRId values of 0x00004220 and 0x00004300 for
12215 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
12218 mips_output_division (const char *division, rtx *operands)
12223 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
12225 output_asm_insn (s, operands);
12228 if (TARGET_CHECK_ZERO_DIV)
12232 output_asm_insn (s, operands);
12233 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
12235 else if (GENERATE_DIVIDE_TRAPS)
12237 /* Avoid long replay penalty on load miss by putting the trap before
12240 output_asm_insn ("teq\t%2,%.,7", operands);
12243 output_asm_insn (s, operands);
12244 s = "teq\t%2,%.,7";
12249 output_asm_insn ("%(bne\t%2,%.,1f", operands);
12250 output_asm_insn (s, operands);
12251 s = "break\t7%)\n1:";
12257 /* Return true if IN_INSN is a multiply-add or multiply-subtract
12258 instruction and if OUT_INSN assigns to the accumulator operand. */
12261 mips_linked_madd_p (rtx out_insn, rtx in_insn)
12265 x = single_set (in_insn);
12271 if (GET_CODE (x) == PLUS
12272 && GET_CODE (XEXP (x, 0)) == MULT
12273 && reg_set_p (XEXP (x, 1), out_insn))
12276 if (GET_CODE (x) == MINUS
12277 && GET_CODE (XEXP (x, 1)) == MULT
12278 && reg_set_p (XEXP (x, 0), out_insn))
12284 /* True if the dependency between OUT_INSN and IN_INSN is on the store
12285 data rather than the address. We need this because the cprestore
12286 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
12287 which causes the default routine to abort. We just return false
12291 mips_store_data_bypass_p (rtx out_insn, rtx in_insn)
12293 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
12296 return !store_data_bypass_p (out_insn, in_insn);
12300 /* Variables and flags used in scheduler hooks when tuning for
12304 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
12307 /* If true, then next ALU1/2 instruction will go to ALU1. */
12310 /* If true, then next FALU1/2 unstruction will go to FALU1. */
12313 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
12314 int alu1_core_unit_code;
12315 int alu2_core_unit_code;
12316 int falu1_core_unit_code;
12317 int falu2_core_unit_code;
12319 /* True if current cycle has a multi instruction.
12320 This flag is used in mips_ls2_dfa_post_advance_cycle. */
12321 bool cycle_has_multi_p;
12323 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
12324 These are used in mips_ls2_dfa_post_advance_cycle to initialize
12326 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
12327 instruction to go ALU1. */
12328 rtx alu1_turn_enabled_insn;
12329 rtx alu2_turn_enabled_insn;
12330 rtx falu1_turn_enabled_insn;
12331 rtx falu2_turn_enabled_insn;
12334 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
12335 dependencies have no cost, except on the 20Kc where output-dependence
12336 is treated like input-dependence. */
12339 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
12340 rtx dep ATTRIBUTE_UNUSED, int cost)
12342 if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT
12345 if (REG_NOTE_KIND (link) != 0)
12350 /* Return the number of instructions that can be issued per cycle. */
12353 mips_issue_rate (void)
12357 case PROCESSOR_74KC:
12358 case PROCESSOR_74KF2_1:
12359 case PROCESSOR_74KF1_1:
12360 case PROCESSOR_74KF3_2:
12361 /* The 74k is not strictly quad-issue cpu, but can be seen as one
12362 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
12363 but in reality only a maximum of 3 insns can be issued as
12364 floating-point loads and stores also require a slot in the
12366 case PROCESSOR_R10000:
12367 /* All R10K Processors are quad-issue (being the first MIPS
12368 processors to support this feature). */
12371 case PROCESSOR_20KC:
12372 case PROCESSOR_R4130:
12373 case PROCESSOR_R5400:
12374 case PROCESSOR_R5500:
12375 case PROCESSOR_R7000:
12376 case PROCESSOR_R9000:
12377 case PROCESSOR_OCTEON:
12378 case PROCESSOR_OCTEON2:
12381 case PROCESSOR_SB1:
12382 case PROCESSOR_SB1A:
12383 /* This is actually 4, but we get better performance if we claim 3.
12384 This is partly because of unwanted speculative code motion with the
12385 larger number, and partly because in most common cases we can't
12386 reach the theoretical max of 4. */
12389 case PROCESSOR_LOONGSON_2E:
12390 case PROCESSOR_LOONGSON_2F:
12391 case PROCESSOR_LOONGSON_3A:
12399 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
12402 mips_ls2_init_dfa_post_cycle_insn (void)
12405 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
12406 mips_ls2.alu1_turn_enabled_insn = get_insns ();
12410 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
12411 mips_ls2.alu2_turn_enabled_insn = get_insns ();
12415 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
12416 mips_ls2.falu1_turn_enabled_insn = get_insns ();
12420 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
12421 mips_ls2.falu2_turn_enabled_insn = get_insns ();
12424 mips_ls2.alu1_core_unit_code = get_cpu_unit_code ("ls2_alu1_core");
12425 mips_ls2.alu2_core_unit_code = get_cpu_unit_code ("ls2_alu2_core");
12426 mips_ls2.falu1_core_unit_code = get_cpu_unit_code ("ls2_falu1_core");
12427 mips_ls2.falu2_core_unit_code = get_cpu_unit_code ("ls2_falu2_core");
12430 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
12431 Init data used in mips_dfa_post_advance_cycle. */
12434 mips_init_dfa_post_cycle_insn (void)
12436 if (TUNE_LOONGSON_2EF)
12437 mips_ls2_init_dfa_post_cycle_insn ();
12440 /* Initialize STATE when scheduling for Loongson 2E/2F.
12441 Support round-robin dispatch scheme by enabling only one of
12442 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
12446 mips_ls2_dfa_post_advance_cycle (state_t state)
12448 if (cpu_unit_reservation_p (state, mips_ls2.alu1_core_unit_code))
12450 /* Though there are no non-pipelined ALU1 insns,
12451 we can get an instruction of type 'multi' before reload. */
12452 gcc_assert (mips_ls2.cycle_has_multi_p);
12453 mips_ls2.alu1_turn_p = false;
12456 mips_ls2.cycle_has_multi_p = false;
12458 if (cpu_unit_reservation_p (state, mips_ls2.alu2_core_unit_code))
12459 /* We have a non-pipelined alu instruction in the core,
12460 adjust round-robin counter. */
12461 mips_ls2.alu1_turn_p = true;
12463 if (mips_ls2.alu1_turn_p)
12465 if (state_transition (state, mips_ls2.alu1_turn_enabled_insn) >= 0)
12466 gcc_unreachable ();
12470 if (state_transition (state, mips_ls2.alu2_turn_enabled_insn) >= 0)
12471 gcc_unreachable ();
12474 if (cpu_unit_reservation_p (state, mips_ls2.falu1_core_unit_code))
12476 /* There are no non-pipelined FALU1 insns. */
12477 gcc_unreachable ();
12478 mips_ls2.falu1_turn_p = false;
12481 if (cpu_unit_reservation_p (state, mips_ls2.falu2_core_unit_code))
12482 /* We have a non-pipelined falu instruction in the core,
12483 adjust round-robin counter. */
12484 mips_ls2.falu1_turn_p = true;
12486 if (mips_ls2.falu1_turn_p)
12488 if (state_transition (state, mips_ls2.falu1_turn_enabled_insn) >= 0)
12489 gcc_unreachable ();
12493 if (state_transition (state, mips_ls2.falu2_turn_enabled_insn) >= 0)
12494 gcc_unreachable ();
12498 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
12499 This hook is being called at the start of each cycle. */
12502 mips_dfa_post_advance_cycle (void)
12504 if (TUNE_LOONGSON_2EF)
12505 mips_ls2_dfa_post_advance_cycle (curr_state);
12508 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
12509 be as wide as the scheduling freedom in the DFA. */
12512 mips_multipass_dfa_lookahead (void)
12514 /* Can schedule up to 4 of the 6 function units in any one cycle. */
12518 if (TUNE_LOONGSON_2EF || TUNE_LOONGSON_3A)
12527 /* Remove the instruction at index LOWER from ready queue READY and
12528 reinsert it in front of the instruction at index HIGHER. LOWER must
12532 mips_promote_ready (rtx *ready, int lower, int higher)
12537 new_head = ready[lower];
12538 for (i = lower; i < higher; i++)
12539 ready[i] = ready[i + 1];
12540 ready[i] = new_head;
12543 /* If the priority of the instruction at POS2 in the ready queue READY
12544 is within LIMIT units of that of the instruction at POS1, swap the
12545 instructions if POS2 is not already less than POS1. */
12548 mips_maybe_swap_ready (rtx *ready, int pos1, int pos2, int limit)
12551 && INSN_PRIORITY (ready[pos1]) + limit >= INSN_PRIORITY (ready[pos2]))
12555 temp = ready[pos1];
12556 ready[pos1] = ready[pos2];
12557 ready[pos2] = temp;
12561 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
12562 that may clobber hi or lo. */
12563 static rtx mips_macc_chains_last_hilo;
12565 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
12566 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
12569 mips_macc_chains_record (rtx insn)
12571 if (get_attr_may_clobber_hilo (insn))
12572 mips_macc_chains_last_hilo = insn;
12575 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
12576 has NREADY elements, looking for a multiply-add or multiply-subtract
12577 instruction that is cumulative with mips_macc_chains_last_hilo.
12578 If there is one, promote it ahead of anything else that might
12579 clobber hi or lo. */
12582 mips_macc_chains_reorder (rtx *ready, int nready)
12586 if (mips_macc_chains_last_hilo != 0)
12587 for (i = nready - 1; i >= 0; i--)
12588 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
12590 for (j = nready - 1; j > i; j--)
12591 if (recog_memoized (ready[j]) >= 0
12592 && get_attr_may_clobber_hilo (ready[j]))
12594 mips_promote_ready (ready, i, j);
12601 /* The last instruction to be scheduled. */
12602 static rtx vr4130_last_insn;
12604 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
12605 points to an rtx that is initially an instruction. Nullify the rtx
12606 if the instruction uses the value of register X. */
12609 vr4130_true_reg_dependence_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
12614 insn_ptr = (rtx *) data;
12617 && reg_referenced_p (x, PATTERN (*insn_ptr)))
12621 /* Return true if there is true register dependence between vr4130_last_insn
12625 vr4130_true_reg_dependence_p (rtx insn)
12627 note_stores (PATTERN (vr4130_last_insn),
12628 vr4130_true_reg_dependence_p_1, &insn);
12632 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
12633 the ready queue and that INSN2 is the instruction after it, return
12634 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
12635 in which INSN1 and INSN2 can probably issue in parallel, but for
12636 which (INSN2, INSN1) should be less sensitive to instruction
12637 alignment than (INSN1, INSN2). See 4130.md for more details. */
12640 vr4130_swap_insns_p (rtx insn1, rtx insn2)
12642 sd_iterator_def sd_it;
12645 /* Check for the following case:
12647 1) there is some other instruction X with an anti dependence on INSN1;
12648 2) X has a higher priority than INSN2; and
12649 3) X is an arithmetic instruction (and thus has no unit restrictions).
12651 If INSN1 is the last instruction blocking X, it would better to
12652 choose (INSN1, X) over (INSN2, INSN1). */
12653 FOR_EACH_DEP (insn1, SD_LIST_FORW, sd_it, dep)
12654 if (DEP_TYPE (dep) == REG_DEP_ANTI
12655 && INSN_PRIORITY (DEP_CON (dep)) > INSN_PRIORITY (insn2)
12656 && recog_memoized (DEP_CON (dep)) >= 0
12657 && get_attr_vr4130_class (DEP_CON (dep)) == VR4130_CLASS_ALU)
12660 if (vr4130_last_insn != 0
12661 && recog_memoized (insn1) >= 0
12662 && recog_memoized (insn2) >= 0)
12664 /* See whether INSN1 and INSN2 use different execution units,
12665 or if they are both ALU-type instructions. If so, they can
12666 probably execute in parallel. */
12667 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
12668 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
12669 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
12671 /* If only one of the instructions has a dependence on
12672 vr4130_last_insn, prefer to schedule the other one first. */
12673 bool dep1_p = vr4130_true_reg_dependence_p (insn1);
12674 bool dep2_p = vr4130_true_reg_dependence_p (insn2);
12675 if (dep1_p != dep2_p)
12678 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
12679 is not an ALU-type instruction and if INSN1 uses the same
12680 execution unit. (Note that if this condition holds, we already
12681 know that INSN2 uses a different execution unit.) */
12682 if (class1 != VR4130_CLASS_ALU
12683 && recog_memoized (vr4130_last_insn) >= 0
12684 && class1 == get_attr_vr4130_class (vr4130_last_insn))
12691 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
12692 queue with at least two instructions. Swap the first two if
12693 vr4130_swap_insns_p says that it could be worthwhile. */
12696 vr4130_reorder (rtx *ready, int nready)
12698 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
12699 mips_promote_ready (ready, nready - 2, nready - 1);
12702 /* Record whether last 74k AGEN instruction was a load or store. */
12703 static enum attr_type mips_last_74k_agen_insn = TYPE_UNKNOWN;
12705 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
12706 resets to TYPE_UNKNOWN state. */
12709 mips_74k_agen_init (rtx insn)
12711 if (!insn || CALL_P (insn) || JUMP_P (insn))
12712 mips_last_74k_agen_insn = TYPE_UNKNOWN;
12715 enum attr_type type = get_attr_type (insn);
12716 if (type == TYPE_LOAD || type == TYPE_STORE)
12717 mips_last_74k_agen_insn = type;
12721 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
12722 loads to be grouped together, and multiple stores to be grouped
12723 together. Swap things around in the ready queue to make this happen. */
12726 mips_74k_agen_reorder (rtx *ready, int nready)
12729 int store_pos, load_pos;
12734 for (i = nready - 1; i >= 0; i--)
12736 rtx insn = ready[i];
12737 if (USEFUL_INSN_P (insn))
12738 switch (get_attr_type (insn))
12741 if (store_pos == -1)
12746 if (load_pos == -1)
12755 if (load_pos == -1 || store_pos == -1)
12758 switch (mips_last_74k_agen_insn)
12761 /* Prefer to schedule loads since they have a higher latency. */
12763 /* Swap loads to the front of the queue. */
12764 mips_maybe_swap_ready (ready, load_pos, store_pos, 4);
12767 /* Swap stores to the front of the queue. */
12768 mips_maybe_swap_ready (ready, store_pos, load_pos, 4);
12775 /* Implement TARGET_SCHED_INIT. */
12778 mips_sched_init (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12779 int max_ready ATTRIBUTE_UNUSED)
12781 mips_macc_chains_last_hilo = 0;
12782 vr4130_last_insn = 0;
12783 mips_74k_agen_init (NULL_RTX);
12785 /* When scheduling for Loongson2, branch instructions go to ALU1,
12786 therefore basic block is most likely to start with round-robin counter
12787 pointed to ALU2. */
12788 mips_ls2.alu1_turn_p = false;
12789 mips_ls2.falu1_turn_p = true;
12792 /* Subroutine used by TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
12795 mips_sched_reorder_1 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12796 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
12798 if (!reload_completed
12799 && TUNE_MACC_CHAINS
12801 mips_macc_chains_reorder (ready, *nreadyp);
12803 if (reload_completed
12805 && !TARGET_VR4130_ALIGN
12807 vr4130_reorder (ready, *nreadyp);
12810 mips_74k_agen_reorder (ready, *nreadyp);
12813 /* Implement TARGET_SCHED_REORDER. */
12816 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12817 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
12819 mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle);
12820 return mips_issue_rate ();
12823 /* Implement TARGET_SCHED_REORDER2. */
12826 mips_sched_reorder2 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12827 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
12829 mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle);
12830 return cached_can_issue_more;
12833 /* Update round-robin counters for ALU1/2 and FALU1/2. */
12836 mips_ls2_variable_issue (rtx insn)
12838 if (mips_ls2.alu1_turn_p)
12840 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu1_core_unit_code))
12841 mips_ls2.alu1_turn_p = false;
12845 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu2_core_unit_code))
12846 mips_ls2.alu1_turn_p = true;
12849 if (mips_ls2.falu1_turn_p)
12851 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu1_core_unit_code))
12852 mips_ls2.falu1_turn_p = false;
12856 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu2_core_unit_code))
12857 mips_ls2.falu1_turn_p = true;
12860 if (recog_memoized (insn) >= 0)
12861 mips_ls2.cycle_has_multi_p |= (get_attr_type (insn) == TYPE_MULTI);
12864 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
12867 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12868 rtx insn, int more)
12870 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
12871 if (USEFUL_INSN_P (insn))
12873 if (get_attr_type (insn) != TYPE_GHOST)
12875 if (!reload_completed && TUNE_MACC_CHAINS)
12876 mips_macc_chains_record (insn);
12877 vr4130_last_insn = insn;
12879 mips_74k_agen_init (insn);
12880 else if (TUNE_LOONGSON_2EF)
12881 mips_ls2_variable_issue (insn);
12884 /* Instructions of type 'multi' should all be split before
12885 the second scheduling pass. */
12886 gcc_assert (!reload_completed
12887 || recog_memoized (insn) < 0
12888 || get_attr_type (insn) != TYPE_MULTI);
12890 cached_can_issue_more = more;
12894 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
12895 return the first operand of the associated PREF or PREFX insn. */
12898 mips_prefetch_cookie (rtx write, rtx locality)
12900 /* store_streamed / load_streamed. */
12901 if (INTVAL (locality) <= 0)
12902 return GEN_INT (INTVAL (write) + 4);
12904 /* store / load. */
12905 if (INTVAL (locality) <= 2)
12908 /* store_retained / load_retained. */
12909 return GEN_INT (INTVAL (write) + 6);
12912 /* Flags that indicate when a built-in function is available.
12914 BUILTIN_AVAIL_NON_MIPS16
12915 The function is available on the current target, but only
12916 in non-MIPS16 mode. */
12917 #define BUILTIN_AVAIL_NON_MIPS16 1
12919 /* Declare an availability predicate for built-in functions that
12920 require non-MIPS16 mode and also require COND to be true.
12921 NAME is the main part of the predicate's name. */
12922 #define AVAIL_NON_MIPS16(NAME, COND) \
12923 static unsigned int \
12924 mips_builtin_avail_##NAME (void) \
12926 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
12929 /* This structure describes a single built-in function. */
12930 struct mips_builtin_description {
12931 /* The code of the main .md file instruction. See mips_builtin_type
12932 for more information. */
12933 enum insn_code icode;
12935 /* The floating-point comparison code to use with ICODE, if any. */
12936 enum mips_fp_condition cond;
12938 /* The name of the built-in function. */
12941 /* Specifies how the function should be expanded. */
12942 enum mips_builtin_type builtin_type;
12944 /* The function's prototype. */
12945 enum mips_function_type function_type;
12947 /* Whether the function is available. */
12948 unsigned int (*avail) (void);
12951 AVAIL_NON_MIPS16 (paired_single, TARGET_PAIRED_SINGLE_FLOAT)
12952 AVAIL_NON_MIPS16 (sb1_paired_single, TARGET_SB1 && TARGET_PAIRED_SINGLE_FLOAT)
12953 AVAIL_NON_MIPS16 (mips3d, TARGET_MIPS3D)
12954 AVAIL_NON_MIPS16 (dsp, TARGET_DSP)
12955 AVAIL_NON_MIPS16 (dspr2, TARGET_DSPR2)
12956 AVAIL_NON_MIPS16 (dsp_32, !TARGET_64BIT && TARGET_DSP)
12957 AVAIL_NON_MIPS16 (dsp_64, TARGET_64BIT && TARGET_DSP)
12958 AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2)
12959 AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS)
12960 AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
12962 /* Construct a mips_builtin_description from the given arguments.
12964 INSN is the name of the associated instruction pattern, without the
12965 leading CODE_FOR_mips_.
12967 CODE is the floating-point condition code associated with the
12968 function. It can be 'f' if the field is not applicable.
12970 NAME is the name of the function itself, without the leading
12973 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
12975 AVAIL is the name of the availability predicate, without the leading
12976 mips_builtin_avail_. */
12977 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
12978 FUNCTION_TYPE, AVAIL) \
12979 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
12980 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
12981 mips_builtin_avail_ ## AVAIL }
12983 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
12984 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
12985 are as for MIPS_BUILTIN. */
12986 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
12987 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
12989 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
12990 are subject to mips_builtin_avail_<AVAIL>. */
12991 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
12992 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
12993 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
12994 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
12995 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
12997 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
12998 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
12999 while the any and all forms are subject to mips_builtin_avail_mips3d. */
13000 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
13001 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
13002 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
13004 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
13005 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
13007 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
13008 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
13010 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
13011 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
13014 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
13015 are subject to mips_builtin_avail_mips3d. */
13016 #define CMP_4S_BUILTINS(INSN, COND) \
13017 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
13018 MIPS_BUILTIN_CMP_ANY, \
13019 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
13020 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
13021 MIPS_BUILTIN_CMP_ALL, \
13022 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
13024 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
13025 instruction requires mips_builtin_avail_<AVAIL>. */
13026 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
13027 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
13028 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
13030 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
13031 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
13034 /* Define all the built-in functions related to C.cond.fmt condition COND. */
13035 #define CMP_BUILTINS(COND) \
13036 MOVTF_BUILTINS (c, COND, paired_single), \
13037 MOVTF_BUILTINS (cabs, COND, mips3d), \
13038 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
13039 CMP_PS_BUILTINS (c, COND, paired_single), \
13040 CMP_PS_BUILTINS (cabs, COND, mips3d), \
13041 CMP_4S_BUILTINS (c, COND), \
13042 CMP_4S_BUILTINS (cabs, COND)
13044 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
13045 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
13046 and AVAIL are as for MIPS_BUILTIN. */
13047 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
13048 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
13049 FUNCTION_TYPE, AVAIL)
13051 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
13052 branch instruction. AVAIL is as for MIPS_BUILTIN. */
13053 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
13054 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
13055 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
13057 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
13058 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
13059 builtin_description field. */
13060 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
13061 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
13062 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
13063 FUNCTION_TYPE, mips_builtin_avail_loongson }
13065 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
13066 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
13067 builtin_description field. */
13068 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
13069 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
13071 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
13072 We use functions of this form when the same insn can be usefully applied
13073 to more than one datatype. */
13074 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
13075 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
13077 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
13078 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
13079 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
13080 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
13081 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
13082 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
13083 #define CODE_FOR_mips_mult CODE_FOR_mulsidi3_32bit
13084 #define CODE_FOR_mips_multu CODE_FOR_umulsidi3_32bit
13086 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
13087 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
13088 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
13089 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
13090 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
13091 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
13092 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
13093 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
13094 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
13095 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
13096 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
13097 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
13098 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
13099 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
13100 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
13101 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
13102 #define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3
13103 #define CODE_FOR_loongson_psllh CODE_FOR_ashlv4hi3
13104 #define CODE_FOR_loongson_psllw CODE_FOR_ashlv2si3
13105 #define CODE_FOR_loongson_psrlh CODE_FOR_lshrv4hi3
13106 #define CODE_FOR_loongson_psrlw CODE_FOR_lshrv2si3
13107 #define CODE_FOR_loongson_psrah CODE_FOR_ashrv4hi3
13108 #define CODE_FOR_loongson_psraw CODE_FOR_ashrv2si3
13109 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
13110 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
13111 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
13112 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
13113 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
13114 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
13115 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
13117 static const struct mips_builtin_description mips_builtins[] = {
13118 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13119 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13120 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13121 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13122 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, paired_single),
13123 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, paired_single),
13124 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, paired_single),
13125 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, paired_single),
13127 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT, paired_single),
13128 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13129 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13130 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
13131 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, mips3d),
13133 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, mips3d),
13134 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, mips3d),
13135 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
13136 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
13137 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
13138 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13140 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, mips3d),
13141 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, mips3d),
13142 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
13143 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
13144 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
13145 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13147 MIPS_FP_CONDITIONS (CMP_BUILTINS),
13149 /* Built-in functions for the SB-1 processor. */
13150 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, sb1_paired_single),
13152 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
13153 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13154 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13155 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
13156 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13157 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13158 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13159 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13160 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
13161 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13162 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13163 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, dsp),
13164 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, dsp),
13165 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, dsp),
13166 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, dsp),
13167 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, dsp),
13168 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, dsp),
13169 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
13170 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
13171 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
13172 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
13173 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, dsp),
13174 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, dsp),
13175 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
13176 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
13177 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
13178 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
13179 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
13180 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
13181 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
13182 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
13183 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
13184 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
13185 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
13186 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
13187 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
13188 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
13189 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
13190 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, dsp),
13191 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
13192 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
13193 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13194 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
13195 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
13196 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, dsp),
13197 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, dsp),
13198 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, dsp),
13199 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, dsp),
13200 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
13201 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
13202 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
13203 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
13204 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
13205 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
13206 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
13207 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
13208 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
13209 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13210 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13211 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13212 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, dsp),
13213 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, dsp),
13214 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_POINTER_SI, dsp),
13215 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_POINTER_SI, dsp),
13216 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_POINTER_SI, dsp),
13217 BPOSGE_BUILTIN (32, dsp),
13219 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
13220 DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, dspr2),
13221 DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13222 DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13223 DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
13224 DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
13225 DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
13226 DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
13227 DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
13228 DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
13229 DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
13230 DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13231 DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13232 DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13233 DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13234 DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13235 DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dspr2),
13236 DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
13237 DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
13238 DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
13239 DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
13240 DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
13241 DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, dspr2),
13242 DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13243 DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13244 DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
13245 DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
13246 DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13247 DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13248 DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13249 DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13250 DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13251 DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13252 DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13253 DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13255 /* Built-in functions for the DSP ASE (32-bit only). */
13256 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
13257 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
13258 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
13259 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
13260 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13261 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13262 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13263 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
13264 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
13265 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13266 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13267 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13268 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13269 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
13270 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
13271 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
13272 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, dsp_32),
13273 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, dsp_32),
13274 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, dsp_32),
13275 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, dsp_32),
13276 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, dsp_32),
13277 DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
13278 DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32),
13279 DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
13280 DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32),
13281 DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, dsp_32),
13282 DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, dsp_32),
13284 /* Built-in functions for the DSP ASE (64-bit only). */
13285 DIRECT_BUILTIN (ldx, MIPS_DI_FTYPE_POINTER_SI, dsp_64),
13287 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
13288 DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13289 DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13290 DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13291 DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13292 DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13293 DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13294 DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13295 DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13296 DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13298 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
13299 LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI),
13300 LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI),
13301 LOONGSON_BUILTIN (packushb, MIPS_UV8QI_FTYPE_UV4HI_UV4HI),
13302 LOONGSON_BUILTIN_SUFFIX (paddw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13303 LOONGSON_BUILTIN_SUFFIX (paddh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13304 LOONGSON_BUILTIN_SUFFIX (paddb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13305 LOONGSON_BUILTIN_SUFFIX (paddw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13306 LOONGSON_BUILTIN_SUFFIX (paddh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13307 LOONGSON_BUILTIN_SUFFIX (paddb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13308 LOONGSON_BUILTIN_SUFFIX (paddd, u, MIPS_UDI_FTYPE_UDI_UDI),
13309 LOONGSON_BUILTIN_SUFFIX (paddd, s, MIPS_DI_FTYPE_DI_DI),
13310 LOONGSON_BUILTIN (paddsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13311 LOONGSON_BUILTIN (paddsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
13312 LOONGSON_BUILTIN (paddush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13313 LOONGSON_BUILTIN (paddusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13314 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_ud, MIPS_UDI_FTYPE_UDI_UDI),
13315 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_uw, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13316 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_uh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13317 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_ub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13318 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_sd, MIPS_DI_FTYPE_DI_DI),
13319 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_sw, MIPS_V2SI_FTYPE_V2SI_V2SI),
13320 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_sh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13321 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_sb, MIPS_V8QI_FTYPE_V8QI_V8QI),
13322 LOONGSON_BUILTIN (pavgh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13323 LOONGSON_BUILTIN (pavgb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13324 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13325 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13326 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13327 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13328 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13329 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13330 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13331 LOONGSON_BUILTIN_SUFFIX (pcmpgth, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13332 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13333 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13334 LOONGSON_BUILTIN_SUFFIX (pcmpgth, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13335 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13336 LOONGSON_BUILTIN_SUFFIX (pextrh, u, MIPS_UV4HI_FTYPE_UV4HI_USI),
13337 LOONGSON_BUILTIN_SUFFIX (pextrh, s, MIPS_V4HI_FTYPE_V4HI_USI),
13338 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13339 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13340 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13341 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13342 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13343 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13344 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13345 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13346 LOONGSON_BUILTIN (pmaddhw, MIPS_V2SI_FTYPE_V4HI_V4HI),
13347 LOONGSON_BUILTIN (pmaxsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13348 LOONGSON_BUILTIN (pmaxub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13349 LOONGSON_BUILTIN (pminsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13350 LOONGSON_BUILTIN (pminub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13351 LOONGSON_BUILTIN_SUFFIX (pmovmskb, u, MIPS_UV8QI_FTYPE_UV8QI),
13352 LOONGSON_BUILTIN_SUFFIX (pmovmskb, s, MIPS_V8QI_FTYPE_V8QI),
13353 LOONGSON_BUILTIN (pmulhuh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13354 LOONGSON_BUILTIN (pmulhh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13355 LOONGSON_BUILTIN (pmullh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13356 LOONGSON_BUILTIN (pmuluw, MIPS_UDI_FTYPE_UV2SI_UV2SI),
13357 LOONGSON_BUILTIN (pasubub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13358 LOONGSON_BUILTIN (biadd, MIPS_UV4HI_FTYPE_UV8QI),
13359 LOONGSON_BUILTIN (psadbh, MIPS_UV4HI_FTYPE_UV8QI_UV8QI),
13360 LOONGSON_BUILTIN_SUFFIX (pshufh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
13361 LOONGSON_BUILTIN_SUFFIX (pshufh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
13362 LOONGSON_BUILTIN_SUFFIX (psllh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
13363 LOONGSON_BUILTIN_SUFFIX (psllh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
13364 LOONGSON_BUILTIN_SUFFIX (psllw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
13365 LOONGSON_BUILTIN_SUFFIX (psllw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
13366 LOONGSON_BUILTIN_SUFFIX (psrah, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
13367 LOONGSON_BUILTIN_SUFFIX (psrah, s, MIPS_V4HI_FTYPE_V4HI_UQI),
13368 LOONGSON_BUILTIN_SUFFIX (psraw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
13369 LOONGSON_BUILTIN_SUFFIX (psraw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
13370 LOONGSON_BUILTIN_SUFFIX (psrlh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
13371 LOONGSON_BUILTIN_SUFFIX (psrlh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
13372 LOONGSON_BUILTIN_SUFFIX (psrlw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
13373 LOONGSON_BUILTIN_SUFFIX (psrlw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
13374 LOONGSON_BUILTIN_SUFFIX (psubw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13375 LOONGSON_BUILTIN_SUFFIX (psubh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13376 LOONGSON_BUILTIN_SUFFIX (psubb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13377 LOONGSON_BUILTIN_SUFFIX (psubw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13378 LOONGSON_BUILTIN_SUFFIX (psubh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13379 LOONGSON_BUILTIN_SUFFIX (psubb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13380 LOONGSON_BUILTIN_SUFFIX (psubd, u, MIPS_UDI_FTYPE_UDI_UDI),
13381 LOONGSON_BUILTIN_SUFFIX (psubd, s, MIPS_DI_FTYPE_DI_DI),
13382 LOONGSON_BUILTIN (psubsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13383 LOONGSON_BUILTIN (psubsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
13384 LOONGSON_BUILTIN (psubush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13385 LOONGSON_BUILTIN (psubusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13386 LOONGSON_BUILTIN_SUFFIX (punpckhbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13387 LOONGSON_BUILTIN_SUFFIX (punpckhhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13388 LOONGSON_BUILTIN_SUFFIX (punpckhwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13389 LOONGSON_BUILTIN_SUFFIX (punpckhbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13390 LOONGSON_BUILTIN_SUFFIX (punpckhhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13391 LOONGSON_BUILTIN_SUFFIX (punpckhwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13392 LOONGSON_BUILTIN_SUFFIX (punpcklbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13393 LOONGSON_BUILTIN_SUFFIX (punpcklhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13394 LOONGSON_BUILTIN_SUFFIX (punpcklwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13395 LOONGSON_BUILTIN_SUFFIX (punpcklbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13396 LOONGSON_BUILTIN_SUFFIX (punpcklhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13397 LOONGSON_BUILTIN_SUFFIX (punpcklwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13399 /* Sundry other built-in functions. */
13400 DIRECT_NO_TARGET_BUILTIN (cache, MIPS_VOID_FTYPE_SI_CVPOINTER, cache)
13403 /* Index I is the function declaration for mips_builtins[I], or null if the
13404 function isn't defined on this target. */
13405 static GTY(()) tree mips_builtin_decls[ARRAY_SIZE (mips_builtins)];
13407 /* MODE is a vector mode whose elements have type TYPE. Return the type
13408 of the vector itself. */
13411 mips_builtin_vector_type (tree type, enum machine_mode mode)
13413 static tree types[2 * (int) MAX_MACHINE_MODE];
13416 mode_index = (int) mode;
13418 if (TREE_CODE (type) == INTEGER_TYPE && TYPE_UNSIGNED (type))
13419 mode_index += MAX_MACHINE_MODE;
13421 if (types[mode_index] == NULL_TREE)
13422 types[mode_index] = build_vector_type_for_mode (type, mode);
13423 return types[mode_index];
13426 /* Return a type for 'const volatile void *'. */
13429 mips_build_cvpointer_type (void)
13433 if (cache == NULL_TREE)
13434 cache = build_pointer_type (build_qualified_type
13436 TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE));
13440 /* Source-level argument types. */
13441 #define MIPS_ATYPE_VOID void_type_node
13442 #define MIPS_ATYPE_INT integer_type_node
13443 #define MIPS_ATYPE_POINTER ptr_type_node
13444 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
13446 /* Standard mode-based argument types. */
13447 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
13448 #define MIPS_ATYPE_SI intSI_type_node
13449 #define MIPS_ATYPE_USI unsigned_intSI_type_node
13450 #define MIPS_ATYPE_DI intDI_type_node
13451 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
13452 #define MIPS_ATYPE_SF float_type_node
13453 #define MIPS_ATYPE_DF double_type_node
13455 /* Vector argument types. */
13456 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
13457 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
13458 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
13459 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
13460 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
13461 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
13462 #define MIPS_ATYPE_UV2SI \
13463 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
13464 #define MIPS_ATYPE_UV4HI \
13465 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
13466 #define MIPS_ATYPE_UV8QI \
13467 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
13469 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
13470 their associated MIPS_ATYPEs. */
13471 #define MIPS_FTYPE_ATYPES1(A, B) \
13472 MIPS_ATYPE_##A, MIPS_ATYPE_##B
13474 #define MIPS_FTYPE_ATYPES2(A, B, C) \
13475 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
13477 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
13478 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
13480 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
13481 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
13484 /* Return the function type associated with function prototype TYPE. */
13487 mips_build_function_type (enum mips_function_type type)
13489 static tree types[(int) MIPS_MAX_FTYPE_MAX];
13491 if (types[(int) type] == NULL_TREE)
13494 #define DEF_MIPS_FTYPE(NUM, ARGS) \
13495 case MIPS_FTYPE_NAME##NUM ARGS: \
13496 types[(int) type] \
13497 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
13500 #include "config/mips/mips-ftypes.def"
13501 #undef DEF_MIPS_FTYPE
13503 gcc_unreachable ();
13506 return types[(int) type];
13509 /* Implement TARGET_INIT_BUILTINS. */
13512 mips_init_builtins (void)
13514 const struct mips_builtin_description *d;
13517 /* Iterate through all of the bdesc arrays, initializing all of the
13518 builtin functions. */
13519 for (i = 0; i < ARRAY_SIZE (mips_builtins); i++)
13521 d = &mips_builtins[i];
13523 mips_builtin_decls[i]
13524 = add_builtin_function (d->name,
13525 mips_build_function_type (d->function_type),
13526 i, BUILT_IN_MD, NULL, NULL);
13530 /* Implement TARGET_BUILTIN_DECL. */
13533 mips_builtin_decl (unsigned int code, bool initialize_p ATTRIBUTE_UNUSED)
13535 if (code >= ARRAY_SIZE (mips_builtins))
13536 return error_mark_node;
13537 return mips_builtin_decls[code];
13540 /* Take argument ARGNO from EXP's argument list and convert it into
13541 an expand operand. Store the operand in *OP. */
13544 mips_prepare_builtin_arg (struct expand_operand *op, tree exp,
13545 unsigned int argno)
13550 arg = CALL_EXPR_ARG (exp, argno);
13551 value = expand_normal (arg);
13552 create_input_operand (op, value, TYPE_MODE (TREE_TYPE (arg)));
13555 /* Expand instruction ICODE as part of a built-in function sequence.
13556 Use the first NOPS elements of OPS as the instruction's operands.
13557 HAS_TARGET_P is true if operand 0 is a target; it is false if the
13558 instruction has no target.
13560 Return the target rtx if HAS_TARGET_P, otherwise return const0_rtx. */
13563 mips_expand_builtin_insn (enum insn_code icode, unsigned int nops,
13564 struct expand_operand *ops, bool has_target_p)
13566 if (!maybe_expand_insn (icode, nops, ops))
13568 error ("invalid argument to built-in function");
13569 return has_target_p ? gen_reg_rtx (ops[0].mode) : const0_rtx;
13571 return has_target_p ? ops[0].value : const0_rtx;
13574 /* Expand a floating-point comparison for built-in function call EXP.
13575 The first NARGS arguments are the values to be compared. ICODE is
13576 the .md pattern that does the comparison and COND is the condition
13577 that is being tested. Return an rtx for the result. */
13580 mips_expand_builtin_compare_1 (enum insn_code icode,
13581 enum mips_fp_condition cond,
13582 tree exp, int nargs)
13584 struct expand_operand ops[MAX_RECOG_OPERANDS];
13587 /* The instruction should have a target operand, an operand for each
13588 argument, and an operand for COND. */
13589 gcc_assert (nargs + 2 == insn_data[(int) icode].n_generator_args);
13592 create_output_operand (&ops[opno++], NULL_RTX,
13593 insn_data[(int) icode].operand[0].mode);
13594 for (argno = 0; argno < nargs; argno++)
13595 mips_prepare_builtin_arg (&ops[opno++], exp, argno);
13596 create_integer_operand (&ops[opno++], (int) cond);
13597 return mips_expand_builtin_insn (icode, opno, ops, true);
13600 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
13601 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
13602 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
13603 suggests a good place to put the result. */
13606 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
13609 struct expand_operand ops[MAX_RECOG_OPERANDS];
13612 /* Map any target to operand 0. */
13615 create_output_operand (&ops[opno++], target, TYPE_MODE (TREE_TYPE (exp)));
13617 /* Map the arguments to the other operands. */
13618 gcc_assert (opno + call_expr_nargs (exp)
13619 == insn_data[icode].n_generator_args);
13620 for (argno = 0; argno < call_expr_nargs (exp); argno++)
13621 mips_prepare_builtin_arg (&ops[opno++], exp, argno);
13623 return mips_expand_builtin_insn (icode, opno, ops, has_target_p);
13626 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
13627 function; TYPE says which. EXP is the CALL_EXPR that calls the
13628 function, ICODE is the instruction that should be used to compare
13629 the first two arguments, and COND is the condition it should test.
13630 TARGET, if nonnull, suggests a good place to put the result. */
13633 mips_expand_builtin_movtf (enum mips_builtin_type type,
13634 enum insn_code icode, enum mips_fp_condition cond,
13635 rtx target, tree exp)
13637 struct expand_operand ops[4];
13640 cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp, 2);
13641 create_output_operand (&ops[0], target, TYPE_MODE (TREE_TYPE (exp)));
13642 if (type == MIPS_BUILTIN_MOVT)
13644 mips_prepare_builtin_arg (&ops[2], exp, 2);
13645 mips_prepare_builtin_arg (&ops[1], exp, 3);
13649 mips_prepare_builtin_arg (&ops[1], exp, 2);
13650 mips_prepare_builtin_arg (&ops[2], exp, 3);
13652 create_fixed_operand (&ops[3], cmp_result);
13653 return mips_expand_builtin_insn (CODE_FOR_mips_cond_move_tf_ps,
13657 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
13658 into TARGET otherwise. Return TARGET. */
13661 mips_builtin_branch_and_move (rtx condition, rtx target,
13662 rtx value_if_true, rtx value_if_false)
13664 rtx true_label, done_label;
13666 true_label = gen_label_rtx ();
13667 done_label = gen_label_rtx ();
13669 /* First assume that CONDITION is false. */
13670 mips_emit_move (target, value_if_false);
13672 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
13673 emit_jump_insn (gen_condjump (condition, true_label));
13674 emit_jump_insn (gen_jump (done_label));
13677 /* Fix TARGET if CONDITION is true. */
13678 emit_label (true_label);
13679 mips_emit_move (target, value_if_true);
13681 emit_label (done_label);
13685 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
13686 the CALL_EXPR that calls the function, ICODE is the code of the
13687 comparison instruction, and COND is the condition it should test.
13688 TARGET, if nonnull, suggests a good place to put the boolean result. */
13691 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
13692 enum insn_code icode, enum mips_fp_condition cond,
13693 rtx target, tree exp)
13695 rtx offset, condition, cmp_result;
13697 if (target == 0 || GET_MODE (target) != SImode)
13698 target = gen_reg_rtx (SImode);
13699 cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp,
13700 call_expr_nargs (exp));
13702 /* If the comparison sets more than one register, we define the result
13703 to be 0 if all registers are false and -1 if all registers are true.
13704 The value of the complete result is indeterminate otherwise. */
13705 switch (builtin_type)
13707 case MIPS_BUILTIN_CMP_ALL:
13708 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
13709 return mips_builtin_branch_and_move (condition, target,
13710 const0_rtx, const1_rtx);
13712 case MIPS_BUILTIN_CMP_UPPER:
13713 case MIPS_BUILTIN_CMP_LOWER:
13714 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
13715 condition = gen_single_cc (cmp_result, offset);
13716 return mips_builtin_branch_and_move (condition, target,
13717 const1_rtx, const0_rtx);
13720 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
13721 return mips_builtin_branch_and_move (condition, target,
13722 const1_rtx, const0_rtx);
13726 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
13727 if nonnull, suggests a good place to put the boolean result. */
13730 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
13732 rtx condition, cmp_result;
13735 if (target == 0 || GET_MODE (target) != SImode)
13736 target = gen_reg_rtx (SImode);
13738 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
13740 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
13745 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
13746 return mips_builtin_branch_and_move (condition, target,
13747 const1_rtx, const0_rtx);
13750 /* Implement TARGET_EXPAND_BUILTIN. */
13753 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
13754 enum machine_mode mode, int ignore)
13757 unsigned int fcode, avail;
13758 const struct mips_builtin_description *d;
13760 fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
13761 fcode = DECL_FUNCTION_CODE (fndecl);
13762 gcc_assert (fcode < ARRAY_SIZE (mips_builtins));
13763 d = &mips_builtins[fcode];
13764 avail = d->avail ();
13765 gcc_assert (avail != 0);
13768 error ("built-in function %qE not supported for MIPS16",
13769 DECL_NAME (fndecl));
13770 return ignore ? const0_rtx : CONST0_RTX (mode);
13772 switch (d->builtin_type)
13774 case MIPS_BUILTIN_DIRECT:
13775 return mips_expand_builtin_direct (d->icode, target, exp, true);
13777 case MIPS_BUILTIN_DIRECT_NO_TARGET:
13778 return mips_expand_builtin_direct (d->icode, target, exp, false);
13780 case MIPS_BUILTIN_MOVT:
13781 case MIPS_BUILTIN_MOVF:
13782 return mips_expand_builtin_movtf (d->builtin_type, d->icode,
13783 d->cond, target, exp);
13785 case MIPS_BUILTIN_CMP_ANY:
13786 case MIPS_BUILTIN_CMP_ALL:
13787 case MIPS_BUILTIN_CMP_UPPER:
13788 case MIPS_BUILTIN_CMP_LOWER:
13789 case MIPS_BUILTIN_CMP_SINGLE:
13790 return mips_expand_builtin_compare (d->builtin_type, d->icode,
13791 d->cond, target, exp);
13793 case MIPS_BUILTIN_BPOSGE32:
13794 return mips_expand_builtin_bposge (d->builtin_type, target);
13796 gcc_unreachable ();
13799 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
13800 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
13801 struct mips16_constant {
13802 struct mips16_constant *next;
13805 enum machine_mode mode;
13808 /* Information about an incomplete MIPS16 constant pool. FIRST is the
13809 first constant, HIGHEST_ADDRESS is the highest address that the first
13810 byte of the pool can have, and INSN_ADDRESS is the current instruction
13812 struct mips16_constant_pool {
13813 struct mips16_constant *first;
13814 int highest_address;
13818 /* Add constant VALUE to POOL and return its label. MODE is the
13819 value's mode (used for CONST_INTs, etc.). */
13822 mips16_add_constant (struct mips16_constant_pool *pool,
13823 rtx value, enum machine_mode mode)
13825 struct mips16_constant **p, *c;
13826 bool first_of_size_p;
13828 /* See whether the constant is already in the pool. If so, return the
13829 existing label, otherwise leave P pointing to the place where the
13830 constant should be added.
13832 Keep the pool sorted in increasing order of mode size so that we can
13833 reduce the number of alignments needed. */
13834 first_of_size_p = true;
13835 for (p = &pool->first; *p != 0; p = &(*p)->next)
13837 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
13838 return (*p)->label;
13839 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
13841 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
13842 first_of_size_p = false;
13845 /* In the worst case, the constant needed by the earliest instruction
13846 will end up at the end of the pool. The entire pool must then be
13847 accessible from that instruction.
13849 When adding the first constant, set the pool's highest address to
13850 the address of the first out-of-range byte. Adjust this address
13851 downwards each time a new constant is added. */
13852 if (pool->first == 0)
13853 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
13854 of the instruction with the lowest two bits clear. The base PC
13855 value for LDPC has the lowest three bits clear. Assume the worst
13856 case here; namely that the PC-relative instruction occupies the
13857 last 2 bytes in an aligned word. */
13858 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
13859 pool->highest_address -= GET_MODE_SIZE (mode);
13860 if (first_of_size_p)
13861 /* Take into account the worst possible padding due to alignment. */
13862 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
13864 /* Create a new entry. */
13865 c = XNEW (struct mips16_constant);
13868 c->label = gen_label_rtx ();
13875 /* Output constant VALUE after instruction INSN and return the last
13876 instruction emitted. MODE is the mode of the constant. */
13879 mips16_emit_constants_1 (enum machine_mode mode, rtx value, rtx insn)
13881 if (SCALAR_INT_MODE_P (mode) || ALL_SCALAR_FIXED_POINT_MODE_P (mode))
13883 rtx size = GEN_INT (GET_MODE_SIZE (mode));
13884 return emit_insn_after (gen_consttable_int (value, size), insn);
13887 if (SCALAR_FLOAT_MODE_P (mode))
13888 return emit_insn_after (gen_consttable_float (value), insn);
13890 if (VECTOR_MODE_P (mode))
13894 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
13895 insn = mips16_emit_constants_1 (GET_MODE_INNER (mode),
13896 CONST_VECTOR_ELT (value, i), insn);
13900 gcc_unreachable ();
13903 /* Dump out the constants in CONSTANTS after INSN. */
13906 mips16_emit_constants (struct mips16_constant *constants, rtx insn)
13908 struct mips16_constant *c, *next;
13912 for (c = constants; c != NULL; c = next)
13914 /* If necessary, increase the alignment of PC. */
13915 if (align < GET_MODE_SIZE (c->mode))
13917 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
13918 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
13920 align = GET_MODE_SIZE (c->mode);
13922 insn = emit_label_after (c->label, insn);
13923 insn = mips16_emit_constants_1 (c->mode, c->value, insn);
13929 emit_barrier_after (insn);
13932 /* Return the length of instruction INSN. */
13935 mips16_insn_length (rtx insn)
13939 rtx body = PATTERN (insn);
13940 if (GET_CODE (body) == ADDR_VEC)
13941 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
13942 if (GET_CODE (body) == ADDR_DIFF_VEC)
13943 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
13945 return get_attr_length (insn);
13948 /* If *X is a symbolic constant that refers to the constant pool, add
13949 the constant to POOL and rewrite *X to use the constant's label. */
13952 mips16_rewrite_pool_constant (struct mips16_constant_pool *pool, rtx *x)
13954 rtx base, offset, label;
13956 split_const (*x, &base, &offset);
13957 if (GET_CODE (base) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (base))
13959 label = mips16_add_constant (pool, get_pool_constant (base),
13960 get_pool_mode (base));
13961 base = gen_rtx_LABEL_REF (Pmode, label);
13962 *x = mips_unspec_address_offset (base, offset, SYMBOL_PC_RELATIVE);
13966 /* This structure is used to communicate with mips16_rewrite_pool_refs.
13967 INSN is the instruction we're rewriting and POOL points to the current
13969 struct mips16_rewrite_pool_refs_info {
13971 struct mips16_constant_pool *pool;
13974 /* Rewrite *X so that constant pool references refer to the constant's
13975 label instead. DATA points to a mips16_rewrite_pool_refs_info
13979 mips16_rewrite_pool_refs (rtx *x, void *data)
13981 struct mips16_rewrite_pool_refs_info *info =
13982 (struct mips16_rewrite_pool_refs_info *) data;
13984 if (force_to_mem_operand (*x, Pmode))
13986 rtx mem = force_const_mem (GET_MODE (*x), *x);
13987 validate_change (info->insn, x, mem, false);
13992 mips16_rewrite_pool_constant (info->pool, &XEXP (*x, 0));
13996 /* Don't rewrite the __mips16_rdwr symbol. */
13997 if (GET_CODE (*x) == UNSPEC && XINT (*x, 1) == UNSPEC_TLS_GET_TP)
14000 if (TARGET_MIPS16_TEXT_LOADS)
14001 mips16_rewrite_pool_constant (info->pool, x);
14003 return GET_CODE (*x) == CONST ? -1 : 0;
14006 /* Return whether CFG is used in mips_reorg. */
14009 mips_cfg_in_reorg (void)
14011 return (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
14012 || TARGET_RELAX_PIC_CALLS);
14015 /* Build MIPS16 constant pools. */
14018 mips16_lay_out_constants (void)
14020 struct mips16_constant_pool pool;
14021 struct mips16_rewrite_pool_refs_info info;
14024 if (!TARGET_MIPS16_PCREL_LOADS)
14027 if (mips_cfg_in_reorg ())
14028 split_all_insns ();
14030 split_all_insns_noflow ();
14032 memset (&pool, 0, sizeof (pool));
14033 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
14035 /* Rewrite constant pool references in INSN. */
14036 if (USEFUL_INSN_P (insn))
14040 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &info);
14043 pool.insn_address += mips16_insn_length (insn);
14045 if (pool.first != NULL)
14047 /* If there are no natural barriers between the first user of
14048 the pool and the highest acceptable address, we'll need to
14049 create a new instruction to jump around the constant pool.
14050 In the worst case, this instruction will be 4 bytes long.
14052 If it's too late to do this transformation after INSN,
14053 do it immediately before INSN. */
14054 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
14058 label = gen_label_rtx ();
14060 jump = emit_jump_insn_before (gen_jump (label), insn);
14061 JUMP_LABEL (jump) = label;
14062 LABEL_NUSES (label) = 1;
14063 barrier = emit_barrier_after (jump);
14065 emit_label_after (label, barrier);
14066 pool.insn_address += 4;
14069 /* See whether the constant pool is now out of range of the first
14070 user. If so, output the constants after the previous barrier.
14071 Note that any instructions between BARRIER and INSN (inclusive)
14072 will use negative offsets to refer to the pool. */
14073 if (pool.insn_address > pool.highest_address)
14075 mips16_emit_constants (pool.first, barrier);
14079 else if (BARRIER_P (insn))
14083 mips16_emit_constants (pool.first, get_last_insn ());
14086 /* Return true if it is worth r10k_simplify_address's while replacing
14087 an address with X. We are looking for constants, and for addresses
14088 at a known offset from the incoming stack pointer. */
14091 r10k_simplified_address_p (rtx x)
14093 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
14095 return x == virtual_incoming_args_rtx || CONSTANT_P (x);
14098 /* X is an expression that appears in INSN. Try to use the UD chains
14099 to simplify it, returning the simplified form on success and the
14100 original form otherwise. Replace the incoming value of $sp with
14101 virtual_incoming_args_rtx (which should never occur in X otherwise). */
14104 r10k_simplify_address (rtx x, rtx insn)
14106 rtx newx, op0, op1, set, def_insn, note;
14108 struct df_link *defs;
14113 op0 = r10k_simplify_address (XEXP (x, 0), insn);
14114 if (op0 != XEXP (x, 0))
14115 newx = simplify_gen_unary (GET_CODE (x), GET_MODE (x),
14116 op0, GET_MODE (XEXP (x, 0)));
14118 else if (BINARY_P (x))
14120 op0 = r10k_simplify_address (XEXP (x, 0), insn);
14121 op1 = r10k_simplify_address (XEXP (x, 1), insn);
14122 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
14123 newx = simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
14125 else if (GET_CODE (x) == LO_SUM)
14127 /* LO_SUMs can be offset from HIGHs, if we know they won't
14128 overflow. See mips_classify_address for the rationale behind
14130 op0 = r10k_simplify_address (XEXP (x, 0), insn);
14131 if (GET_CODE (op0) == HIGH)
14132 newx = XEXP (x, 1);
14134 else if (REG_P (x))
14136 /* Uses are recorded by regno_reg_rtx, not X itself. */
14137 use = df_find_use (insn, regno_reg_rtx[REGNO (x)]);
14139 defs = DF_REF_CHAIN (use);
14141 /* Require a single definition. */
14142 if (defs && defs->next == NULL)
14145 if (DF_REF_IS_ARTIFICIAL (def))
14147 /* Replace the incoming value of $sp with
14148 virtual_incoming_args_rtx. */
14149 if (x == stack_pointer_rtx
14150 && DF_REF_BB (def) == ENTRY_BLOCK_PTR)
14151 newx = virtual_incoming_args_rtx;
14153 else if (dominated_by_p (CDI_DOMINATORS, DF_REF_BB (use),
14156 /* Make sure that DEF_INSN is a single set of REG. */
14157 def_insn = DF_REF_INSN (def);
14158 if (NONJUMP_INSN_P (def_insn))
14160 set = single_set (def_insn);
14161 if (set && rtx_equal_p (SET_DEST (set), x))
14163 /* Prefer to use notes, since the def-use chains
14164 are often shorter. */
14165 note = find_reg_equal_equiv_note (def_insn);
14167 newx = XEXP (note, 0);
14169 newx = SET_SRC (set);
14170 newx = r10k_simplify_address (newx, def_insn);
14176 if (newx && r10k_simplified_address_p (newx))
14181 /* Return true if ADDRESS is known to be an uncached address
14182 on R10K systems. */
14185 r10k_uncached_address_p (unsigned HOST_WIDE_INT address)
14187 unsigned HOST_WIDE_INT upper;
14189 /* Check for KSEG1. */
14190 if (address + 0x60000000 < 0x20000000)
14193 /* Check for uncached XKPHYS addresses. */
14194 if (Pmode == DImode)
14196 upper = (address >> 40) & 0xf9ffff;
14197 if (upper == 0x900000 || upper == 0xb80000)
14203 /* Return true if we can prove that an access to address X in instruction
14204 INSN would be safe from R10K speculation. This X is a general
14205 expression; it might not be a legitimate address. */
14208 r10k_safe_address_p (rtx x, rtx insn)
14211 HOST_WIDE_INT offset_val;
14213 x = r10k_simplify_address (x, insn);
14215 /* Check for references to the stack frame. It doesn't really matter
14216 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
14217 allows us to assume that accesses to any part of the eventual frame
14218 is safe from speculation at any point in the function. */
14219 mips_split_plus (x, &base, &offset_val);
14220 if (base == virtual_incoming_args_rtx
14221 && offset_val >= -cfun->machine->frame.total_size
14222 && offset_val < cfun->machine->frame.args_size)
14225 /* Check for uncached addresses. */
14226 if (CONST_INT_P (x))
14227 return r10k_uncached_address_p (INTVAL (x));
14229 /* Check for accesses to a static object. */
14230 split_const (x, &base, &offset);
14231 return offset_within_block_p (base, INTVAL (offset));
14234 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
14235 an in-range access to an automatic variable, or to an object with
14236 a link-time-constant address. */
14239 r10k_safe_mem_expr_p (tree expr, HOST_WIDE_INT offset)
14241 if (offset < 0 || offset >= int_size_in_bytes (TREE_TYPE (expr)))
14244 while (TREE_CODE (expr) == COMPONENT_REF)
14246 expr = TREE_OPERAND (expr, 0);
14247 if (expr == NULL_TREE)
14251 return DECL_P (expr);
14254 /* A for_each_rtx callback for which DATA points to the instruction
14255 containing *X. Stop the search if we find a MEM that is not safe
14256 from R10K speculation. */
14259 r10k_needs_protection_p_1 (rtx *loc, void *data)
14268 && MEM_OFFSET_KNOWN_P (mem)
14269 && r10k_safe_mem_expr_p (MEM_EXPR (mem), MEM_OFFSET (mem)))
14272 if (r10k_safe_address_p (XEXP (mem, 0), (rtx) data))
14278 /* A note_stores callback for which DATA points to an instruction pointer.
14279 If *DATA is nonnull, make it null if it X contains a MEM that is not
14280 safe from R10K speculation. */
14283 r10k_needs_protection_p_store (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
14288 insn_ptr = (rtx *) data;
14289 if (*insn_ptr && for_each_rtx (&x, r10k_needs_protection_p_1, *insn_ptr))
14290 *insn_ptr = NULL_RTX;
14293 /* A for_each_rtx callback that iterates over the pattern of a CALL_INSN.
14294 Return nonzero if the call is not to a declared function. */
14297 r10k_needs_protection_p_call (rtx *loc, void *data ATTRIBUTE_UNUSED)
14306 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DECL (x))
14312 /* Return true if instruction INSN needs to be protected by an R10K
14316 r10k_needs_protection_p (rtx insn)
14319 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_call, NULL);
14321 if (mips_r10k_cache_barrier == R10K_CACHE_BARRIER_STORE)
14323 note_stores (PATTERN (insn), r10k_needs_protection_p_store, &insn);
14324 return insn == NULL_RTX;
14327 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_1, insn);
14330 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
14331 edge is unconditional. */
14334 r10k_protected_bb_p (basic_block bb, sbitmap protected_bbs)
14339 FOR_EACH_EDGE (e, ei, bb->preds)
14340 if (!single_succ_p (e->src)
14341 || !TEST_BIT (protected_bbs, e->src->index)
14342 || (e->flags & EDGE_COMPLEX) != 0)
14347 /* Implement -mr10k-cache-barrier= for the current function. */
14350 r10k_insert_cache_barriers (void)
14352 int *rev_post_order;
14355 sbitmap protected_bbs;
14356 rtx insn, end, unprotected_region;
14360 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
14364 /* Calculate dominators. */
14365 calculate_dominance_info (CDI_DOMINATORS);
14367 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
14368 X is protected by a cache barrier. */
14369 protected_bbs = sbitmap_alloc (last_basic_block);
14370 sbitmap_zero (protected_bbs);
14372 /* Iterate over the basic blocks in reverse post-order. */
14373 rev_post_order = XNEWVEC (int, last_basic_block);
14374 n = pre_and_rev_post_order_compute (NULL, rev_post_order, false);
14375 for (i = 0; i < n; i++)
14377 bb = BASIC_BLOCK (rev_post_order[i]);
14379 /* If this block is only reached by unconditional edges, and if the
14380 source of every edge is protected, the beginning of the block is
14382 if (r10k_protected_bb_p (bb, protected_bbs))
14383 unprotected_region = NULL_RTX;
14385 unprotected_region = pc_rtx;
14386 end = NEXT_INSN (BB_END (bb));
14388 /* UNPROTECTED_REGION is:
14390 - null if we are processing a protected region,
14391 - pc_rtx if we are processing an unprotected region but have
14392 not yet found the first instruction in it
14393 - the first instruction in an unprotected region otherwise. */
14394 for (insn = BB_HEAD (bb); insn != end; insn = NEXT_INSN (insn))
14396 if (unprotected_region && USEFUL_INSN_P (insn))
14398 if (recog_memoized (insn) == CODE_FOR_mips_cache)
14399 /* This CACHE instruction protects the following code. */
14400 unprotected_region = NULL_RTX;
14403 /* See if INSN is the first instruction in this
14404 unprotected region. */
14405 if (unprotected_region == pc_rtx)
14406 unprotected_region = insn;
14408 /* See if INSN needs to be protected. If so,
14409 we must insert a cache barrier somewhere between
14410 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
14411 clear which position is better performance-wise,
14412 but as a tie-breaker, we assume that it is better
14413 to allow delay slots to be back-filled where
14414 possible, and that it is better not to insert
14415 barriers in the middle of already-scheduled code.
14416 We therefore insert the barrier at the beginning
14418 if (r10k_needs_protection_p (insn))
14420 emit_insn_before (gen_r10k_cache_barrier (),
14421 unprotected_region);
14422 unprotected_region = NULL_RTX;
14428 /* The called function is not required to protect the exit path.
14429 The code that follows a call is therefore unprotected. */
14430 unprotected_region = pc_rtx;
14433 /* Record whether the end of this block is protected. */
14434 if (unprotected_region == NULL_RTX)
14435 SET_BIT (protected_bbs, bb->index);
14437 XDELETEVEC (rev_post_order);
14439 sbitmap_free (protected_bbs);
14441 free_dominance_info (CDI_DOMINATORS);
14444 /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX
14445 otherwise. If INSN has two call rtx, then store the second one in
14449 mips_call_expr_from_insn (rtx insn, rtx *second_call)
14454 if (!CALL_P (insn))
14457 x = PATTERN (insn);
14458 if (GET_CODE (x) == PARALLEL)
14460 /* Calls returning complex values have two CALL rtx. Look for the second
14461 one here, and return it via the SECOND_CALL arg. */
14462 x2 = XVECEXP (x, 0, 1);
14463 if (GET_CODE (x2) == SET)
14465 if (GET_CODE (x2) == CALL)
14468 x = XVECEXP (x, 0, 0);
14470 if (GET_CODE (x) == SET)
14472 gcc_assert (GET_CODE (x) == CALL);
14477 /* REG is set in DEF. See if the definition is one of the ways we load a
14478 register with a symbol address for a mips_use_pic_fn_addr_reg_p call.
14479 If it is, return the symbol reference of the function, otherwise return
14482 If RECURSE_P is true, use mips_find_pic_call_symbol to interpret
14483 the values of source registers, otherwise treat such registers as
14484 having an unknown value. */
14487 mips_pic_call_symbol_from_set (df_ref def, rtx reg, bool recurse_p)
14491 if (DF_REF_IS_ARTIFICIAL (def))
14494 def_insn = DF_REF_INSN (def);
14495 set = single_set (def_insn);
14496 if (set && rtx_equal_p (SET_DEST (set), reg))
14498 rtx note, src, symbol;
14500 /* First, look at REG_EQUAL/EQUIV notes. */
14501 note = find_reg_equal_equiv_note (def_insn);
14502 if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF)
14503 return XEXP (note, 0);
14505 /* For %call16 references we don't have REG_EQUAL. */
14506 src = SET_SRC (set);
14507 symbol = mips_strip_unspec_call (src);
14510 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
14514 /* Follow at most one simple register copy. Such copies are
14515 interesting in cases like:
14519 locally_binding_fn (...);
14524 locally_binding_fn (...);
14526 locally_binding_fn (...);
14528 where the load of locally_binding_fn can legitimately be
14529 hoisted or shared. However, we do not expect to see complex
14530 chains of copies, so a full worklist solution to the problem
14531 would probably be overkill. */
14532 if (recurse_p && REG_P (src))
14533 return mips_find_pic_call_symbol (def_insn, src, false);
14539 /* Find the definition of the use of REG in INSN. See if the definition
14540 is one of the ways we load a register with a symbol address for a
14541 mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference
14542 of the function, otherwise return NULL_RTX. RECURSE_P is as for
14543 mips_pic_call_symbol_from_set. */
14546 mips_find_pic_call_symbol (rtx insn, rtx reg, bool recurse_p)
14549 struct df_link *defs;
14552 use = df_find_use (insn, regno_reg_rtx[REGNO (reg)]);
14555 defs = DF_REF_CHAIN (use);
14558 symbol = mips_pic_call_symbol_from_set (defs->ref, reg, recurse_p);
14562 /* If we have more than one definition, they need to be identical. */
14563 for (defs = defs->next; defs; defs = defs->next)
14567 other = mips_pic_call_symbol_from_set (defs->ref, reg, recurse_p);
14568 if (!rtx_equal_p (symbol, other))
14575 /* Replace the args_size operand of the call expression CALL with the
14576 call-attribute UNSPEC and fill in SYMBOL as the function symbol. */
14579 mips_annotate_pic_call_expr (rtx call, rtx symbol)
14583 args_size = XEXP (call, 1);
14584 XEXP (call, 1) = gen_rtx_UNSPEC (GET_MODE (args_size),
14585 gen_rtvec (2, args_size, symbol),
14589 /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See
14590 if instead of the arg_size argument it contains the call attributes. If
14591 yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function
14592 symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is
14596 mips_get_pic_call_symbol (rtx *operands, int args_size_opno)
14598 rtx args_size, symbol;
14600 if (!TARGET_RELAX_PIC_CALLS || args_size_opno == -1)
14603 args_size = operands[args_size_opno];
14604 if (GET_CODE (args_size) != UNSPEC)
14606 gcc_assert (XINT (args_size, 1) == UNSPEC_CALL_ATTR);
14608 symbol = XVECEXP (args_size, 0, 1);
14609 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
14611 operands[args_size_opno] = symbol;
14615 /* Use DF to annotate PIC indirect calls with the function symbol they
14619 mips_annotate_pic_calls (void)
14625 FOR_BB_INSNS (bb, insn)
14627 rtx call, reg, symbol, second_call;
14630 call = mips_call_expr_from_insn (insn, &second_call);
14633 gcc_assert (MEM_P (XEXP (call, 0)));
14634 reg = XEXP (XEXP (call, 0), 0);
14638 symbol = mips_find_pic_call_symbol (insn, reg, true);
14641 mips_annotate_pic_call_expr (call, symbol);
14643 mips_annotate_pic_call_expr (second_call, symbol);
14648 /* A temporary variable used by for_each_rtx callbacks, etc. */
14649 static rtx mips_sim_insn;
14651 /* A structure representing the state of the processor pipeline.
14652 Used by the mips_sim_* family of functions. */
14654 /* The maximum number of instructions that can be issued in a cycle.
14655 (Caches mips_issue_rate.) */
14656 unsigned int issue_rate;
14658 /* The current simulation time. */
14661 /* How many more instructions can be issued in the current cycle. */
14662 unsigned int insns_left;
14664 /* LAST_SET[X].INSN is the last instruction to set register X.
14665 LAST_SET[X].TIME is the time at which that instruction was issued.
14666 INSN is null if no instruction has yet set register X. */
14670 } last_set[FIRST_PSEUDO_REGISTER];
14672 /* The pipeline's current DFA state. */
14676 /* Reset STATE to the initial simulation state. */
14679 mips_sim_reset (struct mips_sim *state)
14682 state->insns_left = state->issue_rate;
14683 memset (&state->last_set, 0, sizeof (state->last_set));
14684 state_reset (state->dfa_state);
14687 /* Initialize STATE before its first use. DFA_STATE points to an
14688 allocated but uninitialized DFA state. */
14691 mips_sim_init (struct mips_sim *state, state_t dfa_state)
14693 state->issue_rate = mips_issue_rate ();
14694 state->dfa_state = dfa_state;
14695 mips_sim_reset (state);
14698 /* Advance STATE by one clock cycle. */
14701 mips_sim_next_cycle (struct mips_sim *state)
14704 state->insns_left = state->issue_rate;
14705 state_transition (state->dfa_state, 0);
14708 /* Advance simulation state STATE until instruction INSN can read
14712 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
14714 unsigned int regno, end_regno;
14716 end_regno = END_REGNO (reg);
14717 for (regno = REGNO (reg); regno < end_regno; regno++)
14718 if (state->last_set[regno].insn != 0)
14722 t = (state->last_set[regno].time
14723 + insn_latency (state->last_set[regno].insn, insn));
14724 while (state->time < t)
14725 mips_sim_next_cycle (state);
14729 /* A for_each_rtx callback. If *X is a register, advance simulation state
14730 DATA until mips_sim_insn can read the register's value. */
14733 mips_sim_wait_regs_2 (rtx *x, void *data)
14736 mips_sim_wait_reg ((struct mips_sim *) data, mips_sim_insn, *x);
14740 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
14743 mips_sim_wait_regs_1 (rtx *x, void *data)
14745 for_each_rtx (x, mips_sim_wait_regs_2, data);
14748 /* Advance simulation state STATE until all of INSN's register
14749 dependencies are satisfied. */
14752 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
14754 mips_sim_insn = insn;
14755 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
14758 /* Advance simulation state STATE until the units required by
14759 instruction INSN are available. */
14762 mips_sim_wait_units (struct mips_sim *state, rtx insn)
14766 tmp_state = alloca (state_size ());
14767 while (state->insns_left == 0
14768 || (memcpy (tmp_state, state->dfa_state, state_size ()),
14769 state_transition (tmp_state, insn) >= 0))
14770 mips_sim_next_cycle (state);
14773 /* Advance simulation state STATE until INSN is ready to issue. */
14776 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
14778 mips_sim_wait_regs (state, insn);
14779 mips_sim_wait_units (state, insn);
14782 /* mips_sim_insn has just set X. Update the LAST_SET array
14783 in simulation state DATA. */
14786 mips_sim_record_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
14788 struct mips_sim *state;
14790 state = (struct mips_sim *) data;
14793 unsigned int regno, end_regno;
14795 end_regno = END_REGNO (x);
14796 for (regno = REGNO (x); regno < end_regno; regno++)
14798 state->last_set[regno].insn = mips_sim_insn;
14799 state->last_set[regno].time = state->time;
14804 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
14805 can issue immediately (i.e., that mips_sim_wait_insn has already
14809 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
14811 state_transition (state->dfa_state, insn);
14812 state->insns_left--;
14814 mips_sim_insn = insn;
14815 note_stores (PATTERN (insn), mips_sim_record_set, state);
14818 /* Simulate issuing a NOP in state STATE. */
14821 mips_sim_issue_nop (struct mips_sim *state)
14823 if (state->insns_left == 0)
14824 mips_sim_next_cycle (state);
14825 state->insns_left--;
14828 /* Update simulation state STATE so that it's ready to accept the instruction
14829 after INSN. INSN should be part of the main rtl chain, not a member of a
14833 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
14835 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
14837 mips_sim_issue_nop (state);
14839 switch (GET_CODE (SEQ_BEGIN (insn)))
14843 /* We can't predict the processor state after a call or label. */
14844 mips_sim_reset (state);
14848 /* The delay slots of branch likely instructions are only executed
14849 when the branch is taken. Therefore, if the caller has simulated
14850 the delay slot instruction, STATE does not really reflect the state
14851 of the pipeline for the instruction after the delay slot. Also,
14852 branch likely instructions tend to incur a penalty when not taken,
14853 so there will probably be an extra delay between the branch and
14854 the instruction after the delay slot. */
14855 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
14856 mips_sim_reset (state);
14864 /* The VR4130 pipeline issues aligned pairs of instructions together,
14865 but it stalls the second instruction if it depends on the first.
14866 In order to cut down the amount of logic required, this dependence
14867 check is not based on a full instruction decode. Instead, any non-SPECIAL
14868 instruction is assumed to modify the register specified by bits 20-16
14869 (which is usually the "rt" field).
14871 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
14872 input, so we can end up with a false dependence between the branch
14873 and its delay slot. If this situation occurs in instruction INSN,
14874 try to avoid it by swapping rs and rt. */
14877 vr4130_avoid_branch_rt_conflict (rtx insn)
14881 first = SEQ_BEGIN (insn);
14882 second = SEQ_END (insn);
14884 && NONJUMP_INSN_P (second)
14885 && GET_CODE (PATTERN (first)) == SET
14886 && GET_CODE (SET_DEST (PATTERN (first))) == PC
14887 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
14889 /* Check for the right kind of condition. */
14890 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
14891 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
14892 && REG_P (XEXP (cond, 0))
14893 && REG_P (XEXP (cond, 1))
14894 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
14895 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
14897 /* SECOND mentions the rt register but not the rs register. */
14898 rtx tmp = XEXP (cond, 0);
14899 XEXP (cond, 0) = XEXP (cond, 1);
14900 XEXP (cond, 1) = tmp;
14905 /* Implement -mvr4130-align. Go through each basic block and simulate the
14906 processor pipeline. If we find that a pair of instructions could execute
14907 in parallel, and the first of those instructions is not 8-byte aligned,
14908 insert a nop to make it aligned. */
14911 vr4130_align_insns (void)
14913 struct mips_sim state;
14914 rtx insn, subinsn, last, last2, next;
14919 /* LAST is the last instruction before INSN to have a nonzero length.
14920 LAST2 is the last such instruction before LAST. */
14924 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
14927 mips_sim_init (&state, alloca (state_size ()));
14928 for (insn = get_insns (); insn != 0; insn = next)
14930 unsigned int length;
14932 next = NEXT_INSN (insn);
14934 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
14935 This isn't really related to the alignment pass, but we do it on
14936 the fly to avoid a separate instruction walk. */
14937 vr4130_avoid_branch_rt_conflict (insn);
14939 if (USEFUL_INSN_P (insn))
14940 FOR_EACH_SUBINSN (subinsn, insn)
14942 mips_sim_wait_insn (&state, subinsn);
14944 /* If we want this instruction to issue in parallel with the
14945 previous one, make sure that the previous instruction is
14946 aligned. There are several reasons why this isn't worthwhile
14947 when the second instruction is a call:
14949 - Calls are less likely to be performance critical,
14950 - There's a good chance that the delay slot can execute
14951 in parallel with the call.
14952 - The return address would then be unaligned.
14954 In general, if we're going to insert a nop between instructions
14955 X and Y, it's better to insert it immediately after X. That
14956 way, if the nop makes Y aligned, it will also align any labels
14957 between X and Y. */
14958 if (state.insns_left != state.issue_rate
14959 && !CALL_P (subinsn))
14961 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
14963 /* SUBINSN is the first instruction in INSN and INSN is
14964 aligned. We want to align the previous instruction
14965 instead, so insert a nop between LAST2 and LAST.
14967 Note that LAST could be either a single instruction
14968 or a branch with a delay slot. In the latter case,
14969 LAST, like INSN, is already aligned, but the delay
14970 slot must have some extra delay that stops it from
14971 issuing at the same time as the branch. We therefore
14972 insert a nop before the branch in order to align its
14974 emit_insn_after (gen_nop (), last2);
14977 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
14979 /* SUBINSN is the delay slot of INSN, but INSN is
14980 currently unaligned. Insert a nop between
14981 LAST and INSN to align it. */
14982 emit_insn_after (gen_nop (), last);
14986 mips_sim_issue_insn (&state, subinsn);
14988 mips_sim_finish_insn (&state, insn);
14990 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
14991 length = get_attr_length (insn);
14994 /* If the instruction is an asm statement or multi-instruction
14995 mips.md patern, the length is only an estimate. Insert an
14996 8 byte alignment after it so that the following instructions
14997 can be handled correctly. */
14998 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
14999 && (recog_memoized (insn) < 0 || length >= 8))
15001 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
15002 next = NEXT_INSN (next);
15003 mips_sim_next_cycle (&state);
15006 else if (length & 4)
15007 aligned_p = !aligned_p;
15012 /* See whether INSN is an aligned label. */
15013 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
15019 /* This structure records that the current function has a LO_SUM
15020 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
15021 the largest offset applied to BASE by all such LO_SUMs. */
15022 struct mips_lo_sum_offset {
15024 HOST_WIDE_INT offset;
15027 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
15030 mips_hash_base (rtx base)
15032 int do_not_record_p;
15034 return hash_rtx (base, GET_MODE (base), &do_not_record_p, NULL, false);
15037 /* Hash-table callbacks for mips_lo_sum_offsets. */
15040 mips_lo_sum_offset_hash (const void *entry)
15042 return mips_hash_base (((const struct mips_lo_sum_offset *) entry)->base);
15046 mips_lo_sum_offset_eq (const void *entry, const void *value)
15048 return rtx_equal_p (((const struct mips_lo_sum_offset *) entry)->base,
15049 (const_rtx) value);
15052 /* Look up symbolic constant X in HTAB, which is a hash table of
15053 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
15054 paired with a recorded LO_SUM, otherwise record X in the table. */
15057 mips_lo_sum_offset_lookup (htab_t htab, rtx x, enum insert_option option)
15061 struct mips_lo_sum_offset *entry;
15063 /* Split X into a base and offset. */
15064 split_const (x, &base, &offset);
15065 if (UNSPEC_ADDRESS_P (base))
15066 base = UNSPEC_ADDRESS (base);
15068 /* Look up the base in the hash table. */
15069 slot = htab_find_slot_with_hash (htab, base, mips_hash_base (base), option);
15073 entry = (struct mips_lo_sum_offset *) *slot;
15074 if (option == INSERT)
15078 entry = XNEW (struct mips_lo_sum_offset);
15079 entry->base = base;
15080 entry->offset = INTVAL (offset);
15085 if (INTVAL (offset) > entry->offset)
15086 entry->offset = INTVAL (offset);
15089 return INTVAL (offset) <= entry->offset;
15092 /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table.
15093 Record every LO_SUM in *LOC. */
15096 mips_record_lo_sum (rtx *loc, void *data)
15098 if (GET_CODE (*loc) == LO_SUM)
15099 mips_lo_sum_offset_lookup ((htab_t) data, XEXP (*loc, 1), INSERT);
15103 /* Return true if INSN is a SET of an orphaned high-part relocation.
15104 HTAB is a hash table of mips_lo_sum_offsets that describes all the
15105 LO_SUMs in the current function. */
15108 mips_orphaned_high_part_p (htab_t htab, rtx insn)
15110 enum mips_symbol_type type;
15113 set = single_set (insn);
15116 /* Check for %his. */
15118 if (GET_CODE (x) == HIGH
15119 && absolute_symbolic_operand (XEXP (x, 0), VOIDmode))
15120 return !mips_lo_sum_offset_lookup (htab, XEXP (x, 0), NO_INSERT);
15122 /* Check for local %gots (and %got_pages, which is redundant but OK). */
15123 if (GET_CODE (x) == UNSPEC
15124 && XINT (x, 1) == UNSPEC_LOAD_GOT
15125 && mips_symbolic_constant_p (XVECEXP (x, 0, 1),
15126 SYMBOL_CONTEXT_LEA, &type)
15127 && type == SYMBOL_GOTOFF_PAGE)
15128 return !mips_lo_sum_offset_lookup (htab, XVECEXP (x, 0, 1), NO_INSERT);
15133 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
15134 INSN and a previous instruction, avoid it by inserting nops after
15137 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
15138 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
15139 before using the value of that register. *HILO_DELAY counts the
15140 number of instructions since the last hilo hazard (that is,
15141 the number of instructions since the last MFLO or MFHI).
15143 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
15144 for the next instruction.
15146 LO_REG is an rtx for the LO register, used in dependence checking. */
15149 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
15150 rtx *delayed_reg, rtx lo_reg)
15155 pattern = PATTERN (insn);
15157 /* Do not put the whole function in .set noreorder if it contains
15158 an asm statement. We don't know whether there will be hazards
15159 between the asm statement and the gcc-generated code. */
15160 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
15161 cfun->machine->all_noreorder_p = false;
15163 /* Ignore zero-length instructions (barriers and the like). */
15164 ninsns = get_attr_length (insn) / 4;
15168 /* Work out how many nops are needed. Note that we only care about
15169 registers that are explicitly mentioned in the instruction's pattern.
15170 It doesn't matter that calls use the argument registers or that they
15171 clobber hi and lo. */
15172 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
15173 nops = 2 - *hilo_delay;
15174 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
15179 /* Insert the nops between this instruction and the previous one.
15180 Each new nop takes us further from the last hilo hazard. */
15181 *hilo_delay += nops;
15183 emit_insn_after (gen_hazard_nop (), after);
15185 /* Set up the state for the next instruction. */
15186 *hilo_delay += ninsns;
15188 if (INSN_CODE (insn) >= 0)
15189 switch (get_attr_hazard (insn))
15199 set = single_set (insn);
15201 *delayed_reg = SET_DEST (set);
15206 /* Go through the instruction stream and insert nops where necessary.
15207 Also delete any high-part relocations whose partnering low parts
15208 are now all dead. See if the whole function can then be put into
15209 .set noreorder and .set nomacro. */
15212 mips_reorg_process_insns (void)
15214 rtx insn, last_insn, subinsn, next_insn, lo_reg, delayed_reg;
15218 /* Force all instructions to be split into their final form. */
15219 split_all_insns_noflow ();
15221 /* Recalculate instruction lengths without taking nops into account. */
15222 cfun->machine->ignore_hazard_length_p = true;
15223 shorten_branches (get_insns ());
15225 cfun->machine->all_noreorder_p = true;
15227 /* We don't track MIPS16 PC-relative offsets closely enough to make
15228 a good job of "set .noreorder" code in MIPS16 mode. */
15230 cfun->machine->all_noreorder_p = false;
15232 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
15233 if (!TARGET_EXPLICIT_RELOCS)
15234 cfun->machine->all_noreorder_p = false;
15236 /* Profiled functions can't be all noreorder because the profiler
15237 support uses assembler macros. */
15239 cfun->machine->all_noreorder_p = false;
15241 /* Code compiled with -mfix-vr4120 or -mfix-24k can't be all noreorder
15242 because we rely on the assembler to work around some errata. */
15243 if (TARGET_FIX_VR4120 || TARGET_FIX_24K)
15244 cfun->machine->all_noreorder_p = false;
15246 /* The same is true for -mfix-vr4130 if we might generate MFLO or
15247 MFHI instructions. Note that we avoid using MFLO and MFHI if
15248 the VR4130 MACC and DMACC instructions are available instead;
15249 see the *mfhilo_{si,di}_macc patterns. */
15250 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
15251 cfun->machine->all_noreorder_p = false;
15253 htab = htab_create (37, mips_lo_sum_offset_hash,
15254 mips_lo_sum_offset_eq, free);
15256 /* Make a first pass over the instructions, recording all the LO_SUMs. */
15257 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
15258 FOR_EACH_SUBINSN (subinsn, insn)
15259 if (USEFUL_INSN_P (subinsn))
15260 for_each_rtx (&PATTERN (subinsn), mips_record_lo_sum, htab);
15265 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
15267 /* Make a second pass over the instructions. Delete orphaned
15268 high-part relocations or turn them into NOPs. Avoid hazards
15269 by inserting NOPs. */
15270 for (insn = get_insns (); insn != 0; insn = next_insn)
15272 next_insn = NEXT_INSN (insn);
15273 if (USEFUL_INSN_P (insn))
15275 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
15277 /* If we find an orphaned high-part relocation in a delay
15278 slot, it's easier to turn that instruction into a NOP than
15279 to delete it. The delay slot will be a NOP either way. */
15280 FOR_EACH_SUBINSN (subinsn, insn)
15281 if (INSN_P (subinsn))
15283 if (mips_orphaned_high_part_p (htab, subinsn))
15285 PATTERN (subinsn) = gen_nop ();
15286 INSN_CODE (subinsn) = CODE_FOR_nop;
15288 mips_avoid_hazard (last_insn, subinsn, &hilo_delay,
15289 &delayed_reg, lo_reg);
15295 /* INSN is a single instruction. Delete it if it's an
15296 orphaned high-part relocation. */
15297 if (mips_orphaned_high_part_p (htab, insn))
15298 delete_insn (insn);
15299 /* Also delete cache barriers if the last instruction
15300 was an annulled branch. INSN will not be speculatively
15302 else if (recog_memoized (insn) == CODE_FOR_r10k_cache_barrier
15304 && JUMP_P (SEQ_BEGIN (last_insn))
15305 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn)))
15306 delete_insn (insn);
15309 mips_avoid_hazard (last_insn, insn, &hilo_delay,
15310 &delayed_reg, lo_reg);
15317 htab_delete (htab);
15320 /* If we are using a GOT, but have not decided to use a global pointer yet,
15321 see whether we need one to implement long branches. Convert the ghost
15322 global-pointer instructions into real ones if so. */
15325 mips_expand_ghost_gp_insns (void)
15330 /* Quick exit if we already know that we will or won't need a
15332 if (!TARGET_USE_GOT
15333 || cfun->machine->global_pointer == INVALID_REGNUM
15334 || mips_must_initialize_gp_p ())
15337 shorten_branches (get_insns ());
15339 /* Look for a branch that is longer than normal. The normal length for
15340 non-MIPS16 branches is 8, because the length includes the delay slot.
15341 It is 4 for MIPS16, because MIPS16 branches are extended instructions,
15342 but they have no delay slot. */
15343 normal_length = (TARGET_MIPS16 ? 4 : 8);
15344 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
15346 && USEFUL_INSN_P (insn)
15347 && get_attr_length (insn) > normal_length)
15350 if (insn == NULL_RTX)
15353 /* We've now established that we need $gp. */
15354 cfun->machine->must_initialize_gp_p = true;
15355 split_all_insns_noflow ();
15360 /* Subroutine of mips_reorg to manage passes that require DF. */
15363 mips_df_reorg (void)
15365 /* Create def-use chains. */
15366 df_set_flags (DF_EQ_NOTES);
15367 df_chain_add_problem (DF_UD_CHAIN);
15370 if (TARGET_RELAX_PIC_CALLS)
15371 mips_annotate_pic_calls ();
15373 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE)
15374 r10k_insert_cache_barriers ();
15376 df_finish_pass (false);
15379 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
15384 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during
15385 insn splitting in mips16_lay_out_constants, DF insn info is only kept up
15386 to date if the CFG is available. */
15387 if (mips_cfg_in_reorg ())
15388 compute_bb_for_insn ();
15389 mips16_lay_out_constants ();
15390 if (mips_cfg_in_reorg ())
15393 free_bb_for_insn ();
15396 if (optimize > 0 && flag_delayed_branch)
15397 dbr_schedule (get_insns ());
15398 mips_reorg_process_insns ();
15400 && TARGET_EXPLICIT_RELOCS
15402 && TARGET_VR4130_ALIGN)
15403 vr4130_align_insns ();
15404 if (mips_expand_ghost_gp_insns ())
15405 /* The expansion could invalidate some of the VR4130 alignment
15406 optimizations, but this should be an extremely rare case anyhow. */
15407 mips_reorg_process_insns ();
15410 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
15411 in order to avoid duplicating too much logic from elsewhere. */
15414 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
15415 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
15418 rtx this_rtx, temp1, temp2, insn, fnaddr;
15419 bool use_sibcall_p;
15421 /* Pretend to be a post-reload pass while generating rtl. */
15422 reload_completed = 1;
15424 /* Mark the end of the (empty) prologue. */
15425 emit_note (NOTE_INSN_PROLOGUE_END);
15427 /* Determine if we can use a sibcall to call FUNCTION directly. */
15428 fnaddr = XEXP (DECL_RTL (function), 0);
15429 use_sibcall_p = (mips_function_ok_for_sibcall (function, NULL)
15430 && const_call_insn_operand (fnaddr, Pmode));
15432 /* Determine if we need to load FNADDR from the GOT. */
15434 && (mips_got_symbol_type_p
15435 (mips_classify_symbol (fnaddr, SYMBOL_CONTEXT_LEA))))
15437 /* Pick a global pointer. Use a call-clobbered register if
15438 TARGET_CALL_SAVED_GP. */
15439 cfun->machine->global_pointer
15440 = TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM;
15441 cfun->machine->must_initialize_gp_p = true;
15442 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
15444 /* Set up the global pointer for n32 or n64 abicalls. */
15445 mips_emit_loadgp ();
15448 /* We need two temporary registers in some cases. */
15449 temp1 = gen_rtx_REG (Pmode, 2);
15450 temp2 = gen_rtx_REG (Pmode, 3);
15452 /* Find out which register contains the "this" pointer. */
15453 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
15454 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
15456 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST);
15458 /* Add DELTA to THIS_RTX. */
15461 rtx offset = GEN_INT (delta);
15462 if (!SMALL_OPERAND (delta))
15464 mips_emit_move (temp1, offset);
15467 emit_insn (gen_add3_insn (this_rtx, this_rtx, offset));
15470 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
15471 if (vcall_offset != 0)
15475 /* Set TEMP1 to *THIS_RTX. */
15476 mips_emit_move (temp1, gen_rtx_MEM (Pmode, this_rtx));
15478 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
15479 addr = mips_add_offset (temp2, temp1, vcall_offset);
15481 /* Load the offset and add it to THIS_RTX. */
15482 mips_emit_move (temp1, gen_rtx_MEM (Pmode, addr));
15483 emit_insn (gen_add3_insn (this_rtx, this_rtx, temp1));
15486 /* Jump to the target function. Use a sibcall if direct jumps are
15487 allowed, otherwise load the address into a register first. */
15490 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
15491 SIBLING_CALL_P (insn) = 1;
15495 /* This is messy. GAS treats "la $25,foo" as part of a call
15496 sequence and may allow a global "foo" to be lazily bound.
15497 The general move patterns therefore reject this combination.
15499 In this context, lazy binding would actually be OK
15500 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
15501 TARGET_CALL_SAVED_GP; see mips_load_call_address.
15502 We must therefore load the address via a temporary
15503 register if mips_dangerous_for_la25_p.
15505 If we jump to the temporary register rather than $25,
15506 the assembler can use the move insn to fill the jump's
15509 We can use the same technique for MIPS16 code, where $25
15510 is not a valid JR register. */
15511 if (TARGET_USE_PIC_FN_ADDR_REG
15513 && !mips_dangerous_for_la25_p (fnaddr))
15514 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
15515 mips_load_call_address (MIPS_CALL_SIBCALL, temp1, fnaddr);
15517 if (TARGET_USE_PIC_FN_ADDR_REG
15518 && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
15519 mips_emit_move (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
15520 emit_jump_insn (gen_indirect_jump (temp1));
15523 /* Run just enough of rest_of_compilation. This sequence was
15524 "borrowed" from alpha.c. */
15525 insn = get_insns ();
15526 insn_locators_alloc ();
15527 split_all_insns_noflow ();
15528 mips16_lay_out_constants ();
15529 shorten_branches (insn);
15530 final_start_function (insn, file, 1);
15531 final (insn, file, 1);
15532 final_end_function ();
15534 /* Clean up the vars set above. Note that final_end_function resets
15535 the global pointer for us. */
15536 reload_completed = 0;
15539 /* The last argument passed to mips_set_mips16_mode, or negative if the
15540 function hasn't been called yet. */
15541 static int was_mips16_p = -1;
15543 /* Set up the target-dependent global state so that it matches the
15544 current function's ISA mode. */
15547 mips_set_mips16_mode (int mips16_p)
15549 if (mips16_p == was_mips16_p)
15552 /* Restore base settings of various flags. */
15553 target_flags = mips_base_target_flags;
15554 flag_schedule_insns = mips_base_schedule_insns;
15555 flag_reorder_blocks_and_partition = mips_base_reorder_blocks_and_partition;
15556 flag_move_loop_invariants = mips_base_move_loop_invariants;
15557 align_loops = mips_base_align_loops;
15558 align_jumps = mips_base_align_jumps;
15559 align_functions = mips_base_align_functions;
15563 /* Switch to MIPS16 mode. */
15564 target_flags |= MASK_MIPS16;
15566 /* Don't run the scheduler before reload, since it tends to
15567 increase register pressure. */
15568 flag_schedule_insns = 0;
15570 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
15571 the whole function to be in a single section. */
15572 flag_reorder_blocks_and_partition = 0;
15574 /* Don't move loop invariants, because it tends to increase
15575 register pressure. It also introduces an extra move in cases
15576 where the constant is the first operand in a two-operand binary
15577 instruction, or when it forms a register argument to a functon
15579 flag_move_loop_invariants = 0;
15581 target_flags |= MASK_EXPLICIT_RELOCS;
15583 /* Experiments suggest we get the best overall section-anchor
15584 results from using the range of an unextended LW or SW. Code
15585 that makes heavy use of byte or short accesses can do better
15586 with ranges of 0...31 and 0...63 respectively, but most code is
15587 sensitive to the range of LW and SW instead. */
15588 targetm.min_anchor_offset = 0;
15589 targetm.max_anchor_offset = 127;
15591 targetm.const_anchor = 0;
15593 /* MIPS16 has no BAL instruction. */
15594 target_flags &= ~MASK_RELAX_PIC_CALLS;
15596 /* The R4000 errata don't apply to any known MIPS16 cores.
15597 It's simpler to make the R4000 fixes and MIPS16 mode
15598 mutually exclusive. */
15599 target_flags &= ~MASK_FIX_R4000;
15601 if (flag_pic && !TARGET_OLDABI)
15602 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
15605 sorry ("MIPS16 -mxgot code");
15607 if (TARGET_HARD_FLOAT_ABI && !TARGET_OLDABI)
15608 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
15612 /* Switch to normal (non-MIPS16) mode. */
15613 target_flags &= ~MASK_MIPS16;
15615 /* Provide default values for align_* for 64-bit targets. */
15618 if (align_loops == 0)
15620 if (align_jumps == 0)
15622 if (align_functions == 0)
15623 align_functions = 8;
15626 targetm.min_anchor_offset = -32768;
15627 targetm.max_anchor_offset = 32767;
15629 targetm.const_anchor = 0x8000;
15632 /* (Re)initialize MIPS target internals for new ISA. */
15633 mips_init_relocs ();
15637 if (!mips16_globals)
15638 mips16_globals = save_target_globals ();
15640 restore_target_globals (mips16_globals);
15643 restore_target_globals (&default_target_globals);
15645 was_mips16_p = mips16_p;
15648 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
15649 function should use the MIPS16 ISA and switch modes accordingly. */
15652 mips_set_current_function (tree fndecl)
15654 mips_set_mips16_mode (mips_use_mips16_mode_p (fndecl));
15657 /* Allocate a chunk of memory for per-function machine-dependent data. */
15659 static struct machine_function *
15660 mips_init_machine_status (void)
15662 return ggc_alloc_cleared_machine_function ();
15665 /* Return the processor associated with the given ISA level, or null
15666 if the ISA isn't valid. */
15668 static const struct mips_cpu_info *
15669 mips_cpu_info_from_isa (int isa)
15673 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
15674 if (mips_cpu_info_table[i].isa == isa)
15675 return mips_cpu_info_table + i;
15680 /* Return a mips_cpu_info entry determined by an option valued
15683 static const struct mips_cpu_info *
15684 mips_cpu_info_from_opt (int opt)
15688 case MIPS_ARCH_OPTION_FROM_ABI:
15689 /* 'from-abi' selects the most compatible architecture for the
15690 given ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit
15691 ABIs. For the EABIs, we have to decide whether we're using
15692 the 32-bit or 64-bit version. */
15693 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
15694 : ABI_NEEDS_64BIT_REGS ? 3
15695 : (TARGET_64BIT ? 3 : 1));
15697 case MIPS_ARCH_OPTION_NATIVE:
15698 gcc_unreachable ();
15701 return &mips_cpu_info_table[opt];
15705 /* Return a default mips_cpu_info entry, given that no -march= option
15706 was explicitly specified. */
15708 static const struct mips_cpu_info *
15709 mips_default_arch (void)
15711 #if defined (MIPS_CPU_STRING_DEFAULT)
15713 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
15714 if (strcmp (mips_cpu_info_table[i].name, MIPS_CPU_STRING_DEFAULT) == 0)
15715 return mips_cpu_info_table + i;
15716 gcc_unreachable ();
15717 #elif defined (MIPS_ISA_DEFAULT)
15718 return mips_cpu_info_from_isa (MIPS_ISA_DEFAULT);
15720 /* 'from-abi' makes a good default: you get whatever the ABI
15722 return mips_cpu_info_from_opt (MIPS_ARCH_OPTION_FROM_ABI);
15726 /* Set up globals to generate code for the ISA or processor
15727 described by INFO. */
15730 mips_set_architecture (const struct mips_cpu_info *info)
15734 mips_arch_info = info;
15735 mips_arch = info->cpu;
15736 mips_isa = info->isa;
15740 /* Likewise for tuning. */
15743 mips_set_tune (const struct mips_cpu_info *info)
15747 mips_tune_info = info;
15748 mips_tune = info->cpu;
15752 /* Implement TARGET_OPTION_OVERRIDE. */
15755 mips_option_override (void)
15757 int i, start, regno, mode;
15759 if (global_options_set.x_mips_isa_option)
15760 mips_isa_option_info = &mips_cpu_info_table[mips_isa_option];
15762 /* Process flags as though we were generating non-MIPS16 code. */
15763 mips_base_mips16 = TARGET_MIPS16;
15764 target_flags &= ~MASK_MIPS16;
15766 #ifdef SUBTARGET_OVERRIDE_OPTIONS
15767 SUBTARGET_OVERRIDE_OPTIONS;
15770 /* -mno-float overrides -mhard-float and -msoft-float. */
15771 if (TARGET_NO_FLOAT)
15773 target_flags |= MASK_SOFT_FLOAT_ABI;
15774 target_flags_explicit |= MASK_SOFT_FLOAT_ABI;
15777 if (TARGET_FLIP_MIPS16)
15778 TARGET_INTERLINK_MIPS16 = 1;
15780 /* Set the small data limit. */
15781 mips_small_data_threshold = (global_options_set.x_g_switch_value
15783 : MIPS_DEFAULT_GVALUE);
15785 /* The following code determines the architecture and register size.
15786 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
15787 The GAS and GCC code should be kept in sync as much as possible. */
15789 if (global_options_set.x_mips_arch_option)
15790 mips_set_architecture (mips_cpu_info_from_opt (mips_arch_option));
15792 if (mips_isa_option_info != 0)
15794 if (mips_arch_info == 0)
15795 mips_set_architecture (mips_isa_option_info);
15796 else if (mips_arch_info->isa != mips_isa_option_info->isa)
15797 error ("%<-%s%> conflicts with the other architecture options, "
15798 "which specify a %s processor",
15799 mips_isa_option_info->name,
15800 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
15803 if (mips_arch_info == 0)
15804 mips_set_architecture (mips_default_arch ());
15806 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
15807 error ("%<-march=%s%> is not compatible with the selected ABI",
15808 mips_arch_info->name);
15810 /* Optimize for mips_arch, unless -mtune selects a different processor. */
15811 if (global_options_set.x_mips_tune_option)
15812 mips_set_tune (mips_cpu_info_from_opt (mips_tune_option));
15814 if (mips_tune_info == 0)
15815 mips_set_tune (mips_arch_info);
15817 if ((target_flags_explicit & MASK_64BIT) != 0)
15819 /* The user specified the size of the integer registers. Make sure
15820 it agrees with the ABI and ISA. */
15821 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
15822 error ("%<-mgp64%> used with a 32-bit processor");
15823 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
15824 error ("%<-mgp32%> used with a 64-bit ABI");
15825 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
15826 error ("%<-mgp64%> used with a 32-bit ABI");
15830 /* Infer the integer register size from the ABI and processor.
15831 Restrict ourselves to 32-bit registers if that's all the
15832 processor has, or if the ABI cannot handle 64-bit registers. */
15833 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
15834 target_flags &= ~MASK_64BIT;
15836 target_flags |= MASK_64BIT;
15839 if ((target_flags_explicit & MASK_FLOAT64) != 0)
15841 if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
15842 error ("unsupported combination: %s", "-mfp64 -msingle-float");
15843 else if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
15844 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
15845 else if (!TARGET_64BIT && TARGET_FLOAT64)
15847 if (!ISA_HAS_MXHC1)
15848 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
15849 " the target supports the mfhc1 and mthc1 instructions");
15850 else if (mips_abi != ABI_32)
15851 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
15857 /* -msingle-float selects 32-bit float registers. Otherwise the
15858 float registers should be the same size as the integer ones. */
15859 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
15860 target_flags |= MASK_FLOAT64;
15862 target_flags &= ~MASK_FLOAT64;
15865 /* End of code shared with GAS. */
15867 /* If a -mlong* option was given, check that it matches the ABI,
15868 otherwise infer the -mlong* setting from the other options. */
15869 if ((target_flags_explicit & MASK_LONG64) != 0)
15873 if (mips_abi == ABI_N32)
15874 error ("%qs is incompatible with %qs", "-mabi=n32", "-mlong64");
15875 else if (mips_abi == ABI_32)
15876 error ("%qs is incompatible with %qs", "-mabi=32", "-mlong64");
15877 else if (mips_abi == ABI_O64 && TARGET_ABICALLS)
15878 /* We have traditionally allowed non-abicalls code to use
15879 an LP64 form of o64. However, it would take a bit more
15880 effort to support the combination of 32-bit GOT entries
15881 and 64-bit pointers, so we treat the abicalls case as
15883 error ("the combination of %qs and %qs is incompatible with %qs",
15884 "-mabi=o64", "-mabicalls", "-mlong64");
15888 if (mips_abi == ABI_64)
15889 error ("%qs is incompatible with %qs", "-mabi=64", "-mlong32");
15894 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
15895 target_flags |= MASK_LONG64;
15897 target_flags &= ~MASK_LONG64;
15900 if (!TARGET_OLDABI)
15901 flag_pcc_struct_return = 0;
15903 /* Decide which rtx_costs structure to use. */
15905 mips_cost = &mips_rtx_cost_optimize_size;
15907 mips_cost = &mips_rtx_cost_data[mips_tune];
15909 /* If the user hasn't specified a branch cost, use the processor's
15911 if (mips_branch_cost == 0)
15912 mips_branch_cost = mips_cost->branch_cost;
15914 /* If neither -mbranch-likely nor -mno-branch-likely was given
15915 on the command line, set MASK_BRANCHLIKELY based on the target
15916 architecture and tuning flags. Annulled delay slots are a
15917 size win, so we only consider the processor-specific tuning
15918 for !optimize_size. */
15919 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
15921 if (ISA_HAS_BRANCHLIKELY
15923 || (mips_tune_info->tune_flags & PTF_AVOID_BRANCHLIKELY) == 0))
15924 target_flags |= MASK_BRANCHLIKELY;
15926 target_flags &= ~MASK_BRANCHLIKELY;
15928 else if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
15929 warning (0, "the %qs architecture does not support branch-likely"
15930 " instructions", mips_arch_info->name);
15932 /* The effect of -mabicalls isn't defined for the EABI. */
15933 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
15935 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
15936 target_flags &= ~MASK_ABICALLS;
15939 if (TARGET_ABICALLS_PIC2)
15940 /* We need to set flag_pic for executables as well as DSOs
15941 because we may reference symbols that are not defined in
15942 the final executable. (MIPS does not use things like
15943 copy relocs, for example.)
15945 There is a body of code that uses __PIC__ to distinguish
15946 between -mabicalls and -mno-abicalls code. The non-__PIC__
15947 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
15948 long as any indirect jumps use $25. */
15951 /* -mvr4130-align is a "speed over size" optimization: it usually produces
15952 faster code, but at the expense of more nops. Enable it at -O3 and
15954 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
15955 target_flags |= MASK_VR4130_ALIGN;
15957 /* Prefer a call to memcpy over inline code when optimizing for size,
15958 though see MOVE_RATIO in mips.h. */
15959 if (optimize_size && (target_flags_explicit & MASK_MEMCPY) == 0)
15960 target_flags |= MASK_MEMCPY;
15962 /* If we have a nonzero small-data limit, check that the -mgpopt
15963 setting is consistent with the other target flags. */
15964 if (mips_small_data_threshold > 0)
15968 if (!TARGET_EXPLICIT_RELOCS)
15969 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
15971 TARGET_LOCAL_SDATA = false;
15972 TARGET_EXTERN_SDATA = false;
15976 if (TARGET_VXWORKS_RTP)
15977 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
15979 if (TARGET_ABICALLS)
15980 warning (0, "cannot use small-data accesses for %qs",
15985 #ifdef MIPS_TFMODE_FORMAT
15986 REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
15989 /* Make sure that the user didn't turn off paired single support when
15990 MIPS-3D support is requested. */
15992 && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
15993 && !TARGET_PAIRED_SINGLE_FLOAT)
15994 error ("%<-mips3d%> requires %<-mpaired-single%>");
15996 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
15998 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
16000 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
16001 and TARGET_HARD_FLOAT_ABI are both true. */
16002 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT_ABI))
16003 error ("%qs must be used with %qs",
16004 TARGET_MIPS3D ? "-mips3d" : "-mpaired-single",
16005 TARGET_HARD_FLOAT_ABI ? "-mfp64" : "-mhard-float");
16007 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
16009 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_HAS_PAIRED_SINGLE)
16010 warning (0, "the %qs architecture does not support paired-single"
16011 " instructions", mips_arch_info->name);
16013 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
16014 && !TARGET_CACHE_BUILTIN)
16016 error ("%qs requires a target that provides the %qs instruction",
16017 "-mr10k-cache-barrier", "cache");
16018 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE;
16021 /* If TARGET_DSPR2, enable MASK_DSP. */
16023 target_flags |= MASK_DSP;
16025 /* .eh_frame addresses should be the same width as a C pointer.
16026 Most MIPS ABIs support only one pointer size, so the assembler
16027 will usually know exactly how big an .eh_frame address is.
16029 Unfortunately, this is not true of the 64-bit EABI. The ABI was
16030 originally defined to use 64-bit pointers (i.e. it is LP64), and
16031 this is still the default mode. However, we also support an n32-like
16032 ILP32 mode, which is selected by -mlong32. The problem is that the
16033 assembler has traditionally not had an -mlong option, so it has
16034 traditionally not known whether we're using the ILP32 or LP64 form.
16036 As it happens, gas versions up to and including 2.19 use _32-bit_
16037 addresses for EABI64 .cfi_* directives. This is wrong for the
16038 default LP64 mode, so we can't use the directives by default.
16039 Moreover, since gas's current behavior is at odds with gcc's
16040 default behavior, it seems unwise to rely on future versions
16041 of gas behaving the same way. We therefore avoid using .cfi
16042 directives for -mlong32 as well. */
16043 if (mips_abi == ABI_EABI && TARGET_64BIT)
16044 flag_dwarf2_cfi_asm = 0;
16046 /* .cfi_* directives generate a read-only section, so fall back on
16047 manual .eh_frame creation if we need the section to be writable. */
16048 if (TARGET_WRITABLE_EH_FRAME)
16049 flag_dwarf2_cfi_asm = 0;
16051 mips_init_print_operand_punct ();
16053 /* Set up array to map GCC register number to debug register number.
16054 Ignore the special purpose register numbers. */
16056 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
16058 mips_dbx_regno[i] = INVALID_REGNUM;
16059 if (GP_REG_P (i) || FP_REG_P (i) || ALL_COP_REG_P (i))
16060 mips_dwarf_regno[i] = i;
16062 mips_dwarf_regno[i] = INVALID_REGNUM;
16065 start = GP_DBX_FIRST - GP_REG_FIRST;
16066 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
16067 mips_dbx_regno[i] = i + start;
16069 start = FP_DBX_FIRST - FP_REG_FIRST;
16070 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
16071 mips_dbx_regno[i] = i + start;
16073 /* Accumulator debug registers use big-endian ordering. */
16074 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
16075 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
16076 mips_dwarf_regno[HI_REGNUM] = MD_REG_FIRST + 0;
16077 mips_dwarf_regno[LO_REGNUM] = MD_REG_FIRST + 1;
16078 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
16080 mips_dwarf_regno[i + TARGET_LITTLE_ENDIAN] = i;
16081 mips_dwarf_regno[i + TARGET_BIG_ENDIAN] = i + 1;
16084 /* Set up mips_hard_regno_mode_ok. */
16085 for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
16086 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
16087 mips_hard_regno_mode_ok[mode][regno]
16088 = mips_hard_regno_mode_ok_p (regno, (enum machine_mode) mode);
16090 /* Function to allocate machine-dependent function status. */
16091 init_machine_status = &mips_init_machine_status;
16093 /* Default to working around R4000 errata only if the processor
16094 was selected explicitly. */
16095 if ((target_flags_explicit & MASK_FIX_R4000) == 0
16096 && strcmp (mips_arch_info->name, "r4000") == 0)
16097 target_flags |= MASK_FIX_R4000;
16099 /* Default to working around R4400 errata only if the processor
16100 was selected explicitly. */
16101 if ((target_flags_explicit & MASK_FIX_R4400) == 0
16102 && strcmp (mips_arch_info->name, "r4400") == 0)
16103 target_flags |= MASK_FIX_R4400;
16105 /* Default to working around R10000 errata only if the processor
16106 was selected explicitly. */
16107 if ((target_flags_explicit & MASK_FIX_R10000) == 0
16108 && strcmp (mips_arch_info->name, "r10000") == 0)
16109 target_flags |= MASK_FIX_R10000;
16111 /* Make sure that branch-likely instructions available when using
16112 -mfix-r10000. The instructions are not available if either:
16114 1. -mno-branch-likely was passed.
16115 2. The selected ISA does not support branch-likely and
16116 the command line does not include -mbranch-likely. */
16117 if (TARGET_FIX_R10000
16118 && ((target_flags_explicit & MASK_BRANCHLIKELY) == 0
16119 ? !ISA_HAS_BRANCHLIKELY
16120 : !TARGET_BRANCHLIKELY))
16121 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
16123 if (TARGET_SYNCI && !ISA_HAS_SYNCI)
16125 warning (0, "the %qs architecture does not support the synci "
16126 "instruction", mips_arch_info->name);
16127 target_flags &= ~MASK_SYNCI;
16130 /* Only optimize PIC indirect calls if they are actually required. */
16131 if (!TARGET_USE_GOT || !TARGET_EXPLICIT_RELOCS)
16132 target_flags &= ~MASK_RELAX_PIC_CALLS;
16134 /* Save base state of options. */
16135 mips_base_target_flags = target_flags;
16136 mips_base_schedule_insns = flag_schedule_insns;
16137 mips_base_reorder_blocks_and_partition = flag_reorder_blocks_and_partition;
16138 mips_base_move_loop_invariants = flag_move_loop_invariants;
16139 mips_base_align_loops = align_loops;
16140 mips_base_align_jumps = align_jumps;
16141 mips_base_align_functions = align_functions;
16143 /* Now select the ISA mode.
16145 Do all CPP-sensitive stuff in non-MIPS16 mode; we'll switch to
16146 MIPS16 mode afterwards if need be. */
16147 mips_set_mips16_mode (false);
16150 /* Swap the register information for registers I and I + 1, which
16151 currently have the wrong endianness. Note that the registers'
16152 fixedness and call-clobberedness might have been set on the
16156 mips_swap_registers (unsigned int i)
16161 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
16162 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
16164 SWAP_INT (fixed_regs[i], fixed_regs[i + 1]);
16165 SWAP_INT (call_used_regs[i], call_used_regs[i + 1]);
16166 SWAP_INT (call_really_used_regs[i], call_really_used_regs[i + 1]);
16167 SWAP_STRING (reg_names[i], reg_names[i + 1]);
16173 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
16176 mips_conditional_register_usage (void)
16181 /* These DSP control register fields are global. */
16182 global_regs[CCDSP_PO_REGNUM] = 1;
16183 global_regs[CCDSP_SC_REGNUM] = 1;
16186 AND_COMPL_HARD_REG_SET (accessible_reg_set,
16187 reg_class_contents[(int) DSP_ACC_REGS]);
16189 if (!TARGET_HARD_FLOAT)
16191 AND_COMPL_HARD_REG_SET (accessible_reg_set,
16192 reg_class_contents[(int) FP_REGS]);
16193 AND_COMPL_HARD_REG_SET (accessible_reg_set,
16194 reg_class_contents[(int) ST_REGS]);
16196 else if (!ISA_HAS_8CC)
16198 /* We only have a single condition-code register. We implement
16199 this by fixing all the condition-code registers and generating
16200 RTL that refers directly to ST_REG_FIRST. */
16201 AND_COMPL_HARD_REG_SET (accessible_reg_set,
16202 reg_class_contents[(int) ST_REGS]);
16203 SET_HARD_REG_BIT (accessible_reg_set, FPSW_REGNUM);
16204 fixed_regs[FPSW_REGNUM] = call_used_regs[FPSW_REGNUM] = 1;
16208 /* In MIPS16 mode, we permit the $t temporary registers to be used
16209 for reload. We prohibit the unused $s registers, since they
16210 are call-saved, and saving them via a MIPS16 register would
16211 probably waste more time than just reloading the value. */
16212 fixed_regs[18] = call_used_regs[18] = 1;
16213 fixed_regs[19] = call_used_regs[19] = 1;
16214 fixed_regs[20] = call_used_regs[20] = 1;
16215 fixed_regs[21] = call_used_regs[21] = 1;
16216 fixed_regs[22] = call_used_regs[22] = 1;
16217 fixed_regs[23] = call_used_regs[23] = 1;
16218 fixed_regs[26] = call_used_regs[26] = 1;
16219 fixed_regs[27] = call_used_regs[27] = 1;
16220 fixed_regs[30] = call_used_regs[30] = 1;
16222 /* Do not allow HI and LO to be treated as register operands.
16223 There are no MTHI or MTLO instructions (or any real need
16224 for them) and one-way registers cannot easily be reloaded. */
16225 AND_COMPL_HARD_REG_SET (operand_reg_set,
16226 reg_class_contents[(int) MD_REGS]);
16228 /* $f20-$f23 are call-clobbered for n64. */
16229 if (mips_abi == ABI_64)
16232 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
16233 call_really_used_regs[regno] = call_used_regs[regno] = 1;
16235 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
16237 if (mips_abi == ABI_N32)
16240 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
16241 call_really_used_regs[regno] = call_used_regs[regno] = 1;
16243 /* Make sure that double-register accumulator values are correctly
16244 ordered for the current endianness. */
16245 if (TARGET_LITTLE_ENDIAN)
16247 unsigned int regno;
16249 mips_swap_registers (MD_REG_FIRST);
16250 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno += 2)
16251 mips_swap_registers (regno);
16255 /* When generating MIPS16 code, we want to allocate $24 (T_REG) before
16256 other registers for instructions for which it is possible. This
16257 encourages the compiler to use CMP in cases where an XOR would
16258 require some register shuffling. */
16261 mips_order_regs_for_local_alloc (void)
16265 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
16266 reg_alloc_order[i] = i;
16270 /* It really doesn't matter where we put register 0, since it is
16271 a fixed register anyhow. */
16272 reg_alloc_order[0] = 24;
16273 reg_alloc_order[24] = 0;
16277 /* Implement EH_USES. */
16280 mips_eh_uses (unsigned int regno)
16282 if (reload_completed && !TARGET_ABSOLUTE_JUMPS)
16284 /* We need to force certain registers to be live in order to handle
16285 PIC long branches correctly. See mips_must_initialize_gp_p for
16287 if (mips_cfun_has_cprestore_slot_p ())
16289 if (regno == CPRESTORE_SLOT_REGNUM)
16294 if (cfun->machine->global_pointer == regno)
16302 /* Implement EPILOGUE_USES. */
16305 mips_epilogue_uses (unsigned int regno)
16307 /* Say that the epilogue uses the return address register. Note that
16308 in the case of sibcalls, the values "used by the epilogue" are
16309 considered live at the start of the called function. */
16310 if (regno == RETURN_ADDR_REGNUM)
16313 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
16314 See the comment above load_call<mode> for details. */
16315 if (TARGET_USE_GOT && (regno) == GOT_VERSION_REGNUM)
16318 /* An interrupt handler must preserve some registers that are
16319 ordinarily call-clobbered. */
16320 if (cfun->machine->interrupt_handler_p
16321 && mips_interrupt_extra_call_saved_reg_p (regno))
16327 /* A for_each_rtx callback. Stop the search if *X is an AT register. */
16330 mips_at_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
16332 return REG_P (*x) && REGNO (*x) == AT_REGNUM;
16335 /* Return true if INSN needs to be wrapped in ".set noat".
16336 INSN has NOPERANDS operands, stored in OPVEC. */
16339 mips_need_noat_wrapper_p (rtx insn, rtx *opvec, int noperands)
16343 if (recog_memoized (insn) >= 0)
16344 for (i = 0; i < noperands; i++)
16345 if (for_each_rtx (&opvec[i], mips_at_reg_p, NULL))
16350 /* Implement FINAL_PRESCAN_INSN. */
16353 mips_final_prescan_insn (rtx insn, rtx *opvec, int noperands)
16355 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
16356 mips_push_asm_switch (&mips_noat);
16359 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */
16362 mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED, rtx insn,
16363 rtx *opvec, int noperands)
16365 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
16366 mips_pop_asm_switch (&mips_noat);
16369 /* Return the function that is used to expand the <u>mulsidi3 pattern.
16370 EXT_CODE is the code of the extension used. Return NULL if widening
16371 multiplication shouldn't be used. */
16374 mips_mulsidi3_gen_fn (enum rtx_code ext_code)
16378 signed_p = ext_code == SIGN_EXTEND;
16381 /* Don't use widening multiplication with MULT when we have DMUL. Even
16382 with the extension of its input operands DMUL is faster. Note that
16383 the extension is not needed for signed multiplication. In order to
16384 ensure that we always remove the redundant sign-extension in this
16385 case we still expand mulsidi3 for DMUL. */
16387 return signed_p ? gen_mulsidi3_64bit_dmul : NULL;
16390 ? gen_mulsidi3_64bit_mips16
16391 : gen_umulsidi3_64bit_mips16);
16392 if (TARGET_FIX_R4000)
16394 return signed_p ? gen_mulsidi3_64bit : gen_umulsidi3_64bit;
16400 ? gen_mulsidi3_32bit_mips16
16401 : gen_umulsidi3_32bit_mips16);
16402 if (TARGET_FIX_R4000 && !ISA_HAS_DSP)
16403 return signed_p ? gen_mulsidi3_32bit_r4000 : gen_umulsidi3_32bit_r4000;
16404 return signed_p ? gen_mulsidi3_32bit : gen_umulsidi3_32bit;
16408 /* Return the size in bytes of the trampoline code, padded to
16409 TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target
16410 function address immediately follow. */
16413 mips_trampoline_code_size (void)
16415 if (TARGET_USE_PIC_FN_ADDR_REG)
16417 else if (ptr_mode == DImode)
16419 else if (ISA_HAS_LOAD_DELAY)
16425 /* Implement TARGET_TRAMPOLINE_INIT. */
16428 mips_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
16430 rtx addr, end_addr, high, low, opcode, mem;
16433 HOST_WIDE_INT end_addr_offset, static_chain_offset, target_function_offset;
16435 /* Work out the offsets of the pointers from the start of the
16436 trampoline code. */
16437 end_addr_offset = mips_trampoline_code_size ();
16438 static_chain_offset = end_addr_offset;
16439 target_function_offset = static_chain_offset + GET_MODE_SIZE (ptr_mode);
16441 /* Get pointers to the beginning and end of the code block. */
16442 addr = force_reg (Pmode, XEXP (m_tramp, 0));
16443 end_addr = mips_force_binary (Pmode, PLUS, addr, GEN_INT (end_addr_offset));
16445 #define OP(X) gen_int_mode (X, SImode)
16447 /* Build up the code in TRAMPOLINE. */
16449 if (TARGET_USE_PIC_FN_ADDR_REG)
16451 /* $25 contains the address of the trampoline. Emit code of the form:
16453 l[wd] $1, target_function_offset($25)
16454 l[wd] $static_chain, static_chain_offset($25)
16457 trampoline[i++] = OP (MIPS_LOAD_PTR (AT_REGNUM,
16458 target_function_offset,
16459 PIC_FUNCTION_ADDR_REGNUM));
16460 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
16461 static_chain_offset,
16462 PIC_FUNCTION_ADDR_REGNUM));
16463 trampoline[i++] = OP (MIPS_JR (AT_REGNUM));
16464 trampoline[i++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM, AT_REGNUM));
16466 else if (ptr_mode == DImode)
16468 /* It's too cumbersome to create the full 64-bit address, so let's
16474 1: l[wd] $25, target_function_offset - 12($31)
16475 l[wd] $static_chain, static_chain_offset - 12($31)
16479 where 12 is the offset of "1:" from the start of the code block. */
16480 trampoline[i++] = OP (MIPS_MOVE (AT_REGNUM, RETURN_ADDR_REGNUM));
16481 trampoline[i++] = OP (MIPS_BAL (1));
16482 trampoline[i++] = OP (MIPS_NOP);
16483 trampoline[i++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
16484 target_function_offset - 12,
16485 RETURN_ADDR_REGNUM));
16486 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
16487 static_chain_offset - 12,
16488 RETURN_ADDR_REGNUM));
16489 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
16490 trampoline[i++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM, AT_REGNUM));
16494 /* If the target has load delays, emit:
16496 lui $1, %hi(end_addr)
16497 lw $25, %lo(end_addr + ...)($1)
16498 lw $static_chain, %lo(end_addr + ...)($1)
16504 lui $1, %hi(end_addr)
16505 lw $25, %lo(end_addr + ...)($1)
16507 lw $static_chain, %lo(end_addr + ...)($1). */
16509 /* Split END_ADDR into %hi and %lo values. Trampolines are aligned
16510 to 64 bits, so the %lo value will have the bottom 3 bits clear. */
16511 high = expand_simple_binop (SImode, PLUS, end_addr, GEN_INT (0x8000),
16512 NULL, false, OPTAB_WIDEN);
16513 high = expand_simple_binop (SImode, LSHIFTRT, high, GEN_INT (16),
16514 NULL, false, OPTAB_WIDEN);
16515 low = convert_to_mode (SImode, gen_lowpart (HImode, end_addr), true);
16517 /* Emit the LUI. */
16518 opcode = OP (MIPS_LUI (AT_REGNUM, 0));
16519 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, high,
16520 NULL, false, OPTAB_WIDEN);
16522 /* Emit the load of the target function. */
16523 opcode = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
16524 target_function_offset - end_addr_offset,
16526 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
16527 NULL, false, OPTAB_WIDEN);
16529 /* Emit the JR here, if we can. */
16530 if (!ISA_HAS_LOAD_DELAY)
16531 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
16533 /* Emit the load of the static chain register. */
16534 opcode = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
16535 static_chain_offset - end_addr_offset,
16537 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
16538 NULL, false, OPTAB_WIDEN);
16540 /* Emit the JR, if we couldn't above. */
16541 if (ISA_HAS_LOAD_DELAY)
16543 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
16544 trampoline[i++] = OP (MIPS_NOP);
16550 /* Copy the trampoline code. Leave any padding uninitialized. */
16551 for (j = 0; j < i; j++)
16553 mem = adjust_address (m_tramp, SImode, j * GET_MODE_SIZE (SImode));
16554 mips_emit_move (mem, trampoline[j]);
16557 /* Set up the static chain pointer field. */
16558 mem = adjust_address (m_tramp, ptr_mode, static_chain_offset);
16559 mips_emit_move (mem, chain_value);
16561 /* Set up the target function field. */
16562 mem = adjust_address (m_tramp, ptr_mode, target_function_offset);
16563 mips_emit_move (mem, XEXP (DECL_RTL (fndecl), 0));
16565 /* Flush the code part of the trampoline. */
16566 emit_insn (gen_add3_insn (end_addr, addr, GEN_INT (TRAMPOLINE_SIZE)));
16567 emit_insn (gen_clear_cache (addr, end_addr));
16570 /* Implement FUNCTION_PROFILER. */
16572 void mips_function_profiler (FILE *file)
16575 sorry ("mips16 function profiling");
16576 if (TARGET_LONG_CALLS)
16578 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */
16579 if (Pmode == DImode)
16580 fprintf (file, "\tdla\t%s,_mcount\n", reg_names[3]);
16582 fprintf (file, "\tla\t%s,_mcount\n", reg_names[3]);
16584 mips_push_asm_switch (&mips_noat);
16585 fprintf (file, "\tmove\t%s,%s\t\t# save current return address\n",
16586 reg_names[AT_REGNUM], reg_names[RETURN_ADDR_REGNUM]);
16587 /* _mcount treats $2 as the static chain register. */
16588 if (cfun->static_chain_decl != NULL)
16589 fprintf (file, "\tmove\t%s,%s\n", reg_names[2],
16590 reg_names[STATIC_CHAIN_REGNUM]);
16591 if (TARGET_MCOUNT_RA_ADDRESS)
16593 /* If TARGET_MCOUNT_RA_ADDRESS load $12 with the address of the
16594 ra save location. */
16595 if (cfun->machine->frame.ra_fp_offset == 0)
16596 /* ra not saved, pass zero. */
16597 fprintf (file, "\tmove\t%s,%s\n", reg_names[12], reg_names[0]);
16599 fprintf (file, "\t%s\t%s," HOST_WIDE_INT_PRINT_DEC "(%s)\n",
16600 Pmode == DImode ? "dla" : "la", reg_names[12],
16601 cfun->machine->frame.ra_fp_offset,
16602 reg_names[STACK_POINTER_REGNUM]);
16604 if (!TARGET_NEWABI)
16606 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n",
16607 TARGET_64BIT ? "dsubu" : "subu",
16608 reg_names[STACK_POINTER_REGNUM],
16609 reg_names[STACK_POINTER_REGNUM],
16610 Pmode == DImode ? 16 : 8);
16612 if (TARGET_LONG_CALLS)
16613 fprintf (file, "\tjalr\t%s\n", reg_names[3]);
16615 fprintf (file, "\tjal\t_mcount\n");
16616 mips_pop_asm_switch (&mips_noat);
16617 /* _mcount treats $2 as the static chain register. */
16618 if (cfun->static_chain_decl != NULL)
16619 fprintf (file, "\tmove\t%s,%s\n", reg_names[STATIC_CHAIN_REGNUM],
16623 /* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default
16624 behaviour of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even
16625 when TARGET_LOONGSON_VECTORS is true. */
16627 static unsigned HOST_WIDE_INT
16628 mips_shift_truncation_mask (enum machine_mode mode)
16630 if (TARGET_LOONGSON_VECTORS && VECTOR_MODE_P (mode))
16633 return GET_MODE_BITSIZE (mode) - 1;
16636 /* Implement TARGET_PREPARE_PCH_SAVE. */
16639 mips_prepare_pch_save (void)
16641 /* We are called in a context where the current MIPS16 vs. non-MIPS16
16642 setting should be irrelevant. The question then is: which setting
16643 makes most sense at load time?
16645 The PCH is loaded before the first token is read. We should never
16646 have switched into MIPS16 mode by that point, and thus should not
16647 have populated mips16_globals. Nor can we load the entire contents
16648 of mips16_globals from the PCH file, because mips16_globals contains
16649 a combination of GGC and non-GGC data.
16651 There is therefore no point in trying save the GGC part of
16652 mips16_globals to the PCH file, or to preserve MIPS16ness across
16653 the PCH save and load. The loading compiler would not have access
16654 to the non-GGC parts of mips16_globals (either from the PCH file,
16655 or from a copy that the loading compiler generated itself) and would
16656 have to call target_reinit anyway.
16658 It therefore seems best to switch back to non-MIPS16 mode at
16659 save time, and to ensure that mips16_globals remains null after
16661 mips_set_mips16_mode (false);
16662 mips16_globals = 0;
16665 /* Generate or test for an insn that supports a constant permutation. */
16667 #define MAX_VECT_LEN 8
16669 struct expand_vec_perm_d
16671 rtx target, op0, op1;
16672 unsigned char perm[MAX_VECT_LEN];
16673 enum machine_mode vmode;
16674 unsigned char nelt;
16679 /* Construct (set target (vec_select op0 (parallel perm))) and
16680 return true if that's a valid instruction in the active ISA. */
16683 mips_expand_vselect (rtx target, rtx op0,
16684 const unsigned char *perm, unsigned nelt)
16686 rtx rperm[MAX_VECT_LEN], x;
16689 for (i = 0; i < nelt; ++i)
16690 rperm[i] = GEN_INT (perm[i]);
16692 x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (nelt, rperm));
16693 x = gen_rtx_VEC_SELECT (GET_MODE (target), op0, x);
16694 x = gen_rtx_SET (VOIDmode, target, x);
16697 if (recog_memoized (x) < 0)
16705 /* Similar, but generate a vec_concat from op0 and op1 as well. */
16708 mips_expand_vselect_vconcat (rtx target, rtx op0, rtx op1,
16709 const unsigned char *perm, unsigned nelt)
16711 enum machine_mode v2mode;
16714 v2mode = GET_MODE_2XWIDER_MODE (GET_MODE (op0));
16715 x = gen_rtx_VEC_CONCAT (v2mode, op0, op1);
16716 return mips_expand_vselect (target, x, perm, nelt);
16719 /* Recognize patterns for even-odd extraction. */
16722 mips_expand_vpc_loongson_even_odd (struct expand_vec_perm_d *d)
16724 unsigned i, odd, nelt = d->nelt;
16725 rtx t0, t1, t2, t3;
16727 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
16729 /* Even-odd for V2SI/V2SFmode is matched by interleave directly. */
16736 for (i = 1; i < nelt; ++i)
16737 if (d->perm[i] != i * 2 + odd)
16743 /* We need 2*log2(N)-1 operations to achieve odd/even with interleave. */
16744 t0 = gen_reg_rtx (d->vmode);
16745 t1 = gen_reg_rtx (d->vmode);
16749 emit_insn (gen_loongson_punpckhhw (t0, d->op0, d->op1));
16750 emit_insn (gen_loongson_punpcklhw (t1, d->op0, d->op1));
16752 emit_insn (gen_loongson_punpckhhw (d->target, t1, t0));
16754 emit_insn (gen_loongson_punpcklhw (d->target, t1, t0));
16758 t2 = gen_reg_rtx (d->vmode);
16759 t3 = gen_reg_rtx (d->vmode);
16760 emit_insn (gen_loongson_punpckhbh (t0, d->op0, d->op1));
16761 emit_insn (gen_loongson_punpcklbh (t1, d->op0, d->op1));
16762 emit_insn (gen_loongson_punpckhbh (t2, t1, t0));
16763 emit_insn (gen_loongson_punpcklbh (t3, t1, t0));
16765 emit_insn (gen_loongson_punpckhbh (d->target, t3, t2));
16767 emit_insn (gen_loongson_punpcklbh (d->target, t3, t2));
16771 gcc_unreachable ();
16776 /* Recognize patterns for the Loongson PSHUFH instruction. */
16779 mips_expand_vpc_loongson_pshufh (struct expand_vec_perm_d *d)
16784 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
16786 if (d->vmode != V4HImode)
16791 /* Convert the selector into the packed 8-bit form for pshufh. */
16792 /* Recall that loongson is little-endian only. No big-endian
16793 adjustment required. */
16794 for (i = mask = 0; i < 4; i++)
16795 mask |= (d->perm[i] & 3) << (i * 2);
16796 rmask = force_reg (SImode, GEN_INT (mask));
16798 if (d->one_vector_p)
16799 emit_insn (gen_loongson_pshufh (d->target, d->op0, rmask));
16802 rtx t0, t1, x, merge, rmerge[4];
16804 t0 = gen_reg_rtx (V4HImode);
16805 t1 = gen_reg_rtx (V4HImode);
16806 emit_insn (gen_loongson_pshufh (t1, d->op1, rmask));
16807 emit_insn (gen_loongson_pshufh (t0, d->op0, rmask));
16809 for (i = 0; i < 4; ++i)
16810 rmerge[i] = (d->perm[i] & 4 ? constm1_rtx : const0_rtx);
16811 merge = gen_rtx_CONST_VECTOR (V4HImode, gen_rtvec_v (4, rmerge));
16812 merge = force_reg (V4HImode, merge);
16814 x = gen_rtx_AND (V4HImode, merge, t1);
16815 emit_insn (gen_rtx_SET (VOIDmode, t1, x));
16817 x = gen_rtx_NOT (V4HImode, merge);
16818 x = gen_rtx_AND (V4HImode, x, t0);
16819 emit_insn (gen_rtx_SET (VOIDmode, t0, x));
16821 x = gen_rtx_IOR (V4HImode, t0, t1);
16822 emit_insn (gen_rtx_SET (VOIDmode, d->target, x));
16828 /* Recognize broadcast patterns for the Loongson. */
16831 mips_expand_vpc_loongson_bcast (struct expand_vec_perm_d *d)
16836 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
16838 /* Note that we've already matched V2SI via punpck and V4HI via pshufh. */
16839 if (d->vmode != V8QImode)
16841 if (!d->one_vector_p)
16845 for (i = 1; i < 8; ++i)
16846 if (d->perm[i] != elt)
16852 /* With one interleave we put two of the desired element adjacent. */
16853 t0 = gen_reg_rtx (V8QImode);
16855 emit_insn (gen_loongson_punpcklbh (t0, d->op0, d->op0));
16857 emit_insn (gen_loongson_punpckhbh (t0, d->op0, d->op0));
16859 /* Shuffle that one HImode element into all locations. */
16862 t1 = gen_reg_rtx (V4HImode);
16863 emit_insn (gen_loongson_pshufh (t1, gen_lowpart (V4HImode, t0),
16864 force_reg (SImode, GEN_INT (elt))));
16866 emit_move_insn (d->target, gen_lowpart (V8QImode, t1));
16871 mips_expand_vec_perm_const_1 (struct expand_vec_perm_d *d)
16873 unsigned int i, nelt = d->nelt;
16874 unsigned char perm2[MAX_VECT_LEN];
16876 if (d->one_vector_p)
16878 /* Try interleave with alternating operands. */
16879 memcpy (perm2, d->perm, sizeof(perm2));
16880 for (i = 1; i < nelt; i += 2)
16882 if (mips_expand_vselect_vconcat (d->target, d->op0, d->op1, perm2, nelt))
16887 if (mips_expand_vselect_vconcat (d->target, d->op0, d->op1,
16891 /* Try again with swapped operands. */
16892 for (i = 0; i < nelt; ++i)
16893 perm2[i] = (d->perm[i] + nelt) & (2 * nelt - 1);
16894 if (mips_expand_vselect_vconcat (d->target, d->op1, d->op0, perm2, nelt))
16898 if (mips_expand_vpc_loongson_even_odd (d))
16900 if (mips_expand_vpc_loongson_pshufh (d))
16902 if (mips_expand_vpc_loongson_bcast (d))
16907 /* Expand a vec_perm_const pattern. */
16910 mips_expand_vec_perm_const (rtx operands[4])
16912 struct expand_vec_perm_d d;
16913 int i, nelt, which;
16914 unsigned char orig_perm[MAX_VECT_LEN];
16918 d.target = operands[0];
16919 d.op0 = operands[1];
16920 d.op1 = operands[2];
16923 d.vmode = GET_MODE (d.target);
16924 gcc_assert (VECTOR_MODE_P (d.vmode));
16925 d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
16926 d.testing_p = false;
16928 for (i = which = 0; i < nelt; ++i)
16930 rtx e = XVECEXP (sel, 0, i);
16931 int ei = INTVAL (e) & (2 * nelt - 1);
16932 which |= (ei < nelt ? 1 : 2);
16935 memcpy (d.perm, orig_perm, MAX_VECT_LEN);
16943 d.one_vector_p = false;
16944 if (!rtx_equal_p (d.op0, d.op1))
16949 for (i = 0; i < nelt; ++i)
16950 d.perm[i] &= nelt - 1;
16952 d.one_vector_p = true;
16957 d.one_vector_p = true;
16961 ok = mips_expand_vec_perm_const_1 (&d);
16963 /* If we were given a two-vector permutation which just happened to
16964 have both input vectors equal, we folded this into a one-vector
16965 permutation. There are several loongson patterns that are matched
16966 via direct vec_select+vec_concat expansion, but we do not have
16967 support in mips_expand_vec_perm_const_1 to guess the adjustment
16968 that should be made for a single operand. Just try again with
16969 the original permutation. */
16970 if (!ok && which == 3)
16972 d.op0 = operands[1];
16973 d.op1 = operands[2];
16974 d.one_vector_p = false;
16975 memcpy (d.perm, orig_perm, MAX_VECT_LEN);
16976 ok = mips_expand_vec_perm_const_1 (&d);
16982 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST_OK. */
16985 mips_vectorize_vec_perm_const_ok (enum machine_mode vmode,
16986 const unsigned char *sel)
16988 struct expand_vec_perm_d d;
16989 unsigned int i, nelt, which;
16993 d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
16994 d.testing_p = true;
16995 memcpy (d.perm, sel, nelt);
16997 /* Categorize the set of elements in the selector. */
16998 for (i = which = 0; i < nelt; ++i)
17000 unsigned char e = d.perm[i];
17001 gcc_assert (e < 2 * nelt);
17002 which |= (e < nelt ? 1 : 2);
17005 /* For all elements from second vector, fold the elements to first. */
17007 for (i = 0; i < nelt; ++i)
17010 /* Check whether the mask can be applied to the vector type. */
17011 d.one_vector_p = (which != 3);
17013 d.target = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 1);
17014 d.op1 = d.op0 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 2);
17015 if (!d.one_vector_p)
17016 d.op1 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 3);
17019 ret = mips_expand_vec_perm_const_1 (&d);
17025 /* Expand an integral vector unpack operation. */
17028 mips_expand_vec_unpack (rtx operands[2], bool unsigned_p, bool high_p)
17030 enum machine_mode imode = GET_MODE (operands[1]);
17031 rtx (*unpack) (rtx, rtx, rtx);
17032 rtx (*cmpgt) (rtx, rtx, rtx);
17033 rtx tmp, dest, zero;
17039 unpack = gen_loongson_punpckhbh;
17041 unpack = gen_loongson_punpcklbh;
17042 cmpgt = gen_loongson_pcmpgtb;
17046 unpack = gen_loongson_punpckhhw;
17048 unpack = gen_loongson_punpcklhw;
17049 cmpgt = gen_loongson_pcmpgth;
17052 gcc_unreachable ();
17055 zero = force_reg (imode, CONST0_RTX (imode));
17060 tmp = gen_reg_rtx (imode);
17061 emit_insn (cmpgt (tmp, zero, operands[1]));
17064 dest = gen_reg_rtx (imode);
17065 emit_insn (unpack (dest, operands[1], tmp));
17067 emit_move_insn (operands[0], gen_lowpart (GET_MODE (operands[0]), dest));
17070 /* A subroutine of mips_expand_vec_init, match constant vector elements. */
17073 mips_constant_elt_p (rtx x)
17075 return CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE;
17078 /* A subroutine of mips_expand_vec_init, expand via broadcast. */
17081 mips_expand_vi_broadcast (enum machine_mode vmode, rtx target, rtx elt)
17083 struct expand_vec_perm_d d;
17087 if (elt != const0_rtx)
17088 elt = force_reg (GET_MODE_INNER (vmode), elt);
17090 elt = gen_lowpart (DImode, elt);
17092 t1 = gen_reg_rtx (vmode);
17096 emit_insn (gen_loongson_vec_init1_v8qi (t1, elt));
17099 emit_insn (gen_loongson_vec_init1_v4hi (t1, elt));
17102 gcc_unreachable ();
17105 memset (&d, 0, sizeof (d));
17110 d.nelt = GET_MODE_NUNITS (vmode);
17111 d.one_vector_p = true;
17113 ok = mips_expand_vec_perm_const_1 (&d);
17117 /* A subroutine of mips_expand_vec_init, replacing all of the non-constant
17118 elements of VALS with zeros, copy the constant vector to TARGET. */
17121 mips_expand_vi_constant (enum machine_mode vmode, unsigned nelt,
17122 rtx target, rtx vals)
17124 rtvec vec = shallow_copy_rtvec (XVEC (vals, 0));
17127 for (i = 0; i < nelt; ++i)
17129 if (!mips_constant_elt_p (RTVEC_ELT (vec, i)))
17130 RTVEC_ELT (vec, i) = const0_rtx;
17133 emit_move_insn (target, gen_rtx_CONST_VECTOR (vmode, vec));
17137 /* A subroutine of mips_expand_vec_init, expand via pinsrh. */
17140 mips_expand_vi_loongson_one_pinsrh (rtx target, rtx vals, unsigned one_var)
17142 mips_expand_vi_constant (V4HImode, 4, target, vals);
17144 emit_insn (gen_vec_setv4hi (target, target, XVECEXP (vals, 0, one_var),
17145 GEN_INT (one_var)));
17148 /* A subroutine of mips_expand_vec_init, expand anything via memory. */
17151 mips_expand_vi_general (enum machine_mode vmode, enum machine_mode imode,
17152 unsigned nelt, unsigned nvar, rtx target, rtx vals)
17154 rtx mem = assign_stack_temp (vmode, GET_MODE_SIZE (vmode), 0);
17155 unsigned int i, isize = GET_MODE_SIZE (imode);
17158 mips_expand_vi_constant (vmode, nelt, mem, vals);
17160 for (i = 0; i < nelt; ++i)
17162 rtx x = XVECEXP (vals, 0, i);
17163 if (!mips_constant_elt_p (x))
17164 emit_move_insn (adjust_address (mem, imode, i * isize), x);
17167 emit_move_insn (target, mem);
17170 /* Expand a vector initialization. */
17173 mips_expand_vector_init (rtx target, rtx vals)
17175 enum machine_mode vmode = GET_MODE (target);
17176 enum machine_mode imode = GET_MODE_INNER (vmode);
17177 unsigned i, nelt = GET_MODE_NUNITS (vmode);
17178 unsigned nvar = 0, one_var = -1u;
17179 bool all_same = true;
17182 for (i = 0; i < nelt; ++i)
17184 x = XVECEXP (vals, 0, i);
17185 if (!mips_constant_elt_p (x))
17186 nvar++, one_var = i;
17187 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
17191 /* Load constants from the pool, or whatever's handy. */
17194 emit_move_insn (target, gen_rtx_CONST_VECTOR (vmode, XVEC (vals, 0)));
17198 /* For two-part initialization, always use CONCAT. */
17201 rtx op0 = force_reg (imode, XVECEXP (vals, 0, 0));
17202 rtx op1 = force_reg (imode, XVECEXP (vals, 0, 1));
17203 x = gen_rtx_VEC_CONCAT (vmode, op0, op1);
17204 emit_insn (gen_rtx_SET (VOIDmode, target, x));
17208 /* Loongson is the only cpu with vectors with more elements. */
17209 gcc_assert (TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS);
17211 /* If all values are identical, broadcast the value. */
17214 mips_expand_vi_broadcast (vmode, target, XVECEXP (vals, 0, 0));
17218 /* If we've only got one non-variable V4HImode, use PINSRH. */
17219 if (nvar == 1 && vmode == V4HImode)
17221 mips_expand_vi_loongson_one_pinsrh (target, vals, one_var);
17225 mips_expand_vi_general (vmode, imode, nelt, nvar, target, vals);
17228 /* Expand a vector reduction. */
17231 mips_expand_vec_reduc (rtx target, rtx in, rtx (*gen)(rtx, rtx, rtx))
17233 enum machine_mode vmode = GET_MODE (in);
17234 unsigned char perm2[2];
17235 rtx last, next, fold, x;
17239 fold = gen_reg_rtx (vmode);
17243 /* Use PUL/PLU to produce { L, H } op { H, L }.
17244 By reversing the pair order, rather than a pure interleave high,
17245 we avoid erroneous exceptional conditions that we might otherwise
17246 produce from the computation of H op H. */
17249 ok = mips_expand_vselect_vconcat (fold, last, last, perm2, 2);
17254 /* Use interleave to produce { H, L } op { H, H }. */
17255 emit_insn (gen_loongson_punpckhwd (fold, last, last));
17259 /* Perform the first reduction with interleave,
17260 and subsequent reductions with shifts. */
17261 emit_insn (gen_loongson_punpckhwd_hi (fold, last, last));
17263 next = gen_reg_rtx (vmode);
17264 emit_insn (gen (next, last, fold));
17267 fold = gen_reg_rtx (vmode);
17268 x = force_reg (SImode, GEN_INT (16));
17269 emit_insn (gen_vec_shr_v4hi (fold, last, x));
17273 emit_insn (gen_loongson_punpckhwd_qi (fold, last, last));
17275 next = gen_reg_rtx (vmode);
17276 emit_insn (gen (next, last, fold));
17279 fold = gen_reg_rtx (vmode);
17280 x = force_reg (SImode, GEN_INT (16));
17281 emit_insn (gen_vec_shr_v8qi (fold, last, x));
17283 next = gen_reg_rtx (vmode);
17284 emit_insn (gen (next, last, fold));
17287 fold = gen_reg_rtx (vmode);
17288 x = force_reg (SImode, GEN_INT (8));
17289 emit_insn (gen_vec_shr_v8qi (fold, last, x));
17293 gcc_unreachable ();
17296 emit_insn (gen (target, last, fold));
17299 /* Expand a vector minimum/maximum. */
17302 mips_expand_vec_minmax (rtx target, rtx op0, rtx op1,
17303 rtx (*cmp) (rtx, rtx, rtx), bool min_p)
17305 enum machine_mode vmode = GET_MODE (target);
17308 tc = gen_reg_rtx (vmode);
17309 t0 = gen_reg_rtx (vmode);
17310 t1 = gen_reg_rtx (vmode);
17313 emit_insn (cmp (tc, op0, op1));
17315 x = gen_rtx_AND (vmode, tc, (min_p ? op1 : op0));
17316 emit_insn (gen_rtx_SET (VOIDmode, t0, x));
17318 x = gen_rtx_NOT (vmode, tc);
17319 x = gen_rtx_AND (vmode, x, (min_p ? op0 : op1));
17320 emit_insn (gen_rtx_SET (VOIDmode, t1, x));
17322 x = gen_rtx_IOR (vmode, t0, t1);
17323 emit_insn (gen_rtx_SET (VOIDmode, target, x));
17326 /* Initialize the GCC target structure. */
17327 #undef TARGET_ASM_ALIGNED_HI_OP
17328 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
17329 #undef TARGET_ASM_ALIGNED_SI_OP
17330 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
17331 #undef TARGET_ASM_ALIGNED_DI_OP
17332 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
17334 #undef TARGET_OPTION_OVERRIDE
17335 #define TARGET_OPTION_OVERRIDE mips_option_override
17337 #undef TARGET_LEGITIMIZE_ADDRESS
17338 #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
17340 #undef TARGET_ASM_FUNCTION_PROLOGUE
17341 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
17342 #undef TARGET_ASM_FUNCTION_EPILOGUE
17343 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
17344 #undef TARGET_ASM_SELECT_RTX_SECTION
17345 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
17346 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
17347 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
17349 #undef TARGET_SCHED_INIT
17350 #define TARGET_SCHED_INIT mips_sched_init
17351 #undef TARGET_SCHED_REORDER
17352 #define TARGET_SCHED_REORDER mips_sched_reorder
17353 #undef TARGET_SCHED_REORDER2
17354 #define TARGET_SCHED_REORDER2 mips_sched_reorder2
17355 #undef TARGET_SCHED_VARIABLE_ISSUE
17356 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
17357 #undef TARGET_SCHED_ADJUST_COST
17358 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
17359 #undef TARGET_SCHED_ISSUE_RATE
17360 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
17361 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
17362 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
17363 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
17364 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
17365 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
17366 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
17367 mips_multipass_dfa_lookahead
17368 #undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
17369 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
17370 mips_small_register_classes_for_mode_p
17372 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
17373 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
17375 #undef TARGET_INSERT_ATTRIBUTES
17376 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
17377 #undef TARGET_MERGE_DECL_ATTRIBUTES
17378 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
17379 #undef TARGET_SET_CURRENT_FUNCTION
17380 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
17382 #undef TARGET_VALID_POINTER_MODE
17383 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
17384 #undef TARGET_REGISTER_MOVE_COST
17385 #define TARGET_REGISTER_MOVE_COST mips_register_move_cost
17386 #undef TARGET_MEMORY_MOVE_COST
17387 #define TARGET_MEMORY_MOVE_COST mips_memory_move_cost
17388 #undef TARGET_RTX_COSTS
17389 #define TARGET_RTX_COSTS mips_rtx_costs
17390 #undef TARGET_ADDRESS_COST
17391 #define TARGET_ADDRESS_COST mips_address_cost
17393 #undef TARGET_IN_SMALL_DATA_P
17394 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
17396 #undef TARGET_MACHINE_DEPENDENT_REORG
17397 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
17399 #undef TARGET_PREFERRED_RELOAD_CLASS
17400 #define TARGET_PREFERRED_RELOAD_CLASS mips_preferred_reload_class
17402 #undef TARGET_ASM_FILE_START
17403 #define TARGET_ASM_FILE_START mips_file_start
17404 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
17405 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
17406 #undef TARGET_ASM_CODE_END
17407 #define TARGET_ASM_CODE_END mips_code_end
17409 #undef TARGET_INIT_LIBFUNCS
17410 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
17412 #undef TARGET_BUILD_BUILTIN_VA_LIST
17413 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
17414 #undef TARGET_EXPAND_BUILTIN_VA_START
17415 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
17416 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
17417 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
17419 #undef TARGET_PROMOTE_FUNCTION_MODE
17420 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
17421 #undef TARGET_PROMOTE_PROTOTYPES
17422 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
17424 #undef TARGET_FUNCTION_VALUE
17425 #define TARGET_FUNCTION_VALUE mips_function_value
17426 #undef TARGET_LIBCALL_VALUE
17427 #define TARGET_LIBCALL_VALUE mips_libcall_value
17428 #undef TARGET_FUNCTION_VALUE_REGNO_P
17429 #define TARGET_FUNCTION_VALUE_REGNO_P mips_function_value_regno_p
17430 #undef TARGET_RETURN_IN_MEMORY
17431 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
17432 #undef TARGET_RETURN_IN_MSB
17433 #define TARGET_RETURN_IN_MSB mips_return_in_msb
17435 #undef TARGET_ASM_OUTPUT_MI_THUNK
17436 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
17437 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
17438 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
17440 #undef TARGET_PRINT_OPERAND
17441 #define TARGET_PRINT_OPERAND mips_print_operand
17442 #undef TARGET_PRINT_OPERAND_ADDRESS
17443 #define TARGET_PRINT_OPERAND_ADDRESS mips_print_operand_address
17444 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
17445 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mips_print_operand_punct_valid_p
17447 #undef TARGET_SETUP_INCOMING_VARARGS
17448 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
17449 #undef TARGET_STRICT_ARGUMENT_NAMING
17450 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
17451 #undef TARGET_MUST_PASS_IN_STACK
17452 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
17453 #undef TARGET_PASS_BY_REFERENCE
17454 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
17455 #undef TARGET_CALLEE_COPIES
17456 #define TARGET_CALLEE_COPIES mips_callee_copies
17457 #undef TARGET_ARG_PARTIAL_BYTES
17458 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
17459 #undef TARGET_FUNCTION_ARG
17460 #define TARGET_FUNCTION_ARG mips_function_arg
17461 #undef TARGET_FUNCTION_ARG_ADVANCE
17462 #define TARGET_FUNCTION_ARG_ADVANCE mips_function_arg_advance
17463 #undef TARGET_FUNCTION_ARG_BOUNDARY
17464 #define TARGET_FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
17466 #undef TARGET_MODE_REP_EXTENDED
17467 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
17469 #undef TARGET_VECTOR_MODE_SUPPORTED_P
17470 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
17472 #undef TARGET_SCALAR_MODE_SUPPORTED_P
17473 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
17475 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
17476 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE mips_preferred_simd_mode
17478 #undef TARGET_INIT_BUILTINS
17479 #define TARGET_INIT_BUILTINS mips_init_builtins
17480 #undef TARGET_BUILTIN_DECL
17481 #define TARGET_BUILTIN_DECL mips_builtin_decl
17482 #undef TARGET_EXPAND_BUILTIN
17483 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
17485 #undef TARGET_HAVE_TLS
17486 #define TARGET_HAVE_TLS HAVE_AS_TLS
17488 #undef TARGET_CANNOT_FORCE_CONST_MEM
17489 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
17491 #undef TARGET_LEGITIMATE_CONSTANT_P
17492 #define TARGET_LEGITIMATE_CONSTANT_P mips_legitimate_constant_p
17494 #undef TARGET_ENCODE_SECTION_INFO
17495 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
17497 #undef TARGET_ATTRIBUTE_TABLE
17498 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
17499 /* All our function attributes are related to how out-of-line copies should
17500 be compiled or called. They don't in themselves prevent inlining. */
17501 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
17502 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
17504 #undef TARGET_EXTRA_LIVE_ON_ENTRY
17505 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
17507 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
17508 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
17509 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
17510 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
17512 #undef TARGET_COMP_TYPE_ATTRIBUTES
17513 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
17515 #ifdef HAVE_AS_DTPRELWORD
17516 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
17517 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
17519 #undef TARGET_DWARF_REGISTER_SPAN
17520 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
17522 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
17523 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
17525 #undef TARGET_LEGITIMATE_ADDRESS_P
17526 #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p
17528 #undef TARGET_FRAME_POINTER_REQUIRED
17529 #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required
17531 #undef TARGET_CAN_ELIMINATE
17532 #define TARGET_CAN_ELIMINATE mips_can_eliminate
17534 #undef TARGET_CONDITIONAL_REGISTER_USAGE
17535 #define TARGET_CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage
17537 #undef TARGET_TRAMPOLINE_INIT
17538 #define TARGET_TRAMPOLINE_INIT mips_trampoline_init
17540 #undef TARGET_ASM_OUTPUT_SOURCE_FILENAME
17541 #define TARGET_ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
17543 #undef TARGET_SHIFT_TRUNCATION_MASK
17544 #define TARGET_SHIFT_TRUNCATION_MASK mips_shift_truncation_mask
17546 #undef TARGET_PREPARE_PCH_SAVE
17547 #define TARGET_PREPARE_PCH_SAVE mips_prepare_pch_save
17549 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
17550 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK mips_vectorize_vec_perm_const_ok
17552 struct gcc_target targetm = TARGET_INITIALIZER;
17554 #include "gt-mips.h"