1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
5 Free Software Foundation, Inc.
6 Contributed by A. Lichnewsky, lich@inria.inria.fr.
7 Changes by Michael Meissner, meissner@osf.org.
8 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
9 Brendan Eich, brendan@microunity.com.
11 This file is part of GCC.
13 GCC is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GCC is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GCC; see the file COPYING3. If not see
25 <http://www.gnu.org/licenses/>. */
29 #include "coretypes.h"
33 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
36 #include "insn-attr.h"
52 #include "target-def.h"
53 #include "langhooks.h"
54 #include "sched-int.h"
57 #include "diagnostic.h"
58 #include "target-globals.h"
61 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
62 #define UNSPEC_ADDRESS_P(X) \
63 (GET_CODE (X) == UNSPEC \
64 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
65 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
67 /* Extract the symbol or label from UNSPEC wrapper X. */
68 #define UNSPEC_ADDRESS(X) \
71 /* Extract the symbol type from UNSPEC wrapper X. */
72 #define UNSPEC_ADDRESS_TYPE(X) \
73 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
75 /* The maximum distance between the top of the stack frame and the
76 value $sp has when we save and restore registers.
78 The value for normal-mode code must be a SMALL_OPERAND and must
79 preserve the maximum stack alignment. We therefore use a value
80 of 0x7ff0 in this case.
82 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
83 up to 0x7f8 bytes and can usually save or restore all the registers
84 that we need to save or restore. (Note that we can only use these
85 instructions for o32, for which the stack alignment is 8 bytes.)
87 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
88 RESTORE are not available. We can then use unextended instructions
89 to save and restore registers, and to allocate and deallocate the top
91 #define MIPS_MAX_FIRST_STACK_STEP \
92 (!TARGET_MIPS16 ? 0x7ff0 \
93 : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
94 : TARGET_64BIT ? 0x100 : 0x400)
96 /* True if INSN is a mips.md pattern or asm statement. */
97 #define USEFUL_INSN_P(INSN) \
98 (NONDEBUG_INSN_P (INSN) \
99 && GET_CODE (PATTERN (INSN)) != USE \
100 && GET_CODE (PATTERN (INSN)) != CLOBBER \
101 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
102 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
104 /* If INSN is a delayed branch sequence, return the first instruction
105 in the sequence, otherwise return INSN itself. */
106 #define SEQ_BEGIN(INSN) \
107 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
108 ? XVECEXP (PATTERN (INSN), 0, 0) \
111 /* Likewise for the last instruction in a delayed branch sequence. */
112 #define SEQ_END(INSN) \
113 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
114 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
117 /* Execute the following loop body with SUBINSN set to each instruction
118 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
119 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
120 for ((SUBINSN) = SEQ_BEGIN (INSN); \
121 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
122 (SUBINSN) = NEXT_INSN (SUBINSN))
124 /* True if bit BIT is set in VALUE. */
125 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
127 /* Return the opcode for a ptr_mode load of the form:
129 l[wd] DEST, OFFSET(BASE). */
130 #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \
131 (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \
136 /* Return the opcode to move register SRC into register DEST. */
137 #define MIPS_MOVE(DEST, SRC) \
138 ((TARGET_64BIT ? 0x2d : 0x21) \
142 /* Return the opcode for:
145 #define MIPS_LUI(DEST, VALUE) \
146 ((0xf << 26) | ((DEST) << 16) | (VALUE))
148 /* Return the opcode to jump to register DEST. */
149 #define MIPS_JR(DEST) \
150 (((DEST) << 21) | 0x8)
152 /* Return the opcode for:
154 bal . + (1 + OFFSET) * 4. */
155 #define MIPS_BAL(OFFSET) \
156 ((0x1 << 26) | (0x11 << 16) | (OFFSET))
158 /* Return the usual opcode for a nop. */
161 /* Classifies an address.
164 A natural register + offset address. The register satisfies
165 mips_valid_base_register_p and the offset is a const_arith_operand.
168 A LO_SUM rtx. The first operand is a valid base register and
169 the second operand is a symbolic address.
172 A signed 16-bit constant address.
175 A constant symbolic address. */
176 enum mips_address_type {
183 /* Macros to create an enumeration identifier for a function prototype. */
184 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
185 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
186 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
187 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
189 /* Classifies the prototype of a built-in function. */
190 enum mips_function_type {
191 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
192 #include "config/mips/mips-ftypes.def"
193 #undef DEF_MIPS_FTYPE
197 /* Specifies how a built-in function should be converted into rtl. */
198 enum mips_builtin_type {
199 /* The function corresponds directly to an .md pattern. The return
200 value is mapped to operand 0 and the arguments are mapped to
201 operands 1 and above. */
204 /* The function corresponds directly to an .md pattern. There is no return
205 value and the arguments are mapped to operands 0 and above. */
206 MIPS_BUILTIN_DIRECT_NO_TARGET,
208 /* The function corresponds to a comparison instruction followed by
209 a mips_cond_move_tf_ps pattern. The first two arguments are the
210 values to compare and the second two arguments are the vector
211 operands for the movt.ps or movf.ps instruction (in assembly order). */
215 /* The function corresponds to a V2SF comparison instruction. Operand 0
216 of this instruction is the result of the comparison, which has mode
217 CCV2 or CCV4. The function arguments are mapped to operands 1 and
218 above. The function's return value is an SImode boolean that is
219 true under the following conditions:
221 MIPS_BUILTIN_CMP_ANY: one of the registers is true
222 MIPS_BUILTIN_CMP_ALL: all of the registers are true
223 MIPS_BUILTIN_CMP_LOWER: the first register is true
224 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
225 MIPS_BUILTIN_CMP_ANY,
226 MIPS_BUILTIN_CMP_ALL,
227 MIPS_BUILTIN_CMP_UPPER,
228 MIPS_BUILTIN_CMP_LOWER,
230 /* As above, but the instruction only sets a single $fcc register. */
231 MIPS_BUILTIN_CMP_SINGLE,
233 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
234 MIPS_BUILTIN_BPOSGE32
237 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
238 #define MIPS_FP_CONDITIONS(MACRO) \
256 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
257 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
258 enum mips_fp_condition {
259 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
262 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
263 #define STRINGIFY(X) #X
264 static const char *const mips_fp_conditions[] = {
265 MIPS_FP_CONDITIONS (STRINGIFY)
268 /* Information about a function's frame layout. */
269 struct GTY(()) mips_frame_info {
270 /* The size of the frame in bytes. */
271 HOST_WIDE_INT total_size;
273 /* The number of bytes allocated to variables. */
274 HOST_WIDE_INT var_size;
276 /* The number of bytes allocated to outgoing function arguments. */
277 HOST_WIDE_INT args_size;
279 /* The number of bytes allocated to the .cprestore slot, or 0 if there
281 HOST_WIDE_INT cprestore_size;
283 /* Bit X is set if the function saves or restores GPR X. */
286 /* Likewise FPR X. */
289 /* Likewise doubleword accumulator X ($acX). */
290 unsigned int acc_mask;
292 /* The number of GPRs, FPRs, doubleword accumulators and COP0
296 unsigned int num_acc;
297 unsigned int num_cop0_regs;
299 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
300 save slots from the top of the frame, or zero if no such slots are
302 HOST_WIDE_INT gp_save_offset;
303 HOST_WIDE_INT fp_save_offset;
304 HOST_WIDE_INT acc_save_offset;
305 HOST_WIDE_INT cop0_save_offset;
307 /* Likewise, but giving offsets from the bottom of the frame. */
308 HOST_WIDE_INT gp_sp_offset;
309 HOST_WIDE_INT fp_sp_offset;
310 HOST_WIDE_INT acc_sp_offset;
311 HOST_WIDE_INT cop0_sp_offset;
313 /* Similar, but the value passed to _mcount. */
314 HOST_WIDE_INT ra_fp_offset;
316 /* The offset of arg_pointer_rtx from the bottom of the frame. */
317 HOST_WIDE_INT arg_pointer_offset;
319 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
320 HOST_WIDE_INT hard_frame_pointer_offset;
323 struct GTY(()) machine_function {
324 /* The next floating-point condition-code register to allocate
325 for ISA_HAS_8CC targets, relative to ST_REG_FIRST. */
326 unsigned int next_fcc;
328 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
329 rtx mips16_gp_pseudo_rtx;
331 /* The number of extra stack bytes taken up by register varargs.
332 This area is allocated by the callee at the very top of the frame. */
335 /* The current frame information, calculated by mips_compute_frame_info. */
336 struct mips_frame_info frame;
338 /* The register to use as the function's global pointer, or INVALID_REGNUM
339 if the function doesn't need one. */
340 unsigned int global_pointer;
342 /* How many instructions it takes to load a label into $AT, or 0 if
343 this property hasn't yet been calculated. */
344 unsigned int load_label_num_insns;
346 /* True if mips_adjust_insn_length should ignore an instruction's
348 bool ignore_hazard_length_p;
350 /* True if the whole function is suitable for .set noreorder and
352 bool all_noreorder_p;
354 /* True if the function has "inflexible" and "flexible" references
355 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
356 and mips_cfun_has_flexible_gp_ref_p for details. */
357 bool has_inflexible_gp_insn_p;
358 bool has_flexible_gp_insn_p;
360 /* True if the function's prologue must load the global pointer
361 value into pic_offset_table_rtx and store the same value in
362 the function's cprestore slot (if any). Even if this value
363 is currently false, we may decide to set it to true later;
364 see mips_must_initialize_gp_p () for details. */
365 bool must_initialize_gp_p;
367 /* True if the current function must restore $gp after any potential
368 clobber. This value is only meaningful during the first post-epilogue
369 split_insns pass; see mips_must_initialize_gp_p () for details. */
370 bool must_restore_gp_when_clobbered_p;
372 /* True if this is an interrupt handler. */
373 bool interrupt_handler_p;
375 /* True if this is an interrupt handler that uses shadow registers. */
376 bool use_shadow_register_set_p;
378 /* True if this is an interrupt handler that should keep interrupts
380 bool keep_interrupts_masked_p;
382 /* True if this is an interrupt handler that should use DERET
384 bool use_debug_exception_return_p;
387 /* Information about a single argument. */
388 struct mips_arg_info {
389 /* True if the argument is passed in a floating-point register, or
390 would have been if we hadn't run out of registers. */
393 /* The number of words passed in registers, rounded up. */
394 unsigned int reg_words;
396 /* For EABI, the offset of the first register from GP_ARG_FIRST or
397 FP_ARG_FIRST. For other ABIs, the offset of the first register from
398 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
399 comment for details).
401 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
403 unsigned int reg_offset;
405 /* The number of words that must be passed on the stack, rounded up. */
406 unsigned int stack_words;
408 /* The offset from the start of the stack overflow area of the argument's
409 first stack word. Only meaningful when STACK_WORDS is nonzero. */
410 unsigned int stack_offset;
413 /* Information about an address described by mips_address_type.
419 REG is the base register and OFFSET is the constant offset.
422 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
423 is the type of symbol it references.
426 SYMBOL_TYPE is the type of symbol that the address references. */
427 struct mips_address_info {
428 enum mips_address_type type;
431 enum mips_symbol_type symbol_type;
434 /* One stage in a constant building sequence. These sequences have
438 A = A CODE[1] VALUE[1]
439 A = A CODE[2] VALUE[2]
442 where A is an accumulator, each CODE[i] is a binary rtl operation
443 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
444 struct mips_integer_op {
446 unsigned HOST_WIDE_INT value;
449 /* The largest number of operations needed to load an integer constant.
450 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
451 When the lowest bit is clear, we can try, but reject a sequence with
452 an extra SLL at the end. */
453 #define MIPS_MAX_INTEGER_OPS 7
455 /* Information about a MIPS16e SAVE or RESTORE instruction. */
456 struct mips16e_save_restore_info {
457 /* The number of argument registers saved by a SAVE instruction.
458 0 for RESTORE instructions. */
461 /* Bit X is set if the instruction saves or restores GPR X. */
464 /* The total number of bytes to allocate. */
468 /* Costs of various operations on the different architectures. */
470 struct mips_rtx_cost_data
472 unsigned short fp_add;
473 unsigned short fp_mult_sf;
474 unsigned short fp_mult_df;
475 unsigned short fp_div_sf;
476 unsigned short fp_div_df;
477 unsigned short int_mult_si;
478 unsigned short int_mult_di;
479 unsigned short int_div_si;
480 unsigned short int_div_di;
481 unsigned short branch_cost;
482 unsigned short memory_latency;
485 /* Global variables for machine-dependent things. */
487 /* The -G setting, or the configuration's default small-data limit if
488 no -G option is given. */
489 static unsigned int mips_small_data_threshold;
491 /* The number of file directives written by mips_output_filename. */
492 int num_source_filenames;
494 /* The name that appeared in the last .file directive written by
495 mips_output_filename, or "" if mips_output_filename hasn't
496 written anything yet. */
497 const char *current_function_file = "";
499 /* Arrays that map GCC register numbers to debugger register numbers. */
500 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
501 int mips_dwarf_regno[FIRST_PSEUDO_REGISTER];
503 /* Information about the current function's epilogue, used only while
506 /* A list of queued REG_CFA_RESTORE notes. */
509 /* The CFA is currently defined as CFA_REG + CFA_OFFSET. */
511 HOST_WIDE_INT cfa_offset;
513 /* The offset of the CFA from the stack pointer while restoring
515 HOST_WIDE_INT cfa_restore_sp_offset;
518 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
519 struct mips_asm_switch mips_noreorder = { "reorder", 0 };
520 struct mips_asm_switch mips_nomacro = { "macro", 0 };
521 struct mips_asm_switch mips_noat = { "at", 0 };
523 /* True if we're writing out a branch-likely instruction rather than a
525 static bool mips_branch_likely;
527 /* The current instruction-set architecture. */
528 enum processor mips_arch;
529 const struct mips_cpu_info *mips_arch_info;
531 /* The processor that we should tune the code for. */
532 enum processor mips_tune;
533 const struct mips_cpu_info *mips_tune_info;
535 /* The ISA level associated with mips_arch. */
538 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
539 static const struct mips_cpu_info *mips_isa_option_info;
541 /* Which cost information to use. */
542 static const struct mips_rtx_cost_data *mips_cost;
544 /* The ambient target flags, excluding MASK_MIPS16. */
545 static int mips_base_target_flags;
547 /* True if MIPS16 is the default mode. */
548 bool mips_base_mips16;
550 /* The ambient values of other global variables. */
551 static int mips_base_schedule_insns; /* flag_schedule_insns */
552 static int mips_base_reorder_blocks_and_partition; /* flag_reorder... */
553 static int mips_base_move_loop_invariants; /* flag_move_loop_invariants */
554 static int mips_base_align_loops; /* align_loops */
555 static int mips_base_align_jumps; /* align_jumps */
556 static int mips_base_align_functions; /* align_functions */
558 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
559 bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
561 /* Index C is true if character C is a valid PRINT_OPERAND punctation
563 static bool mips_print_operand_punct[256];
565 static GTY (()) int mips_output_filename_first_time = 1;
567 /* mips_split_p[X] is true if symbols of type X can be split by
568 mips_split_symbol. */
569 bool mips_split_p[NUM_SYMBOL_TYPES];
571 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
572 can be split by mips_split_symbol. */
573 bool mips_split_hi_p[NUM_SYMBOL_TYPES];
575 /* mips_use_pcrel_pool_p[X] is true if symbols of type X should be
576 forced into a PC-relative constant pool. */
577 bool mips_use_pcrel_pool_p[NUM_SYMBOL_TYPES];
579 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
580 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
581 if they are matched by a special .md file pattern. */
582 const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
584 /* Likewise for HIGHs. */
585 const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
587 /* Target state for MIPS16. */
588 struct target_globals *mips16_globals;
590 /* Cached value of can_issue_more. This is cached in mips_variable_issue hook
591 and returned from mips_sched_reorder2. */
592 static int cached_can_issue_more;
594 /* True if the output uses __mips16_rdhwr. */
595 static bool mips_need_mips16_rdhwr_p;
597 /* Index R is the smallest register class that contains register R. */
598 const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = {
599 LEA_REGS, LEA_REGS, M16_REGS, V1_REG,
600 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
601 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
602 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
603 M16_REGS, M16_REGS, LEA_REGS, LEA_REGS,
604 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
605 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
606 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
607 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
608 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
609 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
610 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
611 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
612 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
613 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
614 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
615 MD0_REG, MD1_REG, NO_REGS, ST_REGS,
616 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
617 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
618 NO_REGS, FRAME_REGS, FRAME_REGS, NO_REGS,
619 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
620 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
621 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
622 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
623 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
624 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
625 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
626 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
627 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
628 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
629 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
630 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
631 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
632 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
633 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
634 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
635 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
636 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
637 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
638 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
639 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
640 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
641 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
642 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
643 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
644 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
645 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
648 /* The value of TARGET_ATTRIBUTE_TABLE. */
649 static const struct attribute_spec mips_attribute_table[] = {
650 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
652 { "long_call", 0, 0, false, true, true, NULL, false },
653 { "far", 0, 0, false, true, true, NULL, false },
654 { "near", 0, 0, false, true, true, NULL, false },
655 /* We would really like to treat "mips16" and "nomips16" as type
656 attributes, but GCC doesn't provide the hooks we need to support
657 the right conversion rules. As declaration attributes, they affect
658 code generation but don't carry other semantics. */
659 { "mips16", 0, 0, true, false, false, NULL, false },
660 { "nomips16", 0, 0, true, false, false, NULL, false },
661 /* Allow functions to be specified as interrupt handlers */
662 { "interrupt", 0, 0, false, true, true, NULL, false },
663 { "use_shadow_register_set", 0, 0, false, true, true, NULL, false },
664 { "keep_interrupts_masked", 0, 0, false, true, true, NULL, false },
665 { "use_debug_exception_return", 0, 0, false, true, true, NULL, false },
666 { NULL, 0, 0, false, false, false, NULL, false }
669 /* A table describing all the processors GCC knows about; see
670 mips-cpus.def for details. */
671 static const struct mips_cpu_info mips_cpu_info_table[] = {
672 #define MIPS_CPU(NAME, CPU, ISA, FLAGS) \
673 { NAME, CPU, ISA, FLAGS },
674 #include "mips-cpus.def"
678 /* Default costs. If these are used for a processor we should look
679 up the actual costs. */
680 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
681 COSTS_N_INSNS (7), /* fp_mult_sf */ \
682 COSTS_N_INSNS (8), /* fp_mult_df */ \
683 COSTS_N_INSNS (23), /* fp_div_sf */ \
684 COSTS_N_INSNS (36), /* fp_div_df */ \
685 COSTS_N_INSNS (10), /* int_mult_si */ \
686 COSTS_N_INSNS (10), /* int_mult_di */ \
687 COSTS_N_INSNS (69), /* int_div_si */ \
688 COSTS_N_INSNS (69), /* int_div_di */ \
689 2, /* branch_cost */ \
690 4 /* memory_latency */
692 /* Floating-point costs for processors without an FPU. Just assume that
693 all floating-point libcalls are very expensive. */
694 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
695 COSTS_N_INSNS (256), /* fp_mult_sf */ \
696 COSTS_N_INSNS (256), /* fp_mult_df */ \
697 COSTS_N_INSNS (256), /* fp_div_sf */ \
698 COSTS_N_INSNS (256) /* fp_div_df */
700 /* Costs to use when optimizing for size. */
701 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size = {
702 COSTS_N_INSNS (1), /* fp_add */
703 COSTS_N_INSNS (1), /* fp_mult_sf */
704 COSTS_N_INSNS (1), /* fp_mult_df */
705 COSTS_N_INSNS (1), /* fp_div_sf */
706 COSTS_N_INSNS (1), /* fp_div_df */
707 COSTS_N_INSNS (1), /* int_mult_si */
708 COSTS_N_INSNS (1), /* int_mult_di */
709 COSTS_N_INSNS (1), /* int_div_si */
710 COSTS_N_INSNS (1), /* int_div_di */
712 4 /* memory_latency */
715 /* Costs to use when optimizing for speed, indexed by processor. */
716 static const struct mips_rtx_cost_data
717 mips_rtx_cost_data[NUM_PROCESSOR_VALUES] = {
719 COSTS_N_INSNS (2), /* fp_add */
720 COSTS_N_INSNS (4), /* fp_mult_sf */
721 COSTS_N_INSNS (5), /* fp_mult_df */
722 COSTS_N_INSNS (12), /* fp_div_sf */
723 COSTS_N_INSNS (19), /* fp_div_df */
724 COSTS_N_INSNS (12), /* int_mult_si */
725 COSTS_N_INSNS (12), /* int_mult_di */
726 COSTS_N_INSNS (35), /* int_div_si */
727 COSTS_N_INSNS (35), /* int_div_di */
729 4 /* memory_latency */
733 COSTS_N_INSNS (6), /* int_mult_si */
734 COSTS_N_INSNS (6), /* int_mult_di */
735 COSTS_N_INSNS (36), /* int_div_si */
736 COSTS_N_INSNS (36), /* int_div_di */
738 4 /* memory_latency */
742 COSTS_N_INSNS (36), /* int_mult_si */
743 COSTS_N_INSNS (36), /* int_mult_di */
744 COSTS_N_INSNS (37), /* int_div_si */
745 COSTS_N_INSNS (37), /* int_div_di */
747 4 /* memory_latency */
751 COSTS_N_INSNS (4), /* int_mult_si */
752 COSTS_N_INSNS (11), /* int_mult_di */
753 COSTS_N_INSNS (36), /* int_div_si */
754 COSTS_N_INSNS (68), /* int_div_di */
756 4 /* memory_latency */
759 COSTS_N_INSNS (4), /* fp_add */
760 COSTS_N_INSNS (4), /* fp_mult_sf */
761 COSTS_N_INSNS (5), /* fp_mult_df */
762 COSTS_N_INSNS (17), /* fp_div_sf */
763 COSTS_N_INSNS (32), /* fp_div_df */
764 COSTS_N_INSNS (4), /* int_mult_si */
765 COSTS_N_INSNS (11), /* int_mult_di */
766 COSTS_N_INSNS (36), /* int_div_si */
767 COSTS_N_INSNS (68), /* int_div_di */
769 4 /* memory_latency */
772 COSTS_N_INSNS (4), /* fp_add */
773 COSTS_N_INSNS (4), /* fp_mult_sf */
774 COSTS_N_INSNS (5), /* fp_mult_df */
775 COSTS_N_INSNS (17), /* fp_div_sf */
776 COSTS_N_INSNS (32), /* fp_div_df */
777 COSTS_N_INSNS (4), /* int_mult_si */
778 COSTS_N_INSNS (7), /* int_mult_di */
779 COSTS_N_INSNS (42), /* int_div_si */
780 COSTS_N_INSNS (72), /* int_div_di */
782 4 /* memory_latency */
786 COSTS_N_INSNS (5), /* int_mult_si */
787 COSTS_N_INSNS (5), /* int_mult_di */
788 COSTS_N_INSNS (41), /* int_div_si */
789 COSTS_N_INSNS (41), /* int_div_di */
791 4 /* memory_latency */
794 COSTS_N_INSNS (8), /* fp_add */
795 COSTS_N_INSNS (8), /* fp_mult_sf */
796 COSTS_N_INSNS (10), /* fp_mult_df */
797 COSTS_N_INSNS (34), /* fp_div_sf */
798 COSTS_N_INSNS (64), /* fp_div_df */
799 COSTS_N_INSNS (5), /* int_mult_si */
800 COSTS_N_INSNS (5), /* int_mult_di */
801 COSTS_N_INSNS (41), /* int_div_si */
802 COSTS_N_INSNS (41), /* int_div_di */
804 4 /* memory_latency */
807 COSTS_N_INSNS (4), /* fp_add */
808 COSTS_N_INSNS (4), /* fp_mult_sf */
809 COSTS_N_INSNS (5), /* fp_mult_df */
810 COSTS_N_INSNS (17), /* fp_div_sf */
811 COSTS_N_INSNS (32), /* fp_div_df */
812 COSTS_N_INSNS (5), /* int_mult_si */
813 COSTS_N_INSNS (5), /* int_mult_di */
814 COSTS_N_INSNS (41), /* int_div_si */
815 COSTS_N_INSNS (41), /* int_div_di */
817 4 /* memory_latency */
821 COSTS_N_INSNS (5), /* int_mult_si */
822 COSTS_N_INSNS (5), /* int_mult_di */
823 COSTS_N_INSNS (41), /* int_div_si */
824 COSTS_N_INSNS (41), /* int_div_di */
826 4 /* memory_latency */
829 COSTS_N_INSNS (8), /* fp_add */
830 COSTS_N_INSNS (8), /* fp_mult_sf */
831 COSTS_N_INSNS (10), /* fp_mult_df */
832 COSTS_N_INSNS (34), /* fp_div_sf */
833 COSTS_N_INSNS (64), /* fp_div_df */
834 COSTS_N_INSNS (5), /* int_mult_si */
835 COSTS_N_INSNS (5), /* int_mult_di */
836 COSTS_N_INSNS (41), /* int_div_si */
837 COSTS_N_INSNS (41), /* int_div_di */
839 4 /* memory_latency */
842 COSTS_N_INSNS (4), /* fp_add */
843 COSTS_N_INSNS (4), /* fp_mult_sf */
844 COSTS_N_INSNS (5), /* fp_mult_df */
845 COSTS_N_INSNS (17), /* fp_div_sf */
846 COSTS_N_INSNS (32), /* fp_div_df */
847 COSTS_N_INSNS (5), /* int_mult_si */
848 COSTS_N_INSNS (5), /* int_mult_di */
849 COSTS_N_INSNS (41), /* int_div_si */
850 COSTS_N_INSNS (41), /* int_div_di */
852 4 /* memory_latency */
855 COSTS_N_INSNS (6), /* fp_add */
856 COSTS_N_INSNS (6), /* fp_mult_sf */
857 COSTS_N_INSNS (7), /* fp_mult_df */
858 COSTS_N_INSNS (25), /* fp_div_sf */
859 COSTS_N_INSNS (48), /* fp_div_df */
860 COSTS_N_INSNS (5), /* int_mult_si */
861 COSTS_N_INSNS (5), /* int_mult_di */
862 COSTS_N_INSNS (41), /* int_div_si */
863 COSTS_N_INSNS (41), /* int_div_di */
865 4 /* memory_latency */
882 COSTS_N_INSNS (5), /* int_mult_si */
883 COSTS_N_INSNS (5), /* int_mult_di */
884 COSTS_N_INSNS (72), /* int_div_si */
885 COSTS_N_INSNS (72), /* int_div_di */
887 4 /* memory_latency */
892 COSTS_N_INSNS (6), /* int_mult_si */
893 COSTS_N_INSNS (6), /* int_mult_di */
894 COSTS_N_INSNS (18), /* int_div_si */
895 COSTS_N_INSNS (35), /* int_div_di */
897 4 /* memory_latency */
900 COSTS_N_INSNS (2), /* fp_add */
901 COSTS_N_INSNS (4), /* fp_mult_sf */
902 COSTS_N_INSNS (5), /* fp_mult_df */
903 COSTS_N_INSNS (12), /* fp_div_sf */
904 COSTS_N_INSNS (19), /* fp_div_df */
905 COSTS_N_INSNS (2), /* int_mult_si */
906 COSTS_N_INSNS (2), /* int_mult_di */
907 COSTS_N_INSNS (35), /* int_div_si */
908 COSTS_N_INSNS (35), /* int_div_di */
910 4 /* memory_latency */
913 COSTS_N_INSNS (3), /* fp_add */
914 COSTS_N_INSNS (5), /* fp_mult_sf */
915 COSTS_N_INSNS (6), /* fp_mult_df */
916 COSTS_N_INSNS (15), /* fp_div_sf */
917 COSTS_N_INSNS (16), /* fp_div_df */
918 COSTS_N_INSNS (17), /* int_mult_si */
919 COSTS_N_INSNS (17), /* int_mult_di */
920 COSTS_N_INSNS (38), /* int_div_si */
921 COSTS_N_INSNS (38), /* int_div_di */
923 6 /* memory_latency */
926 COSTS_N_INSNS (6), /* fp_add */
927 COSTS_N_INSNS (7), /* fp_mult_sf */
928 COSTS_N_INSNS (8), /* fp_mult_df */
929 COSTS_N_INSNS (23), /* fp_div_sf */
930 COSTS_N_INSNS (36), /* fp_div_df */
931 COSTS_N_INSNS (10), /* int_mult_si */
932 COSTS_N_INSNS (10), /* int_mult_di */
933 COSTS_N_INSNS (69), /* int_div_si */
934 COSTS_N_INSNS (69), /* int_div_di */
936 6 /* memory_latency */
948 /* The only costs that appear to be updated here are
949 integer multiplication. */
951 COSTS_N_INSNS (4), /* int_mult_si */
952 COSTS_N_INSNS (6), /* int_mult_di */
953 COSTS_N_INSNS (69), /* int_div_si */
954 COSTS_N_INSNS (69), /* int_div_di */
956 4 /* memory_latency */
971 COSTS_N_INSNS (6), /* fp_add */
972 COSTS_N_INSNS (4), /* fp_mult_sf */
973 COSTS_N_INSNS (5), /* fp_mult_df */
974 COSTS_N_INSNS (23), /* fp_div_sf */
975 COSTS_N_INSNS (36), /* fp_div_df */
976 COSTS_N_INSNS (5), /* int_mult_si */
977 COSTS_N_INSNS (5), /* int_mult_di */
978 COSTS_N_INSNS (36), /* int_div_si */
979 COSTS_N_INSNS (36), /* int_div_di */
981 4 /* memory_latency */
984 COSTS_N_INSNS (6), /* fp_add */
985 COSTS_N_INSNS (5), /* fp_mult_sf */
986 COSTS_N_INSNS (6), /* fp_mult_df */
987 COSTS_N_INSNS (30), /* fp_div_sf */
988 COSTS_N_INSNS (59), /* fp_div_df */
989 COSTS_N_INSNS (3), /* int_mult_si */
990 COSTS_N_INSNS (4), /* int_mult_di */
991 COSTS_N_INSNS (42), /* int_div_si */
992 COSTS_N_INSNS (74), /* int_div_di */
994 4 /* memory_latency */
997 COSTS_N_INSNS (6), /* fp_add */
998 COSTS_N_INSNS (5), /* fp_mult_sf */
999 COSTS_N_INSNS (6), /* fp_mult_df */
1000 COSTS_N_INSNS (30), /* fp_div_sf */
1001 COSTS_N_INSNS (59), /* fp_div_df */
1002 COSTS_N_INSNS (5), /* int_mult_si */
1003 COSTS_N_INSNS (9), /* int_mult_di */
1004 COSTS_N_INSNS (42), /* int_div_si */
1005 COSTS_N_INSNS (74), /* int_div_di */
1006 1, /* branch_cost */
1007 4 /* memory_latency */
1010 /* The only costs that are changed here are
1011 integer multiplication. */
1012 COSTS_N_INSNS (6), /* fp_add */
1013 COSTS_N_INSNS (7), /* fp_mult_sf */
1014 COSTS_N_INSNS (8), /* fp_mult_df */
1015 COSTS_N_INSNS (23), /* fp_div_sf */
1016 COSTS_N_INSNS (36), /* fp_div_df */
1017 COSTS_N_INSNS (5), /* int_mult_si */
1018 COSTS_N_INSNS (9), /* int_mult_di */
1019 COSTS_N_INSNS (69), /* int_div_si */
1020 COSTS_N_INSNS (69), /* int_div_di */
1021 1, /* branch_cost */
1022 4 /* memory_latency */
1028 /* The only costs that are changed here are
1029 integer multiplication. */
1030 COSTS_N_INSNS (6), /* fp_add */
1031 COSTS_N_INSNS (7), /* fp_mult_sf */
1032 COSTS_N_INSNS (8), /* fp_mult_df */
1033 COSTS_N_INSNS (23), /* fp_div_sf */
1034 COSTS_N_INSNS (36), /* fp_div_df */
1035 COSTS_N_INSNS (3), /* int_mult_si */
1036 COSTS_N_INSNS (8), /* int_mult_di */
1037 COSTS_N_INSNS (69), /* int_div_si */
1038 COSTS_N_INSNS (69), /* int_div_di */
1039 1, /* branch_cost */
1040 4 /* memory_latency */
1043 COSTS_N_INSNS (2), /* fp_add */
1044 COSTS_N_INSNS (2), /* fp_mult_sf */
1045 COSTS_N_INSNS (2), /* fp_mult_df */
1046 COSTS_N_INSNS (12), /* fp_div_sf */
1047 COSTS_N_INSNS (19), /* fp_div_df */
1048 COSTS_N_INSNS (5), /* int_mult_si */
1049 COSTS_N_INSNS (9), /* int_mult_di */
1050 COSTS_N_INSNS (34), /* int_div_si */
1051 COSTS_N_INSNS (66), /* int_div_di */
1052 1, /* branch_cost */
1053 4 /* memory_latency */
1056 /* These costs are the same as the SB-1A below. */
1057 COSTS_N_INSNS (4), /* fp_add */
1058 COSTS_N_INSNS (4), /* fp_mult_sf */
1059 COSTS_N_INSNS (4), /* fp_mult_df */
1060 COSTS_N_INSNS (24), /* fp_div_sf */
1061 COSTS_N_INSNS (32), /* fp_div_df */
1062 COSTS_N_INSNS (3), /* int_mult_si */
1063 COSTS_N_INSNS (4), /* int_mult_di */
1064 COSTS_N_INSNS (36), /* int_div_si */
1065 COSTS_N_INSNS (68), /* int_div_di */
1066 1, /* branch_cost */
1067 4 /* memory_latency */
1070 /* These costs are the same as the SB-1 above. */
1071 COSTS_N_INSNS (4), /* fp_add */
1072 COSTS_N_INSNS (4), /* fp_mult_sf */
1073 COSTS_N_INSNS (4), /* fp_mult_df */
1074 COSTS_N_INSNS (24), /* fp_div_sf */
1075 COSTS_N_INSNS (32), /* fp_div_df */
1076 COSTS_N_INSNS (3), /* int_mult_si */
1077 COSTS_N_INSNS (4), /* int_mult_di */
1078 COSTS_N_INSNS (36), /* int_div_si */
1079 COSTS_N_INSNS (68), /* int_div_di */
1080 1, /* branch_cost */
1081 4 /* memory_latency */
1088 COSTS_N_INSNS (8), /* int_mult_si */
1089 COSTS_N_INSNS (8), /* int_mult_di */
1090 COSTS_N_INSNS (72), /* int_div_si */
1091 COSTS_N_INSNS (72), /* int_div_di */
1092 1, /* branch_cost */
1093 4 /* memory_latency */
1096 /* These costs are the same as 5KF above. */
1097 COSTS_N_INSNS (4), /* fp_add */
1098 COSTS_N_INSNS (4), /* fp_mult_sf */
1099 COSTS_N_INSNS (5), /* fp_mult_df */
1100 COSTS_N_INSNS (17), /* fp_div_sf */
1101 COSTS_N_INSNS (32), /* fp_div_df */
1102 COSTS_N_INSNS (4), /* int_mult_si */
1103 COSTS_N_INSNS (11), /* int_mult_di */
1104 COSTS_N_INSNS (36), /* int_div_si */
1105 COSTS_N_INSNS (68), /* int_div_di */
1106 1, /* branch_cost */
1107 4 /* memory_latency */
1111 static rtx mips_find_pic_call_symbol (rtx, rtx, bool);
1112 static int mips_register_move_cost (enum machine_mode, reg_class_t,
1114 static unsigned int mips_function_arg_boundary (enum machine_mode, const_tree);
1116 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1117 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1118 struct GTY (()) mflip_mips16_entry {
1122 static GTY ((param_is (struct mflip_mips16_entry))) htab_t mflip_mips16_htab;
1124 /* Hash table callbacks for mflip_mips16_htab. */
1127 mflip_mips16_htab_hash (const void *entry)
1129 return htab_hash_string (((const struct mflip_mips16_entry *) entry)->name);
1133 mflip_mips16_htab_eq (const void *entry, const void *name)
1135 return strcmp (((const struct mflip_mips16_entry *) entry)->name,
1136 (const char *) name) == 0;
1139 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1140 mode, false if it should next add an attribute for the opposite mode. */
1141 static GTY(()) bool mips16_flipper;
1143 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1144 for -mflip-mips16. Return true if it should use "mips16" and false if
1145 it should use "nomips16". */
1148 mflip_mips16_use_mips16_p (tree decl)
1150 struct mflip_mips16_entry *entry;
1155 /* Use the opposite of the command-line setting for anonymous decls. */
1156 if (!DECL_NAME (decl))
1157 return !mips_base_mips16;
1159 if (!mflip_mips16_htab)
1160 mflip_mips16_htab = htab_create_ggc (37, mflip_mips16_htab_hash,
1161 mflip_mips16_htab_eq, NULL);
1163 name = IDENTIFIER_POINTER (DECL_NAME (decl));
1164 hash = htab_hash_string (name);
1165 slot = htab_find_slot_with_hash (mflip_mips16_htab, name, hash, INSERT);
1166 entry = (struct mflip_mips16_entry *) *slot;
1169 mips16_flipper = !mips16_flipper;
1170 entry = ggc_alloc_mflip_mips16_entry ();
1172 entry->mips16_p = mips16_flipper ? !mips_base_mips16 : mips_base_mips16;
1175 return entry->mips16_p;
1178 /* Predicates to test for presence of "near" and "far"/"long_call"
1179 attributes on the given TYPE. */
1182 mips_near_type_p (const_tree type)
1184 return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL;
1188 mips_far_type_p (const_tree type)
1190 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL
1191 || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL);
1194 /* Similar predicates for "mips16"/"nomips16" function attributes. */
1197 mips_mips16_decl_p (const_tree decl)
1199 return lookup_attribute ("mips16", DECL_ATTRIBUTES (decl)) != NULL;
1203 mips_nomips16_decl_p (const_tree decl)
1205 return lookup_attribute ("nomips16", DECL_ATTRIBUTES (decl)) != NULL;
1208 /* Check if the interrupt attribute is set for a function. */
1211 mips_interrupt_type_p (tree type)
1213 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type)) != NULL;
1216 /* Check if the attribute to use shadow register set is set for a function. */
1219 mips_use_shadow_register_set_p (tree type)
1221 return lookup_attribute ("use_shadow_register_set",
1222 TYPE_ATTRIBUTES (type)) != NULL;
1225 /* Check if the attribute to keep interrupts masked is set for a function. */
1228 mips_keep_interrupts_masked_p (tree type)
1230 return lookup_attribute ("keep_interrupts_masked",
1231 TYPE_ATTRIBUTES (type)) != NULL;
1234 /* Check if the attribute to use debug exception return is set for
1238 mips_use_debug_exception_return_p (tree type)
1240 return lookup_attribute ("use_debug_exception_return",
1241 TYPE_ATTRIBUTES (type)) != NULL;
1244 /* Return true if function DECL is a MIPS16 function. Return the ambient
1245 setting if DECL is null. */
1248 mips_use_mips16_mode_p (tree decl)
1252 /* Nested functions must use the same frame pointer as their
1253 parent and must therefore use the same ISA mode. */
1254 tree parent = decl_function_context (decl);
1257 if (mips_mips16_decl_p (decl))
1259 if (mips_nomips16_decl_p (decl))
1262 return mips_base_mips16;
1265 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1268 mips_comp_type_attributes (const_tree type1, const_tree type2)
1270 /* Disallow mixed near/far attributes. */
1271 if (mips_far_type_p (type1) && mips_near_type_p (type2))
1273 if (mips_near_type_p (type1) && mips_far_type_p (type2))
1278 /* Implement TARGET_INSERT_ATTRIBUTES. */
1281 mips_insert_attributes (tree decl, tree *attributes)
1284 bool mips16_p, nomips16_p;
1286 /* Check for "mips16" and "nomips16" attributes. */
1287 mips16_p = lookup_attribute ("mips16", *attributes) != NULL;
1288 nomips16_p = lookup_attribute ("nomips16", *attributes) != NULL;
1289 if (TREE_CODE (decl) != FUNCTION_DECL)
1292 error ("%qs attribute only applies to functions", "mips16");
1294 error ("%qs attribute only applies to functions", "nomips16");
1298 mips16_p |= mips_mips16_decl_p (decl);
1299 nomips16_p |= mips_nomips16_decl_p (decl);
1300 if (mips16_p || nomips16_p)
1302 /* DECL cannot be simultaneously "mips16" and "nomips16". */
1303 if (mips16_p && nomips16_p)
1304 error ("%qE cannot have both %<mips16%> and "
1305 "%<nomips16%> attributes",
1308 else if (TARGET_FLIP_MIPS16 && !DECL_ARTIFICIAL (decl))
1310 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1311 "mips16" attribute, arbitrarily pick one. We must pick the same
1312 setting for duplicate declarations of a function. */
1313 name = mflip_mips16_use_mips16_p (decl) ? "mips16" : "nomips16";
1314 *attributes = tree_cons (get_identifier (name), NULL, *attributes);
1319 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1322 mips_merge_decl_attributes (tree olddecl, tree newdecl)
1324 /* The decls' "mips16" and "nomips16" attributes must match exactly. */
1325 if (mips_mips16_decl_p (olddecl) != mips_mips16_decl_p (newdecl))
1326 error ("%qE redeclared with conflicting %qs attributes",
1327 DECL_NAME (newdecl), "mips16");
1328 if (mips_nomips16_decl_p (olddecl) != mips_nomips16_decl_p (newdecl))
1329 error ("%qE redeclared with conflicting %qs attributes",
1330 DECL_NAME (newdecl), "nomips16");
1332 return merge_attributes (DECL_ATTRIBUTES (olddecl),
1333 DECL_ATTRIBUTES (newdecl));
1336 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1337 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1340 mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr)
1342 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
1344 *base_ptr = XEXP (x, 0);
1345 *offset_ptr = INTVAL (XEXP (x, 1));
1354 static unsigned int mips_build_integer (struct mips_integer_op *,
1355 unsigned HOST_WIDE_INT);
1357 /* A subroutine of mips_build_integer, with the same interface.
1358 Assume that the final action in the sequence should be a left shift. */
1361 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1363 unsigned int i, shift;
1365 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1366 since signed numbers are easier to load than unsigned ones. */
1368 while ((value & 1) == 0)
1369 value /= 2, shift++;
1371 i = mips_build_integer (codes, value);
1372 codes[i].code = ASHIFT;
1373 codes[i].value = shift;
1377 /* As for mips_build_shift, but assume that the final action will be
1378 an IOR or PLUS operation. */
1381 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1383 unsigned HOST_WIDE_INT high;
1386 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1387 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
1389 /* The constant is too complex to load with a simple LUI/ORI pair,
1390 so we want to give the recursive call as many trailing zeros as
1391 possible. In this case, we know bit 16 is set and that the
1392 low 16 bits form a negative number. If we subtract that number
1393 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1394 i = mips_build_integer (codes, CONST_HIGH_PART (value));
1395 codes[i].code = PLUS;
1396 codes[i].value = CONST_LOW_PART (value);
1400 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1401 bits gives a value with at least 17 trailing zeros. */
1402 i = mips_build_integer (codes, high);
1403 codes[i].code = IOR;
1404 codes[i].value = value & 0xffff;
1409 /* Fill CODES with a sequence of rtl operations to load VALUE.
1410 Return the number of operations needed. */
1413 mips_build_integer (struct mips_integer_op *codes,
1414 unsigned HOST_WIDE_INT value)
1416 if (SMALL_OPERAND (value)
1417 || SMALL_OPERAND_UNSIGNED (value)
1418 || LUI_OPERAND (value))
1420 /* The value can be loaded with a single instruction. */
1421 codes[0].code = UNKNOWN;
1422 codes[0].value = value;
1425 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
1427 /* Either the constant is a simple LUI/ORI combination or its
1428 lowest bit is set. We don't want to shift in this case. */
1429 return mips_build_lower (codes, value);
1431 else if ((value & 0xffff) == 0)
1433 /* The constant will need at least three actions. The lowest
1434 16 bits are clear, so the final action will be a shift. */
1435 return mips_build_shift (codes, value);
1439 /* The final action could be a shift, add or inclusive OR.
1440 Rather than use a complex condition to select the best
1441 approach, try both mips_build_shift and mips_build_lower
1442 and pick the one that gives the shortest sequence.
1443 Note that this case is only used once per constant. */
1444 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1445 unsigned int cost, alt_cost;
1447 cost = mips_build_shift (codes, value);
1448 alt_cost = mips_build_lower (alt_codes, value);
1449 if (alt_cost < cost)
1451 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
1458 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
1461 mips_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
1463 return mips_const_insns (x) > 0;
1466 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
1469 mips16_stub_function (const char *name)
1473 x = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
1474 SYMBOL_REF_FLAGS (x) |= (SYMBOL_FLAG_EXTERNAL | SYMBOL_FLAG_FUNCTION);
1478 /* Return true if symbols of type TYPE require a GOT access. */
1481 mips_got_symbol_type_p (enum mips_symbol_type type)
1485 case SYMBOL_GOT_PAGE_OFST:
1486 case SYMBOL_GOT_DISP:
1494 /* Return true if X is a thread-local symbol. */
1497 mips_tls_symbol_p (rtx x)
1499 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1502 /* Return true if SYMBOL_REF X is associated with a global symbol
1503 (in the STB_GLOBAL sense). */
1506 mips_global_symbol_p (const_rtx x)
1508 const_tree decl = SYMBOL_REF_DECL (x);
1511 return !SYMBOL_REF_LOCAL_P (x) || SYMBOL_REF_EXTERNAL_P (x);
1513 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1514 or weak symbols. Relocations in the object file will be against
1515 the target symbol, so it's that symbol's binding that matters here. */
1516 return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl));
1519 /* Return true if function X is a libgcc MIPS16 stub function. */
1522 mips16_stub_function_p (const_rtx x)
1524 return (GET_CODE (x) == SYMBOL_REF
1525 && strncmp (XSTR (x, 0), "__mips16_", 9) == 0);
1528 /* Return true if function X is a locally-defined and locally-binding
1532 mips16_local_function_p (const_rtx x)
1534 return (GET_CODE (x) == SYMBOL_REF
1535 && SYMBOL_REF_LOCAL_P (x)
1536 && !SYMBOL_REF_EXTERNAL_P (x)
1537 && mips_use_mips16_mode_p (SYMBOL_REF_DECL (x)));
1540 /* Return true if SYMBOL_REF X binds locally. */
1543 mips_symbol_binds_local_p (const_rtx x)
1545 return (SYMBOL_REF_DECL (x)
1546 ? targetm.binds_local_p (SYMBOL_REF_DECL (x))
1547 : SYMBOL_REF_LOCAL_P (x));
1550 /* Return true if rtx constants of mode MODE should be put into a small
1554 mips_rtx_constant_in_small_data_p (enum machine_mode mode)
1556 return (!TARGET_EMBEDDED_DATA
1557 && TARGET_LOCAL_SDATA
1558 && GET_MODE_SIZE (mode) <= mips_small_data_threshold);
1561 /* Return true if X should not be moved directly into register $25.
1562 We need this because many versions of GAS will treat "la $25,foo" as
1563 part of a call sequence and so allow a global "foo" to be lazily bound. */
1566 mips_dangerous_for_la25_p (rtx x)
1568 return (!TARGET_EXPLICIT_RELOCS
1570 && GET_CODE (x) == SYMBOL_REF
1571 && mips_global_symbol_p (x));
1574 /* Return true if calls to X might need $25 to be valid on entry. */
1577 mips_use_pic_fn_addr_reg_p (const_rtx x)
1579 if (!TARGET_USE_PIC_FN_ADDR_REG)
1582 /* MIPS16 stub functions are guaranteed not to use $25. */
1583 if (mips16_stub_function_p (x))
1586 if (GET_CODE (x) == SYMBOL_REF)
1588 /* If PLTs and copy relocations are available, the static linker
1589 will make sure that $25 is valid on entry to the target function. */
1590 if (TARGET_ABICALLS_PIC0)
1593 /* Locally-defined functions use absolute accesses to set up
1594 the global pointer. */
1595 if (TARGET_ABSOLUTE_ABICALLS
1596 && mips_symbol_binds_local_p (x)
1597 && !SYMBOL_REF_EXTERNAL_P (x))
1604 /* Return the method that should be used to access SYMBOL_REF or
1605 LABEL_REF X in context CONTEXT. */
1607 static enum mips_symbol_type
1608 mips_classify_symbol (const_rtx x, enum mips_symbol_context context)
1611 return SYMBOL_GOT_DISP;
1613 if (GET_CODE (x) == LABEL_REF)
1615 /* Only return SYMBOL_PC_RELATIVE if we are generating MIPS16
1616 code and if we know that the label is in the current function's
1617 text section. LABEL_REFs are used for jump tables as well as
1618 text labels, so we must check whether jump tables live in the
1620 if (TARGET_MIPS16_SHORT_JUMP_TABLES
1621 && !LABEL_REF_NONLOCAL_P (x))
1622 return SYMBOL_PC_RELATIVE;
1624 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1625 return SYMBOL_GOT_PAGE_OFST;
1627 return SYMBOL_ABSOLUTE;
1630 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1632 if (SYMBOL_REF_TLS_MODEL (x))
1635 if (CONSTANT_POOL_ADDRESS_P (x))
1637 if (TARGET_MIPS16_TEXT_LOADS)
1638 return SYMBOL_PC_RELATIVE;
1640 if (TARGET_MIPS16_PCREL_LOADS && context == SYMBOL_CONTEXT_MEM)
1641 return SYMBOL_PC_RELATIVE;
1643 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x)))
1644 return SYMBOL_GP_RELATIVE;
1647 /* Do not use small-data accesses for weak symbols; they may end up
1649 if (TARGET_GPOPT && SYMBOL_REF_SMALL_P (x) && !SYMBOL_REF_WEAK (x))
1650 return SYMBOL_GP_RELATIVE;
1652 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1654 if (TARGET_ABICALLS_PIC2
1655 && !(TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x)))
1657 /* There are three cases to consider:
1659 - o32 PIC (either with or without explicit relocs)
1660 - n32/n64 PIC without explicit relocs
1661 - n32/n64 PIC with explicit relocs
1663 In the first case, both local and global accesses will use an
1664 R_MIPS_GOT16 relocation. We must correctly predict which of
1665 the two semantics (local or global) the assembler and linker
1666 will apply. The choice depends on the symbol's binding rather
1667 than its visibility.
1669 In the second case, the assembler will not use R_MIPS_GOT16
1670 relocations, but it chooses between local and global accesses
1671 in the same way as for o32 PIC.
1673 In the third case we have more freedom since both forms of
1674 access will work for any kind of symbol. However, there seems
1675 little point in doing things differently. */
1676 if (mips_global_symbol_p (x))
1677 return SYMBOL_GOT_DISP;
1679 return SYMBOL_GOT_PAGE_OFST;
1682 return SYMBOL_ABSOLUTE;
1685 /* Classify the base of symbolic expression X, given that X appears in
1688 static enum mips_symbol_type
1689 mips_classify_symbolic_expression (rtx x, enum mips_symbol_context context)
1693 split_const (x, &x, &offset);
1694 if (UNSPEC_ADDRESS_P (x))
1695 return UNSPEC_ADDRESS_TYPE (x);
1697 return mips_classify_symbol (x, context);
1700 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1701 is the alignment in bytes of SYMBOL_REF X. */
1704 mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset)
1706 HOST_WIDE_INT align;
1708 align = SYMBOL_REF_DECL (x) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x)) : 1;
1709 return IN_RANGE (offset, 0, align - 1);
1712 /* Return true if X is a symbolic constant that can be used in context
1713 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1716 mips_symbolic_constant_p (rtx x, enum mips_symbol_context context,
1717 enum mips_symbol_type *symbol_type)
1721 split_const (x, &x, &offset);
1722 if (UNSPEC_ADDRESS_P (x))
1724 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1725 x = UNSPEC_ADDRESS (x);
1727 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1729 *symbol_type = mips_classify_symbol (x, context);
1730 if (*symbol_type == SYMBOL_TLS)
1736 if (offset == const0_rtx)
1739 /* Check whether a nonzero offset is valid for the underlying
1741 switch (*symbol_type)
1743 case SYMBOL_ABSOLUTE:
1744 case SYMBOL_64_HIGH:
1747 /* If the target has 64-bit pointers and the object file only
1748 supports 32-bit symbols, the values of those symbols will be
1749 sign-extended. In this case we can't allow an arbitrary offset
1750 in case the 32-bit value X + OFFSET has a different sign from X. */
1751 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1752 return offset_within_block_p (x, INTVAL (offset));
1754 /* In other cases the relocations can handle any offset. */
1757 case SYMBOL_PC_RELATIVE:
1758 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1759 In this case, we no longer have access to the underlying constant,
1760 but the original symbol-based access was known to be valid. */
1761 if (GET_CODE (x) == LABEL_REF)
1766 case SYMBOL_GP_RELATIVE:
1767 /* Make sure that the offset refers to something within the
1768 same object block. This should guarantee that the final
1769 PC- or GP-relative offset is within the 16-bit limit. */
1770 return offset_within_block_p (x, INTVAL (offset));
1772 case SYMBOL_GOT_PAGE_OFST:
1773 case SYMBOL_GOTOFF_PAGE:
1774 /* If the symbol is global, the GOT entry will contain the symbol's
1775 address, and we will apply a 16-bit offset after loading it.
1776 If the symbol is local, the linker should provide enough local
1777 GOT entries for a 16-bit offset, but larger offsets may lead
1779 return SMALL_INT (offset);
1783 /* There is no carry between the HI and LO REL relocations, so the
1784 offset is only valid if we know it won't lead to such a carry. */
1785 return mips_offset_within_alignment_p (x, INTVAL (offset));
1787 case SYMBOL_GOT_DISP:
1788 case SYMBOL_GOTOFF_DISP:
1789 case SYMBOL_GOTOFF_CALL:
1790 case SYMBOL_GOTOFF_LOADGP:
1793 case SYMBOL_GOTTPREL:
1801 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
1802 single instruction. We rely on the fact that, in the worst case,
1803 all instructions involved in a MIPS16 address calculation are usually
1807 mips_symbol_insns_1 (enum mips_symbol_type type, enum machine_mode mode)
1809 if (mips_use_pcrel_pool_p[(int) type])
1811 if (mode == MAX_MACHINE_MODE)
1812 /* LEAs will be converted into constant-pool references by
1814 type = SYMBOL_PC_RELATIVE;
1816 /* The constant must be loaded and then dereferenced. */
1822 case SYMBOL_ABSOLUTE:
1823 /* When using 64-bit symbols, we need 5 preparatory instructions,
1826 lui $at,%highest(symbol)
1827 daddiu $at,$at,%higher(symbol)
1829 daddiu $at,$at,%hi(symbol)
1832 The final address is then $at + %lo(symbol). With 32-bit
1833 symbols we just need a preparatory LUI for normal mode and
1834 a preparatory LI and SLL for MIPS16. */
1835 return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2;
1837 case SYMBOL_GP_RELATIVE:
1838 /* Treat GP-relative accesses as taking a single instruction on
1839 MIPS16 too; the copy of $gp can often be shared. */
1842 case SYMBOL_PC_RELATIVE:
1843 /* PC-relative constants can be only be used with ADDIUPC,
1844 DADDIUPC, LWPC and LDPC. */
1845 if (mode == MAX_MACHINE_MODE
1846 || GET_MODE_SIZE (mode) == 4
1847 || GET_MODE_SIZE (mode) == 8)
1850 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
1853 case SYMBOL_GOT_DISP:
1854 /* The constant will have to be loaded from the GOT before it
1855 is used in an address. */
1856 if (mode != MAX_MACHINE_MODE)
1861 case SYMBOL_GOT_PAGE_OFST:
1862 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
1863 local/global classification is accurate. The worst cases are:
1865 (1) For local symbols when generating o32 or o64 code. The assembler
1871 ...and the final address will be $at + %lo(symbol).
1873 (2) For global symbols when -mxgot. The assembler will use:
1875 lui $at,%got_hi(symbol)
1878 ...and the final address will be $at + %got_lo(symbol). */
1881 case SYMBOL_GOTOFF_PAGE:
1882 case SYMBOL_GOTOFF_DISP:
1883 case SYMBOL_GOTOFF_CALL:
1884 case SYMBOL_GOTOFF_LOADGP:
1885 case SYMBOL_64_HIGH:
1891 case SYMBOL_GOTTPREL:
1894 /* A 16-bit constant formed by a single relocation, or a 32-bit
1895 constant formed from a high 16-bit relocation and a low 16-bit
1896 relocation. Use mips_split_p to determine which. 32-bit
1897 constants need an "lui; addiu" sequence for normal mode and
1898 an "li; sll; addiu" sequence for MIPS16 mode. */
1899 return !mips_split_p[type] ? 1 : TARGET_MIPS16 ? 3 : 2;
1902 /* We don't treat a bare TLS symbol as a constant. */
1908 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
1909 to load symbols of type TYPE into a register. Return 0 if the given
1910 type of symbol cannot be used as an immediate operand.
1912 Otherwise, return the number of instructions needed to load or store
1913 values of mode MODE to or from addresses of type TYPE. Return 0 if
1914 the given type of symbol is not valid in addresses.
1916 In both cases, treat extended MIPS16 instructions as two instructions. */
1919 mips_symbol_insns (enum mips_symbol_type type, enum machine_mode mode)
1921 return mips_symbol_insns_1 (type, mode) * (TARGET_MIPS16 ? 2 : 1);
1924 /* A for_each_rtx callback. Stop the search if *X references a
1925 thread-local symbol. */
1928 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1930 return mips_tls_symbol_p (*x);
1933 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1936 mips_cannot_force_const_mem (enum machine_mode mode, rtx x)
1938 enum mips_symbol_type type;
1941 /* There is no assembler syntax for expressing an address-sized
1943 if (GET_CODE (x) == HIGH)
1946 /* As an optimization, reject constants that mips_legitimize_move
1949 Suppose we have a multi-instruction sequence that loads constant C
1950 into register R. If R does not get allocated a hard register, and
1951 R is used in an operand that allows both registers and memory
1952 references, reload will consider forcing C into memory and using
1953 one of the instruction's memory alternatives. Returning false
1954 here will force it to use an input reload instead. */
1955 if (CONST_INT_P (x) && mips_legitimate_constant_p (mode, x))
1958 split_const (x, &base, &offset);
1959 if (mips_symbolic_constant_p (base, SYMBOL_CONTEXT_LEA, &type))
1961 /* See whether we explicitly want these symbols in the pool. */
1962 if (mips_use_pcrel_pool_p[(int) type])
1965 /* The same optimization as for CONST_INT. */
1966 if (SMALL_INT (offset) && mips_symbol_insns (type, MAX_MACHINE_MODE) > 0)
1969 /* If MIPS16 constant pools live in the text section, they should
1970 not refer to anything that might need run-time relocation. */
1971 if (TARGET_MIPS16_PCREL_LOADS && mips_got_symbol_type_p (type))
1975 /* TLS symbols must be computed by mips_legitimize_move. */
1976 if (for_each_rtx (&x, &mips_tls_symbol_ref_1, NULL))
1982 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
1983 constants when we're using a per-function constant pool. */
1986 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
1987 const_rtx x ATTRIBUTE_UNUSED)
1989 return !TARGET_MIPS16_PCREL_LOADS;
1992 /* Return true if register REGNO is a valid base register for mode MODE.
1993 STRICT_P is true if REG_OK_STRICT is in effect. */
1996 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode,
1999 if (!HARD_REGISTER_NUM_P (regno))
2003 regno = reg_renumber[regno];
2006 /* These fake registers will be eliminated to either the stack or
2007 hard frame pointer, both of which are usually valid base registers.
2008 Reload deals with the cases where the eliminated form isn't valid. */
2009 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
2012 /* In MIPS16 mode, the stack pointer can only address word and doubleword
2013 values, nothing smaller. There are two problems here:
2015 (a) Instantiating virtual registers can introduce new uses of the
2016 stack pointer. If these virtual registers are valid addresses,
2017 the stack pointer should be too.
2019 (b) Most uses of the stack pointer are not made explicit until
2020 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
2021 We don't know until that stage whether we'll be eliminating to the
2022 stack pointer (which needs the restriction) or the hard frame
2023 pointer (which doesn't).
2025 All in all, it seems more consistent to only enforce this restriction
2026 during and after reload. */
2027 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
2028 return !strict_p || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
2030 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
2033 /* Return true if X is a valid base register for mode MODE.
2034 STRICT_P is true if REG_OK_STRICT is in effect. */
2037 mips_valid_base_register_p (rtx x, enum machine_mode mode, bool strict_p)
2039 if (!strict_p && GET_CODE (x) == SUBREG)
2043 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p));
2046 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2047 can address a value of mode MODE. */
2050 mips_valid_offset_p (rtx x, enum machine_mode mode)
2052 /* Check that X is a signed 16-bit number. */
2053 if (!const_arith_operand (x, Pmode))
2056 /* We may need to split multiword moves, so make sure that every word
2058 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2059 && !SMALL_OPERAND (INTVAL (x) + GET_MODE_SIZE (mode) - UNITS_PER_WORD))
2065 /* Return true if a LO_SUM can address a value of mode MODE when the
2066 LO_SUM symbol has type SYMBOL_TYPE. */
2069 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type, enum machine_mode mode)
2071 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2073 if (mips_symbol_insns (symbol_type, mode) == 0)
2076 /* Check that there is a known low-part relocation. */
2077 if (mips_lo_relocs[symbol_type] == NULL)
2080 /* We may need to split multiword moves, so make sure that each word
2081 can be accessed without inducing a carry. This is mainly needed
2082 for o64, which has historically only guaranteed 64-bit alignment
2083 for 128-bit types. */
2084 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2085 && GET_MODE_BITSIZE (mode) > GET_MODE_ALIGNMENT (mode))
2091 /* Return true if X is a valid address for machine mode MODE. If it is,
2092 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2096 mips_classify_address (struct mips_address_info *info, rtx x,
2097 enum machine_mode mode, bool strict_p)
2099 switch (GET_CODE (x))
2103 info->type = ADDRESS_REG;
2105 info->offset = const0_rtx;
2106 return mips_valid_base_register_p (info->reg, mode, strict_p);
2109 info->type = ADDRESS_REG;
2110 info->reg = XEXP (x, 0);
2111 info->offset = XEXP (x, 1);
2112 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2113 && mips_valid_offset_p (info->offset, mode));
2116 info->type = ADDRESS_LO_SUM;
2117 info->reg = XEXP (x, 0);
2118 info->offset = XEXP (x, 1);
2119 /* We have to trust the creator of the LO_SUM to do something vaguely
2120 sane. Target-independent code that creates a LO_SUM should also
2121 create and verify the matching HIGH. Target-independent code that
2122 adds an offset to a LO_SUM must prove that the offset will not
2123 induce a carry. Failure to do either of these things would be
2124 a bug, and we are not required to check for it here. The MIPS
2125 backend itself should only create LO_SUMs for valid symbolic
2126 constants, with the high part being either a HIGH or a copy
2129 = mips_classify_symbolic_expression (info->offset, SYMBOL_CONTEXT_MEM);
2130 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2131 && mips_valid_lo_sum_p (info->symbol_type, mode));
2134 /* Small-integer addresses don't occur very often, but they
2135 are legitimate if $0 is a valid base register. */
2136 info->type = ADDRESS_CONST_INT;
2137 return !TARGET_MIPS16 && SMALL_INT (x);
2142 info->type = ADDRESS_SYMBOLIC;
2143 return (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_MEM,
2145 && mips_symbol_insns (info->symbol_type, mode) > 0
2146 && !mips_split_p[info->symbol_type]);
2153 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2156 mips_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
2158 struct mips_address_info addr;
2160 return mips_classify_address (&addr, x, mode, strict_p);
2163 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
2166 mips_stack_address_p (rtx x, enum machine_mode mode)
2168 struct mips_address_info addr;
2170 return (mips_classify_address (&addr, x, mode, false)
2171 && addr.type == ADDRESS_REG
2172 && addr.reg == stack_pointer_rtx);
2175 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2176 address instruction. Note that such addresses are not considered
2177 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2178 is so restricted. */
2181 mips_lwxs_address_p (rtx addr)
2184 && GET_CODE (addr) == PLUS
2185 && REG_P (XEXP (addr, 1)))
2187 rtx offset = XEXP (addr, 0);
2188 if (GET_CODE (offset) == MULT
2189 && REG_P (XEXP (offset, 0))
2190 && CONST_INT_P (XEXP (offset, 1))
2191 && INTVAL (XEXP (offset, 1)) == 4)
2197 /* Return true if ADDR matches the pattern for the L{B,H,W,D}{,U}X load
2198 indexed address instruction. Note that such addresses are
2199 not considered legitimate in the TARGET_LEGITIMATE_ADDRESS_P
2200 sense, because their use is so restricted. */
2203 mips_lx_address_p (rtx addr, enum machine_mode mode)
2205 if (GET_CODE (addr) != PLUS
2206 || !REG_P (XEXP (addr, 0))
2207 || !REG_P (XEXP (addr, 1)))
2209 if (ISA_HAS_LBX && mode == QImode)
2211 if (ISA_HAS_LHX && mode == HImode)
2213 if (ISA_HAS_LWX && mode == SImode)
2215 if (ISA_HAS_LDX && mode == DImode)
2220 /* Return true if a value at OFFSET bytes from base register BASE can be
2221 accessed using an unextended MIPS16 instruction. MODE is the mode of
2224 Usually the offset in an unextended instruction is a 5-bit field.
2225 The offset is unsigned and shifted left once for LH and SH, twice
2226 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2227 an 8-bit immediate field that's shifted left twice. */
2230 mips16_unextended_reference_p (enum machine_mode mode, rtx base,
2231 unsigned HOST_WIDE_INT offset)
2233 if (mode != BLKmode && offset % GET_MODE_SIZE (mode) == 0)
2235 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
2236 return offset < 256U * GET_MODE_SIZE (mode);
2237 return offset < 32U * GET_MODE_SIZE (mode);
2242 /* Return the number of instructions needed to load or store a value
2243 of mode MODE at address X. Return 0 if X isn't valid for MODE.
2244 Assume that multiword moves may need to be split into word moves
2245 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2248 For MIPS16 code, count extended instructions as two instructions. */
2251 mips_address_insns (rtx x, enum machine_mode mode, bool might_split_p)
2253 struct mips_address_info addr;
2256 /* BLKmode is used for single unaligned loads and stores and should
2257 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2258 meaningless, so we have to single it out as a special case one way
2260 if (mode != BLKmode && might_split_p)
2261 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2265 if (mips_classify_address (&addr, x, mode, false))
2270 && !mips16_unextended_reference_p (mode, addr.reg,
2271 UINTVAL (addr.offset)))
2275 case ADDRESS_LO_SUM:
2276 return TARGET_MIPS16 ? factor * 2 : factor;
2278 case ADDRESS_CONST_INT:
2281 case ADDRESS_SYMBOLIC:
2282 return factor * mips_symbol_insns (addr.symbol_type, mode);
2287 /* Return the number of instructions needed to load constant X.
2288 Return 0 if X isn't a valid constant. */
2291 mips_const_insns (rtx x)
2293 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2294 enum mips_symbol_type symbol_type;
2297 switch (GET_CODE (x))
2300 if (!mips_symbolic_constant_p (XEXP (x, 0), SYMBOL_CONTEXT_LEA,
2302 || !mips_split_p[symbol_type])
2305 /* This is simply an LUI for normal mode. It is an extended
2306 LI followed by an extended SLL for MIPS16. */
2307 return TARGET_MIPS16 ? 4 : 1;
2311 /* Unsigned 8-bit constants can be loaded using an unextended
2312 LI instruction. Unsigned 16-bit constants can be loaded
2313 using an extended LI. Negative constants must be loaded
2314 using LI and then negated. */
2315 return (IN_RANGE (INTVAL (x), 0, 255) ? 1
2316 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
2317 : IN_RANGE (-INTVAL (x), 0, 255) ? 2
2318 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
2321 return mips_build_integer (codes, INTVAL (x));
2325 /* Allow zeros for normal mode, where we can use $0. */
2326 return !TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0;
2332 /* See if we can refer to X directly. */
2333 if (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_LEA, &symbol_type))
2334 return mips_symbol_insns (symbol_type, MAX_MACHINE_MODE);
2336 /* Otherwise try splitting the constant into a base and offset.
2337 If the offset is a 16-bit value, we can load the base address
2338 into a register and then use (D)ADDIU to add in the offset.
2339 If the offset is larger, we can load the base and offset
2340 into separate registers and add them together with (D)ADDU.
2341 However, the latter is only possible before reload; during
2342 and after reload, we must have the option of forcing the
2343 constant into the pool instead. */
2344 split_const (x, &x, &offset);
2347 int n = mips_const_insns (x);
2350 if (SMALL_INT (offset))
2352 else if (!targetm.cannot_force_const_mem (GET_MODE (x), x))
2353 return n + 1 + mips_build_integer (codes, INTVAL (offset));
2360 return mips_symbol_insns (mips_classify_symbol (x, SYMBOL_CONTEXT_LEA),
2368 /* X is a doubleword constant that can be handled by splitting it into
2369 two words and loading each word separately. Return the number of
2370 instructions required to do this. */
2373 mips_split_const_insns (rtx x)
2375 unsigned int low, high;
2377 low = mips_const_insns (mips_subword (x, false));
2378 high = mips_const_insns (mips_subword (x, true));
2379 gcc_assert (low > 0 && high > 0);
2383 /* Return the number of instructions needed to implement INSN,
2384 given that it loads from or stores to MEM. Count extended
2385 MIPS16 instructions as two instructions. */
2388 mips_load_store_insns (rtx mem, rtx insn)
2390 enum machine_mode mode;
2394 gcc_assert (MEM_P (mem));
2395 mode = GET_MODE (mem);
2397 /* Try to prove that INSN does not need to be split. */
2398 might_split_p = true;
2399 if (GET_MODE_BITSIZE (mode) == 64)
2401 set = single_set (insn);
2402 if (set && !mips_split_64bit_move_p (SET_DEST (set), SET_SRC (set)))
2403 might_split_p = false;
2406 return mips_address_insns (XEXP (mem, 0), mode, might_split_p);
2409 /* Return the number of instructions needed for an integer division. */
2412 mips_idiv_insns (void)
2417 if (TARGET_CHECK_ZERO_DIV)
2419 if (GENERATE_DIVIDE_TRAPS)
2425 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
2430 /* Emit a move from SRC to DEST. Assume that the move expanders can
2431 handle all moves if !can_create_pseudo_p (). The distinction is
2432 important because, unlike emit_move_insn, the move expanders know
2433 how to force Pmode objects into the constant pool even when the
2434 constant pool address is not itself legitimate. */
2437 mips_emit_move (rtx dest, rtx src)
2439 return (can_create_pseudo_p ()
2440 ? emit_move_insn (dest, src)
2441 : emit_move_insn_1 (dest, src));
2444 /* Emit an instruction of the form (set TARGET (CODE OP0)). */
2447 mips_emit_unary (enum rtx_code code, rtx target, rtx op0)
2449 emit_insn (gen_rtx_SET (VOIDmode, target,
2450 gen_rtx_fmt_e (code, GET_MODE (op0), op0)));
2453 /* Compute (CODE OP0) and store the result in a new register of mode MODE.
2454 Return that new register. */
2457 mips_force_unary (enum machine_mode mode, enum rtx_code code, rtx op0)
2461 reg = gen_reg_rtx (mode);
2462 mips_emit_unary (code, reg, op0);
2466 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2469 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
2471 emit_insn (gen_rtx_SET (VOIDmode, target,
2472 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
2475 /* Compute (CODE OP0 OP1) and store the result in a new register
2476 of mode MODE. Return that new register. */
2479 mips_force_binary (enum machine_mode mode, enum rtx_code code, rtx op0, rtx op1)
2483 reg = gen_reg_rtx (mode);
2484 mips_emit_binary (code, reg, op0, op1);
2488 /* Copy VALUE to a register and return that register. If new pseudos
2489 are allowed, copy it into a new register, otherwise use DEST. */
2492 mips_force_temporary (rtx dest, rtx value)
2494 if (can_create_pseudo_p ())
2495 return force_reg (Pmode, value);
2498 mips_emit_move (dest, value);
2503 /* Emit a call sequence with call pattern PATTERN and return the call
2504 instruction itself (which is not necessarily the last instruction
2505 emitted). ORIG_ADDR is the original, unlegitimized address,
2506 ADDR is the legitimized form, and LAZY_P is true if the call
2507 address is lazily-bound. */
2510 mips_emit_call_insn (rtx pattern, rtx orig_addr, rtx addr, bool lazy_p)
2514 insn = emit_call_insn (pattern);
2516 if (TARGET_MIPS16 && mips_use_pic_fn_addr_reg_p (orig_addr))
2518 /* MIPS16 JALRs only take MIPS16 registers. If the target
2519 function requires $25 to be valid on entry, we must copy it
2520 there separately. The move instruction can be put in the
2521 call's delay slot. */
2522 reg = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
2523 emit_insn_before (gen_move_insn (reg, addr), insn);
2524 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
2528 /* Lazy-binding stubs require $gp to be valid on entry. */
2529 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
2533 /* See the comment above load_call<mode> for details. */
2534 use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
2535 gen_rtx_REG (Pmode, GOT_VERSION_REGNUM));
2536 emit_insn (gen_update_got_version ());
2541 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2542 then add CONST_INT OFFSET to the result. */
2545 mips_unspec_address_offset (rtx base, rtx offset,
2546 enum mips_symbol_type symbol_type)
2548 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
2549 UNSPEC_ADDRESS_FIRST + symbol_type);
2550 if (offset != const0_rtx)
2551 base = gen_rtx_PLUS (Pmode, base, offset);
2552 return gen_rtx_CONST (Pmode, base);
2555 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2556 type SYMBOL_TYPE. */
2559 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
2563 split_const (address, &base, &offset);
2564 return mips_unspec_address_offset (base, offset, symbol_type);
2567 /* If OP is an UNSPEC address, return the address to which it refers,
2568 otherwise return OP itself. */
2571 mips_strip_unspec_address (rtx op)
2575 split_const (op, &base, &offset);
2576 if (UNSPEC_ADDRESS_P (base))
2577 op = plus_constant (Pmode, UNSPEC_ADDRESS (base), INTVAL (offset));
2581 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2582 high part to BASE and return the result. Just return BASE otherwise.
2583 TEMP is as for mips_force_temporary.
2585 The returned expression can be used as the first operand to a LO_SUM. */
2588 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
2589 enum mips_symbol_type symbol_type)
2591 if (mips_split_p[symbol_type])
2593 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
2594 addr = mips_force_temporary (temp, addr);
2595 base = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
2600 /* Return an instruction that copies $gp into register REG. We want
2601 GCC to treat the register's value as constant, so that its value
2602 can be rematerialized on demand. */
2605 gen_load_const_gp (rtx reg)
2607 return PMODE_INSN (gen_load_const_gp, (reg));
2610 /* Return a pseudo register that contains the value of $gp throughout
2611 the current function. Such registers are needed by MIPS16 functions,
2612 for which $gp itself is not a valid base register or addition operand. */
2615 mips16_gp_pseudo_reg (void)
2617 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
2621 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
2623 push_topmost_sequence ();
2625 scan = get_insns ();
2626 while (NEXT_INSN (scan) && !INSN_P (NEXT_INSN (scan)))
2627 scan = NEXT_INSN (scan);
2629 insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
2630 insn = emit_insn_after (insn, scan);
2631 INSN_LOCATOR (insn) = 0;
2633 pop_topmost_sequence ();
2636 return cfun->machine->mips16_gp_pseudo_rtx;
2639 /* Return a base register that holds pic_offset_table_rtx.
2640 TEMP, if nonnull, is a scratch Pmode base register. */
2643 mips_pic_base_register (rtx temp)
2646 return pic_offset_table_rtx;
2648 if (currently_expanding_to_rtl)
2649 return mips16_gp_pseudo_reg ();
2651 if (can_create_pseudo_p ())
2652 temp = gen_reg_rtx (Pmode);
2655 /* The first post-reload split exposes all references to $gp
2656 (both uses and definitions). All references must remain
2657 explicit after that point.
2659 It is safe to introduce uses of $gp at any time, so for
2660 simplicity, we do that before the split too. */
2661 mips_emit_move (temp, pic_offset_table_rtx);
2663 emit_insn (gen_load_const_gp (temp));
2667 /* Return the RHS of a load_call<mode> insn. */
2670 mips_unspec_call (rtx reg, rtx symbol)
2674 vec = gen_rtvec (3, reg, symbol, gen_rtx_REG (SImode, GOT_VERSION_REGNUM));
2675 return gen_rtx_UNSPEC (Pmode, vec, UNSPEC_LOAD_CALL);
2678 /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol
2679 reference. Return NULL_RTX otherwise. */
2682 mips_strip_unspec_call (rtx src)
2684 if (GET_CODE (src) == UNSPEC && XINT (src, 1) == UNSPEC_LOAD_CALL)
2685 return mips_strip_unspec_address (XVECEXP (src, 0, 1));
2689 /* Create and return a GOT reference of type TYPE for address ADDR.
2690 TEMP, if nonnull, is a scratch Pmode base register. */
2693 mips_got_load (rtx temp, rtx addr, enum mips_symbol_type type)
2695 rtx base, high, lo_sum_symbol;
2697 base = mips_pic_base_register (temp);
2699 /* If we used the temporary register to load $gp, we can't use
2700 it for the high part as well. */
2701 if (temp != NULL && reg_overlap_mentioned_p (base, temp))
2704 high = mips_unspec_offset_high (temp, base, addr, type);
2705 lo_sum_symbol = mips_unspec_address (addr, type);
2707 if (type == SYMBOL_GOTOFF_CALL)
2708 return mips_unspec_call (high, lo_sum_symbol);
2710 return PMODE_INSN (gen_unspec_got, (high, lo_sum_symbol));
2713 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2714 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2715 constant in that context and can be split into high and low parts.
2716 If so, and if LOW_OUT is nonnull, emit the high part and store the
2717 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
2719 TEMP is as for mips_force_temporary and is used to load the high
2720 part into a register.
2722 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
2723 a legitimize SET_SRC for an .md pattern, otherwise the low part
2724 is guaranteed to be a legitimate address for mode MODE. */
2727 mips_split_symbol (rtx temp, rtx addr, enum machine_mode mode, rtx *low_out)
2729 enum mips_symbol_context context;
2730 enum mips_symbol_type symbol_type;
2733 context = (mode == MAX_MACHINE_MODE
2734 ? SYMBOL_CONTEXT_LEA
2735 : SYMBOL_CONTEXT_MEM);
2736 if (GET_CODE (addr) == HIGH && context == SYMBOL_CONTEXT_LEA)
2738 addr = XEXP (addr, 0);
2739 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2740 && mips_symbol_insns (symbol_type, mode) > 0
2741 && mips_split_hi_p[symbol_type])
2744 switch (symbol_type)
2746 case SYMBOL_GOT_PAGE_OFST:
2747 /* The high part of a page/ofst pair is loaded from the GOT. */
2748 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_PAGE);
2759 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2760 && mips_symbol_insns (symbol_type, mode) > 0
2761 && mips_split_p[symbol_type])
2764 switch (symbol_type)
2766 case SYMBOL_GOT_DISP:
2767 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
2768 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_DISP);
2771 case SYMBOL_GP_RELATIVE:
2772 high = mips_pic_base_register (temp);
2773 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2777 high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
2778 high = mips_force_temporary (temp, high);
2779 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2788 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2789 mips_force_temporary; it is only needed when OFFSET is not a
2793 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
2795 if (!SMALL_OPERAND (offset))
2801 /* Load the full offset into a register so that we can use
2802 an unextended instruction for the address itself. */
2803 high = GEN_INT (offset);
2808 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
2809 The addition inside the macro CONST_HIGH_PART may cause an
2810 overflow, so we need to force a sign-extension check. */
2811 high = gen_int_mode (CONST_HIGH_PART (offset), Pmode);
2812 offset = CONST_LOW_PART (offset);
2814 high = mips_force_temporary (temp, high);
2815 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
2817 return plus_constant (Pmode, reg, offset);
2820 /* The __tls_get_attr symbol. */
2821 static GTY(()) rtx mips_tls_symbol;
2823 /* Return an instruction sequence that calls __tls_get_addr. SYM is
2824 the TLS symbol we are referencing and TYPE is the symbol type to use
2825 (either global dynamic or local dynamic). V0 is an RTX for the
2826 return value location. */
2829 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
2833 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
2835 if (!mips_tls_symbol)
2836 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
2838 loc = mips_unspec_address (sym, type);
2842 emit_insn (gen_rtx_SET (Pmode, a0,
2843 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
2844 insn = mips_expand_call (MIPS_CALL_NORMAL, v0, mips_tls_symbol,
2845 const0_rtx, NULL_RTX, false);
2846 RTL_CONST_CALL_P (insn) = 1;
2847 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
2848 insn = get_insns ();
2855 /* Return a pseudo register that contains the current thread pointer. */
2862 tp = gen_reg_rtx (Pmode);
2865 mips_need_mips16_rdhwr_p = true;
2866 fn = mips16_stub_function ("__mips16_rdhwr");
2867 SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_LOCAL;
2868 if (!call_insn_operand (fn, VOIDmode))
2869 fn = force_reg (Pmode, fn);
2870 emit_insn (PMODE_INSN (gen_tls_get_tp_mips16, (tp, fn)));
2873 emit_insn (PMODE_INSN (gen_tls_get_tp, (tp)));
2877 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
2878 its address. The return value will be both a valid address and a valid
2879 SET_SRC (either a REG or a LO_SUM). */
2882 mips_legitimize_tls_address (rtx loc)
2884 rtx dest, insn, v0, tp, tmp1, tmp2, eqv, offset;
2885 enum tls_model model;
2887 model = SYMBOL_REF_TLS_MODEL (loc);
2888 /* Only TARGET_ABICALLS code can have more than one module; other
2889 code must be be static and should not use a GOT. All TLS models
2890 reduce to local exec in this situation. */
2891 if (!TARGET_ABICALLS)
2892 model = TLS_MODEL_LOCAL_EXEC;
2896 case TLS_MODEL_GLOBAL_DYNAMIC:
2897 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2898 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
2899 dest = gen_reg_rtx (Pmode);
2900 emit_libcall_block (insn, dest, v0, loc);
2903 case TLS_MODEL_LOCAL_DYNAMIC:
2904 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2905 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
2906 tmp1 = gen_reg_rtx (Pmode);
2908 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2909 share the LDM result with other LD model accesses. */
2910 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2912 emit_libcall_block (insn, tmp1, v0, eqv);
2914 offset = mips_unspec_address (loc, SYMBOL_DTPREL);
2915 if (mips_split_p[SYMBOL_DTPREL])
2917 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
2918 dest = gen_rtx_LO_SUM (Pmode, tmp2, offset);
2921 dest = expand_binop (Pmode, add_optab, tmp1, offset,
2922 0, 0, OPTAB_DIRECT);
2925 case TLS_MODEL_INITIAL_EXEC:
2926 tp = mips_get_tp ();
2927 tmp1 = gen_reg_rtx (Pmode);
2928 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
2929 if (Pmode == DImode)
2930 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
2932 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
2933 dest = gen_reg_rtx (Pmode);
2934 emit_insn (gen_add3_insn (dest, tmp1, tp));
2937 case TLS_MODEL_LOCAL_EXEC:
2938 tmp1 = mips_get_tp ();
2939 offset = mips_unspec_address (loc, SYMBOL_TPREL);
2940 if (mips_split_p[SYMBOL_TPREL])
2942 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_TPREL);
2943 dest = gen_rtx_LO_SUM (Pmode, tmp2, offset);
2946 dest = expand_binop (Pmode, add_optab, tmp1, offset,
2947 0, 0, OPTAB_DIRECT);
2956 /* If X is not a valid address for mode MODE, force it into a register. */
2959 mips_force_address (rtx x, enum machine_mode mode)
2961 if (!mips_legitimate_address_p (mode, x, false))
2962 x = force_reg (Pmode, x);
2966 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
2967 be legitimized in a way that the generic machinery might not expect,
2968 return a new address, otherwise return NULL. MODE is the mode of
2969 the memory being accessed. */
2972 mips_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
2973 enum machine_mode mode)
2976 HOST_WIDE_INT offset;
2978 if (mips_tls_symbol_p (x))
2979 return mips_legitimize_tls_address (x);
2981 /* See if the address can split into a high part and a LO_SUM. */
2982 if (mips_split_symbol (NULL, x, mode, &addr))
2983 return mips_force_address (addr, mode);
2985 /* Handle BASE + OFFSET using mips_add_offset. */
2986 mips_split_plus (x, &base, &offset);
2989 if (!mips_valid_base_register_p (base, mode, false))
2990 base = copy_to_mode_reg (Pmode, base);
2991 addr = mips_add_offset (NULL, base, offset);
2992 return mips_force_address (addr, mode);
2998 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
3001 mips_move_integer (rtx temp, rtx dest, unsigned HOST_WIDE_INT value)
3003 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
3004 enum machine_mode mode;
3005 unsigned int i, num_ops;
3008 mode = GET_MODE (dest);
3009 num_ops = mips_build_integer (codes, value);
3011 /* Apply each binary operation to X. Invariant: X is a legitimate
3012 source operand for a SET pattern. */
3013 x = GEN_INT (codes[0].value);
3014 for (i = 1; i < num_ops; i++)
3016 if (!can_create_pseudo_p ())
3018 emit_insn (gen_rtx_SET (VOIDmode, temp, x));
3022 x = force_reg (mode, x);
3023 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
3026 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
3029 /* Subroutine of mips_legitimize_move. Move constant SRC into register
3030 DEST given that SRC satisfies immediate_operand but doesn't satisfy
3034 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
3038 /* Split moves of big integers into smaller pieces. */
3039 if (splittable_const_int_operand (src, mode))
3041 mips_move_integer (dest, dest, INTVAL (src));
3045 /* Split moves of symbolic constants into high/low pairs. */
3046 if (mips_split_symbol (dest, src, MAX_MACHINE_MODE, &src))
3048 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
3052 /* Generate the appropriate access sequences for TLS symbols. */
3053 if (mips_tls_symbol_p (src))
3055 mips_emit_move (dest, mips_legitimize_tls_address (src));
3059 /* If we have (const (plus symbol offset)), and that expression cannot
3060 be forced into memory, load the symbol first and add in the offset.
3061 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
3062 forced into memory, as it usually produces better code. */
3063 split_const (src, &base, &offset);
3064 if (offset != const0_rtx
3065 && (targetm.cannot_force_const_mem (mode, src)
3066 || (!TARGET_MIPS16 && can_create_pseudo_p ())))
3068 base = mips_force_temporary (dest, base);
3069 mips_emit_move (dest, mips_add_offset (NULL, base, INTVAL (offset)));
3073 src = force_const_mem (mode, src);
3075 /* When using explicit relocs, constant pool references are sometimes
3076 not legitimate addresses. */
3077 mips_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0));
3078 mips_emit_move (dest, src);
3081 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
3082 sequence that is valid. */
3085 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
3087 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
3089 mips_emit_move (dest, force_reg (mode, src));
3093 /* We need to deal with constants that would be legitimate
3094 immediate_operands but aren't legitimate move_operands. */
3095 if (CONSTANT_P (src) && !move_operand (src, mode))
3097 mips_legitimize_const_move (mode, dest, src);
3098 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
3104 /* Return true if value X in context CONTEXT is a small-data address
3105 that can be rewritten as a LO_SUM. */
3108 mips_rewrite_small_data_p (rtx x, enum mips_symbol_context context)
3110 enum mips_symbol_type symbol_type;
3112 return (mips_lo_relocs[SYMBOL_GP_RELATIVE]
3113 && !mips_split_p[SYMBOL_GP_RELATIVE]
3114 && mips_symbolic_constant_p (x, context, &symbol_type)
3115 && symbol_type == SYMBOL_GP_RELATIVE);
3118 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
3119 containing MEM, or null if none. */
3122 mips_small_data_pattern_1 (rtx *loc, void *data)
3124 enum mips_symbol_context context;
3126 /* Ignore things like "g" constraints in asms. We make no particular
3127 guarantee about which symbolic constants are acceptable as asm operands
3128 versus which must be forced into a GPR. */
3129 if (GET_CODE (*loc) == LO_SUM || GET_CODE (*loc) == ASM_OPERANDS)
3134 if (for_each_rtx (&XEXP (*loc, 0), mips_small_data_pattern_1, *loc))
3139 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3140 return mips_rewrite_small_data_p (*loc, context);
3143 /* Return true if OP refers to small data symbols directly, not through
3147 mips_small_data_pattern_p (rtx op)
3149 return for_each_rtx (&op, mips_small_data_pattern_1, NULL);
3152 /* A for_each_rtx callback, used by mips_rewrite_small_data.
3153 DATA is the containing MEM, or null if none. */
3156 mips_rewrite_small_data_1 (rtx *loc, void *data)
3158 enum mips_symbol_context context;
3162 for_each_rtx (&XEXP (*loc, 0), mips_rewrite_small_data_1, *loc);
3166 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3167 if (mips_rewrite_small_data_p (*loc, context))
3168 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
3170 if (GET_CODE (*loc) == LO_SUM)
3176 /* Rewrite instruction pattern PATTERN so that it refers to small data
3177 using explicit relocations. */
3180 mips_rewrite_small_data (rtx pattern)
3182 pattern = copy_insn (pattern);
3183 for_each_rtx (&pattern, mips_rewrite_small_data_1, NULL);
3187 /* We need a lot of little routines to check the range of MIPS16 immediate
3191 m16_check_op (rtx op, int low, int high, int mask)
3193 return (CONST_INT_P (op)
3194 && IN_RANGE (INTVAL (op), low, high)
3195 && (INTVAL (op) & mask) == 0);
3199 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3201 return m16_check_op (op, 0x1, 0x8, 0);
3205 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3207 return m16_check_op (op, -0x8, 0x7, 0);
3211 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3213 return m16_check_op (op, -0x7, 0x8, 0);
3217 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3219 return m16_check_op (op, -0x10, 0xf, 0);
3223 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3225 return m16_check_op (op, -0xf, 0x10, 0);
3229 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3231 return m16_check_op (op, -0x10 << 2, 0xf << 2, 3);
3235 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3237 return m16_check_op (op, -0xf << 2, 0x10 << 2, 3);
3241 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3243 return m16_check_op (op, -0x80, 0x7f, 0);
3247 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3249 return m16_check_op (op, -0x7f, 0x80, 0);
3253 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3255 return m16_check_op (op, 0x0, 0xff, 0);
3259 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3261 return m16_check_op (op, -0xff, 0x0, 0);
3265 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3267 return m16_check_op (op, -0x1, 0xfe, 0);
3271 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3273 return m16_check_op (op, 0x0, 0xff << 2, 3);
3277 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3279 return m16_check_op (op, -0xff << 2, 0x0, 3);
3283 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3285 return m16_check_op (op, -0x80 << 3, 0x7f << 3, 7);
3289 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3291 return m16_check_op (op, -0x7f << 3, 0x80 << 3, 7);
3294 /* The cost of loading values from the constant pool. It should be
3295 larger than the cost of any constant we want to synthesize inline. */
3296 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3298 /* Return the cost of X when used as an operand to the MIPS16 instruction
3299 that implements CODE. Return -1 if there is no such instruction, or if
3300 X is not a valid immediate operand for it. */
3303 mips16_constant_cost (int code, HOST_WIDE_INT x)
3310 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3311 other shifts are extended. The shift patterns truncate the shift
3312 count to the right size, so there are no out-of-range values. */
3313 if (IN_RANGE (x, 1, 8))
3315 return COSTS_N_INSNS (1);
3318 if (IN_RANGE (x, -128, 127))
3320 if (SMALL_OPERAND (x))
3321 return COSTS_N_INSNS (1);
3325 /* Like LE, but reject the always-true case. */
3329 /* We add 1 to the immediate and use SLT. */
3332 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3335 if (IN_RANGE (x, 0, 255))
3337 if (SMALL_OPERAND_UNSIGNED (x))
3338 return COSTS_N_INSNS (1);
3343 /* Equality comparisons with 0 are cheap. */
3353 /* Return true if there is a non-MIPS16 instruction that implements CODE
3354 and if that instruction accepts X as an immediate operand. */
3357 mips_immediate_operand_p (int code, HOST_WIDE_INT x)
3364 /* All shift counts are truncated to a valid constant. */
3369 /* Likewise rotates, if the target supports rotates at all. */
3375 /* These instructions take 16-bit unsigned immediates. */
3376 return SMALL_OPERAND_UNSIGNED (x);
3381 /* These instructions take 16-bit signed immediates. */
3382 return SMALL_OPERAND (x);
3388 /* The "immediate" forms of these instructions are really
3389 implemented as comparisons with register 0. */
3394 /* Likewise, meaning that the only valid immediate operand is 1. */
3398 /* We add 1 to the immediate and use SLT. */
3399 return SMALL_OPERAND (x + 1);
3402 /* Likewise SLTU, but reject the always-true case. */
3403 return SMALL_OPERAND (x + 1) && x + 1 != 0;
3407 /* The bit position and size are immediate operands. */
3408 return ISA_HAS_EXT_INS;
3411 /* By default assume that $0 can be used for 0. */
3416 /* Return the cost of binary operation X, given that the instruction
3417 sequence for a word-sized or smaller operation has cost SINGLE_COST
3418 and that the sequence of a double-word operation has cost DOUBLE_COST.
3419 If SPEED is true, optimize for speed otherwise optimize for size. */
3422 mips_binary_cost (rtx x, int single_cost, int double_cost, bool speed)
3426 if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2)
3431 + set_src_cost (XEXP (x, 0), speed)
3432 + rtx_cost (XEXP (x, 1), GET_CODE (x), 1, speed));
3435 /* Return the cost of floating-point multiplications of mode MODE. */
3438 mips_fp_mult_cost (enum machine_mode mode)
3440 return mode == DFmode ? mips_cost->fp_mult_df : mips_cost->fp_mult_sf;
3443 /* Return the cost of floating-point divisions of mode MODE. */
3446 mips_fp_div_cost (enum machine_mode mode)
3448 return mode == DFmode ? mips_cost->fp_div_df : mips_cost->fp_div_sf;
3451 /* Return the cost of sign-extending OP to mode MODE, not including the
3452 cost of OP itself. */
3455 mips_sign_extend_cost (enum machine_mode mode, rtx op)
3458 /* Extended loads are as cheap as unextended ones. */
3461 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3462 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3465 if (ISA_HAS_SEB_SEH || GENERATE_MIPS16E)
3466 /* We can use SEB or SEH. */
3467 return COSTS_N_INSNS (1);
3469 /* We need to use a shift left and a shift right. */
3470 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3473 /* Return the cost of zero-extending OP to mode MODE, not including the
3474 cost of OP itself. */
3477 mips_zero_extend_cost (enum machine_mode mode, rtx op)
3480 /* Extended loads are as cheap as unextended ones. */
3483 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3484 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3485 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3487 if (GENERATE_MIPS16E)
3488 /* We can use ZEB or ZEH. */
3489 return COSTS_N_INSNS (1);
3492 /* We need to load 0xff or 0xffff into a register and use AND. */
3493 return COSTS_N_INSNS (GET_MODE (op) == QImode ? 2 : 3);
3495 /* We can use ANDI. */
3496 return COSTS_N_INSNS (1);
3499 /* Return the cost of moving between two registers of mode MODE,
3500 assuming that the move will be in pieces of at most UNITS bytes. */
3503 mips_set_reg_reg_piece_cost (enum machine_mode mode, unsigned int units)
3505 return COSTS_N_INSNS ((GET_MODE_SIZE (mode) + units - 1) / units);
3508 /* Return the cost of moving between two registers of mode MODE. */
3511 mips_set_reg_reg_cost (enum machine_mode mode)
3513 switch (GET_MODE_CLASS (mode))
3516 return mips_set_reg_reg_piece_cost (mode, GET_MODE_SIZE (CCmode));
3519 case MODE_COMPLEX_FLOAT:
3520 case MODE_VECTOR_FLOAT:
3521 if (TARGET_HARD_FLOAT)
3522 return mips_set_reg_reg_piece_cost (mode, UNITS_PER_HWFPVALUE);
3526 return mips_set_reg_reg_piece_cost (mode, UNITS_PER_WORD);
3530 /* Implement TARGET_RTX_COSTS. */
3533 mips_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
3534 int *total, bool speed)
3536 enum machine_mode mode = GET_MODE (x);
3537 bool float_mode_p = FLOAT_MODE_P (mode);
3541 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3542 appear in the instruction stream, and the cost of a comparison is
3543 really the cost of the branch or scc condition. At the time of
3544 writing, GCC only uses an explicit outer COMPARE code when optabs
3545 is testing whether a constant is expensive enough to force into a
3546 register. We want optabs to pass such constants through the MIPS
3547 expanders instead, so make all constants very cheap here. */
3548 if (outer_code == COMPARE)
3550 gcc_assert (CONSTANT_P (x));
3558 /* Treat *clear_upper32-style ANDs as having zero cost in the
3559 second operand. The cost is entirely in the first operand.
3561 ??? This is needed because we would otherwise try to CSE
3562 the constant operand. Although that's the right thing for
3563 instructions that continue to be a register operation throughout
3564 compilation, it is disastrous for instructions that could
3565 later be converted into a memory operation. */
3567 && outer_code == AND
3568 && UINTVAL (x) == 0xffffffff)
3576 cost = mips16_constant_cost (outer_code, INTVAL (x));
3585 /* When not optimizing for size, we care more about the cost
3586 of hot code, and hot code is often in a loop. If a constant
3587 operand needs to be forced into a register, we will often be
3588 able to hoist the constant load out of the loop, so the load
3589 should not contribute to the cost. */
3590 if (speed || mips_immediate_operand_p (outer_code, INTVAL (x)))
3602 if (force_to_mem_operand (x, VOIDmode))
3604 *total = COSTS_N_INSNS (1);
3607 cost = mips_const_insns (x);
3610 /* If the constant is likely to be stored in a GPR, SETs of
3611 single-insn constants are as cheap as register sets; we
3612 never want to CSE them.
3614 Don't reduce the cost of storing a floating-point zero in
3615 FPRs. If we have a zero in an FPR for other reasons, we
3616 can get better cfg-cleanup and delayed-branch results by
3617 using it consistently, rather than using $0 sometimes and
3618 an FPR at other times. Also, moves between floating-point
3619 registers are sometimes cheaper than (D)MTC1 $0. */
3621 && outer_code == SET
3622 && !(float_mode_p && TARGET_HARD_FLOAT))
3624 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3625 want to CSE the constant itself. It is usually better to
3626 have N copies of the last operation in the sequence and one
3627 shared copy of the other operations. (Note that this is
3628 not true for MIPS16 code, where the final operation in the
3629 sequence is often an extended instruction.)
3631 Also, if we have a CONST_INT, we don't know whether it is
3632 for a word or doubleword operation, so we cannot rely on
3633 the result of mips_build_integer. */
3634 else if (!TARGET_MIPS16
3635 && (outer_code == SET || mode == VOIDmode))
3637 *total = COSTS_N_INSNS (cost);
3640 /* The value will need to be fetched from the constant pool. */
3641 *total = CONSTANT_POOL_COST;
3645 /* If the address is legitimate, return the number of
3646 instructions it needs. */
3648 cost = mips_address_insns (addr, mode, true);
3651 *total = COSTS_N_INSNS (cost + 1);
3654 /* Check for a scaled indexed address. */
3655 if (mips_lwxs_address_p (addr)
3656 || mips_lx_address_p (addr, mode))
3658 *total = COSTS_N_INSNS (2);
3661 /* Otherwise use the default handling. */
3665 *total = COSTS_N_INSNS (6);
3669 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1);
3673 /* Check for a *clear_upper32 pattern and treat it like a zero
3674 extension. See the pattern's comment for details. */
3677 && CONST_INT_P (XEXP (x, 1))
3678 && UINTVAL (XEXP (x, 1)) == 0xffffffff)
3680 *total = (mips_zero_extend_cost (mode, XEXP (x, 0))
3681 + set_src_cost (XEXP (x, 0), speed));
3684 if (ISA_HAS_CINS && CONST_INT_P (XEXP (x, 1)))
3686 rtx op = XEXP (x, 0);
3687 if (GET_CODE (op) == ASHIFT
3688 && CONST_INT_P (XEXP (op, 1))
3689 && mask_low_and_shift_p (mode, XEXP (x, 1), XEXP (op, 1), 32))
3691 *total = COSTS_N_INSNS (1) + set_src_cost (XEXP (op, 0), speed);
3700 /* Double-word operations use two single-word operations. */
3701 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (2),
3710 if (CONSTANT_P (XEXP (x, 1)))
3711 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3714 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (12),
3720 *total = mips_cost->fp_add;
3722 *total = COSTS_N_INSNS (4);
3726 /* Low-part immediates need an extended MIPS16 instruction. */
3727 *total = (COSTS_N_INSNS (TARGET_MIPS16 ? 2 : 1)
3728 + set_src_cost (XEXP (x, 0), speed));
3743 /* Branch comparisons have VOIDmode, so use the first operand's
3745 mode = GET_MODE (XEXP (x, 0));
3746 if (FLOAT_MODE_P (mode))
3748 *total = mips_cost->fp_add;
3751 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3757 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3758 && TARGET_FUSED_MADD
3759 && !HONOR_NANS (mode)
3760 && !HONOR_SIGNED_ZEROS (mode))
3762 /* See if we can use NMADD or NMSUB. See mips.md for the
3763 associated patterns. */
3764 rtx op0 = XEXP (x, 0);
3765 rtx op1 = XEXP (x, 1);
3766 if (GET_CODE (op0) == MULT && GET_CODE (XEXP (op0, 0)) == NEG)
3768 *total = (mips_fp_mult_cost (mode)
3769 + set_src_cost (XEXP (XEXP (op0, 0), 0), speed)
3770 + set_src_cost (XEXP (op0, 1), speed)
3771 + set_src_cost (op1, speed));
3774 if (GET_CODE (op1) == MULT)
3776 *total = (mips_fp_mult_cost (mode)
3777 + set_src_cost (op0, speed)
3778 + set_src_cost (XEXP (op1, 0), speed)
3779 + set_src_cost (XEXP (op1, 1), speed));
3788 /* If this is part of a MADD or MSUB, treat the PLUS as
3791 && TARGET_FUSED_MADD
3792 && GET_CODE (XEXP (x, 0)) == MULT)
3795 *total = mips_cost->fp_add;
3799 /* Double-word operations require three single-word operations and
3800 an SLTU. The MIPS16 version then needs to move the result of
3801 the SLTU from $24 to a MIPS16 register. */
3802 *total = mips_binary_cost (x, COSTS_N_INSNS (1),
3803 COSTS_N_INSNS (TARGET_MIPS16 ? 5 : 4),
3809 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3810 && TARGET_FUSED_MADD
3811 && !HONOR_NANS (mode)
3812 && HONOR_SIGNED_ZEROS (mode))
3814 /* See if we can use NMADD or NMSUB. See mips.md for the
3815 associated patterns. */
3816 rtx op = XEXP (x, 0);
3817 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
3818 && GET_CODE (XEXP (op, 0)) == MULT)
3820 *total = (mips_fp_mult_cost (mode)
3821 + set_src_cost (XEXP (XEXP (op, 0), 0), speed)
3822 + set_src_cost (XEXP (XEXP (op, 0), 1), speed)
3823 + set_src_cost (XEXP (op, 1), speed));
3829 *total = mips_cost->fp_add;
3831 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1);
3836 *total = mips_fp_mult_cost (mode);
3837 else if (mode == DImode && !TARGET_64BIT)
3838 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
3839 where the mulsidi3 always includes an MFHI and an MFLO. */
3841 ? mips_cost->int_mult_si * 3 + 6
3842 : COSTS_N_INSNS (ISA_HAS_MUL3 ? 7 : 9));
3844 *total = COSTS_N_INSNS (ISA_HAS_MUL3 ? 1 : 2);
3845 else if (mode == DImode)
3846 *total = mips_cost->int_mult_di;
3848 *total = mips_cost->int_mult_si;
3852 /* Check for a reciprocal. */
3855 && flag_unsafe_math_optimizations
3856 && XEXP (x, 0) == CONST1_RTX (mode))
3858 if (outer_code == SQRT || GET_CODE (XEXP (x, 1)) == SQRT)
3859 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
3860 division as being free. */
3861 *total = set_src_cost (XEXP (x, 1), speed);
3863 *total = (mips_fp_div_cost (mode)
3864 + set_src_cost (XEXP (x, 1), speed));
3873 *total = mips_fp_div_cost (mode);
3882 /* It is our responsibility to make division by a power of 2
3883 as cheap as 2 register additions if we want the division
3884 expanders to be used for such operations; see the setting
3885 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
3886 should always produce shorter code than using
3887 expand_sdiv2_pow2. */
3889 && CONST_INT_P (XEXP (x, 1))
3890 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
3892 *total = COSTS_N_INSNS (2) + set_src_cost (XEXP (x, 0), speed);
3895 *total = COSTS_N_INSNS (mips_idiv_insns ());
3897 else if (mode == DImode)
3898 *total = mips_cost->int_div_di;
3900 *total = mips_cost->int_div_si;
3904 *total = mips_sign_extend_cost (mode, XEXP (x, 0));
3908 if (outer_code == SET
3910 && (GET_CODE (XEXP (x, 0)) == TRUNCATE
3911 || GET_CODE (XEXP (x, 0)) == SUBREG)
3912 && GET_MODE (XEXP (x, 0)) == QImode
3913 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
3915 *total = set_src_cost (XEXP (XEXP (x, 0), 0), speed);
3918 *total = mips_zero_extend_cost (mode, XEXP (x, 0));
3922 case UNSIGNED_FLOAT:
3925 case FLOAT_TRUNCATE:
3926 *total = mips_cost->fp_add;
3930 if (register_operand (SET_DEST (x), VOIDmode)
3931 && reg_or_0_operand (SET_SRC (x), VOIDmode))
3933 *total = mips_set_reg_reg_cost (GET_MODE (SET_DEST (x)));
3943 /* Implement TARGET_ADDRESS_COST. */
3946 mips_address_cost (rtx addr, enum machine_mode mode,
3947 addr_space_t as ATTRIBUTE_UNUSED,
3948 bool speed ATTRIBUTE_UNUSED)
3950 return mips_address_insns (addr, mode, false);
3953 /* Information about a single instruction in a multi-instruction
3955 struct mips_multi_member {
3956 /* True if this is a label, false if it is code. */
3959 /* The output_asm_insn format of the instruction. */
3962 /* The operands to the instruction. */
3963 rtx operands[MAX_RECOG_OPERANDS];
3965 typedef struct mips_multi_member mips_multi_member;
3967 /* Vector definitions for the above. */
3968 DEF_VEC_O(mips_multi_member);
3969 DEF_VEC_ALLOC_O(mips_multi_member, heap);
3971 /* The instructions that make up the current multi-insn sequence. */
3972 static VEC (mips_multi_member, heap) *mips_multi_members;
3974 /* How many instructions (as opposed to labels) are in the current
3975 multi-insn sequence. */
3976 static unsigned int mips_multi_num_insns;
3978 /* Start a new multi-insn sequence. */
3981 mips_multi_start (void)
3983 VEC_truncate (mips_multi_member, mips_multi_members, 0);
3984 mips_multi_num_insns = 0;
3987 /* Add a new, uninitialized member to the current multi-insn sequence. */
3989 static struct mips_multi_member *
3990 mips_multi_add (void)
3992 mips_multi_member empty;
3993 return VEC_safe_push (mips_multi_member, heap, mips_multi_members, empty);
3996 /* Add a normal insn with the given asm format to the current multi-insn
3997 sequence. The other arguments are a null-terminated list of operands. */
4000 mips_multi_add_insn (const char *format, ...)
4002 struct mips_multi_member *member;
4007 member = mips_multi_add ();
4008 member->is_label_p = false;
4009 member->format = format;
4010 va_start (ap, format);
4012 while ((op = va_arg (ap, rtx)))
4013 member->operands[i++] = op;
4015 mips_multi_num_insns++;
4018 /* Add the given label definition to the current multi-insn sequence.
4019 The definition should include the colon. */
4022 mips_multi_add_label (const char *label)
4024 struct mips_multi_member *member;
4026 member = mips_multi_add ();
4027 member->is_label_p = true;
4028 member->format = label;
4031 /* Return the index of the last member of the current multi-insn sequence. */
4034 mips_multi_last_index (void)
4036 return VEC_length (mips_multi_member, mips_multi_members) - 1;
4039 /* Add a copy of an existing instruction to the current multi-insn
4040 sequence. I is the index of the instruction that should be copied. */
4043 mips_multi_copy_insn (unsigned int i)
4045 struct mips_multi_member *member;
4047 member = mips_multi_add ();
4048 memcpy (member, &VEC_index (mips_multi_member, mips_multi_members, i),
4050 gcc_assert (!member->is_label_p);
4053 /* Change the operand of an existing instruction in the current
4054 multi-insn sequence. I is the index of the instruction,
4055 OP is the index of the operand, and X is the new value. */
4058 mips_multi_set_operand (unsigned int i, unsigned int op, rtx x)
4060 VEC_index (mips_multi_member, mips_multi_members, i).operands[op] = x;
4063 /* Write out the asm code for the current multi-insn sequence. */
4066 mips_multi_write (void)
4068 struct mips_multi_member *member;
4071 FOR_EACH_VEC_ELT (mips_multi_member, mips_multi_members, i, member)
4072 if (member->is_label_p)
4073 fprintf (asm_out_file, "%s\n", member->format);
4075 output_asm_insn (member->format, member->operands);
4078 /* Return one word of double-word value OP, taking into account the fixed
4079 endianness of certain registers. HIGH_P is true to select the high part,
4080 false to select the low part. */
4083 mips_subword (rtx op, bool high_p)
4085 unsigned int byte, offset;
4086 enum machine_mode mode;
4088 mode = GET_MODE (op);
4089 if (mode == VOIDmode)
4090 mode = TARGET_64BIT ? TImode : DImode;
4092 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
4093 byte = UNITS_PER_WORD;
4097 if (FP_REG_RTX_P (op))
4099 /* Paired FPRs are always ordered little-endian. */
4100 offset = (UNITS_PER_WORD < UNITS_PER_HWFPVALUE ? high_p : byte != 0);
4101 return gen_rtx_REG (word_mode, REGNO (op) + offset);
4105 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
4107 return simplify_gen_subreg (word_mode, op, mode, byte);
4110 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
4113 mips_split_64bit_move_p (rtx dest, rtx src)
4118 /* FPR-to-FPR moves can be done in a single instruction, if they're
4120 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
4123 /* Check for floating-point loads and stores. */
4124 if (ISA_HAS_LDC1_SDC1)
4126 if (FP_REG_RTX_P (dest) && MEM_P (src))
4128 if (FP_REG_RTX_P (src) && MEM_P (dest))
4134 /* Split a doubleword move from SRC to DEST. On 32-bit targets,
4135 this function handles 64-bit moves for which mips_split_64bit_move_p
4136 holds. For 64-bit targets, this function handles 128-bit moves. */
4139 mips_split_doubleword_move (rtx dest, rtx src)
4143 if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src))
4145 if (!TARGET_64BIT && GET_MODE (dest) == DImode)
4146 emit_insn (gen_move_doubleword_fprdi (dest, src));
4147 else if (!TARGET_64BIT && GET_MODE (dest) == DFmode)
4148 emit_insn (gen_move_doubleword_fprdf (dest, src));
4149 else if (!TARGET_64BIT && GET_MODE (dest) == V2SFmode)
4150 emit_insn (gen_move_doubleword_fprv2sf (dest, src));
4151 else if (!TARGET_64BIT && GET_MODE (dest) == V2SImode)
4152 emit_insn (gen_move_doubleword_fprv2si (dest, src));
4153 else if (!TARGET_64BIT && GET_MODE (dest) == V4HImode)
4154 emit_insn (gen_move_doubleword_fprv4hi (dest, src));
4155 else if (!TARGET_64BIT && GET_MODE (dest) == V8QImode)
4156 emit_insn (gen_move_doubleword_fprv8qi (dest, src));
4157 else if (TARGET_64BIT && GET_MODE (dest) == TFmode)
4158 emit_insn (gen_move_doubleword_fprtf (dest, src));
4162 else if (REG_P (dest) && REGNO (dest) == MD_REG_FIRST)
4164 low_dest = mips_subword (dest, false);
4165 mips_emit_move (low_dest, mips_subword (src, false));
4167 emit_insn (gen_mthidi_ti (dest, mips_subword (src, true), low_dest));
4169 emit_insn (gen_mthisi_di (dest, mips_subword (src, true), low_dest));
4171 else if (REG_P (src) && REGNO (src) == MD_REG_FIRST)
4173 mips_emit_move (mips_subword (dest, false), mips_subword (src, false));
4175 emit_insn (gen_mfhidi_ti (mips_subword (dest, true), src));
4177 emit_insn (gen_mfhisi_di (mips_subword (dest, true), src));
4181 /* The operation can be split into two normal moves. Decide in
4182 which order to do them. */
4183 low_dest = mips_subword (dest, false);
4184 if (REG_P (low_dest)
4185 && reg_overlap_mentioned_p (low_dest, src))
4187 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4188 mips_emit_move (low_dest, mips_subword (src, false));
4192 mips_emit_move (low_dest, mips_subword (src, false));
4193 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4198 /* Return the appropriate instructions to move SRC into DEST. Assume
4199 that SRC is operand 1 and DEST is operand 0. */
4202 mips_output_move (rtx dest, rtx src)
4204 enum rtx_code dest_code, src_code;
4205 enum machine_mode mode;
4206 enum mips_symbol_type symbol_type;
4209 dest_code = GET_CODE (dest);
4210 src_code = GET_CODE (src);
4211 mode = GET_MODE (dest);
4212 dbl_p = (GET_MODE_SIZE (mode) == 8);
4214 if (dbl_p && mips_split_64bit_move_p (dest, src))
4217 if ((src_code == REG && GP_REG_P (REGNO (src)))
4218 || (!TARGET_MIPS16 && src == CONST0_RTX (mode)))
4220 if (dest_code == REG)
4222 if (GP_REG_P (REGNO (dest)))
4223 return "move\t%0,%z1";
4225 /* Moves to HI are handled by special .md insns. */
4226 if (REGNO (dest) == LO_REGNUM)
4229 if (DSP_ACC_REG_P (REGNO (dest)))
4231 static char retval[] = "mt__\t%z1,%q0";
4233 retval[2] = reg_names[REGNO (dest)][4];
4234 retval[3] = reg_names[REGNO (dest)][5];
4238 if (FP_REG_P (REGNO (dest)))
4239 return dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
4241 if (ALL_COP_REG_P (REGNO (dest)))
4243 static char retval[] = "dmtc_\t%z1,%0";
4245 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4246 return dbl_p ? retval : retval + 1;
4249 if (dest_code == MEM)
4250 switch (GET_MODE_SIZE (mode))
4252 case 1: return "sb\t%z1,%0";
4253 case 2: return "sh\t%z1,%0";
4254 case 4: return "sw\t%z1,%0";
4255 case 8: return "sd\t%z1,%0";
4258 if (dest_code == REG && GP_REG_P (REGNO (dest)))
4260 if (src_code == REG)
4262 /* Moves from HI are handled by special .md insns. */
4263 if (REGNO (src) == LO_REGNUM)
4265 /* When generating VR4120 or VR4130 code, we use MACC and
4266 DMACC instead of MFLO. This avoids both the normal
4267 MIPS III HI/LO hazards and the errata related to
4270 return dbl_p ? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
4274 if (DSP_ACC_REG_P (REGNO (src)))
4276 static char retval[] = "mf__\t%0,%q1";
4278 retval[2] = reg_names[REGNO (src)][4];
4279 retval[3] = reg_names[REGNO (src)][5];
4283 if (FP_REG_P (REGNO (src)))
4284 return dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
4286 if (ALL_COP_REG_P (REGNO (src)))
4288 static char retval[] = "dmfc_\t%0,%1";
4290 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4291 return dbl_p ? retval : retval + 1;
4295 if (src_code == MEM)
4296 switch (GET_MODE_SIZE (mode))
4298 case 1: return "lbu\t%0,%1";
4299 case 2: return "lhu\t%0,%1";
4300 case 4: return "lw\t%0,%1";
4301 case 8: return "ld\t%0,%1";
4304 if (src_code == CONST_INT)
4306 /* Don't use the X format for the operand itself, because that
4307 will give out-of-range numbers for 64-bit hosts and 32-bit
4310 return "li\t%0,%1\t\t\t# %X1";
4312 if (SMALL_OPERAND_UNSIGNED (INTVAL (src)))
4315 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src)))
4319 if (src_code == HIGH)
4320 return TARGET_MIPS16 ? "#" : "lui\t%0,%h1";
4322 if (CONST_GP_P (src))
4323 return "move\t%0,%1";
4325 if (mips_symbolic_constant_p (src, SYMBOL_CONTEXT_LEA, &symbol_type)
4326 && mips_lo_relocs[symbol_type] != 0)
4328 /* A signed 16-bit constant formed by applying a relocation
4329 operator to a symbolic address. */
4330 gcc_assert (!mips_split_p[symbol_type]);
4331 return "li\t%0,%R1";
4334 if (symbolic_operand (src, VOIDmode))
4336 gcc_assert (TARGET_MIPS16
4337 ? TARGET_MIPS16_TEXT_LOADS
4338 : !TARGET_EXPLICIT_RELOCS);
4339 return dbl_p ? "dla\t%0,%1" : "la\t%0,%1";
4342 if (src_code == REG && FP_REG_P (REGNO (src)))
4344 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4346 if (GET_MODE (dest) == V2SFmode)
4347 return "mov.ps\t%0,%1";
4349 return dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1";
4352 if (dest_code == MEM)
4353 return dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0";
4355 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4357 if (src_code == MEM)
4358 return dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1";
4360 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
4362 static char retval[] = "l_c_\t%0,%1";
4364 retval[1] = (dbl_p ? 'd' : 'w');
4365 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4368 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
4370 static char retval[] = "s_c_\t%1,%0";
4372 retval[1] = (dbl_p ? 'd' : 'w');
4373 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4379 /* Return true if CMP1 is a suitable second operand for integer ordering
4380 test CODE. See also the *sCC patterns in mips.md. */
4383 mips_int_order_operand_ok_p (enum rtx_code code, rtx cmp1)
4389 return reg_or_0_operand (cmp1, VOIDmode);
4393 return !TARGET_MIPS16 && cmp1 == const1_rtx;
4397 return arith_operand (cmp1, VOIDmode);
4400 return sle_operand (cmp1, VOIDmode);
4403 return sleu_operand (cmp1, VOIDmode);
4410 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4411 integer ordering test *CODE, or if an equivalent combination can
4412 be formed by adjusting *CODE and *CMP1. When returning true, update
4413 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4417 mips_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1,
4418 enum machine_mode mode)
4420 HOST_WIDE_INT plus_one;
4422 if (mips_int_order_operand_ok_p (*code, *cmp1))
4425 if (CONST_INT_P (*cmp1))
4429 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4430 if (INTVAL (*cmp1) < plus_one)
4433 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4439 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4443 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4454 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4455 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4456 is nonnull, it's OK to set TARGET to the inverse of the result and
4457 flip *INVERT_PTR instead. */
4460 mips_emit_int_order_test (enum rtx_code code, bool *invert_ptr,
4461 rtx target, rtx cmp0, rtx cmp1)
4463 enum machine_mode mode;
4465 /* First see if there is a MIPS instruction that can do this operation.
4466 If not, try doing the same for the inverse operation. If that also
4467 fails, force CMP1 into a register and try again. */
4468 mode = GET_MODE (cmp0);
4469 if (mips_canonicalize_int_order_test (&code, &cmp1, mode))
4470 mips_emit_binary (code, target, cmp0, cmp1);
4473 enum rtx_code inv_code = reverse_condition (code);
4474 if (!mips_canonicalize_int_order_test (&inv_code, &cmp1, mode))
4476 cmp1 = force_reg (mode, cmp1);
4477 mips_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1);
4479 else if (invert_ptr == 0)
4483 inv_target = mips_force_binary (GET_MODE (target),
4484 inv_code, cmp0, cmp1);
4485 mips_emit_binary (XOR, target, inv_target, const1_rtx);
4489 *invert_ptr = !*invert_ptr;
4490 mips_emit_binary (inv_code, target, cmp0, cmp1);
4495 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4496 The register will have the same mode as CMP0. */
4499 mips_zero_if_equal (rtx cmp0, rtx cmp1)
4501 if (cmp1 == const0_rtx)
4504 if (uns_arith_operand (cmp1, VOIDmode))
4505 return expand_binop (GET_MODE (cmp0), xor_optab,
4506 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4508 return expand_binop (GET_MODE (cmp0), sub_optab,
4509 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4512 /* Convert *CODE into a code that can be used in a floating-point
4513 scc instruction (C.cond.fmt). Return true if the values of
4514 the condition code registers will be inverted, with 0 indicating
4515 that the condition holds. */
4518 mips_reversed_fp_cond (enum rtx_code *code)
4525 *code = reverse_condition_maybe_unordered (*code);
4533 /* Allocate a floating-point condition-code register of mode MODE.
4535 These condition code registers are used for certain kinds
4536 of compound operation, such as compare and branches, vconds,
4537 and built-in functions. At expand time, their use is entirely
4538 controlled by MIPS-specific code and is entirely internal
4539 to these compound operations.
4541 We could (and did in the past) expose condition-code values
4542 as pseudo registers and leave the register allocator to pick
4543 appropriate registers. The problem is that it is not practically
4544 possible for the rtl optimizers to guarantee that no spills will
4545 be needed, even when AVOID_CCMODE_COPIES is defined. We would
4546 therefore need spill and reload sequences to handle the worst case.
4548 Although such sequences do exist, they are very expensive and are
4549 not something we'd want to use. This is especially true of CCV2 and
4550 CCV4, where all the shuffling would greatly outweigh whatever benefit
4551 the vectorization itself provides.
4553 The main benefit of having more than one condition-code register
4554 is to allow the pipelining of operations, especially those involving
4555 comparisons and conditional moves. We don't really expect the
4556 registers to be live for long periods, and certainly never want
4557 them to be live across calls.
4559 Also, there should be no penalty attached to using all the available
4560 registers. They are simply bits in the same underlying FPU control
4563 We therefore expose the hardware registers from the outset and use
4564 a simple round-robin allocation scheme. */
4567 mips_allocate_fcc (enum machine_mode mode)
4569 unsigned int regno, count;
4571 gcc_assert (TARGET_HARD_FLOAT && ISA_HAS_8CC);
4575 else if (mode == CCV2mode)
4577 else if (mode == CCV4mode)
4582 cfun->machine->next_fcc += -cfun->machine->next_fcc & (count - 1);
4583 if (cfun->machine->next_fcc > ST_REG_LAST - ST_REG_FIRST)
4584 cfun->machine->next_fcc = 0;
4585 regno = ST_REG_FIRST + cfun->machine->next_fcc;
4586 cfun->machine->next_fcc += count;
4587 return gen_rtx_REG (mode, regno);
4590 /* Convert a comparison into something that can be used in a branch or
4591 conditional move. On entry, *OP0 and *OP1 are the values being
4592 compared and *CODE is the code used to compare them.
4594 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
4595 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
4596 otherwise any standard branch condition can be used. The standard branch
4599 - EQ or NE between two registers.
4600 - any comparison between a register and zero. */
4603 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
4608 if (GET_MODE_CLASS (GET_MODE (*op0)) == MODE_INT)
4610 if (!need_eq_ne_p && *op1 == const0_rtx)
4612 else if (*code == EQ || *code == NE)
4616 *op0 = mips_zero_if_equal (cmp_op0, cmp_op1);
4620 *op1 = force_reg (GET_MODE (cmp_op0), cmp_op1);
4624 /* The comparison needs a separate scc instruction. Store the
4625 result of the scc in *OP0 and compare it against zero. */
4626 bool invert = false;
4627 *op0 = gen_reg_rtx (GET_MODE (cmp_op0));
4628 mips_emit_int_order_test (*code, &invert, *op0, cmp_op0, cmp_op1);
4629 *code = (invert ? EQ : NE);
4633 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0)))
4635 *op0 = gen_rtx_REG (CCDSPmode, CCDSP_CC_REGNUM);
4636 mips_emit_binary (*code, *op0, cmp_op0, cmp_op1);
4642 enum rtx_code cmp_code;
4644 /* Floating-point tests use a separate C.cond.fmt comparison to
4645 set a condition code register. The branch or conditional move
4646 will then compare that register against zero.
4648 Set CMP_CODE to the code of the comparison instruction and
4649 *CODE to the code that the branch or move should use. */
4651 *code = mips_reversed_fp_cond (&cmp_code) ? EQ : NE;
4653 ? mips_allocate_fcc (CCmode)
4654 : gen_rtx_REG (CCmode, FPSW_REGNUM));
4656 mips_emit_binary (cmp_code, *op0, cmp_op0, cmp_op1);
4660 /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2]
4661 and OPERAND[3]. Store the result in OPERANDS[0].
4663 On 64-bit targets, the mode of the comparison and target will always be
4664 SImode, thus possibly narrower than that of the comparison's operands. */
4667 mips_expand_scc (rtx operands[])
4669 rtx target = operands[0];
4670 enum rtx_code code = GET_CODE (operands[1]);
4671 rtx op0 = operands[2];
4672 rtx op1 = operands[3];
4674 gcc_assert (GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT);
4676 if (code == EQ || code == NE)
4679 && reg_imm10_operand (op1, GET_MODE (op1)))
4680 mips_emit_binary (code, target, op0, op1);
4683 rtx zie = mips_zero_if_equal (op0, op1);
4684 mips_emit_binary (code, target, zie, const0_rtx);
4688 mips_emit_int_order_test (code, 0, target, op0, op1);
4691 /* Compare OPERANDS[1] with OPERANDS[2] using comparison code
4692 CODE and jump to OPERANDS[3] if the condition holds. */
4695 mips_expand_conditional_branch (rtx *operands)
4697 enum rtx_code code = GET_CODE (operands[0]);
4698 rtx op0 = operands[1];
4699 rtx op1 = operands[2];
4702 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
4703 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
4704 emit_jump_insn (gen_condjump (condition, operands[3]));
4709 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
4710 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
4713 mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
4714 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
4719 reversed_p = mips_reversed_fp_cond (&cond);
4720 cmp_result = mips_allocate_fcc (CCV2mode);
4721 emit_insn (gen_scc_ps (cmp_result,
4722 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
4724 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
4727 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
4731 /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0]
4732 if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
4735 mips_expand_conditional_move (rtx *operands)
4738 enum rtx_code code = GET_CODE (operands[1]);
4739 rtx op0 = XEXP (operands[1], 0);
4740 rtx op1 = XEXP (operands[1], 1);
4742 mips_emit_compare (&code, &op0, &op1, true);
4743 cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
4744 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
4745 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), cond,
4746 operands[2], operands[3])));
4749 /* Perform the comparison in COMPARISON, then trap if the condition holds. */
4752 mips_expand_conditional_trap (rtx comparison)
4755 enum machine_mode mode;
4758 /* MIPS conditional trap instructions don't have GT or LE flavors,
4759 so we must swap the operands and convert to LT and GE respectively. */
4760 code = GET_CODE (comparison);
4767 code = swap_condition (code);
4768 op0 = XEXP (comparison, 1);
4769 op1 = XEXP (comparison, 0);
4773 op0 = XEXP (comparison, 0);
4774 op1 = XEXP (comparison, 1);
4778 mode = GET_MODE (XEXP (comparison, 0));
4779 op0 = force_reg (mode, op0);
4780 if (!arith_operand (op1, mode))
4781 op1 = force_reg (mode, op1);
4783 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
4784 gen_rtx_fmt_ee (code, mode, op0, op1),
4788 /* Initialize *CUM for a call to a function of type FNTYPE. */
4791 mips_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype)
4793 memset (cum, 0, sizeof (*cum));
4794 cum->prototype = (fntype && prototype_p (fntype));
4795 cum->gp_reg_found = (cum->prototype && stdarg_p (fntype));
4798 /* Fill INFO with information about a single argument. CUM is the
4799 cumulative state for earlier arguments. MODE is the mode of this
4800 argument and TYPE is its type (if known). NAMED is true if this
4801 is a named (fixed) argument rather than a variable one. */
4804 mips_get_arg_info (struct mips_arg_info *info, const CUMULATIVE_ARGS *cum,
4805 enum machine_mode mode, const_tree type, bool named)
4807 bool doubleword_aligned_p;
4808 unsigned int num_bytes, num_words, max_regs;
4810 /* Work out the size of the argument. */
4811 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
4812 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4814 /* Decide whether it should go in a floating-point register, assuming
4815 one is free. Later code checks for availability.
4817 The checks against UNITS_PER_FPVALUE handle the soft-float and
4818 single-float cases. */
4822 /* The EABI conventions have traditionally been defined in terms
4823 of TYPE_MODE, regardless of the actual type. */
4824 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
4825 || mode == V2SFmode)
4826 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4831 /* Only leading floating-point scalars are passed in
4832 floating-point registers. We also handle vector floats the same
4833 say, which is OK because they are not covered by the standard ABI. */
4834 info->fpr_p = (!cum->gp_reg_found
4835 && cum->arg_number < 2
4837 || SCALAR_FLOAT_TYPE_P (type)
4838 || VECTOR_FLOAT_TYPE_P (type))
4839 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4840 || mode == V2SFmode)
4841 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4846 /* Scalar, complex and vector floating-point types are passed in
4847 floating-point registers, as long as this is a named rather
4848 than a variable argument. */
4849 info->fpr_p = (named
4850 && (type == 0 || FLOAT_TYPE_P (type))
4851 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4852 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4853 || mode == V2SFmode)
4854 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
4856 /* ??? According to the ABI documentation, the real and imaginary
4857 parts of complex floats should be passed in individual registers.
4858 The real and imaginary parts of stack arguments are supposed
4859 to be contiguous and there should be an extra word of padding
4862 This has two problems. First, it makes it impossible to use a
4863 single "void *" va_list type, since register and stack arguments
4864 are passed differently. (At the time of writing, MIPSpro cannot
4865 handle complex float varargs correctly.) Second, it's unclear
4866 what should happen when there is only one register free.
4868 For now, we assume that named complex floats should go into FPRs
4869 if there are two FPRs free, otherwise they should be passed in the
4870 same way as a struct containing two floats. */
4872 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4873 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
4875 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
4876 info->fpr_p = false;
4886 /* See whether the argument has doubleword alignment. */
4887 doubleword_aligned_p = (mips_function_arg_boundary (mode, type)
4890 /* Set REG_OFFSET to the register count we're interested in.
4891 The EABI allocates the floating-point registers separately,
4892 but the other ABIs allocate them like integer registers. */
4893 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
4897 /* Advance to an even register if the argument is doubleword-aligned. */
4898 if (doubleword_aligned_p)
4899 info->reg_offset += info->reg_offset & 1;
4901 /* Work out the offset of a stack argument. */
4902 info->stack_offset = cum->stack_words;
4903 if (doubleword_aligned_p)
4904 info->stack_offset += info->stack_offset & 1;
4906 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
4908 /* Partition the argument between registers and stack. */
4909 info->reg_words = MIN (num_words, max_regs);
4910 info->stack_words = num_words - info->reg_words;
4913 /* INFO describes a register argument that has the normal format for the
4914 argument's mode. Return the register it uses, assuming that FPRs are
4915 available if HARD_FLOAT_P. */
4918 mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p)
4920 if (!info->fpr_p || !hard_float_p)
4921 return GP_ARG_FIRST + info->reg_offset;
4922 else if (mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info->reg_offset > 0)
4923 /* In o32, the second argument is always passed in $f14
4924 for TARGET_DOUBLE_FLOAT, regardless of whether the
4925 first argument was a word or doubleword. */
4926 return FP_ARG_FIRST + 2;
4928 return FP_ARG_FIRST + info->reg_offset;
4931 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
4934 mips_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED)
4936 return !TARGET_OLDABI;
4939 /* Implement TARGET_FUNCTION_ARG. */
4942 mips_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
4943 const_tree type, bool named)
4945 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
4946 struct mips_arg_info info;
4948 /* We will be called with a mode of VOIDmode after the last argument
4949 has been seen. Whatever we return will be passed to the call expander.
4950 If we need a MIPS16 fp_code, return a REG with the code stored as
4952 if (mode == VOIDmode)
4954 if (TARGET_MIPS16 && cum->fp_code != 0)
4955 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
4960 mips_get_arg_info (&info, cum, mode, type, named);
4962 /* Return straight away if the whole argument is passed on the stack. */
4963 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
4966 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
4967 contains a double in its entirety, then that 64-bit chunk is passed
4968 in a floating-point register. */
4970 && TARGET_HARD_FLOAT
4973 && TREE_CODE (type) == RECORD_TYPE
4974 && TYPE_SIZE_UNIT (type)
4975 && host_integerp (TYPE_SIZE_UNIT (type), 1))
4979 /* First check to see if there is any such field. */
4980 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
4981 if (TREE_CODE (field) == FIELD_DECL
4982 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
4983 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
4984 && host_integerp (bit_position (field), 0)
4985 && int_bit_position (field) % BITS_PER_WORD == 0)
4990 /* Now handle the special case by returning a PARALLEL
4991 indicating where each 64-bit chunk goes. INFO.REG_WORDS
4992 chunks are passed in registers. */
4994 HOST_WIDE_INT bitpos;
4997 /* assign_parms checks the mode of ENTRY_PARM, so we must
4998 use the actual mode here. */
4999 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
5002 field = TYPE_FIELDS (type);
5003 for (i = 0; i < info.reg_words; i++)
5007 for (; field; field = DECL_CHAIN (field))
5008 if (TREE_CODE (field) == FIELD_DECL
5009 && int_bit_position (field) >= bitpos)
5013 && int_bit_position (field) == bitpos
5014 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
5015 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
5016 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
5018 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
5021 = gen_rtx_EXPR_LIST (VOIDmode, reg,
5022 GEN_INT (bitpos / BITS_PER_UNIT));
5024 bitpos += BITS_PER_WORD;
5030 /* Handle the n32/n64 conventions for passing complex floating-point
5031 arguments in FPR pairs. The real part goes in the lower register
5032 and the imaginary part goes in the upper register. */
5035 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5038 enum machine_mode inner;
5041 inner = GET_MODE_INNER (mode);
5042 regno = FP_ARG_FIRST + info.reg_offset;
5043 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
5045 /* Real part in registers, imaginary part on stack. */
5046 gcc_assert (info.stack_words == info.reg_words);
5047 return gen_rtx_REG (inner, regno);
5051 gcc_assert (info.stack_words == 0);
5052 real = gen_rtx_EXPR_LIST (VOIDmode,
5053 gen_rtx_REG (inner, regno),
5055 imag = gen_rtx_EXPR_LIST (VOIDmode,
5057 regno + info.reg_words / 2),
5058 GEN_INT (GET_MODE_SIZE (inner)));
5059 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
5063 return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT));
5066 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
5069 mips_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
5070 const_tree type, bool named)
5072 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
5073 struct mips_arg_info info;
5075 mips_get_arg_info (&info, cum, mode, type, named);
5078 cum->gp_reg_found = true;
5080 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
5081 an explanation of what this code does. It assumes that we're using
5082 either the o32 or the o64 ABI, both of which pass at most 2 arguments
5084 if (cum->arg_number < 2 && info.fpr_p)
5085 cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2);
5087 /* Advance the register count. This has the effect of setting
5088 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
5089 argument required us to skip the final GPR and pass the whole
5090 argument on the stack. */
5091 if (mips_abi != ABI_EABI || !info.fpr_p)
5092 cum->num_gprs = info.reg_offset + info.reg_words;
5093 else if (info.reg_words > 0)
5094 cum->num_fprs += MAX_FPRS_PER_FMT;
5096 /* Advance the stack word count. */
5097 if (info.stack_words > 0)
5098 cum->stack_words = info.stack_offset + info.stack_words;
5103 /* Implement TARGET_ARG_PARTIAL_BYTES. */
5106 mips_arg_partial_bytes (cumulative_args_t cum,
5107 enum machine_mode mode, tree type, bool named)
5109 struct mips_arg_info info;
5111 mips_get_arg_info (&info, get_cumulative_args (cum), mode, type, named);
5112 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
5115 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
5116 least PARM_BOUNDARY bits of alignment, but will be given anything up
5117 to STACK_BOUNDARY bits if the type requires it. */
5120 mips_function_arg_boundary (enum machine_mode mode, const_tree type)
5122 unsigned int alignment;
5124 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
5125 if (alignment < PARM_BOUNDARY)
5126 alignment = PARM_BOUNDARY;
5127 if (alignment > STACK_BOUNDARY)
5128 alignment = STACK_BOUNDARY;
5132 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
5133 upward rather than downward. In other words, return true if the
5134 first byte of the stack slot has useful data, false if the last
5138 mips_pad_arg_upward (enum machine_mode mode, const_tree type)
5140 /* On little-endian targets, the first byte of every stack argument
5141 is passed in the first byte of the stack slot. */
5142 if (!BYTES_BIG_ENDIAN)
5145 /* Otherwise, integral types are padded downward: the last byte of a
5146 stack argument is passed in the last byte of the stack slot. */
5148 ? (INTEGRAL_TYPE_P (type)
5149 || POINTER_TYPE_P (type)
5150 || FIXED_POINT_TYPE_P (type))
5151 : (SCALAR_INT_MODE_P (mode)
5152 || ALL_SCALAR_FIXED_POINT_MODE_P (mode)))
5155 /* Big-endian o64 pads floating-point arguments downward. */
5156 if (mips_abi == ABI_O64)
5157 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
5160 /* Other types are padded upward for o32, o64, n32 and n64. */
5161 if (mips_abi != ABI_EABI)
5164 /* Arguments smaller than a stack slot are padded downward. */
5165 if (mode != BLKmode)
5166 return GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY;
5168 return int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT);
5171 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
5172 if the least significant byte of the register has useful data. Return
5173 the opposite if the most significant byte does. */
5176 mips_pad_reg_upward (enum machine_mode mode, tree type)
5178 /* No shifting is required for floating-point arguments. */
5179 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
5180 return !BYTES_BIG_ENDIAN;
5182 /* Otherwise, apply the same padding to register arguments as we do
5183 to stack arguments. */
5184 return mips_pad_arg_upward (mode, type);
5187 /* Return nonzero when an argument must be passed by reference. */
5190 mips_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
5191 enum machine_mode mode, const_tree type,
5192 bool named ATTRIBUTE_UNUSED)
5194 if (mips_abi == ABI_EABI)
5198 /* ??? How should SCmode be handled? */
5199 if (mode == DImode || mode == DFmode
5200 || mode == DQmode || mode == UDQmode
5201 || mode == DAmode || mode == UDAmode)
5204 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
5205 return size == -1 || size > UNITS_PER_WORD;
5209 /* If we have a variable-sized parameter, we have no choice. */
5210 return targetm.calls.must_pass_in_stack (mode, type);
5214 /* Implement TARGET_CALLEE_COPIES. */
5217 mips_callee_copies (cumulative_args_t cum ATTRIBUTE_UNUSED,
5218 enum machine_mode mode ATTRIBUTE_UNUSED,
5219 const_tree type ATTRIBUTE_UNUSED, bool named)
5221 return mips_abi == ABI_EABI && named;
5224 /* See whether VALTYPE is a record whose fields should be returned in
5225 floating-point registers. If so, return the number of fields and
5226 list them in FIELDS (which should have two elements). Return 0
5229 For n32 & n64, a structure with one or two fields is returned in
5230 floating-point registers as long as every field has a floating-point
5234 mips_fpr_return_fields (const_tree valtype, tree *fields)
5242 if (TREE_CODE (valtype) != RECORD_TYPE)
5246 for (field = TYPE_FIELDS (valtype); field != 0; field = DECL_CHAIN (field))
5248 if (TREE_CODE (field) != FIELD_DECL)
5251 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)))
5257 fields[i++] = field;
5262 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
5263 a value in the most significant part of $2/$3 if:
5265 - the target is big-endian;
5267 - the value has a structure or union type (we generalize this to
5268 cover aggregates from other languages too); and
5270 - the structure is not returned in floating-point registers. */
5273 mips_return_in_msb (const_tree valtype)
5277 return (TARGET_NEWABI
5278 && TARGET_BIG_ENDIAN
5279 && AGGREGATE_TYPE_P (valtype)
5280 && mips_fpr_return_fields (valtype, fields) == 0);
5283 /* Return true if the function return value MODE will get returned in a
5284 floating-point register. */
5287 mips_return_mode_in_fpr_p (enum machine_mode mode)
5289 return ((GET_MODE_CLASS (mode) == MODE_FLOAT
5291 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5292 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE);
5295 /* Return the representation of an FPR return register when the
5296 value being returned in FP_RETURN has mode VALUE_MODE and the
5297 return type itself has mode TYPE_MODE. On NewABI targets,
5298 the two modes may be different for structures like:
5300 struct __attribute__((packed)) foo { float f; }
5302 where we return the SFmode value of "f" in FP_RETURN, but where
5303 the structure itself has mode BLKmode. */
5306 mips_return_fpr_single (enum machine_mode type_mode,
5307 enum machine_mode value_mode)
5311 x = gen_rtx_REG (value_mode, FP_RETURN);
5312 if (type_mode != value_mode)
5314 x = gen_rtx_EXPR_LIST (VOIDmode, x, const0_rtx);
5315 x = gen_rtx_PARALLEL (type_mode, gen_rtvec (1, x));
5320 /* Return a composite value in a pair of floating-point registers.
5321 MODE1 and OFFSET1 are the mode and byte offset for the first value,
5322 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
5325 For n32 & n64, $f0 always holds the first value and $f2 the second.
5326 Otherwise the values are packed together as closely as possible. */
5329 mips_return_fpr_pair (enum machine_mode mode,
5330 enum machine_mode mode1, HOST_WIDE_INT offset1,
5331 enum machine_mode mode2, HOST_WIDE_INT offset2)
5335 inc = (TARGET_NEWABI ? 2 : MAX_FPRS_PER_FMT);
5336 return gen_rtx_PARALLEL
5339 gen_rtx_EXPR_LIST (VOIDmode,
5340 gen_rtx_REG (mode1, FP_RETURN),
5342 gen_rtx_EXPR_LIST (VOIDmode,
5343 gen_rtx_REG (mode2, FP_RETURN + inc),
5344 GEN_INT (offset2))));
5348 /* Implement TARGET_FUNCTION_VALUE and TARGET_LIBCALL_VALUE.
5349 For normal calls, VALTYPE is the return type and MODE is VOIDmode.
5350 For libcalls, VALTYPE is null and MODE is the mode of the return value. */
5353 mips_function_value_1 (const_tree valtype, const_tree fn_decl_or_type,
5354 enum machine_mode mode)
5362 if (fn_decl_or_type && DECL_P (fn_decl_or_type))
5363 func = fn_decl_or_type;
5367 mode = TYPE_MODE (valtype);
5368 unsigned_p = TYPE_UNSIGNED (valtype);
5370 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
5371 return values, promote the mode here too. */
5372 mode = promote_function_mode (valtype, mode, &unsigned_p, func, 1);
5374 /* Handle structures whose fields are returned in $f0/$f2. */
5375 switch (mips_fpr_return_fields (valtype, fields))
5378 return mips_return_fpr_single (mode,
5379 TYPE_MODE (TREE_TYPE (fields[0])));
5382 return mips_return_fpr_pair (mode,
5383 TYPE_MODE (TREE_TYPE (fields[0])),
5384 int_byte_position (fields[0]),
5385 TYPE_MODE (TREE_TYPE (fields[1])),
5386 int_byte_position (fields[1]));
5389 /* If a value is passed in the most significant part of a register, see
5390 whether we have to round the mode up to a whole number of words. */
5391 if (mips_return_in_msb (valtype))
5393 HOST_WIDE_INT size = int_size_in_bytes (valtype);
5394 if (size % UNITS_PER_WORD != 0)
5396 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
5397 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
5401 /* For EABI, the class of return register depends entirely on MODE.
5402 For example, "struct { some_type x; }" and "union { some_type x; }"
5403 are returned in the same way as a bare "some_type" would be.
5404 Other ABIs only use FPRs for scalar, complex or vector types. */
5405 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
5406 return gen_rtx_REG (mode, GP_RETURN);
5411 /* Handle long doubles for n32 & n64. */
5413 return mips_return_fpr_pair (mode,
5415 DImode, GET_MODE_SIZE (mode) / 2);
5417 if (mips_return_mode_in_fpr_p (mode))
5419 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5420 return mips_return_fpr_pair (mode,
5421 GET_MODE_INNER (mode), 0,
5422 GET_MODE_INNER (mode),
5423 GET_MODE_SIZE (mode) / 2);
5425 return gen_rtx_REG (mode, FP_RETURN);
5429 return gen_rtx_REG (mode, GP_RETURN);
5432 /* Implement TARGET_FUNCTION_VALUE. */
5435 mips_function_value (const_tree valtype, const_tree fn_decl_or_type,
5436 bool outgoing ATTRIBUTE_UNUSED)
5438 return mips_function_value_1 (valtype, fn_decl_or_type, VOIDmode);
5441 /* Implement TARGET_LIBCALL_VALUE. */
5444 mips_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
5446 return mips_function_value_1 (NULL_TREE, NULL_TREE, mode);
5449 /* Implement TARGET_FUNCTION_VALUE_REGNO_P.
5451 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
5452 Currently, R2 and F0 are only implemented here (C has no complex type). */
5455 mips_function_value_regno_p (const unsigned int regno)
5457 if (regno == GP_RETURN
5458 || regno == FP_RETURN
5459 || (LONG_DOUBLE_TYPE_SIZE == 128
5460 && FP_RETURN != GP_RETURN
5461 && regno == FP_RETURN + 2))
5467 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
5468 all BLKmode objects are returned in memory. Under the n32, n64
5469 and embedded ABIs, small structures are returned in a register.
5470 Objects with varying size must still be returned in memory, of
5474 mips_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
5476 return (TARGET_OLDABI
5477 ? TYPE_MODE (type) == BLKmode
5478 : !IN_RANGE (int_size_in_bytes (type), 0, 2 * UNITS_PER_WORD));
5481 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
5484 mips_setup_incoming_varargs (cumulative_args_t cum, enum machine_mode mode,
5485 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5488 CUMULATIVE_ARGS local_cum;
5489 int gp_saved, fp_saved;
5491 /* The caller has advanced CUM up to, but not beyond, the last named
5492 argument. Advance a local copy of CUM past the last "real" named
5493 argument, to find out how many registers are left over. */
5494 local_cum = *get_cumulative_args (cum);
5495 mips_function_arg_advance (pack_cumulative_args (&local_cum), mode, type,
5498 /* Found out how many registers we need to save. */
5499 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
5500 fp_saved = (EABI_FLOAT_VARARGS_P
5501 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
5510 ptr = plus_constant (Pmode, virtual_incoming_args_rtx,
5511 REG_PARM_STACK_SPACE (cfun->decl)
5512 - gp_saved * UNITS_PER_WORD);
5513 mem = gen_frame_mem (BLKmode, ptr);
5514 set_mem_alias_set (mem, get_varargs_alias_set ());
5516 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
5521 /* We can't use move_block_from_reg, because it will use
5523 enum machine_mode mode;
5526 /* Set OFF to the offset from virtual_incoming_args_rtx of
5527 the first float register. The FP save area lies below
5528 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
5529 off = (-gp_saved * UNITS_PER_WORD) & -UNITS_PER_FPVALUE;
5530 off -= fp_saved * UNITS_PER_FPREG;
5532 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
5534 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS;
5535 i += MAX_FPRS_PER_FMT)
5539 ptr = plus_constant (Pmode, virtual_incoming_args_rtx, off);
5540 mem = gen_frame_mem (mode, ptr);
5541 set_mem_alias_set (mem, get_varargs_alias_set ());
5542 mips_emit_move (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
5543 off += UNITS_PER_HWFPVALUE;
5547 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
5548 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
5549 + fp_saved * UNITS_PER_FPREG);
5552 /* Implement TARGET_BUILTIN_VA_LIST. */
5555 mips_build_builtin_va_list (void)
5557 if (EABI_FLOAT_VARARGS_P)
5559 /* We keep 3 pointers, and two offsets.
5561 Two pointers are to the overflow area, which starts at the CFA.
5562 One of these is constant, for addressing into the GPR save area
5563 below it. The other is advanced up the stack through the
5566 The third pointer is to the bottom of the GPR save area.
5567 Since the FPR save area is just below it, we can address
5568 FPR slots off this pointer.
5570 We also keep two one-byte offsets, which are to be subtracted
5571 from the constant pointers to yield addresses in the GPR and
5572 FPR save areas. These are downcounted as float or non-float
5573 arguments are used, and when they get to zero, the argument
5574 must be obtained from the overflow region. */
5575 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
5578 record = lang_hooks.types.make_type (RECORD_TYPE);
5580 f_ovfl = build_decl (BUILTINS_LOCATION,
5581 FIELD_DECL, get_identifier ("__overflow_argptr"),
5583 f_gtop = build_decl (BUILTINS_LOCATION,
5584 FIELD_DECL, get_identifier ("__gpr_top"),
5586 f_ftop = build_decl (BUILTINS_LOCATION,
5587 FIELD_DECL, get_identifier ("__fpr_top"),
5589 f_goff = build_decl (BUILTINS_LOCATION,
5590 FIELD_DECL, get_identifier ("__gpr_offset"),
5591 unsigned_char_type_node);
5592 f_foff = build_decl (BUILTINS_LOCATION,
5593 FIELD_DECL, get_identifier ("__fpr_offset"),
5594 unsigned_char_type_node);
5595 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
5596 warn on every user file. */
5597 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
5598 array = build_array_type (unsigned_char_type_node,
5599 build_index_type (index));
5600 f_res = build_decl (BUILTINS_LOCATION,
5601 FIELD_DECL, get_identifier ("__reserved"), array);
5603 DECL_FIELD_CONTEXT (f_ovfl) = record;
5604 DECL_FIELD_CONTEXT (f_gtop) = record;
5605 DECL_FIELD_CONTEXT (f_ftop) = record;
5606 DECL_FIELD_CONTEXT (f_goff) = record;
5607 DECL_FIELD_CONTEXT (f_foff) = record;
5608 DECL_FIELD_CONTEXT (f_res) = record;
5610 TYPE_FIELDS (record) = f_ovfl;
5611 DECL_CHAIN (f_ovfl) = f_gtop;
5612 DECL_CHAIN (f_gtop) = f_ftop;
5613 DECL_CHAIN (f_ftop) = f_goff;
5614 DECL_CHAIN (f_goff) = f_foff;
5615 DECL_CHAIN (f_foff) = f_res;
5617 layout_type (record);
5621 /* Otherwise, we use 'void *'. */
5622 return ptr_type_node;
5625 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
5628 mips_va_start (tree valist, rtx nextarg)
5630 if (EABI_FLOAT_VARARGS_P)
5632 const CUMULATIVE_ARGS *cum;
5633 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5634 tree ovfl, gtop, ftop, goff, foff;
5636 int gpr_save_area_size;
5637 int fpr_save_area_size;
5640 cum = &crtl->args.info;
5642 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
5644 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
5646 f_ovfl = TYPE_FIELDS (va_list_type_node);
5647 f_gtop = DECL_CHAIN (f_ovfl);
5648 f_ftop = DECL_CHAIN (f_gtop);
5649 f_goff = DECL_CHAIN (f_ftop);
5650 f_foff = DECL_CHAIN (f_goff);
5652 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5654 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
5656 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
5658 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
5660 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
5663 /* Emit code to initialize OVFL, which points to the next varargs
5664 stack argument. CUM->STACK_WORDS gives the number of stack
5665 words used by named arguments. */
5666 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
5667 if (cum->stack_words > 0)
5668 t = fold_build_pointer_plus_hwi (t, cum->stack_words * UNITS_PER_WORD);
5669 t = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
5670 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5672 /* Emit code to initialize GTOP, the top of the GPR save area. */
5673 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
5674 t = build2 (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
5675 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5677 /* Emit code to initialize FTOP, the top of the FPR save area.
5678 This address is gpr_save_area_bytes below GTOP, rounded
5679 down to the next fp-aligned boundary. */
5680 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
5681 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
5682 fpr_offset &= -UNITS_PER_FPVALUE;
5684 t = fold_build_pointer_plus_hwi (t, -fpr_offset);
5685 t = build2 (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
5686 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5688 /* Emit code to initialize GOFF, the offset from GTOP of the
5689 next GPR argument. */
5690 t = build2 (MODIFY_EXPR, TREE_TYPE (goff), goff,
5691 build_int_cst (TREE_TYPE (goff), gpr_save_area_size));
5692 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5694 /* Likewise emit code to initialize FOFF, the offset from FTOP
5695 of the next FPR argument. */
5696 t = build2 (MODIFY_EXPR, TREE_TYPE (foff), foff,
5697 build_int_cst (TREE_TYPE (foff), fpr_save_area_size));
5698 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5702 nextarg = plus_constant (Pmode, nextarg, -cfun->machine->varargs_size);
5703 std_expand_builtin_va_start (valist, nextarg);
5707 /* Like std_gimplify_va_arg_expr, but apply alignment to zero-sized
5711 mips_std_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
5714 tree addr, t, type_size, rounded_size, valist_tmp;
5715 unsigned HOST_WIDE_INT align, boundary;
5718 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, false);
5720 type = build_pointer_type (type);
5722 align = PARM_BOUNDARY / BITS_PER_UNIT;
5723 boundary = targetm.calls.function_arg_boundary (TYPE_MODE (type), type);
5725 /* When we align parameter on stack for caller, if the parameter
5726 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
5727 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
5728 here with caller. */
5729 if (boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
5730 boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
5732 boundary /= BITS_PER_UNIT;
5734 /* Hoist the valist value into a temporary for the moment. */
5735 valist_tmp = get_initialized_tmp_var (valist, pre_p, NULL);
5737 /* va_list pointer is aligned to PARM_BOUNDARY. If argument actually
5738 requires greater alignment, we must perform dynamic alignment. */
5739 if (boundary > align)
5741 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
5742 fold_build_pointer_plus_hwi (valist_tmp, boundary - 1));
5743 gimplify_and_add (t, pre_p);
5745 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
5746 fold_build2 (BIT_AND_EXPR, TREE_TYPE (valist),
5748 build_int_cst (TREE_TYPE (valist), -boundary)));
5749 gimplify_and_add (t, pre_p);
5754 /* If the actual alignment is less than the alignment of the type,
5755 adjust the type accordingly so that we don't assume strict alignment
5756 when dereferencing the pointer. */
5757 boundary *= BITS_PER_UNIT;
5758 if (boundary < TYPE_ALIGN (type))
5760 type = build_variant_type_copy (type);
5761 TYPE_ALIGN (type) = boundary;
5764 /* Compute the rounded size of the type. */
5765 type_size = size_in_bytes (type);
5766 rounded_size = round_up (type_size, align);
5768 /* Reduce rounded_size so it's sharable with the postqueue. */
5769 gimplify_expr (&rounded_size, pre_p, post_p, is_gimple_val, fb_rvalue);
5773 if (PAD_VARARGS_DOWN && !integer_zerop (rounded_size))
5775 /* Small args are padded downward. */
5776 t = fold_build2_loc (input_location, GT_EXPR, sizetype,
5777 rounded_size, size_int (align));
5778 t = fold_build3 (COND_EXPR, sizetype, t, size_zero_node,
5779 size_binop (MINUS_EXPR, rounded_size, type_size));
5780 addr = fold_build_pointer_plus (addr, t);
5783 /* Compute new value for AP. */
5784 t = fold_build_pointer_plus (valist_tmp, rounded_size);
5785 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
5786 gimplify_and_add (t, pre_p);
5788 addr = fold_convert (build_pointer_type (type), addr);
5791 addr = build_va_arg_indirect_ref (addr);
5793 return build_va_arg_indirect_ref (addr);
5796 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
5799 mips_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
5805 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
5807 type = build_pointer_type (type);
5809 if (!EABI_FLOAT_VARARGS_P)
5810 addr = mips_std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5813 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5814 tree ovfl, top, off, align;
5815 HOST_WIDE_INT size, rsize, osize;
5818 f_ovfl = TYPE_FIELDS (va_list_type_node);
5819 f_gtop = DECL_CHAIN (f_ovfl);
5820 f_ftop = DECL_CHAIN (f_gtop);
5821 f_goff = DECL_CHAIN (f_ftop);
5822 f_foff = DECL_CHAIN (f_goff);
5826 TOP be the top of the GPR or FPR save area;
5827 OFF be the offset from TOP of the next register;
5828 ADDR_RTX be the address of the argument;
5829 SIZE be the number of bytes in the argument type;
5830 RSIZE be the number of bytes used to store the argument
5831 when it's in the register save area; and
5832 OSIZE be the number of bytes used to store it when it's
5833 in the stack overflow area.
5835 The code we want is:
5837 1: off &= -rsize; // round down
5840 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
5845 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
5846 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
5850 [1] and [9] can sometimes be optimized away. */
5852 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5854 size = int_size_in_bytes (type);
5856 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
5857 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
5859 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop),
5860 unshare_expr (valist), f_ftop, NULL_TREE);
5861 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff),
5862 unshare_expr (valist), f_foff, NULL_TREE);
5864 /* When va_start saves FPR arguments to the stack, each slot
5865 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
5866 argument's precision. */
5867 rsize = UNITS_PER_HWFPVALUE;
5869 /* Overflow arguments are padded to UNITS_PER_WORD bytes
5870 (= PARM_BOUNDARY bits). This can be different from RSIZE
5873 (1) On 32-bit targets when TYPE is a structure such as:
5875 struct s { float f; };
5877 Such structures are passed in paired FPRs, so RSIZE
5878 will be 8 bytes. However, the structure only takes
5879 up 4 bytes of memory, so OSIZE will only be 4.
5881 (2) In combinations such as -mgp64 -msingle-float
5882 -fshort-double. Doubles passed in registers will then take
5883 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
5884 stack take up UNITS_PER_WORD bytes. */
5885 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
5889 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop),
5890 unshare_expr (valist), f_gtop, NULL_TREE);
5891 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff),
5892 unshare_expr (valist), f_goff, NULL_TREE);
5893 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
5894 if (rsize > UNITS_PER_WORD)
5896 /* [1] Emit code for: off &= -rsize. */
5897 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), unshare_expr (off),
5898 build_int_cst (TREE_TYPE (off), -rsize));
5899 gimplify_assign (unshare_expr (off), t, pre_p);
5904 /* [2] Emit code to branch if off == 0. */
5905 t = build2 (NE_EXPR, boolean_type_node, unshare_expr (off),
5906 build_int_cst (TREE_TYPE (off), 0));
5907 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
5909 /* [5] Emit code for: off -= rsize. We do this as a form of
5910 post-decrement not available to C. */
5911 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
5912 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
5914 /* [4] Emit code for:
5915 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
5916 t = fold_convert (sizetype, t);
5917 t = fold_build1 (NEGATE_EXPR, sizetype, t);
5918 t = fold_build_pointer_plus (top, t);
5919 if (BYTES_BIG_ENDIAN && rsize > size)
5920 t = fold_build_pointer_plus_hwi (t, rsize - size);
5921 COND_EXPR_THEN (addr) = t;
5923 if (osize > UNITS_PER_WORD)
5925 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
5926 t = fold_build_pointer_plus_hwi (unshare_expr (ovfl), osize - 1);
5927 u = build_int_cst (TREE_TYPE (t), -osize);
5928 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t, u);
5929 align = build2 (MODIFY_EXPR, TREE_TYPE (ovfl),
5930 unshare_expr (ovfl), t);
5935 /* [10, 11] Emit code for:
5936 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
5938 u = fold_convert (TREE_TYPE (ovfl), build_int_cst (NULL_TREE, osize));
5939 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
5940 if (BYTES_BIG_ENDIAN && osize > size)
5941 t = fold_build_pointer_plus_hwi (t, osize - size);
5943 /* String [9] and [10, 11] together. */
5945 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
5946 COND_EXPR_ELSE (addr) = t;
5948 addr = fold_convert (build_pointer_type (type), addr);
5949 addr = build_va_arg_indirect_ref (addr);
5953 addr = build_va_arg_indirect_ref (addr);
5958 /* Declare a unique, locally-binding function called NAME, then start
5962 mips_start_unique_function (const char *name)
5966 decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
5967 get_identifier (name),
5968 build_function_type_list (void_type_node, NULL_TREE));
5969 DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
5970 NULL_TREE, void_type_node);
5971 TREE_PUBLIC (decl) = 1;
5972 TREE_STATIC (decl) = 1;
5974 DECL_COMDAT_GROUP (decl) = DECL_ASSEMBLER_NAME (decl);
5976 targetm.asm_out.unique_section (decl, 0);
5977 switch_to_section (get_named_section (decl, NULL, 0));
5979 targetm.asm_out.globalize_label (asm_out_file, name);
5980 fputs ("\t.hidden\t", asm_out_file);
5981 assemble_name (asm_out_file, name);
5982 putc ('\n', asm_out_file);
5985 /* Start a definition of function NAME. MIPS16_P indicates whether the
5986 function contains MIPS16 code. */
5989 mips_start_function_definition (const char *name, bool mips16_p)
5992 fprintf (asm_out_file, "\t.set\tmips16\n");
5994 fprintf (asm_out_file, "\t.set\tnomips16\n");
5996 if (!flag_inhibit_size_directive)
5998 fputs ("\t.ent\t", asm_out_file);
5999 assemble_name (asm_out_file, name);
6000 fputs ("\n", asm_out_file);
6003 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, name, "function");
6005 /* Start the definition proper. */
6006 assemble_name (asm_out_file, name);
6007 fputs (":\n", asm_out_file);
6010 /* End a function definition started by mips_start_function_definition. */
6013 mips_end_function_definition (const char *name)
6015 if (!flag_inhibit_size_directive)
6017 fputs ("\t.end\t", asm_out_file);
6018 assemble_name (asm_out_file, name);
6019 fputs ("\n", asm_out_file);
6023 /* Output a definition of the __mips16_rdhwr function. */
6026 mips_output_mips16_rdhwr (void)
6030 name = "__mips16_rdhwr";
6031 mips_start_unique_function (name);
6032 mips_start_function_definition (name, false);
6033 fprintf (asm_out_file,
6035 "\t.set\tmips32r2\n"
6036 "\t.set\tnoreorder\n"
6040 mips_end_function_definition (name);
6043 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
6046 mips_ok_for_lazy_binding_p (rtx x)
6048 return (TARGET_USE_GOT
6049 && GET_CODE (x) == SYMBOL_REF
6050 && !SYMBOL_REF_BIND_NOW_P (x)
6051 && !mips_symbol_binds_local_p (x));
6054 /* Load function address ADDR into register DEST. TYPE is as for
6055 mips_expand_call. Return true if we used an explicit lazy-binding
6059 mips_load_call_address (enum mips_call_type type, rtx dest, rtx addr)
6061 /* If we're generating PIC, and this call is to a global function,
6062 try to allow its address to be resolved lazily. This isn't
6063 possible for sibcalls when $gp is call-saved because the value
6064 of $gp on entry to the stub would be our caller's gp, not ours. */
6065 if (TARGET_EXPLICIT_RELOCS
6066 && !(type == MIPS_CALL_SIBCALL && TARGET_CALL_SAVED_GP)
6067 && mips_ok_for_lazy_binding_p (addr))
6069 addr = mips_got_load (dest, addr, SYMBOL_GOTOFF_CALL);
6070 emit_insn (gen_rtx_SET (VOIDmode, dest, addr));
6075 mips_emit_move (dest, addr);
6080 /* Each locally-defined hard-float MIPS16 function has a local symbol
6081 associated with it. This hash table maps the function symbol (FUNC)
6082 to the local symbol (LOCAL). */
6083 struct GTY(()) mips16_local_alias {
6087 static GTY ((param_is (struct mips16_local_alias))) htab_t mips16_local_aliases;
6089 /* Hash table callbacks for mips16_local_aliases. */
6092 mips16_local_aliases_hash (const void *entry)
6094 const struct mips16_local_alias *alias;
6096 alias = (const struct mips16_local_alias *) entry;
6097 return htab_hash_string (XSTR (alias->func, 0));
6101 mips16_local_aliases_eq (const void *entry1, const void *entry2)
6103 const struct mips16_local_alias *alias1, *alias2;
6105 alias1 = (const struct mips16_local_alias *) entry1;
6106 alias2 = (const struct mips16_local_alias *) entry2;
6107 return rtx_equal_p (alias1->func, alias2->func);
6110 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
6111 Return a local alias for it, creating a new one if necessary. */
6114 mips16_local_alias (rtx func)
6116 struct mips16_local_alias *alias, tmp_alias;
6119 /* Create the hash table if this is the first call. */
6120 if (mips16_local_aliases == NULL)
6121 mips16_local_aliases = htab_create_ggc (37, mips16_local_aliases_hash,
6122 mips16_local_aliases_eq, NULL);
6124 /* Look up the function symbol, creating a new entry if need be. */
6125 tmp_alias.func = func;
6126 slot = htab_find_slot (mips16_local_aliases, &tmp_alias, INSERT);
6127 gcc_assert (slot != NULL);
6129 alias = (struct mips16_local_alias *) *slot;
6132 const char *func_name, *local_name;
6135 /* Create a new SYMBOL_REF for the local symbol. The choice of
6136 __fn_local_* is based on the __fn_stub_* names that we've
6137 traditionally used for the non-MIPS16 stub. */
6138 func_name = targetm.strip_name_encoding (XSTR (func, 0));
6139 local_name = ACONCAT (("__fn_local_", func_name, NULL));
6140 local = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (local_name));
6141 SYMBOL_REF_FLAGS (local) = SYMBOL_REF_FLAGS (func) | SYMBOL_FLAG_LOCAL;
6143 /* Create a new structure to represent the mapping. */
6144 alias = ggc_alloc_mips16_local_alias ();
6146 alias->local = local;
6149 return alias->local;
6152 /* A chained list of functions for which mips16_build_call_stub has already
6153 generated a stub. NAME is the name of the function and FP_RET_P is true
6154 if the function returns a value in floating-point registers. */
6155 struct mips16_stub {
6156 struct mips16_stub *next;
6160 static struct mips16_stub *mips16_stubs;
6162 /* Return the two-character string that identifies floating-point
6163 return mode MODE in the name of a MIPS16 function stub. */
6166 mips16_call_stub_mode_suffix (enum machine_mode mode)
6170 else if (mode == DFmode)
6172 else if (mode == SCmode)
6174 else if (mode == DCmode)
6176 else if (mode == V2SFmode)
6182 /* Write instructions to move a 32-bit value between general register
6183 GPREG and floating-point register FPREG. DIRECTION is 't' to move
6184 from GPREG to FPREG and 'f' to move in the opposite direction. */
6187 mips_output_32bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
6189 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6190 reg_names[gpreg], reg_names[fpreg]);
6193 /* Likewise for 64-bit values. */
6196 mips_output_64bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
6199 fprintf (asm_out_file, "\tdm%cc1\t%s,%s\n", direction,
6200 reg_names[gpreg], reg_names[fpreg]);
6201 else if (TARGET_FLOAT64)
6203 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6204 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
6205 fprintf (asm_out_file, "\tm%chc1\t%s,%s\n", direction,
6206 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg]);
6210 /* Move the least-significant word. */
6211 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6212 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
6213 /* ...then the most significant word. */
6214 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6215 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg + 1]);
6219 /* Write out code to move floating-point arguments into or out of
6220 general registers. FP_CODE is the code describing which arguments
6221 are present (see the comment above the definition of CUMULATIVE_ARGS
6222 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
6225 mips_output_args_xfer (int fp_code, char direction)
6227 unsigned int gparg, fparg, f;
6228 CUMULATIVE_ARGS cum;
6230 /* This code only works for o32 and o64. */
6231 gcc_assert (TARGET_OLDABI);
6233 mips_init_cumulative_args (&cum, NULL);
6235 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
6237 enum machine_mode mode;
6238 struct mips_arg_info info;
6242 else if ((f & 3) == 2)
6247 mips_get_arg_info (&info, &cum, mode, NULL, true);
6248 gparg = mips_arg_regno (&info, false);
6249 fparg = mips_arg_regno (&info, true);
6252 mips_output_32bit_xfer (direction, gparg, fparg);
6254 mips_output_64bit_xfer (direction, gparg, fparg);
6256 mips_function_arg_advance (pack_cumulative_args (&cum), mode, NULL, true);
6260 /* Write a MIPS16 stub for the current function. This stub is used
6261 for functions which take arguments in the floating-point registers.
6262 It is normal-mode code that moves the floating-point arguments
6263 into the general registers and then jumps to the MIPS16 code. */
6266 mips16_build_function_stub (void)
6268 const char *fnname, *alias_name, *separator;
6269 char *secname, *stubname;
6274 /* Create the name of the stub, and its unique section. */
6275 symbol = XEXP (DECL_RTL (current_function_decl), 0);
6276 alias = mips16_local_alias (symbol);
6278 fnname = targetm.strip_name_encoding (XSTR (symbol, 0));
6279 alias_name = targetm.strip_name_encoding (XSTR (alias, 0));
6280 secname = ACONCAT ((".mips16.fn.", fnname, NULL));
6281 stubname = ACONCAT (("__fn_stub_", fnname, NULL));
6283 /* Build a decl for the stub. */
6284 stubdecl = build_decl (BUILTINS_LOCATION,
6285 FUNCTION_DECL, get_identifier (stubname),
6286 build_function_type_list (void_type_node, NULL_TREE));
6287 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
6288 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
6289 RESULT_DECL, NULL_TREE, void_type_node);
6291 /* Output a comment. */
6292 fprintf (asm_out_file, "\t# Stub function for %s (",
6293 current_function_name ());
6295 for (f = (unsigned int) crtl->args.info.fp_code; f != 0; f >>= 2)
6297 fprintf (asm_out_file, "%s%s", separator,
6298 (f & 3) == 1 ? "float" : "double");
6301 fprintf (asm_out_file, ")\n");
6303 /* Start the function definition. */
6304 assemble_start_function (stubdecl, stubname);
6305 mips_start_function_definition (stubname, false);
6307 /* If generating pic2 code, either set up the global pointer or
6309 if (TARGET_ABICALLS_PIC2)
6311 if (TARGET_ABSOLUTE_ABICALLS)
6312 fprintf (asm_out_file, "\t.option\tpic0\n");
6315 output_asm_insn ("%(.cpload\t%^%)", NULL);
6316 /* Emit an R_MIPS_NONE relocation to tell the linker what the
6317 target function is. Use a local GOT access when loading the
6318 symbol, to cut down on the number of unnecessary GOT entries
6319 for stubs that aren't needed. */
6320 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol);
6325 /* Load the address of the MIPS16 function into $25. Do this first so
6326 that targets with coprocessor interlocks can use an MFC1 to fill the
6328 output_asm_insn ("la\t%^,%0", &symbol);
6330 /* Move the arguments from floating-point registers to general registers. */
6331 mips_output_args_xfer (crtl->args.info.fp_code, 'f');
6333 /* Jump to the MIPS16 function. */
6334 output_asm_insn ("jr\t%^", NULL);
6336 if (TARGET_ABICALLS_PIC2 && TARGET_ABSOLUTE_ABICALLS)
6337 fprintf (asm_out_file, "\t.option\tpic2\n");
6339 mips_end_function_definition (stubname);
6341 /* If the linker needs to create a dynamic symbol for the target
6342 function, it will associate the symbol with the stub (which,
6343 unlike the target function, follows the proper calling conventions).
6344 It is therefore useful to have a local alias for the target function,
6345 so that it can still be identified as MIPS16 code. As an optimization,
6346 this symbol can also be used for indirect MIPS16 references from
6347 within this file. */
6348 ASM_OUTPUT_DEF (asm_out_file, alias_name, fnname);
6350 switch_to_section (function_section (current_function_decl));
6353 /* The current function is a MIPS16 function that returns a value in an FPR.
6354 Copy the return value from its soft-float to its hard-float location.
6355 libgcc2 has special non-MIPS16 helper functions for each case. */
6358 mips16_copy_fpr_return_value (void)
6360 rtx fn, insn, retval;
6362 enum machine_mode return_mode;
6365 return_type = DECL_RESULT (current_function_decl);
6366 return_mode = DECL_MODE (return_type);
6368 name = ACONCAT (("__mips16_ret_",
6369 mips16_call_stub_mode_suffix (return_mode),
6371 fn = mips16_stub_function (name);
6373 /* The function takes arguments in $2 (and possibly $3), so calls
6374 to it cannot be lazily bound. */
6375 SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_BIND_NOW;
6377 /* Model the call as something that takes the GPR return value as
6378 argument and returns an "updated" value. */
6379 retval = gen_rtx_REG (return_mode, GP_RETURN);
6380 insn = mips_expand_call (MIPS_CALL_EPILOGUE, retval, fn,
6381 const0_rtx, NULL_RTX, false);
6382 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), retval);
6385 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
6386 RETVAL is the location of the return value, or null if this is
6387 a "call" rather than a "call_value". ARGS_SIZE is the size of the
6388 arguments and FP_CODE is the code built by mips_function_arg;
6389 see the comment before the fp_code field in CUMULATIVE_ARGS for details.
6391 There are three alternatives:
6393 - If a stub was needed, emit the call and return the call insn itself.
6395 - If we can avoid using a stub by redirecting the call, set *FN_PTR
6396 to the new target and return null.
6398 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
6401 A stub is needed for calls to functions that, in normal mode,
6402 receive arguments in FPRs or return values in FPRs. The stub
6403 copies the arguments from their soft-float positions to their
6404 hard-float positions, calls the real function, then copies the
6405 return value from its hard-float position to its soft-float
6408 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
6409 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
6410 automatically redirects the JAL to the stub, otherwise the JAL
6411 continues to call FN directly. */
6414 mips16_build_call_stub (rtx retval, rtx *fn_ptr, rtx args_size, int fp_code)
6418 struct mips16_stub *l;
6421 /* We don't need to do anything if we aren't in MIPS16 mode, or if
6422 we were invoked with the -msoft-float option. */
6423 if (!TARGET_MIPS16 || TARGET_SOFT_FLOAT_ABI)
6426 /* Figure out whether the value might come back in a floating-point
6428 fp_ret_p = retval && mips_return_mode_in_fpr_p (GET_MODE (retval));
6430 /* We don't need to do anything if there were no floating-point
6431 arguments and the value will not be returned in a floating-point
6433 if (fp_code == 0 && !fp_ret_p)
6436 /* We don't need to do anything if this is a call to a special
6437 MIPS16 support function. */
6439 if (mips16_stub_function_p (fn))
6442 /* If we're calling a locally-defined MIPS16 function, we know that
6443 it will return values in both the "soft-float" and "hard-float"
6444 registers. There is no need to use a stub to move the latter
6446 if (fp_code == 0 && mips16_local_function_p (fn))
6449 /* This code will only work for o32 and o64 abis. The other ABI's
6450 require more sophisticated support. */
6451 gcc_assert (TARGET_OLDABI);
6453 /* If we're calling via a function pointer, use one of the magic
6454 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
6455 Each stub expects the function address to arrive in register $2. */
6456 if (GET_CODE (fn) != SYMBOL_REF
6457 || !call_insn_operand (fn, VOIDmode))
6460 rtx stub_fn, insn, addr;
6463 /* If this is a locally-defined and locally-binding function,
6464 avoid the stub by calling the local alias directly. */
6465 if (mips16_local_function_p (fn))
6467 *fn_ptr = mips16_local_alias (fn);
6471 /* Create a SYMBOL_REF for the libgcc.a function. */
6473 sprintf (buf, "__mips16_call_stub_%s_%d",
6474 mips16_call_stub_mode_suffix (GET_MODE (retval)),
6477 sprintf (buf, "__mips16_call_stub_%d", fp_code);
6478 stub_fn = mips16_stub_function (buf);
6480 /* The function uses $2 as an argument, so calls to it
6481 cannot be lazily bound. */
6482 SYMBOL_REF_FLAGS (stub_fn) |= SYMBOL_FLAG_BIND_NOW;
6484 /* Load the target function into $2. */
6485 addr = gen_rtx_REG (Pmode, GP_REG_FIRST + 2);
6486 lazy_p = mips_load_call_address (MIPS_CALL_NORMAL, addr, fn);
6488 /* Emit the call. */
6489 insn = mips_expand_call (MIPS_CALL_NORMAL, retval, stub_fn,
6490 args_size, NULL_RTX, lazy_p);
6492 /* Tell GCC that this call does indeed use the value of $2. */
6493 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), addr);
6495 /* If we are handling a floating-point return value, we need to
6496 save $18 in the function prologue. Putting a note on the
6497 call will mean that df_regs_ever_live_p ($18) will be true if the
6498 call is not eliminated, and we can check that in the prologue
6501 CALL_INSN_FUNCTION_USAGE (insn) =
6502 gen_rtx_EXPR_LIST (VOIDmode,
6503 gen_rtx_CLOBBER (VOIDmode,
6504 gen_rtx_REG (word_mode, 18)),
6505 CALL_INSN_FUNCTION_USAGE (insn));
6510 /* We know the function we are going to call. If we have already
6511 built a stub, we don't need to do anything further. */
6512 fnname = targetm.strip_name_encoding (XSTR (fn, 0));
6513 for (l = mips16_stubs; l != NULL; l = l->next)
6514 if (strcmp (l->name, fnname) == 0)
6519 const char *separator;
6520 char *secname, *stubname;
6521 tree stubid, stubdecl;
6524 /* If the function does not return in FPRs, the special stub
6528 If the function does return in FPRs, the stub section is named
6529 .mips16.call.fp.FNNAME
6531 Build a decl for the stub. */
6532 secname = ACONCAT ((".mips16.call.", fp_ret_p ? "fp." : "",
6534 stubname = ACONCAT (("__call_stub_", fp_ret_p ? "fp_" : "",
6536 stubid = get_identifier (stubname);
6537 stubdecl = build_decl (BUILTINS_LOCATION,
6538 FUNCTION_DECL, stubid,
6539 build_function_type_list (void_type_node,
6541 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
6542 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
6543 RESULT_DECL, NULL_TREE,
6546 /* Output a comment. */
6547 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
6549 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
6553 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
6555 fprintf (asm_out_file, "%s%s", separator,
6556 (f & 3) == 1 ? "float" : "double");
6559 fprintf (asm_out_file, ")\n");
6561 /* Start the function definition. */
6562 assemble_start_function (stubdecl, stubname);
6563 mips_start_function_definition (stubname, false);
6567 fprintf (asm_out_file, "\t.cfi_startproc\n");
6569 /* Create a fake CFA 4 bytes below the stack pointer.
6570 This works around unwinders (like libgcc's) that expect
6571 the CFA for non-signal frames to be unique. */
6572 fprintf (asm_out_file, "\t.cfi_def_cfa 29,-4\n");
6574 /* "Save" $sp in itself so we don't use the fake CFA.
6575 This is: DW_CFA_val_expression r29, { DW_OP_reg29 }. */
6576 fprintf (asm_out_file, "\t.cfi_escape 0x16,29,1,0x6d\n");
6580 /* Load the address of the MIPS16 function into $25. Do this
6581 first so that targets with coprocessor interlocks can use
6582 an MFC1 to fill the delay slot. */
6583 if (TARGET_EXPLICIT_RELOCS)
6585 output_asm_insn ("lui\t%^,%%hi(%0)", &fn);
6586 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn);
6589 output_asm_insn ("la\t%^,%0", &fn);
6592 /* Move the arguments from general registers to floating-point
6594 mips_output_args_xfer (fp_code, 't');
6598 /* Save the return address in $18 and call the non-MIPS16 function.
6599 The stub's caller knows that $18 might be clobbered, even though
6600 $18 is usually a call-saved register. */
6601 fprintf (asm_out_file, "\tmove\t%s,%s\n",
6602 reg_names[GP_REG_FIRST + 18], reg_names[RETURN_ADDR_REGNUM]);
6603 output_asm_insn (MIPS_CALL ("jal", &fn, 0, -1), &fn);
6604 fprintf (asm_out_file, "\t.cfi_register 31,18\n");
6606 /* Move the result from floating-point registers to
6607 general registers. */
6608 switch (GET_MODE (retval))
6611 mips_output_32bit_xfer ('f', GP_RETURN + TARGET_BIG_ENDIAN,
6613 ? FP_REG_FIRST + MAX_FPRS_PER_FMT
6615 mips_output_32bit_xfer ('f', GP_RETURN + TARGET_LITTLE_ENDIAN,
6616 TARGET_LITTLE_ENDIAN
6617 ? FP_REG_FIRST + MAX_FPRS_PER_FMT
6619 if (GET_MODE (retval) == SCmode && TARGET_64BIT)
6621 /* On 64-bit targets, complex floats are returned in
6622 a single GPR, such that "sd" on a suitably-aligned
6623 target would store the value correctly. */
6624 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
6625 reg_names[GP_RETURN + TARGET_BIG_ENDIAN],
6626 reg_names[GP_RETURN + TARGET_BIG_ENDIAN]);
6627 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
6628 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN],
6629 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN]);
6630 fprintf (asm_out_file, "\tdsrl\t%s,%s,32\n",
6631 reg_names[GP_RETURN + TARGET_BIG_ENDIAN],
6632 reg_names[GP_RETURN + TARGET_BIG_ENDIAN]);
6633 fprintf (asm_out_file, "\tor\t%s,%s,%s\n",
6634 reg_names[GP_RETURN],
6635 reg_names[GP_RETURN],
6636 reg_names[GP_RETURN + 1]);
6641 mips_output_32bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6645 mips_output_64bit_xfer ('f', GP_RETURN + (8 / UNITS_PER_WORD),
6646 FP_REG_FIRST + MAX_FPRS_PER_FMT);
6650 mips_output_64bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6656 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 18]);
6657 fprintf (asm_out_file, "\t.cfi_endproc\n");
6661 /* Jump to the previously-loaded address. */
6662 output_asm_insn ("jr\t%^", NULL);
6665 #ifdef ASM_DECLARE_FUNCTION_SIZE
6666 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
6669 mips_end_function_definition (stubname);
6671 /* Record this stub. */
6672 l = XNEW (struct mips16_stub);
6673 l->name = xstrdup (fnname);
6674 l->fp_ret_p = fp_ret_p;
6675 l->next = mips16_stubs;
6679 /* If we expect a floating-point return value, but we've built a
6680 stub which does not expect one, then we're in trouble. We can't
6681 use the existing stub, because it won't handle the floating-point
6682 value. We can't build a new stub, because the linker won't know
6683 which stub to use for the various calls in this object file.
6684 Fortunately, this case is illegal, since it means that a function
6685 was declared in two different ways in a single compilation. */
6686 if (fp_ret_p && !l->fp_ret_p)
6687 error ("cannot handle inconsistent calls to %qs", fnname);
6689 if (retval == NULL_RTX)
6690 insn = gen_call_internal_direct (fn, args_size);
6692 insn = gen_call_value_internal_direct (retval, fn, args_size);
6693 insn = mips_emit_call_insn (insn, fn, fn, false);
6695 /* If we are calling a stub which handles a floating-point return
6696 value, we need to arrange to save $18 in the prologue. We do this
6697 by marking the function call as using the register. The prologue
6698 will later see that it is used, and emit code to save it. */
6700 CALL_INSN_FUNCTION_USAGE (insn) =
6701 gen_rtx_EXPR_LIST (VOIDmode,
6702 gen_rtx_CLOBBER (VOIDmode,
6703 gen_rtx_REG (word_mode, 18)),
6704 CALL_INSN_FUNCTION_USAGE (insn));
6709 /* Expand a call of type TYPE. RESULT is where the result will go (null
6710 for "call"s and "sibcall"s), ADDR is the address of the function,
6711 ARGS_SIZE is the size of the arguments and AUX is the value passed
6712 to us by mips_function_arg. LAZY_P is true if this call already
6713 involves a lazily-bound function address (such as when calling
6714 functions through a MIPS16 hard-float stub).
6716 Return the call itself. */
6719 mips_expand_call (enum mips_call_type type, rtx result, rtx addr,
6720 rtx args_size, rtx aux, bool lazy_p)
6722 rtx orig_addr, pattern, insn;
6725 fp_code = aux == 0 ? 0 : (int) GET_MODE (aux);
6726 insn = mips16_build_call_stub (result, &addr, args_size, fp_code);
6729 gcc_assert (!lazy_p && type == MIPS_CALL_NORMAL);
6734 if (!call_insn_operand (addr, VOIDmode))
6736 if (type == MIPS_CALL_EPILOGUE)
6737 addr = MIPS_EPILOGUE_TEMP (Pmode);
6739 addr = gen_reg_rtx (Pmode);
6740 lazy_p |= mips_load_call_address (type, addr, orig_addr);
6745 rtx (*fn) (rtx, rtx);
6747 if (type == MIPS_CALL_SIBCALL)
6748 fn = gen_sibcall_internal;
6750 fn = gen_call_internal;
6752 pattern = fn (addr, args_size);
6754 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
6756 /* Handle return values created by mips_return_fpr_pair. */
6757 rtx (*fn) (rtx, rtx, rtx, rtx);
6760 if (type == MIPS_CALL_SIBCALL)
6761 fn = gen_sibcall_value_multiple_internal;
6763 fn = gen_call_value_multiple_internal;
6765 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
6766 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
6767 pattern = fn (reg1, addr, args_size, reg2);
6771 rtx (*fn) (rtx, rtx, rtx);
6773 if (type == MIPS_CALL_SIBCALL)
6774 fn = gen_sibcall_value_internal;
6776 fn = gen_call_value_internal;
6778 /* Handle return values created by mips_return_fpr_single. */
6779 if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 1)
6780 result = XEXP (XVECEXP (result, 0, 0), 0);
6781 pattern = fn (result, addr, args_size);
6784 return mips_emit_call_insn (pattern, orig_addr, addr, lazy_p);
6787 /* Split call instruction INSN into a $gp-clobbering call and
6788 (where necessary) an instruction to restore $gp from its save slot.
6789 CALL_PATTERN is the pattern of the new call. */
6792 mips_split_call (rtx insn, rtx call_pattern)
6794 emit_call_insn (call_pattern);
6795 if (!find_reg_note (insn, REG_NORETURN, 0))
6796 /* Pick a temporary register that is suitable for both MIPS16 and
6797 non-MIPS16 code. $4 and $5 are used for returning complex double
6798 values in soft-float code, so $6 is the first suitable candidate. */
6799 mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode, GP_ARG_FIRST + 2));
6802 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
6805 mips_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
6807 if (!TARGET_SIBCALLS)
6810 /* Interrupt handlers need special epilogue code and therefore can't
6812 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
6815 /* We can't do a sibcall if the called function is a MIPS16 function
6816 because there is no direct "jx" instruction equivalent to "jalx" to
6817 switch the ISA mode. We only care about cases where the sibling
6818 and normal calls would both be direct. */
6820 && mips_use_mips16_mode_p (decl)
6821 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
6824 /* When -minterlink-mips16 is in effect, assume that non-locally-binding
6825 functions could be MIPS16 ones unless an attribute explicitly tells
6827 if (TARGET_INTERLINK_MIPS16
6829 && (DECL_EXTERNAL (decl) || !targetm.binds_local_p (decl))
6830 && !mips_nomips16_decl_p (decl)
6831 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
6838 /* Emit code to move general operand SRC into condition-code
6839 register DEST given that SCRATCH is a scratch TFmode FPR.
6846 where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */
6849 mips_expand_fcc_reload (rtx dest, rtx src, rtx scratch)
6853 /* Change the source to SFmode. */
6855 src = adjust_address (src, SFmode, 0);
6856 else if (REG_P (src) || GET_CODE (src) == SUBREG)
6857 src = gen_rtx_REG (SFmode, true_regnum (src));
6859 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
6860 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + MAX_FPRS_PER_FMT);
6862 mips_emit_move (copy_rtx (fp1), src);
6863 mips_emit_move (copy_rtx (fp2), CONST0_RTX (SFmode));
6864 emit_insn (gen_slt_sf (dest, fp2, fp1));
6867 /* Implement MOVE_BY_PIECES_P. */
6870 mips_move_by_pieces_p (unsigned HOST_WIDE_INT size, unsigned int align)
6874 /* movmemsi is meant to generate code that is at least as good as
6875 move_by_pieces. However, movmemsi effectively uses a by-pieces
6876 implementation both for moves smaller than a word and for
6877 word-aligned moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT
6878 bytes. We should allow the tree-level optimisers to do such
6879 moves by pieces, as it often exposes other optimization
6880 opportunities. We might as well continue to use movmemsi at
6881 the rtl level though, as it produces better code when
6882 scheduling is disabled (such as at -O). */
6883 if (currently_expanding_to_rtl)
6885 if (align < BITS_PER_WORD)
6886 return size < UNITS_PER_WORD;
6887 return size <= MIPS_MAX_MOVE_BYTES_STRAIGHT;
6889 /* The default value. If this becomes a target hook, we should
6890 call the default definition instead. */
6891 return (move_by_pieces_ninsns (size, align, MOVE_MAX_PIECES + 1)
6892 < (unsigned int) MOVE_RATIO (optimize_insn_for_speed_p ()));
6895 /* Implement STORE_BY_PIECES_P. */
6898 mips_store_by_pieces_p (unsigned HOST_WIDE_INT size, unsigned int align)
6900 /* Storing by pieces involves moving constants into registers
6901 of size MIN (ALIGN, BITS_PER_WORD), then storing them.
6902 We need to decide whether it is cheaper to load the address of
6903 constant data into a register and use a block move instead. */
6905 /* If the data is only byte aligned, then:
6907 (a1) A block move of less than 4 bytes would involve three 3 LBs and
6908 3 SBs. We might as well use 3 single-instruction LIs and 3 SBs
6911 (a2) A block move of 4 bytes from aligned source data can use an
6912 LW/SWL/SWR sequence. This is often better than the 4 LIs and
6913 4 SBs that we would generate when storing by pieces. */
6914 if (align <= BITS_PER_UNIT)
6917 /* If the data is 2-byte aligned, then:
6919 (b1) A block move of less than 4 bytes would use a combination of LBs,
6920 LHs, SBs and SHs. We get better code by using single-instruction
6921 LIs, SBs and SHs instead.
6923 (b2) A block move of 4 bytes from aligned source data would again use
6924 an LW/SWL/SWR sequence. In most cases, loading the address of
6925 the source data would require at least one extra instruction.
6926 It is often more efficient to use 2 single-instruction LIs and
6929 (b3) A block move of up to 3 additional bytes would be like (b1).
6931 (b4) A block move of 8 bytes from aligned source data can use two
6932 LW/SWL/SWR sequences or a single LD/SDL/SDR sequence. Both
6933 sequences are better than the 4 LIs and 4 SHs that we'd generate
6934 when storing by pieces.
6936 The reasoning for higher alignments is similar:
6938 (c1) A block move of less than 4 bytes would be the same as (b1).
6940 (c2) A block move of 4 bytes would use an LW/SW sequence. Again,
6941 loading the address of the source data would typically require
6942 at least one extra instruction. It is generally better to use
6945 (c3) A block move of up to 3 additional bytes would be like (b1).
6947 (c4) A block move of 8 bytes can use two LW/SW sequences or a single
6948 LD/SD sequence, and in these cases we've traditionally preferred
6949 the memory copy over the more bulky constant moves. */
6953 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
6954 Assume that the areas do not overlap. */
6957 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
6959 HOST_WIDE_INT offset, delta;
6960 unsigned HOST_WIDE_INT bits;
6962 enum machine_mode mode;
6965 /* Work out how many bits to move at a time. If both operands have
6966 half-word alignment, it is usually better to move in half words.
6967 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
6968 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
6969 Otherwise move word-sized chunks. */
6970 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
6971 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
6972 bits = BITS_PER_WORD / 2;
6974 bits = BITS_PER_WORD;
6976 mode = mode_for_size (bits, MODE_INT, 0);
6977 delta = bits / BITS_PER_UNIT;
6979 /* Allocate a buffer for the temporary registers. */
6980 regs = XALLOCAVEC (rtx, length / delta);
6982 /* Load as many BITS-sized chunks as possible. Use a normal load if
6983 the source has enough alignment, otherwise use left/right pairs. */
6984 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
6986 regs[i] = gen_reg_rtx (mode);
6987 if (MEM_ALIGN (src) >= bits)
6988 mips_emit_move (regs[i], adjust_address (src, mode, offset));
6991 rtx part = adjust_address (src, BLKmode, offset);
6992 if (!mips_expand_ext_as_unaligned_load (regs[i], part, bits, 0, 0))
6997 /* Copy the chunks to the destination. */
6998 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
6999 if (MEM_ALIGN (dest) >= bits)
7000 mips_emit_move (adjust_address (dest, mode, offset), regs[i]);
7003 rtx part = adjust_address (dest, BLKmode, offset);
7004 if (!mips_expand_ins_as_unaligned_store (part, regs[i], bits, 0))
7008 /* Mop up any left-over bytes. */
7009 if (offset < length)
7011 src = adjust_address (src, BLKmode, offset);
7012 dest = adjust_address (dest, BLKmode, offset);
7013 move_by_pieces (dest, src, length - offset,
7014 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
7018 /* Helper function for doing a loop-based block operation on memory
7019 reference MEM. Each iteration of the loop will operate on LENGTH
7022 Create a new base register for use within the loop and point it to
7023 the start of MEM. Create a new memory reference that uses this
7024 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
7027 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
7028 rtx *loop_reg, rtx *loop_mem)
7030 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
7032 /* Although the new mem does not refer to a known location,
7033 it does keep up to LENGTH bytes of alignment. */
7034 *loop_mem = change_address (mem, BLKmode, *loop_reg);
7035 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
7038 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
7039 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
7040 the memory regions do not overlap. */
7043 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length,
7044 HOST_WIDE_INT bytes_per_iter)
7046 rtx label, src_reg, dest_reg, final_src, test;
7047 HOST_WIDE_INT leftover;
7049 leftover = length % bytes_per_iter;
7052 /* Create registers and memory references for use within the loop. */
7053 mips_adjust_block_mem (src, bytes_per_iter, &src_reg, &src);
7054 mips_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest);
7056 /* Calculate the value that SRC_REG should have after the last iteration
7058 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
7061 /* Emit the start of the loop. */
7062 label = gen_label_rtx ();
7065 /* Emit the loop body. */
7066 mips_block_move_straight (dest, src, bytes_per_iter);
7068 /* Move on to the next block. */
7069 mips_emit_move (src_reg, plus_constant (Pmode, src_reg, bytes_per_iter));
7070 mips_emit_move (dest_reg, plus_constant (Pmode, dest_reg, bytes_per_iter));
7072 /* Emit the loop condition. */
7073 test = gen_rtx_NE (VOIDmode, src_reg, final_src);
7074 if (Pmode == DImode)
7075 emit_jump_insn (gen_cbranchdi4 (test, src_reg, final_src, label));
7077 emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label));
7079 /* Mop up any left-over bytes. */
7081 mips_block_move_straight (dest, src, leftover);
7084 /* Expand a movmemsi instruction, which copies LENGTH bytes from
7085 memory reference SRC to memory reference DEST. */
7088 mips_expand_block_move (rtx dest, rtx src, rtx length)
7090 if (CONST_INT_P (length))
7092 if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)
7094 mips_block_move_straight (dest, src, INTVAL (length));
7099 mips_block_move_loop (dest, src, INTVAL (length),
7100 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER);
7107 /* Expand a loop of synci insns for the address range [BEGIN, END). */
7110 mips_expand_synci_loop (rtx begin, rtx end)
7112 rtx inc, label, end_label, cmp_result, mask, length;
7114 /* Create end_label. */
7115 end_label = gen_label_rtx ();
7117 /* Check if begin equals end. */
7118 cmp_result = gen_rtx_EQ (VOIDmode, begin, end);
7119 emit_jump_insn (gen_condjump (cmp_result, end_label));
7121 /* Load INC with the cache line size (rdhwr INC,$1). */
7122 inc = gen_reg_rtx (Pmode);
7123 emit_insn (PMODE_INSN (gen_rdhwr_synci_step, (inc)));
7125 /* Check if inc is 0. */
7126 cmp_result = gen_rtx_EQ (VOIDmode, inc, const0_rtx);
7127 emit_jump_insn (gen_condjump (cmp_result, end_label));
7129 /* Calculate mask. */
7130 mask = mips_force_unary (Pmode, NEG, inc);
7132 /* Mask out begin by mask. */
7133 begin = mips_force_binary (Pmode, AND, begin, mask);
7135 /* Calculate length. */
7136 length = mips_force_binary (Pmode, MINUS, end, begin);
7138 /* Loop back to here. */
7139 label = gen_label_rtx ();
7142 emit_insn (gen_synci (begin));
7144 /* Update length. */
7145 mips_emit_binary (MINUS, length, length, inc);
7148 mips_emit_binary (PLUS, begin, begin, inc);
7150 /* Check if length is greater than 0. */
7151 cmp_result = gen_rtx_GT (VOIDmode, length, const0_rtx);
7152 emit_jump_insn (gen_condjump (cmp_result, label));
7154 emit_label (end_label);
7157 /* Expand a QI or HI mode atomic memory operation.
7159 GENERATOR contains a pointer to the gen_* function that generates
7160 the SI mode underlying atomic operation using masks that we
7163 RESULT is the return register for the operation. Its value is NULL
7166 MEM is the location of the atomic access.
7168 OLDVAL is the first operand for the operation.
7170 NEWVAL is the optional second operand for the operation. Its value
7171 is NULL if unused. */
7174 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator,
7175 rtx result, rtx mem, rtx oldval, rtx newval)
7177 rtx orig_addr, memsi_addr, memsi, shift, shiftsi, unshifted_mask;
7178 rtx unshifted_mask_reg, mask, inverted_mask, si_op;
7180 enum machine_mode mode;
7182 mode = GET_MODE (mem);
7184 /* Compute the address of the containing SImode value. */
7185 orig_addr = force_reg (Pmode, XEXP (mem, 0));
7186 memsi_addr = mips_force_binary (Pmode, AND, orig_addr,
7187 force_reg (Pmode, GEN_INT (-4)));
7189 /* Create a memory reference for it. */
7190 memsi = gen_rtx_MEM (SImode, memsi_addr);
7191 set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER);
7192 MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem);
7194 /* Work out the byte offset of the QImode or HImode value,
7195 counting from the least significant byte. */
7196 shift = mips_force_binary (Pmode, AND, orig_addr, GEN_INT (3));
7197 if (TARGET_BIG_ENDIAN)
7198 mips_emit_binary (XOR, shift, shift, GEN_INT (mode == QImode ? 3 : 2));
7200 /* Multiply by eight to convert the shift value from bytes to bits. */
7201 mips_emit_binary (ASHIFT, shift, shift, GEN_INT (3));
7203 /* Make the final shift an SImode value, so that it can be used in
7204 SImode operations. */
7205 shiftsi = force_reg (SImode, gen_lowpart (SImode, shift));
7207 /* Set MASK to an inclusive mask of the QImode or HImode value. */
7208 unshifted_mask = GEN_INT (GET_MODE_MASK (mode));
7209 unshifted_mask_reg = force_reg (SImode, unshifted_mask);
7210 mask = mips_force_binary (SImode, ASHIFT, unshifted_mask_reg, shiftsi);
7212 /* Compute the equivalent exclusive mask. */
7213 inverted_mask = gen_reg_rtx (SImode);
7214 emit_insn (gen_rtx_SET (VOIDmode, inverted_mask,
7215 gen_rtx_NOT (SImode, mask)));
7217 /* Shift the old value into place. */
7218 if (oldval != const0_rtx)
7220 oldval = convert_modes (SImode, mode, oldval, true);
7221 oldval = force_reg (SImode, oldval);
7222 oldval = mips_force_binary (SImode, ASHIFT, oldval, shiftsi);
7225 /* Do the same for the new value. */
7226 if (newval && newval != const0_rtx)
7228 newval = convert_modes (SImode, mode, newval, true);
7229 newval = force_reg (SImode, newval);
7230 newval = mips_force_binary (SImode, ASHIFT, newval, shiftsi);
7233 /* Do the SImode atomic access. */
7235 res = gen_reg_rtx (SImode);
7237 si_op = generator.fn_6 (res, memsi, mask, inverted_mask, oldval, newval);
7239 si_op = generator.fn_5 (res, memsi, mask, inverted_mask, oldval);
7241 si_op = generator.fn_4 (memsi, mask, inverted_mask, oldval);
7247 /* Shift and convert the result. */
7248 mips_emit_binary (AND, res, res, mask);
7249 mips_emit_binary (LSHIFTRT, res, res, shiftsi);
7250 mips_emit_move (result, gen_lowpart (GET_MODE (result), res));
7254 /* Return true if it is possible to use left/right accesses for a
7255 bitfield of WIDTH bits starting BITPOS bits into *OP. When
7256 returning true, update *OP, *LEFT and *RIGHT as follows:
7258 *OP is a BLKmode reference to the whole field.
7260 *LEFT is a QImode reference to the first byte if big endian or
7261 the last byte if little endian. This address can be used in the
7262 left-side instructions (LWL, SWL, LDL, SDL).
7264 *RIGHT is a QImode reference to the opposite end of the field and
7265 can be used in the patterning right-side instruction. */
7268 mips_get_unaligned_mem (rtx *op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos,
7269 rtx *left, rtx *right)
7273 /* Check that the operand really is a MEM. Not all the extv and
7274 extzv predicates are checked. */
7278 /* Check that the size is valid. */
7279 if (width != 32 && (!TARGET_64BIT || width != 64))
7282 /* We can only access byte-aligned values. Since we are always passed
7283 a reference to the first byte of the field, it is not necessary to
7284 do anything with BITPOS after this check. */
7285 if (bitpos % BITS_PER_UNIT != 0)
7288 /* Reject aligned bitfields: we want to use a normal load or store
7289 instead of a left/right pair. */
7290 if (MEM_ALIGN (*op) >= width)
7293 /* Create a copy of *OP that refers to the whole field. This also has
7294 the effect of legitimizing *OP's address for BLKmode, possibly
7296 *op = copy_rtx (adjust_address (*op, BLKmode, 0));
7297 set_mem_size (*op, width / BITS_PER_UNIT);
7299 /* Get references to both ends of the field. We deliberately don't
7300 use the original QImode *OP for FIRST since the new BLKmode one
7301 might have a simpler address. */
7302 first = adjust_address (*op, QImode, 0);
7303 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
7305 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
7306 correspond to the MSB and RIGHT to the LSB. */
7307 if (TARGET_BIG_ENDIAN)
7308 *left = first, *right = last;
7310 *left = last, *right = first;
7315 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
7316 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
7317 the operation is the equivalent of:
7319 (set DEST (*_extract SRC WIDTH BITPOS))
7321 Return true on success. */
7324 mips_expand_ext_as_unaligned_load (rtx dest, rtx src, HOST_WIDE_INT width,
7325 HOST_WIDE_INT bitpos, bool unsigned_p)
7327 rtx left, right, temp;
7328 rtx dest1 = NULL_RTX;
7330 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
7331 be a paradoxical word_mode subreg. This is the only case in which
7332 we allow the destination to be larger than the source. */
7333 if (GET_CODE (dest) == SUBREG
7334 && GET_MODE (dest) == DImode
7335 && GET_MODE (SUBREG_REG (dest)) == SImode)
7336 dest = SUBREG_REG (dest);
7338 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
7339 be a DImode, create a new temp and emit a zero extend at the end. */
7340 if (GET_MODE (dest) == DImode
7342 && GET_MODE_BITSIZE (SImode) == width)
7345 dest = gen_reg_rtx (SImode);
7348 /* After the above adjustment, the destination must be the same
7349 width as the source. */
7350 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
7353 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
7356 temp = gen_reg_rtx (GET_MODE (dest));
7357 if (GET_MODE (dest) == DImode)
7359 emit_insn (gen_mov_ldl (temp, src, left));
7360 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
7364 emit_insn (gen_mov_lwl (temp, src, left));
7365 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
7368 /* If we were loading 32bits and the original register was DI then
7369 sign/zero extend into the orignal dest. */
7373 emit_insn (gen_zero_extendsidi2 (dest1, dest));
7375 emit_insn (gen_extendsidi2 (dest1, dest));
7380 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
7381 BITPOS and SRC are the operands passed to the expander; the operation
7382 is the equivalent of:
7384 (set (zero_extract DEST WIDTH BITPOS) SRC)
7386 Return true on success. */
7389 mips_expand_ins_as_unaligned_store (rtx dest, rtx src, HOST_WIDE_INT width,
7390 HOST_WIDE_INT bitpos)
7393 enum machine_mode mode;
7395 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
7398 mode = mode_for_size (width, MODE_INT, 0);
7399 src = gen_lowpart (mode, src);
7402 emit_insn (gen_mov_sdl (dest, src, left));
7403 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
7407 emit_insn (gen_mov_swl (dest, src, left));
7408 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
7413 /* Return true if X is a MEM with the same size as MODE. */
7416 mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
7419 && MEM_SIZE_KNOWN_P (x)
7420 && MEM_SIZE (x) == GET_MODE_SIZE (mode));
7423 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
7424 source of an "ext" instruction or the destination of an "ins"
7425 instruction. OP must be a register operand and the following
7426 conditions must hold:
7428 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
7429 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7430 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7432 Also reject lengths equal to a word as they are better handled
7433 by the move patterns. */
7436 mips_use_ins_ext_p (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos)
7438 if (!ISA_HAS_EXT_INS
7439 || !register_operand (op, VOIDmode)
7440 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
7443 if (!IN_RANGE (width, 1, GET_MODE_BITSIZE (GET_MODE (op)) - 1))
7446 if (bitpos < 0 || bitpos + width > GET_MODE_BITSIZE (GET_MODE (op)))
7452 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
7453 operation if MAXLEN is the maxium length of consecutive bits that
7454 can make up MASK. MODE is the mode of the operation. See
7455 mask_low_and_shift_len for the actual definition. */
7458 mask_low_and_shift_p (enum machine_mode mode, rtx mask, rtx shift, int maxlen)
7460 return IN_RANGE (mask_low_and_shift_len (mode, mask, shift), 1, maxlen);
7463 /* Return true iff OP1 and OP2 are valid operands together for the
7464 *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider,
7465 see the table in the comment before the pattern. */
7468 and_operands_ok (enum machine_mode mode, rtx op1, rtx op2)
7470 return (memory_operand (op1, mode)
7471 ? and_load_operand (op2, mode)
7472 : and_reg_operand (op2, mode));
7475 /* The canonical form of a mask-low-and-shift-left operation is
7476 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
7477 cleared. Thus we need to shift MASK to the right before checking if it
7478 is a valid mask value. MODE is the mode of the operation. If true
7479 return the length of the mask, otherwise return -1. */
7482 mask_low_and_shift_len (enum machine_mode mode, rtx mask, rtx shift)
7484 HOST_WIDE_INT shval;
7486 shval = INTVAL (shift) & (GET_MODE_BITSIZE (mode) - 1);
7487 return exact_log2 ((UINTVAL (mask) >> shval) + 1);
7490 /* Return true if -msplit-addresses is selected and should be honored.
7492 -msplit-addresses is a half-way house between explicit relocations
7493 and the traditional assembler macros. It can split absolute 32-bit
7494 symbolic constants into a high/lo_sum pair but uses macros for other
7497 Like explicit relocation support for REL targets, it relies
7498 on GNU extensions in the assembler and the linker.
7500 Although this code should work for -O0, it has traditionally
7501 been treated as an optimization. */
7504 mips_split_addresses_p (void)
7506 return (TARGET_SPLIT_ADDRESSES
7510 && !ABI_HAS_64BIT_SYMBOLS);
7513 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
7516 mips_init_relocs (void)
7518 memset (mips_split_p, '\0', sizeof (mips_split_p));
7519 memset (mips_split_hi_p, '\0', sizeof (mips_split_hi_p));
7520 memset (mips_use_pcrel_pool_p, '\0', sizeof (mips_use_pcrel_pool_p));
7521 memset (mips_hi_relocs, '\0', sizeof (mips_hi_relocs));
7522 memset (mips_lo_relocs, '\0', sizeof (mips_lo_relocs));
7524 if (TARGET_MIPS16_PCREL_LOADS)
7525 mips_use_pcrel_pool_p[SYMBOL_ABSOLUTE] = true;
7528 if (ABI_HAS_64BIT_SYMBOLS)
7530 if (TARGET_EXPLICIT_RELOCS)
7532 mips_split_p[SYMBOL_64_HIGH] = true;
7533 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
7534 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
7536 mips_split_p[SYMBOL_64_MID] = true;
7537 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
7538 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
7540 mips_split_p[SYMBOL_64_LOW] = true;
7541 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
7542 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
7544 mips_split_p[SYMBOL_ABSOLUTE] = true;
7545 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
7550 if (TARGET_EXPLICIT_RELOCS
7551 || mips_split_addresses_p ()
7554 mips_split_p[SYMBOL_ABSOLUTE] = true;
7555 mips_hi_relocs[SYMBOL_ABSOLUTE] = "%hi(";
7556 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
7563 /* The high part is provided by a pseudo copy of $gp. */
7564 mips_split_p[SYMBOL_GP_RELATIVE] = true;
7565 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gprel(";
7567 else if (TARGET_EXPLICIT_RELOCS)
7568 /* Small data constants are kept whole until after reload,
7569 then lowered by mips_rewrite_small_data. */
7570 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gp_rel(";
7572 if (TARGET_EXPLICIT_RELOCS)
7574 mips_split_p[SYMBOL_GOT_PAGE_OFST] = true;
7577 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
7578 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%got_ofst(";
7582 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
7583 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%lo(";
7586 /* Expose the use of $28 as soon as possible. */
7587 mips_split_hi_p[SYMBOL_GOT_PAGE_OFST] = true;
7591 /* The HIGH and LO_SUM are matched by special .md patterns. */
7592 mips_split_p[SYMBOL_GOT_DISP] = true;
7594 mips_split_p[SYMBOL_GOTOFF_DISP] = true;
7595 mips_hi_relocs[SYMBOL_GOTOFF_DISP] = "%got_hi(";
7596 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_lo(";
7598 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
7599 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
7600 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
7605 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_disp(";
7607 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got(";
7608 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
7610 /* Expose the use of $28 as soon as possible. */
7611 mips_split_p[SYMBOL_GOT_DISP] = true;
7617 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
7618 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
7619 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
7622 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
7623 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
7625 if (TARGET_MIPS16_PCREL_LOADS)
7627 mips_use_pcrel_pool_p[SYMBOL_DTPREL] = true;
7628 mips_use_pcrel_pool_p[SYMBOL_TPREL] = true;
7632 mips_split_p[SYMBOL_DTPREL] = true;
7633 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
7634 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
7636 mips_split_p[SYMBOL_TPREL] = true;
7637 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
7638 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
7641 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
7642 mips_lo_relocs[SYMBOL_HALF] = "%half(";
7645 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
7646 in context CONTEXT. RELOCS is the array of relocations to use. */
7649 mips_print_operand_reloc (FILE *file, rtx op, enum mips_symbol_context context,
7650 const char **relocs)
7652 enum mips_symbol_type symbol_type;
7655 symbol_type = mips_classify_symbolic_expression (op, context);
7656 gcc_assert (relocs[symbol_type]);
7658 fputs (relocs[symbol_type], file);
7659 output_addr_const (file, mips_strip_unspec_address (op));
7660 for (p = relocs[symbol_type]; *p != 0; p++)
7665 /* Start a new block with the given asm switch enabled. If we need
7666 to print a directive, emit PREFIX before it and SUFFIX after it. */
7669 mips_push_asm_switch_1 (struct mips_asm_switch *asm_switch,
7670 const char *prefix, const char *suffix)
7672 if (asm_switch->nesting_level == 0)
7673 fprintf (asm_out_file, "%s.set\tno%s%s", prefix, asm_switch->name, suffix);
7674 asm_switch->nesting_level++;
7677 /* Likewise, but end a block. */
7680 mips_pop_asm_switch_1 (struct mips_asm_switch *asm_switch,
7681 const char *prefix, const char *suffix)
7683 gcc_assert (asm_switch->nesting_level);
7684 asm_switch->nesting_level--;
7685 if (asm_switch->nesting_level == 0)
7686 fprintf (asm_out_file, "%s.set\t%s%s", prefix, asm_switch->name, suffix);
7689 /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1
7690 that either print a complete line or print nothing. */
7693 mips_push_asm_switch (struct mips_asm_switch *asm_switch)
7695 mips_push_asm_switch_1 (asm_switch, "\t", "\n");
7699 mips_pop_asm_switch (struct mips_asm_switch *asm_switch)
7701 mips_pop_asm_switch_1 (asm_switch, "\t", "\n");
7704 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
7705 The punctuation characters are:
7707 '(' Start a nested ".set noreorder" block.
7708 ')' End a nested ".set noreorder" block.
7709 '[' Start a nested ".set noat" block.
7710 ']' End a nested ".set noat" block.
7711 '<' Start a nested ".set nomacro" block.
7712 '>' End a nested ".set nomacro" block.
7713 '*' Behave like %(%< if generating a delayed-branch sequence.
7714 '#' Print a nop if in a ".set noreorder" block.
7715 '/' Like '#', but do nothing within a delayed-branch sequence.
7716 '?' Print "l" if mips_branch_likely is true
7717 '~' Print a nop if mips_branch_likely is true
7718 '.' Print the name of the register with a hard-wired zero (zero or $0).
7719 '@' Print the name of the assembler temporary register (at or $1).
7720 '^' Print the name of the pic call-through register (t9 or $25).
7721 '+' Print the name of the gp register (usually gp or $28).
7722 '$' Print the name of the stack pointer register (sp or $29).
7724 See also mips_init_print_operand_pucnt. */
7727 mips_print_operand_punctuation (FILE *file, int ch)
7732 mips_push_asm_switch_1 (&mips_noreorder, "", "\n\t");
7736 mips_pop_asm_switch_1 (&mips_noreorder, "\n\t", "");
7740 mips_push_asm_switch_1 (&mips_noat, "", "\n\t");
7744 mips_pop_asm_switch_1 (&mips_noat, "\n\t", "");
7748 mips_push_asm_switch_1 (&mips_nomacro, "", "\n\t");
7752 mips_pop_asm_switch_1 (&mips_nomacro, "\n\t", "");
7756 if (final_sequence != 0)
7758 mips_print_operand_punctuation (file, '(');
7759 mips_print_operand_punctuation (file, '<');
7764 if (mips_noreorder.nesting_level > 0)
7765 fputs ("\n\tnop", file);
7769 /* Print an extra newline so that the delayed insn is separated
7770 from the following ones. This looks neater and is consistent
7771 with non-nop delayed sequences. */
7772 if (mips_noreorder.nesting_level > 0 && final_sequence == 0)
7773 fputs ("\n\tnop\n", file);
7777 if (mips_branch_likely)
7782 if (mips_branch_likely)
7783 fputs ("\n\tnop", file);
7787 fputs (reg_names[GP_REG_FIRST + 0], file);
7791 fputs (reg_names[AT_REGNUM], file);
7795 fputs (reg_names[PIC_FUNCTION_ADDR_REGNUM], file);
7799 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
7803 fputs (reg_names[STACK_POINTER_REGNUM], file);
7812 /* Initialize mips_print_operand_punct. */
7815 mips_init_print_operand_punct (void)
7819 for (p = "()[]<>*#/?~.@^+$"; *p; p++)
7820 mips_print_operand_punct[(unsigned char) *p] = true;
7823 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
7824 associated with condition CODE. Print the condition part of the
7828 mips_print_int_branch_condition (FILE *file, enum rtx_code code, int letter)
7842 /* Conveniently, the MIPS names for these conditions are the same
7843 as their RTL equivalents. */
7844 fputs (GET_RTX_NAME (code), file);
7848 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
7853 /* Likewise floating-point branches. */
7856 mips_print_float_branch_condition (FILE *file, enum rtx_code code, int letter)
7861 fputs ("c1f", file);
7865 fputs ("c1t", file);
7869 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
7874 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
7877 mips_print_operand_punct_valid_p (unsigned char code)
7879 return mips_print_operand_punct[code];
7882 /* Implement TARGET_PRINT_OPERAND. The MIPS-specific operand codes are:
7884 'X' Print CONST_INT OP in hexadecimal format.
7885 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
7886 'd' Print CONST_INT OP in decimal.
7887 'm' Print one less than CONST_INT OP in decimal.
7888 'h' Print the high-part relocation associated with OP, after stripping
7890 'R' Print the low-part relocation associated with OP.
7891 'C' Print the integer branch condition for comparison OP.
7892 'N' Print the inverse of the integer branch condition for comparison OP.
7893 'F' Print the FPU branch condition for comparison OP.
7894 'W' Print the inverse of the FPU branch condition for comparison OP.
7895 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
7896 'z' for (eq:?I ...), 'n' for (ne:?I ...).
7897 't' Like 'T', but with the EQ/NE cases reversed
7898 'Y' Print mips_fp_conditions[INTVAL (OP)]
7899 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
7900 'q' Print a DSP accumulator register.
7901 'D' Print the second part of a double-word register or memory operand.
7902 'L' Print the low-order register in a double-word register operand.
7903 'M' Print high-order register in a double-word register operand.
7904 'z' Print $0 if OP is zero, otherwise print OP normally.
7905 'b' Print the address of a memory operand, without offset. */
7908 mips_print_operand (FILE *file, rtx op, int letter)
7912 if (mips_print_operand_punct_valid_p (letter))
7914 mips_print_operand_punctuation (file, letter);
7919 code = GET_CODE (op);
7924 if (CONST_INT_P (op))
7925 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
7927 output_operand_lossage ("invalid use of '%%%c'", letter);
7931 if (CONST_INT_P (op))
7932 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op) & 0xffff);
7934 output_operand_lossage ("invalid use of '%%%c'", letter);
7938 if (CONST_INT_P (op))
7939 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op));
7941 output_operand_lossage ("invalid use of '%%%c'", letter);
7945 if (CONST_INT_P (op))
7946 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op) - 1);
7948 output_operand_lossage ("invalid use of '%%%c'", letter);
7954 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_hi_relocs);
7958 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_lo_relocs);
7962 mips_print_int_branch_condition (file, code, letter);
7966 mips_print_int_branch_condition (file, reverse_condition (code), letter);
7970 mips_print_float_branch_condition (file, code, letter);
7974 mips_print_float_branch_condition (file, reverse_condition (code),
7981 int truth = (code == NE) == (letter == 'T');
7982 fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
7987 if (code == CONST_INT && UINTVAL (op) < ARRAY_SIZE (mips_fp_conditions))
7988 fputs (mips_fp_conditions[UINTVAL (op)], file);
7990 output_operand_lossage ("'%%%c' is not a valid operand prefix",
7997 mips_print_operand (file, op, 0);
8003 if (code == REG && MD_REG_P (REGNO (op)))
8004 fprintf (file, "$ac0");
8005 else if (code == REG && DSP_ACC_REG_P (REGNO (op)))
8006 fprintf (file, "$ac%c", reg_names[REGNO (op)][3]);
8008 output_operand_lossage ("invalid use of '%%%c'", letter);
8016 unsigned int regno = REGNO (op);
8017 if ((letter == 'M' && TARGET_LITTLE_ENDIAN)
8018 || (letter == 'L' && TARGET_BIG_ENDIAN)
8021 else if (letter && letter != 'z' && letter != 'M' && letter != 'L')
8022 output_operand_lossage ("invalid use of '%%%c'", letter);
8023 /* We need to print $0 .. $31 for COP0 registers. */
8024 if (COP0_REG_P (regno))
8025 fprintf (file, "$%s", ®_names[regno][4]);
8027 fprintf (file, "%s", reg_names[regno]);
8033 output_address (plus_constant (Pmode, XEXP (op, 0), 4));
8034 else if (letter == 'b')
8036 gcc_assert (REG_P (XEXP (op, 0)));
8037 mips_print_operand (file, XEXP (op, 0), 0);
8039 else if (letter && letter != 'z')
8040 output_operand_lossage ("invalid use of '%%%c'", letter);
8042 output_address (XEXP (op, 0));
8046 if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
8047 fputs (reg_names[GP_REG_FIRST], file);
8048 else if (letter && letter != 'z')
8049 output_operand_lossage ("invalid use of '%%%c'", letter);
8050 else if (CONST_GP_P (op))
8051 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
8053 output_addr_const (file, mips_strip_unspec_address (op));
8059 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
8062 mips_print_operand_address (FILE *file, rtx x)
8064 struct mips_address_info addr;
8066 if (mips_classify_address (&addr, x, word_mode, true))
8070 mips_print_operand (file, addr.offset, 0);
8071 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
8074 case ADDRESS_LO_SUM:
8075 mips_print_operand_reloc (file, addr.offset, SYMBOL_CONTEXT_MEM,
8077 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
8080 case ADDRESS_CONST_INT:
8081 output_addr_const (file, x);
8082 fprintf (file, "(%s)", reg_names[GP_REG_FIRST]);
8085 case ADDRESS_SYMBOLIC:
8086 output_addr_const (file, mips_strip_unspec_address (x));
8092 /* Implement TARGET_ENCODE_SECTION_INFO. */
8095 mips_encode_section_info (tree decl, rtx rtl, int first)
8097 default_encode_section_info (decl, rtl, first);
8099 if (TREE_CODE (decl) == FUNCTION_DECL)
8101 rtx symbol = XEXP (rtl, 0);
8102 tree type = TREE_TYPE (decl);
8104 /* Encode whether the symbol is short or long. */
8105 if ((TARGET_LONG_CALLS && !mips_near_type_p (type))
8106 || mips_far_type_p (type))
8107 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
8111 /* Implement TARGET_SELECT_RTX_SECTION. */
8114 mips_select_rtx_section (enum machine_mode mode, rtx x,
8115 unsigned HOST_WIDE_INT align)
8117 /* ??? Consider using mergeable small data sections. */
8118 if (mips_rtx_constant_in_small_data_p (mode))
8119 return get_named_section (NULL, ".sdata", 0);
8121 return default_elf_select_rtx_section (mode, x, align);
8124 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
8126 The complication here is that, with the combination TARGET_ABICALLS
8127 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
8128 absolute addresses, and should therefore not be included in the
8129 read-only part of a DSO. Handle such cases by selecting a normal
8130 data section instead of a read-only one. The logic apes that in
8131 default_function_rodata_section. */
8134 mips_function_rodata_section (tree decl)
8136 if (!TARGET_ABICALLS || TARGET_ABSOLUTE_ABICALLS || TARGET_GPWORD)
8137 return default_function_rodata_section (decl);
8139 if (decl && DECL_SECTION_NAME (decl))
8141 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
8142 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
8144 char *rname = ASTRDUP (name);
8146 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
8148 else if (flag_function_sections
8149 && flag_data_sections
8150 && strncmp (name, ".text.", 6) == 0)
8152 char *rname = ASTRDUP (name);
8153 memcpy (rname + 1, "data", 4);
8154 return get_section (rname, SECTION_WRITE, decl);
8157 return data_section;
8160 /* Implement TARGET_IN_SMALL_DATA_P. */
8163 mips_in_small_data_p (const_tree decl)
8165 unsigned HOST_WIDE_INT size;
8167 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
8170 /* We don't yet generate small-data references for -mabicalls
8171 or VxWorks RTP code. See the related -G handling in
8172 mips_option_override. */
8173 if (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
8176 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
8180 /* Reject anything that isn't in a known small-data section. */
8181 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
8182 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
8185 /* If a symbol is defined externally, the assembler will use the
8186 usual -G rules when deciding how to implement macros. */
8187 if (mips_lo_relocs[SYMBOL_GP_RELATIVE] || !DECL_EXTERNAL (decl))
8190 else if (TARGET_EMBEDDED_DATA)
8192 /* Don't put constants into the small data section: we want them
8193 to be in ROM rather than RAM. */
8194 if (TREE_CODE (decl) != VAR_DECL)
8197 if (TREE_READONLY (decl)
8198 && !TREE_SIDE_EFFECTS (decl)
8199 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
8203 /* Enforce -mlocal-sdata. */
8204 if (!TARGET_LOCAL_SDATA && !TREE_PUBLIC (decl))
8207 /* Enforce -mextern-sdata. */
8208 if (!TARGET_EXTERN_SDATA && DECL_P (decl))
8210 if (DECL_EXTERNAL (decl))
8212 if (DECL_COMMON (decl) && DECL_INITIAL (decl) == NULL)
8216 /* We have traditionally not treated zero-sized objects as small data,
8217 so this is now effectively part of the ABI. */
8218 size = int_size_in_bytes (TREE_TYPE (decl));
8219 return size > 0 && size <= mips_small_data_threshold;
8222 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
8223 anchors for small data: the GP register acts as an anchor in that
8224 case. We also don't want to use them for PC-relative accesses,
8225 where the PC acts as an anchor. */
8228 mips_use_anchors_for_symbol_p (const_rtx symbol)
8230 switch (mips_classify_symbol (symbol, SYMBOL_CONTEXT_MEM))
8232 case SYMBOL_PC_RELATIVE:
8233 case SYMBOL_GP_RELATIVE:
8237 return default_use_anchors_for_symbol_p (symbol);
8241 /* The MIPS debug format wants all automatic variables and arguments
8242 to be in terms of the virtual frame pointer (stack pointer before
8243 any adjustment in the function), while the MIPS 3.0 linker wants
8244 the frame pointer to be the stack pointer after the initial
8245 adjustment. So, we do the adjustment here. The arg pointer (which
8246 is eliminated) points to the virtual frame pointer, while the frame
8247 pointer (which may be eliminated) points to the stack pointer after
8248 the initial adjustments. */
8251 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
8253 rtx offset2 = const0_rtx;
8254 rtx reg = eliminate_constant_term (addr, &offset2);
8257 offset = INTVAL (offset2);
8259 if (reg == stack_pointer_rtx
8260 || reg == frame_pointer_rtx
8261 || reg == hard_frame_pointer_rtx)
8263 offset -= cfun->machine->frame.total_size;
8264 if (reg == hard_frame_pointer_rtx)
8265 offset += cfun->machine->frame.hard_frame_pointer_offset;
8271 /* Implement ASM_OUTPUT_EXTERNAL. */
8274 mips_output_external (FILE *file, tree decl, const char *name)
8276 default_elf_asm_output_external (file, decl, name);
8278 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
8279 set in order to avoid putting out names that are never really
8281 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
8283 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
8285 /* When using assembler macros, emit .extern directives for
8286 all small-data externs so that the assembler knows how
8289 In most cases it would be safe (though pointless) to emit
8290 .externs for other symbols too. One exception is when an
8291 object is within the -G limit but declared by the user to
8292 be in a section other than .sbss or .sdata. */
8293 fputs ("\t.extern\t", file);
8294 assemble_name (file, name);
8295 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n",
8296 int_size_in_bytes (TREE_TYPE (decl)));
8301 /* Implement TARGET_ASM_OUTPUT_SOURCE_FILENAME. */
8304 mips_output_filename (FILE *stream, const char *name)
8306 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
8308 if (write_symbols == DWARF2_DEBUG)
8310 else if (mips_output_filename_first_time)
8312 mips_output_filename_first_time = 0;
8313 num_source_filenames += 1;
8314 current_function_file = name;
8315 fprintf (stream, "\t.file\t%d ", num_source_filenames);
8316 output_quoted_string (stream, name);
8317 putc ('\n', stream);
8319 /* If we are emitting stabs, let dbxout.c handle this (except for
8320 the mips_output_filename_first_time case). */
8321 else if (write_symbols == DBX_DEBUG)
8323 else if (name != current_function_file
8324 && strcmp (name, current_function_file) != 0)
8326 num_source_filenames += 1;
8327 current_function_file = name;
8328 fprintf (stream, "\t.file\t%d ", num_source_filenames);
8329 output_quoted_string (stream, name);
8330 putc ('\n', stream);
8334 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
8336 static void ATTRIBUTE_UNUSED
8337 mips_output_dwarf_dtprel (FILE *file, int size, rtx x)
8342 fputs ("\t.dtprelword\t", file);
8346 fputs ("\t.dtpreldword\t", file);
8352 output_addr_const (file, x);
8353 fputs ("+0x8000", file);
8356 /* Implement TARGET_DWARF_REGISTER_SPAN. */
8359 mips_dwarf_register_span (rtx reg)
8362 enum machine_mode mode;
8364 /* By default, GCC maps increasing register numbers to increasing
8365 memory locations, but paired FPRs are always little-endian,
8366 regardless of the prevailing endianness. */
8367 mode = GET_MODE (reg);
8368 if (FP_REG_P (REGNO (reg))
8369 && TARGET_BIG_ENDIAN
8370 && MAX_FPRS_PER_FMT > 1
8371 && GET_MODE_SIZE (mode) > UNITS_PER_FPREG)
8373 gcc_assert (GET_MODE_SIZE (mode) == UNITS_PER_HWFPVALUE);
8374 high = mips_subword (reg, true);
8375 low = mips_subword (reg, false);
8376 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, high, low));
8382 /* DSP ALU can bypass data with no delays for the following pairs. */
8383 enum insn_code dspalu_bypass_table[][2] =
8385 {CODE_FOR_mips_addsc, CODE_FOR_mips_addwc},
8386 {CODE_FOR_mips_cmpu_eq_qb, CODE_FOR_mips_pick_qb},
8387 {CODE_FOR_mips_cmpu_lt_qb, CODE_FOR_mips_pick_qb},
8388 {CODE_FOR_mips_cmpu_le_qb, CODE_FOR_mips_pick_qb},
8389 {CODE_FOR_mips_cmp_eq_ph, CODE_FOR_mips_pick_ph},
8390 {CODE_FOR_mips_cmp_lt_ph, CODE_FOR_mips_pick_ph},
8391 {CODE_FOR_mips_cmp_le_ph, CODE_FOR_mips_pick_ph},
8392 {CODE_FOR_mips_wrdsp, CODE_FOR_mips_insv}
8396 mips_dspalu_bypass_p (rtx out_insn, rtx in_insn)
8399 int num_bypass = ARRAY_SIZE (dspalu_bypass_table);
8400 enum insn_code out_icode = (enum insn_code) INSN_CODE (out_insn);
8401 enum insn_code in_icode = (enum insn_code) INSN_CODE (in_insn);
8403 for (i = 0; i < num_bypass; i++)
8405 if (out_icode == dspalu_bypass_table[i][0]
8406 && in_icode == dspalu_bypass_table[i][1])
8412 /* Implement ASM_OUTPUT_ASCII. */
8415 mips_output_ascii (FILE *stream, const char *string, size_t len)
8421 fprintf (stream, "\t.ascii\t\"");
8422 for (i = 0; i < len; i++)
8426 c = (unsigned char) string[i];
8429 if (c == '\\' || c == '\"')
8431 putc ('\\', stream);
8439 fprintf (stream, "\\%03o", c);
8443 if (cur_pos > 72 && i+1 < len)
8446 fprintf (stream, "\"\n\t.ascii\t\"");
8449 fprintf (stream, "\"\n");
8452 /* Return the pseudo-op for full SYMBOL_(D)TPREL address *ADDR.
8453 Update *ADDR with the operand that should be printed. */
8456 mips_output_tls_reloc_directive (rtx *addr)
8458 enum mips_symbol_type type;
8460 type = mips_classify_symbolic_expression (*addr, SYMBOL_CONTEXT_LEA);
8461 *addr = mips_strip_unspec_address (*addr);
8465 return Pmode == SImode ? ".dtprelword\t%0" : ".dtpreldword\t%0";
8468 return Pmode == SImode ? ".tprelword\t%0" : ".tpreldword\t%0";
8475 /* Emit either a label, .comm, or .lcomm directive. When using assembler
8476 macros, mark the symbol as written so that mips_asm_output_external
8477 won't emit an .extern for it. STREAM is the output file, NAME is the
8478 name of the symbol, INIT_STRING is the string that should be written
8479 before the symbol and FINAL_STRING is the string that should be
8480 written after it. FINAL_STRING is a printf format that consumes the
8481 remaining arguments. */
8484 mips_declare_object (FILE *stream, const char *name, const char *init_string,
8485 const char *final_string, ...)
8489 fputs (init_string, stream);
8490 assemble_name (stream, name);
8491 va_start (ap, final_string);
8492 vfprintf (stream, final_string, ap);
8495 if (!TARGET_EXPLICIT_RELOCS)
8497 tree name_tree = get_identifier (name);
8498 TREE_ASM_WRITTEN (name_tree) = 1;
8502 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
8503 NAME is the name of the object and ALIGN is the required alignment
8504 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
8505 alignment argument. */
8508 mips_declare_common_object (FILE *stream, const char *name,
8509 const char *init_string,
8510 unsigned HOST_WIDE_INT size,
8511 unsigned int align, bool takes_alignment_p)
8513 if (!takes_alignment_p)
8515 size += (align / BITS_PER_UNIT) - 1;
8516 size -= size % (align / BITS_PER_UNIT);
8517 mips_declare_object (stream, name, init_string,
8518 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
8521 mips_declare_object (stream, name, init_string,
8522 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
8523 size, align / BITS_PER_UNIT);
8526 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
8527 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
8530 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
8531 unsigned HOST_WIDE_INT size,
8534 /* If the target wants uninitialized const declarations in
8535 .rdata then don't put them in .comm. */
8536 if (TARGET_EMBEDDED_DATA
8537 && TARGET_UNINIT_CONST_IN_RODATA
8538 && TREE_CODE (decl) == VAR_DECL
8539 && TREE_READONLY (decl)
8540 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
8542 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
8543 targetm.asm_out.globalize_label (stream, name);
8545 switch_to_section (readonly_data_section);
8546 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
8547 mips_declare_object (stream, name, "",
8548 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
8552 mips_declare_common_object (stream, name, "\n\t.comm\t",
8556 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8557 extern int size_directive_output;
8559 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
8560 definitions except that it uses mips_declare_object to emit the label. */
8563 mips_declare_object_name (FILE *stream, const char *name,
8564 tree decl ATTRIBUTE_UNUSED)
8566 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8567 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
8570 size_directive_output = 0;
8571 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
8575 size_directive_output = 1;
8576 size = int_size_in_bytes (TREE_TYPE (decl));
8577 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8580 mips_declare_object (stream, name, "", ":\n");
8583 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
8586 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
8590 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
8591 if (!flag_inhibit_size_directive
8592 && DECL_SIZE (decl) != 0
8595 && DECL_INITIAL (decl) == error_mark_node
8596 && !size_directive_output)
8600 size_directive_output = 1;
8601 size = int_size_in_bytes (TREE_TYPE (decl));
8602 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8607 /* Return the FOO in the name of the ".mdebug.FOO" section associated
8608 with the current ABI. */
8611 mips_mdebug_abi_name (void)
8624 return TARGET_64BIT ? "eabi64" : "eabi32";
8630 /* Implement TARGET_ASM_FILE_START. */
8633 mips_file_start (void)
8635 default_file_start ();
8637 /* Generate a special section to describe the ABI switches used to
8638 produce the resultant binary. */
8640 /* Record the ABI itself. Modern versions of binutils encode
8641 this information in the ELF header flags, but GDB needs the
8642 information in order to correctly debug binaries produced by
8643 older binutils. See the function mips_gdbarch_init in
8645 fprintf (asm_out_file, "\t.section .mdebug.%s\n\t.previous\n",
8646 mips_mdebug_abi_name ());
8648 /* There is no ELF header flag to distinguish long32 forms of the
8649 EABI from long64 forms. Emit a special section to help tools
8650 such as GDB. Do the same for o64, which is sometimes used with
8652 if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
8653 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n"
8654 "\t.previous\n", TARGET_LONG64 ? 64 : 32);
8656 #ifdef HAVE_AS_GNU_ATTRIBUTE
8660 /* No floating-point operations, -mno-float. */
8661 if (TARGET_NO_FLOAT)
8663 /* Soft-float code, -msoft-float. */
8664 else if (!TARGET_HARD_FLOAT_ABI)
8666 /* Single-float code, -msingle-float. */
8667 else if (!TARGET_DOUBLE_FLOAT)
8669 /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64. */
8670 else if (!TARGET_64BIT && TARGET_FLOAT64)
8672 /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */
8676 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n", attr);
8680 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
8681 if (TARGET_ABICALLS)
8683 fprintf (asm_out_file, "\t.abicalls\n");
8684 if (TARGET_ABICALLS_PIC0)
8685 fprintf (asm_out_file, "\t.option\tpic0\n");
8688 if (flag_verbose_asm)
8689 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
8691 mips_small_data_threshold, mips_arch_info->name, mips_isa);
8694 /* Implement TARGET_ASM_CODE_END. */
8697 mips_code_end (void)
8699 if (mips_need_mips16_rdhwr_p)
8700 mips_output_mips16_rdhwr ();
8703 /* Make the last instruction frame-related and note that it performs
8704 the operation described by FRAME_PATTERN. */
8707 mips_set_frame_expr (rtx frame_pattern)
8711 insn = get_last_insn ();
8712 RTX_FRAME_RELATED_P (insn) = 1;
8713 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
8718 /* Return a frame-related rtx that stores REG at MEM.
8719 REG must be a single register. */
8722 mips_frame_set (rtx mem, rtx reg)
8726 set = gen_rtx_SET (VOIDmode, mem, reg);
8727 RTX_FRAME_RELATED_P (set) = 1;
8732 /* Record that the epilogue has restored call-saved register REG. */
8735 mips_add_cfa_restore (rtx reg)
8737 mips_epilogue.cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg,
8738 mips_epilogue.cfa_restores);
8741 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
8742 mips16e_s2_s8_regs[X], it must also save the registers in indexes
8743 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
8744 static const unsigned char mips16e_s2_s8_regs[] = {
8745 30, 23, 22, 21, 20, 19, 18
8747 static const unsigned char mips16e_a0_a3_regs[] = {
8751 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
8752 ordered from the uppermost in memory to the lowest in memory. */
8753 static const unsigned char mips16e_save_restore_regs[] = {
8754 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
8757 /* Return the index of the lowest X in the range [0, SIZE) for which
8758 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
8761 mips16e_find_first_register (unsigned int mask, const unsigned char *regs,
8766 for (i = 0; i < size; i++)
8767 if (BITSET_P (mask, regs[i]))
8773 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
8774 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
8775 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
8776 is true for all indexes (X, SIZE). */
8779 mips16e_mask_registers (unsigned int *mask_ptr, const unsigned char *regs,
8780 unsigned int size, unsigned int *num_regs_ptr)
8784 i = mips16e_find_first_register (*mask_ptr, regs, size);
8785 for (i++; i < size; i++)
8786 if (!BITSET_P (*mask_ptr, regs[i]))
8789 *mask_ptr |= 1 << regs[i];
8793 /* Return a simplified form of X using the register values in REG_VALUES.
8794 REG_VALUES[R] is the last value assigned to hard register R, or null
8795 if R has not been modified.
8797 This function is rather limited, but is good enough for our purposes. */
8800 mips16e_collect_propagate_value (rtx x, rtx *reg_values)
8802 x = avoid_constant_pool_reference (x);
8806 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
8807 return simplify_gen_unary (GET_CODE (x), GET_MODE (x),
8808 x0, GET_MODE (XEXP (x, 0)));
8811 if (ARITHMETIC_P (x))
8813 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
8814 rtx x1 = mips16e_collect_propagate_value (XEXP (x, 1), reg_values);
8815 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), x0, x1);
8819 && reg_values[REGNO (x)]
8820 && !rtx_unstable_p (reg_values[REGNO (x)]))
8821 return reg_values[REGNO (x)];
8826 /* Return true if (set DEST SRC) stores an argument register into its
8827 caller-allocated save slot, storing the number of that argument
8828 register in *REGNO_PTR if so. REG_VALUES is as for
8829 mips16e_collect_propagate_value. */
8832 mips16e_collect_argument_save_p (rtx dest, rtx src, rtx *reg_values,
8833 unsigned int *regno_ptr)
8835 unsigned int argno, regno;
8836 HOST_WIDE_INT offset, required_offset;
8839 /* Check that this is a word-mode store. */
8840 if (!MEM_P (dest) || !REG_P (src) || GET_MODE (dest) != word_mode)
8843 /* Check that the register being saved is an unmodified argument
8845 regno = REGNO (src);
8846 if (!IN_RANGE (regno, GP_ARG_FIRST, GP_ARG_LAST) || reg_values[regno])
8848 argno = regno - GP_ARG_FIRST;
8850 /* Check whether the address is an appropriate stack-pointer or
8851 frame-pointer access. */
8852 addr = mips16e_collect_propagate_value (XEXP (dest, 0), reg_values);
8853 mips_split_plus (addr, &base, &offset);
8854 required_offset = cfun->machine->frame.total_size + argno * UNITS_PER_WORD;
8855 if (base == hard_frame_pointer_rtx)
8856 required_offset -= cfun->machine->frame.hard_frame_pointer_offset;
8857 else if (base != stack_pointer_rtx)
8859 if (offset != required_offset)
8866 /* A subroutine of mips_expand_prologue, called only when generating
8867 MIPS16e SAVE instructions. Search the start of the function for any
8868 instructions that save argument registers into their caller-allocated
8869 save slots. Delete such instructions and return a value N such that
8870 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
8871 instructions redundant. */
8874 mips16e_collect_argument_saves (void)
8876 rtx reg_values[FIRST_PSEUDO_REGISTER];
8877 rtx insn, next, set, dest, src;
8878 unsigned int nargs, regno;
8880 push_topmost_sequence ();
8882 memset (reg_values, 0, sizeof (reg_values));
8883 for (insn = get_insns (); insn; insn = next)
8885 next = NEXT_INSN (insn);
8886 if (NOTE_P (insn) || DEBUG_INSN_P (insn))
8892 set = PATTERN (insn);
8893 if (GET_CODE (set) != SET)
8896 dest = SET_DEST (set);
8897 src = SET_SRC (set);
8898 if (mips16e_collect_argument_save_p (dest, src, reg_values, ®no))
8900 if (!BITSET_P (cfun->machine->frame.mask, regno))
8903 nargs = MAX (nargs, (regno - GP_ARG_FIRST) + 1);
8906 else if (REG_P (dest) && GET_MODE (dest) == word_mode)
8907 reg_values[REGNO (dest)]
8908 = mips16e_collect_propagate_value (src, reg_values);
8912 pop_topmost_sequence ();
8917 /* Return a move between register REGNO and memory location SP + OFFSET.
8918 REG_PARM_P is true if SP + OFFSET belongs to REG_PARM_STACK_SPACE.
8919 Make the move a load if RESTORE_P, otherwise make it a store. */
8922 mips16e_save_restore_reg (bool restore_p, bool reg_parm_p,
8923 HOST_WIDE_INT offset, unsigned int regno)
8927 mem = gen_frame_mem (SImode, plus_constant (Pmode, stack_pointer_rtx,
8929 reg = gen_rtx_REG (SImode, regno);
8932 mips_add_cfa_restore (reg);
8933 return gen_rtx_SET (VOIDmode, reg, mem);
8936 return gen_rtx_SET (VOIDmode, mem, reg);
8937 return mips_frame_set (mem, reg);
8940 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
8941 The instruction must:
8943 - Allocate or deallocate SIZE bytes in total; SIZE is known
8946 - Save or restore as many registers in *MASK_PTR as possible.
8947 The instruction saves the first registers at the top of the
8948 allocated area, with the other registers below it.
8950 - Save NARGS argument registers above the allocated area.
8952 (NARGS is always zero if RESTORE_P.)
8954 The SAVE and RESTORE instructions cannot save and restore all general
8955 registers, so there may be some registers left over for the caller to
8956 handle. Destructively modify *MASK_PTR so that it contains the registers
8957 that still need to be saved or restored. The caller can save these
8958 registers in the memory immediately below *OFFSET_PTR, which is a
8959 byte offset from the bottom of the allocated stack area. */
8962 mips16e_build_save_restore (bool restore_p, unsigned int *mask_ptr,
8963 HOST_WIDE_INT *offset_ptr, unsigned int nargs,
8967 HOST_WIDE_INT offset, top_offset;
8968 unsigned int i, regno;
8971 gcc_assert (cfun->machine->frame.num_fp == 0);
8973 /* Calculate the number of elements in the PARALLEL. We need one element
8974 for the stack adjustment, one for each argument register save, and one
8975 for each additional register move. */
8977 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
8978 if (BITSET_P (*mask_ptr, mips16e_save_restore_regs[i]))
8981 /* Create the final PARALLEL. */
8982 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (n));
8985 /* Add the stack pointer adjustment. */
8986 set = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8987 plus_constant (Pmode, stack_pointer_rtx,
8988 restore_p ? size : -size));
8989 RTX_FRAME_RELATED_P (set) = 1;
8990 XVECEXP (pattern, 0, n++) = set;
8992 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8993 top_offset = restore_p ? size : 0;
8995 /* Save the arguments. */
8996 for (i = 0; i < nargs; i++)
8998 offset = top_offset + i * UNITS_PER_WORD;
8999 set = mips16e_save_restore_reg (restore_p, true, offset,
9001 XVECEXP (pattern, 0, n++) = set;
9004 /* Then fill in the other register moves. */
9005 offset = top_offset;
9006 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
9008 regno = mips16e_save_restore_regs[i];
9009 if (BITSET_P (*mask_ptr, regno))
9011 offset -= UNITS_PER_WORD;
9012 set = mips16e_save_restore_reg (restore_p, false, offset, regno);
9013 XVECEXP (pattern, 0, n++) = set;
9014 *mask_ptr &= ~(1 << regno);
9018 /* Tell the caller what offset it should use for the remaining registers. */
9019 *offset_ptr = size + (offset - top_offset);
9021 gcc_assert (n == XVECLEN (pattern, 0));
9026 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
9027 pointer. Return true if PATTERN matches the kind of instruction
9028 generated by mips16e_build_save_restore. If INFO is nonnull,
9029 initialize it when returning true. */
9032 mips16e_save_restore_pattern_p (rtx pattern, HOST_WIDE_INT adjust,
9033 struct mips16e_save_restore_info *info)
9035 unsigned int i, nargs, mask, extra;
9036 HOST_WIDE_INT top_offset, save_offset, offset;
9037 rtx set, reg, mem, base;
9040 if (!GENERATE_MIPS16E_SAVE_RESTORE)
9043 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
9044 top_offset = adjust > 0 ? adjust : 0;
9046 /* Interpret all other members of the PARALLEL. */
9047 save_offset = top_offset - UNITS_PER_WORD;
9051 for (n = 1; n < XVECLEN (pattern, 0); n++)
9053 /* Check that we have a SET. */
9054 set = XVECEXP (pattern, 0, n);
9055 if (GET_CODE (set) != SET)
9058 /* Check that the SET is a load (if restoring) or a store
9060 mem = adjust > 0 ? SET_SRC (set) : SET_DEST (set);
9064 /* Check that the address is the sum of the stack pointer and a
9065 possibly-zero constant offset. */
9066 mips_split_plus (XEXP (mem, 0), &base, &offset);
9067 if (base != stack_pointer_rtx)
9070 /* Check that SET's other operand is a register. */
9071 reg = adjust > 0 ? SET_DEST (set) : SET_SRC (set);
9075 /* Check for argument saves. */
9076 if (offset == top_offset + nargs * UNITS_PER_WORD
9077 && REGNO (reg) == GP_ARG_FIRST + nargs)
9079 else if (offset == save_offset)
9081 while (mips16e_save_restore_regs[i++] != REGNO (reg))
9082 if (i == ARRAY_SIZE (mips16e_save_restore_regs))
9085 mask |= 1 << REGNO (reg);
9086 save_offset -= UNITS_PER_WORD;
9092 /* Check that the restrictions on register ranges are met. */
9094 mips16e_mask_registers (&mask, mips16e_s2_s8_regs,
9095 ARRAY_SIZE (mips16e_s2_s8_regs), &extra);
9096 mips16e_mask_registers (&mask, mips16e_a0_a3_regs,
9097 ARRAY_SIZE (mips16e_a0_a3_regs), &extra);
9101 /* Make sure that the topmost argument register is not saved twice.
9102 The checks above ensure that the same is then true for the other
9103 argument registers. */
9104 if (nargs > 0 && BITSET_P (mask, GP_ARG_FIRST + nargs - 1))
9107 /* Pass back information, if requested. */
9110 info->nargs = nargs;
9112 info->size = (adjust > 0 ? adjust : -adjust);
9118 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
9119 for the register range [MIN_REG, MAX_REG]. Return a pointer to
9120 the null terminator. */
9123 mips16e_add_register_range (char *s, unsigned int min_reg,
9124 unsigned int max_reg)
9126 if (min_reg != max_reg)
9127 s += sprintf (s, ",%s-%s", reg_names[min_reg], reg_names[max_reg]);
9129 s += sprintf (s, ",%s", reg_names[min_reg]);
9133 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
9134 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
9137 mips16e_output_save_restore (rtx pattern, HOST_WIDE_INT adjust)
9139 static char buffer[300];
9141 struct mips16e_save_restore_info info;
9142 unsigned int i, end;
9145 /* Parse the pattern. */
9146 if (!mips16e_save_restore_pattern_p (pattern, adjust, &info))
9149 /* Add the mnemonic. */
9150 s = strcpy (buffer, adjust > 0 ? "restore\t" : "save\t");
9153 /* Save the arguments. */
9155 s += sprintf (s, "%s-%s,", reg_names[GP_ARG_FIRST],
9156 reg_names[GP_ARG_FIRST + info.nargs - 1]);
9157 else if (info.nargs == 1)
9158 s += sprintf (s, "%s,", reg_names[GP_ARG_FIRST]);
9160 /* Emit the amount of stack space to allocate or deallocate. */
9161 s += sprintf (s, "%d", (int) info.size);
9163 /* Save or restore $16. */
9164 if (BITSET_P (info.mask, 16))
9165 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 16]);
9167 /* Save or restore $17. */
9168 if (BITSET_P (info.mask, 17))
9169 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 17]);
9171 /* Save or restore registers in the range $s2...$s8, which
9172 mips16e_s2_s8_regs lists in decreasing order. Note that this
9173 is a software register range; the hardware registers are not
9174 numbered consecutively. */
9175 end = ARRAY_SIZE (mips16e_s2_s8_regs);
9176 i = mips16e_find_first_register (info.mask, mips16e_s2_s8_regs, end);
9178 s = mips16e_add_register_range (s, mips16e_s2_s8_regs[end - 1],
9179 mips16e_s2_s8_regs[i]);
9181 /* Save or restore registers in the range $a0...$a3. */
9182 end = ARRAY_SIZE (mips16e_a0_a3_regs);
9183 i = mips16e_find_first_register (info.mask, mips16e_a0_a3_regs, end);
9185 s = mips16e_add_register_range (s, mips16e_a0_a3_regs[i],
9186 mips16e_a0_a3_regs[end - 1]);
9188 /* Save or restore $31. */
9189 if (BITSET_P (info.mask, RETURN_ADDR_REGNUM))
9190 s += sprintf (s, ",%s", reg_names[RETURN_ADDR_REGNUM]);
9195 /* Return true if the current function returns its value in a floating-point
9196 register in MIPS16 mode. */
9199 mips16_cfun_returns_in_fpr_p (void)
9201 tree return_type = DECL_RESULT (current_function_decl);
9202 return (TARGET_MIPS16
9203 && TARGET_HARD_FLOAT_ABI
9204 && !aggregate_value_p (return_type, current_function_decl)
9205 && mips_return_mode_in_fpr_p (DECL_MODE (return_type)));
9208 /* Return true if predicate PRED is true for at least one instruction.
9209 Cache the result in *CACHE, and assume that the result is true
9210 if *CACHE is already true. */
9213 mips_find_gp_ref (bool *cache, bool (*pred) (rtx))
9219 push_topmost_sequence ();
9220 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9221 if (USEFUL_INSN_P (insn) && pred (insn))
9226 pop_topmost_sequence ();
9231 /* Return true if INSN refers to the global pointer in an "inflexible" way.
9232 See mips_cfun_has_inflexible_gp_ref_p for details. */
9235 mips_insn_has_inflexible_gp_ref_p (rtx insn)
9237 /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE
9238 indicate that the target could be a traditional MIPS
9239 lazily-binding stub. */
9240 return find_reg_fusage (insn, USE, pic_offset_table_rtx);
9243 /* Return true if the current function refers to the global pointer
9244 in a way that forces $28 to be valid. This means that we can't
9245 change the choice of global pointer, even for NewABI code.
9247 One example of this (and one which needs several checks) is that
9248 $28 must be valid when calling traditional MIPS lazy-binding stubs.
9249 (This restriction does not apply to PLTs.) */
9252 mips_cfun_has_inflexible_gp_ref_p (void)
9254 /* If the function has a nonlocal goto, $28 must hold the correct
9255 global pointer for the target function. That is, the target
9256 of the goto implicitly uses $28. */
9257 if (crtl->has_nonlocal_goto)
9260 if (TARGET_ABICALLS_PIC2)
9262 /* Symbolic accesses implicitly use the global pointer unless
9263 -mexplicit-relocs is in effect. JAL macros to symbolic addresses
9264 might go to traditional MIPS lazy-binding stubs. */
9265 if (!TARGET_EXPLICIT_RELOCS)
9268 /* FUNCTION_PROFILER includes a JAL to _mcount, which again
9269 can be lazily-bound. */
9273 /* MIPS16 functions that return in FPRs need to call an
9274 external libgcc routine. This call is only made explict
9275 during mips_expand_epilogue, and it too might be lazily bound. */
9276 if (mips16_cfun_returns_in_fpr_p ())
9280 return mips_find_gp_ref (&cfun->machine->has_inflexible_gp_insn_p,
9281 mips_insn_has_inflexible_gp_ref_p);
9284 /* Return true if INSN refers to the global pointer in a "flexible" way.
9285 See mips_cfun_has_flexible_gp_ref_p for details. */
9288 mips_insn_has_flexible_gp_ref_p (rtx insn)
9290 return (get_attr_got (insn) != GOT_UNSET
9291 || mips_small_data_pattern_p (PATTERN (insn))
9292 || reg_overlap_mentioned_p (pic_offset_table_rtx, PATTERN (insn)));
9295 /* Return true if the current function references the global pointer,
9296 but if those references do not inherently require the global pointer
9297 to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */
9300 mips_cfun_has_flexible_gp_ref_p (void)
9302 /* Reload can sometimes introduce constant pool references
9303 into a function that otherwise didn't need them. For example,
9304 suppose we have an instruction like:
9306 (set (reg:DF R1) (float:DF (reg:SI R2)))
9308 If R2 turns out to be a constant such as 1, the instruction may
9309 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
9310 the option of using this constant if R2 doesn't get allocated
9313 In cases like these, reload will have added the constant to the
9314 pool but no instruction will yet refer to it. */
9315 if (TARGET_ABICALLS_PIC2 && !reload_completed && crtl->uses_const_pool)
9318 return mips_find_gp_ref (&cfun->machine->has_flexible_gp_insn_p,
9319 mips_insn_has_flexible_gp_ref_p);
9322 /* Return the register that should be used as the global pointer
9323 within this function. Return INVALID_REGNUM if the function
9324 doesn't need a global pointer. */
9327 mips_global_pointer (void)
9331 /* $gp is always available unless we're using a GOT. */
9332 if (!TARGET_USE_GOT)
9333 return GLOBAL_POINTER_REGNUM;
9335 /* If there are inflexible references to $gp, we must use the
9336 standard register. */
9337 if (mips_cfun_has_inflexible_gp_ref_p ())
9338 return GLOBAL_POINTER_REGNUM;
9340 /* If there are no current references to $gp, then the only uses
9341 we can introduce later are those involved in long branches. */
9342 if (TARGET_ABSOLUTE_JUMPS && !mips_cfun_has_flexible_gp_ref_p ())
9343 return INVALID_REGNUM;
9345 /* If the global pointer is call-saved, try to use a call-clobbered
9347 if (TARGET_CALL_SAVED_GP && crtl->is_leaf)
9348 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
9349 if (!df_regs_ever_live_p (regno)
9350 && call_really_used_regs[regno]
9351 && !fixed_regs[regno]
9352 && regno != PIC_FUNCTION_ADDR_REGNUM)
9355 return GLOBAL_POINTER_REGNUM;
9358 /* Return true if the current function's prologue must load the global
9359 pointer value into pic_offset_table_rtx and store the same value in
9360 the function's cprestore slot (if any).
9362 One problem we have to deal with is that, when emitting GOT-based
9363 position independent code, long-branch sequences will need to load
9364 the address of the branch target from the GOT. We don't know until
9365 the very end of compilation whether (and where) the function needs
9366 long branches, so we must ensure that _any_ branch can access the
9367 global pointer in some form. However, we do not want to pessimize
9368 the usual case in which all branches are short.
9370 We handle this as follows:
9372 (1) During reload, we set cfun->machine->global_pointer to
9373 INVALID_REGNUM if we _know_ that the current function
9374 doesn't need a global pointer. This is only valid if
9375 long branches don't need the GOT.
9377 Otherwise, we assume that we might need a global pointer
9378 and pick an appropriate register.
9380 (2) If cfun->machine->global_pointer != INVALID_REGNUM,
9381 we ensure that the global pointer is available at every
9382 block boundary bar entry and exit. We do this in one of two ways:
9384 - If the function has a cprestore slot, we ensure that this
9385 slot is valid at every branch. However, as explained in
9386 point (6) below, there is no guarantee that pic_offset_table_rtx
9387 itself is valid if new uses of the global pointer are introduced
9388 after the first post-epilogue split.
9390 We guarantee that the cprestore slot is valid by loading it
9391 into a fake register, CPRESTORE_SLOT_REGNUM. We then make
9392 this register live at every block boundary bar function entry
9393 and exit. It is then invalid to move the load (and thus the
9394 preceding store) across a block boundary.
9396 - If the function has no cprestore slot, we guarantee that
9397 pic_offset_table_rtx itself is valid at every branch.
9399 See mips_eh_uses for the handling of the register liveness.
9401 (3) During prologue and epilogue generation, we emit "ghost"
9402 placeholder instructions to manipulate the global pointer.
9404 (4) During prologue generation, we set cfun->machine->must_initialize_gp_p
9405 and cfun->machine->must_restore_gp_when_clobbered_p if we already know
9406 that the function needs a global pointer. (There is no need to set
9407 them earlier than this, and doing it as late as possible leads to
9408 fewer false positives.)
9410 (5) If cfun->machine->must_initialize_gp_p is true during a
9411 split_insns pass, we split the ghost instructions into real
9412 instructions. These split instructions can then be optimized in
9413 the usual way. Otherwise, we keep the ghost instructions intact,
9414 and optimize for the case where they aren't needed. We still
9415 have the option of splitting them later, if we need to introduce
9416 new uses of the global pointer.
9418 For example, the scheduler ignores a ghost instruction that
9419 stores $28 to the stack, but it handles the split form of
9420 the ghost instruction as an ordinary store.
9422 (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p
9423 is true during the first post-epilogue split_insns pass, we split
9424 calls and restore_gp patterns into instructions that explicitly
9425 load pic_offset_table_rtx from the cprestore slot. Otherwise,
9426 we split these patterns into instructions that _don't_ load from
9429 If cfun->machine->must_restore_gp_when_clobbered_p is true at the
9430 time of the split, then any instructions that exist at that time
9431 can make free use of pic_offset_table_rtx. However, if we want
9432 to introduce new uses of the global pointer after the split,
9433 we must explicitly load the value from the cprestore slot, since
9434 pic_offset_table_rtx itself might not be valid at a given point
9437 The idea is that we want to be able to delete redundant
9438 loads from the cprestore slot in the usual case where no
9439 long branches are needed.
9441 (7) If cfun->machine->must_initialize_gp_p is still false at the end
9442 of md_reorg, we decide whether the global pointer is needed for
9443 long branches. If so, we set cfun->machine->must_initialize_gp_p
9444 to true and split the ghost instructions into real instructions
9447 Note that the ghost instructions must have a zero length for three reasons:
9449 - Giving the length of the underlying $gp sequence might cause
9450 us to use long branches in cases where they aren't really needed.
9452 - They would perturb things like alignment calculations.
9454 - More importantly, the hazard detection in md_reorg relies on
9455 empty instructions having a zero length.
9457 If we find a long branch and split the ghost instructions at the
9458 end of md_reorg, the split could introduce more long branches.
9459 That isn't a problem though, because we still do the split before
9460 the final shorten_branches pass.
9462 This is extremely ugly, but it seems like the best compromise between
9463 correctness and efficiency. */
9466 mips_must_initialize_gp_p (void)
9468 return cfun->machine->must_initialize_gp_p;
9471 /* Return true if REGNO is a register that is ordinarily call-clobbered
9472 but must nevertheless be preserved by an interrupt handler. */
9475 mips_interrupt_extra_call_saved_reg_p (unsigned int regno)
9477 if (MD_REG_P (regno))
9480 if (TARGET_DSP && DSP_ACC_REG_P (regno))
9483 if (GP_REG_P (regno) && !cfun->machine->use_shadow_register_set_p)
9485 /* $0 is hard-wired. */
9486 if (regno == GP_REG_FIRST)
9489 /* The interrupt handler can treat kernel registers as
9490 scratch registers. */
9491 if (KERNEL_REG_P (regno))
9494 /* The function will return the stack pointer to its original value
9496 if (regno == STACK_POINTER_REGNUM)
9499 /* Otherwise, return true for registers that aren't ordinarily
9501 return call_really_used_regs[regno];
9507 /* Return true if the current function should treat register REGNO
9511 mips_cfun_call_saved_reg_p (unsigned int regno)
9513 /* If the user makes an ordinarily-call-saved register global,
9514 that register is no longer call-saved. */
9515 if (global_regs[regno])
9518 /* Interrupt handlers need to save extra registers. */
9519 if (cfun->machine->interrupt_handler_p
9520 && mips_interrupt_extra_call_saved_reg_p (regno))
9523 /* call_insns preserve $28 unless they explicitly say otherwise,
9524 so call_really_used_regs[] treats $28 as call-saved. However,
9525 we want the ABI property rather than the default call_insn
9527 return (regno == GLOBAL_POINTER_REGNUM
9528 ? TARGET_CALL_SAVED_GP
9529 : !call_really_used_regs[regno]);
9532 /* Return true if the function body might clobber register REGNO.
9533 We know that REGNO is call-saved. */
9536 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno)
9538 /* Some functions should be treated as clobbering all call-saved
9540 if (crtl->saves_all_registers)
9543 /* DF handles cases where a register is explicitly referenced in
9544 the rtl. Incoming values are passed in call-clobbered registers,
9545 so we can assume that any live call-saved register is set within
9547 if (df_regs_ever_live_p (regno))
9550 /* Check for registers that are clobbered by FUNCTION_PROFILER.
9551 These clobbers are not explicit in the rtl. */
9552 if (crtl->profile && MIPS_SAVE_REG_FOR_PROFILING_P (regno))
9555 /* If we're using a call-saved global pointer, the function's
9556 prologue will need to set it up. */
9557 if (cfun->machine->global_pointer == regno)
9560 /* The function's prologue will need to set the frame pointer if
9561 frame_pointer_needed. */
9562 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
9565 /* If a MIPS16 function returns a value in FPRs, its epilogue
9566 will need to call an external libgcc routine. This yet-to-be
9567 generated call_insn will clobber $31. */
9568 if (regno == RETURN_ADDR_REGNUM && mips16_cfun_returns_in_fpr_p ())
9571 /* If REGNO is ordinarily call-clobbered, we must assume that any
9572 called function could modify it. */
9573 if (cfun->machine->interrupt_handler_p
9575 && mips_interrupt_extra_call_saved_reg_p (regno))
9581 /* Return true if the current function must save register REGNO. */
9584 mips_save_reg_p (unsigned int regno)
9586 if (mips_cfun_call_saved_reg_p (regno))
9588 if (mips_cfun_might_clobber_call_saved_reg_p (regno))
9591 /* Save both registers in an FPR pair if either one is used. This is
9592 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
9593 register to be used without the even register. */
9594 if (FP_REG_P (regno)
9595 && MAX_FPRS_PER_FMT == 2
9596 && mips_cfun_might_clobber_call_saved_reg_p (regno + 1))
9600 /* We need to save the incoming return address if __builtin_eh_return
9601 is being used to set a different return address. */
9602 if (regno == RETURN_ADDR_REGNUM && crtl->calls_eh_return)
9608 /* Populate the current function's mips_frame_info structure.
9610 MIPS stack frames look like:
9612 +-------------------------------+
9614 | incoming stack arguments |
9616 +-------------------------------+
9618 | caller-allocated save area |
9619 A | for register arguments |
9621 +-------------------------------+ <-- incoming stack pointer
9623 | callee-allocated save area |
9624 B | for arguments that are |
9625 | split between registers and |
9628 +-------------------------------+ <-- arg_pointer_rtx
9630 C | callee-allocated save area |
9631 | for register varargs |
9633 +-------------------------------+ <-- frame_pointer_rtx
9634 | | + cop0_sp_offset
9635 | COP0 reg save area | + UNITS_PER_WORD
9637 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
9638 | | + UNITS_PER_WORD
9639 | accumulator save area |
9641 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
9642 | | + UNITS_PER_HWFPVALUE
9645 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset
9646 | | + UNITS_PER_WORD
9649 +-------------------------------+ <-- frame_pointer_rtx with
9650 | | \ -fstack-protector
9651 | local variables | | var_size
9653 +-------------------------------+
9655 | $gp save area | | cprestore_size
9657 P +-------------------------------+ <-- hard_frame_pointer_rtx for
9659 | outgoing stack arguments | |
9661 +-------------------------------+ | args_size
9663 | caller-allocated save area | |
9664 | for register arguments | |
9666 +-------------------------------+ <-- stack_pointer_rtx
9667 frame_pointer_rtx without
9669 hard_frame_pointer_rtx for
9672 At least two of A, B and C will be empty.
9674 Dynamic stack allocations such as alloca insert data at point P.
9675 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
9676 hard_frame_pointer_rtx unchanged. */
9679 mips_compute_frame_info (void)
9681 struct mips_frame_info *frame;
9682 HOST_WIDE_INT offset, size;
9683 unsigned int regno, i;
9685 /* Set this function's interrupt properties. */
9686 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
9689 error ("the %<interrupt%> attribute requires a MIPS32r2 processor");
9690 else if (TARGET_HARD_FLOAT)
9691 error ("the %<interrupt%> attribute requires %<-msoft-float%>");
9692 else if (TARGET_MIPS16)
9693 error ("interrupt handlers cannot be MIPS16 functions");
9696 cfun->machine->interrupt_handler_p = true;
9697 cfun->machine->use_shadow_register_set_p =
9698 mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl));
9699 cfun->machine->keep_interrupts_masked_p =
9700 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl));
9701 cfun->machine->use_debug_exception_return_p =
9702 mips_use_debug_exception_return_p (TREE_TYPE
9703 (current_function_decl));
9707 frame = &cfun->machine->frame;
9708 memset (frame, 0, sizeof (*frame));
9709 size = get_frame_size ();
9711 cfun->machine->global_pointer = mips_global_pointer ();
9713 /* The first two blocks contain the outgoing argument area and the $gp save
9714 slot. This area isn't needed in leaf functions, but if the
9715 target-independent frame size is nonzero, we have already committed to
9716 allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */
9717 if ((size == 0 || FRAME_GROWS_DOWNWARD) && crtl->is_leaf)
9719 /* The MIPS 3.0 linker does not like functions that dynamically
9720 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
9721 looks like we are trying to create a second frame pointer to the
9722 function, so allocate some stack space to make it happy. */
9723 if (cfun->calls_alloca)
9724 frame->args_size = REG_PARM_STACK_SPACE (cfun->decl);
9726 frame->args_size = 0;
9727 frame->cprestore_size = 0;
9731 frame->args_size = crtl->outgoing_args_size;
9732 frame->cprestore_size = MIPS_GP_SAVE_AREA_SIZE;
9734 offset = frame->args_size + frame->cprestore_size;
9736 /* Move above the local variables. */
9737 frame->var_size = MIPS_STACK_ALIGN (size);
9738 offset += frame->var_size;
9740 /* Find out which GPRs we need to save. */
9741 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
9742 if (mips_save_reg_p (regno))
9745 frame->mask |= 1 << (regno - GP_REG_FIRST);
9748 /* If this function calls eh_return, we must also save and restore the
9749 EH data registers. */
9750 if (crtl->calls_eh_return)
9751 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; i++)
9754 frame->mask |= 1 << (EH_RETURN_DATA_REGNO (i) - GP_REG_FIRST);
9757 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
9758 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
9759 save all later registers too. */
9760 if (GENERATE_MIPS16E_SAVE_RESTORE)
9762 mips16e_mask_registers (&frame->mask, mips16e_s2_s8_regs,
9763 ARRAY_SIZE (mips16e_s2_s8_regs), &frame->num_gp);
9764 mips16e_mask_registers (&frame->mask, mips16e_a0_a3_regs,
9765 ARRAY_SIZE (mips16e_a0_a3_regs), &frame->num_gp);
9768 /* Move above the GPR save area. */
9769 if (frame->num_gp > 0)
9771 offset += MIPS_STACK_ALIGN (frame->num_gp * UNITS_PER_WORD);
9772 frame->gp_sp_offset = offset - UNITS_PER_WORD;
9775 /* Find out which FPRs we need to save. This loop must iterate over
9776 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
9777 if (TARGET_HARD_FLOAT)
9778 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += MAX_FPRS_PER_FMT)
9779 if (mips_save_reg_p (regno))
9781 frame->num_fp += MAX_FPRS_PER_FMT;
9782 frame->fmask |= ~(~0 << MAX_FPRS_PER_FMT) << (regno - FP_REG_FIRST);
9785 /* Move above the FPR save area. */
9786 if (frame->num_fp > 0)
9788 offset += MIPS_STACK_ALIGN (frame->num_fp * UNITS_PER_FPREG);
9789 frame->fp_sp_offset = offset - UNITS_PER_HWFPVALUE;
9792 /* Add in space for the interrupt context information. */
9793 if (cfun->machine->interrupt_handler_p)
9796 if (mips_save_reg_p (LO_REGNUM) || mips_save_reg_p (HI_REGNUM))
9799 frame->acc_mask |= (1 << 0);
9802 /* Check accumulators 1, 2, 3. */
9803 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
9804 if (mips_save_reg_p (i) || mips_save_reg_p (i + 1))
9807 frame->acc_mask |= 1 << (((i - DSP_ACC_REG_FIRST) / 2) + 1);
9810 /* All interrupt context functions need space to preserve STATUS. */
9811 frame->num_cop0_regs++;
9813 /* If we don't keep interrupts masked, we need to save EPC. */
9814 if (!cfun->machine->keep_interrupts_masked_p)
9815 frame->num_cop0_regs++;
9818 /* Move above the accumulator save area. */
9819 if (frame->num_acc > 0)
9821 /* Each accumulator needs 2 words. */
9822 offset += frame->num_acc * 2 * UNITS_PER_WORD;
9823 frame->acc_sp_offset = offset - UNITS_PER_WORD;
9826 /* Move above the COP0 register save area. */
9827 if (frame->num_cop0_regs > 0)
9829 offset += frame->num_cop0_regs * UNITS_PER_WORD;
9830 frame->cop0_sp_offset = offset - UNITS_PER_WORD;
9833 /* Move above the callee-allocated varargs save area. */
9834 offset += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
9835 frame->arg_pointer_offset = offset;
9837 /* Move above the callee-allocated area for pretend stack arguments. */
9838 offset += crtl->args.pretend_args_size;
9839 frame->total_size = offset;
9841 /* Work out the offsets of the save areas from the top of the frame. */
9842 if (frame->gp_sp_offset > 0)
9843 frame->gp_save_offset = frame->gp_sp_offset - offset;
9844 if (frame->fp_sp_offset > 0)
9845 frame->fp_save_offset = frame->fp_sp_offset - offset;
9846 if (frame->acc_sp_offset > 0)
9847 frame->acc_save_offset = frame->acc_sp_offset - offset;
9848 if (frame->num_cop0_regs > 0)
9849 frame->cop0_save_offset = frame->cop0_sp_offset - offset;
9851 /* MIPS16 code offsets the frame pointer by the size of the outgoing
9852 arguments. This tends to increase the chances of using unextended
9853 instructions for local variables and incoming arguments. */
9855 frame->hard_frame_pointer_offset = frame->args_size;
9858 /* Return the style of GP load sequence that is being used for the
9859 current function. */
9861 enum mips_loadgp_style
9862 mips_current_loadgp_style (void)
9864 if (!TARGET_USE_GOT || cfun->machine->global_pointer == INVALID_REGNUM)
9870 if (TARGET_ABSOLUTE_ABICALLS)
9871 return LOADGP_ABSOLUTE;
9873 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
9876 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
9879 mips_frame_pointer_required (void)
9881 /* If the function contains dynamic stack allocations, we need to
9882 use the frame pointer to access the static parts of the frame. */
9883 if (cfun->calls_alloca)
9886 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
9887 reload may be unable to compute the address of a local variable,
9888 since there is no way to add a large constant to the stack pointer
9889 without using a second temporary register. */
9892 mips_compute_frame_info ();
9893 if (!SMALL_OPERAND (cfun->machine->frame.total_size))
9900 /* Make sure that we're not trying to eliminate to the wrong hard frame
9904 mips_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
9906 return (to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM);
9909 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
9910 or argument pointer. TO is either the stack pointer or hard frame
9914 mips_initial_elimination_offset (int from, int to)
9916 HOST_WIDE_INT offset;
9918 mips_compute_frame_info ();
9920 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */
9923 case FRAME_POINTER_REGNUM:
9924 if (FRAME_GROWS_DOWNWARD)
9925 offset = (cfun->machine->frame.args_size
9926 + cfun->machine->frame.cprestore_size
9927 + cfun->machine->frame.var_size);
9932 case ARG_POINTER_REGNUM:
9933 offset = cfun->machine->frame.arg_pointer_offset;
9940 if (to == HARD_FRAME_POINTER_REGNUM)
9941 offset -= cfun->machine->frame.hard_frame_pointer_offset;
9946 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
9949 mips_extra_live_on_entry (bitmap regs)
9953 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
9954 the global pointer. */
9955 if (!TARGET_ABSOLUTE_ABICALLS)
9956 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
9958 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
9959 the global pointer. */
9961 bitmap_set_bit (regs, MIPS16_PIC_TEMP_REGNUM);
9963 /* See the comment above load_call<mode> for details. */
9964 bitmap_set_bit (regs, GOT_VERSION_REGNUM);
9968 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
9972 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
9977 return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);
9980 /* Emit code to change the current function's return address to
9981 ADDRESS. SCRATCH is available as a scratch register, if needed.
9982 ADDRESS and SCRATCH are both word-mode GPRs. */
9985 mips_set_return_address (rtx address, rtx scratch)
9989 gcc_assert (BITSET_P (cfun->machine->frame.mask, RETURN_ADDR_REGNUM));
9990 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
9991 cfun->machine->frame.gp_sp_offset);
9992 mips_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address);
9995 /* Return true if the current function has a cprestore slot. */
9998 mips_cfun_has_cprestore_slot_p (void)
10000 return (cfun->machine->global_pointer != INVALID_REGNUM
10001 && cfun->machine->frame.cprestore_size > 0);
10004 /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the
10005 cprestore slot. LOAD_P is true if the caller wants to load from
10006 the cprestore slot; it is false if the caller wants to store to
10010 mips_get_cprestore_base_and_offset (rtx *base, HOST_WIDE_INT *offset,
10013 const struct mips_frame_info *frame;
10015 frame = &cfun->machine->frame;
10016 /* .cprestore always uses the stack pointer instead of the frame pointer.
10017 We have a free choice for direct stores for non-MIPS16 functions,
10018 and for MIPS16 functions whose cprestore slot is in range of the
10019 stack pointer. Using the stack pointer would sometimes give more
10020 (early) scheduling freedom, but using the frame pointer would
10021 sometimes give more (late) scheduling freedom. It's hard to
10022 predict which applies to a given function, so let's keep things
10025 Loads must always use the frame pointer in functions that call
10026 alloca, and there's little benefit to using the stack pointer
10028 if (frame_pointer_needed && !(TARGET_CPRESTORE_DIRECTIVE && !load_p))
10030 *base = hard_frame_pointer_rtx;
10031 *offset = frame->args_size - frame->hard_frame_pointer_offset;
10035 *base = stack_pointer_rtx;
10036 *offset = frame->args_size;
10040 /* Return true if X is the load or store address of the cprestore slot;
10041 LOAD_P says which. */
10044 mips_cprestore_address_p (rtx x, bool load_p)
10046 rtx given_base, required_base;
10047 HOST_WIDE_INT given_offset, required_offset;
10049 mips_split_plus (x, &given_base, &given_offset);
10050 mips_get_cprestore_base_and_offset (&required_base, &required_offset, load_p);
10051 return given_base == required_base && given_offset == required_offset;
10054 /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are
10055 going to load from it, false if we are going to store to it.
10056 Use TEMP as a temporary register if need be. */
10059 mips_cprestore_slot (rtx temp, bool load_p)
10062 HOST_WIDE_INT offset;
10064 mips_get_cprestore_base_and_offset (&base, &offset, load_p);
10065 return gen_frame_mem (Pmode, mips_add_offset (temp, base, offset));
10068 /* Emit instructions to save global pointer value GP into cprestore
10069 slot MEM. OFFSET is the offset that MEM applies to the base register.
10071 MEM may not be a legitimate address. If it isn't, TEMP is a
10072 temporary register that can be used, otherwise it is a SCRATCH. */
10075 mips_save_gp_to_cprestore_slot (rtx mem, rtx offset, rtx gp, rtx temp)
10077 if (TARGET_CPRESTORE_DIRECTIVE)
10079 gcc_assert (gp == pic_offset_table_rtx);
10080 emit_insn (PMODE_INSN (gen_cprestore, (mem, offset)));
10083 mips_emit_move (mips_cprestore_slot (temp, false), gp);
10086 /* Restore $gp from its save slot, using TEMP as a temporary base register
10087 if need be. This function is for o32 and o64 abicalls only.
10089 See mips_must_initialize_gp_p for details about how we manage the
10093 mips_restore_gp_from_cprestore_slot (rtx temp)
10095 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI && epilogue_completed);
10097 if (!cfun->machine->must_restore_gp_when_clobbered_p)
10099 emit_note (NOTE_INSN_DELETED);
10105 mips_emit_move (temp, mips_cprestore_slot (temp, true));
10106 mips_emit_move (pic_offset_table_rtx, temp);
10109 mips_emit_move (pic_offset_table_rtx, mips_cprestore_slot (temp, true));
10110 if (!TARGET_EXPLICIT_RELOCS)
10111 emit_insn (gen_blockage ());
10114 /* A function to save or store a register. The first argument is the
10115 register and the second is the stack slot. */
10116 typedef void (*mips_save_restore_fn) (rtx, rtx);
10118 /* Use FN to save or restore register REGNO. MODE is the register's
10119 mode and OFFSET is the offset of its save slot from the current
10123 mips_save_restore_reg (enum machine_mode mode, int regno,
10124 HOST_WIDE_INT offset, mips_save_restore_fn fn)
10128 mem = gen_frame_mem (mode, plus_constant (Pmode, stack_pointer_rtx,
10130 fn (gen_rtx_REG (mode, regno), mem);
10133 /* Call FN for each accumlator that is saved by the current function.
10134 SP_OFFSET is the offset of the current stack pointer from the start
10138 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
10140 HOST_WIDE_INT offset;
10143 offset = cfun->machine->frame.acc_sp_offset - sp_offset;
10144 if (BITSET_P (cfun->machine->frame.acc_mask, 0))
10146 mips_save_restore_reg (word_mode, LO_REGNUM, offset, fn);
10147 offset -= UNITS_PER_WORD;
10148 mips_save_restore_reg (word_mode, HI_REGNUM, offset, fn);
10149 offset -= UNITS_PER_WORD;
10152 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
10153 if (BITSET_P (cfun->machine->frame.acc_mask,
10154 ((regno - DSP_ACC_REG_FIRST) / 2) + 1))
10156 mips_save_restore_reg (word_mode, regno, offset, fn);
10157 offset -= UNITS_PER_WORD;
10161 /* Call FN for each register that is saved by the current function.
10162 SP_OFFSET is the offset of the current stack pointer from the start
10166 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset,
10167 mips_save_restore_fn fn)
10169 enum machine_mode fpr_mode;
10170 HOST_WIDE_INT offset;
10173 /* Save registers starting from high to low. The debuggers prefer at least
10174 the return register be stored at func+4, and also it allows us not to
10175 need a nop in the epilogue if at least one register is reloaded in
10176 addition to return address. */
10177 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
10178 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
10179 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
10181 /* Record the ra offset for use by mips_function_profiler. */
10182 if (regno == RETURN_ADDR_REGNUM)
10183 cfun->machine->frame.ra_fp_offset = offset + sp_offset;
10184 mips_save_restore_reg (word_mode, regno, offset, fn);
10185 offset -= UNITS_PER_WORD;
10188 /* This loop must iterate over the same space as its companion in
10189 mips_compute_frame_info. */
10190 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
10191 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
10192 for (regno = FP_REG_LAST - MAX_FPRS_PER_FMT + 1;
10193 regno >= FP_REG_FIRST;
10194 regno -= MAX_FPRS_PER_FMT)
10195 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
10197 mips_save_restore_reg (fpr_mode, regno, offset, fn);
10198 offset -= GET_MODE_SIZE (fpr_mode);
10202 /* Return true if a move between register REGNO and its save slot (MEM)
10203 can be done in a single move. LOAD_P is true if we are loading
10204 from the slot, false if we are storing to it. */
10207 mips_direct_save_slot_move_p (unsigned int regno, rtx mem, bool load_p)
10209 /* There is a specific MIPS16 instruction for saving $31 to the stack. */
10210 if (TARGET_MIPS16 && !load_p && regno == RETURN_ADDR_REGNUM)
10213 return mips_secondary_reload_class (REGNO_REG_CLASS (regno),
10214 GET_MODE (mem), mem, load_p) == NO_REGS;
10217 /* Emit a move from SRC to DEST, given that one of them is a register
10218 save slot and that the other is a register. TEMP is a temporary
10219 GPR of the same mode that is available if need be. */
10222 mips_emit_save_slot_move (rtx dest, rtx src, rtx temp)
10224 unsigned int regno;
10229 regno = REGNO (src);
10234 regno = REGNO (dest);
10238 if (regno == cfun->machine->global_pointer && !mips_must_initialize_gp_p ())
10240 /* We don't yet know whether we'll need this instruction or not.
10241 Postpone the decision by emitting a ghost move. This move
10242 is specifically not frame-related; only the split version is. */
10244 emit_insn (gen_move_gpdi (dest, src));
10246 emit_insn (gen_move_gpsi (dest, src));
10250 if (regno == HI_REGNUM)
10254 mips_emit_move (temp, src);
10256 emit_insn (gen_mthisi_di (gen_rtx_REG (TImode, MD_REG_FIRST),
10257 temp, gen_rtx_REG (DImode, LO_REGNUM)));
10259 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode, MD_REG_FIRST),
10260 temp, gen_rtx_REG (SImode, LO_REGNUM)));
10265 emit_insn (gen_mfhidi_ti (temp,
10266 gen_rtx_REG (TImode, MD_REG_FIRST)));
10268 emit_insn (gen_mfhisi_di (temp,
10269 gen_rtx_REG (DImode, MD_REG_FIRST)));
10270 mips_emit_move (dest, temp);
10273 else if (mips_direct_save_slot_move_p (regno, mem, mem == src))
10274 mips_emit_move (dest, src);
10277 gcc_assert (!reg_overlap_mentioned_p (dest, temp));
10278 mips_emit_move (temp, src);
10279 mips_emit_move (dest, temp);
10282 mips_set_frame_expr (mips_frame_set (dest, src));
10285 /* If we're generating n32 or n64 abicalls, and the current function
10286 does not use $28 as its global pointer, emit a cplocal directive.
10287 Use pic_offset_table_rtx as the argument to the directive. */
10290 mips_output_cplocal (void)
10292 if (!TARGET_EXPLICIT_RELOCS
10293 && mips_must_initialize_gp_p ()
10294 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
10295 output_asm_insn (".cplocal %+", 0);
10298 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
10301 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
10303 const char *fnname;
10305 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
10306 floating-point arguments. */
10308 && TARGET_HARD_FLOAT_ABI
10309 && crtl->args.info.fp_code != 0)
10310 mips16_build_function_stub ();
10312 /* Get the function name the same way that toplev.c does before calling
10313 assemble_start_function. This is needed so that the name used here
10314 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10315 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
10316 mips_start_function_definition (fnname, TARGET_MIPS16);
10318 /* Output MIPS-specific frame information. */
10319 if (!flag_inhibit_size_directive)
10321 const struct mips_frame_info *frame;
10323 frame = &cfun->machine->frame;
10325 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
10327 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
10328 "# vars= " HOST_WIDE_INT_PRINT_DEC
10330 ", args= " HOST_WIDE_INT_PRINT_DEC
10331 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
10332 reg_names[frame_pointer_needed
10333 ? HARD_FRAME_POINTER_REGNUM
10334 : STACK_POINTER_REGNUM],
10335 (frame_pointer_needed
10336 ? frame->total_size - frame->hard_frame_pointer_offset
10337 : frame->total_size),
10338 reg_names[RETURN_ADDR_REGNUM],
10340 frame->num_gp, frame->num_fp,
10342 frame->cprestore_size);
10344 /* .mask MASK, OFFSET. */
10345 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
10346 frame->mask, frame->gp_save_offset);
10348 /* .fmask MASK, OFFSET. */
10349 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
10350 frame->fmask, frame->fp_save_offset);
10353 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
10354 Also emit the ".set noreorder; .set nomacro" sequence for functions
10356 if (mips_must_initialize_gp_p ()
10357 && mips_current_loadgp_style () == LOADGP_OLDABI)
10361 /* This is a fixed-form sequence. The position of the
10362 first two instructions is important because of the
10363 way _gp_disp is defined. */
10364 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
10365 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
10366 output_asm_insn ("sll\t$2,16", 0);
10367 output_asm_insn ("addu\t$2,$3", 0);
10371 /* .cpload must be in a .set noreorder but not a
10372 .set nomacro block. */
10373 mips_push_asm_switch (&mips_noreorder);
10374 output_asm_insn (".cpload\t%^", 0);
10375 if (!cfun->machine->all_noreorder_p)
10376 mips_pop_asm_switch (&mips_noreorder);
10378 mips_push_asm_switch (&mips_nomacro);
10381 else if (cfun->machine->all_noreorder_p)
10383 mips_push_asm_switch (&mips_noreorder);
10384 mips_push_asm_switch (&mips_nomacro);
10387 /* Tell the assembler which register we're using as the global
10388 pointer. This is needed for thunks, since they can use either
10389 explicit relocs or assembler macros. */
10390 mips_output_cplocal ();
10393 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
10396 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
10397 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
10399 const char *fnname;
10401 /* Reinstate the normal $gp. */
10402 SET_REGNO (pic_offset_table_rtx, GLOBAL_POINTER_REGNUM);
10403 mips_output_cplocal ();
10405 if (cfun->machine->all_noreorder_p)
10407 mips_pop_asm_switch (&mips_nomacro);
10408 mips_pop_asm_switch (&mips_noreorder);
10411 /* Get the function name the same way that toplev.c does before calling
10412 assemble_start_function. This is needed so that the name used here
10413 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10414 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
10415 mips_end_function_definition (fnname);
10418 /* Emit an optimisation barrier for accesses to the current frame. */
10421 mips_frame_barrier (void)
10423 emit_clobber (gen_frame_mem (BLKmode, stack_pointer_rtx));
10426 /* Save register REG to MEM. Make the instruction frame-related. */
10429 mips_save_reg (rtx reg, rtx mem)
10431 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
10435 if (mips_split_64bit_move_p (mem, reg))
10436 mips_split_doubleword_move (mem, reg);
10438 mips_emit_move (mem, reg);
10440 x1 = mips_frame_set (mips_subword (mem, false),
10441 mips_subword (reg, false));
10442 x2 = mips_frame_set (mips_subword (mem, true),
10443 mips_subword (reg, true));
10444 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
10447 mips_emit_save_slot_move (mem, reg, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
10450 /* The __gnu_local_gp symbol. */
10452 static GTY(()) rtx mips_gnu_local_gp;
10454 /* If we're generating n32 or n64 abicalls, emit instructions
10455 to set up the global pointer. */
10458 mips_emit_loadgp (void)
10460 rtx addr, offset, incoming_address, base, index, pic_reg;
10462 pic_reg = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
10463 switch (mips_current_loadgp_style ())
10465 case LOADGP_ABSOLUTE:
10466 if (mips_gnu_local_gp == NULL)
10468 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
10469 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
10471 emit_insn (PMODE_INSN (gen_loadgp_absolute,
10472 (pic_reg, mips_gnu_local_gp)));
10475 case LOADGP_OLDABI:
10476 /* Added by mips_output_function_prologue. */
10479 case LOADGP_NEWABI:
10480 addr = XEXP (DECL_RTL (current_function_decl), 0);
10481 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
10482 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
10483 emit_insn (PMODE_INSN (gen_loadgp_newabi,
10484 (pic_reg, offset, incoming_address)));
10488 base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE));
10489 index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX));
10490 emit_insn (PMODE_INSN (gen_loadgp_rtp, (pic_reg, base, index)));
10498 emit_insn (PMODE_INSN (gen_copygp_mips16,
10499 (pic_offset_table_rtx, pic_reg)));
10501 /* Emit a blockage if there are implicit uses of the GP register.
10502 This includes profiled functions, because FUNCTION_PROFILE uses
10504 if (!TARGET_EXPLICIT_RELOCS || crtl->profile)
10505 emit_insn (gen_loadgp_blockage ());
10508 /* A for_each_rtx callback. Stop the search if *X is a kernel register. */
10511 mips_kernel_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
10513 return REG_P (*x) && KERNEL_REG_P (REGNO (*x));
10516 /* Expand the "prologue" pattern. */
10519 mips_expand_prologue (void)
10521 const struct mips_frame_info *frame;
10522 HOST_WIDE_INT size;
10523 unsigned int nargs;
10526 if (cfun->machine->global_pointer != INVALID_REGNUM)
10528 /* Check whether an insn uses pic_offset_table_rtx, either explicitly
10529 or implicitly. If so, we can commit to using a global pointer
10530 straight away, otherwise we need to defer the decision. */
10531 if (mips_cfun_has_inflexible_gp_ref_p ()
10532 || mips_cfun_has_flexible_gp_ref_p ())
10534 cfun->machine->must_initialize_gp_p = true;
10535 cfun->machine->must_restore_gp_when_clobbered_p = true;
10538 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
10541 frame = &cfun->machine->frame;
10542 size = frame->total_size;
10544 if (flag_stack_usage_info)
10545 current_function_static_stack_size = size;
10547 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
10548 bytes beforehand; this is enough to cover the register save area
10549 without going out of range. */
10550 if (((frame->mask | frame->fmask | frame->acc_mask) != 0)
10551 || frame->num_cop0_regs > 0)
10553 HOST_WIDE_INT step1;
10555 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
10556 if (GENERATE_MIPS16E_SAVE_RESTORE)
10558 HOST_WIDE_INT offset;
10559 unsigned int mask, regno;
10561 /* Try to merge argument stores into the save instruction. */
10562 nargs = mips16e_collect_argument_saves ();
10564 /* Build the save instruction. */
10565 mask = frame->mask;
10566 insn = mips16e_build_save_restore (false, &mask, &offset,
10568 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10569 mips_frame_barrier ();
10572 /* Check if we need to save other registers. */
10573 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
10574 if (BITSET_P (mask, regno - GP_REG_FIRST))
10576 offset -= UNITS_PER_WORD;
10577 mips_save_restore_reg (word_mode, regno,
10578 offset, mips_save_reg);
10583 if (cfun->machine->interrupt_handler_p)
10585 HOST_WIDE_INT offset;
10588 /* If this interrupt is using a shadow register set, we need to
10589 get the stack pointer from the previous register set. */
10590 if (cfun->machine->use_shadow_register_set_p)
10591 emit_insn (gen_mips_rdpgpr (stack_pointer_rtx,
10592 stack_pointer_rtx));
10594 if (!cfun->machine->keep_interrupts_masked_p)
10596 /* Move from COP0 Cause to K0. */
10597 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K0_REG_NUM),
10598 gen_rtx_REG (SImode,
10599 COP0_CAUSE_REG_NUM)));
10600 /* Move from COP0 EPC to K1. */
10601 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
10602 gen_rtx_REG (SImode,
10603 COP0_EPC_REG_NUM)));
10606 /* Allocate the first part of the frame. */
10607 insn = gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx,
10609 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10610 mips_frame_barrier ();
10613 /* Start at the uppermost location for saving. */
10614 offset = frame->cop0_sp_offset - size;
10615 if (!cfun->machine->keep_interrupts_masked_p)
10617 /* Push EPC into its stack slot. */
10618 mem = gen_frame_mem (word_mode,
10619 plus_constant (Pmode, stack_pointer_rtx,
10621 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
10622 offset -= UNITS_PER_WORD;
10625 /* Move from COP0 Status to K1. */
10626 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
10627 gen_rtx_REG (SImode,
10628 COP0_STATUS_REG_NUM)));
10630 /* Right justify the RIPL in k0. */
10631 if (!cfun->machine->keep_interrupts_masked_p)
10632 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode, K0_REG_NUM),
10633 gen_rtx_REG (SImode, K0_REG_NUM),
10634 GEN_INT (CAUSE_IPL)));
10636 /* Push Status into its stack slot. */
10637 mem = gen_frame_mem (word_mode,
10638 plus_constant (Pmode, stack_pointer_rtx,
10640 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
10641 offset -= UNITS_PER_WORD;
10643 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
10644 if (!cfun->machine->keep_interrupts_masked_p)
10645 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
10648 gen_rtx_REG (SImode, K0_REG_NUM)));
10650 if (!cfun->machine->keep_interrupts_masked_p)
10651 /* Enable interrupts by clearing the KSU ERL and EXL bits.
10652 IE is already the correct value, so we don't have to do
10653 anything explicit. */
10654 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
10657 gen_rtx_REG (SImode, GP_REG_FIRST)));
10659 /* Disable interrupts by clearing the KSU, ERL, EXL,
10661 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
10664 gen_rtx_REG (SImode, GP_REG_FIRST)));
10668 insn = gen_add3_insn (stack_pointer_rtx,
10671 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10672 mips_frame_barrier ();
10675 mips_for_each_saved_acc (size, mips_save_reg);
10676 mips_for_each_saved_gpr_and_fpr (size, mips_save_reg);
10680 /* Allocate the rest of the frame. */
10683 if (SMALL_OPERAND (-size))
10684 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
10686 GEN_INT (-size)))) = 1;
10689 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
10692 /* There are no instructions to add or subtract registers
10693 from the stack pointer, so use the frame pointer as a
10694 temporary. We should always be using a frame pointer
10695 in this case anyway. */
10696 gcc_assert (frame_pointer_needed);
10697 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
10698 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
10699 hard_frame_pointer_rtx,
10700 MIPS_PROLOGUE_TEMP (Pmode)));
10701 mips_emit_move (stack_pointer_rtx, hard_frame_pointer_rtx);
10704 emit_insn (gen_sub3_insn (stack_pointer_rtx,
10706 MIPS_PROLOGUE_TEMP (Pmode)));
10708 /* Describe the combined effect of the previous instructions. */
10709 mips_set_frame_expr
10710 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
10711 plus_constant (Pmode, stack_pointer_rtx, -size)));
10713 mips_frame_barrier ();
10716 /* Set up the frame pointer, if we're using one. */
10717 if (frame_pointer_needed)
10719 HOST_WIDE_INT offset;
10721 offset = frame->hard_frame_pointer_offset;
10724 insn = mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
10725 RTX_FRAME_RELATED_P (insn) = 1;
10727 else if (SMALL_OPERAND (offset))
10729 insn = gen_add3_insn (hard_frame_pointer_rtx,
10730 stack_pointer_rtx, GEN_INT (offset));
10731 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10735 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (offset));
10736 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
10737 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
10738 hard_frame_pointer_rtx,
10739 MIPS_PROLOGUE_TEMP (Pmode)));
10740 mips_set_frame_expr
10741 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
10742 plus_constant (Pmode, stack_pointer_rtx, offset)));
10746 mips_emit_loadgp ();
10748 /* Initialize the $gp save slot. */
10749 if (mips_cfun_has_cprestore_slot_p ())
10751 rtx base, mem, gp, temp;
10752 HOST_WIDE_INT offset;
10754 mips_get_cprestore_base_and_offset (&base, &offset, false);
10755 mem = gen_frame_mem (Pmode, plus_constant (Pmode, base, offset));
10756 gp = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
10757 temp = (SMALL_OPERAND (offset)
10758 ? gen_rtx_SCRATCH (Pmode)
10759 : MIPS_PROLOGUE_TEMP (Pmode));
10760 emit_insn (PMODE_INSN (gen_potential_cprestore,
10761 (mem, GEN_INT (offset), gp, temp)));
10763 mips_get_cprestore_base_and_offset (&base, &offset, true);
10764 mem = gen_frame_mem (Pmode, plus_constant (Pmode, base, offset));
10765 emit_insn (PMODE_INSN (gen_use_cprestore, (mem)));
10768 /* We need to search back to the last use of K0 or K1. */
10769 if (cfun->machine->interrupt_handler_p)
10771 for (insn = get_last_insn (); insn != NULL_RTX; insn = PREV_INSN (insn))
10773 && for_each_rtx (&PATTERN (insn), mips_kernel_reg_p, NULL))
10775 /* Emit a move from K1 to COP0 Status after insn. */
10776 gcc_assert (insn != NULL_RTX);
10777 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
10778 gen_rtx_REG (SImode, K1_REG_NUM)),
10782 /* If we are profiling, make sure no instructions are scheduled before
10783 the call to mcount. */
10785 emit_insn (gen_blockage ());
10788 /* Attach all pending register saves to the previous instruction.
10789 Return that instruction. */
10792 mips_epilogue_emit_cfa_restores (void)
10796 insn = get_last_insn ();
10797 gcc_assert (insn && !REG_NOTES (insn));
10798 if (mips_epilogue.cfa_restores)
10800 RTX_FRAME_RELATED_P (insn) = 1;
10801 REG_NOTES (insn) = mips_epilogue.cfa_restores;
10802 mips_epilogue.cfa_restores = 0;
10807 /* Like mips_epilogue_emit_cfa_restores, but also record that the CFA is
10808 now at REG + OFFSET. */
10811 mips_epilogue_set_cfa (rtx reg, HOST_WIDE_INT offset)
10815 insn = mips_epilogue_emit_cfa_restores ();
10816 if (reg != mips_epilogue.cfa_reg || offset != mips_epilogue.cfa_offset)
10818 RTX_FRAME_RELATED_P (insn) = 1;
10819 REG_NOTES (insn) = alloc_reg_note (REG_CFA_DEF_CFA,
10820 plus_constant (Pmode, reg, offset),
10822 mips_epilogue.cfa_reg = reg;
10823 mips_epilogue.cfa_offset = offset;
10827 /* Emit instructions to restore register REG from slot MEM. Also update
10828 the cfa_restores list. */
10831 mips_restore_reg (rtx reg, rtx mem)
10833 /* There's no MIPS16 instruction to load $31 directly. Load into
10834 $7 instead and adjust the return insn appropriately. */
10835 if (TARGET_MIPS16 && REGNO (reg) == RETURN_ADDR_REGNUM)
10836 reg = gen_rtx_REG (GET_MODE (reg), GP_REG_FIRST + 7);
10837 else if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
10839 mips_add_cfa_restore (mips_subword (reg, true));
10840 mips_add_cfa_restore (mips_subword (reg, false));
10843 mips_add_cfa_restore (reg);
10845 mips_emit_save_slot_move (reg, mem, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
10846 if (REGNO (reg) == REGNO (mips_epilogue.cfa_reg))
10847 /* The CFA is currently defined in terms of the register whose
10848 value we have just restored. Redefine the CFA in terms of
10849 the stack pointer. */
10850 mips_epilogue_set_cfa (stack_pointer_rtx,
10851 mips_epilogue.cfa_restore_sp_offset);
10854 /* Emit code to set the stack pointer to BASE + OFFSET, given that
10855 BASE + OFFSET is NEW_FRAME_SIZE bytes below the top of the frame.
10856 BASE, if not the stack pointer, is available as a temporary. */
10859 mips_deallocate_stack (rtx base, rtx offset, HOST_WIDE_INT new_frame_size)
10861 if (base == stack_pointer_rtx && offset == const0_rtx)
10864 mips_frame_barrier ();
10865 if (offset == const0_rtx)
10867 emit_move_insn (stack_pointer_rtx, base);
10868 mips_epilogue_set_cfa (stack_pointer_rtx, new_frame_size);
10870 else if (TARGET_MIPS16 && base != stack_pointer_rtx)
10872 emit_insn (gen_add3_insn (base, base, offset));
10873 mips_epilogue_set_cfa (base, new_frame_size);
10874 emit_move_insn (stack_pointer_rtx, base);
10878 emit_insn (gen_add3_insn (stack_pointer_rtx, base, offset));
10879 mips_epilogue_set_cfa (stack_pointer_rtx, new_frame_size);
10883 /* Emit any instructions needed before a return. */
10886 mips_expand_before_return (void)
10888 /* When using a call-clobbered gp, we start out with unified call
10889 insns that include instructions to restore the gp. We then split
10890 these unified calls after reload. These split calls explicitly
10891 clobber gp, so there is no need to define
10892 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
10894 For consistency, we should also insert an explicit clobber of $28
10895 before return insns, so that the post-reload optimizers know that
10896 the register is not live on exit. */
10897 if (TARGET_CALL_CLOBBERED_GP)
10898 emit_clobber (pic_offset_table_rtx);
10901 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
10905 mips_expand_epilogue (bool sibcall_p)
10907 const struct mips_frame_info *frame;
10908 HOST_WIDE_INT step1, step2;
10909 rtx base, adjust, insn;
10911 if (!sibcall_p && mips_can_use_return_insn ())
10913 emit_jump_insn (gen_return ());
10917 /* In MIPS16 mode, if the return value should go into a floating-point
10918 register, we need to call a helper routine to copy it over. */
10919 if (mips16_cfun_returns_in_fpr_p ())
10920 mips16_copy_fpr_return_value ();
10922 /* Split the frame into two. STEP1 is the amount of stack we should
10923 deallocate before restoring the registers. STEP2 is the amount we
10924 should deallocate afterwards.
10926 Start off by assuming that no registers need to be restored. */
10927 frame = &cfun->machine->frame;
10928 step1 = frame->total_size;
10931 /* Work out which register holds the frame address. */
10932 if (!frame_pointer_needed)
10933 base = stack_pointer_rtx;
10936 base = hard_frame_pointer_rtx;
10937 step1 -= frame->hard_frame_pointer_offset;
10939 mips_epilogue.cfa_reg = base;
10940 mips_epilogue.cfa_offset = step1;
10941 mips_epilogue.cfa_restores = NULL_RTX;
10943 /* If we need to restore registers, deallocate as much stack as
10944 possible in the second step without going out of range. */
10945 if ((frame->mask | frame->fmask | frame->acc_mask) != 0
10946 || frame->num_cop0_regs > 0)
10948 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
10952 /* Get an rtx for STEP1 that we can add to BASE. */
10953 adjust = GEN_INT (step1);
10954 if (!SMALL_OPERAND (step1))
10956 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), adjust);
10957 adjust = MIPS_EPILOGUE_TEMP (Pmode);
10959 mips_deallocate_stack (base, adjust, step2);
10961 /* If we're using addressing macros, $gp is implicitly used by all
10962 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
10964 if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS)
10965 emit_insn (gen_blockage ());
10967 mips_epilogue.cfa_restore_sp_offset = step2;
10968 if (GENERATE_MIPS16E_SAVE_RESTORE && frame->mask != 0)
10970 unsigned int regno, mask;
10971 HOST_WIDE_INT offset;
10974 /* Generate the restore instruction. */
10975 mask = frame->mask;
10976 restore = mips16e_build_save_restore (true, &mask, &offset, 0, step2);
10978 /* Restore any other registers manually. */
10979 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
10980 if (BITSET_P (mask, regno - GP_REG_FIRST))
10982 offset -= UNITS_PER_WORD;
10983 mips_save_restore_reg (word_mode, regno, offset, mips_restore_reg);
10986 /* Restore the remaining registers and deallocate the final bit
10988 mips_frame_barrier ();
10989 emit_insn (restore);
10990 mips_epilogue_set_cfa (stack_pointer_rtx, 0);
10994 /* Restore the registers. */
10995 mips_for_each_saved_acc (frame->total_size - step2, mips_restore_reg);
10996 mips_for_each_saved_gpr_and_fpr (frame->total_size - step2,
10999 if (cfun->machine->interrupt_handler_p)
11001 HOST_WIDE_INT offset;
11004 offset = frame->cop0_sp_offset - (frame->total_size - step2);
11005 if (!cfun->machine->keep_interrupts_masked_p)
11007 /* Restore the original EPC. */
11008 mem = gen_frame_mem (word_mode,
11009 plus_constant (Pmode, stack_pointer_rtx,
11011 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
11012 offset -= UNITS_PER_WORD;
11014 /* Move to COP0 EPC. */
11015 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_EPC_REG_NUM),
11016 gen_rtx_REG (SImode, K0_REG_NUM)));
11019 /* Restore the original Status. */
11020 mem = gen_frame_mem (word_mode,
11021 plus_constant (Pmode, stack_pointer_rtx,
11023 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
11024 offset -= UNITS_PER_WORD;
11026 /* If we don't use shoadow register set, we need to update SP. */
11027 if (!cfun->machine->use_shadow_register_set_p)
11028 mips_deallocate_stack (stack_pointer_rtx, GEN_INT (step2), 0);
11030 /* The choice of position is somewhat arbitrary in this case. */
11031 mips_epilogue_emit_cfa_restores ();
11033 /* Move to COP0 Status. */
11034 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
11035 gen_rtx_REG (SImode, K0_REG_NUM)));
11038 /* Deallocate the final bit of the frame. */
11039 mips_deallocate_stack (stack_pointer_rtx, GEN_INT (step2), 0);
11041 gcc_assert (!mips_epilogue.cfa_restores);
11043 /* Add in the __builtin_eh_return stack adjustment. We need to
11044 use a temporary in MIPS16 code. */
11045 if (crtl->calls_eh_return)
11049 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
11050 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
11051 MIPS_EPILOGUE_TEMP (Pmode),
11052 EH_RETURN_STACKADJ_RTX));
11053 mips_emit_move (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
11056 emit_insn (gen_add3_insn (stack_pointer_rtx,
11058 EH_RETURN_STACKADJ_RTX));
11063 mips_expand_before_return ();
11064 if (cfun->machine->interrupt_handler_p)
11066 /* Interrupt handlers generate eret or deret. */
11067 if (cfun->machine->use_debug_exception_return_p)
11068 emit_jump_insn (gen_mips_deret ());
11070 emit_jump_insn (gen_mips_eret ());
11076 /* When generating MIPS16 code, the normal
11077 mips_for_each_saved_gpr_and_fpr path will restore the return
11078 address into $7 rather than $31. */
11080 && !GENERATE_MIPS16E_SAVE_RESTORE
11081 && BITSET_P (frame->mask, RETURN_ADDR_REGNUM))
11083 /* simple_returns cannot rely on values that are only available
11084 on paths through the epilogue (because return paths that do
11085 not pass through the epilogue may nevertheless reuse a
11086 simple_return that occurs at the end of the epilogue).
11087 Use a normal return here instead. */
11088 rtx reg = gen_rtx_REG (Pmode, GP_REG_FIRST + 7);
11089 pat = gen_return_internal (reg);
11093 rtx reg = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
11094 pat = gen_simple_return_internal (reg);
11096 emit_jump_insn (pat);
11100 /* Search from the beginning to the first use of K0 or K1. */
11101 if (cfun->machine->interrupt_handler_p
11102 && !cfun->machine->keep_interrupts_masked_p)
11104 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
11106 && for_each_rtx (&PATTERN(insn), mips_kernel_reg_p, NULL))
11108 gcc_assert (insn != NULL_RTX);
11109 /* Insert disable interrupts before the first use of K0 or K1. */
11110 emit_insn_before (gen_mips_di (), insn);
11111 emit_insn_before (gen_mips_ehb (), insn);
11115 /* Return nonzero if this function is known to have a null epilogue.
11116 This allows the optimizer to omit jumps to jumps if no stack
11120 mips_can_use_return_insn (void)
11122 /* Interrupt handlers need to go through the epilogue. */
11123 if (cfun->machine->interrupt_handler_p)
11126 if (!reload_completed)
11132 /* In MIPS16 mode, a function that returns a floating-point value
11133 needs to arrange to copy the return value into the floating-point
11135 if (mips16_cfun_returns_in_fpr_p ())
11138 return cfun->machine->frame.total_size == 0;
11141 /* Return true if register REGNO can store a value of mode MODE.
11142 The result of this function is cached in mips_hard_regno_mode_ok. */
11145 mips_hard_regno_mode_ok_p (unsigned int regno, enum machine_mode mode)
11148 enum mode_class mclass;
11150 if (mode == CCV2mode)
11151 return (ISA_HAS_8CC
11152 && ST_REG_P (regno)
11153 && (regno - ST_REG_FIRST) % 2 == 0);
11155 if (mode == CCV4mode)
11156 return (ISA_HAS_8CC
11157 && ST_REG_P (regno)
11158 && (regno - ST_REG_FIRST) % 4 == 0);
11160 if (mode == CCmode)
11161 return ISA_HAS_8CC ? ST_REG_P (regno) : regno == FPSW_REGNUM;
11163 size = GET_MODE_SIZE (mode);
11164 mclass = GET_MODE_CLASS (mode);
11166 if (GP_REG_P (regno))
11167 return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD;
11169 if (FP_REG_P (regno)
11170 && (((regno - FP_REG_FIRST) % MAX_FPRS_PER_FMT) == 0
11171 || (MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG)))
11173 /* Allow 64-bit vector modes for Loongson-2E/2F. */
11174 if (TARGET_LOONGSON_VECTORS
11175 && (mode == V2SImode
11176 || mode == V4HImode
11177 || mode == V8QImode
11178 || mode == DImode))
11181 if (mclass == MODE_FLOAT
11182 || mclass == MODE_COMPLEX_FLOAT
11183 || mclass == MODE_VECTOR_FLOAT)
11184 return size <= UNITS_PER_FPVALUE;
11186 /* Allow integer modes that fit into a single register. We need
11187 to put integers into FPRs when using instructions like CVT
11188 and TRUNC. There's no point allowing sizes smaller than a word,
11189 because the FPU has no appropriate load/store instructions. */
11190 if (mclass == MODE_INT)
11191 return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG;
11194 if (ACC_REG_P (regno)
11195 && (INTEGRAL_MODE_P (mode) || ALL_FIXED_POINT_MODE_P (mode)))
11197 if (MD_REG_P (regno))
11199 /* After a multiplication or division, clobbering HI makes
11200 the value of LO unpredictable, and vice versa. This means
11201 that, for all interesting cases, HI and LO are effectively
11204 We model this by requiring that any value that uses HI
11206 if (size <= UNITS_PER_WORD * 2)
11207 return regno == (size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST);
11211 /* DSP accumulators do not have the same restrictions as
11212 HI and LO, so we can treat them as normal doubleword
11214 if (size <= UNITS_PER_WORD)
11217 if (size <= UNITS_PER_WORD * 2
11218 && ((regno - DSP_ACC_REG_FIRST) & 1) == 0)
11223 if (ALL_COP_REG_P (regno))
11224 return mclass == MODE_INT && size <= UNITS_PER_WORD;
11226 if (regno == GOT_VERSION_REGNUM)
11227 return mode == SImode;
11232 /* Implement HARD_REGNO_NREGS. */
11235 mips_hard_regno_nregs (int regno, enum machine_mode mode)
11237 if (ST_REG_P (regno))
11238 /* The size of FP status registers is always 4, because they only hold
11239 CCmode values, and CCmode is always considered to be 4 bytes wide. */
11240 return (GET_MODE_SIZE (mode) + 3) / 4;
11242 if (FP_REG_P (regno))
11243 return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG;
11245 /* All other registers are word-sized. */
11246 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
11249 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
11250 in mips_hard_regno_nregs. */
11253 mips_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
11259 COPY_HARD_REG_SET (left, reg_class_contents[(int) rclass]);
11260 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS]))
11262 if (HARD_REGNO_MODE_OK (ST_REG_FIRST, mode))
11263 size = MIN (size, 4);
11264 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) ST_REGS]);
11266 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS]))
11268 if (HARD_REGNO_MODE_OK (FP_REG_FIRST, mode))
11269 size = MIN (size, UNITS_PER_FPREG);
11270 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]);
11272 if (!hard_reg_set_empty_p (left))
11273 size = MIN (size, UNITS_PER_WORD);
11274 return (GET_MODE_SIZE (mode) + size - 1) / size;
11277 /* Implement CANNOT_CHANGE_MODE_CLASS. */
11280 mips_cannot_change_mode_class (enum machine_mode from,
11281 enum machine_mode to,
11282 enum reg_class rclass)
11284 /* Allow conversions between different Loongson integer vectors,
11285 and between those vectors and DImode. */
11286 if (GET_MODE_SIZE (from) == 8 && GET_MODE_SIZE (to) == 8
11287 && INTEGRAL_MODE_P (from) && INTEGRAL_MODE_P (to))
11290 /* Otherwise, there are several problems with changing the modes of
11291 values in floating-point registers:
11293 - When a multi-word value is stored in paired floating-point
11294 registers, the first register always holds the low word. We
11295 therefore can't allow FPRs to change between single-word and
11296 multi-word modes on big-endian targets.
11298 - GCC assumes that each word of a multiword register can be
11299 accessed individually using SUBREGs. This is not true for
11300 floating-point registers if they are bigger than a word.
11302 - Loading a 32-bit value into a 64-bit floating-point register
11303 will not sign-extend the value, despite what LOAD_EXTEND_OP
11304 says. We can't allow FPRs to change from SImode to a wider
11305 mode on 64-bit targets.
11307 - If the FPU has already interpreted a value in one format, we
11308 must not ask it to treat the value as having a different
11311 We therefore disallow all mode changes involving FPRs. */
11313 return reg_classes_intersect_p (FP_REGS, rclass);
11316 /* Implement target hook small_register_classes_for_mode_p. */
11319 mips_small_register_classes_for_mode_p (enum machine_mode mode
11322 return TARGET_MIPS16;
11325 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
11328 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode)
11333 return TARGET_HARD_FLOAT;
11336 return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT;
11339 return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT;
11346 /* Implement MODES_TIEABLE_P. */
11349 mips_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
11351 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
11352 prefer to put one of them in FPRs. */
11353 return (mode1 == mode2
11354 || (!mips_mode_ok_for_mov_fmt_p (mode1)
11355 && !mips_mode_ok_for_mov_fmt_p (mode2)));
11358 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
11361 mips_preferred_reload_class (rtx x, reg_class_t rclass)
11363 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, rclass))
11366 if (reg_class_subset_p (FP_REGS, rclass)
11367 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x)))
11370 if (reg_class_subset_p (GR_REGS, rclass))
11373 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, rclass))
11379 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
11380 Return a "canonical" class to represent it in later calculations. */
11383 mips_canonicalize_move_class (reg_class_t rclass)
11385 /* All moves involving accumulator registers have the same cost. */
11386 if (reg_class_subset_p (rclass, ACC_REGS))
11389 /* Likewise promote subclasses of general registers to the most
11390 interesting containing class. */
11391 if (TARGET_MIPS16 && reg_class_subset_p (rclass, M16_REGS))
11393 else if (reg_class_subset_p (rclass, GENERAL_REGS))
11394 rclass = GENERAL_REGS;
11399 /* Return the cost of moving a value of mode MODE from a register of
11400 class FROM to a GPR. Return 0 for classes that are unions of other
11401 classes handled by this function. */
11404 mips_move_to_gpr_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
11410 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
11414 /* MFLO and MFHI. */
11422 /* LUI followed by MOVF. */
11428 /* This choice of value is historical. */
11436 /* Return the cost of moving a value of mode MODE from a GPR to a
11437 register of class TO. Return 0 for classes that are unions of
11438 other classes handled by this function. */
11441 mips_move_from_gpr_cost (enum machine_mode mode, reg_class_t to)
11446 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
11450 /* MTLO and MTHI. */
11458 /* A secondary reload through an FPR scratch. */
11459 return (mips_register_move_cost (mode, GENERAL_REGS, FP_REGS)
11460 + mips_register_move_cost (mode, FP_REGS, ST_REGS));
11465 /* This choice of value is historical. */
11473 /* Implement TARGET_REGISTER_MOVE_COST. Return 0 for classes that are the
11474 maximum of the move costs for subclasses; regclass will work out
11475 the maximum for us. */
11478 mips_register_move_cost (enum machine_mode mode,
11479 reg_class_t from, reg_class_t to)
11484 from = mips_canonicalize_move_class (from);
11485 to = mips_canonicalize_move_class (to);
11487 /* Handle moves that can be done without using general-purpose registers. */
11488 if (from == FP_REGS)
11490 if (to == FP_REGS && mips_mode_ok_for_mov_fmt_p (mode))
11494 /* The sequence generated by mips_expand_fcc_reload. */
11498 /* Handle cases in which only one class deviates from the ideal. */
11499 dregs = TARGET_MIPS16 ? M16_REGS : GENERAL_REGS;
11501 return mips_move_from_gpr_cost (mode, to);
11503 return mips_move_to_gpr_cost (mode, from);
11505 /* Handles cases that require a GPR temporary. */
11506 cost1 = mips_move_to_gpr_cost (mode, from);
11509 cost2 = mips_move_from_gpr_cost (mode, to);
11511 return cost1 + cost2;
11517 /* Implement TARGET_MEMORY_MOVE_COST. */
11520 mips_memory_move_cost (enum machine_mode mode, reg_class_t rclass, bool in)
11522 return (mips_cost->memory_latency
11523 + memory_move_secondary_cost (mode, rclass, in));
11526 /* Return the register class required for a secondary register when
11527 copying between one of the registers in RCLASS and value X, which
11528 has mode MODE. X is the source of the move if IN_P, otherwise it
11529 is the destination. Return NO_REGS if no secondary register is
11533 mips_secondary_reload_class (enum reg_class rclass,
11534 enum machine_mode mode, rtx x, bool in_p)
11538 /* If X is a constant that cannot be loaded into $25, it must be loaded
11539 into some other GPR. No other register class allows a direct move. */
11540 if (mips_dangerous_for_la25_p (x))
11541 return reg_class_subset_p (rclass, LEA_REGS) ? NO_REGS : LEA_REGS;
11543 regno = true_regnum (x);
11546 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
11547 if (!reg_class_subset_p (rclass, M16_REGS) && !M16_REG_P (regno))
11553 /* Copying from accumulator registers to anywhere other than a general
11554 register requires a temporary general register. */
11555 if (reg_class_subset_p (rclass, ACC_REGS))
11556 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
11557 if (ACC_REG_P (regno))
11558 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
11560 /* We can only copy a value to a condition code register from a
11561 floating-point register, and even then we require a scratch
11562 floating-point register. We can only copy a value out of a
11563 condition-code register into a general register. */
11564 if (reg_class_subset_p (rclass, ST_REGS))
11568 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
11570 if (ST_REG_P (regno))
11574 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
11577 if (reg_class_subset_p (rclass, FP_REGS))
11580 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8))
11581 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
11582 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
11585 if (GP_REG_P (regno) || x == CONST0_RTX (mode))
11586 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
11589 if (CONSTANT_P (x) && !targetm.cannot_force_const_mem (mode, x))
11590 /* We can force the constant to memory and use lwc1
11591 and ldc1. As above, we will use pairs of lwc1s if
11592 ldc1 is not supported. */
11595 if (FP_REG_P (regno) && mips_mode_ok_for_mov_fmt_p (mode))
11596 /* In this case we can use mov.fmt. */
11599 /* Otherwise, we need to reload through an integer register. */
11602 if (FP_REG_P (regno))
11603 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
11608 /* Implement TARGET_MODE_REP_EXTENDED. */
11611 mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
11613 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
11614 if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
11615 return SIGN_EXTEND;
11620 /* Implement TARGET_VALID_POINTER_MODE. */
11623 mips_valid_pointer_mode (enum machine_mode mode)
11625 return mode == SImode || (TARGET_64BIT && mode == DImode);
11628 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
11631 mips_vector_mode_supported_p (enum machine_mode mode)
11636 return TARGET_PAIRED_SINGLE_FLOAT;
11651 return TARGET_LOONGSON_VECTORS;
11658 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
11661 mips_scalar_mode_supported_p (enum machine_mode mode)
11663 if (ALL_FIXED_POINT_MODE_P (mode)
11664 && GET_MODE_PRECISION (mode) <= 2 * BITS_PER_WORD)
11667 return default_scalar_mode_supported_p (mode);
11670 /* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
11672 static enum machine_mode
11673 mips_preferred_simd_mode (enum machine_mode mode ATTRIBUTE_UNUSED)
11675 if (TARGET_PAIRED_SINGLE_FLOAT
11681 /* Implement TARGET_INIT_LIBFUNCS. */
11684 mips_init_libfuncs (void)
11686 if (TARGET_FIX_VR4120)
11688 /* Register the special divsi3 and modsi3 functions needed to work
11689 around VR4120 division errata. */
11690 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
11691 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
11694 if (TARGET_MIPS16 && TARGET_HARD_FLOAT_ABI)
11696 /* Register the MIPS16 -mhard-float stubs. */
11697 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
11698 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
11699 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
11700 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
11702 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
11703 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
11704 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
11705 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
11706 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
11707 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
11708 set_optab_libfunc (unord_optab, SFmode, "__mips16_unordsf2");
11710 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
11711 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
11712 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__mips16_floatunsisf");
11714 if (TARGET_DOUBLE_FLOAT)
11716 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
11717 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
11718 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
11719 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
11721 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
11722 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
11723 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
11724 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
11725 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
11726 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
11727 set_optab_libfunc (unord_optab, DFmode, "__mips16_unorddf2");
11729 set_conv_libfunc (sext_optab, DFmode, SFmode,
11730 "__mips16_extendsfdf2");
11731 set_conv_libfunc (trunc_optab, SFmode, DFmode,
11732 "__mips16_truncdfsf2");
11733 set_conv_libfunc (sfix_optab, SImode, DFmode,
11734 "__mips16_fix_truncdfsi");
11735 set_conv_libfunc (sfloat_optab, DFmode, SImode,
11736 "__mips16_floatsidf");
11737 set_conv_libfunc (ufloat_optab, DFmode, SImode,
11738 "__mips16_floatunsidf");
11742 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
11743 on an external non-MIPS16 routine to implement __sync_synchronize.
11744 Similarly for the rest of the ll/sc libfuncs. */
11747 synchronize_libfunc = init_one_libfunc ("__sync_synchronize");
11748 init_sync_libfuncs (UNITS_PER_WORD);
11752 /* Build up a multi-insn sequence that loads label TARGET into $AT. */
11755 mips_process_load_label (rtx target)
11757 rtx base, gp, intop;
11758 HOST_WIDE_INT offset;
11760 mips_multi_start ();
11764 mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target, 0);
11765 mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target, 0);
11769 mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target, 0);
11770 mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target, 0);
11774 gp = pic_offset_table_rtx;
11775 if (mips_cfun_has_cprestore_slot_p ())
11777 gp = gen_rtx_REG (Pmode, AT_REGNUM);
11778 mips_get_cprestore_base_and_offset (&base, &offset, true);
11779 if (!SMALL_OPERAND (offset))
11781 intop = GEN_INT (CONST_HIGH_PART (offset));
11782 mips_multi_add_insn ("lui\t%0,%1", gp, intop, 0);
11783 mips_multi_add_insn ("addu\t%0,%0,%1", gp, base, 0);
11786 offset = CONST_LOW_PART (offset);
11788 intop = GEN_INT (offset);
11789 if (ISA_HAS_LOAD_DELAY)
11790 mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp, intop, base, 0);
11792 mips_multi_add_insn ("lw\t%0,%1(%2)", gp, intop, base, 0);
11794 if (ISA_HAS_LOAD_DELAY)
11795 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target, gp, 0);
11797 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target, gp, 0);
11798 mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target, 0);
11803 /* Return the number of instructions needed to load a label into $AT. */
11805 static unsigned int
11806 mips_load_label_num_insns (void)
11808 if (cfun->machine->load_label_num_insns == 0)
11810 mips_process_load_label (pc_rtx);
11811 cfun->machine->load_label_num_insns = mips_multi_num_insns;
11813 return cfun->machine->load_label_num_insns;
11816 /* Emit an asm sequence to start a noat block and load the address
11817 of a label into $1. */
11820 mips_output_load_label (rtx target)
11822 mips_push_asm_switch (&mips_noat);
11823 if (TARGET_EXPLICIT_RELOCS)
11825 mips_process_load_label (target);
11826 mips_multi_write ();
11830 if (Pmode == DImode)
11831 output_asm_insn ("dla\t%@,%0", &target);
11833 output_asm_insn ("la\t%@,%0", &target);
11837 /* Return the length of INSN. LENGTH is the initial length computed by
11838 attributes in the machine-description file. */
11841 mips_adjust_insn_length (rtx insn, int length)
11843 /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length
11844 of a PIC long-branch sequence. Substitute the correct value. */
11845 if (length == MAX_PIC_BRANCH_LENGTH
11846 && INSN_CODE (insn) >= 0
11847 && get_attr_type (insn) == TYPE_BRANCH)
11849 /* Add the branch-over instruction and its delay slot, if this
11850 is a conditional branch. */
11851 length = simplejump_p (insn) ? 0 : 8;
11853 /* Load the label into $AT and jump to it. Ignore the delay
11854 slot of the jump. */
11855 length += 4 * mips_load_label_num_insns() + 4;
11858 /* A unconditional jump has an unfilled delay slot if it is not part
11859 of a sequence. A conditional jump normally has a delay slot, but
11860 does not on MIPS16. */
11861 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
11864 /* See how many nops might be needed to avoid hardware hazards. */
11865 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
11866 switch (get_attr_hazard (insn))
11880 /* In order to make it easier to share MIPS16 and non-MIPS16 patterns,
11881 the .md file length attributes are 4-based for both modes.
11882 Adjust the MIPS16 ones here. */
11889 /* Return the assembly code for INSN, which has the operands given by
11890 OPERANDS, and which branches to OPERANDS[0] if some condition is true.
11891 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0]
11892 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
11893 version of BRANCH_IF_TRUE. */
11896 mips_output_conditional_branch (rtx insn, rtx *operands,
11897 const char *branch_if_true,
11898 const char *branch_if_false)
11900 unsigned int length;
11901 rtx taken, not_taken;
11903 gcc_assert (LABEL_P (operands[0]));
11905 length = get_attr_length (insn);
11908 /* Just a simple conditional branch. */
11909 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
11910 return branch_if_true;
11913 /* Generate a reversed branch around a direct jump. This fallback does
11914 not use branch-likely instructions. */
11915 mips_branch_likely = false;
11916 not_taken = gen_label_rtx ();
11917 taken = operands[0];
11919 /* Generate the reversed branch to NOT_TAKEN. */
11920 operands[0] = not_taken;
11921 output_asm_insn (branch_if_false, operands);
11923 /* If INSN has a delay slot, we must provide delay slots for both the
11924 branch to NOT_TAKEN and the conditional jump. We must also ensure
11925 that INSN's delay slot is executed in the appropriate cases. */
11926 if (final_sequence)
11928 /* This first delay slot will always be executed, so use INSN's
11929 delay slot if is not annulled. */
11930 if (!INSN_ANNULLED_BRANCH_P (insn))
11932 final_scan_insn (XVECEXP (final_sequence, 0, 1),
11933 asm_out_file, optimize, 1, NULL);
11934 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
11937 output_asm_insn ("nop", 0);
11938 fprintf (asm_out_file, "\n");
11941 /* Output the unconditional branch to TAKEN. */
11942 if (TARGET_ABSOLUTE_JUMPS)
11943 output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken);
11946 mips_output_load_label (taken);
11947 output_asm_insn ("jr\t%@%]%/", 0);
11950 /* Now deal with its delay slot; see above. */
11951 if (final_sequence)
11953 /* This delay slot will only be executed if the branch is taken.
11954 Use INSN's delay slot if is annulled. */
11955 if (INSN_ANNULLED_BRANCH_P (insn))
11957 final_scan_insn (XVECEXP (final_sequence, 0, 1),
11958 asm_out_file, optimize, 1, NULL);
11959 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
11962 output_asm_insn ("nop", 0);
11963 fprintf (asm_out_file, "\n");
11966 /* Output NOT_TAKEN. */
11967 targetm.asm_out.internal_label (asm_out_file, "L",
11968 CODE_LABEL_NUMBER (not_taken));
11972 /* Return the assembly code for INSN, which branches to OPERANDS[0]
11973 if some ordering condition is true. The condition is given by
11974 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
11975 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
11976 its second is always zero. */
11979 mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
11981 const char *branch[2];
11983 /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true.
11984 Make BRANCH[0] branch on the inverse condition. */
11985 switch (GET_CODE (operands[1]))
11987 /* These cases are equivalent to comparisons against zero. */
11989 inverted_p = !inverted_p;
11990 /* Fall through. */
11992 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%0");
11993 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%0");
11996 /* These cases are always true or always false. */
11998 inverted_p = !inverted_p;
11999 /* Fall through. */
12001 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%0");
12002 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%0");
12006 branch[!inverted_p] = MIPS_BRANCH ("b%C1z", "%2,%0");
12007 branch[inverted_p] = MIPS_BRANCH ("b%N1z", "%2,%0");
12010 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
12013 /* Start a block of code that needs access to the LL, SC and SYNC
12017 mips_start_ll_sc_sync_block (void)
12019 if (!ISA_HAS_LL_SC)
12021 output_asm_insn (".set\tpush", 0);
12022 output_asm_insn (".set\tmips2", 0);
12026 /* End a block started by mips_start_ll_sc_sync_block. */
12029 mips_end_ll_sc_sync_block (void)
12031 if (!ISA_HAS_LL_SC)
12032 output_asm_insn (".set\tpop", 0);
12035 /* Output and/or return the asm template for a sync instruction. */
12038 mips_output_sync (void)
12040 mips_start_ll_sc_sync_block ();
12041 output_asm_insn ("sync", 0);
12042 mips_end_ll_sc_sync_block ();
12046 /* Return the asm template associated with sync_insn1 value TYPE.
12047 IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */
12049 static const char *
12050 mips_sync_insn1_template (enum attr_sync_insn1 type, bool is_64bit_p)
12054 case SYNC_INSN1_MOVE:
12055 return "move\t%0,%z2";
12056 case SYNC_INSN1_LI:
12057 return "li\t%0,%2";
12058 case SYNC_INSN1_ADDU:
12059 return is_64bit_p ? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2";
12060 case SYNC_INSN1_ADDIU:
12061 return is_64bit_p ? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2";
12062 case SYNC_INSN1_SUBU:
12063 return is_64bit_p ? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2";
12064 case SYNC_INSN1_AND:
12065 return "and\t%0,%1,%z2";
12066 case SYNC_INSN1_ANDI:
12067 return "andi\t%0,%1,%2";
12068 case SYNC_INSN1_OR:
12069 return "or\t%0,%1,%z2";
12070 case SYNC_INSN1_ORI:
12071 return "ori\t%0,%1,%2";
12072 case SYNC_INSN1_XOR:
12073 return "xor\t%0,%1,%z2";
12074 case SYNC_INSN1_XORI:
12075 return "xori\t%0,%1,%2";
12077 gcc_unreachable ();
12080 /* Return the asm template associated with sync_insn2 value TYPE. */
12082 static const char *
12083 mips_sync_insn2_template (enum attr_sync_insn2 type)
12087 case SYNC_INSN2_NOP:
12088 gcc_unreachable ();
12089 case SYNC_INSN2_AND:
12090 return "and\t%0,%1,%z2";
12091 case SYNC_INSN2_XOR:
12092 return "xor\t%0,%1,%z2";
12093 case SYNC_INSN2_NOT:
12094 return "nor\t%0,%1,%.";
12096 gcc_unreachable ();
12099 /* OPERANDS are the operands to a sync loop instruction and INDEX is
12100 the value of the one of the sync_* attributes. Return the operand
12101 referred to by the attribute, or DEFAULT_VALUE if the insn doesn't
12102 have the associated attribute. */
12105 mips_get_sync_operand (rtx *operands, int index, rtx default_value)
12108 default_value = operands[index - 1];
12109 return default_value;
12112 /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn
12113 sequence for it. */
12116 mips_process_sync_loop (rtx insn, rtx *operands)
12118 rtx at, mem, oldval, newval, inclusive_mask, exclusive_mask;
12119 rtx required_oldval, insn1_op2, tmp1, tmp2, tmp3, cmp;
12120 unsigned int tmp3_insn;
12121 enum attr_sync_insn1 insn1;
12122 enum attr_sync_insn2 insn2;
12125 enum memmodel model;
12127 /* Read an operand from the sync_WHAT attribute and store it in
12128 variable WHAT. DEFAULT is the default value if no attribute
12130 #define READ_OPERAND(WHAT, DEFAULT) \
12131 WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \
12134 /* Read the memory. */
12135 READ_OPERAND (mem, 0);
12137 is_64bit_p = (GET_MODE_BITSIZE (GET_MODE (mem)) == 64);
12139 /* Read the other attributes. */
12140 at = gen_rtx_REG (GET_MODE (mem), AT_REGNUM);
12141 READ_OPERAND (oldval, at);
12142 READ_OPERAND (cmp, 0);
12143 READ_OPERAND (newval, at);
12144 READ_OPERAND (inclusive_mask, 0);
12145 READ_OPERAND (exclusive_mask, 0);
12146 READ_OPERAND (required_oldval, 0);
12147 READ_OPERAND (insn1_op2, 0);
12148 insn1 = get_attr_sync_insn1 (insn);
12149 insn2 = get_attr_sync_insn2 (insn);
12151 /* Don't bother setting CMP result that is never used. */
12152 if (cmp && find_reg_note (insn, REG_UNUSED, cmp))
12155 memmodel_attr = get_attr_sync_memmodel (insn);
12156 switch (memmodel_attr)
12159 model = MEMMODEL_ACQ_REL;
12162 model = MEMMODEL_ACQUIRE;
12165 model = (enum memmodel) INTVAL (operands[memmodel_attr]);
12168 mips_multi_start ();
12170 /* Output the release side of the memory barrier. */
12171 if (need_atomic_barrier_p (model, true))
12173 if (required_oldval == 0 && TARGET_OCTEON)
12175 /* Octeon doesn't reorder reads, so a full barrier can be
12176 created by using SYNCW to order writes combined with the
12177 write from the following SC. When the SC successfully
12178 completes, we know that all preceding writes are also
12179 committed to the coherent memory system. It is possible
12180 for a single SYNCW to fail, but a pair of them will never
12181 fail, so we use two. */
12182 mips_multi_add_insn ("syncw", NULL);
12183 mips_multi_add_insn ("syncw", NULL);
12186 mips_multi_add_insn ("sync", NULL);
12189 /* Output the branch-back label. */
12190 mips_multi_add_label ("1:");
12192 /* OLDVAL = *MEM. */
12193 mips_multi_add_insn (is_64bit_p ? "lld\t%0,%1" : "ll\t%0,%1",
12194 oldval, mem, NULL);
12196 /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */
12197 if (required_oldval)
12199 if (inclusive_mask == 0)
12203 gcc_assert (oldval != at);
12204 mips_multi_add_insn ("and\t%0,%1,%2",
12205 at, oldval, inclusive_mask, NULL);
12208 mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1, required_oldval, NULL);
12210 /* CMP = 0 [delay slot]. */
12212 mips_multi_add_insn ("li\t%0,0", cmp, NULL);
12215 /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */
12216 if (exclusive_mask == 0)
12220 gcc_assert (oldval != at);
12221 mips_multi_add_insn ("and\t%0,%1,%z2",
12222 at, oldval, exclusive_mask, NULL);
12226 /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2).
12228 We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit
12229 at least one instruction in that case. */
12230 if (insn1 == SYNC_INSN1_MOVE
12231 && (tmp1 != const0_rtx || insn2 != SYNC_INSN2_NOP))
12235 mips_multi_add_insn (mips_sync_insn1_template (insn1, is_64bit_p),
12236 newval, oldval, insn1_op2, NULL);
12240 /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */
12241 if (insn2 == SYNC_INSN2_NOP)
12245 mips_multi_add_insn (mips_sync_insn2_template (insn2),
12246 newval, tmp2, inclusive_mask, NULL);
12249 tmp3_insn = mips_multi_last_index ();
12251 /* $AT = $TMP1 | $TMP3. */
12252 if (tmp1 == const0_rtx || tmp3 == const0_rtx)
12254 mips_multi_set_operand (tmp3_insn, 0, at);
12259 gcc_assert (tmp1 != tmp3);
12260 mips_multi_add_insn ("or\t%0,%1,%2", at, tmp1, tmp3, NULL);
12263 /* if (!commit (*MEM = $AT)) goto 1.
12265 This will sometimes be a delayed branch; see the write code below
12267 mips_multi_add_insn (is_64bit_p ? "scd\t%0,%1" : "sc\t%0,%1", at, mem, NULL);
12268 mips_multi_add_insn ("beq%?\t%0,%.,1b", at, NULL);
12270 /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */
12271 if (insn1 != SYNC_INSN1_MOVE && insn1 != SYNC_INSN1_LI && tmp3 != newval)
12273 mips_multi_copy_insn (tmp3_insn);
12274 mips_multi_set_operand (mips_multi_last_index (), 0, newval);
12276 else if (!(required_oldval && cmp))
12277 mips_multi_add_insn ("nop", NULL);
12279 /* CMP = 1 -- either standalone or in a delay slot. */
12280 if (required_oldval && cmp)
12281 mips_multi_add_insn ("li\t%0,1", cmp, NULL);
12283 /* Output the acquire side of the memory barrier. */
12284 if (TARGET_SYNC_AFTER_SC && need_atomic_barrier_p (model, false))
12285 mips_multi_add_insn ("sync", NULL);
12287 /* Output the exit label, if needed. */
12288 if (required_oldval)
12289 mips_multi_add_label ("2:");
12291 #undef READ_OPERAND
12294 /* Output and/or return the asm template for sync loop INSN, which has
12295 the operands given by OPERANDS. */
12298 mips_output_sync_loop (rtx insn, rtx *operands)
12300 mips_process_sync_loop (insn, operands);
12302 /* Use branch-likely instructions to work around the LL/SC R10000
12304 mips_branch_likely = TARGET_FIX_R10000;
12306 mips_push_asm_switch (&mips_noreorder);
12307 mips_push_asm_switch (&mips_nomacro);
12308 mips_push_asm_switch (&mips_noat);
12309 mips_start_ll_sc_sync_block ();
12311 mips_multi_write ();
12313 mips_end_ll_sc_sync_block ();
12314 mips_pop_asm_switch (&mips_noat);
12315 mips_pop_asm_switch (&mips_nomacro);
12316 mips_pop_asm_switch (&mips_noreorder);
12321 /* Return the number of individual instructions in sync loop INSN,
12322 which has the operands given by OPERANDS. */
12325 mips_sync_loop_insns (rtx insn, rtx *operands)
12327 mips_process_sync_loop (insn, operands);
12328 return mips_multi_num_insns;
12331 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
12332 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
12334 When working around R4000 and R4400 errata, we need to make sure that
12335 the division is not immediately followed by a shift[1][2]. We also
12336 need to stop the division from being put into a branch delay slot[3].
12337 The easiest way to avoid both problems is to add a nop after the
12338 division. When a divide-by-zero check is needed, this nop can be
12339 used to fill the branch delay slot.
12341 [1] If a double-word or a variable shift executes immediately
12342 after starting an integer division, the shift may give an
12343 incorrect result. See quotations of errata #16 and #28 from
12344 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
12345 in mips.md for details.
12347 [2] A similar bug to [1] exists for all revisions of the
12348 R4000 and the R4400 when run in an MC configuration.
12349 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
12351 "19. In this following sequence:
12353 ddiv (or ddivu or div or divu)
12354 dsll32 (or dsrl32, dsra32)
12356 if an MPT stall occurs, while the divide is slipping the cpu
12357 pipeline, then the following double shift would end up with an
12360 Workaround: The compiler needs to avoid generating any
12361 sequence with divide followed by extended double shift."
12363 This erratum is also present in "MIPS R4400MC Errata, Processor
12364 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
12365 & 3.0" as errata #10 and #4, respectively.
12367 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
12368 (also valid for MIPS R4000MC processors):
12370 "52. R4000SC: This bug does not apply for the R4000PC.
12372 There are two flavors of this bug:
12374 1) If the instruction just after divide takes an RF exception
12375 (tlb-refill, tlb-invalid) and gets an instruction cache
12376 miss (both primary and secondary) and the line which is
12377 currently in secondary cache at this index had the first
12378 data word, where the bits 5..2 are set, then R4000 would
12379 get a wrong result for the div.
12384 ------------------- # end-of page. -tlb-refill
12389 ------------------- # end-of page. -tlb-invalid
12392 2) If the divide is in the taken branch delay slot, where the
12393 target takes RF exception and gets an I-cache miss for the
12394 exception vector or where I-cache miss occurs for the
12395 target address, under the above mentioned scenarios, the
12396 div would get wrong results.
12399 j r2 # to next page mapped or unmapped
12400 div r8,r9 # this bug would be there as long
12401 # as there is an ICache miss and
12402 nop # the "data pattern" is present
12405 beq r0, r0, NextPage # to Next page
12409 This bug is present for div, divu, ddiv, and ddivu
12412 Workaround: For item 1), OS could make sure that the next page
12413 after the divide instruction is also mapped. For item 2), the
12414 compiler could make sure that the divide instruction is not in
12415 the branch delay slot."
12417 These processors have PRId values of 0x00004220 and 0x00004300 for
12418 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
12421 mips_output_division (const char *division, rtx *operands)
12426 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
12428 output_asm_insn (s, operands);
12431 if (TARGET_CHECK_ZERO_DIV)
12435 output_asm_insn (s, operands);
12436 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
12438 else if (GENERATE_DIVIDE_TRAPS)
12440 /* Avoid long replay penalty on load miss by putting the trap before
12443 output_asm_insn ("teq\t%2,%.,7", operands);
12446 output_asm_insn (s, operands);
12447 s = "teq\t%2,%.,7";
12452 output_asm_insn ("%(bne\t%2,%.,1f", operands);
12453 output_asm_insn (s, operands);
12454 s = "break\t7%)\n1:";
12460 /* Return true if IN_INSN is a multiply-add or multiply-subtract
12461 instruction and if OUT_INSN assigns to the accumulator operand. */
12464 mips_linked_madd_p (rtx out_insn, rtx in_insn)
12466 enum attr_accum_in accum_in;
12467 int accum_in_opnum;
12470 if (recog_memoized (in_insn) < 0)
12473 accum_in = get_attr_accum_in (in_insn);
12474 if (accum_in == ACCUM_IN_NONE)
12477 accum_in_opnum = accum_in - ACCUM_IN_0;
12479 extract_insn (in_insn);
12480 gcc_assert (accum_in_opnum < recog_data.n_operands);
12481 accum_in_op = recog_data.operand[accum_in_opnum];
12483 return reg_set_p (accum_in_op, out_insn);
12486 /* True if the dependency between OUT_INSN and IN_INSN is on the store
12487 data rather than the address. We need this because the cprestore
12488 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
12489 which causes the default routine to abort. We just return false
12493 mips_store_data_bypass_p (rtx out_insn, rtx in_insn)
12495 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
12498 return !store_data_bypass_p (out_insn, in_insn);
12502 /* Variables and flags used in scheduler hooks when tuning for
12506 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
12509 /* If true, then next ALU1/2 instruction will go to ALU1. */
12512 /* If true, then next FALU1/2 unstruction will go to FALU1. */
12515 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
12516 int alu1_core_unit_code;
12517 int alu2_core_unit_code;
12518 int falu1_core_unit_code;
12519 int falu2_core_unit_code;
12521 /* True if current cycle has a multi instruction.
12522 This flag is used in mips_ls2_dfa_post_advance_cycle. */
12523 bool cycle_has_multi_p;
12525 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
12526 These are used in mips_ls2_dfa_post_advance_cycle to initialize
12528 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
12529 instruction to go ALU1. */
12530 rtx alu1_turn_enabled_insn;
12531 rtx alu2_turn_enabled_insn;
12532 rtx falu1_turn_enabled_insn;
12533 rtx falu2_turn_enabled_insn;
12536 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
12537 dependencies have no cost, except on the 20Kc where output-dependence
12538 is treated like input-dependence. */
12541 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
12542 rtx dep ATTRIBUTE_UNUSED, int cost)
12544 if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT
12547 if (REG_NOTE_KIND (link) != 0)
12552 /* Return the number of instructions that can be issued per cycle. */
12555 mips_issue_rate (void)
12559 case PROCESSOR_74KC:
12560 case PROCESSOR_74KF2_1:
12561 case PROCESSOR_74KF1_1:
12562 case PROCESSOR_74KF3_2:
12563 /* The 74k is not strictly quad-issue cpu, but can be seen as one
12564 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
12565 but in reality only a maximum of 3 insns can be issued as
12566 floating-point loads and stores also require a slot in the
12568 case PROCESSOR_R10000:
12569 /* All R10K Processors are quad-issue (being the first MIPS
12570 processors to support this feature). */
12573 case PROCESSOR_20KC:
12574 case PROCESSOR_R4130:
12575 case PROCESSOR_R5400:
12576 case PROCESSOR_R5500:
12577 case PROCESSOR_R7000:
12578 case PROCESSOR_R9000:
12579 case PROCESSOR_OCTEON:
12580 case PROCESSOR_OCTEON2:
12583 case PROCESSOR_SB1:
12584 case PROCESSOR_SB1A:
12585 /* This is actually 4, but we get better performance if we claim 3.
12586 This is partly because of unwanted speculative code motion with the
12587 larger number, and partly because in most common cases we can't
12588 reach the theoretical max of 4. */
12591 case PROCESSOR_LOONGSON_2E:
12592 case PROCESSOR_LOONGSON_2F:
12593 case PROCESSOR_LOONGSON_3A:
12596 case PROCESSOR_XLP:
12597 return (reload_completed ? 4 : 3);
12604 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
12607 mips_ls2_init_dfa_post_cycle_insn (void)
12610 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
12611 mips_ls2.alu1_turn_enabled_insn = get_insns ();
12615 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
12616 mips_ls2.alu2_turn_enabled_insn = get_insns ();
12620 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
12621 mips_ls2.falu1_turn_enabled_insn = get_insns ();
12625 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
12626 mips_ls2.falu2_turn_enabled_insn = get_insns ();
12629 mips_ls2.alu1_core_unit_code = get_cpu_unit_code ("ls2_alu1_core");
12630 mips_ls2.alu2_core_unit_code = get_cpu_unit_code ("ls2_alu2_core");
12631 mips_ls2.falu1_core_unit_code = get_cpu_unit_code ("ls2_falu1_core");
12632 mips_ls2.falu2_core_unit_code = get_cpu_unit_code ("ls2_falu2_core");
12635 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
12636 Init data used in mips_dfa_post_advance_cycle. */
12639 mips_init_dfa_post_cycle_insn (void)
12641 if (TUNE_LOONGSON_2EF)
12642 mips_ls2_init_dfa_post_cycle_insn ();
12645 /* Initialize STATE when scheduling for Loongson 2E/2F.
12646 Support round-robin dispatch scheme by enabling only one of
12647 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
12651 mips_ls2_dfa_post_advance_cycle (state_t state)
12653 if (cpu_unit_reservation_p (state, mips_ls2.alu1_core_unit_code))
12655 /* Though there are no non-pipelined ALU1 insns,
12656 we can get an instruction of type 'multi' before reload. */
12657 gcc_assert (mips_ls2.cycle_has_multi_p);
12658 mips_ls2.alu1_turn_p = false;
12661 mips_ls2.cycle_has_multi_p = false;
12663 if (cpu_unit_reservation_p (state, mips_ls2.alu2_core_unit_code))
12664 /* We have a non-pipelined alu instruction in the core,
12665 adjust round-robin counter. */
12666 mips_ls2.alu1_turn_p = true;
12668 if (mips_ls2.alu1_turn_p)
12670 if (state_transition (state, mips_ls2.alu1_turn_enabled_insn) >= 0)
12671 gcc_unreachable ();
12675 if (state_transition (state, mips_ls2.alu2_turn_enabled_insn) >= 0)
12676 gcc_unreachable ();
12679 if (cpu_unit_reservation_p (state, mips_ls2.falu1_core_unit_code))
12681 /* There are no non-pipelined FALU1 insns. */
12682 gcc_unreachable ();
12683 mips_ls2.falu1_turn_p = false;
12686 if (cpu_unit_reservation_p (state, mips_ls2.falu2_core_unit_code))
12687 /* We have a non-pipelined falu instruction in the core,
12688 adjust round-robin counter. */
12689 mips_ls2.falu1_turn_p = true;
12691 if (mips_ls2.falu1_turn_p)
12693 if (state_transition (state, mips_ls2.falu1_turn_enabled_insn) >= 0)
12694 gcc_unreachable ();
12698 if (state_transition (state, mips_ls2.falu2_turn_enabled_insn) >= 0)
12699 gcc_unreachable ();
12703 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
12704 This hook is being called at the start of each cycle. */
12707 mips_dfa_post_advance_cycle (void)
12709 if (TUNE_LOONGSON_2EF)
12710 mips_ls2_dfa_post_advance_cycle (curr_state);
12713 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
12714 be as wide as the scheduling freedom in the DFA. */
12717 mips_multipass_dfa_lookahead (void)
12719 /* Can schedule up to 4 of the 6 function units in any one cycle. */
12723 if (TUNE_LOONGSON_2EF || TUNE_LOONGSON_3A)
12732 /* Remove the instruction at index LOWER from ready queue READY and
12733 reinsert it in front of the instruction at index HIGHER. LOWER must
12737 mips_promote_ready (rtx *ready, int lower, int higher)
12742 new_head = ready[lower];
12743 for (i = lower; i < higher; i++)
12744 ready[i] = ready[i + 1];
12745 ready[i] = new_head;
12748 /* If the priority of the instruction at POS2 in the ready queue READY
12749 is within LIMIT units of that of the instruction at POS1, swap the
12750 instructions if POS2 is not already less than POS1. */
12753 mips_maybe_swap_ready (rtx *ready, int pos1, int pos2, int limit)
12756 && INSN_PRIORITY (ready[pos1]) + limit >= INSN_PRIORITY (ready[pos2]))
12760 temp = ready[pos1];
12761 ready[pos1] = ready[pos2];
12762 ready[pos2] = temp;
12766 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
12767 that may clobber hi or lo. */
12768 static rtx mips_macc_chains_last_hilo;
12770 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
12771 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
12774 mips_macc_chains_record (rtx insn)
12776 if (get_attr_may_clobber_hilo (insn))
12777 mips_macc_chains_last_hilo = insn;
12780 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
12781 has NREADY elements, looking for a multiply-add or multiply-subtract
12782 instruction that is cumulative with mips_macc_chains_last_hilo.
12783 If there is one, promote it ahead of anything else that might
12784 clobber hi or lo. */
12787 mips_macc_chains_reorder (rtx *ready, int nready)
12791 if (mips_macc_chains_last_hilo != 0)
12792 for (i = nready - 1; i >= 0; i--)
12793 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
12795 for (j = nready - 1; j > i; j--)
12796 if (recog_memoized (ready[j]) >= 0
12797 && get_attr_may_clobber_hilo (ready[j]))
12799 mips_promote_ready (ready, i, j);
12806 /* The last instruction to be scheduled. */
12807 static rtx vr4130_last_insn;
12809 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
12810 points to an rtx that is initially an instruction. Nullify the rtx
12811 if the instruction uses the value of register X. */
12814 vr4130_true_reg_dependence_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
12819 insn_ptr = (rtx *) data;
12822 && reg_referenced_p (x, PATTERN (*insn_ptr)))
12826 /* Return true if there is true register dependence between vr4130_last_insn
12830 vr4130_true_reg_dependence_p (rtx insn)
12832 note_stores (PATTERN (vr4130_last_insn),
12833 vr4130_true_reg_dependence_p_1, &insn);
12837 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
12838 the ready queue and that INSN2 is the instruction after it, return
12839 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
12840 in which INSN1 and INSN2 can probably issue in parallel, but for
12841 which (INSN2, INSN1) should be less sensitive to instruction
12842 alignment than (INSN1, INSN2). See 4130.md for more details. */
12845 vr4130_swap_insns_p (rtx insn1, rtx insn2)
12847 sd_iterator_def sd_it;
12850 /* Check for the following case:
12852 1) there is some other instruction X with an anti dependence on INSN1;
12853 2) X has a higher priority than INSN2; and
12854 3) X is an arithmetic instruction (and thus has no unit restrictions).
12856 If INSN1 is the last instruction blocking X, it would better to
12857 choose (INSN1, X) over (INSN2, INSN1). */
12858 FOR_EACH_DEP (insn1, SD_LIST_FORW, sd_it, dep)
12859 if (DEP_TYPE (dep) == REG_DEP_ANTI
12860 && INSN_PRIORITY (DEP_CON (dep)) > INSN_PRIORITY (insn2)
12861 && recog_memoized (DEP_CON (dep)) >= 0
12862 && get_attr_vr4130_class (DEP_CON (dep)) == VR4130_CLASS_ALU)
12865 if (vr4130_last_insn != 0
12866 && recog_memoized (insn1) >= 0
12867 && recog_memoized (insn2) >= 0)
12869 /* See whether INSN1 and INSN2 use different execution units,
12870 or if they are both ALU-type instructions. If so, they can
12871 probably execute in parallel. */
12872 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
12873 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
12874 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
12876 /* If only one of the instructions has a dependence on
12877 vr4130_last_insn, prefer to schedule the other one first. */
12878 bool dep1_p = vr4130_true_reg_dependence_p (insn1);
12879 bool dep2_p = vr4130_true_reg_dependence_p (insn2);
12880 if (dep1_p != dep2_p)
12883 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
12884 is not an ALU-type instruction and if INSN1 uses the same
12885 execution unit. (Note that if this condition holds, we already
12886 know that INSN2 uses a different execution unit.) */
12887 if (class1 != VR4130_CLASS_ALU
12888 && recog_memoized (vr4130_last_insn) >= 0
12889 && class1 == get_attr_vr4130_class (vr4130_last_insn))
12896 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
12897 queue with at least two instructions. Swap the first two if
12898 vr4130_swap_insns_p says that it could be worthwhile. */
12901 vr4130_reorder (rtx *ready, int nready)
12903 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
12904 mips_promote_ready (ready, nready - 2, nready - 1);
12907 /* Record whether last 74k AGEN instruction was a load or store. */
12908 static enum attr_type mips_last_74k_agen_insn = TYPE_UNKNOWN;
12910 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
12911 resets to TYPE_UNKNOWN state. */
12914 mips_74k_agen_init (rtx insn)
12916 if (!insn || CALL_P (insn) || JUMP_P (insn))
12917 mips_last_74k_agen_insn = TYPE_UNKNOWN;
12920 enum attr_type type = get_attr_type (insn);
12921 if (type == TYPE_LOAD || type == TYPE_STORE)
12922 mips_last_74k_agen_insn = type;
12926 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
12927 loads to be grouped together, and multiple stores to be grouped
12928 together. Swap things around in the ready queue to make this happen. */
12931 mips_74k_agen_reorder (rtx *ready, int nready)
12934 int store_pos, load_pos;
12939 for (i = nready - 1; i >= 0; i--)
12941 rtx insn = ready[i];
12942 if (USEFUL_INSN_P (insn))
12943 switch (get_attr_type (insn))
12946 if (store_pos == -1)
12951 if (load_pos == -1)
12960 if (load_pos == -1 || store_pos == -1)
12963 switch (mips_last_74k_agen_insn)
12966 /* Prefer to schedule loads since they have a higher latency. */
12968 /* Swap loads to the front of the queue. */
12969 mips_maybe_swap_ready (ready, load_pos, store_pos, 4);
12972 /* Swap stores to the front of the queue. */
12973 mips_maybe_swap_ready (ready, store_pos, load_pos, 4);
12980 /* Implement TARGET_SCHED_INIT. */
12983 mips_sched_init (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12984 int max_ready ATTRIBUTE_UNUSED)
12986 mips_macc_chains_last_hilo = 0;
12987 vr4130_last_insn = 0;
12988 mips_74k_agen_init (NULL_RTX);
12990 /* When scheduling for Loongson2, branch instructions go to ALU1,
12991 therefore basic block is most likely to start with round-robin counter
12992 pointed to ALU2. */
12993 mips_ls2.alu1_turn_p = false;
12994 mips_ls2.falu1_turn_p = true;
12997 /* Subroutine used by TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
13000 mips_sched_reorder_1 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13001 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
13003 if (!reload_completed
13004 && TUNE_MACC_CHAINS
13006 mips_macc_chains_reorder (ready, *nreadyp);
13008 if (reload_completed
13010 && !TARGET_VR4130_ALIGN
13012 vr4130_reorder (ready, *nreadyp);
13015 mips_74k_agen_reorder (ready, *nreadyp);
13018 /* Implement TARGET_SCHED_REORDER. */
13021 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13022 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
13024 mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle);
13025 return mips_issue_rate ();
13028 /* Implement TARGET_SCHED_REORDER2. */
13031 mips_sched_reorder2 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13032 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
13034 mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle);
13035 return cached_can_issue_more;
13038 /* Update round-robin counters for ALU1/2 and FALU1/2. */
13041 mips_ls2_variable_issue (rtx insn)
13043 if (mips_ls2.alu1_turn_p)
13045 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu1_core_unit_code))
13046 mips_ls2.alu1_turn_p = false;
13050 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu2_core_unit_code))
13051 mips_ls2.alu1_turn_p = true;
13054 if (mips_ls2.falu1_turn_p)
13056 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu1_core_unit_code))
13057 mips_ls2.falu1_turn_p = false;
13061 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu2_core_unit_code))
13062 mips_ls2.falu1_turn_p = true;
13065 if (recog_memoized (insn) >= 0)
13066 mips_ls2.cycle_has_multi_p |= (get_attr_type (insn) == TYPE_MULTI);
13069 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
13072 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13073 rtx insn, int more)
13075 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
13076 if (USEFUL_INSN_P (insn))
13078 if (get_attr_type (insn) != TYPE_GHOST)
13080 if (!reload_completed && TUNE_MACC_CHAINS)
13081 mips_macc_chains_record (insn);
13082 vr4130_last_insn = insn;
13084 mips_74k_agen_init (insn);
13085 else if (TUNE_LOONGSON_2EF)
13086 mips_ls2_variable_issue (insn);
13089 /* Instructions of type 'multi' should all be split before
13090 the second scheduling pass. */
13091 gcc_assert (!reload_completed
13092 || recog_memoized (insn) < 0
13093 || get_attr_type (insn) != TYPE_MULTI);
13095 cached_can_issue_more = more;
13099 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
13100 return the first operand of the associated PREF or PREFX insn. */
13103 mips_prefetch_cookie (rtx write, rtx locality)
13105 /* store_streamed / load_streamed. */
13106 if (INTVAL (locality) <= 0)
13107 return GEN_INT (INTVAL (write) + 4);
13109 /* store / load. */
13110 if (INTVAL (locality) <= 2)
13113 /* store_retained / load_retained. */
13114 return GEN_INT (INTVAL (write) + 6);
13117 /* Flags that indicate when a built-in function is available.
13119 BUILTIN_AVAIL_NON_MIPS16
13120 The function is available on the current target, but only
13121 in non-MIPS16 mode. */
13122 #define BUILTIN_AVAIL_NON_MIPS16 1
13124 /* Declare an availability predicate for built-in functions that
13125 require non-MIPS16 mode and also require COND to be true.
13126 NAME is the main part of the predicate's name. */
13127 #define AVAIL_NON_MIPS16(NAME, COND) \
13128 static unsigned int \
13129 mips_builtin_avail_##NAME (void) \
13131 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
13134 /* This structure describes a single built-in function. */
13135 struct mips_builtin_description {
13136 /* The code of the main .md file instruction. See mips_builtin_type
13137 for more information. */
13138 enum insn_code icode;
13140 /* The floating-point comparison code to use with ICODE, if any. */
13141 enum mips_fp_condition cond;
13143 /* The name of the built-in function. */
13146 /* Specifies how the function should be expanded. */
13147 enum mips_builtin_type builtin_type;
13149 /* The function's prototype. */
13150 enum mips_function_type function_type;
13152 /* Whether the function is available. */
13153 unsigned int (*avail) (void);
13156 AVAIL_NON_MIPS16 (paired_single, TARGET_PAIRED_SINGLE_FLOAT)
13157 AVAIL_NON_MIPS16 (sb1_paired_single, TARGET_SB1 && TARGET_PAIRED_SINGLE_FLOAT)
13158 AVAIL_NON_MIPS16 (mips3d, TARGET_MIPS3D)
13159 AVAIL_NON_MIPS16 (dsp, TARGET_DSP)
13160 AVAIL_NON_MIPS16 (dspr2, TARGET_DSPR2)
13161 AVAIL_NON_MIPS16 (dsp_32, !TARGET_64BIT && TARGET_DSP)
13162 AVAIL_NON_MIPS16 (dsp_64, TARGET_64BIT && TARGET_DSP)
13163 AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2)
13164 AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS)
13165 AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
13167 /* Construct a mips_builtin_description from the given arguments.
13169 INSN is the name of the associated instruction pattern, without the
13170 leading CODE_FOR_mips_.
13172 CODE is the floating-point condition code associated with the
13173 function. It can be 'f' if the field is not applicable.
13175 NAME is the name of the function itself, without the leading
13178 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
13180 AVAIL is the name of the availability predicate, without the leading
13181 mips_builtin_avail_. */
13182 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
13183 FUNCTION_TYPE, AVAIL) \
13184 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
13185 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
13186 mips_builtin_avail_ ## AVAIL }
13188 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
13189 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
13190 are as for MIPS_BUILTIN. */
13191 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
13192 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
13194 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
13195 are subject to mips_builtin_avail_<AVAIL>. */
13196 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
13197 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
13198 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
13199 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
13200 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
13202 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
13203 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
13204 while the any and all forms are subject to mips_builtin_avail_mips3d. */
13205 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
13206 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
13207 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
13209 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
13210 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
13212 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
13213 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
13215 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
13216 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
13219 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
13220 are subject to mips_builtin_avail_mips3d. */
13221 #define CMP_4S_BUILTINS(INSN, COND) \
13222 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
13223 MIPS_BUILTIN_CMP_ANY, \
13224 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
13225 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
13226 MIPS_BUILTIN_CMP_ALL, \
13227 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
13229 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
13230 instruction requires mips_builtin_avail_<AVAIL>. */
13231 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
13232 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
13233 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
13235 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
13236 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
13239 /* Define all the built-in functions related to C.cond.fmt condition COND. */
13240 #define CMP_BUILTINS(COND) \
13241 MOVTF_BUILTINS (c, COND, paired_single), \
13242 MOVTF_BUILTINS (cabs, COND, mips3d), \
13243 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
13244 CMP_PS_BUILTINS (c, COND, paired_single), \
13245 CMP_PS_BUILTINS (cabs, COND, mips3d), \
13246 CMP_4S_BUILTINS (c, COND), \
13247 CMP_4S_BUILTINS (cabs, COND)
13249 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
13250 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
13251 and AVAIL are as for MIPS_BUILTIN. */
13252 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
13253 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
13254 FUNCTION_TYPE, AVAIL)
13256 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
13257 branch instruction. AVAIL is as for MIPS_BUILTIN. */
13258 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
13259 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
13260 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
13262 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
13263 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
13264 builtin_description field. */
13265 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
13266 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
13267 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
13268 FUNCTION_TYPE, mips_builtin_avail_loongson }
13270 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
13271 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
13272 builtin_description field. */
13273 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
13274 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
13276 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
13277 We use functions of this form when the same insn can be usefully applied
13278 to more than one datatype. */
13279 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
13280 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
13282 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
13283 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
13284 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
13285 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
13286 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
13287 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
13288 #define CODE_FOR_mips_mult CODE_FOR_mulsidi3_32bit
13289 #define CODE_FOR_mips_multu CODE_FOR_umulsidi3_32bit
13291 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
13292 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
13293 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
13294 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
13295 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
13296 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
13297 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
13298 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
13299 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
13300 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
13301 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
13302 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
13303 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
13304 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
13305 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
13306 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
13307 #define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3
13308 #define CODE_FOR_loongson_psllh CODE_FOR_ashlv4hi3
13309 #define CODE_FOR_loongson_psllw CODE_FOR_ashlv2si3
13310 #define CODE_FOR_loongson_psrlh CODE_FOR_lshrv4hi3
13311 #define CODE_FOR_loongson_psrlw CODE_FOR_lshrv2si3
13312 #define CODE_FOR_loongson_psrah CODE_FOR_ashrv4hi3
13313 #define CODE_FOR_loongson_psraw CODE_FOR_ashrv2si3
13314 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
13315 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
13316 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
13317 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
13318 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
13319 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
13320 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
13322 static const struct mips_builtin_description mips_builtins[] = {
13323 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13324 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13325 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13326 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13327 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, paired_single),
13328 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, paired_single),
13329 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, paired_single),
13330 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, paired_single),
13332 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT, paired_single),
13333 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13334 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13335 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
13336 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, mips3d),
13338 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, mips3d),
13339 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, mips3d),
13340 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
13341 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
13342 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
13343 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13345 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, mips3d),
13346 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, mips3d),
13347 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
13348 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
13349 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
13350 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13352 MIPS_FP_CONDITIONS (CMP_BUILTINS),
13354 /* Built-in functions for the SB-1 processor. */
13355 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, sb1_paired_single),
13357 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
13358 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13359 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13360 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
13361 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13362 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13363 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13364 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13365 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
13366 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13367 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13368 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, dsp),
13369 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, dsp),
13370 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, dsp),
13371 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, dsp),
13372 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, dsp),
13373 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, dsp),
13374 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
13375 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
13376 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
13377 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
13378 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, dsp),
13379 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, dsp),
13380 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
13381 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
13382 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
13383 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
13384 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
13385 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
13386 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
13387 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
13388 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
13389 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
13390 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
13391 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
13392 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
13393 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
13394 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
13395 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, dsp),
13396 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
13397 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
13398 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13399 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
13400 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
13401 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, dsp),
13402 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, dsp),
13403 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, dsp),
13404 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, dsp),
13405 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
13406 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
13407 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
13408 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
13409 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
13410 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
13411 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
13412 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
13413 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
13414 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13415 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13416 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13417 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, dsp),
13418 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, dsp),
13419 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_POINTER_SI, dsp),
13420 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_POINTER_SI, dsp),
13421 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_POINTER_SI, dsp),
13422 BPOSGE_BUILTIN (32, dsp),
13424 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
13425 DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, dspr2),
13426 DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13427 DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13428 DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
13429 DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
13430 DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
13431 DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
13432 DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
13433 DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
13434 DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
13435 DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13436 DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13437 DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13438 DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13439 DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13440 DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dspr2),
13441 DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
13442 DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
13443 DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
13444 DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
13445 DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
13446 DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, dspr2),
13447 DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13448 DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13449 DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
13450 DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
13451 DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13452 DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13453 DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13454 DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13455 DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13456 DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13457 DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13458 DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13460 /* Built-in functions for the DSP ASE (32-bit only). */
13461 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
13462 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
13463 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
13464 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
13465 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13466 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13467 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13468 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
13469 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
13470 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13471 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13472 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13473 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13474 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
13475 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
13476 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
13477 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, dsp_32),
13478 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, dsp_32),
13479 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, dsp_32),
13480 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, dsp_32),
13481 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, dsp_32),
13482 DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
13483 DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32),
13484 DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
13485 DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32),
13486 DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, dsp_32),
13487 DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, dsp_32),
13489 /* Built-in functions for the DSP ASE (64-bit only). */
13490 DIRECT_BUILTIN (ldx, MIPS_DI_FTYPE_POINTER_SI, dsp_64),
13492 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
13493 DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13494 DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13495 DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13496 DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13497 DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13498 DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13499 DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13500 DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13501 DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13503 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
13504 LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI),
13505 LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI),
13506 LOONGSON_BUILTIN (packushb, MIPS_UV8QI_FTYPE_UV4HI_UV4HI),
13507 LOONGSON_BUILTIN_SUFFIX (paddw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13508 LOONGSON_BUILTIN_SUFFIX (paddh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13509 LOONGSON_BUILTIN_SUFFIX (paddb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13510 LOONGSON_BUILTIN_SUFFIX (paddw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13511 LOONGSON_BUILTIN_SUFFIX (paddh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13512 LOONGSON_BUILTIN_SUFFIX (paddb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13513 LOONGSON_BUILTIN_SUFFIX (paddd, u, MIPS_UDI_FTYPE_UDI_UDI),
13514 LOONGSON_BUILTIN_SUFFIX (paddd, s, MIPS_DI_FTYPE_DI_DI),
13515 LOONGSON_BUILTIN (paddsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13516 LOONGSON_BUILTIN (paddsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
13517 LOONGSON_BUILTIN (paddush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13518 LOONGSON_BUILTIN (paddusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13519 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_ud, MIPS_UDI_FTYPE_UDI_UDI),
13520 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_uw, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13521 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_uh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13522 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_ub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13523 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_sd, MIPS_DI_FTYPE_DI_DI),
13524 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_sw, MIPS_V2SI_FTYPE_V2SI_V2SI),
13525 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_sh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13526 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_sb, MIPS_V8QI_FTYPE_V8QI_V8QI),
13527 LOONGSON_BUILTIN (pavgh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13528 LOONGSON_BUILTIN (pavgb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13529 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13530 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13531 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13532 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13533 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13534 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13535 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13536 LOONGSON_BUILTIN_SUFFIX (pcmpgth, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13537 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13538 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13539 LOONGSON_BUILTIN_SUFFIX (pcmpgth, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13540 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13541 LOONGSON_BUILTIN_SUFFIX (pextrh, u, MIPS_UV4HI_FTYPE_UV4HI_USI),
13542 LOONGSON_BUILTIN_SUFFIX (pextrh, s, MIPS_V4HI_FTYPE_V4HI_USI),
13543 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13544 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13545 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13546 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13547 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13548 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13549 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13550 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13551 LOONGSON_BUILTIN (pmaddhw, MIPS_V2SI_FTYPE_V4HI_V4HI),
13552 LOONGSON_BUILTIN (pmaxsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13553 LOONGSON_BUILTIN (pmaxub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13554 LOONGSON_BUILTIN (pminsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13555 LOONGSON_BUILTIN (pminub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13556 LOONGSON_BUILTIN_SUFFIX (pmovmskb, u, MIPS_UV8QI_FTYPE_UV8QI),
13557 LOONGSON_BUILTIN_SUFFIX (pmovmskb, s, MIPS_V8QI_FTYPE_V8QI),
13558 LOONGSON_BUILTIN (pmulhuh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13559 LOONGSON_BUILTIN (pmulhh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13560 LOONGSON_BUILTIN (pmullh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13561 LOONGSON_BUILTIN (pmuluw, MIPS_UDI_FTYPE_UV2SI_UV2SI),
13562 LOONGSON_BUILTIN (pasubub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13563 LOONGSON_BUILTIN (biadd, MIPS_UV4HI_FTYPE_UV8QI),
13564 LOONGSON_BUILTIN (psadbh, MIPS_UV4HI_FTYPE_UV8QI_UV8QI),
13565 LOONGSON_BUILTIN_SUFFIX (pshufh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
13566 LOONGSON_BUILTIN_SUFFIX (pshufh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
13567 LOONGSON_BUILTIN_SUFFIX (psllh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
13568 LOONGSON_BUILTIN_SUFFIX (psllh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
13569 LOONGSON_BUILTIN_SUFFIX (psllw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
13570 LOONGSON_BUILTIN_SUFFIX (psllw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
13571 LOONGSON_BUILTIN_SUFFIX (psrah, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
13572 LOONGSON_BUILTIN_SUFFIX (psrah, s, MIPS_V4HI_FTYPE_V4HI_UQI),
13573 LOONGSON_BUILTIN_SUFFIX (psraw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
13574 LOONGSON_BUILTIN_SUFFIX (psraw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
13575 LOONGSON_BUILTIN_SUFFIX (psrlh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
13576 LOONGSON_BUILTIN_SUFFIX (psrlh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
13577 LOONGSON_BUILTIN_SUFFIX (psrlw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
13578 LOONGSON_BUILTIN_SUFFIX (psrlw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
13579 LOONGSON_BUILTIN_SUFFIX (psubw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13580 LOONGSON_BUILTIN_SUFFIX (psubh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13581 LOONGSON_BUILTIN_SUFFIX (psubb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13582 LOONGSON_BUILTIN_SUFFIX (psubw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13583 LOONGSON_BUILTIN_SUFFIX (psubh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13584 LOONGSON_BUILTIN_SUFFIX (psubb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13585 LOONGSON_BUILTIN_SUFFIX (psubd, u, MIPS_UDI_FTYPE_UDI_UDI),
13586 LOONGSON_BUILTIN_SUFFIX (psubd, s, MIPS_DI_FTYPE_DI_DI),
13587 LOONGSON_BUILTIN (psubsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13588 LOONGSON_BUILTIN (psubsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
13589 LOONGSON_BUILTIN (psubush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13590 LOONGSON_BUILTIN (psubusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13591 LOONGSON_BUILTIN_SUFFIX (punpckhbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13592 LOONGSON_BUILTIN_SUFFIX (punpckhhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13593 LOONGSON_BUILTIN_SUFFIX (punpckhwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13594 LOONGSON_BUILTIN_SUFFIX (punpckhbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13595 LOONGSON_BUILTIN_SUFFIX (punpckhhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13596 LOONGSON_BUILTIN_SUFFIX (punpckhwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13597 LOONGSON_BUILTIN_SUFFIX (punpcklbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13598 LOONGSON_BUILTIN_SUFFIX (punpcklhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13599 LOONGSON_BUILTIN_SUFFIX (punpcklwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13600 LOONGSON_BUILTIN_SUFFIX (punpcklbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13601 LOONGSON_BUILTIN_SUFFIX (punpcklhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13602 LOONGSON_BUILTIN_SUFFIX (punpcklwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13604 /* Sundry other built-in functions. */
13605 DIRECT_NO_TARGET_BUILTIN (cache, MIPS_VOID_FTYPE_SI_CVPOINTER, cache)
13608 /* Index I is the function declaration for mips_builtins[I], or null if the
13609 function isn't defined on this target. */
13610 static GTY(()) tree mips_builtin_decls[ARRAY_SIZE (mips_builtins)];
13612 /* MODE is a vector mode whose elements have type TYPE. Return the type
13613 of the vector itself. */
13616 mips_builtin_vector_type (tree type, enum machine_mode mode)
13618 static tree types[2 * (int) MAX_MACHINE_MODE];
13621 mode_index = (int) mode;
13623 if (TREE_CODE (type) == INTEGER_TYPE && TYPE_UNSIGNED (type))
13624 mode_index += MAX_MACHINE_MODE;
13626 if (types[mode_index] == NULL_TREE)
13627 types[mode_index] = build_vector_type_for_mode (type, mode);
13628 return types[mode_index];
13631 /* Return a type for 'const volatile void *'. */
13634 mips_build_cvpointer_type (void)
13638 if (cache == NULL_TREE)
13639 cache = build_pointer_type (build_qualified_type
13641 TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE));
13645 /* Source-level argument types. */
13646 #define MIPS_ATYPE_VOID void_type_node
13647 #define MIPS_ATYPE_INT integer_type_node
13648 #define MIPS_ATYPE_POINTER ptr_type_node
13649 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
13651 /* Standard mode-based argument types. */
13652 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
13653 #define MIPS_ATYPE_SI intSI_type_node
13654 #define MIPS_ATYPE_USI unsigned_intSI_type_node
13655 #define MIPS_ATYPE_DI intDI_type_node
13656 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
13657 #define MIPS_ATYPE_SF float_type_node
13658 #define MIPS_ATYPE_DF double_type_node
13660 /* Vector argument types. */
13661 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
13662 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
13663 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
13664 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
13665 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
13666 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
13667 #define MIPS_ATYPE_UV2SI \
13668 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
13669 #define MIPS_ATYPE_UV4HI \
13670 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
13671 #define MIPS_ATYPE_UV8QI \
13672 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
13674 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
13675 their associated MIPS_ATYPEs. */
13676 #define MIPS_FTYPE_ATYPES1(A, B) \
13677 MIPS_ATYPE_##A, MIPS_ATYPE_##B
13679 #define MIPS_FTYPE_ATYPES2(A, B, C) \
13680 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
13682 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
13683 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
13685 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
13686 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
13689 /* Return the function type associated with function prototype TYPE. */
13692 mips_build_function_type (enum mips_function_type type)
13694 static tree types[(int) MIPS_MAX_FTYPE_MAX];
13696 if (types[(int) type] == NULL_TREE)
13699 #define DEF_MIPS_FTYPE(NUM, ARGS) \
13700 case MIPS_FTYPE_NAME##NUM ARGS: \
13701 types[(int) type] \
13702 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
13705 #include "config/mips/mips-ftypes.def"
13706 #undef DEF_MIPS_FTYPE
13708 gcc_unreachable ();
13711 return types[(int) type];
13714 /* Implement TARGET_INIT_BUILTINS. */
13717 mips_init_builtins (void)
13719 const struct mips_builtin_description *d;
13722 /* Iterate through all of the bdesc arrays, initializing all of the
13723 builtin functions. */
13724 for (i = 0; i < ARRAY_SIZE (mips_builtins); i++)
13726 d = &mips_builtins[i];
13728 mips_builtin_decls[i]
13729 = add_builtin_function (d->name,
13730 mips_build_function_type (d->function_type),
13731 i, BUILT_IN_MD, NULL, NULL);
13735 /* Implement TARGET_BUILTIN_DECL. */
13738 mips_builtin_decl (unsigned int code, bool initialize_p ATTRIBUTE_UNUSED)
13740 if (code >= ARRAY_SIZE (mips_builtins))
13741 return error_mark_node;
13742 return mips_builtin_decls[code];
13745 /* Take argument ARGNO from EXP's argument list and convert it into
13746 an expand operand. Store the operand in *OP. */
13749 mips_prepare_builtin_arg (struct expand_operand *op, tree exp,
13750 unsigned int argno)
13755 arg = CALL_EXPR_ARG (exp, argno);
13756 value = expand_normal (arg);
13757 create_input_operand (op, value, TYPE_MODE (TREE_TYPE (arg)));
13760 /* Expand instruction ICODE as part of a built-in function sequence.
13761 Use the first NOPS elements of OPS as the instruction's operands.
13762 HAS_TARGET_P is true if operand 0 is a target; it is false if the
13763 instruction has no target.
13765 Return the target rtx if HAS_TARGET_P, otherwise return const0_rtx. */
13768 mips_expand_builtin_insn (enum insn_code icode, unsigned int nops,
13769 struct expand_operand *ops, bool has_target_p)
13771 if (!maybe_expand_insn (icode, nops, ops))
13773 error ("invalid argument to built-in function");
13774 return has_target_p ? gen_reg_rtx (ops[0].mode) : const0_rtx;
13776 return has_target_p ? ops[0].value : const0_rtx;
13779 /* Expand a floating-point comparison for built-in function call EXP.
13780 The first NARGS arguments are the values to be compared. ICODE is
13781 the .md pattern that does the comparison and COND is the condition
13782 that is being tested. Return an rtx for the result. */
13785 mips_expand_builtin_compare_1 (enum insn_code icode,
13786 enum mips_fp_condition cond,
13787 tree exp, int nargs)
13789 struct expand_operand ops[MAX_RECOG_OPERANDS];
13793 /* The instruction should have a target operand, an operand for each
13794 argument, and an operand for COND. */
13795 gcc_assert (nargs + 2 == insn_data[(int) icode].n_generator_args);
13797 output = mips_allocate_fcc (insn_data[(int) icode].operand[0].mode);
13799 create_fixed_operand (&ops[opno++], output);
13800 for (argno = 0; argno < nargs; argno++)
13801 mips_prepare_builtin_arg (&ops[opno++], exp, argno);
13802 create_integer_operand (&ops[opno++], (int) cond);
13803 return mips_expand_builtin_insn (icode, opno, ops, true);
13806 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
13807 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
13808 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
13809 suggests a good place to put the result. */
13812 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
13815 struct expand_operand ops[MAX_RECOG_OPERANDS];
13818 /* Map any target to operand 0. */
13821 create_output_operand (&ops[opno++], target, TYPE_MODE (TREE_TYPE (exp)));
13823 /* Map the arguments to the other operands. */
13824 gcc_assert (opno + call_expr_nargs (exp)
13825 == insn_data[icode].n_generator_args);
13826 for (argno = 0; argno < call_expr_nargs (exp); argno++)
13827 mips_prepare_builtin_arg (&ops[opno++], exp, argno);
13829 return mips_expand_builtin_insn (icode, opno, ops, has_target_p);
13832 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
13833 function; TYPE says which. EXP is the CALL_EXPR that calls the
13834 function, ICODE is the instruction that should be used to compare
13835 the first two arguments, and COND is the condition it should test.
13836 TARGET, if nonnull, suggests a good place to put the result. */
13839 mips_expand_builtin_movtf (enum mips_builtin_type type,
13840 enum insn_code icode, enum mips_fp_condition cond,
13841 rtx target, tree exp)
13843 struct expand_operand ops[4];
13846 cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp, 2);
13847 create_output_operand (&ops[0], target, TYPE_MODE (TREE_TYPE (exp)));
13848 if (type == MIPS_BUILTIN_MOVT)
13850 mips_prepare_builtin_arg (&ops[2], exp, 2);
13851 mips_prepare_builtin_arg (&ops[1], exp, 3);
13855 mips_prepare_builtin_arg (&ops[1], exp, 2);
13856 mips_prepare_builtin_arg (&ops[2], exp, 3);
13858 create_fixed_operand (&ops[3], cmp_result);
13859 return mips_expand_builtin_insn (CODE_FOR_mips_cond_move_tf_ps,
13863 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
13864 into TARGET otherwise. Return TARGET. */
13867 mips_builtin_branch_and_move (rtx condition, rtx target,
13868 rtx value_if_true, rtx value_if_false)
13870 rtx true_label, done_label;
13872 true_label = gen_label_rtx ();
13873 done_label = gen_label_rtx ();
13875 /* First assume that CONDITION is false. */
13876 mips_emit_move (target, value_if_false);
13878 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
13879 emit_jump_insn (gen_condjump (condition, true_label));
13880 emit_jump_insn (gen_jump (done_label));
13883 /* Fix TARGET if CONDITION is true. */
13884 emit_label (true_label);
13885 mips_emit_move (target, value_if_true);
13887 emit_label (done_label);
13891 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
13892 the CALL_EXPR that calls the function, ICODE is the code of the
13893 comparison instruction, and COND is the condition it should test.
13894 TARGET, if nonnull, suggests a good place to put the boolean result. */
13897 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
13898 enum insn_code icode, enum mips_fp_condition cond,
13899 rtx target, tree exp)
13901 rtx offset, condition, cmp_result;
13903 if (target == 0 || GET_MODE (target) != SImode)
13904 target = gen_reg_rtx (SImode);
13905 cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp,
13906 call_expr_nargs (exp));
13908 /* If the comparison sets more than one register, we define the result
13909 to be 0 if all registers are false and -1 if all registers are true.
13910 The value of the complete result is indeterminate otherwise. */
13911 switch (builtin_type)
13913 case MIPS_BUILTIN_CMP_ALL:
13914 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
13915 return mips_builtin_branch_and_move (condition, target,
13916 const0_rtx, const1_rtx);
13918 case MIPS_BUILTIN_CMP_UPPER:
13919 case MIPS_BUILTIN_CMP_LOWER:
13920 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
13921 condition = gen_single_cc (cmp_result, offset);
13922 return mips_builtin_branch_and_move (condition, target,
13923 const1_rtx, const0_rtx);
13926 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
13927 return mips_builtin_branch_and_move (condition, target,
13928 const1_rtx, const0_rtx);
13932 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
13933 if nonnull, suggests a good place to put the boolean result. */
13936 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
13938 rtx condition, cmp_result;
13941 if (target == 0 || GET_MODE (target) != SImode)
13942 target = gen_reg_rtx (SImode);
13944 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
13946 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
13951 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
13952 return mips_builtin_branch_and_move (condition, target,
13953 const1_rtx, const0_rtx);
13956 /* Implement TARGET_EXPAND_BUILTIN. */
13959 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
13960 enum machine_mode mode, int ignore)
13963 unsigned int fcode, avail;
13964 const struct mips_builtin_description *d;
13966 fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
13967 fcode = DECL_FUNCTION_CODE (fndecl);
13968 gcc_assert (fcode < ARRAY_SIZE (mips_builtins));
13969 d = &mips_builtins[fcode];
13970 avail = d->avail ();
13971 gcc_assert (avail != 0);
13974 error ("built-in function %qE not supported for MIPS16",
13975 DECL_NAME (fndecl));
13976 return ignore ? const0_rtx : CONST0_RTX (mode);
13978 switch (d->builtin_type)
13980 case MIPS_BUILTIN_DIRECT:
13981 return mips_expand_builtin_direct (d->icode, target, exp, true);
13983 case MIPS_BUILTIN_DIRECT_NO_TARGET:
13984 return mips_expand_builtin_direct (d->icode, target, exp, false);
13986 case MIPS_BUILTIN_MOVT:
13987 case MIPS_BUILTIN_MOVF:
13988 return mips_expand_builtin_movtf (d->builtin_type, d->icode,
13989 d->cond, target, exp);
13991 case MIPS_BUILTIN_CMP_ANY:
13992 case MIPS_BUILTIN_CMP_ALL:
13993 case MIPS_BUILTIN_CMP_UPPER:
13994 case MIPS_BUILTIN_CMP_LOWER:
13995 case MIPS_BUILTIN_CMP_SINGLE:
13996 return mips_expand_builtin_compare (d->builtin_type, d->icode,
13997 d->cond, target, exp);
13999 case MIPS_BUILTIN_BPOSGE32:
14000 return mips_expand_builtin_bposge (d->builtin_type, target);
14002 gcc_unreachable ();
14005 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
14006 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
14007 struct mips16_constant {
14008 struct mips16_constant *next;
14011 enum machine_mode mode;
14014 /* Information about an incomplete MIPS16 constant pool. FIRST is the
14015 first constant, HIGHEST_ADDRESS is the highest address that the first
14016 byte of the pool can have, and INSN_ADDRESS is the current instruction
14018 struct mips16_constant_pool {
14019 struct mips16_constant *first;
14020 int highest_address;
14024 /* Add constant VALUE to POOL and return its label. MODE is the
14025 value's mode (used for CONST_INTs, etc.). */
14028 mips16_add_constant (struct mips16_constant_pool *pool,
14029 rtx value, enum machine_mode mode)
14031 struct mips16_constant **p, *c;
14032 bool first_of_size_p;
14034 /* See whether the constant is already in the pool. If so, return the
14035 existing label, otherwise leave P pointing to the place where the
14036 constant should be added.
14038 Keep the pool sorted in increasing order of mode size so that we can
14039 reduce the number of alignments needed. */
14040 first_of_size_p = true;
14041 for (p = &pool->first; *p != 0; p = &(*p)->next)
14043 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
14044 return (*p)->label;
14045 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
14047 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
14048 first_of_size_p = false;
14051 /* In the worst case, the constant needed by the earliest instruction
14052 will end up at the end of the pool. The entire pool must then be
14053 accessible from that instruction.
14055 When adding the first constant, set the pool's highest address to
14056 the address of the first out-of-range byte. Adjust this address
14057 downwards each time a new constant is added. */
14058 if (pool->first == 0)
14059 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
14060 of the instruction with the lowest two bits clear. The base PC
14061 value for LDPC has the lowest three bits clear. Assume the worst
14062 case here; namely that the PC-relative instruction occupies the
14063 last 2 bytes in an aligned word. */
14064 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
14065 pool->highest_address -= GET_MODE_SIZE (mode);
14066 if (first_of_size_p)
14067 /* Take into account the worst possible padding due to alignment. */
14068 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
14070 /* Create a new entry. */
14071 c = XNEW (struct mips16_constant);
14074 c->label = gen_label_rtx ();
14081 /* Output constant VALUE after instruction INSN and return the last
14082 instruction emitted. MODE is the mode of the constant. */
14085 mips16_emit_constants_1 (enum machine_mode mode, rtx value, rtx insn)
14087 if (SCALAR_INT_MODE_P (mode) || ALL_SCALAR_FIXED_POINT_MODE_P (mode))
14089 rtx size = GEN_INT (GET_MODE_SIZE (mode));
14090 return emit_insn_after (gen_consttable_int (value, size), insn);
14093 if (SCALAR_FLOAT_MODE_P (mode))
14094 return emit_insn_after (gen_consttable_float (value), insn);
14096 if (VECTOR_MODE_P (mode))
14100 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
14101 insn = mips16_emit_constants_1 (GET_MODE_INNER (mode),
14102 CONST_VECTOR_ELT (value, i), insn);
14106 gcc_unreachable ();
14109 /* Dump out the constants in CONSTANTS after INSN. */
14112 mips16_emit_constants (struct mips16_constant *constants, rtx insn)
14114 struct mips16_constant *c, *next;
14118 for (c = constants; c != NULL; c = next)
14120 /* If necessary, increase the alignment of PC. */
14121 if (align < GET_MODE_SIZE (c->mode))
14123 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
14124 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
14126 align = GET_MODE_SIZE (c->mode);
14128 insn = emit_label_after (c->label, insn);
14129 insn = mips16_emit_constants_1 (c->mode, c->value, insn);
14135 emit_barrier_after (insn);
14138 /* Return the length of instruction INSN. */
14141 mips16_insn_length (rtx insn)
14145 rtx body = PATTERN (insn);
14146 if (GET_CODE (body) == ADDR_VEC)
14147 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
14148 if (GET_CODE (body) == ADDR_DIFF_VEC)
14149 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
14151 return get_attr_length (insn);
14154 /* If *X is a symbolic constant that refers to the constant pool, add
14155 the constant to POOL and rewrite *X to use the constant's label. */
14158 mips16_rewrite_pool_constant (struct mips16_constant_pool *pool, rtx *x)
14160 rtx base, offset, label;
14162 split_const (*x, &base, &offset);
14163 if (GET_CODE (base) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (base))
14165 label = mips16_add_constant (pool, copy_rtx (get_pool_constant (base)),
14166 get_pool_mode (base));
14167 base = gen_rtx_LABEL_REF (Pmode, label);
14168 *x = mips_unspec_address_offset (base, offset, SYMBOL_PC_RELATIVE);
14172 /* This structure is used to communicate with mips16_rewrite_pool_refs.
14173 INSN is the instruction we're rewriting and POOL points to the current
14175 struct mips16_rewrite_pool_refs_info {
14177 struct mips16_constant_pool *pool;
14180 /* Rewrite *X so that constant pool references refer to the constant's
14181 label instead. DATA points to a mips16_rewrite_pool_refs_info
14185 mips16_rewrite_pool_refs (rtx *x, void *data)
14187 struct mips16_rewrite_pool_refs_info *info =
14188 (struct mips16_rewrite_pool_refs_info *) data;
14190 if (force_to_mem_operand (*x, Pmode))
14192 rtx mem = force_const_mem (GET_MODE (*x), *x);
14193 validate_change (info->insn, x, mem, false);
14198 mips16_rewrite_pool_constant (info->pool, &XEXP (*x, 0));
14202 /* Don't rewrite the __mips16_rdwr symbol. */
14203 if (GET_CODE (*x) == UNSPEC && XINT (*x, 1) == UNSPEC_TLS_GET_TP)
14206 if (TARGET_MIPS16_TEXT_LOADS)
14207 mips16_rewrite_pool_constant (info->pool, x);
14209 return GET_CODE (*x) == CONST ? -1 : 0;
14212 /* Return whether CFG is used in mips_reorg. */
14215 mips_cfg_in_reorg (void)
14217 return (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
14218 || TARGET_RELAX_PIC_CALLS);
14221 /* Build MIPS16 constant pools. Split the instructions if SPLIT_P,
14222 otherwise assume that they are already split. */
14225 mips16_lay_out_constants (bool split_p)
14227 struct mips16_constant_pool pool;
14228 struct mips16_rewrite_pool_refs_info info;
14231 if (!TARGET_MIPS16_PCREL_LOADS)
14236 if (mips_cfg_in_reorg ())
14237 split_all_insns ();
14239 split_all_insns_noflow ();
14242 memset (&pool, 0, sizeof (pool));
14243 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
14245 /* Rewrite constant pool references in INSN. */
14246 if (USEFUL_INSN_P (insn))
14250 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &info);
14253 pool.insn_address += mips16_insn_length (insn);
14255 if (pool.first != NULL)
14257 /* If there are no natural barriers between the first user of
14258 the pool and the highest acceptable address, we'll need to
14259 create a new instruction to jump around the constant pool.
14260 In the worst case, this instruction will be 4 bytes long.
14262 If it's too late to do this transformation after INSN,
14263 do it immediately before INSN. */
14264 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
14268 label = gen_label_rtx ();
14270 jump = emit_jump_insn_before (gen_jump (label), insn);
14271 JUMP_LABEL (jump) = label;
14272 LABEL_NUSES (label) = 1;
14273 barrier = emit_barrier_after (jump);
14275 emit_label_after (label, barrier);
14276 pool.insn_address += 4;
14279 /* See whether the constant pool is now out of range of the first
14280 user. If so, output the constants after the previous barrier.
14281 Note that any instructions between BARRIER and INSN (inclusive)
14282 will use negative offsets to refer to the pool. */
14283 if (pool.insn_address > pool.highest_address)
14285 mips16_emit_constants (pool.first, barrier);
14289 else if (BARRIER_P (insn))
14293 mips16_emit_constants (pool.first, get_last_insn ());
14296 /* Return true if it is worth r10k_simplify_address's while replacing
14297 an address with X. We are looking for constants, and for addresses
14298 at a known offset from the incoming stack pointer. */
14301 r10k_simplified_address_p (rtx x)
14303 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
14305 return x == virtual_incoming_args_rtx || CONSTANT_P (x);
14308 /* X is an expression that appears in INSN. Try to use the UD chains
14309 to simplify it, returning the simplified form on success and the
14310 original form otherwise. Replace the incoming value of $sp with
14311 virtual_incoming_args_rtx (which should never occur in X otherwise). */
14314 r10k_simplify_address (rtx x, rtx insn)
14316 rtx newx, op0, op1, set, def_insn, note;
14318 struct df_link *defs;
14323 op0 = r10k_simplify_address (XEXP (x, 0), insn);
14324 if (op0 != XEXP (x, 0))
14325 newx = simplify_gen_unary (GET_CODE (x), GET_MODE (x),
14326 op0, GET_MODE (XEXP (x, 0)));
14328 else if (BINARY_P (x))
14330 op0 = r10k_simplify_address (XEXP (x, 0), insn);
14331 op1 = r10k_simplify_address (XEXP (x, 1), insn);
14332 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
14333 newx = simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
14335 else if (GET_CODE (x) == LO_SUM)
14337 /* LO_SUMs can be offset from HIGHs, if we know they won't
14338 overflow. See mips_classify_address for the rationale behind
14340 op0 = r10k_simplify_address (XEXP (x, 0), insn);
14341 if (GET_CODE (op0) == HIGH)
14342 newx = XEXP (x, 1);
14344 else if (REG_P (x))
14346 /* Uses are recorded by regno_reg_rtx, not X itself. */
14347 use = df_find_use (insn, regno_reg_rtx[REGNO (x)]);
14349 defs = DF_REF_CHAIN (use);
14351 /* Require a single definition. */
14352 if (defs && defs->next == NULL)
14355 if (DF_REF_IS_ARTIFICIAL (def))
14357 /* Replace the incoming value of $sp with
14358 virtual_incoming_args_rtx. */
14359 if (x == stack_pointer_rtx
14360 && DF_REF_BB (def) == ENTRY_BLOCK_PTR)
14361 newx = virtual_incoming_args_rtx;
14363 else if (dominated_by_p (CDI_DOMINATORS, DF_REF_BB (use),
14366 /* Make sure that DEF_INSN is a single set of REG. */
14367 def_insn = DF_REF_INSN (def);
14368 if (NONJUMP_INSN_P (def_insn))
14370 set = single_set (def_insn);
14371 if (set && rtx_equal_p (SET_DEST (set), x))
14373 /* Prefer to use notes, since the def-use chains
14374 are often shorter. */
14375 note = find_reg_equal_equiv_note (def_insn);
14377 newx = XEXP (note, 0);
14379 newx = SET_SRC (set);
14380 newx = r10k_simplify_address (newx, def_insn);
14386 if (newx && r10k_simplified_address_p (newx))
14391 /* Return true if ADDRESS is known to be an uncached address
14392 on R10K systems. */
14395 r10k_uncached_address_p (unsigned HOST_WIDE_INT address)
14397 unsigned HOST_WIDE_INT upper;
14399 /* Check for KSEG1. */
14400 if (address + 0x60000000 < 0x20000000)
14403 /* Check for uncached XKPHYS addresses. */
14404 if (Pmode == DImode)
14406 upper = (address >> 40) & 0xf9ffff;
14407 if (upper == 0x900000 || upper == 0xb80000)
14413 /* Return true if we can prove that an access to address X in instruction
14414 INSN would be safe from R10K speculation. This X is a general
14415 expression; it might not be a legitimate address. */
14418 r10k_safe_address_p (rtx x, rtx insn)
14421 HOST_WIDE_INT offset_val;
14423 x = r10k_simplify_address (x, insn);
14425 /* Check for references to the stack frame. It doesn't really matter
14426 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
14427 allows us to assume that accesses to any part of the eventual frame
14428 is safe from speculation at any point in the function. */
14429 mips_split_plus (x, &base, &offset_val);
14430 if (base == virtual_incoming_args_rtx
14431 && offset_val >= -cfun->machine->frame.total_size
14432 && offset_val < cfun->machine->frame.args_size)
14435 /* Check for uncached addresses. */
14436 if (CONST_INT_P (x))
14437 return r10k_uncached_address_p (INTVAL (x));
14439 /* Check for accesses to a static object. */
14440 split_const (x, &base, &offset);
14441 return offset_within_block_p (base, INTVAL (offset));
14444 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
14445 an in-range access to an automatic variable, or to an object with
14446 a link-time-constant address. */
14449 r10k_safe_mem_expr_p (tree expr, HOST_WIDE_INT offset)
14451 HOST_WIDE_INT bitoffset, bitsize;
14452 tree inner, var_offset;
14453 enum machine_mode mode;
14454 int unsigned_p, volatile_p;
14456 inner = get_inner_reference (expr, &bitsize, &bitoffset, &var_offset, &mode,
14457 &unsigned_p, &volatile_p, false);
14458 if (!DECL_P (inner) || !DECL_SIZE_UNIT (inner) || var_offset)
14461 offset += bitoffset / BITS_PER_UNIT;
14462 return offset >= 0 && offset < tree_low_cst (DECL_SIZE_UNIT (inner), 1);
14465 /* A for_each_rtx callback for which DATA points to the instruction
14466 containing *X. Stop the search if we find a MEM that is not safe
14467 from R10K speculation. */
14470 r10k_needs_protection_p_1 (rtx *loc, void *data)
14479 && MEM_OFFSET_KNOWN_P (mem)
14480 && r10k_safe_mem_expr_p (MEM_EXPR (mem), MEM_OFFSET (mem)))
14483 if (r10k_safe_address_p (XEXP (mem, 0), (rtx) data))
14489 /* A note_stores callback for which DATA points to an instruction pointer.
14490 If *DATA is nonnull, make it null if it X contains a MEM that is not
14491 safe from R10K speculation. */
14494 r10k_needs_protection_p_store (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
14499 insn_ptr = (rtx *) data;
14500 if (*insn_ptr && for_each_rtx (&x, r10k_needs_protection_p_1, *insn_ptr))
14501 *insn_ptr = NULL_RTX;
14504 /* A for_each_rtx callback that iterates over the pattern of a CALL_INSN.
14505 Return nonzero if the call is not to a declared function. */
14508 r10k_needs_protection_p_call (rtx *loc, void *data ATTRIBUTE_UNUSED)
14517 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DECL (x))
14523 /* Return true if instruction INSN needs to be protected by an R10K
14527 r10k_needs_protection_p (rtx insn)
14530 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_call, NULL);
14532 if (mips_r10k_cache_barrier == R10K_CACHE_BARRIER_STORE)
14534 note_stores (PATTERN (insn), r10k_needs_protection_p_store, &insn);
14535 return insn == NULL_RTX;
14538 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_1, insn);
14541 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
14542 edge is unconditional. */
14545 r10k_protected_bb_p (basic_block bb, sbitmap protected_bbs)
14550 FOR_EACH_EDGE (e, ei, bb->preds)
14551 if (!single_succ_p (e->src)
14552 || !TEST_BIT (protected_bbs, e->src->index)
14553 || (e->flags & EDGE_COMPLEX) != 0)
14558 /* Implement -mr10k-cache-barrier= for the current function. */
14561 r10k_insert_cache_barriers (void)
14563 int *rev_post_order;
14566 sbitmap protected_bbs;
14567 rtx insn, end, unprotected_region;
14571 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
14575 /* Calculate dominators. */
14576 calculate_dominance_info (CDI_DOMINATORS);
14578 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
14579 X is protected by a cache barrier. */
14580 protected_bbs = sbitmap_alloc (last_basic_block);
14581 sbitmap_zero (protected_bbs);
14583 /* Iterate over the basic blocks in reverse post-order. */
14584 rev_post_order = XNEWVEC (int, last_basic_block);
14585 n = pre_and_rev_post_order_compute (NULL, rev_post_order, false);
14586 for (i = 0; i < n; i++)
14588 bb = BASIC_BLOCK (rev_post_order[i]);
14590 /* If this block is only reached by unconditional edges, and if the
14591 source of every edge is protected, the beginning of the block is
14593 if (r10k_protected_bb_p (bb, protected_bbs))
14594 unprotected_region = NULL_RTX;
14596 unprotected_region = pc_rtx;
14597 end = NEXT_INSN (BB_END (bb));
14599 /* UNPROTECTED_REGION is:
14601 - null if we are processing a protected region,
14602 - pc_rtx if we are processing an unprotected region but have
14603 not yet found the first instruction in it
14604 - the first instruction in an unprotected region otherwise. */
14605 for (insn = BB_HEAD (bb); insn != end; insn = NEXT_INSN (insn))
14607 if (unprotected_region && USEFUL_INSN_P (insn))
14609 if (recog_memoized (insn) == CODE_FOR_mips_cache)
14610 /* This CACHE instruction protects the following code. */
14611 unprotected_region = NULL_RTX;
14614 /* See if INSN is the first instruction in this
14615 unprotected region. */
14616 if (unprotected_region == pc_rtx)
14617 unprotected_region = insn;
14619 /* See if INSN needs to be protected. If so,
14620 we must insert a cache barrier somewhere between
14621 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
14622 clear which position is better performance-wise,
14623 but as a tie-breaker, we assume that it is better
14624 to allow delay slots to be back-filled where
14625 possible, and that it is better not to insert
14626 barriers in the middle of already-scheduled code.
14627 We therefore insert the barrier at the beginning
14629 if (r10k_needs_protection_p (insn))
14631 emit_insn_before (gen_r10k_cache_barrier (),
14632 unprotected_region);
14633 unprotected_region = NULL_RTX;
14639 /* The called function is not required to protect the exit path.
14640 The code that follows a call is therefore unprotected. */
14641 unprotected_region = pc_rtx;
14644 /* Record whether the end of this block is protected. */
14645 if (unprotected_region == NULL_RTX)
14646 SET_BIT (protected_bbs, bb->index);
14648 XDELETEVEC (rev_post_order);
14650 sbitmap_free (protected_bbs);
14652 free_dominance_info (CDI_DOMINATORS);
14655 /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX
14656 otherwise. If INSN has two call rtx, then store the second one in
14660 mips_call_expr_from_insn (rtx insn, rtx *second_call)
14665 if (!CALL_P (insn))
14668 x = PATTERN (insn);
14669 if (GET_CODE (x) == PARALLEL)
14671 /* Calls returning complex values have two CALL rtx. Look for the second
14672 one here, and return it via the SECOND_CALL arg. */
14673 x2 = XVECEXP (x, 0, 1);
14674 if (GET_CODE (x2) == SET)
14676 if (GET_CODE (x2) == CALL)
14679 x = XVECEXP (x, 0, 0);
14681 if (GET_CODE (x) == SET)
14683 gcc_assert (GET_CODE (x) == CALL);
14688 /* REG is set in DEF. See if the definition is one of the ways we load a
14689 register with a symbol address for a mips_use_pic_fn_addr_reg_p call.
14690 If it is, return the symbol reference of the function, otherwise return
14693 If RECURSE_P is true, use mips_find_pic_call_symbol to interpret
14694 the values of source registers, otherwise treat such registers as
14695 having an unknown value. */
14698 mips_pic_call_symbol_from_set (df_ref def, rtx reg, bool recurse_p)
14702 if (DF_REF_IS_ARTIFICIAL (def))
14705 def_insn = DF_REF_INSN (def);
14706 set = single_set (def_insn);
14707 if (set && rtx_equal_p (SET_DEST (set), reg))
14709 rtx note, src, symbol;
14711 /* First see whether the source is a plain symbol. This is used
14712 when calling symbols that are not lazily bound. */
14713 src = SET_SRC (set);
14714 if (GET_CODE (src) == SYMBOL_REF)
14717 /* Handle %call16 references. */
14718 symbol = mips_strip_unspec_call (src);
14721 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
14725 /* If we have something more complicated, look for a
14726 REG_EQUAL or REG_EQUIV note. */
14727 note = find_reg_equal_equiv_note (def_insn);
14728 if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF)
14729 return XEXP (note, 0);
14731 /* Follow at most one simple register copy. Such copies are
14732 interesting in cases like:
14736 locally_binding_fn (...);
14741 locally_binding_fn (...);
14743 locally_binding_fn (...);
14745 where the load of locally_binding_fn can legitimately be
14746 hoisted or shared. However, we do not expect to see complex
14747 chains of copies, so a full worklist solution to the problem
14748 would probably be overkill. */
14749 if (recurse_p && REG_P (src))
14750 return mips_find_pic_call_symbol (def_insn, src, false);
14756 /* Find the definition of the use of REG in INSN. See if the definition
14757 is one of the ways we load a register with a symbol address for a
14758 mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference
14759 of the function, otherwise return NULL_RTX. RECURSE_P is as for
14760 mips_pic_call_symbol_from_set. */
14763 mips_find_pic_call_symbol (rtx insn, rtx reg, bool recurse_p)
14766 struct df_link *defs;
14769 use = df_find_use (insn, regno_reg_rtx[REGNO (reg)]);
14772 defs = DF_REF_CHAIN (use);
14775 symbol = mips_pic_call_symbol_from_set (defs->ref, reg, recurse_p);
14779 /* If we have more than one definition, they need to be identical. */
14780 for (defs = defs->next; defs; defs = defs->next)
14784 other = mips_pic_call_symbol_from_set (defs->ref, reg, recurse_p);
14785 if (!rtx_equal_p (symbol, other))
14792 /* Replace the args_size operand of the call expression CALL with the
14793 call-attribute UNSPEC and fill in SYMBOL as the function symbol. */
14796 mips_annotate_pic_call_expr (rtx call, rtx symbol)
14800 args_size = XEXP (call, 1);
14801 XEXP (call, 1) = gen_rtx_UNSPEC (GET_MODE (args_size),
14802 gen_rtvec (2, args_size, symbol),
14806 /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See
14807 if instead of the arg_size argument it contains the call attributes. If
14808 yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function
14809 symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is
14813 mips_get_pic_call_symbol (rtx *operands, int args_size_opno)
14815 rtx args_size, symbol;
14817 if (!TARGET_RELAX_PIC_CALLS || args_size_opno == -1)
14820 args_size = operands[args_size_opno];
14821 if (GET_CODE (args_size) != UNSPEC)
14823 gcc_assert (XINT (args_size, 1) == UNSPEC_CALL_ATTR);
14825 symbol = XVECEXP (args_size, 0, 1);
14826 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
14828 operands[args_size_opno] = symbol;
14832 /* Use DF to annotate PIC indirect calls with the function symbol they
14836 mips_annotate_pic_calls (void)
14842 FOR_BB_INSNS (bb, insn)
14844 rtx call, reg, symbol, second_call;
14847 call = mips_call_expr_from_insn (insn, &second_call);
14850 gcc_assert (MEM_P (XEXP (call, 0)));
14851 reg = XEXP (XEXP (call, 0), 0);
14855 symbol = mips_find_pic_call_symbol (insn, reg, true);
14858 mips_annotate_pic_call_expr (call, symbol);
14860 mips_annotate_pic_call_expr (second_call, symbol);
14865 /* A temporary variable used by for_each_rtx callbacks, etc. */
14866 static rtx mips_sim_insn;
14868 /* A structure representing the state of the processor pipeline.
14869 Used by the mips_sim_* family of functions. */
14871 /* The maximum number of instructions that can be issued in a cycle.
14872 (Caches mips_issue_rate.) */
14873 unsigned int issue_rate;
14875 /* The current simulation time. */
14878 /* How many more instructions can be issued in the current cycle. */
14879 unsigned int insns_left;
14881 /* LAST_SET[X].INSN is the last instruction to set register X.
14882 LAST_SET[X].TIME is the time at which that instruction was issued.
14883 INSN is null if no instruction has yet set register X. */
14887 } last_set[FIRST_PSEUDO_REGISTER];
14889 /* The pipeline's current DFA state. */
14893 /* Reset STATE to the initial simulation state. */
14896 mips_sim_reset (struct mips_sim *state)
14899 state->insns_left = state->issue_rate;
14900 memset (&state->last_set, 0, sizeof (state->last_set));
14901 state_reset (state->dfa_state);
14904 /* Initialize STATE before its first use. DFA_STATE points to an
14905 allocated but uninitialized DFA state. */
14908 mips_sim_init (struct mips_sim *state, state_t dfa_state)
14910 state->issue_rate = mips_issue_rate ();
14911 state->dfa_state = dfa_state;
14912 mips_sim_reset (state);
14915 /* Advance STATE by one clock cycle. */
14918 mips_sim_next_cycle (struct mips_sim *state)
14921 state->insns_left = state->issue_rate;
14922 state_transition (state->dfa_state, 0);
14925 /* Advance simulation state STATE until instruction INSN can read
14929 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
14931 unsigned int regno, end_regno;
14933 end_regno = END_REGNO (reg);
14934 for (regno = REGNO (reg); regno < end_regno; regno++)
14935 if (state->last_set[regno].insn != 0)
14939 t = (state->last_set[regno].time
14940 + insn_latency (state->last_set[regno].insn, insn));
14941 while (state->time < t)
14942 mips_sim_next_cycle (state);
14946 /* A for_each_rtx callback. If *X is a register, advance simulation state
14947 DATA until mips_sim_insn can read the register's value. */
14950 mips_sim_wait_regs_2 (rtx *x, void *data)
14953 mips_sim_wait_reg ((struct mips_sim *) data, mips_sim_insn, *x);
14957 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
14960 mips_sim_wait_regs_1 (rtx *x, void *data)
14962 for_each_rtx (x, mips_sim_wait_regs_2, data);
14965 /* Advance simulation state STATE until all of INSN's register
14966 dependencies are satisfied. */
14969 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
14971 mips_sim_insn = insn;
14972 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
14975 /* Advance simulation state STATE until the units required by
14976 instruction INSN are available. */
14979 mips_sim_wait_units (struct mips_sim *state, rtx insn)
14983 tmp_state = alloca (state_size ());
14984 while (state->insns_left == 0
14985 || (memcpy (tmp_state, state->dfa_state, state_size ()),
14986 state_transition (tmp_state, insn) >= 0))
14987 mips_sim_next_cycle (state);
14990 /* Advance simulation state STATE until INSN is ready to issue. */
14993 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
14995 mips_sim_wait_regs (state, insn);
14996 mips_sim_wait_units (state, insn);
14999 /* mips_sim_insn has just set X. Update the LAST_SET array
15000 in simulation state DATA. */
15003 mips_sim_record_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
15005 struct mips_sim *state;
15007 state = (struct mips_sim *) data;
15010 unsigned int regno, end_regno;
15012 end_regno = END_REGNO (x);
15013 for (regno = REGNO (x); regno < end_regno; regno++)
15015 state->last_set[regno].insn = mips_sim_insn;
15016 state->last_set[regno].time = state->time;
15021 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
15022 can issue immediately (i.e., that mips_sim_wait_insn has already
15026 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
15028 state_transition (state->dfa_state, insn);
15029 state->insns_left--;
15031 mips_sim_insn = insn;
15032 note_stores (PATTERN (insn), mips_sim_record_set, state);
15035 /* Simulate issuing a NOP in state STATE. */
15038 mips_sim_issue_nop (struct mips_sim *state)
15040 if (state->insns_left == 0)
15041 mips_sim_next_cycle (state);
15042 state->insns_left--;
15045 /* Update simulation state STATE so that it's ready to accept the instruction
15046 after INSN. INSN should be part of the main rtl chain, not a member of a
15050 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
15052 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
15054 mips_sim_issue_nop (state);
15056 switch (GET_CODE (SEQ_BEGIN (insn)))
15060 /* We can't predict the processor state after a call or label. */
15061 mips_sim_reset (state);
15065 /* The delay slots of branch likely instructions are only executed
15066 when the branch is taken. Therefore, if the caller has simulated
15067 the delay slot instruction, STATE does not really reflect the state
15068 of the pipeline for the instruction after the delay slot. Also,
15069 branch likely instructions tend to incur a penalty when not taken,
15070 so there will probably be an extra delay between the branch and
15071 the instruction after the delay slot. */
15072 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
15073 mips_sim_reset (state);
15081 /* The VR4130 pipeline issues aligned pairs of instructions together,
15082 but it stalls the second instruction if it depends on the first.
15083 In order to cut down the amount of logic required, this dependence
15084 check is not based on a full instruction decode. Instead, any non-SPECIAL
15085 instruction is assumed to modify the register specified by bits 20-16
15086 (which is usually the "rt" field).
15088 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
15089 input, so we can end up with a false dependence between the branch
15090 and its delay slot. If this situation occurs in instruction INSN,
15091 try to avoid it by swapping rs and rt. */
15094 vr4130_avoid_branch_rt_conflict (rtx insn)
15098 first = SEQ_BEGIN (insn);
15099 second = SEQ_END (insn);
15101 && NONJUMP_INSN_P (second)
15102 && GET_CODE (PATTERN (first)) == SET
15103 && GET_CODE (SET_DEST (PATTERN (first))) == PC
15104 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
15106 /* Check for the right kind of condition. */
15107 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
15108 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
15109 && REG_P (XEXP (cond, 0))
15110 && REG_P (XEXP (cond, 1))
15111 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
15112 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
15114 /* SECOND mentions the rt register but not the rs register. */
15115 rtx tmp = XEXP (cond, 0);
15116 XEXP (cond, 0) = XEXP (cond, 1);
15117 XEXP (cond, 1) = tmp;
15122 /* Implement -mvr4130-align. Go through each basic block and simulate the
15123 processor pipeline. If we find that a pair of instructions could execute
15124 in parallel, and the first of those instructions is not 8-byte aligned,
15125 insert a nop to make it aligned. */
15128 vr4130_align_insns (void)
15130 struct mips_sim state;
15131 rtx insn, subinsn, last, last2, next;
15136 /* LAST is the last instruction before INSN to have a nonzero length.
15137 LAST2 is the last such instruction before LAST. */
15141 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
15144 mips_sim_init (&state, alloca (state_size ()));
15145 for (insn = get_insns (); insn != 0; insn = next)
15147 unsigned int length;
15149 next = NEXT_INSN (insn);
15151 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
15152 This isn't really related to the alignment pass, but we do it on
15153 the fly to avoid a separate instruction walk. */
15154 vr4130_avoid_branch_rt_conflict (insn);
15156 length = get_attr_length (insn);
15157 if (length > 0 && USEFUL_INSN_P (insn))
15158 FOR_EACH_SUBINSN (subinsn, insn)
15160 mips_sim_wait_insn (&state, subinsn);
15162 /* If we want this instruction to issue in parallel with the
15163 previous one, make sure that the previous instruction is
15164 aligned. There are several reasons why this isn't worthwhile
15165 when the second instruction is a call:
15167 - Calls are less likely to be performance critical,
15168 - There's a good chance that the delay slot can execute
15169 in parallel with the call.
15170 - The return address would then be unaligned.
15172 In general, if we're going to insert a nop between instructions
15173 X and Y, it's better to insert it immediately after X. That
15174 way, if the nop makes Y aligned, it will also align any labels
15175 between X and Y. */
15176 if (state.insns_left != state.issue_rate
15177 && !CALL_P (subinsn))
15179 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
15181 /* SUBINSN is the first instruction in INSN and INSN is
15182 aligned. We want to align the previous instruction
15183 instead, so insert a nop between LAST2 and LAST.
15185 Note that LAST could be either a single instruction
15186 or a branch with a delay slot. In the latter case,
15187 LAST, like INSN, is already aligned, but the delay
15188 slot must have some extra delay that stops it from
15189 issuing at the same time as the branch. We therefore
15190 insert a nop before the branch in order to align its
15192 gcc_assert (last2);
15193 emit_insn_after (gen_nop (), last2);
15196 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
15198 /* SUBINSN is the delay slot of INSN, but INSN is
15199 currently unaligned. Insert a nop between
15200 LAST and INSN to align it. */
15202 emit_insn_after (gen_nop (), last);
15206 mips_sim_issue_insn (&state, subinsn);
15208 mips_sim_finish_insn (&state, insn);
15210 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
15211 length = get_attr_length (insn);
15214 /* If the instruction is an asm statement or multi-instruction
15215 mips.md patern, the length is only an estimate. Insert an
15216 8 byte alignment after it so that the following instructions
15217 can be handled correctly. */
15218 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
15219 && (recog_memoized (insn) < 0 || length >= 8))
15221 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
15222 next = NEXT_INSN (next);
15223 mips_sim_next_cycle (&state);
15226 else if (length & 4)
15227 aligned_p = !aligned_p;
15232 /* See whether INSN is an aligned label. */
15233 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
15239 /* This structure records that the current function has a LO_SUM
15240 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
15241 the largest offset applied to BASE by all such LO_SUMs. */
15242 struct mips_lo_sum_offset {
15244 HOST_WIDE_INT offset;
15247 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
15250 mips_hash_base (rtx base)
15252 int do_not_record_p;
15254 return hash_rtx (base, GET_MODE (base), &do_not_record_p, NULL, false);
15257 /* Hash-table callbacks for mips_lo_sum_offsets. */
15260 mips_lo_sum_offset_hash (const void *entry)
15262 return mips_hash_base (((const struct mips_lo_sum_offset *) entry)->base);
15266 mips_lo_sum_offset_eq (const void *entry, const void *value)
15268 return rtx_equal_p (((const struct mips_lo_sum_offset *) entry)->base,
15269 (const_rtx) value);
15272 /* Look up symbolic constant X in HTAB, which is a hash table of
15273 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
15274 paired with a recorded LO_SUM, otherwise record X in the table. */
15277 mips_lo_sum_offset_lookup (htab_t htab, rtx x, enum insert_option option)
15281 struct mips_lo_sum_offset *entry;
15283 /* Split X into a base and offset. */
15284 split_const (x, &base, &offset);
15285 if (UNSPEC_ADDRESS_P (base))
15286 base = UNSPEC_ADDRESS (base);
15288 /* Look up the base in the hash table. */
15289 slot = htab_find_slot_with_hash (htab, base, mips_hash_base (base), option);
15293 entry = (struct mips_lo_sum_offset *) *slot;
15294 if (option == INSERT)
15298 entry = XNEW (struct mips_lo_sum_offset);
15299 entry->base = base;
15300 entry->offset = INTVAL (offset);
15305 if (INTVAL (offset) > entry->offset)
15306 entry->offset = INTVAL (offset);
15309 return INTVAL (offset) <= entry->offset;
15312 /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table.
15313 Record every LO_SUM in *LOC. */
15316 mips_record_lo_sum (rtx *loc, void *data)
15318 if (GET_CODE (*loc) == LO_SUM)
15319 mips_lo_sum_offset_lookup ((htab_t) data, XEXP (*loc, 1), INSERT);
15323 /* Return true if INSN is a SET of an orphaned high-part relocation.
15324 HTAB is a hash table of mips_lo_sum_offsets that describes all the
15325 LO_SUMs in the current function. */
15328 mips_orphaned_high_part_p (htab_t htab, rtx insn)
15330 enum mips_symbol_type type;
15333 set = single_set (insn);
15336 /* Check for %his. */
15338 if (GET_CODE (x) == HIGH
15339 && absolute_symbolic_operand (XEXP (x, 0), VOIDmode))
15340 return !mips_lo_sum_offset_lookup (htab, XEXP (x, 0), NO_INSERT);
15342 /* Check for local %gots (and %got_pages, which is redundant but OK). */
15343 if (GET_CODE (x) == UNSPEC
15344 && XINT (x, 1) == UNSPEC_LOAD_GOT
15345 && mips_symbolic_constant_p (XVECEXP (x, 0, 1),
15346 SYMBOL_CONTEXT_LEA, &type)
15347 && type == SYMBOL_GOTOFF_PAGE)
15348 return !mips_lo_sum_offset_lookup (htab, XVECEXP (x, 0, 1), NO_INSERT);
15353 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
15354 INSN and a previous instruction, avoid it by inserting nops after
15357 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
15358 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
15359 before using the value of that register. *HILO_DELAY counts the
15360 number of instructions since the last hilo hazard (that is,
15361 the number of instructions since the last MFLO or MFHI).
15363 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
15364 for the next instruction.
15366 LO_REG is an rtx for the LO register, used in dependence checking. */
15369 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
15370 rtx *delayed_reg, rtx lo_reg)
15375 pattern = PATTERN (insn);
15377 /* Do not put the whole function in .set noreorder if it contains
15378 an asm statement. We don't know whether there will be hazards
15379 between the asm statement and the gcc-generated code. */
15380 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
15381 cfun->machine->all_noreorder_p = false;
15383 /* Ignore zero-length instructions (barriers and the like). */
15384 ninsns = get_attr_length (insn) / 4;
15388 /* Work out how many nops are needed. Note that we only care about
15389 registers that are explicitly mentioned in the instruction's pattern.
15390 It doesn't matter that calls use the argument registers or that they
15391 clobber hi and lo. */
15392 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
15393 nops = 2 - *hilo_delay;
15394 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
15399 /* Insert the nops between this instruction and the previous one.
15400 Each new nop takes us further from the last hilo hazard. */
15401 *hilo_delay += nops;
15403 emit_insn_after (gen_hazard_nop (), after);
15405 /* Set up the state for the next instruction. */
15406 *hilo_delay += ninsns;
15408 if (INSN_CODE (insn) >= 0)
15409 switch (get_attr_hazard (insn))
15419 set = single_set (insn);
15421 *delayed_reg = SET_DEST (set);
15426 /* Go through the instruction stream and insert nops where necessary.
15427 Also delete any high-part relocations whose partnering low parts
15428 are now all dead. See if the whole function can then be put into
15429 .set noreorder and .set nomacro. */
15432 mips_reorg_process_insns (void)
15434 rtx insn, last_insn, subinsn, next_insn, lo_reg, delayed_reg;
15438 /* Force all instructions to be split into their final form. */
15439 split_all_insns_noflow ();
15441 /* Recalculate instruction lengths without taking nops into account. */
15442 cfun->machine->ignore_hazard_length_p = true;
15443 shorten_branches (get_insns ());
15445 cfun->machine->all_noreorder_p = true;
15447 /* We don't track MIPS16 PC-relative offsets closely enough to make
15448 a good job of "set .noreorder" code in MIPS16 mode. */
15450 cfun->machine->all_noreorder_p = false;
15452 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
15453 if (!TARGET_EXPLICIT_RELOCS)
15454 cfun->machine->all_noreorder_p = false;
15456 /* Profiled functions can't be all noreorder because the profiler
15457 support uses assembler macros. */
15459 cfun->machine->all_noreorder_p = false;
15461 /* Code compiled with -mfix-vr4120 or -mfix-24k can't be all noreorder
15462 because we rely on the assembler to work around some errata. */
15463 if (TARGET_FIX_VR4120 || TARGET_FIX_24K)
15464 cfun->machine->all_noreorder_p = false;
15466 /* The same is true for -mfix-vr4130 if we might generate MFLO or
15467 MFHI instructions. Note that we avoid using MFLO and MFHI if
15468 the VR4130 MACC and DMACC instructions are available instead;
15469 see the *mfhilo_{si,di}_macc patterns. */
15470 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
15471 cfun->machine->all_noreorder_p = false;
15473 htab = htab_create (37, mips_lo_sum_offset_hash,
15474 mips_lo_sum_offset_eq, free);
15476 /* Make a first pass over the instructions, recording all the LO_SUMs. */
15477 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
15478 FOR_EACH_SUBINSN (subinsn, insn)
15479 if (USEFUL_INSN_P (subinsn))
15480 for_each_rtx (&PATTERN (subinsn), mips_record_lo_sum, htab);
15485 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
15487 /* Make a second pass over the instructions. Delete orphaned
15488 high-part relocations or turn them into NOPs. Avoid hazards
15489 by inserting NOPs. */
15490 for (insn = get_insns (); insn != 0; insn = next_insn)
15492 next_insn = NEXT_INSN (insn);
15493 if (USEFUL_INSN_P (insn))
15495 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
15497 /* If we find an orphaned high-part relocation in a delay
15498 slot, it's easier to turn that instruction into a NOP than
15499 to delete it. The delay slot will be a NOP either way. */
15500 FOR_EACH_SUBINSN (subinsn, insn)
15501 if (INSN_P (subinsn))
15503 if (mips_orphaned_high_part_p (htab, subinsn))
15505 PATTERN (subinsn) = gen_nop ();
15506 INSN_CODE (subinsn) = CODE_FOR_nop;
15508 mips_avoid_hazard (last_insn, subinsn, &hilo_delay,
15509 &delayed_reg, lo_reg);
15515 /* INSN is a single instruction. Delete it if it's an
15516 orphaned high-part relocation. */
15517 if (mips_orphaned_high_part_p (htab, insn))
15518 delete_insn (insn);
15519 /* Also delete cache barriers if the last instruction
15520 was an annulled branch. INSN will not be speculatively
15522 else if (recog_memoized (insn) == CODE_FOR_r10k_cache_barrier
15524 && JUMP_P (SEQ_BEGIN (last_insn))
15525 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn)))
15526 delete_insn (insn);
15529 mips_avoid_hazard (last_insn, insn, &hilo_delay,
15530 &delayed_reg, lo_reg);
15537 htab_delete (htab);
15540 /* Return true if the function has a long branch instruction. */
15543 mips_has_long_branch_p (void)
15548 /* We need up-to-date instruction lengths. */
15549 shorten_branches (get_insns ());
15551 /* Look for a branch that is longer than normal. The normal length for
15552 non-MIPS16 branches is 8, because the length includes the delay slot.
15553 It is 4 for MIPS16, because MIPS16 branches are extended instructions,
15554 but they have no delay slot. */
15555 normal_length = (TARGET_MIPS16 ? 4 : 8);
15556 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
15557 FOR_EACH_SUBINSN (subinsn, insn)
15558 if (JUMP_P (subinsn)
15559 && USEFUL_INSN_P (subinsn)
15560 && get_attr_length (subinsn) > normal_length
15561 && (any_condjump_p (subinsn) || any_uncondjump_p (subinsn)))
15567 /* If we are using a GOT, but have not decided to use a global pointer yet,
15568 see whether we need one to implement long branches. Convert the ghost
15569 global-pointer instructions into real ones if so. */
15572 mips_expand_ghost_gp_insns (void)
15574 /* Quick exit if we already know that we will or won't need a
15576 if (!TARGET_USE_GOT
15577 || cfun->machine->global_pointer == INVALID_REGNUM
15578 || mips_must_initialize_gp_p ())
15581 /* Run a full check for long branches. */
15582 if (!mips_has_long_branch_p ())
15585 /* We've now established that we need $gp. */
15586 cfun->machine->must_initialize_gp_p = true;
15587 split_all_insns_noflow ();
15592 /* Subroutine of mips_reorg to manage passes that require DF. */
15595 mips_df_reorg (void)
15597 /* Create def-use chains. */
15598 df_set_flags (DF_EQ_NOTES);
15599 df_chain_add_problem (DF_UD_CHAIN);
15602 if (TARGET_RELAX_PIC_CALLS)
15603 mips_annotate_pic_calls ();
15605 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE)
15606 r10k_insert_cache_barriers ();
15608 df_finish_pass (false);
15611 /* Emit code to load LABEL_REF SRC into MIPS16 register DEST. This is
15612 called very late in mips_reorg, but the caller is required to run
15613 mips16_lay_out_constants on the result. */
15616 mips16_load_branch_target (rtx dest, rtx src)
15618 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
15622 if (mips_cfun_has_cprestore_slot_p ())
15623 mips_emit_move (dest, mips_cprestore_slot (dest, true));
15625 mips_emit_move (dest, pic_offset_table_rtx);
15626 page = mips_unspec_address (src, SYMBOL_GOTOFF_PAGE);
15627 low = mips_unspec_address (src, SYMBOL_GOT_PAGE_OFST);
15628 emit_insn (gen_rtx_SET (VOIDmode, dest,
15629 PMODE_INSN (gen_unspec_got, (dest, page))));
15630 emit_insn (gen_rtx_SET (VOIDmode, dest,
15631 gen_rtx_LO_SUM (Pmode, dest, low)));
15635 src = mips_unspec_address (src, SYMBOL_ABSOLUTE);
15636 mips_emit_move (dest, src);
15640 /* If we're compiling a MIPS16 function, look for and split any long branches.
15641 This must be called after all other instruction modifications in
15645 mips16_split_long_branches (void)
15647 bool something_changed;
15649 if (!TARGET_MIPS16)
15652 /* Loop until the alignments for all targets are sufficient. */
15657 shorten_branches (get_insns ());
15658 something_changed = false;
15659 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
15661 && USEFUL_INSN_P (insn)
15662 && get_attr_length (insn) > 8
15663 && (any_condjump_p (insn) || any_uncondjump_p (insn)))
15665 rtx old_label, new_label, temp, saved_temp;
15666 rtx target, jump, jump_sequence;
15670 /* Free up a MIPS16 register by saving it in $1. */
15671 saved_temp = gen_rtx_REG (Pmode, AT_REGNUM);
15672 temp = gen_rtx_REG (Pmode, GP_REG_FIRST + 2);
15673 emit_move_insn (saved_temp, temp);
15675 /* Load the branch target into TEMP. */
15676 old_label = JUMP_LABEL (insn);
15677 target = gen_rtx_LABEL_REF (Pmode, old_label);
15678 mips16_load_branch_target (temp, target);
15680 /* Jump to the target and restore the register's
15682 jump = emit_jump_insn (PMODE_INSN (gen_indirect_jump_and_restore,
15683 (temp, temp, saved_temp)));
15684 JUMP_LABEL (jump) = old_label;
15685 LABEL_NUSES (old_label)++;
15687 /* Rewrite any symbolic references that are supposed to use
15688 a PC-relative constant pool. */
15689 mips16_lay_out_constants (false);
15691 if (simplejump_p (insn))
15692 /* We're going to replace INSN with a longer form. */
15693 new_label = NULL_RTX;
15696 /* Create a branch-around label for the original
15698 new_label = gen_label_rtx ();
15699 emit_label (new_label);
15702 jump_sequence = get_insns ();
15705 emit_insn_after (jump_sequence, insn);
15707 invert_jump (insn, new_label, false);
15709 delete_insn (insn);
15710 something_changed = true;
15713 while (something_changed);
15716 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
15721 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during
15722 insn splitting in mips16_lay_out_constants, DF insn info is only kept up
15723 to date if the CFG is available. */
15724 if (mips_cfg_in_reorg ())
15725 compute_bb_for_insn ();
15726 mips16_lay_out_constants (true);
15727 if (mips_cfg_in_reorg ())
15730 free_bb_for_insn ();
15733 if (optimize > 0 && flag_delayed_branch)
15735 cleanup_barriers ();
15736 dbr_schedule (get_insns ());
15738 mips_reorg_process_insns ();
15740 && TARGET_EXPLICIT_RELOCS
15742 && TARGET_VR4130_ALIGN)
15743 vr4130_align_insns ();
15744 if (mips_expand_ghost_gp_insns ())
15745 /* The expansion could invalidate some of the VR4130 alignment
15746 optimizations, but this should be an extremely rare case anyhow. */
15747 mips_reorg_process_insns ();
15748 mips16_split_long_branches ();
15751 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
15752 in order to avoid duplicating too much logic from elsewhere. */
15755 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
15756 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
15759 rtx this_rtx, temp1, temp2, insn, fnaddr;
15760 bool use_sibcall_p;
15762 /* Pretend to be a post-reload pass while generating rtl. */
15763 reload_completed = 1;
15765 /* Mark the end of the (empty) prologue. */
15766 emit_note (NOTE_INSN_PROLOGUE_END);
15768 /* Determine if we can use a sibcall to call FUNCTION directly. */
15769 fnaddr = XEXP (DECL_RTL (function), 0);
15770 use_sibcall_p = (mips_function_ok_for_sibcall (function, NULL)
15771 && const_call_insn_operand (fnaddr, Pmode));
15773 /* Determine if we need to load FNADDR from the GOT. */
15775 && (mips_got_symbol_type_p
15776 (mips_classify_symbol (fnaddr, SYMBOL_CONTEXT_LEA))))
15778 /* Pick a global pointer. Use a call-clobbered register if
15779 TARGET_CALL_SAVED_GP. */
15780 cfun->machine->global_pointer
15781 = TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM;
15782 cfun->machine->must_initialize_gp_p = true;
15783 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
15785 /* Set up the global pointer for n32 or n64 abicalls. */
15786 mips_emit_loadgp ();
15789 /* We need two temporary registers in some cases. */
15790 temp1 = gen_rtx_REG (Pmode, 2);
15791 temp2 = gen_rtx_REG (Pmode, 3);
15793 /* Find out which register contains the "this" pointer. */
15794 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
15795 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
15797 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST);
15799 /* Add DELTA to THIS_RTX. */
15802 rtx offset = GEN_INT (delta);
15803 if (!SMALL_OPERAND (delta))
15805 mips_emit_move (temp1, offset);
15808 emit_insn (gen_add3_insn (this_rtx, this_rtx, offset));
15811 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
15812 if (vcall_offset != 0)
15816 /* Set TEMP1 to *THIS_RTX. */
15817 mips_emit_move (temp1, gen_rtx_MEM (Pmode, this_rtx));
15819 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
15820 addr = mips_add_offset (temp2, temp1, vcall_offset);
15822 /* Load the offset and add it to THIS_RTX. */
15823 mips_emit_move (temp1, gen_rtx_MEM (Pmode, addr));
15824 emit_insn (gen_add3_insn (this_rtx, this_rtx, temp1));
15827 /* Jump to the target function. Use a sibcall if direct jumps are
15828 allowed, otherwise load the address into a register first. */
15831 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
15832 SIBLING_CALL_P (insn) = 1;
15836 /* This is messy. GAS treats "la $25,foo" as part of a call
15837 sequence and may allow a global "foo" to be lazily bound.
15838 The general move patterns therefore reject this combination.
15840 In this context, lazy binding would actually be OK
15841 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
15842 TARGET_CALL_SAVED_GP; see mips_load_call_address.
15843 We must therefore load the address via a temporary
15844 register if mips_dangerous_for_la25_p.
15846 If we jump to the temporary register rather than $25,
15847 the assembler can use the move insn to fill the jump's
15850 We can use the same technique for MIPS16 code, where $25
15851 is not a valid JR register. */
15852 if (TARGET_USE_PIC_FN_ADDR_REG
15854 && !mips_dangerous_for_la25_p (fnaddr))
15855 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
15856 mips_load_call_address (MIPS_CALL_SIBCALL, temp1, fnaddr);
15858 if (TARGET_USE_PIC_FN_ADDR_REG
15859 && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
15860 mips_emit_move (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
15861 emit_jump_insn (gen_indirect_jump (temp1));
15864 /* Run just enough of rest_of_compilation. This sequence was
15865 "borrowed" from alpha.c. */
15866 insn = get_insns ();
15867 split_all_insns_noflow ();
15868 mips16_lay_out_constants (true);
15869 shorten_branches (insn);
15870 final_start_function (insn, file, 1);
15871 final (insn, file, 1);
15872 final_end_function ();
15874 /* Clean up the vars set above. Note that final_end_function resets
15875 the global pointer for us. */
15876 reload_completed = 0;
15879 /* The last argument passed to mips_set_mips16_mode, or negative if the
15880 function hasn't been called yet. */
15881 static int was_mips16_p = -1;
15883 /* Set up the target-dependent global state so that it matches the
15884 current function's ISA mode. */
15887 mips_set_mips16_mode (int mips16_p)
15889 if (mips16_p == was_mips16_p)
15892 /* Restore base settings of various flags. */
15893 target_flags = mips_base_target_flags;
15894 flag_schedule_insns = mips_base_schedule_insns;
15895 flag_reorder_blocks_and_partition = mips_base_reorder_blocks_and_partition;
15896 flag_move_loop_invariants = mips_base_move_loop_invariants;
15897 align_loops = mips_base_align_loops;
15898 align_jumps = mips_base_align_jumps;
15899 align_functions = mips_base_align_functions;
15903 /* Switch to MIPS16 mode. */
15904 target_flags |= MASK_MIPS16;
15906 /* Turn off SYNCI if it was on, MIPS16 doesn't support it. */
15907 target_flags &= ~MASK_SYNCI;
15909 /* Don't run the scheduler before reload, since it tends to
15910 increase register pressure. */
15911 flag_schedule_insns = 0;
15913 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
15914 the whole function to be in a single section. */
15915 flag_reorder_blocks_and_partition = 0;
15917 /* Don't move loop invariants, because it tends to increase
15918 register pressure. It also introduces an extra move in cases
15919 where the constant is the first operand in a two-operand binary
15920 instruction, or when it forms a register argument to a functon
15922 flag_move_loop_invariants = 0;
15924 target_flags |= MASK_EXPLICIT_RELOCS;
15926 /* Experiments suggest we get the best overall section-anchor
15927 results from using the range of an unextended LW or SW. Code
15928 that makes heavy use of byte or short accesses can do better
15929 with ranges of 0...31 and 0...63 respectively, but most code is
15930 sensitive to the range of LW and SW instead. */
15931 targetm.min_anchor_offset = 0;
15932 targetm.max_anchor_offset = 127;
15934 targetm.const_anchor = 0;
15936 /* MIPS16 has no BAL instruction. */
15937 target_flags &= ~MASK_RELAX_PIC_CALLS;
15939 /* The R4000 errata don't apply to any known MIPS16 cores.
15940 It's simpler to make the R4000 fixes and MIPS16 mode
15941 mutually exclusive. */
15942 target_flags &= ~MASK_FIX_R4000;
15944 if (flag_pic && !TARGET_OLDABI)
15945 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
15948 sorry ("MIPS16 -mxgot code");
15950 if (TARGET_HARD_FLOAT_ABI && !TARGET_OLDABI)
15951 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
15955 /* Switch to normal (non-MIPS16) mode. */
15956 target_flags &= ~MASK_MIPS16;
15958 /* Provide default values for align_* for 64-bit targets. */
15961 if (align_loops == 0)
15963 if (align_jumps == 0)
15965 if (align_functions == 0)
15966 align_functions = 8;
15969 targetm.min_anchor_offset = -32768;
15970 targetm.max_anchor_offset = 32767;
15972 targetm.const_anchor = 0x8000;
15975 /* (Re)initialize MIPS target internals for new ISA. */
15976 mips_init_relocs ();
15980 if (!mips16_globals)
15981 mips16_globals = save_target_globals ();
15983 restore_target_globals (mips16_globals);
15986 restore_target_globals (&default_target_globals);
15988 was_mips16_p = mips16_p;
15991 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
15992 function should use the MIPS16 ISA and switch modes accordingly. */
15995 mips_set_current_function (tree fndecl)
15997 mips_set_mips16_mode (mips_use_mips16_mode_p (fndecl));
16000 /* Allocate a chunk of memory for per-function machine-dependent data. */
16002 static struct machine_function *
16003 mips_init_machine_status (void)
16005 return ggc_alloc_cleared_machine_function ();
16008 /* Return the processor associated with the given ISA level, or null
16009 if the ISA isn't valid. */
16011 static const struct mips_cpu_info *
16012 mips_cpu_info_from_isa (int isa)
16016 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
16017 if (mips_cpu_info_table[i].isa == isa)
16018 return mips_cpu_info_table + i;
16023 /* Return a mips_cpu_info entry determined by an option valued
16026 static const struct mips_cpu_info *
16027 mips_cpu_info_from_opt (int opt)
16031 case MIPS_ARCH_OPTION_FROM_ABI:
16032 /* 'from-abi' selects the most compatible architecture for the
16033 given ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit
16034 ABIs. For the EABIs, we have to decide whether we're using
16035 the 32-bit or 64-bit version. */
16036 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
16037 : ABI_NEEDS_64BIT_REGS ? 3
16038 : (TARGET_64BIT ? 3 : 1));
16040 case MIPS_ARCH_OPTION_NATIVE:
16041 gcc_unreachable ();
16044 return &mips_cpu_info_table[opt];
16048 /* Return a default mips_cpu_info entry, given that no -march= option
16049 was explicitly specified. */
16051 static const struct mips_cpu_info *
16052 mips_default_arch (void)
16054 #if defined (MIPS_CPU_STRING_DEFAULT)
16056 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
16057 if (strcmp (mips_cpu_info_table[i].name, MIPS_CPU_STRING_DEFAULT) == 0)
16058 return mips_cpu_info_table + i;
16059 gcc_unreachable ();
16060 #elif defined (MIPS_ISA_DEFAULT)
16061 return mips_cpu_info_from_isa (MIPS_ISA_DEFAULT);
16063 /* 'from-abi' makes a good default: you get whatever the ABI
16065 return mips_cpu_info_from_opt (MIPS_ARCH_OPTION_FROM_ABI);
16069 /* Set up globals to generate code for the ISA or processor
16070 described by INFO. */
16073 mips_set_architecture (const struct mips_cpu_info *info)
16077 mips_arch_info = info;
16078 mips_arch = info->cpu;
16079 mips_isa = info->isa;
16083 /* Likewise for tuning. */
16086 mips_set_tune (const struct mips_cpu_info *info)
16090 mips_tune_info = info;
16091 mips_tune = info->cpu;
16095 /* Implement TARGET_OPTION_OVERRIDE. */
16098 mips_option_override (void)
16100 int i, start, regno, mode;
16102 if (global_options_set.x_mips_isa_option)
16103 mips_isa_option_info = &mips_cpu_info_table[mips_isa_option];
16105 /* Process flags as though we were generating non-MIPS16 code. */
16106 mips_base_mips16 = TARGET_MIPS16;
16107 target_flags &= ~MASK_MIPS16;
16109 #ifdef SUBTARGET_OVERRIDE_OPTIONS
16110 SUBTARGET_OVERRIDE_OPTIONS;
16113 /* -mno-float overrides -mhard-float and -msoft-float. */
16114 if (TARGET_NO_FLOAT)
16116 target_flags |= MASK_SOFT_FLOAT_ABI;
16117 target_flags_explicit |= MASK_SOFT_FLOAT_ABI;
16120 if (TARGET_FLIP_MIPS16)
16121 TARGET_INTERLINK_MIPS16 = 1;
16123 /* Set the small data limit. */
16124 mips_small_data_threshold = (global_options_set.x_g_switch_value
16126 : MIPS_DEFAULT_GVALUE);
16128 /* The following code determines the architecture and register size.
16129 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
16130 The GAS and GCC code should be kept in sync as much as possible. */
16132 if (global_options_set.x_mips_arch_option)
16133 mips_set_architecture (mips_cpu_info_from_opt (mips_arch_option));
16135 if (mips_isa_option_info != 0)
16137 if (mips_arch_info == 0)
16138 mips_set_architecture (mips_isa_option_info);
16139 else if (mips_arch_info->isa != mips_isa_option_info->isa)
16140 error ("%<-%s%> conflicts with the other architecture options, "
16141 "which specify a %s processor",
16142 mips_isa_option_info->name,
16143 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
16146 if (mips_arch_info == 0)
16147 mips_set_architecture (mips_default_arch ());
16149 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
16150 error ("%<-march=%s%> is not compatible with the selected ABI",
16151 mips_arch_info->name);
16153 /* Optimize for mips_arch, unless -mtune selects a different processor. */
16154 if (global_options_set.x_mips_tune_option)
16155 mips_set_tune (mips_cpu_info_from_opt (mips_tune_option));
16157 if (mips_tune_info == 0)
16158 mips_set_tune (mips_arch_info);
16160 if ((target_flags_explicit & MASK_64BIT) != 0)
16162 /* The user specified the size of the integer registers. Make sure
16163 it agrees with the ABI and ISA. */
16164 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
16165 error ("%<-mgp64%> used with a 32-bit processor");
16166 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
16167 error ("%<-mgp32%> used with a 64-bit ABI");
16168 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
16169 error ("%<-mgp64%> used with a 32-bit ABI");
16173 /* Infer the integer register size from the ABI and processor.
16174 Restrict ourselves to 32-bit registers if that's all the
16175 processor has, or if the ABI cannot handle 64-bit registers. */
16176 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
16177 target_flags &= ~MASK_64BIT;
16179 target_flags |= MASK_64BIT;
16182 if ((target_flags_explicit & MASK_FLOAT64) != 0)
16184 if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
16185 error ("unsupported combination: %s", "-mfp64 -msingle-float");
16186 else if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
16187 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
16188 else if (!TARGET_64BIT && TARGET_FLOAT64)
16190 if (!ISA_HAS_MXHC1)
16191 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
16192 " the target supports the mfhc1 and mthc1 instructions");
16193 else if (mips_abi != ABI_32)
16194 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
16200 /* -msingle-float selects 32-bit float registers. Otherwise the
16201 float registers should be the same size as the integer ones. */
16202 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
16203 target_flags |= MASK_FLOAT64;
16205 target_flags &= ~MASK_FLOAT64;
16208 /* End of code shared with GAS. */
16210 /* If a -mlong* option was given, check that it matches the ABI,
16211 otherwise infer the -mlong* setting from the other options. */
16212 if ((target_flags_explicit & MASK_LONG64) != 0)
16216 if (mips_abi == ABI_N32)
16217 error ("%qs is incompatible with %qs", "-mabi=n32", "-mlong64");
16218 else if (mips_abi == ABI_32)
16219 error ("%qs is incompatible with %qs", "-mabi=32", "-mlong64");
16220 else if (mips_abi == ABI_O64 && TARGET_ABICALLS)
16221 /* We have traditionally allowed non-abicalls code to use
16222 an LP64 form of o64. However, it would take a bit more
16223 effort to support the combination of 32-bit GOT entries
16224 and 64-bit pointers, so we treat the abicalls case as
16226 error ("the combination of %qs and %qs is incompatible with %qs",
16227 "-mabi=o64", "-mabicalls", "-mlong64");
16231 if (mips_abi == ABI_64)
16232 error ("%qs is incompatible with %qs", "-mabi=64", "-mlong32");
16237 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
16238 target_flags |= MASK_LONG64;
16240 target_flags &= ~MASK_LONG64;
16243 if (!TARGET_OLDABI)
16244 flag_pcc_struct_return = 0;
16246 /* Decide which rtx_costs structure to use. */
16248 mips_cost = &mips_rtx_cost_optimize_size;
16250 mips_cost = &mips_rtx_cost_data[mips_tune];
16252 /* If the user hasn't specified a branch cost, use the processor's
16254 if (mips_branch_cost == 0)
16255 mips_branch_cost = mips_cost->branch_cost;
16257 /* If neither -mbranch-likely nor -mno-branch-likely was given
16258 on the command line, set MASK_BRANCHLIKELY based on the target
16259 architecture and tuning flags. Annulled delay slots are a
16260 size win, so we only consider the processor-specific tuning
16261 for !optimize_size. */
16262 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
16264 if (ISA_HAS_BRANCHLIKELY
16266 || (mips_tune_info->tune_flags & PTF_AVOID_BRANCHLIKELY) == 0))
16267 target_flags |= MASK_BRANCHLIKELY;
16269 target_flags &= ~MASK_BRANCHLIKELY;
16271 else if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
16272 warning (0, "the %qs architecture does not support branch-likely"
16273 " instructions", mips_arch_info->name);
16275 /* The effect of -mabicalls isn't defined for the EABI. */
16276 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
16278 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
16279 target_flags &= ~MASK_ABICALLS;
16282 /* PIC requires -mabicalls. */
16285 if (mips_abi == ABI_EABI)
16286 error ("cannot generate position-independent code for %qs",
16288 else if (!TARGET_ABICALLS)
16289 error ("position-independent code requires %qs", "-mabicalls");
16292 if (TARGET_ABICALLS_PIC2)
16293 /* We need to set flag_pic for executables as well as DSOs
16294 because we may reference symbols that are not defined in
16295 the final executable. (MIPS does not use things like
16296 copy relocs, for example.)
16298 There is a body of code that uses __PIC__ to distinguish
16299 between -mabicalls and -mno-abicalls code. The non-__PIC__
16300 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
16301 long as any indirect jumps use $25. */
16304 /* -mvr4130-align is a "speed over size" optimization: it usually produces
16305 faster code, but at the expense of more nops. Enable it at -O3 and
16307 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
16308 target_flags |= MASK_VR4130_ALIGN;
16310 /* Prefer a call to memcpy over inline code when optimizing for size,
16311 though see MOVE_RATIO in mips.h. */
16312 if (optimize_size && (target_flags_explicit & MASK_MEMCPY) == 0)
16313 target_flags |= MASK_MEMCPY;
16315 /* If we have a nonzero small-data limit, check that the -mgpopt
16316 setting is consistent with the other target flags. */
16317 if (mips_small_data_threshold > 0)
16321 if (!TARGET_EXPLICIT_RELOCS)
16322 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
16324 TARGET_LOCAL_SDATA = false;
16325 TARGET_EXTERN_SDATA = false;
16329 if (TARGET_VXWORKS_RTP)
16330 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
16332 if (TARGET_ABICALLS)
16333 warning (0, "cannot use small-data accesses for %qs",
16338 /* Make sure that the user didn't turn off paired single support when
16339 MIPS-3D support is requested. */
16341 && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
16342 && !TARGET_PAIRED_SINGLE_FLOAT)
16343 error ("%<-mips3d%> requires %<-mpaired-single%>");
16345 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
16347 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
16349 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
16350 and TARGET_HARD_FLOAT_ABI are both true. */
16351 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT_ABI))
16352 error ("%qs must be used with %qs",
16353 TARGET_MIPS3D ? "-mips3d" : "-mpaired-single",
16354 TARGET_HARD_FLOAT_ABI ? "-mfp64" : "-mhard-float");
16356 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
16358 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_HAS_PAIRED_SINGLE)
16359 warning (0, "the %qs architecture does not support paired-single"
16360 " instructions", mips_arch_info->name);
16362 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
16363 && !TARGET_CACHE_BUILTIN)
16365 error ("%qs requires a target that provides the %qs instruction",
16366 "-mr10k-cache-barrier", "cache");
16367 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE;
16370 /* If TARGET_DSPR2, enable MASK_DSP. */
16372 target_flags |= MASK_DSP;
16374 /* .eh_frame addresses should be the same width as a C pointer.
16375 Most MIPS ABIs support only one pointer size, so the assembler
16376 will usually know exactly how big an .eh_frame address is.
16378 Unfortunately, this is not true of the 64-bit EABI. The ABI was
16379 originally defined to use 64-bit pointers (i.e. it is LP64), and
16380 this is still the default mode. However, we also support an n32-like
16381 ILP32 mode, which is selected by -mlong32. The problem is that the
16382 assembler has traditionally not had an -mlong option, so it has
16383 traditionally not known whether we're using the ILP32 or LP64 form.
16385 As it happens, gas versions up to and including 2.19 use _32-bit_
16386 addresses for EABI64 .cfi_* directives. This is wrong for the
16387 default LP64 mode, so we can't use the directives by default.
16388 Moreover, since gas's current behavior is at odds with gcc's
16389 default behavior, it seems unwise to rely on future versions
16390 of gas behaving the same way. We therefore avoid using .cfi
16391 directives for -mlong32 as well. */
16392 if (mips_abi == ABI_EABI && TARGET_64BIT)
16393 flag_dwarf2_cfi_asm = 0;
16395 /* .cfi_* directives generate a read-only section, so fall back on
16396 manual .eh_frame creation if we need the section to be writable. */
16397 if (TARGET_WRITABLE_EH_FRAME)
16398 flag_dwarf2_cfi_asm = 0;
16400 mips_init_print_operand_punct ();
16402 /* Set up array to map GCC register number to debug register number.
16403 Ignore the special purpose register numbers. */
16405 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
16407 mips_dbx_regno[i] = INVALID_REGNUM;
16408 if (GP_REG_P (i) || FP_REG_P (i) || ALL_COP_REG_P (i))
16409 mips_dwarf_regno[i] = i;
16411 mips_dwarf_regno[i] = INVALID_REGNUM;
16414 start = GP_DBX_FIRST - GP_REG_FIRST;
16415 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
16416 mips_dbx_regno[i] = i + start;
16418 start = FP_DBX_FIRST - FP_REG_FIRST;
16419 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
16420 mips_dbx_regno[i] = i + start;
16422 /* Accumulator debug registers use big-endian ordering. */
16423 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
16424 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
16425 mips_dwarf_regno[HI_REGNUM] = MD_REG_FIRST + 0;
16426 mips_dwarf_regno[LO_REGNUM] = MD_REG_FIRST + 1;
16427 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
16429 mips_dwarf_regno[i + TARGET_LITTLE_ENDIAN] = i;
16430 mips_dwarf_regno[i + TARGET_BIG_ENDIAN] = i + 1;
16433 /* Set up mips_hard_regno_mode_ok. */
16434 for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
16435 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
16436 mips_hard_regno_mode_ok[mode][regno]
16437 = mips_hard_regno_mode_ok_p (regno, (enum machine_mode) mode);
16439 /* Function to allocate machine-dependent function status. */
16440 init_machine_status = &mips_init_machine_status;
16442 /* Default to working around R4000 errata only if the processor
16443 was selected explicitly. */
16444 if ((target_flags_explicit & MASK_FIX_R4000) == 0
16445 && strcmp (mips_arch_info->name, "r4000") == 0)
16446 target_flags |= MASK_FIX_R4000;
16448 /* Default to working around R4400 errata only if the processor
16449 was selected explicitly. */
16450 if ((target_flags_explicit & MASK_FIX_R4400) == 0
16451 && strcmp (mips_arch_info->name, "r4400") == 0)
16452 target_flags |= MASK_FIX_R4400;
16454 /* Default to working around R10000 errata only if the processor
16455 was selected explicitly. */
16456 if ((target_flags_explicit & MASK_FIX_R10000) == 0
16457 && strcmp (mips_arch_info->name, "r10000") == 0)
16458 target_flags |= MASK_FIX_R10000;
16460 /* Make sure that branch-likely instructions available when using
16461 -mfix-r10000. The instructions are not available if either:
16463 1. -mno-branch-likely was passed.
16464 2. The selected ISA does not support branch-likely and
16465 the command line does not include -mbranch-likely. */
16466 if (TARGET_FIX_R10000
16467 && ((target_flags_explicit & MASK_BRANCHLIKELY) == 0
16468 ? !ISA_HAS_BRANCHLIKELY
16469 : !TARGET_BRANCHLIKELY))
16470 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
16472 if (TARGET_SYNCI && !ISA_HAS_SYNCI)
16474 warning (0, "the %qs architecture does not support the synci "
16475 "instruction", mips_arch_info->name);
16476 target_flags &= ~MASK_SYNCI;
16479 /* Only optimize PIC indirect calls if they are actually required. */
16480 if (!TARGET_USE_GOT || !TARGET_EXPLICIT_RELOCS)
16481 target_flags &= ~MASK_RELAX_PIC_CALLS;
16483 /* Save base state of options. */
16484 mips_base_target_flags = target_flags;
16485 mips_base_schedule_insns = flag_schedule_insns;
16486 mips_base_reorder_blocks_and_partition = flag_reorder_blocks_and_partition;
16487 mips_base_move_loop_invariants = flag_move_loop_invariants;
16488 mips_base_align_loops = align_loops;
16489 mips_base_align_jumps = align_jumps;
16490 mips_base_align_functions = align_functions;
16492 /* Now select the ISA mode.
16494 Do all CPP-sensitive stuff in non-MIPS16 mode; we'll switch to
16495 MIPS16 mode afterwards if need be. */
16496 mips_set_mips16_mode (false);
16499 /* Swap the register information for registers I and I + 1, which
16500 currently have the wrong endianness. Note that the registers'
16501 fixedness and call-clobberedness might have been set on the
16505 mips_swap_registers (unsigned int i)
16510 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
16511 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
16513 SWAP_INT (fixed_regs[i], fixed_regs[i + 1]);
16514 SWAP_INT (call_used_regs[i], call_used_regs[i + 1]);
16515 SWAP_INT (call_really_used_regs[i], call_really_used_regs[i + 1]);
16516 SWAP_STRING (reg_names[i], reg_names[i + 1]);
16522 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
16525 mips_conditional_register_usage (void)
16530 /* These DSP control register fields are global. */
16531 global_regs[CCDSP_PO_REGNUM] = 1;
16532 global_regs[CCDSP_SC_REGNUM] = 1;
16535 AND_COMPL_HARD_REG_SET (accessible_reg_set,
16536 reg_class_contents[(int) DSP_ACC_REGS]);
16538 if (!TARGET_HARD_FLOAT)
16540 AND_COMPL_HARD_REG_SET (accessible_reg_set,
16541 reg_class_contents[(int) FP_REGS]);
16542 AND_COMPL_HARD_REG_SET (accessible_reg_set,
16543 reg_class_contents[(int) ST_REGS]);
16545 else if (!ISA_HAS_8CC)
16547 /* We only have a single condition-code register. We implement
16548 this by fixing all the condition-code registers and generating
16549 RTL that refers directly to ST_REG_FIRST. */
16550 AND_COMPL_HARD_REG_SET (accessible_reg_set,
16551 reg_class_contents[(int) ST_REGS]);
16552 SET_HARD_REG_BIT (accessible_reg_set, FPSW_REGNUM);
16553 fixed_regs[FPSW_REGNUM] = call_used_regs[FPSW_REGNUM] = 1;
16557 /* In MIPS16 mode, we permit the $t temporary registers to be used
16558 for reload. We prohibit the unused $s registers, since they
16559 are call-saved, and saving them via a MIPS16 register would
16560 probably waste more time than just reloading the value. */
16561 fixed_regs[18] = call_used_regs[18] = 1;
16562 fixed_regs[19] = call_used_regs[19] = 1;
16563 fixed_regs[20] = call_used_regs[20] = 1;
16564 fixed_regs[21] = call_used_regs[21] = 1;
16565 fixed_regs[22] = call_used_regs[22] = 1;
16566 fixed_regs[23] = call_used_regs[23] = 1;
16567 fixed_regs[26] = call_used_regs[26] = 1;
16568 fixed_regs[27] = call_used_regs[27] = 1;
16569 fixed_regs[30] = call_used_regs[30] = 1;
16571 /* Do not allow HI and LO to be treated as register operands.
16572 There are no MTHI or MTLO instructions (or any real need
16573 for them) and one-way registers cannot easily be reloaded. */
16574 AND_COMPL_HARD_REG_SET (operand_reg_set,
16575 reg_class_contents[(int) MD_REGS]);
16577 /* $f20-$f23 are call-clobbered for n64. */
16578 if (mips_abi == ABI_64)
16581 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
16582 call_really_used_regs[regno] = call_used_regs[regno] = 1;
16584 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
16586 if (mips_abi == ABI_N32)
16589 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
16590 call_really_used_regs[regno] = call_used_regs[regno] = 1;
16592 /* Make sure that double-register accumulator values are correctly
16593 ordered for the current endianness. */
16594 if (TARGET_LITTLE_ENDIAN)
16596 unsigned int regno;
16598 mips_swap_registers (MD_REG_FIRST);
16599 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno += 2)
16600 mips_swap_registers (regno);
16604 /* When generating MIPS16 code, we want to allocate $24 (T_REG) before
16605 other registers for instructions for which it is possible. This
16606 encourages the compiler to use CMP in cases where an XOR would
16607 require some register shuffling. */
16610 mips_order_regs_for_local_alloc (void)
16614 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
16615 reg_alloc_order[i] = i;
16619 /* It really doesn't matter where we put register 0, since it is
16620 a fixed register anyhow. */
16621 reg_alloc_order[0] = 24;
16622 reg_alloc_order[24] = 0;
16626 /* Implement EH_USES. */
16629 mips_eh_uses (unsigned int regno)
16631 if (reload_completed && !TARGET_ABSOLUTE_JUMPS)
16633 /* We need to force certain registers to be live in order to handle
16634 PIC long branches correctly. See mips_must_initialize_gp_p for
16636 if (mips_cfun_has_cprestore_slot_p ())
16638 if (regno == CPRESTORE_SLOT_REGNUM)
16643 if (cfun->machine->global_pointer == regno)
16651 /* Implement EPILOGUE_USES. */
16654 mips_epilogue_uses (unsigned int regno)
16656 /* Say that the epilogue uses the return address register. Note that
16657 in the case of sibcalls, the values "used by the epilogue" are
16658 considered live at the start of the called function. */
16659 if (regno == RETURN_ADDR_REGNUM)
16662 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
16663 See the comment above load_call<mode> for details. */
16664 if (TARGET_USE_GOT && (regno) == GOT_VERSION_REGNUM)
16667 /* An interrupt handler must preserve some registers that are
16668 ordinarily call-clobbered. */
16669 if (cfun->machine->interrupt_handler_p
16670 && mips_interrupt_extra_call_saved_reg_p (regno))
16676 /* A for_each_rtx callback. Stop the search if *X is an AT register. */
16679 mips_at_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
16681 return REG_P (*x) && REGNO (*x) == AT_REGNUM;
16684 /* Return true if INSN needs to be wrapped in ".set noat".
16685 INSN has NOPERANDS operands, stored in OPVEC. */
16688 mips_need_noat_wrapper_p (rtx insn, rtx *opvec, int noperands)
16692 if (recog_memoized (insn) >= 0)
16693 for (i = 0; i < noperands; i++)
16694 if (for_each_rtx (&opvec[i], mips_at_reg_p, NULL))
16699 /* Implement FINAL_PRESCAN_INSN. */
16702 mips_final_prescan_insn (rtx insn, rtx *opvec, int noperands)
16704 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
16705 mips_push_asm_switch (&mips_noat);
16708 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */
16711 mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED, rtx insn,
16712 rtx *opvec, int noperands)
16714 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
16715 mips_pop_asm_switch (&mips_noat);
16718 /* Return the function that is used to expand the <u>mulsidi3 pattern.
16719 EXT_CODE is the code of the extension used. Return NULL if widening
16720 multiplication shouldn't be used. */
16723 mips_mulsidi3_gen_fn (enum rtx_code ext_code)
16727 signed_p = ext_code == SIGN_EXTEND;
16730 /* Don't use widening multiplication with MULT when we have DMUL. Even
16731 with the extension of its input operands DMUL is faster. Note that
16732 the extension is not needed for signed multiplication. In order to
16733 ensure that we always remove the redundant sign-extension in this
16734 case we still expand mulsidi3 for DMUL. */
16736 return signed_p ? gen_mulsidi3_64bit_dmul : NULL;
16739 ? gen_mulsidi3_64bit_mips16
16740 : gen_umulsidi3_64bit_mips16);
16741 if (TARGET_FIX_R4000)
16743 return signed_p ? gen_mulsidi3_64bit : gen_umulsidi3_64bit;
16749 ? gen_mulsidi3_32bit_mips16
16750 : gen_umulsidi3_32bit_mips16);
16751 if (TARGET_FIX_R4000 && !ISA_HAS_DSP)
16752 return signed_p ? gen_mulsidi3_32bit_r4000 : gen_umulsidi3_32bit_r4000;
16753 return signed_p ? gen_mulsidi3_32bit : gen_umulsidi3_32bit;
16757 /* Return the size in bytes of the trampoline code, padded to
16758 TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target
16759 function address immediately follow. */
16762 mips_trampoline_code_size (void)
16764 if (TARGET_USE_PIC_FN_ADDR_REG)
16766 else if (ptr_mode == DImode)
16768 else if (ISA_HAS_LOAD_DELAY)
16774 /* Implement TARGET_TRAMPOLINE_INIT. */
16777 mips_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
16779 rtx addr, end_addr, high, low, opcode, mem;
16782 HOST_WIDE_INT end_addr_offset, static_chain_offset, target_function_offset;
16784 /* Work out the offsets of the pointers from the start of the
16785 trampoline code. */
16786 end_addr_offset = mips_trampoline_code_size ();
16787 static_chain_offset = end_addr_offset;
16788 target_function_offset = static_chain_offset + GET_MODE_SIZE (ptr_mode);
16790 /* Get pointers to the beginning and end of the code block. */
16791 addr = force_reg (Pmode, XEXP (m_tramp, 0));
16792 end_addr = mips_force_binary (Pmode, PLUS, addr, GEN_INT (end_addr_offset));
16794 #define OP(X) gen_int_mode (X, SImode)
16796 /* Build up the code in TRAMPOLINE. */
16798 if (TARGET_USE_PIC_FN_ADDR_REG)
16800 /* $25 contains the address of the trampoline. Emit code of the form:
16802 l[wd] $1, target_function_offset($25)
16803 l[wd] $static_chain, static_chain_offset($25)
16806 trampoline[i++] = OP (MIPS_LOAD_PTR (AT_REGNUM,
16807 target_function_offset,
16808 PIC_FUNCTION_ADDR_REGNUM));
16809 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
16810 static_chain_offset,
16811 PIC_FUNCTION_ADDR_REGNUM));
16812 trampoline[i++] = OP (MIPS_JR (AT_REGNUM));
16813 trampoline[i++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM, AT_REGNUM));
16815 else if (ptr_mode == DImode)
16817 /* It's too cumbersome to create the full 64-bit address, so let's
16823 1: l[wd] $25, target_function_offset - 12($31)
16824 l[wd] $static_chain, static_chain_offset - 12($31)
16828 where 12 is the offset of "1:" from the start of the code block. */
16829 trampoline[i++] = OP (MIPS_MOVE (AT_REGNUM, RETURN_ADDR_REGNUM));
16830 trampoline[i++] = OP (MIPS_BAL (1));
16831 trampoline[i++] = OP (MIPS_NOP);
16832 trampoline[i++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
16833 target_function_offset - 12,
16834 RETURN_ADDR_REGNUM));
16835 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
16836 static_chain_offset - 12,
16837 RETURN_ADDR_REGNUM));
16838 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
16839 trampoline[i++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM, AT_REGNUM));
16843 /* If the target has load delays, emit:
16845 lui $1, %hi(end_addr)
16846 lw $25, %lo(end_addr + ...)($1)
16847 lw $static_chain, %lo(end_addr + ...)($1)
16853 lui $1, %hi(end_addr)
16854 lw $25, %lo(end_addr + ...)($1)
16856 lw $static_chain, %lo(end_addr + ...)($1). */
16858 /* Split END_ADDR into %hi and %lo values. Trampolines are aligned
16859 to 64 bits, so the %lo value will have the bottom 3 bits clear. */
16860 high = expand_simple_binop (SImode, PLUS, end_addr, GEN_INT (0x8000),
16861 NULL, false, OPTAB_WIDEN);
16862 high = expand_simple_binop (SImode, LSHIFTRT, high, GEN_INT (16),
16863 NULL, false, OPTAB_WIDEN);
16864 low = convert_to_mode (SImode, gen_lowpart (HImode, end_addr), true);
16866 /* Emit the LUI. */
16867 opcode = OP (MIPS_LUI (AT_REGNUM, 0));
16868 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, high,
16869 NULL, false, OPTAB_WIDEN);
16871 /* Emit the load of the target function. */
16872 opcode = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
16873 target_function_offset - end_addr_offset,
16875 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
16876 NULL, false, OPTAB_WIDEN);
16878 /* Emit the JR here, if we can. */
16879 if (!ISA_HAS_LOAD_DELAY)
16880 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
16882 /* Emit the load of the static chain register. */
16883 opcode = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
16884 static_chain_offset - end_addr_offset,
16886 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
16887 NULL, false, OPTAB_WIDEN);
16889 /* Emit the JR, if we couldn't above. */
16890 if (ISA_HAS_LOAD_DELAY)
16892 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
16893 trampoline[i++] = OP (MIPS_NOP);
16899 /* Copy the trampoline code. Leave any padding uninitialized. */
16900 for (j = 0; j < i; j++)
16902 mem = adjust_address (m_tramp, SImode, j * GET_MODE_SIZE (SImode));
16903 mips_emit_move (mem, trampoline[j]);
16906 /* Set up the static chain pointer field. */
16907 mem = adjust_address (m_tramp, ptr_mode, static_chain_offset);
16908 mips_emit_move (mem, chain_value);
16910 /* Set up the target function field. */
16911 mem = adjust_address (m_tramp, ptr_mode, target_function_offset);
16912 mips_emit_move (mem, XEXP (DECL_RTL (fndecl), 0));
16914 /* Flush the code part of the trampoline. */
16915 emit_insn (gen_add3_insn (end_addr, addr, GEN_INT (TRAMPOLINE_SIZE)));
16916 emit_insn (gen_clear_cache (addr, end_addr));
16919 /* Implement FUNCTION_PROFILER. */
16921 void mips_function_profiler (FILE *file)
16924 sorry ("mips16 function profiling");
16925 if (TARGET_LONG_CALLS)
16927 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */
16928 if (Pmode == DImode)
16929 fprintf (file, "\tdla\t%s,_mcount\n", reg_names[3]);
16931 fprintf (file, "\tla\t%s,_mcount\n", reg_names[3]);
16933 mips_push_asm_switch (&mips_noat);
16934 fprintf (file, "\tmove\t%s,%s\t\t# save current return address\n",
16935 reg_names[AT_REGNUM], reg_names[RETURN_ADDR_REGNUM]);
16936 /* _mcount treats $2 as the static chain register. */
16937 if (cfun->static_chain_decl != NULL)
16938 fprintf (file, "\tmove\t%s,%s\n", reg_names[2],
16939 reg_names[STATIC_CHAIN_REGNUM]);
16940 if (TARGET_MCOUNT_RA_ADDRESS)
16942 /* If TARGET_MCOUNT_RA_ADDRESS load $12 with the address of the
16943 ra save location. */
16944 if (cfun->machine->frame.ra_fp_offset == 0)
16945 /* ra not saved, pass zero. */
16946 fprintf (file, "\tmove\t%s,%s\n", reg_names[12], reg_names[0]);
16948 fprintf (file, "\t%s\t%s," HOST_WIDE_INT_PRINT_DEC "(%s)\n",
16949 Pmode == DImode ? "dla" : "la", reg_names[12],
16950 cfun->machine->frame.ra_fp_offset,
16951 reg_names[STACK_POINTER_REGNUM]);
16953 if (!TARGET_NEWABI)
16955 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n",
16956 TARGET_64BIT ? "dsubu" : "subu",
16957 reg_names[STACK_POINTER_REGNUM],
16958 reg_names[STACK_POINTER_REGNUM],
16959 Pmode == DImode ? 16 : 8);
16961 if (TARGET_LONG_CALLS)
16962 fprintf (file, "\tjalr\t%s\n", reg_names[3]);
16964 fprintf (file, "\tjal\t_mcount\n");
16965 mips_pop_asm_switch (&mips_noat);
16966 /* _mcount treats $2 as the static chain register. */
16967 if (cfun->static_chain_decl != NULL)
16968 fprintf (file, "\tmove\t%s,%s\n", reg_names[STATIC_CHAIN_REGNUM],
16972 /* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default
16973 behaviour of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even
16974 when TARGET_LOONGSON_VECTORS is true. */
16976 static unsigned HOST_WIDE_INT
16977 mips_shift_truncation_mask (enum machine_mode mode)
16979 if (TARGET_LOONGSON_VECTORS && VECTOR_MODE_P (mode))
16982 return GET_MODE_BITSIZE (mode) - 1;
16985 /* Implement TARGET_PREPARE_PCH_SAVE. */
16988 mips_prepare_pch_save (void)
16990 /* We are called in a context where the current MIPS16 vs. non-MIPS16
16991 setting should be irrelevant. The question then is: which setting
16992 makes most sense at load time?
16994 The PCH is loaded before the first token is read. We should never
16995 have switched into MIPS16 mode by that point, and thus should not
16996 have populated mips16_globals. Nor can we load the entire contents
16997 of mips16_globals from the PCH file, because mips16_globals contains
16998 a combination of GGC and non-GGC data.
17000 There is therefore no point in trying save the GGC part of
17001 mips16_globals to the PCH file, or to preserve MIPS16ness across
17002 the PCH save and load. The loading compiler would not have access
17003 to the non-GGC parts of mips16_globals (either from the PCH file,
17004 or from a copy that the loading compiler generated itself) and would
17005 have to call target_reinit anyway.
17007 It therefore seems best to switch back to non-MIPS16 mode at
17008 save time, and to ensure that mips16_globals remains null after
17010 mips_set_mips16_mode (false);
17011 mips16_globals = 0;
17014 /* Generate or test for an insn that supports a constant permutation. */
17016 #define MAX_VECT_LEN 8
17018 struct expand_vec_perm_d
17020 rtx target, op0, op1;
17021 unsigned char perm[MAX_VECT_LEN];
17022 enum machine_mode vmode;
17023 unsigned char nelt;
17028 /* Construct (set target (vec_select op0 (parallel perm))) and
17029 return true if that's a valid instruction in the active ISA. */
17032 mips_expand_vselect (rtx target, rtx op0,
17033 const unsigned char *perm, unsigned nelt)
17035 rtx rperm[MAX_VECT_LEN], x;
17038 for (i = 0; i < nelt; ++i)
17039 rperm[i] = GEN_INT (perm[i]);
17041 x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (nelt, rperm));
17042 x = gen_rtx_VEC_SELECT (GET_MODE (target), op0, x);
17043 x = gen_rtx_SET (VOIDmode, target, x);
17046 if (recog_memoized (x) < 0)
17054 /* Similar, but generate a vec_concat from op0 and op1 as well. */
17057 mips_expand_vselect_vconcat (rtx target, rtx op0, rtx op1,
17058 const unsigned char *perm, unsigned nelt)
17060 enum machine_mode v2mode;
17063 v2mode = GET_MODE_2XWIDER_MODE (GET_MODE (op0));
17064 x = gen_rtx_VEC_CONCAT (v2mode, op0, op1);
17065 return mips_expand_vselect (target, x, perm, nelt);
17068 /* Recognize patterns for even-odd extraction. */
17071 mips_expand_vpc_loongson_even_odd (struct expand_vec_perm_d *d)
17073 unsigned i, odd, nelt = d->nelt;
17074 rtx t0, t1, t2, t3;
17076 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
17078 /* Even-odd for V2SI/V2SFmode is matched by interleave directly. */
17085 for (i = 1; i < nelt; ++i)
17086 if (d->perm[i] != i * 2 + odd)
17092 /* We need 2*log2(N)-1 operations to achieve odd/even with interleave. */
17093 t0 = gen_reg_rtx (d->vmode);
17094 t1 = gen_reg_rtx (d->vmode);
17098 emit_insn (gen_loongson_punpckhhw (t0, d->op0, d->op1));
17099 emit_insn (gen_loongson_punpcklhw (t1, d->op0, d->op1));
17101 emit_insn (gen_loongson_punpckhhw (d->target, t1, t0));
17103 emit_insn (gen_loongson_punpcklhw (d->target, t1, t0));
17107 t2 = gen_reg_rtx (d->vmode);
17108 t3 = gen_reg_rtx (d->vmode);
17109 emit_insn (gen_loongson_punpckhbh (t0, d->op0, d->op1));
17110 emit_insn (gen_loongson_punpcklbh (t1, d->op0, d->op1));
17111 emit_insn (gen_loongson_punpckhbh (t2, t1, t0));
17112 emit_insn (gen_loongson_punpcklbh (t3, t1, t0));
17114 emit_insn (gen_loongson_punpckhbh (d->target, t3, t2));
17116 emit_insn (gen_loongson_punpcklbh (d->target, t3, t2));
17120 gcc_unreachable ();
17125 /* Recognize patterns for the Loongson PSHUFH instruction. */
17128 mips_expand_vpc_loongson_pshufh (struct expand_vec_perm_d *d)
17133 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
17135 if (d->vmode != V4HImode)
17140 /* Convert the selector into the packed 8-bit form for pshufh. */
17141 /* Recall that loongson is little-endian only. No big-endian
17142 adjustment required. */
17143 for (i = mask = 0; i < 4; i++)
17144 mask |= (d->perm[i] & 3) << (i * 2);
17145 rmask = force_reg (SImode, GEN_INT (mask));
17147 if (d->one_vector_p)
17148 emit_insn (gen_loongson_pshufh (d->target, d->op0, rmask));
17151 rtx t0, t1, x, merge, rmerge[4];
17153 t0 = gen_reg_rtx (V4HImode);
17154 t1 = gen_reg_rtx (V4HImode);
17155 emit_insn (gen_loongson_pshufh (t1, d->op1, rmask));
17156 emit_insn (gen_loongson_pshufh (t0, d->op0, rmask));
17158 for (i = 0; i < 4; ++i)
17159 rmerge[i] = (d->perm[i] & 4 ? constm1_rtx : const0_rtx);
17160 merge = gen_rtx_CONST_VECTOR (V4HImode, gen_rtvec_v (4, rmerge));
17161 merge = force_reg (V4HImode, merge);
17163 x = gen_rtx_AND (V4HImode, merge, t1);
17164 emit_insn (gen_rtx_SET (VOIDmode, t1, x));
17166 x = gen_rtx_NOT (V4HImode, merge);
17167 x = gen_rtx_AND (V4HImode, x, t0);
17168 emit_insn (gen_rtx_SET (VOIDmode, t0, x));
17170 x = gen_rtx_IOR (V4HImode, t0, t1);
17171 emit_insn (gen_rtx_SET (VOIDmode, d->target, x));
17177 /* Recognize broadcast patterns for the Loongson. */
17180 mips_expand_vpc_loongson_bcast (struct expand_vec_perm_d *d)
17185 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
17187 /* Note that we've already matched V2SI via punpck and V4HI via pshufh. */
17188 if (d->vmode != V8QImode)
17190 if (!d->one_vector_p)
17194 for (i = 1; i < 8; ++i)
17195 if (d->perm[i] != elt)
17201 /* With one interleave we put two of the desired element adjacent. */
17202 t0 = gen_reg_rtx (V8QImode);
17204 emit_insn (gen_loongson_punpcklbh (t0, d->op0, d->op0));
17206 emit_insn (gen_loongson_punpckhbh (t0, d->op0, d->op0));
17208 /* Shuffle that one HImode element into all locations. */
17211 t1 = gen_reg_rtx (V4HImode);
17212 emit_insn (gen_loongson_pshufh (t1, gen_lowpart (V4HImode, t0),
17213 force_reg (SImode, GEN_INT (elt))));
17215 emit_move_insn (d->target, gen_lowpart (V8QImode, t1));
17220 mips_expand_vec_perm_const_1 (struct expand_vec_perm_d *d)
17222 unsigned int i, nelt = d->nelt;
17223 unsigned char perm2[MAX_VECT_LEN];
17225 if (d->one_vector_p)
17227 /* Try interleave with alternating operands. */
17228 memcpy (perm2, d->perm, sizeof(perm2));
17229 for (i = 1; i < nelt; i += 2)
17231 if (mips_expand_vselect_vconcat (d->target, d->op0, d->op1, perm2, nelt))
17236 if (mips_expand_vselect_vconcat (d->target, d->op0, d->op1,
17240 /* Try again with swapped operands. */
17241 for (i = 0; i < nelt; ++i)
17242 perm2[i] = (d->perm[i] + nelt) & (2 * nelt - 1);
17243 if (mips_expand_vselect_vconcat (d->target, d->op1, d->op0, perm2, nelt))
17247 if (mips_expand_vpc_loongson_even_odd (d))
17249 if (mips_expand_vpc_loongson_pshufh (d))
17251 if (mips_expand_vpc_loongson_bcast (d))
17256 /* Expand a vec_perm_const pattern. */
17259 mips_expand_vec_perm_const (rtx operands[4])
17261 struct expand_vec_perm_d d;
17262 int i, nelt, which;
17263 unsigned char orig_perm[MAX_VECT_LEN];
17267 d.target = operands[0];
17268 d.op0 = operands[1];
17269 d.op1 = operands[2];
17272 d.vmode = GET_MODE (d.target);
17273 gcc_assert (VECTOR_MODE_P (d.vmode));
17274 d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
17275 d.testing_p = false;
17277 for (i = which = 0; i < nelt; ++i)
17279 rtx e = XVECEXP (sel, 0, i);
17280 int ei = INTVAL (e) & (2 * nelt - 1);
17281 which |= (ei < nelt ? 1 : 2);
17284 memcpy (d.perm, orig_perm, MAX_VECT_LEN);
17292 d.one_vector_p = false;
17293 if (!rtx_equal_p (d.op0, d.op1))
17298 for (i = 0; i < nelt; ++i)
17299 d.perm[i] &= nelt - 1;
17301 d.one_vector_p = true;
17306 d.one_vector_p = true;
17310 ok = mips_expand_vec_perm_const_1 (&d);
17312 /* If we were given a two-vector permutation which just happened to
17313 have both input vectors equal, we folded this into a one-vector
17314 permutation. There are several loongson patterns that are matched
17315 via direct vec_select+vec_concat expansion, but we do not have
17316 support in mips_expand_vec_perm_const_1 to guess the adjustment
17317 that should be made for a single operand. Just try again with
17318 the original permutation. */
17319 if (!ok && which == 3)
17321 d.op0 = operands[1];
17322 d.op1 = operands[2];
17323 d.one_vector_p = false;
17324 memcpy (d.perm, orig_perm, MAX_VECT_LEN);
17325 ok = mips_expand_vec_perm_const_1 (&d);
17331 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST_OK. */
17334 mips_vectorize_vec_perm_const_ok (enum machine_mode vmode,
17335 const unsigned char *sel)
17337 struct expand_vec_perm_d d;
17338 unsigned int i, nelt, which;
17342 d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
17343 d.testing_p = true;
17344 memcpy (d.perm, sel, nelt);
17346 /* Categorize the set of elements in the selector. */
17347 for (i = which = 0; i < nelt; ++i)
17349 unsigned char e = d.perm[i];
17350 gcc_assert (e < 2 * nelt);
17351 which |= (e < nelt ? 1 : 2);
17354 /* For all elements from second vector, fold the elements to first. */
17356 for (i = 0; i < nelt; ++i)
17359 /* Check whether the mask can be applied to the vector type. */
17360 d.one_vector_p = (which != 3);
17362 d.target = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 1);
17363 d.op1 = d.op0 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 2);
17364 if (!d.one_vector_p)
17365 d.op1 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 3);
17368 ret = mips_expand_vec_perm_const_1 (&d);
17374 /* Expand an integral vector unpack operation. */
17377 mips_expand_vec_unpack (rtx operands[2], bool unsigned_p, bool high_p)
17379 enum machine_mode imode = GET_MODE (operands[1]);
17380 rtx (*unpack) (rtx, rtx, rtx);
17381 rtx (*cmpgt) (rtx, rtx, rtx);
17382 rtx tmp, dest, zero;
17388 unpack = gen_loongson_punpckhbh;
17390 unpack = gen_loongson_punpcklbh;
17391 cmpgt = gen_loongson_pcmpgtb;
17395 unpack = gen_loongson_punpckhhw;
17397 unpack = gen_loongson_punpcklhw;
17398 cmpgt = gen_loongson_pcmpgth;
17401 gcc_unreachable ();
17404 zero = force_reg (imode, CONST0_RTX (imode));
17409 tmp = gen_reg_rtx (imode);
17410 emit_insn (cmpgt (tmp, zero, operands[1]));
17413 dest = gen_reg_rtx (imode);
17414 emit_insn (unpack (dest, operands[1], tmp));
17416 emit_move_insn (operands[0], gen_lowpart (GET_MODE (operands[0]), dest));
17419 /* A subroutine of mips_expand_vec_init, match constant vector elements. */
17422 mips_constant_elt_p (rtx x)
17424 return CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE;
17427 /* A subroutine of mips_expand_vec_init, expand via broadcast. */
17430 mips_expand_vi_broadcast (enum machine_mode vmode, rtx target, rtx elt)
17432 struct expand_vec_perm_d d;
17436 if (elt != const0_rtx)
17437 elt = force_reg (GET_MODE_INNER (vmode), elt);
17439 elt = gen_lowpart (DImode, elt);
17441 t1 = gen_reg_rtx (vmode);
17445 emit_insn (gen_loongson_vec_init1_v8qi (t1, elt));
17448 emit_insn (gen_loongson_vec_init1_v4hi (t1, elt));
17451 gcc_unreachable ();
17454 memset (&d, 0, sizeof (d));
17459 d.nelt = GET_MODE_NUNITS (vmode);
17460 d.one_vector_p = true;
17462 ok = mips_expand_vec_perm_const_1 (&d);
17466 /* A subroutine of mips_expand_vec_init, replacing all of the non-constant
17467 elements of VALS with zeros, copy the constant vector to TARGET. */
17470 mips_expand_vi_constant (enum machine_mode vmode, unsigned nelt,
17471 rtx target, rtx vals)
17473 rtvec vec = shallow_copy_rtvec (XVEC (vals, 0));
17476 for (i = 0; i < nelt; ++i)
17478 if (!mips_constant_elt_p (RTVEC_ELT (vec, i)))
17479 RTVEC_ELT (vec, i) = const0_rtx;
17482 emit_move_insn (target, gen_rtx_CONST_VECTOR (vmode, vec));
17486 /* A subroutine of mips_expand_vec_init, expand via pinsrh. */
17489 mips_expand_vi_loongson_one_pinsrh (rtx target, rtx vals, unsigned one_var)
17491 mips_expand_vi_constant (V4HImode, 4, target, vals);
17493 emit_insn (gen_vec_setv4hi (target, target, XVECEXP (vals, 0, one_var),
17494 GEN_INT (one_var)));
17497 /* A subroutine of mips_expand_vec_init, expand anything via memory. */
17500 mips_expand_vi_general (enum machine_mode vmode, enum machine_mode imode,
17501 unsigned nelt, unsigned nvar, rtx target, rtx vals)
17503 rtx mem = assign_stack_temp (vmode, GET_MODE_SIZE (vmode));
17504 unsigned int i, isize = GET_MODE_SIZE (imode);
17507 mips_expand_vi_constant (vmode, nelt, mem, vals);
17509 for (i = 0; i < nelt; ++i)
17511 rtx x = XVECEXP (vals, 0, i);
17512 if (!mips_constant_elt_p (x))
17513 emit_move_insn (adjust_address (mem, imode, i * isize), x);
17516 emit_move_insn (target, mem);
17519 /* Expand a vector initialization. */
17522 mips_expand_vector_init (rtx target, rtx vals)
17524 enum machine_mode vmode = GET_MODE (target);
17525 enum machine_mode imode = GET_MODE_INNER (vmode);
17526 unsigned i, nelt = GET_MODE_NUNITS (vmode);
17527 unsigned nvar = 0, one_var = -1u;
17528 bool all_same = true;
17531 for (i = 0; i < nelt; ++i)
17533 x = XVECEXP (vals, 0, i);
17534 if (!mips_constant_elt_p (x))
17535 nvar++, one_var = i;
17536 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
17540 /* Load constants from the pool, or whatever's handy. */
17543 emit_move_insn (target, gen_rtx_CONST_VECTOR (vmode, XVEC (vals, 0)));
17547 /* For two-part initialization, always use CONCAT. */
17550 rtx op0 = force_reg (imode, XVECEXP (vals, 0, 0));
17551 rtx op1 = force_reg (imode, XVECEXP (vals, 0, 1));
17552 x = gen_rtx_VEC_CONCAT (vmode, op0, op1);
17553 emit_insn (gen_rtx_SET (VOIDmode, target, x));
17557 /* Loongson is the only cpu with vectors with more elements. */
17558 gcc_assert (TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS);
17560 /* If all values are identical, broadcast the value. */
17563 mips_expand_vi_broadcast (vmode, target, XVECEXP (vals, 0, 0));
17567 /* If we've only got one non-variable V4HImode, use PINSRH. */
17568 if (nvar == 1 && vmode == V4HImode)
17570 mips_expand_vi_loongson_one_pinsrh (target, vals, one_var);
17574 mips_expand_vi_general (vmode, imode, nelt, nvar, target, vals);
17577 /* Expand a vector reduction. */
17580 mips_expand_vec_reduc (rtx target, rtx in, rtx (*gen)(rtx, rtx, rtx))
17582 enum machine_mode vmode = GET_MODE (in);
17583 unsigned char perm2[2];
17584 rtx last, next, fold, x;
17588 fold = gen_reg_rtx (vmode);
17592 /* Use PUL/PLU to produce { L, H } op { H, L }.
17593 By reversing the pair order, rather than a pure interleave high,
17594 we avoid erroneous exceptional conditions that we might otherwise
17595 produce from the computation of H op H. */
17598 ok = mips_expand_vselect_vconcat (fold, last, last, perm2, 2);
17603 /* Use interleave to produce { H, L } op { H, H }. */
17604 emit_insn (gen_loongson_punpckhwd (fold, last, last));
17608 /* Perform the first reduction with interleave,
17609 and subsequent reductions with shifts. */
17610 emit_insn (gen_loongson_punpckhwd_hi (fold, last, last));
17612 next = gen_reg_rtx (vmode);
17613 emit_insn (gen (next, last, fold));
17616 fold = gen_reg_rtx (vmode);
17617 x = force_reg (SImode, GEN_INT (16));
17618 emit_insn (gen_vec_shr_v4hi (fold, last, x));
17622 emit_insn (gen_loongson_punpckhwd_qi (fold, last, last));
17624 next = gen_reg_rtx (vmode);
17625 emit_insn (gen (next, last, fold));
17628 fold = gen_reg_rtx (vmode);
17629 x = force_reg (SImode, GEN_INT (16));
17630 emit_insn (gen_vec_shr_v8qi (fold, last, x));
17632 next = gen_reg_rtx (vmode);
17633 emit_insn (gen (next, last, fold));
17636 fold = gen_reg_rtx (vmode);
17637 x = force_reg (SImode, GEN_INT (8));
17638 emit_insn (gen_vec_shr_v8qi (fold, last, x));
17642 gcc_unreachable ();
17645 emit_insn (gen (target, last, fold));
17648 /* Expand a vector minimum/maximum. */
17651 mips_expand_vec_minmax (rtx target, rtx op0, rtx op1,
17652 rtx (*cmp) (rtx, rtx, rtx), bool min_p)
17654 enum machine_mode vmode = GET_MODE (target);
17657 tc = gen_reg_rtx (vmode);
17658 t0 = gen_reg_rtx (vmode);
17659 t1 = gen_reg_rtx (vmode);
17662 emit_insn (cmp (tc, op0, op1));
17664 x = gen_rtx_AND (vmode, tc, (min_p ? op1 : op0));
17665 emit_insn (gen_rtx_SET (VOIDmode, t0, x));
17667 x = gen_rtx_NOT (vmode, tc);
17668 x = gen_rtx_AND (vmode, x, (min_p ? op0 : op1));
17669 emit_insn (gen_rtx_SET (VOIDmode, t1, x));
17671 x = gen_rtx_IOR (vmode, t0, t1);
17672 emit_insn (gen_rtx_SET (VOIDmode, target, x));
17675 /* Initialize the GCC target structure. */
17676 #undef TARGET_ASM_ALIGNED_HI_OP
17677 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
17678 #undef TARGET_ASM_ALIGNED_SI_OP
17679 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
17680 #undef TARGET_ASM_ALIGNED_DI_OP
17681 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
17683 #undef TARGET_OPTION_OVERRIDE
17684 #define TARGET_OPTION_OVERRIDE mips_option_override
17686 #undef TARGET_LEGITIMIZE_ADDRESS
17687 #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
17689 #undef TARGET_ASM_FUNCTION_PROLOGUE
17690 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
17691 #undef TARGET_ASM_FUNCTION_EPILOGUE
17692 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
17693 #undef TARGET_ASM_SELECT_RTX_SECTION
17694 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
17695 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
17696 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
17698 #undef TARGET_SCHED_INIT
17699 #define TARGET_SCHED_INIT mips_sched_init
17700 #undef TARGET_SCHED_REORDER
17701 #define TARGET_SCHED_REORDER mips_sched_reorder
17702 #undef TARGET_SCHED_REORDER2
17703 #define TARGET_SCHED_REORDER2 mips_sched_reorder2
17704 #undef TARGET_SCHED_VARIABLE_ISSUE
17705 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
17706 #undef TARGET_SCHED_ADJUST_COST
17707 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
17708 #undef TARGET_SCHED_ISSUE_RATE
17709 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
17710 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
17711 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
17712 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
17713 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
17714 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
17715 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
17716 mips_multipass_dfa_lookahead
17717 #undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
17718 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
17719 mips_small_register_classes_for_mode_p
17721 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
17722 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
17724 #undef TARGET_INSERT_ATTRIBUTES
17725 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
17726 #undef TARGET_MERGE_DECL_ATTRIBUTES
17727 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
17728 #undef TARGET_SET_CURRENT_FUNCTION
17729 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
17731 #undef TARGET_VALID_POINTER_MODE
17732 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
17733 #undef TARGET_REGISTER_MOVE_COST
17734 #define TARGET_REGISTER_MOVE_COST mips_register_move_cost
17735 #undef TARGET_MEMORY_MOVE_COST
17736 #define TARGET_MEMORY_MOVE_COST mips_memory_move_cost
17737 #undef TARGET_RTX_COSTS
17738 #define TARGET_RTX_COSTS mips_rtx_costs
17739 #undef TARGET_ADDRESS_COST
17740 #define TARGET_ADDRESS_COST mips_address_cost
17742 #undef TARGET_IN_SMALL_DATA_P
17743 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
17745 #undef TARGET_MACHINE_DEPENDENT_REORG
17746 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
17748 #undef TARGET_PREFERRED_RELOAD_CLASS
17749 #define TARGET_PREFERRED_RELOAD_CLASS mips_preferred_reload_class
17751 #undef TARGET_ASM_FILE_START
17752 #define TARGET_ASM_FILE_START mips_file_start
17753 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
17754 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
17755 #undef TARGET_ASM_CODE_END
17756 #define TARGET_ASM_CODE_END mips_code_end
17758 #undef TARGET_INIT_LIBFUNCS
17759 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
17761 #undef TARGET_BUILD_BUILTIN_VA_LIST
17762 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
17763 #undef TARGET_EXPAND_BUILTIN_VA_START
17764 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
17765 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
17766 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
17768 #undef TARGET_PROMOTE_FUNCTION_MODE
17769 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
17770 #undef TARGET_PROMOTE_PROTOTYPES
17771 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
17773 #undef TARGET_FUNCTION_VALUE
17774 #define TARGET_FUNCTION_VALUE mips_function_value
17775 #undef TARGET_LIBCALL_VALUE
17776 #define TARGET_LIBCALL_VALUE mips_libcall_value
17777 #undef TARGET_FUNCTION_VALUE_REGNO_P
17778 #define TARGET_FUNCTION_VALUE_REGNO_P mips_function_value_regno_p
17779 #undef TARGET_RETURN_IN_MEMORY
17780 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
17781 #undef TARGET_RETURN_IN_MSB
17782 #define TARGET_RETURN_IN_MSB mips_return_in_msb
17784 #undef TARGET_ASM_OUTPUT_MI_THUNK
17785 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
17786 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
17787 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
17789 #undef TARGET_PRINT_OPERAND
17790 #define TARGET_PRINT_OPERAND mips_print_operand
17791 #undef TARGET_PRINT_OPERAND_ADDRESS
17792 #define TARGET_PRINT_OPERAND_ADDRESS mips_print_operand_address
17793 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
17794 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mips_print_operand_punct_valid_p
17796 #undef TARGET_SETUP_INCOMING_VARARGS
17797 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
17798 #undef TARGET_STRICT_ARGUMENT_NAMING
17799 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
17800 #undef TARGET_MUST_PASS_IN_STACK
17801 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
17802 #undef TARGET_PASS_BY_REFERENCE
17803 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
17804 #undef TARGET_CALLEE_COPIES
17805 #define TARGET_CALLEE_COPIES mips_callee_copies
17806 #undef TARGET_ARG_PARTIAL_BYTES
17807 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
17808 #undef TARGET_FUNCTION_ARG
17809 #define TARGET_FUNCTION_ARG mips_function_arg
17810 #undef TARGET_FUNCTION_ARG_ADVANCE
17811 #define TARGET_FUNCTION_ARG_ADVANCE mips_function_arg_advance
17812 #undef TARGET_FUNCTION_ARG_BOUNDARY
17813 #define TARGET_FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
17815 #undef TARGET_MODE_REP_EXTENDED
17816 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
17818 #undef TARGET_VECTOR_MODE_SUPPORTED_P
17819 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
17821 #undef TARGET_SCALAR_MODE_SUPPORTED_P
17822 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
17824 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
17825 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE mips_preferred_simd_mode
17827 #undef TARGET_INIT_BUILTINS
17828 #define TARGET_INIT_BUILTINS mips_init_builtins
17829 #undef TARGET_BUILTIN_DECL
17830 #define TARGET_BUILTIN_DECL mips_builtin_decl
17831 #undef TARGET_EXPAND_BUILTIN
17832 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
17834 #undef TARGET_HAVE_TLS
17835 #define TARGET_HAVE_TLS HAVE_AS_TLS
17837 #undef TARGET_CANNOT_FORCE_CONST_MEM
17838 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
17840 #undef TARGET_LEGITIMATE_CONSTANT_P
17841 #define TARGET_LEGITIMATE_CONSTANT_P mips_legitimate_constant_p
17843 #undef TARGET_ENCODE_SECTION_INFO
17844 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
17846 #undef TARGET_ATTRIBUTE_TABLE
17847 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
17848 /* All our function attributes are related to how out-of-line copies should
17849 be compiled or called. They don't in themselves prevent inlining. */
17850 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
17851 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
17853 #undef TARGET_EXTRA_LIVE_ON_ENTRY
17854 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
17856 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
17857 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
17858 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
17859 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
17861 #undef TARGET_COMP_TYPE_ATTRIBUTES
17862 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
17864 #ifdef HAVE_AS_DTPRELWORD
17865 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
17866 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
17868 #undef TARGET_DWARF_REGISTER_SPAN
17869 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
17871 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
17872 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
17874 #undef TARGET_LEGITIMATE_ADDRESS_P
17875 #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p
17877 #undef TARGET_FRAME_POINTER_REQUIRED
17878 #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required
17880 #undef TARGET_CAN_ELIMINATE
17881 #define TARGET_CAN_ELIMINATE mips_can_eliminate
17883 #undef TARGET_CONDITIONAL_REGISTER_USAGE
17884 #define TARGET_CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage
17886 #undef TARGET_TRAMPOLINE_INIT
17887 #define TARGET_TRAMPOLINE_INIT mips_trampoline_init
17889 #undef TARGET_ASM_OUTPUT_SOURCE_FILENAME
17890 #define TARGET_ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
17892 #undef TARGET_SHIFT_TRUNCATION_MASK
17893 #define TARGET_SHIFT_TRUNCATION_MASK mips_shift_truncation_mask
17895 #undef TARGET_PREPARE_PCH_SAVE
17896 #define TARGET_PREPARE_PCH_SAVE mips_prepare_pch_save
17898 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
17899 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK mips_vectorize_vec_perm_const_ok
17901 struct gcc_target targetm = TARGET_INITIALIZER;
17903 #include "gt-mips.h"