1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989-2014 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky, lich@inria.inria.fr.
4 Changes by Michael Meissner, meissner@osf.org.
5 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 Brendan Eich, brendan@microunity.com.
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
30 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
38 #include "stringpool.h"
39 #include "stor-layout.h"
50 #include "hash-table.h"
53 #include "target-def.h"
54 #include "common/common-target.h"
55 #include "langhooks.h"
56 #include "sched-int.h"
58 #include "basic-block.h"
59 #include "tree-ssa-alias.h"
60 #include "internal-fn.h"
61 #include "gimple-fold.h"
63 #include "gimple-expr.h"
68 #include "diagnostic.h"
69 #include "target-globals.h"
71 #include "tree-pass.h"
76 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
77 #define UNSPEC_ADDRESS_P(X) \
78 (GET_CODE (X) == UNSPEC \
79 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
80 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
82 /* Extract the symbol or label from UNSPEC wrapper X. */
83 #define UNSPEC_ADDRESS(X) \
86 /* Extract the symbol type from UNSPEC wrapper X. */
87 #define UNSPEC_ADDRESS_TYPE(X) \
88 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
90 /* The maximum distance between the top of the stack frame and the
91 value $sp has when we save and restore registers.
93 The value for normal-mode code must be a SMALL_OPERAND and must
94 preserve the maximum stack alignment. We therefore use a value
95 of 0x7ff0 in this case.
97 microMIPS LWM and SWM support 12-bit offsets (from -0x800 to 0x7ff),
98 so we use a maximum of 0x7f0 for TARGET_MICROMIPS.
100 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
101 up to 0x7f8 bytes and can usually save or restore all the registers
102 that we need to save or restore. (Note that we can only use these
103 instructions for o32, for which the stack alignment is 8 bytes.)
105 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
106 RESTORE are not available. We can then use unextended instructions
107 to save and restore registers, and to allocate and deallocate the top
108 part of the frame. */
109 #define MIPS_MAX_FIRST_STACK_STEP \
110 (!TARGET_COMPRESSION ? 0x7ff0 \
111 : TARGET_MICROMIPS || GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
112 : TARGET_64BIT ? 0x100 : 0x400)
114 /* True if INSN is a mips.md pattern or asm statement. */
115 /* ??? This test exists through the compiler, perhaps it should be
117 #define USEFUL_INSN_P(INSN) \
118 (NONDEBUG_INSN_P (INSN) \
119 && GET_CODE (PATTERN (INSN)) != USE \
120 && GET_CODE (PATTERN (INSN)) != CLOBBER)
122 /* If INSN is a delayed branch sequence, return the first instruction
123 in the sequence, otherwise return INSN itself. */
124 #define SEQ_BEGIN(INSN) \
125 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
126 ? as_a <rtx_insn *> (XVECEXP (PATTERN (INSN), 0, 0)) \
129 /* Likewise for the last instruction in a delayed branch sequence. */
130 #define SEQ_END(INSN) \
131 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
132 ? as_a <rtx_insn *> (XVECEXP (PATTERN (INSN), \
134 XVECLEN (PATTERN (INSN), 0) - 1)) \
137 /* Execute the following loop body with SUBINSN set to each instruction
138 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
139 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
140 for ((SUBINSN) = SEQ_BEGIN (INSN); \
141 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
142 (SUBINSN) = NEXT_INSN (SUBINSN))
144 /* True if bit BIT is set in VALUE. */
145 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
147 /* Return the opcode for a ptr_mode load of the form:
149 l[wd] DEST, OFFSET(BASE). */
150 #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \
151 (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \
156 /* Return the opcode to move register SRC into register DEST. */
157 #define MIPS_MOVE(DEST, SRC) \
158 ((TARGET_64BIT ? 0x2d : 0x21) \
162 /* Return the opcode for:
165 #define MIPS_LUI(DEST, VALUE) \
166 ((0xf << 26) | ((DEST) << 16) | (VALUE))
168 /* Return the opcode to jump to register DEST. */
169 #define MIPS_JR(DEST) \
170 (((DEST) << 21) | 0x8)
172 /* Return the opcode for:
174 bal . + (1 + OFFSET) * 4. */
175 #define MIPS_BAL(OFFSET) \
176 ((0x1 << 26) | (0x11 << 16) | (OFFSET))
178 /* Return the usual opcode for a nop. */
181 /* Classifies an address.
184 A natural register + offset address. The register satisfies
185 mips_valid_base_register_p and the offset is a const_arith_operand.
188 A LO_SUM rtx. The first operand is a valid base register and
189 the second operand is a symbolic address.
192 A signed 16-bit constant address.
195 A constant symbolic address. */
196 enum mips_address_type {
203 /* Macros to create an enumeration identifier for a function prototype. */
204 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
205 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
206 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
207 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
209 /* Classifies the prototype of a built-in function. */
210 enum mips_function_type {
211 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
212 #include "config/mips/mips-ftypes.def"
213 #undef DEF_MIPS_FTYPE
217 /* Specifies how a built-in function should be converted into rtl. */
218 enum mips_builtin_type {
219 /* The function corresponds directly to an .md pattern. The return
220 value is mapped to operand 0 and the arguments are mapped to
221 operands 1 and above. */
224 /* The function corresponds directly to an .md pattern. There is no return
225 value and the arguments are mapped to operands 0 and above. */
226 MIPS_BUILTIN_DIRECT_NO_TARGET,
228 /* The function corresponds to a comparison instruction followed by
229 a mips_cond_move_tf_ps pattern. The first two arguments are the
230 values to compare and the second two arguments are the vector
231 operands for the movt.ps or movf.ps instruction (in assembly order). */
235 /* The function corresponds to a V2SF comparison instruction. Operand 0
236 of this instruction is the result of the comparison, which has mode
237 CCV2 or CCV4. The function arguments are mapped to operands 1 and
238 above. The function's return value is an SImode boolean that is
239 true under the following conditions:
241 MIPS_BUILTIN_CMP_ANY: one of the registers is true
242 MIPS_BUILTIN_CMP_ALL: all of the registers are true
243 MIPS_BUILTIN_CMP_LOWER: the first register is true
244 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
245 MIPS_BUILTIN_CMP_ANY,
246 MIPS_BUILTIN_CMP_ALL,
247 MIPS_BUILTIN_CMP_UPPER,
248 MIPS_BUILTIN_CMP_LOWER,
250 /* As above, but the instruction only sets a single $fcc register. */
251 MIPS_BUILTIN_CMP_SINGLE,
253 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
254 MIPS_BUILTIN_BPOSGE32
257 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
258 #define MIPS_FP_CONDITIONS(MACRO) \
276 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
277 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
278 enum mips_fp_condition {
279 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
281 #undef DECLARE_MIPS_COND
283 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
284 #define STRINGIFY(X) #X
285 static const char *const mips_fp_conditions[] = {
286 MIPS_FP_CONDITIONS (STRINGIFY)
290 /* A class used to control a comdat-style stub that we output in each
291 translation unit that needs it. */
292 class mips_one_only_stub {
294 virtual ~mips_one_only_stub () {}
296 /* Return the name of the stub. */
297 virtual const char *get_name () = 0;
299 /* Output the body of the function to asm_out_file. */
300 virtual void output_body () = 0;
303 /* Tuning information that is automatically derived from other sources
304 (such as the scheduler). */
306 /* The architecture and tuning settings that this structure describes. */
310 /* True if this structure describes MIPS16 settings. */
313 /* True if the structure has been initialized. */
316 /* True if "MULT $0, $0" is preferable to "MTLO $0; MTHI $0"
317 when optimizing for speed. */
318 bool fast_mult_zero_zero_p;
321 /* Information about a function's frame layout. */
322 struct GTY(()) mips_frame_info {
323 /* The size of the frame in bytes. */
324 HOST_WIDE_INT total_size;
326 /* The number of bytes allocated to variables. */
327 HOST_WIDE_INT var_size;
329 /* The number of bytes allocated to outgoing function arguments. */
330 HOST_WIDE_INT args_size;
332 /* The number of bytes allocated to the .cprestore slot, or 0 if there
334 HOST_WIDE_INT cprestore_size;
336 /* Bit X is set if the function saves or restores GPR X. */
339 /* Likewise FPR X. */
342 /* Likewise doubleword accumulator X ($acX). */
343 unsigned int acc_mask;
345 /* The number of GPRs, FPRs, doubleword accumulators and COP0
349 unsigned int num_acc;
350 unsigned int num_cop0_regs;
352 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
353 save slots from the top of the frame, or zero if no such slots are
355 HOST_WIDE_INT gp_save_offset;
356 HOST_WIDE_INT fp_save_offset;
357 HOST_WIDE_INT acc_save_offset;
358 HOST_WIDE_INT cop0_save_offset;
360 /* Likewise, but giving offsets from the bottom of the frame. */
361 HOST_WIDE_INT gp_sp_offset;
362 HOST_WIDE_INT fp_sp_offset;
363 HOST_WIDE_INT acc_sp_offset;
364 HOST_WIDE_INT cop0_sp_offset;
366 /* Similar, but the value passed to _mcount. */
367 HOST_WIDE_INT ra_fp_offset;
369 /* The offset of arg_pointer_rtx from the bottom of the frame. */
370 HOST_WIDE_INT arg_pointer_offset;
372 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
373 HOST_WIDE_INT hard_frame_pointer_offset;
376 struct GTY(()) machine_function {
377 /* The next floating-point condition-code register to allocate
378 for ISA_HAS_8CC targets, relative to ST_REG_FIRST. */
379 unsigned int next_fcc;
381 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
382 rtx mips16_gp_pseudo_rtx;
384 /* The number of extra stack bytes taken up by register varargs.
385 This area is allocated by the callee at the very top of the frame. */
388 /* The current frame information, calculated by mips_compute_frame_info. */
389 struct mips_frame_info frame;
391 /* The register to use as the function's global pointer, or INVALID_REGNUM
392 if the function doesn't need one. */
393 unsigned int global_pointer;
395 /* How many instructions it takes to load a label into $AT, or 0 if
396 this property hasn't yet been calculated. */
397 unsigned int load_label_num_insns;
399 /* True if mips_adjust_insn_length should ignore an instruction's
401 bool ignore_hazard_length_p;
403 /* True if the whole function is suitable for .set noreorder and
405 bool all_noreorder_p;
407 /* True if the function has "inflexible" and "flexible" references
408 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
409 and mips_cfun_has_flexible_gp_ref_p for details. */
410 bool has_inflexible_gp_insn_p;
411 bool has_flexible_gp_insn_p;
413 /* True if the function's prologue must load the global pointer
414 value into pic_offset_table_rtx and store the same value in
415 the function's cprestore slot (if any). Even if this value
416 is currently false, we may decide to set it to true later;
417 see mips_must_initialize_gp_p () for details. */
418 bool must_initialize_gp_p;
420 /* True if the current function must restore $gp after any potential
421 clobber. This value is only meaningful during the first post-epilogue
422 split_insns pass; see mips_must_initialize_gp_p () for details. */
423 bool must_restore_gp_when_clobbered_p;
425 /* True if this is an interrupt handler. */
426 bool interrupt_handler_p;
428 /* True if this is an interrupt handler that uses shadow registers. */
429 bool use_shadow_register_set_p;
431 /* True if this is an interrupt handler that should keep interrupts
433 bool keep_interrupts_masked_p;
435 /* True if this is an interrupt handler that should use DERET
437 bool use_debug_exception_return_p;
440 /* Information about a single argument. */
441 struct mips_arg_info {
442 /* True if the argument is passed in a floating-point register, or
443 would have been if we hadn't run out of registers. */
446 /* The number of words passed in registers, rounded up. */
447 unsigned int reg_words;
449 /* For EABI, the offset of the first register from GP_ARG_FIRST or
450 FP_ARG_FIRST. For other ABIs, the offset of the first register from
451 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
452 comment for details).
454 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
456 unsigned int reg_offset;
458 /* The number of words that must be passed on the stack, rounded up. */
459 unsigned int stack_words;
461 /* The offset from the start of the stack overflow area of the argument's
462 first stack word. Only meaningful when STACK_WORDS is nonzero. */
463 unsigned int stack_offset;
466 /* Information about an address described by mips_address_type.
472 REG is the base register and OFFSET is the constant offset.
475 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
476 is the type of symbol it references.
479 SYMBOL_TYPE is the type of symbol that the address references. */
480 struct mips_address_info {
481 enum mips_address_type type;
484 enum mips_symbol_type symbol_type;
487 /* One stage in a constant building sequence. These sequences have
491 A = A CODE[1] VALUE[1]
492 A = A CODE[2] VALUE[2]
495 where A is an accumulator, each CODE[i] is a binary rtl operation
496 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
497 struct mips_integer_op {
499 unsigned HOST_WIDE_INT value;
502 /* The largest number of operations needed to load an integer constant.
503 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
504 When the lowest bit is clear, we can try, but reject a sequence with
505 an extra SLL at the end. */
506 #define MIPS_MAX_INTEGER_OPS 7
508 /* Information about a MIPS16e SAVE or RESTORE instruction. */
509 struct mips16e_save_restore_info {
510 /* The number of argument registers saved by a SAVE instruction.
511 0 for RESTORE instructions. */
514 /* Bit X is set if the instruction saves or restores GPR X. */
517 /* The total number of bytes to allocate. */
521 /* Costs of various operations on the different architectures. */
523 struct mips_rtx_cost_data
525 unsigned short fp_add;
526 unsigned short fp_mult_sf;
527 unsigned short fp_mult_df;
528 unsigned short fp_div_sf;
529 unsigned short fp_div_df;
530 unsigned short int_mult_si;
531 unsigned short int_mult_di;
532 unsigned short int_div_si;
533 unsigned short int_div_di;
534 unsigned short branch_cost;
535 unsigned short memory_latency;
538 /* Global variables for machine-dependent things. */
540 /* The -G setting, or the configuration's default small-data limit if
541 no -G option is given. */
542 static unsigned int mips_small_data_threshold;
544 /* The number of file directives written by mips_output_filename. */
545 int num_source_filenames;
547 /* The name that appeared in the last .file directive written by
548 mips_output_filename, or "" if mips_output_filename hasn't
549 written anything yet. */
550 const char *current_function_file = "";
552 /* Arrays that map GCC register numbers to debugger register numbers. */
553 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
554 int mips_dwarf_regno[FIRST_PSEUDO_REGISTER];
556 /* Information about the current function's epilogue, used only while
559 /* A list of queued REG_CFA_RESTORE notes. */
562 /* The CFA is currently defined as CFA_REG + CFA_OFFSET. */
564 HOST_WIDE_INT cfa_offset;
566 /* The offset of the CFA from the stack pointer while restoring
568 HOST_WIDE_INT cfa_restore_sp_offset;
571 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
572 struct mips_asm_switch mips_noreorder = { "reorder", 0 };
573 struct mips_asm_switch mips_nomacro = { "macro", 0 };
574 struct mips_asm_switch mips_noat = { "at", 0 };
576 /* True if we're writing out a branch-likely instruction rather than a
578 static bool mips_branch_likely;
580 /* The current instruction-set architecture. */
581 enum processor mips_arch;
582 const struct mips_cpu_info *mips_arch_info;
584 /* The processor that we should tune the code for. */
585 enum processor mips_tune;
586 const struct mips_cpu_info *mips_tune_info;
588 /* The ISA level associated with mips_arch. */
591 /* The ISA revision level. This is 0 for MIPS I to V and N for
595 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
596 static const struct mips_cpu_info *mips_isa_option_info;
598 /* Which cost information to use. */
599 static const struct mips_rtx_cost_data *mips_cost;
601 /* The ambient target flags, excluding MASK_MIPS16. */
602 static int mips_base_target_flags;
604 /* The default compression mode. */
605 unsigned int mips_base_compression_flags;
607 /* The ambient values of other global variables. */
608 static int mips_base_schedule_insns; /* flag_schedule_insns */
609 static int mips_base_reorder_blocks_and_partition; /* flag_reorder... */
610 static int mips_base_move_loop_invariants; /* flag_move_loop_invariants */
611 static int mips_base_align_loops; /* align_loops */
612 static int mips_base_align_jumps; /* align_jumps */
613 static int mips_base_align_functions; /* align_functions */
615 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
616 bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
618 /* Index C is true if character C is a valid PRINT_OPERAND punctation
620 static bool mips_print_operand_punct[256];
622 static GTY (()) int mips_output_filename_first_time = 1;
624 /* mips_split_p[X] is true if symbols of type X can be split by
625 mips_split_symbol. */
626 bool mips_split_p[NUM_SYMBOL_TYPES];
628 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
629 can be split by mips_split_symbol. */
630 bool mips_split_hi_p[NUM_SYMBOL_TYPES];
632 /* mips_use_pcrel_pool_p[X] is true if symbols of type X should be
633 forced into a PC-relative constant pool. */
634 bool mips_use_pcrel_pool_p[NUM_SYMBOL_TYPES];
636 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
637 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
638 if they are matched by a special .md file pattern. */
639 const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
641 /* Likewise for HIGHs. */
642 const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
644 /* Target state for MIPS16. */
645 struct target_globals *mips16_globals;
647 /* Cached value of can_issue_more. This is cached in mips_variable_issue hook
648 and returned from mips_sched_reorder2. */
649 static int cached_can_issue_more;
651 /* The stubs for various MIPS16 support functions, if used. */
652 static mips_one_only_stub *mips16_rdhwr_stub;
653 static mips_one_only_stub *mips16_get_fcsr_stub;
654 static mips_one_only_stub *mips16_set_fcsr_stub;
656 /* Index R is the smallest register class that contains register R. */
657 const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = {
658 LEA_REGS, LEA_REGS, M16_STORE_REGS, V1_REG,
659 M16_STORE_REGS, M16_STORE_REGS, M16_STORE_REGS, M16_STORE_REGS,
660 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
661 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
662 M16_REGS, M16_STORE_REGS, LEA_REGS, LEA_REGS,
663 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
664 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
665 LEA_REGS, M16_SP_REGS, LEA_REGS, LEA_REGS,
667 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
668 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
669 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
670 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
671 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
672 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
673 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
674 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
675 MD0_REG, MD1_REG, NO_REGS, ST_REGS,
676 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
677 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
678 NO_REGS, FRAME_REGS, FRAME_REGS, NO_REGS,
679 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
680 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
681 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
682 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
683 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
684 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
685 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
686 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
687 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
688 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
689 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
690 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
691 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
692 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
693 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
694 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
695 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
696 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
697 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
698 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
699 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
700 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
701 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
702 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
703 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
704 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
705 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
708 /* The value of TARGET_ATTRIBUTE_TABLE. */
709 static const struct attribute_spec mips_attribute_table[] = {
710 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
712 { "long_call", 0, 0, false, true, true, NULL, false },
713 { "far", 0, 0, false, true, true, NULL, false },
714 { "near", 0, 0, false, true, true, NULL, false },
715 /* We would really like to treat "mips16" and "nomips16" as type
716 attributes, but GCC doesn't provide the hooks we need to support
717 the right conversion rules. As declaration attributes, they affect
718 code generation but don't carry other semantics. */
719 { "mips16", 0, 0, true, false, false, NULL, false },
720 { "nomips16", 0, 0, true, false, false, NULL, false },
721 { "micromips", 0, 0, true, false, false, NULL, false },
722 { "nomicromips", 0, 0, true, false, false, NULL, false },
723 { "nocompression", 0, 0, true, false, false, NULL, false },
724 /* Allow functions to be specified as interrupt handlers */
725 { "interrupt", 0, 0, false, true, true, NULL, false },
726 { "use_shadow_register_set", 0, 0, false, true, true, NULL, false },
727 { "keep_interrupts_masked", 0, 0, false, true, true, NULL, false },
728 { "use_debug_exception_return", 0, 0, false, true, true, NULL, false },
729 { NULL, 0, 0, false, false, false, NULL, false }
732 /* A table describing all the processors GCC knows about; see
733 mips-cpus.def for details. */
734 static const struct mips_cpu_info mips_cpu_info_table[] = {
735 #define MIPS_CPU(NAME, CPU, ISA, FLAGS) \
736 { NAME, CPU, ISA, FLAGS },
737 #include "mips-cpus.def"
741 /* Default costs. If these are used for a processor we should look
742 up the actual costs. */
743 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
744 COSTS_N_INSNS (7), /* fp_mult_sf */ \
745 COSTS_N_INSNS (8), /* fp_mult_df */ \
746 COSTS_N_INSNS (23), /* fp_div_sf */ \
747 COSTS_N_INSNS (36), /* fp_div_df */ \
748 COSTS_N_INSNS (10), /* int_mult_si */ \
749 COSTS_N_INSNS (10), /* int_mult_di */ \
750 COSTS_N_INSNS (69), /* int_div_si */ \
751 COSTS_N_INSNS (69), /* int_div_di */ \
752 2, /* branch_cost */ \
753 4 /* memory_latency */
755 /* Floating-point costs for processors without an FPU. Just assume that
756 all floating-point libcalls are very expensive. */
757 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
758 COSTS_N_INSNS (256), /* fp_mult_sf */ \
759 COSTS_N_INSNS (256), /* fp_mult_df */ \
760 COSTS_N_INSNS (256), /* fp_div_sf */ \
761 COSTS_N_INSNS (256) /* fp_div_df */
763 /* Costs to use when optimizing for size. */
764 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size = {
765 COSTS_N_INSNS (1), /* fp_add */
766 COSTS_N_INSNS (1), /* fp_mult_sf */
767 COSTS_N_INSNS (1), /* fp_mult_df */
768 COSTS_N_INSNS (1), /* fp_div_sf */
769 COSTS_N_INSNS (1), /* fp_div_df */
770 COSTS_N_INSNS (1), /* int_mult_si */
771 COSTS_N_INSNS (1), /* int_mult_di */
772 COSTS_N_INSNS (1), /* int_div_si */
773 COSTS_N_INSNS (1), /* int_div_di */
775 4 /* memory_latency */
778 /* Costs to use when optimizing for speed, indexed by processor. */
779 static const struct mips_rtx_cost_data
780 mips_rtx_cost_data[NUM_PROCESSOR_VALUES] = {
782 COSTS_N_INSNS (2), /* fp_add */
783 COSTS_N_INSNS (4), /* fp_mult_sf */
784 COSTS_N_INSNS (5), /* fp_mult_df */
785 COSTS_N_INSNS (12), /* fp_div_sf */
786 COSTS_N_INSNS (19), /* fp_div_df */
787 COSTS_N_INSNS (12), /* int_mult_si */
788 COSTS_N_INSNS (12), /* int_mult_di */
789 COSTS_N_INSNS (35), /* int_div_si */
790 COSTS_N_INSNS (35), /* int_div_di */
792 4 /* memory_latency */
796 COSTS_N_INSNS (6), /* int_mult_si */
797 COSTS_N_INSNS (6), /* int_mult_di */
798 COSTS_N_INSNS (36), /* int_div_si */
799 COSTS_N_INSNS (36), /* int_div_di */
801 4 /* memory_latency */
805 COSTS_N_INSNS (36), /* int_mult_si */
806 COSTS_N_INSNS (36), /* int_mult_di */
807 COSTS_N_INSNS (37), /* int_div_si */
808 COSTS_N_INSNS (37), /* int_div_di */
810 4 /* memory_latency */
814 COSTS_N_INSNS (4), /* int_mult_si */
815 COSTS_N_INSNS (11), /* int_mult_di */
816 COSTS_N_INSNS (36), /* int_div_si */
817 COSTS_N_INSNS (68), /* int_div_di */
819 4 /* memory_latency */
822 COSTS_N_INSNS (4), /* fp_add */
823 COSTS_N_INSNS (4), /* fp_mult_sf */
824 COSTS_N_INSNS (5), /* fp_mult_df */
825 COSTS_N_INSNS (17), /* fp_div_sf */
826 COSTS_N_INSNS (32), /* fp_div_df */
827 COSTS_N_INSNS (4), /* int_mult_si */
828 COSTS_N_INSNS (11), /* int_mult_di */
829 COSTS_N_INSNS (36), /* int_div_si */
830 COSTS_N_INSNS (68), /* int_div_di */
832 4 /* memory_latency */
835 COSTS_N_INSNS (4), /* fp_add */
836 COSTS_N_INSNS (4), /* fp_mult_sf */
837 COSTS_N_INSNS (5), /* fp_mult_df */
838 COSTS_N_INSNS (17), /* fp_div_sf */
839 COSTS_N_INSNS (32), /* fp_div_df */
840 COSTS_N_INSNS (4), /* int_mult_si */
841 COSTS_N_INSNS (7), /* int_mult_di */
842 COSTS_N_INSNS (42), /* int_div_si */
843 COSTS_N_INSNS (72), /* int_div_di */
845 4 /* memory_latency */
849 COSTS_N_INSNS (5), /* int_mult_si */
850 COSTS_N_INSNS (5), /* int_mult_di */
851 COSTS_N_INSNS (41), /* int_div_si */
852 COSTS_N_INSNS (41), /* int_div_di */
854 4 /* memory_latency */
857 COSTS_N_INSNS (8), /* fp_add */
858 COSTS_N_INSNS (8), /* fp_mult_sf */
859 COSTS_N_INSNS (10), /* fp_mult_df */
860 COSTS_N_INSNS (34), /* fp_div_sf */
861 COSTS_N_INSNS (64), /* fp_div_df */
862 COSTS_N_INSNS (5), /* int_mult_si */
863 COSTS_N_INSNS (5), /* int_mult_di */
864 COSTS_N_INSNS (41), /* int_div_si */
865 COSTS_N_INSNS (41), /* int_div_di */
867 4 /* memory_latency */
870 COSTS_N_INSNS (4), /* fp_add */
871 COSTS_N_INSNS (4), /* fp_mult_sf */
872 COSTS_N_INSNS (5), /* fp_mult_df */
873 COSTS_N_INSNS (17), /* fp_div_sf */
874 COSTS_N_INSNS (32), /* fp_div_df */
875 COSTS_N_INSNS (5), /* int_mult_si */
876 COSTS_N_INSNS (5), /* int_mult_di */
877 COSTS_N_INSNS (41), /* int_div_si */
878 COSTS_N_INSNS (41), /* int_div_di */
880 4 /* memory_latency */
884 COSTS_N_INSNS (5), /* int_mult_si */
885 COSTS_N_INSNS (5), /* int_mult_di */
886 COSTS_N_INSNS (41), /* int_div_si */
887 COSTS_N_INSNS (41), /* int_div_di */
889 4 /* memory_latency */
892 COSTS_N_INSNS (8), /* fp_add */
893 COSTS_N_INSNS (8), /* fp_mult_sf */
894 COSTS_N_INSNS (10), /* fp_mult_df */
895 COSTS_N_INSNS (34), /* fp_div_sf */
896 COSTS_N_INSNS (64), /* fp_div_df */
897 COSTS_N_INSNS (5), /* int_mult_si */
898 COSTS_N_INSNS (5), /* int_mult_di */
899 COSTS_N_INSNS (41), /* int_div_si */
900 COSTS_N_INSNS (41), /* int_div_di */
902 4 /* memory_latency */
905 COSTS_N_INSNS (4), /* fp_add */
906 COSTS_N_INSNS (4), /* fp_mult_sf */
907 COSTS_N_INSNS (5), /* fp_mult_df */
908 COSTS_N_INSNS (17), /* fp_div_sf */
909 COSTS_N_INSNS (32), /* fp_div_df */
910 COSTS_N_INSNS (5), /* int_mult_si */
911 COSTS_N_INSNS (5), /* int_mult_di */
912 COSTS_N_INSNS (41), /* int_div_si */
913 COSTS_N_INSNS (41), /* int_div_di */
915 4 /* memory_latency */
918 COSTS_N_INSNS (6), /* fp_add */
919 COSTS_N_INSNS (6), /* fp_mult_sf */
920 COSTS_N_INSNS (7), /* fp_mult_df */
921 COSTS_N_INSNS (25), /* fp_div_sf */
922 COSTS_N_INSNS (48), /* fp_div_df */
923 COSTS_N_INSNS (5), /* int_mult_si */
924 COSTS_N_INSNS (5), /* int_mult_di */
925 COSTS_N_INSNS (41), /* int_div_si */
926 COSTS_N_INSNS (41), /* int_div_di */
928 4 /* memory_latency */
945 COSTS_N_INSNS (5), /* int_mult_si */
946 COSTS_N_INSNS (5), /* int_mult_di */
947 COSTS_N_INSNS (72), /* int_div_si */
948 COSTS_N_INSNS (72), /* int_div_di */
950 4 /* memory_latency */
955 COSTS_N_INSNS (6), /* int_mult_si */
956 COSTS_N_INSNS (6), /* int_mult_di */
957 COSTS_N_INSNS (18), /* int_div_si */
958 COSTS_N_INSNS (35), /* int_div_di */
960 4 /* memory_latency */
963 COSTS_N_INSNS (2), /* fp_add */
964 COSTS_N_INSNS (4), /* fp_mult_sf */
965 COSTS_N_INSNS (5), /* fp_mult_df */
966 COSTS_N_INSNS (12), /* fp_div_sf */
967 COSTS_N_INSNS (19), /* fp_div_df */
968 COSTS_N_INSNS (2), /* int_mult_si */
969 COSTS_N_INSNS (2), /* int_mult_di */
970 COSTS_N_INSNS (35), /* int_div_si */
971 COSTS_N_INSNS (35), /* int_div_di */
973 4 /* memory_latency */
976 COSTS_N_INSNS (3), /* fp_add */
977 COSTS_N_INSNS (5), /* fp_mult_sf */
978 COSTS_N_INSNS (6), /* fp_mult_df */
979 COSTS_N_INSNS (15), /* fp_div_sf */
980 COSTS_N_INSNS (16), /* fp_div_df */
981 COSTS_N_INSNS (17), /* int_mult_si */
982 COSTS_N_INSNS (17), /* int_mult_di */
983 COSTS_N_INSNS (38), /* int_div_si */
984 COSTS_N_INSNS (38), /* int_div_di */
986 6 /* memory_latency */
989 COSTS_N_INSNS (6), /* fp_add */
990 COSTS_N_INSNS (7), /* fp_mult_sf */
991 COSTS_N_INSNS (8), /* fp_mult_df */
992 COSTS_N_INSNS (23), /* fp_div_sf */
993 COSTS_N_INSNS (36), /* fp_div_df */
994 COSTS_N_INSNS (10), /* int_mult_si */
995 COSTS_N_INSNS (10), /* int_mult_di */
996 COSTS_N_INSNS (69), /* int_div_si */
997 COSTS_N_INSNS (69), /* int_div_di */
999 6 /* memory_latency */
1011 /* The only costs that appear to be updated here are
1012 integer multiplication. */
1014 COSTS_N_INSNS (4), /* int_mult_si */
1015 COSTS_N_INSNS (6), /* int_mult_di */
1016 COSTS_N_INSNS (69), /* int_div_si */
1017 COSTS_N_INSNS (69), /* int_div_di */
1018 1, /* branch_cost */
1019 4 /* memory_latency */
1034 COSTS_N_INSNS (6), /* fp_add */
1035 COSTS_N_INSNS (4), /* fp_mult_sf */
1036 COSTS_N_INSNS (5), /* fp_mult_df */
1037 COSTS_N_INSNS (23), /* fp_div_sf */
1038 COSTS_N_INSNS (36), /* fp_div_df */
1039 COSTS_N_INSNS (5), /* int_mult_si */
1040 COSTS_N_INSNS (5), /* int_mult_di */
1041 COSTS_N_INSNS (36), /* int_div_si */
1042 COSTS_N_INSNS (36), /* int_div_di */
1043 1, /* branch_cost */
1044 4 /* memory_latency */
1047 COSTS_N_INSNS (6), /* fp_add */
1048 COSTS_N_INSNS (5), /* fp_mult_sf */
1049 COSTS_N_INSNS (6), /* fp_mult_df */
1050 COSTS_N_INSNS (30), /* fp_div_sf */
1051 COSTS_N_INSNS (59), /* fp_div_df */
1052 COSTS_N_INSNS (3), /* int_mult_si */
1053 COSTS_N_INSNS (4), /* int_mult_di */
1054 COSTS_N_INSNS (42), /* int_div_si */
1055 COSTS_N_INSNS (74), /* int_div_di */
1056 1, /* branch_cost */
1057 4 /* memory_latency */
1060 COSTS_N_INSNS (6), /* fp_add */
1061 COSTS_N_INSNS (5), /* fp_mult_sf */
1062 COSTS_N_INSNS (6), /* fp_mult_df */
1063 COSTS_N_INSNS (30), /* fp_div_sf */
1064 COSTS_N_INSNS (59), /* fp_div_df */
1065 COSTS_N_INSNS (5), /* int_mult_si */
1066 COSTS_N_INSNS (9), /* int_mult_di */
1067 COSTS_N_INSNS (42), /* int_div_si */
1068 COSTS_N_INSNS (74), /* int_div_di */
1069 1, /* branch_cost */
1070 4 /* memory_latency */
1073 COSTS_N_INSNS (4), /* fp_add */
1074 COSTS_N_INSNS (4), /* fp_mult_sf */
1075 COSTS_N_INSNS (256), /* fp_mult_df */
1076 COSTS_N_INSNS (8), /* fp_div_sf */
1077 COSTS_N_INSNS (256), /* fp_div_df */
1078 COSTS_N_INSNS (4), /* int_mult_si */
1079 COSTS_N_INSNS (256), /* int_mult_di */
1080 COSTS_N_INSNS (37), /* int_div_si */
1081 COSTS_N_INSNS (256), /* int_div_di */
1082 1, /* branch_cost */
1083 4 /* memory_latency */
1086 /* The only costs that are changed here are
1087 integer multiplication. */
1088 COSTS_N_INSNS (6), /* fp_add */
1089 COSTS_N_INSNS (7), /* fp_mult_sf */
1090 COSTS_N_INSNS (8), /* fp_mult_df */
1091 COSTS_N_INSNS (23), /* fp_div_sf */
1092 COSTS_N_INSNS (36), /* fp_div_df */
1093 COSTS_N_INSNS (5), /* int_mult_si */
1094 COSTS_N_INSNS (9), /* int_mult_di */
1095 COSTS_N_INSNS (69), /* int_div_si */
1096 COSTS_N_INSNS (69), /* int_div_di */
1097 1, /* branch_cost */
1098 4 /* memory_latency */
1104 /* The only costs that are changed here are
1105 integer multiplication. */
1106 COSTS_N_INSNS (6), /* fp_add */
1107 COSTS_N_INSNS (7), /* fp_mult_sf */
1108 COSTS_N_INSNS (8), /* fp_mult_df */
1109 COSTS_N_INSNS (23), /* fp_div_sf */
1110 COSTS_N_INSNS (36), /* fp_div_df */
1111 COSTS_N_INSNS (3), /* int_mult_si */
1112 COSTS_N_INSNS (8), /* int_mult_di */
1113 COSTS_N_INSNS (69), /* int_div_si */
1114 COSTS_N_INSNS (69), /* int_div_di */
1115 1, /* branch_cost */
1116 4 /* memory_latency */
1119 COSTS_N_INSNS (2), /* fp_add */
1120 COSTS_N_INSNS (2), /* fp_mult_sf */
1121 COSTS_N_INSNS (2), /* fp_mult_df */
1122 COSTS_N_INSNS (12), /* fp_div_sf */
1123 COSTS_N_INSNS (19), /* fp_div_df */
1124 COSTS_N_INSNS (5), /* int_mult_si */
1125 COSTS_N_INSNS (9), /* int_mult_di */
1126 COSTS_N_INSNS (34), /* int_div_si */
1127 COSTS_N_INSNS (66), /* int_div_di */
1128 1, /* branch_cost */
1129 4 /* memory_latency */
1132 /* These costs are the same as the SB-1A below. */
1133 COSTS_N_INSNS (4), /* fp_add */
1134 COSTS_N_INSNS (4), /* fp_mult_sf */
1135 COSTS_N_INSNS (4), /* fp_mult_df */
1136 COSTS_N_INSNS (24), /* fp_div_sf */
1137 COSTS_N_INSNS (32), /* fp_div_df */
1138 COSTS_N_INSNS (3), /* int_mult_si */
1139 COSTS_N_INSNS (4), /* int_mult_di */
1140 COSTS_N_INSNS (36), /* int_div_si */
1141 COSTS_N_INSNS (68), /* int_div_di */
1142 1, /* branch_cost */
1143 4 /* memory_latency */
1146 /* These costs are the same as the SB-1 above. */
1147 COSTS_N_INSNS (4), /* fp_add */
1148 COSTS_N_INSNS (4), /* fp_mult_sf */
1149 COSTS_N_INSNS (4), /* fp_mult_df */
1150 COSTS_N_INSNS (24), /* fp_div_sf */
1151 COSTS_N_INSNS (32), /* fp_div_df */
1152 COSTS_N_INSNS (3), /* int_mult_si */
1153 COSTS_N_INSNS (4), /* int_mult_di */
1154 COSTS_N_INSNS (36), /* int_div_si */
1155 COSTS_N_INSNS (68), /* int_div_di */
1156 1, /* branch_cost */
1157 4 /* memory_latency */
1164 COSTS_N_INSNS (8), /* int_mult_si */
1165 COSTS_N_INSNS (8), /* int_mult_di */
1166 COSTS_N_INSNS (72), /* int_div_si */
1167 COSTS_N_INSNS (72), /* int_div_di */
1168 1, /* branch_cost */
1169 4 /* memory_latency */
1172 /* These costs are the same as 5KF above. */
1173 COSTS_N_INSNS (4), /* fp_add */
1174 COSTS_N_INSNS (4), /* fp_mult_sf */
1175 COSTS_N_INSNS (5), /* fp_mult_df */
1176 COSTS_N_INSNS (17), /* fp_div_sf */
1177 COSTS_N_INSNS (32), /* fp_div_df */
1178 COSTS_N_INSNS (4), /* int_mult_si */
1179 COSTS_N_INSNS (11), /* int_mult_di */
1180 COSTS_N_INSNS (36), /* int_div_si */
1181 COSTS_N_INSNS (68), /* int_div_di */
1182 1, /* branch_cost */
1183 4 /* memory_latency */
1186 COSTS_N_INSNS (4), /* fp_add */
1187 COSTS_N_INSNS (5), /* fp_mult_sf */
1188 COSTS_N_INSNS (5), /* fp_mult_df */
1189 COSTS_N_INSNS (17), /* fp_div_sf */
1190 COSTS_N_INSNS (17), /* fp_div_df */
1191 COSTS_N_INSNS (5), /* int_mult_si */
1192 COSTS_N_INSNS (5), /* int_mult_di */
1193 COSTS_N_INSNS (8), /* int_div_si */
1194 COSTS_N_INSNS (8), /* int_div_di */
1195 2, /* branch_cost */
1196 10 /* memory_latency */
1200 static rtx mips_find_pic_call_symbol (rtx_insn *, rtx, bool);
1201 static int mips_register_move_cost (enum machine_mode, reg_class_t,
1203 static unsigned int mips_function_arg_boundary (enum machine_mode, const_tree);
1205 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1206 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1207 struct GTY (()) mflip_mips16_entry {
1211 static GTY ((param_is (struct mflip_mips16_entry))) htab_t mflip_mips16_htab;
1213 /* Hash table callbacks for mflip_mips16_htab. */
1216 mflip_mips16_htab_hash (const void *entry)
1218 return htab_hash_string (((const struct mflip_mips16_entry *) entry)->name);
1222 mflip_mips16_htab_eq (const void *entry, const void *name)
1224 return strcmp (((const struct mflip_mips16_entry *) entry)->name,
1225 (const char *) name) == 0;
1228 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1229 mode, false if it should next add an attribute for the opposite mode. */
1230 static GTY(()) bool mips16_flipper;
1232 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1233 for -mflip-mips16. Return true if it should use "mips16" and false if
1234 it should use "nomips16". */
1237 mflip_mips16_use_mips16_p (tree decl)
1239 struct mflip_mips16_entry *entry;
1243 bool base_is_mips16 = (mips_base_compression_flags & MASK_MIPS16) != 0;
1245 /* Use the opposite of the command-line setting for anonymous decls. */
1246 if (!DECL_NAME (decl))
1247 return !base_is_mips16;
1249 if (!mflip_mips16_htab)
1250 mflip_mips16_htab = htab_create_ggc (37, mflip_mips16_htab_hash,
1251 mflip_mips16_htab_eq, NULL);
1253 name = IDENTIFIER_POINTER (DECL_NAME (decl));
1254 hash = htab_hash_string (name);
1255 slot = htab_find_slot_with_hash (mflip_mips16_htab, name, hash, INSERT);
1256 entry = (struct mflip_mips16_entry *) *slot;
1259 mips16_flipper = !mips16_flipper;
1260 entry = ggc_alloc<mflip_mips16_entry> ();
1262 entry->mips16_p = mips16_flipper ? !base_is_mips16 : base_is_mips16;
1265 return entry->mips16_p;
1268 /* Predicates to test for presence of "near" and "far"/"long_call"
1269 attributes on the given TYPE. */
1272 mips_near_type_p (const_tree type)
1274 return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL;
1278 mips_far_type_p (const_tree type)
1280 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL
1281 || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL);
1285 /* Check if the interrupt attribute is set for a function. */
1288 mips_interrupt_type_p (tree type)
1290 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type)) != NULL;
1293 /* Check if the attribute to use shadow register set is set for a function. */
1296 mips_use_shadow_register_set_p (tree type)
1298 return lookup_attribute ("use_shadow_register_set",
1299 TYPE_ATTRIBUTES (type)) != NULL;
1302 /* Check if the attribute to keep interrupts masked is set for a function. */
1305 mips_keep_interrupts_masked_p (tree type)
1307 return lookup_attribute ("keep_interrupts_masked",
1308 TYPE_ATTRIBUTES (type)) != NULL;
1311 /* Check if the attribute to use debug exception return is set for
1315 mips_use_debug_exception_return_p (tree type)
1317 return lookup_attribute ("use_debug_exception_return",
1318 TYPE_ATTRIBUTES (type)) != NULL;
1321 /* Return the set of compression modes that are explicitly required
1322 by the attributes in ATTRIBUTES. */
1325 mips_get_compress_on_flags (tree attributes)
1327 unsigned int flags = 0;
1329 if (lookup_attribute ("mips16", attributes) != NULL)
1330 flags |= MASK_MIPS16;
1332 if (lookup_attribute ("micromips", attributes) != NULL)
1333 flags |= MASK_MICROMIPS;
1338 /* Return the set of compression modes that are explicitly forbidden
1339 by the attributes in ATTRIBUTES. */
1342 mips_get_compress_off_flags (tree attributes)
1344 unsigned int flags = 0;
1346 if (lookup_attribute ("nocompression", attributes) != NULL)
1347 flags |= MASK_MIPS16 | MASK_MICROMIPS;
1349 if (lookup_attribute ("nomips16", attributes) != NULL)
1350 flags |= MASK_MIPS16;
1352 if (lookup_attribute ("nomicromips", attributes) != NULL)
1353 flags |= MASK_MICROMIPS;
1358 /* Return the compression mode that should be used for function DECL.
1359 Return the ambient setting if DECL is null. */
1362 mips_get_compress_mode (tree decl)
1364 unsigned int flags, force_on;
1366 flags = mips_base_compression_flags;
1369 /* Nested functions must use the same frame pointer as their
1370 parent and must therefore use the same ISA mode. */
1371 tree parent = decl_function_context (decl);
1374 force_on = mips_get_compress_on_flags (DECL_ATTRIBUTES (decl));
1377 flags &= ~mips_get_compress_off_flags (DECL_ATTRIBUTES (decl));
1382 /* Return the attribute name associated with MASK_MIPS16 and MASK_MICROMIPS
1386 mips_get_compress_on_name (unsigned int flags)
1388 if (flags == MASK_MIPS16)
1393 /* Return the attribute name that forbids MASK_MIPS16 and MASK_MICROMIPS
1397 mips_get_compress_off_name (unsigned int flags)
1399 if (flags == MASK_MIPS16)
1401 if (flags == MASK_MICROMIPS)
1402 return "nomicromips";
1403 return "nocompression";
1406 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1409 mips_comp_type_attributes (const_tree type1, const_tree type2)
1411 /* Disallow mixed near/far attributes. */
1412 if (mips_far_type_p (type1) && mips_near_type_p (type2))
1414 if (mips_near_type_p (type1) && mips_far_type_p (type2))
1419 /* Implement TARGET_INSERT_ATTRIBUTES. */
1422 mips_insert_attributes (tree decl, tree *attributes)
1425 unsigned int compression_flags, nocompression_flags;
1427 /* Check for "mips16" and "nomips16" attributes. */
1428 compression_flags = mips_get_compress_on_flags (*attributes);
1429 nocompression_flags = mips_get_compress_off_flags (*attributes);
1431 if (TREE_CODE (decl) != FUNCTION_DECL)
1433 if (nocompression_flags)
1434 error ("%qs attribute only applies to functions",
1435 mips_get_compress_off_name (nocompression_flags));
1437 if (compression_flags)
1438 error ("%qs attribute only applies to functions",
1439 mips_get_compress_on_name (nocompression_flags));
1443 compression_flags |= mips_get_compress_on_flags (DECL_ATTRIBUTES (decl));
1444 nocompression_flags |=
1445 mips_get_compress_off_flags (DECL_ATTRIBUTES (decl));
1447 if (compression_flags && nocompression_flags)
1448 error ("%qE cannot have both %qs and %qs attributes",
1449 DECL_NAME (decl), mips_get_compress_on_name (compression_flags),
1450 mips_get_compress_off_name (nocompression_flags));
1452 if (compression_flags & MASK_MIPS16
1453 && compression_flags & MASK_MICROMIPS)
1454 error ("%qE cannot have both %qs and %qs attributes",
1455 DECL_NAME (decl), "mips16", "micromips");
1457 if (TARGET_FLIP_MIPS16
1458 && !DECL_ARTIFICIAL (decl)
1459 && compression_flags == 0
1460 && nocompression_flags == 0)
1462 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1463 "mips16" attribute, arbitrarily pick one. We must pick the same
1464 setting for duplicate declarations of a function. */
1465 name = mflip_mips16_use_mips16_p (decl) ? "mips16" : "nomips16";
1466 *attributes = tree_cons (get_identifier (name), NULL, *attributes);
1467 name = "nomicromips";
1468 *attributes = tree_cons (get_identifier (name), NULL, *attributes);
1473 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1476 mips_merge_decl_attributes (tree olddecl, tree newdecl)
1480 diff = (mips_get_compress_on_flags (DECL_ATTRIBUTES (olddecl))
1481 ^ mips_get_compress_on_flags (DECL_ATTRIBUTES (newdecl)));
1483 error ("%qE redeclared with conflicting %qs attributes",
1484 DECL_NAME (newdecl), mips_get_compress_on_name (diff));
1486 diff = (mips_get_compress_off_flags (DECL_ATTRIBUTES (olddecl))
1487 ^ mips_get_compress_off_flags (DECL_ATTRIBUTES (newdecl)));
1489 error ("%qE redeclared with conflicting %qs attributes",
1490 DECL_NAME (newdecl), mips_get_compress_off_name (diff));
1492 return merge_attributes (DECL_ATTRIBUTES (olddecl),
1493 DECL_ATTRIBUTES (newdecl));
1496 /* Implement TARGET_CAN_INLINE_P. */
1499 mips_can_inline_p (tree caller, tree callee)
1501 if (mips_get_compress_mode (callee) != mips_get_compress_mode (caller))
1503 return default_target_can_inline_p (caller, callee);
1506 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1507 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1510 mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr)
1512 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
1514 *base_ptr = XEXP (x, 0);
1515 *offset_ptr = INTVAL (XEXP (x, 1));
1524 static unsigned int mips_build_integer (struct mips_integer_op *,
1525 unsigned HOST_WIDE_INT);
1527 /* A subroutine of mips_build_integer, with the same interface.
1528 Assume that the final action in the sequence should be a left shift. */
1531 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1533 unsigned int i, shift;
1535 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1536 since signed numbers are easier to load than unsigned ones. */
1538 while ((value & 1) == 0)
1539 value /= 2, shift++;
1541 i = mips_build_integer (codes, value);
1542 codes[i].code = ASHIFT;
1543 codes[i].value = shift;
1547 /* As for mips_build_shift, but assume that the final action will be
1548 an IOR or PLUS operation. */
1551 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1553 unsigned HOST_WIDE_INT high;
1556 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1557 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
1559 /* The constant is too complex to load with a simple LUI/ORI pair,
1560 so we want to give the recursive call as many trailing zeros as
1561 possible. In this case, we know bit 16 is set and that the
1562 low 16 bits form a negative number. If we subtract that number
1563 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1564 i = mips_build_integer (codes, CONST_HIGH_PART (value));
1565 codes[i].code = PLUS;
1566 codes[i].value = CONST_LOW_PART (value);
1570 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1571 bits gives a value with at least 17 trailing zeros. */
1572 i = mips_build_integer (codes, high);
1573 codes[i].code = IOR;
1574 codes[i].value = value & 0xffff;
1579 /* Fill CODES with a sequence of rtl operations to load VALUE.
1580 Return the number of operations needed. */
1583 mips_build_integer (struct mips_integer_op *codes,
1584 unsigned HOST_WIDE_INT value)
1586 if (SMALL_OPERAND (value)
1587 || SMALL_OPERAND_UNSIGNED (value)
1588 || LUI_OPERAND (value))
1590 /* The value can be loaded with a single instruction. */
1591 codes[0].code = UNKNOWN;
1592 codes[0].value = value;
1595 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
1597 /* Either the constant is a simple LUI/ORI combination or its
1598 lowest bit is set. We don't want to shift in this case. */
1599 return mips_build_lower (codes, value);
1601 else if ((value & 0xffff) == 0)
1603 /* The constant will need at least three actions. The lowest
1604 16 bits are clear, so the final action will be a shift. */
1605 return mips_build_shift (codes, value);
1609 /* The final action could be a shift, add or inclusive OR.
1610 Rather than use a complex condition to select the best
1611 approach, try both mips_build_shift and mips_build_lower
1612 and pick the one that gives the shortest sequence.
1613 Note that this case is only used once per constant. */
1614 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1615 unsigned int cost, alt_cost;
1617 cost = mips_build_shift (codes, value);
1618 alt_cost = mips_build_lower (alt_codes, value);
1619 if (alt_cost < cost)
1621 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
1628 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
1631 mips_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
1633 return mips_const_insns (x) > 0;
1636 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
1639 mips16_stub_function (const char *name)
1643 x = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
1644 SYMBOL_REF_FLAGS (x) |= (SYMBOL_FLAG_EXTERNAL | SYMBOL_FLAG_FUNCTION);
1648 /* Return a legitimate call address for STUB, given that STUB is a MIPS16
1649 support function. */
1652 mips16_stub_call_address (mips_one_only_stub *stub)
1654 rtx fn = mips16_stub_function (stub->get_name ());
1655 SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_LOCAL;
1656 if (!call_insn_operand (fn, VOIDmode))
1657 fn = force_reg (Pmode, fn);
1661 /* A stub for moving the thread pointer into TLS_GET_TP_REGNUM. */
1663 class mips16_rdhwr_one_only_stub : public mips_one_only_stub
1665 virtual const char *get_name ();
1666 virtual void output_body ();
1670 mips16_rdhwr_one_only_stub::get_name ()
1672 return "__mips16_rdhwr";
1676 mips16_rdhwr_one_only_stub::output_body ()
1678 fprintf (asm_out_file,
1680 "\t.set\tmips32r2\n"
1681 "\t.set\tnoreorder\n"
1687 /* A stub for moving the FCSR into GET_FCSR_REGNUM. */
1688 class mips16_get_fcsr_one_only_stub : public mips_one_only_stub
1690 virtual const char *get_name ();
1691 virtual void output_body ();
1695 mips16_get_fcsr_one_only_stub::get_name ()
1697 return "__mips16_get_fcsr";
1701 mips16_get_fcsr_one_only_stub::output_body ()
1703 fprintf (asm_out_file,
1705 "\tj\t$31\n", reg_names[GET_FCSR_REGNUM]);
1708 /* A stub for moving SET_FCSR_REGNUM into the FCSR. */
1709 class mips16_set_fcsr_one_only_stub : public mips_one_only_stub
1711 virtual const char *get_name ();
1712 virtual void output_body ();
1716 mips16_set_fcsr_one_only_stub::get_name ()
1718 return "__mips16_set_fcsr";
1722 mips16_set_fcsr_one_only_stub::output_body ()
1724 fprintf (asm_out_file,
1726 "\tj\t$31\n", reg_names[SET_FCSR_REGNUM]);
1729 /* Return true if symbols of type TYPE require a GOT access. */
1732 mips_got_symbol_type_p (enum mips_symbol_type type)
1736 case SYMBOL_GOT_PAGE_OFST:
1737 case SYMBOL_GOT_DISP:
1745 /* Return true if X is a thread-local symbol. */
1748 mips_tls_symbol_p (rtx x)
1750 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1753 /* Return true if SYMBOL_REF X is associated with a global symbol
1754 (in the STB_GLOBAL sense). */
1757 mips_global_symbol_p (const_rtx x)
1759 const_tree decl = SYMBOL_REF_DECL (x);
1762 return !SYMBOL_REF_LOCAL_P (x) || SYMBOL_REF_EXTERNAL_P (x);
1764 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1765 or weak symbols. Relocations in the object file will be against
1766 the target symbol, so it's that symbol's binding that matters here. */
1767 return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl));
1770 /* Return true if function X is a libgcc MIPS16 stub function. */
1773 mips16_stub_function_p (const_rtx x)
1775 return (GET_CODE (x) == SYMBOL_REF
1776 && strncmp (XSTR (x, 0), "__mips16_", 9) == 0);
1779 /* Return true if function X is a locally-defined and locally-binding
1783 mips16_local_function_p (const_rtx x)
1785 return (GET_CODE (x) == SYMBOL_REF
1786 && SYMBOL_REF_LOCAL_P (x)
1787 && !SYMBOL_REF_EXTERNAL_P (x)
1788 && (mips_get_compress_mode (SYMBOL_REF_DECL (x)) & MASK_MIPS16));
1791 /* Return true if SYMBOL_REF X binds locally. */
1794 mips_symbol_binds_local_p (const_rtx x)
1796 return (SYMBOL_REF_DECL (x)
1797 ? targetm.binds_local_p (SYMBOL_REF_DECL (x))
1798 : SYMBOL_REF_LOCAL_P (x));
1801 /* Return true if rtx constants of mode MODE should be put into a small
1805 mips_rtx_constant_in_small_data_p (enum machine_mode mode)
1807 return (!TARGET_EMBEDDED_DATA
1808 && TARGET_LOCAL_SDATA
1809 && GET_MODE_SIZE (mode) <= mips_small_data_threshold);
1812 /* Return true if X should not be moved directly into register $25.
1813 We need this because many versions of GAS will treat "la $25,foo" as
1814 part of a call sequence and so allow a global "foo" to be lazily bound. */
1817 mips_dangerous_for_la25_p (rtx x)
1819 return (!TARGET_EXPLICIT_RELOCS
1821 && GET_CODE (x) == SYMBOL_REF
1822 && mips_global_symbol_p (x));
1825 /* Return true if calls to X might need $25 to be valid on entry. */
1828 mips_use_pic_fn_addr_reg_p (const_rtx x)
1830 if (!TARGET_USE_PIC_FN_ADDR_REG)
1833 /* MIPS16 stub functions are guaranteed not to use $25. */
1834 if (mips16_stub_function_p (x))
1837 if (GET_CODE (x) == SYMBOL_REF)
1839 /* If PLTs and copy relocations are available, the static linker
1840 will make sure that $25 is valid on entry to the target function. */
1841 if (TARGET_ABICALLS_PIC0)
1844 /* Locally-defined functions use absolute accesses to set up
1845 the global pointer. */
1846 if (TARGET_ABSOLUTE_ABICALLS
1847 && mips_symbol_binds_local_p (x)
1848 && !SYMBOL_REF_EXTERNAL_P (x))
1855 /* Return the method that should be used to access SYMBOL_REF or
1856 LABEL_REF X in context CONTEXT. */
1858 static enum mips_symbol_type
1859 mips_classify_symbol (const_rtx x, enum mips_symbol_context context)
1862 return SYMBOL_GOT_DISP;
1864 if (GET_CODE (x) == LABEL_REF)
1866 /* Only return SYMBOL_PC_RELATIVE if we are generating MIPS16
1867 code and if we know that the label is in the current function's
1868 text section. LABEL_REFs are used for jump tables as well as
1869 text labels, so we must check whether jump tables live in the
1871 if (TARGET_MIPS16_SHORT_JUMP_TABLES
1872 && !LABEL_REF_NONLOCAL_P (x))
1873 return SYMBOL_PC_RELATIVE;
1875 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1876 return SYMBOL_GOT_PAGE_OFST;
1878 return SYMBOL_ABSOLUTE;
1881 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1883 if (SYMBOL_REF_TLS_MODEL (x))
1886 if (CONSTANT_POOL_ADDRESS_P (x))
1888 if (TARGET_MIPS16_TEXT_LOADS)
1889 return SYMBOL_PC_RELATIVE;
1891 if (TARGET_MIPS16_PCREL_LOADS && context == SYMBOL_CONTEXT_MEM)
1892 return SYMBOL_PC_RELATIVE;
1894 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x)))
1895 return SYMBOL_GP_RELATIVE;
1898 /* Do not use small-data accesses for weak symbols; they may end up
1900 if (TARGET_GPOPT && SYMBOL_REF_SMALL_P (x) && !SYMBOL_REF_WEAK (x))
1901 return SYMBOL_GP_RELATIVE;
1903 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1905 if (TARGET_ABICALLS_PIC2
1906 && !(TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x)))
1908 /* There are three cases to consider:
1910 - o32 PIC (either with or without explicit relocs)
1911 - n32/n64 PIC without explicit relocs
1912 - n32/n64 PIC with explicit relocs
1914 In the first case, both local and global accesses will use an
1915 R_MIPS_GOT16 relocation. We must correctly predict which of
1916 the two semantics (local or global) the assembler and linker
1917 will apply. The choice depends on the symbol's binding rather
1918 than its visibility.
1920 In the second case, the assembler will not use R_MIPS_GOT16
1921 relocations, but it chooses between local and global accesses
1922 in the same way as for o32 PIC.
1924 In the third case we have more freedom since both forms of
1925 access will work for any kind of symbol. However, there seems
1926 little point in doing things differently. */
1927 if (mips_global_symbol_p (x))
1928 return SYMBOL_GOT_DISP;
1930 return SYMBOL_GOT_PAGE_OFST;
1933 return SYMBOL_ABSOLUTE;
1936 /* Classify the base of symbolic expression X, given that X appears in
1939 static enum mips_symbol_type
1940 mips_classify_symbolic_expression (rtx x, enum mips_symbol_context context)
1944 split_const (x, &x, &offset);
1945 if (UNSPEC_ADDRESS_P (x))
1946 return UNSPEC_ADDRESS_TYPE (x);
1948 return mips_classify_symbol (x, context);
1951 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1952 is the alignment in bytes of SYMBOL_REF X. */
1955 mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset)
1957 HOST_WIDE_INT align;
1959 align = SYMBOL_REF_DECL (x) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x)) : 1;
1960 return IN_RANGE (offset, 0, align - 1);
1963 /* Return true if X is a symbolic constant that can be used in context
1964 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1967 mips_symbolic_constant_p (rtx x, enum mips_symbol_context context,
1968 enum mips_symbol_type *symbol_type)
1972 split_const (x, &x, &offset);
1973 if (UNSPEC_ADDRESS_P (x))
1975 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1976 x = UNSPEC_ADDRESS (x);
1978 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1980 *symbol_type = mips_classify_symbol (x, context);
1981 if (*symbol_type == SYMBOL_TLS)
1987 if (offset == const0_rtx)
1990 /* Check whether a nonzero offset is valid for the underlying
1992 switch (*symbol_type)
1994 case SYMBOL_ABSOLUTE:
1995 case SYMBOL_64_HIGH:
1998 /* If the target has 64-bit pointers and the object file only
1999 supports 32-bit symbols, the values of those symbols will be
2000 sign-extended. In this case we can't allow an arbitrary offset
2001 in case the 32-bit value X + OFFSET has a different sign from X. */
2002 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
2003 return offset_within_block_p (x, INTVAL (offset));
2005 /* In other cases the relocations can handle any offset. */
2008 case SYMBOL_PC_RELATIVE:
2009 /* Allow constant pool references to be converted to LABEL+CONSTANT.
2010 In this case, we no longer have access to the underlying constant,
2011 but the original symbol-based access was known to be valid. */
2012 if (GET_CODE (x) == LABEL_REF)
2017 case SYMBOL_GP_RELATIVE:
2018 /* Make sure that the offset refers to something within the
2019 same object block. This should guarantee that the final
2020 PC- or GP-relative offset is within the 16-bit limit. */
2021 return offset_within_block_p (x, INTVAL (offset));
2023 case SYMBOL_GOT_PAGE_OFST:
2024 case SYMBOL_GOTOFF_PAGE:
2025 /* If the symbol is global, the GOT entry will contain the symbol's
2026 address, and we will apply a 16-bit offset after loading it.
2027 If the symbol is local, the linker should provide enough local
2028 GOT entries for a 16-bit offset, but larger offsets may lead
2030 return SMALL_INT (offset);
2034 /* There is no carry between the HI and LO REL relocations, so the
2035 offset is only valid if we know it won't lead to such a carry. */
2036 return mips_offset_within_alignment_p (x, INTVAL (offset));
2038 case SYMBOL_GOT_DISP:
2039 case SYMBOL_GOTOFF_DISP:
2040 case SYMBOL_GOTOFF_CALL:
2041 case SYMBOL_GOTOFF_LOADGP:
2044 case SYMBOL_GOTTPREL:
2052 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
2053 single instruction. We rely on the fact that, in the worst case,
2054 all instructions involved in a MIPS16 address calculation are usually
2058 mips_symbol_insns_1 (enum mips_symbol_type type, enum machine_mode mode)
2060 if (mips_use_pcrel_pool_p[(int) type])
2062 if (mode == MAX_MACHINE_MODE)
2063 /* LEAs will be converted into constant-pool references by
2065 type = SYMBOL_PC_RELATIVE;
2067 /* The constant must be loaded and then dereferenced. */
2073 case SYMBOL_ABSOLUTE:
2074 /* When using 64-bit symbols, we need 5 preparatory instructions,
2077 lui $at,%highest(symbol)
2078 daddiu $at,$at,%higher(symbol)
2080 daddiu $at,$at,%hi(symbol)
2083 The final address is then $at + %lo(symbol). With 32-bit
2084 symbols we just need a preparatory LUI for normal mode and
2085 a preparatory LI and SLL for MIPS16. */
2086 return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2;
2088 case SYMBOL_GP_RELATIVE:
2089 /* Treat GP-relative accesses as taking a single instruction on
2090 MIPS16 too; the copy of $gp can often be shared. */
2093 case SYMBOL_PC_RELATIVE:
2094 /* PC-relative constants can be only be used with ADDIUPC,
2095 DADDIUPC, LWPC and LDPC. */
2096 if (mode == MAX_MACHINE_MODE
2097 || GET_MODE_SIZE (mode) == 4
2098 || GET_MODE_SIZE (mode) == 8)
2101 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
2104 case SYMBOL_GOT_DISP:
2105 /* The constant will have to be loaded from the GOT before it
2106 is used in an address. */
2107 if (mode != MAX_MACHINE_MODE)
2112 case SYMBOL_GOT_PAGE_OFST:
2113 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
2114 local/global classification is accurate. The worst cases are:
2116 (1) For local symbols when generating o32 or o64 code. The assembler
2122 ...and the final address will be $at + %lo(symbol).
2124 (2) For global symbols when -mxgot. The assembler will use:
2126 lui $at,%got_hi(symbol)
2129 ...and the final address will be $at + %got_lo(symbol). */
2132 case SYMBOL_GOTOFF_PAGE:
2133 case SYMBOL_GOTOFF_DISP:
2134 case SYMBOL_GOTOFF_CALL:
2135 case SYMBOL_GOTOFF_LOADGP:
2136 case SYMBOL_64_HIGH:
2142 case SYMBOL_GOTTPREL:
2145 /* A 16-bit constant formed by a single relocation, or a 32-bit
2146 constant formed from a high 16-bit relocation and a low 16-bit
2147 relocation. Use mips_split_p to determine which. 32-bit
2148 constants need an "lui; addiu" sequence for normal mode and
2149 an "li; sll; addiu" sequence for MIPS16 mode. */
2150 return !mips_split_p[type] ? 1 : TARGET_MIPS16 ? 3 : 2;
2153 /* We don't treat a bare TLS symbol as a constant. */
2159 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
2160 to load symbols of type TYPE into a register. Return 0 if the given
2161 type of symbol cannot be used as an immediate operand.
2163 Otherwise, return the number of instructions needed to load or store
2164 values of mode MODE to or from addresses of type TYPE. Return 0 if
2165 the given type of symbol is not valid in addresses.
2167 In both cases, instruction counts are based off BASE_INSN_LENGTH. */
2170 mips_symbol_insns (enum mips_symbol_type type, enum machine_mode mode)
2172 return mips_symbol_insns_1 (type, mode) * (TARGET_MIPS16 ? 2 : 1);
2175 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
2178 mips_cannot_force_const_mem (enum machine_mode mode, rtx x)
2180 enum mips_symbol_type type;
2183 /* There is no assembler syntax for expressing an address-sized
2185 if (GET_CODE (x) == HIGH)
2188 /* As an optimization, reject constants that mips_legitimize_move
2191 Suppose we have a multi-instruction sequence that loads constant C
2192 into register R. If R does not get allocated a hard register, and
2193 R is used in an operand that allows both registers and memory
2194 references, reload will consider forcing C into memory and using
2195 one of the instruction's memory alternatives. Returning false
2196 here will force it to use an input reload instead. */
2197 if (CONST_INT_P (x) && mips_legitimate_constant_p (mode, x))
2200 split_const (x, &base, &offset);
2201 if (mips_symbolic_constant_p (base, SYMBOL_CONTEXT_LEA, &type))
2203 /* See whether we explicitly want these symbols in the pool. */
2204 if (mips_use_pcrel_pool_p[(int) type])
2207 /* The same optimization as for CONST_INT. */
2208 if (SMALL_INT (offset) && mips_symbol_insns (type, MAX_MACHINE_MODE) > 0)
2211 /* If MIPS16 constant pools live in the text section, they should
2212 not refer to anything that might need run-time relocation. */
2213 if (TARGET_MIPS16_PCREL_LOADS && mips_got_symbol_type_p (type))
2217 /* TLS symbols must be computed by mips_legitimize_move. */
2218 if (tls_referenced_p (x))
2224 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
2225 constants when we're using a per-function constant pool. */
2228 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
2229 const_rtx x ATTRIBUTE_UNUSED)
2231 return !TARGET_MIPS16_PCREL_LOADS;
2234 /* Return true if register REGNO is a valid base register for mode MODE.
2235 STRICT_P is true if REG_OK_STRICT is in effect. */
2238 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode,
2241 if (!HARD_REGISTER_NUM_P (regno))
2245 regno = reg_renumber[regno];
2248 /* These fake registers will be eliminated to either the stack or
2249 hard frame pointer, both of which are usually valid base registers.
2250 Reload deals with the cases where the eliminated form isn't valid. */
2251 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
2254 /* In MIPS16 mode, the stack pointer can only address word and doubleword
2255 values, nothing smaller. */
2256 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
2257 return GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
2259 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
2262 /* Return true if X is a valid base register for mode MODE.
2263 STRICT_P is true if REG_OK_STRICT is in effect. */
2266 mips_valid_base_register_p (rtx x, enum machine_mode mode, bool strict_p)
2268 if (!strict_p && GET_CODE (x) == SUBREG)
2272 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p));
2275 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2276 can address a value of mode MODE. */
2279 mips_valid_offset_p (rtx x, enum machine_mode mode)
2281 /* Check that X is a signed 16-bit number. */
2282 if (!const_arith_operand (x, Pmode))
2285 /* We may need to split multiword moves, so make sure that every word
2287 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2288 && !SMALL_OPERAND (INTVAL (x) + GET_MODE_SIZE (mode) - UNITS_PER_WORD))
2294 /* Return true if a LO_SUM can address a value of mode MODE when the
2295 LO_SUM symbol has type SYMBOL_TYPE. */
2298 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type, enum machine_mode mode)
2300 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2302 if (mips_symbol_insns (symbol_type, mode) == 0)
2305 /* Check that there is a known low-part relocation. */
2306 if (mips_lo_relocs[symbol_type] == NULL)
2309 /* We may need to split multiword moves, so make sure that each word
2310 can be accessed without inducing a carry. This is mainly needed
2311 for o64, which has historically only guaranteed 64-bit alignment
2312 for 128-bit types. */
2313 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2314 && GET_MODE_BITSIZE (mode) > GET_MODE_ALIGNMENT (mode))
2320 /* Return true if X is a valid address for machine mode MODE. If it is,
2321 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2325 mips_classify_address (struct mips_address_info *info, rtx x,
2326 enum machine_mode mode, bool strict_p)
2328 switch (GET_CODE (x))
2332 info->type = ADDRESS_REG;
2334 info->offset = const0_rtx;
2335 return mips_valid_base_register_p (info->reg, mode, strict_p);
2338 info->type = ADDRESS_REG;
2339 info->reg = XEXP (x, 0);
2340 info->offset = XEXP (x, 1);
2341 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2342 && mips_valid_offset_p (info->offset, mode));
2345 info->type = ADDRESS_LO_SUM;
2346 info->reg = XEXP (x, 0);
2347 info->offset = XEXP (x, 1);
2348 /* We have to trust the creator of the LO_SUM to do something vaguely
2349 sane. Target-independent code that creates a LO_SUM should also
2350 create and verify the matching HIGH. Target-independent code that
2351 adds an offset to a LO_SUM must prove that the offset will not
2352 induce a carry. Failure to do either of these things would be
2353 a bug, and we are not required to check for it here. The MIPS
2354 backend itself should only create LO_SUMs for valid symbolic
2355 constants, with the high part being either a HIGH or a copy
2358 = mips_classify_symbolic_expression (info->offset, SYMBOL_CONTEXT_MEM);
2359 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2360 && mips_valid_lo_sum_p (info->symbol_type, mode));
2363 /* Small-integer addresses don't occur very often, but they
2364 are legitimate if $0 is a valid base register. */
2365 info->type = ADDRESS_CONST_INT;
2366 return !TARGET_MIPS16 && SMALL_INT (x);
2371 info->type = ADDRESS_SYMBOLIC;
2372 return (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_MEM,
2374 && mips_symbol_insns (info->symbol_type, mode) > 0
2375 && !mips_split_p[info->symbol_type]);
2382 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2385 mips_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
2387 struct mips_address_info addr;
2389 return mips_classify_address (&addr, x, mode, strict_p);
2392 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
2395 mips_stack_address_p (rtx x, enum machine_mode mode)
2397 struct mips_address_info addr;
2399 return (mips_classify_address (&addr, x, mode, false)
2400 && addr.type == ADDRESS_REG
2401 && addr.reg == stack_pointer_rtx);
2404 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2405 address instruction. Note that such addresses are not considered
2406 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2407 is so restricted. */
2410 mips_lwxs_address_p (rtx addr)
2413 && GET_CODE (addr) == PLUS
2414 && REG_P (XEXP (addr, 1)))
2416 rtx offset = XEXP (addr, 0);
2417 if (GET_CODE (offset) == MULT
2418 && REG_P (XEXP (offset, 0))
2419 && CONST_INT_P (XEXP (offset, 1))
2420 && INTVAL (XEXP (offset, 1)) == 4)
2426 /* Return true if ADDR matches the pattern for the L{B,H,W,D}{,U}X load
2427 indexed address instruction. Note that such addresses are
2428 not considered legitimate in the TARGET_LEGITIMATE_ADDRESS_P
2429 sense, because their use is so restricted. */
2432 mips_lx_address_p (rtx addr, enum machine_mode mode)
2434 if (GET_CODE (addr) != PLUS
2435 || !REG_P (XEXP (addr, 0))
2436 || !REG_P (XEXP (addr, 1)))
2438 if (ISA_HAS_LBX && mode == QImode)
2440 if (ISA_HAS_LHX && mode == HImode)
2442 if (ISA_HAS_LWX && mode == SImode)
2444 if (ISA_HAS_LDX && mode == DImode)
2449 /* Return true if a value at OFFSET bytes from base register BASE can be
2450 accessed using an unextended MIPS16 instruction. MODE is the mode of
2453 Usually the offset in an unextended instruction is a 5-bit field.
2454 The offset is unsigned and shifted left once for LH and SH, twice
2455 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2456 an 8-bit immediate field that's shifted left twice. */
2459 mips16_unextended_reference_p (enum machine_mode mode, rtx base,
2460 unsigned HOST_WIDE_INT offset)
2462 if (mode != BLKmode && offset % GET_MODE_SIZE (mode) == 0)
2464 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
2465 return offset < 256U * GET_MODE_SIZE (mode);
2466 return offset < 32U * GET_MODE_SIZE (mode);
2471 /* Return the number of instructions needed to load or store a value
2472 of mode MODE at address X, assuming that BASE_INSN_LENGTH is the
2473 length of one instruction. Return 0 if X isn't valid for MODE.
2474 Assume that multiword moves may need to be split into word moves
2475 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2479 mips_address_insns (rtx x, enum machine_mode mode, bool might_split_p)
2481 struct mips_address_info addr;
2484 /* BLKmode is used for single unaligned loads and stores and should
2485 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2486 meaningless, so we have to single it out as a special case one way
2488 if (mode != BLKmode && might_split_p)
2489 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2493 if (mips_classify_address (&addr, x, mode, false))
2498 && !mips16_unextended_reference_p (mode, addr.reg,
2499 UINTVAL (addr.offset)))
2503 case ADDRESS_LO_SUM:
2504 return TARGET_MIPS16 ? factor * 2 : factor;
2506 case ADDRESS_CONST_INT:
2509 case ADDRESS_SYMBOLIC:
2510 return factor * mips_symbol_insns (addr.symbol_type, mode);
2515 /* Return true if X fits within an unsigned field of BITS bits that is
2516 shifted left SHIFT bits before being used. */
2519 mips_unsigned_immediate_p (unsigned HOST_WIDE_INT x, int bits, int shift = 0)
2521 return (x & ((1 << shift) - 1)) == 0 && x < ((unsigned) 1 << (shift + bits));
2524 /* Return true if X fits within a signed field of BITS bits that is
2525 shifted left SHIFT bits before being used. */
2528 mips_signed_immediate_p (unsigned HOST_WIDE_INT x, int bits, int shift = 0)
2530 x += 1 << (bits + shift - 1);
2531 return mips_unsigned_immediate_p (x, bits, shift);
2534 /* Return true if X is legitimate for accessing values of mode MODE,
2535 if it is based on a MIPS16 register, and if the offset satisfies
2536 OFFSET_PREDICATE. */
2539 m16_based_address_p (rtx x, enum machine_mode mode,
2540 insn_operand_predicate_fn offset_predicate)
2542 struct mips_address_info addr;
2544 return (mips_classify_address (&addr, x, mode, false)
2545 && addr.type == ADDRESS_REG
2546 && M16_REG_P (REGNO (addr.reg))
2547 && offset_predicate (addr.offset, mode));
2550 /* Return true if X is a legitimate address that conforms to the requirements
2551 for a microMIPS LWSP or SWSP insn. */
2554 lwsp_swsp_address_p (rtx x, enum machine_mode mode)
2556 struct mips_address_info addr;
2558 return (mips_classify_address (&addr, x, mode, false)
2559 && addr.type == ADDRESS_REG
2560 && REGNO (addr.reg) == STACK_POINTER_REGNUM
2561 && uw5_operand (addr.offset, mode));
2564 /* Return true if X is a legitimate address with a 12-bit offset.
2565 MODE is the mode of the value being accessed. */
2568 umips_12bit_offset_address_p (rtx x, enum machine_mode mode)
2570 struct mips_address_info addr;
2572 return (mips_classify_address (&addr, x, mode, false)
2573 && addr.type == ADDRESS_REG
2574 && CONST_INT_P (addr.offset)
2575 && UMIPS_12BIT_OFFSET_P (INTVAL (addr.offset)));
2578 /* Return the number of instructions needed to load constant X,
2579 assuming that BASE_INSN_LENGTH is the length of one instruction.
2580 Return 0 if X isn't a valid constant. */
2583 mips_const_insns (rtx x)
2585 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2586 enum mips_symbol_type symbol_type;
2589 switch (GET_CODE (x))
2592 if (!mips_symbolic_constant_p (XEXP (x, 0), SYMBOL_CONTEXT_LEA,
2594 || !mips_split_p[symbol_type])
2597 /* This is simply an LUI for normal mode. It is an extended
2598 LI followed by an extended SLL for MIPS16. */
2599 return TARGET_MIPS16 ? 4 : 1;
2603 /* Unsigned 8-bit constants can be loaded using an unextended
2604 LI instruction. Unsigned 16-bit constants can be loaded
2605 using an extended LI. Negative constants must be loaded
2606 using LI and then negated. */
2607 return (IN_RANGE (INTVAL (x), 0, 255) ? 1
2608 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
2609 : IN_RANGE (-INTVAL (x), 0, 255) ? 2
2610 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
2613 return mips_build_integer (codes, INTVAL (x));
2617 /* Allow zeros for normal mode, where we can use $0. */
2618 return !TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0;
2624 /* See if we can refer to X directly. */
2625 if (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_LEA, &symbol_type))
2626 return mips_symbol_insns (symbol_type, MAX_MACHINE_MODE);
2628 /* Otherwise try splitting the constant into a base and offset.
2629 If the offset is a 16-bit value, we can load the base address
2630 into a register and then use (D)ADDIU to add in the offset.
2631 If the offset is larger, we can load the base and offset
2632 into separate registers and add them together with (D)ADDU.
2633 However, the latter is only possible before reload; during
2634 and after reload, we must have the option of forcing the
2635 constant into the pool instead. */
2636 split_const (x, &x, &offset);
2639 int n = mips_const_insns (x);
2642 if (SMALL_INT (offset))
2644 else if (!targetm.cannot_force_const_mem (GET_MODE (x), x))
2645 return n + 1 + mips_build_integer (codes, INTVAL (offset));
2652 return mips_symbol_insns (mips_classify_symbol (x, SYMBOL_CONTEXT_LEA),
2660 /* X is a doubleword constant that can be handled by splitting it into
2661 two words and loading each word separately. Return the number of
2662 instructions required to do this, assuming that BASE_INSN_LENGTH
2663 is the length of one instruction. */
2666 mips_split_const_insns (rtx x)
2668 unsigned int low, high;
2670 low = mips_const_insns (mips_subword (x, false));
2671 high = mips_const_insns (mips_subword (x, true));
2672 gcc_assert (low > 0 && high > 0);
2676 /* Return the number of instructions needed to implement INSN,
2677 given that it loads from or stores to MEM. Assume that
2678 BASE_INSN_LENGTH is the length of one instruction. */
2681 mips_load_store_insns (rtx mem, rtx_insn *insn)
2683 enum machine_mode mode;
2687 gcc_assert (MEM_P (mem));
2688 mode = GET_MODE (mem);
2690 /* Try to prove that INSN does not need to be split. */
2691 might_split_p = GET_MODE_SIZE (mode) > UNITS_PER_WORD;
2694 set = single_set (insn);
2695 if (set && !mips_split_move_insn_p (SET_DEST (set), SET_SRC (set), insn))
2696 might_split_p = false;
2699 return mips_address_insns (XEXP (mem, 0), mode, might_split_p);
2702 /* Return the number of instructions needed for an integer division,
2703 assuming that BASE_INSN_LENGTH is the length of one instruction. */
2706 mips_idiv_insns (void)
2711 if (TARGET_CHECK_ZERO_DIV)
2713 if (GENERATE_DIVIDE_TRAPS)
2719 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
2724 /* Emit a move from SRC to DEST. Assume that the move expanders can
2725 handle all moves if !can_create_pseudo_p (). The distinction is
2726 important because, unlike emit_move_insn, the move expanders know
2727 how to force Pmode objects into the constant pool even when the
2728 constant pool address is not itself legitimate. */
2731 mips_emit_move (rtx dest, rtx src)
2733 return (can_create_pseudo_p ()
2734 ? emit_move_insn (dest, src)
2735 : emit_move_insn_1 (dest, src));
2738 /* Emit a move from SRC to DEST, splitting compound moves into individual
2739 instructions. SPLIT_TYPE is the type of split to perform. */
2742 mips_emit_move_or_split (rtx dest, rtx src, enum mips_split_type split_type)
2744 if (mips_split_move_p (dest, src, split_type))
2745 mips_split_move (dest, src, split_type);
2747 mips_emit_move (dest, src);
2750 /* Emit an instruction of the form (set TARGET (CODE OP0)). */
2753 mips_emit_unary (enum rtx_code code, rtx target, rtx op0)
2755 emit_insn (gen_rtx_SET (VOIDmode, target,
2756 gen_rtx_fmt_e (code, GET_MODE (op0), op0)));
2759 /* Compute (CODE OP0) and store the result in a new register of mode MODE.
2760 Return that new register. */
2763 mips_force_unary (enum machine_mode mode, enum rtx_code code, rtx op0)
2767 reg = gen_reg_rtx (mode);
2768 mips_emit_unary (code, reg, op0);
2772 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2775 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
2777 emit_insn (gen_rtx_SET (VOIDmode, target,
2778 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
2781 /* Compute (CODE OP0 OP1) and store the result in a new register
2782 of mode MODE. Return that new register. */
2785 mips_force_binary (enum machine_mode mode, enum rtx_code code, rtx op0, rtx op1)
2789 reg = gen_reg_rtx (mode);
2790 mips_emit_binary (code, reg, op0, op1);
2794 /* Copy VALUE to a register and return that register. If new pseudos
2795 are allowed, copy it into a new register, otherwise use DEST. */
2798 mips_force_temporary (rtx dest, rtx value)
2800 if (can_create_pseudo_p ())
2801 return force_reg (Pmode, value);
2804 mips_emit_move (dest, value);
2809 /* Emit a call sequence with call pattern PATTERN and return the call
2810 instruction itself (which is not necessarily the last instruction
2811 emitted). ORIG_ADDR is the original, unlegitimized address,
2812 ADDR is the legitimized form, and LAZY_P is true if the call
2813 address is lazily-bound. */
2816 mips_emit_call_insn (rtx pattern, rtx orig_addr, rtx addr, bool lazy_p)
2821 insn = emit_call_insn (pattern);
2823 if (TARGET_MIPS16 && mips_use_pic_fn_addr_reg_p (orig_addr))
2825 /* MIPS16 JALRs only take MIPS16 registers. If the target
2826 function requires $25 to be valid on entry, we must copy it
2827 there separately. The move instruction can be put in the
2828 call's delay slot. */
2829 reg = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
2830 emit_insn_before (gen_move_insn (reg, addr), insn);
2831 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
2835 /* Lazy-binding stubs require $gp to be valid on entry. */
2836 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
2840 /* See the comment above load_call<mode> for details. */
2841 use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
2842 gen_rtx_REG (Pmode, GOT_VERSION_REGNUM));
2843 emit_insn (gen_update_got_version ());
2847 && TARGET_EXPLICIT_RELOCS
2848 && TARGET_CALL_CLOBBERED_GP)
2850 rtx post_call_tmp_reg = gen_rtx_REG (word_mode, POST_CALL_TMP_REG);
2851 clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), post_call_tmp_reg);
2857 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2858 then add CONST_INT OFFSET to the result. */
2861 mips_unspec_address_offset (rtx base, rtx offset,
2862 enum mips_symbol_type symbol_type)
2864 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
2865 UNSPEC_ADDRESS_FIRST + symbol_type);
2866 if (offset != const0_rtx)
2867 base = gen_rtx_PLUS (Pmode, base, offset);
2868 return gen_rtx_CONST (Pmode, base);
2871 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2872 type SYMBOL_TYPE. */
2875 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
2879 split_const (address, &base, &offset);
2880 return mips_unspec_address_offset (base, offset, symbol_type);
2883 /* If OP is an UNSPEC address, return the address to which it refers,
2884 otherwise return OP itself. */
2887 mips_strip_unspec_address (rtx op)
2891 split_const (op, &base, &offset);
2892 if (UNSPEC_ADDRESS_P (base))
2893 op = plus_constant (Pmode, UNSPEC_ADDRESS (base), INTVAL (offset));
2897 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2898 high part to BASE and return the result. Just return BASE otherwise.
2899 TEMP is as for mips_force_temporary.
2901 The returned expression can be used as the first operand to a LO_SUM. */
2904 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
2905 enum mips_symbol_type symbol_type)
2907 if (mips_split_p[symbol_type])
2909 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
2910 addr = mips_force_temporary (temp, addr);
2911 base = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
2916 /* Return an instruction that copies $gp into register REG. We want
2917 GCC to treat the register's value as constant, so that its value
2918 can be rematerialized on demand. */
2921 gen_load_const_gp (rtx reg)
2923 return PMODE_INSN (gen_load_const_gp, (reg));
2926 /* Return a pseudo register that contains the value of $gp throughout
2927 the current function. Such registers are needed by MIPS16 functions,
2928 for which $gp itself is not a valid base register or addition operand. */
2931 mips16_gp_pseudo_reg (void)
2933 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
2937 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
2939 push_topmost_sequence ();
2941 scan = get_insns ();
2942 while (NEXT_INSN (scan) && !INSN_P (NEXT_INSN (scan)))
2943 scan = NEXT_INSN (scan);
2945 rtx set = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
2946 rtx_insn *insn = emit_insn_after (set, scan);
2947 INSN_LOCATION (insn) = 0;
2949 pop_topmost_sequence ();
2952 return cfun->machine->mips16_gp_pseudo_rtx;
2955 /* Return a base register that holds pic_offset_table_rtx.
2956 TEMP, if nonnull, is a scratch Pmode base register. */
2959 mips_pic_base_register (rtx temp)
2962 return pic_offset_table_rtx;
2964 if (currently_expanding_to_rtl)
2965 return mips16_gp_pseudo_reg ();
2967 if (can_create_pseudo_p ())
2968 temp = gen_reg_rtx (Pmode);
2971 /* The first post-reload split exposes all references to $gp
2972 (both uses and definitions). All references must remain
2973 explicit after that point.
2975 It is safe to introduce uses of $gp at any time, so for
2976 simplicity, we do that before the split too. */
2977 mips_emit_move (temp, pic_offset_table_rtx);
2979 emit_insn (gen_load_const_gp (temp));
2983 /* Return the RHS of a load_call<mode> insn. */
2986 mips_unspec_call (rtx reg, rtx symbol)
2990 vec = gen_rtvec (3, reg, symbol, gen_rtx_REG (SImode, GOT_VERSION_REGNUM));
2991 return gen_rtx_UNSPEC (Pmode, vec, UNSPEC_LOAD_CALL);
2994 /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol
2995 reference. Return NULL_RTX otherwise. */
2998 mips_strip_unspec_call (rtx src)
3000 if (GET_CODE (src) == UNSPEC && XINT (src, 1) == UNSPEC_LOAD_CALL)
3001 return mips_strip_unspec_address (XVECEXP (src, 0, 1));
3005 /* Create and return a GOT reference of type TYPE for address ADDR.
3006 TEMP, if nonnull, is a scratch Pmode base register. */
3009 mips_got_load (rtx temp, rtx addr, enum mips_symbol_type type)
3011 rtx base, high, lo_sum_symbol;
3013 base = mips_pic_base_register (temp);
3015 /* If we used the temporary register to load $gp, we can't use
3016 it for the high part as well. */
3017 if (temp != NULL && reg_overlap_mentioned_p (base, temp))
3020 high = mips_unspec_offset_high (temp, base, addr, type);
3021 lo_sum_symbol = mips_unspec_address (addr, type);
3023 if (type == SYMBOL_GOTOFF_CALL)
3024 return mips_unspec_call (high, lo_sum_symbol);
3026 return PMODE_INSN (gen_unspec_got, (high, lo_sum_symbol));
3029 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
3030 it appears in a MEM of that mode. Return true if ADDR is a legitimate
3031 constant in that context and can be split into high and low parts.
3032 If so, and if LOW_OUT is nonnull, emit the high part and store the
3033 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
3035 TEMP is as for mips_force_temporary and is used to load the high
3036 part into a register.
3038 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
3039 a legitimize SET_SRC for an .md pattern, otherwise the low part
3040 is guaranteed to be a legitimate address for mode MODE. */
3043 mips_split_symbol (rtx temp, rtx addr, enum machine_mode mode, rtx *low_out)
3045 enum mips_symbol_context context;
3046 enum mips_symbol_type symbol_type;
3049 context = (mode == MAX_MACHINE_MODE
3050 ? SYMBOL_CONTEXT_LEA
3051 : SYMBOL_CONTEXT_MEM);
3052 if (GET_CODE (addr) == HIGH && context == SYMBOL_CONTEXT_LEA)
3054 addr = XEXP (addr, 0);
3055 if (mips_symbolic_constant_p (addr, context, &symbol_type)
3056 && mips_symbol_insns (symbol_type, mode) > 0
3057 && mips_split_hi_p[symbol_type])
3060 switch (symbol_type)
3062 case SYMBOL_GOT_PAGE_OFST:
3063 /* The high part of a page/ofst pair is loaded from the GOT. */
3064 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_PAGE);
3075 if (mips_symbolic_constant_p (addr, context, &symbol_type)
3076 && mips_symbol_insns (symbol_type, mode) > 0
3077 && mips_split_p[symbol_type])
3080 switch (symbol_type)
3082 case SYMBOL_GOT_DISP:
3083 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
3084 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_DISP);
3087 case SYMBOL_GP_RELATIVE:
3088 high = mips_pic_base_register (temp);
3089 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
3093 high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
3094 high = mips_force_temporary (temp, high);
3095 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
3104 /* Return a legitimate address for REG + OFFSET. TEMP is as for
3105 mips_force_temporary; it is only needed when OFFSET is not a
3109 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
3111 if (!SMALL_OPERAND (offset))
3117 /* Load the full offset into a register so that we can use
3118 an unextended instruction for the address itself. */
3119 high = GEN_INT (offset);
3124 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
3125 The addition inside the macro CONST_HIGH_PART may cause an
3126 overflow, so we need to force a sign-extension check. */
3127 high = gen_int_mode (CONST_HIGH_PART (offset), Pmode);
3128 offset = CONST_LOW_PART (offset);
3130 high = mips_force_temporary (temp, high);
3131 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
3133 return plus_constant (Pmode, reg, offset);
3136 /* The __tls_get_attr symbol. */
3137 static GTY(()) rtx mips_tls_symbol;
3139 /* Return an instruction sequence that calls __tls_get_addr. SYM is
3140 the TLS symbol we are referencing and TYPE is the symbol type to use
3141 (either global dynamic or local dynamic). V0 is an RTX for the
3142 return value location. */
3145 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
3149 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
3151 if (!mips_tls_symbol)
3152 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
3154 loc = mips_unspec_address (sym, type);
3158 emit_insn (gen_rtx_SET (Pmode, a0,
3159 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
3160 insn = mips_expand_call (MIPS_CALL_NORMAL, v0, mips_tls_symbol,
3161 const0_rtx, NULL_RTX, false);
3162 RTL_CONST_CALL_P (insn) = 1;
3163 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
3164 insn = get_insns ();
3171 /* Return a pseudo register that contains the current thread pointer. */
3174 mips_expand_thread_pointer (rtx tp)
3180 if (!mips16_rdhwr_stub)
3181 mips16_rdhwr_stub = new mips16_rdhwr_one_only_stub ();
3182 fn = mips16_stub_call_address (mips16_rdhwr_stub);
3183 emit_insn (PMODE_INSN (gen_tls_get_tp_mips16, (tp, fn)));
3186 emit_insn (PMODE_INSN (gen_tls_get_tp, (tp)));
3193 return mips_expand_thread_pointer (gen_reg_rtx (Pmode));
3196 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
3197 its address. The return value will be both a valid address and a valid
3198 SET_SRC (either a REG or a LO_SUM). */
3201 mips_legitimize_tls_address (rtx loc)
3203 rtx dest, insn, v0, tp, tmp1, tmp2, eqv, offset;
3204 enum tls_model model;
3206 model = SYMBOL_REF_TLS_MODEL (loc);
3207 /* Only TARGET_ABICALLS code can have more than one module; other
3208 code must be be static and should not use a GOT. All TLS models
3209 reduce to local exec in this situation. */
3210 if (!TARGET_ABICALLS)
3211 model = TLS_MODEL_LOCAL_EXEC;
3215 case TLS_MODEL_GLOBAL_DYNAMIC:
3216 v0 = gen_rtx_REG (Pmode, GP_RETURN);
3217 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
3218 dest = gen_reg_rtx (Pmode);
3219 emit_libcall_block (insn, dest, v0, loc);
3222 case TLS_MODEL_LOCAL_DYNAMIC:
3223 v0 = gen_rtx_REG (Pmode, GP_RETURN);
3224 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
3225 tmp1 = gen_reg_rtx (Pmode);
3227 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
3228 share the LDM result with other LD model accesses. */
3229 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3231 emit_libcall_block (insn, tmp1, v0, eqv);
3233 offset = mips_unspec_address (loc, SYMBOL_DTPREL);
3234 if (mips_split_p[SYMBOL_DTPREL])
3236 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
3237 dest = gen_rtx_LO_SUM (Pmode, tmp2, offset);
3240 dest = expand_binop (Pmode, add_optab, tmp1, offset,
3241 0, 0, OPTAB_DIRECT);
3244 case TLS_MODEL_INITIAL_EXEC:
3245 tp = mips_get_tp ();
3246 tmp1 = gen_reg_rtx (Pmode);
3247 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
3248 if (Pmode == DImode)
3249 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
3251 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
3252 dest = gen_reg_rtx (Pmode);
3253 emit_insn (gen_add3_insn (dest, tmp1, tp));
3256 case TLS_MODEL_LOCAL_EXEC:
3257 tmp1 = mips_get_tp ();
3258 offset = mips_unspec_address (loc, SYMBOL_TPREL);
3259 if (mips_split_p[SYMBOL_TPREL])
3261 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_TPREL);
3262 dest = gen_rtx_LO_SUM (Pmode, tmp2, offset);
3265 dest = expand_binop (Pmode, add_optab, tmp1, offset,
3266 0, 0, OPTAB_DIRECT);
3275 /* Implement "TARGET = __builtin_mips_get_fcsr ()" for MIPS16,
3279 mips16_expand_get_fcsr (rtx target)
3281 if (!mips16_get_fcsr_stub)
3282 mips16_get_fcsr_stub = new mips16_get_fcsr_one_only_stub ();
3283 rtx fn = mips16_stub_call_address (mips16_get_fcsr_stub);
3284 emit_insn (PMODE_INSN (gen_mips_get_fcsr_mips16, (fn)));
3285 emit_move_insn (target, gen_rtx_REG (SImode, GET_FCSR_REGNUM));
3288 /* Implement __builtin_mips_set_fcsr (TARGET) for MIPS16, using a stub. */
3291 mips16_expand_set_fcsr (rtx newval)
3293 if (!mips16_set_fcsr_stub)
3294 mips16_set_fcsr_stub = new mips16_set_fcsr_one_only_stub ();
3295 rtx fn = mips16_stub_call_address (mips16_set_fcsr_stub);
3296 emit_move_insn (gen_rtx_REG (SImode, SET_FCSR_REGNUM), newval);
3297 emit_insn (PMODE_INSN (gen_mips_set_fcsr_mips16, (fn)));
3300 /* If X is not a valid address for mode MODE, force it into a register. */
3303 mips_force_address (rtx x, enum machine_mode mode)
3305 if (!mips_legitimate_address_p (mode, x, false))
3306 x = force_reg (Pmode, x);
3310 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
3311 be legitimized in a way that the generic machinery might not expect,
3312 return a new address, otherwise return NULL. MODE is the mode of
3313 the memory being accessed. */
3316 mips_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3317 enum machine_mode mode)
3320 HOST_WIDE_INT offset;
3322 if (mips_tls_symbol_p (x))
3323 return mips_legitimize_tls_address (x);
3325 /* See if the address can split into a high part and a LO_SUM. */
3326 if (mips_split_symbol (NULL, x, mode, &addr))
3327 return mips_force_address (addr, mode);
3329 /* Handle BASE + OFFSET using mips_add_offset. */
3330 mips_split_plus (x, &base, &offset);
3333 if (!mips_valid_base_register_p (base, mode, false))
3334 base = copy_to_mode_reg (Pmode, base);
3335 addr = mips_add_offset (NULL, base, offset);
3336 return mips_force_address (addr, mode);
3342 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
3345 mips_move_integer (rtx temp, rtx dest, unsigned HOST_WIDE_INT value)
3347 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
3348 enum machine_mode mode;
3349 unsigned int i, num_ops;
3352 mode = GET_MODE (dest);
3353 num_ops = mips_build_integer (codes, value);
3355 /* Apply each binary operation to X. Invariant: X is a legitimate
3356 source operand for a SET pattern. */
3357 x = GEN_INT (codes[0].value);
3358 for (i = 1; i < num_ops; i++)
3360 if (!can_create_pseudo_p ())
3362 emit_insn (gen_rtx_SET (VOIDmode, temp, x));
3366 x = force_reg (mode, x);
3367 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
3370 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
3373 /* Subroutine of mips_legitimize_move. Move constant SRC into register
3374 DEST given that SRC satisfies immediate_operand but doesn't satisfy
3378 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
3382 /* Split moves of big integers into smaller pieces. */
3383 if (splittable_const_int_operand (src, mode))
3385 mips_move_integer (dest, dest, INTVAL (src));
3389 /* Split moves of symbolic constants into high/low pairs. */
3390 if (mips_split_symbol (dest, src, MAX_MACHINE_MODE, &src))
3392 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
3396 /* Generate the appropriate access sequences for TLS symbols. */
3397 if (mips_tls_symbol_p (src))
3399 mips_emit_move (dest, mips_legitimize_tls_address (src));
3403 /* If we have (const (plus symbol offset)), and that expression cannot
3404 be forced into memory, load the symbol first and add in the offset.
3405 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
3406 forced into memory, as it usually produces better code. */
3407 split_const (src, &base, &offset);
3408 if (offset != const0_rtx
3409 && (targetm.cannot_force_const_mem (mode, src)
3410 || (!TARGET_MIPS16 && can_create_pseudo_p ())))
3412 base = mips_force_temporary (dest, base);
3413 mips_emit_move (dest, mips_add_offset (NULL, base, INTVAL (offset)));
3417 src = force_const_mem (mode, src);
3419 /* When using explicit relocs, constant pool references are sometimes
3420 not legitimate addresses. */
3421 mips_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0));
3422 mips_emit_move (dest, src);
3425 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
3426 sequence that is valid. */
3429 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
3431 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
3433 mips_emit_move (dest, force_reg (mode, src));
3437 /* We need to deal with constants that would be legitimate
3438 immediate_operands but aren't legitimate move_operands. */
3439 if (CONSTANT_P (src) && !move_operand (src, mode))
3441 mips_legitimize_const_move (mode, dest, src);
3442 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
3448 /* Return true if value X in context CONTEXT is a small-data address
3449 that can be rewritten as a LO_SUM. */
3452 mips_rewrite_small_data_p (rtx x, enum mips_symbol_context context)
3454 enum mips_symbol_type symbol_type;
3456 return (mips_lo_relocs[SYMBOL_GP_RELATIVE]
3457 && !mips_split_p[SYMBOL_GP_RELATIVE]
3458 && mips_symbolic_constant_p (x, context, &symbol_type)
3459 && symbol_type == SYMBOL_GP_RELATIVE);
3462 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
3463 containing MEM, or null if none. */
3466 mips_small_data_pattern_1 (rtx *loc, void *data)
3468 enum mips_symbol_context context;
3470 /* Ignore things like "g" constraints in asms. We make no particular
3471 guarantee about which symbolic constants are acceptable as asm operands
3472 versus which must be forced into a GPR. */
3473 if (GET_CODE (*loc) == LO_SUM || GET_CODE (*loc) == ASM_OPERANDS)
3478 if (for_each_rtx (&XEXP (*loc, 0), mips_small_data_pattern_1, *loc))
3483 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3484 return mips_rewrite_small_data_p (*loc, context);
3487 /* Return true if OP refers to small data symbols directly, not through
3491 mips_small_data_pattern_p (rtx op)
3493 return for_each_rtx (&op, mips_small_data_pattern_1, NULL);
3496 /* A for_each_rtx callback, used by mips_rewrite_small_data.
3497 DATA is the containing MEM, or null if none. */
3500 mips_rewrite_small_data_1 (rtx *loc, void *data)
3502 enum mips_symbol_context context;
3506 for_each_rtx (&XEXP (*loc, 0), mips_rewrite_small_data_1, *loc);
3510 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3511 if (mips_rewrite_small_data_p (*loc, context))
3512 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
3514 if (GET_CODE (*loc) == LO_SUM)
3520 /* Rewrite instruction pattern PATTERN so that it refers to small data
3521 using explicit relocations. */
3524 mips_rewrite_small_data (rtx pattern)
3526 pattern = copy_insn (pattern);
3527 for_each_rtx (&pattern, mips_rewrite_small_data_1, NULL);
3531 /* The cost of loading values from the constant pool. It should be
3532 larger than the cost of any constant we want to synthesize inline. */
3533 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3535 /* Return the cost of X when used as an operand to the MIPS16 instruction
3536 that implements CODE. Return -1 if there is no such instruction, or if
3537 X is not a valid immediate operand for it. */
3540 mips16_constant_cost (int code, HOST_WIDE_INT x)
3547 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3548 other shifts are extended. The shift patterns truncate the shift
3549 count to the right size, so there are no out-of-range values. */
3550 if (IN_RANGE (x, 1, 8))
3552 return COSTS_N_INSNS (1);
3555 if (IN_RANGE (x, -128, 127))
3557 if (SMALL_OPERAND (x))
3558 return COSTS_N_INSNS (1);
3562 /* Like LE, but reject the always-true case. */
3566 /* We add 1 to the immediate and use SLT. */
3569 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3572 if (IN_RANGE (x, 0, 255))
3574 if (SMALL_OPERAND_UNSIGNED (x))
3575 return COSTS_N_INSNS (1);
3580 /* Equality comparisons with 0 are cheap. */
3590 /* Return true if there is a non-MIPS16 instruction that implements CODE
3591 and if that instruction accepts X as an immediate operand. */
3594 mips_immediate_operand_p (int code, HOST_WIDE_INT x)
3601 /* All shift counts are truncated to a valid constant. */
3606 /* Likewise rotates, if the target supports rotates at all. */
3612 /* These instructions take 16-bit unsigned immediates. */
3613 return SMALL_OPERAND_UNSIGNED (x);
3618 /* These instructions take 16-bit signed immediates. */
3619 return SMALL_OPERAND (x);
3625 /* The "immediate" forms of these instructions are really
3626 implemented as comparisons with register 0. */
3631 /* Likewise, meaning that the only valid immediate operand is 1. */
3635 /* We add 1 to the immediate and use SLT. */
3636 return SMALL_OPERAND (x + 1);
3639 /* Likewise SLTU, but reject the always-true case. */
3640 return SMALL_OPERAND (x + 1) && x + 1 != 0;
3644 /* The bit position and size are immediate operands. */
3645 return ISA_HAS_EXT_INS;
3648 /* By default assume that $0 can be used for 0. */
3653 /* Return the cost of binary operation X, given that the instruction
3654 sequence for a word-sized or smaller operation has cost SINGLE_COST
3655 and that the sequence of a double-word operation has cost DOUBLE_COST.
3656 If SPEED is true, optimize for speed otherwise optimize for size. */
3659 mips_binary_cost (rtx x, int single_cost, int double_cost, bool speed)
3663 if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2)
3668 + set_src_cost (XEXP (x, 0), speed)
3669 + rtx_cost (XEXP (x, 1), GET_CODE (x), 1, speed));
3672 /* Return the cost of floating-point multiplications of mode MODE. */
3675 mips_fp_mult_cost (enum machine_mode mode)
3677 return mode == DFmode ? mips_cost->fp_mult_df : mips_cost->fp_mult_sf;
3680 /* Return the cost of floating-point divisions of mode MODE. */
3683 mips_fp_div_cost (enum machine_mode mode)
3685 return mode == DFmode ? mips_cost->fp_div_df : mips_cost->fp_div_sf;
3688 /* Return the cost of sign-extending OP to mode MODE, not including the
3689 cost of OP itself. */
3692 mips_sign_extend_cost (enum machine_mode mode, rtx op)
3695 /* Extended loads are as cheap as unextended ones. */
3698 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3699 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3702 if (ISA_HAS_SEB_SEH || GENERATE_MIPS16E)
3703 /* We can use SEB or SEH. */
3704 return COSTS_N_INSNS (1);
3706 /* We need to use a shift left and a shift right. */
3707 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3710 /* Return the cost of zero-extending OP to mode MODE, not including the
3711 cost of OP itself. */
3714 mips_zero_extend_cost (enum machine_mode mode, rtx op)
3717 /* Extended loads are as cheap as unextended ones. */
3720 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3721 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3722 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3724 if (GENERATE_MIPS16E)
3725 /* We can use ZEB or ZEH. */
3726 return COSTS_N_INSNS (1);
3729 /* We need to load 0xff or 0xffff into a register and use AND. */
3730 return COSTS_N_INSNS (GET_MODE (op) == QImode ? 2 : 3);
3732 /* We can use ANDI. */
3733 return COSTS_N_INSNS (1);
3736 /* Return the cost of moving between two registers of mode MODE,
3737 assuming that the move will be in pieces of at most UNITS bytes. */
3740 mips_set_reg_reg_piece_cost (enum machine_mode mode, unsigned int units)
3742 return COSTS_N_INSNS ((GET_MODE_SIZE (mode) + units - 1) / units);
3745 /* Return the cost of moving between two registers of mode MODE. */
3748 mips_set_reg_reg_cost (enum machine_mode mode)
3750 switch (GET_MODE_CLASS (mode))
3753 return mips_set_reg_reg_piece_cost (mode, GET_MODE_SIZE (CCmode));
3756 case MODE_COMPLEX_FLOAT:
3757 case MODE_VECTOR_FLOAT:
3758 if (TARGET_HARD_FLOAT)
3759 return mips_set_reg_reg_piece_cost (mode, UNITS_PER_HWFPVALUE);
3763 return mips_set_reg_reg_piece_cost (mode, UNITS_PER_WORD);
3767 /* Implement TARGET_RTX_COSTS. */
3770 mips_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
3771 int *total, bool speed)
3773 enum machine_mode mode = GET_MODE (x);
3774 bool float_mode_p = FLOAT_MODE_P (mode);
3778 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3779 appear in the instruction stream, and the cost of a comparison is
3780 really the cost of the branch or scc condition. At the time of
3781 writing, GCC only uses an explicit outer COMPARE code when optabs
3782 is testing whether a constant is expensive enough to force into a
3783 register. We want optabs to pass such constants through the MIPS
3784 expanders instead, so make all constants very cheap here. */
3785 if (outer_code == COMPARE)
3787 gcc_assert (CONSTANT_P (x));
3795 /* Treat *clear_upper32-style ANDs as having zero cost in the
3796 second operand. The cost is entirely in the first operand.
3798 ??? This is needed because we would otherwise try to CSE
3799 the constant operand. Although that's the right thing for
3800 instructions that continue to be a register operation throughout
3801 compilation, it is disastrous for instructions that could
3802 later be converted into a memory operation. */
3804 && outer_code == AND
3805 && UINTVAL (x) == 0xffffffff)
3813 cost = mips16_constant_cost (outer_code, INTVAL (x));
3822 /* When not optimizing for size, we care more about the cost
3823 of hot code, and hot code is often in a loop. If a constant
3824 operand needs to be forced into a register, we will often be
3825 able to hoist the constant load out of the loop, so the load
3826 should not contribute to the cost. */
3827 if (speed || mips_immediate_operand_p (outer_code, INTVAL (x)))
3839 if (force_to_mem_operand (x, VOIDmode))
3841 *total = COSTS_N_INSNS (1);
3844 cost = mips_const_insns (x);
3847 /* If the constant is likely to be stored in a GPR, SETs of
3848 single-insn constants are as cheap as register sets; we
3849 never want to CSE them.
3851 Don't reduce the cost of storing a floating-point zero in
3852 FPRs. If we have a zero in an FPR for other reasons, we
3853 can get better cfg-cleanup and delayed-branch results by
3854 using it consistently, rather than using $0 sometimes and
3855 an FPR at other times. Also, moves between floating-point
3856 registers are sometimes cheaper than (D)MTC1 $0. */
3858 && outer_code == SET
3859 && !(float_mode_p && TARGET_HARD_FLOAT))
3861 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3862 want to CSE the constant itself. It is usually better to
3863 have N copies of the last operation in the sequence and one
3864 shared copy of the other operations. (Note that this is
3865 not true for MIPS16 code, where the final operation in the
3866 sequence is often an extended instruction.)
3868 Also, if we have a CONST_INT, we don't know whether it is
3869 for a word or doubleword operation, so we cannot rely on
3870 the result of mips_build_integer. */
3871 else if (!TARGET_MIPS16
3872 && (outer_code == SET || mode == VOIDmode))
3874 *total = COSTS_N_INSNS (cost);
3877 /* The value will need to be fetched from the constant pool. */
3878 *total = CONSTANT_POOL_COST;
3882 /* If the address is legitimate, return the number of
3883 instructions it needs. */
3885 cost = mips_address_insns (addr, mode, true);
3888 *total = COSTS_N_INSNS (cost + 1);
3891 /* Check for a scaled indexed address. */
3892 if (mips_lwxs_address_p (addr)
3893 || mips_lx_address_p (addr, mode))
3895 *total = COSTS_N_INSNS (2);
3898 /* Otherwise use the default handling. */
3902 *total = COSTS_N_INSNS (6);
3906 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1);
3910 /* Check for a *clear_upper32 pattern and treat it like a zero
3911 extension. See the pattern's comment for details. */
3914 && CONST_INT_P (XEXP (x, 1))
3915 && UINTVAL (XEXP (x, 1)) == 0xffffffff)
3917 *total = (mips_zero_extend_cost (mode, XEXP (x, 0))
3918 + set_src_cost (XEXP (x, 0), speed));
3921 if (ISA_HAS_CINS && CONST_INT_P (XEXP (x, 1)))
3923 rtx op = XEXP (x, 0);
3924 if (GET_CODE (op) == ASHIFT
3925 && CONST_INT_P (XEXP (op, 1))
3926 && mask_low_and_shift_p (mode, XEXP (x, 1), XEXP (op, 1), 32))
3928 *total = COSTS_N_INSNS (1) + set_src_cost (XEXP (op, 0), speed);
3932 /* (AND (NOT op0) (NOT op1) is a nor operation that can be done in
3933 a single instruction. */
3935 && GET_CODE (XEXP (x, 0)) == NOT
3936 && GET_CODE (XEXP (x, 1)) == NOT)
3938 cost = GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1;
3939 *total = (COSTS_N_INSNS (cost)
3940 + set_src_cost (XEXP (XEXP (x, 0), 0), speed)
3941 + set_src_cost (XEXP (XEXP (x, 1), 0), speed));
3949 /* Double-word operations use two single-word operations. */
3950 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (2),
3959 if (CONSTANT_P (XEXP (x, 1)))
3960 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3963 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (12),
3969 *total = mips_cost->fp_add;
3971 *total = COSTS_N_INSNS (4);
3975 /* Low-part immediates need an extended MIPS16 instruction. */
3976 *total = (COSTS_N_INSNS (TARGET_MIPS16 ? 2 : 1)
3977 + set_src_cost (XEXP (x, 0), speed));
3992 /* Branch comparisons have VOIDmode, so use the first operand's
3994 mode = GET_MODE (XEXP (x, 0));
3995 if (FLOAT_MODE_P (mode))
3997 *total = mips_cost->fp_add;
4000 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
4006 && (ISA_HAS_NMADD4_NMSUB4 || ISA_HAS_NMADD3_NMSUB3)
4007 && TARGET_FUSED_MADD
4008 && !HONOR_NANS (mode)
4009 && !HONOR_SIGNED_ZEROS (mode))
4011 /* See if we can use NMADD or NMSUB. See mips.md for the
4012 associated patterns. */
4013 rtx op0 = XEXP (x, 0);
4014 rtx op1 = XEXP (x, 1);
4015 if (GET_CODE (op0) == MULT && GET_CODE (XEXP (op0, 0)) == NEG)
4017 *total = (mips_fp_mult_cost (mode)
4018 + set_src_cost (XEXP (XEXP (op0, 0), 0), speed)
4019 + set_src_cost (XEXP (op0, 1), speed)
4020 + set_src_cost (op1, speed));
4023 if (GET_CODE (op1) == MULT)
4025 *total = (mips_fp_mult_cost (mode)
4026 + set_src_cost (op0, speed)
4027 + set_src_cost (XEXP (op1, 0), speed)
4028 + set_src_cost (XEXP (op1, 1), speed));
4037 /* If this is part of a MADD or MSUB, treat the PLUS as
4039 if ((ISA_HAS_FP_MADD4_MSUB4 || ISA_HAS_FP_MADD3_MSUB3)
4040 && TARGET_FUSED_MADD
4041 && GET_CODE (XEXP (x, 0)) == MULT)
4044 *total = mips_cost->fp_add;
4048 /* Double-word operations require three single-word operations and
4049 an SLTU. The MIPS16 version then needs to move the result of
4050 the SLTU from $24 to a MIPS16 register. */
4051 *total = mips_binary_cost (x, COSTS_N_INSNS (1),
4052 COSTS_N_INSNS (TARGET_MIPS16 ? 5 : 4),
4058 && (ISA_HAS_NMADD4_NMSUB4 || ISA_HAS_NMADD3_NMSUB3)
4059 && TARGET_FUSED_MADD
4060 && !HONOR_NANS (mode)
4061 && HONOR_SIGNED_ZEROS (mode))
4063 /* See if we can use NMADD or NMSUB. See mips.md for the
4064 associated patterns. */
4065 rtx op = XEXP (x, 0);
4066 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
4067 && GET_CODE (XEXP (op, 0)) == MULT)
4069 *total = (mips_fp_mult_cost (mode)
4070 + set_src_cost (XEXP (XEXP (op, 0), 0), speed)
4071 + set_src_cost (XEXP (XEXP (op, 0), 1), speed)
4072 + set_src_cost (XEXP (op, 1), speed));
4078 *total = mips_cost->fp_add;
4080 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1);
4085 *total = mips_fp_mult_cost (mode);
4086 else if (mode == DImode && !TARGET_64BIT)
4087 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
4088 where the mulsidi3 always includes an MFHI and an MFLO. */
4090 ? mips_cost->int_mult_si * 3 + 6
4091 : COSTS_N_INSNS (ISA_HAS_MUL3 ? 7 : 9));
4093 *total = COSTS_N_INSNS (ISA_HAS_MUL3 ? 1 : 2) + 1;
4094 else if (mode == DImode)
4095 *total = mips_cost->int_mult_di;
4097 *total = mips_cost->int_mult_si;
4101 /* Check for a reciprocal. */
4103 && ISA_HAS_FP_RECIP_RSQRT (mode)
4104 && flag_unsafe_math_optimizations
4105 && XEXP (x, 0) == CONST1_RTX (mode))
4107 if (outer_code == SQRT || GET_CODE (XEXP (x, 1)) == SQRT)
4108 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
4109 division as being free. */
4110 *total = set_src_cost (XEXP (x, 1), speed);
4112 *total = (mips_fp_div_cost (mode)
4113 + set_src_cost (XEXP (x, 1), speed));
4122 *total = mips_fp_div_cost (mode);
4131 /* It is our responsibility to make division by a power of 2
4132 as cheap as 2 register additions if we want the division
4133 expanders to be used for such operations; see the setting
4134 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
4135 should always produce shorter code than using
4136 expand_sdiv2_pow2. */
4138 && CONST_INT_P (XEXP (x, 1))
4139 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
4141 *total = COSTS_N_INSNS (2) + set_src_cost (XEXP (x, 0), speed);
4144 *total = COSTS_N_INSNS (mips_idiv_insns ());
4146 else if (mode == DImode)
4147 *total = mips_cost->int_div_di;
4149 *total = mips_cost->int_div_si;
4153 *total = mips_sign_extend_cost (mode, XEXP (x, 0));
4157 if (outer_code == SET
4159 && (GET_CODE (XEXP (x, 0)) == TRUNCATE
4160 || GET_CODE (XEXP (x, 0)) == SUBREG)
4161 && GET_MODE (XEXP (x, 0)) == QImode
4162 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
4164 *total = set_src_cost (XEXP (XEXP (x, 0), 0), speed);
4167 *total = mips_zero_extend_cost (mode, XEXP (x, 0));
4171 case UNSIGNED_FLOAT:
4174 case FLOAT_TRUNCATE:
4175 *total = mips_cost->fp_add;
4179 if (register_operand (SET_DEST (x), VOIDmode)
4180 && reg_or_0_operand (SET_SRC (x), VOIDmode))
4182 *total = mips_set_reg_reg_cost (GET_MODE (SET_DEST (x)));
4192 /* Implement TARGET_ADDRESS_COST. */
4195 mips_address_cost (rtx addr, enum machine_mode mode,
4196 addr_space_t as ATTRIBUTE_UNUSED,
4197 bool speed ATTRIBUTE_UNUSED)
4199 return mips_address_insns (addr, mode, false);
4202 /* Information about a single instruction in a multi-instruction
4204 struct mips_multi_member {
4205 /* True if this is a label, false if it is code. */
4208 /* The output_asm_insn format of the instruction. */
4211 /* The operands to the instruction. */
4212 rtx operands[MAX_RECOG_OPERANDS];
4214 typedef struct mips_multi_member mips_multi_member;
4216 /* The instructions that make up the current multi-insn sequence. */
4217 static vec<mips_multi_member> mips_multi_members;
4219 /* How many instructions (as opposed to labels) are in the current
4220 multi-insn sequence. */
4221 static unsigned int mips_multi_num_insns;
4223 /* Start a new multi-insn sequence. */
4226 mips_multi_start (void)
4228 mips_multi_members.truncate (0);
4229 mips_multi_num_insns = 0;
4232 /* Add a new, uninitialized member to the current multi-insn sequence. */
4234 static struct mips_multi_member *
4235 mips_multi_add (void)
4237 mips_multi_member empty;
4238 return mips_multi_members.safe_push (empty);
4241 /* Add a normal insn with the given asm format to the current multi-insn
4242 sequence. The other arguments are a null-terminated list of operands. */
4245 mips_multi_add_insn (const char *format, ...)
4247 struct mips_multi_member *member;
4252 member = mips_multi_add ();
4253 member->is_label_p = false;
4254 member->format = format;
4255 va_start (ap, format);
4257 while ((op = va_arg (ap, rtx)))
4258 member->operands[i++] = op;
4260 mips_multi_num_insns++;
4263 /* Add the given label definition to the current multi-insn sequence.
4264 The definition should include the colon. */
4267 mips_multi_add_label (const char *label)
4269 struct mips_multi_member *member;
4271 member = mips_multi_add ();
4272 member->is_label_p = true;
4273 member->format = label;
4276 /* Return the index of the last member of the current multi-insn sequence. */
4279 mips_multi_last_index (void)
4281 return mips_multi_members.length () - 1;
4284 /* Add a copy of an existing instruction to the current multi-insn
4285 sequence. I is the index of the instruction that should be copied. */
4288 mips_multi_copy_insn (unsigned int i)
4290 struct mips_multi_member *member;
4292 member = mips_multi_add ();
4293 memcpy (member, &mips_multi_members[i], sizeof (*member));
4294 gcc_assert (!member->is_label_p);
4297 /* Change the operand of an existing instruction in the current
4298 multi-insn sequence. I is the index of the instruction,
4299 OP is the index of the operand, and X is the new value. */
4302 mips_multi_set_operand (unsigned int i, unsigned int op, rtx x)
4304 mips_multi_members[i].operands[op] = x;
4307 /* Write out the asm code for the current multi-insn sequence. */
4310 mips_multi_write (void)
4312 struct mips_multi_member *member;
4315 FOR_EACH_VEC_ELT (mips_multi_members, i, member)
4316 if (member->is_label_p)
4317 fprintf (asm_out_file, "%s\n", member->format);
4319 output_asm_insn (member->format, member->operands);
4322 /* Return one word of double-word value OP, taking into account the fixed
4323 endianness of certain registers. HIGH_P is true to select the high part,
4324 false to select the low part. */
4327 mips_subword (rtx op, bool high_p)
4329 unsigned int byte, offset;
4330 enum machine_mode mode;
4332 mode = GET_MODE (op);
4333 if (mode == VOIDmode)
4334 mode = TARGET_64BIT ? TImode : DImode;
4336 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
4337 byte = UNITS_PER_WORD;
4341 if (FP_REG_RTX_P (op))
4343 /* Paired FPRs are always ordered little-endian. */
4344 offset = (UNITS_PER_WORD < UNITS_PER_HWFPVALUE ? high_p : byte != 0);
4345 return gen_rtx_REG (word_mode, REGNO (op) + offset);
4349 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
4351 return simplify_gen_subreg (word_mode, op, mode, byte);
4354 /* Return true if SRC should be moved into DEST using "MULT $0, $0".
4355 SPLIT_TYPE is the condition under which moves should be split. */
4358 mips_mult_move_p (rtx dest, rtx src, enum mips_split_type split_type)
4360 return ((split_type != SPLIT_FOR_SPEED
4361 || mips_tuning_info.fast_mult_zero_zero_p)
4362 && src == const0_rtx
4364 && GET_MODE_SIZE (GET_MODE (dest)) == 2 * UNITS_PER_WORD
4365 && (ISA_HAS_DSP_MULT
4366 ? ACC_REG_P (REGNO (dest))
4367 : MD_REG_P (REGNO (dest))));
4370 /* Return true if a move from SRC to DEST should be split into two.
4371 SPLIT_TYPE describes the split condition. */
4374 mips_split_move_p (rtx dest, rtx src, enum mips_split_type split_type)
4376 /* Check whether the move can be done using some variant of MULT $0,$0. */
4377 if (mips_mult_move_p (dest, src, split_type))
4380 /* FPR-to-FPR moves can be done in a single instruction, if they're
4382 unsigned int size = GET_MODE_SIZE (GET_MODE (dest));
4383 if (size == 8 && FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
4386 /* Check for floating-point loads and stores. */
4387 if (size == 8 && ISA_HAS_LDC1_SDC1)
4389 if (FP_REG_RTX_P (dest) && MEM_P (src))
4391 if (FP_REG_RTX_P (src) && MEM_P (dest))
4395 /* Otherwise split all multiword moves. */
4396 return size > UNITS_PER_WORD;
4399 /* Split a move from SRC to DEST, given that mips_split_move_p holds.
4400 SPLIT_TYPE describes the split condition. */
4403 mips_split_move (rtx dest, rtx src, enum mips_split_type split_type)
4407 gcc_checking_assert (mips_split_move_p (dest, src, split_type));
4408 if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src))
4410 if (!TARGET_64BIT && GET_MODE (dest) == DImode)
4411 emit_insn (gen_move_doubleword_fprdi (dest, src));
4412 else if (!TARGET_64BIT && GET_MODE (dest) == DFmode)
4413 emit_insn (gen_move_doubleword_fprdf (dest, src));
4414 else if (!TARGET_64BIT && GET_MODE (dest) == V2SFmode)
4415 emit_insn (gen_move_doubleword_fprv2sf (dest, src));
4416 else if (!TARGET_64BIT && GET_MODE (dest) == V2SImode)
4417 emit_insn (gen_move_doubleword_fprv2si (dest, src));
4418 else if (!TARGET_64BIT && GET_MODE (dest) == V4HImode)
4419 emit_insn (gen_move_doubleword_fprv4hi (dest, src));
4420 else if (!TARGET_64BIT && GET_MODE (dest) == V8QImode)
4421 emit_insn (gen_move_doubleword_fprv8qi (dest, src));
4422 else if (TARGET_64BIT && GET_MODE (dest) == TFmode)
4423 emit_insn (gen_move_doubleword_fprtf (dest, src));
4427 else if (REG_P (dest) && REGNO (dest) == MD_REG_FIRST)
4429 low_dest = mips_subword (dest, false);
4430 mips_emit_move (low_dest, mips_subword (src, false));
4432 emit_insn (gen_mthidi_ti (dest, mips_subword (src, true), low_dest));
4434 emit_insn (gen_mthisi_di (dest, mips_subword (src, true), low_dest));
4436 else if (REG_P (src) && REGNO (src) == MD_REG_FIRST)
4438 mips_emit_move (mips_subword (dest, false), mips_subword (src, false));
4440 emit_insn (gen_mfhidi_ti (mips_subword (dest, true), src));
4442 emit_insn (gen_mfhisi_di (mips_subword (dest, true), src));
4446 /* The operation can be split into two normal moves. Decide in
4447 which order to do them. */
4448 low_dest = mips_subword (dest, false);
4449 if (REG_P (low_dest)
4450 && reg_overlap_mentioned_p (low_dest, src))
4452 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4453 mips_emit_move (low_dest, mips_subword (src, false));
4457 mips_emit_move (low_dest, mips_subword (src, false));
4458 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4463 /* Return the split type for instruction INSN. */
4465 static enum mips_split_type
4466 mips_insn_split_type (rtx insn)
4468 basic_block bb = BLOCK_FOR_INSN (insn);
4471 if (optimize_bb_for_speed_p (bb))
4472 return SPLIT_FOR_SPEED;
4474 return SPLIT_FOR_SIZE;
4476 /* Once CFG information has been removed, we should trust the optimization
4477 decisions made by previous passes and only split where necessary. */
4478 return SPLIT_IF_NECESSARY;
4481 /* Return true if a move from SRC to DEST in INSN should be split. */
4484 mips_split_move_insn_p (rtx dest, rtx src, rtx insn)
4486 return mips_split_move_p (dest, src, mips_insn_split_type (insn));
4489 /* Split a move from SRC to DEST in INSN, given that mips_split_move_insn_p
4493 mips_split_move_insn (rtx dest, rtx src, rtx insn)
4495 mips_split_move (dest, src, mips_insn_split_type (insn));
4498 /* Return the appropriate instructions to move SRC into DEST. Assume
4499 that SRC is operand 1 and DEST is operand 0. */
4502 mips_output_move (rtx dest, rtx src)
4504 enum rtx_code dest_code, src_code;
4505 enum machine_mode mode;
4506 enum mips_symbol_type symbol_type;
4509 dest_code = GET_CODE (dest);
4510 src_code = GET_CODE (src);
4511 mode = GET_MODE (dest);
4512 dbl_p = (GET_MODE_SIZE (mode) == 8);
4514 if (mips_split_move_p (dest, src, SPLIT_IF_NECESSARY))
4517 if ((src_code == REG && GP_REG_P (REGNO (src)))
4518 || (!TARGET_MIPS16 && src == CONST0_RTX (mode)))
4520 if (dest_code == REG)
4522 if (GP_REG_P (REGNO (dest)))
4523 return "move\t%0,%z1";
4525 if (mips_mult_move_p (dest, src, SPLIT_IF_NECESSARY))
4527 if (ISA_HAS_DSP_MULT)
4528 return "mult\t%q0,%.,%.";
4530 return "mult\t%.,%.";
4533 /* Moves to HI are handled by special .md insns. */
4534 if (REGNO (dest) == LO_REGNUM)
4537 if (DSP_ACC_REG_P (REGNO (dest)))
4539 static char retval[] = "mt__\t%z1,%q0";
4541 retval[2] = reg_names[REGNO (dest)][4];
4542 retval[3] = reg_names[REGNO (dest)][5];
4546 if (FP_REG_P (REGNO (dest)))
4547 return dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
4549 if (ALL_COP_REG_P (REGNO (dest)))
4551 static char retval[] = "dmtc_\t%z1,%0";
4553 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4554 return dbl_p ? retval : retval + 1;
4557 if (dest_code == MEM)
4558 switch (GET_MODE_SIZE (mode))
4560 case 1: return "sb\t%z1,%0";
4561 case 2: return "sh\t%z1,%0";
4562 case 4: return "sw\t%z1,%0";
4563 case 8: return "sd\t%z1,%0";
4566 if (dest_code == REG && GP_REG_P (REGNO (dest)))
4568 if (src_code == REG)
4570 /* Moves from HI are handled by special .md insns. */
4571 if (REGNO (src) == LO_REGNUM)
4573 /* When generating VR4120 or VR4130 code, we use MACC and
4574 DMACC instead of MFLO. This avoids both the normal
4575 MIPS III HI/LO hazards and the errata related to
4578 return dbl_p ? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
4582 if (DSP_ACC_REG_P (REGNO (src)))
4584 static char retval[] = "mf__\t%0,%q1";
4586 retval[2] = reg_names[REGNO (src)][4];
4587 retval[3] = reg_names[REGNO (src)][5];
4591 if (FP_REG_P (REGNO (src)))
4592 return dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
4594 if (ALL_COP_REG_P (REGNO (src)))
4596 static char retval[] = "dmfc_\t%0,%1";
4598 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4599 return dbl_p ? retval : retval + 1;
4603 if (src_code == MEM)
4604 switch (GET_MODE_SIZE (mode))
4606 case 1: return "lbu\t%0,%1";
4607 case 2: return "lhu\t%0,%1";
4608 case 4: return "lw\t%0,%1";
4609 case 8: return "ld\t%0,%1";
4612 if (src_code == CONST_INT)
4614 /* Don't use the X format for the operand itself, because that
4615 will give out-of-range numbers for 64-bit hosts and 32-bit
4618 return "li\t%0,%1\t\t\t# %X1";
4620 if (SMALL_OPERAND_UNSIGNED (INTVAL (src)))
4623 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src)))
4627 if (src_code == HIGH)
4628 return TARGET_MIPS16 ? "#" : "lui\t%0,%h1";
4630 if (CONST_GP_P (src))
4631 return "move\t%0,%1";
4633 if (mips_symbolic_constant_p (src, SYMBOL_CONTEXT_LEA, &symbol_type)
4634 && mips_lo_relocs[symbol_type] != 0)
4636 /* A signed 16-bit constant formed by applying a relocation
4637 operator to a symbolic address. */
4638 gcc_assert (!mips_split_p[symbol_type]);
4639 return "li\t%0,%R1";
4642 if (symbolic_operand (src, VOIDmode))
4644 gcc_assert (TARGET_MIPS16
4645 ? TARGET_MIPS16_TEXT_LOADS
4646 : !TARGET_EXPLICIT_RELOCS);
4647 return dbl_p ? "dla\t%0,%1" : "la\t%0,%1";
4650 if (src_code == REG && FP_REG_P (REGNO (src)))
4652 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4654 if (GET_MODE (dest) == V2SFmode)
4655 return "mov.ps\t%0,%1";
4657 return dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1";
4660 if (dest_code == MEM)
4661 return dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0";
4663 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4665 if (src_code == MEM)
4666 return dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1";
4668 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
4670 static char retval[] = "l_c_\t%0,%1";
4672 retval[1] = (dbl_p ? 'd' : 'w');
4673 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4676 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
4678 static char retval[] = "s_c_\t%1,%0";
4680 retval[1] = (dbl_p ? 'd' : 'w');
4681 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4687 /* Return true if CMP1 is a suitable second operand for integer ordering
4688 test CODE. See also the *sCC patterns in mips.md. */
4691 mips_int_order_operand_ok_p (enum rtx_code code, rtx cmp1)
4697 return reg_or_0_operand (cmp1, VOIDmode);
4701 return !TARGET_MIPS16 && cmp1 == const1_rtx;
4705 return arith_operand (cmp1, VOIDmode);
4708 return sle_operand (cmp1, VOIDmode);
4711 return sleu_operand (cmp1, VOIDmode);
4718 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4719 integer ordering test *CODE, or if an equivalent combination can
4720 be formed by adjusting *CODE and *CMP1. When returning true, update
4721 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4725 mips_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1,
4726 enum machine_mode mode)
4728 HOST_WIDE_INT plus_one;
4730 if (mips_int_order_operand_ok_p (*code, *cmp1))
4733 if (CONST_INT_P (*cmp1))
4737 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4738 if (INTVAL (*cmp1) < plus_one)
4741 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4747 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4751 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4762 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4763 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4764 is nonnull, it's OK to set TARGET to the inverse of the result and
4765 flip *INVERT_PTR instead. */
4768 mips_emit_int_order_test (enum rtx_code code, bool *invert_ptr,
4769 rtx target, rtx cmp0, rtx cmp1)
4771 enum machine_mode mode;
4773 /* First see if there is a MIPS instruction that can do this operation.
4774 If not, try doing the same for the inverse operation. If that also
4775 fails, force CMP1 into a register and try again. */
4776 mode = GET_MODE (cmp0);
4777 if (mips_canonicalize_int_order_test (&code, &cmp1, mode))
4778 mips_emit_binary (code, target, cmp0, cmp1);
4781 enum rtx_code inv_code = reverse_condition (code);
4782 if (!mips_canonicalize_int_order_test (&inv_code, &cmp1, mode))
4784 cmp1 = force_reg (mode, cmp1);
4785 mips_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1);
4787 else if (invert_ptr == 0)
4791 inv_target = mips_force_binary (GET_MODE (target),
4792 inv_code, cmp0, cmp1);
4793 mips_emit_binary (XOR, target, inv_target, const1_rtx);
4797 *invert_ptr = !*invert_ptr;
4798 mips_emit_binary (inv_code, target, cmp0, cmp1);
4803 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4804 The register will have the same mode as CMP0. */
4807 mips_zero_if_equal (rtx cmp0, rtx cmp1)
4809 if (cmp1 == const0_rtx)
4812 if (uns_arith_operand (cmp1, VOIDmode))
4813 return expand_binop (GET_MODE (cmp0), xor_optab,
4814 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4816 return expand_binop (GET_MODE (cmp0), sub_optab,
4817 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4820 /* Convert *CODE into a code that can be used in a floating-point
4821 scc instruction (C.cond.fmt). Return true if the values of
4822 the condition code registers will be inverted, with 0 indicating
4823 that the condition holds. */
4826 mips_reversed_fp_cond (enum rtx_code *code)
4833 *code = reverse_condition_maybe_unordered (*code);
4841 /* Allocate a floating-point condition-code register of mode MODE.
4843 These condition code registers are used for certain kinds
4844 of compound operation, such as compare and branches, vconds,
4845 and built-in functions. At expand time, their use is entirely
4846 controlled by MIPS-specific code and is entirely internal
4847 to these compound operations.
4849 We could (and did in the past) expose condition-code values
4850 as pseudo registers and leave the register allocator to pick
4851 appropriate registers. The problem is that it is not practically
4852 possible for the rtl optimizers to guarantee that no spills will
4853 be needed, even when AVOID_CCMODE_COPIES is defined. We would
4854 therefore need spill and reload sequences to handle the worst case.
4856 Although such sequences do exist, they are very expensive and are
4857 not something we'd want to use. This is especially true of CCV2 and
4858 CCV4, where all the shuffling would greatly outweigh whatever benefit
4859 the vectorization itself provides.
4861 The main benefit of having more than one condition-code register
4862 is to allow the pipelining of operations, especially those involving
4863 comparisons and conditional moves. We don't really expect the
4864 registers to be live for long periods, and certainly never want
4865 them to be live across calls.
4867 Also, there should be no penalty attached to using all the available
4868 registers. They are simply bits in the same underlying FPU control
4871 We therefore expose the hardware registers from the outset and use
4872 a simple round-robin allocation scheme. */
4875 mips_allocate_fcc (enum machine_mode mode)
4877 unsigned int regno, count;
4879 gcc_assert (TARGET_HARD_FLOAT && ISA_HAS_8CC);
4883 else if (mode == CCV2mode)
4885 else if (mode == CCV4mode)
4890 cfun->machine->next_fcc += -cfun->machine->next_fcc & (count - 1);
4891 if (cfun->machine->next_fcc > ST_REG_LAST - ST_REG_FIRST)
4892 cfun->machine->next_fcc = 0;
4893 regno = ST_REG_FIRST + cfun->machine->next_fcc;
4894 cfun->machine->next_fcc += count;
4895 return gen_rtx_REG (mode, regno);
4898 /* Convert a comparison into something that can be used in a branch or
4899 conditional move. On entry, *OP0 and *OP1 are the values being
4900 compared and *CODE is the code used to compare them.
4902 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
4903 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
4904 otherwise any standard branch condition can be used. The standard branch
4907 - EQ or NE between two registers.
4908 - any comparison between a register and zero. */
4911 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
4916 if (GET_MODE_CLASS (GET_MODE (*op0)) == MODE_INT)
4918 if (!need_eq_ne_p && *op1 == const0_rtx)
4920 else if (*code == EQ || *code == NE)
4924 *op0 = mips_zero_if_equal (cmp_op0, cmp_op1);
4928 *op1 = force_reg (GET_MODE (cmp_op0), cmp_op1);
4932 /* The comparison needs a separate scc instruction. Store the
4933 result of the scc in *OP0 and compare it against zero. */
4934 bool invert = false;
4935 *op0 = gen_reg_rtx (GET_MODE (cmp_op0));
4936 mips_emit_int_order_test (*code, &invert, *op0, cmp_op0, cmp_op1);
4937 *code = (invert ? EQ : NE);
4941 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0)))
4943 *op0 = gen_rtx_REG (CCDSPmode, CCDSP_CC_REGNUM);
4944 mips_emit_binary (*code, *op0, cmp_op0, cmp_op1);
4950 enum rtx_code cmp_code;
4952 /* Floating-point tests use a separate C.cond.fmt comparison to
4953 set a condition code register. The branch or conditional move
4954 will then compare that register against zero.
4956 Set CMP_CODE to the code of the comparison instruction and
4957 *CODE to the code that the branch or move should use. */
4959 *code = mips_reversed_fp_cond (&cmp_code) ? EQ : NE;
4961 ? mips_allocate_fcc (CCmode)
4962 : gen_rtx_REG (CCmode, FPSW_REGNUM));
4964 mips_emit_binary (cmp_code, *op0, cmp_op0, cmp_op1);
4968 /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2]
4969 and OPERAND[3]. Store the result in OPERANDS[0].
4971 On 64-bit targets, the mode of the comparison and target will always be
4972 SImode, thus possibly narrower than that of the comparison's operands. */
4975 mips_expand_scc (rtx operands[])
4977 rtx target = operands[0];
4978 enum rtx_code code = GET_CODE (operands[1]);
4979 rtx op0 = operands[2];
4980 rtx op1 = operands[3];
4982 gcc_assert (GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT);
4984 if (code == EQ || code == NE)
4987 && reg_imm10_operand (op1, GET_MODE (op1)))
4988 mips_emit_binary (code, target, op0, op1);
4991 rtx zie = mips_zero_if_equal (op0, op1);
4992 mips_emit_binary (code, target, zie, const0_rtx);
4996 mips_emit_int_order_test (code, 0, target, op0, op1);
4999 /* Compare OPERANDS[1] with OPERANDS[2] using comparison code
5000 CODE and jump to OPERANDS[3] if the condition holds. */
5003 mips_expand_conditional_branch (rtx *operands)
5005 enum rtx_code code = GET_CODE (operands[0]);
5006 rtx op0 = operands[1];
5007 rtx op1 = operands[2];
5010 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
5011 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
5012 emit_jump_insn (gen_condjump (condition, operands[3]));
5017 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
5018 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
5021 mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
5022 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
5027 reversed_p = mips_reversed_fp_cond (&cond);
5028 cmp_result = mips_allocate_fcc (CCV2mode);
5029 emit_insn (gen_scc_ps (cmp_result,
5030 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
5032 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
5035 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
5039 /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0]
5040 if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
5043 mips_expand_conditional_move (rtx *operands)
5046 enum rtx_code code = GET_CODE (operands[1]);
5047 rtx op0 = XEXP (operands[1], 0);
5048 rtx op1 = XEXP (operands[1], 1);
5050 mips_emit_compare (&code, &op0, &op1, true);
5051 cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
5052 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
5053 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), cond,
5054 operands[2], operands[3])));
5057 /* Perform the comparison in COMPARISON, then trap if the condition holds. */
5060 mips_expand_conditional_trap (rtx comparison)
5063 enum machine_mode mode;
5066 /* MIPS conditional trap instructions don't have GT or LE flavors,
5067 so we must swap the operands and convert to LT and GE respectively. */
5068 code = GET_CODE (comparison);
5075 code = swap_condition (code);
5076 op0 = XEXP (comparison, 1);
5077 op1 = XEXP (comparison, 0);
5081 op0 = XEXP (comparison, 0);
5082 op1 = XEXP (comparison, 1);
5086 mode = GET_MODE (XEXP (comparison, 0));
5087 op0 = force_reg (mode, op0);
5088 if (!arith_operand (op1, mode))
5089 op1 = force_reg (mode, op1);
5091 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
5092 gen_rtx_fmt_ee (code, mode, op0, op1),
5096 /* Initialize *CUM for a call to a function of type FNTYPE. */
5099 mips_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype)
5101 memset (cum, 0, sizeof (*cum));
5102 cum->prototype = (fntype && prototype_p (fntype));
5103 cum->gp_reg_found = (cum->prototype && stdarg_p (fntype));
5106 /* Fill INFO with information about a single argument. CUM is the
5107 cumulative state for earlier arguments. MODE is the mode of this
5108 argument and TYPE is its type (if known). NAMED is true if this
5109 is a named (fixed) argument rather than a variable one. */
5112 mips_get_arg_info (struct mips_arg_info *info, const CUMULATIVE_ARGS *cum,
5113 enum machine_mode mode, const_tree type, bool named)
5115 bool doubleword_aligned_p;
5116 unsigned int num_bytes, num_words, max_regs;
5118 /* Work out the size of the argument. */
5119 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
5120 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5122 /* Decide whether it should go in a floating-point register, assuming
5123 one is free. Later code checks for availability.
5125 The checks against UNITS_PER_FPVALUE handle the soft-float and
5126 single-float cases. */
5130 /* The EABI conventions have traditionally been defined in terms
5131 of TYPE_MODE, regardless of the actual type. */
5132 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
5133 || mode == V2SFmode)
5134 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
5139 /* Only leading floating-point scalars are passed in
5140 floating-point registers. We also handle vector floats the same
5141 say, which is OK because they are not covered by the standard ABI. */
5142 info->fpr_p = (!cum->gp_reg_found
5143 && cum->arg_number < 2
5145 || SCALAR_FLOAT_TYPE_P (type)
5146 || VECTOR_FLOAT_TYPE_P (type))
5147 && (GET_MODE_CLASS (mode) == MODE_FLOAT
5148 || mode == V2SFmode)
5149 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
5154 /* Scalar, complex and vector floating-point types are passed in
5155 floating-point registers, as long as this is a named rather
5156 than a variable argument. */
5157 info->fpr_p = (named
5158 && (type == 0 || FLOAT_TYPE_P (type))
5159 && (GET_MODE_CLASS (mode) == MODE_FLOAT
5160 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5161 || mode == V2SFmode)
5162 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
5164 /* ??? According to the ABI documentation, the real and imaginary
5165 parts of complex floats should be passed in individual registers.
5166 The real and imaginary parts of stack arguments are supposed
5167 to be contiguous and there should be an extra word of padding
5170 This has two problems. First, it makes it impossible to use a
5171 single "void *" va_list type, since register and stack arguments
5172 are passed differently. (At the time of writing, MIPSpro cannot
5173 handle complex float varargs correctly.) Second, it's unclear
5174 what should happen when there is only one register free.
5176 For now, we assume that named complex floats should go into FPRs
5177 if there are two FPRs free, otherwise they should be passed in the
5178 same way as a struct containing two floats. */
5180 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5181 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
5183 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
5184 info->fpr_p = false;
5194 /* See whether the argument has doubleword alignment. */
5195 doubleword_aligned_p = (mips_function_arg_boundary (mode, type)
5198 /* Set REG_OFFSET to the register count we're interested in.
5199 The EABI allocates the floating-point registers separately,
5200 but the other ABIs allocate them like integer registers. */
5201 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
5205 /* Advance to an even register if the argument is doubleword-aligned. */
5206 if (doubleword_aligned_p)
5207 info->reg_offset += info->reg_offset & 1;
5209 /* Work out the offset of a stack argument. */
5210 info->stack_offset = cum->stack_words;
5211 if (doubleword_aligned_p)
5212 info->stack_offset += info->stack_offset & 1;
5214 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
5216 /* Partition the argument between registers and stack. */
5217 info->reg_words = MIN (num_words, max_regs);
5218 info->stack_words = num_words - info->reg_words;
5221 /* INFO describes a register argument that has the normal format for the
5222 argument's mode. Return the register it uses, assuming that FPRs are
5223 available if HARD_FLOAT_P. */
5226 mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p)
5228 if (!info->fpr_p || !hard_float_p)
5229 return GP_ARG_FIRST + info->reg_offset;
5230 else if (mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info->reg_offset > 0)
5231 /* In o32, the second argument is always passed in $f14
5232 for TARGET_DOUBLE_FLOAT, regardless of whether the
5233 first argument was a word or doubleword. */
5234 return FP_ARG_FIRST + 2;
5236 return FP_ARG_FIRST + info->reg_offset;
5239 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
5242 mips_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED)
5244 return !TARGET_OLDABI;
5247 /* Implement TARGET_FUNCTION_ARG. */
5250 mips_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
5251 const_tree type, bool named)
5253 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
5254 struct mips_arg_info info;
5256 /* We will be called with a mode of VOIDmode after the last argument
5257 has been seen. Whatever we return will be passed to the call expander.
5258 If we need a MIPS16 fp_code, return a REG with the code stored as
5260 if (mode == VOIDmode)
5262 if (TARGET_MIPS16 && cum->fp_code != 0)
5263 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
5268 mips_get_arg_info (&info, cum, mode, type, named);
5270 /* Return straight away if the whole argument is passed on the stack. */
5271 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
5274 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
5275 contains a double in its entirety, then that 64-bit chunk is passed
5276 in a floating-point register. */
5278 && TARGET_HARD_FLOAT
5281 && TREE_CODE (type) == RECORD_TYPE
5282 && TYPE_SIZE_UNIT (type)
5283 && tree_fits_uhwi_p (TYPE_SIZE_UNIT (type)))
5287 /* First check to see if there is any such field. */
5288 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
5289 if (TREE_CODE (field) == FIELD_DECL
5290 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
5291 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
5292 && tree_fits_shwi_p (bit_position (field))
5293 && int_bit_position (field) % BITS_PER_WORD == 0)
5298 /* Now handle the special case by returning a PARALLEL
5299 indicating where each 64-bit chunk goes. INFO.REG_WORDS
5300 chunks are passed in registers. */
5302 HOST_WIDE_INT bitpos;
5305 /* assign_parms checks the mode of ENTRY_PARM, so we must
5306 use the actual mode here. */
5307 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
5310 field = TYPE_FIELDS (type);
5311 for (i = 0; i < info.reg_words; i++)
5315 for (; field; field = DECL_CHAIN (field))
5316 if (TREE_CODE (field) == FIELD_DECL
5317 && int_bit_position (field) >= bitpos)
5321 && int_bit_position (field) == bitpos
5322 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
5323 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
5324 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
5326 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
5329 = gen_rtx_EXPR_LIST (VOIDmode, reg,
5330 GEN_INT (bitpos / BITS_PER_UNIT));
5332 bitpos += BITS_PER_WORD;
5338 /* Handle the n32/n64 conventions for passing complex floating-point
5339 arguments in FPR pairs. The real part goes in the lower register
5340 and the imaginary part goes in the upper register. */
5343 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5346 enum machine_mode inner;
5349 inner = GET_MODE_INNER (mode);
5350 regno = FP_ARG_FIRST + info.reg_offset;
5351 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
5353 /* Real part in registers, imaginary part on stack. */
5354 gcc_assert (info.stack_words == info.reg_words);
5355 return gen_rtx_REG (inner, regno);
5359 gcc_assert (info.stack_words == 0);
5360 real = gen_rtx_EXPR_LIST (VOIDmode,
5361 gen_rtx_REG (inner, regno),
5363 imag = gen_rtx_EXPR_LIST (VOIDmode,
5365 regno + info.reg_words / 2),
5366 GEN_INT (GET_MODE_SIZE (inner)));
5367 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
5371 return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT));
5374 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
5377 mips_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
5378 const_tree type, bool named)
5380 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
5381 struct mips_arg_info info;
5383 mips_get_arg_info (&info, cum, mode, type, named);
5386 cum->gp_reg_found = true;
5388 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
5389 an explanation of what this code does. It assumes that we're using
5390 either the o32 or the o64 ABI, both of which pass at most 2 arguments
5392 if (cum->arg_number < 2 && info.fpr_p)
5393 cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2);
5395 /* Advance the register count. This has the effect of setting
5396 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
5397 argument required us to skip the final GPR and pass the whole
5398 argument on the stack. */
5399 if (mips_abi != ABI_EABI || !info.fpr_p)
5400 cum->num_gprs = info.reg_offset + info.reg_words;
5401 else if (info.reg_words > 0)
5402 cum->num_fprs += MAX_FPRS_PER_FMT;
5404 /* Advance the stack word count. */
5405 if (info.stack_words > 0)
5406 cum->stack_words = info.stack_offset + info.stack_words;
5411 /* Implement TARGET_ARG_PARTIAL_BYTES. */
5414 mips_arg_partial_bytes (cumulative_args_t cum,
5415 enum machine_mode mode, tree type, bool named)
5417 struct mips_arg_info info;
5419 mips_get_arg_info (&info, get_cumulative_args (cum), mode, type, named);
5420 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
5423 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
5424 least PARM_BOUNDARY bits of alignment, but will be given anything up
5425 to STACK_BOUNDARY bits if the type requires it. */
5428 mips_function_arg_boundary (enum machine_mode mode, const_tree type)
5430 unsigned int alignment;
5432 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
5433 if (alignment < PARM_BOUNDARY)
5434 alignment = PARM_BOUNDARY;
5435 if (alignment > STACK_BOUNDARY)
5436 alignment = STACK_BOUNDARY;
5440 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
5441 upward rather than downward. In other words, return true if the
5442 first byte of the stack slot has useful data, false if the last
5446 mips_pad_arg_upward (enum machine_mode mode, const_tree type)
5448 /* On little-endian targets, the first byte of every stack argument
5449 is passed in the first byte of the stack slot. */
5450 if (!BYTES_BIG_ENDIAN)
5453 /* Otherwise, integral types are padded downward: the last byte of a
5454 stack argument is passed in the last byte of the stack slot. */
5456 ? (INTEGRAL_TYPE_P (type)
5457 || POINTER_TYPE_P (type)
5458 || FIXED_POINT_TYPE_P (type))
5459 : (SCALAR_INT_MODE_P (mode)
5460 || ALL_SCALAR_FIXED_POINT_MODE_P (mode)))
5463 /* Big-endian o64 pads floating-point arguments downward. */
5464 if (mips_abi == ABI_O64)
5465 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
5468 /* Other types are padded upward for o32, o64, n32 and n64. */
5469 if (mips_abi != ABI_EABI)
5472 /* Arguments smaller than a stack slot are padded downward. */
5473 if (mode != BLKmode)
5474 return GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY;
5476 return int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT);
5479 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
5480 if the least significant byte of the register has useful data. Return
5481 the opposite if the most significant byte does. */
5484 mips_pad_reg_upward (enum machine_mode mode, tree type)
5486 /* No shifting is required for floating-point arguments. */
5487 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
5488 return !BYTES_BIG_ENDIAN;
5490 /* Otherwise, apply the same padding to register arguments as we do
5491 to stack arguments. */
5492 return mips_pad_arg_upward (mode, type);
5495 /* Return nonzero when an argument must be passed by reference. */
5498 mips_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
5499 enum machine_mode mode, const_tree type,
5500 bool named ATTRIBUTE_UNUSED)
5502 if (mips_abi == ABI_EABI)
5506 /* ??? How should SCmode be handled? */
5507 if (mode == DImode || mode == DFmode
5508 || mode == DQmode || mode == UDQmode
5509 || mode == DAmode || mode == UDAmode)
5512 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
5513 return size == -1 || size > UNITS_PER_WORD;
5517 /* If we have a variable-sized parameter, we have no choice. */
5518 return targetm.calls.must_pass_in_stack (mode, type);
5522 /* Implement TARGET_CALLEE_COPIES. */
5525 mips_callee_copies (cumulative_args_t cum ATTRIBUTE_UNUSED,
5526 enum machine_mode mode ATTRIBUTE_UNUSED,
5527 const_tree type ATTRIBUTE_UNUSED, bool named)
5529 return mips_abi == ABI_EABI && named;
5532 /* See whether VALTYPE is a record whose fields should be returned in
5533 floating-point registers. If so, return the number of fields and
5534 list them in FIELDS (which should have two elements). Return 0
5537 For n32 & n64, a structure with one or two fields is returned in
5538 floating-point registers as long as every field has a floating-point
5542 mips_fpr_return_fields (const_tree valtype, tree *fields)
5550 if (TREE_CODE (valtype) != RECORD_TYPE)
5554 for (field = TYPE_FIELDS (valtype); field != 0; field = DECL_CHAIN (field))
5556 if (TREE_CODE (field) != FIELD_DECL)
5559 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)))
5565 fields[i++] = field;
5570 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
5571 a value in the most significant part of $2/$3 if:
5573 - the target is big-endian;
5575 - the value has a structure or union type (we generalize this to
5576 cover aggregates from other languages too); and
5578 - the structure is not returned in floating-point registers. */
5581 mips_return_in_msb (const_tree valtype)
5585 return (TARGET_NEWABI
5586 && TARGET_BIG_ENDIAN
5587 && AGGREGATE_TYPE_P (valtype)
5588 && mips_fpr_return_fields (valtype, fields) == 0);
5591 /* Return true if the function return value MODE will get returned in a
5592 floating-point register. */
5595 mips_return_mode_in_fpr_p (enum machine_mode mode)
5597 return ((GET_MODE_CLASS (mode) == MODE_FLOAT
5599 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5600 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE);
5603 /* Return the representation of an FPR return register when the
5604 value being returned in FP_RETURN has mode VALUE_MODE and the
5605 return type itself has mode TYPE_MODE. On NewABI targets,
5606 the two modes may be different for structures like:
5608 struct __attribute__((packed)) foo { float f; }
5610 where we return the SFmode value of "f" in FP_RETURN, but where
5611 the structure itself has mode BLKmode. */
5614 mips_return_fpr_single (enum machine_mode type_mode,
5615 enum machine_mode value_mode)
5619 x = gen_rtx_REG (value_mode, FP_RETURN);
5620 if (type_mode != value_mode)
5622 x = gen_rtx_EXPR_LIST (VOIDmode, x, const0_rtx);
5623 x = gen_rtx_PARALLEL (type_mode, gen_rtvec (1, x));
5628 /* Return a composite value in a pair of floating-point registers.
5629 MODE1 and OFFSET1 are the mode and byte offset for the first value,
5630 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
5633 For n32 & n64, $f0 always holds the first value and $f2 the second.
5634 Otherwise the values are packed together as closely as possible. */
5637 mips_return_fpr_pair (enum machine_mode mode,
5638 enum machine_mode mode1, HOST_WIDE_INT offset1,
5639 enum machine_mode mode2, HOST_WIDE_INT offset2)
5643 inc = (TARGET_NEWABI ? 2 : MAX_FPRS_PER_FMT);
5644 return gen_rtx_PARALLEL
5647 gen_rtx_EXPR_LIST (VOIDmode,
5648 gen_rtx_REG (mode1, FP_RETURN),
5650 gen_rtx_EXPR_LIST (VOIDmode,
5651 gen_rtx_REG (mode2, FP_RETURN + inc),
5652 GEN_INT (offset2))));
5656 /* Implement TARGET_FUNCTION_VALUE and TARGET_LIBCALL_VALUE.
5657 For normal calls, VALTYPE is the return type and MODE is VOIDmode.
5658 For libcalls, VALTYPE is null and MODE is the mode of the return value. */
5661 mips_function_value_1 (const_tree valtype, const_tree fn_decl_or_type,
5662 enum machine_mode mode)
5670 if (fn_decl_or_type && DECL_P (fn_decl_or_type))
5671 func = fn_decl_or_type;
5675 mode = TYPE_MODE (valtype);
5676 unsigned_p = TYPE_UNSIGNED (valtype);
5678 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
5679 return values, promote the mode here too. */
5680 mode = promote_function_mode (valtype, mode, &unsigned_p, func, 1);
5682 /* Handle structures whose fields are returned in $f0/$f2. */
5683 switch (mips_fpr_return_fields (valtype, fields))
5686 return mips_return_fpr_single (mode,
5687 TYPE_MODE (TREE_TYPE (fields[0])));
5690 return mips_return_fpr_pair (mode,
5691 TYPE_MODE (TREE_TYPE (fields[0])),
5692 int_byte_position (fields[0]),
5693 TYPE_MODE (TREE_TYPE (fields[1])),
5694 int_byte_position (fields[1]));
5697 /* If a value is passed in the most significant part of a register, see
5698 whether we have to round the mode up to a whole number of words. */
5699 if (mips_return_in_msb (valtype))
5701 HOST_WIDE_INT size = int_size_in_bytes (valtype);
5702 if (size % UNITS_PER_WORD != 0)
5704 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
5705 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
5709 /* For EABI, the class of return register depends entirely on MODE.
5710 For example, "struct { some_type x; }" and "union { some_type x; }"
5711 are returned in the same way as a bare "some_type" would be.
5712 Other ABIs only use FPRs for scalar, complex or vector types. */
5713 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
5714 return gen_rtx_REG (mode, GP_RETURN);
5719 /* Handle long doubles for n32 & n64. */
5721 return mips_return_fpr_pair (mode,
5723 DImode, GET_MODE_SIZE (mode) / 2);
5725 if (mips_return_mode_in_fpr_p (mode))
5727 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5728 return mips_return_fpr_pair (mode,
5729 GET_MODE_INNER (mode), 0,
5730 GET_MODE_INNER (mode),
5731 GET_MODE_SIZE (mode) / 2);
5733 return gen_rtx_REG (mode, FP_RETURN);
5737 return gen_rtx_REG (mode, GP_RETURN);
5740 /* Implement TARGET_FUNCTION_VALUE. */
5743 mips_function_value (const_tree valtype, const_tree fn_decl_or_type,
5744 bool outgoing ATTRIBUTE_UNUSED)
5746 return mips_function_value_1 (valtype, fn_decl_or_type, VOIDmode);
5749 /* Implement TARGET_LIBCALL_VALUE. */
5752 mips_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
5754 return mips_function_value_1 (NULL_TREE, NULL_TREE, mode);
5757 /* Implement TARGET_FUNCTION_VALUE_REGNO_P.
5759 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
5760 Currently, R2 and F0 are only implemented here (C has no complex type). */
5763 mips_function_value_regno_p (const unsigned int regno)
5765 if (regno == GP_RETURN
5766 || regno == FP_RETURN
5767 || (LONG_DOUBLE_TYPE_SIZE == 128
5768 && FP_RETURN != GP_RETURN
5769 && regno == FP_RETURN + 2))
5775 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
5776 all BLKmode objects are returned in memory. Under the n32, n64
5777 and embedded ABIs, small structures are returned in a register.
5778 Objects with varying size must still be returned in memory, of
5782 mips_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
5784 return (TARGET_OLDABI
5785 ? TYPE_MODE (type) == BLKmode
5786 : !IN_RANGE (int_size_in_bytes (type), 0, 2 * UNITS_PER_WORD));
5789 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
5792 mips_setup_incoming_varargs (cumulative_args_t cum, enum machine_mode mode,
5793 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5796 CUMULATIVE_ARGS local_cum;
5797 int gp_saved, fp_saved;
5799 /* The caller has advanced CUM up to, but not beyond, the last named
5800 argument. Advance a local copy of CUM past the last "real" named
5801 argument, to find out how many registers are left over. */
5802 local_cum = *get_cumulative_args (cum);
5803 mips_function_arg_advance (pack_cumulative_args (&local_cum), mode, type,
5806 /* Found out how many registers we need to save. */
5807 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
5808 fp_saved = (EABI_FLOAT_VARARGS_P
5809 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
5818 ptr = plus_constant (Pmode, virtual_incoming_args_rtx,
5819 REG_PARM_STACK_SPACE (cfun->decl)
5820 - gp_saved * UNITS_PER_WORD);
5821 mem = gen_frame_mem (BLKmode, ptr);
5822 set_mem_alias_set (mem, get_varargs_alias_set ());
5824 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
5829 /* We can't use move_block_from_reg, because it will use
5831 enum machine_mode mode;
5834 /* Set OFF to the offset from virtual_incoming_args_rtx of
5835 the first float register. The FP save area lies below
5836 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
5837 off = (-gp_saved * UNITS_PER_WORD) & -UNITS_PER_FPVALUE;
5838 off -= fp_saved * UNITS_PER_FPREG;
5840 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
5842 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS;
5843 i += MAX_FPRS_PER_FMT)
5847 ptr = plus_constant (Pmode, virtual_incoming_args_rtx, off);
5848 mem = gen_frame_mem (mode, ptr);
5849 set_mem_alias_set (mem, get_varargs_alias_set ());
5850 mips_emit_move (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
5851 off += UNITS_PER_HWFPVALUE;
5855 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
5856 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
5857 + fp_saved * UNITS_PER_FPREG);
5860 /* Implement TARGET_BUILTIN_VA_LIST. */
5863 mips_build_builtin_va_list (void)
5865 if (EABI_FLOAT_VARARGS_P)
5867 /* We keep 3 pointers, and two offsets.
5869 Two pointers are to the overflow area, which starts at the CFA.
5870 One of these is constant, for addressing into the GPR save area
5871 below it. The other is advanced up the stack through the
5874 The third pointer is to the bottom of the GPR save area.
5875 Since the FPR save area is just below it, we can address
5876 FPR slots off this pointer.
5878 We also keep two one-byte offsets, which are to be subtracted
5879 from the constant pointers to yield addresses in the GPR and
5880 FPR save areas. These are downcounted as float or non-float
5881 arguments are used, and when they get to zero, the argument
5882 must be obtained from the overflow region. */
5883 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
5886 record = lang_hooks.types.make_type (RECORD_TYPE);
5888 f_ovfl = build_decl (BUILTINS_LOCATION,
5889 FIELD_DECL, get_identifier ("__overflow_argptr"),
5891 f_gtop = build_decl (BUILTINS_LOCATION,
5892 FIELD_DECL, get_identifier ("__gpr_top"),
5894 f_ftop = build_decl (BUILTINS_LOCATION,
5895 FIELD_DECL, get_identifier ("__fpr_top"),
5897 f_goff = build_decl (BUILTINS_LOCATION,
5898 FIELD_DECL, get_identifier ("__gpr_offset"),
5899 unsigned_char_type_node);
5900 f_foff = build_decl (BUILTINS_LOCATION,
5901 FIELD_DECL, get_identifier ("__fpr_offset"),
5902 unsigned_char_type_node);
5903 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
5904 warn on every user file. */
5905 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
5906 array = build_array_type (unsigned_char_type_node,
5907 build_index_type (index));
5908 f_res = build_decl (BUILTINS_LOCATION,
5909 FIELD_DECL, get_identifier ("__reserved"), array);
5911 DECL_FIELD_CONTEXT (f_ovfl) = record;
5912 DECL_FIELD_CONTEXT (f_gtop) = record;
5913 DECL_FIELD_CONTEXT (f_ftop) = record;
5914 DECL_FIELD_CONTEXT (f_goff) = record;
5915 DECL_FIELD_CONTEXT (f_foff) = record;
5916 DECL_FIELD_CONTEXT (f_res) = record;
5918 TYPE_FIELDS (record) = f_ovfl;
5919 DECL_CHAIN (f_ovfl) = f_gtop;
5920 DECL_CHAIN (f_gtop) = f_ftop;
5921 DECL_CHAIN (f_ftop) = f_goff;
5922 DECL_CHAIN (f_goff) = f_foff;
5923 DECL_CHAIN (f_foff) = f_res;
5925 layout_type (record);
5929 /* Otherwise, we use 'void *'. */
5930 return ptr_type_node;
5933 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
5936 mips_va_start (tree valist, rtx nextarg)
5938 if (EABI_FLOAT_VARARGS_P)
5940 const CUMULATIVE_ARGS *cum;
5941 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5942 tree ovfl, gtop, ftop, goff, foff;
5944 int gpr_save_area_size;
5945 int fpr_save_area_size;
5948 cum = &crtl->args.info;
5950 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
5952 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
5954 f_ovfl = TYPE_FIELDS (va_list_type_node);
5955 f_gtop = DECL_CHAIN (f_ovfl);
5956 f_ftop = DECL_CHAIN (f_gtop);
5957 f_goff = DECL_CHAIN (f_ftop);
5958 f_foff = DECL_CHAIN (f_goff);
5960 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5962 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
5964 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
5966 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
5968 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
5971 /* Emit code to initialize OVFL, which points to the next varargs
5972 stack argument. CUM->STACK_WORDS gives the number of stack
5973 words used by named arguments. */
5974 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
5975 if (cum->stack_words > 0)
5976 t = fold_build_pointer_plus_hwi (t, cum->stack_words * UNITS_PER_WORD);
5977 t = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
5978 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5980 /* Emit code to initialize GTOP, the top of the GPR save area. */
5981 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
5982 t = build2 (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
5983 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5985 /* Emit code to initialize FTOP, the top of the FPR save area.
5986 This address is gpr_save_area_bytes below GTOP, rounded
5987 down to the next fp-aligned boundary. */
5988 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
5989 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
5990 fpr_offset &= -UNITS_PER_FPVALUE;
5992 t = fold_build_pointer_plus_hwi (t, -fpr_offset);
5993 t = build2 (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
5994 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5996 /* Emit code to initialize GOFF, the offset from GTOP of the
5997 next GPR argument. */
5998 t = build2 (MODIFY_EXPR, TREE_TYPE (goff), goff,
5999 build_int_cst (TREE_TYPE (goff), gpr_save_area_size));
6000 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6002 /* Likewise emit code to initialize FOFF, the offset from FTOP
6003 of the next FPR argument. */
6004 t = build2 (MODIFY_EXPR, TREE_TYPE (foff), foff,
6005 build_int_cst (TREE_TYPE (foff), fpr_save_area_size));
6006 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6010 nextarg = plus_constant (Pmode, nextarg, -cfun->machine->varargs_size);
6011 std_expand_builtin_va_start (valist, nextarg);
6015 /* Like std_gimplify_va_arg_expr, but apply alignment to zero-sized
6019 mips_std_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
6022 tree addr, t, type_size, rounded_size, valist_tmp;
6023 unsigned HOST_WIDE_INT align, boundary;
6026 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, false);
6028 type = build_pointer_type (type);
6030 align = PARM_BOUNDARY / BITS_PER_UNIT;
6031 boundary = targetm.calls.function_arg_boundary (TYPE_MODE (type), type);
6033 /* When we align parameter on stack for caller, if the parameter
6034 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
6035 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
6036 here with caller. */
6037 if (boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
6038 boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
6040 boundary /= BITS_PER_UNIT;
6042 /* Hoist the valist value into a temporary for the moment. */
6043 valist_tmp = get_initialized_tmp_var (valist, pre_p, NULL);
6045 /* va_list pointer is aligned to PARM_BOUNDARY. If argument actually
6046 requires greater alignment, we must perform dynamic alignment. */
6047 if (boundary > align)
6049 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
6050 fold_build_pointer_plus_hwi (valist_tmp, boundary - 1));
6051 gimplify_and_add (t, pre_p);
6053 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
6054 fold_build2 (BIT_AND_EXPR, TREE_TYPE (valist),
6056 build_int_cst (TREE_TYPE (valist), -boundary)));
6057 gimplify_and_add (t, pre_p);
6062 /* If the actual alignment is less than the alignment of the type,
6063 adjust the type accordingly so that we don't assume strict alignment
6064 when dereferencing the pointer. */
6065 boundary *= BITS_PER_UNIT;
6066 if (boundary < TYPE_ALIGN (type))
6068 type = build_variant_type_copy (type);
6069 TYPE_ALIGN (type) = boundary;
6072 /* Compute the rounded size of the type. */
6073 type_size = size_in_bytes (type);
6074 rounded_size = round_up (type_size, align);
6076 /* Reduce rounded_size so it's sharable with the postqueue. */
6077 gimplify_expr (&rounded_size, pre_p, post_p, is_gimple_val, fb_rvalue);
6081 if (PAD_VARARGS_DOWN && !integer_zerop (rounded_size))
6083 /* Small args are padded downward. */
6084 t = fold_build2_loc (input_location, GT_EXPR, sizetype,
6085 rounded_size, size_int (align));
6086 t = fold_build3 (COND_EXPR, sizetype, t, size_zero_node,
6087 size_binop (MINUS_EXPR, rounded_size, type_size));
6088 addr = fold_build_pointer_plus (addr, t);
6091 /* Compute new value for AP. */
6092 t = fold_build_pointer_plus (valist_tmp, rounded_size);
6093 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
6094 gimplify_and_add (t, pre_p);
6096 addr = fold_convert (build_pointer_type (type), addr);
6099 addr = build_va_arg_indirect_ref (addr);
6101 return build_va_arg_indirect_ref (addr);
6104 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
6107 mips_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
6113 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
6115 type = build_pointer_type (type);
6117 if (!EABI_FLOAT_VARARGS_P)
6118 addr = mips_std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6121 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
6122 tree ovfl, top, off, align;
6123 HOST_WIDE_INT size, rsize, osize;
6126 f_ovfl = TYPE_FIELDS (va_list_type_node);
6127 f_gtop = DECL_CHAIN (f_ovfl);
6128 f_ftop = DECL_CHAIN (f_gtop);
6129 f_goff = DECL_CHAIN (f_ftop);
6130 f_foff = DECL_CHAIN (f_goff);
6134 TOP be the top of the GPR or FPR save area;
6135 OFF be the offset from TOP of the next register;
6136 ADDR_RTX be the address of the argument;
6137 SIZE be the number of bytes in the argument type;
6138 RSIZE be the number of bytes used to store the argument
6139 when it's in the register save area; and
6140 OSIZE be the number of bytes used to store it when it's
6141 in the stack overflow area.
6143 The code we want is:
6145 1: off &= -rsize; // round down
6148 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
6153 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
6154 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
6158 [1] and [9] can sometimes be optimized away. */
6160 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
6162 size = int_size_in_bytes (type);
6164 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
6165 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
6167 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop),
6168 unshare_expr (valist), f_ftop, NULL_TREE);
6169 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff),
6170 unshare_expr (valist), f_foff, NULL_TREE);
6172 /* When va_start saves FPR arguments to the stack, each slot
6173 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
6174 argument's precision. */
6175 rsize = UNITS_PER_HWFPVALUE;
6177 /* Overflow arguments are padded to UNITS_PER_WORD bytes
6178 (= PARM_BOUNDARY bits). This can be different from RSIZE
6181 (1) On 32-bit targets when TYPE is a structure such as:
6183 struct s { float f; };
6185 Such structures are passed in paired FPRs, so RSIZE
6186 will be 8 bytes. However, the structure only takes
6187 up 4 bytes of memory, so OSIZE will only be 4.
6189 (2) In combinations such as -mgp64 -msingle-float
6190 -fshort-double. Doubles passed in registers will then take
6191 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
6192 stack take up UNITS_PER_WORD bytes. */
6193 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
6197 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop),
6198 unshare_expr (valist), f_gtop, NULL_TREE);
6199 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff),
6200 unshare_expr (valist), f_goff, NULL_TREE);
6201 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
6202 if (rsize > UNITS_PER_WORD)
6204 /* [1] Emit code for: off &= -rsize. */
6205 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), unshare_expr (off),
6206 build_int_cst (TREE_TYPE (off), -rsize));
6207 gimplify_assign (unshare_expr (off), t, pre_p);
6212 /* [2] Emit code to branch if off == 0. */
6213 t = build2 (NE_EXPR, boolean_type_node, unshare_expr (off),
6214 build_int_cst (TREE_TYPE (off), 0));
6215 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
6217 /* [5] Emit code for: off -= rsize. We do this as a form of
6218 post-decrement not available to C. */
6219 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
6220 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
6222 /* [4] Emit code for:
6223 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
6224 t = fold_convert (sizetype, t);
6225 t = fold_build1 (NEGATE_EXPR, sizetype, t);
6226 t = fold_build_pointer_plus (top, t);
6227 if (BYTES_BIG_ENDIAN && rsize > size)
6228 t = fold_build_pointer_plus_hwi (t, rsize - size);
6229 COND_EXPR_THEN (addr) = t;
6231 if (osize > UNITS_PER_WORD)
6233 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
6234 t = fold_build_pointer_plus_hwi (unshare_expr (ovfl), osize - 1);
6235 u = build_int_cst (TREE_TYPE (t), -osize);
6236 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t, u);
6237 align = build2 (MODIFY_EXPR, TREE_TYPE (ovfl),
6238 unshare_expr (ovfl), t);
6243 /* [10, 11] Emit code for:
6244 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
6246 u = fold_convert (TREE_TYPE (ovfl), build_int_cst (NULL_TREE, osize));
6247 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
6248 if (BYTES_BIG_ENDIAN && osize > size)
6249 t = fold_build_pointer_plus_hwi (t, osize - size);
6251 /* String [9] and [10, 11] together. */
6253 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
6254 COND_EXPR_ELSE (addr) = t;
6256 addr = fold_convert (build_pointer_type (type), addr);
6257 addr = build_va_arg_indirect_ref (addr);
6261 addr = build_va_arg_indirect_ref (addr);
6266 /* Declare a unique, locally-binding function called NAME, then start
6270 mips_start_unique_function (const char *name)
6274 decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
6275 get_identifier (name),
6276 build_function_type_list (void_type_node, NULL_TREE));
6277 DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
6278 NULL_TREE, void_type_node);
6279 TREE_PUBLIC (decl) = 1;
6280 TREE_STATIC (decl) = 1;
6282 cgraph_node::create (decl)->set_comdat_group (DECL_ASSEMBLER_NAME (decl));
6284 targetm.asm_out.unique_section (decl, 0);
6285 switch_to_section (get_named_section (decl, NULL, 0));
6287 targetm.asm_out.globalize_label (asm_out_file, name);
6288 fputs ("\t.hidden\t", asm_out_file);
6289 assemble_name (asm_out_file, name);
6290 putc ('\n', asm_out_file);
6293 /* Start a definition of function NAME. MIPS16_P indicates whether the
6294 function contains MIPS16 code. */
6297 mips_start_function_definition (const char *name, bool mips16_p)
6300 fprintf (asm_out_file, "\t.set\tmips16\n");
6302 fprintf (asm_out_file, "\t.set\tnomips16\n");
6304 if (TARGET_MICROMIPS)
6305 fprintf (asm_out_file, "\t.set\tmicromips\n");
6306 #ifdef HAVE_GAS_MICROMIPS
6308 fprintf (asm_out_file, "\t.set\tnomicromips\n");
6311 if (!flag_inhibit_size_directive)
6313 fputs ("\t.ent\t", asm_out_file);
6314 assemble_name (asm_out_file, name);
6315 fputs ("\n", asm_out_file);
6318 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, name, "function");
6320 /* Start the definition proper. */
6321 assemble_name (asm_out_file, name);
6322 fputs (":\n", asm_out_file);
6325 /* End a function definition started by mips_start_function_definition. */
6328 mips_end_function_definition (const char *name)
6330 if (!flag_inhibit_size_directive)
6332 fputs ("\t.end\t", asm_out_file);
6333 assemble_name (asm_out_file, name);
6334 fputs ("\n", asm_out_file);
6338 /* If *STUB_PTR points to a stub, output a comdat-style definition for it,
6339 then free *STUB_PTR. */
6342 mips_finish_stub (mips_one_only_stub **stub_ptr)
6344 mips_one_only_stub *stub = *stub_ptr;
6348 const char *name = stub->get_name ();
6349 mips_start_unique_function (name);
6350 mips_start_function_definition (name, false);
6351 stub->output_body ();
6352 mips_end_function_definition (name);
6357 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
6360 mips_ok_for_lazy_binding_p (rtx x)
6362 return (TARGET_USE_GOT
6363 && GET_CODE (x) == SYMBOL_REF
6364 && !SYMBOL_REF_BIND_NOW_P (x)
6365 && !mips_symbol_binds_local_p (x));
6368 /* Load function address ADDR into register DEST. TYPE is as for
6369 mips_expand_call. Return true if we used an explicit lazy-binding
6373 mips_load_call_address (enum mips_call_type type, rtx dest, rtx addr)
6375 /* If we're generating PIC, and this call is to a global function,
6376 try to allow its address to be resolved lazily. This isn't
6377 possible for sibcalls when $gp is call-saved because the value
6378 of $gp on entry to the stub would be our caller's gp, not ours. */
6379 if (TARGET_EXPLICIT_RELOCS
6380 && !(type == MIPS_CALL_SIBCALL && TARGET_CALL_SAVED_GP)
6381 && mips_ok_for_lazy_binding_p (addr))
6383 addr = mips_got_load (dest, addr, SYMBOL_GOTOFF_CALL);
6384 emit_insn (gen_rtx_SET (VOIDmode, dest, addr));
6389 mips_emit_move (dest, addr);
6394 /* Each locally-defined hard-float MIPS16 function has a local symbol
6395 associated with it. This hash table maps the function symbol (FUNC)
6396 to the local symbol (LOCAL). */
6397 struct GTY(()) mips16_local_alias {
6401 static GTY ((param_is (struct mips16_local_alias))) htab_t mips16_local_aliases;
6403 /* Hash table callbacks for mips16_local_aliases. */
6406 mips16_local_aliases_hash (const void *entry)
6408 const struct mips16_local_alias *alias;
6410 alias = (const struct mips16_local_alias *) entry;
6411 return htab_hash_string (XSTR (alias->func, 0));
6415 mips16_local_aliases_eq (const void *entry1, const void *entry2)
6417 const struct mips16_local_alias *alias1, *alias2;
6419 alias1 = (const struct mips16_local_alias *) entry1;
6420 alias2 = (const struct mips16_local_alias *) entry2;
6421 return rtx_equal_p (alias1->func, alias2->func);
6424 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
6425 Return a local alias for it, creating a new one if necessary. */
6428 mips16_local_alias (rtx func)
6430 struct mips16_local_alias *alias, tmp_alias;
6433 /* Create the hash table if this is the first call. */
6434 if (mips16_local_aliases == NULL)
6435 mips16_local_aliases = htab_create_ggc (37, mips16_local_aliases_hash,
6436 mips16_local_aliases_eq, NULL);
6438 /* Look up the function symbol, creating a new entry if need be. */
6439 tmp_alias.func = func;
6440 slot = htab_find_slot (mips16_local_aliases, &tmp_alias, INSERT);
6441 gcc_assert (slot != NULL);
6443 alias = (struct mips16_local_alias *) *slot;
6446 const char *func_name, *local_name;
6449 /* Create a new SYMBOL_REF for the local symbol. The choice of
6450 __fn_local_* is based on the __fn_stub_* names that we've
6451 traditionally used for the non-MIPS16 stub. */
6452 func_name = targetm.strip_name_encoding (XSTR (func, 0));
6453 local_name = ACONCAT (("__fn_local_", func_name, NULL));
6454 local = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (local_name));
6455 SYMBOL_REF_FLAGS (local) = SYMBOL_REF_FLAGS (func) | SYMBOL_FLAG_LOCAL;
6457 /* Create a new structure to represent the mapping. */
6458 alias = ggc_alloc<struct mips16_local_alias> ();
6460 alias->local = local;
6463 return alias->local;
6466 /* A chained list of functions for which mips16_build_call_stub has already
6467 generated a stub. NAME is the name of the function and FP_RET_P is true
6468 if the function returns a value in floating-point registers. */
6469 struct mips16_stub {
6470 struct mips16_stub *next;
6474 static struct mips16_stub *mips16_stubs;
6476 /* Return the two-character string that identifies floating-point
6477 return mode MODE in the name of a MIPS16 function stub. */
6480 mips16_call_stub_mode_suffix (enum machine_mode mode)
6484 else if (mode == DFmode)
6486 else if (mode == SCmode)
6488 else if (mode == DCmode)
6490 else if (mode == V2SFmode)
6496 /* Write instructions to move a 32-bit value between general register
6497 GPREG and floating-point register FPREG. DIRECTION is 't' to move
6498 from GPREG to FPREG and 'f' to move in the opposite direction. */
6501 mips_output_32bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
6503 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6504 reg_names[gpreg], reg_names[fpreg]);
6507 /* Likewise for 64-bit values. */
6510 mips_output_64bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
6513 fprintf (asm_out_file, "\tdm%cc1\t%s,%s\n", direction,
6514 reg_names[gpreg], reg_names[fpreg]);
6515 else if (TARGET_FLOAT64)
6517 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6518 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
6519 fprintf (asm_out_file, "\tm%chc1\t%s,%s\n", direction,
6520 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg]);
6524 /* Move the least-significant word. */
6525 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6526 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
6527 /* ...then the most significant word. */
6528 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6529 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg + 1]);
6533 /* Write out code to move floating-point arguments into or out of
6534 general registers. FP_CODE is the code describing which arguments
6535 are present (see the comment above the definition of CUMULATIVE_ARGS
6536 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
6539 mips_output_args_xfer (int fp_code, char direction)
6541 unsigned int gparg, fparg, f;
6542 CUMULATIVE_ARGS cum;
6544 /* This code only works for o32 and o64. */
6545 gcc_assert (TARGET_OLDABI);
6547 mips_init_cumulative_args (&cum, NULL);
6549 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
6551 enum machine_mode mode;
6552 struct mips_arg_info info;
6556 else if ((f & 3) == 2)
6561 mips_get_arg_info (&info, &cum, mode, NULL, true);
6562 gparg = mips_arg_regno (&info, false);
6563 fparg = mips_arg_regno (&info, true);
6566 mips_output_32bit_xfer (direction, gparg, fparg);
6568 mips_output_64bit_xfer (direction, gparg, fparg);
6570 mips_function_arg_advance (pack_cumulative_args (&cum), mode, NULL, true);
6574 /* Write a MIPS16 stub for the current function. This stub is used
6575 for functions which take arguments in the floating-point registers.
6576 It is normal-mode code that moves the floating-point arguments
6577 into the general registers and then jumps to the MIPS16 code. */
6580 mips16_build_function_stub (void)
6582 const char *fnname, *alias_name, *separator;
6583 char *secname, *stubname;
6588 /* Create the name of the stub, and its unique section. */
6589 symbol = XEXP (DECL_RTL (current_function_decl), 0);
6590 alias = mips16_local_alias (symbol);
6592 fnname = targetm.strip_name_encoding (XSTR (symbol, 0));
6593 alias_name = targetm.strip_name_encoding (XSTR (alias, 0));
6594 secname = ACONCAT ((".mips16.fn.", fnname, NULL));
6595 stubname = ACONCAT (("__fn_stub_", fnname, NULL));
6597 /* Build a decl for the stub. */
6598 stubdecl = build_decl (BUILTINS_LOCATION,
6599 FUNCTION_DECL, get_identifier (stubname),
6600 build_function_type_list (void_type_node, NULL_TREE));
6601 set_decl_section_name (stubdecl, secname);
6602 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
6603 RESULT_DECL, NULL_TREE, void_type_node);
6605 /* Output a comment. */
6606 fprintf (asm_out_file, "\t# Stub function for %s (",
6607 current_function_name ());
6609 for (f = (unsigned int) crtl->args.info.fp_code; f != 0; f >>= 2)
6611 fprintf (asm_out_file, "%s%s", separator,
6612 (f & 3) == 1 ? "float" : "double");
6615 fprintf (asm_out_file, ")\n");
6617 /* Start the function definition. */
6618 assemble_start_function (stubdecl, stubname);
6619 mips_start_function_definition (stubname, false);
6621 /* If generating pic2 code, either set up the global pointer or
6623 if (TARGET_ABICALLS_PIC2)
6625 if (TARGET_ABSOLUTE_ABICALLS)
6626 fprintf (asm_out_file, "\t.option\tpic0\n");
6629 output_asm_insn ("%(.cpload\t%^%)", NULL);
6630 /* Emit an R_MIPS_NONE relocation to tell the linker what the
6631 target function is. Use a local GOT access when loading the
6632 symbol, to cut down on the number of unnecessary GOT entries
6633 for stubs that aren't needed. */
6634 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol);
6639 /* Load the address of the MIPS16 function into $25. Do this first so
6640 that targets with coprocessor interlocks can use an MFC1 to fill the
6642 output_asm_insn ("la\t%^,%0", &symbol);
6644 /* Move the arguments from floating-point registers to general registers. */
6645 mips_output_args_xfer (crtl->args.info.fp_code, 'f');
6647 /* Jump to the MIPS16 function. */
6648 output_asm_insn ("jr\t%^", NULL);
6650 if (TARGET_ABICALLS_PIC2 && TARGET_ABSOLUTE_ABICALLS)
6651 fprintf (asm_out_file, "\t.option\tpic2\n");
6653 mips_end_function_definition (stubname);
6655 /* If the linker needs to create a dynamic symbol for the target
6656 function, it will associate the symbol with the stub (which,
6657 unlike the target function, follows the proper calling conventions).
6658 It is therefore useful to have a local alias for the target function,
6659 so that it can still be identified as MIPS16 code. As an optimization,
6660 this symbol can also be used for indirect MIPS16 references from
6661 within this file. */
6662 ASM_OUTPUT_DEF (asm_out_file, alias_name, fnname);
6664 switch_to_section (function_section (current_function_decl));
6667 /* The current function is a MIPS16 function that returns a value in an FPR.
6668 Copy the return value from its soft-float to its hard-float location.
6669 libgcc2 has special non-MIPS16 helper functions for each case. */
6672 mips16_copy_fpr_return_value (void)
6674 rtx fn, insn, retval;
6676 enum machine_mode return_mode;
6679 return_type = DECL_RESULT (current_function_decl);
6680 return_mode = DECL_MODE (return_type);
6682 name = ACONCAT (("__mips16_ret_",
6683 mips16_call_stub_mode_suffix (return_mode),
6685 fn = mips16_stub_function (name);
6687 /* The function takes arguments in $2 (and possibly $3), so calls
6688 to it cannot be lazily bound. */
6689 SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_BIND_NOW;
6691 /* Model the call as something that takes the GPR return value as
6692 argument and returns an "updated" value. */
6693 retval = gen_rtx_REG (return_mode, GP_RETURN);
6694 insn = mips_expand_call (MIPS_CALL_EPILOGUE, retval, fn,
6695 const0_rtx, NULL_RTX, false);
6696 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), retval);
6699 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
6700 RETVAL is the location of the return value, or null if this is
6701 a "call" rather than a "call_value". ARGS_SIZE is the size of the
6702 arguments and FP_CODE is the code built by mips_function_arg;
6703 see the comment before the fp_code field in CUMULATIVE_ARGS for details.
6705 There are three alternatives:
6707 - If a stub was needed, emit the call and return the call insn itself.
6709 - If we can avoid using a stub by redirecting the call, set *FN_PTR
6710 to the new target and return null.
6712 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
6715 A stub is needed for calls to functions that, in normal mode,
6716 receive arguments in FPRs or return values in FPRs. The stub
6717 copies the arguments from their soft-float positions to their
6718 hard-float positions, calls the real function, then copies the
6719 return value from its hard-float position to its soft-float
6722 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
6723 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
6724 automatically redirects the JAL to the stub, otherwise the JAL
6725 continues to call FN directly. */
6728 mips16_build_call_stub (rtx retval, rtx *fn_ptr, rtx args_size, int fp_code)
6732 struct mips16_stub *l;
6736 /* We don't need to do anything if we aren't in MIPS16 mode, or if
6737 we were invoked with the -msoft-float option. */
6738 if (!TARGET_MIPS16 || TARGET_SOFT_FLOAT_ABI)
6741 /* Figure out whether the value might come back in a floating-point
6743 fp_ret_p = retval && mips_return_mode_in_fpr_p (GET_MODE (retval));
6745 /* We don't need to do anything if there were no floating-point
6746 arguments and the value will not be returned in a floating-point
6748 if (fp_code == 0 && !fp_ret_p)
6751 /* We don't need to do anything if this is a call to a special
6752 MIPS16 support function. */
6754 if (mips16_stub_function_p (fn))
6757 /* If we're calling a locally-defined MIPS16 function, we know that
6758 it will return values in both the "soft-float" and "hard-float"
6759 registers. There is no need to use a stub to move the latter
6761 if (fp_code == 0 && mips16_local_function_p (fn))
6764 /* This code will only work for o32 and o64 abis. The other ABI's
6765 require more sophisticated support. */
6766 gcc_assert (TARGET_OLDABI);
6768 /* If we're calling via a function pointer, use one of the magic
6769 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
6770 Each stub expects the function address to arrive in register $2. */
6771 if (GET_CODE (fn) != SYMBOL_REF
6772 || !call_insn_operand (fn, VOIDmode))
6779 /* If this is a locally-defined and locally-binding function,
6780 avoid the stub by calling the local alias directly. */
6781 if (mips16_local_function_p (fn))
6783 *fn_ptr = mips16_local_alias (fn);
6787 /* Create a SYMBOL_REF for the libgcc.a function. */
6789 sprintf (buf, "__mips16_call_stub_%s_%d",
6790 mips16_call_stub_mode_suffix (GET_MODE (retval)),
6793 sprintf (buf, "__mips16_call_stub_%d", fp_code);
6794 stub_fn = mips16_stub_function (buf);
6796 /* The function uses $2 as an argument, so calls to it
6797 cannot be lazily bound. */
6798 SYMBOL_REF_FLAGS (stub_fn) |= SYMBOL_FLAG_BIND_NOW;
6800 /* Load the target function into $2. */
6801 addr = gen_rtx_REG (Pmode, GP_REG_FIRST + 2);
6802 lazy_p = mips_load_call_address (MIPS_CALL_NORMAL, addr, fn);
6804 /* Emit the call. */
6805 insn = mips_expand_call (MIPS_CALL_NORMAL, retval, stub_fn,
6806 args_size, NULL_RTX, lazy_p);
6808 /* Tell GCC that this call does indeed use the value of $2. */
6809 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), addr);
6811 /* If we are handling a floating-point return value, we need to
6812 save $18 in the function prologue. Putting a note on the
6813 call will mean that df_regs_ever_live_p ($18) will be true if the
6814 call is not eliminated, and we can check that in the prologue
6817 CALL_INSN_FUNCTION_USAGE (insn) =
6818 gen_rtx_EXPR_LIST (VOIDmode,
6819 gen_rtx_CLOBBER (VOIDmode,
6820 gen_rtx_REG (word_mode, 18)),
6821 CALL_INSN_FUNCTION_USAGE (insn));
6826 /* We know the function we are going to call. If we have already
6827 built a stub, we don't need to do anything further. */
6828 fnname = targetm.strip_name_encoding (XSTR (fn, 0));
6829 for (l = mips16_stubs; l != NULL; l = l->next)
6830 if (strcmp (l->name, fnname) == 0)
6835 const char *separator;
6836 char *secname, *stubname;
6837 tree stubid, stubdecl;
6840 /* If the function does not return in FPRs, the special stub
6844 If the function does return in FPRs, the stub section is named
6845 .mips16.call.fp.FNNAME
6847 Build a decl for the stub. */
6848 secname = ACONCAT ((".mips16.call.", fp_ret_p ? "fp." : "",
6850 stubname = ACONCAT (("__call_stub_", fp_ret_p ? "fp_" : "",
6852 stubid = get_identifier (stubname);
6853 stubdecl = build_decl (BUILTINS_LOCATION,
6854 FUNCTION_DECL, stubid,
6855 build_function_type_list (void_type_node,
6857 set_decl_section_name (stubdecl, secname);
6858 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
6859 RESULT_DECL, NULL_TREE,
6862 /* Output a comment. */
6863 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
6865 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
6869 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
6871 fprintf (asm_out_file, "%s%s", separator,
6872 (f & 3) == 1 ? "float" : "double");
6875 fprintf (asm_out_file, ")\n");
6877 /* Start the function definition. */
6878 assemble_start_function (stubdecl, stubname);
6879 mips_start_function_definition (stubname, false);
6883 fprintf (asm_out_file, "\t.cfi_startproc\n");
6885 /* Create a fake CFA 4 bytes below the stack pointer.
6886 This works around unwinders (like libgcc's) that expect
6887 the CFA for non-signal frames to be unique. */
6888 fprintf (asm_out_file, "\t.cfi_def_cfa 29,-4\n");
6890 /* "Save" $sp in itself so we don't use the fake CFA.
6891 This is: DW_CFA_val_expression r29, { DW_OP_reg29 }. */
6892 fprintf (asm_out_file, "\t.cfi_escape 0x16,29,1,0x6d\n");
6896 /* Load the address of the MIPS16 function into $25. Do this
6897 first so that targets with coprocessor interlocks can use
6898 an MFC1 to fill the delay slot. */
6899 if (TARGET_EXPLICIT_RELOCS)
6901 output_asm_insn ("lui\t%^,%%hi(%0)", &fn);
6902 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn);
6905 output_asm_insn ("la\t%^,%0", &fn);
6908 /* Move the arguments from general registers to floating-point
6910 mips_output_args_xfer (fp_code, 't');
6914 /* Save the return address in $18 and call the non-MIPS16 function.
6915 The stub's caller knows that $18 might be clobbered, even though
6916 $18 is usually a call-saved register. */
6917 fprintf (asm_out_file, "\tmove\t%s,%s\n",
6918 reg_names[GP_REG_FIRST + 18], reg_names[RETURN_ADDR_REGNUM]);
6919 output_asm_insn (MIPS_CALL ("jal", &fn, 0, -1), &fn);
6920 fprintf (asm_out_file, "\t.cfi_register 31,18\n");
6922 /* Move the result from floating-point registers to
6923 general registers. */
6924 switch (GET_MODE (retval))
6927 mips_output_32bit_xfer ('f', GP_RETURN + TARGET_BIG_ENDIAN,
6929 ? FP_REG_FIRST + MAX_FPRS_PER_FMT
6931 mips_output_32bit_xfer ('f', GP_RETURN + TARGET_LITTLE_ENDIAN,
6932 TARGET_LITTLE_ENDIAN
6933 ? FP_REG_FIRST + MAX_FPRS_PER_FMT
6935 if (GET_MODE (retval) == SCmode && TARGET_64BIT)
6937 /* On 64-bit targets, complex floats are returned in
6938 a single GPR, such that "sd" on a suitably-aligned
6939 target would store the value correctly. */
6940 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
6941 reg_names[GP_RETURN + TARGET_BIG_ENDIAN],
6942 reg_names[GP_RETURN + TARGET_BIG_ENDIAN]);
6943 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
6944 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN],
6945 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN]);
6946 fprintf (asm_out_file, "\tdsrl\t%s,%s,32\n",
6947 reg_names[GP_RETURN + TARGET_BIG_ENDIAN],
6948 reg_names[GP_RETURN + TARGET_BIG_ENDIAN]);
6949 fprintf (asm_out_file, "\tor\t%s,%s,%s\n",
6950 reg_names[GP_RETURN],
6951 reg_names[GP_RETURN],
6952 reg_names[GP_RETURN + 1]);
6957 mips_output_32bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6961 mips_output_64bit_xfer ('f', GP_RETURN + (8 / UNITS_PER_WORD),
6962 FP_REG_FIRST + MAX_FPRS_PER_FMT);
6966 mips_output_64bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6972 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 18]);
6973 fprintf (asm_out_file, "\t.cfi_endproc\n");
6977 /* Jump to the previously-loaded address. */
6978 output_asm_insn ("jr\t%^", NULL);
6981 #ifdef ASM_DECLARE_FUNCTION_SIZE
6982 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
6985 mips_end_function_definition (stubname);
6987 /* Record this stub. */
6988 l = XNEW (struct mips16_stub);
6989 l->name = xstrdup (fnname);
6990 l->fp_ret_p = fp_ret_p;
6991 l->next = mips16_stubs;
6995 /* If we expect a floating-point return value, but we've built a
6996 stub which does not expect one, then we're in trouble. We can't
6997 use the existing stub, because it won't handle the floating-point
6998 value. We can't build a new stub, because the linker won't know
6999 which stub to use for the various calls in this object file.
7000 Fortunately, this case is illegal, since it means that a function
7001 was declared in two different ways in a single compilation. */
7002 if (fp_ret_p && !l->fp_ret_p)
7003 error ("cannot handle inconsistent calls to %qs", fnname);
7005 if (retval == NULL_RTX)
7006 pattern = gen_call_internal_direct (fn, args_size);
7008 pattern = gen_call_value_internal_direct (retval, fn, args_size);
7009 insn = mips_emit_call_insn (pattern, fn, fn, false);
7011 /* If we are calling a stub which handles a floating-point return
7012 value, we need to arrange to save $18 in the prologue. We do this
7013 by marking the function call as using the register. The prologue
7014 will later see that it is used, and emit code to save it. */
7016 CALL_INSN_FUNCTION_USAGE (insn) =
7017 gen_rtx_EXPR_LIST (VOIDmode,
7018 gen_rtx_CLOBBER (VOIDmode,
7019 gen_rtx_REG (word_mode, 18)),
7020 CALL_INSN_FUNCTION_USAGE (insn));
7025 /* Expand a call of type TYPE. RESULT is where the result will go (null
7026 for "call"s and "sibcall"s), ADDR is the address of the function,
7027 ARGS_SIZE is the size of the arguments and AUX is the value passed
7028 to us by mips_function_arg. LAZY_P is true if this call already
7029 involves a lazily-bound function address (such as when calling
7030 functions through a MIPS16 hard-float stub).
7032 Return the call itself. */
7035 mips_expand_call (enum mips_call_type type, rtx result, rtx addr,
7036 rtx args_size, rtx aux, bool lazy_p)
7038 rtx orig_addr, pattern;
7042 fp_code = aux == 0 ? 0 : (int) GET_MODE (aux);
7043 insn = mips16_build_call_stub (result, &addr, args_size, fp_code);
7046 gcc_assert (!lazy_p && type == MIPS_CALL_NORMAL);
7051 if (!call_insn_operand (addr, VOIDmode))
7053 if (type == MIPS_CALL_EPILOGUE)
7054 addr = MIPS_EPILOGUE_TEMP (Pmode);
7056 addr = gen_reg_rtx (Pmode);
7057 lazy_p |= mips_load_call_address (type, addr, orig_addr);
7062 rtx (*fn) (rtx, rtx);
7064 if (type == MIPS_CALL_SIBCALL)
7065 fn = gen_sibcall_internal;
7067 fn = gen_call_internal;
7069 pattern = fn (addr, args_size);
7071 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
7073 /* Handle return values created by mips_return_fpr_pair. */
7074 rtx (*fn) (rtx, rtx, rtx, rtx);
7077 if (type == MIPS_CALL_SIBCALL)
7078 fn = gen_sibcall_value_multiple_internal;
7080 fn = gen_call_value_multiple_internal;
7082 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
7083 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
7084 pattern = fn (reg1, addr, args_size, reg2);
7088 rtx (*fn) (rtx, rtx, rtx);
7090 if (type == MIPS_CALL_SIBCALL)
7091 fn = gen_sibcall_value_internal;
7093 fn = gen_call_value_internal;
7095 /* Handle return values created by mips_return_fpr_single. */
7096 if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 1)
7097 result = XEXP (XVECEXP (result, 0, 0), 0);
7098 pattern = fn (result, addr, args_size);
7101 return mips_emit_call_insn (pattern, orig_addr, addr, lazy_p);
7104 /* Split call instruction INSN into a $gp-clobbering call and
7105 (where necessary) an instruction to restore $gp from its save slot.
7106 CALL_PATTERN is the pattern of the new call. */
7109 mips_split_call (rtx insn, rtx call_pattern)
7111 emit_call_insn (call_pattern);
7112 if (!find_reg_note (insn, REG_NORETURN, 0))
7113 mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode,
7114 POST_CALL_TMP_REG));
7117 /* Return true if a call to DECL may need to use JALX. */
7120 mips_call_may_need_jalx_p (tree decl)
7122 /* If the current translation unit would use a different mode for DECL,
7123 assume that the call needs JALX. */
7124 if (mips_get_compress_mode (decl) != TARGET_COMPRESSION)
7127 /* mips_get_compress_mode is always accurate for locally-binding
7128 functions in the current translation unit. */
7129 if (!DECL_EXTERNAL (decl) && targetm.binds_local_p (decl))
7132 /* When -minterlink-compressed is in effect, assume that functions
7133 could use a different encoding mode unless an attribute explicitly
7134 tells us otherwise. */
7135 if (TARGET_INTERLINK_COMPRESSED)
7137 if (!TARGET_COMPRESSION
7138 && mips_get_compress_off_flags (DECL_ATTRIBUTES (decl)) ==0)
7140 if (TARGET_COMPRESSION
7141 && mips_get_compress_on_flags (DECL_ATTRIBUTES (decl)) == 0)
7148 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
7151 mips_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
7153 if (!TARGET_SIBCALLS)
7156 /* Interrupt handlers need special epilogue code and therefore can't
7158 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
7161 /* Direct Js are only possible to functions that use the same ISA encoding.
7162 There is no JX counterpoart of JALX. */
7164 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode)
7165 && mips_call_may_need_jalx_p (decl))
7168 /* Sibling calls should not prevent lazy binding. Lazy-binding stubs
7169 require $gp to be valid on entry, so sibcalls can only use stubs
7170 if $gp is call-clobbered. */
7172 && TARGET_CALL_SAVED_GP
7173 && !TARGET_ABICALLS_PIC0
7174 && !targetm.binds_local_p (decl))
7181 /* Implement MOVE_BY_PIECES_P. */
7184 mips_move_by_pieces_p (unsigned HOST_WIDE_INT size, unsigned int align)
7188 /* movmemsi is meant to generate code that is at least as good as
7189 move_by_pieces. However, movmemsi effectively uses a by-pieces
7190 implementation both for moves smaller than a word and for
7191 word-aligned moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT
7192 bytes. We should allow the tree-level optimisers to do such
7193 moves by pieces, as it often exposes other optimization
7194 opportunities. We might as well continue to use movmemsi at
7195 the rtl level though, as it produces better code when
7196 scheduling is disabled (such as at -O). */
7197 if (currently_expanding_to_rtl)
7199 if (align < BITS_PER_WORD)
7200 return size < UNITS_PER_WORD;
7201 return size <= MIPS_MAX_MOVE_BYTES_STRAIGHT;
7203 /* The default value. If this becomes a target hook, we should
7204 call the default definition instead. */
7205 return (move_by_pieces_ninsns (size, align, MOVE_MAX_PIECES + 1)
7206 < (unsigned int) MOVE_RATIO (optimize_insn_for_speed_p ()));
7209 /* Implement STORE_BY_PIECES_P. */
7212 mips_store_by_pieces_p (unsigned HOST_WIDE_INT size, unsigned int align)
7214 /* Storing by pieces involves moving constants into registers
7215 of size MIN (ALIGN, BITS_PER_WORD), then storing them.
7216 We need to decide whether it is cheaper to load the address of
7217 constant data into a register and use a block move instead. */
7219 /* If the data is only byte aligned, then:
7221 (a1) A block move of less than 4 bytes would involve three 3 LBs and
7222 3 SBs. We might as well use 3 single-instruction LIs and 3 SBs
7225 (a2) A block move of 4 bytes from aligned source data can use an
7226 LW/SWL/SWR sequence. This is often better than the 4 LIs and
7227 4 SBs that we would generate when storing by pieces. */
7228 if (align <= BITS_PER_UNIT)
7231 /* If the data is 2-byte aligned, then:
7233 (b1) A block move of less than 4 bytes would use a combination of LBs,
7234 LHs, SBs and SHs. We get better code by using single-instruction
7235 LIs, SBs and SHs instead.
7237 (b2) A block move of 4 bytes from aligned source data would again use
7238 an LW/SWL/SWR sequence. In most cases, loading the address of
7239 the source data would require at least one extra instruction.
7240 It is often more efficient to use 2 single-instruction LIs and
7243 (b3) A block move of up to 3 additional bytes would be like (b1).
7245 (b4) A block move of 8 bytes from aligned source data can use two
7246 LW/SWL/SWR sequences or a single LD/SDL/SDR sequence. Both
7247 sequences are better than the 4 LIs and 4 SHs that we'd generate
7248 when storing by pieces.
7250 The reasoning for higher alignments is similar:
7252 (c1) A block move of less than 4 bytes would be the same as (b1).
7254 (c2) A block move of 4 bytes would use an LW/SW sequence. Again,
7255 loading the address of the source data would typically require
7256 at least one extra instruction. It is generally better to use
7259 (c3) A block move of up to 3 additional bytes would be like (b1).
7261 (c4) A block move of 8 bytes can use two LW/SW sequences or a single
7262 LD/SD sequence, and in these cases we've traditionally preferred
7263 the memory copy over the more bulky constant moves. */
7267 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
7268 Assume that the areas do not overlap. */
7271 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
7273 HOST_WIDE_INT offset, delta;
7274 unsigned HOST_WIDE_INT bits;
7276 enum machine_mode mode;
7279 /* Work out how many bits to move at a time. If both operands have
7280 half-word alignment, it is usually better to move in half words.
7281 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
7282 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
7283 Otherwise move word-sized chunks. */
7284 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
7285 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
7286 bits = BITS_PER_WORD / 2;
7288 bits = BITS_PER_WORD;
7290 mode = mode_for_size (bits, MODE_INT, 0);
7291 delta = bits / BITS_PER_UNIT;
7293 /* Allocate a buffer for the temporary registers. */
7294 regs = XALLOCAVEC (rtx, length / delta);
7296 /* Load as many BITS-sized chunks as possible. Use a normal load if
7297 the source has enough alignment, otherwise use left/right pairs. */
7298 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
7300 regs[i] = gen_reg_rtx (mode);
7301 if (MEM_ALIGN (src) >= bits)
7302 mips_emit_move (regs[i], adjust_address (src, mode, offset));
7305 rtx part = adjust_address (src, BLKmode, offset);
7306 set_mem_size (part, delta);
7307 if (!mips_expand_ext_as_unaligned_load (regs[i], part, bits, 0, 0))
7312 /* Copy the chunks to the destination. */
7313 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
7314 if (MEM_ALIGN (dest) >= bits)
7315 mips_emit_move (adjust_address (dest, mode, offset), regs[i]);
7318 rtx part = adjust_address (dest, BLKmode, offset);
7319 set_mem_size (part, delta);
7320 if (!mips_expand_ins_as_unaligned_store (part, regs[i], bits, 0))
7324 /* Mop up any left-over bytes. */
7325 if (offset < length)
7327 src = adjust_address (src, BLKmode, offset);
7328 dest = adjust_address (dest, BLKmode, offset);
7329 move_by_pieces (dest, src, length - offset,
7330 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
7334 /* Helper function for doing a loop-based block operation on memory
7335 reference MEM. Each iteration of the loop will operate on LENGTH
7338 Create a new base register for use within the loop and point it to
7339 the start of MEM. Create a new memory reference that uses this
7340 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
7343 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
7344 rtx *loop_reg, rtx *loop_mem)
7346 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
7348 /* Although the new mem does not refer to a known location,
7349 it does keep up to LENGTH bytes of alignment. */
7350 *loop_mem = change_address (mem, BLKmode, *loop_reg);
7351 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
7354 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
7355 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
7356 the memory regions do not overlap. */
7359 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length,
7360 HOST_WIDE_INT bytes_per_iter)
7362 rtx_code_label *label;
7363 rtx src_reg, dest_reg, final_src, test;
7364 HOST_WIDE_INT leftover;
7366 leftover = length % bytes_per_iter;
7369 /* Create registers and memory references for use within the loop. */
7370 mips_adjust_block_mem (src, bytes_per_iter, &src_reg, &src);
7371 mips_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest);
7373 /* Calculate the value that SRC_REG should have after the last iteration
7375 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
7378 /* Emit the start of the loop. */
7379 label = gen_label_rtx ();
7382 /* Emit the loop body. */
7383 mips_block_move_straight (dest, src, bytes_per_iter);
7385 /* Move on to the next block. */
7386 mips_emit_move (src_reg, plus_constant (Pmode, src_reg, bytes_per_iter));
7387 mips_emit_move (dest_reg, plus_constant (Pmode, dest_reg, bytes_per_iter));
7389 /* Emit the loop condition. */
7390 test = gen_rtx_NE (VOIDmode, src_reg, final_src);
7391 if (Pmode == DImode)
7392 emit_jump_insn (gen_cbranchdi4 (test, src_reg, final_src, label));
7394 emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label));
7396 /* Mop up any left-over bytes. */
7398 mips_block_move_straight (dest, src, leftover);
7401 /* Expand a movmemsi instruction, which copies LENGTH bytes from
7402 memory reference SRC to memory reference DEST. */
7405 mips_expand_block_move (rtx dest, rtx src, rtx length)
7407 if (CONST_INT_P (length))
7409 if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)
7411 mips_block_move_straight (dest, src, INTVAL (length));
7416 mips_block_move_loop (dest, src, INTVAL (length),
7417 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER);
7424 /* Expand a loop of synci insns for the address range [BEGIN, END). */
7427 mips_expand_synci_loop (rtx begin, rtx end)
7429 rtx inc, cmp_result, mask, length;
7430 rtx_code_label *label, *end_label;
7432 /* Create end_label. */
7433 end_label = gen_label_rtx ();
7435 /* Check if begin equals end. */
7436 cmp_result = gen_rtx_EQ (VOIDmode, begin, end);
7437 emit_jump_insn (gen_condjump (cmp_result, end_label));
7439 /* Load INC with the cache line size (rdhwr INC,$1). */
7440 inc = gen_reg_rtx (Pmode);
7441 emit_insn (PMODE_INSN (gen_rdhwr_synci_step, (inc)));
7443 /* Check if inc is 0. */
7444 cmp_result = gen_rtx_EQ (VOIDmode, inc, const0_rtx);
7445 emit_jump_insn (gen_condjump (cmp_result, end_label));
7447 /* Calculate mask. */
7448 mask = mips_force_unary (Pmode, NEG, inc);
7450 /* Mask out begin by mask. */
7451 begin = mips_force_binary (Pmode, AND, begin, mask);
7453 /* Calculate length. */
7454 length = mips_force_binary (Pmode, MINUS, end, begin);
7456 /* Loop back to here. */
7457 label = gen_label_rtx ();
7460 emit_insn (gen_synci (begin));
7462 /* Update length. */
7463 mips_emit_binary (MINUS, length, length, inc);
7466 mips_emit_binary (PLUS, begin, begin, inc);
7468 /* Check if length is greater than 0. */
7469 cmp_result = gen_rtx_GT (VOIDmode, length, const0_rtx);
7470 emit_jump_insn (gen_condjump (cmp_result, label));
7472 emit_label (end_label);
7475 /* Expand a QI or HI mode atomic memory operation.
7477 GENERATOR contains a pointer to the gen_* function that generates
7478 the SI mode underlying atomic operation using masks that we
7481 RESULT is the return register for the operation. Its value is NULL
7484 MEM is the location of the atomic access.
7486 OLDVAL is the first operand for the operation.
7488 NEWVAL is the optional second operand for the operation. Its value
7489 is NULL if unused. */
7492 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator,
7493 rtx result, rtx mem, rtx oldval, rtx newval)
7495 rtx orig_addr, memsi_addr, memsi, shift, shiftsi, unshifted_mask;
7496 rtx unshifted_mask_reg, mask, inverted_mask, si_op;
7498 enum machine_mode mode;
7500 mode = GET_MODE (mem);
7502 /* Compute the address of the containing SImode value. */
7503 orig_addr = force_reg (Pmode, XEXP (mem, 0));
7504 memsi_addr = mips_force_binary (Pmode, AND, orig_addr,
7505 force_reg (Pmode, GEN_INT (-4)));
7507 /* Create a memory reference for it. */
7508 memsi = gen_rtx_MEM (SImode, memsi_addr);
7509 set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER);
7510 MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem);
7512 /* Work out the byte offset of the QImode or HImode value,
7513 counting from the least significant byte. */
7514 shift = mips_force_binary (Pmode, AND, orig_addr, GEN_INT (3));
7515 if (TARGET_BIG_ENDIAN)
7516 mips_emit_binary (XOR, shift, shift, GEN_INT (mode == QImode ? 3 : 2));
7518 /* Multiply by eight to convert the shift value from bytes to bits. */
7519 mips_emit_binary (ASHIFT, shift, shift, GEN_INT (3));
7521 /* Make the final shift an SImode value, so that it can be used in
7522 SImode operations. */
7523 shiftsi = force_reg (SImode, gen_lowpart (SImode, shift));
7525 /* Set MASK to an inclusive mask of the QImode or HImode value. */
7526 unshifted_mask = GEN_INT (GET_MODE_MASK (mode));
7527 unshifted_mask_reg = force_reg (SImode, unshifted_mask);
7528 mask = mips_force_binary (SImode, ASHIFT, unshifted_mask_reg, shiftsi);
7530 /* Compute the equivalent exclusive mask. */
7531 inverted_mask = gen_reg_rtx (SImode);
7532 emit_insn (gen_rtx_SET (VOIDmode, inverted_mask,
7533 gen_rtx_NOT (SImode, mask)));
7535 /* Shift the old value into place. */
7536 if (oldval != const0_rtx)
7538 oldval = convert_modes (SImode, mode, oldval, true);
7539 oldval = force_reg (SImode, oldval);
7540 oldval = mips_force_binary (SImode, ASHIFT, oldval, shiftsi);
7543 /* Do the same for the new value. */
7544 if (newval && newval != const0_rtx)
7546 newval = convert_modes (SImode, mode, newval, true);
7547 newval = force_reg (SImode, newval);
7548 newval = mips_force_binary (SImode, ASHIFT, newval, shiftsi);
7551 /* Do the SImode atomic access. */
7553 res = gen_reg_rtx (SImode);
7555 si_op = generator.fn_6 (res, memsi, mask, inverted_mask, oldval, newval);
7557 si_op = generator.fn_5 (res, memsi, mask, inverted_mask, oldval);
7559 si_op = generator.fn_4 (memsi, mask, inverted_mask, oldval);
7565 /* Shift and convert the result. */
7566 mips_emit_binary (AND, res, res, mask);
7567 mips_emit_binary (LSHIFTRT, res, res, shiftsi);
7568 mips_emit_move (result, gen_lowpart (GET_MODE (result), res));
7572 /* Return true if it is possible to use left/right accesses for a
7573 bitfield of WIDTH bits starting BITPOS bits into BLKmode memory OP.
7574 When returning true, update *LEFT and *RIGHT as follows:
7576 *LEFT is a QImode reference to the first byte if big endian or
7577 the last byte if little endian. This address can be used in the
7578 left-side instructions (LWL, SWL, LDL, SDL).
7580 *RIGHT is a QImode reference to the opposite end of the field and
7581 can be used in the patterning right-side instruction. */
7584 mips_get_unaligned_mem (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos,
7585 rtx *left, rtx *right)
7589 /* Check that the size is valid. */
7590 if (width != 32 && (!TARGET_64BIT || width != 64))
7593 /* We can only access byte-aligned values. Since we are always passed
7594 a reference to the first byte of the field, it is not necessary to
7595 do anything with BITPOS after this check. */
7596 if (bitpos % BITS_PER_UNIT != 0)
7599 /* Reject aligned bitfields: we want to use a normal load or store
7600 instead of a left/right pair. */
7601 if (MEM_ALIGN (op) >= width)
7604 /* Get references to both ends of the field. */
7605 first = adjust_address (op, QImode, 0);
7606 last = adjust_address (op, QImode, width / BITS_PER_UNIT - 1);
7608 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
7609 correspond to the MSB and RIGHT to the LSB. */
7610 if (TARGET_BIG_ENDIAN)
7611 *left = first, *right = last;
7613 *left = last, *right = first;
7618 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
7619 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
7620 the operation is the equivalent of:
7622 (set DEST (*_extract SRC WIDTH BITPOS))
7624 Return true on success. */
7627 mips_expand_ext_as_unaligned_load (rtx dest, rtx src, HOST_WIDE_INT width,
7628 HOST_WIDE_INT bitpos, bool unsigned_p)
7630 rtx left, right, temp;
7631 rtx dest1 = NULL_RTX;
7633 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
7634 be a DImode, create a new temp and emit a zero extend at the end. */
7635 if (GET_MODE (dest) == DImode
7637 && GET_MODE_BITSIZE (SImode) == width)
7640 dest = gen_reg_rtx (SImode);
7643 if (!mips_get_unaligned_mem (src, width, bitpos, &left, &right))
7646 temp = gen_reg_rtx (GET_MODE (dest));
7647 if (GET_MODE (dest) == DImode)
7649 emit_insn (gen_mov_ldl (temp, src, left));
7650 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
7654 emit_insn (gen_mov_lwl (temp, src, left));
7655 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
7658 /* If we were loading 32bits and the original register was DI then
7659 sign/zero extend into the orignal dest. */
7663 emit_insn (gen_zero_extendsidi2 (dest1, dest));
7665 emit_insn (gen_extendsidi2 (dest1, dest));
7670 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
7671 BITPOS and SRC are the operands passed to the expander; the operation
7672 is the equivalent of:
7674 (set (zero_extract DEST WIDTH BITPOS) SRC)
7676 Return true on success. */
7679 mips_expand_ins_as_unaligned_store (rtx dest, rtx src, HOST_WIDE_INT width,
7680 HOST_WIDE_INT bitpos)
7683 enum machine_mode mode;
7685 if (!mips_get_unaligned_mem (dest, width, bitpos, &left, &right))
7688 mode = mode_for_size (width, MODE_INT, 0);
7689 src = gen_lowpart (mode, src);
7692 emit_insn (gen_mov_sdl (dest, src, left));
7693 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
7697 emit_insn (gen_mov_swl (dest, src, left));
7698 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
7703 /* Return true if X is a MEM with the same size as MODE. */
7706 mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
7709 && MEM_SIZE_KNOWN_P (x)
7710 && MEM_SIZE (x) == GET_MODE_SIZE (mode));
7713 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
7714 source of an "ext" instruction or the destination of an "ins"
7715 instruction. OP must be a register operand and the following
7716 conditions must hold:
7718 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
7719 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7720 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7722 Also reject lengths equal to a word as they are better handled
7723 by the move patterns. */
7726 mips_use_ins_ext_p (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos)
7728 if (!ISA_HAS_EXT_INS
7729 || !register_operand (op, VOIDmode)
7730 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
7733 if (!IN_RANGE (width, 1, GET_MODE_BITSIZE (GET_MODE (op)) - 1))
7736 if (bitpos < 0 || bitpos + width > GET_MODE_BITSIZE (GET_MODE (op)))
7742 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
7743 operation if MAXLEN is the maxium length of consecutive bits that
7744 can make up MASK. MODE is the mode of the operation. See
7745 mask_low_and_shift_len for the actual definition. */
7748 mask_low_and_shift_p (enum machine_mode mode, rtx mask, rtx shift, int maxlen)
7750 return IN_RANGE (mask_low_and_shift_len (mode, mask, shift), 1, maxlen);
7753 /* Return true iff OP1 and OP2 are valid operands together for the
7754 *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider,
7755 see the table in the comment before the pattern. */
7758 and_operands_ok (enum machine_mode mode, rtx op1, rtx op2)
7760 return (memory_operand (op1, mode)
7761 ? and_load_operand (op2, mode)
7762 : and_reg_operand (op2, mode));
7765 /* The canonical form of a mask-low-and-shift-left operation is
7766 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
7767 cleared. Thus we need to shift MASK to the right before checking if it
7768 is a valid mask value. MODE is the mode of the operation. If true
7769 return the length of the mask, otherwise return -1. */
7772 mask_low_and_shift_len (enum machine_mode mode, rtx mask, rtx shift)
7774 HOST_WIDE_INT shval;
7776 shval = INTVAL (shift) & (GET_MODE_BITSIZE (mode) - 1);
7777 return exact_log2 ((UINTVAL (mask) >> shval) + 1);
7780 /* Return true if -msplit-addresses is selected and should be honored.
7782 -msplit-addresses is a half-way house between explicit relocations
7783 and the traditional assembler macros. It can split absolute 32-bit
7784 symbolic constants into a high/lo_sum pair but uses macros for other
7787 Like explicit relocation support for REL targets, it relies
7788 on GNU extensions in the assembler and the linker.
7790 Although this code should work for -O0, it has traditionally
7791 been treated as an optimization. */
7794 mips_split_addresses_p (void)
7796 return (TARGET_SPLIT_ADDRESSES
7800 && !ABI_HAS_64BIT_SYMBOLS);
7803 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
7806 mips_init_relocs (void)
7808 memset (mips_split_p, '\0', sizeof (mips_split_p));
7809 memset (mips_split_hi_p, '\0', sizeof (mips_split_hi_p));
7810 memset (mips_use_pcrel_pool_p, '\0', sizeof (mips_use_pcrel_pool_p));
7811 memset (mips_hi_relocs, '\0', sizeof (mips_hi_relocs));
7812 memset (mips_lo_relocs, '\0', sizeof (mips_lo_relocs));
7814 if (TARGET_MIPS16_PCREL_LOADS)
7815 mips_use_pcrel_pool_p[SYMBOL_ABSOLUTE] = true;
7818 if (ABI_HAS_64BIT_SYMBOLS)
7820 if (TARGET_EXPLICIT_RELOCS)
7822 mips_split_p[SYMBOL_64_HIGH] = true;
7823 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
7824 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
7826 mips_split_p[SYMBOL_64_MID] = true;
7827 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
7828 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
7830 mips_split_p[SYMBOL_64_LOW] = true;
7831 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
7832 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
7834 mips_split_p[SYMBOL_ABSOLUTE] = true;
7835 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
7840 if (TARGET_EXPLICIT_RELOCS
7841 || mips_split_addresses_p ()
7844 mips_split_p[SYMBOL_ABSOLUTE] = true;
7845 mips_hi_relocs[SYMBOL_ABSOLUTE] = "%hi(";
7846 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
7853 /* The high part is provided by a pseudo copy of $gp. */
7854 mips_split_p[SYMBOL_GP_RELATIVE] = true;
7855 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gprel(";
7857 else if (TARGET_EXPLICIT_RELOCS)
7858 /* Small data constants are kept whole until after reload,
7859 then lowered by mips_rewrite_small_data. */
7860 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gp_rel(";
7862 if (TARGET_EXPLICIT_RELOCS)
7864 mips_split_p[SYMBOL_GOT_PAGE_OFST] = true;
7867 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
7868 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%got_ofst(";
7872 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
7873 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%lo(";
7876 /* Expose the use of $28 as soon as possible. */
7877 mips_split_hi_p[SYMBOL_GOT_PAGE_OFST] = true;
7881 /* The HIGH and LO_SUM are matched by special .md patterns. */
7882 mips_split_p[SYMBOL_GOT_DISP] = true;
7884 mips_split_p[SYMBOL_GOTOFF_DISP] = true;
7885 mips_hi_relocs[SYMBOL_GOTOFF_DISP] = "%got_hi(";
7886 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_lo(";
7888 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
7889 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
7890 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
7895 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_disp(";
7897 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got(";
7898 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
7900 /* Expose the use of $28 as soon as possible. */
7901 mips_split_p[SYMBOL_GOT_DISP] = true;
7907 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
7908 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
7909 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
7912 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
7913 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
7915 if (TARGET_MIPS16_PCREL_LOADS)
7917 mips_use_pcrel_pool_p[SYMBOL_DTPREL] = true;
7918 mips_use_pcrel_pool_p[SYMBOL_TPREL] = true;
7922 mips_split_p[SYMBOL_DTPREL] = true;
7923 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
7924 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
7926 mips_split_p[SYMBOL_TPREL] = true;
7927 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
7928 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
7931 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
7932 mips_lo_relocs[SYMBOL_HALF] = "%half(";
7935 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
7936 in context CONTEXT. RELOCS is the array of relocations to use. */
7939 mips_print_operand_reloc (FILE *file, rtx op, enum mips_symbol_context context,
7940 const char **relocs)
7942 enum mips_symbol_type symbol_type;
7945 symbol_type = mips_classify_symbolic_expression (op, context);
7946 gcc_assert (relocs[symbol_type]);
7948 fputs (relocs[symbol_type], file);
7949 output_addr_const (file, mips_strip_unspec_address (op));
7950 for (p = relocs[symbol_type]; *p != 0; p++)
7955 /* Start a new block with the given asm switch enabled. If we need
7956 to print a directive, emit PREFIX before it and SUFFIX after it. */
7959 mips_push_asm_switch_1 (struct mips_asm_switch *asm_switch,
7960 const char *prefix, const char *suffix)
7962 if (asm_switch->nesting_level == 0)
7963 fprintf (asm_out_file, "%s.set\tno%s%s", prefix, asm_switch->name, suffix);
7964 asm_switch->nesting_level++;
7967 /* Likewise, but end a block. */
7970 mips_pop_asm_switch_1 (struct mips_asm_switch *asm_switch,
7971 const char *prefix, const char *suffix)
7973 gcc_assert (asm_switch->nesting_level);
7974 asm_switch->nesting_level--;
7975 if (asm_switch->nesting_level == 0)
7976 fprintf (asm_out_file, "%s.set\t%s%s", prefix, asm_switch->name, suffix);
7979 /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1
7980 that either print a complete line or print nothing. */
7983 mips_push_asm_switch (struct mips_asm_switch *asm_switch)
7985 mips_push_asm_switch_1 (asm_switch, "\t", "\n");
7989 mips_pop_asm_switch (struct mips_asm_switch *asm_switch)
7991 mips_pop_asm_switch_1 (asm_switch, "\t", "\n");
7994 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
7995 The punctuation characters are:
7997 '(' Start a nested ".set noreorder" block.
7998 ')' End a nested ".set noreorder" block.
7999 '[' Start a nested ".set noat" block.
8000 ']' End a nested ".set noat" block.
8001 '<' Start a nested ".set nomacro" block.
8002 '>' End a nested ".set nomacro" block.
8003 '*' Behave like %(%< if generating a delayed-branch sequence.
8004 '#' Print a nop if in a ".set noreorder" block.
8005 '/' Like '#', but do nothing within a delayed-branch sequence.
8006 '?' Print "l" if mips_branch_likely is true
8007 '~' Print a nop if mips_branch_likely is true
8008 '.' Print the name of the register with a hard-wired zero (zero or $0).
8009 '@' Print the name of the assembler temporary register (at or $1).
8010 '^' Print the name of the pic call-through register (t9 or $25).
8011 '+' Print the name of the gp register (usually gp or $28).
8012 '$' Print the name of the stack pointer register (sp or $29).
8013 ':' Print "c" to use the compact version if the delay slot is a nop.
8014 '!' Print "s" to use the short version if the delay slot contains a
8017 See also mips_init_print_operand_pucnt. */
8020 mips_print_operand_punctuation (FILE *file, int ch)
8025 mips_push_asm_switch_1 (&mips_noreorder, "", "\n\t");
8029 mips_pop_asm_switch_1 (&mips_noreorder, "\n\t", "");
8033 mips_push_asm_switch_1 (&mips_noat, "", "\n\t");
8037 mips_pop_asm_switch_1 (&mips_noat, "\n\t", "");
8041 mips_push_asm_switch_1 (&mips_nomacro, "", "\n\t");
8045 mips_pop_asm_switch_1 (&mips_nomacro, "\n\t", "");
8049 if (final_sequence != 0)
8051 mips_print_operand_punctuation (file, '(');
8052 mips_print_operand_punctuation (file, '<');
8057 if (mips_noreorder.nesting_level > 0)
8058 fputs ("\n\tnop", file);
8062 /* Print an extra newline so that the delayed insn is separated
8063 from the following ones. This looks neater and is consistent
8064 with non-nop delayed sequences. */
8065 if (mips_noreorder.nesting_level > 0 && final_sequence == 0)
8066 fputs ("\n\tnop\n", file);
8070 if (mips_branch_likely)
8075 if (mips_branch_likely)
8076 fputs ("\n\tnop", file);
8080 fputs (reg_names[GP_REG_FIRST + 0], file);
8084 fputs (reg_names[AT_REGNUM], file);
8088 fputs (reg_names[PIC_FUNCTION_ADDR_REGNUM], file);
8092 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
8096 fputs (reg_names[STACK_POINTER_REGNUM], file);
8100 /* When final_sequence is 0, the delay slot will be a nop. We can
8101 use the compact version for microMIPS. */
8102 if (final_sequence == 0)
8107 /* If the delay slot instruction is short, then use the
8109 if (final_sequence == 0
8110 || get_attr_length (final_sequence->insn (1)) == 2)
8120 /* Initialize mips_print_operand_punct. */
8123 mips_init_print_operand_punct (void)
8127 for (p = "()[]<>*#/?~.@^+$:!"; *p; p++)
8128 mips_print_operand_punct[(unsigned char) *p] = true;
8131 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
8132 associated with condition CODE. Print the condition part of the
8136 mips_print_int_branch_condition (FILE *file, enum rtx_code code, int letter)
8150 /* Conveniently, the MIPS names for these conditions are the same
8151 as their RTL equivalents. */
8152 fputs (GET_RTX_NAME (code), file);
8156 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
8161 /* Likewise floating-point branches. */
8164 mips_print_float_branch_condition (FILE *file, enum rtx_code code, int letter)
8169 fputs ("c1f", file);
8173 fputs ("c1t", file);
8177 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
8182 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
8185 mips_print_operand_punct_valid_p (unsigned char code)
8187 return mips_print_operand_punct[code];
8190 /* Implement TARGET_PRINT_OPERAND. The MIPS-specific operand codes are:
8192 'X' Print CONST_INT OP in hexadecimal format.
8193 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
8194 'd' Print CONST_INT OP in decimal.
8195 'm' Print one less than CONST_INT OP in decimal.
8196 'h' Print the high-part relocation associated with OP, after stripping
8198 'R' Print the low-part relocation associated with OP.
8199 'C' Print the integer branch condition for comparison OP.
8200 'N' Print the inverse of the integer branch condition for comparison OP.
8201 'F' Print the FPU branch condition for comparison OP.
8202 'W' Print the inverse of the FPU branch condition for comparison OP.
8203 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
8204 'z' for (eq:?I ...), 'n' for (ne:?I ...).
8205 't' Like 'T', but with the EQ/NE cases reversed
8206 'Y' Print mips_fp_conditions[INTVAL (OP)]
8207 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
8208 'q' Print a DSP accumulator register.
8209 'D' Print the second part of a double-word register or memory operand.
8210 'L' Print the low-order register in a double-word register operand.
8211 'M' Print high-order register in a double-word register operand.
8212 'z' Print $0 if OP is zero, otherwise print OP normally.
8213 'b' Print the address of a memory operand, without offset. */
8216 mips_print_operand (FILE *file, rtx op, int letter)
8220 if (mips_print_operand_punct_valid_p (letter))
8222 mips_print_operand_punctuation (file, letter);
8227 code = GET_CODE (op);
8232 if (CONST_INT_P (op))
8233 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
8235 output_operand_lossage ("invalid use of '%%%c'", letter);
8239 if (CONST_INT_P (op))
8240 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op) & 0xffff);
8242 output_operand_lossage ("invalid use of '%%%c'", letter);
8246 if (CONST_INT_P (op))
8247 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op));
8249 output_operand_lossage ("invalid use of '%%%c'", letter);
8253 if (CONST_INT_P (op))
8254 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op) - 1);
8256 output_operand_lossage ("invalid use of '%%%c'", letter);
8262 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_hi_relocs);
8266 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_lo_relocs);
8270 mips_print_int_branch_condition (file, code, letter);
8274 mips_print_int_branch_condition (file, reverse_condition (code), letter);
8278 mips_print_float_branch_condition (file, code, letter);
8282 mips_print_float_branch_condition (file, reverse_condition (code),
8289 int truth = (code == NE) == (letter == 'T');
8290 fputc ("zfnt"[truth * 2 + ST_REG_P (REGNO (XEXP (op, 0)))], file);
8295 if (code == CONST_INT && UINTVAL (op) < ARRAY_SIZE (mips_fp_conditions))
8296 fputs (mips_fp_conditions[UINTVAL (op)], file);
8298 output_operand_lossage ("'%%%c' is not a valid operand prefix",
8305 mips_print_operand (file, op, 0);
8311 if (code == REG && MD_REG_P (REGNO (op)))
8312 fprintf (file, "$ac0");
8313 else if (code == REG && DSP_ACC_REG_P (REGNO (op)))
8314 fprintf (file, "$ac%c", reg_names[REGNO (op)][3]);
8316 output_operand_lossage ("invalid use of '%%%c'", letter);
8324 unsigned int regno = REGNO (op);
8325 if ((letter == 'M' && TARGET_LITTLE_ENDIAN)
8326 || (letter == 'L' && TARGET_BIG_ENDIAN)
8329 else if (letter && letter != 'z' && letter != 'M' && letter != 'L')
8330 output_operand_lossage ("invalid use of '%%%c'", letter);
8331 /* We need to print $0 .. $31 for COP0 registers. */
8332 if (COP0_REG_P (regno))
8333 fprintf (file, "$%s", ®_names[regno][4]);
8335 fprintf (file, "%s", reg_names[regno]);
8341 output_address (plus_constant (Pmode, XEXP (op, 0), 4));
8342 else if (letter == 'b')
8344 gcc_assert (REG_P (XEXP (op, 0)));
8345 mips_print_operand (file, XEXP (op, 0), 0);
8347 else if (letter && letter != 'z')
8348 output_operand_lossage ("invalid use of '%%%c'", letter);
8350 output_address (XEXP (op, 0));
8354 if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
8355 fputs (reg_names[GP_REG_FIRST], file);
8356 else if (letter && letter != 'z')
8357 output_operand_lossage ("invalid use of '%%%c'", letter);
8358 else if (CONST_GP_P (op))
8359 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
8361 output_addr_const (file, mips_strip_unspec_address (op));
8367 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
8370 mips_print_operand_address (FILE *file, rtx x)
8372 struct mips_address_info addr;
8374 if (mips_classify_address (&addr, x, word_mode, true))
8378 mips_print_operand (file, addr.offset, 0);
8379 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
8382 case ADDRESS_LO_SUM:
8383 mips_print_operand_reloc (file, addr.offset, SYMBOL_CONTEXT_MEM,
8385 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
8388 case ADDRESS_CONST_INT:
8389 output_addr_const (file, x);
8390 fprintf (file, "(%s)", reg_names[GP_REG_FIRST]);
8393 case ADDRESS_SYMBOLIC:
8394 output_addr_const (file, mips_strip_unspec_address (x));
8400 /* Implement TARGET_ENCODE_SECTION_INFO. */
8403 mips_encode_section_info (tree decl, rtx rtl, int first)
8405 default_encode_section_info (decl, rtl, first);
8407 if (TREE_CODE (decl) == FUNCTION_DECL)
8409 rtx symbol = XEXP (rtl, 0);
8410 tree type = TREE_TYPE (decl);
8412 /* Encode whether the symbol is short or long. */
8413 if ((TARGET_LONG_CALLS && !mips_near_type_p (type))
8414 || mips_far_type_p (type))
8415 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
8419 /* Implement TARGET_SELECT_RTX_SECTION. */
8422 mips_select_rtx_section (enum machine_mode mode, rtx x,
8423 unsigned HOST_WIDE_INT align)
8425 /* ??? Consider using mergeable small data sections. */
8426 if (mips_rtx_constant_in_small_data_p (mode))
8427 return get_named_section (NULL, ".sdata", 0);
8429 return default_elf_select_rtx_section (mode, x, align);
8432 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
8434 The complication here is that, with the combination TARGET_ABICALLS
8435 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
8436 absolute addresses, and should therefore not be included in the
8437 read-only part of a DSO. Handle such cases by selecting a normal
8438 data section instead of a read-only one. The logic apes that in
8439 default_function_rodata_section. */
8442 mips_function_rodata_section (tree decl)
8444 if (!TARGET_ABICALLS || TARGET_ABSOLUTE_ABICALLS || TARGET_GPWORD)
8445 return default_function_rodata_section (decl);
8447 if (decl && DECL_SECTION_NAME (decl))
8449 const char *name = DECL_SECTION_NAME (decl);
8450 if (DECL_COMDAT_GROUP (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
8452 char *rname = ASTRDUP (name);
8454 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
8456 else if (flag_function_sections
8457 && flag_data_sections
8458 && strncmp (name, ".text.", 6) == 0)
8460 char *rname = ASTRDUP (name);
8461 memcpy (rname + 1, "data", 4);
8462 return get_section (rname, SECTION_WRITE, decl);
8465 return data_section;
8468 /* Implement TARGET_IN_SMALL_DATA_P. */
8471 mips_in_small_data_p (const_tree decl)
8473 unsigned HOST_WIDE_INT size;
8475 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
8478 /* We don't yet generate small-data references for -mabicalls
8479 or VxWorks RTP code. See the related -G handling in
8480 mips_option_override. */
8481 if (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
8484 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
8488 /* Reject anything that isn't in a known small-data section. */
8489 name = DECL_SECTION_NAME (decl);
8490 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
8493 /* If a symbol is defined externally, the assembler will use the
8494 usual -G rules when deciding how to implement macros. */
8495 if (mips_lo_relocs[SYMBOL_GP_RELATIVE] || !DECL_EXTERNAL (decl))
8498 else if (TARGET_EMBEDDED_DATA)
8500 /* Don't put constants into the small data section: we want them
8501 to be in ROM rather than RAM. */
8502 if (TREE_CODE (decl) != VAR_DECL)
8505 if (TREE_READONLY (decl)
8506 && !TREE_SIDE_EFFECTS (decl)
8507 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
8511 /* Enforce -mlocal-sdata. */
8512 if (!TARGET_LOCAL_SDATA && !TREE_PUBLIC (decl))
8515 /* Enforce -mextern-sdata. */
8516 if (!TARGET_EXTERN_SDATA && DECL_P (decl))
8518 if (DECL_EXTERNAL (decl))
8520 if (DECL_COMMON (decl) && DECL_INITIAL (decl) == NULL)
8524 /* We have traditionally not treated zero-sized objects as small data,
8525 so this is now effectively part of the ABI. */
8526 size = int_size_in_bytes (TREE_TYPE (decl));
8527 return size > 0 && size <= mips_small_data_threshold;
8530 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
8531 anchors for small data: the GP register acts as an anchor in that
8532 case. We also don't want to use them for PC-relative accesses,
8533 where the PC acts as an anchor. */
8536 mips_use_anchors_for_symbol_p (const_rtx symbol)
8538 switch (mips_classify_symbol (symbol, SYMBOL_CONTEXT_MEM))
8540 case SYMBOL_PC_RELATIVE:
8541 case SYMBOL_GP_RELATIVE:
8545 return default_use_anchors_for_symbol_p (symbol);
8549 /* The MIPS debug format wants all automatic variables and arguments
8550 to be in terms of the virtual frame pointer (stack pointer before
8551 any adjustment in the function), while the MIPS 3.0 linker wants
8552 the frame pointer to be the stack pointer after the initial
8553 adjustment. So, we do the adjustment here. The arg pointer (which
8554 is eliminated) points to the virtual frame pointer, while the frame
8555 pointer (which may be eliminated) points to the stack pointer after
8556 the initial adjustments. */
8559 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
8561 rtx offset2 = const0_rtx;
8562 rtx reg = eliminate_constant_term (addr, &offset2);
8565 offset = INTVAL (offset2);
8567 if (reg == stack_pointer_rtx
8568 || reg == frame_pointer_rtx
8569 || reg == hard_frame_pointer_rtx)
8571 offset -= cfun->machine->frame.total_size;
8572 if (reg == hard_frame_pointer_rtx)
8573 offset += cfun->machine->frame.hard_frame_pointer_offset;
8579 /* Implement ASM_OUTPUT_EXTERNAL. */
8582 mips_output_external (FILE *file, tree decl, const char *name)
8584 default_elf_asm_output_external (file, decl, name);
8586 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
8587 set in order to avoid putting out names that are never really
8589 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
8591 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
8593 /* When using assembler macros, emit .extern directives for
8594 all small-data externs so that the assembler knows how
8597 In most cases it would be safe (though pointless) to emit
8598 .externs for other symbols too. One exception is when an
8599 object is within the -G limit but declared by the user to
8600 be in a section other than .sbss or .sdata. */
8601 fputs ("\t.extern\t", file);
8602 assemble_name (file, name);
8603 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n",
8604 int_size_in_bytes (TREE_TYPE (decl)));
8609 /* Implement TARGET_ASM_OUTPUT_SOURCE_FILENAME. */
8612 mips_output_filename (FILE *stream, const char *name)
8614 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
8616 if (write_symbols == DWARF2_DEBUG)
8618 else if (mips_output_filename_first_time)
8620 mips_output_filename_first_time = 0;
8621 num_source_filenames += 1;
8622 current_function_file = name;
8623 fprintf (stream, "\t.file\t%d ", num_source_filenames);
8624 output_quoted_string (stream, name);
8625 putc ('\n', stream);
8627 /* If we are emitting stabs, let dbxout.c handle this (except for
8628 the mips_output_filename_first_time case). */
8629 else if (write_symbols == DBX_DEBUG)
8631 else if (name != current_function_file
8632 && strcmp (name, current_function_file) != 0)
8634 num_source_filenames += 1;
8635 current_function_file = name;
8636 fprintf (stream, "\t.file\t%d ", num_source_filenames);
8637 output_quoted_string (stream, name);
8638 putc ('\n', stream);
8642 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
8644 static void ATTRIBUTE_UNUSED
8645 mips_output_dwarf_dtprel (FILE *file, int size, rtx x)
8650 fputs ("\t.dtprelword\t", file);
8654 fputs ("\t.dtpreldword\t", file);
8660 output_addr_const (file, x);
8661 fputs ("+0x8000", file);
8664 /* Implement TARGET_DWARF_REGISTER_SPAN. */
8667 mips_dwarf_register_span (rtx reg)
8670 enum machine_mode mode;
8672 /* By default, GCC maps increasing register numbers to increasing
8673 memory locations, but paired FPRs are always little-endian,
8674 regardless of the prevailing endianness. */
8675 mode = GET_MODE (reg);
8676 if (FP_REG_P (REGNO (reg))
8677 && TARGET_BIG_ENDIAN
8678 && MAX_FPRS_PER_FMT > 1
8679 && GET_MODE_SIZE (mode) > UNITS_PER_FPREG)
8681 gcc_assert (GET_MODE_SIZE (mode) == UNITS_PER_HWFPVALUE);
8682 high = mips_subword (reg, true);
8683 low = mips_subword (reg, false);
8684 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, high, low));
8690 /* DSP ALU can bypass data with no delays for the following pairs. */
8691 enum insn_code dspalu_bypass_table[][2] =
8693 {CODE_FOR_mips_addsc, CODE_FOR_mips_addwc},
8694 {CODE_FOR_mips_cmpu_eq_qb, CODE_FOR_mips_pick_qb},
8695 {CODE_FOR_mips_cmpu_lt_qb, CODE_FOR_mips_pick_qb},
8696 {CODE_FOR_mips_cmpu_le_qb, CODE_FOR_mips_pick_qb},
8697 {CODE_FOR_mips_cmp_eq_ph, CODE_FOR_mips_pick_ph},
8698 {CODE_FOR_mips_cmp_lt_ph, CODE_FOR_mips_pick_ph},
8699 {CODE_FOR_mips_cmp_le_ph, CODE_FOR_mips_pick_ph},
8700 {CODE_FOR_mips_wrdsp, CODE_FOR_mips_insv}
8704 mips_dspalu_bypass_p (rtx out_insn, rtx in_insn)
8707 int num_bypass = ARRAY_SIZE (dspalu_bypass_table);
8708 enum insn_code out_icode = (enum insn_code) INSN_CODE (out_insn);
8709 enum insn_code in_icode = (enum insn_code) INSN_CODE (in_insn);
8711 for (i = 0; i < num_bypass; i++)
8713 if (out_icode == dspalu_bypass_table[i][0]
8714 && in_icode == dspalu_bypass_table[i][1])
8720 /* Implement ASM_OUTPUT_ASCII. */
8723 mips_output_ascii (FILE *stream, const char *string, size_t len)
8729 fprintf (stream, "\t.ascii\t\"");
8730 for (i = 0; i < len; i++)
8734 c = (unsigned char) string[i];
8737 if (c == '\\' || c == '\"')
8739 putc ('\\', stream);
8747 fprintf (stream, "\\%03o", c);
8751 if (cur_pos > 72 && i+1 < len)
8754 fprintf (stream, "\"\n\t.ascii\t\"");
8757 fprintf (stream, "\"\n");
8760 /* Return the pseudo-op for full SYMBOL_(D)TPREL address *ADDR.
8761 Update *ADDR with the operand that should be printed. */
8764 mips_output_tls_reloc_directive (rtx *addr)
8766 enum mips_symbol_type type;
8768 type = mips_classify_symbolic_expression (*addr, SYMBOL_CONTEXT_LEA);
8769 *addr = mips_strip_unspec_address (*addr);
8773 return Pmode == SImode ? ".dtprelword\t%0" : ".dtpreldword\t%0";
8776 return Pmode == SImode ? ".tprelword\t%0" : ".tpreldword\t%0";
8783 /* Emit either a label, .comm, or .lcomm directive. When using assembler
8784 macros, mark the symbol as written so that mips_asm_output_external
8785 won't emit an .extern for it. STREAM is the output file, NAME is the
8786 name of the symbol, INIT_STRING is the string that should be written
8787 before the symbol and FINAL_STRING is the string that should be
8788 written after it. FINAL_STRING is a printf format that consumes the
8789 remaining arguments. */
8792 mips_declare_object (FILE *stream, const char *name, const char *init_string,
8793 const char *final_string, ...)
8797 fputs (init_string, stream);
8798 assemble_name (stream, name);
8799 va_start (ap, final_string);
8800 vfprintf (stream, final_string, ap);
8803 if (!TARGET_EXPLICIT_RELOCS)
8805 tree name_tree = get_identifier (name);
8806 TREE_ASM_WRITTEN (name_tree) = 1;
8810 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
8811 NAME is the name of the object and ALIGN is the required alignment
8812 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
8813 alignment argument. */
8816 mips_declare_common_object (FILE *stream, const char *name,
8817 const char *init_string,
8818 unsigned HOST_WIDE_INT size,
8819 unsigned int align, bool takes_alignment_p)
8821 if (!takes_alignment_p)
8823 size += (align / BITS_PER_UNIT) - 1;
8824 size -= size % (align / BITS_PER_UNIT);
8825 mips_declare_object (stream, name, init_string,
8826 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
8829 mips_declare_object (stream, name, init_string,
8830 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
8831 size, align / BITS_PER_UNIT);
8834 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
8835 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
8838 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
8839 unsigned HOST_WIDE_INT size,
8842 /* If the target wants uninitialized const declarations in
8843 .rdata then don't put them in .comm. */
8844 if (TARGET_EMBEDDED_DATA
8845 && TARGET_UNINIT_CONST_IN_RODATA
8846 && TREE_CODE (decl) == VAR_DECL
8847 && TREE_READONLY (decl)
8848 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
8850 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
8851 targetm.asm_out.globalize_label (stream, name);
8853 switch_to_section (readonly_data_section);
8854 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
8855 mips_declare_object (stream, name, "",
8856 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
8860 mips_declare_common_object (stream, name, "\n\t.comm\t",
8864 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8865 extern int size_directive_output;
8867 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
8868 definitions except that it uses mips_declare_object to emit the label. */
8871 mips_declare_object_name (FILE *stream, const char *name,
8872 tree decl ATTRIBUTE_UNUSED)
8874 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8875 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
8878 size_directive_output = 0;
8879 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
8883 size_directive_output = 1;
8884 size = int_size_in_bytes (TREE_TYPE (decl));
8885 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8888 mips_declare_object (stream, name, "", ":\n");
8891 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
8894 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
8898 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
8899 if (!flag_inhibit_size_directive
8900 && DECL_SIZE (decl) != 0
8903 && DECL_INITIAL (decl) == error_mark_node
8904 && !size_directive_output)
8908 size_directive_output = 1;
8909 size = int_size_in_bytes (TREE_TYPE (decl));
8910 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8915 /* Return the FOO in the name of the ".mdebug.FOO" section associated
8916 with the current ABI. */
8919 mips_mdebug_abi_name (void)
8932 return TARGET_64BIT ? "eabi64" : "eabi32";
8938 /* Implement TARGET_ASM_FILE_START. */
8941 mips_file_start (void)
8943 default_file_start ();
8945 /* Generate a special section to describe the ABI switches used to
8946 produce the resultant binary. */
8948 /* Record the ABI itself. Modern versions of binutils encode
8949 this information in the ELF header flags, but GDB needs the
8950 information in order to correctly debug binaries produced by
8951 older binutils. See the function mips_gdbarch_init in
8953 fprintf (asm_out_file, "\t.section .mdebug.%s\n\t.previous\n",
8954 mips_mdebug_abi_name ());
8956 /* There is no ELF header flag to distinguish long32 forms of the
8957 EABI from long64 forms. Emit a special section to help tools
8958 such as GDB. Do the same for o64, which is sometimes used with
8960 if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
8961 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n"
8962 "\t.previous\n", TARGET_LONG64 ? 64 : 32);
8964 /* Record the NaN encoding. */
8965 if (HAVE_AS_NAN || mips_nan != MIPS_IEEE_754_DEFAULT)
8966 fprintf (asm_out_file, "\t.nan\t%s\n",
8967 mips_nan == MIPS_IEEE_754_2008 ? "2008" : "legacy");
8969 #ifdef HAVE_AS_GNU_ATTRIBUTE
8973 /* No floating-point operations, -mno-float. */
8974 if (TARGET_NO_FLOAT)
8976 /* Soft-float code, -msoft-float. */
8977 else if (!TARGET_HARD_FLOAT_ABI)
8979 /* Single-float code, -msingle-float. */
8980 else if (!TARGET_DOUBLE_FLOAT)
8982 /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64. */
8983 else if (!TARGET_64BIT && TARGET_FLOAT64)
8985 /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */
8989 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n", attr);
8993 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
8994 if (TARGET_ABICALLS)
8996 fprintf (asm_out_file, "\t.abicalls\n");
8997 if (TARGET_ABICALLS_PIC0)
8998 fprintf (asm_out_file, "\t.option\tpic0\n");
9001 if (flag_verbose_asm)
9002 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
9004 mips_small_data_threshold, mips_arch_info->name, mips_isa);
9007 /* Implement TARGET_ASM_CODE_END. */
9010 mips_code_end (void)
9012 mips_finish_stub (&mips16_rdhwr_stub);
9013 mips_finish_stub (&mips16_get_fcsr_stub);
9014 mips_finish_stub (&mips16_set_fcsr_stub);
9017 /* Make the last instruction frame-related and note that it performs
9018 the operation described by FRAME_PATTERN. */
9021 mips_set_frame_expr (rtx frame_pattern)
9025 insn = get_last_insn ();
9026 RTX_FRAME_RELATED_P (insn) = 1;
9027 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
9032 /* Return a frame-related rtx that stores REG at MEM.
9033 REG must be a single register. */
9036 mips_frame_set (rtx mem, rtx reg)
9040 set = gen_rtx_SET (VOIDmode, mem, reg);
9041 RTX_FRAME_RELATED_P (set) = 1;
9046 /* Record that the epilogue has restored call-saved register REG. */
9049 mips_add_cfa_restore (rtx reg)
9051 mips_epilogue.cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg,
9052 mips_epilogue.cfa_restores);
9055 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
9056 mips16e_s2_s8_regs[X], it must also save the registers in indexes
9057 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
9058 static const unsigned char mips16e_s2_s8_regs[] = {
9059 30, 23, 22, 21, 20, 19, 18
9061 static const unsigned char mips16e_a0_a3_regs[] = {
9065 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
9066 ordered from the uppermost in memory to the lowest in memory. */
9067 static const unsigned char mips16e_save_restore_regs[] = {
9068 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
9071 /* Return the index of the lowest X in the range [0, SIZE) for which
9072 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
9075 mips16e_find_first_register (unsigned int mask, const unsigned char *regs,
9080 for (i = 0; i < size; i++)
9081 if (BITSET_P (mask, regs[i]))
9087 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
9088 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
9089 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
9090 is true for all indexes (X, SIZE). */
9093 mips16e_mask_registers (unsigned int *mask_ptr, const unsigned char *regs,
9094 unsigned int size, unsigned int *num_regs_ptr)
9098 i = mips16e_find_first_register (*mask_ptr, regs, size);
9099 for (i++; i < size; i++)
9100 if (!BITSET_P (*mask_ptr, regs[i]))
9103 *mask_ptr |= 1 << regs[i];
9107 /* Return a simplified form of X using the register values in REG_VALUES.
9108 REG_VALUES[R] is the last value assigned to hard register R, or null
9109 if R has not been modified.
9111 This function is rather limited, but is good enough for our purposes. */
9114 mips16e_collect_propagate_value (rtx x, rtx *reg_values)
9116 x = avoid_constant_pool_reference (x);
9120 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
9121 return simplify_gen_unary (GET_CODE (x), GET_MODE (x),
9122 x0, GET_MODE (XEXP (x, 0)));
9125 if (ARITHMETIC_P (x))
9127 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
9128 rtx x1 = mips16e_collect_propagate_value (XEXP (x, 1), reg_values);
9129 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), x0, x1);
9133 && reg_values[REGNO (x)]
9134 && !rtx_unstable_p (reg_values[REGNO (x)]))
9135 return reg_values[REGNO (x)];
9140 /* Return true if (set DEST SRC) stores an argument register into its
9141 caller-allocated save slot, storing the number of that argument
9142 register in *REGNO_PTR if so. REG_VALUES is as for
9143 mips16e_collect_propagate_value. */
9146 mips16e_collect_argument_save_p (rtx dest, rtx src, rtx *reg_values,
9147 unsigned int *regno_ptr)
9149 unsigned int argno, regno;
9150 HOST_WIDE_INT offset, required_offset;
9153 /* Check that this is a word-mode store. */
9154 if (!MEM_P (dest) || !REG_P (src) || GET_MODE (dest) != word_mode)
9157 /* Check that the register being saved is an unmodified argument
9159 regno = REGNO (src);
9160 if (!IN_RANGE (regno, GP_ARG_FIRST, GP_ARG_LAST) || reg_values[regno])
9162 argno = regno - GP_ARG_FIRST;
9164 /* Check whether the address is an appropriate stack-pointer or
9165 frame-pointer access. */
9166 addr = mips16e_collect_propagate_value (XEXP (dest, 0), reg_values);
9167 mips_split_plus (addr, &base, &offset);
9168 required_offset = cfun->machine->frame.total_size + argno * UNITS_PER_WORD;
9169 if (base == hard_frame_pointer_rtx)
9170 required_offset -= cfun->machine->frame.hard_frame_pointer_offset;
9171 else if (base != stack_pointer_rtx)
9173 if (offset != required_offset)
9180 /* A subroutine of mips_expand_prologue, called only when generating
9181 MIPS16e SAVE instructions. Search the start of the function for any
9182 instructions that save argument registers into their caller-allocated
9183 save slots. Delete such instructions and return a value N such that
9184 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
9185 instructions redundant. */
9188 mips16e_collect_argument_saves (void)
9190 rtx reg_values[FIRST_PSEUDO_REGISTER];
9191 rtx_insn *insn, *next;
9193 unsigned int nargs, regno;
9195 push_topmost_sequence ();
9197 memset (reg_values, 0, sizeof (reg_values));
9198 for (insn = get_insns (); insn; insn = next)
9200 next = NEXT_INSN (insn);
9201 if (NOTE_P (insn) || DEBUG_INSN_P (insn))
9207 set = PATTERN (insn);
9208 if (GET_CODE (set) != SET)
9211 dest = SET_DEST (set);
9212 src = SET_SRC (set);
9213 if (mips16e_collect_argument_save_p (dest, src, reg_values, ®no))
9215 if (!BITSET_P (cfun->machine->frame.mask, regno))
9218 nargs = MAX (nargs, (regno - GP_ARG_FIRST) + 1);
9221 else if (REG_P (dest) && GET_MODE (dest) == word_mode)
9222 reg_values[REGNO (dest)]
9223 = mips16e_collect_propagate_value (src, reg_values);
9227 pop_topmost_sequence ();
9232 /* Return a move between register REGNO and memory location SP + OFFSET.
9233 REG_PARM_P is true if SP + OFFSET belongs to REG_PARM_STACK_SPACE.
9234 Make the move a load if RESTORE_P, otherwise make it a store. */
9237 mips16e_save_restore_reg (bool restore_p, bool reg_parm_p,
9238 HOST_WIDE_INT offset, unsigned int regno)
9242 mem = gen_frame_mem (SImode, plus_constant (Pmode, stack_pointer_rtx,
9244 reg = gen_rtx_REG (SImode, regno);
9247 mips_add_cfa_restore (reg);
9248 return gen_rtx_SET (VOIDmode, reg, mem);
9251 return gen_rtx_SET (VOIDmode, mem, reg);
9252 return mips_frame_set (mem, reg);
9255 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
9256 The instruction must:
9258 - Allocate or deallocate SIZE bytes in total; SIZE is known
9261 - Save or restore as many registers in *MASK_PTR as possible.
9262 The instruction saves the first registers at the top of the
9263 allocated area, with the other registers below it.
9265 - Save NARGS argument registers above the allocated area.
9267 (NARGS is always zero if RESTORE_P.)
9269 The SAVE and RESTORE instructions cannot save and restore all general
9270 registers, so there may be some registers left over for the caller to
9271 handle. Destructively modify *MASK_PTR so that it contains the registers
9272 that still need to be saved or restored. The caller can save these
9273 registers in the memory immediately below *OFFSET_PTR, which is a
9274 byte offset from the bottom of the allocated stack area. */
9277 mips16e_build_save_restore (bool restore_p, unsigned int *mask_ptr,
9278 HOST_WIDE_INT *offset_ptr, unsigned int nargs,
9282 HOST_WIDE_INT offset, top_offset;
9283 unsigned int i, regno;
9286 gcc_assert (cfun->machine->frame.num_fp == 0);
9288 /* Calculate the number of elements in the PARALLEL. We need one element
9289 for the stack adjustment, one for each argument register save, and one
9290 for each additional register move. */
9292 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
9293 if (BITSET_P (*mask_ptr, mips16e_save_restore_regs[i]))
9296 /* Create the final PARALLEL. */
9297 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (n));
9300 /* Add the stack pointer adjustment. */
9301 set = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
9302 plus_constant (Pmode, stack_pointer_rtx,
9303 restore_p ? size : -size));
9304 RTX_FRAME_RELATED_P (set) = 1;
9305 XVECEXP (pattern, 0, n++) = set;
9307 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
9308 top_offset = restore_p ? size : 0;
9310 /* Save the arguments. */
9311 for (i = 0; i < nargs; i++)
9313 offset = top_offset + i * UNITS_PER_WORD;
9314 set = mips16e_save_restore_reg (restore_p, true, offset,
9316 XVECEXP (pattern, 0, n++) = set;
9319 /* Then fill in the other register moves. */
9320 offset = top_offset;
9321 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
9323 regno = mips16e_save_restore_regs[i];
9324 if (BITSET_P (*mask_ptr, regno))
9326 offset -= UNITS_PER_WORD;
9327 set = mips16e_save_restore_reg (restore_p, false, offset, regno);
9328 XVECEXP (pattern, 0, n++) = set;
9329 *mask_ptr &= ~(1 << regno);
9333 /* Tell the caller what offset it should use for the remaining registers. */
9334 *offset_ptr = size + (offset - top_offset);
9336 gcc_assert (n == XVECLEN (pattern, 0));
9341 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
9342 pointer. Return true if PATTERN matches the kind of instruction
9343 generated by mips16e_build_save_restore. If INFO is nonnull,
9344 initialize it when returning true. */
9347 mips16e_save_restore_pattern_p (rtx pattern, HOST_WIDE_INT adjust,
9348 struct mips16e_save_restore_info *info)
9350 unsigned int i, nargs, mask, extra;
9351 HOST_WIDE_INT top_offset, save_offset, offset;
9352 rtx set, reg, mem, base;
9355 if (!GENERATE_MIPS16E_SAVE_RESTORE)
9358 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
9359 top_offset = adjust > 0 ? adjust : 0;
9361 /* Interpret all other members of the PARALLEL. */
9362 save_offset = top_offset - UNITS_PER_WORD;
9366 for (n = 1; n < XVECLEN (pattern, 0); n++)
9368 /* Check that we have a SET. */
9369 set = XVECEXP (pattern, 0, n);
9370 if (GET_CODE (set) != SET)
9373 /* Check that the SET is a load (if restoring) or a store
9375 mem = adjust > 0 ? SET_SRC (set) : SET_DEST (set);
9379 /* Check that the address is the sum of the stack pointer and a
9380 possibly-zero constant offset. */
9381 mips_split_plus (XEXP (mem, 0), &base, &offset);
9382 if (base != stack_pointer_rtx)
9385 /* Check that SET's other operand is a register. */
9386 reg = adjust > 0 ? SET_DEST (set) : SET_SRC (set);
9390 /* Check for argument saves. */
9391 if (offset == top_offset + nargs * UNITS_PER_WORD
9392 && REGNO (reg) == GP_ARG_FIRST + nargs)
9394 else if (offset == save_offset)
9396 while (mips16e_save_restore_regs[i++] != REGNO (reg))
9397 if (i == ARRAY_SIZE (mips16e_save_restore_regs))
9400 mask |= 1 << REGNO (reg);
9401 save_offset -= UNITS_PER_WORD;
9407 /* Check that the restrictions on register ranges are met. */
9409 mips16e_mask_registers (&mask, mips16e_s2_s8_regs,
9410 ARRAY_SIZE (mips16e_s2_s8_regs), &extra);
9411 mips16e_mask_registers (&mask, mips16e_a0_a3_regs,
9412 ARRAY_SIZE (mips16e_a0_a3_regs), &extra);
9416 /* Make sure that the topmost argument register is not saved twice.
9417 The checks above ensure that the same is then true for the other
9418 argument registers. */
9419 if (nargs > 0 && BITSET_P (mask, GP_ARG_FIRST + nargs - 1))
9422 /* Pass back information, if requested. */
9425 info->nargs = nargs;
9427 info->size = (adjust > 0 ? adjust : -adjust);
9433 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
9434 for the register range [MIN_REG, MAX_REG]. Return a pointer to
9435 the null terminator. */
9438 mips16e_add_register_range (char *s, unsigned int min_reg,
9439 unsigned int max_reg)
9441 if (min_reg != max_reg)
9442 s += sprintf (s, ",%s-%s", reg_names[min_reg], reg_names[max_reg]);
9444 s += sprintf (s, ",%s", reg_names[min_reg]);
9448 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
9449 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
9452 mips16e_output_save_restore (rtx pattern, HOST_WIDE_INT adjust)
9454 static char buffer[300];
9456 struct mips16e_save_restore_info info;
9457 unsigned int i, end;
9460 /* Parse the pattern. */
9461 if (!mips16e_save_restore_pattern_p (pattern, adjust, &info))
9464 /* Add the mnemonic. */
9465 s = strcpy (buffer, adjust > 0 ? "restore\t" : "save\t");
9468 /* Save the arguments. */
9470 s += sprintf (s, "%s-%s,", reg_names[GP_ARG_FIRST],
9471 reg_names[GP_ARG_FIRST + info.nargs - 1]);
9472 else if (info.nargs == 1)
9473 s += sprintf (s, "%s,", reg_names[GP_ARG_FIRST]);
9475 /* Emit the amount of stack space to allocate or deallocate. */
9476 s += sprintf (s, "%d", (int) info.size);
9478 /* Save or restore $16. */
9479 if (BITSET_P (info.mask, 16))
9480 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 16]);
9482 /* Save or restore $17. */
9483 if (BITSET_P (info.mask, 17))
9484 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 17]);
9486 /* Save or restore registers in the range $s2...$s8, which
9487 mips16e_s2_s8_regs lists in decreasing order. Note that this
9488 is a software register range; the hardware registers are not
9489 numbered consecutively. */
9490 end = ARRAY_SIZE (mips16e_s2_s8_regs);
9491 i = mips16e_find_first_register (info.mask, mips16e_s2_s8_regs, end);
9493 s = mips16e_add_register_range (s, mips16e_s2_s8_regs[end - 1],
9494 mips16e_s2_s8_regs[i]);
9496 /* Save or restore registers in the range $a0...$a3. */
9497 end = ARRAY_SIZE (mips16e_a0_a3_regs);
9498 i = mips16e_find_first_register (info.mask, mips16e_a0_a3_regs, end);
9500 s = mips16e_add_register_range (s, mips16e_a0_a3_regs[i],
9501 mips16e_a0_a3_regs[end - 1]);
9503 /* Save or restore $31. */
9504 if (BITSET_P (info.mask, RETURN_ADDR_REGNUM))
9505 s += sprintf (s, ",%s", reg_names[RETURN_ADDR_REGNUM]);
9510 /* Return true if the current function returns its value in a floating-point
9511 register in MIPS16 mode. */
9514 mips16_cfun_returns_in_fpr_p (void)
9516 tree return_type = DECL_RESULT (current_function_decl);
9517 return (TARGET_MIPS16
9518 && TARGET_HARD_FLOAT_ABI
9519 && !aggregate_value_p (return_type, current_function_decl)
9520 && mips_return_mode_in_fpr_p (DECL_MODE (return_type)));
9523 /* Return true if predicate PRED is true for at least one instruction.
9524 Cache the result in *CACHE, and assume that the result is true
9525 if *CACHE is already true. */
9528 mips_find_gp_ref (bool *cache, bool (*pred) (rtx_insn *))
9534 push_topmost_sequence ();
9535 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9536 if (USEFUL_INSN_P (insn) && pred (insn))
9541 pop_topmost_sequence ();
9546 /* Return true if INSN refers to the global pointer in an "inflexible" way.
9547 See mips_cfun_has_inflexible_gp_ref_p for details. */
9550 mips_insn_has_inflexible_gp_ref_p (rtx_insn *insn)
9552 /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE
9553 indicate that the target could be a traditional MIPS
9554 lazily-binding stub. */
9555 return find_reg_fusage (insn, USE, pic_offset_table_rtx);
9558 /* Return true if the current function refers to the global pointer
9559 in a way that forces $28 to be valid. This means that we can't
9560 change the choice of global pointer, even for NewABI code.
9562 One example of this (and one which needs several checks) is that
9563 $28 must be valid when calling traditional MIPS lazy-binding stubs.
9564 (This restriction does not apply to PLTs.) */
9567 mips_cfun_has_inflexible_gp_ref_p (void)
9569 /* If the function has a nonlocal goto, $28 must hold the correct
9570 global pointer for the target function. That is, the target
9571 of the goto implicitly uses $28. */
9572 if (crtl->has_nonlocal_goto)
9575 if (TARGET_ABICALLS_PIC2)
9577 /* Symbolic accesses implicitly use the global pointer unless
9578 -mexplicit-relocs is in effect. JAL macros to symbolic addresses
9579 might go to traditional MIPS lazy-binding stubs. */
9580 if (!TARGET_EXPLICIT_RELOCS)
9583 /* FUNCTION_PROFILER includes a JAL to _mcount, which again
9584 can be lazily-bound. */
9588 /* MIPS16 functions that return in FPRs need to call an
9589 external libgcc routine. This call is only made explict
9590 during mips_expand_epilogue, and it too might be lazily bound. */
9591 if (mips16_cfun_returns_in_fpr_p ())
9595 return mips_find_gp_ref (&cfun->machine->has_inflexible_gp_insn_p,
9596 mips_insn_has_inflexible_gp_ref_p);
9599 /* Return true if INSN refers to the global pointer in a "flexible" way.
9600 See mips_cfun_has_flexible_gp_ref_p for details. */
9603 mips_insn_has_flexible_gp_ref_p (rtx_insn *insn)
9605 return (get_attr_got (insn) != GOT_UNSET
9606 || mips_small_data_pattern_p (PATTERN (insn))
9607 || reg_overlap_mentioned_p (pic_offset_table_rtx, PATTERN (insn)));
9610 /* Return true if the current function references the global pointer,
9611 but if those references do not inherently require the global pointer
9612 to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */
9615 mips_cfun_has_flexible_gp_ref_p (void)
9617 /* Reload can sometimes introduce constant pool references
9618 into a function that otherwise didn't need them. For example,
9619 suppose we have an instruction like:
9621 (set (reg:DF R1) (float:DF (reg:SI R2)))
9623 If R2 turns out to be a constant such as 1, the instruction may
9624 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
9625 the option of using this constant if R2 doesn't get allocated
9628 In cases like these, reload will have added the constant to the
9629 pool but no instruction will yet refer to it. */
9630 if (TARGET_ABICALLS_PIC2 && !reload_completed && crtl->uses_const_pool)
9633 return mips_find_gp_ref (&cfun->machine->has_flexible_gp_insn_p,
9634 mips_insn_has_flexible_gp_ref_p);
9637 /* Return the register that should be used as the global pointer
9638 within this function. Return INVALID_REGNUM if the function
9639 doesn't need a global pointer. */
9642 mips_global_pointer (void)
9646 /* $gp is always available unless we're using a GOT. */
9647 if (!TARGET_USE_GOT)
9648 return GLOBAL_POINTER_REGNUM;
9650 /* If there are inflexible references to $gp, we must use the
9651 standard register. */
9652 if (mips_cfun_has_inflexible_gp_ref_p ())
9653 return GLOBAL_POINTER_REGNUM;
9655 /* If there are no current references to $gp, then the only uses
9656 we can introduce later are those involved in long branches. */
9657 if (TARGET_ABSOLUTE_JUMPS && !mips_cfun_has_flexible_gp_ref_p ())
9658 return INVALID_REGNUM;
9660 /* If the global pointer is call-saved, try to use a call-clobbered
9662 if (TARGET_CALL_SAVED_GP && crtl->is_leaf)
9663 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
9664 if (!df_regs_ever_live_p (regno)
9665 && call_really_used_regs[regno]
9666 && !fixed_regs[regno]
9667 && regno != PIC_FUNCTION_ADDR_REGNUM)
9670 return GLOBAL_POINTER_REGNUM;
9673 /* Return true if the current function's prologue must load the global
9674 pointer value into pic_offset_table_rtx and store the same value in
9675 the function's cprestore slot (if any).
9677 One problem we have to deal with is that, when emitting GOT-based
9678 position independent code, long-branch sequences will need to load
9679 the address of the branch target from the GOT. We don't know until
9680 the very end of compilation whether (and where) the function needs
9681 long branches, so we must ensure that _any_ branch can access the
9682 global pointer in some form. However, we do not want to pessimize
9683 the usual case in which all branches are short.
9685 We handle this as follows:
9687 (1) During reload, we set cfun->machine->global_pointer to
9688 INVALID_REGNUM if we _know_ that the current function
9689 doesn't need a global pointer. This is only valid if
9690 long branches don't need the GOT.
9692 Otherwise, we assume that we might need a global pointer
9693 and pick an appropriate register.
9695 (2) If cfun->machine->global_pointer != INVALID_REGNUM,
9696 we ensure that the global pointer is available at every
9697 block boundary bar entry and exit. We do this in one of two ways:
9699 - If the function has a cprestore slot, we ensure that this
9700 slot is valid at every branch. However, as explained in
9701 point (6) below, there is no guarantee that pic_offset_table_rtx
9702 itself is valid if new uses of the global pointer are introduced
9703 after the first post-epilogue split.
9705 We guarantee that the cprestore slot is valid by loading it
9706 into a fake register, CPRESTORE_SLOT_REGNUM. We then make
9707 this register live at every block boundary bar function entry
9708 and exit. It is then invalid to move the load (and thus the
9709 preceding store) across a block boundary.
9711 - If the function has no cprestore slot, we guarantee that
9712 pic_offset_table_rtx itself is valid at every branch.
9714 See mips_eh_uses for the handling of the register liveness.
9716 (3) During prologue and epilogue generation, we emit "ghost"
9717 placeholder instructions to manipulate the global pointer.
9719 (4) During prologue generation, we set cfun->machine->must_initialize_gp_p
9720 and cfun->machine->must_restore_gp_when_clobbered_p if we already know
9721 that the function needs a global pointer. (There is no need to set
9722 them earlier than this, and doing it as late as possible leads to
9723 fewer false positives.)
9725 (5) If cfun->machine->must_initialize_gp_p is true during a
9726 split_insns pass, we split the ghost instructions into real
9727 instructions. These split instructions can then be optimized in
9728 the usual way. Otherwise, we keep the ghost instructions intact,
9729 and optimize for the case where they aren't needed. We still
9730 have the option of splitting them later, if we need to introduce
9731 new uses of the global pointer.
9733 For example, the scheduler ignores a ghost instruction that
9734 stores $28 to the stack, but it handles the split form of
9735 the ghost instruction as an ordinary store.
9737 (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p
9738 is true during the first post-epilogue split_insns pass, we split
9739 calls and restore_gp patterns into instructions that explicitly
9740 load pic_offset_table_rtx from the cprestore slot. Otherwise,
9741 we split these patterns into instructions that _don't_ load from
9744 If cfun->machine->must_restore_gp_when_clobbered_p is true at the
9745 time of the split, then any instructions that exist at that time
9746 can make free use of pic_offset_table_rtx. However, if we want
9747 to introduce new uses of the global pointer after the split,
9748 we must explicitly load the value from the cprestore slot, since
9749 pic_offset_table_rtx itself might not be valid at a given point
9752 The idea is that we want to be able to delete redundant
9753 loads from the cprestore slot in the usual case where no
9754 long branches are needed.
9756 (7) If cfun->machine->must_initialize_gp_p is still false at the end
9757 of md_reorg, we decide whether the global pointer is needed for
9758 long branches. If so, we set cfun->machine->must_initialize_gp_p
9759 to true and split the ghost instructions into real instructions
9762 Note that the ghost instructions must have a zero length for three reasons:
9764 - Giving the length of the underlying $gp sequence might cause
9765 us to use long branches in cases where they aren't really needed.
9767 - They would perturb things like alignment calculations.
9769 - More importantly, the hazard detection in md_reorg relies on
9770 empty instructions having a zero length.
9772 If we find a long branch and split the ghost instructions at the
9773 end of md_reorg, the split could introduce more long branches.
9774 That isn't a problem though, because we still do the split before
9775 the final shorten_branches pass.
9777 This is extremely ugly, but it seems like the best compromise between
9778 correctness and efficiency. */
9781 mips_must_initialize_gp_p (void)
9783 return cfun->machine->must_initialize_gp_p;
9786 /* Return true if REGNO is a register that is ordinarily call-clobbered
9787 but must nevertheless be preserved by an interrupt handler. */
9790 mips_interrupt_extra_call_saved_reg_p (unsigned int regno)
9792 if (MD_REG_P (regno))
9795 if (TARGET_DSP && DSP_ACC_REG_P (regno))
9798 if (GP_REG_P (regno) && !cfun->machine->use_shadow_register_set_p)
9800 /* $0 is hard-wired. */
9801 if (regno == GP_REG_FIRST)
9804 /* The interrupt handler can treat kernel registers as
9805 scratch registers. */
9806 if (KERNEL_REG_P (regno))
9809 /* The function will return the stack pointer to its original value
9811 if (regno == STACK_POINTER_REGNUM)
9814 /* Otherwise, return true for registers that aren't ordinarily
9816 return call_really_used_regs[regno];
9822 /* Return true if the current function should treat register REGNO
9826 mips_cfun_call_saved_reg_p (unsigned int regno)
9828 /* If the user makes an ordinarily-call-saved register global,
9829 that register is no longer call-saved. */
9830 if (global_regs[regno])
9833 /* Interrupt handlers need to save extra registers. */
9834 if (cfun->machine->interrupt_handler_p
9835 && mips_interrupt_extra_call_saved_reg_p (regno))
9838 /* call_insns preserve $28 unless they explicitly say otherwise,
9839 so call_really_used_regs[] treats $28 as call-saved. However,
9840 we want the ABI property rather than the default call_insn
9842 return (regno == GLOBAL_POINTER_REGNUM
9843 ? TARGET_CALL_SAVED_GP
9844 : !call_really_used_regs[regno]);
9847 /* Return true if the function body might clobber register REGNO.
9848 We know that REGNO is call-saved. */
9851 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno)
9853 /* Some functions should be treated as clobbering all call-saved
9855 if (crtl->saves_all_registers)
9858 /* DF handles cases where a register is explicitly referenced in
9859 the rtl. Incoming values are passed in call-clobbered registers,
9860 so we can assume that any live call-saved register is set within
9862 if (df_regs_ever_live_p (regno))
9865 /* Check for registers that are clobbered by FUNCTION_PROFILER.
9866 These clobbers are not explicit in the rtl. */
9867 if (crtl->profile && MIPS_SAVE_REG_FOR_PROFILING_P (regno))
9870 /* If we're using a call-saved global pointer, the function's
9871 prologue will need to set it up. */
9872 if (cfun->machine->global_pointer == regno)
9875 /* The function's prologue will need to set the frame pointer if
9876 frame_pointer_needed. */
9877 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
9880 /* If a MIPS16 function returns a value in FPRs, its epilogue
9881 will need to call an external libgcc routine. This yet-to-be
9882 generated call_insn will clobber $31. */
9883 if (regno == RETURN_ADDR_REGNUM && mips16_cfun_returns_in_fpr_p ())
9886 /* If REGNO is ordinarily call-clobbered, we must assume that any
9887 called function could modify it. */
9888 if (cfun->machine->interrupt_handler_p
9890 && mips_interrupt_extra_call_saved_reg_p (regno))
9896 /* Return true if the current function must save register REGNO. */
9899 mips_save_reg_p (unsigned int regno)
9901 if (mips_cfun_call_saved_reg_p (regno))
9903 if (mips_cfun_might_clobber_call_saved_reg_p (regno))
9906 /* Save both registers in an FPR pair if either one is used. This is
9907 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
9908 register to be used without the even register. */
9909 if (FP_REG_P (regno)
9910 && MAX_FPRS_PER_FMT == 2
9911 && mips_cfun_might_clobber_call_saved_reg_p (regno + 1))
9915 /* We need to save the incoming return address if __builtin_eh_return
9916 is being used to set a different return address. */
9917 if (regno == RETURN_ADDR_REGNUM && crtl->calls_eh_return)
9923 /* Populate the current function's mips_frame_info structure.
9925 MIPS stack frames look like:
9927 +-------------------------------+
9929 | incoming stack arguments |
9931 +-------------------------------+
9933 | caller-allocated save area |
9934 A | for register arguments |
9936 +-------------------------------+ <-- incoming stack pointer
9938 | callee-allocated save area |
9939 B | for arguments that are |
9940 | split between registers and |
9943 +-------------------------------+ <-- arg_pointer_rtx
9945 C | callee-allocated save area |
9946 | for register varargs |
9948 +-------------------------------+ <-- frame_pointer_rtx
9949 | | + cop0_sp_offset
9950 | COP0 reg save area | + UNITS_PER_WORD
9952 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
9953 | | + UNITS_PER_WORD
9954 | accumulator save area |
9956 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
9957 | | + UNITS_PER_HWFPVALUE
9960 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset
9961 | | + UNITS_PER_WORD
9964 +-------------------------------+ <-- frame_pointer_rtx with
9965 | | \ -fstack-protector
9966 | local variables | | var_size
9968 +-------------------------------+
9970 | $gp save area | | cprestore_size
9972 P +-------------------------------+ <-- hard_frame_pointer_rtx for
9974 | outgoing stack arguments | |
9976 +-------------------------------+ | args_size
9978 | caller-allocated save area | |
9979 | for register arguments | |
9981 +-------------------------------+ <-- stack_pointer_rtx
9982 frame_pointer_rtx without
9984 hard_frame_pointer_rtx for
9987 At least two of A, B and C will be empty.
9989 Dynamic stack allocations such as alloca insert data at point P.
9990 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
9991 hard_frame_pointer_rtx unchanged. */
9994 mips_compute_frame_info (void)
9996 struct mips_frame_info *frame;
9997 HOST_WIDE_INT offset, size;
9998 unsigned int regno, i;
10000 /* Set this function's interrupt properties. */
10001 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
10003 if (mips_isa_rev < 2)
10004 error ("the %<interrupt%> attribute requires a MIPS32r2 processor or greater");
10005 else if (TARGET_HARD_FLOAT)
10006 error ("the %<interrupt%> attribute requires %<-msoft-float%>");
10007 else if (TARGET_MIPS16)
10008 error ("interrupt handlers cannot be MIPS16 functions");
10011 cfun->machine->interrupt_handler_p = true;
10012 cfun->machine->use_shadow_register_set_p =
10013 mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl));
10014 cfun->machine->keep_interrupts_masked_p =
10015 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl));
10016 cfun->machine->use_debug_exception_return_p =
10017 mips_use_debug_exception_return_p (TREE_TYPE
10018 (current_function_decl));
10022 frame = &cfun->machine->frame;
10023 memset (frame, 0, sizeof (*frame));
10024 size = get_frame_size ();
10026 cfun->machine->global_pointer = mips_global_pointer ();
10028 /* The first two blocks contain the outgoing argument area and the $gp save
10029 slot. This area isn't needed in leaf functions, but if the
10030 target-independent frame size is nonzero, we have already committed to
10031 allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */
10032 if ((size == 0 || FRAME_GROWS_DOWNWARD) && crtl->is_leaf)
10034 /* The MIPS 3.0 linker does not like functions that dynamically
10035 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
10036 looks like we are trying to create a second frame pointer to the
10037 function, so allocate some stack space to make it happy. */
10038 if (cfun->calls_alloca)
10039 frame->args_size = REG_PARM_STACK_SPACE (cfun->decl);
10041 frame->args_size = 0;
10042 frame->cprestore_size = 0;
10046 frame->args_size = crtl->outgoing_args_size;
10047 frame->cprestore_size = MIPS_GP_SAVE_AREA_SIZE;
10049 offset = frame->args_size + frame->cprestore_size;
10051 /* Move above the local variables. */
10052 frame->var_size = MIPS_STACK_ALIGN (size);
10053 offset += frame->var_size;
10055 /* Find out which GPRs we need to save. */
10056 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
10057 if (mips_save_reg_p (regno))
10060 frame->mask |= 1 << (regno - GP_REG_FIRST);
10063 /* If this function calls eh_return, we must also save and restore the
10064 EH data registers. */
10065 if (crtl->calls_eh_return)
10066 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; i++)
10069 frame->mask |= 1 << (EH_RETURN_DATA_REGNO (i) - GP_REG_FIRST);
10072 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
10073 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
10074 save all later registers too. */
10075 if (GENERATE_MIPS16E_SAVE_RESTORE)
10077 mips16e_mask_registers (&frame->mask, mips16e_s2_s8_regs,
10078 ARRAY_SIZE (mips16e_s2_s8_regs), &frame->num_gp);
10079 mips16e_mask_registers (&frame->mask, mips16e_a0_a3_regs,
10080 ARRAY_SIZE (mips16e_a0_a3_regs), &frame->num_gp);
10083 /* Move above the GPR save area. */
10084 if (frame->num_gp > 0)
10086 offset += MIPS_STACK_ALIGN (frame->num_gp * UNITS_PER_WORD);
10087 frame->gp_sp_offset = offset - UNITS_PER_WORD;
10090 /* Find out which FPRs we need to save. This loop must iterate over
10091 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
10092 if (TARGET_HARD_FLOAT)
10093 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += MAX_FPRS_PER_FMT)
10094 if (mips_save_reg_p (regno))
10096 frame->num_fp += MAX_FPRS_PER_FMT;
10097 frame->fmask |= ~(~0 << MAX_FPRS_PER_FMT) << (regno - FP_REG_FIRST);
10100 /* Move above the FPR save area. */
10101 if (frame->num_fp > 0)
10103 offset += MIPS_STACK_ALIGN (frame->num_fp * UNITS_PER_FPREG);
10104 frame->fp_sp_offset = offset - UNITS_PER_HWFPVALUE;
10107 /* Add in space for the interrupt context information. */
10108 if (cfun->machine->interrupt_handler_p)
10111 if (mips_save_reg_p (LO_REGNUM) || mips_save_reg_p (HI_REGNUM))
10114 frame->acc_mask |= (1 << 0);
10117 /* Check accumulators 1, 2, 3. */
10118 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
10119 if (mips_save_reg_p (i) || mips_save_reg_p (i + 1))
10122 frame->acc_mask |= 1 << (((i - DSP_ACC_REG_FIRST) / 2) + 1);
10125 /* All interrupt context functions need space to preserve STATUS. */
10126 frame->num_cop0_regs++;
10128 /* If we don't keep interrupts masked, we need to save EPC. */
10129 if (!cfun->machine->keep_interrupts_masked_p)
10130 frame->num_cop0_regs++;
10133 /* Move above the accumulator save area. */
10134 if (frame->num_acc > 0)
10136 /* Each accumulator needs 2 words. */
10137 offset += frame->num_acc * 2 * UNITS_PER_WORD;
10138 frame->acc_sp_offset = offset - UNITS_PER_WORD;
10141 /* Move above the COP0 register save area. */
10142 if (frame->num_cop0_regs > 0)
10144 offset += frame->num_cop0_regs * UNITS_PER_WORD;
10145 frame->cop0_sp_offset = offset - UNITS_PER_WORD;
10148 /* Move above the callee-allocated varargs save area. */
10149 offset += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
10150 frame->arg_pointer_offset = offset;
10152 /* Move above the callee-allocated area for pretend stack arguments. */
10153 offset += crtl->args.pretend_args_size;
10154 frame->total_size = offset;
10156 /* Work out the offsets of the save areas from the top of the frame. */
10157 if (frame->gp_sp_offset > 0)
10158 frame->gp_save_offset = frame->gp_sp_offset - offset;
10159 if (frame->fp_sp_offset > 0)
10160 frame->fp_save_offset = frame->fp_sp_offset - offset;
10161 if (frame->acc_sp_offset > 0)
10162 frame->acc_save_offset = frame->acc_sp_offset - offset;
10163 if (frame->num_cop0_regs > 0)
10164 frame->cop0_save_offset = frame->cop0_sp_offset - offset;
10166 /* MIPS16 code offsets the frame pointer by the size of the outgoing
10167 arguments. This tends to increase the chances of using unextended
10168 instructions for local variables and incoming arguments. */
10170 frame->hard_frame_pointer_offset = frame->args_size;
10173 /* Return the style of GP load sequence that is being used for the
10174 current function. */
10176 enum mips_loadgp_style
10177 mips_current_loadgp_style (void)
10179 if (!TARGET_USE_GOT || cfun->machine->global_pointer == INVALID_REGNUM)
10180 return LOADGP_NONE;
10182 if (TARGET_RTP_PIC)
10185 if (TARGET_ABSOLUTE_ABICALLS)
10186 return LOADGP_ABSOLUTE;
10188 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
10191 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
10194 mips_frame_pointer_required (void)
10196 /* If the function contains dynamic stack allocations, we need to
10197 use the frame pointer to access the static parts of the frame. */
10198 if (cfun->calls_alloca)
10201 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
10202 reload may be unable to compute the address of a local variable,
10203 since there is no way to add a large constant to the stack pointer
10204 without using a second temporary register. */
10207 mips_compute_frame_info ();
10208 if (!SMALL_OPERAND (cfun->machine->frame.total_size))
10215 /* Make sure that we're not trying to eliminate to the wrong hard frame
10219 mips_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
10221 return (to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM);
10224 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
10225 or argument pointer. TO is either the stack pointer or hard frame
10229 mips_initial_elimination_offset (int from, int to)
10231 HOST_WIDE_INT offset;
10233 mips_compute_frame_info ();
10235 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */
10238 case FRAME_POINTER_REGNUM:
10239 if (FRAME_GROWS_DOWNWARD)
10240 offset = (cfun->machine->frame.args_size
10241 + cfun->machine->frame.cprestore_size
10242 + cfun->machine->frame.var_size);
10247 case ARG_POINTER_REGNUM:
10248 offset = cfun->machine->frame.arg_pointer_offset;
10252 gcc_unreachable ();
10255 if (to == HARD_FRAME_POINTER_REGNUM)
10256 offset -= cfun->machine->frame.hard_frame_pointer_offset;
10261 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
10264 mips_extra_live_on_entry (bitmap regs)
10266 if (TARGET_USE_GOT)
10268 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
10269 the global pointer. */
10270 if (!TARGET_ABSOLUTE_ABICALLS)
10271 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
10273 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
10274 the global pointer. */
10276 bitmap_set_bit (regs, MIPS16_PIC_TEMP_REGNUM);
10278 /* See the comment above load_call<mode> for details. */
10279 bitmap_set_bit (regs, GOT_VERSION_REGNUM);
10283 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
10287 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
10292 return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);
10295 /* Emit code to change the current function's return address to
10296 ADDRESS. SCRATCH is available as a scratch register, if needed.
10297 ADDRESS and SCRATCH are both word-mode GPRs. */
10300 mips_set_return_address (rtx address, rtx scratch)
10304 gcc_assert (BITSET_P (cfun->machine->frame.mask, RETURN_ADDR_REGNUM));
10305 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
10306 cfun->machine->frame.gp_sp_offset);
10307 mips_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address);
10310 /* Return true if the current function has a cprestore slot. */
10313 mips_cfun_has_cprestore_slot_p (void)
10315 return (cfun->machine->global_pointer != INVALID_REGNUM
10316 && cfun->machine->frame.cprestore_size > 0);
10319 /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the
10320 cprestore slot. LOAD_P is true if the caller wants to load from
10321 the cprestore slot; it is false if the caller wants to store to
10325 mips_get_cprestore_base_and_offset (rtx *base, HOST_WIDE_INT *offset,
10328 const struct mips_frame_info *frame;
10330 frame = &cfun->machine->frame;
10331 /* .cprestore always uses the stack pointer instead of the frame pointer.
10332 We have a free choice for direct stores for non-MIPS16 functions,
10333 and for MIPS16 functions whose cprestore slot is in range of the
10334 stack pointer. Using the stack pointer would sometimes give more
10335 (early) scheduling freedom, but using the frame pointer would
10336 sometimes give more (late) scheduling freedom. It's hard to
10337 predict which applies to a given function, so let's keep things
10340 Loads must always use the frame pointer in functions that call
10341 alloca, and there's little benefit to using the stack pointer
10343 if (frame_pointer_needed && !(TARGET_CPRESTORE_DIRECTIVE && !load_p))
10345 *base = hard_frame_pointer_rtx;
10346 *offset = frame->args_size - frame->hard_frame_pointer_offset;
10350 *base = stack_pointer_rtx;
10351 *offset = frame->args_size;
10355 /* Return true if X is the load or store address of the cprestore slot;
10356 LOAD_P says which. */
10359 mips_cprestore_address_p (rtx x, bool load_p)
10361 rtx given_base, required_base;
10362 HOST_WIDE_INT given_offset, required_offset;
10364 mips_split_plus (x, &given_base, &given_offset);
10365 mips_get_cprestore_base_and_offset (&required_base, &required_offset, load_p);
10366 return given_base == required_base && given_offset == required_offset;
10369 /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are
10370 going to load from it, false if we are going to store to it.
10371 Use TEMP as a temporary register if need be. */
10374 mips_cprestore_slot (rtx temp, bool load_p)
10377 HOST_WIDE_INT offset;
10379 mips_get_cprestore_base_and_offset (&base, &offset, load_p);
10380 return gen_frame_mem (Pmode, mips_add_offset (temp, base, offset));
10383 /* Emit instructions to save global pointer value GP into cprestore
10384 slot MEM. OFFSET is the offset that MEM applies to the base register.
10386 MEM may not be a legitimate address. If it isn't, TEMP is a
10387 temporary register that can be used, otherwise it is a SCRATCH. */
10390 mips_save_gp_to_cprestore_slot (rtx mem, rtx offset, rtx gp, rtx temp)
10392 if (TARGET_CPRESTORE_DIRECTIVE)
10394 gcc_assert (gp == pic_offset_table_rtx);
10395 emit_insn (PMODE_INSN (gen_cprestore, (mem, offset)));
10398 mips_emit_move (mips_cprestore_slot (temp, false), gp);
10401 /* Restore $gp from its save slot, using TEMP as a temporary base register
10402 if need be. This function is for o32 and o64 abicalls only.
10404 See mips_must_initialize_gp_p for details about how we manage the
10408 mips_restore_gp_from_cprestore_slot (rtx temp)
10410 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI && epilogue_completed);
10412 if (!cfun->machine->must_restore_gp_when_clobbered_p)
10414 emit_note (NOTE_INSN_DELETED);
10420 mips_emit_move (temp, mips_cprestore_slot (temp, true));
10421 mips_emit_move (pic_offset_table_rtx, temp);
10424 mips_emit_move (pic_offset_table_rtx, mips_cprestore_slot (temp, true));
10425 if (!TARGET_EXPLICIT_RELOCS)
10426 emit_insn (gen_blockage ());
10429 /* A function to save or store a register. The first argument is the
10430 register and the second is the stack slot. */
10431 typedef void (*mips_save_restore_fn) (rtx, rtx);
10433 /* Use FN to save or restore register REGNO. MODE is the register's
10434 mode and OFFSET is the offset of its save slot from the current
10438 mips_save_restore_reg (enum machine_mode mode, int regno,
10439 HOST_WIDE_INT offset, mips_save_restore_fn fn)
10443 mem = gen_frame_mem (mode, plus_constant (Pmode, stack_pointer_rtx,
10445 fn (gen_rtx_REG (mode, regno), mem);
10448 /* Call FN for each accumlator that is saved by the current function.
10449 SP_OFFSET is the offset of the current stack pointer from the start
10453 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
10455 HOST_WIDE_INT offset;
10458 offset = cfun->machine->frame.acc_sp_offset - sp_offset;
10459 if (BITSET_P (cfun->machine->frame.acc_mask, 0))
10461 mips_save_restore_reg (word_mode, LO_REGNUM, offset, fn);
10462 offset -= UNITS_PER_WORD;
10463 mips_save_restore_reg (word_mode, HI_REGNUM, offset, fn);
10464 offset -= UNITS_PER_WORD;
10467 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
10468 if (BITSET_P (cfun->machine->frame.acc_mask,
10469 ((regno - DSP_ACC_REG_FIRST) / 2) + 1))
10471 mips_save_restore_reg (word_mode, regno, offset, fn);
10472 offset -= UNITS_PER_WORD;
10476 /* Save register REG to MEM. Make the instruction frame-related. */
10479 mips_save_reg (rtx reg, rtx mem)
10481 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
10485 mips_emit_move_or_split (mem, reg, SPLIT_IF_NECESSARY);
10487 x1 = mips_frame_set (mips_subword (mem, false),
10488 mips_subword (reg, false));
10489 x2 = mips_frame_set (mips_subword (mem, true),
10490 mips_subword (reg, true));
10491 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
10494 mips_emit_save_slot_move (mem, reg, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
10497 /* Capture the register combinations that are allowed in a SWM or LWM
10498 instruction. The entries are ordered by number of registers set in
10499 the mask. We also ignore the single register encodings because a
10500 normal SW/LW is preferred. */
10502 static const unsigned int umips_swm_mask[17] = {
10503 0xc0ff0000, 0x80ff0000, 0x40ff0000, 0x807f0000,
10504 0x00ff0000, 0x803f0000, 0x007f0000, 0x801f0000,
10505 0x003f0000, 0x800f0000, 0x001f0000, 0x80070000,
10506 0x000f0000, 0x80030000, 0x00070000, 0x80010000,
10510 static const unsigned int umips_swm_encoding[17] = {
10511 25, 24, 9, 23, 8, 22, 7, 21, 6, 20, 5, 19, 4, 18, 3, 17, 2
10514 /* Try to use a microMIPS LWM or SWM instruction to save or restore
10515 as many GPRs in *MASK as possible. *OFFSET is the offset from the
10516 stack pointer of the topmost save slot.
10518 Remove from *MASK all registers that were handled using LWM and SWM.
10519 Update *OFFSET so that it points to the first unused save slot. */
10522 umips_build_save_restore (mips_save_restore_fn fn,
10523 unsigned *mask, HOST_WIDE_INT *offset)
10527 rtx pattern, set, reg, mem;
10528 HOST_WIDE_INT this_offset;
10531 /* Try matching $16 to $31 (s0 to ra). */
10532 for (i = 0; i < ARRAY_SIZE (umips_swm_mask); i++)
10533 if ((*mask & 0xffff0000) == umips_swm_mask[i])
10536 if (i == ARRAY_SIZE (umips_swm_mask))
10539 /* Get the offset of the lowest save slot. */
10540 nregs = (umips_swm_encoding[i] & 0xf) + (umips_swm_encoding[i] >> 4);
10541 this_offset = *offset - UNITS_PER_WORD * (nregs - 1);
10543 /* LWM/SWM can only support offsets from -2048 to 2047. */
10544 if (!UMIPS_12BIT_OFFSET_P (this_offset))
10547 /* Create the final PARALLEL. */
10548 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nregs));
10549 this_base = stack_pointer_rtx;
10551 /* For registers $16-$23 and $30. */
10552 for (j = 0; j < (umips_swm_encoding[i] & 0xf); j++)
10554 HOST_WIDE_INT offset = this_offset + j * UNITS_PER_WORD;
10555 mem = gen_frame_mem (SImode, plus_constant (Pmode, this_base, offset));
10556 unsigned int regno = (j != 8) ? 16 + j : 30;
10557 *mask &= ~(1 << regno);
10558 reg = gen_rtx_REG (SImode, regno);
10559 if (fn == mips_save_reg)
10560 set = mips_frame_set (mem, reg);
10563 set = gen_rtx_SET (VOIDmode, reg, mem);
10564 mips_add_cfa_restore (reg);
10566 XVECEXP (pattern, 0, j) = set;
10569 /* For register $31. */
10570 if (umips_swm_encoding[i] >> 4)
10572 HOST_WIDE_INT offset = this_offset + j * UNITS_PER_WORD;
10573 *mask &= ~(1 << 31);
10574 mem = gen_frame_mem (SImode, plus_constant (Pmode, this_base, offset));
10575 reg = gen_rtx_REG (SImode, 31);
10576 if (fn == mips_save_reg)
10577 set = mips_frame_set (mem, reg);
10580 set = gen_rtx_SET (VOIDmode, reg, mem);
10581 mips_add_cfa_restore (reg);
10583 XVECEXP (pattern, 0, j) = set;
10586 pattern = emit_insn (pattern);
10587 if (fn == mips_save_reg)
10588 RTX_FRAME_RELATED_P (pattern) = 1;
10590 /* Adjust the last offset. */
10591 *offset -= UNITS_PER_WORD * nregs;
10596 /* Call FN for each register that is saved by the current function.
10597 SP_OFFSET is the offset of the current stack pointer from the start
10601 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset,
10602 mips_save_restore_fn fn)
10604 enum machine_mode fpr_mode;
10606 const struct mips_frame_info *frame = &cfun->machine->frame;
10607 HOST_WIDE_INT offset;
10610 /* Save registers starting from high to low. The debuggers prefer at least
10611 the return register be stored at func+4, and also it allows us not to
10612 need a nop in the epilogue if at least one register is reloaded in
10613 addition to return address. */
10614 offset = frame->gp_sp_offset - sp_offset;
10615 mask = frame->mask;
10617 if (TARGET_MICROMIPS)
10618 umips_build_save_restore (fn, &mask, &offset);
10620 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
10621 if (BITSET_P (mask, regno - GP_REG_FIRST))
10623 /* Record the ra offset for use by mips_function_profiler. */
10624 if (regno == RETURN_ADDR_REGNUM)
10625 cfun->machine->frame.ra_fp_offset = offset + sp_offset;
10626 mips_save_restore_reg (word_mode, regno, offset, fn);
10627 offset -= UNITS_PER_WORD;
10630 /* This loop must iterate over the same space as its companion in
10631 mips_compute_frame_info. */
10632 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
10633 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
10634 for (regno = FP_REG_LAST - MAX_FPRS_PER_FMT + 1;
10635 regno >= FP_REG_FIRST;
10636 regno -= MAX_FPRS_PER_FMT)
10637 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
10639 mips_save_restore_reg (fpr_mode, regno, offset, fn);
10640 offset -= GET_MODE_SIZE (fpr_mode);
10644 /* Return true if a move between register REGNO and its save slot (MEM)
10645 can be done in a single move. LOAD_P is true if we are loading
10646 from the slot, false if we are storing to it. */
10649 mips_direct_save_slot_move_p (unsigned int regno, rtx mem, bool load_p)
10651 /* There is a specific MIPS16 instruction for saving $31 to the stack. */
10652 if (TARGET_MIPS16 && !load_p && regno == RETURN_ADDR_REGNUM)
10655 return mips_secondary_reload_class (REGNO_REG_CLASS (regno),
10656 GET_MODE (mem), mem, load_p) == NO_REGS;
10659 /* Emit a move from SRC to DEST, given that one of them is a register
10660 save slot and that the other is a register. TEMP is a temporary
10661 GPR of the same mode that is available if need be. */
10664 mips_emit_save_slot_move (rtx dest, rtx src, rtx temp)
10666 unsigned int regno;
10671 regno = REGNO (src);
10676 regno = REGNO (dest);
10680 if (regno == cfun->machine->global_pointer && !mips_must_initialize_gp_p ())
10682 /* We don't yet know whether we'll need this instruction or not.
10683 Postpone the decision by emitting a ghost move. This move
10684 is specifically not frame-related; only the split version is. */
10686 emit_insn (gen_move_gpdi (dest, src));
10688 emit_insn (gen_move_gpsi (dest, src));
10692 if (regno == HI_REGNUM)
10696 mips_emit_move (temp, src);
10698 emit_insn (gen_mthisi_di (gen_rtx_REG (TImode, MD_REG_FIRST),
10699 temp, gen_rtx_REG (DImode, LO_REGNUM)));
10701 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode, MD_REG_FIRST),
10702 temp, gen_rtx_REG (SImode, LO_REGNUM)));
10707 emit_insn (gen_mfhidi_ti (temp,
10708 gen_rtx_REG (TImode, MD_REG_FIRST)));
10710 emit_insn (gen_mfhisi_di (temp,
10711 gen_rtx_REG (DImode, MD_REG_FIRST)));
10712 mips_emit_move (dest, temp);
10715 else if (mips_direct_save_slot_move_p (regno, mem, mem == src))
10716 mips_emit_move (dest, src);
10719 gcc_assert (!reg_overlap_mentioned_p (dest, temp));
10720 mips_emit_move (temp, src);
10721 mips_emit_move (dest, temp);
10724 mips_set_frame_expr (mips_frame_set (dest, src));
10727 /* If we're generating n32 or n64 abicalls, and the current function
10728 does not use $28 as its global pointer, emit a cplocal directive.
10729 Use pic_offset_table_rtx as the argument to the directive. */
10732 mips_output_cplocal (void)
10734 if (!TARGET_EXPLICIT_RELOCS
10735 && mips_must_initialize_gp_p ()
10736 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
10737 output_asm_insn (".cplocal %+", 0);
10740 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
10743 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
10745 const char *fnname;
10747 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
10748 floating-point arguments. */
10750 && TARGET_HARD_FLOAT_ABI
10751 && crtl->args.info.fp_code != 0)
10752 mips16_build_function_stub ();
10754 /* Get the function name the same way that toplev.c does before calling
10755 assemble_start_function. This is needed so that the name used here
10756 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10757 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
10758 mips_start_function_definition (fnname, TARGET_MIPS16);
10760 /* Output MIPS-specific frame information. */
10761 if (!flag_inhibit_size_directive)
10763 const struct mips_frame_info *frame;
10765 frame = &cfun->machine->frame;
10767 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
10769 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
10770 "# vars= " HOST_WIDE_INT_PRINT_DEC
10772 ", args= " HOST_WIDE_INT_PRINT_DEC
10773 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
10774 reg_names[frame_pointer_needed
10775 ? HARD_FRAME_POINTER_REGNUM
10776 : STACK_POINTER_REGNUM],
10777 (frame_pointer_needed
10778 ? frame->total_size - frame->hard_frame_pointer_offset
10779 : frame->total_size),
10780 reg_names[RETURN_ADDR_REGNUM],
10782 frame->num_gp, frame->num_fp,
10784 frame->cprestore_size);
10786 /* .mask MASK, OFFSET. */
10787 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
10788 frame->mask, frame->gp_save_offset);
10790 /* .fmask MASK, OFFSET. */
10791 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
10792 frame->fmask, frame->fp_save_offset);
10795 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
10796 Also emit the ".set noreorder; .set nomacro" sequence for functions
10798 if (mips_must_initialize_gp_p ()
10799 && mips_current_loadgp_style () == LOADGP_OLDABI)
10803 /* This is a fixed-form sequence. The position of the
10804 first two instructions is important because of the
10805 way _gp_disp is defined. */
10806 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
10807 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
10808 output_asm_insn ("sll\t$2,16", 0);
10809 output_asm_insn ("addu\t$2,$3", 0);
10813 /* .cpload must be in a .set noreorder but not a
10814 .set nomacro block. */
10815 mips_push_asm_switch (&mips_noreorder);
10816 output_asm_insn (".cpload\t%^", 0);
10817 if (!cfun->machine->all_noreorder_p)
10818 mips_pop_asm_switch (&mips_noreorder);
10820 mips_push_asm_switch (&mips_nomacro);
10823 else if (cfun->machine->all_noreorder_p)
10825 mips_push_asm_switch (&mips_noreorder);
10826 mips_push_asm_switch (&mips_nomacro);
10829 /* Tell the assembler which register we're using as the global
10830 pointer. This is needed for thunks, since they can use either
10831 explicit relocs or assembler macros. */
10832 mips_output_cplocal ();
10835 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
10838 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
10839 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
10841 const char *fnname;
10843 /* Reinstate the normal $gp. */
10844 SET_REGNO (pic_offset_table_rtx, GLOBAL_POINTER_REGNUM);
10845 mips_output_cplocal ();
10847 if (cfun->machine->all_noreorder_p)
10849 mips_pop_asm_switch (&mips_nomacro);
10850 mips_pop_asm_switch (&mips_noreorder);
10853 /* Get the function name the same way that toplev.c does before calling
10854 assemble_start_function. This is needed so that the name used here
10855 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10856 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
10857 mips_end_function_definition (fnname);
10860 /* Emit an optimisation barrier for accesses to the current frame. */
10863 mips_frame_barrier (void)
10865 emit_clobber (gen_frame_mem (BLKmode, stack_pointer_rtx));
10869 /* The __gnu_local_gp symbol. */
10871 static GTY(()) rtx mips_gnu_local_gp;
10873 /* If we're generating n32 or n64 abicalls, emit instructions
10874 to set up the global pointer. */
10877 mips_emit_loadgp (void)
10879 rtx addr, offset, incoming_address, base, index, pic_reg;
10881 pic_reg = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
10882 switch (mips_current_loadgp_style ())
10884 case LOADGP_ABSOLUTE:
10885 if (mips_gnu_local_gp == NULL)
10887 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
10888 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
10890 emit_insn (PMODE_INSN (gen_loadgp_absolute,
10891 (pic_reg, mips_gnu_local_gp)));
10894 case LOADGP_OLDABI:
10895 /* Added by mips_output_function_prologue. */
10898 case LOADGP_NEWABI:
10899 addr = XEXP (DECL_RTL (current_function_decl), 0);
10900 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
10901 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
10902 emit_insn (PMODE_INSN (gen_loadgp_newabi,
10903 (pic_reg, offset, incoming_address)));
10907 base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE));
10908 index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX));
10909 emit_insn (PMODE_INSN (gen_loadgp_rtp, (pic_reg, base, index)));
10917 emit_insn (PMODE_INSN (gen_copygp_mips16,
10918 (pic_offset_table_rtx, pic_reg)));
10920 /* Emit a blockage if there are implicit uses of the GP register.
10921 This includes profiled functions, because FUNCTION_PROFILE uses
10923 if (!TARGET_EXPLICIT_RELOCS || crtl->profile)
10924 emit_insn (gen_loadgp_blockage ());
10927 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
10929 #if PROBE_INTERVAL > 32768
10930 #error Cannot use indexed addressing mode for stack probing
10933 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
10934 inclusive. These are offsets from the current stack pointer. */
10937 mips_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size)
10940 sorry ("-fstack-check=specific not implemented for MIPS16");
10942 /* See if we have a constant small number of probes to generate. If so,
10943 that's the easy case. */
10944 if (first + size <= 32768)
10948 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
10949 it exceeds SIZE. If only one probe is needed, this will not
10950 generate any code. Then probe at FIRST + SIZE. */
10951 for (i = PROBE_INTERVAL; i < size; i += PROBE_INTERVAL)
10952 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
10955 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
10959 /* Otherwise, do the same as above, but in a loop. Note that we must be
10960 extra careful with variables wrapping around because we might be at
10961 the very top (or the very bottom) of the address space and we have
10962 to be able to handle this case properly; in particular, we use an
10963 equality test for the loop condition. */
10966 HOST_WIDE_INT rounded_size;
10967 rtx r3 = MIPS_PROLOGUE_TEMP (Pmode);
10968 rtx r12 = MIPS_PROLOGUE_TEMP2 (Pmode);
10970 /* Sanity check for the addressing mode we're going to use. */
10971 gcc_assert (first <= 32768);
10974 /* Step 1: round SIZE to the previous multiple of the interval. */
10976 rounded_size = size & -PROBE_INTERVAL;
10979 /* Step 2: compute initial and final value of the loop counter. */
10981 /* TEST_ADDR = SP + FIRST. */
10982 emit_insn (gen_rtx_SET (VOIDmode, r3,
10983 plus_constant (Pmode, stack_pointer_rtx,
10986 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
10987 if (rounded_size > 32768)
10989 emit_move_insn (r12, GEN_INT (rounded_size));
10990 emit_insn (gen_rtx_SET (VOIDmode, r12,
10991 gen_rtx_MINUS (Pmode, r3, r12)));
10994 emit_insn (gen_rtx_SET (VOIDmode, r12,
10995 plus_constant (Pmode, r3, -rounded_size)));
10998 /* Step 3: the loop
11000 while (TEST_ADDR != LAST_ADDR)
11002 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
11006 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
11007 until it is equal to ROUNDED_SIZE. */
11009 emit_insn (PMODE_INSN (gen_probe_stack_range, (r3, r3, r12)));
11012 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
11013 that SIZE is equal to ROUNDED_SIZE. */
11015 if (size != rounded_size)
11016 emit_stack_probe (plus_constant (Pmode, r12, rounded_size - size));
11019 /* Make sure nothing is scheduled before we are done. */
11020 emit_insn (gen_blockage ());
11023 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
11024 absolute addresses. */
11027 mips_output_probe_stack_range (rtx reg1, rtx reg2)
11029 static int labelno = 0;
11030 char loop_lab[32], end_lab[32], tmp[64];
11033 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno);
11034 ASM_GENERATE_INTERNAL_LABEL (end_lab, "LPSRE", labelno++);
11036 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
11038 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
11041 strcpy (tmp, "%(%<beq\t%0,%1,");
11042 output_asm_insn (strcat (tmp, &end_lab[1]), xops);
11044 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
11045 xops[1] = GEN_INT (-PROBE_INTERVAL);
11046 if (TARGET_64BIT && TARGET_LONG64)
11047 output_asm_insn ("daddiu\t%0,%0,%1", xops);
11049 output_asm_insn ("addiu\t%0,%0,%1", xops);
11051 /* Probe at TEST_ADDR and branch. */
11052 fprintf (asm_out_file, "\tb\t");
11053 assemble_name_raw (asm_out_file, loop_lab);
11054 fputc ('\n', asm_out_file);
11056 output_asm_insn ("sd\t$0,0(%0)%)", xops);
11058 output_asm_insn ("sw\t$0,0(%0)%)", xops);
11060 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, end_lab);
11065 /* A for_each_rtx callback. Stop the search if *X is a kernel register. */
11068 mips_kernel_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
11070 return REG_P (*x) && KERNEL_REG_P (REGNO (*x));
11073 /* Expand the "prologue" pattern. */
11076 mips_expand_prologue (void)
11078 const struct mips_frame_info *frame;
11079 HOST_WIDE_INT size;
11080 unsigned int nargs;
11082 if (cfun->machine->global_pointer != INVALID_REGNUM)
11084 /* Check whether an insn uses pic_offset_table_rtx, either explicitly
11085 or implicitly. If so, we can commit to using a global pointer
11086 straight away, otherwise we need to defer the decision. */
11087 if (mips_cfun_has_inflexible_gp_ref_p ()
11088 || mips_cfun_has_flexible_gp_ref_p ())
11090 cfun->machine->must_initialize_gp_p = true;
11091 cfun->machine->must_restore_gp_when_clobbered_p = true;
11094 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
11097 frame = &cfun->machine->frame;
11098 size = frame->total_size;
11100 if (flag_stack_usage_info)
11101 current_function_static_stack_size = size;
11103 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK)
11105 if (crtl->is_leaf && !cfun->calls_alloca)
11107 if (size > PROBE_INTERVAL && size > STACK_CHECK_PROTECT)
11108 mips_emit_probe_stack_range (STACK_CHECK_PROTECT,
11109 size - STACK_CHECK_PROTECT);
11112 mips_emit_probe_stack_range (STACK_CHECK_PROTECT, size);
11115 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
11116 bytes beforehand; this is enough to cover the register save area
11117 without going out of range. */
11118 if (((frame->mask | frame->fmask | frame->acc_mask) != 0)
11119 || frame->num_cop0_regs > 0)
11121 HOST_WIDE_INT step1;
11123 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
11124 if (GENERATE_MIPS16E_SAVE_RESTORE)
11126 HOST_WIDE_INT offset;
11127 unsigned int mask, regno;
11129 /* Try to merge argument stores into the save instruction. */
11130 nargs = mips16e_collect_argument_saves ();
11132 /* Build the save instruction. */
11133 mask = frame->mask;
11134 rtx insn = mips16e_build_save_restore (false, &mask, &offset,
11136 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
11137 mips_frame_barrier ();
11140 /* Check if we need to save other registers. */
11141 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
11142 if (BITSET_P (mask, regno - GP_REG_FIRST))
11144 offset -= UNITS_PER_WORD;
11145 mips_save_restore_reg (word_mode, regno,
11146 offset, mips_save_reg);
11151 if (cfun->machine->interrupt_handler_p)
11153 HOST_WIDE_INT offset;
11156 /* If this interrupt is using a shadow register set, we need to
11157 get the stack pointer from the previous register set. */
11158 if (cfun->machine->use_shadow_register_set_p)
11159 emit_insn (gen_mips_rdpgpr (stack_pointer_rtx,
11160 stack_pointer_rtx));
11162 if (!cfun->machine->keep_interrupts_masked_p)
11164 /* Move from COP0 Cause to K0. */
11165 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K0_REG_NUM),
11166 gen_rtx_REG (SImode,
11167 COP0_CAUSE_REG_NUM)));
11168 /* Move from COP0 EPC to K1. */
11169 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
11170 gen_rtx_REG (SImode,
11171 COP0_EPC_REG_NUM)));
11174 /* Allocate the first part of the frame. */
11175 rtx insn = gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx,
11177 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
11178 mips_frame_barrier ();
11181 /* Start at the uppermost location for saving. */
11182 offset = frame->cop0_sp_offset - size;
11183 if (!cfun->machine->keep_interrupts_masked_p)
11185 /* Push EPC into its stack slot. */
11186 mem = gen_frame_mem (word_mode,
11187 plus_constant (Pmode, stack_pointer_rtx,
11189 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
11190 offset -= UNITS_PER_WORD;
11193 /* Move from COP0 Status to K1. */
11194 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
11195 gen_rtx_REG (SImode,
11196 COP0_STATUS_REG_NUM)));
11198 /* Right justify the RIPL in k0. */
11199 if (!cfun->machine->keep_interrupts_masked_p)
11200 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode, K0_REG_NUM),
11201 gen_rtx_REG (SImode, K0_REG_NUM),
11202 GEN_INT (CAUSE_IPL)));
11204 /* Push Status into its stack slot. */
11205 mem = gen_frame_mem (word_mode,
11206 plus_constant (Pmode, stack_pointer_rtx,
11208 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
11209 offset -= UNITS_PER_WORD;
11211 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
11212 if (!cfun->machine->keep_interrupts_masked_p)
11213 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
11216 gen_rtx_REG (SImode, K0_REG_NUM)));
11218 if (!cfun->machine->keep_interrupts_masked_p)
11219 /* Enable interrupts by clearing the KSU ERL and EXL bits.
11220 IE is already the correct value, so we don't have to do
11221 anything explicit. */
11222 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
11225 gen_rtx_REG (SImode, GP_REG_FIRST)));
11227 /* Disable interrupts by clearing the KSU, ERL, EXL,
11229 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
11232 gen_rtx_REG (SImode, GP_REG_FIRST)));
11236 rtx insn = gen_add3_insn (stack_pointer_rtx,
11239 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
11240 mips_frame_barrier ();
11243 mips_for_each_saved_acc (size, mips_save_reg);
11244 mips_for_each_saved_gpr_and_fpr (size, mips_save_reg);
11248 /* Allocate the rest of the frame. */
11251 if (SMALL_OPERAND (-size))
11252 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
11254 GEN_INT (-size)))) = 1;
11257 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
11260 /* There are no instructions to add or subtract registers
11261 from the stack pointer, so use the frame pointer as a
11262 temporary. We should always be using a frame pointer
11263 in this case anyway. */
11264 gcc_assert (frame_pointer_needed);
11265 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
11266 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
11267 hard_frame_pointer_rtx,
11268 MIPS_PROLOGUE_TEMP (Pmode)));
11269 mips_emit_move (stack_pointer_rtx, hard_frame_pointer_rtx);
11272 emit_insn (gen_sub3_insn (stack_pointer_rtx,
11274 MIPS_PROLOGUE_TEMP (Pmode)));
11276 /* Describe the combined effect of the previous instructions. */
11277 mips_set_frame_expr
11278 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
11279 plus_constant (Pmode, stack_pointer_rtx, -size)));
11281 mips_frame_barrier ();
11284 /* Set up the frame pointer, if we're using one. */
11285 if (frame_pointer_needed)
11287 HOST_WIDE_INT offset;
11289 offset = frame->hard_frame_pointer_offset;
11292 rtx insn = mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
11293 RTX_FRAME_RELATED_P (insn) = 1;
11295 else if (SMALL_OPERAND (offset))
11297 rtx insn = gen_add3_insn (hard_frame_pointer_rtx,
11298 stack_pointer_rtx, GEN_INT (offset));
11299 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
11303 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (offset));
11304 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
11305 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
11306 hard_frame_pointer_rtx,
11307 MIPS_PROLOGUE_TEMP (Pmode)));
11308 mips_set_frame_expr
11309 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
11310 plus_constant (Pmode, stack_pointer_rtx, offset)));
11314 mips_emit_loadgp ();
11316 /* Initialize the $gp save slot. */
11317 if (mips_cfun_has_cprestore_slot_p ())
11319 rtx base, mem, gp, temp;
11320 HOST_WIDE_INT offset;
11322 mips_get_cprestore_base_and_offset (&base, &offset, false);
11323 mem = gen_frame_mem (Pmode, plus_constant (Pmode, base, offset));
11324 gp = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
11325 temp = (SMALL_OPERAND (offset)
11326 ? gen_rtx_SCRATCH (Pmode)
11327 : MIPS_PROLOGUE_TEMP (Pmode));
11328 emit_insn (PMODE_INSN (gen_potential_cprestore,
11329 (mem, GEN_INT (offset), gp, temp)));
11331 mips_get_cprestore_base_and_offset (&base, &offset, true);
11332 mem = gen_frame_mem (Pmode, plus_constant (Pmode, base, offset));
11333 emit_insn (PMODE_INSN (gen_use_cprestore, (mem)));
11336 /* We need to search back to the last use of K0 or K1. */
11337 if (cfun->machine->interrupt_handler_p)
11340 for (insn = get_last_insn (); insn != NULL_RTX; insn = PREV_INSN (insn))
11342 && for_each_rtx (&PATTERN (insn), mips_kernel_reg_p, NULL))
11344 /* Emit a move from K1 to COP0 Status after insn. */
11345 gcc_assert (insn != NULL_RTX);
11346 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
11347 gen_rtx_REG (SImode, K1_REG_NUM)),
11351 /* If we are profiling, make sure no instructions are scheduled before
11352 the call to mcount. */
11354 emit_insn (gen_blockage ());
11357 /* Attach all pending register saves to the previous instruction.
11358 Return that instruction. */
11361 mips_epilogue_emit_cfa_restores (void)
11365 insn = get_last_insn ();
11366 gcc_assert (insn && !REG_NOTES (insn));
11367 if (mips_epilogue.cfa_restores)
11369 RTX_FRAME_RELATED_P (insn) = 1;
11370 REG_NOTES (insn) = mips_epilogue.cfa_restores;
11371 mips_epilogue.cfa_restores = 0;
11376 /* Like mips_epilogue_emit_cfa_restores, but also record that the CFA is
11377 now at REG + OFFSET. */
11380 mips_epilogue_set_cfa (rtx reg, HOST_WIDE_INT offset)
11384 insn = mips_epilogue_emit_cfa_restores ();
11385 if (reg != mips_epilogue.cfa_reg || offset != mips_epilogue.cfa_offset)
11387 RTX_FRAME_RELATED_P (insn) = 1;
11388 REG_NOTES (insn) = alloc_reg_note (REG_CFA_DEF_CFA,
11389 plus_constant (Pmode, reg, offset),
11391 mips_epilogue.cfa_reg = reg;
11392 mips_epilogue.cfa_offset = offset;
11396 /* Emit instructions to restore register REG from slot MEM. Also update
11397 the cfa_restores list. */
11400 mips_restore_reg (rtx reg, rtx mem)
11402 /* There's no MIPS16 instruction to load $31 directly. Load into
11403 $7 instead and adjust the return insn appropriately. */
11404 if (TARGET_MIPS16 && REGNO (reg) == RETURN_ADDR_REGNUM)
11405 reg = gen_rtx_REG (GET_MODE (reg), GP_REG_FIRST + 7);
11406 else if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
11408 mips_add_cfa_restore (mips_subword (reg, true));
11409 mips_add_cfa_restore (mips_subword (reg, false));
11412 mips_add_cfa_restore (reg);
11414 mips_emit_save_slot_move (reg, mem, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
11415 if (REGNO (reg) == REGNO (mips_epilogue.cfa_reg))
11416 /* The CFA is currently defined in terms of the register whose
11417 value we have just restored. Redefine the CFA in terms of
11418 the stack pointer. */
11419 mips_epilogue_set_cfa (stack_pointer_rtx,
11420 mips_epilogue.cfa_restore_sp_offset);
11423 /* Emit code to set the stack pointer to BASE + OFFSET, given that
11424 BASE + OFFSET is NEW_FRAME_SIZE bytes below the top of the frame.
11425 BASE, if not the stack pointer, is available as a temporary. */
11428 mips_deallocate_stack (rtx base, rtx offset, HOST_WIDE_INT new_frame_size)
11430 if (base == stack_pointer_rtx && offset == const0_rtx)
11433 mips_frame_barrier ();
11434 if (offset == const0_rtx)
11436 emit_move_insn (stack_pointer_rtx, base);
11437 mips_epilogue_set_cfa (stack_pointer_rtx, new_frame_size);
11439 else if (TARGET_MIPS16 && base != stack_pointer_rtx)
11441 emit_insn (gen_add3_insn (base, base, offset));
11442 mips_epilogue_set_cfa (base, new_frame_size);
11443 emit_move_insn (stack_pointer_rtx, base);
11447 emit_insn (gen_add3_insn (stack_pointer_rtx, base, offset));
11448 mips_epilogue_set_cfa (stack_pointer_rtx, new_frame_size);
11452 /* Emit any instructions needed before a return. */
11455 mips_expand_before_return (void)
11457 /* When using a call-clobbered gp, we start out with unified call
11458 insns that include instructions to restore the gp. We then split
11459 these unified calls after reload. These split calls explicitly
11460 clobber gp, so there is no need to define
11461 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
11463 For consistency, we should also insert an explicit clobber of $28
11464 before return insns, so that the post-reload optimizers know that
11465 the register is not live on exit. */
11466 if (TARGET_CALL_CLOBBERED_GP)
11467 emit_clobber (pic_offset_table_rtx);
11470 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
11474 mips_expand_epilogue (bool sibcall_p)
11476 const struct mips_frame_info *frame;
11477 HOST_WIDE_INT step1, step2;
11480 bool use_jraddiusp_p = false;
11482 if (!sibcall_p && mips_can_use_return_insn ())
11484 emit_jump_insn (gen_return ());
11488 /* In MIPS16 mode, if the return value should go into a floating-point
11489 register, we need to call a helper routine to copy it over. */
11490 if (mips16_cfun_returns_in_fpr_p ())
11491 mips16_copy_fpr_return_value ();
11493 /* Split the frame into two. STEP1 is the amount of stack we should
11494 deallocate before restoring the registers. STEP2 is the amount we
11495 should deallocate afterwards.
11497 Start off by assuming that no registers need to be restored. */
11498 frame = &cfun->machine->frame;
11499 step1 = frame->total_size;
11502 /* Work out which register holds the frame address. */
11503 if (!frame_pointer_needed)
11504 base = stack_pointer_rtx;
11507 base = hard_frame_pointer_rtx;
11508 step1 -= frame->hard_frame_pointer_offset;
11510 mips_epilogue.cfa_reg = base;
11511 mips_epilogue.cfa_offset = step1;
11512 mips_epilogue.cfa_restores = NULL_RTX;
11514 /* If we need to restore registers, deallocate as much stack as
11515 possible in the second step without going out of range. */
11516 if ((frame->mask | frame->fmask | frame->acc_mask) != 0
11517 || frame->num_cop0_regs > 0)
11519 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
11523 /* Get an rtx for STEP1 that we can add to BASE. */
11524 adjust = GEN_INT (step1);
11525 if (!SMALL_OPERAND (step1))
11527 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), adjust);
11528 adjust = MIPS_EPILOGUE_TEMP (Pmode);
11530 mips_deallocate_stack (base, adjust, step2);
11532 /* If we're using addressing macros, $gp is implicitly used by all
11533 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
11535 if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS)
11536 emit_insn (gen_blockage ());
11538 mips_epilogue.cfa_restore_sp_offset = step2;
11539 if (GENERATE_MIPS16E_SAVE_RESTORE && frame->mask != 0)
11541 unsigned int regno, mask;
11542 HOST_WIDE_INT offset;
11545 /* Generate the restore instruction. */
11546 mask = frame->mask;
11547 restore = mips16e_build_save_restore (true, &mask, &offset, 0, step2);
11549 /* Restore any other registers manually. */
11550 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
11551 if (BITSET_P (mask, regno - GP_REG_FIRST))
11553 offset -= UNITS_PER_WORD;
11554 mips_save_restore_reg (word_mode, regno, offset, mips_restore_reg);
11557 /* Restore the remaining registers and deallocate the final bit
11559 mips_frame_barrier ();
11560 emit_insn (restore);
11561 mips_epilogue_set_cfa (stack_pointer_rtx, 0);
11565 /* Restore the registers. */
11566 mips_for_each_saved_acc (frame->total_size - step2, mips_restore_reg);
11567 mips_for_each_saved_gpr_and_fpr (frame->total_size - step2,
11570 if (cfun->machine->interrupt_handler_p)
11572 HOST_WIDE_INT offset;
11575 offset = frame->cop0_sp_offset - (frame->total_size - step2);
11576 if (!cfun->machine->keep_interrupts_masked_p)
11578 /* Restore the original EPC. */
11579 mem = gen_frame_mem (word_mode,
11580 plus_constant (Pmode, stack_pointer_rtx,
11582 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
11583 offset -= UNITS_PER_WORD;
11585 /* Move to COP0 EPC. */
11586 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_EPC_REG_NUM),
11587 gen_rtx_REG (SImode, K0_REG_NUM)));
11590 /* Restore the original Status. */
11591 mem = gen_frame_mem (word_mode,
11592 plus_constant (Pmode, stack_pointer_rtx,
11594 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
11595 offset -= UNITS_PER_WORD;
11597 /* If we don't use shadow register set, we need to update SP. */
11598 if (!cfun->machine->use_shadow_register_set_p)
11599 mips_deallocate_stack (stack_pointer_rtx, GEN_INT (step2), 0);
11601 /* The choice of position is somewhat arbitrary in this case. */
11602 mips_epilogue_emit_cfa_restores ();
11604 /* Move to COP0 Status. */
11605 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
11606 gen_rtx_REG (SImode, K0_REG_NUM)));
11608 else if (TARGET_MICROMIPS
11609 && !crtl->calls_eh_return
11612 && mips_unsigned_immediate_p (step2, 5, 2))
11613 use_jraddiusp_p = true;
11615 /* Deallocate the final bit of the frame. */
11616 mips_deallocate_stack (stack_pointer_rtx, GEN_INT (step2), 0);
11619 if (!use_jraddiusp_p)
11620 gcc_assert (!mips_epilogue.cfa_restores);
11622 /* Add in the __builtin_eh_return stack adjustment. We need to
11623 use a temporary in MIPS16 code. */
11624 if (crtl->calls_eh_return)
11628 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
11629 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
11630 MIPS_EPILOGUE_TEMP (Pmode),
11631 EH_RETURN_STACKADJ_RTX));
11632 mips_emit_move (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
11635 emit_insn (gen_add3_insn (stack_pointer_rtx,
11637 EH_RETURN_STACKADJ_RTX));
11642 mips_expand_before_return ();
11643 if (cfun->machine->interrupt_handler_p)
11645 /* Interrupt handlers generate eret or deret. */
11646 if (cfun->machine->use_debug_exception_return_p)
11647 emit_jump_insn (gen_mips_deret ());
11649 emit_jump_insn (gen_mips_eret ());
11655 /* When generating MIPS16 code, the normal
11656 mips_for_each_saved_gpr_and_fpr path will restore the return
11657 address into $7 rather than $31. */
11659 && !GENERATE_MIPS16E_SAVE_RESTORE
11660 && BITSET_P (frame->mask, RETURN_ADDR_REGNUM))
11662 /* simple_returns cannot rely on values that are only available
11663 on paths through the epilogue (because return paths that do
11664 not pass through the epilogue may nevertheless reuse a
11665 simple_return that occurs at the end of the epilogue).
11666 Use a normal return here instead. */
11667 rtx reg = gen_rtx_REG (Pmode, GP_REG_FIRST + 7);
11668 pat = gen_return_internal (reg);
11670 else if (use_jraddiusp_p)
11671 pat = gen_jraddiusp (GEN_INT (step2));
11674 rtx reg = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
11675 pat = gen_simple_return_internal (reg);
11677 emit_jump_insn (pat);
11678 if (use_jraddiusp_p)
11679 mips_epilogue_set_cfa (stack_pointer_rtx, step2);
11683 /* Search from the beginning to the first use of K0 or K1. */
11684 if (cfun->machine->interrupt_handler_p
11685 && !cfun->machine->keep_interrupts_masked_p)
11687 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
11689 && for_each_rtx (&PATTERN(insn), mips_kernel_reg_p, NULL))
11691 gcc_assert (insn != NULL_RTX);
11692 /* Insert disable interrupts before the first use of K0 or K1. */
11693 emit_insn_before (gen_mips_di (), insn);
11694 emit_insn_before (gen_mips_ehb (), insn);
11698 /* Return nonzero if this function is known to have a null epilogue.
11699 This allows the optimizer to omit jumps to jumps if no stack
11703 mips_can_use_return_insn (void)
11705 /* Interrupt handlers need to go through the epilogue. */
11706 if (cfun->machine->interrupt_handler_p)
11709 if (!reload_completed)
11715 /* In MIPS16 mode, a function that returns a floating-point value
11716 needs to arrange to copy the return value into the floating-point
11718 if (mips16_cfun_returns_in_fpr_p ())
11721 return cfun->machine->frame.total_size == 0;
11724 /* Return true if register REGNO can store a value of mode MODE.
11725 The result of this function is cached in mips_hard_regno_mode_ok. */
11728 mips_hard_regno_mode_ok_p (unsigned int regno, enum machine_mode mode)
11731 enum mode_class mclass;
11733 if (mode == CCV2mode)
11734 return (ISA_HAS_8CC
11735 && ST_REG_P (regno)
11736 && (regno - ST_REG_FIRST) % 2 == 0);
11738 if (mode == CCV4mode)
11739 return (ISA_HAS_8CC
11740 && ST_REG_P (regno)
11741 && (regno - ST_REG_FIRST) % 4 == 0);
11743 if (mode == CCmode)
11744 return ISA_HAS_8CC ? ST_REG_P (regno) : regno == FPSW_REGNUM;
11746 size = GET_MODE_SIZE (mode);
11747 mclass = GET_MODE_CLASS (mode);
11749 if (GP_REG_P (regno))
11750 return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD;
11752 if (FP_REG_P (regno)
11753 && (((regno - FP_REG_FIRST) % MAX_FPRS_PER_FMT) == 0
11754 || (MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG)))
11756 /* Allow 64-bit vector modes for Loongson-2E/2F. */
11757 if (TARGET_LOONGSON_VECTORS
11758 && (mode == V2SImode
11759 || mode == V4HImode
11760 || mode == V8QImode
11761 || mode == DImode))
11764 if (mclass == MODE_FLOAT
11765 || mclass == MODE_COMPLEX_FLOAT
11766 || mclass == MODE_VECTOR_FLOAT)
11767 return size <= UNITS_PER_FPVALUE;
11769 /* Allow integer modes that fit into a single register. We need
11770 to put integers into FPRs when using instructions like CVT
11771 and TRUNC. There's no point allowing sizes smaller than a word,
11772 because the FPU has no appropriate load/store instructions. */
11773 if (mclass == MODE_INT)
11774 return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG;
11777 if (ACC_REG_P (regno)
11778 && (INTEGRAL_MODE_P (mode) || ALL_FIXED_POINT_MODE_P (mode)))
11780 if (MD_REG_P (regno))
11782 /* After a multiplication or division, clobbering HI makes
11783 the value of LO unpredictable, and vice versa. This means
11784 that, for all interesting cases, HI and LO are effectively
11787 We model this by requiring that any value that uses HI
11789 if (size <= UNITS_PER_WORD * 2)
11790 return regno == (size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST);
11794 /* DSP accumulators do not have the same restrictions as
11795 HI and LO, so we can treat them as normal doubleword
11797 if (size <= UNITS_PER_WORD)
11800 if (size <= UNITS_PER_WORD * 2
11801 && ((regno - DSP_ACC_REG_FIRST) & 1) == 0)
11806 if (ALL_COP_REG_P (regno))
11807 return mclass == MODE_INT && size <= UNITS_PER_WORD;
11809 if (regno == GOT_VERSION_REGNUM)
11810 return mode == SImode;
11815 /* Implement HARD_REGNO_NREGS. */
11818 mips_hard_regno_nregs (int regno, enum machine_mode mode)
11820 if (ST_REG_P (regno))
11821 /* The size of FP status registers is always 4, because they only hold
11822 CCmode values, and CCmode is always considered to be 4 bytes wide. */
11823 return (GET_MODE_SIZE (mode) + 3) / 4;
11825 if (FP_REG_P (regno))
11826 return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG;
11828 /* All other registers are word-sized. */
11829 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
11832 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
11833 in mips_hard_regno_nregs. */
11836 mips_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
11842 COPY_HARD_REG_SET (left, reg_class_contents[(int) rclass]);
11843 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS]))
11845 if (HARD_REGNO_MODE_OK (ST_REG_FIRST, mode))
11846 size = MIN (size, 4);
11847 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) ST_REGS]);
11849 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS]))
11851 if (HARD_REGNO_MODE_OK (FP_REG_FIRST, mode))
11852 size = MIN (size, UNITS_PER_FPREG);
11853 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]);
11855 if (!hard_reg_set_empty_p (left))
11856 size = MIN (size, UNITS_PER_WORD);
11857 return (GET_MODE_SIZE (mode) + size - 1) / size;
11860 /* Implement CANNOT_CHANGE_MODE_CLASS. */
11863 mips_cannot_change_mode_class (enum machine_mode from,
11864 enum machine_mode to,
11865 enum reg_class rclass)
11867 /* Allow conversions between different Loongson integer vectors,
11868 and between those vectors and DImode. */
11869 if (GET_MODE_SIZE (from) == 8 && GET_MODE_SIZE (to) == 8
11870 && INTEGRAL_MODE_P (from) && INTEGRAL_MODE_P (to))
11873 /* Otherwise, there are several problems with changing the modes of
11874 values in floating-point registers:
11876 - When a multi-word value is stored in paired floating-point
11877 registers, the first register always holds the low word. We
11878 therefore can't allow FPRs to change between single-word and
11879 multi-word modes on big-endian targets.
11881 - GCC assumes that each word of a multiword register can be
11882 accessed individually using SUBREGs. This is not true for
11883 floating-point registers if they are bigger than a word.
11885 - Loading a 32-bit value into a 64-bit floating-point register
11886 will not sign-extend the value, despite what LOAD_EXTEND_OP
11887 says. We can't allow FPRs to change from SImode to a wider
11888 mode on 64-bit targets.
11890 - If the FPU has already interpreted a value in one format, we
11891 must not ask it to treat the value as having a different
11894 We therefore disallow all mode changes involving FPRs. */
11896 return reg_classes_intersect_p (FP_REGS, rclass);
11899 /* Implement target hook small_register_classes_for_mode_p. */
11902 mips_small_register_classes_for_mode_p (enum machine_mode mode
11905 return TARGET_MIPS16;
11908 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
11911 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode)
11916 return TARGET_HARD_FLOAT;
11919 return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT;
11922 return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT;
11929 /* Implement MODES_TIEABLE_P. */
11932 mips_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
11934 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
11935 prefer to put one of them in FPRs. */
11936 return (mode1 == mode2
11937 || (!mips_mode_ok_for_mov_fmt_p (mode1)
11938 && !mips_mode_ok_for_mov_fmt_p (mode2)));
11941 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
11944 mips_preferred_reload_class (rtx x, reg_class_t rclass)
11946 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, rclass))
11949 if (reg_class_subset_p (FP_REGS, rclass)
11950 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x)))
11953 if (reg_class_subset_p (GR_REGS, rclass))
11956 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, rclass))
11962 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
11963 Return a "canonical" class to represent it in later calculations. */
11966 mips_canonicalize_move_class (reg_class_t rclass)
11968 /* All moves involving accumulator registers have the same cost. */
11969 if (reg_class_subset_p (rclass, ACC_REGS))
11972 /* Likewise promote subclasses of general registers to the most
11973 interesting containing class. */
11974 if (TARGET_MIPS16 && reg_class_subset_p (rclass, M16_REGS))
11976 else if (reg_class_subset_p (rclass, GENERAL_REGS))
11977 rclass = GENERAL_REGS;
11982 /* Return the cost of moving a value from a register of class FROM to a GPR.
11983 Return 0 for classes that are unions of other classes handled by this
11987 mips_move_to_gpr_cost (reg_class_t from)
11993 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
11997 /* MFLO and MFHI. */
12007 /* This choice of value is historical. */
12015 /* Return the cost of moving a value from a GPR to a register of class TO.
12016 Return 0 for classes that are unions of other classes handled by this
12020 mips_move_from_gpr_cost (reg_class_t to)
12026 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
12030 /* MTLO and MTHI. */
12040 /* This choice of value is historical. */
12048 /* Implement TARGET_REGISTER_MOVE_COST. Return 0 for classes that are the
12049 maximum of the move costs for subclasses; regclass will work out
12050 the maximum for us. */
12053 mips_register_move_cost (enum machine_mode mode,
12054 reg_class_t from, reg_class_t to)
12059 from = mips_canonicalize_move_class (from);
12060 to = mips_canonicalize_move_class (to);
12062 /* Handle moves that can be done without using general-purpose registers. */
12063 if (from == FP_REGS)
12065 if (to == FP_REGS && mips_mode_ok_for_mov_fmt_p (mode))
12070 /* Handle cases in which only one class deviates from the ideal. */
12071 dregs = TARGET_MIPS16 ? M16_REGS : GENERAL_REGS;
12073 return mips_move_from_gpr_cost (to);
12075 return mips_move_to_gpr_cost (from);
12077 /* Handles cases that require a GPR temporary. */
12078 cost1 = mips_move_to_gpr_cost (from);
12081 cost2 = mips_move_from_gpr_cost (to);
12083 return cost1 + cost2;
12089 /* Implement TARGET_REGISTER_PRIORITY. */
12092 mips_register_priority (int hard_regno)
12094 /* Treat MIPS16 registers with higher priority than other regs. */
12096 && TEST_HARD_REG_BIT (reg_class_contents[M16_REGS], hard_regno))
12101 /* Implement TARGET_MEMORY_MOVE_COST. */
12104 mips_memory_move_cost (enum machine_mode mode, reg_class_t rclass, bool in)
12106 return (mips_cost->memory_latency
12107 + memory_move_secondary_cost (mode, rclass, in));
12110 /* Return the register class required for a secondary register when
12111 copying between one of the registers in RCLASS and value X, which
12112 has mode MODE. X is the source of the move if IN_P, otherwise it
12113 is the destination. Return NO_REGS if no secondary register is
12117 mips_secondary_reload_class (enum reg_class rclass,
12118 enum machine_mode mode, rtx x, bool)
12122 /* If X is a constant that cannot be loaded into $25, it must be loaded
12123 into some other GPR. No other register class allows a direct move. */
12124 if (mips_dangerous_for_la25_p (x))
12125 return reg_class_subset_p (rclass, LEA_REGS) ? NO_REGS : LEA_REGS;
12127 regno = true_regnum (x);
12130 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
12131 if (!reg_class_subset_p (rclass, M16_REGS) && !M16_REG_P (regno))
12137 /* Copying from accumulator registers to anywhere other than a general
12138 register requires a temporary general register. */
12139 if (reg_class_subset_p (rclass, ACC_REGS))
12140 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
12141 if (ACC_REG_P (regno))
12142 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
12144 if (reg_class_subset_p (rclass, FP_REGS))
12148 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8)))
12149 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
12150 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
12153 if (GP_REG_P (regno) || x == CONST0_RTX (mode))
12154 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
12157 if (CONSTANT_P (x) && !targetm.cannot_force_const_mem (mode, x))
12158 /* We can force the constant to memory and use lwc1
12159 and ldc1. As above, we will use pairs of lwc1s if
12160 ldc1 is not supported. */
12163 if (FP_REG_P (regno) && mips_mode_ok_for_mov_fmt_p (mode))
12164 /* In this case we can use mov.fmt. */
12167 /* Otherwise, we need to reload through an integer register. */
12170 if (FP_REG_P (regno))
12171 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
12176 /* Implement TARGET_MODE_REP_EXTENDED. */
12179 mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
12181 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
12182 if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
12183 return SIGN_EXTEND;
12188 /* Implement TARGET_VALID_POINTER_MODE. */
12191 mips_valid_pointer_mode (enum machine_mode mode)
12193 return mode == SImode || (TARGET_64BIT && mode == DImode);
12196 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
12199 mips_vector_mode_supported_p (enum machine_mode mode)
12204 return TARGET_PAIRED_SINGLE_FLOAT;
12219 return TARGET_LOONGSON_VECTORS;
12226 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
12229 mips_scalar_mode_supported_p (enum machine_mode mode)
12231 if (ALL_FIXED_POINT_MODE_P (mode)
12232 && GET_MODE_PRECISION (mode) <= 2 * BITS_PER_WORD)
12235 return default_scalar_mode_supported_p (mode);
12238 /* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
12240 static enum machine_mode
12241 mips_preferred_simd_mode (enum machine_mode mode ATTRIBUTE_UNUSED)
12243 if (TARGET_PAIRED_SINGLE_FLOAT
12249 /* Implement TARGET_INIT_LIBFUNCS. */
12252 mips_init_libfuncs (void)
12254 if (TARGET_FIX_VR4120)
12256 /* Register the special divsi3 and modsi3 functions needed to work
12257 around VR4120 division errata. */
12258 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
12259 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
12262 if (TARGET_MIPS16 && TARGET_HARD_FLOAT_ABI)
12264 /* Register the MIPS16 -mhard-float stubs. */
12265 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
12266 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
12267 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
12268 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
12270 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
12271 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
12272 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
12273 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
12274 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
12275 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
12276 set_optab_libfunc (unord_optab, SFmode, "__mips16_unordsf2");
12278 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
12279 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
12280 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__mips16_floatunsisf");
12282 if (TARGET_DOUBLE_FLOAT)
12284 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
12285 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
12286 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
12287 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
12289 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
12290 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
12291 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
12292 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
12293 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
12294 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
12295 set_optab_libfunc (unord_optab, DFmode, "__mips16_unorddf2");
12297 set_conv_libfunc (sext_optab, DFmode, SFmode,
12298 "__mips16_extendsfdf2");
12299 set_conv_libfunc (trunc_optab, SFmode, DFmode,
12300 "__mips16_truncdfsf2");
12301 set_conv_libfunc (sfix_optab, SImode, DFmode,
12302 "__mips16_fix_truncdfsi");
12303 set_conv_libfunc (sfloat_optab, DFmode, SImode,
12304 "__mips16_floatsidf");
12305 set_conv_libfunc (ufloat_optab, DFmode, SImode,
12306 "__mips16_floatunsidf");
12310 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
12311 on an external non-MIPS16 routine to implement __sync_synchronize.
12312 Similarly for the rest of the ll/sc libfuncs. */
12315 synchronize_libfunc = init_one_libfunc ("__sync_synchronize");
12316 init_sync_libfuncs (UNITS_PER_WORD);
12320 /* Build up a multi-insn sequence that loads label TARGET into $AT. */
12323 mips_process_load_label (rtx target)
12325 rtx base, gp, intop;
12326 HOST_WIDE_INT offset;
12328 mips_multi_start ();
12332 mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target, 0);
12333 mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target, 0);
12337 mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target, 0);
12338 mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target, 0);
12342 gp = pic_offset_table_rtx;
12343 if (mips_cfun_has_cprestore_slot_p ())
12345 gp = gen_rtx_REG (Pmode, AT_REGNUM);
12346 mips_get_cprestore_base_and_offset (&base, &offset, true);
12347 if (!SMALL_OPERAND (offset))
12349 intop = GEN_INT (CONST_HIGH_PART (offset));
12350 mips_multi_add_insn ("lui\t%0,%1", gp, intop, 0);
12351 mips_multi_add_insn ("addu\t%0,%0,%1", gp, base, 0);
12354 offset = CONST_LOW_PART (offset);
12356 intop = GEN_INT (offset);
12357 if (ISA_HAS_LOAD_DELAY)
12358 mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp, intop, base, 0);
12360 mips_multi_add_insn ("lw\t%0,%1(%2)", gp, intop, base, 0);
12362 if (ISA_HAS_LOAD_DELAY)
12363 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target, gp, 0);
12365 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target, gp, 0);
12366 mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target, 0);
12371 /* Return the number of instructions needed to load a label into $AT. */
12373 static unsigned int
12374 mips_load_label_num_insns (void)
12376 if (cfun->machine->load_label_num_insns == 0)
12378 mips_process_load_label (pc_rtx);
12379 cfun->machine->load_label_num_insns = mips_multi_num_insns;
12381 return cfun->machine->load_label_num_insns;
12384 /* Emit an asm sequence to start a noat block and load the address
12385 of a label into $1. */
12388 mips_output_load_label (rtx target)
12390 mips_push_asm_switch (&mips_noat);
12391 if (TARGET_EXPLICIT_RELOCS)
12393 mips_process_load_label (target);
12394 mips_multi_write ();
12398 if (Pmode == DImode)
12399 output_asm_insn ("dla\t%@,%0", &target);
12401 output_asm_insn ("la\t%@,%0", &target);
12405 /* Return the length of INSN. LENGTH is the initial length computed by
12406 attributes in the machine-description file. */
12409 mips_adjust_insn_length (rtx_insn *insn, int length)
12411 /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length
12412 of a PIC long-branch sequence. Substitute the correct value. */
12413 if (length == MAX_PIC_BRANCH_LENGTH
12415 && INSN_CODE (insn) >= 0
12416 && get_attr_type (insn) == TYPE_BRANCH)
12418 /* Add the branch-over instruction and its delay slot, if this
12419 is a conditional branch. */
12420 length = simplejump_p (insn) ? 0 : 8;
12422 /* Add the size of a load into $AT. */
12423 length += BASE_INSN_LENGTH * mips_load_label_num_insns ();
12425 /* Add the length of an indirect jump, ignoring the delay slot. */
12426 length += TARGET_COMPRESSION ? 2 : 4;
12429 /* A unconditional jump has an unfilled delay slot if it is not part
12430 of a sequence. A conditional jump normally has a delay slot, but
12431 does not on MIPS16. */
12432 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
12433 length += TARGET_MIPS16 ? 2 : 4;
12435 /* See how many nops might be needed to avoid hardware hazards. */
12436 if (!cfun->machine->ignore_hazard_length_p
12438 && INSN_CODE (insn) >= 0)
12439 switch (get_attr_hazard (insn))
12445 length += NOP_INSN_LENGTH;
12449 length += NOP_INSN_LENGTH * 2;
12456 /* Return the assembly code for INSN, which has the operands given by
12457 OPERANDS, and which branches to OPERANDS[0] if some condition is true.
12458 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0]
12459 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
12460 version of BRANCH_IF_TRUE. */
12463 mips_output_conditional_branch (rtx_insn *insn, rtx *operands,
12464 const char *branch_if_true,
12465 const char *branch_if_false)
12467 unsigned int length;
12470 gcc_assert (LABEL_P (operands[0]));
12472 length = get_attr_length (insn);
12475 /* Just a simple conditional branch. */
12476 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
12477 return branch_if_true;
12480 /* Generate a reversed branch around a direct jump. This fallback does
12481 not use branch-likely instructions. */
12482 mips_branch_likely = false;
12483 rtx_code_label *not_taken = gen_label_rtx ();
12484 taken = operands[0];
12486 /* Generate the reversed branch to NOT_TAKEN. */
12487 operands[0] = not_taken;
12488 output_asm_insn (branch_if_false, operands);
12490 /* If INSN has a delay slot, we must provide delay slots for both the
12491 branch to NOT_TAKEN and the conditional jump. We must also ensure
12492 that INSN's delay slot is executed in the appropriate cases. */
12493 if (final_sequence)
12495 /* This first delay slot will always be executed, so use INSN's
12496 delay slot if is not annulled. */
12497 if (!INSN_ANNULLED_BRANCH_P (insn))
12499 final_scan_insn (final_sequence->insn (1),
12500 asm_out_file, optimize, 1, NULL);
12501 final_sequence->insn (1)->set_deleted ();
12504 output_asm_insn ("nop", 0);
12505 fprintf (asm_out_file, "\n");
12508 /* Output the unconditional branch to TAKEN. */
12509 if (TARGET_ABSOLUTE_JUMPS)
12510 output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken);
12513 mips_output_load_label (taken);
12514 output_asm_insn ("jr\t%@%]%/", 0);
12517 /* Now deal with its delay slot; see above. */
12518 if (final_sequence)
12520 /* This delay slot will only be executed if the branch is taken.
12521 Use INSN's delay slot if is annulled. */
12522 if (INSN_ANNULLED_BRANCH_P (insn))
12524 final_scan_insn (final_sequence->insn (1),
12525 asm_out_file, optimize, 1, NULL);
12526 final_sequence->insn (1)->set_deleted ();
12529 output_asm_insn ("nop", 0);
12530 fprintf (asm_out_file, "\n");
12533 /* Output NOT_TAKEN. */
12534 targetm.asm_out.internal_label (asm_out_file, "L",
12535 CODE_LABEL_NUMBER (not_taken));
12539 /* Return the assembly code for INSN, which branches to OPERANDS[0]
12540 if some ordering condition is true. The condition is given by
12541 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
12542 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
12543 its second is always zero. */
12546 mips_output_order_conditional_branch (rtx_insn *insn, rtx *operands, bool inverted_p)
12548 const char *branch[2];
12550 /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true.
12551 Make BRANCH[0] branch on the inverse condition. */
12552 switch (GET_CODE (operands[1]))
12554 /* These cases are equivalent to comparisons against zero. */
12556 inverted_p = !inverted_p;
12557 /* Fall through. */
12559 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%0");
12560 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%0");
12563 /* These cases are always true or always false. */
12565 inverted_p = !inverted_p;
12566 /* Fall through. */
12568 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%0");
12569 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%0");
12573 branch[!inverted_p] = MIPS_BRANCH ("b%C1z", "%2,%0");
12574 branch[inverted_p] = MIPS_BRANCH ("b%N1z", "%2,%0");
12577 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
12580 /* Start a block of code that needs access to the LL, SC and SYNC
12584 mips_start_ll_sc_sync_block (void)
12586 if (!ISA_HAS_LL_SC)
12588 output_asm_insn (".set\tpush", 0);
12590 output_asm_insn (".set\tmips3", 0);
12592 output_asm_insn (".set\tmips2", 0);
12596 /* End a block started by mips_start_ll_sc_sync_block. */
12599 mips_end_ll_sc_sync_block (void)
12601 if (!ISA_HAS_LL_SC)
12602 output_asm_insn (".set\tpop", 0);
12605 /* Output and/or return the asm template for a sync instruction. */
12608 mips_output_sync (void)
12610 mips_start_ll_sc_sync_block ();
12611 output_asm_insn ("sync", 0);
12612 mips_end_ll_sc_sync_block ();
12616 /* Return the asm template associated with sync_insn1 value TYPE.
12617 IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */
12619 static const char *
12620 mips_sync_insn1_template (enum attr_sync_insn1 type, bool is_64bit_p)
12624 case SYNC_INSN1_MOVE:
12625 return "move\t%0,%z2";
12626 case SYNC_INSN1_LI:
12627 return "li\t%0,%2";
12628 case SYNC_INSN1_ADDU:
12629 return is_64bit_p ? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2";
12630 case SYNC_INSN1_ADDIU:
12631 return is_64bit_p ? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2";
12632 case SYNC_INSN1_SUBU:
12633 return is_64bit_p ? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2";
12634 case SYNC_INSN1_AND:
12635 return "and\t%0,%1,%z2";
12636 case SYNC_INSN1_ANDI:
12637 return "andi\t%0,%1,%2";
12638 case SYNC_INSN1_OR:
12639 return "or\t%0,%1,%z2";
12640 case SYNC_INSN1_ORI:
12641 return "ori\t%0,%1,%2";
12642 case SYNC_INSN1_XOR:
12643 return "xor\t%0,%1,%z2";
12644 case SYNC_INSN1_XORI:
12645 return "xori\t%0,%1,%2";
12647 gcc_unreachable ();
12650 /* Return the asm template associated with sync_insn2 value TYPE. */
12652 static const char *
12653 mips_sync_insn2_template (enum attr_sync_insn2 type)
12657 case SYNC_INSN2_NOP:
12658 gcc_unreachable ();
12659 case SYNC_INSN2_AND:
12660 return "and\t%0,%1,%z2";
12661 case SYNC_INSN2_XOR:
12662 return "xor\t%0,%1,%z2";
12663 case SYNC_INSN2_NOT:
12664 return "nor\t%0,%1,%.";
12666 gcc_unreachable ();
12669 /* OPERANDS are the operands to a sync loop instruction and INDEX is
12670 the value of the one of the sync_* attributes. Return the operand
12671 referred to by the attribute, or DEFAULT_VALUE if the insn doesn't
12672 have the associated attribute. */
12675 mips_get_sync_operand (rtx *operands, int index, rtx default_value)
12678 default_value = operands[index - 1];
12679 return default_value;
12682 /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn
12683 sequence for it. */
12686 mips_process_sync_loop (rtx_insn *insn, rtx *operands)
12688 rtx at, mem, oldval, newval, inclusive_mask, exclusive_mask;
12689 rtx required_oldval, insn1_op2, tmp1, tmp2, tmp3, cmp;
12690 unsigned int tmp3_insn;
12691 enum attr_sync_insn1 insn1;
12692 enum attr_sync_insn2 insn2;
12695 enum memmodel model;
12697 /* Read an operand from the sync_WHAT attribute and store it in
12698 variable WHAT. DEFAULT is the default value if no attribute
12700 #define READ_OPERAND(WHAT, DEFAULT) \
12701 WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \
12704 /* Read the memory. */
12705 READ_OPERAND (mem, 0);
12707 is_64bit_p = (GET_MODE_BITSIZE (GET_MODE (mem)) == 64);
12709 /* Read the other attributes. */
12710 at = gen_rtx_REG (GET_MODE (mem), AT_REGNUM);
12711 READ_OPERAND (oldval, at);
12712 READ_OPERAND (cmp, 0);
12713 READ_OPERAND (newval, at);
12714 READ_OPERAND (inclusive_mask, 0);
12715 READ_OPERAND (exclusive_mask, 0);
12716 READ_OPERAND (required_oldval, 0);
12717 READ_OPERAND (insn1_op2, 0);
12718 insn1 = get_attr_sync_insn1 (insn);
12719 insn2 = get_attr_sync_insn2 (insn);
12721 /* Don't bother setting CMP result that is never used. */
12722 if (cmp && find_reg_note (insn, REG_UNUSED, cmp))
12725 memmodel_attr = get_attr_sync_memmodel (insn);
12726 switch (memmodel_attr)
12729 model = MEMMODEL_ACQ_REL;
12732 model = MEMMODEL_ACQUIRE;
12735 model = (enum memmodel) INTVAL (operands[memmodel_attr]);
12738 mips_multi_start ();
12740 /* Output the release side of the memory barrier. */
12741 if (need_atomic_barrier_p (model, true))
12743 if (required_oldval == 0 && TARGET_OCTEON)
12745 /* Octeon doesn't reorder reads, so a full barrier can be
12746 created by using SYNCW to order writes combined with the
12747 write from the following SC. When the SC successfully
12748 completes, we know that all preceding writes are also
12749 committed to the coherent memory system. It is possible
12750 for a single SYNCW to fail, but a pair of them will never
12751 fail, so we use two. */
12752 mips_multi_add_insn ("syncw", NULL);
12753 mips_multi_add_insn ("syncw", NULL);
12756 mips_multi_add_insn ("sync", NULL);
12759 /* Output the branch-back label. */
12760 mips_multi_add_label ("1:");
12762 /* OLDVAL = *MEM. */
12763 mips_multi_add_insn (is_64bit_p ? "lld\t%0,%1" : "ll\t%0,%1",
12764 oldval, mem, NULL);
12766 /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */
12767 if (required_oldval)
12769 if (inclusive_mask == 0)
12773 gcc_assert (oldval != at);
12774 mips_multi_add_insn ("and\t%0,%1,%2",
12775 at, oldval, inclusive_mask, NULL);
12778 mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1, required_oldval, NULL);
12780 /* CMP = 0 [delay slot]. */
12782 mips_multi_add_insn ("li\t%0,0", cmp, NULL);
12785 /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */
12786 if (exclusive_mask == 0)
12790 gcc_assert (oldval != at);
12791 mips_multi_add_insn ("and\t%0,%1,%z2",
12792 at, oldval, exclusive_mask, NULL);
12796 /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2).
12798 We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit
12799 at least one instruction in that case. */
12800 if (insn1 == SYNC_INSN1_MOVE
12801 && (tmp1 != const0_rtx || insn2 != SYNC_INSN2_NOP))
12805 mips_multi_add_insn (mips_sync_insn1_template (insn1, is_64bit_p),
12806 newval, oldval, insn1_op2, NULL);
12810 /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */
12811 if (insn2 == SYNC_INSN2_NOP)
12815 mips_multi_add_insn (mips_sync_insn2_template (insn2),
12816 newval, tmp2, inclusive_mask, NULL);
12819 tmp3_insn = mips_multi_last_index ();
12821 /* $AT = $TMP1 | $TMP3. */
12822 if (tmp1 == const0_rtx || tmp3 == const0_rtx)
12824 mips_multi_set_operand (tmp3_insn, 0, at);
12829 gcc_assert (tmp1 != tmp3);
12830 mips_multi_add_insn ("or\t%0,%1,%2", at, tmp1, tmp3, NULL);
12833 /* if (!commit (*MEM = $AT)) goto 1.
12835 This will sometimes be a delayed branch; see the write code below
12837 mips_multi_add_insn (is_64bit_p ? "scd\t%0,%1" : "sc\t%0,%1", at, mem, NULL);
12838 mips_multi_add_insn ("beq%?\t%0,%.,1b", at, NULL);
12840 /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */
12841 if (insn1 != SYNC_INSN1_MOVE && insn1 != SYNC_INSN1_LI && tmp3 != newval)
12843 mips_multi_copy_insn (tmp3_insn);
12844 mips_multi_set_operand (mips_multi_last_index (), 0, newval);
12846 else if (!(required_oldval && cmp))
12847 mips_multi_add_insn ("nop", NULL);
12849 /* CMP = 1 -- either standalone or in a delay slot. */
12850 if (required_oldval && cmp)
12851 mips_multi_add_insn ("li\t%0,1", cmp, NULL);
12853 /* Output the acquire side of the memory barrier. */
12854 if (TARGET_SYNC_AFTER_SC && need_atomic_barrier_p (model, false))
12855 mips_multi_add_insn ("sync", NULL);
12857 /* Output the exit label, if needed. */
12858 if (required_oldval)
12859 mips_multi_add_label ("2:");
12861 #undef READ_OPERAND
12864 /* Output and/or return the asm template for sync loop INSN, which has
12865 the operands given by OPERANDS. */
12868 mips_output_sync_loop (rtx_insn *insn, rtx *operands)
12870 mips_process_sync_loop (insn, operands);
12872 /* Use branch-likely instructions to work around the LL/SC R10000
12874 mips_branch_likely = TARGET_FIX_R10000;
12876 mips_push_asm_switch (&mips_noreorder);
12877 mips_push_asm_switch (&mips_nomacro);
12878 mips_push_asm_switch (&mips_noat);
12879 mips_start_ll_sc_sync_block ();
12881 mips_multi_write ();
12883 mips_end_ll_sc_sync_block ();
12884 mips_pop_asm_switch (&mips_noat);
12885 mips_pop_asm_switch (&mips_nomacro);
12886 mips_pop_asm_switch (&mips_noreorder);
12891 /* Return the number of individual instructions in sync loop INSN,
12892 which has the operands given by OPERANDS. */
12895 mips_sync_loop_insns (rtx_insn *insn, rtx *operands)
12897 mips_process_sync_loop (insn, operands);
12898 return mips_multi_num_insns;
12901 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
12902 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
12904 When working around R4000 and R4400 errata, we need to make sure that
12905 the division is not immediately followed by a shift[1][2]. We also
12906 need to stop the division from being put into a branch delay slot[3].
12907 The easiest way to avoid both problems is to add a nop after the
12908 division. When a divide-by-zero check is needed, this nop can be
12909 used to fill the branch delay slot.
12911 [1] If a double-word or a variable shift executes immediately
12912 after starting an integer division, the shift may give an
12913 incorrect result. See quotations of errata #16 and #28 from
12914 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
12915 in mips.md for details.
12917 [2] A similar bug to [1] exists for all revisions of the
12918 R4000 and the R4400 when run in an MC configuration.
12919 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
12921 "19. In this following sequence:
12923 ddiv (or ddivu or div or divu)
12924 dsll32 (or dsrl32, dsra32)
12926 if an MPT stall occurs, while the divide is slipping the cpu
12927 pipeline, then the following double shift would end up with an
12930 Workaround: The compiler needs to avoid generating any
12931 sequence with divide followed by extended double shift."
12933 This erratum is also present in "MIPS R4400MC Errata, Processor
12934 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
12935 & 3.0" as errata #10 and #4, respectively.
12937 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
12938 (also valid for MIPS R4000MC processors):
12940 "52. R4000SC: This bug does not apply for the R4000PC.
12942 There are two flavors of this bug:
12944 1) If the instruction just after divide takes an RF exception
12945 (tlb-refill, tlb-invalid) and gets an instruction cache
12946 miss (both primary and secondary) and the line which is
12947 currently in secondary cache at this index had the first
12948 data word, where the bits 5..2 are set, then R4000 would
12949 get a wrong result for the div.
12954 ------------------- # end-of page. -tlb-refill
12959 ------------------- # end-of page. -tlb-invalid
12962 2) If the divide is in the taken branch delay slot, where the
12963 target takes RF exception and gets an I-cache miss for the
12964 exception vector or where I-cache miss occurs for the
12965 target address, under the above mentioned scenarios, the
12966 div would get wrong results.
12969 j r2 # to next page mapped or unmapped
12970 div r8,r9 # this bug would be there as long
12971 # as there is an ICache miss and
12972 nop # the "data pattern" is present
12975 beq r0, r0, NextPage # to Next page
12979 This bug is present for div, divu, ddiv, and ddivu
12982 Workaround: For item 1), OS could make sure that the next page
12983 after the divide instruction is also mapped. For item 2), the
12984 compiler could make sure that the divide instruction is not in
12985 the branch delay slot."
12987 These processors have PRId values of 0x00004220 and 0x00004300 for
12988 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
12991 mips_output_division (const char *division, rtx *operands)
12996 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
12998 output_asm_insn (s, operands);
13001 if (TARGET_CHECK_ZERO_DIV)
13005 output_asm_insn (s, operands);
13006 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
13008 else if (GENERATE_DIVIDE_TRAPS)
13010 /* Avoid long replay penalty on load miss by putting the trap before
13013 output_asm_insn ("teq\t%2,%.,7", operands);
13016 output_asm_insn (s, operands);
13017 s = "teq\t%2,%.,7";
13022 output_asm_insn ("%(bne\t%2,%.,1f", operands);
13023 output_asm_insn (s, operands);
13024 s = "break\t7%)\n1:";
13030 /* Return true if destination of IN_INSN is used as add source in
13031 OUT_INSN. Both IN_INSN and OUT_INSN are of type fmadd. Example:
13032 madd.s dst, x, y, z
13033 madd.s a, dst, b, c */
13036 mips_fmadd_bypass (rtx_insn *out_insn, rtx_insn *in_insn)
13038 int dst_reg, src_reg;
13040 gcc_assert (get_attr_type (in_insn) == TYPE_FMADD);
13041 gcc_assert (get_attr_type (out_insn) == TYPE_FMADD);
13043 extract_insn (in_insn);
13044 dst_reg = REG_P (recog_data.operand[0]);
13046 extract_insn (out_insn);
13047 src_reg = REG_P (recog_data.operand[1]);
13049 if (dst_reg == src_reg)
13055 /* Return true if IN_INSN is a multiply-add or multiply-subtract
13056 instruction and if OUT_INSN assigns to the accumulator operand. */
13059 mips_linked_madd_p (rtx_insn *out_insn, rtx_insn *in_insn)
13061 enum attr_accum_in accum_in;
13062 int accum_in_opnum;
13065 if (recog_memoized (in_insn) < 0)
13068 accum_in = get_attr_accum_in (in_insn);
13069 if (accum_in == ACCUM_IN_NONE)
13072 accum_in_opnum = accum_in - ACCUM_IN_0;
13074 extract_insn (in_insn);
13075 gcc_assert (accum_in_opnum < recog_data.n_operands);
13076 accum_in_op = recog_data.operand[accum_in_opnum];
13078 return reg_set_p (accum_in_op, out_insn);
13081 /* True if the dependency between OUT_INSN and IN_INSN is on the store
13082 data rather than the address. We need this because the cprestore
13083 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
13084 which causes the default routine to abort. We just return false
13088 mips_store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
13090 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
13093 return !store_data_bypass_p (out_insn, in_insn);
13097 /* Variables and flags used in scheduler hooks when tuning for
13101 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
13104 /* If true, then next ALU1/2 instruction will go to ALU1. */
13107 /* If true, then next FALU1/2 unstruction will go to FALU1. */
13110 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
13111 int alu1_core_unit_code;
13112 int alu2_core_unit_code;
13113 int falu1_core_unit_code;
13114 int falu2_core_unit_code;
13116 /* True if current cycle has a multi instruction.
13117 This flag is used in mips_ls2_dfa_post_advance_cycle. */
13118 bool cycle_has_multi_p;
13120 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
13121 These are used in mips_ls2_dfa_post_advance_cycle to initialize
13123 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
13124 instruction to go ALU1. */
13125 rtx_insn *alu1_turn_enabled_insn;
13126 rtx_insn *alu2_turn_enabled_insn;
13127 rtx_insn *falu1_turn_enabled_insn;
13128 rtx_insn *falu2_turn_enabled_insn;
13131 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
13132 dependencies have no cost, except on the 20Kc where output-dependence
13133 is treated like input-dependence. */
13136 mips_adjust_cost (rtx_insn *insn ATTRIBUTE_UNUSED, rtx link,
13137 rtx_insn *dep ATTRIBUTE_UNUSED, int cost)
13139 if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT
13142 if (REG_NOTE_KIND (link) != 0)
13147 /* Return the number of instructions that can be issued per cycle. */
13150 mips_issue_rate (void)
13154 case PROCESSOR_74KC:
13155 case PROCESSOR_74KF2_1:
13156 case PROCESSOR_74KF1_1:
13157 case PROCESSOR_74KF3_2:
13158 /* The 74k is not strictly quad-issue cpu, but can be seen as one
13159 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
13160 but in reality only a maximum of 3 insns can be issued as
13161 floating-point loads and stores also require a slot in the
13163 case PROCESSOR_R10000:
13164 /* All R10K Processors are quad-issue (being the first MIPS
13165 processors to support this feature). */
13168 case PROCESSOR_20KC:
13169 case PROCESSOR_R4130:
13170 case PROCESSOR_R5400:
13171 case PROCESSOR_R5500:
13172 case PROCESSOR_R5900:
13173 case PROCESSOR_R7000:
13174 case PROCESSOR_R9000:
13175 case PROCESSOR_OCTEON:
13176 case PROCESSOR_OCTEON2:
13179 case PROCESSOR_SB1:
13180 case PROCESSOR_SB1A:
13181 /* This is actually 4, but we get better performance if we claim 3.
13182 This is partly because of unwanted speculative code motion with the
13183 larger number, and partly because in most common cases we can't
13184 reach the theoretical max of 4. */
13187 case PROCESSOR_LOONGSON_2E:
13188 case PROCESSOR_LOONGSON_2F:
13189 case PROCESSOR_LOONGSON_3A:
13190 case PROCESSOR_P5600:
13193 case PROCESSOR_XLP:
13194 return (reload_completed ? 4 : 3);
13201 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
13204 mips_ls2_init_dfa_post_cycle_insn (void)
13207 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
13208 mips_ls2.alu1_turn_enabled_insn = get_insns ();
13212 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
13213 mips_ls2.alu2_turn_enabled_insn = get_insns ();
13217 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
13218 mips_ls2.falu1_turn_enabled_insn = get_insns ();
13222 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
13223 mips_ls2.falu2_turn_enabled_insn = get_insns ();
13226 mips_ls2.alu1_core_unit_code = get_cpu_unit_code ("ls2_alu1_core");
13227 mips_ls2.alu2_core_unit_code = get_cpu_unit_code ("ls2_alu2_core");
13228 mips_ls2.falu1_core_unit_code = get_cpu_unit_code ("ls2_falu1_core");
13229 mips_ls2.falu2_core_unit_code = get_cpu_unit_code ("ls2_falu2_core");
13232 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
13233 Init data used in mips_dfa_post_advance_cycle. */
13236 mips_init_dfa_post_cycle_insn (void)
13238 if (TUNE_LOONGSON_2EF)
13239 mips_ls2_init_dfa_post_cycle_insn ();
13242 /* Initialize STATE when scheduling for Loongson 2E/2F.
13243 Support round-robin dispatch scheme by enabling only one of
13244 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
13248 mips_ls2_dfa_post_advance_cycle (state_t state)
13250 if (cpu_unit_reservation_p (state, mips_ls2.alu1_core_unit_code))
13252 /* Though there are no non-pipelined ALU1 insns,
13253 we can get an instruction of type 'multi' before reload. */
13254 gcc_assert (mips_ls2.cycle_has_multi_p);
13255 mips_ls2.alu1_turn_p = false;
13258 mips_ls2.cycle_has_multi_p = false;
13260 if (cpu_unit_reservation_p (state, mips_ls2.alu2_core_unit_code))
13261 /* We have a non-pipelined alu instruction in the core,
13262 adjust round-robin counter. */
13263 mips_ls2.alu1_turn_p = true;
13265 if (mips_ls2.alu1_turn_p)
13267 if (state_transition (state, mips_ls2.alu1_turn_enabled_insn) >= 0)
13268 gcc_unreachable ();
13272 if (state_transition (state, mips_ls2.alu2_turn_enabled_insn) >= 0)
13273 gcc_unreachable ();
13276 if (cpu_unit_reservation_p (state, mips_ls2.falu1_core_unit_code))
13278 /* There are no non-pipelined FALU1 insns. */
13279 gcc_unreachable ();
13280 mips_ls2.falu1_turn_p = false;
13283 if (cpu_unit_reservation_p (state, mips_ls2.falu2_core_unit_code))
13284 /* We have a non-pipelined falu instruction in the core,
13285 adjust round-robin counter. */
13286 mips_ls2.falu1_turn_p = true;
13288 if (mips_ls2.falu1_turn_p)
13290 if (state_transition (state, mips_ls2.falu1_turn_enabled_insn) >= 0)
13291 gcc_unreachable ();
13295 if (state_transition (state, mips_ls2.falu2_turn_enabled_insn) >= 0)
13296 gcc_unreachable ();
13300 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
13301 This hook is being called at the start of each cycle. */
13304 mips_dfa_post_advance_cycle (void)
13306 if (TUNE_LOONGSON_2EF)
13307 mips_ls2_dfa_post_advance_cycle (curr_state);
13310 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
13311 be as wide as the scheduling freedom in the DFA. */
13314 mips_multipass_dfa_lookahead (void)
13316 /* Can schedule up to 4 of the 6 function units in any one cycle. */
13320 if (TUNE_LOONGSON_2EF || TUNE_LOONGSON_3A)
13332 /* Remove the instruction at index LOWER from ready queue READY and
13333 reinsert it in front of the instruction at index HIGHER. LOWER must
13337 mips_promote_ready (rtx_insn **ready, int lower, int higher)
13339 rtx_insn *new_head;
13342 new_head = ready[lower];
13343 for (i = lower; i < higher; i++)
13344 ready[i] = ready[i + 1];
13345 ready[i] = new_head;
13348 /* If the priority of the instruction at POS2 in the ready queue READY
13349 is within LIMIT units of that of the instruction at POS1, swap the
13350 instructions if POS2 is not already less than POS1. */
13353 mips_maybe_swap_ready (rtx_insn **ready, int pos1, int pos2, int limit)
13356 && INSN_PRIORITY (ready[pos1]) + limit >= INSN_PRIORITY (ready[pos2]))
13360 temp = ready[pos1];
13361 ready[pos1] = ready[pos2];
13362 ready[pos2] = temp;
13366 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
13367 that may clobber hi or lo. */
13368 static rtx_insn *mips_macc_chains_last_hilo;
13370 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
13371 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
13374 mips_macc_chains_record (rtx_insn *insn)
13376 if (get_attr_may_clobber_hilo (insn))
13377 mips_macc_chains_last_hilo = insn;
13380 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
13381 has NREADY elements, looking for a multiply-add or multiply-subtract
13382 instruction that is cumulative with mips_macc_chains_last_hilo.
13383 If there is one, promote it ahead of anything else that might
13384 clobber hi or lo. */
13387 mips_macc_chains_reorder (rtx_insn **ready, int nready)
13391 if (mips_macc_chains_last_hilo != 0)
13392 for (i = nready - 1; i >= 0; i--)
13393 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
13395 for (j = nready - 1; j > i; j--)
13396 if (recog_memoized (ready[j]) >= 0
13397 && get_attr_may_clobber_hilo (ready[j]))
13399 mips_promote_ready (ready, i, j);
13406 /* The last instruction to be scheduled. */
13407 static rtx_insn *vr4130_last_insn;
13409 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
13410 points to an rtx that is initially an instruction. Nullify the rtx
13411 if the instruction uses the value of register X. */
13414 vr4130_true_reg_dependence_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
13419 insn_ptr = (rtx *) data;
13422 && reg_referenced_p (x, PATTERN (*insn_ptr)))
13426 /* Return true if there is true register dependence between vr4130_last_insn
13430 vr4130_true_reg_dependence_p (rtx insn)
13432 note_stores (PATTERN (vr4130_last_insn),
13433 vr4130_true_reg_dependence_p_1, &insn);
13437 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
13438 the ready queue and that INSN2 is the instruction after it, return
13439 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
13440 in which INSN1 and INSN2 can probably issue in parallel, but for
13441 which (INSN2, INSN1) should be less sensitive to instruction
13442 alignment than (INSN1, INSN2). See 4130.md for more details. */
13445 vr4130_swap_insns_p (rtx_insn *insn1, rtx_insn *insn2)
13447 sd_iterator_def sd_it;
13450 /* Check for the following case:
13452 1) there is some other instruction X with an anti dependence on INSN1;
13453 2) X has a higher priority than INSN2; and
13454 3) X is an arithmetic instruction (and thus has no unit restrictions).
13456 If INSN1 is the last instruction blocking X, it would better to
13457 choose (INSN1, X) over (INSN2, INSN1). */
13458 FOR_EACH_DEP (insn1, SD_LIST_FORW, sd_it, dep)
13459 if (DEP_TYPE (dep) == REG_DEP_ANTI
13460 && INSN_PRIORITY (DEP_CON (dep)) > INSN_PRIORITY (insn2)
13461 && recog_memoized (DEP_CON (dep)) >= 0
13462 && get_attr_vr4130_class (DEP_CON (dep)) == VR4130_CLASS_ALU)
13465 if (vr4130_last_insn != 0
13466 && recog_memoized (insn1) >= 0
13467 && recog_memoized (insn2) >= 0)
13469 /* See whether INSN1 and INSN2 use different execution units,
13470 or if they are both ALU-type instructions. If so, they can
13471 probably execute in parallel. */
13472 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
13473 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
13474 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
13476 /* If only one of the instructions has a dependence on
13477 vr4130_last_insn, prefer to schedule the other one first. */
13478 bool dep1_p = vr4130_true_reg_dependence_p (insn1);
13479 bool dep2_p = vr4130_true_reg_dependence_p (insn2);
13480 if (dep1_p != dep2_p)
13483 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
13484 is not an ALU-type instruction and if INSN1 uses the same
13485 execution unit. (Note that if this condition holds, we already
13486 know that INSN2 uses a different execution unit.) */
13487 if (class1 != VR4130_CLASS_ALU
13488 && recog_memoized (vr4130_last_insn) >= 0
13489 && class1 == get_attr_vr4130_class (vr4130_last_insn))
13496 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
13497 queue with at least two instructions. Swap the first two if
13498 vr4130_swap_insns_p says that it could be worthwhile. */
13501 vr4130_reorder (rtx_insn **ready, int nready)
13503 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
13504 mips_promote_ready (ready, nready - 2, nready - 1);
13507 /* Record whether last 74k AGEN instruction was a load or store. */
13508 static enum attr_type mips_last_74k_agen_insn = TYPE_UNKNOWN;
13510 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
13511 resets to TYPE_UNKNOWN state. */
13514 mips_74k_agen_init (rtx_insn *insn)
13516 if (!insn || CALL_P (insn) || JUMP_P (insn))
13517 mips_last_74k_agen_insn = TYPE_UNKNOWN;
13520 enum attr_type type = get_attr_type (insn);
13521 if (type == TYPE_LOAD || type == TYPE_STORE)
13522 mips_last_74k_agen_insn = type;
13526 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
13527 loads to be grouped together, and multiple stores to be grouped
13528 together. Swap things around in the ready queue to make this happen. */
13531 mips_74k_agen_reorder (rtx_insn **ready, int nready)
13534 int store_pos, load_pos;
13539 for (i = nready - 1; i >= 0; i--)
13541 rtx_insn *insn = ready[i];
13542 if (USEFUL_INSN_P (insn))
13543 switch (get_attr_type (insn))
13546 if (store_pos == -1)
13551 if (load_pos == -1)
13560 if (load_pos == -1 || store_pos == -1)
13563 switch (mips_last_74k_agen_insn)
13566 /* Prefer to schedule loads since they have a higher latency. */
13568 /* Swap loads to the front of the queue. */
13569 mips_maybe_swap_ready (ready, load_pos, store_pos, 4);
13572 /* Swap stores to the front of the queue. */
13573 mips_maybe_swap_ready (ready, store_pos, load_pos, 4);
13580 /* Implement TARGET_SCHED_INIT. */
13583 mips_sched_init (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13584 int max_ready ATTRIBUTE_UNUSED)
13586 mips_macc_chains_last_hilo = 0;
13587 vr4130_last_insn = 0;
13588 mips_74k_agen_init (NULL);
13590 /* When scheduling for Loongson2, branch instructions go to ALU1,
13591 therefore basic block is most likely to start with round-robin counter
13592 pointed to ALU2. */
13593 mips_ls2.alu1_turn_p = false;
13594 mips_ls2.falu1_turn_p = true;
13597 /* Subroutine used by TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
13600 mips_sched_reorder_1 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13601 rtx_insn **ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
13603 if (!reload_completed
13604 && TUNE_MACC_CHAINS
13606 mips_macc_chains_reorder (ready, *nreadyp);
13608 if (reload_completed
13610 && !TARGET_VR4130_ALIGN
13612 vr4130_reorder (ready, *nreadyp);
13615 mips_74k_agen_reorder (ready, *nreadyp);
13618 /* Implement TARGET_SCHED_REORDER. */
13621 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13622 rtx_insn **ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
13624 mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle);
13625 return mips_issue_rate ();
13628 /* Implement TARGET_SCHED_REORDER2. */
13631 mips_sched_reorder2 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13632 rtx_insn **ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
13634 mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle);
13635 return cached_can_issue_more;
13638 /* Update round-robin counters for ALU1/2 and FALU1/2. */
13641 mips_ls2_variable_issue (rtx_insn *insn)
13643 if (mips_ls2.alu1_turn_p)
13645 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu1_core_unit_code))
13646 mips_ls2.alu1_turn_p = false;
13650 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu2_core_unit_code))
13651 mips_ls2.alu1_turn_p = true;
13654 if (mips_ls2.falu1_turn_p)
13656 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu1_core_unit_code))
13657 mips_ls2.falu1_turn_p = false;
13661 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu2_core_unit_code))
13662 mips_ls2.falu1_turn_p = true;
13665 if (recog_memoized (insn) >= 0)
13666 mips_ls2.cycle_has_multi_p |= (get_attr_type (insn) == TYPE_MULTI);
13669 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
13672 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13673 rtx_insn *insn, int more)
13675 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
13676 if (USEFUL_INSN_P (insn))
13678 if (get_attr_type (insn) != TYPE_GHOST)
13680 if (!reload_completed && TUNE_MACC_CHAINS)
13681 mips_macc_chains_record (insn);
13682 vr4130_last_insn = insn;
13684 mips_74k_agen_init (insn);
13685 else if (TUNE_LOONGSON_2EF)
13686 mips_ls2_variable_issue (insn);
13689 /* Instructions of type 'multi' should all be split before
13690 the second scheduling pass. */
13691 gcc_assert (!reload_completed
13692 || recog_memoized (insn) < 0
13693 || get_attr_type (insn) != TYPE_MULTI);
13695 cached_can_issue_more = more;
13699 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
13700 return the first operand of the associated PREF or PREFX insn. */
13703 mips_prefetch_cookie (rtx write, rtx locality)
13705 /* store_streamed / load_streamed. */
13706 if (INTVAL (locality) <= 0)
13707 return GEN_INT (INTVAL (write) + 4);
13709 /* store / load. */
13710 if (INTVAL (locality) <= 2)
13713 /* store_retained / load_retained. */
13714 return GEN_INT (INTVAL (write) + 6);
13717 /* Flags that indicate when a built-in function is available.
13719 BUILTIN_AVAIL_NON_MIPS16
13720 The function is available on the current target if !TARGET_MIPS16.
13722 BUILTIN_AVAIL_MIPS16
13723 The function is available on the current target if TARGET_MIPS16. */
13724 #define BUILTIN_AVAIL_NON_MIPS16 1
13725 #define BUILTIN_AVAIL_MIPS16 2
13727 /* Declare an availability predicate for built-in functions that
13728 require non-MIPS16 mode and also require COND to be true.
13729 NAME is the main part of the predicate's name. */
13730 #define AVAIL_NON_MIPS16(NAME, COND) \
13731 static unsigned int \
13732 mips_builtin_avail_##NAME (void) \
13734 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
13737 /* Declare an availability predicate for built-in functions that
13738 support both MIPS16 and non-MIPS16 code and also require COND
13739 to be true. NAME is the main part of the predicate's name. */
13740 #define AVAIL_ALL(NAME, COND) \
13741 static unsigned int \
13742 mips_builtin_avail_##NAME (void) \
13744 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 | BUILTIN_AVAIL_MIPS16 : 0; \
13747 /* This structure describes a single built-in function. */
13748 struct mips_builtin_description {
13749 /* The code of the main .md file instruction. See mips_builtin_type
13750 for more information. */
13751 enum insn_code icode;
13753 /* The floating-point comparison code to use with ICODE, if any. */
13754 enum mips_fp_condition cond;
13756 /* The name of the built-in function. */
13759 /* Specifies how the function should be expanded. */
13760 enum mips_builtin_type builtin_type;
13762 /* The function's prototype. */
13763 enum mips_function_type function_type;
13765 /* Whether the function is available. */
13766 unsigned int (*avail) (void);
13769 AVAIL_ALL (hard_float, TARGET_HARD_FLOAT_ABI)
13770 AVAIL_NON_MIPS16 (paired_single, TARGET_PAIRED_SINGLE_FLOAT)
13771 AVAIL_NON_MIPS16 (sb1_paired_single, TARGET_SB1 && TARGET_PAIRED_SINGLE_FLOAT)
13772 AVAIL_NON_MIPS16 (mips3d, TARGET_MIPS3D)
13773 AVAIL_NON_MIPS16 (dsp, TARGET_DSP)
13774 AVAIL_NON_MIPS16 (dspr2, TARGET_DSPR2)
13775 AVAIL_NON_MIPS16 (dsp_32, !TARGET_64BIT && TARGET_DSP)
13776 AVAIL_NON_MIPS16 (dsp_64, TARGET_64BIT && TARGET_DSP)
13777 AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2)
13778 AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS)
13779 AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
13781 /* Construct a mips_builtin_description from the given arguments.
13783 INSN is the name of the associated instruction pattern, without the
13784 leading CODE_FOR_mips_.
13786 CODE is the floating-point condition code associated with the
13787 function. It can be 'f' if the field is not applicable.
13789 NAME is the name of the function itself, without the leading
13792 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
13794 AVAIL is the name of the availability predicate, without the leading
13795 mips_builtin_avail_. */
13796 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
13797 FUNCTION_TYPE, AVAIL) \
13798 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
13799 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
13800 mips_builtin_avail_ ## AVAIL }
13802 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
13803 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
13804 are as for MIPS_BUILTIN. */
13805 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
13806 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
13808 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
13809 are subject to mips_builtin_avail_<AVAIL>. */
13810 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
13811 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
13812 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
13813 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
13814 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
13816 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
13817 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
13818 while the any and all forms are subject to mips_builtin_avail_mips3d. */
13819 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
13820 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
13821 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
13823 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
13824 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
13826 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
13827 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
13829 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
13830 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
13833 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
13834 are subject to mips_builtin_avail_mips3d. */
13835 #define CMP_4S_BUILTINS(INSN, COND) \
13836 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
13837 MIPS_BUILTIN_CMP_ANY, \
13838 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
13839 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
13840 MIPS_BUILTIN_CMP_ALL, \
13841 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
13843 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
13844 instruction requires mips_builtin_avail_<AVAIL>. */
13845 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
13846 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
13847 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
13849 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
13850 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
13853 /* Define all the built-in functions related to C.cond.fmt condition COND. */
13854 #define CMP_BUILTINS(COND) \
13855 MOVTF_BUILTINS (c, COND, paired_single), \
13856 MOVTF_BUILTINS (cabs, COND, mips3d), \
13857 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
13858 CMP_PS_BUILTINS (c, COND, paired_single), \
13859 CMP_PS_BUILTINS (cabs, COND, mips3d), \
13860 CMP_4S_BUILTINS (c, COND), \
13861 CMP_4S_BUILTINS (cabs, COND)
13863 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
13864 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
13865 and AVAIL are as for MIPS_BUILTIN. */
13866 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
13867 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
13868 FUNCTION_TYPE, AVAIL)
13870 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
13871 branch instruction. AVAIL is as for MIPS_BUILTIN. */
13872 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
13873 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
13874 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
13876 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
13877 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
13878 builtin_description field. */
13879 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
13880 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
13881 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
13882 FUNCTION_TYPE, mips_builtin_avail_loongson }
13884 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
13885 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
13886 builtin_description field. */
13887 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
13888 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
13890 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
13891 We use functions of this form when the same insn can be usefully applied
13892 to more than one datatype. */
13893 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
13894 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
13896 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
13897 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
13898 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
13899 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
13900 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
13901 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
13902 #define CODE_FOR_mips_mult CODE_FOR_mulsidi3_32bit
13903 #define CODE_FOR_mips_multu CODE_FOR_umulsidi3_32bit
13905 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
13906 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
13907 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
13908 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
13909 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
13910 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
13911 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
13912 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
13913 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
13914 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
13915 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
13916 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
13917 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
13918 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
13919 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
13920 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
13921 #define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3
13922 #define CODE_FOR_loongson_psllh CODE_FOR_ashlv4hi3
13923 #define CODE_FOR_loongson_psllw CODE_FOR_ashlv2si3
13924 #define CODE_FOR_loongson_psrlh CODE_FOR_lshrv4hi3
13925 #define CODE_FOR_loongson_psrlw CODE_FOR_lshrv2si3
13926 #define CODE_FOR_loongson_psrah CODE_FOR_ashrv4hi3
13927 #define CODE_FOR_loongson_psraw CODE_FOR_ashrv2si3
13928 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
13929 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
13930 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
13931 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
13932 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
13933 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
13934 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
13936 static const struct mips_builtin_description mips_builtins[] = {
13937 #define MIPS_GET_FCSR 0
13938 DIRECT_BUILTIN (get_fcsr, MIPS_USI_FTYPE_VOID, hard_float),
13939 #define MIPS_SET_FCSR 1
13940 DIRECT_NO_TARGET_BUILTIN (set_fcsr, MIPS_VOID_FTYPE_USI, hard_float),
13942 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13943 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13944 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13945 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13946 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, paired_single),
13947 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, paired_single),
13948 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, paired_single),
13949 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, paired_single),
13951 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT, paired_single),
13952 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13953 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13954 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
13955 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, mips3d),
13957 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, mips3d),
13958 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, mips3d),
13959 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
13960 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
13961 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
13962 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13964 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, mips3d),
13965 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, mips3d),
13966 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
13967 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
13968 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
13969 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13971 MIPS_FP_CONDITIONS (CMP_BUILTINS),
13973 /* Built-in functions for the SB-1 processor. */
13974 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, sb1_paired_single),
13976 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
13977 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13978 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13979 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
13980 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13981 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13982 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13983 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13984 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
13985 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13986 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13987 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, dsp),
13988 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, dsp),
13989 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, dsp),
13990 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, dsp),
13991 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, dsp),
13992 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, dsp),
13993 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
13994 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
13995 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
13996 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
13997 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, dsp),
13998 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, dsp),
13999 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
14000 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
14001 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
14002 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
14003 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
14004 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
14005 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
14006 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
14007 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
14008 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
14009 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
14010 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
14011 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
14012 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
14013 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
14014 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, dsp),
14015 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
14016 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
14017 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
14018 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
14019 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
14020 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, dsp),
14021 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, dsp),
14022 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, dsp),
14023 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, dsp),
14024 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
14025 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
14026 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
14027 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
14028 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
14029 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
14030 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
14031 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
14032 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
14033 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
14034 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
14035 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
14036 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, dsp),
14037 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, dsp),
14038 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_POINTER_SI, dsp),
14039 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_POINTER_SI, dsp),
14040 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_POINTER_SI, dsp),
14041 BPOSGE_BUILTIN (32, dsp),
14043 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
14044 DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, dspr2),
14045 DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14046 DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14047 DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
14048 DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
14049 DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
14050 DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
14051 DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
14052 DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
14053 DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
14054 DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14055 DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14056 DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, dspr2),
14057 DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14058 DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, dspr2),
14059 DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dspr2),
14060 DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
14061 DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
14062 DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
14063 DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
14064 DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
14065 DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, dspr2),
14066 DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14067 DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14068 DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
14069 DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
14070 DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14071 DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14072 DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
14073 DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
14074 DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14075 DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14076 DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
14077 DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
14079 /* Built-in functions for the DSP ASE (32-bit only). */
14080 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
14081 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
14082 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
14083 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
14084 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
14085 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
14086 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
14087 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
14088 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
14089 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
14090 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
14091 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
14092 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
14093 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
14094 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
14095 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
14096 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, dsp_32),
14097 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, dsp_32),
14098 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, dsp_32),
14099 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, dsp_32),
14100 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, dsp_32),
14101 DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
14102 DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32),
14103 DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
14104 DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32),
14105 DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, dsp_32),
14106 DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, dsp_32),
14108 /* Built-in functions for the DSP ASE (64-bit only). */
14109 DIRECT_BUILTIN (ldx, MIPS_DI_FTYPE_POINTER_SI, dsp_64),
14111 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
14112 DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14113 DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14114 DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14115 DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14116 DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14117 DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14118 DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14119 DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14120 DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14122 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
14123 LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI),
14124 LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI),
14125 LOONGSON_BUILTIN (packushb, MIPS_UV8QI_FTYPE_UV4HI_UV4HI),
14126 LOONGSON_BUILTIN_SUFFIX (paddw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14127 LOONGSON_BUILTIN_SUFFIX (paddh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14128 LOONGSON_BUILTIN_SUFFIX (paddb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14129 LOONGSON_BUILTIN_SUFFIX (paddw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14130 LOONGSON_BUILTIN_SUFFIX (paddh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14131 LOONGSON_BUILTIN_SUFFIX (paddb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14132 LOONGSON_BUILTIN_SUFFIX (paddd, u, MIPS_UDI_FTYPE_UDI_UDI),
14133 LOONGSON_BUILTIN_SUFFIX (paddd, s, MIPS_DI_FTYPE_DI_DI),
14134 LOONGSON_BUILTIN (paddsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14135 LOONGSON_BUILTIN (paddsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
14136 LOONGSON_BUILTIN (paddush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14137 LOONGSON_BUILTIN (paddusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14138 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_ud, MIPS_UDI_FTYPE_UDI_UDI),
14139 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_uw, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14140 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_uh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14141 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_ub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14142 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_sd, MIPS_DI_FTYPE_DI_DI),
14143 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_sw, MIPS_V2SI_FTYPE_V2SI_V2SI),
14144 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_sh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14145 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_sb, MIPS_V8QI_FTYPE_V8QI_V8QI),
14146 LOONGSON_BUILTIN (pavgh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14147 LOONGSON_BUILTIN (pavgb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14148 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14149 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14150 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14151 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14152 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14153 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14154 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14155 LOONGSON_BUILTIN_SUFFIX (pcmpgth, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14156 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14157 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14158 LOONGSON_BUILTIN_SUFFIX (pcmpgth, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14159 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14160 LOONGSON_BUILTIN_SUFFIX (pextrh, u, MIPS_UV4HI_FTYPE_UV4HI_USI),
14161 LOONGSON_BUILTIN_SUFFIX (pextrh, s, MIPS_V4HI_FTYPE_V4HI_USI),
14162 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14163 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14164 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14165 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14166 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14167 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14168 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14169 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14170 LOONGSON_BUILTIN (pmaddhw, MIPS_V2SI_FTYPE_V4HI_V4HI),
14171 LOONGSON_BUILTIN (pmaxsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14172 LOONGSON_BUILTIN (pmaxub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14173 LOONGSON_BUILTIN (pminsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14174 LOONGSON_BUILTIN (pminub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14175 LOONGSON_BUILTIN_SUFFIX (pmovmskb, u, MIPS_UV8QI_FTYPE_UV8QI),
14176 LOONGSON_BUILTIN_SUFFIX (pmovmskb, s, MIPS_V8QI_FTYPE_V8QI),
14177 LOONGSON_BUILTIN (pmulhuh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14178 LOONGSON_BUILTIN (pmulhh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14179 LOONGSON_BUILTIN (pmullh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14180 LOONGSON_BUILTIN (pmuluw, MIPS_UDI_FTYPE_UV2SI_UV2SI),
14181 LOONGSON_BUILTIN (pasubub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14182 LOONGSON_BUILTIN (biadd, MIPS_UV4HI_FTYPE_UV8QI),
14183 LOONGSON_BUILTIN (psadbh, MIPS_UV4HI_FTYPE_UV8QI_UV8QI),
14184 LOONGSON_BUILTIN_SUFFIX (pshufh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
14185 LOONGSON_BUILTIN_SUFFIX (pshufh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
14186 LOONGSON_BUILTIN_SUFFIX (psllh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
14187 LOONGSON_BUILTIN_SUFFIX (psllh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
14188 LOONGSON_BUILTIN_SUFFIX (psllw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
14189 LOONGSON_BUILTIN_SUFFIX (psllw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
14190 LOONGSON_BUILTIN_SUFFIX (psrah, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
14191 LOONGSON_BUILTIN_SUFFIX (psrah, s, MIPS_V4HI_FTYPE_V4HI_UQI),
14192 LOONGSON_BUILTIN_SUFFIX (psraw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
14193 LOONGSON_BUILTIN_SUFFIX (psraw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
14194 LOONGSON_BUILTIN_SUFFIX (psrlh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
14195 LOONGSON_BUILTIN_SUFFIX (psrlh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
14196 LOONGSON_BUILTIN_SUFFIX (psrlw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
14197 LOONGSON_BUILTIN_SUFFIX (psrlw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
14198 LOONGSON_BUILTIN_SUFFIX (psubw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14199 LOONGSON_BUILTIN_SUFFIX (psubh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14200 LOONGSON_BUILTIN_SUFFIX (psubb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14201 LOONGSON_BUILTIN_SUFFIX (psubw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14202 LOONGSON_BUILTIN_SUFFIX (psubh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14203 LOONGSON_BUILTIN_SUFFIX (psubb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14204 LOONGSON_BUILTIN_SUFFIX (psubd, u, MIPS_UDI_FTYPE_UDI_UDI),
14205 LOONGSON_BUILTIN_SUFFIX (psubd, s, MIPS_DI_FTYPE_DI_DI),
14206 LOONGSON_BUILTIN (psubsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14207 LOONGSON_BUILTIN (psubsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
14208 LOONGSON_BUILTIN (psubush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14209 LOONGSON_BUILTIN (psubusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14210 LOONGSON_BUILTIN_SUFFIX (punpckhbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14211 LOONGSON_BUILTIN_SUFFIX (punpckhhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14212 LOONGSON_BUILTIN_SUFFIX (punpckhwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14213 LOONGSON_BUILTIN_SUFFIX (punpckhbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14214 LOONGSON_BUILTIN_SUFFIX (punpckhhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14215 LOONGSON_BUILTIN_SUFFIX (punpckhwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14216 LOONGSON_BUILTIN_SUFFIX (punpcklbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14217 LOONGSON_BUILTIN_SUFFIX (punpcklhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14218 LOONGSON_BUILTIN_SUFFIX (punpcklwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14219 LOONGSON_BUILTIN_SUFFIX (punpcklbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14220 LOONGSON_BUILTIN_SUFFIX (punpcklhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14221 LOONGSON_BUILTIN_SUFFIX (punpcklwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14223 /* Sundry other built-in functions. */
14224 DIRECT_NO_TARGET_BUILTIN (cache, MIPS_VOID_FTYPE_SI_CVPOINTER, cache)
14227 /* Index I is the function declaration for mips_builtins[I], or null if the
14228 function isn't defined on this target. */
14229 static GTY(()) tree mips_builtin_decls[ARRAY_SIZE (mips_builtins)];
14231 /* MODE is a vector mode whose elements have type TYPE. Return the type
14232 of the vector itself. */
14235 mips_builtin_vector_type (tree type, enum machine_mode mode)
14237 static tree types[2 * (int) MAX_MACHINE_MODE];
14240 mode_index = (int) mode;
14242 if (TREE_CODE (type) == INTEGER_TYPE && TYPE_UNSIGNED (type))
14243 mode_index += MAX_MACHINE_MODE;
14245 if (types[mode_index] == NULL_TREE)
14246 types[mode_index] = build_vector_type_for_mode (type, mode);
14247 return types[mode_index];
14250 /* Return a type for 'const volatile void *'. */
14253 mips_build_cvpointer_type (void)
14257 if (cache == NULL_TREE)
14258 cache = build_pointer_type (build_qualified_type
14260 TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE));
14264 /* Source-level argument types. */
14265 #define MIPS_ATYPE_VOID void_type_node
14266 #define MIPS_ATYPE_INT integer_type_node
14267 #define MIPS_ATYPE_POINTER ptr_type_node
14268 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
14270 /* Standard mode-based argument types. */
14271 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
14272 #define MIPS_ATYPE_SI intSI_type_node
14273 #define MIPS_ATYPE_USI unsigned_intSI_type_node
14274 #define MIPS_ATYPE_DI intDI_type_node
14275 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
14276 #define MIPS_ATYPE_SF float_type_node
14277 #define MIPS_ATYPE_DF double_type_node
14279 /* Vector argument types. */
14280 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
14281 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
14282 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
14283 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
14284 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
14285 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
14286 #define MIPS_ATYPE_UV2SI \
14287 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
14288 #define MIPS_ATYPE_UV4HI \
14289 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
14290 #define MIPS_ATYPE_UV8QI \
14291 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
14293 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
14294 their associated MIPS_ATYPEs. */
14295 #define MIPS_FTYPE_ATYPES1(A, B) \
14296 MIPS_ATYPE_##A, MIPS_ATYPE_##B
14298 #define MIPS_FTYPE_ATYPES2(A, B, C) \
14299 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
14301 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
14302 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
14304 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
14305 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
14308 /* Return the function type associated with function prototype TYPE. */
14311 mips_build_function_type (enum mips_function_type type)
14313 static tree types[(int) MIPS_MAX_FTYPE_MAX];
14315 if (types[(int) type] == NULL_TREE)
14318 #define DEF_MIPS_FTYPE(NUM, ARGS) \
14319 case MIPS_FTYPE_NAME##NUM ARGS: \
14320 types[(int) type] \
14321 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
14324 #include "config/mips/mips-ftypes.def"
14325 #undef DEF_MIPS_FTYPE
14327 gcc_unreachable ();
14330 return types[(int) type];
14333 /* Implement TARGET_INIT_BUILTINS. */
14336 mips_init_builtins (void)
14338 const struct mips_builtin_description *d;
14341 /* Iterate through all of the bdesc arrays, initializing all of the
14342 builtin functions. */
14343 for (i = 0; i < ARRAY_SIZE (mips_builtins); i++)
14345 d = &mips_builtins[i];
14347 mips_builtin_decls[i]
14348 = add_builtin_function (d->name,
14349 mips_build_function_type (d->function_type),
14350 i, BUILT_IN_MD, NULL, NULL);
14354 /* Implement TARGET_BUILTIN_DECL. */
14357 mips_builtin_decl (unsigned int code, bool initialize_p ATTRIBUTE_UNUSED)
14359 if (code >= ARRAY_SIZE (mips_builtins))
14360 return error_mark_node;
14361 return mips_builtin_decls[code];
14364 /* Take argument ARGNO from EXP's argument list and convert it into
14365 an expand operand. Store the operand in *OP. */
14368 mips_prepare_builtin_arg (struct expand_operand *op, tree exp,
14369 unsigned int argno)
14374 arg = CALL_EXPR_ARG (exp, argno);
14375 value = expand_normal (arg);
14376 create_input_operand (op, value, TYPE_MODE (TREE_TYPE (arg)));
14379 /* Expand instruction ICODE as part of a built-in function sequence.
14380 Use the first NOPS elements of OPS as the instruction's operands.
14381 HAS_TARGET_P is true if operand 0 is a target; it is false if the
14382 instruction has no target.
14384 Return the target rtx if HAS_TARGET_P, otherwise return const0_rtx. */
14387 mips_expand_builtin_insn (enum insn_code icode, unsigned int nops,
14388 struct expand_operand *ops, bool has_target_p)
14390 if (!maybe_expand_insn (icode, nops, ops))
14392 error ("invalid argument to built-in function");
14393 return has_target_p ? gen_reg_rtx (ops[0].mode) : const0_rtx;
14395 return has_target_p ? ops[0].value : const0_rtx;
14398 /* Expand a floating-point comparison for built-in function call EXP.
14399 The first NARGS arguments are the values to be compared. ICODE is
14400 the .md pattern that does the comparison and COND is the condition
14401 that is being tested. Return an rtx for the result. */
14404 mips_expand_builtin_compare_1 (enum insn_code icode,
14405 enum mips_fp_condition cond,
14406 tree exp, int nargs)
14408 struct expand_operand ops[MAX_RECOG_OPERANDS];
14412 /* The instruction should have a target operand, an operand for each
14413 argument, and an operand for COND. */
14414 gcc_assert (nargs + 2 == insn_data[(int) icode].n_generator_args);
14416 output = mips_allocate_fcc (insn_data[(int) icode].operand[0].mode);
14418 create_fixed_operand (&ops[opno++], output);
14419 for (argno = 0; argno < nargs; argno++)
14420 mips_prepare_builtin_arg (&ops[opno++], exp, argno);
14421 create_integer_operand (&ops[opno++], (int) cond);
14422 return mips_expand_builtin_insn (icode, opno, ops, true);
14425 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
14426 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
14427 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
14428 suggests a good place to put the result. */
14431 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
14434 struct expand_operand ops[MAX_RECOG_OPERANDS];
14437 /* Map any target to operand 0. */
14440 create_output_operand (&ops[opno++], target, TYPE_MODE (TREE_TYPE (exp)));
14442 /* Map the arguments to the other operands. */
14443 gcc_assert (opno + call_expr_nargs (exp)
14444 == insn_data[icode].n_generator_args);
14445 for (argno = 0; argno < call_expr_nargs (exp); argno++)
14446 mips_prepare_builtin_arg (&ops[opno++], exp, argno);
14448 return mips_expand_builtin_insn (icode, opno, ops, has_target_p);
14451 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
14452 function; TYPE says which. EXP is the CALL_EXPR that calls the
14453 function, ICODE is the instruction that should be used to compare
14454 the first two arguments, and COND is the condition it should test.
14455 TARGET, if nonnull, suggests a good place to put the result. */
14458 mips_expand_builtin_movtf (enum mips_builtin_type type,
14459 enum insn_code icode, enum mips_fp_condition cond,
14460 rtx target, tree exp)
14462 struct expand_operand ops[4];
14465 cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp, 2);
14466 create_output_operand (&ops[0], target, TYPE_MODE (TREE_TYPE (exp)));
14467 if (type == MIPS_BUILTIN_MOVT)
14469 mips_prepare_builtin_arg (&ops[2], exp, 2);
14470 mips_prepare_builtin_arg (&ops[1], exp, 3);
14474 mips_prepare_builtin_arg (&ops[1], exp, 2);
14475 mips_prepare_builtin_arg (&ops[2], exp, 3);
14477 create_fixed_operand (&ops[3], cmp_result);
14478 return mips_expand_builtin_insn (CODE_FOR_mips_cond_move_tf_ps,
14482 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
14483 into TARGET otherwise. Return TARGET. */
14486 mips_builtin_branch_and_move (rtx condition, rtx target,
14487 rtx value_if_true, rtx value_if_false)
14489 rtx_code_label *true_label, *done_label;
14491 true_label = gen_label_rtx ();
14492 done_label = gen_label_rtx ();
14494 /* First assume that CONDITION is false. */
14495 mips_emit_move (target, value_if_false);
14497 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
14498 emit_jump_insn (gen_condjump (condition, true_label));
14499 emit_jump_insn (gen_jump (done_label));
14502 /* Fix TARGET if CONDITION is true. */
14503 emit_label (true_label);
14504 mips_emit_move (target, value_if_true);
14506 emit_label (done_label);
14510 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
14511 the CALL_EXPR that calls the function, ICODE is the code of the
14512 comparison instruction, and COND is the condition it should test.
14513 TARGET, if nonnull, suggests a good place to put the boolean result. */
14516 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
14517 enum insn_code icode, enum mips_fp_condition cond,
14518 rtx target, tree exp)
14520 rtx offset, condition, cmp_result;
14522 if (target == 0 || GET_MODE (target) != SImode)
14523 target = gen_reg_rtx (SImode);
14524 cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp,
14525 call_expr_nargs (exp));
14527 /* If the comparison sets more than one register, we define the result
14528 to be 0 if all registers are false and -1 if all registers are true.
14529 The value of the complete result is indeterminate otherwise. */
14530 switch (builtin_type)
14532 case MIPS_BUILTIN_CMP_ALL:
14533 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
14534 return mips_builtin_branch_and_move (condition, target,
14535 const0_rtx, const1_rtx);
14537 case MIPS_BUILTIN_CMP_UPPER:
14538 case MIPS_BUILTIN_CMP_LOWER:
14539 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
14540 condition = gen_single_cc (cmp_result, offset);
14541 return mips_builtin_branch_and_move (condition, target,
14542 const1_rtx, const0_rtx);
14545 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
14546 return mips_builtin_branch_and_move (condition, target,
14547 const1_rtx, const0_rtx);
14551 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
14552 if nonnull, suggests a good place to put the boolean result. */
14555 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
14557 rtx condition, cmp_result;
14560 if (target == 0 || GET_MODE (target) != SImode)
14561 target = gen_reg_rtx (SImode);
14563 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
14565 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
14570 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
14571 return mips_builtin_branch_and_move (condition, target,
14572 const1_rtx, const0_rtx);
14575 /* Implement TARGET_EXPAND_BUILTIN. */
14578 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
14579 enum machine_mode mode, int ignore)
14582 unsigned int fcode, avail;
14583 const struct mips_builtin_description *d;
14585 fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
14586 fcode = DECL_FUNCTION_CODE (fndecl);
14587 gcc_assert (fcode < ARRAY_SIZE (mips_builtins));
14588 d = &mips_builtins[fcode];
14589 avail = d->avail ();
14590 gcc_assert (avail != 0);
14591 if (TARGET_MIPS16 && !(avail & BUILTIN_AVAIL_MIPS16))
14593 error ("built-in function %qE not supported for MIPS16",
14594 DECL_NAME (fndecl));
14595 return ignore ? const0_rtx : CONST0_RTX (mode);
14597 switch (d->builtin_type)
14599 case MIPS_BUILTIN_DIRECT:
14600 return mips_expand_builtin_direct (d->icode, target, exp, true);
14602 case MIPS_BUILTIN_DIRECT_NO_TARGET:
14603 return mips_expand_builtin_direct (d->icode, target, exp, false);
14605 case MIPS_BUILTIN_MOVT:
14606 case MIPS_BUILTIN_MOVF:
14607 return mips_expand_builtin_movtf (d->builtin_type, d->icode,
14608 d->cond, target, exp);
14610 case MIPS_BUILTIN_CMP_ANY:
14611 case MIPS_BUILTIN_CMP_ALL:
14612 case MIPS_BUILTIN_CMP_UPPER:
14613 case MIPS_BUILTIN_CMP_LOWER:
14614 case MIPS_BUILTIN_CMP_SINGLE:
14615 return mips_expand_builtin_compare (d->builtin_type, d->icode,
14616 d->cond, target, exp);
14618 case MIPS_BUILTIN_BPOSGE32:
14619 return mips_expand_builtin_bposge (d->builtin_type, target);
14621 gcc_unreachable ();
14624 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
14625 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
14626 struct mips16_constant {
14627 struct mips16_constant *next;
14629 rtx_code_label *label;
14630 enum machine_mode mode;
14633 /* Information about an incomplete MIPS16 constant pool. FIRST is the
14634 first constant, HIGHEST_ADDRESS is the highest address that the first
14635 byte of the pool can have, and INSN_ADDRESS is the current instruction
14637 struct mips16_constant_pool {
14638 struct mips16_constant *first;
14639 int highest_address;
14643 /* Add constant VALUE to POOL and return its label. MODE is the
14644 value's mode (used for CONST_INTs, etc.). */
14646 static rtx_code_label *
14647 mips16_add_constant (struct mips16_constant_pool *pool,
14648 rtx value, enum machine_mode mode)
14650 struct mips16_constant **p, *c;
14651 bool first_of_size_p;
14653 /* See whether the constant is already in the pool. If so, return the
14654 existing label, otherwise leave P pointing to the place where the
14655 constant should be added.
14657 Keep the pool sorted in increasing order of mode size so that we can
14658 reduce the number of alignments needed. */
14659 first_of_size_p = true;
14660 for (p = &pool->first; *p != 0; p = &(*p)->next)
14662 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
14663 return (*p)->label;
14664 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
14666 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
14667 first_of_size_p = false;
14670 /* In the worst case, the constant needed by the earliest instruction
14671 will end up at the end of the pool. The entire pool must then be
14672 accessible from that instruction.
14674 When adding the first constant, set the pool's highest address to
14675 the address of the first out-of-range byte. Adjust this address
14676 downwards each time a new constant is added. */
14677 if (pool->first == 0)
14678 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
14679 of the instruction with the lowest two bits clear. The base PC
14680 value for LDPC has the lowest three bits clear. Assume the worst
14681 case here; namely that the PC-relative instruction occupies the
14682 last 2 bytes in an aligned word. */
14683 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
14684 pool->highest_address -= GET_MODE_SIZE (mode);
14685 if (first_of_size_p)
14686 /* Take into account the worst possible padding due to alignment. */
14687 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
14689 /* Create a new entry. */
14690 c = XNEW (struct mips16_constant);
14693 c->label = gen_label_rtx ();
14700 /* Output constant VALUE after instruction INSN and return the last
14701 instruction emitted. MODE is the mode of the constant. */
14704 mips16_emit_constants_1 (enum machine_mode mode, rtx value, rtx_insn *insn)
14706 if (SCALAR_INT_MODE_P (mode) || ALL_SCALAR_FIXED_POINT_MODE_P (mode))
14708 rtx size = GEN_INT (GET_MODE_SIZE (mode));
14709 return emit_insn_after (gen_consttable_int (value, size), insn);
14712 if (SCALAR_FLOAT_MODE_P (mode))
14713 return emit_insn_after (gen_consttable_float (value), insn);
14715 if (VECTOR_MODE_P (mode))
14719 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
14720 insn = mips16_emit_constants_1 (GET_MODE_INNER (mode),
14721 CONST_VECTOR_ELT (value, i), insn);
14725 gcc_unreachable ();
14728 /* Dump out the constants in CONSTANTS after INSN. */
14731 mips16_emit_constants (struct mips16_constant *constants, rtx_insn *insn)
14733 struct mips16_constant *c, *next;
14737 for (c = constants; c != NULL; c = next)
14739 /* If necessary, increase the alignment of PC. */
14740 if (align < GET_MODE_SIZE (c->mode))
14742 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
14743 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
14745 align = GET_MODE_SIZE (c->mode);
14747 insn = emit_label_after (c->label, insn);
14748 insn = mips16_emit_constants_1 (c->mode, c->value, insn);
14754 emit_barrier_after (insn);
14757 /* Return the length of instruction INSN. */
14760 mips16_insn_length (rtx_insn *insn)
14762 if (JUMP_TABLE_DATA_P (insn))
14764 rtx body = PATTERN (insn);
14765 if (GET_CODE (body) == ADDR_VEC)
14766 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
14767 else if (GET_CODE (body) == ADDR_DIFF_VEC)
14768 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
14770 gcc_unreachable ();
14772 return get_attr_length (insn);
14775 /* If *X is a symbolic constant that refers to the constant pool, add
14776 the constant to POOL and rewrite *X to use the constant's label. */
14779 mips16_rewrite_pool_constant (struct mips16_constant_pool *pool, rtx *x)
14782 rtx_code_label *label;
14784 split_const (*x, &base, &offset);
14785 if (GET_CODE (base) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (base))
14787 label = mips16_add_constant (pool, copy_rtx (get_pool_constant (base)),
14788 get_pool_mode (base));
14789 base = gen_rtx_LABEL_REF (Pmode, label);
14790 *x = mips_unspec_address_offset (base, offset, SYMBOL_PC_RELATIVE);
14794 /* This structure is used to communicate with mips16_rewrite_pool_refs.
14795 INSN is the instruction we're rewriting and POOL points to the current
14797 struct mips16_rewrite_pool_refs_info {
14799 struct mips16_constant_pool *pool;
14802 /* Rewrite *X so that constant pool references refer to the constant's
14803 label instead. DATA points to a mips16_rewrite_pool_refs_info
14807 mips16_rewrite_pool_refs (rtx *x, void *data)
14809 struct mips16_rewrite_pool_refs_info *info =
14810 (struct mips16_rewrite_pool_refs_info *) data;
14812 if (force_to_mem_operand (*x, Pmode))
14814 rtx mem = force_const_mem (GET_MODE (*x), *x);
14815 validate_change (info->insn, x, mem, false);
14820 mips16_rewrite_pool_constant (info->pool, &XEXP (*x, 0));
14824 /* Don't rewrite the __mips16_rdwr symbol. */
14825 if (GET_CODE (*x) == UNSPEC && XINT (*x, 1) == UNSPEC_TLS_GET_TP)
14828 if (TARGET_MIPS16_TEXT_LOADS)
14829 mips16_rewrite_pool_constant (info->pool, x);
14831 return GET_CODE (*x) == CONST ? -1 : 0;
14834 /* Return whether CFG is used in mips_reorg. */
14837 mips_cfg_in_reorg (void)
14839 return (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
14840 || TARGET_RELAX_PIC_CALLS);
14843 /* Build MIPS16 constant pools. Split the instructions if SPLIT_P,
14844 otherwise assume that they are already split. */
14847 mips16_lay_out_constants (bool split_p)
14849 struct mips16_constant_pool pool;
14850 struct mips16_rewrite_pool_refs_info info;
14851 rtx_insn *insn, *barrier;
14853 if (!TARGET_MIPS16_PCREL_LOADS)
14858 if (mips_cfg_in_reorg ())
14859 split_all_insns ();
14861 split_all_insns_noflow ();
14864 memset (&pool, 0, sizeof (pool));
14865 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
14867 /* Rewrite constant pool references in INSN. */
14868 if (USEFUL_INSN_P (insn))
14872 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &info);
14875 pool.insn_address += mips16_insn_length (insn);
14877 if (pool.first != NULL)
14879 /* If there are no natural barriers between the first user of
14880 the pool and the highest acceptable address, we'll need to
14881 create a new instruction to jump around the constant pool.
14882 In the worst case, this instruction will be 4 bytes long.
14884 If it's too late to do this transformation after INSN,
14885 do it immediately before INSN. */
14886 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
14888 rtx_code_label *label;
14891 label = gen_label_rtx ();
14893 jump = emit_jump_insn_before (gen_jump (label), insn);
14894 JUMP_LABEL (jump) = label;
14895 LABEL_NUSES (label) = 1;
14896 barrier = emit_barrier_after (jump);
14898 emit_label_after (label, barrier);
14899 pool.insn_address += 4;
14902 /* See whether the constant pool is now out of range of the first
14903 user. If so, output the constants after the previous barrier.
14904 Note that any instructions between BARRIER and INSN (inclusive)
14905 will use negative offsets to refer to the pool. */
14906 if (pool.insn_address > pool.highest_address)
14908 mips16_emit_constants (pool.first, barrier);
14912 else if (BARRIER_P (insn))
14916 mips16_emit_constants (pool.first, get_last_insn ());
14919 /* Return true if it is worth r10k_simplify_address's while replacing
14920 an address with X. We are looking for constants, and for addresses
14921 at a known offset from the incoming stack pointer. */
14924 r10k_simplified_address_p (rtx x)
14926 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
14928 return x == virtual_incoming_args_rtx || CONSTANT_P (x);
14931 /* X is an expression that appears in INSN. Try to use the UD chains
14932 to simplify it, returning the simplified form on success and the
14933 original form otherwise. Replace the incoming value of $sp with
14934 virtual_incoming_args_rtx (which should never occur in X otherwise). */
14937 r10k_simplify_address (rtx x, rtx_insn *insn)
14939 rtx newx, op0, op1, set, note;
14940 rtx_insn *def_insn;
14942 struct df_link *defs;
14947 op0 = r10k_simplify_address (XEXP (x, 0), insn);
14948 if (op0 != XEXP (x, 0))
14949 newx = simplify_gen_unary (GET_CODE (x), GET_MODE (x),
14950 op0, GET_MODE (XEXP (x, 0)));
14952 else if (BINARY_P (x))
14954 op0 = r10k_simplify_address (XEXP (x, 0), insn);
14955 op1 = r10k_simplify_address (XEXP (x, 1), insn);
14956 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
14957 newx = simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
14959 else if (GET_CODE (x) == LO_SUM)
14961 /* LO_SUMs can be offset from HIGHs, if we know they won't
14962 overflow. See mips_classify_address for the rationale behind
14964 op0 = r10k_simplify_address (XEXP (x, 0), insn);
14965 if (GET_CODE (op0) == HIGH)
14966 newx = XEXP (x, 1);
14968 else if (REG_P (x))
14970 /* Uses are recorded by regno_reg_rtx, not X itself. */
14971 use = df_find_use (insn, regno_reg_rtx[REGNO (x)]);
14973 defs = DF_REF_CHAIN (use);
14975 /* Require a single definition. */
14976 if (defs && defs->next == NULL)
14979 if (DF_REF_IS_ARTIFICIAL (def))
14981 /* Replace the incoming value of $sp with
14982 virtual_incoming_args_rtx. */
14983 if (x == stack_pointer_rtx
14984 && DF_REF_BB (def) == ENTRY_BLOCK_PTR_FOR_FN (cfun))
14985 newx = virtual_incoming_args_rtx;
14987 else if (dominated_by_p (CDI_DOMINATORS, DF_REF_BB (use),
14990 /* Make sure that DEF_INSN is a single set of REG. */
14991 def_insn = DF_REF_INSN (def);
14992 if (NONJUMP_INSN_P (def_insn))
14994 set = single_set (def_insn);
14995 if (set && rtx_equal_p (SET_DEST (set), x))
14997 /* Prefer to use notes, since the def-use chains
14998 are often shorter. */
14999 note = find_reg_equal_equiv_note (def_insn);
15001 newx = XEXP (note, 0);
15003 newx = SET_SRC (set);
15004 newx = r10k_simplify_address (newx, def_insn);
15010 if (newx && r10k_simplified_address_p (newx))
15015 /* Return true if ADDRESS is known to be an uncached address
15016 on R10K systems. */
15019 r10k_uncached_address_p (unsigned HOST_WIDE_INT address)
15021 unsigned HOST_WIDE_INT upper;
15023 /* Check for KSEG1. */
15024 if (address + 0x60000000 < 0x20000000)
15027 /* Check for uncached XKPHYS addresses. */
15028 if (Pmode == DImode)
15030 upper = (address >> 40) & 0xf9ffff;
15031 if (upper == 0x900000 || upper == 0xb80000)
15037 /* Return true if we can prove that an access to address X in instruction
15038 INSN would be safe from R10K speculation. This X is a general
15039 expression; it might not be a legitimate address. */
15042 r10k_safe_address_p (rtx x, rtx_insn *insn)
15045 HOST_WIDE_INT offset_val;
15047 x = r10k_simplify_address (x, insn);
15049 /* Check for references to the stack frame. It doesn't really matter
15050 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
15051 allows us to assume that accesses to any part of the eventual frame
15052 is safe from speculation at any point in the function. */
15053 mips_split_plus (x, &base, &offset_val);
15054 if (base == virtual_incoming_args_rtx
15055 && offset_val >= -cfun->machine->frame.total_size
15056 && offset_val < cfun->machine->frame.args_size)
15059 /* Check for uncached addresses. */
15060 if (CONST_INT_P (x))
15061 return r10k_uncached_address_p (INTVAL (x));
15063 /* Check for accesses to a static object. */
15064 split_const (x, &base, &offset);
15065 return offset_within_block_p (base, INTVAL (offset));
15068 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
15069 an in-range access to an automatic variable, or to an object with
15070 a link-time-constant address. */
15073 r10k_safe_mem_expr_p (tree expr, unsigned HOST_WIDE_INT offset)
15075 HOST_WIDE_INT bitoffset, bitsize;
15076 tree inner, var_offset;
15077 enum machine_mode mode;
15078 int unsigned_p, volatile_p;
15080 inner = get_inner_reference (expr, &bitsize, &bitoffset, &var_offset, &mode,
15081 &unsigned_p, &volatile_p, false);
15082 if (!DECL_P (inner) || !DECL_SIZE_UNIT (inner) || var_offset)
15085 offset += bitoffset / BITS_PER_UNIT;
15086 return offset < tree_to_uhwi (DECL_SIZE_UNIT (inner));
15089 /* A for_each_rtx callback for which DATA points to the instruction
15090 containing *X. Stop the search if we find a MEM that is not safe
15091 from R10K speculation. */
15094 r10k_needs_protection_p_1 (rtx *loc, void *data)
15103 && MEM_OFFSET_KNOWN_P (mem)
15104 && r10k_safe_mem_expr_p (MEM_EXPR (mem), MEM_OFFSET (mem)))
15107 if (r10k_safe_address_p (XEXP (mem, 0), (rtx_insn *) data))
15113 /* A note_stores callback for which DATA points to an instruction pointer.
15114 If *DATA is nonnull, make it null if it X contains a MEM that is not
15115 safe from R10K speculation. */
15118 r10k_needs_protection_p_store (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
15121 rtx_insn **insn_ptr;
15123 insn_ptr = (rtx_insn **) data;
15124 if (*insn_ptr && for_each_rtx (&x, r10k_needs_protection_p_1, *insn_ptr))
15128 /* A for_each_rtx callback that iterates over the pattern of a CALL_INSN.
15129 Return nonzero if the call is not to a declared function. */
15132 r10k_needs_protection_p_call (rtx *loc, void *data ATTRIBUTE_UNUSED)
15141 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DECL (x))
15147 /* Return true if instruction INSN needs to be protected by an R10K
15151 r10k_needs_protection_p (rtx_insn *insn)
15154 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_call, NULL);
15156 if (mips_r10k_cache_barrier == R10K_CACHE_BARRIER_STORE)
15158 note_stores (PATTERN (insn), r10k_needs_protection_p_store, &insn);
15159 return insn == NULL_RTX;
15162 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_1, insn);
15165 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
15166 edge is unconditional. */
15169 r10k_protected_bb_p (basic_block bb, sbitmap protected_bbs)
15174 FOR_EACH_EDGE (e, ei, bb->preds)
15175 if (!single_succ_p (e->src)
15176 || !bitmap_bit_p (protected_bbs, e->src->index)
15177 || (e->flags & EDGE_COMPLEX) != 0)
15182 /* Implement -mr10k-cache-barrier= for the current function. */
15185 r10k_insert_cache_barriers (void)
15187 int *rev_post_order;
15190 sbitmap protected_bbs;
15191 rtx_insn *insn, *end;
15192 rtx unprotected_region;
15196 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
15200 /* Calculate dominators. */
15201 calculate_dominance_info (CDI_DOMINATORS);
15203 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
15204 X is protected by a cache barrier. */
15205 protected_bbs = sbitmap_alloc (last_basic_block_for_fn (cfun));
15206 bitmap_clear (protected_bbs);
15208 /* Iterate over the basic blocks in reverse post-order. */
15209 rev_post_order = XNEWVEC (int, last_basic_block_for_fn (cfun));
15210 n = pre_and_rev_post_order_compute (NULL, rev_post_order, false);
15211 for (i = 0; i < n; i++)
15213 bb = BASIC_BLOCK_FOR_FN (cfun, rev_post_order[i]);
15215 /* If this block is only reached by unconditional edges, and if the
15216 source of every edge is protected, the beginning of the block is
15218 if (r10k_protected_bb_p (bb, protected_bbs))
15219 unprotected_region = NULL_RTX;
15221 unprotected_region = pc_rtx;
15222 end = NEXT_INSN (BB_END (bb));
15224 /* UNPROTECTED_REGION is:
15226 - null if we are processing a protected region,
15227 - pc_rtx if we are processing an unprotected region but have
15228 not yet found the first instruction in it
15229 - the first instruction in an unprotected region otherwise. */
15230 for (insn = BB_HEAD (bb); insn != end; insn = NEXT_INSN (insn))
15232 if (unprotected_region && USEFUL_INSN_P (insn))
15234 if (recog_memoized (insn) == CODE_FOR_mips_cache)
15235 /* This CACHE instruction protects the following code. */
15236 unprotected_region = NULL_RTX;
15239 /* See if INSN is the first instruction in this
15240 unprotected region. */
15241 if (unprotected_region == pc_rtx)
15242 unprotected_region = insn;
15244 /* See if INSN needs to be protected. If so,
15245 we must insert a cache barrier somewhere between
15246 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
15247 clear which position is better performance-wise,
15248 but as a tie-breaker, we assume that it is better
15249 to allow delay slots to be back-filled where
15250 possible, and that it is better not to insert
15251 barriers in the middle of already-scheduled code.
15252 We therefore insert the barrier at the beginning
15254 if (r10k_needs_protection_p (insn))
15256 emit_insn_before (gen_r10k_cache_barrier (),
15257 unprotected_region);
15258 unprotected_region = NULL_RTX;
15264 /* The called function is not required to protect the exit path.
15265 The code that follows a call is therefore unprotected. */
15266 unprotected_region = pc_rtx;
15269 /* Record whether the end of this block is protected. */
15270 if (unprotected_region == NULL_RTX)
15271 bitmap_set_bit (protected_bbs, bb->index);
15273 XDELETEVEC (rev_post_order);
15275 sbitmap_free (protected_bbs);
15277 free_dominance_info (CDI_DOMINATORS);
15280 /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX
15281 otherwise. If INSN has two call rtx, then store the second one in
15285 mips_call_expr_from_insn (rtx_insn *insn, rtx *second_call)
15290 if (!CALL_P (insn))
15293 x = PATTERN (insn);
15294 if (GET_CODE (x) == PARALLEL)
15296 /* Calls returning complex values have two CALL rtx. Look for the second
15297 one here, and return it via the SECOND_CALL arg. */
15298 x2 = XVECEXP (x, 0, 1);
15299 if (GET_CODE (x2) == SET)
15301 if (GET_CODE (x2) == CALL)
15304 x = XVECEXP (x, 0, 0);
15306 if (GET_CODE (x) == SET)
15308 gcc_assert (GET_CODE (x) == CALL);
15313 /* REG is set in DEF. See if the definition is one of the ways we load a
15314 register with a symbol address for a mips_use_pic_fn_addr_reg_p call.
15315 If it is, return the symbol reference of the function, otherwise return
15318 If RECURSE_P is true, use mips_find_pic_call_symbol to interpret
15319 the values of source registers, otherwise treat such registers as
15320 having an unknown value. */
15323 mips_pic_call_symbol_from_set (df_ref def, rtx reg, bool recurse_p)
15325 rtx_insn *def_insn;
15328 if (DF_REF_IS_ARTIFICIAL (def))
15331 def_insn = DF_REF_INSN (def);
15332 set = single_set (def_insn);
15333 if (set && rtx_equal_p (SET_DEST (set), reg))
15335 rtx note, src, symbol;
15337 /* First see whether the source is a plain symbol. This is used
15338 when calling symbols that are not lazily bound. */
15339 src = SET_SRC (set);
15340 if (GET_CODE (src) == SYMBOL_REF)
15343 /* Handle %call16 references. */
15344 symbol = mips_strip_unspec_call (src);
15347 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
15351 /* If we have something more complicated, look for a
15352 REG_EQUAL or REG_EQUIV note. */
15353 note = find_reg_equal_equiv_note (def_insn);
15354 if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF)
15355 return XEXP (note, 0);
15357 /* Follow at most one simple register copy. Such copies are
15358 interesting in cases like:
15362 locally_binding_fn (...);
15367 locally_binding_fn (...);
15369 locally_binding_fn (...);
15371 where the load of locally_binding_fn can legitimately be
15372 hoisted or shared. However, we do not expect to see complex
15373 chains of copies, so a full worklist solution to the problem
15374 would probably be overkill. */
15375 if (recurse_p && REG_P (src))
15376 return mips_find_pic_call_symbol (def_insn, src, false);
15382 /* Find the definition of the use of REG in INSN. See if the definition
15383 is one of the ways we load a register with a symbol address for a
15384 mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference
15385 of the function, otherwise return NULL_RTX. RECURSE_P is as for
15386 mips_pic_call_symbol_from_set. */
15389 mips_find_pic_call_symbol (rtx_insn *insn, rtx reg, bool recurse_p)
15392 struct df_link *defs;
15395 use = df_find_use (insn, regno_reg_rtx[REGNO (reg)]);
15398 defs = DF_REF_CHAIN (use);
15401 symbol = mips_pic_call_symbol_from_set (defs->ref, reg, recurse_p);
15405 /* If we have more than one definition, they need to be identical. */
15406 for (defs = defs->next; defs; defs = defs->next)
15410 other = mips_pic_call_symbol_from_set (defs->ref, reg, recurse_p);
15411 if (!rtx_equal_p (symbol, other))
15418 /* Replace the args_size operand of the call expression CALL with the
15419 call-attribute UNSPEC and fill in SYMBOL as the function symbol. */
15422 mips_annotate_pic_call_expr (rtx call, rtx symbol)
15426 args_size = XEXP (call, 1);
15427 XEXP (call, 1) = gen_rtx_UNSPEC (GET_MODE (args_size),
15428 gen_rtvec (2, args_size, symbol),
15432 /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See
15433 if instead of the arg_size argument it contains the call attributes. If
15434 yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function
15435 symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is
15439 mips_get_pic_call_symbol (rtx *operands, int args_size_opno)
15441 rtx args_size, symbol;
15443 if (!TARGET_RELAX_PIC_CALLS || args_size_opno == -1)
15446 args_size = operands[args_size_opno];
15447 if (GET_CODE (args_size) != UNSPEC)
15449 gcc_assert (XINT (args_size, 1) == UNSPEC_CALL_ATTR);
15451 symbol = XVECEXP (args_size, 0, 1);
15452 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
15454 operands[args_size_opno] = symbol;
15458 /* Use DF to annotate PIC indirect calls with the function symbol they
15462 mips_annotate_pic_calls (void)
15467 FOR_EACH_BB_FN (bb, cfun)
15468 FOR_BB_INSNS (bb, insn)
15470 rtx call, reg, symbol, second_call;
15473 call = mips_call_expr_from_insn (insn, &second_call);
15476 gcc_assert (MEM_P (XEXP (call, 0)));
15477 reg = XEXP (XEXP (call, 0), 0);
15481 symbol = mips_find_pic_call_symbol (insn, reg, true);
15484 mips_annotate_pic_call_expr (call, symbol);
15486 mips_annotate_pic_call_expr (second_call, symbol);
15491 /* A temporary variable used by for_each_rtx callbacks, etc. */
15492 static rtx_insn *mips_sim_insn;
15494 /* A structure representing the state of the processor pipeline.
15495 Used by the mips_sim_* family of functions. */
15497 /* The maximum number of instructions that can be issued in a cycle.
15498 (Caches mips_issue_rate.) */
15499 unsigned int issue_rate;
15501 /* The current simulation time. */
15504 /* How many more instructions can be issued in the current cycle. */
15505 unsigned int insns_left;
15507 /* LAST_SET[X].INSN is the last instruction to set register X.
15508 LAST_SET[X].TIME is the time at which that instruction was issued.
15509 INSN is null if no instruction has yet set register X. */
15513 } last_set[FIRST_PSEUDO_REGISTER];
15515 /* The pipeline's current DFA state. */
15519 /* Reset STATE to the initial simulation state. */
15522 mips_sim_reset (struct mips_sim *state)
15524 curr_state = state->dfa_state;
15527 state->insns_left = state->issue_rate;
15528 memset (&state->last_set, 0, sizeof (state->last_set));
15529 state_reset (curr_state);
15531 targetm.sched.init (0, false, 0);
15532 advance_state (curr_state);
15535 /* Initialize STATE before its first use. DFA_STATE points to an
15536 allocated but uninitialized DFA state. */
15539 mips_sim_init (struct mips_sim *state, state_t dfa_state)
15541 if (targetm.sched.init_dfa_pre_cycle_insn)
15542 targetm.sched.init_dfa_pre_cycle_insn ();
15544 if (targetm.sched.init_dfa_post_cycle_insn)
15545 targetm.sched.init_dfa_post_cycle_insn ();
15547 state->issue_rate = mips_issue_rate ();
15548 state->dfa_state = dfa_state;
15549 mips_sim_reset (state);
15552 /* Advance STATE by one clock cycle. */
15555 mips_sim_next_cycle (struct mips_sim *state)
15557 curr_state = state->dfa_state;
15560 state->insns_left = state->issue_rate;
15561 advance_state (curr_state);
15564 /* Advance simulation state STATE until instruction INSN can read
15568 mips_sim_wait_reg (struct mips_sim *state, rtx_insn *insn, rtx reg)
15570 unsigned int regno, end_regno;
15572 end_regno = END_REGNO (reg);
15573 for (regno = REGNO (reg); regno < end_regno; regno++)
15574 if (state->last_set[regno].insn != 0)
15578 t = (state->last_set[regno].time
15579 + insn_latency (state->last_set[regno].insn, insn));
15580 while (state->time < t)
15581 mips_sim_next_cycle (state);
15585 /* A for_each_rtx callback. If *X is a register, advance simulation state
15586 DATA until mips_sim_insn can read the register's value. */
15589 mips_sim_wait_regs_2 (rtx *x, void *data)
15592 mips_sim_wait_reg ((struct mips_sim *) data, mips_sim_insn, *x);
15596 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
15599 mips_sim_wait_regs_1 (rtx *x, void *data)
15601 for_each_rtx (x, mips_sim_wait_regs_2, data);
15604 /* Advance simulation state STATE until all of INSN's register
15605 dependencies are satisfied. */
15608 mips_sim_wait_regs (struct mips_sim *state, rtx_insn *insn)
15610 mips_sim_insn = insn;
15611 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
15614 /* Advance simulation state STATE until the units required by
15615 instruction INSN are available. */
15618 mips_sim_wait_units (struct mips_sim *state, rtx_insn *insn)
15622 tmp_state = alloca (state_size ());
15623 while (state->insns_left == 0
15624 || (memcpy (tmp_state, state->dfa_state, state_size ()),
15625 state_transition (tmp_state, insn) >= 0))
15626 mips_sim_next_cycle (state);
15629 /* Advance simulation state STATE until INSN is ready to issue. */
15632 mips_sim_wait_insn (struct mips_sim *state, rtx_insn *insn)
15634 mips_sim_wait_regs (state, insn);
15635 mips_sim_wait_units (state, insn);
15638 /* mips_sim_insn has just set X. Update the LAST_SET array
15639 in simulation state DATA. */
15642 mips_sim_record_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
15644 struct mips_sim *state;
15646 state = (struct mips_sim *) data;
15649 unsigned int regno, end_regno;
15651 end_regno = END_REGNO (x);
15652 for (regno = REGNO (x); regno < end_regno; regno++)
15654 state->last_set[regno].insn = mips_sim_insn;
15655 state->last_set[regno].time = state->time;
15660 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
15661 can issue immediately (i.e., that mips_sim_wait_insn has already
15665 mips_sim_issue_insn (struct mips_sim *state, rtx_insn *insn)
15667 curr_state = state->dfa_state;
15669 state_transition (curr_state, insn);
15670 state->insns_left = targetm.sched.variable_issue (0, false, insn,
15671 state->insns_left);
15673 mips_sim_insn = insn;
15674 note_stores (PATTERN (insn), mips_sim_record_set, state);
15677 /* Simulate issuing a NOP in state STATE. */
15680 mips_sim_issue_nop (struct mips_sim *state)
15682 if (state->insns_left == 0)
15683 mips_sim_next_cycle (state);
15684 state->insns_left--;
15687 /* Update simulation state STATE so that it's ready to accept the instruction
15688 after INSN. INSN should be part of the main rtl chain, not a member of a
15692 mips_sim_finish_insn (struct mips_sim *state, rtx_insn *insn)
15694 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
15696 mips_sim_issue_nop (state);
15698 switch (GET_CODE (SEQ_BEGIN (insn)))
15702 /* We can't predict the processor state after a call or label. */
15703 mips_sim_reset (state);
15707 /* The delay slots of branch likely instructions are only executed
15708 when the branch is taken. Therefore, if the caller has simulated
15709 the delay slot instruction, STATE does not really reflect the state
15710 of the pipeline for the instruction after the delay slot. Also,
15711 branch likely instructions tend to incur a penalty when not taken,
15712 so there will probably be an extra delay between the branch and
15713 the instruction after the delay slot. */
15714 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
15715 mips_sim_reset (state);
15723 /* Use simulator state STATE to calculate the execution time of
15724 instruction sequence SEQ. */
15726 static unsigned int
15727 mips_seq_time (struct mips_sim *state, rtx_insn *seq)
15729 mips_sim_reset (state);
15730 for (rtx_insn *insn = seq; insn; insn = NEXT_INSN (insn))
15732 mips_sim_wait_insn (state, insn);
15733 mips_sim_issue_insn (state, insn);
15735 return state->time;
15738 /* Return the execution-time cost of mips_tuning_info.fast_mult_zero_zero_p
15739 setting SETTING, using STATE to simulate instruction sequences. */
15741 static unsigned int
15742 mips_mult_zero_zero_cost (struct mips_sim *state, bool setting)
15744 mips_tuning_info.fast_mult_zero_zero_p = setting;
15747 enum machine_mode dword_mode = TARGET_64BIT ? TImode : DImode;
15748 rtx hilo = gen_rtx_REG (dword_mode, MD_REG_FIRST);
15749 mips_emit_move_or_split (hilo, const0_rtx, SPLIT_FOR_SPEED);
15751 /* If the target provides mulsidi3_32bit then that's the most likely
15752 consumer of the result. Test for bypasses. */
15753 if (dword_mode == DImode && HAVE_maddsidi4)
15755 rtx gpr = gen_rtx_REG (SImode, GP_REG_FIRST + 4);
15756 emit_insn (gen_maddsidi4 (hilo, gpr, gpr, hilo));
15759 unsigned int time = mips_seq_time (state, get_insns ());
15764 /* Check the relative speeds of "MULT $0,$0" and "MTLO $0; MTHI $0"
15765 and set up mips_tuning_info.fast_mult_zero_zero_p accordingly.
15766 Prefer MULT -- which is shorter -- in the event of a tie. */
15769 mips_set_fast_mult_zero_zero_p (struct mips_sim *state)
15772 /* No MTLO or MTHI available. */
15773 mips_tuning_info.fast_mult_zero_zero_p = true;
15776 unsigned int true_time = mips_mult_zero_zero_cost (state, true);
15777 unsigned int false_time = mips_mult_zero_zero_cost (state, false);
15778 mips_tuning_info.fast_mult_zero_zero_p = (true_time <= false_time);
15782 /* Set up costs based on the current architecture and tuning settings. */
15785 mips_set_tuning_info (void)
15787 if (mips_tuning_info.initialized_p
15788 && mips_tuning_info.arch == mips_arch
15789 && mips_tuning_info.tune == mips_tune
15790 && mips_tuning_info.mips16_p == TARGET_MIPS16)
15793 mips_tuning_info.arch = mips_arch;
15794 mips_tuning_info.tune = mips_tune;
15795 mips_tuning_info.mips16_p = TARGET_MIPS16;
15796 mips_tuning_info.initialized_p = true;
15800 struct mips_sim state;
15801 mips_sim_init (&state, alloca (state_size ()));
15803 mips_set_fast_mult_zero_zero_p (&state);
15808 /* Implement TARGET_EXPAND_TO_RTL_HOOK. */
15811 mips_expand_to_rtl_hook (void)
15813 /* We need to call this at a point where we can safely create sequences
15814 of instructions, so TARGET_OVERRIDE_OPTIONS is too early. We also
15815 need to call it at a point where the DFA infrastructure is not
15816 already in use, so we can't just call it lazily on demand.
15818 At present, mips_tuning_info is only needed during post-expand
15819 RTL passes such as split_insns, so this hook should be early enough.
15820 We may need to move the call elsewhere if mips_tuning_info starts
15821 to be used for other things (such as rtx_costs, or expanders that
15822 could be called during gimple optimization). */
15823 mips_set_tuning_info ();
15826 /* The VR4130 pipeline issues aligned pairs of instructions together,
15827 but it stalls the second instruction if it depends on the first.
15828 In order to cut down the amount of logic required, this dependence
15829 check is not based on a full instruction decode. Instead, any non-SPECIAL
15830 instruction is assumed to modify the register specified by bits 20-16
15831 (which is usually the "rt" field).
15833 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
15834 input, so we can end up with a false dependence between the branch
15835 and its delay slot. If this situation occurs in instruction INSN,
15836 try to avoid it by swapping rs and rt. */
15839 vr4130_avoid_branch_rt_conflict (rtx_insn *insn)
15841 rtx_insn *first, *second;
15843 first = SEQ_BEGIN (insn);
15844 second = SEQ_END (insn);
15846 && NONJUMP_INSN_P (second)
15847 && GET_CODE (PATTERN (first)) == SET
15848 && GET_CODE (SET_DEST (PATTERN (first))) == PC
15849 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
15851 /* Check for the right kind of condition. */
15852 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
15853 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
15854 && REG_P (XEXP (cond, 0))
15855 && REG_P (XEXP (cond, 1))
15856 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
15857 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
15859 /* SECOND mentions the rt register but not the rs register. */
15860 rtx tmp = XEXP (cond, 0);
15861 XEXP (cond, 0) = XEXP (cond, 1);
15862 XEXP (cond, 1) = tmp;
15867 /* Implement -mvr4130-align. Go through each basic block and simulate the
15868 processor pipeline. If we find that a pair of instructions could execute
15869 in parallel, and the first of those instructions is not 8-byte aligned,
15870 insert a nop to make it aligned. */
15873 vr4130_align_insns (void)
15875 struct mips_sim state;
15876 rtx_insn *insn, *subinsn, *last, *last2, *next;
15881 /* LAST is the last instruction before INSN to have a nonzero length.
15882 LAST2 is the last such instruction before LAST. */
15886 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
15889 mips_sim_init (&state, alloca (state_size ()));
15890 for (insn = get_insns (); insn != 0; insn = next)
15892 unsigned int length;
15894 next = NEXT_INSN (insn);
15896 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
15897 This isn't really related to the alignment pass, but we do it on
15898 the fly to avoid a separate instruction walk. */
15899 vr4130_avoid_branch_rt_conflict (insn);
15901 length = get_attr_length (insn);
15902 if (length > 0 && USEFUL_INSN_P (insn))
15903 FOR_EACH_SUBINSN (subinsn, insn)
15905 mips_sim_wait_insn (&state, subinsn);
15907 /* If we want this instruction to issue in parallel with the
15908 previous one, make sure that the previous instruction is
15909 aligned. There are several reasons why this isn't worthwhile
15910 when the second instruction is a call:
15912 - Calls are less likely to be performance critical,
15913 - There's a good chance that the delay slot can execute
15914 in parallel with the call.
15915 - The return address would then be unaligned.
15917 In general, if we're going to insert a nop between instructions
15918 X and Y, it's better to insert it immediately after X. That
15919 way, if the nop makes Y aligned, it will also align any labels
15920 between X and Y. */
15921 if (state.insns_left != state.issue_rate
15922 && !CALL_P (subinsn))
15924 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
15926 /* SUBINSN is the first instruction in INSN and INSN is
15927 aligned. We want to align the previous instruction
15928 instead, so insert a nop between LAST2 and LAST.
15930 Note that LAST could be either a single instruction
15931 or a branch with a delay slot. In the latter case,
15932 LAST, like INSN, is already aligned, but the delay
15933 slot must have some extra delay that stops it from
15934 issuing at the same time as the branch. We therefore
15935 insert a nop before the branch in order to align its
15937 gcc_assert (last2);
15938 emit_insn_after (gen_nop (), last2);
15941 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
15943 /* SUBINSN is the delay slot of INSN, but INSN is
15944 currently unaligned. Insert a nop between
15945 LAST and INSN to align it. */
15947 emit_insn_after (gen_nop (), last);
15951 mips_sim_issue_insn (&state, subinsn);
15953 mips_sim_finish_insn (&state, insn);
15955 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
15956 length = get_attr_length (insn);
15959 /* If the instruction is an asm statement or multi-instruction
15960 mips.md patern, the length is only an estimate. Insert an
15961 8 byte alignment after it so that the following instructions
15962 can be handled correctly. */
15963 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
15964 && (recog_memoized (insn) < 0 || length >= 8))
15966 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
15967 next = NEXT_INSN (next);
15968 mips_sim_next_cycle (&state);
15971 else if (length & 4)
15972 aligned_p = !aligned_p;
15977 /* See whether INSN is an aligned label. */
15978 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
15984 /* This structure records that the current function has a LO_SUM
15985 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
15986 the largest offset applied to BASE by all such LO_SUMs. */
15987 struct mips_lo_sum_offset {
15989 HOST_WIDE_INT offset;
15992 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
15995 mips_hash_base (rtx base)
15997 int do_not_record_p;
15999 return hash_rtx (base, GET_MODE (base), &do_not_record_p, NULL, false);
16002 /* Hashtable helpers. */
16004 struct mips_lo_sum_offset_hasher : typed_free_remove <mips_lo_sum_offset>
16006 typedef mips_lo_sum_offset value_type;
16007 typedef rtx_def compare_type;
16008 static inline hashval_t hash (const value_type *);
16009 static inline bool equal (const value_type *, const compare_type *);
16012 /* Hash-table callbacks for mips_lo_sum_offsets. */
16015 mips_lo_sum_offset_hasher::hash (const value_type *entry)
16017 return mips_hash_base (entry->base);
16021 mips_lo_sum_offset_hasher::equal (const value_type *entry,
16022 const compare_type *value)
16024 return rtx_equal_p (entry->base, value);
16027 typedef hash_table<mips_lo_sum_offset_hasher> mips_offset_table;
16029 /* Look up symbolic constant X in HTAB, which is a hash table of
16030 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
16031 paired with a recorded LO_SUM, otherwise record X in the table. */
16034 mips_lo_sum_offset_lookup (mips_offset_table *htab, rtx x,
16035 enum insert_option option)
16038 mips_lo_sum_offset **slot;
16039 struct mips_lo_sum_offset *entry;
16041 /* Split X into a base and offset. */
16042 split_const (x, &base, &offset);
16043 if (UNSPEC_ADDRESS_P (base))
16044 base = UNSPEC_ADDRESS (base);
16046 /* Look up the base in the hash table. */
16047 slot = htab->find_slot_with_hash (base, mips_hash_base (base), option);
16051 entry = (struct mips_lo_sum_offset *) *slot;
16052 if (option == INSERT)
16056 entry = XNEW (struct mips_lo_sum_offset);
16057 entry->base = base;
16058 entry->offset = INTVAL (offset);
16063 if (INTVAL (offset) > entry->offset)
16064 entry->offset = INTVAL (offset);
16067 return INTVAL (offset) <= entry->offset;
16070 /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table.
16071 Record every LO_SUM in *LOC. */
16074 mips_record_lo_sum (rtx *loc, void *data)
16076 if (GET_CODE (*loc) == LO_SUM)
16077 mips_lo_sum_offset_lookup ((mips_offset_table*) data,
16078 XEXP (*loc, 1), INSERT);
16082 /* Return true if INSN is a SET of an orphaned high-part relocation.
16083 HTAB is a hash table of mips_lo_sum_offsets that describes all the
16084 LO_SUMs in the current function. */
16087 mips_orphaned_high_part_p (mips_offset_table *htab, rtx_insn *insn)
16089 enum mips_symbol_type type;
16092 set = single_set (insn);
16095 /* Check for %his. */
16097 if (GET_CODE (x) == HIGH
16098 && absolute_symbolic_operand (XEXP (x, 0), VOIDmode))
16099 return !mips_lo_sum_offset_lookup (htab, XEXP (x, 0), NO_INSERT);
16101 /* Check for local %gots (and %got_pages, which is redundant but OK). */
16102 if (GET_CODE (x) == UNSPEC
16103 && XINT (x, 1) == UNSPEC_LOAD_GOT
16104 && mips_symbolic_constant_p (XVECEXP (x, 0, 1),
16105 SYMBOL_CONTEXT_LEA, &type)
16106 && type == SYMBOL_GOTOFF_PAGE)
16107 return !mips_lo_sum_offset_lookup (htab, XVECEXP (x, 0, 1), NO_INSERT);
16112 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
16113 INSN and a previous instruction, avoid it by inserting nops after
16116 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
16117 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
16118 before using the value of that register. *HILO_DELAY counts the
16119 number of instructions since the last hilo hazard (that is,
16120 the number of instructions since the last MFLO or MFHI).
16122 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
16123 for the next instruction.
16125 LO_REG is an rtx for the LO register, used in dependence checking. */
16128 mips_avoid_hazard (rtx_insn *after, rtx_insn *insn, int *hilo_delay,
16129 rtx *delayed_reg, rtx lo_reg)
16134 pattern = PATTERN (insn);
16136 /* Do not put the whole function in .set noreorder if it contains
16137 an asm statement. We don't know whether there will be hazards
16138 between the asm statement and the gcc-generated code. */
16139 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
16140 cfun->machine->all_noreorder_p = false;
16142 /* Ignore zero-length instructions (barriers and the like). */
16143 ninsns = get_attr_length (insn) / 4;
16147 /* Work out how many nops are needed. Note that we only care about
16148 registers that are explicitly mentioned in the instruction's pattern.
16149 It doesn't matter that calls use the argument registers or that they
16150 clobber hi and lo. */
16151 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
16152 nops = 2 - *hilo_delay;
16153 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
16158 /* Insert the nops between this instruction and the previous one.
16159 Each new nop takes us further from the last hilo hazard. */
16160 *hilo_delay += nops;
16162 emit_insn_after (gen_hazard_nop (), after);
16164 /* Set up the state for the next instruction. */
16165 *hilo_delay += ninsns;
16167 if (INSN_CODE (insn) >= 0)
16168 switch (get_attr_hazard (insn))
16178 set = single_set (insn);
16180 *delayed_reg = SET_DEST (set);
16185 /* Go through the instruction stream and insert nops where necessary.
16186 Also delete any high-part relocations whose partnering low parts
16187 are now all dead. See if the whole function can then be put into
16188 .set noreorder and .set nomacro. */
16191 mips_reorg_process_insns (void)
16193 rtx_insn *insn, *last_insn, *subinsn, *next_insn;
16194 rtx lo_reg, delayed_reg;
16197 /* Force all instructions to be split into their final form. */
16198 split_all_insns_noflow ();
16200 /* Recalculate instruction lengths without taking nops into account. */
16201 cfun->machine->ignore_hazard_length_p = true;
16202 shorten_branches (get_insns ());
16204 cfun->machine->all_noreorder_p = true;
16206 /* We don't track MIPS16 PC-relative offsets closely enough to make
16207 a good job of "set .noreorder" code in MIPS16 mode. */
16209 cfun->machine->all_noreorder_p = false;
16211 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
16212 if (!TARGET_EXPLICIT_RELOCS)
16213 cfun->machine->all_noreorder_p = false;
16215 /* Profiled functions can't be all noreorder because the profiler
16216 support uses assembler macros. */
16218 cfun->machine->all_noreorder_p = false;
16220 /* Code compiled with -mfix-vr4120, -mfix-rm7000 or -mfix-24k can't be
16221 all noreorder because we rely on the assembler to work around some
16222 errata. The R5900 too has several bugs. */
16223 if (TARGET_FIX_VR4120
16224 || TARGET_FIX_RM7000
16226 || TARGET_MIPS5900)
16227 cfun->machine->all_noreorder_p = false;
16229 /* The same is true for -mfix-vr4130 if we might generate MFLO or
16230 MFHI instructions. Note that we avoid using MFLO and MFHI if
16231 the VR4130 MACC and DMACC instructions are available instead;
16232 see the *mfhilo_{si,di}_macc patterns. */
16233 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
16234 cfun->machine->all_noreorder_p = false;
16236 mips_offset_table htab (37);
16238 /* Make a first pass over the instructions, recording all the LO_SUMs. */
16239 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
16240 FOR_EACH_SUBINSN (subinsn, insn)
16241 if (USEFUL_INSN_P (subinsn))
16243 rtx body = PATTERN (insn);
16244 int noperands = asm_noperands (body);
16245 if (noperands >= 0)
16247 rtx *ops = XALLOCAVEC (rtx, noperands);
16248 bool *used = XALLOCAVEC (bool, noperands);
16249 const char *string = decode_asm_operands (body, ops, NULL, NULL,
16251 get_referenced_operands (string, used, noperands);
16252 for (int i = 0; i < noperands; ++i)
16254 for_each_rtx (&ops[i], mips_record_lo_sum, &htab);
16257 for_each_rtx (&PATTERN (subinsn), mips_record_lo_sum, &htab);
16263 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
16265 /* Make a second pass over the instructions. Delete orphaned
16266 high-part relocations or turn them into NOPs. Avoid hazards
16267 by inserting NOPs. */
16268 for (insn = get_insns (); insn != 0; insn = next_insn)
16270 next_insn = NEXT_INSN (insn);
16271 if (USEFUL_INSN_P (insn))
16273 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
16275 /* If we find an orphaned high-part relocation in a delay
16276 slot, it's easier to turn that instruction into a NOP than
16277 to delete it. The delay slot will be a NOP either way. */
16278 FOR_EACH_SUBINSN (subinsn, insn)
16279 if (INSN_P (subinsn))
16281 if (mips_orphaned_high_part_p (&htab, subinsn))
16283 PATTERN (subinsn) = gen_nop ();
16284 INSN_CODE (subinsn) = CODE_FOR_nop;
16286 mips_avoid_hazard (last_insn, subinsn, &hilo_delay,
16287 &delayed_reg, lo_reg);
16293 /* INSN is a single instruction. Delete it if it's an
16294 orphaned high-part relocation. */
16295 if (mips_orphaned_high_part_p (&htab, insn))
16296 delete_insn (insn);
16297 /* Also delete cache barriers if the last instruction
16298 was an annulled branch. INSN will not be speculatively
16300 else if (recog_memoized (insn) == CODE_FOR_r10k_cache_barrier
16302 && JUMP_P (SEQ_BEGIN (last_insn))
16303 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn)))
16304 delete_insn (insn);
16307 mips_avoid_hazard (last_insn, insn, &hilo_delay,
16308 &delayed_reg, lo_reg);
16316 /* Return true if the function has a long branch instruction. */
16319 mips_has_long_branch_p (void)
16321 rtx_insn *insn, *subinsn;
16324 /* We need up-to-date instruction lengths. */
16325 shorten_branches (get_insns ());
16327 /* Look for a branch that is longer than normal. The normal length for
16328 non-MIPS16 branches is 8, because the length includes the delay slot.
16329 It is 4 for MIPS16, because MIPS16 branches are extended instructions,
16330 but they have no delay slot. */
16331 normal_length = (TARGET_MIPS16 ? 4 : 8);
16332 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
16333 FOR_EACH_SUBINSN (subinsn, insn)
16334 if (JUMP_P (subinsn)
16335 && get_attr_length (subinsn) > normal_length
16336 && (any_condjump_p (subinsn) || any_uncondjump_p (subinsn)))
16342 /* If we are using a GOT, but have not decided to use a global pointer yet,
16343 see whether we need one to implement long branches. Convert the ghost
16344 global-pointer instructions into real ones if so. */
16347 mips_expand_ghost_gp_insns (void)
16349 /* Quick exit if we already know that we will or won't need a
16351 if (!TARGET_USE_GOT
16352 || cfun->machine->global_pointer == INVALID_REGNUM
16353 || mips_must_initialize_gp_p ())
16356 /* Run a full check for long branches. */
16357 if (!mips_has_long_branch_p ())
16360 /* We've now established that we need $gp. */
16361 cfun->machine->must_initialize_gp_p = true;
16362 split_all_insns_noflow ();
16367 /* Subroutine of mips_reorg to manage passes that require DF. */
16370 mips_df_reorg (void)
16372 /* Create def-use chains. */
16373 df_set_flags (DF_EQ_NOTES);
16374 df_chain_add_problem (DF_UD_CHAIN);
16377 if (TARGET_RELAX_PIC_CALLS)
16378 mips_annotate_pic_calls ();
16380 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE)
16381 r10k_insert_cache_barriers ();
16383 df_finish_pass (false);
16386 /* Emit code to load LABEL_REF SRC into MIPS16 register DEST. This is
16387 called very late in mips_reorg, but the caller is required to run
16388 mips16_lay_out_constants on the result. */
16391 mips16_load_branch_target (rtx dest, rtx src)
16393 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
16397 if (mips_cfun_has_cprestore_slot_p ())
16398 mips_emit_move (dest, mips_cprestore_slot (dest, true));
16400 mips_emit_move (dest, pic_offset_table_rtx);
16401 page = mips_unspec_address (src, SYMBOL_GOTOFF_PAGE);
16402 low = mips_unspec_address (src, SYMBOL_GOT_PAGE_OFST);
16403 emit_insn (gen_rtx_SET (VOIDmode, dest,
16404 PMODE_INSN (gen_unspec_got, (dest, page))));
16405 emit_insn (gen_rtx_SET (VOIDmode, dest,
16406 gen_rtx_LO_SUM (Pmode, dest, low)));
16410 src = mips_unspec_address (src, SYMBOL_ABSOLUTE);
16411 mips_emit_move (dest, src);
16415 /* If we're compiling a MIPS16 function, look for and split any long branches.
16416 This must be called after all other instruction modifications in
16420 mips16_split_long_branches (void)
16422 bool something_changed;
16424 if (!TARGET_MIPS16)
16427 /* Loop until the alignments for all targets are sufficient. */
16432 shorten_branches (get_insns ());
16433 something_changed = false;
16434 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
16436 && get_attr_length (insn) > 4
16437 && (any_condjump_p (insn) || any_uncondjump_p (insn)))
16439 rtx old_label, temp, saved_temp;
16440 rtx_code_label *new_label;
16442 rtx_insn *jump, *jump_sequence;
16446 /* Free up a MIPS16 register by saving it in $1. */
16447 saved_temp = gen_rtx_REG (Pmode, AT_REGNUM);
16448 temp = gen_rtx_REG (Pmode, GP_REG_FIRST + 2);
16449 emit_move_insn (saved_temp, temp);
16451 /* Load the branch target into TEMP. */
16452 old_label = JUMP_LABEL (insn);
16453 target = gen_rtx_LABEL_REF (Pmode, old_label);
16454 mips16_load_branch_target (temp, target);
16456 /* Jump to the target and restore the register's
16458 jump = emit_jump_insn (PMODE_INSN (gen_indirect_jump_and_restore,
16459 (temp, temp, saved_temp)));
16460 JUMP_LABEL (jump) = old_label;
16461 LABEL_NUSES (old_label)++;
16463 /* Rewrite any symbolic references that are supposed to use
16464 a PC-relative constant pool. */
16465 mips16_lay_out_constants (false);
16467 if (simplejump_p (insn))
16468 /* We're going to replace INSN with a longer form. */
16472 /* Create a branch-around label for the original
16474 new_label = gen_label_rtx ();
16475 emit_label (new_label);
16478 jump_sequence = get_insns ();
16481 emit_insn_after (jump_sequence, insn);
16483 invert_jump (insn, new_label, false);
16485 delete_insn (insn);
16486 something_changed = true;
16489 while (something_changed);
16492 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
16497 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during
16498 insn splitting in mips16_lay_out_constants, DF insn info is only kept up
16499 to date if the CFG is available. */
16500 if (mips_cfg_in_reorg ())
16501 compute_bb_for_insn ();
16502 mips16_lay_out_constants (true);
16503 if (mips_cfg_in_reorg ())
16506 free_bb_for_insn ();
16510 /* We use a machine specific pass to do a second machine dependent reorg
16511 pass after delay branch scheduling. */
16513 static unsigned int
16514 mips_machine_reorg2 (void)
16516 mips_reorg_process_insns ();
16518 && TARGET_EXPLICIT_RELOCS
16520 && TARGET_VR4130_ALIGN)
16521 vr4130_align_insns ();
16522 if (mips_expand_ghost_gp_insns ())
16523 /* The expansion could invalidate some of the VR4130 alignment
16524 optimizations, but this should be an extremely rare case anyhow. */
16525 mips_reorg_process_insns ();
16526 mips16_split_long_branches ();
16532 const pass_data pass_data_mips_machine_reorg2 =
16534 RTL_PASS, /* type */
16535 "mach2", /* name */
16536 OPTGROUP_NONE, /* optinfo_flags */
16537 TV_MACH_DEP, /* tv_id */
16538 0, /* properties_required */
16539 0, /* properties_provided */
16540 0, /* properties_destroyed */
16541 0, /* todo_flags_start */
16542 0, /* todo_flags_finish */
16545 class pass_mips_machine_reorg2 : public rtl_opt_pass
16548 pass_mips_machine_reorg2(gcc::context *ctxt)
16549 : rtl_opt_pass(pass_data_mips_machine_reorg2, ctxt)
16552 /* opt_pass methods: */
16553 virtual unsigned int execute (function *) { return mips_machine_reorg2 (); }
16555 }; // class pass_mips_machine_reorg2
16557 } // anon namespace
16560 make_pass_mips_machine_reorg2 (gcc::context *ctxt)
16562 return new pass_mips_machine_reorg2 (ctxt);
16566 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
16567 in order to avoid duplicating too much logic from elsewhere. */
16570 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
16571 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
16574 rtx this_rtx, temp1, temp2, fnaddr;
16576 bool use_sibcall_p;
16578 /* Pretend to be a post-reload pass while generating rtl. */
16579 reload_completed = 1;
16581 /* Mark the end of the (empty) prologue. */
16582 emit_note (NOTE_INSN_PROLOGUE_END);
16584 /* Determine if we can use a sibcall to call FUNCTION directly. */
16585 fnaddr = XEXP (DECL_RTL (function), 0);
16586 use_sibcall_p = (mips_function_ok_for_sibcall (function, NULL)
16587 && const_call_insn_operand (fnaddr, Pmode));
16589 /* Determine if we need to load FNADDR from the GOT. */
16591 && (mips_got_symbol_type_p
16592 (mips_classify_symbol (fnaddr, SYMBOL_CONTEXT_LEA))))
16594 /* Pick a global pointer. Use a call-clobbered register if
16595 TARGET_CALL_SAVED_GP. */
16596 cfun->machine->global_pointer
16597 = TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM;
16598 cfun->machine->must_initialize_gp_p = true;
16599 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
16601 /* Set up the global pointer for n32 or n64 abicalls. */
16602 mips_emit_loadgp ();
16605 /* We need two temporary registers in some cases. */
16606 temp1 = gen_rtx_REG (Pmode, 2);
16607 temp2 = gen_rtx_REG (Pmode, 3);
16609 /* Find out which register contains the "this" pointer. */
16610 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
16611 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
16613 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST);
16615 /* Add DELTA to THIS_RTX. */
16618 rtx offset = GEN_INT (delta);
16619 if (!SMALL_OPERAND (delta))
16621 mips_emit_move (temp1, offset);
16624 emit_insn (gen_add3_insn (this_rtx, this_rtx, offset));
16627 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
16628 if (vcall_offset != 0)
16632 /* Set TEMP1 to *THIS_RTX. */
16633 mips_emit_move (temp1, gen_rtx_MEM (Pmode, this_rtx));
16635 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
16636 addr = mips_add_offset (temp2, temp1, vcall_offset);
16638 /* Load the offset and add it to THIS_RTX. */
16639 mips_emit_move (temp1, gen_rtx_MEM (Pmode, addr));
16640 emit_insn (gen_add3_insn (this_rtx, this_rtx, temp1));
16643 /* Jump to the target function. Use a sibcall if direct jumps are
16644 allowed, otherwise load the address into a register first. */
16647 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
16648 SIBLING_CALL_P (insn) = 1;
16652 /* This is messy. GAS treats "la $25,foo" as part of a call
16653 sequence and may allow a global "foo" to be lazily bound.
16654 The general move patterns therefore reject this combination.
16656 In this context, lazy binding would actually be OK
16657 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
16658 TARGET_CALL_SAVED_GP; see mips_load_call_address.
16659 We must therefore load the address via a temporary
16660 register if mips_dangerous_for_la25_p.
16662 If we jump to the temporary register rather than $25,
16663 the assembler can use the move insn to fill the jump's
16666 We can use the same technique for MIPS16 code, where $25
16667 is not a valid JR register. */
16668 if (TARGET_USE_PIC_FN_ADDR_REG
16670 && !mips_dangerous_for_la25_p (fnaddr))
16671 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
16672 mips_load_call_address (MIPS_CALL_SIBCALL, temp1, fnaddr);
16674 if (TARGET_USE_PIC_FN_ADDR_REG
16675 && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
16676 mips_emit_move (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
16677 emit_jump_insn (gen_indirect_jump (temp1));
16680 /* Run just enough of rest_of_compilation. This sequence was
16681 "borrowed" from alpha.c. */
16682 insn = get_insns ();
16683 split_all_insns_noflow ();
16684 mips16_lay_out_constants (true);
16685 shorten_branches (insn);
16686 final_start_function (insn, file, 1);
16687 final (insn, file, 1);
16688 final_end_function ();
16690 /* Clean up the vars set above. Note that final_end_function resets
16691 the global pointer for us. */
16692 reload_completed = 0;
16696 /* The last argument passed to mips_set_compression_mode,
16697 or negative if the function hasn't been called yet. */
16698 static unsigned int old_compression_mode = -1;
16700 /* Set up the target-dependent global state for ISA mode COMPRESSION_MODE,
16701 which is either MASK_MIPS16 or MASK_MICROMIPS. */
16704 mips_set_compression_mode (unsigned int compression_mode)
16707 if (compression_mode == old_compression_mode)
16710 /* Restore base settings of various flags. */
16711 target_flags = mips_base_target_flags;
16712 flag_schedule_insns = mips_base_schedule_insns;
16713 flag_reorder_blocks_and_partition = mips_base_reorder_blocks_and_partition;
16714 flag_move_loop_invariants = mips_base_move_loop_invariants;
16715 align_loops = mips_base_align_loops;
16716 align_jumps = mips_base_align_jumps;
16717 align_functions = mips_base_align_functions;
16718 target_flags &= ~(MASK_MIPS16 | MASK_MICROMIPS);
16719 target_flags |= compression_mode;
16721 if (compression_mode & MASK_MIPS16)
16723 /* Switch to MIPS16 mode. */
16724 target_flags |= MASK_MIPS16;
16726 /* Turn off SYNCI if it was on, MIPS16 doesn't support it. */
16727 target_flags &= ~MASK_SYNCI;
16729 /* Don't run the scheduler before reload, since it tends to
16730 increase register pressure. */
16731 flag_schedule_insns = 0;
16733 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
16734 the whole function to be in a single section. */
16735 flag_reorder_blocks_and_partition = 0;
16737 /* Don't move loop invariants, because it tends to increase
16738 register pressure. It also introduces an extra move in cases
16739 where the constant is the first operand in a two-operand binary
16740 instruction, or when it forms a register argument to a functon
16742 flag_move_loop_invariants = 0;
16744 target_flags |= MASK_EXPLICIT_RELOCS;
16746 /* Experiments suggest we get the best overall section-anchor
16747 results from using the range of an unextended LW or SW. Code
16748 that makes heavy use of byte or short accesses can do better
16749 with ranges of 0...31 and 0...63 respectively, but most code is
16750 sensitive to the range of LW and SW instead. */
16751 targetm.min_anchor_offset = 0;
16752 targetm.max_anchor_offset = 127;
16754 targetm.const_anchor = 0;
16756 /* MIPS16 has no BAL instruction. */
16757 target_flags &= ~MASK_RELAX_PIC_CALLS;
16759 /* The R4000 errata don't apply to any known MIPS16 cores.
16760 It's simpler to make the R4000 fixes and MIPS16 mode
16761 mutually exclusive. */
16762 target_flags &= ~MASK_FIX_R4000;
16764 if (flag_pic && !TARGET_OLDABI)
16765 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
16768 sorry ("MIPS16 -mxgot code");
16770 if (TARGET_HARD_FLOAT_ABI && !TARGET_OLDABI)
16771 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
16775 /* Switch to microMIPS or the standard encoding. */
16777 if (TARGET_MICROMIPS)
16778 /* Avoid branch likely. */
16779 target_flags &= ~MASK_BRANCHLIKELY;
16781 /* Provide default values for align_* for 64-bit targets. */
16784 if (align_loops == 0)
16786 if (align_jumps == 0)
16788 if (align_functions == 0)
16789 align_functions = 8;
16792 targetm.min_anchor_offset = -32768;
16793 targetm.max_anchor_offset = 32767;
16795 targetm.const_anchor = 0x8000;
16798 /* (Re)initialize MIPS target internals for new ISA. */
16799 mips_init_relocs ();
16801 if (compression_mode & MASK_MIPS16)
16803 if (!mips16_globals)
16804 mips16_globals = save_target_globals_default_opts ();
16806 restore_target_globals (mips16_globals);
16809 restore_target_globals (&default_target_globals);
16811 old_compression_mode = compression_mode;
16814 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
16815 function should use the MIPS16 or microMIPS ISA and switch modes
16819 mips_set_current_function (tree fndecl)
16821 mips_set_compression_mode (mips_get_compress_mode (fndecl));
16824 /* Allocate a chunk of memory for per-function machine-dependent data. */
16826 static struct machine_function *
16827 mips_init_machine_status (void)
16829 return ggc_cleared_alloc<machine_function> ();
16832 /* Return the processor associated with the given ISA level, or null
16833 if the ISA isn't valid. */
16835 static const struct mips_cpu_info *
16836 mips_cpu_info_from_isa (int isa)
16840 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
16841 if (mips_cpu_info_table[i].isa == isa)
16842 return mips_cpu_info_table + i;
16847 /* Return a mips_cpu_info entry determined by an option valued
16850 static const struct mips_cpu_info *
16851 mips_cpu_info_from_opt (int opt)
16855 case MIPS_ARCH_OPTION_FROM_ABI:
16856 /* 'from-abi' selects the most compatible architecture for the
16857 given ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit
16858 ABIs. For the EABIs, we have to decide whether we're using
16859 the 32-bit or 64-bit version. */
16860 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
16861 : ABI_NEEDS_64BIT_REGS ? 3
16862 : (TARGET_64BIT ? 3 : 1));
16864 case MIPS_ARCH_OPTION_NATIVE:
16865 gcc_unreachable ();
16868 return &mips_cpu_info_table[opt];
16872 /* Return a default mips_cpu_info entry, given that no -march= option
16873 was explicitly specified. */
16875 static const struct mips_cpu_info *
16876 mips_default_arch (void)
16878 #if defined (MIPS_CPU_STRING_DEFAULT)
16880 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
16881 if (strcmp (mips_cpu_info_table[i].name, MIPS_CPU_STRING_DEFAULT) == 0)
16882 return mips_cpu_info_table + i;
16883 gcc_unreachable ();
16884 #elif defined (MIPS_ISA_DEFAULT)
16885 return mips_cpu_info_from_isa (MIPS_ISA_DEFAULT);
16887 /* 'from-abi' makes a good default: you get whatever the ABI
16889 return mips_cpu_info_from_opt (MIPS_ARCH_OPTION_FROM_ABI);
16893 /* Set up globals to generate code for the ISA or processor
16894 described by INFO. */
16897 mips_set_architecture (const struct mips_cpu_info *info)
16901 mips_arch_info = info;
16902 mips_arch = info->cpu;
16903 mips_isa = info->isa;
16907 mips_isa_rev = (mips_isa & 31) + 1;
16911 /* Likewise for tuning. */
16914 mips_set_tune (const struct mips_cpu_info *info)
16918 mips_tune_info = info;
16919 mips_tune = info->cpu;
16923 /* Implement TARGET_OPTION_OVERRIDE. */
16926 mips_option_override (void)
16928 int i, start, regno, mode;
16930 if (global_options_set.x_mips_isa_option)
16931 mips_isa_option_info = &mips_cpu_info_table[mips_isa_option];
16933 #ifdef SUBTARGET_OVERRIDE_OPTIONS
16934 SUBTARGET_OVERRIDE_OPTIONS;
16937 /* MIPS16 and microMIPS cannot coexist. */
16938 if (TARGET_MICROMIPS && TARGET_MIPS16)
16939 error ("unsupported combination: %s", "-mips16 -mmicromips");
16941 /* Save the base compression state and process flags as though we
16942 were generating uncompressed code. */
16943 mips_base_compression_flags = TARGET_COMPRESSION;
16944 target_flags &= ~TARGET_COMPRESSION;
16946 /* -mno-float overrides -mhard-float and -msoft-float. */
16947 if (TARGET_NO_FLOAT)
16949 target_flags |= MASK_SOFT_FLOAT_ABI;
16950 target_flags_explicit |= MASK_SOFT_FLOAT_ABI;
16953 if (TARGET_FLIP_MIPS16)
16954 TARGET_INTERLINK_COMPRESSED = 1;
16956 /* Set the small data limit. */
16957 mips_small_data_threshold = (global_options_set.x_g_switch_value
16959 : MIPS_DEFAULT_GVALUE);
16961 /* The following code determines the architecture and register size.
16962 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
16963 The GAS and GCC code should be kept in sync as much as possible. */
16965 if (global_options_set.x_mips_arch_option)
16966 mips_set_architecture (mips_cpu_info_from_opt (mips_arch_option));
16968 if (mips_isa_option_info != 0)
16970 if (mips_arch_info == 0)
16971 mips_set_architecture (mips_isa_option_info);
16972 else if (mips_arch_info->isa != mips_isa_option_info->isa)
16973 error ("%<-%s%> conflicts with the other architecture options, "
16974 "which specify a %s processor",
16975 mips_isa_option_info->name,
16976 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
16979 if (mips_arch_info == 0)
16980 mips_set_architecture (mips_default_arch ());
16982 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
16983 error ("%<-march=%s%> is not compatible with the selected ABI",
16984 mips_arch_info->name);
16986 /* Optimize for mips_arch, unless -mtune selects a different processor. */
16987 if (global_options_set.x_mips_tune_option)
16988 mips_set_tune (mips_cpu_info_from_opt (mips_tune_option));
16990 if (mips_tune_info == 0)
16991 mips_set_tune (mips_arch_info);
16993 if ((target_flags_explicit & MASK_64BIT) != 0)
16995 /* The user specified the size of the integer registers. Make sure
16996 it agrees with the ABI and ISA. */
16997 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
16998 error ("%<-mgp64%> used with a 32-bit processor");
16999 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
17000 error ("%<-mgp32%> used with a 64-bit ABI");
17001 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
17002 error ("%<-mgp64%> used with a 32-bit ABI");
17006 /* Infer the integer register size from the ABI and processor.
17007 Restrict ourselves to 32-bit registers if that's all the
17008 processor has, or if the ABI cannot handle 64-bit registers. */
17009 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
17010 target_flags &= ~MASK_64BIT;
17012 target_flags |= MASK_64BIT;
17015 if ((target_flags_explicit & MASK_FLOAT64) != 0)
17017 if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
17018 error ("unsupported combination: %s", "-mfp64 -msingle-float");
17019 else if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
17020 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
17021 else if (!TARGET_64BIT && TARGET_FLOAT64)
17023 if (!ISA_HAS_MXHC1)
17024 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
17025 " the target supports the mfhc1 and mthc1 instructions");
17026 else if (mips_abi != ABI_32)
17027 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
17033 /* -msingle-float selects 32-bit float registers. Otherwise the
17034 float registers should be the same size as the integer ones. */
17035 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
17036 target_flags |= MASK_FLOAT64;
17038 target_flags &= ~MASK_FLOAT64;
17041 /* End of code shared with GAS. */
17043 /* The R5900 FPU only supports single precision. */
17044 if (TARGET_MIPS5900 && TARGET_HARD_FLOAT_ABI && TARGET_DOUBLE_FLOAT)
17045 error ("unsupported combination: %s",
17046 "-march=r5900 -mhard-float -mdouble-float");
17048 /* If a -mlong* option was given, check that it matches the ABI,
17049 otherwise infer the -mlong* setting from the other options. */
17050 if ((target_flags_explicit & MASK_LONG64) != 0)
17054 if (mips_abi == ABI_N32)
17055 error ("%qs is incompatible with %qs", "-mabi=n32", "-mlong64");
17056 else if (mips_abi == ABI_32)
17057 error ("%qs is incompatible with %qs", "-mabi=32", "-mlong64");
17058 else if (mips_abi == ABI_O64 && TARGET_ABICALLS)
17059 /* We have traditionally allowed non-abicalls code to use
17060 an LP64 form of o64. However, it would take a bit more
17061 effort to support the combination of 32-bit GOT entries
17062 and 64-bit pointers, so we treat the abicalls case as
17064 error ("the combination of %qs and %qs is incompatible with %qs",
17065 "-mabi=o64", "-mabicalls", "-mlong64");
17069 if (mips_abi == ABI_64)
17070 error ("%qs is incompatible with %qs", "-mabi=64", "-mlong32");
17075 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
17076 target_flags |= MASK_LONG64;
17078 target_flags &= ~MASK_LONG64;
17081 if (!TARGET_OLDABI)
17082 flag_pcc_struct_return = 0;
17084 /* Decide which rtx_costs structure to use. */
17086 mips_cost = &mips_rtx_cost_optimize_size;
17088 mips_cost = &mips_rtx_cost_data[mips_tune];
17090 /* If the user hasn't specified a branch cost, use the processor's
17092 if (mips_branch_cost == 0)
17093 mips_branch_cost = mips_cost->branch_cost;
17095 /* If neither -mbranch-likely nor -mno-branch-likely was given
17096 on the command line, set MASK_BRANCHLIKELY based on the target
17097 architecture and tuning flags. Annulled delay slots are a
17098 size win, so we only consider the processor-specific tuning
17099 for !optimize_size. */
17100 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
17102 if (ISA_HAS_BRANCHLIKELY
17104 || (mips_tune_info->tune_flags & PTF_AVOID_BRANCHLIKELY) == 0))
17105 target_flags |= MASK_BRANCHLIKELY;
17107 target_flags &= ~MASK_BRANCHLIKELY;
17109 else if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
17110 warning (0, "the %qs architecture does not support branch-likely"
17111 " instructions", mips_arch_info->name);
17113 /* If the user hasn't specified -mimadd or -mno-imadd set
17114 MASK_IMADD based on the target architecture and tuning
17116 if ((target_flags_explicit & MASK_IMADD) == 0)
17118 if (ISA_HAS_MADD_MSUB &&
17119 (mips_tune_info->tune_flags & PTF_AVOID_IMADD) == 0)
17120 target_flags |= MASK_IMADD;
17122 target_flags &= ~MASK_IMADD;
17124 else if (TARGET_IMADD && !ISA_HAS_MADD_MSUB)
17125 warning (0, "the %qs architecture does not support madd or msub"
17126 " instructions", mips_arch_info->name);
17128 /* The effect of -mabicalls isn't defined for the EABI. */
17129 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
17131 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
17132 target_flags &= ~MASK_ABICALLS;
17135 /* PIC requires -mabicalls. */
17138 if (mips_abi == ABI_EABI)
17139 error ("cannot generate position-independent code for %qs",
17141 else if (!TARGET_ABICALLS)
17142 error ("position-independent code requires %qs", "-mabicalls");
17145 if (TARGET_ABICALLS_PIC2)
17146 /* We need to set flag_pic for executables as well as DSOs
17147 because we may reference symbols that are not defined in
17148 the final executable. (MIPS does not use things like
17149 copy relocs, for example.)
17151 There is a body of code that uses __PIC__ to distinguish
17152 between -mabicalls and -mno-abicalls code. The non-__PIC__
17153 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
17154 long as any indirect jumps use $25. */
17157 /* -mvr4130-align is a "speed over size" optimization: it usually produces
17158 faster code, but at the expense of more nops. Enable it at -O3 and
17160 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
17161 target_flags |= MASK_VR4130_ALIGN;
17163 /* Prefer a call to memcpy over inline code when optimizing for size,
17164 though see MOVE_RATIO in mips.h. */
17165 if (optimize_size && (target_flags_explicit & MASK_MEMCPY) == 0)
17166 target_flags |= MASK_MEMCPY;
17168 /* If we have a nonzero small-data limit, check that the -mgpopt
17169 setting is consistent with the other target flags. */
17170 if (mips_small_data_threshold > 0)
17174 if (!TARGET_EXPLICIT_RELOCS)
17175 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
17177 TARGET_LOCAL_SDATA = false;
17178 TARGET_EXTERN_SDATA = false;
17182 if (TARGET_VXWORKS_RTP)
17183 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
17185 if (TARGET_ABICALLS)
17186 warning (0, "cannot use small-data accesses for %qs",
17191 /* Pre-IEEE 754-2008 MIPS hardware has a quirky almost-IEEE format
17192 for all its floating point. */
17193 if (mips_nan != MIPS_IEEE_754_2008)
17195 REAL_MODE_FORMAT (SFmode) = &mips_single_format;
17196 REAL_MODE_FORMAT (DFmode) = &mips_double_format;
17197 REAL_MODE_FORMAT (TFmode) = &mips_quad_format;
17200 /* Make sure that the user didn't turn off paired single support when
17201 MIPS-3D support is requested. */
17203 && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
17204 && !TARGET_PAIRED_SINGLE_FLOAT)
17205 error ("%<-mips3d%> requires %<-mpaired-single%>");
17207 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
17209 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
17211 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
17212 and TARGET_HARD_FLOAT_ABI are both true. */
17213 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT_ABI))
17215 error ("%qs must be used with %qs",
17216 TARGET_MIPS3D ? "-mips3d" : "-mpaired-single",
17217 TARGET_HARD_FLOAT_ABI ? "-mfp64" : "-mhard-float");
17218 target_flags &= ~MASK_PAIRED_SINGLE_FLOAT;
17222 /* Make sure that -mpaired-single is only used on ISAs that support it.
17223 We must disable it otherwise since it relies on other ISA properties
17224 like ISA_HAS_8CC having their normal values. */
17225 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_HAS_PAIRED_SINGLE)
17227 error ("the %qs architecture does not support paired-single"
17228 " instructions", mips_arch_info->name);
17229 target_flags &= ~MASK_PAIRED_SINGLE_FLOAT;
17233 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
17234 && !TARGET_CACHE_BUILTIN)
17236 error ("%qs requires a target that provides the %qs instruction",
17237 "-mr10k-cache-barrier", "cache");
17238 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE;
17241 /* If TARGET_DSPR2, enable TARGET_DSP. */
17245 /* .eh_frame addresses should be the same width as a C pointer.
17246 Most MIPS ABIs support only one pointer size, so the assembler
17247 will usually know exactly how big an .eh_frame address is.
17249 Unfortunately, this is not true of the 64-bit EABI. The ABI was
17250 originally defined to use 64-bit pointers (i.e. it is LP64), and
17251 this is still the default mode. However, we also support an n32-like
17252 ILP32 mode, which is selected by -mlong32. The problem is that the
17253 assembler has traditionally not had an -mlong option, so it has
17254 traditionally not known whether we're using the ILP32 or LP64 form.
17256 As it happens, gas versions up to and including 2.19 use _32-bit_
17257 addresses for EABI64 .cfi_* directives. This is wrong for the
17258 default LP64 mode, so we can't use the directives by default.
17259 Moreover, since gas's current behavior is at odds with gcc's
17260 default behavior, it seems unwise to rely on future versions
17261 of gas behaving the same way. We therefore avoid using .cfi
17262 directives for -mlong32 as well. */
17263 if (mips_abi == ABI_EABI && TARGET_64BIT)
17264 flag_dwarf2_cfi_asm = 0;
17266 /* .cfi_* directives generate a read-only section, so fall back on
17267 manual .eh_frame creation if we need the section to be writable. */
17268 if (TARGET_WRITABLE_EH_FRAME)
17269 flag_dwarf2_cfi_asm = 0;
17271 mips_init_print_operand_punct ();
17273 /* Set up array to map GCC register number to debug register number.
17274 Ignore the special purpose register numbers. */
17276 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
17278 mips_dbx_regno[i] = IGNORED_DWARF_REGNUM;
17279 if (GP_REG_P (i) || FP_REG_P (i) || ALL_COP_REG_P (i))
17280 mips_dwarf_regno[i] = i;
17282 mips_dwarf_regno[i] = INVALID_REGNUM;
17285 start = GP_DBX_FIRST - GP_REG_FIRST;
17286 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
17287 mips_dbx_regno[i] = i + start;
17289 start = FP_DBX_FIRST - FP_REG_FIRST;
17290 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
17291 mips_dbx_regno[i] = i + start;
17293 /* Accumulator debug registers use big-endian ordering. */
17294 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
17295 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
17296 mips_dwarf_regno[HI_REGNUM] = MD_REG_FIRST + 0;
17297 mips_dwarf_regno[LO_REGNUM] = MD_REG_FIRST + 1;
17298 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
17300 mips_dwarf_regno[i + TARGET_LITTLE_ENDIAN] = i;
17301 mips_dwarf_regno[i + TARGET_BIG_ENDIAN] = i + 1;
17304 /* Set up mips_hard_regno_mode_ok. */
17305 for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
17306 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
17307 mips_hard_regno_mode_ok[mode][regno]
17308 = mips_hard_regno_mode_ok_p (regno, (enum machine_mode) mode);
17310 /* Function to allocate machine-dependent function status. */
17311 init_machine_status = &mips_init_machine_status;
17313 /* Default to working around R4000 errata only if the processor
17314 was selected explicitly. */
17315 if ((target_flags_explicit & MASK_FIX_R4000) == 0
17316 && strcmp (mips_arch_info->name, "r4000") == 0)
17317 target_flags |= MASK_FIX_R4000;
17319 /* Default to working around R4400 errata only if the processor
17320 was selected explicitly. */
17321 if ((target_flags_explicit & MASK_FIX_R4400) == 0
17322 && strcmp (mips_arch_info->name, "r4400") == 0)
17323 target_flags |= MASK_FIX_R4400;
17325 /* Default to working around R10000 errata only if the processor
17326 was selected explicitly. */
17327 if ((target_flags_explicit & MASK_FIX_R10000) == 0
17328 && strcmp (mips_arch_info->name, "r10000") == 0)
17329 target_flags |= MASK_FIX_R10000;
17331 /* Make sure that branch-likely instructions available when using
17332 -mfix-r10000. The instructions are not available if either:
17334 1. -mno-branch-likely was passed.
17335 2. The selected ISA does not support branch-likely and
17336 the command line does not include -mbranch-likely. */
17337 if (TARGET_FIX_R10000
17338 && ((target_flags_explicit & MASK_BRANCHLIKELY) == 0
17339 ? !ISA_HAS_BRANCHLIKELY
17340 : !TARGET_BRANCHLIKELY))
17341 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
17343 if (TARGET_SYNCI && !ISA_HAS_SYNCI)
17345 warning (0, "the %qs architecture does not support the synci "
17346 "instruction", mips_arch_info->name);
17347 target_flags &= ~MASK_SYNCI;
17350 /* Only optimize PIC indirect calls if they are actually required. */
17351 if (!TARGET_USE_GOT || !TARGET_EXPLICIT_RELOCS)
17352 target_flags &= ~MASK_RELAX_PIC_CALLS;
17354 /* Save base state of options. */
17355 mips_base_target_flags = target_flags;
17356 mips_base_schedule_insns = flag_schedule_insns;
17357 mips_base_reorder_blocks_and_partition = flag_reorder_blocks_and_partition;
17358 mips_base_move_loop_invariants = flag_move_loop_invariants;
17359 mips_base_align_loops = align_loops;
17360 mips_base_align_jumps = align_jumps;
17361 mips_base_align_functions = align_functions;
17363 /* Now select the ISA mode.
17365 Do all CPP-sensitive stuff in uncompressed mode; we'll switch modes
17366 later if required. */
17367 mips_set_compression_mode (0);
17369 /* We register a second machine specific reorg pass after delay slot
17370 filling. Registering the pass must be done at start up. It's
17371 convenient to do it here. */
17372 opt_pass *new_pass = make_pass_mips_machine_reorg2 (g);
17373 struct register_pass_info insert_pass_mips_machine_reorg2 =
17375 new_pass, /* pass */
17376 "dbr", /* reference_pass_name */
17377 1, /* ref_pass_instance_number */
17378 PASS_POS_INSERT_AFTER /* po_op */
17380 register_pass (&insert_pass_mips_machine_reorg2);
17382 if (TARGET_HARD_FLOAT_ABI && TARGET_MIPS5900)
17383 REAL_MODE_FORMAT (SFmode) = &spu_single_format;
17386 /* Swap the register information for registers I and I + 1, which
17387 currently have the wrong endianness. Note that the registers'
17388 fixedness and call-clobberedness might have been set on the
17392 mips_swap_registers (unsigned int i)
17397 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
17398 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
17400 SWAP_INT (fixed_regs[i], fixed_regs[i + 1]);
17401 SWAP_INT (call_used_regs[i], call_used_regs[i + 1]);
17402 SWAP_INT (call_really_used_regs[i], call_really_used_regs[i + 1]);
17403 SWAP_STRING (reg_names[i], reg_names[i + 1]);
17409 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
17412 mips_conditional_register_usage (void)
17417 /* These DSP control register fields are global. */
17418 global_regs[CCDSP_PO_REGNUM] = 1;
17419 global_regs[CCDSP_SC_REGNUM] = 1;
17422 AND_COMPL_HARD_REG_SET (accessible_reg_set,
17423 reg_class_contents[(int) DSP_ACC_REGS]);
17425 if (!TARGET_HARD_FLOAT)
17427 AND_COMPL_HARD_REG_SET (accessible_reg_set,
17428 reg_class_contents[(int) FP_REGS]);
17429 AND_COMPL_HARD_REG_SET (accessible_reg_set,
17430 reg_class_contents[(int) ST_REGS]);
17432 else if (!ISA_HAS_8CC)
17434 /* We only have a single condition-code register. We implement
17435 this by fixing all the condition-code registers and generating
17436 RTL that refers directly to ST_REG_FIRST. */
17437 AND_COMPL_HARD_REG_SET (accessible_reg_set,
17438 reg_class_contents[(int) ST_REGS]);
17439 SET_HARD_REG_BIT (accessible_reg_set, FPSW_REGNUM);
17440 fixed_regs[FPSW_REGNUM] = call_used_regs[FPSW_REGNUM] = 1;
17444 /* In MIPS16 mode, we prohibit the unused $s registers, since they
17445 are call-saved, and saving them via a MIPS16 register would
17446 probably waste more time than just reloading the value.
17448 We permit the $t temporary registers when optimizing for speed
17449 but not when optimizing for space because using them results in
17450 code that is larger (but faster) then not using them. We do
17451 allow $24 (t8) because it is used in CMP and CMPI instructions
17452 and $25 (t9) because it is used as the function call address in
17455 fixed_regs[18] = call_used_regs[18] = 1;
17456 fixed_regs[19] = call_used_regs[19] = 1;
17457 fixed_regs[20] = call_used_regs[20] = 1;
17458 fixed_regs[21] = call_used_regs[21] = 1;
17459 fixed_regs[22] = call_used_regs[22] = 1;
17460 fixed_regs[23] = call_used_regs[23] = 1;
17461 fixed_regs[26] = call_used_regs[26] = 1;
17462 fixed_regs[27] = call_used_regs[27] = 1;
17463 fixed_regs[30] = call_used_regs[30] = 1;
17466 fixed_regs[8] = call_used_regs[8] = 1;
17467 fixed_regs[9] = call_used_regs[9] = 1;
17468 fixed_regs[10] = call_used_regs[10] = 1;
17469 fixed_regs[11] = call_used_regs[11] = 1;
17470 fixed_regs[12] = call_used_regs[12] = 1;
17471 fixed_regs[13] = call_used_regs[13] = 1;
17472 fixed_regs[14] = call_used_regs[14] = 1;
17473 fixed_regs[15] = call_used_regs[15] = 1;
17476 /* Do not allow HI and LO to be treated as register operands.
17477 There are no MTHI or MTLO instructions (or any real need
17478 for them) and one-way registers cannot easily be reloaded. */
17479 AND_COMPL_HARD_REG_SET (operand_reg_set,
17480 reg_class_contents[(int) MD_REGS]);
17482 /* $f20-$f23 are call-clobbered for n64. */
17483 if (mips_abi == ABI_64)
17486 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
17487 call_really_used_regs[regno] = call_used_regs[regno] = 1;
17489 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
17491 if (mips_abi == ABI_N32)
17494 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
17495 call_really_used_regs[regno] = call_used_regs[regno] = 1;
17497 /* Make sure that double-register accumulator values are correctly
17498 ordered for the current endianness. */
17499 if (TARGET_LITTLE_ENDIAN)
17501 unsigned int regno;
17503 mips_swap_registers (MD_REG_FIRST);
17504 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno += 2)
17505 mips_swap_registers (regno);
17509 /* Implement EH_USES. */
17512 mips_eh_uses (unsigned int regno)
17514 if (reload_completed && !TARGET_ABSOLUTE_JUMPS)
17516 /* We need to force certain registers to be live in order to handle
17517 PIC long branches correctly. See mips_must_initialize_gp_p for
17519 if (mips_cfun_has_cprestore_slot_p ())
17521 if (regno == CPRESTORE_SLOT_REGNUM)
17526 if (cfun->machine->global_pointer == regno)
17534 /* Implement EPILOGUE_USES. */
17537 mips_epilogue_uses (unsigned int regno)
17539 /* Say that the epilogue uses the return address register. Note that
17540 in the case of sibcalls, the values "used by the epilogue" are
17541 considered live at the start of the called function. */
17542 if (regno == RETURN_ADDR_REGNUM)
17545 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
17546 See the comment above load_call<mode> for details. */
17547 if (TARGET_USE_GOT && (regno) == GOT_VERSION_REGNUM)
17550 /* An interrupt handler must preserve some registers that are
17551 ordinarily call-clobbered. */
17552 if (cfun->machine->interrupt_handler_p
17553 && mips_interrupt_extra_call_saved_reg_p (regno))
17559 /* A for_each_rtx callback. Stop the search if *X is an AT register. */
17562 mips_at_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
17564 return REG_P (*x) && REGNO (*x) == AT_REGNUM;
17567 /* Return true if INSN needs to be wrapped in ".set noat".
17568 INSN has NOPERANDS operands, stored in OPVEC. */
17571 mips_need_noat_wrapper_p (rtx_insn *insn, rtx *opvec, int noperands)
17575 if (recog_memoized (insn) >= 0)
17576 for (i = 0; i < noperands; i++)
17577 if (for_each_rtx (&opvec[i], mips_at_reg_p, NULL))
17582 /* Implement FINAL_PRESCAN_INSN. */
17585 mips_final_prescan_insn (rtx_insn *insn, rtx *opvec, int noperands)
17587 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
17588 mips_push_asm_switch (&mips_noat);
17591 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */
17594 mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED, rtx_insn *insn,
17595 rtx *opvec, int noperands)
17597 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
17598 mips_pop_asm_switch (&mips_noat);
17601 /* Return the function that is used to expand the <u>mulsidi3 pattern.
17602 EXT_CODE is the code of the extension used. Return NULL if widening
17603 multiplication shouldn't be used. */
17606 mips_mulsidi3_gen_fn (enum rtx_code ext_code)
17610 signed_p = ext_code == SIGN_EXTEND;
17613 /* Don't use widening multiplication with MULT when we have DMUL. Even
17614 with the extension of its input operands DMUL is faster. Note that
17615 the extension is not needed for signed multiplication. In order to
17616 ensure that we always remove the redundant sign-extension in this
17617 case we still expand mulsidi3 for DMUL. */
17619 return signed_p ? gen_mulsidi3_64bit_dmul : NULL;
17622 ? gen_mulsidi3_64bit_mips16
17623 : gen_umulsidi3_64bit_mips16);
17624 if (TARGET_FIX_R4000)
17626 return signed_p ? gen_mulsidi3_64bit : gen_umulsidi3_64bit;
17632 ? gen_mulsidi3_32bit_mips16
17633 : gen_umulsidi3_32bit_mips16);
17634 if (TARGET_FIX_R4000 && !ISA_HAS_DSP)
17635 return signed_p ? gen_mulsidi3_32bit_r4000 : gen_umulsidi3_32bit_r4000;
17636 return signed_p ? gen_mulsidi3_32bit : gen_umulsidi3_32bit;
17640 /* Return true if PATTERN matches the kind of instruction generated by
17641 umips_build_save_restore. SAVE_P is true for store. */
17644 umips_save_restore_pattern_p (bool save_p, rtx pattern)
17648 HOST_WIDE_INT first_offset = 0;
17649 rtx first_base = 0;
17650 unsigned int regmask = 0;
17652 for (n = 0; n < XVECLEN (pattern, 0); n++)
17654 rtx set, reg, mem, this_base;
17655 HOST_WIDE_INT this_offset;
17657 /* Check that we have a SET. */
17658 set = XVECEXP (pattern, 0, n);
17659 if (GET_CODE (set) != SET)
17662 /* Check that the SET is a load (if restoring) or a store
17664 mem = save_p ? SET_DEST (set) : SET_SRC (set);
17665 if (!MEM_P (mem) || MEM_VOLATILE_P (mem))
17668 /* Check that the address is the sum of base and a possibly-zero
17669 constant offset. Determine if the offset is in range. */
17670 mips_split_plus (XEXP (mem, 0), &this_base, &this_offset);
17671 if (!REG_P (this_base))
17676 if (!UMIPS_12BIT_OFFSET_P (this_offset))
17678 first_base = this_base;
17679 first_offset = this_offset;
17683 /* Check that the save slots are consecutive. */
17684 if (REGNO (this_base) != REGNO (first_base)
17685 || this_offset != first_offset + UNITS_PER_WORD * n)
17689 /* Check that SET's other operand is a register. */
17690 reg = save_p ? SET_SRC (set) : SET_DEST (set);
17694 regmask |= 1 << REGNO (reg);
17697 for (i = 0; i < ARRAY_SIZE (umips_swm_mask); i++)
17698 if (regmask == umips_swm_mask[i])
17704 /* Return the assembly instruction for microMIPS LWM or SWM.
17705 SAVE_P and PATTERN are as for umips_save_restore_pattern_p. */
17708 umips_output_save_restore (bool save_p, rtx pattern)
17710 static char buffer[300];
17713 HOST_WIDE_INT offset;
17714 rtx base, mem, set, last_set, last_reg;
17716 /* Parse the pattern. */
17717 gcc_assert (umips_save_restore_pattern_p (save_p, pattern));
17719 s = strcpy (buffer, save_p ? "swm\t" : "lwm\t");
17721 n = XVECLEN (pattern, 0);
17723 set = XVECEXP (pattern, 0, 0);
17724 mem = save_p ? SET_DEST (set) : SET_SRC (set);
17725 mips_split_plus (XEXP (mem, 0), &base, &offset);
17727 last_set = XVECEXP (pattern, 0, n - 1);
17728 last_reg = save_p ? SET_SRC (last_set) : SET_DEST (last_set);
17730 if (REGNO (last_reg) == 31)
17733 gcc_assert (n <= 9);
17737 s += sprintf (s, "%s,", reg_names[16]);
17739 s += sprintf (s, "%s-%s,", reg_names[16], reg_names[15 + n]);
17741 s += sprintf (s, "%s-%s,%s,", reg_names[16], reg_names[23],
17744 if (REGNO (last_reg) == 31)
17745 s += sprintf (s, "%s,", reg_names[31]);
17747 s += sprintf (s, "%d(%s)", (int)offset, reg_names[REGNO (base)]);
17751 /* Return true if MEM1 and MEM2 use the same base register, and the
17752 offset of MEM2 equals the offset of MEM1 plus 4. FIRST_REG is the
17753 register into (from) which the contents of MEM1 will be loaded
17754 (stored), depending on the value of LOAD_P.
17755 SWAP_P is true when the 1st and 2nd instructions are swapped. */
17758 umips_load_store_pair_p_1 (bool load_p, bool swap_p,
17759 rtx first_reg, rtx mem1, rtx mem2)
17762 HOST_WIDE_INT offset1, offset2;
17764 if (!MEM_P (mem1) || !MEM_P (mem2))
17767 mips_split_plus (XEXP (mem1, 0), &base1, &offset1);
17768 mips_split_plus (XEXP (mem2, 0), &base2, &offset2);
17770 if (!REG_P (base1) || !rtx_equal_p (base1, base2))
17773 /* Avoid invalid load pair instructions. */
17774 if (load_p && REGNO (first_reg) == REGNO (base1))
17777 /* We must avoid this case for anti-dependence.
17780 first_reg is $2, but the base is $3. */
17783 && REGNO (first_reg) + 1 == REGNO (base1))
17786 if (offset2 != offset1 + 4)
17789 if (!UMIPS_12BIT_OFFSET_P (offset1))
17795 /* OPERANDS describes the operands to a pair of SETs, in the order
17796 dest1, src1, dest2, src2. Return true if the operands can be used
17797 in an LWP or SWP instruction; LOAD_P says which. */
17800 umips_load_store_pair_p (bool load_p, rtx *operands)
17802 rtx reg1, reg2, mem1, mem2;
17806 reg1 = operands[0];
17807 reg2 = operands[2];
17808 mem1 = operands[1];
17809 mem2 = operands[3];
17813 reg1 = operands[1];
17814 reg2 = operands[3];
17815 mem1 = operands[0];
17816 mem2 = operands[2];
17819 if (REGNO (reg2) == REGNO (reg1) + 1)
17820 return umips_load_store_pair_p_1 (load_p, false, reg1, mem1, mem2);
17822 if (REGNO (reg1) == REGNO (reg2) + 1)
17823 return umips_load_store_pair_p_1 (load_p, true, reg2, mem2, mem1);
17828 /* Return the assembly instruction for a microMIPS LWP or SWP in which
17829 the first register is REG and the first memory slot is MEM.
17830 LOAD_P is true for LWP. */
17833 umips_output_load_store_pair_1 (bool load_p, rtx reg, rtx mem)
17835 rtx ops[] = {reg, mem};
17838 output_asm_insn ("lwp\t%0,%1", ops);
17840 output_asm_insn ("swp\t%0,%1", ops);
17843 /* Output the assembly instruction for a microMIPS LWP or SWP instruction.
17844 LOAD_P and OPERANDS are as for umips_load_store_pair_p. */
17847 umips_output_load_store_pair (bool load_p, rtx *operands)
17849 rtx reg1, reg2, mem1, mem2;
17852 reg1 = operands[0];
17853 reg2 = operands[2];
17854 mem1 = operands[1];
17855 mem2 = operands[3];
17859 reg1 = operands[1];
17860 reg2 = operands[3];
17861 mem1 = operands[0];
17862 mem2 = operands[2];
17865 if (REGNO (reg2) == REGNO (reg1) + 1)
17867 umips_output_load_store_pair_1 (load_p, reg1, mem1);
17871 gcc_assert (REGNO (reg1) == REGNO (reg2) + 1);
17872 umips_output_load_store_pair_1 (load_p, reg2, mem2);
17875 /* Return true if REG1 and REG2 match the criteria for a movep insn. */
17878 umips_movep_target_p (rtx reg1, rtx reg2)
17880 int regno1, regno2, pair;
17882 static const int match[8] = {
17883 0x00000060, /* 5, 6 */
17884 0x000000a0, /* 5, 7 */
17885 0x000000c0, /* 6, 7 */
17886 0x00200010, /* 4, 21 */
17887 0x00400010, /* 4, 22 */
17888 0x00000030, /* 4, 5 */
17889 0x00000050, /* 4, 6 */
17890 0x00000090 /* 4, 7 */
17893 if (!REG_P (reg1) || !REG_P (reg2))
17896 regno1 = REGNO (reg1);
17897 regno2 = REGNO (reg2);
17899 if (!GP_REG_P (regno1) || !GP_REG_P (regno2))
17902 pair = (1 << regno1) | (1 << regno2);
17904 for (i = 0; i < ARRAY_SIZE (match); i++)
17905 if (pair == match[i])
17911 /* Return the size in bytes of the trampoline code, padded to
17912 TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target
17913 function address immediately follow. */
17916 mips_trampoline_code_size (void)
17918 if (TARGET_USE_PIC_FN_ADDR_REG)
17920 else if (ptr_mode == DImode)
17922 else if (ISA_HAS_LOAD_DELAY)
17928 /* Implement TARGET_TRAMPOLINE_INIT. */
17931 mips_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
17933 rtx addr, end_addr, high, low, opcode, mem;
17936 HOST_WIDE_INT end_addr_offset, static_chain_offset, target_function_offset;
17938 /* Work out the offsets of the pointers from the start of the
17939 trampoline code. */
17940 end_addr_offset = mips_trampoline_code_size ();
17941 static_chain_offset = end_addr_offset;
17942 target_function_offset = static_chain_offset + GET_MODE_SIZE (ptr_mode);
17944 /* Get pointers to the beginning and end of the code block. */
17945 addr = force_reg (Pmode, XEXP (m_tramp, 0));
17946 end_addr = mips_force_binary (Pmode, PLUS, addr, GEN_INT (end_addr_offset));
17948 #define OP(X) gen_int_mode (X, SImode)
17950 /* Build up the code in TRAMPOLINE. */
17952 if (TARGET_USE_PIC_FN_ADDR_REG)
17954 /* $25 contains the address of the trampoline. Emit code of the form:
17956 l[wd] $1, target_function_offset($25)
17957 l[wd] $static_chain, static_chain_offset($25)
17960 trampoline[i++] = OP (MIPS_LOAD_PTR (AT_REGNUM,
17961 target_function_offset,
17962 PIC_FUNCTION_ADDR_REGNUM));
17963 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
17964 static_chain_offset,
17965 PIC_FUNCTION_ADDR_REGNUM));
17966 trampoline[i++] = OP (MIPS_JR (AT_REGNUM));
17967 trampoline[i++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM, AT_REGNUM));
17969 else if (ptr_mode == DImode)
17971 /* It's too cumbersome to create the full 64-bit address, so let's
17977 1: l[wd] $25, target_function_offset - 12($31)
17978 l[wd] $static_chain, static_chain_offset - 12($31)
17982 where 12 is the offset of "1:" from the start of the code block. */
17983 trampoline[i++] = OP (MIPS_MOVE (AT_REGNUM, RETURN_ADDR_REGNUM));
17984 trampoline[i++] = OP (MIPS_BAL (1));
17985 trampoline[i++] = OP (MIPS_NOP);
17986 trampoline[i++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
17987 target_function_offset - 12,
17988 RETURN_ADDR_REGNUM));
17989 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
17990 static_chain_offset - 12,
17991 RETURN_ADDR_REGNUM));
17992 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
17993 trampoline[i++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM, AT_REGNUM));
17997 /* If the target has load delays, emit:
17999 lui $1, %hi(end_addr)
18000 lw $25, %lo(end_addr + ...)($1)
18001 lw $static_chain, %lo(end_addr + ...)($1)
18007 lui $1, %hi(end_addr)
18008 lw $25, %lo(end_addr + ...)($1)
18010 lw $static_chain, %lo(end_addr + ...)($1). */
18012 /* Split END_ADDR into %hi and %lo values. Trampolines are aligned
18013 to 64 bits, so the %lo value will have the bottom 3 bits clear. */
18014 high = expand_simple_binop (SImode, PLUS, end_addr, GEN_INT (0x8000),
18015 NULL, false, OPTAB_WIDEN);
18016 high = expand_simple_binop (SImode, LSHIFTRT, high, GEN_INT (16),
18017 NULL, false, OPTAB_WIDEN);
18018 low = convert_to_mode (SImode, gen_lowpart (HImode, end_addr), true);
18020 /* Emit the LUI. */
18021 opcode = OP (MIPS_LUI (AT_REGNUM, 0));
18022 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, high,
18023 NULL, false, OPTAB_WIDEN);
18025 /* Emit the load of the target function. */
18026 opcode = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
18027 target_function_offset - end_addr_offset,
18029 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
18030 NULL, false, OPTAB_WIDEN);
18032 /* Emit the JR here, if we can. */
18033 if (!ISA_HAS_LOAD_DELAY)
18034 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
18036 /* Emit the load of the static chain register. */
18037 opcode = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
18038 static_chain_offset - end_addr_offset,
18040 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
18041 NULL, false, OPTAB_WIDEN);
18043 /* Emit the JR, if we couldn't above. */
18044 if (ISA_HAS_LOAD_DELAY)
18046 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
18047 trampoline[i++] = OP (MIPS_NOP);
18053 /* Copy the trampoline code. Leave any padding uninitialized. */
18054 for (j = 0; j < i; j++)
18056 mem = adjust_address (m_tramp, SImode, j * GET_MODE_SIZE (SImode));
18057 mips_emit_move (mem, trampoline[j]);
18060 /* Set up the static chain pointer field. */
18061 mem = adjust_address (m_tramp, ptr_mode, static_chain_offset);
18062 mips_emit_move (mem, chain_value);
18064 /* Set up the target function field. */
18065 mem = adjust_address (m_tramp, ptr_mode, target_function_offset);
18066 mips_emit_move (mem, XEXP (DECL_RTL (fndecl), 0));
18068 /* Flush the code part of the trampoline. */
18069 emit_insn (gen_add3_insn (end_addr, addr, GEN_INT (TRAMPOLINE_SIZE)));
18070 emit_insn (gen_clear_cache (addr, end_addr));
18073 /* Implement FUNCTION_PROFILER. */
18075 void mips_function_profiler (FILE *file)
18078 sorry ("mips16 function profiling");
18079 if (TARGET_LONG_CALLS)
18081 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */
18082 if (Pmode == DImode)
18083 fprintf (file, "\tdla\t%s,_mcount\n", reg_names[3]);
18085 fprintf (file, "\tla\t%s,_mcount\n", reg_names[3]);
18087 mips_push_asm_switch (&mips_noat);
18088 fprintf (file, "\tmove\t%s,%s\t\t# save current return address\n",
18089 reg_names[AT_REGNUM], reg_names[RETURN_ADDR_REGNUM]);
18090 /* _mcount treats $2 as the static chain register. */
18091 if (cfun->static_chain_decl != NULL)
18092 fprintf (file, "\tmove\t%s,%s\n", reg_names[2],
18093 reg_names[STATIC_CHAIN_REGNUM]);
18094 if (TARGET_MCOUNT_RA_ADDRESS)
18096 /* If TARGET_MCOUNT_RA_ADDRESS load $12 with the address of the
18097 ra save location. */
18098 if (cfun->machine->frame.ra_fp_offset == 0)
18099 /* ra not saved, pass zero. */
18100 fprintf (file, "\tmove\t%s,%s\n", reg_names[12], reg_names[0]);
18102 fprintf (file, "\t%s\t%s," HOST_WIDE_INT_PRINT_DEC "(%s)\n",
18103 Pmode == DImode ? "dla" : "la", reg_names[12],
18104 cfun->machine->frame.ra_fp_offset,
18105 reg_names[STACK_POINTER_REGNUM]);
18107 if (!TARGET_NEWABI)
18109 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n",
18110 TARGET_64BIT ? "dsubu" : "subu",
18111 reg_names[STACK_POINTER_REGNUM],
18112 reg_names[STACK_POINTER_REGNUM],
18113 Pmode == DImode ? 16 : 8);
18115 if (TARGET_LONG_CALLS)
18116 fprintf (file, "\tjalr\t%s\n", reg_names[3]);
18118 fprintf (file, "\tjal\t_mcount\n");
18119 mips_pop_asm_switch (&mips_noat);
18120 /* _mcount treats $2 as the static chain register. */
18121 if (cfun->static_chain_decl != NULL)
18122 fprintf (file, "\tmove\t%s,%s\n", reg_names[STATIC_CHAIN_REGNUM],
18126 /* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default
18127 behaviour of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even
18128 when TARGET_LOONGSON_VECTORS is true. */
18130 static unsigned HOST_WIDE_INT
18131 mips_shift_truncation_mask (enum machine_mode mode)
18133 if (TARGET_LOONGSON_VECTORS && VECTOR_MODE_P (mode))
18136 return GET_MODE_BITSIZE (mode) - 1;
18139 /* Implement TARGET_PREPARE_PCH_SAVE. */
18142 mips_prepare_pch_save (void)
18144 /* We are called in a context where the current MIPS16 vs. non-MIPS16
18145 setting should be irrelevant. The question then is: which setting
18146 makes most sense at load time?
18148 The PCH is loaded before the first token is read. We should never
18149 have switched into MIPS16 mode by that point, and thus should not
18150 have populated mips16_globals. Nor can we load the entire contents
18151 of mips16_globals from the PCH file, because mips16_globals contains
18152 a combination of GGC and non-GGC data.
18154 There is therefore no point in trying save the GGC part of
18155 mips16_globals to the PCH file, or to preserve MIPS16ness across
18156 the PCH save and load. The loading compiler would not have access
18157 to the non-GGC parts of mips16_globals (either from the PCH file,
18158 or from a copy that the loading compiler generated itself) and would
18159 have to call target_reinit anyway.
18161 It therefore seems best to switch back to non-MIPS16 mode at
18162 save time, and to ensure that mips16_globals remains null after
18164 mips_set_compression_mode (0);
18165 mips16_globals = 0;
18168 /* Generate or test for an insn that supports a constant permutation. */
18170 #define MAX_VECT_LEN 8
18172 struct expand_vec_perm_d
18174 rtx target, op0, op1;
18175 unsigned char perm[MAX_VECT_LEN];
18176 enum machine_mode vmode;
18177 unsigned char nelt;
18182 /* Construct (set target (vec_select op0 (parallel perm))) and
18183 return true if that's a valid instruction in the active ISA. */
18186 mips_expand_vselect (rtx target, rtx op0,
18187 const unsigned char *perm, unsigned nelt)
18189 rtx rperm[MAX_VECT_LEN], x;
18193 for (i = 0; i < nelt; ++i)
18194 rperm[i] = GEN_INT (perm[i]);
18196 x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (nelt, rperm));
18197 x = gen_rtx_VEC_SELECT (GET_MODE (target), op0, x);
18198 x = gen_rtx_SET (VOIDmode, target, x);
18200 insn = emit_insn (x);
18201 if (recog_memoized (insn) < 0)
18203 remove_insn (insn);
18209 /* Similar, but generate a vec_concat from op0 and op1 as well. */
18212 mips_expand_vselect_vconcat (rtx target, rtx op0, rtx op1,
18213 const unsigned char *perm, unsigned nelt)
18215 enum machine_mode v2mode;
18218 v2mode = GET_MODE_2XWIDER_MODE (GET_MODE (op0));
18219 x = gen_rtx_VEC_CONCAT (v2mode, op0, op1);
18220 return mips_expand_vselect (target, x, perm, nelt);
18223 /* Recognize patterns for even-odd extraction. */
18226 mips_expand_vpc_loongson_even_odd (struct expand_vec_perm_d *d)
18228 unsigned i, odd, nelt = d->nelt;
18229 rtx t0, t1, t2, t3;
18231 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
18233 /* Even-odd for V2SI/V2SFmode is matched by interleave directly. */
18240 for (i = 1; i < nelt; ++i)
18241 if (d->perm[i] != i * 2 + odd)
18247 /* We need 2*log2(N)-1 operations to achieve odd/even with interleave. */
18248 t0 = gen_reg_rtx (d->vmode);
18249 t1 = gen_reg_rtx (d->vmode);
18253 emit_insn (gen_loongson_punpckhhw (t0, d->op0, d->op1));
18254 emit_insn (gen_loongson_punpcklhw (t1, d->op0, d->op1));
18256 emit_insn (gen_loongson_punpckhhw (d->target, t1, t0));
18258 emit_insn (gen_loongson_punpcklhw (d->target, t1, t0));
18262 t2 = gen_reg_rtx (d->vmode);
18263 t3 = gen_reg_rtx (d->vmode);
18264 emit_insn (gen_loongson_punpckhbh (t0, d->op0, d->op1));
18265 emit_insn (gen_loongson_punpcklbh (t1, d->op0, d->op1));
18266 emit_insn (gen_loongson_punpckhbh (t2, t1, t0));
18267 emit_insn (gen_loongson_punpcklbh (t3, t1, t0));
18269 emit_insn (gen_loongson_punpckhbh (d->target, t3, t2));
18271 emit_insn (gen_loongson_punpcklbh (d->target, t3, t2));
18275 gcc_unreachable ();
18280 /* Recognize patterns for the Loongson PSHUFH instruction. */
18283 mips_expand_vpc_loongson_pshufh (struct expand_vec_perm_d *d)
18288 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
18290 if (d->vmode != V4HImode)
18295 /* Convert the selector into the packed 8-bit form for pshufh. */
18296 /* Recall that loongson is little-endian only. No big-endian
18297 adjustment required. */
18298 for (i = mask = 0; i < 4; i++)
18299 mask |= (d->perm[i] & 3) << (i * 2);
18300 rmask = force_reg (SImode, GEN_INT (mask));
18302 if (d->one_vector_p)
18303 emit_insn (gen_loongson_pshufh (d->target, d->op0, rmask));
18306 rtx t0, t1, x, merge, rmerge[4];
18308 t0 = gen_reg_rtx (V4HImode);
18309 t1 = gen_reg_rtx (V4HImode);
18310 emit_insn (gen_loongson_pshufh (t1, d->op1, rmask));
18311 emit_insn (gen_loongson_pshufh (t0, d->op0, rmask));
18313 for (i = 0; i < 4; ++i)
18314 rmerge[i] = (d->perm[i] & 4 ? constm1_rtx : const0_rtx);
18315 merge = gen_rtx_CONST_VECTOR (V4HImode, gen_rtvec_v (4, rmerge));
18316 merge = force_reg (V4HImode, merge);
18318 x = gen_rtx_AND (V4HImode, merge, t1);
18319 emit_insn (gen_rtx_SET (VOIDmode, t1, x));
18321 x = gen_rtx_NOT (V4HImode, merge);
18322 x = gen_rtx_AND (V4HImode, x, t0);
18323 emit_insn (gen_rtx_SET (VOIDmode, t0, x));
18325 x = gen_rtx_IOR (V4HImode, t0, t1);
18326 emit_insn (gen_rtx_SET (VOIDmode, d->target, x));
18332 /* Recognize broadcast patterns for the Loongson. */
18335 mips_expand_vpc_loongson_bcast (struct expand_vec_perm_d *d)
18340 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
18342 /* Note that we've already matched V2SI via punpck and V4HI via pshufh. */
18343 if (d->vmode != V8QImode)
18345 if (!d->one_vector_p)
18349 for (i = 1; i < 8; ++i)
18350 if (d->perm[i] != elt)
18356 /* With one interleave we put two of the desired element adjacent. */
18357 t0 = gen_reg_rtx (V8QImode);
18359 emit_insn (gen_loongson_punpcklbh (t0, d->op0, d->op0));
18361 emit_insn (gen_loongson_punpckhbh (t0, d->op0, d->op0));
18363 /* Shuffle that one HImode element into all locations. */
18366 t1 = gen_reg_rtx (V4HImode);
18367 emit_insn (gen_loongson_pshufh (t1, gen_lowpart (V4HImode, t0),
18368 force_reg (SImode, GEN_INT (elt))));
18370 emit_move_insn (d->target, gen_lowpart (V8QImode, t1));
18375 mips_expand_vec_perm_const_1 (struct expand_vec_perm_d *d)
18377 unsigned int i, nelt = d->nelt;
18378 unsigned char perm2[MAX_VECT_LEN];
18380 if (d->one_vector_p)
18382 /* Try interleave with alternating operands. */
18383 memcpy (perm2, d->perm, sizeof(perm2));
18384 for (i = 1; i < nelt; i += 2)
18386 if (mips_expand_vselect_vconcat (d->target, d->op0, d->op1, perm2, nelt))
18391 if (mips_expand_vselect_vconcat (d->target, d->op0, d->op1,
18395 /* Try again with swapped operands. */
18396 for (i = 0; i < nelt; ++i)
18397 perm2[i] = (d->perm[i] + nelt) & (2 * nelt - 1);
18398 if (mips_expand_vselect_vconcat (d->target, d->op1, d->op0, perm2, nelt))
18402 if (mips_expand_vpc_loongson_even_odd (d))
18404 if (mips_expand_vpc_loongson_pshufh (d))
18406 if (mips_expand_vpc_loongson_bcast (d))
18411 /* Expand a vec_perm_const pattern. */
18414 mips_expand_vec_perm_const (rtx operands[4])
18416 struct expand_vec_perm_d d;
18417 int i, nelt, which;
18418 unsigned char orig_perm[MAX_VECT_LEN];
18422 d.target = operands[0];
18423 d.op0 = operands[1];
18424 d.op1 = operands[2];
18427 d.vmode = GET_MODE (d.target);
18428 gcc_assert (VECTOR_MODE_P (d.vmode));
18429 d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
18430 d.testing_p = false;
18432 for (i = which = 0; i < nelt; ++i)
18434 rtx e = XVECEXP (sel, 0, i);
18435 int ei = INTVAL (e) & (2 * nelt - 1);
18436 which |= (ei < nelt ? 1 : 2);
18439 memcpy (d.perm, orig_perm, MAX_VECT_LEN);
18447 d.one_vector_p = false;
18448 if (!rtx_equal_p (d.op0, d.op1))
18453 for (i = 0; i < nelt; ++i)
18454 d.perm[i] &= nelt - 1;
18456 d.one_vector_p = true;
18461 d.one_vector_p = true;
18465 ok = mips_expand_vec_perm_const_1 (&d);
18467 /* If we were given a two-vector permutation which just happened to
18468 have both input vectors equal, we folded this into a one-vector
18469 permutation. There are several loongson patterns that are matched
18470 via direct vec_select+vec_concat expansion, but we do not have
18471 support in mips_expand_vec_perm_const_1 to guess the adjustment
18472 that should be made for a single operand. Just try again with
18473 the original permutation. */
18474 if (!ok && which == 3)
18476 d.op0 = operands[1];
18477 d.op1 = operands[2];
18478 d.one_vector_p = false;
18479 memcpy (d.perm, orig_perm, MAX_VECT_LEN);
18480 ok = mips_expand_vec_perm_const_1 (&d);
18486 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST_OK. */
18489 mips_vectorize_vec_perm_const_ok (enum machine_mode vmode,
18490 const unsigned char *sel)
18492 struct expand_vec_perm_d d;
18493 unsigned int i, nelt, which;
18497 d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
18498 d.testing_p = true;
18499 memcpy (d.perm, sel, nelt);
18501 /* Categorize the set of elements in the selector. */
18502 for (i = which = 0; i < nelt; ++i)
18504 unsigned char e = d.perm[i];
18505 gcc_assert (e < 2 * nelt);
18506 which |= (e < nelt ? 1 : 2);
18509 /* For all elements from second vector, fold the elements to first. */
18511 for (i = 0; i < nelt; ++i)
18514 /* Check whether the mask can be applied to the vector type. */
18515 d.one_vector_p = (which != 3);
18517 d.target = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 1);
18518 d.op1 = d.op0 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 2);
18519 if (!d.one_vector_p)
18520 d.op1 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 3);
18523 ret = mips_expand_vec_perm_const_1 (&d);
18529 /* Expand an integral vector unpack operation. */
18532 mips_expand_vec_unpack (rtx operands[2], bool unsigned_p, bool high_p)
18534 enum machine_mode imode = GET_MODE (operands[1]);
18535 rtx (*unpack) (rtx, rtx, rtx);
18536 rtx (*cmpgt) (rtx, rtx, rtx);
18537 rtx tmp, dest, zero;
18543 unpack = gen_loongson_punpckhbh;
18545 unpack = gen_loongson_punpcklbh;
18546 cmpgt = gen_loongson_pcmpgtb;
18550 unpack = gen_loongson_punpckhhw;
18552 unpack = gen_loongson_punpcklhw;
18553 cmpgt = gen_loongson_pcmpgth;
18556 gcc_unreachable ();
18559 zero = force_reg (imode, CONST0_RTX (imode));
18564 tmp = gen_reg_rtx (imode);
18565 emit_insn (cmpgt (tmp, zero, operands[1]));
18568 dest = gen_reg_rtx (imode);
18569 emit_insn (unpack (dest, operands[1], tmp));
18571 emit_move_insn (operands[0], gen_lowpart (GET_MODE (operands[0]), dest));
18574 /* A subroutine of mips_expand_vec_init, match constant vector elements. */
18577 mips_constant_elt_p (rtx x)
18579 return CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE;
18582 /* A subroutine of mips_expand_vec_init, expand via broadcast. */
18585 mips_expand_vi_broadcast (enum machine_mode vmode, rtx target, rtx elt)
18587 struct expand_vec_perm_d d;
18591 if (elt != const0_rtx)
18592 elt = force_reg (GET_MODE_INNER (vmode), elt);
18594 elt = gen_lowpart (DImode, elt);
18596 t1 = gen_reg_rtx (vmode);
18600 emit_insn (gen_loongson_vec_init1_v8qi (t1, elt));
18603 emit_insn (gen_loongson_vec_init1_v4hi (t1, elt));
18606 gcc_unreachable ();
18609 memset (&d, 0, sizeof (d));
18614 d.nelt = GET_MODE_NUNITS (vmode);
18615 d.one_vector_p = true;
18617 ok = mips_expand_vec_perm_const_1 (&d);
18621 /* A subroutine of mips_expand_vec_init, replacing all of the non-constant
18622 elements of VALS with zeros, copy the constant vector to TARGET. */
18625 mips_expand_vi_constant (enum machine_mode vmode, unsigned nelt,
18626 rtx target, rtx vals)
18628 rtvec vec = shallow_copy_rtvec (XVEC (vals, 0));
18631 for (i = 0; i < nelt; ++i)
18633 if (!mips_constant_elt_p (RTVEC_ELT (vec, i)))
18634 RTVEC_ELT (vec, i) = const0_rtx;
18637 emit_move_insn (target, gen_rtx_CONST_VECTOR (vmode, vec));
18641 /* A subroutine of mips_expand_vec_init, expand via pinsrh. */
18644 mips_expand_vi_loongson_one_pinsrh (rtx target, rtx vals, unsigned one_var)
18646 mips_expand_vi_constant (V4HImode, 4, target, vals);
18648 emit_insn (gen_vec_setv4hi (target, target, XVECEXP (vals, 0, one_var),
18649 GEN_INT (one_var)));
18652 /* A subroutine of mips_expand_vec_init, expand anything via memory. */
18655 mips_expand_vi_general (enum machine_mode vmode, enum machine_mode imode,
18656 unsigned nelt, unsigned nvar, rtx target, rtx vals)
18658 rtx mem = assign_stack_temp (vmode, GET_MODE_SIZE (vmode));
18659 unsigned int i, isize = GET_MODE_SIZE (imode);
18662 mips_expand_vi_constant (vmode, nelt, mem, vals);
18664 for (i = 0; i < nelt; ++i)
18666 rtx x = XVECEXP (vals, 0, i);
18667 if (!mips_constant_elt_p (x))
18668 emit_move_insn (adjust_address (mem, imode, i * isize), x);
18671 emit_move_insn (target, mem);
18674 /* Expand a vector initialization. */
18677 mips_expand_vector_init (rtx target, rtx vals)
18679 enum machine_mode vmode = GET_MODE (target);
18680 enum machine_mode imode = GET_MODE_INNER (vmode);
18681 unsigned i, nelt = GET_MODE_NUNITS (vmode);
18682 unsigned nvar = 0, one_var = -1u;
18683 bool all_same = true;
18686 for (i = 0; i < nelt; ++i)
18688 x = XVECEXP (vals, 0, i);
18689 if (!mips_constant_elt_p (x))
18690 nvar++, one_var = i;
18691 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
18695 /* Load constants from the pool, or whatever's handy. */
18698 emit_move_insn (target, gen_rtx_CONST_VECTOR (vmode, XVEC (vals, 0)));
18702 /* For two-part initialization, always use CONCAT. */
18705 rtx op0 = force_reg (imode, XVECEXP (vals, 0, 0));
18706 rtx op1 = force_reg (imode, XVECEXP (vals, 0, 1));
18707 x = gen_rtx_VEC_CONCAT (vmode, op0, op1);
18708 emit_insn (gen_rtx_SET (VOIDmode, target, x));
18712 /* Loongson is the only cpu with vectors with more elements. */
18713 gcc_assert (TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS);
18715 /* If all values are identical, broadcast the value. */
18718 mips_expand_vi_broadcast (vmode, target, XVECEXP (vals, 0, 0));
18722 /* If we've only got one non-variable V4HImode, use PINSRH. */
18723 if (nvar == 1 && vmode == V4HImode)
18725 mips_expand_vi_loongson_one_pinsrh (target, vals, one_var);
18729 mips_expand_vi_general (vmode, imode, nelt, nvar, target, vals);
18732 /* Expand a vector reduction. */
18735 mips_expand_vec_reduc (rtx target, rtx in, rtx (*gen)(rtx, rtx, rtx))
18737 enum machine_mode vmode = GET_MODE (in);
18738 unsigned char perm2[2];
18739 rtx last, next, fold, x;
18743 fold = gen_reg_rtx (vmode);
18747 /* Use PUL/PLU to produce { L, H } op { H, L }.
18748 By reversing the pair order, rather than a pure interleave high,
18749 we avoid erroneous exceptional conditions that we might otherwise
18750 produce from the computation of H op H. */
18753 ok = mips_expand_vselect_vconcat (fold, last, last, perm2, 2);
18758 /* Use interleave to produce { H, L } op { H, H }. */
18759 emit_insn (gen_loongson_punpckhwd (fold, last, last));
18763 /* Perform the first reduction with interleave,
18764 and subsequent reductions with shifts. */
18765 emit_insn (gen_loongson_punpckhwd_hi (fold, last, last));
18767 next = gen_reg_rtx (vmode);
18768 emit_insn (gen (next, last, fold));
18771 fold = gen_reg_rtx (vmode);
18772 x = force_reg (SImode, GEN_INT (16));
18773 emit_insn (gen_vec_shr_v4hi (fold, last, x));
18777 emit_insn (gen_loongson_punpckhwd_qi (fold, last, last));
18779 next = gen_reg_rtx (vmode);
18780 emit_insn (gen (next, last, fold));
18783 fold = gen_reg_rtx (vmode);
18784 x = force_reg (SImode, GEN_INT (16));
18785 emit_insn (gen_vec_shr_v8qi (fold, last, x));
18787 next = gen_reg_rtx (vmode);
18788 emit_insn (gen (next, last, fold));
18791 fold = gen_reg_rtx (vmode);
18792 x = force_reg (SImode, GEN_INT (8));
18793 emit_insn (gen_vec_shr_v8qi (fold, last, x));
18797 gcc_unreachable ();
18800 emit_insn (gen (target, last, fold));
18803 /* Expand a vector minimum/maximum. */
18806 mips_expand_vec_minmax (rtx target, rtx op0, rtx op1,
18807 rtx (*cmp) (rtx, rtx, rtx), bool min_p)
18809 enum machine_mode vmode = GET_MODE (target);
18812 tc = gen_reg_rtx (vmode);
18813 t0 = gen_reg_rtx (vmode);
18814 t1 = gen_reg_rtx (vmode);
18817 emit_insn (cmp (tc, op0, op1));
18819 x = gen_rtx_AND (vmode, tc, (min_p ? op1 : op0));
18820 emit_insn (gen_rtx_SET (VOIDmode, t0, x));
18822 x = gen_rtx_NOT (vmode, tc);
18823 x = gen_rtx_AND (vmode, x, (min_p ? op0 : op1));
18824 emit_insn (gen_rtx_SET (VOIDmode, t1, x));
18826 x = gen_rtx_IOR (vmode, t0, t1);
18827 emit_insn (gen_rtx_SET (VOIDmode, target, x));
18830 /* Implement TARGET_CASE_VALUES_THRESHOLD. */
18833 mips_case_values_threshold (void)
18835 /* In MIPS16 mode using a larger case threshold generates smaller code. */
18836 if (TARGET_MIPS16 && optimize_size)
18839 return default_case_values_threshold ();
18842 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
18845 mips_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
18847 if (!TARGET_HARD_FLOAT_ABI)
18849 tree exceptions_var = create_tmp_var (MIPS_ATYPE_USI, NULL);
18850 tree fcsr_orig_var = create_tmp_var (MIPS_ATYPE_USI, NULL);
18851 tree fcsr_mod_var = create_tmp_var (MIPS_ATYPE_USI, NULL);
18852 tree get_fcsr = mips_builtin_decls[MIPS_GET_FCSR];
18853 tree set_fcsr = mips_builtin_decls[MIPS_SET_FCSR];
18854 tree get_fcsr_hold_call = build_call_expr (get_fcsr, 0);
18855 tree hold_assign_orig = build2 (MODIFY_EXPR, MIPS_ATYPE_USI,
18856 fcsr_orig_var, get_fcsr_hold_call);
18857 tree hold_mod_val = build2 (BIT_AND_EXPR, MIPS_ATYPE_USI, fcsr_orig_var,
18858 build_int_cst (MIPS_ATYPE_USI, 0xfffff003));
18859 tree hold_assign_mod = build2 (MODIFY_EXPR, MIPS_ATYPE_USI,
18860 fcsr_mod_var, hold_mod_val);
18861 tree set_fcsr_hold_call = build_call_expr (set_fcsr, 1, fcsr_mod_var);
18862 tree hold_all = build2 (COMPOUND_EXPR, MIPS_ATYPE_USI,
18863 hold_assign_orig, hold_assign_mod);
18864 *hold = build2 (COMPOUND_EXPR, void_type_node, hold_all,
18865 set_fcsr_hold_call);
18867 *clear = build_call_expr (set_fcsr, 1, fcsr_mod_var);
18869 tree get_fcsr_update_call = build_call_expr (get_fcsr, 0);
18870 *update = build2 (MODIFY_EXPR, MIPS_ATYPE_USI,
18871 exceptions_var, get_fcsr_update_call);
18872 tree set_fcsr_update_call = build_call_expr (set_fcsr, 1, fcsr_orig_var);
18873 *update = build2 (COMPOUND_EXPR, void_type_node, *update,
18874 set_fcsr_update_call);
18875 tree atomic_feraiseexcept
18876 = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT);
18877 tree int_exceptions_var = fold_convert (integer_type_node,
18879 tree atomic_feraiseexcept_call = build_call_expr (atomic_feraiseexcept,
18880 1, int_exceptions_var);
18881 *update = build2 (COMPOUND_EXPR, void_type_node, *update,
18882 atomic_feraiseexcept_call);
18885 /* Implement TARGET_SPILL_CLASS. */
18888 mips_spill_class (reg_class_t rclass ATTRIBUTE_UNUSED,
18889 enum machine_mode mode ATTRIBUTE_UNUSED)
18896 /* Implement TARGET_LRA_P. */
18901 return mips_lra_flag;
18904 /* Initialize the GCC target structure. */
18905 #undef TARGET_ASM_ALIGNED_HI_OP
18906 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
18907 #undef TARGET_ASM_ALIGNED_SI_OP
18908 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
18909 #undef TARGET_ASM_ALIGNED_DI_OP
18910 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
18912 #undef TARGET_OPTION_OVERRIDE
18913 #define TARGET_OPTION_OVERRIDE mips_option_override
18915 #undef TARGET_LEGITIMIZE_ADDRESS
18916 #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
18918 #undef TARGET_ASM_FUNCTION_PROLOGUE
18919 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
18920 #undef TARGET_ASM_FUNCTION_EPILOGUE
18921 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
18922 #undef TARGET_ASM_SELECT_RTX_SECTION
18923 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
18924 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
18925 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
18927 #undef TARGET_SCHED_INIT
18928 #define TARGET_SCHED_INIT mips_sched_init
18929 #undef TARGET_SCHED_REORDER
18930 #define TARGET_SCHED_REORDER mips_sched_reorder
18931 #undef TARGET_SCHED_REORDER2
18932 #define TARGET_SCHED_REORDER2 mips_sched_reorder2
18933 #undef TARGET_SCHED_VARIABLE_ISSUE
18934 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
18935 #undef TARGET_SCHED_ADJUST_COST
18936 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
18937 #undef TARGET_SCHED_ISSUE_RATE
18938 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
18939 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
18940 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
18941 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
18942 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
18943 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
18944 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
18945 mips_multipass_dfa_lookahead
18946 #undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
18947 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
18948 mips_small_register_classes_for_mode_p
18950 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
18951 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
18953 #undef TARGET_INSERT_ATTRIBUTES
18954 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
18955 #undef TARGET_MERGE_DECL_ATTRIBUTES
18956 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
18957 #undef TARGET_CAN_INLINE_P
18958 #define TARGET_CAN_INLINE_P mips_can_inline_p
18959 #undef TARGET_SET_CURRENT_FUNCTION
18960 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
18962 #undef TARGET_VALID_POINTER_MODE
18963 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
18964 #undef TARGET_REGISTER_MOVE_COST
18965 #define TARGET_REGISTER_MOVE_COST mips_register_move_cost
18966 #undef TARGET_REGISTER_PRIORITY
18967 #define TARGET_REGISTER_PRIORITY mips_register_priority
18968 #undef TARGET_MEMORY_MOVE_COST
18969 #define TARGET_MEMORY_MOVE_COST mips_memory_move_cost
18970 #undef TARGET_RTX_COSTS
18971 #define TARGET_RTX_COSTS mips_rtx_costs
18972 #undef TARGET_ADDRESS_COST
18973 #define TARGET_ADDRESS_COST mips_address_cost
18975 #undef TARGET_IN_SMALL_DATA_P
18976 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
18978 #undef TARGET_MACHINE_DEPENDENT_REORG
18979 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
18981 #undef TARGET_PREFERRED_RELOAD_CLASS
18982 #define TARGET_PREFERRED_RELOAD_CLASS mips_preferred_reload_class
18984 #undef TARGET_EXPAND_TO_RTL_HOOK
18985 #define TARGET_EXPAND_TO_RTL_HOOK mips_expand_to_rtl_hook
18986 #undef TARGET_ASM_FILE_START
18987 #define TARGET_ASM_FILE_START mips_file_start
18988 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
18989 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
18990 #undef TARGET_ASM_CODE_END
18991 #define TARGET_ASM_CODE_END mips_code_end
18993 #undef TARGET_INIT_LIBFUNCS
18994 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
18996 #undef TARGET_BUILD_BUILTIN_VA_LIST
18997 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
18998 #undef TARGET_EXPAND_BUILTIN_VA_START
18999 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
19000 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
19001 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
19003 #undef TARGET_PROMOTE_FUNCTION_MODE
19004 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
19005 #undef TARGET_PROMOTE_PROTOTYPES
19006 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
19008 #undef TARGET_FUNCTION_VALUE
19009 #define TARGET_FUNCTION_VALUE mips_function_value
19010 #undef TARGET_LIBCALL_VALUE
19011 #define TARGET_LIBCALL_VALUE mips_libcall_value
19012 #undef TARGET_FUNCTION_VALUE_REGNO_P
19013 #define TARGET_FUNCTION_VALUE_REGNO_P mips_function_value_regno_p
19014 #undef TARGET_RETURN_IN_MEMORY
19015 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
19016 #undef TARGET_RETURN_IN_MSB
19017 #define TARGET_RETURN_IN_MSB mips_return_in_msb
19019 #undef TARGET_ASM_OUTPUT_MI_THUNK
19020 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
19021 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
19022 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
19024 #undef TARGET_PRINT_OPERAND
19025 #define TARGET_PRINT_OPERAND mips_print_operand
19026 #undef TARGET_PRINT_OPERAND_ADDRESS
19027 #define TARGET_PRINT_OPERAND_ADDRESS mips_print_operand_address
19028 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
19029 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mips_print_operand_punct_valid_p
19031 #undef TARGET_SETUP_INCOMING_VARARGS
19032 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
19033 #undef TARGET_STRICT_ARGUMENT_NAMING
19034 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
19035 #undef TARGET_MUST_PASS_IN_STACK
19036 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
19037 #undef TARGET_PASS_BY_REFERENCE
19038 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
19039 #undef TARGET_CALLEE_COPIES
19040 #define TARGET_CALLEE_COPIES mips_callee_copies
19041 #undef TARGET_ARG_PARTIAL_BYTES
19042 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
19043 #undef TARGET_FUNCTION_ARG
19044 #define TARGET_FUNCTION_ARG mips_function_arg
19045 #undef TARGET_FUNCTION_ARG_ADVANCE
19046 #define TARGET_FUNCTION_ARG_ADVANCE mips_function_arg_advance
19047 #undef TARGET_FUNCTION_ARG_BOUNDARY
19048 #define TARGET_FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
19050 #undef TARGET_MODE_REP_EXTENDED
19051 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
19053 #undef TARGET_VECTOR_MODE_SUPPORTED_P
19054 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
19056 #undef TARGET_SCALAR_MODE_SUPPORTED_P
19057 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
19059 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
19060 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE mips_preferred_simd_mode
19062 #undef TARGET_INIT_BUILTINS
19063 #define TARGET_INIT_BUILTINS mips_init_builtins
19064 #undef TARGET_BUILTIN_DECL
19065 #define TARGET_BUILTIN_DECL mips_builtin_decl
19066 #undef TARGET_EXPAND_BUILTIN
19067 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
19069 #undef TARGET_HAVE_TLS
19070 #define TARGET_HAVE_TLS HAVE_AS_TLS
19072 #undef TARGET_CANNOT_FORCE_CONST_MEM
19073 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
19075 #undef TARGET_LEGITIMATE_CONSTANT_P
19076 #define TARGET_LEGITIMATE_CONSTANT_P mips_legitimate_constant_p
19078 #undef TARGET_ENCODE_SECTION_INFO
19079 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
19081 #undef TARGET_ATTRIBUTE_TABLE
19082 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
19083 /* All our function attributes are related to how out-of-line copies should
19084 be compiled or called. They don't in themselves prevent inlining. */
19085 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
19086 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
19088 #undef TARGET_EXTRA_LIVE_ON_ENTRY
19089 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
19091 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
19092 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
19093 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
19094 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
19096 #undef TARGET_COMP_TYPE_ATTRIBUTES
19097 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
19099 #ifdef HAVE_AS_DTPRELWORD
19100 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
19101 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
19103 #undef TARGET_DWARF_REGISTER_SPAN
19104 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
19106 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
19107 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
19109 #undef TARGET_LEGITIMATE_ADDRESS_P
19110 #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p
19112 #undef TARGET_FRAME_POINTER_REQUIRED
19113 #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required
19115 #undef TARGET_CAN_ELIMINATE
19116 #define TARGET_CAN_ELIMINATE mips_can_eliminate
19118 #undef TARGET_CONDITIONAL_REGISTER_USAGE
19119 #define TARGET_CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage
19121 #undef TARGET_TRAMPOLINE_INIT
19122 #define TARGET_TRAMPOLINE_INIT mips_trampoline_init
19124 #undef TARGET_ASM_OUTPUT_SOURCE_FILENAME
19125 #define TARGET_ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
19127 #undef TARGET_SHIFT_TRUNCATION_MASK
19128 #define TARGET_SHIFT_TRUNCATION_MASK mips_shift_truncation_mask
19130 #undef TARGET_PREPARE_PCH_SAVE
19131 #define TARGET_PREPARE_PCH_SAVE mips_prepare_pch_save
19133 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
19134 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK mips_vectorize_vec_perm_const_ok
19136 #undef TARGET_CASE_VALUES_THRESHOLD
19137 #define TARGET_CASE_VALUES_THRESHOLD mips_case_values_threshold
19139 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
19140 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV mips_atomic_assign_expand_fenv
19142 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
19143 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
19145 #undef TARGET_SPILL_CLASS
19146 #define TARGET_SPILL_CLASS mips_spill_class
19147 #undef TARGET_LRA_P
19148 #define TARGET_LRA_P mips_lra_p
19150 struct gcc_target targetm = TARGET_INITIALIZER;
19152 #include "gt-mips.h"