1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky, lich@inria.inria.fr.
6 Changes by Michael Meissner, meissner@osf.org.
7 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
8 Brendan Eich, brendan@microunity.com.
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
28 #include "coretypes.h"
32 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
35 #include "insn-attr.h"
51 #include "target-def.h"
52 #include "integrate.h"
53 #include "langhooks.h"
54 #include "cfglayout.h"
55 #include "sched-int.h"
58 #include "diagnostic.h"
59 #include "target-globals.h"
61 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
62 #define UNSPEC_ADDRESS_P(X) \
63 (GET_CODE (X) == UNSPEC \
64 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
65 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
67 /* Extract the symbol or label from UNSPEC wrapper X. */
68 #define UNSPEC_ADDRESS(X) \
71 /* Extract the symbol type from UNSPEC wrapper X. */
72 #define UNSPEC_ADDRESS_TYPE(X) \
73 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
75 /* The maximum distance between the top of the stack frame and the
76 value $sp has when we save and restore registers.
78 The value for normal-mode code must be a SMALL_OPERAND and must
79 preserve the maximum stack alignment. We therefore use a value
80 of 0x7ff0 in this case.
82 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
83 up to 0x7f8 bytes and can usually save or restore all the registers
84 that we need to save or restore. (Note that we can only use these
85 instructions for o32, for which the stack alignment is 8 bytes.)
87 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
88 RESTORE are not available. We can then use unextended instructions
89 to save and restore registers, and to allocate and deallocate the top
91 #define MIPS_MAX_FIRST_STACK_STEP \
92 (!TARGET_MIPS16 ? 0x7ff0 \
93 : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
94 : TARGET_64BIT ? 0x100 : 0x400)
96 /* True if INSN is a mips.md pattern or asm statement. */
97 #define USEFUL_INSN_P(INSN) \
98 (NONDEBUG_INSN_P (INSN) \
99 && GET_CODE (PATTERN (INSN)) != USE \
100 && GET_CODE (PATTERN (INSN)) != CLOBBER \
101 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
102 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
104 /* If INSN is a delayed branch sequence, return the first instruction
105 in the sequence, otherwise return INSN itself. */
106 #define SEQ_BEGIN(INSN) \
107 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
108 ? XVECEXP (PATTERN (INSN), 0, 0) \
111 /* Likewise for the last instruction in a delayed branch sequence. */
112 #define SEQ_END(INSN) \
113 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
114 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
117 /* Execute the following loop body with SUBINSN set to each instruction
118 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
119 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
120 for ((SUBINSN) = SEQ_BEGIN (INSN); \
121 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
122 (SUBINSN) = NEXT_INSN (SUBINSN))
124 /* True if bit BIT is set in VALUE. */
125 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
127 /* Return the opcode for a ptr_mode load of the form:
129 l[wd] DEST, OFFSET(BASE). */
130 #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \
131 (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \
136 /* Return the opcode to move register SRC into register DEST. */
137 #define MIPS_MOVE(DEST, SRC) \
138 ((TARGET_64BIT ? 0x2d : 0x21) \
142 /* Return the opcode for:
145 #define MIPS_LUI(DEST, VALUE) \
146 ((0xf << 26) | ((DEST) << 16) | (VALUE))
148 /* Return the opcode to jump to register DEST. */
149 #define MIPS_JR(DEST) \
150 (((DEST) << 21) | 0x8)
152 /* Return the opcode for:
154 bal . + (1 + OFFSET) * 4. */
155 #define MIPS_BAL(OFFSET) \
156 ((0x1 << 26) | (0x11 << 16) | (OFFSET))
158 /* Return the usual opcode for a nop. */
161 /* Classifies an address.
164 A natural register + offset address. The register satisfies
165 mips_valid_base_register_p and the offset is a const_arith_operand.
168 A LO_SUM rtx. The first operand is a valid base register and
169 the second operand is a symbolic address.
172 A signed 16-bit constant address.
175 A constant symbolic address. */
176 enum mips_address_type {
183 /* Enumerates the setting of the -mr10k-cache-barrier option. */
184 enum mips_r10k_cache_barrier_setting {
185 R10K_CACHE_BARRIER_NONE,
186 R10K_CACHE_BARRIER_STORE,
187 R10K_CACHE_BARRIER_LOAD_STORE
190 /* Macros to create an enumeration identifier for a function prototype. */
191 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
192 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
193 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
194 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
196 /* Classifies the prototype of a built-in function. */
197 enum mips_function_type {
198 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
199 #include "config/mips/mips-ftypes.def"
200 #undef DEF_MIPS_FTYPE
204 /* Specifies how a built-in function should be converted into rtl. */
205 enum mips_builtin_type {
206 /* The function corresponds directly to an .md pattern. The return
207 value is mapped to operand 0 and the arguments are mapped to
208 operands 1 and above. */
211 /* The function corresponds directly to an .md pattern. There is no return
212 value and the arguments are mapped to operands 0 and above. */
213 MIPS_BUILTIN_DIRECT_NO_TARGET,
215 /* The function corresponds to a comparison instruction followed by
216 a mips_cond_move_tf_ps pattern. The first two arguments are the
217 values to compare and the second two arguments are the vector
218 operands for the movt.ps or movf.ps instruction (in assembly order). */
222 /* The function corresponds to a V2SF comparison instruction. Operand 0
223 of this instruction is the result of the comparison, which has mode
224 CCV2 or CCV4. The function arguments are mapped to operands 1 and
225 above. The function's return value is an SImode boolean that is
226 true under the following conditions:
228 MIPS_BUILTIN_CMP_ANY: one of the registers is true
229 MIPS_BUILTIN_CMP_ALL: all of the registers are true
230 MIPS_BUILTIN_CMP_LOWER: the first register is true
231 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
232 MIPS_BUILTIN_CMP_ANY,
233 MIPS_BUILTIN_CMP_ALL,
234 MIPS_BUILTIN_CMP_UPPER,
235 MIPS_BUILTIN_CMP_LOWER,
237 /* As above, but the instruction only sets a single $fcc register. */
238 MIPS_BUILTIN_CMP_SINGLE,
240 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
241 MIPS_BUILTIN_BPOSGE32
244 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
245 #define MIPS_FP_CONDITIONS(MACRO) \
263 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
264 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
265 enum mips_fp_condition {
266 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
269 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
270 #define STRINGIFY(X) #X
271 static const char *const mips_fp_conditions[] = {
272 MIPS_FP_CONDITIONS (STRINGIFY)
275 /* Information about a function's frame layout. */
276 struct GTY(()) mips_frame_info {
277 /* The size of the frame in bytes. */
278 HOST_WIDE_INT total_size;
280 /* The number of bytes allocated to variables. */
281 HOST_WIDE_INT var_size;
283 /* The number of bytes allocated to outgoing function arguments. */
284 HOST_WIDE_INT args_size;
286 /* The number of bytes allocated to the .cprestore slot, or 0 if there
288 HOST_WIDE_INT cprestore_size;
290 /* Bit X is set if the function saves or restores GPR X. */
293 /* Likewise FPR X. */
296 /* Likewise doubleword accumulator X ($acX). */
297 unsigned int acc_mask;
299 /* The number of GPRs, FPRs, doubleword accumulators and COP0
303 unsigned int num_acc;
304 unsigned int num_cop0_regs;
306 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
307 save slots from the top of the frame, or zero if no such slots are
309 HOST_WIDE_INT gp_save_offset;
310 HOST_WIDE_INT fp_save_offset;
311 HOST_WIDE_INT acc_save_offset;
312 HOST_WIDE_INT cop0_save_offset;
314 /* Likewise, but giving offsets from the bottom of the frame. */
315 HOST_WIDE_INT gp_sp_offset;
316 HOST_WIDE_INT fp_sp_offset;
317 HOST_WIDE_INT acc_sp_offset;
318 HOST_WIDE_INT cop0_sp_offset;
320 /* Similar, but the value passed to _mcount. */
321 HOST_WIDE_INT ra_fp_offset;
323 /* The offset of arg_pointer_rtx from the bottom of the frame. */
324 HOST_WIDE_INT arg_pointer_offset;
326 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
327 HOST_WIDE_INT hard_frame_pointer_offset;
330 struct GTY(()) machine_function {
331 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
332 rtx mips16_gp_pseudo_rtx;
334 /* The number of extra stack bytes taken up by register varargs.
335 This area is allocated by the callee at the very top of the frame. */
338 /* The current frame information, calculated by mips_compute_frame_info. */
339 struct mips_frame_info frame;
341 /* The register to use as the function's global pointer, or INVALID_REGNUM
342 if the function doesn't need one. */
343 unsigned int global_pointer;
345 /* How many instructions it takes to load a label into $AT, or 0 if
346 this property hasn't yet been calculated. */
347 unsigned int load_label_num_insns;
349 /* True if mips_adjust_insn_length should ignore an instruction's
351 bool ignore_hazard_length_p;
353 /* True if the whole function is suitable for .set noreorder and
355 bool all_noreorder_p;
357 /* True if the function has "inflexible" and "flexible" references
358 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
359 and mips_cfun_has_flexible_gp_ref_p for details. */
360 bool has_inflexible_gp_insn_p;
361 bool has_flexible_gp_insn_p;
363 /* True if the function's prologue must load the global pointer
364 value into pic_offset_table_rtx and store the same value in
365 the function's cprestore slot (if any). Even if this value
366 is currently false, we may decide to set it to true later;
367 see mips_must_initialize_gp_p () for details. */
368 bool must_initialize_gp_p;
370 /* True if the current function must restore $gp after any potential
371 clobber. This value is only meaningful during the first post-epilogue
372 split_insns pass; see mips_must_initialize_gp_p () for details. */
373 bool must_restore_gp_when_clobbered_p;
375 /* True if this is an interrupt handler. */
376 bool interrupt_handler_p;
378 /* True if this is an interrupt handler that uses shadow registers. */
379 bool use_shadow_register_set_p;
381 /* True if this is an interrupt handler that should keep interrupts
383 bool keep_interrupts_masked_p;
385 /* True if this is an interrupt handler that should use DERET
387 bool use_debug_exception_return_p;
390 /* Information about a single argument. */
391 struct mips_arg_info {
392 /* True if the argument is passed in a floating-point register, or
393 would have been if we hadn't run out of registers. */
396 /* The number of words passed in registers, rounded up. */
397 unsigned int reg_words;
399 /* For EABI, the offset of the first register from GP_ARG_FIRST or
400 FP_ARG_FIRST. For other ABIs, the offset of the first register from
401 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
402 comment for details).
404 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
406 unsigned int reg_offset;
408 /* The number of words that must be passed on the stack, rounded up. */
409 unsigned int stack_words;
411 /* The offset from the start of the stack overflow area of the argument's
412 first stack word. Only meaningful when STACK_WORDS is nonzero. */
413 unsigned int stack_offset;
416 /* Information about an address described by mips_address_type.
422 REG is the base register and OFFSET is the constant offset.
425 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
426 is the type of symbol it references.
429 SYMBOL_TYPE is the type of symbol that the address references. */
430 struct mips_address_info {
431 enum mips_address_type type;
434 enum mips_symbol_type symbol_type;
437 /* One stage in a constant building sequence. These sequences have
441 A = A CODE[1] VALUE[1]
442 A = A CODE[2] VALUE[2]
445 where A is an accumulator, each CODE[i] is a binary rtl operation
446 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
447 struct mips_integer_op {
449 unsigned HOST_WIDE_INT value;
452 /* The largest number of operations needed to load an integer constant.
453 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
454 When the lowest bit is clear, we can try, but reject a sequence with
455 an extra SLL at the end. */
456 #define MIPS_MAX_INTEGER_OPS 7
458 /* Information about a MIPS16e SAVE or RESTORE instruction. */
459 struct mips16e_save_restore_info {
460 /* The number of argument registers saved by a SAVE instruction.
461 0 for RESTORE instructions. */
464 /* Bit X is set if the instruction saves or restores GPR X. */
467 /* The total number of bytes to allocate. */
471 /* Costs of various operations on the different architectures. */
473 struct mips_rtx_cost_data
475 unsigned short fp_add;
476 unsigned short fp_mult_sf;
477 unsigned short fp_mult_df;
478 unsigned short fp_div_sf;
479 unsigned short fp_div_df;
480 unsigned short int_mult_si;
481 unsigned short int_mult_di;
482 unsigned short int_div_si;
483 unsigned short int_div_di;
484 unsigned short branch_cost;
485 unsigned short memory_latency;
488 /* Global variables for machine-dependent things. */
490 /* The -G setting, or the configuration's default small-data limit if
491 no -G option is given. */
492 static unsigned int mips_small_data_threshold;
494 /* The number of file directives written by mips_output_filename. */
495 int num_source_filenames;
497 /* The name that appeared in the last .file directive written by
498 mips_output_filename, or "" if mips_output_filename hasn't
499 written anything yet. */
500 const char *current_function_file = "";
502 /* A label counter used by PUT_SDB_BLOCK_START and PUT_SDB_BLOCK_END. */
505 /* Arrays that map GCC register numbers to debugger register numbers. */
506 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
507 int mips_dwarf_regno[FIRST_PSEUDO_REGISTER];
509 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
510 struct mips_asm_switch mips_noreorder = { "reorder", 0 };
511 struct mips_asm_switch mips_nomacro = { "macro", 0 };
512 struct mips_asm_switch mips_noat = { "at", 0 };
514 /* True if we're writing out a branch-likely instruction rather than a
516 static bool mips_branch_likely;
518 /* The current instruction-set architecture. */
519 enum processor mips_arch;
520 const struct mips_cpu_info *mips_arch_info;
522 /* The processor that we should tune the code for. */
523 enum processor mips_tune;
524 const struct mips_cpu_info *mips_tune_info;
526 /* The ISA level associated with mips_arch. */
529 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
530 static const struct mips_cpu_info *mips_isa_option_info;
532 /* Which ABI to use. */
533 int mips_abi = MIPS_ABI_DEFAULT;
535 /* Which cost information to use. */
536 static const struct mips_rtx_cost_data *mips_cost;
538 /* The ambient target flags, excluding MASK_MIPS16. */
539 static int mips_base_target_flags;
541 /* True if MIPS16 is the default mode. */
542 bool mips_base_mips16;
544 /* The ambient values of other global variables. */
545 static int mips_base_schedule_insns; /* flag_schedule_insns */
546 static int mips_base_reorder_blocks_and_partition; /* flag_reorder... */
547 static int mips_base_move_loop_invariants; /* flag_move_loop_invariants */
548 static int mips_base_align_loops; /* align_loops */
549 static int mips_base_align_jumps; /* align_jumps */
550 static int mips_base_align_functions; /* align_functions */
552 /* The -mcode-readable setting. */
553 enum mips_code_readable_setting mips_code_readable = CODE_READABLE_YES;
555 /* The -mr10k-cache-barrier setting. */
556 static enum mips_r10k_cache_barrier_setting mips_r10k_cache_barrier;
558 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
559 bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
561 /* Index C is true if character C is a valid PRINT_OPERAND punctation
563 static bool mips_print_operand_punct[256];
565 static GTY (()) int mips_output_filename_first_time = 1;
567 /* mips_split_p[X] is true if symbols of type X can be split by
568 mips_split_symbol. */
569 bool mips_split_p[NUM_SYMBOL_TYPES];
571 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
572 can be split by mips_split_symbol. */
573 bool mips_split_hi_p[NUM_SYMBOL_TYPES];
575 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
576 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
577 if they are matched by a special .md file pattern. */
578 static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
580 /* Likewise for HIGHs. */
581 static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
583 /* Target state for MIPS16. */
584 struct target_globals *mips16_globals;
586 /* Cached value of can_issue_more. This is cached in mips_variable_issue hook
587 and returned from mips_sched_reorder2. */
588 static int cached_can_issue_more;
590 /* Index R is the smallest register class that contains register R. */
591 const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = {
592 LEA_REGS, LEA_REGS, M16_REGS, V1_REG,
593 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
594 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
595 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
596 M16_REGS, M16_REGS, LEA_REGS, LEA_REGS,
597 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
598 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
599 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
600 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
601 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
602 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
603 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
604 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
605 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
606 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
607 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
608 MD0_REG, MD1_REG, NO_REGS, ST_REGS,
609 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
610 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
611 NO_REGS, FRAME_REGS, FRAME_REGS, NO_REGS,
612 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
613 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
614 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
615 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
616 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
617 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
618 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
619 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
620 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
621 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
622 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
623 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
624 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
625 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
626 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
627 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
628 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
629 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
630 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
631 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
632 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
633 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
634 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
635 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
636 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
637 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
638 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
641 /* The value of TARGET_ATTRIBUTE_TABLE. */
642 static const struct attribute_spec mips_attribute_table[] = {
643 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
644 { "long_call", 0, 0, false, true, true, NULL },
645 { "far", 0, 0, false, true, true, NULL },
646 { "near", 0, 0, false, true, true, NULL },
647 /* We would really like to treat "mips16" and "nomips16" as type
648 attributes, but GCC doesn't provide the hooks we need to support
649 the right conversion rules. As declaration attributes, they affect
650 code generation but don't carry other semantics. */
651 { "mips16", 0, 0, true, false, false, NULL },
652 { "nomips16", 0, 0, true, false, false, NULL },
653 /* Allow functions to be specified as interrupt handlers */
654 { "interrupt", 0, 0, false, true, true, NULL },
655 { "use_shadow_register_set", 0, 0, false, true, true, NULL },
656 { "keep_interrupts_masked", 0, 0, false, true, true, NULL },
657 { "use_debug_exception_return", 0, 0, false, true, true, NULL },
658 { NULL, 0, 0, false, false, false, NULL }
661 /* A table describing all the processors GCC knows about. Names are
662 matched in the order listed. The first mention of an ISA level is
663 taken as the canonical name for that ISA.
665 To ease comparison, please keep this table in the same order
666 as GAS's mips_cpu_info_table. Please also make sure that
667 MIPS_ISA_LEVEL_SPEC and MIPS_ARCH_FLOAT_SPEC handle all -march
668 options correctly. */
669 static const struct mips_cpu_info mips_cpu_info_table[] = {
670 /* Entries for generic ISAs. */
671 { "mips1", PROCESSOR_R3000, 1, 0 },
672 { "mips2", PROCESSOR_R6000, 2, 0 },
673 { "mips3", PROCESSOR_R4000, 3, 0 },
674 { "mips4", PROCESSOR_R8000, 4, 0 },
675 /* Prefer not to use branch-likely instructions for generic MIPS32rX
676 and MIPS64rX code. The instructions were officially deprecated
677 in revisions 2 and earlier, but revision 3 is likely to downgrade
678 that to a recommendation to avoid the instructions in code that
679 isn't tuned to a specific processor. */
680 { "mips32", PROCESSOR_4KC, 32, PTF_AVOID_BRANCHLIKELY },
681 { "mips32r2", PROCESSOR_M4K, 33, PTF_AVOID_BRANCHLIKELY },
682 { "mips64", PROCESSOR_5KC, 64, PTF_AVOID_BRANCHLIKELY },
683 /* ??? For now just tune the generic MIPS64r2 for 5KC as well. */
684 { "mips64r2", PROCESSOR_5KC, 65, PTF_AVOID_BRANCHLIKELY },
686 /* MIPS I processors. */
687 { "r3000", PROCESSOR_R3000, 1, 0 },
688 { "r2000", PROCESSOR_R3000, 1, 0 },
689 { "r3900", PROCESSOR_R3900, 1, 0 },
691 /* MIPS II processors. */
692 { "r6000", PROCESSOR_R6000, 2, 0 },
694 /* MIPS III processors. */
695 { "r4000", PROCESSOR_R4000, 3, 0 },
696 { "vr4100", PROCESSOR_R4100, 3, 0 },
697 { "vr4111", PROCESSOR_R4111, 3, 0 },
698 { "vr4120", PROCESSOR_R4120, 3, 0 },
699 { "vr4130", PROCESSOR_R4130, 3, 0 },
700 { "vr4300", PROCESSOR_R4300, 3, 0 },
701 { "r4400", PROCESSOR_R4000, 3, 0 },
702 { "r4600", PROCESSOR_R4600, 3, 0 },
703 { "orion", PROCESSOR_R4600, 3, 0 },
704 { "r4650", PROCESSOR_R4650, 3, 0 },
705 /* ST Loongson 2E/2F processors. */
706 { "loongson2e", PROCESSOR_LOONGSON_2E, 3, PTF_AVOID_BRANCHLIKELY },
707 { "loongson2f", PROCESSOR_LOONGSON_2F, 3, PTF_AVOID_BRANCHLIKELY },
709 /* MIPS IV processors. */
710 { "r8000", PROCESSOR_R8000, 4, 0 },
711 { "r10000", PROCESSOR_R10000, 4, 0 },
712 { "r12000", PROCESSOR_R10000, 4, 0 },
713 { "r14000", PROCESSOR_R10000, 4, 0 },
714 { "r16000", PROCESSOR_R10000, 4, 0 },
715 { "vr5000", PROCESSOR_R5000, 4, 0 },
716 { "vr5400", PROCESSOR_R5400, 4, 0 },
717 { "vr5500", PROCESSOR_R5500, 4, PTF_AVOID_BRANCHLIKELY },
718 { "rm7000", PROCESSOR_R7000, 4, 0 },
719 { "rm9000", PROCESSOR_R9000, 4, 0 },
721 /* MIPS32 processors. */
722 { "4kc", PROCESSOR_4KC, 32, 0 },
723 { "4km", PROCESSOR_4KC, 32, 0 },
724 { "4kp", PROCESSOR_4KP, 32, 0 },
725 { "4ksc", PROCESSOR_4KC, 32, 0 },
727 /* MIPS32 Release 2 processors. */
728 { "m4k", PROCESSOR_M4K, 33, 0 },
729 { "4kec", PROCESSOR_4KC, 33, 0 },
730 { "4kem", PROCESSOR_4KC, 33, 0 },
731 { "4kep", PROCESSOR_4KP, 33, 0 },
732 { "4ksd", PROCESSOR_4KC, 33, 0 },
734 { "24kc", PROCESSOR_24KC, 33, 0 },
735 { "24kf2_1", PROCESSOR_24KF2_1, 33, 0 },
736 { "24kf", PROCESSOR_24KF2_1, 33, 0 },
737 { "24kf1_1", PROCESSOR_24KF1_1, 33, 0 },
738 { "24kfx", PROCESSOR_24KF1_1, 33, 0 },
739 { "24kx", PROCESSOR_24KF1_1, 33, 0 },
741 { "24kec", PROCESSOR_24KC, 33, 0 }, /* 24K with DSP. */
742 { "24kef2_1", PROCESSOR_24KF2_1, 33, 0 },
743 { "24kef", PROCESSOR_24KF2_1, 33, 0 },
744 { "24kef1_1", PROCESSOR_24KF1_1, 33, 0 },
745 { "24kefx", PROCESSOR_24KF1_1, 33, 0 },
746 { "24kex", PROCESSOR_24KF1_1, 33, 0 },
748 { "34kc", PROCESSOR_24KC, 33, 0 }, /* 34K with MT/DSP. */
749 { "34kf2_1", PROCESSOR_24KF2_1, 33, 0 },
750 { "34kf", PROCESSOR_24KF2_1, 33, 0 },
751 { "34kf1_1", PROCESSOR_24KF1_1, 33, 0 },
752 { "34kfx", PROCESSOR_24KF1_1, 33, 0 },
753 { "34kx", PROCESSOR_24KF1_1, 33, 0 },
755 { "74kc", PROCESSOR_74KC, 33, 0 }, /* 74K with DSPr2. */
756 { "74kf2_1", PROCESSOR_74KF2_1, 33, 0 },
757 { "74kf", PROCESSOR_74KF2_1, 33, 0 },
758 { "74kf1_1", PROCESSOR_74KF1_1, 33, 0 },
759 { "74kfx", PROCESSOR_74KF1_1, 33, 0 },
760 { "74kx", PROCESSOR_74KF1_1, 33, 0 },
761 { "74kf3_2", PROCESSOR_74KF3_2, 33, 0 },
763 { "1004kc", PROCESSOR_24KC, 33, 0 }, /* 1004K with MT/DSP. */
764 { "1004kf2_1", PROCESSOR_24KF2_1, 33, 0 },
765 { "1004kf", PROCESSOR_24KF2_1, 33, 0 },
766 { "1004kf1_1", PROCESSOR_24KF1_1, 33, 0 },
768 /* MIPS64 processors. */
769 { "5kc", PROCESSOR_5KC, 64, 0 },
770 { "5kf", PROCESSOR_5KF, 64, 0 },
771 { "20kc", PROCESSOR_20KC, 64, PTF_AVOID_BRANCHLIKELY },
772 { "sb1", PROCESSOR_SB1, 64, PTF_AVOID_BRANCHLIKELY },
773 { "sb1a", PROCESSOR_SB1A, 64, PTF_AVOID_BRANCHLIKELY },
774 { "sr71000", PROCESSOR_SR71000, 64, PTF_AVOID_BRANCHLIKELY },
775 { "xlr", PROCESSOR_XLR, 64, 0 },
776 { "loongson3a", PROCESSOR_LOONGSON_3A, 64, PTF_AVOID_BRANCHLIKELY },
778 /* MIPS64 Release 2 processors. */
779 { "octeon", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY }
782 /* Default costs. If these are used for a processor we should look
783 up the actual costs. */
784 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
785 COSTS_N_INSNS (7), /* fp_mult_sf */ \
786 COSTS_N_INSNS (8), /* fp_mult_df */ \
787 COSTS_N_INSNS (23), /* fp_div_sf */ \
788 COSTS_N_INSNS (36), /* fp_div_df */ \
789 COSTS_N_INSNS (10), /* int_mult_si */ \
790 COSTS_N_INSNS (10), /* int_mult_di */ \
791 COSTS_N_INSNS (69), /* int_div_si */ \
792 COSTS_N_INSNS (69), /* int_div_di */ \
793 2, /* branch_cost */ \
794 4 /* memory_latency */
796 /* Floating-point costs for processors without an FPU. Just assume that
797 all floating-point libcalls are very expensive. */
798 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
799 COSTS_N_INSNS (256), /* fp_mult_sf */ \
800 COSTS_N_INSNS (256), /* fp_mult_df */ \
801 COSTS_N_INSNS (256), /* fp_div_sf */ \
802 COSTS_N_INSNS (256) /* fp_div_df */
804 /* Costs to use when optimizing for size. */
805 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size = {
806 COSTS_N_INSNS (1), /* fp_add */
807 COSTS_N_INSNS (1), /* fp_mult_sf */
808 COSTS_N_INSNS (1), /* fp_mult_df */
809 COSTS_N_INSNS (1), /* fp_div_sf */
810 COSTS_N_INSNS (1), /* fp_div_df */
811 COSTS_N_INSNS (1), /* int_mult_si */
812 COSTS_N_INSNS (1), /* int_mult_di */
813 COSTS_N_INSNS (1), /* int_div_si */
814 COSTS_N_INSNS (1), /* int_div_di */
816 4 /* memory_latency */
819 /* Costs to use when optimizing for speed, indexed by processor. */
820 static const struct mips_rtx_cost_data
821 mips_rtx_cost_data[NUM_PROCESSOR_VALUES] = {
823 COSTS_N_INSNS (2), /* fp_add */
824 COSTS_N_INSNS (4), /* fp_mult_sf */
825 COSTS_N_INSNS (5), /* fp_mult_df */
826 COSTS_N_INSNS (12), /* fp_div_sf */
827 COSTS_N_INSNS (19), /* fp_div_df */
828 COSTS_N_INSNS (12), /* int_mult_si */
829 COSTS_N_INSNS (12), /* int_mult_di */
830 COSTS_N_INSNS (35), /* int_div_si */
831 COSTS_N_INSNS (35), /* int_div_di */
833 4 /* memory_latency */
837 COSTS_N_INSNS (6), /* int_mult_si */
838 COSTS_N_INSNS (6), /* int_mult_di */
839 COSTS_N_INSNS (36), /* int_div_si */
840 COSTS_N_INSNS (36), /* int_div_di */
842 4 /* memory_latency */
846 COSTS_N_INSNS (36), /* int_mult_si */
847 COSTS_N_INSNS (36), /* int_mult_di */
848 COSTS_N_INSNS (37), /* int_div_si */
849 COSTS_N_INSNS (37), /* int_div_di */
851 4 /* memory_latency */
855 COSTS_N_INSNS (4), /* int_mult_si */
856 COSTS_N_INSNS (11), /* int_mult_di */
857 COSTS_N_INSNS (36), /* int_div_si */
858 COSTS_N_INSNS (68), /* int_div_di */
860 4 /* memory_latency */
863 COSTS_N_INSNS (4), /* fp_add */
864 COSTS_N_INSNS (4), /* fp_mult_sf */
865 COSTS_N_INSNS (5), /* fp_mult_df */
866 COSTS_N_INSNS (17), /* fp_div_sf */
867 COSTS_N_INSNS (32), /* fp_div_df */
868 COSTS_N_INSNS (4), /* int_mult_si */
869 COSTS_N_INSNS (11), /* int_mult_di */
870 COSTS_N_INSNS (36), /* int_div_si */
871 COSTS_N_INSNS (68), /* int_div_di */
873 4 /* memory_latency */
876 COSTS_N_INSNS (4), /* fp_add */
877 COSTS_N_INSNS (4), /* fp_mult_sf */
878 COSTS_N_INSNS (5), /* fp_mult_df */
879 COSTS_N_INSNS (17), /* fp_div_sf */
880 COSTS_N_INSNS (32), /* fp_div_df */
881 COSTS_N_INSNS (4), /* int_mult_si */
882 COSTS_N_INSNS (7), /* int_mult_di */
883 COSTS_N_INSNS (42), /* int_div_si */
884 COSTS_N_INSNS (72), /* int_div_di */
886 4 /* memory_latency */
890 COSTS_N_INSNS (5), /* int_mult_si */
891 COSTS_N_INSNS (5), /* int_mult_di */
892 COSTS_N_INSNS (41), /* int_div_si */
893 COSTS_N_INSNS (41), /* int_div_di */
895 4 /* memory_latency */
898 COSTS_N_INSNS (8), /* fp_add */
899 COSTS_N_INSNS (8), /* fp_mult_sf */
900 COSTS_N_INSNS (10), /* fp_mult_df */
901 COSTS_N_INSNS (34), /* fp_div_sf */
902 COSTS_N_INSNS (64), /* fp_div_df */
903 COSTS_N_INSNS (5), /* int_mult_si */
904 COSTS_N_INSNS (5), /* int_mult_di */
905 COSTS_N_INSNS (41), /* int_div_si */
906 COSTS_N_INSNS (41), /* int_div_di */
908 4 /* memory_latency */
911 COSTS_N_INSNS (4), /* fp_add */
912 COSTS_N_INSNS (4), /* fp_mult_sf */
913 COSTS_N_INSNS (5), /* fp_mult_df */
914 COSTS_N_INSNS (17), /* fp_div_sf */
915 COSTS_N_INSNS (32), /* fp_div_df */
916 COSTS_N_INSNS (5), /* int_mult_si */
917 COSTS_N_INSNS (5), /* int_mult_di */
918 COSTS_N_INSNS (41), /* int_div_si */
919 COSTS_N_INSNS (41), /* int_div_di */
921 4 /* memory_latency */
925 COSTS_N_INSNS (5), /* int_mult_si */
926 COSTS_N_INSNS (5), /* int_mult_di */
927 COSTS_N_INSNS (41), /* int_div_si */
928 COSTS_N_INSNS (41), /* int_div_di */
930 4 /* memory_latency */
933 COSTS_N_INSNS (8), /* fp_add */
934 COSTS_N_INSNS (8), /* fp_mult_sf */
935 COSTS_N_INSNS (10), /* fp_mult_df */
936 COSTS_N_INSNS (34), /* fp_div_sf */
937 COSTS_N_INSNS (64), /* fp_div_df */
938 COSTS_N_INSNS (5), /* int_mult_si */
939 COSTS_N_INSNS (5), /* int_mult_di */
940 COSTS_N_INSNS (41), /* int_div_si */
941 COSTS_N_INSNS (41), /* int_div_di */
943 4 /* memory_latency */
946 COSTS_N_INSNS (4), /* fp_add */
947 COSTS_N_INSNS (4), /* fp_mult_sf */
948 COSTS_N_INSNS (5), /* fp_mult_df */
949 COSTS_N_INSNS (17), /* fp_div_sf */
950 COSTS_N_INSNS (32), /* fp_div_df */
951 COSTS_N_INSNS (5), /* int_mult_si */
952 COSTS_N_INSNS (5), /* int_mult_di */
953 COSTS_N_INSNS (41), /* int_div_si */
954 COSTS_N_INSNS (41), /* int_div_di */
956 4 /* memory_latency */
959 COSTS_N_INSNS (6), /* fp_add */
960 COSTS_N_INSNS (6), /* fp_mult_sf */
961 COSTS_N_INSNS (7), /* fp_mult_df */
962 COSTS_N_INSNS (25), /* fp_div_sf */
963 COSTS_N_INSNS (48), /* fp_div_df */
964 COSTS_N_INSNS (5), /* int_mult_si */
965 COSTS_N_INSNS (5), /* int_mult_di */
966 COSTS_N_INSNS (41), /* int_div_si */
967 COSTS_N_INSNS (41), /* int_div_di */
969 4 /* memory_latency */
986 COSTS_N_INSNS (5), /* int_mult_si */
987 COSTS_N_INSNS (5), /* int_mult_di */
988 COSTS_N_INSNS (72), /* int_div_si */
989 COSTS_N_INSNS (72), /* int_div_di */
991 4 /* memory_latency */
994 COSTS_N_INSNS (2), /* fp_add */
995 COSTS_N_INSNS (4), /* fp_mult_sf */
996 COSTS_N_INSNS (5), /* fp_mult_df */
997 COSTS_N_INSNS (12), /* fp_div_sf */
998 COSTS_N_INSNS (19), /* fp_div_df */
999 COSTS_N_INSNS (2), /* int_mult_si */
1000 COSTS_N_INSNS (2), /* int_mult_di */
1001 COSTS_N_INSNS (35), /* int_div_si */
1002 COSTS_N_INSNS (35), /* int_div_di */
1003 1, /* branch_cost */
1004 4 /* memory_latency */
1007 COSTS_N_INSNS (3), /* fp_add */
1008 COSTS_N_INSNS (5), /* fp_mult_sf */
1009 COSTS_N_INSNS (6), /* fp_mult_df */
1010 COSTS_N_INSNS (15), /* fp_div_sf */
1011 COSTS_N_INSNS (16), /* fp_div_df */
1012 COSTS_N_INSNS (17), /* int_mult_si */
1013 COSTS_N_INSNS (17), /* int_mult_di */
1014 COSTS_N_INSNS (38), /* int_div_si */
1015 COSTS_N_INSNS (38), /* int_div_di */
1016 2, /* branch_cost */
1017 6 /* memory_latency */
1020 COSTS_N_INSNS (6), /* fp_add */
1021 COSTS_N_INSNS (7), /* fp_mult_sf */
1022 COSTS_N_INSNS (8), /* fp_mult_df */
1023 COSTS_N_INSNS (23), /* fp_div_sf */
1024 COSTS_N_INSNS (36), /* fp_div_df */
1025 COSTS_N_INSNS (10), /* int_mult_si */
1026 COSTS_N_INSNS (10), /* int_mult_di */
1027 COSTS_N_INSNS (69), /* int_div_si */
1028 COSTS_N_INSNS (69), /* int_div_di */
1029 2, /* branch_cost */
1030 6 /* memory_latency */
1042 /* The only costs that appear to be updated here are
1043 integer multiplication. */
1045 COSTS_N_INSNS (4), /* int_mult_si */
1046 COSTS_N_INSNS (6), /* int_mult_di */
1047 COSTS_N_INSNS (69), /* int_div_si */
1048 COSTS_N_INSNS (69), /* int_div_di */
1049 1, /* branch_cost */
1050 4 /* memory_latency */
1062 COSTS_N_INSNS (6), /* fp_add */
1063 COSTS_N_INSNS (4), /* fp_mult_sf */
1064 COSTS_N_INSNS (5), /* fp_mult_df */
1065 COSTS_N_INSNS (23), /* fp_div_sf */
1066 COSTS_N_INSNS (36), /* fp_div_df */
1067 COSTS_N_INSNS (5), /* int_mult_si */
1068 COSTS_N_INSNS (5), /* int_mult_di */
1069 COSTS_N_INSNS (36), /* int_div_si */
1070 COSTS_N_INSNS (36), /* int_div_di */
1071 1, /* branch_cost */
1072 4 /* memory_latency */
1075 COSTS_N_INSNS (6), /* fp_add */
1076 COSTS_N_INSNS (5), /* fp_mult_sf */
1077 COSTS_N_INSNS (6), /* fp_mult_df */
1078 COSTS_N_INSNS (30), /* fp_div_sf */
1079 COSTS_N_INSNS (59), /* fp_div_df */
1080 COSTS_N_INSNS (3), /* int_mult_si */
1081 COSTS_N_INSNS (4), /* int_mult_di */
1082 COSTS_N_INSNS (42), /* int_div_si */
1083 COSTS_N_INSNS (74), /* int_div_di */
1084 1, /* branch_cost */
1085 4 /* memory_latency */
1088 COSTS_N_INSNS (6), /* fp_add */
1089 COSTS_N_INSNS (5), /* fp_mult_sf */
1090 COSTS_N_INSNS (6), /* fp_mult_df */
1091 COSTS_N_INSNS (30), /* fp_div_sf */
1092 COSTS_N_INSNS (59), /* fp_div_df */
1093 COSTS_N_INSNS (5), /* int_mult_si */
1094 COSTS_N_INSNS (9), /* int_mult_di */
1095 COSTS_N_INSNS (42), /* int_div_si */
1096 COSTS_N_INSNS (74), /* int_div_di */
1097 1, /* branch_cost */
1098 4 /* memory_latency */
1101 /* The only costs that are changed here are
1102 integer multiplication. */
1103 COSTS_N_INSNS (6), /* fp_add */
1104 COSTS_N_INSNS (7), /* fp_mult_sf */
1105 COSTS_N_INSNS (8), /* fp_mult_df */
1106 COSTS_N_INSNS (23), /* fp_div_sf */
1107 COSTS_N_INSNS (36), /* fp_div_df */
1108 COSTS_N_INSNS (5), /* int_mult_si */
1109 COSTS_N_INSNS (9), /* int_mult_di */
1110 COSTS_N_INSNS (69), /* int_div_si */
1111 COSTS_N_INSNS (69), /* int_div_di */
1112 1, /* branch_cost */
1113 4 /* memory_latency */
1119 /* The only costs that are changed here are
1120 integer multiplication. */
1121 COSTS_N_INSNS (6), /* fp_add */
1122 COSTS_N_INSNS (7), /* fp_mult_sf */
1123 COSTS_N_INSNS (8), /* fp_mult_df */
1124 COSTS_N_INSNS (23), /* fp_div_sf */
1125 COSTS_N_INSNS (36), /* fp_div_df */
1126 COSTS_N_INSNS (3), /* int_mult_si */
1127 COSTS_N_INSNS (8), /* int_mult_di */
1128 COSTS_N_INSNS (69), /* int_div_si */
1129 COSTS_N_INSNS (69), /* int_div_di */
1130 1, /* branch_cost */
1131 4 /* memory_latency */
1134 COSTS_N_INSNS (2), /* fp_add */
1135 COSTS_N_INSNS (2), /* fp_mult_sf */
1136 COSTS_N_INSNS (2), /* fp_mult_df */
1137 COSTS_N_INSNS (12), /* fp_div_sf */
1138 COSTS_N_INSNS (19), /* fp_div_df */
1139 COSTS_N_INSNS (5), /* int_mult_si */
1140 COSTS_N_INSNS (9), /* int_mult_di */
1141 COSTS_N_INSNS (34), /* int_div_si */
1142 COSTS_N_INSNS (66), /* int_div_di */
1143 1, /* branch_cost */
1144 4 /* memory_latency */
1147 /* These costs are the same as the SB-1A below. */
1148 COSTS_N_INSNS (4), /* fp_add */
1149 COSTS_N_INSNS (4), /* fp_mult_sf */
1150 COSTS_N_INSNS (4), /* fp_mult_df */
1151 COSTS_N_INSNS (24), /* fp_div_sf */
1152 COSTS_N_INSNS (32), /* fp_div_df */
1153 COSTS_N_INSNS (3), /* int_mult_si */
1154 COSTS_N_INSNS (4), /* int_mult_di */
1155 COSTS_N_INSNS (36), /* int_div_si */
1156 COSTS_N_INSNS (68), /* int_div_di */
1157 1, /* branch_cost */
1158 4 /* memory_latency */
1161 /* These costs are the same as the SB-1 above. */
1162 COSTS_N_INSNS (4), /* fp_add */
1163 COSTS_N_INSNS (4), /* fp_mult_sf */
1164 COSTS_N_INSNS (4), /* fp_mult_df */
1165 COSTS_N_INSNS (24), /* fp_div_sf */
1166 COSTS_N_INSNS (32), /* fp_div_df */
1167 COSTS_N_INSNS (3), /* int_mult_si */
1168 COSTS_N_INSNS (4), /* int_mult_di */
1169 COSTS_N_INSNS (36), /* int_div_si */
1170 COSTS_N_INSNS (68), /* int_div_di */
1171 1, /* branch_cost */
1172 4 /* memory_latency */
1179 COSTS_N_INSNS (8), /* int_mult_si */
1180 COSTS_N_INSNS (8), /* int_mult_di */
1181 COSTS_N_INSNS (72), /* int_div_si */
1182 COSTS_N_INSNS (72), /* int_div_di */
1183 1, /* branch_cost */
1184 4 /* memory_latency */
1188 static rtx mips_find_pic_call_symbol (rtx, rtx);
1189 static int mips_register_move_cost (enum machine_mode, reg_class_t,
1191 static unsigned int mips_function_arg_boundary (enum machine_mode, const_tree);
1193 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1194 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1195 struct GTY (()) mflip_mips16_entry {
1199 static GTY ((param_is (struct mflip_mips16_entry))) htab_t mflip_mips16_htab;
1201 /* Hash table callbacks for mflip_mips16_htab. */
1204 mflip_mips16_htab_hash (const void *entry)
1206 return htab_hash_string (((const struct mflip_mips16_entry *) entry)->name);
1210 mflip_mips16_htab_eq (const void *entry, const void *name)
1212 return strcmp (((const struct mflip_mips16_entry *) entry)->name,
1213 (const char *) name) == 0;
1216 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1217 mode, false if it should next add an attribute for the opposite mode. */
1218 static GTY(()) bool mips16_flipper;
1220 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1221 for -mflip-mips16. Return true if it should use "mips16" and false if
1222 it should use "nomips16". */
1225 mflip_mips16_use_mips16_p (tree decl)
1227 struct mflip_mips16_entry *entry;
1232 /* Use the opposite of the command-line setting for anonymous decls. */
1233 if (!DECL_NAME (decl))
1234 return !mips_base_mips16;
1236 if (!mflip_mips16_htab)
1237 mflip_mips16_htab = htab_create_ggc (37, mflip_mips16_htab_hash,
1238 mflip_mips16_htab_eq, NULL);
1240 name = IDENTIFIER_POINTER (DECL_NAME (decl));
1241 hash = htab_hash_string (name);
1242 slot = htab_find_slot_with_hash (mflip_mips16_htab, name, hash, INSERT);
1243 entry = (struct mflip_mips16_entry *) *slot;
1246 mips16_flipper = !mips16_flipper;
1247 entry = ggc_alloc_mflip_mips16_entry ();
1249 entry->mips16_p = mips16_flipper ? !mips_base_mips16 : mips_base_mips16;
1252 return entry->mips16_p;
1255 /* Predicates to test for presence of "near" and "far"/"long_call"
1256 attributes on the given TYPE. */
1259 mips_near_type_p (const_tree type)
1261 return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL;
1265 mips_far_type_p (const_tree type)
1267 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL
1268 || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL);
1271 /* Similar predicates for "mips16"/"nomips16" function attributes. */
1274 mips_mips16_decl_p (const_tree decl)
1276 return lookup_attribute ("mips16", DECL_ATTRIBUTES (decl)) != NULL;
1280 mips_nomips16_decl_p (const_tree decl)
1282 return lookup_attribute ("nomips16", DECL_ATTRIBUTES (decl)) != NULL;
1285 /* Check if the interrupt attribute is set for a function. */
1288 mips_interrupt_type_p (tree type)
1290 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type)) != NULL;
1293 /* Check if the attribute to use shadow register set is set for a function. */
1296 mips_use_shadow_register_set_p (tree type)
1298 return lookup_attribute ("use_shadow_register_set",
1299 TYPE_ATTRIBUTES (type)) != NULL;
1302 /* Check if the attribute to keep interrupts masked is set for a function. */
1305 mips_keep_interrupts_masked_p (tree type)
1307 return lookup_attribute ("keep_interrupts_masked",
1308 TYPE_ATTRIBUTES (type)) != NULL;
1311 /* Check if the attribute to use debug exception return is set for
1315 mips_use_debug_exception_return_p (tree type)
1317 return lookup_attribute ("use_debug_exception_return",
1318 TYPE_ATTRIBUTES (type)) != NULL;
1321 /* Return true if function DECL is a MIPS16 function. Return the ambient
1322 setting if DECL is null. */
1325 mips_use_mips16_mode_p (tree decl)
1329 /* Nested functions must use the same frame pointer as their
1330 parent and must therefore use the same ISA mode. */
1331 tree parent = decl_function_context (decl);
1334 if (mips_mips16_decl_p (decl))
1336 if (mips_nomips16_decl_p (decl))
1339 return mips_base_mips16;
1342 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1345 mips_comp_type_attributes (const_tree type1, const_tree type2)
1347 /* Disallow mixed near/far attributes. */
1348 if (mips_far_type_p (type1) && mips_near_type_p (type2))
1350 if (mips_near_type_p (type1) && mips_far_type_p (type2))
1355 /* Implement TARGET_INSERT_ATTRIBUTES. */
1358 mips_insert_attributes (tree decl, tree *attributes)
1361 bool mips16_p, nomips16_p;
1363 /* Check for "mips16" and "nomips16" attributes. */
1364 mips16_p = lookup_attribute ("mips16", *attributes) != NULL;
1365 nomips16_p = lookup_attribute ("nomips16", *attributes) != NULL;
1366 if (TREE_CODE (decl) != FUNCTION_DECL)
1369 error ("%qs attribute only applies to functions", "mips16");
1371 error ("%qs attribute only applies to functions", "nomips16");
1375 mips16_p |= mips_mips16_decl_p (decl);
1376 nomips16_p |= mips_nomips16_decl_p (decl);
1377 if (mips16_p || nomips16_p)
1379 /* DECL cannot be simultaneously "mips16" and "nomips16". */
1380 if (mips16_p && nomips16_p)
1381 error ("%qE cannot have both %<mips16%> and "
1382 "%<nomips16%> attributes",
1385 else if (TARGET_FLIP_MIPS16 && !DECL_ARTIFICIAL (decl))
1387 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1388 "mips16" attribute, arbitrarily pick one. We must pick the same
1389 setting for duplicate declarations of a function. */
1390 name = mflip_mips16_use_mips16_p (decl) ? "mips16" : "nomips16";
1391 *attributes = tree_cons (get_identifier (name), NULL, *attributes);
1396 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1399 mips_merge_decl_attributes (tree olddecl, tree newdecl)
1401 /* The decls' "mips16" and "nomips16" attributes must match exactly. */
1402 if (mips_mips16_decl_p (olddecl) != mips_mips16_decl_p (newdecl))
1403 error ("%qE redeclared with conflicting %qs attributes",
1404 DECL_NAME (newdecl), "mips16");
1405 if (mips_nomips16_decl_p (olddecl) != mips_nomips16_decl_p (newdecl))
1406 error ("%qE redeclared with conflicting %qs attributes",
1407 DECL_NAME (newdecl), "nomips16");
1409 return merge_attributes (DECL_ATTRIBUTES (olddecl),
1410 DECL_ATTRIBUTES (newdecl));
1413 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1414 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1417 mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr)
1419 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
1421 *base_ptr = XEXP (x, 0);
1422 *offset_ptr = INTVAL (XEXP (x, 1));
1431 static unsigned int mips_build_integer (struct mips_integer_op *,
1432 unsigned HOST_WIDE_INT);
1434 /* A subroutine of mips_build_integer, with the same interface.
1435 Assume that the final action in the sequence should be a left shift. */
1438 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1440 unsigned int i, shift;
1442 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1443 since signed numbers are easier to load than unsigned ones. */
1445 while ((value & 1) == 0)
1446 value /= 2, shift++;
1448 i = mips_build_integer (codes, value);
1449 codes[i].code = ASHIFT;
1450 codes[i].value = shift;
1454 /* As for mips_build_shift, but assume that the final action will be
1455 an IOR or PLUS operation. */
1458 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1460 unsigned HOST_WIDE_INT high;
1463 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1464 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
1466 /* The constant is too complex to load with a simple LUI/ORI pair,
1467 so we want to give the recursive call as many trailing zeros as
1468 possible. In this case, we know bit 16 is set and that the
1469 low 16 bits form a negative number. If we subtract that number
1470 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1471 i = mips_build_integer (codes, CONST_HIGH_PART (value));
1472 codes[i].code = PLUS;
1473 codes[i].value = CONST_LOW_PART (value);
1477 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1478 bits gives a value with at least 17 trailing zeros. */
1479 i = mips_build_integer (codes, high);
1480 codes[i].code = IOR;
1481 codes[i].value = value & 0xffff;
1486 /* Fill CODES with a sequence of rtl operations to load VALUE.
1487 Return the number of operations needed. */
1490 mips_build_integer (struct mips_integer_op *codes,
1491 unsigned HOST_WIDE_INT value)
1493 if (SMALL_OPERAND (value)
1494 || SMALL_OPERAND_UNSIGNED (value)
1495 || LUI_OPERAND (value))
1497 /* The value can be loaded with a single instruction. */
1498 codes[0].code = UNKNOWN;
1499 codes[0].value = value;
1502 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
1504 /* Either the constant is a simple LUI/ORI combination or its
1505 lowest bit is set. We don't want to shift in this case. */
1506 return mips_build_lower (codes, value);
1508 else if ((value & 0xffff) == 0)
1510 /* The constant will need at least three actions. The lowest
1511 16 bits are clear, so the final action will be a shift. */
1512 return mips_build_shift (codes, value);
1516 /* The final action could be a shift, add or inclusive OR.
1517 Rather than use a complex condition to select the best
1518 approach, try both mips_build_shift and mips_build_lower
1519 and pick the one that gives the shortest sequence.
1520 Note that this case is only used once per constant. */
1521 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1522 unsigned int cost, alt_cost;
1524 cost = mips_build_shift (codes, value);
1525 alt_cost = mips_build_lower (alt_codes, value);
1526 if (alt_cost < cost)
1528 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
1535 /* Return true if symbols of type TYPE require a GOT access. */
1538 mips_got_symbol_type_p (enum mips_symbol_type type)
1542 case SYMBOL_GOT_PAGE_OFST:
1543 case SYMBOL_GOT_DISP:
1551 /* Return true if X is a thread-local symbol. */
1554 mips_tls_symbol_p (rtx x)
1556 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1559 /* Return true if SYMBOL_REF X is associated with a global symbol
1560 (in the STB_GLOBAL sense). */
1563 mips_global_symbol_p (const_rtx x)
1565 const_tree decl = SYMBOL_REF_DECL (x);
1568 return !SYMBOL_REF_LOCAL_P (x) || SYMBOL_REF_EXTERNAL_P (x);
1570 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1571 or weak symbols. Relocations in the object file will be against
1572 the target symbol, so it's that symbol's binding that matters here. */
1573 return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl));
1576 /* Return true if function X is a libgcc MIPS16 stub function. */
1579 mips16_stub_function_p (const_rtx x)
1581 return (GET_CODE (x) == SYMBOL_REF
1582 && strncmp (XSTR (x, 0), "__mips16_", 9) == 0);
1585 /* Return true if function X is a locally-defined and locally-binding
1589 mips16_local_function_p (const_rtx x)
1591 return (GET_CODE (x) == SYMBOL_REF
1592 && SYMBOL_REF_LOCAL_P (x)
1593 && !SYMBOL_REF_EXTERNAL_P (x)
1594 && mips_use_mips16_mode_p (SYMBOL_REF_DECL (x)));
1597 /* Return true if SYMBOL_REF X binds locally. */
1600 mips_symbol_binds_local_p (const_rtx x)
1602 return (SYMBOL_REF_DECL (x)
1603 ? targetm.binds_local_p (SYMBOL_REF_DECL (x))
1604 : SYMBOL_REF_LOCAL_P (x));
1607 /* Return true if rtx constants of mode MODE should be put into a small
1611 mips_rtx_constant_in_small_data_p (enum machine_mode mode)
1613 return (!TARGET_EMBEDDED_DATA
1614 && TARGET_LOCAL_SDATA
1615 && GET_MODE_SIZE (mode) <= mips_small_data_threshold);
1618 /* Return true if X should not be moved directly into register $25.
1619 We need this because many versions of GAS will treat "la $25,foo" as
1620 part of a call sequence and so allow a global "foo" to be lazily bound. */
1623 mips_dangerous_for_la25_p (rtx x)
1625 return (!TARGET_EXPLICIT_RELOCS
1627 && GET_CODE (x) == SYMBOL_REF
1628 && mips_global_symbol_p (x));
1631 /* Return true if calls to X might need $25 to be valid on entry. */
1634 mips_use_pic_fn_addr_reg_p (const_rtx x)
1636 if (!TARGET_USE_PIC_FN_ADDR_REG)
1639 /* MIPS16 stub functions are guaranteed not to use $25. */
1640 if (mips16_stub_function_p (x))
1643 if (GET_CODE (x) == SYMBOL_REF)
1645 /* If PLTs and copy relocations are available, the static linker
1646 will make sure that $25 is valid on entry to the target function. */
1647 if (TARGET_ABICALLS_PIC0)
1650 /* Locally-defined functions use absolute accesses to set up
1651 the global pointer. */
1652 if (TARGET_ABSOLUTE_ABICALLS
1653 && mips_symbol_binds_local_p (x)
1654 && !SYMBOL_REF_EXTERNAL_P (x))
1661 /* Return the method that should be used to access SYMBOL_REF or
1662 LABEL_REF X in context CONTEXT. */
1664 static enum mips_symbol_type
1665 mips_classify_symbol (const_rtx x, enum mips_symbol_context context)
1668 return SYMBOL_GOT_DISP;
1670 if (GET_CODE (x) == LABEL_REF)
1672 /* Only return SYMBOL_PC_RELATIVE if we are generating MIPS16
1673 code and if we know that the label is in the current function's
1674 text section. LABEL_REFs are used for jump tables as well as
1675 text labels, so we must check whether jump tables live in the
1677 if (TARGET_MIPS16_SHORT_JUMP_TABLES
1678 && !LABEL_REF_NONLOCAL_P (x))
1679 return SYMBOL_PC_RELATIVE;
1681 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1682 return SYMBOL_GOT_PAGE_OFST;
1684 return SYMBOL_ABSOLUTE;
1687 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1689 if (SYMBOL_REF_TLS_MODEL (x))
1692 if (CONSTANT_POOL_ADDRESS_P (x))
1694 if (TARGET_MIPS16_TEXT_LOADS)
1695 return SYMBOL_PC_RELATIVE;
1697 if (TARGET_MIPS16_PCREL_LOADS && context == SYMBOL_CONTEXT_MEM)
1698 return SYMBOL_PC_RELATIVE;
1700 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x)))
1701 return SYMBOL_GP_RELATIVE;
1704 /* Do not use small-data accesses for weak symbols; they may end up
1706 if (TARGET_GPOPT && SYMBOL_REF_SMALL_P (x) && !SYMBOL_REF_WEAK (x))
1707 return SYMBOL_GP_RELATIVE;
1709 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1711 if (TARGET_ABICALLS_PIC2
1712 && !(TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x)))
1714 /* There are three cases to consider:
1716 - o32 PIC (either with or without explicit relocs)
1717 - n32/n64 PIC without explicit relocs
1718 - n32/n64 PIC with explicit relocs
1720 In the first case, both local and global accesses will use an
1721 R_MIPS_GOT16 relocation. We must correctly predict which of
1722 the two semantics (local or global) the assembler and linker
1723 will apply. The choice depends on the symbol's binding rather
1724 than its visibility.
1726 In the second case, the assembler will not use R_MIPS_GOT16
1727 relocations, but it chooses between local and global accesses
1728 in the same way as for o32 PIC.
1730 In the third case we have more freedom since both forms of
1731 access will work for any kind of symbol. However, there seems
1732 little point in doing things differently. */
1733 if (mips_global_symbol_p (x))
1734 return SYMBOL_GOT_DISP;
1736 return SYMBOL_GOT_PAGE_OFST;
1739 if (TARGET_MIPS16_PCREL_LOADS && context != SYMBOL_CONTEXT_CALL)
1740 return SYMBOL_FORCE_TO_MEM;
1742 return SYMBOL_ABSOLUTE;
1745 /* Classify the base of symbolic expression X, given that X appears in
1748 static enum mips_symbol_type
1749 mips_classify_symbolic_expression (rtx x, enum mips_symbol_context context)
1753 split_const (x, &x, &offset);
1754 if (UNSPEC_ADDRESS_P (x))
1755 return UNSPEC_ADDRESS_TYPE (x);
1757 return mips_classify_symbol (x, context);
1760 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1761 is the alignment in bytes of SYMBOL_REF X. */
1764 mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset)
1766 HOST_WIDE_INT align;
1768 align = SYMBOL_REF_DECL (x) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x)) : 1;
1769 return IN_RANGE (offset, 0, align - 1);
1772 /* Return true if X is a symbolic constant that can be used in context
1773 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1776 mips_symbolic_constant_p (rtx x, enum mips_symbol_context context,
1777 enum mips_symbol_type *symbol_type)
1781 split_const (x, &x, &offset);
1782 if (UNSPEC_ADDRESS_P (x))
1784 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1785 x = UNSPEC_ADDRESS (x);
1787 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1789 *symbol_type = mips_classify_symbol (x, context);
1790 if (*symbol_type == SYMBOL_TLS)
1796 if (offset == const0_rtx)
1799 /* Check whether a nonzero offset is valid for the underlying
1801 switch (*symbol_type)
1803 case SYMBOL_ABSOLUTE:
1804 case SYMBOL_FORCE_TO_MEM:
1805 case SYMBOL_32_HIGH:
1806 case SYMBOL_64_HIGH:
1809 /* If the target has 64-bit pointers and the object file only
1810 supports 32-bit symbols, the values of those symbols will be
1811 sign-extended. In this case we can't allow an arbitrary offset
1812 in case the 32-bit value X + OFFSET has a different sign from X. */
1813 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1814 return offset_within_block_p (x, INTVAL (offset));
1816 /* In other cases the relocations can handle any offset. */
1819 case SYMBOL_PC_RELATIVE:
1820 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1821 In this case, we no longer have access to the underlying constant,
1822 but the original symbol-based access was known to be valid. */
1823 if (GET_CODE (x) == LABEL_REF)
1828 case SYMBOL_GP_RELATIVE:
1829 /* Make sure that the offset refers to something within the
1830 same object block. This should guarantee that the final
1831 PC- or GP-relative offset is within the 16-bit limit. */
1832 return offset_within_block_p (x, INTVAL (offset));
1834 case SYMBOL_GOT_PAGE_OFST:
1835 case SYMBOL_GOTOFF_PAGE:
1836 /* If the symbol is global, the GOT entry will contain the symbol's
1837 address, and we will apply a 16-bit offset after loading it.
1838 If the symbol is local, the linker should provide enough local
1839 GOT entries for a 16-bit offset, but larger offsets may lead
1841 return SMALL_INT (offset);
1845 /* There is no carry between the HI and LO REL relocations, so the
1846 offset is only valid if we know it won't lead to such a carry. */
1847 return mips_offset_within_alignment_p (x, INTVAL (offset));
1849 case SYMBOL_GOT_DISP:
1850 case SYMBOL_GOTOFF_DISP:
1851 case SYMBOL_GOTOFF_CALL:
1852 case SYMBOL_GOTOFF_LOADGP:
1855 case SYMBOL_GOTTPREL:
1863 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
1864 single instruction. We rely on the fact that, in the worst case,
1865 all instructions involved in a MIPS16 address calculation are usually
1869 mips_symbol_insns_1 (enum mips_symbol_type type, enum machine_mode mode)
1873 case SYMBOL_ABSOLUTE:
1874 /* When using 64-bit symbols, we need 5 preparatory instructions,
1877 lui $at,%highest(symbol)
1878 daddiu $at,$at,%higher(symbol)
1880 daddiu $at,$at,%hi(symbol)
1883 The final address is then $at + %lo(symbol). With 32-bit
1884 symbols we just need a preparatory LUI for normal mode and
1885 a preparatory LI and SLL for MIPS16. */
1886 return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2;
1888 case SYMBOL_GP_RELATIVE:
1889 /* Treat GP-relative accesses as taking a single instruction on
1890 MIPS16 too; the copy of $gp can often be shared. */
1893 case SYMBOL_PC_RELATIVE:
1894 /* PC-relative constants can be only be used with ADDIUPC,
1895 DADDIUPC, LWPC and LDPC. */
1896 if (mode == MAX_MACHINE_MODE
1897 || GET_MODE_SIZE (mode) == 4
1898 || GET_MODE_SIZE (mode) == 8)
1901 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
1904 case SYMBOL_FORCE_TO_MEM:
1905 /* LEAs will be converted into constant-pool references by
1907 if (mode == MAX_MACHINE_MODE)
1910 /* The constant must be loaded and then dereferenced. */
1913 case SYMBOL_GOT_DISP:
1914 /* The constant will have to be loaded from the GOT before it
1915 is used in an address. */
1916 if (mode != MAX_MACHINE_MODE)
1921 case SYMBOL_GOT_PAGE_OFST:
1922 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
1923 local/global classification is accurate. The worst cases are:
1925 (1) For local symbols when generating o32 or o64 code. The assembler
1931 ...and the final address will be $at + %lo(symbol).
1933 (2) For global symbols when -mxgot. The assembler will use:
1935 lui $at,%got_hi(symbol)
1938 ...and the final address will be $at + %got_lo(symbol). */
1941 case SYMBOL_GOTOFF_PAGE:
1942 case SYMBOL_GOTOFF_DISP:
1943 case SYMBOL_GOTOFF_CALL:
1944 case SYMBOL_GOTOFF_LOADGP:
1945 case SYMBOL_32_HIGH:
1946 case SYMBOL_64_HIGH:
1952 case SYMBOL_GOTTPREL:
1955 /* A 16-bit constant formed by a single relocation, or a 32-bit
1956 constant formed from a high 16-bit relocation and a low 16-bit
1957 relocation. Use mips_split_p to determine which. 32-bit
1958 constants need an "lui; addiu" sequence for normal mode and
1959 an "li; sll; addiu" sequence for MIPS16 mode. */
1960 return !mips_split_p[type] ? 1 : TARGET_MIPS16 ? 3 : 2;
1963 /* We don't treat a bare TLS symbol as a constant. */
1969 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
1970 to load symbols of type TYPE into a register. Return 0 if the given
1971 type of symbol cannot be used as an immediate operand.
1973 Otherwise, return the number of instructions needed to load or store
1974 values of mode MODE to or from addresses of type TYPE. Return 0 if
1975 the given type of symbol is not valid in addresses.
1977 In both cases, treat extended MIPS16 instructions as two instructions. */
1980 mips_symbol_insns (enum mips_symbol_type type, enum machine_mode mode)
1982 return mips_symbol_insns_1 (type, mode) * (TARGET_MIPS16 ? 2 : 1);
1985 /* A for_each_rtx callback. Stop the search if *X references a
1986 thread-local symbol. */
1989 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1991 return mips_tls_symbol_p (*x);
1994 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1997 mips_cannot_force_const_mem (rtx x)
1999 enum mips_symbol_type type;
2002 /* There is no assembler syntax for expressing an address-sized
2004 if (GET_CODE (x) == HIGH)
2007 /* As an optimization, reject constants that mips_legitimize_move
2010 Suppose we have a multi-instruction sequence that loads constant C
2011 into register R. If R does not get allocated a hard register, and
2012 R is used in an operand that allows both registers and memory
2013 references, reload will consider forcing C into memory and using
2014 one of the instruction's memory alternatives. Returning false
2015 here will force it to use an input reload instead. */
2016 if (CONST_INT_P (x) && LEGITIMATE_CONSTANT_P (x))
2019 split_const (x, &base, &offset);
2020 if (mips_symbolic_constant_p (base, SYMBOL_CONTEXT_LEA, &type)
2021 && type != SYMBOL_FORCE_TO_MEM)
2023 /* The same optimization as for CONST_INT. */
2024 if (SMALL_INT (offset) && mips_symbol_insns (type, MAX_MACHINE_MODE) > 0)
2027 /* If MIPS16 constant pools live in the text section, they should
2028 not refer to anything that might need run-time relocation. */
2029 if (TARGET_MIPS16_PCREL_LOADS && mips_got_symbol_type_p (type))
2033 /* TLS symbols must be computed by mips_legitimize_move. */
2034 if (for_each_rtx (&x, &mips_tls_symbol_ref_1, NULL))
2040 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
2041 constants when we're using a per-function constant pool. */
2044 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
2045 const_rtx x ATTRIBUTE_UNUSED)
2047 return !TARGET_MIPS16_PCREL_LOADS;
2050 /* Return true if register REGNO is a valid base register for mode MODE.
2051 STRICT_P is true if REG_OK_STRICT is in effect. */
2054 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode,
2057 if (!HARD_REGISTER_NUM_P (regno))
2061 regno = reg_renumber[regno];
2064 /* These fake registers will be eliminated to either the stack or
2065 hard frame pointer, both of which are usually valid base registers.
2066 Reload deals with the cases where the eliminated form isn't valid. */
2067 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
2070 /* In MIPS16 mode, the stack pointer can only address word and doubleword
2071 values, nothing smaller. There are two problems here:
2073 (a) Instantiating virtual registers can introduce new uses of the
2074 stack pointer. If these virtual registers are valid addresses,
2075 the stack pointer should be too.
2077 (b) Most uses of the stack pointer are not made explicit until
2078 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
2079 We don't know until that stage whether we'll be eliminating to the
2080 stack pointer (which needs the restriction) or the hard frame
2081 pointer (which doesn't).
2083 All in all, it seems more consistent to only enforce this restriction
2084 during and after reload. */
2085 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
2086 return !strict_p || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
2088 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
2091 /* Return true if X is a valid base register for mode MODE.
2092 STRICT_P is true if REG_OK_STRICT is in effect. */
2095 mips_valid_base_register_p (rtx x, enum machine_mode mode, bool strict_p)
2097 if (!strict_p && GET_CODE (x) == SUBREG)
2101 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p));
2104 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2105 can address a value of mode MODE. */
2108 mips_valid_offset_p (rtx x, enum machine_mode mode)
2110 /* Check that X is a signed 16-bit number. */
2111 if (!const_arith_operand (x, Pmode))
2114 /* We may need to split multiword moves, so make sure that every word
2116 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2117 && !SMALL_OPERAND (INTVAL (x) + GET_MODE_SIZE (mode) - UNITS_PER_WORD))
2123 /* Return true if a LO_SUM can address a value of mode MODE when the
2124 LO_SUM symbol has type SYMBOL_TYPE. */
2127 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type, enum machine_mode mode)
2129 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2131 if (mips_symbol_insns (symbol_type, mode) == 0)
2134 /* Check that there is a known low-part relocation. */
2135 if (mips_lo_relocs[symbol_type] == NULL)
2138 /* We may need to split multiword moves, so make sure that each word
2139 can be accessed without inducing a carry. This is mainly needed
2140 for o64, which has historically only guaranteed 64-bit alignment
2141 for 128-bit types. */
2142 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2143 && GET_MODE_BITSIZE (mode) > GET_MODE_ALIGNMENT (mode))
2149 /* Return true if X is a valid address for machine mode MODE. If it is,
2150 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2154 mips_classify_address (struct mips_address_info *info, rtx x,
2155 enum machine_mode mode, bool strict_p)
2157 switch (GET_CODE (x))
2161 info->type = ADDRESS_REG;
2163 info->offset = const0_rtx;
2164 return mips_valid_base_register_p (info->reg, mode, strict_p);
2167 info->type = ADDRESS_REG;
2168 info->reg = XEXP (x, 0);
2169 info->offset = XEXP (x, 1);
2170 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2171 && mips_valid_offset_p (info->offset, mode));
2174 info->type = ADDRESS_LO_SUM;
2175 info->reg = XEXP (x, 0);
2176 info->offset = XEXP (x, 1);
2177 /* We have to trust the creator of the LO_SUM to do something vaguely
2178 sane. Target-independent code that creates a LO_SUM should also
2179 create and verify the matching HIGH. Target-independent code that
2180 adds an offset to a LO_SUM must prove that the offset will not
2181 induce a carry. Failure to do either of these things would be
2182 a bug, and we are not required to check for it here. The MIPS
2183 backend itself should only create LO_SUMs for valid symbolic
2184 constants, with the high part being either a HIGH or a copy
2187 = mips_classify_symbolic_expression (info->offset, SYMBOL_CONTEXT_MEM);
2188 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2189 && mips_valid_lo_sum_p (info->symbol_type, mode));
2192 /* Small-integer addresses don't occur very often, but they
2193 are legitimate if $0 is a valid base register. */
2194 info->type = ADDRESS_CONST_INT;
2195 return !TARGET_MIPS16 && SMALL_INT (x);
2200 info->type = ADDRESS_SYMBOLIC;
2201 return (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_MEM,
2203 && mips_symbol_insns (info->symbol_type, mode) > 0
2204 && !mips_split_p[info->symbol_type]);
2211 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2214 mips_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
2216 struct mips_address_info addr;
2218 return mips_classify_address (&addr, x, mode, strict_p);
2221 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
2224 mips_stack_address_p (rtx x, enum machine_mode mode)
2226 struct mips_address_info addr;
2228 return (mips_classify_address (&addr, x, mode, false)
2229 && addr.type == ADDRESS_REG
2230 && addr.reg == stack_pointer_rtx);
2233 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2234 address instruction. Note that such addresses are not considered
2235 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2236 is so restricted. */
2239 mips_lwxs_address_p (rtx addr)
2242 && GET_CODE (addr) == PLUS
2243 && REG_P (XEXP (addr, 1)))
2245 rtx offset = XEXP (addr, 0);
2246 if (GET_CODE (offset) == MULT
2247 && REG_P (XEXP (offset, 0))
2248 && CONST_INT_P (XEXP (offset, 1))
2249 && INTVAL (XEXP (offset, 1)) == 4)
2255 /* Return true if a value at OFFSET bytes from base register BASE can be
2256 accessed using an unextended MIPS16 instruction. MODE is the mode of
2259 Usually the offset in an unextended instruction is a 5-bit field.
2260 The offset is unsigned and shifted left once for LH and SH, twice
2261 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2262 an 8-bit immediate field that's shifted left twice. */
2265 mips16_unextended_reference_p (enum machine_mode mode, rtx base,
2266 unsigned HOST_WIDE_INT offset)
2268 if (offset % GET_MODE_SIZE (mode) == 0)
2270 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
2271 return offset < 256U * GET_MODE_SIZE (mode);
2272 return offset < 32U * GET_MODE_SIZE (mode);
2277 /* Return the number of instructions needed to load or store a value
2278 of mode MODE at address X. Return 0 if X isn't valid for MODE.
2279 Assume that multiword moves may need to be split into word moves
2280 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2283 For MIPS16 code, count extended instructions as two instructions. */
2286 mips_address_insns (rtx x, enum machine_mode mode, bool might_split_p)
2288 struct mips_address_info addr;
2291 /* BLKmode is used for single unaligned loads and stores and should
2292 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2293 meaningless, so we have to single it out as a special case one way
2295 if (mode != BLKmode && might_split_p)
2296 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2300 if (mips_classify_address (&addr, x, mode, false))
2305 && !mips16_unextended_reference_p (mode, addr.reg,
2306 UINTVAL (addr.offset)))
2310 case ADDRESS_LO_SUM:
2311 return TARGET_MIPS16 ? factor * 2 : factor;
2313 case ADDRESS_CONST_INT:
2316 case ADDRESS_SYMBOLIC:
2317 return factor * mips_symbol_insns (addr.symbol_type, mode);
2322 /* Return the number of instructions needed to load constant X.
2323 Return 0 if X isn't a valid constant. */
2326 mips_const_insns (rtx x)
2328 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2329 enum mips_symbol_type symbol_type;
2332 switch (GET_CODE (x))
2335 if (!mips_symbolic_constant_p (XEXP (x, 0), SYMBOL_CONTEXT_LEA,
2337 || !mips_split_p[symbol_type])
2340 /* This is simply an LUI for normal mode. It is an extended
2341 LI followed by an extended SLL for MIPS16. */
2342 return TARGET_MIPS16 ? 4 : 1;
2346 /* Unsigned 8-bit constants can be loaded using an unextended
2347 LI instruction. Unsigned 16-bit constants can be loaded
2348 using an extended LI. Negative constants must be loaded
2349 using LI and then negated. */
2350 return (IN_RANGE (INTVAL (x), 0, 255) ? 1
2351 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
2352 : IN_RANGE (-INTVAL (x), 0, 255) ? 2
2353 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
2356 return mips_build_integer (codes, INTVAL (x));
2360 /* Allow zeros for normal mode, where we can use $0. */
2361 return !TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0;
2367 /* See if we can refer to X directly. */
2368 if (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_LEA, &symbol_type))
2369 return mips_symbol_insns (symbol_type, MAX_MACHINE_MODE);
2371 /* Otherwise try splitting the constant into a base and offset.
2372 If the offset is a 16-bit value, we can load the base address
2373 into a register and then use (D)ADDIU to add in the offset.
2374 If the offset is larger, we can load the base and offset
2375 into separate registers and add them together with (D)ADDU.
2376 However, the latter is only possible before reload; during
2377 and after reload, we must have the option of forcing the
2378 constant into the pool instead. */
2379 split_const (x, &x, &offset);
2382 int n = mips_const_insns (x);
2385 if (SMALL_INT (offset))
2387 else if (!targetm.cannot_force_const_mem (x))
2388 return n + 1 + mips_build_integer (codes, INTVAL (offset));
2395 return mips_symbol_insns (mips_classify_symbol (x, SYMBOL_CONTEXT_LEA),
2403 /* X is a doubleword constant that can be handled by splitting it into
2404 two words and loading each word separately. Return the number of
2405 instructions required to do this. */
2408 mips_split_const_insns (rtx x)
2410 unsigned int low, high;
2412 low = mips_const_insns (mips_subword (x, false));
2413 high = mips_const_insns (mips_subword (x, true));
2414 gcc_assert (low > 0 && high > 0);
2418 /* Return the number of instructions needed to implement INSN,
2419 given that it loads from or stores to MEM. Count extended
2420 MIPS16 instructions as two instructions. */
2423 mips_load_store_insns (rtx mem, rtx insn)
2425 enum machine_mode mode;
2429 gcc_assert (MEM_P (mem));
2430 mode = GET_MODE (mem);
2432 /* Try to prove that INSN does not need to be split. */
2433 might_split_p = true;
2434 if (GET_MODE_BITSIZE (mode) == 64)
2436 set = single_set (insn);
2437 if (set && !mips_split_64bit_move_p (SET_DEST (set), SET_SRC (set)))
2438 might_split_p = false;
2441 return mips_address_insns (XEXP (mem, 0), mode, might_split_p);
2444 /* Return the number of instructions needed for an integer division. */
2447 mips_idiv_insns (void)
2452 if (TARGET_CHECK_ZERO_DIV)
2454 if (GENERATE_DIVIDE_TRAPS)
2460 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
2465 /* Emit a move from SRC to DEST. Assume that the move expanders can
2466 handle all moves if !can_create_pseudo_p (). The distinction is
2467 important because, unlike emit_move_insn, the move expanders know
2468 how to force Pmode objects into the constant pool even when the
2469 constant pool address is not itself legitimate. */
2472 mips_emit_move (rtx dest, rtx src)
2474 return (can_create_pseudo_p ()
2475 ? emit_move_insn (dest, src)
2476 : emit_move_insn_1 (dest, src));
2479 /* Emit an instruction of the form (set TARGET (CODE OP0)). */
2482 mips_emit_unary (enum rtx_code code, rtx target, rtx op0)
2484 emit_insn (gen_rtx_SET (VOIDmode, target,
2485 gen_rtx_fmt_e (code, GET_MODE (op0), op0)));
2488 /* Compute (CODE OP0) and store the result in a new register of mode MODE.
2489 Return that new register. */
2492 mips_force_unary (enum machine_mode mode, enum rtx_code code, rtx op0)
2496 reg = gen_reg_rtx (mode);
2497 mips_emit_unary (code, reg, op0);
2501 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2504 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
2506 emit_insn (gen_rtx_SET (VOIDmode, target,
2507 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
2510 /* Compute (CODE OP0 OP1) and store the result in a new register
2511 of mode MODE. Return that new register. */
2514 mips_force_binary (enum machine_mode mode, enum rtx_code code, rtx op0, rtx op1)
2518 reg = gen_reg_rtx (mode);
2519 mips_emit_binary (code, reg, op0, op1);
2523 /* Copy VALUE to a register and return that register. If new pseudos
2524 are allowed, copy it into a new register, otherwise use DEST. */
2527 mips_force_temporary (rtx dest, rtx value)
2529 if (can_create_pseudo_p ())
2530 return force_reg (Pmode, value);
2533 mips_emit_move (dest, value);
2538 /* Emit a call sequence with call pattern PATTERN and return the call
2539 instruction itself (which is not necessarily the last instruction
2540 emitted). ORIG_ADDR is the original, unlegitimized address,
2541 ADDR is the legitimized form, and LAZY_P is true if the call
2542 address is lazily-bound. */
2545 mips_emit_call_insn (rtx pattern, rtx orig_addr, rtx addr, bool lazy_p)
2549 insn = emit_call_insn (pattern);
2551 if (TARGET_MIPS16 && mips_use_pic_fn_addr_reg_p (orig_addr))
2553 /* MIPS16 JALRs only take MIPS16 registers. If the target
2554 function requires $25 to be valid on entry, we must copy it
2555 there separately. The move instruction can be put in the
2556 call's delay slot. */
2557 reg = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
2558 emit_insn_before (gen_move_insn (reg, addr), insn);
2559 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
2563 /* Lazy-binding stubs require $gp to be valid on entry. */
2564 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
2568 /* See the comment above load_call<mode> for details. */
2569 use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
2570 gen_rtx_REG (Pmode, GOT_VERSION_REGNUM));
2571 emit_insn (gen_update_got_version ());
2576 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2577 then add CONST_INT OFFSET to the result. */
2580 mips_unspec_address_offset (rtx base, rtx offset,
2581 enum mips_symbol_type symbol_type)
2583 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
2584 UNSPEC_ADDRESS_FIRST + symbol_type);
2585 if (offset != const0_rtx)
2586 base = gen_rtx_PLUS (Pmode, base, offset);
2587 return gen_rtx_CONST (Pmode, base);
2590 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2591 type SYMBOL_TYPE. */
2594 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
2598 split_const (address, &base, &offset);
2599 return mips_unspec_address_offset (base, offset, symbol_type);
2602 /* If OP is an UNSPEC address, return the address to which it refers,
2603 otherwise return OP itself. */
2606 mips_strip_unspec_address (rtx op)
2610 split_const (op, &base, &offset);
2611 if (UNSPEC_ADDRESS_P (base))
2612 op = plus_constant (UNSPEC_ADDRESS (base), INTVAL (offset));
2616 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2617 high part to BASE and return the result. Just return BASE otherwise.
2618 TEMP is as for mips_force_temporary.
2620 The returned expression can be used as the first operand to a LO_SUM. */
2623 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
2624 enum mips_symbol_type symbol_type)
2626 if (mips_split_p[symbol_type])
2628 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
2629 addr = mips_force_temporary (temp, addr);
2630 base = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
2635 /* Return an instruction that copies $gp into register REG. We want
2636 GCC to treat the register's value as constant, so that its value
2637 can be rematerialized on demand. */
2640 gen_load_const_gp (rtx reg)
2642 return (Pmode == SImode
2643 ? gen_load_const_gp_si (reg)
2644 : gen_load_const_gp_di (reg));
2647 /* Return a pseudo register that contains the value of $gp throughout
2648 the current function. Such registers are needed by MIPS16 functions,
2649 for which $gp itself is not a valid base register or addition operand. */
2652 mips16_gp_pseudo_reg (void)
2654 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
2658 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
2660 push_topmost_sequence ();
2662 scan = get_insns ();
2663 while (NEXT_INSN (scan) && !INSN_P (NEXT_INSN (scan)))
2664 scan = NEXT_INSN (scan);
2666 insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
2667 emit_insn_after (insn, scan);
2669 pop_topmost_sequence ();
2672 return cfun->machine->mips16_gp_pseudo_rtx;
2675 /* Return a base register that holds pic_offset_table_rtx.
2676 TEMP, if nonnull, is a scratch Pmode base register. */
2679 mips_pic_base_register (rtx temp)
2682 return pic_offset_table_rtx;
2684 if (currently_expanding_to_rtl)
2685 return mips16_gp_pseudo_reg ();
2687 if (can_create_pseudo_p ())
2688 temp = gen_reg_rtx (Pmode);
2691 /* The first post-reload split exposes all references to $gp
2692 (both uses and definitions). All references must remain
2693 explicit after that point.
2695 It is safe to introduce uses of $gp at any time, so for
2696 simplicity, we do that before the split too. */
2697 mips_emit_move (temp, pic_offset_table_rtx);
2699 emit_insn (gen_load_const_gp (temp));
2703 /* Return the RHS of a load_call<mode> insn. */
2706 mips_unspec_call (rtx reg, rtx symbol)
2710 vec = gen_rtvec (3, reg, symbol, gen_rtx_REG (SImode, GOT_VERSION_REGNUM));
2711 return gen_rtx_UNSPEC (Pmode, vec, UNSPEC_LOAD_CALL);
2714 /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol
2715 reference. Return NULL_RTX otherwise. */
2718 mips_strip_unspec_call (rtx src)
2720 if (GET_CODE (src) == UNSPEC && XINT (src, 1) == UNSPEC_LOAD_CALL)
2721 return mips_strip_unspec_address (XVECEXP (src, 0, 1));
2725 /* Create and return a GOT reference of type TYPE for address ADDR.
2726 TEMP, if nonnull, is a scratch Pmode base register. */
2729 mips_got_load (rtx temp, rtx addr, enum mips_symbol_type type)
2731 rtx base, high, lo_sum_symbol;
2733 base = mips_pic_base_register (temp);
2735 /* If we used the temporary register to load $gp, we can't use
2736 it for the high part as well. */
2737 if (temp != NULL && reg_overlap_mentioned_p (base, temp))
2740 high = mips_unspec_offset_high (temp, base, addr, type);
2741 lo_sum_symbol = mips_unspec_address (addr, type);
2743 if (type == SYMBOL_GOTOFF_CALL)
2744 return mips_unspec_call (high, lo_sum_symbol);
2746 return (Pmode == SImode
2747 ? gen_unspec_gotsi (high, lo_sum_symbol)
2748 : gen_unspec_gotdi (high, lo_sum_symbol));
2751 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2752 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2753 constant in that context and can be split into high and low parts.
2754 If so, and if LOW_OUT is nonnull, emit the high part and store the
2755 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
2757 TEMP is as for mips_force_temporary and is used to load the high
2758 part into a register.
2760 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
2761 a legitimize SET_SRC for an .md pattern, otherwise the low part
2762 is guaranteed to be a legitimate address for mode MODE. */
2765 mips_split_symbol (rtx temp, rtx addr, enum machine_mode mode, rtx *low_out)
2767 enum mips_symbol_context context;
2768 enum mips_symbol_type symbol_type;
2771 context = (mode == MAX_MACHINE_MODE
2772 ? SYMBOL_CONTEXT_LEA
2773 : SYMBOL_CONTEXT_MEM);
2774 if (GET_CODE (addr) == HIGH && context == SYMBOL_CONTEXT_LEA)
2776 addr = XEXP (addr, 0);
2777 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2778 && mips_symbol_insns (symbol_type, mode) > 0
2779 && mips_split_hi_p[symbol_type])
2782 switch (symbol_type)
2784 case SYMBOL_GOT_PAGE_OFST:
2785 /* The high part of a page/ofst pair is loaded from the GOT. */
2786 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_PAGE);
2797 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2798 && mips_symbol_insns (symbol_type, mode) > 0
2799 && mips_split_p[symbol_type])
2802 switch (symbol_type)
2804 case SYMBOL_GOT_DISP:
2805 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
2806 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_DISP);
2809 case SYMBOL_GP_RELATIVE:
2810 high = mips_pic_base_register (temp);
2811 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2815 high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
2816 high = mips_force_temporary (temp, high);
2817 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2826 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2827 mips_force_temporary; it is only needed when OFFSET is not a
2831 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
2833 if (!SMALL_OPERAND (offset))
2839 /* Load the full offset into a register so that we can use
2840 an unextended instruction for the address itself. */
2841 high = GEN_INT (offset);
2846 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
2847 The addition inside the macro CONST_HIGH_PART may cause an
2848 overflow, so we need to force a sign-extension check. */
2849 high = gen_int_mode (CONST_HIGH_PART (offset), Pmode);
2850 offset = CONST_LOW_PART (offset);
2852 high = mips_force_temporary (temp, high);
2853 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
2855 return plus_constant (reg, offset);
2858 /* The __tls_get_attr symbol. */
2859 static GTY(()) rtx mips_tls_symbol;
2861 /* Return an instruction sequence that calls __tls_get_addr. SYM is
2862 the TLS symbol we are referencing and TYPE is the symbol type to use
2863 (either global dynamic or local dynamic). V0 is an RTX for the
2864 return value location. */
2867 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
2871 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
2873 if (!mips_tls_symbol)
2874 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
2876 loc = mips_unspec_address (sym, type);
2880 emit_insn (gen_rtx_SET (Pmode, a0,
2881 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
2882 insn = mips_expand_call (MIPS_CALL_NORMAL, v0, mips_tls_symbol,
2883 const0_rtx, NULL_RTX, false);
2884 RTL_CONST_CALL_P (insn) = 1;
2885 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
2886 insn = get_insns ();
2893 /* Return a pseudo register that contains the current thread pointer. */
2900 tp = gen_reg_rtx (Pmode);
2901 if (Pmode == DImode)
2902 emit_insn (gen_tls_get_tp_di (tp));
2904 emit_insn (gen_tls_get_tp_si (tp));
2908 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
2909 its address. The return value will be both a valid address and a valid
2910 SET_SRC (either a REG or a LO_SUM). */
2913 mips_legitimize_tls_address (rtx loc)
2915 rtx dest, insn, v0, tp, tmp1, tmp2, eqv;
2916 enum tls_model model;
2920 sorry ("MIPS16 TLS");
2921 return gen_reg_rtx (Pmode);
2924 model = SYMBOL_REF_TLS_MODEL (loc);
2925 /* Only TARGET_ABICALLS code can have more than one module; other
2926 code must be be static and should not use a GOT. All TLS models
2927 reduce to local exec in this situation. */
2928 if (!TARGET_ABICALLS)
2929 model = TLS_MODEL_LOCAL_EXEC;
2933 case TLS_MODEL_GLOBAL_DYNAMIC:
2934 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2935 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
2936 dest = gen_reg_rtx (Pmode);
2937 emit_libcall_block (insn, dest, v0, loc);
2940 case TLS_MODEL_LOCAL_DYNAMIC:
2941 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2942 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
2943 tmp1 = gen_reg_rtx (Pmode);
2945 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2946 share the LDM result with other LD model accesses. */
2947 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2949 emit_libcall_block (insn, tmp1, v0, eqv);
2951 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
2952 dest = gen_rtx_LO_SUM (Pmode, tmp2,
2953 mips_unspec_address (loc, SYMBOL_DTPREL));
2956 case TLS_MODEL_INITIAL_EXEC:
2957 tp = mips_get_tp ();
2958 tmp1 = gen_reg_rtx (Pmode);
2959 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
2960 if (Pmode == DImode)
2961 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
2963 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
2964 dest = gen_reg_rtx (Pmode);
2965 emit_insn (gen_add3_insn (dest, tmp1, tp));
2968 case TLS_MODEL_LOCAL_EXEC:
2969 tp = mips_get_tp ();
2970 tmp1 = mips_unspec_offset_high (NULL, tp, loc, SYMBOL_TPREL);
2971 dest = gen_rtx_LO_SUM (Pmode, tmp1,
2972 mips_unspec_address (loc, SYMBOL_TPREL));
2981 /* If X is not a valid address for mode MODE, force it into a register. */
2984 mips_force_address (rtx x, enum machine_mode mode)
2986 if (!mips_legitimate_address_p (mode, x, false))
2987 x = force_reg (Pmode, x);
2991 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
2992 be legitimized in a way that the generic machinery might not expect,
2993 return a new address, otherwise return NULL. MODE is the mode of
2994 the memory being accessed. */
2997 mips_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
2998 enum machine_mode mode)
3001 HOST_WIDE_INT offset;
3003 if (mips_tls_symbol_p (x))
3004 return mips_legitimize_tls_address (x);
3006 /* See if the address can split into a high part and a LO_SUM. */
3007 if (mips_split_symbol (NULL, x, mode, &addr))
3008 return mips_force_address (addr, mode);
3010 /* Handle BASE + OFFSET using mips_add_offset. */
3011 mips_split_plus (x, &base, &offset);
3014 if (!mips_valid_base_register_p (base, mode, false))
3015 base = copy_to_mode_reg (Pmode, base);
3016 addr = mips_add_offset (NULL, base, offset);
3017 return mips_force_address (addr, mode);
3023 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
3026 mips_move_integer (rtx temp, rtx dest, unsigned HOST_WIDE_INT value)
3028 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
3029 enum machine_mode mode;
3030 unsigned int i, num_ops;
3033 mode = GET_MODE (dest);
3034 num_ops = mips_build_integer (codes, value);
3036 /* Apply each binary operation to X. Invariant: X is a legitimate
3037 source operand for a SET pattern. */
3038 x = GEN_INT (codes[0].value);
3039 for (i = 1; i < num_ops; i++)
3041 if (!can_create_pseudo_p ())
3043 emit_insn (gen_rtx_SET (VOIDmode, temp, x));
3047 x = force_reg (mode, x);
3048 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
3051 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
3054 /* Subroutine of mips_legitimize_move. Move constant SRC into register
3055 DEST given that SRC satisfies immediate_operand but doesn't satisfy
3059 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
3063 /* Split moves of big integers into smaller pieces. */
3064 if (splittable_const_int_operand (src, mode))
3066 mips_move_integer (dest, dest, INTVAL (src));
3070 /* Split moves of symbolic constants into high/low pairs. */
3071 if (mips_split_symbol (dest, src, MAX_MACHINE_MODE, &src))
3073 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
3077 /* Generate the appropriate access sequences for TLS symbols. */
3078 if (mips_tls_symbol_p (src))
3080 mips_emit_move (dest, mips_legitimize_tls_address (src));
3084 /* If we have (const (plus symbol offset)), and that expression cannot
3085 be forced into memory, load the symbol first and add in the offset.
3086 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
3087 forced into memory, as it usually produces better code. */
3088 split_const (src, &base, &offset);
3089 if (offset != const0_rtx
3090 && (targetm.cannot_force_const_mem (src)
3091 || (!TARGET_MIPS16 && can_create_pseudo_p ())))
3093 base = mips_force_temporary (dest, base);
3094 mips_emit_move (dest, mips_add_offset (NULL, base, INTVAL (offset)));
3098 src = force_const_mem (mode, src);
3100 /* When using explicit relocs, constant pool references are sometimes
3101 not legitimate addresses. */
3102 mips_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0));
3103 mips_emit_move (dest, src);
3106 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
3107 sequence that is valid. */
3110 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
3112 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
3114 mips_emit_move (dest, force_reg (mode, src));
3118 /* We need to deal with constants that would be legitimate
3119 immediate_operands but aren't legitimate move_operands. */
3120 if (CONSTANT_P (src) && !move_operand (src, mode))
3122 mips_legitimize_const_move (mode, dest, src);
3123 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
3129 /* Return true if value X in context CONTEXT is a small-data address
3130 that can be rewritten as a LO_SUM. */
3133 mips_rewrite_small_data_p (rtx x, enum mips_symbol_context context)
3135 enum mips_symbol_type symbol_type;
3137 return (mips_lo_relocs[SYMBOL_GP_RELATIVE]
3138 && !mips_split_p[SYMBOL_GP_RELATIVE]
3139 && mips_symbolic_constant_p (x, context, &symbol_type)
3140 && symbol_type == SYMBOL_GP_RELATIVE);
3143 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
3144 containing MEM, or null if none. */
3147 mips_small_data_pattern_1 (rtx *loc, void *data)
3149 enum mips_symbol_context context;
3151 if (GET_CODE (*loc) == LO_SUM)
3156 if (for_each_rtx (&XEXP (*loc, 0), mips_small_data_pattern_1, *loc))
3161 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3162 return mips_rewrite_small_data_p (*loc, context);
3165 /* Return true if OP refers to small data symbols directly, not through
3169 mips_small_data_pattern_p (rtx op)
3171 return for_each_rtx (&op, mips_small_data_pattern_1, NULL);
3174 /* A for_each_rtx callback, used by mips_rewrite_small_data.
3175 DATA is the containing MEM, or null if none. */
3178 mips_rewrite_small_data_1 (rtx *loc, void *data)
3180 enum mips_symbol_context context;
3184 for_each_rtx (&XEXP (*loc, 0), mips_rewrite_small_data_1, *loc);
3188 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3189 if (mips_rewrite_small_data_p (*loc, context))
3190 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
3192 if (GET_CODE (*loc) == LO_SUM)
3198 /* Rewrite instruction pattern PATTERN so that it refers to small data
3199 using explicit relocations. */
3202 mips_rewrite_small_data (rtx pattern)
3204 pattern = copy_insn (pattern);
3205 for_each_rtx (&pattern, mips_rewrite_small_data_1, NULL);
3209 /* We need a lot of little routines to check the range of MIPS16 immediate
3213 m16_check_op (rtx op, int low, int high, int mask)
3215 return (CONST_INT_P (op)
3216 && IN_RANGE (INTVAL (op), low, high)
3217 && (INTVAL (op) & mask) == 0);
3221 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3223 return m16_check_op (op, 0x1, 0x8, 0);
3227 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3229 return m16_check_op (op, -0x8, 0x7, 0);
3233 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3235 return m16_check_op (op, -0x7, 0x8, 0);
3239 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3241 return m16_check_op (op, -0x10, 0xf, 0);
3245 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3247 return m16_check_op (op, -0xf, 0x10, 0);
3251 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3253 return m16_check_op (op, -0x10 << 2, 0xf << 2, 3);
3257 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3259 return m16_check_op (op, -0xf << 2, 0x10 << 2, 3);
3263 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3265 return m16_check_op (op, -0x80, 0x7f, 0);
3269 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3271 return m16_check_op (op, -0x7f, 0x80, 0);
3275 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3277 return m16_check_op (op, 0x0, 0xff, 0);
3281 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3283 return m16_check_op (op, -0xff, 0x0, 0);
3287 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3289 return m16_check_op (op, -0x1, 0xfe, 0);
3293 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3295 return m16_check_op (op, 0x0, 0xff << 2, 3);
3299 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3301 return m16_check_op (op, -0xff << 2, 0x0, 3);
3305 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3307 return m16_check_op (op, -0x80 << 3, 0x7f << 3, 7);
3311 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3313 return m16_check_op (op, -0x7f << 3, 0x80 << 3, 7);
3316 /* The cost of loading values from the constant pool. It should be
3317 larger than the cost of any constant we want to synthesize inline. */
3318 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3320 /* Return the cost of X when used as an operand to the MIPS16 instruction
3321 that implements CODE. Return -1 if there is no such instruction, or if
3322 X is not a valid immediate operand for it. */
3325 mips16_constant_cost (int code, HOST_WIDE_INT x)
3332 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3333 other shifts are extended. The shift patterns truncate the shift
3334 count to the right size, so there are no out-of-range values. */
3335 if (IN_RANGE (x, 1, 8))
3337 return COSTS_N_INSNS (1);
3340 if (IN_RANGE (x, -128, 127))
3342 if (SMALL_OPERAND (x))
3343 return COSTS_N_INSNS (1);
3347 /* Like LE, but reject the always-true case. */
3351 /* We add 1 to the immediate and use SLT. */
3354 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3357 if (IN_RANGE (x, 0, 255))
3359 if (SMALL_OPERAND_UNSIGNED (x))
3360 return COSTS_N_INSNS (1);
3365 /* Equality comparisons with 0 are cheap. */
3375 /* Return true if there is a non-MIPS16 instruction that implements CODE
3376 and if that instruction accepts X as an immediate operand. */
3379 mips_immediate_operand_p (int code, HOST_WIDE_INT x)
3386 /* All shift counts are truncated to a valid constant. */
3391 /* Likewise rotates, if the target supports rotates at all. */
3397 /* These instructions take 16-bit unsigned immediates. */
3398 return SMALL_OPERAND_UNSIGNED (x);
3403 /* These instructions take 16-bit signed immediates. */
3404 return SMALL_OPERAND (x);
3410 /* The "immediate" forms of these instructions are really
3411 implemented as comparisons with register 0. */
3416 /* Likewise, meaning that the only valid immediate operand is 1. */
3420 /* We add 1 to the immediate and use SLT. */
3421 return SMALL_OPERAND (x + 1);
3424 /* Likewise SLTU, but reject the always-true case. */
3425 return SMALL_OPERAND (x + 1) && x + 1 != 0;
3429 /* The bit position and size are immediate operands. */
3430 return ISA_HAS_EXT_INS;
3433 /* By default assume that $0 can be used for 0. */
3438 /* Return the cost of binary operation X, given that the instruction
3439 sequence for a word-sized or smaller operation has cost SINGLE_COST
3440 and that the sequence of a double-word operation has cost DOUBLE_COST.
3441 If SPEED is true, optimize for speed otherwise optimize for size. */
3444 mips_binary_cost (rtx x, int single_cost, int double_cost, bool speed)
3448 if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2)
3453 + rtx_cost (XEXP (x, 0), SET, speed)
3454 + rtx_cost (XEXP (x, 1), GET_CODE (x), speed));
3457 /* Return the cost of floating-point multiplications of mode MODE. */
3460 mips_fp_mult_cost (enum machine_mode mode)
3462 return mode == DFmode ? mips_cost->fp_mult_df : mips_cost->fp_mult_sf;
3465 /* Return the cost of floating-point divisions of mode MODE. */
3468 mips_fp_div_cost (enum machine_mode mode)
3470 return mode == DFmode ? mips_cost->fp_div_df : mips_cost->fp_div_sf;
3473 /* Return the cost of sign-extending OP to mode MODE, not including the
3474 cost of OP itself. */
3477 mips_sign_extend_cost (enum machine_mode mode, rtx op)
3480 /* Extended loads are as cheap as unextended ones. */
3483 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3484 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3487 if (ISA_HAS_SEB_SEH || GENERATE_MIPS16E)
3488 /* We can use SEB or SEH. */
3489 return COSTS_N_INSNS (1);
3491 /* We need to use a shift left and a shift right. */
3492 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3495 /* Return the cost of zero-extending OP to mode MODE, not including the
3496 cost of OP itself. */
3499 mips_zero_extend_cost (enum machine_mode mode, rtx op)
3502 /* Extended loads are as cheap as unextended ones. */
3505 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3506 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3507 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3509 if (GENERATE_MIPS16E)
3510 /* We can use ZEB or ZEH. */
3511 return COSTS_N_INSNS (1);
3514 /* We need to load 0xff or 0xffff into a register and use AND. */
3515 return COSTS_N_INSNS (GET_MODE (op) == QImode ? 2 : 3);
3517 /* We can use ANDI. */
3518 return COSTS_N_INSNS (1);
3521 /* Implement TARGET_RTX_COSTS. */
3524 mips_rtx_costs (rtx x, int code, int outer_code, int *total, bool speed)
3526 enum machine_mode mode = GET_MODE (x);
3527 bool float_mode_p = FLOAT_MODE_P (mode);
3531 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3532 appear in the instruction stream, and the cost of a comparison is
3533 really the cost of the branch or scc condition. At the time of
3534 writing, GCC only uses an explicit outer COMPARE code when optabs
3535 is testing whether a constant is expensive enough to force into a
3536 register. We want optabs to pass such constants through the MIPS
3537 expanders instead, so make all constants very cheap here. */
3538 if (outer_code == COMPARE)
3540 gcc_assert (CONSTANT_P (x));
3548 /* Treat *clear_upper32-style ANDs as having zero cost in the
3549 second operand. The cost is entirely in the first operand.
3551 ??? This is needed because we would otherwise try to CSE
3552 the constant operand. Although that's the right thing for
3553 instructions that continue to be a register operation throughout
3554 compilation, it is disastrous for instructions that could
3555 later be converted into a memory operation. */
3557 && outer_code == AND
3558 && UINTVAL (x) == 0xffffffff)
3566 cost = mips16_constant_cost (outer_code, INTVAL (x));
3575 /* When not optimizing for size, we care more about the cost
3576 of hot code, and hot code is often in a loop. If a constant
3577 operand needs to be forced into a register, we will often be
3578 able to hoist the constant load out of the loop, so the load
3579 should not contribute to the cost. */
3580 if (speed || mips_immediate_operand_p (outer_code, INTVAL (x)))
3592 if (force_to_mem_operand (x, VOIDmode))
3594 *total = COSTS_N_INSNS (1);
3597 cost = mips_const_insns (x);
3600 /* If the constant is likely to be stored in a GPR, SETs of
3601 single-insn constants are as cheap as register sets; we
3602 never want to CSE them.
3604 Don't reduce the cost of storing a floating-point zero in
3605 FPRs. If we have a zero in an FPR for other reasons, we
3606 can get better cfg-cleanup and delayed-branch results by
3607 using it consistently, rather than using $0 sometimes and
3608 an FPR at other times. Also, moves between floating-point
3609 registers are sometimes cheaper than (D)MTC1 $0. */
3611 && outer_code == SET
3612 && !(float_mode_p && TARGET_HARD_FLOAT))
3614 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3615 want to CSE the constant itself. It is usually better to
3616 have N copies of the last operation in the sequence and one
3617 shared copy of the other operations. (Note that this is
3618 not true for MIPS16 code, where the final operation in the
3619 sequence is often an extended instruction.)
3621 Also, if we have a CONST_INT, we don't know whether it is
3622 for a word or doubleword operation, so we cannot rely on
3623 the result of mips_build_integer. */
3624 else if (!TARGET_MIPS16
3625 && (outer_code == SET || mode == VOIDmode))
3627 *total = COSTS_N_INSNS (cost);
3630 /* The value will need to be fetched from the constant pool. */
3631 *total = CONSTANT_POOL_COST;
3635 /* If the address is legitimate, return the number of
3636 instructions it needs. */
3638 cost = mips_address_insns (addr, mode, true);
3641 *total = COSTS_N_INSNS (cost + 1);
3644 /* Check for a scaled indexed address. */
3645 if (mips_lwxs_address_p (addr))
3647 *total = COSTS_N_INSNS (2);
3650 /* Otherwise use the default handling. */
3654 *total = COSTS_N_INSNS (6);
3658 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1);
3662 /* Check for a *clear_upper32 pattern and treat it like a zero
3663 extension. See the pattern's comment for details. */
3666 && CONST_INT_P (XEXP (x, 1))
3667 && UINTVAL (XEXP (x, 1)) == 0xffffffff)
3669 *total = (mips_zero_extend_cost (mode, XEXP (x, 0))
3670 + rtx_cost (XEXP (x, 0), SET, speed));
3677 /* Double-word operations use two single-word operations. */
3678 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (2),
3687 if (CONSTANT_P (XEXP (x, 1)))
3688 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3691 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (12),
3697 *total = mips_cost->fp_add;
3699 *total = COSTS_N_INSNS (4);
3703 /* Low-part immediates need an extended MIPS16 instruction. */
3704 *total = (COSTS_N_INSNS (TARGET_MIPS16 ? 2 : 1)
3705 + rtx_cost (XEXP (x, 0), SET, speed));
3720 /* Branch comparisons have VOIDmode, so use the first operand's
3722 mode = GET_MODE (XEXP (x, 0));
3723 if (FLOAT_MODE_P (mode))
3725 *total = mips_cost->fp_add;
3728 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3734 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3735 && TARGET_FUSED_MADD
3736 && !HONOR_NANS (mode)
3737 && !HONOR_SIGNED_ZEROS (mode))
3739 /* See if we can use NMADD or NMSUB. See mips.md for the
3740 associated patterns. */
3741 rtx op0 = XEXP (x, 0);
3742 rtx op1 = XEXP (x, 1);
3743 if (GET_CODE (op0) == MULT && GET_CODE (XEXP (op0, 0)) == NEG)
3745 *total = (mips_fp_mult_cost (mode)
3746 + rtx_cost (XEXP (XEXP (op0, 0), 0), SET, speed)
3747 + rtx_cost (XEXP (op0, 1), SET, speed)
3748 + rtx_cost (op1, SET, speed));
3751 if (GET_CODE (op1) == MULT)
3753 *total = (mips_fp_mult_cost (mode)
3754 + rtx_cost (op0, SET, speed)
3755 + rtx_cost (XEXP (op1, 0), SET, speed)
3756 + rtx_cost (XEXP (op1, 1), SET, speed));
3765 /* If this is part of a MADD or MSUB, treat the PLUS as
3768 && TARGET_FUSED_MADD
3769 && GET_CODE (XEXP (x, 0)) == MULT)
3772 *total = mips_cost->fp_add;
3776 /* Double-word operations require three single-word operations and
3777 an SLTU. The MIPS16 version then needs to move the result of
3778 the SLTU from $24 to a MIPS16 register. */
3779 *total = mips_binary_cost (x, COSTS_N_INSNS (1),
3780 COSTS_N_INSNS (TARGET_MIPS16 ? 5 : 4),
3786 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3787 && TARGET_FUSED_MADD
3788 && !HONOR_NANS (mode)
3789 && HONOR_SIGNED_ZEROS (mode))
3791 /* See if we can use NMADD or NMSUB. See mips.md for the
3792 associated patterns. */
3793 rtx op = XEXP (x, 0);
3794 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
3795 && GET_CODE (XEXP (op, 0)) == MULT)
3797 *total = (mips_fp_mult_cost (mode)
3798 + rtx_cost (XEXP (XEXP (op, 0), 0), SET, speed)
3799 + rtx_cost (XEXP (XEXP (op, 0), 1), SET, speed)
3800 + rtx_cost (XEXP (op, 1), SET, speed));
3806 *total = mips_cost->fp_add;
3808 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1);
3813 *total = mips_fp_mult_cost (mode);
3814 else if (mode == DImode && !TARGET_64BIT)
3815 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
3816 where the mulsidi3 always includes an MFHI and an MFLO. */
3818 ? mips_cost->int_mult_si * 3 + 6
3819 : COSTS_N_INSNS (ISA_HAS_MUL3 ? 7 : 9));
3821 *total = (ISA_HAS_MUL3 ? 1 : 2);
3822 else if (mode == DImode)
3823 *total = mips_cost->int_mult_di;
3825 *total = mips_cost->int_mult_si;
3829 /* Check for a reciprocal. */
3832 && flag_unsafe_math_optimizations
3833 && XEXP (x, 0) == CONST1_RTX (mode))
3835 if (outer_code == SQRT || GET_CODE (XEXP (x, 1)) == SQRT)
3836 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
3837 division as being free. */
3838 *total = rtx_cost (XEXP (x, 1), SET, speed);
3840 *total = (mips_fp_div_cost (mode)
3841 + rtx_cost (XEXP (x, 1), SET, speed));
3850 *total = mips_fp_div_cost (mode);
3859 /* It is our responsibility to make division by a power of 2
3860 as cheap as 2 register additions if we want the division
3861 expanders to be used for such operations; see the setting
3862 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
3863 should always produce shorter code than using
3864 expand_sdiv2_pow2. */
3866 && CONST_INT_P (XEXP (x, 1))
3867 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
3869 *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), SET, speed);
3872 *total = COSTS_N_INSNS (mips_idiv_insns ());
3874 else if (mode == DImode)
3875 *total = mips_cost->int_div_di;
3877 *total = mips_cost->int_div_si;
3881 *total = mips_sign_extend_cost (mode, XEXP (x, 0));
3885 *total = mips_zero_extend_cost (mode, XEXP (x, 0));
3889 case UNSIGNED_FLOAT:
3892 case FLOAT_TRUNCATE:
3893 *total = mips_cost->fp_add;
3901 /* Implement TARGET_ADDRESS_COST. */
3904 mips_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED)
3906 return mips_address_insns (addr, SImode, false);
3909 /* Information about a single instruction in a multi-instruction
3911 struct mips_multi_member {
3912 /* True if this is a label, false if it is code. */
3915 /* The output_asm_insn format of the instruction. */
3918 /* The operands to the instruction. */
3919 rtx operands[MAX_RECOG_OPERANDS];
3921 typedef struct mips_multi_member mips_multi_member;
3923 /* Vector definitions for the above. */
3924 DEF_VEC_O(mips_multi_member);
3925 DEF_VEC_ALLOC_O(mips_multi_member, heap);
3927 /* The instructions that make up the current multi-insn sequence. */
3928 static VEC (mips_multi_member, heap) *mips_multi_members;
3930 /* How many instructions (as opposed to labels) are in the current
3931 multi-insn sequence. */
3932 static unsigned int mips_multi_num_insns;
3934 /* Start a new multi-insn sequence. */
3937 mips_multi_start (void)
3939 VEC_truncate (mips_multi_member, mips_multi_members, 0);
3940 mips_multi_num_insns = 0;
3943 /* Add a new, uninitialized member to the current multi-insn sequence. */
3945 static struct mips_multi_member *
3946 mips_multi_add (void)
3948 return VEC_safe_push (mips_multi_member, heap, mips_multi_members, 0);
3951 /* Add a normal insn with the given asm format to the current multi-insn
3952 sequence. The other arguments are a null-terminated list of operands. */
3955 mips_multi_add_insn (const char *format, ...)
3957 struct mips_multi_member *member;
3962 member = mips_multi_add ();
3963 member->is_label_p = false;
3964 member->format = format;
3965 va_start (ap, format);
3967 while ((op = va_arg (ap, rtx)))
3968 member->operands[i++] = op;
3970 mips_multi_num_insns++;
3973 /* Add the given label definition to the current multi-insn sequence.
3974 The definition should include the colon. */
3977 mips_multi_add_label (const char *label)
3979 struct mips_multi_member *member;
3981 member = mips_multi_add ();
3982 member->is_label_p = true;
3983 member->format = label;
3986 /* Return the index of the last member of the current multi-insn sequence. */
3989 mips_multi_last_index (void)
3991 return VEC_length (mips_multi_member, mips_multi_members) - 1;
3994 /* Add a copy of an existing instruction to the current multi-insn
3995 sequence. I is the index of the instruction that should be copied. */
3998 mips_multi_copy_insn (unsigned int i)
4000 struct mips_multi_member *member;
4002 member = mips_multi_add ();
4003 memcpy (member, VEC_index (mips_multi_member, mips_multi_members, i),
4005 gcc_assert (!member->is_label_p);
4008 /* Change the operand of an existing instruction in the current
4009 multi-insn sequence. I is the index of the instruction,
4010 OP is the index of the operand, and X is the new value. */
4013 mips_multi_set_operand (unsigned int i, unsigned int op, rtx x)
4015 VEC_index (mips_multi_member, mips_multi_members, i)->operands[op] = x;
4018 /* Write out the asm code for the current multi-insn sequence. */
4021 mips_multi_write (void)
4023 struct mips_multi_member *member;
4026 FOR_EACH_VEC_ELT (mips_multi_member, mips_multi_members, i, member)
4027 if (member->is_label_p)
4028 fprintf (asm_out_file, "%s\n", member->format);
4030 output_asm_insn (member->format, member->operands);
4033 /* Return one word of double-word value OP, taking into account the fixed
4034 endianness of certain registers. HIGH_P is true to select the high part,
4035 false to select the low part. */
4038 mips_subword (rtx op, bool high_p)
4040 unsigned int byte, offset;
4041 enum machine_mode mode;
4043 mode = GET_MODE (op);
4044 if (mode == VOIDmode)
4045 mode = TARGET_64BIT ? TImode : DImode;
4047 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
4048 byte = UNITS_PER_WORD;
4052 if (FP_REG_RTX_P (op))
4054 /* Paired FPRs are always ordered little-endian. */
4055 offset = (UNITS_PER_WORD < UNITS_PER_HWFPVALUE ? high_p : byte != 0);
4056 return gen_rtx_REG (word_mode, REGNO (op) + offset);
4060 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
4062 return simplify_gen_subreg (word_mode, op, mode, byte);
4065 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
4068 mips_split_64bit_move_p (rtx dest, rtx src)
4073 /* FPR-to-FPR moves can be done in a single instruction, if they're
4075 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
4078 /* Check for floating-point loads and stores. */
4079 if (ISA_HAS_LDC1_SDC1)
4081 if (FP_REG_RTX_P (dest) && MEM_P (src))
4083 if (FP_REG_RTX_P (src) && MEM_P (dest))
4089 /* Split a doubleword move from SRC to DEST. On 32-bit targets,
4090 this function handles 64-bit moves for which mips_split_64bit_move_p
4091 holds. For 64-bit targets, this function handles 128-bit moves. */
4094 mips_split_doubleword_move (rtx dest, rtx src)
4098 if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src))
4100 if (!TARGET_64BIT && GET_MODE (dest) == DImode)
4101 emit_insn (gen_move_doubleword_fprdi (dest, src));
4102 else if (!TARGET_64BIT && GET_MODE (dest) == DFmode)
4103 emit_insn (gen_move_doubleword_fprdf (dest, src));
4104 else if (!TARGET_64BIT && GET_MODE (dest) == V2SFmode)
4105 emit_insn (gen_move_doubleword_fprv2sf (dest, src));
4106 else if (!TARGET_64BIT && GET_MODE (dest) == V2SImode)
4107 emit_insn (gen_move_doubleword_fprv2si (dest, src));
4108 else if (!TARGET_64BIT && GET_MODE (dest) == V4HImode)
4109 emit_insn (gen_move_doubleword_fprv4hi (dest, src));
4110 else if (!TARGET_64BIT && GET_MODE (dest) == V8QImode)
4111 emit_insn (gen_move_doubleword_fprv8qi (dest, src));
4112 else if (TARGET_64BIT && GET_MODE (dest) == TFmode)
4113 emit_insn (gen_move_doubleword_fprtf (dest, src));
4117 else if (REG_P (dest) && REGNO (dest) == MD_REG_FIRST)
4119 low_dest = mips_subword (dest, false);
4120 mips_emit_move (low_dest, mips_subword (src, false));
4122 emit_insn (gen_mthidi_ti (dest, mips_subword (src, true), low_dest));
4124 emit_insn (gen_mthisi_di (dest, mips_subword (src, true), low_dest));
4126 else if (REG_P (src) && REGNO (src) == MD_REG_FIRST)
4128 mips_emit_move (mips_subword (dest, false), mips_subword (src, false));
4130 emit_insn (gen_mfhidi_ti (mips_subword (dest, true), src));
4132 emit_insn (gen_mfhisi_di (mips_subword (dest, true), src));
4136 /* The operation can be split into two normal moves. Decide in
4137 which order to do them. */
4138 low_dest = mips_subword (dest, false);
4139 if (REG_P (low_dest)
4140 && reg_overlap_mentioned_p (low_dest, src))
4142 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4143 mips_emit_move (low_dest, mips_subword (src, false));
4147 mips_emit_move (low_dest, mips_subword (src, false));
4148 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4153 /* Return the appropriate instructions to move SRC into DEST. Assume
4154 that SRC is operand 1 and DEST is operand 0. */
4157 mips_output_move (rtx dest, rtx src)
4159 enum rtx_code dest_code, src_code;
4160 enum machine_mode mode;
4161 enum mips_symbol_type symbol_type;
4164 dest_code = GET_CODE (dest);
4165 src_code = GET_CODE (src);
4166 mode = GET_MODE (dest);
4167 dbl_p = (GET_MODE_SIZE (mode) == 8);
4169 if (dbl_p && mips_split_64bit_move_p (dest, src))
4172 if ((src_code == REG && GP_REG_P (REGNO (src)))
4173 || (!TARGET_MIPS16 && src == CONST0_RTX (mode)))
4175 if (dest_code == REG)
4177 if (GP_REG_P (REGNO (dest)))
4178 return "move\t%0,%z1";
4180 /* Moves to HI are handled by special .md insns. */
4181 if (REGNO (dest) == LO_REGNUM)
4184 if (DSP_ACC_REG_P (REGNO (dest)))
4186 static char retval[] = "mt__\t%z1,%q0";
4188 retval[2] = reg_names[REGNO (dest)][4];
4189 retval[3] = reg_names[REGNO (dest)][5];
4193 if (FP_REG_P (REGNO (dest)))
4194 return dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
4196 if (ALL_COP_REG_P (REGNO (dest)))
4198 static char retval[] = "dmtc_\t%z1,%0";
4200 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4201 return dbl_p ? retval : retval + 1;
4204 if (dest_code == MEM)
4205 switch (GET_MODE_SIZE (mode))
4207 case 1: return "sb\t%z1,%0";
4208 case 2: return "sh\t%z1,%0";
4209 case 4: return "sw\t%z1,%0";
4210 case 8: return "sd\t%z1,%0";
4213 if (dest_code == REG && GP_REG_P (REGNO (dest)))
4215 if (src_code == REG)
4217 /* Moves from HI are handled by special .md insns. */
4218 if (REGNO (src) == LO_REGNUM)
4220 /* When generating VR4120 or VR4130 code, we use MACC and
4221 DMACC instead of MFLO. This avoids both the normal
4222 MIPS III HI/LO hazards and the errata related to
4225 return dbl_p ? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
4229 if (DSP_ACC_REG_P (REGNO (src)))
4231 static char retval[] = "mf__\t%0,%q1";
4233 retval[2] = reg_names[REGNO (src)][4];
4234 retval[3] = reg_names[REGNO (src)][5];
4238 if (FP_REG_P (REGNO (src)))
4239 return dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
4241 if (ALL_COP_REG_P (REGNO (src)))
4243 static char retval[] = "dmfc_\t%0,%1";
4245 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4246 return dbl_p ? retval : retval + 1;
4249 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
4250 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
4253 if (src_code == MEM)
4254 switch (GET_MODE_SIZE (mode))
4256 case 1: return "lbu\t%0,%1";
4257 case 2: return "lhu\t%0,%1";
4258 case 4: return "lw\t%0,%1";
4259 case 8: return "ld\t%0,%1";
4262 if (src_code == CONST_INT)
4264 /* Don't use the X format for the operand itself, because that
4265 will give out-of-range numbers for 64-bit hosts and 32-bit
4268 return "li\t%0,%1\t\t\t# %X1";
4270 if (SMALL_OPERAND_UNSIGNED (INTVAL (src)))
4273 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src)))
4277 if (src_code == HIGH)
4278 return TARGET_MIPS16 ? "#" : "lui\t%0,%h1";
4280 if (CONST_GP_P (src))
4281 return "move\t%0,%1";
4283 if (mips_symbolic_constant_p (src, SYMBOL_CONTEXT_LEA, &symbol_type)
4284 && mips_lo_relocs[symbol_type] != 0)
4286 /* A signed 16-bit constant formed by applying a relocation
4287 operator to a symbolic address. */
4288 gcc_assert (!mips_split_p[symbol_type]);
4289 return "li\t%0,%R1";
4292 if (symbolic_operand (src, VOIDmode))
4294 gcc_assert (TARGET_MIPS16
4295 ? TARGET_MIPS16_TEXT_LOADS
4296 : !TARGET_EXPLICIT_RELOCS);
4297 return dbl_p ? "dla\t%0,%1" : "la\t%0,%1";
4300 if (src_code == REG && FP_REG_P (REGNO (src)))
4302 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4304 if (GET_MODE (dest) == V2SFmode)
4305 return "mov.ps\t%0,%1";
4307 return dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1";
4310 if (dest_code == MEM)
4311 return dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0";
4313 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4315 if (src_code == MEM)
4316 return dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1";
4318 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
4320 static char retval[] = "l_c_\t%0,%1";
4322 retval[1] = (dbl_p ? 'd' : 'w');
4323 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4326 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
4328 static char retval[] = "s_c_\t%1,%0";
4330 retval[1] = (dbl_p ? 'd' : 'w');
4331 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4337 /* Return true if CMP1 is a suitable second operand for integer ordering
4338 test CODE. See also the *sCC patterns in mips.md. */
4341 mips_int_order_operand_ok_p (enum rtx_code code, rtx cmp1)
4347 return reg_or_0_operand (cmp1, VOIDmode);
4351 return !TARGET_MIPS16 && cmp1 == const1_rtx;
4355 return arith_operand (cmp1, VOIDmode);
4358 return sle_operand (cmp1, VOIDmode);
4361 return sleu_operand (cmp1, VOIDmode);
4368 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4369 integer ordering test *CODE, or if an equivalent combination can
4370 be formed by adjusting *CODE and *CMP1. When returning true, update
4371 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4375 mips_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1,
4376 enum machine_mode mode)
4378 HOST_WIDE_INT plus_one;
4380 if (mips_int_order_operand_ok_p (*code, *cmp1))
4383 if (CONST_INT_P (*cmp1))
4387 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4388 if (INTVAL (*cmp1) < plus_one)
4391 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4397 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4401 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4412 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4413 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4414 is nonnull, it's OK to set TARGET to the inverse of the result and
4415 flip *INVERT_PTR instead. */
4418 mips_emit_int_order_test (enum rtx_code code, bool *invert_ptr,
4419 rtx target, rtx cmp0, rtx cmp1)
4421 enum machine_mode mode;
4423 /* First see if there is a MIPS instruction that can do this operation.
4424 If not, try doing the same for the inverse operation. If that also
4425 fails, force CMP1 into a register and try again. */
4426 mode = GET_MODE (cmp0);
4427 if (mips_canonicalize_int_order_test (&code, &cmp1, mode))
4428 mips_emit_binary (code, target, cmp0, cmp1);
4431 enum rtx_code inv_code = reverse_condition (code);
4432 if (!mips_canonicalize_int_order_test (&inv_code, &cmp1, mode))
4434 cmp1 = force_reg (mode, cmp1);
4435 mips_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1);
4437 else if (invert_ptr == 0)
4441 inv_target = mips_force_binary (GET_MODE (target),
4442 inv_code, cmp0, cmp1);
4443 mips_emit_binary (XOR, target, inv_target, const1_rtx);
4447 *invert_ptr = !*invert_ptr;
4448 mips_emit_binary (inv_code, target, cmp0, cmp1);
4453 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4454 The register will have the same mode as CMP0. */
4457 mips_zero_if_equal (rtx cmp0, rtx cmp1)
4459 if (cmp1 == const0_rtx)
4462 if (uns_arith_operand (cmp1, VOIDmode))
4463 return expand_binop (GET_MODE (cmp0), xor_optab,
4464 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4466 return expand_binop (GET_MODE (cmp0), sub_optab,
4467 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4470 /* Convert *CODE into a code that can be used in a floating-point
4471 scc instruction (C.cond.fmt). Return true if the values of
4472 the condition code registers will be inverted, with 0 indicating
4473 that the condition holds. */
4476 mips_reversed_fp_cond (enum rtx_code *code)
4483 *code = reverse_condition_maybe_unordered (*code);
4491 /* Convert a comparison into something that can be used in a branch or
4492 conditional move. On entry, *OP0 and *OP1 are the values being
4493 compared and *CODE is the code used to compare them.
4495 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
4496 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
4497 otherwise any standard branch condition can be used. The standard branch
4500 - EQ or NE between two registers.
4501 - any comparison between a register and zero. */
4504 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
4509 if (GET_MODE_CLASS (GET_MODE (*op0)) == MODE_INT)
4511 if (!need_eq_ne_p && *op1 == const0_rtx)
4513 else if (*code == EQ || *code == NE)
4517 *op0 = mips_zero_if_equal (cmp_op0, cmp_op1);
4521 *op1 = force_reg (GET_MODE (cmp_op0), cmp_op1);
4525 /* The comparison needs a separate scc instruction. Store the
4526 result of the scc in *OP0 and compare it against zero. */
4527 bool invert = false;
4528 *op0 = gen_reg_rtx (GET_MODE (cmp_op0));
4529 mips_emit_int_order_test (*code, &invert, *op0, cmp_op0, cmp_op1);
4530 *code = (invert ? EQ : NE);
4534 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0)))
4536 *op0 = gen_rtx_REG (CCDSPmode, CCDSP_CC_REGNUM);
4537 mips_emit_binary (*code, *op0, cmp_op0, cmp_op1);
4543 enum rtx_code cmp_code;
4545 /* Floating-point tests use a separate C.cond.fmt comparison to
4546 set a condition code register. The branch or conditional move
4547 will then compare that register against zero.
4549 Set CMP_CODE to the code of the comparison instruction and
4550 *CODE to the code that the branch or move should use. */
4552 *code = mips_reversed_fp_cond (&cmp_code) ? EQ : NE;
4554 ? gen_reg_rtx (CCmode)
4555 : gen_rtx_REG (CCmode, FPSW_REGNUM));
4557 mips_emit_binary (cmp_code, *op0, cmp_op0, cmp_op1);
4561 /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2]
4562 and OPERAND[3]. Store the result in OPERANDS[0].
4564 On 64-bit targets, the mode of the comparison and target will always be
4565 SImode, thus possibly narrower than that of the comparison's operands. */
4568 mips_expand_scc (rtx operands[])
4570 rtx target = operands[0];
4571 enum rtx_code code = GET_CODE (operands[1]);
4572 rtx op0 = operands[2];
4573 rtx op1 = operands[3];
4575 gcc_assert (GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT);
4577 if (code == EQ || code == NE)
4580 && reg_imm10_operand (op1, GET_MODE (op1)))
4581 mips_emit_binary (code, target, op0, op1);
4584 rtx zie = mips_zero_if_equal (op0, op1);
4585 mips_emit_binary (code, target, zie, const0_rtx);
4589 mips_emit_int_order_test (code, 0, target, op0, op1);
4592 /* Compare OPERANDS[1] with OPERANDS[2] using comparison code
4593 CODE and jump to OPERANDS[3] if the condition holds. */
4596 mips_expand_conditional_branch (rtx *operands)
4598 enum rtx_code code = GET_CODE (operands[0]);
4599 rtx op0 = operands[1];
4600 rtx op1 = operands[2];
4603 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
4604 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
4605 emit_jump_insn (gen_condjump (condition, operands[3]));
4610 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
4611 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
4614 mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
4615 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
4620 reversed_p = mips_reversed_fp_cond (&cond);
4621 cmp_result = gen_reg_rtx (CCV2mode);
4622 emit_insn (gen_scc_ps (cmp_result,
4623 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
4625 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
4628 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
4632 /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0]
4633 if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
4636 mips_expand_conditional_move (rtx *operands)
4639 enum rtx_code code = GET_CODE (operands[1]);
4640 rtx op0 = XEXP (operands[1], 0);
4641 rtx op1 = XEXP (operands[1], 1);
4643 mips_emit_compare (&code, &op0, &op1, true);
4644 cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
4645 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
4646 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), cond,
4647 operands[2], operands[3])));
4650 /* Perform the comparison in COMPARISON, then trap if the condition holds. */
4653 mips_expand_conditional_trap (rtx comparison)
4656 enum machine_mode mode;
4659 /* MIPS conditional trap instructions don't have GT or LE flavors,
4660 so we must swap the operands and convert to LT and GE respectively. */
4661 code = GET_CODE (comparison);
4668 code = swap_condition (code);
4669 op0 = XEXP (comparison, 1);
4670 op1 = XEXP (comparison, 0);
4674 op0 = XEXP (comparison, 0);
4675 op1 = XEXP (comparison, 1);
4679 mode = GET_MODE (XEXP (comparison, 0));
4680 op0 = force_reg (mode, op0);
4681 if (!arith_operand (op1, mode))
4682 op1 = force_reg (mode, op1);
4684 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
4685 gen_rtx_fmt_ee (code, mode, op0, op1),
4689 /* Initialize *CUM for a call to a function of type FNTYPE. */
4692 mips_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype)
4694 memset (cum, 0, sizeof (*cum));
4695 cum->prototype = (fntype && prototype_p (fntype));
4696 cum->gp_reg_found = (cum->prototype && stdarg_p (fntype));
4699 /* Fill INFO with information about a single argument. CUM is the
4700 cumulative state for earlier arguments. MODE is the mode of this
4701 argument and TYPE is its type (if known). NAMED is true if this
4702 is a named (fixed) argument rather than a variable one. */
4705 mips_get_arg_info (struct mips_arg_info *info, const CUMULATIVE_ARGS *cum,
4706 enum machine_mode mode, const_tree type, bool named)
4708 bool doubleword_aligned_p;
4709 unsigned int num_bytes, num_words, max_regs;
4711 /* Work out the size of the argument. */
4712 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
4713 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4715 /* Decide whether it should go in a floating-point register, assuming
4716 one is free. Later code checks for availability.
4718 The checks against UNITS_PER_FPVALUE handle the soft-float and
4719 single-float cases. */
4723 /* The EABI conventions have traditionally been defined in terms
4724 of TYPE_MODE, regardless of the actual type. */
4725 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
4726 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4727 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4732 /* Only leading floating-point scalars are passed in
4733 floating-point registers. We also handle vector floats the same
4734 say, which is OK because they are not covered by the standard ABI. */
4735 info->fpr_p = (!cum->gp_reg_found
4736 && cum->arg_number < 2
4738 || SCALAR_FLOAT_TYPE_P (type)
4739 || VECTOR_FLOAT_TYPE_P (type))
4740 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4741 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4742 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4747 /* Scalar, complex and vector floating-point types are passed in
4748 floating-point registers, as long as this is a named rather
4749 than a variable argument. */
4750 info->fpr_p = (named
4751 && (type == 0 || FLOAT_TYPE_P (type))
4752 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4753 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4754 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4755 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
4757 /* ??? According to the ABI documentation, the real and imaginary
4758 parts of complex floats should be passed in individual registers.
4759 The real and imaginary parts of stack arguments are supposed
4760 to be contiguous and there should be an extra word of padding
4763 This has two problems. First, it makes it impossible to use a
4764 single "void *" va_list type, since register and stack arguments
4765 are passed differently. (At the time of writing, MIPSpro cannot
4766 handle complex float varargs correctly.) Second, it's unclear
4767 what should happen when there is only one register free.
4769 For now, we assume that named complex floats should go into FPRs
4770 if there are two FPRs free, otherwise they should be passed in the
4771 same way as a struct containing two floats. */
4773 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4774 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
4776 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
4777 info->fpr_p = false;
4787 /* See whether the argument has doubleword alignment. */
4788 doubleword_aligned_p = (mips_function_arg_boundary (mode, type)
4791 /* Set REG_OFFSET to the register count we're interested in.
4792 The EABI allocates the floating-point registers separately,
4793 but the other ABIs allocate them like integer registers. */
4794 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
4798 /* Advance to an even register if the argument is doubleword-aligned. */
4799 if (doubleword_aligned_p)
4800 info->reg_offset += info->reg_offset & 1;
4802 /* Work out the offset of a stack argument. */
4803 info->stack_offset = cum->stack_words;
4804 if (doubleword_aligned_p)
4805 info->stack_offset += info->stack_offset & 1;
4807 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
4809 /* Partition the argument between registers and stack. */
4810 info->reg_words = MIN (num_words, max_regs);
4811 info->stack_words = num_words - info->reg_words;
4814 /* INFO describes a register argument that has the normal format for the
4815 argument's mode. Return the register it uses, assuming that FPRs are
4816 available if HARD_FLOAT_P. */
4819 mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p)
4821 if (!info->fpr_p || !hard_float_p)
4822 return GP_ARG_FIRST + info->reg_offset;
4823 else if (mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info->reg_offset > 0)
4824 /* In o32, the second argument is always passed in $f14
4825 for TARGET_DOUBLE_FLOAT, regardless of whether the
4826 first argument was a word or doubleword. */
4827 return FP_ARG_FIRST + 2;
4829 return FP_ARG_FIRST + info->reg_offset;
4832 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
4835 mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
4837 return !TARGET_OLDABI;
4840 /* Implement TARGET_FUNCTION_ARG. */
4843 mips_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4844 const_tree type, bool named)
4846 struct mips_arg_info info;
4848 /* We will be called with a mode of VOIDmode after the last argument
4849 has been seen. Whatever we return will be passed to the call expander.
4850 If we need a MIPS16 fp_code, return a REG with the code stored as
4852 if (mode == VOIDmode)
4854 if (TARGET_MIPS16 && cum->fp_code != 0)
4855 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
4860 mips_get_arg_info (&info, cum, mode, type, named);
4862 /* Return straight away if the whole argument is passed on the stack. */
4863 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
4866 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
4867 contains a double in its entirety, then that 64-bit chunk is passed
4868 in a floating-point register. */
4870 && TARGET_HARD_FLOAT
4873 && TREE_CODE (type) == RECORD_TYPE
4874 && TYPE_SIZE_UNIT (type)
4875 && host_integerp (TYPE_SIZE_UNIT (type), 1))
4879 /* First check to see if there is any such field. */
4880 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
4881 if (TREE_CODE (field) == FIELD_DECL
4882 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
4883 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
4884 && host_integerp (bit_position (field), 0)
4885 && int_bit_position (field) % BITS_PER_WORD == 0)
4890 /* Now handle the special case by returning a PARALLEL
4891 indicating where each 64-bit chunk goes. INFO.REG_WORDS
4892 chunks are passed in registers. */
4894 HOST_WIDE_INT bitpos;
4897 /* assign_parms checks the mode of ENTRY_PARM, so we must
4898 use the actual mode here. */
4899 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
4902 field = TYPE_FIELDS (type);
4903 for (i = 0; i < info.reg_words; i++)
4907 for (; field; field = DECL_CHAIN (field))
4908 if (TREE_CODE (field) == FIELD_DECL
4909 && int_bit_position (field) >= bitpos)
4913 && int_bit_position (field) == bitpos
4914 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
4915 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
4916 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
4918 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
4921 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4922 GEN_INT (bitpos / BITS_PER_UNIT));
4924 bitpos += BITS_PER_WORD;
4930 /* Handle the n32/n64 conventions for passing complex floating-point
4931 arguments in FPR pairs. The real part goes in the lower register
4932 and the imaginary part goes in the upper register. */
4935 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4938 enum machine_mode inner;
4941 inner = GET_MODE_INNER (mode);
4942 regno = FP_ARG_FIRST + info.reg_offset;
4943 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
4945 /* Real part in registers, imaginary part on stack. */
4946 gcc_assert (info.stack_words == info.reg_words);
4947 return gen_rtx_REG (inner, regno);
4951 gcc_assert (info.stack_words == 0);
4952 real = gen_rtx_EXPR_LIST (VOIDmode,
4953 gen_rtx_REG (inner, regno),
4955 imag = gen_rtx_EXPR_LIST (VOIDmode,
4957 regno + info.reg_words / 2),
4958 GEN_INT (GET_MODE_SIZE (inner)));
4959 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
4963 return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT));
4966 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
4969 mips_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4970 const_tree type, bool named)
4972 struct mips_arg_info info;
4974 mips_get_arg_info (&info, cum, mode, type, named);
4977 cum->gp_reg_found = true;
4979 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
4980 an explanation of what this code does. It assumes that we're using
4981 either the o32 or the o64 ABI, both of which pass at most 2 arguments
4983 if (cum->arg_number < 2 && info.fpr_p)
4984 cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2);
4986 /* Advance the register count. This has the effect of setting
4987 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
4988 argument required us to skip the final GPR and pass the whole
4989 argument on the stack. */
4990 if (mips_abi != ABI_EABI || !info.fpr_p)
4991 cum->num_gprs = info.reg_offset + info.reg_words;
4992 else if (info.reg_words > 0)
4993 cum->num_fprs += MAX_FPRS_PER_FMT;
4995 /* Advance the stack word count. */
4996 if (info.stack_words > 0)
4997 cum->stack_words = info.stack_offset + info.stack_words;
5002 /* Implement TARGET_ARG_PARTIAL_BYTES. */
5005 mips_arg_partial_bytes (CUMULATIVE_ARGS *cum,
5006 enum machine_mode mode, tree type, bool named)
5008 struct mips_arg_info info;
5010 mips_get_arg_info (&info, cum, mode, type, named);
5011 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
5014 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
5015 least PARM_BOUNDARY bits of alignment, but will be given anything up
5016 to STACK_BOUNDARY bits if the type requires it. */
5019 mips_function_arg_boundary (enum machine_mode mode, const_tree type)
5021 unsigned int alignment;
5023 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
5024 if (alignment < PARM_BOUNDARY)
5025 alignment = PARM_BOUNDARY;
5026 if (alignment > STACK_BOUNDARY)
5027 alignment = STACK_BOUNDARY;
5031 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
5032 upward rather than downward. In other words, return true if the
5033 first byte of the stack slot has useful data, false if the last
5037 mips_pad_arg_upward (enum machine_mode mode, const_tree type)
5039 /* On little-endian targets, the first byte of every stack argument
5040 is passed in the first byte of the stack slot. */
5041 if (!BYTES_BIG_ENDIAN)
5044 /* Otherwise, integral types are padded downward: the last byte of a
5045 stack argument is passed in the last byte of the stack slot. */
5047 ? (INTEGRAL_TYPE_P (type)
5048 || POINTER_TYPE_P (type)
5049 || FIXED_POINT_TYPE_P (type))
5050 : (SCALAR_INT_MODE_P (mode)
5051 || ALL_SCALAR_FIXED_POINT_MODE_P (mode)))
5054 /* Big-endian o64 pads floating-point arguments downward. */
5055 if (mips_abi == ABI_O64)
5056 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
5059 /* Other types are padded upward for o32, o64, n32 and n64. */
5060 if (mips_abi != ABI_EABI)
5063 /* Arguments smaller than a stack slot are padded downward. */
5064 if (mode != BLKmode)
5065 return GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY;
5067 return int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT);
5070 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
5071 if the least significant byte of the register has useful data. Return
5072 the opposite if the most significant byte does. */
5075 mips_pad_reg_upward (enum machine_mode mode, tree type)
5077 /* No shifting is required for floating-point arguments. */
5078 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
5079 return !BYTES_BIG_ENDIAN;
5081 /* Otherwise, apply the same padding to register arguments as we do
5082 to stack arguments. */
5083 return mips_pad_arg_upward (mode, type);
5086 /* Return nonzero when an argument must be passed by reference. */
5089 mips_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5090 enum machine_mode mode, const_tree type,
5091 bool named ATTRIBUTE_UNUSED)
5093 if (mips_abi == ABI_EABI)
5097 /* ??? How should SCmode be handled? */
5098 if (mode == DImode || mode == DFmode
5099 || mode == DQmode || mode == UDQmode
5100 || mode == DAmode || mode == UDAmode)
5103 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
5104 return size == -1 || size > UNITS_PER_WORD;
5108 /* If we have a variable-sized parameter, we have no choice. */
5109 return targetm.calls.must_pass_in_stack (mode, type);
5113 /* Implement TARGET_CALLEE_COPIES. */
5116 mips_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5117 enum machine_mode mode ATTRIBUTE_UNUSED,
5118 const_tree type ATTRIBUTE_UNUSED, bool named)
5120 return mips_abi == ABI_EABI && named;
5123 /* See whether VALTYPE is a record whose fields should be returned in
5124 floating-point registers. If so, return the number of fields and
5125 list them in FIELDS (which should have two elements). Return 0
5128 For n32 & n64, a structure with one or two fields is returned in
5129 floating-point registers as long as every field has a floating-point
5133 mips_fpr_return_fields (const_tree valtype, tree *fields)
5141 if (TREE_CODE (valtype) != RECORD_TYPE)
5145 for (field = TYPE_FIELDS (valtype); field != 0; field = DECL_CHAIN (field))
5147 if (TREE_CODE (field) != FIELD_DECL)
5150 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)))
5156 fields[i++] = field;
5161 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
5162 a value in the most significant part of $2/$3 if:
5164 - the target is big-endian;
5166 - the value has a structure or union type (we generalize this to
5167 cover aggregates from other languages too); and
5169 - the structure is not returned in floating-point registers. */
5172 mips_return_in_msb (const_tree valtype)
5176 return (TARGET_NEWABI
5177 && TARGET_BIG_ENDIAN
5178 && AGGREGATE_TYPE_P (valtype)
5179 && mips_fpr_return_fields (valtype, fields) == 0);
5182 /* Return true if the function return value MODE will get returned in a
5183 floating-point register. */
5186 mips_return_mode_in_fpr_p (enum machine_mode mode)
5188 return ((GET_MODE_CLASS (mode) == MODE_FLOAT
5189 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT
5190 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5191 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE);
5194 /* Return the representation of an FPR return register when the
5195 value being returned in FP_RETURN has mode VALUE_MODE and the
5196 return type itself has mode TYPE_MODE. On NewABI targets,
5197 the two modes may be different for structures like:
5199 struct __attribute__((packed)) foo { float f; }
5201 where we return the SFmode value of "f" in FP_RETURN, but where
5202 the structure itself has mode BLKmode. */
5205 mips_return_fpr_single (enum machine_mode type_mode,
5206 enum machine_mode value_mode)
5210 x = gen_rtx_REG (value_mode, FP_RETURN);
5211 if (type_mode != value_mode)
5213 x = gen_rtx_EXPR_LIST (VOIDmode, x, const0_rtx);
5214 x = gen_rtx_PARALLEL (type_mode, gen_rtvec (1, x));
5219 /* Return a composite value in a pair of floating-point registers.
5220 MODE1 and OFFSET1 are the mode and byte offset for the first value,
5221 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
5224 For n32 & n64, $f0 always holds the first value and $f2 the second.
5225 Otherwise the values are packed together as closely as possible. */
5228 mips_return_fpr_pair (enum machine_mode mode,
5229 enum machine_mode mode1, HOST_WIDE_INT offset1,
5230 enum machine_mode mode2, HOST_WIDE_INT offset2)
5234 inc = (TARGET_NEWABI ? 2 : MAX_FPRS_PER_FMT);
5235 return gen_rtx_PARALLEL
5238 gen_rtx_EXPR_LIST (VOIDmode,
5239 gen_rtx_REG (mode1, FP_RETURN),
5241 gen_rtx_EXPR_LIST (VOIDmode,
5242 gen_rtx_REG (mode2, FP_RETURN + inc),
5243 GEN_INT (offset2))));
5247 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
5248 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
5249 VALTYPE is null and MODE is the mode of the return value. */
5252 mips_function_value (const_tree valtype, const_tree func, enum machine_mode mode)
5259 mode = TYPE_MODE (valtype);
5260 unsigned_p = TYPE_UNSIGNED (valtype);
5262 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
5263 return values, promote the mode here too. */
5264 mode = promote_function_mode (valtype, mode, &unsigned_p, func, 1);
5266 /* Handle structures whose fields are returned in $f0/$f2. */
5267 switch (mips_fpr_return_fields (valtype, fields))
5270 return mips_return_fpr_single (mode,
5271 TYPE_MODE (TREE_TYPE (fields[0])));
5274 return mips_return_fpr_pair (mode,
5275 TYPE_MODE (TREE_TYPE (fields[0])),
5276 int_byte_position (fields[0]),
5277 TYPE_MODE (TREE_TYPE (fields[1])),
5278 int_byte_position (fields[1]));
5281 /* If a value is passed in the most significant part of a register, see
5282 whether we have to round the mode up to a whole number of words. */
5283 if (mips_return_in_msb (valtype))
5285 HOST_WIDE_INT size = int_size_in_bytes (valtype);
5286 if (size % UNITS_PER_WORD != 0)
5288 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
5289 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
5293 /* For EABI, the class of return register depends entirely on MODE.
5294 For example, "struct { some_type x; }" and "union { some_type x; }"
5295 are returned in the same way as a bare "some_type" would be.
5296 Other ABIs only use FPRs for scalar, complex or vector types. */
5297 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
5298 return gen_rtx_REG (mode, GP_RETURN);
5303 /* Handle long doubles for n32 & n64. */
5305 return mips_return_fpr_pair (mode,
5307 DImode, GET_MODE_SIZE (mode) / 2);
5309 if (mips_return_mode_in_fpr_p (mode))
5311 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5312 return mips_return_fpr_pair (mode,
5313 GET_MODE_INNER (mode), 0,
5314 GET_MODE_INNER (mode),
5315 GET_MODE_SIZE (mode) / 2);
5317 return gen_rtx_REG (mode, FP_RETURN);
5321 return gen_rtx_REG (mode, GP_RETURN);
5324 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
5325 all BLKmode objects are returned in memory. Under the n32, n64
5326 and embedded ABIs, small structures are returned in a register.
5327 Objects with varying size must still be returned in memory, of
5331 mips_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
5333 return (TARGET_OLDABI
5334 ? TYPE_MODE (type) == BLKmode
5335 : !IN_RANGE (int_size_in_bytes (type), 0, 2 * UNITS_PER_WORD));
5338 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
5341 mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5342 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5345 CUMULATIVE_ARGS local_cum;
5346 int gp_saved, fp_saved;
5348 /* The caller has advanced CUM up to, but not beyond, the last named
5349 argument. Advance a local copy of CUM past the last "real" named
5350 argument, to find out how many registers are left over. */
5352 mips_function_arg_advance (&local_cum, mode, type, true);
5354 /* Found out how many registers we need to save. */
5355 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
5356 fp_saved = (EABI_FLOAT_VARARGS_P
5357 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
5366 ptr = plus_constant (virtual_incoming_args_rtx,
5367 REG_PARM_STACK_SPACE (cfun->decl)
5368 - gp_saved * UNITS_PER_WORD);
5369 mem = gen_frame_mem (BLKmode, ptr);
5370 set_mem_alias_set (mem, get_varargs_alias_set ());
5372 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
5377 /* We can't use move_block_from_reg, because it will use
5379 enum machine_mode mode;
5382 /* Set OFF to the offset from virtual_incoming_args_rtx of
5383 the first float register. The FP save area lies below
5384 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
5385 off = (-gp_saved * UNITS_PER_WORD) & -UNITS_PER_FPVALUE;
5386 off -= fp_saved * UNITS_PER_FPREG;
5388 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
5390 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS;
5391 i += MAX_FPRS_PER_FMT)
5395 ptr = plus_constant (virtual_incoming_args_rtx, off);
5396 mem = gen_frame_mem (mode, ptr);
5397 set_mem_alias_set (mem, get_varargs_alias_set ());
5398 mips_emit_move (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
5399 off += UNITS_PER_HWFPVALUE;
5403 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
5404 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
5405 + fp_saved * UNITS_PER_FPREG);
5408 /* Implement TARGET_BUILTIN_VA_LIST. */
5411 mips_build_builtin_va_list (void)
5413 if (EABI_FLOAT_VARARGS_P)
5415 /* We keep 3 pointers, and two offsets.
5417 Two pointers are to the overflow area, which starts at the CFA.
5418 One of these is constant, for addressing into the GPR save area
5419 below it. The other is advanced up the stack through the
5422 The third pointer is to the bottom of the GPR save area.
5423 Since the FPR save area is just below it, we can address
5424 FPR slots off this pointer.
5426 We also keep two one-byte offsets, which are to be subtracted
5427 from the constant pointers to yield addresses in the GPR and
5428 FPR save areas. These are downcounted as float or non-float
5429 arguments are used, and when they get to zero, the argument
5430 must be obtained from the overflow region. */
5431 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
5434 record = lang_hooks.types.make_type (RECORD_TYPE);
5436 f_ovfl = build_decl (BUILTINS_LOCATION,
5437 FIELD_DECL, get_identifier ("__overflow_argptr"),
5439 f_gtop = build_decl (BUILTINS_LOCATION,
5440 FIELD_DECL, get_identifier ("__gpr_top"),
5442 f_ftop = build_decl (BUILTINS_LOCATION,
5443 FIELD_DECL, get_identifier ("__fpr_top"),
5445 f_goff = build_decl (BUILTINS_LOCATION,
5446 FIELD_DECL, get_identifier ("__gpr_offset"),
5447 unsigned_char_type_node);
5448 f_foff = build_decl (BUILTINS_LOCATION,
5449 FIELD_DECL, get_identifier ("__fpr_offset"),
5450 unsigned_char_type_node);
5451 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
5452 warn on every user file. */
5453 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
5454 array = build_array_type (unsigned_char_type_node,
5455 build_index_type (index));
5456 f_res = build_decl (BUILTINS_LOCATION,
5457 FIELD_DECL, get_identifier ("__reserved"), array);
5459 DECL_FIELD_CONTEXT (f_ovfl) = record;
5460 DECL_FIELD_CONTEXT (f_gtop) = record;
5461 DECL_FIELD_CONTEXT (f_ftop) = record;
5462 DECL_FIELD_CONTEXT (f_goff) = record;
5463 DECL_FIELD_CONTEXT (f_foff) = record;
5464 DECL_FIELD_CONTEXT (f_res) = record;
5466 TYPE_FIELDS (record) = f_ovfl;
5467 DECL_CHAIN (f_ovfl) = f_gtop;
5468 DECL_CHAIN (f_gtop) = f_ftop;
5469 DECL_CHAIN (f_ftop) = f_goff;
5470 DECL_CHAIN (f_goff) = f_foff;
5471 DECL_CHAIN (f_foff) = f_res;
5473 layout_type (record);
5476 else if (TARGET_IRIX6)
5477 /* On IRIX 6, this type is 'char *'. */
5478 return build_pointer_type (char_type_node);
5480 /* Otherwise, we use 'void *'. */
5481 return ptr_type_node;
5484 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
5487 mips_va_start (tree valist, rtx nextarg)
5489 if (EABI_FLOAT_VARARGS_P)
5491 const CUMULATIVE_ARGS *cum;
5492 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5493 tree ovfl, gtop, ftop, goff, foff;
5495 int gpr_save_area_size;
5496 int fpr_save_area_size;
5499 cum = &crtl->args.info;
5501 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
5503 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
5505 f_ovfl = TYPE_FIELDS (va_list_type_node);
5506 f_gtop = DECL_CHAIN (f_ovfl);
5507 f_ftop = DECL_CHAIN (f_gtop);
5508 f_goff = DECL_CHAIN (f_ftop);
5509 f_foff = DECL_CHAIN (f_goff);
5511 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5513 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
5515 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
5517 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
5519 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
5522 /* Emit code to initialize OVFL, which points to the next varargs
5523 stack argument. CUM->STACK_WORDS gives the number of stack
5524 words used by named arguments. */
5525 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
5526 if (cum->stack_words > 0)
5527 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl), t,
5528 size_int (cum->stack_words * UNITS_PER_WORD));
5529 t = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
5530 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5532 /* Emit code to initialize GTOP, the top of the GPR save area. */
5533 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
5534 t = build2 (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
5535 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5537 /* Emit code to initialize FTOP, the top of the FPR save area.
5538 This address is gpr_save_area_bytes below GTOP, rounded
5539 down to the next fp-aligned boundary. */
5540 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
5541 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
5542 fpr_offset &= -UNITS_PER_FPVALUE;
5544 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ftop), t,
5545 size_int (-fpr_offset));
5546 t = build2 (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
5547 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5549 /* Emit code to initialize GOFF, the offset from GTOP of the
5550 next GPR argument. */
5551 t = build2 (MODIFY_EXPR, TREE_TYPE (goff), goff,
5552 build_int_cst (TREE_TYPE (goff), gpr_save_area_size));
5553 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5555 /* Likewise emit code to initialize FOFF, the offset from FTOP
5556 of the next FPR argument. */
5557 t = build2 (MODIFY_EXPR, TREE_TYPE (foff), foff,
5558 build_int_cst (TREE_TYPE (foff), fpr_save_area_size));
5559 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5563 nextarg = plus_constant (nextarg, -cfun->machine->varargs_size);
5564 std_expand_builtin_va_start (valist, nextarg);
5568 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
5571 mips_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
5577 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
5579 type = build_pointer_type (type);
5581 if (!EABI_FLOAT_VARARGS_P)
5582 addr = std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5585 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5586 tree ovfl, top, off, align;
5587 HOST_WIDE_INT size, rsize, osize;
5590 f_ovfl = TYPE_FIELDS (va_list_type_node);
5591 f_gtop = DECL_CHAIN (f_ovfl);
5592 f_ftop = DECL_CHAIN (f_gtop);
5593 f_goff = DECL_CHAIN (f_ftop);
5594 f_foff = DECL_CHAIN (f_goff);
5598 TOP be the top of the GPR or FPR save area;
5599 OFF be the offset from TOP of the next register;
5600 ADDR_RTX be the address of the argument;
5601 SIZE be the number of bytes in the argument type;
5602 RSIZE be the number of bytes used to store the argument
5603 when it's in the register save area; and
5604 OSIZE be the number of bytes used to store it when it's
5605 in the stack overflow area.
5607 The code we want is:
5609 1: off &= -rsize; // round down
5612 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
5617 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
5618 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
5622 [1] and [9] can sometimes be optimized away. */
5624 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5626 size = int_size_in_bytes (type);
5628 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
5629 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
5631 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop),
5632 unshare_expr (valist), f_ftop, NULL_TREE);
5633 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff),
5634 unshare_expr (valist), f_foff, NULL_TREE);
5636 /* When va_start saves FPR arguments to the stack, each slot
5637 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
5638 argument's precision. */
5639 rsize = UNITS_PER_HWFPVALUE;
5641 /* Overflow arguments are padded to UNITS_PER_WORD bytes
5642 (= PARM_BOUNDARY bits). This can be different from RSIZE
5645 (1) On 32-bit targets when TYPE is a structure such as:
5647 struct s { float f; };
5649 Such structures are passed in paired FPRs, so RSIZE
5650 will be 8 bytes. However, the structure only takes
5651 up 4 bytes of memory, so OSIZE will only be 4.
5653 (2) In combinations such as -mgp64 -msingle-float
5654 -fshort-double. Doubles passed in registers will then take
5655 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
5656 stack take up UNITS_PER_WORD bytes. */
5657 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
5661 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop),
5662 unshare_expr (valist), f_gtop, NULL_TREE);
5663 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff),
5664 unshare_expr (valist), f_goff, NULL_TREE);
5665 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
5666 if (rsize > UNITS_PER_WORD)
5668 /* [1] Emit code for: off &= -rsize. */
5669 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), unshare_expr (off),
5670 build_int_cst (TREE_TYPE (off), -rsize));
5671 gimplify_assign (unshare_expr (off), t, pre_p);
5676 /* [2] Emit code to branch if off == 0. */
5677 t = build2 (NE_EXPR, boolean_type_node, off,
5678 build_int_cst (TREE_TYPE (off), 0));
5679 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
5681 /* [5] Emit code for: off -= rsize. We do this as a form of
5682 post-decrement not available to C. */
5683 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
5684 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
5686 /* [4] Emit code for:
5687 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
5688 t = fold_convert (sizetype, t);
5689 t = fold_build1 (NEGATE_EXPR, sizetype, t);
5690 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (top), top, t);
5691 if (BYTES_BIG_ENDIAN && rsize > size)
5693 u = size_int (rsize - size);
5694 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
5696 COND_EXPR_THEN (addr) = t;
5698 if (osize > UNITS_PER_WORD)
5700 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
5701 u = size_int (osize - 1);
5702 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl),
5703 unshare_expr (ovfl), u);
5704 t = fold_convert (sizetype, t);
5705 u = size_int (-osize);
5706 t = build2 (BIT_AND_EXPR, sizetype, t, u);
5707 t = fold_convert (TREE_TYPE (ovfl), t);
5708 align = build2 (MODIFY_EXPR, TREE_TYPE (ovfl),
5709 unshare_expr (ovfl), t);
5714 /* [10, 11] Emit code for:
5715 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
5717 u = fold_convert (TREE_TYPE (ovfl), build_int_cst (NULL_TREE, osize));
5718 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
5719 if (BYTES_BIG_ENDIAN && osize > size)
5721 u = size_int (osize - size);
5722 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
5725 /* String [9] and [10, 11] together. */
5727 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
5728 COND_EXPR_ELSE (addr) = t;
5730 addr = fold_convert (build_pointer_type (type), addr);
5731 addr = build_va_arg_indirect_ref (addr);
5735 addr = build_va_arg_indirect_ref (addr);
5740 /* Start a definition of function NAME. MIPS16_P indicates whether the
5741 function contains MIPS16 code. */
5744 mips_start_function_definition (const char *name, bool mips16_p)
5747 fprintf (asm_out_file, "\t.set\tmips16\n");
5749 fprintf (asm_out_file, "\t.set\tnomips16\n");
5751 if (!flag_inhibit_size_directive)
5753 fputs ("\t.ent\t", asm_out_file);
5754 assemble_name (asm_out_file, name);
5755 fputs ("\n", asm_out_file);
5758 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, name, "function");
5760 /* Start the definition proper. */
5761 assemble_name (asm_out_file, name);
5762 fputs (":\n", asm_out_file);
5765 /* End a function definition started by mips_start_function_definition. */
5768 mips_end_function_definition (const char *name)
5770 if (!flag_inhibit_size_directive)
5772 fputs ("\t.end\t", asm_out_file);
5773 assemble_name (asm_out_file, name);
5774 fputs ("\n", asm_out_file);
5778 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
5781 mips_ok_for_lazy_binding_p (rtx x)
5783 return (TARGET_USE_GOT
5784 && GET_CODE (x) == SYMBOL_REF
5785 && !SYMBOL_REF_BIND_NOW_P (x)
5786 && !mips_symbol_binds_local_p (x));
5789 /* Load function address ADDR into register DEST. TYPE is as for
5790 mips_expand_call. Return true if we used an explicit lazy-binding
5794 mips_load_call_address (enum mips_call_type type, rtx dest, rtx addr)
5796 /* If we're generating PIC, and this call is to a global function,
5797 try to allow its address to be resolved lazily. This isn't
5798 possible for sibcalls when $gp is call-saved because the value
5799 of $gp on entry to the stub would be our caller's gp, not ours. */
5800 if (TARGET_EXPLICIT_RELOCS
5801 && !(type == MIPS_CALL_SIBCALL && TARGET_CALL_SAVED_GP)
5802 && mips_ok_for_lazy_binding_p (addr))
5804 addr = mips_got_load (dest, addr, SYMBOL_GOTOFF_CALL);
5805 emit_insn (gen_rtx_SET (VOIDmode, dest, addr));
5810 mips_emit_move (dest, addr);
5815 /* Each locally-defined hard-float MIPS16 function has a local symbol
5816 associated with it. This hash table maps the function symbol (FUNC)
5817 to the local symbol (LOCAL). */
5818 struct GTY(()) mips16_local_alias {
5822 static GTY ((param_is (struct mips16_local_alias))) htab_t mips16_local_aliases;
5824 /* Hash table callbacks for mips16_local_aliases. */
5827 mips16_local_aliases_hash (const void *entry)
5829 const struct mips16_local_alias *alias;
5831 alias = (const struct mips16_local_alias *) entry;
5832 return htab_hash_string (XSTR (alias->func, 0));
5836 mips16_local_aliases_eq (const void *entry1, const void *entry2)
5838 const struct mips16_local_alias *alias1, *alias2;
5840 alias1 = (const struct mips16_local_alias *) entry1;
5841 alias2 = (const struct mips16_local_alias *) entry2;
5842 return rtx_equal_p (alias1->func, alias2->func);
5845 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
5846 Return a local alias for it, creating a new one if necessary. */
5849 mips16_local_alias (rtx func)
5851 struct mips16_local_alias *alias, tmp_alias;
5854 /* Create the hash table if this is the first call. */
5855 if (mips16_local_aliases == NULL)
5856 mips16_local_aliases = htab_create_ggc (37, mips16_local_aliases_hash,
5857 mips16_local_aliases_eq, NULL);
5859 /* Look up the function symbol, creating a new entry if need be. */
5860 tmp_alias.func = func;
5861 slot = htab_find_slot (mips16_local_aliases, &tmp_alias, INSERT);
5862 gcc_assert (slot != NULL);
5864 alias = (struct mips16_local_alias *) *slot;
5867 const char *func_name, *local_name;
5870 /* Create a new SYMBOL_REF for the local symbol. The choice of
5871 __fn_local_* is based on the __fn_stub_* names that we've
5872 traditionally used for the non-MIPS16 stub. */
5873 func_name = targetm.strip_name_encoding (XSTR (func, 0));
5874 local_name = ACONCAT (("__fn_local_", func_name, NULL));
5875 local = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (local_name));
5876 SYMBOL_REF_FLAGS (local) = SYMBOL_REF_FLAGS (func) | SYMBOL_FLAG_LOCAL;
5878 /* Create a new structure to represent the mapping. */
5879 alias = ggc_alloc_mips16_local_alias ();
5881 alias->local = local;
5884 return alias->local;
5887 /* A chained list of functions for which mips16_build_call_stub has already
5888 generated a stub. NAME is the name of the function and FP_RET_P is true
5889 if the function returns a value in floating-point registers. */
5890 struct mips16_stub {
5891 struct mips16_stub *next;
5895 static struct mips16_stub *mips16_stubs;
5897 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
5900 mips16_stub_function (const char *name)
5904 x = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
5905 SYMBOL_REF_FLAGS (x) |= (SYMBOL_FLAG_EXTERNAL | SYMBOL_FLAG_FUNCTION);
5909 /* Return the two-character string that identifies floating-point
5910 return mode MODE in the name of a MIPS16 function stub. */
5913 mips16_call_stub_mode_suffix (enum machine_mode mode)
5917 else if (mode == DFmode)
5919 else if (mode == SCmode)
5921 else if (mode == DCmode)
5923 else if (mode == V2SFmode)
5929 /* Write instructions to move a 32-bit value between general register
5930 GPREG and floating-point register FPREG. DIRECTION is 't' to move
5931 from GPREG to FPREG and 'f' to move in the opposite direction. */
5934 mips_output_32bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
5936 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5937 reg_names[gpreg], reg_names[fpreg]);
5940 /* Likewise for 64-bit values. */
5943 mips_output_64bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
5946 fprintf (asm_out_file, "\tdm%cc1\t%s,%s\n", direction,
5947 reg_names[gpreg], reg_names[fpreg]);
5948 else if (TARGET_FLOAT64)
5950 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5951 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
5952 fprintf (asm_out_file, "\tm%chc1\t%s,%s\n", direction,
5953 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg]);
5957 /* Move the least-significant word. */
5958 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5959 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
5960 /* ...then the most significant word. */
5961 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5962 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg + 1]);
5966 /* Write out code to move floating-point arguments into or out of
5967 general registers. FP_CODE is the code describing which arguments
5968 are present (see the comment above the definition of CUMULATIVE_ARGS
5969 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
5972 mips_output_args_xfer (int fp_code, char direction)
5974 unsigned int gparg, fparg, f;
5975 CUMULATIVE_ARGS cum;
5977 /* This code only works for o32 and o64. */
5978 gcc_assert (TARGET_OLDABI);
5980 mips_init_cumulative_args (&cum, NULL);
5982 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
5984 enum machine_mode mode;
5985 struct mips_arg_info info;
5989 else if ((f & 3) == 2)
5994 mips_get_arg_info (&info, &cum, mode, NULL, true);
5995 gparg = mips_arg_regno (&info, false);
5996 fparg = mips_arg_regno (&info, true);
5999 mips_output_32bit_xfer (direction, gparg, fparg);
6001 mips_output_64bit_xfer (direction, gparg, fparg);
6003 mips_function_arg_advance (&cum, mode, NULL, true);
6007 /* Write a MIPS16 stub for the current function. This stub is used
6008 for functions which take arguments in the floating-point registers.
6009 It is normal-mode code that moves the floating-point arguments
6010 into the general registers and then jumps to the MIPS16 code. */
6013 mips16_build_function_stub (void)
6015 const char *fnname, *alias_name, *separator;
6016 char *secname, *stubname;
6021 /* Create the name of the stub, and its unique section. */
6022 symbol = XEXP (DECL_RTL (current_function_decl), 0);
6023 alias = mips16_local_alias (symbol);
6025 fnname = targetm.strip_name_encoding (XSTR (symbol, 0));
6026 alias_name = targetm.strip_name_encoding (XSTR (alias, 0));
6027 secname = ACONCAT ((".mips16.fn.", fnname, NULL));
6028 stubname = ACONCAT (("__fn_stub_", fnname, NULL));
6030 /* Build a decl for the stub. */
6031 stubdecl = build_decl (BUILTINS_LOCATION,
6032 FUNCTION_DECL, get_identifier (stubname),
6033 build_function_type (void_type_node, NULL_TREE));
6034 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
6035 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
6036 RESULT_DECL, NULL_TREE, void_type_node);
6038 /* Output a comment. */
6039 fprintf (asm_out_file, "\t# Stub function for %s (",
6040 current_function_name ());
6042 for (f = (unsigned int) crtl->args.info.fp_code; f != 0; f >>= 2)
6044 fprintf (asm_out_file, "%s%s", separator,
6045 (f & 3) == 1 ? "float" : "double");
6048 fprintf (asm_out_file, ")\n");
6050 /* Start the function definition. */
6051 assemble_start_function (stubdecl, stubname);
6052 mips_start_function_definition (stubname, false);
6054 /* If generating pic2 code, either set up the global pointer or
6056 if (TARGET_ABICALLS_PIC2)
6058 if (TARGET_ABSOLUTE_ABICALLS)
6059 fprintf (asm_out_file, "\t.option\tpic0\n");
6062 output_asm_insn ("%(.cpload\t%^%)", NULL);
6063 /* Emit an R_MIPS_NONE relocation to tell the linker what the
6064 target function is. Use a local GOT access when loading the
6065 symbol, to cut down on the number of unnecessary GOT entries
6066 for stubs that aren't needed. */
6067 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol);
6072 /* Load the address of the MIPS16 function into $25. Do this first so
6073 that targets with coprocessor interlocks can use an MFC1 to fill the
6075 output_asm_insn ("la\t%^,%0", &symbol);
6077 /* Move the arguments from floating-point registers to general registers. */
6078 mips_output_args_xfer (crtl->args.info.fp_code, 'f');
6080 /* Jump to the MIPS16 function. */
6081 output_asm_insn ("jr\t%^", NULL);
6083 if (TARGET_ABICALLS_PIC2 && TARGET_ABSOLUTE_ABICALLS)
6084 fprintf (asm_out_file, "\t.option\tpic2\n");
6086 mips_end_function_definition (stubname);
6088 /* If the linker needs to create a dynamic symbol for the target
6089 function, it will associate the symbol with the stub (which,
6090 unlike the target function, follows the proper calling conventions).
6091 It is therefore useful to have a local alias for the target function,
6092 so that it can still be identified as MIPS16 code. As an optimization,
6093 this symbol can also be used for indirect MIPS16 references from
6094 within this file. */
6095 ASM_OUTPUT_DEF (asm_out_file, alias_name, fnname);
6097 switch_to_section (function_section (current_function_decl));
6100 /* The current function is a MIPS16 function that returns a value in an FPR.
6101 Copy the return value from its soft-float to its hard-float location.
6102 libgcc2 has special non-MIPS16 helper functions for each case. */
6105 mips16_copy_fpr_return_value (void)
6107 rtx fn, insn, retval;
6109 enum machine_mode return_mode;
6112 return_type = DECL_RESULT (current_function_decl);
6113 return_mode = DECL_MODE (return_type);
6115 name = ACONCAT (("__mips16_ret_",
6116 mips16_call_stub_mode_suffix (return_mode),
6118 fn = mips16_stub_function (name);
6120 /* The function takes arguments in $2 (and possibly $3), so calls
6121 to it cannot be lazily bound. */
6122 SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_BIND_NOW;
6124 /* Model the call as something that takes the GPR return value as
6125 argument and returns an "updated" value. */
6126 retval = gen_rtx_REG (return_mode, GP_RETURN);
6127 insn = mips_expand_call (MIPS_CALL_EPILOGUE, retval, fn,
6128 const0_rtx, NULL_RTX, false);
6129 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), retval);
6132 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
6133 RETVAL is the location of the return value, or null if this is
6134 a "call" rather than a "call_value". ARGS_SIZE is the size of the
6135 arguments and FP_CODE is the code built by mips_function_arg;
6136 see the comment before the fp_code field in CUMULATIVE_ARGS for details.
6138 There are three alternatives:
6140 - If a stub was needed, emit the call and return the call insn itself.
6142 - If we can avoid using a stub by redirecting the call, set *FN_PTR
6143 to the new target and return null.
6145 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
6148 A stub is needed for calls to functions that, in normal mode,
6149 receive arguments in FPRs or return values in FPRs. The stub
6150 copies the arguments from their soft-float positions to their
6151 hard-float positions, calls the real function, then copies the
6152 return value from its hard-float position to its soft-float
6155 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
6156 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
6157 automatically redirects the JAL to the stub, otherwise the JAL
6158 continues to call FN directly. */
6161 mips16_build_call_stub (rtx retval, rtx *fn_ptr, rtx args_size, int fp_code)
6165 struct mips16_stub *l;
6168 /* We don't need to do anything if we aren't in MIPS16 mode, or if
6169 we were invoked with the -msoft-float option. */
6170 if (!TARGET_MIPS16 || TARGET_SOFT_FLOAT_ABI)
6173 /* Figure out whether the value might come back in a floating-point
6175 fp_ret_p = retval && mips_return_mode_in_fpr_p (GET_MODE (retval));
6177 /* We don't need to do anything if there were no floating-point
6178 arguments and the value will not be returned in a floating-point
6180 if (fp_code == 0 && !fp_ret_p)
6183 /* We don't need to do anything if this is a call to a special
6184 MIPS16 support function. */
6186 if (mips16_stub_function_p (fn))
6189 /* This code will only work for o32 and o64 abis. The other ABI's
6190 require more sophisticated support. */
6191 gcc_assert (TARGET_OLDABI);
6193 /* If we're calling via a function pointer, use one of the magic
6194 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
6195 Each stub expects the function address to arrive in register $2. */
6196 if (GET_CODE (fn) != SYMBOL_REF
6197 || !call_insn_operand (fn, VOIDmode))
6200 rtx stub_fn, insn, addr;
6203 /* If this is a locally-defined and locally-binding function,
6204 avoid the stub by calling the local alias directly. */
6205 if (mips16_local_function_p (fn))
6207 *fn_ptr = mips16_local_alias (fn);
6211 /* Create a SYMBOL_REF for the libgcc.a function. */
6213 sprintf (buf, "__mips16_call_stub_%s_%d",
6214 mips16_call_stub_mode_suffix (GET_MODE (retval)),
6217 sprintf (buf, "__mips16_call_stub_%d", fp_code);
6218 stub_fn = mips16_stub_function (buf);
6220 /* The function uses $2 as an argument, so calls to it
6221 cannot be lazily bound. */
6222 SYMBOL_REF_FLAGS (stub_fn) |= SYMBOL_FLAG_BIND_NOW;
6224 /* Load the target function into $2. */
6225 addr = gen_rtx_REG (Pmode, GP_REG_FIRST + 2);
6226 lazy_p = mips_load_call_address (MIPS_CALL_NORMAL, addr, fn);
6228 /* Emit the call. */
6229 insn = mips_expand_call (MIPS_CALL_NORMAL, retval, stub_fn,
6230 args_size, NULL_RTX, lazy_p);
6232 /* Tell GCC that this call does indeed use the value of $2. */
6233 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), addr);
6235 /* If we are handling a floating-point return value, we need to
6236 save $18 in the function prologue. Putting a note on the
6237 call will mean that df_regs_ever_live_p ($18) will be true if the
6238 call is not eliminated, and we can check that in the prologue
6241 CALL_INSN_FUNCTION_USAGE (insn) =
6242 gen_rtx_EXPR_LIST (VOIDmode,
6243 gen_rtx_CLOBBER (VOIDmode,
6244 gen_rtx_REG (word_mode, 18)),
6245 CALL_INSN_FUNCTION_USAGE (insn));
6250 /* We know the function we are going to call. If we have already
6251 built a stub, we don't need to do anything further. */
6252 fnname = targetm.strip_name_encoding (XSTR (fn, 0));
6253 for (l = mips16_stubs; l != NULL; l = l->next)
6254 if (strcmp (l->name, fnname) == 0)
6259 const char *separator;
6260 char *secname, *stubname;
6261 tree stubid, stubdecl;
6264 /* If the function does not return in FPRs, the special stub
6268 If the function does return in FPRs, the stub section is named
6269 .mips16.call.fp.FNNAME
6271 Build a decl for the stub. */
6272 secname = ACONCAT ((".mips16.call.", fp_ret_p ? "fp." : "",
6274 stubname = ACONCAT (("__call_stub_", fp_ret_p ? "fp_" : "",
6276 stubid = get_identifier (stubname);
6277 stubdecl = build_decl (BUILTINS_LOCATION,
6278 FUNCTION_DECL, stubid,
6279 build_function_type (void_type_node, NULL_TREE));
6280 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
6281 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
6282 RESULT_DECL, NULL_TREE,
6285 /* Output a comment. */
6286 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
6288 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
6292 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
6294 fprintf (asm_out_file, "%s%s", separator,
6295 (f & 3) == 1 ? "float" : "double");
6298 fprintf (asm_out_file, ")\n");
6300 /* Start the function definition. */
6301 assemble_start_function (stubdecl, stubname);
6302 mips_start_function_definition (stubname, false);
6306 /* Load the address of the MIPS16 function into $25. Do this
6307 first so that targets with coprocessor interlocks can use
6308 an MFC1 to fill the delay slot. */
6309 if (TARGET_EXPLICIT_RELOCS)
6311 output_asm_insn ("lui\t%^,%%hi(%0)", &fn);
6312 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn);
6315 output_asm_insn ("la\t%^,%0", &fn);
6318 /* Move the arguments from general registers to floating-point
6320 mips_output_args_xfer (fp_code, 't');
6324 /* Jump to the previously-loaded address. */
6325 output_asm_insn ("jr\t%^", NULL);
6329 /* Save the return address in $18 and call the non-MIPS16 function.
6330 The stub's caller knows that $18 might be clobbered, even though
6331 $18 is usually a call-saved register. */
6332 fprintf (asm_out_file, "\tmove\t%s,%s\n",
6333 reg_names[GP_REG_FIRST + 18], reg_names[RETURN_ADDR_REGNUM]);
6334 output_asm_insn (MIPS_CALL ("jal", &fn, 0, -1), &fn);
6336 /* Move the result from floating-point registers to
6337 general registers. */
6338 switch (GET_MODE (retval))
6341 mips_output_32bit_xfer ('f', GP_RETURN + TARGET_BIG_ENDIAN,
6343 ? FP_REG_FIRST + MAX_FPRS_PER_FMT
6345 mips_output_32bit_xfer ('f', GP_RETURN + TARGET_LITTLE_ENDIAN,
6346 TARGET_LITTLE_ENDIAN
6347 ? FP_REG_FIRST + MAX_FPRS_PER_FMT
6349 if (GET_MODE (retval) == SCmode && TARGET_64BIT)
6351 /* On 64-bit targets, complex floats are returned in
6352 a single GPR, such that "sd" on a suitably-aligned
6353 target would store the value correctly. */
6354 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
6355 reg_names[GP_RETURN + TARGET_BIG_ENDIAN],
6356 reg_names[GP_RETURN + TARGET_BIG_ENDIAN]);
6357 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
6358 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN],
6359 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN]);
6360 fprintf (asm_out_file, "\tdsrl\t%s,%s,32\n",
6361 reg_names[GP_RETURN + TARGET_BIG_ENDIAN],
6362 reg_names[GP_RETURN + TARGET_BIG_ENDIAN]);
6363 fprintf (asm_out_file, "\tor\t%s,%s,%s\n",
6364 reg_names[GP_RETURN],
6365 reg_names[GP_RETURN],
6366 reg_names[GP_RETURN + 1]);
6371 mips_output_32bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6375 mips_output_64bit_xfer ('f', GP_RETURN + (8 / UNITS_PER_WORD),
6376 FP_REG_FIRST + MAX_FPRS_PER_FMT);
6380 mips_output_64bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6386 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 18]);
6389 #ifdef ASM_DECLARE_FUNCTION_SIZE
6390 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
6393 mips_end_function_definition (stubname);
6395 /* Record this stub. */
6396 l = XNEW (struct mips16_stub);
6397 l->name = xstrdup (fnname);
6398 l->fp_ret_p = fp_ret_p;
6399 l->next = mips16_stubs;
6403 /* If we expect a floating-point return value, but we've built a
6404 stub which does not expect one, then we're in trouble. We can't
6405 use the existing stub, because it won't handle the floating-point
6406 value. We can't build a new stub, because the linker won't know
6407 which stub to use for the various calls in this object file.
6408 Fortunately, this case is illegal, since it means that a function
6409 was declared in two different ways in a single compilation. */
6410 if (fp_ret_p && !l->fp_ret_p)
6411 error ("cannot handle inconsistent calls to %qs", fnname);
6413 if (retval == NULL_RTX)
6414 insn = gen_call_internal_direct (fn, args_size);
6416 insn = gen_call_value_internal_direct (retval, fn, args_size);
6417 insn = mips_emit_call_insn (insn, fn, fn, false);
6419 /* If we are calling a stub which handles a floating-point return
6420 value, we need to arrange to save $18 in the prologue. We do this
6421 by marking the function call as using the register. The prologue
6422 will later see that it is used, and emit code to save it. */
6424 CALL_INSN_FUNCTION_USAGE (insn) =
6425 gen_rtx_EXPR_LIST (VOIDmode,
6426 gen_rtx_CLOBBER (VOIDmode,
6427 gen_rtx_REG (word_mode, 18)),
6428 CALL_INSN_FUNCTION_USAGE (insn));
6433 /* Expand a call of type TYPE. RESULT is where the result will go (null
6434 for "call"s and "sibcall"s), ADDR is the address of the function,
6435 ARGS_SIZE is the size of the arguments and AUX is the value passed
6436 to us by mips_function_arg. LAZY_P is true if this call already
6437 involves a lazily-bound function address (such as when calling
6438 functions through a MIPS16 hard-float stub).
6440 Return the call itself. */
6443 mips_expand_call (enum mips_call_type type, rtx result, rtx addr,
6444 rtx args_size, rtx aux, bool lazy_p)
6446 rtx orig_addr, pattern, insn;
6449 fp_code = aux == 0 ? 0 : (int) GET_MODE (aux);
6450 insn = mips16_build_call_stub (result, &addr, args_size, fp_code);
6453 gcc_assert (!lazy_p && type == MIPS_CALL_NORMAL);
6458 if (!call_insn_operand (addr, VOIDmode))
6460 if (type == MIPS_CALL_EPILOGUE)
6461 addr = MIPS_EPILOGUE_TEMP (Pmode);
6463 addr = gen_reg_rtx (Pmode);
6464 lazy_p |= mips_load_call_address (type, addr, orig_addr);
6469 rtx (*fn) (rtx, rtx);
6471 if (type == MIPS_CALL_SIBCALL)
6472 fn = gen_sibcall_internal;
6474 fn = gen_call_internal;
6476 pattern = fn (addr, args_size);
6478 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
6480 /* Handle return values created by mips_return_fpr_pair. */
6481 rtx (*fn) (rtx, rtx, rtx, rtx);
6484 if (type == MIPS_CALL_SIBCALL)
6485 fn = gen_sibcall_value_multiple_internal;
6487 fn = gen_call_value_multiple_internal;
6489 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
6490 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
6491 pattern = fn (reg1, addr, args_size, reg2);
6495 rtx (*fn) (rtx, rtx, rtx);
6497 if (type == MIPS_CALL_SIBCALL)
6498 fn = gen_sibcall_value_internal;
6500 fn = gen_call_value_internal;
6502 /* Handle return values created by mips_return_fpr_single. */
6503 if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 1)
6504 result = XEXP (XVECEXP (result, 0, 0), 0);
6505 pattern = fn (result, addr, args_size);
6508 return mips_emit_call_insn (pattern, orig_addr, addr, lazy_p);
6511 /* Split call instruction INSN into a $gp-clobbering call and
6512 (where necessary) an instruction to restore $gp from its save slot.
6513 CALL_PATTERN is the pattern of the new call. */
6516 mips_split_call (rtx insn, rtx call_pattern)
6518 emit_call_insn (call_pattern);
6519 if (!find_reg_note (insn, REG_NORETURN, 0))
6520 /* Pick a temporary register that is suitable for both MIPS16 and
6521 non-MIPS16 code. $4 and $5 are used for returning complex double
6522 values in soft-float code, so $6 is the first suitable candidate. */
6523 mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode, GP_ARG_FIRST + 2));
6526 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
6529 mips_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
6531 if (!TARGET_SIBCALLS)
6534 /* Interrupt handlers need special epilogue code and therefore can't
6536 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
6539 /* We can't do a sibcall if the called function is a MIPS16 function
6540 because there is no direct "jx" instruction equivalent to "jalx" to
6541 switch the ISA mode. We only care about cases where the sibling
6542 and normal calls would both be direct. */
6544 && mips_use_mips16_mode_p (decl)
6545 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
6548 /* When -minterlink-mips16 is in effect, assume that non-locally-binding
6549 functions could be MIPS16 ones unless an attribute explicitly tells
6551 if (TARGET_INTERLINK_MIPS16
6553 && (DECL_EXTERNAL (decl) || !targetm.binds_local_p (decl))
6554 && !mips_nomips16_decl_p (decl)
6555 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
6562 /* Emit code to move general operand SRC into condition-code
6563 register DEST given that SCRATCH is a scratch TFmode FPR.
6570 where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */
6573 mips_expand_fcc_reload (rtx dest, rtx src, rtx scratch)
6577 /* Change the source to SFmode. */
6579 src = adjust_address (src, SFmode, 0);
6580 else if (REG_P (src) || GET_CODE (src) == SUBREG)
6581 src = gen_rtx_REG (SFmode, true_regnum (src));
6583 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
6584 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + MAX_FPRS_PER_FMT);
6586 mips_emit_move (copy_rtx (fp1), src);
6587 mips_emit_move (copy_rtx (fp2), CONST0_RTX (SFmode));
6588 emit_insn (gen_slt_sf (dest, fp2, fp1));
6591 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
6592 Assume that the areas do not overlap. */
6595 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
6597 HOST_WIDE_INT offset, delta;
6598 unsigned HOST_WIDE_INT bits;
6600 enum machine_mode mode;
6603 /* Work out how many bits to move at a time. If both operands have
6604 half-word alignment, it is usually better to move in half words.
6605 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
6606 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
6607 Otherwise move word-sized chunks. */
6608 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
6609 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
6610 bits = BITS_PER_WORD / 2;
6612 bits = BITS_PER_WORD;
6614 mode = mode_for_size (bits, MODE_INT, 0);
6615 delta = bits / BITS_PER_UNIT;
6617 /* Allocate a buffer for the temporary registers. */
6618 regs = XALLOCAVEC (rtx, length / delta);
6620 /* Load as many BITS-sized chunks as possible. Use a normal load if
6621 the source has enough alignment, otherwise use left/right pairs. */
6622 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
6624 regs[i] = gen_reg_rtx (mode);
6625 if (MEM_ALIGN (src) >= bits)
6626 mips_emit_move (regs[i], adjust_address (src, mode, offset));
6629 rtx part = adjust_address (src, BLKmode, offset);
6630 if (!mips_expand_ext_as_unaligned_load (regs[i], part, bits, 0))
6635 /* Copy the chunks to the destination. */
6636 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
6637 if (MEM_ALIGN (dest) >= bits)
6638 mips_emit_move (adjust_address (dest, mode, offset), regs[i]);
6641 rtx part = adjust_address (dest, BLKmode, offset);
6642 if (!mips_expand_ins_as_unaligned_store (part, regs[i], bits, 0))
6646 /* Mop up any left-over bytes. */
6647 if (offset < length)
6649 src = adjust_address (src, BLKmode, offset);
6650 dest = adjust_address (dest, BLKmode, offset);
6651 move_by_pieces (dest, src, length - offset,
6652 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
6656 /* Helper function for doing a loop-based block operation on memory
6657 reference MEM. Each iteration of the loop will operate on LENGTH
6660 Create a new base register for use within the loop and point it to
6661 the start of MEM. Create a new memory reference that uses this
6662 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
6665 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
6666 rtx *loop_reg, rtx *loop_mem)
6668 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
6670 /* Although the new mem does not refer to a known location,
6671 it does keep up to LENGTH bytes of alignment. */
6672 *loop_mem = change_address (mem, BLKmode, *loop_reg);
6673 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
6676 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
6677 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
6678 the memory regions do not overlap. */
6681 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length,
6682 HOST_WIDE_INT bytes_per_iter)
6684 rtx label, src_reg, dest_reg, final_src, test;
6685 HOST_WIDE_INT leftover;
6687 leftover = length % bytes_per_iter;
6690 /* Create registers and memory references for use within the loop. */
6691 mips_adjust_block_mem (src, bytes_per_iter, &src_reg, &src);
6692 mips_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest);
6694 /* Calculate the value that SRC_REG should have after the last iteration
6696 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
6699 /* Emit the start of the loop. */
6700 label = gen_label_rtx ();
6703 /* Emit the loop body. */
6704 mips_block_move_straight (dest, src, bytes_per_iter);
6706 /* Move on to the next block. */
6707 mips_emit_move (src_reg, plus_constant (src_reg, bytes_per_iter));
6708 mips_emit_move (dest_reg, plus_constant (dest_reg, bytes_per_iter));
6710 /* Emit the loop condition. */
6711 test = gen_rtx_NE (VOIDmode, src_reg, final_src);
6712 if (Pmode == DImode)
6713 emit_jump_insn (gen_cbranchdi4 (test, src_reg, final_src, label));
6715 emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label));
6717 /* Mop up any left-over bytes. */
6719 mips_block_move_straight (dest, src, leftover);
6722 /* Expand a movmemsi instruction, which copies LENGTH bytes from
6723 memory reference SRC to memory reference DEST. */
6726 mips_expand_block_move (rtx dest, rtx src, rtx length)
6728 if (CONST_INT_P (length))
6730 if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)
6732 mips_block_move_straight (dest, src, INTVAL (length));
6737 mips_block_move_loop (dest, src, INTVAL (length),
6738 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER);
6745 /* Expand a loop of synci insns for the address range [BEGIN, END). */
6748 mips_expand_synci_loop (rtx begin, rtx end)
6750 rtx inc, label, end_label, cmp_result, mask, length;
6752 /* Create end_label. */
6753 end_label = gen_label_rtx ();
6755 /* Check if begin equals end. */
6756 cmp_result = gen_rtx_EQ (VOIDmode, begin, end);
6757 emit_jump_insn (gen_condjump (cmp_result, end_label));
6759 /* Load INC with the cache line size (rdhwr INC,$1). */
6760 inc = gen_reg_rtx (Pmode);
6761 emit_insn (Pmode == SImode
6762 ? gen_rdhwr_synci_step_si (inc)
6763 : gen_rdhwr_synci_step_di (inc));
6765 /* Check if inc is 0. */
6766 cmp_result = gen_rtx_EQ (VOIDmode, inc, const0_rtx);
6767 emit_jump_insn (gen_condjump (cmp_result, end_label));
6769 /* Calculate mask. */
6770 mask = mips_force_unary (Pmode, NEG, inc);
6772 /* Mask out begin by mask. */
6773 begin = mips_force_binary (Pmode, AND, begin, mask);
6775 /* Calculate length. */
6776 length = mips_force_binary (Pmode, MINUS, end, begin);
6778 /* Loop back to here. */
6779 label = gen_label_rtx ();
6782 emit_insn (gen_synci (begin));
6784 /* Update length. */
6785 mips_emit_binary (MINUS, length, length, inc);
6788 mips_emit_binary (PLUS, begin, begin, inc);
6790 /* Check if length is greater than 0. */
6791 cmp_result = gen_rtx_GT (VOIDmode, length, const0_rtx);
6792 emit_jump_insn (gen_condjump (cmp_result, label));
6794 emit_label (end_label);
6797 /* Expand a QI or HI mode atomic memory operation.
6799 GENERATOR contains a pointer to the gen_* function that generates
6800 the SI mode underlying atomic operation using masks that we
6803 RESULT is the return register for the operation. Its value is NULL
6806 MEM is the location of the atomic access.
6808 OLDVAL is the first operand for the operation.
6810 NEWVAL is the optional second operand for the operation. Its value
6811 is NULL if unused. */
6814 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator,
6815 rtx result, rtx mem, rtx oldval, rtx newval)
6817 rtx orig_addr, memsi_addr, memsi, shift, shiftsi, unshifted_mask;
6818 rtx unshifted_mask_reg, mask, inverted_mask, si_op;
6820 enum machine_mode mode;
6822 mode = GET_MODE (mem);
6824 /* Compute the address of the containing SImode value. */
6825 orig_addr = force_reg (Pmode, XEXP (mem, 0));
6826 memsi_addr = mips_force_binary (Pmode, AND, orig_addr,
6827 force_reg (Pmode, GEN_INT (-4)));
6829 /* Create a memory reference for it. */
6830 memsi = gen_rtx_MEM (SImode, memsi_addr);
6831 set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER);
6832 MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem);
6834 /* Work out the byte offset of the QImode or HImode value,
6835 counting from the least significant byte. */
6836 shift = mips_force_binary (Pmode, AND, orig_addr, GEN_INT (3));
6837 if (TARGET_BIG_ENDIAN)
6838 mips_emit_binary (XOR, shift, shift, GEN_INT (mode == QImode ? 3 : 2));
6840 /* Multiply by eight to convert the shift value from bytes to bits. */
6841 mips_emit_binary (ASHIFT, shift, shift, GEN_INT (3));
6843 /* Make the final shift an SImode value, so that it can be used in
6844 SImode operations. */
6845 shiftsi = force_reg (SImode, gen_lowpart (SImode, shift));
6847 /* Set MASK to an inclusive mask of the QImode or HImode value. */
6848 unshifted_mask = GEN_INT (GET_MODE_MASK (mode));
6849 unshifted_mask_reg = force_reg (SImode, unshifted_mask);
6850 mask = mips_force_binary (SImode, ASHIFT, unshifted_mask_reg, shiftsi);
6852 /* Compute the equivalent exclusive mask. */
6853 inverted_mask = gen_reg_rtx (SImode);
6854 emit_insn (gen_rtx_SET (VOIDmode, inverted_mask,
6855 gen_rtx_NOT (SImode, mask)));
6857 /* Shift the old value into place. */
6858 if (oldval != const0_rtx)
6860 oldval = convert_modes (SImode, mode, oldval, true);
6861 oldval = force_reg (SImode, oldval);
6862 oldval = mips_force_binary (SImode, ASHIFT, oldval, shiftsi);
6865 /* Do the same for the new value. */
6866 if (newval && newval != const0_rtx)
6868 newval = convert_modes (SImode, mode, newval, true);
6869 newval = force_reg (SImode, newval);
6870 newval = mips_force_binary (SImode, ASHIFT, newval, shiftsi);
6873 /* Do the SImode atomic access. */
6875 res = gen_reg_rtx (SImode);
6877 si_op = generator.fn_6 (res, memsi, mask, inverted_mask, oldval, newval);
6879 si_op = generator.fn_5 (res, memsi, mask, inverted_mask, oldval);
6881 si_op = generator.fn_4 (memsi, mask, inverted_mask, oldval);
6887 /* Shift and convert the result. */
6888 mips_emit_binary (AND, res, res, mask);
6889 mips_emit_binary (LSHIFTRT, res, res, shiftsi);
6890 mips_emit_move (result, gen_lowpart (GET_MODE (result), res));
6894 /* Return true if it is possible to use left/right accesses for a
6895 bitfield of WIDTH bits starting BITPOS bits into *OP. When
6896 returning true, update *OP, *LEFT and *RIGHT as follows:
6898 *OP is a BLKmode reference to the whole field.
6900 *LEFT is a QImode reference to the first byte if big endian or
6901 the last byte if little endian. This address can be used in the
6902 left-side instructions (LWL, SWL, LDL, SDL).
6904 *RIGHT is a QImode reference to the opposite end of the field and
6905 can be used in the patterning right-side instruction. */
6908 mips_get_unaligned_mem (rtx *op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos,
6909 rtx *left, rtx *right)
6913 /* Check that the operand really is a MEM. Not all the extv and
6914 extzv predicates are checked. */
6918 /* Check that the size is valid. */
6919 if (width != 32 && (!TARGET_64BIT || width != 64))
6922 /* We can only access byte-aligned values. Since we are always passed
6923 a reference to the first byte of the field, it is not necessary to
6924 do anything with BITPOS after this check. */
6925 if (bitpos % BITS_PER_UNIT != 0)
6928 /* Reject aligned bitfields: we want to use a normal load or store
6929 instead of a left/right pair. */
6930 if (MEM_ALIGN (*op) >= width)
6933 /* Adjust *OP to refer to the whole field. This also has the effect
6934 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
6935 *op = adjust_address (*op, BLKmode, 0);
6936 set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
6938 /* Get references to both ends of the field. We deliberately don't
6939 use the original QImode *OP for FIRST since the new BLKmode one
6940 might have a simpler address. */
6941 first = adjust_address (*op, QImode, 0);
6942 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
6944 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
6945 correspond to the MSB and RIGHT to the LSB. */
6946 if (TARGET_BIG_ENDIAN)
6947 *left = first, *right = last;
6949 *left = last, *right = first;
6954 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
6955 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
6956 the operation is the equivalent of:
6958 (set DEST (*_extract SRC WIDTH BITPOS))
6960 Return true on success. */
6963 mips_expand_ext_as_unaligned_load (rtx dest, rtx src, HOST_WIDE_INT width,
6964 HOST_WIDE_INT bitpos)
6966 rtx left, right, temp;
6968 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
6969 be a paradoxical word_mode subreg. This is the only case in which
6970 we allow the destination to be larger than the source. */
6971 if (GET_CODE (dest) == SUBREG
6972 && GET_MODE (dest) == DImode
6973 && GET_MODE (SUBREG_REG (dest)) == SImode)
6974 dest = SUBREG_REG (dest);
6976 /* After the above adjustment, the destination must be the same
6977 width as the source. */
6978 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
6981 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
6984 temp = gen_reg_rtx (GET_MODE (dest));
6985 if (GET_MODE (dest) == DImode)
6987 emit_insn (gen_mov_ldl (temp, src, left));
6988 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
6992 emit_insn (gen_mov_lwl (temp, src, left));
6993 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
6998 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
6999 BITPOS and SRC are the operands passed to the expander; the operation
7000 is the equivalent of:
7002 (set (zero_extract DEST WIDTH BITPOS) SRC)
7004 Return true on success. */
7007 mips_expand_ins_as_unaligned_store (rtx dest, rtx src, HOST_WIDE_INT width,
7008 HOST_WIDE_INT bitpos)
7011 enum machine_mode mode;
7013 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
7016 mode = mode_for_size (width, MODE_INT, 0);
7017 src = gen_lowpart (mode, src);
7020 emit_insn (gen_mov_sdl (dest, src, left));
7021 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
7025 emit_insn (gen_mov_swl (dest, src, left));
7026 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
7031 /* Return true if X is a MEM with the same size as MODE. */
7034 mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
7041 size = MEM_SIZE (x);
7042 return size && INTVAL (size) == GET_MODE_SIZE (mode);
7045 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
7046 source of an "ext" instruction or the destination of an "ins"
7047 instruction. OP must be a register operand and the following
7048 conditions must hold:
7050 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
7051 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7052 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7054 Also reject lengths equal to a word as they are better handled
7055 by the move patterns. */
7058 mips_use_ins_ext_p (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos)
7060 if (!ISA_HAS_EXT_INS
7061 || !register_operand (op, VOIDmode)
7062 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
7065 if (!IN_RANGE (width, 1, GET_MODE_BITSIZE (GET_MODE (op)) - 1))
7068 if (bitpos < 0 || bitpos + width > GET_MODE_BITSIZE (GET_MODE (op)))
7074 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
7075 operation if MAXLEN is the maxium length of consecutive bits that
7076 can make up MASK. MODE is the mode of the operation. See
7077 mask_low_and_shift_len for the actual definition. */
7080 mask_low_and_shift_p (enum machine_mode mode, rtx mask, rtx shift, int maxlen)
7082 return IN_RANGE (mask_low_and_shift_len (mode, mask, shift), 1, maxlen);
7085 /* Return true iff OP1 and OP2 are valid operands together for the
7086 *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider,
7087 see the table in the comment before the pattern. */
7090 and_operands_ok (enum machine_mode mode, rtx op1, rtx op2)
7092 return (memory_operand (op1, mode)
7093 ? and_load_operand (op2, mode)
7094 : and_reg_operand (op2, mode));
7097 /* The canonical form of a mask-low-and-shift-left operation is
7098 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
7099 cleared. Thus we need to shift MASK to the right before checking if it
7100 is a valid mask value. MODE is the mode of the operation. If true
7101 return the length of the mask, otherwise return -1. */
7104 mask_low_and_shift_len (enum machine_mode mode, rtx mask, rtx shift)
7106 HOST_WIDE_INT shval;
7108 shval = INTVAL (shift) & (GET_MODE_BITSIZE (mode) - 1);
7109 return exact_log2 ((UINTVAL (mask) >> shval) + 1);
7112 /* Return true if -msplit-addresses is selected and should be honored.
7114 -msplit-addresses is a half-way house between explicit relocations
7115 and the traditional assembler macros. It can split absolute 32-bit
7116 symbolic constants into a high/lo_sum pair but uses macros for other
7119 Like explicit relocation support for REL targets, it relies
7120 on GNU extensions in the assembler and the linker.
7122 Although this code should work for -O0, it has traditionally
7123 been treated as an optimization. */
7126 mips_split_addresses_p (void)
7128 return (TARGET_SPLIT_ADDRESSES
7132 && !ABI_HAS_64BIT_SYMBOLS);
7135 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
7138 mips_init_relocs (void)
7140 memset (mips_split_p, '\0', sizeof (mips_split_p));
7141 memset (mips_split_hi_p, '\0', sizeof (mips_split_hi_p));
7142 memset (mips_hi_relocs, '\0', sizeof (mips_hi_relocs));
7143 memset (mips_lo_relocs, '\0', sizeof (mips_lo_relocs));
7145 if (ABI_HAS_64BIT_SYMBOLS)
7147 if (TARGET_EXPLICIT_RELOCS)
7149 mips_split_p[SYMBOL_64_HIGH] = true;
7150 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
7151 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
7153 mips_split_p[SYMBOL_64_MID] = true;
7154 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
7155 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
7157 mips_split_p[SYMBOL_64_LOW] = true;
7158 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
7159 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
7161 mips_split_p[SYMBOL_ABSOLUTE] = true;
7162 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
7167 if (TARGET_EXPLICIT_RELOCS || mips_split_addresses_p () || TARGET_MIPS16)
7169 mips_split_p[SYMBOL_ABSOLUTE] = true;
7170 mips_hi_relocs[SYMBOL_ABSOLUTE] = "%hi(";
7171 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
7173 mips_lo_relocs[SYMBOL_32_HIGH] = "%hi(";
7179 /* The high part is provided by a pseudo copy of $gp. */
7180 mips_split_p[SYMBOL_GP_RELATIVE] = true;
7181 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gprel(";
7183 else if (TARGET_EXPLICIT_RELOCS)
7184 /* Small data constants are kept whole until after reload,
7185 then lowered by mips_rewrite_small_data. */
7186 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gp_rel(";
7188 if (TARGET_EXPLICIT_RELOCS)
7190 mips_split_p[SYMBOL_GOT_PAGE_OFST] = true;
7193 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
7194 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%got_ofst(";
7198 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
7199 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%lo(";
7202 /* Expose the use of $28 as soon as possible. */
7203 mips_split_hi_p[SYMBOL_GOT_PAGE_OFST] = true;
7207 /* The HIGH and LO_SUM are matched by special .md patterns. */
7208 mips_split_p[SYMBOL_GOT_DISP] = true;
7210 mips_split_p[SYMBOL_GOTOFF_DISP] = true;
7211 mips_hi_relocs[SYMBOL_GOTOFF_DISP] = "%got_hi(";
7212 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_lo(";
7214 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
7215 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
7216 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
7221 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_disp(";
7223 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got(";
7224 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
7226 /* Expose the use of $28 as soon as possible. */
7227 mips_split_p[SYMBOL_GOT_DISP] = true;
7233 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
7234 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
7235 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
7238 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
7239 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
7241 mips_split_p[SYMBOL_DTPREL] = true;
7242 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
7243 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
7245 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
7247 mips_split_p[SYMBOL_TPREL] = true;
7248 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
7249 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
7251 mips_lo_relocs[SYMBOL_HALF] = "%half(";
7254 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
7255 in context CONTEXT. RELOCS is the array of relocations to use. */
7258 mips_print_operand_reloc (FILE *file, rtx op, enum mips_symbol_context context,
7259 const char **relocs)
7261 enum mips_symbol_type symbol_type;
7264 symbol_type = mips_classify_symbolic_expression (op, context);
7265 gcc_assert (relocs[symbol_type]);
7267 fputs (relocs[symbol_type], file);
7268 output_addr_const (file, mips_strip_unspec_address (op));
7269 for (p = relocs[symbol_type]; *p != 0; p++)
7274 /* Start a new block with the given asm switch enabled. If we need
7275 to print a directive, emit PREFIX before it and SUFFIX after it. */
7278 mips_push_asm_switch_1 (struct mips_asm_switch *asm_switch,
7279 const char *prefix, const char *suffix)
7281 if (asm_switch->nesting_level == 0)
7282 fprintf (asm_out_file, "%s.set\tno%s%s", prefix, asm_switch->name, suffix);
7283 asm_switch->nesting_level++;
7286 /* Likewise, but end a block. */
7289 mips_pop_asm_switch_1 (struct mips_asm_switch *asm_switch,
7290 const char *prefix, const char *suffix)
7292 gcc_assert (asm_switch->nesting_level);
7293 asm_switch->nesting_level--;
7294 if (asm_switch->nesting_level == 0)
7295 fprintf (asm_out_file, "%s.set\t%s%s", prefix, asm_switch->name, suffix);
7298 /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1
7299 that either print a complete line or print nothing. */
7302 mips_push_asm_switch (struct mips_asm_switch *asm_switch)
7304 mips_push_asm_switch_1 (asm_switch, "\t", "\n");
7308 mips_pop_asm_switch (struct mips_asm_switch *asm_switch)
7310 mips_pop_asm_switch_1 (asm_switch, "\t", "\n");
7313 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
7314 The punctuation characters are:
7316 '(' Start a nested ".set noreorder" block.
7317 ')' End a nested ".set noreorder" block.
7318 '[' Start a nested ".set noat" block.
7319 ']' End a nested ".set noat" block.
7320 '<' Start a nested ".set nomacro" block.
7321 '>' End a nested ".set nomacro" block.
7322 '*' Behave like %(%< if generating a delayed-branch sequence.
7323 '#' Print a nop if in a ".set noreorder" block.
7324 '/' Like '#', but do nothing within a delayed-branch sequence.
7325 '?' Print "l" if mips_branch_likely is true
7326 '~' Print a nop if mips_branch_likely is true
7327 '.' Print the name of the register with a hard-wired zero (zero or $0).
7328 '@' Print the name of the assembler temporary register (at or $1).
7329 '^' Print the name of the pic call-through register (t9 or $25).
7330 '+' Print the name of the gp register (usually gp or $28).
7331 '$' Print the name of the stack pointer register (sp or $29).
7333 See also mips_init_print_operand_pucnt. */
7336 mips_print_operand_punctuation (FILE *file, int ch)
7341 mips_push_asm_switch_1 (&mips_noreorder, "", "\n\t");
7345 mips_pop_asm_switch_1 (&mips_noreorder, "\n\t", "");
7349 mips_push_asm_switch_1 (&mips_noat, "", "\n\t");
7353 mips_pop_asm_switch_1 (&mips_noat, "\n\t", "");
7357 mips_push_asm_switch_1 (&mips_nomacro, "", "\n\t");
7361 mips_pop_asm_switch_1 (&mips_nomacro, "\n\t", "");
7365 if (final_sequence != 0)
7367 mips_print_operand_punctuation (file, '(');
7368 mips_print_operand_punctuation (file, '<');
7373 if (mips_noreorder.nesting_level > 0)
7374 fputs ("\n\tnop", file);
7378 /* Print an extra newline so that the delayed insn is separated
7379 from the following ones. This looks neater and is consistent
7380 with non-nop delayed sequences. */
7381 if (mips_noreorder.nesting_level > 0 && final_sequence == 0)
7382 fputs ("\n\tnop\n", file);
7386 if (mips_branch_likely)
7391 if (mips_branch_likely)
7392 fputs ("\n\tnop", file);
7396 fputs (reg_names[GP_REG_FIRST + 0], file);
7400 fputs (reg_names[AT_REGNUM], file);
7404 fputs (reg_names[PIC_FUNCTION_ADDR_REGNUM], file);
7408 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
7412 fputs (reg_names[STACK_POINTER_REGNUM], file);
7421 /* Initialize mips_print_operand_punct. */
7424 mips_init_print_operand_punct (void)
7428 for (p = "()[]<>*#/?~.@^+$"; *p; p++)
7429 mips_print_operand_punct[(unsigned char) *p] = true;
7432 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
7433 associated with condition CODE. Print the condition part of the
7437 mips_print_int_branch_condition (FILE *file, enum rtx_code code, int letter)
7451 /* Conveniently, the MIPS names for these conditions are the same
7452 as their RTL equivalents. */
7453 fputs (GET_RTX_NAME (code), file);
7457 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
7462 /* Likewise floating-point branches. */
7465 mips_print_float_branch_condition (FILE *file, enum rtx_code code, int letter)
7470 fputs ("c1f", file);
7474 fputs ("c1t", file);
7478 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
7483 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
7486 mips_print_operand_punct_valid_p (unsigned char code)
7488 return mips_print_operand_punct[code];
7491 /* Implement TARGET_PRINT_OPERAND. The MIPS-specific operand codes are:
7493 'X' Print CONST_INT OP in hexadecimal format.
7494 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
7495 'd' Print CONST_INT OP in decimal.
7496 'm' Print one less than CONST_INT OP in decimal.
7497 'h' Print the high-part relocation associated with OP, after stripping
7499 'R' Print the low-part relocation associated with OP.
7500 'C' Print the integer branch condition for comparison OP.
7501 'N' Print the inverse of the integer branch condition for comparison OP.
7502 'F' Print the FPU branch condition for comparison OP.
7503 'W' Print the inverse of the FPU branch condition for comparison OP.
7504 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
7505 'z' for (eq:?I ...), 'n' for (ne:?I ...).
7506 't' Like 'T', but with the EQ/NE cases reversed
7507 'Y' Print mips_fp_conditions[INTVAL (OP)]
7508 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
7509 'q' Print a DSP accumulator register.
7510 'D' Print the second part of a double-word register or memory operand.
7511 'L' Print the low-order register in a double-word register operand.
7512 'M' Print high-order register in a double-word register operand.
7513 'z' Print $0 if OP is zero, otherwise print OP normally. */
7516 mips_print_operand (FILE *file, rtx op, int letter)
7520 if (mips_print_operand_punct_valid_p (letter))
7522 mips_print_operand_punctuation (file, letter);
7527 code = GET_CODE (op);
7532 if (CONST_INT_P (op))
7533 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
7535 output_operand_lossage ("invalid use of '%%%c'", letter);
7539 if (CONST_INT_P (op))
7540 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op) & 0xffff);
7542 output_operand_lossage ("invalid use of '%%%c'", letter);
7546 if (CONST_INT_P (op))
7547 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op));
7549 output_operand_lossage ("invalid use of '%%%c'", letter);
7553 if (CONST_INT_P (op))
7554 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op) - 1);
7556 output_operand_lossage ("invalid use of '%%%c'", letter);
7562 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_hi_relocs);
7566 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_lo_relocs);
7570 mips_print_int_branch_condition (file, code, letter);
7574 mips_print_int_branch_condition (file, reverse_condition (code), letter);
7578 mips_print_float_branch_condition (file, code, letter);
7582 mips_print_float_branch_condition (file, reverse_condition (code),
7589 int truth = (code == NE) == (letter == 'T');
7590 fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
7595 if (code == CONST_INT && UINTVAL (op) < ARRAY_SIZE (mips_fp_conditions))
7596 fputs (mips_fp_conditions[UINTVAL (op)], file);
7598 output_operand_lossage ("'%%%c' is not a valid operand prefix",
7605 mips_print_operand (file, op, 0);
7611 if (code == REG && MD_REG_P (REGNO (op)))
7612 fprintf (file, "$ac0");
7613 else if (code == REG && DSP_ACC_REG_P (REGNO (op)))
7614 fprintf (file, "$ac%c", reg_names[REGNO (op)][3]);
7616 output_operand_lossage ("invalid use of '%%%c'", letter);
7624 unsigned int regno = REGNO (op);
7625 if ((letter == 'M' && TARGET_LITTLE_ENDIAN)
7626 || (letter == 'L' && TARGET_BIG_ENDIAN)
7629 else if (letter && letter != 'z' && letter != 'M' && letter != 'L')
7630 output_operand_lossage ("invalid use of '%%%c'", letter);
7631 /* We need to print $0 .. $31 for COP0 registers. */
7632 if (COP0_REG_P (regno))
7633 fprintf (file, "$%s", ®_names[regno][4]);
7635 fprintf (file, "%s", reg_names[regno]);
7641 output_address (plus_constant (XEXP (op, 0), 4));
7642 else if (letter && letter != 'z')
7643 output_operand_lossage ("invalid use of '%%%c'", letter);
7645 output_address (XEXP (op, 0));
7649 if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
7650 fputs (reg_names[GP_REG_FIRST], file);
7651 else if (letter && letter != 'z')
7652 output_operand_lossage ("invalid use of '%%%c'", letter);
7653 else if (CONST_GP_P (op))
7654 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
7656 output_addr_const (file, mips_strip_unspec_address (op));
7662 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
7665 mips_print_operand_address (FILE *file, rtx x)
7667 struct mips_address_info addr;
7669 if (mips_classify_address (&addr, x, word_mode, true))
7673 mips_print_operand (file, addr.offset, 0);
7674 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
7677 case ADDRESS_LO_SUM:
7678 mips_print_operand_reloc (file, addr.offset, SYMBOL_CONTEXT_MEM,
7680 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
7683 case ADDRESS_CONST_INT:
7684 output_addr_const (file, x);
7685 fprintf (file, "(%s)", reg_names[GP_REG_FIRST]);
7688 case ADDRESS_SYMBOLIC:
7689 output_addr_const (file, mips_strip_unspec_address (x));
7695 /* Implement TARGET_ENCODE_SECTION_INFO. */
7698 mips_encode_section_info (tree decl, rtx rtl, int first)
7700 default_encode_section_info (decl, rtl, first);
7702 if (TREE_CODE (decl) == FUNCTION_DECL)
7704 rtx symbol = XEXP (rtl, 0);
7705 tree type = TREE_TYPE (decl);
7707 /* Encode whether the symbol is short or long. */
7708 if ((TARGET_LONG_CALLS && !mips_near_type_p (type))
7709 || mips_far_type_p (type))
7710 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
7714 /* Implement TARGET_SELECT_RTX_SECTION. */
7717 mips_select_rtx_section (enum machine_mode mode, rtx x,
7718 unsigned HOST_WIDE_INT align)
7720 /* ??? Consider using mergeable small data sections. */
7721 if (mips_rtx_constant_in_small_data_p (mode))
7722 return get_named_section (NULL, ".sdata", 0);
7724 return default_elf_select_rtx_section (mode, x, align);
7727 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
7729 The complication here is that, with the combination TARGET_ABICALLS
7730 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
7731 absolute addresses, and should therefore not be included in the
7732 read-only part of a DSO. Handle such cases by selecting a normal
7733 data section instead of a read-only one. The logic apes that in
7734 default_function_rodata_section. */
7737 mips_function_rodata_section (tree decl)
7739 if (!TARGET_ABICALLS || TARGET_ABSOLUTE_ABICALLS || TARGET_GPWORD)
7740 return default_function_rodata_section (decl);
7742 if (decl && DECL_SECTION_NAME (decl))
7744 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7745 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
7747 char *rname = ASTRDUP (name);
7749 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
7751 else if (flag_function_sections
7752 && flag_data_sections
7753 && strncmp (name, ".text.", 6) == 0)
7755 char *rname = ASTRDUP (name);
7756 memcpy (rname + 1, "data", 4);
7757 return get_section (rname, SECTION_WRITE, decl);
7760 return data_section;
7763 /* Implement TARGET_IN_SMALL_DATA_P. */
7766 mips_in_small_data_p (const_tree decl)
7768 unsigned HOST_WIDE_INT size;
7770 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
7773 /* We don't yet generate small-data references for -mabicalls
7774 or VxWorks RTP code. See the related -G handling in
7775 mips_option_override. */
7776 if (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
7779 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
7783 /* Reject anything that isn't in a known small-data section. */
7784 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7785 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
7788 /* If a symbol is defined externally, the assembler will use the
7789 usual -G rules when deciding how to implement macros. */
7790 if (mips_lo_relocs[SYMBOL_GP_RELATIVE] || !DECL_EXTERNAL (decl))
7793 else if (TARGET_EMBEDDED_DATA)
7795 /* Don't put constants into the small data section: we want them
7796 to be in ROM rather than RAM. */
7797 if (TREE_CODE (decl) != VAR_DECL)
7800 if (TREE_READONLY (decl)
7801 && !TREE_SIDE_EFFECTS (decl)
7802 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
7806 /* Enforce -mlocal-sdata. */
7807 if (!TARGET_LOCAL_SDATA && !TREE_PUBLIC (decl))
7810 /* Enforce -mextern-sdata. */
7811 if (!TARGET_EXTERN_SDATA && DECL_P (decl))
7813 if (DECL_EXTERNAL (decl))
7815 if (DECL_COMMON (decl) && DECL_INITIAL (decl) == NULL)
7819 /* We have traditionally not treated zero-sized objects as small data,
7820 so this is now effectively part of the ABI. */
7821 size = int_size_in_bytes (TREE_TYPE (decl));
7822 return size > 0 && size <= mips_small_data_threshold;
7825 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
7826 anchors for small data: the GP register acts as an anchor in that
7827 case. We also don't want to use them for PC-relative accesses,
7828 where the PC acts as an anchor. */
7831 mips_use_anchors_for_symbol_p (const_rtx symbol)
7833 switch (mips_classify_symbol (symbol, SYMBOL_CONTEXT_MEM))
7835 case SYMBOL_PC_RELATIVE:
7836 case SYMBOL_GP_RELATIVE:
7840 return default_use_anchors_for_symbol_p (symbol);
7844 /* The MIPS debug format wants all automatic variables and arguments
7845 to be in terms of the virtual frame pointer (stack pointer before
7846 any adjustment in the function), while the MIPS 3.0 linker wants
7847 the frame pointer to be the stack pointer after the initial
7848 adjustment. So, we do the adjustment here. The arg pointer (which
7849 is eliminated) points to the virtual frame pointer, while the frame
7850 pointer (which may be eliminated) points to the stack pointer after
7851 the initial adjustments. */
7854 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
7856 rtx offset2 = const0_rtx;
7857 rtx reg = eliminate_constant_term (addr, &offset2);
7860 offset = INTVAL (offset2);
7862 if (reg == stack_pointer_rtx
7863 || reg == frame_pointer_rtx
7864 || reg == hard_frame_pointer_rtx)
7866 offset -= cfun->machine->frame.total_size;
7867 if (reg == hard_frame_pointer_rtx)
7868 offset += cfun->machine->frame.hard_frame_pointer_offset;
7871 /* sdbout_parms does not want this to crash for unrecognized cases. */
7873 else if (reg != arg_pointer_rtx)
7874 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
7881 /* Implement ASM_OUTPUT_EXTERNAL. */
7884 mips_output_external (FILE *file, tree decl, const char *name)
7886 default_elf_asm_output_external (file, decl, name);
7888 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
7889 set in order to avoid putting out names that are never really
7891 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
7893 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
7895 /* When using assembler macros, emit .extern directives for
7896 all small-data externs so that the assembler knows how
7899 In most cases it would be safe (though pointless) to emit
7900 .externs for other symbols too. One exception is when an
7901 object is within the -G limit but declared by the user to
7902 be in a section other than .sbss or .sdata. */
7903 fputs ("\t.extern\t", file);
7904 assemble_name (file, name);
7905 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n",
7906 int_size_in_bytes (TREE_TYPE (decl)));
7911 /* Implement TARGET_ASM_OUTPUT_SOURCE_FILENAME. */
7914 mips_output_filename (FILE *stream, const char *name)
7916 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
7918 if (write_symbols == DWARF2_DEBUG)
7920 else if (mips_output_filename_first_time)
7922 mips_output_filename_first_time = 0;
7923 num_source_filenames += 1;
7924 current_function_file = name;
7925 fprintf (stream, "\t.file\t%d ", num_source_filenames);
7926 output_quoted_string (stream, name);
7927 putc ('\n', stream);
7929 /* If we are emitting stabs, let dbxout.c handle this (except for
7930 the mips_output_filename_first_time case). */
7931 else if (write_symbols == DBX_DEBUG)
7933 else if (name != current_function_file
7934 && strcmp (name, current_function_file) != 0)
7936 num_source_filenames += 1;
7937 current_function_file = name;
7938 fprintf (stream, "\t.file\t%d ", num_source_filenames);
7939 output_quoted_string (stream, name);
7940 putc ('\n', stream);
7944 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
7946 static void ATTRIBUTE_UNUSED
7947 mips_output_dwarf_dtprel (FILE *file, int size, rtx x)
7952 fputs ("\t.dtprelword\t", file);
7956 fputs ("\t.dtpreldword\t", file);
7962 output_addr_const (file, x);
7963 fputs ("+0x8000", file);
7966 /* Implement TARGET_DWARF_REGISTER_SPAN. */
7969 mips_dwarf_register_span (rtx reg)
7972 enum machine_mode mode;
7974 /* By default, GCC maps increasing register numbers to increasing
7975 memory locations, but paired FPRs are always little-endian,
7976 regardless of the prevailing endianness. */
7977 mode = GET_MODE (reg);
7978 if (FP_REG_P (REGNO (reg))
7979 && TARGET_BIG_ENDIAN
7980 && MAX_FPRS_PER_FMT > 1
7981 && GET_MODE_SIZE (mode) > UNITS_PER_FPREG)
7983 gcc_assert (GET_MODE_SIZE (mode) == UNITS_PER_HWFPVALUE);
7984 high = mips_subword (reg, true);
7985 low = mips_subword (reg, false);
7986 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, high, low));
7992 /* Implement ASM_OUTPUT_ASCII. */
7995 mips_output_ascii (FILE *stream, const char *string, size_t len)
8001 fprintf (stream, "\t.ascii\t\"");
8002 for (i = 0; i < len; i++)
8006 c = (unsigned char) string[i];
8009 if (c == '\\' || c == '\"')
8011 putc ('\\', stream);
8019 fprintf (stream, "\\%03o", c);
8023 if (cur_pos > 72 && i+1 < len)
8026 fprintf (stream, "\"\n\t.ascii\t\"");
8029 fprintf (stream, "\"\n");
8032 /* Emit either a label, .comm, or .lcomm directive. When using assembler
8033 macros, mark the symbol as written so that mips_asm_output_external
8034 won't emit an .extern for it. STREAM is the output file, NAME is the
8035 name of the symbol, INIT_STRING is the string that should be written
8036 before the symbol and FINAL_STRING is the string that should be
8037 written after it. FINAL_STRING is a printf format that consumes the
8038 remaining arguments. */
8041 mips_declare_object (FILE *stream, const char *name, const char *init_string,
8042 const char *final_string, ...)
8046 fputs (init_string, stream);
8047 assemble_name (stream, name);
8048 va_start (ap, final_string);
8049 vfprintf (stream, final_string, ap);
8052 if (!TARGET_EXPLICIT_RELOCS)
8054 tree name_tree = get_identifier (name);
8055 TREE_ASM_WRITTEN (name_tree) = 1;
8059 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
8060 NAME is the name of the object and ALIGN is the required alignment
8061 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
8062 alignment argument. */
8065 mips_declare_common_object (FILE *stream, const char *name,
8066 const char *init_string,
8067 unsigned HOST_WIDE_INT size,
8068 unsigned int align, bool takes_alignment_p)
8070 if (!takes_alignment_p)
8072 size += (align / BITS_PER_UNIT) - 1;
8073 size -= size % (align / BITS_PER_UNIT);
8074 mips_declare_object (stream, name, init_string,
8075 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
8078 mips_declare_object (stream, name, init_string,
8079 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
8080 size, align / BITS_PER_UNIT);
8083 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
8084 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
8087 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
8088 unsigned HOST_WIDE_INT size,
8091 /* If the target wants uninitialized const declarations in
8092 .rdata then don't put them in .comm. */
8093 if (TARGET_EMBEDDED_DATA
8094 && TARGET_UNINIT_CONST_IN_RODATA
8095 && TREE_CODE (decl) == VAR_DECL
8096 && TREE_READONLY (decl)
8097 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
8099 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
8100 targetm.asm_out.globalize_label (stream, name);
8102 switch_to_section (readonly_data_section);
8103 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
8104 mips_declare_object (stream, name, "",
8105 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
8109 mips_declare_common_object (stream, name, "\n\t.comm\t",
8113 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8114 extern int size_directive_output;
8116 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
8117 definitions except that it uses mips_declare_object to emit the label. */
8120 mips_declare_object_name (FILE *stream, const char *name,
8121 tree decl ATTRIBUTE_UNUSED)
8123 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8124 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
8127 size_directive_output = 0;
8128 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
8132 size_directive_output = 1;
8133 size = int_size_in_bytes (TREE_TYPE (decl));
8134 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8137 mips_declare_object (stream, name, "", ":\n");
8140 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
8143 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
8147 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
8148 if (!flag_inhibit_size_directive
8149 && DECL_SIZE (decl) != 0
8152 && DECL_INITIAL (decl) == error_mark_node
8153 && !size_directive_output)
8157 size_directive_output = 1;
8158 size = int_size_in_bytes (TREE_TYPE (decl));
8159 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8164 /* Return the FOO in the name of the ".mdebug.FOO" section associated
8165 with the current ABI. */
8168 mips_mdebug_abi_name (void)
8181 return TARGET_64BIT ? "eabi64" : "eabi32";
8187 /* Implement TARGET_ASM_FILE_START. */
8190 mips_file_start (void)
8192 default_file_start ();
8194 /* Generate a special section to describe the ABI switches used to
8195 produce the resultant binary. This is unnecessary on IRIX and
8196 causes unwanted warnings from the native linker. */
8199 /* Record the ABI itself. Modern versions of binutils encode
8200 this information in the ELF header flags, but GDB needs the
8201 information in order to correctly debug binaries produced by
8202 older binutils. See the function mips_gdbarch_init in
8204 fprintf (asm_out_file, "\t.section .mdebug.%s\n\t.previous\n",
8205 mips_mdebug_abi_name ());
8207 /* There is no ELF header flag to distinguish long32 forms of the
8208 EABI from long64 forms. Emit a special section to help tools
8209 such as GDB. Do the same for o64, which is sometimes used with
8211 if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
8212 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n"
8213 "\t.previous\n", TARGET_LONG64 ? 64 : 32);
8215 #ifdef HAVE_AS_GNU_ATTRIBUTE
8219 /* No floating-point operations, -mno-float. */
8220 if (TARGET_NO_FLOAT)
8222 /* Soft-float code, -msoft-float. */
8223 else if (!TARGET_HARD_FLOAT_ABI)
8225 /* Single-float code, -msingle-float. */
8226 else if (!TARGET_DOUBLE_FLOAT)
8228 /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64. */
8229 else if (!TARGET_64BIT && TARGET_FLOAT64)
8231 /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */
8235 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n", attr);
8240 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
8241 if (TARGET_ABICALLS)
8243 fprintf (asm_out_file, "\t.abicalls\n");
8244 if (TARGET_ABICALLS_PIC0)
8245 fprintf (asm_out_file, "\t.option\tpic0\n");
8248 if (flag_verbose_asm)
8249 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
8251 mips_small_data_threshold, mips_arch_info->name, mips_isa);
8254 /* Make the last instruction frame-related and note that it performs
8255 the operation described by FRAME_PATTERN. */
8258 mips_set_frame_expr (rtx frame_pattern)
8262 insn = get_last_insn ();
8263 RTX_FRAME_RELATED_P (insn) = 1;
8264 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
8269 /* Return a frame-related rtx that stores REG at MEM.
8270 REG must be a single register. */
8273 mips_frame_set (rtx mem, rtx reg)
8277 /* If we're saving the return address register and the DWARF return
8278 address column differs from the hard register number, adjust the
8279 note reg to refer to the former. */
8280 if (REGNO (reg) == RETURN_ADDR_REGNUM
8281 && DWARF_FRAME_RETURN_COLUMN != RETURN_ADDR_REGNUM)
8282 reg = gen_rtx_REG (GET_MODE (reg), DWARF_FRAME_RETURN_COLUMN);
8284 set = gen_rtx_SET (VOIDmode, mem, reg);
8285 RTX_FRAME_RELATED_P (set) = 1;
8290 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
8291 mips16e_s2_s8_regs[X], it must also save the registers in indexes
8292 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
8293 static const unsigned char mips16e_s2_s8_regs[] = {
8294 30, 23, 22, 21, 20, 19, 18
8296 static const unsigned char mips16e_a0_a3_regs[] = {
8300 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
8301 ordered from the uppermost in memory to the lowest in memory. */
8302 static const unsigned char mips16e_save_restore_regs[] = {
8303 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
8306 /* Return the index of the lowest X in the range [0, SIZE) for which
8307 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
8310 mips16e_find_first_register (unsigned int mask, const unsigned char *regs,
8315 for (i = 0; i < size; i++)
8316 if (BITSET_P (mask, regs[i]))
8322 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
8323 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
8324 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
8325 is true for all indexes (X, SIZE). */
8328 mips16e_mask_registers (unsigned int *mask_ptr, const unsigned char *regs,
8329 unsigned int size, unsigned int *num_regs_ptr)
8333 i = mips16e_find_first_register (*mask_ptr, regs, size);
8334 for (i++; i < size; i++)
8335 if (!BITSET_P (*mask_ptr, regs[i]))
8338 *mask_ptr |= 1 << regs[i];
8342 /* Return a simplified form of X using the register values in REG_VALUES.
8343 REG_VALUES[R] is the last value assigned to hard register R, or null
8344 if R has not been modified.
8346 This function is rather limited, but is good enough for our purposes. */
8349 mips16e_collect_propagate_value (rtx x, rtx *reg_values)
8351 x = avoid_constant_pool_reference (x);
8355 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
8356 return simplify_gen_unary (GET_CODE (x), GET_MODE (x),
8357 x0, GET_MODE (XEXP (x, 0)));
8360 if (ARITHMETIC_P (x))
8362 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
8363 rtx x1 = mips16e_collect_propagate_value (XEXP (x, 1), reg_values);
8364 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), x0, x1);
8368 && reg_values[REGNO (x)]
8369 && !rtx_unstable_p (reg_values[REGNO (x)]))
8370 return reg_values[REGNO (x)];
8375 /* Return true if (set DEST SRC) stores an argument register into its
8376 caller-allocated save slot, storing the number of that argument
8377 register in *REGNO_PTR if so. REG_VALUES is as for
8378 mips16e_collect_propagate_value. */
8381 mips16e_collect_argument_save_p (rtx dest, rtx src, rtx *reg_values,
8382 unsigned int *regno_ptr)
8384 unsigned int argno, regno;
8385 HOST_WIDE_INT offset, required_offset;
8388 /* Check that this is a word-mode store. */
8389 if (!MEM_P (dest) || !REG_P (src) || GET_MODE (dest) != word_mode)
8392 /* Check that the register being saved is an unmodified argument
8394 regno = REGNO (src);
8395 if (!IN_RANGE (regno, GP_ARG_FIRST, GP_ARG_LAST) || reg_values[regno])
8397 argno = regno - GP_ARG_FIRST;
8399 /* Check whether the address is an appropriate stack-pointer or
8400 frame-pointer access. */
8401 addr = mips16e_collect_propagate_value (XEXP (dest, 0), reg_values);
8402 mips_split_plus (addr, &base, &offset);
8403 required_offset = cfun->machine->frame.total_size + argno * UNITS_PER_WORD;
8404 if (base == hard_frame_pointer_rtx)
8405 required_offset -= cfun->machine->frame.hard_frame_pointer_offset;
8406 else if (base != stack_pointer_rtx)
8408 if (offset != required_offset)
8415 /* A subroutine of mips_expand_prologue, called only when generating
8416 MIPS16e SAVE instructions. Search the start of the function for any
8417 instructions that save argument registers into their caller-allocated
8418 save slots. Delete such instructions and return a value N such that
8419 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
8420 instructions redundant. */
8423 mips16e_collect_argument_saves (void)
8425 rtx reg_values[FIRST_PSEUDO_REGISTER];
8426 rtx insn, next, set, dest, src;
8427 unsigned int nargs, regno;
8429 push_topmost_sequence ();
8431 memset (reg_values, 0, sizeof (reg_values));
8432 for (insn = get_insns (); insn; insn = next)
8434 next = NEXT_INSN (insn);
8435 if (NOTE_P (insn) || DEBUG_INSN_P (insn))
8441 set = PATTERN (insn);
8442 if (GET_CODE (set) != SET)
8445 dest = SET_DEST (set);
8446 src = SET_SRC (set);
8447 if (mips16e_collect_argument_save_p (dest, src, reg_values, ®no))
8449 if (!BITSET_P (cfun->machine->frame.mask, regno))
8452 nargs = MAX (nargs, (regno - GP_ARG_FIRST) + 1);
8455 else if (REG_P (dest) && GET_MODE (dest) == word_mode)
8456 reg_values[REGNO (dest)]
8457 = mips16e_collect_propagate_value (src, reg_values);
8461 pop_topmost_sequence ();
8466 /* Return a move between register REGNO and memory location SP + OFFSET.
8467 Make the move a load if RESTORE_P, otherwise make it a frame-related
8471 mips16e_save_restore_reg (bool restore_p, HOST_WIDE_INT offset,
8476 mem = gen_frame_mem (SImode, plus_constant (stack_pointer_rtx, offset));
8477 reg = gen_rtx_REG (SImode, regno);
8479 ? gen_rtx_SET (VOIDmode, reg, mem)
8480 : mips_frame_set (mem, reg));
8483 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
8484 The instruction must:
8486 - Allocate or deallocate SIZE bytes in total; SIZE is known
8489 - Save or restore as many registers in *MASK_PTR as possible.
8490 The instruction saves the first registers at the top of the
8491 allocated area, with the other registers below it.
8493 - Save NARGS argument registers above the allocated area.
8495 (NARGS is always zero if RESTORE_P.)
8497 The SAVE and RESTORE instructions cannot save and restore all general
8498 registers, so there may be some registers left over for the caller to
8499 handle. Destructively modify *MASK_PTR so that it contains the registers
8500 that still need to be saved or restored. The caller can save these
8501 registers in the memory immediately below *OFFSET_PTR, which is a
8502 byte offset from the bottom of the allocated stack area. */
8505 mips16e_build_save_restore (bool restore_p, unsigned int *mask_ptr,
8506 HOST_WIDE_INT *offset_ptr, unsigned int nargs,
8510 HOST_WIDE_INT offset, top_offset;
8511 unsigned int i, regno;
8514 gcc_assert (cfun->machine->frame.num_fp == 0);
8516 /* Calculate the number of elements in the PARALLEL. We need one element
8517 for the stack adjustment, one for each argument register save, and one
8518 for each additional register move. */
8520 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
8521 if (BITSET_P (*mask_ptr, mips16e_save_restore_regs[i]))
8524 /* Create the final PARALLEL. */
8525 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (n));
8528 /* Add the stack pointer adjustment. */
8529 set = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8530 plus_constant (stack_pointer_rtx,
8531 restore_p ? size : -size));
8532 RTX_FRAME_RELATED_P (set) = 1;
8533 XVECEXP (pattern, 0, n++) = set;
8535 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8536 top_offset = restore_p ? size : 0;
8538 /* Save the arguments. */
8539 for (i = 0; i < nargs; i++)
8541 offset = top_offset + i * UNITS_PER_WORD;
8542 set = mips16e_save_restore_reg (restore_p, offset, GP_ARG_FIRST + i);
8543 XVECEXP (pattern, 0, n++) = set;
8546 /* Then fill in the other register moves. */
8547 offset = top_offset;
8548 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
8550 regno = mips16e_save_restore_regs[i];
8551 if (BITSET_P (*mask_ptr, regno))
8553 offset -= UNITS_PER_WORD;
8554 set = mips16e_save_restore_reg (restore_p, offset, regno);
8555 XVECEXP (pattern, 0, n++) = set;
8556 *mask_ptr &= ~(1 << regno);
8560 /* Tell the caller what offset it should use for the remaining registers. */
8561 *offset_ptr = size + (offset - top_offset);
8563 gcc_assert (n == XVECLEN (pattern, 0));
8568 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
8569 pointer. Return true if PATTERN matches the kind of instruction
8570 generated by mips16e_build_save_restore. If INFO is nonnull,
8571 initialize it when returning true. */
8574 mips16e_save_restore_pattern_p (rtx pattern, HOST_WIDE_INT adjust,
8575 struct mips16e_save_restore_info *info)
8577 unsigned int i, nargs, mask, extra;
8578 HOST_WIDE_INT top_offset, save_offset, offset;
8579 rtx set, reg, mem, base;
8582 if (!GENERATE_MIPS16E_SAVE_RESTORE)
8585 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8586 top_offset = adjust > 0 ? adjust : 0;
8588 /* Interpret all other members of the PARALLEL. */
8589 save_offset = top_offset - UNITS_PER_WORD;
8593 for (n = 1; n < XVECLEN (pattern, 0); n++)
8595 /* Check that we have a SET. */
8596 set = XVECEXP (pattern, 0, n);
8597 if (GET_CODE (set) != SET)
8600 /* Check that the SET is a load (if restoring) or a store
8602 mem = adjust > 0 ? SET_SRC (set) : SET_DEST (set);
8606 /* Check that the address is the sum of the stack pointer and a
8607 possibly-zero constant offset. */
8608 mips_split_plus (XEXP (mem, 0), &base, &offset);
8609 if (base != stack_pointer_rtx)
8612 /* Check that SET's other operand is a register. */
8613 reg = adjust > 0 ? SET_DEST (set) : SET_SRC (set);
8617 /* Check for argument saves. */
8618 if (offset == top_offset + nargs * UNITS_PER_WORD
8619 && REGNO (reg) == GP_ARG_FIRST + nargs)
8621 else if (offset == save_offset)
8623 while (mips16e_save_restore_regs[i++] != REGNO (reg))
8624 if (i == ARRAY_SIZE (mips16e_save_restore_regs))
8627 mask |= 1 << REGNO (reg);
8628 save_offset -= UNITS_PER_WORD;
8634 /* Check that the restrictions on register ranges are met. */
8636 mips16e_mask_registers (&mask, mips16e_s2_s8_regs,
8637 ARRAY_SIZE (mips16e_s2_s8_regs), &extra);
8638 mips16e_mask_registers (&mask, mips16e_a0_a3_regs,
8639 ARRAY_SIZE (mips16e_a0_a3_regs), &extra);
8643 /* Make sure that the topmost argument register is not saved twice.
8644 The checks above ensure that the same is then true for the other
8645 argument registers. */
8646 if (nargs > 0 && BITSET_P (mask, GP_ARG_FIRST + nargs - 1))
8649 /* Pass back information, if requested. */
8652 info->nargs = nargs;
8654 info->size = (adjust > 0 ? adjust : -adjust);
8660 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
8661 for the register range [MIN_REG, MAX_REG]. Return a pointer to
8662 the null terminator. */
8665 mips16e_add_register_range (char *s, unsigned int min_reg,
8666 unsigned int max_reg)
8668 if (min_reg != max_reg)
8669 s += sprintf (s, ",%s-%s", reg_names[min_reg], reg_names[max_reg]);
8671 s += sprintf (s, ",%s", reg_names[min_reg]);
8675 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
8676 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
8679 mips16e_output_save_restore (rtx pattern, HOST_WIDE_INT adjust)
8681 static char buffer[300];
8683 struct mips16e_save_restore_info info;
8684 unsigned int i, end;
8687 /* Parse the pattern. */
8688 if (!mips16e_save_restore_pattern_p (pattern, adjust, &info))
8691 /* Add the mnemonic. */
8692 s = strcpy (buffer, adjust > 0 ? "restore\t" : "save\t");
8695 /* Save the arguments. */
8697 s += sprintf (s, "%s-%s,", reg_names[GP_ARG_FIRST],
8698 reg_names[GP_ARG_FIRST + info.nargs - 1]);
8699 else if (info.nargs == 1)
8700 s += sprintf (s, "%s,", reg_names[GP_ARG_FIRST]);
8702 /* Emit the amount of stack space to allocate or deallocate. */
8703 s += sprintf (s, "%d", (int) info.size);
8705 /* Save or restore $16. */
8706 if (BITSET_P (info.mask, 16))
8707 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 16]);
8709 /* Save or restore $17. */
8710 if (BITSET_P (info.mask, 17))
8711 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 17]);
8713 /* Save or restore registers in the range $s2...$s8, which
8714 mips16e_s2_s8_regs lists in decreasing order. Note that this
8715 is a software register range; the hardware registers are not
8716 numbered consecutively. */
8717 end = ARRAY_SIZE (mips16e_s2_s8_regs);
8718 i = mips16e_find_first_register (info.mask, mips16e_s2_s8_regs, end);
8720 s = mips16e_add_register_range (s, mips16e_s2_s8_regs[end - 1],
8721 mips16e_s2_s8_regs[i]);
8723 /* Save or restore registers in the range $a0...$a3. */
8724 end = ARRAY_SIZE (mips16e_a0_a3_regs);
8725 i = mips16e_find_first_register (info.mask, mips16e_a0_a3_regs, end);
8727 s = mips16e_add_register_range (s, mips16e_a0_a3_regs[i],
8728 mips16e_a0_a3_regs[end - 1]);
8730 /* Save or restore $31. */
8731 if (BITSET_P (info.mask, RETURN_ADDR_REGNUM))
8732 s += sprintf (s, ",%s", reg_names[RETURN_ADDR_REGNUM]);
8737 /* Return true if the current function returns its value in a floating-point
8738 register in MIPS16 mode. */
8741 mips16_cfun_returns_in_fpr_p (void)
8743 tree return_type = DECL_RESULT (current_function_decl);
8744 return (TARGET_MIPS16
8745 && TARGET_HARD_FLOAT_ABI
8746 && !aggregate_value_p (return_type, current_function_decl)
8747 && mips_return_mode_in_fpr_p (DECL_MODE (return_type)));
8750 /* Return true if predicate PRED is true for at least one instruction.
8751 Cache the result in *CACHE, and assume that the result is true
8752 if *CACHE is already true. */
8755 mips_find_gp_ref (bool *cache, bool (*pred) (rtx))
8761 push_topmost_sequence ();
8762 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8763 if (USEFUL_INSN_P (insn) && pred (insn))
8768 pop_topmost_sequence ();
8773 /* Return true if INSN refers to the global pointer in an "inflexible" way.
8774 See mips_cfun_has_inflexible_gp_ref_p for details. */
8777 mips_insn_has_inflexible_gp_ref_p (rtx insn)
8779 /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE
8780 indicate that the target could be a traditional MIPS
8781 lazily-binding stub. */
8782 return find_reg_fusage (insn, USE, pic_offset_table_rtx);
8785 /* Return true if the current function refers to the global pointer
8786 in a way that forces $28 to be valid. This means that we can't
8787 change the choice of global pointer, even for NewABI code.
8789 One example of this (and one which needs several checks) is that
8790 $28 must be valid when calling traditional MIPS lazy-binding stubs.
8791 (This restriction does not apply to PLTs.) */
8794 mips_cfun_has_inflexible_gp_ref_p (void)
8796 /* If the function has a nonlocal goto, $28 must hold the correct
8797 global pointer for the target function. That is, the target
8798 of the goto implicitly uses $28. */
8799 if (crtl->has_nonlocal_goto)
8802 if (TARGET_ABICALLS_PIC2)
8804 /* Symbolic accesses implicitly use the global pointer unless
8805 -mexplicit-relocs is in effect. JAL macros to symbolic addresses
8806 might go to traditional MIPS lazy-binding stubs. */
8807 if (!TARGET_EXPLICIT_RELOCS)
8810 /* FUNCTION_PROFILER includes a JAL to _mcount, which again
8811 can be lazily-bound. */
8815 /* MIPS16 functions that return in FPRs need to call an
8816 external libgcc routine. This call is only made explict
8817 during mips_expand_epilogue, and it too might be lazily bound. */
8818 if (mips16_cfun_returns_in_fpr_p ())
8822 return mips_find_gp_ref (&cfun->machine->has_inflexible_gp_insn_p,
8823 mips_insn_has_inflexible_gp_ref_p);
8826 /* Return true if INSN refers to the global pointer in a "flexible" way.
8827 See mips_cfun_has_flexible_gp_ref_p for details. */
8830 mips_insn_has_flexible_gp_ref_p (rtx insn)
8832 return (get_attr_got (insn) != GOT_UNSET
8833 || mips_small_data_pattern_p (PATTERN (insn))
8834 || reg_overlap_mentioned_p (pic_offset_table_rtx, PATTERN (insn)));
8837 /* Return true if the current function references the global pointer,
8838 but if those references do not inherently require the global pointer
8839 to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */
8842 mips_cfun_has_flexible_gp_ref_p (void)
8844 /* Reload can sometimes introduce constant pool references
8845 into a function that otherwise didn't need them. For example,
8846 suppose we have an instruction like:
8848 (set (reg:DF R1) (float:DF (reg:SI R2)))
8850 If R2 turns out to be a constant such as 1, the instruction may
8851 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
8852 the option of using this constant if R2 doesn't get allocated
8855 In cases like these, reload will have added the constant to the
8856 pool but no instruction will yet refer to it. */
8857 if (TARGET_ABICALLS_PIC2 && !reload_completed && crtl->uses_const_pool)
8860 return mips_find_gp_ref (&cfun->machine->has_flexible_gp_insn_p,
8861 mips_insn_has_flexible_gp_ref_p);
8864 /* Return the register that should be used as the global pointer
8865 within this function. Return INVALID_REGNUM if the function
8866 doesn't need a global pointer. */
8869 mips_global_pointer (void)
8873 /* $gp is always available unless we're using a GOT. */
8874 if (!TARGET_USE_GOT)
8875 return GLOBAL_POINTER_REGNUM;
8877 /* If there are inflexible references to $gp, we must use the
8878 standard register. */
8879 if (mips_cfun_has_inflexible_gp_ref_p ())
8880 return GLOBAL_POINTER_REGNUM;
8882 /* If there are no current references to $gp, then the only uses
8883 we can introduce later are those involved in long branches. */
8884 if (TARGET_ABSOLUTE_JUMPS && !mips_cfun_has_flexible_gp_ref_p ())
8885 return INVALID_REGNUM;
8887 /* If the global pointer is call-saved, try to use a call-clobbered
8889 if (TARGET_CALL_SAVED_GP && current_function_is_leaf)
8890 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
8891 if (!df_regs_ever_live_p (regno)
8892 && call_really_used_regs[regno]
8893 && !fixed_regs[regno]
8894 && regno != PIC_FUNCTION_ADDR_REGNUM)
8897 return GLOBAL_POINTER_REGNUM;
8900 /* Return true if the current function's prologue must load the global
8901 pointer value into pic_offset_table_rtx and store the same value in
8902 the function's cprestore slot (if any).
8904 One problem we have to deal with is that, when emitting GOT-based
8905 position independent code, long-branch sequences will need to load
8906 the address of the branch target from the GOT. We don't know until
8907 the very end of compilation whether (and where) the function needs
8908 long branches, so we must ensure that _any_ branch can access the
8909 global pointer in some form. However, we do not want to pessimize
8910 the usual case in which all branches are short.
8912 We handle this as follows:
8914 (1) During reload, we set cfun->machine->global_pointer to
8915 INVALID_REGNUM if we _know_ that the current function
8916 doesn't need a global pointer. This is only valid if
8917 long branches don't need the GOT.
8919 Otherwise, we assume that we might need a global pointer
8920 and pick an appropriate register.
8922 (2) If cfun->machine->global_pointer != INVALID_REGNUM,
8923 we ensure that the global pointer is available at every
8924 block boundary bar entry and exit. We do this in one of two ways:
8926 - If the function has a cprestore slot, we ensure that this
8927 slot is valid at every branch. However, as explained in
8928 point (6) below, there is no guarantee that pic_offset_table_rtx
8929 itself is valid if new uses of the global pointer are introduced
8930 after the first post-epilogue split.
8932 We guarantee that the cprestore slot is valid by loading it
8933 into a fake register, CPRESTORE_SLOT_REGNUM. We then make
8934 this register live at every block boundary bar function entry
8935 and exit. It is then invalid to move the load (and thus the
8936 preceding store) across a block boundary.
8938 - If the function has no cprestore slot, we guarantee that
8939 pic_offset_table_rtx itself is valid at every branch.
8941 See mips_eh_uses for the handling of the register liveness.
8943 (3) During prologue and epilogue generation, we emit "ghost"
8944 placeholder instructions to manipulate the global pointer.
8946 (4) During prologue generation, we set cfun->machine->must_initialize_gp_p
8947 and cfun->machine->must_restore_gp_when_clobbered_p if we already know
8948 that the function needs a global pointer. (There is no need to set
8949 them earlier than this, and doing it as late as possible leads to
8950 fewer false positives.)
8952 (5) If cfun->machine->must_initialize_gp_p is true during a
8953 split_insns pass, we split the ghost instructions into real
8954 instructions. These split instructions can then be optimized in
8955 the usual way. Otherwise, we keep the ghost instructions intact,
8956 and optimize for the case where they aren't needed. We still
8957 have the option of splitting them later, if we need to introduce
8958 new uses of the global pointer.
8960 For example, the scheduler ignores a ghost instruction that
8961 stores $28 to the stack, but it handles the split form of
8962 the ghost instruction as an ordinary store.
8964 (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p
8965 is true during the first post-epilogue split_insns pass, we split
8966 calls and restore_gp patterns into instructions that explicitly
8967 load pic_offset_table_rtx from the cprestore slot. Otherwise,
8968 we split these patterns into instructions that _don't_ load from
8971 If cfun->machine->must_restore_gp_when_clobbered_p is true at the
8972 time of the split, then any instructions that exist at that time
8973 can make free use of pic_offset_table_rtx. However, if we want
8974 to introduce new uses of the global pointer after the split,
8975 we must explicitly load the value from the cprestore slot, since
8976 pic_offset_table_rtx itself might not be valid at a given point
8979 The idea is that we want to be able to delete redundant
8980 loads from the cprestore slot in the usual case where no
8981 long branches are needed.
8983 (7) If cfun->machine->must_initialize_gp_p is still false at the end
8984 of md_reorg, we decide whether the global pointer is needed for
8985 long branches. If so, we set cfun->machine->must_initialize_gp_p
8986 to true and split the ghost instructions into real instructions
8989 Note that the ghost instructions must have a zero length for three reasons:
8991 - Giving the length of the underlying $gp sequence might cause
8992 us to use long branches in cases where they aren't really needed.
8994 - They would perturb things like alignment calculations.
8996 - More importantly, the hazard detection in md_reorg relies on
8997 empty instructions having a zero length.
8999 If we find a long branch and split the ghost instructions at the
9000 end of md_reorg, the split could introduce more long branches.
9001 That isn't a problem though, because we still do the split before
9002 the final shorten_branches pass.
9004 This is extremely ugly, but it seems like the best compromise between
9005 correctness and efficiency. */
9008 mips_must_initialize_gp_p (void)
9010 return cfun->machine->must_initialize_gp_p;
9013 /* Return true if REGNO is a register that is ordinarily call-clobbered
9014 but must nevertheless be preserved by an interrupt handler. */
9017 mips_interrupt_extra_call_saved_reg_p (unsigned int regno)
9019 if (MD_REG_P (regno))
9022 if (TARGET_DSP && DSP_ACC_REG_P (regno))
9025 if (GP_REG_P (regno) && !cfun->machine->use_shadow_register_set_p)
9027 /* $0 is hard-wired. */
9028 if (regno == GP_REG_FIRST)
9031 /* The interrupt handler can treat kernel registers as
9032 scratch registers. */
9033 if (KERNEL_REG_P (regno))
9036 /* The function will return the stack pointer to its original value
9038 if (regno == STACK_POINTER_REGNUM)
9041 /* Otherwise, return true for registers that aren't ordinarily
9043 return call_really_used_regs[regno];
9049 /* Return true if the current function should treat register REGNO
9053 mips_cfun_call_saved_reg_p (unsigned int regno)
9055 /* Interrupt handlers need to save extra registers. */
9056 if (cfun->machine->interrupt_handler_p
9057 && mips_interrupt_extra_call_saved_reg_p (regno))
9060 /* call_insns preserve $28 unless they explicitly say otherwise,
9061 so call_really_used_regs[] treats $28 as call-saved. However,
9062 we want the ABI property rather than the default call_insn
9064 return (regno == GLOBAL_POINTER_REGNUM
9065 ? TARGET_CALL_SAVED_GP
9066 : !call_really_used_regs[regno]);
9069 /* Return true if the function body might clobber register REGNO.
9070 We know that REGNO is call-saved. */
9073 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno)
9075 /* Some functions should be treated as clobbering all call-saved
9077 if (crtl->saves_all_registers)
9080 /* DF handles cases where a register is explicitly referenced in
9081 the rtl. Incoming values are passed in call-clobbered registers,
9082 so we can assume that any live call-saved register is set within
9084 if (df_regs_ever_live_p (regno))
9087 /* Check for registers that are clobbered by FUNCTION_PROFILER.
9088 These clobbers are not explicit in the rtl. */
9089 if (crtl->profile && MIPS_SAVE_REG_FOR_PROFILING_P (regno))
9092 /* If we're using a call-saved global pointer, the function's
9093 prologue will need to set it up. */
9094 if (cfun->machine->global_pointer == regno)
9097 /* The function's prologue will need to set the frame pointer if
9098 frame_pointer_needed. */
9099 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
9102 /* If a MIPS16 function returns a value in FPRs, its epilogue
9103 will need to call an external libgcc routine. This yet-to-be
9104 generated call_insn will clobber $31. */
9105 if (regno == RETURN_ADDR_REGNUM && mips16_cfun_returns_in_fpr_p ())
9108 /* If REGNO is ordinarily call-clobbered, we must assume that any
9109 called function could modify it. */
9110 if (cfun->machine->interrupt_handler_p
9111 && !current_function_is_leaf
9112 && mips_interrupt_extra_call_saved_reg_p (regno))
9118 /* Return true if the current function must save register REGNO. */
9121 mips_save_reg_p (unsigned int regno)
9123 if (mips_cfun_call_saved_reg_p (regno))
9125 if (mips_cfun_might_clobber_call_saved_reg_p (regno))
9128 /* Save both registers in an FPR pair if either one is used. This is
9129 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
9130 register to be used without the even register. */
9131 if (FP_REG_P (regno)
9132 && MAX_FPRS_PER_FMT == 2
9133 && mips_cfun_might_clobber_call_saved_reg_p (regno + 1))
9137 /* We need to save the incoming return address if __builtin_eh_return
9138 is being used to set a different return address. */
9139 if (regno == RETURN_ADDR_REGNUM && crtl->calls_eh_return)
9145 /* Populate the current function's mips_frame_info structure.
9147 MIPS stack frames look like:
9149 +-------------------------------+
9151 | incoming stack arguments |
9153 +-------------------------------+
9155 | caller-allocated save area |
9156 A | for register arguments |
9158 +-------------------------------+ <-- incoming stack pointer
9160 | callee-allocated save area |
9161 B | for arguments that are |
9162 | split between registers and |
9165 +-------------------------------+ <-- arg_pointer_rtx
9167 C | callee-allocated save area |
9168 | for register varargs |
9170 +-------------------------------+ <-- frame_pointer_rtx
9171 | | + cop0_sp_offset
9172 | COP0 reg save area | + UNITS_PER_WORD
9174 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
9175 | | + UNITS_PER_WORD
9176 | accumulator save area |
9178 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
9179 | | + UNITS_PER_HWFPVALUE
9182 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset
9183 | | + UNITS_PER_WORD
9186 +-------------------------------+ <-- frame_pointer_rtx with
9187 | | \ -fstack-protector
9188 | local variables | | var_size
9190 +-------------------------------+
9192 | $gp save area | | cprestore_size
9194 P +-------------------------------+ <-- hard_frame_pointer_rtx for
9196 | outgoing stack arguments | |
9198 +-------------------------------+ | args_size
9200 | caller-allocated save area | |
9201 | for register arguments | |
9203 +-------------------------------+ <-- stack_pointer_rtx
9204 frame_pointer_rtx without
9206 hard_frame_pointer_rtx for
9209 At least two of A, B and C will be empty.
9211 Dynamic stack allocations such as alloca insert data at point P.
9212 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
9213 hard_frame_pointer_rtx unchanged. */
9216 mips_compute_frame_info (void)
9218 struct mips_frame_info *frame;
9219 HOST_WIDE_INT offset, size;
9220 unsigned int regno, i;
9222 /* Set this function's interrupt properties. */
9223 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
9226 error ("the %<interrupt%> attribute requires a MIPS32r2 processor");
9227 else if (TARGET_HARD_FLOAT)
9228 error ("the %<interrupt%> attribute requires %<-msoft-float%>");
9229 else if (TARGET_MIPS16)
9230 error ("interrupt handlers cannot be MIPS16 functions");
9233 cfun->machine->interrupt_handler_p = true;
9234 cfun->machine->use_shadow_register_set_p =
9235 mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl));
9236 cfun->machine->keep_interrupts_masked_p =
9237 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl));
9238 cfun->machine->use_debug_exception_return_p =
9239 mips_use_debug_exception_return_p (TREE_TYPE
9240 (current_function_decl));
9244 frame = &cfun->machine->frame;
9245 memset (frame, 0, sizeof (*frame));
9246 size = get_frame_size ();
9248 cfun->machine->global_pointer = mips_global_pointer ();
9250 /* The first two blocks contain the outgoing argument area and the $gp save
9251 slot. This area isn't needed in leaf functions, but if the
9252 target-independent frame size is nonzero, we have already committed to
9253 allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */
9254 if ((size == 0 || FRAME_GROWS_DOWNWARD) && current_function_is_leaf)
9256 /* The MIPS 3.0 linker does not like functions that dynamically
9257 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
9258 looks like we are trying to create a second frame pointer to the
9259 function, so allocate some stack space to make it happy. */
9260 if (cfun->calls_alloca)
9261 frame->args_size = REG_PARM_STACK_SPACE (cfun->decl);
9263 frame->args_size = 0;
9264 frame->cprestore_size = 0;
9268 frame->args_size = crtl->outgoing_args_size;
9269 frame->cprestore_size = MIPS_GP_SAVE_AREA_SIZE;
9271 offset = frame->args_size + frame->cprestore_size;
9273 /* Move above the local variables. */
9274 frame->var_size = MIPS_STACK_ALIGN (size);
9275 offset += frame->var_size;
9277 /* Find out which GPRs we need to save. */
9278 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
9279 if (mips_save_reg_p (regno))
9282 frame->mask |= 1 << (regno - GP_REG_FIRST);
9285 /* If this function calls eh_return, we must also save and restore the
9286 EH data registers. */
9287 if (crtl->calls_eh_return)
9288 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; i++)
9291 frame->mask |= 1 << (EH_RETURN_DATA_REGNO (i) - GP_REG_FIRST);
9294 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
9295 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
9296 save all later registers too. */
9297 if (GENERATE_MIPS16E_SAVE_RESTORE)
9299 mips16e_mask_registers (&frame->mask, mips16e_s2_s8_regs,
9300 ARRAY_SIZE (mips16e_s2_s8_regs), &frame->num_gp);
9301 mips16e_mask_registers (&frame->mask, mips16e_a0_a3_regs,
9302 ARRAY_SIZE (mips16e_a0_a3_regs), &frame->num_gp);
9305 /* Move above the GPR save area. */
9306 if (frame->num_gp > 0)
9308 offset += MIPS_STACK_ALIGN (frame->num_gp * UNITS_PER_WORD);
9309 frame->gp_sp_offset = offset - UNITS_PER_WORD;
9312 /* Find out which FPRs we need to save. This loop must iterate over
9313 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
9314 if (TARGET_HARD_FLOAT)
9315 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += MAX_FPRS_PER_FMT)
9316 if (mips_save_reg_p (regno))
9318 frame->num_fp += MAX_FPRS_PER_FMT;
9319 frame->fmask |= ~(~0 << MAX_FPRS_PER_FMT) << (regno - FP_REG_FIRST);
9322 /* Move above the FPR save area. */
9323 if (frame->num_fp > 0)
9325 offset += MIPS_STACK_ALIGN (frame->num_fp * UNITS_PER_FPREG);
9326 frame->fp_sp_offset = offset - UNITS_PER_HWFPVALUE;
9329 /* Add in space for the interrupt context information. */
9330 if (cfun->machine->interrupt_handler_p)
9333 if (mips_save_reg_p (LO_REGNUM) || mips_save_reg_p (HI_REGNUM))
9336 frame->acc_mask |= (1 << 0);
9339 /* Check accumulators 1, 2, 3. */
9340 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
9341 if (mips_save_reg_p (i) || mips_save_reg_p (i + 1))
9344 frame->acc_mask |= 1 << (((i - DSP_ACC_REG_FIRST) / 2) + 1);
9347 /* All interrupt context functions need space to preserve STATUS. */
9348 frame->num_cop0_regs++;
9350 /* If we don't keep interrupts masked, we need to save EPC. */
9351 if (!cfun->machine->keep_interrupts_masked_p)
9352 frame->num_cop0_regs++;
9355 /* Move above the accumulator save area. */
9356 if (frame->num_acc > 0)
9358 /* Each accumulator needs 2 words. */
9359 offset += frame->num_acc * 2 * UNITS_PER_WORD;
9360 frame->acc_sp_offset = offset - UNITS_PER_WORD;
9363 /* Move above the COP0 register save area. */
9364 if (frame->num_cop0_regs > 0)
9366 offset += frame->num_cop0_regs * UNITS_PER_WORD;
9367 frame->cop0_sp_offset = offset - UNITS_PER_WORD;
9370 /* Move above the callee-allocated varargs save area. */
9371 offset += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
9372 frame->arg_pointer_offset = offset;
9374 /* Move above the callee-allocated area for pretend stack arguments. */
9375 offset += crtl->args.pretend_args_size;
9376 frame->total_size = offset;
9378 /* Work out the offsets of the save areas from the top of the frame. */
9379 if (frame->gp_sp_offset > 0)
9380 frame->gp_save_offset = frame->gp_sp_offset - offset;
9381 if (frame->fp_sp_offset > 0)
9382 frame->fp_save_offset = frame->fp_sp_offset - offset;
9383 if (frame->acc_sp_offset > 0)
9384 frame->acc_save_offset = frame->acc_sp_offset - offset;
9385 if (frame->num_cop0_regs > 0)
9386 frame->cop0_save_offset = frame->cop0_sp_offset - offset;
9388 /* MIPS16 code offsets the frame pointer by the size of the outgoing
9389 arguments. This tends to increase the chances of using unextended
9390 instructions for local variables and incoming arguments. */
9392 frame->hard_frame_pointer_offset = frame->args_size;
9395 /* Return the style of GP load sequence that is being used for the
9396 current function. */
9398 enum mips_loadgp_style
9399 mips_current_loadgp_style (void)
9401 if (!TARGET_USE_GOT || cfun->machine->global_pointer == INVALID_REGNUM)
9407 if (TARGET_ABSOLUTE_ABICALLS)
9408 return LOADGP_ABSOLUTE;
9410 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
9413 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
9416 mips_frame_pointer_required (void)
9418 /* If the function contains dynamic stack allocations, we need to
9419 use the frame pointer to access the static parts of the frame. */
9420 if (cfun->calls_alloca)
9423 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
9424 reload may be unable to compute the address of a local variable,
9425 since there is no way to add a large constant to the stack pointer
9426 without using a second temporary register. */
9429 mips_compute_frame_info ();
9430 if (!SMALL_OPERAND (cfun->machine->frame.total_size))
9437 /* Make sure that we're not trying to eliminate to the wrong hard frame
9441 mips_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
9443 return (to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM);
9446 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
9447 or argument pointer. TO is either the stack pointer or hard frame
9451 mips_initial_elimination_offset (int from, int to)
9453 HOST_WIDE_INT offset;
9455 mips_compute_frame_info ();
9457 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */
9460 case FRAME_POINTER_REGNUM:
9461 if (FRAME_GROWS_DOWNWARD)
9462 offset = (cfun->machine->frame.args_size
9463 + cfun->machine->frame.cprestore_size
9464 + cfun->machine->frame.var_size);
9469 case ARG_POINTER_REGNUM:
9470 offset = cfun->machine->frame.arg_pointer_offset;
9477 if (to == HARD_FRAME_POINTER_REGNUM)
9478 offset -= cfun->machine->frame.hard_frame_pointer_offset;
9483 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
9486 mips_extra_live_on_entry (bitmap regs)
9490 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
9491 the global pointer. */
9492 if (!TARGET_ABSOLUTE_ABICALLS)
9493 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
9495 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
9496 the global pointer. */
9498 bitmap_set_bit (regs, MIPS16_PIC_TEMP_REGNUM);
9500 /* See the comment above load_call<mode> for details. */
9501 bitmap_set_bit (regs, GOT_VERSION_REGNUM);
9505 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
9509 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
9514 return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);
9517 /* Emit code to change the current function's return address to
9518 ADDRESS. SCRATCH is available as a scratch register, if needed.
9519 ADDRESS and SCRATCH are both word-mode GPRs. */
9522 mips_set_return_address (rtx address, rtx scratch)
9526 gcc_assert (BITSET_P (cfun->machine->frame.mask, RETURN_ADDR_REGNUM));
9527 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
9528 cfun->machine->frame.gp_sp_offset);
9529 mips_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address);
9532 /* Return true if the current function has a cprestore slot. */
9535 mips_cfun_has_cprestore_slot_p (void)
9537 return (cfun->machine->global_pointer != INVALID_REGNUM
9538 && cfun->machine->frame.cprestore_size > 0);
9541 /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the
9542 cprestore slot. LOAD_P is true if the caller wants to load from
9543 the cprestore slot; it is false if the caller wants to store to
9547 mips_get_cprestore_base_and_offset (rtx *base, HOST_WIDE_INT *offset,
9550 const struct mips_frame_info *frame;
9552 frame = &cfun->machine->frame;
9553 /* .cprestore always uses the stack pointer instead of the frame pointer.
9554 We have a free choice for direct stores for non-MIPS16 functions,
9555 and for MIPS16 functions whose cprestore slot is in range of the
9556 stack pointer. Using the stack pointer would sometimes give more
9557 (early) scheduling freedom, but using the frame pointer would
9558 sometimes give more (late) scheduling freedom. It's hard to
9559 predict which applies to a given function, so let's keep things
9562 Loads must always use the frame pointer in functions that call
9563 alloca, and there's little benefit to using the stack pointer
9565 if (frame_pointer_needed && !(TARGET_CPRESTORE_DIRECTIVE && !load_p))
9567 *base = hard_frame_pointer_rtx;
9568 *offset = frame->args_size - frame->hard_frame_pointer_offset;
9572 *base = stack_pointer_rtx;
9573 *offset = frame->args_size;
9577 /* Return true if X is the load or store address of the cprestore slot;
9578 LOAD_P says which. */
9581 mips_cprestore_address_p (rtx x, bool load_p)
9583 rtx given_base, required_base;
9584 HOST_WIDE_INT given_offset, required_offset;
9586 mips_split_plus (x, &given_base, &given_offset);
9587 mips_get_cprestore_base_and_offset (&required_base, &required_offset, load_p);
9588 return given_base == required_base && given_offset == required_offset;
9591 /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are
9592 going to load from it, false if we are going to store to it.
9593 Use TEMP as a temporary register if need be. */
9596 mips_cprestore_slot (rtx temp, bool load_p)
9599 HOST_WIDE_INT offset;
9601 mips_get_cprestore_base_and_offset (&base, &offset, load_p);
9602 return gen_frame_mem (Pmode, mips_add_offset (temp, base, offset));
9605 /* Emit instructions to save global pointer value GP into cprestore
9606 slot MEM. OFFSET is the offset that MEM applies to the base register.
9608 MEM may not be a legitimate address. If it isn't, TEMP is a
9609 temporary register that can be used, otherwise it is a SCRATCH. */
9612 mips_save_gp_to_cprestore_slot (rtx mem, rtx offset, rtx gp, rtx temp)
9614 if (TARGET_CPRESTORE_DIRECTIVE)
9616 gcc_assert (gp == pic_offset_table_rtx);
9617 emit_insn (gen_cprestore (mem, offset));
9620 mips_emit_move (mips_cprestore_slot (temp, false), gp);
9623 /* Restore $gp from its save slot, using TEMP as a temporary base register
9624 if need be. This function is for o32 and o64 abicalls only.
9626 See mips_must_initialize_gp_p for details about how we manage the
9630 mips_restore_gp_from_cprestore_slot (rtx temp)
9632 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI && epilogue_completed);
9634 if (!cfun->machine->must_restore_gp_when_clobbered_p)
9636 emit_note (NOTE_INSN_DELETED);
9642 mips_emit_move (temp, mips_cprestore_slot (temp, true));
9643 mips_emit_move (pic_offset_table_rtx, temp);
9646 mips_emit_move (pic_offset_table_rtx, mips_cprestore_slot (temp, true));
9647 if (!TARGET_EXPLICIT_RELOCS)
9648 emit_insn (gen_blockage ());
9651 /* A function to save or store a register. The first argument is the
9652 register and the second is the stack slot. */
9653 typedef void (*mips_save_restore_fn) (rtx, rtx);
9655 /* Use FN to save or restore register REGNO. MODE is the register's
9656 mode and OFFSET is the offset of its save slot from the current
9660 mips_save_restore_reg (enum machine_mode mode, int regno,
9661 HOST_WIDE_INT offset, mips_save_restore_fn fn)
9665 mem = gen_frame_mem (mode, plus_constant (stack_pointer_rtx, offset));
9666 fn (gen_rtx_REG (mode, regno), mem);
9669 /* Call FN for each accumlator that is saved by the current function.
9670 SP_OFFSET is the offset of the current stack pointer from the start
9674 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
9676 HOST_WIDE_INT offset;
9679 offset = cfun->machine->frame.acc_sp_offset - sp_offset;
9680 if (BITSET_P (cfun->machine->frame.acc_mask, 0))
9682 mips_save_restore_reg (word_mode, LO_REGNUM, offset, fn);
9683 offset -= UNITS_PER_WORD;
9684 mips_save_restore_reg (word_mode, HI_REGNUM, offset, fn);
9685 offset -= UNITS_PER_WORD;
9688 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
9689 if (BITSET_P (cfun->machine->frame.acc_mask,
9690 ((regno - DSP_ACC_REG_FIRST) / 2) + 1))
9692 mips_save_restore_reg (word_mode, regno, offset, fn);
9693 offset -= UNITS_PER_WORD;
9697 /* Call FN for each register that is saved by the current function.
9698 SP_OFFSET is the offset of the current stack pointer from the start
9702 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset,
9703 mips_save_restore_fn fn)
9705 enum machine_mode fpr_mode;
9706 HOST_WIDE_INT offset;
9709 /* Save registers starting from high to low. The debuggers prefer at least
9710 the return register be stored at func+4, and also it allows us not to
9711 need a nop in the epilogue if at least one register is reloaded in
9712 addition to return address. */
9713 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
9714 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
9715 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
9717 /* Record the ra offset for use by mips_function_profiler. */
9718 if (regno == RETURN_ADDR_REGNUM)
9719 cfun->machine->frame.ra_fp_offset = offset + sp_offset;
9720 mips_save_restore_reg (word_mode, regno, offset, fn);
9721 offset -= UNITS_PER_WORD;
9724 /* This loop must iterate over the same space as its companion in
9725 mips_compute_frame_info. */
9726 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
9727 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
9728 for (regno = FP_REG_LAST - MAX_FPRS_PER_FMT + 1;
9729 regno >= FP_REG_FIRST;
9730 regno -= MAX_FPRS_PER_FMT)
9731 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
9733 mips_save_restore_reg (fpr_mode, regno, offset, fn);
9734 offset -= GET_MODE_SIZE (fpr_mode);
9738 /* Return true if a move between register REGNO and its save slot (MEM)
9739 can be done in a single move. LOAD_P is true if we are loading
9740 from the slot, false if we are storing to it. */
9743 mips_direct_save_slot_move_p (unsigned int regno, rtx mem, bool load_p)
9745 /* There is a specific MIPS16 instruction for saving $31 to the stack. */
9746 if (TARGET_MIPS16 && !load_p && regno == RETURN_ADDR_REGNUM)
9749 return mips_secondary_reload_class (REGNO_REG_CLASS (regno),
9750 GET_MODE (mem), mem, load_p) == NO_REGS;
9753 /* Emit a move from SRC to DEST, given that one of them is a register
9754 save slot and that the other is a register. TEMP is a temporary
9755 GPR of the same mode that is available if need be. */
9758 mips_emit_save_slot_move (rtx dest, rtx src, rtx temp)
9765 regno = REGNO (src);
9770 regno = REGNO (dest);
9774 if (regno == cfun->machine->global_pointer && !mips_must_initialize_gp_p ())
9776 /* We don't yet know whether we'll need this instruction or not.
9777 Postpone the decision by emitting a ghost move. This move
9778 is specifically not frame-related; only the split version is. */
9780 emit_insn (gen_move_gpdi (dest, src));
9782 emit_insn (gen_move_gpsi (dest, src));
9786 if (regno == HI_REGNUM)
9790 mips_emit_move (temp, src);
9792 emit_insn (gen_mthisi_di (gen_rtx_REG (TImode, MD_REG_FIRST),
9793 temp, gen_rtx_REG (DImode, LO_REGNUM)));
9795 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode, MD_REG_FIRST),
9796 temp, gen_rtx_REG (SImode, LO_REGNUM)));
9801 emit_insn (gen_mfhidi_ti (temp,
9802 gen_rtx_REG (TImode, MD_REG_FIRST)));
9804 emit_insn (gen_mfhisi_di (temp,
9805 gen_rtx_REG (DImode, MD_REG_FIRST)));
9806 mips_emit_move (dest, temp);
9809 else if (mips_direct_save_slot_move_p (regno, mem, mem == src))
9810 mips_emit_move (dest, src);
9813 gcc_assert (!reg_overlap_mentioned_p (dest, temp));
9814 mips_emit_move (temp, src);
9815 mips_emit_move (dest, temp);
9818 mips_set_frame_expr (mips_frame_set (dest, src));
9821 /* If we're generating n32 or n64 abicalls, and the current function
9822 does not use $28 as its global pointer, emit a cplocal directive.
9823 Use pic_offset_table_rtx as the argument to the directive. */
9826 mips_output_cplocal (void)
9828 if (!TARGET_EXPLICIT_RELOCS
9829 && mips_must_initialize_gp_p ()
9830 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
9831 output_asm_insn (".cplocal %+", 0);
9834 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
9837 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9841 #ifdef SDB_DEBUGGING_INFO
9842 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
9843 SDB_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
9846 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
9847 floating-point arguments. */
9849 && TARGET_HARD_FLOAT_ABI
9850 && crtl->args.info.fp_code != 0)
9851 mips16_build_function_stub ();
9853 /* Get the function name the same way that toplev.c does before calling
9854 assemble_start_function. This is needed so that the name used here
9855 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
9856 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
9857 mips_start_function_definition (fnname, TARGET_MIPS16);
9859 /* Output MIPS-specific frame information. */
9860 if (!flag_inhibit_size_directive)
9862 const struct mips_frame_info *frame;
9864 frame = &cfun->machine->frame;
9866 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
9868 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
9869 "# vars= " HOST_WIDE_INT_PRINT_DEC
9871 ", args= " HOST_WIDE_INT_PRINT_DEC
9872 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
9873 reg_names[frame_pointer_needed
9874 ? HARD_FRAME_POINTER_REGNUM
9875 : STACK_POINTER_REGNUM],
9876 (frame_pointer_needed
9877 ? frame->total_size - frame->hard_frame_pointer_offset
9878 : frame->total_size),
9879 reg_names[RETURN_ADDR_REGNUM],
9881 frame->num_gp, frame->num_fp,
9883 frame->cprestore_size);
9885 /* .mask MASK, OFFSET. */
9886 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
9887 frame->mask, frame->gp_save_offset);
9889 /* .fmask MASK, OFFSET. */
9890 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
9891 frame->fmask, frame->fp_save_offset);
9894 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
9895 Also emit the ".set noreorder; .set nomacro" sequence for functions
9897 if (mips_must_initialize_gp_p ()
9898 && mips_current_loadgp_style () == LOADGP_OLDABI)
9902 /* This is a fixed-form sequence. The position of the
9903 first two instructions is important because of the
9904 way _gp_disp is defined. */
9905 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
9906 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
9907 output_asm_insn ("sll\t$2,16", 0);
9908 output_asm_insn ("addu\t$2,$3", 0);
9912 /* .cpload must be in a .set noreorder but not a
9913 .set nomacro block. */
9914 mips_push_asm_switch (&mips_noreorder);
9915 output_asm_insn (".cpload\t%^", 0);
9916 if (!cfun->machine->all_noreorder_p)
9917 mips_pop_asm_switch (&mips_noreorder);
9919 mips_push_asm_switch (&mips_nomacro);
9922 else if (cfun->machine->all_noreorder_p)
9924 mips_push_asm_switch (&mips_noreorder);
9925 mips_push_asm_switch (&mips_nomacro);
9928 /* Tell the assembler which register we're using as the global
9929 pointer. This is needed for thunks, since they can use either
9930 explicit relocs or assembler macros. */
9931 mips_output_cplocal ();
9934 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
9937 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
9938 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9942 /* Reinstate the normal $gp. */
9943 SET_REGNO (pic_offset_table_rtx, GLOBAL_POINTER_REGNUM);
9944 mips_output_cplocal ();
9946 if (cfun->machine->all_noreorder_p)
9948 mips_pop_asm_switch (&mips_nomacro);
9949 mips_pop_asm_switch (&mips_noreorder);
9952 /* Get the function name the same way that toplev.c does before calling
9953 assemble_start_function. This is needed so that the name used here
9954 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
9955 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
9956 mips_end_function_definition (fnname);
9959 /* Save register REG to MEM. Make the instruction frame-related. */
9962 mips_save_reg (rtx reg, rtx mem)
9964 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
9968 if (mips_split_64bit_move_p (mem, reg))
9969 mips_split_doubleword_move (mem, reg);
9971 mips_emit_move (mem, reg);
9973 x1 = mips_frame_set (mips_subword (mem, false),
9974 mips_subword (reg, false));
9975 x2 = mips_frame_set (mips_subword (mem, true),
9976 mips_subword (reg, true));
9977 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
9980 mips_emit_save_slot_move (mem, reg, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
9983 /* The __gnu_local_gp symbol. */
9985 static GTY(()) rtx mips_gnu_local_gp;
9987 /* If we're generating n32 or n64 abicalls, emit instructions
9988 to set up the global pointer. */
9991 mips_emit_loadgp (void)
9993 rtx addr, offset, incoming_address, base, index, pic_reg;
9995 pic_reg = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
9996 switch (mips_current_loadgp_style ())
9998 case LOADGP_ABSOLUTE:
9999 if (mips_gnu_local_gp == NULL)
10001 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
10002 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
10004 emit_insn (Pmode == SImode
10005 ? gen_loadgp_absolute_si (pic_reg, mips_gnu_local_gp)
10006 : gen_loadgp_absolute_di (pic_reg, mips_gnu_local_gp));
10009 case LOADGP_OLDABI:
10010 /* Added by mips_output_function_prologue. */
10013 case LOADGP_NEWABI:
10014 addr = XEXP (DECL_RTL (current_function_decl), 0);
10015 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
10016 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
10017 emit_insn (Pmode == SImode
10018 ? gen_loadgp_newabi_si (pic_reg, offset, incoming_address)
10019 : gen_loadgp_newabi_di (pic_reg, offset, incoming_address));
10023 base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE));
10024 index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX));
10025 emit_insn (Pmode == SImode
10026 ? gen_loadgp_rtp_si (pic_reg, base, index)
10027 : gen_loadgp_rtp_di (pic_reg, base, index));
10035 emit_insn (gen_copygp_mips16 (pic_offset_table_rtx, pic_reg));
10037 /* Emit a blockage if there are implicit uses of the GP register.
10038 This includes profiled functions, because FUNCTION_PROFILE uses
10040 if (!TARGET_EXPLICIT_RELOCS || crtl->profile)
10041 emit_insn (gen_loadgp_blockage ());
10044 /* A for_each_rtx callback. Stop the search if *X is a kernel register. */
10047 mips_kernel_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
10049 return REG_P (*x) && KERNEL_REG_P (REGNO (*x));
10052 /* Expand the "prologue" pattern. */
10055 mips_expand_prologue (void)
10057 const struct mips_frame_info *frame;
10058 HOST_WIDE_INT size;
10059 unsigned int nargs;
10062 if (cfun->machine->global_pointer != INVALID_REGNUM)
10064 /* Check whether an insn uses pic_offset_table_rtx, either explicitly
10065 or implicitly. If so, we can commit to using a global pointer
10066 straight away, otherwise we need to defer the decision. */
10067 if (mips_cfun_has_inflexible_gp_ref_p ()
10068 || mips_cfun_has_flexible_gp_ref_p ())
10070 cfun->machine->must_initialize_gp_p = true;
10071 cfun->machine->must_restore_gp_when_clobbered_p = true;
10074 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
10077 frame = &cfun->machine->frame;
10078 size = frame->total_size;
10080 if (flag_stack_usage)
10081 current_function_static_stack_size = size;
10083 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
10084 bytes beforehand; this is enough to cover the register save area
10085 without going out of range. */
10086 if (((frame->mask | frame->fmask | frame->acc_mask) != 0)
10087 || frame->num_cop0_regs > 0)
10089 HOST_WIDE_INT step1;
10091 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
10092 if (GENERATE_MIPS16E_SAVE_RESTORE)
10094 HOST_WIDE_INT offset;
10095 unsigned int mask, regno;
10097 /* Try to merge argument stores into the save instruction. */
10098 nargs = mips16e_collect_argument_saves ();
10100 /* Build the save instruction. */
10101 mask = frame->mask;
10102 insn = mips16e_build_save_restore (false, &mask, &offset,
10104 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10107 /* Check if we need to save other registers. */
10108 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
10109 if (BITSET_P (mask, regno - GP_REG_FIRST))
10111 offset -= UNITS_PER_WORD;
10112 mips_save_restore_reg (word_mode, regno,
10113 offset, mips_save_reg);
10118 if (cfun->machine->interrupt_handler_p)
10120 HOST_WIDE_INT offset;
10123 /* If this interrupt is using a shadow register set, we need to
10124 get the stack pointer from the previous register set. */
10125 if (cfun->machine->use_shadow_register_set_p)
10126 emit_insn (gen_mips_rdpgpr (stack_pointer_rtx,
10127 stack_pointer_rtx));
10129 if (!cfun->machine->keep_interrupts_masked_p)
10131 /* Move from COP0 Cause to K0. */
10132 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K0_REG_NUM),
10133 gen_rtx_REG (SImode,
10134 COP0_CAUSE_REG_NUM)));
10135 /* Move from COP0 EPC to K1. */
10136 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
10137 gen_rtx_REG (SImode,
10138 COP0_EPC_REG_NUM)));
10141 /* Allocate the first part of the frame. */
10142 insn = gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx,
10144 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10147 /* Start at the uppermost location for saving. */
10148 offset = frame->cop0_sp_offset - size;
10149 if (!cfun->machine->keep_interrupts_masked_p)
10151 /* Push EPC into its stack slot. */
10152 mem = gen_frame_mem (word_mode,
10153 plus_constant (stack_pointer_rtx,
10155 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
10156 offset -= UNITS_PER_WORD;
10159 /* Move from COP0 Status to K1. */
10160 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
10161 gen_rtx_REG (SImode,
10162 COP0_STATUS_REG_NUM)));
10164 /* Right justify the RIPL in k0. */
10165 if (!cfun->machine->keep_interrupts_masked_p)
10166 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode, K0_REG_NUM),
10167 gen_rtx_REG (SImode, K0_REG_NUM),
10168 GEN_INT (CAUSE_IPL)));
10170 /* Push Status into its stack slot. */
10171 mem = gen_frame_mem (word_mode,
10172 plus_constant (stack_pointer_rtx, offset));
10173 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
10174 offset -= UNITS_PER_WORD;
10176 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
10177 if (!cfun->machine->keep_interrupts_masked_p)
10178 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
10181 gen_rtx_REG (SImode, K0_REG_NUM)));
10183 if (!cfun->machine->keep_interrupts_masked_p)
10184 /* Enable interrupts by clearing the KSU ERL and EXL bits.
10185 IE is already the correct value, so we don't have to do
10186 anything explicit. */
10187 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
10190 gen_rtx_REG (SImode, GP_REG_FIRST)));
10192 /* Disable interrupts by clearing the KSU, ERL, EXL,
10194 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
10197 gen_rtx_REG (SImode, GP_REG_FIRST)));
10201 insn = gen_add3_insn (stack_pointer_rtx,
10204 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10207 mips_for_each_saved_acc (size, mips_save_reg);
10208 mips_for_each_saved_gpr_and_fpr (size, mips_save_reg);
10212 /* Allocate the rest of the frame. */
10215 if (SMALL_OPERAND (-size))
10216 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
10218 GEN_INT (-size)))) = 1;
10221 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
10224 /* There are no instructions to add or subtract registers
10225 from the stack pointer, so use the frame pointer as a
10226 temporary. We should always be using a frame pointer
10227 in this case anyway. */
10228 gcc_assert (frame_pointer_needed);
10229 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
10230 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
10231 hard_frame_pointer_rtx,
10232 MIPS_PROLOGUE_TEMP (Pmode)));
10233 mips_emit_move (stack_pointer_rtx, hard_frame_pointer_rtx);
10236 emit_insn (gen_sub3_insn (stack_pointer_rtx,
10238 MIPS_PROLOGUE_TEMP (Pmode)));
10240 /* Describe the combined effect of the previous instructions. */
10241 mips_set_frame_expr
10242 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
10243 plus_constant (stack_pointer_rtx, -size)));
10247 /* Set up the frame pointer, if we're using one. */
10248 if (frame_pointer_needed)
10250 HOST_WIDE_INT offset;
10252 offset = frame->hard_frame_pointer_offset;
10255 insn = mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
10256 RTX_FRAME_RELATED_P (insn) = 1;
10258 else if (SMALL_OPERAND (offset))
10260 insn = gen_add3_insn (hard_frame_pointer_rtx,
10261 stack_pointer_rtx, GEN_INT (offset));
10262 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10266 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (offset));
10267 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
10268 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
10269 hard_frame_pointer_rtx,
10270 MIPS_PROLOGUE_TEMP (Pmode)));
10271 mips_set_frame_expr
10272 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
10273 plus_constant (stack_pointer_rtx, offset)));
10277 mips_emit_loadgp ();
10279 /* Initialize the $gp save slot. */
10280 if (mips_cfun_has_cprestore_slot_p ())
10282 rtx base, mem, gp, temp;
10283 HOST_WIDE_INT offset;
10285 mips_get_cprestore_base_and_offset (&base, &offset, false);
10286 mem = gen_frame_mem (Pmode, plus_constant (base, offset));
10287 gp = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
10288 temp = (SMALL_OPERAND (offset)
10289 ? gen_rtx_SCRATCH (Pmode)
10290 : MIPS_PROLOGUE_TEMP (Pmode));
10291 emit_insn (gen_potential_cprestore (mem, GEN_INT (offset), gp, temp));
10293 mips_get_cprestore_base_and_offset (&base, &offset, true);
10294 mem = gen_frame_mem (Pmode, plus_constant (base, offset));
10295 emit_insn (gen_use_cprestore (mem));
10298 /* We need to search back to the last use of K0 or K1. */
10299 if (cfun->machine->interrupt_handler_p)
10301 for (insn = get_last_insn (); insn != NULL_RTX; insn = PREV_INSN (insn))
10303 && for_each_rtx (&PATTERN (insn), mips_kernel_reg_p, NULL))
10305 /* Emit a move from K1 to COP0 Status after insn. */
10306 gcc_assert (insn != NULL_RTX);
10307 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
10308 gen_rtx_REG (SImode, K1_REG_NUM)),
10312 /* If we are profiling, make sure no instructions are scheduled before
10313 the call to mcount. */
10315 emit_insn (gen_blockage ());
10318 /* Emit instructions to restore register REG from slot MEM. */
10321 mips_restore_reg (rtx reg, rtx mem)
10323 /* There's no MIPS16 instruction to load $31 directly. Load into
10324 $7 instead and adjust the return insn appropriately. */
10325 if (TARGET_MIPS16 && REGNO (reg) == RETURN_ADDR_REGNUM)
10326 reg = gen_rtx_REG (GET_MODE (reg), GP_REG_FIRST + 7);
10328 mips_emit_save_slot_move (reg, mem, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
10331 /* Emit any instructions needed before a return. */
10334 mips_expand_before_return (void)
10336 /* When using a call-clobbered gp, we start out with unified call
10337 insns that include instructions to restore the gp. We then split
10338 these unified calls after reload. These split calls explicitly
10339 clobber gp, so there is no need to define
10340 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
10342 For consistency, we should also insert an explicit clobber of $28
10343 before return insns, so that the post-reload optimizers know that
10344 the register is not live on exit. */
10345 if (TARGET_CALL_CLOBBERED_GP)
10346 emit_clobber (pic_offset_table_rtx);
10349 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
10353 mips_expand_epilogue (bool sibcall_p)
10355 const struct mips_frame_info *frame;
10356 HOST_WIDE_INT step1, step2;
10357 rtx base, target, insn;
10359 if (!sibcall_p && mips_can_use_return_insn ())
10361 emit_jump_insn (gen_return ());
10365 /* In MIPS16 mode, if the return value should go into a floating-point
10366 register, we need to call a helper routine to copy it over. */
10367 if (mips16_cfun_returns_in_fpr_p ())
10368 mips16_copy_fpr_return_value ();
10370 /* Split the frame into two. STEP1 is the amount of stack we should
10371 deallocate before restoring the registers. STEP2 is the amount we
10372 should deallocate afterwards.
10374 Start off by assuming that no registers need to be restored. */
10375 frame = &cfun->machine->frame;
10376 step1 = frame->total_size;
10379 /* Work out which register holds the frame address. */
10380 if (!frame_pointer_needed)
10381 base = stack_pointer_rtx;
10384 base = hard_frame_pointer_rtx;
10385 step1 -= frame->hard_frame_pointer_offset;
10388 /* If we need to restore registers, deallocate as much stack as
10389 possible in the second step without going out of range. */
10390 if ((frame->mask | frame->fmask | frame->acc_mask) != 0
10391 || frame->num_cop0_regs > 0)
10393 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
10397 /* Set TARGET to BASE + STEP1. */
10403 /* Get an rtx for STEP1 that we can add to BASE. */
10404 adjust = GEN_INT (step1);
10405 if (!SMALL_OPERAND (step1))
10407 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), adjust);
10408 adjust = MIPS_EPILOGUE_TEMP (Pmode);
10411 /* Normal mode code can copy the result straight into $sp. */
10412 if (!TARGET_MIPS16)
10413 target = stack_pointer_rtx;
10415 emit_insn (gen_add3_insn (target, base, adjust));
10418 /* Copy TARGET into the stack pointer. */
10419 if (target != stack_pointer_rtx)
10420 mips_emit_move (stack_pointer_rtx, target);
10422 /* If we're using addressing macros, $gp is implicitly used by all
10423 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
10425 if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS)
10426 emit_insn (gen_blockage ());
10428 if (GENERATE_MIPS16E_SAVE_RESTORE && frame->mask != 0)
10430 unsigned int regno, mask;
10431 HOST_WIDE_INT offset;
10434 /* Generate the restore instruction. */
10435 mask = frame->mask;
10436 restore = mips16e_build_save_restore (true, &mask, &offset, 0, step2);
10438 /* Restore any other registers manually. */
10439 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
10440 if (BITSET_P (mask, regno - GP_REG_FIRST))
10442 offset -= UNITS_PER_WORD;
10443 mips_save_restore_reg (word_mode, regno, offset, mips_restore_reg);
10446 /* Restore the remaining registers and deallocate the final bit
10448 emit_insn (restore);
10452 /* Restore the registers. */
10453 mips_for_each_saved_acc (frame->total_size - step2, mips_restore_reg);
10454 mips_for_each_saved_gpr_and_fpr (frame->total_size - step2,
10457 if (cfun->machine->interrupt_handler_p)
10459 HOST_WIDE_INT offset;
10462 offset = frame->cop0_sp_offset - (frame->total_size - step2);
10463 if (!cfun->machine->keep_interrupts_masked_p)
10465 /* Restore the original EPC. */
10466 mem = gen_frame_mem (word_mode,
10467 plus_constant (stack_pointer_rtx, offset));
10468 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
10469 offset -= UNITS_PER_WORD;
10471 /* Move to COP0 EPC. */
10472 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_EPC_REG_NUM),
10473 gen_rtx_REG (SImode, K0_REG_NUM)));
10476 /* Restore the original Status. */
10477 mem = gen_frame_mem (word_mode,
10478 plus_constant (stack_pointer_rtx, offset));
10479 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
10480 offset -= UNITS_PER_WORD;
10482 /* If we don't use shoadow register set, we need to update SP. */
10483 if (!cfun->machine->use_shadow_register_set_p && step2 > 0)
10484 emit_insn (gen_add3_insn (stack_pointer_rtx,
10488 /* Move to COP0 Status. */
10489 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
10490 gen_rtx_REG (SImode, K0_REG_NUM)));
10494 /* Deallocate the final bit of the frame. */
10496 emit_insn (gen_add3_insn (stack_pointer_rtx,
10502 /* Add in the __builtin_eh_return stack adjustment. We need to
10503 use a temporary in MIPS16 code. */
10504 if (crtl->calls_eh_return)
10508 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
10509 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
10510 MIPS_EPILOGUE_TEMP (Pmode),
10511 EH_RETURN_STACKADJ_RTX));
10512 mips_emit_move (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
10515 emit_insn (gen_add3_insn (stack_pointer_rtx,
10517 EH_RETURN_STACKADJ_RTX));
10522 mips_expand_before_return ();
10523 if (cfun->machine->interrupt_handler_p)
10525 /* Interrupt handlers generate eret or deret. */
10526 if (cfun->machine->use_debug_exception_return_p)
10527 emit_jump_insn (gen_mips_deret ());
10529 emit_jump_insn (gen_mips_eret ());
10533 unsigned int regno;
10535 /* When generating MIPS16 code, the normal
10536 mips_for_each_saved_gpr_and_fpr path will restore the return
10537 address into $7 rather than $31. */
10539 && !GENERATE_MIPS16E_SAVE_RESTORE
10540 && BITSET_P (frame->mask, RETURN_ADDR_REGNUM))
10541 regno = GP_REG_FIRST + 7;
10543 regno = RETURN_ADDR_REGNUM;
10544 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, regno)));
10548 /* Search from the beginning to the first use of K0 or K1. */
10549 if (cfun->machine->interrupt_handler_p
10550 && !cfun->machine->keep_interrupts_masked_p)
10552 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
10554 && for_each_rtx (&PATTERN(insn), mips_kernel_reg_p, NULL))
10556 gcc_assert (insn != NULL_RTX);
10557 /* Insert disable interrupts before the first use of K0 or K1. */
10558 emit_insn_before (gen_mips_di (), insn);
10559 emit_insn_before (gen_mips_ehb (), insn);
10563 /* Return nonzero if this function is known to have a null epilogue.
10564 This allows the optimizer to omit jumps to jumps if no stack
10568 mips_can_use_return_insn (void)
10570 /* Interrupt handlers need to go through the epilogue. */
10571 if (cfun->machine->interrupt_handler_p)
10574 if (!reload_completed)
10580 /* In MIPS16 mode, a function that returns a floating-point value
10581 needs to arrange to copy the return value into the floating-point
10583 if (mips16_cfun_returns_in_fpr_p ())
10586 return cfun->machine->frame.total_size == 0;
10589 /* Return true if register REGNO can store a value of mode MODE.
10590 The result of this function is cached in mips_hard_regno_mode_ok. */
10593 mips_hard_regno_mode_ok_p (unsigned int regno, enum machine_mode mode)
10596 enum mode_class mclass;
10598 if (mode == CCV2mode)
10599 return (ISA_HAS_8CC
10600 && ST_REG_P (regno)
10601 && (regno - ST_REG_FIRST) % 2 == 0);
10603 if (mode == CCV4mode)
10604 return (ISA_HAS_8CC
10605 && ST_REG_P (regno)
10606 && (regno - ST_REG_FIRST) % 4 == 0);
10608 if (mode == CCmode)
10611 return regno == FPSW_REGNUM;
10613 return (ST_REG_P (regno)
10614 || GP_REG_P (regno)
10615 || FP_REG_P (regno));
10618 size = GET_MODE_SIZE (mode);
10619 mclass = GET_MODE_CLASS (mode);
10621 if (GP_REG_P (regno))
10622 return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD;
10624 if (FP_REG_P (regno)
10625 && (((regno - FP_REG_FIRST) % MAX_FPRS_PER_FMT) == 0
10626 || (MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG)))
10628 /* Allow TFmode for CCmode reloads. */
10629 if (mode == TFmode && ISA_HAS_8CC)
10632 /* Allow 64-bit vector modes for Loongson-2E/2F. */
10633 if (TARGET_LOONGSON_VECTORS
10634 && (mode == V2SImode
10635 || mode == V4HImode
10636 || mode == V8QImode
10637 || mode == DImode))
10640 if (mclass == MODE_FLOAT
10641 || mclass == MODE_COMPLEX_FLOAT
10642 || mclass == MODE_VECTOR_FLOAT)
10643 return size <= UNITS_PER_FPVALUE;
10645 /* Allow integer modes that fit into a single register. We need
10646 to put integers into FPRs when using instructions like CVT
10647 and TRUNC. There's no point allowing sizes smaller than a word,
10648 because the FPU has no appropriate load/store instructions. */
10649 if (mclass == MODE_INT)
10650 return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG;
10653 if (ACC_REG_P (regno)
10654 && (INTEGRAL_MODE_P (mode) || ALL_FIXED_POINT_MODE_P (mode)))
10656 if (MD_REG_P (regno))
10658 /* After a multiplication or division, clobbering HI makes
10659 the value of LO unpredictable, and vice versa. This means
10660 that, for all interesting cases, HI and LO are effectively
10663 We model this by requiring that any value that uses HI
10665 if (size <= UNITS_PER_WORD * 2)
10666 return regno == (size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST);
10670 /* DSP accumulators do not have the same restrictions as
10671 HI and LO, so we can treat them as normal doubleword
10673 if (size <= UNITS_PER_WORD)
10676 if (size <= UNITS_PER_WORD * 2
10677 && ((regno - DSP_ACC_REG_FIRST) & 1) == 0)
10682 if (ALL_COP_REG_P (regno))
10683 return mclass == MODE_INT && size <= UNITS_PER_WORD;
10685 if (regno == GOT_VERSION_REGNUM)
10686 return mode == SImode;
10691 /* Implement HARD_REGNO_NREGS. */
10694 mips_hard_regno_nregs (int regno, enum machine_mode mode)
10696 if (ST_REG_P (regno))
10697 /* The size of FP status registers is always 4, because they only hold
10698 CCmode values, and CCmode is always considered to be 4 bytes wide. */
10699 return (GET_MODE_SIZE (mode) + 3) / 4;
10701 if (FP_REG_P (regno))
10702 return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG;
10704 /* All other registers are word-sized. */
10705 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
10708 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
10709 in mips_hard_regno_nregs. */
10712 mips_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
10718 COPY_HARD_REG_SET (left, reg_class_contents[(int) rclass]);
10719 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS]))
10721 size = MIN (size, 4);
10722 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) ST_REGS]);
10724 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS]))
10726 size = MIN (size, UNITS_PER_FPREG);
10727 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]);
10729 if (!hard_reg_set_empty_p (left))
10730 size = MIN (size, UNITS_PER_WORD);
10731 return (GET_MODE_SIZE (mode) + size - 1) / size;
10734 /* Implement CANNOT_CHANGE_MODE_CLASS. */
10737 mips_cannot_change_mode_class (enum machine_mode from ATTRIBUTE_UNUSED,
10738 enum machine_mode to ATTRIBUTE_UNUSED,
10739 enum reg_class rclass)
10741 /* There are several problems with changing the modes of values
10742 in floating-point registers:
10744 - When a multi-word value is stored in paired floating-point
10745 registers, the first register always holds the low word.
10746 We therefore can't allow FPRs to change between single-word
10747 and multi-word modes on big-endian targets.
10749 - GCC assumes that each word of a multiword register can be accessed
10750 individually using SUBREGs. This is not true for floating-point
10751 registers if they are bigger than a word.
10753 - Loading a 32-bit value into a 64-bit floating-point register
10754 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
10755 We can't allow FPRs to change from SImode to to a wider mode on
10758 - If the FPU has already interpreted a value in one format, we must
10759 not ask it to treat the value as having a different format.
10761 We therefore disallow all mode changes involving FPRs. */
10762 return reg_classes_intersect_p (FP_REGS, rclass);
10765 /* Implement target hook small_register_classes_for_mode_p. */
10768 mips_small_register_classes_for_mode_p (enum machine_mode mode
10771 return TARGET_MIPS16;
10774 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
10777 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode)
10782 return TARGET_HARD_FLOAT;
10785 return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT;
10788 return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT;
10795 /* Implement MODES_TIEABLE_P. */
10798 mips_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
10800 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
10801 prefer to put one of them in FPRs. */
10802 return (mode1 == mode2
10803 || (!mips_mode_ok_for_mov_fmt_p (mode1)
10804 && !mips_mode_ok_for_mov_fmt_p (mode2)));
10807 /* Implement PREFERRED_RELOAD_CLASS. */
10810 mips_preferred_reload_class (rtx x, enum reg_class rclass)
10812 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, rclass))
10815 if (reg_class_subset_p (FP_REGS, rclass)
10816 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x)))
10819 if (reg_class_subset_p (GR_REGS, rclass))
10822 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, rclass))
10828 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
10829 Return a "canonical" class to represent it in later calculations. */
10832 mips_canonicalize_move_class (reg_class_t rclass)
10834 /* All moves involving accumulator registers have the same cost. */
10835 if (reg_class_subset_p (rclass, ACC_REGS))
10838 /* Likewise promote subclasses of general registers to the most
10839 interesting containing class. */
10840 if (TARGET_MIPS16 && reg_class_subset_p (rclass, M16_REGS))
10842 else if (reg_class_subset_p (rclass, GENERAL_REGS))
10843 rclass = GENERAL_REGS;
10848 /* Return the cost of moving a value of mode MODE from a register of
10849 class FROM to a GPR. Return 0 for classes that are unions of other
10850 classes handled by this function. */
10853 mips_move_to_gpr_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
10859 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
10863 /* MFLO and MFHI. */
10871 /* LUI followed by MOVF. */
10877 /* This choice of value is historical. */
10885 /* Return the cost of moving a value of mode MODE from a GPR to a
10886 register of class TO. Return 0 for classes that are unions of
10887 other classes handled by this function. */
10890 mips_move_from_gpr_cost (enum machine_mode mode, reg_class_t to)
10895 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
10899 /* MTLO and MTHI. */
10907 /* A secondary reload through an FPR scratch. */
10908 return (mips_register_move_cost (mode, GENERAL_REGS, FP_REGS)
10909 + mips_register_move_cost (mode, FP_REGS, ST_REGS));
10914 /* This choice of value is historical. */
10922 /* Implement TARGET_REGISTER_MOVE_COST. Return 0 for classes that are the
10923 maximum of the move costs for subclasses; regclass will work out
10924 the maximum for us. */
10927 mips_register_move_cost (enum machine_mode mode,
10928 reg_class_t from, reg_class_t to)
10933 from = mips_canonicalize_move_class (from);
10934 to = mips_canonicalize_move_class (to);
10936 /* Handle moves that can be done without using general-purpose registers. */
10937 if (from == FP_REGS)
10939 if (to == FP_REGS && mips_mode_ok_for_mov_fmt_p (mode))
10943 /* The sequence generated by mips_expand_fcc_reload. */
10947 /* Handle cases in which only one class deviates from the ideal. */
10948 dregs = TARGET_MIPS16 ? M16_REGS : GENERAL_REGS;
10950 return mips_move_from_gpr_cost (mode, to);
10952 return mips_move_to_gpr_cost (mode, from);
10954 /* Handles cases that require a GPR temporary. */
10955 cost1 = mips_move_to_gpr_cost (mode, from);
10958 cost2 = mips_move_from_gpr_cost (mode, to);
10960 return cost1 + cost2;
10966 /* Implement TARGET_MEMORY_MOVE_COST. */
10969 mips_memory_move_cost (enum machine_mode mode, reg_class_t rclass, bool in)
10971 return (mips_cost->memory_latency
10972 + memory_move_secondary_cost (mode, rclass, in));
10975 /* Implement TARGET_IRA_COVER_CLASSES. */
10977 static const reg_class_t *
10978 mips_ira_cover_classes (void)
10980 static const reg_class_t acc_classes[] = {
10981 GR_AND_ACC_REGS, FP_REGS, COP0_REGS, COP2_REGS, COP3_REGS,
10982 ST_REGS, LIM_REG_CLASSES
10984 static const reg_class_t no_acc_classes[] = {
10985 GR_REGS, FP_REGS, COP0_REGS, COP2_REGS, COP3_REGS,
10986 ST_REGS, LIM_REG_CLASSES
10989 /* Don't allow the register allocators to use LO and HI in MIPS16 mode,
10990 which has no MTLO or MTHI instructions. Also, using GR_AND_ACC_REGS
10991 as a cover class only works well when we keep per-register costs.
10992 Using it when not optimizing can cause us to think accumulators
10993 have the same cost as GPRs in cases where GPRs are actually much
10995 return TARGET_MIPS16 || !optimize ? no_acc_classes : acc_classes;
10998 /* Return the register class required for a secondary register when
10999 copying between one of the registers in RCLASS and value X, which
11000 has mode MODE. X is the source of the move if IN_P, otherwise it
11001 is the destination. Return NO_REGS if no secondary register is
11005 mips_secondary_reload_class (enum reg_class rclass,
11006 enum machine_mode mode, rtx x, bool in_p)
11010 /* If X is a constant that cannot be loaded into $25, it must be loaded
11011 into some other GPR. No other register class allows a direct move. */
11012 if (mips_dangerous_for_la25_p (x))
11013 return reg_class_subset_p (rclass, LEA_REGS) ? NO_REGS : LEA_REGS;
11015 regno = true_regnum (x);
11018 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
11019 if (!reg_class_subset_p (rclass, M16_REGS) && !M16_REG_P (regno))
11025 /* Copying from accumulator registers to anywhere other than a general
11026 register requires a temporary general register. */
11027 if (reg_class_subset_p (rclass, ACC_REGS))
11028 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
11029 if (ACC_REG_P (regno))
11030 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
11032 /* We can only copy a value to a condition code register from a
11033 floating-point register, and even then we require a scratch
11034 floating-point register. We can only copy a value out of a
11035 condition-code register into a general register. */
11036 if (reg_class_subset_p (rclass, ST_REGS))
11040 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
11042 if (ST_REG_P (regno))
11046 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
11049 if (reg_class_subset_p (rclass, FP_REGS))
11052 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8))
11053 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
11054 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
11057 if (GP_REG_P (regno) || x == CONST0_RTX (mode))
11058 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
11061 if (CONSTANT_P (x) && !targetm.cannot_force_const_mem (x))
11062 /* We can force the constant to memory and use lwc1
11063 and ldc1. As above, we will use pairs of lwc1s if
11064 ldc1 is not supported. */
11067 if (FP_REG_P (regno) && mips_mode_ok_for_mov_fmt_p (mode))
11068 /* In this case we can use mov.fmt. */
11071 /* Otherwise, we need to reload through an integer register. */
11074 if (FP_REG_P (regno))
11075 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
11080 /* Implement TARGET_MODE_REP_EXTENDED. */
11083 mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
11085 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
11086 if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
11087 return SIGN_EXTEND;
11092 /* Implement TARGET_VALID_POINTER_MODE. */
11095 mips_valid_pointer_mode (enum machine_mode mode)
11097 return mode == SImode || (TARGET_64BIT && mode == DImode);
11100 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
11103 mips_vector_mode_supported_p (enum machine_mode mode)
11108 return TARGET_PAIRED_SINGLE_FLOAT;
11123 return TARGET_LOONGSON_VECTORS;
11130 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
11133 mips_scalar_mode_supported_p (enum machine_mode mode)
11135 if (ALL_FIXED_POINT_MODE_P (mode)
11136 && GET_MODE_PRECISION (mode) <= 2 * BITS_PER_WORD)
11139 return default_scalar_mode_supported_p (mode);
11142 /* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
11144 static enum machine_mode
11145 mips_preferred_simd_mode (enum machine_mode mode ATTRIBUTE_UNUSED)
11147 if (TARGET_PAIRED_SINGLE_FLOAT
11153 /* Implement TARGET_INIT_LIBFUNCS. */
11156 mips_init_libfuncs (void)
11158 if (TARGET_FIX_VR4120)
11160 /* Register the special divsi3 and modsi3 functions needed to work
11161 around VR4120 division errata. */
11162 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
11163 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
11166 if (TARGET_MIPS16 && TARGET_HARD_FLOAT_ABI)
11168 /* Register the MIPS16 -mhard-float stubs. */
11169 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
11170 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
11171 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
11172 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
11174 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
11175 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
11176 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
11177 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
11178 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
11179 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
11180 set_optab_libfunc (unord_optab, SFmode, "__mips16_unordsf2");
11182 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
11183 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
11184 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__mips16_floatunsisf");
11186 if (TARGET_DOUBLE_FLOAT)
11188 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
11189 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
11190 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
11191 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
11193 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
11194 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
11195 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
11196 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
11197 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
11198 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
11199 set_optab_libfunc (unord_optab, DFmode, "__mips16_unorddf2");
11201 set_conv_libfunc (sext_optab, DFmode, SFmode,
11202 "__mips16_extendsfdf2");
11203 set_conv_libfunc (trunc_optab, SFmode, DFmode,
11204 "__mips16_truncdfsf2");
11205 set_conv_libfunc (sfix_optab, SImode, DFmode,
11206 "__mips16_fix_truncdfsi");
11207 set_conv_libfunc (sfloat_optab, DFmode, SImode,
11208 "__mips16_floatsidf");
11209 set_conv_libfunc (ufloat_optab, DFmode, SImode,
11210 "__mips16_floatunsidf");
11214 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
11215 on an external non-MIPS16 routine to implement __sync_synchronize. */
11217 synchronize_libfunc = init_one_libfunc ("__sync_synchronize");
11220 /* Build up a multi-insn sequence that loads label TARGET into $AT. */
11223 mips_process_load_label (rtx target)
11225 rtx base, gp, intop;
11226 HOST_WIDE_INT offset;
11228 mips_multi_start ();
11232 mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target, 0);
11233 mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target, 0);
11237 mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target, 0);
11238 mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target, 0);
11242 gp = pic_offset_table_rtx;
11243 if (mips_cfun_has_cprestore_slot_p ())
11245 gp = gen_rtx_REG (Pmode, AT_REGNUM);
11246 mips_get_cprestore_base_and_offset (&base, &offset, true);
11247 if (!SMALL_OPERAND (offset))
11249 intop = GEN_INT (CONST_HIGH_PART (offset));
11250 mips_multi_add_insn ("lui\t%0,%1", gp, intop, 0);
11251 mips_multi_add_insn ("addu\t%0,%0,%1", gp, base, 0);
11254 offset = CONST_LOW_PART (offset);
11256 intop = GEN_INT (offset);
11257 if (ISA_HAS_LOAD_DELAY)
11258 mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp, intop, base, 0);
11260 mips_multi_add_insn ("lw\t%0,%1(%2)", gp, intop, base, 0);
11262 if (ISA_HAS_LOAD_DELAY)
11263 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target, gp, 0);
11265 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target, gp, 0);
11266 mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target, 0);
11271 /* Return the number of instructions needed to load a label into $AT. */
11273 static unsigned int
11274 mips_load_label_num_insns (void)
11276 if (cfun->machine->load_label_num_insns == 0)
11278 mips_process_load_label (pc_rtx);
11279 cfun->machine->load_label_num_insns = mips_multi_num_insns;
11281 return cfun->machine->load_label_num_insns;
11284 /* Emit an asm sequence to start a noat block and load the address
11285 of a label into $1. */
11288 mips_output_load_label (rtx target)
11290 mips_push_asm_switch (&mips_noat);
11291 if (TARGET_EXPLICIT_RELOCS)
11293 mips_process_load_label (target);
11294 mips_multi_write ();
11298 if (Pmode == DImode)
11299 output_asm_insn ("dla\t%@,%0", &target);
11301 output_asm_insn ("la\t%@,%0", &target);
11305 /* Return the length of INSN. LENGTH is the initial length computed by
11306 attributes in the machine-description file. */
11309 mips_adjust_insn_length (rtx insn, int length)
11311 /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length
11312 of a PIC long-branch sequence. Substitute the correct value. */
11313 if (length == MAX_PIC_BRANCH_LENGTH
11314 && INSN_CODE (insn) >= 0
11315 && get_attr_type (insn) == TYPE_BRANCH)
11317 /* Add the branch-over instruction and its delay slot, if this
11318 is a conditional branch. */
11319 length = simplejump_p (insn) ? 0 : 8;
11321 /* Load the label into $AT and jump to it. Ignore the delay
11322 slot of the jump. */
11323 length += 4 * mips_load_label_num_insns() + 4;
11326 /* A unconditional jump has an unfilled delay slot if it is not part
11327 of a sequence. A conditional jump normally has a delay slot, but
11328 does not on MIPS16. */
11329 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
11332 /* See how many nops might be needed to avoid hardware hazards. */
11333 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
11334 switch (get_attr_hazard (insn))
11348 /* In order to make it easier to share MIPS16 and non-MIPS16 patterns,
11349 the .md file length attributes are 4-based for both modes.
11350 Adjust the MIPS16 ones here. */
11357 /* Return the assembly code for INSN, which has the operands given by
11358 OPERANDS, and which branches to OPERANDS[0] if some condition is true.
11359 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0]
11360 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
11361 version of BRANCH_IF_TRUE. */
11364 mips_output_conditional_branch (rtx insn, rtx *operands,
11365 const char *branch_if_true,
11366 const char *branch_if_false)
11368 unsigned int length;
11369 rtx taken, not_taken;
11371 gcc_assert (LABEL_P (operands[0]));
11373 length = get_attr_length (insn);
11376 /* Just a simple conditional branch. */
11377 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
11378 return branch_if_true;
11381 /* Generate a reversed branch around a direct jump. This fallback does
11382 not use branch-likely instructions. */
11383 mips_branch_likely = false;
11384 not_taken = gen_label_rtx ();
11385 taken = operands[0];
11387 /* Generate the reversed branch to NOT_TAKEN. */
11388 operands[0] = not_taken;
11389 output_asm_insn (branch_if_false, operands);
11391 /* If INSN has a delay slot, we must provide delay slots for both the
11392 branch to NOT_TAKEN and the conditional jump. We must also ensure
11393 that INSN's delay slot is executed in the appropriate cases. */
11394 if (final_sequence)
11396 /* This first delay slot will always be executed, so use INSN's
11397 delay slot if is not annulled. */
11398 if (!INSN_ANNULLED_BRANCH_P (insn))
11400 final_scan_insn (XVECEXP (final_sequence, 0, 1),
11401 asm_out_file, optimize, 1, NULL);
11402 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
11405 output_asm_insn ("nop", 0);
11406 fprintf (asm_out_file, "\n");
11409 /* Output the unconditional branch to TAKEN. */
11410 if (TARGET_ABSOLUTE_JUMPS)
11411 output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken);
11414 mips_output_load_label (taken);
11415 output_asm_insn ("jr\t%@%]%/", 0);
11418 /* Now deal with its delay slot; see above. */
11419 if (final_sequence)
11421 /* This delay slot will only be executed if the branch is taken.
11422 Use INSN's delay slot if is annulled. */
11423 if (INSN_ANNULLED_BRANCH_P (insn))
11425 final_scan_insn (XVECEXP (final_sequence, 0, 1),
11426 asm_out_file, optimize, 1, NULL);
11427 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
11430 output_asm_insn ("nop", 0);
11431 fprintf (asm_out_file, "\n");
11434 /* Output NOT_TAKEN. */
11435 targetm.asm_out.internal_label (asm_out_file, "L",
11436 CODE_LABEL_NUMBER (not_taken));
11440 /* Return the assembly code for INSN, which branches to OPERANDS[0]
11441 if some ordering condition is true. The condition is given by
11442 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
11443 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
11444 its second is always zero. */
11447 mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
11449 const char *branch[2];
11451 /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true.
11452 Make BRANCH[0] branch on the inverse condition. */
11453 switch (GET_CODE (operands[1]))
11455 /* These cases are equivalent to comparisons against zero. */
11457 inverted_p = !inverted_p;
11458 /* Fall through. */
11460 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%0");
11461 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%0");
11464 /* These cases are always true or always false. */
11466 inverted_p = !inverted_p;
11467 /* Fall through. */
11469 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%0");
11470 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%0");
11474 branch[!inverted_p] = MIPS_BRANCH ("b%C1z", "%2,%0");
11475 branch[inverted_p] = MIPS_BRANCH ("b%N1z", "%2,%0");
11478 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
11481 /* Start a block of code that needs access to the LL, SC and SYNC
11485 mips_start_ll_sc_sync_block (void)
11487 if (!ISA_HAS_LL_SC)
11489 output_asm_insn (".set\tpush", 0);
11490 output_asm_insn (".set\tmips2", 0);
11494 /* End a block started by mips_start_ll_sc_sync_block. */
11497 mips_end_ll_sc_sync_block (void)
11499 if (!ISA_HAS_LL_SC)
11500 output_asm_insn (".set\tpop", 0);
11503 /* Output and/or return the asm template for a sync instruction. */
11506 mips_output_sync (void)
11508 mips_start_ll_sc_sync_block ();
11509 output_asm_insn ("sync", 0);
11510 mips_end_ll_sc_sync_block ();
11514 /* Return the asm template associated with sync_insn1 value TYPE.
11515 IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */
11517 static const char *
11518 mips_sync_insn1_template (enum attr_sync_insn1 type, bool is_64bit_p)
11522 case SYNC_INSN1_MOVE:
11523 return "move\t%0,%z2";
11524 case SYNC_INSN1_LI:
11525 return "li\t%0,%2";
11526 case SYNC_INSN1_ADDU:
11527 return is_64bit_p ? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2";
11528 case SYNC_INSN1_ADDIU:
11529 return is_64bit_p ? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2";
11530 case SYNC_INSN1_SUBU:
11531 return is_64bit_p ? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2";
11532 case SYNC_INSN1_AND:
11533 return "and\t%0,%1,%z2";
11534 case SYNC_INSN1_ANDI:
11535 return "andi\t%0,%1,%2";
11536 case SYNC_INSN1_OR:
11537 return "or\t%0,%1,%z2";
11538 case SYNC_INSN1_ORI:
11539 return "ori\t%0,%1,%2";
11540 case SYNC_INSN1_XOR:
11541 return "xor\t%0,%1,%z2";
11542 case SYNC_INSN1_XORI:
11543 return "xori\t%0,%1,%2";
11545 gcc_unreachable ();
11548 /* Return the asm template associated with sync_insn2 value TYPE. */
11550 static const char *
11551 mips_sync_insn2_template (enum attr_sync_insn2 type)
11555 case SYNC_INSN2_NOP:
11556 gcc_unreachable ();
11557 case SYNC_INSN2_AND:
11558 return "and\t%0,%1,%z2";
11559 case SYNC_INSN2_XOR:
11560 return "xor\t%0,%1,%z2";
11561 case SYNC_INSN2_NOT:
11562 return "nor\t%0,%1,%.";
11564 gcc_unreachable ();
11567 /* OPERANDS are the operands to a sync loop instruction and INDEX is
11568 the value of the one of the sync_* attributes. Return the operand
11569 referred to by the attribute, or DEFAULT_VALUE if the insn doesn't
11570 have the associated attribute. */
11573 mips_get_sync_operand (rtx *operands, int index, rtx default_value)
11576 default_value = operands[index - 1];
11577 return default_value;
11580 /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn
11581 sequence for it. */
11584 mips_process_sync_loop (rtx insn, rtx *operands)
11586 rtx at, mem, oldval, newval, inclusive_mask, exclusive_mask;
11587 rtx required_oldval, insn1_op2, tmp1, tmp2, tmp3;
11588 unsigned int tmp3_insn;
11589 enum attr_sync_insn1 insn1;
11590 enum attr_sync_insn2 insn2;
11593 /* Read an operand from the sync_WHAT attribute and store it in
11594 variable WHAT. DEFAULT is the default value if no attribute
11596 #define READ_OPERAND(WHAT, DEFAULT) \
11597 WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \
11600 /* Read the memory. */
11601 READ_OPERAND (mem, 0);
11603 is_64bit_p = (GET_MODE_BITSIZE (GET_MODE (mem)) == 64);
11605 /* Read the other attributes. */
11606 at = gen_rtx_REG (GET_MODE (mem), AT_REGNUM);
11607 READ_OPERAND (oldval, at);
11608 READ_OPERAND (newval, at);
11609 READ_OPERAND (inclusive_mask, 0);
11610 READ_OPERAND (exclusive_mask, 0);
11611 READ_OPERAND (required_oldval, 0);
11612 READ_OPERAND (insn1_op2, 0);
11613 insn1 = get_attr_sync_insn1 (insn);
11614 insn2 = get_attr_sync_insn2 (insn);
11616 mips_multi_start ();
11618 /* Output the release side of the memory barrier. */
11619 if (get_attr_sync_release_barrier (insn) == SYNC_RELEASE_BARRIER_YES)
11621 if (required_oldval == 0 && TARGET_OCTEON)
11623 /* Octeon doesn't reorder reads, so a full barrier can be
11624 created by using SYNCW to order writes combined with the
11625 write from the following SC. When the SC successfully
11626 completes, we know that all preceding writes are also
11627 committed to the coherent memory system. It is possible
11628 for a single SYNCW to fail, but a pair of them will never
11629 fail, so we use two. */
11630 mips_multi_add_insn ("syncw", NULL);
11631 mips_multi_add_insn ("syncw", NULL);
11634 mips_multi_add_insn ("sync", NULL);
11637 /* Output the branch-back label. */
11638 mips_multi_add_label ("1:");
11640 /* OLDVAL = *MEM. */
11641 mips_multi_add_insn (is_64bit_p ? "lld\t%0,%1" : "ll\t%0,%1",
11642 oldval, mem, NULL);
11644 /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */
11645 if (required_oldval)
11647 if (inclusive_mask == 0)
11651 gcc_assert (oldval != at);
11652 mips_multi_add_insn ("and\t%0,%1,%2",
11653 at, oldval, inclusive_mask, NULL);
11656 mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1, required_oldval, NULL);
11659 /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */
11660 if (exclusive_mask == 0)
11664 gcc_assert (oldval != at);
11665 mips_multi_add_insn ("and\t%0,%1,%z2",
11666 at, oldval, exclusive_mask, NULL);
11670 /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2).
11672 We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit
11673 at least one instruction in that case. */
11674 if (insn1 == SYNC_INSN1_MOVE
11675 && (tmp1 != const0_rtx || insn2 != SYNC_INSN2_NOP))
11679 mips_multi_add_insn (mips_sync_insn1_template (insn1, is_64bit_p),
11680 newval, oldval, insn1_op2, NULL);
11684 /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */
11685 if (insn2 == SYNC_INSN2_NOP)
11689 mips_multi_add_insn (mips_sync_insn2_template (insn2),
11690 newval, tmp2, inclusive_mask, NULL);
11693 tmp3_insn = mips_multi_last_index ();
11695 /* $AT = $TMP1 | $TMP3. */
11696 if (tmp1 == const0_rtx || tmp3 == const0_rtx)
11698 mips_multi_set_operand (tmp3_insn, 0, at);
11703 gcc_assert (tmp1 != tmp3);
11704 mips_multi_add_insn ("or\t%0,%1,%2", at, tmp1, tmp3, NULL);
11707 /* if (!commit (*MEM = $AT)) goto 1.
11709 This will sometimes be a delayed branch; see the write code below
11711 mips_multi_add_insn (is_64bit_p ? "scd\t%0,%1" : "sc\t%0,%1", at, mem, NULL);
11712 mips_multi_add_insn ("beq%?\t%0,%.,1b", at, NULL);
11714 /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */
11715 if (insn1 != SYNC_INSN1_MOVE && insn1 != SYNC_INSN1_LI && tmp3 != newval)
11717 mips_multi_copy_insn (tmp3_insn);
11718 mips_multi_set_operand (mips_multi_last_index (), 0, newval);
11721 mips_multi_add_insn ("nop", NULL);
11723 /* Output the acquire side of the memory barrier. */
11724 if (TARGET_SYNC_AFTER_SC)
11725 mips_multi_add_insn ("sync", NULL);
11727 /* Output the exit label, if needed. */
11728 if (required_oldval)
11729 mips_multi_add_label ("2:");
11731 #undef READ_OPERAND
11734 /* Output and/or return the asm template for sync loop INSN, which has
11735 the operands given by OPERANDS. */
11738 mips_output_sync_loop (rtx insn, rtx *operands)
11740 mips_process_sync_loop (insn, operands);
11742 /* Use branch-likely instructions to work around the LL/SC R10000
11744 mips_branch_likely = TARGET_FIX_R10000;
11746 mips_push_asm_switch (&mips_noreorder);
11747 mips_push_asm_switch (&mips_nomacro);
11748 mips_push_asm_switch (&mips_noat);
11749 mips_start_ll_sc_sync_block ();
11751 mips_multi_write ();
11753 mips_end_ll_sc_sync_block ();
11754 mips_pop_asm_switch (&mips_noat);
11755 mips_pop_asm_switch (&mips_nomacro);
11756 mips_pop_asm_switch (&mips_noreorder);
11761 /* Return the number of individual instructions in sync loop INSN,
11762 which has the operands given by OPERANDS. */
11765 mips_sync_loop_insns (rtx insn, rtx *operands)
11767 mips_process_sync_loop (insn, operands);
11768 return mips_multi_num_insns;
11771 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
11772 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
11774 When working around R4000 and R4400 errata, we need to make sure that
11775 the division is not immediately followed by a shift[1][2]. We also
11776 need to stop the division from being put into a branch delay slot[3].
11777 The easiest way to avoid both problems is to add a nop after the
11778 division. When a divide-by-zero check is needed, this nop can be
11779 used to fill the branch delay slot.
11781 [1] If a double-word or a variable shift executes immediately
11782 after starting an integer division, the shift may give an
11783 incorrect result. See quotations of errata #16 and #28 from
11784 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
11785 in mips.md for details.
11787 [2] A similar bug to [1] exists for all revisions of the
11788 R4000 and the R4400 when run in an MC configuration.
11789 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
11791 "19. In this following sequence:
11793 ddiv (or ddivu or div or divu)
11794 dsll32 (or dsrl32, dsra32)
11796 if an MPT stall occurs, while the divide is slipping the cpu
11797 pipeline, then the following double shift would end up with an
11800 Workaround: The compiler needs to avoid generating any
11801 sequence with divide followed by extended double shift."
11803 This erratum is also present in "MIPS R4400MC Errata, Processor
11804 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
11805 & 3.0" as errata #10 and #4, respectively.
11807 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
11808 (also valid for MIPS R4000MC processors):
11810 "52. R4000SC: This bug does not apply for the R4000PC.
11812 There are two flavors of this bug:
11814 1) If the instruction just after divide takes an RF exception
11815 (tlb-refill, tlb-invalid) and gets an instruction cache
11816 miss (both primary and secondary) and the line which is
11817 currently in secondary cache at this index had the first
11818 data word, where the bits 5..2 are set, then R4000 would
11819 get a wrong result for the div.
11824 ------------------- # end-of page. -tlb-refill
11829 ------------------- # end-of page. -tlb-invalid
11832 2) If the divide is in the taken branch delay slot, where the
11833 target takes RF exception and gets an I-cache miss for the
11834 exception vector or where I-cache miss occurs for the
11835 target address, under the above mentioned scenarios, the
11836 div would get wrong results.
11839 j r2 # to next page mapped or unmapped
11840 div r8,r9 # this bug would be there as long
11841 # as there is an ICache miss and
11842 nop # the "data pattern" is present
11845 beq r0, r0, NextPage # to Next page
11849 This bug is present for div, divu, ddiv, and ddivu
11852 Workaround: For item 1), OS could make sure that the next page
11853 after the divide instruction is also mapped. For item 2), the
11854 compiler could make sure that the divide instruction is not in
11855 the branch delay slot."
11857 These processors have PRId values of 0x00004220 and 0x00004300 for
11858 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
11861 mips_output_division (const char *division, rtx *operands)
11866 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
11868 output_asm_insn (s, operands);
11871 if (TARGET_CHECK_ZERO_DIV)
11875 output_asm_insn (s, operands);
11876 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
11878 else if (GENERATE_DIVIDE_TRAPS)
11880 /* Avoid long replay penalty on load miss by putting the trap before
11883 output_asm_insn ("teq\t%2,%.,7", operands);
11886 output_asm_insn (s, operands);
11887 s = "teq\t%2,%.,7";
11892 output_asm_insn ("%(bne\t%2,%.,1f", operands);
11893 output_asm_insn (s, operands);
11894 s = "break\t7%)\n1:";
11900 /* Return true if IN_INSN is a multiply-add or multiply-subtract
11901 instruction and if OUT_INSN assigns to the accumulator operand. */
11904 mips_linked_madd_p (rtx out_insn, rtx in_insn)
11908 x = single_set (in_insn);
11914 if (GET_CODE (x) == PLUS
11915 && GET_CODE (XEXP (x, 0)) == MULT
11916 && reg_set_p (XEXP (x, 1), out_insn))
11919 if (GET_CODE (x) == MINUS
11920 && GET_CODE (XEXP (x, 1)) == MULT
11921 && reg_set_p (XEXP (x, 0), out_insn))
11927 /* True if the dependency between OUT_INSN and IN_INSN is on the store
11928 data rather than the address. We need this because the cprestore
11929 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
11930 which causes the default routine to abort. We just return false
11934 mips_store_data_bypass_p (rtx out_insn, rtx in_insn)
11936 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
11939 return !store_data_bypass_p (out_insn, in_insn);
11943 /* Variables and flags used in scheduler hooks when tuning for
11947 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
11950 /* If true, then next ALU1/2 instruction will go to ALU1. */
11953 /* If true, then next FALU1/2 unstruction will go to FALU1. */
11956 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
11957 int alu1_core_unit_code;
11958 int alu2_core_unit_code;
11959 int falu1_core_unit_code;
11960 int falu2_core_unit_code;
11962 /* True if current cycle has a multi instruction.
11963 This flag is used in mips_ls2_dfa_post_advance_cycle. */
11964 bool cycle_has_multi_p;
11966 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
11967 These are used in mips_ls2_dfa_post_advance_cycle to initialize
11969 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
11970 instruction to go ALU1. */
11971 rtx alu1_turn_enabled_insn;
11972 rtx alu2_turn_enabled_insn;
11973 rtx falu1_turn_enabled_insn;
11974 rtx falu2_turn_enabled_insn;
11977 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
11978 dependencies have no cost, except on the 20Kc where output-dependence
11979 is treated like input-dependence. */
11982 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
11983 rtx dep ATTRIBUTE_UNUSED, int cost)
11985 if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT
11988 if (REG_NOTE_KIND (link) != 0)
11993 /* Return the number of instructions that can be issued per cycle. */
11996 mips_issue_rate (void)
12000 case PROCESSOR_74KC:
12001 case PROCESSOR_74KF2_1:
12002 case PROCESSOR_74KF1_1:
12003 case PROCESSOR_74KF3_2:
12004 /* The 74k is not strictly quad-issue cpu, but can be seen as one
12005 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
12006 but in reality only a maximum of 3 insns can be issued as
12007 floating-point loads and stores also require a slot in the
12009 case PROCESSOR_R10000:
12010 /* All R10K Processors are quad-issue (being the first MIPS
12011 processors to support this feature). */
12014 case PROCESSOR_20KC:
12015 case PROCESSOR_R4130:
12016 case PROCESSOR_R5400:
12017 case PROCESSOR_R5500:
12018 case PROCESSOR_R7000:
12019 case PROCESSOR_R9000:
12020 case PROCESSOR_OCTEON:
12023 case PROCESSOR_SB1:
12024 case PROCESSOR_SB1A:
12025 /* This is actually 4, but we get better performance if we claim 3.
12026 This is partly because of unwanted speculative code motion with the
12027 larger number, and partly because in most common cases we can't
12028 reach the theoretical max of 4. */
12031 case PROCESSOR_LOONGSON_2E:
12032 case PROCESSOR_LOONGSON_2F:
12033 case PROCESSOR_LOONGSON_3A:
12041 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
12044 mips_ls2_init_dfa_post_cycle_insn (void)
12047 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
12048 mips_ls2.alu1_turn_enabled_insn = get_insns ();
12052 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
12053 mips_ls2.alu2_turn_enabled_insn = get_insns ();
12057 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
12058 mips_ls2.falu1_turn_enabled_insn = get_insns ();
12062 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
12063 mips_ls2.falu2_turn_enabled_insn = get_insns ();
12066 mips_ls2.alu1_core_unit_code = get_cpu_unit_code ("ls2_alu1_core");
12067 mips_ls2.alu2_core_unit_code = get_cpu_unit_code ("ls2_alu2_core");
12068 mips_ls2.falu1_core_unit_code = get_cpu_unit_code ("ls2_falu1_core");
12069 mips_ls2.falu2_core_unit_code = get_cpu_unit_code ("ls2_falu2_core");
12072 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
12073 Init data used in mips_dfa_post_advance_cycle. */
12076 mips_init_dfa_post_cycle_insn (void)
12078 if (TUNE_LOONGSON_2EF)
12079 mips_ls2_init_dfa_post_cycle_insn ();
12082 /* Initialize STATE when scheduling for Loongson 2E/2F.
12083 Support round-robin dispatch scheme by enabling only one of
12084 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
12088 mips_ls2_dfa_post_advance_cycle (state_t state)
12090 if (cpu_unit_reservation_p (state, mips_ls2.alu1_core_unit_code))
12092 /* Though there are no non-pipelined ALU1 insns,
12093 we can get an instruction of type 'multi' before reload. */
12094 gcc_assert (mips_ls2.cycle_has_multi_p);
12095 mips_ls2.alu1_turn_p = false;
12098 mips_ls2.cycle_has_multi_p = false;
12100 if (cpu_unit_reservation_p (state, mips_ls2.alu2_core_unit_code))
12101 /* We have a non-pipelined alu instruction in the core,
12102 adjust round-robin counter. */
12103 mips_ls2.alu1_turn_p = true;
12105 if (mips_ls2.alu1_turn_p)
12107 if (state_transition (state, mips_ls2.alu1_turn_enabled_insn) >= 0)
12108 gcc_unreachable ();
12112 if (state_transition (state, mips_ls2.alu2_turn_enabled_insn) >= 0)
12113 gcc_unreachable ();
12116 if (cpu_unit_reservation_p (state, mips_ls2.falu1_core_unit_code))
12118 /* There are no non-pipelined FALU1 insns. */
12119 gcc_unreachable ();
12120 mips_ls2.falu1_turn_p = false;
12123 if (cpu_unit_reservation_p (state, mips_ls2.falu2_core_unit_code))
12124 /* We have a non-pipelined falu instruction in the core,
12125 adjust round-robin counter. */
12126 mips_ls2.falu1_turn_p = true;
12128 if (mips_ls2.falu1_turn_p)
12130 if (state_transition (state, mips_ls2.falu1_turn_enabled_insn) >= 0)
12131 gcc_unreachable ();
12135 if (state_transition (state, mips_ls2.falu2_turn_enabled_insn) >= 0)
12136 gcc_unreachable ();
12140 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
12141 This hook is being called at the start of each cycle. */
12144 mips_dfa_post_advance_cycle (void)
12146 if (TUNE_LOONGSON_2EF)
12147 mips_ls2_dfa_post_advance_cycle (curr_state);
12150 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
12151 be as wide as the scheduling freedom in the DFA. */
12154 mips_multipass_dfa_lookahead (void)
12156 /* Can schedule up to 4 of the 6 function units in any one cycle. */
12160 if (TUNE_LOONGSON_2EF || TUNE_LOONGSON_3A)
12169 /* Remove the instruction at index LOWER from ready queue READY and
12170 reinsert it in front of the instruction at index HIGHER. LOWER must
12174 mips_promote_ready (rtx *ready, int lower, int higher)
12179 new_head = ready[lower];
12180 for (i = lower; i < higher; i++)
12181 ready[i] = ready[i + 1];
12182 ready[i] = new_head;
12185 /* If the priority of the instruction at POS2 in the ready queue READY
12186 is within LIMIT units of that of the instruction at POS1, swap the
12187 instructions if POS2 is not already less than POS1. */
12190 mips_maybe_swap_ready (rtx *ready, int pos1, int pos2, int limit)
12193 && INSN_PRIORITY (ready[pos1]) + limit >= INSN_PRIORITY (ready[pos2]))
12197 temp = ready[pos1];
12198 ready[pos1] = ready[pos2];
12199 ready[pos2] = temp;
12203 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
12204 that may clobber hi or lo. */
12205 static rtx mips_macc_chains_last_hilo;
12207 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
12208 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
12211 mips_macc_chains_record (rtx insn)
12213 if (get_attr_may_clobber_hilo (insn))
12214 mips_macc_chains_last_hilo = insn;
12217 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
12218 has NREADY elements, looking for a multiply-add or multiply-subtract
12219 instruction that is cumulative with mips_macc_chains_last_hilo.
12220 If there is one, promote it ahead of anything else that might
12221 clobber hi or lo. */
12224 mips_macc_chains_reorder (rtx *ready, int nready)
12228 if (mips_macc_chains_last_hilo != 0)
12229 for (i = nready - 1; i >= 0; i--)
12230 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
12232 for (j = nready - 1; j > i; j--)
12233 if (recog_memoized (ready[j]) >= 0
12234 && get_attr_may_clobber_hilo (ready[j]))
12236 mips_promote_ready (ready, i, j);
12243 /* The last instruction to be scheduled. */
12244 static rtx vr4130_last_insn;
12246 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
12247 points to an rtx that is initially an instruction. Nullify the rtx
12248 if the instruction uses the value of register X. */
12251 vr4130_true_reg_dependence_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
12256 insn_ptr = (rtx *) data;
12259 && reg_referenced_p (x, PATTERN (*insn_ptr)))
12263 /* Return true if there is true register dependence between vr4130_last_insn
12267 vr4130_true_reg_dependence_p (rtx insn)
12269 note_stores (PATTERN (vr4130_last_insn),
12270 vr4130_true_reg_dependence_p_1, &insn);
12274 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
12275 the ready queue and that INSN2 is the instruction after it, return
12276 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
12277 in which INSN1 and INSN2 can probably issue in parallel, but for
12278 which (INSN2, INSN1) should be less sensitive to instruction
12279 alignment than (INSN1, INSN2). See 4130.md for more details. */
12282 vr4130_swap_insns_p (rtx insn1, rtx insn2)
12284 sd_iterator_def sd_it;
12287 /* Check for the following case:
12289 1) there is some other instruction X with an anti dependence on INSN1;
12290 2) X has a higher priority than INSN2; and
12291 3) X is an arithmetic instruction (and thus has no unit restrictions).
12293 If INSN1 is the last instruction blocking X, it would better to
12294 choose (INSN1, X) over (INSN2, INSN1). */
12295 FOR_EACH_DEP (insn1, SD_LIST_FORW, sd_it, dep)
12296 if (DEP_TYPE (dep) == REG_DEP_ANTI
12297 && INSN_PRIORITY (DEP_CON (dep)) > INSN_PRIORITY (insn2)
12298 && recog_memoized (DEP_CON (dep)) >= 0
12299 && get_attr_vr4130_class (DEP_CON (dep)) == VR4130_CLASS_ALU)
12302 if (vr4130_last_insn != 0
12303 && recog_memoized (insn1) >= 0
12304 && recog_memoized (insn2) >= 0)
12306 /* See whether INSN1 and INSN2 use different execution units,
12307 or if they are both ALU-type instructions. If so, they can
12308 probably execute in parallel. */
12309 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
12310 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
12311 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
12313 /* If only one of the instructions has a dependence on
12314 vr4130_last_insn, prefer to schedule the other one first. */
12315 bool dep1_p = vr4130_true_reg_dependence_p (insn1);
12316 bool dep2_p = vr4130_true_reg_dependence_p (insn2);
12317 if (dep1_p != dep2_p)
12320 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
12321 is not an ALU-type instruction and if INSN1 uses the same
12322 execution unit. (Note that if this condition holds, we already
12323 know that INSN2 uses a different execution unit.) */
12324 if (class1 != VR4130_CLASS_ALU
12325 && recog_memoized (vr4130_last_insn) >= 0
12326 && class1 == get_attr_vr4130_class (vr4130_last_insn))
12333 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
12334 queue with at least two instructions. Swap the first two if
12335 vr4130_swap_insns_p says that it could be worthwhile. */
12338 vr4130_reorder (rtx *ready, int nready)
12340 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
12341 mips_promote_ready (ready, nready - 2, nready - 1);
12344 /* Record whether last 74k AGEN instruction was a load or store. */
12345 static enum attr_type mips_last_74k_agen_insn = TYPE_UNKNOWN;
12347 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
12348 resets to TYPE_UNKNOWN state. */
12351 mips_74k_agen_init (rtx insn)
12353 if (!insn || CALL_P (insn) || JUMP_P (insn))
12354 mips_last_74k_agen_insn = TYPE_UNKNOWN;
12357 enum attr_type type = get_attr_type (insn);
12358 if (type == TYPE_LOAD || type == TYPE_STORE)
12359 mips_last_74k_agen_insn = type;
12363 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
12364 loads to be grouped together, and multiple stores to be grouped
12365 together. Swap things around in the ready queue to make this happen. */
12368 mips_74k_agen_reorder (rtx *ready, int nready)
12371 int store_pos, load_pos;
12376 for (i = nready - 1; i >= 0; i--)
12378 rtx insn = ready[i];
12379 if (USEFUL_INSN_P (insn))
12380 switch (get_attr_type (insn))
12383 if (store_pos == -1)
12388 if (load_pos == -1)
12397 if (load_pos == -1 || store_pos == -1)
12400 switch (mips_last_74k_agen_insn)
12403 /* Prefer to schedule loads since they have a higher latency. */
12405 /* Swap loads to the front of the queue. */
12406 mips_maybe_swap_ready (ready, load_pos, store_pos, 4);
12409 /* Swap stores to the front of the queue. */
12410 mips_maybe_swap_ready (ready, store_pos, load_pos, 4);
12417 /* Implement TARGET_SCHED_INIT. */
12420 mips_sched_init (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12421 int max_ready ATTRIBUTE_UNUSED)
12423 mips_macc_chains_last_hilo = 0;
12424 vr4130_last_insn = 0;
12425 mips_74k_agen_init (NULL_RTX);
12427 /* When scheduling for Loongson2, branch instructions go to ALU1,
12428 therefore basic block is most likely to start with round-robin counter
12429 pointed to ALU2. */
12430 mips_ls2.alu1_turn_p = false;
12431 mips_ls2.falu1_turn_p = true;
12434 /* Subroutine used by TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
12437 mips_sched_reorder_1 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12438 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
12440 if (!reload_completed
12441 && TUNE_MACC_CHAINS
12443 mips_macc_chains_reorder (ready, *nreadyp);
12445 if (reload_completed
12447 && !TARGET_VR4130_ALIGN
12449 vr4130_reorder (ready, *nreadyp);
12452 mips_74k_agen_reorder (ready, *nreadyp);
12455 /* Implement TARGET_SCHED_REORDER. */
12458 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12459 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
12461 mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle);
12462 return mips_issue_rate ();
12465 /* Implement TARGET_SCHED_REORDER2. */
12468 mips_sched_reorder2 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12469 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
12471 mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle);
12472 return cached_can_issue_more;
12475 /* Update round-robin counters for ALU1/2 and FALU1/2. */
12478 mips_ls2_variable_issue (rtx insn)
12480 if (mips_ls2.alu1_turn_p)
12482 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu1_core_unit_code))
12483 mips_ls2.alu1_turn_p = false;
12487 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu2_core_unit_code))
12488 mips_ls2.alu1_turn_p = true;
12491 if (mips_ls2.falu1_turn_p)
12493 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu1_core_unit_code))
12494 mips_ls2.falu1_turn_p = false;
12498 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu2_core_unit_code))
12499 mips_ls2.falu1_turn_p = true;
12502 if (recog_memoized (insn) >= 0)
12503 mips_ls2.cycle_has_multi_p |= (get_attr_type (insn) == TYPE_MULTI);
12506 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
12509 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12510 rtx insn, int more)
12512 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
12513 if (USEFUL_INSN_P (insn))
12515 if (get_attr_type (insn) != TYPE_GHOST)
12517 if (!reload_completed && TUNE_MACC_CHAINS)
12518 mips_macc_chains_record (insn);
12519 vr4130_last_insn = insn;
12521 mips_74k_agen_init (insn);
12522 else if (TUNE_LOONGSON_2EF)
12523 mips_ls2_variable_issue (insn);
12526 /* Instructions of type 'multi' should all be split before
12527 the second scheduling pass. */
12528 gcc_assert (!reload_completed
12529 || recog_memoized (insn) < 0
12530 || get_attr_type (insn) != TYPE_MULTI);
12532 cached_can_issue_more = more;
12536 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
12537 return the first operand of the associated PREF or PREFX insn. */
12540 mips_prefetch_cookie (rtx write, rtx locality)
12542 /* store_streamed / load_streamed. */
12543 if (INTVAL (locality) <= 0)
12544 return GEN_INT (INTVAL (write) + 4);
12546 /* store / load. */
12547 if (INTVAL (locality) <= 2)
12550 /* store_retained / load_retained. */
12551 return GEN_INT (INTVAL (write) + 6);
12554 /* Flags that indicate when a built-in function is available.
12556 BUILTIN_AVAIL_NON_MIPS16
12557 The function is available on the current target, but only
12558 in non-MIPS16 mode. */
12559 #define BUILTIN_AVAIL_NON_MIPS16 1
12561 /* Declare an availability predicate for built-in functions that
12562 require non-MIPS16 mode and also require COND to be true.
12563 NAME is the main part of the predicate's name. */
12564 #define AVAIL_NON_MIPS16(NAME, COND) \
12565 static unsigned int \
12566 mips_builtin_avail_##NAME (void) \
12568 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
12571 /* This structure describes a single built-in function. */
12572 struct mips_builtin_description {
12573 /* The code of the main .md file instruction. See mips_builtin_type
12574 for more information. */
12575 enum insn_code icode;
12577 /* The floating-point comparison code to use with ICODE, if any. */
12578 enum mips_fp_condition cond;
12580 /* The name of the built-in function. */
12583 /* Specifies how the function should be expanded. */
12584 enum mips_builtin_type builtin_type;
12586 /* The function's prototype. */
12587 enum mips_function_type function_type;
12589 /* Whether the function is available. */
12590 unsigned int (*avail) (void);
12593 AVAIL_NON_MIPS16 (paired_single, TARGET_PAIRED_SINGLE_FLOAT)
12594 AVAIL_NON_MIPS16 (sb1_paired_single, TARGET_SB1 && TARGET_PAIRED_SINGLE_FLOAT)
12595 AVAIL_NON_MIPS16 (mips3d, TARGET_MIPS3D)
12596 AVAIL_NON_MIPS16 (dsp, TARGET_DSP)
12597 AVAIL_NON_MIPS16 (dspr2, TARGET_DSPR2)
12598 AVAIL_NON_MIPS16 (dsp_32, !TARGET_64BIT && TARGET_DSP)
12599 AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2)
12600 AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS)
12601 AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
12603 /* Construct a mips_builtin_description from the given arguments.
12605 INSN is the name of the associated instruction pattern, without the
12606 leading CODE_FOR_mips_.
12608 CODE is the floating-point condition code associated with the
12609 function. It can be 'f' if the field is not applicable.
12611 NAME is the name of the function itself, without the leading
12614 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
12616 AVAIL is the name of the availability predicate, without the leading
12617 mips_builtin_avail_. */
12618 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
12619 FUNCTION_TYPE, AVAIL) \
12620 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
12621 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
12622 mips_builtin_avail_ ## AVAIL }
12624 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
12625 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
12626 are as for MIPS_BUILTIN. */
12627 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
12628 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
12630 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
12631 are subject to mips_builtin_avail_<AVAIL>. */
12632 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
12633 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
12634 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
12635 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
12636 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
12638 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
12639 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
12640 while the any and all forms are subject to mips_builtin_avail_mips3d. */
12641 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
12642 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
12643 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
12645 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
12646 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
12648 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
12649 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
12651 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
12652 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
12655 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
12656 are subject to mips_builtin_avail_mips3d. */
12657 #define CMP_4S_BUILTINS(INSN, COND) \
12658 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
12659 MIPS_BUILTIN_CMP_ANY, \
12660 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
12661 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
12662 MIPS_BUILTIN_CMP_ALL, \
12663 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
12665 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
12666 instruction requires mips_builtin_avail_<AVAIL>. */
12667 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
12668 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
12669 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
12671 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
12672 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
12675 /* Define all the built-in functions related to C.cond.fmt condition COND. */
12676 #define CMP_BUILTINS(COND) \
12677 MOVTF_BUILTINS (c, COND, paired_single), \
12678 MOVTF_BUILTINS (cabs, COND, mips3d), \
12679 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
12680 CMP_PS_BUILTINS (c, COND, paired_single), \
12681 CMP_PS_BUILTINS (cabs, COND, mips3d), \
12682 CMP_4S_BUILTINS (c, COND), \
12683 CMP_4S_BUILTINS (cabs, COND)
12685 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
12686 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
12687 and AVAIL are as for MIPS_BUILTIN. */
12688 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
12689 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
12690 FUNCTION_TYPE, AVAIL)
12692 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
12693 branch instruction. AVAIL is as for MIPS_BUILTIN. */
12694 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
12695 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
12696 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
12698 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
12699 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
12700 builtin_description field. */
12701 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
12702 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
12703 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
12704 FUNCTION_TYPE, mips_builtin_avail_loongson }
12706 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
12707 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
12708 builtin_description field. */
12709 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
12710 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
12712 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
12713 We use functions of this form when the same insn can be usefully applied
12714 to more than one datatype. */
12715 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
12716 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
12718 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
12719 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
12720 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
12721 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
12722 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
12723 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
12724 #define CODE_FOR_mips_mult CODE_FOR_mulsidi3_32bit
12725 #define CODE_FOR_mips_multu CODE_FOR_umulsidi3_32bit
12727 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
12728 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
12729 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
12730 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
12731 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
12732 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
12733 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
12734 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
12735 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
12736 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
12737 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
12738 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
12739 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
12740 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
12741 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
12742 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
12743 #define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3
12744 #define CODE_FOR_loongson_psllh CODE_FOR_ashlv4hi3
12745 #define CODE_FOR_loongson_psllw CODE_FOR_ashlv2si3
12746 #define CODE_FOR_loongson_psrlh CODE_FOR_lshrv4hi3
12747 #define CODE_FOR_loongson_psrlw CODE_FOR_lshrv2si3
12748 #define CODE_FOR_loongson_psrah CODE_FOR_ashrv4hi3
12749 #define CODE_FOR_loongson_psraw CODE_FOR_ashrv2si3
12750 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
12751 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
12752 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
12753 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
12754 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
12755 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
12756 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
12757 #define CODE_FOR_loongson_punpckhbh CODE_FOR_vec_interleave_highv8qi
12758 #define CODE_FOR_loongson_punpckhhw CODE_FOR_vec_interleave_highv4hi
12759 #define CODE_FOR_loongson_punpckhwd CODE_FOR_vec_interleave_highv2si
12760 #define CODE_FOR_loongson_punpcklbh CODE_FOR_vec_interleave_lowv8qi
12761 #define CODE_FOR_loongson_punpcklhw CODE_FOR_vec_interleave_lowv4hi
12762 #define CODE_FOR_loongson_punpcklwd CODE_FOR_vec_interleave_lowv2si
12764 static const struct mips_builtin_description mips_builtins[] = {
12765 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
12766 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
12767 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
12768 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
12769 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, paired_single),
12770 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, paired_single),
12771 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, paired_single),
12772 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, paired_single),
12774 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT, paired_single),
12775 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
12776 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
12777 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
12778 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, mips3d),
12780 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, mips3d),
12781 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, mips3d),
12782 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
12783 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
12784 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
12785 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
12787 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, mips3d),
12788 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, mips3d),
12789 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
12790 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
12791 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
12792 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
12794 MIPS_FP_CONDITIONS (CMP_BUILTINS),
12796 /* Built-in functions for the SB-1 processor. */
12797 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, sb1_paired_single),
12799 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
12800 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12801 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12802 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
12803 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12804 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12805 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12806 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12807 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
12808 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12809 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12810 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, dsp),
12811 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, dsp),
12812 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, dsp),
12813 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, dsp),
12814 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, dsp),
12815 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, dsp),
12816 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
12817 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
12818 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
12819 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
12820 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, dsp),
12821 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, dsp),
12822 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
12823 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
12824 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
12825 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
12826 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
12827 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
12828 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
12829 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
12830 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
12831 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
12832 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
12833 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
12834 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
12835 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
12836 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
12837 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, dsp),
12838 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
12839 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
12840 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12841 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
12842 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
12843 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, dsp),
12844 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, dsp),
12845 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, dsp),
12846 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, dsp),
12847 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
12848 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
12849 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
12850 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
12851 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
12852 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
12853 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
12854 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
12855 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
12856 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12857 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12858 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12859 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, dsp),
12860 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, dsp),
12861 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_POINTER_SI, dsp),
12862 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_POINTER_SI, dsp),
12863 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_POINTER_SI, dsp),
12864 BPOSGE_BUILTIN (32, dsp),
12866 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
12867 DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, dspr2),
12868 DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12869 DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12870 DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
12871 DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
12872 DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
12873 DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
12874 DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
12875 DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
12876 DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
12877 DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12878 DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12879 DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12880 DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12881 DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12882 DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dspr2),
12883 DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
12884 DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
12885 DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
12886 DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
12887 DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
12888 DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, dspr2),
12889 DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12890 DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12891 DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
12892 DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
12893 DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12894 DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12895 DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12896 DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12897 DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12898 DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12899 DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12900 DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12902 /* Built-in functions for the DSP ASE (32-bit only). */
12903 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
12904 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
12905 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
12906 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
12907 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12908 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12909 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12910 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
12911 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
12912 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12913 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12914 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12915 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12916 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
12917 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
12918 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
12919 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, dsp_32),
12920 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, dsp_32),
12921 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, dsp_32),
12922 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, dsp_32),
12923 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, dsp_32),
12924 DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
12925 DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32),
12926 DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
12927 DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32),
12928 DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, dsp_32),
12929 DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, dsp_32),
12931 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
12932 DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12933 DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12934 DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12935 DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12936 DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12937 DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12938 DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12939 DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12940 DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12942 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
12943 LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI),
12944 LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI),
12945 LOONGSON_BUILTIN (packushb, MIPS_UV8QI_FTYPE_UV4HI_UV4HI),
12946 LOONGSON_BUILTIN_SUFFIX (paddw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12947 LOONGSON_BUILTIN_SUFFIX (paddh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12948 LOONGSON_BUILTIN_SUFFIX (paddb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12949 LOONGSON_BUILTIN_SUFFIX (paddw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
12950 LOONGSON_BUILTIN_SUFFIX (paddh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12951 LOONGSON_BUILTIN_SUFFIX (paddb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
12952 LOONGSON_BUILTIN_SUFFIX (paddd, u, MIPS_UDI_FTYPE_UDI_UDI),
12953 LOONGSON_BUILTIN_SUFFIX (paddd, s, MIPS_DI_FTYPE_DI_DI),
12954 LOONGSON_BUILTIN (paddsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12955 LOONGSON_BUILTIN (paddsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
12956 LOONGSON_BUILTIN (paddush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12957 LOONGSON_BUILTIN (paddusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12958 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_ud, MIPS_UDI_FTYPE_UDI_UDI),
12959 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_uw, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12960 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_uh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12961 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_ub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12962 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_sd, MIPS_DI_FTYPE_DI_DI),
12963 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_sw, MIPS_V2SI_FTYPE_V2SI_V2SI),
12964 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_sh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12965 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_sb, MIPS_V8QI_FTYPE_V8QI_V8QI),
12966 LOONGSON_BUILTIN (pavgh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12967 LOONGSON_BUILTIN (pavgb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12968 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12969 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12970 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12971 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
12972 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12973 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
12974 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12975 LOONGSON_BUILTIN_SUFFIX (pcmpgth, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12976 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12977 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
12978 LOONGSON_BUILTIN_SUFFIX (pcmpgth, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12979 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
12980 LOONGSON_BUILTIN_SUFFIX (pextrh, u, MIPS_UV4HI_FTYPE_UV4HI_USI),
12981 LOONGSON_BUILTIN_SUFFIX (pextrh, s, MIPS_V4HI_FTYPE_V4HI_USI),
12982 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12983 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12984 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12985 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12986 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12987 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12988 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12989 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12990 LOONGSON_BUILTIN (pmaddhw, MIPS_V2SI_FTYPE_V4HI_V4HI),
12991 LOONGSON_BUILTIN (pmaxsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12992 LOONGSON_BUILTIN (pmaxub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12993 LOONGSON_BUILTIN (pminsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12994 LOONGSON_BUILTIN (pminub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12995 LOONGSON_BUILTIN_SUFFIX (pmovmskb, u, MIPS_UV8QI_FTYPE_UV8QI),
12996 LOONGSON_BUILTIN_SUFFIX (pmovmskb, s, MIPS_V8QI_FTYPE_V8QI),
12997 LOONGSON_BUILTIN (pmulhuh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12998 LOONGSON_BUILTIN (pmulhh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12999 LOONGSON_BUILTIN (pmullh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13000 LOONGSON_BUILTIN (pmuluw, MIPS_UDI_FTYPE_UV2SI_UV2SI),
13001 LOONGSON_BUILTIN (pasubub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13002 LOONGSON_BUILTIN (biadd, MIPS_UV4HI_FTYPE_UV8QI),
13003 LOONGSON_BUILTIN (psadbh, MIPS_UV4HI_FTYPE_UV8QI_UV8QI),
13004 LOONGSON_BUILTIN_SUFFIX (pshufh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI_UQI),
13005 LOONGSON_BUILTIN_SUFFIX (pshufh, s, MIPS_V4HI_FTYPE_V4HI_V4HI_UQI),
13006 LOONGSON_BUILTIN_SUFFIX (psllh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
13007 LOONGSON_BUILTIN_SUFFIX (psllh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
13008 LOONGSON_BUILTIN_SUFFIX (psllw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
13009 LOONGSON_BUILTIN_SUFFIX (psllw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
13010 LOONGSON_BUILTIN_SUFFIX (psrah, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
13011 LOONGSON_BUILTIN_SUFFIX (psrah, s, MIPS_V4HI_FTYPE_V4HI_UQI),
13012 LOONGSON_BUILTIN_SUFFIX (psraw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
13013 LOONGSON_BUILTIN_SUFFIX (psraw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
13014 LOONGSON_BUILTIN_SUFFIX (psrlh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
13015 LOONGSON_BUILTIN_SUFFIX (psrlh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
13016 LOONGSON_BUILTIN_SUFFIX (psrlw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
13017 LOONGSON_BUILTIN_SUFFIX (psrlw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
13018 LOONGSON_BUILTIN_SUFFIX (psubw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13019 LOONGSON_BUILTIN_SUFFIX (psubh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13020 LOONGSON_BUILTIN_SUFFIX (psubb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13021 LOONGSON_BUILTIN_SUFFIX (psubw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13022 LOONGSON_BUILTIN_SUFFIX (psubh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13023 LOONGSON_BUILTIN_SUFFIX (psubb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13024 LOONGSON_BUILTIN_SUFFIX (psubd, u, MIPS_UDI_FTYPE_UDI_UDI),
13025 LOONGSON_BUILTIN_SUFFIX (psubd, s, MIPS_DI_FTYPE_DI_DI),
13026 LOONGSON_BUILTIN (psubsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13027 LOONGSON_BUILTIN (psubsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
13028 LOONGSON_BUILTIN (psubush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13029 LOONGSON_BUILTIN (psubusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13030 LOONGSON_BUILTIN_SUFFIX (punpckhbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13031 LOONGSON_BUILTIN_SUFFIX (punpckhhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13032 LOONGSON_BUILTIN_SUFFIX (punpckhwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13033 LOONGSON_BUILTIN_SUFFIX (punpckhbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13034 LOONGSON_BUILTIN_SUFFIX (punpckhhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13035 LOONGSON_BUILTIN_SUFFIX (punpckhwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13036 LOONGSON_BUILTIN_SUFFIX (punpcklbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13037 LOONGSON_BUILTIN_SUFFIX (punpcklhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13038 LOONGSON_BUILTIN_SUFFIX (punpcklwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13039 LOONGSON_BUILTIN_SUFFIX (punpcklbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13040 LOONGSON_BUILTIN_SUFFIX (punpcklhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13041 LOONGSON_BUILTIN_SUFFIX (punpcklwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13043 /* Sundry other built-in functions. */
13044 DIRECT_NO_TARGET_BUILTIN (cache, MIPS_VOID_FTYPE_SI_CVPOINTER, cache)
13047 /* Index I is the function declaration for mips_builtins[I], or null if the
13048 function isn't defined on this target. */
13049 static GTY(()) tree mips_builtin_decls[ARRAY_SIZE (mips_builtins)];
13051 /* MODE is a vector mode whose elements have type TYPE. Return the type
13052 of the vector itself. */
13055 mips_builtin_vector_type (tree type, enum machine_mode mode)
13057 static tree types[2 * (int) MAX_MACHINE_MODE];
13060 mode_index = (int) mode;
13062 if (TREE_CODE (type) == INTEGER_TYPE && TYPE_UNSIGNED (type))
13063 mode_index += MAX_MACHINE_MODE;
13065 if (types[mode_index] == NULL_TREE)
13066 types[mode_index] = build_vector_type_for_mode (type, mode);
13067 return types[mode_index];
13070 /* Return a type for 'const volatile void *'. */
13073 mips_build_cvpointer_type (void)
13077 if (cache == NULL_TREE)
13078 cache = build_pointer_type (build_qualified_type
13080 TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE));
13084 /* Source-level argument types. */
13085 #define MIPS_ATYPE_VOID void_type_node
13086 #define MIPS_ATYPE_INT integer_type_node
13087 #define MIPS_ATYPE_POINTER ptr_type_node
13088 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
13090 /* Standard mode-based argument types. */
13091 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
13092 #define MIPS_ATYPE_SI intSI_type_node
13093 #define MIPS_ATYPE_USI unsigned_intSI_type_node
13094 #define MIPS_ATYPE_DI intDI_type_node
13095 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
13096 #define MIPS_ATYPE_SF float_type_node
13097 #define MIPS_ATYPE_DF double_type_node
13099 /* Vector argument types. */
13100 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
13101 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
13102 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
13103 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
13104 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
13105 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
13106 #define MIPS_ATYPE_UV2SI \
13107 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
13108 #define MIPS_ATYPE_UV4HI \
13109 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
13110 #define MIPS_ATYPE_UV8QI \
13111 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
13113 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
13114 their associated MIPS_ATYPEs. */
13115 #define MIPS_FTYPE_ATYPES1(A, B) \
13116 MIPS_ATYPE_##A, MIPS_ATYPE_##B
13118 #define MIPS_FTYPE_ATYPES2(A, B, C) \
13119 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
13121 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
13122 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
13124 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
13125 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
13128 /* Return the function type associated with function prototype TYPE. */
13131 mips_build_function_type (enum mips_function_type type)
13133 static tree types[(int) MIPS_MAX_FTYPE_MAX];
13135 if (types[(int) type] == NULL_TREE)
13138 #define DEF_MIPS_FTYPE(NUM, ARGS) \
13139 case MIPS_FTYPE_NAME##NUM ARGS: \
13140 types[(int) type] \
13141 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
13144 #include "config/mips/mips-ftypes.def"
13145 #undef DEF_MIPS_FTYPE
13147 gcc_unreachable ();
13150 return types[(int) type];
13153 /* Implement TARGET_INIT_BUILTINS. */
13156 mips_init_builtins (void)
13158 const struct mips_builtin_description *d;
13161 /* Iterate through all of the bdesc arrays, initializing all of the
13162 builtin functions. */
13163 for (i = 0; i < ARRAY_SIZE (mips_builtins); i++)
13165 d = &mips_builtins[i];
13167 mips_builtin_decls[i]
13168 = add_builtin_function (d->name,
13169 mips_build_function_type (d->function_type),
13170 i, BUILT_IN_MD, NULL, NULL);
13174 /* Implement TARGET_BUILTIN_DECL. */
13177 mips_builtin_decl (unsigned int code, bool initialize_p ATTRIBUTE_UNUSED)
13179 if (code >= ARRAY_SIZE (mips_builtins))
13180 return error_mark_node;
13181 return mips_builtin_decls[code];
13184 /* Take argument ARGNO from EXP's argument list and convert it into a
13185 form suitable for input operand OPNO of instruction ICODE. Return the
13189 mips_prepare_builtin_arg (enum insn_code icode,
13190 unsigned int opno, tree exp, unsigned int argno)
13194 enum machine_mode mode;
13196 arg = CALL_EXPR_ARG (exp, argno);
13197 value = expand_normal (arg);
13198 mode = insn_data[icode].operand[opno].mode;
13199 if (!insn_data[icode].operand[opno].predicate (value, mode))
13201 /* We need to get the mode from ARG for two reasons:
13203 - to cope with address operands, where MODE is the mode of the
13204 memory, rather than of VALUE itself.
13206 - to cope with special predicates like pmode_register_operand,
13207 where MODE is VOIDmode. */
13208 value = copy_to_mode_reg (TYPE_MODE (TREE_TYPE (arg)), value);
13210 /* Check the predicate again. */
13211 if (!insn_data[icode].operand[opno].predicate (value, mode))
13213 error ("invalid argument to built-in function");
13221 /* Return an rtx suitable for output operand OP of instruction ICODE.
13222 If TARGET is non-null, try to use it where possible. */
13225 mips_prepare_builtin_target (enum insn_code icode, unsigned int op, rtx target)
13227 enum machine_mode mode;
13229 mode = insn_data[icode].operand[op].mode;
13230 if (target == 0 || !insn_data[icode].operand[op].predicate (target, mode))
13231 target = gen_reg_rtx (mode);
13236 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
13237 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
13238 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
13239 suggests a good place to put the result. */
13242 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
13245 rtx ops[MAX_RECOG_OPERANDS];
13248 /* Map any target to operand 0. */
13252 target = mips_prepare_builtin_target (icode, opno, target);
13253 ops[opno] = target;
13257 /* Map the arguments to the other operands. The n_operands value
13258 for an expander includes match_dups and match_scratches as well as
13259 match_operands, so n_operands is only an upper bound on the number
13260 of arguments to the expander function. */
13261 gcc_assert (opno + call_expr_nargs (exp) <= insn_data[icode].n_operands);
13262 for (argno = 0; argno < call_expr_nargs (exp); argno++, opno++)
13263 ops[opno] = mips_prepare_builtin_arg (icode, opno, exp, argno);
13268 emit_insn (GEN_FCN (icode) (ops[0], ops[1]));
13272 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2]));
13276 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3]));
13280 gcc_unreachable ();
13285 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
13286 function; TYPE says which. EXP is the CALL_EXPR that calls the
13287 function, ICODE is the instruction that should be used to compare
13288 the first two arguments, and COND is the condition it should test.
13289 TARGET, if nonnull, suggests a good place to put the result. */
13292 mips_expand_builtin_movtf (enum mips_builtin_type type,
13293 enum insn_code icode, enum mips_fp_condition cond,
13294 rtx target, tree exp)
13296 rtx cmp_result, op0, op1;
13298 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
13299 op0 = mips_prepare_builtin_arg (icode, 1, exp, 0);
13300 op1 = mips_prepare_builtin_arg (icode, 2, exp, 1);
13301 emit_insn (GEN_FCN (icode) (cmp_result, op0, op1, GEN_INT (cond)));
13303 icode = CODE_FOR_mips_cond_move_tf_ps;
13304 target = mips_prepare_builtin_target (icode, 0, target);
13305 if (type == MIPS_BUILTIN_MOVT)
13307 op1 = mips_prepare_builtin_arg (icode, 2, exp, 2);
13308 op0 = mips_prepare_builtin_arg (icode, 1, exp, 3);
13312 op0 = mips_prepare_builtin_arg (icode, 1, exp, 2);
13313 op1 = mips_prepare_builtin_arg (icode, 2, exp, 3);
13315 emit_insn (gen_mips_cond_move_tf_ps (target, op0, op1, cmp_result));
13319 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
13320 into TARGET otherwise. Return TARGET. */
13323 mips_builtin_branch_and_move (rtx condition, rtx target,
13324 rtx value_if_true, rtx value_if_false)
13326 rtx true_label, done_label;
13328 true_label = gen_label_rtx ();
13329 done_label = gen_label_rtx ();
13331 /* First assume that CONDITION is false. */
13332 mips_emit_move (target, value_if_false);
13334 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
13335 emit_jump_insn (gen_condjump (condition, true_label));
13336 emit_jump_insn (gen_jump (done_label));
13339 /* Fix TARGET if CONDITION is true. */
13340 emit_label (true_label);
13341 mips_emit_move (target, value_if_true);
13343 emit_label (done_label);
13347 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
13348 the CALL_EXPR that calls the function, ICODE is the code of the
13349 comparison instruction, and COND is the condition it should test.
13350 TARGET, if nonnull, suggests a good place to put the boolean result. */
13353 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
13354 enum insn_code icode, enum mips_fp_condition cond,
13355 rtx target, tree exp)
13357 rtx offset, condition, cmp_result, args[MAX_RECOG_OPERANDS];
13360 if (target == 0 || GET_MODE (target) != SImode)
13361 target = gen_reg_rtx (SImode);
13363 /* The instruction should have a target operand, an operand for each
13364 argument, and an operand for COND. */
13365 gcc_assert (call_expr_nargs (exp) + 2 == insn_data[icode].n_operands);
13367 /* Prepare the operands to the comparison. */
13368 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
13369 for (argno = 0; argno < call_expr_nargs (exp); argno++)
13370 args[argno] = mips_prepare_builtin_arg (icode, argno + 1, exp, argno);
13372 switch (insn_data[icode].n_operands)
13375 emit_insn (GEN_FCN (icode) (cmp_result, args[0], args[1],
13380 emit_insn (GEN_FCN (icode) (cmp_result, args[0], args[1],
13381 args[2], args[3], GEN_INT (cond)));
13385 gcc_unreachable ();
13388 /* If the comparison sets more than one register, we define the result
13389 to be 0 if all registers are false and -1 if all registers are true.
13390 The value of the complete result is indeterminate otherwise. */
13391 switch (builtin_type)
13393 case MIPS_BUILTIN_CMP_ALL:
13394 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
13395 return mips_builtin_branch_and_move (condition, target,
13396 const0_rtx, const1_rtx);
13398 case MIPS_BUILTIN_CMP_UPPER:
13399 case MIPS_BUILTIN_CMP_LOWER:
13400 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
13401 condition = gen_single_cc (cmp_result, offset);
13402 return mips_builtin_branch_and_move (condition, target,
13403 const1_rtx, const0_rtx);
13406 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
13407 return mips_builtin_branch_and_move (condition, target,
13408 const1_rtx, const0_rtx);
13412 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
13413 if nonnull, suggests a good place to put the boolean result. */
13416 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
13418 rtx condition, cmp_result;
13421 if (target == 0 || GET_MODE (target) != SImode)
13422 target = gen_reg_rtx (SImode);
13424 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
13426 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
13431 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
13432 return mips_builtin_branch_and_move (condition, target,
13433 const1_rtx, const0_rtx);
13436 /* Implement TARGET_EXPAND_BUILTIN. */
13439 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
13440 enum machine_mode mode, int ignore)
13443 unsigned int fcode, avail;
13444 const struct mips_builtin_description *d;
13446 fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
13447 fcode = DECL_FUNCTION_CODE (fndecl);
13448 gcc_assert (fcode < ARRAY_SIZE (mips_builtins));
13449 d = &mips_builtins[fcode];
13450 avail = d->avail ();
13451 gcc_assert (avail != 0);
13454 error ("built-in function %qE not supported for MIPS16",
13455 DECL_NAME (fndecl));
13456 return ignore ? const0_rtx : CONST0_RTX (mode);
13458 switch (d->builtin_type)
13460 case MIPS_BUILTIN_DIRECT:
13461 return mips_expand_builtin_direct (d->icode, target, exp, true);
13463 case MIPS_BUILTIN_DIRECT_NO_TARGET:
13464 return mips_expand_builtin_direct (d->icode, target, exp, false);
13466 case MIPS_BUILTIN_MOVT:
13467 case MIPS_BUILTIN_MOVF:
13468 return mips_expand_builtin_movtf (d->builtin_type, d->icode,
13469 d->cond, target, exp);
13471 case MIPS_BUILTIN_CMP_ANY:
13472 case MIPS_BUILTIN_CMP_ALL:
13473 case MIPS_BUILTIN_CMP_UPPER:
13474 case MIPS_BUILTIN_CMP_LOWER:
13475 case MIPS_BUILTIN_CMP_SINGLE:
13476 return mips_expand_builtin_compare (d->builtin_type, d->icode,
13477 d->cond, target, exp);
13479 case MIPS_BUILTIN_BPOSGE32:
13480 return mips_expand_builtin_bposge (d->builtin_type, target);
13482 gcc_unreachable ();
13485 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
13486 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
13487 struct mips16_constant {
13488 struct mips16_constant *next;
13491 enum machine_mode mode;
13494 /* Information about an incomplete MIPS16 constant pool. FIRST is the
13495 first constant, HIGHEST_ADDRESS is the highest address that the first
13496 byte of the pool can have, and INSN_ADDRESS is the current instruction
13498 struct mips16_constant_pool {
13499 struct mips16_constant *first;
13500 int highest_address;
13504 /* Add constant VALUE to POOL and return its label. MODE is the
13505 value's mode (used for CONST_INTs, etc.). */
13508 mips16_add_constant (struct mips16_constant_pool *pool,
13509 rtx value, enum machine_mode mode)
13511 struct mips16_constant **p, *c;
13512 bool first_of_size_p;
13514 /* See whether the constant is already in the pool. If so, return the
13515 existing label, otherwise leave P pointing to the place where the
13516 constant should be added.
13518 Keep the pool sorted in increasing order of mode size so that we can
13519 reduce the number of alignments needed. */
13520 first_of_size_p = true;
13521 for (p = &pool->first; *p != 0; p = &(*p)->next)
13523 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
13524 return (*p)->label;
13525 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
13527 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
13528 first_of_size_p = false;
13531 /* In the worst case, the constant needed by the earliest instruction
13532 will end up at the end of the pool. The entire pool must then be
13533 accessible from that instruction.
13535 When adding the first constant, set the pool's highest address to
13536 the address of the first out-of-range byte. Adjust this address
13537 downwards each time a new constant is added. */
13538 if (pool->first == 0)
13539 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
13540 of the instruction with the lowest two bits clear. The base PC
13541 value for LDPC has the lowest three bits clear. Assume the worst
13542 case here; namely that the PC-relative instruction occupies the
13543 last 2 bytes in an aligned word. */
13544 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
13545 pool->highest_address -= GET_MODE_SIZE (mode);
13546 if (first_of_size_p)
13547 /* Take into account the worst possible padding due to alignment. */
13548 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
13550 /* Create a new entry. */
13551 c = XNEW (struct mips16_constant);
13554 c->label = gen_label_rtx ();
13561 /* Output constant VALUE after instruction INSN and return the last
13562 instruction emitted. MODE is the mode of the constant. */
13565 mips16_emit_constants_1 (enum machine_mode mode, rtx value, rtx insn)
13567 if (SCALAR_INT_MODE_P (mode) || ALL_SCALAR_FIXED_POINT_MODE_P (mode))
13569 rtx size = GEN_INT (GET_MODE_SIZE (mode));
13570 return emit_insn_after (gen_consttable_int (value, size), insn);
13573 if (SCALAR_FLOAT_MODE_P (mode))
13574 return emit_insn_after (gen_consttable_float (value), insn);
13576 if (VECTOR_MODE_P (mode))
13580 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
13581 insn = mips16_emit_constants_1 (GET_MODE_INNER (mode),
13582 CONST_VECTOR_ELT (value, i), insn);
13586 gcc_unreachable ();
13589 /* Dump out the constants in CONSTANTS after INSN. */
13592 mips16_emit_constants (struct mips16_constant *constants, rtx insn)
13594 struct mips16_constant *c, *next;
13598 for (c = constants; c != NULL; c = next)
13600 /* If necessary, increase the alignment of PC. */
13601 if (align < GET_MODE_SIZE (c->mode))
13603 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
13604 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
13606 align = GET_MODE_SIZE (c->mode);
13608 insn = emit_label_after (c->label, insn);
13609 insn = mips16_emit_constants_1 (c->mode, c->value, insn);
13615 emit_barrier_after (insn);
13618 /* Return the length of instruction INSN. */
13621 mips16_insn_length (rtx insn)
13625 rtx body = PATTERN (insn);
13626 if (GET_CODE (body) == ADDR_VEC)
13627 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
13628 if (GET_CODE (body) == ADDR_DIFF_VEC)
13629 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
13631 return get_attr_length (insn);
13634 /* If *X is a symbolic constant that refers to the constant pool, add
13635 the constant to POOL and rewrite *X to use the constant's label. */
13638 mips16_rewrite_pool_constant (struct mips16_constant_pool *pool, rtx *x)
13640 rtx base, offset, label;
13642 split_const (*x, &base, &offset);
13643 if (GET_CODE (base) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (base))
13645 label = mips16_add_constant (pool, get_pool_constant (base),
13646 get_pool_mode (base));
13647 base = gen_rtx_LABEL_REF (Pmode, label);
13648 *x = mips_unspec_address_offset (base, offset, SYMBOL_PC_RELATIVE);
13652 /* This structure is used to communicate with mips16_rewrite_pool_refs.
13653 INSN is the instruction we're rewriting and POOL points to the current
13655 struct mips16_rewrite_pool_refs_info {
13657 struct mips16_constant_pool *pool;
13660 /* Rewrite *X so that constant pool references refer to the constant's
13661 label instead. DATA points to a mips16_rewrite_pool_refs_info
13665 mips16_rewrite_pool_refs (rtx *x, void *data)
13667 struct mips16_rewrite_pool_refs_info *info =
13668 (struct mips16_rewrite_pool_refs_info *) data;
13670 if (force_to_mem_operand (*x, Pmode))
13672 rtx mem = force_const_mem (GET_MODE (*x), *x);
13673 validate_change (info->insn, x, mem, false);
13678 mips16_rewrite_pool_constant (info->pool, &XEXP (*x, 0));
13682 if (TARGET_MIPS16_TEXT_LOADS)
13683 mips16_rewrite_pool_constant (info->pool, x);
13685 return GET_CODE (*x) == CONST ? -1 : 0;
13688 /* Return whether CFG is used in mips_reorg. */
13691 mips_cfg_in_reorg (void)
13693 return (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
13694 || TARGET_RELAX_PIC_CALLS);
13697 /* Build MIPS16 constant pools. */
13700 mips16_lay_out_constants (void)
13702 struct mips16_constant_pool pool;
13703 struct mips16_rewrite_pool_refs_info info;
13706 if (!TARGET_MIPS16_PCREL_LOADS)
13709 if (mips_cfg_in_reorg ())
13710 split_all_insns ();
13712 split_all_insns_noflow ();
13714 memset (&pool, 0, sizeof (pool));
13715 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
13717 /* Rewrite constant pool references in INSN. */
13718 if (USEFUL_INSN_P (insn))
13722 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &info);
13725 pool.insn_address += mips16_insn_length (insn);
13727 if (pool.first != NULL)
13729 /* If there are no natural barriers between the first user of
13730 the pool and the highest acceptable address, we'll need to
13731 create a new instruction to jump around the constant pool.
13732 In the worst case, this instruction will be 4 bytes long.
13734 If it's too late to do this transformation after INSN,
13735 do it immediately before INSN. */
13736 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
13740 label = gen_label_rtx ();
13742 jump = emit_jump_insn_before (gen_jump (label), insn);
13743 JUMP_LABEL (jump) = label;
13744 LABEL_NUSES (label) = 1;
13745 barrier = emit_barrier_after (jump);
13747 emit_label_after (label, barrier);
13748 pool.insn_address += 4;
13751 /* See whether the constant pool is now out of range of the first
13752 user. If so, output the constants after the previous barrier.
13753 Note that any instructions between BARRIER and INSN (inclusive)
13754 will use negative offsets to refer to the pool. */
13755 if (pool.insn_address > pool.highest_address)
13757 mips16_emit_constants (pool.first, barrier);
13761 else if (BARRIER_P (insn))
13765 mips16_emit_constants (pool.first, get_last_insn ());
13768 /* Return true if it is worth r10k_simplify_address's while replacing
13769 an address with X. We are looking for constants, and for addresses
13770 at a known offset from the incoming stack pointer. */
13773 r10k_simplified_address_p (rtx x)
13775 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
13777 return x == virtual_incoming_args_rtx || CONSTANT_P (x);
13780 /* X is an expression that appears in INSN. Try to use the UD chains
13781 to simplify it, returning the simplified form on success and the
13782 original form otherwise. Replace the incoming value of $sp with
13783 virtual_incoming_args_rtx (which should never occur in X otherwise). */
13786 r10k_simplify_address (rtx x, rtx insn)
13788 rtx newx, op0, op1, set, def_insn, note;
13790 struct df_link *defs;
13795 op0 = r10k_simplify_address (XEXP (x, 0), insn);
13796 if (op0 != XEXP (x, 0))
13797 newx = simplify_gen_unary (GET_CODE (x), GET_MODE (x),
13798 op0, GET_MODE (XEXP (x, 0)));
13800 else if (BINARY_P (x))
13802 op0 = r10k_simplify_address (XEXP (x, 0), insn);
13803 op1 = r10k_simplify_address (XEXP (x, 1), insn);
13804 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
13805 newx = simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
13807 else if (GET_CODE (x) == LO_SUM)
13809 /* LO_SUMs can be offset from HIGHs, if we know they won't
13810 overflow. See mips_classify_address for the rationale behind
13812 op0 = r10k_simplify_address (XEXP (x, 0), insn);
13813 if (GET_CODE (op0) == HIGH)
13814 newx = XEXP (x, 1);
13816 else if (REG_P (x))
13818 /* Uses are recorded by regno_reg_rtx, not X itself. */
13819 use = df_find_use (insn, regno_reg_rtx[REGNO (x)]);
13821 defs = DF_REF_CHAIN (use);
13823 /* Require a single definition. */
13824 if (defs && defs->next == NULL)
13827 if (DF_REF_IS_ARTIFICIAL (def))
13829 /* Replace the incoming value of $sp with
13830 virtual_incoming_args_rtx. */
13831 if (x == stack_pointer_rtx
13832 && DF_REF_BB (def) == ENTRY_BLOCK_PTR)
13833 newx = virtual_incoming_args_rtx;
13835 else if (dominated_by_p (CDI_DOMINATORS, DF_REF_BB (use),
13838 /* Make sure that DEF_INSN is a single set of REG. */
13839 def_insn = DF_REF_INSN (def);
13840 if (NONJUMP_INSN_P (def_insn))
13842 set = single_set (def_insn);
13843 if (set && rtx_equal_p (SET_DEST (set), x))
13845 /* Prefer to use notes, since the def-use chains
13846 are often shorter. */
13847 note = find_reg_equal_equiv_note (def_insn);
13849 newx = XEXP (note, 0);
13851 newx = SET_SRC (set);
13852 newx = r10k_simplify_address (newx, def_insn);
13858 if (newx && r10k_simplified_address_p (newx))
13863 /* Return true if ADDRESS is known to be an uncached address
13864 on R10K systems. */
13867 r10k_uncached_address_p (unsigned HOST_WIDE_INT address)
13869 unsigned HOST_WIDE_INT upper;
13871 /* Check for KSEG1. */
13872 if (address + 0x60000000 < 0x20000000)
13875 /* Check for uncached XKPHYS addresses. */
13876 if (Pmode == DImode)
13878 upper = (address >> 40) & 0xf9ffff;
13879 if (upper == 0x900000 || upper == 0xb80000)
13885 /* Return true if we can prove that an access to address X in instruction
13886 INSN would be safe from R10K speculation. This X is a general
13887 expression; it might not be a legitimate address. */
13890 r10k_safe_address_p (rtx x, rtx insn)
13893 HOST_WIDE_INT offset_val;
13895 x = r10k_simplify_address (x, insn);
13897 /* Check for references to the stack frame. It doesn't really matter
13898 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
13899 allows us to assume that accesses to any part of the eventual frame
13900 is safe from speculation at any point in the function. */
13901 mips_split_plus (x, &base, &offset_val);
13902 if (base == virtual_incoming_args_rtx
13903 && offset_val >= -cfun->machine->frame.total_size
13904 && offset_val < cfun->machine->frame.args_size)
13907 /* Check for uncached addresses. */
13908 if (CONST_INT_P (x))
13909 return r10k_uncached_address_p (INTVAL (x));
13911 /* Check for accesses to a static object. */
13912 split_const (x, &base, &offset);
13913 return offset_within_block_p (base, INTVAL (offset));
13916 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
13917 an in-range access to an automatic variable, or to an object with
13918 a link-time-constant address. */
13921 r10k_safe_mem_expr_p (tree expr, rtx offset)
13923 if (expr == NULL_TREE
13924 || offset == NULL_RTX
13925 || !CONST_INT_P (offset)
13926 || INTVAL (offset) < 0
13927 || INTVAL (offset) >= int_size_in_bytes (TREE_TYPE (expr)))
13930 while (TREE_CODE (expr) == COMPONENT_REF)
13932 expr = TREE_OPERAND (expr, 0);
13933 if (expr == NULL_TREE)
13937 return DECL_P (expr);
13940 /* A for_each_rtx callback for which DATA points to the instruction
13941 containing *X. Stop the search if we find a MEM that is not safe
13942 from R10K speculation. */
13945 r10k_needs_protection_p_1 (rtx *loc, void *data)
13953 if (r10k_safe_mem_expr_p (MEM_EXPR (mem), MEM_OFFSET (mem)))
13956 if (r10k_safe_address_p (XEXP (mem, 0), (rtx) data))
13962 /* A note_stores callback for which DATA points to an instruction pointer.
13963 If *DATA is nonnull, make it null if it X contains a MEM that is not
13964 safe from R10K speculation. */
13967 r10k_needs_protection_p_store (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
13972 insn_ptr = (rtx *) data;
13973 if (*insn_ptr && for_each_rtx (&x, r10k_needs_protection_p_1, *insn_ptr))
13974 *insn_ptr = NULL_RTX;
13977 /* A for_each_rtx callback that iterates over the pattern of a CALL_INSN.
13978 Return nonzero if the call is not to a declared function. */
13981 r10k_needs_protection_p_call (rtx *loc, void *data ATTRIBUTE_UNUSED)
13990 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DECL (x))
13996 /* Return true if instruction INSN needs to be protected by an R10K
14000 r10k_needs_protection_p (rtx insn)
14003 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_call, NULL);
14005 if (mips_r10k_cache_barrier == R10K_CACHE_BARRIER_STORE)
14007 note_stores (PATTERN (insn), r10k_needs_protection_p_store, &insn);
14008 return insn == NULL_RTX;
14011 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_1, insn);
14014 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
14015 edge is unconditional. */
14018 r10k_protected_bb_p (basic_block bb, sbitmap protected_bbs)
14023 FOR_EACH_EDGE (e, ei, bb->preds)
14024 if (!single_succ_p (e->src)
14025 || !TEST_BIT (protected_bbs, e->src->index)
14026 || (e->flags & EDGE_COMPLEX) != 0)
14031 /* Implement -mr10k-cache-barrier= for the current function. */
14034 r10k_insert_cache_barriers (void)
14036 int *rev_post_order;
14039 sbitmap protected_bbs;
14040 rtx insn, end, unprotected_region;
14044 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
14048 /* Calculate dominators. */
14049 calculate_dominance_info (CDI_DOMINATORS);
14051 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
14052 X is protected by a cache barrier. */
14053 protected_bbs = sbitmap_alloc (last_basic_block);
14054 sbitmap_zero (protected_bbs);
14056 /* Iterate over the basic blocks in reverse post-order. */
14057 rev_post_order = XNEWVEC (int, last_basic_block);
14058 n = pre_and_rev_post_order_compute (NULL, rev_post_order, false);
14059 for (i = 0; i < n; i++)
14061 bb = BASIC_BLOCK (rev_post_order[i]);
14063 /* If this block is only reached by unconditional edges, and if the
14064 source of every edge is protected, the beginning of the block is
14066 if (r10k_protected_bb_p (bb, protected_bbs))
14067 unprotected_region = NULL_RTX;
14069 unprotected_region = pc_rtx;
14070 end = NEXT_INSN (BB_END (bb));
14072 /* UNPROTECTED_REGION is:
14074 - null if we are processing a protected region,
14075 - pc_rtx if we are processing an unprotected region but have
14076 not yet found the first instruction in it
14077 - the first instruction in an unprotected region otherwise. */
14078 for (insn = BB_HEAD (bb); insn != end; insn = NEXT_INSN (insn))
14080 if (unprotected_region && USEFUL_INSN_P (insn))
14082 if (recog_memoized (insn) == CODE_FOR_mips_cache)
14083 /* This CACHE instruction protects the following code. */
14084 unprotected_region = NULL_RTX;
14087 /* See if INSN is the first instruction in this
14088 unprotected region. */
14089 if (unprotected_region == pc_rtx)
14090 unprotected_region = insn;
14092 /* See if INSN needs to be protected. If so,
14093 we must insert a cache barrier somewhere between
14094 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
14095 clear which position is better performance-wise,
14096 but as a tie-breaker, we assume that it is better
14097 to allow delay slots to be back-filled where
14098 possible, and that it is better not to insert
14099 barriers in the middle of already-scheduled code.
14100 We therefore insert the barrier at the beginning
14102 if (r10k_needs_protection_p (insn))
14104 emit_insn_before (gen_r10k_cache_barrier (),
14105 unprotected_region);
14106 unprotected_region = NULL_RTX;
14112 /* The called function is not required to protect the exit path.
14113 The code that follows a call is therefore unprotected. */
14114 unprotected_region = pc_rtx;
14117 /* Record whether the end of this block is protected. */
14118 if (unprotected_region == NULL_RTX)
14119 SET_BIT (protected_bbs, bb->index);
14121 XDELETEVEC (rev_post_order);
14123 sbitmap_free (protected_bbs);
14125 free_dominance_info (CDI_DOMINATORS);
14128 /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX
14129 otherwise. If INSN has two call rtx, then store the second one in
14133 mips_call_expr_from_insn (rtx insn, rtx *second_call)
14138 if (!CALL_P (insn))
14141 x = PATTERN (insn);
14142 if (GET_CODE (x) == PARALLEL)
14144 /* Calls returning complex values have two CALL rtx. Look for the second
14145 one here, and return it via the SECOND_CALL arg. */
14146 x2 = XVECEXP (x, 0, 1);
14147 if (GET_CODE (x2) == SET)
14149 if (GET_CODE (x2) == CALL)
14152 x = XVECEXP (x, 0, 0);
14154 if (GET_CODE (x) == SET)
14156 gcc_assert (GET_CODE (x) == CALL);
14161 /* REG is set in DEF. See if the definition is one of the ways we load a
14162 register with a symbol address for a mips_use_pic_fn_addr_reg_p call. If
14163 it is return the symbol reference of the function, otherwise return
14167 mips_pic_call_symbol_from_set (df_ref def, rtx reg)
14171 if (DF_REF_IS_ARTIFICIAL (def))
14174 def_insn = DF_REF_INSN (def);
14175 set = single_set (def_insn);
14176 if (set && rtx_equal_p (SET_DEST (set), reg))
14178 rtx note, src, symbol;
14180 /* First, look at REG_EQUAL/EQUIV notes. */
14181 note = find_reg_equal_equiv_note (def_insn);
14182 if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF)
14183 return XEXP (note, 0);
14185 /* For %call16 references we don't have REG_EQUAL. */
14186 src = SET_SRC (set);
14187 symbol = mips_strip_unspec_call (src);
14190 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
14194 /* Follow simple register copies. */
14196 return mips_find_pic_call_symbol (def_insn, src);
14202 /* Find the definition of the use of REG in INSN. See if the definition is
14203 one of the ways we load a register with a symbol address for a
14204 mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference of
14205 the function, otherwise return NULL_RTX. */
14208 mips_find_pic_call_symbol (rtx insn, rtx reg)
14211 struct df_link *defs;
14214 use = df_find_use (insn, regno_reg_rtx[REGNO (reg)]);
14217 defs = DF_REF_CHAIN (use);
14220 symbol = mips_pic_call_symbol_from_set (defs->ref, reg);
14224 /* If we have more than one definition, they need to be identical. */
14225 for (defs = defs->next; defs; defs = defs->next)
14229 other = mips_pic_call_symbol_from_set (defs->ref, reg);
14230 if (!rtx_equal_p (symbol, other))
14237 /* Replace the args_size operand of the call expression CALL with the
14238 call-attribute UNSPEC and fill in SYMBOL as the function symbol. */
14241 mips_annotate_pic_call_expr (rtx call, rtx symbol)
14245 args_size = XEXP (call, 1);
14246 XEXP (call, 1) = gen_rtx_UNSPEC (GET_MODE (args_size),
14247 gen_rtvec (2, args_size, symbol),
14251 /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See
14252 if instead of the arg_size argument it contains the call attributes. If
14253 yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function
14254 symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is
14258 mips_get_pic_call_symbol (rtx *operands, int args_size_opno)
14260 rtx args_size, symbol;
14262 if (!TARGET_RELAX_PIC_CALLS || args_size_opno == -1)
14265 args_size = operands[args_size_opno];
14266 if (GET_CODE (args_size) != UNSPEC)
14268 gcc_assert (XINT (args_size, 1) == UNSPEC_CALL_ATTR);
14270 symbol = XVECEXP (args_size, 0, 1);
14271 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
14273 operands[args_size_opno] = symbol;
14277 /* Use DF to annotate PIC indirect calls with the function symbol they
14281 mips_annotate_pic_calls (void)
14287 FOR_BB_INSNS (bb, insn)
14289 rtx call, reg, symbol, second_call;
14292 call = mips_call_expr_from_insn (insn, &second_call);
14295 gcc_assert (MEM_P (XEXP (call, 0)));
14296 reg = XEXP (XEXP (call, 0), 0);
14300 symbol = mips_find_pic_call_symbol (insn, reg);
14303 mips_annotate_pic_call_expr (call, symbol);
14305 mips_annotate_pic_call_expr (second_call, symbol);
14310 /* A temporary variable used by for_each_rtx callbacks, etc. */
14311 static rtx mips_sim_insn;
14313 /* A structure representing the state of the processor pipeline.
14314 Used by the mips_sim_* family of functions. */
14316 /* The maximum number of instructions that can be issued in a cycle.
14317 (Caches mips_issue_rate.) */
14318 unsigned int issue_rate;
14320 /* The current simulation time. */
14323 /* How many more instructions can be issued in the current cycle. */
14324 unsigned int insns_left;
14326 /* LAST_SET[X].INSN is the last instruction to set register X.
14327 LAST_SET[X].TIME is the time at which that instruction was issued.
14328 INSN is null if no instruction has yet set register X. */
14332 } last_set[FIRST_PSEUDO_REGISTER];
14334 /* The pipeline's current DFA state. */
14338 /* Reset STATE to the initial simulation state. */
14341 mips_sim_reset (struct mips_sim *state)
14344 state->insns_left = state->issue_rate;
14345 memset (&state->last_set, 0, sizeof (state->last_set));
14346 state_reset (state->dfa_state);
14349 /* Initialize STATE before its first use. DFA_STATE points to an
14350 allocated but uninitialized DFA state. */
14353 mips_sim_init (struct mips_sim *state, state_t dfa_state)
14355 state->issue_rate = mips_issue_rate ();
14356 state->dfa_state = dfa_state;
14357 mips_sim_reset (state);
14360 /* Advance STATE by one clock cycle. */
14363 mips_sim_next_cycle (struct mips_sim *state)
14366 state->insns_left = state->issue_rate;
14367 state_transition (state->dfa_state, 0);
14370 /* Advance simulation state STATE until instruction INSN can read
14374 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
14376 unsigned int regno, end_regno;
14378 end_regno = END_REGNO (reg);
14379 for (regno = REGNO (reg); regno < end_regno; regno++)
14380 if (state->last_set[regno].insn != 0)
14384 t = (state->last_set[regno].time
14385 + insn_latency (state->last_set[regno].insn, insn));
14386 while (state->time < t)
14387 mips_sim_next_cycle (state);
14391 /* A for_each_rtx callback. If *X is a register, advance simulation state
14392 DATA until mips_sim_insn can read the register's value. */
14395 mips_sim_wait_regs_2 (rtx *x, void *data)
14398 mips_sim_wait_reg ((struct mips_sim *) data, mips_sim_insn, *x);
14402 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
14405 mips_sim_wait_regs_1 (rtx *x, void *data)
14407 for_each_rtx (x, mips_sim_wait_regs_2, data);
14410 /* Advance simulation state STATE until all of INSN's register
14411 dependencies are satisfied. */
14414 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
14416 mips_sim_insn = insn;
14417 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
14420 /* Advance simulation state STATE until the units required by
14421 instruction INSN are available. */
14424 mips_sim_wait_units (struct mips_sim *state, rtx insn)
14428 tmp_state = alloca (state_size ());
14429 while (state->insns_left == 0
14430 || (memcpy (tmp_state, state->dfa_state, state_size ()),
14431 state_transition (tmp_state, insn) >= 0))
14432 mips_sim_next_cycle (state);
14435 /* Advance simulation state STATE until INSN is ready to issue. */
14438 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
14440 mips_sim_wait_regs (state, insn);
14441 mips_sim_wait_units (state, insn);
14444 /* mips_sim_insn has just set X. Update the LAST_SET array
14445 in simulation state DATA. */
14448 mips_sim_record_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
14450 struct mips_sim *state;
14452 state = (struct mips_sim *) data;
14455 unsigned int regno, end_regno;
14457 end_regno = END_REGNO (x);
14458 for (regno = REGNO (x); regno < end_regno; regno++)
14460 state->last_set[regno].insn = mips_sim_insn;
14461 state->last_set[regno].time = state->time;
14466 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
14467 can issue immediately (i.e., that mips_sim_wait_insn has already
14471 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
14473 state_transition (state->dfa_state, insn);
14474 state->insns_left--;
14476 mips_sim_insn = insn;
14477 note_stores (PATTERN (insn), mips_sim_record_set, state);
14480 /* Simulate issuing a NOP in state STATE. */
14483 mips_sim_issue_nop (struct mips_sim *state)
14485 if (state->insns_left == 0)
14486 mips_sim_next_cycle (state);
14487 state->insns_left--;
14490 /* Update simulation state STATE so that it's ready to accept the instruction
14491 after INSN. INSN should be part of the main rtl chain, not a member of a
14495 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
14497 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
14499 mips_sim_issue_nop (state);
14501 switch (GET_CODE (SEQ_BEGIN (insn)))
14505 /* We can't predict the processor state after a call or label. */
14506 mips_sim_reset (state);
14510 /* The delay slots of branch likely instructions are only executed
14511 when the branch is taken. Therefore, if the caller has simulated
14512 the delay slot instruction, STATE does not really reflect the state
14513 of the pipeline for the instruction after the delay slot. Also,
14514 branch likely instructions tend to incur a penalty when not taken,
14515 so there will probably be an extra delay between the branch and
14516 the instruction after the delay slot. */
14517 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
14518 mips_sim_reset (state);
14526 /* The VR4130 pipeline issues aligned pairs of instructions together,
14527 but it stalls the second instruction if it depends on the first.
14528 In order to cut down the amount of logic required, this dependence
14529 check is not based on a full instruction decode. Instead, any non-SPECIAL
14530 instruction is assumed to modify the register specified by bits 20-16
14531 (which is usually the "rt" field).
14533 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
14534 input, so we can end up with a false dependence between the branch
14535 and its delay slot. If this situation occurs in instruction INSN,
14536 try to avoid it by swapping rs and rt. */
14539 vr4130_avoid_branch_rt_conflict (rtx insn)
14543 first = SEQ_BEGIN (insn);
14544 second = SEQ_END (insn);
14546 && NONJUMP_INSN_P (second)
14547 && GET_CODE (PATTERN (first)) == SET
14548 && GET_CODE (SET_DEST (PATTERN (first))) == PC
14549 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
14551 /* Check for the right kind of condition. */
14552 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
14553 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
14554 && REG_P (XEXP (cond, 0))
14555 && REG_P (XEXP (cond, 1))
14556 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
14557 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
14559 /* SECOND mentions the rt register but not the rs register. */
14560 rtx tmp = XEXP (cond, 0);
14561 XEXP (cond, 0) = XEXP (cond, 1);
14562 XEXP (cond, 1) = tmp;
14567 /* Implement -mvr4130-align. Go through each basic block and simulate the
14568 processor pipeline. If we find that a pair of instructions could execute
14569 in parallel, and the first of those instructions is not 8-byte aligned,
14570 insert a nop to make it aligned. */
14573 vr4130_align_insns (void)
14575 struct mips_sim state;
14576 rtx insn, subinsn, last, last2, next;
14581 /* LAST is the last instruction before INSN to have a nonzero length.
14582 LAST2 is the last such instruction before LAST. */
14586 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
14589 mips_sim_init (&state, alloca (state_size ()));
14590 for (insn = get_insns (); insn != 0; insn = next)
14592 unsigned int length;
14594 next = NEXT_INSN (insn);
14596 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
14597 This isn't really related to the alignment pass, but we do it on
14598 the fly to avoid a separate instruction walk. */
14599 vr4130_avoid_branch_rt_conflict (insn);
14601 if (USEFUL_INSN_P (insn))
14602 FOR_EACH_SUBINSN (subinsn, insn)
14604 mips_sim_wait_insn (&state, subinsn);
14606 /* If we want this instruction to issue in parallel with the
14607 previous one, make sure that the previous instruction is
14608 aligned. There are several reasons why this isn't worthwhile
14609 when the second instruction is a call:
14611 - Calls are less likely to be performance critical,
14612 - There's a good chance that the delay slot can execute
14613 in parallel with the call.
14614 - The return address would then be unaligned.
14616 In general, if we're going to insert a nop between instructions
14617 X and Y, it's better to insert it immediately after X. That
14618 way, if the nop makes Y aligned, it will also align any labels
14619 between X and Y. */
14620 if (state.insns_left != state.issue_rate
14621 && !CALL_P (subinsn))
14623 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
14625 /* SUBINSN is the first instruction in INSN and INSN is
14626 aligned. We want to align the previous instruction
14627 instead, so insert a nop between LAST2 and LAST.
14629 Note that LAST could be either a single instruction
14630 or a branch with a delay slot. In the latter case,
14631 LAST, like INSN, is already aligned, but the delay
14632 slot must have some extra delay that stops it from
14633 issuing at the same time as the branch. We therefore
14634 insert a nop before the branch in order to align its
14636 emit_insn_after (gen_nop (), last2);
14639 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
14641 /* SUBINSN is the delay slot of INSN, but INSN is
14642 currently unaligned. Insert a nop between
14643 LAST and INSN to align it. */
14644 emit_insn_after (gen_nop (), last);
14648 mips_sim_issue_insn (&state, subinsn);
14650 mips_sim_finish_insn (&state, insn);
14652 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
14653 length = get_attr_length (insn);
14656 /* If the instruction is an asm statement or multi-instruction
14657 mips.md patern, the length is only an estimate. Insert an
14658 8 byte alignment after it so that the following instructions
14659 can be handled correctly. */
14660 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
14661 && (recog_memoized (insn) < 0 || length >= 8))
14663 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
14664 next = NEXT_INSN (next);
14665 mips_sim_next_cycle (&state);
14668 else if (length & 4)
14669 aligned_p = !aligned_p;
14674 /* See whether INSN is an aligned label. */
14675 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
14681 /* This structure records that the current function has a LO_SUM
14682 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
14683 the largest offset applied to BASE by all such LO_SUMs. */
14684 struct mips_lo_sum_offset {
14686 HOST_WIDE_INT offset;
14689 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
14692 mips_hash_base (rtx base)
14694 int do_not_record_p;
14696 return hash_rtx (base, GET_MODE (base), &do_not_record_p, NULL, false);
14699 /* Hash-table callbacks for mips_lo_sum_offsets. */
14702 mips_lo_sum_offset_hash (const void *entry)
14704 return mips_hash_base (((const struct mips_lo_sum_offset *) entry)->base);
14708 mips_lo_sum_offset_eq (const void *entry, const void *value)
14710 return rtx_equal_p (((const struct mips_lo_sum_offset *) entry)->base,
14711 (const_rtx) value);
14714 /* Look up symbolic constant X in HTAB, which is a hash table of
14715 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
14716 paired with a recorded LO_SUM, otherwise record X in the table. */
14719 mips_lo_sum_offset_lookup (htab_t htab, rtx x, enum insert_option option)
14723 struct mips_lo_sum_offset *entry;
14725 /* Split X into a base and offset. */
14726 split_const (x, &base, &offset);
14727 if (UNSPEC_ADDRESS_P (base))
14728 base = UNSPEC_ADDRESS (base);
14730 /* Look up the base in the hash table. */
14731 slot = htab_find_slot_with_hash (htab, base, mips_hash_base (base), option);
14735 entry = (struct mips_lo_sum_offset *) *slot;
14736 if (option == INSERT)
14740 entry = XNEW (struct mips_lo_sum_offset);
14741 entry->base = base;
14742 entry->offset = INTVAL (offset);
14747 if (INTVAL (offset) > entry->offset)
14748 entry->offset = INTVAL (offset);
14751 return INTVAL (offset) <= entry->offset;
14754 /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table.
14755 Record every LO_SUM in *LOC. */
14758 mips_record_lo_sum (rtx *loc, void *data)
14760 if (GET_CODE (*loc) == LO_SUM)
14761 mips_lo_sum_offset_lookup ((htab_t) data, XEXP (*loc, 1), INSERT);
14765 /* Return true if INSN is a SET of an orphaned high-part relocation.
14766 HTAB is a hash table of mips_lo_sum_offsets that describes all the
14767 LO_SUMs in the current function. */
14770 mips_orphaned_high_part_p (htab_t htab, rtx insn)
14772 enum mips_symbol_type type;
14775 set = single_set (insn);
14778 /* Check for %his. */
14780 if (GET_CODE (x) == HIGH
14781 && absolute_symbolic_operand (XEXP (x, 0), VOIDmode))
14782 return !mips_lo_sum_offset_lookup (htab, XEXP (x, 0), NO_INSERT);
14784 /* Check for local %gots (and %got_pages, which is redundant but OK). */
14785 if (GET_CODE (x) == UNSPEC
14786 && XINT (x, 1) == UNSPEC_LOAD_GOT
14787 && mips_symbolic_constant_p (XVECEXP (x, 0, 1),
14788 SYMBOL_CONTEXT_LEA, &type)
14789 && type == SYMBOL_GOTOFF_PAGE)
14790 return !mips_lo_sum_offset_lookup (htab, XVECEXP (x, 0, 1), NO_INSERT);
14795 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
14796 INSN and a previous instruction, avoid it by inserting nops after
14799 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
14800 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
14801 before using the value of that register. *HILO_DELAY counts the
14802 number of instructions since the last hilo hazard (that is,
14803 the number of instructions since the last MFLO or MFHI).
14805 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
14806 for the next instruction.
14808 LO_REG is an rtx for the LO register, used in dependence checking. */
14811 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
14812 rtx *delayed_reg, rtx lo_reg)
14817 pattern = PATTERN (insn);
14819 /* Do not put the whole function in .set noreorder if it contains
14820 an asm statement. We don't know whether there will be hazards
14821 between the asm statement and the gcc-generated code. */
14822 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
14823 cfun->machine->all_noreorder_p = false;
14825 /* Ignore zero-length instructions (barriers and the like). */
14826 ninsns = get_attr_length (insn) / 4;
14830 /* Work out how many nops are needed. Note that we only care about
14831 registers that are explicitly mentioned in the instruction's pattern.
14832 It doesn't matter that calls use the argument registers or that they
14833 clobber hi and lo. */
14834 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
14835 nops = 2 - *hilo_delay;
14836 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
14841 /* Insert the nops between this instruction and the previous one.
14842 Each new nop takes us further from the last hilo hazard. */
14843 *hilo_delay += nops;
14845 emit_insn_after (gen_hazard_nop (), after);
14847 /* Set up the state for the next instruction. */
14848 *hilo_delay += ninsns;
14850 if (INSN_CODE (insn) >= 0)
14851 switch (get_attr_hazard (insn))
14861 set = single_set (insn);
14863 *delayed_reg = SET_DEST (set);
14868 /* Go through the instruction stream and insert nops where necessary.
14869 Also delete any high-part relocations whose partnering low parts
14870 are now all dead. See if the whole function can then be put into
14871 .set noreorder and .set nomacro. */
14874 mips_reorg_process_insns (void)
14876 rtx insn, last_insn, subinsn, next_insn, lo_reg, delayed_reg;
14880 /* Force all instructions to be split into their final form. */
14881 split_all_insns_noflow ();
14883 /* Recalculate instruction lengths without taking nops into account. */
14884 cfun->machine->ignore_hazard_length_p = true;
14885 shorten_branches (get_insns ());
14887 cfun->machine->all_noreorder_p = true;
14889 /* We don't track MIPS16 PC-relative offsets closely enough to make
14890 a good job of "set .noreorder" code in MIPS16 mode. */
14892 cfun->machine->all_noreorder_p = false;
14894 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
14895 if (!TARGET_EXPLICIT_RELOCS)
14896 cfun->machine->all_noreorder_p = false;
14898 /* Profiled functions can't be all noreorder because the profiler
14899 support uses assembler macros. */
14901 cfun->machine->all_noreorder_p = false;
14903 /* Code compiled with -mfix-vr4120 can't be all noreorder because
14904 we rely on the assembler to work around some errata. */
14905 if (TARGET_FIX_VR4120)
14906 cfun->machine->all_noreorder_p = false;
14908 /* The same is true for -mfix-vr4130 if we might generate MFLO or
14909 MFHI instructions. Note that we avoid using MFLO and MFHI if
14910 the VR4130 MACC and DMACC instructions are available instead;
14911 see the *mfhilo_{si,di}_macc patterns. */
14912 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
14913 cfun->machine->all_noreorder_p = false;
14915 htab = htab_create (37, mips_lo_sum_offset_hash,
14916 mips_lo_sum_offset_eq, free);
14918 /* Make a first pass over the instructions, recording all the LO_SUMs. */
14919 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
14920 FOR_EACH_SUBINSN (subinsn, insn)
14921 if (USEFUL_INSN_P (subinsn))
14922 for_each_rtx (&PATTERN (subinsn), mips_record_lo_sum, htab);
14927 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
14929 /* Make a second pass over the instructions. Delete orphaned
14930 high-part relocations or turn them into NOPs. Avoid hazards
14931 by inserting NOPs. */
14932 for (insn = get_insns (); insn != 0; insn = next_insn)
14934 next_insn = NEXT_INSN (insn);
14935 if (USEFUL_INSN_P (insn))
14937 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
14939 /* If we find an orphaned high-part relocation in a delay
14940 slot, it's easier to turn that instruction into a NOP than
14941 to delete it. The delay slot will be a NOP either way. */
14942 FOR_EACH_SUBINSN (subinsn, insn)
14943 if (INSN_P (subinsn))
14945 if (mips_orphaned_high_part_p (htab, subinsn))
14947 PATTERN (subinsn) = gen_nop ();
14948 INSN_CODE (subinsn) = CODE_FOR_nop;
14950 mips_avoid_hazard (last_insn, subinsn, &hilo_delay,
14951 &delayed_reg, lo_reg);
14957 /* INSN is a single instruction. Delete it if it's an
14958 orphaned high-part relocation. */
14959 if (mips_orphaned_high_part_p (htab, insn))
14960 delete_insn (insn);
14961 /* Also delete cache barriers if the last instruction
14962 was an annulled branch. INSN will not be speculatively
14964 else if (recog_memoized (insn) == CODE_FOR_r10k_cache_barrier
14966 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn)))
14967 delete_insn (insn);
14970 mips_avoid_hazard (last_insn, insn, &hilo_delay,
14971 &delayed_reg, lo_reg);
14978 htab_delete (htab);
14981 /* If we are using a GOT, but have not decided to use a global pointer yet,
14982 see whether we need one to implement long branches. Convert the ghost
14983 global-pointer instructions into real ones if so. */
14986 mips_expand_ghost_gp_insns (void)
14991 /* Quick exit if we already know that we will or won't need a
14993 if (!TARGET_USE_GOT
14994 || cfun->machine->global_pointer == INVALID_REGNUM
14995 || mips_must_initialize_gp_p ())
14998 shorten_branches (get_insns ());
15000 /* Look for a branch that is longer than normal. The normal length for
15001 non-MIPS16 branches is 8, because the length includes the delay slot.
15002 It is 4 for MIPS16, because MIPS16 branches are extended instructions,
15003 but they have no delay slot. */
15004 normal_length = (TARGET_MIPS16 ? 4 : 8);
15005 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
15007 && USEFUL_INSN_P (insn)
15008 && get_attr_length (insn) > normal_length)
15011 if (insn == NULL_RTX)
15014 /* We've now established that we need $gp. */
15015 cfun->machine->must_initialize_gp_p = true;
15016 split_all_insns_noflow ();
15021 /* Subroutine of mips_reorg to manage passes that require DF. */
15024 mips_df_reorg (void)
15026 /* Create def-use chains. */
15027 df_set_flags (DF_EQ_NOTES);
15028 df_chain_add_problem (DF_UD_CHAIN);
15031 if (TARGET_RELAX_PIC_CALLS)
15032 mips_annotate_pic_calls ();
15034 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE)
15035 r10k_insert_cache_barriers ();
15037 df_finish_pass (false);
15040 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
15045 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during
15046 insn splitting in mips16_lay_out_constants, DF insn info is only kept up
15047 to date if the CFG is available. */
15048 if (mips_cfg_in_reorg ())
15049 compute_bb_for_insn ();
15050 mips16_lay_out_constants ();
15051 if (mips_cfg_in_reorg ())
15054 free_bb_for_insn ();
15057 if (optimize > 0 && flag_delayed_branch)
15058 dbr_schedule (get_insns ());
15059 mips_reorg_process_insns ();
15061 && TARGET_EXPLICIT_RELOCS
15063 && TARGET_VR4130_ALIGN)
15064 vr4130_align_insns ();
15065 if (mips_expand_ghost_gp_insns ())
15066 /* The expansion could invalidate some of the VR4130 alignment
15067 optimizations, but this should be an extremely rare case anyhow. */
15068 mips_reorg_process_insns ();
15071 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
15072 in order to avoid duplicating too much logic from elsewhere. */
15075 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
15076 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
15079 rtx this_rtx, temp1, temp2, insn, fnaddr;
15080 bool use_sibcall_p;
15082 /* Pretend to be a post-reload pass while generating rtl. */
15083 reload_completed = 1;
15085 /* Mark the end of the (empty) prologue. */
15086 emit_note (NOTE_INSN_PROLOGUE_END);
15088 /* Determine if we can use a sibcall to call FUNCTION directly. */
15089 fnaddr = XEXP (DECL_RTL (function), 0);
15090 use_sibcall_p = (mips_function_ok_for_sibcall (function, NULL)
15091 && const_call_insn_operand (fnaddr, Pmode));
15093 /* Determine if we need to load FNADDR from the GOT. */
15095 && (mips_got_symbol_type_p
15096 (mips_classify_symbol (fnaddr, SYMBOL_CONTEXT_LEA))))
15098 /* Pick a global pointer. Use a call-clobbered register if
15099 TARGET_CALL_SAVED_GP. */
15100 cfun->machine->global_pointer
15101 = TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM;
15102 cfun->machine->must_initialize_gp_p = true;
15103 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
15105 /* Set up the global pointer for n32 or n64 abicalls. */
15106 mips_emit_loadgp ();
15109 /* We need two temporary registers in some cases. */
15110 temp1 = gen_rtx_REG (Pmode, 2);
15111 temp2 = gen_rtx_REG (Pmode, 3);
15113 /* Find out which register contains the "this" pointer. */
15114 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
15115 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
15117 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST);
15119 /* Add DELTA to THIS_RTX. */
15122 rtx offset = GEN_INT (delta);
15123 if (!SMALL_OPERAND (delta))
15125 mips_emit_move (temp1, offset);
15128 emit_insn (gen_add3_insn (this_rtx, this_rtx, offset));
15131 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
15132 if (vcall_offset != 0)
15136 /* Set TEMP1 to *THIS_RTX. */
15137 mips_emit_move (temp1, gen_rtx_MEM (Pmode, this_rtx));
15139 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
15140 addr = mips_add_offset (temp2, temp1, vcall_offset);
15142 /* Load the offset and add it to THIS_RTX. */
15143 mips_emit_move (temp1, gen_rtx_MEM (Pmode, addr));
15144 emit_insn (gen_add3_insn (this_rtx, this_rtx, temp1));
15147 /* Jump to the target function. Use a sibcall if direct jumps are
15148 allowed, otherwise load the address into a register first. */
15151 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
15152 SIBLING_CALL_P (insn) = 1;
15156 /* This is messy. GAS treats "la $25,foo" as part of a call
15157 sequence and may allow a global "foo" to be lazily bound.
15158 The general move patterns therefore reject this combination.
15160 In this context, lazy binding would actually be OK
15161 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
15162 TARGET_CALL_SAVED_GP; see mips_load_call_address.
15163 We must therefore load the address via a temporary
15164 register if mips_dangerous_for_la25_p.
15166 If we jump to the temporary register rather than $25,
15167 the assembler can use the move insn to fill the jump's
15170 We can use the same technique for MIPS16 code, where $25
15171 is not a valid JR register. */
15172 if (TARGET_USE_PIC_FN_ADDR_REG
15174 && !mips_dangerous_for_la25_p (fnaddr))
15175 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
15176 mips_load_call_address (MIPS_CALL_SIBCALL, temp1, fnaddr);
15178 if (TARGET_USE_PIC_FN_ADDR_REG
15179 && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
15180 mips_emit_move (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
15181 emit_jump_insn (gen_indirect_jump (temp1));
15184 /* Run just enough of rest_of_compilation. This sequence was
15185 "borrowed" from alpha.c. */
15186 insn = get_insns ();
15187 insn_locators_alloc ();
15188 split_all_insns_noflow ();
15189 mips16_lay_out_constants ();
15190 shorten_branches (insn);
15191 final_start_function (insn, file, 1);
15192 final (insn, file, 1);
15193 final_end_function ();
15195 /* Clean up the vars set above. Note that final_end_function resets
15196 the global pointer for us. */
15197 reload_completed = 0;
15200 /* The last argument passed to mips_set_mips16_mode, or negative if the
15201 function hasn't been called yet.
15203 There are two copies of this information. One is saved and restored
15204 by the PCH process while the other is specific to this compiler
15205 invocation. The information calculated by mips_set_mips16_mode
15206 is invalid unless the two variables are the same. */
15207 static int was_mips16_p = -1;
15208 static GTY(()) int was_mips16_pch_p = -1;
15210 /* Set up the target-dependent global state so that it matches the
15211 current function's ISA mode. */
15214 mips_set_mips16_mode (int mips16_p)
15216 if (mips16_p == was_mips16_p
15217 && mips16_p == was_mips16_pch_p)
15220 /* Restore base settings of various flags. */
15221 target_flags = mips_base_target_flags;
15222 flag_schedule_insns = mips_base_schedule_insns;
15223 flag_reorder_blocks_and_partition = mips_base_reorder_blocks_and_partition;
15224 flag_move_loop_invariants = mips_base_move_loop_invariants;
15225 align_loops = mips_base_align_loops;
15226 align_jumps = mips_base_align_jumps;
15227 align_functions = mips_base_align_functions;
15231 /* Switch to MIPS16 mode. */
15232 target_flags |= MASK_MIPS16;
15234 /* Don't run the scheduler before reload, since it tends to
15235 increase register pressure. */
15236 flag_schedule_insns = 0;
15238 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
15239 the whole function to be in a single section. */
15240 flag_reorder_blocks_and_partition = 0;
15242 /* Don't move loop invariants, because it tends to increase
15243 register pressure. It also introduces an extra move in cases
15244 where the constant is the first operand in a two-operand binary
15245 instruction, or when it forms a register argument to a functon
15247 flag_move_loop_invariants = 0;
15249 target_flags |= MASK_EXPLICIT_RELOCS;
15251 /* Experiments suggest we get the best overall section-anchor
15252 results from using the range of an unextended LW or SW. Code
15253 that makes heavy use of byte or short accesses can do better
15254 with ranges of 0...31 and 0...63 respectively, but most code is
15255 sensitive to the range of LW and SW instead. */
15256 targetm.min_anchor_offset = 0;
15257 targetm.max_anchor_offset = 127;
15259 targetm.const_anchor = 0;
15261 /* MIPS16 has no BAL instruction. */
15262 target_flags &= ~MASK_RELAX_PIC_CALLS;
15264 if (flag_pic && !TARGET_OLDABI)
15265 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
15268 sorry ("MIPS16 -mxgot code");
15270 if (TARGET_HARD_FLOAT_ABI && !TARGET_OLDABI)
15271 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
15275 /* Switch to normal (non-MIPS16) mode. */
15276 target_flags &= ~MASK_MIPS16;
15278 /* Provide default values for align_* for 64-bit targets. */
15281 if (align_loops == 0)
15283 if (align_jumps == 0)
15285 if (align_functions == 0)
15286 align_functions = 8;
15289 targetm.min_anchor_offset = -32768;
15290 targetm.max_anchor_offset = 32767;
15292 targetm.const_anchor = 0x8000;
15295 /* (Re)initialize MIPS target internals for new ISA. */
15296 mips_init_relocs ();
15300 if (!mips16_globals)
15301 mips16_globals = save_target_globals ();
15303 restore_target_globals (mips16_globals);
15306 restore_target_globals (&default_target_globals);
15308 was_mips16_p = mips16_p;
15309 was_mips16_pch_p = mips16_p;
15312 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
15313 function should use the MIPS16 ISA and switch modes accordingly. */
15316 mips_set_current_function (tree fndecl)
15318 mips_set_mips16_mode (mips_use_mips16_mode_p (fndecl));
15321 /* Allocate a chunk of memory for per-function machine-dependent data. */
15323 static struct machine_function *
15324 mips_init_machine_status (void)
15326 return ggc_alloc_cleared_machine_function ();
15329 /* Return the processor associated with the given ISA level, or null
15330 if the ISA isn't valid. */
15332 static const struct mips_cpu_info *
15333 mips_cpu_info_from_isa (int isa)
15337 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
15338 if (mips_cpu_info_table[i].isa == isa)
15339 return mips_cpu_info_table + i;
15344 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
15345 with a final "000" replaced by "k". Ignore case.
15347 Note: this function is shared between GCC and GAS. */
15350 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
15352 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
15353 given++, canonical++;
15355 return ((*given == 0 && *canonical == 0)
15356 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
15359 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
15360 CPU name. We've traditionally allowed a lot of variation here.
15362 Note: this function is shared between GCC and GAS. */
15365 mips_matching_cpu_name_p (const char *canonical, const char *given)
15367 /* First see if the name matches exactly, or with a final "000"
15368 turned into "k". */
15369 if (mips_strict_matching_cpu_name_p (canonical, given))
15372 /* If not, try comparing based on numerical designation alone.
15373 See if GIVEN is an unadorned number, or 'r' followed by a number. */
15374 if (TOLOWER (*given) == 'r')
15376 if (!ISDIGIT (*given))
15379 /* Skip over some well-known prefixes in the canonical name,
15380 hoping to find a number there too. */
15381 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
15383 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
15385 else if (TOLOWER (canonical[0]) == 'r')
15388 return mips_strict_matching_cpu_name_p (canonical, given);
15391 /* Return the mips_cpu_info entry for the processor or ISA given
15392 by CPU_STRING. Return null if the string isn't recognized.
15394 A similar function exists in GAS. */
15396 static const struct mips_cpu_info *
15397 mips_parse_cpu (const char *cpu_string)
15402 /* In the past, we allowed upper-case CPU names, but it doesn't
15403 work well with the multilib machinery. */
15404 for (s = cpu_string; *s != 0; s++)
15407 warning (0, "CPU names must be lower case");
15411 /* 'from-abi' selects the most compatible architecture for the given
15412 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
15413 EABIs, we have to decide whether we're using the 32-bit or 64-bit
15415 if (strcasecmp (cpu_string, "from-abi") == 0)
15416 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
15417 : ABI_NEEDS_64BIT_REGS ? 3
15418 : (TARGET_64BIT ? 3 : 1));
15420 /* 'default' has traditionally been a no-op. Probably not very useful. */
15421 if (strcasecmp (cpu_string, "default") == 0)
15424 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
15425 if (mips_matching_cpu_name_p (mips_cpu_info_table[i].name, cpu_string))
15426 return mips_cpu_info_table + i;
15431 /* Set up globals to generate code for the ISA or processor
15432 described by INFO. */
15435 mips_set_architecture (const struct mips_cpu_info *info)
15439 mips_arch_info = info;
15440 mips_arch = info->cpu;
15441 mips_isa = info->isa;
15445 /* Likewise for tuning. */
15448 mips_set_tune (const struct mips_cpu_info *info)
15452 mips_tune_info = info;
15453 mips_tune = info->cpu;
15457 /* Implement TARGET_HANDLE_OPTION. */
15460 mips_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
15465 if (strcmp (arg, "32") == 0)
15467 else if (strcmp (arg, "o64") == 0)
15468 mips_abi = ABI_O64;
15469 else if (strcmp (arg, "n32") == 0)
15470 mips_abi = ABI_N32;
15471 else if (strcmp (arg, "64") == 0)
15473 else if (strcmp (arg, "eabi") == 0)
15474 mips_abi = ABI_EABI;
15481 return mips_parse_cpu (arg) != 0;
15484 mips_isa_option_info = mips_parse_cpu (ACONCAT (("mips", arg, NULL)));
15485 return mips_isa_option_info != 0;
15487 case OPT_mno_flush_func:
15488 mips_cache_flush_func = NULL;
15491 case OPT_mcode_readable_:
15492 if (strcmp (arg, "yes") == 0)
15493 mips_code_readable = CODE_READABLE_YES;
15494 else if (strcmp (arg, "pcrel") == 0)
15495 mips_code_readable = CODE_READABLE_PCREL;
15496 else if (strcmp (arg, "no") == 0)
15497 mips_code_readable = CODE_READABLE_NO;
15502 case OPT_mr10k_cache_barrier_:
15503 if (strcmp (arg, "load-store") == 0)
15504 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_LOAD_STORE;
15505 else if (strcmp (arg, "store") == 0)
15506 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_STORE;
15507 else if (strcmp (arg, "none") == 0)
15508 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE;
15518 /* Implement TARGET_OPTION_OVERRIDE. */
15521 mips_option_override (void)
15523 int i, start, regno, mode;
15525 /* Process flags as though we were generating non-MIPS16 code. */
15526 mips_base_mips16 = TARGET_MIPS16;
15527 target_flags &= ~MASK_MIPS16;
15529 #ifdef SUBTARGET_OVERRIDE_OPTIONS
15530 SUBTARGET_OVERRIDE_OPTIONS;
15533 /* -mno-float overrides -mhard-float and -msoft-float. */
15534 if (TARGET_NO_FLOAT)
15536 target_flags |= MASK_SOFT_FLOAT_ABI;
15537 target_flags_explicit |= MASK_SOFT_FLOAT_ABI;
15540 if (TARGET_FLIP_MIPS16)
15541 TARGET_INTERLINK_MIPS16 = 1;
15543 /* Set the small data limit. */
15544 mips_small_data_threshold = (global_options_set.x_g_switch_value
15546 : MIPS_DEFAULT_GVALUE);
15548 /* The following code determines the architecture and register size.
15549 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
15550 The GAS and GCC code should be kept in sync as much as possible. */
15552 if (mips_arch_string != 0)
15553 mips_set_architecture (mips_parse_cpu (mips_arch_string));
15555 if (mips_isa_option_info != 0)
15557 if (mips_arch_info == 0)
15558 mips_set_architecture (mips_isa_option_info);
15559 else if (mips_arch_info->isa != mips_isa_option_info->isa)
15560 error ("%<-%s%> conflicts with the other architecture options, "
15561 "which specify a %s processor",
15562 mips_isa_option_info->name,
15563 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
15566 if (mips_arch_info == 0)
15568 #ifdef MIPS_CPU_STRING_DEFAULT
15569 mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT));
15571 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
15575 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
15576 error ("%<-march=%s%> is not compatible with the selected ABI",
15577 mips_arch_info->name);
15579 /* Optimize for mips_arch, unless -mtune selects a different processor. */
15580 if (mips_tune_string != 0)
15581 mips_set_tune (mips_parse_cpu (mips_tune_string));
15583 if (mips_tune_info == 0)
15584 mips_set_tune (mips_arch_info);
15586 if ((target_flags_explicit & MASK_64BIT) != 0)
15588 /* The user specified the size of the integer registers. Make sure
15589 it agrees with the ABI and ISA. */
15590 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
15591 error ("%<-mgp64%> used with a 32-bit processor");
15592 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
15593 error ("%<-mgp32%> used with a 64-bit ABI");
15594 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
15595 error ("%<-mgp64%> used with a 32-bit ABI");
15599 /* Infer the integer register size from the ABI and processor.
15600 Restrict ourselves to 32-bit registers if that's all the
15601 processor has, or if the ABI cannot handle 64-bit registers. */
15602 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
15603 target_flags &= ~MASK_64BIT;
15605 target_flags |= MASK_64BIT;
15608 if ((target_flags_explicit & MASK_FLOAT64) != 0)
15610 if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
15611 error ("unsupported combination: %s", "-mfp64 -msingle-float");
15612 else if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
15613 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
15614 else if (!TARGET_64BIT && TARGET_FLOAT64)
15616 if (!ISA_HAS_MXHC1)
15617 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
15618 " the target supports the mfhc1 and mthc1 instructions");
15619 else if (mips_abi != ABI_32)
15620 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
15626 /* -msingle-float selects 32-bit float registers. Otherwise the
15627 float registers should be the same size as the integer ones. */
15628 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
15629 target_flags |= MASK_FLOAT64;
15631 target_flags &= ~MASK_FLOAT64;
15634 /* End of code shared with GAS. */
15636 /* If no -mlong* option was given, infer it from the other options. */
15637 if ((target_flags_explicit & MASK_LONG64) == 0)
15639 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
15640 target_flags |= MASK_LONG64;
15642 target_flags &= ~MASK_LONG64;
15645 if (!TARGET_OLDABI)
15646 flag_pcc_struct_return = 0;
15648 /* Decide which rtx_costs structure to use. */
15650 mips_cost = &mips_rtx_cost_optimize_size;
15652 mips_cost = &mips_rtx_cost_data[mips_tune];
15654 /* If the user hasn't specified a branch cost, use the processor's
15656 if (mips_branch_cost == 0)
15657 mips_branch_cost = mips_cost->branch_cost;
15659 /* If neither -mbranch-likely nor -mno-branch-likely was given
15660 on the command line, set MASK_BRANCHLIKELY based on the target
15661 architecture and tuning flags. Annulled delay slots are a
15662 size win, so we only consider the processor-specific tuning
15663 for !optimize_size. */
15664 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
15666 if (ISA_HAS_BRANCHLIKELY
15668 || (mips_tune_info->tune_flags & PTF_AVOID_BRANCHLIKELY) == 0))
15669 target_flags |= MASK_BRANCHLIKELY;
15671 target_flags &= ~MASK_BRANCHLIKELY;
15673 else if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
15674 warning (0, "the %qs architecture does not support branch-likely"
15675 " instructions", mips_arch_info->name);
15677 /* The effect of -mabicalls isn't defined for the EABI. */
15678 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
15680 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
15681 target_flags &= ~MASK_ABICALLS;
15684 if (TARGET_ABICALLS_PIC2)
15685 /* We need to set flag_pic for executables as well as DSOs
15686 because we may reference symbols that are not defined in
15687 the final executable. (MIPS does not use things like
15688 copy relocs, for example.)
15690 There is a body of code that uses __PIC__ to distinguish
15691 between -mabicalls and -mno-abicalls code. The non-__PIC__
15692 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
15693 long as any indirect jumps use $25. */
15696 /* -mvr4130-align is a "speed over size" optimization: it usually produces
15697 faster code, but at the expense of more nops. Enable it at -O3 and
15699 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
15700 target_flags |= MASK_VR4130_ALIGN;
15702 /* Prefer a call to memcpy over inline code when optimizing for size,
15703 though see MOVE_RATIO in mips.h. */
15704 if (optimize_size && (target_flags_explicit & MASK_MEMCPY) == 0)
15705 target_flags |= MASK_MEMCPY;
15707 /* If we have a nonzero small-data limit, check that the -mgpopt
15708 setting is consistent with the other target flags. */
15709 if (mips_small_data_threshold > 0)
15713 if (!TARGET_EXPLICIT_RELOCS)
15714 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
15716 TARGET_LOCAL_SDATA = false;
15717 TARGET_EXTERN_SDATA = false;
15721 if (TARGET_VXWORKS_RTP)
15722 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
15724 if (TARGET_ABICALLS)
15725 warning (0, "cannot use small-data accesses for %qs",
15730 #ifdef MIPS_TFMODE_FORMAT
15731 REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
15734 /* Make sure that the user didn't turn off paired single support when
15735 MIPS-3D support is requested. */
15737 && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
15738 && !TARGET_PAIRED_SINGLE_FLOAT)
15739 error ("%<-mips3d%> requires %<-mpaired-single%>");
15741 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
15743 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
15745 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
15746 and TARGET_HARD_FLOAT_ABI are both true. */
15747 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT_ABI))
15748 error ("%qs must be used with %qs",
15749 TARGET_MIPS3D ? "-mips3d" : "-mpaired-single",
15750 TARGET_HARD_FLOAT_ABI ? "-mfp64" : "-mhard-float");
15752 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
15754 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_HAS_PAIRED_SINGLE)
15755 warning (0, "the %qs architecture does not support paired-single"
15756 " instructions", mips_arch_info->name);
15758 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
15759 && !TARGET_CACHE_BUILTIN)
15761 error ("%qs requires a target that provides the %qs instruction",
15762 "-mr10k-cache-barrier", "cache");
15763 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE;
15766 /* If TARGET_DSPR2, enable MASK_DSP. */
15768 target_flags |= MASK_DSP;
15770 /* .eh_frame addresses should be the same width as a C pointer.
15771 Most MIPS ABIs support only one pointer size, so the assembler
15772 will usually know exactly how big an .eh_frame address is.
15774 Unfortunately, this is not true of the 64-bit EABI. The ABI was
15775 originally defined to use 64-bit pointers (i.e. it is LP64), and
15776 this is still the default mode. However, we also support an n32-like
15777 ILP32 mode, which is selected by -mlong32. The problem is that the
15778 assembler has traditionally not had an -mlong option, so it has
15779 traditionally not known whether we're using the ILP32 or LP64 form.
15781 As it happens, gas versions up to and including 2.19 use _32-bit_
15782 addresses for EABI64 .cfi_* directives. This is wrong for the
15783 default LP64 mode, so we can't use the directives by default.
15784 Moreover, since gas's current behavior is at odds with gcc's
15785 default behavior, it seems unwise to rely on future versions
15786 of gas behaving the same way. We therefore avoid using .cfi
15787 directives for -mlong32 as well. */
15788 if (mips_abi == ABI_EABI && TARGET_64BIT)
15789 flag_dwarf2_cfi_asm = 0;
15791 /* .cfi_* directives generate a read-only section, so fall back on
15792 manual .eh_frame creation if we need the section to be writable. */
15793 if (TARGET_WRITABLE_EH_FRAME)
15794 flag_dwarf2_cfi_asm = 0;
15796 mips_init_print_operand_punct ();
15798 /* Set up array to map GCC register number to debug register number.
15799 Ignore the special purpose register numbers. */
15801 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
15803 mips_dbx_regno[i] = INVALID_REGNUM;
15804 if (GP_REG_P (i) || FP_REG_P (i) || ALL_COP_REG_P (i))
15805 mips_dwarf_regno[i] = i;
15807 mips_dwarf_regno[i] = INVALID_REGNUM;
15810 start = GP_DBX_FIRST - GP_REG_FIRST;
15811 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
15812 mips_dbx_regno[i] = i + start;
15814 start = FP_DBX_FIRST - FP_REG_FIRST;
15815 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
15816 mips_dbx_regno[i] = i + start;
15818 /* Accumulator debug registers use big-endian ordering. */
15819 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
15820 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
15821 mips_dwarf_regno[HI_REGNUM] = MD_REG_FIRST + 0;
15822 mips_dwarf_regno[LO_REGNUM] = MD_REG_FIRST + 1;
15823 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
15825 mips_dwarf_regno[i + TARGET_LITTLE_ENDIAN] = i;
15826 mips_dwarf_regno[i + TARGET_BIG_ENDIAN] = i + 1;
15829 /* Set up mips_hard_regno_mode_ok. */
15830 for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
15831 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
15832 mips_hard_regno_mode_ok[mode][regno]
15833 = mips_hard_regno_mode_ok_p (regno, (enum machine_mode) mode);
15835 /* Function to allocate machine-dependent function status. */
15836 init_machine_status = &mips_init_machine_status;
15838 /* Default to working around R4000 errata only if the processor
15839 was selected explicitly. */
15840 if ((target_flags_explicit & MASK_FIX_R4000) == 0
15841 && mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
15842 target_flags |= MASK_FIX_R4000;
15844 /* Default to working around R4400 errata only if the processor
15845 was selected explicitly. */
15846 if ((target_flags_explicit & MASK_FIX_R4400) == 0
15847 && mips_matching_cpu_name_p (mips_arch_info->name, "r4400"))
15848 target_flags |= MASK_FIX_R4400;
15850 /* Default to working around R10000 errata only if the processor
15851 was selected explicitly. */
15852 if ((target_flags_explicit & MASK_FIX_R10000) == 0
15853 && mips_matching_cpu_name_p (mips_arch_info->name, "r10000"))
15854 target_flags |= MASK_FIX_R10000;
15856 /* Make sure that branch-likely instructions available when using
15857 -mfix-r10000. The instructions are not available if either:
15859 1. -mno-branch-likely was passed.
15860 2. The selected ISA does not support branch-likely and
15861 the command line does not include -mbranch-likely. */
15862 if (TARGET_FIX_R10000
15863 && ((target_flags_explicit & MASK_BRANCHLIKELY) == 0
15864 ? !ISA_HAS_BRANCHLIKELY
15865 : !TARGET_BRANCHLIKELY))
15866 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
15868 if (TARGET_SYNCI && !ISA_HAS_SYNCI)
15870 warning (0, "the %qs architecture does not support the synci "
15871 "instruction", mips_arch_info->name);
15872 target_flags &= ~MASK_SYNCI;
15875 /* Only optimize PIC indirect calls if they are actually required. */
15876 if (!TARGET_USE_GOT || !TARGET_EXPLICIT_RELOCS)
15877 target_flags &= ~MASK_RELAX_PIC_CALLS;
15879 /* Save base state of options. */
15880 mips_base_target_flags = target_flags;
15881 mips_base_schedule_insns = flag_schedule_insns;
15882 mips_base_reorder_blocks_and_partition = flag_reorder_blocks_and_partition;
15883 mips_base_move_loop_invariants = flag_move_loop_invariants;
15884 mips_base_align_loops = align_loops;
15885 mips_base_align_jumps = align_jumps;
15886 mips_base_align_functions = align_functions;
15888 /* Now select the ISA mode.
15890 Do all CPP-sensitive stuff in non-MIPS16 mode; we'll switch to
15891 MIPS16 mode afterwards if need be. */
15892 mips_set_mips16_mode (false);
15895 /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
15896 static const struct default_options mips_option_optimization_table[] =
15898 { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
15899 { OPT_LEVELS_NONE, 0, NULL, 0 }
15902 /* Swap the register information for registers I and I + 1, which
15903 currently have the wrong endianness. Note that the registers'
15904 fixedness and call-clobberedness might have been set on the
15908 mips_swap_registers (unsigned int i)
15913 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
15914 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
15916 SWAP_INT (fixed_regs[i], fixed_regs[i + 1]);
15917 SWAP_INT (call_used_regs[i], call_used_regs[i + 1]);
15918 SWAP_INT (call_really_used_regs[i], call_really_used_regs[i + 1]);
15919 SWAP_STRING (reg_names[i], reg_names[i + 1]);
15925 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
15928 mips_conditional_register_usage (void)
15933 /* These DSP control register fields are global. */
15934 global_regs[CCDSP_PO_REGNUM] = 1;
15935 global_regs[CCDSP_SC_REGNUM] = 1;
15941 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
15942 fixed_regs[regno] = call_used_regs[regno] = 1;
15944 if (!TARGET_HARD_FLOAT)
15948 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
15949 fixed_regs[regno] = call_used_regs[regno] = 1;
15950 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
15951 fixed_regs[regno] = call_used_regs[regno] = 1;
15953 else if (! ISA_HAS_8CC)
15957 /* We only have a single condition-code register. We implement
15958 this by fixing all the condition-code registers and generating
15959 RTL that refers directly to ST_REG_FIRST. */
15960 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
15961 fixed_regs[regno] = call_used_regs[regno] = 1;
15963 /* In MIPS16 mode, we permit the $t temporary registers to be used
15964 for reload. We prohibit the unused $s registers, since they
15965 are call-saved, and saving them via a MIPS16 register would
15966 probably waste more time than just reloading the value. */
15969 fixed_regs[18] = call_used_regs[18] = 1;
15970 fixed_regs[19] = call_used_regs[19] = 1;
15971 fixed_regs[20] = call_used_regs[20] = 1;
15972 fixed_regs[21] = call_used_regs[21] = 1;
15973 fixed_regs[22] = call_used_regs[22] = 1;
15974 fixed_regs[23] = call_used_regs[23] = 1;
15975 fixed_regs[26] = call_used_regs[26] = 1;
15976 fixed_regs[27] = call_used_regs[27] = 1;
15977 fixed_regs[30] = call_used_regs[30] = 1;
15979 /* $f20-$f23 are call-clobbered for n64. */
15980 if (mips_abi == ABI_64)
15983 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
15984 call_really_used_regs[regno] = call_used_regs[regno] = 1;
15986 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
15988 if (mips_abi == ABI_N32)
15991 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
15992 call_really_used_regs[regno] = call_used_regs[regno] = 1;
15994 /* Make sure that double-register accumulator values are correctly
15995 ordered for the current endianness. */
15996 if (TARGET_LITTLE_ENDIAN)
15998 unsigned int regno;
16000 mips_swap_registers (MD_REG_FIRST);
16001 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno += 2)
16002 mips_swap_registers (regno);
16006 /* Initialize vector TARGET to VALS. */
16009 mips_expand_vector_init (rtx target, rtx vals)
16011 enum machine_mode mode;
16012 enum machine_mode inner;
16013 unsigned int i, n_elts;
16016 mode = GET_MODE (target);
16017 inner = GET_MODE_INNER (mode);
16018 n_elts = GET_MODE_NUNITS (mode);
16020 gcc_assert (VECTOR_MODE_P (mode));
16022 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
16023 for (i = 0; i < n_elts; i++)
16024 emit_move_insn (adjust_address_nv (mem, inner, i * GET_MODE_SIZE (inner)),
16025 XVECEXP (vals, 0, i));
16027 emit_move_insn (target, mem);
16030 /* When generating MIPS16 code, we want to allocate $24 (T_REG) before
16031 other registers for instructions for which it is possible. This
16032 encourages the compiler to use CMP in cases where an XOR would
16033 require some register shuffling. */
16036 mips_order_regs_for_local_alloc (void)
16040 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
16041 reg_alloc_order[i] = i;
16045 /* It really doesn't matter where we put register 0, since it is
16046 a fixed register anyhow. */
16047 reg_alloc_order[0] = 24;
16048 reg_alloc_order[24] = 0;
16052 /* Implement EH_USES. */
16055 mips_eh_uses (unsigned int regno)
16057 if (reload_completed && !TARGET_ABSOLUTE_JUMPS)
16059 /* We need to force certain registers to be live in order to handle
16060 PIC long branches correctly. See mips_must_initialize_gp_p for
16062 if (mips_cfun_has_cprestore_slot_p ())
16064 if (regno == CPRESTORE_SLOT_REGNUM)
16069 if (cfun->machine->global_pointer == regno)
16077 /* Implement EPILOGUE_USES. */
16080 mips_epilogue_uses (unsigned int regno)
16082 /* Say that the epilogue uses the return address register. Note that
16083 in the case of sibcalls, the values "used by the epilogue" are
16084 considered live at the start of the called function. */
16085 if (regno == RETURN_ADDR_REGNUM)
16088 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
16089 See the comment above load_call<mode> for details. */
16090 if (TARGET_USE_GOT && (regno) == GOT_VERSION_REGNUM)
16093 /* An interrupt handler must preserve some registers that are
16094 ordinarily call-clobbered. */
16095 if (cfun->machine->interrupt_handler_p
16096 && mips_interrupt_extra_call_saved_reg_p (regno))
16102 /* A for_each_rtx callback. Stop the search if *X is an AT register. */
16105 mips_at_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
16107 return REG_P (*x) && REGNO (*x) == AT_REGNUM;
16110 /* Return true if INSN needs to be wrapped in ".set noat".
16111 INSN has NOPERANDS operands, stored in OPVEC. */
16114 mips_need_noat_wrapper_p (rtx insn, rtx *opvec, int noperands)
16118 if (recog_memoized (insn) >= 0)
16119 for (i = 0; i < noperands; i++)
16120 if (for_each_rtx (&opvec[i], mips_at_reg_p, NULL))
16125 /* Implement FINAL_PRESCAN_INSN. */
16128 mips_final_prescan_insn (rtx insn, rtx *opvec, int noperands)
16130 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
16131 mips_push_asm_switch (&mips_noat);
16134 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */
16137 mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED, rtx insn,
16138 rtx *opvec, int noperands)
16140 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
16141 mips_pop_asm_switch (&mips_noat);
16144 /* Return the function that is used to expand the <u>mulsidi3 pattern.
16145 EXT_CODE is the code of the extension used. Return NULL if widening
16146 multiplication shouldn't be used. */
16149 mips_mulsidi3_gen_fn (enum rtx_code ext_code)
16153 signed_p = ext_code == SIGN_EXTEND;
16156 /* Don't use widening multiplication with MULT when we have DMUL. Even
16157 with the extension of its input operands DMUL is faster. Note that
16158 the extension is not needed for signed multiplication. In order to
16159 ensure that we always remove the redundant sign-extension in this
16160 case we still expand mulsidi3 for DMUL. */
16162 return signed_p ? gen_mulsidi3_64bit_dmul : NULL;
16163 if (TARGET_FIX_R4000)
16165 return signed_p ? gen_mulsidi3_64bit : gen_umulsidi3_64bit;
16169 if (TARGET_FIX_R4000 && !ISA_HAS_DSP)
16170 return signed_p ? gen_mulsidi3_32bit_r4000 : gen_umulsidi3_32bit_r4000;
16171 return signed_p ? gen_mulsidi3_32bit : gen_umulsidi3_32bit;
16175 /* Return the size in bytes of the trampoline code, padded to
16176 TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target
16177 function address immediately follow. */
16180 mips_trampoline_code_size (void)
16182 if (TARGET_USE_PIC_FN_ADDR_REG)
16184 else if (ptr_mode == DImode)
16186 else if (ISA_HAS_LOAD_DELAY)
16192 /* Implement TARGET_TRAMPOLINE_INIT. */
16195 mips_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
16197 rtx addr, end_addr, high, low, opcode, mem;
16200 HOST_WIDE_INT end_addr_offset, static_chain_offset, target_function_offset;
16202 /* Work out the offsets of the pointers from the start of the
16203 trampoline code. */
16204 end_addr_offset = mips_trampoline_code_size ();
16205 static_chain_offset = end_addr_offset;
16206 target_function_offset = static_chain_offset + GET_MODE_SIZE (ptr_mode);
16208 /* Get pointers to the beginning and end of the code block. */
16209 addr = force_reg (Pmode, XEXP (m_tramp, 0));
16210 end_addr = mips_force_binary (Pmode, PLUS, addr, GEN_INT (end_addr_offset));
16212 #define OP(X) gen_int_mode (X, SImode)
16214 /* Build up the code in TRAMPOLINE. */
16216 if (TARGET_USE_PIC_FN_ADDR_REG)
16218 /* $25 contains the address of the trampoline. Emit code of the form:
16220 l[wd] $1, target_function_offset($25)
16221 l[wd] $static_chain, static_chain_offset($25)
16224 trampoline[i++] = OP (MIPS_LOAD_PTR (AT_REGNUM,
16225 target_function_offset,
16226 PIC_FUNCTION_ADDR_REGNUM));
16227 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
16228 static_chain_offset,
16229 PIC_FUNCTION_ADDR_REGNUM));
16230 trampoline[i++] = OP (MIPS_JR (AT_REGNUM));
16231 trampoline[i++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM, AT_REGNUM));
16233 else if (ptr_mode == DImode)
16235 /* It's too cumbersome to create the full 64-bit address, so let's
16241 1: l[wd] $25, target_function_offset - 12($31)
16242 l[wd] $static_chain, static_chain_offset - 12($31)
16246 where 12 is the offset of "1:" from the start of the code block. */
16247 trampoline[i++] = OP (MIPS_MOVE (AT_REGNUM, RETURN_ADDR_REGNUM));
16248 trampoline[i++] = OP (MIPS_BAL (1));
16249 trampoline[i++] = OP (MIPS_NOP);
16250 trampoline[i++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
16251 target_function_offset - 12,
16252 RETURN_ADDR_REGNUM));
16253 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
16254 static_chain_offset - 12,
16255 RETURN_ADDR_REGNUM));
16256 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
16257 trampoline[i++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM, AT_REGNUM));
16261 /* If the target has load delays, emit:
16263 lui $1, %hi(end_addr)
16264 lw $25, %lo(end_addr + ...)($1)
16265 lw $static_chain, %lo(end_addr + ...)($1)
16271 lui $1, %hi(end_addr)
16272 lw $25, %lo(end_addr + ...)($1)
16274 lw $static_chain, %lo(end_addr + ...)($1). */
16276 /* Split END_ADDR into %hi and %lo values. Trampolines are aligned
16277 to 64 bits, so the %lo value will have the bottom 3 bits clear. */
16278 high = expand_simple_binop (SImode, PLUS, end_addr, GEN_INT (0x8000),
16279 NULL, false, OPTAB_WIDEN);
16280 high = expand_simple_binop (SImode, LSHIFTRT, high, GEN_INT (16),
16281 NULL, false, OPTAB_WIDEN);
16282 low = convert_to_mode (SImode, gen_lowpart (HImode, end_addr), true);
16284 /* Emit the LUI. */
16285 opcode = OP (MIPS_LUI (AT_REGNUM, 0));
16286 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, high,
16287 NULL, false, OPTAB_WIDEN);
16289 /* Emit the load of the target function. */
16290 opcode = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
16291 target_function_offset - end_addr_offset,
16293 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
16294 NULL, false, OPTAB_WIDEN);
16296 /* Emit the JR here, if we can. */
16297 if (!ISA_HAS_LOAD_DELAY)
16298 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
16300 /* Emit the load of the static chain register. */
16301 opcode = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
16302 static_chain_offset - end_addr_offset,
16304 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
16305 NULL, false, OPTAB_WIDEN);
16307 /* Emit the JR, if we couldn't above. */
16308 if (ISA_HAS_LOAD_DELAY)
16310 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
16311 trampoline[i++] = OP (MIPS_NOP);
16317 /* Copy the trampoline code. Leave any padding uninitialized. */
16318 for (j = 0; j < i; j++)
16320 mem = adjust_address (m_tramp, SImode, j * GET_MODE_SIZE (SImode));
16321 mips_emit_move (mem, trampoline[j]);
16324 /* Set up the static chain pointer field. */
16325 mem = adjust_address (m_tramp, ptr_mode, static_chain_offset);
16326 mips_emit_move (mem, chain_value);
16328 /* Set up the target function field. */
16329 mem = adjust_address (m_tramp, ptr_mode, target_function_offset);
16330 mips_emit_move (mem, XEXP (DECL_RTL (fndecl), 0));
16332 /* Flush the code part of the trampoline. */
16333 emit_insn (gen_add3_insn (end_addr, addr, GEN_INT (TRAMPOLINE_SIZE)));
16334 emit_insn (gen_clear_cache (addr, end_addr));
16337 /* Implement FUNCTION_PROFILER. */
16339 void mips_function_profiler (FILE *file)
16342 sorry ("mips16 function profiling");
16343 if (TARGET_LONG_CALLS)
16345 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */
16346 if (Pmode == DImode)
16347 fprintf (file, "\tdla\t%s,_mcount\n", reg_names[3]);
16349 fprintf (file, "\tla\t%s,_mcount\n", reg_names[3]);
16351 mips_push_asm_switch (&mips_noat);
16352 fprintf (file, "\tmove\t%s,%s\t\t# save current return address\n",
16353 reg_names[AT_REGNUM], reg_names[RETURN_ADDR_REGNUM]);
16354 /* _mcount treats $2 as the static chain register. */
16355 if (cfun->static_chain_decl != NULL)
16356 fprintf (file, "\tmove\t%s,%s\n", reg_names[2],
16357 reg_names[STATIC_CHAIN_REGNUM]);
16358 if (TARGET_MCOUNT_RA_ADDRESS)
16360 /* If TARGET_MCOUNT_RA_ADDRESS load $12 with the address of the
16361 ra save location. */
16362 if (cfun->machine->frame.ra_fp_offset == 0)
16363 /* ra not saved, pass zero. */
16364 fprintf (file, "\tmove\t%s,%s\n", reg_names[12], reg_names[0]);
16366 fprintf (file, "\t%s\t%s," HOST_WIDE_INT_PRINT_DEC "(%s)\n",
16367 Pmode == DImode ? "dla" : "la", reg_names[12],
16368 cfun->machine->frame.ra_fp_offset,
16369 reg_names[STACK_POINTER_REGNUM]);
16371 if (!TARGET_NEWABI)
16373 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n",
16374 TARGET_64BIT ? "dsubu" : "subu",
16375 reg_names[STACK_POINTER_REGNUM],
16376 reg_names[STACK_POINTER_REGNUM],
16377 Pmode == DImode ? 16 : 8);
16379 if (TARGET_LONG_CALLS)
16380 fprintf (file, "\tjalr\t%s\n", reg_names[3]);
16382 fprintf (file, "\tjal\t_mcount\n");
16383 mips_pop_asm_switch (&mips_noat);
16384 /* _mcount treats $2 as the static chain register. */
16385 if (cfun->static_chain_decl != NULL)
16386 fprintf (file, "\tmove\t%s,%s\n", reg_names[STATIC_CHAIN_REGNUM],
16390 /* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default
16391 behaviour of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even
16392 when TARGET_LOONGSON_VECTORS is true. */
16394 static unsigned HOST_WIDE_INT
16395 mips_shift_truncation_mask (enum machine_mode mode)
16397 if (TARGET_LOONGSON_VECTORS && VECTOR_MODE_P (mode))
16400 return GET_MODE_BITSIZE (mode) - 1;
16404 /* Initialize the GCC target structure. */
16405 #undef TARGET_ASM_ALIGNED_HI_OP
16406 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
16407 #undef TARGET_ASM_ALIGNED_SI_OP
16408 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
16409 #undef TARGET_ASM_ALIGNED_DI_OP
16410 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
16412 #undef TARGET_OPTION_OVERRIDE
16413 #define TARGET_OPTION_OVERRIDE mips_option_override
16414 #undef TARGET_OPTION_OPTIMIZATION_TABLE
16415 #define TARGET_OPTION_OPTIMIZATION_TABLE mips_option_optimization_table
16417 #undef TARGET_LEGITIMIZE_ADDRESS
16418 #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
16420 #undef TARGET_ASM_FUNCTION_PROLOGUE
16421 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
16422 #undef TARGET_ASM_FUNCTION_EPILOGUE
16423 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
16424 #undef TARGET_ASM_SELECT_RTX_SECTION
16425 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
16426 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
16427 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
16429 #undef TARGET_SCHED_INIT
16430 #define TARGET_SCHED_INIT mips_sched_init
16431 #undef TARGET_SCHED_REORDER
16432 #define TARGET_SCHED_REORDER mips_sched_reorder
16433 #undef TARGET_SCHED_REORDER2
16434 #define TARGET_SCHED_REORDER2 mips_sched_reorder2
16435 #undef TARGET_SCHED_VARIABLE_ISSUE
16436 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
16437 #undef TARGET_SCHED_ADJUST_COST
16438 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
16439 #undef TARGET_SCHED_ISSUE_RATE
16440 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
16441 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
16442 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
16443 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
16444 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
16445 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
16446 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
16447 mips_multipass_dfa_lookahead
16448 #undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
16449 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
16450 mips_small_register_classes_for_mode_p
16452 #undef TARGET_DEFAULT_TARGET_FLAGS
16453 #define TARGET_DEFAULT_TARGET_FLAGS \
16455 | TARGET_CPU_DEFAULT \
16456 | TARGET_ENDIAN_DEFAULT \
16457 | TARGET_FP_EXCEPTIONS_DEFAULT \
16458 | MASK_CHECK_ZERO_DIV \
16460 #undef TARGET_HANDLE_OPTION
16461 #define TARGET_HANDLE_OPTION mips_handle_option
16463 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
16464 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
16466 #undef TARGET_INSERT_ATTRIBUTES
16467 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
16468 #undef TARGET_MERGE_DECL_ATTRIBUTES
16469 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
16470 #undef TARGET_SET_CURRENT_FUNCTION
16471 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
16473 #undef TARGET_VALID_POINTER_MODE
16474 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
16475 #undef TARGET_REGISTER_MOVE_COST
16476 #define TARGET_REGISTER_MOVE_COST mips_register_move_cost
16477 #undef TARGET_MEMORY_MOVE_COST
16478 #define TARGET_MEMORY_MOVE_COST mips_memory_move_cost
16479 #undef TARGET_RTX_COSTS
16480 #define TARGET_RTX_COSTS mips_rtx_costs
16481 #undef TARGET_ADDRESS_COST
16482 #define TARGET_ADDRESS_COST mips_address_cost
16484 #undef TARGET_IN_SMALL_DATA_P
16485 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
16487 #undef TARGET_MACHINE_DEPENDENT_REORG
16488 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
16490 #undef TARGET_ASM_FILE_START
16491 #define TARGET_ASM_FILE_START mips_file_start
16492 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
16493 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
16495 #undef TARGET_INIT_LIBFUNCS
16496 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
16498 #undef TARGET_BUILD_BUILTIN_VA_LIST
16499 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
16500 #undef TARGET_EXPAND_BUILTIN_VA_START
16501 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
16502 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
16503 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
16505 #undef TARGET_PROMOTE_FUNCTION_MODE
16506 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
16507 #undef TARGET_PROMOTE_PROTOTYPES
16508 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
16510 #undef TARGET_RETURN_IN_MEMORY
16511 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
16512 #undef TARGET_RETURN_IN_MSB
16513 #define TARGET_RETURN_IN_MSB mips_return_in_msb
16515 #undef TARGET_ASM_OUTPUT_MI_THUNK
16516 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
16517 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
16518 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
16520 #undef TARGET_PRINT_OPERAND
16521 #define TARGET_PRINT_OPERAND mips_print_operand
16522 #undef TARGET_PRINT_OPERAND_ADDRESS
16523 #define TARGET_PRINT_OPERAND_ADDRESS mips_print_operand_address
16524 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
16525 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mips_print_operand_punct_valid_p
16527 #undef TARGET_SETUP_INCOMING_VARARGS
16528 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
16529 #undef TARGET_STRICT_ARGUMENT_NAMING
16530 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
16531 #undef TARGET_MUST_PASS_IN_STACK
16532 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
16533 #undef TARGET_PASS_BY_REFERENCE
16534 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
16535 #undef TARGET_CALLEE_COPIES
16536 #define TARGET_CALLEE_COPIES mips_callee_copies
16537 #undef TARGET_ARG_PARTIAL_BYTES
16538 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
16539 #undef TARGET_FUNCTION_ARG
16540 #define TARGET_FUNCTION_ARG mips_function_arg
16541 #undef TARGET_FUNCTION_ARG_ADVANCE
16542 #define TARGET_FUNCTION_ARG_ADVANCE mips_function_arg_advance
16543 #undef TARGET_FUNCTION_ARG_BOUNDARY
16544 #define TARGET_FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
16546 #undef TARGET_MODE_REP_EXTENDED
16547 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
16549 #undef TARGET_VECTOR_MODE_SUPPORTED_P
16550 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
16552 #undef TARGET_SCALAR_MODE_SUPPORTED_P
16553 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
16555 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
16556 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE mips_preferred_simd_mode
16558 #undef TARGET_INIT_BUILTINS
16559 #define TARGET_INIT_BUILTINS mips_init_builtins
16560 #undef TARGET_BUILTIN_DECL
16561 #define TARGET_BUILTIN_DECL mips_builtin_decl
16562 #undef TARGET_EXPAND_BUILTIN
16563 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
16565 #undef TARGET_HAVE_TLS
16566 #define TARGET_HAVE_TLS HAVE_AS_TLS
16568 #undef TARGET_CANNOT_FORCE_CONST_MEM
16569 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
16571 #undef TARGET_ENCODE_SECTION_INFO
16572 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
16574 #undef TARGET_ATTRIBUTE_TABLE
16575 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
16576 /* All our function attributes are related to how out-of-line copies should
16577 be compiled or called. They don't in themselves prevent inlining. */
16578 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
16579 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
16581 #undef TARGET_EXTRA_LIVE_ON_ENTRY
16582 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
16584 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
16585 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
16586 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
16587 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
16589 #undef TARGET_COMP_TYPE_ATTRIBUTES
16590 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
16592 #ifdef HAVE_AS_DTPRELWORD
16593 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
16594 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
16596 #undef TARGET_DWARF_REGISTER_SPAN
16597 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
16599 #undef TARGET_IRA_COVER_CLASSES
16600 #define TARGET_IRA_COVER_CLASSES mips_ira_cover_classes
16602 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
16603 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
16605 #undef TARGET_LEGITIMATE_ADDRESS_P
16606 #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p
16608 #undef TARGET_FRAME_POINTER_REQUIRED
16609 #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required
16611 #undef TARGET_CAN_ELIMINATE
16612 #define TARGET_CAN_ELIMINATE mips_can_eliminate
16614 #undef TARGET_CONDITIONAL_REGISTER_USAGE
16615 #define TARGET_CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage
16617 #undef TARGET_TRAMPOLINE_INIT
16618 #define TARGET_TRAMPOLINE_INIT mips_trampoline_init
16620 #undef TARGET_ASM_OUTPUT_SOURCE_FILENAME
16621 #define TARGET_ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
16623 #undef TARGET_SHIFT_TRUNCATION_MASK
16624 #define TARGET_SHIFT_TRUNCATION_MASK mips_shift_truncation_mask
16626 struct gcc_target targetm = TARGET_INITIALIZER;
16628 #include "gt-mips.h"