1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
5 Free Software Foundation, Inc.
6 Contributed by A. Lichnewsky, lich@inria.inria.fr.
7 Changes by Michael Meissner, meissner@osf.org.
8 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
9 Brendan Eich, brendan@microunity.com.
11 This file is part of GCC.
13 GCC is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GCC is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GCC; see the file COPYING3. If not see
25 <http://www.gnu.org/licenses/>. */
29 #include "coretypes.h"
33 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
36 #include "insn-attr.h"
52 #include "target-def.h"
53 #include "langhooks.h"
54 #include "sched-int.h"
57 #include "diagnostic.h"
58 #include "target-globals.h"
61 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
62 #define UNSPEC_ADDRESS_P(X) \
63 (GET_CODE (X) == UNSPEC \
64 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
65 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
67 /* Extract the symbol or label from UNSPEC wrapper X. */
68 #define UNSPEC_ADDRESS(X) \
71 /* Extract the symbol type from UNSPEC wrapper X. */
72 #define UNSPEC_ADDRESS_TYPE(X) \
73 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
75 /* The maximum distance between the top of the stack frame and the
76 value $sp has when we save and restore registers.
78 The value for normal-mode code must be a SMALL_OPERAND and must
79 preserve the maximum stack alignment. We therefore use a value
80 of 0x7ff0 in this case.
82 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
83 up to 0x7f8 bytes and can usually save or restore all the registers
84 that we need to save or restore. (Note that we can only use these
85 instructions for o32, for which the stack alignment is 8 bytes.)
87 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
88 RESTORE are not available. We can then use unextended instructions
89 to save and restore registers, and to allocate and deallocate the top
91 #define MIPS_MAX_FIRST_STACK_STEP \
92 (!TARGET_MIPS16 ? 0x7ff0 \
93 : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
94 : TARGET_64BIT ? 0x100 : 0x400)
96 /* True if INSN is a mips.md pattern or asm statement. */
97 #define USEFUL_INSN_P(INSN) \
98 (NONDEBUG_INSN_P (INSN) \
99 && GET_CODE (PATTERN (INSN)) != USE \
100 && GET_CODE (PATTERN (INSN)) != CLOBBER \
101 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
102 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
104 /* If INSN is a delayed branch sequence, return the first instruction
105 in the sequence, otherwise return INSN itself. */
106 #define SEQ_BEGIN(INSN) \
107 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
108 ? XVECEXP (PATTERN (INSN), 0, 0) \
111 /* Likewise for the last instruction in a delayed branch sequence. */
112 #define SEQ_END(INSN) \
113 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
114 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
117 /* Execute the following loop body with SUBINSN set to each instruction
118 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
119 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
120 for ((SUBINSN) = SEQ_BEGIN (INSN); \
121 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
122 (SUBINSN) = NEXT_INSN (SUBINSN))
124 /* True if bit BIT is set in VALUE. */
125 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
127 /* Return the opcode for a ptr_mode load of the form:
129 l[wd] DEST, OFFSET(BASE). */
130 #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \
131 (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \
136 /* Return the opcode to move register SRC into register DEST. */
137 #define MIPS_MOVE(DEST, SRC) \
138 ((TARGET_64BIT ? 0x2d : 0x21) \
142 /* Return the opcode for:
145 #define MIPS_LUI(DEST, VALUE) \
146 ((0xf << 26) | ((DEST) << 16) | (VALUE))
148 /* Return the opcode to jump to register DEST. */
149 #define MIPS_JR(DEST) \
150 (((DEST) << 21) | 0x8)
152 /* Return the opcode for:
154 bal . + (1 + OFFSET) * 4. */
155 #define MIPS_BAL(OFFSET) \
156 ((0x1 << 26) | (0x11 << 16) | (OFFSET))
158 /* Return the usual opcode for a nop. */
161 /* Classifies an address.
164 A natural register + offset address. The register satisfies
165 mips_valid_base_register_p and the offset is a const_arith_operand.
168 A LO_SUM rtx. The first operand is a valid base register and
169 the second operand is a symbolic address.
172 A signed 16-bit constant address.
175 A constant symbolic address. */
176 enum mips_address_type {
183 /* Macros to create an enumeration identifier for a function prototype. */
184 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
185 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
186 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
187 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
189 /* Classifies the prototype of a built-in function. */
190 enum mips_function_type {
191 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
192 #include "config/mips/mips-ftypes.def"
193 #undef DEF_MIPS_FTYPE
197 /* Specifies how a built-in function should be converted into rtl. */
198 enum mips_builtin_type {
199 /* The function corresponds directly to an .md pattern. The return
200 value is mapped to operand 0 and the arguments are mapped to
201 operands 1 and above. */
204 /* The function corresponds directly to an .md pattern. There is no return
205 value and the arguments are mapped to operands 0 and above. */
206 MIPS_BUILTIN_DIRECT_NO_TARGET,
208 /* The function corresponds to a comparison instruction followed by
209 a mips_cond_move_tf_ps pattern. The first two arguments are the
210 values to compare and the second two arguments are the vector
211 operands for the movt.ps or movf.ps instruction (in assembly order). */
215 /* The function corresponds to a V2SF comparison instruction. Operand 0
216 of this instruction is the result of the comparison, which has mode
217 CCV2 or CCV4. The function arguments are mapped to operands 1 and
218 above. The function's return value is an SImode boolean that is
219 true under the following conditions:
221 MIPS_BUILTIN_CMP_ANY: one of the registers is true
222 MIPS_BUILTIN_CMP_ALL: all of the registers are true
223 MIPS_BUILTIN_CMP_LOWER: the first register is true
224 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
225 MIPS_BUILTIN_CMP_ANY,
226 MIPS_BUILTIN_CMP_ALL,
227 MIPS_BUILTIN_CMP_UPPER,
228 MIPS_BUILTIN_CMP_LOWER,
230 /* As above, but the instruction only sets a single $fcc register. */
231 MIPS_BUILTIN_CMP_SINGLE,
233 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
234 MIPS_BUILTIN_BPOSGE32
237 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
238 #define MIPS_FP_CONDITIONS(MACRO) \
256 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
257 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
258 enum mips_fp_condition {
259 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
262 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
263 #define STRINGIFY(X) #X
264 static const char *const mips_fp_conditions[] = {
265 MIPS_FP_CONDITIONS (STRINGIFY)
268 /* Information about a function's frame layout. */
269 struct GTY(()) mips_frame_info {
270 /* The size of the frame in bytes. */
271 HOST_WIDE_INT total_size;
273 /* The number of bytes allocated to variables. */
274 HOST_WIDE_INT var_size;
276 /* The number of bytes allocated to outgoing function arguments. */
277 HOST_WIDE_INT args_size;
279 /* The number of bytes allocated to the .cprestore slot, or 0 if there
281 HOST_WIDE_INT cprestore_size;
283 /* Bit X is set if the function saves or restores GPR X. */
286 /* Likewise FPR X. */
289 /* Likewise doubleword accumulator X ($acX). */
290 unsigned int acc_mask;
292 /* The number of GPRs, FPRs, doubleword accumulators and COP0
296 unsigned int num_acc;
297 unsigned int num_cop0_regs;
299 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
300 save slots from the top of the frame, or zero if no such slots are
302 HOST_WIDE_INT gp_save_offset;
303 HOST_WIDE_INT fp_save_offset;
304 HOST_WIDE_INT acc_save_offset;
305 HOST_WIDE_INT cop0_save_offset;
307 /* Likewise, but giving offsets from the bottom of the frame. */
308 HOST_WIDE_INT gp_sp_offset;
309 HOST_WIDE_INT fp_sp_offset;
310 HOST_WIDE_INT acc_sp_offset;
311 HOST_WIDE_INT cop0_sp_offset;
313 /* Similar, but the value passed to _mcount. */
314 HOST_WIDE_INT ra_fp_offset;
316 /* The offset of arg_pointer_rtx from the bottom of the frame. */
317 HOST_WIDE_INT arg_pointer_offset;
319 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
320 HOST_WIDE_INT hard_frame_pointer_offset;
323 struct GTY(()) machine_function {
324 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
325 rtx mips16_gp_pseudo_rtx;
327 /* The number of extra stack bytes taken up by register varargs.
328 This area is allocated by the callee at the very top of the frame. */
331 /* The current frame information, calculated by mips_compute_frame_info. */
332 struct mips_frame_info frame;
334 /* The register to use as the function's global pointer, or INVALID_REGNUM
335 if the function doesn't need one. */
336 unsigned int global_pointer;
338 /* How many instructions it takes to load a label into $AT, or 0 if
339 this property hasn't yet been calculated. */
340 unsigned int load_label_num_insns;
342 /* True if mips_adjust_insn_length should ignore an instruction's
344 bool ignore_hazard_length_p;
346 /* True if the whole function is suitable for .set noreorder and
348 bool all_noreorder_p;
350 /* True if the function has "inflexible" and "flexible" references
351 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
352 and mips_cfun_has_flexible_gp_ref_p for details. */
353 bool has_inflexible_gp_insn_p;
354 bool has_flexible_gp_insn_p;
356 /* True if the function's prologue must load the global pointer
357 value into pic_offset_table_rtx and store the same value in
358 the function's cprestore slot (if any). Even if this value
359 is currently false, we may decide to set it to true later;
360 see mips_must_initialize_gp_p () for details. */
361 bool must_initialize_gp_p;
363 /* True if the current function must restore $gp after any potential
364 clobber. This value is only meaningful during the first post-epilogue
365 split_insns pass; see mips_must_initialize_gp_p () for details. */
366 bool must_restore_gp_when_clobbered_p;
368 /* True if this is an interrupt handler. */
369 bool interrupt_handler_p;
371 /* True if this is an interrupt handler that uses shadow registers. */
372 bool use_shadow_register_set_p;
374 /* True if this is an interrupt handler that should keep interrupts
376 bool keep_interrupts_masked_p;
378 /* True if this is an interrupt handler that should use DERET
380 bool use_debug_exception_return_p;
383 /* Information about a single argument. */
384 struct mips_arg_info {
385 /* True if the argument is passed in a floating-point register, or
386 would have been if we hadn't run out of registers. */
389 /* The number of words passed in registers, rounded up. */
390 unsigned int reg_words;
392 /* For EABI, the offset of the first register from GP_ARG_FIRST or
393 FP_ARG_FIRST. For other ABIs, the offset of the first register from
394 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
395 comment for details).
397 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
399 unsigned int reg_offset;
401 /* The number of words that must be passed on the stack, rounded up. */
402 unsigned int stack_words;
404 /* The offset from the start of the stack overflow area of the argument's
405 first stack word. Only meaningful when STACK_WORDS is nonzero. */
406 unsigned int stack_offset;
409 /* Information about an address described by mips_address_type.
415 REG is the base register and OFFSET is the constant offset.
418 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
419 is the type of symbol it references.
422 SYMBOL_TYPE is the type of symbol that the address references. */
423 struct mips_address_info {
424 enum mips_address_type type;
427 enum mips_symbol_type symbol_type;
430 /* One stage in a constant building sequence. These sequences have
434 A = A CODE[1] VALUE[1]
435 A = A CODE[2] VALUE[2]
438 where A is an accumulator, each CODE[i] is a binary rtl operation
439 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
440 struct mips_integer_op {
442 unsigned HOST_WIDE_INT value;
445 /* The largest number of operations needed to load an integer constant.
446 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
447 When the lowest bit is clear, we can try, but reject a sequence with
448 an extra SLL at the end. */
449 #define MIPS_MAX_INTEGER_OPS 7
451 /* Information about a MIPS16e SAVE or RESTORE instruction. */
452 struct mips16e_save_restore_info {
453 /* The number of argument registers saved by a SAVE instruction.
454 0 for RESTORE instructions. */
457 /* Bit X is set if the instruction saves or restores GPR X. */
460 /* The total number of bytes to allocate. */
464 /* Costs of various operations on the different architectures. */
466 struct mips_rtx_cost_data
468 unsigned short fp_add;
469 unsigned short fp_mult_sf;
470 unsigned short fp_mult_df;
471 unsigned short fp_div_sf;
472 unsigned short fp_div_df;
473 unsigned short int_mult_si;
474 unsigned short int_mult_di;
475 unsigned short int_div_si;
476 unsigned short int_div_di;
477 unsigned short branch_cost;
478 unsigned short memory_latency;
481 /* Global variables for machine-dependent things. */
483 /* The -G setting, or the configuration's default small-data limit if
484 no -G option is given. */
485 static unsigned int mips_small_data_threshold;
487 /* The number of file directives written by mips_output_filename. */
488 int num_source_filenames;
490 /* The name that appeared in the last .file directive written by
491 mips_output_filename, or "" if mips_output_filename hasn't
492 written anything yet. */
493 const char *current_function_file = "";
495 /* Arrays that map GCC register numbers to debugger register numbers. */
496 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
497 int mips_dwarf_regno[FIRST_PSEUDO_REGISTER];
499 /* Information about the current function's epilogue, used only while
502 /* A list of queued REG_CFA_RESTORE notes. */
505 /* The CFA is currently defined as CFA_REG + CFA_OFFSET. */
507 HOST_WIDE_INT cfa_offset;
509 /* The offset of the CFA from the stack pointer while restoring
511 HOST_WIDE_INT cfa_restore_sp_offset;
514 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
515 struct mips_asm_switch mips_noreorder = { "reorder", 0 };
516 struct mips_asm_switch mips_nomacro = { "macro", 0 };
517 struct mips_asm_switch mips_noat = { "at", 0 };
519 /* True if we're writing out a branch-likely instruction rather than a
521 static bool mips_branch_likely;
523 /* The current instruction-set architecture. */
524 enum processor mips_arch;
525 const struct mips_cpu_info *mips_arch_info;
527 /* The processor that we should tune the code for. */
528 enum processor mips_tune;
529 const struct mips_cpu_info *mips_tune_info;
531 /* The ISA level associated with mips_arch. */
534 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
535 static const struct mips_cpu_info *mips_isa_option_info;
537 /* Which cost information to use. */
538 static const struct mips_rtx_cost_data *mips_cost;
540 /* The ambient target flags, excluding MASK_MIPS16. */
541 static int mips_base_target_flags;
543 /* True if MIPS16 is the default mode. */
544 bool mips_base_mips16;
546 /* The ambient values of other global variables. */
547 static int mips_base_schedule_insns; /* flag_schedule_insns */
548 static int mips_base_reorder_blocks_and_partition; /* flag_reorder... */
549 static int mips_base_move_loop_invariants; /* flag_move_loop_invariants */
550 static int mips_base_align_loops; /* align_loops */
551 static int mips_base_align_jumps; /* align_jumps */
552 static int mips_base_align_functions; /* align_functions */
554 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
555 bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
557 /* Index C is true if character C is a valid PRINT_OPERAND punctation
559 static bool mips_print_operand_punct[256];
561 static GTY (()) int mips_output_filename_first_time = 1;
563 /* mips_split_p[X] is true if symbols of type X can be split by
564 mips_split_symbol. */
565 bool mips_split_p[NUM_SYMBOL_TYPES];
567 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
568 can be split by mips_split_symbol. */
569 bool mips_split_hi_p[NUM_SYMBOL_TYPES];
571 /* mips_use_pcrel_pool_p[X] is true if symbols of type X should be
572 forced into a PC-relative constant pool. */
573 bool mips_use_pcrel_pool_p[NUM_SYMBOL_TYPES];
575 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
576 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
577 if they are matched by a special .md file pattern. */
578 const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
580 /* Likewise for HIGHs. */
581 const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
583 /* Target state for MIPS16. */
584 struct target_globals *mips16_globals;
586 /* Cached value of can_issue_more. This is cached in mips_variable_issue hook
587 and returned from mips_sched_reorder2. */
588 static int cached_can_issue_more;
590 /* True if the output uses __mips16_rdhwr. */
591 static bool mips_need_mips16_rdhwr_p;
593 /* Index R is the smallest register class that contains register R. */
594 const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = {
595 LEA_REGS, LEA_REGS, M16_REGS, V1_REG,
596 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
597 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
598 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
599 M16_REGS, M16_REGS, LEA_REGS, LEA_REGS,
600 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
601 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
602 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
603 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
604 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
605 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
606 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
607 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
608 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
609 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
610 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
611 MD0_REG, MD1_REG, NO_REGS, ST_REGS,
612 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
613 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
614 NO_REGS, FRAME_REGS, FRAME_REGS, NO_REGS,
615 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
616 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
617 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
618 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
619 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
620 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
621 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
622 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
623 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
624 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
625 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
626 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
627 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
628 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
629 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
630 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
631 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
632 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
633 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
634 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
635 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
636 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
637 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
638 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
639 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
640 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
641 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
644 /* The value of TARGET_ATTRIBUTE_TABLE. */
645 static const struct attribute_spec mips_attribute_table[] = {
646 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
648 { "long_call", 0, 0, false, true, true, NULL, false },
649 { "far", 0, 0, false, true, true, NULL, false },
650 { "near", 0, 0, false, true, true, NULL, false },
651 /* We would really like to treat "mips16" and "nomips16" as type
652 attributes, but GCC doesn't provide the hooks we need to support
653 the right conversion rules. As declaration attributes, they affect
654 code generation but don't carry other semantics. */
655 { "mips16", 0, 0, true, false, false, NULL, false },
656 { "nomips16", 0, 0, true, false, false, NULL, false },
657 /* Allow functions to be specified as interrupt handlers */
658 { "interrupt", 0, 0, false, true, true, NULL, false },
659 { "use_shadow_register_set", 0, 0, false, true, true, NULL, false },
660 { "keep_interrupts_masked", 0, 0, false, true, true, NULL, false },
661 { "use_debug_exception_return", 0, 0, false, true, true, NULL, false },
662 { NULL, 0, 0, false, false, false, NULL, false }
665 /* A table describing all the processors GCC knows about; see
666 mips-cpus.def for details. */
667 static const struct mips_cpu_info mips_cpu_info_table[] = {
668 #define MIPS_CPU(NAME, CPU, ISA, FLAGS) \
669 { NAME, CPU, ISA, FLAGS },
670 #include "mips-cpus.def"
674 /* Default costs. If these are used for a processor we should look
675 up the actual costs. */
676 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
677 COSTS_N_INSNS (7), /* fp_mult_sf */ \
678 COSTS_N_INSNS (8), /* fp_mult_df */ \
679 COSTS_N_INSNS (23), /* fp_div_sf */ \
680 COSTS_N_INSNS (36), /* fp_div_df */ \
681 COSTS_N_INSNS (10), /* int_mult_si */ \
682 COSTS_N_INSNS (10), /* int_mult_di */ \
683 COSTS_N_INSNS (69), /* int_div_si */ \
684 COSTS_N_INSNS (69), /* int_div_di */ \
685 2, /* branch_cost */ \
686 4 /* memory_latency */
688 /* Floating-point costs for processors without an FPU. Just assume that
689 all floating-point libcalls are very expensive. */
690 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
691 COSTS_N_INSNS (256), /* fp_mult_sf */ \
692 COSTS_N_INSNS (256), /* fp_mult_df */ \
693 COSTS_N_INSNS (256), /* fp_div_sf */ \
694 COSTS_N_INSNS (256) /* fp_div_df */
696 /* Costs to use when optimizing for size. */
697 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size = {
698 COSTS_N_INSNS (1), /* fp_add */
699 COSTS_N_INSNS (1), /* fp_mult_sf */
700 COSTS_N_INSNS (1), /* fp_mult_df */
701 COSTS_N_INSNS (1), /* fp_div_sf */
702 COSTS_N_INSNS (1), /* fp_div_df */
703 COSTS_N_INSNS (1), /* int_mult_si */
704 COSTS_N_INSNS (1), /* int_mult_di */
705 COSTS_N_INSNS (1), /* int_div_si */
706 COSTS_N_INSNS (1), /* int_div_di */
708 4 /* memory_latency */
711 /* Costs to use when optimizing for speed, indexed by processor. */
712 static const struct mips_rtx_cost_data
713 mips_rtx_cost_data[NUM_PROCESSOR_VALUES] = {
715 COSTS_N_INSNS (2), /* fp_add */
716 COSTS_N_INSNS (4), /* fp_mult_sf */
717 COSTS_N_INSNS (5), /* fp_mult_df */
718 COSTS_N_INSNS (12), /* fp_div_sf */
719 COSTS_N_INSNS (19), /* fp_div_df */
720 COSTS_N_INSNS (12), /* int_mult_si */
721 COSTS_N_INSNS (12), /* int_mult_di */
722 COSTS_N_INSNS (35), /* int_div_si */
723 COSTS_N_INSNS (35), /* int_div_di */
725 4 /* memory_latency */
729 COSTS_N_INSNS (6), /* int_mult_si */
730 COSTS_N_INSNS (6), /* int_mult_di */
731 COSTS_N_INSNS (36), /* int_div_si */
732 COSTS_N_INSNS (36), /* int_div_di */
734 4 /* memory_latency */
738 COSTS_N_INSNS (36), /* int_mult_si */
739 COSTS_N_INSNS (36), /* int_mult_di */
740 COSTS_N_INSNS (37), /* int_div_si */
741 COSTS_N_INSNS (37), /* int_div_di */
743 4 /* memory_latency */
747 COSTS_N_INSNS (4), /* int_mult_si */
748 COSTS_N_INSNS (11), /* int_mult_di */
749 COSTS_N_INSNS (36), /* int_div_si */
750 COSTS_N_INSNS (68), /* int_div_di */
752 4 /* memory_latency */
755 COSTS_N_INSNS (4), /* fp_add */
756 COSTS_N_INSNS (4), /* fp_mult_sf */
757 COSTS_N_INSNS (5), /* fp_mult_df */
758 COSTS_N_INSNS (17), /* fp_div_sf */
759 COSTS_N_INSNS (32), /* fp_div_df */
760 COSTS_N_INSNS (4), /* int_mult_si */
761 COSTS_N_INSNS (11), /* int_mult_di */
762 COSTS_N_INSNS (36), /* int_div_si */
763 COSTS_N_INSNS (68), /* int_div_di */
765 4 /* memory_latency */
768 COSTS_N_INSNS (4), /* fp_add */
769 COSTS_N_INSNS (4), /* fp_mult_sf */
770 COSTS_N_INSNS (5), /* fp_mult_df */
771 COSTS_N_INSNS (17), /* fp_div_sf */
772 COSTS_N_INSNS (32), /* fp_div_df */
773 COSTS_N_INSNS (4), /* int_mult_si */
774 COSTS_N_INSNS (7), /* int_mult_di */
775 COSTS_N_INSNS (42), /* int_div_si */
776 COSTS_N_INSNS (72), /* int_div_di */
778 4 /* memory_latency */
782 COSTS_N_INSNS (5), /* int_mult_si */
783 COSTS_N_INSNS (5), /* int_mult_di */
784 COSTS_N_INSNS (41), /* int_div_si */
785 COSTS_N_INSNS (41), /* int_div_di */
787 4 /* memory_latency */
790 COSTS_N_INSNS (8), /* fp_add */
791 COSTS_N_INSNS (8), /* fp_mult_sf */
792 COSTS_N_INSNS (10), /* fp_mult_df */
793 COSTS_N_INSNS (34), /* fp_div_sf */
794 COSTS_N_INSNS (64), /* fp_div_df */
795 COSTS_N_INSNS (5), /* int_mult_si */
796 COSTS_N_INSNS (5), /* int_mult_di */
797 COSTS_N_INSNS (41), /* int_div_si */
798 COSTS_N_INSNS (41), /* int_div_di */
800 4 /* memory_latency */
803 COSTS_N_INSNS (4), /* fp_add */
804 COSTS_N_INSNS (4), /* fp_mult_sf */
805 COSTS_N_INSNS (5), /* fp_mult_df */
806 COSTS_N_INSNS (17), /* fp_div_sf */
807 COSTS_N_INSNS (32), /* fp_div_df */
808 COSTS_N_INSNS (5), /* int_mult_si */
809 COSTS_N_INSNS (5), /* int_mult_di */
810 COSTS_N_INSNS (41), /* int_div_si */
811 COSTS_N_INSNS (41), /* int_div_di */
813 4 /* memory_latency */
817 COSTS_N_INSNS (5), /* int_mult_si */
818 COSTS_N_INSNS (5), /* int_mult_di */
819 COSTS_N_INSNS (41), /* int_div_si */
820 COSTS_N_INSNS (41), /* int_div_di */
822 4 /* memory_latency */
825 COSTS_N_INSNS (8), /* fp_add */
826 COSTS_N_INSNS (8), /* fp_mult_sf */
827 COSTS_N_INSNS (10), /* fp_mult_df */
828 COSTS_N_INSNS (34), /* fp_div_sf */
829 COSTS_N_INSNS (64), /* fp_div_df */
830 COSTS_N_INSNS (5), /* int_mult_si */
831 COSTS_N_INSNS (5), /* int_mult_di */
832 COSTS_N_INSNS (41), /* int_div_si */
833 COSTS_N_INSNS (41), /* int_div_di */
835 4 /* memory_latency */
838 COSTS_N_INSNS (4), /* fp_add */
839 COSTS_N_INSNS (4), /* fp_mult_sf */
840 COSTS_N_INSNS (5), /* fp_mult_df */
841 COSTS_N_INSNS (17), /* fp_div_sf */
842 COSTS_N_INSNS (32), /* fp_div_df */
843 COSTS_N_INSNS (5), /* int_mult_si */
844 COSTS_N_INSNS (5), /* int_mult_di */
845 COSTS_N_INSNS (41), /* int_div_si */
846 COSTS_N_INSNS (41), /* int_div_di */
848 4 /* memory_latency */
851 COSTS_N_INSNS (6), /* fp_add */
852 COSTS_N_INSNS (6), /* fp_mult_sf */
853 COSTS_N_INSNS (7), /* fp_mult_df */
854 COSTS_N_INSNS (25), /* fp_div_sf */
855 COSTS_N_INSNS (48), /* fp_div_df */
856 COSTS_N_INSNS (5), /* int_mult_si */
857 COSTS_N_INSNS (5), /* int_mult_di */
858 COSTS_N_INSNS (41), /* int_div_si */
859 COSTS_N_INSNS (41), /* int_div_di */
861 4 /* memory_latency */
878 COSTS_N_INSNS (5), /* int_mult_si */
879 COSTS_N_INSNS (5), /* int_mult_di */
880 COSTS_N_INSNS (72), /* int_div_si */
881 COSTS_N_INSNS (72), /* int_div_di */
883 4 /* memory_latency */
888 COSTS_N_INSNS (6), /* int_mult_si */
889 COSTS_N_INSNS (6), /* int_mult_di */
890 COSTS_N_INSNS (18), /* int_div_si */
891 COSTS_N_INSNS (35), /* int_div_di */
893 4 /* memory_latency */
896 COSTS_N_INSNS (2), /* fp_add */
897 COSTS_N_INSNS (4), /* fp_mult_sf */
898 COSTS_N_INSNS (5), /* fp_mult_df */
899 COSTS_N_INSNS (12), /* fp_div_sf */
900 COSTS_N_INSNS (19), /* fp_div_df */
901 COSTS_N_INSNS (2), /* int_mult_si */
902 COSTS_N_INSNS (2), /* int_mult_di */
903 COSTS_N_INSNS (35), /* int_div_si */
904 COSTS_N_INSNS (35), /* int_div_di */
906 4 /* memory_latency */
909 COSTS_N_INSNS (3), /* fp_add */
910 COSTS_N_INSNS (5), /* fp_mult_sf */
911 COSTS_N_INSNS (6), /* fp_mult_df */
912 COSTS_N_INSNS (15), /* fp_div_sf */
913 COSTS_N_INSNS (16), /* fp_div_df */
914 COSTS_N_INSNS (17), /* int_mult_si */
915 COSTS_N_INSNS (17), /* int_mult_di */
916 COSTS_N_INSNS (38), /* int_div_si */
917 COSTS_N_INSNS (38), /* int_div_di */
919 6 /* memory_latency */
922 COSTS_N_INSNS (6), /* fp_add */
923 COSTS_N_INSNS (7), /* fp_mult_sf */
924 COSTS_N_INSNS (8), /* fp_mult_df */
925 COSTS_N_INSNS (23), /* fp_div_sf */
926 COSTS_N_INSNS (36), /* fp_div_df */
927 COSTS_N_INSNS (10), /* int_mult_si */
928 COSTS_N_INSNS (10), /* int_mult_di */
929 COSTS_N_INSNS (69), /* int_div_si */
930 COSTS_N_INSNS (69), /* int_div_di */
932 6 /* memory_latency */
944 /* The only costs that appear to be updated here are
945 integer multiplication. */
947 COSTS_N_INSNS (4), /* int_mult_si */
948 COSTS_N_INSNS (6), /* int_mult_di */
949 COSTS_N_INSNS (69), /* int_div_si */
950 COSTS_N_INSNS (69), /* int_div_di */
952 4 /* memory_latency */
967 COSTS_N_INSNS (6), /* fp_add */
968 COSTS_N_INSNS (4), /* fp_mult_sf */
969 COSTS_N_INSNS (5), /* fp_mult_df */
970 COSTS_N_INSNS (23), /* fp_div_sf */
971 COSTS_N_INSNS (36), /* fp_div_df */
972 COSTS_N_INSNS (5), /* int_mult_si */
973 COSTS_N_INSNS (5), /* int_mult_di */
974 COSTS_N_INSNS (36), /* int_div_si */
975 COSTS_N_INSNS (36), /* int_div_di */
977 4 /* memory_latency */
980 COSTS_N_INSNS (6), /* fp_add */
981 COSTS_N_INSNS (5), /* fp_mult_sf */
982 COSTS_N_INSNS (6), /* fp_mult_df */
983 COSTS_N_INSNS (30), /* fp_div_sf */
984 COSTS_N_INSNS (59), /* fp_div_df */
985 COSTS_N_INSNS (3), /* int_mult_si */
986 COSTS_N_INSNS (4), /* int_mult_di */
987 COSTS_N_INSNS (42), /* int_div_si */
988 COSTS_N_INSNS (74), /* int_div_di */
990 4 /* memory_latency */
993 COSTS_N_INSNS (6), /* fp_add */
994 COSTS_N_INSNS (5), /* fp_mult_sf */
995 COSTS_N_INSNS (6), /* fp_mult_df */
996 COSTS_N_INSNS (30), /* fp_div_sf */
997 COSTS_N_INSNS (59), /* fp_div_df */
998 COSTS_N_INSNS (5), /* int_mult_si */
999 COSTS_N_INSNS (9), /* int_mult_di */
1000 COSTS_N_INSNS (42), /* int_div_si */
1001 COSTS_N_INSNS (74), /* int_div_di */
1002 1, /* branch_cost */
1003 4 /* memory_latency */
1006 /* The only costs that are changed here are
1007 integer multiplication. */
1008 COSTS_N_INSNS (6), /* fp_add */
1009 COSTS_N_INSNS (7), /* fp_mult_sf */
1010 COSTS_N_INSNS (8), /* fp_mult_df */
1011 COSTS_N_INSNS (23), /* fp_div_sf */
1012 COSTS_N_INSNS (36), /* fp_div_df */
1013 COSTS_N_INSNS (5), /* int_mult_si */
1014 COSTS_N_INSNS (9), /* int_mult_di */
1015 COSTS_N_INSNS (69), /* int_div_si */
1016 COSTS_N_INSNS (69), /* int_div_di */
1017 1, /* branch_cost */
1018 4 /* memory_latency */
1024 /* The only costs that are changed here are
1025 integer multiplication. */
1026 COSTS_N_INSNS (6), /* fp_add */
1027 COSTS_N_INSNS (7), /* fp_mult_sf */
1028 COSTS_N_INSNS (8), /* fp_mult_df */
1029 COSTS_N_INSNS (23), /* fp_div_sf */
1030 COSTS_N_INSNS (36), /* fp_div_df */
1031 COSTS_N_INSNS (3), /* int_mult_si */
1032 COSTS_N_INSNS (8), /* int_mult_di */
1033 COSTS_N_INSNS (69), /* int_div_si */
1034 COSTS_N_INSNS (69), /* int_div_di */
1035 1, /* branch_cost */
1036 4 /* memory_latency */
1039 COSTS_N_INSNS (2), /* fp_add */
1040 COSTS_N_INSNS (2), /* fp_mult_sf */
1041 COSTS_N_INSNS (2), /* fp_mult_df */
1042 COSTS_N_INSNS (12), /* fp_div_sf */
1043 COSTS_N_INSNS (19), /* fp_div_df */
1044 COSTS_N_INSNS (5), /* int_mult_si */
1045 COSTS_N_INSNS (9), /* int_mult_di */
1046 COSTS_N_INSNS (34), /* int_div_si */
1047 COSTS_N_INSNS (66), /* int_div_di */
1048 1, /* branch_cost */
1049 4 /* memory_latency */
1052 /* These costs are the same as the SB-1A below. */
1053 COSTS_N_INSNS (4), /* fp_add */
1054 COSTS_N_INSNS (4), /* fp_mult_sf */
1055 COSTS_N_INSNS (4), /* fp_mult_df */
1056 COSTS_N_INSNS (24), /* fp_div_sf */
1057 COSTS_N_INSNS (32), /* fp_div_df */
1058 COSTS_N_INSNS (3), /* int_mult_si */
1059 COSTS_N_INSNS (4), /* int_mult_di */
1060 COSTS_N_INSNS (36), /* int_div_si */
1061 COSTS_N_INSNS (68), /* int_div_di */
1062 1, /* branch_cost */
1063 4 /* memory_latency */
1066 /* These costs are the same as the SB-1 above. */
1067 COSTS_N_INSNS (4), /* fp_add */
1068 COSTS_N_INSNS (4), /* fp_mult_sf */
1069 COSTS_N_INSNS (4), /* fp_mult_df */
1070 COSTS_N_INSNS (24), /* fp_div_sf */
1071 COSTS_N_INSNS (32), /* fp_div_df */
1072 COSTS_N_INSNS (3), /* int_mult_si */
1073 COSTS_N_INSNS (4), /* int_mult_di */
1074 COSTS_N_INSNS (36), /* int_div_si */
1075 COSTS_N_INSNS (68), /* int_div_di */
1076 1, /* branch_cost */
1077 4 /* memory_latency */
1084 COSTS_N_INSNS (8), /* int_mult_si */
1085 COSTS_N_INSNS (8), /* int_mult_di */
1086 COSTS_N_INSNS (72), /* int_div_si */
1087 COSTS_N_INSNS (72), /* int_div_di */
1088 1, /* branch_cost */
1089 4 /* memory_latency */
1092 /* These costs are the same as 5KF above. */
1093 COSTS_N_INSNS (4), /* fp_add */
1094 COSTS_N_INSNS (4), /* fp_mult_sf */
1095 COSTS_N_INSNS (5), /* fp_mult_df */
1096 COSTS_N_INSNS (17), /* fp_div_sf */
1097 COSTS_N_INSNS (32), /* fp_div_df */
1098 COSTS_N_INSNS (4), /* int_mult_si */
1099 COSTS_N_INSNS (11), /* int_mult_di */
1100 COSTS_N_INSNS (36), /* int_div_si */
1101 COSTS_N_INSNS (68), /* int_div_di */
1102 1, /* branch_cost */
1103 4 /* memory_latency */
1107 static rtx mips_find_pic_call_symbol (rtx, rtx, bool);
1108 static int mips_register_move_cost (enum machine_mode, reg_class_t,
1110 static unsigned int mips_function_arg_boundary (enum machine_mode, const_tree);
1112 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1113 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1114 struct GTY (()) mflip_mips16_entry {
1118 static GTY ((param_is (struct mflip_mips16_entry))) htab_t mflip_mips16_htab;
1120 /* Hash table callbacks for mflip_mips16_htab. */
1123 mflip_mips16_htab_hash (const void *entry)
1125 return htab_hash_string (((const struct mflip_mips16_entry *) entry)->name);
1129 mflip_mips16_htab_eq (const void *entry, const void *name)
1131 return strcmp (((const struct mflip_mips16_entry *) entry)->name,
1132 (const char *) name) == 0;
1135 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1136 mode, false if it should next add an attribute for the opposite mode. */
1137 static GTY(()) bool mips16_flipper;
1139 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1140 for -mflip-mips16. Return true if it should use "mips16" and false if
1141 it should use "nomips16". */
1144 mflip_mips16_use_mips16_p (tree decl)
1146 struct mflip_mips16_entry *entry;
1151 /* Use the opposite of the command-line setting for anonymous decls. */
1152 if (!DECL_NAME (decl))
1153 return !mips_base_mips16;
1155 if (!mflip_mips16_htab)
1156 mflip_mips16_htab = htab_create_ggc (37, mflip_mips16_htab_hash,
1157 mflip_mips16_htab_eq, NULL);
1159 name = IDENTIFIER_POINTER (DECL_NAME (decl));
1160 hash = htab_hash_string (name);
1161 slot = htab_find_slot_with_hash (mflip_mips16_htab, name, hash, INSERT);
1162 entry = (struct mflip_mips16_entry *) *slot;
1165 mips16_flipper = !mips16_flipper;
1166 entry = ggc_alloc_mflip_mips16_entry ();
1168 entry->mips16_p = mips16_flipper ? !mips_base_mips16 : mips_base_mips16;
1171 return entry->mips16_p;
1174 /* Predicates to test for presence of "near" and "far"/"long_call"
1175 attributes on the given TYPE. */
1178 mips_near_type_p (const_tree type)
1180 return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL;
1184 mips_far_type_p (const_tree type)
1186 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL
1187 || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL);
1190 /* Similar predicates for "mips16"/"nomips16" function attributes. */
1193 mips_mips16_decl_p (const_tree decl)
1195 return lookup_attribute ("mips16", DECL_ATTRIBUTES (decl)) != NULL;
1199 mips_nomips16_decl_p (const_tree decl)
1201 return lookup_attribute ("nomips16", DECL_ATTRIBUTES (decl)) != NULL;
1204 /* Check if the interrupt attribute is set for a function. */
1207 mips_interrupt_type_p (tree type)
1209 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type)) != NULL;
1212 /* Check if the attribute to use shadow register set is set for a function. */
1215 mips_use_shadow_register_set_p (tree type)
1217 return lookup_attribute ("use_shadow_register_set",
1218 TYPE_ATTRIBUTES (type)) != NULL;
1221 /* Check if the attribute to keep interrupts masked is set for a function. */
1224 mips_keep_interrupts_masked_p (tree type)
1226 return lookup_attribute ("keep_interrupts_masked",
1227 TYPE_ATTRIBUTES (type)) != NULL;
1230 /* Check if the attribute to use debug exception return is set for
1234 mips_use_debug_exception_return_p (tree type)
1236 return lookup_attribute ("use_debug_exception_return",
1237 TYPE_ATTRIBUTES (type)) != NULL;
1240 /* Return true if function DECL is a MIPS16 function. Return the ambient
1241 setting if DECL is null. */
1244 mips_use_mips16_mode_p (tree decl)
1248 /* Nested functions must use the same frame pointer as their
1249 parent and must therefore use the same ISA mode. */
1250 tree parent = decl_function_context (decl);
1253 if (mips_mips16_decl_p (decl))
1255 if (mips_nomips16_decl_p (decl))
1258 return mips_base_mips16;
1261 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1264 mips_comp_type_attributes (const_tree type1, const_tree type2)
1266 /* Disallow mixed near/far attributes. */
1267 if (mips_far_type_p (type1) && mips_near_type_p (type2))
1269 if (mips_near_type_p (type1) && mips_far_type_p (type2))
1274 /* Implement TARGET_INSERT_ATTRIBUTES. */
1277 mips_insert_attributes (tree decl, tree *attributes)
1280 bool mips16_p, nomips16_p;
1282 /* Check for "mips16" and "nomips16" attributes. */
1283 mips16_p = lookup_attribute ("mips16", *attributes) != NULL;
1284 nomips16_p = lookup_attribute ("nomips16", *attributes) != NULL;
1285 if (TREE_CODE (decl) != FUNCTION_DECL)
1288 error ("%qs attribute only applies to functions", "mips16");
1290 error ("%qs attribute only applies to functions", "nomips16");
1294 mips16_p |= mips_mips16_decl_p (decl);
1295 nomips16_p |= mips_nomips16_decl_p (decl);
1296 if (mips16_p || nomips16_p)
1298 /* DECL cannot be simultaneously "mips16" and "nomips16". */
1299 if (mips16_p && nomips16_p)
1300 error ("%qE cannot have both %<mips16%> and "
1301 "%<nomips16%> attributes",
1304 else if (TARGET_FLIP_MIPS16 && !DECL_ARTIFICIAL (decl))
1306 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1307 "mips16" attribute, arbitrarily pick one. We must pick the same
1308 setting for duplicate declarations of a function. */
1309 name = mflip_mips16_use_mips16_p (decl) ? "mips16" : "nomips16";
1310 *attributes = tree_cons (get_identifier (name), NULL, *attributes);
1315 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1318 mips_merge_decl_attributes (tree olddecl, tree newdecl)
1320 /* The decls' "mips16" and "nomips16" attributes must match exactly. */
1321 if (mips_mips16_decl_p (olddecl) != mips_mips16_decl_p (newdecl))
1322 error ("%qE redeclared with conflicting %qs attributes",
1323 DECL_NAME (newdecl), "mips16");
1324 if (mips_nomips16_decl_p (olddecl) != mips_nomips16_decl_p (newdecl))
1325 error ("%qE redeclared with conflicting %qs attributes",
1326 DECL_NAME (newdecl), "nomips16");
1328 return merge_attributes (DECL_ATTRIBUTES (olddecl),
1329 DECL_ATTRIBUTES (newdecl));
1332 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1333 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1336 mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr)
1338 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
1340 *base_ptr = XEXP (x, 0);
1341 *offset_ptr = INTVAL (XEXP (x, 1));
1350 static unsigned int mips_build_integer (struct mips_integer_op *,
1351 unsigned HOST_WIDE_INT);
1353 /* A subroutine of mips_build_integer, with the same interface.
1354 Assume that the final action in the sequence should be a left shift. */
1357 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1359 unsigned int i, shift;
1361 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1362 since signed numbers are easier to load than unsigned ones. */
1364 while ((value & 1) == 0)
1365 value /= 2, shift++;
1367 i = mips_build_integer (codes, value);
1368 codes[i].code = ASHIFT;
1369 codes[i].value = shift;
1373 /* As for mips_build_shift, but assume that the final action will be
1374 an IOR or PLUS operation. */
1377 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1379 unsigned HOST_WIDE_INT high;
1382 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1383 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
1385 /* The constant is too complex to load with a simple LUI/ORI pair,
1386 so we want to give the recursive call as many trailing zeros as
1387 possible. In this case, we know bit 16 is set and that the
1388 low 16 bits form a negative number. If we subtract that number
1389 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1390 i = mips_build_integer (codes, CONST_HIGH_PART (value));
1391 codes[i].code = PLUS;
1392 codes[i].value = CONST_LOW_PART (value);
1396 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1397 bits gives a value with at least 17 trailing zeros. */
1398 i = mips_build_integer (codes, high);
1399 codes[i].code = IOR;
1400 codes[i].value = value & 0xffff;
1405 /* Fill CODES with a sequence of rtl operations to load VALUE.
1406 Return the number of operations needed. */
1409 mips_build_integer (struct mips_integer_op *codes,
1410 unsigned HOST_WIDE_INT value)
1412 if (SMALL_OPERAND (value)
1413 || SMALL_OPERAND_UNSIGNED (value)
1414 || LUI_OPERAND (value))
1416 /* The value can be loaded with a single instruction. */
1417 codes[0].code = UNKNOWN;
1418 codes[0].value = value;
1421 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
1423 /* Either the constant is a simple LUI/ORI combination or its
1424 lowest bit is set. We don't want to shift in this case. */
1425 return mips_build_lower (codes, value);
1427 else if ((value & 0xffff) == 0)
1429 /* The constant will need at least three actions. The lowest
1430 16 bits are clear, so the final action will be a shift. */
1431 return mips_build_shift (codes, value);
1435 /* The final action could be a shift, add or inclusive OR.
1436 Rather than use a complex condition to select the best
1437 approach, try both mips_build_shift and mips_build_lower
1438 and pick the one that gives the shortest sequence.
1439 Note that this case is only used once per constant. */
1440 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1441 unsigned int cost, alt_cost;
1443 cost = mips_build_shift (codes, value);
1444 alt_cost = mips_build_lower (alt_codes, value);
1445 if (alt_cost < cost)
1447 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
1454 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
1457 mips_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
1459 return mips_const_insns (x) > 0;
1462 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
1465 mips16_stub_function (const char *name)
1469 x = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
1470 SYMBOL_REF_FLAGS (x) |= (SYMBOL_FLAG_EXTERNAL | SYMBOL_FLAG_FUNCTION);
1474 /* Return true if symbols of type TYPE require a GOT access. */
1477 mips_got_symbol_type_p (enum mips_symbol_type type)
1481 case SYMBOL_GOT_PAGE_OFST:
1482 case SYMBOL_GOT_DISP:
1490 /* Return true if X is a thread-local symbol. */
1493 mips_tls_symbol_p (rtx x)
1495 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1498 /* Return true if SYMBOL_REF X is associated with a global symbol
1499 (in the STB_GLOBAL sense). */
1502 mips_global_symbol_p (const_rtx x)
1504 const_tree decl = SYMBOL_REF_DECL (x);
1507 return !SYMBOL_REF_LOCAL_P (x) || SYMBOL_REF_EXTERNAL_P (x);
1509 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1510 or weak symbols. Relocations in the object file will be against
1511 the target symbol, so it's that symbol's binding that matters here. */
1512 return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl));
1515 /* Return true if function X is a libgcc MIPS16 stub function. */
1518 mips16_stub_function_p (const_rtx x)
1520 return (GET_CODE (x) == SYMBOL_REF
1521 && strncmp (XSTR (x, 0), "__mips16_", 9) == 0);
1524 /* Return true if function X is a locally-defined and locally-binding
1528 mips16_local_function_p (const_rtx x)
1530 return (GET_CODE (x) == SYMBOL_REF
1531 && SYMBOL_REF_LOCAL_P (x)
1532 && !SYMBOL_REF_EXTERNAL_P (x)
1533 && mips_use_mips16_mode_p (SYMBOL_REF_DECL (x)));
1536 /* Return true if SYMBOL_REF X binds locally. */
1539 mips_symbol_binds_local_p (const_rtx x)
1541 return (SYMBOL_REF_DECL (x)
1542 ? targetm.binds_local_p (SYMBOL_REF_DECL (x))
1543 : SYMBOL_REF_LOCAL_P (x));
1546 /* Return true if rtx constants of mode MODE should be put into a small
1550 mips_rtx_constant_in_small_data_p (enum machine_mode mode)
1552 return (!TARGET_EMBEDDED_DATA
1553 && TARGET_LOCAL_SDATA
1554 && GET_MODE_SIZE (mode) <= mips_small_data_threshold);
1557 /* Return true if X should not be moved directly into register $25.
1558 We need this because many versions of GAS will treat "la $25,foo" as
1559 part of a call sequence and so allow a global "foo" to be lazily bound. */
1562 mips_dangerous_for_la25_p (rtx x)
1564 return (!TARGET_EXPLICIT_RELOCS
1566 && GET_CODE (x) == SYMBOL_REF
1567 && mips_global_symbol_p (x));
1570 /* Return true if calls to X might need $25 to be valid on entry. */
1573 mips_use_pic_fn_addr_reg_p (const_rtx x)
1575 if (!TARGET_USE_PIC_FN_ADDR_REG)
1578 /* MIPS16 stub functions are guaranteed not to use $25. */
1579 if (mips16_stub_function_p (x))
1582 if (GET_CODE (x) == SYMBOL_REF)
1584 /* If PLTs and copy relocations are available, the static linker
1585 will make sure that $25 is valid on entry to the target function. */
1586 if (TARGET_ABICALLS_PIC0)
1589 /* Locally-defined functions use absolute accesses to set up
1590 the global pointer. */
1591 if (TARGET_ABSOLUTE_ABICALLS
1592 && mips_symbol_binds_local_p (x)
1593 && !SYMBOL_REF_EXTERNAL_P (x))
1600 /* Return the method that should be used to access SYMBOL_REF or
1601 LABEL_REF X in context CONTEXT. */
1603 static enum mips_symbol_type
1604 mips_classify_symbol (const_rtx x, enum mips_symbol_context context)
1607 return SYMBOL_GOT_DISP;
1609 if (GET_CODE (x) == LABEL_REF)
1611 /* Only return SYMBOL_PC_RELATIVE if we are generating MIPS16
1612 code and if we know that the label is in the current function's
1613 text section. LABEL_REFs are used for jump tables as well as
1614 text labels, so we must check whether jump tables live in the
1616 if (TARGET_MIPS16_SHORT_JUMP_TABLES
1617 && !LABEL_REF_NONLOCAL_P (x))
1618 return SYMBOL_PC_RELATIVE;
1620 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1621 return SYMBOL_GOT_PAGE_OFST;
1623 return SYMBOL_ABSOLUTE;
1626 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1628 if (SYMBOL_REF_TLS_MODEL (x))
1631 if (CONSTANT_POOL_ADDRESS_P (x))
1633 if (TARGET_MIPS16_TEXT_LOADS)
1634 return SYMBOL_PC_RELATIVE;
1636 if (TARGET_MIPS16_PCREL_LOADS && context == SYMBOL_CONTEXT_MEM)
1637 return SYMBOL_PC_RELATIVE;
1639 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x)))
1640 return SYMBOL_GP_RELATIVE;
1643 /* Do not use small-data accesses for weak symbols; they may end up
1645 if (TARGET_GPOPT && SYMBOL_REF_SMALL_P (x) && !SYMBOL_REF_WEAK (x))
1646 return SYMBOL_GP_RELATIVE;
1648 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1650 if (TARGET_ABICALLS_PIC2
1651 && !(TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x)))
1653 /* There are three cases to consider:
1655 - o32 PIC (either with or without explicit relocs)
1656 - n32/n64 PIC without explicit relocs
1657 - n32/n64 PIC with explicit relocs
1659 In the first case, both local and global accesses will use an
1660 R_MIPS_GOT16 relocation. We must correctly predict which of
1661 the two semantics (local or global) the assembler and linker
1662 will apply. The choice depends on the symbol's binding rather
1663 than its visibility.
1665 In the second case, the assembler will not use R_MIPS_GOT16
1666 relocations, but it chooses between local and global accesses
1667 in the same way as for o32 PIC.
1669 In the third case we have more freedom since both forms of
1670 access will work for any kind of symbol. However, there seems
1671 little point in doing things differently. */
1672 if (mips_global_symbol_p (x))
1673 return SYMBOL_GOT_DISP;
1675 return SYMBOL_GOT_PAGE_OFST;
1678 return SYMBOL_ABSOLUTE;
1681 /* Classify the base of symbolic expression X, given that X appears in
1684 static enum mips_symbol_type
1685 mips_classify_symbolic_expression (rtx x, enum mips_symbol_context context)
1689 split_const (x, &x, &offset);
1690 if (UNSPEC_ADDRESS_P (x))
1691 return UNSPEC_ADDRESS_TYPE (x);
1693 return mips_classify_symbol (x, context);
1696 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1697 is the alignment in bytes of SYMBOL_REF X. */
1700 mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset)
1702 HOST_WIDE_INT align;
1704 align = SYMBOL_REF_DECL (x) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x)) : 1;
1705 return IN_RANGE (offset, 0, align - 1);
1708 /* Return true if X is a symbolic constant that can be used in context
1709 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1712 mips_symbolic_constant_p (rtx x, enum mips_symbol_context context,
1713 enum mips_symbol_type *symbol_type)
1717 split_const (x, &x, &offset);
1718 if (UNSPEC_ADDRESS_P (x))
1720 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1721 x = UNSPEC_ADDRESS (x);
1723 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1725 *symbol_type = mips_classify_symbol (x, context);
1726 if (*symbol_type == SYMBOL_TLS)
1732 if (offset == const0_rtx)
1735 /* Check whether a nonzero offset is valid for the underlying
1737 switch (*symbol_type)
1739 case SYMBOL_ABSOLUTE:
1740 case SYMBOL_64_HIGH:
1743 /* If the target has 64-bit pointers and the object file only
1744 supports 32-bit symbols, the values of those symbols will be
1745 sign-extended. In this case we can't allow an arbitrary offset
1746 in case the 32-bit value X + OFFSET has a different sign from X. */
1747 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1748 return offset_within_block_p (x, INTVAL (offset));
1750 /* In other cases the relocations can handle any offset. */
1753 case SYMBOL_PC_RELATIVE:
1754 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1755 In this case, we no longer have access to the underlying constant,
1756 but the original symbol-based access was known to be valid. */
1757 if (GET_CODE (x) == LABEL_REF)
1762 case SYMBOL_GP_RELATIVE:
1763 /* Make sure that the offset refers to something within the
1764 same object block. This should guarantee that the final
1765 PC- or GP-relative offset is within the 16-bit limit. */
1766 return offset_within_block_p (x, INTVAL (offset));
1768 case SYMBOL_GOT_PAGE_OFST:
1769 case SYMBOL_GOTOFF_PAGE:
1770 /* If the symbol is global, the GOT entry will contain the symbol's
1771 address, and we will apply a 16-bit offset after loading it.
1772 If the symbol is local, the linker should provide enough local
1773 GOT entries for a 16-bit offset, but larger offsets may lead
1775 return SMALL_INT (offset);
1779 /* There is no carry between the HI and LO REL relocations, so the
1780 offset is only valid if we know it won't lead to such a carry. */
1781 return mips_offset_within_alignment_p (x, INTVAL (offset));
1783 case SYMBOL_GOT_DISP:
1784 case SYMBOL_GOTOFF_DISP:
1785 case SYMBOL_GOTOFF_CALL:
1786 case SYMBOL_GOTOFF_LOADGP:
1789 case SYMBOL_GOTTPREL:
1797 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
1798 single instruction. We rely on the fact that, in the worst case,
1799 all instructions involved in a MIPS16 address calculation are usually
1803 mips_symbol_insns_1 (enum mips_symbol_type type, enum machine_mode mode)
1805 if (mips_use_pcrel_pool_p[(int) type])
1807 if (mode == MAX_MACHINE_MODE)
1808 /* LEAs will be converted into constant-pool references by
1810 type = SYMBOL_PC_RELATIVE;
1812 /* The constant must be loaded and then dereferenced. */
1818 case SYMBOL_ABSOLUTE:
1819 /* When using 64-bit symbols, we need 5 preparatory instructions,
1822 lui $at,%highest(symbol)
1823 daddiu $at,$at,%higher(symbol)
1825 daddiu $at,$at,%hi(symbol)
1828 The final address is then $at + %lo(symbol). With 32-bit
1829 symbols we just need a preparatory LUI for normal mode and
1830 a preparatory LI and SLL for MIPS16. */
1831 return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2;
1833 case SYMBOL_GP_RELATIVE:
1834 /* Treat GP-relative accesses as taking a single instruction on
1835 MIPS16 too; the copy of $gp can often be shared. */
1838 case SYMBOL_PC_RELATIVE:
1839 /* PC-relative constants can be only be used with ADDIUPC,
1840 DADDIUPC, LWPC and LDPC. */
1841 if (mode == MAX_MACHINE_MODE
1842 || GET_MODE_SIZE (mode) == 4
1843 || GET_MODE_SIZE (mode) == 8)
1846 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
1849 case SYMBOL_GOT_DISP:
1850 /* The constant will have to be loaded from the GOT before it
1851 is used in an address. */
1852 if (mode != MAX_MACHINE_MODE)
1857 case SYMBOL_GOT_PAGE_OFST:
1858 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
1859 local/global classification is accurate. The worst cases are:
1861 (1) For local symbols when generating o32 or o64 code. The assembler
1867 ...and the final address will be $at + %lo(symbol).
1869 (2) For global symbols when -mxgot. The assembler will use:
1871 lui $at,%got_hi(symbol)
1874 ...and the final address will be $at + %got_lo(symbol). */
1877 case SYMBOL_GOTOFF_PAGE:
1878 case SYMBOL_GOTOFF_DISP:
1879 case SYMBOL_GOTOFF_CALL:
1880 case SYMBOL_GOTOFF_LOADGP:
1881 case SYMBOL_64_HIGH:
1887 case SYMBOL_GOTTPREL:
1890 /* A 16-bit constant formed by a single relocation, or a 32-bit
1891 constant formed from a high 16-bit relocation and a low 16-bit
1892 relocation. Use mips_split_p to determine which. 32-bit
1893 constants need an "lui; addiu" sequence for normal mode and
1894 an "li; sll; addiu" sequence for MIPS16 mode. */
1895 return !mips_split_p[type] ? 1 : TARGET_MIPS16 ? 3 : 2;
1898 /* We don't treat a bare TLS symbol as a constant. */
1904 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
1905 to load symbols of type TYPE into a register. Return 0 if the given
1906 type of symbol cannot be used as an immediate operand.
1908 Otherwise, return the number of instructions needed to load or store
1909 values of mode MODE to or from addresses of type TYPE. Return 0 if
1910 the given type of symbol is not valid in addresses.
1912 In both cases, treat extended MIPS16 instructions as two instructions. */
1915 mips_symbol_insns (enum mips_symbol_type type, enum machine_mode mode)
1917 return mips_symbol_insns_1 (type, mode) * (TARGET_MIPS16 ? 2 : 1);
1920 /* A for_each_rtx callback. Stop the search if *X references a
1921 thread-local symbol. */
1924 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1926 return mips_tls_symbol_p (*x);
1929 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1932 mips_cannot_force_const_mem (enum machine_mode mode, rtx x)
1934 enum mips_symbol_type type;
1937 /* There is no assembler syntax for expressing an address-sized
1939 if (GET_CODE (x) == HIGH)
1942 /* As an optimization, reject constants that mips_legitimize_move
1945 Suppose we have a multi-instruction sequence that loads constant C
1946 into register R. If R does not get allocated a hard register, and
1947 R is used in an operand that allows both registers and memory
1948 references, reload will consider forcing C into memory and using
1949 one of the instruction's memory alternatives. Returning false
1950 here will force it to use an input reload instead. */
1951 if (CONST_INT_P (x) && mips_legitimate_constant_p (mode, x))
1954 split_const (x, &base, &offset);
1955 if (mips_symbolic_constant_p (base, SYMBOL_CONTEXT_LEA, &type))
1957 /* See whether we explicitly want these symbols in the pool. */
1958 if (mips_use_pcrel_pool_p[(int) type])
1961 /* The same optimization as for CONST_INT. */
1962 if (SMALL_INT (offset) && mips_symbol_insns (type, MAX_MACHINE_MODE) > 0)
1965 /* If MIPS16 constant pools live in the text section, they should
1966 not refer to anything that might need run-time relocation. */
1967 if (TARGET_MIPS16_PCREL_LOADS && mips_got_symbol_type_p (type))
1971 /* TLS symbols must be computed by mips_legitimize_move. */
1972 if (for_each_rtx (&x, &mips_tls_symbol_ref_1, NULL))
1978 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
1979 constants when we're using a per-function constant pool. */
1982 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
1983 const_rtx x ATTRIBUTE_UNUSED)
1985 return !TARGET_MIPS16_PCREL_LOADS;
1988 /* Return true if register REGNO is a valid base register for mode MODE.
1989 STRICT_P is true if REG_OK_STRICT is in effect. */
1992 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode,
1995 if (!HARD_REGISTER_NUM_P (regno))
1999 regno = reg_renumber[regno];
2002 /* These fake registers will be eliminated to either the stack or
2003 hard frame pointer, both of which are usually valid base registers.
2004 Reload deals with the cases where the eliminated form isn't valid. */
2005 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
2008 /* In MIPS16 mode, the stack pointer can only address word and doubleword
2009 values, nothing smaller. There are two problems here:
2011 (a) Instantiating virtual registers can introduce new uses of the
2012 stack pointer. If these virtual registers are valid addresses,
2013 the stack pointer should be too.
2015 (b) Most uses of the stack pointer are not made explicit until
2016 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
2017 We don't know until that stage whether we'll be eliminating to the
2018 stack pointer (which needs the restriction) or the hard frame
2019 pointer (which doesn't).
2021 All in all, it seems more consistent to only enforce this restriction
2022 during and after reload. */
2023 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
2024 return !strict_p || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
2026 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
2029 /* Return true if X is a valid base register for mode MODE.
2030 STRICT_P is true if REG_OK_STRICT is in effect. */
2033 mips_valid_base_register_p (rtx x, enum machine_mode mode, bool strict_p)
2035 if (!strict_p && GET_CODE (x) == SUBREG)
2039 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p));
2042 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2043 can address a value of mode MODE. */
2046 mips_valid_offset_p (rtx x, enum machine_mode mode)
2048 /* Check that X is a signed 16-bit number. */
2049 if (!const_arith_operand (x, Pmode))
2052 /* We may need to split multiword moves, so make sure that every word
2054 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2055 && !SMALL_OPERAND (INTVAL (x) + GET_MODE_SIZE (mode) - UNITS_PER_WORD))
2061 /* Return true if a LO_SUM can address a value of mode MODE when the
2062 LO_SUM symbol has type SYMBOL_TYPE. */
2065 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type, enum machine_mode mode)
2067 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2069 if (mips_symbol_insns (symbol_type, mode) == 0)
2072 /* Check that there is a known low-part relocation. */
2073 if (mips_lo_relocs[symbol_type] == NULL)
2076 /* We may need to split multiword moves, so make sure that each word
2077 can be accessed without inducing a carry. This is mainly needed
2078 for o64, which has historically only guaranteed 64-bit alignment
2079 for 128-bit types. */
2080 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2081 && GET_MODE_BITSIZE (mode) > GET_MODE_ALIGNMENT (mode))
2087 /* Return true if X is a valid address for machine mode MODE. If it is,
2088 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2092 mips_classify_address (struct mips_address_info *info, rtx x,
2093 enum machine_mode mode, bool strict_p)
2095 switch (GET_CODE (x))
2099 info->type = ADDRESS_REG;
2101 info->offset = const0_rtx;
2102 return mips_valid_base_register_p (info->reg, mode, strict_p);
2105 info->type = ADDRESS_REG;
2106 info->reg = XEXP (x, 0);
2107 info->offset = XEXP (x, 1);
2108 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2109 && mips_valid_offset_p (info->offset, mode));
2112 info->type = ADDRESS_LO_SUM;
2113 info->reg = XEXP (x, 0);
2114 info->offset = XEXP (x, 1);
2115 /* We have to trust the creator of the LO_SUM to do something vaguely
2116 sane. Target-independent code that creates a LO_SUM should also
2117 create and verify the matching HIGH. Target-independent code that
2118 adds an offset to a LO_SUM must prove that the offset will not
2119 induce a carry. Failure to do either of these things would be
2120 a bug, and we are not required to check for it here. The MIPS
2121 backend itself should only create LO_SUMs for valid symbolic
2122 constants, with the high part being either a HIGH or a copy
2125 = mips_classify_symbolic_expression (info->offset, SYMBOL_CONTEXT_MEM);
2126 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2127 && mips_valid_lo_sum_p (info->symbol_type, mode));
2130 /* Small-integer addresses don't occur very often, but they
2131 are legitimate if $0 is a valid base register. */
2132 info->type = ADDRESS_CONST_INT;
2133 return !TARGET_MIPS16 && SMALL_INT (x);
2138 info->type = ADDRESS_SYMBOLIC;
2139 return (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_MEM,
2141 && mips_symbol_insns (info->symbol_type, mode) > 0
2142 && !mips_split_p[info->symbol_type]);
2149 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2152 mips_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
2154 struct mips_address_info addr;
2156 return mips_classify_address (&addr, x, mode, strict_p);
2159 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
2162 mips_stack_address_p (rtx x, enum machine_mode mode)
2164 struct mips_address_info addr;
2166 return (mips_classify_address (&addr, x, mode, false)
2167 && addr.type == ADDRESS_REG
2168 && addr.reg == stack_pointer_rtx);
2171 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2172 address instruction. Note that such addresses are not considered
2173 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2174 is so restricted. */
2177 mips_lwxs_address_p (rtx addr)
2180 && GET_CODE (addr) == PLUS
2181 && REG_P (XEXP (addr, 1)))
2183 rtx offset = XEXP (addr, 0);
2184 if (GET_CODE (offset) == MULT
2185 && REG_P (XEXP (offset, 0))
2186 && CONST_INT_P (XEXP (offset, 1))
2187 && INTVAL (XEXP (offset, 1)) == 4)
2193 /* Return true if ADDR matches the pattern for the L{B,H,W,D}{,U}X load
2194 indexed address instruction. Note that such addresses are
2195 not considered legitimate in the TARGET_LEGITIMATE_ADDRESS_P
2196 sense, because their use is so restricted. */
2199 mips_lx_address_p (rtx addr, enum machine_mode mode)
2201 if (GET_CODE (addr) != PLUS
2202 || !REG_P (XEXP (addr, 0))
2203 || !REG_P (XEXP (addr, 1)))
2205 if (ISA_HAS_LBX && mode == QImode)
2207 if (ISA_HAS_LHX && mode == HImode)
2209 if (ISA_HAS_LWX && mode == SImode)
2211 if (ISA_HAS_LDX && mode == DImode)
2216 /* Return true if a value at OFFSET bytes from base register BASE can be
2217 accessed using an unextended MIPS16 instruction. MODE is the mode of
2220 Usually the offset in an unextended instruction is a 5-bit field.
2221 The offset is unsigned and shifted left once for LH and SH, twice
2222 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2223 an 8-bit immediate field that's shifted left twice. */
2226 mips16_unextended_reference_p (enum machine_mode mode, rtx base,
2227 unsigned HOST_WIDE_INT offset)
2229 if (mode != BLKmode && offset % GET_MODE_SIZE (mode) == 0)
2231 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
2232 return offset < 256U * GET_MODE_SIZE (mode);
2233 return offset < 32U * GET_MODE_SIZE (mode);
2238 /* Return the number of instructions needed to load or store a value
2239 of mode MODE at address X. Return 0 if X isn't valid for MODE.
2240 Assume that multiword moves may need to be split into word moves
2241 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2244 For MIPS16 code, count extended instructions as two instructions. */
2247 mips_address_insns (rtx x, enum machine_mode mode, bool might_split_p)
2249 struct mips_address_info addr;
2252 /* BLKmode is used for single unaligned loads and stores and should
2253 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2254 meaningless, so we have to single it out as a special case one way
2256 if (mode != BLKmode && might_split_p)
2257 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2261 if (mips_classify_address (&addr, x, mode, false))
2266 && !mips16_unextended_reference_p (mode, addr.reg,
2267 UINTVAL (addr.offset)))
2271 case ADDRESS_LO_SUM:
2272 return TARGET_MIPS16 ? factor * 2 : factor;
2274 case ADDRESS_CONST_INT:
2277 case ADDRESS_SYMBOLIC:
2278 return factor * mips_symbol_insns (addr.symbol_type, mode);
2283 /* Return the number of instructions needed to load constant X.
2284 Return 0 if X isn't a valid constant. */
2287 mips_const_insns (rtx x)
2289 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2290 enum mips_symbol_type symbol_type;
2293 switch (GET_CODE (x))
2296 if (!mips_symbolic_constant_p (XEXP (x, 0), SYMBOL_CONTEXT_LEA,
2298 || !mips_split_p[symbol_type])
2301 /* This is simply an LUI for normal mode. It is an extended
2302 LI followed by an extended SLL for MIPS16. */
2303 return TARGET_MIPS16 ? 4 : 1;
2307 /* Unsigned 8-bit constants can be loaded using an unextended
2308 LI instruction. Unsigned 16-bit constants can be loaded
2309 using an extended LI. Negative constants must be loaded
2310 using LI and then negated. */
2311 return (IN_RANGE (INTVAL (x), 0, 255) ? 1
2312 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
2313 : IN_RANGE (-INTVAL (x), 0, 255) ? 2
2314 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
2317 return mips_build_integer (codes, INTVAL (x));
2321 /* Allow zeros for normal mode, where we can use $0. */
2322 return !TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0;
2328 /* See if we can refer to X directly. */
2329 if (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_LEA, &symbol_type))
2330 return mips_symbol_insns (symbol_type, MAX_MACHINE_MODE);
2332 /* Otherwise try splitting the constant into a base and offset.
2333 If the offset is a 16-bit value, we can load the base address
2334 into a register and then use (D)ADDIU to add in the offset.
2335 If the offset is larger, we can load the base and offset
2336 into separate registers and add them together with (D)ADDU.
2337 However, the latter is only possible before reload; during
2338 and after reload, we must have the option of forcing the
2339 constant into the pool instead. */
2340 split_const (x, &x, &offset);
2343 int n = mips_const_insns (x);
2346 if (SMALL_INT (offset))
2348 else if (!targetm.cannot_force_const_mem (GET_MODE (x), x))
2349 return n + 1 + mips_build_integer (codes, INTVAL (offset));
2356 return mips_symbol_insns (mips_classify_symbol (x, SYMBOL_CONTEXT_LEA),
2364 /* X is a doubleword constant that can be handled by splitting it into
2365 two words and loading each word separately. Return the number of
2366 instructions required to do this. */
2369 mips_split_const_insns (rtx x)
2371 unsigned int low, high;
2373 low = mips_const_insns (mips_subword (x, false));
2374 high = mips_const_insns (mips_subword (x, true));
2375 gcc_assert (low > 0 && high > 0);
2379 /* Return the number of instructions needed to implement INSN,
2380 given that it loads from or stores to MEM. Count extended
2381 MIPS16 instructions as two instructions. */
2384 mips_load_store_insns (rtx mem, rtx insn)
2386 enum machine_mode mode;
2390 gcc_assert (MEM_P (mem));
2391 mode = GET_MODE (mem);
2393 /* Try to prove that INSN does not need to be split. */
2394 might_split_p = true;
2395 if (GET_MODE_BITSIZE (mode) == 64)
2397 set = single_set (insn);
2398 if (set && !mips_split_64bit_move_p (SET_DEST (set), SET_SRC (set)))
2399 might_split_p = false;
2402 return mips_address_insns (XEXP (mem, 0), mode, might_split_p);
2405 /* Return the number of instructions needed for an integer division. */
2408 mips_idiv_insns (void)
2413 if (TARGET_CHECK_ZERO_DIV)
2415 if (GENERATE_DIVIDE_TRAPS)
2421 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
2426 /* Emit a move from SRC to DEST. Assume that the move expanders can
2427 handle all moves if !can_create_pseudo_p (). The distinction is
2428 important because, unlike emit_move_insn, the move expanders know
2429 how to force Pmode objects into the constant pool even when the
2430 constant pool address is not itself legitimate. */
2433 mips_emit_move (rtx dest, rtx src)
2435 return (can_create_pseudo_p ()
2436 ? emit_move_insn (dest, src)
2437 : emit_move_insn_1 (dest, src));
2440 /* Emit an instruction of the form (set TARGET (CODE OP0)). */
2443 mips_emit_unary (enum rtx_code code, rtx target, rtx op0)
2445 emit_insn (gen_rtx_SET (VOIDmode, target,
2446 gen_rtx_fmt_e (code, GET_MODE (op0), op0)));
2449 /* Compute (CODE OP0) and store the result in a new register of mode MODE.
2450 Return that new register. */
2453 mips_force_unary (enum machine_mode mode, enum rtx_code code, rtx op0)
2457 reg = gen_reg_rtx (mode);
2458 mips_emit_unary (code, reg, op0);
2462 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2465 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
2467 emit_insn (gen_rtx_SET (VOIDmode, target,
2468 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
2471 /* Compute (CODE OP0 OP1) and store the result in a new register
2472 of mode MODE. Return that new register. */
2475 mips_force_binary (enum machine_mode mode, enum rtx_code code, rtx op0, rtx op1)
2479 reg = gen_reg_rtx (mode);
2480 mips_emit_binary (code, reg, op0, op1);
2484 /* Copy VALUE to a register and return that register. If new pseudos
2485 are allowed, copy it into a new register, otherwise use DEST. */
2488 mips_force_temporary (rtx dest, rtx value)
2490 if (can_create_pseudo_p ())
2491 return force_reg (Pmode, value);
2494 mips_emit_move (dest, value);
2499 /* Emit a call sequence with call pattern PATTERN and return the call
2500 instruction itself (which is not necessarily the last instruction
2501 emitted). ORIG_ADDR is the original, unlegitimized address,
2502 ADDR is the legitimized form, and LAZY_P is true if the call
2503 address is lazily-bound. */
2506 mips_emit_call_insn (rtx pattern, rtx orig_addr, rtx addr, bool lazy_p)
2510 insn = emit_call_insn (pattern);
2512 if (TARGET_MIPS16 && mips_use_pic_fn_addr_reg_p (orig_addr))
2514 /* MIPS16 JALRs only take MIPS16 registers. If the target
2515 function requires $25 to be valid on entry, we must copy it
2516 there separately. The move instruction can be put in the
2517 call's delay slot. */
2518 reg = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
2519 emit_insn_before (gen_move_insn (reg, addr), insn);
2520 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
2524 /* Lazy-binding stubs require $gp to be valid on entry. */
2525 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
2529 /* See the comment above load_call<mode> for details. */
2530 use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
2531 gen_rtx_REG (Pmode, GOT_VERSION_REGNUM));
2532 emit_insn (gen_update_got_version ());
2537 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2538 then add CONST_INT OFFSET to the result. */
2541 mips_unspec_address_offset (rtx base, rtx offset,
2542 enum mips_symbol_type symbol_type)
2544 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
2545 UNSPEC_ADDRESS_FIRST + symbol_type);
2546 if (offset != const0_rtx)
2547 base = gen_rtx_PLUS (Pmode, base, offset);
2548 return gen_rtx_CONST (Pmode, base);
2551 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2552 type SYMBOL_TYPE. */
2555 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
2559 split_const (address, &base, &offset);
2560 return mips_unspec_address_offset (base, offset, symbol_type);
2563 /* If OP is an UNSPEC address, return the address to which it refers,
2564 otherwise return OP itself. */
2567 mips_strip_unspec_address (rtx op)
2571 split_const (op, &base, &offset);
2572 if (UNSPEC_ADDRESS_P (base))
2573 op = plus_constant (Pmode, UNSPEC_ADDRESS (base), INTVAL (offset));
2577 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2578 high part to BASE and return the result. Just return BASE otherwise.
2579 TEMP is as for mips_force_temporary.
2581 The returned expression can be used as the first operand to a LO_SUM. */
2584 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
2585 enum mips_symbol_type symbol_type)
2587 if (mips_split_p[symbol_type])
2589 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
2590 addr = mips_force_temporary (temp, addr);
2591 base = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
2596 /* Return an instruction that copies $gp into register REG. We want
2597 GCC to treat the register's value as constant, so that its value
2598 can be rematerialized on demand. */
2601 gen_load_const_gp (rtx reg)
2603 return PMODE_INSN (gen_load_const_gp, (reg));
2606 /* Return a pseudo register that contains the value of $gp throughout
2607 the current function. Such registers are needed by MIPS16 functions,
2608 for which $gp itself is not a valid base register or addition operand. */
2611 mips16_gp_pseudo_reg (void)
2613 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
2617 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
2619 push_topmost_sequence ();
2621 scan = get_insns ();
2622 while (NEXT_INSN (scan) && !INSN_P (NEXT_INSN (scan)))
2623 scan = NEXT_INSN (scan);
2625 insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
2626 insn = emit_insn_after (insn, scan);
2627 INSN_LOCATOR (insn) = 0;
2629 pop_topmost_sequence ();
2632 return cfun->machine->mips16_gp_pseudo_rtx;
2635 /* Return a base register that holds pic_offset_table_rtx.
2636 TEMP, if nonnull, is a scratch Pmode base register. */
2639 mips_pic_base_register (rtx temp)
2642 return pic_offset_table_rtx;
2644 if (currently_expanding_to_rtl)
2645 return mips16_gp_pseudo_reg ();
2647 if (can_create_pseudo_p ())
2648 temp = gen_reg_rtx (Pmode);
2651 /* The first post-reload split exposes all references to $gp
2652 (both uses and definitions). All references must remain
2653 explicit after that point.
2655 It is safe to introduce uses of $gp at any time, so for
2656 simplicity, we do that before the split too. */
2657 mips_emit_move (temp, pic_offset_table_rtx);
2659 emit_insn (gen_load_const_gp (temp));
2663 /* Return the RHS of a load_call<mode> insn. */
2666 mips_unspec_call (rtx reg, rtx symbol)
2670 vec = gen_rtvec (3, reg, symbol, gen_rtx_REG (SImode, GOT_VERSION_REGNUM));
2671 return gen_rtx_UNSPEC (Pmode, vec, UNSPEC_LOAD_CALL);
2674 /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol
2675 reference. Return NULL_RTX otherwise. */
2678 mips_strip_unspec_call (rtx src)
2680 if (GET_CODE (src) == UNSPEC && XINT (src, 1) == UNSPEC_LOAD_CALL)
2681 return mips_strip_unspec_address (XVECEXP (src, 0, 1));
2685 /* Create and return a GOT reference of type TYPE for address ADDR.
2686 TEMP, if nonnull, is a scratch Pmode base register. */
2689 mips_got_load (rtx temp, rtx addr, enum mips_symbol_type type)
2691 rtx base, high, lo_sum_symbol;
2693 base = mips_pic_base_register (temp);
2695 /* If we used the temporary register to load $gp, we can't use
2696 it for the high part as well. */
2697 if (temp != NULL && reg_overlap_mentioned_p (base, temp))
2700 high = mips_unspec_offset_high (temp, base, addr, type);
2701 lo_sum_symbol = mips_unspec_address (addr, type);
2703 if (type == SYMBOL_GOTOFF_CALL)
2704 return mips_unspec_call (high, lo_sum_symbol);
2706 return PMODE_INSN (gen_unspec_got, (high, lo_sum_symbol));
2709 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2710 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2711 constant in that context and can be split into high and low parts.
2712 If so, and if LOW_OUT is nonnull, emit the high part and store the
2713 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
2715 TEMP is as for mips_force_temporary and is used to load the high
2716 part into a register.
2718 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
2719 a legitimize SET_SRC for an .md pattern, otherwise the low part
2720 is guaranteed to be a legitimate address for mode MODE. */
2723 mips_split_symbol (rtx temp, rtx addr, enum machine_mode mode, rtx *low_out)
2725 enum mips_symbol_context context;
2726 enum mips_symbol_type symbol_type;
2729 context = (mode == MAX_MACHINE_MODE
2730 ? SYMBOL_CONTEXT_LEA
2731 : SYMBOL_CONTEXT_MEM);
2732 if (GET_CODE (addr) == HIGH && context == SYMBOL_CONTEXT_LEA)
2734 addr = XEXP (addr, 0);
2735 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2736 && mips_symbol_insns (symbol_type, mode) > 0
2737 && mips_split_hi_p[symbol_type])
2740 switch (symbol_type)
2742 case SYMBOL_GOT_PAGE_OFST:
2743 /* The high part of a page/ofst pair is loaded from the GOT. */
2744 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_PAGE);
2755 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2756 && mips_symbol_insns (symbol_type, mode) > 0
2757 && mips_split_p[symbol_type])
2760 switch (symbol_type)
2762 case SYMBOL_GOT_DISP:
2763 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
2764 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_DISP);
2767 case SYMBOL_GP_RELATIVE:
2768 high = mips_pic_base_register (temp);
2769 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2773 high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
2774 high = mips_force_temporary (temp, high);
2775 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2784 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2785 mips_force_temporary; it is only needed when OFFSET is not a
2789 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
2791 if (!SMALL_OPERAND (offset))
2797 /* Load the full offset into a register so that we can use
2798 an unextended instruction for the address itself. */
2799 high = GEN_INT (offset);
2804 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
2805 The addition inside the macro CONST_HIGH_PART may cause an
2806 overflow, so we need to force a sign-extension check. */
2807 high = gen_int_mode (CONST_HIGH_PART (offset), Pmode);
2808 offset = CONST_LOW_PART (offset);
2810 high = mips_force_temporary (temp, high);
2811 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
2813 return plus_constant (Pmode, reg, offset);
2816 /* The __tls_get_attr symbol. */
2817 static GTY(()) rtx mips_tls_symbol;
2819 /* Return an instruction sequence that calls __tls_get_addr. SYM is
2820 the TLS symbol we are referencing and TYPE is the symbol type to use
2821 (either global dynamic or local dynamic). V0 is an RTX for the
2822 return value location. */
2825 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
2829 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
2831 if (!mips_tls_symbol)
2832 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
2834 loc = mips_unspec_address (sym, type);
2838 emit_insn (gen_rtx_SET (Pmode, a0,
2839 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
2840 insn = mips_expand_call (MIPS_CALL_NORMAL, v0, mips_tls_symbol,
2841 const0_rtx, NULL_RTX, false);
2842 RTL_CONST_CALL_P (insn) = 1;
2843 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
2844 insn = get_insns ();
2851 /* Return a pseudo register that contains the current thread pointer. */
2858 tp = gen_reg_rtx (Pmode);
2861 mips_need_mips16_rdhwr_p = true;
2862 fn = mips16_stub_function ("__mips16_rdhwr");
2863 SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_LOCAL;
2864 if (!call_insn_operand (fn, VOIDmode))
2865 fn = force_reg (Pmode, fn);
2866 emit_insn (PMODE_INSN (gen_tls_get_tp_mips16, (tp, fn)));
2869 emit_insn (PMODE_INSN (gen_tls_get_tp, (tp)));
2873 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
2874 its address. The return value will be both a valid address and a valid
2875 SET_SRC (either a REG or a LO_SUM). */
2878 mips_legitimize_tls_address (rtx loc)
2880 rtx dest, insn, v0, tp, tmp1, tmp2, eqv, offset;
2881 enum tls_model model;
2883 model = SYMBOL_REF_TLS_MODEL (loc);
2884 /* Only TARGET_ABICALLS code can have more than one module; other
2885 code must be be static and should not use a GOT. All TLS models
2886 reduce to local exec in this situation. */
2887 if (!TARGET_ABICALLS)
2888 model = TLS_MODEL_LOCAL_EXEC;
2892 case TLS_MODEL_GLOBAL_DYNAMIC:
2893 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2894 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
2895 dest = gen_reg_rtx (Pmode);
2896 emit_libcall_block (insn, dest, v0, loc);
2899 case TLS_MODEL_LOCAL_DYNAMIC:
2900 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2901 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
2902 tmp1 = gen_reg_rtx (Pmode);
2904 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2905 share the LDM result with other LD model accesses. */
2906 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2908 emit_libcall_block (insn, tmp1, v0, eqv);
2910 offset = mips_unspec_address (loc, SYMBOL_DTPREL);
2911 if (mips_split_p[SYMBOL_DTPREL])
2913 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
2914 dest = gen_rtx_LO_SUM (Pmode, tmp2, offset);
2917 dest = expand_binop (Pmode, add_optab, tmp1, offset,
2918 0, 0, OPTAB_DIRECT);
2921 case TLS_MODEL_INITIAL_EXEC:
2922 tp = mips_get_tp ();
2923 tmp1 = gen_reg_rtx (Pmode);
2924 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
2925 if (Pmode == DImode)
2926 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
2928 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
2929 dest = gen_reg_rtx (Pmode);
2930 emit_insn (gen_add3_insn (dest, tmp1, tp));
2933 case TLS_MODEL_LOCAL_EXEC:
2934 tmp1 = mips_get_tp ();
2935 offset = mips_unspec_address (loc, SYMBOL_TPREL);
2936 if (mips_split_p[SYMBOL_TPREL])
2938 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_TPREL);
2939 dest = gen_rtx_LO_SUM (Pmode, tmp2, offset);
2942 dest = expand_binop (Pmode, add_optab, tmp1, offset,
2943 0, 0, OPTAB_DIRECT);
2952 /* If X is not a valid address for mode MODE, force it into a register. */
2955 mips_force_address (rtx x, enum machine_mode mode)
2957 if (!mips_legitimate_address_p (mode, x, false))
2958 x = force_reg (Pmode, x);
2962 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
2963 be legitimized in a way that the generic machinery might not expect,
2964 return a new address, otherwise return NULL. MODE is the mode of
2965 the memory being accessed. */
2968 mips_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
2969 enum machine_mode mode)
2972 HOST_WIDE_INT offset;
2974 if (mips_tls_symbol_p (x))
2975 return mips_legitimize_tls_address (x);
2977 /* See if the address can split into a high part and a LO_SUM. */
2978 if (mips_split_symbol (NULL, x, mode, &addr))
2979 return mips_force_address (addr, mode);
2981 /* Handle BASE + OFFSET using mips_add_offset. */
2982 mips_split_plus (x, &base, &offset);
2985 if (!mips_valid_base_register_p (base, mode, false))
2986 base = copy_to_mode_reg (Pmode, base);
2987 addr = mips_add_offset (NULL, base, offset);
2988 return mips_force_address (addr, mode);
2994 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
2997 mips_move_integer (rtx temp, rtx dest, unsigned HOST_WIDE_INT value)
2999 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
3000 enum machine_mode mode;
3001 unsigned int i, num_ops;
3004 mode = GET_MODE (dest);
3005 num_ops = mips_build_integer (codes, value);
3007 /* Apply each binary operation to X. Invariant: X is a legitimate
3008 source operand for a SET pattern. */
3009 x = GEN_INT (codes[0].value);
3010 for (i = 1; i < num_ops; i++)
3012 if (!can_create_pseudo_p ())
3014 emit_insn (gen_rtx_SET (VOIDmode, temp, x));
3018 x = force_reg (mode, x);
3019 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
3022 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
3025 /* Subroutine of mips_legitimize_move. Move constant SRC into register
3026 DEST given that SRC satisfies immediate_operand but doesn't satisfy
3030 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
3034 /* Split moves of big integers into smaller pieces. */
3035 if (splittable_const_int_operand (src, mode))
3037 mips_move_integer (dest, dest, INTVAL (src));
3041 /* Split moves of symbolic constants into high/low pairs. */
3042 if (mips_split_symbol (dest, src, MAX_MACHINE_MODE, &src))
3044 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
3048 /* Generate the appropriate access sequences for TLS symbols. */
3049 if (mips_tls_symbol_p (src))
3051 mips_emit_move (dest, mips_legitimize_tls_address (src));
3055 /* If we have (const (plus symbol offset)), and that expression cannot
3056 be forced into memory, load the symbol first and add in the offset.
3057 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
3058 forced into memory, as it usually produces better code. */
3059 split_const (src, &base, &offset);
3060 if (offset != const0_rtx
3061 && (targetm.cannot_force_const_mem (mode, src)
3062 || (!TARGET_MIPS16 && can_create_pseudo_p ())))
3064 base = mips_force_temporary (dest, base);
3065 mips_emit_move (dest, mips_add_offset (NULL, base, INTVAL (offset)));
3069 src = force_const_mem (mode, src);
3071 /* When using explicit relocs, constant pool references are sometimes
3072 not legitimate addresses. */
3073 mips_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0));
3074 mips_emit_move (dest, src);
3077 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
3078 sequence that is valid. */
3081 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
3083 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
3085 mips_emit_move (dest, force_reg (mode, src));
3089 /* We need to deal with constants that would be legitimate
3090 immediate_operands but aren't legitimate move_operands. */
3091 if (CONSTANT_P (src) && !move_operand (src, mode))
3093 mips_legitimize_const_move (mode, dest, src);
3094 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
3100 /* Return true if value X in context CONTEXT is a small-data address
3101 that can be rewritten as a LO_SUM. */
3104 mips_rewrite_small_data_p (rtx x, enum mips_symbol_context context)
3106 enum mips_symbol_type symbol_type;
3108 return (mips_lo_relocs[SYMBOL_GP_RELATIVE]
3109 && !mips_split_p[SYMBOL_GP_RELATIVE]
3110 && mips_symbolic_constant_p (x, context, &symbol_type)
3111 && symbol_type == SYMBOL_GP_RELATIVE);
3114 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
3115 containing MEM, or null if none. */
3118 mips_small_data_pattern_1 (rtx *loc, void *data)
3120 enum mips_symbol_context context;
3122 /* Ignore things like "g" constraints in asms. We make no particular
3123 guarantee about which symbolic constants are acceptable as asm operands
3124 versus which must be forced into a GPR. */
3125 if (GET_CODE (*loc) == LO_SUM || GET_CODE (*loc) == ASM_OPERANDS)
3130 if (for_each_rtx (&XEXP (*loc, 0), mips_small_data_pattern_1, *loc))
3135 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3136 return mips_rewrite_small_data_p (*loc, context);
3139 /* Return true if OP refers to small data symbols directly, not through
3143 mips_small_data_pattern_p (rtx op)
3145 return for_each_rtx (&op, mips_small_data_pattern_1, NULL);
3148 /* A for_each_rtx callback, used by mips_rewrite_small_data.
3149 DATA is the containing MEM, or null if none. */
3152 mips_rewrite_small_data_1 (rtx *loc, void *data)
3154 enum mips_symbol_context context;
3158 for_each_rtx (&XEXP (*loc, 0), mips_rewrite_small_data_1, *loc);
3162 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3163 if (mips_rewrite_small_data_p (*loc, context))
3164 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
3166 if (GET_CODE (*loc) == LO_SUM)
3172 /* Rewrite instruction pattern PATTERN so that it refers to small data
3173 using explicit relocations. */
3176 mips_rewrite_small_data (rtx pattern)
3178 pattern = copy_insn (pattern);
3179 for_each_rtx (&pattern, mips_rewrite_small_data_1, NULL);
3183 /* We need a lot of little routines to check the range of MIPS16 immediate
3187 m16_check_op (rtx op, int low, int high, int mask)
3189 return (CONST_INT_P (op)
3190 && IN_RANGE (INTVAL (op), low, high)
3191 && (INTVAL (op) & mask) == 0);
3195 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3197 return m16_check_op (op, 0x1, 0x8, 0);
3201 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3203 return m16_check_op (op, -0x8, 0x7, 0);
3207 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3209 return m16_check_op (op, -0x7, 0x8, 0);
3213 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3215 return m16_check_op (op, -0x10, 0xf, 0);
3219 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3221 return m16_check_op (op, -0xf, 0x10, 0);
3225 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3227 return m16_check_op (op, -0x10 << 2, 0xf << 2, 3);
3231 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3233 return m16_check_op (op, -0xf << 2, 0x10 << 2, 3);
3237 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3239 return m16_check_op (op, -0x80, 0x7f, 0);
3243 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3245 return m16_check_op (op, -0x7f, 0x80, 0);
3249 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3251 return m16_check_op (op, 0x0, 0xff, 0);
3255 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3257 return m16_check_op (op, -0xff, 0x0, 0);
3261 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3263 return m16_check_op (op, -0x1, 0xfe, 0);
3267 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3269 return m16_check_op (op, 0x0, 0xff << 2, 3);
3273 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3275 return m16_check_op (op, -0xff << 2, 0x0, 3);
3279 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3281 return m16_check_op (op, -0x80 << 3, 0x7f << 3, 7);
3285 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3287 return m16_check_op (op, -0x7f << 3, 0x80 << 3, 7);
3290 /* The cost of loading values from the constant pool. It should be
3291 larger than the cost of any constant we want to synthesize inline. */
3292 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3294 /* Return the cost of X when used as an operand to the MIPS16 instruction
3295 that implements CODE. Return -1 if there is no such instruction, or if
3296 X is not a valid immediate operand for it. */
3299 mips16_constant_cost (int code, HOST_WIDE_INT x)
3306 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3307 other shifts are extended. The shift patterns truncate the shift
3308 count to the right size, so there are no out-of-range values. */
3309 if (IN_RANGE (x, 1, 8))
3311 return COSTS_N_INSNS (1);
3314 if (IN_RANGE (x, -128, 127))
3316 if (SMALL_OPERAND (x))
3317 return COSTS_N_INSNS (1);
3321 /* Like LE, but reject the always-true case. */
3325 /* We add 1 to the immediate and use SLT. */
3328 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3331 if (IN_RANGE (x, 0, 255))
3333 if (SMALL_OPERAND_UNSIGNED (x))
3334 return COSTS_N_INSNS (1);
3339 /* Equality comparisons with 0 are cheap. */
3349 /* Return true if there is a non-MIPS16 instruction that implements CODE
3350 and if that instruction accepts X as an immediate operand. */
3353 mips_immediate_operand_p (int code, HOST_WIDE_INT x)
3360 /* All shift counts are truncated to a valid constant. */
3365 /* Likewise rotates, if the target supports rotates at all. */
3371 /* These instructions take 16-bit unsigned immediates. */
3372 return SMALL_OPERAND_UNSIGNED (x);
3377 /* These instructions take 16-bit signed immediates. */
3378 return SMALL_OPERAND (x);
3384 /* The "immediate" forms of these instructions are really
3385 implemented as comparisons with register 0. */
3390 /* Likewise, meaning that the only valid immediate operand is 1. */
3394 /* We add 1 to the immediate and use SLT. */
3395 return SMALL_OPERAND (x + 1);
3398 /* Likewise SLTU, but reject the always-true case. */
3399 return SMALL_OPERAND (x + 1) && x + 1 != 0;
3403 /* The bit position and size are immediate operands. */
3404 return ISA_HAS_EXT_INS;
3407 /* By default assume that $0 can be used for 0. */
3412 /* Return the cost of binary operation X, given that the instruction
3413 sequence for a word-sized or smaller operation has cost SINGLE_COST
3414 and that the sequence of a double-word operation has cost DOUBLE_COST.
3415 If SPEED is true, optimize for speed otherwise optimize for size. */
3418 mips_binary_cost (rtx x, int single_cost, int double_cost, bool speed)
3422 if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2)
3427 + set_src_cost (XEXP (x, 0), speed)
3428 + rtx_cost (XEXP (x, 1), GET_CODE (x), 1, speed));
3431 /* Return the cost of floating-point multiplications of mode MODE. */
3434 mips_fp_mult_cost (enum machine_mode mode)
3436 return mode == DFmode ? mips_cost->fp_mult_df : mips_cost->fp_mult_sf;
3439 /* Return the cost of floating-point divisions of mode MODE. */
3442 mips_fp_div_cost (enum machine_mode mode)
3444 return mode == DFmode ? mips_cost->fp_div_df : mips_cost->fp_div_sf;
3447 /* Return the cost of sign-extending OP to mode MODE, not including the
3448 cost of OP itself. */
3451 mips_sign_extend_cost (enum machine_mode mode, rtx op)
3454 /* Extended loads are as cheap as unextended ones. */
3457 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3458 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3461 if (ISA_HAS_SEB_SEH || GENERATE_MIPS16E)
3462 /* We can use SEB or SEH. */
3463 return COSTS_N_INSNS (1);
3465 /* We need to use a shift left and a shift right. */
3466 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3469 /* Return the cost of zero-extending OP to mode MODE, not including the
3470 cost of OP itself. */
3473 mips_zero_extend_cost (enum machine_mode mode, rtx op)
3476 /* Extended loads are as cheap as unextended ones. */
3479 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3480 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3481 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3483 if (GENERATE_MIPS16E)
3484 /* We can use ZEB or ZEH. */
3485 return COSTS_N_INSNS (1);
3488 /* We need to load 0xff or 0xffff into a register and use AND. */
3489 return COSTS_N_INSNS (GET_MODE (op) == QImode ? 2 : 3);
3491 /* We can use ANDI. */
3492 return COSTS_N_INSNS (1);
3495 /* Return the cost of moving between two registers of mode MODE,
3496 assuming that the move will be in pieces of at most UNITS bytes. */
3499 mips_set_reg_reg_piece_cost (enum machine_mode mode, unsigned int units)
3501 return COSTS_N_INSNS ((GET_MODE_SIZE (mode) + units - 1) / units);
3504 /* Return the cost of moving between two registers of mode MODE. */
3507 mips_set_reg_reg_cost (enum machine_mode mode)
3509 switch (GET_MODE_CLASS (mode))
3512 return mips_set_reg_reg_piece_cost (mode, GET_MODE_SIZE (CCmode));
3515 case MODE_COMPLEX_FLOAT:
3516 case MODE_VECTOR_FLOAT:
3517 if (TARGET_HARD_FLOAT)
3518 return mips_set_reg_reg_piece_cost (mode, UNITS_PER_HWFPVALUE);
3522 return mips_set_reg_reg_piece_cost (mode, UNITS_PER_WORD);
3526 /* Implement TARGET_RTX_COSTS. */
3529 mips_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
3530 int *total, bool speed)
3532 enum machine_mode mode = GET_MODE (x);
3533 bool float_mode_p = FLOAT_MODE_P (mode);
3537 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3538 appear in the instruction stream, and the cost of a comparison is
3539 really the cost of the branch or scc condition. At the time of
3540 writing, GCC only uses an explicit outer COMPARE code when optabs
3541 is testing whether a constant is expensive enough to force into a
3542 register. We want optabs to pass such constants through the MIPS
3543 expanders instead, so make all constants very cheap here. */
3544 if (outer_code == COMPARE)
3546 gcc_assert (CONSTANT_P (x));
3554 /* Treat *clear_upper32-style ANDs as having zero cost in the
3555 second operand. The cost is entirely in the first operand.
3557 ??? This is needed because we would otherwise try to CSE
3558 the constant operand. Although that's the right thing for
3559 instructions that continue to be a register operation throughout
3560 compilation, it is disastrous for instructions that could
3561 later be converted into a memory operation. */
3563 && outer_code == AND
3564 && UINTVAL (x) == 0xffffffff)
3572 cost = mips16_constant_cost (outer_code, INTVAL (x));
3581 /* When not optimizing for size, we care more about the cost
3582 of hot code, and hot code is often in a loop. If a constant
3583 operand needs to be forced into a register, we will often be
3584 able to hoist the constant load out of the loop, so the load
3585 should not contribute to the cost. */
3586 if (speed || mips_immediate_operand_p (outer_code, INTVAL (x)))
3598 if (force_to_mem_operand (x, VOIDmode))
3600 *total = COSTS_N_INSNS (1);
3603 cost = mips_const_insns (x);
3606 /* If the constant is likely to be stored in a GPR, SETs of
3607 single-insn constants are as cheap as register sets; we
3608 never want to CSE them.
3610 Don't reduce the cost of storing a floating-point zero in
3611 FPRs. If we have a zero in an FPR for other reasons, we
3612 can get better cfg-cleanup and delayed-branch results by
3613 using it consistently, rather than using $0 sometimes and
3614 an FPR at other times. Also, moves between floating-point
3615 registers are sometimes cheaper than (D)MTC1 $0. */
3617 && outer_code == SET
3618 && !(float_mode_p && TARGET_HARD_FLOAT))
3620 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3621 want to CSE the constant itself. It is usually better to
3622 have N copies of the last operation in the sequence and one
3623 shared copy of the other operations. (Note that this is
3624 not true for MIPS16 code, where the final operation in the
3625 sequence is often an extended instruction.)
3627 Also, if we have a CONST_INT, we don't know whether it is
3628 for a word or doubleword operation, so we cannot rely on
3629 the result of mips_build_integer. */
3630 else if (!TARGET_MIPS16
3631 && (outer_code == SET || mode == VOIDmode))
3633 *total = COSTS_N_INSNS (cost);
3636 /* The value will need to be fetched from the constant pool. */
3637 *total = CONSTANT_POOL_COST;
3641 /* If the address is legitimate, return the number of
3642 instructions it needs. */
3644 cost = mips_address_insns (addr, mode, true);
3647 *total = COSTS_N_INSNS (cost + 1);
3650 /* Check for a scaled indexed address. */
3651 if (mips_lwxs_address_p (addr)
3652 || mips_lx_address_p (addr, mode))
3654 *total = COSTS_N_INSNS (2);
3657 /* Otherwise use the default handling. */
3661 *total = COSTS_N_INSNS (6);
3665 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1);
3669 /* Check for a *clear_upper32 pattern and treat it like a zero
3670 extension. See the pattern's comment for details. */
3673 && CONST_INT_P (XEXP (x, 1))
3674 && UINTVAL (XEXP (x, 1)) == 0xffffffff)
3676 *total = (mips_zero_extend_cost (mode, XEXP (x, 0))
3677 + set_src_cost (XEXP (x, 0), speed));
3684 /* Double-word operations use two single-word operations. */
3685 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (2),
3694 if (CONSTANT_P (XEXP (x, 1)))
3695 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3698 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (12),
3704 *total = mips_cost->fp_add;
3706 *total = COSTS_N_INSNS (4);
3710 /* Low-part immediates need an extended MIPS16 instruction. */
3711 *total = (COSTS_N_INSNS (TARGET_MIPS16 ? 2 : 1)
3712 + set_src_cost (XEXP (x, 0), speed));
3727 /* Branch comparisons have VOIDmode, so use the first operand's
3729 mode = GET_MODE (XEXP (x, 0));
3730 if (FLOAT_MODE_P (mode))
3732 *total = mips_cost->fp_add;
3735 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3741 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3742 && TARGET_FUSED_MADD
3743 && !HONOR_NANS (mode)
3744 && !HONOR_SIGNED_ZEROS (mode))
3746 /* See if we can use NMADD or NMSUB. See mips.md for the
3747 associated patterns. */
3748 rtx op0 = XEXP (x, 0);
3749 rtx op1 = XEXP (x, 1);
3750 if (GET_CODE (op0) == MULT && GET_CODE (XEXP (op0, 0)) == NEG)
3752 *total = (mips_fp_mult_cost (mode)
3753 + set_src_cost (XEXP (XEXP (op0, 0), 0), speed)
3754 + set_src_cost (XEXP (op0, 1), speed)
3755 + set_src_cost (op1, speed));
3758 if (GET_CODE (op1) == MULT)
3760 *total = (mips_fp_mult_cost (mode)
3761 + set_src_cost (op0, speed)
3762 + set_src_cost (XEXP (op1, 0), speed)
3763 + set_src_cost (XEXP (op1, 1), speed));
3772 /* If this is part of a MADD or MSUB, treat the PLUS as
3775 && TARGET_FUSED_MADD
3776 && GET_CODE (XEXP (x, 0)) == MULT)
3779 *total = mips_cost->fp_add;
3783 /* Double-word operations require three single-word operations and
3784 an SLTU. The MIPS16 version then needs to move the result of
3785 the SLTU from $24 to a MIPS16 register. */
3786 *total = mips_binary_cost (x, COSTS_N_INSNS (1),
3787 COSTS_N_INSNS (TARGET_MIPS16 ? 5 : 4),
3793 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3794 && TARGET_FUSED_MADD
3795 && !HONOR_NANS (mode)
3796 && HONOR_SIGNED_ZEROS (mode))
3798 /* See if we can use NMADD or NMSUB. See mips.md for the
3799 associated patterns. */
3800 rtx op = XEXP (x, 0);
3801 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
3802 && GET_CODE (XEXP (op, 0)) == MULT)
3804 *total = (mips_fp_mult_cost (mode)
3805 + set_src_cost (XEXP (XEXP (op, 0), 0), speed)
3806 + set_src_cost (XEXP (XEXP (op, 0), 1), speed)
3807 + set_src_cost (XEXP (op, 1), speed));
3813 *total = mips_cost->fp_add;
3815 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1);
3820 *total = mips_fp_mult_cost (mode);
3821 else if (mode == DImode && !TARGET_64BIT)
3822 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
3823 where the mulsidi3 always includes an MFHI and an MFLO. */
3825 ? mips_cost->int_mult_si * 3 + 6
3826 : COSTS_N_INSNS (ISA_HAS_MUL3 ? 7 : 9));
3828 *total = (ISA_HAS_MUL3 ? 1 : 2);
3829 else if (mode == DImode)
3830 *total = mips_cost->int_mult_di;
3832 *total = mips_cost->int_mult_si;
3836 /* Check for a reciprocal. */
3839 && flag_unsafe_math_optimizations
3840 && XEXP (x, 0) == CONST1_RTX (mode))
3842 if (outer_code == SQRT || GET_CODE (XEXP (x, 1)) == SQRT)
3843 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
3844 division as being free. */
3845 *total = set_src_cost (XEXP (x, 1), speed);
3847 *total = (mips_fp_div_cost (mode)
3848 + set_src_cost (XEXP (x, 1), speed));
3857 *total = mips_fp_div_cost (mode);
3866 /* It is our responsibility to make division by a power of 2
3867 as cheap as 2 register additions if we want the division
3868 expanders to be used for such operations; see the setting
3869 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
3870 should always produce shorter code than using
3871 expand_sdiv2_pow2. */
3873 && CONST_INT_P (XEXP (x, 1))
3874 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
3876 *total = COSTS_N_INSNS (2) + set_src_cost (XEXP (x, 0), speed);
3879 *total = COSTS_N_INSNS (mips_idiv_insns ());
3881 else if (mode == DImode)
3882 *total = mips_cost->int_div_di;
3884 *total = mips_cost->int_div_si;
3888 *total = mips_sign_extend_cost (mode, XEXP (x, 0));
3892 if (outer_code == SET
3894 && (GET_CODE (XEXP (x, 0)) == TRUNCATE
3895 || GET_CODE (XEXP (x, 0)) == SUBREG)
3896 && GET_MODE (XEXP (x, 0)) == QImode
3897 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
3899 *total = set_src_cost (XEXP (XEXP (x, 0), 0), speed);
3902 *total = mips_zero_extend_cost (mode, XEXP (x, 0));
3906 case UNSIGNED_FLOAT:
3909 case FLOAT_TRUNCATE:
3910 *total = mips_cost->fp_add;
3914 if (register_operand (SET_DEST (x), VOIDmode)
3915 && reg_or_0_operand (SET_SRC (x), VOIDmode))
3917 *total = mips_set_reg_reg_cost (GET_MODE (SET_DEST (x)));
3927 /* Implement TARGET_ADDRESS_COST. */
3930 mips_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED)
3932 return mips_address_insns (addr, SImode, false);
3935 /* Information about a single instruction in a multi-instruction
3937 struct mips_multi_member {
3938 /* True if this is a label, false if it is code. */
3941 /* The output_asm_insn format of the instruction. */
3944 /* The operands to the instruction. */
3945 rtx operands[MAX_RECOG_OPERANDS];
3947 typedef struct mips_multi_member mips_multi_member;
3949 /* Vector definitions for the above. */
3950 DEF_VEC_O(mips_multi_member);
3951 DEF_VEC_ALLOC_O(mips_multi_member, heap);
3953 /* The instructions that make up the current multi-insn sequence. */
3954 static VEC (mips_multi_member, heap) *mips_multi_members;
3956 /* How many instructions (as opposed to labels) are in the current
3957 multi-insn sequence. */
3958 static unsigned int mips_multi_num_insns;
3960 /* Start a new multi-insn sequence. */
3963 mips_multi_start (void)
3965 VEC_truncate (mips_multi_member, mips_multi_members, 0);
3966 mips_multi_num_insns = 0;
3969 /* Add a new, uninitialized member to the current multi-insn sequence. */
3971 static struct mips_multi_member *
3972 mips_multi_add (void)
3974 return VEC_safe_push (mips_multi_member, heap, mips_multi_members, 0);
3977 /* Add a normal insn with the given asm format to the current multi-insn
3978 sequence. The other arguments are a null-terminated list of operands. */
3981 mips_multi_add_insn (const char *format, ...)
3983 struct mips_multi_member *member;
3988 member = mips_multi_add ();
3989 member->is_label_p = false;
3990 member->format = format;
3991 va_start (ap, format);
3993 while ((op = va_arg (ap, rtx)))
3994 member->operands[i++] = op;
3996 mips_multi_num_insns++;
3999 /* Add the given label definition to the current multi-insn sequence.
4000 The definition should include the colon. */
4003 mips_multi_add_label (const char *label)
4005 struct mips_multi_member *member;
4007 member = mips_multi_add ();
4008 member->is_label_p = true;
4009 member->format = label;
4012 /* Return the index of the last member of the current multi-insn sequence. */
4015 mips_multi_last_index (void)
4017 return VEC_length (mips_multi_member, mips_multi_members) - 1;
4020 /* Add a copy of an existing instruction to the current multi-insn
4021 sequence. I is the index of the instruction that should be copied. */
4024 mips_multi_copy_insn (unsigned int i)
4026 struct mips_multi_member *member;
4028 member = mips_multi_add ();
4029 memcpy (member, VEC_index (mips_multi_member, mips_multi_members, i),
4031 gcc_assert (!member->is_label_p);
4034 /* Change the operand of an existing instruction in the current
4035 multi-insn sequence. I is the index of the instruction,
4036 OP is the index of the operand, and X is the new value. */
4039 mips_multi_set_operand (unsigned int i, unsigned int op, rtx x)
4041 VEC_index (mips_multi_member, mips_multi_members, i)->operands[op] = x;
4044 /* Write out the asm code for the current multi-insn sequence. */
4047 mips_multi_write (void)
4049 struct mips_multi_member *member;
4052 FOR_EACH_VEC_ELT (mips_multi_member, mips_multi_members, i, member)
4053 if (member->is_label_p)
4054 fprintf (asm_out_file, "%s\n", member->format);
4056 output_asm_insn (member->format, member->operands);
4059 /* Return one word of double-word value OP, taking into account the fixed
4060 endianness of certain registers. HIGH_P is true to select the high part,
4061 false to select the low part. */
4064 mips_subword (rtx op, bool high_p)
4066 unsigned int byte, offset;
4067 enum machine_mode mode;
4069 mode = GET_MODE (op);
4070 if (mode == VOIDmode)
4071 mode = TARGET_64BIT ? TImode : DImode;
4073 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
4074 byte = UNITS_PER_WORD;
4078 if (FP_REG_RTX_P (op))
4080 /* Paired FPRs are always ordered little-endian. */
4081 offset = (UNITS_PER_WORD < UNITS_PER_HWFPVALUE ? high_p : byte != 0);
4082 return gen_rtx_REG (word_mode, REGNO (op) + offset);
4086 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
4088 return simplify_gen_subreg (word_mode, op, mode, byte);
4091 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
4094 mips_split_64bit_move_p (rtx dest, rtx src)
4099 /* FPR-to-FPR moves can be done in a single instruction, if they're
4101 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
4104 /* Check for floating-point loads and stores. */
4105 if (ISA_HAS_LDC1_SDC1)
4107 if (FP_REG_RTX_P (dest) && MEM_P (src))
4109 if (FP_REG_RTX_P (src) && MEM_P (dest))
4115 /* Split a doubleword move from SRC to DEST. On 32-bit targets,
4116 this function handles 64-bit moves for which mips_split_64bit_move_p
4117 holds. For 64-bit targets, this function handles 128-bit moves. */
4120 mips_split_doubleword_move (rtx dest, rtx src)
4124 if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src))
4126 if (!TARGET_64BIT && GET_MODE (dest) == DImode)
4127 emit_insn (gen_move_doubleword_fprdi (dest, src));
4128 else if (!TARGET_64BIT && GET_MODE (dest) == DFmode)
4129 emit_insn (gen_move_doubleword_fprdf (dest, src));
4130 else if (!TARGET_64BIT && GET_MODE (dest) == V2SFmode)
4131 emit_insn (gen_move_doubleword_fprv2sf (dest, src));
4132 else if (!TARGET_64BIT && GET_MODE (dest) == V2SImode)
4133 emit_insn (gen_move_doubleword_fprv2si (dest, src));
4134 else if (!TARGET_64BIT && GET_MODE (dest) == V4HImode)
4135 emit_insn (gen_move_doubleword_fprv4hi (dest, src));
4136 else if (!TARGET_64BIT && GET_MODE (dest) == V8QImode)
4137 emit_insn (gen_move_doubleword_fprv8qi (dest, src));
4138 else if (TARGET_64BIT && GET_MODE (dest) == TFmode)
4139 emit_insn (gen_move_doubleword_fprtf (dest, src));
4143 else if (REG_P (dest) && REGNO (dest) == MD_REG_FIRST)
4145 low_dest = mips_subword (dest, false);
4146 mips_emit_move (low_dest, mips_subword (src, false));
4148 emit_insn (gen_mthidi_ti (dest, mips_subword (src, true), low_dest));
4150 emit_insn (gen_mthisi_di (dest, mips_subword (src, true), low_dest));
4152 else if (REG_P (src) && REGNO (src) == MD_REG_FIRST)
4154 mips_emit_move (mips_subword (dest, false), mips_subword (src, false));
4156 emit_insn (gen_mfhidi_ti (mips_subword (dest, true), src));
4158 emit_insn (gen_mfhisi_di (mips_subword (dest, true), src));
4162 /* The operation can be split into two normal moves. Decide in
4163 which order to do them. */
4164 low_dest = mips_subword (dest, false);
4165 if (REG_P (low_dest)
4166 && reg_overlap_mentioned_p (low_dest, src))
4168 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4169 mips_emit_move (low_dest, mips_subword (src, false));
4173 mips_emit_move (low_dest, mips_subword (src, false));
4174 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4179 /* Return the appropriate instructions to move SRC into DEST. Assume
4180 that SRC is operand 1 and DEST is operand 0. */
4183 mips_output_move (rtx dest, rtx src)
4185 enum rtx_code dest_code, src_code;
4186 enum machine_mode mode;
4187 enum mips_symbol_type symbol_type;
4190 dest_code = GET_CODE (dest);
4191 src_code = GET_CODE (src);
4192 mode = GET_MODE (dest);
4193 dbl_p = (GET_MODE_SIZE (mode) == 8);
4195 if (dbl_p && mips_split_64bit_move_p (dest, src))
4198 if ((src_code == REG && GP_REG_P (REGNO (src)))
4199 || (!TARGET_MIPS16 && src == CONST0_RTX (mode)))
4201 if (dest_code == REG)
4203 if (GP_REG_P (REGNO (dest)))
4204 return "move\t%0,%z1";
4206 /* Moves to HI are handled by special .md insns. */
4207 if (REGNO (dest) == LO_REGNUM)
4210 if (DSP_ACC_REG_P (REGNO (dest)))
4212 static char retval[] = "mt__\t%z1,%q0";
4214 retval[2] = reg_names[REGNO (dest)][4];
4215 retval[3] = reg_names[REGNO (dest)][5];
4219 if (FP_REG_P (REGNO (dest)))
4220 return dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
4222 if (ALL_COP_REG_P (REGNO (dest)))
4224 static char retval[] = "dmtc_\t%z1,%0";
4226 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4227 return dbl_p ? retval : retval + 1;
4230 if (dest_code == MEM)
4231 switch (GET_MODE_SIZE (mode))
4233 case 1: return "sb\t%z1,%0";
4234 case 2: return "sh\t%z1,%0";
4235 case 4: return "sw\t%z1,%0";
4236 case 8: return "sd\t%z1,%0";
4239 if (dest_code == REG && GP_REG_P (REGNO (dest)))
4241 if (src_code == REG)
4243 /* Moves from HI are handled by special .md insns. */
4244 if (REGNO (src) == LO_REGNUM)
4246 /* When generating VR4120 or VR4130 code, we use MACC and
4247 DMACC instead of MFLO. This avoids both the normal
4248 MIPS III HI/LO hazards and the errata related to
4251 return dbl_p ? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
4255 if (DSP_ACC_REG_P (REGNO (src)))
4257 static char retval[] = "mf__\t%0,%q1";
4259 retval[2] = reg_names[REGNO (src)][4];
4260 retval[3] = reg_names[REGNO (src)][5];
4264 if (FP_REG_P (REGNO (src)))
4265 return dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
4267 if (ALL_COP_REG_P (REGNO (src)))
4269 static char retval[] = "dmfc_\t%0,%1";
4271 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4272 return dbl_p ? retval : retval + 1;
4275 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
4276 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
4279 if (src_code == MEM)
4280 switch (GET_MODE_SIZE (mode))
4282 case 1: return "lbu\t%0,%1";
4283 case 2: return "lhu\t%0,%1";
4284 case 4: return "lw\t%0,%1";
4285 case 8: return "ld\t%0,%1";
4288 if (src_code == CONST_INT)
4290 /* Don't use the X format for the operand itself, because that
4291 will give out-of-range numbers for 64-bit hosts and 32-bit
4294 return "li\t%0,%1\t\t\t# %X1";
4296 if (SMALL_OPERAND_UNSIGNED (INTVAL (src)))
4299 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src)))
4303 if (src_code == HIGH)
4304 return TARGET_MIPS16 ? "#" : "lui\t%0,%h1";
4306 if (CONST_GP_P (src))
4307 return "move\t%0,%1";
4309 if (mips_symbolic_constant_p (src, SYMBOL_CONTEXT_LEA, &symbol_type)
4310 && mips_lo_relocs[symbol_type] != 0)
4312 /* A signed 16-bit constant formed by applying a relocation
4313 operator to a symbolic address. */
4314 gcc_assert (!mips_split_p[symbol_type]);
4315 return "li\t%0,%R1";
4318 if (symbolic_operand (src, VOIDmode))
4320 gcc_assert (TARGET_MIPS16
4321 ? TARGET_MIPS16_TEXT_LOADS
4322 : !TARGET_EXPLICIT_RELOCS);
4323 return dbl_p ? "dla\t%0,%1" : "la\t%0,%1";
4326 if (src_code == REG && FP_REG_P (REGNO (src)))
4328 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4330 if (GET_MODE (dest) == V2SFmode)
4331 return "mov.ps\t%0,%1";
4333 return dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1";
4336 if (dest_code == MEM)
4337 return dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0";
4339 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4341 if (src_code == MEM)
4342 return dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1";
4344 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
4346 static char retval[] = "l_c_\t%0,%1";
4348 retval[1] = (dbl_p ? 'd' : 'w');
4349 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4352 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
4354 static char retval[] = "s_c_\t%1,%0";
4356 retval[1] = (dbl_p ? 'd' : 'w');
4357 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4363 /* Return true if CMP1 is a suitable second operand for integer ordering
4364 test CODE. See also the *sCC patterns in mips.md. */
4367 mips_int_order_operand_ok_p (enum rtx_code code, rtx cmp1)
4373 return reg_or_0_operand (cmp1, VOIDmode);
4377 return !TARGET_MIPS16 && cmp1 == const1_rtx;
4381 return arith_operand (cmp1, VOIDmode);
4384 return sle_operand (cmp1, VOIDmode);
4387 return sleu_operand (cmp1, VOIDmode);
4394 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4395 integer ordering test *CODE, or if an equivalent combination can
4396 be formed by adjusting *CODE and *CMP1. When returning true, update
4397 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4401 mips_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1,
4402 enum machine_mode mode)
4404 HOST_WIDE_INT plus_one;
4406 if (mips_int_order_operand_ok_p (*code, *cmp1))
4409 if (CONST_INT_P (*cmp1))
4413 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4414 if (INTVAL (*cmp1) < plus_one)
4417 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4423 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4427 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4438 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4439 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4440 is nonnull, it's OK to set TARGET to the inverse of the result and
4441 flip *INVERT_PTR instead. */
4444 mips_emit_int_order_test (enum rtx_code code, bool *invert_ptr,
4445 rtx target, rtx cmp0, rtx cmp1)
4447 enum machine_mode mode;
4449 /* First see if there is a MIPS instruction that can do this operation.
4450 If not, try doing the same for the inverse operation. If that also
4451 fails, force CMP1 into a register and try again. */
4452 mode = GET_MODE (cmp0);
4453 if (mips_canonicalize_int_order_test (&code, &cmp1, mode))
4454 mips_emit_binary (code, target, cmp0, cmp1);
4457 enum rtx_code inv_code = reverse_condition (code);
4458 if (!mips_canonicalize_int_order_test (&inv_code, &cmp1, mode))
4460 cmp1 = force_reg (mode, cmp1);
4461 mips_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1);
4463 else if (invert_ptr == 0)
4467 inv_target = mips_force_binary (GET_MODE (target),
4468 inv_code, cmp0, cmp1);
4469 mips_emit_binary (XOR, target, inv_target, const1_rtx);
4473 *invert_ptr = !*invert_ptr;
4474 mips_emit_binary (inv_code, target, cmp0, cmp1);
4479 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4480 The register will have the same mode as CMP0. */
4483 mips_zero_if_equal (rtx cmp0, rtx cmp1)
4485 if (cmp1 == const0_rtx)
4488 if (uns_arith_operand (cmp1, VOIDmode))
4489 return expand_binop (GET_MODE (cmp0), xor_optab,
4490 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4492 return expand_binop (GET_MODE (cmp0), sub_optab,
4493 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4496 /* Convert *CODE into a code that can be used in a floating-point
4497 scc instruction (C.cond.fmt). Return true if the values of
4498 the condition code registers will be inverted, with 0 indicating
4499 that the condition holds. */
4502 mips_reversed_fp_cond (enum rtx_code *code)
4509 *code = reverse_condition_maybe_unordered (*code);
4517 /* Convert a comparison into something that can be used in a branch or
4518 conditional move. On entry, *OP0 and *OP1 are the values being
4519 compared and *CODE is the code used to compare them.
4521 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
4522 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
4523 otherwise any standard branch condition can be used. The standard branch
4526 - EQ or NE between two registers.
4527 - any comparison between a register and zero. */
4530 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
4535 if (GET_MODE_CLASS (GET_MODE (*op0)) == MODE_INT)
4537 if (!need_eq_ne_p && *op1 == const0_rtx)
4539 else if (*code == EQ || *code == NE)
4543 *op0 = mips_zero_if_equal (cmp_op0, cmp_op1);
4547 *op1 = force_reg (GET_MODE (cmp_op0), cmp_op1);
4551 /* The comparison needs a separate scc instruction. Store the
4552 result of the scc in *OP0 and compare it against zero. */
4553 bool invert = false;
4554 *op0 = gen_reg_rtx (GET_MODE (cmp_op0));
4555 mips_emit_int_order_test (*code, &invert, *op0, cmp_op0, cmp_op1);
4556 *code = (invert ? EQ : NE);
4560 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0)))
4562 *op0 = gen_rtx_REG (CCDSPmode, CCDSP_CC_REGNUM);
4563 mips_emit_binary (*code, *op0, cmp_op0, cmp_op1);
4569 enum rtx_code cmp_code;
4571 /* Floating-point tests use a separate C.cond.fmt comparison to
4572 set a condition code register. The branch or conditional move
4573 will then compare that register against zero.
4575 Set CMP_CODE to the code of the comparison instruction and
4576 *CODE to the code that the branch or move should use. */
4578 *code = mips_reversed_fp_cond (&cmp_code) ? EQ : NE;
4580 ? gen_reg_rtx (CCmode)
4581 : gen_rtx_REG (CCmode, FPSW_REGNUM));
4583 mips_emit_binary (cmp_code, *op0, cmp_op0, cmp_op1);
4587 /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2]
4588 and OPERAND[3]. Store the result in OPERANDS[0].
4590 On 64-bit targets, the mode of the comparison and target will always be
4591 SImode, thus possibly narrower than that of the comparison's operands. */
4594 mips_expand_scc (rtx operands[])
4596 rtx target = operands[0];
4597 enum rtx_code code = GET_CODE (operands[1]);
4598 rtx op0 = operands[2];
4599 rtx op1 = operands[3];
4601 gcc_assert (GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT);
4603 if (code == EQ || code == NE)
4606 && reg_imm10_operand (op1, GET_MODE (op1)))
4607 mips_emit_binary (code, target, op0, op1);
4610 rtx zie = mips_zero_if_equal (op0, op1);
4611 mips_emit_binary (code, target, zie, const0_rtx);
4615 mips_emit_int_order_test (code, 0, target, op0, op1);
4618 /* Compare OPERANDS[1] with OPERANDS[2] using comparison code
4619 CODE and jump to OPERANDS[3] if the condition holds. */
4622 mips_expand_conditional_branch (rtx *operands)
4624 enum rtx_code code = GET_CODE (operands[0]);
4625 rtx op0 = operands[1];
4626 rtx op1 = operands[2];
4629 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
4630 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
4631 emit_jump_insn (gen_condjump (condition, operands[3]));
4636 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
4637 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
4640 mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
4641 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
4646 reversed_p = mips_reversed_fp_cond (&cond);
4647 cmp_result = gen_reg_rtx (CCV2mode);
4648 emit_insn (gen_scc_ps (cmp_result,
4649 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
4651 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
4654 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
4658 /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0]
4659 if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
4662 mips_expand_conditional_move (rtx *operands)
4665 enum rtx_code code = GET_CODE (operands[1]);
4666 rtx op0 = XEXP (operands[1], 0);
4667 rtx op1 = XEXP (operands[1], 1);
4669 mips_emit_compare (&code, &op0, &op1, true);
4670 cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
4671 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
4672 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), cond,
4673 operands[2], operands[3])));
4676 /* Perform the comparison in COMPARISON, then trap if the condition holds. */
4679 mips_expand_conditional_trap (rtx comparison)
4682 enum machine_mode mode;
4685 /* MIPS conditional trap instructions don't have GT or LE flavors,
4686 so we must swap the operands and convert to LT and GE respectively. */
4687 code = GET_CODE (comparison);
4694 code = swap_condition (code);
4695 op0 = XEXP (comparison, 1);
4696 op1 = XEXP (comparison, 0);
4700 op0 = XEXP (comparison, 0);
4701 op1 = XEXP (comparison, 1);
4705 mode = GET_MODE (XEXP (comparison, 0));
4706 op0 = force_reg (mode, op0);
4707 if (!arith_operand (op1, mode))
4708 op1 = force_reg (mode, op1);
4710 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
4711 gen_rtx_fmt_ee (code, mode, op0, op1),
4715 /* Initialize *CUM for a call to a function of type FNTYPE. */
4718 mips_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype)
4720 memset (cum, 0, sizeof (*cum));
4721 cum->prototype = (fntype && prototype_p (fntype));
4722 cum->gp_reg_found = (cum->prototype && stdarg_p (fntype));
4725 /* Fill INFO with information about a single argument. CUM is the
4726 cumulative state for earlier arguments. MODE is the mode of this
4727 argument and TYPE is its type (if known). NAMED is true if this
4728 is a named (fixed) argument rather than a variable one. */
4731 mips_get_arg_info (struct mips_arg_info *info, const CUMULATIVE_ARGS *cum,
4732 enum machine_mode mode, const_tree type, bool named)
4734 bool doubleword_aligned_p;
4735 unsigned int num_bytes, num_words, max_regs;
4737 /* Work out the size of the argument. */
4738 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
4739 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4741 /* Decide whether it should go in a floating-point register, assuming
4742 one is free. Later code checks for availability.
4744 The checks against UNITS_PER_FPVALUE handle the soft-float and
4745 single-float cases. */
4749 /* The EABI conventions have traditionally been defined in terms
4750 of TYPE_MODE, regardless of the actual type. */
4751 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
4752 || mode == V2SFmode)
4753 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4758 /* Only leading floating-point scalars are passed in
4759 floating-point registers. We also handle vector floats the same
4760 say, which is OK because they are not covered by the standard ABI. */
4761 info->fpr_p = (!cum->gp_reg_found
4762 && cum->arg_number < 2
4764 || SCALAR_FLOAT_TYPE_P (type)
4765 || VECTOR_FLOAT_TYPE_P (type))
4766 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4767 || mode == V2SFmode)
4768 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4773 /* Scalar, complex and vector floating-point types are passed in
4774 floating-point registers, as long as this is a named rather
4775 than a variable argument. */
4776 info->fpr_p = (named
4777 && (type == 0 || FLOAT_TYPE_P (type))
4778 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4779 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4780 || mode == V2SFmode)
4781 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
4783 /* ??? According to the ABI documentation, the real and imaginary
4784 parts of complex floats should be passed in individual registers.
4785 The real and imaginary parts of stack arguments are supposed
4786 to be contiguous and there should be an extra word of padding
4789 This has two problems. First, it makes it impossible to use a
4790 single "void *" va_list type, since register and stack arguments
4791 are passed differently. (At the time of writing, MIPSpro cannot
4792 handle complex float varargs correctly.) Second, it's unclear
4793 what should happen when there is only one register free.
4795 For now, we assume that named complex floats should go into FPRs
4796 if there are two FPRs free, otherwise they should be passed in the
4797 same way as a struct containing two floats. */
4799 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4800 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
4802 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
4803 info->fpr_p = false;
4813 /* See whether the argument has doubleword alignment. */
4814 doubleword_aligned_p = (mips_function_arg_boundary (mode, type)
4817 /* Set REG_OFFSET to the register count we're interested in.
4818 The EABI allocates the floating-point registers separately,
4819 but the other ABIs allocate them like integer registers. */
4820 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
4824 /* Advance to an even register if the argument is doubleword-aligned. */
4825 if (doubleword_aligned_p)
4826 info->reg_offset += info->reg_offset & 1;
4828 /* Work out the offset of a stack argument. */
4829 info->stack_offset = cum->stack_words;
4830 if (doubleword_aligned_p)
4831 info->stack_offset += info->stack_offset & 1;
4833 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
4835 /* Partition the argument between registers and stack. */
4836 info->reg_words = MIN (num_words, max_regs);
4837 info->stack_words = num_words - info->reg_words;
4840 /* INFO describes a register argument that has the normal format for the
4841 argument's mode. Return the register it uses, assuming that FPRs are
4842 available if HARD_FLOAT_P. */
4845 mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p)
4847 if (!info->fpr_p || !hard_float_p)
4848 return GP_ARG_FIRST + info->reg_offset;
4849 else if (mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info->reg_offset > 0)
4850 /* In o32, the second argument is always passed in $f14
4851 for TARGET_DOUBLE_FLOAT, regardless of whether the
4852 first argument was a word or doubleword. */
4853 return FP_ARG_FIRST + 2;
4855 return FP_ARG_FIRST + info->reg_offset;
4858 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
4861 mips_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED)
4863 return !TARGET_OLDABI;
4866 /* Implement TARGET_FUNCTION_ARG. */
4869 mips_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
4870 const_tree type, bool named)
4872 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
4873 struct mips_arg_info info;
4875 /* We will be called with a mode of VOIDmode after the last argument
4876 has been seen. Whatever we return will be passed to the call expander.
4877 If we need a MIPS16 fp_code, return a REG with the code stored as
4879 if (mode == VOIDmode)
4881 if (TARGET_MIPS16 && cum->fp_code != 0)
4882 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
4887 mips_get_arg_info (&info, cum, mode, type, named);
4889 /* Return straight away if the whole argument is passed on the stack. */
4890 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
4893 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
4894 contains a double in its entirety, then that 64-bit chunk is passed
4895 in a floating-point register. */
4897 && TARGET_HARD_FLOAT
4900 && TREE_CODE (type) == RECORD_TYPE
4901 && TYPE_SIZE_UNIT (type)
4902 && host_integerp (TYPE_SIZE_UNIT (type), 1))
4906 /* First check to see if there is any such field. */
4907 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
4908 if (TREE_CODE (field) == FIELD_DECL
4909 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
4910 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
4911 && host_integerp (bit_position (field), 0)
4912 && int_bit_position (field) % BITS_PER_WORD == 0)
4917 /* Now handle the special case by returning a PARALLEL
4918 indicating where each 64-bit chunk goes. INFO.REG_WORDS
4919 chunks are passed in registers. */
4921 HOST_WIDE_INT bitpos;
4924 /* assign_parms checks the mode of ENTRY_PARM, so we must
4925 use the actual mode here. */
4926 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
4929 field = TYPE_FIELDS (type);
4930 for (i = 0; i < info.reg_words; i++)
4934 for (; field; field = DECL_CHAIN (field))
4935 if (TREE_CODE (field) == FIELD_DECL
4936 && int_bit_position (field) >= bitpos)
4940 && int_bit_position (field) == bitpos
4941 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
4942 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
4943 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
4945 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
4948 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4949 GEN_INT (bitpos / BITS_PER_UNIT));
4951 bitpos += BITS_PER_WORD;
4957 /* Handle the n32/n64 conventions for passing complex floating-point
4958 arguments in FPR pairs. The real part goes in the lower register
4959 and the imaginary part goes in the upper register. */
4962 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4965 enum machine_mode inner;
4968 inner = GET_MODE_INNER (mode);
4969 regno = FP_ARG_FIRST + info.reg_offset;
4970 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
4972 /* Real part in registers, imaginary part on stack. */
4973 gcc_assert (info.stack_words == info.reg_words);
4974 return gen_rtx_REG (inner, regno);
4978 gcc_assert (info.stack_words == 0);
4979 real = gen_rtx_EXPR_LIST (VOIDmode,
4980 gen_rtx_REG (inner, regno),
4982 imag = gen_rtx_EXPR_LIST (VOIDmode,
4984 regno + info.reg_words / 2),
4985 GEN_INT (GET_MODE_SIZE (inner)));
4986 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
4990 return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT));
4993 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
4996 mips_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
4997 const_tree type, bool named)
4999 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
5000 struct mips_arg_info info;
5002 mips_get_arg_info (&info, cum, mode, type, named);
5005 cum->gp_reg_found = true;
5007 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
5008 an explanation of what this code does. It assumes that we're using
5009 either the o32 or the o64 ABI, both of which pass at most 2 arguments
5011 if (cum->arg_number < 2 && info.fpr_p)
5012 cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2);
5014 /* Advance the register count. This has the effect of setting
5015 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
5016 argument required us to skip the final GPR and pass the whole
5017 argument on the stack. */
5018 if (mips_abi != ABI_EABI || !info.fpr_p)
5019 cum->num_gprs = info.reg_offset + info.reg_words;
5020 else if (info.reg_words > 0)
5021 cum->num_fprs += MAX_FPRS_PER_FMT;
5023 /* Advance the stack word count. */
5024 if (info.stack_words > 0)
5025 cum->stack_words = info.stack_offset + info.stack_words;
5030 /* Implement TARGET_ARG_PARTIAL_BYTES. */
5033 mips_arg_partial_bytes (cumulative_args_t cum,
5034 enum machine_mode mode, tree type, bool named)
5036 struct mips_arg_info info;
5038 mips_get_arg_info (&info, get_cumulative_args (cum), mode, type, named);
5039 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
5042 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
5043 least PARM_BOUNDARY bits of alignment, but will be given anything up
5044 to STACK_BOUNDARY bits if the type requires it. */
5047 mips_function_arg_boundary (enum machine_mode mode, const_tree type)
5049 unsigned int alignment;
5051 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
5052 if (alignment < PARM_BOUNDARY)
5053 alignment = PARM_BOUNDARY;
5054 if (alignment > STACK_BOUNDARY)
5055 alignment = STACK_BOUNDARY;
5059 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
5060 upward rather than downward. In other words, return true if the
5061 first byte of the stack slot has useful data, false if the last
5065 mips_pad_arg_upward (enum machine_mode mode, const_tree type)
5067 /* On little-endian targets, the first byte of every stack argument
5068 is passed in the first byte of the stack slot. */
5069 if (!BYTES_BIG_ENDIAN)
5072 /* Otherwise, integral types are padded downward: the last byte of a
5073 stack argument is passed in the last byte of the stack slot. */
5075 ? (INTEGRAL_TYPE_P (type)
5076 || POINTER_TYPE_P (type)
5077 || FIXED_POINT_TYPE_P (type))
5078 : (SCALAR_INT_MODE_P (mode)
5079 || ALL_SCALAR_FIXED_POINT_MODE_P (mode)))
5082 /* Big-endian o64 pads floating-point arguments downward. */
5083 if (mips_abi == ABI_O64)
5084 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
5087 /* Other types are padded upward for o32, o64, n32 and n64. */
5088 if (mips_abi != ABI_EABI)
5091 /* Arguments smaller than a stack slot are padded downward. */
5092 if (mode != BLKmode)
5093 return GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY;
5095 return int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT);
5098 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
5099 if the least significant byte of the register has useful data. Return
5100 the opposite if the most significant byte does. */
5103 mips_pad_reg_upward (enum machine_mode mode, tree type)
5105 /* No shifting is required for floating-point arguments. */
5106 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
5107 return !BYTES_BIG_ENDIAN;
5109 /* Otherwise, apply the same padding to register arguments as we do
5110 to stack arguments. */
5111 return mips_pad_arg_upward (mode, type);
5114 /* Return nonzero when an argument must be passed by reference. */
5117 mips_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
5118 enum machine_mode mode, const_tree type,
5119 bool named ATTRIBUTE_UNUSED)
5121 if (mips_abi == ABI_EABI)
5125 /* ??? How should SCmode be handled? */
5126 if (mode == DImode || mode == DFmode
5127 || mode == DQmode || mode == UDQmode
5128 || mode == DAmode || mode == UDAmode)
5131 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
5132 return size == -1 || size > UNITS_PER_WORD;
5136 /* If we have a variable-sized parameter, we have no choice. */
5137 return targetm.calls.must_pass_in_stack (mode, type);
5141 /* Implement TARGET_CALLEE_COPIES. */
5144 mips_callee_copies (cumulative_args_t cum ATTRIBUTE_UNUSED,
5145 enum machine_mode mode ATTRIBUTE_UNUSED,
5146 const_tree type ATTRIBUTE_UNUSED, bool named)
5148 return mips_abi == ABI_EABI && named;
5151 /* See whether VALTYPE is a record whose fields should be returned in
5152 floating-point registers. If so, return the number of fields and
5153 list them in FIELDS (which should have two elements). Return 0
5156 For n32 & n64, a structure with one or two fields is returned in
5157 floating-point registers as long as every field has a floating-point
5161 mips_fpr_return_fields (const_tree valtype, tree *fields)
5169 if (TREE_CODE (valtype) != RECORD_TYPE)
5173 for (field = TYPE_FIELDS (valtype); field != 0; field = DECL_CHAIN (field))
5175 if (TREE_CODE (field) != FIELD_DECL)
5178 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)))
5184 fields[i++] = field;
5189 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
5190 a value in the most significant part of $2/$3 if:
5192 - the target is big-endian;
5194 - the value has a structure or union type (we generalize this to
5195 cover aggregates from other languages too); and
5197 - the structure is not returned in floating-point registers. */
5200 mips_return_in_msb (const_tree valtype)
5204 return (TARGET_NEWABI
5205 && TARGET_BIG_ENDIAN
5206 && AGGREGATE_TYPE_P (valtype)
5207 && mips_fpr_return_fields (valtype, fields) == 0);
5210 /* Return true if the function return value MODE will get returned in a
5211 floating-point register. */
5214 mips_return_mode_in_fpr_p (enum machine_mode mode)
5216 return ((GET_MODE_CLASS (mode) == MODE_FLOAT
5218 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5219 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE);
5222 /* Return the representation of an FPR return register when the
5223 value being returned in FP_RETURN has mode VALUE_MODE and the
5224 return type itself has mode TYPE_MODE. On NewABI targets,
5225 the two modes may be different for structures like:
5227 struct __attribute__((packed)) foo { float f; }
5229 where we return the SFmode value of "f" in FP_RETURN, but where
5230 the structure itself has mode BLKmode. */
5233 mips_return_fpr_single (enum machine_mode type_mode,
5234 enum machine_mode value_mode)
5238 x = gen_rtx_REG (value_mode, FP_RETURN);
5239 if (type_mode != value_mode)
5241 x = gen_rtx_EXPR_LIST (VOIDmode, x, const0_rtx);
5242 x = gen_rtx_PARALLEL (type_mode, gen_rtvec (1, x));
5247 /* Return a composite value in a pair of floating-point registers.
5248 MODE1 and OFFSET1 are the mode and byte offset for the first value,
5249 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
5252 For n32 & n64, $f0 always holds the first value and $f2 the second.
5253 Otherwise the values are packed together as closely as possible. */
5256 mips_return_fpr_pair (enum machine_mode mode,
5257 enum machine_mode mode1, HOST_WIDE_INT offset1,
5258 enum machine_mode mode2, HOST_WIDE_INT offset2)
5262 inc = (TARGET_NEWABI ? 2 : MAX_FPRS_PER_FMT);
5263 return gen_rtx_PARALLEL
5266 gen_rtx_EXPR_LIST (VOIDmode,
5267 gen_rtx_REG (mode1, FP_RETURN),
5269 gen_rtx_EXPR_LIST (VOIDmode,
5270 gen_rtx_REG (mode2, FP_RETURN + inc),
5271 GEN_INT (offset2))));
5275 /* Implement TARGET_FUNCTION_VALUE and TARGET_LIBCALL_VALUE.
5276 For normal calls, VALTYPE is the return type and MODE is VOIDmode.
5277 For libcalls, VALTYPE is null and MODE is the mode of the return value. */
5280 mips_function_value_1 (const_tree valtype, const_tree fn_decl_or_type,
5281 enum machine_mode mode)
5289 if (fn_decl_or_type && DECL_P (fn_decl_or_type))
5290 func = fn_decl_or_type;
5294 mode = TYPE_MODE (valtype);
5295 unsigned_p = TYPE_UNSIGNED (valtype);
5297 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
5298 return values, promote the mode here too. */
5299 mode = promote_function_mode (valtype, mode, &unsigned_p, func, 1);
5301 /* Handle structures whose fields are returned in $f0/$f2. */
5302 switch (mips_fpr_return_fields (valtype, fields))
5305 return mips_return_fpr_single (mode,
5306 TYPE_MODE (TREE_TYPE (fields[0])));
5309 return mips_return_fpr_pair (mode,
5310 TYPE_MODE (TREE_TYPE (fields[0])),
5311 int_byte_position (fields[0]),
5312 TYPE_MODE (TREE_TYPE (fields[1])),
5313 int_byte_position (fields[1]));
5316 /* If a value is passed in the most significant part of a register, see
5317 whether we have to round the mode up to a whole number of words. */
5318 if (mips_return_in_msb (valtype))
5320 HOST_WIDE_INT size = int_size_in_bytes (valtype);
5321 if (size % UNITS_PER_WORD != 0)
5323 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
5324 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
5328 /* For EABI, the class of return register depends entirely on MODE.
5329 For example, "struct { some_type x; }" and "union { some_type x; }"
5330 are returned in the same way as a bare "some_type" would be.
5331 Other ABIs only use FPRs for scalar, complex or vector types. */
5332 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
5333 return gen_rtx_REG (mode, GP_RETURN);
5338 /* Handle long doubles for n32 & n64. */
5340 return mips_return_fpr_pair (mode,
5342 DImode, GET_MODE_SIZE (mode) / 2);
5344 if (mips_return_mode_in_fpr_p (mode))
5346 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5347 return mips_return_fpr_pair (mode,
5348 GET_MODE_INNER (mode), 0,
5349 GET_MODE_INNER (mode),
5350 GET_MODE_SIZE (mode) / 2);
5352 return gen_rtx_REG (mode, FP_RETURN);
5356 return gen_rtx_REG (mode, GP_RETURN);
5359 /* Implement TARGET_FUNCTION_VALUE. */
5362 mips_function_value (const_tree valtype, const_tree fn_decl_or_type,
5363 bool outgoing ATTRIBUTE_UNUSED)
5365 return mips_function_value_1 (valtype, fn_decl_or_type, VOIDmode);
5368 /* Implement TARGET_LIBCALL_VALUE. */
5371 mips_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
5373 return mips_function_value_1 (NULL_TREE, NULL_TREE, mode);
5376 /* Implement TARGET_FUNCTION_VALUE_REGNO_P.
5378 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
5379 Currently, R2 and F0 are only implemented here (C has no complex type). */
5382 mips_function_value_regno_p (const unsigned int regno)
5384 if (regno == GP_RETURN
5385 || regno == FP_RETURN
5386 || (LONG_DOUBLE_TYPE_SIZE == 128
5387 && FP_RETURN != GP_RETURN
5388 && regno == FP_RETURN + 2))
5394 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
5395 all BLKmode objects are returned in memory. Under the n32, n64
5396 and embedded ABIs, small structures are returned in a register.
5397 Objects with varying size must still be returned in memory, of
5401 mips_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
5403 return (TARGET_OLDABI
5404 ? TYPE_MODE (type) == BLKmode
5405 : !IN_RANGE (int_size_in_bytes (type), 0, 2 * UNITS_PER_WORD));
5408 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
5411 mips_setup_incoming_varargs (cumulative_args_t cum, enum machine_mode mode,
5412 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5415 CUMULATIVE_ARGS local_cum;
5416 int gp_saved, fp_saved;
5418 /* The caller has advanced CUM up to, but not beyond, the last named
5419 argument. Advance a local copy of CUM past the last "real" named
5420 argument, to find out how many registers are left over. */
5421 local_cum = *get_cumulative_args (cum);
5422 mips_function_arg_advance (pack_cumulative_args (&local_cum), mode, type,
5425 /* Found out how many registers we need to save. */
5426 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
5427 fp_saved = (EABI_FLOAT_VARARGS_P
5428 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
5437 ptr = plus_constant (Pmode, virtual_incoming_args_rtx,
5438 REG_PARM_STACK_SPACE (cfun->decl)
5439 - gp_saved * UNITS_PER_WORD);
5440 mem = gen_frame_mem (BLKmode, ptr);
5441 set_mem_alias_set (mem, get_varargs_alias_set ());
5443 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
5448 /* We can't use move_block_from_reg, because it will use
5450 enum machine_mode mode;
5453 /* Set OFF to the offset from virtual_incoming_args_rtx of
5454 the first float register. The FP save area lies below
5455 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
5456 off = (-gp_saved * UNITS_PER_WORD) & -UNITS_PER_FPVALUE;
5457 off -= fp_saved * UNITS_PER_FPREG;
5459 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
5461 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS;
5462 i += MAX_FPRS_PER_FMT)
5466 ptr = plus_constant (Pmode, virtual_incoming_args_rtx, off);
5467 mem = gen_frame_mem (mode, ptr);
5468 set_mem_alias_set (mem, get_varargs_alias_set ());
5469 mips_emit_move (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
5470 off += UNITS_PER_HWFPVALUE;
5474 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
5475 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
5476 + fp_saved * UNITS_PER_FPREG);
5479 /* Implement TARGET_BUILTIN_VA_LIST. */
5482 mips_build_builtin_va_list (void)
5484 if (EABI_FLOAT_VARARGS_P)
5486 /* We keep 3 pointers, and two offsets.
5488 Two pointers are to the overflow area, which starts at the CFA.
5489 One of these is constant, for addressing into the GPR save area
5490 below it. The other is advanced up the stack through the
5493 The third pointer is to the bottom of the GPR save area.
5494 Since the FPR save area is just below it, we can address
5495 FPR slots off this pointer.
5497 We also keep two one-byte offsets, which are to be subtracted
5498 from the constant pointers to yield addresses in the GPR and
5499 FPR save areas. These are downcounted as float or non-float
5500 arguments are used, and when they get to zero, the argument
5501 must be obtained from the overflow region. */
5502 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
5505 record = lang_hooks.types.make_type (RECORD_TYPE);
5507 f_ovfl = build_decl (BUILTINS_LOCATION,
5508 FIELD_DECL, get_identifier ("__overflow_argptr"),
5510 f_gtop = build_decl (BUILTINS_LOCATION,
5511 FIELD_DECL, get_identifier ("__gpr_top"),
5513 f_ftop = build_decl (BUILTINS_LOCATION,
5514 FIELD_DECL, get_identifier ("__fpr_top"),
5516 f_goff = build_decl (BUILTINS_LOCATION,
5517 FIELD_DECL, get_identifier ("__gpr_offset"),
5518 unsigned_char_type_node);
5519 f_foff = build_decl (BUILTINS_LOCATION,
5520 FIELD_DECL, get_identifier ("__fpr_offset"),
5521 unsigned_char_type_node);
5522 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
5523 warn on every user file. */
5524 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
5525 array = build_array_type (unsigned_char_type_node,
5526 build_index_type (index));
5527 f_res = build_decl (BUILTINS_LOCATION,
5528 FIELD_DECL, get_identifier ("__reserved"), array);
5530 DECL_FIELD_CONTEXT (f_ovfl) = record;
5531 DECL_FIELD_CONTEXT (f_gtop) = record;
5532 DECL_FIELD_CONTEXT (f_ftop) = record;
5533 DECL_FIELD_CONTEXT (f_goff) = record;
5534 DECL_FIELD_CONTEXT (f_foff) = record;
5535 DECL_FIELD_CONTEXT (f_res) = record;
5537 TYPE_FIELDS (record) = f_ovfl;
5538 DECL_CHAIN (f_ovfl) = f_gtop;
5539 DECL_CHAIN (f_gtop) = f_ftop;
5540 DECL_CHAIN (f_ftop) = f_goff;
5541 DECL_CHAIN (f_goff) = f_foff;
5542 DECL_CHAIN (f_foff) = f_res;
5544 layout_type (record);
5548 /* Otherwise, we use 'void *'. */
5549 return ptr_type_node;
5552 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
5555 mips_va_start (tree valist, rtx nextarg)
5557 if (EABI_FLOAT_VARARGS_P)
5559 const CUMULATIVE_ARGS *cum;
5560 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5561 tree ovfl, gtop, ftop, goff, foff;
5563 int gpr_save_area_size;
5564 int fpr_save_area_size;
5567 cum = &crtl->args.info;
5569 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
5571 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
5573 f_ovfl = TYPE_FIELDS (va_list_type_node);
5574 f_gtop = DECL_CHAIN (f_ovfl);
5575 f_ftop = DECL_CHAIN (f_gtop);
5576 f_goff = DECL_CHAIN (f_ftop);
5577 f_foff = DECL_CHAIN (f_goff);
5579 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5581 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
5583 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
5585 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
5587 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
5590 /* Emit code to initialize OVFL, which points to the next varargs
5591 stack argument. CUM->STACK_WORDS gives the number of stack
5592 words used by named arguments. */
5593 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
5594 if (cum->stack_words > 0)
5595 t = fold_build_pointer_plus_hwi (t, cum->stack_words * UNITS_PER_WORD);
5596 t = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
5597 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5599 /* Emit code to initialize GTOP, the top of the GPR save area. */
5600 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
5601 t = build2 (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
5602 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5604 /* Emit code to initialize FTOP, the top of the FPR save area.
5605 This address is gpr_save_area_bytes below GTOP, rounded
5606 down to the next fp-aligned boundary. */
5607 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
5608 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
5609 fpr_offset &= -UNITS_PER_FPVALUE;
5611 t = fold_build_pointer_plus_hwi (t, -fpr_offset);
5612 t = build2 (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
5613 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5615 /* Emit code to initialize GOFF, the offset from GTOP of the
5616 next GPR argument. */
5617 t = build2 (MODIFY_EXPR, TREE_TYPE (goff), goff,
5618 build_int_cst (TREE_TYPE (goff), gpr_save_area_size));
5619 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5621 /* Likewise emit code to initialize FOFF, the offset from FTOP
5622 of the next FPR argument. */
5623 t = build2 (MODIFY_EXPR, TREE_TYPE (foff), foff,
5624 build_int_cst (TREE_TYPE (foff), fpr_save_area_size));
5625 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5629 nextarg = plus_constant (Pmode, nextarg, -cfun->machine->varargs_size);
5630 std_expand_builtin_va_start (valist, nextarg);
5634 /* Like std_gimplify_va_arg_expr, but apply alignment to zero-sized
5638 mips_std_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
5641 tree addr, t, type_size, rounded_size, valist_tmp;
5642 unsigned HOST_WIDE_INT align, boundary;
5645 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, false);
5647 type = build_pointer_type (type);
5649 align = PARM_BOUNDARY / BITS_PER_UNIT;
5650 boundary = targetm.calls.function_arg_boundary (TYPE_MODE (type), type);
5652 /* When we align parameter on stack for caller, if the parameter
5653 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
5654 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
5655 here with caller. */
5656 if (boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
5657 boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
5659 boundary /= BITS_PER_UNIT;
5661 /* Hoist the valist value into a temporary for the moment. */
5662 valist_tmp = get_initialized_tmp_var (valist, pre_p, NULL);
5664 /* va_list pointer is aligned to PARM_BOUNDARY. If argument actually
5665 requires greater alignment, we must perform dynamic alignment. */
5666 if (boundary > align)
5668 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
5669 fold_build_pointer_plus_hwi (valist_tmp, boundary - 1));
5670 gimplify_and_add (t, pre_p);
5672 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
5673 fold_build2 (BIT_AND_EXPR, TREE_TYPE (valist),
5675 build_int_cst (TREE_TYPE (valist), -boundary)));
5676 gimplify_and_add (t, pre_p);
5681 /* If the actual alignment is less than the alignment of the type,
5682 adjust the type accordingly so that we don't assume strict alignment
5683 when dereferencing the pointer. */
5684 boundary *= BITS_PER_UNIT;
5685 if (boundary < TYPE_ALIGN (type))
5687 type = build_variant_type_copy (type);
5688 TYPE_ALIGN (type) = boundary;
5691 /* Compute the rounded size of the type. */
5692 type_size = size_in_bytes (type);
5693 rounded_size = round_up (type_size, align);
5695 /* Reduce rounded_size so it's sharable with the postqueue. */
5696 gimplify_expr (&rounded_size, pre_p, post_p, is_gimple_val, fb_rvalue);
5700 if (PAD_VARARGS_DOWN && !integer_zerop (rounded_size))
5702 /* Small args are padded downward. */
5703 t = fold_build2_loc (input_location, GT_EXPR, sizetype,
5704 rounded_size, size_int (align));
5705 t = fold_build3 (COND_EXPR, sizetype, t, size_zero_node,
5706 size_binop (MINUS_EXPR, rounded_size, type_size));
5707 addr = fold_build_pointer_plus (addr, t);
5710 /* Compute new value for AP. */
5711 t = fold_build_pointer_plus (valist_tmp, rounded_size);
5712 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
5713 gimplify_and_add (t, pre_p);
5715 addr = fold_convert (build_pointer_type (type), addr);
5718 addr = build_va_arg_indirect_ref (addr);
5720 return build_va_arg_indirect_ref (addr);
5723 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
5726 mips_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
5732 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
5734 type = build_pointer_type (type);
5736 if (!EABI_FLOAT_VARARGS_P)
5737 addr = mips_std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5740 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5741 tree ovfl, top, off, align;
5742 HOST_WIDE_INT size, rsize, osize;
5745 f_ovfl = TYPE_FIELDS (va_list_type_node);
5746 f_gtop = DECL_CHAIN (f_ovfl);
5747 f_ftop = DECL_CHAIN (f_gtop);
5748 f_goff = DECL_CHAIN (f_ftop);
5749 f_foff = DECL_CHAIN (f_goff);
5753 TOP be the top of the GPR or FPR save area;
5754 OFF be the offset from TOP of the next register;
5755 ADDR_RTX be the address of the argument;
5756 SIZE be the number of bytes in the argument type;
5757 RSIZE be the number of bytes used to store the argument
5758 when it's in the register save area; and
5759 OSIZE be the number of bytes used to store it when it's
5760 in the stack overflow area.
5762 The code we want is:
5764 1: off &= -rsize; // round down
5767 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
5772 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
5773 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
5777 [1] and [9] can sometimes be optimized away. */
5779 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5781 size = int_size_in_bytes (type);
5783 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
5784 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
5786 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop),
5787 unshare_expr (valist), f_ftop, NULL_TREE);
5788 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff),
5789 unshare_expr (valist), f_foff, NULL_TREE);
5791 /* When va_start saves FPR arguments to the stack, each slot
5792 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
5793 argument's precision. */
5794 rsize = UNITS_PER_HWFPVALUE;
5796 /* Overflow arguments are padded to UNITS_PER_WORD bytes
5797 (= PARM_BOUNDARY bits). This can be different from RSIZE
5800 (1) On 32-bit targets when TYPE is a structure such as:
5802 struct s { float f; };
5804 Such structures are passed in paired FPRs, so RSIZE
5805 will be 8 bytes. However, the structure only takes
5806 up 4 bytes of memory, so OSIZE will only be 4.
5808 (2) In combinations such as -mgp64 -msingle-float
5809 -fshort-double. Doubles passed in registers will then take
5810 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
5811 stack take up UNITS_PER_WORD bytes. */
5812 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
5816 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop),
5817 unshare_expr (valist), f_gtop, NULL_TREE);
5818 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff),
5819 unshare_expr (valist), f_goff, NULL_TREE);
5820 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
5821 if (rsize > UNITS_PER_WORD)
5823 /* [1] Emit code for: off &= -rsize. */
5824 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), unshare_expr (off),
5825 build_int_cst (TREE_TYPE (off), -rsize));
5826 gimplify_assign (unshare_expr (off), t, pre_p);
5831 /* [2] Emit code to branch if off == 0. */
5832 t = build2 (NE_EXPR, boolean_type_node, unshare_expr (off),
5833 build_int_cst (TREE_TYPE (off), 0));
5834 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
5836 /* [5] Emit code for: off -= rsize. We do this as a form of
5837 post-decrement not available to C. */
5838 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
5839 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
5841 /* [4] Emit code for:
5842 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
5843 t = fold_convert (sizetype, t);
5844 t = fold_build1 (NEGATE_EXPR, sizetype, t);
5845 t = fold_build_pointer_plus (top, t);
5846 if (BYTES_BIG_ENDIAN && rsize > size)
5847 t = fold_build_pointer_plus_hwi (t, rsize - size);
5848 COND_EXPR_THEN (addr) = t;
5850 if (osize > UNITS_PER_WORD)
5852 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
5853 t = fold_build_pointer_plus_hwi (unshare_expr (ovfl), osize - 1);
5854 u = build_int_cst (TREE_TYPE (t), -osize);
5855 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t, u);
5856 align = build2 (MODIFY_EXPR, TREE_TYPE (ovfl),
5857 unshare_expr (ovfl), t);
5862 /* [10, 11] Emit code for:
5863 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
5865 u = fold_convert (TREE_TYPE (ovfl), build_int_cst (NULL_TREE, osize));
5866 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
5867 if (BYTES_BIG_ENDIAN && osize > size)
5868 t = fold_build_pointer_plus_hwi (t, osize - size);
5870 /* String [9] and [10, 11] together. */
5872 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
5873 COND_EXPR_ELSE (addr) = t;
5875 addr = fold_convert (build_pointer_type (type), addr);
5876 addr = build_va_arg_indirect_ref (addr);
5880 addr = build_va_arg_indirect_ref (addr);
5885 /* Declare a unique, locally-binding function called NAME, then start
5889 mips_start_unique_function (const char *name)
5893 decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
5894 get_identifier (name),
5895 build_function_type_list (void_type_node, NULL_TREE));
5896 DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
5897 NULL_TREE, void_type_node);
5898 TREE_PUBLIC (decl) = 1;
5899 TREE_STATIC (decl) = 1;
5901 DECL_COMDAT_GROUP (decl) = DECL_ASSEMBLER_NAME (decl);
5903 targetm.asm_out.unique_section (decl, 0);
5904 switch_to_section (get_named_section (decl, NULL, 0));
5906 targetm.asm_out.globalize_label (asm_out_file, name);
5907 fputs ("\t.hidden\t", asm_out_file);
5908 assemble_name (asm_out_file, name);
5909 putc ('\n', asm_out_file);
5912 /* Start a definition of function NAME. MIPS16_P indicates whether the
5913 function contains MIPS16 code. */
5916 mips_start_function_definition (const char *name, bool mips16_p)
5919 fprintf (asm_out_file, "\t.set\tmips16\n");
5921 fprintf (asm_out_file, "\t.set\tnomips16\n");
5923 if (!flag_inhibit_size_directive)
5925 fputs ("\t.ent\t", asm_out_file);
5926 assemble_name (asm_out_file, name);
5927 fputs ("\n", asm_out_file);
5930 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, name, "function");
5932 /* Start the definition proper. */
5933 assemble_name (asm_out_file, name);
5934 fputs (":\n", asm_out_file);
5937 /* End a function definition started by mips_start_function_definition. */
5940 mips_end_function_definition (const char *name)
5942 if (!flag_inhibit_size_directive)
5944 fputs ("\t.end\t", asm_out_file);
5945 assemble_name (asm_out_file, name);
5946 fputs ("\n", asm_out_file);
5950 /* Output a definition of the __mips16_rdhwr function. */
5953 mips_output_mips16_rdhwr (void)
5957 name = "__mips16_rdhwr";
5958 mips_start_unique_function (name);
5959 mips_start_function_definition (name, false);
5960 fprintf (asm_out_file,
5962 "\t.set\tmips32r2\n"
5963 "\t.set\tnoreorder\n"
5967 mips_end_function_definition (name);
5970 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
5973 mips_ok_for_lazy_binding_p (rtx x)
5975 return (TARGET_USE_GOT
5976 && GET_CODE (x) == SYMBOL_REF
5977 && !SYMBOL_REF_BIND_NOW_P (x)
5978 && !mips_symbol_binds_local_p (x));
5981 /* Load function address ADDR into register DEST. TYPE is as for
5982 mips_expand_call. Return true if we used an explicit lazy-binding
5986 mips_load_call_address (enum mips_call_type type, rtx dest, rtx addr)
5988 /* If we're generating PIC, and this call is to a global function,
5989 try to allow its address to be resolved lazily. This isn't
5990 possible for sibcalls when $gp is call-saved because the value
5991 of $gp on entry to the stub would be our caller's gp, not ours. */
5992 if (TARGET_EXPLICIT_RELOCS
5993 && !(type == MIPS_CALL_SIBCALL && TARGET_CALL_SAVED_GP)
5994 && mips_ok_for_lazy_binding_p (addr))
5996 addr = mips_got_load (dest, addr, SYMBOL_GOTOFF_CALL);
5997 emit_insn (gen_rtx_SET (VOIDmode, dest, addr));
6002 mips_emit_move (dest, addr);
6007 /* Each locally-defined hard-float MIPS16 function has a local symbol
6008 associated with it. This hash table maps the function symbol (FUNC)
6009 to the local symbol (LOCAL). */
6010 struct GTY(()) mips16_local_alias {
6014 static GTY ((param_is (struct mips16_local_alias))) htab_t mips16_local_aliases;
6016 /* Hash table callbacks for mips16_local_aliases. */
6019 mips16_local_aliases_hash (const void *entry)
6021 const struct mips16_local_alias *alias;
6023 alias = (const struct mips16_local_alias *) entry;
6024 return htab_hash_string (XSTR (alias->func, 0));
6028 mips16_local_aliases_eq (const void *entry1, const void *entry2)
6030 const struct mips16_local_alias *alias1, *alias2;
6032 alias1 = (const struct mips16_local_alias *) entry1;
6033 alias2 = (const struct mips16_local_alias *) entry2;
6034 return rtx_equal_p (alias1->func, alias2->func);
6037 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
6038 Return a local alias for it, creating a new one if necessary. */
6041 mips16_local_alias (rtx func)
6043 struct mips16_local_alias *alias, tmp_alias;
6046 /* Create the hash table if this is the first call. */
6047 if (mips16_local_aliases == NULL)
6048 mips16_local_aliases = htab_create_ggc (37, mips16_local_aliases_hash,
6049 mips16_local_aliases_eq, NULL);
6051 /* Look up the function symbol, creating a new entry if need be. */
6052 tmp_alias.func = func;
6053 slot = htab_find_slot (mips16_local_aliases, &tmp_alias, INSERT);
6054 gcc_assert (slot != NULL);
6056 alias = (struct mips16_local_alias *) *slot;
6059 const char *func_name, *local_name;
6062 /* Create a new SYMBOL_REF for the local symbol. The choice of
6063 __fn_local_* is based on the __fn_stub_* names that we've
6064 traditionally used for the non-MIPS16 stub. */
6065 func_name = targetm.strip_name_encoding (XSTR (func, 0));
6066 local_name = ACONCAT (("__fn_local_", func_name, NULL));
6067 local = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (local_name));
6068 SYMBOL_REF_FLAGS (local) = SYMBOL_REF_FLAGS (func) | SYMBOL_FLAG_LOCAL;
6070 /* Create a new structure to represent the mapping. */
6071 alias = ggc_alloc_mips16_local_alias ();
6073 alias->local = local;
6076 return alias->local;
6079 /* A chained list of functions for which mips16_build_call_stub has already
6080 generated a stub. NAME is the name of the function and FP_RET_P is true
6081 if the function returns a value in floating-point registers. */
6082 struct mips16_stub {
6083 struct mips16_stub *next;
6087 static struct mips16_stub *mips16_stubs;
6089 /* Return the two-character string that identifies floating-point
6090 return mode MODE in the name of a MIPS16 function stub. */
6093 mips16_call_stub_mode_suffix (enum machine_mode mode)
6097 else if (mode == DFmode)
6099 else if (mode == SCmode)
6101 else if (mode == DCmode)
6103 else if (mode == V2SFmode)
6109 /* Write instructions to move a 32-bit value between general register
6110 GPREG and floating-point register FPREG. DIRECTION is 't' to move
6111 from GPREG to FPREG and 'f' to move in the opposite direction. */
6114 mips_output_32bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
6116 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6117 reg_names[gpreg], reg_names[fpreg]);
6120 /* Likewise for 64-bit values. */
6123 mips_output_64bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
6126 fprintf (asm_out_file, "\tdm%cc1\t%s,%s\n", direction,
6127 reg_names[gpreg], reg_names[fpreg]);
6128 else if (TARGET_FLOAT64)
6130 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6131 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
6132 fprintf (asm_out_file, "\tm%chc1\t%s,%s\n", direction,
6133 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg]);
6137 /* Move the least-significant word. */
6138 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6139 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
6140 /* ...then the most significant word. */
6141 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6142 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg + 1]);
6146 /* Write out code to move floating-point arguments into or out of
6147 general registers. FP_CODE is the code describing which arguments
6148 are present (see the comment above the definition of CUMULATIVE_ARGS
6149 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
6152 mips_output_args_xfer (int fp_code, char direction)
6154 unsigned int gparg, fparg, f;
6155 CUMULATIVE_ARGS cum;
6157 /* This code only works for o32 and o64. */
6158 gcc_assert (TARGET_OLDABI);
6160 mips_init_cumulative_args (&cum, NULL);
6162 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
6164 enum machine_mode mode;
6165 struct mips_arg_info info;
6169 else if ((f & 3) == 2)
6174 mips_get_arg_info (&info, &cum, mode, NULL, true);
6175 gparg = mips_arg_regno (&info, false);
6176 fparg = mips_arg_regno (&info, true);
6179 mips_output_32bit_xfer (direction, gparg, fparg);
6181 mips_output_64bit_xfer (direction, gparg, fparg);
6183 mips_function_arg_advance (pack_cumulative_args (&cum), mode, NULL, true);
6187 /* Write a MIPS16 stub for the current function. This stub is used
6188 for functions which take arguments in the floating-point registers.
6189 It is normal-mode code that moves the floating-point arguments
6190 into the general registers and then jumps to the MIPS16 code. */
6193 mips16_build_function_stub (void)
6195 const char *fnname, *alias_name, *separator;
6196 char *secname, *stubname;
6201 /* Create the name of the stub, and its unique section. */
6202 symbol = XEXP (DECL_RTL (current_function_decl), 0);
6203 alias = mips16_local_alias (symbol);
6205 fnname = targetm.strip_name_encoding (XSTR (symbol, 0));
6206 alias_name = targetm.strip_name_encoding (XSTR (alias, 0));
6207 secname = ACONCAT ((".mips16.fn.", fnname, NULL));
6208 stubname = ACONCAT (("__fn_stub_", fnname, NULL));
6210 /* Build a decl for the stub. */
6211 stubdecl = build_decl (BUILTINS_LOCATION,
6212 FUNCTION_DECL, get_identifier (stubname),
6213 build_function_type_list (void_type_node, NULL_TREE));
6214 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
6215 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
6216 RESULT_DECL, NULL_TREE, void_type_node);
6218 /* Output a comment. */
6219 fprintf (asm_out_file, "\t# Stub function for %s (",
6220 current_function_name ());
6222 for (f = (unsigned int) crtl->args.info.fp_code; f != 0; f >>= 2)
6224 fprintf (asm_out_file, "%s%s", separator,
6225 (f & 3) == 1 ? "float" : "double");
6228 fprintf (asm_out_file, ")\n");
6230 /* Start the function definition. */
6231 assemble_start_function (stubdecl, stubname);
6232 mips_start_function_definition (stubname, false);
6234 /* If generating pic2 code, either set up the global pointer or
6236 if (TARGET_ABICALLS_PIC2)
6238 if (TARGET_ABSOLUTE_ABICALLS)
6239 fprintf (asm_out_file, "\t.option\tpic0\n");
6242 output_asm_insn ("%(.cpload\t%^%)", NULL);
6243 /* Emit an R_MIPS_NONE relocation to tell the linker what the
6244 target function is. Use a local GOT access when loading the
6245 symbol, to cut down on the number of unnecessary GOT entries
6246 for stubs that aren't needed. */
6247 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol);
6252 /* Load the address of the MIPS16 function into $25. Do this first so
6253 that targets with coprocessor interlocks can use an MFC1 to fill the
6255 output_asm_insn ("la\t%^,%0", &symbol);
6257 /* Move the arguments from floating-point registers to general registers. */
6258 mips_output_args_xfer (crtl->args.info.fp_code, 'f');
6260 /* Jump to the MIPS16 function. */
6261 output_asm_insn ("jr\t%^", NULL);
6263 if (TARGET_ABICALLS_PIC2 && TARGET_ABSOLUTE_ABICALLS)
6264 fprintf (asm_out_file, "\t.option\tpic2\n");
6266 mips_end_function_definition (stubname);
6268 /* If the linker needs to create a dynamic symbol for the target
6269 function, it will associate the symbol with the stub (which,
6270 unlike the target function, follows the proper calling conventions).
6271 It is therefore useful to have a local alias for the target function,
6272 so that it can still be identified as MIPS16 code. As an optimization,
6273 this symbol can also be used for indirect MIPS16 references from
6274 within this file. */
6275 ASM_OUTPUT_DEF (asm_out_file, alias_name, fnname);
6277 switch_to_section (function_section (current_function_decl));
6280 /* The current function is a MIPS16 function that returns a value in an FPR.
6281 Copy the return value from its soft-float to its hard-float location.
6282 libgcc2 has special non-MIPS16 helper functions for each case. */
6285 mips16_copy_fpr_return_value (void)
6287 rtx fn, insn, retval;
6289 enum machine_mode return_mode;
6292 return_type = DECL_RESULT (current_function_decl);
6293 return_mode = DECL_MODE (return_type);
6295 name = ACONCAT (("__mips16_ret_",
6296 mips16_call_stub_mode_suffix (return_mode),
6298 fn = mips16_stub_function (name);
6300 /* The function takes arguments in $2 (and possibly $3), so calls
6301 to it cannot be lazily bound. */
6302 SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_BIND_NOW;
6304 /* Model the call as something that takes the GPR return value as
6305 argument and returns an "updated" value. */
6306 retval = gen_rtx_REG (return_mode, GP_RETURN);
6307 insn = mips_expand_call (MIPS_CALL_EPILOGUE, retval, fn,
6308 const0_rtx, NULL_RTX, false);
6309 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), retval);
6312 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
6313 RETVAL is the location of the return value, or null if this is
6314 a "call" rather than a "call_value". ARGS_SIZE is the size of the
6315 arguments and FP_CODE is the code built by mips_function_arg;
6316 see the comment before the fp_code field in CUMULATIVE_ARGS for details.
6318 There are three alternatives:
6320 - If a stub was needed, emit the call and return the call insn itself.
6322 - If we can avoid using a stub by redirecting the call, set *FN_PTR
6323 to the new target and return null.
6325 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
6328 A stub is needed for calls to functions that, in normal mode,
6329 receive arguments in FPRs or return values in FPRs. The stub
6330 copies the arguments from their soft-float positions to their
6331 hard-float positions, calls the real function, then copies the
6332 return value from its hard-float position to its soft-float
6335 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
6336 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
6337 automatically redirects the JAL to the stub, otherwise the JAL
6338 continues to call FN directly. */
6341 mips16_build_call_stub (rtx retval, rtx *fn_ptr, rtx args_size, int fp_code)
6345 struct mips16_stub *l;
6348 /* We don't need to do anything if we aren't in MIPS16 mode, or if
6349 we were invoked with the -msoft-float option. */
6350 if (!TARGET_MIPS16 || TARGET_SOFT_FLOAT_ABI)
6353 /* Figure out whether the value might come back in a floating-point
6355 fp_ret_p = retval && mips_return_mode_in_fpr_p (GET_MODE (retval));
6357 /* We don't need to do anything if there were no floating-point
6358 arguments and the value will not be returned in a floating-point
6360 if (fp_code == 0 && !fp_ret_p)
6363 /* We don't need to do anything if this is a call to a special
6364 MIPS16 support function. */
6366 if (mips16_stub_function_p (fn))
6369 /* If we're calling a locally-defined MIPS16 function, we know that
6370 it will return values in both the "soft-float" and "hard-float"
6371 registers. There is no need to use a stub to move the latter
6373 if (fp_code == 0 && mips16_local_function_p (fn))
6376 /* This code will only work for o32 and o64 abis. The other ABI's
6377 require more sophisticated support. */
6378 gcc_assert (TARGET_OLDABI);
6380 /* If we're calling via a function pointer, use one of the magic
6381 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
6382 Each stub expects the function address to arrive in register $2. */
6383 if (GET_CODE (fn) != SYMBOL_REF
6384 || !call_insn_operand (fn, VOIDmode))
6387 rtx stub_fn, insn, addr;
6390 /* If this is a locally-defined and locally-binding function,
6391 avoid the stub by calling the local alias directly. */
6392 if (mips16_local_function_p (fn))
6394 *fn_ptr = mips16_local_alias (fn);
6398 /* Create a SYMBOL_REF for the libgcc.a function. */
6400 sprintf (buf, "__mips16_call_stub_%s_%d",
6401 mips16_call_stub_mode_suffix (GET_MODE (retval)),
6404 sprintf (buf, "__mips16_call_stub_%d", fp_code);
6405 stub_fn = mips16_stub_function (buf);
6407 /* The function uses $2 as an argument, so calls to it
6408 cannot be lazily bound. */
6409 SYMBOL_REF_FLAGS (stub_fn) |= SYMBOL_FLAG_BIND_NOW;
6411 /* Load the target function into $2. */
6412 addr = gen_rtx_REG (Pmode, GP_REG_FIRST + 2);
6413 lazy_p = mips_load_call_address (MIPS_CALL_NORMAL, addr, fn);
6415 /* Emit the call. */
6416 insn = mips_expand_call (MIPS_CALL_NORMAL, retval, stub_fn,
6417 args_size, NULL_RTX, lazy_p);
6419 /* Tell GCC that this call does indeed use the value of $2. */
6420 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), addr);
6422 /* If we are handling a floating-point return value, we need to
6423 save $18 in the function prologue. Putting a note on the
6424 call will mean that df_regs_ever_live_p ($18) will be true if the
6425 call is not eliminated, and we can check that in the prologue
6428 CALL_INSN_FUNCTION_USAGE (insn) =
6429 gen_rtx_EXPR_LIST (VOIDmode,
6430 gen_rtx_CLOBBER (VOIDmode,
6431 gen_rtx_REG (word_mode, 18)),
6432 CALL_INSN_FUNCTION_USAGE (insn));
6437 /* We know the function we are going to call. If we have already
6438 built a stub, we don't need to do anything further. */
6439 fnname = targetm.strip_name_encoding (XSTR (fn, 0));
6440 for (l = mips16_stubs; l != NULL; l = l->next)
6441 if (strcmp (l->name, fnname) == 0)
6446 const char *separator;
6447 char *secname, *stubname;
6448 tree stubid, stubdecl;
6451 /* If the function does not return in FPRs, the special stub
6455 If the function does return in FPRs, the stub section is named
6456 .mips16.call.fp.FNNAME
6458 Build a decl for the stub. */
6459 secname = ACONCAT ((".mips16.call.", fp_ret_p ? "fp." : "",
6461 stubname = ACONCAT (("__call_stub_", fp_ret_p ? "fp_" : "",
6463 stubid = get_identifier (stubname);
6464 stubdecl = build_decl (BUILTINS_LOCATION,
6465 FUNCTION_DECL, stubid,
6466 build_function_type_list (void_type_node,
6468 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
6469 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
6470 RESULT_DECL, NULL_TREE,
6473 /* Output a comment. */
6474 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
6476 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
6480 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
6482 fprintf (asm_out_file, "%s%s", separator,
6483 (f & 3) == 1 ? "float" : "double");
6486 fprintf (asm_out_file, ")\n");
6488 /* Start the function definition. */
6489 assemble_start_function (stubdecl, stubname);
6490 mips_start_function_definition (stubname, false);
6494 fprintf (asm_out_file, "\t.cfi_startproc\n");
6496 /* Create a fake CFA 4 bytes below the stack pointer.
6497 This works around unwinders (like libgcc's) that expect
6498 the CFA for non-signal frames to be unique. */
6499 fprintf (asm_out_file, "\t.cfi_def_cfa 29,-4\n");
6501 /* "Save" $sp in itself so we don't use the fake CFA.
6502 This is: DW_CFA_val_expression r29, { DW_OP_reg29 }. */
6503 fprintf (asm_out_file, "\t.cfi_escape 0x16,29,1,0x6d\n");
6507 /* Load the address of the MIPS16 function into $25. Do this
6508 first so that targets with coprocessor interlocks can use
6509 an MFC1 to fill the delay slot. */
6510 if (TARGET_EXPLICIT_RELOCS)
6512 output_asm_insn ("lui\t%^,%%hi(%0)", &fn);
6513 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn);
6516 output_asm_insn ("la\t%^,%0", &fn);
6519 /* Move the arguments from general registers to floating-point
6521 mips_output_args_xfer (fp_code, 't');
6525 /* Save the return address in $18 and call the non-MIPS16 function.
6526 The stub's caller knows that $18 might be clobbered, even though
6527 $18 is usually a call-saved register. */
6528 fprintf (asm_out_file, "\tmove\t%s,%s\n",
6529 reg_names[GP_REG_FIRST + 18], reg_names[RETURN_ADDR_REGNUM]);
6530 output_asm_insn (MIPS_CALL ("jal", &fn, 0, -1), &fn);
6531 fprintf (asm_out_file, "\t.cfi_register 31,18\n");
6533 /* Move the result from floating-point registers to
6534 general registers. */
6535 switch (GET_MODE (retval))
6538 mips_output_32bit_xfer ('f', GP_RETURN + TARGET_BIG_ENDIAN,
6540 ? FP_REG_FIRST + MAX_FPRS_PER_FMT
6542 mips_output_32bit_xfer ('f', GP_RETURN + TARGET_LITTLE_ENDIAN,
6543 TARGET_LITTLE_ENDIAN
6544 ? FP_REG_FIRST + MAX_FPRS_PER_FMT
6546 if (GET_MODE (retval) == SCmode && TARGET_64BIT)
6548 /* On 64-bit targets, complex floats are returned in
6549 a single GPR, such that "sd" on a suitably-aligned
6550 target would store the value correctly. */
6551 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
6552 reg_names[GP_RETURN + TARGET_BIG_ENDIAN],
6553 reg_names[GP_RETURN + TARGET_BIG_ENDIAN]);
6554 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
6555 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN],
6556 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN]);
6557 fprintf (asm_out_file, "\tdsrl\t%s,%s,32\n",
6558 reg_names[GP_RETURN + TARGET_BIG_ENDIAN],
6559 reg_names[GP_RETURN + TARGET_BIG_ENDIAN]);
6560 fprintf (asm_out_file, "\tor\t%s,%s,%s\n",
6561 reg_names[GP_RETURN],
6562 reg_names[GP_RETURN],
6563 reg_names[GP_RETURN + 1]);
6568 mips_output_32bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6572 mips_output_64bit_xfer ('f', GP_RETURN + (8 / UNITS_PER_WORD),
6573 FP_REG_FIRST + MAX_FPRS_PER_FMT);
6577 mips_output_64bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6583 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 18]);
6584 fprintf (asm_out_file, "\t.cfi_endproc\n");
6588 /* Jump to the previously-loaded address. */
6589 output_asm_insn ("jr\t%^", NULL);
6592 #ifdef ASM_DECLARE_FUNCTION_SIZE
6593 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
6596 mips_end_function_definition (stubname);
6598 /* Record this stub. */
6599 l = XNEW (struct mips16_stub);
6600 l->name = xstrdup (fnname);
6601 l->fp_ret_p = fp_ret_p;
6602 l->next = mips16_stubs;
6606 /* If we expect a floating-point return value, but we've built a
6607 stub which does not expect one, then we're in trouble. We can't
6608 use the existing stub, because it won't handle the floating-point
6609 value. We can't build a new stub, because the linker won't know
6610 which stub to use for the various calls in this object file.
6611 Fortunately, this case is illegal, since it means that a function
6612 was declared in two different ways in a single compilation. */
6613 if (fp_ret_p && !l->fp_ret_p)
6614 error ("cannot handle inconsistent calls to %qs", fnname);
6616 if (retval == NULL_RTX)
6617 insn = gen_call_internal_direct (fn, args_size);
6619 insn = gen_call_value_internal_direct (retval, fn, args_size);
6620 insn = mips_emit_call_insn (insn, fn, fn, false);
6622 /* If we are calling a stub which handles a floating-point return
6623 value, we need to arrange to save $18 in the prologue. We do this
6624 by marking the function call as using the register. The prologue
6625 will later see that it is used, and emit code to save it. */
6627 CALL_INSN_FUNCTION_USAGE (insn) =
6628 gen_rtx_EXPR_LIST (VOIDmode,
6629 gen_rtx_CLOBBER (VOIDmode,
6630 gen_rtx_REG (word_mode, 18)),
6631 CALL_INSN_FUNCTION_USAGE (insn));
6636 /* Expand a call of type TYPE. RESULT is where the result will go (null
6637 for "call"s and "sibcall"s), ADDR is the address of the function,
6638 ARGS_SIZE is the size of the arguments and AUX is the value passed
6639 to us by mips_function_arg. LAZY_P is true if this call already
6640 involves a lazily-bound function address (such as when calling
6641 functions through a MIPS16 hard-float stub).
6643 Return the call itself. */
6646 mips_expand_call (enum mips_call_type type, rtx result, rtx addr,
6647 rtx args_size, rtx aux, bool lazy_p)
6649 rtx orig_addr, pattern, insn;
6652 fp_code = aux == 0 ? 0 : (int) GET_MODE (aux);
6653 insn = mips16_build_call_stub (result, &addr, args_size, fp_code);
6656 gcc_assert (!lazy_p && type == MIPS_CALL_NORMAL);
6661 if (!call_insn_operand (addr, VOIDmode))
6663 if (type == MIPS_CALL_EPILOGUE)
6664 addr = MIPS_EPILOGUE_TEMP (Pmode);
6666 addr = gen_reg_rtx (Pmode);
6667 lazy_p |= mips_load_call_address (type, addr, orig_addr);
6672 rtx (*fn) (rtx, rtx);
6674 if (type == MIPS_CALL_SIBCALL)
6675 fn = gen_sibcall_internal;
6677 fn = gen_call_internal;
6679 pattern = fn (addr, args_size);
6681 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
6683 /* Handle return values created by mips_return_fpr_pair. */
6684 rtx (*fn) (rtx, rtx, rtx, rtx);
6687 if (type == MIPS_CALL_SIBCALL)
6688 fn = gen_sibcall_value_multiple_internal;
6690 fn = gen_call_value_multiple_internal;
6692 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
6693 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
6694 pattern = fn (reg1, addr, args_size, reg2);
6698 rtx (*fn) (rtx, rtx, rtx);
6700 if (type == MIPS_CALL_SIBCALL)
6701 fn = gen_sibcall_value_internal;
6703 fn = gen_call_value_internal;
6705 /* Handle return values created by mips_return_fpr_single. */
6706 if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 1)
6707 result = XEXP (XVECEXP (result, 0, 0), 0);
6708 pattern = fn (result, addr, args_size);
6711 return mips_emit_call_insn (pattern, orig_addr, addr, lazy_p);
6714 /* Split call instruction INSN into a $gp-clobbering call and
6715 (where necessary) an instruction to restore $gp from its save slot.
6716 CALL_PATTERN is the pattern of the new call. */
6719 mips_split_call (rtx insn, rtx call_pattern)
6721 emit_call_insn (call_pattern);
6722 if (!find_reg_note (insn, REG_NORETURN, 0))
6723 /* Pick a temporary register that is suitable for both MIPS16 and
6724 non-MIPS16 code. $4 and $5 are used for returning complex double
6725 values in soft-float code, so $6 is the first suitable candidate. */
6726 mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode, GP_ARG_FIRST + 2));
6729 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
6732 mips_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
6734 if (!TARGET_SIBCALLS)
6737 /* Interrupt handlers need special epilogue code and therefore can't
6739 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
6742 /* We can't do a sibcall if the called function is a MIPS16 function
6743 because there is no direct "jx" instruction equivalent to "jalx" to
6744 switch the ISA mode. We only care about cases where the sibling
6745 and normal calls would both be direct. */
6747 && mips_use_mips16_mode_p (decl)
6748 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
6751 /* When -minterlink-mips16 is in effect, assume that non-locally-binding
6752 functions could be MIPS16 ones unless an attribute explicitly tells
6754 if (TARGET_INTERLINK_MIPS16
6756 && (DECL_EXTERNAL (decl) || !targetm.binds_local_p (decl))
6757 && !mips_nomips16_decl_p (decl)
6758 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
6765 /* Emit code to move general operand SRC into condition-code
6766 register DEST given that SCRATCH is a scratch TFmode FPR.
6773 where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */
6776 mips_expand_fcc_reload (rtx dest, rtx src, rtx scratch)
6780 /* Change the source to SFmode. */
6782 src = adjust_address (src, SFmode, 0);
6783 else if (REG_P (src) || GET_CODE (src) == SUBREG)
6784 src = gen_rtx_REG (SFmode, true_regnum (src));
6786 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
6787 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + MAX_FPRS_PER_FMT);
6789 mips_emit_move (copy_rtx (fp1), src);
6790 mips_emit_move (copy_rtx (fp2), CONST0_RTX (SFmode));
6791 emit_insn (gen_slt_sf (dest, fp2, fp1));
6794 /* Implement MOVE_BY_PIECES_P. */
6797 mips_move_by_pieces_p (unsigned HOST_WIDE_INT size, unsigned int align)
6801 /* movmemsi is meant to generate code that is at least as good as
6802 move_by_pieces. However, movmemsi effectively uses a by-pieces
6803 implementation both for moves smaller than a word and for
6804 word-aligned moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT
6805 bytes. We should allow the tree-level optimisers to do such
6806 moves by pieces, as it often exposes other optimization
6807 opportunities. We might as well continue to use movmemsi at
6808 the rtl level though, as it produces better code when
6809 scheduling is disabled (such as at -O). */
6810 if (currently_expanding_to_rtl)
6812 if (align < BITS_PER_WORD)
6813 return size < UNITS_PER_WORD;
6814 return size <= MIPS_MAX_MOVE_BYTES_STRAIGHT;
6816 /* The default value. If this becomes a target hook, we should
6817 call the default definition instead. */
6818 return (move_by_pieces_ninsns (size, align, MOVE_MAX_PIECES + 1)
6819 < (unsigned int) MOVE_RATIO (optimize_insn_for_speed_p ()));
6822 /* Implement STORE_BY_PIECES_P. */
6825 mips_store_by_pieces_p (unsigned HOST_WIDE_INT size, unsigned int align)
6827 /* Storing by pieces involves moving constants into registers
6828 of size MIN (ALIGN, BITS_PER_WORD), then storing them.
6829 We need to decide whether it is cheaper to load the address of
6830 constant data into a register and use a block move instead. */
6832 /* If the data is only byte aligned, then:
6834 (a1) A block move of less than 4 bytes would involve three 3 LBs and
6835 3 SBs. We might as well use 3 single-instruction LIs and 3 SBs
6838 (a2) A block move of 4 bytes from aligned source data can use an
6839 LW/SWL/SWR sequence. This is often better than the 4 LIs and
6840 4 SBs that we would generate when storing by pieces. */
6841 if (align <= BITS_PER_UNIT)
6844 /* If the data is 2-byte aligned, then:
6846 (b1) A block move of less than 4 bytes would use a combination of LBs,
6847 LHs, SBs and SHs. We get better code by using single-instruction
6848 LIs, SBs and SHs instead.
6850 (b2) A block move of 4 bytes from aligned source data would again use
6851 an LW/SWL/SWR sequence. In most cases, loading the address of
6852 the source data would require at least one extra instruction.
6853 It is often more efficient to use 2 single-instruction LIs and
6856 (b3) A block move of up to 3 additional bytes would be like (b1).
6858 (b4) A block move of 8 bytes from aligned source data can use two
6859 LW/SWL/SWR sequences or a single LD/SDL/SDR sequence. Both
6860 sequences are better than the 4 LIs and 4 SHs that we'd generate
6861 when storing by pieces.
6863 The reasoning for higher alignments is similar:
6865 (c1) A block move of less than 4 bytes would be the same as (b1).
6867 (c2) A block move of 4 bytes would use an LW/SW sequence. Again,
6868 loading the address of the source data would typically require
6869 at least one extra instruction. It is generally better to use
6872 (c3) A block move of up to 3 additional bytes would be like (b1).
6874 (c4) A block move of 8 bytes can use two LW/SW sequences or a single
6875 LD/SD sequence, and in these cases we've traditionally preferred
6876 the memory copy over the more bulky constant moves. */
6880 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
6881 Assume that the areas do not overlap. */
6884 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
6886 HOST_WIDE_INT offset, delta;
6887 unsigned HOST_WIDE_INT bits;
6889 enum machine_mode mode;
6892 /* Work out how many bits to move at a time. If both operands have
6893 half-word alignment, it is usually better to move in half words.
6894 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
6895 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
6896 Otherwise move word-sized chunks. */
6897 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
6898 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
6899 bits = BITS_PER_WORD / 2;
6901 bits = BITS_PER_WORD;
6903 mode = mode_for_size (bits, MODE_INT, 0);
6904 delta = bits / BITS_PER_UNIT;
6906 /* Allocate a buffer for the temporary registers. */
6907 regs = XALLOCAVEC (rtx, length / delta);
6909 /* Load as many BITS-sized chunks as possible. Use a normal load if
6910 the source has enough alignment, otherwise use left/right pairs. */
6911 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
6913 regs[i] = gen_reg_rtx (mode);
6914 if (MEM_ALIGN (src) >= bits)
6915 mips_emit_move (regs[i], adjust_address (src, mode, offset));
6918 rtx part = adjust_address (src, BLKmode, offset);
6919 if (!mips_expand_ext_as_unaligned_load (regs[i], part, bits, 0))
6924 /* Copy the chunks to the destination. */
6925 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
6926 if (MEM_ALIGN (dest) >= bits)
6927 mips_emit_move (adjust_address (dest, mode, offset), regs[i]);
6930 rtx part = adjust_address (dest, BLKmode, offset);
6931 if (!mips_expand_ins_as_unaligned_store (part, regs[i], bits, 0))
6935 /* Mop up any left-over bytes. */
6936 if (offset < length)
6938 src = adjust_address (src, BLKmode, offset);
6939 dest = adjust_address (dest, BLKmode, offset);
6940 move_by_pieces (dest, src, length - offset,
6941 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
6945 /* Helper function for doing a loop-based block operation on memory
6946 reference MEM. Each iteration of the loop will operate on LENGTH
6949 Create a new base register for use within the loop and point it to
6950 the start of MEM. Create a new memory reference that uses this
6951 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
6954 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
6955 rtx *loop_reg, rtx *loop_mem)
6957 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
6959 /* Although the new mem does not refer to a known location,
6960 it does keep up to LENGTH bytes of alignment. */
6961 *loop_mem = change_address (mem, BLKmode, *loop_reg);
6962 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
6965 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
6966 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
6967 the memory regions do not overlap. */
6970 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length,
6971 HOST_WIDE_INT bytes_per_iter)
6973 rtx label, src_reg, dest_reg, final_src, test;
6974 HOST_WIDE_INT leftover;
6976 leftover = length % bytes_per_iter;
6979 /* Create registers and memory references for use within the loop. */
6980 mips_adjust_block_mem (src, bytes_per_iter, &src_reg, &src);
6981 mips_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest);
6983 /* Calculate the value that SRC_REG should have after the last iteration
6985 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
6988 /* Emit the start of the loop. */
6989 label = gen_label_rtx ();
6992 /* Emit the loop body. */
6993 mips_block_move_straight (dest, src, bytes_per_iter);
6995 /* Move on to the next block. */
6996 mips_emit_move (src_reg, plus_constant (Pmode, src_reg, bytes_per_iter));
6997 mips_emit_move (dest_reg, plus_constant (Pmode, dest_reg, bytes_per_iter));
6999 /* Emit the loop condition. */
7000 test = gen_rtx_NE (VOIDmode, src_reg, final_src);
7001 if (Pmode == DImode)
7002 emit_jump_insn (gen_cbranchdi4 (test, src_reg, final_src, label));
7004 emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label));
7006 /* Mop up any left-over bytes. */
7008 mips_block_move_straight (dest, src, leftover);
7011 /* Expand a movmemsi instruction, which copies LENGTH bytes from
7012 memory reference SRC to memory reference DEST. */
7015 mips_expand_block_move (rtx dest, rtx src, rtx length)
7017 if (CONST_INT_P (length))
7019 if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)
7021 mips_block_move_straight (dest, src, INTVAL (length));
7026 mips_block_move_loop (dest, src, INTVAL (length),
7027 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER);
7034 /* Expand a loop of synci insns for the address range [BEGIN, END). */
7037 mips_expand_synci_loop (rtx begin, rtx end)
7039 rtx inc, label, end_label, cmp_result, mask, length;
7041 /* Create end_label. */
7042 end_label = gen_label_rtx ();
7044 /* Check if begin equals end. */
7045 cmp_result = gen_rtx_EQ (VOIDmode, begin, end);
7046 emit_jump_insn (gen_condjump (cmp_result, end_label));
7048 /* Load INC with the cache line size (rdhwr INC,$1). */
7049 inc = gen_reg_rtx (Pmode);
7050 emit_insn (PMODE_INSN (gen_rdhwr_synci_step, (inc)));
7052 /* Check if inc is 0. */
7053 cmp_result = gen_rtx_EQ (VOIDmode, inc, const0_rtx);
7054 emit_jump_insn (gen_condjump (cmp_result, end_label));
7056 /* Calculate mask. */
7057 mask = mips_force_unary (Pmode, NEG, inc);
7059 /* Mask out begin by mask. */
7060 begin = mips_force_binary (Pmode, AND, begin, mask);
7062 /* Calculate length. */
7063 length = mips_force_binary (Pmode, MINUS, end, begin);
7065 /* Loop back to here. */
7066 label = gen_label_rtx ();
7069 emit_insn (gen_synci (begin));
7071 /* Update length. */
7072 mips_emit_binary (MINUS, length, length, inc);
7075 mips_emit_binary (PLUS, begin, begin, inc);
7077 /* Check if length is greater than 0. */
7078 cmp_result = gen_rtx_GT (VOIDmode, length, const0_rtx);
7079 emit_jump_insn (gen_condjump (cmp_result, label));
7081 emit_label (end_label);
7084 /* Expand a QI or HI mode atomic memory operation.
7086 GENERATOR contains a pointer to the gen_* function that generates
7087 the SI mode underlying atomic operation using masks that we
7090 RESULT is the return register for the operation. Its value is NULL
7093 MEM is the location of the atomic access.
7095 OLDVAL is the first operand for the operation.
7097 NEWVAL is the optional second operand for the operation. Its value
7098 is NULL if unused. */
7101 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator,
7102 rtx result, rtx mem, rtx oldval, rtx newval)
7104 rtx orig_addr, memsi_addr, memsi, shift, shiftsi, unshifted_mask;
7105 rtx unshifted_mask_reg, mask, inverted_mask, si_op;
7107 enum machine_mode mode;
7109 mode = GET_MODE (mem);
7111 /* Compute the address of the containing SImode value. */
7112 orig_addr = force_reg (Pmode, XEXP (mem, 0));
7113 memsi_addr = mips_force_binary (Pmode, AND, orig_addr,
7114 force_reg (Pmode, GEN_INT (-4)));
7116 /* Create a memory reference for it. */
7117 memsi = gen_rtx_MEM (SImode, memsi_addr);
7118 set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER);
7119 MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem);
7121 /* Work out the byte offset of the QImode or HImode value,
7122 counting from the least significant byte. */
7123 shift = mips_force_binary (Pmode, AND, orig_addr, GEN_INT (3));
7124 if (TARGET_BIG_ENDIAN)
7125 mips_emit_binary (XOR, shift, shift, GEN_INT (mode == QImode ? 3 : 2));
7127 /* Multiply by eight to convert the shift value from bytes to bits. */
7128 mips_emit_binary (ASHIFT, shift, shift, GEN_INT (3));
7130 /* Make the final shift an SImode value, so that it can be used in
7131 SImode operations. */
7132 shiftsi = force_reg (SImode, gen_lowpart (SImode, shift));
7134 /* Set MASK to an inclusive mask of the QImode or HImode value. */
7135 unshifted_mask = GEN_INT (GET_MODE_MASK (mode));
7136 unshifted_mask_reg = force_reg (SImode, unshifted_mask);
7137 mask = mips_force_binary (SImode, ASHIFT, unshifted_mask_reg, shiftsi);
7139 /* Compute the equivalent exclusive mask. */
7140 inverted_mask = gen_reg_rtx (SImode);
7141 emit_insn (gen_rtx_SET (VOIDmode, inverted_mask,
7142 gen_rtx_NOT (SImode, mask)));
7144 /* Shift the old value into place. */
7145 if (oldval != const0_rtx)
7147 oldval = convert_modes (SImode, mode, oldval, true);
7148 oldval = force_reg (SImode, oldval);
7149 oldval = mips_force_binary (SImode, ASHIFT, oldval, shiftsi);
7152 /* Do the same for the new value. */
7153 if (newval && newval != const0_rtx)
7155 newval = convert_modes (SImode, mode, newval, true);
7156 newval = force_reg (SImode, newval);
7157 newval = mips_force_binary (SImode, ASHIFT, newval, shiftsi);
7160 /* Do the SImode atomic access. */
7162 res = gen_reg_rtx (SImode);
7164 si_op = generator.fn_6 (res, memsi, mask, inverted_mask, oldval, newval);
7166 si_op = generator.fn_5 (res, memsi, mask, inverted_mask, oldval);
7168 si_op = generator.fn_4 (memsi, mask, inverted_mask, oldval);
7174 /* Shift and convert the result. */
7175 mips_emit_binary (AND, res, res, mask);
7176 mips_emit_binary (LSHIFTRT, res, res, shiftsi);
7177 mips_emit_move (result, gen_lowpart (GET_MODE (result), res));
7181 /* Return true if it is possible to use left/right accesses for a
7182 bitfield of WIDTH bits starting BITPOS bits into *OP. When
7183 returning true, update *OP, *LEFT and *RIGHT as follows:
7185 *OP is a BLKmode reference to the whole field.
7187 *LEFT is a QImode reference to the first byte if big endian or
7188 the last byte if little endian. This address can be used in the
7189 left-side instructions (LWL, SWL, LDL, SDL).
7191 *RIGHT is a QImode reference to the opposite end of the field and
7192 can be used in the patterning right-side instruction. */
7195 mips_get_unaligned_mem (rtx *op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos,
7196 rtx *left, rtx *right)
7200 /* Check that the operand really is a MEM. Not all the extv and
7201 extzv predicates are checked. */
7205 /* Check that the size is valid. */
7206 if (width != 32 && (!TARGET_64BIT || width != 64))
7209 /* We can only access byte-aligned values. Since we are always passed
7210 a reference to the first byte of the field, it is not necessary to
7211 do anything with BITPOS after this check. */
7212 if (bitpos % BITS_PER_UNIT != 0)
7215 /* Reject aligned bitfields: we want to use a normal load or store
7216 instead of a left/right pair. */
7217 if (MEM_ALIGN (*op) >= width)
7220 /* Adjust *OP to refer to the whole field. This also has the effect
7221 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
7222 *op = adjust_address (*op, BLKmode, 0);
7223 set_mem_size (*op, width / BITS_PER_UNIT);
7225 /* Get references to both ends of the field. We deliberately don't
7226 use the original QImode *OP for FIRST since the new BLKmode one
7227 might have a simpler address. */
7228 first = adjust_address (*op, QImode, 0);
7229 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
7231 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
7232 correspond to the MSB and RIGHT to the LSB. */
7233 if (TARGET_BIG_ENDIAN)
7234 *left = first, *right = last;
7236 *left = last, *right = first;
7241 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
7242 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
7243 the operation is the equivalent of:
7245 (set DEST (*_extract SRC WIDTH BITPOS))
7247 Return true on success. */
7250 mips_expand_ext_as_unaligned_load (rtx dest, rtx src, HOST_WIDE_INT width,
7251 HOST_WIDE_INT bitpos)
7253 rtx left, right, temp;
7255 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
7256 be a paradoxical word_mode subreg. This is the only case in which
7257 we allow the destination to be larger than the source. */
7258 if (GET_CODE (dest) == SUBREG
7259 && GET_MODE (dest) == DImode
7260 && GET_MODE (SUBREG_REG (dest)) == SImode)
7261 dest = SUBREG_REG (dest);
7263 /* After the above adjustment, the destination must be the same
7264 width as the source. */
7265 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
7268 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
7271 temp = gen_reg_rtx (GET_MODE (dest));
7272 if (GET_MODE (dest) == DImode)
7274 emit_insn (gen_mov_ldl (temp, src, left));
7275 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
7279 emit_insn (gen_mov_lwl (temp, src, left));
7280 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
7285 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
7286 BITPOS and SRC are the operands passed to the expander; the operation
7287 is the equivalent of:
7289 (set (zero_extract DEST WIDTH BITPOS) SRC)
7291 Return true on success. */
7294 mips_expand_ins_as_unaligned_store (rtx dest, rtx src, HOST_WIDE_INT width,
7295 HOST_WIDE_INT bitpos)
7298 enum machine_mode mode;
7300 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
7303 mode = mode_for_size (width, MODE_INT, 0);
7304 src = gen_lowpart (mode, src);
7307 emit_insn (gen_mov_sdl (dest, src, left));
7308 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
7312 emit_insn (gen_mov_swl (dest, src, left));
7313 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
7318 /* Return true if X is a MEM with the same size as MODE. */
7321 mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
7324 && MEM_SIZE_KNOWN_P (x)
7325 && MEM_SIZE (x) == GET_MODE_SIZE (mode));
7328 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
7329 source of an "ext" instruction or the destination of an "ins"
7330 instruction. OP must be a register operand and the following
7331 conditions must hold:
7333 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
7334 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7335 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7337 Also reject lengths equal to a word as they are better handled
7338 by the move patterns. */
7341 mips_use_ins_ext_p (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos)
7343 if (!ISA_HAS_EXT_INS
7344 || !register_operand (op, VOIDmode)
7345 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
7348 if (!IN_RANGE (width, 1, GET_MODE_BITSIZE (GET_MODE (op)) - 1))
7351 if (bitpos < 0 || bitpos + width > GET_MODE_BITSIZE (GET_MODE (op)))
7357 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
7358 operation if MAXLEN is the maxium length of consecutive bits that
7359 can make up MASK. MODE is the mode of the operation. See
7360 mask_low_and_shift_len for the actual definition. */
7363 mask_low_and_shift_p (enum machine_mode mode, rtx mask, rtx shift, int maxlen)
7365 return IN_RANGE (mask_low_and_shift_len (mode, mask, shift), 1, maxlen);
7368 /* Return true iff OP1 and OP2 are valid operands together for the
7369 *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider,
7370 see the table in the comment before the pattern. */
7373 and_operands_ok (enum machine_mode mode, rtx op1, rtx op2)
7375 return (memory_operand (op1, mode)
7376 ? and_load_operand (op2, mode)
7377 : and_reg_operand (op2, mode));
7380 /* The canonical form of a mask-low-and-shift-left operation is
7381 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
7382 cleared. Thus we need to shift MASK to the right before checking if it
7383 is a valid mask value. MODE is the mode of the operation. If true
7384 return the length of the mask, otherwise return -1. */
7387 mask_low_and_shift_len (enum machine_mode mode, rtx mask, rtx shift)
7389 HOST_WIDE_INT shval;
7391 shval = INTVAL (shift) & (GET_MODE_BITSIZE (mode) - 1);
7392 return exact_log2 ((UINTVAL (mask) >> shval) + 1);
7395 /* Return true if -msplit-addresses is selected and should be honored.
7397 -msplit-addresses is a half-way house between explicit relocations
7398 and the traditional assembler macros. It can split absolute 32-bit
7399 symbolic constants into a high/lo_sum pair but uses macros for other
7402 Like explicit relocation support for REL targets, it relies
7403 on GNU extensions in the assembler and the linker.
7405 Although this code should work for -O0, it has traditionally
7406 been treated as an optimization. */
7409 mips_split_addresses_p (void)
7411 return (TARGET_SPLIT_ADDRESSES
7415 && !ABI_HAS_64BIT_SYMBOLS);
7418 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
7421 mips_init_relocs (void)
7423 memset (mips_split_p, '\0', sizeof (mips_split_p));
7424 memset (mips_split_hi_p, '\0', sizeof (mips_split_hi_p));
7425 memset (mips_use_pcrel_pool_p, '\0', sizeof (mips_use_pcrel_pool_p));
7426 memset (mips_hi_relocs, '\0', sizeof (mips_hi_relocs));
7427 memset (mips_lo_relocs, '\0', sizeof (mips_lo_relocs));
7429 if (TARGET_MIPS16_PCREL_LOADS)
7430 mips_use_pcrel_pool_p[SYMBOL_ABSOLUTE] = true;
7433 if (ABI_HAS_64BIT_SYMBOLS)
7435 if (TARGET_EXPLICIT_RELOCS)
7437 mips_split_p[SYMBOL_64_HIGH] = true;
7438 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
7439 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
7441 mips_split_p[SYMBOL_64_MID] = true;
7442 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
7443 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
7445 mips_split_p[SYMBOL_64_LOW] = true;
7446 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
7447 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
7449 mips_split_p[SYMBOL_ABSOLUTE] = true;
7450 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
7455 if (TARGET_EXPLICIT_RELOCS
7456 || mips_split_addresses_p ()
7459 mips_split_p[SYMBOL_ABSOLUTE] = true;
7460 mips_hi_relocs[SYMBOL_ABSOLUTE] = "%hi(";
7461 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
7468 /* The high part is provided by a pseudo copy of $gp. */
7469 mips_split_p[SYMBOL_GP_RELATIVE] = true;
7470 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gprel(";
7472 else if (TARGET_EXPLICIT_RELOCS)
7473 /* Small data constants are kept whole until after reload,
7474 then lowered by mips_rewrite_small_data. */
7475 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gp_rel(";
7477 if (TARGET_EXPLICIT_RELOCS)
7479 mips_split_p[SYMBOL_GOT_PAGE_OFST] = true;
7482 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
7483 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%got_ofst(";
7487 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
7488 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%lo(";
7491 /* Expose the use of $28 as soon as possible. */
7492 mips_split_hi_p[SYMBOL_GOT_PAGE_OFST] = true;
7496 /* The HIGH and LO_SUM are matched by special .md patterns. */
7497 mips_split_p[SYMBOL_GOT_DISP] = true;
7499 mips_split_p[SYMBOL_GOTOFF_DISP] = true;
7500 mips_hi_relocs[SYMBOL_GOTOFF_DISP] = "%got_hi(";
7501 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_lo(";
7503 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
7504 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
7505 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
7510 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_disp(";
7512 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got(";
7513 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
7515 /* Expose the use of $28 as soon as possible. */
7516 mips_split_p[SYMBOL_GOT_DISP] = true;
7522 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
7523 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
7524 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
7527 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
7528 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
7530 if (TARGET_MIPS16_PCREL_LOADS)
7532 mips_use_pcrel_pool_p[SYMBOL_DTPREL] = true;
7533 mips_use_pcrel_pool_p[SYMBOL_TPREL] = true;
7537 mips_split_p[SYMBOL_DTPREL] = true;
7538 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
7539 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
7541 mips_split_p[SYMBOL_TPREL] = true;
7542 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
7543 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
7546 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
7547 mips_lo_relocs[SYMBOL_HALF] = "%half(";
7550 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
7551 in context CONTEXT. RELOCS is the array of relocations to use. */
7554 mips_print_operand_reloc (FILE *file, rtx op, enum mips_symbol_context context,
7555 const char **relocs)
7557 enum mips_symbol_type symbol_type;
7560 symbol_type = mips_classify_symbolic_expression (op, context);
7561 gcc_assert (relocs[symbol_type]);
7563 fputs (relocs[symbol_type], file);
7564 output_addr_const (file, mips_strip_unspec_address (op));
7565 for (p = relocs[symbol_type]; *p != 0; p++)
7570 /* Start a new block with the given asm switch enabled. If we need
7571 to print a directive, emit PREFIX before it and SUFFIX after it. */
7574 mips_push_asm_switch_1 (struct mips_asm_switch *asm_switch,
7575 const char *prefix, const char *suffix)
7577 if (asm_switch->nesting_level == 0)
7578 fprintf (asm_out_file, "%s.set\tno%s%s", prefix, asm_switch->name, suffix);
7579 asm_switch->nesting_level++;
7582 /* Likewise, but end a block. */
7585 mips_pop_asm_switch_1 (struct mips_asm_switch *asm_switch,
7586 const char *prefix, const char *suffix)
7588 gcc_assert (asm_switch->nesting_level);
7589 asm_switch->nesting_level--;
7590 if (asm_switch->nesting_level == 0)
7591 fprintf (asm_out_file, "%s.set\t%s%s", prefix, asm_switch->name, suffix);
7594 /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1
7595 that either print a complete line or print nothing. */
7598 mips_push_asm_switch (struct mips_asm_switch *asm_switch)
7600 mips_push_asm_switch_1 (asm_switch, "\t", "\n");
7604 mips_pop_asm_switch (struct mips_asm_switch *asm_switch)
7606 mips_pop_asm_switch_1 (asm_switch, "\t", "\n");
7609 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
7610 The punctuation characters are:
7612 '(' Start a nested ".set noreorder" block.
7613 ')' End a nested ".set noreorder" block.
7614 '[' Start a nested ".set noat" block.
7615 ']' End a nested ".set noat" block.
7616 '<' Start a nested ".set nomacro" block.
7617 '>' End a nested ".set nomacro" block.
7618 '*' Behave like %(%< if generating a delayed-branch sequence.
7619 '#' Print a nop if in a ".set noreorder" block.
7620 '/' Like '#', but do nothing within a delayed-branch sequence.
7621 '?' Print "l" if mips_branch_likely is true
7622 '~' Print a nop if mips_branch_likely is true
7623 '.' Print the name of the register with a hard-wired zero (zero or $0).
7624 '@' Print the name of the assembler temporary register (at or $1).
7625 '^' Print the name of the pic call-through register (t9 or $25).
7626 '+' Print the name of the gp register (usually gp or $28).
7627 '$' Print the name of the stack pointer register (sp or $29).
7629 See also mips_init_print_operand_pucnt. */
7632 mips_print_operand_punctuation (FILE *file, int ch)
7637 mips_push_asm_switch_1 (&mips_noreorder, "", "\n\t");
7641 mips_pop_asm_switch_1 (&mips_noreorder, "\n\t", "");
7645 mips_push_asm_switch_1 (&mips_noat, "", "\n\t");
7649 mips_pop_asm_switch_1 (&mips_noat, "\n\t", "");
7653 mips_push_asm_switch_1 (&mips_nomacro, "", "\n\t");
7657 mips_pop_asm_switch_1 (&mips_nomacro, "\n\t", "");
7661 if (final_sequence != 0)
7663 mips_print_operand_punctuation (file, '(');
7664 mips_print_operand_punctuation (file, '<');
7669 if (mips_noreorder.nesting_level > 0)
7670 fputs ("\n\tnop", file);
7674 /* Print an extra newline so that the delayed insn is separated
7675 from the following ones. This looks neater and is consistent
7676 with non-nop delayed sequences. */
7677 if (mips_noreorder.nesting_level > 0 && final_sequence == 0)
7678 fputs ("\n\tnop\n", file);
7682 if (mips_branch_likely)
7687 if (mips_branch_likely)
7688 fputs ("\n\tnop", file);
7692 fputs (reg_names[GP_REG_FIRST + 0], file);
7696 fputs (reg_names[AT_REGNUM], file);
7700 fputs (reg_names[PIC_FUNCTION_ADDR_REGNUM], file);
7704 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
7708 fputs (reg_names[STACK_POINTER_REGNUM], file);
7717 /* Initialize mips_print_operand_punct. */
7720 mips_init_print_operand_punct (void)
7724 for (p = "()[]<>*#/?~.@^+$"; *p; p++)
7725 mips_print_operand_punct[(unsigned char) *p] = true;
7728 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
7729 associated with condition CODE. Print the condition part of the
7733 mips_print_int_branch_condition (FILE *file, enum rtx_code code, int letter)
7747 /* Conveniently, the MIPS names for these conditions are the same
7748 as their RTL equivalents. */
7749 fputs (GET_RTX_NAME (code), file);
7753 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
7758 /* Likewise floating-point branches. */
7761 mips_print_float_branch_condition (FILE *file, enum rtx_code code, int letter)
7766 fputs ("c1f", file);
7770 fputs ("c1t", file);
7774 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
7779 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
7782 mips_print_operand_punct_valid_p (unsigned char code)
7784 return mips_print_operand_punct[code];
7787 /* Implement TARGET_PRINT_OPERAND. The MIPS-specific operand codes are:
7789 'X' Print CONST_INT OP in hexadecimal format.
7790 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
7791 'd' Print CONST_INT OP in decimal.
7792 'm' Print one less than CONST_INT OP in decimal.
7793 'h' Print the high-part relocation associated with OP, after stripping
7795 'R' Print the low-part relocation associated with OP.
7796 'C' Print the integer branch condition for comparison OP.
7797 'N' Print the inverse of the integer branch condition for comparison OP.
7798 'F' Print the FPU branch condition for comparison OP.
7799 'W' Print the inverse of the FPU branch condition for comparison OP.
7800 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
7801 'z' for (eq:?I ...), 'n' for (ne:?I ...).
7802 't' Like 'T', but with the EQ/NE cases reversed
7803 'Y' Print mips_fp_conditions[INTVAL (OP)]
7804 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
7805 'q' Print a DSP accumulator register.
7806 'D' Print the second part of a double-word register or memory operand.
7807 'L' Print the low-order register in a double-word register operand.
7808 'M' Print high-order register in a double-word register operand.
7809 'z' Print $0 if OP is zero, otherwise print OP normally.
7810 'b' Print the address of a memory operand, without offset. */
7813 mips_print_operand (FILE *file, rtx op, int letter)
7817 if (mips_print_operand_punct_valid_p (letter))
7819 mips_print_operand_punctuation (file, letter);
7824 code = GET_CODE (op);
7829 if (CONST_INT_P (op))
7830 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
7832 output_operand_lossage ("invalid use of '%%%c'", letter);
7836 if (CONST_INT_P (op))
7837 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op) & 0xffff);
7839 output_operand_lossage ("invalid use of '%%%c'", letter);
7843 if (CONST_INT_P (op))
7844 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op));
7846 output_operand_lossage ("invalid use of '%%%c'", letter);
7850 if (CONST_INT_P (op))
7851 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op) - 1);
7853 output_operand_lossage ("invalid use of '%%%c'", letter);
7859 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_hi_relocs);
7863 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_lo_relocs);
7867 mips_print_int_branch_condition (file, code, letter);
7871 mips_print_int_branch_condition (file, reverse_condition (code), letter);
7875 mips_print_float_branch_condition (file, code, letter);
7879 mips_print_float_branch_condition (file, reverse_condition (code),
7886 int truth = (code == NE) == (letter == 'T');
7887 fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
7892 if (code == CONST_INT && UINTVAL (op) < ARRAY_SIZE (mips_fp_conditions))
7893 fputs (mips_fp_conditions[UINTVAL (op)], file);
7895 output_operand_lossage ("'%%%c' is not a valid operand prefix",
7902 mips_print_operand (file, op, 0);
7908 if (code == REG && MD_REG_P (REGNO (op)))
7909 fprintf (file, "$ac0");
7910 else if (code == REG && DSP_ACC_REG_P (REGNO (op)))
7911 fprintf (file, "$ac%c", reg_names[REGNO (op)][3]);
7913 output_operand_lossage ("invalid use of '%%%c'", letter);
7921 unsigned int regno = REGNO (op);
7922 if ((letter == 'M' && TARGET_LITTLE_ENDIAN)
7923 || (letter == 'L' && TARGET_BIG_ENDIAN)
7926 else if (letter && letter != 'z' && letter != 'M' && letter != 'L')
7927 output_operand_lossage ("invalid use of '%%%c'", letter);
7928 /* We need to print $0 .. $31 for COP0 registers. */
7929 if (COP0_REG_P (regno))
7930 fprintf (file, "$%s", ®_names[regno][4]);
7932 fprintf (file, "%s", reg_names[regno]);
7938 output_address (plus_constant (Pmode, XEXP (op, 0), 4));
7939 else if (letter == 'b')
7941 gcc_assert (REG_P (XEXP (op, 0)));
7942 mips_print_operand (file, XEXP (op, 0), 0);
7944 else if (letter && letter != 'z')
7945 output_operand_lossage ("invalid use of '%%%c'", letter);
7947 output_address (XEXP (op, 0));
7951 if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
7952 fputs (reg_names[GP_REG_FIRST], file);
7953 else if (letter && letter != 'z')
7954 output_operand_lossage ("invalid use of '%%%c'", letter);
7955 else if (CONST_GP_P (op))
7956 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
7958 output_addr_const (file, mips_strip_unspec_address (op));
7964 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
7967 mips_print_operand_address (FILE *file, rtx x)
7969 struct mips_address_info addr;
7971 if (mips_classify_address (&addr, x, word_mode, true))
7975 mips_print_operand (file, addr.offset, 0);
7976 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
7979 case ADDRESS_LO_SUM:
7980 mips_print_operand_reloc (file, addr.offset, SYMBOL_CONTEXT_MEM,
7982 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
7985 case ADDRESS_CONST_INT:
7986 output_addr_const (file, x);
7987 fprintf (file, "(%s)", reg_names[GP_REG_FIRST]);
7990 case ADDRESS_SYMBOLIC:
7991 output_addr_const (file, mips_strip_unspec_address (x));
7997 /* Implement TARGET_ENCODE_SECTION_INFO. */
8000 mips_encode_section_info (tree decl, rtx rtl, int first)
8002 default_encode_section_info (decl, rtl, first);
8004 if (TREE_CODE (decl) == FUNCTION_DECL)
8006 rtx symbol = XEXP (rtl, 0);
8007 tree type = TREE_TYPE (decl);
8009 /* Encode whether the symbol is short or long. */
8010 if ((TARGET_LONG_CALLS && !mips_near_type_p (type))
8011 || mips_far_type_p (type))
8012 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
8016 /* Implement TARGET_SELECT_RTX_SECTION. */
8019 mips_select_rtx_section (enum machine_mode mode, rtx x,
8020 unsigned HOST_WIDE_INT align)
8022 /* ??? Consider using mergeable small data sections. */
8023 if (mips_rtx_constant_in_small_data_p (mode))
8024 return get_named_section (NULL, ".sdata", 0);
8026 return default_elf_select_rtx_section (mode, x, align);
8029 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
8031 The complication here is that, with the combination TARGET_ABICALLS
8032 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
8033 absolute addresses, and should therefore not be included in the
8034 read-only part of a DSO. Handle such cases by selecting a normal
8035 data section instead of a read-only one. The logic apes that in
8036 default_function_rodata_section. */
8039 mips_function_rodata_section (tree decl)
8041 if (!TARGET_ABICALLS || TARGET_ABSOLUTE_ABICALLS || TARGET_GPWORD)
8042 return default_function_rodata_section (decl);
8044 if (decl && DECL_SECTION_NAME (decl))
8046 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
8047 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
8049 char *rname = ASTRDUP (name);
8051 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
8053 else if (flag_function_sections
8054 && flag_data_sections
8055 && strncmp (name, ".text.", 6) == 0)
8057 char *rname = ASTRDUP (name);
8058 memcpy (rname + 1, "data", 4);
8059 return get_section (rname, SECTION_WRITE, decl);
8062 return data_section;
8065 /* Implement TARGET_IN_SMALL_DATA_P. */
8068 mips_in_small_data_p (const_tree decl)
8070 unsigned HOST_WIDE_INT size;
8072 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
8075 /* We don't yet generate small-data references for -mabicalls
8076 or VxWorks RTP code. See the related -G handling in
8077 mips_option_override. */
8078 if (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
8081 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
8085 /* Reject anything that isn't in a known small-data section. */
8086 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
8087 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
8090 /* If a symbol is defined externally, the assembler will use the
8091 usual -G rules when deciding how to implement macros. */
8092 if (mips_lo_relocs[SYMBOL_GP_RELATIVE] || !DECL_EXTERNAL (decl))
8095 else if (TARGET_EMBEDDED_DATA)
8097 /* Don't put constants into the small data section: we want them
8098 to be in ROM rather than RAM. */
8099 if (TREE_CODE (decl) != VAR_DECL)
8102 if (TREE_READONLY (decl)
8103 && !TREE_SIDE_EFFECTS (decl)
8104 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
8108 /* Enforce -mlocal-sdata. */
8109 if (!TARGET_LOCAL_SDATA && !TREE_PUBLIC (decl))
8112 /* Enforce -mextern-sdata. */
8113 if (!TARGET_EXTERN_SDATA && DECL_P (decl))
8115 if (DECL_EXTERNAL (decl))
8117 if (DECL_COMMON (decl) && DECL_INITIAL (decl) == NULL)
8121 /* We have traditionally not treated zero-sized objects as small data,
8122 so this is now effectively part of the ABI. */
8123 size = int_size_in_bytes (TREE_TYPE (decl));
8124 return size > 0 && size <= mips_small_data_threshold;
8127 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
8128 anchors for small data: the GP register acts as an anchor in that
8129 case. We also don't want to use them for PC-relative accesses,
8130 where the PC acts as an anchor. */
8133 mips_use_anchors_for_symbol_p (const_rtx symbol)
8135 switch (mips_classify_symbol (symbol, SYMBOL_CONTEXT_MEM))
8137 case SYMBOL_PC_RELATIVE:
8138 case SYMBOL_GP_RELATIVE:
8142 return default_use_anchors_for_symbol_p (symbol);
8146 /* The MIPS debug format wants all automatic variables and arguments
8147 to be in terms of the virtual frame pointer (stack pointer before
8148 any adjustment in the function), while the MIPS 3.0 linker wants
8149 the frame pointer to be the stack pointer after the initial
8150 adjustment. So, we do the adjustment here. The arg pointer (which
8151 is eliminated) points to the virtual frame pointer, while the frame
8152 pointer (which may be eliminated) points to the stack pointer after
8153 the initial adjustments. */
8156 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
8158 rtx offset2 = const0_rtx;
8159 rtx reg = eliminate_constant_term (addr, &offset2);
8162 offset = INTVAL (offset2);
8164 if (reg == stack_pointer_rtx
8165 || reg == frame_pointer_rtx
8166 || reg == hard_frame_pointer_rtx)
8168 offset -= cfun->machine->frame.total_size;
8169 if (reg == hard_frame_pointer_rtx)
8170 offset += cfun->machine->frame.hard_frame_pointer_offset;
8176 /* Implement ASM_OUTPUT_EXTERNAL. */
8179 mips_output_external (FILE *file, tree decl, const char *name)
8181 default_elf_asm_output_external (file, decl, name);
8183 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
8184 set in order to avoid putting out names that are never really
8186 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
8188 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
8190 /* When using assembler macros, emit .extern directives for
8191 all small-data externs so that the assembler knows how
8194 In most cases it would be safe (though pointless) to emit
8195 .externs for other symbols too. One exception is when an
8196 object is within the -G limit but declared by the user to
8197 be in a section other than .sbss or .sdata. */
8198 fputs ("\t.extern\t", file);
8199 assemble_name (file, name);
8200 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n",
8201 int_size_in_bytes (TREE_TYPE (decl)));
8206 /* Implement TARGET_ASM_OUTPUT_SOURCE_FILENAME. */
8209 mips_output_filename (FILE *stream, const char *name)
8211 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
8213 if (write_symbols == DWARF2_DEBUG)
8215 else if (mips_output_filename_first_time)
8217 mips_output_filename_first_time = 0;
8218 num_source_filenames += 1;
8219 current_function_file = name;
8220 fprintf (stream, "\t.file\t%d ", num_source_filenames);
8221 output_quoted_string (stream, name);
8222 putc ('\n', stream);
8224 /* If we are emitting stabs, let dbxout.c handle this (except for
8225 the mips_output_filename_first_time case). */
8226 else if (write_symbols == DBX_DEBUG)
8228 else if (name != current_function_file
8229 && strcmp (name, current_function_file) != 0)
8231 num_source_filenames += 1;
8232 current_function_file = name;
8233 fprintf (stream, "\t.file\t%d ", num_source_filenames);
8234 output_quoted_string (stream, name);
8235 putc ('\n', stream);
8239 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
8241 static void ATTRIBUTE_UNUSED
8242 mips_output_dwarf_dtprel (FILE *file, int size, rtx x)
8247 fputs ("\t.dtprelword\t", file);
8251 fputs ("\t.dtpreldword\t", file);
8257 output_addr_const (file, x);
8258 fputs ("+0x8000", file);
8261 /* Implement TARGET_DWARF_REGISTER_SPAN. */
8264 mips_dwarf_register_span (rtx reg)
8267 enum machine_mode mode;
8269 /* By default, GCC maps increasing register numbers to increasing
8270 memory locations, but paired FPRs are always little-endian,
8271 regardless of the prevailing endianness. */
8272 mode = GET_MODE (reg);
8273 if (FP_REG_P (REGNO (reg))
8274 && TARGET_BIG_ENDIAN
8275 && MAX_FPRS_PER_FMT > 1
8276 && GET_MODE_SIZE (mode) > UNITS_PER_FPREG)
8278 gcc_assert (GET_MODE_SIZE (mode) == UNITS_PER_HWFPVALUE);
8279 high = mips_subword (reg, true);
8280 low = mips_subword (reg, false);
8281 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, high, low));
8287 /* Implement ASM_OUTPUT_ASCII. */
8290 mips_output_ascii (FILE *stream, const char *string, size_t len)
8296 fprintf (stream, "\t.ascii\t\"");
8297 for (i = 0; i < len; i++)
8301 c = (unsigned char) string[i];
8304 if (c == '\\' || c == '\"')
8306 putc ('\\', stream);
8314 fprintf (stream, "\\%03o", c);
8318 if (cur_pos > 72 && i+1 < len)
8321 fprintf (stream, "\"\n\t.ascii\t\"");
8324 fprintf (stream, "\"\n");
8327 /* Return the pseudo-op for full SYMBOL_(D)TPREL address *ADDR.
8328 Update *ADDR with the operand that should be printed. */
8331 mips_output_tls_reloc_directive (rtx *addr)
8333 enum mips_symbol_type type;
8335 type = mips_classify_symbolic_expression (*addr, SYMBOL_CONTEXT_LEA);
8336 *addr = mips_strip_unspec_address (*addr);
8340 return Pmode == SImode ? ".dtprelword\t%0" : ".dtpreldword\t%0";
8343 return Pmode == SImode ? ".tprelword\t%0" : ".tpreldword\t%0";
8350 /* Emit either a label, .comm, or .lcomm directive. When using assembler
8351 macros, mark the symbol as written so that mips_asm_output_external
8352 won't emit an .extern for it. STREAM is the output file, NAME is the
8353 name of the symbol, INIT_STRING is the string that should be written
8354 before the symbol and FINAL_STRING is the string that should be
8355 written after it. FINAL_STRING is a printf format that consumes the
8356 remaining arguments. */
8359 mips_declare_object (FILE *stream, const char *name, const char *init_string,
8360 const char *final_string, ...)
8364 fputs (init_string, stream);
8365 assemble_name (stream, name);
8366 va_start (ap, final_string);
8367 vfprintf (stream, final_string, ap);
8370 if (!TARGET_EXPLICIT_RELOCS)
8372 tree name_tree = get_identifier (name);
8373 TREE_ASM_WRITTEN (name_tree) = 1;
8377 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
8378 NAME is the name of the object and ALIGN is the required alignment
8379 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
8380 alignment argument. */
8383 mips_declare_common_object (FILE *stream, const char *name,
8384 const char *init_string,
8385 unsigned HOST_WIDE_INT size,
8386 unsigned int align, bool takes_alignment_p)
8388 if (!takes_alignment_p)
8390 size += (align / BITS_PER_UNIT) - 1;
8391 size -= size % (align / BITS_PER_UNIT);
8392 mips_declare_object (stream, name, init_string,
8393 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
8396 mips_declare_object (stream, name, init_string,
8397 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
8398 size, align / BITS_PER_UNIT);
8401 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
8402 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
8405 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
8406 unsigned HOST_WIDE_INT size,
8409 /* If the target wants uninitialized const declarations in
8410 .rdata then don't put them in .comm. */
8411 if (TARGET_EMBEDDED_DATA
8412 && TARGET_UNINIT_CONST_IN_RODATA
8413 && TREE_CODE (decl) == VAR_DECL
8414 && TREE_READONLY (decl)
8415 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
8417 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
8418 targetm.asm_out.globalize_label (stream, name);
8420 switch_to_section (readonly_data_section);
8421 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
8422 mips_declare_object (stream, name, "",
8423 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
8427 mips_declare_common_object (stream, name, "\n\t.comm\t",
8431 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8432 extern int size_directive_output;
8434 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
8435 definitions except that it uses mips_declare_object to emit the label. */
8438 mips_declare_object_name (FILE *stream, const char *name,
8439 tree decl ATTRIBUTE_UNUSED)
8441 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8442 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
8445 size_directive_output = 0;
8446 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
8450 size_directive_output = 1;
8451 size = int_size_in_bytes (TREE_TYPE (decl));
8452 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8455 mips_declare_object (stream, name, "", ":\n");
8458 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
8461 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
8465 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
8466 if (!flag_inhibit_size_directive
8467 && DECL_SIZE (decl) != 0
8470 && DECL_INITIAL (decl) == error_mark_node
8471 && !size_directive_output)
8475 size_directive_output = 1;
8476 size = int_size_in_bytes (TREE_TYPE (decl));
8477 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8482 /* Return the FOO in the name of the ".mdebug.FOO" section associated
8483 with the current ABI. */
8486 mips_mdebug_abi_name (void)
8499 return TARGET_64BIT ? "eabi64" : "eabi32";
8505 /* Implement TARGET_ASM_FILE_START. */
8508 mips_file_start (void)
8510 default_file_start ();
8512 /* Generate a special section to describe the ABI switches used to
8513 produce the resultant binary. */
8515 /* Record the ABI itself. Modern versions of binutils encode
8516 this information in the ELF header flags, but GDB needs the
8517 information in order to correctly debug binaries produced by
8518 older binutils. See the function mips_gdbarch_init in
8520 fprintf (asm_out_file, "\t.section .mdebug.%s\n\t.previous\n",
8521 mips_mdebug_abi_name ());
8523 /* There is no ELF header flag to distinguish long32 forms of the
8524 EABI from long64 forms. Emit a special section to help tools
8525 such as GDB. Do the same for o64, which is sometimes used with
8527 if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
8528 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n"
8529 "\t.previous\n", TARGET_LONG64 ? 64 : 32);
8531 #ifdef HAVE_AS_GNU_ATTRIBUTE
8535 /* No floating-point operations, -mno-float. */
8536 if (TARGET_NO_FLOAT)
8538 /* Soft-float code, -msoft-float. */
8539 else if (!TARGET_HARD_FLOAT_ABI)
8541 /* Single-float code, -msingle-float. */
8542 else if (!TARGET_DOUBLE_FLOAT)
8544 /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64. */
8545 else if (!TARGET_64BIT && TARGET_FLOAT64)
8547 /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */
8551 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n", attr);
8555 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
8556 if (TARGET_ABICALLS)
8558 fprintf (asm_out_file, "\t.abicalls\n");
8559 if (TARGET_ABICALLS_PIC0)
8560 fprintf (asm_out_file, "\t.option\tpic0\n");
8563 if (flag_verbose_asm)
8564 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
8566 mips_small_data_threshold, mips_arch_info->name, mips_isa);
8569 /* Implement TARGET_ASM_CODE_END. */
8572 mips_code_end (void)
8574 if (mips_need_mips16_rdhwr_p)
8575 mips_output_mips16_rdhwr ();
8578 /* Make the last instruction frame-related and note that it performs
8579 the operation described by FRAME_PATTERN. */
8582 mips_set_frame_expr (rtx frame_pattern)
8586 insn = get_last_insn ();
8587 RTX_FRAME_RELATED_P (insn) = 1;
8588 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
8593 /* Return a frame-related rtx that stores REG at MEM.
8594 REG must be a single register. */
8597 mips_frame_set (rtx mem, rtx reg)
8601 set = gen_rtx_SET (VOIDmode, mem, reg);
8602 RTX_FRAME_RELATED_P (set) = 1;
8607 /* Record that the epilogue has restored call-saved register REG. */
8610 mips_add_cfa_restore (rtx reg)
8612 mips_epilogue.cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg,
8613 mips_epilogue.cfa_restores);
8616 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
8617 mips16e_s2_s8_regs[X], it must also save the registers in indexes
8618 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
8619 static const unsigned char mips16e_s2_s8_regs[] = {
8620 30, 23, 22, 21, 20, 19, 18
8622 static const unsigned char mips16e_a0_a3_regs[] = {
8626 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
8627 ordered from the uppermost in memory to the lowest in memory. */
8628 static const unsigned char mips16e_save_restore_regs[] = {
8629 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
8632 /* Return the index of the lowest X in the range [0, SIZE) for which
8633 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
8636 mips16e_find_first_register (unsigned int mask, const unsigned char *regs,
8641 for (i = 0; i < size; i++)
8642 if (BITSET_P (mask, regs[i]))
8648 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
8649 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
8650 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
8651 is true for all indexes (X, SIZE). */
8654 mips16e_mask_registers (unsigned int *mask_ptr, const unsigned char *regs,
8655 unsigned int size, unsigned int *num_regs_ptr)
8659 i = mips16e_find_first_register (*mask_ptr, regs, size);
8660 for (i++; i < size; i++)
8661 if (!BITSET_P (*mask_ptr, regs[i]))
8664 *mask_ptr |= 1 << regs[i];
8668 /* Return a simplified form of X using the register values in REG_VALUES.
8669 REG_VALUES[R] is the last value assigned to hard register R, or null
8670 if R has not been modified.
8672 This function is rather limited, but is good enough for our purposes. */
8675 mips16e_collect_propagate_value (rtx x, rtx *reg_values)
8677 x = avoid_constant_pool_reference (x);
8681 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
8682 return simplify_gen_unary (GET_CODE (x), GET_MODE (x),
8683 x0, GET_MODE (XEXP (x, 0)));
8686 if (ARITHMETIC_P (x))
8688 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
8689 rtx x1 = mips16e_collect_propagate_value (XEXP (x, 1), reg_values);
8690 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), x0, x1);
8694 && reg_values[REGNO (x)]
8695 && !rtx_unstable_p (reg_values[REGNO (x)]))
8696 return reg_values[REGNO (x)];
8701 /* Return true if (set DEST SRC) stores an argument register into its
8702 caller-allocated save slot, storing the number of that argument
8703 register in *REGNO_PTR if so. REG_VALUES is as for
8704 mips16e_collect_propagate_value. */
8707 mips16e_collect_argument_save_p (rtx dest, rtx src, rtx *reg_values,
8708 unsigned int *regno_ptr)
8710 unsigned int argno, regno;
8711 HOST_WIDE_INT offset, required_offset;
8714 /* Check that this is a word-mode store. */
8715 if (!MEM_P (dest) || !REG_P (src) || GET_MODE (dest) != word_mode)
8718 /* Check that the register being saved is an unmodified argument
8720 regno = REGNO (src);
8721 if (!IN_RANGE (regno, GP_ARG_FIRST, GP_ARG_LAST) || reg_values[regno])
8723 argno = regno - GP_ARG_FIRST;
8725 /* Check whether the address is an appropriate stack-pointer or
8726 frame-pointer access. */
8727 addr = mips16e_collect_propagate_value (XEXP (dest, 0), reg_values);
8728 mips_split_plus (addr, &base, &offset);
8729 required_offset = cfun->machine->frame.total_size + argno * UNITS_PER_WORD;
8730 if (base == hard_frame_pointer_rtx)
8731 required_offset -= cfun->machine->frame.hard_frame_pointer_offset;
8732 else if (base != stack_pointer_rtx)
8734 if (offset != required_offset)
8741 /* A subroutine of mips_expand_prologue, called only when generating
8742 MIPS16e SAVE instructions. Search the start of the function for any
8743 instructions that save argument registers into their caller-allocated
8744 save slots. Delete such instructions and return a value N such that
8745 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
8746 instructions redundant. */
8749 mips16e_collect_argument_saves (void)
8751 rtx reg_values[FIRST_PSEUDO_REGISTER];
8752 rtx insn, next, set, dest, src;
8753 unsigned int nargs, regno;
8755 push_topmost_sequence ();
8757 memset (reg_values, 0, sizeof (reg_values));
8758 for (insn = get_insns (); insn; insn = next)
8760 next = NEXT_INSN (insn);
8761 if (NOTE_P (insn) || DEBUG_INSN_P (insn))
8767 set = PATTERN (insn);
8768 if (GET_CODE (set) != SET)
8771 dest = SET_DEST (set);
8772 src = SET_SRC (set);
8773 if (mips16e_collect_argument_save_p (dest, src, reg_values, ®no))
8775 if (!BITSET_P (cfun->machine->frame.mask, regno))
8778 nargs = MAX (nargs, (regno - GP_ARG_FIRST) + 1);
8781 else if (REG_P (dest) && GET_MODE (dest) == word_mode)
8782 reg_values[REGNO (dest)]
8783 = mips16e_collect_propagate_value (src, reg_values);
8787 pop_topmost_sequence ();
8792 /* Return a move between register REGNO and memory location SP + OFFSET.
8793 REG_PARM_P is true if SP + OFFSET belongs to REG_PARM_STACK_SPACE.
8794 Make the move a load if RESTORE_P, otherwise make it a store. */
8797 mips16e_save_restore_reg (bool restore_p, bool reg_parm_p,
8798 HOST_WIDE_INT offset, unsigned int regno)
8802 mem = gen_frame_mem (SImode, plus_constant (Pmode, stack_pointer_rtx,
8804 reg = gen_rtx_REG (SImode, regno);
8807 mips_add_cfa_restore (reg);
8808 return gen_rtx_SET (VOIDmode, reg, mem);
8811 return gen_rtx_SET (VOIDmode, mem, reg);
8812 return mips_frame_set (mem, reg);
8815 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
8816 The instruction must:
8818 - Allocate or deallocate SIZE bytes in total; SIZE is known
8821 - Save or restore as many registers in *MASK_PTR as possible.
8822 The instruction saves the first registers at the top of the
8823 allocated area, with the other registers below it.
8825 - Save NARGS argument registers above the allocated area.
8827 (NARGS is always zero if RESTORE_P.)
8829 The SAVE and RESTORE instructions cannot save and restore all general
8830 registers, so there may be some registers left over for the caller to
8831 handle. Destructively modify *MASK_PTR so that it contains the registers
8832 that still need to be saved or restored. The caller can save these
8833 registers in the memory immediately below *OFFSET_PTR, which is a
8834 byte offset from the bottom of the allocated stack area. */
8837 mips16e_build_save_restore (bool restore_p, unsigned int *mask_ptr,
8838 HOST_WIDE_INT *offset_ptr, unsigned int nargs,
8842 HOST_WIDE_INT offset, top_offset;
8843 unsigned int i, regno;
8846 gcc_assert (cfun->machine->frame.num_fp == 0);
8848 /* Calculate the number of elements in the PARALLEL. We need one element
8849 for the stack adjustment, one for each argument register save, and one
8850 for each additional register move. */
8852 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
8853 if (BITSET_P (*mask_ptr, mips16e_save_restore_regs[i]))
8856 /* Create the final PARALLEL. */
8857 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (n));
8860 /* Add the stack pointer adjustment. */
8861 set = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8862 plus_constant (Pmode, stack_pointer_rtx,
8863 restore_p ? size : -size));
8864 RTX_FRAME_RELATED_P (set) = 1;
8865 XVECEXP (pattern, 0, n++) = set;
8867 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8868 top_offset = restore_p ? size : 0;
8870 /* Save the arguments. */
8871 for (i = 0; i < nargs; i++)
8873 offset = top_offset + i * UNITS_PER_WORD;
8874 set = mips16e_save_restore_reg (restore_p, true, offset,
8876 XVECEXP (pattern, 0, n++) = set;
8879 /* Then fill in the other register moves. */
8880 offset = top_offset;
8881 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
8883 regno = mips16e_save_restore_regs[i];
8884 if (BITSET_P (*mask_ptr, regno))
8886 offset -= UNITS_PER_WORD;
8887 set = mips16e_save_restore_reg (restore_p, false, offset, regno);
8888 XVECEXP (pattern, 0, n++) = set;
8889 *mask_ptr &= ~(1 << regno);
8893 /* Tell the caller what offset it should use for the remaining registers. */
8894 *offset_ptr = size + (offset - top_offset);
8896 gcc_assert (n == XVECLEN (pattern, 0));
8901 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
8902 pointer. Return true if PATTERN matches the kind of instruction
8903 generated by mips16e_build_save_restore. If INFO is nonnull,
8904 initialize it when returning true. */
8907 mips16e_save_restore_pattern_p (rtx pattern, HOST_WIDE_INT adjust,
8908 struct mips16e_save_restore_info *info)
8910 unsigned int i, nargs, mask, extra;
8911 HOST_WIDE_INT top_offset, save_offset, offset;
8912 rtx set, reg, mem, base;
8915 if (!GENERATE_MIPS16E_SAVE_RESTORE)
8918 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8919 top_offset = adjust > 0 ? adjust : 0;
8921 /* Interpret all other members of the PARALLEL. */
8922 save_offset = top_offset - UNITS_PER_WORD;
8926 for (n = 1; n < XVECLEN (pattern, 0); n++)
8928 /* Check that we have a SET. */
8929 set = XVECEXP (pattern, 0, n);
8930 if (GET_CODE (set) != SET)
8933 /* Check that the SET is a load (if restoring) or a store
8935 mem = adjust > 0 ? SET_SRC (set) : SET_DEST (set);
8939 /* Check that the address is the sum of the stack pointer and a
8940 possibly-zero constant offset. */
8941 mips_split_plus (XEXP (mem, 0), &base, &offset);
8942 if (base != stack_pointer_rtx)
8945 /* Check that SET's other operand is a register. */
8946 reg = adjust > 0 ? SET_DEST (set) : SET_SRC (set);
8950 /* Check for argument saves. */
8951 if (offset == top_offset + nargs * UNITS_PER_WORD
8952 && REGNO (reg) == GP_ARG_FIRST + nargs)
8954 else if (offset == save_offset)
8956 while (mips16e_save_restore_regs[i++] != REGNO (reg))
8957 if (i == ARRAY_SIZE (mips16e_save_restore_regs))
8960 mask |= 1 << REGNO (reg);
8961 save_offset -= UNITS_PER_WORD;
8967 /* Check that the restrictions on register ranges are met. */
8969 mips16e_mask_registers (&mask, mips16e_s2_s8_regs,
8970 ARRAY_SIZE (mips16e_s2_s8_regs), &extra);
8971 mips16e_mask_registers (&mask, mips16e_a0_a3_regs,
8972 ARRAY_SIZE (mips16e_a0_a3_regs), &extra);
8976 /* Make sure that the topmost argument register is not saved twice.
8977 The checks above ensure that the same is then true for the other
8978 argument registers. */
8979 if (nargs > 0 && BITSET_P (mask, GP_ARG_FIRST + nargs - 1))
8982 /* Pass back information, if requested. */
8985 info->nargs = nargs;
8987 info->size = (adjust > 0 ? adjust : -adjust);
8993 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
8994 for the register range [MIN_REG, MAX_REG]. Return a pointer to
8995 the null terminator. */
8998 mips16e_add_register_range (char *s, unsigned int min_reg,
8999 unsigned int max_reg)
9001 if (min_reg != max_reg)
9002 s += sprintf (s, ",%s-%s", reg_names[min_reg], reg_names[max_reg]);
9004 s += sprintf (s, ",%s", reg_names[min_reg]);
9008 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
9009 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
9012 mips16e_output_save_restore (rtx pattern, HOST_WIDE_INT adjust)
9014 static char buffer[300];
9016 struct mips16e_save_restore_info info;
9017 unsigned int i, end;
9020 /* Parse the pattern. */
9021 if (!mips16e_save_restore_pattern_p (pattern, adjust, &info))
9024 /* Add the mnemonic. */
9025 s = strcpy (buffer, adjust > 0 ? "restore\t" : "save\t");
9028 /* Save the arguments. */
9030 s += sprintf (s, "%s-%s,", reg_names[GP_ARG_FIRST],
9031 reg_names[GP_ARG_FIRST + info.nargs - 1]);
9032 else if (info.nargs == 1)
9033 s += sprintf (s, "%s,", reg_names[GP_ARG_FIRST]);
9035 /* Emit the amount of stack space to allocate or deallocate. */
9036 s += sprintf (s, "%d", (int) info.size);
9038 /* Save or restore $16. */
9039 if (BITSET_P (info.mask, 16))
9040 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 16]);
9042 /* Save or restore $17. */
9043 if (BITSET_P (info.mask, 17))
9044 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 17]);
9046 /* Save or restore registers in the range $s2...$s8, which
9047 mips16e_s2_s8_regs lists in decreasing order. Note that this
9048 is a software register range; the hardware registers are not
9049 numbered consecutively. */
9050 end = ARRAY_SIZE (mips16e_s2_s8_regs);
9051 i = mips16e_find_first_register (info.mask, mips16e_s2_s8_regs, end);
9053 s = mips16e_add_register_range (s, mips16e_s2_s8_regs[end - 1],
9054 mips16e_s2_s8_regs[i]);
9056 /* Save or restore registers in the range $a0...$a3. */
9057 end = ARRAY_SIZE (mips16e_a0_a3_regs);
9058 i = mips16e_find_first_register (info.mask, mips16e_a0_a3_regs, end);
9060 s = mips16e_add_register_range (s, mips16e_a0_a3_regs[i],
9061 mips16e_a0_a3_regs[end - 1]);
9063 /* Save or restore $31. */
9064 if (BITSET_P (info.mask, RETURN_ADDR_REGNUM))
9065 s += sprintf (s, ",%s", reg_names[RETURN_ADDR_REGNUM]);
9070 /* Return true if the current function returns its value in a floating-point
9071 register in MIPS16 mode. */
9074 mips16_cfun_returns_in_fpr_p (void)
9076 tree return_type = DECL_RESULT (current_function_decl);
9077 return (TARGET_MIPS16
9078 && TARGET_HARD_FLOAT_ABI
9079 && !aggregate_value_p (return_type, current_function_decl)
9080 && mips_return_mode_in_fpr_p (DECL_MODE (return_type)));
9083 /* Return true if predicate PRED is true for at least one instruction.
9084 Cache the result in *CACHE, and assume that the result is true
9085 if *CACHE is already true. */
9088 mips_find_gp_ref (bool *cache, bool (*pred) (rtx))
9094 push_topmost_sequence ();
9095 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9096 if (USEFUL_INSN_P (insn) && pred (insn))
9101 pop_topmost_sequence ();
9106 /* Return true if INSN refers to the global pointer in an "inflexible" way.
9107 See mips_cfun_has_inflexible_gp_ref_p for details. */
9110 mips_insn_has_inflexible_gp_ref_p (rtx insn)
9112 /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE
9113 indicate that the target could be a traditional MIPS
9114 lazily-binding stub. */
9115 return find_reg_fusage (insn, USE, pic_offset_table_rtx);
9118 /* Return true if the current function refers to the global pointer
9119 in a way that forces $28 to be valid. This means that we can't
9120 change the choice of global pointer, even for NewABI code.
9122 One example of this (and one which needs several checks) is that
9123 $28 must be valid when calling traditional MIPS lazy-binding stubs.
9124 (This restriction does not apply to PLTs.) */
9127 mips_cfun_has_inflexible_gp_ref_p (void)
9129 /* If the function has a nonlocal goto, $28 must hold the correct
9130 global pointer for the target function. That is, the target
9131 of the goto implicitly uses $28. */
9132 if (crtl->has_nonlocal_goto)
9135 if (TARGET_ABICALLS_PIC2)
9137 /* Symbolic accesses implicitly use the global pointer unless
9138 -mexplicit-relocs is in effect. JAL macros to symbolic addresses
9139 might go to traditional MIPS lazy-binding stubs. */
9140 if (!TARGET_EXPLICIT_RELOCS)
9143 /* FUNCTION_PROFILER includes a JAL to _mcount, which again
9144 can be lazily-bound. */
9148 /* MIPS16 functions that return in FPRs need to call an
9149 external libgcc routine. This call is only made explict
9150 during mips_expand_epilogue, and it too might be lazily bound. */
9151 if (mips16_cfun_returns_in_fpr_p ())
9155 return mips_find_gp_ref (&cfun->machine->has_inflexible_gp_insn_p,
9156 mips_insn_has_inflexible_gp_ref_p);
9159 /* Return true if INSN refers to the global pointer in a "flexible" way.
9160 See mips_cfun_has_flexible_gp_ref_p for details. */
9163 mips_insn_has_flexible_gp_ref_p (rtx insn)
9165 return (get_attr_got (insn) != GOT_UNSET
9166 || mips_small_data_pattern_p (PATTERN (insn))
9167 || reg_overlap_mentioned_p (pic_offset_table_rtx, PATTERN (insn)));
9170 /* Return true if the current function references the global pointer,
9171 but if those references do not inherently require the global pointer
9172 to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */
9175 mips_cfun_has_flexible_gp_ref_p (void)
9177 /* Reload can sometimes introduce constant pool references
9178 into a function that otherwise didn't need them. For example,
9179 suppose we have an instruction like:
9181 (set (reg:DF R1) (float:DF (reg:SI R2)))
9183 If R2 turns out to be a constant such as 1, the instruction may
9184 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
9185 the option of using this constant if R2 doesn't get allocated
9188 In cases like these, reload will have added the constant to the
9189 pool but no instruction will yet refer to it. */
9190 if (TARGET_ABICALLS_PIC2 && !reload_completed && crtl->uses_const_pool)
9193 return mips_find_gp_ref (&cfun->machine->has_flexible_gp_insn_p,
9194 mips_insn_has_flexible_gp_ref_p);
9197 /* Return the register that should be used as the global pointer
9198 within this function. Return INVALID_REGNUM if the function
9199 doesn't need a global pointer. */
9202 mips_global_pointer (void)
9206 /* $gp is always available unless we're using a GOT. */
9207 if (!TARGET_USE_GOT)
9208 return GLOBAL_POINTER_REGNUM;
9210 /* If there are inflexible references to $gp, we must use the
9211 standard register. */
9212 if (mips_cfun_has_inflexible_gp_ref_p ())
9213 return GLOBAL_POINTER_REGNUM;
9215 /* If there are no current references to $gp, then the only uses
9216 we can introduce later are those involved in long branches. */
9217 if (TARGET_ABSOLUTE_JUMPS && !mips_cfun_has_flexible_gp_ref_p ())
9218 return INVALID_REGNUM;
9220 /* If the global pointer is call-saved, try to use a call-clobbered
9222 if (TARGET_CALL_SAVED_GP && crtl->is_leaf)
9223 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
9224 if (!df_regs_ever_live_p (regno)
9225 && call_really_used_regs[regno]
9226 && !fixed_regs[regno]
9227 && regno != PIC_FUNCTION_ADDR_REGNUM)
9230 return GLOBAL_POINTER_REGNUM;
9233 /* Return true if the current function's prologue must load the global
9234 pointer value into pic_offset_table_rtx and store the same value in
9235 the function's cprestore slot (if any).
9237 One problem we have to deal with is that, when emitting GOT-based
9238 position independent code, long-branch sequences will need to load
9239 the address of the branch target from the GOT. We don't know until
9240 the very end of compilation whether (and where) the function needs
9241 long branches, so we must ensure that _any_ branch can access the
9242 global pointer in some form. However, we do not want to pessimize
9243 the usual case in which all branches are short.
9245 We handle this as follows:
9247 (1) During reload, we set cfun->machine->global_pointer to
9248 INVALID_REGNUM if we _know_ that the current function
9249 doesn't need a global pointer. This is only valid if
9250 long branches don't need the GOT.
9252 Otherwise, we assume that we might need a global pointer
9253 and pick an appropriate register.
9255 (2) If cfun->machine->global_pointer != INVALID_REGNUM,
9256 we ensure that the global pointer is available at every
9257 block boundary bar entry and exit. We do this in one of two ways:
9259 - If the function has a cprestore slot, we ensure that this
9260 slot is valid at every branch. However, as explained in
9261 point (6) below, there is no guarantee that pic_offset_table_rtx
9262 itself is valid if new uses of the global pointer are introduced
9263 after the first post-epilogue split.
9265 We guarantee that the cprestore slot is valid by loading it
9266 into a fake register, CPRESTORE_SLOT_REGNUM. We then make
9267 this register live at every block boundary bar function entry
9268 and exit. It is then invalid to move the load (and thus the
9269 preceding store) across a block boundary.
9271 - If the function has no cprestore slot, we guarantee that
9272 pic_offset_table_rtx itself is valid at every branch.
9274 See mips_eh_uses for the handling of the register liveness.
9276 (3) During prologue and epilogue generation, we emit "ghost"
9277 placeholder instructions to manipulate the global pointer.
9279 (4) During prologue generation, we set cfun->machine->must_initialize_gp_p
9280 and cfun->machine->must_restore_gp_when_clobbered_p if we already know
9281 that the function needs a global pointer. (There is no need to set
9282 them earlier than this, and doing it as late as possible leads to
9283 fewer false positives.)
9285 (5) If cfun->machine->must_initialize_gp_p is true during a
9286 split_insns pass, we split the ghost instructions into real
9287 instructions. These split instructions can then be optimized in
9288 the usual way. Otherwise, we keep the ghost instructions intact,
9289 and optimize for the case where they aren't needed. We still
9290 have the option of splitting them later, if we need to introduce
9291 new uses of the global pointer.
9293 For example, the scheduler ignores a ghost instruction that
9294 stores $28 to the stack, but it handles the split form of
9295 the ghost instruction as an ordinary store.
9297 (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p
9298 is true during the first post-epilogue split_insns pass, we split
9299 calls and restore_gp patterns into instructions that explicitly
9300 load pic_offset_table_rtx from the cprestore slot. Otherwise,
9301 we split these patterns into instructions that _don't_ load from
9304 If cfun->machine->must_restore_gp_when_clobbered_p is true at the
9305 time of the split, then any instructions that exist at that time
9306 can make free use of pic_offset_table_rtx. However, if we want
9307 to introduce new uses of the global pointer after the split,
9308 we must explicitly load the value from the cprestore slot, since
9309 pic_offset_table_rtx itself might not be valid at a given point
9312 The idea is that we want to be able to delete redundant
9313 loads from the cprestore slot in the usual case where no
9314 long branches are needed.
9316 (7) If cfun->machine->must_initialize_gp_p is still false at the end
9317 of md_reorg, we decide whether the global pointer is needed for
9318 long branches. If so, we set cfun->machine->must_initialize_gp_p
9319 to true and split the ghost instructions into real instructions
9322 Note that the ghost instructions must have a zero length for three reasons:
9324 - Giving the length of the underlying $gp sequence might cause
9325 us to use long branches in cases where they aren't really needed.
9327 - They would perturb things like alignment calculations.
9329 - More importantly, the hazard detection in md_reorg relies on
9330 empty instructions having a zero length.
9332 If we find a long branch and split the ghost instructions at the
9333 end of md_reorg, the split could introduce more long branches.
9334 That isn't a problem though, because we still do the split before
9335 the final shorten_branches pass.
9337 This is extremely ugly, but it seems like the best compromise between
9338 correctness and efficiency. */
9341 mips_must_initialize_gp_p (void)
9343 return cfun->machine->must_initialize_gp_p;
9346 /* Return true if REGNO is a register that is ordinarily call-clobbered
9347 but must nevertheless be preserved by an interrupt handler. */
9350 mips_interrupt_extra_call_saved_reg_p (unsigned int regno)
9352 if (MD_REG_P (regno))
9355 if (TARGET_DSP && DSP_ACC_REG_P (regno))
9358 if (GP_REG_P (regno) && !cfun->machine->use_shadow_register_set_p)
9360 /* $0 is hard-wired. */
9361 if (regno == GP_REG_FIRST)
9364 /* The interrupt handler can treat kernel registers as
9365 scratch registers. */
9366 if (KERNEL_REG_P (regno))
9369 /* The function will return the stack pointer to its original value
9371 if (regno == STACK_POINTER_REGNUM)
9374 /* Otherwise, return true for registers that aren't ordinarily
9376 return call_really_used_regs[regno];
9382 /* Return true if the current function should treat register REGNO
9386 mips_cfun_call_saved_reg_p (unsigned int regno)
9388 /* If the user makes an ordinarily-call-saved register global,
9389 that register is no longer call-saved. */
9390 if (global_regs[regno])
9393 /* Interrupt handlers need to save extra registers. */
9394 if (cfun->machine->interrupt_handler_p
9395 && mips_interrupt_extra_call_saved_reg_p (regno))
9398 /* call_insns preserve $28 unless they explicitly say otherwise,
9399 so call_really_used_regs[] treats $28 as call-saved. However,
9400 we want the ABI property rather than the default call_insn
9402 return (regno == GLOBAL_POINTER_REGNUM
9403 ? TARGET_CALL_SAVED_GP
9404 : !call_really_used_regs[regno]);
9407 /* Return true if the function body might clobber register REGNO.
9408 We know that REGNO is call-saved. */
9411 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno)
9413 /* Some functions should be treated as clobbering all call-saved
9415 if (crtl->saves_all_registers)
9418 /* DF handles cases where a register is explicitly referenced in
9419 the rtl. Incoming values are passed in call-clobbered registers,
9420 so we can assume that any live call-saved register is set within
9422 if (df_regs_ever_live_p (regno))
9425 /* Check for registers that are clobbered by FUNCTION_PROFILER.
9426 These clobbers are not explicit in the rtl. */
9427 if (crtl->profile && MIPS_SAVE_REG_FOR_PROFILING_P (regno))
9430 /* If we're using a call-saved global pointer, the function's
9431 prologue will need to set it up. */
9432 if (cfun->machine->global_pointer == regno)
9435 /* The function's prologue will need to set the frame pointer if
9436 frame_pointer_needed. */
9437 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
9440 /* If a MIPS16 function returns a value in FPRs, its epilogue
9441 will need to call an external libgcc routine. This yet-to-be
9442 generated call_insn will clobber $31. */
9443 if (regno == RETURN_ADDR_REGNUM && mips16_cfun_returns_in_fpr_p ())
9446 /* If REGNO is ordinarily call-clobbered, we must assume that any
9447 called function could modify it. */
9448 if (cfun->machine->interrupt_handler_p
9450 && mips_interrupt_extra_call_saved_reg_p (regno))
9456 /* Return true if the current function must save register REGNO. */
9459 mips_save_reg_p (unsigned int regno)
9461 if (mips_cfun_call_saved_reg_p (regno))
9463 if (mips_cfun_might_clobber_call_saved_reg_p (regno))
9466 /* Save both registers in an FPR pair if either one is used. This is
9467 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
9468 register to be used without the even register. */
9469 if (FP_REG_P (regno)
9470 && MAX_FPRS_PER_FMT == 2
9471 && mips_cfun_might_clobber_call_saved_reg_p (regno + 1))
9475 /* We need to save the incoming return address if __builtin_eh_return
9476 is being used to set a different return address. */
9477 if (regno == RETURN_ADDR_REGNUM && crtl->calls_eh_return)
9483 /* Populate the current function's mips_frame_info structure.
9485 MIPS stack frames look like:
9487 +-------------------------------+
9489 | incoming stack arguments |
9491 +-------------------------------+
9493 | caller-allocated save area |
9494 A | for register arguments |
9496 +-------------------------------+ <-- incoming stack pointer
9498 | callee-allocated save area |
9499 B | for arguments that are |
9500 | split between registers and |
9503 +-------------------------------+ <-- arg_pointer_rtx
9505 C | callee-allocated save area |
9506 | for register varargs |
9508 +-------------------------------+ <-- frame_pointer_rtx
9509 | | + cop0_sp_offset
9510 | COP0 reg save area | + UNITS_PER_WORD
9512 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
9513 | | + UNITS_PER_WORD
9514 | accumulator save area |
9516 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
9517 | | + UNITS_PER_HWFPVALUE
9520 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset
9521 | | + UNITS_PER_WORD
9524 +-------------------------------+ <-- frame_pointer_rtx with
9525 | | \ -fstack-protector
9526 | local variables | | var_size
9528 +-------------------------------+
9530 | $gp save area | | cprestore_size
9532 P +-------------------------------+ <-- hard_frame_pointer_rtx for
9534 | outgoing stack arguments | |
9536 +-------------------------------+ | args_size
9538 | caller-allocated save area | |
9539 | for register arguments | |
9541 +-------------------------------+ <-- stack_pointer_rtx
9542 frame_pointer_rtx without
9544 hard_frame_pointer_rtx for
9547 At least two of A, B and C will be empty.
9549 Dynamic stack allocations such as alloca insert data at point P.
9550 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
9551 hard_frame_pointer_rtx unchanged. */
9554 mips_compute_frame_info (void)
9556 struct mips_frame_info *frame;
9557 HOST_WIDE_INT offset, size;
9558 unsigned int regno, i;
9560 /* Set this function's interrupt properties. */
9561 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
9564 error ("the %<interrupt%> attribute requires a MIPS32r2 processor");
9565 else if (TARGET_HARD_FLOAT)
9566 error ("the %<interrupt%> attribute requires %<-msoft-float%>");
9567 else if (TARGET_MIPS16)
9568 error ("interrupt handlers cannot be MIPS16 functions");
9571 cfun->machine->interrupt_handler_p = true;
9572 cfun->machine->use_shadow_register_set_p =
9573 mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl));
9574 cfun->machine->keep_interrupts_masked_p =
9575 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl));
9576 cfun->machine->use_debug_exception_return_p =
9577 mips_use_debug_exception_return_p (TREE_TYPE
9578 (current_function_decl));
9582 frame = &cfun->machine->frame;
9583 memset (frame, 0, sizeof (*frame));
9584 size = get_frame_size ();
9586 cfun->machine->global_pointer = mips_global_pointer ();
9588 /* The first two blocks contain the outgoing argument area and the $gp save
9589 slot. This area isn't needed in leaf functions, but if the
9590 target-independent frame size is nonzero, we have already committed to
9591 allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */
9592 if ((size == 0 || FRAME_GROWS_DOWNWARD) && crtl->is_leaf)
9594 /* The MIPS 3.0 linker does not like functions that dynamically
9595 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
9596 looks like we are trying to create a second frame pointer to the
9597 function, so allocate some stack space to make it happy. */
9598 if (cfun->calls_alloca)
9599 frame->args_size = REG_PARM_STACK_SPACE (cfun->decl);
9601 frame->args_size = 0;
9602 frame->cprestore_size = 0;
9606 frame->args_size = crtl->outgoing_args_size;
9607 frame->cprestore_size = MIPS_GP_SAVE_AREA_SIZE;
9609 offset = frame->args_size + frame->cprestore_size;
9611 /* Move above the local variables. */
9612 frame->var_size = MIPS_STACK_ALIGN (size);
9613 offset += frame->var_size;
9615 /* Find out which GPRs we need to save. */
9616 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
9617 if (mips_save_reg_p (regno))
9620 frame->mask |= 1 << (regno - GP_REG_FIRST);
9623 /* If this function calls eh_return, we must also save and restore the
9624 EH data registers. */
9625 if (crtl->calls_eh_return)
9626 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; i++)
9629 frame->mask |= 1 << (EH_RETURN_DATA_REGNO (i) - GP_REG_FIRST);
9632 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
9633 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
9634 save all later registers too. */
9635 if (GENERATE_MIPS16E_SAVE_RESTORE)
9637 mips16e_mask_registers (&frame->mask, mips16e_s2_s8_regs,
9638 ARRAY_SIZE (mips16e_s2_s8_regs), &frame->num_gp);
9639 mips16e_mask_registers (&frame->mask, mips16e_a0_a3_regs,
9640 ARRAY_SIZE (mips16e_a0_a3_regs), &frame->num_gp);
9643 /* Move above the GPR save area. */
9644 if (frame->num_gp > 0)
9646 offset += MIPS_STACK_ALIGN (frame->num_gp * UNITS_PER_WORD);
9647 frame->gp_sp_offset = offset - UNITS_PER_WORD;
9650 /* Find out which FPRs we need to save. This loop must iterate over
9651 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
9652 if (TARGET_HARD_FLOAT)
9653 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += MAX_FPRS_PER_FMT)
9654 if (mips_save_reg_p (regno))
9656 frame->num_fp += MAX_FPRS_PER_FMT;
9657 frame->fmask |= ~(~0 << MAX_FPRS_PER_FMT) << (regno - FP_REG_FIRST);
9660 /* Move above the FPR save area. */
9661 if (frame->num_fp > 0)
9663 offset += MIPS_STACK_ALIGN (frame->num_fp * UNITS_PER_FPREG);
9664 frame->fp_sp_offset = offset - UNITS_PER_HWFPVALUE;
9667 /* Add in space for the interrupt context information. */
9668 if (cfun->machine->interrupt_handler_p)
9671 if (mips_save_reg_p (LO_REGNUM) || mips_save_reg_p (HI_REGNUM))
9674 frame->acc_mask |= (1 << 0);
9677 /* Check accumulators 1, 2, 3. */
9678 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
9679 if (mips_save_reg_p (i) || mips_save_reg_p (i + 1))
9682 frame->acc_mask |= 1 << (((i - DSP_ACC_REG_FIRST) / 2) + 1);
9685 /* All interrupt context functions need space to preserve STATUS. */
9686 frame->num_cop0_regs++;
9688 /* If we don't keep interrupts masked, we need to save EPC. */
9689 if (!cfun->machine->keep_interrupts_masked_p)
9690 frame->num_cop0_regs++;
9693 /* Move above the accumulator save area. */
9694 if (frame->num_acc > 0)
9696 /* Each accumulator needs 2 words. */
9697 offset += frame->num_acc * 2 * UNITS_PER_WORD;
9698 frame->acc_sp_offset = offset - UNITS_PER_WORD;
9701 /* Move above the COP0 register save area. */
9702 if (frame->num_cop0_regs > 0)
9704 offset += frame->num_cop0_regs * UNITS_PER_WORD;
9705 frame->cop0_sp_offset = offset - UNITS_PER_WORD;
9708 /* Move above the callee-allocated varargs save area. */
9709 offset += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
9710 frame->arg_pointer_offset = offset;
9712 /* Move above the callee-allocated area for pretend stack arguments. */
9713 offset += crtl->args.pretend_args_size;
9714 frame->total_size = offset;
9716 /* Work out the offsets of the save areas from the top of the frame. */
9717 if (frame->gp_sp_offset > 0)
9718 frame->gp_save_offset = frame->gp_sp_offset - offset;
9719 if (frame->fp_sp_offset > 0)
9720 frame->fp_save_offset = frame->fp_sp_offset - offset;
9721 if (frame->acc_sp_offset > 0)
9722 frame->acc_save_offset = frame->acc_sp_offset - offset;
9723 if (frame->num_cop0_regs > 0)
9724 frame->cop0_save_offset = frame->cop0_sp_offset - offset;
9726 /* MIPS16 code offsets the frame pointer by the size of the outgoing
9727 arguments. This tends to increase the chances of using unextended
9728 instructions for local variables and incoming arguments. */
9730 frame->hard_frame_pointer_offset = frame->args_size;
9733 /* Return the style of GP load sequence that is being used for the
9734 current function. */
9736 enum mips_loadgp_style
9737 mips_current_loadgp_style (void)
9739 if (!TARGET_USE_GOT || cfun->machine->global_pointer == INVALID_REGNUM)
9745 if (TARGET_ABSOLUTE_ABICALLS)
9746 return LOADGP_ABSOLUTE;
9748 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
9751 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
9754 mips_frame_pointer_required (void)
9756 /* If the function contains dynamic stack allocations, we need to
9757 use the frame pointer to access the static parts of the frame. */
9758 if (cfun->calls_alloca)
9761 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
9762 reload may be unable to compute the address of a local variable,
9763 since there is no way to add a large constant to the stack pointer
9764 without using a second temporary register. */
9767 mips_compute_frame_info ();
9768 if (!SMALL_OPERAND (cfun->machine->frame.total_size))
9775 /* Make sure that we're not trying to eliminate to the wrong hard frame
9779 mips_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
9781 return (to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM);
9784 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
9785 or argument pointer. TO is either the stack pointer or hard frame
9789 mips_initial_elimination_offset (int from, int to)
9791 HOST_WIDE_INT offset;
9793 mips_compute_frame_info ();
9795 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */
9798 case FRAME_POINTER_REGNUM:
9799 if (FRAME_GROWS_DOWNWARD)
9800 offset = (cfun->machine->frame.args_size
9801 + cfun->machine->frame.cprestore_size
9802 + cfun->machine->frame.var_size);
9807 case ARG_POINTER_REGNUM:
9808 offset = cfun->machine->frame.arg_pointer_offset;
9815 if (to == HARD_FRAME_POINTER_REGNUM)
9816 offset -= cfun->machine->frame.hard_frame_pointer_offset;
9821 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
9824 mips_extra_live_on_entry (bitmap regs)
9828 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
9829 the global pointer. */
9830 if (!TARGET_ABSOLUTE_ABICALLS)
9831 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
9833 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
9834 the global pointer. */
9836 bitmap_set_bit (regs, MIPS16_PIC_TEMP_REGNUM);
9838 /* See the comment above load_call<mode> for details. */
9839 bitmap_set_bit (regs, GOT_VERSION_REGNUM);
9843 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
9847 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
9852 return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);
9855 /* Emit code to change the current function's return address to
9856 ADDRESS. SCRATCH is available as a scratch register, if needed.
9857 ADDRESS and SCRATCH are both word-mode GPRs. */
9860 mips_set_return_address (rtx address, rtx scratch)
9864 gcc_assert (BITSET_P (cfun->machine->frame.mask, RETURN_ADDR_REGNUM));
9865 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
9866 cfun->machine->frame.gp_sp_offset);
9867 mips_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address);
9870 /* Return true if the current function has a cprestore slot. */
9873 mips_cfun_has_cprestore_slot_p (void)
9875 return (cfun->machine->global_pointer != INVALID_REGNUM
9876 && cfun->machine->frame.cprestore_size > 0);
9879 /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the
9880 cprestore slot. LOAD_P is true if the caller wants to load from
9881 the cprestore slot; it is false if the caller wants to store to
9885 mips_get_cprestore_base_and_offset (rtx *base, HOST_WIDE_INT *offset,
9888 const struct mips_frame_info *frame;
9890 frame = &cfun->machine->frame;
9891 /* .cprestore always uses the stack pointer instead of the frame pointer.
9892 We have a free choice for direct stores for non-MIPS16 functions,
9893 and for MIPS16 functions whose cprestore slot is in range of the
9894 stack pointer. Using the stack pointer would sometimes give more
9895 (early) scheduling freedom, but using the frame pointer would
9896 sometimes give more (late) scheduling freedom. It's hard to
9897 predict which applies to a given function, so let's keep things
9900 Loads must always use the frame pointer in functions that call
9901 alloca, and there's little benefit to using the stack pointer
9903 if (frame_pointer_needed && !(TARGET_CPRESTORE_DIRECTIVE && !load_p))
9905 *base = hard_frame_pointer_rtx;
9906 *offset = frame->args_size - frame->hard_frame_pointer_offset;
9910 *base = stack_pointer_rtx;
9911 *offset = frame->args_size;
9915 /* Return true if X is the load or store address of the cprestore slot;
9916 LOAD_P says which. */
9919 mips_cprestore_address_p (rtx x, bool load_p)
9921 rtx given_base, required_base;
9922 HOST_WIDE_INT given_offset, required_offset;
9924 mips_split_plus (x, &given_base, &given_offset);
9925 mips_get_cprestore_base_and_offset (&required_base, &required_offset, load_p);
9926 return given_base == required_base && given_offset == required_offset;
9929 /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are
9930 going to load from it, false if we are going to store to it.
9931 Use TEMP as a temporary register if need be. */
9934 mips_cprestore_slot (rtx temp, bool load_p)
9937 HOST_WIDE_INT offset;
9939 mips_get_cprestore_base_and_offset (&base, &offset, load_p);
9940 return gen_frame_mem (Pmode, mips_add_offset (temp, base, offset));
9943 /* Emit instructions to save global pointer value GP into cprestore
9944 slot MEM. OFFSET is the offset that MEM applies to the base register.
9946 MEM may not be a legitimate address. If it isn't, TEMP is a
9947 temporary register that can be used, otherwise it is a SCRATCH. */
9950 mips_save_gp_to_cprestore_slot (rtx mem, rtx offset, rtx gp, rtx temp)
9952 if (TARGET_CPRESTORE_DIRECTIVE)
9954 gcc_assert (gp == pic_offset_table_rtx);
9955 emit_insn (PMODE_INSN (gen_cprestore, (mem, offset)));
9958 mips_emit_move (mips_cprestore_slot (temp, false), gp);
9961 /* Restore $gp from its save slot, using TEMP as a temporary base register
9962 if need be. This function is for o32 and o64 abicalls only.
9964 See mips_must_initialize_gp_p for details about how we manage the
9968 mips_restore_gp_from_cprestore_slot (rtx temp)
9970 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI && epilogue_completed);
9972 if (!cfun->machine->must_restore_gp_when_clobbered_p)
9974 emit_note (NOTE_INSN_DELETED);
9980 mips_emit_move (temp, mips_cprestore_slot (temp, true));
9981 mips_emit_move (pic_offset_table_rtx, temp);
9984 mips_emit_move (pic_offset_table_rtx, mips_cprestore_slot (temp, true));
9985 if (!TARGET_EXPLICIT_RELOCS)
9986 emit_insn (gen_blockage ());
9989 /* A function to save or store a register. The first argument is the
9990 register and the second is the stack slot. */
9991 typedef void (*mips_save_restore_fn) (rtx, rtx);
9993 /* Use FN to save or restore register REGNO. MODE is the register's
9994 mode and OFFSET is the offset of its save slot from the current
9998 mips_save_restore_reg (enum machine_mode mode, int regno,
9999 HOST_WIDE_INT offset, mips_save_restore_fn fn)
10003 mem = gen_frame_mem (mode, plus_constant (Pmode, stack_pointer_rtx,
10005 fn (gen_rtx_REG (mode, regno), mem);
10008 /* Call FN for each accumlator that is saved by the current function.
10009 SP_OFFSET is the offset of the current stack pointer from the start
10013 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
10015 HOST_WIDE_INT offset;
10018 offset = cfun->machine->frame.acc_sp_offset - sp_offset;
10019 if (BITSET_P (cfun->machine->frame.acc_mask, 0))
10021 mips_save_restore_reg (word_mode, LO_REGNUM, offset, fn);
10022 offset -= UNITS_PER_WORD;
10023 mips_save_restore_reg (word_mode, HI_REGNUM, offset, fn);
10024 offset -= UNITS_PER_WORD;
10027 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
10028 if (BITSET_P (cfun->machine->frame.acc_mask,
10029 ((regno - DSP_ACC_REG_FIRST) / 2) + 1))
10031 mips_save_restore_reg (word_mode, regno, offset, fn);
10032 offset -= UNITS_PER_WORD;
10036 /* Call FN for each register that is saved by the current function.
10037 SP_OFFSET is the offset of the current stack pointer from the start
10041 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset,
10042 mips_save_restore_fn fn)
10044 enum machine_mode fpr_mode;
10045 HOST_WIDE_INT offset;
10048 /* Save registers starting from high to low. The debuggers prefer at least
10049 the return register be stored at func+4, and also it allows us not to
10050 need a nop in the epilogue if at least one register is reloaded in
10051 addition to return address. */
10052 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
10053 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
10054 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
10056 /* Record the ra offset for use by mips_function_profiler. */
10057 if (regno == RETURN_ADDR_REGNUM)
10058 cfun->machine->frame.ra_fp_offset = offset + sp_offset;
10059 mips_save_restore_reg (word_mode, regno, offset, fn);
10060 offset -= UNITS_PER_WORD;
10063 /* This loop must iterate over the same space as its companion in
10064 mips_compute_frame_info. */
10065 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
10066 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
10067 for (regno = FP_REG_LAST - MAX_FPRS_PER_FMT + 1;
10068 regno >= FP_REG_FIRST;
10069 regno -= MAX_FPRS_PER_FMT)
10070 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
10072 mips_save_restore_reg (fpr_mode, regno, offset, fn);
10073 offset -= GET_MODE_SIZE (fpr_mode);
10077 /* Return true if a move between register REGNO and its save slot (MEM)
10078 can be done in a single move. LOAD_P is true if we are loading
10079 from the slot, false if we are storing to it. */
10082 mips_direct_save_slot_move_p (unsigned int regno, rtx mem, bool load_p)
10084 /* There is a specific MIPS16 instruction for saving $31 to the stack. */
10085 if (TARGET_MIPS16 && !load_p && regno == RETURN_ADDR_REGNUM)
10088 return mips_secondary_reload_class (REGNO_REG_CLASS (regno),
10089 GET_MODE (mem), mem, load_p) == NO_REGS;
10092 /* Emit a move from SRC to DEST, given that one of them is a register
10093 save slot and that the other is a register. TEMP is a temporary
10094 GPR of the same mode that is available if need be. */
10097 mips_emit_save_slot_move (rtx dest, rtx src, rtx temp)
10099 unsigned int regno;
10104 regno = REGNO (src);
10109 regno = REGNO (dest);
10113 if (regno == cfun->machine->global_pointer && !mips_must_initialize_gp_p ())
10115 /* We don't yet know whether we'll need this instruction or not.
10116 Postpone the decision by emitting a ghost move. This move
10117 is specifically not frame-related; only the split version is. */
10119 emit_insn (gen_move_gpdi (dest, src));
10121 emit_insn (gen_move_gpsi (dest, src));
10125 if (regno == HI_REGNUM)
10129 mips_emit_move (temp, src);
10131 emit_insn (gen_mthisi_di (gen_rtx_REG (TImode, MD_REG_FIRST),
10132 temp, gen_rtx_REG (DImode, LO_REGNUM)));
10134 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode, MD_REG_FIRST),
10135 temp, gen_rtx_REG (SImode, LO_REGNUM)));
10140 emit_insn (gen_mfhidi_ti (temp,
10141 gen_rtx_REG (TImode, MD_REG_FIRST)));
10143 emit_insn (gen_mfhisi_di (temp,
10144 gen_rtx_REG (DImode, MD_REG_FIRST)));
10145 mips_emit_move (dest, temp);
10148 else if (mips_direct_save_slot_move_p (regno, mem, mem == src))
10149 mips_emit_move (dest, src);
10152 gcc_assert (!reg_overlap_mentioned_p (dest, temp));
10153 mips_emit_move (temp, src);
10154 mips_emit_move (dest, temp);
10157 mips_set_frame_expr (mips_frame_set (dest, src));
10160 /* If we're generating n32 or n64 abicalls, and the current function
10161 does not use $28 as its global pointer, emit a cplocal directive.
10162 Use pic_offset_table_rtx as the argument to the directive. */
10165 mips_output_cplocal (void)
10167 if (!TARGET_EXPLICIT_RELOCS
10168 && mips_must_initialize_gp_p ()
10169 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
10170 output_asm_insn (".cplocal %+", 0);
10173 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
10176 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
10178 const char *fnname;
10180 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
10181 floating-point arguments. */
10183 && TARGET_HARD_FLOAT_ABI
10184 && crtl->args.info.fp_code != 0)
10185 mips16_build_function_stub ();
10187 /* Get the function name the same way that toplev.c does before calling
10188 assemble_start_function. This is needed so that the name used here
10189 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10190 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
10191 mips_start_function_definition (fnname, TARGET_MIPS16);
10193 /* Output MIPS-specific frame information. */
10194 if (!flag_inhibit_size_directive)
10196 const struct mips_frame_info *frame;
10198 frame = &cfun->machine->frame;
10200 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
10202 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
10203 "# vars= " HOST_WIDE_INT_PRINT_DEC
10205 ", args= " HOST_WIDE_INT_PRINT_DEC
10206 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
10207 reg_names[frame_pointer_needed
10208 ? HARD_FRAME_POINTER_REGNUM
10209 : STACK_POINTER_REGNUM],
10210 (frame_pointer_needed
10211 ? frame->total_size - frame->hard_frame_pointer_offset
10212 : frame->total_size),
10213 reg_names[RETURN_ADDR_REGNUM],
10215 frame->num_gp, frame->num_fp,
10217 frame->cprestore_size);
10219 /* .mask MASK, OFFSET. */
10220 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
10221 frame->mask, frame->gp_save_offset);
10223 /* .fmask MASK, OFFSET. */
10224 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
10225 frame->fmask, frame->fp_save_offset);
10228 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
10229 Also emit the ".set noreorder; .set nomacro" sequence for functions
10231 if (mips_must_initialize_gp_p ()
10232 && mips_current_loadgp_style () == LOADGP_OLDABI)
10236 /* This is a fixed-form sequence. The position of the
10237 first two instructions is important because of the
10238 way _gp_disp is defined. */
10239 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
10240 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
10241 output_asm_insn ("sll\t$2,16", 0);
10242 output_asm_insn ("addu\t$2,$3", 0);
10246 /* .cpload must be in a .set noreorder but not a
10247 .set nomacro block. */
10248 mips_push_asm_switch (&mips_noreorder);
10249 output_asm_insn (".cpload\t%^", 0);
10250 if (!cfun->machine->all_noreorder_p)
10251 mips_pop_asm_switch (&mips_noreorder);
10253 mips_push_asm_switch (&mips_nomacro);
10256 else if (cfun->machine->all_noreorder_p)
10258 mips_push_asm_switch (&mips_noreorder);
10259 mips_push_asm_switch (&mips_nomacro);
10262 /* Tell the assembler which register we're using as the global
10263 pointer. This is needed for thunks, since they can use either
10264 explicit relocs or assembler macros. */
10265 mips_output_cplocal ();
10268 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
10271 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
10272 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
10274 const char *fnname;
10276 /* Reinstate the normal $gp. */
10277 SET_REGNO (pic_offset_table_rtx, GLOBAL_POINTER_REGNUM);
10278 mips_output_cplocal ();
10280 if (cfun->machine->all_noreorder_p)
10282 mips_pop_asm_switch (&mips_nomacro);
10283 mips_pop_asm_switch (&mips_noreorder);
10286 /* Get the function name the same way that toplev.c does before calling
10287 assemble_start_function. This is needed so that the name used here
10288 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10289 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
10290 mips_end_function_definition (fnname);
10293 /* Emit an optimisation barrier for accesses to the current frame. */
10296 mips_frame_barrier (void)
10298 emit_clobber (gen_frame_mem (BLKmode, stack_pointer_rtx));
10301 /* Save register REG to MEM. Make the instruction frame-related. */
10304 mips_save_reg (rtx reg, rtx mem)
10306 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
10310 if (mips_split_64bit_move_p (mem, reg))
10311 mips_split_doubleword_move (mem, reg);
10313 mips_emit_move (mem, reg);
10315 x1 = mips_frame_set (mips_subword (mem, false),
10316 mips_subword (reg, false));
10317 x2 = mips_frame_set (mips_subword (mem, true),
10318 mips_subword (reg, true));
10319 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
10322 mips_emit_save_slot_move (mem, reg, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
10325 /* The __gnu_local_gp symbol. */
10327 static GTY(()) rtx mips_gnu_local_gp;
10329 /* If we're generating n32 or n64 abicalls, emit instructions
10330 to set up the global pointer. */
10333 mips_emit_loadgp (void)
10335 rtx addr, offset, incoming_address, base, index, pic_reg;
10337 pic_reg = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
10338 switch (mips_current_loadgp_style ())
10340 case LOADGP_ABSOLUTE:
10341 if (mips_gnu_local_gp == NULL)
10343 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
10344 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
10346 emit_insn (PMODE_INSN (gen_loadgp_absolute,
10347 (pic_reg, mips_gnu_local_gp)));
10350 case LOADGP_OLDABI:
10351 /* Added by mips_output_function_prologue. */
10354 case LOADGP_NEWABI:
10355 addr = XEXP (DECL_RTL (current_function_decl), 0);
10356 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
10357 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
10358 emit_insn (PMODE_INSN (gen_loadgp_newabi,
10359 (pic_reg, offset, incoming_address)));
10363 base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE));
10364 index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX));
10365 emit_insn (PMODE_INSN (gen_loadgp_rtp, (pic_reg, base, index)));
10373 emit_insn (PMODE_INSN (gen_copygp_mips16,
10374 (pic_offset_table_rtx, pic_reg)));
10376 /* Emit a blockage if there are implicit uses of the GP register.
10377 This includes profiled functions, because FUNCTION_PROFILE uses
10379 if (!TARGET_EXPLICIT_RELOCS || crtl->profile)
10380 emit_insn (gen_loadgp_blockage ());
10383 /* A for_each_rtx callback. Stop the search if *X is a kernel register. */
10386 mips_kernel_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
10388 return REG_P (*x) && KERNEL_REG_P (REGNO (*x));
10391 /* Expand the "prologue" pattern. */
10394 mips_expand_prologue (void)
10396 const struct mips_frame_info *frame;
10397 HOST_WIDE_INT size;
10398 unsigned int nargs;
10401 if (cfun->machine->global_pointer != INVALID_REGNUM)
10403 /* Check whether an insn uses pic_offset_table_rtx, either explicitly
10404 or implicitly. If so, we can commit to using a global pointer
10405 straight away, otherwise we need to defer the decision. */
10406 if (mips_cfun_has_inflexible_gp_ref_p ()
10407 || mips_cfun_has_flexible_gp_ref_p ())
10409 cfun->machine->must_initialize_gp_p = true;
10410 cfun->machine->must_restore_gp_when_clobbered_p = true;
10413 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
10416 frame = &cfun->machine->frame;
10417 size = frame->total_size;
10419 if (flag_stack_usage_info)
10420 current_function_static_stack_size = size;
10422 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
10423 bytes beforehand; this is enough to cover the register save area
10424 without going out of range. */
10425 if (((frame->mask | frame->fmask | frame->acc_mask) != 0)
10426 || frame->num_cop0_regs > 0)
10428 HOST_WIDE_INT step1;
10430 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
10431 if (GENERATE_MIPS16E_SAVE_RESTORE)
10433 HOST_WIDE_INT offset;
10434 unsigned int mask, regno;
10436 /* Try to merge argument stores into the save instruction. */
10437 nargs = mips16e_collect_argument_saves ();
10439 /* Build the save instruction. */
10440 mask = frame->mask;
10441 insn = mips16e_build_save_restore (false, &mask, &offset,
10443 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10444 mips_frame_barrier ();
10447 /* Check if we need to save other registers. */
10448 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
10449 if (BITSET_P (mask, regno - GP_REG_FIRST))
10451 offset -= UNITS_PER_WORD;
10452 mips_save_restore_reg (word_mode, regno,
10453 offset, mips_save_reg);
10458 if (cfun->machine->interrupt_handler_p)
10460 HOST_WIDE_INT offset;
10463 /* If this interrupt is using a shadow register set, we need to
10464 get the stack pointer from the previous register set. */
10465 if (cfun->machine->use_shadow_register_set_p)
10466 emit_insn (gen_mips_rdpgpr (stack_pointer_rtx,
10467 stack_pointer_rtx));
10469 if (!cfun->machine->keep_interrupts_masked_p)
10471 /* Move from COP0 Cause to K0. */
10472 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K0_REG_NUM),
10473 gen_rtx_REG (SImode,
10474 COP0_CAUSE_REG_NUM)));
10475 /* Move from COP0 EPC to K1. */
10476 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
10477 gen_rtx_REG (SImode,
10478 COP0_EPC_REG_NUM)));
10481 /* Allocate the first part of the frame. */
10482 insn = gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx,
10484 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10485 mips_frame_barrier ();
10488 /* Start at the uppermost location for saving. */
10489 offset = frame->cop0_sp_offset - size;
10490 if (!cfun->machine->keep_interrupts_masked_p)
10492 /* Push EPC into its stack slot. */
10493 mem = gen_frame_mem (word_mode,
10494 plus_constant (Pmode, stack_pointer_rtx,
10496 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
10497 offset -= UNITS_PER_WORD;
10500 /* Move from COP0 Status to K1. */
10501 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
10502 gen_rtx_REG (SImode,
10503 COP0_STATUS_REG_NUM)));
10505 /* Right justify the RIPL in k0. */
10506 if (!cfun->machine->keep_interrupts_masked_p)
10507 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode, K0_REG_NUM),
10508 gen_rtx_REG (SImode, K0_REG_NUM),
10509 GEN_INT (CAUSE_IPL)));
10511 /* Push Status into its stack slot. */
10512 mem = gen_frame_mem (word_mode,
10513 plus_constant (Pmode, stack_pointer_rtx,
10515 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
10516 offset -= UNITS_PER_WORD;
10518 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
10519 if (!cfun->machine->keep_interrupts_masked_p)
10520 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
10523 gen_rtx_REG (SImode, K0_REG_NUM)));
10525 if (!cfun->machine->keep_interrupts_masked_p)
10526 /* Enable interrupts by clearing the KSU ERL and EXL bits.
10527 IE is already the correct value, so we don't have to do
10528 anything explicit. */
10529 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
10532 gen_rtx_REG (SImode, GP_REG_FIRST)));
10534 /* Disable interrupts by clearing the KSU, ERL, EXL,
10536 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
10539 gen_rtx_REG (SImode, GP_REG_FIRST)));
10543 insn = gen_add3_insn (stack_pointer_rtx,
10546 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10547 mips_frame_barrier ();
10550 mips_for_each_saved_acc (size, mips_save_reg);
10551 mips_for_each_saved_gpr_and_fpr (size, mips_save_reg);
10555 /* Allocate the rest of the frame. */
10558 if (SMALL_OPERAND (-size))
10559 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
10561 GEN_INT (-size)))) = 1;
10564 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
10567 /* There are no instructions to add or subtract registers
10568 from the stack pointer, so use the frame pointer as a
10569 temporary. We should always be using a frame pointer
10570 in this case anyway. */
10571 gcc_assert (frame_pointer_needed);
10572 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
10573 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
10574 hard_frame_pointer_rtx,
10575 MIPS_PROLOGUE_TEMP (Pmode)));
10576 mips_emit_move (stack_pointer_rtx, hard_frame_pointer_rtx);
10579 emit_insn (gen_sub3_insn (stack_pointer_rtx,
10581 MIPS_PROLOGUE_TEMP (Pmode)));
10583 /* Describe the combined effect of the previous instructions. */
10584 mips_set_frame_expr
10585 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
10586 plus_constant (Pmode, stack_pointer_rtx, -size)));
10588 mips_frame_barrier ();
10591 /* Set up the frame pointer, if we're using one. */
10592 if (frame_pointer_needed)
10594 HOST_WIDE_INT offset;
10596 offset = frame->hard_frame_pointer_offset;
10599 insn = mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
10600 RTX_FRAME_RELATED_P (insn) = 1;
10602 else if (SMALL_OPERAND (offset))
10604 insn = gen_add3_insn (hard_frame_pointer_rtx,
10605 stack_pointer_rtx, GEN_INT (offset));
10606 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10610 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (offset));
10611 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
10612 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
10613 hard_frame_pointer_rtx,
10614 MIPS_PROLOGUE_TEMP (Pmode)));
10615 mips_set_frame_expr
10616 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
10617 plus_constant (Pmode, stack_pointer_rtx, offset)));
10621 mips_emit_loadgp ();
10623 /* Initialize the $gp save slot. */
10624 if (mips_cfun_has_cprestore_slot_p ())
10626 rtx base, mem, gp, temp;
10627 HOST_WIDE_INT offset;
10629 mips_get_cprestore_base_and_offset (&base, &offset, false);
10630 mem = gen_frame_mem (Pmode, plus_constant (Pmode, base, offset));
10631 gp = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
10632 temp = (SMALL_OPERAND (offset)
10633 ? gen_rtx_SCRATCH (Pmode)
10634 : MIPS_PROLOGUE_TEMP (Pmode));
10635 emit_insn (PMODE_INSN (gen_potential_cprestore,
10636 (mem, GEN_INT (offset), gp, temp)));
10638 mips_get_cprestore_base_and_offset (&base, &offset, true);
10639 mem = gen_frame_mem (Pmode, plus_constant (Pmode, base, offset));
10640 emit_insn (PMODE_INSN (gen_use_cprestore, (mem)));
10643 /* We need to search back to the last use of K0 or K1. */
10644 if (cfun->machine->interrupt_handler_p)
10646 for (insn = get_last_insn (); insn != NULL_RTX; insn = PREV_INSN (insn))
10648 && for_each_rtx (&PATTERN (insn), mips_kernel_reg_p, NULL))
10650 /* Emit a move from K1 to COP0 Status after insn. */
10651 gcc_assert (insn != NULL_RTX);
10652 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
10653 gen_rtx_REG (SImode, K1_REG_NUM)),
10657 /* If we are profiling, make sure no instructions are scheduled before
10658 the call to mcount. */
10660 emit_insn (gen_blockage ());
10663 /* Attach all pending register saves to the previous instruction.
10664 Return that instruction. */
10667 mips_epilogue_emit_cfa_restores (void)
10671 insn = get_last_insn ();
10672 gcc_assert (insn && !REG_NOTES (insn));
10673 if (mips_epilogue.cfa_restores)
10675 RTX_FRAME_RELATED_P (insn) = 1;
10676 REG_NOTES (insn) = mips_epilogue.cfa_restores;
10677 mips_epilogue.cfa_restores = 0;
10682 /* Like mips_epilogue_emit_cfa_restores, but also record that the CFA is
10683 now at REG + OFFSET. */
10686 mips_epilogue_set_cfa (rtx reg, HOST_WIDE_INT offset)
10690 insn = mips_epilogue_emit_cfa_restores ();
10691 if (reg != mips_epilogue.cfa_reg || offset != mips_epilogue.cfa_offset)
10693 RTX_FRAME_RELATED_P (insn) = 1;
10694 REG_NOTES (insn) = alloc_reg_note (REG_CFA_DEF_CFA,
10695 plus_constant (Pmode, reg, offset),
10697 mips_epilogue.cfa_reg = reg;
10698 mips_epilogue.cfa_offset = offset;
10702 /* Emit instructions to restore register REG from slot MEM. Also update
10703 the cfa_restores list. */
10706 mips_restore_reg (rtx reg, rtx mem)
10708 /* There's no MIPS16 instruction to load $31 directly. Load into
10709 $7 instead and adjust the return insn appropriately. */
10710 if (TARGET_MIPS16 && REGNO (reg) == RETURN_ADDR_REGNUM)
10711 reg = gen_rtx_REG (GET_MODE (reg), GP_REG_FIRST + 7);
10712 else if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
10714 mips_add_cfa_restore (mips_subword (reg, true));
10715 mips_add_cfa_restore (mips_subword (reg, false));
10718 mips_add_cfa_restore (reg);
10720 mips_emit_save_slot_move (reg, mem, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
10721 if (REGNO (reg) == REGNO (mips_epilogue.cfa_reg))
10722 /* The CFA is currently defined in terms of the register whose
10723 value we have just restored. Redefine the CFA in terms of
10724 the stack pointer. */
10725 mips_epilogue_set_cfa (stack_pointer_rtx,
10726 mips_epilogue.cfa_restore_sp_offset);
10729 /* Emit code to set the stack pointer to BASE + OFFSET, given that
10730 BASE + OFFSET is NEW_FRAME_SIZE bytes below the top of the frame.
10731 BASE, if not the stack pointer, is available as a temporary. */
10734 mips_deallocate_stack (rtx base, rtx offset, HOST_WIDE_INT new_frame_size)
10736 if (base == stack_pointer_rtx && offset == const0_rtx)
10739 mips_frame_barrier ();
10740 if (offset == const0_rtx)
10742 emit_move_insn (stack_pointer_rtx, base);
10743 mips_epilogue_set_cfa (stack_pointer_rtx, new_frame_size);
10745 else if (TARGET_MIPS16 && base != stack_pointer_rtx)
10747 emit_insn (gen_add3_insn (base, base, offset));
10748 mips_epilogue_set_cfa (base, new_frame_size);
10749 emit_move_insn (stack_pointer_rtx, base);
10753 emit_insn (gen_add3_insn (stack_pointer_rtx, base, offset));
10754 mips_epilogue_set_cfa (stack_pointer_rtx, new_frame_size);
10758 /* Emit any instructions needed before a return. */
10761 mips_expand_before_return (void)
10763 /* When using a call-clobbered gp, we start out with unified call
10764 insns that include instructions to restore the gp. We then split
10765 these unified calls after reload. These split calls explicitly
10766 clobber gp, so there is no need to define
10767 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
10769 For consistency, we should also insert an explicit clobber of $28
10770 before return insns, so that the post-reload optimizers know that
10771 the register is not live on exit. */
10772 if (TARGET_CALL_CLOBBERED_GP)
10773 emit_clobber (pic_offset_table_rtx);
10776 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
10780 mips_expand_epilogue (bool sibcall_p)
10782 const struct mips_frame_info *frame;
10783 HOST_WIDE_INT step1, step2;
10784 rtx base, adjust, insn;
10786 if (!sibcall_p && mips_can_use_return_insn ())
10788 emit_jump_insn (gen_return ());
10792 /* In MIPS16 mode, if the return value should go into a floating-point
10793 register, we need to call a helper routine to copy it over. */
10794 if (mips16_cfun_returns_in_fpr_p ())
10795 mips16_copy_fpr_return_value ();
10797 /* Split the frame into two. STEP1 is the amount of stack we should
10798 deallocate before restoring the registers. STEP2 is the amount we
10799 should deallocate afterwards.
10801 Start off by assuming that no registers need to be restored. */
10802 frame = &cfun->machine->frame;
10803 step1 = frame->total_size;
10806 /* Work out which register holds the frame address. */
10807 if (!frame_pointer_needed)
10808 base = stack_pointer_rtx;
10811 base = hard_frame_pointer_rtx;
10812 step1 -= frame->hard_frame_pointer_offset;
10814 mips_epilogue.cfa_reg = base;
10815 mips_epilogue.cfa_offset = step1;
10816 mips_epilogue.cfa_restores = NULL_RTX;
10818 /* If we need to restore registers, deallocate as much stack as
10819 possible in the second step without going out of range. */
10820 if ((frame->mask | frame->fmask | frame->acc_mask) != 0
10821 || frame->num_cop0_regs > 0)
10823 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
10827 /* Get an rtx for STEP1 that we can add to BASE. */
10828 adjust = GEN_INT (step1);
10829 if (!SMALL_OPERAND (step1))
10831 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), adjust);
10832 adjust = MIPS_EPILOGUE_TEMP (Pmode);
10834 mips_deallocate_stack (base, adjust, step2);
10836 /* If we're using addressing macros, $gp is implicitly used by all
10837 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
10839 if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS)
10840 emit_insn (gen_blockage ());
10842 mips_epilogue.cfa_restore_sp_offset = step2;
10843 if (GENERATE_MIPS16E_SAVE_RESTORE && frame->mask != 0)
10845 unsigned int regno, mask;
10846 HOST_WIDE_INT offset;
10849 /* Generate the restore instruction. */
10850 mask = frame->mask;
10851 restore = mips16e_build_save_restore (true, &mask, &offset, 0, step2);
10853 /* Restore any other registers manually. */
10854 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
10855 if (BITSET_P (mask, regno - GP_REG_FIRST))
10857 offset -= UNITS_PER_WORD;
10858 mips_save_restore_reg (word_mode, regno, offset, mips_restore_reg);
10861 /* Restore the remaining registers and deallocate the final bit
10863 mips_frame_barrier ();
10864 emit_insn (restore);
10865 mips_epilogue_set_cfa (stack_pointer_rtx, 0);
10869 /* Restore the registers. */
10870 mips_for_each_saved_acc (frame->total_size - step2, mips_restore_reg);
10871 mips_for_each_saved_gpr_and_fpr (frame->total_size - step2,
10874 if (cfun->machine->interrupt_handler_p)
10876 HOST_WIDE_INT offset;
10879 offset = frame->cop0_sp_offset - (frame->total_size - step2);
10880 if (!cfun->machine->keep_interrupts_masked_p)
10882 /* Restore the original EPC. */
10883 mem = gen_frame_mem (word_mode,
10884 plus_constant (Pmode, stack_pointer_rtx,
10886 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
10887 offset -= UNITS_PER_WORD;
10889 /* Move to COP0 EPC. */
10890 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_EPC_REG_NUM),
10891 gen_rtx_REG (SImode, K0_REG_NUM)));
10894 /* Restore the original Status. */
10895 mem = gen_frame_mem (word_mode,
10896 plus_constant (Pmode, stack_pointer_rtx,
10898 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
10899 offset -= UNITS_PER_WORD;
10901 /* If we don't use shoadow register set, we need to update SP. */
10902 if (!cfun->machine->use_shadow_register_set_p)
10903 mips_deallocate_stack (stack_pointer_rtx, GEN_INT (step2), 0);
10905 /* The choice of position is somewhat arbitrary in this case. */
10906 mips_epilogue_emit_cfa_restores ();
10908 /* Move to COP0 Status. */
10909 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
10910 gen_rtx_REG (SImode, K0_REG_NUM)));
10913 /* Deallocate the final bit of the frame. */
10914 mips_deallocate_stack (stack_pointer_rtx, GEN_INT (step2), 0);
10916 gcc_assert (!mips_epilogue.cfa_restores);
10918 /* Add in the __builtin_eh_return stack adjustment. We need to
10919 use a temporary in MIPS16 code. */
10920 if (crtl->calls_eh_return)
10924 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
10925 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
10926 MIPS_EPILOGUE_TEMP (Pmode),
10927 EH_RETURN_STACKADJ_RTX));
10928 mips_emit_move (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
10931 emit_insn (gen_add3_insn (stack_pointer_rtx,
10933 EH_RETURN_STACKADJ_RTX));
10938 mips_expand_before_return ();
10939 if (cfun->machine->interrupt_handler_p)
10941 /* Interrupt handlers generate eret or deret. */
10942 if (cfun->machine->use_debug_exception_return_p)
10943 emit_jump_insn (gen_mips_deret ());
10945 emit_jump_insn (gen_mips_eret ());
10951 /* When generating MIPS16 code, the normal
10952 mips_for_each_saved_gpr_and_fpr path will restore the return
10953 address into $7 rather than $31. */
10955 && !GENERATE_MIPS16E_SAVE_RESTORE
10956 && BITSET_P (frame->mask, RETURN_ADDR_REGNUM))
10958 /* simple_returns cannot rely on values that are only available
10959 on paths through the epilogue (because return paths that do
10960 not pass through the epilogue may nevertheless reuse a
10961 simple_return that occurs at the end of the epilogue).
10962 Use a normal return here instead. */
10963 rtx reg = gen_rtx_REG (Pmode, GP_REG_FIRST + 7);
10964 pat = gen_return_internal (reg);
10968 rtx reg = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
10969 pat = gen_simple_return_internal (reg);
10971 emit_jump_insn (pat);
10975 /* Search from the beginning to the first use of K0 or K1. */
10976 if (cfun->machine->interrupt_handler_p
10977 && !cfun->machine->keep_interrupts_masked_p)
10979 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
10981 && for_each_rtx (&PATTERN(insn), mips_kernel_reg_p, NULL))
10983 gcc_assert (insn != NULL_RTX);
10984 /* Insert disable interrupts before the first use of K0 or K1. */
10985 emit_insn_before (gen_mips_di (), insn);
10986 emit_insn_before (gen_mips_ehb (), insn);
10990 /* Return nonzero if this function is known to have a null epilogue.
10991 This allows the optimizer to omit jumps to jumps if no stack
10995 mips_can_use_return_insn (void)
10997 /* Interrupt handlers need to go through the epilogue. */
10998 if (cfun->machine->interrupt_handler_p)
11001 if (!reload_completed)
11007 /* In MIPS16 mode, a function that returns a floating-point value
11008 needs to arrange to copy the return value into the floating-point
11010 if (mips16_cfun_returns_in_fpr_p ())
11013 return cfun->machine->frame.total_size == 0;
11016 /* Return true if register REGNO can store a value of mode MODE.
11017 The result of this function is cached in mips_hard_regno_mode_ok. */
11020 mips_hard_regno_mode_ok_p (unsigned int regno, enum machine_mode mode)
11023 enum mode_class mclass;
11025 if (mode == CCV2mode)
11026 return (ISA_HAS_8CC
11027 && ST_REG_P (regno)
11028 && (regno - ST_REG_FIRST) % 2 == 0);
11030 if (mode == CCV4mode)
11031 return (ISA_HAS_8CC
11032 && ST_REG_P (regno)
11033 && (regno - ST_REG_FIRST) % 4 == 0);
11035 if (mode == CCmode)
11038 return regno == FPSW_REGNUM;
11040 return (ST_REG_P (regno)
11041 || GP_REG_P (regno)
11042 || FP_REG_P (regno));
11045 size = GET_MODE_SIZE (mode);
11046 mclass = GET_MODE_CLASS (mode);
11048 if (GP_REG_P (regno))
11049 return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD;
11051 if (FP_REG_P (regno)
11052 && (((regno - FP_REG_FIRST) % MAX_FPRS_PER_FMT) == 0
11053 || (MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG)))
11055 /* Allow TFmode for CCmode reloads. */
11056 if (mode == TFmode && ISA_HAS_8CC)
11059 /* Allow 64-bit vector modes for Loongson-2E/2F. */
11060 if (TARGET_LOONGSON_VECTORS
11061 && (mode == V2SImode
11062 || mode == V4HImode
11063 || mode == V8QImode
11064 || mode == DImode))
11067 if (mclass == MODE_FLOAT
11068 || mclass == MODE_COMPLEX_FLOAT
11069 || mclass == MODE_VECTOR_FLOAT)
11070 return size <= UNITS_PER_FPVALUE;
11072 /* Allow integer modes that fit into a single register. We need
11073 to put integers into FPRs when using instructions like CVT
11074 and TRUNC. There's no point allowing sizes smaller than a word,
11075 because the FPU has no appropriate load/store instructions. */
11076 if (mclass == MODE_INT)
11077 return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG;
11080 if (ACC_REG_P (regno)
11081 && (INTEGRAL_MODE_P (mode) || ALL_FIXED_POINT_MODE_P (mode)))
11083 if (MD_REG_P (regno))
11085 /* After a multiplication or division, clobbering HI makes
11086 the value of LO unpredictable, and vice versa. This means
11087 that, for all interesting cases, HI and LO are effectively
11090 We model this by requiring that any value that uses HI
11092 if (size <= UNITS_PER_WORD * 2)
11093 return regno == (size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST);
11097 /* DSP accumulators do not have the same restrictions as
11098 HI and LO, so we can treat them as normal doubleword
11100 if (size <= UNITS_PER_WORD)
11103 if (size <= UNITS_PER_WORD * 2
11104 && ((regno - DSP_ACC_REG_FIRST) & 1) == 0)
11109 if (ALL_COP_REG_P (regno))
11110 return mclass == MODE_INT && size <= UNITS_PER_WORD;
11112 if (regno == GOT_VERSION_REGNUM)
11113 return mode == SImode;
11118 /* Implement HARD_REGNO_NREGS. */
11121 mips_hard_regno_nregs (int regno, enum machine_mode mode)
11123 if (ST_REG_P (regno))
11124 /* The size of FP status registers is always 4, because they only hold
11125 CCmode values, and CCmode is always considered to be 4 bytes wide. */
11126 return (GET_MODE_SIZE (mode) + 3) / 4;
11128 if (FP_REG_P (regno))
11129 return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG;
11131 /* All other registers are word-sized. */
11132 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
11135 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
11136 in mips_hard_regno_nregs. */
11139 mips_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
11145 COPY_HARD_REG_SET (left, reg_class_contents[(int) rclass]);
11146 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS]))
11148 if (HARD_REGNO_MODE_OK (ST_REG_FIRST, mode))
11149 size = MIN (size, 4);
11150 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) ST_REGS]);
11152 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS]))
11154 if (HARD_REGNO_MODE_OK (FP_REG_FIRST, mode))
11155 size = MIN (size, UNITS_PER_FPREG);
11156 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]);
11158 if (!hard_reg_set_empty_p (left))
11159 size = MIN (size, UNITS_PER_WORD);
11160 return (GET_MODE_SIZE (mode) + size - 1) / size;
11163 /* Implement CANNOT_CHANGE_MODE_CLASS. */
11166 mips_cannot_change_mode_class (enum machine_mode from,
11167 enum machine_mode to,
11168 enum reg_class rclass)
11170 /* Allow conversions between different Loongson integer vectors,
11171 and between those vectors and DImode. */
11172 if (GET_MODE_SIZE (from) == 8 && GET_MODE_SIZE (to) == 8
11173 && INTEGRAL_MODE_P (from) && INTEGRAL_MODE_P (to))
11176 /* Otherwise, there are several problems with changing the modes of
11177 values in floating-point registers:
11179 - When a multi-word value is stored in paired floating-point
11180 registers, the first register always holds the low word. We
11181 therefore can't allow FPRs to change between single-word and
11182 multi-word modes on big-endian targets.
11184 - GCC assumes that each word of a multiword register can be
11185 accessed individually using SUBREGs. This is not true for
11186 floating-point registers if they are bigger than a word.
11188 - Loading a 32-bit value into a 64-bit floating-point register
11189 will not sign-extend the value, despite what LOAD_EXTEND_OP
11190 says. We can't allow FPRs to change from SImode to a wider
11191 mode on 64-bit targets.
11193 - If the FPU has already interpreted a value in one format, we
11194 must not ask it to treat the value as having a different
11197 We therefore disallow all mode changes involving FPRs. */
11199 return reg_classes_intersect_p (FP_REGS, rclass);
11202 /* Implement target hook small_register_classes_for_mode_p. */
11205 mips_small_register_classes_for_mode_p (enum machine_mode mode
11208 return TARGET_MIPS16;
11211 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
11214 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode)
11219 return TARGET_HARD_FLOAT;
11222 return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT;
11225 return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT;
11232 /* Implement MODES_TIEABLE_P. */
11235 mips_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
11237 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
11238 prefer to put one of them in FPRs. */
11239 return (mode1 == mode2
11240 || (!mips_mode_ok_for_mov_fmt_p (mode1)
11241 && !mips_mode_ok_for_mov_fmt_p (mode2)));
11244 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
11247 mips_preferred_reload_class (rtx x, reg_class_t rclass)
11249 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, rclass))
11252 if (reg_class_subset_p (FP_REGS, rclass)
11253 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x)))
11256 if (reg_class_subset_p (GR_REGS, rclass))
11259 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, rclass))
11265 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
11266 Return a "canonical" class to represent it in later calculations. */
11269 mips_canonicalize_move_class (reg_class_t rclass)
11271 /* All moves involving accumulator registers have the same cost. */
11272 if (reg_class_subset_p (rclass, ACC_REGS))
11275 /* Likewise promote subclasses of general registers to the most
11276 interesting containing class. */
11277 if (TARGET_MIPS16 && reg_class_subset_p (rclass, M16_REGS))
11279 else if (reg_class_subset_p (rclass, GENERAL_REGS))
11280 rclass = GENERAL_REGS;
11285 /* Return the cost of moving a value of mode MODE from a register of
11286 class FROM to a GPR. Return 0 for classes that are unions of other
11287 classes handled by this function. */
11290 mips_move_to_gpr_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
11296 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
11300 /* MFLO and MFHI. */
11308 /* LUI followed by MOVF. */
11314 /* This choice of value is historical. */
11322 /* Return the cost of moving a value of mode MODE from a GPR to a
11323 register of class TO. Return 0 for classes that are unions of
11324 other classes handled by this function. */
11327 mips_move_from_gpr_cost (enum machine_mode mode, reg_class_t to)
11332 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
11336 /* MTLO and MTHI. */
11344 /* A secondary reload through an FPR scratch. */
11345 return (mips_register_move_cost (mode, GENERAL_REGS, FP_REGS)
11346 + mips_register_move_cost (mode, FP_REGS, ST_REGS));
11351 /* This choice of value is historical. */
11359 /* Implement TARGET_REGISTER_MOVE_COST. Return 0 for classes that are the
11360 maximum of the move costs for subclasses; regclass will work out
11361 the maximum for us. */
11364 mips_register_move_cost (enum machine_mode mode,
11365 reg_class_t from, reg_class_t to)
11370 from = mips_canonicalize_move_class (from);
11371 to = mips_canonicalize_move_class (to);
11373 /* Handle moves that can be done without using general-purpose registers. */
11374 if (from == FP_REGS)
11376 if (to == FP_REGS && mips_mode_ok_for_mov_fmt_p (mode))
11380 /* The sequence generated by mips_expand_fcc_reload. */
11384 /* Handle cases in which only one class deviates from the ideal. */
11385 dregs = TARGET_MIPS16 ? M16_REGS : GENERAL_REGS;
11387 return mips_move_from_gpr_cost (mode, to);
11389 return mips_move_to_gpr_cost (mode, from);
11391 /* Handles cases that require a GPR temporary. */
11392 cost1 = mips_move_to_gpr_cost (mode, from);
11395 cost2 = mips_move_from_gpr_cost (mode, to);
11397 return cost1 + cost2;
11403 /* Implement TARGET_MEMORY_MOVE_COST. */
11406 mips_memory_move_cost (enum machine_mode mode, reg_class_t rclass, bool in)
11408 return (mips_cost->memory_latency
11409 + memory_move_secondary_cost (mode, rclass, in));
11412 /* Return the register class required for a secondary register when
11413 copying between one of the registers in RCLASS and value X, which
11414 has mode MODE. X is the source of the move if IN_P, otherwise it
11415 is the destination. Return NO_REGS if no secondary register is
11419 mips_secondary_reload_class (enum reg_class rclass,
11420 enum machine_mode mode, rtx x, bool in_p)
11424 /* If X is a constant that cannot be loaded into $25, it must be loaded
11425 into some other GPR. No other register class allows a direct move. */
11426 if (mips_dangerous_for_la25_p (x))
11427 return reg_class_subset_p (rclass, LEA_REGS) ? NO_REGS : LEA_REGS;
11429 regno = true_regnum (x);
11432 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
11433 if (!reg_class_subset_p (rclass, M16_REGS) && !M16_REG_P (regno))
11439 /* Copying from accumulator registers to anywhere other than a general
11440 register requires a temporary general register. */
11441 if (reg_class_subset_p (rclass, ACC_REGS))
11442 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
11443 if (ACC_REG_P (regno))
11444 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
11446 /* We can only copy a value to a condition code register from a
11447 floating-point register, and even then we require a scratch
11448 floating-point register. We can only copy a value out of a
11449 condition-code register into a general register. */
11450 if (reg_class_subset_p (rclass, ST_REGS))
11454 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
11456 if (ST_REG_P (regno))
11460 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
11463 if (reg_class_subset_p (rclass, FP_REGS))
11466 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8))
11467 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
11468 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
11471 if (GP_REG_P (regno) || x == CONST0_RTX (mode))
11472 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
11475 if (CONSTANT_P (x) && !targetm.cannot_force_const_mem (mode, x))
11476 /* We can force the constant to memory and use lwc1
11477 and ldc1. As above, we will use pairs of lwc1s if
11478 ldc1 is not supported. */
11481 if (FP_REG_P (regno) && mips_mode_ok_for_mov_fmt_p (mode))
11482 /* In this case we can use mov.fmt. */
11485 /* Otherwise, we need to reload through an integer register. */
11488 if (FP_REG_P (regno))
11489 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
11494 /* Implement TARGET_MODE_REP_EXTENDED. */
11497 mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
11499 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
11500 if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
11501 return SIGN_EXTEND;
11506 /* Implement TARGET_VALID_POINTER_MODE. */
11509 mips_valid_pointer_mode (enum machine_mode mode)
11511 return mode == SImode || (TARGET_64BIT && mode == DImode);
11514 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
11517 mips_vector_mode_supported_p (enum machine_mode mode)
11522 return TARGET_PAIRED_SINGLE_FLOAT;
11537 return TARGET_LOONGSON_VECTORS;
11544 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
11547 mips_scalar_mode_supported_p (enum machine_mode mode)
11549 if (ALL_FIXED_POINT_MODE_P (mode)
11550 && GET_MODE_PRECISION (mode) <= 2 * BITS_PER_WORD)
11553 return default_scalar_mode_supported_p (mode);
11556 /* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
11558 static enum machine_mode
11559 mips_preferred_simd_mode (enum machine_mode mode ATTRIBUTE_UNUSED)
11561 if (TARGET_PAIRED_SINGLE_FLOAT
11567 /* Implement TARGET_INIT_LIBFUNCS. */
11570 mips_init_libfuncs (void)
11572 if (TARGET_FIX_VR4120)
11574 /* Register the special divsi3 and modsi3 functions needed to work
11575 around VR4120 division errata. */
11576 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
11577 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
11580 if (TARGET_MIPS16 && TARGET_HARD_FLOAT_ABI)
11582 /* Register the MIPS16 -mhard-float stubs. */
11583 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
11584 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
11585 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
11586 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
11588 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
11589 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
11590 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
11591 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
11592 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
11593 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
11594 set_optab_libfunc (unord_optab, SFmode, "__mips16_unordsf2");
11596 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
11597 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
11598 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__mips16_floatunsisf");
11600 if (TARGET_DOUBLE_FLOAT)
11602 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
11603 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
11604 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
11605 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
11607 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
11608 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
11609 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
11610 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
11611 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
11612 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
11613 set_optab_libfunc (unord_optab, DFmode, "__mips16_unorddf2");
11615 set_conv_libfunc (sext_optab, DFmode, SFmode,
11616 "__mips16_extendsfdf2");
11617 set_conv_libfunc (trunc_optab, SFmode, DFmode,
11618 "__mips16_truncdfsf2");
11619 set_conv_libfunc (sfix_optab, SImode, DFmode,
11620 "__mips16_fix_truncdfsi");
11621 set_conv_libfunc (sfloat_optab, DFmode, SImode,
11622 "__mips16_floatsidf");
11623 set_conv_libfunc (ufloat_optab, DFmode, SImode,
11624 "__mips16_floatunsidf");
11628 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
11629 on an external non-MIPS16 routine to implement __sync_synchronize.
11630 Similarly for the rest of the ll/sc libfuncs. */
11633 synchronize_libfunc = init_one_libfunc ("__sync_synchronize");
11634 init_sync_libfuncs (UNITS_PER_WORD);
11638 /* Build up a multi-insn sequence that loads label TARGET into $AT. */
11641 mips_process_load_label (rtx target)
11643 rtx base, gp, intop;
11644 HOST_WIDE_INT offset;
11646 mips_multi_start ();
11650 mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target, 0);
11651 mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target, 0);
11655 mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target, 0);
11656 mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target, 0);
11660 gp = pic_offset_table_rtx;
11661 if (mips_cfun_has_cprestore_slot_p ())
11663 gp = gen_rtx_REG (Pmode, AT_REGNUM);
11664 mips_get_cprestore_base_and_offset (&base, &offset, true);
11665 if (!SMALL_OPERAND (offset))
11667 intop = GEN_INT (CONST_HIGH_PART (offset));
11668 mips_multi_add_insn ("lui\t%0,%1", gp, intop, 0);
11669 mips_multi_add_insn ("addu\t%0,%0,%1", gp, base, 0);
11672 offset = CONST_LOW_PART (offset);
11674 intop = GEN_INT (offset);
11675 if (ISA_HAS_LOAD_DELAY)
11676 mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp, intop, base, 0);
11678 mips_multi_add_insn ("lw\t%0,%1(%2)", gp, intop, base, 0);
11680 if (ISA_HAS_LOAD_DELAY)
11681 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target, gp, 0);
11683 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target, gp, 0);
11684 mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target, 0);
11689 /* Return the number of instructions needed to load a label into $AT. */
11691 static unsigned int
11692 mips_load_label_num_insns (void)
11694 if (cfun->machine->load_label_num_insns == 0)
11696 mips_process_load_label (pc_rtx);
11697 cfun->machine->load_label_num_insns = mips_multi_num_insns;
11699 return cfun->machine->load_label_num_insns;
11702 /* Emit an asm sequence to start a noat block and load the address
11703 of a label into $1. */
11706 mips_output_load_label (rtx target)
11708 mips_push_asm_switch (&mips_noat);
11709 if (TARGET_EXPLICIT_RELOCS)
11711 mips_process_load_label (target);
11712 mips_multi_write ();
11716 if (Pmode == DImode)
11717 output_asm_insn ("dla\t%@,%0", &target);
11719 output_asm_insn ("la\t%@,%0", &target);
11723 /* Return the length of INSN. LENGTH is the initial length computed by
11724 attributes in the machine-description file. */
11727 mips_adjust_insn_length (rtx insn, int length)
11729 /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length
11730 of a PIC long-branch sequence. Substitute the correct value. */
11731 if (length == MAX_PIC_BRANCH_LENGTH
11732 && INSN_CODE (insn) >= 0
11733 && get_attr_type (insn) == TYPE_BRANCH)
11735 /* Add the branch-over instruction and its delay slot, if this
11736 is a conditional branch. */
11737 length = simplejump_p (insn) ? 0 : 8;
11739 /* Load the label into $AT and jump to it. Ignore the delay
11740 slot of the jump. */
11741 length += 4 * mips_load_label_num_insns() + 4;
11744 /* A unconditional jump has an unfilled delay slot if it is not part
11745 of a sequence. A conditional jump normally has a delay slot, but
11746 does not on MIPS16. */
11747 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
11750 /* See how many nops might be needed to avoid hardware hazards. */
11751 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
11752 switch (get_attr_hazard (insn))
11766 /* In order to make it easier to share MIPS16 and non-MIPS16 patterns,
11767 the .md file length attributes are 4-based for both modes.
11768 Adjust the MIPS16 ones here. */
11775 /* Return the assembly code for INSN, which has the operands given by
11776 OPERANDS, and which branches to OPERANDS[0] if some condition is true.
11777 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0]
11778 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
11779 version of BRANCH_IF_TRUE. */
11782 mips_output_conditional_branch (rtx insn, rtx *operands,
11783 const char *branch_if_true,
11784 const char *branch_if_false)
11786 unsigned int length;
11787 rtx taken, not_taken;
11789 gcc_assert (LABEL_P (operands[0]));
11791 length = get_attr_length (insn);
11794 /* Just a simple conditional branch. */
11795 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
11796 return branch_if_true;
11799 /* Generate a reversed branch around a direct jump. This fallback does
11800 not use branch-likely instructions. */
11801 mips_branch_likely = false;
11802 not_taken = gen_label_rtx ();
11803 taken = operands[0];
11805 /* Generate the reversed branch to NOT_TAKEN. */
11806 operands[0] = not_taken;
11807 output_asm_insn (branch_if_false, operands);
11809 /* If INSN has a delay slot, we must provide delay slots for both the
11810 branch to NOT_TAKEN and the conditional jump. We must also ensure
11811 that INSN's delay slot is executed in the appropriate cases. */
11812 if (final_sequence)
11814 /* This first delay slot will always be executed, so use INSN's
11815 delay slot if is not annulled. */
11816 if (!INSN_ANNULLED_BRANCH_P (insn))
11818 final_scan_insn (XVECEXP (final_sequence, 0, 1),
11819 asm_out_file, optimize, 1, NULL);
11820 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
11823 output_asm_insn ("nop", 0);
11824 fprintf (asm_out_file, "\n");
11827 /* Output the unconditional branch to TAKEN. */
11828 if (TARGET_ABSOLUTE_JUMPS)
11829 output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken);
11832 mips_output_load_label (taken);
11833 output_asm_insn ("jr\t%@%]%/", 0);
11836 /* Now deal with its delay slot; see above. */
11837 if (final_sequence)
11839 /* This delay slot will only be executed if the branch is taken.
11840 Use INSN's delay slot if is annulled. */
11841 if (INSN_ANNULLED_BRANCH_P (insn))
11843 final_scan_insn (XVECEXP (final_sequence, 0, 1),
11844 asm_out_file, optimize, 1, NULL);
11845 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
11848 output_asm_insn ("nop", 0);
11849 fprintf (asm_out_file, "\n");
11852 /* Output NOT_TAKEN. */
11853 targetm.asm_out.internal_label (asm_out_file, "L",
11854 CODE_LABEL_NUMBER (not_taken));
11858 /* Return the assembly code for INSN, which branches to OPERANDS[0]
11859 if some ordering condition is true. The condition is given by
11860 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
11861 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
11862 its second is always zero. */
11865 mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
11867 const char *branch[2];
11869 /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true.
11870 Make BRANCH[0] branch on the inverse condition. */
11871 switch (GET_CODE (operands[1]))
11873 /* These cases are equivalent to comparisons against zero. */
11875 inverted_p = !inverted_p;
11876 /* Fall through. */
11878 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%0");
11879 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%0");
11882 /* These cases are always true or always false. */
11884 inverted_p = !inverted_p;
11885 /* Fall through. */
11887 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%0");
11888 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%0");
11892 branch[!inverted_p] = MIPS_BRANCH ("b%C1z", "%2,%0");
11893 branch[inverted_p] = MIPS_BRANCH ("b%N1z", "%2,%0");
11896 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
11899 /* Start a block of code that needs access to the LL, SC and SYNC
11903 mips_start_ll_sc_sync_block (void)
11905 if (!ISA_HAS_LL_SC)
11907 output_asm_insn (".set\tpush", 0);
11908 output_asm_insn (".set\tmips2", 0);
11912 /* End a block started by mips_start_ll_sc_sync_block. */
11915 mips_end_ll_sc_sync_block (void)
11917 if (!ISA_HAS_LL_SC)
11918 output_asm_insn (".set\tpop", 0);
11921 /* Output and/or return the asm template for a sync instruction. */
11924 mips_output_sync (void)
11926 mips_start_ll_sc_sync_block ();
11927 output_asm_insn ("sync", 0);
11928 mips_end_ll_sc_sync_block ();
11932 /* Return the asm template associated with sync_insn1 value TYPE.
11933 IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */
11935 static const char *
11936 mips_sync_insn1_template (enum attr_sync_insn1 type, bool is_64bit_p)
11940 case SYNC_INSN1_MOVE:
11941 return "move\t%0,%z2";
11942 case SYNC_INSN1_LI:
11943 return "li\t%0,%2";
11944 case SYNC_INSN1_ADDU:
11945 return is_64bit_p ? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2";
11946 case SYNC_INSN1_ADDIU:
11947 return is_64bit_p ? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2";
11948 case SYNC_INSN1_SUBU:
11949 return is_64bit_p ? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2";
11950 case SYNC_INSN1_AND:
11951 return "and\t%0,%1,%z2";
11952 case SYNC_INSN1_ANDI:
11953 return "andi\t%0,%1,%2";
11954 case SYNC_INSN1_OR:
11955 return "or\t%0,%1,%z2";
11956 case SYNC_INSN1_ORI:
11957 return "ori\t%0,%1,%2";
11958 case SYNC_INSN1_XOR:
11959 return "xor\t%0,%1,%z2";
11960 case SYNC_INSN1_XORI:
11961 return "xori\t%0,%1,%2";
11963 gcc_unreachable ();
11966 /* Return the asm template associated with sync_insn2 value TYPE. */
11968 static const char *
11969 mips_sync_insn2_template (enum attr_sync_insn2 type)
11973 case SYNC_INSN2_NOP:
11974 gcc_unreachable ();
11975 case SYNC_INSN2_AND:
11976 return "and\t%0,%1,%z2";
11977 case SYNC_INSN2_XOR:
11978 return "xor\t%0,%1,%z2";
11979 case SYNC_INSN2_NOT:
11980 return "nor\t%0,%1,%.";
11982 gcc_unreachable ();
11985 /* OPERANDS are the operands to a sync loop instruction and INDEX is
11986 the value of the one of the sync_* attributes. Return the operand
11987 referred to by the attribute, or DEFAULT_VALUE if the insn doesn't
11988 have the associated attribute. */
11991 mips_get_sync_operand (rtx *operands, int index, rtx default_value)
11994 default_value = operands[index - 1];
11995 return default_value;
11998 /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn
11999 sequence for it. */
12002 mips_process_sync_loop (rtx insn, rtx *operands)
12004 rtx at, mem, oldval, newval, inclusive_mask, exclusive_mask;
12005 rtx required_oldval, insn1_op2, tmp1, tmp2, tmp3, cmp;
12006 unsigned int tmp3_insn;
12007 enum attr_sync_insn1 insn1;
12008 enum attr_sync_insn2 insn2;
12011 enum memmodel model;
12013 /* Read an operand from the sync_WHAT attribute and store it in
12014 variable WHAT. DEFAULT is the default value if no attribute
12016 #define READ_OPERAND(WHAT, DEFAULT) \
12017 WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \
12020 /* Read the memory. */
12021 READ_OPERAND (mem, 0);
12023 is_64bit_p = (GET_MODE_BITSIZE (GET_MODE (mem)) == 64);
12025 /* Read the other attributes. */
12026 at = gen_rtx_REG (GET_MODE (mem), AT_REGNUM);
12027 READ_OPERAND (oldval, at);
12028 READ_OPERAND (cmp, 0);
12029 READ_OPERAND (newval, at);
12030 READ_OPERAND (inclusive_mask, 0);
12031 READ_OPERAND (exclusive_mask, 0);
12032 READ_OPERAND (required_oldval, 0);
12033 READ_OPERAND (insn1_op2, 0);
12034 insn1 = get_attr_sync_insn1 (insn);
12035 insn2 = get_attr_sync_insn2 (insn);
12037 /* Don't bother setting CMP result that is never used. */
12038 if (cmp && find_reg_note (insn, REG_UNUSED, cmp))
12041 memmodel_attr = get_attr_sync_memmodel (insn);
12042 switch (memmodel_attr)
12045 model = MEMMODEL_ACQ_REL;
12048 model = MEMMODEL_ACQUIRE;
12051 model = (enum memmodel) INTVAL (operands[memmodel_attr]);
12054 mips_multi_start ();
12056 /* Output the release side of the memory barrier. */
12057 if (need_atomic_barrier_p (model, true))
12059 if (required_oldval == 0 && TARGET_OCTEON)
12061 /* Octeon doesn't reorder reads, so a full barrier can be
12062 created by using SYNCW to order writes combined with the
12063 write from the following SC. When the SC successfully
12064 completes, we know that all preceding writes are also
12065 committed to the coherent memory system. It is possible
12066 for a single SYNCW to fail, but a pair of them will never
12067 fail, so we use two. */
12068 mips_multi_add_insn ("syncw", NULL);
12069 mips_multi_add_insn ("syncw", NULL);
12072 mips_multi_add_insn ("sync", NULL);
12075 /* Output the branch-back label. */
12076 mips_multi_add_label ("1:");
12078 /* OLDVAL = *MEM. */
12079 mips_multi_add_insn (is_64bit_p ? "lld\t%0,%1" : "ll\t%0,%1",
12080 oldval, mem, NULL);
12082 /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */
12083 if (required_oldval)
12085 if (inclusive_mask == 0)
12089 gcc_assert (oldval != at);
12090 mips_multi_add_insn ("and\t%0,%1,%2",
12091 at, oldval, inclusive_mask, NULL);
12094 mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1, required_oldval, NULL);
12096 /* CMP = 0 [delay slot]. */
12098 mips_multi_add_insn ("li\t%0,0", cmp, NULL);
12101 /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */
12102 if (exclusive_mask == 0)
12106 gcc_assert (oldval != at);
12107 mips_multi_add_insn ("and\t%0,%1,%z2",
12108 at, oldval, exclusive_mask, NULL);
12112 /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2).
12114 We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit
12115 at least one instruction in that case. */
12116 if (insn1 == SYNC_INSN1_MOVE
12117 && (tmp1 != const0_rtx || insn2 != SYNC_INSN2_NOP))
12121 mips_multi_add_insn (mips_sync_insn1_template (insn1, is_64bit_p),
12122 newval, oldval, insn1_op2, NULL);
12126 /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */
12127 if (insn2 == SYNC_INSN2_NOP)
12131 mips_multi_add_insn (mips_sync_insn2_template (insn2),
12132 newval, tmp2, inclusive_mask, NULL);
12135 tmp3_insn = mips_multi_last_index ();
12137 /* $AT = $TMP1 | $TMP3. */
12138 if (tmp1 == const0_rtx || tmp3 == const0_rtx)
12140 mips_multi_set_operand (tmp3_insn, 0, at);
12145 gcc_assert (tmp1 != tmp3);
12146 mips_multi_add_insn ("or\t%0,%1,%2", at, tmp1, tmp3, NULL);
12149 /* if (!commit (*MEM = $AT)) goto 1.
12151 This will sometimes be a delayed branch; see the write code below
12153 mips_multi_add_insn (is_64bit_p ? "scd\t%0,%1" : "sc\t%0,%1", at, mem, NULL);
12154 mips_multi_add_insn ("beq%?\t%0,%.,1b", at, NULL);
12156 /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */
12157 if (insn1 != SYNC_INSN1_MOVE && insn1 != SYNC_INSN1_LI && tmp3 != newval)
12159 mips_multi_copy_insn (tmp3_insn);
12160 mips_multi_set_operand (mips_multi_last_index (), 0, newval);
12162 else if (!(required_oldval && cmp))
12163 mips_multi_add_insn ("nop", NULL);
12165 /* CMP = 1 -- either standalone or in a delay slot. */
12166 if (required_oldval && cmp)
12167 mips_multi_add_insn ("li\t%0,1", cmp, NULL);
12169 /* Output the acquire side of the memory barrier. */
12170 if (TARGET_SYNC_AFTER_SC && need_atomic_barrier_p (model, false))
12171 mips_multi_add_insn ("sync", NULL);
12173 /* Output the exit label, if needed. */
12174 if (required_oldval)
12175 mips_multi_add_label ("2:");
12177 #undef READ_OPERAND
12180 /* Output and/or return the asm template for sync loop INSN, which has
12181 the operands given by OPERANDS. */
12184 mips_output_sync_loop (rtx insn, rtx *operands)
12186 mips_process_sync_loop (insn, operands);
12188 /* Use branch-likely instructions to work around the LL/SC R10000
12190 mips_branch_likely = TARGET_FIX_R10000;
12192 mips_push_asm_switch (&mips_noreorder);
12193 mips_push_asm_switch (&mips_nomacro);
12194 mips_push_asm_switch (&mips_noat);
12195 mips_start_ll_sc_sync_block ();
12197 mips_multi_write ();
12199 mips_end_ll_sc_sync_block ();
12200 mips_pop_asm_switch (&mips_noat);
12201 mips_pop_asm_switch (&mips_nomacro);
12202 mips_pop_asm_switch (&mips_noreorder);
12207 /* Return the number of individual instructions in sync loop INSN,
12208 which has the operands given by OPERANDS. */
12211 mips_sync_loop_insns (rtx insn, rtx *operands)
12213 mips_process_sync_loop (insn, operands);
12214 return mips_multi_num_insns;
12217 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
12218 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
12220 When working around R4000 and R4400 errata, we need to make sure that
12221 the division is not immediately followed by a shift[1][2]. We also
12222 need to stop the division from being put into a branch delay slot[3].
12223 The easiest way to avoid both problems is to add a nop after the
12224 division. When a divide-by-zero check is needed, this nop can be
12225 used to fill the branch delay slot.
12227 [1] If a double-word or a variable shift executes immediately
12228 after starting an integer division, the shift may give an
12229 incorrect result. See quotations of errata #16 and #28 from
12230 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
12231 in mips.md for details.
12233 [2] A similar bug to [1] exists for all revisions of the
12234 R4000 and the R4400 when run in an MC configuration.
12235 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
12237 "19. In this following sequence:
12239 ddiv (or ddivu or div or divu)
12240 dsll32 (or dsrl32, dsra32)
12242 if an MPT stall occurs, while the divide is slipping the cpu
12243 pipeline, then the following double shift would end up with an
12246 Workaround: The compiler needs to avoid generating any
12247 sequence with divide followed by extended double shift."
12249 This erratum is also present in "MIPS R4400MC Errata, Processor
12250 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
12251 & 3.0" as errata #10 and #4, respectively.
12253 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
12254 (also valid for MIPS R4000MC processors):
12256 "52. R4000SC: This bug does not apply for the R4000PC.
12258 There are two flavors of this bug:
12260 1) If the instruction just after divide takes an RF exception
12261 (tlb-refill, tlb-invalid) and gets an instruction cache
12262 miss (both primary and secondary) and the line which is
12263 currently in secondary cache at this index had the first
12264 data word, where the bits 5..2 are set, then R4000 would
12265 get a wrong result for the div.
12270 ------------------- # end-of page. -tlb-refill
12275 ------------------- # end-of page. -tlb-invalid
12278 2) If the divide is in the taken branch delay slot, where the
12279 target takes RF exception and gets an I-cache miss for the
12280 exception vector or where I-cache miss occurs for the
12281 target address, under the above mentioned scenarios, the
12282 div would get wrong results.
12285 j r2 # to next page mapped or unmapped
12286 div r8,r9 # this bug would be there as long
12287 # as there is an ICache miss and
12288 nop # the "data pattern" is present
12291 beq r0, r0, NextPage # to Next page
12295 This bug is present for div, divu, ddiv, and ddivu
12298 Workaround: For item 1), OS could make sure that the next page
12299 after the divide instruction is also mapped. For item 2), the
12300 compiler could make sure that the divide instruction is not in
12301 the branch delay slot."
12303 These processors have PRId values of 0x00004220 and 0x00004300 for
12304 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
12307 mips_output_division (const char *division, rtx *operands)
12312 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
12314 output_asm_insn (s, operands);
12317 if (TARGET_CHECK_ZERO_DIV)
12321 output_asm_insn (s, operands);
12322 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
12324 else if (GENERATE_DIVIDE_TRAPS)
12326 /* Avoid long replay penalty on load miss by putting the trap before
12329 output_asm_insn ("teq\t%2,%.,7", operands);
12332 output_asm_insn (s, operands);
12333 s = "teq\t%2,%.,7";
12338 output_asm_insn ("%(bne\t%2,%.,1f", operands);
12339 output_asm_insn (s, operands);
12340 s = "break\t7%)\n1:";
12346 /* Return true if IN_INSN is a multiply-add or multiply-subtract
12347 instruction and if OUT_INSN assigns to the accumulator operand. */
12350 mips_linked_madd_p (rtx out_insn, rtx in_insn)
12354 x = single_set (in_insn);
12360 if (GET_CODE (x) == PLUS
12361 && GET_CODE (XEXP (x, 0)) == MULT
12362 && reg_set_p (XEXP (x, 1), out_insn))
12365 if (GET_CODE (x) == MINUS
12366 && GET_CODE (XEXP (x, 1)) == MULT
12367 && reg_set_p (XEXP (x, 0), out_insn))
12373 /* True if the dependency between OUT_INSN and IN_INSN is on the store
12374 data rather than the address. We need this because the cprestore
12375 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
12376 which causes the default routine to abort. We just return false
12380 mips_store_data_bypass_p (rtx out_insn, rtx in_insn)
12382 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
12385 return !store_data_bypass_p (out_insn, in_insn);
12389 /* Variables and flags used in scheduler hooks when tuning for
12393 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
12396 /* If true, then next ALU1/2 instruction will go to ALU1. */
12399 /* If true, then next FALU1/2 unstruction will go to FALU1. */
12402 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
12403 int alu1_core_unit_code;
12404 int alu2_core_unit_code;
12405 int falu1_core_unit_code;
12406 int falu2_core_unit_code;
12408 /* True if current cycle has a multi instruction.
12409 This flag is used in mips_ls2_dfa_post_advance_cycle. */
12410 bool cycle_has_multi_p;
12412 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
12413 These are used in mips_ls2_dfa_post_advance_cycle to initialize
12415 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
12416 instruction to go ALU1. */
12417 rtx alu1_turn_enabled_insn;
12418 rtx alu2_turn_enabled_insn;
12419 rtx falu1_turn_enabled_insn;
12420 rtx falu2_turn_enabled_insn;
12423 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
12424 dependencies have no cost, except on the 20Kc where output-dependence
12425 is treated like input-dependence. */
12428 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
12429 rtx dep ATTRIBUTE_UNUSED, int cost)
12431 if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT
12434 if (REG_NOTE_KIND (link) != 0)
12439 /* Return the number of instructions that can be issued per cycle. */
12442 mips_issue_rate (void)
12446 case PROCESSOR_74KC:
12447 case PROCESSOR_74KF2_1:
12448 case PROCESSOR_74KF1_1:
12449 case PROCESSOR_74KF3_2:
12450 /* The 74k is not strictly quad-issue cpu, but can be seen as one
12451 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
12452 but in reality only a maximum of 3 insns can be issued as
12453 floating-point loads and stores also require a slot in the
12455 case PROCESSOR_R10000:
12456 /* All R10K Processors are quad-issue (being the first MIPS
12457 processors to support this feature). */
12460 case PROCESSOR_20KC:
12461 case PROCESSOR_R4130:
12462 case PROCESSOR_R5400:
12463 case PROCESSOR_R5500:
12464 case PROCESSOR_R7000:
12465 case PROCESSOR_R9000:
12466 case PROCESSOR_OCTEON:
12467 case PROCESSOR_OCTEON2:
12470 case PROCESSOR_SB1:
12471 case PROCESSOR_SB1A:
12472 /* This is actually 4, but we get better performance if we claim 3.
12473 This is partly because of unwanted speculative code motion with the
12474 larger number, and partly because in most common cases we can't
12475 reach the theoretical max of 4. */
12478 case PROCESSOR_LOONGSON_2E:
12479 case PROCESSOR_LOONGSON_2F:
12480 case PROCESSOR_LOONGSON_3A:
12488 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
12491 mips_ls2_init_dfa_post_cycle_insn (void)
12494 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
12495 mips_ls2.alu1_turn_enabled_insn = get_insns ();
12499 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
12500 mips_ls2.alu2_turn_enabled_insn = get_insns ();
12504 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
12505 mips_ls2.falu1_turn_enabled_insn = get_insns ();
12509 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
12510 mips_ls2.falu2_turn_enabled_insn = get_insns ();
12513 mips_ls2.alu1_core_unit_code = get_cpu_unit_code ("ls2_alu1_core");
12514 mips_ls2.alu2_core_unit_code = get_cpu_unit_code ("ls2_alu2_core");
12515 mips_ls2.falu1_core_unit_code = get_cpu_unit_code ("ls2_falu1_core");
12516 mips_ls2.falu2_core_unit_code = get_cpu_unit_code ("ls2_falu2_core");
12519 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
12520 Init data used in mips_dfa_post_advance_cycle. */
12523 mips_init_dfa_post_cycle_insn (void)
12525 if (TUNE_LOONGSON_2EF)
12526 mips_ls2_init_dfa_post_cycle_insn ();
12529 /* Initialize STATE when scheduling for Loongson 2E/2F.
12530 Support round-robin dispatch scheme by enabling only one of
12531 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
12535 mips_ls2_dfa_post_advance_cycle (state_t state)
12537 if (cpu_unit_reservation_p (state, mips_ls2.alu1_core_unit_code))
12539 /* Though there are no non-pipelined ALU1 insns,
12540 we can get an instruction of type 'multi' before reload. */
12541 gcc_assert (mips_ls2.cycle_has_multi_p);
12542 mips_ls2.alu1_turn_p = false;
12545 mips_ls2.cycle_has_multi_p = false;
12547 if (cpu_unit_reservation_p (state, mips_ls2.alu2_core_unit_code))
12548 /* We have a non-pipelined alu instruction in the core,
12549 adjust round-robin counter. */
12550 mips_ls2.alu1_turn_p = true;
12552 if (mips_ls2.alu1_turn_p)
12554 if (state_transition (state, mips_ls2.alu1_turn_enabled_insn) >= 0)
12555 gcc_unreachable ();
12559 if (state_transition (state, mips_ls2.alu2_turn_enabled_insn) >= 0)
12560 gcc_unreachable ();
12563 if (cpu_unit_reservation_p (state, mips_ls2.falu1_core_unit_code))
12565 /* There are no non-pipelined FALU1 insns. */
12566 gcc_unreachable ();
12567 mips_ls2.falu1_turn_p = false;
12570 if (cpu_unit_reservation_p (state, mips_ls2.falu2_core_unit_code))
12571 /* We have a non-pipelined falu instruction in the core,
12572 adjust round-robin counter. */
12573 mips_ls2.falu1_turn_p = true;
12575 if (mips_ls2.falu1_turn_p)
12577 if (state_transition (state, mips_ls2.falu1_turn_enabled_insn) >= 0)
12578 gcc_unreachable ();
12582 if (state_transition (state, mips_ls2.falu2_turn_enabled_insn) >= 0)
12583 gcc_unreachable ();
12587 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
12588 This hook is being called at the start of each cycle. */
12591 mips_dfa_post_advance_cycle (void)
12593 if (TUNE_LOONGSON_2EF)
12594 mips_ls2_dfa_post_advance_cycle (curr_state);
12597 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
12598 be as wide as the scheduling freedom in the DFA. */
12601 mips_multipass_dfa_lookahead (void)
12603 /* Can schedule up to 4 of the 6 function units in any one cycle. */
12607 if (TUNE_LOONGSON_2EF || TUNE_LOONGSON_3A)
12616 /* Remove the instruction at index LOWER from ready queue READY and
12617 reinsert it in front of the instruction at index HIGHER. LOWER must
12621 mips_promote_ready (rtx *ready, int lower, int higher)
12626 new_head = ready[lower];
12627 for (i = lower; i < higher; i++)
12628 ready[i] = ready[i + 1];
12629 ready[i] = new_head;
12632 /* If the priority of the instruction at POS2 in the ready queue READY
12633 is within LIMIT units of that of the instruction at POS1, swap the
12634 instructions if POS2 is not already less than POS1. */
12637 mips_maybe_swap_ready (rtx *ready, int pos1, int pos2, int limit)
12640 && INSN_PRIORITY (ready[pos1]) + limit >= INSN_PRIORITY (ready[pos2]))
12644 temp = ready[pos1];
12645 ready[pos1] = ready[pos2];
12646 ready[pos2] = temp;
12650 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
12651 that may clobber hi or lo. */
12652 static rtx mips_macc_chains_last_hilo;
12654 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
12655 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
12658 mips_macc_chains_record (rtx insn)
12660 if (get_attr_may_clobber_hilo (insn))
12661 mips_macc_chains_last_hilo = insn;
12664 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
12665 has NREADY elements, looking for a multiply-add or multiply-subtract
12666 instruction that is cumulative with mips_macc_chains_last_hilo.
12667 If there is one, promote it ahead of anything else that might
12668 clobber hi or lo. */
12671 mips_macc_chains_reorder (rtx *ready, int nready)
12675 if (mips_macc_chains_last_hilo != 0)
12676 for (i = nready - 1; i >= 0; i--)
12677 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
12679 for (j = nready - 1; j > i; j--)
12680 if (recog_memoized (ready[j]) >= 0
12681 && get_attr_may_clobber_hilo (ready[j]))
12683 mips_promote_ready (ready, i, j);
12690 /* The last instruction to be scheduled. */
12691 static rtx vr4130_last_insn;
12693 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
12694 points to an rtx that is initially an instruction. Nullify the rtx
12695 if the instruction uses the value of register X. */
12698 vr4130_true_reg_dependence_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
12703 insn_ptr = (rtx *) data;
12706 && reg_referenced_p (x, PATTERN (*insn_ptr)))
12710 /* Return true if there is true register dependence between vr4130_last_insn
12714 vr4130_true_reg_dependence_p (rtx insn)
12716 note_stores (PATTERN (vr4130_last_insn),
12717 vr4130_true_reg_dependence_p_1, &insn);
12721 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
12722 the ready queue and that INSN2 is the instruction after it, return
12723 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
12724 in which INSN1 and INSN2 can probably issue in parallel, but for
12725 which (INSN2, INSN1) should be less sensitive to instruction
12726 alignment than (INSN1, INSN2). See 4130.md for more details. */
12729 vr4130_swap_insns_p (rtx insn1, rtx insn2)
12731 sd_iterator_def sd_it;
12734 /* Check for the following case:
12736 1) there is some other instruction X with an anti dependence on INSN1;
12737 2) X has a higher priority than INSN2; and
12738 3) X is an arithmetic instruction (and thus has no unit restrictions).
12740 If INSN1 is the last instruction blocking X, it would better to
12741 choose (INSN1, X) over (INSN2, INSN1). */
12742 FOR_EACH_DEP (insn1, SD_LIST_FORW, sd_it, dep)
12743 if (DEP_TYPE (dep) == REG_DEP_ANTI
12744 && INSN_PRIORITY (DEP_CON (dep)) > INSN_PRIORITY (insn2)
12745 && recog_memoized (DEP_CON (dep)) >= 0
12746 && get_attr_vr4130_class (DEP_CON (dep)) == VR4130_CLASS_ALU)
12749 if (vr4130_last_insn != 0
12750 && recog_memoized (insn1) >= 0
12751 && recog_memoized (insn2) >= 0)
12753 /* See whether INSN1 and INSN2 use different execution units,
12754 or if they are both ALU-type instructions. If so, they can
12755 probably execute in parallel. */
12756 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
12757 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
12758 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
12760 /* If only one of the instructions has a dependence on
12761 vr4130_last_insn, prefer to schedule the other one first. */
12762 bool dep1_p = vr4130_true_reg_dependence_p (insn1);
12763 bool dep2_p = vr4130_true_reg_dependence_p (insn2);
12764 if (dep1_p != dep2_p)
12767 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
12768 is not an ALU-type instruction and if INSN1 uses the same
12769 execution unit. (Note that if this condition holds, we already
12770 know that INSN2 uses a different execution unit.) */
12771 if (class1 != VR4130_CLASS_ALU
12772 && recog_memoized (vr4130_last_insn) >= 0
12773 && class1 == get_attr_vr4130_class (vr4130_last_insn))
12780 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
12781 queue with at least two instructions. Swap the first two if
12782 vr4130_swap_insns_p says that it could be worthwhile. */
12785 vr4130_reorder (rtx *ready, int nready)
12787 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
12788 mips_promote_ready (ready, nready - 2, nready - 1);
12791 /* Record whether last 74k AGEN instruction was a load or store. */
12792 static enum attr_type mips_last_74k_agen_insn = TYPE_UNKNOWN;
12794 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
12795 resets to TYPE_UNKNOWN state. */
12798 mips_74k_agen_init (rtx insn)
12800 if (!insn || CALL_P (insn) || JUMP_P (insn))
12801 mips_last_74k_agen_insn = TYPE_UNKNOWN;
12804 enum attr_type type = get_attr_type (insn);
12805 if (type == TYPE_LOAD || type == TYPE_STORE)
12806 mips_last_74k_agen_insn = type;
12810 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
12811 loads to be grouped together, and multiple stores to be grouped
12812 together. Swap things around in the ready queue to make this happen. */
12815 mips_74k_agen_reorder (rtx *ready, int nready)
12818 int store_pos, load_pos;
12823 for (i = nready - 1; i >= 0; i--)
12825 rtx insn = ready[i];
12826 if (USEFUL_INSN_P (insn))
12827 switch (get_attr_type (insn))
12830 if (store_pos == -1)
12835 if (load_pos == -1)
12844 if (load_pos == -1 || store_pos == -1)
12847 switch (mips_last_74k_agen_insn)
12850 /* Prefer to schedule loads since they have a higher latency. */
12852 /* Swap loads to the front of the queue. */
12853 mips_maybe_swap_ready (ready, load_pos, store_pos, 4);
12856 /* Swap stores to the front of the queue. */
12857 mips_maybe_swap_ready (ready, store_pos, load_pos, 4);
12864 /* Implement TARGET_SCHED_INIT. */
12867 mips_sched_init (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12868 int max_ready ATTRIBUTE_UNUSED)
12870 mips_macc_chains_last_hilo = 0;
12871 vr4130_last_insn = 0;
12872 mips_74k_agen_init (NULL_RTX);
12874 /* When scheduling for Loongson2, branch instructions go to ALU1,
12875 therefore basic block is most likely to start with round-robin counter
12876 pointed to ALU2. */
12877 mips_ls2.alu1_turn_p = false;
12878 mips_ls2.falu1_turn_p = true;
12881 /* Subroutine used by TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
12884 mips_sched_reorder_1 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12885 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
12887 if (!reload_completed
12888 && TUNE_MACC_CHAINS
12890 mips_macc_chains_reorder (ready, *nreadyp);
12892 if (reload_completed
12894 && !TARGET_VR4130_ALIGN
12896 vr4130_reorder (ready, *nreadyp);
12899 mips_74k_agen_reorder (ready, *nreadyp);
12902 /* Implement TARGET_SCHED_REORDER. */
12905 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12906 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
12908 mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle);
12909 return mips_issue_rate ();
12912 /* Implement TARGET_SCHED_REORDER2. */
12915 mips_sched_reorder2 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12916 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
12918 mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle);
12919 return cached_can_issue_more;
12922 /* Update round-robin counters for ALU1/2 and FALU1/2. */
12925 mips_ls2_variable_issue (rtx insn)
12927 if (mips_ls2.alu1_turn_p)
12929 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu1_core_unit_code))
12930 mips_ls2.alu1_turn_p = false;
12934 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu2_core_unit_code))
12935 mips_ls2.alu1_turn_p = true;
12938 if (mips_ls2.falu1_turn_p)
12940 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu1_core_unit_code))
12941 mips_ls2.falu1_turn_p = false;
12945 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu2_core_unit_code))
12946 mips_ls2.falu1_turn_p = true;
12949 if (recog_memoized (insn) >= 0)
12950 mips_ls2.cycle_has_multi_p |= (get_attr_type (insn) == TYPE_MULTI);
12953 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
12956 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12957 rtx insn, int more)
12959 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
12960 if (USEFUL_INSN_P (insn))
12962 if (get_attr_type (insn) != TYPE_GHOST)
12964 if (!reload_completed && TUNE_MACC_CHAINS)
12965 mips_macc_chains_record (insn);
12966 vr4130_last_insn = insn;
12968 mips_74k_agen_init (insn);
12969 else if (TUNE_LOONGSON_2EF)
12970 mips_ls2_variable_issue (insn);
12973 /* Instructions of type 'multi' should all be split before
12974 the second scheduling pass. */
12975 gcc_assert (!reload_completed
12976 || recog_memoized (insn) < 0
12977 || get_attr_type (insn) != TYPE_MULTI);
12979 cached_can_issue_more = more;
12983 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
12984 return the first operand of the associated PREF or PREFX insn. */
12987 mips_prefetch_cookie (rtx write, rtx locality)
12989 /* store_streamed / load_streamed. */
12990 if (INTVAL (locality) <= 0)
12991 return GEN_INT (INTVAL (write) + 4);
12993 /* store / load. */
12994 if (INTVAL (locality) <= 2)
12997 /* store_retained / load_retained. */
12998 return GEN_INT (INTVAL (write) + 6);
13001 /* Flags that indicate when a built-in function is available.
13003 BUILTIN_AVAIL_NON_MIPS16
13004 The function is available on the current target, but only
13005 in non-MIPS16 mode. */
13006 #define BUILTIN_AVAIL_NON_MIPS16 1
13008 /* Declare an availability predicate for built-in functions that
13009 require non-MIPS16 mode and also require COND to be true.
13010 NAME is the main part of the predicate's name. */
13011 #define AVAIL_NON_MIPS16(NAME, COND) \
13012 static unsigned int \
13013 mips_builtin_avail_##NAME (void) \
13015 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
13018 /* This structure describes a single built-in function. */
13019 struct mips_builtin_description {
13020 /* The code of the main .md file instruction. See mips_builtin_type
13021 for more information. */
13022 enum insn_code icode;
13024 /* The floating-point comparison code to use with ICODE, if any. */
13025 enum mips_fp_condition cond;
13027 /* The name of the built-in function. */
13030 /* Specifies how the function should be expanded. */
13031 enum mips_builtin_type builtin_type;
13033 /* The function's prototype. */
13034 enum mips_function_type function_type;
13036 /* Whether the function is available. */
13037 unsigned int (*avail) (void);
13040 AVAIL_NON_MIPS16 (paired_single, TARGET_PAIRED_SINGLE_FLOAT)
13041 AVAIL_NON_MIPS16 (sb1_paired_single, TARGET_SB1 && TARGET_PAIRED_SINGLE_FLOAT)
13042 AVAIL_NON_MIPS16 (mips3d, TARGET_MIPS3D)
13043 AVAIL_NON_MIPS16 (dsp, TARGET_DSP)
13044 AVAIL_NON_MIPS16 (dspr2, TARGET_DSPR2)
13045 AVAIL_NON_MIPS16 (dsp_32, !TARGET_64BIT && TARGET_DSP)
13046 AVAIL_NON_MIPS16 (dsp_64, TARGET_64BIT && TARGET_DSP)
13047 AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2)
13048 AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS)
13049 AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
13051 /* Construct a mips_builtin_description from the given arguments.
13053 INSN is the name of the associated instruction pattern, without the
13054 leading CODE_FOR_mips_.
13056 CODE is the floating-point condition code associated with the
13057 function. It can be 'f' if the field is not applicable.
13059 NAME is the name of the function itself, without the leading
13062 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
13064 AVAIL is the name of the availability predicate, without the leading
13065 mips_builtin_avail_. */
13066 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
13067 FUNCTION_TYPE, AVAIL) \
13068 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
13069 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
13070 mips_builtin_avail_ ## AVAIL }
13072 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
13073 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
13074 are as for MIPS_BUILTIN. */
13075 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
13076 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
13078 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
13079 are subject to mips_builtin_avail_<AVAIL>. */
13080 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
13081 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
13082 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
13083 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
13084 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
13086 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
13087 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
13088 while the any and all forms are subject to mips_builtin_avail_mips3d. */
13089 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
13090 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
13091 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
13093 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
13094 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
13096 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
13097 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
13099 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
13100 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
13103 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
13104 are subject to mips_builtin_avail_mips3d. */
13105 #define CMP_4S_BUILTINS(INSN, COND) \
13106 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
13107 MIPS_BUILTIN_CMP_ANY, \
13108 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
13109 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
13110 MIPS_BUILTIN_CMP_ALL, \
13111 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
13113 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
13114 instruction requires mips_builtin_avail_<AVAIL>. */
13115 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
13116 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
13117 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
13119 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
13120 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
13123 /* Define all the built-in functions related to C.cond.fmt condition COND. */
13124 #define CMP_BUILTINS(COND) \
13125 MOVTF_BUILTINS (c, COND, paired_single), \
13126 MOVTF_BUILTINS (cabs, COND, mips3d), \
13127 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
13128 CMP_PS_BUILTINS (c, COND, paired_single), \
13129 CMP_PS_BUILTINS (cabs, COND, mips3d), \
13130 CMP_4S_BUILTINS (c, COND), \
13131 CMP_4S_BUILTINS (cabs, COND)
13133 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
13134 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
13135 and AVAIL are as for MIPS_BUILTIN. */
13136 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
13137 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
13138 FUNCTION_TYPE, AVAIL)
13140 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
13141 branch instruction. AVAIL is as for MIPS_BUILTIN. */
13142 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
13143 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
13144 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
13146 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
13147 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
13148 builtin_description field. */
13149 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
13150 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
13151 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
13152 FUNCTION_TYPE, mips_builtin_avail_loongson }
13154 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
13155 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
13156 builtin_description field. */
13157 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
13158 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
13160 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
13161 We use functions of this form when the same insn can be usefully applied
13162 to more than one datatype. */
13163 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
13164 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
13166 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
13167 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
13168 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
13169 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
13170 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
13171 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
13172 #define CODE_FOR_mips_mult CODE_FOR_mulsidi3_32bit
13173 #define CODE_FOR_mips_multu CODE_FOR_umulsidi3_32bit
13175 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
13176 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
13177 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
13178 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
13179 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
13180 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
13181 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
13182 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
13183 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
13184 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
13185 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
13186 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
13187 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
13188 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
13189 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
13190 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
13191 #define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3
13192 #define CODE_FOR_loongson_psllh CODE_FOR_ashlv4hi3
13193 #define CODE_FOR_loongson_psllw CODE_FOR_ashlv2si3
13194 #define CODE_FOR_loongson_psrlh CODE_FOR_lshrv4hi3
13195 #define CODE_FOR_loongson_psrlw CODE_FOR_lshrv2si3
13196 #define CODE_FOR_loongson_psrah CODE_FOR_ashrv4hi3
13197 #define CODE_FOR_loongson_psraw CODE_FOR_ashrv2si3
13198 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
13199 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
13200 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
13201 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
13202 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
13203 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
13204 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
13206 static const struct mips_builtin_description mips_builtins[] = {
13207 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13208 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13209 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13210 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13211 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, paired_single),
13212 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, paired_single),
13213 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, paired_single),
13214 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, paired_single),
13216 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT, paired_single),
13217 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13218 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13219 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
13220 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, mips3d),
13222 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, mips3d),
13223 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, mips3d),
13224 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
13225 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
13226 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
13227 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13229 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, mips3d),
13230 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, mips3d),
13231 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
13232 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
13233 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
13234 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13236 MIPS_FP_CONDITIONS (CMP_BUILTINS),
13238 /* Built-in functions for the SB-1 processor. */
13239 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, sb1_paired_single),
13241 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
13242 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13243 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13244 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
13245 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13246 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13247 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13248 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13249 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
13250 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13251 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13252 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, dsp),
13253 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, dsp),
13254 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, dsp),
13255 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, dsp),
13256 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, dsp),
13257 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, dsp),
13258 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
13259 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
13260 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
13261 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
13262 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, dsp),
13263 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, dsp),
13264 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
13265 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
13266 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
13267 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
13268 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
13269 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
13270 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
13271 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
13272 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
13273 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
13274 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
13275 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
13276 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
13277 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
13278 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
13279 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, dsp),
13280 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
13281 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
13282 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13283 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
13284 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
13285 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, dsp),
13286 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, dsp),
13287 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, dsp),
13288 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, dsp),
13289 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
13290 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
13291 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
13292 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
13293 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
13294 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
13295 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
13296 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
13297 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
13298 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13299 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13300 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13301 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, dsp),
13302 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, dsp),
13303 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_POINTER_SI, dsp),
13304 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_POINTER_SI, dsp),
13305 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_POINTER_SI, dsp),
13306 BPOSGE_BUILTIN (32, dsp),
13308 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
13309 DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, dspr2),
13310 DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13311 DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13312 DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
13313 DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
13314 DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
13315 DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
13316 DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
13317 DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
13318 DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
13319 DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13320 DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13321 DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13322 DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13323 DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13324 DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dspr2),
13325 DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
13326 DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
13327 DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
13328 DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
13329 DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
13330 DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, dspr2),
13331 DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13332 DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13333 DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
13334 DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
13335 DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13336 DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13337 DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13338 DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13339 DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13340 DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13341 DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13342 DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13344 /* Built-in functions for the DSP ASE (32-bit only). */
13345 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
13346 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
13347 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
13348 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
13349 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13350 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13351 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13352 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
13353 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
13354 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13355 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13356 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13357 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13358 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
13359 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
13360 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
13361 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, dsp_32),
13362 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, dsp_32),
13363 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, dsp_32),
13364 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, dsp_32),
13365 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, dsp_32),
13366 DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
13367 DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32),
13368 DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
13369 DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32),
13370 DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, dsp_32),
13371 DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, dsp_32),
13373 /* Built-in functions for the DSP ASE (64-bit only). */
13374 DIRECT_BUILTIN (ldx, MIPS_DI_FTYPE_POINTER_SI, dsp_64),
13376 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
13377 DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13378 DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13379 DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13380 DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13381 DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13382 DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13383 DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13384 DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13385 DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13387 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
13388 LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI),
13389 LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI),
13390 LOONGSON_BUILTIN (packushb, MIPS_UV8QI_FTYPE_UV4HI_UV4HI),
13391 LOONGSON_BUILTIN_SUFFIX (paddw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13392 LOONGSON_BUILTIN_SUFFIX (paddh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13393 LOONGSON_BUILTIN_SUFFIX (paddb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13394 LOONGSON_BUILTIN_SUFFIX (paddw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13395 LOONGSON_BUILTIN_SUFFIX (paddh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13396 LOONGSON_BUILTIN_SUFFIX (paddb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13397 LOONGSON_BUILTIN_SUFFIX (paddd, u, MIPS_UDI_FTYPE_UDI_UDI),
13398 LOONGSON_BUILTIN_SUFFIX (paddd, s, MIPS_DI_FTYPE_DI_DI),
13399 LOONGSON_BUILTIN (paddsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13400 LOONGSON_BUILTIN (paddsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
13401 LOONGSON_BUILTIN (paddush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13402 LOONGSON_BUILTIN (paddusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13403 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_ud, MIPS_UDI_FTYPE_UDI_UDI),
13404 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_uw, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13405 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_uh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13406 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_ub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13407 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_sd, MIPS_DI_FTYPE_DI_DI),
13408 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_sw, MIPS_V2SI_FTYPE_V2SI_V2SI),
13409 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_sh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13410 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_sb, MIPS_V8QI_FTYPE_V8QI_V8QI),
13411 LOONGSON_BUILTIN (pavgh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13412 LOONGSON_BUILTIN (pavgb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13413 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13414 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13415 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13416 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13417 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13418 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13419 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13420 LOONGSON_BUILTIN_SUFFIX (pcmpgth, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13421 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13422 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13423 LOONGSON_BUILTIN_SUFFIX (pcmpgth, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13424 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13425 LOONGSON_BUILTIN_SUFFIX (pextrh, u, MIPS_UV4HI_FTYPE_UV4HI_USI),
13426 LOONGSON_BUILTIN_SUFFIX (pextrh, s, MIPS_V4HI_FTYPE_V4HI_USI),
13427 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13428 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13429 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13430 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13431 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13432 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13433 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13434 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13435 LOONGSON_BUILTIN (pmaddhw, MIPS_V2SI_FTYPE_V4HI_V4HI),
13436 LOONGSON_BUILTIN (pmaxsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13437 LOONGSON_BUILTIN (pmaxub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13438 LOONGSON_BUILTIN (pminsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13439 LOONGSON_BUILTIN (pminub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13440 LOONGSON_BUILTIN_SUFFIX (pmovmskb, u, MIPS_UV8QI_FTYPE_UV8QI),
13441 LOONGSON_BUILTIN_SUFFIX (pmovmskb, s, MIPS_V8QI_FTYPE_V8QI),
13442 LOONGSON_BUILTIN (pmulhuh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13443 LOONGSON_BUILTIN (pmulhh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13444 LOONGSON_BUILTIN (pmullh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13445 LOONGSON_BUILTIN (pmuluw, MIPS_UDI_FTYPE_UV2SI_UV2SI),
13446 LOONGSON_BUILTIN (pasubub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13447 LOONGSON_BUILTIN (biadd, MIPS_UV4HI_FTYPE_UV8QI),
13448 LOONGSON_BUILTIN (psadbh, MIPS_UV4HI_FTYPE_UV8QI_UV8QI),
13449 LOONGSON_BUILTIN_SUFFIX (pshufh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
13450 LOONGSON_BUILTIN_SUFFIX (pshufh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
13451 LOONGSON_BUILTIN_SUFFIX (psllh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
13452 LOONGSON_BUILTIN_SUFFIX (psllh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
13453 LOONGSON_BUILTIN_SUFFIX (psllw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
13454 LOONGSON_BUILTIN_SUFFIX (psllw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
13455 LOONGSON_BUILTIN_SUFFIX (psrah, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
13456 LOONGSON_BUILTIN_SUFFIX (psrah, s, MIPS_V4HI_FTYPE_V4HI_UQI),
13457 LOONGSON_BUILTIN_SUFFIX (psraw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
13458 LOONGSON_BUILTIN_SUFFIX (psraw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
13459 LOONGSON_BUILTIN_SUFFIX (psrlh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
13460 LOONGSON_BUILTIN_SUFFIX (psrlh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
13461 LOONGSON_BUILTIN_SUFFIX (psrlw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
13462 LOONGSON_BUILTIN_SUFFIX (psrlw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
13463 LOONGSON_BUILTIN_SUFFIX (psubw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13464 LOONGSON_BUILTIN_SUFFIX (psubh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13465 LOONGSON_BUILTIN_SUFFIX (psubb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13466 LOONGSON_BUILTIN_SUFFIX (psubw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13467 LOONGSON_BUILTIN_SUFFIX (psubh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13468 LOONGSON_BUILTIN_SUFFIX (psubb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13469 LOONGSON_BUILTIN_SUFFIX (psubd, u, MIPS_UDI_FTYPE_UDI_UDI),
13470 LOONGSON_BUILTIN_SUFFIX (psubd, s, MIPS_DI_FTYPE_DI_DI),
13471 LOONGSON_BUILTIN (psubsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13472 LOONGSON_BUILTIN (psubsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
13473 LOONGSON_BUILTIN (psubush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13474 LOONGSON_BUILTIN (psubusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13475 LOONGSON_BUILTIN_SUFFIX (punpckhbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13476 LOONGSON_BUILTIN_SUFFIX (punpckhhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13477 LOONGSON_BUILTIN_SUFFIX (punpckhwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13478 LOONGSON_BUILTIN_SUFFIX (punpckhbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13479 LOONGSON_BUILTIN_SUFFIX (punpckhhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13480 LOONGSON_BUILTIN_SUFFIX (punpckhwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13481 LOONGSON_BUILTIN_SUFFIX (punpcklbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13482 LOONGSON_BUILTIN_SUFFIX (punpcklhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13483 LOONGSON_BUILTIN_SUFFIX (punpcklwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13484 LOONGSON_BUILTIN_SUFFIX (punpcklbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13485 LOONGSON_BUILTIN_SUFFIX (punpcklhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13486 LOONGSON_BUILTIN_SUFFIX (punpcklwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13488 /* Sundry other built-in functions. */
13489 DIRECT_NO_TARGET_BUILTIN (cache, MIPS_VOID_FTYPE_SI_CVPOINTER, cache)
13492 /* Index I is the function declaration for mips_builtins[I], or null if the
13493 function isn't defined on this target. */
13494 static GTY(()) tree mips_builtin_decls[ARRAY_SIZE (mips_builtins)];
13496 /* MODE is a vector mode whose elements have type TYPE. Return the type
13497 of the vector itself. */
13500 mips_builtin_vector_type (tree type, enum machine_mode mode)
13502 static tree types[2 * (int) MAX_MACHINE_MODE];
13505 mode_index = (int) mode;
13507 if (TREE_CODE (type) == INTEGER_TYPE && TYPE_UNSIGNED (type))
13508 mode_index += MAX_MACHINE_MODE;
13510 if (types[mode_index] == NULL_TREE)
13511 types[mode_index] = build_vector_type_for_mode (type, mode);
13512 return types[mode_index];
13515 /* Return a type for 'const volatile void *'. */
13518 mips_build_cvpointer_type (void)
13522 if (cache == NULL_TREE)
13523 cache = build_pointer_type (build_qualified_type
13525 TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE));
13529 /* Source-level argument types. */
13530 #define MIPS_ATYPE_VOID void_type_node
13531 #define MIPS_ATYPE_INT integer_type_node
13532 #define MIPS_ATYPE_POINTER ptr_type_node
13533 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
13535 /* Standard mode-based argument types. */
13536 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
13537 #define MIPS_ATYPE_SI intSI_type_node
13538 #define MIPS_ATYPE_USI unsigned_intSI_type_node
13539 #define MIPS_ATYPE_DI intDI_type_node
13540 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
13541 #define MIPS_ATYPE_SF float_type_node
13542 #define MIPS_ATYPE_DF double_type_node
13544 /* Vector argument types. */
13545 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
13546 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
13547 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
13548 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
13549 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
13550 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
13551 #define MIPS_ATYPE_UV2SI \
13552 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
13553 #define MIPS_ATYPE_UV4HI \
13554 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
13555 #define MIPS_ATYPE_UV8QI \
13556 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
13558 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
13559 their associated MIPS_ATYPEs. */
13560 #define MIPS_FTYPE_ATYPES1(A, B) \
13561 MIPS_ATYPE_##A, MIPS_ATYPE_##B
13563 #define MIPS_FTYPE_ATYPES2(A, B, C) \
13564 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
13566 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
13567 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
13569 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
13570 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
13573 /* Return the function type associated with function prototype TYPE. */
13576 mips_build_function_type (enum mips_function_type type)
13578 static tree types[(int) MIPS_MAX_FTYPE_MAX];
13580 if (types[(int) type] == NULL_TREE)
13583 #define DEF_MIPS_FTYPE(NUM, ARGS) \
13584 case MIPS_FTYPE_NAME##NUM ARGS: \
13585 types[(int) type] \
13586 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
13589 #include "config/mips/mips-ftypes.def"
13590 #undef DEF_MIPS_FTYPE
13592 gcc_unreachable ();
13595 return types[(int) type];
13598 /* Implement TARGET_INIT_BUILTINS. */
13601 mips_init_builtins (void)
13603 const struct mips_builtin_description *d;
13606 /* Iterate through all of the bdesc arrays, initializing all of the
13607 builtin functions. */
13608 for (i = 0; i < ARRAY_SIZE (mips_builtins); i++)
13610 d = &mips_builtins[i];
13612 mips_builtin_decls[i]
13613 = add_builtin_function (d->name,
13614 mips_build_function_type (d->function_type),
13615 i, BUILT_IN_MD, NULL, NULL);
13619 /* Implement TARGET_BUILTIN_DECL. */
13622 mips_builtin_decl (unsigned int code, bool initialize_p ATTRIBUTE_UNUSED)
13624 if (code >= ARRAY_SIZE (mips_builtins))
13625 return error_mark_node;
13626 return mips_builtin_decls[code];
13629 /* Take argument ARGNO from EXP's argument list and convert it into
13630 an expand operand. Store the operand in *OP. */
13633 mips_prepare_builtin_arg (struct expand_operand *op, tree exp,
13634 unsigned int argno)
13639 arg = CALL_EXPR_ARG (exp, argno);
13640 value = expand_normal (arg);
13641 create_input_operand (op, value, TYPE_MODE (TREE_TYPE (arg)));
13644 /* Expand instruction ICODE as part of a built-in function sequence.
13645 Use the first NOPS elements of OPS as the instruction's operands.
13646 HAS_TARGET_P is true if operand 0 is a target; it is false if the
13647 instruction has no target.
13649 Return the target rtx if HAS_TARGET_P, otherwise return const0_rtx. */
13652 mips_expand_builtin_insn (enum insn_code icode, unsigned int nops,
13653 struct expand_operand *ops, bool has_target_p)
13655 if (!maybe_expand_insn (icode, nops, ops))
13657 error ("invalid argument to built-in function");
13658 return has_target_p ? gen_reg_rtx (ops[0].mode) : const0_rtx;
13660 return has_target_p ? ops[0].value : const0_rtx;
13663 /* Expand a floating-point comparison for built-in function call EXP.
13664 The first NARGS arguments are the values to be compared. ICODE is
13665 the .md pattern that does the comparison and COND is the condition
13666 that is being tested. Return an rtx for the result. */
13669 mips_expand_builtin_compare_1 (enum insn_code icode,
13670 enum mips_fp_condition cond,
13671 tree exp, int nargs)
13673 struct expand_operand ops[MAX_RECOG_OPERANDS];
13676 /* The instruction should have a target operand, an operand for each
13677 argument, and an operand for COND. */
13678 gcc_assert (nargs + 2 == insn_data[(int) icode].n_generator_args);
13681 create_output_operand (&ops[opno++], NULL_RTX,
13682 insn_data[(int) icode].operand[0].mode);
13683 for (argno = 0; argno < nargs; argno++)
13684 mips_prepare_builtin_arg (&ops[opno++], exp, argno);
13685 create_integer_operand (&ops[opno++], (int) cond);
13686 return mips_expand_builtin_insn (icode, opno, ops, true);
13689 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
13690 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
13691 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
13692 suggests a good place to put the result. */
13695 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
13698 struct expand_operand ops[MAX_RECOG_OPERANDS];
13701 /* Map any target to operand 0. */
13704 create_output_operand (&ops[opno++], target, TYPE_MODE (TREE_TYPE (exp)));
13706 /* Map the arguments to the other operands. */
13707 gcc_assert (opno + call_expr_nargs (exp)
13708 == insn_data[icode].n_generator_args);
13709 for (argno = 0; argno < call_expr_nargs (exp); argno++)
13710 mips_prepare_builtin_arg (&ops[opno++], exp, argno);
13712 return mips_expand_builtin_insn (icode, opno, ops, has_target_p);
13715 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
13716 function; TYPE says which. EXP is the CALL_EXPR that calls the
13717 function, ICODE is the instruction that should be used to compare
13718 the first two arguments, and COND is the condition it should test.
13719 TARGET, if nonnull, suggests a good place to put the result. */
13722 mips_expand_builtin_movtf (enum mips_builtin_type type,
13723 enum insn_code icode, enum mips_fp_condition cond,
13724 rtx target, tree exp)
13726 struct expand_operand ops[4];
13729 cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp, 2);
13730 create_output_operand (&ops[0], target, TYPE_MODE (TREE_TYPE (exp)));
13731 if (type == MIPS_BUILTIN_MOVT)
13733 mips_prepare_builtin_arg (&ops[2], exp, 2);
13734 mips_prepare_builtin_arg (&ops[1], exp, 3);
13738 mips_prepare_builtin_arg (&ops[1], exp, 2);
13739 mips_prepare_builtin_arg (&ops[2], exp, 3);
13741 create_fixed_operand (&ops[3], cmp_result);
13742 return mips_expand_builtin_insn (CODE_FOR_mips_cond_move_tf_ps,
13746 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
13747 into TARGET otherwise. Return TARGET. */
13750 mips_builtin_branch_and_move (rtx condition, rtx target,
13751 rtx value_if_true, rtx value_if_false)
13753 rtx true_label, done_label;
13755 true_label = gen_label_rtx ();
13756 done_label = gen_label_rtx ();
13758 /* First assume that CONDITION is false. */
13759 mips_emit_move (target, value_if_false);
13761 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
13762 emit_jump_insn (gen_condjump (condition, true_label));
13763 emit_jump_insn (gen_jump (done_label));
13766 /* Fix TARGET if CONDITION is true. */
13767 emit_label (true_label);
13768 mips_emit_move (target, value_if_true);
13770 emit_label (done_label);
13774 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
13775 the CALL_EXPR that calls the function, ICODE is the code of the
13776 comparison instruction, and COND is the condition it should test.
13777 TARGET, if nonnull, suggests a good place to put the boolean result. */
13780 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
13781 enum insn_code icode, enum mips_fp_condition cond,
13782 rtx target, tree exp)
13784 rtx offset, condition, cmp_result;
13786 if (target == 0 || GET_MODE (target) != SImode)
13787 target = gen_reg_rtx (SImode);
13788 cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp,
13789 call_expr_nargs (exp));
13791 /* If the comparison sets more than one register, we define the result
13792 to be 0 if all registers are false and -1 if all registers are true.
13793 The value of the complete result is indeterminate otherwise. */
13794 switch (builtin_type)
13796 case MIPS_BUILTIN_CMP_ALL:
13797 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
13798 return mips_builtin_branch_and_move (condition, target,
13799 const0_rtx, const1_rtx);
13801 case MIPS_BUILTIN_CMP_UPPER:
13802 case MIPS_BUILTIN_CMP_LOWER:
13803 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
13804 condition = gen_single_cc (cmp_result, offset);
13805 return mips_builtin_branch_and_move (condition, target,
13806 const1_rtx, const0_rtx);
13809 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
13810 return mips_builtin_branch_and_move (condition, target,
13811 const1_rtx, const0_rtx);
13815 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
13816 if nonnull, suggests a good place to put the boolean result. */
13819 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
13821 rtx condition, cmp_result;
13824 if (target == 0 || GET_MODE (target) != SImode)
13825 target = gen_reg_rtx (SImode);
13827 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
13829 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
13834 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
13835 return mips_builtin_branch_and_move (condition, target,
13836 const1_rtx, const0_rtx);
13839 /* Implement TARGET_EXPAND_BUILTIN. */
13842 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
13843 enum machine_mode mode, int ignore)
13846 unsigned int fcode, avail;
13847 const struct mips_builtin_description *d;
13849 fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
13850 fcode = DECL_FUNCTION_CODE (fndecl);
13851 gcc_assert (fcode < ARRAY_SIZE (mips_builtins));
13852 d = &mips_builtins[fcode];
13853 avail = d->avail ();
13854 gcc_assert (avail != 0);
13857 error ("built-in function %qE not supported for MIPS16",
13858 DECL_NAME (fndecl));
13859 return ignore ? const0_rtx : CONST0_RTX (mode);
13861 switch (d->builtin_type)
13863 case MIPS_BUILTIN_DIRECT:
13864 return mips_expand_builtin_direct (d->icode, target, exp, true);
13866 case MIPS_BUILTIN_DIRECT_NO_TARGET:
13867 return mips_expand_builtin_direct (d->icode, target, exp, false);
13869 case MIPS_BUILTIN_MOVT:
13870 case MIPS_BUILTIN_MOVF:
13871 return mips_expand_builtin_movtf (d->builtin_type, d->icode,
13872 d->cond, target, exp);
13874 case MIPS_BUILTIN_CMP_ANY:
13875 case MIPS_BUILTIN_CMP_ALL:
13876 case MIPS_BUILTIN_CMP_UPPER:
13877 case MIPS_BUILTIN_CMP_LOWER:
13878 case MIPS_BUILTIN_CMP_SINGLE:
13879 return mips_expand_builtin_compare (d->builtin_type, d->icode,
13880 d->cond, target, exp);
13882 case MIPS_BUILTIN_BPOSGE32:
13883 return mips_expand_builtin_bposge (d->builtin_type, target);
13885 gcc_unreachable ();
13888 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
13889 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
13890 struct mips16_constant {
13891 struct mips16_constant *next;
13894 enum machine_mode mode;
13897 /* Information about an incomplete MIPS16 constant pool. FIRST is the
13898 first constant, HIGHEST_ADDRESS is the highest address that the first
13899 byte of the pool can have, and INSN_ADDRESS is the current instruction
13901 struct mips16_constant_pool {
13902 struct mips16_constant *first;
13903 int highest_address;
13907 /* Add constant VALUE to POOL and return its label. MODE is the
13908 value's mode (used for CONST_INTs, etc.). */
13911 mips16_add_constant (struct mips16_constant_pool *pool,
13912 rtx value, enum machine_mode mode)
13914 struct mips16_constant **p, *c;
13915 bool first_of_size_p;
13917 /* See whether the constant is already in the pool. If so, return the
13918 existing label, otherwise leave P pointing to the place where the
13919 constant should be added.
13921 Keep the pool sorted in increasing order of mode size so that we can
13922 reduce the number of alignments needed. */
13923 first_of_size_p = true;
13924 for (p = &pool->first; *p != 0; p = &(*p)->next)
13926 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
13927 return (*p)->label;
13928 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
13930 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
13931 first_of_size_p = false;
13934 /* In the worst case, the constant needed by the earliest instruction
13935 will end up at the end of the pool. The entire pool must then be
13936 accessible from that instruction.
13938 When adding the first constant, set the pool's highest address to
13939 the address of the first out-of-range byte. Adjust this address
13940 downwards each time a new constant is added. */
13941 if (pool->first == 0)
13942 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
13943 of the instruction with the lowest two bits clear. The base PC
13944 value for LDPC has the lowest three bits clear. Assume the worst
13945 case here; namely that the PC-relative instruction occupies the
13946 last 2 bytes in an aligned word. */
13947 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
13948 pool->highest_address -= GET_MODE_SIZE (mode);
13949 if (first_of_size_p)
13950 /* Take into account the worst possible padding due to alignment. */
13951 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
13953 /* Create a new entry. */
13954 c = XNEW (struct mips16_constant);
13957 c->label = gen_label_rtx ();
13964 /* Output constant VALUE after instruction INSN and return the last
13965 instruction emitted. MODE is the mode of the constant. */
13968 mips16_emit_constants_1 (enum machine_mode mode, rtx value, rtx insn)
13970 if (SCALAR_INT_MODE_P (mode) || ALL_SCALAR_FIXED_POINT_MODE_P (mode))
13972 rtx size = GEN_INT (GET_MODE_SIZE (mode));
13973 return emit_insn_after (gen_consttable_int (value, size), insn);
13976 if (SCALAR_FLOAT_MODE_P (mode))
13977 return emit_insn_after (gen_consttable_float (value), insn);
13979 if (VECTOR_MODE_P (mode))
13983 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
13984 insn = mips16_emit_constants_1 (GET_MODE_INNER (mode),
13985 CONST_VECTOR_ELT (value, i), insn);
13989 gcc_unreachable ();
13992 /* Dump out the constants in CONSTANTS after INSN. */
13995 mips16_emit_constants (struct mips16_constant *constants, rtx insn)
13997 struct mips16_constant *c, *next;
14001 for (c = constants; c != NULL; c = next)
14003 /* If necessary, increase the alignment of PC. */
14004 if (align < GET_MODE_SIZE (c->mode))
14006 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
14007 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
14009 align = GET_MODE_SIZE (c->mode);
14011 insn = emit_label_after (c->label, insn);
14012 insn = mips16_emit_constants_1 (c->mode, c->value, insn);
14018 emit_barrier_after (insn);
14021 /* Return the length of instruction INSN. */
14024 mips16_insn_length (rtx insn)
14028 rtx body = PATTERN (insn);
14029 if (GET_CODE (body) == ADDR_VEC)
14030 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
14031 if (GET_CODE (body) == ADDR_DIFF_VEC)
14032 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
14034 return get_attr_length (insn);
14037 /* If *X is a symbolic constant that refers to the constant pool, add
14038 the constant to POOL and rewrite *X to use the constant's label. */
14041 mips16_rewrite_pool_constant (struct mips16_constant_pool *pool, rtx *x)
14043 rtx base, offset, label;
14045 split_const (*x, &base, &offset);
14046 if (GET_CODE (base) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (base))
14048 label = mips16_add_constant (pool, get_pool_constant (base),
14049 get_pool_mode (base));
14050 base = gen_rtx_LABEL_REF (Pmode, label);
14051 *x = mips_unspec_address_offset (base, offset, SYMBOL_PC_RELATIVE);
14055 /* This structure is used to communicate with mips16_rewrite_pool_refs.
14056 INSN is the instruction we're rewriting and POOL points to the current
14058 struct mips16_rewrite_pool_refs_info {
14060 struct mips16_constant_pool *pool;
14063 /* Rewrite *X so that constant pool references refer to the constant's
14064 label instead. DATA points to a mips16_rewrite_pool_refs_info
14068 mips16_rewrite_pool_refs (rtx *x, void *data)
14070 struct mips16_rewrite_pool_refs_info *info =
14071 (struct mips16_rewrite_pool_refs_info *) data;
14073 if (force_to_mem_operand (*x, Pmode))
14075 rtx mem = force_const_mem (GET_MODE (*x), *x);
14076 validate_change (info->insn, x, mem, false);
14081 mips16_rewrite_pool_constant (info->pool, &XEXP (*x, 0));
14085 /* Don't rewrite the __mips16_rdwr symbol. */
14086 if (GET_CODE (*x) == UNSPEC && XINT (*x, 1) == UNSPEC_TLS_GET_TP)
14089 if (TARGET_MIPS16_TEXT_LOADS)
14090 mips16_rewrite_pool_constant (info->pool, x);
14092 return GET_CODE (*x) == CONST ? -1 : 0;
14095 /* Return whether CFG is used in mips_reorg. */
14098 mips_cfg_in_reorg (void)
14100 return (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
14101 || TARGET_RELAX_PIC_CALLS);
14104 /* Build MIPS16 constant pools. */
14107 mips16_lay_out_constants (void)
14109 struct mips16_constant_pool pool;
14110 struct mips16_rewrite_pool_refs_info info;
14113 if (!TARGET_MIPS16_PCREL_LOADS)
14116 if (mips_cfg_in_reorg ())
14117 split_all_insns ();
14119 split_all_insns_noflow ();
14121 memset (&pool, 0, sizeof (pool));
14122 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
14124 /* Rewrite constant pool references in INSN. */
14125 if (USEFUL_INSN_P (insn))
14129 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &info);
14132 pool.insn_address += mips16_insn_length (insn);
14134 if (pool.first != NULL)
14136 /* If there are no natural barriers between the first user of
14137 the pool and the highest acceptable address, we'll need to
14138 create a new instruction to jump around the constant pool.
14139 In the worst case, this instruction will be 4 bytes long.
14141 If it's too late to do this transformation after INSN,
14142 do it immediately before INSN. */
14143 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
14147 label = gen_label_rtx ();
14149 jump = emit_jump_insn_before (gen_jump (label), insn);
14150 JUMP_LABEL (jump) = label;
14151 LABEL_NUSES (label) = 1;
14152 barrier = emit_barrier_after (jump);
14154 emit_label_after (label, barrier);
14155 pool.insn_address += 4;
14158 /* See whether the constant pool is now out of range of the first
14159 user. If so, output the constants after the previous barrier.
14160 Note that any instructions between BARRIER and INSN (inclusive)
14161 will use negative offsets to refer to the pool. */
14162 if (pool.insn_address > pool.highest_address)
14164 mips16_emit_constants (pool.first, barrier);
14168 else if (BARRIER_P (insn))
14172 mips16_emit_constants (pool.first, get_last_insn ());
14175 /* Return true if it is worth r10k_simplify_address's while replacing
14176 an address with X. We are looking for constants, and for addresses
14177 at a known offset from the incoming stack pointer. */
14180 r10k_simplified_address_p (rtx x)
14182 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
14184 return x == virtual_incoming_args_rtx || CONSTANT_P (x);
14187 /* X is an expression that appears in INSN. Try to use the UD chains
14188 to simplify it, returning the simplified form on success and the
14189 original form otherwise. Replace the incoming value of $sp with
14190 virtual_incoming_args_rtx (which should never occur in X otherwise). */
14193 r10k_simplify_address (rtx x, rtx insn)
14195 rtx newx, op0, op1, set, def_insn, note;
14197 struct df_link *defs;
14202 op0 = r10k_simplify_address (XEXP (x, 0), insn);
14203 if (op0 != XEXP (x, 0))
14204 newx = simplify_gen_unary (GET_CODE (x), GET_MODE (x),
14205 op0, GET_MODE (XEXP (x, 0)));
14207 else if (BINARY_P (x))
14209 op0 = r10k_simplify_address (XEXP (x, 0), insn);
14210 op1 = r10k_simplify_address (XEXP (x, 1), insn);
14211 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
14212 newx = simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
14214 else if (GET_CODE (x) == LO_SUM)
14216 /* LO_SUMs can be offset from HIGHs, if we know they won't
14217 overflow. See mips_classify_address for the rationale behind
14219 op0 = r10k_simplify_address (XEXP (x, 0), insn);
14220 if (GET_CODE (op0) == HIGH)
14221 newx = XEXP (x, 1);
14223 else if (REG_P (x))
14225 /* Uses are recorded by regno_reg_rtx, not X itself. */
14226 use = df_find_use (insn, regno_reg_rtx[REGNO (x)]);
14228 defs = DF_REF_CHAIN (use);
14230 /* Require a single definition. */
14231 if (defs && defs->next == NULL)
14234 if (DF_REF_IS_ARTIFICIAL (def))
14236 /* Replace the incoming value of $sp with
14237 virtual_incoming_args_rtx. */
14238 if (x == stack_pointer_rtx
14239 && DF_REF_BB (def) == ENTRY_BLOCK_PTR)
14240 newx = virtual_incoming_args_rtx;
14242 else if (dominated_by_p (CDI_DOMINATORS, DF_REF_BB (use),
14245 /* Make sure that DEF_INSN is a single set of REG. */
14246 def_insn = DF_REF_INSN (def);
14247 if (NONJUMP_INSN_P (def_insn))
14249 set = single_set (def_insn);
14250 if (set && rtx_equal_p (SET_DEST (set), x))
14252 /* Prefer to use notes, since the def-use chains
14253 are often shorter. */
14254 note = find_reg_equal_equiv_note (def_insn);
14256 newx = XEXP (note, 0);
14258 newx = SET_SRC (set);
14259 newx = r10k_simplify_address (newx, def_insn);
14265 if (newx && r10k_simplified_address_p (newx))
14270 /* Return true if ADDRESS is known to be an uncached address
14271 on R10K systems. */
14274 r10k_uncached_address_p (unsigned HOST_WIDE_INT address)
14276 unsigned HOST_WIDE_INT upper;
14278 /* Check for KSEG1. */
14279 if (address + 0x60000000 < 0x20000000)
14282 /* Check for uncached XKPHYS addresses. */
14283 if (Pmode == DImode)
14285 upper = (address >> 40) & 0xf9ffff;
14286 if (upper == 0x900000 || upper == 0xb80000)
14292 /* Return true if we can prove that an access to address X in instruction
14293 INSN would be safe from R10K speculation. This X is a general
14294 expression; it might not be a legitimate address. */
14297 r10k_safe_address_p (rtx x, rtx insn)
14300 HOST_WIDE_INT offset_val;
14302 x = r10k_simplify_address (x, insn);
14304 /* Check for references to the stack frame. It doesn't really matter
14305 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
14306 allows us to assume that accesses to any part of the eventual frame
14307 is safe from speculation at any point in the function. */
14308 mips_split_plus (x, &base, &offset_val);
14309 if (base == virtual_incoming_args_rtx
14310 && offset_val >= -cfun->machine->frame.total_size
14311 && offset_val < cfun->machine->frame.args_size)
14314 /* Check for uncached addresses. */
14315 if (CONST_INT_P (x))
14316 return r10k_uncached_address_p (INTVAL (x));
14318 /* Check for accesses to a static object. */
14319 split_const (x, &base, &offset);
14320 return offset_within_block_p (base, INTVAL (offset));
14323 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
14324 an in-range access to an automatic variable, or to an object with
14325 a link-time-constant address. */
14328 r10k_safe_mem_expr_p (tree expr, HOST_WIDE_INT offset)
14330 if (offset < 0 || offset >= int_size_in_bytes (TREE_TYPE (expr)))
14333 while (TREE_CODE (expr) == COMPONENT_REF)
14335 expr = TREE_OPERAND (expr, 0);
14336 if (expr == NULL_TREE)
14340 return DECL_P (expr);
14343 /* A for_each_rtx callback for which DATA points to the instruction
14344 containing *X. Stop the search if we find a MEM that is not safe
14345 from R10K speculation. */
14348 r10k_needs_protection_p_1 (rtx *loc, void *data)
14357 && MEM_OFFSET_KNOWN_P (mem)
14358 && r10k_safe_mem_expr_p (MEM_EXPR (mem), MEM_OFFSET (mem)))
14361 if (r10k_safe_address_p (XEXP (mem, 0), (rtx) data))
14367 /* A note_stores callback for which DATA points to an instruction pointer.
14368 If *DATA is nonnull, make it null if it X contains a MEM that is not
14369 safe from R10K speculation. */
14372 r10k_needs_protection_p_store (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
14377 insn_ptr = (rtx *) data;
14378 if (*insn_ptr && for_each_rtx (&x, r10k_needs_protection_p_1, *insn_ptr))
14379 *insn_ptr = NULL_RTX;
14382 /* A for_each_rtx callback that iterates over the pattern of a CALL_INSN.
14383 Return nonzero if the call is not to a declared function. */
14386 r10k_needs_protection_p_call (rtx *loc, void *data ATTRIBUTE_UNUSED)
14395 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DECL (x))
14401 /* Return true if instruction INSN needs to be protected by an R10K
14405 r10k_needs_protection_p (rtx insn)
14408 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_call, NULL);
14410 if (mips_r10k_cache_barrier == R10K_CACHE_BARRIER_STORE)
14412 note_stores (PATTERN (insn), r10k_needs_protection_p_store, &insn);
14413 return insn == NULL_RTX;
14416 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_1, insn);
14419 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
14420 edge is unconditional. */
14423 r10k_protected_bb_p (basic_block bb, sbitmap protected_bbs)
14428 FOR_EACH_EDGE (e, ei, bb->preds)
14429 if (!single_succ_p (e->src)
14430 || !TEST_BIT (protected_bbs, e->src->index)
14431 || (e->flags & EDGE_COMPLEX) != 0)
14436 /* Implement -mr10k-cache-barrier= for the current function. */
14439 r10k_insert_cache_barriers (void)
14441 int *rev_post_order;
14444 sbitmap protected_bbs;
14445 rtx insn, end, unprotected_region;
14449 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
14453 /* Calculate dominators. */
14454 calculate_dominance_info (CDI_DOMINATORS);
14456 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
14457 X is protected by a cache barrier. */
14458 protected_bbs = sbitmap_alloc (last_basic_block);
14459 sbitmap_zero (protected_bbs);
14461 /* Iterate over the basic blocks in reverse post-order. */
14462 rev_post_order = XNEWVEC (int, last_basic_block);
14463 n = pre_and_rev_post_order_compute (NULL, rev_post_order, false);
14464 for (i = 0; i < n; i++)
14466 bb = BASIC_BLOCK (rev_post_order[i]);
14468 /* If this block is only reached by unconditional edges, and if the
14469 source of every edge is protected, the beginning of the block is
14471 if (r10k_protected_bb_p (bb, protected_bbs))
14472 unprotected_region = NULL_RTX;
14474 unprotected_region = pc_rtx;
14475 end = NEXT_INSN (BB_END (bb));
14477 /* UNPROTECTED_REGION is:
14479 - null if we are processing a protected region,
14480 - pc_rtx if we are processing an unprotected region but have
14481 not yet found the first instruction in it
14482 - the first instruction in an unprotected region otherwise. */
14483 for (insn = BB_HEAD (bb); insn != end; insn = NEXT_INSN (insn))
14485 if (unprotected_region && USEFUL_INSN_P (insn))
14487 if (recog_memoized (insn) == CODE_FOR_mips_cache)
14488 /* This CACHE instruction protects the following code. */
14489 unprotected_region = NULL_RTX;
14492 /* See if INSN is the first instruction in this
14493 unprotected region. */
14494 if (unprotected_region == pc_rtx)
14495 unprotected_region = insn;
14497 /* See if INSN needs to be protected. If so,
14498 we must insert a cache barrier somewhere between
14499 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
14500 clear which position is better performance-wise,
14501 but as a tie-breaker, we assume that it is better
14502 to allow delay slots to be back-filled where
14503 possible, and that it is better not to insert
14504 barriers in the middle of already-scheduled code.
14505 We therefore insert the barrier at the beginning
14507 if (r10k_needs_protection_p (insn))
14509 emit_insn_before (gen_r10k_cache_barrier (),
14510 unprotected_region);
14511 unprotected_region = NULL_RTX;
14517 /* The called function is not required to protect the exit path.
14518 The code that follows a call is therefore unprotected. */
14519 unprotected_region = pc_rtx;
14522 /* Record whether the end of this block is protected. */
14523 if (unprotected_region == NULL_RTX)
14524 SET_BIT (protected_bbs, bb->index);
14526 XDELETEVEC (rev_post_order);
14528 sbitmap_free (protected_bbs);
14530 free_dominance_info (CDI_DOMINATORS);
14533 /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX
14534 otherwise. If INSN has two call rtx, then store the second one in
14538 mips_call_expr_from_insn (rtx insn, rtx *second_call)
14543 if (!CALL_P (insn))
14546 x = PATTERN (insn);
14547 if (GET_CODE (x) == PARALLEL)
14549 /* Calls returning complex values have two CALL rtx. Look for the second
14550 one here, and return it via the SECOND_CALL arg. */
14551 x2 = XVECEXP (x, 0, 1);
14552 if (GET_CODE (x2) == SET)
14554 if (GET_CODE (x2) == CALL)
14557 x = XVECEXP (x, 0, 0);
14559 if (GET_CODE (x) == SET)
14561 gcc_assert (GET_CODE (x) == CALL);
14566 /* REG is set in DEF. See if the definition is one of the ways we load a
14567 register with a symbol address for a mips_use_pic_fn_addr_reg_p call.
14568 If it is, return the symbol reference of the function, otherwise return
14571 If RECURSE_P is true, use mips_find_pic_call_symbol to interpret
14572 the values of source registers, otherwise treat such registers as
14573 having an unknown value. */
14576 mips_pic_call_symbol_from_set (df_ref def, rtx reg, bool recurse_p)
14580 if (DF_REF_IS_ARTIFICIAL (def))
14583 def_insn = DF_REF_INSN (def);
14584 set = single_set (def_insn);
14585 if (set && rtx_equal_p (SET_DEST (set), reg))
14587 rtx note, src, symbol;
14589 /* First, look at REG_EQUAL/EQUIV notes. */
14590 note = find_reg_equal_equiv_note (def_insn);
14591 if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF)
14592 return XEXP (note, 0);
14594 /* For %call16 references we don't have REG_EQUAL. */
14595 src = SET_SRC (set);
14596 symbol = mips_strip_unspec_call (src);
14599 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
14603 /* Follow at most one simple register copy. Such copies are
14604 interesting in cases like:
14608 locally_binding_fn (...);
14613 locally_binding_fn (...);
14615 locally_binding_fn (...);
14617 where the load of locally_binding_fn can legitimately be
14618 hoisted or shared. However, we do not expect to see complex
14619 chains of copies, so a full worklist solution to the problem
14620 would probably be overkill. */
14621 if (recurse_p && REG_P (src))
14622 return mips_find_pic_call_symbol (def_insn, src, false);
14628 /* Find the definition of the use of REG in INSN. See if the definition
14629 is one of the ways we load a register with a symbol address for a
14630 mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference
14631 of the function, otherwise return NULL_RTX. RECURSE_P is as for
14632 mips_pic_call_symbol_from_set. */
14635 mips_find_pic_call_symbol (rtx insn, rtx reg, bool recurse_p)
14638 struct df_link *defs;
14641 use = df_find_use (insn, regno_reg_rtx[REGNO (reg)]);
14644 defs = DF_REF_CHAIN (use);
14647 symbol = mips_pic_call_symbol_from_set (defs->ref, reg, recurse_p);
14651 /* If we have more than one definition, they need to be identical. */
14652 for (defs = defs->next; defs; defs = defs->next)
14656 other = mips_pic_call_symbol_from_set (defs->ref, reg, recurse_p);
14657 if (!rtx_equal_p (symbol, other))
14664 /* Replace the args_size operand of the call expression CALL with the
14665 call-attribute UNSPEC and fill in SYMBOL as the function symbol. */
14668 mips_annotate_pic_call_expr (rtx call, rtx symbol)
14672 args_size = XEXP (call, 1);
14673 XEXP (call, 1) = gen_rtx_UNSPEC (GET_MODE (args_size),
14674 gen_rtvec (2, args_size, symbol),
14678 /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See
14679 if instead of the arg_size argument it contains the call attributes. If
14680 yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function
14681 symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is
14685 mips_get_pic_call_symbol (rtx *operands, int args_size_opno)
14687 rtx args_size, symbol;
14689 if (!TARGET_RELAX_PIC_CALLS || args_size_opno == -1)
14692 args_size = operands[args_size_opno];
14693 if (GET_CODE (args_size) != UNSPEC)
14695 gcc_assert (XINT (args_size, 1) == UNSPEC_CALL_ATTR);
14697 symbol = XVECEXP (args_size, 0, 1);
14698 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
14700 operands[args_size_opno] = symbol;
14704 /* Use DF to annotate PIC indirect calls with the function symbol they
14708 mips_annotate_pic_calls (void)
14714 FOR_BB_INSNS (bb, insn)
14716 rtx call, reg, symbol, second_call;
14719 call = mips_call_expr_from_insn (insn, &second_call);
14722 gcc_assert (MEM_P (XEXP (call, 0)));
14723 reg = XEXP (XEXP (call, 0), 0);
14727 symbol = mips_find_pic_call_symbol (insn, reg, true);
14730 mips_annotate_pic_call_expr (call, symbol);
14732 mips_annotate_pic_call_expr (second_call, symbol);
14737 /* A temporary variable used by for_each_rtx callbacks, etc. */
14738 static rtx mips_sim_insn;
14740 /* A structure representing the state of the processor pipeline.
14741 Used by the mips_sim_* family of functions. */
14743 /* The maximum number of instructions that can be issued in a cycle.
14744 (Caches mips_issue_rate.) */
14745 unsigned int issue_rate;
14747 /* The current simulation time. */
14750 /* How many more instructions can be issued in the current cycle. */
14751 unsigned int insns_left;
14753 /* LAST_SET[X].INSN is the last instruction to set register X.
14754 LAST_SET[X].TIME is the time at which that instruction was issued.
14755 INSN is null if no instruction has yet set register X. */
14759 } last_set[FIRST_PSEUDO_REGISTER];
14761 /* The pipeline's current DFA state. */
14765 /* Reset STATE to the initial simulation state. */
14768 mips_sim_reset (struct mips_sim *state)
14771 state->insns_left = state->issue_rate;
14772 memset (&state->last_set, 0, sizeof (state->last_set));
14773 state_reset (state->dfa_state);
14776 /* Initialize STATE before its first use. DFA_STATE points to an
14777 allocated but uninitialized DFA state. */
14780 mips_sim_init (struct mips_sim *state, state_t dfa_state)
14782 state->issue_rate = mips_issue_rate ();
14783 state->dfa_state = dfa_state;
14784 mips_sim_reset (state);
14787 /* Advance STATE by one clock cycle. */
14790 mips_sim_next_cycle (struct mips_sim *state)
14793 state->insns_left = state->issue_rate;
14794 state_transition (state->dfa_state, 0);
14797 /* Advance simulation state STATE until instruction INSN can read
14801 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
14803 unsigned int regno, end_regno;
14805 end_regno = END_REGNO (reg);
14806 for (regno = REGNO (reg); regno < end_regno; regno++)
14807 if (state->last_set[regno].insn != 0)
14811 t = (state->last_set[regno].time
14812 + insn_latency (state->last_set[regno].insn, insn));
14813 while (state->time < t)
14814 mips_sim_next_cycle (state);
14818 /* A for_each_rtx callback. If *X is a register, advance simulation state
14819 DATA until mips_sim_insn can read the register's value. */
14822 mips_sim_wait_regs_2 (rtx *x, void *data)
14825 mips_sim_wait_reg ((struct mips_sim *) data, mips_sim_insn, *x);
14829 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
14832 mips_sim_wait_regs_1 (rtx *x, void *data)
14834 for_each_rtx (x, mips_sim_wait_regs_2, data);
14837 /* Advance simulation state STATE until all of INSN's register
14838 dependencies are satisfied. */
14841 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
14843 mips_sim_insn = insn;
14844 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
14847 /* Advance simulation state STATE until the units required by
14848 instruction INSN are available. */
14851 mips_sim_wait_units (struct mips_sim *state, rtx insn)
14855 tmp_state = alloca (state_size ());
14856 while (state->insns_left == 0
14857 || (memcpy (tmp_state, state->dfa_state, state_size ()),
14858 state_transition (tmp_state, insn) >= 0))
14859 mips_sim_next_cycle (state);
14862 /* Advance simulation state STATE until INSN is ready to issue. */
14865 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
14867 mips_sim_wait_regs (state, insn);
14868 mips_sim_wait_units (state, insn);
14871 /* mips_sim_insn has just set X. Update the LAST_SET array
14872 in simulation state DATA. */
14875 mips_sim_record_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
14877 struct mips_sim *state;
14879 state = (struct mips_sim *) data;
14882 unsigned int regno, end_regno;
14884 end_regno = END_REGNO (x);
14885 for (regno = REGNO (x); regno < end_regno; regno++)
14887 state->last_set[regno].insn = mips_sim_insn;
14888 state->last_set[regno].time = state->time;
14893 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
14894 can issue immediately (i.e., that mips_sim_wait_insn has already
14898 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
14900 state_transition (state->dfa_state, insn);
14901 state->insns_left--;
14903 mips_sim_insn = insn;
14904 note_stores (PATTERN (insn), mips_sim_record_set, state);
14907 /* Simulate issuing a NOP in state STATE. */
14910 mips_sim_issue_nop (struct mips_sim *state)
14912 if (state->insns_left == 0)
14913 mips_sim_next_cycle (state);
14914 state->insns_left--;
14917 /* Update simulation state STATE so that it's ready to accept the instruction
14918 after INSN. INSN should be part of the main rtl chain, not a member of a
14922 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
14924 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
14926 mips_sim_issue_nop (state);
14928 switch (GET_CODE (SEQ_BEGIN (insn)))
14932 /* We can't predict the processor state after a call or label. */
14933 mips_sim_reset (state);
14937 /* The delay slots of branch likely instructions are only executed
14938 when the branch is taken. Therefore, if the caller has simulated
14939 the delay slot instruction, STATE does not really reflect the state
14940 of the pipeline for the instruction after the delay slot. Also,
14941 branch likely instructions tend to incur a penalty when not taken,
14942 so there will probably be an extra delay between the branch and
14943 the instruction after the delay slot. */
14944 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
14945 mips_sim_reset (state);
14953 /* The VR4130 pipeline issues aligned pairs of instructions together,
14954 but it stalls the second instruction if it depends on the first.
14955 In order to cut down the amount of logic required, this dependence
14956 check is not based on a full instruction decode. Instead, any non-SPECIAL
14957 instruction is assumed to modify the register specified by bits 20-16
14958 (which is usually the "rt" field).
14960 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
14961 input, so we can end up with a false dependence between the branch
14962 and its delay slot. If this situation occurs in instruction INSN,
14963 try to avoid it by swapping rs and rt. */
14966 vr4130_avoid_branch_rt_conflict (rtx insn)
14970 first = SEQ_BEGIN (insn);
14971 second = SEQ_END (insn);
14973 && NONJUMP_INSN_P (second)
14974 && GET_CODE (PATTERN (first)) == SET
14975 && GET_CODE (SET_DEST (PATTERN (first))) == PC
14976 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
14978 /* Check for the right kind of condition. */
14979 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
14980 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
14981 && REG_P (XEXP (cond, 0))
14982 && REG_P (XEXP (cond, 1))
14983 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
14984 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
14986 /* SECOND mentions the rt register but not the rs register. */
14987 rtx tmp = XEXP (cond, 0);
14988 XEXP (cond, 0) = XEXP (cond, 1);
14989 XEXP (cond, 1) = tmp;
14994 /* Implement -mvr4130-align. Go through each basic block and simulate the
14995 processor pipeline. If we find that a pair of instructions could execute
14996 in parallel, and the first of those instructions is not 8-byte aligned,
14997 insert a nop to make it aligned. */
15000 vr4130_align_insns (void)
15002 struct mips_sim state;
15003 rtx insn, subinsn, last, last2, next;
15008 /* LAST is the last instruction before INSN to have a nonzero length.
15009 LAST2 is the last such instruction before LAST. */
15013 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
15016 mips_sim_init (&state, alloca (state_size ()));
15017 for (insn = get_insns (); insn != 0; insn = next)
15019 unsigned int length;
15021 next = NEXT_INSN (insn);
15023 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
15024 This isn't really related to the alignment pass, but we do it on
15025 the fly to avoid a separate instruction walk. */
15026 vr4130_avoid_branch_rt_conflict (insn);
15028 if (USEFUL_INSN_P (insn))
15029 FOR_EACH_SUBINSN (subinsn, insn)
15031 mips_sim_wait_insn (&state, subinsn);
15033 /* If we want this instruction to issue in parallel with the
15034 previous one, make sure that the previous instruction is
15035 aligned. There are several reasons why this isn't worthwhile
15036 when the second instruction is a call:
15038 - Calls are less likely to be performance critical,
15039 - There's a good chance that the delay slot can execute
15040 in parallel with the call.
15041 - The return address would then be unaligned.
15043 In general, if we're going to insert a nop between instructions
15044 X and Y, it's better to insert it immediately after X. That
15045 way, if the nop makes Y aligned, it will also align any labels
15046 between X and Y. */
15047 if (state.insns_left != state.issue_rate
15048 && !CALL_P (subinsn))
15050 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
15052 /* SUBINSN is the first instruction in INSN and INSN is
15053 aligned. We want to align the previous instruction
15054 instead, so insert a nop between LAST2 and LAST.
15056 Note that LAST could be either a single instruction
15057 or a branch with a delay slot. In the latter case,
15058 LAST, like INSN, is already aligned, but the delay
15059 slot must have some extra delay that stops it from
15060 issuing at the same time as the branch. We therefore
15061 insert a nop before the branch in order to align its
15063 emit_insn_after (gen_nop (), last2);
15066 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
15068 /* SUBINSN is the delay slot of INSN, but INSN is
15069 currently unaligned. Insert a nop between
15070 LAST and INSN to align it. */
15071 emit_insn_after (gen_nop (), last);
15075 mips_sim_issue_insn (&state, subinsn);
15077 mips_sim_finish_insn (&state, insn);
15079 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
15080 length = get_attr_length (insn);
15083 /* If the instruction is an asm statement or multi-instruction
15084 mips.md patern, the length is only an estimate. Insert an
15085 8 byte alignment after it so that the following instructions
15086 can be handled correctly. */
15087 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
15088 && (recog_memoized (insn) < 0 || length >= 8))
15090 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
15091 next = NEXT_INSN (next);
15092 mips_sim_next_cycle (&state);
15095 else if (length & 4)
15096 aligned_p = !aligned_p;
15101 /* See whether INSN is an aligned label. */
15102 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
15108 /* This structure records that the current function has a LO_SUM
15109 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
15110 the largest offset applied to BASE by all such LO_SUMs. */
15111 struct mips_lo_sum_offset {
15113 HOST_WIDE_INT offset;
15116 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
15119 mips_hash_base (rtx base)
15121 int do_not_record_p;
15123 return hash_rtx (base, GET_MODE (base), &do_not_record_p, NULL, false);
15126 /* Hash-table callbacks for mips_lo_sum_offsets. */
15129 mips_lo_sum_offset_hash (const void *entry)
15131 return mips_hash_base (((const struct mips_lo_sum_offset *) entry)->base);
15135 mips_lo_sum_offset_eq (const void *entry, const void *value)
15137 return rtx_equal_p (((const struct mips_lo_sum_offset *) entry)->base,
15138 (const_rtx) value);
15141 /* Look up symbolic constant X in HTAB, which is a hash table of
15142 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
15143 paired with a recorded LO_SUM, otherwise record X in the table. */
15146 mips_lo_sum_offset_lookup (htab_t htab, rtx x, enum insert_option option)
15150 struct mips_lo_sum_offset *entry;
15152 /* Split X into a base and offset. */
15153 split_const (x, &base, &offset);
15154 if (UNSPEC_ADDRESS_P (base))
15155 base = UNSPEC_ADDRESS (base);
15157 /* Look up the base in the hash table. */
15158 slot = htab_find_slot_with_hash (htab, base, mips_hash_base (base), option);
15162 entry = (struct mips_lo_sum_offset *) *slot;
15163 if (option == INSERT)
15167 entry = XNEW (struct mips_lo_sum_offset);
15168 entry->base = base;
15169 entry->offset = INTVAL (offset);
15174 if (INTVAL (offset) > entry->offset)
15175 entry->offset = INTVAL (offset);
15178 return INTVAL (offset) <= entry->offset;
15181 /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table.
15182 Record every LO_SUM in *LOC. */
15185 mips_record_lo_sum (rtx *loc, void *data)
15187 if (GET_CODE (*loc) == LO_SUM)
15188 mips_lo_sum_offset_lookup ((htab_t) data, XEXP (*loc, 1), INSERT);
15192 /* Return true if INSN is a SET of an orphaned high-part relocation.
15193 HTAB is a hash table of mips_lo_sum_offsets that describes all the
15194 LO_SUMs in the current function. */
15197 mips_orphaned_high_part_p (htab_t htab, rtx insn)
15199 enum mips_symbol_type type;
15202 set = single_set (insn);
15205 /* Check for %his. */
15207 if (GET_CODE (x) == HIGH
15208 && absolute_symbolic_operand (XEXP (x, 0), VOIDmode))
15209 return !mips_lo_sum_offset_lookup (htab, XEXP (x, 0), NO_INSERT);
15211 /* Check for local %gots (and %got_pages, which is redundant but OK). */
15212 if (GET_CODE (x) == UNSPEC
15213 && XINT (x, 1) == UNSPEC_LOAD_GOT
15214 && mips_symbolic_constant_p (XVECEXP (x, 0, 1),
15215 SYMBOL_CONTEXT_LEA, &type)
15216 && type == SYMBOL_GOTOFF_PAGE)
15217 return !mips_lo_sum_offset_lookup (htab, XVECEXP (x, 0, 1), NO_INSERT);
15222 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
15223 INSN and a previous instruction, avoid it by inserting nops after
15226 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
15227 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
15228 before using the value of that register. *HILO_DELAY counts the
15229 number of instructions since the last hilo hazard (that is,
15230 the number of instructions since the last MFLO or MFHI).
15232 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
15233 for the next instruction.
15235 LO_REG is an rtx for the LO register, used in dependence checking. */
15238 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
15239 rtx *delayed_reg, rtx lo_reg)
15244 pattern = PATTERN (insn);
15246 /* Do not put the whole function in .set noreorder if it contains
15247 an asm statement. We don't know whether there will be hazards
15248 between the asm statement and the gcc-generated code. */
15249 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
15250 cfun->machine->all_noreorder_p = false;
15252 /* Ignore zero-length instructions (barriers and the like). */
15253 ninsns = get_attr_length (insn) / 4;
15257 /* Work out how many nops are needed. Note that we only care about
15258 registers that are explicitly mentioned in the instruction's pattern.
15259 It doesn't matter that calls use the argument registers or that they
15260 clobber hi and lo. */
15261 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
15262 nops = 2 - *hilo_delay;
15263 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
15268 /* Insert the nops between this instruction and the previous one.
15269 Each new nop takes us further from the last hilo hazard. */
15270 *hilo_delay += nops;
15272 emit_insn_after (gen_hazard_nop (), after);
15274 /* Set up the state for the next instruction. */
15275 *hilo_delay += ninsns;
15277 if (INSN_CODE (insn) >= 0)
15278 switch (get_attr_hazard (insn))
15288 set = single_set (insn);
15290 *delayed_reg = SET_DEST (set);
15295 /* Go through the instruction stream and insert nops where necessary.
15296 Also delete any high-part relocations whose partnering low parts
15297 are now all dead. See if the whole function can then be put into
15298 .set noreorder and .set nomacro. */
15301 mips_reorg_process_insns (void)
15303 rtx insn, last_insn, subinsn, next_insn, lo_reg, delayed_reg;
15307 /* Force all instructions to be split into their final form. */
15308 split_all_insns_noflow ();
15310 /* Recalculate instruction lengths without taking nops into account. */
15311 cfun->machine->ignore_hazard_length_p = true;
15312 shorten_branches (get_insns ());
15314 cfun->machine->all_noreorder_p = true;
15316 /* We don't track MIPS16 PC-relative offsets closely enough to make
15317 a good job of "set .noreorder" code in MIPS16 mode. */
15319 cfun->machine->all_noreorder_p = false;
15321 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
15322 if (!TARGET_EXPLICIT_RELOCS)
15323 cfun->machine->all_noreorder_p = false;
15325 /* Profiled functions can't be all noreorder because the profiler
15326 support uses assembler macros. */
15328 cfun->machine->all_noreorder_p = false;
15330 /* Code compiled with -mfix-vr4120 or -mfix-24k can't be all noreorder
15331 because we rely on the assembler to work around some errata. */
15332 if (TARGET_FIX_VR4120 || TARGET_FIX_24K)
15333 cfun->machine->all_noreorder_p = false;
15335 /* The same is true for -mfix-vr4130 if we might generate MFLO or
15336 MFHI instructions. Note that we avoid using MFLO and MFHI if
15337 the VR4130 MACC and DMACC instructions are available instead;
15338 see the *mfhilo_{si,di}_macc patterns. */
15339 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
15340 cfun->machine->all_noreorder_p = false;
15342 htab = htab_create (37, mips_lo_sum_offset_hash,
15343 mips_lo_sum_offset_eq, free);
15345 /* Make a first pass over the instructions, recording all the LO_SUMs. */
15346 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
15347 FOR_EACH_SUBINSN (subinsn, insn)
15348 if (USEFUL_INSN_P (subinsn))
15349 for_each_rtx (&PATTERN (subinsn), mips_record_lo_sum, htab);
15354 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
15356 /* Make a second pass over the instructions. Delete orphaned
15357 high-part relocations or turn them into NOPs. Avoid hazards
15358 by inserting NOPs. */
15359 for (insn = get_insns (); insn != 0; insn = next_insn)
15361 next_insn = NEXT_INSN (insn);
15362 if (USEFUL_INSN_P (insn))
15364 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
15366 /* If we find an orphaned high-part relocation in a delay
15367 slot, it's easier to turn that instruction into a NOP than
15368 to delete it. The delay slot will be a NOP either way. */
15369 FOR_EACH_SUBINSN (subinsn, insn)
15370 if (INSN_P (subinsn))
15372 if (mips_orphaned_high_part_p (htab, subinsn))
15374 PATTERN (subinsn) = gen_nop ();
15375 INSN_CODE (subinsn) = CODE_FOR_nop;
15377 mips_avoid_hazard (last_insn, subinsn, &hilo_delay,
15378 &delayed_reg, lo_reg);
15384 /* INSN is a single instruction. Delete it if it's an
15385 orphaned high-part relocation. */
15386 if (mips_orphaned_high_part_p (htab, insn))
15387 delete_insn (insn);
15388 /* Also delete cache barriers if the last instruction
15389 was an annulled branch. INSN will not be speculatively
15391 else if (recog_memoized (insn) == CODE_FOR_r10k_cache_barrier
15393 && JUMP_P (SEQ_BEGIN (last_insn))
15394 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn)))
15395 delete_insn (insn);
15398 mips_avoid_hazard (last_insn, insn, &hilo_delay,
15399 &delayed_reg, lo_reg);
15406 htab_delete (htab);
15409 /* If we are using a GOT, but have not decided to use a global pointer yet,
15410 see whether we need one to implement long branches. Convert the ghost
15411 global-pointer instructions into real ones if so. */
15414 mips_expand_ghost_gp_insns (void)
15419 /* Quick exit if we already know that we will or won't need a
15421 if (!TARGET_USE_GOT
15422 || cfun->machine->global_pointer == INVALID_REGNUM
15423 || mips_must_initialize_gp_p ())
15426 shorten_branches (get_insns ());
15428 /* Look for a branch that is longer than normal. The normal length for
15429 non-MIPS16 branches is 8, because the length includes the delay slot.
15430 It is 4 for MIPS16, because MIPS16 branches are extended instructions,
15431 but they have no delay slot. */
15432 normal_length = (TARGET_MIPS16 ? 4 : 8);
15433 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
15435 && USEFUL_INSN_P (insn)
15436 && get_attr_length (insn) > normal_length)
15439 if (insn == NULL_RTX)
15442 /* We've now established that we need $gp. */
15443 cfun->machine->must_initialize_gp_p = true;
15444 split_all_insns_noflow ();
15449 /* Subroutine of mips_reorg to manage passes that require DF. */
15452 mips_df_reorg (void)
15454 /* Create def-use chains. */
15455 df_set_flags (DF_EQ_NOTES);
15456 df_chain_add_problem (DF_UD_CHAIN);
15459 if (TARGET_RELAX_PIC_CALLS)
15460 mips_annotate_pic_calls ();
15462 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE)
15463 r10k_insert_cache_barriers ();
15465 df_finish_pass (false);
15468 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
15473 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during
15474 insn splitting in mips16_lay_out_constants, DF insn info is only kept up
15475 to date if the CFG is available. */
15476 if (mips_cfg_in_reorg ())
15477 compute_bb_for_insn ();
15478 mips16_lay_out_constants ();
15479 if (mips_cfg_in_reorg ())
15482 free_bb_for_insn ();
15485 if (optimize > 0 && flag_delayed_branch)
15486 dbr_schedule (get_insns ());
15487 mips_reorg_process_insns ();
15489 && TARGET_EXPLICIT_RELOCS
15491 && TARGET_VR4130_ALIGN)
15492 vr4130_align_insns ();
15493 if (mips_expand_ghost_gp_insns ())
15494 /* The expansion could invalidate some of the VR4130 alignment
15495 optimizations, but this should be an extremely rare case anyhow. */
15496 mips_reorg_process_insns ();
15499 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
15500 in order to avoid duplicating too much logic from elsewhere. */
15503 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
15504 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
15507 rtx this_rtx, temp1, temp2, insn, fnaddr;
15508 bool use_sibcall_p;
15510 /* Pretend to be a post-reload pass while generating rtl. */
15511 reload_completed = 1;
15513 /* Mark the end of the (empty) prologue. */
15514 emit_note (NOTE_INSN_PROLOGUE_END);
15516 /* Determine if we can use a sibcall to call FUNCTION directly. */
15517 fnaddr = XEXP (DECL_RTL (function), 0);
15518 use_sibcall_p = (mips_function_ok_for_sibcall (function, NULL)
15519 && const_call_insn_operand (fnaddr, Pmode));
15521 /* Determine if we need to load FNADDR from the GOT. */
15523 && (mips_got_symbol_type_p
15524 (mips_classify_symbol (fnaddr, SYMBOL_CONTEXT_LEA))))
15526 /* Pick a global pointer. Use a call-clobbered register if
15527 TARGET_CALL_SAVED_GP. */
15528 cfun->machine->global_pointer
15529 = TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM;
15530 cfun->machine->must_initialize_gp_p = true;
15531 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
15533 /* Set up the global pointer for n32 or n64 abicalls. */
15534 mips_emit_loadgp ();
15537 /* We need two temporary registers in some cases. */
15538 temp1 = gen_rtx_REG (Pmode, 2);
15539 temp2 = gen_rtx_REG (Pmode, 3);
15541 /* Find out which register contains the "this" pointer. */
15542 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
15543 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
15545 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST);
15547 /* Add DELTA to THIS_RTX. */
15550 rtx offset = GEN_INT (delta);
15551 if (!SMALL_OPERAND (delta))
15553 mips_emit_move (temp1, offset);
15556 emit_insn (gen_add3_insn (this_rtx, this_rtx, offset));
15559 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
15560 if (vcall_offset != 0)
15564 /* Set TEMP1 to *THIS_RTX. */
15565 mips_emit_move (temp1, gen_rtx_MEM (Pmode, this_rtx));
15567 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
15568 addr = mips_add_offset (temp2, temp1, vcall_offset);
15570 /* Load the offset and add it to THIS_RTX. */
15571 mips_emit_move (temp1, gen_rtx_MEM (Pmode, addr));
15572 emit_insn (gen_add3_insn (this_rtx, this_rtx, temp1));
15575 /* Jump to the target function. Use a sibcall if direct jumps are
15576 allowed, otherwise load the address into a register first. */
15579 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
15580 SIBLING_CALL_P (insn) = 1;
15584 /* This is messy. GAS treats "la $25,foo" as part of a call
15585 sequence and may allow a global "foo" to be lazily bound.
15586 The general move patterns therefore reject this combination.
15588 In this context, lazy binding would actually be OK
15589 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
15590 TARGET_CALL_SAVED_GP; see mips_load_call_address.
15591 We must therefore load the address via a temporary
15592 register if mips_dangerous_for_la25_p.
15594 If we jump to the temporary register rather than $25,
15595 the assembler can use the move insn to fill the jump's
15598 We can use the same technique for MIPS16 code, where $25
15599 is not a valid JR register. */
15600 if (TARGET_USE_PIC_FN_ADDR_REG
15602 && !mips_dangerous_for_la25_p (fnaddr))
15603 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
15604 mips_load_call_address (MIPS_CALL_SIBCALL, temp1, fnaddr);
15606 if (TARGET_USE_PIC_FN_ADDR_REG
15607 && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
15608 mips_emit_move (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
15609 emit_jump_insn (gen_indirect_jump (temp1));
15612 /* Run just enough of rest_of_compilation. This sequence was
15613 "borrowed" from alpha.c. */
15614 insn = get_insns ();
15615 insn_locators_alloc ();
15616 split_all_insns_noflow ();
15617 mips16_lay_out_constants ();
15618 shorten_branches (insn);
15619 final_start_function (insn, file, 1);
15620 final (insn, file, 1);
15621 final_end_function ();
15623 /* Clean up the vars set above. Note that final_end_function resets
15624 the global pointer for us. */
15625 reload_completed = 0;
15628 /* The last argument passed to mips_set_mips16_mode, or negative if the
15629 function hasn't been called yet. */
15630 static int was_mips16_p = -1;
15632 /* Set up the target-dependent global state so that it matches the
15633 current function's ISA mode. */
15636 mips_set_mips16_mode (int mips16_p)
15638 if (mips16_p == was_mips16_p)
15641 /* Restore base settings of various flags. */
15642 target_flags = mips_base_target_flags;
15643 flag_schedule_insns = mips_base_schedule_insns;
15644 flag_reorder_blocks_and_partition = mips_base_reorder_blocks_and_partition;
15645 flag_move_loop_invariants = mips_base_move_loop_invariants;
15646 align_loops = mips_base_align_loops;
15647 align_jumps = mips_base_align_jumps;
15648 align_functions = mips_base_align_functions;
15652 /* Switch to MIPS16 mode. */
15653 target_flags |= MASK_MIPS16;
15655 /* Don't run the scheduler before reload, since it tends to
15656 increase register pressure. */
15657 flag_schedule_insns = 0;
15659 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
15660 the whole function to be in a single section. */
15661 flag_reorder_blocks_and_partition = 0;
15663 /* Don't move loop invariants, because it tends to increase
15664 register pressure. It also introduces an extra move in cases
15665 where the constant is the first operand in a two-operand binary
15666 instruction, or when it forms a register argument to a functon
15668 flag_move_loop_invariants = 0;
15670 target_flags |= MASK_EXPLICIT_RELOCS;
15672 /* Experiments suggest we get the best overall section-anchor
15673 results from using the range of an unextended LW or SW. Code
15674 that makes heavy use of byte or short accesses can do better
15675 with ranges of 0...31 and 0...63 respectively, but most code is
15676 sensitive to the range of LW and SW instead. */
15677 targetm.min_anchor_offset = 0;
15678 targetm.max_anchor_offset = 127;
15680 targetm.const_anchor = 0;
15682 /* MIPS16 has no BAL instruction. */
15683 target_flags &= ~MASK_RELAX_PIC_CALLS;
15685 /* The R4000 errata don't apply to any known MIPS16 cores.
15686 It's simpler to make the R4000 fixes and MIPS16 mode
15687 mutually exclusive. */
15688 target_flags &= ~MASK_FIX_R4000;
15690 if (flag_pic && !TARGET_OLDABI)
15691 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
15694 sorry ("MIPS16 -mxgot code");
15696 if (TARGET_HARD_FLOAT_ABI && !TARGET_OLDABI)
15697 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
15701 /* Switch to normal (non-MIPS16) mode. */
15702 target_flags &= ~MASK_MIPS16;
15704 /* Provide default values for align_* for 64-bit targets. */
15707 if (align_loops == 0)
15709 if (align_jumps == 0)
15711 if (align_functions == 0)
15712 align_functions = 8;
15715 targetm.min_anchor_offset = -32768;
15716 targetm.max_anchor_offset = 32767;
15718 targetm.const_anchor = 0x8000;
15721 /* (Re)initialize MIPS target internals for new ISA. */
15722 mips_init_relocs ();
15726 if (!mips16_globals)
15727 mips16_globals = save_target_globals ();
15729 restore_target_globals (mips16_globals);
15732 restore_target_globals (&default_target_globals);
15734 was_mips16_p = mips16_p;
15737 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
15738 function should use the MIPS16 ISA and switch modes accordingly. */
15741 mips_set_current_function (tree fndecl)
15743 mips_set_mips16_mode (mips_use_mips16_mode_p (fndecl));
15746 /* Allocate a chunk of memory for per-function machine-dependent data. */
15748 static struct machine_function *
15749 mips_init_machine_status (void)
15751 return ggc_alloc_cleared_machine_function ();
15754 /* Return the processor associated with the given ISA level, or null
15755 if the ISA isn't valid. */
15757 static const struct mips_cpu_info *
15758 mips_cpu_info_from_isa (int isa)
15762 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
15763 if (mips_cpu_info_table[i].isa == isa)
15764 return mips_cpu_info_table + i;
15769 /* Return a mips_cpu_info entry determined by an option valued
15772 static const struct mips_cpu_info *
15773 mips_cpu_info_from_opt (int opt)
15777 case MIPS_ARCH_OPTION_FROM_ABI:
15778 /* 'from-abi' selects the most compatible architecture for the
15779 given ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit
15780 ABIs. For the EABIs, we have to decide whether we're using
15781 the 32-bit or 64-bit version. */
15782 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
15783 : ABI_NEEDS_64BIT_REGS ? 3
15784 : (TARGET_64BIT ? 3 : 1));
15786 case MIPS_ARCH_OPTION_NATIVE:
15787 gcc_unreachable ();
15790 return &mips_cpu_info_table[opt];
15794 /* Return a default mips_cpu_info entry, given that no -march= option
15795 was explicitly specified. */
15797 static const struct mips_cpu_info *
15798 mips_default_arch (void)
15800 #if defined (MIPS_CPU_STRING_DEFAULT)
15802 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
15803 if (strcmp (mips_cpu_info_table[i].name, MIPS_CPU_STRING_DEFAULT) == 0)
15804 return mips_cpu_info_table + i;
15805 gcc_unreachable ();
15806 #elif defined (MIPS_ISA_DEFAULT)
15807 return mips_cpu_info_from_isa (MIPS_ISA_DEFAULT);
15809 /* 'from-abi' makes a good default: you get whatever the ABI
15811 return mips_cpu_info_from_opt (MIPS_ARCH_OPTION_FROM_ABI);
15815 /* Set up globals to generate code for the ISA or processor
15816 described by INFO. */
15819 mips_set_architecture (const struct mips_cpu_info *info)
15823 mips_arch_info = info;
15824 mips_arch = info->cpu;
15825 mips_isa = info->isa;
15829 /* Likewise for tuning. */
15832 mips_set_tune (const struct mips_cpu_info *info)
15836 mips_tune_info = info;
15837 mips_tune = info->cpu;
15841 /* Implement TARGET_OPTION_OVERRIDE. */
15844 mips_option_override (void)
15846 int i, start, regno, mode;
15848 if (global_options_set.x_mips_isa_option)
15849 mips_isa_option_info = &mips_cpu_info_table[mips_isa_option];
15851 /* Process flags as though we were generating non-MIPS16 code. */
15852 mips_base_mips16 = TARGET_MIPS16;
15853 target_flags &= ~MASK_MIPS16;
15855 #ifdef SUBTARGET_OVERRIDE_OPTIONS
15856 SUBTARGET_OVERRIDE_OPTIONS;
15859 /* -mno-float overrides -mhard-float and -msoft-float. */
15860 if (TARGET_NO_FLOAT)
15862 target_flags |= MASK_SOFT_FLOAT_ABI;
15863 target_flags_explicit |= MASK_SOFT_FLOAT_ABI;
15866 if (TARGET_FLIP_MIPS16)
15867 TARGET_INTERLINK_MIPS16 = 1;
15869 /* Set the small data limit. */
15870 mips_small_data_threshold = (global_options_set.x_g_switch_value
15872 : MIPS_DEFAULT_GVALUE);
15874 /* The following code determines the architecture and register size.
15875 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
15876 The GAS and GCC code should be kept in sync as much as possible. */
15878 if (global_options_set.x_mips_arch_option)
15879 mips_set_architecture (mips_cpu_info_from_opt (mips_arch_option));
15881 if (mips_isa_option_info != 0)
15883 if (mips_arch_info == 0)
15884 mips_set_architecture (mips_isa_option_info);
15885 else if (mips_arch_info->isa != mips_isa_option_info->isa)
15886 error ("%<-%s%> conflicts with the other architecture options, "
15887 "which specify a %s processor",
15888 mips_isa_option_info->name,
15889 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
15892 if (mips_arch_info == 0)
15893 mips_set_architecture (mips_default_arch ());
15895 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
15896 error ("%<-march=%s%> is not compatible with the selected ABI",
15897 mips_arch_info->name);
15899 /* Optimize for mips_arch, unless -mtune selects a different processor. */
15900 if (global_options_set.x_mips_tune_option)
15901 mips_set_tune (mips_cpu_info_from_opt (mips_tune_option));
15903 if (mips_tune_info == 0)
15904 mips_set_tune (mips_arch_info);
15906 if ((target_flags_explicit & MASK_64BIT) != 0)
15908 /* The user specified the size of the integer registers. Make sure
15909 it agrees with the ABI and ISA. */
15910 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
15911 error ("%<-mgp64%> used with a 32-bit processor");
15912 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
15913 error ("%<-mgp32%> used with a 64-bit ABI");
15914 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
15915 error ("%<-mgp64%> used with a 32-bit ABI");
15919 /* Infer the integer register size from the ABI and processor.
15920 Restrict ourselves to 32-bit registers if that's all the
15921 processor has, or if the ABI cannot handle 64-bit registers. */
15922 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
15923 target_flags &= ~MASK_64BIT;
15925 target_flags |= MASK_64BIT;
15928 if ((target_flags_explicit & MASK_FLOAT64) != 0)
15930 if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
15931 error ("unsupported combination: %s", "-mfp64 -msingle-float");
15932 else if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
15933 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
15934 else if (!TARGET_64BIT && TARGET_FLOAT64)
15936 if (!ISA_HAS_MXHC1)
15937 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
15938 " the target supports the mfhc1 and mthc1 instructions");
15939 else if (mips_abi != ABI_32)
15940 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
15946 /* -msingle-float selects 32-bit float registers. Otherwise the
15947 float registers should be the same size as the integer ones. */
15948 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
15949 target_flags |= MASK_FLOAT64;
15951 target_flags &= ~MASK_FLOAT64;
15954 /* End of code shared with GAS. */
15956 /* If a -mlong* option was given, check that it matches the ABI,
15957 otherwise infer the -mlong* setting from the other options. */
15958 if ((target_flags_explicit & MASK_LONG64) != 0)
15962 if (mips_abi == ABI_N32)
15963 error ("%qs is incompatible with %qs", "-mabi=n32", "-mlong64");
15964 else if (mips_abi == ABI_32)
15965 error ("%qs is incompatible with %qs", "-mabi=32", "-mlong64");
15966 else if (mips_abi == ABI_O64 && TARGET_ABICALLS)
15967 /* We have traditionally allowed non-abicalls code to use
15968 an LP64 form of o64. However, it would take a bit more
15969 effort to support the combination of 32-bit GOT entries
15970 and 64-bit pointers, so we treat the abicalls case as
15972 error ("the combination of %qs and %qs is incompatible with %qs",
15973 "-mabi=o64", "-mabicalls", "-mlong64");
15977 if (mips_abi == ABI_64)
15978 error ("%qs is incompatible with %qs", "-mabi=64", "-mlong32");
15983 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
15984 target_flags |= MASK_LONG64;
15986 target_flags &= ~MASK_LONG64;
15989 if (!TARGET_OLDABI)
15990 flag_pcc_struct_return = 0;
15992 /* Decide which rtx_costs structure to use. */
15994 mips_cost = &mips_rtx_cost_optimize_size;
15996 mips_cost = &mips_rtx_cost_data[mips_tune];
15998 /* If the user hasn't specified a branch cost, use the processor's
16000 if (mips_branch_cost == 0)
16001 mips_branch_cost = mips_cost->branch_cost;
16003 /* If neither -mbranch-likely nor -mno-branch-likely was given
16004 on the command line, set MASK_BRANCHLIKELY based on the target
16005 architecture and tuning flags. Annulled delay slots are a
16006 size win, so we only consider the processor-specific tuning
16007 for !optimize_size. */
16008 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
16010 if (ISA_HAS_BRANCHLIKELY
16012 || (mips_tune_info->tune_flags & PTF_AVOID_BRANCHLIKELY) == 0))
16013 target_flags |= MASK_BRANCHLIKELY;
16015 target_flags &= ~MASK_BRANCHLIKELY;
16017 else if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
16018 warning (0, "the %qs architecture does not support branch-likely"
16019 " instructions", mips_arch_info->name);
16021 /* The effect of -mabicalls isn't defined for the EABI. */
16022 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
16024 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
16025 target_flags &= ~MASK_ABICALLS;
16028 if (TARGET_ABICALLS_PIC2)
16029 /* We need to set flag_pic for executables as well as DSOs
16030 because we may reference symbols that are not defined in
16031 the final executable. (MIPS does not use things like
16032 copy relocs, for example.)
16034 There is a body of code that uses __PIC__ to distinguish
16035 between -mabicalls and -mno-abicalls code. The non-__PIC__
16036 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
16037 long as any indirect jumps use $25. */
16040 /* -mvr4130-align is a "speed over size" optimization: it usually produces
16041 faster code, but at the expense of more nops. Enable it at -O3 and
16043 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
16044 target_flags |= MASK_VR4130_ALIGN;
16046 /* Prefer a call to memcpy over inline code when optimizing for size,
16047 though see MOVE_RATIO in mips.h. */
16048 if (optimize_size && (target_flags_explicit & MASK_MEMCPY) == 0)
16049 target_flags |= MASK_MEMCPY;
16051 /* If we have a nonzero small-data limit, check that the -mgpopt
16052 setting is consistent with the other target flags. */
16053 if (mips_small_data_threshold > 0)
16057 if (!TARGET_EXPLICIT_RELOCS)
16058 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
16060 TARGET_LOCAL_SDATA = false;
16061 TARGET_EXTERN_SDATA = false;
16065 if (TARGET_VXWORKS_RTP)
16066 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
16068 if (TARGET_ABICALLS)
16069 warning (0, "cannot use small-data accesses for %qs",
16074 /* Make sure that the user didn't turn off paired single support when
16075 MIPS-3D support is requested. */
16077 && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
16078 && !TARGET_PAIRED_SINGLE_FLOAT)
16079 error ("%<-mips3d%> requires %<-mpaired-single%>");
16081 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
16083 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
16085 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
16086 and TARGET_HARD_FLOAT_ABI are both true. */
16087 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT_ABI))
16088 error ("%qs must be used with %qs",
16089 TARGET_MIPS3D ? "-mips3d" : "-mpaired-single",
16090 TARGET_HARD_FLOAT_ABI ? "-mfp64" : "-mhard-float");
16092 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
16094 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_HAS_PAIRED_SINGLE)
16095 warning (0, "the %qs architecture does not support paired-single"
16096 " instructions", mips_arch_info->name);
16098 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
16099 && !TARGET_CACHE_BUILTIN)
16101 error ("%qs requires a target that provides the %qs instruction",
16102 "-mr10k-cache-barrier", "cache");
16103 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE;
16106 /* If TARGET_DSPR2, enable MASK_DSP. */
16108 target_flags |= MASK_DSP;
16110 /* .eh_frame addresses should be the same width as a C pointer.
16111 Most MIPS ABIs support only one pointer size, so the assembler
16112 will usually know exactly how big an .eh_frame address is.
16114 Unfortunately, this is not true of the 64-bit EABI. The ABI was
16115 originally defined to use 64-bit pointers (i.e. it is LP64), and
16116 this is still the default mode. However, we also support an n32-like
16117 ILP32 mode, which is selected by -mlong32. The problem is that the
16118 assembler has traditionally not had an -mlong option, so it has
16119 traditionally not known whether we're using the ILP32 or LP64 form.
16121 As it happens, gas versions up to and including 2.19 use _32-bit_
16122 addresses for EABI64 .cfi_* directives. This is wrong for the
16123 default LP64 mode, so we can't use the directives by default.
16124 Moreover, since gas's current behavior is at odds with gcc's
16125 default behavior, it seems unwise to rely on future versions
16126 of gas behaving the same way. We therefore avoid using .cfi
16127 directives for -mlong32 as well. */
16128 if (mips_abi == ABI_EABI && TARGET_64BIT)
16129 flag_dwarf2_cfi_asm = 0;
16131 /* .cfi_* directives generate a read-only section, so fall back on
16132 manual .eh_frame creation if we need the section to be writable. */
16133 if (TARGET_WRITABLE_EH_FRAME)
16134 flag_dwarf2_cfi_asm = 0;
16136 mips_init_print_operand_punct ();
16138 /* Set up array to map GCC register number to debug register number.
16139 Ignore the special purpose register numbers. */
16141 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
16143 mips_dbx_regno[i] = INVALID_REGNUM;
16144 if (GP_REG_P (i) || FP_REG_P (i) || ALL_COP_REG_P (i))
16145 mips_dwarf_regno[i] = i;
16147 mips_dwarf_regno[i] = INVALID_REGNUM;
16150 start = GP_DBX_FIRST - GP_REG_FIRST;
16151 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
16152 mips_dbx_regno[i] = i + start;
16154 start = FP_DBX_FIRST - FP_REG_FIRST;
16155 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
16156 mips_dbx_regno[i] = i + start;
16158 /* Accumulator debug registers use big-endian ordering. */
16159 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
16160 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
16161 mips_dwarf_regno[HI_REGNUM] = MD_REG_FIRST + 0;
16162 mips_dwarf_regno[LO_REGNUM] = MD_REG_FIRST + 1;
16163 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
16165 mips_dwarf_regno[i + TARGET_LITTLE_ENDIAN] = i;
16166 mips_dwarf_regno[i + TARGET_BIG_ENDIAN] = i + 1;
16169 /* Set up mips_hard_regno_mode_ok. */
16170 for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
16171 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
16172 mips_hard_regno_mode_ok[mode][regno]
16173 = mips_hard_regno_mode_ok_p (regno, (enum machine_mode) mode);
16175 /* Function to allocate machine-dependent function status. */
16176 init_machine_status = &mips_init_machine_status;
16178 /* Default to working around R4000 errata only if the processor
16179 was selected explicitly. */
16180 if ((target_flags_explicit & MASK_FIX_R4000) == 0
16181 && strcmp (mips_arch_info->name, "r4000") == 0)
16182 target_flags |= MASK_FIX_R4000;
16184 /* Default to working around R4400 errata only if the processor
16185 was selected explicitly. */
16186 if ((target_flags_explicit & MASK_FIX_R4400) == 0
16187 && strcmp (mips_arch_info->name, "r4400") == 0)
16188 target_flags |= MASK_FIX_R4400;
16190 /* Default to working around R10000 errata only if the processor
16191 was selected explicitly. */
16192 if ((target_flags_explicit & MASK_FIX_R10000) == 0
16193 && strcmp (mips_arch_info->name, "r10000") == 0)
16194 target_flags |= MASK_FIX_R10000;
16196 /* Make sure that branch-likely instructions available when using
16197 -mfix-r10000. The instructions are not available if either:
16199 1. -mno-branch-likely was passed.
16200 2. The selected ISA does not support branch-likely and
16201 the command line does not include -mbranch-likely. */
16202 if (TARGET_FIX_R10000
16203 && ((target_flags_explicit & MASK_BRANCHLIKELY) == 0
16204 ? !ISA_HAS_BRANCHLIKELY
16205 : !TARGET_BRANCHLIKELY))
16206 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
16208 if (TARGET_SYNCI && !ISA_HAS_SYNCI)
16210 warning (0, "the %qs architecture does not support the synci "
16211 "instruction", mips_arch_info->name);
16212 target_flags &= ~MASK_SYNCI;
16215 /* Only optimize PIC indirect calls if they are actually required. */
16216 if (!TARGET_USE_GOT || !TARGET_EXPLICIT_RELOCS)
16217 target_flags &= ~MASK_RELAX_PIC_CALLS;
16219 /* Save base state of options. */
16220 mips_base_target_flags = target_flags;
16221 mips_base_schedule_insns = flag_schedule_insns;
16222 mips_base_reorder_blocks_and_partition = flag_reorder_blocks_and_partition;
16223 mips_base_move_loop_invariants = flag_move_loop_invariants;
16224 mips_base_align_loops = align_loops;
16225 mips_base_align_jumps = align_jumps;
16226 mips_base_align_functions = align_functions;
16228 /* Now select the ISA mode.
16230 Do all CPP-sensitive stuff in non-MIPS16 mode; we'll switch to
16231 MIPS16 mode afterwards if need be. */
16232 mips_set_mips16_mode (false);
16235 /* Swap the register information for registers I and I + 1, which
16236 currently have the wrong endianness. Note that the registers'
16237 fixedness and call-clobberedness might have been set on the
16241 mips_swap_registers (unsigned int i)
16246 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
16247 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
16249 SWAP_INT (fixed_regs[i], fixed_regs[i + 1]);
16250 SWAP_INT (call_used_regs[i], call_used_regs[i + 1]);
16251 SWAP_INT (call_really_used_regs[i], call_really_used_regs[i + 1]);
16252 SWAP_STRING (reg_names[i], reg_names[i + 1]);
16258 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
16261 mips_conditional_register_usage (void)
16266 /* These DSP control register fields are global. */
16267 global_regs[CCDSP_PO_REGNUM] = 1;
16268 global_regs[CCDSP_SC_REGNUM] = 1;
16271 AND_COMPL_HARD_REG_SET (accessible_reg_set,
16272 reg_class_contents[(int) DSP_ACC_REGS]);
16274 if (!TARGET_HARD_FLOAT)
16276 AND_COMPL_HARD_REG_SET (accessible_reg_set,
16277 reg_class_contents[(int) FP_REGS]);
16278 AND_COMPL_HARD_REG_SET (accessible_reg_set,
16279 reg_class_contents[(int) ST_REGS]);
16281 else if (!ISA_HAS_8CC)
16283 /* We only have a single condition-code register. We implement
16284 this by fixing all the condition-code registers and generating
16285 RTL that refers directly to ST_REG_FIRST. */
16286 AND_COMPL_HARD_REG_SET (accessible_reg_set,
16287 reg_class_contents[(int) ST_REGS]);
16288 SET_HARD_REG_BIT (accessible_reg_set, FPSW_REGNUM);
16289 fixed_regs[FPSW_REGNUM] = call_used_regs[FPSW_REGNUM] = 1;
16293 /* In MIPS16 mode, we permit the $t temporary registers to be used
16294 for reload. We prohibit the unused $s registers, since they
16295 are call-saved, and saving them via a MIPS16 register would
16296 probably waste more time than just reloading the value. */
16297 fixed_regs[18] = call_used_regs[18] = 1;
16298 fixed_regs[19] = call_used_regs[19] = 1;
16299 fixed_regs[20] = call_used_regs[20] = 1;
16300 fixed_regs[21] = call_used_regs[21] = 1;
16301 fixed_regs[22] = call_used_regs[22] = 1;
16302 fixed_regs[23] = call_used_regs[23] = 1;
16303 fixed_regs[26] = call_used_regs[26] = 1;
16304 fixed_regs[27] = call_used_regs[27] = 1;
16305 fixed_regs[30] = call_used_regs[30] = 1;
16307 /* Do not allow HI and LO to be treated as register operands.
16308 There are no MTHI or MTLO instructions (or any real need
16309 for them) and one-way registers cannot easily be reloaded. */
16310 AND_COMPL_HARD_REG_SET (operand_reg_set,
16311 reg_class_contents[(int) MD_REGS]);
16313 /* $f20-$f23 are call-clobbered for n64. */
16314 if (mips_abi == ABI_64)
16317 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
16318 call_really_used_regs[regno] = call_used_regs[regno] = 1;
16320 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
16322 if (mips_abi == ABI_N32)
16325 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
16326 call_really_used_regs[regno] = call_used_regs[regno] = 1;
16328 /* Make sure that double-register accumulator values are correctly
16329 ordered for the current endianness. */
16330 if (TARGET_LITTLE_ENDIAN)
16332 unsigned int regno;
16334 mips_swap_registers (MD_REG_FIRST);
16335 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno += 2)
16336 mips_swap_registers (regno);
16340 /* When generating MIPS16 code, we want to allocate $24 (T_REG) before
16341 other registers for instructions for which it is possible. This
16342 encourages the compiler to use CMP in cases where an XOR would
16343 require some register shuffling. */
16346 mips_order_regs_for_local_alloc (void)
16350 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
16351 reg_alloc_order[i] = i;
16355 /* It really doesn't matter where we put register 0, since it is
16356 a fixed register anyhow. */
16357 reg_alloc_order[0] = 24;
16358 reg_alloc_order[24] = 0;
16362 /* Implement EH_USES. */
16365 mips_eh_uses (unsigned int regno)
16367 if (reload_completed && !TARGET_ABSOLUTE_JUMPS)
16369 /* We need to force certain registers to be live in order to handle
16370 PIC long branches correctly. See mips_must_initialize_gp_p for
16372 if (mips_cfun_has_cprestore_slot_p ())
16374 if (regno == CPRESTORE_SLOT_REGNUM)
16379 if (cfun->machine->global_pointer == regno)
16387 /* Implement EPILOGUE_USES. */
16390 mips_epilogue_uses (unsigned int regno)
16392 /* Say that the epilogue uses the return address register. Note that
16393 in the case of sibcalls, the values "used by the epilogue" are
16394 considered live at the start of the called function. */
16395 if (regno == RETURN_ADDR_REGNUM)
16398 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
16399 See the comment above load_call<mode> for details. */
16400 if (TARGET_USE_GOT && (regno) == GOT_VERSION_REGNUM)
16403 /* An interrupt handler must preserve some registers that are
16404 ordinarily call-clobbered. */
16405 if (cfun->machine->interrupt_handler_p
16406 && mips_interrupt_extra_call_saved_reg_p (regno))
16412 /* A for_each_rtx callback. Stop the search if *X is an AT register. */
16415 mips_at_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
16417 return REG_P (*x) && REGNO (*x) == AT_REGNUM;
16420 /* Return true if INSN needs to be wrapped in ".set noat".
16421 INSN has NOPERANDS operands, stored in OPVEC. */
16424 mips_need_noat_wrapper_p (rtx insn, rtx *opvec, int noperands)
16428 if (recog_memoized (insn) >= 0)
16429 for (i = 0; i < noperands; i++)
16430 if (for_each_rtx (&opvec[i], mips_at_reg_p, NULL))
16435 /* Implement FINAL_PRESCAN_INSN. */
16438 mips_final_prescan_insn (rtx insn, rtx *opvec, int noperands)
16440 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
16441 mips_push_asm_switch (&mips_noat);
16444 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */
16447 mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED, rtx insn,
16448 rtx *opvec, int noperands)
16450 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
16451 mips_pop_asm_switch (&mips_noat);
16454 /* Return the function that is used to expand the <u>mulsidi3 pattern.
16455 EXT_CODE is the code of the extension used. Return NULL if widening
16456 multiplication shouldn't be used. */
16459 mips_mulsidi3_gen_fn (enum rtx_code ext_code)
16463 signed_p = ext_code == SIGN_EXTEND;
16466 /* Don't use widening multiplication with MULT when we have DMUL. Even
16467 with the extension of its input operands DMUL is faster. Note that
16468 the extension is not needed for signed multiplication. In order to
16469 ensure that we always remove the redundant sign-extension in this
16470 case we still expand mulsidi3 for DMUL. */
16472 return signed_p ? gen_mulsidi3_64bit_dmul : NULL;
16475 ? gen_mulsidi3_64bit_mips16
16476 : gen_umulsidi3_64bit_mips16);
16477 if (TARGET_FIX_R4000)
16479 return signed_p ? gen_mulsidi3_64bit : gen_umulsidi3_64bit;
16485 ? gen_mulsidi3_32bit_mips16
16486 : gen_umulsidi3_32bit_mips16);
16487 if (TARGET_FIX_R4000 && !ISA_HAS_DSP)
16488 return signed_p ? gen_mulsidi3_32bit_r4000 : gen_umulsidi3_32bit_r4000;
16489 return signed_p ? gen_mulsidi3_32bit : gen_umulsidi3_32bit;
16493 /* Return the size in bytes of the trampoline code, padded to
16494 TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target
16495 function address immediately follow. */
16498 mips_trampoline_code_size (void)
16500 if (TARGET_USE_PIC_FN_ADDR_REG)
16502 else if (ptr_mode == DImode)
16504 else if (ISA_HAS_LOAD_DELAY)
16510 /* Implement TARGET_TRAMPOLINE_INIT. */
16513 mips_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
16515 rtx addr, end_addr, high, low, opcode, mem;
16518 HOST_WIDE_INT end_addr_offset, static_chain_offset, target_function_offset;
16520 /* Work out the offsets of the pointers from the start of the
16521 trampoline code. */
16522 end_addr_offset = mips_trampoline_code_size ();
16523 static_chain_offset = end_addr_offset;
16524 target_function_offset = static_chain_offset + GET_MODE_SIZE (ptr_mode);
16526 /* Get pointers to the beginning and end of the code block. */
16527 addr = force_reg (Pmode, XEXP (m_tramp, 0));
16528 end_addr = mips_force_binary (Pmode, PLUS, addr, GEN_INT (end_addr_offset));
16530 #define OP(X) gen_int_mode (X, SImode)
16532 /* Build up the code in TRAMPOLINE. */
16534 if (TARGET_USE_PIC_FN_ADDR_REG)
16536 /* $25 contains the address of the trampoline. Emit code of the form:
16538 l[wd] $1, target_function_offset($25)
16539 l[wd] $static_chain, static_chain_offset($25)
16542 trampoline[i++] = OP (MIPS_LOAD_PTR (AT_REGNUM,
16543 target_function_offset,
16544 PIC_FUNCTION_ADDR_REGNUM));
16545 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
16546 static_chain_offset,
16547 PIC_FUNCTION_ADDR_REGNUM));
16548 trampoline[i++] = OP (MIPS_JR (AT_REGNUM));
16549 trampoline[i++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM, AT_REGNUM));
16551 else if (ptr_mode == DImode)
16553 /* It's too cumbersome to create the full 64-bit address, so let's
16559 1: l[wd] $25, target_function_offset - 12($31)
16560 l[wd] $static_chain, static_chain_offset - 12($31)
16564 where 12 is the offset of "1:" from the start of the code block. */
16565 trampoline[i++] = OP (MIPS_MOVE (AT_REGNUM, RETURN_ADDR_REGNUM));
16566 trampoline[i++] = OP (MIPS_BAL (1));
16567 trampoline[i++] = OP (MIPS_NOP);
16568 trampoline[i++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
16569 target_function_offset - 12,
16570 RETURN_ADDR_REGNUM));
16571 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
16572 static_chain_offset - 12,
16573 RETURN_ADDR_REGNUM));
16574 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
16575 trampoline[i++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM, AT_REGNUM));
16579 /* If the target has load delays, emit:
16581 lui $1, %hi(end_addr)
16582 lw $25, %lo(end_addr + ...)($1)
16583 lw $static_chain, %lo(end_addr + ...)($1)
16589 lui $1, %hi(end_addr)
16590 lw $25, %lo(end_addr + ...)($1)
16592 lw $static_chain, %lo(end_addr + ...)($1). */
16594 /* Split END_ADDR into %hi and %lo values. Trampolines are aligned
16595 to 64 bits, so the %lo value will have the bottom 3 bits clear. */
16596 high = expand_simple_binop (SImode, PLUS, end_addr, GEN_INT (0x8000),
16597 NULL, false, OPTAB_WIDEN);
16598 high = expand_simple_binop (SImode, LSHIFTRT, high, GEN_INT (16),
16599 NULL, false, OPTAB_WIDEN);
16600 low = convert_to_mode (SImode, gen_lowpart (HImode, end_addr), true);
16602 /* Emit the LUI. */
16603 opcode = OP (MIPS_LUI (AT_REGNUM, 0));
16604 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, high,
16605 NULL, false, OPTAB_WIDEN);
16607 /* Emit the load of the target function. */
16608 opcode = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
16609 target_function_offset - end_addr_offset,
16611 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
16612 NULL, false, OPTAB_WIDEN);
16614 /* Emit the JR here, if we can. */
16615 if (!ISA_HAS_LOAD_DELAY)
16616 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
16618 /* Emit the load of the static chain register. */
16619 opcode = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
16620 static_chain_offset - end_addr_offset,
16622 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
16623 NULL, false, OPTAB_WIDEN);
16625 /* Emit the JR, if we couldn't above. */
16626 if (ISA_HAS_LOAD_DELAY)
16628 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
16629 trampoline[i++] = OP (MIPS_NOP);
16635 /* Copy the trampoline code. Leave any padding uninitialized. */
16636 for (j = 0; j < i; j++)
16638 mem = adjust_address (m_tramp, SImode, j * GET_MODE_SIZE (SImode));
16639 mips_emit_move (mem, trampoline[j]);
16642 /* Set up the static chain pointer field. */
16643 mem = adjust_address (m_tramp, ptr_mode, static_chain_offset);
16644 mips_emit_move (mem, chain_value);
16646 /* Set up the target function field. */
16647 mem = adjust_address (m_tramp, ptr_mode, target_function_offset);
16648 mips_emit_move (mem, XEXP (DECL_RTL (fndecl), 0));
16650 /* Flush the code part of the trampoline. */
16651 emit_insn (gen_add3_insn (end_addr, addr, GEN_INT (TRAMPOLINE_SIZE)));
16652 emit_insn (gen_clear_cache (addr, end_addr));
16655 /* Implement FUNCTION_PROFILER. */
16657 void mips_function_profiler (FILE *file)
16660 sorry ("mips16 function profiling");
16661 if (TARGET_LONG_CALLS)
16663 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */
16664 if (Pmode == DImode)
16665 fprintf (file, "\tdla\t%s,_mcount\n", reg_names[3]);
16667 fprintf (file, "\tla\t%s,_mcount\n", reg_names[3]);
16669 mips_push_asm_switch (&mips_noat);
16670 fprintf (file, "\tmove\t%s,%s\t\t# save current return address\n",
16671 reg_names[AT_REGNUM], reg_names[RETURN_ADDR_REGNUM]);
16672 /* _mcount treats $2 as the static chain register. */
16673 if (cfun->static_chain_decl != NULL)
16674 fprintf (file, "\tmove\t%s,%s\n", reg_names[2],
16675 reg_names[STATIC_CHAIN_REGNUM]);
16676 if (TARGET_MCOUNT_RA_ADDRESS)
16678 /* If TARGET_MCOUNT_RA_ADDRESS load $12 with the address of the
16679 ra save location. */
16680 if (cfun->machine->frame.ra_fp_offset == 0)
16681 /* ra not saved, pass zero. */
16682 fprintf (file, "\tmove\t%s,%s\n", reg_names[12], reg_names[0]);
16684 fprintf (file, "\t%s\t%s," HOST_WIDE_INT_PRINT_DEC "(%s)\n",
16685 Pmode == DImode ? "dla" : "la", reg_names[12],
16686 cfun->machine->frame.ra_fp_offset,
16687 reg_names[STACK_POINTER_REGNUM]);
16689 if (!TARGET_NEWABI)
16691 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n",
16692 TARGET_64BIT ? "dsubu" : "subu",
16693 reg_names[STACK_POINTER_REGNUM],
16694 reg_names[STACK_POINTER_REGNUM],
16695 Pmode == DImode ? 16 : 8);
16697 if (TARGET_LONG_CALLS)
16698 fprintf (file, "\tjalr\t%s\n", reg_names[3]);
16700 fprintf (file, "\tjal\t_mcount\n");
16701 mips_pop_asm_switch (&mips_noat);
16702 /* _mcount treats $2 as the static chain register. */
16703 if (cfun->static_chain_decl != NULL)
16704 fprintf (file, "\tmove\t%s,%s\n", reg_names[STATIC_CHAIN_REGNUM],
16708 /* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default
16709 behaviour of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even
16710 when TARGET_LOONGSON_VECTORS is true. */
16712 static unsigned HOST_WIDE_INT
16713 mips_shift_truncation_mask (enum machine_mode mode)
16715 if (TARGET_LOONGSON_VECTORS && VECTOR_MODE_P (mode))
16718 return GET_MODE_BITSIZE (mode) - 1;
16721 /* Implement TARGET_PREPARE_PCH_SAVE. */
16724 mips_prepare_pch_save (void)
16726 /* We are called in a context where the current MIPS16 vs. non-MIPS16
16727 setting should be irrelevant. The question then is: which setting
16728 makes most sense at load time?
16730 The PCH is loaded before the first token is read. We should never
16731 have switched into MIPS16 mode by that point, and thus should not
16732 have populated mips16_globals. Nor can we load the entire contents
16733 of mips16_globals from the PCH file, because mips16_globals contains
16734 a combination of GGC and non-GGC data.
16736 There is therefore no point in trying save the GGC part of
16737 mips16_globals to the PCH file, or to preserve MIPS16ness across
16738 the PCH save and load. The loading compiler would not have access
16739 to the non-GGC parts of mips16_globals (either from the PCH file,
16740 or from a copy that the loading compiler generated itself) and would
16741 have to call target_reinit anyway.
16743 It therefore seems best to switch back to non-MIPS16 mode at
16744 save time, and to ensure that mips16_globals remains null after
16746 mips_set_mips16_mode (false);
16747 mips16_globals = 0;
16750 /* Generate or test for an insn that supports a constant permutation. */
16752 #define MAX_VECT_LEN 8
16754 struct expand_vec_perm_d
16756 rtx target, op0, op1;
16757 unsigned char perm[MAX_VECT_LEN];
16758 enum machine_mode vmode;
16759 unsigned char nelt;
16764 /* Construct (set target (vec_select op0 (parallel perm))) and
16765 return true if that's a valid instruction in the active ISA. */
16768 mips_expand_vselect (rtx target, rtx op0,
16769 const unsigned char *perm, unsigned nelt)
16771 rtx rperm[MAX_VECT_LEN], x;
16774 for (i = 0; i < nelt; ++i)
16775 rperm[i] = GEN_INT (perm[i]);
16777 x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (nelt, rperm));
16778 x = gen_rtx_VEC_SELECT (GET_MODE (target), op0, x);
16779 x = gen_rtx_SET (VOIDmode, target, x);
16782 if (recog_memoized (x) < 0)
16790 /* Similar, but generate a vec_concat from op0 and op1 as well. */
16793 mips_expand_vselect_vconcat (rtx target, rtx op0, rtx op1,
16794 const unsigned char *perm, unsigned nelt)
16796 enum machine_mode v2mode;
16799 v2mode = GET_MODE_2XWIDER_MODE (GET_MODE (op0));
16800 x = gen_rtx_VEC_CONCAT (v2mode, op0, op1);
16801 return mips_expand_vselect (target, x, perm, nelt);
16804 /* Recognize patterns for even-odd extraction. */
16807 mips_expand_vpc_loongson_even_odd (struct expand_vec_perm_d *d)
16809 unsigned i, odd, nelt = d->nelt;
16810 rtx t0, t1, t2, t3;
16812 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
16814 /* Even-odd for V2SI/V2SFmode is matched by interleave directly. */
16821 for (i = 1; i < nelt; ++i)
16822 if (d->perm[i] != i * 2 + odd)
16828 /* We need 2*log2(N)-1 operations to achieve odd/even with interleave. */
16829 t0 = gen_reg_rtx (d->vmode);
16830 t1 = gen_reg_rtx (d->vmode);
16834 emit_insn (gen_loongson_punpckhhw (t0, d->op0, d->op1));
16835 emit_insn (gen_loongson_punpcklhw (t1, d->op0, d->op1));
16837 emit_insn (gen_loongson_punpckhhw (d->target, t1, t0));
16839 emit_insn (gen_loongson_punpcklhw (d->target, t1, t0));
16843 t2 = gen_reg_rtx (d->vmode);
16844 t3 = gen_reg_rtx (d->vmode);
16845 emit_insn (gen_loongson_punpckhbh (t0, d->op0, d->op1));
16846 emit_insn (gen_loongson_punpcklbh (t1, d->op0, d->op1));
16847 emit_insn (gen_loongson_punpckhbh (t2, t1, t0));
16848 emit_insn (gen_loongson_punpcklbh (t3, t1, t0));
16850 emit_insn (gen_loongson_punpckhbh (d->target, t3, t2));
16852 emit_insn (gen_loongson_punpcklbh (d->target, t3, t2));
16856 gcc_unreachable ();
16861 /* Recognize patterns for the Loongson PSHUFH instruction. */
16864 mips_expand_vpc_loongson_pshufh (struct expand_vec_perm_d *d)
16869 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
16871 if (d->vmode != V4HImode)
16876 /* Convert the selector into the packed 8-bit form for pshufh. */
16877 /* Recall that loongson is little-endian only. No big-endian
16878 adjustment required. */
16879 for (i = mask = 0; i < 4; i++)
16880 mask |= (d->perm[i] & 3) << (i * 2);
16881 rmask = force_reg (SImode, GEN_INT (mask));
16883 if (d->one_vector_p)
16884 emit_insn (gen_loongson_pshufh (d->target, d->op0, rmask));
16887 rtx t0, t1, x, merge, rmerge[4];
16889 t0 = gen_reg_rtx (V4HImode);
16890 t1 = gen_reg_rtx (V4HImode);
16891 emit_insn (gen_loongson_pshufh (t1, d->op1, rmask));
16892 emit_insn (gen_loongson_pshufh (t0, d->op0, rmask));
16894 for (i = 0; i < 4; ++i)
16895 rmerge[i] = (d->perm[i] & 4 ? constm1_rtx : const0_rtx);
16896 merge = gen_rtx_CONST_VECTOR (V4HImode, gen_rtvec_v (4, rmerge));
16897 merge = force_reg (V4HImode, merge);
16899 x = gen_rtx_AND (V4HImode, merge, t1);
16900 emit_insn (gen_rtx_SET (VOIDmode, t1, x));
16902 x = gen_rtx_NOT (V4HImode, merge);
16903 x = gen_rtx_AND (V4HImode, x, t0);
16904 emit_insn (gen_rtx_SET (VOIDmode, t0, x));
16906 x = gen_rtx_IOR (V4HImode, t0, t1);
16907 emit_insn (gen_rtx_SET (VOIDmode, d->target, x));
16913 /* Recognize broadcast patterns for the Loongson. */
16916 mips_expand_vpc_loongson_bcast (struct expand_vec_perm_d *d)
16921 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
16923 /* Note that we've already matched V2SI via punpck and V4HI via pshufh. */
16924 if (d->vmode != V8QImode)
16926 if (!d->one_vector_p)
16930 for (i = 1; i < 8; ++i)
16931 if (d->perm[i] != elt)
16937 /* With one interleave we put two of the desired element adjacent. */
16938 t0 = gen_reg_rtx (V8QImode);
16940 emit_insn (gen_loongson_punpcklbh (t0, d->op0, d->op0));
16942 emit_insn (gen_loongson_punpckhbh (t0, d->op0, d->op0));
16944 /* Shuffle that one HImode element into all locations. */
16947 t1 = gen_reg_rtx (V4HImode);
16948 emit_insn (gen_loongson_pshufh (t1, gen_lowpart (V4HImode, t0),
16949 force_reg (SImode, GEN_INT (elt))));
16951 emit_move_insn (d->target, gen_lowpart (V8QImode, t1));
16956 mips_expand_vec_perm_const_1 (struct expand_vec_perm_d *d)
16958 unsigned int i, nelt = d->nelt;
16959 unsigned char perm2[MAX_VECT_LEN];
16961 if (d->one_vector_p)
16963 /* Try interleave with alternating operands. */
16964 memcpy (perm2, d->perm, sizeof(perm2));
16965 for (i = 1; i < nelt; i += 2)
16967 if (mips_expand_vselect_vconcat (d->target, d->op0, d->op1, perm2, nelt))
16972 if (mips_expand_vselect_vconcat (d->target, d->op0, d->op1,
16976 /* Try again with swapped operands. */
16977 for (i = 0; i < nelt; ++i)
16978 perm2[i] = (d->perm[i] + nelt) & (2 * nelt - 1);
16979 if (mips_expand_vselect_vconcat (d->target, d->op1, d->op0, perm2, nelt))
16983 if (mips_expand_vpc_loongson_even_odd (d))
16985 if (mips_expand_vpc_loongson_pshufh (d))
16987 if (mips_expand_vpc_loongson_bcast (d))
16992 /* Expand a vec_perm_const pattern. */
16995 mips_expand_vec_perm_const (rtx operands[4])
16997 struct expand_vec_perm_d d;
16998 int i, nelt, which;
16999 unsigned char orig_perm[MAX_VECT_LEN];
17003 d.target = operands[0];
17004 d.op0 = operands[1];
17005 d.op1 = operands[2];
17008 d.vmode = GET_MODE (d.target);
17009 gcc_assert (VECTOR_MODE_P (d.vmode));
17010 d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
17011 d.testing_p = false;
17013 for (i = which = 0; i < nelt; ++i)
17015 rtx e = XVECEXP (sel, 0, i);
17016 int ei = INTVAL (e) & (2 * nelt - 1);
17017 which |= (ei < nelt ? 1 : 2);
17020 memcpy (d.perm, orig_perm, MAX_VECT_LEN);
17028 d.one_vector_p = false;
17029 if (!rtx_equal_p (d.op0, d.op1))
17034 for (i = 0; i < nelt; ++i)
17035 d.perm[i] &= nelt - 1;
17037 d.one_vector_p = true;
17042 d.one_vector_p = true;
17046 ok = mips_expand_vec_perm_const_1 (&d);
17048 /* If we were given a two-vector permutation which just happened to
17049 have both input vectors equal, we folded this into a one-vector
17050 permutation. There are several loongson patterns that are matched
17051 via direct vec_select+vec_concat expansion, but we do not have
17052 support in mips_expand_vec_perm_const_1 to guess the adjustment
17053 that should be made for a single operand. Just try again with
17054 the original permutation. */
17055 if (!ok && which == 3)
17057 d.op0 = operands[1];
17058 d.op1 = operands[2];
17059 d.one_vector_p = false;
17060 memcpy (d.perm, orig_perm, MAX_VECT_LEN);
17061 ok = mips_expand_vec_perm_const_1 (&d);
17067 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST_OK. */
17070 mips_vectorize_vec_perm_const_ok (enum machine_mode vmode,
17071 const unsigned char *sel)
17073 struct expand_vec_perm_d d;
17074 unsigned int i, nelt, which;
17078 d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
17079 d.testing_p = true;
17080 memcpy (d.perm, sel, nelt);
17082 /* Categorize the set of elements in the selector. */
17083 for (i = which = 0; i < nelt; ++i)
17085 unsigned char e = d.perm[i];
17086 gcc_assert (e < 2 * nelt);
17087 which |= (e < nelt ? 1 : 2);
17090 /* For all elements from second vector, fold the elements to first. */
17092 for (i = 0; i < nelt; ++i)
17095 /* Check whether the mask can be applied to the vector type. */
17096 d.one_vector_p = (which != 3);
17098 d.target = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 1);
17099 d.op1 = d.op0 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 2);
17100 if (!d.one_vector_p)
17101 d.op1 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 3);
17104 ret = mips_expand_vec_perm_const_1 (&d);
17110 /* Expand an integral vector unpack operation. */
17113 mips_expand_vec_unpack (rtx operands[2], bool unsigned_p, bool high_p)
17115 enum machine_mode imode = GET_MODE (operands[1]);
17116 rtx (*unpack) (rtx, rtx, rtx);
17117 rtx (*cmpgt) (rtx, rtx, rtx);
17118 rtx tmp, dest, zero;
17124 unpack = gen_loongson_punpckhbh;
17126 unpack = gen_loongson_punpcklbh;
17127 cmpgt = gen_loongson_pcmpgtb;
17131 unpack = gen_loongson_punpckhhw;
17133 unpack = gen_loongson_punpcklhw;
17134 cmpgt = gen_loongson_pcmpgth;
17137 gcc_unreachable ();
17140 zero = force_reg (imode, CONST0_RTX (imode));
17145 tmp = gen_reg_rtx (imode);
17146 emit_insn (cmpgt (tmp, zero, operands[1]));
17149 dest = gen_reg_rtx (imode);
17150 emit_insn (unpack (dest, operands[1], tmp));
17152 emit_move_insn (operands[0], gen_lowpart (GET_MODE (operands[0]), dest));
17155 /* A subroutine of mips_expand_vec_init, match constant vector elements. */
17158 mips_constant_elt_p (rtx x)
17160 return CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE;
17163 /* A subroutine of mips_expand_vec_init, expand via broadcast. */
17166 mips_expand_vi_broadcast (enum machine_mode vmode, rtx target, rtx elt)
17168 struct expand_vec_perm_d d;
17172 if (elt != const0_rtx)
17173 elt = force_reg (GET_MODE_INNER (vmode), elt);
17175 elt = gen_lowpart (DImode, elt);
17177 t1 = gen_reg_rtx (vmode);
17181 emit_insn (gen_loongson_vec_init1_v8qi (t1, elt));
17184 emit_insn (gen_loongson_vec_init1_v4hi (t1, elt));
17187 gcc_unreachable ();
17190 memset (&d, 0, sizeof (d));
17195 d.nelt = GET_MODE_NUNITS (vmode);
17196 d.one_vector_p = true;
17198 ok = mips_expand_vec_perm_const_1 (&d);
17202 /* A subroutine of mips_expand_vec_init, replacing all of the non-constant
17203 elements of VALS with zeros, copy the constant vector to TARGET. */
17206 mips_expand_vi_constant (enum machine_mode vmode, unsigned nelt,
17207 rtx target, rtx vals)
17209 rtvec vec = shallow_copy_rtvec (XVEC (vals, 0));
17212 for (i = 0; i < nelt; ++i)
17214 if (!mips_constant_elt_p (RTVEC_ELT (vec, i)))
17215 RTVEC_ELT (vec, i) = const0_rtx;
17218 emit_move_insn (target, gen_rtx_CONST_VECTOR (vmode, vec));
17222 /* A subroutine of mips_expand_vec_init, expand via pinsrh. */
17225 mips_expand_vi_loongson_one_pinsrh (rtx target, rtx vals, unsigned one_var)
17227 mips_expand_vi_constant (V4HImode, 4, target, vals);
17229 emit_insn (gen_vec_setv4hi (target, target, XVECEXP (vals, 0, one_var),
17230 GEN_INT (one_var)));
17233 /* A subroutine of mips_expand_vec_init, expand anything via memory. */
17236 mips_expand_vi_general (enum machine_mode vmode, enum machine_mode imode,
17237 unsigned nelt, unsigned nvar, rtx target, rtx vals)
17239 rtx mem = assign_stack_temp (vmode, GET_MODE_SIZE (vmode));
17240 unsigned int i, isize = GET_MODE_SIZE (imode);
17243 mips_expand_vi_constant (vmode, nelt, mem, vals);
17245 for (i = 0; i < nelt; ++i)
17247 rtx x = XVECEXP (vals, 0, i);
17248 if (!mips_constant_elt_p (x))
17249 emit_move_insn (adjust_address (mem, imode, i * isize), x);
17252 emit_move_insn (target, mem);
17255 /* Expand a vector initialization. */
17258 mips_expand_vector_init (rtx target, rtx vals)
17260 enum machine_mode vmode = GET_MODE (target);
17261 enum machine_mode imode = GET_MODE_INNER (vmode);
17262 unsigned i, nelt = GET_MODE_NUNITS (vmode);
17263 unsigned nvar = 0, one_var = -1u;
17264 bool all_same = true;
17267 for (i = 0; i < nelt; ++i)
17269 x = XVECEXP (vals, 0, i);
17270 if (!mips_constant_elt_p (x))
17271 nvar++, one_var = i;
17272 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
17276 /* Load constants from the pool, or whatever's handy. */
17279 emit_move_insn (target, gen_rtx_CONST_VECTOR (vmode, XVEC (vals, 0)));
17283 /* For two-part initialization, always use CONCAT. */
17286 rtx op0 = force_reg (imode, XVECEXP (vals, 0, 0));
17287 rtx op1 = force_reg (imode, XVECEXP (vals, 0, 1));
17288 x = gen_rtx_VEC_CONCAT (vmode, op0, op1);
17289 emit_insn (gen_rtx_SET (VOIDmode, target, x));
17293 /* Loongson is the only cpu with vectors with more elements. */
17294 gcc_assert (TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS);
17296 /* If all values are identical, broadcast the value. */
17299 mips_expand_vi_broadcast (vmode, target, XVECEXP (vals, 0, 0));
17303 /* If we've only got one non-variable V4HImode, use PINSRH. */
17304 if (nvar == 1 && vmode == V4HImode)
17306 mips_expand_vi_loongson_one_pinsrh (target, vals, one_var);
17310 mips_expand_vi_general (vmode, imode, nelt, nvar, target, vals);
17313 /* Expand a vector reduction. */
17316 mips_expand_vec_reduc (rtx target, rtx in, rtx (*gen)(rtx, rtx, rtx))
17318 enum machine_mode vmode = GET_MODE (in);
17319 unsigned char perm2[2];
17320 rtx last, next, fold, x;
17324 fold = gen_reg_rtx (vmode);
17328 /* Use PUL/PLU to produce { L, H } op { H, L }.
17329 By reversing the pair order, rather than a pure interleave high,
17330 we avoid erroneous exceptional conditions that we might otherwise
17331 produce from the computation of H op H. */
17334 ok = mips_expand_vselect_vconcat (fold, last, last, perm2, 2);
17339 /* Use interleave to produce { H, L } op { H, H }. */
17340 emit_insn (gen_loongson_punpckhwd (fold, last, last));
17344 /* Perform the first reduction with interleave,
17345 and subsequent reductions with shifts. */
17346 emit_insn (gen_loongson_punpckhwd_hi (fold, last, last));
17348 next = gen_reg_rtx (vmode);
17349 emit_insn (gen (next, last, fold));
17352 fold = gen_reg_rtx (vmode);
17353 x = force_reg (SImode, GEN_INT (16));
17354 emit_insn (gen_vec_shr_v4hi (fold, last, x));
17358 emit_insn (gen_loongson_punpckhwd_qi (fold, last, last));
17360 next = gen_reg_rtx (vmode);
17361 emit_insn (gen (next, last, fold));
17364 fold = gen_reg_rtx (vmode);
17365 x = force_reg (SImode, GEN_INT (16));
17366 emit_insn (gen_vec_shr_v8qi (fold, last, x));
17368 next = gen_reg_rtx (vmode);
17369 emit_insn (gen (next, last, fold));
17372 fold = gen_reg_rtx (vmode);
17373 x = force_reg (SImode, GEN_INT (8));
17374 emit_insn (gen_vec_shr_v8qi (fold, last, x));
17378 gcc_unreachable ();
17381 emit_insn (gen (target, last, fold));
17384 /* Expand a vector minimum/maximum. */
17387 mips_expand_vec_minmax (rtx target, rtx op0, rtx op1,
17388 rtx (*cmp) (rtx, rtx, rtx), bool min_p)
17390 enum machine_mode vmode = GET_MODE (target);
17393 tc = gen_reg_rtx (vmode);
17394 t0 = gen_reg_rtx (vmode);
17395 t1 = gen_reg_rtx (vmode);
17398 emit_insn (cmp (tc, op0, op1));
17400 x = gen_rtx_AND (vmode, tc, (min_p ? op1 : op0));
17401 emit_insn (gen_rtx_SET (VOIDmode, t0, x));
17403 x = gen_rtx_NOT (vmode, tc);
17404 x = gen_rtx_AND (vmode, x, (min_p ? op0 : op1));
17405 emit_insn (gen_rtx_SET (VOIDmode, t1, x));
17407 x = gen_rtx_IOR (vmode, t0, t1);
17408 emit_insn (gen_rtx_SET (VOIDmode, target, x));
17411 /* Initialize the GCC target structure. */
17412 #undef TARGET_ASM_ALIGNED_HI_OP
17413 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
17414 #undef TARGET_ASM_ALIGNED_SI_OP
17415 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
17416 #undef TARGET_ASM_ALIGNED_DI_OP
17417 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
17419 #undef TARGET_OPTION_OVERRIDE
17420 #define TARGET_OPTION_OVERRIDE mips_option_override
17422 #undef TARGET_LEGITIMIZE_ADDRESS
17423 #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
17425 #undef TARGET_ASM_FUNCTION_PROLOGUE
17426 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
17427 #undef TARGET_ASM_FUNCTION_EPILOGUE
17428 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
17429 #undef TARGET_ASM_SELECT_RTX_SECTION
17430 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
17431 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
17432 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
17434 #undef TARGET_SCHED_INIT
17435 #define TARGET_SCHED_INIT mips_sched_init
17436 #undef TARGET_SCHED_REORDER
17437 #define TARGET_SCHED_REORDER mips_sched_reorder
17438 #undef TARGET_SCHED_REORDER2
17439 #define TARGET_SCHED_REORDER2 mips_sched_reorder2
17440 #undef TARGET_SCHED_VARIABLE_ISSUE
17441 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
17442 #undef TARGET_SCHED_ADJUST_COST
17443 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
17444 #undef TARGET_SCHED_ISSUE_RATE
17445 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
17446 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
17447 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
17448 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
17449 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
17450 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
17451 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
17452 mips_multipass_dfa_lookahead
17453 #undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
17454 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
17455 mips_small_register_classes_for_mode_p
17457 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
17458 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
17460 #undef TARGET_INSERT_ATTRIBUTES
17461 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
17462 #undef TARGET_MERGE_DECL_ATTRIBUTES
17463 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
17464 #undef TARGET_SET_CURRENT_FUNCTION
17465 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
17467 #undef TARGET_VALID_POINTER_MODE
17468 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
17469 #undef TARGET_REGISTER_MOVE_COST
17470 #define TARGET_REGISTER_MOVE_COST mips_register_move_cost
17471 #undef TARGET_MEMORY_MOVE_COST
17472 #define TARGET_MEMORY_MOVE_COST mips_memory_move_cost
17473 #undef TARGET_RTX_COSTS
17474 #define TARGET_RTX_COSTS mips_rtx_costs
17475 #undef TARGET_ADDRESS_COST
17476 #define TARGET_ADDRESS_COST mips_address_cost
17478 #undef TARGET_IN_SMALL_DATA_P
17479 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
17481 #undef TARGET_MACHINE_DEPENDENT_REORG
17482 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
17484 #undef TARGET_PREFERRED_RELOAD_CLASS
17485 #define TARGET_PREFERRED_RELOAD_CLASS mips_preferred_reload_class
17487 #undef TARGET_ASM_FILE_START
17488 #define TARGET_ASM_FILE_START mips_file_start
17489 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
17490 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
17491 #undef TARGET_ASM_CODE_END
17492 #define TARGET_ASM_CODE_END mips_code_end
17494 #undef TARGET_INIT_LIBFUNCS
17495 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
17497 #undef TARGET_BUILD_BUILTIN_VA_LIST
17498 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
17499 #undef TARGET_EXPAND_BUILTIN_VA_START
17500 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
17501 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
17502 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
17504 #undef TARGET_PROMOTE_FUNCTION_MODE
17505 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
17506 #undef TARGET_PROMOTE_PROTOTYPES
17507 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
17509 #undef TARGET_FUNCTION_VALUE
17510 #define TARGET_FUNCTION_VALUE mips_function_value
17511 #undef TARGET_LIBCALL_VALUE
17512 #define TARGET_LIBCALL_VALUE mips_libcall_value
17513 #undef TARGET_FUNCTION_VALUE_REGNO_P
17514 #define TARGET_FUNCTION_VALUE_REGNO_P mips_function_value_regno_p
17515 #undef TARGET_RETURN_IN_MEMORY
17516 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
17517 #undef TARGET_RETURN_IN_MSB
17518 #define TARGET_RETURN_IN_MSB mips_return_in_msb
17520 #undef TARGET_ASM_OUTPUT_MI_THUNK
17521 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
17522 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
17523 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
17525 #undef TARGET_PRINT_OPERAND
17526 #define TARGET_PRINT_OPERAND mips_print_operand
17527 #undef TARGET_PRINT_OPERAND_ADDRESS
17528 #define TARGET_PRINT_OPERAND_ADDRESS mips_print_operand_address
17529 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
17530 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mips_print_operand_punct_valid_p
17532 #undef TARGET_SETUP_INCOMING_VARARGS
17533 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
17534 #undef TARGET_STRICT_ARGUMENT_NAMING
17535 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
17536 #undef TARGET_MUST_PASS_IN_STACK
17537 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
17538 #undef TARGET_PASS_BY_REFERENCE
17539 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
17540 #undef TARGET_CALLEE_COPIES
17541 #define TARGET_CALLEE_COPIES mips_callee_copies
17542 #undef TARGET_ARG_PARTIAL_BYTES
17543 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
17544 #undef TARGET_FUNCTION_ARG
17545 #define TARGET_FUNCTION_ARG mips_function_arg
17546 #undef TARGET_FUNCTION_ARG_ADVANCE
17547 #define TARGET_FUNCTION_ARG_ADVANCE mips_function_arg_advance
17548 #undef TARGET_FUNCTION_ARG_BOUNDARY
17549 #define TARGET_FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
17551 #undef TARGET_MODE_REP_EXTENDED
17552 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
17554 #undef TARGET_VECTOR_MODE_SUPPORTED_P
17555 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
17557 #undef TARGET_SCALAR_MODE_SUPPORTED_P
17558 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
17560 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
17561 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE mips_preferred_simd_mode
17563 #undef TARGET_INIT_BUILTINS
17564 #define TARGET_INIT_BUILTINS mips_init_builtins
17565 #undef TARGET_BUILTIN_DECL
17566 #define TARGET_BUILTIN_DECL mips_builtin_decl
17567 #undef TARGET_EXPAND_BUILTIN
17568 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
17570 #undef TARGET_HAVE_TLS
17571 #define TARGET_HAVE_TLS HAVE_AS_TLS
17573 #undef TARGET_CANNOT_FORCE_CONST_MEM
17574 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
17576 #undef TARGET_LEGITIMATE_CONSTANT_P
17577 #define TARGET_LEGITIMATE_CONSTANT_P mips_legitimate_constant_p
17579 #undef TARGET_ENCODE_SECTION_INFO
17580 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
17582 #undef TARGET_ATTRIBUTE_TABLE
17583 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
17584 /* All our function attributes are related to how out-of-line copies should
17585 be compiled or called. They don't in themselves prevent inlining. */
17586 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
17587 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
17589 #undef TARGET_EXTRA_LIVE_ON_ENTRY
17590 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
17592 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
17593 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
17594 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
17595 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
17597 #undef TARGET_COMP_TYPE_ATTRIBUTES
17598 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
17600 #ifdef HAVE_AS_DTPRELWORD
17601 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
17602 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
17604 #undef TARGET_DWARF_REGISTER_SPAN
17605 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
17607 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
17608 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
17610 #undef TARGET_LEGITIMATE_ADDRESS_P
17611 #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p
17613 #undef TARGET_FRAME_POINTER_REQUIRED
17614 #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required
17616 #undef TARGET_CAN_ELIMINATE
17617 #define TARGET_CAN_ELIMINATE mips_can_eliminate
17619 #undef TARGET_CONDITIONAL_REGISTER_USAGE
17620 #define TARGET_CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage
17622 #undef TARGET_TRAMPOLINE_INIT
17623 #define TARGET_TRAMPOLINE_INIT mips_trampoline_init
17625 #undef TARGET_ASM_OUTPUT_SOURCE_FILENAME
17626 #define TARGET_ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
17628 #undef TARGET_SHIFT_TRUNCATION_MASK
17629 #define TARGET_SHIFT_TRUNCATION_MASK mips_shift_truncation_mask
17631 #undef TARGET_PREPARE_PCH_SAVE
17632 #define TARGET_PREPARE_PCH_SAVE mips_prepare_pch_save
17634 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
17635 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK mips_vectorize_vec_perm_const_ok
17637 struct gcc_target targetm = TARGET_INITIALIZER;
17639 #include "gt-mips.h"