1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989-2013 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky, lich@inria.inria.fr.
4 Changes by Michael Meissner, meissner@osf.org.
5 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 Brendan Eich, brendan@microunity.com.
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
30 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
49 #include "target-def.h"
50 #include "common/common-target.h"
51 #include "langhooks.h"
52 #include "sched-int.h"
55 #include "diagnostic.h"
56 #include "target-globals.h"
59 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
60 #define UNSPEC_ADDRESS_P(X) \
61 (GET_CODE (X) == UNSPEC \
62 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
63 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
65 /* Extract the symbol or label from UNSPEC wrapper X. */
66 #define UNSPEC_ADDRESS(X) \
69 /* Extract the symbol type from UNSPEC wrapper X. */
70 #define UNSPEC_ADDRESS_TYPE(X) \
71 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
73 /* The maximum distance between the top of the stack frame and the
74 value $sp has when we save and restore registers.
76 The value for normal-mode code must be a SMALL_OPERAND and must
77 preserve the maximum stack alignment. We therefore use a value
78 of 0x7ff0 in this case.
80 microMIPS LWM and SWM support 12-bit offsets (from -0x800 to 0x7ff),
81 so we use a maximum of 0x7f0 for TARGET_MICROMIPS.
83 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
84 up to 0x7f8 bytes and can usually save or restore all the registers
85 that we need to save or restore. (Note that we can only use these
86 instructions for o32, for which the stack alignment is 8 bytes.)
88 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
89 RESTORE are not available. We can then use unextended instructions
90 to save and restore registers, and to allocate and deallocate the top
92 #define MIPS_MAX_FIRST_STACK_STEP \
93 (!TARGET_COMPRESSION ? 0x7ff0 \
94 : TARGET_MICROMIPS || GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
95 : TARGET_64BIT ? 0x100 : 0x400)
97 /* True if INSN is a mips.md pattern or asm statement. */
98 /* ??? This test exists through the compiler, perhaps it should be
100 #define USEFUL_INSN_P(INSN) \
101 (NONDEBUG_INSN_P (INSN) \
102 && GET_CODE (PATTERN (INSN)) != USE \
103 && GET_CODE (PATTERN (INSN)) != CLOBBER)
105 /* If INSN is a delayed branch sequence, return the first instruction
106 in the sequence, otherwise return INSN itself. */
107 #define SEQ_BEGIN(INSN) \
108 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
109 ? XVECEXP (PATTERN (INSN), 0, 0) \
112 /* Likewise for the last instruction in a delayed branch sequence. */
113 #define SEQ_END(INSN) \
114 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
115 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
118 /* Execute the following loop body with SUBINSN set to each instruction
119 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
120 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
121 for ((SUBINSN) = SEQ_BEGIN (INSN); \
122 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
123 (SUBINSN) = NEXT_INSN (SUBINSN))
125 /* True if bit BIT is set in VALUE. */
126 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
128 /* Return the opcode for a ptr_mode load of the form:
130 l[wd] DEST, OFFSET(BASE). */
131 #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \
132 (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \
137 /* Return the opcode to move register SRC into register DEST. */
138 #define MIPS_MOVE(DEST, SRC) \
139 ((TARGET_64BIT ? 0x2d : 0x21) \
143 /* Return the opcode for:
146 #define MIPS_LUI(DEST, VALUE) \
147 ((0xf << 26) | ((DEST) << 16) | (VALUE))
149 /* Return the opcode to jump to register DEST. */
150 #define MIPS_JR(DEST) \
151 (((DEST) << 21) | 0x8)
153 /* Return the opcode for:
155 bal . + (1 + OFFSET) * 4. */
156 #define MIPS_BAL(OFFSET) \
157 ((0x1 << 26) | (0x11 << 16) | (OFFSET))
159 /* Return the usual opcode for a nop. */
162 /* Classifies an address.
165 A natural register + offset address. The register satisfies
166 mips_valid_base_register_p and the offset is a const_arith_operand.
169 A LO_SUM rtx. The first operand is a valid base register and
170 the second operand is a symbolic address.
173 A signed 16-bit constant address.
176 A constant symbolic address. */
177 enum mips_address_type {
184 /* Macros to create an enumeration identifier for a function prototype. */
185 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
186 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
187 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
188 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
190 /* Classifies the prototype of a built-in function. */
191 enum mips_function_type {
192 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
193 #include "config/mips/mips-ftypes.def"
194 #undef DEF_MIPS_FTYPE
198 /* Specifies how a built-in function should be converted into rtl. */
199 enum mips_builtin_type {
200 /* The function corresponds directly to an .md pattern. The return
201 value is mapped to operand 0 and the arguments are mapped to
202 operands 1 and above. */
205 /* The function corresponds directly to an .md pattern. There is no return
206 value and the arguments are mapped to operands 0 and above. */
207 MIPS_BUILTIN_DIRECT_NO_TARGET,
209 /* The function corresponds to a comparison instruction followed by
210 a mips_cond_move_tf_ps pattern. The first two arguments are the
211 values to compare and the second two arguments are the vector
212 operands for the movt.ps or movf.ps instruction (in assembly order). */
216 /* The function corresponds to a V2SF comparison instruction. Operand 0
217 of this instruction is the result of the comparison, which has mode
218 CCV2 or CCV4. The function arguments are mapped to operands 1 and
219 above. The function's return value is an SImode boolean that is
220 true under the following conditions:
222 MIPS_BUILTIN_CMP_ANY: one of the registers is true
223 MIPS_BUILTIN_CMP_ALL: all of the registers are true
224 MIPS_BUILTIN_CMP_LOWER: the first register is true
225 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
226 MIPS_BUILTIN_CMP_ANY,
227 MIPS_BUILTIN_CMP_ALL,
228 MIPS_BUILTIN_CMP_UPPER,
229 MIPS_BUILTIN_CMP_LOWER,
231 /* As above, but the instruction only sets a single $fcc register. */
232 MIPS_BUILTIN_CMP_SINGLE,
234 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
235 MIPS_BUILTIN_BPOSGE32
238 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
239 #define MIPS_FP_CONDITIONS(MACRO) \
257 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
258 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
259 enum mips_fp_condition {
260 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
263 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
264 #define STRINGIFY(X) #X
265 static const char *const mips_fp_conditions[] = {
266 MIPS_FP_CONDITIONS (STRINGIFY)
269 /* Tuning information that is automatically derived from other sources
270 (such as the scheduler). */
272 /* The architecture and tuning settings that this structure describes. */
276 /* True if this structure describes MIPS16 settings. */
279 /* True if the structure has been initialized. */
282 /* True if "MULT $0, $0" is preferable to "MTLO $0; MTHI $0"
283 when optimizing for speed. */
284 bool fast_mult_zero_zero_p;
287 /* Information about a function's frame layout. */
288 struct GTY(()) mips_frame_info {
289 /* The size of the frame in bytes. */
290 HOST_WIDE_INT total_size;
292 /* The number of bytes allocated to variables. */
293 HOST_WIDE_INT var_size;
295 /* The number of bytes allocated to outgoing function arguments. */
296 HOST_WIDE_INT args_size;
298 /* The number of bytes allocated to the .cprestore slot, or 0 if there
300 HOST_WIDE_INT cprestore_size;
302 /* Bit X is set if the function saves or restores GPR X. */
305 /* Likewise FPR X. */
308 /* Likewise doubleword accumulator X ($acX). */
309 unsigned int acc_mask;
311 /* The number of GPRs, FPRs, doubleword accumulators and COP0
315 unsigned int num_acc;
316 unsigned int num_cop0_regs;
318 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
319 save slots from the top of the frame, or zero if no such slots are
321 HOST_WIDE_INT gp_save_offset;
322 HOST_WIDE_INT fp_save_offset;
323 HOST_WIDE_INT acc_save_offset;
324 HOST_WIDE_INT cop0_save_offset;
326 /* Likewise, but giving offsets from the bottom of the frame. */
327 HOST_WIDE_INT gp_sp_offset;
328 HOST_WIDE_INT fp_sp_offset;
329 HOST_WIDE_INT acc_sp_offset;
330 HOST_WIDE_INT cop0_sp_offset;
332 /* Similar, but the value passed to _mcount. */
333 HOST_WIDE_INT ra_fp_offset;
335 /* The offset of arg_pointer_rtx from the bottom of the frame. */
336 HOST_WIDE_INT arg_pointer_offset;
338 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
339 HOST_WIDE_INT hard_frame_pointer_offset;
342 struct GTY(()) machine_function {
343 /* The next floating-point condition-code register to allocate
344 for ISA_HAS_8CC targets, relative to ST_REG_FIRST. */
345 unsigned int next_fcc;
347 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
348 rtx mips16_gp_pseudo_rtx;
350 /* The number of extra stack bytes taken up by register varargs.
351 This area is allocated by the callee at the very top of the frame. */
354 /* The current frame information, calculated by mips_compute_frame_info. */
355 struct mips_frame_info frame;
357 /* The register to use as the function's global pointer, or INVALID_REGNUM
358 if the function doesn't need one. */
359 unsigned int global_pointer;
361 /* How many instructions it takes to load a label into $AT, or 0 if
362 this property hasn't yet been calculated. */
363 unsigned int load_label_num_insns;
365 /* True if mips_adjust_insn_length should ignore an instruction's
367 bool ignore_hazard_length_p;
369 /* True if the whole function is suitable for .set noreorder and
371 bool all_noreorder_p;
373 /* True if the function has "inflexible" and "flexible" references
374 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
375 and mips_cfun_has_flexible_gp_ref_p for details. */
376 bool has_inflexible_gp_insn_p;
377 bool has_flexible_gp_insn_p;
379 /* True if the function's prologue must load the global pointer
380 value into pic_offset_table_rtx and store the same value in
381 the function's cprestore slot (if any). Even if this value
382 is currently false, we may decide to set it to true later;
383 see mips_must_initialize_gp_p () for details. */
384 bool must_initialize_gp_p;
386 /* True if the current function must restore $gp after any potential
387 clobber. This value is only meaningful during the first post-epilogue
388 split_insns pass; see mips_must_initialize_gp_p () for details. */
389 bool must_restore_gp_when_clobbered_p;
391 /* True if this is an interrupt handler. */
392 bool interrupt_handler_p;
394 /* True if this is an interrupt handler that uses shadow registers. */
395 bool use_shadow_register_set_p;
397 /* True if this is an interrupt handler that should keep interrupts
399 bool keep_interrupts_masked_p;
401 /* True if this is an interrupt handler that should use DERET
403 bool use_debug_exception_return_p;
406 /* Information about a single argument. */
407 struct mips_arg_info {
408 /* True if the argument is passed in a floating-point register, or
409 would have been if we hadn't run out of registers. */
412 /* The number of words passed in registers, rounded up. */
413 unsigned int reg_words;
415 /* For EABI, the offset of the first register from GP_ARG_FIRST or
416 FP_ARG_FIRST. For other ABIs, the offset of the first register from
417 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
418 comment for details).
420 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
422 unsigned int reg_offset;
424 /* The number of words that must be passed on the stack, rounded up. */
425 unsigned int stack_words;
427 /* The offset from the start of the stack overflow area of the argument's
428 first stack word. Only meaningful when STACK_WORDS is nonzero. */
429 unsigned int stack_offset;
432 /* Information about an address described by mips_address_type.
438 REG is the base register and OFFSET is the constant offset.
441 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
442 is the type of symbol it references.
445 SYMBOL_TYPE is the type of symbol that the address references. */
446 struct mips_address_info {
447 enum mips_address_type type;
450 enum mips_symbol_type symbol_type;
453 /* One stage in a constant building sequence. These sequences have
457 A = A CODE[1] VALUE[1]
458 A = A CODE[2] VALUE[2]
461 where A is an accumulator, each CODE[i] is a binary rtl operation
462 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
463 struct mips_integer_op {
465 unsigned HOST_WIDE_INT value;
468 /* The largest number of operations needed to load an integer constant.
469 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
470 When the lowest bit is clear, we can try, but reject a sequence with
471 an extra SLL at the end. */
472 #define MIPS_MAX_INTEGER_OPS 7
474 /* Information about a MIPS16e SAVE or RESTORE instruction. */
475 struct mips16e_save_restore_info {
476 /* The number of argument registers saved by a SAVE instruction.
477 0 for RESTORE instructions. */
480 /* Bit X is set if the instruction saves or restores GPR X. */
483 /* The total number of bytes to allocate. */
487 /* Costs of various operations on the different architectures. */
489 struct mips_rtx_cost_data
491 unsigned short fp_add;
492 unsigned short fp_mult_sf;
493 unsigned short fp_mult_df;
494 unsigned short fp_div_sf;
495 unsigned short fp_div_df;
496 unsigned short int_mult_si;
497 unsigned short int_mult_di;
498 unsigned short int_div_si;
499 unsigned short int_div_di;
500 unsigned short branch_cost;
501 unsigned short memory_latency;
504 /* Global variables for machine-dependent things. */
506 /* The -G setting, or the configuration's default small-data limit if
507 no -G option is given. */
508 static unsigned int mips_small_data_threshold;
510 /* The number of file directives written by mips_output_filename. */
511 int num_source_filenames;
513 /* The name that appeared in the last .file directive written by
514 mips_output_filename, or "" if mips_output_filename hasn't
515 written anything yet. */
516 const char *current_function_file = "";
518 /* Arrays that map GCC register numbers to debugger register numbers. */
519 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
520 int mips_dwarf_regno[FIRST_PSEUDO_REGISTER];
522 /* Information about the current function's epilogue, used only while
525 /* A list of queued REG_CFA_RESTORE notes. */
528 /* The CFA is currently defined as CFA_REG + CFA_OFFSET. */
530 HOST_WIDE_INT cfa_offset;
532 /* The offset of the CFA from the stack pointer while restoring
534 HOST_WIDE_INT cfa_restore_sp_offset;
537 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
538 struct mips_asm_switch mips_noreorder = { "reorder", 0 };
539 struct mips_asm_switch mips_nomacro = { "macro", 0 };
540 struct mips_asm_switch mips_noat = { "at", 0 };
542 /* True if we're writing out a branch-likely instruction rather than a
544 static bool mips_branch_likely;
546 /* The current instruction-set architecture. */
547 enum processor mips_arch;
548 const struct mips_cpu_info *mips_arch_info;
550 /* The processor that we should tune the code for. */
551 enum processor mips_tune;
552 const struct mips_cpu_info *mips_tune_info;
554 /* The ISA level associated with mips_arch. */
557 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
558 static const struct mips_cpu_info *mips_isa_option_info;
560 /* Which cost information to use. */
561 static const struct mips_rtx_cost_data *mips_cost;
563 /* The ambient target flags, excluding MASK_MIPS16. */
564 static int mips_base_target_flags;
566 /* The default compression mode. */
567 unsigned int mips_base_compression_flags;
569 /* The ambient values of other global variables. */
570 static int mips_base_schedule_insns; /* flag_schedule_insns */
571 static int mips_base_reorder_blocks_and_partition; /* flag_reorder... */
572 static int mips_base_move_loop_invariants; /* flag_move_loop_invariants */
573 static int mips_base_align_loops; /* align_loops */
574 static int mips_base_align_jumps; /* align_jumps */
575 static int mips_base_align_functions; /* align_functions */
577 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
578 bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
580 /* Index C is true if character C is a valid PRINT_OPERAND punctation
582 static bool mips_print_operand_punct[256];
584 static GTY (()) int mips_output_filename_first_time = 1;
586 /* mips_split_p[X] is true if symbols of type X can be split by
587 mips_split_symbol. */
588 bool mips_split_p[NUM_SYMBOL_TYPES];
590 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
591 can be split by mips_split_symbol. */
592 bool mips_split_hi_p[NUM_SYMBOL_TYPES];
594 /* mips_use_pcrel_pool_p[X] is true if symbols of type X should be
595 forced into a PC-relative constant pool. */
596 bool mips_use_pcrel_pool_p[NUM_SYMBOL_TYPES];
598 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
599 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
600 if they are matched by a special .md file pattern. */
601 const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
603 /* Likewise for HIGHs. */
604 const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
606 /* Target state for MIPS16. */
607 struct target_globals *mips16_globals;
609 /* Cached value of can_issue_more. This is cached in mips_variable_issue hook
610 and returned from mips_sched_reorder2. */
611 static int cached_can_issue_more;
613 /* True if the output uses __mips16_rdhwr. */
614 static bool mips_need_mips16_rdhwr_p;
616 /* Index R is the smallest register class that contains register R. */
617 const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = {
618 LEA_REGS, LEA_REGS, M16_REGS, V1_REG,
619 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
620 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
621 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
622 M16_REGS, M16_REGS, LEA_REGS, LEA_REGS,
623 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
624 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
625 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
626 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
627 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
628 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
629 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
630 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
631 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
632 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
633 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
634 MD0_REG, MD1_REG, NO_REGS, ST_REGS,
635 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
636 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
637 NO_REGS, FRAME_REGS, FRAME_REGS, NO_REGS,
638 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
639 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
640 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
641 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
642 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
643 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
644 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
645 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
646 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
647 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
648 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
649 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
650 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
651 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
652 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
653 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
654 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
655 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
656 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
657 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
658 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
659 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
660 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
661 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
662 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
663 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
664 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
667 /* The value of TARGET_ATTRIBUTE_TABLE. */
668 static const struct attribute_spec mips_attribute_table[] = {
669 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
671 { "long_call", 0, 0, false, true, true, NULL, false },
672 { "far", 0, 0, false, true, true, NULL, false },
673 { "near", 0, 0, false, true, true, NULL, false },
674 /* We would really like to treat "mips16" and "nomips16" as type
675 attributes, but GCC doesn't provide the hooks we need to support
676 the right conversion rules. As declaration attributes, they affect
677 code generation but don't carry other semantics. */
678 { "mips16", 0, 0, true, false, false, NULL, false },
679 { "nomips16", 0, 0, true, false, false, NULL, false },
680 { "micromips", 0, 0, true, false, false, NULL, false },
681 { "nomicromips", 0, 0, true, false, false, NULL, false },
682 { "nocompression", 0, 0, true, false, false, NULL, false },
683 /* Allow functions to be specified as interrupt handlers */
684 { "interrupt", 0, 0, false, true, true, NULL, false },
685 { "use_shadow_register_set", 0, 0, false, true, true, NULL, false },
686 { "keep_interrupts_masked", 0, 0, false, true, true, NULL, false },
687 { "use_debug_exception_return", 0, 0, false, true, true, NULL, false },
688 { NULL, 0, 0, false, false, false, NULL, false }
691 /* A table describing all the processors GCC knows about; see
692 mips-cpus.def for details. */
693 static const struct mips_cpu_info mips_cpu_info_table[] = {
694 #define MIPS_CPU(NAME, CPU, ISA, FLAGS) \
695 { NAME, CPU, ISA, FLAGS },
696 #include "mips-cpus.def"
700 /* Default costs. If these are used for a processor we should look
701 up the actual costs. */
702 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
703 COSTS_N_INSNS (7), /* fp_mult_sf */ \
704 COSTS_N_INSNS (8), /* fp_mult_df */ \
705 COSTS_N_INSNS (23), /* fp_div_sf */ \
706 COSTS_N_INSNS (36), /* fp_div_df */ \
707 COSTS_N_INSNS (10), /* int_mult_si */ \
708 COSTS_N_INSNS (10), /* int_mult_di */ \
709 COSTS_N_INSNS (69), /* int_div_si */ \
710 COSTS_N_INSNS (69), /* int_div_di */ \
711 2, /* branch_cost */ \
712 4 /* memory_latency */
714 /* Floating-point costs for processors without an FPU. Just assume that
715 all floating-point libcalls are very expensive. */
716 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
717 COSTS_N_INSNS (256), /* fp_mult_sf */ \
718 COSTS_N_INSNS (256), /* fp_mult_df */ \
719 COSTS_N_INSNS (256), /* fp_div_sf */ \
720 COSTS_N_INSNS (256) /* fp_div_df */
722 /* Costs to use when optimizing for size. */
723 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size = {
724 COSTS_N_INSNS (1), /* fp_add */
725 COSTS_N_INSNS (1), /* fp_mult_sf */
726 COSTS_N_INSNS (1), /* fp_mult_df */
727 COSTS_N_INSNS (1), /* fp_div_sf */
728 COSTS_N_INSNS (1), /* fp_div_df */
729 COSTS_N_INSNS (1), /* int_mult_si */
730 COSTS_N_INSNS (1), /* int_mult_di */
731 COSTS_N_INSNS (1), /* int_div_si */
732 COSTS_N_INSNS (1), /* int_div_di */
734 4 /* memory_latency */
737 /* Costs to use when optimizing for speed, indexed by processor. */
738 static const struct mips_rtx_cost_data
739 mips_rtx_cost_data[NUM_PROCESSOR_VALUES] = {
741 COSTS_N_INSNS (2), /* fp_add */
742 COSTS_N_INSNS (4), /* fp_mult_sf */
743 COSTS_N_INSNS (5), /* fp_mult_df */
744 COSTS_N_INSNS (12), /* fp_div_sf */
745 COSTS_N_INSNS (19), /* fp_div_df */
746 COSTS_N_INSNS (12), /* int_mult_si */
747 COSTS_N_INSNS (12), /* int_mult_di */
748 COSTS_N_INSNS (35), /* int_div_si */
749 COSTS_N_INSNS (35), /* int_div_di */
751 4 /* memory_latency */
755 COSTS_N_INSNS (6), /* int_mult_si */
756 COSTS_N_INSNS (6), /* int_mult_di */
757 COSTS_N_INSNS (36), /* int_div_si */
758 COSTS_N_INSNS (36), /* int_div_di */
760 4 /* memory_latency */
764 COSTS_N_INSNS (36), /* int_mult_si */
765 COSTS_N_INSNS (36), /* int_mult_di */
766 COSTS_N_INSNS (37), /* int_div_si */
767 COSTS_N_INSNS (37), /* int_div_di */
769 4 /* memory_latency */
773 COSTS_N_INSNS (4), /* int_mult_si */
774 COSTS_N_INSNS (11), /* int_mult_di */
775 COSTS_N_INSNS (36), /* int_div_si */
776 COSTS_N_INSNS (68), /* int_div_di */
778 4 /* memory_latency */
781 COSTS_N_INSNS (4), /* fp_add */
782 COSTS_N_INSNS (4), /* fp_mult_sf */
783 COSTS_N_INSNS (5), /* fp_mult_df */
784 COSTS_N_INSNS (17), /* fp_div_sf */
785 COSTS_N_INSNS (32), /* fp_div_df */
786 COSTS_N_INSNS (4), /* int_mult_si */
787 COSTS_N_INSNS (11), /* int_mult_di */
788 COSTS_N_INSNS (36), /* int_div_si */
789 COSTS_N_INSNS (68), /* int_div_di */
791 4 /* memory_latency */
794 COSTS_N_INSNS (4), /* fp_add */
795 COSTS_N_INSNS (4), /* fp_mult_sf */
796 COSTS_N_INSNS (5), /* fp_mult_df */
797 COSTS_N_INSNS (17), /* fp_div_sf */
798 COSTS_N_INSNS (32), /* fp_div_df */
799 COSTS_N_INSNS (4), /* int_mult_si */
800 COSTS_N_INSNS (7), /* int_mult_di */
801 COSTS_N_INSNS (42), /* int_div_si */
802 COSTS_N_INSNS (72), /* int_div_di */
804 4 /* memory_latency */
808 COSTS_N_INSNS (5), /* int_mult_si */
809 COSTS_N_INSNS (5), /* int_mult_di */
810 COSTS_N_INSNS (41), /* int_div_si */
811 COSTS_N_INSNS (41), /* int_div_di */
813 4 /* memory_latency */
816 COSTS_N_INSNS (8), /* fp_add */
817 COSTS_N_INSNS (8), /* fp_mult_sf */
818 COSTS_N_INSNS (10), /* fp_mult_df */
819 COSTS_N_INSNS (34), /* fp_div_sf */
820 COSTS_N_INSNS (64), /* fp_div_df */
821 COSTS_N_INSNS (5), /* int_mult_si */
822 COSTS_N_INSNS (5), /* int_mult_di */
823 COSTS_N_INSNS (41), /* int_div_si */
824 COSTS_N_INSNS (41), /* int_div_di */
826 4 /* memory_latency */
829 COSTS_N_INSNS (4), /* fp_add */
830 COSTS_N_INSNS (4), /* fp_mult_sf */
831 COSTS_N_INSNS (5), /* fp_mult_df */
832 COSTS_N_INSNS (17), /* fp_div_sf */
833 COSTS_N_INSNS (32), /* fp_div_df */
834 COSTS_N_INSNS (5), /* int_mult_si */
835 COSTS_N_INSNS (5), /* int_mult_di */
836 COSTS_N_INSNS (41), /* int_div_si */
837 COSTS_N_INSNS (41), /* int_div_di */
839 4 /* memory_latency */
843 COSTS_N_INSNS (5), /* int_mult_si */
844 COSTS_N_INSNS (5), /* int_mult_di */
845 COSTS_N_INSNS (41), /* int_div_si */
846 COSTS_N_INSNS (41), /* int_div_di */
848 4 /* memory_latency */
851 COSTS_N_INSNS (8), /* fp_add */
852 COSTS_N_INSNS (8), /* fp_mult_sf */
853 COSTS_N_INSNS (10), /* fp_mult_df */
854 COSTS_N_INSNS (34), /* fp_div_sf */
855 COSTS_N_INSNS (64), /* fp_div_df */
856 COSTS_N_INSNS (5), /* int_mult_si */
857 COSTS_N_INSNS (5), /* int_mult_di */
858 COSTS_N_INSNS (41), /* int_div_si */
859 COSTS_N_INSNS (41), /* int_div_di */
861 4 /* memory_latency */
864 COSTS_N_INSNS (4), /* fp_add */
865 COSTS_N_INSNS (4), /* fp_mult_sf */
866 COSTS_N_INSNS (5), /* fp_mult_df */
867 COSTS_N_INSNS (17), /* fp_div_sf */
868 COSTS_N_INSNS (32), /* fp_div_df */
869 COSTS_N_INSNS (5), /* int_mult_si */
870 COSTS_N_INSNS (5), /* int_mult_di */
871 COSTS_N_INSNS (41), /* int_div_si */
872 COSTS_N_INSNS (41), /* int_div_di */
874 4 /* memory_latency */
877 COSTS_N_INSNS (6), /* fp_add */
878 COSTS_N_INSNS (6), /* fp_mult_sf */
879 COSTS_N_INSNS (7), /* fp_mult_df */
880 COSTS_N_INSNS (25), /* fp_div_sf */
881 COSTS_N_INSNS (48), /* fp_div_df */
882 COSTS_N_INSNS (5), /* int_mult_si */
883 COSTS_N_INSNS (5), /* int_mult_di */
884 COSTS_N_INSNS (41), /* int_div_si */
885 COSTS_N_INSNS (41), /* int_div_di */
887 4 /* memory_latency */
904 COSTS_N_INSNS (5), /* int_mult_si */
905 COSTS_N_INSNS (5), /* int_mult_di */
906 COSTS_N_INSNS (72), /* int_div_si */
907 COSTS_N_INSNS (72), /* int_div_di */
909 4 /* memory_latency */
914 COSTS_N_INSNS (6), /* int_mult_si */
915 COSTS_N_INSNS (6), /* int_mult_di */
916 COSTS_N_INSNS (18), /* int_div_si */
917 COSTS_N_INSNS (35), /* int_div_di */
919 4 /* memory_latency */
922 COSTS_N_INSNS (2), /* fp_add */
923 COSTS_N_INSNS (4), /* fp_mult_sf */
924 COSTS_N_INSNS (5), /* fp_mult_df */
925 COSTS_N_INSNS (12), /* fp_div_sf */
926 COSTS_N_INSNS (19), /* fp_div_df */
927 COSTS_N_INSNS (2), /* int_mult_si */
928 COSTS_N_INSNS (2), /* int_mult_di */
929 COSTS_N_INSNS (35), /* int_div_si */
930 COSTS_N_INSNS (35), /* int_div_di */
932 4 /* memory_latency */
935 COSTS_N_INSNS (3), /* fp_add */
936 COSTS_N_INSNS (5), /* fp_mult_sf */
937 COSTS_N_INSNS (6), /* fp_mult_df */
938 COSTS_N_INSNS (15), /* fp_div_sf */
939 COSTS_N_INSNS (16), /* fp_div_df */
940 COSTS_N_INSNS (17), /* int_mult_si */
941 COSTS_N_INSNS (17), /* int_mult_di */
942 COSTS_N_INSNS (38), /* int_div_si */
943 COSTS_N_INSNS (38), /* int_div_di */
945 6 /* memory_latency */
948 COSTS_N_INSNS (6), /* fp_add */
949 COSTS_N_INSNS (7), /* fp_mult_sf */
950 COSTS_N_INSNS (8), /* fp_mult_df */
951 COSTS_N_INSNS (23), /* fp_div_sf */
952 COSTS_N_INSNS (36), /* fp_div_df */
953 COSTS_N_INSNS (10), /* int_mult_si */
954 COSTS_N_INSNS (10), /* int_mult_di */
955 COSTS_N_INSNS (69), /* int_div_si */
956 COSTS_N_INSNS (69), /* int_div_di */
958 6 /* memory_latency */
970 /* The only costs that appear to be updated here are
971 integer multiplication. */
973 COSTS_N_INSNS (4), /* int_mult_si */
974 COSTS_N_INSNS (6), /* int_mult_di */
975 COSTS_N_INSNS (69), /* int_div_si */
976 COSTS_N_INSNS (69), /* int_div_di */
978 4 /* memory_latency */
993 COSTS_N_INSNS (6), /* fp_add */
994 COSTS_N_INSNS (4), /* fp_mult_sf */
995 COSTS_N_INSNS (5), /* fp_mult_df */
996 COSTS_N_INSNS (23), /* fp_div_sf */
997 COSTS_N_INSNS (36), /* fp_div_df */
998 COSTS_N_INSNS (5), /* int_mult_si */
999 COSTS_N_INSNS (5), /* int_mult_di */
1000 COSTS_N_INSNS (36), /* int_div_si */
1001 COSTS_N_INSNS (36), /* int_div_di */
1002 1, /* branch_cost */
1003 4 /* memory_latency */
1006 COSTS_N_INSNS (6), /* fp_add */
1007 COSTS_N_INSNS (5), /* fp_mult_sf */
1008 COSTS_N_INSNS (6), /* fp_mult_df */
1009 COSTS_N_INSNS (30), /* fp_div_sf */
1010 COSTS_N_INSNS (59), /* fp_div_df */
1011 COSTS_N_INSNS (3), /* int_mult_si */
1012 COSTS_N_INSNS (4), /* int_mult_di */
1013 COSTS_N_INSNS (42), /* int_div_si */
1014 COSTS_N_INSNS (74), /* int_div_di */
1015 1, /* branch_cost */
1016 4 /* memory_latency */
1019 COSTS_N_INSNS (6), /* fp_add */
1020 COSTS_N_INSNS (5), /* fp_mult_sf */
1021 COSTS_N_INSNS (6), /* fp_mult_df */
1022 COSTS_N_INSNS (30), /* fp_div_sf */
1023 COSTS_N_INSNS (59), /* fp_div_df */
1024 COSTS_N_INSNS (5), /* int_mult_si */
1025 COSTS_N_INSNS (9), /* int_mult_di */
1026 COSTS_N_INSNS (42), /* int_div_si */
1027 COSTS_N_INSNS (74), /* int_div_di */
1028 1, /* branch_cost */
1029 4 /* memory_latency */
1032 /* The only costs that are changed here are
1033 integer multiplication. */
1034 COSTS_N_INSNS (6), /* fp_add */
1035 COSTS_N_INSNS (7), /* fp_mult_sf */
1036 COSTS_N_INSNS (8), /* fp_mult_df */
1037 COSTS_N_INSNS (23), /* fp_div_sf */
1038 COSTS_N_INSNS (36), /* fp_div_df */
1039 COSTS_N_INSNS (5), /* int_mult_si */
1040 COSTS_N_INSNS (9), /* int_mult_di */
1041 COSTS_N_INSNS (69), /* int_div_si */
1042 COSTS_N_INSNS (69), /* int_div_di */
1043 1, /* branch_cost */
1044 4 /* memory_latency */
1050 /* The only costs that are changed here are
1051 integer multiplication. */
1052 COSTS_N_INSNS (6), /* fp_add */
1053 COSTS_N_INSNS (7), /* fp_mult_sf */
1054 COSTS_N_INSNS (8), /* fp_mult_df */
1055 COSTS_N_INSNS (23), /* fp_div_sf */
1056 COSTS_N_INSNS (36), /* fp_div_df */
1057 COSTS_N_INSNS (3), /* int_mult_si */
1058 COSTS_N_INSNS (8), /* int_mult_di */
1059 COSTS_N_INSNS (69), /* int_div_si */
1060 COSTS_N_INSNS (69), /* int_div_di */
1061 1, /* branch_cost */
1062 4 /* memory_latency */
1065 COSTS_N_INSNS (2), /* fp_add */
1066 COSTS_N_INSNS (2), /* fp_mult_sf */
1067 COSTS_N_INSNS (2), /* fp_mult_df */
1068 COSTS_N_INSNS (12), /* fp_div_sf */
1069 COSTS_N_INSNS (19), /* fp_div_df */
1070 COSTS_N_INSNS (5), /* int_mult_si */
1071 COSTS_N_INSNS (9), /* int_mult_di */
1072 COSTS_N_INSNS (34), /* int_div_si */
1073 COSTS_N_INSNS (66), /* int_div_di */
1074 1, /* branch_cost */
1075 4 /* memory_latency */
1078 /* These costs are the same as the SB-1A below. */
1079 COSTS_N_INSNS (4), /* fp_add */
1080 COSTS_N_INSNS (4), /* fp_mult_sf */
1081 COSTS_N_INSNS (4), /* fp_mult_df */
1082 COSTS_N_INSNS (24), /* fp_div_sf */
1083 COSTS_N_INSNS (32), /* fp_div_df */
1084 COSTS_N_INSNS (3), /* int_mult_si */
1085 COSTS_N_INSNS (4), /* int_mult_di */
1086 COSTS_N_INSNS (36), /* int_div_si */
1087 COSTS_N_INSNS (68), /* int_div_di */
1088 1, /* branch_cost */
1089 4 /* memory_latency */
1092 /* These costs are the same as the SB-1 above. */
1093 COSTS_N_INSNS (4), /* fp_add */
1094 COSTS_N_INSNS (4), /* fp_mult_sf */
1095 COSTS_N_INSNS (4), /* fp_mult_df */
1096 COSTS_N_INSNS (24), /* fp_div_sf */
1097 COSTS_N_INSNS (32), /* fp_div_df */
1098 COSTS_N_INSNS (3), /* int_mult_si */
1099 COSTS_N_INSNS (4), /* int_mult_di */
1100 COSTS_N_INSNS (36), /* int_div_si */
1101 COSTS_N_INSNS (68), /* int_div_di */
1102 1, /* branch_cost */
1103 4 /* memory_latency */
1110 COSTS_N_INSNS (8), /* int_mult_si */
1111 COSTS_N_INSNS (8), /* int_mult_di */
1112 COSTS_N_INSNS (72), /* int_div_si */
1113 COSTS_N_INSNS (72), /* int_div_di */
1114 1, /* branch_cost */
1115 4 /* memory_latency */
1118 /* These costs are the same as 5KF above. */
1119 COSTS_N_INSNS (4), /* fp_add */
1120 COSTS_N_INSNS (4), /* fp_mult_sf */
1121 COSTS_N_INSNS (5), /* fp_mult_df */
1122 COSTS_N_INSNS (17), /* fp_div_sf */
1123 COSTS_N_INSNS (32), /* fp_div_df */
1124 COSTS_N_INSNS (4), /* int_mult_si */
1125 COSTS_N_INSNS (11), /* int_mult_di */
1126 COSTS_N_INSNS (36), /* int_div_si */
1127 COSTS_N_INSNS (68), /* int_div_di */
1128 1, /* branch_cost */
1129 4 /* memory_latency */
1133 static rtx mips_find_pic_call_symbol (rtx, rtx, bool);
1134 static int mips_register_move_cost (enum machine_mode, reg_class_t,
1136 static unsigned int mips_function_arg_boundary (enum machine_mode, const_tree);
1138 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1139 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1140 struct GTY (()) mflip_mips16_entry {
1144 static GTY ((param_is (struct mflip_mips16_entry))) htab_t mflip_mips16_htab;
1146 /* Hash table callbacks for mflip_mips16_htab. */
1149 mflip_mips16_htab_hash (const void *entry)
1151 return htab_hash_string (((const struct mflip_mips16_entry *) entry)->name);
1155 mflip_mips16_htab_eq (const void *entry, const void *name)
1157 return strcmp (((const struct mflip_mips16_entry *) entry)->name,
1158 (const char *) name) == 0;
1161 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1162 mode, false if it should next add an attribute for the opposite mode. */
1163 static GTY(()) bool mips16_flipper;
1165 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1166 for -mflip-mips16. Return true if it should use "mips16" and false if
1167 it should use "nomips16". */
1170 mflip_mips16_use_mips16_p (tree decl)
1172 struct mflip_mips16_entry *entry;
1176 bool base_is_mips16 = (mips_base_compression_flags & MASK_MIPS16) != 0;
1178 /* Use the opposite of the command-line setting for anonymous decls. */
1179 if (!DECL_NAME (decl))
1180 return !base_is_mips16;
1182 if (!mflip_mips16_htab)
1183 mflip_mips16_htab = htab_create_ggc (37, mflip_mips16_htab_hash,
1184 mflip_mips16_htab_eq, NULL);
1186 name = IDENTIFIER_POINTER (DECL_NAME (decl));
1187 hash = htab_hash_string (name);
1188 slot = htab_find_slot_with_hash (mflip_mips16_htab, name, hash, INSERT);
1189 entry = (struct mflip_mips16_entry *) *slot;
1192 mips16_flipper = !mips16_flipper;
1193 entry = ggc_alloc_mflip_mips16_entry ();
1195 entry->mips16_p = mips16_flipper ? !base_is_mips16 : base_is_mips16;
1198 return entry->mips16_p;
1201 /* Predicates to test for presence of "near" and "far"/"long_call"
1202 attributes on the given TYPE. */
1205 mips_near_type_p (const_tree type)
1207 return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL;
1211 mips_far_type_p (const_tree type)
1213 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL
1214 || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL);
1218 /* Check if the interrupt attribute is set for a function. */
1221 mips_interrupt_type_p (tree type)
1223 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type)) != NULL;
1226 /* Check if the attribute to use shadow register set is set for a function. */
1229 mips_use_shadow_register_set_p (tree type)
1231 return lookup_attribute ("use_shadow_register_set",
1232 TYPE_ATTRIBUTES (type)) != NULL;
1235 /* Check if the attribute to keep interrupts masked is set for a function. */
1238 mips_keep_interrupts_masked_p (tree type)
1240 return lookup_attribute ("keep_interrupts_masked",
1241 TYPE_ATTRIBUTES (type)) != NULL;
1244 /* Check if the attribute to use debug exception return is set for
1248 mips_use_debug_exception_return_p (tree type)
1250 return lookup_attribute ("use_debug_exception_return",
1251 TYPE_ATTRIBUTES (type)) != NULL;
1254 /* Return the set of compression modes that are explicitly required
1255 by the attributes in ATTRIBUTES. */
1258 mips_get_compress_on_flags (tree attributes)
1260 unsigned int flags = 0;
1262 if (lookup_attribute ("mips16", attributes) != NULL)
1263 flags |= MASK_MIPS16;
1265 if (lookup_attribute ("micromips", attributes) != NULL)
1266 flags |= MASK_MICROMIPS;
1271 /* Return the set of compression modes that are explicitly forbidden
1272 by the attributes in ATTRIBUTES. */
1275 mips_get_compress_off_flags (tree attributes)
1277 unsigned int flags = 0;
1279 if (lookup_attribute ("nocompression", attributes) != NULL)
1280 flags |= MASK_MIPS16 | MASK_MICROMIPS;
1282 if (lookup_attribute ("nomips16", attributes) != NULL)
1283 flags |= MASK_MIPS16;
1285 if (lookup_attribute ("nomicromips", attributes) != NULL)
1286 flags |= MASK_MICROMIPS;
1291 /* Return the compression mode that should be used for function DECL.
1292 Return the ambient setting if DECL is null. */
1295 mips_get_compress_mode (tree decl)
1297 unsigned int flags, force_on;
1299 flags = mips_base_compression_flags;
1302 /* Nested functions must use the same frame pointer as their
1303 parent and must therefore use the same ISA mode. */
1304 tree parent = decl_function_context (decl);
1307 force_on = mips_get_compress_on_flags (DECL_ATTRIBUTES (decl));
1310 flags &= ~mips_get_compress_off_flags (DECL_ATTRIBUTES (decl));
1315 /* Return the attribute name associated with MASK_MIPS16 and MASK_MICROMIPS
1319 mips_get_compress_on_name (unsigned int flags)
1321 if (flags == MASK_MIPS16)
1326 /* Return the attribute name that forbids MASK_MIPS16 and MASK_MICROMIPS
1330 mips_get_compress_off_name (unsigned int flags)
1332 if (flags == MASK_MIPS16)
1334 if (flags == MASK_MICROMIPS)
1335 return "nomicromips";
1336 return "nocompression";
1339 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1342 mips_comp_type_attributes (const_tree type1, const_tree type2)
1344 /* Disallow mixed near/far attributes. */
1345 if (mips_far_type_p (type1) && mips_near_type_p (type2))
1347 if (mips_near_type_p (type1) && mips_far_type_p (type2))
1352 /* Implement TARGET_INSERT_ATTRIBUTES. */
1355 mips_insert_attributes (tree decl, tree *attributes)
1358 unsigned int compression_flags, nocompression_flags;
1360 /* Check for "mips16" and "nomips16" attributes. */
1361 compression_flags = mips_get_compress_on_flags (*attributes);
1362 nocompression_flags = mips_get_compress_off_flags (*attributes);
1364 if (TREE_CODE (decl) != FUNCTION_DECL)
1366 if (nocompression_flags)
1367 error ("%qs attribute only applies to functions",
1368 mips_get_compress_off_name (nocompression_flags));
1370 if (compression_flags)
1371 error ("%qs attribute only applies to functions",
1372 mips_get_compress_on_name (nocompression_flags));
1376 compression_flags |= mips_get_compress_on_flags (DECL_ATTRIBUTES (decl));
1377 nocompression_flags |=
1378 mips_get_compress_off_flags (DECL_ATTRIBUTES (decl));
1380 if (compression_flags && nocompression_flags)
1381 error ("%qE cannot have both %qs and %qs attributes",
1382 DECL_NAME (decl), mips_get_compress_on_name (compression_flags),
1383 mips_get_compress_off_name (nocompression_flags));
1385 if (compression_flags & MASK_MIPS16
1386 && compression_flags & MASK_MICROMIPS)
1387 error ("%qE cannot have both %qs and %qs attributes",
1388 DECL_NAME (decl), "mips16", "micromips");
1390 if (TARGET_FLIP_MIPS16
1391 && !DECL_ARTIFICIAL (decl)
1392 && compression_flags == 0
1393 && nocompression_flags == 0)
1395 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1396 "mips16" attribute, arbitrarily pick one. We must pick the same
1397 setting for duplicate declarations of a function. */
1398 name = mflip_mips16_use_mips16_p (decl) ? "mips16" : "nomips16";
1399 *attributes = tree_cons (get_identifier (name), NULL, *attributes);
1400 name = "nomicromips";
1401 *attributes = tree_cons (get_identifier (name), NULL, *attributes);
1406 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1409 mips_merge_decl_attributes (tree olddecl, tree newdecl)
1413 diff = (mips_get_compress_on_flags (DECL_ATTRIBUTES (olddecl))
1414 ^ mips_get_compress_on_flags (DECL_ATTRIBUTES (newdecl)));
1416 error ("%qE redeclared with conflicting %qs attributes",
1417 DECL_NAME (newdecl), mips_get_compress_on_name (diff));
1419 diff = (mips_get_compress_off_flags (DECL_ATTRIBUTES (olddecl))
1420 ^ mips_get_compress_off_flags (DECL_ATTRIBUTES (newdecl)));
1422 error ("%qE redeclared with conflicting %qs attributes",
1423 DECL_NAME (newdecl), mips_get_compress_off_name (diff));
1425 return merge_attributes (DECL_ATTRIBUTES (olddecl),
1426 DECL_ATTRIBUTES (newdecl));
1429 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1430 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1433 mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr)
1435 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
1437 *base_ptr = XEXP (x, 0);
1438 *offset_ptr = INTVAL (XEXP (x, 1));
1447 static unsigned int mips_build_integer (struct mips_integer_op *,
1448 unsigned HOST_WIDE_INT);
1450 /* A subroutine of mips_build_integer, with the same interface.
1451 Assume that the final action in the sequence should be a left shift. */
1454 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1456 unsigned int i, shift;
1458 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1459 since signed numbers are easier to load than unsigned ones. */
1461 while ((value & 1) == 0)
1462 value /= 2, shift++;
1464 i = mips_build_integer (codes, value);
1465 codes[i].code = ASHIFT;
1466 codes[i].value = shift;
1470 /* As for mips_build_shift, but assume that the final action will be
1471 an IOR or PLUS operation. */
1474 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1476 unsigned HOST_WIDE_INT high;
1479 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1480 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
1482 /* The constant is too complex to load with a simple LUI/ORI pair,
1483 so we want to give the recursive call as many trailing zeros as
1484 possible. In this case, we know bit 16 is set and that the
1485 low 16 bits form a negative number. If we subtract that number
1486 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1487 i = mips_build_integer (codes, CONST_HIGH_PART (value));
1488 codes[i].code = PLUS;
1489 codes[i].value = CONST_LOW_PART (value);
1493 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1494 bits gives a value with at least 17 trailing zeros. */
1495 i = mips_build_integer (codes, high);
1496 codes[i].code = IOR;
1497 codes[i].value = value & 0xffff;
1502 /* Fill CODES with a sequence of rtl operations to load VALUE.
1503 Return the number of operations needed. */
1506 mips_build_integer (struct mips_integer_op *codes,
1507 unsigned HOST_WIDE_INT value)
1509 if (SMALL_OPERAND (value)
1510 || SMALL_OPERAND_UNSIGNED (value)
1511 || LUI_OPERAND (value))
1513 /* The value can be loaded with a single instruction. */
1514 codes[0].code = UNKNOWN;
1515 codes[0].value = value;
1518 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
1520 /* Either the constant is a simple LUI/ORI combination or its
1521 lowest bit is set. We don't want to shift in this case. */
1522 return mips_build_lower (codes, value);
1524 else if ((value & 0xffff) == 0)
1526 /* The constant will need at least three actions. The lowest
1527 16 bits are clear, so the final action will be a shift. */
1528 return mips_build_shift (codes, value);
1532 /* The final action could be a shift, add or inclusive OR.
1533 Rather than use a complex condition to select the best
1534 approach, try both mips_build_shift and mips_build_lower
1535 and pick the one that gives the shortest sequence.
1536 Note that this case is only used once per constant. */
1537 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1538 unsigned int cost, alt_cost;
1540 cost = mips_build_shift (codes, value);
1541 alt_cost = mips_build_lower (alt_codes, value);
1542 if (alt_cost < cost)
1544 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
1551 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
1554 mips_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
1556 return mips_const_insns (x) > 0;
1559 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
1562 mips16_stub_function (const char *name)
1566 x = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
1567 SYMBOL_REF_FLAGS (x) |= (SYMBOL_FLAG_EXTERNAL | SYMBOL_FLAG_FUNCTION);
1571 /* Return true if symbols of type TYPE require a GOT access. */
1574 mips_got_symbol_type_p (enum mips_symbol_type type)
1578 case SYMBOL_GOT_PAGE_OFST:
1579 case SYMBOL_GOT_DISP:
1587 /* Return true if X is a thread-local symbol. */
1590 mips_tls_symbol_p (rtx x)
1592 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1595 /* Return true if SYMBOL_REF X is associated with a global symbol
1596 (in the STB_GLOBAL sense). */
1599 mips_global_symbol_p (const_rtx x)
1601 const_tree decl = SYMBOL_REF_DECL (x);
1604 return !SYMBOL_REF_LOCAL_P (x) || SYMBOL_REF_EXTERNAL_P (x);
1606 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1607 or weak symbols. Relocations in the object file will be against
1608 the target symbol, so it's that symbol's binding that matters here. */
1609 return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl));
1612 /* Return true if function X is a libgcc MIPS16 stub function. */
1615 mips16_stub_function_p (const_rtx x)
1617 return (GET_CODE (x) == SYMBOL_REF
1618 && strncmp (XSTR (x, 0), "__mips16_", 9) == 0);
1621 /* Return true if function X is a locally-defined and locally-binding
1625 mips16_local_function_p (const_rtx x)
1627 return (GET_CODE (x) == SYMBOL_REF
1628 && SYMBOL_REF_LOCAL_P (x)
1629 && !SYMBOL_REF_EXTERNAL_P (x)
1630 && (mips_get_compress_mode (SYMBOL_REF_DECL (x)) & MASK_MIPS16));
1633 /* Return true if SYMBOL_REF X binds locally. */
1636 mips_symbol_binds_local_p (const_rtx x)
1638 return (SYMBOL_REF_DECL (x)
1639 ? targetm.binds_local_p (SYMBOL_REF_DECL (x))
1640 : SYMBOL_REF_LOCAL_P (x));
1643 /* Return true if rtx constants of mode MODE should be put into a small
1647 mips_rtx_constant_in_small_data_p (enum machine_mode mode)
1649 return (!TARGET_EMBEDDED_DATA
1650 && TARGET_LOCAL_SDATA
1651 && GET_MODE_SIZE (mode) <= mips_small_data_threshold);
1654 /* Return true if X should not be moved directly into register $25.
1655 We need this because many versions of GAS will treat "la $25,foo" as
1656 part of a call sequence and so allow a global "foo" to be lazily bound. */
1659 mips_dangerous_for_la25_p (rtx x)
1661 return (!TARGET_EXPLICIT_RELOCS
1663 && GET_CODE (x) == SYMBOL_REF
1664 && mips_global_symbol_p (x));
1667 /* Return true if calls to X might need $25 to be valid on entry. */
1670 mips_use_pic_fn_addr_reg_p (const_rtx x)
1672 if (!TARGET_USE_PIC_FN_ADDR_REG)
1675 /* MIPS16 stub functions are guaranteed not to use $25. */
1676 if (mips16_stub_function_p (x))
1679 if (GET_CODE (x) == SYMBOL_REF)
1681 /* If PLTs and copy relocations are available, the static linker
1682 will make sure that $25 is valid on entry to the target function. */
1683 if (TARGET_ABICALLS_PIC0)
1686 /* Locally-defined functions use absolute accesses to set up
1687 the global pointer. */
1688 if (TARGET_ABSOLUTE_ABICALLS
1689 && mips_symbol_binds_local_p (x)
1690 && !SYMBOL_REF_EXTERNAL_P (x))
1697 /* Return the method that should be used to access SYMBOL_REF or
1698 LABEL_REF X in context CONTEXT. */
1700 static enum mips_symbol_type
1701 mips_classify_symbol (const_rtx x, enum mips_symbol_context context)
1704 return SYMBOL_GOT_DISP;
1706 if (GET_CODE (x) == LABEL_REF)
1708 /* Only return SYMBOL_PC_RELATIVE if we are generating MIPS16
1709 code and if we know that the label is in the current function's
1710 text section. LABEL_REFs are used for jump tables as well as
1711 text labels, so we must check whether jump tables live in the
1713 if (TARGET_MIPS16_SHORT_JUMP_TABLES
1714 && !LABEL_REF_NONLOCAL_P (x))
1715 return SYMBOL_PC_RELATIVE;
1717 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1718 return SYMBOL_GOT_PAGE_OFST;
1720 return SYMBOL_ABSOLUTE;
1723 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1725 if (SYMBOL_REF_TLS_MODEL (x))
1728 if (CONSTANT_POOL_ADDRESS_P (x))
1730 if (TARGET_MIPS16_TEXT_LOADS)
1731 return SYMBOL_PC_RELATIVE;
1733 if (TARGET_MIPS16_PCREL_LOADS && context == SYMBOL_CONTEXT_MEM)
1734 return SYMBOL_PC_RELATIVE;
1736 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x)))
1737 return SYMBOL_GP_RELATIVE;
1740 /* Do not use small-data accesses for weak symbols; they may end up
1742 if (TARGET_GPOPT && SYMBOL_REF_SMALL_P (x) && !SYMBOL_REF_WEAK (x))
1743 return SYMBOL_GP_RELATIVE;
1745 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1747 if (TARGET_ABICALLS_PIC2
1748 && !(TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x)))
1750 /* There are three cases to consider:
1752 - o32 PIC (either with or without explicit relocs)
1753 - n32/n64 PIC without explicit relocs
1754 - n32/n64 PIC with explicit relocs
1756 In the first case, both local and global accesses will use an
1757 R_MIPS_GOT16 relocation. We must correctly predict which of
1758 the two semantics (local or global) the assembler and linker
1759 will apply. The choice depends on the symbol's binding rather
1760 than its visibility.
1762 In the second case, the assembler will not use R_MIPS_GOT16
1763 relocations, but it chooses between local and global accesses
1764 in the same way as for o32 PIC.
1766 In the third case we have more freedom since both forms of
1767 access will work for any kind of symbol. However, there seems
1768 little point in doing things differently. */
1769 if (mips_global_symbol_p (x))
1770 return SYMBOL_GOT_DISP;
1772 return SYMBOL_GOT_PAGE_OFST;
1775 return SYMBOL_ABSOLUTE;
1778 /* Classify the base of symbolic expression X, given that X appears in
1781 static enum mips_symbol_type
1782 mips_classify_symbolic_expression (rtx x, enum mips_symbol_context context)
1786 split_const (x, &x, &offset);
1787 if (UNSPEC_ADDRESS_P (x))
1788 return UNSPEC_ADDRESS_TYPE (x);
1790 return mips_classify_symbol (x, context);
1793 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1794 is the alignment in bytes of SYMBOL_REF X. */
1797 mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset)
1799 HOST_WIDE_INT align;
1801 align = SYMBOL_REF_DECL (x) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x)) : 1;
1802 return IN_RANGE (offset, 0, align - 1);
1805 /* Return true if X is a symbolic constant that can be used in context
1806 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1809 mips_symbolic_constant_p (rtx x, enum mips_symbol_context context,
1810 enum mips_symbol_type *symbol_type)
1814 split_const (x, &x, &offset);
1815 if (UNSPEC_ADDRESS_P (x))
1817 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1818 x = UNSPEC_ADDRESS (x);
1820 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1822 *symbol_type = mips_classify_symbol (x, context);
1823 if (*symbol_type == SYMBOL_TLS)
1829 if (offset == const0_rtx)
1832 /* Check whether a nonzero offset is valid for the underlying
1834 switch (*symbol_type)
1836 case SYMBOL_ABSOLUTE:
1837 case SYMBOL_64_HIGH:
1840 /* If the target has 64-bit pointers and the object file only
1841 supports 32-bit symbols, the values of those symbols will be
1842 sign-extended. In this case we can't allow an arbitrary offset
1843 in case the 32-bit value X + OFFSET has a different sign from X. */
1844 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1845 return offset_within_block_p (x, INTVAL (offset));
1847 /* In other cases the relocations can handle any offset. */
1850 case SYMBOL_PC_RELATIVE:
1851 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1852 In this case, we no longer have access to the underlying constant,
1853 but the original symbol-based access was known to be valid. */
1854 if (GET_CODE (x) == LABEL_REF)
1859 case SYMBOL_GP_RELATIVE:
1860 /* Make sure that the offset refers to something within the
1861 same object block. This should guarantee that the final
1862 PC- or GP-relative offset is within the 16-bit limit. */
1863 return offset_within_block_p (x, INTVAL (offset));
1865 case SYMBOL_GOT_PAGE_OFST:
1866 case SYMBOL_GOTOFF_PAGE:
1867 /* If the symbol is global, the GOT entry will contain the symbol's
1868 address, and we will apply a 16-bit offset after loading it.
1869 If the symbol is local, the linker should provide enough local
1870 GOT entries for a 16-bit offset, but larger offsets may lead
1872 return SMALL_INT (offset);
1876 /* There is no carry between the HI and LO REL relocations, so the
1877 offset is only valid if we know it won't lead to such a carry. */
1878 return mips_offset_within_alignment_p (x, INTVAL (offset));
1880 case SYMBOL_GOT_DISP:
1881 case SYMBOL_GOTOFF_DISP:
1882 case SYMBOL_GOTOFF_CALL:
1883 case SYMBOL_GOTOFF_LOADGP:
1886 case SYMBOL_GOTTPREL:
1894 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
1895 single instruction. We rely on the fact that, in the worst case,
1896 all instructions involved in a MIPS16 address calculation are usually
1900 mips_symbol_insns_1 (enum mips_symbol_type type, enum machine_mode mode)
1902 if (mips_use_pcrel_pool_p[(int) type])
1904 if (mode == MAX_MACHINE_MODE)
1905 /* LEAs will be converted into constant-pool references by
1907 type = SYMBOL_PC_RELATIVE;
1909 /* The constant must be loaded and then dereferenced. */
1915 case SYMBOL_ABSOLUTE:
1916 /* When using 64-bit symbols, we need 5 preparatory instructions,
1919 lui $at,%highest(symbol)
1920 daddiu $at,$at,%higher(symbol)
1922 daddiu $at,$at,%hi(symbol)
1925 The final address is then $at + %lo(symbol). With 32-bit
1926 symbols we just need a preparatory LUI for normal mode and
1927 a preparatory LI and SLL for MIPS16. */
1928 return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2;
1930 case SYMBOL_GP_RELATIVE:
1931 /* Treat GP-relative accesses as taking a single instruction on
1932 MIPS16 too; the copy of $gp can often be shared. */
1935 case SYMBOL_PC_RELATIVE:
1936 /* PC-relative constants can be only be used with ADDIUPC,
1937 DADDIUPC, LWPC and LDPC. */
1938 if (mode == MAX_MACHINE_MODE
1939 || GET_MODE_SIZE (mode) == 4
1940 || GET_MODE_SIZE (mode) == 8)
1943 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
1946 case SYMBOL_GOT_DISP:
1947 /* The constant will have to be loaded from the GOT before it
1948 is used in an address. */
1949 if (mode != MAX_MACHINE_MODE)
1954 case SYMBOL_GOT_PAGE_OFST:
1955 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
1956 local/global classification is accurate. The worst cases are:
1958 (1) For local symbols when generating o32 or o64 code. The assembler
1964 ...and the final address will be $at + %lo(symbol).
1966 (2) For global symbols when -mxgot. The assembler will use:
1968 lui $at,%got_hi(symbol)
1971 ...and the final address will be $at + %got_lo(symbol). */
1974 case SYMBOL_GOTOFF_PAGE:
1975 case SYMBOL_GOTOFF_DISP:
1976 case SYMBOL_GOTOFF_CALL:
1977 case SYMBOL_GOTOFF_LOADGP:
1978 case SYMBOL_64_HIGH:
1984 case SYMBOL_GOTTPREL:
1987 /* A 16-bit constant formed by a single relocation, or a 32-bit
1988 constant formed from a high 16-bit relocation and a low 16-bit
1989 relocation. Use mips_split_p to determine which. 32-bit
1990 constants need an "lui; addiu" sequence for normal mode and
1991 an "li; sll; addiu" sequence for MIPS16 mode. */
1992 return !mips_split_p[type] ? 1 : TARGET_MIPS16 ? 3 : 2;
1995 /* We don't treat a bare TLS symbol as a constant. */
2001 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
2002 to load symbols of type TYPE into a register. Return 0 if the given
2003 type of symbol cannot be used as an immediate operand.
2005 Otherwise, return the number of instructions needed to load or store
2006 values of mode MODE to or from addresses of type TYPE. Return 0 if
2007 the given type of symbol is not valid in addresses.
2009 In both cases, treat extended MIPS16 instructions as two instructions. */
2012 mips_symbol_insns (enum mips_symbol_type type, enum machine_mode mode)
2014 return mips_symbol_insns_1 (type, mode) * (TARGET_MIPS16 ? 2 : 1);
2017 /* A for_each_rtx callback. Stop the search if *X references a
2018 thread-local symbol. */
2021 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
2023 return mips_tls_symbol_p (*x);
2026 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
2029 mips_cannot_force_const_mem (enum machine_mode mode, rtx x)
2031 enum mips_symbol_type type;
2034 /* There is no assembler syntax for expressing an address-sized
2036 if (GET_CODE (x) == HIGH)
2039 /* As an optimization, reject constants that mips_legitimize_move
2042 Suppose we have a multi-instruction sequence that loads constant C
2043 into register R. If R does not get allocated a hard register, and
2044 R is used in an operand that allows both registers and memory
2045 references, reload will consider forcing C into memory and using
2046 one of the instruction's memory alternatives. Returning false
2047 here will force it to use an input reload instead. */
2048 if (CONST_INT_P (x) && mips_legitimate_constant_p (mode, x))
2051 split_const (x, &base, &offset);
2052 if (mips_symbolic_constant_p (base, SYMBOL_CONTEXT_LEA, &type))
2054 /* See whether we explicitly want these symbols in the pool. */
2055 if (mips_use_pcrel_pool_p[(int) type])
2058 /* The same optimization as for CONST_INT. */
2059 if (SMALL_INT (offset) && mips_symbol_insns (type, MAX_MACHINE_MODE) > 0)
2062 /* If MIPS16 constant pools live in the text section, they should
2063 not refer to anything that might need run-time relocation. */
2064 if (TARGET_MIPS16_PCREL_LOADS && mips_got_symbol_type_p (type))
2068 /* TLS symbols must be computed by mips_legitimize_move. */
2069 if (for_each_rtx (&x, &mips_tls_symbol_ref_1, NULL))
2075 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
2076 constants when we're using a per-function constant pool. */
2079 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
2080 const_rtx x ATTRIBUTE_UNUSED)
2082 return !TARGET_MIPS16_PCREL_LOADS;
2085 /* Return true if register REGNO is a valid base register for mode MODE.
2086 STRICT_P is true if REG_OK_STRICT is in effect. */
2089 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode,
2092 if (!HARD_REGISTER_NUM_P (regno))
2096 regno = reg_renumber[regno];
2099 /* These fake registers will be eliminated to either the stack or
2100 hard frame pointer, both of which are usually valid base registers.
2101 Reload deals with the cases where the eliminated form isn't valid. */
2102 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
2105 /* In MIPS16 mode, the stack pointer can only address word and doubleword
2106 values, nothing smaller. There are two problems here:
2108 (a) Instantiating virtual registers can introduce new uses of the
2109 stack pointer. If these virtual registers are valid addresses,
2110 the stack pointer should be too.
2112 (b) Most uses of the stack pointer are not made explicit until
2113 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
2114 We don't know until that stage whether we'll be eliminating to the
2115 stack pointer (which needs the restriction) or the hard frame
2116 pointer (which doesn't).
2118 All in all, it seems more consistent to only enforce this restriction
2119 during and after reload. */
2120 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
2121 return !strict_p || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
2123 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
2126 /* Return true if X is a valid base register for mode MODE.
2127 STRICT_P is true if REG_OK_STRICT is in effect. */
2130 mips_valid_base_register_p (rtx x, enum machine_mode mode, bool strict_p)
2132 if (!strict_p && GET_CODE (x) == SUBREG)
2136 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p));
2139 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2140 can address a value of mode MODE. */
2143 mips_valid_offset_p (rtx x, enum machine_mode mode)
2145 /* Check that X is a signed 16-bit number. */
2146 if (!const_arith_operand (x, Pmode))
2149 /* We may need to split multiword moves, so make sure that every word
2151 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2152 && !SMALL_OPERAND (INTVAL (x) + GET_MODE_SIZE (mode) - UNITS_PER_WORD))
2158 /* Return true if a LO_SUM can address a value of mode MODE when the
2159 LO_SUM symbol has type SYMBOL_TYPE. */
2162 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type, enum machine_mode mode)
2164 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2166 if (mips_symbol_insns (symbol_type, mode) == 0)
2169 /* Check that there is a known low-part relocation. */
2170 if (mips_lo_relocs[symbol_type] == NULL)
2173 /* We may need to split multiword moves, so make sure that each word
2174 can be accessed without inducing a carry. This is mainly needed
2175 for o64, which has historically only guaranteed 64-bit alignment
2176 for 128-bit types. */
2177 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2178 && GET_MODE_BITSIZE (mode) > GET_MODE_ALIGNMENT (mode))
2184 /* Return true if X is a valid address for machine mode MODE. If it is,
2185 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2189 mips_classify_address (struct mips_address_info *info, rtx x,
2190 enum machine_mode mode, bool strict_p)
2192 switch (GET_CODE (x))
2196 info->type = ADDRESS_REG;
2198 info->offset = const0_rtx;
2199 return mips_valid_base_register_p (info->reg, mode, strict_p);
2202 info->type = ADDRESS_REG;
2203 info->reg = XEXP (x, 0);
2204 info->offset = XEXP (x, 1);
2205 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2206 && mips_valid_offset_p (info->offset, mode));
2209 info->type = ADDRESS_LO_SUM;
2210 info->reg = XEXP (x, 0);
2211 info->offset = XEXP (x, 1);
2212 /* We have to trust the creator of the LO_SUM to do something vaguely
2213 sane. Target-independent code that creates a LO_SUM should also
2214 create and verify the matching HIGH. Target-independent code that
2215 adds an offset to a LO_SUM must prove that the offset will not
2216 induce a carry. Failure to do either of these things would be
2217 a bug, and we are not required to check for it here. The MIPS
2218 backend itself should only create LO_SUMs for valid symbolic
2219 constants, with the high part being either a HIGH or a copy
2222 = mips_classify_symbolic_expression (info->offset, SYMBOL_CONTEXT_MEM);
2223 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2224 && mips_valid_lo_sum_p (info->symbol_type, mode));
2227 /* Small-integer addresses don't occur very often, but they
2228 are legitimate if $0 is a valid base register. */
2229 info->type = ADDRESS_CONST_INT;
2230 return !TARGET_MIPS16 && SMALL_INT (x);
2235 info->type = ADDRESS_SYMBOLIC;
2236 return (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_MEM,
2238 && mips_symbol_insns (info->symbol_type, mode) > 0
2239 && !mips_split_p[info->symbol_type]);
2246 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2249 mips_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
2251 struct mips_address_info addr;
2253 return mips_classify_address (&addr, x, mode, strict_p);
2256 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
2259 mips_stack_address_p (rtx x, enum machine_mode mode)
2261 struct mips_address_info addr;
2263 return (mips_classify_address (&addr, x, mode, false)
2264 && addr.type == ADDRESS_REG
2265 && addr.reg == stack_pointer_rtx);
2268 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2269 address instruction. Note that such addresses are not considered
2270 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2271 is so restricted. */
2274 mips_lwxs_address_p (rtx addr)
2277 && GET_CODE (addr) == PLUS
2278 && REG_P (XEXP (addr, 1)))
2280 rtx offset = XEXP (addr, 0);
2281 if (GET_CODE (offset) == MULT
2282 && REG_P (XEXP (offset, 0))
2283 && CONST_INT_P (XEXP (offset, 1))
2284 && INTVAL (XEXP (offset, 1)) == 4)
2290 /* Return true if ADDR matches the pattern for the L{B,H,W,D}{,U}X load
2291 indexed address instruction. Note that such addresses are
2292 not considered legitimate in the TARGET_LEGITIMATE_ADDRESS_P
2293 sense, because their use is so restricted. */
2296 mips_lx_address_p (rtx addr, enum machine_mode mode)
2298 if (GET_CODE (addr) != PLUS
2299 || !REG_P (XEXP (addr, 0))
2300 || !REG_P (XEXP (addr, 1)))
2302 if (ISA_HAS_LBX && mode == QImode)
2304 if (ISA_HAS_LHX && mode == HImode)
2306 if (ISA_HAS_LWX && mode == SImode)
2308 if (ISA_HAS_LDX && mode == DImode)
2313 /* Return true if a value at OFFSET bytes from base register BASE can be
2314 accessed using an unextended MIPS16 instruction. MODE is the mode of
2317 Usually the offset in an unextended instruction is a 5-bit field.
2318 The offset is unsigned and shifted left once for LH and SH, twice
2319 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2320 an 8-bit immediate field that's shifted left twice. */
2323 mips16_unextended_reference_p (enum machine_mode mode, rtx base,
2324 unsigned HOST_WIDE_INT offset)
2326 if (mode != BLKmode && offset % GET_MODE_SIZE (mode) == 0)
2328 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
2329 return offset < 256U * GET_MODE_SIZE (mode);
2330 return offset < 32U * GET_MODE_SIZE (mode);
2335 /* Return the number of instructions needed to load or store a value
2336 of mode MODE at address X. Return 0 if X isn't valid for MODE.
2337 Assume that multiword moves may need to be split into word moves
2338 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2341 For MIPS16 code, count extended instructions as two instructions. */
2344 mips_address_insns (rtx x, enum machine_mode mode, bool might_split_p)
2346 struct mips_address_info addr;
2349 /* BLKmode is used for single unaligned loads and stores and should
2350 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2351 meaningless, so we have to single it out as a special case one way
2353 if (mode != BLKmode && might_split_p)
2354 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2358 if (mips_classify_address (&addr, x, mode, false))
2363 && !mips16_unextended_reference_p (mode, addr.reg,
2364 UINTVAL (addr.offset)))
2368 case ADDRESS_LO_SUM:
2369 return TARGET_MIPS16 ? factor * 2 : factor;
2371 case ADDRESS_CONST_INT:
2374 case ADDRESS_SYMBOLIC:
2375 return factor * mips_symbol_insns (addr.symbol_type, mode);
2380 /* Return true if X fits within an unsigned field of BITS bits that is
2381 shifted left SHIFT bits before being used. */
2384 mips_unsigned_immediate_p (unsigned HOST_WIDE_INT x, int bits, int shift = 0)
2386 return (x & ((1 << shift) - 1)) == 0 && x < ((unsigned) 1 << (shift + bits));
2389 /* Return true if X fits within a signed field of BITS bits that is
2390 shifted left SHIFT bits before being used. */
2393 mips_signed_immediate_p (unsigned HOST_WIDE_INT x, int bits, int shift = 0)
2395 x += 1 << (bits + shift - 1);
2396 return mips_unsigned_immediate_p (x, bits, shift);
2399 /* Return true if X is legitimate for accessing values of mode MODE,
2400 if it is based on a MIPS16 register, and if the offset satisfies
2401 OFFSET_PREDICATE. */
2404 m16_based_address_p (rtx x, enum machine_mode mode,
2405 insn_operand_predicate_fn offset_predicate)
2407 struct mips_address_info addr;
2409 return (mips_classify_address (&addr, x, mode, false)
2410 && addr.type == ADDRESS_REG
2411 && M16_REG_P (REGNO (addr.reg))
2412 && offset_predicate (addr.offset, mode));
2415 /* Return true if X is a legitimate address that conforms to the requirements
2416 for a microMIPS LWSP or SWSP insn. */
2419 lwsp_swsp_address_p (rtx x, enum machine_mode mode)
2421 struct mips_address_info addr;
2423 return (mips_classify_address (&addr, x, mode, false)
2424 && addr.type == ADDRESS_REG
2425 && REGNO (addr.reg) == STACK_POINTER_REGNUM
2426 && uw5_operand (addr.offset, mode));
2429 /* Return true if X is a legitimate address with a 12-bit offset.
2430 MODE is the mode of the value being accessed. */
2433 umips_12bit_offset_address_p (rtx x, enum machine_mode mode)
2435 struct mips_address_info addr;
2437 return (mips_classify_address (&addr, x, mode, false)
2438 && addr.type == ADDRESS_REG
2439 && CONST_INT_P (addr.offset)
2440 && UMIPS_12BIT_OFFSET_P (INTVAL (addr.offset)));
2443 /* Return the number of instructions needed to load constant X.
2444 Return 0 if X isn't a valid constant. */
2447 mips_const_insns (rtx x)
2449 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2450 enum mips_symbol_type symbol_type;
2453 switch (GET_CODE (x))
2456 if (!mips_symbolic_constant_p (XEXP (x, 0), SYMBOL_CONTEXT_LEA,
2458 || !mips_split_p[symbol_type])
2461 /* This is simply an LUI for normal mode. It is an extended
2462 LI followed by an extended SLL for MIPS16. */
2463 return TARGET_MIPS16 ? 4 : 1;
2467 /* Unsigned 8-bit constants can be loaded using an unextended
2468 LI instruction. Unsigned 16-bit constants can be loaded
2469 using an extended LI. Negative constants must be loaded
2470 using LI and then negated. */
2471 return (IN_RANGE (INTVAL (x), 0, 255) ? 1
2472 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
2473 : IN_RANGE (-INTVAL (x), 0, 255) ? 2
2474 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
2477 return mips_build_integer (codes, INTVAL (x));
2481 /* Allow zeros for normal mode, where we can use $0. */
2482 return !TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0;
2488 /* See if we can refer to X directly. */
2489 if (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_LEA, &symbol_type))
2490 return mips_symbol_insns (symbol_type, MAX_MACHINE_MODE);
2492 /* Otherwise try splitting the constant into a base and offset.
2493 If the offset is a 16-bit value, we can load the base address
2494 into a register and then use (D)ADDIU to add in the offset.
2495 If the offset is larger, we can load the base and offset
2496 into separate registers and add them together with (D)ADDU.
2497 However, the latter is only possible before reload; during
2498 and after reload, we must have the option of forcing the
2499 constant into the pool instead. */
2500 split_const (x, &x, &offset);
2503 int n = mips_const_insns (x);
2506 if (SMALL_INT (offset))
2508 else if (!targetm.cannot_force_const_mem (GET_MODE (x), x))
2509 return n + 1 + mips_build_integer (codes, INTVAL (offset));
2516 return mips_symbol_insns (mips_classify_symbol (x, SYMBOL_CONTEXT_LEA),
2524 /* X is a doubleword constant that can be handled by splitting it into
2525 two words and loading each word separately. Return the number of
2526 instructions required to do this. */
2529 mips_split_const_insns (rtx x)
2531 unsigned int low, high;
2533 low = mips_const_insns (mips_subword (x, false));
2534 high = mips_const_insns (mips_subword (x, true));
2535 gcc_assert (low > 0 && high > 0);
2539 /* Return the number of instructions needed to implement INSN,
2540 given that it loads from or stores to MEM. Count extended
2541 MIPS16 instructions as two instructions. */
2544 mips_load_store_insns (rtx mem, rtx insn)
2546 enum machine_mode mode;
2550 gcc_assert (MEM_P (mem));
2551 mode = GET_MODE (mem);
2553 /* Try to prove that INSN does not need to be split. */
2554 might_split_p = GET_MODE_SIZE (mode) > UNITS_PER_WORD;
2557 set = single_set (insn);
2558 if (set && !mips_split_move_insn_p (SET_DEST (set), SET_SRC (set), insn))
2559 might_split_p = false;
2562 return mips_address_insns (XEXP (mem, 0), mode, might_split_p);
2565 /* Return the number of instructions needed for an integer division. */
2568 mips_idiv_insns (void)
2573 if (TARGET_CHECK_ZERO_DIV)
2575 if (GENERATE_DIVIDE_TRAPS)
2581 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
2586 /* Emit a move from SRC to DEST. Assume that the move expanders can
2587 handle all moves if !can_create_pseudo_p (). The distinction is
2588 important because, unlike emit_move_insn, the move expanders know
2589 how to force Pmode objects into the constant pool even when the
2590 constant pool address is not itself legitimate. */
2593 mips_emit_move (rtx dest, rtx src)
2595 return (can_create_pseudo_p ()
2596 ? emit_move_insn (dest, src)
2597 : emit_move_insn_1 (dest, src));
2600 /* Emit a move from SRC to DEST, splitting compound moves into individual
2601 instructions. SPLIT_TYPE is the type of split to perform. */
2604 mips_emit_move_or_split (rtx dest, rtx src, enum mips_split_type split_type)
2606 if (mips_split_move_p (dest, src, split_type))
2607 mips_split_move (dest, src, split_type);
2609 mips_emit_move (dest, src);
2612 /* Emit an instruction of the form (set TARGET (CODE OP0)). */
2615 mips_emit_unary (enum rtx_code code, rtx target, rtx op0)
2617 emit_insn (gen_rtx_SET (VOIDmode, target,
2618 gen_rtx_fmt_e (code, GET_MODE (op0), op0)));
2621 /* Compute (CODE OP0) and store the result in a new register of mode MODE.
2622 Return that new register. */
2625 mips_force_unary (enum machine_mode mode, enum rtx_code code, rtx op0)
2629 reg = gen_reg_rtx (mode);
2630 mips_emit_unary (code, reg, op0);
2634 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2637 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
2639 emit_insn (gen_rtx_SET (VOIDmode, target,
2640 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
2643 /* Compute (CODE OP0 OP1) and store the result in a new register
2644 of mode MODE. Return that new register. */
2647 mips_force_binary (enum machine_mode mode, enum rtx_code code, rtx op0, rtx op1)
2651 reg = gen_reg_rtx (mode);
2652 mips_emit_binary (code, reg, op0, op1);
2656 /* Copy VALUE to a register and return that register. If new pseudos
2657 are allowed, copy it into a new register, otherwise use DEST. */
2660 mips_force_temporary (rtx dest, rtx value)
2662 if (can_create_pseudo_p ())
2663 return force_reg (Pmode, value);
2666 mips_emit_move (dest, value);
2671 /* Emit a call sequence with call pattern PATTERN and return the call
2672 instruction itself (which is not necessarily the last instruction
2673 emitted). ORIG_ADDR is the original, unlegitimized address,
2674 ADDR is the legitimized form, and LAZY_P is true if the call
2675 address is lazily-bound. */
2678 mips_emit_call_insn (rtx pattern, rtx orig_addr, rtx addr, bool lazy_p)
2682 insn = emit_call_insn (pattern);
2684 if (TARGET_MIPS16 && mips_use_pic_fn_addr_reg_p (orig_addr))
2686 /* MIPS16 JALRs only take MIPS16 registers. If the target
2687 function requires $25 to be valid on entry, we must copy it
2688 there separately. The move instruction can be put in the
2689 call's delay slot. */
2690 reg = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
2691 emit_insn_before (gen_move_insn (reg, addr), insn);
2692 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
2696 /* Lazy-binding stubs require $gp to be valid on entry. */
2697 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
2701 /* See the comment above load_call<mode> for details. */
2702 use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
2703 gen_rtx_REG (Pmode, GOT_VERSION_REGNUM));
2704 emit_insn (gen_update_got_version ());
2709 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2710 then add CONST_INT OFFSET to the result. */
2713 mips_unspec_address_offset (rtx base, rtx offset,
2714 enum mips_symbol_type symbol_type)
2716 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
2717 UNSPEC_ADDRESS_FIRST + symbol_type);
2718 if (offset != const0_rtx)
2719 base = gen_rtx_PLUS (Pmode, base, offset);
2720 return gen_rtx_CONST (Pmode, base);
2723 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2724 type SYMBOL_TYPE. */
2727 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
2731 split_const (address, &base, &offset);
2732 return mips_unspec_address_offset (base, offset, symbol_type);
2735 /* If OP is an UNSPEC address, return the address to which it refers,
2736 otherwise return OP itself. */
2739 mips_strip_unspec_address (rtx op)
2743 split_const (op, &base, &offset);
2744 if (UNSPEC_ADDRESS_P (base))
2745 op = plus_constant (Pmode, UNSPEC_ADDRESS (base), INTVAL (offset));
2749 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2750 high part to BASE and return the result. Just return BASE otherwise.
2751 TEMP is as for mips_force_temporary.
2753 The returned expression can be used as the first operand to a LO_SUM. */
2756 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
2757 enum mips_symbol_type symbol_type)
2759 if (mips_split_p[symbol_type])
2761 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
2762 addr = mips_force_temporary (temp, addr);
2763 base = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
2768 /* Return an instruction that copies $gp into register REG. We want
2769 GCC to treat the register's value as constant, so that its value
2770 can be rematerialized on demand. */
2773 gen_load_const_gp (rtx reg)
2775 return PMODE_INSN (gen_load_const_gp, (reg));
2778 /* Return a pseudo register that contains the value of $gp throughout
2779 the current function. Such registers are needed by MIPS16 functions,
2780 for which $gp itself is not a valid base register or addition operand. */
2783 mips16_gp_pseudo_reg (void)
2785 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
2789 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
2791 push_topmost_sequence ();
2793 scan = get_insns ();
2794 while (NEXT_INSN (scan) && !INSN_P (NEXT_INSN (scan)))
2795 scan = NEXT_INSN (scan);
2797 insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
2798 insn = emit_insn_after (insn, scan);
2799 INSN_LOCATION (insn) = 0;
2801 pop_topmost_sequence ();
2804 return cfun->machine->mips16_gp_pseudo_rtx;
2807 /* Return a base register that holds pic_offset_table_rtx.
2808 TEMP, if nonnull, is a scratch Pmode base register. */
2811 mips_pic_base_register (rtx temp)
2814 return pic_offset_table_rtx;
2816 if (currently_expanding_to_rtl)
2817 return mips16_gp_pseudo_reg ();
2819 if (can_create_pseudo_p ())
2820 temp = gen_reg_rtx (Pmode);
2823 /* The first post-reload split exposes all references to $gp
2824 (both uses and definitions). All references must remain
2825 explicit after that point.
2827 It is safe to introduce uses of $gp at any time, so for
2828 simplicity, we do that before the split too. */
2829 mips_emit_move (temp, pic_offset_table_rtx);
2831 emit_insn (gen_load_const_gp (temp));
2835 /* Return the RHS of a load_call<mode> insn. */
2838 mips_unspec_call (rtx reg, rtx symbol)
2842 vec = gen_rtvec (3, reg, symbol, gen_rtx_REG (SImode, GOT_VERSION_REGNUM));
2843 return gen_rtx_UNSPEC (Pmode, vec, UNSPEC_LOAD_CALL);
2846 /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol
2847 reference. Return NULL_RTX otherwise. */
2850 mips_strip_unspec_call (rtx src)
2852 if (GET_CODE (src) == UNSPEC && XINT (src, 1) == UNSPEC_LOAD_CALL)
2853 return mips_strip_unspec_address (XVECEXP (src, 0, 1));
2857 /* Create and return a GOT reference of type TYPE for address ADDR.
2858 TEMP, if nonnull, is a scratch Pmode base register. */
2861 mips_got_load (rtx temp, rtx addr, enum mips_symbol_type type)
2863 rtx base, high, lo_sum_symbol;
2865 base = mips_pic_base_register (temp);
2867 /* If we used the temporary register to load $gp, we can't use
2868 it for the high part as well. */
2869 if (temp != NULL && reg_overlap_mentioned_p (base, temp))
2872 high = mips_unspec_offset_high (temp, base, addr, type);
2873 lo_sum_symbol = mips_unspec_address (addr, type);
2875 if (type == SYMBOL_GOTOFF_CALL)
2876 return mips_unspec_call (high, lo_sum_symbol);
2878 return PMODE_INSN (gen_unspec_got, (high, lo_sum_symbol));
2881 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2882 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2883 constant in that context and can be split into high and low parts.
2884 If so, and if LOW_OUT is nonnull, emit the high part and store the
2885 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
2887 TEMP is as for mips_force_temporary and is used to load the high
2888 part into a register.
2890 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
2891 a legitimize SET_SRC for an .md pattern, otherwise the low part
2892 is guaranteed to be a legitimate address for mode MODE. */
2895 mips_split_symbol (rtx temp, rtx addr, enum machine_mode mode, rtx *low_out)
2897 enum mips_symbol_context context;
2898 enum mips_symbol_type symbol_type;
2901 context = (mode == MAX_MACHINE_MODE
2902 ? SYMBOL_CONTEXT_LEA
2903 : SYMBOL_CONTEXT_MEM);
2904 if (GET_CODE (addr) == HIGH && context == SYMBOL_CONTEXT_LEA)
2906 addr = XEXP (addr, 0);
2907 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2908 && mips_symbol_insns (symbol_type, mode) > 0
2909 && mips_split_hi_p[symbol_type])
2912 switch (symbol_type)
2914 case SYMBOL_GOT_PAGE_OFST:
2915 /* The high part of a page/ofst pair is loaded from the GOT. */
2916 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_PAGE);
2927 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2928 && mips_symbol_insns (symbol_type, mode) > 0
2929 && mips_split_p[symbol_type])
2932 switch (symbol_type)
2934 case SYMBOL_GOT_DISP:
2935 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
2936 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_DISP);
2939 case SYMBOL_GP_RELATIVE:
2940 high = mips_pic_base_register (temp);
2941 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2945 high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
2946 high = mips_force_temporary (temp, high);
2947 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2956 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2957 mips_force_temporary; it is only needed when OFFSET is not a
2961 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
2963 if (!SMALL_OPERAND (offset))
2969 /* Load the full offset into a register so that we can use
2970 an unextended instruction for the address itself. */
2971 high = GEN_INT (offset);
2976 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
2977 The addition inside the macro CONST_HIGH_PART may cause an
2978 overflow, so we need to force a sign-extension check. */
2979 high = gen_int_mode (CONST_HIGH_PART (offset), Pmode);
2980 offset = CONST_LOW_PART (offset);
2982 high = mips_force_temporary (temp, high);
2983 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
2985 return plus_constant (Pmode, reg, offset);
2988 /* The __tls_get_attr symbol. */
2989 static GTY(()) rtx mips_tls_symbol;
2991 /* Return an instruction sequence that calls __tls_get_addr. SYM is
2992 the TLS symbol we are referencing and TYPE is the symbol type to use
2993 (either global dynamic or local dynamic). V0 is an RTX for the
2994 return value location. */
2997 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
3001 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
3003 if (!mips_tls_symbol)
3004 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
3006 loc = mips_unspec_address (sym, type);
3010 emit_insn (gen_rtx_SET (Pmode, a0,
3011 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
3012 insn = mips_expand_call (MIPS_CALL_NORMAL, v0, mips_tls_symbol,
3013 const0_rtx, NULL_RTX, false);
3014 RTL_CONST_CALL_P (insn) = 1;
3015 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
3016 insn = get_insns ();
3023 /* Return a pseudo register that contains the current thread pointer. */
3026 mips_expand_thread_pointer (rtx tp)
3032 mips_need_mips16_rdhwr_p = true;
3033 fn = mips16_stub_function ("__mips16_rdhwr");
3034 SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_LOCAL;
3035 if (!call_insn_operand (fn, VOIDmode))
3036 fn = force_reg (Pmode, fn);
3037 emit_insn (PMODE_INSN (gen_tls_get_tp_mips16, (tp, fn)));
3040 emit_insn (PMODE_INSN (gen_tls_get_tp, (tp)));
3047 return mips_expand_thread_pointer (gen_reg_rtx (Pmode));
3050 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
3051 its address. The return value will be both a valid address and a valid
3052 SET_SRC (either a REG or a LO_SUM). */
3055 mips_legitimize_tls_address (rtx loc)
3057 rtx dest, insn, v0, tp, tmp1, tmp2, eqv, offset;
3058 enum tls_model model;
3060 model = SYMBOL_REF_TLS_MODEL (loc);
3061 /* Only TARGET_ABICALLS code can have more than one module; other
3062 code must be be static and should not use a GOT. All TLS models
3063 reduce to local exec in this situation. */
3064 if (!TARGET_ABICALLS)
3065 model = TLS_MODEL_LOCAL_EXEC;
3069 case TLS_MODEL_GLOBAL_DYNAMIC:
3070 v0 = gen_rtx_REG (Pmode, GP_RETURN);
3071 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
3072 dest = gen_reg_rtx (Pmode);
3073 emit_libcall_block (insn, dest, v0, loc);
3076 case TLS_MODEL_LOCAL_DYNAMIC:
3077 v0 = gen_rtx_REG (Pmode, GP_RETURN);
3078 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
3079 tmp1 = gen_reg_rtx (Pmode);
3081 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
3082 share the LDM result with other LD model accesses. */
3083 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3085 emit_libcall_block (insn, tmp1, v0, eqv);
3087 offset = mips_unspec_address (loc, SYMBOL_DTPREL);
3088 if (mips_split_p[SYMBOL_DTPREL])
3090 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
3091 dest = gen_rtx_LO_SUM (Pmode, tmp2, offset);
3094 dest = expand_binop (Pmode, add_optab, tmp1, offset,
3095 0, 0, OPTAB_DIRECT);
3098 case TLS_MODEL_INITIAL_EXEC:
3099 tp = mips_get_tp ();
3100 tmp1 = gen_reg_rtx (Pmode);
3101 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
3102 if (Pmode == DImode)
3103 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
3105 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
3106 dest = gen_reg_rtx (Pmode);
3107 emit_insn (gen_add3_insn (dest, tmp1, tp));
3110 case TLS_MODEL_LOCAL_EXEC:
3111 tmp1 = mips_get_tp ();
3112 offset = mips_unspec_address (loc, SYMBOL_TPREL);
3113 if (mips_split_p[SYMBOL_TPREL])
3115 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_TPREL);
3116 dest = gen_rtx_LO_SUM (Pmode, tmp2, offset);
3119 dest = expand_binop (Pmode, add_optab, tmp1, offset,
3120 0, 0, OPTAB_DIRECT);
3129 /* If X is not a valid address for mode MODE, force it into a register. */
3132 mips_force_address (rtx x, enum machine_mode mode)
3134 if (!mips_legitimate_address_p (mode, x, false))
3135 x = force_reg (Pmode, x);
3139 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
3140 be legitimized in a way that the generic machinery might not expect,
3141 return a new address, otherwise return NULL. MODE is the mode of
3142 the memory being accessed. */
3145 mips_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3146 enum machine_mode mode)
3149 HOST_WIDE_INT offset;
3151 if (mips_tls_symbol_p (x))
3152 return mips_legitimize_tls_address (x);
3154 /* See if the address can split into a high part and a LO_SUM. */
3155 if (mips_split_symbol (NULL, x, mode, &addr))
3156 return mips_force_address (addr, mode);
3158 /* Handle BASE + OFFSET using mips_add_offset. */
3159 mips_split_plus (x, &base, &offset);
3162 if (!mips_valid_base_register_p (base, mode, false))
3163 base = copy_to_mode_reg (Pmode, base);
3164 addr = mips_add_offset (NULL, base, offset);
3165 return mips_force_address (addr, mode);
3171 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
3174 mips_move_integer (rtx temp, rtx dest, unsigned HOST_WIDE_INT value)
3176 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
3177 enum machine_mode mode;
3178 unsigned int i, num_ops;
3181 mode = GET_MODE (dest);
3182 num_ops = mips_build_integer (codes, value);
3184 /* Apply each binary operation to X. Invariant: X is a legitimate
3185 source operand for a SET pattern. */
3186 x = GEN_INT (codes[0].value);
3187 for (i = 1; i < num_ops; i++)
3189 if (!can_create_pseudo_p ())
3191 emit_insn (gen_rtx_SET (VOIDmode, temp, x));
3195 x = force_reg (mode, x);
3196 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
3199 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
3202 /* Subroutine of mips_legitimize_move. Move constant SRC into register
3203 DEST given that SRC satisfies immediate_operand but doesn't satisfy
3207 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
3211 /* Split moves of big integers into smaller pieces. */
3212 if (splittable_const_int_operand (src, mode))
3214 mips_move_integer (dest, dest, INTVAL (src));
3218 /* Split moves of symbolic constants into high/low pairs. */
3219 if (mips_split_symbol (dest, src, MAX_MACHINE_MODE, &src))
3221 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
3225 /* Generate the appropriate access sequences for TLS symbols. */
3226 if (mips_tls_symbol_p (src))
3228 mips_emit_move (dest, mips_legitimize_tls_address (src));
3232 /* If we have (const (plus symbol offset)), and that expression cannot
3233 be forced into memory, load the symbol first and add in the offset.
3234 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
3235 forced into memory, as it usually produces better code. */
3236 split_const (src, &base, &offset);
3237 if (offset != const0_rtx
3238 && (targetm.cannot_force_const_mem (mode, src)
3239 || (!TARGET_MIPS16 && can_create_pseudo_p ())))
3241 base = mips_force_temporary (dest, base);
3242 mips_emit_move (dest, mips_add_offset (NULL, base, INTVAL (offset)));
3246 src = force_const_mem (mode, src);
3248 /* When using explicit relocs, constant pool references are sometimes
3249 not legitimate addresses. */
3250 mips_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0));
3251 mips_emit_move (dest, src);
3254 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
3255 sequence that is valid. */
3258 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
3260 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
3262 mips_emit_move (dest, force_reg (mode, src));
3266 /* We need to deal with constants that would be legitimate
3267 immediate_operands but aren't legitimate move_operands. */
3268 if (CONSTANT_P (src) && !move_operand (src, mode))
3270 mips_legitimize_const_move (mode, dest, src);
3271 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
3277 /* Return true if value X in context CONTEXT is a small-data address
3278 that can be rewritten as a LO_SUM. */
3281 mips_rewrite_small_data_p (rtx x, enum mips_symbol_context context)
3283 enum mips_symbol_type symbol_type;
3285 return (mips_lo_relocs[SYMBOL_GP_RELATIVE]
3286 && !mips_split_p[SYMBOL_GP_RELATIVE]
3287 && mips_symbolic_constant_p (x, context, &symbol_type)
3288 && symbol_type == SYMBOL_GP_RELATIVE);
3291 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
3292 containing MEM, or null if none. */
3295 mips_small_data_pattern_1 (rtx *loc, void *data)
3297 enum mips_symbol_context context;
3299 /* Ignore things like "g" constraints in asms. We make no particular
3300 guarantee about which symbolic constants are acceptable as asm operands
3301 versus which must be forced into a GPR. */
3302 if (GET_CODE (*loc) == LO_SUM || GET_CODE (*loc) == ASM_OPERANDS)
3307 if (for_each_rtx (&XEXP (*loc, 0), mips_small_data_pattern_1, *loc))
3312 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3313 return mips_rewrite_small_data_p (*loc, context);
3316 /* Return true if OP refers to small data symbols directly, not through
3320 mips_small_data_pattern_p (rtx op)
3322 return for_each_rtx (&op, mips_small_data_pattern_1, NULL);
3325 /* A for_each_rtx callback, used by mips_rewrite_small_data.
3326 DATA is the containing MEM, or null if none. */
3329 mips_rewrite_small_data_1 (rtx *loc, void *data)
3331 enum mips_symbol_context context;
3335 for_each_rtx (&XEXP (*loc, 0), mips_rewrite_small_data_1, *loc);
3339 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3340 if (mips_rewrite_small_data_p (*loc, context))
3341 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
3343 if (GET_CODE (*loc) == LO_SUM)
3349 /* Rewrite instruction pattern PATTERN so that it refers to small data
3350 using explicit relocations. */
3353 mips_rewrite_small_data (rtx pattern)
3355 pattern = copy_insn (pattern);
3356 for_each_rtx (&pattern, mips_rewrite_small_data_1, NULL);
3360 /* We need a lot of little routines to check the range of MIPS16 immediate
3364 m16_check_op (rtx op, int low, int high, int mask)
3366 return (CONST_INT_P (op)
3367 && IN_RANGE (INTVAL (op), low, high)
3368 && (INTVAL (op) & mask) == 0);
3372 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3374 return m16_check_op (op, 0x1, 0x8, 0);
3378 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3380 return m16_check_op (op, -0x8, 0x7, 0);
3384 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3386 return m16_check_op (op, -0x7, 0x8, 0);
3390 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3392 return m16_check_op (op, -0x10, 0xf, 0);
3396 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3398 return m16_check_op (op, -0xf, 0x10, 0);
3402 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3404 return m16_check_op (op, -0x10 << 2, 0xf << 2, 3);
3408 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3410 return m16_check_op (op, -0xf << 2, 0x10 << 2, 3);
3414 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3416 return m16_check_op (op, -0x80, 0x7f, 0);
3420 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3422 return m16_check_op (op, -0x7f, 0x80, 0);
3426 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3428 return m16_check_op (op, 0x0, 0xff, 0);
3432 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3434 return m16_check_op (op, -0xff, 0x0, 0);
3438 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3440 return m16_check_op (op, -0x1, 0xfe, 0);
3444 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3446 return m16_check_op (op, 0x0, 0xff << 2, 3);
3450 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3452 return m16_check_op (op, -0xff << 2, 0x0, 3);
3456 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3458 return m16_check_op (op, -0x80 << 3, 0x7f << 3, 7);
3462 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3464 return m16_check_op (op, -0x7f << 3, 0x80 << 3, 7);
3467 /* The cost of loading values from the constant pool. It should be
3468 larger than the cost of any constant we want to synthesize inline. */
3469 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3471 /* Return the cost of X when used as an operand to the MIPS16 instruction
3472 that implements CODE. Return -1 if there is no such instruction, or if
3473 X is not a valid immediate operand for it. */
3476 mips16_constant_cost (int code, HOST_WIDE_INT x)
3483 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3484 other shifts are extended. The shift patterns truncate the shift
3485 count to the right size, so there are no out-of-range values. */
3486 if (IN_RANGE (x, 1, 8))
3488 return COSTS_N_INSNS (1);
3491 if (IN_RANGE (x, -128, 127))
3493 if (SMALL_OPERAND (x))
3494 return COSTS_N_INSNS (1);
3498 /* Like LE, but reject the always-true case. */
3502 /* We add 1 to the immediate and use SLT. */
3505 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3508 if (IN_RANGE (x, 0, 255))
3510 if (SMALL_OPERAND_UNSIGNED (x))
3511 return COSTS_N_INSNS (1);
3516 /* Equality comparisons with 0 are cheap. */
3526 /* Return true if there is a non-MIPS16 instruction that implements CODE
3527 and if that instruction accepts X as an immediate operand. */
3530 mips_immediate_operand_p (int code, HOST_WIDE_INT x)
3537 /* All shift counts are truncated to a valid constant. */
3542 /* Likewise rotates, if the target supports rotates at all. */
3548 /* These instructions take 16-bit unsigned immediates. */
3549 return SMALL_OPERAND_UNSIGNED (x);
3554 /* These instructions take 16-bit signed immediates. */
3555 return SMALL_OPERAND (x);
3561 /* The "immediate" forms of these instructions are really
3562 implemented as comparisons with register 0. */
3567 /* Likewise, meaning that the only valid immediate operand is 1. */
3571 /* We add 1 to the immediate and use SLT. */
3572 return SMALL_OPERAND (x + 1);
3575 /* Likewise SLTU, but reject the always-true case. */
3576 return SMALL_OPERAND (x + 1) && x + 1 != 0;
3580 /* The bit position and size are immediate operands. */
3581 return ISA_HAS_EXT_INS;
3584 /* By default assume that $0 can be used for 0. */
3589 /* Return the cost of binary operation X, given that the instruction
3590 sequence for a word-sized or smaller operation has cost SINGLE_COST
3591 and that the sequence of a double-word operation has cost DOUBLE_COST.
3592 If SPEED is true, optimize for speed otherwise optimize for size. */
3595 mips_binary_cost (rtx x, int single_cost, int double_cost, bool speed)
3599 if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2)
3604 + set_src_cost (XEXP (x, 0), speed)
3605 + rtx_cost (XEXP (x, 1), GET_CODE (x), 1, speed));
3608 /* Return the cost of floating-point multiplications of mode MODE. */
3611 mips_fp_mult_cost (enum machine_mode mode)
3613 return mode == DFmode ? mips_cost->fp_mult_df : mips_cost->fp_mult_sf;
3616 /* Return the cost of floating-point divisions of mode MODE. */
3619 mips_fp_div_cost (enum machine_mode mode)
3621 return mode == DFmode ? mips_cost->fp_div_df : mips_cost->fp_div_sf;
3624 /* Return the cost of sign-extending OP to mode MODE, not including the
3625 cost of OP itself. */
3628 mips_sign_extend_cost (enum machine_mode mode, rtx op)
3631 /* Extended loads are as cheap as unextended ones. */
3634 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3635 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3638 if (ISA_HAS_SEB_SEH || GENERATE_MIPS16E)
3639 /* We can use SEB or SEH. */
3640 return COSTS_N_INSNS (1);
3642 /* We need to use a shift left and a shift right. */
3643 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3646 /* Return the cost of zero-extending OP to mode MODE, not including the
3647 cost of OP itself. */
3650 mips_zero_extend_cost (enum machine_mode mode, rtx op)
3653 /* Extended loads are as cheap as unextended ones. */
3656 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3657 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3658 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3660 if (GENERATE_MIPS16E)
3661 /* We can use ZEB or ZEH. */
3662 return COSTS_N_INSNS (1);
3665 /* We need to load 0xff or 0xffff into a register and use AND. */
3666 return COSTS_N_INSNS (GET_MODE (op) == QImode ? 2 : 3);
3668 /* We can use ANDI. */
3669 return COSTS_N_INSNS (1);
3672 /* Return the cost of moving between two registers of mode MODE,
3673 assuming that the move will be in pieces of at most UNITS bytes. */
3676 mips_set_reg_reg_piece_cost (enum machine_mode mode, unsigned int units)
3678 return COSTS_N_INSNS ((GET_MODE_SIZE (mode) + units - 1) / units);
3681 /* Return the cost of moving between two registers of mode MODE. */
3684 mips_set_reg_reg_cost (enum machine_mode mode)
3686 switch (GET_MODE_CLASS (mode))
3689 return mips_set_reg_reg_piece_cost (mode, GET_MODE_SIZE (CCmode));
3692 case MODE_COMPLEX_FLOAT:
3693 case MODE_VECTOR_FLOAT:
3694 if (TARGET_HARD_FLOAT)
3695 return mips_set_reg_reg_piece_cost (mode, UNITS_PER_HWFPVALUE);
3699 return mips_set_reg_reg_piece_cost (mode, UNITS_PER_WORD);
3703 /* Return the cost of an operand X that can be trucated for free.
3704 SPEED says whether we're optimizing for size or speed. */
3707 mips_truncated_op_cost (rtx x, bool speed)
3709 if (GET_CODE (x) == TRUNCATE)
3711 return set_src_cost (x, speed);
3714 /* Implement TARGET_RTX_COSTS. */
3717 mips_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
3718 int *total, bool speed)
3720 enum machine_mode mode = GET_MODE (x);
3721 bool float_mode_p = FLOAT_MODE_P (mode);
3725 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3726 appear in the instruction stream, and the cost of a comparison is
3727 really the cost of the branch or scc condition. At the time of
3728 writing, GCC only uses an explicit outer COMPARE code when optabs
3729 is testing whether a constant is expensive enough to force into a
3730 register. We want optabs to pass such constants through the MIPS
3731 expanders instead, so make all constants very cheap here. */
3732 if (outer_code == COMPARE)
3734 gcc_assert (CONSTANT_P (x));
3742 /* Treat *clear_upper32-style ANDs as having zero cost in the
3743 second operand. The cost is entirely in the first operand.
3745 ??? This is needed because we would otherwise try to CSE
3746 the constant operand. Although that's the right thing for
3747 instructions that continue to be a register operation throughout
3748 compilation, it is disastrous for instructions that could
3749 later be converted into a memory operation. */
3751 && outer_code == AND
3752 && UINTVAL (x) == 0xffffffff)
3760 cost = mips16_constant_cost (outer_code, INTVAL (x));
3769 /* When not optimizing for size, we care more about the cost
3770 of hot code, and hot code is often in a loop. If a constant
3771 operand needs to be forced into a register, we will often be
3772 able to hoist the constant load out of the loop, so the load
3773 should not contribute to the cost. */
3774 if (speed || mips_immediate_operand_p (outer_code, INTVAL (x)))
3786 if (force_to_mem_operand (x, VOIDmode))
3788 *total = COSTS_N_INSNS (1);
3791 cost = mips_const_insns (x);
3794 /* If the constant is likely to be stored in a GPR, SETs of
3795 single-insn constants are as cheap as register sets; we
3796 never want to CSE them.
3798 Don't reduce the cost of storing a floating-point zero in
3799 FPRs. If we have a zero in an FPR for other reasons, we
3800 can get better cfg-cleanup and delayed-branch results by
3801 using it consistently, rather than using $0 sometimes and
3802 an FPR at other times. Also, moves between floating-point
3803 registers are sometimes cheaper than (D)MTC1 $0. */
3805 && outer_code == SET
3806 && !(float_mode_p && TARGET_HARD_FLOAT))
3808 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3809 want to CSE the constant itself. It is usually better to
3810 have N copies of the last operation in the sequence and one
3811 shared copy of the other operations. (Note that this is
3812 not true for MIPS16 code, where the final operation in the
3813 sequence is often an extended instruction.)
3815 Also, if we have a CONST_INT, we don't know whether it is
3816 for a word or doubleword operation, so we cannot rely on
3817 the result of mips_build_integer. */
3818 else if (!TARGET_MIPS16
3819 && (outer_code == SET || mode == VOIDmode))
3821 *total = COSTS_N_INSNS (cost);
3824 /* The value will need to be fetched from the constant pool. */
3825 *total = CONSTANT_POOL_COST;
3829 /* If the address is legitimate, return the number of
3830 instructions it needs. */
3832 cost = mips_address_insns (addr, mode, true);
3835 *total = COSTS_N_INSNS (cost + 1);
3838 /* Check for a scaled indexed address. */
3839 if (mips_lwxs_address_p (addr)
3840 || mips_lx_address_p (addr, mode))
3842 *total = COSTS_N_INSNS (2);
3845 /* Otherwise use the default handling. */
3849 *total = COSTS_N_INSNS (6);
3853 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1);
3857 /* Check for a *clear_upper32 pattern and treat it like a zero
3858 extension. See the pattern's comment for details. */
3861 && CONST_INT_P (XEXP (x, 1))
3862 && UINTVAL (XEXP (x, 1)) == 0xffffffff)
3864 *total = (mips_zero_extend_cost (mode, XEXP (x, 0))
3865 + set_src_cost (XEXP (x, 0), speed));
3868 if (ISA_HAS_CINS && CONST_INT_P (XEXP (x, 1)))
3870 rtx op = XEXP (x, 0);
3871 if (GET_CODE (op) == ASHIFT
3872 && CONST_INT_P (XEXP (op, 1))
3873 && mask_low_and_shift_p (mode, XEXP (x, 1), XEXP (op, 1), 32))
3875 *total = COSTS_N_INSNS (1) + set_src_cost (XEXP (op, 0), speed);
3884 /* Double-word operations use two single-word operations. */
3885 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (2),
3894 if (CONSTANT_P (XEXP (x, 1)))
3895 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3898 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (12),
3904 *total = mips_cost->fp_add;
3906 *total = COSTS_N_INSNS (4);
3910 /* Low-part immediates need an extended MIPS16 instruction. */
3911 *total = (COSTS_N_INSNS (TARGET_MIPS16 ? 2 : 1)
3912 + set_src_cost (XEXP (x, 0), speed));
3927 /* Branch comparisons have VOIDmode, so use the first operand's
3929 mode = GET_MODE (XEXP (x, 0));
3930 if (FLOAT_MODE_P (mode))
3932 *total = mips_cost->fp_add;
3935 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3941 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3942 && TARGET_FUSED_MADD
3943 && !HONOR_NANS (mode)
3944 && !HONOR_SIGNED_ZEROS (mode))
3946 /* See if we can use NMADD or NMSUB. See mips.md for the
3947 associated patterns. */
3948 rtx op0 = XEXP (x, 0);
3949 rtx op1 = XEXP (x, 1);
3950 if (GET_CODE (op0) == MULT && GET_CODE (XEXP (op0, 0)) == NEG)
3952 *total = (mips_fp_mult_cost (mode)
3953 + set_src_cost (XEXP (XEXP (op0, 0), 0), speed)
3954 + set_src_cost (XEXP (op0, 1), speed)
3955 + set_src_cost (op1, speed));
3958 if (GET_CODE (op1) == MULT)
3960 *total = (mips_fp_mult_cost (mode)
3961 + set_src_cost (op0, speed)
3962 + set_src_cost (XEXP (op1, 0), speed)
3963 + set_src_cost (XEXP (op1, 1), speed));
3972 /* If this is part of a MADD or MSUB, treat the PLUS as
3975 && TARGET_FUSED_MADD
3976 && GET_CODE (XEXP (x, 0)) == MULT)
3979 *total = mips_cost->fp_add;
3983 /* Double-word operations require three single-word operations and
3984 an SLTU. The MIPS16 version then needs to move the result of
3985 the SLTU from $24 to a MIPS16 register. */
3986 *total = mips_binary_cost (x, COSTS_N_INSNS (1),
3987 COSTS_N_INSNS (TARGET_MIPS16 ? 5 : 4),
3993 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3994 && TARGET_FUSED_MADD
3995 && !HONOR_NANS (mode)
3996 && HONOR_SIGNED_ZEROS (mode))
3998 /* See if we can use NMADD or NMSUB. See mips.md for the
3999 associated patterns. */
4000 rtx op = XEXP (x, 0);
4001 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
4002 && GET_CODE (XEXP (op, 0)) == MULT)
4004 *total = (mips_fp_mult_cost (mode)
4005 + set_src_cost (XEXP (XEXP (op, 0), 0), speed)
4006 + set_src_cost (XEXP (XEXP (op, 0), 1), speed)
4007 + set_src_cost (XEXP (op, 1), speed));
4013 *total = mips_cost->fp_add;
4015 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1);
4020 *total = mips_fp_mult_cost (mode);
4021 else if (mode == DImode && !TARGET_64BIT)
4022 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
4023 where the mulsidi3 always includes an MFHI and an MFLO. */
4025 ? mips_cost->int_mult_si * 3 + 6
4026 : COSTS_N_INSNS (ISA_HAS_MUL3 ? 7 : 9));
4028 *total = COSTS_N_INSNS (ISA_HAS_MUL3 ? 1 : 2);
4029 else if (mode == DImode)
4030 *total = mips_cost->int_mult_di;
4032 *total = mips_cost->int_mult_si;
4036 /* Check for a reciprocal. */
4039 && flag_unsafe_math_optimizations
4040 && XEXP (x, 0) == CONST1_RTX (mode))
4042 if (outer_code == SQRT || GET_CODE (XEXP (x, 1)) == SQRT)
4043 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
4044 division as being free. */
4045 *total = set_src_cost (XEXP (x, 1), speed);
4047 *total = (mips_fp_div_cost (mode)
4048 + set_src_cost (XEXP (x, 1), speed));
4057 *total = mips_fp_div_cost (mode);
4066 /* It is our responsibility to make division by a power of 2
4067 as cheap as 2 register additions if we want the division
4068 expanders to be used for such operations; see the setting
4069 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
4070 should always produce shorter code than using
4071 expand_sdiv2_pow2. */
4073 && CONST_INT_P (XEXP (x, 1))
4074 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
4076 *total = COSTS_N_INSNS (2) + set_src_cost (XEXP (x, 0), speed);
4079 *total = COSTS_N_INSNS (mips_idiv_insns ());
4081 else if (mode == DImode)
4082 *total = mips_cost->int_div_di;
4084 *total = mips_cost->int_div_si;
4088 *total = mips_sign_extend_cost (mode, XEXP (x, 0));
4092 if (outer_code == SET
4094 && GET_MODE (XEXP (x, 0)) == QImode
4095 && GET_CODE (XEXP (x, 0)) == PLUS)
4097 rtx plus = XEXP (x, 0);
4098 *total = (COSTS_N_INSNS (1)
4099 + mips_truncated_op_cost (XEXP (plus, 0), speed)
4100 + mips_truncated_op_cost (XEXP (plus, 1), speed));
4103 *total = mips_zero_extend_cost (mode, XEXP (x, 0));
4107 case UNSIGNED_FLOAT:
4110 case FLOAT_TRUNCATE:
4111 *total = mips_cost->fp_add;
4115 if (register_operand (SET_DEST (x), VOIDmode)
4116 && reg_or_0_operand (SET_SRC (x), VOIDmode))
4118 *total = mips_set_reg_reg_cost (GET_MODE (SET_DEST (x)));
4128 /* Implement TARGET_ADDRESS_COST. */
4131 mips_address_cost (rtx addr, enum machine_mode mode,
4132 addr_space_t as ATTRIBUTE_UNUSED,
4133 bool speed ATTRIBUTE_UNUSED)
4135 return mips_address_insns (addr, mode, false);
4138 /* Information about a single instruction in a multi-instruction
4140 struct mips_multi_member {
4141 /* True if this is a label, false if it is code. */
4144 /* The output_asm_insn format of the instruction. */
4147 /* The operands to the instruction. */
4148 rtx operands[MAX_RECOG_OPERANDS];
4150 typedef struct mips_multi_member mips_multi_member;
4152 /* The instructions that make up the current multi-insn sequence. */
4153 static vec<mips_multi_member> mips_multi_members;
4155 /* How many instructions (as opposed to labels) are in the current
4156 multi-insn sequence. */
4157 static unsigned int mips_multi_num_insns;
4159 /* Start a new multi-insn sequence. */
4162 mips_multi_start (void)
4164 mips_multi_members.truncate (0);
4165 mips_multi_num_insns = 0;
4168 /* Add a new, uninitialized member to the current multi-insn sequence. */
4170 static struct mips_multi_member *
4171 mips_multi_add (void)
4173 mips_multi_member empty;
4174 return mips_multi_members.safe_push (empty);
4177 /* Add a normal insn with the given asm format to the current multi-insn
4178 sequence. The other arguments are a null-terminated list of operands. */
4181 mips_multi_add_insn (const char *format, ...)
4183 struct mips_multi_member *member;
4188 member = mips_multi_add ();
4189 member->is_label_p = false;
4190 member->format = format;
4191 va_start (ap, format);
4193 while ((op = va_arg (ap, rtx)))
4194 member->operands[i++] = op;
4196 mips_multi_num_insns++;
4199 /* Add the given label definition to the current multi-insn sequence.
4200 The definition should include the colon. */
4203 mips_multi_add_label (const char *label)
4205 struct mips_multi_member *member;
4207 member = mips_multi_add ();
4208 member->is_label_p = true;
4209 member->format = label;
4212 /* Return the index of the last member of the current multi-insn sequence. */
4215 mips_multi_last_index (void)
4217 return mips_multi_members.length () - 1;
4220 /* Add a copy of an existing instruction to the current multi-insn
4221 sequence. I is the index of the instruction that should be copied. */
4224 mips_multi_copy_insn (unsigned int i)
4226 struct mips_multi_member *member;
4228 member = mips_multi_add ();
4229 memcpy (member, &mips_multi_members[i], sizeof (*member));
4230 gcc_assert (!member->is_label_p);
4233 /* Change the operand of an existing instruction in the current
4234 multi-insn sequence. I is the index of the instruction,
4235 OP is the index of the operand, and X is the new value. */
4238 mips_multi_set_operand (unsigned int i, unsigned int op, rtx x)
4240 mips_multi_members[i].operands[op] = x;
4243 /* Write out the asm code for the current multi-insn sequence. */
4246 mips_multi_write (void)
4248 struct mips_multi_member *member;
4251 FOR_EACH_VEC_ELT (mips_multi_members, i, member)
4252 if (member->is_label_p)
4253 fprintf (asm_out_file, "%s\n", member->format);
4255 output_asm_insn (member->format, member->operands);
4258 /* Return one word of double-word value OP, taking into account the fixed
4259 endianness of certain registers. HIGH_P is true to select the high part,
4260 false to select the low part. */
4263 mips_subword (rtx op, bool high_p)
4265 unsigned int byte, offset;
4266 enum machine_mode mode;
4268 mode = GET_MODE (op);
4269 if (mode == VOIDmode)
4270 mode = TARGET_64BIT ? TImode : DImode;
4272 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
4273 byte = UNITS_PER_WORD;
4277 if (FP_REG_RTX_P (op))
4279 /* Paired FPRs are always ordered little-endian. */
4280 offset = (UNITS_PER_WORD < UNITS_PER_HWFPVALUE ? high_p : byte != 0);
4281 return gen_rtx_REG (word_mode, REGNO (op) + offset);
4285 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
4287 return simplify_gen_subreg (word_mode, op, mode, byte);
4290 /* Return true if SRC should be moved into DEST using "MULT $0, $0".
4291 SPLIT_TYPE is the condition under which moves should be split. */
4294 mips_mult_move_p (rtx dest, rtx src, enum mips_split_type split_type)
4296 return ((split_type != SPLIT_FOR_SPEED
4297 || mips_tuning_info.fast_mult_zero_zero_p)
4298 && src == const0_rtx
4300 && GET_MODE_SIZE (GET_MODE (dest)) == 2 * UNITS_PER_WORD
4301 && (ISA_HAS_DSP_MULT
4302 ? ACC_REG_P (REGNO (dest))
4303 : MD_REG_P (REGNO (dest))));
4306 /* Return true if a move from SRC to DEST should be split into two.
4307 SPLIT_TYPE describes the split condition. */
4310 mips_split_move_p (rtx dest, rtx src, enum mips_split_type split_type)
4312 /* Check whether the move can be done using some variant of MULT $0,$0. */
4313 if (mips_mult_move_p (dest, src, split_type))
4316 /* FPR-to-FPR moves can be done in a single instruction, if they're
4318 unsigned int size = GET_MODE_SIZE (GET_MODE (dest));
4319 if (size == 8 && FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
4322 /* Check for floating-point loads and stores. */
4323 if (size == 8 && ISA_HAS_LDC1_SDC1)
4325 if (FP_REG_RTX_P (dest) && MEM_P (src))
4327 if (FP_REG_RTX_P (src) && MEM_P (dest))
4331 /* Otherwise split all multiword moves. */
4332 return size > UNITS_PER_WORD;
4335 /* Split a move from SRC to DEST, given that mips_split_move_p holds.
4336 SPLIT_TYPE describes the split condition. */
4339 mips_split_move (rtx dest, rtx src, enum mips_split_type split_type)
4343 gcc_checking_assert (mips_split_move_p (dest, src, split_type));
4344 if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src))
4346 if (!TARGET_64BIT && GET_MODE (dest) == DImode)
4347 emit_insn (gen_move_doubleword_fprdi (dest, src));
4348 else if (!TARGET_64BIT && GET_MODE (dest) == DFmode)
4349 emit_insn (gen_move_doubleword_fprdf (dest, src));
4350 else if (!TARGET_64BIT && GET_MODE (dest) == V2SFmode)
4351 emit_insn (gen_move_doubleword_fprv2sf (dest, src));
4352 else if (!TARGET_64BIT && GET_MODE (dest) == V2SImode)
4353 emit_insn (gen_move_doubleword_fprv2si (dest, src));
4354 else if (!TARGET_64BIT && GET_MODE (dest) == V4HImode)
4355 emit_insn (gen_move_doubleword_fprv4hi (dest, src));
4356 else if (!TARGET_64BIT && GET_MODE (dest) == V8QImode)
4357 emit_insn (gen_move_doubleword_fprv8qi (dest, src));
4358 else if (TARGET_64BIT && GET_MODE (dest) == TFmode)
4359 emit_insn (gen_move_doubleword_fprtf (dest, src));
4363 else if (REG_P (dest) && REGNO (dest) == MD_REG_FIRST)
4365 low_dest = mips_subword (dest, false);
4366 mips_emit_move (low_dest, mips_subword (src, false));
4368 emit_insn (gen_mthidi_ti (dest, mips_subword (src, true), low_dest));
4370 emit_insn (gen_mthisi_di (dest, mips_subword (src, true), low_dest));
4372 else if (REG_P (src) && REGNO (src) == MD_REG_FIRST)
4374 mips_emit_move (mips_subword (dest, false), mips_subword (src, false));
4376 emit_insn (gen_mfhidi_ti (mips_subword (dest, true), src));
4378 emit_insn (gen_mfhisi_di (mips_subword (dest, true), src));
4382 /* The operation can be split into two normal moves. Decide in
4383 which order to do them. */
4384 low_dest = mips_subword (dest, false);
4385 if (REG_P (low_dest)
4386 && reg_overlap_mentioned_p (low_dest, src))
4388 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4389 mips_emit_move (low_dest, mips_subword (src, false));
4393 mips_emit_move (low_dest, mips_subword (src, false));
4394 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4399 /* Return the split type for instruction INSN. */
4401 static enum mips_split_type
4402 mips_insn_split_type (rtx insn)
4404 basic_block bb = BLOCK_FOR_INSN (insn);
4407 if (optimize_bb_for_speed_p (bb))
4408 return SPLIT_FOR_SPEED;
4410 return SPLIT_FOR_SIZE;
4412 /* Once CFG information has been removed, we should trust the optimization
4413 decisions made by previous passes and only split where necessary. */
4414 return SPLIT_IF_NECESSARY;
4417 /* Return true if a move from SRC to DEST in INSN should be split. */
4420 mips_split_move_insn_p (rtx dest, rtx src, rtx insn)
4422 return mips_split_move_p (dest, src, mips_insn_split_type (insn));
4425 /* Split a move from SRC to DEST in INSN, given that mips_split_move_insn_p
4429 mips_split_move_insn (rtx dest, rtx src, rtx insn)
4431 mips_split_move (dest, src, mips_insn_split_type (insn));
4434 /* Return the appropriate instructions to move SRC into DEST. Assume
4435 that SRC is operand 1 and DEST is operand 0. */
4438 mips_output_move (rtx dest, rtx src)
4440 enum rtx_code dest_code, src_code;
4441 enum machine_mode mode;
4442 enum mips_symbol_type symbol_type;
4445 dest_code = GET_CODE (dest);
4446 src_code = GET_CODE (src);
4447 mode = GET_MODE (dest);
4448 dbl_p = (GET_MODE_SIZE (mode) == 8);
4450 if (mips_split_move_p (dest, src, SPLIT_IF_NECESSARY))
4453 if ((src_code == REG && GP_REG_P (REGNO (src)))
4454 || (!TARGET_MIPS16 && src == CONST0_RTX (mode)))
4456 if (dest_code == REG)
4458 if (GP_REG_P (REGNO (dest)))
4459 return "move\t%0,%z1";
4461 if (mips_mult_move_p (dest, src, SPLIT_IF_NECESSARY))
4463 if (ISA_HAS_DSP_MULT)
4464 return "mult\t%q0,%.,%.";
4466 return "mult\t%.,%.";
4469 /* Moves to HI are handled by special .md insns. */
4470 if (REGNO (dest) == LO_REGNUM)
4473 if (DSP_ACC_REG_P (REGNO (dest)))
4475 static char retval[] = "mt__\t%z1,%q0";
4477 retval[2] = reg_names[REGNO (dest)][4];
4478 retval[3] = reg_names[REGNO (dest)][5];
4482 if (FP_REG_P (REGNO (dest)))
4483 return dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
4485 if (ALL_COP_REG_P (REGNO (dest)))
4487 static char retval[] = "dmtc_\t%z1,%0";
4489 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4490 return dbl_p ? retval : retval + 1;
4493 if (dest_code == MEM)
4494 switch (GET_MODE_SIZE (mode))
4496 case 1: return "sb\t%z1,%0";
4497 case 2: return "sh\t%z1,%0";
4498 case 4: return "sw\t%z1,%0";
4499 case 8: return "sd\t%z1,%0";
4502 if (dest_code == REG && GP_REG_P (REGNO (dest)))
4504 if (src_code == REG)
4506 /* Moves from HI are handled by special .md insns. */
4507 if (REGNO (src) == LO_REGNUM)
4509 /* When generating VR4120 or VR4130 code, we use MACC and
4510 DMACC instead of MFLO. This avoids both the normal
4511 MIPS III HI/LO hazards and the errata related to
4514 return dbl_p ? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
4518 if (DSP_ACC_REG_P (REGNO (src)))
4520 static char retval[] = "mf__\t%0,%q1";
4522 retval[2] = reg_names[REGNO (src)][4];
4523 retval[3] = reg_names[REGNO (src)][5];
4527 if (FP_REG_P (REGNO (src)))
4528 return dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
4530 if (ALL_COP_REG_P (REGNO (src)))
4532 static char retval[] = "dmfc_\t%0,%1";
4534 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4535 return dbl_p ? retval : retval + 1;
4539 if (src_code == MEM)
4540 switch (GET_MODE_SIZE (mode))
4542 case 1: return "lbu\t%0,%1";
4543 case 2: return "lhu\t%0,%1";
4544 case 4: return "lw\t%0,%1";
4545 case 8: return "ld\t%0,%1";
4548 if (src_code == CONST_INT)
4550 /* Don't use the X format for the operand itself, because that
4551 will give out-of-range numbers for 64-bit hosts and 32-bit
4554 return "li\t%0,%1\t\t\t# %X1";
4556 if (SMALL_OPERAND_UNSIGNED (INTVAL (src)))
4559 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src)))
4563 if (src_code == HIGH)
4564 return TARGET_MIPS16 ? "#" : "lui\t%0,%h1";
4566 if (CONST_GP_P (src))
4567 return "move\t%0,%1";
4569 if (mips_symbolic_constant_p (src, SYMBOL_CONTEXT_LEA, &symbol_type)
4570 && mips_lo_relocs[symbol_type] != 0)
4572 /* A signed 16-bit constant formed by applying a relocation
4573 operator to a symbolic address. */
4574 gcc_assert (!mips_split_p[symbol_type]);
4575 return "li\t%0,%R1";
4578 if (symbolic_operand (src, VOIDmode))
4580 gcc_assert (TARGET_MIPS16
4581 ? TARGET_MIPS16_TEXT_LOADS
4582 : !TARGET_EXPLICIT_RELOCS);
4583 return dbl_p ? "dla\t%0,%1" : "la\t%0,%1";
4586 if (src_code == REG && FP_REG_P (REGNO (src)))
4588 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4590 if (GET_MODE (dest) == V2SFmode)
4591 return "mov.ps\t%0,%1";
4593 return dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1";
4596 if (dest_code == MEM)
4597 return dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0";
4599 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4601 if (src_code == MEM)
4602 return dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1";
4604 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
4606 static char retval[] = "l_c_\t%0,%1";
4608 retval[1] = (dbl_p ? 'd' : 'w');
4609 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4612 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
4614 static char retval[] = "s_c_\t%1,%0";
4616 retval[1] = (dbl_p ? 'd' : 'w');
4617 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4623 /* Return true if CMP1 is a suitable second operand for integer ordering
4624 test CODE. See also the *sCC patterns in mips.md. */
4627 mips_int_order_operand_ok_p (enum rtx_code code, rtx cmp1)
4633 return reg_or_0_operand (cmp1, VOIDmode);
4637 return !TARGET_MIPS16 && cmp1 == const1_rtx;
4641 return arith_operand (cmp1, VOIDmode);
4644 return sle_operand (cmp1, VOIDmode);
4647 return sleu_operand (cmp1, VOIDmode);
4654 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4655 integer ordering test *CODE, or if an equivalent combination can
4656 be formed by adjusting *CODE and *CMP1. When returning true, update
4657 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4661 mips_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1,
4662 enum machine_mode mode)
4664 HOST_WIDE_INT plus_one;
4666 if (mips_int_order_operand_ok_p (*code, *cmp1))
4669 if (CONST_INT_P (*cmp1))
4673 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4674 if (INTVAL (*cmp1) < plus_one)
4677 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4683 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4687 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4698 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4699 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4700 is nonnull, it's OK to set TARGET to the inverse of the result and
4701 flip *INVERT_PTR instead. */
4704 mips_emit_int_order_test (enum rtx_code code, bool *invert_ptr,
4705 rtx target, rtx cmp0, rtx cmp1)
4707 enum machine_mode mode;
4709 /* First see if there is a MIPS instruction that can do this operation.
4710 If not, try doing the same for the inverse operation. If that also
4711 fails, force CMP1 into a register and try again. */
4712 mode = GET_MODE (cmp0);
4713 if (mips_canonicalize_int_order_test (&code, &cmp1, mode))
4714 mips_emit_binary (code, target, cmp0, cmp1);
4717 enum rtx_code inv_code = reverse_condition (code);
4718 if (!mips_canonicalize_int_order_test (&inv_code, &cmp1, mode))
4720 cmp1 = force_reg (mode, cmp1);
4721 mips_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1);
4723 else if (invert_ptr == 0)
4727 inv_target = mips_force_binary (GET_MODE (target),
4728 inv_code, cmp0, cmp1);
4729 mips_emit_binary (XOR, target, inv_target, const1_rtx);
4733 *invert_ptr = !*invert_ptr;
4734 mips_emit_binary (inv_code, target, cmp0, cmp1);
4739 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4740 The register will have the same mode as CMP0. */
4743 mips_zero_if_equal (rtx cmp0, rtx cmp1)
4745 if (cmp1 == const0_rtx)
4748 if (uns_arith_operand (cmp1, VOIDmode))
4749 return expand_binop (GET_MODE (cmp0), xor_optab,
4750 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4752 return expand_binop (GET_MODE (cmp0), sub_optab,
4753 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4756 /* Convert *CODE into a code that can be used in a floating-point
4757 scc instruction (C.cond.fmt). Return true if the values of
4758 the condition code registers will be inverted, with 0 indicating
4759 that the condition holds. */
4762 mips_reversed_fp_cond (enum rtx_code *code)
4769 *code = reverse_condition_maybe_unordered (*code);
4777 /* Allocate a floating-point condition-code register of mode MODE.
4779 These condition code registers are used for certain kinds
4780 of compound operation, such as compare and branches, vconds,
4781 and built-in functions. At expand time, their use is entirely
4782 controlled by MIPS-specific code and is entirely internal
4783 to these compound operations.
4785 We could (and did in the past) expose condition-code values
4786 as pseudo registers and leave the register allocator to pick
4787 appropriate registers. The problem is that it is not practically
4788 possible for the rtl optimizers to guarantee that no spills will
4789 be needed, even when AVOID_CCMODE_COPIES is defined. We would
4790 therefore need spill and reload sequences to handle the worst case.
4792 Although such sequences do exist, they are very expensive and are
4793 not something we'd want to use. This is especially true of CCV2 and
4794 CCV4, where all the shuffling would greatly outweigh whatever benefit
4795 the vectorization itself provides.
4797 The main benefit of having more than one condition-code register
4798 is to allow the pipelining of operations, especially those involving
4799 comparisons and conditional moves. We don't really expect the
4800 registers to be live for long periods, and certainly never want
4801 them to be live across calls.
4803 Also, there should be no penalty attached to using all the available
4804 registers. They are simply bits in the same underlying FPU control
4807 We therefore expose the hardware registers from the outset and use
4808 a simple round-robin allocation scheme. */
4811 mips_allocate_fcc (enum machine_mode mode)
4813 unsigned int regno, count;
4815 gcc_assert (TARGET_HARD_FLOAT && ISA_HAS_8CC);
4819 else if (mode == CCV2mode)
4821 else if (mode == CCV4mode)
4826 cfun->machine->next_fcc += -cfun->machine->next_fcc & (count - 1);
4827 if (cfun->machine->next_fcc > ST_REG_LAST - ST_REG_FIRST)
4828 cfun->machine->next_fcc = 0;
4829 regno = ST_REG_FIRST + cfun->machine->next_fcc;
4830 cfun->machine->next_fcc += count;
4831 return gen_rtx_REG (mode, regno);
4834 /* Convert a comparison into something that can be used in a branch or
4835 conditional move. On entry, *OP0 and *OP1 are the values being
4836 compared and *CODE is the code used to compare them.
4838 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
4839 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
4840 otherwise any standard branch condition can be used. The standard branch
4843 - EQ or NE between two registers.
4844 - any comparison between a register and zero. */
4847 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
4852 if (GET_MODE_CLASS (GET_MODE (*op0)) == MODE_INT)
4854 if (!need_eq_ne_p && *op1 == const0_rtx)
4856 else if (*code == EQ || *code == NE)
4860 *op0 = mips_zero_if_equal (cmp_op0, cmp_op1);
4864 *op1 = force_reg (GET_MODE (cmp_op0), cmp_op1);
4868 /* The comparison needs a separate scc instruction. Store the
4869 result of the scc in *OP0 and compare it against zero. */
4870 bool invert = false;
4871 *op0 = gen_reg_rtx (GET_MODE (cmp_op0));
4872 mips_emit_int_order_test (*code, &invert, *op0, cmp_op0, cmp_op1);
4873 *code = (invert ? EQ : NE);
4877 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0)))
4879 *op0 = gen_rtx_REG (CCDSPmode, CCDSP_CC_REGNUM);
4880 mips_emit_binary (*code, *op0, cmp_op0, cmp_op1);
4886 enum rtx_code cmp_code;
4888 /* Floating-point tests use a separate C.cond.fmt comparison to
4889 set a condition code register. The branch or conditional move
4890 will then compare that register against zero.
4892 Set CMP_CODE to the code of the comparison instruction and
4893 *CODE to the code that the branch or move should use. */
4895 *code = mips_reversed_fp_cond (&cmp_code) ? EQ : NE;
4897 ? mips_allocate_fcc (CCmode)
4898 : gen_rtx_REG (CCmode, FPSW_REGNUM));
4900 mips_emit_binary (cmp_code, *op0, cmp_op0, cmp_op1);
4904 /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2]
4905 and OPERAND[3]. Store the result in OPERANDS[0].
4907 On 64-bit targets, the mode of the comparison and target will always be
4908 SImode, thus possibly narrower than that of the comparison's operands. */
4911 mips_expand_scc (rtx operands[])
4913 rtx target = operands[0];
4914 enum rtx_code code = GET_CODE (operands[1]);
4915 rtx op0 = operands[2];
4916 rtx op1 = operands[3];
4918 gcc_assert (GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT);
4920 if (code == EQ || code == NE)
4923 && reg_imm10_operand (op1, GET_MODE (op1)))
4924 mips_emit_binary (code, target, op0, op1);
4927 rtx zie = mips_zero_if_equal (op0, op1);
4928 mips_emit_binary (code, target, zie, const0_rtx);
4932 mips_emit_int_order_test (code, 0, target, op0, op1);
4935 /* Compare OPERANDS[1] with OPERANDS[2] using comparison code
4936 CODE and jump to OPERANDS[3] if the condition holds. */
4939 mips_expand_conditional_branch (rtx *operands)
4941 enum rtx_code code = GET_CODE (operands[0]);
4942 rtx op0 = operands[1];
4943 rtx op1 = operands[2];
4946 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
4947 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
4948 emit_jump_insn (gen_condjump (condition, operands[3]));
4953 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
4954 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
4957 mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
4958 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
4963 reversed_p = mips_reversed_fp_cond (&cond);
4964 cmp_result = mips_allocate_fcc (CCV2mode);
4965 emit_insn (gen_scc_ps (cmp_result,
4966 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
4968 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
4971 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
4975 /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0]
4976 if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
4979 mips_expand_conditional_move (rtx *operands)
4982 enum rtx_code code = GET_CODE (operands[1]);
4983 rtx op0 = XEXP (operands[1], 0);
4984 rtx op1 = XEXP (operands[1], 1);
4986 mips_emit_compare (&code, &op0, &op1, true);
4987 cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
4988 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
4989 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), cond,
4990 operands[2], operands[3])));
4993 /* Perform the comparison in COMPARISON, then trap if the condition holds. */
4996 mips_expand_conditional_trap (rtx comparison)
4999 enum machine_mode mode;
5002 /* MIPS conditional trap instructions don't have GT or LE flavors,
5003 so we must swap the operands and convert to LT and GE respectively. */
5004 code = GET_CODE (comparison);
5011 code = swap_condition (code);
5012 op0 = XEXP (comparison, 1);
5013 op1 = XEXP (comparison, 0);
5017 op0 = XEXP (comparison, 0);
5018 op1 = XEXP (comparison, 1);
5022 mode = GET_MODE (XEXP (comparison, 0));
5023 op0 = force_reg (mode, op0);
5024 if (!arith_operand (op1, mode))
5025 op1 = force_reg (mode, op1);
5027 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
5028 gen_rtx_fmt_ee (code, mode, op0, op1),
5032 /* Initialize *CUM for a call to a function of type FNTYPE. */
5035 mips_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype)
5037 memset (cum, 0, sizeof (*cum));
5038 cum->prototype = (fntype && prototype_p (fntype));
5039 cum->gp_reg_found = (cum->prototype && stdarg_p (fntype));
5042 /* Fill INFO with information about a single argument. CUM is the
5043 cumulative state for earlier arguments. MODE is the mode of this
5044 argument and TYPE is its type (if known). NAMED is true if this
5045 is a named (fixed) argument rather than a variable one. */
5048 mips_get_arg_info (struct mips_arg_info *info, const CUMULATIVE_ARGS *cum,
5049 enum machine_mode mode, const_tree type, bool named)
5051 bool doubleword_aligned_p;
5052 unsigned int num_bytes, num_words, max_regs;
5054 /* Work out the size of the argument. */
5055 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
5056 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5058 /* Decide whether it should go in a floating-point register, assuming
5059 one is free. Later code checks for availability.
5061 The checks against UNITS_PER_FPVALUE handle the soft-float and
5062 single-float cases. */
5066 /* The EABI conventions have traditionally been defined in terms
5067 of TYPE_MODE, regardless of the actual type. */
5068 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
5069 || mode == V2SFmode)
5070 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
5075 /* Only leading floating-point scalars are passed in
5076 floating-point registers. We also handle vector floats the same
5077 say, which is OK because they are not covered by the standard ABI. */
5078 info->fpr_p = (!cum->gp_reg_found
5079 && cum->arg_number < 2
5081 || SCALAR_FLOAT_TYPE_P (type)
5082 || VECTOR_FLOAT_TYPE_P (type))
5083 && (GET_MODE_CLASS (mode) == MODE_FLOAT
5084 || mode == V2SFmode)
5085 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
5090 /* Scalar, complex and vector floating-point types are passed in
5091 floating-point registers, as long as this is a named rather
5092 than a variable argument. */
5093 info->fpr_p = (named
5094 && (type == 0 || FLOAT_TYPE_P (type))
5095 && (GET_MODE_CLASS (mode) == MODE_FLOAT
5096 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5097 || mode == V2SFmode)
5098 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
5100 /* ??? According to the ABI documentation, the real and imaginary
5101 parts of complex floats should be passed in individual registers.
5102 The real and imaginary parts of stack arguments are supposed
5103 to be contiguous and there should be an extra word of padding
5106 This has two problems. First, it makes it impossible to use a
5107 single "void *" va_list type, since register and stack arguments
5108 are passed differently. (At the time of writing, MIPSpro cannot
5109 handle complex float varargs correctly.) Second, it's unclear
5110 what should happen when there is only one register free.
5112 For now, we assume that named complex floats should go into FPRs
5113 if there are two FPRs free, otherwise they should be passed in the
5114 same way as a struct containing two floats. */
5116 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5117 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
5119 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
5120 info->fpr_p = false;
5130 /* See whether the argument has doubleword alignment. */
5131 doubleword_aligned_p = (mips_function_arg_boundary (mode, type)
5134 /* Set REG_OFFSET to the register count we're interested in.
5135 The EABI allocates the floating-point registers separately,
5136 but the other ABIs allocate them like integer registers. */
5137 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
5141 /* Advance to an even register if the argument is doubleword-aligned. */
5142 if (doubleword_aligned_p)
5143 info->reg_offset += info->reg_offset & 1;
5145 /* Work out the offset of a stack argument. */
5146 info->stack_offset = cum->stack_words;
5147 if (doubleword_aligned_p)
5148 info->stack_offset += info->stack_offset & 1;
5150 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
5152 /* Partition the argument between registers and stack. */
5153 info->reg_words = MIN (num_words, max_regs);
5154 info->stack_words = num_words - info->reg_words;
5157 /* INFO describes a register argument that has the normal format for the
5158 argument's mode. Return the register it uses, assuming that FPRs are
5159 available if HARD_FLOAT_P. */
5162 mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p)
5164 if (!info->fpr_p || !hard_float_p)
5165 return GP_ARG_FIRST + info->reg_offset;
5166 else if (mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info->reg_offset > 0)
5167 /* In o32, the second argument is always passed in $f14
5168 for TARGET_DOUBLE_FLOAT, regardless of whether the
5169 first argument was a word or doubleword. */
5170 return FP_ARG_FIRST + 2;
5172 return FP_ARG_FIRST + info->reg_offset;
5175 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
5178 mips_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED)
5180 return !TARGET_OLDABI;
5183 /* Implement TARGET_FUNCTION_ARG. */
5186 mips_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
5187 const_tree type, bool named)
5189 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
5190 struct mips_arg_info info;
5192 /* We will be called with a mode of VOIDmode after the last argument
5193 has been seen. Whatever we return will be passed to the call expander.
5194 If we need a MIPS16 fp_code, return a REG with the code stored as
5196 if (mode == VOIDmode)
5198 if (TARGET_MIPS16 && cum->fp_code != 0)
5199 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
5204 mips_get_arg_info (&info, cum, mode, type, named);
5206 /* Return straight away if the whole argument is passed on the stack. */
5207 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
5210 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
5211 contains a double in its entirety, then that 64-bit chunk is passed
5212 in a floating-point register. */
5214 && TARGET_HARD_FLOAT
5217 && TREE_CODE (type) == RECORD_TYPE
5218 && TYPE_SIZE_UNIT (type)
5219 && host_integerp (TYPE_SIZE_UNIT (type), 1))
5223 /* First check to see if there is any such field. */
5224 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
5225 if (TREE_CODE (field) == FIELD_DECL
5226 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
5227 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
5228 && host_integerp (bit_position (field), 0)
5229 && int_bit_position (field) % BITS_PER_WORD == 0)
5234 /* Now handle the special case by returning a PARALLEL
5235 indicating where each 64-bit chunk goes. INFO.REG_WORDS
5236 chunks are passed in registers. */
5238 HOST_WIDE_INT bitpos;
5241 /* assign_parms checks the mode of ENTRY_PARM, so we must
5242 use the actual mode here. */
5243 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
5246 field = TYPE_FIELDS (type);
5247 for (i = 0; i < info.reg_words; i++)
5251 for (; field; field = DECL_CHAIN (field))
5252 if (TREE_CODE (field) == FIELD_DECL
5253 && int_bit_position (field) >= bitpos)
5257 && int_bit_position (field) == bitpos
5258 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
5259 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
5260 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
5262 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
5265 = gen_rtx_EXPR_LIST (VOIDmode, reg,
5266 GEN_INT (bitpos / BITS_PER_UNIT));
5268 bitpos += BITS_PER_WORD;
5274 /* Handle the n32/n64 conventions for passing complex floating-point
5275 arguments in FPR pairs. The real part goes in the lower register
5276 and the imaginary part goes in the upper register. */
5279 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5282 enum machine_mode inner;
5285 inner = GET_MODE_INNER (mode);
5286 regno = FP_ARG_FIRST + info.reg_offset;
5287 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
5289 /* Real part in registers, imaginary part on stack. */
5290 gcc_assert (info.stack_words == info.reg_words);
5291 return gen_rtx_REG (inner, regno);
5295 gcc_assert (info.stack_words == 0);
5296 real = gen_rtx_EXPR_LIST (VOIDmode,
5297 gen_rtx_REG (inner, regno),
5299 imag = gen_rtx_EXPR_LIST (VOIDmode,
5301 regno + info.reg_words / 2),
5302 GEN_INT (GET_MODE_SIZE (inner)));
5303 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
5307 return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT));
5310 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
5313 mips_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
5314 const_tree type, bool named)
5316 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
5317 struct mips_arg_info info;
5319 mips_get_arg_info (&info, cum, mode, type, named);
5322 cum->gp_reg_found = true;
5324 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
5325 an explanation of what this code does. It assumes that we're using
5326 either the o32 or the o64 ABI, both of which pass at most 2 arguments
5328 if (cum->arg_number < 2 && info.fpr_p)
5329 cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2);
5331 /* Advance the register count. This has the effect of setting
5332 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
5333 argument required us to skip the final GPR and pass the whole
5334 argument on the stack. */
5335 if (mips_abi != ABI_EABI || !info.fpr_p)
5336 cum->num_gprs = info.reg_offset + info.reg_words;
5337 else if (info.reg_words > 0)
5338 cum->num_fprs += MAX_FPRS_PER_FMT;
5340 /* Advance the stack word count. */
5341 if (info.stack_words > 0)
5342 cum->stack_words = info.stack_offset + info.stack_words;
5347 /* Implement TARGET_ARG_PARTIAL_BYTES. */
5350 mips_arg_partial_bytes (cumulative_args_t cum,
5351 enum machine_mode mode, tree type, bool named)
5353 struct mips_arg_info info;
5355 mips_get_arg_info (&info, get_cumulative_args (cum), mode, type, named);
5356 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
5359 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
5360 least PARM_BOUNDARY bits of alignment, but will be given anything up
5361 to STACK_BOUNDARY bits if the type requires it. */
5364 mips_function_arg_boundary (enum machine_mode mode, const_tree type)
5366 unsigned int alignment;
5368 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
5369 if (alignment < PARM_BOUNDARY)
5370 alignment = PARM_BOUNDARY;
5371 if (alignment > STACK_BOUNDARY)
5372 alignment = STACK_BOUNDARY;
5376 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
5377 upward rather than downward. In other words, return true if the
5378 first byte of the stack slot has useful data, false if the last
5382 mips_pad_arg_upward (enum machine_mode mode, const_tree type)
5384 /* On little-endian targets, the first byte of every stack argument
5385 is passed in the first byte of the stack slot. */
5386 if (!BYTES_BIG_ENDIAN)
5389 /* Otherwise, integral types are padded downward: the last byte of a
5390 stack argument is passed in the last byte of the stack slot. */
5392 ? (INTEGRAL_TYPE_P (type)
5393 || POINTER_TYPE_P (type)
5394 || FIXED_POINT_TYPE_P (type))
5395 : (SCALAR_INT_MODE_P (mode)
5396 || ALL_SCALAR_FIXED_POINT_MODE_P (mode)))
5399 /* Big-endian o64 pads floating-point arguments downward. */
5400 if (mips_abi == ABI_O64)
5401 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
5404 /* Other types are padded upward for o32, o64, n32 and n64. */
5405 if (mips_abi != ABI_EABI)
5408 /* Arguments smaller than a stack slot are padded downward. */
5409 if (mode != BLKmode)
5410 return GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY;
5412 return int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT);
5415 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
5416 if the least significant byte of the register has useful data. Return
5417 the opposite if the most significant byte does. */
5420 mips_pad_reg_upward (enum machine_mode mode, tree type)
5422 /* No shifting is required for floating-point arguments. */
5423 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
5424 return !BYTES_BIG_ENDIAN;
5426 /* Otherwise, apply the same padding to register arguments as we do
5427 to stack arguments. */
5428 return mips_pad_arg_upward (mode, type);
5431 /* Return nonzero when an argument must be passed by reference. */
5434 mips_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
5435 enum machine_mode mode, const_tree type,
5436 bool named ATTRIBUTE_UNUSED)
5438 if (mips_abi == ABI_EABI)
5442 /* ??? How should SCmode be handled? */
5443 if (mode == DImode || mode == DFmode
5444 || mode == DQmode || mode == UDQmode
5445 || mode == DAmode || mode == UDAmode)
5448 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
5449 return size == -1 || size > UNITS_PER_WORD;
5453 /* If we have a variable-sized parameter, we have no choice. */
5454 return targetm.calls.must_pass_in_stack (mode, type);
5458 /* Implement TARGET_CALLEE_COPIES. */
5461 mips_callee_copies (cumulative_args_t cum ATTRIBUTE_UNUSED,
5462 enum machine_mode mode ATTRIBUTE_UNUSED,
5463 const_tree type ATTRIBUTE_UNUSED, bool named)
5465 return mips_abi == ABI_EABI && named;
5468 /* See whether VALTYPE is a record whose fields should be returned in
5469 floating-point registers. If so, return the number of fields and
5470 list them in FIELDS (which should have two elements). Return 0
5473 For n32 & n64, a structure with one or two fields is returned in
5474 floating-point registers as long as every field has a floating-point
5478 mips_fpr_return_fields (const_tree valtype, tree *fields)
5486 if (TREE_CODE (valtype) != RECORD_TYPE)
5490 for (field = TYPE_FIELDS (valtype); field != 0; field = DECL_CHAIN (field))
5492 if (TREE_CODE (field) != FIELD_DECL)
5495 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)))
5501 fields[i++] = field;
5506 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
5507 a value in the most significant part of $2/$3 if:
5509 - the target is big-endian;
5511 - the value has a structure or union type (we generalize this to
5512 cover aggregates from other languages too); and
5514 - the structure is not returned in floating-point registers. */
5517 mips_return_in_msb (const_tree valtype)
5521 return (TARGET_NEWABI
5522 && TARGET_BIG_ENDIAN
5523 && AGGREGATE_TYPE_P (valtype)
5524 && mips_fpr_return_fields (valtype, fields) == 0);
5527 /* Return true if the function return value MODE will get returned in a
5528 floating-point register. */
5531 mips_return_mode_in_fpr_p (enum machine_mode mode)
5533 return ((GET_MODE_CLASS (mode) == MODE_FLOAT
5535 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5536 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE);
5539 /* Return the representation of an FPR return register when the
5540 value being returned in FP_RETURN has mode VALUE_MODE and the
5541 return type itself has mode TYPE_MODE. On NewABI targets,
5542 the two modes may be different for structures like:
5544 struct __attribute__((packed)) foo { float f; }
5546 where we return the SFmode value of "f" in FP_RETURN, but where
5547 the structure itself has mode BLKmode. */
5550 mips_return_fpr_single (enum machine_mode type_mode,
5551 enum machine_mode value_mode)
5555 x = gen_rtx_REG (value_mode, FP_RETURN);
5556 if (type_mode != value_mode)
5558 x = gen_rtx_EXPR_LIST (VOIDmode, x, const0_rtx);
5559 x = gen_rtx_PARALLEL (type_mode, gen_rtvec (1, x));
5564 /* Return a composite value in a pair of floating-point registers.
5565 MODE1 and OFFSET1 are the mode and byte offset for the first value,
5566 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
5569 For n32 & n64, $f0 always holds the first value and $f2 the second.
5570 Otherwise the values are packed together as closely as possible. */
5573 mips_return_fpr_pair (enum machine_mode mode,
5574 enum machine_mode mode1, HOST_WIDE_INT offset1,
5575 enum machine_mode mode2, HOST_WIDE_INT offset2)
5579 inc = (TARGET_NEWABI ? 2 : MAX_FPRS_PER_FMT);
5580 return gen_rtx_PARALLEL
5583 gen_rtx_EXPR_LIST (VOIDmode,
5584 gen_rtx_REG (mode1, FP_RETURN),
5586 gen_rtx_EXPR_LIST (VOIDmode,
5587 gen_rtx_REG (mode2, FP_RETURN + inc),
5588 GEN_INT (offset2))));
5592 /* Implement TARGET_FUNCTION_VALUE and TARGET_LIBCALL_VALUE.
5593 For normal calls, VALTYPE is the return type and MODE is VOIDmode.
5594 For libcalls, VALTYPE is null and MODE is the mode of the return value. */
5597 mips_function_value_1 (const_tree valtype, const_tree fn_decl_or_type,
5598 enum machine_mode mode)
5606 if (fn_decl_or_type && DECL_P (fn_decl_or_type))
5607 func = fn_decl_or_type;
5611 mode = TYPE_MODE (valtype);
5612 unsigned_p = TYPE_UNSIGNED (valtype);
5614 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
5615 return values, promote the mode here too. */
5616 mode = promote_function_mode (valtype, mode, &unsigned_p, func, 1);
5618 /* Handle structures whose fields are returned in $f0/$f2. */
5619 switch (mips_fpr_return_fields (valtype, fields))
5622 return mips_return_fpr_single (mode,
5623 TYPE_MODE (TREE_TYPE (fields[0])));
5626 return mips_return_fpr_pair (mode,
5627 TYPE_MODE (TREE_TYPE (fields[0])),
5628 int_byte_position (fields[0]),
5629 TYPE_MODE (TREE_TYPE (fields[1])),
5630 int_byte_position (fields[1]));
5633 /* If a value is passed in the most significant part of a register, see
5634 whether we have to round the mode up to a whole number of words. */
5635 if (mips_return_in_msb (valtype))
5637 HOST_WIDE_INT size = int_size_in_bytes (valtype);
5638 if (size % UNITS_PER_WORD != 0)
5640 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
5641 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
5645 /* For EABI, the class of return register depends entirely on MODE.
5646 For example, "struct { some_type x; }" and "union { some_type x; }"
5647 are returned in the same way as a bare "some_type" would be.
5648 Other ABIs only use FPRs for scalar, complex or vector types. */
5649 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
5650 return gen_rtx_REG (mode, GP_RETURN);
5655 /* Handle long doubles for n32 & n64. */
5657 return mips_return_fpr_pair (mode,
5659 DImode, GET_MODE_SIZE (mode) / 2);
5661 if (mips_return_mode_in_fpr_p (mode))
5663 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5664 return mips_return_fpr_pair (mode,
5665 GET_MODE_INNER (mode), 0,
5666 GET_MODE_INNER (mode),
5667 GET_MODE_SIZE (mode) / 2);
5669 return gen_rtx_REG (mode, FP_RETURN);
5673 return gen_rtx_REG (mode, GP_RETURN);
5676 /* Implement TARGET_FUNCTION_VALUE. */
5679 mips_function_value (const_tree valtype, const_tree fn_decl_or_type,
5680 bool outgoing ATTRIBUTE_UNUSED)
5682 return mips_function_value_1 (valtype, fn_decl_or_type, VOIDmode);
5685 /* Implement TARGET_LIBCALL_VALUE. */
5688 mips_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
5690 return mips_function_value_1 (NULL_TREE, NULL_TREE, mode);
5693 /* Implement TARGET_FUNCTION_VALUE_REGNO_P.
5695 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
5696 Currently, R2 and F0 are only implemented here (C has no complex type). */
5699 mips_function_value_regno_p (const unsigned int regno)
5701 if (regno == GP_RETURN
5702 || regno == FP_RETURN
5703 || (LONG_DOUBLE_TYPE_SIZE == 128
5704 && FP_RETURN != GP_RETURN
5705 && regno == FP_RETURN + 2))
5711 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
5712 all BLKmode objects are returned in memory. Under the n32, n64
5713 and embedded ABIs, small structures are returned in a register.
5714 Objects with varying size must still be returned in memory, of
5718 mips_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
5720 return (TARGET_OLDABI
5721 ? TYPE_MODE (type) == BLKmode
5722 : !IN_RANGE (int_size_in_bytes (type), 0, 2 * UNITS_PER_WORD));
5725 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
5728 mips_setup_incoming_varargs (cumulative_args_t cum, enum machine_mode mode,
5729 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5732 CUMULATIVE_ARGS local_cum;
5733 int gp_saved, fp_saved;
5735 /* The caller has advanced CUM up to, but not beyond, the last named
5736 argument. Advance a local copy of CUM past the last "real" named
5737 argument, to find out how many registers are left over. */
5738 local_cum = *get_cumulative_args (cum);
5739 mips_function_arg_advance (pack_cumulative_args (&local_cum), mode, type,
5742 /* Found out how many registers we need to save. */
5743 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
5744 fp_saved = (EABI_FLOAT_VARARGS_P
5745 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
5754 ptr = plus_constant (Pmode, virtual_incoming_args_rtx,
5755 REG_PARM_STACK_SPACE (cfun->decl)
5756 - gp_saved * UNITS_PER_WORD);
5757 mem = gen_frame_mem (BLKmode, ptr);
5758 set_mem_alias_set (mem, get_varargs_alias_set ());
5760 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
5765 /* We can't use move_block_from_reg, because it will use
5767 enum machine_mode mode;
5770 /* Set OFF to the offset from virtual_incoming_args_rtx of
5771 the first float register. The FP save area lies below
5772 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
5773 off = (-gp_saved * UNITS_PER_WORD) & -UNITS_PER_FPVALUE;
5774 off -= fp_saved * UNITS_PER_FPREG;
5776 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
5778 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS;
5779 i += MAX_FPRS_PER_FMT)
5783 ptr = plus_constant (Pmode, virtual_incoming_args_rtx, off);
5784 mem = gen_frame_mem (mode, ptr);
5785 set_mem_alias_set (mem, get_varargs_alias_set ());
5786 mips_emit_move (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
5787 off += UNITS_PER_HWFPVALUE;
5791 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
5792 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
5793 + fp_saved * UNITS_PER_FPREG);
5796 /* Implement TARGET_BUILTIN_VA_LIST. */
5799 mips_build_builtin_va_list (void)
5801 if (EABI_FLOAT_VARARGS_P)
5803 /* We keep 3 pointers, and two offsets.
5805 Two pointers are to the overflow area, which starts at the CFA.
5806 One of these is constant, for addressing into the GPR save area
5807 below it. The other is advanced up the stack through the
5810 The third pointer is to the bottom of the GPR save area.
5811 Since the FPR save area is just below it, we can address
5812 FPR slots off this pointer.
5814 We also keep two one-byte offsets, which are to be subtracted
5815 from the constant pointers to yield addresses in the GPR and
5816 FPR save areas. These are downcounted as float or non-float
5817 arguments are used, and when they get to zero, the argument
5818 must be obtained from the overflow region. */
5819 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
5822 record = lang_hooks.types.make_type (RECORD_TYPE);
5824 f_ovfl = build_decl (BUILTINS_LOCATION,
5825 FIELD_DECL, get_identifier ("__overflow_argptr"),
5827 f_gtop = build_decl (BUILTINS_LOCATION,
5828 FIELD_DECL, get_identifier ("__gpr_top"),
5830 f_ftop = build_decl (BUILTINS_LOCATION,
5831 FIELD_DECL, get_identifier ("__fpr_top"),
5833 f_goff = build_decl (BUILTINS_LOCATION,
5834 FIELD_DECL, get_identifier ("__gpr_offset"),
5835 unsigned_char_type_node);
5836 f_foff = build_decl (BUILTINS_LOCATION,
5837 FIELD_DECL, get_identifier ("__fpr_offset"),
5838 unsigned_char_type_node);
5839 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
5840 warn on every user file. */
5841 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
5842 array = build_array_type (unsigned_char_type_node,
5843 build_index_type (index));
5844 f_res = build_decl (BUILTINS_LOCATION,
5845 FIELD_DECL, get_identifier ("__reserved"), array);
5847 DECL_FIELD_CONTEXT (f_ovfl) = record;
5848 DECL_FIELD_CONTEXT (f_gtop) = record;
5849 DECL_FIELD_CONTEXT (f_ftop) = record;
5850 DECL_FIELD_CONTEXT (f_goff) = record;
5851 DECL_FIELD_CONTEXT (f_foff) = record;
5852 DECL_FIELD_CONTEXT (f_res) = record;
5854 TYPE_FIELDS (record) = f_ovfl;
5855 DECL_CHAIN (f_ovfl) = f_gtop;
5856 DECL_CHAIN (f_gtop) = f_ftop;
5857 DECL_CHAIN (f_ftop) = f_goff;
5858 DECL_CHAIN (f_goff) = f_foff;
5859 DECL_CHAIN (f_foff) = f_res;
5861 layout_type (record);
5865 /* Otherwise, we use 'void *'. */
5866 return ptr_type_node;
5869 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
5872 mips_va_start (tree valist, rtx nextarg)
5874 if (EABI_FLOAT_VARARGS_P)
5876 const CUMULATIVE_ARGS *cum;
5877 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5878 tree ovfl, gtop, ftop, goff, foff;
5880 int gpr_save_area_size;
5881 int fpr_save_area_size;
5884 cum = &crtl->args.info;
5886 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
5888 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
5890 f_ovfl = TYPE_FIELDS (va_list_type_node);
5891 f_gtop = DECL_CHAIN (f_ovfl);
5892 f_ftop = DECL_CHAIN (f_gtop);
5893 f_goff = DECL_CHAIN (f_ftop);
5894 f_foff = DECL_CHAIN (f_goff);
5896 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5898 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
5900 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
5902 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
5904 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
5907 /* Emit code to initialize OVFL, which points to the next varargs
5908 stack argument. CUM->STACK_WORDS gives the number of stack
5909 words used by named arguments. */
5910 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
5911 if (cum->stack_words > 0)
5912 t = fold_build_pointer_plus_hwi (t, cum->stack_words * UNITS_PER_WORD);
5913 t = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
5914 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5916 /* Emit code to initialize GTOP, the top of the GPR save area. */
5917 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
5918 t = build2 (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
5919 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5921 /* Emit code to initialize FTOP, the top of the FPR save area.
5922 This address is gpr_save_area_bytes below GTOP, rounded
5923 down to the next fp-aligned boundary. */
5924 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
5925 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
5926 fpr_offset &= -UNITS_PER_FPVALUE;
5928 t = fold_build_pointer_plus_hwi (t, -fpr_offset);
5929 t = build2 (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
5930 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5932 /* Emit code to initialize GOFF, the offset from GTOP of the
5933 next GPR argument. */
5934 t = build2 (MODIFY_EXPR, TREE_TYPE (goff), goff,
5935 build_int_cst (TREE_TYPE (goff), gpr_save_area_size));
5936 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5938 /* Likewise emit code to initialize FOFF, the offset from FTOP
5939 of the next FPR argument. */
5940 t = build2 (MODIFY_EXPR, TREE_TYPE (foff), foff,
5941 build_int_cst (TREE_TYPE (foff), fpr_save_area_size));
5942 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5946 nextarg = plus_constant (Pmode, nextarg, -cfun->machine->varargs_size);
5947 std_expand_builtin_va_start (valist, nextarg);
5951 /* Like std_gimplify_va_arg_expr, but apply alignment to zero-sized
5955 mips_std_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
5958 tree addr, t, type_size, rounded_size, valist_tmp;
5959 unsigned HOST_WIDE_INT align, boundary;
5962 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, false);
5964 type = build_pointer_type (type);
5966 align = PARM_BOUNDARY / BITS_PER_UNIT;
5967 boundary = targetm.calls.function_arg_boundary (TYPE_MODE (type), type);
5969 /* When we align parameter on stack for caller, if the parameter
5970 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
5971 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
5972 here with caller. */
5973 if (boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
5974 boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
5976 boundary /= BITS_PER_UNIT;
5978 /* Hoist the valist value into a temporary for the moment. */
5979 valist_tmp = get_initialized_tmp_var (valist, pre_p, NULL);
5981 /* va_list pointer is aligned to PARM_BOUNDARY. If argument actually
5982 requires greater alignment, we must perform dynamic alignment. */
5983 if (boundary > align)
5985 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
5986 fold_build_pointer_plus_hwi (valist_tmp, boundary - 1));
5987 gimplify_and_add (t, pre_p);
5989 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
5990 fold_build2 (BIT_AND_EXPR, TREE_TYPE (valist),
5992 build_int_cst (TREE_TYPE (valist), -boundary)));
5993 gimplify_and_add (t, pre_p);
5998 /* If the actual alignment is less than the alignment of the type,
5999 adjust the type accordingly so that we don't assume strict alignment
6000 when dereferencing the pointer. */
6001 boundary *= BITS_PER_UNIT;
6002 if (boundary < TYPE_ALIGN (type))
6004 type = build_variant_type_copy (type);
6005 TYPE_ALIGN (type) = boundary;
6008 /* Compute the rounded size of the type. */
6009 type_size = size_in_bytes (type);
6010 rounded_size = round_up (type_size, align);
6012 /* Reduce rounded_size so it's sharable with the postqueue. */
6013 gimplify_expr (&rounded_size, pre_p, post_p, is_gimple_val, fb_rvalue);
6017 if (PAD_VARARGS_DOWN && !integer_zerop (rounded_size))
6019 /* Small args are padded downward. */
6020 t = fold_build2_loc (input_location, GT_EXPR, sizetype,
6021 rounded_size, size_int (align));
6022 t = fold_build3 (COND_EXPR, sizetype, t, size_zero_node,
6023 size_binop (MINUS_EXPR, rounded_size, type_size));
6024 addr = fold_build_pointer_plus (addr, t);
6027 /* Compute new value for AP. */
6028 t = fold_build_pointer_plus (valist_tmp, rounded_size);
6029 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
6030 gimplify_and_add (t, pre_p);
6032 addr = fold_convert (build_pointer_type (type), addr);
6035 addr = build_va_arg_indirect_ref (addr);
6037 return build_va_arg_indirect_ref (addr);
6040 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
6043 mips_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
6049 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
6051 type = build_pointer_type (type);
6053 if (!EABI_FLOAT_VARARGS_P)
6054 addr = mips_std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6057 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
6058 tree ovfl, top, off, align;
6059 HOST_WIDE_INT size, rsize, osize;
6062 f_ovfl = TYPE_FIELDS (va_list_type_node);
6063 f_gtop = DECL_CHAIN (f_ovfl);
6064 f_ftop = DECL_CHAIN (f_gtop);
6065 f_goff = DECL_CHAIN (f_ftop);
6066 f_foff = DECL_CHAIN (f_goff);
6070 TOP be the top of the GPR or FPR save area;
6071 OFF be the offset from TOP of the next register;
6072 ADDR_RTX be the address of the argument;
6073 SIZE be the number of bytes in the argument type;
6074 RSIZE be the number of bytes used to store the argument
6075 when it's in the register save area; and
6076 OSIZE be the number of bytes used to store it when it's
6077 in the stack overflow area.
6079 The code we want is:
6081 1: off &= -rsize; // round down
6084 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
6089 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
6090 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
6094 [1] and [9] can sometimes be optimized away. */
6096 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
6098 size = int_size_in_bytes (type);
6100 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
6101 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
6103 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop),
6104 unshare_expr (valist), f_ftop, NULL_TREE);
6105 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff),
6106 unshare_expr (valist), f_foff, NULL_TREE);
6108 /* When va_start saves FPR arguments to the stack, each slot
6109 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
6110 argument's precision. */
6111 rsize = UNITS_PER_HWFPVALUE;
6113 /* Overflow arguments are padded to UNITS_PER_WORD bytes
6114 (= PARM_BOUNDARY bits). This can be different from RSIZE
6117 (1) On 32-bit targets when TYPE is a structure such as:
6119 struct s { float f; };
6121 Such structures are passed in paired FPRs, so RSIZE
6122 will be 8 bytes. However, the structure only takes
6123 up 4 bytes of memory, so OSIZE will only be 4.
6125 (2) In combinations such as -mgp64 -msingle-float
6126 -fshort-double. Doubles passed in registers will then take
6127 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
6128 stack take up UNITS_PER_WORD bytes. */
6129 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
6133 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop),
6134 unshare_expr (valist), f_gtop, NULL_TREE);
6135 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff),
6136 unshare_expr (valist), f_goff, NULL_TREE);
6137 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
6138 if (rsize > UNITS_PER_WORD)
6140 /* [1] Emit code for: off &= -rsize. */
6141 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), unshare_expr (off),
6142 build_int_cst (TREE_TYPE (off), -rsize));
6143 gimplify_assign (unshare_expr (off), t, pre_p);
6148 /* [2] Emit code to branch if off == 0. */
6149 t = build2 (NE_EXPR, boolean_type_node, unshare_expr (off),
6150 build_int_cst (TREE_TYPE (off), 0));
6151 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
6153 /* [5] Emit code for: off -= rsize. We do this as a form of
6154 post-decrement not available to C. */
6155 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
6156 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
6158 /* [4] Emit code for:
6159 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
6160 t = fold_convert (sizetype, t);
6161 t = fold_build1 (NEGATE_EXPR, sizetype, t);
6162 t = fold_build_pointer_plus (top, t);
6163 if (BYTES_BIG_ENDIAN && rsize > size)
6164 t = fold_build_pointer_plus_hwi (t, rsize - size);
6165 COND_EXPR_THEN (addr) = t;
6167 if (osize > UNITS_PER_WORD)
6169 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
6170 t = fold_build_pointer_plus_hwi (unshare_expr (ovfl), osize - 1);
6171 u = build_int_cst (TREE_TYPE (t), -osize);
6172 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t, u);
6173 align = build2 (MODIFY_EXPR, TREE_TYPE (ovfl),
6174 unshare_expr (ovfl), t);
6179 /* [10, 11] Emit code for:
6180 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
6182 u = fold_convert (TREE_TYPE (ovfl), build_int_cst (NULL_TREE, osize));
6183 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
6184 if (BYTES_BIG_ENDIAN && osize > size)
6185 t = fold_build_pointer_plus_hwi (t, osize - size);
6187 /* String [9] and [10, 11] together. */
6189 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
6190 COND_EXPR_ELSE (addr) = t;
6192 addr = fold_convert (build_pointer_type (type), addr);
6193 addr = build_va_arg_indirect_ref (addr);
6197 addr = build_va_arg_indirect_ref (addr);
6202 /* Declare a unique, locally-binding function called NAME, then start
6206 mips_start_unique_function (const char *name)
6210 decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
6211 get_identifier (name),
6212 build_function_type_list (void_type_node, NULL_TREE));
6213 DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
6214 NULL_TREE, void_type_node);
6215 TREE_PUBLIC (decl) = 1;
6216 TREE_STATIC (decl) = 1;
6218 DECL_COMDAT_GROUP (decl) = DECL_ASSEMBLER_NAME (decl);
6220 targetm.asm_out.unique_section (decl, 0);
6221 switch_to_section (get_named_section (decl, NULL, 0));
6223 targetm.asm_out.globalize_label (asm_out_file, name);
6224 fputs ("\t.hidden\t", asm_out_file);
6225 assemble_name (asm_out_file, name);
6226 putc ('\n', asm_out_file);
6229 /* Start a definition of function NAME. MIPS16_P indicates whether the
6230 function contains MIPS16 code. */
6233 mips_start_function_definition (const char *name, bool mips16_p)
6236 fprintf (asm_out_file, "\t.set\tmips16\n");
6238 fprintf (asm_out_file, "\t.set\tnomips16\n");
6240 if (TARGET_MICROMIPS)
6241 fprintf (asm_out_file, "\t.set\tmicromips\n");
6242 #ifdef HAVE_GAS_MICROMIPS
6244 fprintf (asm_out_file, "\t.set\tnomicromips\n");
6247 if (!flag_inhibit_size_directive)
6249 fputs ("\t.ent\t", asm_out_file);
6250 assemble_name (asm_out_file, name);
6251 fputs ("\n", asm_out_file);
6254 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, name, "function");
6256 /* Start the definition proper. */
6257 assemble_name (asm_out_file, name);
6258 fputs (":\n", asm_out_file);
6261 /* End a function definition started by mips_start_function_definition. */
6264 mips_end_function_definition (const char *name)
6266 if (!flag_inhibit_size_directive)
6268 fputs ("\t.end\t", asm_out_file);
6269 assemble_name (asm_out_file, name);
6270 fputs ("\n", asm_out_file);
6274 /* Output a definition of the __mips16_rdhwr function. */
6277 mips_output_mips16_rdhwr (void)
6281 name = "__mips16_rdhwr";
6282 mips_start_unique_function (name);
6283 mips_start_function_definition (name, false);
6284 fprintf (asm_out_file,
6286 "\t.set\tmips32r2\n"
6287 "\t.set\tnoreorder\n"
6291 mips_end_function_definition (name);
6294 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
6297 mips_ok_for_lazy_binding_p (rtx x)
6299 return (TARGET_USE_GOT
6300 && GET_CODE (x) == SYMBOL_REF
6301 && !SYMBOL_REF_BIND_NOW_P (x)
6302 && !mips_symbol_binds_local_p (x));
6305 /* Load function address ADDR into register DEST. TYPE is as for
6306 mips_expand_call. Return true if we used an explicit lazy-binding
6310 mips_load_call_address (enum mips_call_type type, rtx dest, rtx addr)
6312 /* If we're generating PIC, and this call is to a global function,
6313 try to allow its address to be resolved lazily. This isn't
6314 possible for sibcalls when $gp is call-saved because the value
6315 of $gp on entry to the stub would be our caller's gp, not ours. */
6316 if (TARGET_EXPLICIT_RELOCS
6317 && !(type == MIPS_CALL_SIBCALL && TARGET_CALL_SAVED_GP)
6318 && mips_ok_for_lazy_binding_p (addr))
6320 addr = mips_got_load (dest, addr, SYMBOL_GOTOFF_CALL);
6321 emit_insn (gen_rtx_SET (VOIDmode, dest, addr));
6326 mips_emit_move (dest, addr);
6331 /* Each locally-defined hard-float MIPS16 function has a local symbol
6332 associated with it. This hash table maps the function symbol (FUNC)
6333 to the local symbol (LOCAL). */
6334 struct GTY(()) mips16_local_alias {
6338 static GTY ((param_is (struct mips16_local_alias))) htab_t mips16_local_aliases;
6340 /* Hash table callbacks for mips16_local_aliases. */
6343 mips16_local_aliases_hash (const void *entry)
6345 const struct mips16_local_alias *alias;
6347 alias = (const struct mips16_local_alias *) entry;
6348 return htab_hash_string (XSTR (alias->func, 0));
6352 mips16_local_aliases_eq (const void *entry1, const void *entry2)
6354 const struct mips16_local_alias *alias1, *alias2;
6356 alias1 = (const struct mips16_local_alias *) entry1;
6357 alias2 = (const struct mips16_local_alias *) entry2;
6358 return rtx_equal_p (alias1->func, alias2->func);
6361 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
6362 Return a local alias for it, creating a new one if necessary. */
6365 mips16_local_alias (rtx func)
6367 struct mips16_local_alias *alias, tmp_alias;
6370 /* Create the hash table if this is the first call. */
6371 if (mips16_local_aliases == NULL)
6372 mips16_local_aliases = htab_create_ggc (37, mips16_local_aliases_hash,
6373 mips16_local_aliases_eq, NULL);
6375 /* Look up the function symbol, creating a new entry if need be. */
6376 tmp_alias.func = func;
6377 slot = htab_find_slot (mips16_local_aliases, &tmp_alias, INSERT);
6378 gcc_assert (slot != NULL);
6380 alias = (struct mips16_local_alias *) *slot;
6383 const char *func_name, *local_name;
6386 /* Create a new SYMBOL_REF for the local symbol. The choice of
6387 __fn_local_* is based on the __fn_stub_* names that we've
6388 traditionally used for the non-MIPS16 stub. */
6389 func_name = targetm.strip_name_encoding (XSTR (func, 0));
6390 local_name = ACONCAT (("__fn_local_", func_name, NULL));
6391 local = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (local_name));
6392 SYMBOL_REF_FLAGS (local) = SYMBOL_REF_FLAGS (func) | SYMBOL_FLAG_LOCAL;
6394 /* Create a new structure to represent the mapping. */
6395 alias = ggc_alloc_mips16_local_alias ();
6397 alias->local = local;
6400 return alias->local;
6403 /* A chained list of functions for which mips16_build_call_stub has already
6404 generated a stub. NAME is the name of the function and FP_RET_P is true
6405 if the function returns a value in floating-point registers. */
6406 struct mips16_stub {
6407 struct mips16_stub *next;
6411 static struct mips16_stub *mips16_stubs;
6413 /* Return the two-character string that identifies floating-point
6414 return mode MODE in the name of a MIPS16 function stub. */
6417 mips16_call_stub_mode_suffix (enum machine_mode mode)
6421 else if (mode == DFmode)
6423 else if (mode == SCmode)
6425 else if (mode == DCmode)
6427 else if (mode == V2SFmode)
6433 /* Write instructions to move a 32-bit value between general register
6434 GPREG and floating-point register FPREG. DIRECTION is 't' to move
6435 from GPREG to FPREG and 'f' to move in the opposite direction. */
6438 mips_output_32bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
6440 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6441 reg_names[gpreg], reg_names[fpreg]);
6444 /* Likewise for 64-bit values. */
6447 mips_output_64bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
6450 fprintf (asm_out_file, "\tdm%cc1\t%s,%s\n", direction,
6451 reg_names[gpreg], reg_names[fpreg]);
6452 else if (TARGET_FLOAT64)
6454 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6455 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
6456 fprintf (asm_out_file, "\tm%chc1\t%s,%s\n", direction,
6457 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg]);
6461 /* Move the least-significant word. */
6462 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6463 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
6464 /* ...then the most significant word. */
6465 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6466 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg + 1]);
6470 /* Write out code to move floating-point arguments into or out of
6471 general registers. FP_CODE is the code describing which arguments
6472 are present (see the comment above the definition of CUMULATIVE_ARGS
6473 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
6476 mips_output_args_xfer (int fp_code, char direction)
6478 unsigned int gparg, fparg, f;
6479 CUMULATIVE_ARGS cum;
6481 /* This code only works for o32 and o64. */
6482 gcc_assert (TARGET_OLDABI);
6484 mips_init_cumulative_args (&cum, NULL);
6486 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
6488 enum machine_mode mode;
6489 struct mips_arg_info info;
6493 else if ((f & 3) == 2)
6498 mips_get_arg_info (&info, &cum, mode, NULL, true);
6499 gparg = mips_arg_regno (&info, false);
6500 fparg = mips_arg_regno (&info, true);
6503 mips_output_32bit_xfer (direction, gparg, fparg);
6505 mips_output_64bit_xfer (direction, gparg, fparg);
6507 mips_function_arg_advance (pack_cumulative_args (&cum), mode, NULL, true);
6511 /* Write a MIPS16 stub for the current function. This stub is used
6512 for functions which take arguments in the floating-point registers.
6513 It is normal-mode code that moves the floating-point arguments
6514 into the general registers and then jumps to the MIPS16 code. */
6517 mips16_build_function_stub (void)
6519 const char *fnname, *alias_name, *separator;
6520 char *secname, *stubname;
6525 /* Create the name of the stub, and its unique section. */
6526 symbol = XEXP (DECL_RTL (current_function_decl), 0);
6527 alias = mips16_local_alias (symbol);
6529 fnname = targetm.strip_name_encoding (XSTR (symbol, 0));
6530 alias_name = targetm.strip_name_encoding (XSTR (alias, 0));
6531 secname = ACONCAT ((".mips16.fn.", fnname, NULL));
6532 stubname = ACONCAT (("__fn_stub_", fnname, NULL));
6534 /* Build a decl for the stub. */
6535 stubdecl = build_decl (BUILTINS_LOCATION,
6536 FUNCTION_DECL, get_identifier (stubname),
6537 build_function_type_list (void_type_node, NULL_TREE));
6538 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
6539 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
6540 RESULT_DECL, NULL_TREE, void_type_node);
6542 /* Output a comment. */
6543 fprintf (asm_out_file, "\t# Stub function for %s (",
6544 current_function_name ());
6546 for (f = (unsigned int) crtl->args.info.fp_code; f != 0; f >>= 2)
6548 fprintf (asm_out_file, "%s%s", separator,
6549 (f & 3) == 1 ? "float" : "double");
6552 fprintf (asm_out_file, ")\n");
6554 /* Start the function definition. */
6555 assemble_start_function (stubdecl, stubname);
6556 mips_start_function_definition (stubname, false);
6558 /* If generating pic2 code, either set up the global pointer or
6560 if (TARGET_ABICALLS_PIC2)
6562 if (TARGET_ABSOLUTE_ABICALLS)
6563 fprintf (asm_out_file, "\t.option\tpic0\n");
6566 output_asm_insn ("%(.cpload\t%^%)", NULL);
6567 /* Emit an R_MIPS_NONE relocation to tell the linker what the
6568 target function is. Use a local GOT access when loading the
6569 symbol, to cut down on the number of unnecessary GOT entries
6570 for stubs that aren't needed. */
6571 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol);
6576 /* Load the address of the MIPS16 function into $25. Do this first so
6577 that targets with coprocessor interlocks can use an MFC1 to fill the
6579 output_asm_insn ("la\t%^,%0", &symbol);
6581 /* Move the arguments from floating-point registers to general registers. */
6582 mips_output_args_xfer (crtl->args.info.fp_code, 'f');
6584 /* Jump to the MIPS16 function. */
6585 output_asm_insn ("jr\t%^", NULL);
6587 if (TARGET_ABICALLS_PIC2 && TARGET_ABSOLUTE_ABICALLS)
6588 fprintf (asm_out_file, "\t.option\tpic2\n");
6590 mips_end_function_definition (stubname);
6592 /* If the linker needs to create a dynamic symbol for the target
6593 function, it will associate the symbol with the stub (which,
6594 unlike the target function, follows the proper calling conventions).
6595 It is therefore useful to have a local alias for the target function,
6596 so that it can still be identified as MIPS16 code. As an optimization,
6597 this symbol can also be used for indirect MIPS16 references from
6598 within this file. */
6599 ASM_OUTPUT_DEF (asm_out_file, alias_name, fnname);
6601 switch_to_section (function_section (current_function_decl));
6604 /* The current function is a MIPS16 function that returns a value in an FPR.
6605 Copy the return value from its soft-float to its hard-float location.
6606 libgcc2 has special non-MIPS16 helper functions for each case. */
6609 mips16_copy_fpr_return_value (void)
6611 rtx fn, insn, retval;
6613 enum machine_mode return_mode;
6616 return_type = DECL_RESULT (current_function_decl);
6617 return_mode = DECL_MODE (return_type);
6619 name = ACONCAT (("__mips16_ret_",
6620 mips16_call_stub_mode_suffix (return_mode),
6622 fn = mips16_stub_function (name);
6624 /* The function takes arguments in $2 (and possibly $3), so calls
6625 to it cannot be lazily bound. */
6626 SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_BIND_NOW;
6628 /* Model the call as something that takes the GPR return value as
6629 argument and returns an "updated" value. */
6630 retval = gen_rtx_REG (return_mode, GP_RETURN);
6631 insn = mips_expand_call (MIPS_CALL_EPILOGUE, retval, fn,
6632 const0_rtx, NULL_RTX, false);
6633 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), retval);
6636 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
6637 RETVAL is the location of the return value, or null if this is
6638 a "call" rather than a "call_value". ARGS_SIZE is the size of the
6639 arguments and FP_CODE is the code built by mips_function_arg;
6640 see the comment before the fp_code field in CUMULATIVE_ARGS for details.
6642 There are three alternatives:
6644 - If a stub was needed, emit the call and return the call insn itself.
6646 - If we can avoid using a stub by redirecting the call, set *FN_PTR
6647 to the new target and return null.
6649 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
6652 A stub is needed for calls to functions that, in normal mode,
6653 receive arguments in FPRs or return values in FPRs. The stub
6654 copies the arguments from their soft-float positions to their
6655 hard-float positions, calls the real function, then copies the
6656 return value from its hard-float position to its soft-float
6659 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
6660 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
6661 automatically redirects the JAL to the stub, otherwise the JAL
6662 continues to call FN directly. */
6665 mips16_build_call_stub (rtx retval, rtx *fn_ptr, rtx args_size, int fp_code)
6669 struct mips16_stub *l;
6672 /* We don't need to do anything if we aren't in MIPS16 mode, or if
6673 we were invoked with the -msoft-float option. */
6674 if (!TARGET_MIPS16 || TARGET_SOFT_FLOAT_ABI)
6677 /* Figure out whether the value might come back in a floating-point
6679 fp_ret_p = retval && mips_return_mode_in_fpr_p (GET_MODE (retval));
6681 /* We don't need to do anything if there were no floating-point
6682 arguments and the value will not be returned in a floating-point
6684 if (fp_code == 0 && !fp_ret_p)
6687 /* We don't need to do anything if this is a call to a special
6688 MIPS16 support function. */
6690 if (mips16_stub_function_p (fn))
6693 /* If we're calling a locally-defined MIPS16 function, we know that
6694 it will return values in both the "soft-float" and "hard-float"
6695 registers. There is no need to use a stub to move the latter
6697 if (fp_code == 0 && mips16_local_function_p (fn))
6700 /* This code will only work for o32 and o64 abis. The other ABI's
6701 require more sophisticated support. */
6702 gcc_assert (TARGET_OLDABI);
6704 /* If we're calling via a function pointer, use one of the magic
6705 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
6706 Each stub expects the function address to arrive in register $2. */
6707 if (GET_CODE (fn) != SYMBOL_REF
6708 || !call_insn_operand (fn, VOIDmode))
6711 rtx stub_fn, insn, addr;
6714 /* If this is a locally-defined and locally-binding function,
6715 avoid the stub by calling the local alias directly. */
6716 if (mips16_local_function_p (fn))
6718 *fn_ptr = mips16_local_alias (fn);
6722 /* Create a SYMBOL_REF for the libgcc.a function. */
6724 sprintf (buf, "__mips16_call_stub_%s_%d",
6725 mips16_call_stub_mode_suffix (GET_MODE (retval)),
6728 sprintf (buf, "__mips16_call_stub_%d", fp_code);
6729 stub_fn = mips16_stub_function (buf);
6731 /* The function uses $2 as an argument, so calls to it
6732 cannot be lazily bound. */
6733 SYMBOL_REF_FLAGS (stub_fn) |= SYMBOL_FLAG_BIND_NOW;
6735 /* Load the target function into $2. */
6736 addr = gen_rtx_REG (Pmode, GP_REG_FIRST + 2);
6737 lazy_p = mips_load_call_address (MIPS_CALL_NORMAL, addr, fn);
6739 /* Emit the call. */
6740 insn = mips_expand_call (MIPS_CALL_NORMAL, retval, stub_fn,
6741 args_size, NULL_RTX, lazy_p);
6743 /* Tell GCC that this call does indeed use the value of $2. */
6744 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), addr);
6746 /* If we are handling a floating-point return value, we need to
6747 save $18 in the function prologue. Putting a note on the
6748 call will mean that df_regs_ever_live_p ($18) will be true if the
6749 call is not eliminated, and we can check that in the prologue
6752 CALL_INSN_FUNCTION_USAGE (insn) =
6753 gen_rtx_EXPR_LIST (VOIDmode,
6754 gen_rtx_CLOBBER (VOIDmode,
6755 gen_rtx_REG (word_mode, 18)),
6756 CALL_INSN_FUNCTION_USAGE (insn));
6761 /* We know the function we are going to call. If we have already
6762 built a stub, we don't need to do anything further. */
6763 fnname = targetm.strip_name_encoding (XSTR (fn, 0));
6764 for (l = mips16_stubs; l != NULL; l = l->next)
6765 if (strcmp (l->name, fnname) == 0)
6770 const char *separator;
6771 char *secname, *stubname;
6772 tree stubid, stubdecl;
6775 /* If the function does not return in FPRs, the special stub
6779 If the function does return in FPRs, the stub section is named
6780 .mips16.call.fp.FNNAME
6782 Build a decl for the stub. */
6783 secname = ACONCAT ((".mips16.call.", fp_ret_p ? "fp." : "",
6785 stubname = ACONCAT (("__call_stub_", fp_ret_p ? "fp_" : "",
6787 stubid = get_identifier (stubname);
6788 stubdecl = build_decl (BUILTINS_LOCATION,
6789 FUNCTION_DECL, stubid,
6790 build_function_type_list (void_type_node,
6792 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
6793 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
6794 RESULT_DECL, NULL_TREE,
6797 /* Output a comment. */
6798 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
6800 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
6804 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
6806 fprintf (asm_out_file, "%s%s", separator,
6807 (f & 3) == 1 ? "float" : "double");
6810 fprintf (asm_out_file, ")\n");
6812 /* Start the function definition. */
6813 assemble_start_function (stubdecl, stubname);
6814 mips_start_function_definition (stubname, false);
6818 fprintf (asm_out_file, "\t.cfi_startproc\n");
6820 /* Create a fake CFA 4 bytes below the stack pointer.
6821 This works around unwinders (like libgcc's) that expect
6822 the CFA for non-signal frames to be unique. */
6823 fprintf (asm_out_file, "\t.cfi_def_cfa 29,-4\n");
6825 /* "Save" $sp in itself so we don't use the fake CFA.
6826 This is: DW_CFA_val_expression r29, { DW_OP_reg29 }. */
6827 fprintf (asm_out_file, "\t.cfi_escape 0x16,29,1,0x6d\n");
6831 /* Load the address of the MIPS16 function into $25. Do this
6832 first so that targets with coprocessor interlocks can use
6833 an MFC1 to fill the delay slot. */
6834 if (TARGET_EXPLICIT_RELOCS)
6836 output_asm_insn ("lui\t%^,%%hi(%0)", &fn);
6837 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn);
6840 output_asm_insn ("la\t%^,%0", &fn);
6843 /* Move the arguments from general registers to floating-point
6845 mips_output_args_xfer (fp_code, 't');
6849 /* Save the return address in $18 and call the non-MIPS16 function.
6850 The stub's caller knows that $18 might be clobbered, even though
6851 $18 is usually a call-saved register. */
6852 fprintf (asm_out_file, "\tmove\t%s,%s\n",
6853 reg_names[GP_REG_FIRST + 18], reg_names[RETURN_ADDR_REGNUM]);
6854 output_asm_insn (MIPS_CALL ("jal", &fn, 0, -1), &fn);
6855 fprintf (asm_out_file, "\t.cfi_register 31,18\n");
6857 /* Move the result from floating-point registers to
6858 general registers. */
6859 switch (GET_MODE (retval))
6862 mips_output_32bit_xfer ('f', GP_RETURN + TARGET_BIG_ENDIAN,
6864 ? FP_REG_FIRST + MAX_FPRS_PER_FMT
6866 mips_output_32bit_xfer ('f', GP_RETURN + TARGET_LITTLE_ENDIAN,
6867 TARGET_LITTLE_ENDIAN
6868 ? FP_REG_FIRST + MAX_FPRS_PER_FMT
6870 if (GET_MODE (retval) == SCmode && TARGET_64BIT)
6872 /* On 64-bit targets, complex floats are returned in
6873 a single GPR, such that "sd" on a suitably-aligned
6874 target would store the value correctly. */
6875 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
6876 reg_names[GP_RETURN + TARGET_BIG_ENDIAN],
6877 reg_names[GP_RETURN + TARGET_BIG_ENDIAN]);
6878 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
6879 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN],
6880 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN]);
6881 fprintf (asm_out_file, "\tdsrl\t%s,%s,32\n",
6882 reg_names[GP_RETURN + TARGET_BIG_ENDIAN],
6883 reg_names[GP_RETURN + TARGET_BIG_ENDIAN]);
6884 fprintf (asm_out_file, "\tor\t%s,%s,%s\n",
6885 reg_names[GP_RETURN],
6886 reg_names[GP_RETURN],
6887 reg_names[GP_RETURN + 1]);
6892 mips_output_32bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6896 mips_output_64bit_xfer ('f', GP_RETURN + (8 / UNITS_PER_WORD),
6897 FP_REG_FIRST + MAX_FPRS_PER_FMT);
6901 mips_output_64bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6907 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 18]);
6908 fprintf (asm_out_file, "\t.cfi_endproc\n");
6912 /* Jump to the previously-loaded address. */
6913 output_asm_insn ("jr\t%^", NULL);
6916 #ifdef ASM_DECLARE_FUNCTION_SIZE
6917 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
6920 mips_end_function_definition (stubname);
6922 /* Record this stub. */
6923 l = XNEW (struct mips16_stub);
6924 l->name = xstrdup (fnname);
6925 l->fp_ret_p = fp_ret_p;
6926 l->next = mips16_stubs;
6930 /* If we expect a floating-point return value, but we've built a
6931 stub which does not expect one, then we're in trouble. We can't
6932 use the existing stub, because it won't handle the floating-point
6933 value. We can't build a new stub, because the linker won't know
6934 which stub to use for the various calls in this object file.
6935 Fortunately, this case is illegal, since it means that a function
6936 was declared in two different ways in a single compilation. */
6937 if (fp_ret_p && !l->fp_ret_p)
6938 error ("cannot handle inconsistent calls to %qs", fnname);
6940 if (retval == NULL_RTX)
6941 insn = gen_call_internal_direct (fn, args_size);
6943 insn = gen_call_value_internal_direct (retval, fn, args_size);
6944 insn = mips_emit_call_insn (insn, fn, fn, false);
6946 /* If we are calling a stub which handles a floating-point return
6947 value, we need to arrange to save $18 in the prologue. We do this
6948 by marking the function call as using the register. The prologue
6949 will later see that it is used, and emit code to save it. */
6951 CALL_INSN_FUNCTION_USAGE (insn) =
6952 gen_rtx_EXPR_LIST (VOIDmode,
6953 gen_rtx_CLOBBER (VOIDmode,
6954 gen_rtx_REG (word_mode, 18)),
6955 CALL_INSN_FUNCTION_USAGE (insn));
6960 /* Expand a call of type TYPE. RESULT is where the result will go (null
6961 for "call"s and "sibcall"s), ADDR is the address of the function,
6962 ARGS_SIZE is the size of the arguments and AUX is the value passed
6963 to us by mips_function_arg. LAZY_P is true if this call already
6964 involves a lazily-bound function address (such as when calling
6965 functions through a MIPS16 hard-float stub).
6967 Return the call itself. */
6970 mips_expand_call (enum mips_call_type type, rtx result, rtx addr,
6971 rtx args_size, rtx aux, bool lazy_p)
6973 rtx orig_addr, pattern, insn;
6976 fp_code = aux == 0 ? 0 : (int) GET_MODE (aux);
6977 insn = mips16_build_call_stub (result, &addr, args_size, fp_code);
6980 gcc_assert (!lazy_p && type == MIPS_CALL_NORMAL);
6985 if (!call_insn_operand (addr, VOIDmode))
6987 if (type == MIPS_CALL_EPILOGUE)
6988 addr = MIPS_EPILOGUE_TEMP (Pmode);
6990 addr = gen_reg_rtx (Pmode);
6991 lazy_p |= mips_load_call_address (type, addr, orig_addr);
6996 rtx (*fn) (rtx, rtx);
6998 if (type == MIPS_CALL_SIBCALL)
6999 fn = gen_sibcall_internal;
7001 fn = gen_call_internal;
7003 pattern = fn (addr, args_size);
7005 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
7007 /* Handle return values created by mips_return_fpr_pair. */
7008 rtx (*fn) (rtx, rtx, rtx, rtx);
7011 if (type == MIPS_CALL_SIBCALL)
7012 fn = gen_sibcall_value_multiple_internal;
7014 fn = gen_call_value_multiple_internal;
7016 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
7017 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
7018 pattern = fn (reg1, addr, args_size, reg2);
7022 rtx (*fn) (rtx, rtx, rtx);
7024 if (type == MIPS_CALL_SIBCALL)
7025 fn = gen_sibcall_value_internal;
7027 fn = gen_call_value_internal;
7029 /* Handle return values created by mips_return_fpr_single. */
7030 if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 1)
7031 result = XEXP (XVECEXP (result, 0, 0), 0);
7032 pattern = fn (result, addr, args_size);
7035 return mips_emit_call_insn (pattern, orig_addr, addr, lazy_p);
7038 /* Split call instruction INSN into a $gp-clobbering call and
7039 (where necessary) an instruction to restore $gp from its save slot.
7040 CALL_PATTERN is the pattern of the new call. */
7043 mips_split_call (rtx insn, rtx call_pattern)
7045 emit_call_insn (call_pattern);
7046 if (!find_reg_note (insn, REG_NORETURN, 0))
7047 /* Pick a temporary register that is suitable for both MIPS16 and
7048 non-MIPS16 code. $4 and $5 are used for returning complex double
7049 values in soft-float code, so $6 is the first suitable candidate. */
7050 mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode, GP_ARG_FIRST + 2));
7053 /* Return true if a call to DECL may need to use JALX. */
7056 mips_call_may_need_jalx_p (tree decl)
7058 /* If the current translation unit would use a different mode for DECL,
7059 assume that the call needs JALX. */
7060 if (mips_get_compress_mode (decl) != TARGET_COMPRESSION)
7063 /* mips_get_compress_mode is always accurate for locally-binding
7064 functions in the current translation unit. */
7065 if (!DECL_EXTERNAL (decl) && targetm.binds_local_p (decl))
7068 /* When -minterlink-compressed is in effect, assume that functions
7069 could use a different encoding mode unless an attribute explicitly
7070 tells us otherwise. */
7071 if (TARGET_INTERLINK_COMPRESSED)
7073 if (!TARGET_COMPRESSION
7074 && mips_get_compress_off_flags (DECL_ATTRIBUTES (decl)) ==0)
7076 if (TARGET_COMPRESSION
7077 && mips_get_compress_on_flags (DECL_ATTRIBUTES (decl)) == 0)
7084 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
7087 mips_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
7089 if (!TARGET_SIBCALLS)
7092 /* Interrupt handlers need special epilogue code and therefore can't
7094 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
7097 /* Direct Js are only possible to functions that use the same ISA encoding.
7098 There is no JX counterpoart of JALX. */
7100 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode)
7101 && mips_call_may_need_jalx_p (decl))
7108 /* Emit code to move general operand SRC into condition-code
7109 register DEST given that SCRATCH is a scratch TFmode FPR.
7116 where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */
7119 mips_expand_fcc_reload (rtx dest, rtx src, rtx scratch)
7123 /* Change the source to SFmode. */
7125 src = adjust_address (src, SFmode, 0);
7126 else if (REG_P (src) || GET_CODE (src) == SUBREG)
7127 src = gen_rtx_REG (SFmode, true_regnum (src));
7129 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
7130 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + MAX_FPRS_PER_FMT);
7132 mips_emit_move (copy_rtx (fp1), src);
7133 mips_emit_move (copy_rtx (fp2), CONST0_RTX (SFmode));
7134 emit_insn (gen_slt_sf (dest, fp2, fp1));
7137 /* Implement MOVE_BY_PIECES_P. */
7140 mips_move_by_pieces_p (unsigned HOST_WIDE_INT size, unsigned int align)
7144 /* movmemsi is meant to generate code that is at least as good as
7145 move_by_pieces. However, movmemsi effectively uses a by-pieces
7146 implementation both for moves smaller than a word and for
7147 word-aligned moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT
7148 bytes. We should allow the tree-level optimisers to do such
7149 moves by pieces, as it often exposes other optimization
7150 opportunities. We might as well continue to use movmemsi at
7151 the rtl level though, as it produces better code when
7152 scheduling is disabled (such as at -O). */
7153 if (currently_expanding_to_rtl)
7155 if (align < BITS_PER_WORD)
7156 return size < UNITS_PER_WORD;
7157 return size <= MIPS_MAX_MOVE_BYTES_STRAIGHT;
7159 /* The default value. If this becomes a target hook, we should
7160 call the default definition instead. */
7161 return (move_by_pieces_ninsns (size, align, MOVE_MAX_PIECES + 1)
7162 < (unsigned int) MOVE_RATIO (optimize_insn_for_speed_p ()));
7165 /* Implement STORE_BY_PIECES_P. */
7168 mips_store_by_pieces_p (unsigned HOST_WIDE_INT size, unsigned int align)
7170 /* Storing by pieces involves moving constants into registers
7171 of size MIN (ALIGN, BITS_PER_WORD), then storing them.
7172 We need to decide whether it is cheaper to load the address of
7173 constant data into a register and use a block move instead. */
7175 /* If the data is only byte aligned, then:
7177 (a1) A block move of less than 4 bytes would involve three 3 LBs and
7178 3 SBs. We might as well use 3 single-instruction LIs and 3 SBs
7181 (a2) A block move of 4 bytes from aligned source data can use an
7182 LW/SWL/SWR sequence. This is often better than the 4 LIs and
7183 4 SBs that we would generate when storing by pieces. */
7184 if (align <= BITS_PER_UNIT)
7187 /* If the data is 2-byte aligned, then:
7189 (b1) A block move of less than 4 bytes would use a combination of LBs,
7190 LHs, SBs and SHs. We get better code by using single-instruction
7191 LIs, SBs and SHs instead.
7193 (b2) A block move of 4 bytes from aligned source data would again use
7194 an LW/SWL/SWR sequence. In most cases, loading the address of
7195 the source data would require at least one extra instruction.
7196 It is often more efficient to use 2 single-instruction LIs and
7199 (b3) A block move of up to 3 additional bytes would be like (b1).
7201 (b4) A block move of 8 bytes from aligned source data can use two
7202 LW/SWL/SWR sequences or a single LD/SDL/SDR sequence. Both
7203 sequences are better than the 4 LIs and 4 SHs that we'd generate
7204 when storing by pieces.
7206 The reasoning for higher alignments is similar:
7208 (c1) A block move of less than 4 bytes would be the same as (b1).
7210 (c2) A block move of 4 bytes would use an LW/SW sequence. Again,
7211 loading the address of the source data would typically require
7212 at least one extra instruction. It is generally better to use
7215 (c3) A block move of up to 3 additional bytes would be like (b1).
7217 (c4) A block move of 8 bytes can use two LW/SW sequences or a single
7218 LD/SD sequence, and in these cases we've traditionally preferred
7219 the memory copy over the more bulky constant moves. */
7223 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
7224 Assume that the areas do not overlap. */
7227 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
7229 HOST_WIDE_INT offset, delta;
7230 unsigned HOST_WIDE_INT bits;
7232 enum machine_mode mode;
7235 /* Work out how many bits to move at a time. If both operands have
7236 half-word alignment, it is usually better to move in half words.
7237 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
7238 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
7239 Otherwise move word-sized chunks. */
7240 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
7241 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
7242 bits = BITS_PER_WORD / 2;
7244 bits = BITS_PER_WORD;
7246 mode = mode_for_size (bits, MODE_INT, 0);
7247 delta = bits / BITS_PER_UNIT;
7249 /* Allocate a buffer for the temporary registers. */
7250 regs = XALLOCAVEC (rtx, length / delta);
7252 /* Load as many BITS-sized chunks as possible. Use a normal load if
7253 the source has enough alignment, otherwise use left/right pairs. */
7254 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
7256 regs[i] = gen_reg_rtx (mode);
7257 if (MEM_ALIGN (src) >= bits)
7258 mips_emit_move (regs[i], adjust_address (src, mode, offset));
7261 rtx part = adjust_address (src, BLKmode, offset);
7262 set_mem_size (part, delta);
7263 if (!mips_expand_ext_as_unaligned_load (regs[i], part, bits, 0, 0))
7268 /* Copy the chunks to the destination. */
7269 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
7270 if (MEM_ALIGN (dest) >= bits)
7271 mips_emit_move (adjust_address (dest, mode, offset), regs[i]);
7274 rtx part = adjust_address (dest, BLKmode, offset);
7275 set_mem_size (part, delta);
7276 if (!mips_expand_ins_as_unaligned_store (part, regs[i], bits, 0))
7280 /* Mop up any left-over bytes. */
7281 if (offset < length)
7283 src = adjust_address (src, BLKmode, offset);
7284 dest = adjust_address (dest, BLKmode, offset);
7285 move_by_pieces (dest, src, length - offset,
7286 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
7290 /* Helper function for doing a loop-based block operation on memory
7291 reference MEM. Each iteration of the loop will operate on LENGTH
7294 Create a new base register for use within the loop and point it to
7295 the start of MEM. Create a new memory reference that uses this
7296 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
7299 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
7300 rtx *loop_reg, rtx *loop_mem)
7302 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
7304 /* Although the new mem does not refer to a known location,
7305 it does keep up to LENGTH bytes of alignment. */
7306 *loop_mem = change_address (mem, BLKmode, *loop_reg);
7307 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
7310 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
7311 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
7312 the memory regions do not overlap. */
7315 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length,
7316 HOST_WIDE_INT bytes_per_iter)
7318 rtx label, src_reg, dest_reg, final_src, test;
7319 HOST_WIDE_INT leftover;
7321 leftover = length % bytes_per_iter;
7324 /* Create registers and memory references for use within the loop. */
7325 mips_adjust_block_mem (src, bytes_per_iter, &src_reg, &src);
7326 mips_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest);
7328 /* Calculate the value that SRC_REG should have after the last iteration
7330 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
7333 /* Emit the start of the loop. */
7334 label = gen_label_rtx ();
7337 /* Emit the loop body. */
7338 mips_block_move_straight (dest, src, bytes_per_iter);
7340 /* Move on to the next block. */
7341 mips_emit_move (src_reg, plus_constant (Pmode, src_reg, bytes_per_iter));
7342 mips_emit_move (dest_reg, plus_constant (Pmode, dest_reg, bytes_per_iter));
7344 /* Emit the loop condition. */
7345 test = gen_rtx_NE (VOIDmode, src_reg, final_src);
7346 if (Pmode == DImode)
7347 emit_jump_insn (gen_cbranchdi4 (test, src_reg, final_src, label));
7349 emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label));
7351 /* Mop up any left-over bytes. */
7353 mips_block_move_straight (dest, src, leftover);
7356 /* Expand a movmemsi instruction, which copies LENGTH bytes from
7357 memory reference SRC to memory reference DEST. */
7360 mips_expand_block_move (rtx dest, rtx src, rtx length)
7362 if (CONST_INT_P (length))
7364 if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)
7366 mips_block_move_straight (dest, src, INTVAL (length));
7371 mips_block_move_loop (dest, src, INTVAL (length),
7372 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER);
7379 /* Expand a loop of synci insns for the address range [BEGIN, END). */
7382 mips_expand_synci_loop (rtx begin, rtx end)
7384 rtx inc, label, end_label, cmp_result, mask, length;
7386 /* Create end_label. */
7387 end_label = gen_label_rtx ();
7389 /* Check if begin equals end. */
7390 cmp_result = gen_rtx_EQ (VOIDmode, begin, end);
7391 emit_jump_insn (gen_condjump (cmp_result, end_label));
7393 /* Load INC with the cache line size (rdhwr INC,$1). */
7394 inc = gen_reg_rtx (Pmode);
7395 emit_insn (PMODE_INSN (gen_rdhwr_synci_step, (inc)));
7397 /* Check if inc is 0. */
7398 cmp_result = gen_rtx_EQ (VOIDmode, inc, const0_rtx);
7399 emit_jump_insn (gen_condjump (cmp_result, end_label));
7401 /* Calculate mask. */
7402 mask = mips_force_unary (Pmode, NEG, inc);
7404 /* Mask out begin by mask. */
7405 begin = mips_force_binary (Pmode, AND, begin, mask);
7407 /* Calculate length. */
7408 length = mips_force_binary (Pmode, MINUS, end, begin);
7410 /* Loop back to here. */
7411 label = gen_label_rtx ();
7414 emit_insn (gen_synci (begin));
7416 /* Update length. */
7417 mips_emit_binary (MINUS, length, length, inc);
7420 mips_emit_binary (PLUS, begin, begin, inc);
7422 /* Check if length is greater than 0. */
7423 cmp_result = gen_rtx_GT (VOIDmode, length, const0_rtx);
7424 emit_jump_insn (gen_condjump (cmp_result, label));
7426 emit_label (end_label);
7429 /* Expand a QI or HI mode atomic memory operation.
7431 GENERATOR contains a pointer to the gen_* function that generates
7432 the SI mode underlying atomic operation using masks that we
7435 RESULT is the return register for the operation. Its value is NULL
7438 MEM is the location of the atomic access.
7440 OLDVAL is the first operand for the operation.
7442 NEWVAL is the optional second operand for the operation. Its value
7443 is NULL if unused. */
7446 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator,
7447 rtx result, rtx mem, rtx oldval, rtx newval)
7449 rtx orig_addr, memsi_addr, memsi, shift, shiftsi, unshifted_mask;
7450 rtx unshifted_mask_reg, mask, inverted_mask, si_op;
7452 enum machine_mode mode;
7454 mode = GET_MODE (mem);
7456 /* Compute the address of the containing SImode value. */
7457 orig_addr = force_reg (Pmode, XEXP (mem, 0));
7458 memsi_addr = mips_force_binary (Pmode, AND, orig_addr,
7459 force_reg (Pmode, GEN_INT (-4)));
7461 /* Create a memory reference for it. */
7462 memsi = gen_rtx_MEM (SImode, memsi_addr);
7463 set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER);
7464 MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem);
7466 /* Work out the byte offset of the QImode or HImode value,
7467 counting from the least significant byte. */
7468 shift = mips_force_binary (Pmode, AND, orig_addr, GEN_INT (3));
7469 if (TARGET_BIG_ENDIAN)
7470 mips_emit_binary (XOR, shift, shift, GEN_INT (mode == QImode ? 3 : 2));
7472 /* Multiply by eight to convert the shift value from bytes to bits. */
7473 mips_emit_binary (ASHIFT, shift, shift, GEN_INT (3));
7475 /* Make the final shift an SImode value, so that it can be used in
7476 SImode operations. */
7477 shiftsi = force_reg (SImode, gen_lowpart (SImode, shift));
7479 /* Set MASK to an inclusive mask of the QImode or HImode value. */
7480 unshifted_mask = GEN_INT (GET_MODE_MASK (mode));
7481 unshifted_mask_reg = force_reg (SImode, unshifted_mask);
7482 mask = mips_force_binary (SImode, ASHIFT, unshifted_mask_reg, shiftsi);
7484 /* Compute the equivalent exclusive mask. */
7485 inverted_mask = gen_reg_rtx (SImode);
7486 emit_insn (gen_rtx_SET (VOIDmode, inverted_mask,
7487 gen_rtx_NOT (SImode, mask)));
7489 /* Shift the old value into place. */
7490 if (oldval != const0_rtx)
7492 oldval = convert_modes (SImode, mode, oldval, true);
7493 oldval = force_reg (SImode, oldval);
7494 oldval = mips_force_binary (SImode, ASHIFT, oldval, shiftsi);
7497 /* Do the same for the new value. */
7498 if (newval && newval != const0_rtx)
7500 newval = convert_modes (SImode, mode, newval, true);
7501 newval = force_reg (SImode, newval);
7502 newval = mips_force_binary (SImode, ASHIFT, newval, shiftsi);
7505 /* Do the SImode atomic access. */
7507 res = gen_reg_rtx (SImode);
7509 si_op = generator.fn_6 (res, memsi, mask, inverted_mask, oldval, newval);
7511 si_op = generator.fn_5 (res, memsi, mask, inverted_mask, oldval);
7513 si_op = generator.fn_4 (memsi, mask, inverted_mask, oldval);
7519 /* Shift and convert the result. */
7520 mips_emit_binary (AND, res, res, mask);
7521 mips_emit_binary (LSHIFTRT, res, res, shiftsi);
7522 mips_emit_move (result, gen_lowpart (GET_MODE (result), res));
7526 /* Return true if it is possible to use left/right accesses for a
7527 bitfield of WIDTH bits starting BITPOS bits into BLKmode memory OP.
7528 When returning true, update *LEFT and *RIGHT as follows:
7530 *LEFT is a QImode reference to the first byte if big endian or
7531 the last byte if little endian. This address can be used in the
7532 left-side instructions (LWL, SWL, LDL, SDL).
7534 *RIGHT is a QImode reference to the opposite end of the field and
7535 can be used in the patterning right-side instruction. */
7538 mips_get_unaligned_mem (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos,
7539 rtx *left, rtx *right)
7543 /* Check that the size is valid. */
7544 if (width != 32 && (!TARGET_64BIT || width != 64))
7547 /* We can only access byte-aligned values. Since we are always passed
7548 a reference to the first byte of the field, it is not necessary to
7549 do anything with BITPOS after this check. */
7550 if (bitpos % BITS_PER_UNIT != 0)
7553 /* Reject aligned bitfields: we want to use a normal load or store
7554 instead of a left/right pair. */
7555 if (MEM_ALIGN (op) >= width)
7558 /* Get references to both ends of the field. */
7559 first = adjust_address (op, QImode, 0);
7560 last = adjust_address (op, QImode, width / BITS_PER_UNIT - 1);
7562 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
7563 correspond to the MSB and RIGHT to the LSB. */
7564 if (TARGET_BIG_ENDIAN)
7565 *left = first, *right = last;
7567 *left = last, *right = first;
7572 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
7573 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
7574 the operation is the equivalent of:
7576 (set DEST (*_extract SRC WIDTH BITPOS))
7578 Return true on success. */
7581 mips_expand_ext_as_unaligned_load (rtx dest, rtx src, HOST_WIDE_INT width,
7582 HOST_WIDE_INT bitpos, bool unsigned_p)
7584 rtx left, right, temp;
7585 rtx dest1 = NULL_RTX;
7587 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
7588 be a DImode, create a new temp and emit a zero extend at the end. */
7589 if (GET_MODE (dest) == DImode
7591 && GET_MODE_BITSIZE (SImode) == width)
7594 dest = gen_reg_rtx (SImode);
7597 if (!mips_get_unaligned_mem (src, width, bitpos, &left, &right))
7600 temp = gen_reg_rtx (GET_MODE (dest));
7601 if (GET_MODE (dest) == DImode)
7603 emit_insn (gen_mov_ldl (temp, src, left));
7604 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
7608 emit_insn (gen_mov_lwl (temp, src, left));
7609 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
7612 /* If we were loading 32bits and the original register was DI then
7613 sign/zero extend into the orignal dest. */
7617 emit_insn (gen_zero_extendsidi2 (dest1, dest));
7619 emit_insn (gen_extendsidi2 (dest1, dest));
7624 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
7625 BITPOS and SRC are the operands passed to the expander; the operation
7626 is the equivalent of:
7628 (set (zero_extract DEST WIDTH BITPOS) SRC)
7630 Return true on success. */
7633 mips_expand_ins_as_unaligned_store (rtx dest, rtx src, HOST_WIDE_INT width,
7634 HOST_WIDE_INT bitpos)
7637 enum machine_mode mode;
7639 if (!mips_get_unaligned_mem (dest, width, bitpos, &left, &right))
7642 mode = mode_for_size (width, MODE_INT, 0);
7643 src = gen_lowpart (mode, src);
7646 emit_insn (gen_mov_sdl (dest, src, left));
7647 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
7651 emit_insn (gen_mov_swl (dest, src, left));
7652 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
7657 /* Return true if X is a MEM with the same size as MODE. */
7660 mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
7663 && MEM_SIZE_KNOWN_P (x)
7664 && MEM_SIZE (x) == GET_MODE_SIZE (mode));
7667 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
7668 source of an "ext" instruction or the destination of an "ins"
7669 instruction. OP must be a register operand and the following
7670 conditions must hold:
7672 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
7673 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7674 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7676 Also reject lengths equal to a word as they are better handled
7677 by the move patterns. */
7680 mips_use_ins_ext_p (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos)
7682 if (!ISA_HAS_EXT_INS
7683 || !register_operand (op, VOIDmode)
7684 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
7687 if (!IN_RANGE (width, 1, GET_MODE_BITSIZE (GET_MODE (op)) - 1))
7690 if (bitpos < 0 || bitpos + width > GET_MODE_BITSIZE (GET_MODE (op)))
7696 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
7697 operation if MAXLEN is the maxium length of consecutive bits that
7698 can make up MASK. MODE is the mode of the operation. See
7699 mask_low_and_shift_len for the actual definition. */
7702 mask_low_and_shift_p (enum machine_mode mode, rtx mask, rtx shift, int maxlen)
7704 return IN_RANGE (mask_low_and_shift_len (mode, mask, shift), 1, maxlen);
7707 /* Return true iff OP1 and OP2 are valid operands together for the
7708 *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider,
7709 see the table in the comment before the pattern. */
7712 and_operands_ok (enum machine_mode mode, rtx op1, rtx op2)
7714 return (memory_operand (op1, mode)
7715 ? and_load_operand (op2, mode)
7716 : and_reg_operand (op2, mode));
7719 /* The canonical form of a mask-low-and-shift-left operation is
7720 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
7721 cleared. Thus we need to shift MASK to the right before checking if it
7722 is a valid mask value. MODE is the mode of the operation. If true
7723 return the length of the mask, otherwise return -1. */
7726 mask_low_and_shift_len (enum machine_mode mode, rtx mask, rtx shift)
7728 HOST_WIDE_INT shval;
7730 shval = INTVAL (shift) & (GET_MODE_BITSIZE (mode) - 1);
7731 return exact_log2 ((UINTVAL (mask) >> shval) + 1);
7734 /* Return true if -msplit-addresses is selected and should be honored.
7736 -msplit-addresses is a half-way house between explicit relocations
7737 and the traditional assembler macros. It can split absolute 32-bit
7738 symbolic constants into a high/lo_sum pair but uses macros for other
7741 Like explicit relocation support for REL targets, it relies
7742 on GNU extensions in the assembler and the linker.
7744 Although this code should work for -O0, it has traditionally
7745 been treated as an optimization. */
7748 mips_split_addresses_p (void)
7750 return (TARGET_SPLIT_ADDRESSES
7754 && !ABI_HAS_64BIT_SYMBOLS);
7757 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
7760 mips_init_relocs (void)
7762 memset (mips_split_p, '\0', sizeof (mips_split_p));
7763 memset (mips_split_hi_p, '\0', sizeof (mips_split_hi_p));
7764 memset (mips_use_pcrel_pool_p, '\0', sizeof (mips_use_pcrel_pool_p));
7765 memset (mips_hi_relocs, '\0', sizeof (mips_hi_relocs));
7766 memset (mips_lo_relocs, '\0', sizeof (mips_lo_relocs));
7768 if (TARGET_MIPS16_PCREL_LOADS)
7769 mips_use_pcrel_pool_p[SYMBOL_ABSOLUTE] = true;
7772 if (ABI_HAS_64BIT_SYMBOLS)
7774 if (TARGET_EXPLICIT_RELOCS)
7776 mips_split_p[SYMBOL_64_HIGH] = true;
7777 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
7778 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
7780 mips_split_p[SYMBOL_64_MID] = true;
7781 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
7782 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
7784 mips_split_p[SYMBOL_64_LOW] = true;
7785 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
7786 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
7788 mips_split_p[SYMBOL_ABSOLUTE] = true;
7789 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
7794 if (TARGET_EXPLICIT_RELOCS
7795 || mips_split_addresses_p ()
7798 mips_split_p[SYMBOL_ABSOLUTE] = true;
7799 mips_hi_relocs[SYMBOL_ABSOLUTE] = "%hi(";
7800 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
7807 /* The high part is provided by a pseudo copy of $gp. */
7808 mips_split_p[SYMBOL_GP_RELATIVE] = true;
7809 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gprel(";
7811 else if (TARGET_EXPLICIT_RELOCS)
7812 /* Small data constants are kept whole until after reload,
7813 then lowered by mips_rewrite_small_data. */
7814 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gp_rel(";
7816 if (TARGET_EXPLICIT_RELOCS)
7818 mips_split_p[SYMBOL_GOT_PAGE_OFST] = true;
7821 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
7822 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%got_ofst(";
7826 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
7827 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%lo(";
7830 /* Expose the use of $28 as soon as possible. */
7831 mips_split_hi_p[SYMBOL_GOT_PAGE_OFST] = true;
7835 /* The HIGH and LO_SUM are matched by special .md patterns. */
7836 mips_split_p[SYMBOL_GOT_DISP] = true;
7838 mips_split_p[SYMBOL_GOTOFF_DISP] = true;
7839 mips_hi_relocs[SYMBOL_GOTOFF_DISP] = "%got_hi(";
7840 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_lo(";
7842 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
7843 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
7844 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
7849 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_disp(";
7851 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got(";
7852 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
7854 /* Expose the use of $28 as soon as possible. */
7855 mips_split_p[SYMBOL_GOT_DISP] = true;
7861 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
7862 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
7863 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
7866 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
7867 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
7869 if (TARGET_MIPS16_PCREL_LOADS)
7871 mips_use_pcrel_pool_p[SYMBOL_DTPREL] = true;
7872 mips_use_pcrel_pool_p[SYMBOL_TPREL] = true;
7876 mips_split_p[SYMBOL_DTPREL] = true;
7877 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
7878 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
7880 mips_split_p[SYMBOL_TPREL] = true;
7881 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
7882 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
7885 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
7886 mips_lo_relocs[SYMBOL_HALF] = "%half(";
7889 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
7890 in context CONTEXT. RELOCS is the array of relocations to use. */
7893 mips_print_operand_reloc (FILE *file, rtx op, enum mips_symbol_context context,
7894 const char **relocs)
7896 enum mips_symbol_type symbol_type;
7899 symbol_type = mips_classify_symbolic_expression (op, context);
7900 gcc_assert (relocs[symbol_type]);
7902 fputs (relocs[symbol_type], file);
7903 output_addr_const (file, mips_strip_unspec_address (op));
7904 for (p = relocs[symbol_type]; *p != 0; p++)
7909 /* Start a new block with the given asm switch enabled. If we need
7910 to print a directive, emit PREFIX before it and SUFFIX after it. */
7913 mips_push_asm_switch_1 (struct mips_asm_switch *asm_switch,
7914 const char *prefix, const char *suffix)
7916 if (asm_switch->nesting_level == 0)
7917 fprintf (asm_out_file, "%s.set\tno%s%s", prefix, asm_switch->name, suffix);
7918 asm_switch->nesting_level++;
7921 /* Likewise, but end a block. */
7924 mips_pop_asm_switch_1 (struct mips_asm_switch *asm_switch,
7925 const char *prefix, const char *suffix)
7927 gcc_assert (asm_switch->nesting_level);
7928 asm_switch->nesting_level--;
7929 if (asm_switch->nesting_level == 0)
7930 fprintf (asm_out_file, "%s.set\t%s%s", prefix, asm_switch->name, suffix);
7933 /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1
7934 that either print a complete line or print nothing. */
7937 mips_push_asm_switch (struct mips_asm_switch *asm_switch)
7939 mips_push_asm_switch_1 (asm_switch, "\t", "\n");
7943 mips_pop_asm_switch (struct mips_asm_switch *asm_switch)
7945 mips_pop_asm_switch_1 (asm_switch, "\t", "\n");
7948 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
7949 The punctuation characters are:
7951 '(' Start a nested ".set noreorder" block.
7952 ')' End a nested ".set noreorder" block.
7953 '[' Start a nested ".set noat" block.
7954 ']' End a nested ".set noat" block.
7955 '<' Start a nested ".set nomacro" block.
7956 '>' End a nested ".set nomacro" block.
7957 '*' Behave like %(%< if generating a delayed-branch sequence.
7958 '#' Print a nop if in a ".set noreorder" block.
7959 '/' Like '#', but do nothing within a delayed-branch sequence.
7960 '?' Print "l" if mips_branch_likely is true
7961 '~' Print a nop if mips_branch_likely is true
7962 '.' Print the name of the register with a hard-wired zero (zero or $0).
7963 '@' Print the name of the assembler temporary register (at or $1).
7964 '^' Print the name of the pic call-through register (t9 or $25).
7965 '+' Print the name of the gp register (usually gp or $28).
7966 '$' Print the name of the stack pointer register (sp or $29).
7967 ':' Print "c" to use the compact version if the delay slot is a nop.
7968 '!' Print "s" to use the short version if the delay slot contains a
7971 See also mips_init_print_operand_pucnt. */
7974 mips_print_operand_punctuation (FILE *file, int ch)
7979 mips_push_asm_switch_1 (&mips_noreorder, "", "\n\t");
7983 mips_pop_asm_switch_1 (&mips_noreorder, "\n\t", "");
7987 mips_push_asm_switch_1 (&mips_noat, "", "\n\t");
7991 mips_pop_asm_switch_1 (&mips_noat, "\n\t", "");
7995 mips_push_asm_switch_1 (&mips_nomacro, "", "\n\t");
7999 mips_pop_asm_switch_1 (&mips_nomacro, "\n\t", "");
8003 if (final_sequence != 0)
8005 mips_print_operand_punctuation (file, '(');
8006 mips_print_operand_punctuation (file, '<');
8011 if (mips_noreorder.nesting_level > 0)
8012 fputs ("\n\tnop", file);
8016 /* Print an extra newline so that the delayed insn is separated
8017 from the following ones. This looks neater and is consistent
8018 with non-nop delayed sequences. */
8019 if (mips_noreorder.nesting_level > 0 && final_sequence == 0)
8020 fputs ("\n\tnop\n", file);
8024 if (mips_branch_likely)
8029 if (mips_branch_likely)
8030 fputs ("\n\tnop", file);
8034 fputs (reg_names[GP_REG_FIRST + 0], file);
8038 fputs (reg_names[AT_REGNUM], file);
8042 fputs (reg_names[PIC_FUNCTION_ADDR_REGNUM], file);
8046 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
8050 fputs (reg_names[STACK_POINTER_REGNUM], file);
8054 /* When final_sequence is 0, the delay slot will be a nop. We can
8055 use the compact version for microMIPS. */
8056 if (final_sequence == 0)
8061 /* If the delay slot instruction is short, then use the
8063 if (final_sequence == 0
8064 || get_attr_length (XVECEXP (final_sequence, 0, 1)) == 2)
8074 /* Initialize mips_print_operand_punct. */
8077 mips_init_print_operand_punct (void)
8081 for (p = "()[]<>*#/?~.@^+$:!"; *p; p++)
8082 mips_print_operand_punct[(unsigned char) *p] = true;
8085 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
8086 associated with condition CODE. Print the condition part of the
8090 mips_print_int_branch_condition (FILE *file, enum rtx_code code, int letter)
8104 /* Conveniently, the MIPS names for these conditions are the same
8105 as their RTL equivalents. */
8106 fputs (GET_RTX_NAME (code), file);
8110 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
8115 /* Likewise floating-point branches. */
8118 mips_print_float_branch_condition (FILE *file, enum rtx_code code, int letter)
8123 fputs ("c1f", file);
8127 fputs ("c1t", file);
8131 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
8136 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
8139 mips_print_operand_punct_valid_p (unsigned char code)
8141 return mips_print_operand_punct[code];
8144 /* Implement TARGET_PRINT_OPERAND. The MIPS-specific operand codes are:
8146 'X' Print CONST_INT OP in hexadecimal format.
8147 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
8148 'd' Print CONST_INT OP in decimal.
8149 'm' Print one less than CONST_INT OP in decimal.
8150 'h' Print the high-part relocation associated with OP, after stripping
8152 'R' Print the low-part relocation associated with OP.
8153 'C' Print the integer branch condition for comparison OP.
8154 'N' Print the inverse of the integer branch condition for comparison OP.
8155 'F' Print the FPU branch condition for comparison OP.
8156 'W' Print the inverse of the FPU branch condition for comparison OP.
8157 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
8158 'z' for (eq:?I ...), 'n' for (ne:?I ...).
8159 't' Like 'T', but with the EQ/NE cases reversed
8160 'Y' Print mips_fp_conditions[INTVAL (OP)]
8161 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
8162 'q' Print a DSP accumulator register.
8163 'D' Print the second part of a double-word register or memory operand.
8164 'L' Print the low-order register in a double-word register operand.
8165 'M' Print high-order register in a double-word register operand.
8166 'z' Print $0 if OP is zero, otherwise print OP normally.
8167 'b' Print the address of a memory operand, without offset. */
8170 mips_print_operand (FILE *file, rtx op, int letter)
8174 if (mips_print_operand_punct_valid_p (letter))
8176 mips_print_operand_punctuation (file, letter);
8181 code = GET_CODE (op);
8186 if (CONST_INT_P (op))
8187 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
8189 output_operand_lossage ("invalid use of '%%%c'", letter);
8193 if (CONST_INT_P (op))
8194 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op) & 0xffff);
8196 output_operand_lossage ("invalid use of '%%%c'", letter);
8200 if (CONST_INT_P (op))
8201 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op));
8203 output_operand_lossage ("invalid use of '%%%c'", letter);
8207 if (CONST_INT_P (op))
8208 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op) - 1);
8210 output_operand_lossage ("invalid use of '%%%c'", letter);
8216 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_hi_relocs);
8220 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_lo_relocs);
8224 mips_print_int_branch_condition (file, code, letter);
8228 mips_print_int_branch_condition (file, reverse_condition (code), letter);
8232 mips_print_float_branch_condition (file, code, letter);
8236 mips_print_float_branch_condition (file, reverse_condition (code),
8243 int truth = (code == NE) == (letter == 'T');
8244 fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
8249 if (code == CONST_INT && UINTVAL (op) < ARRAY_SIZE (mips_fp_conditions))
8250 fputs (mips_fp_conditions[UINTVAL (op)], file);
8252 output_operand_lossage ("'%%%c' is not a valid operand prefix",
8259 mips_print_operand (file, op, 0);
8265 if (code == REG && MD_REG_P (REGNO (op)))
8266 fprintf (file, "$ac0");
8267 else if (code == REG && DSP_ACC_REG_P (REGNO (op)))
8268 fprintf (file, "$ac%c", reg_names[REGNO (op)][3]);
8270 output_operand_lossage ("invalid use of '%%%c'", letter);
8278 unsigned int regno = REGNO (op);
8279 if ((letter == 'M' && TARGET_LITTLE_ENDIAN)
8280 || (letter == 'L' && TARGET_BIG_ENDIAN)
8283 else if (letter && letter != 'z' && letter != 'M' && letter != 'L')
8284 output_operand_lossage ("invalid use of '%%%c'", letter);
8285 /* We need to print $0 .. $31 for COP0 registers. */
8286 if (COP0_REG_P (regno))
8287 fprintf (file, "$%s", ®_names[regno][4]);
8289 fprintf (file, "%s", reg_names[regno]);
8295 output_address (plus_constant (Pmode, XEXP (op, 0), 4));
8296 else if (letter == 'b')
8298 gcc_assert (REG_P (XEXP (op, 0)));
8299 mips_print_operand (file, XEXP (op, 0), 0);
8301 else if (letter && letter != 'z')
8302 output_operand_lossage ("invalid use of '%%%c'", letter);
8304 output_address (XEXP (op, 0));
8308 if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
8309 fputs (reg_names[GP_REG_FIRST], file);
8310 else if (letter && letter != 'z')
8311 output_operand_lossage ("invalid use of '%%%c'", letter);
8312 else if (CONST_GP_P (op))
8313 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
8315 output_addr_const (file, mips_strip_unspec_address (op));
8321 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
8324 mips_print_operand_address (FILE *file, rtx x)
8326 struct mips_address_info addr;
8328 if (mips_classify_address (&addr, x, word_mode, true))
8332 mips_print_operand (file, addr.offset, 0);
8333 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
8336 case ADDRESS_LO_SUM:
8337 mips_print_operand_reloc (file, addr.offset, SYMBOL_CONTEXT_MEM,
8339 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
8342 case ADDRESS_CONST_INT:
8343 output_addr_const (file, x);
8344 fprintf (file, "(%s)", reg_names[GP_REG_FIRST]);
8347 case ADDRESS_SYMBOLIC:
8348 output_addr_const (file, mips_strip_unspec_address (x));
8354 /* Implement TARGET_ENCODE_SECTION_INFO. */
8357 mips_encode_section_info (tree decl, rtx rtl, int first)
8359 default_encode_section_info (decl, rtl, first);
8361 if (TREE_CODE (decl) == FUNCTION_DECL)
8363 rtx symbol = XEXP (rtl, 0);
8364 tree type = TREE_TYPE (decl);
8366 /* Encode whether the symbol is short or long. */
8367 if ((TARGET_LONG_CALLS && !mips_near_type_p (type))
8368 || mips_far_type_p (type))
8369 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
8373 /* Implement TARGET_SELECT_RTX_SECTION. */
8376 mips_select_rtx_section (enum machine_mode mode, rtx x,
8377 unsigned HOST_WIDE_INT align)
8379 /* ??? Consider using mergeable small data sections. */
8380 if (mips_rtx_constant_in_small_data_p (mode))
8381 return get_named_section (NULL, ".sdata", 0);
8383 return default_elf_select_rtx_section (mode, x, align);
8386 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
8388 The complication here is that, with the combination TARGET_ABICALLS
8389 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
8390 absolute addresses, and should therefore not be included in the
8391 read-only part of a DSO. Handle such cases by selecting a normal
8392 data section instead of a read-only one. The logic apes that in
8393 default_function_rodata_section. */
8396 mips_function_rodata_section (tree decl)
8398 if (!TARGET_ABICALLS || TARGET_ABSOLUTE_ABICALLS || TARGET_GPWORD)
8399 return default_function_rodata_section (decl);
8401 if (decl && DECL_SECTION_NAME (decl))
8403 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
8404 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
8406 char *rname = ASTRDUP (name);
8408 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
8410 else if (flag_function_sections
8411 && flag_data_sections
8412 && strncmp (name, ".text.", 6) == 0)
8414 char *rname = ASTRDUP (name);
8415 memcpy (rname + 1, "data", 4);
8416 return get_section (rname, SECTION_WRITE, decl);
8419 return data_section;
8422 /* Implement TARGET_IN_SMALL_DATA_P. */
8425 mips_in_small_data_p (const_tree decl)
8427 unsigned HOST_WIDE_INT size;
8429 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
8432 /* We don't yet generate small-data references for -mabicalls
8433 or VxWorks RTP code. See the related -G handling in
8434 mips_option_override. */
8435 if (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
8438 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
8442 /* Reject anything that isn't in a known small-data section. */
8443 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
8444 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
8447 /* If a symbol is defined externally, the assembler will use the
8448 usual -G rules when deciding how to implement macros. */
8449 if (mips_lo_relocs[SYMBOL_GP_RELATIVE] || !DECL_EXTERNAL (decl))
8452 else if (TARGET_EMBEDDED_DATA)
8454 /* Don't put constants into the small data section: we want them
8455 to be in ROM rather than RAM. */
8456 if (TREE_CODE (decl) != VAR_DECL)
8459 if (TREE_READONLY (decl)
8460 && !TREE_SIDE_EFFECTS (decl)
8461 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
8465 /* Enforce -mlocal-sdata. */
8466 if (!TARGET_LOCAL_SDATA && !TREE_PUBLIC (decl))
8469 /* Enforce -mextern-sdata. */
8470 if (!TARGET_EXTERN_SDATA && DECL_P (decl))
8472 if (DECL_EXTERNAL (decl))
8474 if (DECL_COMMON (decl) && DECL_INITIAL (decl) == NULL)
8478 /* We have traditionally not treated zero-sized objects as small data,
8479 so this is now effectively part of the ABI. */
8480 size = int_size_in_bytes (TREE_TYPE (decl));
8481 return size > 0 && size <= mips_small_data_threshold;
8484 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
8485 anchors for small data: the GP register acts as an anchor in that
8486 case. We also don't want to use them for PC-relative accesses,
8487 where the PC acts as an anchor. */
8490 mips_use_anchors_for_symbol_p (const_rtx symbol)
8492 switch (mips_classify_symbol (symbol, SYMBOL_CONTEXT_MEM))
8494 case SYMBOL_PC_RELATIVE:
8495 case SYMBOL_GP_RELATIVE:
8499 return default_use_anchors_for_symbol_p (symbol);
8503 /* The MIPS debug format wants all automatic variables and arguments
8504 to be in terms of the virtual frame pointer (stack pointer before
8505 any adjustment in the function), while the MIPS 3.0 linker wants
8506 the frame pointer to be the stack pointer after the initial
8507 adjustment. So, we do the adjustment here. The arg pointer (which
8508 is eliminated) points to the virtual frame pointer, while the frame
8509 pointer (which may be eliminated) points to the stack pointer after
8510 the initial adjustments. */
8513 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
8515 rtx offset2 = const0_rtx;
8516 rtx reg = eliminate_constant_term (addr, &offset2);
8519 offset = INTVAL (offset2);
8521 if (reg == stack_pointer_rtx
8522 || reg == frame_pointer_rtx
8523 || reg == hard_frame_pointer_rtx)
8525 offset -= cfun->machine->frame.total_size;
8526 if (reg == hard_frame_pointer_rtx)
8527 offset += cfun->machine->frame.hard_frame_pointer_offset;
8533 /* Implement ASM_OUTPUT_EXTERNAL. */
8536 mips_output_external (FILE *file, tree decl, const char *name)
8538 default_elf_asm_output_external (file, decl, name);
8540 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
8541 set in order to avoid putting out names that are never really
8543 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
8545 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
8547 /* When using assembler macros, emit .extern directives for
8548 all small-data externs so that the assembler knows how
8551 In most cases it would be safe (though pointless) to emit
8552 .externs for other symbols too. One exception is when an
8553 object is within the -G limit but declared by the user to
8554 be in a section other than .sbss or .sdata. */
8555 fputs ("\t.extern\t", file);
8556 assemble_name (file, name);
8557 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n",
8558 int_size_in_bytes (TREE_TYPE (decl)));
8563 /* Implement TARGET_ASM_OUTPUT_SOURCE_FILENAME. */
8566 mips_output_filename (FILE *stream, const char *name)
8568 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
8570 if (write_symbols == DWARF2_DEBUG)
8572 else if (mips_output_filename_first_time)
8574 mips_output_filename_first_time = 0;
8575 num_source_filenames += 1;
8576 current_function_file = name;
8577 fprintf (stream, "\t.file\t%d ", num_source_filenames);
8578 output_quoted_string (stream, name);
8579 putc ('\n', stream);
8581 /* If we are emitting stabs, let dbxout.c handle this (except for
8582 the mips_output_filename_first_time case). */
8583 else if (write_symbols == DBX_DEBUG)
8585 else if (name != current_function_file
8586 && strcmp (name, current_function_file) != 0)
8588 num_source_filenames += 1;
8589 current_function_file = name;
8590 fprintf (stream, "\t.file\t%d ", num_source_filenames);
8591 output_quoted_string (stream, name);
8592 putc ('\n', stream);
8596 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
8598 static void ATTRIBUTE_UNUSED
8599 mips_output_dwarf_dtprel (FILE *file, int size, rtx x)
8604 fputs ("\t.dtprelword\t", file);
8608 fputs ("\t.dtpreldword\t", file);
8614 output_addr_const (file, x);
8615 fputs ("+0x8000", file);
8618 /* Implement TARGET_DWARF_REGISTER_SPAN. */
8621 mips_dwarf_register_span (rtx reg)
8624 enum machine_mode mode;
8626 /* By default, GCC maps increasing register numbers to increasing
8627 memory locations, but paired FPRs are always little-endian,
8628 regardless of the prevailing endianness. */
8629 mode = GET_MODE (reg);
8630 if (FP_REG_P (REGNO (reg))
8631 && TARGET_BIG_ENDIAN
8632 && MAX_FPRS_PER_FMT > 1
8633 && GET_MODE_SIZE (mode) > UNITS_PER_FPREG)
8635 gcc_assert (GET_MODE_SIZE (mode) == UNITS_PER_HWFPVALUE);
8636 high = mips_subword (reg, true);
8637 low = mips_subword (reg, false);
8638 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, high, low));
8644 /* DSP ALU can bypass data with no delays for the following pairs. */
8645 enum insn_code dspalu_bypass_table[][2] =
8647 {CODE_FOR_mips_addsc, CODE_FOR_mips_addwc},
8648 {CODE_FOR_mips_cmpu_eq_qb, CODE_FOR_mips_pick_qb},
8649 {CODE_FOR_mips_cmpu_lt_qb, CODE_FOR_mips_pick_qb},
8650 {CODE_FOR_mips_cmpu_le_qb, CODE_FOR_mips_pick_qb},
8651 {CODE_FOR_mips_cmp_eq_ph, CODE_FOR_mips_pick_ph},
8652 {CODE_FOR_mips_cmp_lt_ph, CODE_FOR_mips_pick_ph},
8653 {CODE_FOR_mips_cmp_le_ph, CODE_FOR_mips_pick_ph},
8654 {CODE_FOR_mips_wrdsp, CODE_FOR_mips_insv}
8658 mips_dspalu_bypass_p (rtx out_insn, rtx in_insn)
8661 int num_bypass = ARRAY_SIZE (dspalu_bypass_table);
8662 enum insn_code out_icode = (enum insn_code) INSN_CODE (out_insn);
8663 enum insn_code in_icode = (enum insn_code) INSN_CODE (in_insn);
8665 for (i = 0; i < num_bypass; i++)
8667 if (out_icode == dspalu_bypass_table[i][0]
8668 && in_icode == dspalu_bypass_table[i][1])
8674 /* Implement ASM_OUTPUT_ASCII. */
8677 mips_output_ascii (FILE *stream, const char *string, size_t len)
8683 fprintf (stream, "\t.ascii\t\"");
8684 for (i = 0; i < len; i++)
8688 c = (unsigned char) string[i];
8691 if (c == '\\' || c == '\"')
8693 putc ('\\', stream);
8701 fprintf (stream, "\\%03o", c);
8705 if (cur_pos > 72 && i+1 < len)
8708 fprintf (stream, "\"\n\t.ascii\t\"");
8711 fprintf (stream, "\"\n");
8714 /* Return the pseudo-op for full SYMBOL_(D)TPREL address *ADDR.
8715 Update *ADDR with the operand that should be printed. */
8718 mips_output_tls_reloc_directive (rtx *addr)
8720 enum mips_symbol_type type;
8722 type = mips_classify_symbolic_expression (*addr, SYMBOL_CONTEXT_LEA);
8723 *addr = mips_strip_unspec_address (*addr);
8727 return Pmode == SImode ? ".dtprelword\t%0" : ".dtpreldword\t%0";
8730 return Pmode == SImode ? ".tprelword\t%0" : ".tpreldword\t%0";
8737 /* Emit either a label, .comm, or .lcomm directive. When using assembler
8738 macros, mark the symbol as written so that mips_asm_output_external
8739 won't emit an .extern for it. STREAM is the output file, NAME is the
8740 name of the symbol, INIT_STRING is the string that should be written
8741 before the symbol and FINAL_STRING is the string that should be
8742 written after it. FINAL_STRING is a printf format that consumes the
8743 remaining arguments. */
8746 mips_declare_object (FILE *stream, const char *name, const char *init_string,
8747 const char *final_string, ...)
8751 fputs (init_string, stream);
8752 assemble_name (stream, name);
8753 va_start (ap, final_string);
8754 vfprintf (stream, final_string, ap);
8757 if (!TARGET_EXPLICIT_RELOCS)
8759 tree name_tree = get_identifier (name);
8760 TREE_ASM_WRITTEN (name_tree) = 1;
8764 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
8765 NAME is the name of the object and ALIGN is the required alignment
8766 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
8767 alignment argument. */
8770 mips_declare_common_object (FILE *stream, const char *name,
8771 const char *init_string,
8772 unsigned HOST_WIDE_INT size,
8773 unsigned int align, bool takes_alignment_p)
8775 if (!takes_alignment_p)
8777 size += (align / BITS_PER_UNIT) - 1;
8778 size -= size % (align / BITS_PER_UNIT);
8779 mips_declare_object (stream, name, init_string,
8780 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
8783 mips_declare_object (stream, name, init_string,
8784 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
8785 size, align / BITS_PER_UNIT);
8788 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
8789 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
8792 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
8793 unsigned HOST_WIDE_INT size,
8796 /* If the target wants uninitialized const declarations in
8797 .rdata then don't put them in .comm. */
8798 if (TARGET_EMBEDDED_DATA
8799 && TARGET_UNINIT_CONST_IN_RODATA
8800 && TREE_CODE (decl) == VAR_DECL
8801 && TREE_READONLY (decl)
8802 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
8804 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
8805 targetm.asm_out.globalize_label (stream, name);
8807 switch_to_section (readonly_data_section);
8808 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
8809 mips_declare_object (stream, name, "",
8810 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
8814 mips_declare_common_object (stream, name, "\n\t.comm\t",
8818 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8819 extern int size_directive_output;
8821 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
8822 definitions except that it uses mips_declare_object to emit the label. */
8825 mips_declare_object_name (FILE *stream, const char *name,
8826 tree decl ATTRIBUTE_UNUSED)
8828 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8829 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
8832 size_directive_output = 0;
8833 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
8837 size_directive_output = 1;
8838 size = int_size_in_bytes (TREE_TYPE (decl));
8839 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8842 mips_declare_object (stream, name, "", ":\n");
8845 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
8848 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
8852 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
8853 if (!flag_inhibit_size_directive
8854 && DECL_SIZE (decl) != 0
8857 && DECL_INITIAL (decl) == error_mark_node
8858 && !size_directive_output)
8862 size_directive_output = 1;
8863 size = int_size_in_bytes (TREE_TYPE (decl));
8864 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8869 /* Return the FOO in the name of the ".mdebug.FOO" section associated
8870 with the current ABI. */
8873 mips_mdebug_abi_name (void)
8886 return TARGET_64BIT ? "eabi64" : "eabi32";
8892 /* Implement TARGET_ASM_FILE_START. */
8895 mips_file_start (void)
8897 default_file_start ();
8899 /* Generate a special section to describe the ABI switches used to
8900 produce the resultant binary. */
8902 /* Record the ABI itself. Modern versions of binutils encode
8903 this information in the ELF header flags, but GDB needs the
8904 information in order to correctly debug binaries produced by
8905 older binutils. See the function mips_gdbarch_init in
8907 fprintf (asm_out_file, "\t.section .mdebug.%s\n\t.previous\n",
8908 mips_mdebug_abi_name ());
8910 /* There is no ELF header flag to distinguish long32 forms of the
8911 EABI from long64 forms. Emit a special section to help tools
8912 such as GDB. Do the same for o64, which is sometimes used with
8914 if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
8915 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n"
8916 "\t.previous\n", TARGET_LONG64 ? 64 : 32);
8918 #ifdef HAVE_AS_GNU_ATTRIBUTE
8922 /* No floating-point operations, -mno-float. */
8923 if (TARGET_NO_FLOAT)
8925 /* Soft-float code, -msoft-float. */
8926 else if (!TARGET_HARD_FLOAT_ABI)
8928 /* Single-float code, -msingle-float. */
8929 else if (!TARGET_DOUBLE_FLOAT)
8931 /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64. */
8932 else if (!TARGET_64BIT && TARGET_FLOAT64)
8934 /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */
8938 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n", attr);
8942 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
8943 if (TARGET_ABICALLS)
8945 fprintf (asm_out_file, "\t.abicalls\n");
8946 if (TARGET_ABICALLS_PIC0)
8947 fprintf (asm_out_file, "\t.option\tpic0\n");
8950 if (flag_verbose_asm)
8951 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
8953 mips_small_data_threshold, mips_arch_info->name, mips_isa);
8956 /* Implement TARGET_ASM_CODE_END. */
8959 mips_code_end (void)
8961 if (mips_need_mips16_rdhwr_p)
8962 mips_output_mips16_rdhwr ();
8965 /* Make the last instruction frame-related and note that it performs
8966 the operation described by FRAME_PATTERN. */
8969 mips_set_frame_expr (rtx frame_pattern)
8973 insn = get_last_insn ();
8974 RTX_FRAME_RELATED_P (insn) = 1;
8975 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
8980 /* Return a frame-related rtx that stores REG at MEM.
8981 REG must be a single register. */
8984 mips_frame_set (rtx mem, rtx reg)
8988 set = gen_rtx_SET (VOIDmode, mem, reg);
8989 RTX_FRAME_RELATED_P (set) = 1;
8994 /* Record that the epilogue has restored call-saved register REG. */
8997 mips_add_cfa_restore (rtx reg)
8999 mips_epilogue.cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg,
9000 mips_epilogue.cfa_restores);
9003 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
9004 mips16e_s2_s8_regs[X], it must also save the registers in indexes
9005 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
9006 static const unsigned char mips16e_s2_s8_regs[] = {
9007 30, 23, 22, 21, 20, 19, 18
9009 static const unsigned char mips16e_a0_a3_regs[] = {
9013 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
9014 ordered from the uppermost in memory to the lowest in memory. */
9015 static const unsigned char mips16e_save_restore_regs[] = {
9016 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
9019 /* Return the index of the lowest X in the range [0, SIZE) for which
9020 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
9023 mips16e_find_first_register (unsigned int mask, const unsigned char *regs,
9028 for (i = 0; i < size; i++)
9029 if (BITSET_P (mask, regs[i]))
9035 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
9036 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
9037 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
9038 is true for all indexes (X, SIZE). */
9041 mips16e_mask_registers (unsigned int *mask_ptr, const unsigned char *regs,
9042 unsigned int size, unsigned int *num_regs_ptr)
9046 i = mips16e_find_first_register (*mask_ptr, regs, size);
9047 for (i++; i < size; i++)
9048 if (!BITSET_P (*mask_ptr, regs[i]))
9051 *mask_ptr |= 1 << regs[i];
9055 /* Return a simplified form of X using the register values in REG_VALUES.
9056 REG_VALUES[R] is the last value assigned to hard register R, or null
9057 if R has not been modified.
9059 This function is rather limited, but is good enough for our purposes. */
9062 mips16e_collect_propagate_value (rtx x, rtx *reg_values)
9064 x = avoid_constant_pool_reference (x);
9068 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
9069 return simplify_gen_unary (GET_CODE (x), GET_MODE (x),
9070 x0, GET_MODE (XEXP (x, 0)));
9073 if (ARITHMETIC_P (x))
9075 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
9076 rtx x1 = mips16e_collect_propagate_value (XEXP (x, 1), reg_values);
9077 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), x0, x1);
9081 && reg_values[REGNO (x)]
9082 && !rtx_unstable_p (reg_values[REGNO (x)]))
9083 return reg_values[REGNO (x)];
9088 /* Return true if (set DEST SRC) stores an argument register into its
9089 caller-allocated save slot, storing the number of that argument
9090 register in *REGNO_PTR if so. REG_VALUES is as for
9091 mips16e_collect_propagate_value. */
9094 mips16e_collect_argument_save_p (rtx dest, rtx src, rtx *reg_values,
9095 unsigned int *regno_ptr)
9097 unsigned int argno, regno;
9098 HOST_WIDE_INT offset, required_offset;
9101 /* Check that this is a word-mode store. */
9102 if (!MEM_P (dest) || !REG_P (src) || GET_MODE (dest) != word_mode)
9105 /* Check that the register being saved is an unmodified argument
9107 regno = REGNO (src);
9108 if (!IN_RANGE (regno, GP_ARG_FIRST, GP_ARG_LAST) || reg_values[regno])
9110 argno = regno - GP_ARG_FIRST;
9112 /* Check whether the address is an appropriate stack-pointer or
9113 frame-pointer access. */
9114 addr = mips16e_collect_propagate_value (XEXP (dest, 0), reg_values);
9115 mips_split_plus (addr, &base, &offset);
9116 required_offset = cfun->machine->frame.total_size + argno * UNITS_PER_WORD;
9117 if (base == hard_frame_pointer_rtx)
9118 required_offset -= cfun->machine->frame.hard_frame_pointer_offset;
9119 else if (base != stack_pointer_rtx)
9121 if (offset != required_offset)
9128 /* A subroutine of mips_expand_prologue, called only when generating
9129 MIPS16e SAVE instructions. Search the start of the function for any
9130 instructions that save argument registers into their caller-allocated
9131 save slots. Delete such instructions and return a value N such that
9132 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
9133 instructions redundant. */
9136 mips16e_collect_argument_saves (void)
9138 rtx reg_values[FIRST_PSEUDO_REGISTER];
9139 rtx insn, next, set, dest, src;
9140 unsigned int nargs, regno;
9142 push_topmost_sequence ();
9144 memset (reg_values, 0, sizeof (reg_values));
9145 for (insn = get_insns (); insn; insn = next)
9147 next = NEXT_INSN (insn);
9148 if (NOTE_P (insn) || DEBUG_INSN_P (insn))
9154 set = PATTERN (insn);
9155 if (GET_CODE (set) != SET)
9158 dest = SET_DEST (set);
9159 src = SET_SRC (set);
9160 if (mips16e_collect_argument_save_p (dest, src, reg_values, ®no))
9162 if (!BITSET_P (cfun->machine->frame.mask, regno))
9165 nargs = MAX (nargs, (regno - GP_ARG_FIRST) + 1);
9168 else if (REG_P (dest) && GET_MODE (dest) == word_mode)
9169 reg_values[REGNO (dest)]
9170 = mips16e_collect_propagate_value (src, reg_values);
9174 pop_topmost_sequence ();
9179 /* Return a move between register REGNO and memory location SP + OFFSET.
9180 REG_PARM_P is true if SP + OFFSET belongs to REG_PARM_STACK_SPACE.
9181 Make the move a load if RESTORE_P, otherwise make it a store. */
9184 mips16e_save_restore_reg (bool restore_p, bool reg_parm_p,
9185 HOST_WIDE_INT offset, unsigned int regno)
9189 mem = gen_frame_mem (SImode, plus_constant (Pmode, stack_pointer_rtx,
9191 reg = gen_rtx_REG (SImode, regno);
9194 mips_add_cfa_restore (reg);
9195 return gen_rtx_SET (VOIDmode, reg, mem);
9198 return gen_rtx_SET (VOIDmode, mem, reg);
9199 return mips_frame_set (mem, reg);
9202 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
9203 The instruction must:
9205 - Allocate or deallocate SIZE bytes in total; SIZE is known
9208 - Save or restore as many registers in *MASK_PTR as possible.
9209 The instruction saves the first registers at the top of the
9210 allocated area, with the other registers below it.
9212 - Save NARGS argument registers above the allocated area.
9214 (NARGS is always zero if RESTORE_P.)
9216 The SAVE and RESTORE instructions cannot save and restore all general
9217 registers, so there may be some registers left over for the caller to
9218 handle. Destructively modify *MASK_PTR so that it contains the registers
9219 that still need to be saved or restored. The caller can save these
9220 registers in the memory immediately below *OFFSET_PTR, which is a
9221 byte offset from the bottom of the allocated stack area. */
9224 mips16e_build_save_restore (bool restore_p, unsigned int *mask_ptr,
9225 HOST_WIDE_INT *offset_ptr, unsigned int nargs,
9229 HOST_WIDE_INT offset, top_offset;
9230 unsigned int i, regno;
9233 gcc_assert (cfun->machine->frame.num_fp == 0);
9235 /* Calculate the number of elements in the PARALLEL. We need one element
9236 for the stack adjustment, one for each argument register save, and one
9237 for each additional register move. */
9239 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
9240 if (BITSET_P (*mask_ptr, mips16e_save_restore_regs[i]))
9243 /* Create the final PARALLEL. */
9244 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (n));
9247 /* Add the stack pointer adjustment. */
9248 set = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
9249 plus_constant (Pmode, stack_pointer_rtx,
9250 restore_p ? size : -size));
9251 RTX_FRAME_RELATED_P (set) = 1;
9252 XVECEXP (pattern, 0, n++) = set;
9254 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
9255 top_offset = restore_p ? size : 0;
9257 /* Save the arguments. */
9258 for (i = 0; i < nargs; i++)
9260 offset = top_offset + i * UNITS_PER_WORD;
9261 set = mips16e_save_restore_reg (restore_p, true, offset,
9263 XVECEXP (pattern, 0, n++) = set;
9266 /* Then fill in the other register moves. */
9267 offset = top_offset;
9268 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
9270 regno = mips16e_save_restore_regs[i];
9271 if (BITSET_P (*mask_ptr, regno))
9273 offset -= UNITS_PER_WORD;
9274 set = mips16e_save_restore_reg (restore_p, false, offset, regno);
9275 XVECEXP (pattern, 0, n++) = set;
9276 *mask_ptr &= ~(1 << regno);
9280 /* Tell the caller what offset it should use for the remaining registers. */
9281 *offset_ptr = size + (offset - top_offset);
9283 gcc_assert (n == XVECLEN (pattern, 0));
9288 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
9289 pointer. Return true if PATTERN matches the kind of instruction
9290 generated by mips16e_build_save_restore. If INFO is nonnull,
9291 initialize it when returning true. */
9294 mips16e_save_restore_pattern_p (rtx pattern, HOST_WIDE_INT adjust,
9295 struct mips16e_save_restore_info *info)
9297 unsigned int i, nargs, mask, extra;
9298 HOST_WIDE_INT top_offset, save_offset, offset;
9299 rtx set, reg, mem, base;
9302 if (!GENERATE_MIPS16E_SAVE_RESTORE)
9305 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
9306 top_offset = adjust > 0 ? adjust : 0;
9308 /* Interpret all other members of the PARALLEL. */
9309 save_offset = top_offset - UNITS_PER_WORD;
9313 for (n = 1; n < XVECLEN (pattern, 0); n++)
9315 /* Check that we have a SET. */
9316 set = XVECEXP (pattern, 0, n);
9317 if (GET_CODE (set) != SET)
9320 /* Check that the SET is a load (if restoring) or a store
9322 mem = adjust > 0 ? SET_SRC (set) : SET_DEST (set);
9326 /* Check that the address is the sum of the stack pointer and a
9327 possibly-zero constant offset. */
9328 mips_split_plus (XEXP (mem, 0), &base, &offset);
9329 if (base != stack_pointer_rtx)
9332 /* Check that SET's other operand is a register. */
9333 reg = adjust > 0 ? SET_DEST (set) : SET_SRC (set);
9337 /* Check for argument saves. */
9338 if (offset == top_offset + nargs * UNITS_PER_WORD
9339 && REGNO (reg) == GP_ARG_FIRST + nargs)
9341 else if (offset == save_offset)
9343 while (mips16e_save_restore_regs[i++] != REGNO (reg))
9344 if (i == ARRAY_SIZE (mips16e_save_restore_regs))
9347 mask |= 1 << REGNO (reg);
9348 save_offset -= UNITS_PER_WORD;
9354 /* Check that the restrictions on register ranges are met. */
9356 mips16e_mask_registers (&mask, mips16e_s2_s8_regs,
9357 ARRAY_SIZE (mips16e_s2_s8_regs), &extra);
9358 mips16e_mask_registers (&mask, mips16e_a0_a3_regs,
9359 ARRAY_SIZE (mips16e_a0_a3_regs), &extra);
9363 /* Make sure that the topmost argument register is not saved twice.
9364 The checks above ensure that the same is then true for the other
9365 argument registers. */
9366 if (nargs > 0 && BITSET_P (mask, GP_ARG_FIRST + nargs - 1))
9369 /* Pass back information, if requested. */
9372 info->nargs = nargs;
9374 info->size = (adjust > 0 ? adjust : -adjust);
9380 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
9381 for the register range [MIN_REG, MAX_REG]. Return a pointer to
9382 the null terminator. */
9385 mips16e_add_register_range (char *s, unsigned int min_reg,
9386 unsigned int max_reg)
9388 if (min_reg != max_reg)
9389 s += sprintf (s, ",%s-%s", reg_names[min_reg], reg_names[max_reg]);
9391 s += sprintf (s, ",%s", reg_names[min_reg]);
9395 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
9396 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
9399 mips16e_output_save_restore (rtx pattern, HOST_WIDE_INT adjust)
9401 static char buffer[300];
9403 struct mips16e_save_restore_info info;
9404 unsigned int i, end;
9407 /* Parse the pattern. */
9408 if (!mips16e_save_restore_pattern_p (pattern, adjust, &info))
9411 /* Add the mnemonic. */
9412 s = strcpy (buffer, adjust > 0 ? "restore\t" : "save\t");
9415 /* Save the arguments. */
9417 s += sprintf (s, "%s-%s,", reg_names[GP_ARG_FIRST],
9418 reg_names[GP_ARG_FIRST + info.nargs - 1]);
9419 else if (info.nargs == 1)
9420 s += sprintf (s, "%s,", reg_names[GP_ARG_FIRST]);
9422 /* Emit the amount of stack space to allocate or deallocate. */
9423 s += sprintf (s, "%d", (int) info.size);
9425 /* Save or restore $16. */
9426 if (BITSET_P (info.mask, 16))
9427 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 16]);
9429 /* Save or restore $17. */
9430 if (BITSET_P (info.mask, 17))
9431 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 17]);
9433 /* Save or restore registers in the range $s2...$s8, which
9434 mips16e_s2_s8_regs lists in decreasing order. Note that this
9435 is a software register range; the hardware registers are not
9436 numbered consecutively. */
9437 end = ARRAY_SIZE (mips16e_s2_s8_regs);
9438 i = mips16e_find_first_register (info.mask, mips16e_s2_s8_regs, end);
9440 s = mips16e_add_register_range (s, mips16e_s2_s8_regs[end - 1],
9441 mips16e_s2_s8_regs[i]);
9443 /* Save or restore registers in the range $a0...$a3. */
9444 end = ARRAY_SIZE (mips16e_a0_a3_regs);
9445 i = mips16e_find_first_register (info.mask, mips16e_a0_a3_regs, end);
9447 s = mips16e_add_register_range (s, mips16e_a0_a3_regs[i],
9448 mips16e_a0_a3_regs[end - 1]);
9450 /* Save or restore $31. */
9451 if (BITSET_P (info.mask, RETURN_ADDR_REGNUM))
9452 s += sprintf (s, ",%s", reg_names[RETURN_ADDR_REGNUM]);
9457 /* Return true if the current function returns its value in a floating-point
9458 register in MIPS16 mode. */
9461 mips16_cfun_returns_in_fpr_p (void)
9463 tree return_type = DECL_RESULT (current_function_decl);
9464 return (TARGET_MIPS16
9465 && TARGET_HARD_FLOAT_ABI
9466 && !aggregate_value_p (return_type, current_function_decl)
9467 && mips_return_mode_in_fpr_p (DECL_MODE (return_type)));
9470 /* Return true if predicate PRED is true for at least one instruction.
9471 Cache the result in *CACHE, and assume that the result is true
9472 if *CACHE is already true. */
9475 mips_find_gp_ref (bool *cache, bool (*pred) (rtx))
9481 push_topmost_sequence ();
9482 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9483 if (USEFUL_INSN_P (insn) && pred (insn))
9488 pop_topmost_sequence ();
9493 /* Return true if INSN refers to the global pointer in an "inflexible" way.
9494 See mips_cfun_has_inflexible_gp_ref_p for details. */
9497 mips_insn_has_inflexible_gp_ref_p (rtx insn)
9499 /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE
9500 indicate that the target could be a traditional MIPS
9501 lazily-binding stub. */
9502 return find_reg_fusage (insn, USE, pic_offset_table_rtx);
9505 /* Return true if the current function refers to the global pointer
9506 in a way that forces $28 to be valid. This means that we can't
9507 change the choice of global pointer, even for NewABI code.
9509 One example of this (and one which needs several checks) is that
9510 $28 must be valid when calling traditional MIPS lazy-binding stubs.
9511 (This restriction does not apply to PLTs.) */
9514 mips_cfun_has_inflexible_gp_ref_p (void)
9516 /* If the function has a nonlocal goto, $28 must hold the correct
9517 global pointer for the target function. That is, the target
9518 of the goto implicitly uses $28. */
9519 if (crtl->has_nonlocal_goto)
9522 if (TARGET_ABICALLS_PIC2)
9524 /* Symbolic accesses implicitly use the global pointer unless
9525 -mexplicit-relocs is in effect. JAL macros to symbolic addresses
9526 might go to traditional MIPS lazy-binding stubs. */
9527 if (!TARGET_EXPLICIT_RELOCS)
9530 /* FUNCTION_PROFILER includes a JAL to _mcount, which again
9531 can be lazily-bound. */
9535 /* MIPS16 functions that return in FPRs need to call an
9536 external libgcc routine. This call is only made explict
9537 during mips_expand_epilogue, and it too might be lazily bound. */
9538 if (mips16_cfun_returns_in_fpr_p ())
9542 return mips_find_gp_ref (&cfun->machine->has_inflexible_gp_insn_p,
9543 mips_insn_has_inflexible_gp_ref_p);
9546 /* Return true if INSN refers to the global pointer in a "flexible" way.
9547 See mips_cfun_has_flexible_gp_ref_p for details. */
9550 mips_insn_has_flexible_gp_ref_p (rtx insn)
9552 return (get_attr_got (insn) != GOT_UNSET
9553 || mips_small_data_pattern_p (PATTERN (insn))
9554 || reg_overlap_mentioned_p (pic_offset_table_rtx, PATTERN (insn)));
9557 /* Return true if the current function references the global pointer,
9558 but if those references do not inherently require the global pointer
9559 to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */
9562 mips_cfun_has_flexible_gp_ref_p (void)
9564 /* Reload can sometimes introduce constant pool references
9565 into a function that otherwise didn't need them. For example,
9566 suppose we have an instruction like:
9568 (set (reg:DF R1) (float:DF (reg:SI R2)))
9570 If R2 turns out to be a constant such as 1, the instruction may
9571 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
9572 the option of using this constant if R2 doesn't get allocated
9575 In cases like these, reload will have added the constant to the
9576 pool but no instruction will yet refer to it. */
9577 if (TARGET_ABICALLS_PIC2 && !reload_completed && crtl->uses_const_pool)
9580 return mips_find_gp_ref (&cfun->machine->has_flexible_gp_insn_p,
9581 mips_insn_has_flexible_gp_ref_p);
9584 /* Return the register that should be used as the global pointer
9585 within this function. Return INVALID_REGNUM if the function
9586 doesn't need a global pointer. */
9589 mips_global_pointer (void)
9593 /* $gp is always available unless we're using a GOT. */
9594 if (!TARGET_USE_GOT)
9595 return GLOBAL_POINTER_REGNUM;
9597 /* If there are inflexible references to $gp, we must use the
9598 standard register. */
9599 if (mips_cfun_has_inflexible_gp_ref_p ())
9600 return GLOBAL_POINTER_REGNUM;
9602 /* If there are no current references to $gp, then the only uses
9603 we can introduce later are those involved in long branches. */
9604 if (TARGET_ABSOLUTE_JUMPS && !mips_cfun_has_flexible_gp_ref_p ())
9605 return INVALID_REGNUM;
9607 /* If the global pointer is call-saved, try to use a call-clobbered
9609 if (TARGET_CALL_SAVED_GP && crtl->is_leaf)
9610 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
9611 if (!df_regs_ever_live_p (regno)
9612 && call_really_used_regs[regno]
9613 && !fixed_regs[regno]
9614 && regno != PIC_FUNCTION_ADDR_REGNUM)
9617 return GLOBAL_POINTER_REGNUM;
9620 /* Return true if the current function's prologue must load the global
9621 pointer value into pic_offset_table_rtx and store the same value in
9622 the function's cprestore slot (if any).
9624 One problem we have to deal with is that, when emitting GOT-based
9625 position independent code, long-branch sequences will need to load
9626 the address of the branch target from the GOT. We don't know until
9627 the very end of compilation whether (and where) the function needs
9628 long branches, so we must ensure that _any_ branch can access the
9629 global pointer in some form. However, we do not want to pessimize
9630 the usual case in which all branches are short.
9632 We handle this as follows:
9634 (1) During reload, we set cfun->machine->global_pointer to
9635 INVALID_REGNUM if we _know_ that the current function
9636 doesn't need a global pointer. This is only valid if
9637 long branches don't need the GOT.
9639 Otherwise, we assume that we might need a global pointer
9640 and pick an appropriate register.
9642 (2) If cfun->machine->global_pointer != INVALID_REGNUM,
9643 we ensure that the global pointer is available at every
9644 block boundary bar entry and exit. We do this in one of two ways:
9646 - If the function has a cprestore slot, we ensure that this
9647 slot is valid at every branch. However, as explained in
9648 point (6) below, there is no guarantee that pic_offset_table_rtx
9649 itself is valid if new uses of the global pointer are introduced
9650 after the first post-epilogue split.
9652 We guarantee that the cprestore slot is valid by loading it
9653 into a fake register, CPRESTORE_SLOT_REGNUM. We then make
9654 this register live at every block boundary bar function entry
9655 and exit. It is then invalid to move the load (and thus the
9656 preceding store) across a block boundary.
9658 - If the function has no cprestore slot, we guarantee that
9659 pic_offset_table_rtx itself is valid at every branch.
9661 See mips_eh_uses for the handling of the register liveness.
9663 (3) During prologue and epilogue generation, we emit "ghost"
9664 placeholder instructions to manipulate the global pointer.
9666 (4) During prologue generation, we set cfun->machine->must_initialize_gp_p
9667 and cfun->machine->must_restore_gp_when_clobbered_p if we already know
9668 that the function needs a global pointer. (There is no need to set
9669 them earlier than this, and doing it as late as possible leads to
9670 fewer false positives.)
9672 (5) If cfun->machine->must_initialize_gp_p is true during a
9673 split_insns pass, we split the ghost instructions into real
9674 instructions. These split instructions can then be optimized in
9675 the usual way. Otherwise, we keep the ghost instructions intact,
9676 and optimize for the case where they aren't needed. We still
9677 have the option of splitting them later, if we need to introduce
9678 new uses of the global pointer.
9680 For example, the scheduler ignores a ghost instruction that
9681 stores $28 to the stack, but it handles the split form of
9682 the ghost instruction as an ordinary store.
9684 (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p
9685 is true during the first post-epilogue split_insns pass, we split
9686 calls and restore_gp patterns into instructions that explicitly
9687 load pic_offset_table_rtx from the cprestore slot. Otherwise,
9688 we split these patterns into instructions that _don't_ load from
9691 If cfun->machine->must_restore_gp_when_clobbered_p is true at the
9692 time of the split, then any instructions that exist at that time
9693 can make free use of pic_offset_table_rtx. However, if we want
9694 to introduce new uses of the global pointer after the split,
9695 we must explicitly load the value from the cprestore slot, since
9696 pic_offset_table_rtx itself might not be valid at a given point
9699 The idea is that we want to be able to delete redundant
9700 loads from the cprestore slot in the usual case where no
9701 long branches are needed.
9703 (7) If cfun->machine->must_initialize_gp_p is still false at the end
9704 of md_reorg, we decide whether the global pointer is needed for
9705 long branches. If so, we set cfun->machine->must_initialize_gp_p
9706 to true and split the ghost instructions into real instructions
9709 Note that the ghost instructions must have a zero length for three reasons:
9711 - Giving the length of the underlying $gp sequence might cause
9712 us to use long branches in cases where they aren't really needed.
9714 - They would perturb things like alignment calculations.
9716 - More importantly, the hazard detection in md_reorg relies on
9717 empty instructions having a zero length.
9719 If we find a long branch and split the ghost instructions at the
9720 end of md_reorg, the split could introduce more long branches.
9721 That isn't a problem though, because we still do the split before
9722 the final shorten_branches pass.
9724 This is extremely ugly, but it seems like the best compromise between
9725 correctness and efficiency. */
9728 mips_must_initialize_gp_p (void)
9730 return cfun->machine->must_initialize_gp_p;
9733 /* Return true if REGNO is a register that is ordinarily call-clobbered
9734 but must nevertheless be preserved by an interrupt handler. */
9737 mips_interrupt_extra_call_saved_reg_p (unsigned int regno)
9739 if (MD_REG_P (regno))
9742 if (TARGET_DSP && DSP_ACC_REG_P (regno))
9745 if (GP_REG_P (regno) && !cfun->machine->use_shadow_register_set_p)
9747 /* $0 is hard-wired. */
9748 if (regno == GP_REG_FIRST)
9751 /* The interrupt handler can treat kernel registers as
9752 scratch registers. */
9753 if (KERNEL_REG_P (regno))
9756 /* The function will return the stack pointer to its original value
9758 if (regno == STACK_POINTER_REGNUM)
9761 /* Otherwise, return true for registers that aren't ordinarily
9763 return call_really_used_regs[regno];
9769 /* Return true if the current function should treat register REGNO
9773 mips_cfun_call_saved_reg_p (unsigned int regno)
9775 /* If the user makes an ordinarily-call-saved register global,
9776 that register is no longer call-saved. */
9777 if (global_regs[regno])
9780 /* Interrupt handlers need to save extra registers. */
9781 if (cfun->machine->interrupt_handler_p
9782 && mips_interrupt_extra_call_saved_reg_p (regno))
9785 /* call_insns preserve $28 unless they explicitly say otherwise,
9786 so call_really_used_regs[] treats $28 as call-saved. However,
9787 we want the ABI property rather than the default call_insn
9789 return (regno == GLOBAL_POINTER_REGNUM
9790 ? TARGET_CALL_SAVED_GP
9791 : !call_really_used_regs[regno]);
9794 /* Return true if the function body might clobber register REGNO.
9795 We know that REGNO is call-saved. */
9798 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno)
9800 /* Some functions should be treated as clobbering all call-saved
9802 if (crtl->saves_all_registers)
9805 /* DF handles cases where a register is explicitly referenced in
9806 the rtl. Incoming values are passed in call-clobbered registers,
9807 so we can assume that any live call-saved register is set within
9809 if (df_regs_ever_live_p (regno))
9812 /* Check for registers that are clobbered by FUNCTION_PROFILER.
9813 These clobbers are not explicit in the rtl. */
9814 if (crtl->profile && MIPS_SAVE_REG_FOR_PROFILING_P (regno))
9817 /* If we're using a call-saved global pointer, the function's
9818 prologue will need to set it up. */
9819 if (cfun->machine->global_pointer == regno)
9822 /* The function's prologue will need to set the frame pointer if
9823 frame_pointer_needed. */
9824 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
9827 /* If a MIPS16 function returns a value in FPRs, its epilogue
9828 will need to call an external libgcc routine. This yet-to-be
9829 generated call_insn will clobber $31. */
9830 if (regno == RETURN_ADDR_REGNUM && mips16_cfun_returns_in_fpr_p ())
9833 /* If REGNO is ordinarily call-clobbered, we must assume that any
9834 called function could modify it. */
9835 if (cfun->machine->interrupt_handler_p
9837 && mips_interrupt_extra_call_saved_reg_p (regno))
9843 /* Return true if the current function must save register REGNO. */
9846 mips_save_reg_p (unsigned int regno)
9848 if (mips_cfun_call_saved_reg_p (regno))
9850 if (mips_cfun_might_clobber_call_saved_reg_p (regno))
9853 /* Save both registers in an FPR pair if either one is used. This is
9854 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
9855 register to be used without the even register. */
9856 if (FP_REG_P (regno)
9857 && MAX_FPRS_PER_FMT == 2
9858 && mips_cfun_might_clobber_call_saved_reg_p (regno + 1))
9862 /* We need to save the incoming return address if __builtin_eh_return
9863 is being used to set a different return address. */
9864 if (regno == RETURN_ADDR_REGNUM && crtl->calls_eh_return)
9870 /* Populate the current function's mips_frame_info structure.
9872 MIPS stack frames look like:
9874 +-------------------------------+
9876 | incoming stack arguments |
9878 +-------------------------------+
9880 | caller-allocated save area |
9881 A | for register arguments |
9883 +-------------------------------+ <-- incoming stack pointer
9885 | callee-allocated save area |
9886 B | for arguments that are |
9887 | split between registers and |
9890 +-------------------------------+ <-- arg_pointer_rtx
9892 C | callee-allocated save area |
9893 | for register varargs |
9895 +-------------------------------+ <-- frame_pointer_rtx
9896 | | + cop0_sp_offset
9897 | COP0 reg save area | + UNITS_PER_WORD
9899 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
9900 | | + UNITS_PER_WORD
9901 | accumulator save area |
9903 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
9904 | | + UNITS_PER_HWFPVALUE
9907 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset
9908 | | + UNITS_PER_WORD
9911 +-------------------------------+ <-- frame_pointer_rtx with
9912 | | \ -fstack-protector
9913 | local variables | | var_size
9915 +-------------------------------+
9917 | $gp save area | | cprestore_size
9919 P +-------------------------------+ <-- hard_frame_pointer_rtx for
9921 | outgoing stack arguments | |
9923 +-------------------------------+ | args_size
9925 | caller-allocated save area | |
9926 | for register arguments | |
9928 +-------------------------------+ <-- stack_pointer_rtx
9929 frame_pointer_rtx without
9931 hard_frame_pointer_rtx for
9934 At least two of A, B and C will be empty.
9936 Dynamic stack allocations such as alloca insert data at point P.
9937 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
9938 hard_frame_pointer_rtx unchanged. */
9941 mips_compute_frame_info (void)
9943 struct mips_frame_info *frame;
9944 HOST_WIDE_INT offset, size;
9945 unsigned int regno, i;
9947 /* Set this function's interrupt properties. */
9948 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
9951 error ("the %<interrupt%> attribute requires a MIPS32r2 processor");
9952 else if (TARGET_HARD_FLOAT)
9953 error ("the %<interrupt%> attribute requires %<-msoft-float%>");
9954 else if (TARGET_MIPS16)
9955 error ("interrupt handlers cannot be MIPS16 functions");
9958 cfun->machine->interrupt_handler_p = true;
9959 cfun->machine->use_shadow_register_set_p =
9960 mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl));
9961 cfun->machine->keep_interrupts_masked_p =
9962 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl));
9963 cfun->machine->use_debug_exception_return_p =
9964 mips_use_debug_exception_return_p (TREE_TYPE
9965 (current_function_decl));
9969 frame = &cfun->machine->frame;
9970 memset (frame, 0, sizeof (*frame));
9971 size = get_frame_size ();
9973 cfun->machine->global_pointer = mips_global_pointer ();
9975 /* The first two blocks contain the outgoing argument area and the $gp save
9976 slot. This area isn't needed in leaf functions, but if the
9977 target-independent frame size is nonzero, we have already committed to
9978 allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */
9979 if ((size == 0 || FRAME_GROWS_DOWNWARD) && crtl->is_leaf)
9981 /* The MIPS 3.0 linker does not like functions that dynamically
9982 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
9983 looks like we are trying to create a second frame pointer to the
9984 function, so allocate some stack space to make it happy. */
9985 if (cfun->calls_alloca)
9986 frame->args_size = REG_PARM_STACK_SPACE (cfun->decl);
9988 frame->args_size = 0;
9989 frame->cprestore_size = 0;
9993 frame->args_size = crtl->outgoing_args_size;
9994 frame->cprestore_size = MIPS_GP_SAVE_AREA_SIZE;
9996 offset = frame->args_size + frame->cprestore_size;
9998 /* Move above the local variables. */
9999 frame->var_size = MIPS_STACK_ALIGN (size);
10000 offset += frame->var_size;
10002 /* Find out which GPRs we need to save. */
10003 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
10004 if (mips_save_reg_p (regno))
10007 frame->mask |= 1 << (regno - GP_REG_FIRST);
10010 /* If this function calls eh_return, we must also save and restore the
10011 EH data registers. */
10012 if (crtl->calls_eh_return)
10013 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; i++)
10016 frame->mask |= 1 << (EH_RETURN_DATA_REGNO (i) - GP_REG_FIRST);
10019 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
10020 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
10021 save all later registers too. */
10022 if (GENERATE_MIPS16E_SAVE_RESTORE)
10024 mips16e_mask_registers (&frame->mask, mips16e_s2_s8_regs,
10025 ARRAY_SIZE (mips16e_s2_s8_regs), &frame->num_gp);
10026 mips16e_mask_registers (&frame->mask, mips16e_a0_a3_regs,
10027 ARRAY_SIZE (mips16e_a0_a3_regs), &frame->num_gp);
10030 /* Move above the GPR save area. */
10031 if (frame->num_gp > 0)
10033 offset += MIPS_STACK_ALIGN (frame->num_gp * UNITS_PER_WORD);
10034 frame->gp_sp_offset = offset - UNITS_PER_WORD;
10037 /* Find out which FPRs we need to save. This loop must iterate over
10038 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
10039 if (TARGET_HARD_FLOAT)
10040 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += MAX_FPRS_PER_FMT)
10041 if (mips_save_reg_p (regno))
10043 frame->num_fp += MAX_FPRS_PER_FMT;
10044 frame->fmask |= ~(~0 << MAX_FPRS_PER_FMT) << (regno - FP_REG_FIRST);
10047 /* Move above the FPR save area. */
10048 if (frame->num_fp > 0)
10050 offset += MIPS_STACK_ALIGN (frame->num_fp * UNITS_PER_FPREG);
10051 frame->fp_sp_offset = offset - UNITS_PER_HWFPVALUE;
10054 /* Add in space for the interrupt context information. */
10055 if (cfun->machine->interrupt_handler_p)
10058 if (mips_save_reg_p (LO_REGNUM) || mips_save_reg_p (HI_REGNUM))
10061 frame->acc_mask |= (1 << 0);
10064 /* Check accumulators 1, 2, 3. */
10065 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
10066 if (mips_save_reg_p (i) || mips_save_reg_p (i + 1))
10069 frame->acc_mask |= 1 << (((i - DSP_ACC_REG_FIRST) / 2) + 1);
10072 /* All interrupt context functions need space to preserve STATUS. */
10073 frame->num_cop0_regs++;
10075 /* If we don't keep interrupts masked, we need to save EPC. */
10076 if (!cfun->machine->keep_interrupts_masked_p)
10077 frame->num_cop0_regs++;
10080 /* Move above the accumulator save area. */
10081 if (frame->num_acc > 0)
10083 /* Each accumulator needs 2 words. */
10084 offset += frame->num_acc * 2 * UNITS_PER_WORD;
10085 frame->acc_sp_offset = offset - UNITS_PER_WORD;
10088 /* Move above the COP0 register save area. */
10089 if (frame->num_cop0_regs > 0)
10091 offset += frame->num_cop0_regs * UNITS_PER_WORD;
10092 frame->cop0_sp_offset = offset - UNITS_PER_WORD;
10095 /* Move above the callee-allocated varargs save area. */
10096 offset += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
10097 frame->arg_pointer_offset = offset;
10099 /* Move above the callee-allocated area for pretend stack arguments. */
10100 offset += crtl->args.pretend_args_size;
10101 frame->total_size = offset;
10103 /* Work out the offsets of the save areas from the top of the frame. */
10104 if (frame->gp_sp_offset > 0)
10105 frame->gp_save_offset = frame->gp_sp_offset - offset;
10106 if (frame->fp_sp_offset > 0)
10107 frame->fp_save_offset = frame->fp_sp_offset - offset;
10108 if (frame->acc_sp_offset > 0)
10109 frame->acc_save_offset = frame->acc_sp_offset - offset;
10110 if (frame->num_cop0_regs > 0)
10111 frame->cop0_save_offset = frame->cop0_sp_offset - offset;
10113 /* MIPS16 code offsets the frame pointer by the size of the outgoing
10114 arguments. This tends to increase the chances of using unextended
10115 instructions for local variables and incoming arguments. */
10117 frame->hard_frame_pointer_offset = frame->args_size;
10120 /* Return the style of GP load sequence that is being used for the
10121 current function. */
10123 enum mips_loadgp_style
10124 mips_current_loadgp_style (void)
10126 if (!TARGET_USE_GOT || cfun->machine->global_pointer == INVALID_REGNUM)
10127 return LOADGP_NONE;
10129 if (TARGET_RTP_PIC)
10132 if (TARGET_ABSOLUTE_ABICALLS)
10133 return LOADGP_ABSOLUTE;
10135 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
10138 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
10141 mips_frame_pointer_required (void)
10143 /* If the function contains dynamic stack allocations, we need to
10144 use the frame pointer to access the static parts of the frame. */
10145 if (cfun->calls_alloca)
10148 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
10149 reload may be unable to compute the address of a local variable,
10150 since there is no way to add a large constant to the stack pointer
10151 without using a second temporary register. */
10154 mips_compute_frame_info ();
10155 if (!SMALL_OPERAND (cfun->machine->frame.total_size))
10162 /* Make sure that we're not trying to eliminate to the wrong hard frame
10166 mips_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
10168 return (to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM);
10171 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
10172 or argument pointer. TO is either the stack pointer or hard frame
10176 mips_initial_elimination_offset (int from, int to)
10178 HOST_WIDE_INT offset;
10180 mips_compute_frame_info ();
10182 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */
10185 case FRAME_POINTER_REGNUM:
10186 if (FRAME_GROWS_DOWNWARD)
10187 offset = (cfun->machine->frame.args_size
10188 + cfun->machine->frame.cprestore_size
10189 + cfun->machine->frame.var_size);
10194 case ARG_POINTER_REGNUM:
10195 offset = cfun->machine->frame.arg_pointer_offset;
10199 gcc_unreachable ();
10202 if (to == HARD_FRAME_POINTER_REGNUM)
10203 offset -= cfun->machine->frame.hard_frame_pointer_offset;
10208 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
10211 mips_extra_live_on_entry (bitmap regs)
10213 if (TARGET_USE_GOT)
10215 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
10216 the global pointer. */
10217 if (!TARGET_ABSOLUTE_ABICALLS)
10218 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
10220 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
10221 the global pointer. */
10223 bitmap_set_bit (regs, MIPS16_PIC_TEMP_REGNUM);
10225 /* See the comment above load_call<mode> for details. */
10226 bitmap_set_bit (regs, GOT_VERSION_REGNUM);
10230 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
10234 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
10239 return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);
10242 /* Emit code to change the current function's return address to
10243 ADDRESS. SCRATCH is available as a scratch register, if needed.
10244 ADDRESS and SCRATCH are both word-mode GPRs. */
10247 mips_set_return_address (rtx address, rtx scratch)
10251 gcc_assert (BITSET_P (cfun->machine->frame.mask, RETURN_ADDR_REGNUM));
10252 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
10253 cfun->machine->frame.gp_sp_offset);
10254 mips_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address);
10257 /* Return true if the current function has a cprestore slot. */
10260 mips_cfun_has_cprestore_slot_p (void)
10262 return (cfun->machine->global_pointer != INVALID_REGNUM
10263 && cfun->machine->frame.cprestore_size > 0);
10266 /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the
10267 cprestore slot. LOAD_P is true if the caller wants to load from
10268 the cprestore slot; it is false if the caller wants to store to
10272 mips_get_cprestore_base_and_offset (rtx *base, HOST_WIDE_INT *offset,
10275 const struct mips_frame_info *frame;
10277 frame = &cfun->machine->frame;
10278 /* .cprestore always uses the stack pointer instead of the frame pointer.
10279 We have a free choice for direct stores for non-MIPS16 functions,
10280 and for MIPS16 functions whose cprestore slot is in range of the
10281 stack pointer. Using the stack pointer would sometimes give more
10282 (early) scheduling freedom, but using the frame pointer would
10283 sometimes give more (late) scheduling freedom. It's hard to
10284 predict which applies to a given function, so let's keep things
10287 Loads must always use the frame pointer in functions that call
10288 alloca, and there's little benefit to using the stack pointer
10290 if (frame_pointer_needed && !(TARGET_CPRESTORE_DIRECTIVE && !load_p))
10292 *base = hard_frame_pointer_rtx;
10293 *offset = frame->args_size - frame->hard_frame_pointer_offset;
10297 *base = stack_pointer_rtx;
10298 *offset = frame->args_size;
10302 /* Return true if X is the load or store address of the cprestore slot;
10303 LOAD_P says which. */
10306 mips_cprestore_address_p (rtx x, bool load_p)
10308 rtx given_base, required_base;
10309 HOST_WIDE_INT given_offset, required_offset;
10311 mips_split_plus (x, &given_base, &given_offset);
10312 mips_get_cprestore_base_and_offset (&required_base, &required_offset, load_p);
10313 return given_base == required_base && given_offset == required_offset;
10316 /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are
10317 going to load from it, false if we are going to store to it.
10318 Use TEMP as a temporary register if need be. */
10321 mips_cprestore_slot (rtx temp, bool load_p)
10324 HOST_WIDE_INT offset;
10326 mips_get_cprestore_base_and_offset (&base, &offset, load_p);
10327 return gen_frame_mem (Pmode, mips_add_offset (temp, base, offset));
10330 /* Emit instructions to save global pointer value GP into cprestore
10331 slot MEM. OFFSET is the offset that MEM applies to the base register.
10333 MEM may not be a legitimate address. If it isn't, TEMP is a
10334 temporary register that can be used, otherwise it is a SCRATCH. */
10337 mips_save_gp_to_cprestore_slot (rtx mem, rtx offset, rtx gp, rtx temp)
10339 if (TARGET_CPRESTORE_DIRECTIVE)
10341 gcc_assert (gp == pic_offset_table_rtx);
10342 emit_insn (PMODE_INSN (gen_cprestore, (mem, offset)));
10345 mips_emit_move (mips_cprestore_slot (temp, false), gp);
10348 /* Restore $gp from its save slot, using TEMP as a temporary base register
10349 if need be. This function is for o32 and o64 abicalls only.
10351 See mips_must_initialize_gp_p for details about how we manage the
10355 mips_restore_gp_from_cprestore_slot (rtx temp)
10357 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI && epilogue_completed);
10359 if (!cfun->machine->must_restore_gp_when_clobbered_p)
10361 emit_note (NOTE_INSN_DELETED);
10367 mips_emit_move (temp, mips_cprestore_slot (temp, true));
10368 mips_emit_move (pic_offset_table_rtx, temp);
10371 mips_emit_move (pic_offset_table_rtx, mips_cprestore_slot (temp, true));
10372 if (!TARGET_EXPLICIT_RELOCS)
10373 emit_insn (gen_blockage ());
10376 /* A function to save or store a register. The first argument is the
10377 register and the second is the stack slot. */
10378 typedef void (*mips_save_restore_fn) (rtx, rtx);
10380 /* Use FN to save or restore register REGNO. MODE is the register's
10381 mode and OFFSET is the offset of its save slot from the current
10385 mips_save_restore_reg (enum machine_mode mode, int regno,
10386 HOST_WIDE_INT offset, mips_save_restore_fn fn)
10390 mem = gen_frame_mem (mode, plus_constant (Pmode, stack_pointer_rtx,
10392 fn (gen_rtx_REG (mode, regno), mem);
10395 /* Call FN for each accumlator that is saved by the current function.
10396 SP_OFFSET is the offset of the current stack pointer from the start
10400 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
10402 HOST_WIDE_INT offset;
10405 offset = cfun->machine->frame.acc_sp_offset - sp_offset;
10406 if (BITSET_P (cfun->machine->frame.acc_mask, 0))
10408 mips_save_restore_reg (word_mode, LO_REGNUM, offset, fn);
10409 offset -= UNITS_PER_WORD;
10410 mips_save_restore_reg (word_mode, HI_REGNUM, offset, fn);
10411 offset -= UNITS_PER_WORD;
10414 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
10415 if (BITSET_P (cfun->machine->frame.acc_mask,
10416 ((regno - DSP_ACC_REG_FIRST) / 2) + 1))
10418 mips_save_restore_reg (word_mode, regno, offset, fn);
10419 offset -= UNITS_PER_WORD;
10423 /* Save register REG to MEM. Make the instruction frame-related. */
10426 mips_save_reg (rtx reg, rtx mem)
10428 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
10432 mips_emit_move_or_split (mem, reg, SPLIT_IF_NECESSARY);
10434 x1 = mips_frame_set (mips_subword (mem, false),
10435 mips_subword (reg, false));
10436 x2 = mips_frame_set (mips_subword (mem, true),
10437 mips_subword (reg, true));
10438 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
10441 mips_emit_save_slot_move (mem, reg, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
10444 /* Capture the register combinations that are allowed in a SWM or LWM
10445 instruction. The entries are ordered by number of registers set in
10446 the mask. We also ignore the single register encodings because a
10447 normal SW/LW is preferred. */
10449 static const unsigned int umips_swm_mask[17] = {
10450 0xc0ff0000, 0x80ff0000, 0x40ff0000, 0x807f0000,
10451 0x00ff0000, 0x803f0000, 0x007f0000, 0x801f0000,
10452 0x003f0000, 0x800f0000, 0x001f0000, 0x80070000,
10453 0x000f0000, 0x80030000, 0x00070000, 0x80010000,
10457 static const unsigned int umips_swm_encoding[17] = {
10458 25, 24, 9, 23, 8, 22, 7, 21, 6, 20, 5, 19, 4, 18, 3, 17, 2
10461 /* Try to use a microMIPS LWM or SWM instruction to save or restore
10462 as many GPRs in *MASK as possible. *OFFSET is the offset from the
10463 stack pointer of the topmost save slot.
10465 Remove from *MASK all registers that were handled using LWM and SWM.
10466 Update *OFFSET so that it points to the first unused save slot. */
10469 umips_build_save_restore (mips_save_restore_fn fn,
10470 unsigned *mask, HOST_WIDE_INT *offset)
10474 rtx pattern, set, reg, mem;
10475 HOST_WIDE_INT this_offset;
10478 /* Try matching $16 to $31 (s0 to ra). */
10479 for (i = 0; i < ARRAY_SIZE (umips_swm_mask); i++)
10480 if ((*mask & 0xffff0000) == umips_swm_mask[i])
10483 if (i == ARRAY_SIZE (umips_swm_mask))
10486 /* Get the offset of the lowest save slot. */
10487 nregs = (umips_swm_encoding[i] & 0xf) + (umips_swm_encoding[i] >> 4);
10488 this_offset = *offset - UNITS_PER_WORD * (nregs - 1);
10490 /* LWM/SWM can only support offsets from -2048 to 2047. */
10491 if (!UMIPS_12BIT_OFFSET_P (this_offset))
10494 /* Create the final PARALLEL. */
10495 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nregs));
10496 this_base = stack_pointer_rtx;
10498 /* For registers $16-$23 and $30. */
10499 for (j = 0; j < (umips_swm_encoding[i] & 0xf); j++)
10501 HOST_WIDE_INT offset = this_offset + j * UNITS_PER_WORD;
10502 mem = gen_frame_mem (SImode, plus_constant (Pmode, this_base, offset));
10503 unsigned int regno = (j != 8) ? 16 + j : 30;
10504 *mask &= ~(1 << regno);
10505 reg = gen_rtx_REG (SImode, regno);
10506 if (fn == mips_save_reg)
10507 set = mips_frame_set (mem, reg);
10510 set = gen_rtx_SET (VOIDmode, reg, mem);
10511 mips_add_cfa_restore (reg);
10513 XVECEXP (pattern, 0, j) = set;
10516 /* For register $31. */
10517 if (umips_swm_encoding[i] >> 4)
10519 HOST_WIDE_INT offset = this_offset + j * UNITS_PER_WORD;
10520 *mask &= ~(1 << 31);
10521 mem = gen_frame_mem (SImode, plus_constant (Pmode, this_base, offset));
10522 reg = gen_rtx_REG (SImode, 31);
10523 if (fn == mips_save_reg)
10524 set = mips_frame_set (mem, reg);
10527 set = gen_rtx_SET (VOIDmode, reg, mem);
10528 mips_add_cfa_restore (reg);
10530 XVECEXP (pattern, 0, j) = set;
10533 pattern = emit_insn (pattern);
10534 if (fn == mips_save_reg)
10535 RTX_FRAME_RELATED_P (pattern) = 1;
10537 /* Adjust the last offset. */
10538 *offset -= UNITS_PER_WORD * nregs;
10543 /* Call FN for each register that is saved by the current function.
10544 SP_OFFSET is the offset of the current stack pointer from the start
10548 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset,
10549 mips_save_restore_fn fn)
10551 enum machine_mode fpr_mode;
10553 const struct mips_frame_info *frame = &cfun->machine->frame;
10554 HOST_WIDE_INT offset;
10557 /* Save registers starting from high to low. The debuggers prefer at least
10558 the return register be stored at func+4, and also it allows us not to
10559 need a nop in the epilogue if at least one register is reloaded in
10560 addition to return address. */
10561 offset = frame->gp_sp_offset - sp_offset;
10562 mask = frame->mask;
10564 if (TARGET_MICROMIPS)
10565 umips_build_save_restore (fn, &mask, &offset);
10567 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
10568 if (BITSET_P (mask, regno - GP_REG_FIRST))
10570 /* Record the ra offset for use by mips_function_profiler. */
10571 if (regno == RETURN_ADDR_REGNUM)
10572 cfun->machine->frame.ra_fp_offset = offset + sp_offset;
10573 mips_save_restore_reg (word_mode, regno, offset, fn);
10574 offset -= UNITS_PER_WORD;
10577 /* This loop must iterate over the same space as its companion in
10578 mips_compute_frame_info. */
10579 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
10580 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
10581 for (regno = FP_REG_LAST - MAX_FPRS_PER_FMT + 1;
10582 regno >= FP_REG_FIRST;
10583 regno -= MAX_FPRS_PER_FMT)
10584 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
10586 mips_save_restore_reg (fpr_mode, regno, offset, fn);
10587 offset -= GET_MODE_SIZE (fpr_mode);
10591 /* Return true if a move between register REGNO and its save slot (MEM)
10592 can be done in a single move. LOAD_P is true if we are loading
10593 from the slot, false if we are storing to it. */
10596 mips_direct_save_slot_move_p (unsigned int regno, rtx mem, bool load_p)
10598 /* There is a specific MIPS16 instruction for saving $31 to the stack. */
10599 if (TARGET_MIPS16 && !load_p && regno == RETURN_ADDR_REGNUM)
10602 return mips_secondary_reload_class (REGNO_REG_CLASS (regno),
10603 GET_MODE (mem), mem, load_p) == NO_REGS;
10606 /* Emit a move from SRC to DEST, given that one of them is a register
10607 save slot and that the other is a register. TEMP is a temporary
10608 GPR of the same mode that is available if need be. */
10611 mips_emit_save_slot_move (rtx dest, rtx src, rtx temp)
10613 unsigned int regno;
10618 regno = REGNO (src);
10623 regno = REGNO (dest);
10627 if (regno == cfun->machine->global_pointer && !mips_must_initialize_gp_p ())
10629 /* We don't yet know whether we'll need this instruction or not.
10630 Postpone the decision by emitting a ghost move. This move
10631 is specifically not frame-related; only the split version is. */
10633 emit_insn (gen_move_gpdi (dest, src));
10635 emit_insn (gen_move_gpsi (dest, src));
10639 if (regno == HI_REGNUM)
10643 mips_emit_move (temp, src);
10645 emit_insn (gen_mthisi_di (gen_rtx_REG (TImode, MD_REG_FIRST),
10646 temp, gen_rtx_REG (DImode, LO_REGNUM)));
10648 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode, MD_REG_FIRST),
10649 temp, gen_rtx_REG (SImode, LO_REGNUM)));
10654 emit_insn (gen_mfhidi_ti (temp,
10655 gen_rtx_REG (TImode, MD_REG_FIRST)));
10657 emit_insn (gen_mfhisi_di (temp,
10658 gen_rtx_REG (DImode, MD_REG_FIRST)));
10659 mips_emit_move (dest, temp);
10662 else if (mips_direct_save_slot_move_p (regno, mem, mem == src))
10663 mips_emit_move (dest, src);
10666 gcc_assert (!reg_overlap_mentioned_p (dest, temp));
10667 mips_emit_move (temp, src);
10668 mips_emit_move (dest, temp);
10671 mips_set_frame_expr (mips_frame_set (dest, src));
10674 /* If we're generating n32 or n64 abicalls, and the current function
10675 does not use $28 as its global pointer, emit a cplocal directive.
10676 Use pic_offset_table_rtx as the argument to the directive. */
10679 mips_output_cplocal (void)
10681 if (!TARGET_EXPLICIT_RELOCS
10682 && mips_must_initialize_gp_p ()
10683 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
10684 output_asm_insn (".cplocal %+", 0);
10687 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
10690 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
10692 const char *fnname;
10694 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
10695 floating-point arguments. */
10697 && TARGET_HARD_FLOAT_ABI
10698 && crtl->args.info.fp_code != 0)
10699 mips16_build_function_stub ();
10701 /* Get the function name the same way that toplev.c does before calling
10702 assemble_start_function. This is needed so that the name used here
10703 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10704 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
10705 mips_start_function_definition (fnname, TARGET_MIPS16);
10707 /* Output MIPS-specific frame information. */
10708 if (!flag_inhibit_size_directive)
10710 const struct mips_frame_info *frame;
10712 frame = &cfun->machine->frame;
10714 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
10716 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
10717 "# vars= " HOST_WIDE_INT_PRINT_DEC
10719 ", args= " HOST_WIDE_INT_PRINT_DEC
10720 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
10721 reg_names[frame_pointer_needed
10722 ? HARD_FRAME_POINTER_REGNUM
10723 : STACK_POINTER_REGNUM],
10724 (frame_pointer_needed
10725 ? frame->total_size - frame->hard_frame_pointer_offset
10726 : frame->total_size),
10727 reg_names[RETURN_ADDR_REGNUM],
10729 frame->num_gp, frame->num_fp,
10731 frame->cprestore_size);
10733 /* .mask MASK, OFFSET. */
10734 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
10735 frame->mask, frame->gp_save_offset);
10737 /* .fmask MASK, OFFSET. */
10738 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
10739 frame->fmask, frame->fp_save_offset);
10742 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
10743 Also emit the ".set noreorder; .set nomacro" sequence for functions
10745 if (mips_must_initialize_gp_p ()
10746 && mips_current_loadgp_style () == LOADGP_OLDABI)
10750 /* This is a fixed-form sequence. The position of the
10751 first two instructions is important because of the
10752 way _gp_disp is defined. */
10753 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
10754 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
10755 output_asm_insn ("sll\t$2,16", 0);
10756 output_asm_insn ("addu\t$2,$3", 0);
10760 /* .cpload must be in a .set noreorder but not a
10761 .set nomacro block. */
10762 mips_push_asm_switch (&mips_noreorder);
10763 output_asm_insn (".cpload\t%^", 0);
10764 if (!cfun->machine->all_noreorder_p)
10765 mips_pop_asm_switch (&mips_noreorder);
10767 mips_push_asm_switch (&mips_nomacro);
10770 else if (cfun->machine->all_noreorder_p)
10772 mips_push_asm_switch (&mips_noreorder);
10773 mips_push_asm_switch (&mips_nomacro);
10776 /* Tell the assembler which register we're using as the global
10777 pointer. This is needed for thunks, since they can use either
10778 explicit relocs or assembler macros. */
10779 mips_output_cplocal ();
10782 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
10785 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
10786 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
10788 const char *fnname;
10790 /* Reinstate the normal $gp. */
10791 SET_REGNO (pic_offset_table_rtx, GLOBAL_POINTER_REGNUM);
10792 mips_output_cplocal ();
10794 if (cfun->machine->all_noreorder_p)
10796 mips_pop_asm_switch (&mips_nomacro);
10797 mips_pop_asm_switch (&mips_noreorder);
10800 /* Get the function name the same way that toplev.c does before calling
10801 assemble_start_function. This is needed so that the name used here
10802 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10803 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
10804 mips_end_function_definition (fnname);
10807 /* Emit an optimisation barrier for accesses to the current frame. */
10810 mips_frame_barrier (void)
10812 emit_clobber (gen_frame_mem (BLKmode, stack_pointer_rtx));
10816 /* The __gnu_local_gp symbol. */
10818 static GTY(()) rtx mips_gnu_local_gp;
10820 /* If we're generating n32 or n64 abicalls, emit instructions
10821 to set up the global pointer. */
10824 mips_emit_loadgp (void)
10826 rtx addr, offset, incoming_address, base, index, pic_reg;
10828 pic_reg = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
10829 switch (mips_current_loadgp_style ())
10831 case LOADGP_ABSOLUTE:
10832 if (mips_gnu_local_gp == NULL)
10834 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
10835 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
10837 emit_insn (PMODE_INSN (gen_loadgp_absolute,
10838 (pic_reg, mips_gnu_local_gp)));
10841 case LOADGP_OLDABI:
10842 /* Added by mips_output_function_prologue. */
10845 case LOADGP_NEWABI:
10846 addr = XEXP (DECL_RTL (current_function_decl), 0);
10847 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
10848 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
10849 emit_insn (PMODE_INSN (gen_loadgp_newabi,
10850 (pic_reg, offset, incoming_address)));
10854 base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE));
10855 index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX));
10856 emit_insn (PMODE_INSN (gen_loadgp_rtp, (pic_reg, base, index)));
10864 emit_insn (PMODE_INSN (gen_copygp_mips16,
10865 (pic_offset_table_rtx, pic_reg)));
10867 /* Emit a blockage if there are implicit uses of the GP register.
10868 This includes profiled functions, because FUNCTION_PROFILE uses
10870 if (!TARGET_EXPLICIT_RELOCS || crtl->profile)
10871 emit_insn (gen_loadgp_blockage ());
10874 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
10876 #if PROBE_INTERVAL > 32768
10877 #error Cannot use indexed addressing mode for stack probing
10880 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
10881 inclusive. These are offsets from the current stack pointer. */
10884 mips_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size)
10887 sorry ("-fstack-check=specific not implemented for MIPS16");
10889 /* See if we have a constant small number of probes to generate. If so,
10890 that's the easy case. */
10891 if (first + size <= 32768)
10895 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
10896 it exceeds SIZE. If only one probe is needed, this will not
10897 generate any code. Then probe at FIRST + SIZE. */
10898 for (i = PROBE_INTERVAL; i < size; i += PROBE_INTERVAL)
10899 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
10902 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
10906 /* Otherwise, do the same as above, but in a loop. Note that we must be
10907 extra careful with variables wrapping around because we might be at
10908 the very top (or the very bottom) of the address space and we have
10909 to be able to handle this case properly; in particular, we use an
10910 equality test for the loop condition. */
10913 HOST_WIDE_INT rounded_size;
10914 rtx r3 = MIPS_PROLOGUE_TEMP (Pmode);
10915 rtx r12 = MIPS_PROLOGUE_TEMP2 (Pmode);
10917 /* Sanity check for the addressing mode we're going to use. */
10918 gcc_assert (first <= 32768);
10921 /* Step 1: round SIZE to the previous multiple of the interval. */
10923 rounded_size = size & -PROBE_INTERVAL;
10926 /* Step 2: compute initial and final value of the loop counter. */
10928 /* TEST_ADDR = SP + FIRST. */
10929 emit_insn (gen_rtx_SET (VOIDmode, r3,
10930 plus_constant (Pmode, stack_pointer_rtx,
10933 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
10934 if (rounded_size > 32768)
10936 emit_move_insn (r12, GEN_INT (rounded_size));
10937 emit_insn (gen_rtx_SET (VOIDmode, r12,
10938 gen_rtx_MINUS (Pmode, r3, r12)));
10941 emit_insn (gen_rtx_SET (VOIDmode, r12,
10942 plus_constant (Pmode, r3, -rounded_size)));
10945 /* Step 3: the loop
10947 while (TEST_ADDR != LAST_ADDR)
10949 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
10953 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
10954 until it is equal to ROUNDED_SIZE. */
10956 emit_insn (PMODE_INSN (gen_probe_stack_range, (r3, r3, r12)));
10959 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
10960 that SIZE is equal to ROUNDED_SIZE. */
10962 if (size != rounded_size)
10963 emit_stack_probe (plus_constant (Pmode, r12, rounded_size - size));
10966 /* Make sure nothing is scheduled before we are done. */
10967 emit_insn (gen_blockage ());
10970 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
10971 absolute addresses. */
10974 mips_output_probe_stack_range (rtx reg1, rtx reg2)
10976 static int labelno = 0;
10977 char loop_lab[32], end_lab[32], tmp[64];
10980 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno);
10981 ASM_GENERATE_INTERNAL_LABEL (end_lab, "LPSRE", labelno++);
10983 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
10985 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
10988 strcpy (tmp, "%(%<beq\t%0,%1,");
10989 output_asm_insn (strcat (tmp, &end_lab[1]), xops);
10991 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
10992 xops[1] = GEN_INT (-PROBE_INTERVAL);
10993 if (TARGET_64BIT && TARGET_LONG64)
10994 output_asm_insn ("daddiu\t%0,%0,%1", xops);
10996 output_asm_insn ("addiu\t%0,%0,%1", xops);
10998 /* Probe at TEST_ADDR and branch. */
10999 fprintf (asm_out_file, "\tb\t");
11000 assemble_name_raw (asm_out_file, loop_lab);
11001 fputc ('\n', asm_out_file);
11003 output_asm_insn ("sd\t$0,0(%0)%)", xops);
11005 output_asm_insn ("sw\t$0,0(%0)%)", xops);
11007 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, end_lab);
11012 /* A for_each_rtx callback. Stop the search if *X is a kernel register. */
11015 mips_kernel_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
11017 return REG_P (*x) && KERNEL_REG_P (REGNO (*x));
11020 /* Expand the "prologue" pattern. */
11023 mips_expand_prologue (void)
11025 const struct mips_frame_info *frame;
11026 HOST_WIDE_INT size;
11027 unsigned int nargs;
11030 if (cfun->machine->global_pointer != INVALID_REGNUM)
11032 /* Check whether an insn uses pic_offset_table_rtx, either explicitly
11033 or implicitly. If so, we can commit to using a global pointer
11034 straight away, otherwise we need to defer the decision. */
11035 if (mips_cfun_has_inflexible_gp_ref_p ()
11036 || mips_cfun_has_flexible_gp_ref_p ())
11038 cfun->machine->must_initialize_gp_p = true;
11039 cfun->machine->must_restore_gp_when_clobbered_p = true;
11042 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
11045 frame = &cfun->machine->frame;
11046 size = frame->total_size;
11048 if (flag_stack_usage_info)
11049 current_function_static_stack_size = size;
11051 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK && size)
11052 mips_emit_probe_stack_range (STACK_CHECK_PROTECT, size);
11054 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
11055 bytes beforehand; this is enough to cover the register save area
11056 without going out of range. */
11057 if (((frame->mask | frame->fmask | frame->acc_mask) != 0)
11058 || frame->num_cop0_regs > 0)
11060 HOST_WIDE_INT step1;
11062 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
11063 if (GENERATE_MIPS16E_SAVE_RESTORE)
11065 HOST_WIDE_INT offset;
11066 unsigned int mask, regno;
11068 /* Try to merge argument stores into the save instruction. */
11069 nargs = mips16e_collect_argument_saves ();
11071 /* Build the save instruction. */
11072 mask = frame->mask;
11073 insn = mips16e_build_save_restore (false, &mask, &offset,
11075 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
11076 mips_frame_barrier ();
11079 /* Check if we need to save other registers. */
11080 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
11081 if (BITSET_P (mask, regno - GP_REG_FIRST))
11083 offset -= UNITS_PER_WORD;
11084 mips_save_restore_reg (word_mode, regno,
11085 offset, mips_save_reg);
11090 if (cfun->machine->interrupt_handler_p)
11092 HOST_WIDE_INT offset;
11095 /* If this interrupt is using a shadow register set, we need to
11096 get the stack pointer from the previous register set. */
11097 if (cfun->machine->use_shadow_register_set_p)
11098 emit_insn (gen_mips_rdpgpr (stack_pointer_rtx,
11099 stack_pointer_rtx));
11101 if (!cfun->machine->keep_interrupts_masked_p)
11103 /* Move from COP0 Cause to K0. */
11104 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K0_REG_NUM),
11105 gen_rtx_REG (SImode,
11106 COP0_CAUSE_REG_NUM)));
11107 /* Move from COP0 EPC to K1. */
11108 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
11109 gen_rtx_REG (SImode,
11110 COP0_EPC_REG_NUM)));
11113 /* Allocate the first part of the frame. */
11114 insn = gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx,
11116 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
11117 mips_frame_barrier ();
11120 /* Start at the uppermost location for saving. */
11121 offset = frame->cop0_sp_offset - size;
11122 if (!cfun->machine->keep_interrupts_masked_p)
11124 /* Push EPC into its stack slot. */
11125 mem = gen_frame_mem (word_mode,
11126 plus_constant (Pmode, stack_pointer_rtx,
11128 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
11129 offset -= UNITS_PER_WORD;
11132 /* Move from COP0 Status to K1. */
11133 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
11134 gen_rtx_REG (SImode,
11135 COP0_STATUS_REG_NUM)));
11137 /* Right justify the RIPL in k0. */
11138 if (!cfun->machine->keep_interrupts_masked_p)
11139 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode, K0_REG_NUM),
11140 gen_rtx_REG (SImode, K0_REG_NUM),
11141 GEN_INT (CAUSE_IPL)));
11143 /* Push Status into its stack slot. */
11144 mem = gen_frame_mem (word_mode,
11145 plus_constant (Pmode, stack_pointer_rtx,
11147 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
11148 offset -= UNITS_PER_WORD;
11150 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
11151 if (!cfun->machine->keep_interrupts_masked_p)
11152 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
11155 gen_rtx_REG (SImode, K0_REG_NUM)));
11157 if (!cfun->machine->keep_interrupts_masked_p)
11158 /* Enable interrupts by clearing the KSU ERL and EXL bits.
11159 IE is already the correct value, so we don't have to do
11160 anything explicit. */
11161 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
11164 gen_rtx_REG (SImode, GP_REG_FIRST)));
11166 /* Disable interrupts by clearing the KSU, ERL, EXL,
11168 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
11171 gen_rtx_REG (SImode, GP_REG_FIRST)));
11175 insn = gen_add3_insn (stack_pointer_rtx,
11178 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
11179 mips_frame_barrier ();
11182 mips_for_each_saved_acc (size, mips_save_reg);
11183 mips_for_each_saved_gpr_and_fpr (size, mips_save_reg);
11187 /* Allocate the rest of the frame. */
11190 if (SMALL_OPERAND (-size))
11191 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
11193 GEN_INT (-size)))) = 1;
11196 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
11199 /* There are no instructions to add or subtract registers
11200 from the stack pointer, so use the frame pointer as a
11201 temporary. We should always be using a frame pointer
11202 in this case anyway. */
11203 gcc_assert (frame_pointer_needed);
11204 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
11205 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
11206 hard_frame_pointer_rtx,
11207 MIPS_PROLOGUE_TEMP (Pmode)));
11208 mips_emit_move (stack_pointer_rtx, hard_frame_pointer_rtx);
11211 emit_insn (gen_sub3_insn (stack_pointer_rtx,
11213 MIPS_PROLOGUE_TEMP (Pmode)));
11215 /* Describe the combined effect of the previous instructions. */
11216 mips_set_frame_expr
11217 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
11218 plus_constant (Pmode, stack_pointer_rtx, -size)));
11220 mips_frame_barrier ();
11223 /* Set up the frame pointer, if we're using one. */
11224 if (frame_pointer_needed)
11226 HOST_WIDE_INT offset;
11228 offset = frame->hard_frame_pointer_offset;
11231 insn = mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
11232 RTX_FRAME_RELATED_P (insn) = 1;
11234 else if (SMALL_OPERAND (offset))
11236 insn = gen_add3_insn (hard_frame_pointer_rtx,
11237 stack_pointer_rtx, GEN_INT (offset));
11238 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
11242 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (offset));
11243 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
11244 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
11245 hard_frame_pointer_rtx,
11246 MIPS_PROLOGUE_TEMP (Pmode)));
11247 mips_set_frame_expr
11248 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
11249 plus_constant (Pmode, stack_pointer_rtx, offset)));
11253 mips_emit_loadgp ();
11255 /* Initialize the $gp save slot. */
11256 if (mips_cfun_has_cprestore_slot_p ())
11258 rtx base, mem, gp, temp;
11259 HOST_WIDE_INT offset;
11261 mips_get_cprestore_base_and_offset (&base, &offset, false);
11262 mem = gen_frame_mem (Pmode, plus_constant (Pmode, base, offset));
11263 gp = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
11264 temp = (SMALL_OPERAND (offset)
11265 ? gen_rtx_SCRATCH (Pmode)
11266 : MIPS_PROLOGUE_TEMP (Pmode));
11267 emit_insn (PMODE_INSN (gen_potential_cprestore,
11268 (mem, GEN_INT (offset), gp, temp)));
11270 mips_get_cprestore_base_and_offset (&base, &offset, true);
11271 mem = gen_frame_mem (Pmode, plus_constant (Pmode, base, offset));
11272 emit_insn (PMODE_INSN (gen_use_cprestore, (mem)));
11275 /* We need to search back to the last use of K0 or K1. */
11276 if (cfun->machine->interrupt_handler_p)
11278 for (insn = get_last_insn (); insn != NULL_RTX; insn = PREV_INSN (insn))
11280 && for_each_rtx (&PATTERN (insn), mips_kernel_reg_p, NULL))
11282 /* Emit a move from K1 to COP0 Status after insn. */
11283 gcc_assert (insn != NULL_RTX);
11284 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
11285 gen_rtx_REG (SImode, K1_REG_NUM)),
11289 /* If we are profiling, make sure no instructions are scheduled before
11290 the call to mcount. */
11292 emit_insn (gen_blockage ());
11295 /* Attach all pending register saves to the previous instruction.
11296 Return that instruction. */
11299 mips_epilogue_emit_cfa_restores (void)
11303 insn = get_last_insn ();
11304 gcc_assert (insn && !REG_NOTES (insn));
11305 if (mips_epilogue.cfa_restores)
11307 RTX_FRAME_RELATED_P (insn) = 1;
11308 REG_NOTES (insn) = mips_epilogue.cfa_restores;
11309 mips_epilogue.cfa_restores = 0;
11314 /* Like mips_epilogue_emit_cfa_restores, but also record that the CFA is
11315 now at REG + OFFSET. */
11318 mips_epilogue_set_cfa (rtx reg, HOST_WIDE_INT offset)
11322 insn = mips_epilogue_emit_cfa_restores ();
11323 if (reg != mips_epilogue.cfa_reg || offset != mips_epilogue.cfa_offset)
11325 RTX_FRAME_RELATED_P (insn) = 1;
11326 REG_NOTES (insn) = alloc_reg_note (REG_CFA_DEF_CFA,
11327 plus_constant (Pmode, reg, offset),
11329 mips_epilogue.cfa_reg = reg;
11330 mips_epilogue.cfa_offset = offset;
11334 /* Emit instructions to restore register REG from slot MEM. Also update
11335 the cfa_restores list. */
11338 mips_restore_reg (rtx reg, rtx mem)
11340 /* There's no MIPS16 instruction to load $31 directly. Load into
11341 $7 instead and adjust the return insn appropriately. */
11342 if (TARGET_MIPS16 && REGNO (reg) == RETURN_ADDR_REGNUM)
11343 reg = gen_rtx_REG (GET_MODE (reg), GP_REG_FIRST + 7);
11344 else if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
11346 mips_add_cfa_restore (mips_subword (reg, true));
11347 mips_add_cfa_restore (mips_subword (reg, false));
11350 mips_add_cfa_restore (reg);
11352 mips_emit_save_slot_move (reg, mem, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
11353 if (REGNO (reg) == REGNO (mips_epilogue.cfa_reg))
11354 /* The CFA is currently defined in terms of the register whose
11355 value we have just restored. Redefine the CFA in terms of
11356 the stack pointer. */
11357 mips_epilogue_set_cfa (stack_pointer_rtx,
11358 mips_epilogue.cfa_restore_sp_offset);
11361 /* Emit code to set the stack pointer to BASE + OFFSET, given that
11362 BASE + OFFSET is NEW_FRAME_SIZE bytes below the top of the frame.
11363 BASE, if not the stack pointer, is available as a temporary. */
11366 mips_deallocate_stack (rtx base, rtx offset, HOST_WIDE_INT new_frame_size)
11368 if (base == stack_pointer_rtx && offset == const0_rtx)
11371 mips_frame_barrier ();
11372 if (offset == const0_rtx)
11374 emit_move_insn (stack_pointer_rtx, base);
11375 mips_epilogue_set_cfa (stack_pointer_rtx, new_frame_size);
11377 else if (TARGET_MIPS16 && base != stack_pointer_rtx)
11379 emit_insn (gen_add3_insn (base, base, offset));
11380 mips_epilogue_set_cfa (base, new_frame_size);
11381 emit_move_insn (stack_pointer_rtx, base);
11385 emit_insn (gen_add3_insn (stack_pointer_rtx, base, offset));
11386 mips_epilogue_set_cfa (stack_pointer_rtx, new_frame_size);
11390 /* Emit any instructions needed before a return. */
11393 mips_expand_before_return (void)
11395 /* When using a call-clobbered gp, we start out with unified call
11396 insns that include instructions to restore the gp. We then split
11397 these unified calls after reload. These split calls explicitly
11398 clobber gp, so there is no need to define
11399 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
11401 For consistency, we should also insert an explicit clobber of $28
11402 before return insns, so that the post-reload optimizers know that
11403 the register is not live on exit. */
11404 if (TARGET_CALL_CLOBBERED_GP)
11405 emit_clobber (pic_offset_table_rtx);
11408 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
11412 mips_expand_epilogue (bool sibcall_p)
11414 const struct mips_frame_info *frame;
11415 HOST_WIDE_INT step1, step2;
11416 rtx base, adjust, insn;
11418 if (!sibcall_p && mips_can_use_return_insn ())
11420 emit_jump_insn (gen_return ());
11424 /* In MIPS16 mode, if the return value should go into a floating-point
11425 register, we need to call a helper routine to copy it over. */
11426 if (mips16_cfun_returns_in_fpr_p ())
11427 mips16_copy_fpr_return_value ();
11429 /* Split the frame into two. STEP1 is the amount of stack we should
11430 deallocate before restoring the registers. STEP2 is the amount we
11431 should deallocate afterwards.
11433 Start off by assuming that no registers need to be restored. */
11434 frame = &cfun->machine->frame;
11435 step1 = frame->total_size;
11438 /* Work out which register holds the frame address. */
11439 if (!frame_pointer_needed)
11440 base = stack_pointer_rtx;
11443 base = hard_frame_pointer_rtx;
11444 step1 -= frame->hard_frame_pointer_offset;
11446 mips_epilogue.cfa_reg = base;
11447 mips_epilogue.cfa_offset = step1;
11448 mips_epilogue.cfa_restores = NULL_RTX;
11450 /* If we need to restore registers, deallocate as much stack as
11451 possible in the second step without going out of range. */
11452 if ((frame->mask | frame->fmask | frame->acc_mask) != 0
11453 || frame->num_cop0_regs > 0)
11455 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
11459 /* Get an rtx for STEP1 that we can add to BASE. */
11460 adjust = GEN_INT (step1);
11461 if (!SMALL_OPERAND (step1))
11463 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), adjust);
11464 adjust = MIPS_EPILOGUE_TEMP (Pmode);
11466 mips_deallocate_stack (base, adjust, step2);
11468 /* If we're using addressing macros, $gp is implicitly used by all
11469 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
11471 if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS)
11472 emit_insn (gen_blockage ());
11474 mips_epilogue.cfa_restore_sp_offset = step2;
11475 if (GENERATE_MIPS16E_SAVE_RESTORE && frame->mask != 0)
11477 unsigned int regno, mask;
11478 HOST_WIDE_INT offset;
11481 /* Generate the restore instruction. */
11482 mask = frame->mask;
11483 restore = mips16e_build_save_restore (true, &mask, &offset, 0, step2);
11485 /* Restore any other registers manually. */
11486 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
11487 if (BITSET_P (mask, regno - GP_REG_FIRST))
11489 offset -= UNITS_PER_WORD;
11490 mips_save_restore_reg (word_mode, regno, offset, mips_restore_reg);
11493 /* Restore the remaining registers and deallocate the final bit
11495 mips_frame_barrier ();
11496 emit_insn (restore);
11497 mips_epilogue_set_cfa (stack_pointer_rtx, 0);
11501 /* Restore the registers. */
11502 mips_for_each_saved_acc (frame->total_size - step2, mips_restore_reg);
11503 mips_for_each_saved_gpr_and_fpr (frame->total_size - step2,
11506 if (cfun->machine->interrupt_handler_p)
11508 HOST_WIDE_INT offset;
11511 offset = frame->cop0_sp_offset - (frame->total_size - step2);
11512 if (!cfun->machine->keep_interrupts_masked_p)
11514 /* Restore the original EPC. */
11515 mem = gen_frame_mem (word_mode,
11516 plus_constant (Pmode, stack_pointer_rtx,
11518 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
11519 offset -= UNITS_PER_WORD;
11521 /* Move to COP0 EPC. */
11522 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_EPC_REG_NUM),
11523 gen_rtx_REG (SImode, K0_REG_NUM)));
11526 /* Restore the original Status. */
11527 mem = gen_frame_mem (word_mode,
11528 plus_constant (Pmode, stack_pointer_rtx,
11530 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
11531 offset -= UNITS_PER_WORD;
11533 /* If we don't use shadow register set, we need to update SP. */
11534 if (!cfun->machine->use_shadow_register_set_p)
11535 mips_deallocate_stack (stack_pointer_rtx, GEN_INT (step2), 0);
11537 /* The choice of position is somewhat arbitrary in this case. */
11538 mips_epilogue_emit_cfa_restores ();
11540 /* Move to COP0 Status. */
11541 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
11542 gen_rtx_REG (SImode, K0_REG_NUM)));
11545 /* Deallocate the final bit of the frame. */
11546 mips_deallocate_stack (stack_pointer_rtx, GEN_INT (step2), 0);
11549 gcc_assert (!mips_epilogue.cfa_restores);
11551 /* Add in the __builtin_eh_return stack adjustment. We need to
11552 use a temporary in MIPS16 code. */
11553 if (crtl->calls_eh_return)
11557 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
11558 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
11559 MIPS_EPILOGUE_TEMP (Pmode),
11560 EH_RETURN_STACKADJ_RTX));
11561 mips_emit_move (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
11564 emit_insn (gen_add3_insn (stack_pointer_rtx,
11566 EH_RETURN_STACKADJ_RTX));
11571 mips_expand_before_return ();
11572 if (cfun->machine->interrupt_handler_p)
11574 /* Interrupt handlers generate eret or deret. */
11575 if (cfun->machine->use_debug_exception_return_p)
11576 emit_jump_insn (gen_mips_deret ());
11578 emit_jump_insn (gen_mips_eret ());
11584 /* When generating MIPS16 code, the normal
11585 mips_for_each_saved_gpr_and_fpr path will restore the return
11586 address into $7 rather than $31. */
11588 && !GENERATE_MIPS16E_SAVE_RESTORE
11589 && BITSET_P (frame->mask, RETURN_ADDR_REGNUM))
11591 /* simple_returns cannot rely on values that are only available
11592 on paths through the epilogue (because return paths that do
11593 not pass through the epilogue may nevertheless reuse a
11594 simple_return that occurs at the end of the epilogue).
11595 Use a normal return here instead. */
11596 rtx reg = gen_rtx_REG (Pmode, GP_REG_FIRST + 7);
11597 pat = gen_return_internal (reg);
11601 rtx reg = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
11602 pat = gen_simple_return_internal (reg);
11604 emit_jump_insn (pat);
11608 /* Search from the beginning to the first use of K0 or K1. */
11609 if (cfun->machine->interrupt_handler_p
11610 && !cfun->machine->keep_interrupts_masked_p)
11612 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
11614 && for_each_rtx (&PATTERN(insn), mips_kernel_reg_p, NULL))
11616 gcc_assert (insn != NULL_RTX);
11617 /* Insert disable interrupts before the first use of K0 or K1. */
11618 emit_insn_before (gen_mips_di (), insn);
11619 emit_insn_before (gen_mips_ehb (), insn);
11623 /* Return nonzero if this function is known to have a null epilogue.
11624 This allows the optimizer to omit jumps to jumps if no stack
11628 mips_can_use_return_insn (void)
11630 /* Interrupt handlers need to go through the epilogue. */
11631 if (cfun->machine->interrupt_handler_p)
11634 if (!reload_completed)
11640 /* In MIPS16 mode, a function that returns a floating-point value
11641 needs to arrange to copy the return value into the floating-point
11643 if (mips16_cfun_returns_in_fpr_p ())
11646 return cfun->machine->frame.total_size == 0;
11649 /* Return true if register REGNO can store a value of mode MODE.
11650 The result of this function is cached in mips_hard_regno_mode_ok. */
11653 mips_hard_regno_mode_ok_p (unsigned int regno, enum machine_mode mode)
11656 enum mode_class mclass;
11658 if (mode == CCV2mode)
11659 return (ISA_HAS_8CC
11660 && ST_REG_P (regno)
11661 && (regno - ST_REG_FIRST) % 2 == 0);
11663 if (mode == CCV4mode)
11664 return (ISA_HAS_8CC
11665 && ST_REG_P (regno)
11666 && (regno - ST_REG_FIRST) % 4 == 0);
11668 if (mode == CCmode)
11669 return ISA_HAS_8CC ? ST_REG_P (regno) : regno == FPSW_REGNUM;
11671 size = GET_MODE_SIZE (mode);
11672 mclass = GET_MODE_CLASS (mode);
11674 if (GP_REG_P (regno))
11675 return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD;
11677 if (FP_REG_P (regno)
11678 && (((regno - FP_REG_FIRST) % MAX_FPRS_PER_FMT) == 0
11679 || (MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG)))
11681 /* Allow 64-bit vector modes for Loongson-2E/2F. */
11682 if (TARGET_LOONGSON_VECTORS
11683 && (mode == V2SImode
11684 || mode == V4HImode
11685 || mode == V8QImode
11686 || mode == DImode))
11689 if (mclass == MODE_FLOAT
11690 || mclass == MODE_COMPLEX_FLOAT
11691 || mclass == MODE_VECTOR_FLOAT)
11692 return size <= UNITS_PER_FPVALUE;
11694 /* Allow integer modes that fit into a single register. We need
11695 to put integers into FPRs when using instructions like CVT
11696 and TRUNC. There's no point allowing sizes smaller than a word,
11697 because the FPU has no appropriate load/store instructions. */
11698 if (mclass == MODE_INT)
11699 return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG;
11702 if (ACC_REG_P (regno)
11703 && (INTEGRAL_MODE_P (mode) || ALL_FIXED_POINT_MODE_P (mode)))
11705 if (MD_REG_P (regno))
11707 /* After a multiplication or division, clobbering HI makes
11708 the value of LO unpredictable, and vice versa. This means
11709 that, for all interesting cases, HI and LO are effectively
11712 We model this by requiring that any value that uses HI
11714 if (size <= UNITS_PER_WORD * 2)
11715 return regno == (size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST);
11719 /* DSP accumulators do not have the same restrictions as
11720 HI and LO, so we can treat them as normal doubleword
11722 if (size <= UNITS_PER_WORD)
11725 if (size <= UNITS_PER_WORD * 2
11726 && ((regno - DSP_ACC_REG_FIRST) & 1) == 0)
11731 if (ALL_COP_REG_P (regno))
11732 return mclass == MODE_INT && size <= UNITS_PER_WORD;
11734 if (regno == GOT_VERSION_REGNUM)
11735 return mode == SImode;
11740 /* Implement HARD_REGNO_NREGS. */
11743 mips_hard_regno_nregs (int regno, enum machine_mode mode)
11745 if (ST_REG_P (regno))
11746 /* The size of FP status registers is always 4, because they only hold
11747 CCmode values, and CCmode is always considered to be 4 bytes wide. */
11748 return (GET_MODE_SIZE (mode) + 3) / 4;
11750 if (FP_REG_P (regno))
11751 return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG;
11753 /* All other registers are word-sized. */
11754 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
11757 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
11758 in mips_hard_regno_nregs. */
11761 mips_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
11767 COPY_HARD_REG_SET (left, reg_class_contents[(int) rclass]);
11768 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS]))
11770 if (HARD_REGNO_MODE_OK (ST_REG_FIRST, mode))
11771 size = MIN (size, 4);
11772 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) ST_REGS]);
11774 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS]))
11776 if (HARD_REGNO_MODE_OK (FP_REG_FIRST, mode))
11777 size = MIN (size, UNITS_PER_FPREG);
11778 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]);
11780 if (!hard_reg_set_empty_p (left))
11781 size = MIN (size, UNITS_PER_WORD);
11782 return (GET_MODE_SIZE (mode) + size - 1) / size;
11785 /* Implement CANNOT_CHANGE_MODE_CLASS. */
11788 mips_cannot_change_mode_class (enum machine_mode from,
11789 enum machine_mode to,
11790 enum reg_class rclass)
11792 /* Allow conversions between different Loongson integer vectors,
11793 and between those vectors and DImode. */
11794 if (GET_MODE_SIZE (from) == 8 && GET_MODE_SIZE (to) == 8
11795 && INTEGRAL_MODE_P (from) && INTEGRAL_MODE_P (to))
11798 /* Otherwise, there are several problems with changing the modes of
11799 values in floating-point registers:
11801 - When a multi-word value is stored in paired floating-point
11802 registers, the first register always holds the low word. We
11803 therefore can't allow FPRs to change between single-word and
11804 multi-word modes on big-endian targets.
11806 - GCC assumes that each word of a multiword register can be
11807 accessed individually using SUBREGs. This is not true for
11808 floating-point registers if they are bigger than a word.
11810 - Loading a 32-bit value into a 64-bit floating-point register
11811 will not sign-extend the value, despite what LOAD_EXTEND_OP
11812 says. We can't allow FPRs to change from SImode to a wider
11813 mode on 64-bit targets.
11815 - If the FPU has already interpreted a value in one format, we
11816 must not ask it to treat the value as having a different
11819 We therefore disallow all mode changes involving FPRs. */
11821 return reg_classes_intersect_p (FP_REGS, rclass);
11824 /* Implement target hook small_register_classes_for_mode_p. */
11827 mips_small_register_classes_for_mode_p (enum machine_mode mode
11830 return TARGET_MIPS16;
11833 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
11836 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode)
11841 return TARGET_HARD_FLOAT;
11844 return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT;
11847 return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT;
11854 /* Implement MODES_TIEABLE_P. */
11857 mips_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
11859 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
11860 prefer to put one of them in FPRs. */
11861 return (mode1 == mode2
11862 || (!mips_mode_ok_for_mov_fmt_p (mode1)
11863 && !mips_mode_ok_for_mov_fmt_p (mode2)));
11866 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
11869 mips_preferred_reload_class (rtx x, reg_class_t rclass)
11871 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, rclass))
11874 if (reg_class_subset_p (FP_REGS, rclass)
11875 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x)))
11878 if (reg_class_subset_p (GR_REGS, rclass))
11881 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, rclass))
11887 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
11888 Return a "canonical" class to represent it in later calculations. */
11891 mips_canonicalize_move_class (reg_class_t rclass)
11893 /* All moves involving accumulator registers have the same cost. */
11894 if (reg_class_subset_p (rclass, ACC_REGS))
11897 /* Likewise promote subclasses of general registers to the most
11898 interesting containing class. */
11899 if (TARGET_MIPS16 && reg_class_subset_p (rclass, M16_REGS))
11901 else if (reg_class_subset_p (rclass, GENERAL_REGS))
11902 rclass = GENERAL_REGS;
11907 /* Return the cost of moving a value of mode MODE from a register of
11908 class FROM to a GPR. Return 0 for classes that are unions of other
11909 classes handled by this function. */
11912 mips_move_to_gpr_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
11918 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
11922 /* MFLO and MFHI. */
11930 /* LUI followed by MOVF. */
11936 /* This choice of value is historical. */
11944 /* Return the cost of moving a value of mode MODE from a GPR to a
11945 register of class TO. Return 0 for classes that are unions of
11946 other classes handled by this function. */
11949 mips_move_from_gpr_cost (enum machine_mode mode, reg_class_t to)
11954 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
11958 /* MTLO and MTHI. */
11966 /* A secondary reload through an FPR scratch. */
11967 return (mips_register_move_cost (mode, GENERAL_REGS, FP_REGS)
11968 + mips_register_move_cost (mode, FP_REGS, ST_REGS));
11973 /* This choice of value is historical. */
11981 /* Implement TARGET_REGISTER_MOVE_COST. Return 0 for classes that are the
11982 maximum of the move costs for subclasses; regclass will work out
11983 the maximum for us. */
11986 mips_register_move_cost (enum machine_mode mode,
11987 reg_class_t from, reg_class_t to)
11992 from = mips_canonicalize_move_class (from);
11993 to = mips_canonicalize_move_class (to);
11995 /* Handle moves that can be done without using general-purpose registers. */
11996 if (from == FP_REGS)
11998 if (to == FP_REGS && mips_mode_ok_for_mov_fmt_p (mode))
12002 /* The sequence generated by mips_expand_fcc_reload. */
12006 /* Handle cases in which only one class deviates from the ideal. */
12007 dregs = TARGET_MIPS16 ? M16_REGS : GENERAL_REGS;
12009 return mips_move_from_gpr_cost (mode, to);
12011 return mips_move_to_gpr_cost (mode, from);
12013 /* Handles cases that require a GPR temporary. */
12014 cost1 = mips_move_to_gpr_cost (mode, from);
12017 cost2 = mips_move_from_gpr_cost (mode, to);
12019 return cost1 + cost2;
12025 /* Implement TARGET_MEMORY_MOVE_COST. */
12028 mips_memory_move_cost (enum machine_mode mode, reg_class_t rclass, bool in)
12030 return (mips_cost->memory_latency
12031 + memory_move_secondary_cost (mode, rclass, in));
12034 /* Return the register class required for a secondary register when
12035 copying between one of the registers in RCLASS and value X, which
12036 has mode MODE. X is the source of the move if IN_P, otherwise it
12037 is the destination. Return NO_REGS if no secondary register is
12041 mips_secondary_reload_class (enum reg_class rclass,
12042 enum machine_mode mode, rtx x, bool in_p)
12046 /* If X is a constant that cannot be loaded into $25, it must be loaded
12047 into some other GPR. No other register class allows a direct move. */
12048 if (mips_dangerous_for_la25_p (x))
12049 return reg_class_subset_p (rclass, LEA_REGS) ? NO_REGS : LEA_REGS;
12051 regno = true_regnum (x);
12054 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
12055 if (!reg_class_subset_p (rclass, M16_REGS) && !M16_REG_P (regno))
12061 /* Copying from accumulator registers to anywhere other than a general
12062 register requires a temporary general register. */
12063 if (reg_class_subset_p (rclass, ACC_REGS))
12064 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
12065 if (ACC_REG_P (regno))
12066 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
12068 /* We can only copy a value to a condition code register from a
12069 floating-point register, and even then we require a scratch
12070 floating-point register. We can only copy a value out of a
12071 condition-code register into a general register. */
12072 if (reg_class_subset_p (rclass, ST_REGS))
12076 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
12078 if (ST_REG_P (regno))
12082 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
12085 if (reg_class_subset_p (rclass, FP_REGS))
12088 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8))
12089 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
12090 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
12093 if (GP_REG_P (regno) || x == CONST0_RTX (mode))
12094 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
12097 if (CONSTANT_P (x) && !targetm.cannot_force_const_mem (mode, x))
12098 /* We can force the constant to memory and use lwc1
12099 and ldc1. As above, we will use pairs of lwc1s if
12100 ldc1 is not supported. */
12103 if (FP_REG_P (regno) && mips_mode_ok_for_mov_fmt_p (mode))
12104 /* In this case we can use mov.fmt. */
12107 /* Otherwise, we need to reload through an integer register. */
12110 if (FP_REG_P (regno))
12111 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
12116 /* Implement TARGET_MODE_REP_EXTENDED. */
12119 mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
12121 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
12122 if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
12123 return SIGN_EXTEND;
12128 /* Implement TARGET_VALID_POINTER_MODE. */
12131 mips_valid_pointer_mode (enum machine_mode mode)
12133 return mode == SImode || (TARGET_64BIT && mode == DImode);
12136 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
12139 mips_vector_mode_supported_p (enum machine_mode mode)
12144 return TARGET_PAIRED_SINGLE_FLOAT;
12159 return TARGET_LOONGSON_VECTORS;
12166 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
12169 mips_scalar_mode_supported_p (enum machine_mode mode)
12171 if (ALL_FIXED_POINT_MODE_P (mode)
12172 && GET_MODE_PRECISION (mode) <= 2 * BITS_PER_WORD)
12175 return default_scalar_mode_supported_p (mode);
12178 /* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
12180 static enum machine_mode
12181 mips_preferred_simd_mode (enum machine_mode mode ATTRIBUTE_UNUSED)
12183 if (TARGET_PAIRED_SINGLE_FLOAT
12189 /* Implement TARGET_INIT_LIBFUNCS. */
12192 mips_init_libfuncs (void)
12194 if (TARGET_FIX_VR4120)
12196 /* Register the special divsi3 and modsi3 functions needed to work
12197 around VR4120 division errata. */
12198 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
12199 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
12202 if (TARGET_MIPS16 && TARGET_HARD_FLOAT_ABI)
12204 /* Register the MIPS16 -mhard-float stubs. */
12205 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
12206 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
12207 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
12208 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
12210 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
12211 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
12212 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
12213 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
12214 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
12215 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
12216 set_optab_libfunc (unord_optab, SFmode, "__mips16_unordsf2");
12218 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
12219 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
12220 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__mips16_floatunsisf");
12222 if (TARGET_DOUBLE_FLOAT)
12224 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
12225 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
12226 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
12227 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
12229 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
12230 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
12231 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
12232 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
12233 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
12234 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
12235 set_optab_libfunc (unord_optab, DFmode, "__mips16_unorddf2");
12237 set_conv_libfunc (sext_optab, DFmode, SFmode,
12238 "__mips16_extendsfdf2");
12239 set_conv_libfunc (trunc_optab, SFmode, DFmode,
12240 "__mips16_truncdfsf2");
12241 set_conv_libfunc (sfix_optab, SImode, DFmode,
12242 "__mips16_fix_truncdfsi");
12243 set_conv_libfunc (sfloat_optab, DFmode, SImode,
12244 "__mips16_floatsidf");
12245 set_conv_libfunc (ufloat_optab, DFmode, SImode,
12246 "__mips16_floatunsidf");
12250 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
12251 on an external non-MIPS16 routine to implement __sync_synchronize.
12252 Similarly for the rest of the ll/sc libfuncs. */
12255 synchronize_libfunc = init_one_libfunc ("__sync_synchronize");
12256 init_sync_libfuncs (UNITS_PER_WORD);
12260 /* Build up a multi-insn sequence that loads label TARGET into $AT. */
12263 mips_process_load_label (rtx target)
12265 rtx base, gp, intop;
12266 HOST_WIDE_INT offset;
12268 mips_multi_start ();
12272 mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target, 0);
12273 mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target, 0);
12277 mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target, 0);
12278 mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target, 0);
12282 gp = pic_offset_table_rtx;
12283 if (mips_cfun_has_cprestore_slot_p ())
12285 gp = gen_rtx_REG (Pmode, AT_REGNUM);
12286 mips_get_cprestore_base_and_offset (&base, &offset, true);
12287 if (!SMALL_OPERAND (offset))
12289 intop = GEN_INT (CONST_HIGH_PART (offset));
12290 mips_multi_add_insn ("lui\t%0,%1", gp, intop, 0);
12291 mips_multi_add_insn ("addu\t%0,%0,%1", gp, base, 0);
12294 offset = CONST_LOW_PART (offset);
12296 intop = GEN_INT (offset);
12297 if (ISA_HAS_LOAD_DELAY)
12298 mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp, intop, base, 0);
12300 mips_multi_add_insn ("lw\t%0,%1(%2)", gp, intop, base, 0);
12302 if (ISA_HAS_LOAD_DELAY)
12303 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target, gp, 0);
12305 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target, gp, 0);
12306 mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target, 0);
12311 /* Return the number of instructions needed to load a label into $AT. */
12313 static unsigned int
12314 mips_load_label_num_insns (void)
12316 if (cfun->machine->load_label_num_insns == 0)
12318 mips_process_load_label (pc_rtx);
12319 cfun->machine->load_label_num_insns = mips_multi_num_insns;
12321 return cfun->machine->load_label_num_insns;
12324 /* Emit an asm sequence to start a noat block and load the address
12325 of a label into $1. */
12328 mips_output_load_label (rtx target)
12330 mips_push_asm_switch (&mips_noat);
12331 if (TARGET_EXPLICIT_RELOCS)
12333 mips_process_load_label (target);
12334 mips_multi_write ();
12338 if (Pmode == DImode)
12339 output_asm_insn ("dla\t%@,%0", &target);
12341 output_asm_insn ("la\t%@,%0", &target);
12345 /* Return the length of INSN. LENGTH is the initial length computed by
12346 attributes in the machine-description file. */
12349 mips_adjust_insn_length (rtx insn, int length)
12351 /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length
12352 of a PIC long-branch sequence. Substitute the correct value. */
12353 if (length == MAX_PIC_BRANCH_LENGTH
12354 && INSN_CODE (insn) >= 0
12355 && get_attr_type (insn) == TYPE_BRANCH)
12357 /* Add the branch-over instruction and its delay slot, if this
12358 is a conditional branch. */
12359 length = simplejump_p (insn) ? 0 : 8;
12361 /* Load the label into $AT and jump to it. Ignore the delay
12362 slot of the jump. */
12363 length += 4 * mips_load_label_num_insns() + 4;
12366 /* A unconditional jump has an unfilled delay slot if it is not part
12367 of a sequence. A conditional jump normally has a delay slot, but
12368 does not on MIPS16. */
12369 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
12372 /* See how many nops might be needed to avoid hardware hazards. */
12373 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
12374 switch (get_attr_hazard (insn))
12388 /* In order to make it easier to share MIPS16 and non-MIPS16 patterns,
12389 the .md file length attributes are 4-based for both modes.
12390 Adjust the MIPS16 ones here. */
12397 /* Return the assembly code for INSN, which has the operands given by
12398 OPERANDS, and which branches to OPERANDS[0] if some condition is true.
12399 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0]
12400 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
12401 version of BRANCH_IF_TRUE. */
12404 mips_output_conditional_branch (rtx insn, rtx *operands,
12405 const char *branch_if_true,
12406 const char *branch_if_false)
12408 unsigned int length;
12409 rtx taken, not_taken;
12411 gcc_assert (LABEL_P (operands[0]));
12413 length = get_attr_length (insn);
12416 /* Just a simple conditional branch. */
12417 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
12418 return branch_if_true;
12421 /* Generate a reversed branch around a direct jump. This fallback does
12422 not use branch-likely instructions. */
12423 mips_branch_likely = false;
12424 not_taken = gen_label_rtx ();
12425 taken = operands[0];
12427 /* Generate the reversed branch to NOT_TAKEN. */
12428 operands[0] = not_taken;
12429 output_asm_insn (branch_if_false, operands);
12431 /* If INSN has a delay slot, we must provide delay slots for both the
12432 branch to NOT_TAKEN and the conditional jump. We must also ensure
12433 that INSN's delay slot is executed in the appropriate cases. */
12434 if (final_sequence)
12436 /* This first delay slot will always be executed, so use INSN's
12437 delay slot if is not annulled. */
12438 if (!INSN_ANNULLED_BRANCH_P (insn))
12440 final_scan_insn (XVECEXP (final_sequence, 0, 1),
12441 asm_out_file, optimize, 1, NULL);
12442 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
12445 output_asm_insn ("nop", 0);
12446 fprintf (asm_out_file, "\n");
12449 /* Output the unconditional branch to TAKEN. */
12450 if (TARGET_ABSOLUTE_JUMPS)
12451 output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken);
12454 mips_output_load_label (taken);
12455 output_asm_insn ("jr\t%@%]%/", 0);
12458 /* Now deal with its delay slot; see above. */
12459 if (final_sequence)
12461 /* This delay slot will only be executed if the branch is taken.
12462 Use INSN's delay slot if is annulled. */
12463 if (INSN_ANNULLED_BRANCH_P (insn))
12465 final_scan_insn (XVECEXP (final_sequence, 0, 1),
12466 asm_out_file, optimize, 1, NULL);
12467 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
12470 output_asm_insn ("nop", 0);
12471 fprintf (asm_out_file, "\n");
12474 /* Output NOT_TAKEN. */
12475 targetm.asm_out.internal_label (asm_out_file, "L",
12476 CODE_LABEL_NUMBER (not_taken));
12480 /* Return the assembly code for INSN, which branches to OPERANDS[0]
12481 if some ordering condition is true. The condition is given by
12482 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
12483 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
12484 its second is always zero. */
12487 mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
12489 const char *branch[2];
12491 /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true.
12492 Make BRANCH[0] branch on the inverse condition. */
12493 switch (GET_CODE (operands[1]))
12495 /* These cases are equivalent to comparisons against zero. */
12497 inverted_p = !inverted_p;
12498 /* Fall through. */
12500 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%0");
12501 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%0");
12504 /* These cases are always true or always false. */
12506 inverted_p = !inverted_p;
12507 /* Fall through. */
12509 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%0");
12510 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%0");
12514 branch[!inverted_p] = MIPS_BRANCH ("b%C1z", "%2,%0");
12515 branch[inverted_p] = MIPS_BRANCH ("b%N1z", "%2,%0");
12518 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
12521 /* Start a block of code that needs access to the LL, SC and SYNC
12525 mips_start_ll_sc_sync_block (void)
12527 if (!ISA_HAS_LL_SC)
12529 output_asm_insn (".set\tpush", 0);
12530 output_asm_insn (".set\tmips2", 0);
12534 /* End a block started by mips_start_ll_sc_sync_block. */
12537 mips_end_ll_sc_sync_block (void)
12539 if (!ISA_HAS_LL_SC)
12540 output_asm_insn (".set\tpop", 0);
12543 /* Output and/or return the asm template for a sync instruction. */
12546 mips_output_sync (void)
12548 mips_start_ll_sc_sync_block ();
12549 output_asm_insn ("sync", 0);
12550 mips_end_ll_sc_sync_block ();
12554 /* Return the asm template associated with sync_insn1 value TYPE.
12555 IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */
12557 static const char *
12558 mips_sync_insn1_template (enum attr_sync_insn1 type, bool is_64bit_p)
12562 case SYNC_INSN1_MOVE:
12563 return "move\t%0,%z2";
12564 case SYNC_INSN1_LI:
12565 return "li\t%0,%2";
12566 case SYNC_INSN1_ADDU:
12567 return is_64bit_p ? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2";
12568 case SYNC_INSN1_ADDIU:
12569 return is_64bit_p ? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2";
12570 case SYNC_INSN1_SUBU:
12571 return is_64bit_p ? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2";
12572 case SYNC_INSN1_AND:
12573 return "and\t%0,%1,%z2";
12574 case SYNC_INSN1_ANDI:
12575 return "andi\t%0,%1,%2";
12576 case SYNC_INSN1_OR:
12577 return "or\t%0,%1,%z2";
12578 case SYNC_INSN1_ORI:
12579 return "ori\t%0,%1,%2";
12580 case SYNC_INSN1_XOR:
12581 return "xor\t%0,%1,%z2";
12582 case SYNC_INSN1_XORI:
12583 return "xori\t%0,%1,%2";
12585 gcc_unreachable ();
12588 /* Return the asm template associated with sync_insn2 value TYPE. */
12590 static const char *
12591 mips_sync_insn2_template (enum attr_sync_insn2 type)
12595 case SYNC_INSN2_NOP:
12596 gcc_unreachable ();
12597 case SYNC_INSN2_AND:
12598 return "and\t%0,%1,%z2";
12599 case SYNC_INSN2_XOR:
12600 return "xor\t%0,%1,%z2";
12601 case SYNC_INSN2_NOT:
12602 return "nor\t%0,%1,%.";
12604 gcc_unreachable ();
12607 /* OPERANDS are the operands to a sync loop instruction and INDEX is
12608 the value of the one of the sync_* attributes. Return the operand
12609 referred to by the attribute, or DEFAULT_VALUE if the insn doesn't
12610 have the associated attribute. */
12613 mips_get_sync_operand (rtx *operands, int index, rtx default_value)
12616 default_value = operands[index - 1];
12617 return default_value;
12620 /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn
12621 sequence for it. */
12624 mips_process_sync_loop (rtx insn, rtx *operands)
12626 rtx at, mem, oldval, newval, inclusive_mask, exclusive_mask;
12627 rtx required_oldval, insn1_op2, tmp1, tmp2, tmp3, cmp;
12628 unsigned int tmp3_insn;
12629 enum attr_sync_insn1 insn1;
12630 enum attr_sync_insn2 insn2;
12633 enum memmodel model;
12635 /* Read an operand from the sync_WHAT attribute and store it in
12636 variable WHAT. DEFAULT is the default value if no attribute
12638 #define READ_OPERAND(WHAT, DEFAULT) \
12639 WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \
12642 /* Read the memory. */
12643 READ_OPERAND (mem, 0);
12645 is_64bit_p = (GET_MODE_BITSIZE (GET_MODE (mem)) == 64);
12647 /* Read the other attributes. */
12648 at = gen_rtx_REG (GET_MODE (mem), AT_REGNUM);
12649 READ_OPERAND (oldval, at);
12650 READ_OPERAND (cmp, 0);
12651 READ_OPERAND (newval, at);
12652 READ_OPERAND (inclusive_mask, 0);
12653 READ_OPERAND (exclusive_mask, 0);
12654 READ_OPERAND (required_oldval, 0);
12655 READ_OPERAND (insn1_op2, 0);
12656 insn1 = get_attr_sync_insn1 (insn);
12657 insn2 = get_attr_sync_insn2 (insn);
12659 /* Don't bother setting CMP result that is never used. */
12660 if (cmp && find_reg_note (insn, REG_UNUSED, cmp))
12663 memmodel_attr = get_attr_sync_memmodel (insn);
12664 switch (memmodel_attr)
12667 model = MEMMODEL_ACQ_REL;
12670 model = MEMMODEL_ACQUIRE;
12673 model = (enum memmodel) INTVAL (operands[memmodel_attr]);
12676 mips_multi_start ();
12678 /* Output the release side of the memory barrier. */
12679 if (need_atomic_barrier_p (model, true))
12681 if (required_oldval == 0 && TARGET_OCTEON)
12683 /* Octeon doesn't reorder reads, so a full barrier can be
12684 created by using SYNCW to order writes combined with the
12685 write from the following SC. When the SC successfully
12686 completes, we know that all preceding writes are also
12687 committed to the coherent memory system. It is possible
12688 for a single SYNCW to fail, but a pair of them will never
12689 fail, so we use two. */
12690 mips_multi_add_insn ("syncw", NULL);
12691 mips_multi_add_insn ("syncw", NULL);
12694 mips_multi_add_insn ("sync", NULL);
12697 /* Output the branch-back label. */
12698 mips_multi_add_label ("1:");
12700 /* OLDVAL = *MEM. */
12701 mips_multi_add_insn (is_64bit_p ? "lld\t%0,%1" : "ll\t%0,%1",
12702 oldval, mem, NULL);
12704 /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */
12705 if (required_oldval)
12707 if (inclusive_mask == 0)
12711 gcc_assert (oldval != at);
12712 mips_multi_add_insn ("and\t%0,%1,%2",
12713 at, oldval, inclusive_mask, NULL);
12716 mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1, required_oldval, NULL);
12718 /* CMP = 0 [delay slot]. */
12720 mips_multi_add_insn ("li\t%0,0", cmp, NULL);
12723 /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */
12724 if (exclusive_mask == 0)
12728 gcc_assert (oldval != at);
12729 mips_multi_add_insn ("and\t%0,%1,%z2",
12730 at, oldval, exclusive_mask, NULL);
12734 /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2).
12736 We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit
12737 at least one instruction in that case. */
12738 if (insn1 == SYNC_INSN1_MOVE
12739 && (tmp1 != const0_rtx || insn2 != SYNC_INSN2_NOP))
12743 mips_multi_add_insn (mips_sync_insn1_template (insn1, is_64bit_p),
12744 newval, oldval, insn1_op2, NULL);
12748 /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */
12749 if (insn2 == SYNC_INSN2_NOP)
12753 mips_multi_add_insn (mips_sync_insn2_template (insn2),
12754 newval, tmp2, inclusive_mask, NULL);
12757 tmp3_insn = mips_multi_last_index ();
12759 /* $AT = $TMP1 | $TMP3. */
12760 if (tmp1 == const0_rtx || tmp3 == const0_rtx)
12762 mips_multi_set_operand (tmp3_insn, 0, at);
12767 gcc_assert (tmp1 != tmp3);
12768 mips_multi_add_insn ("or\t%0,%1,%2", at, tmp1, tmp3, NULL);
12771 /* if (!commit (*MEM = $AT)) goto 1.
12773 This will sometimes be a delayed branch; see the write code below
12775 mips_multi_add_insn (is_64bit_p ? "scd\t%0,%1" : "sc\t%0,%1", at, mem, NULL);
12776 mips_multi_add_insn ("beq%?\t%0,%.,1b", at, NULL);
12778 /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */
12779 if (insn1 != SYNC_INSN1_MOVE && insn1 != SYNC_INSN1_LI && tmp3 != newval)
12781 mips_multi_copy_insn (tmp3_insn);
12782 mips_multi_set_operand (mips_multi_last_index (), 0, newval);
12784 else if (!(required_oldval && cmp))
12785 mips_multi_add_insn ("nop", NULL);
12787 /* CMP = 1 -- either standalone or in a delay slot. */
12788 if (required_oldval && cmp)
12789 mips_multi_add_insn ("li\t%0,1", cmp, NULL);
12791 /* Output the acquire side of the memory barrier. */
12792 if (TARGET_SYNC_AFTER_SC && need_atomic_barrier_p (model, false))
12793 mips_multi_add_insn ("sync", NULL);
12795 /* Output the exit label, if needed. */
12796 if (required_oldval)
12797 mips_multi_add_label ("2:");
12799 #undef READ_OPERAND
12802 /* Output and/or return the asm template for sync loop INSN, which has
12803 the operands given by OPERANDS. */
12806 mips_output_sync_loop (rtx insn, rtx *operands)
12808 mips_process_sync_loop (insn, operands);
12810 /* Use branch-likely instructions to work around the LL/SC R10000
12812 mips_branch_likely = TARGET_FIX_R10000;
12814 mips_push_asm_switch (&mips_noreorder);
12815 mips_push_asm_switch (&mips_nomacro);
12816 mips_push_asm_switch (&mips_noat);
12817 mips_start_ll_sc_sync_block ();
12819 mips_multi_write ();
12821 mips_end_ll_sc_sync_block ();
12822 mips_pop_asm_switch (&mips_noat);
12823 mips_pop_asm_switch (&mips_nomacro);
12824 mips_pop_asm_switch (&mips_noreorder);
12829 /* Return the number of individual instructions in sync loop INSN,
12830 which has the operands given by OPERANDS. */
12833 mips_sync_loop_insns (rtx insn, rtx *operands)
12835 mips_process_sync_loop (insn, operands);
12836 return mips_multi_num_insns;
12839 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
12840 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
12842 When working around R4000 and R4400 errata, we need to make sure that
12843 the division is not immediately followed by a shift[1][2]. We also
12844 need to stop the division from being put into a branch delay slot[3].
12845 The easiest way to avoid both problems is to add a nop after the
12846 division. When a divide-by-zero check is needed, this nop can be
12847 used to fill the branch delay slot.
12849 [1] If a double-word or a variable shift executes immediately
12850 after starting an integer division, the shift may give an
12851 incorrect result. See quotations of errata #16 and #28 from
12852 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
12853 in mips.md for details.
12855 [2] A similar bug to [1] exists for all revisions of the
12856 R4000 and the R4400 when run in an MC configuration.
12857 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
12859 "19. In this following sequence:
12861 ddiv (or ddivu or div or divu)
12862 dsll32 (or dsrl32, dsra32)
12864 if an MPT stall occurs, while the divide is slipping the cpu
12865 pipeline, then the following double shift would end up with an
12868 Workaround: The compiler needs to avoid generating any
12869 sequence with divide followed by extended double shift."
12871 This erratum is also present in "MIPS R4400MC Errata, Processor
12872 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
12873 & 3.0" as errata #10 and #4, respectively.
12875 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
12876 (also valid for MIPS R4000MC processors):
12878 "52. R4000SC: This bug does not apply for the R4000PC.
12880 There are two flavors of this bug:
12882 1) If the instruction just after divide takes an RF exception
12883 (tlb-refill, tlb-invalid) and gets an instruction cache
12884 miss (both primary and secondary) and the line which is
12885 currently in secondary cache at this index had the first
12886 data word, where the bits 5..2 are set, then R4000 would
12887 get a wrong result for the div.
12892 ------------------- # end-of page. -tlb-refill
12897 ------------------- # end-of page. -tlb-invalid
12900 2) If the divide is in the taken branch delay slot, where the
12901 target takes RF exception and gets an I-cache miss for the
12902 exception vector or where I-cache miss occurs for the
12903 target address, under the above mentioned scenarios, the
12904 div would get wrong results.
12907 j r2 # to next page mapped or unmapped
12908 div r8,r9 # this bug would be there as long
12909 # as there is an ICache miss and
12910 nop # the "data pattern" is present
12913 beq r0, r0, NextPage # to Next page
12917 This bug is present for div, divu, ddiv, and ddivu
12920 Workaround: For item 1), OS could make sure that the next page
12921 after the divide instruction is also mapped. For item 2), the
12922 compiler could make sure that the divide instruction is not in
12923 the branch delay slot."
12925 These processors have PRId values of 0x00004220 and 0x00004300 for
12926 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
12929 mips_output_division (const char *division, rtx *operands)
12934 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
12936 output_asm_insn (s, operands);
12939 if (TARGET_CHECK_ZERO_DIV)
12943 output_asm_insn (s, operands);
12944 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
12946 else if (GENERATE_DIVIDE_TRAPS)
12948 /* Avoid long replay penalty on load miss by putting the trap before
12951 output_asm_insn ("teq\t%2,%.,7", operands);
12954 output_asm_insn (s, operands);
12955 s = "teq\t%2,%.,7";
12960 output_asm_insn ("%(bne\t%2,%.,1f", operands);
12961 output_asm_insn (s, operands);
12962 s = "break\t7%)\n1:";
12968 /* Return true if IN_INSN is a multiply-add or multiply-subtract
12969 instruction and if OUT_INSN assigns to the accumulator operand. */
12972 mips_linked_madd_p (rtx out_insn, rtx in_insn)
12974 enum attr_accum_in accum_in;
12975 int accum_in_opnum;
12978 if (recog_memoized (in_insn) < 0)
12981 accum_in = get_attr_accum_in (in_insn);
12982 if (accum_in == ACCUM_IN_NONE)
12985 accum_in_opnum = accum_in - ACCUM_IN_0;
12987 extract_insn (in_insn);
12988 gcc_assert (accum_in_opnum < recog_data.n_operands);
12989 accum_in_op = recog_data.operand[accum_in_opnum];
12991 return reg_set_p (accum_in_op, out_insn);
12994 /* True if the dependency between OUT_INSN and IN_INSN is on the store
12995 data rather than the address. We need this because the cprestore
12996 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
12997 which causes the default routine to abort. We just return false
13001 mips_store_data_bypass_p (rtx out_insn, rtx in_insn)
13003 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
13006 return !store_data_bypass_p (out_insn, in_insn);
13010 /* Variables and flags used in scheduler hooks when tuning for
13014 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
13017 /* If true, then next ALU1/2 instruction will go to ALU1. */
13020 /* If true, then next FALU1/2 unstruction will go to FALU1. */
13023 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
13024 int alu1_core_unit_code;
13025 int alu2_core_unit_code;
13026 int falu1_core_unit_code;
13027 int falu2_core_unit_code;
13029 /* True if current cycle has a multi instruction.
13030 This flag is used in mips_ls2_dfa_post_advance_cycle. */
13031 bool cycle_has_multi_p;
13033 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
13034 These are used in mips_ls2_dfa_post_advance_cycle to initialize
13036 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
13037 instruction to go ALU1. */
13038 rtx alu1_turn_enabled_insn;
13039 rtx alu2_turn_enabled_insn;
13040 rtx falu1_turn_enabled_insn;
13041 rtx falu2_turn_enabled_insn;
13044 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
13045 dependencies have no cost, except on the 20Kc where output-dependence
13046 is treated like input-dependence. */
13049 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
13050 rtx dep ATTRIBUTE_UNUSED, int cost)
13052 if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT
13055 if (REG_NOTE_KIND (link) != 0)
13060 /* Return the number of instructions that can be issued per cycle. */
13063 mips_issue_rate (void)
13067 case PROCESSOR_74KC:
13068 case PROCESSOR_74KF2_1:
13069 case PROCESSOR_74KF1_1:
13070 case PROCESSOR_74KF3_2:
13071 /* The 74k is not strictly quad-issue cpu, but can be seen as one
13072 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
13073 but in reality only a maximum of 3 insns can be issued as
13074 floating-point loads and stores also require a slot in the
13076 case PROCESSOR_R10000:
13077 /* All R10K Processors are quad-issue (being the first MIPS
13078 processors to support this feature). */
13081 case PROCESSOR_20KC:
13082 case PROCESSOR_R4130:
13083 case PROCESSOR_R5400:
13084 case PROCESSOR_R5500:
13085 case PROCESSOR_R7000:
13086 case PROCESSOR_R9000:
13087 case PROCESSOR_OCTEON:
13088 case PROCESSOR_OCTEON2:
13091 case PROCESSOR_SB1:
13092 case PROCESSOR_SB1A:
13093 /* This is actually 4, but we get better performance if we claim 3.
13094 This is partly because of unwanted speculative code motion with the
13095 larger number, and partly because in most common cases we can't
13096 reach the theoretical max of 4. */
13099 case PROCESSOR_LOONGSON_2E:
13100 case PROCESSOR_LOONGSON_2F:
13101 case PROCESSOR_LOONGSON_3A:
13104 case PROCESSOR_XLP:
13105 return (reload_completed ? 4 : 3);
13112 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
13115 mips_ls2_init_dfa_post_cycle_insn (void)
13118 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
13119 mips_ls2.alu1_turn_enabled_insn = get_insns ();
13123 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
13124 mips_ls2.alu2_turn_enabled_insn = get_insns ();
13128 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
13129 mips_ls2.falu1_turn_enabled_insn = get_insns ();
13133 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
13134 mips_ls2.falu2_turn_enabled_insn = get_insns ();
13137 mips_ls2.alu1_core_unit_code = get_cpu_unit_code ("ls2_alu1_core");
13138 mips_ls2.alu2_core_unit_code = get_cpu_unit_code ("ls2_alu2_core");
13139 mips_ls2.falu1_core_unit_code = get_cpu_unit_code ("ls2_falu1_core");
13140 mips_ls2.falu2_core_unit_code = get_cpu_unit_code ("ls2_falu2_core");
13143 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
13144 Init data used in mips_dfa_post_advance_cycle. */
13147 mips_init_dfa_post_cycle_insn (void)
13149 if (TUNE_LOONGSON_2EF)
13150 mips_ls2_init_dfa_post_cycle_insn ();
13153 /* Initialize STATE when scheduling for Loongson 2E/2F.
13154 Support round-robin dispatch scheme by enabling only one of
13155 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
13159 mips_ls2_dfa_post_advance_cycle (state_t state)
13161 if (cpu_unit_reservation_p (state, mips_ls2.alu1_core_unit_code))
13163 /* Though there are no non-pipelined ALU1 insns,
13164 we can get an instruction of type 'multi' before reload. */
13165 gcc_assert (mips_ls2.cycle_has_multi_p);
13166 mips_ls2.alu1_turn_p = false;
13169 mips_ls2.cycle_has_multi_p = false;
13171 if (cpu_unit_reservation_p (state, mips_ls2.alu2_core_unit_code))
13172 /* We have a non-pipelined alu instruction in the core,
13173 adjust round-robin counter. */
13174 mips_ls2.alu1_turn_p = true;
13176 if (mips_ls2.alu1_turn_p)
13178 if (state_transition (state, mips_ls2.alu1_turn_enabled_insn) >= 0)
13179 gcc_unreachable ();
13183 if (state_transition (state, mips_ls2.alu2_turn_enabled_insn) >= 0)
13184 gcc_unreachable ();
13187 if (cpu_unit_reservation_p (state, mips_ls2.falu1_core_unit_code))
13189 /* There are no non-pipelined FALU1 insns. */
13190 gcc_unreachable ();
13191 mips_ls2.falu1_turn_p = false;
13194 if (cpu_unit_reservation_p (state, mips_ls2.falu2_core_unit_code))
13195 /* We have a non-pipelined falu instruction in the core,
13196 adjust round-robin counter. */
13197 mips_ls2.falu1_turn_p = true;
13199 if (mips_ls2.falu1_turn_p)
13201 if (state_transition (state, mips_ls2.falu1_turn_enabled_insn) >= 0)
13202 gcc_unreachable ();
13206 if (state_transition (state, mips_ls2.falu2_turn_enabled_insn) >= 0)
13207 gcc_unreachable ();
13211 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
13212 This hook is being called at the start of each cycle. */
13215 mips_dfa_post_advance_cycle (void)
13217 if (TUNE_LOONGSON_2EF)
13218 mips_ls2_dfa_post_advance_cycle (curr_state);
13221 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
13222 be as wide as the scheduling freedom in the DFA. */
13225 mips_multipass_dfa_lookahead (void)
13227 /* Can schedule up to 4 of the 6 function units in any one cycle. */
13231 if (TUNE_LOONGSON_2EF || TUNE_LOONGSON_3A)
13240 /* Remove the instruction at index LOWER from ready queue READY and
13241 reinsert it in front of the instruction at index HIGHER. LOWER must
13245 mips_promote_ready (rtx *ready, int lower, int higher)
13250 new_head = ready[lower];
13251 for (i = lower; i < higher; i++)
13252 ready[i] = ready[i + 1];
13253 ready[i] = new_head;
13256 /* If the priority of the instruction at POS2 in the ready queue READY
13257 is within LIMIT units of that of the instruction at POS1, swap the
13258 instructions if POS2 is not already less than POS1. */
13261 mips_maybe_swap_ready (rtx *ready, int pos1, int pos2, int limit)
13264 && INSN_PRIORITY (ready[pos1]) + limit >= INSN_PRIORITY (ready[pos2]))
13268 temp = ready[pos1];
13269 ready[pos1] = ready[pos2];
13270 ready[pos2] = temp;
13274 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
13275 that may clobber hi or lo. */
13276 static rtx mips_macc_chains_last_hilo;
13278 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
13279 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
13282 mips_macc_chains_record (rtx insn)
13284 if (get_attr_may_clobber_hilo (insn))
13285 mips_macc_chains_last_hilo = insn;
13288 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
13289 has NREADY elements, looking for a multiply-add or multiply-subtract
13290 instruction that is cumulative with mips_macc_chains_last_hilo.
13291 If there is one, promote it ahead of anything else that might
13292 clobber hi or lo. */
13295 mips_macc_chains_reorder (rtx *ready, int nready)
13299 if (mips_macc_chains_last_hilo != 0)
13300 for (i = nready - 1; i >= 0; i--)
13301 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
13303 for (j = nready - 1; j > i; j--)
13304 if (recog_memoized (ready[j]) >= 0
13305 && get_attr_may_clobber_hilo (ready[j]))
13307 mips_promote_ready (ready, i, j);
13314 /* The last instruction to be scheduled. */
13315 static rtx vr4130_last_insn;
13317 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
13318 points to an rtx that is initially an instruction. Nullify the rtx
13319 if the instruction uses the value of register X. */
13322 vr4130_true_reg_dependence_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
13327 insn_ptr = (rtx *) data;
13330 && reg_referenced_p (x, PATTERN (*insn_ptr)))
13334 /* Return true if there is true register dependence between vr4130_last_insn
13338 vr4130_true_reg_dependence_p (rtx insn)
13340 note_stores (PATTERN (vr4130_last_insn),
13341 vr4130_true_reg_dependence_p_1, &insn);
13345 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
13346 the ready queue and that INSN2 is the instruction after it, return
13347 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
13348 in which INSN1 and INSN2 can probably issue in parallel, but for
13349 which (INSN2, INSN1) should be less sensitive to instruction
13350 alignment than (INSN1, INSN2). See 4130.md for more details. */
13353 vr4130_swap_insns_p (rtx insn1, rtx insn2)
13355 sd_iterator_def sd_it;
13358 /* Check for the following case:
13360 1) there is some other instruction X with an anti dependence on INSN1;
13361 2) X has a higher priority than INSN2; and
13362 3) X is an arithmetic instruction (and thus has no unit restrictions).
13364 If INSN1 is the last instruction blocking X, it would better to
13365 choose (INSN1, X) over (INSN2, INSN1). */
13366 FOR_EACH_DEP (insn1, SD_LIST_FORW, sd_it, dep)
13367 if (DEP_TYPE (dep) == REG_DEP_ANTI
13368 && INSN_PRIORITY (DEP_CON (dep)) > INSN_PRIORITY (insn2)
13369 && recog_memoized (DEP_CON (dep)) >= 0
13370 && get_attr_vr4130_class (DEP_CON (dep)) == VR4130_CLASS_ALU)
13373 if (vr4130_last_insn != 0
13374 && recog_memoized (insn1) >= 0
13375 && recog_memoized (insn2) >= 0)
13377 /* See whether INSN1 and INSN2 use different execution units,
13378 or if they are both ALU-type instructions. If so, they can
13379 probably execute in parallel. */
13380 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
13381 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
13382 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
13384 /* If only one of the instructions has a dependence on
13385 vr4130_last_insn, prefer to schedule the other one first. */
13386 bool dep1_p = vr4130_true_reg_dependence_p (insn1);
13387 bool dep2_p = vr4130_true_reg_dependence_p (insn2);
13388 if (dep1_p != dep2_p)
13391 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
13392 is not an ALU-type instruction and if INSN1 uses the same
13393 execution unit. (Note that if this condition holds, we already
13394 know that INSN2 uses a different execution unit.) */
13395 if (class1 != VR4130_CLASS_ALU
13396 && recog_memoized (vr4130_last_insn) >= 0
13397 && class1 == get_attr_vr4130_class (vr4130_last_insn))
13404 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
13405 queue with at least two instructions. Swap the first two if
13406 vr4130_swap_insns_p says that it could be worthwhile. */
13409 vr4130_reorder (rtx *ready, int nready)
13411 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
13412 mips_promote_ready (ready, nready - 2, nready - 1);
13415 /* Record whether last 74k AGEN instruction was a load or store. */
13416 static enum attr_type mips_last_74k_agen_insn = TYPE_UNKNOWN;
13418 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
13419 resets to TYPE_UNKNOWN state. */
13422 mips_74k_agen_init (rtx insn)
13424 if (!insn || CALL_P (insn) || JUMP_P (insn))
13425 mips_last_74k_agen_insn = TYPE_UNKNOWN;
13428 enum attr_type type = get_attr_type (insn);
13429 if (type == TYPE_LOAD || type == TYPE_STORE)
13430 mips_last_74k_agen_insn = type;
13434 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
13435 loads to be grouped together, and multiple stores to be grouped
13436 together. Swap things around in the ready queue to make this happen. */
13439 mips_74k_agen_reorder (rtx *ready, int nready)
13442 int store_pos, load_pos;
13447 for (i = nready - 1; i >= 0; i--)
13449 rtx insn = ready[i];
13450 if (USEFUL_INSN_P (insn))
13451 switch (get_attr_type (insn))
13454 if (store_pos == -1)
13459 if (load_pos == -1)
13468 if (load_pos == -1 || store_pos == -1)
13471 switch (mips_last_74k_agen_insn)
13474 /* Prefer to schedule loads since they have a higher latency. */
13476 /* Swap loads to the front of the queue. */
13477 mips_maybe_swap_ready (ready, load_pos, store_pos, 4);
13480 /* Swap stores to the front of the queue. */
13481 mips_maybe_swap_ready (ready, store_pos, load_pos, 4);
13488 /* Implement TARGET_SCHED_INIT. */
13491 mips_sched_init (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13492 int max_ready ATTRIBUTE_UNUSED)
13494 mips_macc_chains_last_hilo = 0;
13495 vr4130_last_insn = 0;
13496 mips_74k_agen_init (NULL_RTX);
13498 /* When scheduling for Loongson2, branch instructions go to ALU1,
13499 therefore basic block is most likely to start with round-robin counter
13500 pointed to ALU2. */
13501 mips_ls2.alu1_turn_p = false;
13502 mips_ls2.falu1_turn_p = true;
13505 /* Subroutine used by TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
13508 mips_sched_reorder_1 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13509 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
13511 if (!reload_completed
13512 && TUNE_MACC_CHAINS
13514 mips_macc_chains_reorder (ready, *nreadyp);
13516 if (reload_completed
13518 && !TARGET_VR4130_ALIGN
13520 vr4130_reorder (ready, *nreadyp);
13523 mips_74k_agen_reorder (ready, *nreadyp);
13526 /* Implement TARGET_SCHED_REORDER. */
13529 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13530 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
13532 mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle);
13533 return mips_issue_rate ();
13536 /* Implement TARGET_SCHED_REORDER2. */
13539 mips_sched_reorder2 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13540 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
13542 mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle);
13543 return cached_can_issue_more;
13546 /* Update round-robin counters for ALU1/2 and FALU1/2. */
13549 mips_ls2_variable_issue (rtx insn)
13551 if (mips_ls2.alu1_turn_p)
13553 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu1_core_unit_code))
13554 mips_ls2.alu1_turn_p = false;
13558 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu2_core_unit_code))
13559 mips_ls2.alu1_turn_p = true;
13562 if (mips_ls2.falu1_turn_p)
13564 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu1_core_unit_code))
13565 mips_ls2.falu1_turn_p = false;
13569 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu2_core_unit_code))
13570 mips_ls2.falu1_turn_p = true;
13573 if (recog_memoized (insn) >= 0)
13574 mips_ls2.cycle_has_multi_p |= (get_attr_type (insn) == TYPE_MULTI);
13577 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
13580 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13581 rtx insn, int more)
13583 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
13584 if (USEFUL_INSN_P (insn))
13586 if (get_attr_type (insn) != TYPE_GHOST)
13588 if (!reload_completed && TUNE_MACC_CHAINS)
13589 mips_macc_chains_record (insn);
13590 vr4130_last_insn = insn;
13592 mips_74k_agen_init (insn);
13593 else if (TUNE_LOONGSON_2EF)
13594 mips_ls2_variable_issue (insn);
13597 /* Instructions of type 'multi' should all be split before
13598 the second scheduling pass. */
13599 gcc_assert (!reload_completed
13600 || recog_memoized (insn) < 0
13601 || get_attr_type (insn) != TYPE_MULTI);
13603 cached_can_issue_more = more;
13607 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
13608 return the first operand of the associated PREF or PREFX insn. */
13611 mips_prefetch_cookie (rtx write, rtx locality)
13613 /* store_streamed / load_streamed. */
13614 if (INTVAL (locality) <= 0)
13615 return GEN_INT (INTVAL (write) + 4);
13617 /* store / load. */
13618 if (INTVAL (locality) <= 2)
13621 /* store_retained / load_retained. */
13622 return GEN_INT (INTVAL (write) + 6);
13625 /* Flags that indicate when a built-in function is available.
13627 BUILTIN_AVAIL_NON_MIPS16
13628 The function is available on the current target, but only
13629 in non-MIPS16 mode. */
13630 #define BUILTIN_AVAIL_NON_MIPS16 1
13632 /* Declare an availability predicate for built-in functions that
13633 require non-MIPS16 mode and also require COND to be true.
13634 NAME is the main part of the predicate's name. */
13635 #define AVAIL_NON_MIPS16(NAME, COND) \
13636 static unsigned int \
13637 mips_builtin_avail_##NAME (void) \
13639 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
13642 /* This structure describes a single built-in function. */
13643 struct mips_builtin_description {
13644 /* The code of the main .md file instruction. See mips_builtin_type
13645 for more information. */
13646 enum insn_code icode;
13648 /* The floating-point comparison code to use with ICODE, if any. */
13649 enum mips_fp_condition cond;
13651 /* The name of the built-in function. */
13654 /* Specifies how the function should be expanded. */
13655 enum mips_builtin_type builtin_type;
13657 /* The function's prototype. */
13658 enum mips_function_type function_type;
13660 /* Whether the function is available. */
13661 unsigned int (*avail) (void);
13664 AVAIL_NON_MIPS16 (paired_single, TARGET_PAIRED_SINGLE_FLOAT)
13665 AVAIL_NON_MIPS16 (sb1_paired_single, TARGET_SB1 && TARGET_PAIRED_SINGLE_FLOAT)
13666 AVAIL_NON_MIPS16 (mips3d, TARGET_MIPS3D)
13667 AVAIL_NON_MIPS16 (dsp, TARGET_DSP)
13668 AVAIL_NON_MIPS16 (dspr2, TARGET_DSPR2)
13669 AVAIL_NON_MIPS16 (dsp_32, !TARGET_64BIT && TARGET_DSP)
13670 AVAIL_NON_MIPS16 (dsp_64, TARGET_64BIT && TARGET_DSP)
13671 AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2)
13672 AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS)
13673 AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
13675 /* Construct a mips_builtin_description from the given arguments.
13677 INSN is the name of the associated instruction pattern, without the
13678 leading CODE_FOR_mips_.
13680 CODE is the floating-point condition code associated with the
13681 function. It can be 'f' if the field is not applicable.
13683 NAME is the name of the function itself, without the leading
13686 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
13688 AVAIL is the name of the availability predicate, without the leading
13689 mips_builtin_avail_. */
13690 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
13691 FUNCTION_TYPE, AVAIL) \
13692 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
13693 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
13694 mips_builtin_avail_ ## AVAIL }
13696 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
13697 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
13698 are as for MIPS_BUILTIN. */
13699 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
13700 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
13702 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
13703 are subject to mips_builtin_avail_<AVAIL>. */
13704 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
13705 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
13706 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
13707 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
13708 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
13710 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
13711 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
13712 while the any and all forms are subject to mips_builtin_avail_mips3d. */
13713 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
13714 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
13715 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
13717 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
13718 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
13720 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
13721 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
13723 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
13724 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
13727 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
13728 are subject to mips_builtin_avail_mips3d. */
13729 #define CMP_4S_BUILTINS(INSN, COND) \
13730 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
13731 MIPS_BUILTIN_CMP_ANY, \
13732 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
13733 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
13734 MIPS_BUILTIN_CMP_ALL, \
13735 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
13737 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
13738 instruction requires mips_builtin_avail_<AVAIL>. */
13739 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
13740 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
13741 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
13743 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
13744 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
13747 /* Define all the built-in functions related to C.cond.fmt condition COND. */
13748 #define CMP_BUILTINS(COND) \
13749 MOVTF_BUILTINS (c, COND, paired_single), \
13750 MOVTF_BUILTINS (cabs, COND, mips3d), \
13751 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
13752 CMP_PS_BUILTINS (c, COND, paired_single), \
13753 CMP_PS_BUILTINS (cabs, COND, mips3d), \
13754 CMP_4S_BUILTINS (c, COND), \
13755 CMP_4S_BUILTINS (cabs, COND)
13757 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
13758 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
13759 and AVAIL are as for MIPS_BUILTIN. */
13760 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
13761 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
13762 FUNCTION_TYPE, AVAIL)
13764 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
13765 branch instruction. AVAIL is as for MIPS_BUILTIN. */
13766 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
13767 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
13768 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
13770 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
13771 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
13772 builtin_description field. */
13773 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
13774 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
13775 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
13776 FUNCTION_TYPE, mips_builtin_avail_loongson }
13778 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
13779 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
13780 builtin_description field. */
13781 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
13782 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
13784 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
13785 We use functions of this form when the same insn can be usefully applied
13786 to more than one datatype. */
13787 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
13788 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
13790 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
13791 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
13792 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
13793 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
13794 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
13795 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
13796 #define CODE_FOR_mips_mult CODE_FOR_mulsidi3_32bit
13797 #define CODE_FOR_mips_multu CODE_FOR_umulsidi3_32bit
13799 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
13800 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
13801 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
13802 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
13803 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
13804 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
13805 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
13806 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
13807 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
13808 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
13809 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
13810 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
13811 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
13812 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
13813 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
13814 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
13815 #define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3
13816 #define CODE_FOR_loongson_psllh CODE_FOR_ashlv4hi3
13817 #define CODE_FOR_loongson_psllw CODE_FOR_ashlv2si3
13818 #define CODE_FOR_loongson_psrlh CODE_FOR_lshrv4hi3
13819 #define CODE_FOR_loongson_psrlw CODE_FOR_lshrv2si3
13820 #define CODE_FOR_loongson_psrah CODE_FOR_ashrv4hi3
13821 #define CODE_FOR_loongson_psraw CODE_FOR_ashrv2si3
13822 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
13823 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
13824 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
13825 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
13826 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
13827 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
13828 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
13830 static const struct mips_builtin_description mips_builtins[] = {
13831 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13832 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13833 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13834 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13835 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, paired_single),
13836 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, paired_single),
13837 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, paired_single),
13838 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, paired_single),
13840 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT, paired_single),
13841 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13842 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13843 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
13844 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, mips3d),
13846 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, mips3d),
13847 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, mips3d),
13848 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
13849 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
13850 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
13851 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13853 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, mips3d),
13854 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, mips3d),
13855 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
13856 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
13857 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
13858 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13860 MIPS_FP_CONDITIONS (CMP_BUILTINS),
13862 /* Built-in functions for the SB-1 processor. */
13863 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, sb1_paired_single),
13865 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
13866 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13867 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13868 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
13869 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13870 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13871 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13872 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13873 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
13874 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13875 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13876 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, dsp),
13877 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, dsp),
13878 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, dsp),
13879 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, dsp),
13880 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, dsp),
13881 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, dsp),
13882 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
13883 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
13884 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
13885 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
13886 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, dsp),
13887 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, dsp),
13888 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
13889 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
13890 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
13891 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
13892 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
13893 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
13894 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
13895 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
13896 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
13897 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
13898 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
13899 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
13900 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
13901 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
13902 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
13903 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, dsp),
13904 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
13905 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
13906 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13907 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
13908 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
13909 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, dsp),
13910 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, dsp),
13911 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, dsp),
13912 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, dsp),
13913 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
13914 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
13915 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
13916 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
13917 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
13918 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
13919 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
13920 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
13921 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
13922 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13923 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13924 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13925 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, dsp),
13926 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, dsp),
13927 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_POINTER_SI, dsp),
13928 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_POINTER_SI, dsp),
13929 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_POINTER_SI, dsp),
13930 BPOSGE_BUILTIN (32, dsp),
13932 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
13933 DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, dspr2),
13934 DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13935 DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13936 DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
13937 DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
13938 DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
13939 DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
13940 DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
13941 DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
13942 DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
13943 DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13944 DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13945 DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13946 DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13947 DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13948 DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dspr2),
13949 DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
13950 DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
13951 DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
13952 DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
13953 DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
13954 DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, dspr2),
13955 DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13956 DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13957 DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
13958 DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
13959 DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13960 DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13961 DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13962 DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13963 DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13964 DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13965 DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13966 DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13968 /* Built-in functions for the DSP ASE (32-bit only). */
13969 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
13970 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
13971 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
13972 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
13973 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13974 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13975 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13976 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
13977 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
13978 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13979 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13980 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13981 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13982 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
13983 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
13984 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
13985 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, dsp_32),
13986 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, dsp_32),
13987 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, dsp_32),
13988 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, dsp_32),
13989 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, dsp_32),
13990 DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
13991 DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32),
13992 DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
13993 DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32),
13994 DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, dsp_32),
13995 DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, dsp_32),
13997 /* Built-in functions for the DSP ASE (64-bit only). */
13998 DIRECT_BUILTIN (ldx, MIPS_DI_FTYPE_POINTER_SI, dsp_64),
14000 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
14001 DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14002 DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14003 DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14004 DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14005 DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14006 DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14007 DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14008 DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14009 DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14011 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
14012 LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI),
14013 LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI),
14014 LOONGSON_BUILTIN (packushb, MIPS_UV8QI_FTYPE_UV4HI_UV4HI),
14015 LOONGSON_BUILTIN_SUFFIX (paddw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14016 LOONGSON_BUILTIN_SUFFIX (paddh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14017 LOONGSON_BUILTIN_SUFFIX (paddb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14018 LOONGSON_BUILTIN_SUFFIX (paddw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14019 LOONGSON_BUILTIN_SUFFIX (paddh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14020 LOONGSON_BUILTIN_SUFFIX (paddb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14021 LOONGSON_BUILTIN_SUFFIX (paddd, u, MIPS_UDI_FTYPE_UDI_UDI),
14022 LOONGSON_BUILTIN_SUFFIX (paddd, s, MIPS_DI_FTYPE_DI_DI),
14023 LOONGSON_BUILTIN (paddsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14024 LOONGSON_BUILTIN (paddsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
14025 LOONGSON_BUILTIN (paddush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14026 LOONGSON_BUILTIN (paddusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14027 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_ud, MIPS_UDI_FTYPE_UDI_UDI),
14028 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_uw, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14029 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_uh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14030 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_ub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14031 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_sd, MIPS_DI_FTYPE_DI_DI),
14032 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_sw, MIPS_V2SI_FTYPE_V2SI_V2SI),
14033 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_sh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14034 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_sb, MIPS_V8QI_FTYPE_V8QI_V8QI),
14035 LOONGSON_BUILTIN (pavgh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14036 LOONGSON_BUILTIN (pavgb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14037 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14038 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14039 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14040 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14041 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14042 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14043 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14044 LOONGSON_BUILTIN_SUFFIX (pcmpgth, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14045 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14046 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14047 LOONGSON_BUILTIN_SUFFIX (pcmpgth, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14048 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14049 LOONGSON_BUILTIN_SUFFIX (pextrh, u, MIPS_UV4HI_FTYPE_UV4HI_USI),
14050 LOONGSON_BUILTIN_SUFFIX (pextrh, s, MIPS_V4HI_FTYPE_V4HI_USI),
14051 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14052 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14053 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14054 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14055 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14056 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14057 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14058 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14059 LOONGSON_BUILTIN (pmaddhw, MIPS_V2SI_FTYPE_V4HI_V4HI),
14060 LOONGSON_BUILTIN (pmaxsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14061 LOONGSON_BUILTIN (pmaxub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14062 LOONGSON_BUILTIN (pminsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14063 LOONGSON_BUILTIN (pminub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14064 LOONGSON_BUILTIN_SUFFIX (pmovmskb, u, MIPS_UV8QI_FTYPE_UV8QI),
14065 LOONGSON_BUILTIN_SUFFIX (pmovmskb, s, MIPS_V8QI_FTYPE_V8QI),
14066 LOONGSON_BUILTIN (pmulhuh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14067 LOONGSON_BUILTIN (pmulhh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14068 LOONGSON_BUILTIN (pmullh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14069 LOONGSON_BUILTIN (pmuluw, MIPS_UDI_FTYPE_UV2SI_UV2SI),
14070 LOONGSON_BUILTIN (pasubub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14071 LOONGSON_BUILTIN (biadd, MIPS_UV4HI_FTYPE_UV8QI),
14072 LOONGSON_BUILTIN (psadbh, MIPS_UV4HI_FTYPE_UV8QI_UV8QI),
14073 LOONGSON_BUILTIN_SUFFIX (pshufh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
14074 LOONGSON_BUILTIN_SUFFIX (pshufh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
14075 LOONGSON_BUILTIN_SUFFIX (psllh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
14076 LOONGSON_BUILTIN_SUFFIX (psllh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
14077 LOONGSON_BUILTIN_SUFFIX (psllw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
14078 LOONGSON_BUILTIN_SUFFIX (psllw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
14079 LOONGSON_BUILTIN_SUFFIX (psrah, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
14080 LOONGSON_BUILTIN_SUFFIX (psrah, s, MIPS_V4HI_FTYPE_V4HI_UQI),
14081 LOONGSON_BUILTIN_SUFFIX (psraw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
14082 LOONGSON_BUILTIN_SUFFIX (psraw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
14083 LOONGSON_BUILTIN_SUFFIX (psrlh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
14084 LOONGSON_BUILTIN_SUFFIX (psrlh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
14085 LOONGSON_BUILTIN_SUFFIX (psrlw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
14086 LOONGSON_BUILTIN_SUFFIX (psrlw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
14087 LOONGSON_BUILTIN_SUFFIX (psubw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14088 LOONGSON_BUILTIN_SUFFIX (psubh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14089 LOONGSON_BUILTIN_SUFFIX (psubb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14090 LOONGSON_BUILTIN_SUFFIX (psubw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14091 LOONGSON_BUILTIN_SUFFIX (psubh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14092 LOONGSON_BUILTIN_SUFFIX (psubb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14093 LOONGSON_BUILTIN_SUFFIX (psubd, u, MIPS_UDI_FTYPE_UDI_UDI),
14094 LOONGSON_BUILTIN_SUFFIX (psubd, s, MIPS_DI_FTYPE_DI_DI),
14095 LOONGSON_BUILTIN (psubsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14096 LOONGSON_BUILTIN (psubsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
14097 LOONGSON_BUILTIN (psubush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14098 LOONGSON_BUILTIN (psubusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14099 LOONGSON_BUILTIN_SUFFIX (punpckhbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14100 LOONGSON_BUILTIN_SUFFIX (punpckhhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14101 LOONGSON_BUILTIN_SUFFIX (punpckhwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14102 LOONGSON_BUILTIN_SUFFIX (punpckhbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14103 LOONGSON_BUILTIN_SUFFIX (punpckhhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14104 LOONGSON_BUILTIN_SUFFIX (punpckhwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14105 LOONGSON_BUILTIN_SUFFIX (punpcklbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14106 LOONGSON_BUILTIN_SUFFIX (punpcklhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14107 LOONGSON_BUILTIN_SUFFIX (punpcklwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14108 LOONGSON_BUILTIN_SUFFIX (punpcklbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14109 LOONGSON_BUILTIN_SUFFIX (punpcklhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14110 LOONGSON_BUILTIN_SUFFIX (punpcklwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14112 /* Sundry other built-in functions. */
14113 DIRECT_NO_TARGET_BUILTIN (cache, MIPS_VOID_FTYPE_SI_CVPOINTER, cache)
14116 /* Index I is the function declaration for mips_builtins[I], or null if the
14117 function isn't defined on this target. */
14118 static GTY(()) tree mips_builtin_decls[ARRAY_SIZE (mips_builtins)];
14120 /* MODE is a vector mode whose elements have type TYPE. Return the type
14121 of the vector itself. */
14124 mips_builtin_vector_type (tree type, enum machine_mode mode)
14126 static tree types[2 * (int) MAX_MACHINE_MODE];
14129 mode_index = (int) mode;
14131 if (TREE_CODE (type) == INTEGER_TYPE && TYPE_UNSIGNED (type))
14132 mode_index += MAX_MACHINE_MODE;
14134 if (types[mode_index] == NULL_TREE)
14135 types[mode_index] = build_vector_type_for_mode (type, mode);
14136 return types[mode_index];
14139 /* Return a type for 'const volatile void *'. */
14142 mips_build_cvpointer_type (void)
14146 if (cache == NULL_TREE)
14147 cache = build_pointer_type (build_qualified_type
14149 TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE));
14153 /* Source-level argument types. */
14154 #define MIPS_ATYPE_VOID void_type_node
14155 #define MIPS_ATYPE_INT integer_type_node
14156 #define MIPS_ATYPE_POINTER ptr_type_node
14157 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
14159 /* Standard mode-based argument types. */
14160 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
14161 #define MIPS_ATYPE_SI intSI_type_node
14162 #define MIPS_ATYPE_USI unsigned_intSI_type_node
14163 #define MIPS_ATYPE_DI intDI_type_node
14164 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
14165 #define MIPS_ATYPE_SF float_type_node
14166 #define MIPS_ATYPE_DF double_type_node
14168 /* Vector argument types. */
14169 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
14170 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
14171 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
14172 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
14173 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
14174 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
14175 #define MIPS_ATYPE_UV2SI \
14176 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
14177 #define MIPS_ATYPE_UV4HI \
14178 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
14179 #define MIPS_ATYPE_UV8QI \
14180 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
14182 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
14183 their associated MIPS_ATYPEs. */
14184 #define MIPS_FTYPE_ATYPES1(A, B) \
14185 MIPS_ATYPE_##A, MIPS_ATYPE_##B
14187 #define MIPS_FTYPE_ATYPES2(A, B, C) \
14188 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
14190 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
14191 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
14193 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
14194 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
14197 /* Return the function type associated with function prototype TYPE. */
14200 mips_build_function_type (enum mips_function_type type)
14202 static tree types[(int) MIPS_MAX_FTYPE_MAX];
14204 if (types[(int) type] == NULL_TREE)
14207 #define DEF_MIPS_FTYPE(NUM, ARGS) \
14208 case MIPS_FTYPE_NAME##NUM ARGS: \
14209 types[(int) type] \
14210 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
14213 #include "config/mips/mips-ftypes.def"
14214 #undef DEF_MIPS_FTYPE
14216 gcc_unreachable ();
14219 return types[(int) type];
14222 /* Implement TARGET_INIT_BUILTINS. */
14225 mips_init_builtins (void)
14227 const struct mips_builtin_description *d;
14230 /* Iterate through all of the bdesc arrays, initializing all of the
14231 builtin functions. */
14232 for (i = 0; i < ARRAY_SIZE (mips_builtins); i++)
14234 d = &mips_builtins[i];
14236 mips_builtin_decls[i]
14237 = add_builtin_function (d->name,
14238 mips_build_function_type (d->function_type),
14239 i, BUILT_IN_MD, NULL, NULL);
14243 /* Implement TARGET_BUILTIN_DECL. */
14246 mips_builtin_decl (unsigned int code, bool initialize_p ATTRIBUTE_UNUSED)
14248 if (code >= ARRAY_SIZE (mips_builtins))
14249 return error_mark_node;
14250 return mips_builtin_decls[code];
14253 /* Take argument ARGNO from EXP's argument list and convert it into
14254 an expand operand. Store the operand in *OP. */
14257 mips_prepare_builtin_arg (struct expand_operand *op, tree exp,
14258 unsigned int argno)
14263 arg = CALL_EXPR_ARG (exp, argno);
14264 value = expand_normal (arg);
14265 create_input_operand (op, value, TYPE_MODE (TREE_TYPE (arg)));
14268 /* Expand instruction ICODE as part of a built-in function sequence.
14269 Use the first NOPS elements of OPS as the instruction's operands.
14270 HAS_TARGET_P is true if operand 0 is a target; it is false if the
14271 instruction has no target.
14273 Return the target rtx if HAS_TARGET_P, otherwise return const0_rtx. */
14276 mips_expand_builtin_insn (enum insn_code icode, unsigned int nops,
14277 struct expand_operand *ops, bool has_target_p)
14279 if (!maybe_expand_insn (icode, nops, ops))
14281 error ("invalid argument to built-in function");
14282 return has_target_p ? gen_reg_rtx (ops[0].mode) : const0_rtx;
14284 return has_target_p ? ops[0].value : const0_rtx;
14287 /* Expand a floating-point comparison for built-in function call EXP.
14288 The first NARGS arguments are the values to be compared. ICODE is
14289 the .md pattern that does the comparison and COND is the condition
14290 that is being tested. Return an rtx for the result. */
14293 mips_expand_builtin_compare_1 (enum insn_code icode,
14294 enum mips_fp_condition cond,
14295 tree exp, int nargs)
14297 struct expand_operand ops[MAX_RECOG_OPERANDS];
14301 /* The instruction should have a target operand, an operand for each
14302 argument, and an operand for COND. */
14303 gcc_assert (nargs + 2 == insn_data[(int) icode].n_generator_args);
14305 output = mips_allocate_fcc (insn_data[(int) icode].operand[0].mode);
14307 create_fixed_operand (&ops[opno++], output);
14308 for (argno = 0; argno < nargs; argno++)
14309 mips_prepare_builtin_arg (&ops[opno++], exp, argno);
14310 create_integer_operand (&ops[opno++], (int) cond);
14311 return mips_expand_builtin_insn (icode, opno, ops, true);
14314 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
14315 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
14316 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
14317 suggests a good place to put the result. */
14320 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
14323 struct expand_operand ops[MAX_RECOG_OPERANDS];
14326 /* Map any target to operand 0. */
14329 create_output_operand (&ops[opno++], target, TYPE_MODE (TREE_TYPE (exp)));
14331 /* Map the arguments to the other operands. */
14332 gcc_assert (opno + call_expr_nargs (exp)
14333 == insn_data[icode].n_generator_args);
14334 for (argno = 0; argno < call_expr_nargs (exp); argno++)
14335 mips_prepare_builtin_arg (&ops[opno++], exp, argno);
14337 return mips_expand_builtin_insn (icode, opno, ops, has_target_p);
14340 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
14341 function; TYPE says which. EXP is the CALL_EXPR that calls the
14342 function, ICODE is the instruction that should be used to compare
14343 the first two arguments, and COND is the condition it should test.
14344 TARGET, if nonnull, suggests a good place to put the result. */
14347 mips_expand_builtin_movtf (enum mips_builtin_type type,
14348 enum insn_code icode, enum mips_fp_condition cond,
14349 rtx target, tree exp)
14351 struct expand_operand ops[4];
14354 cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp, 2);
14355 create_output_operand (&ops[0], target, TYPE_MODE (TREE_TYPE (exp)));
14356 if (type == MIPS_BUILTIN_MOVT)
14358 mips_prepare_builtin_arg (&ops[2], exp, 2);
14359 mips_prepare_builtin_arg (&ops[1], exp, 3);
14363 mips_prepare_builtin_arg (&ops[1], exp, 2);
14364 mips_prepare_builtin_arg (&ops[2], exp, 3);
14366 create_fixed_operand (&ops[3], cmp_result);
14367 return mips_expand_builtin_insn (CODE_FOR_mips_cond_move_tf_ps,
14371 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
14372 into TARGET otherwise. Return TARGET. */
14375 mips_builtin_branch_and_move (rtx condition, rtx target,
14376 rtx value_if_true, rtx value_if_false)
14378 rtx true_label, done_label;
14380 true_label = gen_label_rtx ();
14381 done_label = gen_label_rtx ();
14383 /* First assume that CONDITION is false. */
14384 mips_emit_move (target, value_if_false);
14386 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
14387 emit_jump_insn (gen_condjump (condition, true_label));
14388 emit_jump_insn (gen_jump (done_label));
14391 /* Fix TARGET if CONDITION is true. */
14392 emit_label (true_label);
14393 mips_emit_move (target, value_if_true);
14395 emit_label (done_label);
14399 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
14400 the CALL_EXPR that calls the function, ICODE is the code of the
14401 comparison instruction, and COND is the condition it should test.
14402 TARGET, if nonnull, suggests a good place to put the boolean result. */
14405 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
14406 enum insn_code icode, enum mips_fp_condition cond,
14407 rtx target, tree exp)
14409 rtx offset, condition, cmp_result;
14411 if (target == 0 || GET_MODE (target) != SImode)
14412 target = gen_reg_rtx (SImode);
14413 cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp,
14414 call_expr_nargs (exp));
14416 /* If the comparison sets more than one register, we define the result
14417 to be 0 if all registers are false and -1 if all registers are true.
14418 The value of the complete result is indeterminate otherwise. */
14419 switch (builtin_type)
14421 case MIPS_BUILTIN_CMP_ALL:
14422 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
14423 return mips_builtin_branch_and_move (condition, target,
14424 const0_rtx, const1_rtx);
14426 case MIPS_BUILTIN_CMP_UPPER:
14427 case MIPS_BUILTIN_CMP_LOWER:
14428 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
14429 condition = gen_single_cc (cmp_result, offset);
14430 return mips_builtin_branch_and_move (condition, target,
14431 const1_rtx, const0_rtx);
14434 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
14435 return mips_builtin_branch_and_move (condition, target,
14436 const1_rtx, const0_rtx);
14440 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
14441 if nonnull, suggests a good place to put the boolean result. */
14444 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
14446 rtx condition, cmp_result;
14449 if (target == 0 || GET_MODE (target) != SImode)
14450 target = gen_reg_rtx (SImode);
14452 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
14454 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
14459 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
14460 return mips_builtin_branch_and_move (condition, target,
14461 const1_rtx, const0_rtx);
14464 /* Implement TARGET_EXPAND_BUILTIN. */
14467 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
14468 enum machine_mode mode, int ignore)
14471 unsigned int fcode, avail;
14472 const struct mips_builtin_description *d;
14474 fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
14475 fcode = DECL_FUNCTION_CODE (fndecl);
14476 gcc_assert (fcode < ARRAY_SIZE (mips_builtins));
14477 d = &mips_builtins[fcode];
14478 avail = d->avail ();
14479 gcc_assert (avail != 0);
14482 error ("built-in function %qE not supported for MIPS16",
14483 DECL_NAME (fndecl));
14484 return ignore ? const0_rtx : CONST0_RTX (mode);
14486 switch (d->builtin_type)
14488 case MIPS_BUILTIN_DIRECT:
14489 return mips_expand_builtin_direct (d->icode, target, exp, true);
14491 case MIPS_BUILTIN_DIRECT_NO_TARGET:
14492 return mips_expand_builtin_direct (d->icode, target, exp, false);
14494 case MIPS_BUILTIN_MOVT:
14495 case MIPS_BUILTIN_MOVF:
14496 return mips_expand_builtin_movtf (d->builtin_type, d->icode,
14497 d->cond, target, exp);
14499 case MIPS_BUILTIN_CMP_ANY:
14500 case MIPS_BUILTIN_CMP_ALL:
14501 case MIPS_BUILTIN_CMP_UPPER:
14502 case MIPS_BUILTIN_CMP_LOWER:
14503 case MIPS_BUILTIN_CMP_SINGLE:
14504 return mips_expand_builtin_compare (d->builtin_type, d->icode,
14505 d->cond, target, exp);
14507 case MIPS_BUILTIN_BPOSGE32:
14508 return mips_expand_builtin_bposge (d->builtin_type, target);
14510 gcc_unreachable ();
14513 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
14514 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
14515 struct mips16_constant {
14516 struct mips16_constant *next;
14519 enum machine_mode mode;
14522 /* Information about an incomplete MIPS16 constant pool. FIRST is the
14523 first constant, HIGHEST_ADDRESS is the highest address that the first
14524 byte of the pool can have, and INSN_ADDRESS is the current instruction
14526 struct mips16_constant_pool {
14527 struct mips16_constant *first;
14528 int highest_address;
14532 /* Add constant VALUE to POOL and return its label. MODE is the
14533 value's mode (used for CONST_INTs, etc.). */
14536 mips16_add_constant (struct mips16_constant_pool *pool,
14537 rtx value, enum machine_mode mode)
14539 struct mips16_constant **p, *c;
14540 bool first_of_size_p;
14542 /* See whether the constant is already in the pool. If so, return the
14543 existing label, otherwise leave P pointing to the place where the
14544 constant should be added.
14546 Keep the pool sorted in increasing order of mode size so that we can
14547 reduce the number of alignments needed. */
14548 first_of_size_p = true;
14549 for (p = &pool->first; *p != 0; p = &(*p)->next)
14551 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
14552 return (*p)->label;
14553 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
14555 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
14556 first_of_size_p = false;
14559 /* In the worst case, the constant needed by the earliest instruction
14560 will end up at the end of the pool. The entire pool must then be
14561 accessible from that instruction.
14563 When adding the first constant, set the pool's highest address to
14564 the address of the first out-of-range byte. Adjust this address
14565 downwards each time a new constant is added. */
14566 if (pool->first == 0)
14567 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
14568 of the instruction with the lowest two bits clear. The base PC
14569 value for LDPC has the lowest three bits clear. Assume the worst
14570 case here; namely that the PC-relative instruction occupies the
14571 last 2 bytes in an aligned word. */
14572 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
14573 pool->highest_address -= GET_MODE_SIZE (mode);
14574 if (first_of_size_p)
14575 /* Take into account the worst possible padding due to alignment. */
14576 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
14578 /* Create a new entry. */
14579 c = XNEW (struct mips16_constant);
14582 c->label = gen_label_rtx ();
14589 /* Output constant VALUE after instruction INSN and return the last
14590 instruction emitted. MODE is the mode of the constant. */
14593 mips16_emit_constants_1 (enum machine_mode mode, rtx value, rtx insn)
14595 if (SCALAR_INT_MODE_P (mode) || ALL_SCALAR_FIXED_POINT_MODE_P (mode))
14597 rtx size = GEN_INT (GET_MODE_SIZE (mode));
14598 return emit_insn_after (gen_consttable_int (value, size), insn);
14601 if (SCALAR_FLOAT_MODE_P (mode))
14602 return emit_insn_after (gen_consttable_float (value), insn);
14604 if (VECTOR_MODE_P (mode))
14608 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
14609 insn = mips16_emit_constants_1 (GET_MODE_INNER (mode),
14610 CONST_VECTOR_ELT (value, i), insn);
14614 gcc_unreachable ();
14617 /* Dump out the constants in CONSTANTS after INSN. */
14620 mips16_emit_constants (struct mips16_constant *constants, rtx insn)
14622 struct mips16_constant *c, *next;
14626 for (c = constants; c != NULL; c = next)
14628 /* If necessary, increase the alignment of PC. */
14629 if (align < GET_MODE_SIZE (c->mode))
14631 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
14632 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
14634 align = GET_MODE_SIZE (c->mode);
14636 insn = emit_label_after (c->label, insn);
14637 insn = mips16_emit_constants_1 (c->mode, c->value, insn);
14643 emit_barrier_after (insn);
14646 /* Return the length of instruction INSN. */
14649 mips16_insn_length (rtx insn)
14651 if (JUMP_TABLE_DATA_P (insn))
14653 rtx body = PATTERN (insn);
14654 if (GET_CODE (body) == ADDR_VEC)
14655 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
14656 else if (GET_CODE (body) == ADDR_DIFF_VEC)
14657 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
14659 gcc_unreachable ();
14661 return get_attr_length (insn);
14664 /* If *X is a symbolic constant that refers to the constant pool, add
14665 the constant to POOL and rewrite *X to use the constant's label. */
14668 mips16_rewrite_pool_constant (struct mips16_constant_pool *pool, rtx *x)
14670 rtx base, offset, label;
14672 split_const (*x, &base, &offset);
14673 if (GET_CODE (base) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (base))
14675 label = mips16_add_constant (pool, copy_rtx (get_pool_constant (base)),
14676 get_pool_mode (base));
14677 base = gen_rtx_LABEL_REF (Pmode, label);
14678 *x = mips_unspec_address_offset (base, offset, SYMBOL_PC_RELATIVE);
14682 /* This structure is used to communicate with mips16_rewrite_pool_refs.
14683 INSN is the instruction we're rewriting and POOL points to the current
14685 struct mips16_rewrite_pool_refs_info {
14687 struct mips16_constant_pool *pool;
14690 /* Rewrite *X so that constant pool references refer to the constant's
14691 label instead. DATA points to a mips16_rewrite_pool_refs_info
14695 mips16_rewrite_pool_refs (rtx *x, void *data)
14697 struct mips16_rewrite_pool_refs_info *info =
14698 (struct mips16_rewrite_pool_refs_info *) data;
14700 if (force_to_mem_operand (*x, Pmode))
14702 rtx mem = force_const_mem (GET_MODE (*x), *x);
14703 validate_change (info->insn, x, mem, false);
14708 mips16_rewrite_pool_constant (info->pool, &XEXP (*x, 0));
14712 /* Don't rewrite the __mips16_rdwr symbol. */
14713 if (GET_CODE (*x) == UNSPEC && XINT (*x, 1) == UNSPEC_TLS_GET_TP)
14716 if (TARGET_MIPS16_TEXT_LOADS)
14717 mips16_rewrite_pool_constant (info->pool, x);
14719 return GET_CODE (*x) == CONST ? -1 : 0;
14722 /* Return whether CFG is used in mips_reorg. */
14725 mips_cfg_in_reorg (void)
14727 return (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
14728 || TARGET_RELAX_PIC_CALLS);
14731 /* Build MIPS16 constant pools. Split the instructions if SPLIT_P,
14732 otherwise assume that they are already split. */
14735 mips16_lay_out_constants (bool split_p)
14737 struct mips16_constant_pool pool;
14738 struct mips16_rewrite_pool_refs_info info;
14741 if (!TARGET_MIPS16_PCREL_LOADS)
14746 if (mips_cfg_in_reorg ())
14747 split_all_insns ();
14749 split_all_insns_noflow ();
14752 memset (&pool, 0, sizeof (pool));
14753 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
14755 /* Rewrite constant pool references in INSN. */
14756 if (USEFUL_INSN_P (insn))
14760 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &info);
14763 pool.insn_address += mips16_insn_length (insn);
14765 if (pool.first != NULL)
14767 /* If there are no natural barriers between the first user of
14768 the pool and the highest acceptable address, we'll need to
14769 create a new instruction to jump around the constant pool.
14770 In the worst case, this instruction will be 4 bytes long.
14772 If it's too late to do this transformation after INSN,
14773 do it immediately before INSN. */
14774 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
14778 label = gen_label_rtx ();
14780 jump = emit_jump_insn_before (gen_jump (label), insn);
14781 JUMP_LABEL (jump) = label;
14782 LABEL_NUSES (label) = 1;
14783 barrier = emit_barrier_after (jump);
14785 emit_label_after (label, barrier);
14786 pool.insn_address += 4;
14789 /* See whether the constant pool is now out of range of the first
14790 user. If so, output the constants after the previous barrier.
14791 Note that any instructions between BARRIER and INSN (inclusive)
14792 will use negative offsets to refer to the pool. */
14793 if (pool.insn_address > pool.highest_address)
14795 mips16_emit_constants (pool.first, barrier);
14799 else if (BARRIER_P (insn))
14803 mips16_emit_constants (pool.first, get_last_insn ());
14806 /* Return true if it is worth r10k_simplify_address's while replacing
14807 an address with X. We are looking for constants, and for addresses
14808 at a known offset from the incoming stack pointer. */
14811 r10k_simplified_address_p (rtx x)
14813 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
14815 return x == virtual_incoming_args_rtx || CONSTANT_P (x);
14818 /* X is an expression that appears in INSN. Try to use the UD chains
14819 to simplify it, returning the simplified form on success and the
14820 original form otherwise. Replace the incoming value of $sp with
14821 virtual_incoming_args_rtx (which should never occur in X otherwise). */
14824 r10k_simplify_address (rtx x, rtx insn)
14826 rtx newx, op0, op1, set, def_insn, note;
14828 struct df_link *defs;
14833 op0 = r10k_simplify_address (XEXP (x, 0), insn);
14834 if (op0 != XEXP (x, 0))
14835 newx = simplify_gen_unary (GET_CODE (x), GET_MODE (x),
14836 op0, GET_MODE (XEXP (x, 0)));
14838 else if (BINARY_P (x))
14840 op0 = r10k_simplify_address (XEXP (x, 0), insn);
14841 op1 = r10k_simplify_address (XEXP (x, 1), insn);
14842 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
14843 newx = simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
14845 else if (GET_CODE (x) == LO_SUM)
14847 /* LO_SUMs can be offset from HIGHs, if we know they won't
14848 overflow. See mips_classify_address for the rationale behind
14850 op0 = r10k_simplify_address (XEXP (x, 0), insn);
14851 if (GET_CODE (op0) == HIGH)
14852 newx = XEXP (x, 1);
14854 else if (REG_P (x))
14856 /* Uses are recorded by regno_reg_rtx, not X itself. */
14857 use = df_find_use (insn, regno_reg_rtx[REGNO (x)]);
14859 defs = DF_REF_CHAIN (use);
14861 /* Require a single definition. */
14862 if (defs && defs->next == NULL)
14865 if (DF_REF_IS_ARTIFICIAL (def))
14867 /* Replace the incoming value of $sp with
14868 virtual_incoming_args_rtx. */
14869 if (x == stack_pointer_rtx
14870 && DF_REF_BB (def) == ENTRY_BLOCK_PTR)
14871 newx = virtual_incoming_args_rtx;
14873 else if (dominated_by_p (CDI_DOMINATORS, DF_REF_BB (use),
14876 /* Make sure that DEF_INSN is a single set of REG. */
14877 def_insn = DF_REF_INSN (def);
14878 if (NONJUMP_INSN_P (def_insn))
14880 set = single_set (def_insn);
14881 if (set && rtx_equal_p (SET_DEST (set), x))
14883 /* Prefer to use notes, since the def-use chains
14884 are often shorter. */
14885 note = find_reg_equal_equiv_note (def_insn);
14887 newx = XEXP (note, 0);
14889 newx = SET_SRC (set);
14890 newx = r10k_simplify_address (newx, def_insn);
14896 if (newx && r10k_simplified_address_p (newx))
14901 /* Return true if ADDRESS is known to be an uncached address
14902 on R10K systems. */
14905 r10k_uncached_address_p (unsigned HOST_WIDE_INT address)
14907 unsigned HOST_WIDE_INT upper;
14909 /* Check for KSEG1. */
14910 if (address + 0x60000000 < 0x20000000)
14913 /* Check for uncached XKPHYS addresses. */
14914 if (Pmode == DImode)
14916 upper = (address >> 40) & 0xf9ffff;
14917 if (upper == 0x900000 || upper == 0xb80000)
14923 /* Return true if we can prove that an access to address X in instruction
14924 INSN would be safe from R10K speculation. This X is a general
14925 expression; it might not be a legitimate address. */
14928 r10k_safe_address_p (rtx x, rtx insn)
14931 HOST_WIDE_INT offset_val;
14933 x = r10k_simplify_address (x, insn);
14935 /* Check for references to the stack frame. It doesn't really matter
14936 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
14937 allows us to assume that accesses to any part of the eventual frame
14938 is safe from speculation at any point in the function. */
14939 mips_split_plus (x, &base, &offset_val);
14940 if (base == virtual_incoming_args_rtx
14941 && offset_val >= -cfun->machine->frame.total_size
14942 && offset_val < cfun->machine->frame.args_size)
14945 /* Check for uncached addresses. */
14946 if (CONST_INT_P (x))
14947 return r10k_uncached_address_p (INTVAL (x));
14949 /* Check for accesses to a static object. */
14950 split_const (x, &base, &offset);
14951 return offset_within_block_p (base, INTVAL (offset));
14954 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
14955 an in-range access to an automatic variable, or to an object with
14956 a link-time-constant address. */
14959 r10k_safe_mem_expr_p (tree expr, HOST_WIDE_INT offset)
14961 HOST_WIDE_INT bitoffset, bitsize;
14962 tree inner, var_offset;
14963 enum machine_mode mode;
14964 int unsigned_p, volatile_p;
14966 inner = get_inner_reference (expr, &bitsize, &bitoffset, &var_offset, &mode,
14967 &unsigned_p, &volatile_p, false);
14968 if (!DECL_P (inner) || !DECL_SIZE_UNIT (inner) || var_offset)
14971 offset += bitoffset / BITS_PER_UNIT;
14972 return offset >= 0 && offset < tree_low_cst (DECL_SIZE_UNIT (inner), 1);
14975 /* A for_each_rtx callback for which DATA points to the instruction
14976 containing *X. Stop the search if we find a MEM that is not safe
14977 from R10K speculation. */
14980 r10k_needs_protection_p_1 (rtx *loc, void *data)
14989 && MEM_OFFSET_KNOWN_P (mem)
14990 && r10k_safe_mem_expr_p (MEM_EXPR (mem), MEM_OFFSET (mem)))
14993 if (r10k_safe_address_p (XEXP (mem, 0), (rtx) data))
14999 /* A note_stores callback for which DATA points to an instruction pointer.
15000 If *DATA is nonnull, make it null if it X contains a MEM that is not
15001 safe from R10K speculation. */
15004 r10k_needs_protection_p_store (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
15009 insn_ptr = (rtx *) data;
15010 if (*insn_ptr && for_each_rtx (&x, r10k_needs_protection_p_1, *insn_ptr))
15011 *insn_ptr = NULL_RTX;
15014 /* A for_each_rtx callback that iterates over the pattern of a CALL_INSN.
15015 Return nonzero if the call is not to a declared function. */
15018 r10k_needs_protection_p_call (rtx *loc, void *data ATTRIBUTE_UNUSED)
15027 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DECL (x))
15033 /* Return true if instruction INSN needs to be protected by an R10K
15037 r10k_needs_protection_p (rtx insn)
15040 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_call, NULL);
15042 if (mips_r10k_cache_barrier == R10K_CACHE_BARRIER_STORE)
15044 note_stores (PATTERN (insn), r10k_needs_protection_p_store, &insn);
15045 return insn == NULL_RTX;
15048 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_1, insn);
15051 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
15052 edge is unconditional. */
15055 r10k_protected_bb_p (basic_block bb, sbitmap protected_bbs)
15060 FOR_EACH_EDGE (e, ei, bb->preds)
15061 if (!single_succ_p (e->src)
15062 || !bitmap_bit_p (protected_bbs, e->src->index)
15063 || (e->flags & EDGE_COMPLEX) != 0)
15068 /* Implement -mr10k-cache-barrier= for the current function. */
15071 r10k_insert_cache_barriers (void)
15073 int *rev_post_order;
15076 sbitmap protected_bbs;
15077 rtx insn, end, unprotected_region;
15081 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
15085 /* Calculate dominators. */
15086 calculate_dominance_info (CDI_DOMINATORS);
15088 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
15089 X is protected by a cache barrier. */
15090 protected_bbs = sbitmap_alloc (last_basic_block);
15091 bitmap_clear (protected_bbs);
15093 /* Iterate over the basic blocks in reverse post-order. */
15094 rev_post_order = XNEWVEC (int, last_basic_block);
15095 n = pre_and_rev_post_order_compute (NULL, rev_post_order, false);
15096 for (i = 0; i < n; i++)
15098 bb = BASIC_BLOCK (rev_post_order[i]);
15100 /* If this block is only reached by unconditional edges, and if the
15101 source of every edge is protected, the beginning of the block is
15103 if (r10k_protected_bb_p (bb, protected_bbs))
15104 unprotected_region = NULL_RTX;
15106 unprotected_region = pc_rtx;
15107 end = NEXT_INSN (BB_END (bb));
15109 /* UNPROTECTED_REGION is:
15111 - null if we are processing a protected region,
15112 - pc_rtx if we are processing an unprotected region but have
15113 not yet found the first instruction in it
15114 - the first instruction in an unprotected region otherwise. */
15115 for (insn = BB_HEAD (bb); insn != end; insn = NEXT_INSN (insn))
15117 if (unprotected_region && USEFUL_INSN_P (insn))
15119 if (recog_memoized (insn) == CODE_FOR_mips_cache)
15120 /* This CACHE instruction protects the following code. */
15121 unprotected_region = NULL_RTX;
15124 /* See if INSN is the first instruction in this
15125 unprotected region. */
15126 if (unprotected_region == pc_rtx)
15127 unprotected_region = insn;
15129 /* See if INSN needs to be protected. If so,
15130 we must insert a cache barrier somewhere between
15131 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
15132 clear which position is better performance-wise,
15133 but as a tie-breaker, we assume that it is better
15134 to allow delay slots to be back-filled where
15135 possible, and that it is better not to insert
15136 barriers in the middle of already-scheduled code.
15137 We therefore insert the barrier at the beginning
15139 if (r10k_needs_protection_p (insn))
15141 emit_insn_before (gen_r10k_cache_barrier (),
15142 unprotected_region);
15143 unprotected_region = NULL_RTX;
15149 /* The called function is not required to protect the exit path.
15150 The code that follows a call is therefore unprotected. */
15151 unprotected_region = pc_rtx;
15154 /* Record whether the end of this block is protected. */
15155 if (unprotected_region == NULL_RTX)
15156 bitmap_set_bit (protected_bbs, bb->index);
15158 XDELETEVEC (rev_post_order);
15160 sbitmap_free (protected_bbs);
15162 free_dominance_info (CDI_DOMINATORS);
15165 /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX
15166 otherwise. If INSN has two call rtx, then store the second one in
15170 mips_call_expr_from_insn (rtx insn, rtx *second_call)
15175 if (!CALL_P (insn))
15178 x = PATTERN (insn);
15179 if (GET_CODE (x) == PARALLEL)
15181 /* Calls returning complex values have two CALL rtx. Look for the second
15182 one here, and return it via the SECOND_CALL arg. */
15183 x2 = XVECEXP (x, 0, 1);
15184 if (GET_CODE (x2) == SET)
15186 if (GET_CODE (x2) == CALL)
15189 x = XVECEXP (x, 0, 0);
15191 if (GET_CODE (x) == SET)
15193 gcc_assert (GET_CODE (x) == CALL);
15198 /* REG is set in DEF. See if the definition is one of the ways we load a
15199 register with a symbol address for a mips_use_pic_fn_addr_reg_p call.
15200 If it is, return the symbol reference of the function, otherwise return
15203 If RECURSE_P is true, use mips_find_pic_call_symbol to interpret
15204 the values of source registers, otherwise treat such registers as
15205 having an unknown value. */
15208 mips_pic_call_symbol_from_set (df_ref def, rtx reg, bool recurse_p)
15212 if (DF_REF_IS_ARTIFICIAL (def))
15215 def_insn = DF_REF_INSN (def);
15216 set = single_set (def_insn);
15217 if (set && rtx_equal_p (SET_DEST (set), reg))
15219 rtx note, src, symbol;
15221 /* First see whether the source is a plain symbol. This is used
15222 when calling symbols that are not lazily bound. */
15223 src = SET_SRC (set);
15224 if (GET_CODE (src) == SYMBOL_REF)
15227 /* Handle %call16 references. */
15228 symbol = mips_strip_unspec_call (src);
15231 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
15235 /* If we have something more complicated, look for a
15236 REG_EQUAL or REG_EQUIV note. */
15237 note = find_reg_equal_equiv_note (def_insn);
15238 if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF)
15239 return XEXP (note, 0);
15241 /* Follow at most one simple register copy. Such copies are
15242 interesting in cases like:
15246 locally_binding_fn (...);
15251 locally_binding_fn (...);
15253 locally_binding_fn (...);
15255 where the load of locally_binding_fn can legitimately be
15256 hoisted or shared. However, we do not expect to see complex
15257 chains of copies, so a full worklist solution to the problem
15258 would probably be overkill. */
15259 if (recurse_p && REG_P (src))
15260 return mips_find_pic_call_symbol (def_insn, src, false);
15266 /* Find the definition of the use of REG in INSN. See if the definition
15267 is one of the ways we load a register with a symbol address for a
15268 mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference
15269 of the function, otherwise return NULL_RTX. RECURSE_P is as for
15270 mips_pic_call_symbol_from_set. */
15273 mips_find_pic_call_symbol (rtx insn, rtx reg, bool recurse_p)
15276 struct df_link *defs;
15279 use = df_find_use (insn, regno_reg_rtx[REGNO (reg)]);
15282 defs = DF_REF_CHAIN (use);
15285 symbol = mips_pic_call_symbol_from_set (defs->ref, reg, recurse_p);
15289 /* If we have more than one definition, they need to be identical. */
15290 for (defs = defs->next; defs; defs = defs->next)
15294 other = mips_pic_call_symbol_from_set (defs->ref, reg, recurse_p);
15295 if (!rtx_equal_p (symbol, other))
15302 /* Replace the args_size operand of the call expression CALL with the
15303 call-attribute UNSPEC and fill in SYMBOL as the function symbol. */
15306 mips_annotate_pic_call_expr (rtx call, rtx symbol)
15310 args_size = XEXP (call, 1);
15311 XEXP (call, 1) = gen_rtx_UNSPEC (GET_MODE (args_size),
15312 gen_rtvec (2, args_size, symbol),
15316 /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See
15317 if instead of the arg_size argument it contains the call attributes. If
15318 yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function
15319 symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is
15323 mips_get_pic_call_symbol (rtx *operands, int args_size_opno)
15325 rtx args_size, symbol;
15327 if (!TARGET_RELAX_PIC_CALLS || args_size_opno == -1)
15330 args_size = operands[args_size_opno];
15331 if (GET_CODE (args_size) != UNSPEC)
15333 gcc_assert (XINT (args_size, 1) == UNSPEC_CALL_ATTR);
15335 symbol = XVECEXP (args_size, 0, 1);
15336 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
15338 operands[args_size_opno] = symbol;
15342 /* Use DF to annotate PIC indirect calls with the function symbol they
15346 mips_annotate_pic_calls (void)
15352 FOR_BB_INSNS (bb, insn)
15354 rtx call, reg, symbol, second_call;
15357 call = mips_call_expr_from_insn (insn, &second_call);
15360 gcc_assert (MEM_P (XEXP (call, 0)));
15361 reg = XEXP (XEXP (call, 0), 0);
15365 symbol = mips_find_pic_call_symbol (insn, reg, true);
15368 mips_annotate_pic_call_expr (call, symbol);
15370 mips_annotate_pic_call_expr (second_call, symbol);
15375 /* A temporary variable used by for_each_rtx callbacks, etc. */
15376 static rtx mips_sim_insn;
15378 /* A structure representing the state of the processor pipeline.
15379 Used by the mips_sim_* family of functions. */
15381 /* The maximum number of instructions that can be issued in a cycle.
15382 (Caches mips_issue_rate.) */
15383 unsigned int issue_rate;
15385 /* The current simulation time. */
15388 /* How many more instructions can be issued in the current cycle. */
15389 unsigned int insns_left;
15391 /* LAST_SET[X].INSN is the last instruction to set register X.
15392 LAST_SET[X].TIME is the time at which that instruction was issued.
15393 INSN is null if no instruction has yet set register X. */
15397 } last_set[FIRST_PSEUDO_REGISTER];
15399 /* The pipeline's current DFA state. */
15403 /* Reset STATE to the initial simulation state. */
15406 mips_sim_reset (struct mips_sim *state)
15408 curr_state = state->dfa_state;
15411 state->insns_left = state->issue_rate;
15412 memset (&state->last_set, 0, sizeof (state->last_set));
15413 state_reset (curr_state);
15415 targetm.sched.init (0, false, 0);
15416 advance_state (curr_state);
15419 /* Initialize STATE before its first use. DFA_STATE points to an
15420 allocated but uninitialized DFA state. */
15423 mips_sim_init (struct mips_sim *state, state_t dfa_state)
15425 if (targetm.sched.init_dfa_pre_cycle_insn)
15426 targetm.sched.init_dfa_pre_cycle_insn ();
15428 if (targetm.sched.init_dfa_post_cycle_insn)
15429 targetm.sched.init_dfa_post_cycle_insn ();
15431 state->issue_rate = mips_issue_rate ();
15432 state->dfa_state = dfa_state;
15433 mips_sim_reset (state);
15436 /* Advance STATE by one clock cycle. */
15439 mips_sim_next_cycle (struct mips_sim *state)
15441 curr_state = state->dfa_state;
15444 state->insns_left = state->issue_rate;
15445 advance_state (curr_state);
15448 /* Advance simulation state STATE until instruction INSN can read
15452 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
15454 unsigned int regno, end_regno;
15456 end_regno = END_REGNO (reg);
15457 for (regno = REGNO (reg); regno < end_regno; regno++)
15458 if (state->last_set[regno].insn != 0)
15462 t = (state->last_set[regno].time
15463 + insn_latency (state->last_set[regno].insn, insn));
15464 while (state->time < t)
15465 mips_sim_next_cycle (state);
15469 /* A for_each_rtx callback. If *X is a register, advance simulation state
15470 DATA until mips_sim_insn can read the register's value. */
15473 mips_sim_wait_regs_2 (rtx *x, void *data)
15476 mips_sim_wait_reg ((struct mips_sim *) data, mips_sim_insn, *x);
15480 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
15483 mips_sim_wait_regs_1 (rtx *x, void *data)
15485 for_each_rtx (x, mips_sim_wait_regs_2, data);
15488 /* Advance simulation state STATE until all of INSN's register
15489 dependencies are satisfied. */
15492 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
15494 mips_sim_insn = insn;
15495 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
15498 /* Advance simulation state STATE until the units required by
15499 instruction INSN are available. */
15502 mips_sim_wait_units (struct mips_sim *state, rtx insn)
15506 tmp_state = alloca (state_size ());
15507 while (state->insns_left == 0
15508 || (memcpy (tmp_state, state->dfa_state, state_size ()),
15509 state_transition (tmp_state, insn) >= 0))
15510 mips_sim_next_cycle (state);
15513 /* Advance simulation state STATE until INSN is ready to issue. */
15516 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
15518 mips_sim_wait_regs (state, insn);
15519 mips_sim_wait_units (state, insn);
15522 /* mips_sim_insn has just set X. Update the LAST_SET array
15523 in simulation state DATA. */
15526 mips_sim_record_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
15528 struct mips_sim *state;
15530 state = (struct mips_sim *) data;
15533 unsigned int regno, end_regno;
15535 end_regno = END_REGNO (x);
15536 for (regno = REGNO (x); regno < end_regno; regno++)
15538 state->last_set[regno].insn = mips_sim_insn;
15539 state->last_set[regno].time = state->time;
15544 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
15545 can issue immediately (i.e., that mips_sim_wait_insn has already
15549 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
15551 curr_state = state->dfa_state;
15553 state_transition (curr_state, insn);
15554 state->insns_left = targetm.sched.variable_issue (0, false, insn,
15555 state->insns_left);
15557 mips_sim_insn = insn;
15558 note_stores (PATTERN (insn), mips_sim_record_set, state);
15561 /* Simulate issuing a NOP in state STATE. */
15564 mips_sim_issue_nop (struct mips_sim *state)
15566 if (state->insns_left == 0)
15567 mips_sim_next_cycle (state);
15568 state->insns_left--;
15571 /* Update simulation state STATE so that it's ready to accept the instruction
15572 after INSN. INSN should be part of the main rtl chain, not a member of a
15576 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
15578 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
15580 mips_sim_issue_nop (state);
15582 switch (GET_CODE (SEQ_BEGIN (insn)))
15586 /* We can't predict the processor state after a call or label. */
15587 mips_sim_reset (state);
15591 /* The delay slots of branch likely instructions are only executed
15592 when the branch is taken. Therefore, if the caller has simulated
15593 the delay slot instruction, STATE does not really reflect the state
15594 of the pipeline for the instruction after the delay slot. Also,
15595 branch likely instructions tend to incur a penalty when not taken,
15596 so there will probably be an extra delay between the branch and
15597 the instruction after the delay slot. */
15598 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
15599 mips_sim_reset (state);
15607 /* Use simulator state STATE to calculate the execution time of
15608 instruction sequence SEQ. */
15610 static unsigned int
15611 mips_seq_time (struct mips_sim *state, rtx seq)
15613 mips_sim_reset (state);
15614 for (rtx insn = seq; insn; insn = NEXT_INSN (insn))
15616 mips_sim_wait_insn (state, insn);
15617 mips_sim_issue_insn (state, insn);
15619 return state->time;
15622 /* Return the execution-time cost of mips_tuning_info.fast_mult_zero_zero_p
15623 setting SETTING, using STATE to simulate instruction sequences. */
15625 static unsigned int
15626 mips_mult_zero_zero_cost (struct mips_sim *state, bool setting)
15628 mips_tuning_info.fast_mult_zero_zero_p = setting;
15631 enum machine_mode dword_mode = TARGET_64BIT ? TImode : DImode;
15632 rtx hilo = gen_rtx_REG (dword_mode, MD_REG_FIRST);
15633 mips_emit_move_or_split (hilo, const0_rtx, SPLIT_FOR_SPEED);
15635 /* If the target provides mulsidi3_32bit then that's the most likely
15636 consumer of the result. Test for bypasses. */
15637 if (dword_mode == DImode && HAVE_maddsidi4)
15639 rtx gpr = gen_rtx_REG (SImode, GP_REG_FIRST + 4);
15640 emit_insn (gen_maddsidi4 (hilo, gpr, gpr, hilo));
15643 unsigned int time = mips_seq_time (state, get_insns ());
15648 /* Check the relative speeds of "MULT $0,$0" and "MTLO $0; MTHI $0"
15649 and set up mips_tuning_info.fast_mult_zero_zero_p accordingly.
15650 Prefer MULT -- which is shorter -- in the event of a tie. */
15653 mips_set_fast_mult_zero_zero_p (struct mips_sim *state)
15656 /* No MTLO or MTHI available. */
15657 mips_tuning_info.fast_mult_zero_zero_p = true;
15660 unsigned int true_time = mips_mult_zero_zero_cost (state, true);
15661 unsigned int false_time = mips_mult_zero_zero_cost (state, false);
15662 mips_tuning_info.fast_mult_zero_zero_p = (true_time <= false_time);
15666 /* Set up costs based on the current architecture and tuning settings. */
15669 mips_set_tuning_info (void)
15671 if (mips_tuning_info.initialized_p
15672 && mips_tuning_info.arch == mips_arch
15673 && mips_tuning_info.tune == mips_tune
15674 && mips_tuning_info.mips16_p == TARGET_MIPS16)
15677 mips_tuning_info.arch = mips_arch;
15678 mips_tuning_info.tune = mips_tune;
15679 mips_tuning_info.mips16_p = TARGET_MIPS16;
15680 mips_tuning_info.initialized_p = true;
15684 struct mips_sim state;
15685 mips_sim_init (&state, alloca (state_size ()));
15687 mips_set_fast_mult_zero_zero_p (&state);
15692 /* Implement TARGET_EXPAND_TO_RTL_HOOK. */
15695 mips_expand_to_rtl_hook (void)
15697 /* We need to call this at a point where we can safely create sequences
15698 of instructions, so TARGET_OVERRIDE_OPTIONS is too early. We also
15699 need to call it at a point where the DFA infrastructure is not
15700 already in use, so we can't just call it lazily on demand.
15702 At present, mips_tuning_info is only needed during post-expand
15703 RTL passes such as split_insns, so this hook should be early enough.
15704 We may need to move the call elsewhere if mips_tuning_info starts
15705 to be used for other things (such as rtx_costs, or expanders that
15706 could be called during gimple optimization). */
15707 mips_set_tuning_info ();
15710 /* The VR4130 pipeline issues aligned pairs of instructions together,
15711 but it stalls the second instruction if it depends on the first.
15712 In order to cut down the amount of logic required, this dependence
15713 check is not based on a full instruction decode. Instead, any non-SPECIAL
15714 instruction is assumed to modify the register specified by bits 20-16
15715 (which is usually the "rt" field).
15717 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
15718 input, so we can end up with a false dependence between the branch
15719 and its delay slot. If this situation occurs in instruction INSN,
15720 try to avoid it by swapping rs and rt. */
15723 vr4130_avoid_branch_rt_conflict (rtx insn)
15727 first = SEQ_BEGIN (insn);
15728 second = SEQ_END (insn);
15730 && NONJUMP_INSN_P (second)
15731 && GET_CODE (PATTERN (first)) == SET
15732 && GET_CODE (SET_DEST (PATTERN (first))) == PC
15733 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
15735 /* Check for the right kind of condition. */
15736 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
15737 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
15738 && REG_P (XEXP (cond, 0))
15739 && REG_P (XEXP (cond, 1))
15740 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
15741 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
15743 /* SECOND mentions the rt register but not the rs register. */
15744 rtx tmp = XEXP (cond, 0);
15745 XEXP (cond, 0) = XEXP (cond, 1);
15746 XEXP (cond, 1) = tmp;
15751 /* Implement -mvr4130-align. Go through each basic block and simulate the
15752 processor pipeline. If we find that a pair of instructions could execute
15753 in parallel, and the first of those instructions is not 8-byte aligned,
15754 insert a nop to make it aligned. */
15757 vr4130_align_insns (void)
15759 struct mips_sim state;
15760 rtx insn, subinsn, last, last2, next;
15765 /* LAST is the last instruction before INSN to have a nonzero length.
15766 LAST2 is the last such instruction before LAST. */
15770 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
15773 mips_sim_init (&state, alloca (state_size ()));
15774 for (insn = get_insns (); insn != 0; insn = next)
15776 unsigned int length;
15778 next = NEXT_INSN (insn);
15780 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
15781 This isn't really related to the alignment pass, but we do it on
15782 the fly to avoid a separate instruction walk. */
15783 vr4130_avoid_branch_rt_conflict (insn);
15785 length = get_attr_length (insn);
15786 if (length > 0 && USEFUL_INSN_P (insn))
15787 FOR_EACH_SUBINSN (subinsn, insn)
15789 mips_sim_wait_insn (&state, subinsn);
15791 /* If we want this instruction to issue in parallel with the
15792 previous one, make sure that the previous instruction is
15793 aligned. There are several reasons why this isn't worthwhile
15794 when the second instruction is a call:
15796 - Calls are less likely to be performance critical,
15797 - There's a good chance that the delay slot can execute
15798 in parallel with the call.
15799 - The return address would then be unaligned.
15801 In general, if we're going to insert a nop between instructions
15802 X and Y, it's better to insert it immediately after X. That
15803 way, if the nop makes Y aligned, it will also align any labels
15804 between X and Y. */
15805 if (state.insns_left != state.issue_rate
15806 && !CALL_P (subinsn))
15808 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
15810 /* SUBINSN is the first instruction in INSN and INSN is
15811 aligned. We want to align the previous instruction
15812 instead, so insert a nop between LAST2 and LAST.
15814 Note that LAST could be either a single instruction
15815 or a branch with a delay slot. In the latter case,
15816 LAST, like INSN, is already aligned, but the delay
15817 slot must have some extra delay that stops it from
15818 issuing at the same time as the branch. We therefore
15819 insert a nop before the branch in order to align its
15821 gcc_assert (last2);
15822 emit_insn_after (gen_nop (), last2);
15825 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
15827 /* SUBINSN is the delay slot of INSN, but INSN is
15828 currently unaligned. Insert a nop between
15829 LAST and INSN to align it. */
15831 emit_insn_after (gen_nop (), last);
15835 mips_sim_issue_insn (&state, subinsn);
15837 mips_sim_finish_insn (&state, insn);
15839 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
15840 length = get_attr_length (insn);
15843 /* If the instruction is an asm statement or multi-instruction
15844 mips.md patern, the length is only an estimate. Insert an
15845 8 byte alignment after it so that the following instructions
15846 can be handled correctly. */
15847 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
15848 && (recog_memoized (insn) < 0 || length >= 8))
15850 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
15851 next = NEXT_INSN (next);
15852 mips_sim_next_cycle (&state);
15855 else if (length & 4)
15856 aligned_p = !aligned_p;
15861 /* See whether INSN is an aligned label. */
15862 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
15868 /* This structure records that the current function has a LO_SUM
15869 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
15870 the largest offset applied to BASE by all such LO_SUMs. */
15871 struct mips_lo_sum_offset {
15873 HOST_WIDE_INT offset;
15876 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
15879 mips_hash_base (rtx base)
15881 int do_not_record_p;
15883 return hash_rtx (base, GET_MODE (base), &do_not_record_p, NULL, false);
15886 /* Hash-table callbacks for mips_lo_sum_offsets. */
15889 mips_lo_sum_offset_hash (const void *entry)
15891 return mips_hash_base (((const struct mips_lo_sum_offset *) entry)->base);
15895 mips_lo_sum_offset_eq (const void *entry, const void *value)
15897 return rtx_equal_p (((const struct mips_lo_sum_offset *) entry)->base,
15898 (const_rtx) value);
15901 /* Look up symbolic constant X in HTAB, which is a hash table of
15902 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
15903 paired with a recorded LO_SUM, otherwise record X in the table. */
15906 mips_lo_sum_offset_lookup (htab_t htab, rtx x, enum insert_option option)
15910 struct mips_lo_sum_offset *entry;
15912 /* Split X into a base and offset. */
15913 split_const (x, &base, &offset);
15914 if (UNSPEC_ADDRESS_P (base))
15915 base = UNSPEC_ADDRESS (base);
15917 /* Look up the base in the hash table. */
15918 slot = htab_find_slot_with_hash (htab, base, mips_hash_base (base), option);
15922 entry = (struct mips_lo_sum_offset *) *slot;
15923 if (option == INSERT)
15927 entry = XNEW (struct mips_lo_sum_offset);
15928 entry->base = base;
15929 entry->offset = INTVAL (offset);
15934 if (INTVAL (offset) > entry->offset)
15935 entry->offset = INTVAL (offset);
15938 return INTVAL (offset) <= entry->offset;
15941 /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table.
15942 Record every LO_SUM in *LOC. */
15945 mips_record_lo_sum (rtx *loc, void *data)
15947 if (GET_CODE (*loc) == LO_SUM)
15948 mips_lo_sum_offset_lookup ((htab_t) data, XEXP (*loc, 1), INSERT);
15952 /* Return true if INSN is a SET of an orphaned high-part relocation.
15953 HTAB is a hash table of mips_lo_sum_offsets that describes all the
15954 LO_SUMs in the current function. */
15957 mips_orphaned_high_part_p (htab_t htab, rtx insn)
15959 enum mips_symbol_type type;
15962 set = single_set (insn);
15965 /* Check for %his. */
15967 if (GET_CODE (x) == HIGH
15968 && absolute_symbolic_operand (XEXP (x, 0), VOIDmode))
15969 return !mips_lo_sum_offset_lookup (htab, XEXP (x, 0), NO_INSERT);
15971 /* Check for local %gots (and %got_pages, which is redundant but OK). */
15972 if (GET_CODE (x) == UNSPEC
15973 && XINT (x, 1) == UNSPEC_LOAD_GOT
15974 && mips_symbolic_constant_p (XVECEXP (x, 0, 1),
15975 SYMBOL_CONTEXT_LEA, &type)
15976 && type == SYMBOL_GOTOFF_PAGE)
15977 return !mips_lo_sum_offset_lookup (htab, XVECEXP (x, 0, 1), NO_INSERT);
15982 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
15983 INSN and a previous instruction, avoid it by inserting nops after
15986 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
15987 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
15988 before using the value of that register. *HILO_DELAY counts the
15989 number of instructions since the last hilo hazard (that is,
15990 the number of instructions since the last MFLO or MFHI).
15992 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
15993 for the next instruction.
15995 LO_REG is an rtx for the LO register, used in dependence checking. */
15998 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
15999 rtx *delayed_reg, rtx lo_reg)
16004 pattern = PATTERN (insn);
16006 /* Do not put the whole function in .set noreorder if it contains
16007 an asm statement. We don't know whether there will be hazards
16008 between the asm statement and the gcc-generated code. */
16009 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
16010 cfun->machine->all_noreorder_p = false;
16012 /* Ignore zero-length instructions (barriers and the like). */
16013 ninsns = get_attr_length (insn) / 4;
16017 /* Work out how many nops are needed. Note that we only care about
16018 registers that are explicitly mentioned in the instruction's pattern.
16019 It doesn't matter that calls use the argument registers or that they
16020 clobber hi and lo. */
16021 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
16022 nops = 2 - *hilo_delay;
16023 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
16028 /* Insert the nops between this instruction and the previous one.
16029 Each new nop takes us further from the last hilo hazard. */
16030 *hilo_delay += nops;
16032 emit_insn_after (gen_hazard_nop (), after);
16034 /* Set up the state for the next instruction. */
16035 *hilo_delay += ninsns;
16037 if (INSN_CODE (insn) >= 0)
16038 switch (get_attr_hazard (insn))
16048 set = single_set (insn);
16050 *delayed_reg = SET_DEST (set);
16055 /* Go through the instruction stream and insert nops where necessary.
16056 Also delete any high-part relocations whose partnering low parts
16057 are now all dead. See if the whole function can then be put into
16058 .set noreorder and .set nomacro. */
16061 mips_reorg_process_insns (void)
16063 rtx insn, last_insn, subinsn, next_insn, lo_reg, delayed_reg;
16067 /* Force all instructions to be split into their final form. */
16068 split_all_insns_noflow ();
16070 /* Recalculate instruction lengths without taking nops into account. */
16071 cfun->machine->ignore_hazard_length_p = true;
16072 shorten_branches (get_insns ());
16074 cfun->machine->all_noreorder_p = true;
16076 /* We don't track MIPS16 PC-relative offsets closely enough to make
16077 a good job of "set .noreorder" code in MIPS16 mode. */
16079 cfun->machine->all_noreorder_p = false;
16081 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
16082 if (!TARGET_EXPLICIT_RELOCS)
16083 cfun->machine->all_noreorder_p = false;
16085 /* Profiled functions can't be all noreorder because the profiler
16086 support uses assembler macros. */
16088 cfun->machine->all_noreorder_p = false;
16090 /* Code compiled with -mfix-vr4120 or -mfix-24k can't be all noreorder
16091 because we rely on the assembler to work around some errata. */
16092 if (TARGET_FIX_VR4120 || TARGET_FIX_24K)
16093 cfun->machine->all_noreorder_p = false;
16095 /* The same is true for -mfix-vr4130 if we might generate MFLO or
16096 MFHI instructions. Note that we avoid using MFLO and MFHI if
16097 the VR4130 MACC and DMACC instructions are available instead;
16098 see the *mfhilo_{si,di}_macc patterns. */
16099 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
16100 cfun->machine->all_noreorder_p = false;
16102 htab = htab_create (37, mips_lo_sum_offset_hash,
16103 mips_lo_sum_offset_eq, free);
16105 /* Make a first pass over the instructions, recording all the LO_SUMs. */
16106 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
16107 FOR_EACH_SUBINSN (subinsn, insn)
16108 if (USEFUL_INSN_P (subinsn))
16109 for_each_rtx (&PATTERN (subinsn), mips_record_lo_sum, htab);
16114 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
16116 /* Make a second pass over the instructions. Delete orphaned
16117 high-part relocations or turn them into NOPs. Avoid hazards
16118 by inserting NOPs. */
16119 for (insn = get_insns (); insn != 0; insn = next_insn)
16121 next_insn = NEXT_INSN (insn);
16122 if (USEFUL_INSN_P (insn))
16124 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
16126 /* If we find an orphaned high-part relocation in a delay
16127 slot, it's easier to turn that instruction into a NOP than
16128 to delete it. The delay slot will be a NOP either way. */
16129 FOR_EACH_SUBINSN (subinsn, insn)
16130 if (INSN_P (subinsn))
16132 if (mips_orphaned_high_part_p (htab, subinsn))
16134 PATTERN (subinsn) = gen_nop ();
16135 INSN_CODE (subinsn) = CODE_FOR_nop;
16137 mips_avoid_hazard (last_insn, subinsn, &hilo_delay,
16138 &delayed_reg, lo_reg);
16144 /* INSN is a single instruction. Delete it if it's an
16145 orphaned high-part relocation. */
16146 if (mips_orphaned_high_part_p (htab, insn))
16147 delete_insn (insn);
16148 /* Also delete cache barriers if the last instruction
16149 was an annulled branch. INSN will not be speculatively
16151 else if (recog_memoized (insn) == CODE_FOR_r10k_cache_barrier
16153 && JUMP_P (SEQ_BEGIN (last_insn))
16154 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn)))
16155 delete_insn (insn);
16158 mips_avoid_hazard (last_insn, insn, &hilo_delay,
16159 &delayed_reg, lo_reg);
16166 htab_delete (htab);
16169 /* Return true if the function has a long branch instruction. */
16172 mips_has_long_branch_p (void)
16177 /* We need up-to-date instruction lengths. */
16178 shorten_branches (get_insns ());
16180 /* Look for a branch that is longer than normal. The normal length for
16181 non-MIPS16 branches is 8, because the length includes the delay slot.
16182 It is 4 for MIPS16, because MIPS16 branches are extended instructions,
16183 but they have no delay slot. */
16184 normal_length = (TARGET_MIPS16 ? 4 : 8);
16185 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
16186 FOR_EACH_SUBINSN (subinsn, insn)
16187 if (JUMP_P (subinsn)
16188 && get_attr_length (subinsn) > normal_length
16189 && (any_condjump_p (subinsn) || any_uncondjump_p (subinsn)))
16195 /* If we are using a GOT, but have not decided to use a global pointer yet,
16196 see whether we need one to implement long branches. Convert the ghost
16197 global-pointer instructions into real ones if so. */
16200 mips_expand_ghost_gp_insns (void)
16202 /* Quick exit if we already know that we will or won't need a
16204 if (!TARGET_USE_GOT
16205 || cfun->machine->global_pointer == INVALID_REGNUM
16206 || mips_must_initialize_gp_p ())
16209 /* Run a full check for long branches. */
16210 if (!mips_has_long_branch_p ())
16213 /* We've now established that we need $gp. */
16214 cfun->machine->must_initialize_gp_p = true;
16215 split_all_insns_noflow ();
16220 /* Subroutine of mips_reorg to manage passes that require DF. */
16223 mips_df_reorg (void)
16225 /* Create def-use chains. */
16226 df_set_flags (DF_EQ_NOTES);
16227 df_chain_add_problem (DF_UD_CHAIN);
16230 if (TARGET_RELAX_PIC_CALLS)
16231 mips_annotate_pic_calls ();
16233 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE)
16234 r10k_insert_cache_barriers ();
16236 df_finish_pass (false);
16239 /* Emit code to load LABEL_REF SRC into MIPS16 register DEST. This is
16240 called very late in mips_reorg, but the caller is required to run
16241 mips16_lay_out_constants on the result. */
16244 mips16_load_branch_target (rtx dest, rtx src)
16246 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
16250 if (mips_cfun_has_cprestore_slot_p ())
16251 mips_emit_move (dest, mips_cprestore_slot (dest, true));
16253 mips_emit_move (dest, pic_offset_table_rtx);
16254 page = mips_unspec_address (src, SYMBOL_GOTOFF_PAGE);
16255 low = mips_unspec_address (src, SYMBOL_GOT_PAGE_OFST);
16256 emit_insn (gen_rtx_SET (VOIDmode, dest,
16257 PMODE_INSN (gen_unspec_got, (dest, page))));
16258 emit_insn (gen_rtx_SET (VOIDmode, dest,
16259 gen_rtx_LO_SUM (Pmode, dest, low)));
16263 src = mips_unspec_address (src, SYMBOL_ABSOLUTE);
16264 mips_emit_move (dest, src);
16268 /* If we're compiling a MIPS16 function, look for and split any long branches.
16269 This must be called after all other instruction modifications in
16273 mips16_split_long_branches (void)
16275 bool something_changed;
16277 if (!TARGET_MIPS16)
16280 /* Loop until the alignments for all targets are sufficient. */
16285 shorten_branches (get_insns ());
16286 something_changed = false;
16287 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
16289 && get_attr_length (insn) > 8
16290 && (any_condjump_p (insn) || any_uncondjump_p (insn)))
16292 rtx old_label, new_label, temp, saved_temp;
16293 rtx target, jump, jump_sequence;
16297 /* Free up a MIPS16 register by saving it in $1. */
16298 saved_temp = gen_rtx_REG (Pmode, AT_REGNUM);
16299 temp = gen_rtx_REG (Pmode, GP_REG_FIRST + 2);
16300 emit_move_insn (saved_temp, temp);
16302 /* Load the branch target into TEMP. */
16303 old_label = JUMP_LABEL (insn);
16304 target = gen_rtx_LABEL_REF (Pmode, old_label);
16305 mips16_load_branch_target (temp, target);
16307 /* Jump to the target and restore the register's
16309 jump = emit_jump_insn (PMODE_INSN (gen_indirect_jump_and_restore,
16310 (temp, temp, saved_temp)));
16311 JUMP_LABEL (jump) = old_label;
16312 LABEL_NUSES (old_label)++;
16314 /* Rewrite any symbolic references that are supposed to use
16315 a PC-relative constant pool. */
16316 mips16_lay_out_constants (false);
16318 if (simplejump_p (insn))
16319 /* We're going to replace INSN with a longer form. */
16320 new_label = NULL_RTX;
16323 /* Create a branch-around label for the original
16325 new_label = gen_label_rtx ();
16326 emit_label (new_label);
16329 jump_sequence = get_insns ();
16332 emit_insn_after (jump_sequence, insn);
16334 invert_jump (insn, new_label, false);
16336 delete_insn (insn);
16337 something_changed = true;
16340 while (something_changed);
16343 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
16348 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during
16349 insn splitting in mips16_lay_out_constants, DF insn info is only kept up
16350 to date if the CFG is available. */
16351 if (mips_cfg_in_reorg ())
16352 compute_bb_for_insn ();
16353 mips16_lay_out_constants (true);
16354 if (mips_cfg_in_reorg ())
16357 free_bb_for_insn ();
16360 if (optimize > 0 && flag_delayed_branch)
16362 cleanup_barriers ();
16363 dbr_schedule (get_insns ());
16365 mips_reorg_process_insns ();
16367 && TARGET_EXPLICIT_RELOCS
16369 && TARGET_VR4130_ALIGN)
16370 vr4130_align_insns ();
16371 if (mips_expand_ghost_gp_insns ())
16372 /* The expansion could invalidate some of the VR4130 alignment
16373 optimizations, but this should be an extremely rare case anyhow. */
16374 mips_reorg_process_insns ();
16375 mips16_split_long_branches ();
16378 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
16379 in order to avoid duplicating too much logic from elsewhere. */
16382 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
16383 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
16386 rtx this_rtx, temp1, temp2, insn, fnaddr;
16387 bool use_sibcall_p;
16389 /* Pretend to be a post-reload pass while generating rtl. */
16390 reload_completed = 1;
16392 /* Mark the end of the (empty) prologue. */
16393 emit_note (NOTE_INSN_PROLOGUE_END);
16395 /* Determine if we can use a sibcall to call FUNCTION directly. */
16396 fnaddr = XEXP (DECL_RTL (function), 0);
16397 use_sibcall_p = (mips_function_ok_for_sibcall (function, NULL)
16398 && const_call_insn_operand (fnaddr, Pmode));
16400 /* Determine if we need to load FNADDR from the GOT. */
16402 && (mips_got_symbol_type_p
16403 (mips_classify_symbol (fnaddr, SYMBOL_CONTEXT_LEA))))
16405 /* Pick a global pointer. Use a call-clobbered register if
16406 TARGET_CALL_SAVED_GP. */
16407 cfun->machine->global_pointer
16408 = TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM;
16409 cfun->machine->must_initialize_gp_p = true;
16410 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
16412 /* Set up the global pointer for n32 or n64 abicalls. */
16413 mips_emit_loadgp ();
16416 /* We need two temporary registers in some cases. */
16417 temp1 = gen_rtx_REG (Pmode, 2);
16418 temp2 = gen_rtx_REG (Pmode, 3);
16420 /* Find out which register contains the "this" pointer. */
16421 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
16422 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
16424 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST);
16426 /* Add DELTA to THIS_RTX. */
16429 rtx offset = GEN_INT (delta);
16430 if (!SMALL_OPERAND (delta))
16432 mips_emit_move (temp1, offset);
16435 emit_insn (gen_add3_insn (this_rtx, this_rtx, offset));
16438 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
16439 if (vcall_offset != 0)
16443 /* Set TEMP1 to *THIS_RTX. */
16444 mips_emit_move (temp1, gen_rtx_MEM (Pmode, this_rtx));
16446 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
16447 addr = mips_add_offset (temp2, temp1, vcall_offset);
16449 /* Load the offset and add it to THIS_RTX. */
16450 mips_emit_move (temp1, gen_rtx_MEM (Pmode, addr));
16451 emit_insn (gen_add3_insn (this_rtx, this_rtx, temp1));
16454 /* Jump to the target function. Use a sibcall if direct jumps are
16455 allowed, otherwise load the address into a register first. */
16458 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
16459 SIBLING_CALL_P (insn) = 1;
16463 /* This is messy. GAS treats "la $25,foo" as part of a call
16464 sequence and may allow a global "foo" to be lazily bound.
16465 The general move patterns therefore reject this combination.
16467 In this context, lazy binding would actually be OK
16468 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
16469 TARGET_CALL_SAVED_GP; see mips_load_call_address.
16470 We must therefore load the address via a temporary
16471 register if mips_dangerous_for_la25_p.
16473 If we jump to the temporary register rather than $25,
16474 the assembler can use the move insn to fill the jump's
16477 We can use the same technique for MIPS16 code, where $25
16478 is not a valid JR register. */
16479 if (TARGET_USE_PIC_FN_ADDR_REG
16481 && !mips_dangerous_for_la25_p (fnaddr))
16482 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
16483 mips_load_call_address (MIPS_CALL_SIBCALL, temp1, fnaddr);
16485 if (TARGET_USE_PIC_FN_ADDR_REG
16486 && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
16487 mips_emit_move (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
16488 emit_jump_insn (gen_indirect_jump (temp1));
16491 /* Run just enough of rest_of_compilation. This sequence was
16492 "borrowed" from alpha.c. */
16493 insn = get_insns ();
16494 split_all_insns_noflow ();
16495 mips16_lay_out_constants (true);
16496 shorten_branches (insn);
16497 final_start_function (insn, file, 1);
16498 final (insn, file, 1);
16499 final_end_function ();
16501 /* Clean up the vars set above. Note that final_end_function resets
16502 the global pointer for us. */
16503 reload_completed = 0;
16507 /* The last argument passed to mips_set_compression_mode,
16508 or negative if the function hasn't been called yet. */
16509 static unsigned int old_compression_mode = -1;
16511 /* Set up the target-dependent global state for ISA mode COMPRESSION_MODE,
16512 which is either MASK_MIPS16 or MASK_MICROMIPS. */
16515 mips_set_compression_mode (unsigned int compression_mode)
16518 if (compression_mode == old_compression_mode)
16521 /* Restore base settings of various flags. */
16522 target_flags = mips_base_target_flags;
16523 flag_schedule_insns = mips_base_schedule_insns;
16524 flag_reorder_blocks_and_partition = mips_base_reorder_blocks_and_partition;
16525 flag_move_loop_invariants = mips_base_move_loop_invariants;
16526 align_loops = mips_base_align_loops;
16527 align_jumps = mips_base_align_jumps;
16528 align_functions = mips_base_align_functions;
16529 target_flags &= ~(MASK_MIPS16 | MASK_MICROMIPS);
16530 target_flags |= compression_mode;
16532 if (compression_mode & MASK_MIPS16)
16534 /* Switch to MIPS16 mode. */
16535 target_flags |= MASK_MIPS16;
16537 /* Turn off SYNCI if it was on, MIPS16 doesn't support it. */
16538 target_flags &= ~MASK_SYNCI;
16540 /* Don't run the scheduler before reload, since it tends to
16541 increase register pressure. */
16542 flag_schedule_insns = 0;
16544 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
16545 the whole function to be in a single section. */
16546 flag_reorder_blocks_and_partition = 0;
16548 /* Don't move loop invariants, because it tends to increase
16549 register pressure. It also introduces an extra move in cases
16550 where the constant is the first operand in a two-operand binary
16551 instruction, or when it forms a register argument to a functon
16553 flag_move_loop_invariants = 0;
16555 target_flags |= MASK_EXPLICIT_RELOCS;
16557 /* Experiments suggest we get the best overall section-anchor
16558 results from using the range of an unextended LW or SW. Code
16559 that makes heavy use of byte or short accesses can do better
16560 with ranges of 0...31 and 0...63 respectively, but most code is
16561 sensitive to the range of LW and SW instead. */
16562 targetm.min_anchor_offset = 0;
16563 targetm.max_anchor_offset = 127;
16565 targetm.const_anchor = 0;
16567 /* MIPS16 has no BAL instruction. */
16568 target_flags &= ~MASK_RELAX_PIC_CALLS;
16570 /* The R4000 errata don't apply to any known MIPS16 cores.
16571 It's simpler to make the R4000 fixes and MIPS16 mode
16572 mutually exclusive. */
16573 target_flags &= ~MASK_FIX_R4000;
16575 if (flag_pic && !TARGET_OLDABI)
16576 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
16579 sorry ("MIPS16 -mxgot code");
16581 if (TARGET_HARD_FLOAT_ABI && !TARGET_OLDABI)
16582 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
16586 /* Switch to microMIPS or the standard encoding. */
16588 if (TARGET_MICROMIPS)
16589 /* Avoid branch likely. */
16590 target_flags &= ~MASK_BRANCHLIKELY;
16592 /* Provide default values for align_* for 64-bit targets. */
16595 if (align_loops == 0)
16597 if (align_jumps == 0)
16599 if (align_functions == 0)
16600 align_functions = 8;
16603 targetm.min_anchor_offset = -32768;
16604 targetm.max_anchor_offset = 32767;
16606 targetm.const_anchor = 0x8000;
16609 /* (Re)initialize MIPS target internals for new ISA. */
16610 mips_init_relocs ();
16612 if (compression_mode & MASK_MIPS16)
16614 if (!mips16_globals)
16615 mips16_globals = save_target_globals_default_opts ();
16617 restore_target_globals (mips16_globals);
16620 restore_target_globals (&default_target_globals);
16622 old_compression_mode = compression_mode;
16625 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
16626 function should use the MIPS16 or microMIPS ISA and switch modes
16630 mips_set_current_function (tree fndecl)
16632 mips_set_compression_mode (mips_get_compress_mode (fndecl));
16635 /* Allocate a chunk of memory for per-function machine-dependent data. */
16637 static struct machine_function *
16638 mips_init_machine_status (void)
16640 return ggc_alloc_cleared_machine_function ();
16643 /* Return the processor associated with the given ISA level, or null
16644 if the ISA isn't valid. */
16646 static const struct mips_cpu_info *
16647 mips_cpu_info_from_isa (int isa)
16651 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
16652 if (mips_cpu_info_table[i].isa == isa)
16653 return mips_cpu_info_table + i;
16658 /* Return a mips_cpu_info entry determined by an option valued
16661 static const struct mips_cpu_info *
16662 mips_cpu_info_from_opt (int opt)
16666 case MIPS_ARCH_OPTION_FROM_ABI:
16667 /* 'from-abi' selects the most compatible architecture for the
16668 given ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit
16669 ABIs. For the EABIs, we have to decide whether we're using
16670 the 32-bit or 64-bit version. */
16671 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
16672 : ABI_NEEDS_64BIT_REGS ? 3
16673 : (TARGET_64BIT ? 3 : 1));
16675 case MIPS_ARCH_OPTION_NATIVE:
16676 gcc_unreachable ();
16679 return &mips_cpu_info_table[opt];
16683 /* Return a default mips_cpu_info entry, given that no -march= option
16684 was explicitly specified. */
16686 static const struct mips_cpu_info *
16687 mips_default_arch (void)
16689 #if defined (MIPS_CPU_STRING_DEFAULT)
16691 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
16692 if (strcmp (mips_cpu_info_table[i].name, MIPS_CPU_STRING_DEFAULT) == 0)
16693 return mips_cpu_info_table + i;
16694 gcc_unreachable ();
16695 #elif defined (MIPS_ISA_DEFAULT)
16696 return mips_cpu_info_from_isa (MIPS_ISA_DEFAULT);
16698 /* 'from-abi' makes a good default: you get whatever the ABI
16700 return mips_cpu_info_from_opt (MIPS_ARCH_OPTION_FROM_ABI);
16704 /* Set up globals to generate code for the ISA or processor
16705 described by INFO. */
16708 mips_set_architecture (const struct mips_cpu_info *info)
16712 mips_arch_info = info;
16713 mips_arch = info->cpu;
16714 mips_isa = info->isa;
16718 /* Likewise for tuning. */
16721 mips_set_tune (const struct mips_cpu_info *info)
16725 mips_tune_info = info;
16726 mips_tune = info->cpu;
16730 /* Implement TARGET_OPTION_OVERRIDE. */
16733 mips_option_override (void)
16735 int i, start, regno, mode;
16737 if (global_options_set.x_mips_isa_option)
16738 mips_isa_option_info = &mips_cpu_info_table[mips_isa_option];
16740 #ifdef SUBTARGET_OVERRIDE_OPTIONS
16741 SUBTARGET_OVERRIDE_OPTIONS;
16744 /* MIPS16 and microMIPS cannot coexist. */
16745 if (TARGET_MICROMIPS && TARGET_MIPS16)
16746 error ("unsupported combination: %s", "-mips16 -mmicromips");
16748 /* Save the base compression state and process flags as though we
16749 were generating uncompressed code. */
16750 mips_base_compression_flags = TARGET_COMPRESSION;
16751 target_flags &= ~TARGET_COMPRESSION;
16753 /* -mno-float overrides -mhard-float and -msoft-float. */
16754 if (TARGET_NO_FLOAT)
16756 target_flags |= MASK_SOFT_FLOAT_ABI;
16757 target_flags_explicit |= MASK_SOFT_FLOAT_ABI;
16760 if (TARGET_FLIP_MIPS16)
16761 TARGET_INTERLINK_COMPRESSED = 1;
16763 /* Set the small data limit. */
16764 mips_small_data_threshold = (global_options_set.x_g_switch_value
16766 : MIPS_DEFAULT_GVALUE);
16768 /* The following code determines the architecture and register size.
16769 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
16770 The GAS and GCC code should be kept in sync as much as possible. */
16772 if (global_options_set.x_mips_arch_option)
16773 mips_set_architecture (mips_cpu_info_from_opt (mips_arch_option));
16775 if (mips_isa_option_info != 0)
16777 if (mips_arch_info == 0)
16778 mips_set_architecture (mips_isa_option_info);
16779 else if (mips_arch_info->isa != mips_isa_option_info->isa)
16780 error ("%<-%s%> conflicts with the other architecture options, "
16781 "which specify a %s processor",
16782 mips_isa_option_info->name,
16783 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
16786 if (mips_arch_info == 0)
16787 mips_set_architecture (mips_default_arch ());
16789 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
16790 error ("%<-march=%s%> is not compatible with the selected ABI",
16791 mips_arch_info->name);
16793 /* Optimize for mips_arch, unless -mtune selects a different processor. */
16794 if (global_options_set.x_mips_tune_option)
16795 mips_set_tune (mips_cpu_info_from_opt (mips_tune_option));
16797 if (mips_tune_info == 0)
16798 mips_set_tune (mips_arch_info);
16800 if ((target_flags_explicit & MASK_64BIT) != 0)
16802 /* The user specified the size of the integer registers. Make sure
16803 it agrees with the ABI and ISA. */
16804 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
16805 error ("%<-mgp64%> used with a 32-bit processor");
16806 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
16807 error ("%<-mgp32%> used with a 64-bit ABI");
16808 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
16809 error ("%<-mgp64%> used with a 32-bit ABI");
16813 /* Infer the integer register size from the ABI and processor.
16814 Restrict ourselves to 32-bit registers if that's all the
16815 processor has, or if the ABI cannot handle 64-bit registers. */
16816 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
16817 target_flags &= ~MASK_64BIT;
16819 target_flags |= MASK_64BIT;
16822 if ((target_flags_explicit & MASK_FLOAT64) != 0)
16824 if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
16825 error ("unsupported combination: %s", "-mfp64 -msingle-float");
16826 else if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
16827 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
16828 else if (!TARGET_64BIT && TARGET_FLOAT64)
16830 if (!ISA_HAS_MXHC1)
16831 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
16832 " the target supports the mfhc1 and mthc1 instructions");
16833 else if (mips_abi != ABI_32)
16834 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
16840 /* -msingle-float selects 32-bit float registers. Otherwise the
16841 float registers should be the same size as the integer ones. */
16842 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
16843 target_flags |= MASK_FLOAT64;
16845 target_flags &= ~MASK_FLOAT64;
16848 /* End of code shared with GAS. */
16850 /* If a -mlong* option was given, check that it matches the ABI,
16851 otherwise infer the -mlong* setting from the other options. */
16852 if ((target_flags_explicit & MASK_LONG64) != 0)
16856 if (mips_abi == ABI_N32)
16857 error ("%qs is incompatible with %qs", "-mabi=n32", "-mlong64");
16858 else if (mips_abi == ABI_32)
16859 error ("%qs is incompatible with %qs", "-mabi=32", "-mlong64");
16860 else if (mips_abi == ABI_O64 && TARGET_ABICALLS)
16861 /* We have traditionally allowed non-abicalls code to use
16862 an LP64 form of o64. However, it would take a bit more
16863 effort to support the combination of 32-bit GOT entries
16864 and 64-bit pointers, so we treat the abicalls case as
16866 error ("the combination of %qs and %qs is incompatible with %qs",
16867 "-mabi=o64", "-mabicalls", "-mlong64");
16871 if (mips_abi == ABI_64)
16872 error ("%qs is incompatible with %qs", "-mabi=64", "-mlong32");
16877 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
16878 target_flags |= MASK_LONG64;
16880 target_flags &= ~MASK_LONG64;
16883 if (!TARGET_OLDABI)
16884 flag_pcc_struct_return = 0;
16886 /* Decide which rtx_costs structure to use. */
16888 mips_cost = &mips_rtx_cost_optimize_size;
16890 mips_cost = &mips_rtx_cost_data[mips_tune];
16892 /* If the user hasn't specified a branch cost, use the processor's
16894 if (mips_branch_cost == 0)
16895 mips_branch_cost = mips_cost->branch_cost;
16897 /* If neither -mbranch-likely nor -mno-branch-likely was given
16898 on the command line, set MASK_BRANCHLIKELY based on the target
16899 architecture and tuning flags. Annulled delay slots are a
16900 size win, so we only consider the processor-specific tuning
16901 for !optimize_size. */
16902 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
16904 if (ISA_HAS_BRANCHLIKELY
16906 || (mips_tune_info->tune_flags & PTF_AVOID_BRANCHLIKELY) == 0))
16907 target_flags |= MASK_BRANCHLIKELY;
16909 target_flags &= ~MASK_BRANCHLIKELY;
16911 else if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
16912 warning (0, "the %qs architecture does not support branch-likely"
16913 " instructions", mips_arch_info->name);
16915 /* If the user hasn't specified -mimadd or -mno-imadd set
16916 MASK_IMADD based on the target architecture and tuning
16918 if ((target_flags_explicit & MASK_IMADD) == 0)
16920 if (ISA_HAS_MADD_MSUB &&
16921 (mips_tune_info->tune_flags & PTF_AVOID_IMADD) == 0)
16922 target_flags |= MASK_IMADD;
16924 target_flags &= ~MASK_IMADD;
16926 else if (TARGET_IMADD && !ISA_HAS_MADD_MSUB)
16927 warning (0, "the %qs architecture does not support madd or msub"
16928 " instructions", mips_arch_info->name);
16930 /* The effect of -mabicalls isn't defined for the EABI. */
16931 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
16933 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
16934 target_flags &= ~MASK_ABICALLS;
16937 /* PIC requires -mabicalls. */
16940 if (mips_abi == ABI_EABI)
16941 error ("cannot generate position-independent code for %qs",
16943 else if (!TARGET_ABICALLS)
16944 error ("position-independent code requires %qs", "-mabicalls");
16947 if (TARGET_ABICALLS_PIC2)
16948 /* We need to set flag_pic for executables as well as DSOs
16949 because we may reference symbols that are not defined in
16950 the final executable. (MIPS does not use things like
16951 copy relocs, for example.)
16953 There is a body of code that uses __PIC__ to distinguish
16954 between -mabicalls and -mno-abicalls code. The non-__PIC__
16955 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
16956 long as any indirect jumps use $25. */
16959 /* -mvr4130-align is a "speed over size" optimization: it usually produces
16960 faster code, but at the expense of more nops. Enable it at -O3 and
16962 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
16963 target_flags |= MASK_VR4130_ALIGN;
16965 /* Prefer a call to memcpy over inline code when optimizing for size,
16966 though see MOVE_RATIO in mips.h. */
16967 if (optimize_size && (target_flags_explicit & MASK_MEMCPY) == 0)
16968 target_flags |= MASK_MEMCPY;
16970 /* If we have a nonzero small-data limit, check that the -mgpopt
16971 setting is consistent with the other target flags. */
16972 if (mips_small_data_threshold > 0)
16976 if (!TARGET_EXPLICIT_RELOCS)
16977 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
16979 TARGET_LOCAL_SDATA = false;
16980 TARGET_EXTERN_SDATA = false;
16984 if (TARGET_VXWORKS_RTP)
16985 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
16987 if (TARGET_ABICALLS)
16988 warning (0, "cannot use small-data accesses for %qs",
16993 /* Make sure that the user didn't turn off paired single support when
16994 MIPS-3D support is requested. */
16996 && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
16997 && !TARGET_PAIRED_SINGLE_FLOAT)
16998 error ("%<-mips3d%> requires %<-mpaired-single%>");
17000 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
17002 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
17004 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
17005 and TARGET_HARD_FLOAT_ABI are both true. */
17006 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT_ABI))
17007 error ("%qs must be used with %qs",
17008 TARGET_MIPS3D ? "-mips3d" : "-mpaired-single",
17009 TARGET_HARD_FLOAT_ABI ? "-mfp64" : "-mhard-float");
17011 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
17013 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_HAS_PAIRED_SINGLE)
17014 warning (0, "the %qs architecture does not support paired-single"
17015 " instructions", mips_arch_info->name);
17017 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
17018 && !TARGET_CACHE_BUILTIN)
17020 error ("%qs requires a target that provides the %qs instruction",
17021 "-mr10k-cache-barrier", "cache");
17022 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE;
17025 /* If TARGET_DSPR2, enable MASK_DSP. */
17027 target_flags |= MASK_DSP;
17029 /* .eh_frame addresses should be the same width as a C pointer.
17030 Most MIPS ABIs support only one pointer size, so the assembler
17031 will usually know exactly how big an .eh_frame address is.
17033 Unfortunately, this is not true of the 64-bit EABI. The ABI was
17034 originally defined to use 64-bit pointers (i.e. it is LP64), and
17035 this is still the default mode. However, we also support an n32-like
17036 ILP32 mode, which is selected by -mlong32. The problem is that the
17037 assembler has traditionally not had an -mlong option, so it has
17038 traditionally not known whether we're using the ILP32 or LP64 form.
17040 As it happens, gas versions up to and including 2.19 use _32-bit_
17041 addresses for EABI64 .cfi_* directives. This is wrong for the
17042 default LP64 mode, so we can't use the directives by default.
17043 Moreover, since gas's current behavior is at odds with gcc's
17044 default behavior, it seems unwise to rely on future versions
17045 of gas behaving the same way. We therefore avoid using .cfi
17046 directives for -mlong32 as well. */
17047 if (mips_abi == ABI_EABI && TARGET_64BIT)
17048 flag_dwarf2_cfi_asm = 0;
17050 /* .cfi_* directives generate a read-only section, so fall back on
17051 manual .eh_frame creation if we need the section to be writable. */
17052 if (TARGET_WRITABLE_EH_FRAME)
17053 flag_dwarf2_cfi_asm = 0;
17055 mips_init_print_operand_punct ();
17057 /* Set up array to map GCC register number to debug register number.
17058 Ignore the special purpose register numbers. */
17060 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
17062 mips_dbx_regno[i] = IGNORED_DWARF_REGNUM;
17063 if (GP_REG_P (i) || FP_REG_P (i) || ALL_COP_REG_P (i))
17064 mips_dwarf_regno[i] = i;
17066 mips_dwarf_regno[i] = INVALID_REGNUM;
17069 start = GP_DBX_FIRST - GP_REG_FIRST;
17070 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
17071 mips_dbx_regno[i] = i + start;
17073 start = FP_DBX_FIRST - FP_REG_FIRST;
17074 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
17075 mips_dbx_regno[i] = i + start;
17077 /* Accumulator debug registers use big-endian ordering. */
17078 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
17079 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
17080 mips_dwarf_regno[HI_REGNUM] = MD_REG_FIRST + 0;
17081 mips_dwarf_regno[LO_REGNUM] = MD_REG_FIRST + 1;
17082 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
17084 mips_dwarf_regno[i + TARGET_LITTLE_ENDIAN] = i;
17085 mips_dwarf_regno[i + TARGET_BIG_ENDIAN] = i + 1;
17088 /* Set up mips_hard_regno_mode_ok. */
17089 for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
17090 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
17091 mips_hard_regno_mode_ok[mode][regno]
17092 = mips_hard_regno_mode_ok_p (regno, (enum machine_mode) mode);
17094 /* Function to allocate machine-dependent function status. */
17095 init_machine_status = &mips_init_machine_status;
17097 /* Default to working around R4000 errata only if the processor
17098 was selected explicitly. */
17099 if ((target_flags_explicit & MASK_FIX_R4000) == 0
17100 && strcmp (mips_arch_info->name, "r4000") == 0)
17101 target_flags |= MASK_FIX_R4000;
17103 /* Default to working around R4400 errata only if the processor
17104 was selected explicitly. */
17105 if ((target_flags_explicit & MASK_FIX_R4400) == 0
17106 && strcmp (mips_arch_info->name, "r4400") == 0)
17107 target_flags |= MASK_FIX_R4400;
17109 /* Default to working around R10000 errata only if the processor
17110 was selected explicitly. */
17111 if ((target_flags_explicit & MASK_FIX_R10000) == 0
17112 && strcmp (mips_arch_info->name, "r10000") == 0)
17113 target_flags |= MASK_FIX_R10000;
17115 /* Make sure that branch-likely instructions available when using
17116 -mfix-r10000. The instructions are not available if either:
17118 1. -mno-branch-likely was passed.
17119 2. The selected ISA does not support branch-likely and
17120 the command line does not include -mbranch-likely. */
17121 if (TARGET_FIX_R10000
17122 && ((target_flags_explicit & MASK_BRANCHLIKELY) == 0
17123 ? !ISA_HAS_BRANCHLIKELY
17124 : !TARGET_BRANCHLIKELY))
17125 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
17127 if (TARGET_SYNCI && !ISA_HAS_SYNCI)
17129 warning (0, "the %qs architecture does not support the synci "
17130 "instruction", mips_arch_info->name);
17131 target_flags &= ~MASK_SYNCI;
17134 /* Only optimize PIC indirect calls if they are actually required. */
17135 if (!TARGET_USE_GOT || !TARGET_EXPLICIT_RELOCS)
17136 target_flags &= ~MASK_RELAX_PIC_CALLS;
17138 /* Save base state of options. */
17139 mips_base_target_flags = target_flags;
17140 mips_base_schedule_insns = flag_schedule_insns;
17141 mips_base_reorder_blocks_and_partition = flag_reorder_blocks_and_partition;
17142 mips_base_move_loop_invariants = flag_move_loop_invariants;
17143 mips_base_align_loops = align_loops;
17144 mips_base_align_jumps = align_jumps;
17145 mips_base_align_functions = align_functions;
17147 /* Now select the ISA mode.
17149 Do all CPP-sensitive stuff in uncompressed mode; we'll switch modes
17150 later if required. */
17151 mips_set_compression_mode (0);
17154 /* Swap the register information for registers I and I + 1, which
17155 currently have the wrong endianness. Note that the registers'
17156 fixedness and call-clobberedness might have been set on the
17160 mips_swap_registers (unsigned int i)
17165 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
17166 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
17168 SWAP_INT (fixed_regs[i], fixed_regs[i + 1]);
17169 SWAP_INT (call_used_regs[i], call_used_regs[i + 1]);
17170 SWAP_INT (call_really_used_regs[i], call_really_used_regs[i + 1]);
17171 SWAP_STRING (reg_names[i], reg_names[i + 1]);
17177 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
17180 mips_conditional_register_usage (void)
17185 /* These DSP control register fields are global. */
17186 global_regs[CCDSP_PO_REGNUM] = 1;
17187 global_regs[CCDSP_SC_REGNUM] = 1;
17190 AND_COMPL_HARD_REG_SET (accessible_reg_set,
17191 reg_class_contents[(int) DSP_ACC_REGS]);
17193 if (!TARGET_HARD_FLOAT)
17195 AND_COMPL_HARD_REG_SET (accessible_reg_set,
17196 reg_class_contents[(int) FP_REGS]);
17197 AND_COMPL_HARD_REG_SET (accessible_reg_set,
17198 reg_class_contents[(int) ST_REGS]);
17200 else if (!ISA_HAS_8CC)
17202 /* We only have a single condition-code register. We implement
17203 this by fixing all the condition-code registers and generating
17204 RTL that refers directly to ST_REG_FIRST. */
17205 AND_COMPL_HARD_REG_SET (accessible_reg_set,
17206 reg_class_contents[(int) ST_REGS]);
17207 SET_HARD_REG_BIT (accessible_reg_set, FPSW_REGNUM);
17208 fixed_regs[FPSW_REGNUM] = call_used_regs[FPSW_REGNUM] = 1;
17212 /* In MIPS16 mode, we permit the $t temporary registers to be used
17213 for reload. We prohibit the unused $s registers, since they
17214 are call-saved, and saving them via a MIPS16 register would
17215 probably waste more time than just reloading the value. */
17216 fixed_regs[18] = call_used_regs[18] = 1;
17217 fixed_regs[19] = call_used_regs[19] = 1;
17218 fixed_regs[20] = call_used_regs[20] = 1;
17219 fixed_regs[21] = call_used_regs[21] = 1;
17220 fixed_regs[22] = call_used_regs[22] = 1;
17221 fixed_regs[23] = call_used_regs[23] = 1;
17222 fixed_regs[26] = call_used_regs[26] = 1;
17223 fixed_regs[27] = call_used_regs[27] = 1;
17224 fixed_regs[30] = call_used_regs[30] = 1;
17226 /* Do not allow HI and LO to be treated as register operands.
17227 There are no MTHI or MTLO instructions (or any real need
17228 for them) and one-way registers cannot easily be reloaded. */
17229 AND_COMPL_HARD_REG_SET (operand_reg_set,
17230 reg_class_contents[(int) MD_REGS]);
17232 /* $f20-$f23 are call-clobbered for n64. */
17233 if (mips_abi == ABI_64)
17236 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
17237 call_really_used_regs[regno] = call_used_regs[regno] = 1;
17239 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
17241 if (mips_abi == ABI_N32)
17244 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
17245 call_really_used_regs[regno] = call_used_regs[regno] = 1;
17247 /* Make sure that double-register accumulator values are correctly
17248 ordered for the current endianness. */
17249 if (TARGET_LITTLE_ENDIAN)
17251 unsigned int regno;
17253 mips_swap_registers (MD_REG_FIRST);
17254 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno += 2)
17255 mips_swap_registers (regno);
17259 /* When generating MIPS16 code, we want to allocate $24 (T_REG) before
17260 other registers for instructions for which it is possible. This
17261 encourages the compiler to use CMP in cases where an XOR would
17262 require some register shuffling. */
17265 mips_order_regs_for_local_alloc (void)
17269 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
17270 reg_alloc_order[i] = i;
17274 /* It really doesn't matter where we put register 0, since it is
17275 a fixed register anyhow. */
17276 reg_alloc_order[0] = 24;
17277 reg_alloc_order[24] = 0;
17281 /* Implement EH_USES. */
17284 mips_eh_uses (unsigned int regno)
17286 if (reload_completed && !TARGET_ABSOLUTE_JUMPS)
17288 /* We need to force certain registers to be live in order to handle
17289 PIC long branches correctly. See mips_must_initialize_gp_p for
17291 if (mips_cfun_has_cprestore_slot_p ())
17293 if (regno == CPRESTORE_SLOT_REGNUM)
17298 if (cfun->machine->global_pointer == regno)
17306 /* Implement EPILOGUE_USES. */
17309 mips_epilogue_uses (unsigned int regno)
17311 /* Say that the epilogue uses the return address register. Note that
17312 in the case of sibcalls, the values "used by the epilogue" are
17313 considered live at the start of the called function. */
17314 if (regno == RETURN_ADDR_REGNUM)
17317 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
17318 See the comment above load_call<mode> for details. */
17319 if (TARGET_USE_GOT && (regno) == GOT_VERSION_REGNUM)
17322 /* An interrupt handler must preserve some registers that are
17323 ordinarily call-clobbered. */
17324 if (cfun->machine->interrupt_handler_p
17325 && mips_interrupt_extra_call_saved_reg_p (regno))
17331 /* A for_each_rtx callback. Stop the search if *X is an AT register. */
17334 mips_at_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
17336 return REG_P (*x) && REGNO (*x) == AT_REGNUM;
17339 /* Return true if INSN needs to be wrapped in ".set noat".
17340 INSN has NOPERANDS operands, stored in OPVEC. */
17343 mips_need_noat_wrapper_p (rtx insn, rtx *opvec, int noperands)
17347 if (recog_memoized (insn) >= 0)
17348 for (i = 0; i < noperands; i++)
17349 if (for_each_rtx (&opvec[i], mips_at_reg_p, NULL))
17354 /* Implement FINAL_PRESCAN_INSN. */
17357 mips_final_prescan_insn (rtx insn, rtx *opvec, int noperands)
17359 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
17360 mips_push_asm_switch (&mips_noat);
17363 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */
17366 mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED, rtx insn,
17367 rtx *opvec, int noperands)
17369 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
17370 mips_pop_asm_switch (&mips_noat);
17373 /* Return the function that is used to expand the <u>mulsidi3 pattern.
17374 EXT_CODE is the code of the extension used. Return NULL if widening
17375 multiplication shouldn't be used. */
17378 mips_mulsidi3_gen_fn (enum rtx_code ext_code)
17382 signed_p = ext_code == SIGN_EXTEND;
17385 /* Don't use widening multiplication with MULT when we have DMUL. Even
17386 with the extension of its input operands DMUL is faster. Note that
17387 the extension is not needed for signed multiplication. In order to
17388 ensure that we always remove the redundant sign-extension in this
17389 case we still expand mulsidi3 for DMUL. */
17391 return signed_p ? gen_mulsidi3_64bit_dmul : NULL;
17394 ? gen_mulsidi3_64bit_mips16
17395 : gen_umulsidi3_64bit_mips16);
17396 if (TARGET_FIX_R4000)
17398 return signed_p ? gen_mulsidi3_64bit : gen_umulsidi3_64bit;
17404 ? gen_mulsidi3_32bit_mips16
17405 : gen_umulsidi3_32bit_mips16);
17406 if (TARGET_FIX_R4000 && !ISA_HAS_DSP)
17407 return signed_p ? gen_mulsidi3_32bit_r4000 : gen_umulsidi3_32bit_r4000;
17408 return signed_p ? gen_mulsidi3_32bit : gen_umulsidi3_32bit;
17412 /* Return true if PATTERN matches the kind of instruction generated by
17413 umips_build_save_restore. SAVE_P is true for store. */
17416 umips_save_restore_pattern_p (bool save_p, rtx pattern)
17420 HOST_WIDE_INT first_offset = 0;
17421 rtx first_base = 0;
17422 unsigned int regmask = 0;
17424 for (n = 0; n < XVECLEN (pattern, 0); n++)
17426 rtx set, reg, mem, this_base;
17427 HOST_WIDE_INT this_offset;
17429 /* Check that we have a SET. */
17430 set = XVECEXP (pattern, 0, n);
17431 if (GET_CODE (set) != SET)
17434 /* Check that the SET is a load (if restoring) or a store
17436 mem = save_p ? SET_DEST (set) : SET_SRC (set);
17437 if (!MEM_P (mem) || MEM_VOLATILE_P (mem))
17440 /* Check that the address is the sum of base and a possibly-zero
17441 constant offset. Determine if the offset is in range. */
17442 mips_split_plus (XEXP (mem, 0), &this_base, &this_offset);
17443 if (!REG_P (this_base))
17448 if (!UMIPS_12BIT_OFFSET_P (this_offset))
17450 first_base = this_base;
17451 first_offset = this_offset;
17455 /* Check that the save slots are consecutive. */
17456 if (REGNO (this_base) != REGNO (first_base)
17457 || this_offset != first_offset + UNITS_PER_WORD * n)
17461 /* Check that SET's other operand is a register. */
17462 reg = save_p ? SET_SRC (set) : SET_DEST (set);
17466 regmask |= 1 << REGNO (reg);
17469 for (i = 0; i < ARRAY_SIZE (umips_swm_mask); i++)
17470 if (regmask == umips_swm_mask[i])
17476 /* Return the assembly instruction for microMIPS LWM or SWM.
17477 SAVE_P and PATTERN are as for umips_save_restore_pattern_p. */
17480 umips_output_save_restore (bool save_p, rtx pattern)
17482 static char buffer[300];
17485 HOST_WIDE_INT offset;
17486 rtx base, mem, set, last_set, last_reg;
17488 /* Parse the pattern. */
17489 gcc_assert (umips_save_restore_pattern_p (save_p, pattern));
17491 s = strcpy (buffer, save_p ? "swm\t" : "lwm\t");
17493 n = XVECLEN (pattern, 0);
17495 set = XVECEXP (pattern, 0, 0);
17496 mem = save_p ? SET_DEST (set) : SET_SRC (set);
17497 mips_split_plus (XEXP (mem, 0), &base, &offset);
17499 last_set = XVECEXP (pattern, 0, n - 1);
17500 last_reg = save_p ? SET_SRC (last_set) : SET_DEST (last_set);
17502 if (REGNO (last_reg) == 31)
17505 gcc_assert (n <= 9);
17509 s += sprintf (s, "%s,", reg_names[16]);
17511 s += sprintf (s, "%s-%s,", reg_names[16], reg_names[15 + n]);
17513 s += sprintf (s, "%s-%s,%s,", reg_names[16], reg_names[23],
17516 if (REGNO (last_reg) == 31)
17517 s += sprintf (s, "%s,", reg_names[31]);
17519 s += sprintf (s, "%d(%s)", (int)offset, reg_names[REGNO (base)]);
17523 /* Return true if MEM1 and MEM2 use the same base register, and the
17524 offset of MEM2 equals the offset of MEM1 plus 4. FIRST_REG is the
17525 register into (from) which the contents of MEM1 will be loaded
17526 (stored), depending on the value of LOAD_P.
17527 SWAP_P is true when the 1st and 2nd instructions are swapped. */
17530 umips_load_store_pair_p_1 (bool load_p, bool swap_p,
17531 rtx first_reg, rtx mem1, rtx mem2)
17534 HOST_WIDE_INT offset1, offset2;
17536 if (!MEM_P (mem1) || !MEM_P (mem2))
17539 mips_split_plus (XEXP (mem1, 0), &base1, &offset1);
17540 mips_split_plus (XEXP (mem2, 0), &base2, &offset2);
17542 if (!REG_P (base1) || !rtx_equal_p (base1, base2))
17545 /* Avoid invalid load pair instructions. */
17546 if (load_p && REGNO (first_reg) == REGNO (base1))
17549 /* We must avoid this case for anti-dependence.
17552 first_reg is $2, but the base is $3. */
17555 && REGNO (first_reg) + 1 == REGNO (base1))
17558 if (offset2 != offset1 + 4)
17561 if (!UMIPS_12BIT_OFFSET_P (offset1))
17567 /* OPERANDS describes the operands to a pair of SETs, in the order
17568 dest1, src1, dest2, src2. Return true if the operands can be used
17569 in an LWP or SWP instruction; LOAD_P says which. */
17572 umips_load_store_pair_p (bool load_p, rtx *operands)
17574 rtx reg1, reg2, mem1, mem2;
17578 reg1 = operands[0];
17579 reg2 = operands[2];
17580 mem1 = operands[1];
17581 mem2 = operands[3];
17585 reg1 = operands[1];
17586 reg2 = operands[3];
17587 mem1 = operands[0];
17588 mem2 = operands[2];
17591 if (REGNO (reg2) == REGNO (reg1) + 1)
17592 return umips_load_store_pair_p_1 (load_p, false, reg1, mem1, mem2);
17594 if (REGNO (reg1) == REGNO (reg2) + 1)
17595 return umips_load_store_pair_p_1 (load_p, true, reg2, mem2, mem1);
17600 /* Return the assembly instruction for a microMIPS LWP or SWP in which
17601 the first register is REG and the first memory slot is MEM.
17602 LOAD_P is true for LWP. */
17605 umips_output_load_store_pair_1 (bool load_p, rtx reg, rtx mem)
17607 rtx ops[] = {reg, mem};
17610 output_asm_insn ("lwp\t%0,%1", ops);
17612 output_asm_insn ("swp\t%0,%1", ops);
17615 /* Output the assembly instruction for a microMIPS LWP or SWP instruction.
17616 LOAD_P and OPERANDS are as for umips_load_store_pair_p. */
17619 umips_output_load_store_pair (bool load_p, rtx *operands)
17621 rtx reg1, reg2, mem1, mem2;
17624 reg1 = operands[0];
17625 reg2 = operands[2];
17626 mem1 = operands[1];
17627 mem2 = operands[3];
17631 reg1 = operands[1];
17632 reg2 = operands[3];
17633 mem1 = operands[0];
17634 mem2 = operands[2];
17637 if (REGNO (reg2) == REGNO (reg1) + 1)
17639 umips_output_load_store_pair_1 (load_p, reg1, mem1);
17643 gcc_assert (REGNO (reg1) == REGNO (reg2) + 1);
17644 umips_output_load_store_pair_1 (load_p, reg2, mem2);
17647 /* Return true if REG1 and REG2 match the criteria for a movep insn. */
17650 umips_movep_target_p (rtx reg1, rtx reg2)
17652 int regno1, regno2, pair;
17654 static const int match[8] = {
17655 0x00000060, /* 5, 6 */
17656 0x000000a0, /* 5, 7 */
17657 0x000000c0, /* 6, 7 */
17658 0x00200010, /* 4, 21 */
17659 0x00400010, /* 4, 22 */
17660 0x00000030, /* 4, 5 */
17661 0x00000050, /* 4, 6 */
17662 0x00000090 /* 4, 7 */
17665 if (!REG_P (reg1) || !REG_P (reg2))
17668 regno1 = REGNO (reg1);
17669 regno2 = REGNO (reg2);
17671 if (!GP_REG_P (regno1) || !GP_REG_P (regno2))
17674 pair = (1 << regno1) | (1 << regno2);
17676 for (i = 0; i < ARRAY_SIZE (match); i++)
17677 if (pair == match[i])
17683 /* Return the size in bytes of the trampoline code, padded to
17684 TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target
17685 function address immediately follow. */
17688 mips_trampoline_code_size (void)
17690 if (TARGET_USE_PIC_FN_ADDR_REG)
17692 else if (ptr_mode == DImode)
17694 else if (ISA_HAS_LOAD_DELAY)
17700 /* Implement TARGET_TRAMPOLINE_INIT. */
17703 mips_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
17705 rtx addr, end_addr, high, low, opcode, mem;
17708 HOST_WIDE_INT end_addr_offset, static_chain_offset, target_function_offset;
17710 /* Work out the offsets of the pointers from the start of the
17711 trampoline code. */
17712 end_addr_offset = mips_trampoline_code_size ();
17713 static_chain_offset = end_addr_offset;
17714 target_function_offset = static_chain_offset + GET_MODE_SIZE (ptr_mode);
17716 /* Get pointers to the beginning and end of the code block. */
17717 addr = force_reg (Pmode, XEXP (m_tramp, 0));
17718 end_addr = mips_force_binary (Pmode, PLUS, addr, GEN_INT (end_addr_offset));
17720 #define OP(X) gen_int_mode (X, SImode)
17722 /* Build up the code in TRAMPOLINE. */
17724 if (TARGET_USE_PIC_FN_ADDR_REG)
17726 /* $25 contains the address of the trampoline. Emit code of the form:
17728 l[wd] $1, target_function_offset($25)
17729 l[wd] $static_chain, static_chain_offset($25)
17732 trampoline[i++] = OP (MIPS_LOAD_PTR (AT_REGNUM,
17733 target_function_offset,
17734 PIC_FUNCTION_ADDR_REGNUM));
17735 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
17736 static_chain_offset,
17737 PIC_FUNCTION_ADDR_REGNUM));
17738 trampoline[i++] = OP (MIPS_JR (AT_REGNUM));
17739 trampoline[i++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM, AT_REGNUM));
17741 else if (ptr_mode == DImode)
17743 /* It's too cumbersome to create the full 64-bit address, so let's
17749 1: l[wd] $25, target_function_offset - 12($31)
17750 l[wd] $static_chain, static_chain_offset - 12($31)
17754 where 12 is the offset of "1:" from the start of the code block. */
17755 trampoline[i++] = OP (MIPS_MOVE (AT_REGNUM, RETURN_ADDR_REGNUM));
17756 trampoline[i++] = OP (MIPS_BAL (1));
17757 trampoline[i++] = OP (MIPS_NOP);
17758 trampoline[i++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
17759 target_function_offset - 12,
17760 RETURN_ADDR_REGNUM));
17761 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
17762 static_chain_offset - 12,
17763 RETURN_ADDR_REGNUM));
17764 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
17765 trampoline[i++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM, AT_REGNUM));
17769 /* If the target has load delays, emit:
17771 lui $1, %hi(end_addr)
17772 lw $25, %lo(end_addr + ...)($1)
17773 lw $static_chain, %lo(end_addr + ...)($1)
17779 lui $1, %hi(end_addr)
17780 lw $25, %lo(end_addr + ...)($1)
17782 lw $static_chain, %lo(end_addr + ...)($1). */
17784 /* Split END_ADDR into %hi and %lo values. Trampolines are aligned
17785 to 64 bits, so the %lo value will have the bottom 3 bits clear. */
17786 high = expand_simple_binop (SImode, PLUS, end_addr, GEN_INT (0x8000),
17787 NULL, false, OPTAB_WIDEN);
17788 high = expand_simple_binop (SImode, LSHIFTRT, high, GEN_INT (16),
17789 NULL, false, OPTAB_WIDEN);
17790 low = convert_to_mode (SImode, gen_lowpart (HImode, end_addr), true);
17792 /* Emit the LUI. */
17793 opcode = OP (MIPS_LUI (AT_REGNUM, 0));
17794 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, high,
17795 NULL, false, OPTAB_WIDEN);
17797 /* Emit the load of the target function. */
17798 opcode = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
17799 target_function_offset - end_addr_offset,
17801 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
17802 NULL, false, OPTAB_WIDEN);
17804 /* Emit the JR here, if we can. */
17805 if (!ISA_HAS_LOAD_DELAY)
17806 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
17808 /* Emit the load of the static chain register. */
17809 opcode = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
17810 static_chain_offset - end_addr_offset,
17812 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
17813 NULL, false, OPTAB_WIDEN);
17815 /* Emit the JR, if we couldn't above. */
17816 if (ISA_HAS_LOAD_DELAY)
17818 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
17819 trampoline[i++] = OP (MIPS_NOP);
17825 /* Copy the trampoline code. Leave any padding uninitialized. */
17826 for (j = 0; j < i; j++)
17828 mem = adjust_address (m_tramp, SImode, j * GET_MODE_SIZE (SImode));
17829 mips_emit_move (mem, trampoline[j]);
17832 /* Set up the static chain pointer field. */
17833 mem = adjust_address (m_tramp, ptr_mode, static_chain_offset);
17834 mips_emit_move (mem, chain_value);
17836 /* Set up the target function field. */
17837 mem = adjust_address (m_tramp, ptr_mode, target_function_offset);
17838 mips_emit_move (mem, XEXP (DECL_RTL (fndecl), 0));
17840 /* Flush the code part of the trampoline. */
17841 emit_insn (gen_add3_insn (end_addr, addr, GEN_INT (TRAMPOLINE_SIZE)));
17842 emit_insn (gen_clear_cache (addr, end_addr));
17845 /* Implement FUNCTION_PROFILER. */
17847 void mips_function_profiler (FILE *file)
17850 sorry ("mips16 function profiling");
17851 if (TARGET_LONG_CALLS)
17853 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */
17854 if (Pmode == DImode)
17855 fprintf (file, "\tdla\t%s,_mcount\n", reg_names[3]);
17857 fprintf (file, "\tla\t%s,_mcount\n", reg_names[3]);
17859 mips_push_asm_switch (&mips_noat);
17860 fprintf (file, "\tmove\t%s,%s\t\t# save current return address\n",
17861 reg_names[AT_REGNUM], reg_names[RETURN_ADDR_REGNUM]);
17862 /* _mcount treats $2 as the static chain register. */
17863 if (cfun->static_chain_decl != NULL)
17864 fprintf (file, "\tmove\t%s,%s\n", reg_names[2],
17865 reg_names[STATIC_CHAIN_REGNUM]);
17866 if (TARGET_MCOUNT_RA_ADDRESS)
17868 /* If TARGET_MCOUNT_RA_ADDRESS load $12 with the address of the
17869 ra save location. */
17870 if (cfun->machine->frame.ra_fp_offset == 0)
17871 /* ra not saved, pass zero. */
17872 fprintf (file, "\tmove\t%s,%s\n", reg_names[12], reg_names[0]);
17874 fprintf (file, "\t%s\t%s," HOST_WIDE_INT_PRINT_DEC "(%s)\n",
17875 Pmode == DImode ? "dla" : "la", reg_names[12],
17876 cfun->machine->frame.ra_fp_offset,
17877 reg_names[STACK_POINTER_REGNUM]);
17879 if (!TARGET_NEWABI)
17881 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n",
17882 TARGET_64BIT ? "dsubu" : "subu",
17883 reg_names[STACK_POINTER_REGNUM],
17884 reg_names[STACK_POINTER_REGNUM],
17885 Pmode == DImode ? 16 : 8);
17887 if (TARGET_LONG_CALLS)
17888 fprintf (file, "\tjalr\t%s\n", reg_names[3]);
17890 fprintf (file, "\tjal\t_mcount\n");
17891 mips_pop_asm_switch (&mips_noat);
17892 /* _mcount treats $2 as the static chain register. */
17893 if (cfun->static_chain_decl != NULL)
17894 fprintf (file, "\tmove\t%s,%s\n", reg_names[STATIC_CHAIN_REGNUM],
17898 /* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default
17899 behaviour of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even
17900 when TARGET_LOONGSON_VECTORS is true. */
17902 static unsigned HOST_WIDE_INT
17903 mips_shift_truncation_mask (enum machine_mode mode)
17905 if (TARGET_LOONGSON_VECTORS && VECTOR_MODE_P (mode))
17908 return GET_MODE_BITSIZE (mode) - 1;
17911 /* Implement TARGET_PREPARE_PCH_SAVE. */
17914 mips_prepare_pch_save (void)
17916 /* We are called in a context where the current MIPS16 vs. non-MIPS16
17917 setting should be irrelevant. The question then is: which setting
17918 makes most sense at load time?
17920 The PCH is loaded before the first token is read. We should never
17921 have switched into MIPS16 mode by that point, and thus should not
17922 have populated mips16_globals. Nor can we load the entire contents
17923 of mips16_globals from the PCH file, because mips16_globals contains
17924 a combination of GGC and non-GGC data.
17926 There is therefore no point in trying save the GGC part of
17927 mips16_globals to the PCH file, or to preserve MIPS16ness across
17928 the PCH save and load. The loading compiler would not have access
17929 to the non-GGC parts of mips16_globals (either from the PCH file,
17930 or from a copy that the loading compiler generated itself) and would
17931 have to call target_reinit anyway.
17933 It therefore seems best to switch back to non-MIPS16 mode at
17934 save time, and to ensure that mips16_globals remains null after
17936 mips_set_compression_mode (0);
17937 mips16_globals = 0;
17940 /* Generate or test for an insn that supports a constant permutation. */
17942 #define MAX_VECT_LEN 8
17944 struct expand_vec_perm_d
17946 rtx target, op0, op1;
17947 unsigned char perm[MAX_VECT_LEN];
17948 enum machine_mode vmode;
17949 unsigned char nelt;
17954 /* Construct (set target (vec_select op0 (parallel perm))) and
17955 return true if that's a valid instruction in the active ISA. */
17958 mips_expand_vselect (rtx target, rtx op0,
17959 const unsigned char *perm, unsigned nelt)
17961 rtx rperm[MAX_VECT_LEN], x;
17964 for (i = 0; i < nelt; ++i)
17965 rperm[i] = GEN_INT (perm[i]);
17967 x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (nelt, rperm));
17968 x = gen_rtx_VEC_SELECT (GET_MODE (target), op0, x);
17969 x = gen_rtx_SET (VOIDmode, target, x);
17972 if (recog_memoized (x) < 0)
17980 /* Similar, but generate a vec_concat from op0 and op1 as well. */
17983 mips_expand_vselect_vconcat (rtx target, rtx op0, rtx op1,
17984 const unsigned char *perm, unsigned nelt)
17986 enum machine_mode v2mode;
17989 v2mode = GET_MODE_2XWIDER_MODE (GET_MODE (op0));
17990 x = gen_rtx_VEC_CONCAT (v2mode, op0, op1);
17991 return mips_expand_vselect (target, x, perm, nelt);
17994 /* Recognize patterns for even-odd extraction. */
17997 mips_expand_vpc_loongson_even_odd (struct expand_vec_perm_d *d)
17999 unsigned i, odd, nelt = d->nelt;
18000 rtx t0, t1, t2, t3;
18002 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
18004 /* Even-odd for V2SI/V2SFmode is matched by interleave directly. */
18011 for (i = 1; i < nelt; ++i)
18012 if (d->perm[i] != i * 2 + odd)
18018 /* We need 2*log2(N)-1 operations to achieve odd/even with interleave. */
18019 t0 = gen_reg_rtx (d->vmode);
18020 t1 = gen_reg_rtx (d->vmode);
18024 emit_insn (gen_loongson_punpckhhw (t0, d->op0, d->op1));
18025 emit_insn (gen_loongson_punpcklhw (t1, d->op0, d->op1));
18027 emit_insn (gen_loongson_punpckhhw (d->target, t1, t0));
18029 emit_insn (gen_loongson_punpcklhw (d->target, t1, t0));
18033 t2 = gen_reg_rtx (d->vmode);
18034 t3 = gen_reg_rtx (d->vmode);
18035 emit_insn (gen_loongson_punpckhbh (t0, d->op0, d->op1));
18036 emit_insn (gen_loongson_punpcklbh (t1, d->op0, d->op1));
18037 emit_insn (gen_loongson_punpckhbh (t2, t1, t0));
18038 emit_insn (gen_loongson_punpcklbh (t3, t1, t0));
18040 emit_insn (gen_loongson_punpckhbh (d->target, t3, t2));
18042 emit_insn (gen_loongson_punpcklbh (d->target, t3, t2));
18046 gcc_unreachable ();
18051 /* Recognize patterns for the Loongson PSHUFH instruction. */
18054 mips_expand_vpc_loongson_pshufh (struct expand_vec_perm_d *d)
18059 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
18061 if (d->vmode != V4HImode)
18066 /* Convert the selector into the packed 8-bit form for pshufh. */
18067 /* Recall that loongson is little-endian only. No big-endian
18068 adjustment required. */
18069 for (i = mask = 0; i < 4; i++)
18070 mask |= (d->perm[i] & 3) << (i * 2);
18071 rmask = force_reg (SImode, GEN_INT (mask));
18073 if (d->one_vector_p)
18074 emit_insn (gen_loongson_pshufh (d->target, d->op0, rmask));
18077 rtx t0, t1, x, merge, rmerge[4];
18079 t0 = gen_reg_rtx (V4HImode);
18080 t1 = gen_reg_rtx (V4HImode);
18081 emit_insn (gen_loongson_pshufh (t1, d->op1, rmask));
18082 emit_insn (gen_loongson_pshufh (t0, d->op0, rmask));
18084 for (i = 0; i < 4; ++i)
18085 rmerge[i] = (d->perm[i] & 4 ? constm1_rtx : const0_rtx);
18086 merge = gen_rtx_CONST_VECTOR (V4HImode, gen_rtvec_v (4, rmerge));
18087 merge = force_reg (V4HImode, merge);
18089 x = gen_rtx_AND (V4HImode, merge, t1);
18090 emit_insn (gen_rtx_SET (VOIDmode, t1, x));
18092 x = gen_rtx_NOT (V4HImode, merge);
18093 x = gen_rtx_AND (V4HImode, x, t0);
18094 emit_insn (gen_rtx_SET (VOIDmode, t0, x));
18096 x = gen_rtx_IOR (V4HImode, t0, t1);
18097 emit_insn (gen_rtx_SET (VOIDmode, d->target, x));
18103 /* Recognize broadcast patterns for the Loongson. */
18106 mips_expand_vpc_loongson_bcast (struct expand_vec_perm_d *d)
18111 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
18113 /* Note that we've already matched V2SI via punpck and V4HI via pshufh. */
18114 if (d->vmode != V8QImode)
18116 if (!d->one_vector_p)
18120 for (i = 1; i < 8; ++i)
18121 if (d->perm[i] != elt)
18127 /* With one interleave we put two of the desired element adjacent. */
18128 t0 = gen_reg_rtx (V8QImode);
18130 emit_insn (gen_loongson_punpcklbh (t0, d->op0, d->op0));
18132 emit_insn (gen_loongson_punpckhbh (t0, d->op0, d->op0));
18134 /* Shuffle that one HImode element into all locations. */
18137 t1 = gen_reg_rtx (V4HImode);
18138 emit_insn (gen_loongson_pshufh (t1, gen_lowpart (V4HImode, t0),
18139 force_reg (SImode, GEN_INT (elt))));
18141 emit_move_insn (d->target, gen_lowpart (V8QImode, t1));
18146 mips_expand_vec_perm_const_1 (struct expand_vec_perm_d *d)
18148 unsigned int i, nelt = d->nelt;
18149 unsigned char perm2[MAX_VECT_LEN];
18151 if (d->one_vector_p)
18153 /* Try interleave with alternating operands. */
18154 memcpy (perm2, d->perm, sizeof(perm2));
18155 for (i = 1; i < nelt; i += 2)
18157 if (mips_expand_vselect_vconcat (d->target, d->op0, d->op1, perm2, nelt))
18162 if (mips_expand_vselect_vconcat (d->target, d->op0, d->op1,
18166 /* Try again with swapped operands. */
18167 for (i = 0; i < nelt; ++i)
18168 perm2[i] = (d->perm[i] + nelt) & (2 * nelt - 1);
18169 if (mips_expand_vselect_vconcat (d->target, d->op1, d->op0, perm2, nelt))
18173 if (mips_expand_vpc_loongson_even_odd (d))
18175 if (mips_expand_vpc_loongson_pshufh (d))
18177 if (mips_expand_vpc_loongson_bcast (d))
18182 /* Expand a vec_perm_const pattern. */
18185 mips_expand_vec_perm_const (rtx operands[4])
18187 struct expand_vec_perm_d d;
18188 int i, nelt, which;
18189 unsigned char orig_perm[MAX_VECT_LEN];
18193 d.target = operands[0];
18194 d.op0 = operands[1];
18195 d.op1 = operands[2];
18198 d.vmode = GET_MODE (d.target);
18199 gcc_assert (VECTOR_MODE_P (d.vmode));
18200 d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
18201 d.testing_p = false;
18203 for (i = which = 0; i < nelt; ++i)
18205 rtx e = XVECEXP (sel, 0, i);
18206 int ei = INTVAL (e) & (2 * nelt - 1);
18207 which |= (ei < nelt ? 1 : 2);
18210 memcpy (d.perm, orig_perm, MAX_VECT_LEN);
18218 d.one_vector_p = false;
18219 if (!rtx_equal_p (d.op0, d.op1))
18224 for (i = 0; i < nelt; ++i)
18225 d.perm[i] &= nelt - 1;
18227 d.one_vector_p = true;
18232 d.one_vector_p = true;
18236 ok = mips_expand_vec_perm_const_1 (&d);
18238 /* If we were given a two-vector permutation which just happened to
18239 have both input vectors equal, we folded this into a one-vector
18240 permutation. There are several loongson patterns that are matched
18241 via direct vec_select+vec_concat expansion, but we do not have
18242 support in mips_expand_vec_perm_const_1 to guess the adjustment
18243 that should be made for a single operand. Just try again with
18244 the original permutation. */
18245 if (!ok && which == 3)
18247 d.op0 = operands[1];
18248 d.op1 = operands[2];
18249 d.one_vector_p = false;
18250 memcpy (d.perm, orig_perm, MAX_VECT_LEN);
18251 ok = mips_expand_vec_perm_const_1 (&d);
18257 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST_OK. */
18260 mips_vectorize_vec_perm_const_ok (enum machine_mode vmode,
18261 const unsigned char *sel)
18263 struct expand_vec_perm_d d;
18264 unsigned int i, nelt, which;
18268 d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
18269 d.testing_p = true;
18270 memcpy (d.perm, sel, nelt);
18272 /* Categorize the set of elements in the selector. */
18273 for (i = which = 0; i < nelt; ++i)
18275 unsigned char e = d.perm[i];
18276 gcc_assert (e < 2 * nelt);
18277 which |= (e < nelt ? 1 : 2);
18280 /* For all elements from second vector, fold the elements to first. */
18282 for (i = 0; i < nelt; ++i)
18285 /* Check whether the mask can be applied to the vector type. */
18286 d.one_vector_p = (which != 3);
18288 d.target = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 1);
18289 d.op1 = d.op0 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 2);
18290 if (!d.one_vector_p)
18291 d.op1 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 3);
18294 ret = mips_expand_vec_perm_const_1 (&d);
18300 /* Expand an integral vector unpack operation. */
18303 mips_expand_vec_unpack (rtx operands[2], bool unsigned_p, bool high_p)
18305 enum machine_mode imode = GET_MODE (operands[1]);
18306 rtx (*unpack) (rtx, rtx, rtx);
18307 rtx (*cmpgt) (rtx, rtx, rtx);
18308 rtx tmp, dest, zero;
18314 unpack = gen_loongson_punpckhbh;
18316 unpack = gen_loongson_punpcklbh;
18317 cmpgt = gen_loongson_pcmpgtb;
18321 unpack = gen_loongson_punpckhhw;
18323 unpack = gen_loongson_punpcklhw;
18324 cmpgt = gen_loongson_pcmpgth;
18327 gcc_unreachable ();
18330 zero = force_reg (imode, CONST0_RTX (imode));
18335 tmp = gen_reg_rtx (imode);
18336 emit_insn (cmpgt (tmp, zero, operands[1]));
18339 dest = gen_reg_rtx (imode);
18340 emit_insn (unpack (dest, operands[1], tmp));
18342 emit_move_insn (operands[0], gen_lowpart (GET_MODE (operands[0]), dest));
18345 /* A subroutine of mips_expand_vec_init, match constant vector elements. */
18348 mips_constant_elt_p (rtx x)
18350 return CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE;
18353 /* A subroutine of mips_expand_vec_init, expand via broadcast. */
18356 mips_expand_vi_broadcast (enum machine_mode vmode, rtx target, rtx elt)
18358 struct expand_vec_perm_d d;
18362 if (elt != const0_rtx)
18363 elt = force_reg (GET_MODE_INNER (vmode), elt);
18365 elt = gen_lowpart (DImode, elt);
18367 t1 = gen_reg_rtx (vmode);
18371 emit_insn (gen_loongson_vec_init1_v8qi (t1, elt));
18374 emit_insn (gen_loongson_vec_init1_v4hi (t1, elt));
18377 gcc_unreachable ();
18380 memset (&d, 0, sizeof (d));
18385 d.nelt = GET_MODE_NUNITS (vmode);
18386 d.one_vector_p = true;
18388 ok = mips_expand_vec_perm_const_1 (&d);
18392 /* A subroutine of mips_expand_vec_init, replacing all of the non-constant
18393 elements of VALS with zeros, copy the constant vector to TARGET. */
18396 mips_expand_vi_constant (enum machine_mode vmode, unsigned nelt,
18397 rtx target, rtx vals)
18399 rtvec vec = shallow_copy_rtvec (XVEC (vals, 0));
18402 for (i = 0; i < nelt; ++i)
18404 if (!mips_constant_elt_p (RTVEC_ELT (vec, i)))
18405 RTVEC_ELT (vec, i) = const0_rtx;
18408 emit_move_insn (target, gen_rtx_CONST_VECTOR (vmode, vec));
18412 /* A subroutine of mips_expand_vec_init, expand via pinsrh. */
18415 mips_expand_vi_loongson_one_pinsrh (rtx target, rtx vals, unsigned one_var)
18417 mips_expand_vi_constant (V4HImode, 4, target, vals);
18419 emit_insn (gen_vec_setv4hi (target, target, XVECEXP (vals, 0, one_var),
18420 GEN_INT (one_var)));
18423 /* A subroutine of mips_expand_vec_init, expand anything via memory. */
18426 mips_expand_vi_general (enum machine_mode vmode, enum machine_mode imode,
18427 unsigned nelt, unsigned nvar, rtx target, rtx vals)
18429 rtx mem = assign_stack_temp (vmode, GET_MODE_SIZE (vmode));
18430 unsigned int i, isize = GET_MODE_SIZE (imode);
18433 mips_expand_vi_constant (vmode, nelt, mem, vals);
18435 for (i = 0; i < nelt; ++i)
18437 rtx x = XVECEXP (vals, 0, i);
18438 if (!mips_constant_elt_p (x))
18439 emit_move_insn (adjust_address (mem, imode, i * isize), x);
18442 emit_move_insn (target, mem);
18445 /* Expand a vector initialization. */
18448 mips_expand_vector_init (rtx target, rtx vals)
18450 enum machine_mode vmode = GET_MODE (target);
18451 enum machine_mode imode = GET_MODE_INNER (vmode);
18452 unsigned i, nelt = GET_MODE_NUNITS (vmode);
18453 unsigned nvar = 0, one_var = -1u;
18454 bool all_same = true;
18457 for (i = 0; i < nelt; ++i)
18459 x = XVECEXP (vals, 0, i);
18460 if (!mips_constant_elt_p (x))
18461 nvar++, one_var = i;
18462 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
18466 /* Load constants from the pool, or whatever's handy. */
18469 emit_move_insn (target, gen_rtx_CONST_VECTOR (vmode, XVEC (vals, 0)));
18473 /* For two-part initialization, always use CONCAT. */
18476 rtx op0 = force_reg (imode, XVECEXP (vals, 0, 0));
18477 rtx op1 = force_reg (imode, XVECEXP (vals, 0, 1));
18478 x = gen_rtx_VEC_CONCAT (vmode, op0, op1);
18479 emit_insn (gen_rtx_SET (VOIDmode, target, x));
18483 /* Loongson is the only cpu with vectors with more elements. */
18484 gcc_assert (TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS);
18486 /* If all values are identical, broadcast the value. */
18489 mips_expand_vi_broadcast (vmode, target, XVECEXP (vals, 0, 0));
18493 /* If we've only got one non-variable V4HImode, use PINSRH. */
18494 if (nvar == 1 && vmode == V4HImode)
18496 mips_expand_vi_loongson_one_pinsrh (target, vals, one_var);
18500 mips_expand_vi_general (vmode, imode, nelt, nvar, target, vals);
18503 /* Expand a vector reduction. */
18506 mips_expand_vec_reduc (rtx target, rtx in, rtx (*gen)(rtx, rtx, rtx))
18508 enum machine_mode vmode = GET_MODE (in);
18509 unsigned char perm2[2];
18510 rtx last, next, fold, x;
18514 fold = gen_reg_rtx (vmode);
18518 /* Use PUL/PLU to produce { L, H } op { H, L }.
18519 By reversing the pair order, rather than a pure interleave high,
18520 we avoid erroneous exceptional conditions that we might otherwise
18521 produce from the computation of H op H. */
18524 ok = mips_expand_vselect_vconcat (fold, last, last, perm2, 2);
18529 /* Use interleave to produce { H, L } op { H, H }. */
18530 emit_insn (gen_loongson_punpckhwd (fold, last, last));
18534 /* Perform the first reduction with interleave,
18535 and subsequent reductions with shifts. */
18536 emit_insn (gen_loongson_punpckhwd_hi (fold, last, last));
18538 next = gen_reg_rtx (vmode);
18539 emit_insn (gen (next, last, fold));
18542 fold = gen_reg_rtx (vmode);
18543 x = force_reg (SImode, GEN_INT (16));
18544 emit_insn (gen_vec_shr_v4hi (fold, last, x));
18548 emit_insn (gen_loongson_punpckhwd_qi (fold, last, last));
18550 next = gen_reg_rtx (vmode);
18551 emit_insn (gen (next, last, fold));
18554 fold = gen_reg_rtx (vmode);
18555 x = force_reg (SImode, GEN_INT (16));
18556 emit_insn (gen_vec_shr_v8qi (fold, last, x));
18558 next = gen_reg_rtx (vmode);
18559 emit_insn (gen (next, last, fold));
18562 fold = gen_reg_rtx (vmode);
18563 x = force_reg (SImode, GEN_INT (8));
18564 emit_insn (gen_vec_shr_v8qi (fold, last, x));
18568 gcc_unreachable ();
18571 emit_insn (gen (target, last, fold));
18574 /* Expand a vector minimum/maximum. */
18577 mips_expand_vec_minmax (rtx target, rtx op0, rtx op1,
18578 rtx (*cmp) (rtx, rtx, rtx), bool min_p)
18580 enum machine_mode vmode = GET_MODE (target);
18583 tc = gen_reg_rtx (vmode);
18584 t0 = gen_reg_rtx (vmode);
18585 t1 = gen_reg_rtx (vmode);
18588 emit_insn (cmp (tc, op0, op1));
18590 x = gen_rtx_AND (vmode, tc, (min_p ? op1 : op0));
18591 emit_insn (gen_rtx_SET (VOIDmode, t0, x));
18593 x = gen_rtx_NOT (vmode, tc);
18594 x = gen_rtx_AND (vmode, x, (min_p ? op0 : op1));
18595 emit_insn (gen_rtx_SET (VOIDmode, t1, x));
18597 x = gen_rtx_IOR (vmode, t0, t1);
18598 emit_insn (gen_rtx_SET (VOIDmode, target, x));
18601 /* Initialize the GCC target structure. */
18602 #undef TARGET_ASM_ALIGNED_HI_OP
18603 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
18604 #undef TARGET_ASM_ALIGNED_SI_OP
18605 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
18606 #undef TARGET_ASM_ALIGNED_DI_OP
18607 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
18609 #undef TARGET_OPTION_OVERRIDE
18610 #define TARGET_OPTION_OVERRIDE mips_option_override
18612 #undef TARGET_LEGITIMIZE_ADDRESS
18613 #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
18615 #undef TARGET_ASM_FUNCTION_PROLOGUE
18616 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
18617 #undef TARGET_ASM_FUNCTION_EPILOGUE
18618 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
18619 #undef TARGET_ASM_SELECT_RTX_SECTION
18620 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
18621 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
18622 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
18624 #undef TARGET_SCHED_INIT
18625 #define TARGET_SCHED_INIT mips_sched_init
18626 #undef TARGET_SCHED_REORDER
18627 #define TARGET_SCHED_REORDER mips_sched_reorder
18628 #undef TARGET_SCHED_REORDER2
18629 #define TARGET_SCHED_REORDER2 mips_sched_reorder2
18630 #undef TARGET_SCHED_VARIABLE_ISSUE
18631 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
18632 #undef TARGET_SCHED_ADJUST_COST
18633 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
18634 #undef TARGET_SCHED_ISSUE_RATE
18635 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
18636 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
18637 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
18638 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
18639 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
18640 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
18641 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
18642 mips_multipass_dfa_lookahead
18643 #undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
18644 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
18645 mips_small_register_classes_for_mode_p
18647 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
18648 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
18650 #undef TARGET_INSERT_ATTRIBUTES
18651 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
18652 #undef TARGET_MERGE_DECL_ATTRIBUTES
18653 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
18654 #undef TARGET_SET_CURRENT_FUNCTION
18655 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
18657 #undef TARGET_VALID_POINTER_MODE
18658 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
18659 #undef TARGET_REGISTER_MOVE_COST
18660 #define TARGET_REGISTER_MOVE_COST mips_register_move_cost
18661 #undef TARGET_MEMORY_MOVE_COST
18662 #define TARGET_MEMORY_MOVE_COST mips_memory_move_cost
18663 #undef TARGET_RTX_COSTS
18664 #define TARGET_RTX_COSTS mips_rtx_costs
18665 #undef TARGET_ADDRESS_COST
18666 #define TARGET_ADDRESS_COST mips_address_cost
18668 #undef TARGET_IN_SMALL_DATA_P
18669 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
18671 #undef TARGET_MACHINE_DEPENDENT_REORG
18672 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
18674 #undef TARGET_PREFERRED_RELOAD_CLASS
18675 #define TARGET_PREFERRED_RELOAD_CLASS mips_preferred_reload_class
18677 #undef TARGET_EXPAND_TO_RTL_HOOK
18678 #define TARGET_EXPAND_TO_RTL_HOOK mips_expand_to_rtl_hook
18679 #undef TARGET_ASM_FILE_START
18680 #define TARGET_ASM_FILE_START mips_file_start
18681 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
18682 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
18683 #undef TARGET_ASM_CODE_END
18684 #define TARGET_ASM_CODE_END mips_code_end
18686 #undef TARGET_INIT_LIBFUNCS
18687 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
18689 #undef TARGET_BUILD_BUILTIN_VA_LIST
18690 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
18691 #undef TARGET_EXPAND_BUILTIN_VA_START
18692 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
18693 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
18694 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
18696 #undef TARGET_PROMOTE_FUNCTION_MODE
18697 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
18698 #undef TARGET_PROMOTE_PROTOTYPES
18699 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
18701 #undef TARGET_FUNCTION_VALUE
18702 #define TARGET_FUNCTION_VALUE mips_function_value
18703 #undef TARGET_LIBCALL_VALUE
18704 #define TARGET_LIBCALL_VALUE mips_libcall_value
18705 #undef TARGET_FUNCTION_VALUE_REGNO_P
18706 #define TARGET_FUNCTION_VALUE_REGNO_P mips_function_value_regno_p
18707 #undef TARGET_RETURN_IN_MEMORY
18708 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
18709 #undef TARGET_RETURN_IN_MSB
18710 #define TARGET_RETURN_IN_MSB mips_return_in_msb
18712 #undef TARGET_ASM_OUTPUT_MI_THUNK
18713 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
18714 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
18715 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
18717 #undef TARGET_PRINT_OPERAND
18718 #define TARGET_PRINT_OPERAND mips_print_operand
18719 #undef TARGET_PRINT_OPERAND_ADDRESS
18720 #define TARGET_PRINT_OPERAND_ADDRESS mips_print_operand_address
18721 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
18722 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mips_print_operand_punct_valid_p
18724 #undef TARGET_SETUP_INCOMING_VARARGS
18725 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
18726 #undef TARGET_STRICT_ARGUMENT_NAMING
18727 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
18728 #undef TARGET_MUST_PASS_IN_STACK
18729 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
18730 #undef TARGET_PASS_BY_REFERENCE
18731 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
18732 #undef TARGET_CALLEE_COPIES
18733 #define TARGET_CALLEE_COPIES mips_callee_copies
18734 #undef TARGET_ARG_PARTIAL_BYTES
18735 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
18736 #undef TARGET_FUNCTION_ARG
18737 #define TARGET_FUNCTION_ARG mips_function_arg
18738 #undef TARGET_FUNCTION_ARG_ADVANCE
18739 #define TARGET_FUNCTION_ARG_ADVANCE mips_function_arg_advance
18740 #undef TARGET_FUNCTION_ARG_BOUNDARY
18741 #define TARGET_FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
18743 #undef TARGET_MODE_REP_EXTENDED
18744 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
18746 #undef TARGET_VECTOR_MODE_SUPPORTED_P
18747 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
18749 #undef TARGET_SCALAR_MODE_SUPPORTED_P
18750 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
18752 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
18753 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE mips_preferred_simd_mode
18755 #undef TARGET_INIT_BUILTINS
18756 #define TARGET_INIT_BUILTINS mips_init_builtins
18757 #undef TARGET_BUILTIN_DECL
18758 #define TARGET_BUILTIN_DECL mips_builtin_decl
18759 #undef TARGET_EXPAND_BUILTIN
18760 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
18762 #undef TARGET_HAVE_TLS
18763 #define TARGET_HAVE_TLS HAVE_AS_TLS
18765 #undef TARGET_CANNOT_FORCE_CONST_MEM
18766 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
18768 #undef TARGET_LEGITIMATE_CONSTANT_P
18769 #define TARGET_LEGITIMATE_CONSTANT_P mips_legitimate_constant_p
18771 #undef TARGET_ENCODE_SECTION_INFO
18772 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
18774 #undef TARGET_ATTRIBUTE_TABLE
18775 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
18776 /* All our function attributes are related to how out-of-line copies should
18777 be compiled or called. They don't in themselves prevent inlining. */
18778 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
18779 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
18781 #undef TARGET_EXTRA_LIVE_ON_ENTRY
18782 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
18784 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
18785 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
18786 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
18787 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
18789 #undef TARGET_COMP_TYPE_ATTRIBUTES
18790 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
18792 #ifdef HAVE_AS_DTPRELWORD
18793 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
18794 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
18796 #undef TARGET_DWARF_REGISTER_SPAN
18797 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
18799 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
18800 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
18802 #undef TARGET_LEGITIMATE_ADDRESS_P
18803 #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p
18805 #undef TARGET_FRAME_POINTER_REQUIRED
18806 #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required
18808 #undef TARGET_CAN_ELIMINATE
18809 #define TARGET_CAN_ELIMINATE mips_can_eliminate
18811 #undef TARGET_CONDITIONAL_REGISTER_USAGE
18812 #define TARGET_CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage
18814 #undef TARGET_TRAMPOLINE_INIT
18815 #define TARGET_TRAMPOLINE_INIT mips_trampoline_init
18817 #undef TARGET_ASM_OUTPUT_SOURCE_FILENAME
18818 #define TARGET_ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
18820 #undef TARGET_SHIFT_TRUNCATION_MASK
18821 #define TARGET_SHIFT_TRUNCATION_MASK mips_shift_truncation_mask
18823 #undef TARGET_PREPARE_PCH_SAVE
18824 #define TARGET_PREPARE_PCH_SAVE mips_prepare_pch_save
18826 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
18827 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK mips_vectorize_vec_perm_const_ok
18829 struct gcc_target targetm = TARGET_INITIALIZER;
18831 #include "gt-mips.h"