1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
5 Free Software Foundation, Inc.
6 Contributed by A. Lichnewsky, lich@inria.inria.fr.
7 Changes by Michael Meissner, meissner@osf.org.
8 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
9 Brendan Eich, brendan@microunity.com.
11 This file is part of GCC.
13 GCC is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GCC is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GCC; see the file COPYING3. If not see
25 <http://www.gnu.org/licenses/>. */
29 #include "coretypes.h"
33 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
36 #include "insn-attr.h"
52 #include "target-def.h"
53 #include "common/common-target.h"
54 #include "langhooks.h"
55 #include "sched-int.h"
58 #include "diagnostic.h"
59 #include "target-globals.h"
62 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
63 #define UNSPEC_ADDRESS_P(X) \
64 (GET_CODE (X) == UNSPEC \
65 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
66 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
68 /* Extract the symbol or label from UNSPEC wrapper X. */
69 #define UNSPEC_ADDRESS(X) \
72 /* Extract the symbol type from UNSPEC wrapper X. */
73 #define UNSPEC_ADDRESS_TYPE(X) \
74 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
76 /* The maximum distance between the top of the stack frame and the
77 value $sp has when we save and restore registers.
79 The value for normal-mode code must be a SMALL_OPERAND and must
80 preserve the maximum stack alignment. We therefore use a value
81 of 0x7ff0 in this case.
83 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
84 up to 0x7f8 bytes and can usually save or restore all the registers
85 that we need to save or restore. (Note that we can only use these
86 instructions for o32, for which the stack alignment is 8 bytes.)
88 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
89 RESTORE are not available. We can then use unextended instructions
90 to save and restore registers, and to allocate and deallocate the top
92 #define MIPS_MAX_FIRST_STACK_STEP \
93 (!TARGET_MIPS16 ? 0x7ff0 \
94 : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
95 : TARGET_64BIT ? 0x100 : 0x400)
97 /* True if INSN is a mips.md pattern or asm statement. */
98 #define USEFUL_INSN_P(INSN) \
99 (NONDEBUG_INSN_P (INSN) \
100 && GET_CODE (PATTERN (INSN)) != USE \
101 && GET_CODE (PATTERN (INSN)) != CLOBBER \
102 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
103 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
105 /* If INSN is a delayed branch sequence, return the first instruction
106 in the sequence, otherwise return INSN itself. */
107 #define SEQ_BEGIN(INSN) \
108 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
109 ? XVECEXP (PATTERN (INSN), 0, 0) \
112 /* Likewise for the last instruction in a delayed branch sequence. */
113 #define SEQ_END(INSN) \
114 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
115 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
118 /* Execute the following loop body with SUBINSN set to each instruction
119 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
120 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
121 for ((SUBINSN) = SEQ_BEGIN (INSN); \
122 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
123 (SUBINSN) = NEXT_INSN (SUBINSN))
125 /* True if bit BIT is set in VALUE. */
126 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
128 /* Return the opcode for a ptr_mode load of the form:
130 l[wd] DEST, OFFSET(BASE). */
131 #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \
132 (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \
137 /* Return the opcode to move register SRC into register DEST. */
138 #define MIPS_MOVE(DEST, SRC) \
139 ((TARGET_64BIT ? 0x2d : 0x21) \
143 /* Return the opcode for:
146 #define MIPS_LUI(DEST, VALUE) \
147 ((0xf << 26) | ((DEST) << 16) | (VALUE))
149 /* Return the opcode to jump to register DEST. */
150 #define MIPS_JR(DEST) \
151 (((DEST) << 21) | 0x8)
153 /* Return the opcode for:
155 bal . + (1 + OFFSET) * 4. */
156 #define MIPS_BAL(OFFSET) \
157 ((0x1 << 26) | (0x11 << 16) | (OFFSET))
159 /* Return the usual opcode for a nop. */
162 /* Classifies an address.
165 A natural register + offset address. The register satisfies
166 mips_valid_base_register_p and the offset is a const_arith_operand.
169 A LO_SUM rtx. The first operand is a valid base register and
170 the second operand is a symbolic address.
173 A signed 16-bit constant address.
176 A constant symbolic address. */
177 enum mips_address_type {
184 /* Macros to create an enumeration identifier for a function prototype. */
185 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
186 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
187 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
188 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
190 /* Classifies the prototype of a built-in function. */
191 enum mips_function_type {
192 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
193 #include "config/mips/mips-ftypes.def"
194 #undef DEF_MIPS_FTYPE
198 /* Specifies how a built-in function should be converted into rtl. */
199 enum mips_builtin_type {
200 /* The function corresponds directly to an .md pattern. The return
201 value is mapped to operand 0 and the arguments are mapped to
202 operands 1 and above. */
205 /* The function corresponds directly to an .md pattern. There is no return
206 value and the arguments are mapped to operands 0 and above. */
207 MIPS_BUILTIN_DIRECT_NO_TARGET,
209 /* The function corresponds to a comparison instruction followed by
210 a mips_cond_move_tf_ps pattern. The first two arguments are the
211 values to compare and the second two arguments are the vector
212 operands for the movt.ps or movf.ps instruction (in assembly order). */
216 /* The function corresponds to a V2SF comparison instruction. Operand 0
217 of this instruction is the result of the comparison, which has mode
218 CCV2 or CCV4. The function arguments are mapped to operands 1 and
219 above. The function's return value is an SImode boolean that is
220 true under the following conditions:
222 MIPS_BUILTIN_CMP_ANY: one of the registers is true
223 MIPS_BUILTIN_CMP_ALL: all of the registers are true
224 MIPS_BUILTIN_CMP_LOWER: the first register is true
225 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
226 MIPS_BUILTIN_CMP_ANY,
227 MIPS_BUILTIN_CMP_ALL,
228 MIPS_BUILTIN_CMP_UPPER,
229 MIPS_BUILTIN_CMP_LOWER,
231 /* As above, but the instruction only sets a single $fcc register. */
232 MIPS_BUILTIN_CMP_SINGLE,
234 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
235 MIPS_BUILTIN_BPOSGE32
238 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
239 #define MIPS_FP_CONDITIONS(MACRO) \
257 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
258 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
259 enum mips_fp_condition {
260 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
263 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
264 #define STRINGIFY(X) #X
265 static const char *const mips_fp_conditions[] = {
266 MIPS_FP_CONDITIONS (STRINGIFY)
269 /* Tuning information that is automatically derived from other sources
270 (such as the scheduler). */
272 /* The architecture and tuning settings that this structure describes. */
276 /* True if this structure describes MIPS16 settings. */
279 /* True if the structure has been initialized. */
282 /* True if "MULT $0, $0" is preferable to "MTLO $0; MTHI $0"
283 when optimizing for speed. */
284 bool fast_mult_zero_zero_p;
287 /* Information about a function's frame layout. */
288 struct GTY(()) mips_frame_info {
289 /* The size of the frame in bytes. */
290 HOST_WIDE_INT total_size;
292 /* The number of bytes allocated to variables. */
293 HOST_WIDE_INT var_size;
295 /* The number of bytes allocated to outgoing function arguments. */
296 HOST_WIDE_INT args_size;
298 /* The number of bytes allocated to the .cprestore slot, or 0 if there
300 HOST_WIDE_INT cprestore_size;
302 /* Bit X is set if the function saves or restores GPR X. */
305 /* Likewise FPR X. */
308 /* Likewise doubleword accumulator X ($acX). */
309 unsigned int acc_mask;
311 /* The number of GPRs, FPRs, doubleword accumulators and COP0
315 unsigned int num_acc;
316 unsigned int num_cop0_regs;
318 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
319 save slots from the top of the frame, or zero if no such slots are
321 HOST_WIDE_INT gp_save_offset;
322 HOST_WIDE_INT fp_save_offset;
323 HOST_WIDE_INT acc_save_offset;
324 HOST_WIDE_INT cop0_save_offset;
326 /* Likewise, but giving offsets from the bottom of the frame. */
327 HOST_WIDE_INT gp_sp_offset;
328 HOST_WIDE_INT fp_sp_offset;
329 HOST_WIDE_INT acc_sp_offset;
330 HOST_WIDE_INT cop0_sp_offset;
332 /* Similar, but the value passed to _mcount. */
333 HOST_WIDE_INT ra_fp_offset;
335 /* The offset of arg_pointer_rtx from the bottom of the frame. */
336 HOST_WIDE_INT arg_pointer_offset;
338 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
339 HOST_WIDE_INT hard_frame_pointer_offset;
342 struct GTY(()) machine_function {
343 /* The next floating-point condition-code register to allocate
344 for ISA_HAS_8CC targets, relative to ST_REG_FIRST. */
345 unsigned int next_fcc;
347 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
348 rtx mips16_gp_pseudo_rtx;
350 /* The number of extra stack bytes taken up by register varargs.
351 This area is allocated by the callee at the very top of the frame. */
354 /* The current frame information, calculated by mips_compute_frame_info. */
355 struct mips_frame_info frame;
357 /* The register to use as the function's global pointer, or INVALID_REGNUM
358 if the function doesn't need one. */
359 unsigned int global_pointer;
361 /* How many instructions it takes to load a label into $AT, or 0 if
362 this property hasn't yet been calculated. */
363 unsigned int load_label_num_insns;
365 /* True if mips_adjust_insn_length should ignore an instruction's
367 bool ignore_hazard_length_p;
369 /* True if the whole function is suitable for .set noreorder and
371 bool all_noreorder_p;
373 /* True if the function has "inflexible" and "flexible" references
374 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
375 and mips_cfun_has_flexible_gp_ref_p for details. */
376 bool has_inflexible_gp_insn_p;
377 bool has_flexible_gp_insn_p;
379 /* True if the function's prologue must load the global pointer
380 value into pic_offset_table_rtx and store the same value in
381 the function's cprestore slot (if any). Even if this value
382 is currently false, we may decide to set it to true later;
383 see mips_must_initialize_gp_p () for details. */
384 bool must_initialize_gp_p;
386 /* True if the current function must restore $gp after any potential
387 clobber. This value is only meaningful during the first post-epilogue
388 split_insns pass; see mips_must_initialize_gp_p () for details. */
389 bool must_restore_gp_when_clobbered_p;
391 /* True if this is an interrupt handler. */
392 bool interrupt_handler_p;
394 /* True if this is an interrupt handler that uses shadow registers. */
395 bool use_shadow_register_set_p;
397 /* True if this is an interrupt handler that should keep interrupts
399 bool keep_interrupts_masked_p;
401 /* True if this is an interrupt handler that should use DERET
403 bool use_debug_exception_return_p;
406 /* Information about a single argument. */
407 struct mips_arg_info {
408 /* True if the argument is passed in a floating-point register, or
409 would have been if we hadn't run out of registers. */
412 /* The number of words passed in registers, rounded up. */
413 unsigned int reg_words;
415 /* For EABI, the offset of the first register from GP_ARG_FIRST or
416 FP_ARG_FIRST. For other ABIs, the offset of the first register from
417 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
418 comment for details).
420 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
422 unsigned int reg_offset;
424 /* The number of words that must be passed on the stack, rounded up. */
425 unsigned int stack_words;
427 /* The offset from the start of the stack overflow area of the argument's
428 first stack word. Only meaningful when STACK_WORDS is nonzero. */
429 unsigned int stack_offset;
432 /* Information about an address described by mips_address_type.
438 REG is the base register and OFFSET is the constant offset.
441 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
442 is the type of symbol it references.
445 SYMBOL_TYPE is the type of symbol that the address references. */
446 struct mips_address_info {
447 enum mips_address_type type;
450 enum mips_symbol_type symbol_type;
453 /* One stage in a constant building sequence. These sequences have
457 A = A CODE[1] VALUE[1]
458 A = A CODE[2] VALUE[2]
461 where A is an accumulator, each CODE[i] is a binary rtl operation
462 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
463 struct mips_integer_op {
465 unsigned HOST_WIDE_INT value;
468 /* The largest number of operations needed to load an integer constant.
469 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
470 When the lowest bit is clear, we can try, but reject a sequence with
471 an extra SLL at the end. */
472 #define MIPS_MAX_INTEGER_OPS 7
474 /* Information about a MIPS16e SAVE or RESTORE instruction. */
475 struct mips16e_save_restore_info {
476 /* The number of argument registers saved by a SAVE instruction.
477 0 for RESTORE instructions. */
480 /* Bit X is set if the instruction saves or restores GPR X. */
483 /* The total number of bytes to allocate. */
487 /* Costs of various operations on the different architectures. */
489 struct mips_rtx_cost_data
491 unsigned short fp_add;
492 unsigned short fp_mult_sf;
493 unsigned short fp_mult_df;
494 unsigned short fp_div_sf;
495 unsigned short fp_div_df;
496 unsigned short int_mult_si;
497 unsigned short int_mult_di;
498 unsigned short int_div_si;
499 unsigned short int_div_di;
500 unsigned short branch_cost;
501 unsigned short memory_latency;
504 /* Global variables for machine-dependent things. */
506 /* The -G setting, or the configuration's default small-data limit if
507 no -G option is given. */
508 static unsigned int mips_small_data_threshold;
510 /* The number of file directives written by mips_output_filename. */
511 int num_source_filenames;
513 /* The name that appeared in the last .file directive written by
514 mips_output_filename, or "" if mips_output_filename hasn't
515 written anything yet. */
516 const char *current_function_file = "";
518 /* Arrays that map GCC register numbers to debugger register numbers. */
519 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
520 int mips_dwarf_regno[FIRST_PSEUDO_REGISTER];
522 /* Information about the current function's epilogue, used only while
525 /* A list of queued REG_CFA_RESTORE notes. */
528 /* The CFA is currently defined as CFA_REG + CFA_OFFSET. */
530 HOST_WIDE_INT cfa_offset;
532 /* The offset of the CFA from the stack pointer while restoring
534 HOST_WIDE_INT cfa_restore_sp_offset;
537 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
538 struct mips_asm_switch mips_noreorder = { "reorder", 0 };
539 struct mips_asm_switch mips_nomacro = { "macro", 0 };
540 struct mips_asm_switch mips_noat = { "at", 0 };
542 /* True if we're writing out a branch-likely instruction rather than a
544 static bool mips_branch_likely;
546 /* The current instruction-set architecture. */
547 enum processor mips_arch;
548 const struct mips_cpu_info *mips_arch_info;
550 /* The processor that we should tune the code for. */
551 enum processor mips_tune;
552 const struct mips_cpu_info *mips_tune_info;
554 /* The ISA level associated with mips_arch. */
557 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
558 static const struct mips_cpu_info *mips_isa_option_info;
560 /* Which cost information to use. */
561 static const struct mips_rtx_cost_data *mips_cost;
563 /* The ambient target flags, excluding MASK_MIPS16. */
564 static int mips_base_target_flags;
566 /* True if MIPS16 is the default mode. */
567 bool mips_base_mips16;
569 /* The ambient values of other global variables. */
570 static int mips_base_schedule_insns; /* flag_schedule_insns */
571 static int mips_base_reorder_blocks_and_partition; /* flag_reorder... */
572 static int mips_base_move_loop_invariants; /* flag_move_loop_invariants */
573 static int mips_base_align_loops; /* align_loops */
574 static int mips_base_align_jumps; /* align_jumps */
575 static int mips_base_align_functions; /* align_functions */
577 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
578 bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
580 /* Index C is true if character C is a valid PRINT_OPERAND punctation
582 static bool mips_print_operand_punct[256];
584 static GTY (()) int mips_output_filename_first_time = 1;
586 /* mips_split_p[X] is true if symbols of type X can be split by
587 mips_split_symbol. */
588 bool mips_split_p[NUM_SYMBOL_TYPES];
590 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
591 can be split by mips_split_symbol. */
592 bool mips_split_hi_p[NUM_SYMBOL_TYPES];
594 /* mips_use_pcrel_pool_p[X] is true if symbols of type X should be
595 forced into a PC-relative constant pool. */
596 bool mips_use_pcrel_pool_p[NUM_SYMBOL_TYPES];
598 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
599 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
600 if they are matched by a special .md file pattern. */
601 const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
603 /* Likewise for HIGHs. */
604 const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
606 /* Target state for MIPS16. */
607 struct target_globals *mips16_globals;
609 /* Cached value of can_issue_more. This is cached in mips_variable_issue hook
610 and returned from mips_sched_reorder2. */
611 static int cached_can_issue_more;
613 /* True if the output uses __mips16_rdhwr. */
614 static bool mips_need_mips16_rdhwr_p;
616 /* Index R is the smallest register class that contains register R. */
617 const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = {
618 LEA_REGS, LEA_REGS, M16_REGS, V1_REG,
619 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
620 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
621 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
622 M16_REGS, M16_REGS, LEA_REGS, LEA_REGS,
623 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
624 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
625 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
626 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
627 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
628 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
629 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
630 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
631 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
632 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
633 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
634 MD0_REG, MD1_REG, NO_REGS, ST_REGS,
635 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
636 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
637 NO_REGS, FRAME_REGS, FRAME_REGS, NO_REGS,
638 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
639 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
640 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
641 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
642 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
643 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
644 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
645 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
646 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
647 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
648 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
649 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
650 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
651 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
652 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
653 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
654 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
655 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
656 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
657 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
658 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
659 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
660 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
661 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
662 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
663 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
664 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
667 /* The value of TARGET_ATTRIBUTE_TABLE. */
668 static const struct attribute_spec mips_attribute_table[] = {
669 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
671 { "long_call", 0, 0, false, true, true, NULL, false },
672 { "far", 0, 0, false, true, true, NULL, false },
673 { "near", 0, 0, false, true, true, NULL, false },
674 /* We would really like to treat "mips16" and "nomips16" as type
675 attributes, but GCC doesn't provide the hooks we need to support
676 the right conversion rules. As declaration attributes, they affect
677 code generation but don't carry other semantics. */
678 { "mips16", 0, 0, true, false, false, NULL, false },
679 { "nomips16", 0, 0, true, false, false, NULL, false },
680 /* Allow functions to be specified as interrupt handlers */
681 { "interrupt", 0, 0, false, true, true, NULL, false },
682 { "use_shadow_register_set", 0, 0, false, true, true, NULL, false },
683 { "keep_interrupts_masked", 0, 0, false, true, true, NULL, false },
684 { "use_debug_exception_return", 0, 0, false, true, true, NULL, false },
685 { NULL, 0, 0, false, false, false, NULL, false }
688 /* A table describing all the processors GCC knows about; see
689 mips-cpus.def for details. */
690 static const struct mips_cpu_info mips_cpu_info_table[] = {
691 #define MIPS_CPU(NAME, CPU, ISA, FLAGS) \
692 { NAME, CPU, ISA, FLAGS },
693 #include "mips-cpus.def"
697 /* Default costs. If these are used for a processor we should look
698 up the actual costs. */
699 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
700 COSTS_N_INSNS (7), /* fp_mult_sf */ \
701 COSTS_N_INSNS (8), /* fp_mult_df */ \
702 COSTS_N_INSNS (23), /* fp_div_sf */ \
703 COSTS_N_INSNS (36), /* fp_div_df */ \
704 COSTS_N_INSNS (10), /* int_mult_si */ \
705 COSTS_N_INSNS (10), /* int_mult_di */ \
706 COSTS_N_INSNS (69), /* int_div_si */ \
707 COSTS_N_INSNS (69), /* int_div_di */ \
708 2, /* branch_cost */ \
709 4 /* memory_latency */
711 /* Floating-point costs for processors without an FPU. Just assume that
712 all floating-point libcalls are very expensive. */
713 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
714 COSTS_N_INSNS (256), /* fp_mult_sf */ \
715 COSTS_N_INSNS (256), /* fp_mult_df */ \
716 COSTS_N_INSNS (256), /* fp_div_sf */ \
717 COSTS_N_INSNS (256) /* fp_div_df */
719 /* Costs to use when optimizing for size. */
720 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size = {
721 COSTS_N_INSNS (1), /* fp_add */
722 COSTS_N_INSNS (1), /* fp_mult_sf */
723 COSTS_N_INSNS (1), /* fp_mult_df */
724 COSTS_N_INSNS (1), /* fp_div_sf */
725 COSTS_N_INSNS (1), /* fp_div_df */
726 COSTS_N_INSNS (1), /* int_mult_si */
727 COSTS_N_INSNS (1), /* int_mult_di */
728 COSTS_N_INSNS (1), /* int_div_si */
729 COSTS_N_INSNS (1), /* int_div_di */
731 4 /* memory_latency */
734 /* Costs to use when optimizing for speed, indexed by processor. */
735 static const struct mips_rtx_cost_data
736 mips_rtx_cost_data[NUM_PROCESSOR_VALUES] = {
738 COSTS_N_INSNS (2), /* fp_add */
739 COSTS_N_INSNS (4), /* fp_mult_sf */
740 COSTS_N_INSNS (5), /* fp_mult_df */
741 COSTS_N_INSNS (12), /* fp_div_sf */
742 COSTS_N_INSNS (19), /* fp_div_df */
743 COSTS_N_INSNS (12), /* int_mult_si */
744 COSTS_N_INSNS (12), /* int_mult_di */
745 COSTS_N_INSNS (35), /* int_div_si */
746 COSTS_N_INSNS (35), /* int_div_di */
748 4 /* memory_latency */
752 COSTS_N_INSNS (6), /* int_mult_si */
753 COSTS_N_INSNS (6), /* int_mult_di */
754 COSTS_N_INSNS (36), /* int_div_si */
755 COSTS_N_INSNS (36), /* int_div_di */
757 4 /* memory_latency */
761 COSTS_N_INSNS (36), /* int_mult_si */
762 COSTS_N_INSNS (36), /* int_mult_di */
763 COSTS_N_INSNS (37), /* int_div_si */
764 COSTS_N_INSNS (37), /* int_div_di */
766 4 /* memory_latency */
770 COSTS_N_INSNS (4), /* int_mult_si */
771 COSTS_N_INSNS (11), /* int_mult_di */
772 COSTS_N_INSNS (36), /* int_div_si */
773 COSTS_N_INSNS (68), /* int_div_di */
775 4 /* memory_latency */
778 COSTS_N_INSNS (4), /* fp_add */
779 COSTS_N_INSNS (4), /* fp_mult_sf */
780 COSTS_N_INSNS (5), /* fp_mult_df */
781 COSTS_N_INSNS (17), /* fp_div_sf */
782 COSTS_N_INSNS (32), /* fp_div_df */
783 COSTS_N_INSNS (4), /* int_mult_si */
784 COSTS_N_INSNS (11), /* int_mult_di */
785 COSTS_N_INSNS (36), /* int_div_si */
786 COSTS_N_INSNS (68), /* int_div_di */
788 4 /* memory_latency */
791 COSTS_N_INSNS (4), /* fp_add */
792 COSTS_N_INSNS (4), /* fp_mult_sf */
793 COSTS_N_INSNS (5), /* fp_mult_df */
794 COSTS_N_INSNS (17), /* fp_div_sf */
795 COSTS_N_INSNS (32), /* fp_div_df */
796 COSTS_N_INSNS (4), /* int_mult_si */
797 COSTS_N_INSNS (7), /* int_mult_di */
798 COSTS_N_INSNS (42), /* int_div_si */
799 COSTS_N_INSNS (72), /* int_div_di */
801 4 /* memory_latency */
805 COSTS_N_INSNS (5), /* int_mult_si */
806 COSTS_N_INSNS (5), /* int_mult_di */
807 COSTS_N_INSNS (41), /* int_div_si */
808 COSTS_N_INSNS (41), /* int_div_di */
810 4 /* memory_latency */
813 COSTS_N_INSNS (8), /* fp_add */
814 COSTS_N_INSNS (8), /* fp_mult_sf */
815 COSTS_N_INSNS (10), /* fp_mult_df */
816 COSTS_N_INSNS (34), /* fp_div_sf */
817 COSTS_N_INSNS (64), /* fp_div_df */
818 COSTS_N_INSNS (5), /* int_mult_si */
819 COSTS_N_INSNS (5), /* int_mult_di */
820 COSTS_N_INSNS (41), /* int_div_si */
821 COSTS_N_INSNS (41), /* int_div_di */
823 4 /* memory_latency */
826 COSTS_N_INSNS (4), /* fp_add */
827 COSTS_N_INSNS (4), /* fp_mult_sf */
828 COSTS_N_INSNS (5), /* fp_mult_df */
829 COSTS_N_INSNS (17), /* fp_div_sf */
830 COSTS_N_INSNS (32), /* fp_div_df */
831 COSTS_N_INSNS (5), /* int_mult_si */
832 COSTS_N_INSNS (5), /* int_mult_di */
833 COSTS_N_INSNS (41), /* int_div_si */
834 COSTS_N_INSNS (41), /* int_div_di */
836 4 /* memory_latency */
840 COSTS_N_INSNS (5), /* int_mult_si */
841 COSTS_N_INSNS (5), /* int_mult_di */
842 COSTS_N_INSNS (41), /* int_div_si */
843 COSTS_N_INSNS (41), /* int_div_di */
845 4 /* memory_latency */
848 COSTS_N_INSNS (8), /* fp_add */
849 COSTS_N_INSNS (8), /* fp_mult_sf */
850 COSTS_N_INSNS (10), /* fp_mult_df */
851 COSTS_N_INSNS (34), /* fp_div_sf */
852 COSTS_N_INSNS (64), /* fp_div_df */
853 COSTS_N_INSNS (5), /* int_mult_si */
854 COSTS_N_INSNS (5), /* int_mult_di */
855 COSTS_N_INSNS (41), /* int_div_si */
856 COSTS_N_INSNS (41), /* int_div_di */
858 4 /* memory_latency */
861 COSTS_N_INSNS (4), /* fp_add */
862 COSTS_N_INSNS (4), /* fp_mult_sf */
863 COSTS_N_INSNS (5), /* fp_mult_df */
864 COSTS_N_INSNS (17), /* fp_div_sf */
865 COSTS_N_INSNS (32), /* fp_div_df */
866 COSTS_N_INSNS (5), /* int_mult_si */
867 COSTS_N_INSNS (5), /* int_mult_di */
868 COSTS_N_INSNS (41), /* int_div_si */
869 COSTS_N_INSNS (41), /* int_div_di */
871 4 /* memory_latency */
874 COSTS_N_INSNS (6), /* fp_add */
875 COSTS_N_INSNS (6), /* fp_mult_sf */
876 COSTS_N_INSNS (7), /* fp_mult_df */
877 COSTS_N_INSNS (25), /* fp_div_sf */
878 COSTS_N_INSNS (48), /* fp_div_df */
879 COSTS_N_INSNS (5), /* int_mult_si */
880 COSTS_N_INSNS (5), /* int_mult_di */
881 COSTS_N_INSNS (41), /* int_div_si */
882 COSTS_N_INSNS (41), /* int_div_di */
884 4 /* memory_latency */
901 COSTS_N_INSNS (5), /* int_mult_si */
902 COSTS_N_INSNS (5), /* int_mult_di */
903 COSTS_N_INSNS (72), /* int_div_si */
904 COSTS_N_INSNS (72), /* int_div_di */
906 4 /* memory_latency */
911 COSTS_N_INSNS (6), /* int_mult_si */
912 COSTS_N_INSNS (6), /* int_mult_di */
913 COSTS_N_INSNS (18), /* int_div_si */
914 COSTS_N_INSNS (35), /* int_div_di */
916 4 /* memory_latency */
919 COSTS_N_INSNS (2), /* fp_add */
920 COSTS_N_INSNS (4), /* fp_mult_sf */
921 COSTS_N_INSNS (5), /* fp_mult_df */
922 COSTS_N_INSNS (12), /* fp_div_sf */
923 COSTS_N_INSNS (19), /* fp_div_df */
924 COSTS_N_INSNS (2), /* int_mult_si */
925 COSTS_N_INSNS (2), /* int_mult_di */
926 COSTS_N_INSNS (35), /* int_div_si */
927 COSTS_N_INSNS (35), /* int_div_di */
929 4 /* memory_latency */
932 COSTS_N_INSNS (3), /* fp_add */
933 COSTS_N_INSNS (5), /* fp_mult_sf */
934 COSTS_N_INSNS (6), /* fp_mult_df */
935 COSTS_N_INSNS (15), /* fp_div_sf */
936 COSTS_N_INSNS (16), /* fp_div_df */
937 COSTS_N_INSNS (17), /* int_mult_si */
938 COSTS_N_INSNS (17), /* int_mult_di */
939 COSTS_N_INSNS (38), /* int_div_si */
940 COSTS_N_INSNS (38), /* int_div_di */
942 6 /* memory_latency */
945 COSTS_N_INSNS (6), /* fp_add */
946 COSTS_N_INSNS (7), /* fp_mult_sf */
947 COSTS_N_INSNS (8), /* fp_mult_df */
948 COSTS_N_INSNS (23), /* fp_div_sf */
949 COSTS_N_INSNS (36), /* fp_div_df */
950 COSTS_N_INSNS (10), /* int_mult_si */
951 COSTS_N_INSNS (10), /* int_mult_di */
952 COSTS_N_INSNS (69), /* int_div_si */
953 COSTS_N_INSNS (69), /* int_div_di */
955 6 /* memory_latency */
967 /* The only costs that appear to be updated here are
968 integer multiplication. */
970 COSTS_N_INSNS (4), /* int_mult_si */
971 COSTS_N_INSNS (6), /* int_mult_di */
972 COSTS_N_INSNS (69), /* int_div_si */
973 COSTS_N_INSNS (69), /* int_div_di */
975 4 /* memory_latency */
990 COSTS_N_INSNS (6), /* fp_add */
991 COSTS_N_INSNS (4), /* fp_mult_sf */
992 COSTS_N_INSNS (5), /* fp_mult_df */
993 COSTS_N_INSNS (23), /* fp_div_sf */
994 COSTS_N_INSNS (36), /* fp_div_df */
995 COSTS_N_INSNS (5), /* int_mult_si */
996 COSTS_N_INSNS (5), /* int_mult_di */
997 COSTS_N_INSNS (36), /* int_div_si */
998 COSTS_N_INSNS (36), /* int_div_di */
1000 4 /* memory_latency */
1003 COSTS_N_INSNS (6), /* fp_add */
1004 COSTS_N_INSNS (5), /* fp_mult_sf */
1005 COSTS_N_INSNS (6), /* fp_mult_df */
1006 COSTS_N_INSNS (30), /* fp_div_sf */
1007 COSTS_N_INSNS (59), /* fp_div_df */
1008 COSTS_N_INSNS (3), /* int_mult_si */
1009 COSTS_N_INSNS (4), /* int_mult_di */
1010 COSTS_N_INSNS (42), /* int_div_si */
1011 COSTS_N_INSNS (74), /* int_div_di */
1012 1, /* branch_cost */
1013 4 /* memory_latency */
1016 COSTS_N_INSNS (6), /* fp_add */
1017 COSTS_N_INSNS (5), /* fp_mult_sf */
1018 COSTS_N_INSNS (6), /* fp_mult_df */
1019 COSTS_N_INSNS (30), /* fp_div_sf */
1020 COSTS_N_INSNS (59), /* fp_div_df */
1021 COSTS_N_INSNS (5), /* int_mult_si */
1022 COSTS_N_INSNS (9), /* int_mult_di */
1023 COSTS_N_INSNS (42), /* int_div_si */
1024 COSTS_N_INSNS (74), /* int_div_di */
1025 1, /* branch_cost */
1026 4 /* memory_latency */
1029 /* The only costs that are changed here are
1030 integer multiplication. */
1031 COSTS_N_INSNS (6), /* fp_add */
1032 COSTS_N_INSNS (7), /* fp_mult_sf */
1033 COSTS_N_INSNS (8), /* fp_mult_df */
1034 COSTS_N_INSNS (23), /* fp_div_sf */
1035 COSTS_N_INSNS (36), /* fp_div_df */
1036 COSTS_N_INSNS (5), /* int_mult_si */
1037 COSTS_N_INSNS (9), /* int_mult_di */
1038 COSTS_N_INSNS (69), /* int_div_si */
1039 COSTS_N_INSNS (69), /* int_div_di */
1040 1, /* branch_cost */
1041 4 /* memory_latency */
1047 /* The only costs that are changed here are
1048 integer multiplication. */
1049 COSTS_N_INSNS (6), /* fp_add */
1050 COSTS_N_INSNS (7), /* fp_mult_sf */
1051 COSTS_N_INSNS (8), /* fp_mult_df */
1052 COSTS_N_INSNS (23), /* fp_div_sf */
1053 COSTS_N_INSNS (36), /* fp_div_df */
1054 COSTS_N_INSNS (3), /* int_mult_si */
1055 COSTS_N_INSNS (8), /* int_mult_di */
1056 COSTS_N_INSNS (69), /* int_div_si */
1057 COSTS_N_INSNS (69), /* int_div_di */
1058 1, /* branch_cost */
1059 4 /* memory_latency */
1062 COSTS_N_INSNS (2), /* fp_add */
1063 COSTS_N_INSNS (2), /* fp_mult_sf */
1064 COSTS_N_INSNS (2), /* fp_mult_df */
1065 COSTS_N_INSNS (12), /* fp_div_sf */
1066 COSTS_N_INSNS (19), /* fp_div_df */
1067 COSTS_N_INSNS (5), /* int_mult_si */
1068 COSTS_N_INSNS (9), /* int_mult_di */
1069 COSTS_N_INSNS (34), /* int_div_si */
1070 COSTS_N_INSNS (66), /* int_div_di */
1071 1, /* branch_cost */
1072 4 /* memory_latency */
1075 /* These costs are the same as the SB-1A below. */
1076 COSTS_N_INSNS (4), /* fp_add */
1077 COSTS_N_INSNS (4), /* fp_mult_sf */
1078 COSTS_N_INSNS (4), /* fp_mult_df */
1079 COSTS_N_INSNS (24), /* fp_div_sf */
1080 COSTS_N_INSNS (32), /* fp_div_df */
1081 COSTS_N_INSNS (3), /* int_mult_si */
1082 COSTS_N_INSNS (4), /* int_mult_di */
1083 COSTS_N_INSNS (36), /* int_div_si */
1084 COSTS_N_INSNS (68), /* int_div_di */
1085 1, /* branch_cost */
1086 4 /* memory_latency */
1089 /* These costs are the same as the SB-1 above. */
1090 COSTS_N_INSNS (4), /* fp_add */
1091 COSTS_N_INSNS (4), /* fp_mult_sf */
1092 COSTS_N_INSNS (4), /* fp_mult_df */
1093 COSTS_N_INSNS (24), /* fp_div_sf */
1094 COSTS_N_INSNS (32), /* fp_div_df */
1095 COSTS_N_INSNS (3), /* int_mult_si */
1096 COSTS_N_INSNS (4), /* int_mult_di */
1097 COSTS_N_INSNS (36), /* int_div_si */
1098 COSTS_N_INSNS (68), /* int_div_di */
1099 1, /* branch_cost */
1100 4 /* memory_latency */
1107 COSTS_N_INSNS (8), /* int_mult_si */
1108 COSTS_N_INSNS (8), /* int_mult_di */
1109 COSTS_N_INSNS (72), /* int_div_si */
1110 COSTS_N_INSNS (72), /* int_div_di */
1111 1, /* branch_cost */
1112 4 /* memory_latency */
1115 /* These costs are the same as 5KF above. */
1116 COSTS_N_INSNS (4), /* fp_add */
1117 COSTS_N_INSNS (4), /* fp_mult_sf */
1118 COSTS_N_INSNS (5), /* fp_mult_df */
1119 COSTS_N_INSNS (17), /* fp_div_sf */
1120 COSTS_N_INSNS (32), /* fp_div_df */
1121 COSTS_N_INSNS (4), /* int_mult_si */
1122 COSTS_N_INSNS (11), /* int_mult_di */
1123 COSTS_N_INSNS (36), /* int_div_si */
1124 COSTS_N_INSNS (68), /* int_div_di */
1125 1, /* branch_cost */
1126 4 /* memory_latency */
1130 static rtx mips_find_pic_call_symbol (rtx, rtx, bool);
1131 static int mips_register_move_cost (enum machine_mode, reg_class_t,
1133 static unsigned int mips_function_arg_boundary (enum machine_mode, const_tree);
1135 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1136 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1137 struct GTY (()) mflip_mips16_entry {
1141 static GTY ((param_is (struct mflip_mips16_entry))) htab_t mflip_mips16_htab;
1143 /* Hash table callbacks for mflip_mips16_htab. */
1146 mflip_mips16_htab_hash (const void *entry)
1148 return htab_hash_string (((const struct mflip_mips16_entry *) entry)->name);
1152 mflip_mips16_htab_eq (const void *entry, const void *name)
1154 return strcmp (((const struct mflip_mips16_entry *) entry)->name,
1155 (const char *) name) == 0;
1158 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1159 mode, false if it should next add an attribute for the opposite mode. */
1160 static GTY(()) bool mips16_flipper;
1162 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1163 for -mflip-mips16. Return true if it should use "mips16" and false if
1164 it should use "nomips16". */
1167 mflip_mips16_use_mips16_p (tree decl)
1169 struct mflip_mips16_entry *entry;
1174 /* Use the opposite of the command-line setting for anonymous decls. */
1175 if (!DECL_NAME (decl))
1176 return !mips_base_mips16;
1178 if (!mflip_mips16_htab)
1179 mflip_mips16_htab = htab_create_ggc (37, mflip_mips16_htab_hash,
1180 mflip_mips16_htab_eq, NULL);
1182 name = IDENTIFIER_POINTER (DECL_NAME (decl));
1183 hash = htab_hash_string (name);
1184 slot = htab_find_slot_with_hash (mflip_mips16_htab, name, hash, INSERT);
1185 entry = (struct mflip_mips16_entry *) *slot;
1188 mips16_flipper = !mips16_flipper;
1189 entry = ggc_alloc_mflip_mips16_entry ();
1191 entry->mips16_p = mips16_flipper ? !mips_base_mips16 : mips_base_mips16;
1194 return entry->mips16_p;
1197 /* Predicates to test for presence of "near" and "far"/"long_call"
1198 attributes on the given TYPE. */
1201 mips_near_type_p (const_tree type)
1203 return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL;
1207 mips_far_type_p (const_tree type)
1209 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL
1210 || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL);
1213 /* Similar predicates for "mips16"/"nomips16" function attributes. */
1216 mips_mips16_decl_p (const_tree decl)
1218 return lookup_attribute ("mips16", DECL_ATTRIBUTES (decl)) != NULL;
1222 mips_nomips16_decl_p (const_tree decl)
1224 return lookup_attribute ("nomips16", DECL_ATTRIBUTES (decl)) != NULL;
1227 /* Check if the interrupt attribute is set for a function. */
1230 mips_interrupt_type_p (tree type)
1232 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type)) != NULL;
1235 /* Check if the attribute to use shadow register set is set for a function. */
1238 mips_use_shadow_register_set_p (tree type)
1240 return lookup_attribute ("use_shadow_register_set",
1241 TYPE_ATTRIBUTES (type)) != NULL;
1244 /* Check if the attribute to keep interrupts masked is set for a function. */
1247 mips_keep_interrupts_masked_p (tree type)
1249 return lookup_attribute ("keep_interrupts_masked",
1250 TYPE_ATTRIBUTES (type)) != NULL;
1253 /* Check if the attribute to use debug exception return is set for
1257 mips_use_debug_exception_return_p (tree type)
1259 return lookup_attribute ("use_debug_exception_return",
1260 TYPE_ATTRIBUTES (type)) != NULL;
1263 /* Return true if function DECL is a MIPS16 function. Return the ambient
1264 setting if DECL is null. */
1267 mips_use_mips16_mode_p (tree decl)
1271 /* Nested functions must use the same frame pointer as their
1272 parent and must therefore use the same ISA mode. */
1273 tree parent = decl_function_context (decl);
1276 if (mips_mips16_decl_p (decl))
1278 if (mips_nomips16_decl_p (decl))
1281 return mips_base_mips16;
1284 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1287 mips_comp_type_attributes (const_tree type1, const_tree type2)
1289 /* Disallow mixed near/far attributes. */
1290 if (mips_far_type_p (type1) && mips_near_type_p (type2))
1292 if (mips_near_type_p (type1) && mips_far_type_p (type2))
1297 /* Implement TARGET_INSERT_ATTRIBUTES. */
1300 mips_insert_attributes (tree decl, tree *attributes)
1303 bool mips16_p, nomips16_p;
1305 /* Check for "mips16" and "nomips16" attributes. */
1306 mips16_p = lookup_attribute ("mips16", *attributes) != NULL;
1307 nomips16_p = lookup_attribute ("nomips16", *attributes) != NULL;
1308 if (TREE_CODE (decl) != FUNCTION_DECL)
1311 error ("%qs attribute only applies to functions", "mips16");
1313 error ("%qs attribute only applies to functions", "nomips16");
1317 mips16_p |= mips_mips16_decl_p (decl);
1318 nomips16_p |= mips_nomips16_decl_p (decl);
1319 if (mips16_p || nomips16_p)
1321 /* DECL cannot be simultaneously "mips16" and "nomips16". */
1322 if (mips16_p && nomips16_p)
1323 error ("%qE cannot have both %<mips16%> and "
1324 "%<nomips16%> attributes",
1327 else if (TARGET_FLIP_MIPS16 && !DECL_ARTIFICIAL (decl))
1329 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1330 "mips16" attribute, arbitrarily pick one. We must pick the same
1331 setting for duplicate declarations of a function. */
1332 name = mflip_mips16_use_mips16_p (decl) ? "mips16" : "nomips16";
1333 *attributes = tree_cons (get_identifier (name), NULL, *attributes);
1338 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1341 mips_merge_decl_attributes (tree olddecl, tree newdecl)
1343 /* The decls' "mips16" and "nomips16" attributes must match exactly. */
1344 if (mips_mips16_decl_p (olddecl) != mips_mips16_decl_p (newdecl))
1345 error ("%qE redeclared with conflicting %qs attributes",
1346 DECL_NAME (newdecl), "mips16");
1347 if (mips_nomips16_decl_p (olddecl) != mips_nomips16_decl_p (newdecl))
1348 error ("%qE redeclared with conflicting %qs attributes",
1349 DECL_NAME (newdecl), "nomips16");
1351 return merge_attributes (DECL_ATTRIBUTES (olddecl),
1352 DECL_ATTRIBUTES (newdecl));
1355 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1356 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1359 mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr)
1361 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
1363 *base_ptr = XEXP (x, 0);
1364 *offset_ptr = INTVAL (XEXP (x, 1));
1373 static unsigned int mips_build_integer (struct mips_integer_op *,
1374 unsigned HOST_WIDE_INT);
1376 /* A subroutine of mips_build_integer, with the same interface.
1377 Assume that the final action in the sequence should be a left shift. */
1380 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1382 unsigned int i, shift;
1384 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1385 since signed numbers are easier to load than unsigned ones. */
1387 while ((value & 1) == 0)
1388 value /= 2, shift++;
1390 i = mips_build_integer (codes, value);
1391 codes[i].code = ASHIFT;
1392 codes[i].value = shift;
1396 /* As for mips_build_shift, but assume that the final action will be
1397 an IOR or PLUS operation. */
1400 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1402 unsigned HOST_WIDE_INT high;
1405 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1406 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
1408 /* The constant is too complex to load with a simple LUI/ORI pair,
1409 so we want to give the recursive call as many trailing zeros as
1410 possible. In this case, we know bit 16 is set and that the
1411 low 16 bits form a negative number. If we subtract that number
1412 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1413 i = mips_build_integer (codes, CONST_HIGH_PART (value));
1414 codes[i].code = PLUS;
1415 codes[i].value = CONST_LOW_PART (value);
1419 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1420 bits gives a value with at least 17 trailing zeros. */
1421 i = mips_build_integer (codes, high);
1422 codes[i].code = IOR;
1423 codes[i].value = value & 0xffff;
1428 /* Fill CODES with a sequence of rtl operations to load VALUE.
1429 Return the number of operations needed. */
1432 mips_build_integer (struct mips_integer_op *codes,
1433 unsigned HOST_WIDE_INT value)
1435 if (SMALL_OPERAND (value)
1436 || SMALL_OPERAND_UNSIGNED (value)
1437 || LUI_OPERAND (value))
1439 /* The value can be loaded with a single instruction. */
1440 codes[0].code = UNKNOWN;
1441 codes[0].value = value;
1444 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
1446 /* Either the constant is a simple LUI/ORI combination or its
1447 lowest bit is set. We don't want to shift in this case. */
1448 return mips_build_lower (codes, value);
1450 else if ((value & 0xffff) == 0)
1452 /* The constant will need at least three actions. The lowest
1453 16 bits are clear, so the final action will be a shift. */
1454 return mips_build_shift (codes, value);
1458 /* The final action could be a shift, add or inclusive OR.
1459 Rather than use a complex condition to select the best
1460 approach, try both mips_build_shift and mips_build_lower
1461 and pick the one that gives the shortest sequence.
1462 Note that this case is only used once per constant. */
1463 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1464 unsigned int cost, alt_cost;
1466 cost = mips_build_shift (codes, value);
1467 alt_cost = mips_build_lower (alt_codes, value);
1468 if (alt_cost < cost)
1470 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
1477 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
1480 mips_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
1482 return mips_const_insns (x) > 0;
1485 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
1488 mips16_stub_function (const char *name)
1492 x = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
1493 SYMBOL_REF_FLAGS (x) |= (SYMBOL_FLAG_EXTERNAL | SYMBOL_FLAG_FUNCTION);
1497 /* Return true if symbols of type TYPE require a GOT access. */
1500 mips_got_symbol_type_p (enum mips_symbol_type type)
1504 case SYMBOL_GOT_PAGE_OFST:
1505 case SYMBOL_GOT_DISP:
1513 /* Return true if X is a thread-local symbol. */
1516 mips_tls_symbol_p (rtx x)
1518 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1521 /* Return true if SYMBOL_REF X is associated with a global symbol
1522 (in the STB_GLOBAL sense). */
1525 mips_global_symbol_p (const_rtx x)
1527 const_tree decl = SYMBOL_REF_DECL (x);
1530 return !SYMBOL_REF_LOCAL_P (x) || SYMBOL_REF_EXTERNAL_P (x);
1532 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1533 or weak symbols. Relocations in the object file will be against
1534 the target symbol, so it's that symbol's binding that matters here. */
1535 return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl));
1538 /* Return true if function X is a libgcc MIPS16 stub function. */
1541 mips16_stub_function_p (const_rtx x)
1543 return (GET_CODE (x) == SYMBOL_REF
1544 && strncmp (XSTR (x, 0), "__mips16_", 9) == 0);
1547 /* Return true if function X is a locally-defined and locally-binding
1551 mips16_local_function_p (const_rtx x)
1553 return (GET_CODE (x) == SYMBOL_REF
1554 && SYMBOL_REF_LOCAL_P (x)
1555 && !SYMBOL_REF_EXTERNAL_P (x)
1556 && mips_use_mips16_mode_p (SYMBOL_REF_DECL (x)));
1559 /* Return true if SYMBOL_REF X binds locally. */
1562 mips_symbol_binds_local_p (const_rtx x)
1564 return (SYMBOL_REF_DECL (x)
1565 ? targetm.binds_local_p (SYMBOL_REF_DECL (x))
1566 : SYMBOL_REF_LOCAL_P (x));
1569 /* Return true if rtx constants of mode MODE should be put into a small
1573 mips_rtx_constant_in_small_data_p (enum machine_mode mode)
1575 return (!TARGET_EMBEDDED_DATA
1576 && TARGET_LOCAL_SDATA
1577 && GET_MODE_SIZE (mode) <= mips_small_data_threshold);
1580 /* Return true if X should not be moved directly into register $25.
1581 We need this because many versions of GAS will treat "la $25,foo" as
1582 part of a call sequence and so allow a global "foo" to be lazily bound. */
1585 mips_dangerous_for_la25_p (rtx x)
1587 return (!TARGET_EXPLICIT_RELOCS
1589 && GET_CODE (x) == SYMBOL_REF
1590 && mips_global_symbol_p (x));
1593 /* Return true if calls to X might need $25 to be valid on entry. */
1596 mips_use_pic_fn_addr_reg_p (const_rtx x)
1598 if (!TARGET_USE_PIC_FN_ADDR_REG)
1601 /* MIPS16 stub functions are guaranteed not to use $25. */
1602 if (mips16_stub_function_p (x))
1605 if (GET_CODE (x) == SYMBOL_REF)
1607 /* If PLTs and copy relocations are available, the static linker
1608 will make sure that $25 is valid on entry to the target function. */
1609 if (TARGET_ABICALLS_PIC0)
1612 /* Locally-defined functions use absolute accesses to set up
1613 the global pointer. */
1614 if (TARGET_ABSOLUTE_ABICALLS
1615 && mips_symbol_binds_local_p (x)
1616 && !SYMBOL_REF_EXTERNAL_P (x))
1623 /* Return the method that should be used to access SYMBOL_REF or
1624 LABEL_REF X in context CONTEXT. */
1626 static enum mips_symbol_type
1627 mips_classify_symbol (const_rtx x, enum mips_symbol_context context)
1630 return SYMBOL_GOT_DISP;
1632 if (GET_CODE (x) == LABEL_REF)
1634 /* Only return SYMBOL_PC_RELATIVE if we are generating MIPS16
1635 code and if we know that the label is in the current function's
1636 text section. LABEL_REFs are used for jump tables as well as
1637 text labels, so we must check whether jump tables live in the
1639 if (TARGET_MIPS16_SHORT_JUMP_TABLES
1640 && !LABEL_REF_NONLOCAL_P (x))
1641 return SYMBOL_PC_RELATIVE;
1643 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1644 return SYMBOL_GOT_PAGE_OFST;
1646 return SYMBOL_ABSOLUTE;
1649 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1651 if (SYMBOL_REF_TLS_MODEL (x))
1654 if (CONSTANT_POOL_ADDRESS_P (x))
1656 if (TARGET_MIPS16_TEXT_LOADS)
1657 return SYMBOL_PC_RELATIVE;
1659 if (TARGET_MIPS16_PCREL_LOADS && context == SYMBOL_CONTEXT_MEM)
1660 return SYMBOL_PC_RELATIVE;
1662 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x)))
1663 return SYMBOL_GP_RELATIVE;
1666 /* Do not use small-data accesses for weak symbols; they may end up
1668 if (TARGET_GPOPT && SYMBOL_REF_SMALL_P (x) && !SYMBOL_REF_WEAK (x))
1669 return SYMBOL_GP_RELATIVE;
1671 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1673 if (TARGET_ABICALLS_PIC2
1674 && !(TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x)))
1676 /* There are three cases to consider:
1678 - o32 PIC (either with or without explicit relocs)
1679 - n32/n64 PIC without explicit relocs
1680 - n32/n64 PIC with explicit relocs
1682 In the first case, both local and global accesses will use an
1683 R_MIPS_GOT16 relocation. We must correctly predict which of
1684 the two semantics (local or global) the assembler and linker
1685 will apply. The choice depends on the symbol's binding rather
1686 than its visibility.
1688 In the second case, the assembler will not use R_MIPS_GOT16
1689 relocations, but it chooses between local and global accesses
1690 in the same way as for o32 PIC.
1692 In the third case we have more freedom since both forms of
1693 access will work for any kind of symbol. However, there seems
1694 little point in doing things differently. */
1695 if (mips_global_symbol_p (x))
1696 return SYMBOL_GOT_DISP;
1698 return SYMBOL_GOT_PAGE_OFST;
1701 return SYMBOL_ABSOLUTE;
1704 /* Classify the base of symbolic expression X, given that X appears in
1707 static enum mips_symbol_type
1708 mips_classify_symbolic_expression (rtx x, enum mips_symbol_context context)
1712 split_const (x, &x, &offset);
1713 if (UNSPEC_ADDRESS_P (x))
1714 return UNSPEC_ADDRESS_TYPE (x);
1716 return mips_classify_symbol (x, context);
1719 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1720 is the alignment in bytes of SYMBOL_REF X. */
1723 mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset)
1725 HOST_WIDE_INT align;
1727 align = SYMBOL_REF_DECL (x) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x)) : 1;
1728 return IN_RANGE (offset, 0, align - 1);
1731 /* Return true if X is a symbolic constant that can be used in context
1732 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1735 mips_symbolic_constant_p (rtx x, enum mips_symbol_context context,
1736 enum mips_symbol_type *symbol_type)
1740 split_const (x, &x, &offset);
1741 if (UNSPEC_ADDRESS_P (x))
1743 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1744 x = UNSPEC_ADDRESS (x);
1746 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1748 *symbol_type = mips_classify_symbol (x, context);
1749 if (*symbol_type == SYMBOL_TLS)
1755 if (offset == const0_rtx)
1758 /* Check whether a nonzero offset is valid for the underlying
1760 switch (*symbol_type)
1762 case SYMBOL_ABSOLUTE:
1763 case SYMBOL_64_HIGH:
1766 /* If the target has 64-bit pointers and the object file only
1767 supports 32-bit symbols, the values of those symbols will be
1768 sign-extended. In this case we can't allow an arbitrary offset
1769 in case the 32-bit value X + OFFSET has a different sign from X. */
1770 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1771 return offset_within_block_p (x, INTVAL (offset));
1773 /* In other cases the relocations can handle any offset. */
1776 case SYMBOL_PC_RELATIVE:
1777 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1778 In this case, we no longer have access to the underlying constant,
1779 but the original symbol-based access was known to be valid. */
1780 if (GET_CODE (x) == LABEL_REF)
1785 case SYMBOL_GP_RELATIVE:
1786 /* Make sure that the offset refers to something within the
1787 same object block. This should guarantee that the final
1788 PC- or GP-relative offset is within the 16-bit limit. */
1789 return offset_within_block_p (x, INTVAL (offset));
1791 case SYMBOL_GOT_PAGE_OFST:
1792 case SYMBOL_GOTOFF_PAGE:
1793 /* If the symbol is global, the GOT entry will contain the symbol's
1794 address, and we will apply a 16-bit offset after loading it.
1795 If the symbol is local, the linker should provide enough local
1796 GOT entries for a 16-bit offset, but larger offsets may lead
1798 return SMALL_INT (offset);
1802 /* There is no carry between the HI and LO REL relocations, so the
1803 offset is only valid if we know it won't lead to such a carry. */
1804 return mips_offset_within_alignment_p (x, INTVAL (offset));
1806 case SYMBOL_GOT_DISP:
1807 case SYMBOL_GOTOFF_DISP:
1808 case SYMBOL_GOTOFF_CALL:
1809 case SYMBOL_GOTOFF_LOADGP:
1812 case SYMBOL_GOTTPREL:
1820 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
1821 single instruction. We rely on the fact that, in the worst case,
1822 all instructions involved in a MIPS16 address calculation are usually
1826 mips_symbol_insns_1 (enum mips_symbol_type type, enum machine_mode mode)
1828 if (mips_use_pcrel_pool_p[(int) type])
1830 if (mode == MAX_MACHINE_MODE)
1831 /* LEAs will be converted into constant-pool references by
1833 type = SYMBOL_PC_RELATIVE;
1835 /* The constant must be loaded and then dereferenced. */
1841 case SYMBOL_ABSOLUTE:
1842 /* When using 64-bit symbols, we need 5 preparatory instructions,
1845 lui $at,%highest(symbol)
1846 daddiu $at,$at,%higher(symbol)
1848 daddiu $at,$at,%hi(symbol)
1851 The final address is then $at + %lo(symbol). With 32-bit
1852 symbols we just need a preparatory LUI for normal mode and
1853 a preparatory LI and SLL for MIPS16. */
1854 return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2;
1856 case SYMBOL_GP_RELATIVE:
1857 /* Treat GP-relative accesses as taking a single instruction on
1858 MIPS16 too; the copy of $gp can often be shared. */
1861 case SYMBOL_PC_RELATIVE:
1862 /* PC-relative constants can be only be used with ADDIUPC,
1863 DADDIUPC, LWPC and LDPC. */
1864 if (mode == MAX_MACHINE_MODE
1865 || GET_MODE_SIZE (mode) == 4
1866 || GET_MODE_SIZE (mode) == 8)
1869 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
1872 case SYMBOL_GOT_DISP:
1873 /* The constant will have to be loaded from the GOT before it
1874 is used in an address. */
1875 if (mode != MAX_MACHINE_MODE)
1880 case SYMBOL_GOT_PAGE_OFST:
1881 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
1882 local/global classification is accurate. The worst cases are:
1884 (1) For local symbols when generating o32 or o64 code. The assembler
1890 ...and the final address will be $at + %lo(symbol).
1892 (2) For global symbols when -mxgot. The assembler will use:
1894 lui $at,%got_hi(symbol)
1897 ...and the final address will be $at + %got_lo(symbol). */
1900 case SYMBOL_GOTOFF_PAGE:
1901 case SYMBOL_GOTOFF_DISP:
1902 case SYMBOL_GOTOFF_CALL:
1903 case SYMBOL_GOTOFF_LOADGP:
1904 case SYMBOL_64_HIGH:
1910 case SYMBOL_GOTTPREL:
1913 /* A 16-bit constant formed by a single relocation, or a 32-bit
1914 constant formed from a high 16-bit relocation and a low 16-bit
1915 relocation. Use mips_split_p to determine which. 32-bit
1916 constants need an "lui; addiu" sequence for normal mode and
1917 an "li; sll; addiu" sequence for MIPS16 mode. */
1918 return !mips_split_p[type] ? 1 : TARGET_MIPS16 ? 3 : 2;
1921 /* We don't treat a bare TLS symbol as a constant. */
1927 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
1928 to load symbols of type TYPE into a register. Return 0 if the given
1929 type of symbol cannot be used as an immediate operand.
1931 Otherwise, return the number of instructions needed to load or store
1932 values of mode MODE to or from addresses of type TYPE. Return 0 if
1933 the given type of symbol is not valid in addresses.
1935 In both cases, treat extended MIPS16 instructions as two instructions. */
1938 mips_symbol_insns (enum mips_symbol_type type, enum machine_mode mode)
1940 return mips_symbol_insns_1 (type, mode) * (TARGET_MIPS16 ? 2 : 1);
1943 /* A for_each_rtx callback. Stop the search if *X references a
1944 thread-local symbol. */
1947 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1949 return mips_tls_symbol_p (*x);
1952 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1955 mips_cannot_force_const_mem (enum machine_mode mode, rtx x)
1957 enum mips_symbol_type type;
1960 /* There is no assembler syntax for expressing an address-sized
1962 if (GET_CODE (x) == HIGH)
1965 /* As an optimization, reject constants that mips_legitimize_move
1968 Suppose we have a multi-instruction sequence that loads constant C
1969 into register R. If R does not get allocated a hard register, and
1970 R is used in an operand that allows both registers and memory
1971 references, reload will consider forcing C into memory and using
1972 one of the instruction's memory alternatives. Returning false
1973 here will force it to use an input reload instead. */
1974 if (CONST_INT_P (x) && mips_legitimate_constant_p (mode, x))
1977 split_const (x, &base, &offset);
1978 if (mips_symbolic_constant_p (base, SYMBOL_CONTEXT_LEA, &type))
1980 /* See whether we explicitly want these symbols in the pool. */
1981 if (mips_use_pcrel_pool_p[(int) type])
1984 /* The same optimization as for CONST_INT. */
1985 if (SMALL_INT (offset) && mips_symbol_insns (type, MAX_MACHINE_MODE) > 0)
1988 /* If MIPS16 constant pools live in the text section, they should
1989 not refer to anything that might need run-time relocation. */
1990 if (TARGET_MIPS16_PCREL_LOADS && mips_got_symbol_type_p (type))
1994 /* TLS symbols must be computed by mips_legitimize_move. */
1995 if (for_each_rtx (&x, &mips_tls_symbol_ref_1, NULL))
2001 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
2002 constants when we're using a per-function constant pool. */
2005 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
2006 const_rtx x ATTRIBUTE_UNUSED)
2008 return !TARGET_MIPS16_PCREL_LOADS;
2011 /* Return true if register REGNO is a valid base register for mode MODE.
2012 STRICT_P is true if REG_OK_STRICT is in effect. */
2015 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode,
2018 if (!HARD_REGISTER_NUM_P (regno))
2022 regno = reg_renumber[regno];
2025 /* These fake registers will be eliminated to either the stack or
2026 hard frame pointer, both of which are usually valid base registers.
2027 Reload deals with the cases where the eliminated form isn't valid. */
2028 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
2031 /* In MIPS16 mode, the stack pointer can only address word and doubleword
2032 values, nothing smaller. There are two problems here:
2034 (a) Instantiating virtual registers can introduce new uses of the
2035 stack pointer. If these virtual registers are valid addresses,
2036 the stack pointer should be too.
2038 (b) Most uses of the stack pointer are not made explicit until
2039 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
2040 We don't know until that stage whether we'll be eliminating to the
2041 stack pointer (which needs the restriction) or the hard frame
2042 pointer (which doesn't).
2044 All in all, it seems more consistent to only enforce this restriction
2045 during and after reload. */
2046 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
2047 return !strict_p || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
2049 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
2052 /* Return true if X is a valid base register for mode MODE.
2053 STRICT_P is true if REG_OK_STRICT is in effect. */
2056 mips_valid_base_register_p (rtx x, enum machine_mode mode, bool strict_p)
2058 if (!strict_p && GET_CODE (x) == SUBREG)
2062 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p));
2065 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2066 can address a value of mode MODE. */
2069 mips_valid_offset_p (rtx x, enum machine_mode mode)
2071 /* Check that X is a signed 16-bit number. */
2072 if (!const_arith_operand (x, Pmode))
2075 /* We may need to split multiword moves, so make sure that every word
2077 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2078 && !SMALL_OPERAND (INTVAL (x) + GET_MODE_SIZE (mode) - UNITS_PER_WORD))
2084 /* Return true if a LO_SUM can address a value of mode MODE when the
2085 LO_SUM symbol has type SYMBOL_TYPE. */
2088 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type, enum machine_mode mode)
2090 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2092 if (mips_symbol_insns (symbol_type, mode) == 0)
2095 /* Check that there is a known low-part relocation. */
2096 if (mips_lo_relocs[symbol_type] == NULL)
2099 /* We may need to split multiword moves, so make sure that each word
2100 can be accessed without inducing a carry. This is mainly needed
2101 for o64, which has historically only guaranteed 64-bit alignment
2102 for 128-bit types. */
2103 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2104 && GET_MODE_BITSIZE (mode) > GET_MODE_ALIGNMENT (mode))
2110 /* Return true if X is a valid address for machine mode MODE. If it is,
2111 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2115 mips_classify_address (struct mips_address_info *info, rtx x,
2116 enum machine_mode mode, bool strict_p)
2118 switch (GET_CODE (x))
2122 info->type = ADDRESS_REG;
2124 info->offset = const0_rtx;
2125 return mips_valid_base_register_p (info->reg, mode, strict_p);
2128 info->type = ADDRESS_REG;
2129 info->reg = XEXP (x, 0);
2130 info->offset = XEXP (x, 1);
2131 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2132 && mips_valid_offset_p (info->offset, mode));
2135 info->type = ADDRESS_LO_SUM;
2136 info->reg = XEXP (x, 0);
2137 info->offset = XEXP (x, 1);
2138 /* We have to trust the creator of the LO_SUM to do something vaguely
2139 sane. Target-independent code that creates a LO_SUM should also
2140 create and verify the matching HIGH. Target-independent code that
2141 adds an offset to a LO_SUM must prove that the offset will not
2142 induce a carry. Failure to do either of these things would be
2143 a bug, and we are not required to check for it here. The MIPS
2144 backend itself should only create LO_SUMs for valid symbolic
2145 constants, with the high part being either a HIGH or a copy
2148 = mips_classify_symbolic_expression (info->offset, SYMBOL_CONTEXT_MEM);
2149 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2150 && mips_valid_lo_sum_p (info->symbol_type, mode));
2153 /* Small-integer addresses don't occur very often, but they
2154 are legitimate if $0 is a valid base register. */
2155 info->type = ADDRESS_CONST_INT;
2156 return !TARGET_MIPS16 && SMALL_INT (x);
2161 info->type = ADDRESS_SYMBOLIC;
2162 return (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_MEM,
2164 && mips_symbol_insns (info->symbol_type, mode) > 0
2165 && !mips_split_p[info->symbol_type]);
2172 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2175 mips_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
2177 struct mips_address_info addr;
2179 return mips_classify_address (&addr, x, mode, strict_p);
2182 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
2185 mips_stack_address_p (rtx x, enum machine_mode mode)
2187 struct mips_address_info addr;
2189 return (mips_classify_address (&addr, x, mode, false)
2190 && addr.type == ADDRESS_REG
2191 && addr.reg == stack_pointer_rtx);
2194 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2195 address instruction. Note that such addresses are not considered
2196 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2197 is so restricted. */
2200 mips_lwxs_address_p (rtx addr)
2203 && GET_CODE (addr) == PLUS
2204 && REG_P (XEXP (addr, 1)))
2206 rtx offset = XEXP (addr, 0);
2207 if (GET_CODE (offset) == MULT
2208 && REG_P (XEXP (offset, 0))
2209 && CONST_INT_P (XEXP (offset, 1))
2210 && INTVAL (XEXP (offset, 1)) == 4)
2216 /* Return true if ADDR matches the pattern for the L{B,H,W,D}{,U}X load
2217 indexed address instruction. Note that such addresses are
2218 not considered legitimate in the TARGET_LEGITIMATE_ADDRESS_P
2219 sense, because their use is so restricted. */
2222 mips_lx_address_p (rtx addr, enum machine_mode mode)
2224 if (GET_CODE (addr) != PLUS
2225 || !REG_P (XEXP (addr, 0))
2226 || !REG_P (XEXP (addr, 1)))
2228 if (ISA_HAS_LBX && mode == QImode)
2230 if (ISA_HAS_LHX && mode == HImode)
2232 if (ISA_HAS_LWX && mode == SImode)
2234 if (ISA_HAS_LDX && mode == DImode)
2239 /* Return true if a value at OFFSET bytes from base register BASE can be
2240 accessed using an unextended MIPS16 instruction. MODE is the mode of
2243 Usually the offset in an unextended instruction is a 5-bit field.
2244 The offset is unsigned and shifted left once for LH and SH, twice
2245 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2246 an 8-bit immediate field that's shifted left twice. */
2249 mips16_unextended_reference_p (enum machine_mode mode, rtx base,
2250 unsigned HOST_WIDE_INT offset)
2252 if (mode != BLKmode && offset % GET_MODE_SIZE (mode) == 0)
2254 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
2255 return offset < 256U * GET_MODE_SIZE (mode);
2256 return offset < 32U * GET_MODE_SIZE (mode);
2261 /* Return the number of instructions needed to load or store a value
2262 of mode MODE at address X. Return 0 if X isn't valid for MODE.
2263 Assume that multiword moves may need to be split into word moves
2264 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2267 For MIPS16 code, count extended instructions as two instructions. */
2270 mips_address_insns (rtx x, enum machine_mode mode, bool might_split_p)
2272 struct mips_address_info addr;
2275 /* BLKmode is used for single unaligned loads and stores and should
2276 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2277 meaningless, so we have to single it out as a special case one way
2279 if (mode != BLKmode && might_split_p)
2280 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2284 if (mips_classify_address (&addr, x, mode, false))
2289 && !mips16_unextended_reference_p (mode, addr.reg,
2290 UINTVAL (addr.offset)))
2294 case ADDRESS_LO_SUM:
2295 return TARGET_MIPS16 ? factor * 2 : factor;
2297 case ADDRESS_CONST_INT:
2300 case ADDRESS_SYMBOLIC:
2301 return factor * mips_symbol_insns (addr.symbol_type, mode);
2306 /* Return the number of instructions needed to load constant X.
2307 Return 0 if X isn't a valid constant. */
2310 mips_const_insns (rtx x)
2312 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2313 enum mips_symbol_type symbol_type;
2316 switch (GET_CODE (x))
2319 if (!mips_symbolic_constant_p (XEXP (x, 0), SYMBOL_CONTEXT_LEA,
2321 || !mips_split_p[symbol_type])
2324 /* This is simply an LUI for normal mode. It is an extended
2325 LI followed by an extended SLL for MIPS16. */
2326 return TARGET_MIPS16 ? 4 : 1;
2330 /* Unsigned 8-bit constants can be loaded using an unextended
2331 LI instruction. Unsigned 16-bit constants can be loaded
2332 using an extended LI. Negative constants must be loaded
2333 using LI and then negated. */
2334 return (IN_RANGE (INTVAL (x), 0, 255) ? 1
2335 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
2336 : IN_RANGE (-INTVAL (x), 0, 255) ? 2
2337 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
2340 return mips_build_integer (codes, INTVAL (x));
2344 /* Allow zeros for normal mode, where we can use $0. */
2345 return !TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0;
2351 /* See if we can refer to X directly. */
2352 if (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_LEA, &symbol_type))
2353 return mips_symbol_insns (symbol_type, MAX_MACHINE_MODE);
2355 /* Otherwise try splitting the constant into a base and offset.
2356 If the offset is a 16-bit value, we can load the base address
2357 into a register and then use (D)ADDIU to add in the offset.
2358 If the offset is larger, we can load the base and offset
2359 into separate registers and add them together with (D)ADDU.
2360 However, the latter is only possible before reload; during
2361 and after reload, we must have the option of forcing the
2362 constant into the pool instead. */
2363 split_const (x, &x, &offset);
2366 int n = mips_const_insns (x);
2369 if (SMALL_INT (offset))
2371 else if (!targetm.cannot_force_const_mem (GET_MODE (x), x))
2372 return n + 1 + mips_build_integer (codes, INTVAL (offset));
2379 return mips_symbol_insns (mips_classify_symbol (x, SYMBOL_CONTEXT_LEA),
2387 /* X is a doubleword constant that can be handled by splitting it into
2388 two words and loading each word separately. Return the number of
2389 instructions required to do this. */
2392 mips_split_const_insns (rtx x)
2394 unsigned int low, high;
2396 low = mips_const_insns (mips_subword (x, false));
2397 high = mips_const_insns (mips_subword (x, true));
2398 gcc_assert (low > 0 && high > 0);
2402 /* Return the number of instructions needed to implement INSN,
2403 given that it loads from or stores to MEM. Count extended
2404 MIPS16 instructions as two instructions. */
2407 mips_load_store_insns (rtx mem, rtx insn)
2409 enum machine_mode mode;
2413 gcc_assert (MEM_P (mem));
2414 mode = GET_MODE (mem);
2416 /* Try to prove that INSN does not need to be split. */
2417 might_split_p = GET_MODE_SIZE (mode) > UNITS_PER_WORD;
2420 set = single_set (insn);
2421 if (set && !mips_split_move_insn_p (SET_DEST (set), SET_SRC (set), insn))
2422 might_split_p = false;
2425 return mips_address_insns (XEXP (mem, 0), mode, might_split_p);
2428 /* Return the number of instructions needed for an integer division. */
2431 mips_idiv_insns (void)
2436 if (TARGET_CHECK_ZERO_DIV)
2438 if (GENERATE_DIVIDE_TRAPS)
2444 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
2449 /* Emit a move from SRC to DEST. Assume that the move expanders can
2450 handle all moves if !can_create_pseudo_p (). The distinction is
2451 important because, unlike emit_move_insn, the move expanders know
2452 how to force Pmode objects into the constant pool even when the
2453 constant pool address is not itself legitimate. */
2456 mips_emit_move (rtx dest, rtx src)
2458 return (can_create_pseudo_p ()
2459 ? emit_move_insn (dest, src)
2460 : emit_move_insn_1 (dest, src));
2463 /* Emit a move from SRC to DEST, splitting compound moves into individual
2464 instructions. SPLIT_TYPE is the type of split to perform. */
2467 mips_emit_move_or_split (rtx dest, rtx src, enum mips_split_type split_type)
2469 if (mips_split_move_p (dest, src, split_type))
2470 mips_split_move (dest, src, split_type);
2472 mips_emit_move (dest, src);
2475 /* Emit an instruction of the form (set TARGET (CODE OP0)). */
2478 mips_emit_unary (enum rtx_code code, rtx target, rtx op0)
2480 emit_insn (gen_rtx_SET (VOIDmode, target,
2481 gen_rtx_fmt_e (code, GET_MODE (op0), op0)));
2484 /* Compute (CODE OP0) and store the result in a new register of mode MODE.
2485 Return that new register. */
2488 mips_force_unary (enum machine_mode mode, enum rtx_code code, rtx op0)
2492 reg = gen_reg_rtx (mode);
2493 mips_emit_unary (code, reg, op0);
2497 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2500 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
2502 emit_insn (gen_rtx_SET (VOIDmode, target,
2503 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
2506 /* Compute (CODE OP0 OP1) and store the result in a new register
2507 of mode MODE. Return that new register. */
2510 mips_force_binary (enum machine_mode mode, enum rtx_code code, rtx op0, rtx op1)
2514 reg = gen_reg_rtx (mode);
2515 mips_emit_binary (code, reg, op0, op1);
2519 /* Copy VALUE to a register and return that register. If new pseudos
2520 are allowed, copy it into a new register, otherwise use DEST. */
2523 mips_force_temporary (rtx dest, rtx value)
2525 if (can_create_pseudo_p ())
2526 return force_reg (Pmode, value);
2529 mips_emit_move (dest, value);
2534 /* Emit a call sequence with call pattern PATTERN and return the call
2535 instruction itself (which is not necessarily the last instruction
2536 emitted). ORIG_ADDR is the original, unlegitimized address,
2537 ADDR is the legitimized form, and LAZY_P is true if the call
2538 address is lazily-bound. */
2541 mips_emit_call_insn (rtx pattern, rtx orig_addr, rtx addr, bool lazy_p)
2545 insn = emit_call_insn (pattern);
2547 if (TARGET_MIPS16 && mips_use_pic_fn_addr_reg_p (orig_addr))
2549 /* MIPS16 JALRs only take MIPS16 registers. If the target
2550 function requires $25 to be valid on entry, we must copy it
2551 there separately. The move instruction can be put in the
2552 call's delay slot. */
2553 reg = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
2554 emit_insn_before (gen_move_insn (reg, addr), insn);
2555 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
2559 /* Lazy-binding stubs require $gp to be valid on entry. */
2560 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
2564 /* See the comment above load_call<mode> for details. */
2565 use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
2566 gen_rtx_REG (Pmode, GOT_VERSION_REGNUM));
2567 emit_insn (gen_update_got_version ());
2572 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2573 then add CONST_INT OFFSET to the result. */
2576 mips_unspec_address_offset (rtx base, rtx offset,
2577 enum mips_symbol_type symbol_type)
2579 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
2580 UNSPEC_ADDRESS_FIRST + symbol_type);
2581 if (offset != const0_rtx)
2582 base = gen_rtx_PLUS (Pmode, base, offset);
2583 return gen_rtx_CONST (Pmode, base);
2586 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2587 type SYMBOL_TYPE. */
2590 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
2594 split_const (address, &base, &offset);
2595 return mips_unspec_address_offset (base, offset, symbol_type);
2598 /* If OP is an UNSPEC address, return the address to which it refers,
2599 otherwise return OP itself. */
2602 mips_strip_unspec_address (rtx op)
2606 split_const (op, &base, &offset);
2607 if (UNSPEC_ADDRESS_P (base))
2608 op = plus_constant (Pmode, UNSPEC_ADDRESS (base), INTVAL (offset));
2612 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2613 high part to BASE and return the result. Just return BASE otherwise.
2614 TEMP is as for mips_force_temporary.
2616 The returned expression can be used as the first operand to a LO_SUM. */
2619 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
2620 enum mips_symbol_type symbol_type)
2622 if (mips_split_p[symbol_type])
2624 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
2625 addr = mips_force_temporary (temp, addr);
2626 base = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
2631 /* Return an instruction that copies $gp into register REG. We want
2632 GCC to treat the register's value as constant, so that its value
2633 can be rematerialized on demand. */
2636 gen_load_const_gp (rtx reg)
2638 return PMODE_INSN (gen_load_const_gp, (reg));
2641 /* Return a pseudo register that contains the value of $gp throughout
2642 the current function. Such registers are needed by MIPS16 functions,
2643 for which $gp itself is not a valid base register or addition operand. */
2646 mips16_gp_pseudo_reg (void)
2648 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
2652 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
2654 push_topmost_sequence ();
2656 scan = get_insns ();
2657 while (NEXT_INSN (scan) && !INSN_P (NEXT_INSN (scan)))
2658 scan = NEXT_INSN (scan);
2660 insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
2661 insn = emit_insn_after (insn, scan);
2662 INSN_LOCATION (insn) = 0;
2664 pop_topmost_sequence ();
2667 return cfun->machine->mips16_gp_pseudo_rtx;
2670 /* Return a base register that holds pic_offset_table_rtx.
2671 TEMP, if nonnull, is a scratch Pmode base register. */
2674 mips_pic_base_register (rtx temp)
2677 return pic_offset_table_rtx;
2679 if (currently_expanding_to_rtl)
2680 return mips16_gp_pseudo_reg ();
2682 if (can_create_pseudo_p ())
2683 temp = gen_reg_rtx (Pmode);
2686 /* The first post-reload split exposes all references to $gp
2687 (both uses and definitions). All references must remain
2688 explicit after that point.
2690 It is safe to introduce uses of $gp at any time, so for
2691 simplicity, we do that before the split too. */
2692 mips_emit_move (temp, pic_offset_table_rtx);
2694 emit_insn (gen_load_const_gp (temp));
2698 /* Return the RHS of a load_call<mode> insn. */
2701 mips_unspec_call (rtx reg, rtx symbol)
2705 vec = gen_rtvec (3, reg, symbol, gen_rtx_REG (SImode, GOT_VERSION_REGNUM));
2706 return gen_rtx_UNSPEC (Pmode, vec, UNSPEC_LOAD_CALL);
2709 /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol
2710 reference. Return NULL_RTX otherwise. */
2713 mips_strip_unspec_call (rtx src)
2715 if (GET_CODE (src) == UNSPEC && XINT (src, 1) == UNSPEC_LOAD_CALL)
2716 return mips_strip_unspec_address (XVECEXP (src, 0, 1));
2720 /* Create and return a GOT reference of type TYPE for address ADDR.
2721 TEMP, if nonnull, is a scratch Pmode base register. */
2724 mips_got_load (rtx temp, rtx addr, enum mips_symbol_type type)
2726 rtx base, high, lo_sum_symbol;
2728 base = mips_pic_base_register (temp);
2730 /* If we used the temporary register to load $gp, we can't use
2731 it for the high part as well. */
2732 if (temp != NULL && reg_overlap_mentioned_p (base, temp))
2735 high = mips_unspec_offset_high (temp, base, addr, type);
2736 lo_sum_symbol = mips_unspec_address (addr, type);
2738 if (type == SYMBOL_GOTOFF_CALL)
2739 return mips_unspec_call (high, lo_sum_symbol);
2741 return PMODE_INSN (gen_unspec_got, (high, lo_sum_symbol));
2744 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2745 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2746 constant in that context and can be split into high and low parts.
2747 If so, and if LOW_OUT is nonnull, emit the high part and store the
2748 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
2750 TEMP is as for mips_force_temporary and is used to load the high
2751 part into a register.
2753 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
2754 a legitimize SET_SRC for an .md pattern, otherwise the low part
2755 is guaranteed to be a legitimate address for mode MODE. */
2758 mips_split_symbol (rtx temp, rtx addr, enum machine_mode mode, rtx *low_out)
2760 enum mips_symbol_context context;
2761 enum mips_symbol_type symbol_type;
2764 context = (mode == MAX_MACHINE_MODE
2765 ? SYMBOL_CONTEXT_LEA
2766 : SYMBOL_CONTEXT_MEM);
2767 if (GET_CODE (addr) == HIGH && context == SYMBOL_CONTEXT_LEA)
2769 addr = XEXP (addr, 0);
2770 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2771 && mips_symbol_insns (symbol_type, mode) > 0
2772 && mips_split_hi_p[symbol_type])
2775 switch (symbol_type)
2777 case SYMBOL_GOT_PAGE_OFST:
2778 /* The high part of a page/ofst pair is loaded from the GOT. */
2779 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_PAGE);
2790 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2791 && mips_symbol_insns (symbol_type, mode) > 0
2792 && mips_split_p[symbol_type])
2795 switch (symbol_type)
2797 case SYMBOL_GOT_DISP:
2798 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
2799 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_DISP);
2802 case SYMBOL_GP_RELATIVE:
2803 high = mips_pic_base_register (temp);
2804 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2808 high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
2809 high = mips_force_temporary (temp, high);
2810 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2819 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2820 mips_force_temporary; it is only needed when OFFSET is not a
2824 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
2826 if (!SMALL_OPERAND (offset))
2832 /* Load the full offset into a register so that we can use
2833 an unextended instruction for the address itself. */
2834 high = GEN_INT (offset);
2839 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
2840 The addition inside the macro CONST_HIGH_PART may cause an
2841 overflow, so we need to force a sign-extension check. */
2842 high = gen_int_mode (CONST_HIGH_PART (offset), Pmode);
2843 offset = CONST_LOW_PART (offset);
2845 high = mips_force_temporary (temp, high);
2846 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
2848 return plus_constant (Pmode, reg, offset);
2851 /* The __tls_get_attr symbol. */
2852 static GTY(()) rtx mips_tls_symbol;
2854 /* Return an instruction sequence that calls __tls_get_addr. SYM is
2855 the TLS symbol we are referencing and TYPE is the symbol type to use
2856 (either global dynamic or local dynamic). V0 is an RTX for the
2857 return value location. */
2860 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
2864 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
2866 if (!mips_tls_symbol)
2867 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
2869 loc = mips_unspec_address (sym, type);
2873 emit_insn (gen_rtx_SET (Pmode, a0,
2874 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
2875 insn = mips_expand_call (MIPS_CALL_NORMAL, v0, mips_tls_symbol,
2876 const0_rtx, NULL_RTX, false);
2877 RTL_CONST_CALL_P (insn) = 1;
2878 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
2879 insn = get_insns ();
2886 /* Return a pseudo register that contains the current thread pointer. */
2889 mips_expand_thread_pointer (rtx tp)
2895 mips_need_mips16_rdhwr_p = true;
2896 fn = mips16_stub_function ("__mips16_rdhwr");
2897 SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_LOCAL;
2898 if (!call_insn_operand (fn, VOIDmode))
2899 fn = force_reg (Pmode, fn);
2900 emit_insn (PMODE_INSN (gen_tls_get_tp_mips16, (tp, fn)));
2903 emit_insn (PMODE_INSN (gen_tls_get_tp, (tp)));
2910 return mips_expand_thread_pointer (gen_reg_rtx (Pmode));
2913 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
2914 its address. The return value will be both a valid address and a valid
2915 SET_SRC (either a REG or a LO_SUM). */
2918 mips_legitimize_tls_address (rtx loc)
2920 rtx dest, insn, v0, tp, tmp1, tmp2, eqv, offset;
2921 enum tls_model model;
2923 model = SYMBOL_REF_TLS_MODEL (loc);
2924 /* Only TARGET_ABICALLS code can have more than one module; other
2925 code must be be static and should not use a GOT. All TLS models
2926 reduce to local exec in this situation. */
2927 if (!TARGET_ABICALLS)
2928 model = TLS_MODEL_LOCAL_EXEC;
2932 case TLS_MODEL_GLOBAL_DYNAMIC:
2933 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2934 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
2935 dest = gen_reg_rtx (Pmode);
2936 emit_libcall_block (insn, dest, v0, loc);
2939 case TLS_MODEL_LOCAL_DYNAMIC:
2940 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2941 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
2942 tmp1 = gen_reg_rtx (Pmode);
2944 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2945 share the LDM result with other LD model accesses. */
2946 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2948 emit_libcall_block (insn, tmp1, v0, eqv);
2950 offset = mips_unspec_address (loc, SYMBOL_DTPREL);
2951 if (mips_split_p[SYMBOL_DTPREL])
2953 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
2954 dest = gen_rtx_LO_SUM (Pmode, tmp2, offset);
2957 dest = expand_binop (Pmode, add_optab, tmp1, offset,
2958 0, 0, OPTAB_DIRECT);
2961 case TLS_MODEL_INITIAL_EXEC:
2962 tp = mips_get_tp ();
2963 tmp1 = gen_reg_rtx (Pmode);
2964 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
2965 if (Pmode == DImode)
2966 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
2968 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
2969 dest = gen_reg_rtx (Pmode);
2970 emit_insn (gen_add3_insn (dest, tmp1, tp));
2973 case TLS_MODEL_LOCAL_EXEC:
2974 tmp1 = mips_get_tp ();
2975 offset = mips_unspec_address (loc, SYMBOL_TPREL);
2976 if (mips_split_p[SYMBOL_TPREL])
2978 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_TPREL);
2979 dest = gen_rtx_LO_SUM (Pmode, tmp2, offset);
2982 dest = expand_binop (Pmode, add_optab, tmp1, offset,
2983 0, 0, OPTAB_DIRECT);
2992 /* If X is not a valid address for mode MODE, force it into a register. */
2995 mips_force_address (rtx x, enum machine_mode mode)
2997 if (!mips_legitimate_address_p (mode, x, false))
2998 x = force_reg (Pmode, x);
3002 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
3003 be legitimized in a way that the generic machinery might not expect,
3004 return a new address, otherwise return NULL. MODE is the mode of
3005 the memory being accessed. */
3008 mips_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3009 enum machine_mode mode)
3012 HOST_WIDE_INT offset;
3014 if (mips_tls_symbol_p (x))
3015 return mips_legitimize_tls_address (x);
3017 /* See if the address can split into a high part and a LO_SUM. */
3018 if (mips_split_symbol (NULL, x, mode, &addr))
3019 return mips_force_address (addr, mode);
3021 /* Handle BASE + OFFSET using mips_add_offset. */
3022 mips_split_plus (x, &base, &offset);
3025 if (!mips_valid_base_register_p (base, mode, false))
3026 base = copy_to_mode_reg (Pmode, base);
3027 addr = mips_add_offset (NULL, base, offset);
3028 return mips_force_address (addr, mode);
3034 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
3037 mips_move_integer (rtx temp, rtx dest, unsigned HOST_WIDE_INT value)
3039 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
3040 enum machine_mode mode;
3041 unsigned int i, num_ops;
3044 mode = GET_MODE (dest);
3045 num_ops = mips_build_integer (codes, value);
3047 /* Apply each binary operation to X. Invariant: X is a legitimate
3048 source operand for a SET pattern. */
3049 x = GEN_INT (codes[0].value);
3050 for (i = 1; i < num_ops; i++)
3052 if (!can_create_pseudo_p ())
3054 emit_insn (gen_rtx_SET (VOIDmode, temp, x));
3058 x = force_reg (mode, x);
3059 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
3062 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
3065 /* Subroutine of mips_legitimize_move. Move constant SRC into register
3066 DEST given that SRC satisfies immediate_operand but doesn't satisfy
3070 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
3074 /* Split moves of big integers into smaller pieces. */
3075 if (splittable_const_int_operand (src, mode))
3077 mips_move_integer (dest, dest, INTVAL (src));
3081 /* Split moves of symbolic constants into high/low pairs. */
3082 if (mips_split_symbol (dest, src, MAX_MACHINE_MODE, &src))
3084 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
3088 /* Generate the appropriate access sequences for TLS symbols. */
3089 if (mips_tls_symbol_p (src))
3091 mips_emit_move (dest, mips_legitimize_tls_address (src));
3095 /* If we have (const (plus symbol offset)), and that expression cannot
3096 be forced into memory, load the symbol first and add in the offset.
3097 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
3098 forced into memory, as it usually produces better code. */
3099 split_const (src, &base, &offset);
3100 if (offset != const0_rtx
3101 && (targetm.cannot_force_const_mem (mode, src)
3102 || (!TARGET_MIPS16 && can_create_pseudo_p ())))
3104 base = mips_force_temporary (dest, base);
3105 mips_emit_move (dest, mips_add_offset (NULL, base, INTVAL (offset)));
3109 src = force_const_mem (mode, src);
3111 /* When using explicit relocs, constant pool references are sometimes
3112 not legitimate addresses. */
3113 mips_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0));
3114 mips_emit_move (dest, src);
3117 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
3118 sequence that is valid. */
3121 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
3123 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
3125 mips_emit_move (dest, force_reg (mode, src));
3129 /* We need to deal with constants that would be legitimate
3130 immediate_operands but aren't legitimate move_operands. */
3131 if (CONSTANT_P (src) && !move_operand (src, mode))
3133 mips_legitimize_const_move (mode, dest, src);
3134 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
3140 /* Return true if value X in context CONTEXT is a small-data address
3141 that can be rewritten as a LO_SUM. */
3144 mips_rewrite_small_data_p (rtx x, enum mips_symbol_context context)
3146 enum mips_symbol_type symbol_type;
3148 return (mips_lo_relocs[SYMBOL_GP_RELATIVE]
3149 && !mips_split_p[SYMBOL_GP_RELATIVE]
3150 && mips_symbolic_constant_p (x, context, &symbol_type)
3151 && symbol_type == SYMBOL_GP_RELATIVE);
3154 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
3155 containing MEM, or null if none. */
3158 mips_small_data_pattern_1 (rtx *loc, void *data)
3160 enum mips_symbol_context context;
3162 /* Ignore things like "g" constraints in asms. We make no particular
3163 guarantee about which symbolic constants are acceptable as asm operands
3164 versus which must be forced into a GPR. */
3165 if (GET_CODE (*loc) == LO_SUM || GET_CODE (*loc) == ASM_OPERANDS)
3170 if (for_each_rtx (&XEXP (*loc, 0), mips_small_data_pattern_1, *loc))
3175 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3176 return mips_rewrite_small_data_p (*loc, context);
3179 /* Return true if OP refers to small data symbols directly, not through
3183 mips_small_data_pattern_p (rtx op)
3185 return for_each_rtx (&op, mips_small_data_pattern_1, NULL);
3188 /* A for_each_rtx callback, used by mips_rewrite_small_data.
3189 DATA is the containing MEM, or null if none. */
3192 mips_rewrite_small_data_1 (rtx *loc, void *data)
3194 enum mips_symbol_context context;
3198 for_each_rtx (&XEXP (*loc, 0), mips_rewrite_small_data_1, *loc);
3202 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3203 if (mips_rewrite_small_data_p (*loc, context))
3204 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
3206 if (GET_CODE (*loc) == LO_SUM)
3212 /* Rewrite instruction pattern PATTERN so that it refers to small data
3213 using explicit relocations. */
3216 mips_rewrite_small_data (rtx pattern)
3218 pattern = copy_insn (pattern);
3219 for_each_rtx (&pattern, mips_rewrite_small_data_1, NULL);
3223 /* We need a lot of little routines to check the range of MIPS16 immediate
3227 m16_check_op (rtx op, int low, int high, int mask)
3229 return (CONST_INT_P (op)
3230 && IN_RANGE (INTVAL (op), low, high)
3231 && (INTVAL (op) & mask) == 0);
3235 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3237 return m16_check_op (op, 0x1, 0x8, 0);
3241 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3243 return m16_check_op (op, -0x8, 0x7, 0);
3247 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3249 return m16_check_op (op, -0x7, 0x8, 0);
3253 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3255 return m16_check_op (op, -0x10, 0xf, 0);
3259 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3261 return m16_check_op (op, -0xf, 0x10, 0);
3265 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3267 return m16_check_op (op, -0x10 << 2, 0xf << 2, 3);
3271 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3273 return m16_check_op (op, -0xf << 2, 0x10 << 2, 3);
3277 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3279 return m16_check_op (op, -0x80, 0x7f, 0);
3283 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3285 return m16_check_op (op, -0x7f, 0x80, 0);
3289 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3291 return m16_check_op (op, 0x0, 0xff, 0);
3295 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3297 return m16_check_op (op, -0xff, 0x0, 0);
3301 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3303 return m16_check_op (op, -0x1, 0xfe, 0);
3307 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3309 return m16_check_op (op, 0x0, 0xff << 2, 3);
3313 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3315 return m16_check_op (op, -0xff << 2, 0x0, 3);
3319 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3321 return m16_check_op (op, -0x80 << 3, 0x7f << 3, 7);
3325 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3327 return m16_check_op (op, -0x7f << 3, 0x80 << 3, 7);
3330 /* The cost of loading values from the constant pool. It should be
3331 larger than the cost of any constant we want to synthesize inline. */
3332 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3334 /* Return the cost of X when used as an operand to the MIPS16 instruction
3335 that implements CODE. Return -1 if there is no such instruction, or if
3336 X is not a valid immediate operand for it. */
3339 mips16_constant_cost (int code, HOST_WIDE_INT x)
3346 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3347 other shifts are extended. The shift patterns truncate the shift
3348 count to the right size, so there are no out-of-range values. */
3349 if (IN_RANGE (x, 1, 8))
3351 return COSTS_N_INSNS (1);
3354 if (IN_RANGE (x, -128, 127))
3356 if (SMALL_OPERAND (x))
3357 return COSTS_N_INSNS (1);
3361 /* Like LE, but reject the always-true case. */
3365 /* We add 1 to the immediate and use SLT. */
3368 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3371 if (IN_RANGE (x, 0, 255))
3373 if (SMALL_OPERAND_UNSIGNED (x))
3374 return COSTS_N_INSNS (1);
3379 /* Equality comparisons with 0 are cheap. */
3389 /* Return true if there is a non-MIPS16 instruction that implements CODE
3390 and if that instruction accepts X as an immediate operand. */
3393 mips_immediate_operand_p (int code, HOST_WIDE_INT x)
3400 /* All shift counts are truncated to a valid constant. */
3405 /* Likewise rotates, if the target supports rotates at all. */
3411 /* These instructions take 16-bit unsigned immediates. */
3412 return SMALL_OPERAND_UNSIGNED (x);
3417 /* These instructions take 16-bit signed immediates. */
3418 return SMALL_OPERAND (x);
3424 /* The "immediate" forms of these instructions are really
3425 implemented as comparisons with register 0. */
3430 /* Likewise, meaning that the only valid immediate operand is 1. */
3434 /* We add 1 to the immediate and use SLT. */
3435 return SMALL_OPERAND (x + 1);
3438 /* Likewise SLTU, but reject the always-true case. */
3439 return SMALL_OPERAND (x + 1) && x + 1 != 0;
3443 /* The bit position and size are immediate operands. */
3444 return ISA_HAS_EXT_INS;
3447 /* By default assume that $0 can be used for 0. */
3452 /* Return the cost of binary operation X, given that the instruction
3453 sequence for a word-sized or smaller operation has cost SINGLE_COST
3454 and that the sequence of a double-word operation has cost DOUBLE_COST.
3455 If SPEED is true, optimize for speed otherwise optimize for size. */
3458 mips_binary_cost (rtx x, int single_cost, int double_cost, bool speed)
3462 if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2)
3467 + set_src_cost (XEXP (x, 0), speed)
3468 + rtx_cost (XEXP (x, 1), GET_CODE (x), 1, speed));
3471 /* Return the cost of floating-point multiplications of mode MODE. */
3474 mips_fp_mult_cost (enum machine_mode mode)
3476 return mode == DFmode ? mips_cost->fp_mult_df : mips_cost->fp_mult_sf;
3479 /* Return the cost of floating-point divisions of mode MODE. */
3482 mips_fp_div_cost (enum machine_mode mode)
3484 return mode == DFmode ? mips_cost->fp_div_df : mips_cost->fp_div_sf;
3487 /* Return the cost of sign-extending OP to mode MODE, not including the
3488 cost of OP itself. */
3491 mips_sign_extend_cost (enum machine_mode mode, rtx op)
3494 /* Extended loads are as cheap as unextended ones. */
3497 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3498 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3501 if (ISA_HAS_SEB_SEH || GENERATE_MIPS16E)
3502 /* We can use SEB or SEH. */
3503 return COSTS_N_INSNS (1);
3505 /* We need to use a shift left and a shift right. */
3506 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3509 /* Return the cost of zero-extending OP to mode MODE, not including the
3510 cost of OP itself. */
3513 mips_zero_extend_cost (enum machine_mode mode, rtx op)
3516 /* Extended loads are as cheap as unextended ones. */
3519 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3520 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3521 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3523 if (GENERATE_MIPS16E)
3524 /* We can use ZEB or ZEH. */
3525 return COSTS_N_INSNS (1);
3528 /* We need to load 0xff or 0xffff into a register and use AND. */
3529 return COSTS_N_INSNS (GET_MODE (op) == QImode ? 2 : 3);
3531 /* We can use ANDI. */
3532 return COSTS_N_INSNS (1);
3535 /* Return the cost of moving between two registers of mode MODE,
3536 assuming that the move will be in pieces of at most UNITS bytes. */
3539 mips_set_reg_reg_piece_cost (enum machine_mode mode, unsigned int units)
3541 return COSTS_N_INSNS ((GET_MODE_SIZE (mode) + units - 1) / units);
3544 /* Return the cost of moving between two registers of mode MODE. */
3547 mips_set_reg_reg_cost (enum machine_mode mode)
3549 switch (GET_MODE_CLASS (mode))
3552 return mips_set_reg_reg_piece_cost (mode, GET_MODE_SIZE (CCmode));
3555 case MODE_COMPLEX_FLOAT:
3556 case MODE_VECTOR_FLOAT:
3557 if (TARGET_HARD_FLOAT)
3558 return mips_set_reg_reg_piece_cost (mode, UNITS_PER_HWFPVALUE);
3562 return mips_set_reg_reg_piece_cost (mode, UNITS_PER_WORD);
3566 /* Return the cost of an operand X that can be trucated for free.
3567 SPEED says whether we're optimizing for size or speed. */
3570 mips_truncated_op_cost (rtx x, bool speed)
3572 if (GET_CODE (x) == TRUNCATE)
3574 return set_src_cost (x, speed);
3577 /* Implement TARGET_RTX_COSTS. */
3580 mips_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
3581 int *total, bool speed)
3583 enum machine_mode mode = GET_MODE (x);
3584 bool float_mode_p = FLOAT_MODE_P (mode);
3588 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3589 appear in the instruction stream, and the cost of a comparison is
3590 really the cost of the branch or scc condition. At the time of
3591 writing, GCC only uses an explicit outer COMPARE code when optabs
3592 is testing whether a constant is expensive enough to force into a
3593 register. We want optabs to pass such constants through the MIPS
3594 expanders instead, so make all constants very cheap here. */
3595 if (outer_code == COMPARE)
3597 gcc_assert (CONSTANT_P (x));
3605 /* Treat *clear_upper32-style ANDs as having zero cost in the
3606 second operand. The cost is entirely in the first operand.
3608 ??? This is needed because we would otherwise try to CSE
3609 the constant operand. Although that's the right thing for
3610 instructions that continue to be a register operation throughout
3611 compilation, it is disastrous for instructions that could
3612 later be converted into a memory operation. */
3614 && outer_code == AND
3615 && UINTVAL (x) == 0xffffffff)
3623 cost = mips16_constant_cost (outer_code, INTVAL (x));
3632 /* When not optimizing for size, we care more about the cost
3633 of hot code, and hot code is often in a loop. If a constant
3634 operand needs to be forced into a register, we will often be
3635 able to hoist the constant load out of the loop, so the load
3636 should not contribute to the cost. */
3637 if (speed || mips_immediate_operand_p (outer_code, INTVAL (x)))
3649 if (force_to_mem_operand (x, VOIDmode))
3651 *total = COSTS_N_INSNS (1);
3654 cost = mips_const_insns (x);
3657 /* If the constant is likely to be stored in a GPR, SETs of
3658 single-insn constants are as cheap as register sets; we
3659 never want to CSE them.
3661 Don't reduce the cost of storing a floating-point zero in
3662 FPRs. If we have a zero in an FPR for other reasons, we
3663 can get better cfg-cleanup and delayed-branch results by
3664 using it consistently, rather than using $0 sometimes and
3665 an FPR at other times. Also, moves between floating-point
3666 registers are sometimes cheaper than (D)MTC1 $0. */
3668 && outer_code == SET
3669 && !(float_mode_p && TARGET_HARD_FLOAT))
3671 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3672 want to CSE the constant itself. It is usually better to
3673 have N copies of the last operation in the sequence and one
3674 shared copy of the other operations. (Note that this is
3675 not true for MIPS16 code, where the final operation in the
3676 sequence is often an extended instruction.)
3678 Also, if we have a CONST_INT, we don't know whether it is
3679 for a word or doubleword operation, so we cannot rely on
3680 the result of mips_build_integer. */
3681 else if (!TARGET_MIPS16
3682 && (outer_code == SET || mode == VOIDmode))
3684 *total = COSTS_N_INSNS (cost);
3687 /* The value will need to be fetched from the constant pool. */
3688 *total = CONSTANT_POOL_COST;
3692 /* If the address is legitimate, return the number of
3693 instructions it needs. */
3695 cost = mips_address_insns (addr, mode, true);
3698 *total = COSTS_N_INSNS (cost + 1);
3701 /* Check for a scaled indexed address. */
3702 if (mips_lwxs_address_p (addr)
3703 || mips_lx_address_p (addr, mode))
3705 *total = COSTS_N_INSNS (2);
3708 /* Otherwise use the default handling. */
3712 *total = COSTS_N_INSNS (6);
3716 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1);
3720 /* Check for a *clear_upper32 pattern and treat it like a zero
3721 extension. See the pattern's comment for details. */
3724 && CONST_INT_P (XEXP (x, 1))
3725 && UINTVAL (XEXP (x, 1)) == 0xffffffff)
3727 *total = (mips_zero_extend_cost (mode, XEXP (x, 0))
3728 + set_src_cost (XEXP (x, 0), speed));
3731 if (ISA_HAS_CINS && CONST_INT_P (XEXP (x, 1)))
3733 rtx op = XEXP (x, 0);
3734 if (GET_CODE (op) == ASHIFT
3735 && CONST_INT_P (XEXP (op, 1))
3736 && mask_low_and_shift_p (mode, XEXP (x, 1), XEXP (op, 1), 32))
3738 *total = COSTS_N_INSNS (1) + set_src_cost (XEXP (op, 0), speed);
3747 /* Double-word operations use two single-word operations. */
3748 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (2),
3757 if (CONSTANT_P (XEXP (x, 1)))
3758 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3761 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (12),
3767 *total = mips_cost->fp_add;
3769 *total = COSTS_N_INSNS (4);
3773 /* Low-part immediates need an extended MIPS16 instruction. */
3774 *total = (COSTS_N_INSNS (TARGET_MIPS16 ? 2 : 1)
3775 + set_src_cost (XEXP (x, 0), speed));
3790 /* Branch comparisons have VOIDmode, so use the first operand's
3792 mode = GET_MODE (XEXP (x, 0));
3793 if (FLOAT_MODE_P (mode))
3795 *total = mips_cost->fp_add;
3798 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3804 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3805 && TARGET_FUSED_MADD
3806 && !HONOR_NANS (mode)
3807 && !HONOR_SIGNED_ZEROS (mode))
3809 /* See if we can use NMADD or NMSUB. See mips.md for the
3810 associated patterns. */
3811 rtx op0 = XEXP (x, 0);
3812 rtx op1 = XEXP (x, 1);
3813 if (GET_CODE (op0) == MULT && GET_CODE (XEXP (op0, 0)) == NEG)
3815 *total = (mips_fp_mult_cost (mode)
3816 + set_src_cost (XEXP (XEXP (op0, 0), 0), speed)
3817 + set_src_cost (XEXP (op0, 1), speed)
3818 + set_src_cost (op1, speed));
3821 if (GET_CODE (op1) == MULT)
3823 *total = (mips_fp_mult_cost (mode)
3824 + set_src_cost (op0, speed)
3825 + set_src_cost (XEXP (op1, 0), speed)
3826 + set_src_cost (XEXP (op1, 1), speed));
3835 /* If this is part of a MADD or MSUB, treat the PLUS as
3838 && TARGET_FUSED_MADD
3839 && GET_CODE (XEXP (x, 0)) == MULT)
3842 *total = mips_cost->fp_add;
3846 /* Double-word operations require three single-word operations and
3847 an SLTU. The MIPS16 version then needs to move the result of
3848 the SLTU from $24 to a MIPS16 register. */
3849 *total = mips_binary_cost (x, COSTS_N_INSNS (1),
3850 COSTS_N_INSNS (TARGET_MIPS16 ? 5 : 4),
3856 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3857 && TARGET_FUSED_MADD
3858 && !HONOR_NANS (mode)
3859 && HONOR_SIGNED_ZEROS (mode))
3861 /* See if we can use NMADD or NMSUB. See mips.md for the
3862 associated patterns. */
3863 rtx op = XEXP (x, 0);
3864 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
3865 && GET_CODE (XEXP (op, 0)) == MULT)
3867 *total = (mips_fp_mult_cost (mode)
3868 + set_src_cost (XEXP (XEXP (op, 0), 0), speed)
3869 + set_src_cost (XEXP (XEXP (op, 0), 1), speed)
3870 + set_src_cost (XEXP (op, 1), speed));
3876 *total = mips_cost->fp_add;
3878 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1);
3883 *total = mips_fp_mult_cost (mode);
3884 else if (mode == DImode && !TARGET_64BIT)
3885 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
3886 where the mulsidi3 always includes an MFHI and an MFLO. */
3888 ? mips_cost->int_mult_si * 3 + 6
3889 : COSTS_N_INSNS (ISA_HAS_MUL3 ? 7 : 9));
3891 *total = COSTS_N_INSNS (ISA_HAS_MUL3 ? 1 : 2);
3892 else if (mode == DImode)
3893 *total = mips_cost->int_mult_di;
3895 *total = mips_cost->int_mult_si;
3899 /* Check for a reciprocal. */
3902 && flag_unsafe_math_optimizations
3903 && XEXP (x, 0) == CONST1_RTX (mode))
3905 if (outer_code == SQRT || GET_CODE (XEXP (x, 1)) == SQRT)
3906 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
3907 division as being free. */
3908 *total = set_src_cost (XEXP (x, 1), speed);
3910 *total = (mips_fp_div_cost (mode)
3911 + set_src_cost (XEXP (x, 1), speed));
3920 *total = mips_fp_div_cost (mode);
3929 /* It is our responsibility to make division by a power of 2
3930 as cheap as 2 register additions if we want the division
3931 expanders to be used for such operations; see the setting
3932 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
3933 should always produce shorter code than using
3934 expand_sdiv2_pow2. */
3936 && CONST_INT_P (XEXP (x, 1))
3937 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
3939 *total = COSTS_N_INSNS (2) + set_src_cost (XEXP (x, 0), speed);
3942 *total = COSTS_N_INSNS (mips_idiv_insns ());
3944 else if (mode == DImode)
3945 *total = mips_cost->int_div_di;
3947 *total = mips_cost->int_div_si;
3951 *total = mips_sign_extend_cost (mode, XEXP (x, 0));
3955 if (outer_code == SET
3957 && GET_MODE (XEXP (x, 0)) == QImode
3958 && GET_CODE (XEXP (x, 0)) == PLUS)
3960 rtx plus = XEXP (x, 0);
3961 *total = (COSTS_N_INSNS (1)
3962 + mips_truncated_op_cost (XEXP (plus, 0), speed)
3963 + mips_truncated_op_cost (XEXP (plus, 1), speed));
3966 *total = mips_zero_extend_cost (mode, XEXP (x, 0));
3970 case UNSIGNED_FLOAT:
3973 case FLOAT_TRUNCATE:
3974 *total = mips_cost->fp_add;
3978 if (register_operand (SET_DEST (x), VOIDmode)
3979 && reg_or_0_operand (SET_SRC (x), VOIDmode))
3981 *total = mips_set_reg_reg_cost (GET_MODE (SET_DEST (x)));
3991 /* Implement TARGET_ADDRESS_COST. */
3994 mips_address_cost (rtx addr, enum machine_mode mode,
3995 addr_space_t as ATTRIBUTE_UNUSED,
3996 bool speed ATTRIBUTE_UNUSED)
3998 return mips_address_insns (addr, mode, false);
4001 /* Information about a single instruction in a multi-instruction
4003 struct mips_multi_member {
4004 /* True if this is a label, false if it is code. */
4007 /* The output_asm_insn format of the instruction. */
4010 /* The operands to the instruction. */
4011 rtx operands[MAX_RECOG_OPERANDS];
4013 typedef struct mips_multi_member mips_multi_member;
4015 /* The instructions that make up the current multi-insn sequence. */
4016 static vec<mips_multi_member> mips_multi_members;
4018 /* How many instructions (as opposed to labels) are in the current
4019 multi-insn sequence. */
4020 static unsigned int mips_multi_num_insns;
4022 /* Start a new multi-insn sequence. */
4025 mips_multi_start (void)
4027 mips_multi_members.truncate (0);
4028 mips_multi_num_insns = 0;
4031 /* Add a new, uninitialized member to the current multi-insn sequence. */
4033 static struct mips_multi_member *
4034 mips_multi_add (void)
4036 mips_multi_member empty;
4037 return mips_multi_members.safe_push (empty);
4040 /* Add a normal insn with the given asm format to the current multi-insn
4041 sequence. The other arguments are a null-terminated list of operands. */
4044 mips_multi_add_insn (const char *format, ...)
4046 struct mips_multi_member *member;
4051 member = mips_multi_add ();
4052 member->is_label_p = false;
4053 member->format = format;
4054 va_start (ap, format);
4056 while ((op = va_arg (ap, rtx)))
4057 member->operands[i++] = op;
4059 mips_multi_num_insns++;
4062 /* Add the given label definition to the current multi-insn sequence.
4063 The definition should include the colon. */
4066 mips_multi_add_label (const char *label)
4068 struct mips_multi_member *member;
4070 member = mips_multi_add ();
4071 member->is_label_p = true;
4072 member->format = label;
4075 /* Return the index of the last member of the current multi-insn sequence. */
4078 mips_multi_last_index (void)
4080 return mips_multi_members.length () - 1;
4083 /* Add a copy of an existing instruction to the current multi-insn
4084 sequence. I is the index of the instruction that should be copied. */
4087 mips_multi_copy_insn (unsigned int i)
4089 struct mips_multi_member *member;
4091 member = mips_multi_add ();
4092 memcpy (member, &mips_multi_members[i], sizeof (*member));
4093 gcc_assert (!member->is_label_p);
4096 /* Change the operand of an existing instruction in the current
4097 multi-insn sequence. I is the index of the instruction,
4098 OP is the index of the operand, and X is the new value. */
4101 mips_multi_set_operand (unsigned int i, unsigned int op, rtx x)
4103 mips_multi_members[i].operands[op] = x;
4106 /* Write out the asm code for the current multi-insn sequence. */
4109 mips_multi_write (void)
4111 struct mips_multi_member *member;
4114 FOR_EACH_VEC_ELT (mips_multi_members, i, member)
4115 if (member->is_label_p)
4116 fprintf (asm_out_file, "%s\n", member->format);
4118 output_asm_insn (member->format, member->operands);
4121 /* Return one word of double-word value OP, taking into account the fixed
4122 endianness of certain registers. HIGH_P is true to select the high part,
4123 false to select the low part. */
4126 mips_subword (rtx op, bool high_p)
4128 unsigned int byte, offset;
4129 enum machine_mode mode;
4131 mode = GET_MODE (op);
4132 if (mode == VOIDmode)
4133 mode = TARGET_64BIT ? TImode : DImode;
4135 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
4136 byte = UNITS_PER_WORD;
4140 if (FP_REG_RTX_P (op))
4142 /* Paired FPRs are always ordered little-endian. */
4143 offset = (UNITS_PER_WORD < UNITS_PER_HWFPVALUE ? high_p : byte != 0);
4144 return gen_rtx_REG (word_mode, REGNO (op) + offset);
4148 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
4150 return simplify_gen_subreg (word_mode, op, mode, byte);
4153 /* Return true if SRC should be moved into DEST using "MULT $0, $0".
4154 SPLIT_TYPE is the condition under which moves should be split. */
4157 mips_mult_move_p (rtx dest, rtx src, enum mips_split_type split_type)
4159 return ((split_type != SPLIT_FOR_SPEED
4160 || mips_tuning_info.fast_mult_zero_zero_p)
4161 && src == const0_rtx
4163 && GET_MODE_SIZE (GET_MODE (dest)) == 2 * UNITS_PER_WORD
4164 && (ISA_HAS_DSP_MULT
4165 ? ACC_REG_P (REGNO (dest))
4166 : MD_REG_P (REGNO (dest))));
4169 /* Return true if a move from SRC to DEST should be split into two.
4170 SPLIT_TYPE describes the split condition. */
4173 mips_split_move_p (rtx dest, rtx src, enum mips_split_type split_type)
4175 /* Check whether the move can be done using some variant of MULT $0,$0. */
4176 if (mips_mult_move_p (dest, src, split_type))
4179 /* FPR-to-FPR moves can be done in a single instruction, if they're
4181 unsigned int size = GET_MODE_SIZE (GET_MODE (dest));
4182 if (size == 8 && FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
4185 /* Check for floating-point loads and stores. */
4186 if (size == 8 && ISA_HAS_LDC1_SDC1)
4188 if (FP_REG_RTX_P (dest) && MEM_P (src))
4190 if (FP_REG_RTX_P (src) && MEM_P (dest))
4194 /* Otherwise split all multiword moves. */
4195 return size > UNITS_PER_WORD;
4198 /* Split a move from SRC to DEST, given that mips_split_move_p holds.
4199 SPLIT_TYPE describes the split condition. */
4202 mips_split_move (rtx dest, rtx src, enum mips_split_type split_type)
4206 gcc_checking_assert (mips_split_move_p (dest, src, split_type));
4207 if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src))
4209 if (!TARGET_64BIT && GET_MODE (dest) == DImode)
4210 emit_insn (gen_move_doubleword_fprdi (dest, src));
4211 else if (!TARGET_64BIT && GET_MODE (dest) == DFmode)
4212 emit_insn (gen_move_doubleword_fprdf (dest, src));
4213 else if (!TARGET_64BIT && GET_MODE (dest) == V2SFmode)
4214 emit_insn (gen_move_doubleword_fprv2sf (dest, src));
4215 else if (!TARGET_64BIT && GET_MODE (dest) == V2SImode)
4216 emit_insn (gen_move_doubleword_fprv2si (dest, src));
4217 else if (!TARGET_64BIT && GET_MODE (dest) == V4HImode)
4218 emit_insn (gen_move_doubleword_fprv4hi (dest, src));
4219 else if (!TARGET_64BIT && GET_MODE (dest) == V8QImode)
4220 emit_insn (gen_move_doubleword_fprv8qi (dest, src));
4221 else if (TARGET_64BIT && GET_MODE (dest) == TFmode)
4222 emit_insn (gen_move_doubleword_fprtf (dest, src));
4226 else if (REG_P (dest) && REGNO (dest) == MD_REG_FIRST)
4228 low_dest = mips_subword (dest, false);
4229 mips_emit_move (low_dest, mips_subword (src, false));
4231 emit_insn (gen_mthidi_ti (dest, mips_subword (src, true), low_dest));
4233 emit_insn (gen_mthisi_di (dest, mips_subword (src, true), low_dest));
4235 else if (REG_P (src) && REGNO (src) == MD_REG_FIRST)
4237 mips_emit_move (mips_subword (dest, false), mips_subword (src, false));
4239 emit_insn (gen_mfhidi_ti (mips_subword (dest, true), src));
4241 emit_insn (gen_mfhisi_di (mips_subword (dest, true), src));
4245 /* The operation can be split into two normal moves. Decide in
4246 which order to do them. */
4247 low_dest = mips_subword (dest, false);
4248 if (REG_P (low_dest)
4249 && reg_overlap_mentioned_p (low_dest, src))
4251 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4252 mips_emit_move (low_dest, mips_subword (src, false));
4256 mips_emit_move (low_dest, mips_subword (src, false));
4257 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4262 /* Return the split type for instruction INSN. */
4264 static enum mips_split_type
4265 mips_insn_split_type (rtx insn)
4267 basic_block bb = BLOCK_FOR_INSN (insn);
4270 if (optimize_bb_for_speed_p (bb))
4271 return SPLIT_FOR_SPEED;
4273 return SPLIT_FOR_SIZE;
4275 /* Once CFG information has been removed, we should trust the optimization
4276 decisions made by previous passes and only split where necessary. */
4277 return SPLIT_IF_NECESSARY;
4280 /* Return true if a move from SRC to DEST in INSN should be split. */
4283 mips_split_move_insn_p (rtx dest, rtx src, rtx insn)
4285 return mips_split_move_p (dest, src, mips_insn_split_type (insn));
4288 /* Split a move from SRC to DEST in INSN, given that mips_split_move_insn_p
4292 mips_split_move_insn (rtx dest, rtx src, rtx insn)
4294 mips_split_move (dest, src, mips_insn_split_type (insn));
4297 /* Return the appropriate instructions to move SRC into DEST. Assume
4298 that SRC is operand 1 and DEST is operand 0. */
4301 mips_output_move (rtx dest, rtx src)
4303 enum rtx_code dest_code, src_code;
4304 enum machine_mode mode;
4305 enum mips_symbol_type symbol_type;
4308 dest_code = GET_CODE (dest);
4309 src_code = GET_CODE (src);
4310 mode = GET_MODE (dest);
4311 dbl_p = (GET_MODE_SIZE (mode) == 8);
4313 if (mips_split_move_p (dest, src, SPLIT_IF_NECESSARY))
4316 if ((src_code == REG && GP_REG_P (REGNO (src)))
4317 || (!TARGET_MIPS16 && src == CONST0_RTX (mode)))
4319 if (dest_code == REG)
4321 if (GP_REG_P (REGNO (dest)))
4322 return "move\t%0,%z1";
4324 if (mips_mult_move_p (dest, src, SPLIT_IF_NECESSARY))
4326 if (ISA_HAS_DSP_MULT)
4327 return "mult\t%q0,%.,%.";
4329 return "mult\t%.,%.";
4332 /* Moves to HI are handled by special .md insns. */
4333 if (REGNO (dest) == LO_REGNUM)
4336 if (DSP_ACC_REG_P (REGNO (dest)))
4338 static char retval[] = "mt__\t%z1,%q0";
4340 retval[2] = reg_names[REGNO (dest)][4];
4341 retval[3] = reg_names[REGNO (dest)][5];
4345 if (FP_REG_P (REGNO (dest)))
4346 return dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
4348 if (ALL_COP_REG_P (REGNO (dest)))
4350 static char retval[] = "dmtc_\t%z1,%0";
4352 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4353 return dbl_p ? retval : retval + 1;
4356 if (dest_code == MEM)
4357 switch (GET_MODE_SIZE (mode))
4359 case 1: return "sb\t%z1,%0";
4360 case 2: return "sh\t%z1,%0";
4361 case 4: return "sw\t%z1,%0";
4362 case 8: return "sd\t%z1,%0";
4365 if (dest_code == REG && GP_REG_P (REGNO (dest)))
4367 if (src_code == REG)
4369 /* Moves from HI are handled by special .md insns. */
4370 if (REGNO (src) == LO_REGNUM)
4372 /* When generating VR4120 or VR4130 code, we use MACC and
4373 DMACC instead of MFLO. This avoids both the normal
4374 MIPS III HI/LO hazards and the errata related to
4377 return dbl_p ? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
4381 if (DSP_ACC_REG_P (REGNO (src)))
4383 static char retval[] = "mf__\t%0,%q1";
4385 retval[2] = reg_names[REGNO (src)][4];
4386 retval[3] = reg_names[REGNO (src)][5];
4390 if (FP_REG_P (REGNO (src)))
4391 return dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
4393 if (ALL_COP_REG_P (REGNO (src)))
4395 static char retval[] = "dmfc_\t%0,%1";
4397 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4398 return dbl_p ? retval : retval + 1;
4402 if (src_code == MEM)
4403 switch (GET_MODE_SIZE (mode))
4405 case 1: return "lbu\t%0,%1";
4406 case 2: return "lhu\t%0,%1";
4407 case 4: return "lw\t%0,%1";
4408 case 8: return "ld\t%0,%1";
4411 if (src_code == CONST_INT)
4413 /* Don't use the X format for the operand itself, because that
4414 will give out-of-range numbers for 64-bit hosts and 32-bit
4417 return "li\t%0,%1\t\t\t# %X1";
4419 if (SMALL_OPERAND_UNSIGNED (INTVAL (src)))
4422 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src)))
4426 if (src_code == HIGH)
4427 return TARGET_MIPS16 ? "#" : "lui\t%0,%h1";
4429 if (CONST_GP_P (src))
4430 return "move\t%0,%1";
4432 if (mips_symbolic_constant_p (src, SYMBOL_CONTEXT_LEA, &symbol_type)
4433 && mips_lo_relocs[symbol_type] != 0)
4435 /* A signed 16-bit constant formed by applying a relocation
4436 operator to a symbolic address. */
4437 gcc_assert (!mips_split_p[symbol_type]);
4438 return "li\t%0,%R1";
4441 if (symbolic_operand (src, VOIDmode))
4443 gcc_assert (TARGET_MIPS16
4444 ? TARGET_MIPS16_TEXT_LOADS
4445 : !TARGET_EXPLICIT_RELOCS);
4446 return dbl_p ? "dla\t%0,%1" : "la\t%0,%1";
4449 if (src_code == REG && FP_REG_P (REGNO (src)))
4451 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4453 if (GET_MODE (dest) == V2SFmode)
4454 return "mov.ps\t%0,%1";
4456 return dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1";
4459 if (dest_code == MEM)
4460 return dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0";
4462 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4464 if (src_code == MEM)
4465 return dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1";
4467 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
4469 static char retval[] = "l_c_\t%0,%1";
4471 retval[1] = (dbl_p ? 'd' : 'w');
4472 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4475 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
4477 static char retval[] = "s_c_\t%1,%0";
4479 retval[1] = (dbl_p ? 'd' : 'w');
4480 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4486 /* Return true if CMP1 is a suitable second operand for integer ordering
4487 test CODE. See also the *sCC patterns in mips.md. */
4490 mips_int_order_operand_ok_p (enum rtx_code code, rtx cmp1)
4496 return reg_or_0_operand (cmp1, VOIDmode);
4500 return !TARGET_MIPS16 && cmp1 == const1_rtx;
4504 return arith_operand (cmp1, VOIDmode);
4507 return sle_operand (cmp1, VOIDmode);
4510 return sleu_operand (cmp1, VOIDmode);
4517 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4518 integer ordering test *CODE, or if an equivalent combination can
4519 be formed by adjusting *CODE and *CMP1. When returning true, update
4520 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4524 mips_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1,
4525 enum machine_mode mode)
4527 HOST_WIDE_INT plus_one;
4529 if (mips_int_order_operand_ok_p (*code, *cmp1))
4532 if (CONST_INT_P (*cmp1))
4536 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4537 if (INTVAL (*cmp1) < plus_one)
4540 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4546 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4550 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4561 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4562 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4563 is nonnull, it's OK to set TARGET to the inverse of the result and
4564 flip *INVERT_PTR instead. */
4567 mips_emit_int_order_test (enum rtx_code code, bool *invert_ptr,
4568 rtx target, rtx cmp0, rtx cmp1)
4570 enum machine_mode mode;
4572 /* First see if there is a MIPS instruction that can do this operation.
4573 If not, try doing the same for the inverse operation. If that also
4574 fails, force CMP1 into a register and try again. */
4575 mode = GET_MODE (cmp0);
4576 if (mips_canonicalize_int_order_test (&code, &cmp1, mode))
4577 mips_emit_binary (code, target, cmp0, cmp1);
4580 enum rtx_code inv_code = reverse_condition (code);
4581 if (!mips_canonicalize_int_order_test (&inv_code, &cmp1, mode))
4583 cmp1 = force_reg (mode, cmp1);
4584 mips_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1);
4586 else if (invert_ptr == 0)
4590 inv_target = mips_force_binary (GET_MODE (target),
4591 inv_code, cmp0, cmp1);
4592 mips_emit_binary (XOR, target, inv_target, const1_rtx);
4596 *invert_ptr = !*invert_ptr;
4597 mips_emit_binary (inv_code, target, cmp0, cmp1);
4602 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4603 The register will have the same mode as CMP0. */
4606 mips_zero_if_equal (rtx cmp0, rtx cmp1)
4608 if (cmp1 == const0_rtx)
4611 if (uns_arith_operand (cmp1, VOIDmode))
4612 return expand_binop (GET_MODE (cmp0), xor_optab,
4613 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4615 return expand_binop (GET_MODE (cmp0), sub_optab,
4616 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4619 /* Convert *CODE into a code that can be used in a floating-point
4620 scc instruction (C.cond.fmt). Return true if the values of
4621 the condition code registers will be inverted, with 0 indicating
4622 that the condition holds. */
4625 mips_reversed_fp_cond (enum rtx_code *code)
4632 *code = reverse_condition_maybe_unordered (*code);
4640 /* Allocate a floating-point condition-code register of mode MODE.
4642 These condition code registers are used for certain kinds
4643 of compound operation, such as compare and branches, vconds,
4644 and built-in functions. At expand time, their use is entirely
4645 controlled by MIPS-specific code and is entirely internal
4646 to these compound operations.
4648 We could (and did in the past) expose condition-code values
4649 as pseudo registers and leave the register allocator to pick
4650 appropriate registers. The problem is that it is not practically
4651 possible for the rtl optimizers to guarantee that no spills will
4652 be needed, even when AVOID_CCMODE_COPIES is defined. We would
4653 therefore need spill and reload sequences to handle the worst case.
4655 Although such sequences do exist, they are very expensive and are
4656 not something we'd want to use. This is especially true of CCV2 and
4657 CCV4, where all the shuffling would greatly outweigh whatever benefit
4658 the vectorization itself provides.
4660 The main benefit of having more than one condition-code register
4661 is to allow the pipelining of operations, especially those involving
4662 comparisons and conditional moves. We don't really expect the
4663 registers to be live for long periods, and certainly never want
4664 them to be live across calls.
4666 Also, there should be no penalty attached to using all the available
4667 registers. They are simply bits in the same underlying FPU control
4670 We therefore expose the hardware registers from the outset and use
4671 a simple round-robin allocation scheme. */
4674 mips_allocate_fcc (enum machine_mode mode)
4676 unsigned int regno, count;
4678 gcc_assert (TARGET_HARD_FLOAT && ISA_HAS_8CC);
4682 else if (mode == CCV2mode)
4684 else if (mode == CCV4mode)
4689 cfun->machine->next_fcc += -cfun->machine->next_fcc & (count - 1);
4690 if (cfun->machine->next_fcc > ST_REG_LAST - ST_REG_FIRST)
4691 cfun->machine->next_fcc = 0;
4692 regno = ST_REG_FIRST + cfun->machine->next_fcc;
4693 cfun->machine->next_fcc += count;
4694 return gen_rtx_REG (mode, regno);
4697 /* Convert a comparison into something that can be used in a branch or
4698 conditional move. On entry, *OP0 and *OP1 are the values being
4699 compared and *CODE is the code used to compare them.
4701 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
4702 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
4703 otherwise any standard branch condition can be used. The standard branch
4706 - EQ or NE between two registers.
4707 - any comparison between a register and zero. */
4710 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
4715 if (GET_MODE_CLASS (GET_MODE (*op0)) == MODE_INT)
4717 if (!need_eq_ne_p && *op1 == const0_rtx)
4719 else if (*code == EQ || *code == NE)
4723 *op0 = mips_zero_if_equal (cmp_op0, cmp_op1);
4727 *op1 = force_reg (GET_MODE (cmp_op0), cmp_op1);
4731 /* The comparison needs a separate scc instruction. Store the
4732 result of the scc in *OP0 and compare it against zero. */
4733 bool invert = false;
4734 *op0 = gen_reg_rtx (GET_MODE (cmp_op0));
4735 mips_emit_int_order_test (*code, &invert, *op0, cmp_op0, cmp_op1);
4736 *code = (invert ? EQ : NE);
4740 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0)))
4742 *op0 = gen_rtx_REG (CCDSPmode, CCDSP_CC_REGNUM);
4743 mips_emit_binary (*code, *op0, cmp_op0, cmp_op1);
4749 enum rtx_code cmp_code;
4751 /* Floating-point tests use a separate C.cond.fmt comparison to
4752 set a condition code register. The branch or conditional move
4753 will then compare that register against zero.
4755 Set CMP_CODE to the code of the comparison instruction and
4756 *CODE to the code that the branch or move should use. */
4758 *code = mips_reversed_fp_cond (&cmp_code) ? EQ : NE;
4760 ? mips_allocate_fcc (CCmode)
4761 : gen_rtx_REG (CCmode, FPSW_REGNUM));
4763 mips_emit_binary (cmp_code, *op0, cmp_op0, cmp_op1);
4767 /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2]
4768 and OPERAND[3]. Store the result in OPERANDS[0].
4770 On 64-bit targets, the mode of the comparison and target will always be
4771 SImode, thus possibly narrower than that of the comparison's operands. */
4774 mips_expand_scc (rtx operands[])
4776 rtx target = operands[0];
4777 enum rtx_code code = GET_CODE (operands[1]);
4778 rtx op0 = operands[2];
4779 rtx op1 = operands[3];
4781 gcc_assert (GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT);
4783 if (code == EQ || code == NE)
4786 && reg_imm10_operand (op1, GET_MODE (op1)))
4787 mips_emit_binary (code, target, op0, op1);
4790 rtx zie = mips_zero_if_equal (op0, op1);
4791 mips_emit_binary (code, target, zie, const0_rtx);
4795 mips_emit_int_order_test (code, 0, target, op0, op1);
4798 /* Compare OPERANDS[1] with OPERANDS[2] using comparison code
4799 CODE and jump to OPERANDS[3] if the condition holds. */
4802 mips_expand_conditional_branch (rtx *operands)
4804 enum rtx_code code = GET_CODE (operands[0]);
4805 rtx op0 = operands[1];
4806 rtx op1 = operands[2];
4809 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
4810 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
4811 emit_jump_insn (gen_condjump (condition, operands[3]));
4816 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
4817 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
4820 mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
4821 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
4826 reversed_p = mips_reversed_fp_cond (&cond);
4827 cmp_result = mips_allocate_fcc (CCV2mode);
4828 emit_insn (gen_scc_ps (cmp_result,
4829 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
4831 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
4834 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
4838 /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0]
4839 if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
4842 mips_expand_conditional_move (rtx *operands)
4845 enum rtx_code code = GET_CODE (operands[1]);
4846 rtx op0 = XEXP (operands[1], 0);
4847 rtx op1 = XEXP (operands[1], 1);
4849 mips_emit_compare (&code, &op0, &op1, true);
4850 cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
4851 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
4852 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), cond,
4853 operands[2], operands[3])));
4856 /* Perform the comparison in COMPARISON, then trap if the condition holds. */
4859 mips_expand_conditional_trap (rtx comparison)
4862 enum machine_mode mode;
4865 /* MIPS conditional trap instructions don't have GT or LE flavors,
4866 so we must swap the operands and convert to LT and GE respectively. */
4867 code = GET_CODE (comparison);
4874 code = swap_condition (code);
4875 op0 = XEXP (comparison, 1);
4876 op1 = XEXP (comparison, 0);
4880 op0 = XEXP (comparison, 0);
4881 op1 = XEXP (comparison, 1);
4885 mode = GET_MODE (XEXP (comparison, 0));
4886 op0 = force_reg (mode, op0);
4887 if (!arith_operand (op1, mode))
4888 op1 = force_reg (mode, op1);
4890 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
4891 gen_rtx_fmt_ee (code, mode, op0, op1),
4895 /* Initialize *CUM for a call to a function of type FNTYPE. */
4898 mips_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype)
4900 memset (cum, 0, sizeof (*cum));
4901 cum->prototype = (fntype && prototype_p (fntype));
4902 cum->gp_reg_found = (cum->prototype && stdarg_p (fntype));
4905 /* Fill INFO with information about a single argument. CUM is the
4906 cumulative state for earlier arguments. MODE is the mode of this
4907 argument and TYPE is its type (if known). NAMED is true if this
4908 is a named (fixed) argument rather than a variable one. */
4911 mips_get_arg_info (struct mips_arg_info *info, const CUMULATIVE_ARGS *cum,
4912 enum machine_mode mode, const_tree type, bool named)
4914 bool doubleword_aligned_p;
4915 unsigned int num_bytes, num_words, max_regs;
4917 /* Work out the size of the argument. */
4918 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
4919 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4921 /* Decide whether it should go in a floating-point register, assuming
4922 one is free. Later code checks for availability.
4924 The checks against UNITS_PER_FPVALUE handle the soft-float and
4925 single-float cases. */
4929 /* The EABI conventions have traditionally been defined in terms
4930 of TYPE_MODE, regardless of the actual type. */
4931 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
4932 || mode == V2SFmode)
4933 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4938 /* Only leading floating-point scalars are passed in
4939 floating-point registers. We also handle vector floats the same
4940 say, which is OK because they are not covered by the standard ABI. */
4941 info->fpr_p = (!cum->gp_reg_found
4942 && cum->arg_number < 2
4944 || SCALAR_FLOAT_TYPE_P (type)
4945 || VECTOR_FLOAT_TYPE_P (type))
4946 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4947 || mode == V2SFmode)
4948 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4953 /* Scalar, complex and vector floating-point types are passed in
4954 floating-point registers, as long as this is a named rather
4955 than a variable argument. */
4956 info->fpr_p = (named
4957 && (type == 0 || FLOAT_TYPE_P (type))
4958 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4959 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4960 || mode == V2SFmode)
4961 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
4963 /* ??? According to the ABI documentation, the real and imaginary
4964 parts of complex floats should be passed in individual registers.
4965 The real and imaginary parts of stack arguments are supposed
4966 to be contiguous and there should be an extra word of padding
4969 This has two problems. First, it makes it impossible to use a
4970 single "void *" va_list type, since register and stack arguments
4971 are passed differently. (At the time of writing, MIPSpro cannot
4972 handle complex float varargs correctly.) Second, it's unclear
4973 what should happen when there is only one register free.
4975 For now, we assume that named complex floats should go into FPRs
4976 if there are two FPRs free, otherwise they should be passed in the
4977 same way as a struct containing two floats. */
4979 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4980 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
4982 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
4983 info->fpr_p = false;
4993 /* See whether the argument has doubleword alignment. */
4994 doubleword_aligned_p = (mips_function_arg_boundary (mode, type)
4997 /* Set REG_OFFSET to the register count we're interested in.
4998 The EABI allocates the floating-point registers separately,
4999 but the other ABIs allocate them like integer registers. */
5000 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
5004 /* Advance to an even register if the argument is doubleword-aligned. */
5005 if (doubleword_aligned_p)
5006 info->reg_offset += info->reg_offset & 1;
5008 /* Work out the offset of a stack argument. */
5009 info->stack_offset = cum->stack_words;
5010 if (doubleword_aligned_p)
5011 info->stack_offset += info->stack_offset & 1;
5013 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
5015 /* Partition the argument between registers and stack. */
5016 info->reg_words = MIN (num_words, max_regs);
5017 info->stack_words = num_words - info->reg_words;
5020 /* INFO describes a register argument that has the normal format for the
5021 argument's mode. Return the register it uses, assuming that FPRs are
5022 available if HARD_FLOAT_P. */
5025 mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p)
5027 if (!info->fpr_p || !hard_float_p)
5028 return GP_ARG_FIRST + info->reg_offset;
5029 else if (mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info->reg_offset > 0)
5030 /* In o32, the second argument is always passed in $f14
5031 for TARGET_DOUBLE_FLOAT, regardless of whether the
5032 first argument was a word or doubleword. */
5033 return FP_ARG_FIRST + 2;
5035 return FP_ARG_FIRST + info->reg_offset;
5038 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
5041 mips_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED)
5043 return !TARGET_OLDABI;
5046 /* Implement TARGET_FUNCTION_ARG. */
5049 mips_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
5050 const_tree type, bool named)
5052 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
5053 struct mips_arg_info info;
5055 /* We will be called with a mode of VOIDmode after the last argument
5056 has been seen. Whatever we return will be passed to the call expander.
5057 If we need a MIPS16 fp_code, return a REG with the code stored as
5059 if (mode == VOIDmode)
5061 if (TARGET_MIPS16 && cum->fp_code != 0)
5062 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
5067 mips_get_arg_info (&info, cum, mode, type, named);
5069 /* Return straight away if the whole argument is passed on the stack. */
5070 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
5073 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
5074 contains a double in its entirety, then that 64-bit chunk is passed
5075 in a floating-point register. */
5077 && TARGET_HARD_FLOAT
5080 && TREE_CODE (type) == RECORD_TYPE
5081 && TYPE_SIZE_UNIT (type)
5082 && host_integerp (TYPE_SIZE_UNIT (type), 1))
5086 /* First check to see if there is any such field. */
5087 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
5088 if (TREE_CODE (field) == FIELD_DECL
5089 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
5090 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
5091 && host_integerp (bit_position (field), 0)
5092 && int_bit_position (field) % BITS_PER_WORD == 0)
5097 /* Now handle the special case by returning a PARALLEL
5098 indicating where each 64-bit chunk goes. INFO.REG_WORDS
5099 chunks are passed in registers. */
5101 HOST_WIDE_INT bitpos;
5104 /* assign_parms checks the mode of ENTRY_PARM, so we must
5105 use the actual mode here. */
5106 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
5109 field = TYPE_FIELDS (type);
5110 for (i = 0; i < info.reg_words; i++)
5114 for (; field; field = DECL_CHAIN (field))
5115 if (TREE_CODE (field) == FIELD_DECL
5116 && int_bit_position (field) >= bitpos)
5120 && int_bit_position (field) == bitpos
5121 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
5122 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
5123 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
5125 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
5128 = gen_rtx_EXPR_LIST (VOIDmode, reg,
5129 GEN_INT (bitpos / BITS_PER_UNIT));
5131 bitpos += BITS_PER_WORD;
5137 /* Handle the n32/n64 conventions for passing complex floating-point
5138 arguments in FPR pairs. The real part goes in the lower register
5139 and the imaginary part goes in the upper register. */
5142 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5145 enum machine_mode inner;
5148 inner = GET_MODE_INNER (mode);
5149 regno = FP_ARG_FIRST + info.reg_offset;
5150 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
5152 /* Real part in registers, imaginary part on stack. */
5153 gcc_assert (info.stack_words == info.reg_words);
5154 return gen_rtx_REG (inner, regno);
5158 gcc_assert (info.stack_words == 0);
5159 real = gen_rtx_EXPR_LIST (VOIDmode,
5160 gen_rtx_REG (inner, regno),
5162 imag = gen_rtx_EXPR_LIST (VOIDmode,
5164 regno + info.reg_words / 2),
5165 GEN_INT (GET_MODE_SIZE (inner)));
5166 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
5170 return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT));
5173 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
5176 mips_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
5177 const_tree type, bool named)
5179 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
5180 struct mips_arg_info info;
5182 mips_get_arg_info (&info, cum, mode, type, named);
5185 cum->gp_reg_found = true;
5187 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
5188 an explanation of what this code does. It assumes that we're using
5189 either the o32 or the o64 ABI, both of which pass at most 2 arguments
5191 if (cum->arg_number < 2 && info.fpr_p)
5192 cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2);
5194 /* Advance the register count. This has the effect of setting
5195 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
5196 argument required us to skip the final GPR and pass the whole
5197 argument on the stack. */
5198 if (mips_abi != ABI_EABI || !info.fpr_p)
5199 cum->num_gprs = info.reg_offset + info.reg_words;
5200 else if (info.reg_words > 0)
5201 cum->num_fprs += MAX_FPRS_PER_FMT;
5203 /* Advance the stack word count. */
5204 if (info.stack_words > 0)
5205 cum->stack_words = info.stack_offset + info.stack_words;
5210 /* Implement TARGET_ARG_PARTIAL_BYTES. */
5213 mips_arg_partial_bytes (cumulative_args_t cum,
5214 enum machine_mode mode, tree type, bool named)
5216 struct mips_arg_info info;
5218 mips_get_arg_info (&info, get_cumulative_args (cum), mode, type, named);
5219 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
5222 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
5223 least PARM_BOUNDARY bits of alignment, but will be given anything up
5224 to STACK_BOUNDARY bits if the type requires it. */
5227 mips_function_arg_boundary (enum machine_mode mode, const_tree type)
5229 unsigned int alignment;
5231 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
5232 if (alignment < PARM_BOUNDARY)
5233 alignment = PARM_BOUNDARY;
5234 if (alignment > STACK_BOUNDARY)
5235 alignment = STACK_BOUNDARY;
5239 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
5240 upward rather than downward. In other words, return true if the
5241 first byte of the stack slot has useful data, false if the last
5245 mips_pad_arg_upward (enum machine_mode mode, const_tree type)
5247 /* On little-endian targets, the first byte of every stack argument
5248 is passed in the first byte of the stack slot. */
5249 if (!BYTES_BIG_ENDIAN)
5252 /* Otherwise, integral types are padded downward: the last byte of a
5253 stack argument is passed in the last byte of the stack slot. */
5255 ? (INTEGRAL_TYPE_P (type)
5256 || POINTER_TYPE_P (type)
5257 || FIXED_POINT_TYPE_P (type))
5258 : (SCALAR_INT_MODE_P (mode)
5259 || ALL_SCALAR_FIXED_POINT_MODE_P (mode)))
5262 /* Big-endian o64 pads floating-point arguments downward. */
5263 if (mips_abi == ABI_O64)
5264 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
5267 /* Other types are padded upward for o32, o64, n32 and n64. */
5268 if (mips_abi != ABI_EABI)
5271 /* Arguments smaller than a stack slot are padded downward. */
5272 if (mode != BLKmode)
5273 return GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY;
5275 return int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT);
5278 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
5279 if the least significant byte of the register has useful data. Return
5280 the opposite if the most significant byte does. */
5283 mips_pad_reg_upward (enum machine_mode mode, tree type)
5285 /* No shifting is required for floating-point arguments. */
5286 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
5287 return !BYTES_BIG_ENDIAN;
5289 /* Otherwise, apply the same padding to register arguments as we do
5290 to stack arguments. */
5291 return mips_pad_arg_upward (mode, type);
5294 /* Return nonzero when an argument must be passed by reference. */
5297 mips_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
5298 enum machine_mode mode, const_tree type,
5299 bool named ATTRIBUTE_UNUSED)
5301 if (mips_abi == ABI_EABI)
5305 /* ??? How should SCmode be handled? */
5306 if (mode == DImode || mode == DFmode
5307 || mode == DQmode || mode == UDQmode
5308 || mode == DAmode || mode == UDAmode)
5311 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
5312 return size == -1 || size > UNITS_PER_WORD;
5316 /* If we have a variable-sized parameter, we have no choice. */
5317 return targetm.calls.must_pass_in_stack (mode, type);
5321 /* Implement TARGET_CALLEE_COPIES. */
5324 mips_callee_copies (cumulative_args_t cum ATTRIBUTE_UNUSED,
5325 enum machine_mode mode ATTRIBUTE_UNUSED,
5326 const_tree type ATTRIBUTE_UNUSED, bool named)
5328 return mips_abi == ABI_EABI && named;
5331 /* See whether VALTYPE is a record whose fields should be returned in
5332 floating-point registers. If so, return the number of fields and
5333 list them in FIELDS (which should have two elements). Return 0
5336 For n32 & n64, a structure with one or two fields is returned in
5337 floating-point registers as long as every field has a floating-point
5341 mips_fpr_return_fields (const_tree valtype, tree *fields)
5349 if (TREE_CODE (valtype) != RECORD_TYPE)
5353 for (field = TYPE_FIELDS (valtype); field != 0; field = DECL_CHAIN (field))
5355 if (TREE_CODE (field) != FIELD_DECL)
5358 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)))
5364 fields[i++] = field;
5369 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
5370 a value in the most significant part of $2/$3 if:
5372 - the target is big-endian;
5374 - the value has a structure or union type (we generalize this to
5375 cover aggregates from other languages too); and
5377 - the structure is not returned in floating-point registers. */
5380 mips_return_in_msb (const_tree valtype)
5384 return (TARGET_NEWABI
5385 && TARGET_BIG_ENDIAN
5386 && AGGREGATE_TYPE_P (valtype)
5387 && mips_fpr_return_fields (valtype, fields) == 0);
5390 /* Return true if the function return value MODE will get returned in a
5391 floating-point register. */
5394 mips_return_mode_in_fpr_p (enum machine_mode mode)
5396 return ((GET_MODE_CLASS (mode) == MODE_FLOAT
5398 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5399 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE);
5402 /* Return the representation of an FPR return register when the
5403 value being returned in FP_RETURN has mode VALUE_MODE and the
5404 return type itself has mode TYPE_MODE. On NewABI targets,
5405 the two modes may be different for structures like:
5407 struct __attribute__((packed)) foo { float f; }
5409 where we return the SFmode value of "f" in FP_RETURN, but where
5410 the structure itself has mode BLKmode. */
5413 mips_return_fpr_single (enum machine_mode type_mode,
5414 enum machine_mode value_mode)
5418 x = gen_rtx_REG (value_mode, FP_RETURN);
5419 if (type_mode != value_mode)
5421 x = gen_rtx_EXPR_LIST (VOIDmode, x, const0_rtx);
5422 x = gen_rtx_PARALLEL (type_mode, gen_rtvec (1, x));
5427 /* Return a composite value in a pair of floating-point registers.
5428 MODE1 and OFFSET1 are the mode and byte offset for the first value,
5429 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
5432 For n32 & n64, $f0 always holds the first value and $f2 the second.
5433 Otherwise the values are packed together as closely as possible. */
5436 mips_return_fpr_pair (enum machine_mode mode,
5437 enum machine_mode mode1, HOST_WIDE_INT offset1,
5438 enum machine_mode mode2, HOST_WIDE_INT offset2)
5442 inc = (TARGET_NEWABI ? 2 : MAX_FPRS_PER_FMT);
5443 return gen_rtx_PARALLEL
5446 gen_rtx_EXPR_LIST (VOIDmode,
5447 gen_rtx_REG (mode1, FP_RETURN),
5449 gen_rtx_EXPR_LIST (VOIDmode,
5450 gen_rtx_REG (mode2, FP_RETURN + inc),
5451 GEN_INT (offset2))));
5455 /* Implement TARGET_FUNCTION_VALUE and TARGET_LIBCALL_VALUE.
5456 For normal calls, VALTYPE is the return type and MODE is VOIDmode.
5457 For libcalls, VALTYPE is null and MODE is the mode of the return value. */
5460 mips_function_value_1 (const_tree valtype, const_tree fn_decl_or_type,
5461 enum machine_mode mode)
5469 if (fn_decl_or_type && DECL_P (fn_decl_or_type))
5470 func = fn_decl_or_type;
5474 mode = TYPE_MODE (valtype);
5475 unsigned_p = TYPE_UNSIGNED (valtype);
5477 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
5478 return values, promote the mode here too. */
5479 mode = promote_function_mode (valtype, mode, &unsigned_p, func, 1);
5481 /* Handle structures whose fields are returned in $f0/$f2. */
5482 switch (mips_fpr_return_fields (valtype, fields))
5485 return mips_return_fpr_single (mode,
5486 TYPE_MODE (TREE_TYPE (fields[0])));
5489 return mips_return_fpr_pair (mode,
5490 TYPE_MODE (TREE_TYPE (fields[0])),
5491 int_byte_position (fields[0]),
5492 TYPE_MODE (TREE_TYPE (fields[1])),
5493 int_byte_position (fields[1]));
5496 /* If a value is passed in the most significant part of a register, see
5497 whether we have to round the mode up to a whole number of words. */
5498 if (mips_return_in_msb (valtype))
5500 HOST_WIDE_INT size = int_size_in_bytes (valtype);
5501 if (size % UNITS_PER_WORD != 0)
5503 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
5504 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
5508 /* For EABI, the class of return register depends entirely on MODE.
5509 For example, "struct { some_type x; }" and "union { some_type x; }"
5510 are returned in the same way as a bare "some_type" would be.
5511 Other ABIs only use FPRs for scalar, complex or vector types. */
5512 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
5513 return gen_rtx_REG (mode, GP_RETURN);
5518 /* Handle long doubles for n32 & n64. */
5520 return mips_return_fpr_pair (mode,
5522 DImode, GET_MODE_SIZE (mode) / 2);
5524 if (mips_return_mode_in_fpr_p (mode))
5526 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5527 return mips_return_fpr_pair (mode,
5528 GET_MODE_INNER (mode), 0,
5529 GET_MODE_INNER (mode),
5530 GET_MODE_SIZE (mode) / 2);
5532 return gen_rtx_REG (mode, FP_RETURN);
5536 return gen_rtx_REG (mode, GP_RETURN);
5539 /* Implement TARGET_FUNCTION_VALUE. */
5542 mips_function_value (const_tree valtype, const_tree fn_decl_or_type,
5543 bool outgoing ATTRIBUTE_UNUSED)
5545 return mips_function_value_1 (valtype, fn_decl_or_type, VOIDmode);
5548 /* Implement TARGET_LIBCALL_VALUE. */
5551 mips_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
5553 return mips_function_value_1 (NULL_TREE, NULL_TREE, mode);
5556 /* Implement TARGET_FUNCTION_VALUE_REGNO_P.
5558 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
5559 Currently, R2 and F0 are only implemented here (C has no complex type). */
5562 mips_function_value_regno_p (const unsigned int regno)
5564 if (regno == GP_RETURN
5565 || regno == FP_RETURN
5566 || (LONG_DOUBLE_TYPE_SIZE == 128
5567 && FP_RETURN != GP_RETURN
5568 && regno == FP_RETURN + 2))
5574 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
5575 all BLKmode objects are returned in memory. Under the n32, n64
5576 and embedded ABIs, small structures are returned in a register.
5577 Objects with varying size must still be returned in memory, of
5581 mips_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
5583 return (TARGET_OLDABI
5584 ? TYPE_MODE (type) == BLKmode
5585 : !IN_RANGE (int_size_in_bytes (type), 0, 2 * UNITS_PER_WORD));
5588 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
5591 mips_setup_incoming_varargs (cumulative_args_t cum, enum machine_mode mode,
5592 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5595 CUMULATIVE_ARGS local_cum;
5596 int gp_saved, fp_saved;
5598 /* The caller has advanced CUM up to, but not beyond, the last named
5599 argument. Advance a local copy of CUM past the last "real" named
5600 argument, to find out how many registers are left over. */
5601 local_cum = *get_cumulative_args (cum);
5602 mips_function_arg_advance (pack_cumulative_args (&local_cum), mode, type,
5605 /* Found out how many registers we need to save. */
5606 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
5607 fp_saved = (EABI_FLOAT_VARARGS_P
5608 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
5617 ptr = plus_constant (Pmode, virtual_incoming_args_rtx,
5618 REG_PARM_STACK_SPACE (cfun->decl)
5619 - gp_saved * UNITS_PER_WORD);
5620 mem = gen_frame_mem (BLKmode, ptr);
5621 set_mem_alias_set (mem, get_varargs_alias_set ());
5623 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
5628 /* We can't use move_block_from_reg, because it will use
5630 enum machine_mode mode;
5633 /* Set OFF to the offset from virtual_incoming_args_rtx of
5634 the first float register. The FP save area lies below
5635 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
5636 off = (-gp_saved * UNITS_PER_WORD) & -UNITS_PER_FPVALUE;
5637 off -= fp_saved * UNITS_PER_FPREG;
5639 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
5641 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS;
5642 i += MAX_FPRS_PER_FMT)
5646 ptr = plus_constant (Pmode, virtual_incoming_args_rtx, off);
5647 mem = gen_frame_mem (mode, ptr);
5648 set_mem_alias_set (mem, get_varargs_alias_set ());
5649 mips_emit_move (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
5650 off += UNITS_PER_HWFPVALUE;
5654 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
5655 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
5656 + fp_saved * UNITS_PER_FPREG);
5659 /* Implement TARGET_BUILTIN_VA_LIST. */
5662 mips_build_builtin_va_list (void)
5664 if (EABI_FLOAT_VARARGS_P)
5666 /* We keep 3 pointers, and two offsets.
5668 Two pointers are to the overflow area, which starts at the CFA.
5669 One of these is constant, for addressing into the GPR save area
5670 below it. The other is advanced up the stack through the
5673 The third pointer is to the bottom of the GPR save area.
5674 Since the FPR save area is just below it, we can address
5675 FPR slots off this pointer.
5677 We also keep two one-byte offsets, which are to be subtracted
5678 from the constant pointers to yield addresses in the GPR and
5679 FPR save areas. These are downcounted as float or non-float
5680 arguments are used, and when they get to zero, the argument
5681 must be obtained from the overflow region. */
5682 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
5685 record = lang_hooks.types.make_type (RECORD_TYPE);
5687 f_ovfl = build_decl (BUILTINS_LOCATION,
5688 FIELD_DECL, get_identifier ("__overflow_argptr"),
5690 f_gtop = build_decl (BUILTINS_LOCATION,
5691 FIELD_DECL, get_identifier ("__gpr_top"),
5693 f_ftop = build_decl (BUILTINS_LOCATION,
5694 FIELD_DECL, get_identifier ("__fpr_top"),
5696 f_goff = build_decl (BUILTINS_LOCATION,
5697 FIELD_DECL, get_identifier ("__gpr_offset"),
5698 unsigned_char_type_node);
5699 f_foff = build_decl (BUILTINS_LOCATION,
5700 FIELD_DECL, get_identifier ("__fpr_offset"),
5701 unsigned_char_type_node);
5702 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
5703 warn on every user file. */
5704 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
5705 array = build_array_type (unsigned_char_type_node,
5706 build_index_type (index));
5707 f_res = build_decl (BUILTINS_LOCATION,
5708 FIELD_DECL, get_identifier ("__reserved"), array);
5710 DECL_FIELD_CONTEXT (f_ovfl) = record;
5711 DECL_FIELD_CONTEXT (f_gtop) = record;
5712 DECL_FIELD_CONTEXT (f_ftop) = record;
5713 DECL_FIELD_CONTEXT (f_goff) = record;
5714 DECL_FIELD_CONTEXT (f_foff) = record;
5715 DECL_FIELD_CONTEXT (f_res) = record;
5717 TYPE_FIELDS (record) = f_ovfl;
5718 DECL_CHAIN (f_ovfl) = f_gtop;
5719 DECL_CHAIN (f_gtop) = f_ftop;
5720 DECL_CHAIN (f_ftop) = f_goff;
5721 DECL_CHAIN (f_goff) = f_foff;
5722 DECL_CHAIN (f_foff) = f_res;
5724 layout_type (record);
5728 /* Otherwise, we use 'void *'. */
5729 return ptr_type_node;
5732 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
5735 mips_va_start (tree valist, rtx nextarg)
5737 if (EABI_FLOAT_VARARGS_P)
5739 const CUMULATIVE_ARGS *cum;
5740 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5741 tree ovfl, gtop, ftop, goff, foff;
5743 int gpr_save_area_size;
5744 int fpr_save_area_size;
5747 cum = &crtl->args.info;
5749 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
5751 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
5753 f_ovfl = TYPE_FIELDS (va_list_type_node);
5754 f_gtop = DECL_CHAIN (f_ovfl);
5755 f_ftop = DECL_CHAIN (f_gtop);
5756 f_goff = DECL_CHAIN (f_ftop);
5757 f_foff = DECL_CHAIN (f_goff);
5759 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5761 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
5763 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
5765 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
5767 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
5770 /* Emit code to initialize OVFL, which points to the next varargs
5771 stack argument. CUM->STACK_WORDS gives the number of stack
5772 words used by named arguments. */
5773 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
5774 if (cum->stack_words > 0)
5775 t = fold_build_pointer_plus_hwi (t, cum->stack_words * UNITS_PER_WORD);
5776 t = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
5777 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5779 /* Emit code to initialize GTOP, the top of the GPR save area. */
5780 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
5781 t = build2 (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
5782 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5784 /* Emit code to initialize FTOP, the top of the FPR save area.
5785 This address is gpr_save_area_bytes below GTOP, rounded
5786 down to the next fp-aligned boundary. */
5787 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
5788 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
5789 fpr_offset &= -UNITS_PER_FPVALUE;
5791 t = fold_build_pointer_plus_hwi (t, -fpr_offset);
5792 t = build2 (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
5793 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5795 /* Emit code to initialize GOFF, the offset from GTOP of the
5796 next GPR argument. */
5797 t = build2 (MODIFY_EXPR, TREE_TYPE (goff), goff,
5798 build_int_cst (TREE_TYPE (goff), gpr_save_area_size));
5799 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5801 /* Likewise emit code to initialize FOFF, the offset from FTOP
5802 of the next FPR argument. */
5803 t = build2 (MODIFY_EXPR, TREE_TYPE (foff), foff,
5804 build_int_cst (TREE_TYPE (foff), fpr_save_area_size));
5805 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5809 nextarg = plus_constant (Pmode, nextarg, -cfun->machine->varargs_size);
5810 std_expand_builtin_va_start (valist, nextarg);
5814 /* Like std_gimplify_va_arg_expr, but apply alignment to zero-sized
5818 mips_std_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
5821 tree addr, t, type_size, rounded_size, valist_tmp;
5822 unsigned HOST_WIDE_INT align, boundary;
5825 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, false);
5827 type = build_pointer_type (type);
5829 align = PARM_BOUNDARY / BITS_PER_UNIT;
5830 boundary = targetm.calls.function_arg_boundary (TYPE_MODE (type), type);
5832 /* When we align parameter on stack for caller, if the parameter
5833 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
5834 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
5835 here with caller. */
5836 if (boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
5837 boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
5839 boundary /= BITS_PER_UNIT;
5841 /* Hoist the valist value into a temporary for the moment. */
5842 valist_tmp = get_initialized_tmp_var (valist, pre_p, NULL);
5844 /* va_list pointer is aligned to PARM_BOUNDARY. If argument actually
5845 requires greater alignment, we must perform dynamic alignment. */
5846 if (boundary > align)
5848 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
5849 fold_build_pointer_plus_hwi (valist_tmp, boundary - 1));
5850 gimplify_and_add (t, pre_p);
5852 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
5853 fold_build2 (BIT_AND_EXPR, TREE_TYPE (valist),
5855 build_int_cst (TREE_TYPE (valist), -boundary)));
5856 gimplify_and_add (t, pre_p);
5861 /* If the actual alignment is less than the alignment of the type,
5862 adjust the type accordingly so that we don't assume strict alignment
5863 when dereferencing the pointer. */
5864 boundary *= BITS_PER_UNIT;
5865 if (boundary < TYPE_ALIGN (type))
5867 type = build_variant_type_copy (type);
5868 TYPE_ALIGN (type) = boundary;
5871 /* Compute the rounded size of the type. */
5872 type_size = size_in_bytes (type);
5873 rounded_size = round_up (type_size, align);
5875 /* Reduce rounded_size so it's sharable with the postqueue. */
5876 gimplify_expr (&rounded_size, pre_p, post_p, is_gimple_val, fb_rvalue);
5880 if (PAD_VARARGS_DOWN && !integer_zerop (rounded_size))
5882 /* Small args are padded downward. */
5883 t = fold_build2_loc (input_location, GT_EXPR, sizetype,
5884 rounded_size, size_int (align));
5885 t = fold_build3 (COND_EXPR, sizetype, t, size_zero_node,
5886 size_binop (MINUS_EXPR, rounded_size, type_size));
5887 addr = fold_build_pointer_plus (addr, t);
5890 /* Compute new value for AP. */
5891 t = fold_build_pointer_plus (valist_tmp, rounded_size);
5892 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
5893 gimplify_and_add (t, pre_p);
5895 addr = fold_convert (build_pointer_type (type), addr);
5898 addr = build_va_arg_indirect_ref (addr);
5900 return build_va_arg_indirect_ref (addr);
5903 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
5906 mips_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
5912 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
5914 type = build_pointer_type (type);
5916 if (!EABI_FLOAT_VARARGS_P)
5917 addr = mips_std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5920 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5921 tree ovfl, top, off, align;
5922 HOST_WIDE_INT size, rsize, osize;
5925 f_ovfl = TYPE_FIELDS (va_list_type_node);
5926 f_gtop = DECL_CHAIN (f_ovfl);
5927 f_ftop = DECL_CHAIN (f_gtop);
5928 f_goff = DECL_CHAIN (f_ftop);
5929 f_foff = DECL_CHAIN (f_goff);
5933 TOP be the top of the GPR or FPR save area;
5934 OFF be the offset from TOP of the next register;
5935 ADDR_RTX be the address of the argument;
5936 SIZE be the number of bytes in the argument type;
5937 RSIZE be the number of bytes used to store the argument
5938 when it's in the register save area; and
5939 OSIZE be the number of bytes used to store it when it's
5940 in the stack overflow area.
5942 The code we want is:
5944 1: off &= -rsize; // round down
5947 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
5952 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
5953 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
5957 [1] and [9] can sometimes be optimized away. */
5959 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5961 size = int_size_in_bytes (type);
5963 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
5964 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
5966 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop),
5967 unshare_expr (valist), f_ftop, NULL_TREE);
5968 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff),
5969 unshare_expr (valist), f_foff, NULL_TREE);
5971 /* When va_start saves FPR arguments to the stack, each slot
5972 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
5973 argument's precision. */
5974 rsize = UNITS_PER_HWFPVALUE;
5976 /* Overflow arguments are padded to UNITS_PER_WORD bytes
5977 (= PARM_BOUNDARY bits). This can be different from RSIZE
5980 (1) On 32-bit targets when TYPE is a structure such as:
5982 struct s { float f; };
5984 Such structures are passed in paired FPRs, so RSIZE
5985 will be 8 bytes. However, the structure only takes
5986 up 4 bytes of memory, so OSIZE will only be 4.
5988 (2) In combinations such as -mgp64 -msingle-float
5989 -fshort-double. Doubles passed in registers will then take
5990 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
5991 stack take up UNITS_PER_WORD bytes. */
5992 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
5996 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop),
5997 unshare_expr (valist), f_gtop, NULL_TREE);
5998 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff),
5999 unshare_expr (valist), f_goff, NULL_TREE);
6000 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
6001 if (rsize > UNITS_PER_WORD)
6003 /* [1] Emit code for: off &= -rsize. */
6004 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), unshare_expr (off),
6005 build_int_cst (TREE_TYPE (off), -rsize));
6006 gimplify_assign (unshare_expr (off), t, pre_p);
6011 /* [2] Emit code to branch if off == 0. */
6012 t = build2 (NE_EXPR, boolean_type_node, unshare_expr (off),
6013 build_int_cst (TREE_TYPE (off), 0));
6014 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
6016 /* [5] Emit code for: off -= rsize. We do this as a form of
6017 post-decrement not available to C. */
6018 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
6019 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
6021 /* [4] Emit code for:
6022 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
6023 t = fold_convert (sizetype, t);
6024 t = fold_build1 (NEGATE_EXPR, sizetype, t);
6025 t = fold_build_pointer_plus (top, t);
6026 if (BYTES_BIG_ENDIAN && rsize > size)
6027 t = fold_build_pointer_plus_hwi (t, rsize - size);
6028 COND_EXPR_THEN (addr) = t;
6030 if (osize > UNITS_PER_WORD)
6032 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
6033 t = fold_build_pointer_plus_hwi (unshare_expr (ovfl), osize - 1);
6034 u = build_int_cst (TREE_TYPE (t), -osize);
6035 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t, u);
6036 align = build2 (MODIFY_EXPR, TREE_TYPE (ovfl),
6037 unshare_expr (ovfl), t);
6042 /* [10, 11] Emit code for:
6043 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
6045 u = fold_convert (TREE_TYPE (ovfl), build_int_cst (NULL_TREE, osize));
6046 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
6047 if (BYTES_BIG_ENDIAN && osize > size)
6048 t = fold_build_pointer_plus_hwi (t, osize - size);
6050 /* String [9] and [10, 11] together. */
6052 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
6053 COND_EXPR_ELSE (addr) = t;
6055 addr = fold_convert (build_pointer_type (type), addr);
6056 addr = build_va_arg_indirect_ref (addr);
6060 addr = build_va_arg_indirect_ref (addr);
6065 /* Declare a unique, locally-binding function called NAME, then start
6069 mips_start_unique_function (const char *name)
6073 decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
6074 get_identifier (name),
6075 build_function_type_list (void_type_node, NULL_TREE));
6076 DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
6077 NULL_TREE, void_type_node);
6078 TREE_PUBLIC (decl) = 1;
6079 TREE_STATIC (decl) = 1;
6081 DECL_COMDAT_GROUP (decl) = DECL_ASSEMBLER_NAME (decl);
6083 targetm.asm_out.unique_section (decl, 0);
6084 switch_to_section (get_named_section (decl, NULL, 0));
6086 targetm.asm_out.globalize_label (asm_out_file, name);
6087 fputs ("\t.hidden\t", asm_out_file);
6088 assemble_name (asm_out_file, name);
6089 putc ('\n', asm_out_file);
6092 /* Start a definition of function NAME. MIPS16_P indicates whether the
6093 function contains MIPS16 code. */
6096 mips_start_function_definition (const char *name, bool mips16_p)
6099 fprintf (asm_out_file, "\t.set\tmips16\n");
6101 fprintf (asm_out_file, "\t.set\tnomips16\n");
6103 if (!flag_inhibit_size_directive)
6105 fputs ("\t.ent\t", asm_out_file);
6106 assemble_name (asm_out_file, name);
6107 fputs ("\n", asm_out_file);
6110 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, name, "function");
6112 /* Start the definition proper. */
6113 assemble_name (asm_out_file, name);
6114 fputs (":\n", asm_out_file);
6117 /* End a function definition started by mips_start_function_definition. */
6120 mips_end_function_definition (const char *name)
6122 if (!flag_inhibit_size_directive)
6124 fputs ("\t.end\t", asm_out_file);
6125 assemble_name (asm_out_file, name);
6126 fputs ("\n", asm_out_file);
6130 /* Output a definition of the __mips16_rdhwr function. */
6133 mips_output_mips16_rdhwr (void)
6137 name = "__mips16_rdhwr";
6138 mips_start_unique_function (name);
6139 mips_start_function_definition (name, false);
6140 fprintf (asm_out_file,
6142 "\t.set\tmips32r2\n"
6143 "\t.set\tnoreorder\n"
6147 mips_end_function_definition (name);
6150 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
6153 mips_ok_for_lazy_binding_p (rtx x)
6155 return (TARGET_USE_GOT
6156 && GET_CODE (x) == SYMBOL_REF
6157 && !SYMBOL_REF_BIND_NOW_P (x)
6158 && !mips_symbol_binds_local_p (x));
6161 /* Load function address ADDR into register DEST. TYPE is as for
6162 mips_expand_call. Return true if we used an explicit lazy-binding
6166 mips_load_call_address (enum mips_call_type type, rtx dest, rtx addr)
6168 /* If we're generating PIC, and this call is to a global function,
6169 try to allow its address to be resolved lazily. This isn't
6170 possible for sibcalls when $gp is call-saved because the value
6171 of $gp on entry to the stub would be our caller's gp, not ours. */
6172 if (TARGET_EXPLICIT_RELOCS
6173 && !(type == MIPS_CALL_SIBCALL && TARGET_CALL_SAVED_GP)
6174 && mips_ok_for_lazy_binding_p (addr))
6176 addr = mips_got_load (dest, addr, SYMBOL_GOTOFF_CALL);
6177 emit_insn (gen_rtx_SET (VOIDmode, dest, addr));
6182 mips_emit_move (dest, addr);
6187 /* Each locally-defined hard-float MIPS16 function has a local symbol
6188 associated with it. This hash table maps the function symbol (FUNC)
6189 to the local symbol (LOCAL). */
6190 struct GTY(()) mips16_local_alias {
6194 static GTY ((param_is (struct mips16_local_alias))) htab_t mips16_local_aliases;
6196 /* Hash table callbacks for mips16_local_aliases. */
6199 mips16_local_aliases_hash (const void *entry)
6201 const struct mips16_local_alias *alias;
6203 alias = (const struct mips16_local_alias *) entry;
6204 return htab_hash_string (XSTR (alias->func, 0));
6208 mips16_local_aliases_eq (const void *entry1, const void *entry2)
6210 const struct mips16_local_alias *alias1, *alias2;
6212 alias1 = (const struct mips16_local_alias *) entry1;
6213 alias2 = (const struct mips16_local_alias *) entry2;
6214 return rtx_equal_p (alias1->func, alias2->func);
6217 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
6218 Return a local alias for it, creating a new one if necessary. */
6221 mips16_local_alias (rtx func)
6223 struct mips16_local_alias *alias, tmp_alias;
6226 /* Create the hash table if this is the first call. */
6227 if (mips16_local_aliases == NULL)
6228 mips16_local_aliases = htab_create_ggc (37, mips16_local_aliases_hash,
6229 mips16_local_aliases_eq, NULL);
6231 /* Look up the function symbol, creating a new entry if need be. */
6232 tmp_alias.func = func;
6233 slot = htab_find_slot (mips16_local_aliases, &tmp_alias, INSERT);
6234 gcc_assert (slot != NULL);
6236 alias = (struct mips16_local_alias *) *slot;
6239 const char *func_name, *local_name;
6242 /* Create a new SYMBOL_REF for the local symbol. The choice of
6243 __fn_local_* is based on the __fn_stub_* names that we've
6244 traditionally used for the non-MIPS16 stub. */
6245 func_name = targetm.strip_name_encoding (XSTR (func, 0));
6246 local_name = ACONCAT (("__fn_local_", func_name, NULL));
6247 local = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (local_name));
6248 SYMBOL_REF_FLAGS (local) = SYMBOL_REF_FLAGS (func) | SYMBOL_FLAG_LOCAL;
6250 /* Create a new structure to represent the mapping. */
6251 alias = ggc_alloc_mips16_local_alias ();
6253 alias->local = local;
6256 return alias->local;
6259 /* A chained list of functions for which mips16_build_call_stub has already
6260 generated a stub. NAME is the name of the function and FP_RET_P is true
6261 if the function returns a value in floating-point registers. */
6262 struct mips16_stub {
6263 struct mips16_stub *next;
6267 static struct mips16_stub *mips16_stubs;
6269 /* Return the two-character string that identifies floating-point
6270 return mode MODE in the name of a MIPS16 function stub. */
6273 mips16_call_stub_mode_suffix (enum machine_mode mode)
6277 else if (mode == DFmode)
6279 else if (mode == SCmode)
6281 else if (mode == DCmode)
6283 else if (mode == V2SFmode)
6289 /* Write instructions to move a 32-bit value between general register
6290 GPREG and floating-point register FPREG. DIRECTION is 't' to move
6291 from GPREG to FPREG and 'f' to move in the opposite direction. */
6294 mips_output_32bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
6296 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6297 reg_names[gpreg], reg_names[fpreg]);
6300 /* Likewise for 64-bit values. */
6303 mips_output_64bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
6306 fprintf (asm_out_file, "\tdm%cc1\t%s,%s\n", direction,
6307 reg_names[gpreg], reg_names[fpreg]);
6308 else if (TARGET_FLOAT64)
6310 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6311 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
6312 fprintf (asm_out_file, "\tm%chc1\t%s,%s\n", direction,
6313 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg]);
6317 /* Move the least-significant word. */
6318 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6319 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
6320 /* ...then the most significant word. */
6321 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6322 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg + 1]);
6326 /* Write out code to move floating-point arguments into or out of
6327 general registers. FP_CODE is the code describing which arguments
6328 are present (see the comment above the definition of CUMULATIVE_ARGS
6329 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
6332 mips_output_args_xfer (int fp_code, char direction)
6334 unsigned int gparg, fparg, f;
6335 CUMULATIVE_ARGS cum;
6337 /* This code only works for o32 and o64. */
6338 gcc_assert (TARGET_OLDABI);
6340 mips_init_cumulative_args (&cum, NULL);
6342 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
6344 enum machine_mode mode;
6345 struct mips_arg_info info;
6349 else if ((f & 3) == 2)
6354 mips_get_arg_info (&info, &cum, mode, NULL, true);
6355 gparg = mips_arg_regno (&info, false);
6356 fparg = mips_arg_regno (&info, true);
6359 mips_output_32bit_xfer (direction, gparg, fparg);
6361 mips_output_64bit_xfer (direction, gparg, fparg);
6363 mips_function_arg_advance (pack_cumulative_args (&cum), mode, NULL, true);
6367 /* Write a MIPS16 stub for the current function. This stub is used
6368 for functions which take arguments in the floating-point registers.
6369 It is normal-mode code that moves the floating-point arguments
6370 into the general registers and then jumps to the MIPS16 code. */
6373 mips16_build_function_stub (void)
6375 const char *fnname, *alias_name, *separator;
6376 char *secname, *stubname;
6381 /* Create the name of the stub, and its unique section. */
6382 symbol = XEXP (DECL_RTL (current_function_decl), 0);
6383 alias = mips16_local_alias (symbol);
6385 fnname = targetm.strip_name_encoding (XSTR (symbol, 0));
6386 alias_name = targetm.strip_name_encoding (XSTR (alias, 0));
6387 secname = ACONCAT ((".mips16.fn.", fnname, NULL));
6388 stubname = ACONCAT (("__fn_stub_", fnname, NULL));
6390 /* Build a decl for the stub. */
6391 stubdecl = build_decl (BUILTINS_LOCATION,
6392 FUNCTION_DECL, get_identifier (stubname),
6393 build_function_type_list (void_type_node, NULL_TREE));
6394 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
6395 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
6396 RESULT_DECL, NULL_TREE, void_type_node);
6398 /* Output a comment. */
6399 fprintf (asm_out_file, "\t# Stub function for %s (",
6400 current_function_name ());
6402 for (f = (unsigned int) crtl->args.info.fp_code; f != 0; f >>= 2)
6404 fprintf (asm_out_file, "%s%s", separator,
6405 (f & 3) == 1 ? "float" : "double");
6408 fprintf (asm_out_file, ")\n");
6410 /* Start the function definition. */
6411 assemble_start_function (stubdecl, stubname);
6412 mips_start_function_definition (stubname, false);
6414 /* If generating pic2 code, either set up the global pointer or
6416 if (TARGET_ABICALLS_PIC2)
6418 if (TARGET_ABSOLUTE_ABICALLS)
6419 fprintf (asm_out_file, "\t.option\tpic0\n");
6422 output_asm_insn ("%(.cpload\t%^%)", NULL);
6423 /* Emit an R_MIPS_NONE relocation to tell the linker what the
6424 target function is. Use a local GOT access when loading the
6425 symbol, to cut down on the number of unnecessary GOT entries
6426 for stubs that aren't needed. */
6427 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol);
6432 /* Load the address of the MIPS16 function into $25. Do this first so
6433 that targets with coprocessor interlocks can use an MFC1 to fill the
6435 output_asm_insn ("la\t%^,%0", &symbol);
6437 /* Move the arguments from floating-point registers to general registers. */
6438 mips_output_args_xfer (crtl->args.info.fp_code, 'f');
6440 /* Jump to the MIPS16 function. */
6441 output_asm_insn ("jr\t%^", NULL);
6443 if (TARGET_ABICALLS_PIC2 && TARGET_ABSOLUTE_ABICALLS)
6444 fprintf (asm_out_file, "\t.option\tpic2\n");
6446 mips_end_function_definition (stubname);
6448 /* If the linker needs to create a dynamic symbol for the target
6449 function, it will associate the symbol with the stub (which,
6450 unlike the target function, follows the proper calling conventions).
6451 It is therefore useful to have a local alias for the target function,
6452 so that it can still be identified as MIPS16 code. As an optimization,
6453 this symbol can also be used for indirect MIPS16 references from
6454 within this file. */
6455 ASM_OUTPUT_DEF (asm_out_file, alias_name, fnname);
6457 switch_to_section (function_section (current_function_decl));
6460 /* The current function is a MIPS16 function that returns a value in an FPR.
6461 Copy the return value from its soft-float to its hard-float location.
6462 libgcc2 has special non-MIPS16 helper functions for each case. */
6465 mips16_copy_fpr_return_value (void)
6467 rtx fn, insn, retval;
6469 enum machine_mode return_mode;
6472 return_type = DECL_RESULT (current_function_decl);
6473 return_mode = DECL_MODE (return_type);
6475 name = ACONCAT (("__mips16_ret_",
6476 mips16_call_stub_mode_suffix (return_mode),
6478 fn = mips16_stub_function (name);
6480 /* The function takes arguments in $2 (and possibly $3), so calls
6481 to it cannot be lazily bound. */
6482 SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_BIND_NOW;
6484 /* Model the call as something that takes the GPR return value as
6485 argument and returns an "updated" value. */
6486 retval = gen_rtx_REG (return_mode, GP_RETURN);
6487 insn = mips_expand_call (MIPS_CALL_EPILOGUE, retval, fn,
6488 const0_rtx, NULL_RTX, false);
6489 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), retval);
6492 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
6493 RETVAL is the location of the return value, or null if this is
6494 a "call" rather than a "call_value". ARGS_SIZE is the size of the
6495 arguments and FP_CODE is the code built by mips_function_arg;
6496 see the comment before the fp_code field in CUMULATIVE_ARGS for details.
6498 There are three alternatives:
6500 - If a stub was needed, emit the call and return the call insn itself.
6502 - If we can avoid using a stub by redirecting the call, set *FN_PTR
6503 to the new target and return null.
6505 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
6508 A stub is needed for calls to functions that, in normal mode,
6509 receive arguments in FPRs or return values in FPRs. The stub
6510 copies the arguments from their soft-float positions to their
6511 hard-float positions, calls the real function, then copies the
6512 return value from its hard-float position to its soft-float
6515 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
6516 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
6517 automatically redirects the JAL to the stub, otherwise the JAL
6518 continues to call FN directly. */
6521 mips16_build_call_stub (rtx retval, rtx *fn_ptr, rtx args_size, int fp_code)
6525 struct mips16_stub *l;
6528 /* We don't need to do anything if we aren't in MIPS16 mode, or if
6529 we were invoked with the -msoft-float option. */
6530 if (!TARGET_MIPS16 || TARGET_SOFT_FLOAT_ABI)
6533 /* Figure out whether the value might come back in a floating-point
6535 fp_ret_p = retval && mips_return_mode_in_fpr_p (GET_MODE (retval));
6537 /* We don't need to do anything if there were no floating-point
6538 arguments and the value will not be returned in a floating-point
6540 if (fp_code == 0 && !fp_ret_p)
6543 /* We don't need to do anything if this is a call to a special
6544 MIPS16 support function. */
6546 if (mips16_stub_function_p (fn))
6549 /* If we're calling a locally-defined MIPS16 function, we know that
6550 it will return values in both the "soft-float" and "hard-float"
6551 registers. There is no need to use a stub to move the latter
6553 if (fp_code == 0 && mips16_local_function_p (fn))
6556 /* This code will only work for o32 and o64 abis. The other ABI's
6557 require more sophisticated support. */
6558 gcc_assert (TARGET_OLDABI);
6560 /* If we're calling via a function pointer, use one of the magic
6561 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
6562 Each stub expects the function address to arrive in register $2. */
6563 if (GET_CODE (fn) != SYMBOL_REF
6564 || !call_insn_operand (fn, VOIDmode))
6567 rtx stub_fn, insn, addr;
6570 /* If this is a locally-defined and locally-binding function,
6571 avoid the stub by calling the local alias directly. */
6572 if (mips16_local_function_p (fn))
6574 *fn_ptr = mips16_local_alias (fn);
6578 /* Create a SYMBOL_REF for the libgcc.a function. */
6580 sprintf (buf, "__mips16_call_stub_%s_%d",
6581 mips16_call_stub_mode_suffix (GET_MODE (retval)),
6584 sprintf (buf, "__mips16_call_stub_%d", fp_code);
6585 stub_fn = mips16_stub_function (buf);
6587 /* The function uses $2 as an argument, so calls to it
6588 cannot be lazily bound. */
6589 SYMBOL_REF_FLAGS (stub_fn) |= SYMBOL_FLAG_BIND_NOW;
6591 /* Load the target function into $2. */
6592 addr = gen_rtx_REG (Pmode, GP_REG_FIRST + 2);
6593 lazy_p = mips_load_call_address (MIPS_CALL_NORMAL, addr, fn);
6595 /* Emit the call. */
6596 insn = mips_expand_call (MIPS_CALL_NORMAL, retval, stub_fn,
6597 args_size, NULL_RTX, lazy_p);
6599 /* Tell GCC that this call does indeed use the value of $2. */
6600 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), addr);
6602 /* If we are handling a floating-point return value, we need to
6603 save $18 in the function prologue. Putting a note on the
6604 call will mean that df_regs_ever_live_p ($18) will be true if the
6605 call is not eliminated, and we can check that in the prologue
6608 CALL_INSN_FUNCTION_USAGE (insn) =
6609 gen_rtx_EXPR_LIST (VOIDmode,
6610 gen_rtx_CLOBBER (VOIDmode,
6611 gen_rtx_REG (word_mode, 18)),
6612 CALL_INSN_FUNCTION_USAGE (insn));
6617 /* We know the function we are going to call. If we have already
6618 built a stub, we don't need to do anything further. */
6619 fnname = targetm.strip_name_encoding (XSTR (fn, 0));
6620 for (l = mips16_stubs; l != NULL; l = l->next)
6621 if (strcmp (l->name, fnname) == 0)
6626 const char *separator;
6627 char *secname, *stubname;
6628 tree stubid, stubdecl;
6631 /* If the function does not return in FPRs, the special stub
6635 If the function does return in FPRs, the stub section is named
6636 .mips16.call.fp.FNNAME
6638 Build a decl for the stub. */
6639 secname = ACONCAT ((".mips16.call.", fp_ret_p ? "fp." : "",
6641 stubname = ACONCAT (("__call_stub_", fp_ret_p ? "fp_" : "",
6643 stubid = get_identifier (stubname);
6644 stubdecl = build_decl (BUILTINS_LOCATION,
6645 FUNCTION_DECL, stubid,
6646 build_function_type_list (void_type_node,
6648 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
6649 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
6650 RESULT_DECL, NULL_TREE,
6653 /* Output a comment. */
6654 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
6656 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
6660 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
6662 fprintf (asm_out_file, "%s%s", separator,
6663 (f & 3) == 1 ? "float" : "double");
6666 fprintf (asm_out_file, ")\n");
6668 /* Start the function definition. */
6669 assemble_start_function (stubdecl, stubname);
6670 mips_start_function_definition (stubname, false);
6674 fprintf (asm_out_file, "\t.cfi_startproc\n");
6676 /* Create a fake CFA 4 bytes below the stack pointer.
6677 This works around unwinders (like libgcc's) that expect
6678 the CFA for non-signal frames to be unique. */
6679 fprintf (asm_out_file, "\t.cfi_def_cfa 29,-4\n");
6681 /* "Save" $sp in itself so we don't use the fake CFA.
6682 This is: DW_CFA_val_expression r29, { DW_OP_reg29 }. */
6683 fprintf (asm_out_file, "\t.cfi_escape 0x16,29,1,0x6d\n");
6687 /* Load the address of the MIPS16 function into $25. Do this
6688 first so that targets with coprocessor interlocks can use
6689 an MFC1 to fill the delay slot. */
6690 if (TARGET_EXPLICIT_RELOCS)
6692 output_asm_insn ("lui\t%^,%%hi(%0)", &fn);
6693 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn);
6696 output_asm_insn ("la\t%^,%0", &fn);
6699 /* Move the arguments from general registers to floating-point
6701 mips_output_args_xfer (fp_code, 't');
6705 /* Save the return address in $18 and call the non-MIPS16 function.
6706 The stub's caller knows that $18 might be clobbered, even though
6707 $18 is usually a call-saved register. */
6708 fprintf (asm_out_file, "\tmove\t%s,%s\n",
6709 reg_names[GP_REG_FIRST + 18], reg_names[RETURN_ADDR_REGNUM]);
6710 output_asm_insn (MIPS_CALL ("jal", &fn, 0, -1), &fn);
6711 fprintf (asm_out_file, "\t.cfi_register 31,18\n");
6713 /* Move the result from floating-point registers to
6714 general registers. */
6715 switch (GET_MODE (retval))
6718 mips_output_32bit_xfer ('f', GP_RETURN + TARGET_BIG_ENDIAN,
6720 ? FP_REG_FIRST + MAX_FPRS_PER_FMT
6722 mips_output_32bit_xfer ('f', GP_RETURN + TARGET_LITTLE_ENDIAN,
6723 TARGET_LITTLE_ENDIAN
6724 ? FP_REG_FIRST + MAX_FPRS_PER_FMT
6726 if (GET_MODE (retval) == SCmode && TARGET_64BIT)
6728 /* On 64-bit targets, complex floats are returned in
6729 a single GPR, such that "sd" on a suitably-aligned
6730 target would store the value correctly. */
6731 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
6732 reg_names[GP_RETURN + TARGET_BIG_ENDIAN],
6733 reg_names[GP_RETURN + TARGET_BIG_ENDIAN]);
6734 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
6735 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN],
6736 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN]);
6737 fprintf (asm_out_file, "\tdsrl\t%s,%s,32\n",
6738 reg_names[GP_RETURN + TARGET_BIG_ENDIAN],
6739 reg_names[GP_RETURN + TARGET_BIG_ENDIAN]);
6740 fprintf (asm_out_file, "\tor\t%s,%s,%s\n",
6741 reg_names[GP_RETURN],
6742 reg_names[GP_RETURN],
6743 reg_names[GP_RETURN + 1]);
6748 mips_output_32bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6752 mips_output_64bit_xfer ('f', GP_RETURN + (8 / UNITS_PER_WORD),
6753 FP_REG_FIRST + MAX_FPRS_PER_FMT);
6757 mips_output_64bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6763 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 18]);
6764 fprintf (asm_out_file, "\t.cfi_endproc\n");
6768 /* Jump to the previously-loaded address. */
6769 output_asm_insn ("jr\t%^", NULL);
6772 #ifdef ASM_DECLARE_FUNCTION_SIZE
6773 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
6776 mips_end_function_definition (stubname);
6778 /* Record this stub. */
6779 l = XNEW (struct mips16_stub);
6780 l->name = xstrdup (fnname);
6781 l->fp_ret_p = fp_ret_p;
6782 l->next = mips16_stubs;
6786 /* If we expect a floating-point return value, but we've built a
6787 stub which does not expect one, then we're in trouble. We can't
6788 use the existing stub, because it won't handle the floating-point
6789 value. We can't build a new stub, because the linker won't know
6790 which stub to use for the various calls in this object file.
6791 Fortunately, this case is illegal, since it means that a function
6792 was declared in two different ways in a single compilation. */
6793 if (fp_ret_p && !l->fp_ret_p)
6794 error ("cannot handle inconsistent calls to %qs", fnname);
6796 if (retval == NULL_RTX)
6797 insn = gen_call_internal_direct (fn, args_size);
6799 insn = gen_call_value_internal_direct (retval, fn, args_size);
6800 insn = mips_emit_call_insn (insn, fn, fn, false);
6802 /* If we are calling a stub which handles a floating-point return
6803 value, we need to arrange to save $18 in the prologue. We do this
6804 by marking the function call as using the register. The prologue
6805 will later see that it is used, and emit code to save it. */
6807 CALL_INSN_FUNCTION_USAGE (insn) =
6808 gen_rtx_EXPR_LIST (VOIDmode,
6809 gen_rtx_CLOBBER (VOIDmode,
6810 gen_rtx_REG (word_mode, 18)),
6811 CALL_INSN_FUNCTION_USAGE (insn));
6816 /* Expand a call of type TYPE. RESULT is where the result will go (null
6817 for "call"s and "sibcall"s), ADDR is the address of the function,
6818 ARGS_SIZE is the size of the arguments and AUX is the value passed
6819 to us by mips_function_arg. LAZY_P is true if this call already
6820 involves a lazily-bound function address (such as when calling
6821 functions through a MIPS16 hard-float stub).
6823 Return the call itself. */
6826 mips_expand_call (enum mips_call_type type, rtx result, rtx addr,
6827 rtx args_size, rtx aux, bool lazy_p)
6829 rtx orig_addr, pattern, insn;
6832 fp_code = aux == 0 ? 0 : (int) GET_MODE (aux);
6833 insn = mips16_build_call_stub (result, &addr, args_size, fp_code);
6836 gcc_assert (!lazy_p && type == MIPS_CALL_NORMAL);
6841 if (!call_insn_operand (addr, VOIDmode))
6843 if (type == MIPS_CALL_EPILOGUE)
6844 addr = MIPS_EPILOGUE_TEMP (Pmode);
6846 addr = gen_reg_rtx (Pmode);
6847 lazy_p |= mips_load_call_address (type, addr, orig_addr);
6852 rtx (*fn) (rtx, rtx);
6854 if (type == MIPS_CALL_SIBCALL)
6855 fn = gen_sibcall_internal;
6857 fn = gen_call_internal;
6859 pattern = fn (addr, args_size);
6861 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
6863 /* Handle return values created by mips_return_fpr_pair. */
6864 rtx (*fn) (rtx, rtx, rtx, rtx);
6867 if (type == MIPS_CALL_SIBCALL)
6868 fn = gen_sibcall_value_multiple_internal;
6870 fn = gen_call_value_multiple_internal;
6872 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
6873 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
6874 pattern = fn (reg1, addr, args_size, reg2);
6878 rtx (*fn) (rtx, rtx, rtx);
6880 if (type == MIPS_CALL_SIBCALL)
6881 fn = gen_sibcall_value_internal;
6883 fn = gen_call_value_internal;
6885 /* Handle return values created by mips_return_fpr_single. */
6886 if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 1)
6887 result = XEXP (XVECEXP (result, 0, 0), 0);
6888 pattern = fn (result, addr, args_size);
6891 return mips_emit_call_insn (pattern, orig_addr, addr, lazy_p);
6894 /* Split call instruction INSN into a $gp-clobbering call and
6895 (where necessary) an instruction to restore $gp from its save slot.
6896 CALL_PATTERN is the pattern of the new call. */
6899 mips_split_call (rtx insn, rtx call_pattern)
6901 emit_call_insn (call_pattern);
6902 if (!find_reg_note (insn, REG_NORETURN, 0))
6903 /* Pick a temporary register that is suitable for both MIPS16 and
6904 non-MIPS16 code. $4 and $5 are used for returning complex double
6905 values in soft-float code, so $6 is the first suitable candidate. */
6906 mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode, GP_ARG_FIRST + 2));
6909 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
6912 mips_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
6914 if (!TARGET_SIBCALLS)
6917 /* Interrupt handlers need special epilogue code and therefore can't
6919 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
6922 /* We can't do a sibcall if the called function is a MIPS16 function
6923 because there is no direct "jx" instruction equivalent to "jalx" to
6924 switch the ISA mode. We only care about cases where the sibling
6925 and normal calls would both be direct. */
6927 && mips_use_mips16_mode_p (decl)
6928 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
6931 /* When -minterlink-mips16 is in effect, assume that non-locally-binding
6932 functions could be MIPS16 ones unless an attribute explicitly tells
6934 if (TARGET_INTERLINK_MIPS16
6936 && (DECL_EXTERNAL (decl) || !targetm.binds_local_p (decl))
6937 && !mips_nomips16_decl_p (decl)
6938 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
6945 /* Emit code to move general operand SRC into condition-code
6946 register DEST given that SCRATCH is a scratch TFmode FPR.
6953 where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */
6956 mips_expand_fcc_reload (rtx dest, rtx src, rtx scratch)
6960 /* Change the source to SFmode. */
6962 src = adjust_address (src, SFmode, 0);
6963 else if (REG_P (src) || GET_CODE (src) == SUBREG)
6964 src = gen_rtx_REG (SFmode, true_regnum (src));
6966 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
6967 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + MAX_FPRS_PER_FMT);
6969 mips_emit_move (copy_rtx (fp1), src);
6970 mips_emit_move (copy_rtx (fp2), CONST0_RTX (SFmode));
6971 emit_insn (gen_slt_sf (dest, fp2, fp1));
6974 /* Implement MOVE_BY_PIECES_P. */
6977 mips_move_by_pieces_p (unsigned HOST_WIDE_INT size, unsigned int align)
6981 /* movmemsi is meant to generate code that is at least as good as
6982 move_by_pieces. However, movmemsi effectively uses a by-pieces
6983 implementation both for moves smaller than a word and for
6984 word-aligned moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT
6985 bytes. We should allow the tree-level optimisers to do such
6986 moves by pieces, as it often exposes other optimization
6987 opportunities. We might as well continue to use movmemsi at
6988 the rtl level though, as it produces better code when
6989 scheduling is disabled (such as at -O). */
6990 if (currently_expanding_to_rtl)
6992 if (align < BITS_PER_WORD)
6993 return size < UNITS_PER_WORD;
6994 return size <= MIPS_MAX_MOVE_BYTES_STRAIGHT;
6996 /* The default value. If this becomes a target hook, we should
6997 call the default definition instead. */
6998 return (move_by_pieces_ninsns (size, align, MOVE_MAX_PIECES + 1)
6999 < (unsigned int) MOVE_RATIO (optimize_insn_for_speed_p ()));
7002 /* Implement STORE_BY_PIECES_P. */
7005 mips_store_by_pieces_p (unsigned HOST_WIDE_INT size, unsigned int align)
7007 /* Storing by pieces involves moving constants into registers
7008 of size MIN (ALIGN, BITS_PER_WORD), then storing them.
7009 We need to decide whether it is cheaper to load the address of
7010 constant data into a register and use a block move instead. */
7012 /* If the data is only byte aligned, then:
7014 (a1) A block move of less than 4 bytes would involve three 3 LBs and
7015 3 SBs. We might as well use 3 single-instruction LIs and 3 SBs
7018 (a2) A block move of 4 bytes from aligned source data can use an
7019 LW/SWL/SWR sequence. This is often better than the 4 LIs and
7020 4 SBs that we would generate when storing by pieces. */
7021 if (align <= BITS_PER_UNIT)
7024 /* If the data is 2-byte aligned, then:
7026 (b1) A block move of less than 4 bytes would use a combination of LBs,
7027 LHs, SBs and SHs. We get better code by using single-instruction
7028 LIs, SBs and SHs instead.
7030 (b2) A block move of 4 bytes from aligned source data would again use
7031 an LW/SWL/SWR sequence. In most cases, loading the address of
7032 the source data would require at least one extra instruction.
7033 It is often more efficient to use 2 single-instruction LIs and
7036 (b3) A block move of up to 3 additional bytes would be like (b1).
7038 (b4) A block move of 8 bytes from aligned source data can use two
7039 LW/SWL/SWR sequences or a single LD/SDL/SDR sequence. Both
7040 sequences are better than the 4 LIs and 4 SHs that we'd generate
7041 when storing by pieces.
7043 The reasoning for higher alignments is similar:
7045 (c1) A block move of less than 4 bytes would be the same as (b1).
7047 (c2) A block move of 4 bytes would use an LW/SW sequence. Again,
7048 loading the address of the source data would typically require
7049 at least one extra instruction. It is generally better to use
7052 (c3) A block move of up to 3 additional bytes would be like (b1).
7054 (c4) A block move of 8 bytes can use two LW/SW sequences or a single
7055 LD/SD sequence, and in these cases we've traditionally preferred
7056 the memory copy over the more bulky constant moves. */
7060 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
7061 Assume that the areas do not overlap. */
7064 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
7066 HOST_WIDE_INT offset, delta;
7067 unsigned HOST_WIDE_INT bits;
7069 enum machine_mode mode;
7072 /* Work out how many bits to move at a time. If both operands have
7073 half-word alignment, it is usually better to move in half words.
7074 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
7075 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
7076 Otherwise move word-sized chunks. */
7077 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
7078 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
7079 bits = BITS_PER_WORD / 2;
7081 bits = BITS_PER_WORD;
7083 mode = mode_for_size (bits, MODE_INT, 0);
7084 delta = bits / BITS_PER_UNIT;
7086 /* Allocate a buffer for the temporary registers. */
7087 regs = XALLOCAVEC (rtx, length / delta);
7089 /* Load as many BITS-sized chunks as possible. Use a normal load if
7090 the source has enough alignment, otherwise use left/right pairs. */
7091 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
7093 regs[i] = gen_reg_rtx (mode);
7094 if (MEM_ALIGN (src) >= bits)
7095 mips_emit_move (regs[i], adjust_address (src, mode, offset));
7098 rtx part = adjust_address (src, BLKmode, offset);
7099 set_mem_size (part, delta);
7100 if (!mips_expand_ext_as_unaligned_load (regs[i], part, bits, 0, 0))
7105 /* Copy the chunks to the destination. */
7106 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
7107 if (MEM_ALIGN (dest) >= bits)
7108 mips_emit_move (adjust_address (dest, mode, offset), regs[i]);
7111 rtx part = adjust_address (dest, BLKmode, offset);
7112 set_mem_size (part, delta);
7113 if (!mips_expand_ins_as_unaligned_store (part, regs[i], bits, 0))
7117 /* Mop up any left-over bytes. */
7118 if (offset < length)
7120 src = adjust_address (src, BLKmode, offset);
7121 dest = adjust_address (dest, BLKmode, offset);
7122 move_by_pieces (dest, src, length - offset,
7123 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
7127 /* Helper function for doing a loop-based block operation on memory
7128 reference MEM. Each iteration of the loop will operate on LENGTH
7131 Create a new base register for use within the loop and point it to
7132 the start of MEM. Create a new memory reference that uses this
7133 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
7136 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
7137 rtx *loop_reg, rtx *loop_mem)
7139 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
7141 /* Although the new mem does not refer to a known location,
7142 it does keep up to LENGTH bytes of alignment. */
7143 *loop_mem = change_address (mem, BLKmode, *loop_reg);
7144 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
7147 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
7148 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
7149 the memory regions do not overlap. */
7152 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length,
7153 HOST_WIDE_INT bytes_per_iter)
7155 rtx label, src_reg, dest_reg, final_src, test;
7156 HOST_WIDE_INT leftover;
7158 leftover = length % bytes_per_iter;
7161 /* Create registers and memory references for use within the loop. */
7162 mips_adjust_block_mem (src, bytes_per_iter, &src_reg, &src);
7163 mips_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest);
7165 /* Calculate the value that SRC_REG should have after the last iteration
7167 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
7170 /* Emit the start of the loop. */
7171 label = gen_label_rtx ();
7174 /* Emit the loop body. */
7175 mips_block_move_straight (dest, src, bytes_per_iter);
7177 /* Move on to the next block. */
7178 mips_emit_move (src_reg, plus_constant (Pmode, src_reg, bytes_per_iter));
7179 mips_emit_move (dest_reg, plus_constant (Pmode, dest_reg, bytes_per_iter));
7181 /* Emit the loop condition. */
7182 test = gen_rtx_NE (VOIDmode, src_reg, final_src);
7183 if (Pmode == DImode)
7184 emit_jump_insn (gen_cbranchdi4 (test, src_reg, final_src, label));
7186 emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label));
7188 /* Mop up any left-over bytes. */
7190 mips_block_move_straight (dest, src, leftover);
7193 /* Expand a movmemsi instruction, which copies LENGTH bytes from
7194 memory reference SRC to memory reference DEST. */
7197 mips_expand_block_move (rtx dest, rtx src, rtx length)
7199 if (CONST_INT_P (length))
7201 if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)
7203 mips_block_move_straight (dest, src, INTVAL (length));
7208 mips_block_move_loop (dest, src, INTVAL (length),
7209 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER);
7216 /* Expand a loop of synci insns for the address range [BEGIN, END). */
7219 mips_expand_synci_loop (rtx begin, rtx end)
7221 rtx inc, label, end_label, cmp_result, mask, length;
7223 /* Create end_label. */
7224 end_label = gen_label_rtx ();
7226 /* Check if begin equals end. */
7227 cmp_result = gen_rtx_EQ (VOIDmode, begin, end);
7228 emit_jump_insn (gen_condjump (cmp_result, end_label));
7230 /* Load INC with the cache line size (rdhwr INC,$1). */
7231 inc = gen_reg_rtx (Pmode);
7232 emit_insn (PMODE_INSN (gen_rdhwr_synci_step, (inc)));
7234 /* Check if inc is 0. */
7235 cmp_result = gen_rtx_EQ (VOIDmode, inc, const0_rtx);
7236 emit_jump_insn (gen_condjump (cmp_result, end_label));
7238 /* Calculate mask. */
7239 mask = mips_force_unary (Pmode, NEG, inc);
7241 /* Mask out begin by mask. */
7242 begin = mips_force_binary (Pmode, AND, begin, mask);
7244 /* Calculate length. */
7245 length = mips_force_binary (Pmode, MINUS, end, begin);
7247 /* Loop back to here. */
7248 label = gen_label_rtx ();
7251 emit_insn (gen_synci (begin));
7253 /* Update length. */
7254 mips_emit_binary (MINUS, length, length, inc);
7257 mips_emit_binary (PLUS, begin, begin, inc);
7259 /* Check if length is greater than 0. */
7260 cmp_result = gen_rtx_GT (VOIDmode, length, const0_rtx);
7261 emit_jump_insn (gen_condjump (cmp_result, label));
7263 emit_label (end_label);
7266 /* Expand a QI or HI mode atomic memory operation.
7268 GENERATOR contains a pointer to the gen_* function that generates
7269 the SI mode underlying atomic operation using masks that we
7272 RESULT is the return register for the operation. Its value is NULL
7275 MEM is the location of the atomic access.
7277 OLDVAL is the first operand for the operation.
7279 NEWVAL is the optional second operand for the operation. Its value
7280 is NULL if unused. */
7283 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator,
7284 rtx result, rtx mem, rtx oldval, rtx newval)
7286 rtx orig_addr, memsi_addr, memsi, shift, shiftsi, unshifted_mask;
7287 rtx unshifted_mask_reg, mask, inverted_mask, si_op;
7289 enum machine_mode mode;
7291 mode = GET_MODE (mem);
7293 /* Compute the address of the containing SImode value. */
7294 orig_addr = force_reg (Pmode, XEXP (mem, 0));
7295 memsi_addr = mips_force_binary (Pmode, AND, orig_addr,
7296 force_reg (Pmode, GEN_INT (-4)));
7298 /* Create a memory reference for it. */
7299 memsi = gen_rtx_MEM (SImode, memsi_addr);
7300 set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER);
7301 MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem);
7303 /* Work out the byte offset of the QImode or HImode value,
7304 counting from the least significant byte. */
7305 shift = mips_force_binary (Pmode, AND, orig_addr, GEN_INT (3));
7306 if (TARGET_BIG_ENDIAN)
7307 mips_emit_binary (XOR, shift, shift, GEN_INT (mode == QImode ? 3 : 2));
7309 /* Multiply by eight to convert the shift value from bytes to bits. */
7310 mips_emit_binary (ASHIFT, shift, shift, GEN_INT (3));
7312 /* Make the final shift an SImode value, so that it can be used in
7313 SImode operations. */
7314 shiftsi = force_reg (SImode, gen_lowpart (SImode, shift));
7316 /* Set MASK to an inclusive mask of the QImode or HImode value. */
7317 unshifted_mask = GEN_INT (GET_MODE_MASK (mode));
7318 unshifted_mask_reg = force_reg (SImode, unshifted_mask);
7319 mask = mips_force_binary (SImode, ASHIFT, unshifted_mask_reg, shiftsi);
7321 /* Compute the equivalent exclusive mask. */
7322 inverted_mask = gen_reg_rtx (SImode);
7323 emit_insn (gen_rtx_SET (VOIDmode, inverted_mask,
7324 gen_rtx_NOT (SImode, mask)));
7326 /* Shift the old value into place. */
7327 if (oldval != const0_rtx)
7329 oldval = convert_modes (SImode, mode, oldval, true);
7330 oldval = force_reg (SImode, oldval);
7331 oldval = mips_force_binary (SImode, ASHIFT, oldval, shiftsi);
7334 /* Do the same for the new value. */
7335 if (newval && newval != const0_rtx)
7337 newval = convert_modes (SImode, mode, newval, true);
7338 newval = force_reg (SImode, newval);
7339 newval = mips_force_binary (SImode, ASHIFT, newval, shiftsi);
7342 /* Do the SImode atomic access. */
7344 res = gen_reg_rtx (SImode);
7346 si_op = generator.fn_6 (res, memsi, mask, inverted_mask, oldval, newval);
7348 si_op = generator.fn_5 (res, memsi, mask, inverted_mask, oldval);
7350 si_op = generator.fn_4 (memsi, mask, inverted_mask, oldval);
7356 /* Shift and convert the result. */
7357 mips_emit_binary (AND, res, res, mask);
7358 mips_emit_binary (LSHIFTRT, res, res, shiftsi);
7359 mips_emit_move (result, gen_lowpart (GET_MODE (result), res));
7363 /* Return true if it is possible to use left/right accesses for a
7364 bitfield of WIDTH bits starting BITPOS bits into BLKmode memory OP.
7365 When returning true, update *LEFT and *RIGHT as follows:
7367 *LEFT is a QImode reference to the first byte if big endian or
7368 the last byte if little endian. This address can be used in the
7369 left-side instructions (LWL, SWL, LDL, SDL).
7371 *RIGHT is a QImode reference to the opposite end of the field and
7372 can be used in the patterning right-side instruction. */
7375 mips_get_unaligned_mem (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos,
7376 rtx *left, rtx *right)
7380 /* Check that the size is valid. */
7381 if (width != 32 && (!TARGET_64BIT || width != 64))
7384 /* We can only access byte-aligned values. Since we are always passed
7385 a reference to the first byte of the field, it is not necessary to
7386 do anything with BITPOS after this check. */
7387 if (bitpos % BITS_PER_UNIT != 0)
7390 /* Reject aligned bitfields: we want to use a normal load or store
7391 instead of a left/right pair. */
7392 if (MEM_ALIGN (op) >= width)
7395 /* Get references to both ends of the field. */
7396 first = adjust_address (op, QImode, 0);
7397 last = adjust_address (op, QImode, width / BITS_PER_UNIT - 1);
7399 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
7400 correspond to the MSB and RIGHT to the LSB. */
7401 if (TARGET_BIG_ENDIAN)
7402 *left = first, *right = last;
7404 *left = last, *right = first;
7409 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
7410 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
7411 the operation is the equivalent of:
7413 (set DEST (*_extract SRC WIDTH BITPOS))
7415 Return true on success. */
7418 mips_expand_ext_as_unaligned_load (rtx dest, rtx src, HOST_WIDE_INT width,
7419 HOST_WIDE_INT bitpos, bool unsigned_p)
7421 rtx left, right, temp;
7422 rtx dest1 = NULL_RTX;
7424 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
7425 be a DImode, create a new temp and emit a zero extend at the end. */
7426 if (GET_MODE (dest) == DImode
7428 && GET_MODE_BITSIZE (SImode) == width)
7431 dest = gen_reg_rtx (SImode);
7434 if (!mips_get_unaligned_mem (src, width, bitpos, &left, &right))
7437 temp = gen_reg_rtx (GET_MODE (dest));
7438 if (GET_MODE (dest) == DImode)
7440 emit_insn (gen_mov_ldl (temp, src, left));
7441 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
7445 emit_insn (gen_mov_lwl (temp, src, left));
7446 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
7449 /* If we were loading 32bits and the original register was DI then
7450 sign/zero extend into the orignal dest. */
7454 emit_insn (gen_zero_extendsidi2 (dest1, dest));
7456 emit_insn (gen_extendsidi2 (dest1, dest));
7461 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
7462 BITPOS and SRC are the operands passed to the expander; the operation
7463 is the equivalent of:
7465 (set (zero_extract DEST WIDTH BITPOS) SRC)
7467 Return true on success. */
7470 mips_expand_ins_as_unaligned_store (rtx dest, rtx src, HOST_WIDE_INT width,
7471 HOST_WIDE_INT bitpos)
7474 enum machine_mode mode;
7476 if (!mips_get_unaligned_mem (dest, width, bitpos, &left, &right))
7479 mode = mode_for_size (width, MODE_INT, 0);
7480 src = gen_lowpart (mode, src);
7483 emit_insn (gen_mov_sdl (dest, src, left));
7484 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
7488 emit_insn (gen_mov_swl (dest, src, left));
7489 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
7494 /* Return true if X is a MEM with the same size as MODE. */
7497 mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
7500 && MEM_SIZE_KNOWN_P (x)
7501 && MEM_SIZE (x) == GET_MODE_SIZE (mode));
7504 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
7505 source of an "ext" instruction or the destination of an "ins"
7506 instruction. OP must be a register operand and the following
7507 conditions must hold:
7509 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
7510 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7511 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7513 Also reject lengths equal to a word as they are better handled
7514 by the move patterns. */
7517 mips_use_ins_ext_p (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos)
7519 if (!ISA_HAS_EXT_INS
7520 || !register_operand (op, VOIDmode)
7521 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
7524 if (!IN_RANGE (width, 1, GET_MODE_BITSIZE (GET_MODE (op)) - 1))
7527 if (bitpos < 0 || bitpos + width > GET_MODE_BITSIZE (GET_MODE (op)))
7533 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
7534 operation if MAXLEN is the maxium length of consecutive bits that
7535 can make up MASK. MODE is the mode of the operation. See
7536 mask_low_and_shift_len for the actual definition. */
7539 mask_low_and_shift_p (enum machine_mode mode, rtx mask, rtx shift, int maxlen)
7541 return IN_RANGE (mask_low_and_shift_len (mode, mask, shift), 1, maxlen);
7544 /* Return true iff OP1 and OP2 are valid operands together for the
7545 *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider,
7546 see the table in the comment before the pattern. */
7549 and_operands_ok (enum machine_mode mode, rtx op1, rtx op2)
7551 return (memory_operand (op1, mode)
7552 ? and_load_operand (op2, mode)
7553 : and_reg_operand (op2, mode));
7556 /* The canonical form of a mask-low-and-shift-left operation is
7557 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
7558 cleared. Thus we need to shift MASK to the right before checking if it
7559 is a valid mask value. MODE is the mode of the operation. If true
7560 return the length of the mask, otherwise return -1. */
7563 mask_low_and_shift_len (enum machine_mode mode, rtx mask, rtx shift)
7565 HOST_WIDE_INT shval;
7567 shval = INTVAL (shift) & (GET_MODE_BITSIZE (mode) - 1);
7568 return exact_log2 ((UINTVAL (mask) >> shval) + 1);
7571 /* Return true if -msplit-addresses is selected and should be honored.
7573 -msplit-addresses is a half-way house between explicit relocations
7574 and the traditional assembler macros. It can split absolute 32-bit
7575 symbolic constants into a high/lo_sum pair but uses macros for other
7578 Like explicit relocation support for REL targets, it relies
7579 on GNU extensions in the assembler and the linker.
7581 Although this code should work for -O0, it has traditionally
7582 been treated as an optimization. */
7585 mips_split_addresses_p (void)
7587 return (TARGET_SPLIT_ADDRESSES
7591 && !ABI_HAS_64BIT_SYMBOLS);
7594 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
7597 mips_init_relocs (void)
7599 memset (mips_split_p, '\0', sizeof (mips_split_p));
7600 memset (mips_split_hi_p, '\0', sizeof (mips_split_hi_p));
7601 memset (mips_use_pcrel_pool_p, '\0', sizeof (mips_use_pcrel_pool_p));
7602 memset (mips_hi_relocs, '\0', sizeof (mips_hi_relocs));
7603 memset (mips_lo_relocs, '\0', sizeof (mips_lo_relocs));
7605 if (TARGET_MIPS16_PCREL_LOADS)
7606 mips_use_pcrel_pool_p[SYMBOL_ABSOLUTE] = true;
7609 if (ABI_HAS_64BIT_SYMBOLS)
7611 if (TARGET_EXPLICIT_RELOCS)
7613 mips_split_p[SYMBOL_64_HIGH] = true;
7614 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
7615 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
7617 mips_split_p[SYMBOL_64_MID] = true;
7618 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
7619 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
7621 mips_split_p[SYMBOL_64_LOW] = true;
7622 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
7623 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
7625 mips_split_p[SYMBOL_ABSOLUTE] = true;
7626 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
7631 if (TARGET_EXPLICIT_RELOCS
7632 || mips_split_addresses_p ()
7635 mips_split_p[SYMBOL_ABSOLUTE] = true;
7636 mips_hi_relocs[SYMBOL_ABSOLUTE] = "%hi(";
7637 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
7644 /* The high part is provided by a pseudo copy of $gp. */
7645 mips_split_p[SYMBOL_GP_RELATIVE] = true;
7646 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gprel(";
7648 else if (TARGET_EXPLICIT_RELOCS)
7649 /* Small data constants are kept whole until after reload,
7650 then lowered by mips_rewrite_small_data. */
7651 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gp_rel(";
7653 if (TARGET_EXPLICIT_RELOCS)
7655 mips_split_p[SYMBOL_GOT_PAGE_OFST] = true;
7658 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
7659 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%got_ofst(";
7663 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
7664 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%lo(";
7667 /* Expose the use of $28 as soon as possible. */
7668 mips_split_hi_p[SYMBOL_GOT_PAGE_OFST] = true;
7672 /* The HIGH and LO_SUM are matched by special .md patterns. */
7673 mips_split_p[SYMBOL_GOT_DISP] = true;
7675 mips_split_p[SYMBOL_GOTOFF_DISP] = true;
7676 mips_hi_relocs[SYMBOL_GOTOFF_DISP] = "%got_hi(";
7677 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_lo(";
7679 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
7680 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
7681 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
7686 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_disp(";
7688 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got(";
7689 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
7691 /* Expose the use of $28 as soon as possible. */
7692 mips_split_p[SYMBOL_GOT_DISP] = true;
7698 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
7699 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
7700 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
7703 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
7704 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
7706 if (TARGET_MIPS16_PCREL_LOADS)
7708 mips_use_pcrel_pool_p[SYMBOL_DTPREL] = true;
7709 mips_use_pcrel_pool_p[SYMBOL_TPREL] = true;
7713 mips_split_p[SYMBOL_DTPREL] = true;
7714 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
7715 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
7717 mips_split_p[SYMBOL_TPREL] = true;
7718 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
7719 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
7722 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
7723 mips_lo_relocs[SYMBOL_HALF] = "%half(";
7726 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
7727 in context CONTEXT. RELOCS is the array of relocations to use. */
7730 mips_print_operand_reloc (FILE *file, rtx op, enum mips_symbol_context context,
7731 const char **relocs)
7733 enum mips_symbol_type symbol_type;
7736 symbol_type = mips_classify_symbolic_expression (op, context);
7737 gcc_assert (relocs[symbol_type]);
7739 fputs (relocs[symbol_type], file);
7740 output_addr_const (file, mips_strip_unspec_address (op));
7741 for (p = relocs[symbol_type]; *p != 0; p++)
7746 /* Start a new block with the given asm switch enabled. If we need
7747 to print a directive, emit PREFIX before it and SUFFIX after it. */
7750 mips_push_asm_switch_1 (struct mips_asm_switch *asm_switch,
7751 const char *prefix, const char *suffix)
7753 if (asm_switch->nesting_level == 0)
7754 fprintf (asm_out_file, "%s.set\tno%s%s", prefix, asm_switch->name, suffix);
7755 asm_switch->nesting_level++;
7758 /* Likewise, but end a block. */
7761 mips_pop_asm_switch_1 (struct mips_asm_switch *asm_switch,
7762 const char *prefix, const char *suffix)
7764 gcc_assert (asm_switch->nesting_level);
7765 asm_switch->nesting_level--;
7766 if (asm_switch->nesting_level == 0)
7767 fprintf (asm_out_file, "%s.set\t%s%s", prefix, asm_switch->name, suffix);
7770 /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1
7771 that either print a complete line or print nothing. */
7774 mips_push_asm_switch (struct mips_asm_switch *asm_switch)
7776 mips_push_asm_switch_1 (asm_switch, "\t", "\n");
7780 mips_pop_asm_switch (struct mips_asm_switch *asm_switch)
7782 mips_pop_asm_switch_1 (asm_switch, "\t", "\n");
7785 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
7786 The punctuation characters are:
7788 '(' Start a nested ".set noreorder" block.
7789 ')' End a nested ".set noreorder" block.
7790 '[' Start a nested ".set noat" block.
7791 ']' End a nested ".set noat" block.
7792 '<' Start a nested ".set nomacro" block.
7793 '>' End a nested ".set nomacro" block.
7794 '*' Behave like %(%< if generating a delayed-branch sequence.
7795 '#' Print a nop if in a ".set noreorder" block.
7796 '/' Like '#', but do nothing within a delayed-branch sequence.
7797 '?' Print "l" if mips_branch_likely is true
7798 '~' Print a nop if mips_branch_likely is true
7799 '.' Print the name of the register with a hard-wired zero (zero or $0).
7800 '@' Print the name of the assembler temporary register (at or $1).
7801 '^' Print the name of the pic call-through register (t9 or $25).
7802 '+' Print the name of the gp register (usually gp or $28).
7803 '$' Print the name of the stack pointer register (sp or $29).
7805 See also mips_init_print_operand_pucnt. */
7808 mips_print_operand_punctuation (FILE *file, int ch)
7813 mips_push_asm_switch_1 (&mips_noreorder, "", "\n\t");
7817 mips_pop_asm_switch_1 (&mips_noreorder, "\n\t", "");
7821 mips_push_asm_switch_1 (&mips_noat, "", "\n\t");
7825 mips_pop_asm_switch_1 (&mips_noat, "\n\t", "");
7829 mips_push_asm_switch_1 (&mips_nomacro, "", "\n\t");
7833 mips_pop_asm_switch_1 (&mips_nomacro, "\n\t", "");
7837 if (final_sequence != 0)
7839 mips_print_operand_punctuation (file, '(');
7840 mips_print_operand_punctuation (file, '<');
7845 if (mips_noreorder.nesting_level > 0)
7846 fputs ("\n\tnop", file);
7850 /* Print an extra newline so that the delayed insn is separated
7851 from the following ones. This looks neater and is consistent
7852 with non-nop delayed sequences. */
7853 if (mips_noreorder.nesting_level > 0 && final_sequence == 0)
7854 fputs ("\n\tnop\n", file);
7858 if (mips_branch_likely)
7863 if (mips_branch_likely)
7864 fputs ("\n\tnop", file);
7868 fputs (reg_names[GP_REG_FIRST + 0], file);
7872 fputs (reg_names[AT_REGNUM], file);
7876 fputs (reg_names[PIC_FUNCTION_ADDR_REGNUM], file);
7880 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
7884 fputs (reg_names[STACK_POINTER_REGNUM], file);
7893 /* Initialize mips_print_operand_punct. */
7896 mips_init_print_operand_punct (void)
7900 for (p = "()[]<>*#/?~.@^+$"; *p; p++)
7901 mips_print_operand_punct[(unsigned char) *p] = true;
7904 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
7905 associated with condition CODE. Print the condition part of the
7909 mips_print_int_branch_condition (FILE *file, enum rtx_code code, int letter)
7923 /* Conveniently, the MIPS names for these conditions are the same
7924 as their RTL equivalents. */
7925 fputs (GET_RTX_NAME (code), file);
7929 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
7934 /* Likewise floating-point branches. */
7937 mips_print_float_branch_condition (FILE *file, enum rtx_code code, int letter)
7942 fputs ("c1f", file);
7946 fputs ("c1t", file);
7950 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
7955 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
7958 mips_print_operand_punct_valid_p (unsigned char code)
7960 return mips_print_operand_punct[code];
7963 /* Implement TARGET_PRINT_OPERAND. The MIPS-specific operand codes are:
7965 'X' Print CONST_INT OP in hexadecimal format.
7966 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
7967 'd' Print CONST_INT OP in decimal.
7968 'm' Print one less than CONST_INT OP in decimal.
7969 'h' Print the high-part relocation associated with OP, after stripping
7971 'R' Print the low-part relocation associated with OP.
7972 'C' Print the integer branch condition for comparison OP.
7973 'N' Print the inverse of the integer branch condition for comparison OP.
7974 'F' Print the FPU branch condition for comparison OP.
7975 'W' Print the inverse of the FPU branch condition for comparison OP.
7976 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
7977 'z' for (eq:?I ...), 'n' for (ne:?I ...).
7978 't' Like 'T', but with the EQ/NE cases reversed
7979 'Y' Print mips_fp_conditions[INTVAL (OP)]
7980 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
7981 'q' Print a DSP accumulator register.
7982 'D' Print the second part of a double-word register or memory operand.
7983 'L' Print the low-order register in a double-word register operand.
7984 'M' Print high-order register in a double-word register operand.
7985 'z' Print $0 if OP is zero, otherwise print OP normally.
7986 'b' Print the address of a memory operand, without offset. */
7989 mips_print_operand (FILE *file, rtx op, int letter)
7993 if (mips_print_operand_punct_valid_p (letter))
7995 mips_print_operand_punctuation (file, letter);
8000 code = GET_CODE (op);
8005 if (CONST_INT_P (op))
8006 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
8008 output_operand_lossage ("invalid use of '%%%c'", letter);
8012 if (CONST_INT_P (op))
8013 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op) & 0xffff);
8015 output_operand_lossage ("invalid use of '%%%c'", letter);
8019 if (CONST_INT_P (op))
8020 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op));
8022 output_operand_lossage ("invalid use of '%%%c'", letter);
8026 if (CONST_INT_P (op))
8027 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op) - 1);
8029 output_operand_lossage ("invalid use of '%%%c'", letter);
8035 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_hi_relocs);
8039 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_lo_relocs);
8043 mips_print_int_branch_condition (file, code, letter);
8047 mips_print_int_branch_condition (file, reverse_condition (code), letter);
8051 mips_print_float_branch_condition (file, code, letter);
8055 mips_print_float_branch_condition (file, reverse_condition (code),
8062 int truth = (code == NE) == (letter == 'T');
8063 fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
8068 if (code == CONST_INT && UINTVAL (op) < ARRAY_SIZE (mips_fp_conditions))
8069 fputs (mips_fp_conditions[UINTVAL (op)], file);
8071 output_operand_lossage ("'%%%c' is not a valid operand prefix",
8078 mips_print_operand (file, op, 0);
8084 if (code == REG && MD_REG_P (REGNO (op)))
8085 fprintf (file, "$ac0");
8086 else if (code == REG && DSP_ACC_REG_P (REGNO (op)))
8087 fprintf (file, "$ac%c", reg_names[REGNO (op)][3]);
8089 output_operand_lossage ("invalid use of '%%%c'", letter);
8097 unsigned int regno = REGNO (op);
8098 if ((letter == 'M' && TARGET_LITTLE_ENDIAN)
8099 || (letter == 'L' && TARGET_BIG_ENDIAN)
8102 else if (letter && letter != 'z' && letter != 'M' && letter != 'L')
8103 output_operand_lossage ("invalid use of '%%%c'", letter);
8104 /* We need to print $0 .. $31 for COP0 registers. */
8105 if (COP0_REG_P (regno))
8106 fprintf (file, "$%s", ®_names[regno][4]);
8108 fprintf (file, "%s", reg_names[regno]);
8114 output_address (plus_constant (Pmode, XEXP (op, 0), 4));
8115 else if (letter == 'b')
8117 gcc_assert (REG_P (XEXP (op, 0)));
8118 mips_print_operand (file, XEXP (op, 0), 0);
8120 else if (letter && letter != 'z')
8121 output_operand_lossage ("invalid use of '%%%c'", letter);
8123 output_address (XEXP (op, 0));
8127 if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
8128 fputs (reg_names[GP_REG_FIRST], file);
8129 else if (letter && letter != 'z')
8130 output_operand_lossage ("invalid use of '%%%c'", letter);
8131 else if (CONST_GP_P (op))
8132 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
8134 output_addr_const (file, mips_strip_unspec_address (op));
8140 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
8143 mips_print_operand_address (FILE *file, rtx x)
8145 struct mips_address_info addr;
8147 if (mips_classify_address (&addr, x, word_mode, true))
8151 mips_print_operand (file, addr.offset, 0);
8152 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
8155 case ADDRESS_LO_SUM:
8156 mips_print_operand_reloc (file, addr.offset, SYMBOL_CONTEXT_MEM,
8158 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
8161 case ADDRESS_CONST_INT:
8162 output_addr_const (file, x);
8163 fprintf (file, "(%s)", reg_names[GP_REG_FIRST]);
8166 case ADDRESS_SYMBOLIC:
8167 output_addr_const (file, mips_strip_unspec_address (x));
8173 /* Implement TARGET_ENCODE_SECTION_INFO. */
8176 mips_encode_section_info (tree decl, rtx rtl, int first)
8178 default_encode_section_info (decl, rtl, first);
8180 if (TREE_CODE (decl) == FUNCTION_DECL)
8182 rtx symbol = XEXP (rtl, 0);
8183 tree type = TREE_TYPE (decl);
8185 /* Encode whether the symbol is short or long. */
8186 if ((TARGET_LONG_CALLS && !mips_near_type_p (type))
8187 || mips_far_type_p (type))
8188 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
8192 /* Implement TARGET_SELECT_RTX_SECTION. */
8195 mips_select_rtx_section (enum machine_mode mode, rtx x,
8196 unsigned HOST_WIDE_INT align)
8198 /* ??? Consider using mergeable small data sections. */
8199 if (mips_rtx_constant_in_small_data_p (mode))
8200 return get_named_section (NULL, ".sdata", 0);
8202 return default_elf_select_rtx_section (mode, x, align);
8205 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
8207 The complication here is that, with the combination TARGET_ABICALLS
8208 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
8209 absolute addresses, and should therefore not be included in the
8210 read-only part of a DSO. Handle such cases by selecting a normal
8211 data section instead of a read-only one. The logic apes that in
8212 default_function_rodata_section. */
8215 mips_function_rodata_section (tree decl)
8217 if (!TARGET_ABICALLS || TARGET_ABSOLUTE_ABICALLS || TARGET_GPWORD)
8218 return default_function_rodata_section (decl);
8220 if (decl && DECL_SECTION_NAME (decl))
8222 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
8223 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
8225 char *rname = ASTRDUP (name);
8227 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
8229 else if (flag_function_sections
8230 && flag_data_sections
8231 && strncmp (name, ".text.", 6) == 0)
8233 char *rname = ASTRDUP (name);
8234 memcpy (rname + 1, "data", 4);
8235 return get_section (rname, SECTION_WRITE, decl);
8238 return data_section;
8241 /* Implement TARGET_IN_SMALL_DATA_P. */
8244 mips_in_small_data_p (const_tree decl)
8246 unsigned HOST_WIDE_INT size;
8248 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
8251 /* We don't yet generate small-data references for -mabicalls
8252 or VxWorks RTP code. See the related -G handling in
8253 mips_option_override. */
8254 if (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
8257 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
8261 /* Reject anything that isn't in a known small-data section. */
8262 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
8263 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
8266 /* If a symbol is defined externally, the assembler will use the
8267 usual -G rules when deciding how to implement macros. */
8268 if (mips_lo_relocs[SYMBOL_GP_RELATIVE] || !DECL_EXTERNAL (decl))
8271 else if (TARGET_EMBEDDED_DATA)
8273 /* Don't put constants into the small data section: we want them
8274 to be in ROM rather than RAM. */
8275 if (TREE_CODE (decl) != VAR_DECL)
8278 if (TREE_READONLY (decl)
8279 && !TREE_SIDE_EFFECTS (decl)
8280 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
8284 /* Enforce -mlocal-sdata. */
8285 if (!TARGET_LOCAL_SDATA && !TREE_PUBLIC (decl))
8288 /* Enforce -mextern-sdata. */
8289 if (!TARGET_EXTERN_SDATA && DECL_P (decl))
8291 if (DECL_EXTERNAL (decl))
8293 if (DECL_COMMON (decl) && DECL_INITIAL (decl) == NULL)
8297 /* We have traditionally not treated zero-sized objects as small data,
8298 so this is now effectively part of the ABI. */
8299 size = int_size_in_bytes (TREE_TYPE (decl));
8300 return size > 0 && size <= mips_small_data_threshold;
8303 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
8304 anchors for small data: the GP register acts as an anchor in that
8305 case. We also don't want to use them for PC-relative accesses,
8306 where the PC acts as an anchor. */
8309 mips_use_anchors_for_symbol_p (const_rtx symbol)
8311 switch (mips_classify_symbol (symbol, SYMBOL_CONTEXT_MEM))
8313 case SYMBOL_PC_RELATIVE:
8314 case SYMBOL_GP_RELATIVE:
8318 return default_use_anchors_for_symbol_p (symbol);
8322 /* The MIPS debug format wants all automatic variables and arguments
8323 to be in terms of the virtual frame pointer (stack pointer before
8324 any adjustment in the function), while the MIPS 3.0 linker wants
8325 the frame pointer to be the stack pointer after the initial
8326 adjustment. So, we do the adjustment here. The arg pointer (which
8327 is eliminated) points to the virtual frame pointer, while the frame
8328 pointer (which may be eliminated) points to the stack pointer after
8329 the initial adjustments. */
8332 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
8334 rtx offset2 = const0_rtx;
8335 rtx reg = eliminate_constant_term (addr, &offset2);
8338 offset = INTVAL (offset2);
8340 if (reg == stack_pointer_rtx
8341 || reg == frame_pointer_rtx
8342 || reg == hard_frame_pointer_rtx)
8344 offset -= cfun->machine->frame.total_size;
8345 if (reg == hard_frame_pointer_rtx)
8346 offset += cfun->machine->frame.hard_frame_pointer_offset;
8352 /* Implement ASM_OUTPUT_EXTERNAL. */
8355 mips_output_external (FILE *file, tree decl, const char *name)
8357 default_elf_asm_output_external (file, decl, name);
8359 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
8360 set in order to avoid putting out names that are never really
8362 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
8364 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
8366 /* When using assembler macros, emit .extern directives for
8367 all small-data externs so that the assembler knows how
8370 In most cases it would be safe (though pointless) to emit
8371 .externs for other symbols too. One exception is when an
8372 object is within the -G limit but declared by the user to
8373 be in a section other than .sbss or .sdata. */
8374 fputs ("\t.extern\t", file);
8375 assemble_name (file, name);
8376 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n",
8377 int_size_in_bytes (TREE_TYPE (decl)));
8382 /* Implement TARGET_ASM_OUTPUT_SOURCE_FILENAME. */
8385 mips_output_filename (FILE *stream, const char *name)
8387 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
8389 if (write_symbols == DWARF2_DEBUG)
8391 else if (mips_output_filename_first_time)
8393 mips_output_filename_first_time = 0;
8394 num_source_filenames += 1;
8395 current_function_file = name;
8396 fprintf (stream, "\t.file\t%d ", num_source_filenames);
8397 output_quoted_string (stream, name);
8398 putc ('\n', stream);
8400 /* If we are emitting stabs, let dbxout.c handle this (except for
8401 the mips_output_filename_first_time case). */
8402 else if (write_symbols == DBX_DEBUG)
8404 else if (name != current_function_file
8405 && strcmp (name, current_function_file) != 0)
8407 num_source_filenames += 1;
8408 current_function_file = name;
8409 fprintf (stream, "\t.file\t%d ", num_source_filenames);
8410 output_quoted_string (stream, name);
8411 putc ('\n', stream);
8415 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
8417 static void ATTRIBUTE_UNUSED
8418 mips_output_dwarf_dtprel (FILE *file, int size, rtx x)
8423 fputs ("\t.dtprelword\t", file);
8427 fputs ("\t.dtpreldword\t", file);
8433 output_addr_const (file, x);
8434 fputs ("+0x8000", file);
8437 /* Implement TARGET_DWARF_REGISTER_SPAN. */
8440 mips_dwarf_register_span (rtx reg)
8443 enum machine_mode mode;
8445 /* By default, GCC maps increasing register numbers to increasing
8446 memory locations, but paired FPRs are always little-endian,
8447 regardless of the prevailing endianness. */
8448 mode = GET_MODE (reg);
8449 if (FP_REG_P (REGNO (reg))
8450 && TARGET_BIG_ENDIAN
8451 && MAX_FPRS_PER_FMT > 1
8452 && GET_MODE_SIZE (mode) > UNITS_PER_FPREG)
8454 gcc_assert (GET_MODE_SIZE (mode) == UNITS_PER_HWFPVALUE);
8455 high = mips_subword (reg, true);
8456 low = mips_subword (reg, false);
8457 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, high, low));
8463 /* DSP ALU can bypass data with no delays for the following pairs. */
8464 enum insn_code dspalu_bypass_table[][2] =
8466 {CODE_FOR_mips_addsc, CODE_FOR_mips_addwc},
8467 {CODE_FOR_mips_cmpu_eq_qb, CODE_FOR_mips_pick_qb},
8468 {CODE_FOR_mips_cmpu_lt_qb, CODE_FOR_mips_pick_qb},
8469 {CODE_FOR_mips_cmpu_le_qb, CODE_FOR_mips_pick_qb},
8470 {CODE_FOR_mips_cmp_eq_ph, CODE_FOR_mips_pick_ph},
8471 {CODE_FOR_mips_cmp_lt_ph, CODE_FOR_mips_pick_ph},
8472 {CODE_FOR_mips_cmp_le_ph, CODE_FOR_mips_pick_ph},
8473 {CODE_FOR_mips_wrdsp, CODE_FOR_mips_insv}
8477 mips_dspalu_bypass_p (rtx out_insn, rtx in_insn)
8480 int num_bypass = ARRAY_SIZE (dspalu_bypass_table);
8481 enum insn_code out_icode = (enum insn_code) INSN_CODE (out_insn);
8482 enum insn_code in_icode = (enum insn_code) INSN_CODE (in_insn);
8484 for (i = 0; i < num_bypass; i++)
8486 if (out_icode == dspalu_bypass_table[i][0]
8487 && in_icode == dspalu_bypass_table[i][1])
8493 /* Implement ASM_OUTPUT_ASCII. */
8496 mips_output_ascii (FILE *stream, const char *string, size_t len)
8502 fprintf (stream, "\t.ascii\t\"");
8503 for (i = 0; i < len; i++)
8507 c = (unsigned char) string[i];
8510 if (c == '\\' || c == '\"')
8512 putc ('\\', stream);
8520 fprintf (stream, "\\%03o", c);
8524 if (cur_pos > 72 && i+1 < len)
8527 fprintf (stream, "\"\n\t.ascii\t\"");
8530 fprintf (stream, "\"\n");
8533 /* Return the pseudo-op for full SYMBOL_(D)TPREL address *ADDR.
8534 Update *ADDR with the operand that should be printed. */
8537 mips_output_tls_reloc_directive (rtx *addr)
8539 enum mips_symbol_type type;
8541 type = mips_classify_symbolic_expression (*addr, SYMBOL_CONTEXT_LEA);
8542 *addr = mips_strip_unspec_address (*addr);
8546 return Pmode == SImode ? ".dtprelword\t%0" : ".dtpreldword\t%0";
8549 return Pmode == SImode ? ".tprelword\t%0" : ".tpreldword\t%0";
8556 /* Emit either a label, .comm, or .lcomm directive. When using assembler
8557 macros, mark the symbol as written so that mips_asm_output_external
8558 won't emit an .extern for it. STREAM is the output file, NAME is the
8559 name of the symbol, INIT_STRING is the string that should be written
8560 before the symbol and FINAL_STRING is the string that should be
8561 written after it. FINAL_STRING is a printf format that consumes the
8562 remaining arguments. */
8565 mips_declare_object (FILE *stream, const char *name, const char *init_string,
8566 const char *final_string, ...)
8570 fputs (init_string, stream);
8571 assemble_name (stream, name);
8572 va_start (ap, final_string);
8573 vfprintf (stream, final_string, ap);
8576 if (!TARGET_EXPLICIT_RELOCS)
8578 tree name_tree = get_identifier (name);
8579 TREE_ASM_WRITTEN (name_tree) = 1;
8583 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
8584 NAME is the name of the object and ALIGN is the required alignment
8585 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
8586 alignment argument. */
8589 mips_declare_common_object (FILE *stream, const char *name,
8590 const char *init_string,
8591 unsigned HOST_WIDE_INT size,
8592 unsigned int align, bool takes_alignment_p)
8594 if (!takes_alignment_p)
8596 size += (align / BITS_PER_UNIT) - 1;
8597 size -= size % (align / BITS_PER_UNIT);
8598 mips_declare_object (stream, name, init_string,
8599 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
8602 mips_declare_object (stream, name, init_string,
8603 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
8604 size, align / BITS_PER_UNIT);
8607 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
8608 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
8611 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
8612 unsigned HOST_WIDE_INT size,
8615 /* If the target wants uninitialized const declarations in
8616 .rdata then don't put them in .comm. */
8617 if (TARGET_EMBEDDED_DATA
8618 && TARGET_UNINIT_CONST_IN_RODATA
8619 && TREE_CODE (decl) == VAR_DECL
8620 && TREE_READONLY (decl)
8621 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
8623 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
8624 targetm.asm_out.globalize_label (stream, name);
8626 switch_to_section (readonly_data_section);
8627 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
8628 mips_declare_object (stream, name, "",
8629 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
8633 mips_declare_common_object (stream, name, "\n\t.comm\t",
8637 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8638 extern int size_directive_output;
8640 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
8641 definitions except that it uses mips_declare_object to emit the label. */
8644 mips_declare_object_name (FILE *stream, const char *name,
8645 tree decl ATTRIBUTE_UNUSED)
8647 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8648 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
8651 size_directive_output = 0;
8652 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
8656 size_directive_output = 1;
8657 size = int_size_in_bytes (TREE_TYPE (decl));
8658 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8661 mips_declare_object (stream, name, "", ":\n");
8664 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
8667 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
8671 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
8672 if (!flag_inhibit_size_directive
8673 && DECL_SIZE (decl) != 0
8676 && DECL_INITIAL (decl) == error_mark_node
8677 && !size_directive_output)
8681 size_directive_output = 1;
8682 size = int_size_in_bytes (TREE_TYPE (decl));
8683 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8688 /* Return the FOO in the name of the ".mdebug.FOO" section associated
8689 with the current ABI. */
8692 mips_mdebug_abi_name (void)
8705 return TARGET_64BIT ? "eabi64" : "eabi32";
8711 /* Implement TARGET_ASM_FILE_START. */
8714 mips_file_start (void)
8716 default_file_start ();
8718 /* Generate a special section to describe the ABI switches used to
8719 produce the resultant binary. */
8721 /* Record the ABI itself. Modern versions of binutils encode
8722 this information in the ELF header flags, but GDB needs the
8723 information in order to correctly debug binaries produced by
8724 older binutils. See the function mips_gdbarch_init in
8726 fprintf (asm_out_file, "\t.section .mdebug.%s\n\t.previous\n",
8727 mips_mdebug_abi_name ());
8729 /* There is no ELF header flag to distinguish long32 forms of the
8730 EABI from long64 forms. Emit a special section to help tools
8731 such as GDB. Do the same for o64, which is sometimes used with
8733 if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
8734 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n"
8735 "\t.previous\n", TARGET_LONG64 ? 64 : 32);
8737 #ifdef HAVE_AS_GNU_ATTRIBUTE
8741 /* No floating-point operations, -mno-float. */
8742 if (TARGET_NO_FLOAT)
8744 /* Soft-float code, -msoft-float. */
8745 else if (!TARGET_HARD_FLOAT_ABI)
8747 /* Single-float code, -msingle-float. */
8748 else if (!TARGET_DOUBLE_FLOAT)
8750 /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64. */
8751 else if (!TARGET_64BIT && TARGET_FLOAT64)
8753 /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */
8757 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n", attr);
8761 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
8762 if (TARGET_ABICALLS)
8764 fprintf (asm_out_file, "\t.abicalls\n");
8765 if (TARGET_ABICALLS_PIC0)
8766 fprintf (asm_out_file, "\t.option\tpic0\n");
8769 if (flag_verbose_asm)
8770 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
8772 mips_small_data_threshold, mips_arch_info->name, mips_isa);
8775 /* Implement TARGET_ASM_CODE_END. */
8778 mips_code_end (void)
8780 if (mips_need_mips16_rdhwr_p)
8781 mips_output_mips16_rdhwr ();
8784 /* Make the last instruction frame-related and note that it performs
8785 the operation described by FRAME_PATTERN. */
8788 mips_set_frame_expr (rtx frame_pattern)
8792 insn = get_last_insn ();
8793 RTX_FRAME_RELATED_P (insn) = 1;
8794 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
8799 /* Return a frame-related rtx that stores REG at MEM.
8800 REG must be a single register. */
8803 mips_frame_set (rtx mem, rtx reg)
8807 set = gen_rtx_SET (VOIDmode, mem, reg);
8808 RTX_FRAME_RELATED_P (set) = 1;
8813 /* Record that the epilogue has restored call-saved register REG. */
8816 mips_add_cfa_restore (rtx reg)
8818 mips_epilogue.cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg,
8819 mips_epilogue.cfa_restores);
8822 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
8823 mips16e_s2_s8_regs[X], it must also save the registers in indexes
8824 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
8825 static const unsigned char mips16e_s2_s8_regs[] = {
8826 30, 23, 22, 21, 20, 19, 18
8828 static const unsigned char mips16e_a0_a3_regs[] = {
8832 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
8833 ordered from the uppermost in memory to the lowest in memory. */
8834 static const unsigned char mips16e_save_restore_regs[] = {
8835 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
8838 /* Return the index of the lowest X in the range [0, SIZE) for which
8839 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
8842 mips16e_find_first_register (unsigned int mask, const unsigned char *regs,
8847 for (i = 0; i < size; i++)
8848 if (BITSET_P (mask, regs[i]))
8854 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
8855 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
8856 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
8857 is true for all indexes (X, SIZE). */
8860 mips16e_mask_registers (unsigned int *mask_ptr, const unsigned char *regs,
8861 unsigned int size, unsigned int *num_regs_ptr)
8865 i = mips16e_find_first_register (*mask_ptr, regs, size);
8866 for (i++; i < size; i++)
8867 if (!BITSET_P (*mask_ptr, regs[i]))
8870 *mask_ptr |= 1 << regs[i];
8874 /* Return a simplified form of X using the register values in REG_VALUES.
8875 REG_VALUES[R] is the last value assigned to hard register R, or null
8876 if R has not been modified.
8878 This function is rather limited, but is good enough for our purposes. */
8881 mips16e_collect_propagate_value (rtx x, rtx *reg_values)
8883 x = avoid_constant_pool_reference (x);
8887 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
8888 return simplify_gen_unary (GET_CODE (x), GET_MODE (x),
8889 x0, GET_MODE (XEXP (x, 0)));
8892 if (ARITHMETIC_P (x))
8894 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
8895 rtx x1 = mips16e_collect_propagate_value (XEXP (x, 1), reg_values);
8896 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), x0, x1);
8900 && reg_values[REGNO (x)]
8901 && !rtx_unstable_p (reg_values[REGNO (x)]))
8902 return reg_values[REGNO (x)];
8907 /* Return true if (set DEST SRC) stores an argument register into its
8908 caller-allocated save slot, storing the number of that argument
8909 register in *REGNO_PTR if so. REG_VALUES is as for
8910 mips16e_collect_propagate_value. */
8913 mips16e_collect_argument_save_p (rtx dest, rtx src, rtx *reg_values,
8914 unsigned int *regno_ptr)
8916 unsigned int argno, regno;
8917 HOST_WIDE_INT offset, required_offset;
8920 /* Check that this is a word-mode store. */
8921 if (!MEM_P (dest) || !REG_P (src) || GET_MODE (dest) != word_mode)
8924 /* Check that the register being saved is an unmodified argument
8926 regno = REGNO (src);
8927 if (!IN_RANGE (regno, GP_ARG_FIRST, GP_ARG_LAST) || reg_values[regno])
8929 argno = regno - GP_ARG_FIRST;
8931 /* Check whether the address is an appropriate stack-pointer or
8932 frame-pointer access. */
8933 addr = mips16e_collect_propagate_value (XEXP (dest, 0), reg_values);
8934 mips_split_plus (addr, &base, &offset);
8935 required_offset = cfun->machine->frame.total_size + argno * UNITS_PER_WORD;
8936 if (base == hard_frame_pointer_rtx)
8937 required_offset -= cfun->machine->frame.hard_frame_pointer_offset;
8938 else if (base != stack_pointer_rtx)
8940 if (offset != required_offset)
8947 /* A subroutine of mips_expand_prologue, called only when generating
8948 MIPS16e SAVE instructions. Search the start of the function for any
8949 instructions that save argument registers into their caller-allocated
8950 save slots. Delete such instructions and return a value N such that
8951 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
8952 instructions redundant. */
8955 mips16e_collect_argument_saves (void)
8957 rtx reg_values[FIRST_PSEUDO_REGISTER];
8958 rtx insn, next, set, dest, src;
8959 unsigned int nargs, regno;
8961 push_topmost_sequence ();
8963 memset (reg_values, 0, sizeof (reg_values));
8964 for (insn = get_insns (); insn; insn = next)
8966 next = NEXT_INSN (insn);
8967 if (NOTE_P (insn) || DEBUG_INSN_P (insn))
8973 set = PATTERN (insn);
8974 if (GET_CODE (set) != SET)
8977 dest = SET_DEST (set);
8978 src = SET_SRC (set);
8979 if (mips16e_collect_argument_save_p (dest, src, reg_values, ®no))
8981 if (!BITSET_P (cfun->machine->frame.mask, regno))
8984 nargs = MAX (nargs, (regno - GP_ARG_FIRST) + 1);
8987 else if (REG_P (dest) && GET_MODE (dest) == word_mode)
8988 reg_values[REGNO (dest)]
8989 = mips16e_collect_propagate_value (src, reg_values);
8993 pop_topmost_sequence ();
8998 /* Return a move between register REGNO and memory location SP + OFFSET.
8999 REG_PARM_P is true if SP + OFFSET belongs to REG_PARM_STACK_SPACE.
9000 Make the move a load if RESTORE_P, otherwise make it a store. */
9003 mips16e_save_restore_reg (bool restore_p, bool reg_parm_p,
9004 HOST_WIDE_INT offset, unsigned int regno)
9008 mem = gen_frame_mem (SImode, plus_constant (Pmode, stack_pointer_rtx,
9010 reg = gen_rtx_REG (SImode, regno);
9013 mips_add_cfa_restore (reg);
9014 return gen_rtx_SET (VOIDmode, reg, mem);
9017 return gen_rtx_SET (VOIDmode, mem, reg);
9018 return mips_frame_set (mem, reg);
9021 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
9022 The instruction must:
9024 - Allocate or deallocate SIZE bytes in total; SIZE is known
9027 - Save or restore as many registers in *MASK_PTR as possible.
9028 The instruction saves the first registers at the top of the
9029 allocated area, with the other registers below it.
9031 - Save NARGS argument registers above the allocated area.
9033 (NARGS is always zero if RESTORE_P.)
9035 The SAVE and RESTORE instructions cannot save and restore all general
9036 registers, so there may be some registers left over for the caller to
9037 handle. Destructively modify *MASK_PTR so that it contains the registers
9038 that still need to be saved or restored. The caller can save these
9039 registers in the memory immediately below *OFFSET_PTR, which is a
9040 byte offset from the bottom of the allocated stack area. */
9043 mips16e_build_save_restore (bool restore_p, unsigned int *mask_ptr,
9044 HOST_WIDE_INT *offset_ptr, unsigned int nargs,
9048 HOST_WIDE_INT offset, top_offset;
9049 unsigned int i, regno;
9052 gcc_assert (cfun->machine->frame.num_fp == 0);
9054 /* Calculate the number of elements in the PARALLEL. We need one element
9055 for the stack adjustment, one for each argument register save, and one
9056 for each additional register move. */
9058 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
9059 if (BITSET_P (*mask_ptr, mips16e_save_restore_regs[i]))
9062 /* Create the final PARALLEL. */
9063 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (n));
9066 /* Add the stack pointer adjustment. */
9067 set = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
9068 plus_constant (Pmode, stack_pointer_rtx,
9069 restore_p ? size : -size));
9070 RTX_FRAME_RELATED_P (set) = 1;
9071 XVECEXP (pattern, 0, n++) = set;
9073 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
9074 top_offset = restore_p ? size : 0;
9076 /* Save the arguments. */
9077 for (i = 0; i < nargs; i++)
9079 offset = top_offset + i * UNITS_PER_WORD;
9080 set = mips16e_save_restore_reg (restore_p, true, offset,
9082 XVECEXP (pattern, 0, n++) = set;
9085 /* Then fill in the other register moves. */
9086 offset = top_offset;
9087 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
9089 regno = mips16e_save_restore_regs[i];
9090 if (BITSET_P (*mask_ptr, regno))
9092 offset -= UNITS_PER_WORD;
9093 set = mips16e_save_restore_reg (restore_p, false, offset, regno);
9094 XVECEXP (pattern, 0, n++) = set;
9095 *mask_ptr &= ~(1 << regno);
9099 /* Tell the caller what offset it should use for the remaining registers. */
9100 *offset_ptr = size + (offset - top_offset);
9102 gcc_assert (n == XVECLEN (pattern, 0));
9107 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
9108 pointer. Return true if PATTERN matches the kind of instruction
9109 generated by mips16e_build_save_restore. If INFO is nonnull,
9110 initialize it when returning true. */
9113 mips16e_save_restore_pattern_p (rtx pattern, HOST_WIDE_INT adjust,
9114 struct mips16e_save_restore_info *info)
9116 unsigned int i, nargs, mask, extra;
9117 HOST_WIDE_INT top_offset, save_offset, offset;
9118 rtx set, reg, mem, base;
9121 if (!GENERATE_MIPS16E_SAVE_RESTORE)
9124 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
9125 top_offset = adjust > 0 ? adjust : 0;
9127 /* Interpret all other members of the PARALLEL. */
9128 save_offset = top_offset - UNITS_PER_WORD;
9132 for (n = 1; n < XVECLEN (pattern, 0); n++)
9134 /* Check that we have a SET. */
9135 set = XVECEXP (pattern, 0, n);
9136 if (GET_CODE (set) != SET)
9139 /* Check that the SET is a load (if restoring) or a store
9141 mem = adjust > 0 ? SET_SRC (set) : SET_DEST (set);
9145 /* Check that the address is the sum of the stack pointer and a
9146 possibly-zero constant offset. */
9147 mips_split_plus (XEXP (mem, 0), &base, &offset);
9148 if (base != stack_pointer_rtx)
9151 /* Check that SET's other operand is a register. */
9152 reg = adjust > 0 ? SET_DEST (set) : SET_SRC (set);
9156 /* Check for argument saves. */
9157 if (offset == top_offset + nargs * UNITS_PER_WORD
9158 && REGNO (reg) == GP_ARG_FIRST + nargs)
9160 else if (offset == save_offset)
9162 while (mips16e_save_restore_regs[i++] != REGNO (reg))
9163 if (i == ARRAY_SIZE (mips16e_save_restore_regs))
9166 mask |= 1 << REGNO (reg);
9167 save_offset -= UNITS_PER_WORD;
9173 /* Check that the restrictions on register ranges are met. */
9175 mips16e_mask_registers (&mask, mips16e_s2_s8_regs,
9176 ARRAY_SIZE (mips16e_s2_s8_regs), &extra);
9177 mips16e_mask_registers (&mask, mips16e_a0_a3_regs,
9178 ARRAY_SIZE (mips16e_a0_a3_regs), &extra);
9182 /* Make sure that the topmost argument register is not saved twice.
9183 The checks above ensure that the same is then true for the other
9184 argument registers. */
9185 if (nargs > 0 && BITSET_P (mask, GP_ARG_FIRST + nargs - 1))
9188 /* Pass back information, if requested. */
9191 info->nargs = nargs;
9193 info->size = (adjust > 0 ? adjust : -adjust);
9199 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
9200 for the register range [MIN_REG, MAX_REG]. Return a pointer to
9201 the null terminator. */
9204 mips16e_add_register_range (char *s, unsigned int min_reg,
9205 unsigned int max_reg)
9207 if (min_reg != max_reg)
9208 s += sprintf (s, ",%s-%s", reg_names[min_reg], reg_names[max_reg]);
9210 s += sprintf (s, ",%s", reg_names[min_reg]);
9214 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
9215 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
9218 mips16e_output_save_restore (rtx pattern, HOST_WIDE_INT adjust)
9220 static char buffer[300];
9222 struct mips16e_save_restore_info info;
9223 unsigned int i, end;
9226 /* Parse the pattern. */
9227 if (!mips16e_save_restore_pattern_p (pattern, adjust, &info))
9230 /* Add the mnemonic. */
9231 s = strcpy (buffer, adjust > 0 ? "restore\t" : "save\t");
9234 /* Save the arguments. */
9236 s += sprintf (s, "%s-%s,", reg_names[GP_ARG_FIRST],
9237 reg_names[GP_ARG_FIRST + info.nargs - 1]);
9238 else if (info.nargs == 1)
9239 s += sprintf (s, "%s,", reg_names[GP_ARG_FIRST]);
9241 /* Emit the amount of stack space to allocate or deallocate. */
9242 s += sprintf (s, "%d", (int) info.size);
9244 /* Save or restore $16. */
9245 if (BITSET_P (info.mask, 16))
9246 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 16]);
9248 /* Save or restore $17. */
9249 if (BITSET_P (info.mask, 17))
9250 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 17]);
9252 /* Save or restore registers in the range $s2...$s8, which
9253 mips16e_s2_s8_regs lists in decreasing order. Note that this
9254 is a software register range; the hardware registers are not
9255 numbered consecutively. */
9256 end = ARRAY_SIZE (mips16e_s2_s8_regs);
9257 i = mips16e_find_first_register (info.mask, mips16e_s2_s8_regs, end);
9259 s = mips16e_add_register_range (s, mips16e_s2_s8_regs[end - 1],
9260 mips16e_s2_s8_regs[i]);
9262 /* Save or restore registers in the range $a0...$a3. */
9263 end = ARRAY_SIZE (mips16e_a0_a3_regs);
9264 i = mips16e_find_first_register (info.mask, mips16e_a0_a3_regs, end);
9266 s = mips16e_add_register_range (s, mips16e_a0_a3_regs[i],
9267 mips16e_a0_a3_regs[end - 1]);
9269 /* Save or restore $31. */
9270 if (BITSET_P (info.mask, RETURN_ADDR_REGNUM))
9271 s += sprintf (s, ",%s", reg_names[RETURN_ADDR_REGNUM]);
9276 /* Return true if the current function returns its value in a floating-point
9277 register in MIPS16 mode. */
9280 mips16_cfun_returns_in_fpr_p (void)
9282 tree return_type = DECL_RESULT (current_function_decl);
9283 return (TARGET_MIPS16
9284 && TARGET_HARD_FLOAT_ABI
9285 && !aggregate_value_p (return_type, current_function_decl)
9286 && mips_return_mode_in_fpr_p (DECL_MODE (return_type)));
9289 /* Return true if predicate PRED is true for at least one instruction.
9290 Cache the result in *CACHE, and assume that the result is true
9291 if *CACHE is already true. */
9294 mips_find_gp_ref (bool *cache, bool (*pred) (rtx))
9300 push_topmost_sequence ();
9301 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9302 if (USEFUL_INSN_P (insn) && pred (insn))
9307 pop_topmost_sequence ();
9312 /* Return true if INSN refers to the global pointer in an "inflexible" way.
9313 See mips_cfun_has_inflexible_gp_ref_p for details. */
9316 mips_insn_has_inflexible_gp_ref_p (rtx insn)
9318 /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE
9319 indicate that the target could be a traditional MIPS
9320 lazily-binding stub. */
9321 return find_reg_fusage (insn, USE, pic_offset_table_rtx);
9324 /* Return true if the current function refers to the global pointer
9325 in a way that forces $28 to be valid. This means that we can't
9326 change the choice of global pointer, even for NewABI code.
9328 One example of this (and one which needs several checks) is that
9329 $28 must be valid when calling traditional MIPS lazy-binding stubs.
9330 (This restriction does not apply to PLTs.) */
9333 mips_cfun_has_inflexible_gp_ref_p (void)
9335 /* If the function has a nonlocal goto, $28 must hold the correct
9336 global pointer for the target function. That is, the target
9337 of the goto implicitly uses $28. */
9338 if (crtl->has_nonlocal_goto)
9341 if (TARGET_ABICALLS_PIC2)
9343 /* Symbolic accesses implicitly use the global pointer unless
9344 -mexplicit-relocs is in effect. JAL macros to symbolic addresses
9345 might go to traditional MIPS lazy-binding stubs. */
9346 if (!TARGET_EXPLICIT_RELOCS)
9349 /* FUNCTION_PROFILER includes a JAL to _mcount, which again
9350 can be lazily-bound. */
9354 /* MIPS16 functions that return in FPRs need to call an
9355 external libgcc routine. This call is only made explict
9356 during mips_expand_epilogue, and it too might be lazily bound. */
9357 if (mips16_cfun_returns_in_fpr_p ())
9361 return mips_find_gp_ref (&cfun->machine->has_inflexible_gp_insn_p,
9362 mips_insn_has_inflexible_gp_ref_p);
9365 /* Return true if INSN refers to the global pointer in a "flexible" way.
9366 See mips_cfun_has_flexible_gp_ref_p for details. */
9369 mips_insn_has_flexible_gp_ref_p (rtx insn)
9371 return (get_attr_got (insn) != GOT_UNSET
9372 || mips_small_data_pattern_p (PATTERN (insn))
9373 || reg_overlap_mentioned_p (pic_offset_table_rtx, PATTERN (insn)));
9376 /* Return true if the current function references the global pointer,
9377 but if those references do not inherently require the global pointer
9378 to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */
9381 mips_cfun_has_flexible_gp_ref_p (void)
9383 /* Reload can sometimes introduce constant pool references
9384 into a function that otherwise didn't need them. For example,
9385 suppose we have an instruction like:
9387 (set (reg:DF R1) (float:DF (reg:SI R2)))
9389 If R2 turns out to be a constant such as 1, the instruction may
9390 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
9391 the option of using this constant if R2 doesn't get allocated
9394 In cases like these, reload will have added the constant to the
9395 pool but no instruction will yet refer to it. */
9396 if (TARGET_ABICALLS_PIC2 && !reload_completed && crtl->uses_const_pool)
9399 return mips_find_gp_ref (&cfun->machine->has_flexible_gp_insn_p,
9400 mips_insn_has_flexible_gp_ref_p);
9403 /* Return the register that should be used as the global pointer
9404 within this function. Return INVALID_REGNUM if the function
9405 doesn't need a global pointer. */
9408 mips_global_pointer (void)
9412 /* $gp is always available unless we're using a GOT. */
9413 if (!TARGET_USE_GOT)
9414 return GLOBAL_POINTER_REGNUM;
9416 /* If there are inflexible references to $gp, we must use the
9417 standard register. */
9418 if (mips_cfun_has_inflexible_gp_ref_p ())
9419 return GLOBAL_POINTER_REGNUM;
9421 /* If there are no current references to $gp, then the only uses
9422 we can introduce later are those involved in long branches. */
9423 if (TARGET_ABSOLUTE_JUMPS && !mips_cfun_has_flexible_gp_ref_p ())
9424 return INVALID_REGNUM;
9426 /* If the global pointer is call-saved, try to use a call-clobbered
9428 if (TARGET_CALL_SAVED_GP && crtl->is_leaf)
9429 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
9430 if (!df_regs_ever_live_p (regno)
9431 && call_really_used_regs[regno]
9432 && !fixed_regs[regno]
9433 && regno != PIC_FUNCTION_ADDR_REGNUM)
9436 return GLOBAL_POINTER_REGNUM;
9439 /* Return true if the current function's prologue must load the global
9440 pointer value into pic_offset_table_rtx and store the same value in
9441 the function's cprestore slot (if any).
9443 One problem we have to deal with is that, when emitting GOT-based
9444 position independent code, long-branch sequences will need to load
9445 the address of the branch target from the GOT. We don't know until
9446 the very end of compilation whether (and where) the function needs
9447 long branches, so we must ensure that _any_ branch can access the
9448 global pointer in some form. However, we do not want to pessimize
9449 the usual case in which all branches are short.
9451 We handle this as follows:
9453 (1) During reload, we set cfun->machine->global_pointer to
9454 INVALID_REGNUM if we _know_ that the current function
9455 doesn't need a global pointer. This is only valid if
9456 long branches don't need the GOT.
9458 Otherwise, we assume that we might need a global pointer
9459 and pick an appropriate register.
9461 (2) If cfun->machine->global_pointer != INVALID_REGNUM,
9462 we ensure that the global pointer is available at every
9463 block boundary bar entry and exit. We do this in one of two ways:
9465 - If the function has a cprestore slot, we ensure that this
9466 slot is valid at every branch. However, as explained in
9467 point (6) below, there is no guarantee that pic_offset_table_rtx
9468 itself is valid if new uses of the global pointer are introduced
9469 after the first post-epilogue split.
9471 We guarantee that the cprestore slot is valid by loading it
9472 into a fake register, CPRESTORE_SLOT_REGNUM. We then make
9473 this register live at every block boundary bar function entry
9474 and exit. It is then invalid to move the load (and thus the
9475 preceding store) across a block boundary.
9477 - If the function has no cprestore slot, we guarantee that
9478 pic_offset_table_rtx itself is valid at every branch.
9480 See mips_eh_uses for the handling of the register liveness.
9482 (3) During prologue and epilogue generation, we emit "ghost"
9483 placeholder instructions to manipulate the global pointer.
9485 (4) During prologue generation, we set cfun->machine->must_initialize_gp_p
9486 and cfun->machine->must_restore_gp_when_clobbered_p if we already know
9487 that the function needs a global pointer. (There is no need to set
9488 them earlier than this, and doing it as late as possible leads to
9489 fewer false positives.)
9491 (5) If cfun->machine->must_initialize_gp_p is true during a
9492 split_insns pass, we split the ghost instructions into real
9493 instructions. These split instructions can then be optimized in
9494 the usual way. Otherwise, we keep the ghost instructions intact,
9495 and optimize for the case where they aren't needed. We still
9496 have the option of splitting them later, if we need to introduce
9497 new uses of the global pointer.
9499 For example, the scheduler ignores a ghost instruction that
9500 stores $28 to the stack, but it handles the split form of
9501 the ghost instruction as an ordinary store.
9503 (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p
9504 is true during the first post-epilogue split_insns pass, we split
9505 calls and restore_gp patterns into instructions that explicitly
9506 load pic_offset_table_rtx from the cprestore slot. Otherwise,
9507 we split these patterns into instructions that _don't_ load from
9510 If cfun->machine->must_restore_gp_when_clobbered_p is true at the
9511 time of the split, then any instructions that exist at that time
9512 can make free use of pic_offset_table_rtx. However, if we want
9513 to introduce new uses of the global pointer after the split,
9514 we must explicitly load the value from the cprestore slot, since
9515 pic_offset_table_rtx itself might not be valid at a given point
9518 The idea is that we want to be able to delete redundant
9519 loads from the cprestore slot in the usual case where no
9520 long branches are needed.
9522 (7) If cfun->machine->must_initialize_gp_p is still false at the end
9523 of md_reorg, we decide whether the global pointer is needed for
9524 long branches. If so, we set cfun->machine->must_initialize_gp_p
9525 to true and split the ghost instructions into real instructions
9528 Note that the ghost instructions must have a zero length for three reasons:
9530 - Giving the length of the underlying $gp sequence might cause
9531 us to use long branches in cases where they aren't really needed.
9533 - They would perturb things like alignment calculations.
9535 - More importantly, the hazard detection in md_reorg relies on
9536 empty instructions having a zero length.
9538 If we find a long branch and split the ghost instructions at the
9539 end of md_reorg, the split could introduce more long branches.
9540 That isn't a problem though, because we still do the split before
9541 the final shorten_branches pass.
9543 This is extremely ugly, but it seems like the best compromise between
9544 correctness and efficiency. */
9547 mips_must_initialize_gp_p (void)
9549 return cfun->machine->must_initialize_gp_p;
9552 /* Return true if REGNO is a register that is ordinarily call-clobbered
9553 but must nevertheless be preserved by an interrupt handler. */
9556 mips_interrupt_extra_call_saved_reg_p (unsigned int regno)
9558 if (MD_REG_P (regno))
9561 if (TARGET_DSP && DSP_ACC_REG_P (regno))
9564 if (GP_REG_P (regno) && !cfun->machine->use_shadow_register_set_p)
9566 /* $0 is hard-wired. */
9567 if (regno == GP_REG_FIRST)
9570 /* The interrupt handler can treat kernel registers as
9571 scratch registers. */
9572 if (KERNEL_REG_P (regno))
9575 /* The function will return the stack pointer to its original value
9577 if (regno == STACK_POINTER_REGNUM)
9580 /* Otherwise, return true for registers that aren't ordinarily
9582 return call_really_used_regs[regno];
9588 /* Return true if the current function should treat register REGNO
9592 mips_cfun_call_saved_reg_p (unsigned int regno)
9594 /* If the user makes an ordinarily-call-saved register global,
9595 that register is no longer call-saved. */
9596 if (global_regs[regno])
9599 /* Interrupt handlers need to save extra registers. */
9600 if (cfun->machine->interrupt_handler_p
9601 && mips_interrupt_extra_call_saved_reg_p (regno))
9604 /* call_insns preserve $28 unless they explicitly say otherwise,
9605 so call_really_used_regs[] treats $28 as call-saved. However,
9606 we want the ABI property rather than the default call_insn
9608 return (regno == GLOBAL_POINTER_REGNUM
9609 ? TARGET_CALL_SAVED_GP
9610 : !call_really_used_regs[regno]);
9613 /* Return true if the function body might clobber register REGNO.
9614 We know that REGNO is call-saved. */
9617 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno)
9619 /* Some functions should be treated as clobbering all call-saved
9621 if (crtl->saves_all_registers)
9624 /* DF handles cases where a register is explicitly referenced in
9625 the rtl. Incoming values are passed in call-clobbered registers,
9626 so we can assume that any live call-saved register is set within
9628 if (df_regs_ever_live_p (regno))
9631 /* Check for registers that are clobbered by FUNCTION_PROFILER.
9632 These clobbers are not explicit in the rtl. */
9633 if (crtl->profile && MIPS_SAVE_REG_FOR_PROFILING_P (regno))
9636 /* If we're using a call-saved global pointer, the function's
9637 prologue will need to set it up. */
9638 if (cfun->machine->global_pointer == regno)
9641 /* The function's prologue will need to set the frame pointer if
9642 frame_pointer_needed. */
9643 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
9646 /* If a MIPS16 function returns a value in FPRs, its epilogue
9647 will need to call an external libgcc routine. This yet-to-be
9648 generated call_insn will clobber $31. */
9649 if (regno == RETURN_ADDR_REGNUM && mips16_cfun_returns_in_fpr_p ())
9652 /* If REGNO is ordinarily call-clobbered, we must assume that any
9653 called function could modify it. */
9654 if (cfun->machine->interrupt_handler_p
9656 && mips_interrupt_extra_call_saved_reg_p (regno))
9662 /* Return true if the current function must save register REGNO. */
9665 mips_save_reg_p (unsigned int regno)
9667 if (mips_cfun_call_saved_reg_p (regno))
9669 if (mips_cfun_might_clobber_call_saved_reg_p (regno))
9672 /* Save both registers in an FPR pair if either one is used. This is
9673 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
9674 register to be used without the even register. */
9675 if (FP_REG_P (regno)
9676 && MAX_FPRS_PER_FMT == 2
9677 && mips_cfun_might_clobber_call_saved_reg_p (regno + 1))
9681 /* We need to save the incoming return address if __builtin_eh_return
9682 is being used to set a different return address. */
9683 if (regno == RETURN_ADDR_REGNUM && crtl->calls_eh_return)
9689 /* Populate the current function's mips_frame_info structure.
9691 MIPS stack frames look like:
9693 +-------------------------------+
9695 | incoming stack arguments |
9697 +-------------------------------+
9699 | caller-allocated save area |
9700 A | for register arguments |
9702 +-------------------------------+ <-- incoming stack pointer
9704 | callee-allocated save area |
9705 B | for arguments that are |
9706 | split between registers and |
9709 +-------------------------------+ <-- arg_pointer_rtx
9711 C | callee-allocated save area |
9712 | for register varargs |
9714 +-------------------------------+ <-- frame_pointer_rtx
9715 | | + cop0_sp_offset
9716 | COP0 reg save area | + UNITS_PER_WORD
9718 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
9719 | | + UNITS_PER_WORD
9720 | accumulator save area |
9722 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
9723 | | + UNITS_PER_HWFPVALUE
9726 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset
9727 | | + UNITS_PER_WORD
9730 +-------------------------------+ <-- frame_pointer_rtx with
9731 | | \ -fstack-protector
9732 | local variables | | var_size
9734 +-------------------------------+
9736 | $gp save area | | cprestore_size
9738 P +-------------------------------+ <-- hard_frame_pointer_rtx for
9740 | outgoing stack arguments | |
9742 +-------------------------------+ | args_size
9744 | caller-allocated save area | |
9745 | for register arguments | |
9747 +-------------------------------+ <-- stack_pointer_rtx
9748 frame_pointer_rtx without
9750 hard_frame_pointer_rtx for
9753 At least two of A, B and C will be empty.
9755 Dynamic stack allocations such as alloca insert data at point P.
9756 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
9757 hard_frame_pointer_rtx unchanged. */
9760 mips_compute_frame_info (void)
9762 struct mips_frame_info *frame;
9763 HOST_WIDE_INT offset, size;
9764 unsigned int regno, i;
9766 /* Set this function's interrupt properties. */
9767 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
9770 error ("the %<interrupt%> attribute requires a MIPS32r2 processor");
9771 else if (TARGET_HARD_FLOAT)
9772 error ("the %<interrupt%> attribute requires %<-msoft-float%>");
9773 else if (TARGET_MIPS16)
9774 error ("interrupt handlers cannot be MIPS16 functions");
9777 cfun->machine->interrupt_handler_p = true;
9778 cfun->machine->use_shadow_register_set_p =
9779 mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl));
9780 cfun->machine->keep_interrupts_masked_p =
9781 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl));
9782 cfun->machine->use_debug_exception_return_p =
9783 mips_use_debug_exception_return_p (TREE_TYPE
9784 (current_function_decl));
9788 frame = &cfun->machine->frame;
9789 memset (frame, 0, sizeof (*frame));
9790 size = get_frame_size ();
9792 cfun->machine->global_pointer = mips_global_pointer ();
9794 /* The first two blocks contain the outgoing argument area and the $gp save
9795 slot. This area isn't needed in leaf functions, but if the
9796 target-independent frame size is nonzero, we have already committed to
9797 allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */
9798 if ((size == 0 || FRAME_GROWS_DOWNWARD) && crtl->is_leaf)
9800 /* The MIPS 3.0 linker does not like functions that dynamically
9801 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
9802 looks like we are trying to create a second frame pointer to the
9803 function, so allocate some stack space to make it happy. */
9804 if (cfun->calls_alloca)
9805 frame->args_size = REG_PARM_STACK_SPACE (cfun->decl);
9807 frame->args_size = 0;
9808 frame->cprestore_size = 0;
9812 frame->args_size = crtl->outgoing_args_size;
9813 frame->cprestore_size = MIPS_GP_SAVE_AREA_SIZE;
9815 offset = frame->args_size + frame->cprestore_size;
9817 /* Move above the local variables. */
9818 frame->var_size = MIPS_STACK_ALIGN (size);
9819 offset += frame->var_size;
9821 /* Find out which GPRs we need to save. */
9822 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
9823 if (mips_save_reg_p (regno))
9826 frame->mask |= 1 << (regno - GP_REG_FIRST);
9829 /* If this function calls eh_return, we must also save and restore the
9830 EH data registers. */
9831 if (crtl->calls_eh_return)
9832 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; i++)
9835 frame->mask |= 1 << (EH_RETURN_DATA_REGNO (i) - GP_REG_FIRST);
9838 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
9839 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
9840 save all later registers too. */
9841 if (GENERATE_MIPS16E_SAVE_RESTORE)
9843 mips16e_mask_registers (&frame->mask, mips16e_s2_s8_regs,
9844 ARRAY_SIZE (mips16e_s2_s8_regs), &frame->num_gp);
9845 mips16e_mask_registers (&frame->mask, mips16e_a0_a3_regs,
9846 ARRAY_SIZE (mips16e_a0_a3_regs), &frame->num_gp);
9849 /* Move above the GPR save area. */
9850 if (frame->num_gp > 0)
9852 offset += MIPS_STACK_ALIGN (frame->num_gp * UNITS_PER_WORD);
9853 frame->gp_sp_offset = offset - UNITS_PER_WORD;
9856 /* Find out which FPRs we need to save. This loop must iterate over
9857 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
9858 if (TARGET_HARD_FLOAT)
9859 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += MAX_FPRS_PER_FMT)
9860 if (mips_save_reg_p (regno))
9862 frame->num_fp += MAX_FPRS_PER_FMT;
9863 frame->fmask |= ~(~0 << MAX_FPRS_PER_FMT) << (regno - FP_REG_FIRST);
9866 /* Move above the FPR save area. */
9867 if (frame->num_fp > 0)
9869 offset += MIPS_STACK_ALIGN (frame->num_fp * UNITS_PER_FPREG);
9870 frame->fp_sp_offset = offset - UNITS_PER_HWFPVALUE;
9873 /* Add in space for the interrupt context information. */
9874 if (cfun->machine->interrupt_handler_p)
9877 if (mips_save_reg_p (LO_REGNUM) || mips_save_reg_p (HI_REGNUM))
9880 frame->acc_mask |= (1 << 0);
9883 /* Check accumulators 1, 2, 3. */
9884 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
9885 if (mips_save_reg_p (i) || mips_save_reg_p (i + 1))
9888 frame->acc_mask |= 1 << (((i - DSP_ACC_REG_FIRST) / 2) + 1);
9891 /* All interrupt context functions need space to preserve STATUS. */
9892 frame->num_cop0_regs++;
9894 /* If we don't keep interrupts masked, we need to save EPC. */
9895 if (!cfun->machine->keep_interrupts_masked_p)
9896 frame->num_cop0_regs++;
9899 /* Move above the accumulator save area. */
9900 if (frame->num_acc > 0)
9902 /* Each accumulator needs 2 words. */
9903 offset += frame->num_acc * 2 * UNITS_PER_WORD;
9904 frame->acc_sp_offset = offset - UNITS_PER_WORD;
9907 /* Move above the COP0 register save area. */
9908 if (frame->num_cop0_regs > 0)
9910 offset += frame->num_cop0_regs * UNITS_PER_WORD;
9911 frame->cop0_sp_offset = offset - UNITS_PER_WORD;
9914 /* Move above the callee-allocated varargs save area. */
9915 offset += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
9916 frame->arg_pointer_offset = offset;
9918 /* Move above the callee-allocated area for pretend stack arguments. */
9919 offset += crtl->args.pretend_args_size;
9920 frame->total_size = offset;
9922 /* Work out the offsets of the save areas from the top of the frame. */
9923 if (frame->gp_sp_offset > 0)
9924 frame->gp_save_offset = frame->gp_sp_offset - offset;
9925 if (frame->fp_sp_offset > 0)
9926 frame->fp_save_offset = frame->fp_sp_offset - offset;
9927 if (frame->acc_sp_offset > 0)
9928 frame->acc_save_offset = frame->acc_sp_offset - offset;
9929 if (frame->num_cop0_regs > 0)
9930 frame->cop0_save_offset = frame->cop0_sp_offset - offset;
9932 /* MIPS16 code offsets the frame pointer by the size of the outgoing
9933 arguments. This tends to increase the chances of using unextended
9934 instructions for local variables and incoming arguments. */
9936 frame->hard_frame_pointer_offset = frame->args_size;
9939 /* Return the style of GP load sequence that is being used for the
9940 current function. */
9942 enum mips_loadgp_style
9943 mips_current_loadgp_style (void)
9945 if (!TARGET_USE_GOT || cfun->machine->global_pointer == INVALID_REGNUM)
9951 if (TARGET_ABSOLUTE_ABICALLS)
9952 return LOADGP_ABSOLUTE;
9954 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
9957 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
9960 mips_frame_pointer_required (void)
9962 /* If the function contains dynamic stack allocations, we need to
9963 use the frame pointer to access the static parts of the frame. */
9964 if (cfun->calls_alloca)
9967 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
9968 reload may be unable to compute the address of a local variable,
9969 since there is no way to add a large constant to the stack pointer
9970 without using a second temporary register. */
9973 mips_compute_frame_info ();
9974 if (!SMALL_OPERAND (cfun->machine->frame.total_size))
9981 /* Make sure that we're not trying to eliminate to the wrong hard frame
9985 mips_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
9987 return (to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM);
9990 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
9991 or argument pointer. TO is either the stack pointer or hard frame
9995 mips_initial_elimination_offset (int from, int to)
9997 HOST_WIDE_INT offset;
9999 mips_compute_frame_info ();
10001 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */
10004 case FRAME_POINTER_REGNUM:
10005 if (FRAME_GROWS_DOWNWARD)
10006 offset = (cfun->machine->frame.args_size
10007 + cfun->machine->frame.cprestore_size
10008 + cfun->machine->frame.var_size);
10013 case ARG_POINTER_REGNUM:
10014 offset = cfun->machine->frame.arg_pointer_offset;
10018 gcc_unreachable ();
10021 if (to == HARD_FRAME_POINTER_REGNUM)
10022 offset -= cfun->machine->frame.hard_frame_pointer_offset;
10027 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
10030 mips_extra_live_on_entry (bitmap regs)
10032 if (TARGET_USE_GOT)
10034 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
10035 the global pointer. */
10036 if (!TARGET_ABSOLUTE_ABICALLS)
10037 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
10039 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
10040 the global pointer. */
10042 bitmap_set_bit (regs, MIPS16_PIC_TEMP_REGNUM);
10044 /* See the comment above load_call<mode> for details. */
10045 bitmap_set_bit (regs, GOT_VERSION_REGNUM);
10049 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
10053 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
10058 return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);
10061 /* Emit code to change the current function's return address to
10062 ADDRESS. SCRATCH is available as a scratch register, if needed.
10063 ADDRESS and SCRATCH are both word-mode GPRs. */
10066 mips_set_return_address (rtx address, rtx scratch)
10070 gcc_assert (BITSET_P (cfun->machine->frame.mask, RETURN_ADDR_REGNUM));
10071 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
10072 cfun->machine->frame.gp_sp_offset);
10073 mips_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address);
10076 /* Return true if the current function has a cprestore slot. */
10079 mips_cfun_has_cprestore_slot_p (void)
10081 return (cfun->machine->global_pointer != INVALID_REGNUM
10082 && cfun->machine->frame.cprestore_size > 0);
10085 /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the
10086 cprestore slot. LOAD_P is true if the caller wants to load from
10087 the cprestore slot; it is false if the caller wants to store to
10091 mips_get_cprestore_base_and_offset (rtx *base, HOST_WIDE_INT *offset,
10094 const struct mips_frame_info *frame;
10096 frame = &cfun->machine->frame;
10097 /* .cprestore always uses the stack pointer instead of the frame pointer.
10098 We have a free choice for direct stores for non-MIPS16 functions,
10099 and for MIPS16 functions whose cprestore slot is in range of the
10100 stack pointer. Using the stack pointer would sometimes give more
10101 (early) scheduling freedom, but using the frame pointer would
10102 sometimes give more (late) scheduling freedom. It's hard to
10103 predict which applies to a given function, so let's keep things
10106 Loads must always use the frame pointer in functions that call
10107 alloca, and there's little benefit to using the stack pointer
10109 if (frame_pointer_needed && !(TARGET_CPRESTORE_DIRECTIVE && !load_p))
10111 *base = hard_frame_pointer_rtx;
10112 *offset = frame->args_size - frame->hard_frame_pointer_offset;
10116 *base = stack_pointer_rtx;
10117 *offset = frame->args_size;
10121 /* Return true if X is the load or store address of the cprestore slot;
10122 LOAD_P says which. */
10125 mips_cprestore_address_p (rtx x, bool load_p)
10127 rtx given_base, required_base;
10128 HOST_WIDE_INT given_offset, required_offset;
10130 mips_split_plus (x, &given_base, &given_offset);
10131 mips_get_cprestore_base_and_offset (&required_base, &required_offset, load_p);
10132 return given_base == required_base && given_offset == required_offset;
10135 /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are
10136 going to load from it, false if we are going to store to it.
10137 Use TEMP as a temporary register if need be. */
10140 mips_cprestore_slot (rtx temp, bool load_p)
10143 HOST_WIDE_INT offset;
10145 mips_get_cprestore_base_and_offset (&base, &offset, load_p);
10146 return gen_frame_mem (Pmode, mips_add_offset (temp, base, offset));
10149 /* Emit instructions to save global pointer value GP into cprestore
10150 slot MEM. OFFSET is the offset that MEM applies to the base register.
10152 MEM may not be a legitimate address. If it isn't, TEMP is a
10153 temporary register that can be used, otherwise it is a SCRATCH. */
10156 mips_save_gp_to_cprestore_slot (rtx mem, rtx offset, rtx gp, rtx temp)
10158 if (TARGET_CPRESTORE_DIRECTIVE)
10160 gcc_assert (gp == pic_offset_table_rtx);
10161 emit_insn (PMODE_INSN (gen_cprestore, (mem, offset)));
10164 mips_emit_move (mips_cprestore_slot (temp, false), gp);
10167 /* Restore $gp from its save slot, using TEMP as a temporary base register
10168 if need be. This function is for o32 and o64 abicalls only.
10170 See mips_must_initialize_gp_p for details about how we manage the
10174 mips_restore_gp_from_cprestore_slot (rtx temp)
10176 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI && epilogue_completed);
10178 if (!cfun->machine->must_restore_gp_when_clobbered_p)
10180 emit_note (NOTE_INSN_DELETED);
10186 mips_emit_move (temp, mips_cprestore_slot (temp, true));
10187 mips_emit_move (pic_offset_table_rtx, temp);
10190 mips_emit_move (pic_offset_table_rtx, mips_cprestore_slot (temp, true));
10191 if (!TARGET_EXPLICIT_RELOCS)
10192 emit_insn (gen_blockage ());
10195 /* A function to save or store a register. The first argument is the
10196 register and the second is the stack slot. */
10197 typedef void (*mips_save_restore_fn) (rtx, rtx);
10199 /* Use FN to save or restore register REGNO. MODE is the register's
10200 mode and OFFSET is the offset of its save slot from the current
10204 mips_save_restore_reg (enum machine_mode mode, int regno,
10205 HOST_WIDE_INT offset, mips_save_restore_fn fn)
10209 mem = gen_frame_mem (mode, plus_constant (Pmode, stack_pointer_rtx,
10211 fn (gen_rtx_REG (mode, regno), mem);
10214 /* Call FN for each accumlator that is saved by the current function.
10215 SP_OFFSET is the offset of the current stack pointer from the start
10219 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
10221 HOST_WIDE_INT offset;
10224 offset = cfun->machine->frame.acc_sp_offset - sp_offset;
10225 if (BITSET_P (cfun->machine->frame.acc_mask, 0))
10227 mips_save_restore_reg (word_mode, LO_REGNUM, offset, fn);
10228 offset -= UNITS_PER_WORD;
10229 mips_save_restore_reg (word_mode, HI_REGNUM, offset, fn);
10230 offset -= UNITS_PER_WORD;
10233 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
10234 if (BITSET_P (cfun->machine->frame.acc_mask,
10235 ((regno - DSP_ACC_REG_FIRST) / 2) + 1))
10237 mips_save_restore_reg (word_mode, regno, offset, fn);
10238 offset -= UNITS_PER_WORD;
10242 /* Call FN for each register that is saved by the current function.
10243 SP_OFFSET is the offset of the current stack pointer from the start
10247 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset,
10248 mips_save_restore_fn fn)
10250 enum machine_mode fpr_mode;
10251 HOST_WIDE_INT offset;
10254 /* Save registers starting from high to low. The debuggers prefer at least
10255 the return register be stored at func+4, and also it allows us not to
10256 need a nop in the epilogue if at least one register is reloaded in
10257 addition to return address. */
10258 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
10259 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
10260 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
10262 /* Record the ra offset for use by mips_function_profiler. */
10263 if (regno == RETURN_ADDR_REGNUM)
10264 cfun->machine->frame.ra_fp_offset = offset + sp_offset;
10265 mips_save_restore_reg (word_mode, regno, offset, fn);
10266 offset -= UNITS_PER_WORD;
10269 /* This loop must iterate over the same space as its companion in
10270 mips_compute_frame_info. */
10271 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
10272 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
10273 for (regno = FP_REG_LAST - MAX_FPRS_PER_FMT + 1;
10274 regno >= FP_REG_FIRST;
10275 regno -= MAX_FPRS_PER_FMT)
10276 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
10278 mips_save_restore_reg (fpr_mode, regno, offset, fn);
10279 offset -= GET_MODE_SIZE (fpr_mode);
10283 /* Return true if a move between register REGNO and its save slot (MEM)
10284 can be done in a single move. LOAD_P is true if we are loading
10285 from the slot, false if we are storing to it. */
10288 mips_direct_save_slot_move_p (unsigned int regno, rtx mem, bool load_p)
10290 /* There is a specific MIPS16 instruction for saving $31 to the stack. */
10291 if (TARGET_MIPS16 && !load_p && regno == RETURN_ADDR_REGNUM)
10294 return mips_secondary_reload_class (REGNO_REG_CLASS (regno),
10295 GET_MODE (mem), mem, load_p) == NO_REGS;
10298 /* Emit a move from SRC to DEST, given that one of them is a register
10299 save slot and that the other is a register. TEMP is a temporary
10300 GPR of the same mode that is available if need be. */
10303 mips_emit_save_slot_move (rtx dest, rtx src, rtx temp)
10305 unsigned int regno;
10310 regno = REGNO (src);
10315 regno = REGNO (dest);
10319 if (regno == cfun->machine->global_pointer && !mips_must_initialize_gp_p ())
10321 /* We don't yet know whether we'll need this instruction or not.
10322 Postpone the decision by emitting a ghost move. This move
10323 is specifically not frame-related; only the split version is. */
10325 emit_insn (gen_move_gpdi (dest, src));
10327 emit_insn (gen_move_gpsi (dest, src));
10331 if (regno == HI_REGNUM)
10335 mips_emit_move (temp, src);
10337 emit_insn (gen_mthisi_di (gen_rtx_REG (TImode, MD_REG_FIRST),
10338 temp, gen_rtx_REG (DImode, LO_REGNUM)));
10340 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode, MD_REG_FIRST),
10341 temp, gen_rtx_REG (SImode, LO_REGNUM)));
10346 emit_insn (gen_mfhidi_ti (temp,
10347 gen_rtx_REG (TImode, MD_REG_FIRST)));
10349 emit_insn (gen_mfhisi_di (temp,
10350 gen_rtx_REG (DImode, MD_REG_FIRST)));
10351 mips_emit_move (dest, temp);
10354 else if (mips_direct_save_slot_move_p (regno, mem, mem == src))
10355 mips_emit_move (dest, src);
10358 gcc_assert (!reg_overlap_mentioned_p (dest, temp));
10359 mips_emit_move (temp, src);
10360 mips_emit_move (dest, temp);
10363 mips_set_frame_expr (mips_frame_set (dest, src));
10366 /* If we're generating n32 or n64 abicalls, and the current function
10367 does not use $28 as its global pointer, emit a cplocal directive.
10368 Use pic_offset_table_rtx as the argument to the directive. */
10371 mips_output_cplocal (void)
10373 if (!TARGET_EXPLICIT_RELOCS
10374 && mips_must_initialize_gp_p ()
10375 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
10376 output_asm_insn (".cplocal %+", 0);
10379 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
10382 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
10384 const char *fnname;
10386 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
10387 floating-point arguments. */
10389 && TARGET_HARD_FLOAT_ABI
10390 && crtl->args.info.fp_code != 0)
10391 mips16_build_function_stub ();
10393 /* Get the function name the same way that toplev.c does before calling
10394 assemble_start_function. This is needed so that the name used here
10395 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10396 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
10397 mips_start_function_definition (fnname, TARGET_MIPS16);
10399 /* Output MIPS-specific frame information. */
10400 if (!flag_inhibit_size_directive)
10402 const struct mips_frame_info *frame;
10404 frame = &cfun->machine->frame;
10406 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
10408 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
10409 "# vars= " HOST_WIDE_INT_PRINT_DEC
10411 ", args= " HOST_WIDE_INT_PRINT_DEC
10412 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
10413 reg_names[frame_pointer_needed
10414 ? HARD_FRAME_POINTER_REGNUM
10415 : STACK_POINTER_REGNUM],
10416 (frame_pointer_needed
10417 ? frame->total_size - frame->hard_frame_pointer_offset
10418 : frame->total_size),
10419 reg_names[RETURN_ADDR_REGNUM],
10421 frame->num_gp, frame->num_fp,
10423 frame->cprestore_size);
10425 /* .mask MASK, OFFSET. */
10426 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
10427 frame->mask, frame->gp_save_offset);
10429 /* .fmask MASK, OFFSET. */
10430 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
10431 frame->fmask, frame->fp_save_offset);
10434 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
10435 Also emit the ".set noreorder; .set nomacro" sequence for functions
10437 if (mips_must_initialize_gp_p ()
10438 && mips_current_loadgp_style () == LOADGP_OLDABI)
10442 /* This is a fixed-form sequence. The position of the
10443 first two instructions is important because of the
10444 way _gp_disp is defined. */
10445 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
10446 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
10447 output_asm_insn ("sll\t$2,16", 0);
10448 output_asm_insn ("addu\t$2,$3", 0);
10452 /* .cpload must be in a .set noreorder but not a
10453 .set nomacro block. */
10454 mips_push_asm_switch (&mips_noreorder);
10455 output_asm_insn (".cpload\t%^", 0);
10456 if (!cfun->machine->all_noreorder_p)
10457 mips_pop_asm_switch (&mips_noreorder);
10459 mips_push_asm_switch (&mips_nomacro);
10462 else if (cfun->machine->all_noreorder_p)
10464 mips_push_asm_switch (&mips_noreorder);
10465 mips_push_asm_switch (&mips_nomacro);
10468 /* Tell the assembler which register we're using as the global
10469 pointer. This is needed for thunks, since they can use either
10470 explicit relocs or assembler macros. */
10471 mips_output_cplocal ();
10474 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
10477 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
10478 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
10480 const char *fnname;
10482 /* Reinstate the normal $gp. */
10483 SET_REGNO (pic_offset_table_rtx, GLOBAL_POINTER_REGNUM);
10484 mips_output_cplocal ();
10486 if (cfun->machine->all_noreorder_p)
10488 mips_pop_asm_switch (&mips_nomacro);
10489 mips_pop_asm_switch (&mips_noreorder);
10492 /* Get the function name the same way that toplev.c does before calling
10493 assemble_start_function. This is needed so that the name used here
10494 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10495 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
10496 mips_end_function_definition (fnname);
10499 /* Emit an optimisation barrier for accesses to the current frame. */
10502 mips_frame_barrier (void)
10504 emit_clobber (gen_frame_mem (BLKmode, stack_pointer_rtx));
10507 /* Save register REG to MEM. Make the instruction frame-related. */
10510 mips_save_reg (rtx reg, rtx mem)
10512 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
10516 mips_emit_move_or_split (mem, reg, SPLIT_IF_NECESSARY);
10518 x1 = mips_frame_set (mips_subword (mem, false),
10519 mips_subword (reg, false));
10520 x2 = mips_frame_set (mips_subword (mem, true),
10521 mips_subword (reg, true));
10522 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
10525 mips_emit_save_slot_move (mem, reg, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
10528 /* The __gnu_local_gp symbol. */
10530 static GTY(()) rtx mips_gnu_local_gp;
10532 /* If we're generating n32 or n64 abicalls, emit instructions
10533 to set up the global pointer. */
10536 mips_emit_loadgp (void)
10538 rtx addr, offset, incoming_address, base, index, pic_reg;
10540 pic_reg = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
10541 switch (mips_current_loadgp_style ())
10543 case LOADGP_ABSOLUTE:
10544 if (mips_gnu_local_gp == NULL)
10546 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
10547 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
10549 emit_insn (PMODE_INSN (gen_loadgp_absolute,
10550 (pic_reg, mips_gnu_local_gp)));
10553 case LOADGP_OLDABI:
10554 /* Added by mips_output_function_prologue. */
10557 case LOADGP_NEWABI:
10558 addr = XEXP (DECL_RTL (current_function_decl), 0);
10559 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
10560 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
10561 emit_insn (PMODE_INSN (gen_loadgp_newabi,
10562 (pic_reg, offset, incoming_address)));
10566 base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE));
10567 index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX));
10568 emit_insn (PMODE_INSN (gen_loadgp_rtp, (pic_reg, base, index)));
10576 emit_insn (PMODE_INSN (gen_copygp_mips16,
10577 (pic_offset_table_rtx, pic_reg)));
10579 /* Emit a blockage if there are implicit uses of the GP register.
10580 This includes profiled functions, because FUNCTION_PROFILE uses
10582 if (!TARGET_EXPLICIT_RELOCS || crtl->profile)
10583 emit_insn (gen_loadgp_blockage ());
10586 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
10588 #if PROBE_INTERVAL > 32768
10589 #error Cannot use indexed addressing mode for stack probing
10592 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
10593 inclusive. These are offsets from the current stack pointer. */
10596 mips_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size)
10599 sorry ("-fstack-check=specific not implemented for MIPS16");
10601 /* See if we have a constant small number of probes to generate. If so,
10602 that's the easy case. */
10603 if (first + size <= 32768)
10607 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
10608 it exceeds SIZE. If only one probe is needed, this will not
10609 generate any code. Then probe at FIRST + SIZE. */
10610 for (i = PROBE_INTERVAL; i < size; i += PROBE_INTERVAL)
10611 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
10614 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
10618 /* Otherwise, do the same as above, but in a loop. Note that we must be
10619 extra careful with variables wrapping around because we might be at
10620 the very top (or the very bottom) of the address space and we have
10621 to be able to handle this case properly; in particular, we use an
10622 equality test for the loop condition. */
10625 HOST_WIDE_INT rounded_size;
10626 rtx r3 = MIPS_PROLOGUE_TEMP (Pmode);
10627 rtx r12 = MIPS_PROLOGUE_TEMP2 (Pmode);
10629 /* Sanity check for the addressing mode we're going to use. */
10630 gcc_assert (first <= 32768);
10633 /* Step 1: round SIZE to the previous multiple of the interval. */
10635 rounded_size = size & -PROBE_INTERVAL;
10638 /* Step 2: compute initial and final value of the loop counter. */
10640 /* TEST_ADDR = SP + FIRST. */
10641 emit_insn (gen_rtx_SET (VOIDmode, r3,
10642 plus_constant (Pmode, stack_pointer_rtx,
10645 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
10646 if (rounded_size > 32768)
10648 emit_move_insn (r12, GEN_INT (rounded_size));
10649 emit_insn (gen_rtx_SET (VOIDmode, r12,
10650 gen_rtx_MINUS (Pmode, r3, r12)));
10653 emit_insn (gen_rtx_SET (VOIDmode, r12,
10654 plus_constant (Pmode, r3, -rounded_size)));
10657 /* Step 3: the loop
10659 while (TEST_ADDR != LAST_ADDR)
10661 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
10665 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
10666 until it is equal to ROUNDED_SIZE. */
10668 emit_insn (PMODE_INSN (gen_probe_stack_range, (r3, r3, r12)));
10671 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
10672 that SIZE is equal to ROUNDED_SIZE. */
10674 if (size != rounded_size)
10675 emit_stack_probe (plus_constant (Pmode, r12, rounded_size - size));
10678 /* Make sure nothing is scheduled before we are done. */
10679 emit_insn (gen_blockage ());
10682 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
10683 absolute addresses. */
10686 mips_output_probe_stack_range (rtx reg1, rtx reg2)
10688 static int labelno = 0;
10689 char loop_lab[32], end_lab[32], tmp[64];
10692 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno);
10693 ASM_GENERATE_INTERNAL_LABEL (end_lab, "LPSRE", labelno++);
10695 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
10697 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
10700 strcpy (tmp, "%(%<beq\t%0,%1,");
10701 output_asm_insn (strcat (tmp, &end_lab[1]), xops);
10703 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
10704 xops[1] = GEN_INT (-PROBE_INTERVAL);
10705 if (TARGET_64BIT && TARGET_LONG64)
10706 output_asm_insn ("daddiu\t%0,%0,%1", xops);
10708 output_asm_insn ("addiu\t%0,%0,%1", xops);
10710 /* Probe at TEST_ADDR and branch. */
10711 fprintf (asm_out_file, "\tb\t");
10712 assemble_name_raw (asm_out_file, loop_lab);
10713 fputc ('\n', asm_out_file);
10715 output_asm_insn ("sd\t$0,0(%0)%)", xops);
10717 output_asm_insn ("sw\t$0,0(%0)%)", xops);
10719 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, end_lab);
10724 /* A for_each_rtx callback. Stop the search if *X is a kernel register. */
10727 mips_kernel_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
10729 return REG_P (*x) && KERNEL_REG_P (REGNO (*x));
10732 /* Expand the "prologue" pattern. */
10735 mips_expand_prologue (void)
10737 const struct mips_frame_info *frame;
10738 HOST_WIDE_INT size;
10739 unsigned int nargs;
10742 if (cfun->machine->global_pointer != INVALID_REGNUM)
10744 /* Check whether an insn uses pic_offset_table_rtx, either explicitly
10745 or implicitly. If so, we can commit to using a global pointer
10746 straight away, otherwise we need to defer the decision. */
10747 if (mips_cfun_has_inflexible_gp_ref_p ()
10748 || mips_cfun_has_flexible_gp_ref_p ())
10750 cfun->machine->must_initialize_gp_p = true;
10751 cfun->machine->must_restore_gp_when_clobbered_p = true;
10754 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
10757 frame = &cfun->machine->frame;
10758 size = frame->total_size;
10760 if (flag_stack_usage_info)
10761 current_function_static_stack_size = size;
10763 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK && size)
10764 mips_emit_probe_stack_range (STACK_CHECK_PROTECT, size);
10766 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
10767 bytes beforehand; this is enough to cover the register save area
10768 without going out of range. */
10769 if (((frame->mask | frame->fmask | frame->acc_mask) != 0)
10770 || frame->num_cop0_regs > 0)
10772 HOST_WIDE_INT step1;
10774 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
10775 if (GENERATE_MIPS16E_SAVE_RESTORE)
10777 HOST_WIDE_INT offset;
10778 unsigned int mask, regno;
10780 /* Try to merge argument stores into the save instruction. */
10781 nargs = mips16e_collect_argument_saves ();
10783 /* Build the save instruction. */
10784 mask = frame->mask;
10785 insn = mips16e_build_save_restore (false, &mask, &offset,
10787 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10788 mips_frame_barrier ();
10791 /* Check if we need to save other registers. */
10792 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
10793 if (BITSET_P (mask, regno - GP_REG_FIRST))
10795 offset -= UNITS_PER_WORD;
10796 mips_save_restore_reg (word_mode, regno,
10797 offset, mips_save_reg);
10802 if (cfun->machine->interrupt_handler_p)
10804 HOST_WIDE_INT offset;
10807 /* If this interrupt is using a shadow register set, we need to
10808 get the stack pointer from the previous register set. */
10809 if (cfun->machine->use_shadow_register_set_p)
10810 emit_insn (gen_mips_rdpgpr (stack_pointer_rtx,
10811 stack_pointer_rtx));
10813 if (!cfun->machine->keep_interrupts_masked_p)
10815 /* Move from COP0 Cause to K0. */
10816 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K0_REG_NUM),
10817 gen_rtx_REG (SImode,
10818 COP0_CAUSE_REG_NUM)));
10819 /* Move from COP0 EPC to K1. */
10820 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
10821 gen_rtx_REG (SImode,
10822 COP0_EPC_REG_NUM)));
10825 /* Allocate the first part of the frame. */
10826 insn = gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx,
10828 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10829 mips_frame_barrier ();
10832 /* Start at the uppermost location for saving. */
10833 offset = frame->cop0_sp_offset - size;
10834 if (!cfun->machine->keep_interrupts_masked_p)
10836 /* Push EPC into its stack slot. */
10837 mem = gen_frame_mem (word_mode,
10838 plus_constant (Pmode, stack_pointer_rtx,
10840 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
10841 offset -= UNITS_PER_WORD;
10844 /* Move from COP0 Status to K1. */
10845 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
10846 gen_rtx_REG (SImode,
10847 COP0_STATUS_REG_NUM)));
10849 /* Right justify the RIPL in k0. */
10850 if (!cfun->machine->keep_interrupts_masked_p)
10851 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode, K0_REG_NUM),
10852 gen_rtx_REG (SImode, K0_REG_NUM),
10853 GEN_INT (CAUSE_IPL)));
10855 /* Push Status into its stack slot. */
10856 mem = gen_frame_mem (word_mode,
10857 plus_constant (Pmode, stack_pointer_rtx,
10859 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
10860 offset -= UNITS_PER_WORD;
10862 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
10863 if (!cfun->machine->keep_interrupts_masked_p)
10864 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
10867 gen_rtx_REG (SImode, K0_REG_NUM)));
10869 if (!cfun->machine->keep_interrupts_masked_p)
10870 /* Enable interrupts by clearing the KSU ERL and EXL bits.
10871 IE is already the correct value, so we don't have to do
10872 anything explicit. */
10873 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
10876 gen_rtx_REG (SImode, GP_REG_FIRST)));
10878 /* Disable interrupts by clearing the KSU, ERL, EXL,
10880 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
10883 gen_rtx_REG (SImode, GP_REG_FIRST)));
10887 insn = gen_add3_insn (stack_pointer_rtx,
10890 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10891 mips_frame_barrier ();
10894 mips_for_each_saved_acc (size, mips_save_reg);
10895 mips_for_each_saved_gpr_and_fpr (size, mips_save_reg);
10899 /* Allocate the rest of the frame. */
10902 if (SMALL_OPERAND (-size))
10903 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
10905 GEN_INT (-size)))) = 1;
10908 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
10911 /* There are no instructions to add or subtract registers
10912 from the stack pointer, so use the frame pointer as a
10913 temporary. We should always be using a frame pointer
10914 in this case anyway. */
10915 gcc_assert (frame_pointer_needed);
10916 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
10917 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
10918 hard_frame_pointer_rtx,
10919 MIPS_PROLOGUE_TEMP (Pmode)));
10920 mips_emit_move (stack_pointer_rtx, hard_frame_pointer_rtx);
10923 emit_insn (gen_sub3_insn (stack_pointer_rtx,
10925 MIPS_PROLOGUE_TEMP (Pmode)));
10927 /* Describe the combined effect of the previous instructions. */
10928 mips_set_frame_expr
10929 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
10930 plus_constant (Pmode, stack_pointer_rtx, -size)));
10932 mips_frame_barrier ();
10935 /* Set up the frame pointer, if we're using one. */
10936 if (frame_pointer_needed)
10938 HOST_WIDE_INT offset;
10940 offset = frame->hard_frame_pointer_offset;
10943 insn = mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
10944 RTX_FRAME_RELATED_P (insn) = 1;
10946 else if (SMALL_OPERAND (offset))
10948 insn = gen_add3_insn (hard_frame_pointer_rtx,
10949 stack_pointer_rtx, GEN_INT (offset));
10950 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10954 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (offset));
10955 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
10956 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
10957 hard_frame_pointer_rtx,
10958 MIPS_PROLOGUE_TEMP (Pmode)));
10959 mips_set_frame_expr
10960 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
10961 plus_constant (Pmode, stack_pointer_rtx, offset)));
10965 mips_emit_loadgp ();
10967 /* Initialize the $gp save slot. */
10968 if (mips_cfun_has_cprestore_slot_p ())
10970 rtx base, mem, gp, temp;
10971 HOST_WIDE_INT offset;
10973 mips_get_cprestore_base_and_offset (&base, &offset, false);
10974 mem = gen_frame_mem (Pmode, plus_constant (Pmode, base, offset));
10975 gp = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
10976 temp = (SMALL_OPERAND (offset)
10977 ? gen_rtx_SCRATCH (Pmode)
10978 : MIPS_PROLOGUE_TEMP (Pmode));
10979 emit_insn (PMODE_INSN (gen_potential_cprestore,
10980 (mem, GEN_INT (offset), gp, temp)));
10982 mips_get_cprestore_base_and_offset (&base, &offset, true);
10983 mem = gen_frame_mem (Pmode, plus_constant (Pmode, base, offset));
10984 emit_insn (PMODE_INSN (gen_use_cprestore, (mem)));
10987 /* We need to search back to the last use of K0 or K1. */
10988 if (cfun->machine->interrupt_handler_p)
10990 for (insn = get_last_insn (); insn != NULL_RTX; insn = PREV_INSN (insn))
10992 && for_each_rtx (&PATTERN (insn), mips_kernel_reg_p, NULL))
10994 /* Emit a move from K1 to COP0 Status after insn. */
10995 gcc_assert (insn != NULL_RTX);
10996 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
10997 gen_rtx_REG (SImode, K1_REG_NUM)),
11001 /* If we are profiling, make sure no instructions are scheduled before
11002 the call to mcount. */
11004 emit_insn (gen_blockage ());
11007 /* Attach all pending register saves to the previous instruction.
11008 Return that instruction. */
11011 mips_epilogue_emit_cfa_restores (void)
11015 insn = get_last_insn ();
11016 gcc_assert (insn && !REG_NOTES (insn));
11017 if (mips_epilogue.cfa_restores)
11019 RTX_FRAME_RELATED_P (insn) = 1;
11020 REG_NOTES (insn) = mips_epilogue.cfa_restores;
11021 mips_epilogue.cfa_restores = 0;
11026 /* Like mips_epilogue_emit_cfa_restores, but also record that the CFA is
11027 now at REG + OFFSET. */
11030 mips_epilogue_set_cfa (rtx reg, HOST_WIDE_INT offset)
11034 insn = mips_epilogue_emit_cfa_restores ();
11035 if (reg != mips_epilogue.cfa_reg || offset != mips_epilogue.cfa_offset)
11037 RTX_FRAME_RELATED_P (insn) = 1;
11038 REG_NOTES (insn) = alloc_reg_note (REG_CFA_DEF_CFA,
11039 plus_constant (Pmode, reg, offset),
11041 mips_epilogue.cfa_reg = reg;
11042 mips_epilogue.cfa_offset = offset;
11046 /* Emit instructions to restore register REG from slot MEM. Also update
11047 the cfa_restores list. */
11050 mips_restore_reg (rtx reg, rtx mem)
11052 /* There's no MIPS16 instruction to load $31 directly. Load into
11053 $7 instead and adjust the return insn appropriately. */
11054 if (TARGET_MIPS16 && REGNO (reg) == RETURN_ADDR_REGNUM)
11055 reg = gen_rtx_REG (GET_MODE (reg), GP_REG_FIRST + 7);
11056 else if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
11058 mips_add_cfa_restore (mips_subword (reg, true));
11059 mips_add_cfa_restore (mips_subword (reg, false));
11062 mips_add_cfa_restore (reg);
11064 mips_emit_save_slot_move (reg, mem, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
11065 if (REGNO (reg) == REGNO (mips_epilogue.cfa_reg))
11066 /* The CFA is currently defined in terms of the register whose
11067 value we have just restored. Redefine the CFA in terms of
11068 the stack pointer. */
11069 mips_epilogue_set_cfa (stack_pointer_rtx,
11070 mips_epilogue.cfa_restore_sp_offset);
11073 /* Emit code to set the stack pointer to BASE + OFFSET, given that
11074 BASE + OFFSET is NEW_FRAME_SIZE bytes below the top of the frame.
11075 BASE, if not the stack pointer, is available as a temporary. */
11078 mips_deallocate_stack (rtx base, rtx offset, HOST_WIDE_INT new_frame_size)
11080 if (base == stack_pointer_rtx && offset == const0_rtx)
11083 mips_frame_barrier ();
11084 if (offset == const0_rtx)
11086 emit_move_insn (stack_pointer_rtx, base);
11087 mips_epilogue_set_cfa (stack_pointer_rtx, new_frame_size);
11089 else if (TARGET_MIPS16 && base != stack_pointer_rtx)
11091 emit_insn (gen_add3_insn (base, base, offset));
11092 mips_epilogue_set_cfa (base, new_frame_size);
11093 emit_move_insn (stack_pointer_rtx, base);
11097 emit_insn (gen_add3_insn (stack_pointer_rtx, base, offset));
11098 mips_epilogue_set_cfa (stack_pointer_rtx, new_frame_size);
11102 /* Emit any instructions needed before a return. */
11105 mips_expand_before_return (void)
11107 /* When using a call-clobbered gp, we start out with unified call
11108 insns that include instructions to restore the gp. We then split
11109 these unified calls after reload. These split calls explicitly
11110 clobber gp, so there is no need to define
11111 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
11113 For consistency, we should also insert an explicit clobber of $28
11114 before return insns, so that the post-reload optimizers know that
11115 the register is not live on exit. */
11116 if (TARGET_CALL_CLOBBERED_GP)
11117 emit_clobber (pic_offset_table_rtx);
11120 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
11124 mips_expand_epilogue (bool sibcall_p)
11126 const struct mips_frame_info *frame;
11127 HOST_WIDE_INT step1, step2;
11128 rtx base, adjust, insn;
11130 if (!sibcall_p && mips_can_use_return_insn ())
11132 emit_jump_insn (gen_return ());
11136 /* In MIPS16 mode, if the return value should go into a floating-point
11137 register, we need to call a helper routine to copy it over. */
11138 if (mips16_cfun_returns_in_fpr_p ())
11139 mips16_copy_fpr_return_value ();
11141 /* Split the frame into two. STEP1 is the amount of stack we should
11142 deallocate before restoring the registers. STEP2 is the amount we
11143 should deallocate afterwards.
11145 Start off by assuming that no registers need to be restored. */
11146 frame = &cfun->machine->frame;
11147 step1 = frame->total_size;
11150 /* Work out which register holds the frame address. */
11151 if (!frame_pointer_needed)
11152 base = stack_pointer_rtx;
11155 base = hard_frame_pointer_rtx;
11156 step1 -= frame->hard_frame_pointer_offset;
11158 mips_epilogue.cfa_reg = base;
11159 mips_epilogue.cfa_offset = step1;
11160 mips_epilogue.cfa_restores = NULL_RTX;
11162 /* If we need to restore registers, deallocate as much stack as
11163 possible in the second step without going out of range. */
11164 if ((frame->mask | frame->fmask | frame->acc_mask) != 0
11165 || frame->num_cop0_regs > 0)
11167 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
11171 /* Get an rtx for STEP1 that we can add to BASE. */
11172 adjust = GEN_INT (step1);
11173 if (!SMALL_OPERAND (step1))
11175 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), adjust);
11176 adjust = MIPS_EPILOGUE_TEMP (Pmode);
11178 mips_deallocate_stack (base, adjust, step2);
11180 /* If we're using addressing macros, $gp is implicitly used by all
11181 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
11183 if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS)
11184 emit_insn (gen_blockage ());
11186 mips_epilogue.cfa_restore_sp_offset = step2;
11187 if (GENERATE_MIPS16E_SAVE_RESTORE && frame->mask != 0)
11189 unsigned int regno, mask;
11190 HOST_WIDE_INT offset;
11193 /* Generate the restore instruction. */
11194 mask = frame->mask;
11195 restore = mips16e_build_save_restore (true, &mask, &offset, 0, step2);
11197 /* Restore any other registers manually. */
11198 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
11199 if (BITSET_P (mask, regno - GP_REG_FIRST))
11201 offset -= UNITS_PER_WORD;
11202 mips_save_restore_reg (word_mode, regno, offset, mips_restore_reg);
11205 /* Restore the remaining registers and deallocate the final bit
11207 mips_frame_barrier ();
11208 emit_insn (restore);
11209 mips_epilogue_set_cfa (stack_pointer_rtx, 0);
11213 /* Restore the registers. */
11214 mips_for_each_saved_acc (frame->total_size - step2, mips_restore_reg);
11215 mips_for_each_saved_gpr_and_fpr (frame->total_size - step2,
11218 if (cfun->machine->interrupt_handler_p)
11220 HOST_WIDE_INT offset;
11223 offset = frame->cop0_sp_offset - (frame->total_size - step2);
11224 if (!cfun->machine->keep_interrupts_masked_p)
11226 /* Restore the original EPC. */
11227 mem = gen_frame_mem (word_mode,
11228 plus_constant (Pmode, stack_pointer_rtx,
11230 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
11231 offset -= UNITS_PER_WORD;
11233 /* Move to COP0 EPC. */
11234 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_EPC_REG_NUM),
11235 gen_rtx_REG (SImode, K0_REG_NUM)));
11238 /* Restore the original Status. */
11239 mem = gen_frame_mem (word_mode,
11240 plus_constant (Pmode, stack_pointer_rtx,
11242 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
11243 offset -= UNITS_PER_WORD;
11245 /* If we don't use shoadow register set, we need to update SP. */
11246 if (!cfun->machine->use_shadow_register_set_p)
11247 mips_deallocate_stack (stack_pointer_rtx, GEN_INT (step2), 0);
11249 /* The choice of position is somewhat arbitrary in this case. */
11250 mips_epilogue_emit_cfa_restores ();
11252 /* Move to COP0 Status. */
11253 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
11254 gen_rtx_REG (SImode, K0_REG_NUM)));
11257 /* Deallocate the final bit of the frame. */
11258 mips_deallocate_stack (stack_pointer_rtx, GEN_INT (step2), 0);
11260 gcc_assert (!mips_epilogue.cfa_restores);
11262 /* Add in the __builtin_eh_return stack adjustment. We need to
11263 use a temporary in MIPS16 code. */
11264 if (crtl->calls_eh_return)
11268 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
11269 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
11270 MIPS_EPILOGUE_TEMP (Pmode),
11271 EH_RETURN_STACKADJ_RTX));
11272 mips_emit_move (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
11275 emit_insn (gen_add3_insn (stack_pointer_rtx,
11277 EH_RETURN_STACKADJ_RTX));
11282 mips_expand_before_return ();
11283 if (cfun->machine->interrupt_handler_p)
11285 /* Interrupt handlers generate eret or deret. */
11286 if (cfun->machine->use_debug_exception_return_p)
11287 emit_jump_insn (gen_mips_deret ());
11289 emit_jump_insn (gen_mips_eret ());
11295 /* When generating MIPS16 code, the normal
11296 mips_for_each_saved_gpr_and_fpr path will restore the return
11297 address into $7 rather than $31. */
11299 && !GENERATE_MIPS16E_SAVE_RESTORE
11300 && BITSET_P (frame->mask, RETURN_ADDR_REGNUM))
11302 /* simple_returns cannot rely on values that are only available
11303 on paths through the epilogue (because return paths that do
11304 not pass through the epilogue may nevertheless reuse a
11305 simple_return that occurs at the end of the epilogue).
11306 Use a normal return here instead. */
11307 rtx reg = gen_rtx_REG (Pmode, GP_REG_FIRST + 7);
11308 pat = gen_return_internal (reg);
11312 rtx reg = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
11313 pat = gen_simple_return_internal (reg);
11315 emit_jump_insn (pat);
11319 /* Search from the beginning to the first use of K0 or K1. */
11320 if (cfun->machine->interrupt_handler_p
11321 && !cfun->machine->keep_interrupts_masked_p)
11323 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
11325 && for_each_rtx (&PATTERN(insn), mips_kernel_reg_p, NULL))
11327 gcc_assert (insn != NULL_RTX);
11328 /* Insert disable interrupts before the first use of K0 or K1. */
11329 emit_insn_before (gen_mips_di (), insn);
11330 emit_insn_before (gen_mips_ehb (), insn);
11334 /* Return nonzero if this function is known to have a null epilogue.
11335 This allows the optimizer to omit jumps to jumps if no stack
11339 mips_can_use_return_insn (void)
11341 /* Interrupt handlers need to go through the epilogue. */
11342 if (cfun->machine->interrupt_handler_p)
11345 if (!reload_completed)
11351 /* In MIPS16 mode, a function that returns a floating-point value
11352 needs to arrange to copy the return value into the floating-point
11354 if (mips16_cfun_returns_in_fpr_p ())
11357 return cfun->machine->frame.total_size == 0;
11360 /* Return true if register REGNO can store a value of mode MODE.
11361 The result of this function is cached in mips_hard_regno_mode_ok. */
11364 mips_hard_regno_mode_ok_p (unsigned int regno, enum machine_mode mode)
11367 enum mode_class mclass;
11369 if (mode == CCV2mode)
11370 return (ISA_HAS_8CC
11371 && ST_REG_P (regno)
11372 && (regno - ST_REG_FIRST) % 2 == 0);
11374 if (mode == CCV4mode)
11375 return (ISA_HAS_8CC
11376 && ST_REG_P (regno)
11377 && (regno - ST_REG_FIRST) % 4 == 0);
11379 if (mode == CCmode)
11380 return ISA_HAS_8CC ? ST_REG_P (regno) : regno == FPSW_REGNUM;
11382 size = GET_MODE_SIZE (mode);
11383 mclass = GET_MODE_CLASS (mode);
11385 if (GP_REG_P (regno))
11386 return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD;
11388 if (FP_REG_P (regno)
11389 && (((regno - FP_REG_FIRST) % MAX_FPRS_PER_FMT) == 0
11390 || (MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG)))
11392 /* Allow 64-bit vector modes for Loongson-2E/2F. */
11393 if (TARGET_LOONGSON_VECTORS
11394 && (mode == V2SImode
11395 || mode == V4HImode
11396 || mode == V8QImode
11397 || mode == DImode))
11400 if (mclass == MODE_FLOAT
11401 || mclass == MODE_COMPLEX_FLOAT
11402 || mclass == MODE_VECTOR_FLOAT)
11403 return size <= UNITS_PER_FPVALUE;
11405 /* Allow integer modes that fit into a single register. We need
11406 to put integers into FPRs when using instructions like CVT
11407 and TRUNC. There's no point allowing sizes smaller than a word,
11408 because the FPU has no appropriate load/store instructions. */
11409 if (mclass == MODE_INT)
11410 return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG;
11413 if (ACC_REG_P (regno)
11414 && (INTEGRAL_MODE_P (mode) || ALL_FIXED_POINT_MODE_P (mode)))
11416 if (MD_REG_P (regno))
11418 /* After a multiplication or division, clobbering HI makes
11419 the value of LO unpredictable, and vice versa. This means
11420 that, for all interesting cases, HI and LO are effectively
11423 We model this by requiring that any value that uses HI
11425 if (size <= UNITS_PER_WORD * 2)
11426 return regno == (size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST);
11430 /* DSP accumulators do not have the same restrictions as
11431 HI and LO, so we can treat them as normal doubleword
11433 if (size <= UNITS_PER_WORD)
11436 if (size <= UNITS_PER_WORD * 2
11437 && ((regno - DSP_ACC_REG_FIRST) & 1) == 0)
11442 if (ALL_COP_REG_P (regno))
11443 return mclass == MODE_INT && size <= UNITS_PER_WORD;
11445 if (regno == GOT_VERSION_REGNUM)
11446 return mode == SImode;
11451 /* Implement HARD_REGNO_NREGS. */
11454 mips_hard_regno_nregs (int regno, enum machine_mode mode)
11456 if (ST_REG_P (regno))
11457 /* The size of FP status registers is always 4, because they only hold
11458 CCmode values, and CCmode is always considered to be 4 bytes wide. */
11459 return (GET_MODE_SIZE (mode) + 3) / 4;
11461 if (FP_REG_P (regno))
11462 return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG;
11464 /* All other registers are word-sized. */
11465 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
11468 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
11469 in mips_hard_regno_nregs. */
11472 mips_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
11478 COPY_HARD_REG_SET (left, reg_class_contents[(int) rclass]);
11479 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS]))
11481 if (HARD_REGNO_MODE_OK (ST_REG_FIRST, mode))
11482 size = MIN (size, 4);
11483 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) ST_REGS]);
11485 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS]))
11487 if (HARD_REGNO_MODE_OK (FP_REG_FIRST, mode))
11488 size = MIN (size, UNITS_PER_FPREG);
11489 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]);
11491 if (!hard_reg_set_empty_p (left))
11492 size = MIN (size, UNITS_PER_WORD);
11493 return (GET_MODE_SIZE (mode) + size - 1) / size;
11496 /* Implement CANNOT_CHANGE_MODE_CLASS. */
11499 mips_cannot_change_mode_class (enum machine_mode from,
11500 enum machine_mode to,
11501 enum reg_class rclass)
11503 /* Allow conversions between different Loongson integer vectors,
11504 and between those vectors and DImode. */
11505 if (GET_MODE_SIZE (from) == 8 && GET_MODE_SIZE (to) == 8
11506 && INTEGRAL_MODE_P (from) && INTEGRAL_MODE_P (to))
11509 /* Otherwise, there are several problems with changing the modes of
11510 values in floating-point registers:
11512 - When a multi-word value is stored in paired floating-point
11513 registers, the first register always holds the low word. We
11514 therefore can't allow FPRs to change between single-word and
11515 multi-word modes on big-endian targets.
11517 - GCC assumes that each word of a multiword register can be
11518 accessed individually using SUBREGs. This is not true for
11519 floating-point registers if they are bigger than a word.
11521 - Loading a 32-bit value into a 64-bit floating-point register
11522 will not sign-extend the value, despite what LOAD_EXTEND_OP
11523 says. We can't allow FPRs to change from SImode to a wider
11524 mode on 64-bit targets.
11526 - If the FPU has already interpreted a value in one format, we
11527 must not ask it to treat the value as having a different
11530 We therefore disallow all mode changes involving FPRs. */
11532 return reg_classes_intersect_p (FP_REGS, rclass);
11535 /* Implement target hook small_register_classes_for_mode_p. */
11538 mips_small_register_classes_for_mode_p (enum machine_mode mode
11541 return TARGET_MIPS16;
11544 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
11547 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode)
11552 return TARGET_HARD_FLOAT;
11555 return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT;
11558 return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT;
11565 /* Implement MODES_TIEABLE_P. */
11568 mips_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
11570 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
11571 prefer to put one of them in FPRs. */
11572 return (mode1 == mode2
11573 || (!mips_mode_ok_for_mov_fmt_p (mode1)
11574 && !mips_mode_ok_for_mov_fmt_p (mode2)));
11577 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
11580 mips_preferred_reload_class (rtx x, reg_class_t rclass)
11582 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, rclass))
11585 if (reg_class_subset_p (FP_REGS, rclass)
11586 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x)))
11589 if (reg_class_subset_p (GR_REGS, rclass))
11592 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, rclass))
11598 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
11599 Return a "canonical" class to represent it in later calculations. */
11602 mips_canonicalize_move_class (reg_class_t rclass)
11604 /* All moves involving accumulator registers have the same cost. */
11605 if (reg_class_subset_p (rclass, ACC_REGS))
11608 /* Likewise promote subclasses of general registers to the most
11609 interesting containing class. */
11610 if (TARGET_MIPS16 && reg_class_subset_p (rclass, M16_REGS))
11612 else if (reg_class_subset_p (rclass, GENERAL_REGS))
11613 rclass = GENERAL_REGS;
11618 /* Return the cost of moving a value of mode MODE from a register of
11619 class FROM to a GPR. Return 0 for classes that are unions of other
11620 classes handled by this function. */
11623 mips_move_to_gpr_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
11629 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
11633 /* MFLO and MFHI. */
11641 /* LUI followed by MOVF. */
11647 /* This choice of value is historical. */
11655 /* Return the cost of moving a value of mode MODE from a GPR to a
11656 register of class TO. Return 0 for classes that are unions of
11657 other classes handled by this function. */
11660 mips_move_from_gpr_cost (enum machine_mode mode, reg_class_t to)
11665 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
11669 /* MTLO and MTHI. */
11677 /* A secondary reload through an FPR scratch. */
11678 return (mips_register_move_cost (mode, GENERAL_REGS, FP_REGS)
11679 + mips_register_move_cost (mode, FP_REGS, ST_REGS));
11684 /* This choice of value is historical. */
11692 /* Implement TARGET_REGISTER_MOVE_COST. Return 0 for classes that are the
11693 maximum of the move costs for subclasses; regclass will work out
11694 the maximum for us. */
11697 mips_register_move_cost (enum machine_mode mode,
11698 reg_class_t from, reg_class_t to)
11703 from = mips_canonicalize_move_class (from);
11704 to = mips_canonicalize_move_class (to);
11706 /* Handle moves that can be done without using general-purpose registers. */
11707 if (from == FP_REGS)
11709 if (to == FP_REGS && mips_mode_ok_for_mov_fmt_p (mode))
11713 /* The sequence generated by mips_expand_fcc_reload. */
11717 /* Handle cases in which only one class deviates from the ideal. */
11718 dregs = TARGET_MIPS16 ? M16_REGS : GENERAL_REGS;
11720 return mips_move_from_gpr_cost (mode, to);
11722 return mips_move_to_gpr_cost (mode, from);
11724 /* Handles cases that require a GPR temporary. */
11725 cost1 = mips_move_to_gpr_cost (mode, from);
11728 cost2 = mips_move_from_gpr_cost (mode, to);
11730 return cost1 + cost2;
11736 /* Implement TARGET_MEMORY_MOVE_COST. */
11739 mips_memory_move_cost (enum machine_mode mode, reg_class_t rclass, bool in)
11741 return (mips_cost->memory_latency
11742 + memory_move_secondary_cost (mode, rclass, in));
11745 /* Return the register class required for a secondary register when
11746 copying between one of the registers in RCLASS and value X, which
11747 has mode MODE. X is the source of the move if IN_P, otherwise it
11748 is the destination. Return NO_REGS if no secondary register is
11752 mips_secondary_reload_class (enum reg_class rclass,
11753 enum machine_mode mode, rtx x, bool in_p)
11757 /* If X is a constant that cannot be loaded into $25, it must be loaded
11758 into some other GPR. No other register class allows a direct move. */
11759 if (mips_dangerous_for_la25_p (x))
11760 return reg_class_subset_p (rclass, LEA_REGS) ? NO_REGS : LEA_REGS;
11762 regno = true_regnum (x);
11765 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
11766 if (!reg_class_subset_p (rclass, M16_REGS) && !M16_REG_P (regno))
11772 /* Copying from accumulator registers to anywhere other than a general
11773 register requires a temporary general register. */
11774 if (reg_class_subset_p (rclass, ACC_REGS))
11775 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
11776 if (ACC_REG_P (regno))
11777 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
11779 /* We can only copy a value to a condition code register from a
11780 floating-point register, and even then we require a scratch
11781 floating-point register. We can only copy a value out of a
11782 condition-code register into a general register. */
11783 if (reg_class_subset_p (rclass, ST_REGS))
11787 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
11789 if (ST_REG_P (regno))
11793 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
11796 if (reg_class_subset_p (rclass, FP_REGS))
11799 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8))
11800 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
11801 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
11804 if (GP_REG_P (regno) || x == CONST0_RTX (mode))
11805 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
11808 if (CONSTANT_P (x) && !targetm.cannot_force_const_mem (mode, x))
11809 /* We can force the constant to memory and use lwc1
11810 and ldc1. As above, we will use pairs of lwc1s if
11811 ldc1 is not supported. */
11814 if (FP_REG_P (regno) && mips_mode_ok_for_mov_fmt_p (mode))
11815 /* In this case we can use mov.fmt. */
11818 /* Otherwise, we need to reload through an integer register. */
11821 if (FP_REG_P (regno))
11822 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
11827 /* Implement TARGET_MODE_REP_EXTENDED. */
11830 mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
11832 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
11833 if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
11834 return SIGN_EXTEND;
11839 /* Implement TARGET_VALID_POINTER_MODE. */
11842 mips_valid_pointer_mode (enum machine_mode mode)
11844 return mode == SImode || (TARGET_64BIT && mode == DImode);
11847 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
11850 mips_vector_mode_supported_p (enum machine_mode mode)
11855 return TARGET_PAIRED_SINGLE_FLOAT;
11870 return TARGET_LOONGSON_VECTORS;
11877 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
11880 mips_scalar_mode_supported_p (enum machine_mode mode)
11882 if (ALL_FIXED_POINT_MODE_P (mode)
11883 && GET_MODE_PRECISION (mode) <= 2 * BITS_PER_WORD)
11886 return default_scalar_mode_supported_p (mode);
11889 /* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
11891 static enum machine_mode
11892 mips_preferred_simd_mode (enum machine_mode mode ATTRIBUTE_UNUSED)
11894 if (TARGET_PAIRED_SINGLE_FLOAT
11900 /* Implement TARGET_INIT_LIBFUNCS. */
11903 mips_init_libfuncs (void)
11905 if (TARGET_FIX_VR4120)
11907 /* Register the special divsi3 and modsi3 functions needed to work
11908 around VR4120 division errata. */
11909 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
11910 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
11913 if (TARGET_MIPS16 && TARGET_HARD_FLOAT_ABI)
11915 /* Register the MIPS16 -mhard-float stubs. */
11916 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
11917 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
11918 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
11919 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
11921 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
11922 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
11923 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
11924 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
11925 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
11926 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
11927 set_optab_libfunc (unord_optab, SFmode, "__mips16_unordsf2");
11929 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
11930 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
11931 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__mips16_floatunsisf");
11933 if (TARGET_DOUBLE_FLOAT)
11935 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
11936 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
11937 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
11938 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
11940 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
11941 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
11942 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
11943 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
11944 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
11945 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
11946 set_optab_libfunc (unord_optab, DFmode, "__mips16_unorddf2");
11948 set_conv_libfunc (sext_optab, DFmode, SFmode,
11949 "__mips16_extendsfdf2");
11950 set_conv_libfunc (trunc_optab, SFmode, DFmode,
11951 "__mips16_truncdfsf2");
11952 set_conv_libfunc (sfix_optab, SImode, DFmode,
11953 "__mips16_fix_truncdfsi");
11954 set_conv_libfunc (sfloat_optab, DFmode, SImode,
11955 "__mips16_floatsidf");
11956 set_conv_libfunc (ufloat_optab, DFmode, SImode,
11957 "__mips16_floatunsidf");
11961 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
11962 on an external non-MIPS16 routine to implement __sync_synchronize.
11963 Similarly for the rest of the ll/sc libfuncs. */
11966 synchronize_libfunc = init_one_libfunc ("__sync_synchronize");
11967 init_sync_libfuncs (UNITS_PER_WORD);
11971 /* Build up a multi-insn sequence that loads label TARGET into $AT. */
11974 mips_process_load_label (rtx target)
11976 rtx base, gp, intop;
11977 HOST_WIDE_INT offset;
11979 mips_multi_start ();
11983 mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target, 0);
11984 mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target, 0);
11988 mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target, 0);
11989 mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target, 0);
11993 gp = pic_offset_table_rtx;
11994 if (mips_cfun_has_cprestore_slot_p ())
11996 gp = gen_rtx_REG (Pmode, AT_REGNUM);
11997 mips_get_cprestore_base_and_offset (&base, &offset, true);
11998 if (!SMALL_OPERAND (offset))
12000 intop = GEN_INT (CONST_HIGH_PART (offset));
12001 mips_multi_add_insn ("lui\t%0,%1", gp, intop, 0);
12002 mips_multi_add_insn ("addu\t%0,%0,%1", gp, base, 0);
12005 offset = CONST_LOW_PART (offset);
12007 intop = GEN_INT (offset);
12008 if (ISA_HAS_LOAD_DELAY)
12009 mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp, intop, base, 0);
12011 mips_multi_add_insn ("lw\t%0,%1(%2)", gp, intop, base, 0);
12013 if (ISA_HAS_LOAD_DELAY)
12014 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target, gp, 0);
12016 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target, gp, 0);
12017 mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target, 0);
12022 /* Return the number of instructions needed to load a label into $AT. */
12024 static unsigned int
12025 mips_load_label_num_insns (void)
12027 if (cfun->machine->load_label_num_insns == 0)
12029 mips_process_load_label (pc_rtx);
12030 cfun->machine->load_label_num_insns = mips_multi_num_insns;
12032 return cfun->machine->load_label_num_insns;
12035 /* Emit an asm sequence to start a noat block and load the address
12036 of a label into $1. */
12039 mips_output_load_label (rtx target)
12041 mips_push_asm_switch (&mips_noat);
12042 if (TARGET_EXPLICIT_RELOCS)
12044 mips_process_load_label (target);
12045 mips_multi_write ();
12049 if (Pmode == DImode)
12050 output_asm_insn ("dla\t%@,%0", &target);
12052 output_asm_insn ("la\t%@,%0", &target);
12056 /* Return the length of INSN. LENGTH is the initial length computed by
12057 attributes in the machine-description file. */
12060 mips_adjust_insn_length (rtx insn, int length)
12062 /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length
12063 of a PIC long-branch sequence. Substitute the correct value. */
12064 if (length == MAX_PIC_BRANCH_LENGTH
12065 && INSN_CODE (insn) >= 0
12066 && get_attr_type (insn) == TYPE_BRANCH)
12068 /* Add the branch-over instruction and its delay slot, if this
12069 is a conditional branch. */
12070 length = simplejump_p (insn) ? 0 : 8;
12072 /* Load the label into $AT and jump to it. Ignore the delay
12073 slot of the jump. */
12074 length += 4 * mips_load_label_num_insns() + 4;
12077 /* A unconditional jump has an unfilled delay slot if it is not part
12078 of a sequence. A conditional jump normally has a delay slot, but
12079 does not on MIPS16. */
12080 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
12083 /* See how many nops might be needed to avoid hardware hazards. */
12084 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
12085 switch (get_attr_hazard (insn))
12099 /* In order to make it easier to share MIPS16 and non-MIPS16 patterns,
12100 the .md file length attributes are 4-based for both modes.
12101 Adjust the MIPS16 ones here. */
12108 /* Return the assembly code for INSN, which has the operands given by
12109 OPERANDS, and which branches to OPERANDS[0] if some condition is true.
12110 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0]
12111 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
12112 version of BRANCH_IF_TRUE. */
12115 mips_output_conditional_branch (rtx insn, rtx *operands,
12116 const char *branch_if_true,
12117 const char *branch_if_false)
12119 unsigned int length;
12120 rtx taken, not_taken;
12122 gcc_assert (LABEL_P (operands[0]));
12124 length = get_attr_length (insn);
12127 /* Just a simple conditional branch. */
12128 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
12129 return branch_if_true;
12132 /* Generate a reversed branch around a direct jump. This fallback does
12133 not use branch-likely instructions. */
12134 mips_branch_likely = false;
12135 not_taken = gen_label_rtx ();
12136 taken = operands[0];
12138 /* Generate the reversed branch to NOT_TAKEN. */
12139 operands[0] = not_taken;
12140 output_asm_insn (branch_if_false, operands);
12142 /* If INSN has a delay slot, we must provide delay slots for both the
12143 branch to NOT_TAKEN and the conditional jump. We must also ensure
12144 that INSN's delay slot is executed in the appropriate cases. */
12145 if (final_sequence)
12147 /* This first delay slot will always be executed, so use INSN's
12148 delay slot if is not annulled. */
12149 if (!INSN_ANNULLED_BRANCH_P (insn))
12151 final_scan_insn (XVECEXP (final_sequence, 0, 1),
12152 asm_out_file, optimize, 1, NULL);
12153 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
12156 output_asm_insn ("nop", 0);
12157 fprintf (asm_out_file, "\n");
12160 /* Output the unconditional branch to TAKEN. */
12161 if (TARGET_ABSOLUTE_JUMPS)
12162 output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken);
12165 mips_output_load_label (taken);
12166 output_asm_insn ("jr\t%@%]%/", 0);
12169 /* Now deal with its delay slot; see above. */
12170 if (final_sequence)
12172 /* This delay slot will only be executed if the branch is taken.
12173 Use INSN's delay slot if is annulled. */
12174 if (INSN_ANNULLED_BRANCH_P (insn))
12176 final_scan_insn (XVECEXP (final_sequence, 0, 1),
12177 asm_out_file, optimize, 1, NULL);
12178 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
12181 output_asm_insn ("nop", 0);
12182 fprintf (asm_out_file, "\n");
12185 /* Output NOT_TAKEN. */
12186 targetm.asm_out.internal_label (asm_out_file, "L",
12187 CODE_LABEL_NUMBER (not_taken));
12191 /* Return the assembly code for INSN, which branches to OPERANDS[0]
12192 if some ordering condition is true. The condition is given by
12193 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
12194 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
12195 its second is always zero. */
12198 mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
12200 const char *branch[2];
12202 /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true.
12203 Make BRANCH[0] branch on the inverse condition. */
12204 switch (GET_CODE (operands[1]))
12206 /* These cases are equivalent to comparisons against zero. */
12208 inverted_p = !inverted_p;
12209 /* Fall through. */
12211 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%0");
12212 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%0");
12215 /* These cases are always true or always false. */
12217 inverted_p = !inverted_p;
12218 /* Fall through. */
12220 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%0");
12221 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%0");
12225 branch[!inverted_p] = MIPS_BRANCH ("b%C1z", "%2,%0");
12226 branch[inverted_p] = MIPS_BRANCH ("b%N1z", "%2,%0");
12229 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
12232 /* Start a block of code that needs access to the LL, SC and SYNC
12236 mips_start_ll_sc_sync_block (void)
12238 if (!ISA_HAS_LL_SC)
12240 output_asm_insn (".set\tpush", 0);
12241 output_asm_insn (".set\tmips2", 0);
12245 /* End a block started by mips_start_ll_sc_sync_block. */
12248 mips_end_ll_sc_sync_block (void)
12250 if (!ISA_HAS_LL_SC)
12251 output_asm_insn (".set\tpop", 0);
12254 /* Output and/or return the asm template for a sync instruction. */
12257 mips_output_sync (void)
12259 mips_start_ll_sc_sync_block ();
12260 output_asm_insn ("sync", 0);
12261 mips_end_ll_sc_sync_block ();
12265 /* Return the asm template associated with sync_insn1 value TYPE.
12266 IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */
12268 static const char *
12269 mips_sync_insn1_template (enum attr_sync_insn1 type, bool is_64bit_p)
12273 case SYNC_INSN1_MOVE:
12274 return "move\t%0,%z2";
12275 case SYNC_INSN1_LI:
12276 return "li\t%0,%2";
12277 case SYNC_INSN1_ADDU:
12278 return is_64bit_p ? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2";
12279 case SYNC_INSN1_ADDIU:
12280 return is_64bit_p ? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2";
12281 case SYNC_INSN1_SUBU:
12282 return is_64bit_p ? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2";
12283 case SYNC_INSN1_AND:
12284 return "and\t%0,%1,%z2";
12285 case SYNC_INSN1_ANDI:
12286 return "andi\t%0,%1,%2";
12287 case SYNC_INSN1_OR:
12288 return "or\t%0,%1,%z2";
12289 case SYNC_INSN1_ORI:
12290 return "ori\t%0,%1,%2";
12291 case SYNC_INSN1_XOR:
12292 return "xor\t%0,%1,%z2";
12293 case SYNC_INSN1_XORI:
12294 return "xori\t%0,%1,%2";
12296 gcc_unreachable ();
12299 /* Return the asm template associated with sync_insn2 value TYPE. */
12301 static const char *
12302 mips_sync_insn2_template (enum attr_sync_insn2 type)
12306 case SYNC_INSN2_NOP:
12307 gcc_unreachable ();
12308 case SYNC_INSN2_AND:
12309 return "and\t%0,%1,%z2";
12310 case SYNC_INSN2_XOR:
12311 return "xor\t%0,%1,%z2";
12312 case SYNC_INSN2_NOT:
12313 return "nor\t%0,%1,%.";
12315 gcc_unreachable ();
12318 /* OPERANDS are the operands to a sync loop instruction and INDEX is
12319 the value of the one of the sync_* attributes. Return the operand
12320 referred to by the attribute, or DEFAULT_VALUE if the insn doesn't
12321 have the associated attribute. */
12324 mips_get_sync_operand (rtx *operands, int index, rtx default_value)
12327 default_value = operands[index - 1];
12328 return default_value;
12331 /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn
12332 sequence for it. */
12335 mips_process_sync_loop (rtx insn, rtx *operands)
12337 rtx at, mem, oldval, newval, inclusive_mask, exclusive_mask;
12338 rtx required_oldval, insn1_op2, tmp1, tmp2, tmp3, cmp;
12339 unsigned int tmp3_insn;
12340 enum attr_sync_insn1 insn1;
12341 enum attr_sync_insn2 insn2;
12344 enum memmodel model;
12346 /* Read an operand from the sync_WHAT attribute and store it in
12347 variable WHAT. DEFAULT is the default value if no attribute
12349 #define READ_OPERAND(WHAT, DEFAULT) \
12350 WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \
12353 /* Read the memory. */
12354 READ_OPERAND (mem, 0);
12356 is_64bit_p = (GET_MODE_BITSIZE (GET_MODE (mem)) == 64);
12358 /* Read the other attributes. */
12359 at = gen_rtx_REG (GET_MODE (mem), AT_REGNUM);
12360 READ_OPERAND (oldval, at);
12361 READ_OPERAND (cmp, 0);
12362 READ_OPERAND (newval, at);
12363 READ_OPERAND (inclusive_mask, 0);
12364 READ_OPERAND (exclusive_mask, 0);
12365 READ_OPERAND (required_oldval, 0);
12366 READ_OPERAND (insn1_op2, 0);
12367 insn1 = get_attr_sync_insn1 (insn);
12368 insn2 = get_attr_sync_insn2 (insn);
12370 /* Don't bother setting CMP result that is never used. */
12371 if (cmp && find_reg_note (insn, REG_UNUSED, cmp))
12374 memmodel_attr = get_attr_sync_memmodel (insn);
12375 switch (memmodel_attr)
12378 model = MEMMODEL_ACQ_REL;
12381 model = MEMMODEL_ACQUIRE;
12384 model = (enum memmodel) INTVAL (operands[memmodel_attr]);
12387 mips_multi_start ();
12389 /* Output the release side of the memory barrier. */
12390 if (need_atomic_barrier_p (model, true))
12392 if (required_oldval == 0 && TARGET_OCTEON)
12394 /* Octeon doesn't reorder reads, so a full barrier can be
12395 created by using SYNCW to order writes combined with the
12396 write from the following SC. When the SC successfully
12397 completes, we know that all preceding writes are also
12398 committed to the coherent memory system. It is possible
12399 for a single SYNCW to fail, but a pair of them will never
12400 fail, so we use two. */
12401 mips_multi_add_insn ("syncw", NULL);
12402 mips_multi_add_insn ("syncw", NULL);
12405 mips_multi_add_insn ("sync", NULL);
12408 /* Output the branch-back label. */
12409 mips_multi_add_label ("1:");
12411 /* OLDVAL = *MEM. */
12412 mips_multi_add_insn (is_64bit_p ? "lld\t%0,%1" : "ll\t%0,%1",
12413 oldval, mem, NULL);
12415 /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */
12416 if (required_oldval)
12418 if (inclusive_mask == 0)
12422 gcc_assert (oldval != at);
12423 mips_multi_add_insn ("and\t%0,%1,%2",
12424 at, oldval, inclusive_mask, NULL);
12427 mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1, required_oldval, NULL);
12429 /* CMP = 0 [delay slot]. */
12431 mips_multi_add_insn ("li\t%0,0", cmp, NULL);
12434 /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */
12435 if (exclusive_mask == 0)
12439 gcc_assert (oldval != at);
12440 mips_multi_add_insn ("and\t%0,%1,%z2",
12441 at, oldval, exclusive_mask, NULL);
12445 /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2).
12447 We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit
12448 at least one instruction in that case. */
12449 if (insn1 == SYNC_INSN1_MOVE
12450 && (tmp1 != const0_rtx || insn2 != SYNC_INSN2_NOP))
12454 mips_multi_add_insn (mips_sync_insn1_template (insn1, is_64bit_p),
12455 newval, oldval, insn1_op2, NULL);
12459 /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */
12460 if (insn2 == SYNC_INSN2_NOP)
12464 mips_multi_add_insn (mips_sync_insn2_template (insn2),
12465 newval, tmp2, inclusive_mask, NULL);
12468 tmp3_insn = mips_multi_last_index ();
12470 /* $AT = $TMP1 | $TMP3. */
12471 if (tmp1 == const0_rtx || tmp3 == const0_rtx)
12473 mips_multi_set_operand (tmp3_insn, 0, at);
12478 gcc_assert (tmp1 != tmp3);
12479 mips_multi_add_insn ("or\t%0,%1,%2", at, tmp1, tmp3, NULL);
12482 /* if (!commit (*MEM = $AT)) goto 1.
12484 This will sometimes be a delayed branch; see the write code below
12486 mips_multi_add_insn (is_64bit_p ? "scd\t%0,%1" : "sc\t%0,%1", at, mem, NULL);
12487 mips_multi_add_insn ("beq%?\t%0,%.,1b", at, NULL);
12489 /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */
12490 if (insn1 != SYNC_INSN1_MOVE && insn1 != SYNC_INSN1_LI && tmp3 != newval)
12492 mips_multi_copy_insn (tmp3_insn);
12493 mips_multi_set_operand (mips_multi_last_index (), 0, newval);
12495 else if (!(required_oldval && cmp))
12496 mips_multi_add_insn ("nop", NULL);
12498 /* CMP = 1 -- either standalone or in a delay slot. */
12499 if (required_oldval && cmp)
12500 mips_multi_add_insn ("li\t%0,1", cmp, NULL);
12502 /* Output the acquire side of the memory barrier. */
12503 if (TARGET_SYNC_AFTER_SC && need_atomic_barrier_p (model, false))
12504 mips_multi_add_insn ("sync", NULL);
12506 /* Output the exit label, if needed. */
12507 if (required_oldval)
12508 mips_multi_add_label ("2:");
12510 #undef READ_OPERAND
12513 /* Output and/or return the asm template for sync loop INSN, which has
12514 the operands given by OPERANDS. */
12517 mips_output_sync_loop (rtx insn, rtx *operands)
12519 mips_process_sync_loop (insn, operands);
12521 /* Use branch-likely instructions to work around the LL/SC R10000
12523 mips_branch_likely = TARGET_FIX_R10000;
12525 mips_push_asm_switch (&mips_noreorder);
12526 mips_push_asm_switch (&mips_nomacro);
12527 mips_push_asm_switch (&mips_noat);
12528 mips_start_ll_sc_sync_block ();
12530 mips_multi_write ();
12532 mips_end_ll_sc_sync_block ();
12533 mips_pop_asm_switch (&mips_noat);
12534 mips_pop_asm_switch (&mips_nomacro);
12535 mips_pop_asm_switch (&mips_noreorder);
12540 /* Return the number of individual instructions in sync loop INSN,
12541 which has the operands given by OPERANDS. */
12544 mips_sync_loop_insns (rtx insn, rtx *operands)
12546 mips_process_sync_loop (insn, operands);
12547 return mips_multi_num_insns;
12550 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
12551 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
12553 When working around R4000 and R4400 errata, we need to make sure that
12554 the division is not immediately followed by a shift[1][2]. We also
12555 need to stop the division from being put into a branch delay slot[3].
12556 The easiest way to avoid both problems is to add a nop after the
12557 division. When a divide-by-zero check is needed, this nop can be
12558 used to fill the branch delay slot.
12560 [1] If a double-word or a variable shift executes immediately
12561 after starting an integer division, the shift may give an
12562 incorrect result. See quotations of errata #16 and #28 from
12563 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
12564 in mips.md for details.
12566 [2] A similar bug to [1] exists for all revisions of the
12567 R4000 and the R4400 when run in an MC configuration.
12568 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
12570 "19. In this following sequence:
12572 ddiv (or ddivu or div or divu)
12573 dsll32 (or dsrl32, dsra32)
12575 if an MPT stall occurs, while the divide is slipping the cpu
12576 pipeline, then the following double shift would end up with an
12579 Workaround: The compiler needs to avoid generating any
12580 sequence with divide followed by extended double shift."
12582 This erratum is also present in "MIPS R4400MC Errata, Processor
12583 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
12584 & 3.0" as errata #10 and #4, respectively.
12586 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
12587 (also valid for MIPS R4000MC processors):
12589 "52. R4000SC: This bug does not apply for the R4000PC.
12591 There are two flavors of this bug:
12593 1) If the instruction just after divide takes an RF exception
12594 (tlb-refill, tlb-invalid) and gets an instruction cache
12595 miss (both primary and secondary) and the line which is
12596 currently in secondary cache at this index had the first
12597 data word, where the bits 5..2 are set, then R4000 would
12598 get a wrong result for the div.
12603 ------------------- # end-of page. -tlb-refill
12608 ------------------- # end-of page. -tlb-invalid
12611 2) If the divide is in the taken branch delay slot, where the
12612 target takes RF exception and gets an I-cache miss for the
12613 exception vector or where I-cache miss occurs for the
12614 target address, under the above mentioned scenarios, the
12615 div would get wrong results.
12618 j r2 # to next page mapped or unmapped
12619 div r8,r9 # this bug would be there as long
12620 # as there is an ICache miss and
12621 nop # the "data pattern" is present
12624 beq r0, r0, NextPage # to Next page
12628 This bug is present for div, divu, ddiv, and ddivu
12631 Workaround: For item 1), OS could make sure that the next page
12632 after the divide instruction is also mapped. For item 2), the
12633 compiler could make sure that the divide instruction is not in
12634 the branch delay slot."
12636 These processors have PRId values of 0x00004220 and 0x00004300 for
12637 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
12640 mips_output_division (const char *division, rtx *operands)
12645 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
12647 output_asm_insn (s, operands);
12650 if (TARGET_CHECK_ZERO_DIV)
12654 output_asm_insn (s, operands);
12655 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
12657 else if (GENERATE_DIVIDE_TRAPS)
12659 /* Avoid long replay penalty on load miss by putting the trap before
12662 output_asm_insn ("teq\t%2,%.,7", operands);
12665 output_asm_insn (s, operands);
12666 s = "teq\t%2,%.,7";
12671 output_asm_insn ("%(bne\t%2,%.,1f", operands);
12672 output_asm_insn (s, operands);
12673 s = "break\t7%)\n1:";
12679 /* Return true if IN_INSN is a multiply-add or multiply-subtract
12680 instruction and if OUT_INSN assigns to the accumulator operand. */
12683 mips_linked_madd_p (rtx out_insn, rtx in_insn)
12685 enum attr_accum_in accum_in;
12686 int accum_in_opnum;
12689 if (recog_memoized (in_insn) < 0)
12692 accum_in = get_attr_accum_in (in_insn);
12693 if (accum_in == ACCUM_IN_NONE)
12696 accum_in_opnum = accum_in - ACCUM_IN_0;
12698 extract_insn (in_insn);
12699 gcc_assert (accum_in_opnum < recog_data.n_operands);
12700 accum_in_op = recog_data.operand[accum_in_opnum];
12702 return reg_set_p (accum_in_op, out_insn);
12705 /* True if the dependency between OUT_INSN and IN_INSN is on the store
12706 data rather than the address. We need this because the cprestore
12707 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
12708 which causes the default routine to abort. We just return false
12712 mips_store_data_bypass_p (rtx out_insn, rtx in_insn)
12714 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
12717 return !store_data_bypass_p (out_insn, in_insn);
12721 /* Variables and flags used in scheduler hooks when tuning for
12725 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
12728 /* If true, then next ALU1/2 instruction will go to ALU1. */
12731 /* If true, then next FALU1/2 unstruction will go to FALU1. */
12734 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
12735 int alu1_core_unit_code;
12736 int alu2_core_unit_code;
12737 int falu1_core_unit_code;
12738 int falu2_core_unit_code;
12740 /* True if current cycle has a multi instruction.
12741 This flag is used in mips_ls2_dfa_post_advance_cycle. */
12742 bool cycle_has_multi_p;
12744 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
12745 These are used in mips_ls2_dfa_post_advance_cycle to initialize
12747 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
12748 instruction to go ALU1. */
12749 rtx alu1_turn_enabled_insn;
12750 rtx alu2_turn_enabled_insn;
12751 rtx falu1_turn_enabled_insn;
12752 rtx falu2_turn_enabled_insn;
12755 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
12756 dependencies have no cost, except on the 20Kc where output-dependence
12757 is treated like input-dependence. */
12760 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
12761 rtx dep ATTRIBUTE_UNUSED, int cost)
12763 if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT
12766 if (REG_NOTE_KIND (link) != 0)
12771 /* Return the number of instructions that can be issued per cycle. */
12774 mips_issue_rate (void)
12778 case PROCESSOR_74KC:
12779 case PROCESSOR_74KF2_1:
12780 case PROCESSOR_74KF1_1:
12781 case PROCESSOR_74KF3_2:
12782 /* The 74k is not strictly quad-issue cpu, but can be seen as one
12783 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
12784 but in reality only a maximum of 3 insns can be issued as
12785 floating-point loads and stores also require a slot in the
12787 case PROCESSOR_R10000:
12788 /* All R10K Processors are quad-issue (being the first MIPS
12789 processors to support this feature). */
12792 case PROCESSOR_20KC:
12793 case PROCESSOR_R4130:
12794 case PROCESSOR_R5400:
12795 case PROCESSOR_R5500:
12796 case PROCESSOR_R7000:
12797 case PROCESSOR_R9000:
12798 case PROCESSOR_OCTEON:
12799 case PROCESSOR_OCTEON2:
12802 case PROCESSOR_SB1:
12803 case PROCESSOR_SB1A:
12804 /* This is actually 4, but we get better performance if we claim 3.
12805 This is partly because of unwanted speculative code motion with the
12806 larger number, and partly because in most common cases we can't
12807 reach the theoretical max of 4. */
12810 case PROCESSOR_LOONGSON_2E:
12811 case PROCESSOR_LOONGSON_2F:
12812 case PROCESSOR_LOONGSON_3A:
12815 case PROCESSOR_XLP:
12816 return (reload_completed ? 4 : 3);
12823 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
12826 mips_ls2_init_dfa_post_cycle_insn (void)
12829 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
12830 mips_ls2.alu1_turn_enabled_insn = get_insns ();
12834 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
12835 mips_ls2.alu2_turn_enabled_insn = get_insns ();
12839 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
12840 mips_ls2.falu1_turn_enabled_insn = get_insns ();
12844 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
12845 mips_ls2.falu2_turn_enabled_insn = get_insns ();
12848 mips_ls2.alu1_core_unit_code = get_cpu_unit_code ("ls2_alu1_core");
12849 mips_ls2.alu2_core_unit_code = get_cpu_unit_code ("ls2_alu2_core");
12850 mips_ls2.falu1_core_unit_code = get_cpu_unit_code ("ls2_falu1_core");
12851 mips_ls2.falu2_core_unit_code = get_cpu_unit_code ("ls2_falu2_core");
12854 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
12855 Init data used in mips_dfa_post_advance_cycle. */
12858 mips_init_dfa_post_cycle_insn (void)
12860 if (TUNE_LOONGSON_2EF)
12861 mips_ls2_init_dfa_post_cycle_insn ();
12864 /* Initialize STATE when scheduling for Loongson 2E/2F.
12865 Support round-robin dispatch scheme by enabling only one of
12866 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
12870 mips_ls2_dfa_post_advance_cycle (state_t state)
12872 if (cpu_unit_reservation_p (state, mips_ls2.alu1_core_unit_code))
12874 /* Though there are no non-pipelined ALU1 insns,
12875 we can get an instruction of type 'multi' before reload. */
12876 gcc_assert (mips_ls2.cycle_has_multi_p);
12877 mips_ls2.alu1_turn_p = false;
12880 mips_ls2.cycle_has_multi_p = false;
12882 if (cpu_unit_reservation_p (state, mips_ls2.alu2_core_unit_code))
12883 /* We have a non-pipelined alu instruction in the core,
12884 adjust round-robin counter. */
12885 mips_ls2.alu1_turn_p = true;
12887 if (mips_ls2.alu1_turn_p)
12889 if (state_transition (state, mips_ls2.alu1_turn_enabled_insn) >= 0)
12890 gcc_unreachable ();
12894 if (state_transition (state, mips_ls2.alu2_turn_enabled_insn) >= 0)
12895 gcc_unreachable ();
12898 if (cpu_unit_reservation_p (state, mips_ls2.falu1_core_unit_code))
12900 /* There are no non-pipelined FALU1 insns. */
12901 gcc_unreachable ();
12902 mips_ls2.falu1_turn_p = false;
12905 if (cpu_unit_reservation_p (state, mips_ls2.falu2_core_unit_code))
12906 /* We have a non-pipelined falu instruction in the core,
12907 adjust round-robin counter. */
12908 mips_ls2.falu1_turn_p = true;
12910 if (mips_ls2.falu1_turn_p)
12912 if (state_transition (state, mips_ls2.falu1_turn_enabled_insn) >= 0)
12913 gcc_unreachable ();
12917 if (state_transition (state, mips_ls2.falu2_turn_enabled_insn) >= 0)
12918 gcc_unreachable ();
12922 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
12923 This hook is being called at the start of each cycle. */
12926 mips_dfa_post_advance_cycle (void)
12928 if (TUNE_LOONGSON_2EF)
12929 mips_ls2_dfa_post_advance_cycle (curr_state);
12932 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
12933 be as wide as the scheduling freedom in the DFA. */
12936 mips_multipass_dfa_lookahead (void)
12938 /* Can schedule up to 4 of the 6 function units in any one cycle. */
12942 if (TUNE_LOONGSON_2EF || TUNE_LOONGSON_3A)
12951 /* Remove the instruction at index LOWER from ready queue READY and
12952 reinsert it in front of the instruction at index HIGHER. LOWER must
12956 mips_promote_ready (rtx *ready, int lower, int higher)
12961 new_head = ready[lower];
12962 for (i = lower; i < higher; i++)
12963 ready[i] = ready[i + 1];
12964 ready[i] = new_head;
12967 /* If the priority of the instruction at POS2 in the ready queue READY
12968 is within LIMIT units of that of the instruction at POS1, swap the
12969 instructions if POS2 is not already less than POS1. */
12972 mips_maybe_swap_ready (rtx *ready, int pos1, int pos2, int limit)
12975 && INSN_PRIORITY (ready[pos1]) + limit >= INSN_PRIORITY (ready[pos2]))
12979 temp = ready[pos1];
12980 ready[pos1] = ready[pos2];
12981 ready[pos2] = temp;
12985 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
12986 that may clobber hi or lo. */
12987 static rtx mips_macc_chains_last_hilo;
12989 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
12990 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
12993 mips_macc_chains_record (rtx insn)
12995 if (get_attr_may_clobber_hilo (insn))
12996 mips_macc_chains_last_hilo = insn;
12999 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
13000 has NREADY elements, looking for a multiply-add or multiply-subtract
13001 instruction that is cumulative with mips_macc_chains_last_hilo.
13002 If there is one, promote it ahead of anything else that might
13003 clobber hi or lo. */
13006 mips_macc_chains_reorder (rtx *ready, int nready)
13010 if (mips_macc_chains_last_hilo != 0)
13011 for (i = nready - 1; i >= 0; i--)
13012 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
13014 for (j = nready - 1; j > i; j--)
13015 if (recog_memoized (ready[j]) >= 0
13016 && get_attr_may_clobber_hilo (ready[j]))
13018 mips_promote_ready (ready, i, j);
13025 /* The last instruction to be scheduled. */
13026 static rtx vr4130_last_insn;
13028 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
13029 points to an rtx that is initially an instruction. Nullify the rtx
13030 if the instruction uses the value of register X. */
13033 vr4130_true_reg_dependence_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
13038 insn_ptr = (rtx *) data;
13041 && reg_referenced_p (x, PATTERN (*insn_ptr)))
13045 /* Return true if there is true register dependence between vr4130_last_insn
13049 vr4130_true_reg_dependence_p (rtx insn)
13051 note_stores (PATTERN (vr4130_last_insn),
13052 vr4130_true_reg_dependence_p_1, &insn);
13056 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
13057 the ready queue and that INSN2 is the instruction after it, return
13058 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
13059 in which INSN1 and INSN2 can probably issue in parallel, but for
13060 which (INSN2, INSN1) should be less sensitive to instruction
13061 alignment than (INSN1, INSN2). See 4130.md for more details. */
13064 vr4130_swap_insns_p (rtx insn1, rtx insn2)
13066 sd_iterator_def sd_it;
13069 /* Check for the following case:
13071 1) there is some other instruction X with an anti dependence on INSN1;
13072 2) X has a higher priority than INSN2; and
13073 3) X is an arithmetic instruction (and thus has no unit restrictions).
13075 If INSN1 is the last instruction blocking X, it would better to
13076 choose (INSN1, X) over (INSN2, INSN1). */
13077 FOR_EACH_DEP (insn1, SD_LIST_FORW, sd_it, dep)
13078 if (DEP_TYPE (dep) == REG_DEP_ANTI
13079 && INSN_PRIORITY (DEP_CON (dep)) > INSN_PRIORITY (insn2)
13080 && recog_memoized (DEP_CON (dep)) >= 0
13081 && get_attr_vr4130_class (DEP_CON (dep)) == VR4130_CLASS_ALU)
13084 if (vr4130_last_insn != 0
13085 && recog_memoized (insn1) >= 0
13086 && recog_memoized (insn2) >= 0)
13088 /* See whether INSN1 and INSN2 use different execution units,
13089 or if they are both ALU-type instructions. If so, they can
13090 probably execute in parallel. */
13091 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
13092 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
13093 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
13095 /* If only one of the instructions has a dependence on
13096 vr4130_last_insn, prefer to schedule the other one first. */
13097 bool dep1_p = vr4130_true_reg_dependence_p (insn1);
13098 bool dep2_p = vr4130_true_reg_dependence_p (insn2);
13099 if (dep1_p != dep2_p)
13102 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
13103 is not an ALU-type instruction and if INSN1 uses the same
13104 execution unit. (Note that if this condition holds, we already
13105 know that INSN2 uses a different execution unit.) */
13106 if (class1 != VR4130_CLASS_ALU
13107 && recog_memoized (vr4130_last_insn) >= 0
13108 && class1 == get_attr_vr4130_class (vr4130_last_insn))
13115 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
13116 queue with at least two instructions. Swap the first two if
13117 vr4130_swap_insns_p says that it could be worthwhile. */
13120 vr4130_reorder (rtx *ready, int nready)
13122 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
13123 mips_promote_ready (ready, nready - 2, nready - 1);
13126 /* Record whether last 74k AGEN instruction was a load or store. */
13127 static enum attr_type mips_last_74k_agen_insn = TYPE_UNKNOWN;
13129 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
13130 resets to TYPE_UNKNOWN state. */
13133 mips_74k_agen_init (rtx insn)
13135 if (!insn || CALL_P (insn) || JUMP_P (insn))
13136 mips_last_74k_agen_insn = TYPE_UNKNOWN;
13139 enum attr_type type = get_attr_type (insn);
13140 if (type == TYPE_LOAD || type == TYPE_STORE)
13141 mips_last_74k_agen_insn = type;
13145 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
13146 loads to be grouped together, and multiple stores to be grouped
13147 together. Swap things around in the ready queue to make this happen. */
13150 mips_74k_agen_reorder (rtx *ready, int nready)
13153 int store_pos, load_pos;
13158 for (i = nready - 1; i >= 0; i--)
13160 rtx insn = ready[i];
13161 if (USEFUL_INSN_P (insn))
13162 switch (get_attr_type (insn))
13165 if (store_pos == -1)
13170 if (load_pos == -1)
13179 if (load_pos == -1 || store_pos == -1)
13182 switch (mips_last_74k_agen_insn)
13185 /* Prefer to schedule loads since they have a higher latency. */
13187 /* Swap loads to the front of the queue. */
13188 mips_maybe_swap_ready (ready, load_pos, store_pos, 4);
13191 /* Swap stores to the front of the queue. */
13192 mips_maybe_swap_ready (ready, store_pos, load_pos, 4);
13199 /* Implement TARGET_SCHED_INIT. */
13202 mips_sched_init (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13203 int max_ready ATTRIBUTE_UNUSED)
13205 mips_macc_chains_last_hilo = 0;
13206 vr4130_last_insn = 0;
13207 mips_74k_agen_init (NULL_RTX);
13209 /* When scheduling for Loongson2, branch instructions go to ALU1,
13210 therefore basic block is most likely to start with round-robin counter
13211 pointed to ALU2. */
13212 mips_ls2.alu1_turn_p = false;
13213 mips_ls2.falu1_turn_p = true;
13216 /* Subroutine used by TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
13219 mips_sched_reorder_1 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13220 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
13222 if (!reload_completed
13223 && TUNE_MACC_CHAINS
13225 mips_macc_chains_reorder (ready, *nreadyp);
13227 if (reload_completed
13229 && !TARGET_VR4130_ALIGN
13231 vr4130_reorder (ready, *nreadyp);
13234 mips_74k_agen_reorder (ready, *nreadyp);
13237 /* Implement TARGET_SCHED_REORDER. */
13240 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13241 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
13243 mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle);
13244 return mips_issue_rate ();
13247 /* Implement TARGET_SCHED_REORDER2. */
13250 mips_sched_reorder2 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13251 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
13253 mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle);
13254 return cached_can_issue_more;
13257 /* Update round-robin counters for ALU1/2 and FALU1/2. */
13260 mips_ls2_variable_issue (rtx insn)
13262 if (mips_ls2.alu1_turn_p)
13264 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu1_core_unit_code))
13265 mips_ls2.alu1_turn_p = false;
13269 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu2_core_unit_code))
13270 mips_ls2.alu1_turn_p = true;
13273 if (mips_ls2.falu1_turn_p)
13275 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu1_core_unit_code))
13276 mips_ls2.falu1_turn_p = false;
13280 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu2_core_unit_code))
13281 mips_ls2.falu1_turn_p = true;
13284 if (recog_memoized (insn) >= 0)
13285 mips_ls2.cycle_has_multi_p |= (get_attr_type (insn) == TYPE_MULTI);
13288 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
13291 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13292 rtx insn, int more)
13294 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
13295 if (USEFUL_INSN_P (insn))
13297 if (get_attr_type (insn) != TYPE_GHOST)
13299 if (!reload_completed && TUNE_MACC_CHAINS)
13300 mips_macc_chains_record (insn);
13301 vr4130_last_insn = insn;
13303 mips_74k_agen_init (insn);
13304 else if (TUNE_LOONGSON_2EF)
13305 mips_ls2_variable_issue (insn);
13308 /* Instructions of type 'multi' should all be split before
13309 the second scheduling pass. */
13310 gcc_assert (!reload_completed
13311 || recog_memoized (insn) < 0
13312 || get_attr_type (insn) != TYPE_MULTI);
13314 cached_can_issue_more = more;
13318 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
13319 return the first operand of the associated PREF or PREFX insn. */
13322 mips_prefetch_cookie (rtx write, rtx locality)
13324 /* store_streamed / load_streamed. */
13325 if (INTVAL (locality) <= 0)
13326 return GEN_INT (INTVAL (write) + 4);
13328 /* store / load. */
13329 if (INTVAL (locality) <= 2)
13332 /* store_retained / load_retained. */
13333 return GEN_INT (INTVAL (write) + 6);
13336 /* Flags that indicate when a built-in function is available.
13338 BUILTIN_AVAIL_NON_MIPS16
13339 The function is available on the current target, but only
13340 in non-MIPS16 mode. */
13341 #define BUILTIN_AVAIL_NON_MIPS16 1
13343 /* Declare an availability predicate for built-in functions that
13344 require non-MIPS16 mode and also require COND to be true.
13345 NAME is the main part of the predicate's name. */
13346 #define AVAIL_NON_MIPS16(NAME, COND) \
13347 static unsigned int \
13348 mips_builtin_avail_##NAME (void) \
13350 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
13353 /* This structure describes a single built-in function. */
13354 struct mips_builtin_description {
13355 /* The code of the main .md file instruction. See mips_builtin_type
13356 for more information. */
13357 enum insn_code icode;
13359 /* The floating-point comparison code to use with ICODE, if any. */
13360 enum mips_fp_condition cond;
13362 /* The name of the built-in function. */
13365 /* Specifies how the function should be expanded. */
13366 enum mips_builtin_type builtin_type;
13368 /* The function's prototype. */
13369 enum mips_function_type function_type;
13371 /* Whether the function is available. */
13372 unsigned int (*avail) (void);
13375 AVAIL_NON_MIPS16 (paired_single, TARGET_PAIRED_SINGLE_FLOAT)
13376 AVAIL_NON_MIPS16 (sb1_paired_single, TARGET_SB1 && TARGET_PAIRED_SINGLE_FLOAT)
13377 AVAIL_NON_MIPS16 (mips3d, TARGET_MIPS3D)
13378 AVAIL_NON_MIPS16 (dsp, TARGET_DSP)
13379 AVAIL_NON_MIPS16 (dspr2, TARGET_DSPR2)
13380 AVAIL_NON_MIPS16 (dsp_32, !TARGET_64BIT && TARGET_DSP)
13381 AVAIL_NON_MIPS16 (dsp_64, TARGET_64BIT && TARGET_DSP)
13382 AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2)
13383 AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS)
13384 AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
13386 /* Construct a mips_builtin_description from the given arguments.
13388 INSN is the name of the associated instruction pattern, without the
13389 leading CODE_FOR_mips_.
13391 CODE is the floating-point condition code associated with the
13392 function. It can be 'f' if the field is not applicable.
13394 NAME is the name of the function itself, without the leading
13397 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
13399 AVAIL is the name of the availability predicate, without the leading
13400 mips_builtin_avail_. */
13401 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
13402 FUNCTION_TYPE, AVAIL) \
13403 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
13404 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
13405 mips_builtin_avail_ ## AVAIL }
13407 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
13408 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
13409 are as for MIPS_BUILTIN. */
13410 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
13411 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
13413 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
13414 are subject to mips_builtin_avail_<AVAIL>. */
13415 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
13416 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
13417 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
13418 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
13419 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
13421 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
13422 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
13423 while the any and all forms are subject to mips_builtin_avail_mips3d. */
13424 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
13425 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
13426 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
13428 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
13429 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
13431 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
13432 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
13434 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
13435 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
13438 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
13439 are subject to mips_builtin_avail_mips3d. */
13440 #define CMP_4S_BUILTINS(INSN, COND) \
13441 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
13442 MIPS_BUILTIN_CMP_ANY, \
13443 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
13444 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
13445 MIPS_BUILTIN_CMP_ALL, \
13446 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
13448 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
13449 instruction requires mips_builtin_avail_<AVAIL>. */
13450 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
13451 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
13452 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
13454 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
13455 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
13458 /* Define all the built-in functions related to C.cond.fmt condition COND. */
13459 #define CMP_BUILTINS(COND) \
13460 MOVTF_BUILTINS (c, COND, paired_single), \
13461 MOVTF_BUILTINS (cabs, COND, mips3d), \
13462 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
13463 CMP_PS_BUILTINS (c, COND, paired_single), \
13464 CMP_PS_BUILTINS (cabs, COND, mips3d), \
13465 CMP_4S_BUILTINS (c, COND), \
13466 CMP_4S_BUILTINS (cabs, COND)
13468 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
13469 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
13470 and AVAIL are as for MIPS_BUILTIN. */
13471 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
13472 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
13473 FUNCTION_TYPE, AVAIL)
13475 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
13476 branch instruction. AVAIL is as for MIPS_BUILTIN. */
13477 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
13478 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
13479 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
13481 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
13482 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
13483 builtin_description field. */
13484 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
13485 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
13486 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
13487 FUNCTION_TYPE, mips_builtin_avail_loongson }
13489 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
13490 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
13491 builtin_description field. */
13492 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
13493 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
13495 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
13496 We use functions of this form when the same insn can be usefully applied
13497 to more than one datatype. */
13498 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
13499 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
13501 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
13502 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
13503 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
13504 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
13505 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
13506 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
13507 #define CODE_FOR_mips_mult CODE_FOR_mulsidi3_32bit
13508 #define CODE_FOR_mips_multu CODE_FOR_umulsidi3_32bit
13510 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
13511 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
13512 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
13513 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
13514 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
13515 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
13516 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
13517 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
13518 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
13519 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
13520 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
13521 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
13522 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
13523 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
13524 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
13525 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
13526 #define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3
13527 #define CODE_FOR_loongson_psllh CODE_FOR_ashlv4hi3
13528 #define CODE_FOR_loongson_psllw CODE_FOR_ashlv2si3
13529 #define CODE_FOR_loongson_psrlh CODE_FOR_lshrv4hi3
13530 #define CODE_FOR_loongson_psrlw CODE_FOR_lshrv2si3
13531 #define CODE_FOR_loongson_psrah CODE_FOR_ashrv4hi3
13532 #define CODE_FOR_loongson_psraw CODE_FOR_ashrv2si3
13533 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
13534 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
13535 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
13536 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
13537 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
13538 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
13539 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
13541 static const struct mips_builtin_description mips_builtins[] = {
13542 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13543 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13544 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13545 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13546 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, paired_single),
13547 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, paired_single),
13548 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, paired_single),
13549 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, paired_single),
13551 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT, paired_single),
13552 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13553 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13554 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
13555 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, mips3d),
13557 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, mips3d),
13558 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, mips3d),
13559 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
13560 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
13561 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
13562 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13564 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, mips3d),
13565 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, mips3d),
13566 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
13567 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
13568 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
13569 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13571 MIPS_FP_CONDITIONS (CMP_BUILTINS),
13573 /* Built-in functions for the SB-1 processor. */
13574 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, sb1_paired_single),
13576 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
13577 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13578 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13579 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
13580 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13581 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13582 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13583 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13584 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
13585 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13586 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13587 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, dsp),
13588 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, dsp),
13589 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, dsp),
13590 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, dsp),
13591 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, dsp),
13592 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, dsp),
13593 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
13594 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
13595 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
13596 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
13597 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, dsp),
13598 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, dsp),
13599 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
13600 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
13601 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
13602 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
13603 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
13604 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
13605 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
13606 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
13607 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
13608 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
13609 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
13610 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
13611 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
13612 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
13613 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
13614 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, dsp),
13615 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
13616 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
13617 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13618 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
13619 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
13620 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, dsp),
13621 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, dsp),
13622 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, dsp),
13623 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, dsp),
13624 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
13625 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
13626 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
13627 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
13628 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
13629 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
13630 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
13631 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
13632 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
13633 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13634 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13635 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13636 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, dsp),
13637 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, dsp),
13638 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_POINTER_SI, dsp),
13639 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_POINTER_SI, dsp),
13640 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_POINTER_SI, dsp),
13641 BPOSGE_BUILTIN (32, dsp),
13643 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
13644 DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, dspr2),
13645 DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13646 DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13647 DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
13648 DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
13649 DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
13650 DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
13651 DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
13652 DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
13653 DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
13654 DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13655 DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13656 DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13657 DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13658 DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13659 DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dspr2),
13660 DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
13661 DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
13662 DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
13663 DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
13664 DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
13665 DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, dspr2),
13666 DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13667 DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13668 DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
13669 DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
13670 DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13671 DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13672 DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13673 DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13674 DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13675 DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13676 DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13677 DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13679 /* Built-in functions for the DSP ASE (32-bit only). */
13680 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
13681 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
13682 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
13683 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
13684 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13685 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13686 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13687 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
13688 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
13689 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13690 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13691 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13692 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13693 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
13694 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
13695 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
13696 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, dsp_32),
13697 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, dsp_32),
13698 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, dsp_32),
13699 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, dsp_32),
13700 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, dsp_32),
13701 DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
13702 DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32),
13703 DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
13704 DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32),
13705 DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, dsp_32),
13706 DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, dsp_32),
13708 /* Built-in functions for the DSP ASE (64-bit only). */
13709 DIRECT_BUILTIN (ldx, MIPS_DI_FTYPE_POINTER_SI, dsp_64),
13711 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
13712 DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13713 DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13714 DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13715 DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13716 DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13717 DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13718 DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13719 DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13720 DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13722 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
13723 LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI),
13724 LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI),
13725 LOONGSON_BUILTIN (packushb, MIPS_UV8QI_FTYPE_UV4HI_UV4HI),
13726 LOONGSON_BUILTIN_SUFFIX (paddw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13727 LOONGSON_BUILTIN_SUFFIX (paddh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13728 LOONGSON_BUILTIN_SUFFIX (paddb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13729 LOONGSON_BUILTIN_SUFFIX (paddw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13730 LOONGSON_BUILTIN_SUFFIX (paddh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13731 LOONGSON_BUILTIN_SUFFIX (paddb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13732 LOONGSON_BUILTIN_SUFFIX (paddd, u, MIPS_UDI_FTYPE_UDI_UDI),
13733 LOONGSON_BUILTIN_SUFFIX (paddd, s, MIPS_DI_FTYPE_DI_DI),
13734 LOONGSON_BUILTIN (paddsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13735 LOONGSON_BUILTIN (paddsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
13736 LOONGSON_BUILTIN (paddush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13737 LOONGSON_BUILTIN (paddusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13738 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_ud, MIPS_UDI_FTYPE_UDI_UDI),
13739 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_uw, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13740 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_uh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13741 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_ub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13742 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_sd, MIPS_DI_FTYPE_DI_DI),
13743 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_sw, MIPS_V2SI_FTYPE_V2SI_V2SI),
13744 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_sh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13745 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_sb, MIPS_V8QI_FTYPE_V8QI_V8QI),
13746 LOONGSON_BUILTIN (pavgh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13747 LOONGSON_BUILTIN (pavgb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13748 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13749 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13750 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13751 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13752 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13753 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13754 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13755 LOONGSON_BUILTIN_SUFFIX (pcmpgth, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13756 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13757 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13758 LOONGSON_BUILTIN_SUFFIX (pcmpgth, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13759 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13760 LOONGSON_BUILTIN_SUFFIX (pextrh, u, MIPS_UV4HI_FTYPE_UV4HI_USI),
13761 LOONGSON_BUILTIN_SUFFIX (pextrh, s, MIPS_V4HI_FTYPE_V4HI_USI),
13762 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13763 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13764 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13765 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13766 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13767 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13768 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13769 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13770 LOONGSON_BUILTIN (pmaddhw, MIPS_V2SI_FTYPE_V4HI_V4HI),
13771 LOONGSON_BUILTIN (pmaxsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13772 LOONGSON_BUILTIN (pmaxub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13773 LOONGSON_BUILTIN (pminsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13774 LOONGSON_BUILTIN (pminub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13775 LOONGSON_BUILTIN_SUFFIX (pmovmskb, u, MIPS_UV8QI_FTYPE_UV8QI),
13776 LOONGSON_BUILTIN_SUFFIX (pmovmskb, s, MIPS_V8QI_FTYPE_V8QI),
13777 LOONGSON_BUILTIN (pmulhuh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13778 LOONGSON_BUILTIN (pmulhh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13779 LOONGSON_BUILTIN (pmullh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13780 LOONGSON_BUILTIN (pmuluw, MIPS_UDI_FTYPE_UV2SI_UV2SI),
13781 LOONGSON_BUILTIN (pasubub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13782 LOONGSON_BUILTIN (biadd, MIPS_UV4HI_FTYPE_UV8QI),
13783 LOONGSON_BUILTIN (psadbh, MIPS_UV4HI_FTYPE_UV8QI_UV8QI),
13784 LOONGSON_BUILTIN_SUFFIX (pshufh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
13785 LOONGSON_BUILTIN_SUFFIX (pshufh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
13786 LOONGSON_BUILTIN_SUFFIX (psllh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
13787 LOONGSON_BUILTIN_SUFFIX (psllh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
13788 LOONGSON_BUILTIN_SUFFIX (psllw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
13789 LOONGSON_BUILTIN_SUFFIX (psllw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
13790 LOONGSON_BUILTIN_SUFFIX (psrah, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
13791 LOONGSON_BUILTIN_SUFFIX (psrah, s, MIPS_V4HI_FTYPE_V4HI_UQI),
13792 LOONGSON_BUILTIN_SUFFIX (psraw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
13793 LOONGSON_BUILTIN_SUFFIX (psraw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
13794 LOONGSON_BUILTIN_SUFFIX (psrlh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
13795 LOONGSON_BUILTIN_SUFFIX (psrlh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
13796 LOONGSON_BUILTIN_SUFFIX (psrlw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
13797 LOONGSON_BUILTIN_SUFFIX (psrlw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
13798 LOONGSON_BUILTIN_SUFFIX (psubw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13799 LOONGSON_BUILTIN_SUFFIX (psubh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13800 LOONGSON_BUILTIN_SUFFIX (psubb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13801 LOONGSON_BUILTIN_SUFFIX (psubw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13802 LOONGSON_BUILTIN_SUFFIX (psubh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13803 LOONGSON_BUILTIN_SUFFIX (psubb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13804 LOONGSON_BUILTIN_SUFFIX (psubd, u, MIPS_UDI_FTYPE_UDI_UDI),
13805 LOONGSON_BUILTIN_SUFFIX (psubd, s, MIPS_DI_FTYPE_DI_DI),
13806 LOONGSON_BUILTIN (psubsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13807 LOONGSON_BUILTIN (psubsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
13808 LOONGSON_BUILTIN (psubush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13809 LOONGSON_BUILTIN (psubusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13810 LOONGSON_BUILTIN_SUFFIX (punpckhbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13811 LOONGSON_BUILTIN_SUFFIX (punpckhhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13812 LOONGSON_BUILTIN_SUFFIX (punpckhwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13813 LOONGSON_BUILTIN_SUFFIX (punpckhbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13814 LOONGSON_BUILTIN_SUFFIX (punpckhhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13815 LOONGSON_BUILTIN_SUFFIX (punpckhwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13816 LOONGSON_BUILTIN_SUFFIX (punpcklbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13817 LOONGSON_BUILTIN_SUFFIX (punpcklhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13818 LOONGSON_BUILTIN_SUFFIX (punpcklwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13819 LOONGSON_BUILTIN_SUFFIX (punpcklbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13820 LOONGSON_BUILTIN_SUFFIX (punpcklhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13821 LOONGSON_BUILTIN_SUFFIX (punpcklwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13823 /* Sundry other built-in functions. */
13824 DIRECT_NO_TARGET_BUILTIN (cache, MIPS_VOID_FTYPE_SI_CVPOINTER, cache)
13827 /* Index I is the function declaration for mips_builtins[I], or null if the
13828 function isn't defined on this target. */
13829 static GTY(()) tree mips_builtin_decls[ARRAY_SIZE (mips_builtins)];
13831 /* MODE is a vector mode whose elements have type TYPE. Return the type
13832 of the vector itself. */
13835 mips_builtin_vector_type (tree type, enum machine_mode mode)
13837 static tree types[2 * (int) MAX_MACHINE_MODE];
13840 mode_index = (int) mode;
13842 if (TREE_CODE (type) == INTEGER_TYPE && TYPE_UNSIGNED (type))
13843 mode_index += MAX_MACHINE_MODE;
13845 if (types[mode_index] == NULL_TREE)
13846 types[mode_index] = build_vector_type_for_mode (type, mode);
13847 return types[mode_index];
13850 /* Return a type for 'const volatile void *'. */
13853 mips_build_cvpointer_type (void)
13857 if (cache == NULL_TREE)
13858 cache = build_pointer_type (build_qualified_type
13860 TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE));
13864 /* Source-level argument types. */
13865 #define MIPS_ATYPE_VOID void_type_node
13866 #define MIPS_ATYPE_INT integer_type_node
13867 #define MIPS_ATYPE_POINTER ptr_type_node
13868 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
13870 /* Standard mode-based argument types. */
13871 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
13872 #define MIPS_ATYPE_SI intSI_type_node
13873 #define MIPS_ATYPE_USI unsigned_intSI_type_node
13874 #define MIPS_ATYPE_DI intDI_type_node
13875 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
13876 #define MIPS_ATYPE_SF float_type_node
13877 #define MIPS_ATYPE_DF double_type_node
13879 /* Vector argument types. */
13880 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
13881 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
13882 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
13883 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
13884 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
13885 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
13886 #define MIPS_ATYPE_UV2SI \
13887 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
13888 #define MIPS_ATYPE_UV4HI \
13889 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
13890 #define MIPS_ATYPE_UV8QI \
13891 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
13893 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
13894 their associated MIPS_ATYPEs. */
13895 #define MIPS_FTYPE_ATYPES1(A, B) \
13896 MIPS_ATYPE_##A, MIPS_ATYPE_##B
13898 #define MIPS_FTYPE_ATYPES2(A, B, C) \
13899 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
13901 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
13902 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
13904 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
13905 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
13908 /* Return the function type associated with function prototype TYPE. */
13911 mips_build_function_type (enum mips_function_type type)
13913 static tree types[(int) MIPS_MAX_FTYPE_MAX];
13915 if (types[(int) type] == NULL_TREE)
13918 #define DEF_MIPS_FTYPE(NUM, ARGS) \
13919 case MIPS_FTYPE_NAME##NUM ARGS: \
13920 types[(int) type] \
13921 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
13924 #include "config/mips/mips-ftypes.def"
13925 #undef DEF_MIPS_FTYPE
13927 gcc_unreachable ();
13930 return types[(int) type];
13933 /* Implement TARGET_INIT_BUILTINS. */
13936 mips_init_builtins (void)
13938 const struct mips_builtin_description *d;
13941 /* Iterate through all of the bdesc arrays, initializing all of the
13942 builtin functions. */
13943 for (i = 0; i < ARRAY_SIZE (mips_builtins); i++)
13945 d = &mips_builtins[i];
13947 mips_builtin_decls[i]
13948 = add_builtin_function (d->name,
13949 mips_build_function_type (d->function_type),
13950 i, BUILT_IN_MD, NULL, NULL);
13954 /* Implement TARGET_BUILTIN_DECL. */
13957 mips_builtin_decl (unsigned int code, bool initialize_p ATTRIBUTE_UNUSED)
13959 if (code >= ARRAY_SIZE (mips_builtins))
13960 return error_mark_node;
13961 return mips_builtin_decls[code];
13964 /* Take argument ARGNO from EXP's argument list and convert it into
13965 an expand operand. Store the operand in *OP. */
13968 mips_prepare_builtin_arg (struct expand_operand *op, tree exp,
13969 unsigned int argno)
13974 arg = CALL_EXPR_ARG (exp, argno);
13975 value = expand_normal (arg);
13976 create_input_operand (op, value, TYPE_MODE (TREE_TYPE (arg)));
13979 /* Expand instruction ICODE as part of a built-in function sequence.
13980 Use the first NOPS elements of OPS as the instruction's operands.
13981 HAS_TARGET_P is true if operand 0 is a target; it is false if the
13982 instruction has no target.
13984 Return the target rtx if HAS_TARGET_P, otherwise return const0_rtx. */
13987 mips_expand_builtin_insn (enum insn_code icode, unsigned int nops,
13988 struct expand_operand *ops, bool has_target_p)
13990 if (!maybe_expand_insn (icode, nops, ops))
13992 error ("invalid argument to built-in function");
13993 return has_target_p ? gen_reg_rtx (ops[0].mode) : const0_rtx;
13995 return has_target_p ? ops[0].value : const0_rtx;
13998 /* Expand a floating-point comparison for built-in function call EXP.
13999 The first NARGS arguments are the values to be compared. ICODE is
14000 the .md pattern that does the comparison and COND is the condition
14001 that is being tested. Return an rtx for the result. */
14004 mips_expand_builtin_compare_1 (enum insn_code icode,
14005 enum mips_fp_condition cond,
14006 tree exp, int nargs)
14008 struct expand_operand ops[MAX_RECOG_OPERANDS];
14012 /* The instruction should have a target operand, an operand for each
14013 argument, and an operand for COND. */
14014 gcc_assert (nargs + 2 == insn_data[(int) icode].n_generator_args);
14016 output = mips_allocate_fcc (insn_data[(int) icode].operand[0].mode);
14018 create_fixed_operand (&ops[opno++], output);
14019 for (argno = 0; argno < nargs; argno++)
14020 mips_prepare_builtin_arg (&ops[opno++], exp, argno);
14021 create_integer_operand (&ops[opno++], (int) cond);
14022 return mips_expand_builtin_insn (icode, opno, ops, true);
14025 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
14026 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
14027 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
14028 suggests a good place to put the result. */
14031 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
14034 struct expand_operand ops[MAX_RECOG_OPERANDS];
14037 /* Map any target to operand 0. */
14040 create_output_operand (&ops[opno++], target, TYPE_MODE (TREE_TYPE (exp)));
14042 /* Map the arguments to the other operands. */
14043 gcc_assert (opno + call_expr_nargs (exp)
14044 == insn_data[icode].n_generator_args);
14045 for (argno = 0; argno < call_expr_nargs (exp); argno++)
14046 mips_prepare_builtin_arg (&ops[opno++], exp, argno);
14048 return mips_expand_builtin_insn (icode, opno, ops, has_target_p);
14051 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
14052 function; TYPE says which. EXP is the CALL_EXPR that calls the
14053 function, ICODE is the instruction that should be used to compare
14054 the first two arguments, and COND is the condition it should test.
14055 TARGET, if nonnull, suggests a good place to put the result. */
14058 mips_expand_builtin_movtf (enum mips_builtin_type type,
14059 enum insn_code icode, enum mips_fp_condition cond,
14060 rtx target, tree exp)
14062 struct expand_operand ops[4];
14065 cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp, 2);
14066 create_output_operand (&ops[0], target, TYPE_MODE (TREE_TYPE (exp)));
14067 if (type == MIPS_BUILTIN_MOVT)
14069 mips_prepare_builtin_arg (&ops[2], exp, 2);
14070 mips_prepare_builtin_arg (&ops[1], exp, 3);
14074 mips_prepare_builtin_arg (&ops[1], exp, 2);
14075 mips_prepare_builtin_arg (&ops[2], exp, 3);
14077 create_fixed_operand (&ops[3], cmp_result);
14078 return mips_expand_builtin_insn (CODE_FOR_mips_cond_move_tf_ps,
14082 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
14083 into TARGET otherwise. Return TARGET. */
14086 mips_builtin_branch_and_move (rtx condition, rtx target,
14087 rtx value_if_true, rtx value_if_false)
14089 rtx true_label, done_label;
14091 true_label = gen_label_rtx ();
14092 done_label = gen_label_rtx ();
14094 /* First assume that CONDITION is false. */
14095 mips_emit_move (target, value_if_false);
14097 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
14098 emit_jump_insn (gen_condjump (condition, true_label));
14099 emit_jump_insn (gen_jump (done_label));
14102 /* Fix TARGET if CONDITION is true. */
14103 emit_label (true_label);
14104 mips_emit_move (target, value_if_true);
14106 emit_label (done_label);
14110 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
14111 the CALL_EXPR that calls the function, ICODE is the code of the
14112 comparison instruction, and COND is the condition it should test.
14113 TARGET, if nonnull, suggests a good place to put the boolean result. */
14116 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
14117 enum insn_code icode, enum mips_fp_condition cond,
14118 rtx target, tree exp)
14120 rtx offset, condition, cmp_result;
14122 if (target == 0 || GET_MODE (target) != SImode)
14123 target = gen_reg_rtx (SImode);
14124 cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp,
14125 call_expr_nargs (exp));
14127 /* If the comparison sets more than one register, we define the result
14128 to be 0 if all registers are false and -1 if all registers are true.
14129 The value of the complete result is indeterminate otherwise. */
14130 switch (builtin_type)
14132 case MIPS_BUILTIN_CMP_ALL:
14133 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
14134 return mips_builtin_branch_and_move (condition, target,
14135 const0_rtx, const1_rtx);
14137 case MIPS_BUILTIN_CMP_UPPER:
14138 case MIPS_BUILTIN_CMP_LOWER:
14139 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
14140 condition = gen_single_cc (cmp_result, offset);
14141 return mips_builtin_branch_and_move (condition, target,
14142 const1_rtx, const0_rtx);
14145 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
14146 return mips_builtin_branch_and_move (condition, target,
14147 const1_rtx, const0_rtx);
14151 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
14152 if nonnull, suggests a good place to put the boolean result. */
14155 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
14157 rtx condition, cmp_result;
14160 if (target == 0 || GET_MODE (target) != SImode)
14161 target = gen_reg_rtx (SImode);
14163 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
14165 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
14170 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
14171 return mips_builtin_branch_and_move (condition, target,
14172 const1_rtx, const0_rtx);
14175 /* Implement TARGET_EXPAND_BUILTIN. */
14178 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
14179 enum machine_mode mode, int ignore)
14182 unsigned int fcode, avail;
14183 const struct mips_builtin_description *d;
14185 fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
14186 fcode = DECL_FUNCTION_CODE (fndecl);
14187 gcc_assert (fcode < ARRAY_SIZE (mips_builtins));
14188 d = &mips_builtins[fcode];
14189 avail = d->avail ();
14190 gcc_assert (avail != 0);
14193 error ("built-in function %qE not supported for MIPS16",
14194 DECL_NAME (fndecl));
14195 return ignore ? const0_rtx : CONST0_RTX (mode);
14197 switch (d->builtin_type)
14199 case MIPS_BUILTIN_DIRECT:
14200 return mips_expand_builtin_direct (d->icode, target, exp, true);
14202 case MIPS_BUILTIN_DIRECT_NO_TARGET:
14203 return mips_expand_builtin_direct (d->icode, target, exp, false);
14205 case MIPS_BUILTIN_MOVT:
14206 case MIPS_BUILTIN_MOVF:
14207 return mips_expand_builtin_movtf (d->builtin_type, d->icode,
14208 d->cond, target, exp);
14210 case MIPS_BUILTIN_CMP_ANY:
14211 case MIPS_BUILTIN_CMP_ALL:
14212 case MIPS_BUILTIN_CMP_UPPER:
14213 case MIPS_BUILTIN_CMP_LOWER:
14214 case MIPS_BUILTIN_CMP_SINGLE:
14215 return mips_expand_builtin_compare (d->builtin_type, d->icode,
14216 d->cond, target, exp);
14218 case MIPS_BUILTIN_BPOSGE32:
14219 return mips_expand_builtin_bposge (d->builtin_type, target);
14221 gcc_unreachable ();
14224 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
14225 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
14226 struct mips16_constant {
14227 struct mips16_constant *next;
14230 enum machine_mode mode;
14233 /* Information about an incomplete MIPS16 constant pool. FIRST is the
14234 first constant, HIGHEST_ADDRESS is the highest address that the first
14235 byte of the pool can have, and INSN_ADDRESS is the current instruction
14237 struct mips16_constant_pool {
14238 struct mips16_constant *first;
14239 int highest_address;
14243 /* Add constant VALUE to POOL and return its label. MODE is the
14244 value's mode (used for CONST_INTs, etc.). */
14247 mips16_add_constant (struct mips16_constant_pool *pool,
14248 rtx value, enum machine_mode mode)
14250 struct mips16_constant **p, *c;
14251 bool first_of_size_p;
14253 /* See whether the constant is already in the pool. If so, return the
14254 existing label, otherwise leave P pointing to the place where the
14255 constant should be added.
14257 Keep the pool sorted in increasing order of mode size so that we can
14258 reduce the number of alignments needed. */
14259 first_of_size_p = true;
14260 for (p = &pool->first; *p != 0; p = &(*p)->next)
14262 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
14263 return (*p)->label;
14264 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
14266 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
14267 first_of_size_p = false;
14270 /* In the worst case, the constant needed by the earliest instruction
14271 will end up at the end of the pool. The entire pool must then be
14272 accessible from that instruction.
14274 When adding the first constant, set the pool's highest address to
14275 the address of the first out-of-range byte. Adjust this address
14276 downwards each time a new constant is added. */
14277 if (pool->first == 0)
14278 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
14279 of the instruction with the lowest two bits clear. The base PC
14280 value for LDPC has the lowest three bits clear. Assume the worst
14281 case here; namely that the PC-relative instruction occupies the
14282 last 2 bytes in an aligned word. */
14283 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
14284 pool->highest_address -= GET_MODE_SIZE (mode);
14285 if (first_of_size_p)
14286 /* Take into account the worst possible padding due to alignment. */
14287 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
14289 /* Create a new entry. */
14290 c = XNEW (struct mips16_constant);
14293 c->label = gen_label_rtx ();
14300 /* Output constant VALUE after instruction INSN and return the last
14301 instruction emitted. MODE is the mode of the constant. */
14304 mips16_emit_constants_1 (enum machine_mode mode, rtx value, rtx insn)
14306 if (SCALAR_INT_MODE_P (mode) || ALL_SCALAR_FIXED_POINT_MODE_P (mode))
14308 rtx size = GEN_INT (GET_MODE_SIZE (mode));
14309 return emit_insn_after (gen_consttable_int (value, size), insn);
14312 if (SCALAR_FLOAT_MODE_P (mode))
14313 return emit_insn_after (gen_consttable_float (value), insn);
14315 if (VECTOR_MODE_P (mode))
14319 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
14320 insn = mips16_emit_constants_1 (GET_MODE_INNER (mode),
14321 CONST_VECTOR_ELT (value, i), insn);
14325 gcc_unreachable ();
14328 /* Dump out the constants in CONSTANTS after INSN. */
14331 mips16_emit_constants (struct mips16_constant *constants, rtx insn)
14333 struct mips16_constant *c, *next;
14337 for (c = constants; c != NULL; c = next)
14339 /* If necessary, increase the alignment of PC. */
14340 if (align < GET_MODE_SIZE (c->mode))
14342 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
14343 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
14345 align = GET_MODE_SIZE (c->mode);
14347 insn = emit_label_after (c->label, insn);
14348 insn = mips16_emit_constants_1 (c->mode, c->value, insn);
14354 emit_barrier_after (insn);
14357 /* Return the length of instruction INSN. */
14360 mips16_insn_length (rtx insn)
14364 rtx body = PATTERN (insn);
14365 if (GET_CODE (body) == ADDR_VEC)
14366 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
14367 if (GET_CODE (body) == ADDR_DIFF_VEC)
14368 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
14370 return get_attr_length (insn);
14373 /* If *X is a symbolic constant that refers to the constant pool, add
14374 the constant to POOL and rewrite *X to use the constant's label. */
14377 mips16_rewrite_pool_constant (struct mips16_constant_pool *pool, rtx *x)
14379 rtx base, offset, label;
14381 split_const (*x, &base, &offset);
14382 if (GET_CODE (base) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (base))
14384 label = mips16_add_constant (pool, copy_rtx (get_pool_constant (base)),
14385 get_pool_mode (base));
14386 base = gen_rtx_LABEL_REF (Pmode, label);
14387 *x = mips_unspec_address_offset (base, offset, SYMBOL_PC_RELATIVE);
14391 /* This structure is used to communicate with mips16_rewrite_pool_refs.
14392 INSN is the instruction we're rewriting and POOL points to the current
14394 struct mips16_rewrite_pool_refs_info {
14396 struct mips16_constant_pool *pool;
14399 /* Rewrite *X so that constant pool references refer to the constant's
14400 label instead. DATA points to a mips16_rewrite_pool_refs_info
14404 mips16_rewrite_pool_refs (rtx *x, void *data)
14406 struct mips16_rewrite_pool_refs_info *info =
14407 (struct mips16_rewrite_pool_refs_info *) data;
14409 if (force_to_mem_operand (*x, Pmode))
14411 rtx mem = force_const_mem (GET_MODE (*x), *x);
14412 validate_change (info->insn, x, mem, false);
14417 mips16_rewrite_pool_constant (info->pool, &XEXP (*x, 0));
14421 /* Don't rewrite the __mips16_rdwr symbol. */
14422 if (GET_CODE (*x) == UNSPEC && XINT (*x, 1) == UNSPEC_TLS_GET_TP)
14425 if (TARGET_MIPS16_TEXT_LOADS)
14426 mips16_rewrite_pool_constant (info->pool, x);
14428 return GET_CODE (*x) == CONST ? -1 : 0;
14431 /* Return whether CFG is used in mips_reorg. */
14434 mips_cfg_in_reorg (void)
14436 return (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
14437 || TARGET_RELAX_PIC_CALLS);
14440 /* Build MIPS16 constant pools. Split the instructions if SPLIT_P,
14441 otherwise assume that they are already split. */
14444 mips16_lay_out_constants (bool split_p)
14446 struct mips16_constant_pool pool;
14447 struct mips16_rewrite_pool_refs_info info;
14450 if (!TARGET_MIPS16_PCREL_LOADS)
14455 if (mips_cfg_in_reorg ())
14456 split_all_insns ();
14458 split_all_insns_noflow ();
14461 memset (&pool, 0, sizeof (pool));
14462 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
14464 /* Rewrite constant pool references in INSN. */
14465 if (USEFUL_INSN_P (insn))
14469 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &info);
14472 pool.insn_address += mips16_insn_length (insn);
14474 if (pool.first != NULL)
14476 /* If there are no natural barriers between the first user of
14477 the pool and the highest acceptable address, we'll need to
14478 create a new instruction to jump around the constant pool.
14479 In the worst case, this instruction will be 4 bytes long.
14481 If it's too late to do this transformation after INSN,
14482 do it immediately before INSN. */
14483 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
14487 label = gen_label_rtx ();
14489 jump = emit_jump_insn_before (gen_jump (label), insn);
14490 JUMP_LABEL (jump) = label;
14491 LABEL_NUSES (label) = 1;
14492 barrier = emit_barrier_after (jump);
14494 emit_label_after (label, barrier);
14495 pool.insn_address += 4;
14498 /* See whether the constant pool is now out of range of the first
14499 user. If so, output the constants after the previous barrier.
14500 Note that any instructions between BARRIER and INSN (inclusive)
14501 will use negative offsets to refer to the pool. */
14502 if (pool.insn_address > pool.highest_address)
14504 mips16_emit_constants (pool.first, barrier);
14508 else if (BARRIER_P (insn))
14512 mips16_emit_constants (pool.first, get_last_insn ());
14515 /* Return true if it is worth r10k_simplify_address's while replacing
14516 an address with X. We are looking for constants, and for addresses
14517 at a known offset from the incoming stack pointer. */
14520 r10k_simplified_address_p (rtx x)
14522 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
14524 return x == virtual_incoming_args_rtx || CONSTANT_P (x);
14527 /* X is an expression that appears in INSN. Try to use the UD chains
14528 to simplify it, returning the simplified form on success and the
14529 original form otherwise. Replace the incoming value of $sp with
14530 virtual_incoming_args_rtx (which should never occur in X otherwise). */
14533 r10k_simplify_address (rtx x, rtx insn)
14535 rtx newx, op0, op1, set, def_insn, note;
14537 struct df_link *defs;
14542 op0 = r10k_simplify_address (XEXP (x, 0), insn);
14543 if (op0 != XEXP (x, 0))
14544 newx = simplify_gen_unary (GET_CODE (x), GET_MODE (x),
14545 op0, GET_MODE (XEXP (x, 0)));
14547 else if (BINARY_P (x))
14549 op0 = r10k_simplify_address (XEXP (x, 0), insn);
14550 op1 = r10k_simplify_address (XEXP (x, 1), insn);
14551 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
14552 newx = simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
14554 else if (GET_CODE (x) == LO_SUM)
14556 /* LO_SUMs can be offset from HIGHs, if we know they won't
14557 overflow. See mips_classify_address for the rationale behind
14559 op0 = r10k_simplify_address (XEXP (x, 0), insn);
14560 if (GET_CODE (op0) == HIGH)
14561 newx = XEXP (x, 1);
14563 else if (REG_P (x))
14565 /* Uses are recorded by regno_reg_rtx, not X itself. */
14566 use = df_find_use (insn, regno_reg_rtx[REGNO (x)]);
14568 defs = DF_REF_CHAIN (use);
14570 /* Require a single definition. */
14571 if (defs && defs->next == NULL)
14574 if (DF_REF_IS_ARTIFICIAL (def))
14576 /* Replace the incoming value of $sp with
14577 virtual_incoming_args_rtx. */
14578 if (x == stack_pointer_rtx
14579 && DF_REF_BB (def) == ENTRY_BLOCK_PTR)
14580 newx = virtual_incoming_args_rtx;
14582 else if (dominated_by_p (CDI_DOMINATORS, DF_REF_BB (use),
14585 /* Make sure that DEF_INSN is a single set of REG. */
14586 def_insn = DF_REF_INSN (def);
14587 if (NONJUMP_INSN_P (def_insn))
14589 set = single_set (def_insn);
14590 if (set && rtx_equal_p (SET_DEST (set), x))
14592 /* Prefer to use notes, since the def-use chains
14593 are often shorter. */
14594 note = find_reg_equal_equiv_note (def_insn);
14596 newx = XEXP (note, 0);
14598 newx = SET_SRC (set);
14599 newx = r10k_simplify_address (newx, def_insn);
14605 if (newx && r10k_simplified_address_p (newx))
14610 /* Return true if ADDRESS is known to be an uncached address
14611 on R10K systems. */
14614 r10k_uncached_address_p (unsigned HOST_WIDE_INT address)
14616 unsigned HOST_WIDE_INT upper;
14618 /* Check for KSEG1. */
14619 if (address + 0x60000000 < 0x20000000)
14622 /* Check for uncached XKPHYS addresses. */
14623 if (Pmode == DImode)
14625 upper = (address >> 40) & 0xf9ffff;
14626 if (upper == 0x900000 || upper == 0xb80000)
14632 /* Return true if we can prove that an access to address X in instruction
14633 INSN would be safe from R10K speculation. This X is a general
14634 expression; it might not be a legitimate address. */
14637 r10k_safe_address_p (rtx x, rtx insn)
14640 HOST_WIDE_INT offset_val;
14642 x = r10k_simplify_address (x, insn);
14644 /* Check for references to the stack frame. It doesn't really matter
14645 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
14646 allows us to assume that accesses to any part of the eventual frame
14647 is safe from speculation at any point in the function. */
14648 mips_split_plus (x, &base, &offset_val);
14649 if (base == virtual_incoming_args_rtx
14650 && offset_val >= -cfun->machine->frame.total_size
14651 && offset_val < cfun->machine->frame.args_size)
14654 /* Check for uncached addresses. */
14655 if (CONST_INT_P (x))
14656 return r10k_uncached_address_p (INTVAL (x));
14658 /* Check for accesses to a static object. */
14659 split_const (x, &base, &offset);
14660 return offset_within_block_p (base, INTVAL (offset));
14663 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
14664 an in-range access to an automatic variable, or to an object with
14665 a link-time-constant address. */
14668 r10k_safe_mem_expr_p (tree expr, HOST_WIDE_INT offset)
14670 HOST_WIDE_INT bitoffset, bitsize;
14671 tree inner, var_offset;
14672 enum machine_mode mode;
14673 int unsigned_p, volatile_p;
14675 inner = get_inner_reference (expr, &bitsize, &bitoffset, &var_offset, &mode,
14676 &unsigned_p, &volatile_p, false);
14677 if (!DECL_P (inner) || !DECL_SIZE_UNIT (inner) || var_offset)
14680 offset += bitoffset / BITS_PER_UNIT;
14681 return offset >= 0 && offset < tree_low_cst (DECL_SIZE_UNIT (inner), 1);
14684 /* A for_each_rtx callback for which DATA points to the instruction
14685 containing *X. Stop the search if we find a MEM that is not safe
14686 from R10K speculation. */
14689 r10k_needs_protection_p_1 (rtx *loc, void *data)
14698 && MEM_OFFSET_KNOWN_P (mem)
14699 && r10k_safe_mem_expr_p (MEM_EXPR (mem), MEM_OFFSET (mem)))
14702 if (r10k_safe_address_p (XEXP (mem, 0), (rtx) data))
14708 /* A note_stores callback for which DATA points to an instruction pointer.
14709 If *DATA is nonnull, make it null if it X contains a MEM that is not
14710 safe from R10K speculation. */
14713 r10k_needs_protection_p_store (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
14718 insn_ptr = (rtx *) data;
14719 if (*insn_ptr && for_each_rtx (&x, r10k_needs_protection_p_1, *insn_ptr))
14720 *insn_ptr = NULL_RTX;
14723 /* A for_each_rtx callback that iterates over the pattern of a CALL_INSN.
14724 Return nonzero if the call is not to a declared function. */
14727 r10k_needs_protection_p_call (rtx *loc, void *data ATTRIBUTE_UNUSED)
14736 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DECL (x))
14742 /* Return true if instruction INSN needs to be protected by an R10K
14746 r10k_needs_protection_p (rtx insn)
14749 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_call, NULL);
14751 if (mips_r10k_cache_barrier == R10K_CACHE_BARRIER_STORE)
14753 note_stores (PATTERN (insn), r10k_needs_protection_p_store, &insn);
14754 return insn == NULL_RTX;
14757 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_1, insn);
14760 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
14761 edge is unconditional. */
14764 r10k_protected_bb_p (basic_block bb, sbitmap protected_bbs)
14769 FOR_EACH_EDGE (e, ei, bb->preds)
14770 if (!single_succ_p (e->src)
14771 || !bitmap_bit_p (protected_bbs, e->src->index)
14772 || (e->flags & EDGE_COMPLEX) != 0)
14777 /* Implement -mr10k-cache-barrier= for the current function. */
14780 r10k_insert_cache_barriers (void)
14782 int *rev_post_order;
14785 sbitmap protected_bbs;
14786 rtx insn, end, unprotected_region;
14790 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
14794 /* Calculate dominators. */
14795 calculate_dominance_info (CDI_DOMINATORS);
14797 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
14798 X is protected by a cache barrier. */
14799 protected_bbs = sbitmap_alloc (last_basic_block);
14800 bitmap_clear (protected_bbs);
14802 /* Iterate over the basic blocks in reverse post-order. */
14803 rev_post_order = XNEWVEC (int, last_basic_block);
14804 n = pre_and_rev_post_order_compute (NULL, rev_post_order, false);
14805 for (i = 0; i < n; i++)
14807 bb = BASIC_BLOCK (rev_post_order[i]);
14809 /* If this block is only reached by unconditional edges, and if the
14810 source of every edge is protected, the beginning of the block is
14812 if (r10k_protected_bb_p (bb, protected_bbs))
14813 unprotected_region = NULL_RTX;
14815 unprotected_region = pc_rtx;
14816 end = NEXT_INSN (BB_END (bb));
14818 /* UNPROTECTED_REGION is:
14820 - null if we are processing a protected region,
14821 - pc_rtx if we are processing an unprotected region but have
14822 not yet found the first instruction in it
14823 - the first instruction in an unprotected region otherwise. */
14824 for (insn = BB_HEAD (bb); insn != end; insn = NEXT_INSN (insn))
14826 if (unprotected_region && USEFUL_INSN_P (insn))
14828 if (recog_memoized (insn) == CODE_FOR_mips_cache)
14829 /* This CACHE instruction protects the following code. */
14830 unprotected_region = NULL_RTX;
14833 /* See if INSN is the first instruction in this
14834 unprotected region. */
14835 if (unprotected_region == pc_rtx)
14836 unprotected_region = insn;
14838 /* See if INSN needs to be protected. If so,
14839 we must insert a cache barrier somewhere between
14840 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
14841 clear which position is better performance-wise,
14842 but as a tie-breaker, we assume that it is better
14843 to allow delay slots to be back-filled where
14844 possible, and that it is better not to insert
14845 barriers in the middle of already-scheduled code.
14846 We therefore insert the barrier at the beginning
14848 if (r10k_needs_protection_p (insn))
14850 emit_insn_before (gen_r10k_cache_barrier (),
14851 unprotected_region);
14852 unprotected_region = NULL_RTX;
14858 /* The called function is not required to protect the exit path.
14859 The code that follows a call is therefore unprotected. */
14860 unprotected_region = pc_rtx;
14863 /* Record whether the end of this block is protected. */
14864 if (unprotected_region == NULL_RTX)
14865 bitmap_set_bit (protected_bbs, bb->index);
14867 XDELETEVEC (rev_post_order);
14869 sbitmap_free (protected_bbs);
14871 free_dominance_info (CDI_DOMINATORS);
14874 /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX
14875 otherwise. If INSN has two call rtx, then store the second one in
14879 mips_call_expr_from_insn (rtx insn, rtx *second_call)
14884 if (!CALL_P (insn))
14887 x = PATTERN (insn);
14888 if (GET_CODE (x) == PARALLEL)
14890 /* Calls returning complex values have two CALL rtx. Look for the second
14891 one here, and return it via the SECOND_CALL arg. */
14892 x2 = XVECEXP (x, 0, 1);
14893 if (GET_CODE (x2) == SET)
14895 if (GET_CODE (x2) == CALL)
14898 x = XVECEXP (x, 0, 0);
14900 if (GET_CODE (x) == SET)
14902 gcc_assert (GET_CODE (x) == CALL);
14907 /* REG is set in DEF. See if the definition is one of the ways we load a
14908 register with a symbol address for a mips_use_pic_fn_addr_reg_p call.
14909 If it is, return the symbol reference of the function, otherwise return
14912 If RECURSE_P is true, use mips_find_pic_call_symbol to interpret
14913 the values of source registers, otherwise treat such registers as
14914 having an unknown value. */
14917 mips_pic_call_symbol_from_set (df_ref def, rtx reg, bool recurse_p)
14921 if (DF_REF_IS_ARTIFICIAL (def))
14924 def_insn = DF_REF_INSN (def);
14925 set = single_set (def_insn);
14926 if (set && rtx_equal_p (SET_DEST (set), reg))
14928 rtx note, src, symbol;
14930 /* First see whether the source is a plain symbol. This is used
14931 when calling symbols that are not lazily bound. */
14932 src = SET_SRC (set);
14933 if (GET_CODE (src) == SYMBOL_REF)
14936 /* Handle %call16 references. */
14937 symbol = mips_strip_unspec_call (src);
14940 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
14944 /* If we have something more complicated, look for a
14945 REG_EQUAL or REG_EQUIV note. */
14946 note = find_reg_equal_equiv_note (def_insn);
14947 if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF)
14948 return XEXP (note, 0);
14950 /* Follow at most one simple register copy. Such copies are
14951 interesting in cases like:
14955 locally_binding_fn (...);
14960 locally_binding_fn (...);
14962 locally_binding_fn (...);
14964 where the load of locally_binding_fn can legitimately be
14965 hoisted or shared. However, we do not expect to see complex
14966 chains of copies, so a full worklist solution to the problem
14967 would probably be overkill. */
14968 if (recurse_p && REG_P (src))
14969 return mips_find_pic_call_symbol (def_insn, src, false);
14975 /* Find the definition of the use of REG in INSN. See if the definition
14976 is one of the ways we load a register with a symbol address for a
14977 mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference
14978 of the function, otherwise return NULL_RTX. RECURSE_P is as for
14979 mips_pic_call_symbol_from_set. */
14982 mips_find_pic_call_symbol (rtx insn, rtx reg, bool recurse_p)
14985 struct df_link *defs;
14988 use = df_find_use (insn, regno_reg_rtx[REGNO (reg)]);
14991 defs = DF_REF_CHAIN (use);
14994 symbol = mips_pic_call_symbol_from_set (defs->ref, reg, recurse_p);
14998 /* If we have more than one definition, they need to be identical. */
14999 for (defs = defs->next; defs; defs = defs->next)
15003 other = mips_pic_call_symbol_from_set (defs->ref, reg, recurse_p);
15004 if (!rtx_equal_p (symbol, other))
15011 /* Replace the args_size operand of the call expression CALL with the
15012 call-attribute UNSPEC and fill in SYMBOL as the function symbol. */
15015 mips_annotate_pic_call_expr (rtx call, rtx symbol)
15019 args_size = XEXP (call, 1);
15020 XEXP (call, 1) = gen_rtx_UNSPEC (GET_MODE (args_size),
15021 gen_rtvec (2, args_size, symbol),
15025 /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See
15026 if instead of the arg_size argument it contains the call attributes. If
15027 yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function
15028 symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is
15032 mips_get_pic_call_symbol (rtx *operands, int args_size_opno)
15034 rtx args_size, symbol;
15036 if (!TARGET_RELAX_PIC_CALLS || args_size_opno == -1)
15039 args_size = operands[args_size_opno];
15040 if (GET_CODE (args_size) != UNSPEC)
15042 gcc_assert (XINT (args_size, 1) == UNSPEC_CALL_ATTR);
15044 symbol = XVECEXP (args_size, 0, 1);
15045 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
15047 operands[args_size_opno] = symbol;
15051 /* Use DF to annotate PIC indirect calls with the function symbol they
15055 mips_annotate_pic_calls (void)
15061 FOR_BB_INSNS (bb, insn)
15063 rtx call, reg, symbol, second_call;
15066 call = mips_call_expr_from_insn (insn, &second_call);
15069 gcc_assert (MEM_P (XEXP (call, 0)));
15070 reg = XEXP (XEXP (call, 0), 0);
15074 symbol = mips_find_pic_call_symbol (insn, reg, true);
15077 mips_annotate_pic_call_expr (call, symbol);
15079 mips_annotate_pic_call_expr (second_call, symbol);
15084 /* A temporary variable used by for_each_rtx callbacks, etc. */
15085 static rtx mips_sim_insn;
15087 /* A structure representing the state of the processor pipeline.
15088 Used by the mips_sim_* family of functions. */
15090 /* The maximum number of instructions that can be issued in a cycle.
15091 (Caches mips_issue_rate.) */
15092 unsigned int issue_rate;
15094 /* The current simulation time. */
15097 /* How many more instructions can be issued in the current cycle. */
15098 unsigned int insns_left;
15100 /* LAST_SET[X].INSN is the last instruction to set register X.
15101 LAST_SET[X].TIME is the time at which that instruction was issued.
15102 INSN is null if no instruction has yet set register X. */
15106 } last_set[FIRST_PSEUDO_REGISTER];
15108 /* The pipeline's current DFA state. */
15112 /* Reset STATE to the initial simulation state. */
15115 mips_sim_reset (struct mips_sim *state)
15117 curr_state = state->dfa_state;
15120 state->insns_left = state->issue_rate;
15121 memset (&state->last_set, 0, sizeof (state->last_set));
15122 state_reset (curr_state);
15124 targetm.sched.init (0, false, 0);
15125 advance_state (curr_state);
15128 /* Initialize STATE before its first use. DFA_STATE points to an
15129 allocated but uninitialized DFA state. */
15132 mips_sim_init (struct mips_sim *state, state_t dfa_state)
15134 if (targetm.sched.init_dfa_pre_cycle_insn)
15135 targetm.sched.init_dfa_pre_cycle_insn ();
15137 if (targetm.sched.init_dfa_post_cycle_insn)
15138 targetm.sched.init_dfa_post_cycle_insn ();
15140 state->issue_rate = mips_issue_rate ();
15141 state->dfa_state = dfa_state;
15142 mips_sim_reset (state);
15145 /* Advance STATE by one clock cycle. */
15148 mips_sim_next_cycle (struct mips_sim *state)
15150 curr_state = state->dfa_state;
15153 state->insns_left = state->issue_rate;
15154 advance_state (curr_state);
15157 /* Advance simulation state STATE until instruction INSN can read
15161 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
15163 unsigned int regno, end_regno;
15165 end_regno = END_REGNO (reg);
15166 for (regno = REGNO (reg); regno < end_regno; regno++)
15167 if (state->last_set[regno].insn != 0)
15171 t = (state->last_set[regno].time
15172 + insn_latency (state->last_set[regno].insn, insn));
15173 while (state->time < t)
15174 mips_sim_next_cycle (state);
15178 /* A for_each_rtx callback. If *X is a register, advance simulation state
15179 DATA until mips_sim_insn can read the register's value. */
15182 mips_sim_wait_regs_2 (rtx *x, void *data)
15185 mips_sim_wait_reg ((struct mips_sim *) data, mips_sim_insn, *x);
15189 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
15192 mips_sim_wait_regs_1 (rtx *x, void *data)
15194 for_each_rtx (x, mips_sim_wait_regs_2, data);
15197 /* Advance simulation state STATE until all of INSN's register
15198 dependencies are satisfied. */
15201 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
15203 mips_sim_insn = insn;
15204 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
15207 /* Advance simulation state STATE until the units required by
15208 instruction INSN are available. */
15211 mips_sim_wait_units (struct mips_sim *state, rtx insn)
15215 tmp_state = alloca (state_size ());
15216 while (state->insns_left == 0
15217 || (memcpy (tmp_state, state->dfa_state, state_size ()),
15218 state_transition (tmp_state, insn) >= 0))
15219 mips_sim_next_cycle (state);
15222 /* Advance simulation state STATE until INSN is ready to issue. */
15225 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
15227 mips_sim_wait_regs (state, insn);
15228 mips_sim_wait_units (state, insn);
15231 /* mips_sim_insn has just set X. Update the LAST_SET array
15232 in simulation state DATA. */
15235 mips_sim_record_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
15237 struct mips_sim *state;
15239 state = (struct mips_sim *) data;
15242 unsigned int regno, end_regno;
15244 end_regno = END_REGNO (x);
15245 for (regno = REGNO (x); regno < end_regno; regno++)
15247 state->last_set[regno].insn = mips_sim_insn;
15248 state->last_set[regno].time = state->time;
15253 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
15254 can issue immediately (i.e., that mips_sim_wait_insn has already
15258 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
15260 curr_state = state->dfa_state;
15262 state_transition (curr_state, insn);
15263 state->insns_left = targetm.sched.variable_issue (0, false, insn,
15264 state->insns_left);
15266 mips_sim_insn = insn;
15267 note_stores (PATTERN (insn), mips_sim_record_set, state);
15270 /* Simulate issuing a NOP in state STATE. */
15273 mips_sim_issue_nop (struct mips_sim *state)
15275 if (state->insns_left == 0)
15276 mips_sim_next_cycle (state);
15277 state->insns_left--;
15280 /* Update simulation state STATE so that it's ready to accept the instruction
15281 after INSN. INSN should be part of the main rtl chain, not a member of a
15285 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
15287 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
15289 mips_sim_issue_nop (state);
15291 switch (GET_CODE (SEQ_BEGIN (insn)))
15295 /* We can't predict the processor state after a call or label. */
15296 mips_sim_reset (state);
15300 /* The delay slots of branch likely instructions are only executed
15301 when the branch is taken. Therefore, if the caller has simulated
15302 the delay slot instruction, STATE does not really reflect the state
15303 of the pipeline for the instruction after the delay slot. Also,
15304 branch likely instructions tend to incur a penalty when not taken,
15305 so there will probably be an extra delay between the branch and
15306 the instruction after the delay slot. */
15307 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
15308 mips_sim_reset (state);
15316 /* Use simulator state STATE to calculate the execution time of
15317 instruction sequence SEQ. */
15319 static unsigned int
15320 mips_seq_time (struct mips_sim *state, rtx seq)
15322 mips_sim_reset (state);
15323 for (rtx insn = seq; insn; insn = NEXT_INSN (insn))
15325 mips_sim_wait_insn (state, insn);
15326 mips_sim_issue_insn (state, insn);
15328 return state->time;
15331 /* Return the execution-time cost of mips_tuning_info.fast_mult_zero_zero_p
15332 setting SETTING, using STATE to simulate instruction sequences. */
15334 static unsigned int
15335 mips_mult_zero_zero_cost (struct mips_sim *state, bool setting)
15337 mips_tuning_info.fast_mult_zero_zero_p = setting;
15340 enum machine_mode dword_mode = TARGET_64BIT ? TImode : DImode;
15341 rtx hilo = gen_rtx_REG (dword_mode, MD_REG_FIRST);
15342 mips_emit_move_or_split (hilo, const0_rtx, SPLIT_FOR_SPEED);
15344 /* If the target provides mulsidi3_32bit then that's the most likely
15345 consumer of the result. Test for bypasses. */
15346 if (dword_mode == DImode && HAVE_maddsidi4)
15348 rtx gpr = gen_rtx_REG (SImode, GP_REG_FIRST + 4);
15349 emit_insn (gen_maddsidi4 (hilo, gpr, gpr, hilo));
15352 unsigned int time = mips_seq_time (state, get_insns ());
15357 /* Check the relative speeds of "MULT $0,$0" and "MTLO $0; MTHI $0"
15358 and set up mips_tuning_info.fast_mult_zero_zero_p accordingly.
15359 Prefer MULT -- which is shorter -- in the event of a tie. */
15362 mips_set_fast_mult_zero_zero_p (struct mips_sim *state)
15365 /* No MTLO or MTHI available. */
15366 mips_tuning_info.fast_mult_zero_zero_p = true;
15369 unsigned int true_time = mips_mult_zero_zero_cost (state, true);
15370 unsigned int false_time = mips_mult_zero_zero_cost (state, false);
15371 mips_tuning_info.fast_mult_zero_zero_p = (true_time <= false_time);
15375 /* Set up costs based on the current architecture and tuning settings. */
15378 mips_set_tuning_info (void)
15380 if (mips_tuning_info.initialized_p
15381 && mips_tuning_info.arch == mips_arch
15382 && mips_tuning_info.tune == mips_tune
15383 && mips_tuning_info.mips16_p == TARGET_MIPS16)
15386 mips_tuning_info.arch = mips_arch;
15387 mips_tuning_info.tune = mips_tune;
15388 mips_tuning_info.mips16_p = TARGET_MIPS16;
15389 mips_tuning_info.initialized_p = true;
15393 struct mips_sim state;
15394 mips_sim_init (&state, alloca (state_size ()));
15396 mips_set_fast_mult_zero_zero_p (&state);
15401 /* Implement TARGET_EXPAND_TO_RTL_HOOK. */
15404 mips_expand_to_rtl_hook (void)
15406 /* We need to call this at a point where we can safely create sequences
15407 of instructions, so TARGET_OVERRIDE_OPTIONS is too early. We also
15408 need to call it at a point where the DFA infrastructure is not
15409 already in use, so we can't just call it lazily on demand.
15411 At present, mips_tuning_info is only needed during post-expand
15412 RTL passes such as split_insns, so this hook should be early enough.
15413 We may need to move the call elsewhere if mips_tuning_info starts
15414 to be used for other things (such as rtx_costs, or expanders that
15415 could be called during gimple optimization). */
15416 mips_set_tuning_info ();
15419 /* The VR4130 pipeline issues aligned pairs of instructions together,
15420 but it stalls the second instruction if it depends on the first.
15421 In order to cut down the amount of logic required, this dependence
15422 check is not based on a full instruction decode. Instead, any non-SPECIAL
15423 instruction is assumed to modify the register specified by bits 20-16
15424 (which is usually the "rt" field).
15426 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
15427 input, so we can end up with a false dependence between the branch
15428 and its delay slot. If this situation occurs in instruction INSN,
15429 try to avoid it by swapping rs and rt. */
15432 vr4130_avoid_branch_rt_conflict (rtx insn)
15436 first = SEQ_BEGIN (insn);
15437 second = SEQ_END (insn);
15439 && NONJUMP_INSN_P (second)
15440 && GET_CODE (PATTERN (first)) == SET
15441 && GET_CODE (SET_DEST (PATTERN (first))) == PC
15442 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
15444 /* Check for the right kind of condition. */
15445 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
15446 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
15447 && REG_P (XEXP (cond, 0))
15448 && REG_P (XEXP (cond, 1))
15449 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
15450 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
15452 /* SECOND mentions the rt register but not the rs register. */
15453 rtx tmp = XEXP (cond, 0);
15454 XEXP (cond, 0) = XEXP (cond, 1);
15455 XEXP (cond, 1) = tmp;
15460 /* Implement -mvr4130-align. Go through each basic block and simulate the
15461 processor pipeline. If we find that a pair of instructions could execute
15462 in parallel, and the first of those instructions is not 8-byte aligned,
15463 insert a nop to make it aligned. */
15466 vr4130_align_insns (void)
15468 struct mips_sim state;
15469 rtx insn, subinsn, last, last2, next;
15474 /* LAST is the last instruction before INSN to have a nonzero length.
15475 LAST2 is the last such instruction before LAST. */
15479 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
15482 mips_sim_init (&state, alloca (state_size ()));
15483 for (insn = get_insns (); insn != 0; insn = next)
15485 unsigned int length;
15487 next = NEXT_INSN (insn);
15489 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
15490 This isn't really related to the alignment pass, but we do it on
15491 the fly to avoid a separate instruction walk. */
15492 vr4130_avoid_branch_rt_conflict (insn);
15494 length = get_attr_length (insn);
15495 if (length > 0 && USEFUL_INSN_P (insn))
15496 FOR_EACH_SUBINSN (subinsn, insn)
15498 mips_sim_wait_insn (&state, subinsn);
15500 /* If we want this instruction to issue in parallel with the
15501 previous one, make sure that the previous instruction is
15502 aligned. There are several reasons why this isn't worthwhile
15503 when the second instruction is a call:
15505 - Calls are less likely to be performance critical,
15506 - There's a good chance that the delay slot can execute
15507 in parallel with the call.
15508 - The return address would then be unaligned.
15510 In general, if we're going to insert a nop between instructions
15511 X and Y, it's better to insert it immediately after X. That
15512 way, if the nop makes Y aligned, it will also align any labels
15513 between X and Y. */
15514 if (state.insns_left != state.issue_rate
15515 && !CALL_P (subinsn))
15517 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
15519 /* SUBINSN is the first instruction in INSN and INSN is
15520 aligned. We want to align the previous instruction
15521 instead, so insert a nop between LAST2 and LAST.
15523 Note that LAST could be either a single instruction
15524 or a branch with a delay slot. In the latter case,
15525 LAST, like INSN, is already aligned, but the delay
15526 slot must have some extra delay that stops it from
15527 issuing at the same time as the branch. We therefore
15528 insert a nop before the branch in order to align its
15530 gcc_assert (last2);
15531 emit_insn_after (gen_nop (), last2);
15534 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
15536 /* SUBINSN is the delay slot of INSN, but INSN is
15537 currently unaligned. Insert a nop between
15538 LAST and INSN to align it. */
15540 emit_insn_after (gen_nop (), last);
15544 mips_sim_issue_insn (&state, subinsn);
15546 mips_sim_finish_insn (&state, insn);
15548 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
15549 length = get_attr_length (insn);
15552 /* If the instruction is an asm statement or multi-instruction
15553 mips.md patern, the length is only an estimate. Insert an
15554 8 byte alignment after it so that the following instructions
15555 can be handled correctly. */
15556 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
15557 && (recog_memoized (insn) < 0 || length >= 8))
15559 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
15560 next = NEXT_INSN (next);
15561 mips_sim_next_cycle (&state);
15564 else if (length & 4)
15565 aligned_p = !aligned_p;
15570 /* See whether INSN is an aligned label. */
15571 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
15577 /* This structure records that the current function has a LO_SUM
15578 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
15579 the largest offset applied to BASE by all such LO_SUMs. */
15580 struct mips_lo_sum_offset {
15582 HOST_WIDE_INT offset;
15585 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
15588 mips_hash_base (rtx base)
15590 int do_not_record_p;
15592 return hash_rtx (base, GET_MODE (base), &do_not_record_p, NULL, false);
15595 /* Hash-table callbacks for mips_lo_sum_offsets. */
15598 mips_lo_sum_offset_hash (const void *entry)
15600 return mips_hash_base (((const struct mips_lo_sum_offset *) entry)->base);
15604 mips_lo_sum_offset_eq (const void *entry, const void *value)
15606 return rtx_equal_p (((const struct mips_lo_sum_offset *) entry)->base,
15607 (const_rtx) value);
15610 /* Look up symbolic constant X in HTAB, which is a hash table of
15611 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
15612 paired with a recorded LO_SUM, otherwise record X in the table. */
15615 mips_lo_sum_offset_lookup (htab_t htab, rtx x, enum insert_option option)
15619 struct mips_lo_sum_offset *entry;
15621 /* Split X into a base and offset. */
15622 split_const (x, &base, &offset);
15623 if (UNSPEC_ADDRESS_P (base))
15624 base = UNSPEC_ADDRESS (base);
15626 /* Look up the base in the hash table. */
15627 slot = htab_find_slot_with_hash (htab, base, mips_hash_base (base), option);
15631 entry = (struct mips_lo_sum_offset *) *slot;
15632 if (option == INSERT)
15636 entry = XNEW (struct mips_lo_sum_offset);
15637 entry->base = base;
15638 entry->offset = INTVAL (offset);
15643 if (INTVAL (offset) > entry->offset)
15644 entry->offset = INTVAL (offset);
15647 return INTVAL (offset) <= entry->offset;
15650 /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table.
15651 Record every LO_SUM in *LOC. */
15654 mips_record_lo_sum (rtx *loc, void *data)
15656 if (GET_CODE (*loc) == LO_SUM)
15657 mips_lo_sum_offset_lookup ((htab_t) data, XEXP (*loc, 1), INSERT);
15661 /* Return true if INSN is a SET of an orphaned high-part relocation.
15662 HTAB is a hash table of mips_lo_sum_offsets that describes all the
15663 LO_SUMs in the current function. */
15666 mips_orphaned_high_part_p (htab_t htab, rtx insn)
15668 enum mips_symbol_type type;
15671 set = single_set (insn);
15674 /* Check for %his. */
15676 if (GET_CODE (x) == HIGH
15677 && absolute_symbolic_operand (XEXP (x, 0), VOIDmode))
15678 return !mips_lo_sum_offset_lookup (htab, XEXP (x, 0), NO_INSERT);
15680 /* Check for local %gots (and %got_pages, which is redundant but OK). */
15681 if (GET_CODE (x) == UNSPEC
15682 && XINT (x, 1) == UNSPEC_LOAD_GOT
15683 && mips_symbolic_constant_p (XVECEXP (x, 0, 1),
15684 SYMBOL_CONTEXT_LEA, &type)
15685 && type == SYMBOL_GOTOFF_PAGE)
15686 return !mips_lo_sum_offset_lookup (htab, XVECEXP (x, 0, 1), NO_INSERT);
15691 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
15692 INSN and a previous instruction, avoid it by inserting nops after
15695 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
15696 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
15697 before using the value of that register. *HILO_DELAY counts the
15698 number of instructions since the last hilo hazard (that is,
15699 the number of instructions since the last MFLO or MFHI).
15701 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
15702 for the next instruction.
15704 LO_REG is an rtx for the LO register, used in dependence checking. */
15707 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
15708 rtx *delayed_reg, rtx lo_reg)
15713 pattern = PATTERN (insn);
15715 /* Do not put the whole function in .set noreorder if it contains
15716 an asm statement. We don't know whether there will be hazards
15717 between the asm statement and the gcc-generated code. */
15718 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
15719 cfun->machine->all_noreorder_p = false;
15721 /* Ignore zero-length instructions (barriers and the like). */
15722 ninsns = get_attr_length (insn) / 4;
15726 /* Work out how many nops are needed. Note that we only care about
15727 registers that are explicitly mentioned in the instruction's pattern.
15728 It doesn't matter that calls use the argument registers or that they
15729 clobber hi and lo. */
15730 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
15731 nops = 2 - *hilo_delay;
15732 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
15737 /* Insert the nops between this instruction and the previous one.
15738 Each new nop takes us further from the last hilo hazard. */
15739 *hilo_delay += nops;
15741 emit_insn_after (gen_hazard_nop (), after);
15743 /* Set up the state for the next instruction. */
15744 *hilo_delay += ninsns;
15746 if (INSN_CODE (insn) >= 0)
15747 switch (get_attr_hazard (insn))
15757 set = single_set (insn);
15759 *delayed_reg = SET_DEST (set);
15764 /* Go through the instruction stream and insert nops where necessary.
15765 Also delete any high-part relocations whose partnering low parts
15766 are now all dead. See if the whole function can then be put into
15767 .set noreorder and .set nomacro. */
15770 mips_reorg_process_insns (void)
15772 rtx insn, last_insn, subinsn, next_insn, lo_reg, delayed_reg;
15776 /* Force all instructions to be split into their final form. */
15777 split_all_insns_noflow ();
15779 /* Recalculate instruction lengths without taking nops into account. */
15780 cfun->machine->ignore_hazard_length_p = true;
15781 shorten_branches (get_insns ());
15783 cfun->machine->all_noreorder_p = true;
15785 /* We don't track MIPS16 PC-relative offsets closely enough to make
15786 a good job of "set .noreorder" code in MIPS16 mode. */
15788 cfun->machine->all_noreorder_p = false;
15790 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
15791 if (!TARGET_EXPLICIT_RELOCS)
15792 cfun->machine->all_noreorder_p = false;
15794 /* Profiled functions can't be all noreorder because the profiler
15795 support uses assembler macros. */
15797 cfun->machine->all_noreorder_p = false;
15799 /* Code compiled with -mfix-vr4120 or -mfix-24k can't be all noreorder
15800 because we rely on the assembler to work around some errata. */
15801 if (TARGET_FIX_VR4120 || TARGET_FIX_24K)
15802 cfun->machine->all_noreorder_p = false;
15804 /* The same is true for -mfix-vr4130 if we might generate MFLO or
15805 MFHI instructions. Note that we avoid using MFLO and MFHI if
15806 the VR4130 MACC and DMACC instructions are available instead;
15807 see the *mfhilo_{si,di}_macc patterns. */
15808 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
15809 cfun->machine->all_noreorder_p = false;
15811 htab = htab_create (37, mips_lo_sum_offset_hash,
15812 mips_lo_sum_offset_eq, free);
15814 /* Make a first pass over the instructions, recording all the LO_SUMs. */
15815 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
15816 FOR_EACH_SUBINSN (subinsn, insn)
15817 if (USEFUL_INSN_P (subinsn))
15818 for_each_rtx (&PATTERN (subinsn), mips_record_lo_sum, htab);
15823 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
15825 /* Make a second pass over the instructions. Delete orphaned
15826 high-part relocations or turn them into NOPs. Avoid hazards
15827 by inserting NOPs. */
15828 for (insn = get_insns (); insn != 0; insn = next_insn)
15830 next_insn = NEXT_INSN (insn);
15831 if (USEFUL_INSN_P (insn))
15833 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
15835 /* If we find an orphaned high-part relocation in a delay
15836 slot, it's easier to turn that instruction into a NOP than
15837 to delete it. The delay slot will be a NOP either way. */
15838 FOR_EACH_SUBINSN (subinsn, insn)
15839 if (INSN_P (subinsn))
15841 if (mips_orphaned_high_part_p (htab, subinsn))
15843 PATTERN (subinsn) = gen_nop ();
15844 INSN_CODE (subinsn) = CODE_FOR_nop;
15846 mips_avoid_hazard (last_insn, subinsn, &hilo_delay,
15847 &delayed_reg, lo_reg);
15853 /* INSN is a single instruction. Delete it if it's an
15854 orphaned high-part relocation. */
15855 if (mips_orphaned_high_part_p (htab, insn))
15856 delete_insn (insn);
15857 /* Also delete cache barriers if the last instruction
15858 was an annulled branch. INSN will not be speculatively
15860 else if (recog_memoized (insn) == CODE_FOR_r10k_cache_barrier
15862 && JUMP_P (SEQ_BEGIN (last_insn))
15863 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn)))
15864 delete_insn (insn);
15867 mips_avoid_hazard (last_insn, insn, &hilo_delay,
15868 &delayed_reg, lo_reg);
15875 htab_delete (htab);
15878 /* Return true if the function has a long branch instruction. */
15881 mips_has_long_branch_p (void)
15886 /* We need up-to-date instruction lengths. */
15887 shorten_branches (get_insns ());
15889 /* Look for a branch that is longer than normal. The normal length for
15890 non-MIPS16 branches is 8, because the length includes the delay slot.
15891 It is 4 for MIPS16, because MIPS16 branches are extended instructions,
15892 but they have no delay slot. */
15893 normal_length = (TARGET_MIPS16 ? 4 : 8);
15894 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
15895 FOR_EACH_SUBINSN (subinsn, insn)
15896 if (JUMP_P (subinsn)
15897 && USEFUL_INSN_P (subinsn)
15898 && get_attr_length (subinsn) > normal_length
15899 && (any_condjump_p (subinsn) || any_uncondjump_p (subinsn)))
15905 /* If we are using a GOT, but have not decided to use a global pointer yet,
15906 see whether we need one to implement long branches. Convert the ghost
15907 global-pointer instructions into real ones if so. */
15910 mips_expand_ghost_gp_insns (void)
15912 /* Quick exit if we already know that we will or won't need a
15914 if (!TARGET_USE_GOT
15915 || cfun->machine->global_pointer == INVALID_REGNUM
15916 || mips_must_initialize_gp_p ())
15919 /* Run a full check for long branches. */
15920 if (!mips_has_long_branch_p ())
15923 /* We've now established that we need $gp. */
15924 cfun->machine->must_initialize_gp_p = true;
15925 split_all_insns_noflow ();
15930 /* Subroutine of mips_reorg to manage passes that require DF. */
15933 mips_df_reorg (void)
15935 /* Create def-use chains. */
15936 df_set_flags (DF_EQ_NOTES);
15937 df_chain_add_problem (DF_UD_CHAIN);
15940 if (TARGET_RELAX_PIC_CALLS)
15941 mips_annotate_pic_calls ();
15943 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE)
15944 r10k_insert_cache_barriers ();
15946 df_finish_pass (false);
15949 /* Emit code to load LABEL_REF SRC into MIPS16 register DEST. This is
15950 called very late in mips_reorg, but the caller is required to run
15951 mips16_lay_out_constants on the result. */
15954 mips16_load_branch_target (rtx dest, rtx src)
15956 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
15960 if (mips_cfun_has_cprestore_slot_p ())
15961 mips_emit_move (dest, mips_cprestore_slot (dest, true));
15963 mips_emit_move (dest, pic_offset_table_rtx);
15964 page = mips_unspec_address (src, SYMBOL_GOTOFF_PAGE);
15965 low = mips_unspec_address (src, SYMBOL_GOT_PAGE_OFST);
15966 emit_insn (gen_rtx_SET (VOIDmode, dest,
15967 PMODE_INSN (gen_unspec_got, (dest, page))));
15968 emit_insn (gen_rtx_SET (VOIDmode, dest,
15969 gen_rtx_LO_SUM (Pmode, dest, low)));
15973 src = mips_unspec_address (src, SYMBOL_ABSOLUTE);
15974 mips_emit_move (dest, src);
15978 /* If we're compiling a MIPS16 function, look for and split any long branches.
15979 This must be called after all other instruction modifications in
15983 mips16_split_long_branches (void)
15985 bool something_changed;
15987 if (!TARGET_MIPS16)
15990 /* Loop until the alignments for all targets are sufficient. */
15995 shorten_branches (get_insns ());
15996 something_changed = false;
15997 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
15999 && USEFUL_INSN_P (insn)
16000 && get_attr_length (insn) > 8
16001 && (any_condjump_p (insn) || any_uncondjump_p (insn)))
16003 rtx old_label, new_label, temp, saved_temp;
16004 rtx target, jump, jump_sequence;
16008 /* Free up a MIPS16 register by saving it in $1. */
16009 saved_temp = gen_rtx_REG (Pmode, AT_REGNUM);
16010 temp = gen_rtx_REG (Pmode, GP_REG_FIRST + 2);
16011 emit_move_insn (saved_temp, temp);
16013 /* Load the branch target into TEMP. */
16014 old_label = JUMP_LABEL (insn);
16015 target = gen_rtx_LABEL_REF (Pmode, old_label);
16016 mips16_load_branch_target (temp, target);
16018 /* Jump to the target and restore the register's
16020 jump = emit_jump_insn (PMODE_INSN (gen_indirect_jump_and_restore,
16021 (temp, temp, saved_temp)));
16022 JUMP_LABEL (jump) = old_label;
16023 LABEL_NUSES (old_label)++;
16025 /* Rewrite any symbolic references that are supposed to use
16026 a PC-relative constant pool. */
16027 mips16_lay_out_constants (false);
16029 if (simplejump_p (insn))
16030 /* We're going to replace INSN with a longer form. */
16031 new_label = NULL_RTX;
16034 /* Create a branch-around label for the original
16036 new_label = gen_label_rtx ();
16037 emit_label (new_label);
16040 jump_sequence = get_insns ();
16043 emit_insn_after (jump_sequence, insn);
16045 invert_jump (insn, new_label, false);
16047 delete_insn (insn);
16048 something_changed = true;
16051 while (something_changed);
16054 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
16059 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during
16060 insn splitting in mips16_lay_out_constants, DF insn info is only kept up
16061 to date if the CFG is available. */
16062 if (mips_cfg_in_reorg ())
16063 compute_bb_for_insn ();
16064 mips16_lay_out_constants (true);
16065 if (mips_cfg_in_reorg ())
16068 free_bb_for_insn ();
16071 if (optimize > 0 && flag_delayed_branch)
16073 cleanup_barriers ();
16074 dbr_schedule (get_insns ());
16076 mips_reorg_process_insns ();
16078 && TARGET_EXPLICIT_RELOCS
16080 && TARGET_VR4130_ALIGN)
16081 vr4130_align_insns ();
16082 if (mips_expand_ghost_gp_insns ())
16083 /* The expansion could invalidate some of the VR4130 alignment
16084 optimizations, but this should be an extremely rare case anyhow. */
16085 mips_reorg_process_insns ();
16086 mips16_split_long_branches ();
16089 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
16090 in order to avoid duplicating too much logic from elsewhere. */
16093 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
16094 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
16097 rtx this_rtx, temp1, temp2, insn, fnaddr;
16098 bool use_sibcall_p;
16100 /* Pretend to be a post-reload pass while generating rtl. */
16101 reload_completed = 1;
16103 /* Mark the end of the (empty) prologue. */
16104 emit_note (NOTE_INSN_PROLOGUE_END);
16106 /* Determine if we can use a sibcall to call FUNCTION directly. */
16107 fnaddr = XEXP (DECL_RTL (function), 0);
16108 use_sibcall_p = (mips_function_ok_for_sibcall (function, NULL)
16109 && const_call_insn_operand (fnaddr, Pmode));
16111 /* Determine if we need to load FNADDR from the GOT. */
16113 && (mips_got_symbol_type_p
16114 (mips_classify_symbol (fnaddr, SYMBOL_CONTEXT_LEA))))
16116 /* Pick a global pointer. Use a call-clobbered register if
16117 TARGET_CALL_SAVED_GP. */
16118 cfun->machine->global_pointer
16119 = TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM;
16120 cfun->machine->must_initialize_gp_p = true;
16121 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
16123 /* Set up the global pointer for n32 or n64 abicalls. */
16124 mips_emit_loadgp ();
16127 /* We need two temporary registers in some cases. */
16128 temp1 = gen_rtx_REG (Pmode, 2);
16129 temp2 = gen_rtx_REG (Pmode, 3);
16131 /* Find out which register contains the "this" pointer. */
16132 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
16133 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
16135 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST);
16137 /* Add DELTA to THIS_RTX. */
16140 rtx offset = GEN_INT (delta);
16141 if (!SMALL_OPERAND (delta))
16143 mips_emit_move (temp1, offset);
16146 emit_insn (gen_add3_insn (this_rtx, this_rtx, offset));
16149 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
16150 if (vcall_offset != 0)
16154 /* Set TEMP1 to *THIS_RTX. */
16155 mips_emit_move (temp1, gen_rtx_MEM (Pmode, this_rtx));
16157 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
16158 addr = mips_add_offset (temp2, temp1, vcall_offset);
16160 /* Load the offset and add it to THIS_RTX. */
16161 mips_emit_move (temp1, gen_rtx_MEM (Pmode, addr));
16162 emit_insn (gen_add3_insn (this_rtx, this_rtx, temp1));
16165 /* Jump to the target function. Use a sibcall if direct jumps are
16166 allowed, otherwise load the address into a register first. */
16169 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
16170 SIBLING_CALL_P (insn) = 1;
16174 /* This is messy. GAS treats "la $25,foo" as part of a call
16175 sequence and may allow a global "foo" to be lazily bound.
16176 The general move patterns therefore reject this combination.
16178 In this context, lazy binding would actually be OK
16179 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
16180 TARGET_CALL_SAVED_GP; see mips_load_call_address.
16181 We must therefore load the address via a temporary
16182 register if mips_dangerous_for_la25_p.
16184 If we jump to the temporary register rather than $25,
16185 the assembler can use the move insn to fill the jump's
16188 We can use the same technique for MIPS16 code, where $25
16189 is not a valid JR register. */
16190 if (TARGET_USE_PIC_FN_ADDR_REG
16192 && !mips_dangerous_for_la25_p (fnaddr))
16193 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
16194 mips_load_call_address (MIPS_CALL_SIBCALL, temp1, fnaddr);
16196 if (TARGET_USE_PIC_FN_ADDR_REG
16197 && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
16198 mips_emit_move (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
16199 emit_jump_insn (gen_indirect_jump (temp1));
16202 /* Run just enough of rest_of_compilation. This sequence was
16203 "borrowed" from alpha.c. */
16204 insn = get_insns ();
16205 split_all_insns_noflow ();
16206 mips16_lay_out_constants (true);
16207 shorten_branches (insn);
16208 final_start_function (insn, file, 1);
16209 final (insn, file, 1);
16210 final_end_function ();
16212 /* Clean up the vars set above. Note that final_end_function resets
16213 the global pointer for us. */
16214 reload_completed = 0;
16217 /* The last argument passed to mips_set_mips16_mode, or negative if the
16218 function hasn't been called yet. */
16219 static int was_mips16_p = -1;
16221 /* Set up the target-dependent global state so that it matches the
16222 current function's ISA mode. */
16225 mips_set_mips16_mode (int mips16_p)
16227 if (mips16_p == was_mips16_p)
16230 /* Restore base settings of various flags. */
16231 target_flags = mips_base_target_flags;
16232 flag_schedule_insns = mips_base_schedule_insns;
16233 flag_reorder_blocks_and_partition = mips_base_reorder_blocks_and_partition;
16234 flag_move_loop_invariants = mips_base_move_loop_invariants;
16235 align_loops = mips_base_align_loops;
16236 align_jumps = mips_base_align_jumps;
16237 align_functions = mips_base_align_functions;
16241 /* Switch to MIPS16 mode. */
16242 target_flags |= MASK_MIPS16;
16244 /* Turn off SYNCI if it was on, MIPS16 doesn't support it. */
16245 target_flags &= ~MASK_SYNCI;
16247 /* Don't run the scheduler before reload, since it tends to
16248 increase register pressure. */
16249 flag_schedule_insns = 0;
16251 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
16252 the whole function to be in a single section. */
16253 flag_reorder_blocks_and_partition = 0;
16255 /* Don't move loop invariants, because it tends to increase
16256 register pressure. It also introduces an extra move in cases
16257 where the constant is the first operand in a two-operand binary
16258 instruction, or when it forms a register argument to a functon
16260 flag_move_loop_invariants = 0;
16262 target_flags |= MASK_EXPLICIT_RELOCS;
16264 /* Experiments suggest we get the best overall section-anchor
16265 results from using the range of an unextended LW or SW. Code
16266 that makes heavy use of byte or short accesses can do better
16267 with ranges of 0...31 and 0...63 respectively, but most code is
16268 sensitive to the range of LW and SW instead. */
16269 targetm.min_anchor_offset = 0;
16270 targetm.max_anchor_offset = 127;
16272 targetm.const_anchor = 0;
16274 /* MIPS16 has no BAL instruction. */
16275 target_flags &= ~MASK_RELAX_PIC_CALLS;
16277 /* The R4000 errata don't apply to any known MIPS16 cores.
16278 It's simpler to make the R4000 fixes and MIPS16 mode
16279 mutually exclusive. */
16280 target_flags &= ~MASK_FIX_R4000;
16282 if (flag_pic && !TARGET_OLDABI)
16283 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
16286 sorry ("MIPS16 -mxgot code");
16288 if (TARGET_HARD_FLOAT_ABI && !TARGET_OLDABI)
16289 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
16293 /* Switch to normal (non-MIPS16) mode. */
16294 target_flags &= ~MASK_MIPS16;
16296 /* Provide default values for align_* for 64-bit targets. */
16299 if (align_loops == 0)
16301 if (align_jumps == 0)
16303 if (align_functions == 0)
16304 align_functions = 8;
16307 targetm.min_anchor_offset = -32768;
16308 targetm.max_anchor_offset = 32767;
16310 targetm.const_anchor = 0x8000;
16313 /* (Re)initialize MIPS target internals for new ISA. */
16314 mips_init_relocs ();
16318 if (!mips16_globals)
16319 mips16_globals = save_target_globals ();
16321 restore_target_globals (mips16_globals);
16324 restore_target_globals (&default_target_globals);
16326 was_mips16_p = mips16_p;
16329 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
16330 function should use the MIPS16 ISA and switch modes accordingly. */
16333 mips_set_current_function (tree fndecl)
16335 mips_set_mips16_mode (mips_use_mips16_mode_p (fndecl));
16338 /* Allocate a chunk of memory for per-function machine-dependent data. */
16340 static struct machine_function *
16341 mips_init_machine_status (void)
16343 return ggc_alloc_cleared_machine_function ();
16346 /* Return the processor associated with the given ISA level, or null
16347 if the ISA isn't valid. */
16349 static const struct mips_cpu_info *
16350 mips_cpu_info_from_isa (int isa)
16354 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
16355 if (mips_cpu_info_table[i].isa == isa)
16356 return mips_cpu_info_table + i;
16361 /* Return a mips_cpu_info entry determined by an option valued
16364 static const struct mips_cpu_info *
16365 mips_cpu_info_from_opt (int opt)
16369 case MIPS_ARCH_OPTION_FROM_ABI:
16370 /* 'from-abi' selects the most compatible architecture for the
16371 given ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit
16372 ABIs. For the EABIs, we have to decide whether we're using
16373 the 32-bit or 64-bit version. */
16374 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
16375 : ABI_NEEDS_64BIT_REGS ? 3
16376 : (TARGET_64BIT ? 3 : 1));
16378 case MIPS_ARCH_OPTION_NATIVE:
16379 gcc_unreachable ();
16382 return &mips_cpu_info_table[opt];
16386 /* Return a default mips_cpu_info entry, given that no -march= option
16387 was explicitly specified. */
16389 static const struct mips_cpu_info *
16390 mips_default_arch (void)
16392 #if defined (MIPS_CPU_STRING_DEFAULT)
16394 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
16395 if (strcmp (mips_cpu_info_table[i].name, MIPS_CPU_STRING_DEFAULT) == 0)
16396 return mips_cpu_info_table + i;
16397 gcc_unreachable ();
16398 #elif defined (MIPS_ISA_DEFAULT)
16399 return mips_cpu_info_from_isa (MIPS_ISA_DEFAULT);
16401 /* 'from-abi' makes a good default: you get whatever the ABI
16403 return mips_cpu_info_from_opt (MIPS_ARCH_OPTION_FROM_ABI);
16407 /* Set up globals to generate code for the ISA or processor
16408 described by INFO. */
16411 mips_set_architecture (const struct mips_cpu_info *info)
16415 mips_arch_info = info;
16416 mips_arch = info->cpu;
16417 mips_isa = info->isa;
16421 /* Likewise for tuning. */
16424 mips_set_tune (const struct mips_cpu_info *info)
16428 mips_tune_info = info;
16429 mips_tune = info->cpu;
16433 /* Implement TARGET_OPTION_OVERRIDE. */
16436 mips_option_override (void)
16438 int i, start, regno, mode;
16440 if (global_options_set.x_mips_isa_option)
16441 mips_isa_option_info = &mips_cpu_info_table[mips_isa_option];
16443 /* Process flags as though we were generating non-MIPS16 code. */
16444 mips_base_mips16 = TARGET_MIPS16;
16445 target_flags &= ~MASK_MIPS16;
16447 #ifdef SUBTARGET_OVERRIDE_OPTIONS
16448 SUBTARGET_OVERRIDE_OPTIONS;
16451 /* -mno-float overrides -mhard-float and -msoft-float. */
16452 if (TARGET_NO_FLOAT)
16454 target_flags |= MASK_SOFT_FLOAT_ABI;
16455 target_flags_explicit |= MASK_SOFT_FLOAT_ABI;
16458 if (TARGET_FLIP_MIPS16)
16459 TARGET_INTERLINK_MIPS16 = 1;
16461 /* Set the small data limit. */
16462 mips_small_data_threshold = (global_options_set.x_g_switch_value
16464 : MIPS_DEFAULT_GVALUE);
16466 /* The following code determines the architecture and register size.
16467 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
16468 The GAS and GCC code should be kept in sync as much as possible. */
16470 if (global_options_set.x_mips_arch_option)
16471 mips_set_architecture (mips_cpu_info_from_opt (mips_arch_option));
16473 if (mips_isa_option_info != 0)
16475 if (mips_arch_info == 0)
16476 mips_set_architecture (mips_isa_option_info);
16477 else if (mips_arch_info->isa != mips_isa_option_info->isa)
16478 error ("%<-%s%> conflicts with the other architecture options, "
16479 "which specify a %s processor",
16480 mips_isa_option_info->name,
16481 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
16484 if (mips_arch_info == 0)
16485 mips_set_architecture (mips_default_arch ());
16487 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
16488 error ("%<-march=%s%> is not compatible with the selected ABI",
16489 mips_arch_info->name);
16491 /* Optimize for mips_arch, unless -mtune selects a different processor. */
16492 if (global_options_set.x_mips_tune_option)
16493 mips_set_tune (mips_cpu_info_from_opt (mips_tune_option));
16495 if (mips_tune_info == 0)
16496 mips_set_tune (mips_arch_info);
16498 if ((target_flags_explicit & MASK_64BIT) != 0)
16500 /* The user specified the size of the integer registers. Make sure
16501 it agrees with the ABI and ISA. */
16502 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
16503 error ("%<-mgp64%> used with a 32-bit processor");
16504 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
16505 error ("%<-mgp32%> used with a 64-bit ABI");
16506 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
16507 error ("%<-mgp64%> used with a 32-bit ABI");
16511 /* Infer the integer register size from the ABI and processor.
16512 Restrict ourselves to 32-bit registers if that's all the
16513 processor has, or if the ABI cannot handle 64-bit registers. */
16514 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
16515 target_flags &= ~MASK_64BIT;
16517 target_flags |= MASK_64BIT;
16520 if ((target_flags_explicit & MASK_FLOAT64) != 0)
16522 if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
16523 error ("unsupported combination: %s", "-mfp64 -msingle-float");
16524 else if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
16525 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
16526 else if (!TARGET_64BIT && TARGET_FLOAT64)
16528 if (!ISA_HAS_MXHC1)
16529 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
16530 " the target supports the mfhc1 and mthc1 instructions");
16531 else if (mips_abi != ABI_32)
16532 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
16538 /* -msingle-float selects 32-bit float registers. Otherwise the
16539 float registers should be the same size as the integer ones. */
16540 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
16541 target_flags |= MASK_FLOAT64;
16543 target_flags &= ~MASK_FLOAT64;
16546 /* End of code shared with GAS. */
16548 /* If a -mlong* option was given, check that it matches the ABI,
16549 otherwise infer the -mlong* setting from the other options. */
16550 if ((target_flags_explicit & MASK_LONG64) != 0)
16554 if (mips_abi == ABI_N32)
16555 error ("%qs is incompatible with %qs", "-mabi=n32", "-mlong64");
16556 else if (mips_abi == ABI_32)
16557 error ("%qs is incompatible with %qs", "-mabi=32", "-mlong64");
16558 else if (mips_abi == ABI_O64 && TARGET_ABICALLS)
16559 /* We have traditionally allowed non-abicalls code to use
16560 an LP64 form of o64. However, it would take a bit more
16561 effort to support the combination of 32-bit GOT entries
16562 and 64-bit pointers, so we treat the abicalls case as
16564 error ("the combination of %qs and %qs is incompatible with %qs",
16565 "-mabi=o64", "-mabicalls", "-mlong64");
16569 if (mips_abi == ABI_64)
16570 error ("%qs is incompatible with %qs", "-mabi=64", "-mlong32");
16575 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
16576 target_flags |= MASK_LONG64;
16578 target_flags &= ~MASK_LONG64;
16581 if (!TARGET_OLDABI)
16582 flag_pcc_struct_return = 0;
16584 /* Decide which rtx_costs structure to use. */
16586 mips_cost = &mips_rtx_cost_optimize_size;
16588 mips_cost = &mips_rtx_cost_data[mips_tune];
16590 /* If the user hasn't specified a branch cost, use the processor's
16592 if (mips_branch_cost == 0)
16593 mips_branch_cost = mips_cost->branch_cost;
16595 /* If neither -mbranch-likely nor -mno-branch-likely was given
16596 on the command line, set MASK_BRANCHLIKELY based on the target
16597 architecture and tuning flags. Annulled delay slots are a
16598 size win, so we only consider the processor-specific tuning
16599 for !optimize_size. */
16600 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
16602 if (ISA_HAS_BRANCHLIKELY
16604 || (mips_tune_info->tune_flags & PTF_AVOID_BRANCHLIKELY) == 0))
16605 target_flags |= MASK_BRANCHLIKELY;
16607 target_flags &= ~MASK_BRANCHLIKELY;
16609 else if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
16610 warning (0, "the %qs architecture does not support branch-likely"
16611 " instructions", mips_arch_info->name);
16613 /* The effect of -mabicalls isn't defined for the EABI. */
16614 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
16616 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
16617 target_flags &= ~MASK_ABICALLS;
16620 /* PIC requires -mabicalls. */
16623 if (mips_abi == ABI_EABI)
16624 error ("cannot generate position-independent code for %qs",
16626 else if (!TARGET_ABICALLS)
16627 error ("position-independent code requires %qs", "-mabicalls");
16630 if (TARGET_ABICALLS_PIC2)
16631 /* We need to set flag_pic for executables as well as DSOs
16632 because we may reference symbols that are not defined in
16633 the final executable. (MIPS does not use things like
16634 copy relocs, for example.)
16636 There is a body of code that uses __PIC__ to distinguish
16637 between -mabicalls and -mno-abicalls code. The non-__PIC__
16638 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
16639 long as any indirect jumps use $25. */
16642 /* -mvr4130-align is a "speed over size" optimization: it usually produces
16643 faster code, but at the expense of more nops. Enable it at -O3 and
16645 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
16646 target_flags |= MASK_VR4130_ALIGN;
16648 /* Prefer a call to memcpy over inline code when optimizing for size,
16649 though see MOVE_RATIO in mips.h. */
16650 if (optimize_size && (target_flags_explicit & MASK_MEMCPY) == 0)
16651 target_flags |= MASK_MEMCPY;
16653 /* If we have a nonzero small-data limit, check that the -mgpopt
16654 setting is consistent with the other target flags. */
16655 if (mips_small_data_threshold > 0)
16659 if (!TARGET_EXPLICIT_RELOCS)
16660 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
16662 TARGET_LOCAL_SDATA = false;
16663 TARGET_EXTERN_SDATA = false;
16667 if (TARGET_VXWORKS_RTP)
16668 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
16670 if (TARGET_ABICALLS)
16671 warning (0, "cannot use small-data accesses for %qs",
16676 /* Make sure that the user didn't turn off paired single support when
16677 MIPS-3D support is requested. */
16679 && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
16680 && !TARGET_PAIRED_SINGLE_FLOAT)
16681 error ("%<-mips3d%> requires %<-mpaired-single%>");
16683 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
16685 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
16687 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
16688 and TARGET_HARD_FLOAT_ABI are both true. */
16689 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT_ABI))
16690 error ("%qs must be used with %qs",
16691 TARGET_MIPS3D ? "-mips3d" : "-mpaired-single",
16692 TARGET_HARD_FLOAT_ABI ? "-mfp64" : "-mhard-float");
16694 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
16696 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_HAS_PAIRED_SINGLE)
16697 warning (0, "the %qs architecture does not support paired-single"
16698 " instructions", mips_arch_info->name);
16700 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
16701 && !TARGET_CACHE_BUILTIN)
16703 error ("%qs requires a target that provides the %qs instruction",
16704 "-mr10k-cache-barrier", "cache");
16705 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE;
16708 /* If TARGET_DSPR2, enable MASK_DSP. */
16710 target_flags |= MASK_DSP;
16712 /* .eh_frame addresses should be the same width as a C pointer.
16713 Most MIPS ABIs support only one pointer size, so the assembler
16714 will usually know exactly how big an .eh_frame address is.
16716 Unfortunately, this is not true of the 64-bit EABI. The ABI was
16717 originally defined to use 64-bit pointers (i.e. it is LP64), and
16718 this is still the default mode. However, we also support an n32-like
16719 ILP32 mode, which is selected by -mlong32. The problem is that the
16720 assembler has traditionally not had an -mlong option, so it has
16721 traditionally not known whether we're using the ILP32 or LP64 form.
16723 As it happens, gas versions up to and including 2.19 use _32-bit_
16724 addresses for EABI64 .cfi_* directives. This is wrong for the
16725 default LP64 mode, so we can't use the directives by default.
16726 Moreover, since gas's current behavior is at odds with gcc's
16727 default behavior, it seems unwise to rely on future versions
16728 of gas behaving the same way. We therefore avoid using .cfi
16729 directives for -mlong32 as well. */
16730 if (mips_abi == ABI_EABI && TARGET_64BIT)
16731 flag_dwarf2_cfi_asm = 0;
16733 /* .cfi_* directives generate a read-only section, so fall back on
16734 manual .eh_frame creation if we need the section to be writable. */
16735 if (TARGET_WRITABLE_EH_FRAME)
16736 flag_dwarf2_cfi_asm = 0;
16738 mips_init_print_operand_punct ();
16740 /* Set up array to map GCC register number to debug register number.
16741 Ignore the special purpose register numbers. */
16743 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
16745 mips_dbx_regno[i] = IGNORED_DWARF_REGNUM;
16746 if (GP_REG_P (i) || FP_REG_P (i) || ALL_COP_REG_P (i))
16747 mips_dwarf_regno[i] = i;
16749 mips_dwarf_regno[i] = INVALID_REGNUM;
16752 start = GP_DBX_FIRST - GP_REG_FIRST;
16753 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
16754 mips_dbx_regno[i] = i + start;
16756 start = FP_DBX_FIRST - FP_REG_FIRST;
16757 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
16758 mips_dbx_regno[i] = i + start;
16760 /* Accumulator debug registers use big-endian ordering. */
16761 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
16762 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
16763 mips_dwarf_regno[HI_REGNUM] = MD_REG_FIRST + 0;
16764 mips_dwarf_regno[LO_REGNUM] = MD_REG_FIRST + 1;
16765 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
16767 mips_dwarf_regno[i + TARGET_LITTLE_ENDIAN] = i;
16768 mips_dwarf_regno[i + TARGET_BIG_ENDIAN] = i + 1;
16771 /* Set up mips_hard_regno_mode_ok. */
16772 for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
16773 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
16774 mips_hard_regno_mode_ok[mode][regno]
16775 = mips_hard_regno_mode_ok_p (regno, (enum machine_mode) mode);
16777 /* Function to allocate machine-dependent function status. */
16778 init_machine_status = &mips_init_machine_status;
16780 /* Default to working around R4000 errata only if the processor
16781 was selected explicitly. */
16782 if ((target_flags_explicit & MASK_FIX_R4000) == 0
16783 && strcmp (mips_arch_info->name, "r4000") == 0)
16784 target_flags |= MASK_FIX_R4000;
16786 /* Default to working around R4400 errata only if the processor
16787 was selected explicitly. */
16788 if ((target_flags_explicit & MASK_FIX_R4400) == 0
16789 && strcmp (mips_arch_info->name, "r4400") == 0)
16790 target_flags |= MASK_FIX_R4400;
16792 /* Default to working around R10000 errata only if the processor
16793 was selected explicitly. */
16794 if ((target_flags_explicit & MASK_FIX_R10000) == 0
16795 && strcmp (mips_arch_info->name, "r10000") == 0)
16796 target_flags |= MASK_FIX_R10000;
16798 /* Make sure that branch-likely instructions available when using
16799 -mfix-r10000. The instructions are not available if either:
16801 1. -mno-branch-likely was passed.
16802 2. The selected ISA does not support branch-likely and
16803 the command line does not include -mbranch-likely. */
16804 if (TARGET_FIX_R10000
16805 && ((target_flags_explicit & MASK_BRANCHLIKELY) == 0
16806 ? !ISA_HAS_BRANCHLIKELY
16807 : !TARGET_BRANCHLIKELY))
16808 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
16810 if (TARGET_SYNCI && !ISA_HAS_SYNCI)
16812 warning (0, "the %qs architecture does not support the synci "
16813 "instruction", mips_arch_info->name);
16814 target_flags &= ~MASK_SYNCI;
16817 /* Only optimize PIC indirect calls if they are actually required. */
16818 if (!TARGET_USE_GOT || !TARGET_EXPLICIT_RELOCS)
16819 target_flags &= ~MASK_RELAX_PIC_CALLS;
16821 /* Save base state of options. */
16822 mips_base_target_flags = target_flags;
16823 mips_base_schedule_insns = flag_schedule_insns;
16824 mips_base_reorder_blocks_and_partition = flag_reorder_blocks_and_partition;
16825 mips_base_move_loop_invariants = flag_move_loop_invariants;
16826 mips_base_align_loops = align_loops;
16827 mips_base_align_jumps = align_jumps;
16828 mips_base_align_functions = align_functions;
16830 /* Now select the ISA mode.
16832 Do all CPP-sensitive stuff in non-MIPS16 mode; we'll switch to
16833 MIPS16 mode afterwards if need be. */
16834 mips_set_mips16_mode (false);
16837 /* Swap the register information for registers I and I + 1, which
16838 currently have the wrong endianness. Note that the registers'
16839 fixedness and call-clobberedness might have been set on the
16843 mips_swap_registers (unsigned int i)
16848 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
16849 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
16851 SWAP_INT (fixed_regs[i], fixed_regs[i + 1]);
16852 SWAP_INT (call_used_regs[i], call_used_regs[i + 1]);
16853 SWAP_INT (call_really_used_regs[i], call_really_used_regs[i + 1]);
16854 SWAP_STRING (reg_names[i], reg_names[i + 1]);
16860 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
16863 mips_conditional_register_usage (void)
16868 /* These DSP control register fields are global. */
16869 global_regs[CCDSP_PO_REGNUM] = 1;
16870 global_regs[CCDSP_SC_REGNUM] = 1;
16873 AND_COMPL_HARD_REG_SET (accessible_reg_set,
16874 reg_class_contents[(int) DSP_ACC_REGS]);
16876 if (!TARGET_HARD_FLOAT)
16878 AND_COMPL_HARD_REG_SET (accessible_reg_set,
16879 reg_class_contents[(int) FP_REGS]);
16880 AND_COMPL_HARD_REG_SET (accessible_reg_set,
16881 reg_class_contents[(int) ST_REGS]);
16883 else if (!ISA_HAS_8CC)
16885 /* We only have a single condition-code register. We implement
16886 this by fixing all the condition-code registers and generating
16887 RTL that refers directly to ST_REG_FIRST. */
16888 AND_COMPL_HARD_REG_SET (accessible_reg_set,
16889 reg_class_contents[(int) ST_REGS]);
16890 SET_HARD_REG_BIT (accessible_reg_set, FPSW_REGNUM);
16891 fixed_regs[FPSW_REGNUM] = call_used_regs[FPSW_REGNUM] = 1;
16895 /* In MIPS16 mode, we permit the $t temporary registers to be used
16896 for reload. We prohibit the unused $s registers, since they
16897 are call-saved, and saving them via a MIPS16 register would
16898 probably waste more time than just reloading the value. */
16899 fixed_regs[18] = call_used_regs[18] = 1;
16900 fixed_regs[19] = call_used_regs[19] = 1;
16901 fixed_regs[20] = call_used_regs[20] = 1;
16902 fixed_regs[21] = call_used_regs[21] = 1;
16903 fixed_regs[22] = call_used_regs[22] = 1;
16904 fixed_regs[23] = call_used_regs[23] = 1;
16905 fixed_regs[26] = call_used_regs[26] = 1;
16906 fixed_regs[27] = call_used_regs[27] = 1;
16907 fixed_regs[30] = call_used_regs[30] = 1;
16909 /* Do not allow HI and LO to be treated as register operands.
16910 There are no MTHI or MTLO instructions (or any real need
16911 for them) and one-way registers cannot easily be reloaded. */
16912 AND_COMPL_HARD_REG_SET (operand_reg_set,
16913 reg_class_contents[(int) MD_REGS]);
16915 /* $f20-$f23 are call-clobbered for n64. */
16916 if (mips_abi == ABI_64)
16919 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
16920 call_really_used_regs[regno] = call_used_regs[regno] = 1;
16922 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
16924 if (mips_abi == ABI_N32)
16927 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
16928 call_really_used_regs[regno] = call_used_regs[regno] = 1;
16930 /* Make sure that double-register accumulator values are correctly
16931 ordered for the current endianness. */
16932 if (TARGET_LITTLE_ENDIAN)
16934 unsigned int regno;
16936 mips_swap_registers (MD_REG_FIRST);
16937 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno += 2)
16938 mips_swap_registers (regno);
16942 /* When generating MIPS16 code, we want to allocate $24 (T_REG) before
16943 other registers for instructions for which it is possible. This
16944 encourages the compiler to use CMP in cases where an XOR would
16945 require some register shuffling. */
16948 mips_order_regs_for_local_alloc (void)
16952 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
16953 reg_alloc_order[i] = i;
16957 /* It really doesn't matter where we put register 0, since it is
16958 a fixed register anyhow. */
16959 reg_alloc_order[0] = 24;
16960 reg_alloc_order[24] = 0;
16964 /* Implement EH_USES. */
16967 mips_eh_uses (unsigned int regno)
16969 if (reload_completed && !TARGET_ABSOLUTE_JUMPS)
16971 /* We need to force certain registers to be live in order to handle
16972 PIC long branches correctly. See mips_must_initialize_gp_p for
16974 if (mips_cfun_has_cprestore_slot_p ())
16976 if (regno == CPRESTORE_SLOT_REGNUM)
16981 if (cfun->machine->global_pointer == regno)
16989 /* Implement EPILOGUE_USES. */
16992 mips_epilogue_uses (unsigned int regno)
16994 /* Say that the epilogue uses the return address register. Note that
16995 in the case of sibcalls, the values "used by the epilogue" are
16996 considered live at the start of the called function. */
16997 if (regno == RETURN_ADDR_REGNUM)
17000 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
17001 See the comment above load_call<mode> for details. */
17002 if (TARGET_USE_GOT && (regno) == GOT_VERSION_REGNUM)
17005 /* An interrupt handler must preserve some registers that are
17006 ordinarily call-clobbered. */
17007 if (cfun->machine->interrupt_handler_p
17008 && mips_interrupt_extra_call_saved_reg_p (regno))
17014 /* A for_each_rtx callback. Stop the search if *X is an AT register. */
17017 mips_at_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
17019 return REG_P (*x) && REGNO (*x) == AT_REGNUM;
17022 /* Return true if INSN needs to be wrapped in ".set noat".
17023 INSN has NOPERANDS operands, stored in OPVEC. */
17026 mips_need_noat_wrapper_p (rtx insn, rtx *opvec, int noperands)
17030 if (recog_memoized (insn) >= 0)
17031 for (i = 0; i < noperands; i++)
17032 if (for_each_rtx (&opvec[i], mips_at_reg_p, NULL))
17037 /* Implement FINAL_PRESCAN_INSN. */
17040 mips_final_prescan_insn (rtx insn, rtx *opvec, int noperands)
17042 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
17043 mips_push_asm_switch (&mips_noat);
17046 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */
17049 mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED, rtx insn,
17050 rtx *opvec, int noperands)
17052 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
17053 mips_pop_asm_switch (&mips_noat);
17056 /* Return the function that is used to expand the <u>mulsidi3 pattern.
17057 EXT_CODE is the code of the extension used. Return NULL if widening
17058 multiplication shouldn't be used. */
17061 mips_mulsidi3_gen_fn (enum rtx_code ext_code)
17065 signed_p = ext_code == SIGN_EXTEND;
17068 /* Don't use widening multiplication with MULT when we have DMUL. Even
17069 with the extension of its input operands DMUL is faster. Note that
17070 the extension is not needed for signed multiplication. In order to
17071 ensure that we always remove the redundant sign-extension in this
17072 case we still expand mulsidi3 for DMUL. */
17074 return signed_p ? gen_mulsidi3_64bit_dmul : NULL;
17077 ? gen_mulsidi3_64bit_mips16
17078 : gen_umulsidi3_64bit_mips16);
17079 if (TARGET_FIX_R4000)
17081 return signed_p ? gen_mulsidi3_64bit : gen_umulsidi3_64bit;
17087 ? gen_mulsidi3_32bit_mips16
17088 : gen_umulsidi3_32bit_mips16);
17089 if (TARGET_FIX_R4000 && !ISA_HAS_DSP)
17090 return signed_p ? gen_mulsidi3_32bit_r4000 : gen_umulsidi3_32bit_r4000;
17091 return signed_p ? gen_mulsidi3_32bit : gen_umulsidi3_32bit;
17095 /* Return the size in bytes of the trampoline code, padded to
17096 TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target
17097 function address immediately follow. */
17100 mips_trampoline_code_size (void)
17102 if (TARGET_USE_PIC_FN_ADDR_REG)
17104 else if (ptr_mode == DImode)
17106 else if (ISA_HAS_LOAD_DELAY)
17112 /* Implement TARGET_TRAMPOLINE_INIT. */
17115 mips_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
17117 rtx addr, end_addr, high, low, opcode, mem;
17120 HOST_WIDE_INT end_addr_offset, static_chain_offset, target_function_offset;
17122 /* Work out the offsets of the pointers from the start of the
17123 trampoline code. */
17124 end_addr_offset = mips_trampoline_code_size ();
17125 static_chain_offset = end_addr_offset;
17126 target_function_offset = static_chain_offset + GET_MODE_SIZE (ptr_mode);
17128 /* Get pointers to the beginning and end of the code block. */
17129 addr = force_reg (Pmode, XEXP (m_tramp, 0));
17130 end_addr = mips_force_binary (Pmode, PLUS, addr, GEN_INT (end_addr_offset));
17132 #define OP(X) gen_int_mode (X, SImode)
17134 /* Build up the code in TRAMPOLINE. */
17136 if (TARGET_USE_PIC_FN_ADDR_REG)
17138 /* $25 contains the address of the trampoline. Emit code of the form:
17140 l[wd] $1, target_function_offset($25)
17141 l[wd] $static_chain, static_chain_offset($25)
17144 trampoline[i++] = OP (MIPS_LOAD_PTR (AT_REGNUM,
17145 target_function_offset,
17146 PIC_FUNCTION_ADDR_REGNUM));
17147 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
17148 static_chain_offset,
17149 PIC_FUNCTION_ADDR_REGNUM));
17150 trampoline[i++] = OP (MIPS_JR (AT_REGNUM));
17151 trampoline[i++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM, AT_REGNUM));
17153 else if (ptr_mode == DImode)
17155 /* It's too cumbersome to create the full 64-bit address, so let's
17161 1: l[wd] $25, target_function_offset - 12($31)
17162 l[wd] $static_chain, static_chain_offset - 12($31)
17166 where 12 is the offset of "1:" from the start of the code block. */
17167 trampoline[i++] = OP (MIPS_MOVE (AT_REGNUM, RETURN_ADDR_REGNUM));
17168 trampoline[i++] = OP (MIPS_BAL (1));
17169 trampoline[i++] = OP (MIPS_NOP);
17170 trampoline[i++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
17171 target_function_offset - 12,
17172 RETURN_ADDR_REGNUM));
17173 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
17174 static_chain_offset - 12,
17175 RETURN_ADDR_REGNUM));
17176 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
17177 trampoline[i++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM, AT_REGNUM));
17181 /* If the target has load delays, emit:
17183 lui $1, %hi(end_addr)
17184 lw $25, %lo(end_addr + ...)($1)
17185 lw $static_chain, %lo(end_addr + ...)($1)
17191 lui $1, %hi(end_addr)
17192 lw $25, %lo(end_addr + ...)($1)
17194 lw $static_chain, %lo(end_addr + ...)($1). */
17196 /* Split END_ADDR into %hi and %lo values. Trampolines are aligned
17197 to 64 bits, so the %lo value will have the bottom 3 bits clear. */
17198 high = expand_simple_binop (SImode, PLUS, end_addr, GEN_INT (0x8000),
17199 NULL, false, OPTAB_WIDEN);
17200 high = expand_simple_binop (SImode, LSHIFTRT, high, GEN_INT (16),
17201 NULL, false, OPTAB_WIDEN);
17202 low = convert_to_mode (SImode, gen_lowpart (HImode, end_addr), true);
17204 /* Emit the LUI. */
17205 opcode = OP (MIPS_LUI (AT_REGNUM, 0));
17206 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, high,
17207 NULL, false, OPTAB_WIDEN);
17209 /* Emit the load of the target function. */
17210 opcode = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
17211 target_function_offset - end_addr_offset,
17213 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
17214 NULL, false, OPTAB_WIDEN);
17216 /* Emit the JR here, if we can. */
17217 if (!ISA_HAS_LOAD_DELAY)
17218 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
17220 /* Emit the load of the static chain register. */
17221 opcode = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
17222 static_chain_offset - end_addr_offset,
17224 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
17225 NULL, false, OPTAB_WIDEN);
17227 /* Emit the JR, if we couldn't above. */
17228 if (ISA_HAS_LOAD_DELAY)
17230 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
17231 trampoline[i++] = OP (MIPS_NOP);
17237 /* Copy the trampoline code. Leave any padding uninitialized. */
17238 for (j = 0; j < i; j++)
17240 mem = adjust_address (m_tramp, SImode, j * GET_MODE_SIZE (SImode));
17241 mips_emit_move (mem, trampoline[j]);
17244 /* Set up the static chain pointer field. */
17245 mem = adjust_address (m_tramp, ptr_mode, static_chain_offset);
17246 mips_emit_move (mem, chain_value);
17248 /* Set up the target function field. */
17249 mem = adjust_address (m_tramp, ptr_mode, target_function_offset);
17250 mips_emit_move (mem, XEXP (DECL_RTL (fndecl), 0));
17252 /* Flush the code part of the trampoline. */
17253 emit_insn (gen_add3_insn (end_addr, addr, GEN_INT (TRAMPOLINE_SIZE)));
17254 emit_insn (gen_clear_cache (addr, end_addr));
17257 /* Implement FUNCTION_PROFILER. */
17259 void mips_function_profiler (FILE *file)
17262 sorry ("mips16 function profiling");
17263 if (TARGET_LONG_CALLS)
17265 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */
17266 if (Pmode == DImode)
17267 fprintf (file, "\tdla\t%s,_mcount\n", reg_names[3]);
17269 fprintf (file, "\tla\t%s,_mcount\n", reg_names[3]);
17271 mips_push_asm_switch (&mips_noat);
17272 fprintf (file, "\tmove\t%s,%s\t\t# save current return address\n",
17273 reg_names[AT_REGNUM], reg_names[RETURN_ADDR_REGNUM]);
17274 /* _mcount treats $2 as the static chain register. */
17275 if (cfun->static_chain_decl != NULL)
17276 fprintf (file, "\tmove\t%s,%s\n", reg_names[2],
17277 reg_names[STATIC_CHAIN_REGNUM]);
17278 if (TARGET_MCOUNT_RA_ADDRESS)
17280 /* If TARGET_MCOUNT_RA_ADDRESS load $12 with the address of the
17281 ra save location. */
17282 if (cfun->machine->frame.ra_fp_offset == 0)
17283 /* ra not saved, pass zero. */
17284 fprintf (file, "\tmove\t%s,%s\n", reg_names[12], reg_names[0]);
17286 fprintf (file, "\t%s\t%s," HOST_WIDE_INT_PRINT_DEC "(%s)\n",
17287 Pmode == DImode ? "dla" : "la", reg_names[12],
17288 cfun->machine->frame.ra_fp_offset,
17289 reg_names[STACK_POINTER_REGNUM]);
17291 if (!TARGET_NEWABI)
17293 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n",
17294 TARGET_64BIT ? "dsubu" : "subu",
17295 reg_names[STACK_POINTER_REGNUM],
17296 reg_names[STACK_POINTER_REGNUM],
17297 Pmode == DImode ? 16 : 8);
17299 if (TARGET_LONG_CALLS)
17300 fprintf (file, "\tjalr\t%s\n", reg_names[3]);
17302 fprintf (file, "\tjal\t_mcount\n");
17303 mips_pop_asm_switch (&mips_noat);
17304 /* _mcount treats $2 as the static chain register. */
17305 if (cfun->static_chain_decl != NULL)
17306 fprintf (file, "\tmove\t%s,%s\n", reg_names[STATIC_CHAIN_REGNUM],
17310 /* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default
17311 behaviour of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even
17312 when TARGET_LOONGSON_VECTORS is true. */
17314 static unsigned HOST_WIDE_INT
17315 mips_shift_truncation_mask (enum machine_mode mode)
17317 if (TARGET_LOONGSON_VECTORS && VECTOR_MODE_P (mode))
17320 return GET_MODE_BITSIZE (mode) - 1;
17323 /* Implement TARGET_PREPARE_PCH_SAVE. */
17326 mips_prepare_pch_save (void)
17328 /* We are called in a context where the current MIPS16 vs. non-MIPS16
17329 setting should be irrelevant. The question then is: which setting
17330 makes most sense at load time?
17332 The PCH is loaded before the first token is read. We should never
17333 have switched into MIPS16 mode by that point, and thus should not
17334 have populated mips16_globals. Nor can we load the entire contents
17335 of mips16_globals from the PCH file, because mips16_globals contains
17336 a combination of GGC and non-GGC data.
17338 There is therefore no point in trying save the GGC part of
17339 mips16_globals to the PCH file, or to preserve MIPS16ness across
17340 the PCH save and load. The loading compiler would not have access
17341 to the non-GGC parts of mips16_globals (either from the PCH file,
17342 or from a copy that the loading compiler generated itself) and would
17343 have to call target_reinit anyway.
17345 It therefore seems best to switch back to non-MIPS16 mode at
17346 save time, and to ensure that mips16_globals remains null after
17348 mips_set_mips16_mode (false);
17349 mips16_globals = 0;
17352 /* Generate or test for an insn that supports a constant permutation. */
17354 #define MAX_VECT_LEN 8
17356 struct expand_vec_perm_d
17358 rtx target, op0, op1;
17359 unsigned char perm[MAX_VECT_LEN];
17360 enum machine_mode vmode;
17361 unsigned char nelt;
17366 /* Construct (set target (vec_select op0 (parallel perm))) and
17367 return true if that's a valid instruction in the active ISA. */
17370 mips_expand_vselect (rtx target, rtx op0,
17371 const unsigned char *perm, unsigned nelt)
17373 rtx rperm[MAX_VECT_LEN], x;
17376 for (i = 0; i < nelt; ++i)
17377 rperm[i] = GEN_INT (perm[i]);
17379 x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (nelt, rperm));
17380 x = gen_rtx_VEC_SELECT (GET_MODE (target), op0, x);
17381 x = gen_rtx_SET (VOIDmode, target, x);
17384 if (recog_memoized (x) < 0)
17392 /* Similar, but generate a vec_concat from op0 and op1 as well. */
17395 mips_expand_vselect_vconcat (rtx target, rtx op0, rtx op1,
17396 const unsigned char *perm, unsigned nelt)
17398 enum machine_mode v2mode;
17401 v2mode = GET_MODE_2XWIDER_MODE (GET_MODE (op0));
17402 x = gen_rtx_VEC_CONCAT (v2mode, op0, op1);
17403 return mips_expand_vselect (target, x, perm, nelt);
17406 /* Recognize patterns for even-odd extraction. */
17409 mips_expand_vpc_loongson_even_odd (struct expand_vec_perm_d *d)
17411 unsigned i, odd, nelt = d->nelt;
17412 rtx t0, t1, t2, t3;
17414 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
17416 /* Even-odd for V2SI/V2SFmode is matched by interleave directly. */
17423 for (i = 1; i < nelt; ++i)
17424 if (d->perm[i] != i * 2 + odd)
17430 /* We need 2*log2(N)-1 operations to achieve odd/even with interleave. */
17431 t0 = gen_reg_rtx (d->vmode);
17432 t1 = gen_reg_rtx (d->vmode);
17436 emit_insn (gen_loongson_punpckhhw (t0, d->op0, d->op1));
17437 emit_insn (gen_loongson_punpcklhw (t1, d->op0, d->op1));
17439 emit_insn (gen_loongson_punpckhhw (d->target, t1, t0));
17441 emit_insn (gen_loongson_punpcklhw (d->target, t1, t0));
17445 t2 = gen_reg_rtx (d->vmode);
17446 t3 = gen_reg_rtx (d->vmode);
17447 emit_insn (gen_loongson_punpckhbh (t0, d->op0, d->op1));
17448 emit_insn (gen_loongson_punpcklbh (t1, d->op0, d->op1));
17449 emit_insn (gen_loongson_punpckhbh (t2, t1, t0));
17450 emit_insn (gen_loongson_punpcklbh (t3, t1, t0));
17452 emit_insn (gen_loongson_punpckhbh (d->target, t3, t2));
17454 emit_insn (gen_loongson_punpcklbh (d->target, t3, t2));
17458 gcc_unreachable ();
17463 /* Recognize patterns for the Loongson PSHUFH instruction. */
17466 mips_expand_vpc_loongson_pshufh (struct expand_vec_perm_d *d)
17471 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
17473 if (d->vmode != V4HImode)
17478 /* Convert the selector into the packed 8-bit form for pshufh. */
17479 /* Recall that loongson is little-endian only. No big-endian
17480 adjustment required. */
17481 for (i = mask = 0; i < 4; i++)
17482 mask |= (d->perm[i] & 3) << (i * 2);
17483 rmask = force_reg (SImode, GEN_INT (mask));
17485 if (d->one_vector_p)
17486 emit_insn (gen_loongson_pshufh (d->target, d->op0, rmask));
17489 rtx t0, t1, x, merge, rmerge[4];
17491 t0 = gen_reg_rtx (V4HImode);
17492 t1 = gen_reg_rtx (V4HImode);
17493 emit_insn (gen_loongson_pshufh (t1, d->op1, rmask));
17494 emit_insn (gen_loongson_pshufh (t0, d->op0, rmask));
17496 for (i = 0; i < 4; ++i)
17497 rmerge[i] = (d->perm[i] & 4 ? constm1_rtx : const0_rtx);
17498 merge = gen_rtx_CONST_VECTOR (V4HImode, gen_rtvec_v (4, rmerge));
17499 merge = force_reg (V4HImode, merge);
17501 x = gen_rtx_AND (V4HImode, merge, t1);
17502 emit_insn (gen_rtx_SET (VOIDmode, t1, x));
17504 x = gen_rtx_NOT (V4HImode, merge);
17505 x = gen_rtx_AND (V4HImode, x, t0);
17506 emit_insn (gen_rtx_SET (VOIDmode, t0, x));
17508 x = gen_rtx_IOR (V4HImode, t0, t1);
17509 emit_insn (gen_rtx_SET (VOIDmode, d->target, x));
17515 /* Recognize broadcast patterns for the Loongson. */
17518 mips_expand_vpc_loongson_bcast (struct expand_vec_perm_d *d)
17523 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
17525 /* Note that we've already matched V2SI via punpck and V4HI via pshufh. */
17526 if (d->vmode != V8QImode)
17528 if (!d->one_vector_p)
17532 for (i = 1; i < 8; ++i)
17533 if (d->perm[i] != elt)
17539 /* With one interleave we put two of the desired element adjacent. */
17540 t0 = gen_reg_rtx (V8QImode);
17542 emit_insn (gen_loongson_punpcklbh (t0, d->op0, d->op0));
17544 emit_insn (gen_loongson_punpckhbh (t0, d->op0, d->op0));
17546 /* Shuffle that one HImode element into all locations. */
17549 t1 = gen_reg_rtx (V4HImode);
17550 emit_insn (gen_loongson_pshufh (t1, gen_lowpart (V4HImode, t0),
17551 force_reg (SImode, GEN_INT (elt))));
17553 emit_move_insn (d->target, gen_lowpart (V8QImode, t1));
17558 mips_expand_vec_perm_const_1 (struct expand_vec_perm_d *d)
17560 unsigned int i, nelt = d->nelt;
17561 unsigned char perm2[MAX_VECT_LEN];
17563 if (d->one_vector_p)
17565 /* Try interleave with alternating operands. */
17566 memcpy (perm2, d->perm, sizeof(perm2));
17567 for (i = 1; i < nelt; i += 2)
17569 if (mips_expand_vselect_vconcat (d->target, d->op0, d->op1, perm2, nelt))
17574 if (mips_expand_vselect_vconcat (d->target, d->op0, d->op1,
17578 /* Try again with swapped operands. */
17579 for (i = 0; i < nelt; ++i)
17580 perm2[i] = (d->perm[i] + nelt) & (2 * nelt - 1);
17581 if (mips_expand_vselect_vconcat (d->target, d->op1, d->op0, perm2, nelt))
17585 if (mips_expand_vpc_loongson_even_odd (d))
17587 if (mips_expand_vpc_loongson_pshufh (d))
17589 if (mips_expand_vpc_loongson_bcast (d))
17594 /* Expand a vec_perm_const pattern. */
17597 mips_expand_vec_perm_const (rtx operands[4])
17599 struct expand_vec_perm_d d;
17600 int i, nelt, which;
17601 unsigned char orig_perm[MAX_VECT_LEN];
17605 d.target = operands[0];
17606 d.op0 = operands[1];
17607 d.op1 = operands[2];
17610 d.vmode = GET_MODE (d.target);
17611 gcc_assert (VECTOR_MODE_P (d.vmode));
17612 d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
17613 d.testing_p = false;
17615 for (i = which = 0; i < nelt; ++i)
17617 rtx e = XVECEXP (sel, 0, i);
17618 int ei = INTVAL (e) & (2 * nelt - 1);
17619 which |= (ei < nelt ? 1 : 2);
17622 memcpy (d.perm, orig_perm, MAX_VECT_LEN);
17630 d.one_vector_p = false;
17631 if (!rtx_equal_p (d.op0, d.op1))
17636 for (i = 0; i < nelt; ++i)
17637 d.perm[i] &= nelt - 1;
17639 d.one_vector_p = true;
17644 d.one_vector_p = true;
17648 ok = mips_expand_vec_perm_const_1 (&d);
17650 /* If we were given a two-vector permutation which just happened to
17651 have both input vectors equal, we folded this into a one-vector
17652 permutation. There are several loongson patterns that are matched
17653 via direct vec_select+vec_concat expansion, but we do not have
17654 support in mips_expand_vec_perm_const_1 to guess the adjustment
17655 that should be made for a single operand. Just try again with
17656 the original permutation. */
17657 if (!ok && which == 3)
17659 d.op0 = operands[1];
17660 d.op1 = operands[2];
17661 d.one_vector_p = false;
17662 memcpy (d.perm, orig_perm, MAX_VECT_LEN);
17663 ok = mips_expand_vec_perm_const_1 (&d);
17669 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST_OK. */
17672 mips_vectorize_vec_perm_const_ok (enum machine_mode vmode,
17673 const unsigned char *sel)
17675 struct expand_vec_perm_d d;
17676 unsigned int i, nelt, which;
17680 d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
17681 d.testing_p = true;
17682 memcpy (d.perm, sel, nelt);
17684 /* Categorize the set of elements in the selector. */
17685 for (i = which = 0; i < nelt; ++i)
17687 unsigned char e = d.perm[i];
17688 gcc_assert (e < 2 * nelt);
17689 which |= (e < nelt ? 1 : 2);
17692 /* For all elements from second vector, fold the elements to first. */
17694 for (i = 0; i < nelt; ++i)
17697 /* Check whether the mask can be applied to the vector type. */
17698 d.one_vector_p = (which != 3);
17700 d.target = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 1);
17701 d.op1 = d.op0 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 2);
17702 if (!d.one_vector_p)
17703 d.op1 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 3);
17706 ret = mips_expand_vec_perm_const_1 (&d);
17712 /* Expand an integral vector unpack operation. */
17715 mips_expand_vec_unpack (rtx operands[2], bool unsigned_p, bool high_p)
17717 enum machine_mode imode = GET_MODE (operands[1]);
17718 rtx (*unpack) (rtx, rtx, rtx);
17719 rtx (*cmpgt) (rtx, rtx, rtx);
17720 rtx tmp, dest, zero;
17726 unpack = gen_loongson_punpckhbh;
17728 unpack = gen_loongson_punpcklbh;
17729 cmpgt = gen_loongson_pcmpgtb;
17733 unpack = gen_loongson_punpckhhw;
17735 unpack = gen_loongson_punpcklhw;
17736 cmpgt = gen_loongson_pcmpgth;
17739 gcc_unreachable ();
17742 zero = force_reg (imode, CONST0_RTX (imode));
17747 tmp = gen_reg_rtx (imode);
17748 emit_insn (cmpgt (tmp, zero, operands[1]));
17751 dest = gen_reg_rtx (imode);
17752 emit_insn (unpack (dest, operands[1], tmp));
17754 emit_move_insn (operands[0], gen_lowpart (GET_MODE (operands[0]), dest));
17757 /* A subroutine of mips_expand_vec_init, match constant vector elements. */
17760 mips_constant_elt_p (rtx x)
17762 return CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE;
17765 /* A subroutine of mips_expand_vec_init, expand via broadcast. */
17768 mips_expand_vi_broadcast (enum machine_mode vmode, rtx target, rtx elt)
17770 struct expand_vec_perm_d d;
17774 if (elt != const0_rtx)
17775 elt = force_reg (GET_MODE_INNER (vmode), elt);
17777 elt = gen_lowpart (DImode, elt);
17779 t1 = gen_reg_rtx (vmode);
17783 emit_insn (gen_loongson_vec_init1_v8qi (t1, elt));
17786 emit_insn (gen_loongson_vec_init1_v4hi (t1, elt));
17789 gcc_unreachable ();
17792 memset (&d, 0, sizeof (d));
17797 d.nelt = GET_MODE_NUNITS (vmode);
17798 d.one_vector_p = true;
17800 ok = mips_expand_vec_perm_const_1 (&d);
17804 /* A subroutine of mips_expand_vec_init, replacing all of the non-constant
17805 elements of VALS with zeros, copy the constant vector to TARGET. */
17808 mips_expand_vi_constant (enum machine_mode vmode, unsigned nelt,
17809 rtx target, rtx vals)
17811 rtvec vec = shallow_copy_rtvec (XVEC (vals, 0));
17814 for (i = 0; i < nelt; ++i)
17816 if (!mips_constant_elt_p (RTVEC_ELT (vec, i)))
17817 RTVEC_ELT (vec, i) = const0_rtx;
17820 emit_move_insn (target, gen_rtx_CONST_VECTOR (vmode, vec));
17824 /* A subroutine of mips_expand_vec_init, expand via pinsrh. */
17827 mips_expand_vi_loongson_one_pinsrh (rtx target, rtx vals, unsigned one_var)
17829 mips_expand_vi_constant (V4HImode, 4, target, vals);
17831 emit_insn (gen_vec_setv4hi (target, target, XVECEXP (vals, 0, one_var),
17832 GEN_INT (one_var)));
17835 /* A subroutine of mips_expand_vec_init, expand anything via memory. */
17838 mips_expand_vi_general (enum machine_mode vmode, enum machine_mode imode,
17839 unsigned nelt, unsigned nvar, rtx target, rtx vals)
17841 rtx mem = assign_stack_temp (vmode, GET_MODE_SIZE (vmode));
17842 unsigned int i, isize = GET_MODE_SIZE (imode);
17845 mips_expand_vi_constant (vmode, nelt, mem, vals);
17847 for (i = 0; i < nelt; ++i)
17849 rtx x = XVECEXP (vals, 0, i);
17850 if (!mips_constant_elt_p (x))
17851 emit_move_insn (adjust_address (mem, imode, i * isize), x);
17854 emit_move_insn (target, mem);
17857 /* Expand a vector initialization. */
17860 mips_expand_vector_init (rtx target, rtx vals)
17862 enum machine_mode vmode = GET_MODE (target);
17863 enum machine_mode imode = GET_MODE_INNER (vmode);
17864 unsigned i, nelt = GET_MODE_NUNITS (vmode);
17865 unsigned nvar = 0, one_var = -1u;
17866 bool all_same = true;
17869 for (i = 0; i < nelt; ++i)
17871 x = XVECEXP (vals, 0, i);
17872 if (!mips_constant_elt_p (x))
17873 nvar++, one_var = i;
17874 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
17878 /* Load constants from the pool, or whatever's handy. */
17881 emit_move_insn (target, gen_rtx_CONST_VECTOR (vmode, XVEC (vals, 0)));
17885 /* For two-part initialization, always use CONCAT. */
17888 rtx op0 = force_reg (imode, XVECEXP (vals, 0, 0));
17889 rtx op1 = force_reg (imode, XVECEXP (vals, 0, 1));
17890 x = gen_rtx_VEC_CONCAT (vmode, op0, op1);
17891 emit_insn (gen_rtx_SET (VOIDmode, target, x));
17895 /* Loongson is the only cpu with vectors with more elements. */
17896 gcc_assert (TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS);
17898 /* If all values are identical, broadcast the value. */
17901 mips_expand_vi_broadcast (vmode, target, XVECEXP (vals, 0, 0));
17905 /* If we've only got one non-variable V4HImode, use PINSRH. */
17906 if (nvar == 1 && vmode == V4HImode)
17908 mips_expand_vi_loongson_one_pinsrh (target, vals, one_var);
17912 mips_expand_vi_general (vmode, imode, nelt, nvar, target, vals);
17915 /* Expand a vector reduction. */
17918 mips_expand_vec_reduc (rtx target, rtx in, rtx (*gen)(rtx, rtx, rtx))
17920 enum machine_mode vmode = GET_MODE (in);
17921 unsigned char perm2[2];
17922 rtx last, next, fold, x;
17926 fold = gen_reg_rtx (vmode);
17930 /* Use PUL/PLU to produce { L, H } op { H, L }.
17931 By reversing the pair order, rather than a pure interleave high,
17932 we avoid erroneous exceptional conditions that we might otherwise
17933 produce from the computation of H op H. */
17936 ok = mips_expand_vselect_vconcat (fold, last, last, perm2, 2);
17941 /* Use interleave to produce { H, L } op { H, H }. */
17942 emit_insn (gen_loongson_punpckhwd (fold, last, last));
17946 /* Perform the first reduction with interleave,
17947 and subsequent reductions with shifts. */
17948 emit_insn (gen_loongson_punpckhwd_hi (fold, last, last));
17950 next = gen_reg_rtx (vmode);
17951 emit_insn (gen (next, last, fold));
17954 fold = gen_reg_rtx (vmode);
17955 x = force_reg (SImode, GEN_INT (16));
17956 emit_insn (gen_vec_shr_v4hi (fold, last, x));
17960 emit_insn (gen_loongson_punpckhwd_qi (fold, last, last));
17962 next = gen_reg_rtx (vmode);
17963 emit_insn (gen (next, last, fold));
17966 fold = gen_reg_rtx (vmode);
17967 x = force_reg (SImode, GEN_INT (16));
17968 emit_insn (gen_vec_shr_v8qi (fold, last, x));
17970 next = gen_reg_rtx (vmode);
17971 emit_insn (gen (next, last, fold));
17974 fold = gen_reg_rtx (vmode);
17975 x = force_reg (SImode, GEN_INT (8));
17976 emit_insn (gen_vec_shr_v8qi (fold, last, x));
17980 gcc_unreachable ();
17983 emit_insn (gen (target, last, fold));
17986 /* Expand a vector minimum/maximum. */
17989 mips_expand_vec_minmax (rtx target, rtx op0, rtx op1,
17990 rtx (*cmp) (rtx, rtx, rtx), bool min_p)
17992 enum machine_mode vmode = GET_MODE (target);
17995 tc = gen_reg_rtx (vmode);
17996 t0 = gen_reg_rtx (vmode);
17997 t1 = gen_reg_rtx (vmode);
18000 emit_insn (cmp (tc, op0, op1));
18002 x = gen_rtx_AND (vmode, tc, (min_p ? op1 : op0));
18003 emit_insn (gen_rtx_SET (VOIDmode, t0, x));
18005 x = gen_rtx_NOT (vmode, tc);
18006 x = gen_rtx_AND (vmode, x, (min_p ? op0 : op1));
18007 emit_insn (gen_rtx_SET (VOIDmode, t1, x));
18009 x = gen_rtx_IOR (vmode, t0, t1);
18010 emit_insn (gen_rtx_SET (VOIDmode, target, x));
18013 /* Initialize the GCC target structure. */
18014 #undef TARGET_ASM_ALIGNED_HI_OP
18015 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
18016 #undef TARGET_ASM_ALIGNED_SI_OP
18017 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
18018 #undef TARGET_ASM_ALIGNED_DI_OP
18019 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
18021 #undef TARGET_OPTION_OVERRIDE
18022 #define TARGET_OPTION_OVERRIDE mips_option_override
18024 #undef TARGET_LEGITIMIZE_ADDRESS
18025 #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
18027 #undef TARGET_ASM_FUNCTION_PROLOGUE
18028 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
18029 #undef TARGET_ASM_FUNCTION_EPILOGUE
18030 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
18031 #undef TARGET_ASM_SELECT_RTX_SECTION
18032 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
18033 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
18034 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
18036 #undef TARGET_SCHED_INIT
18037 #define TARGET_SCHED_INIT mips_sched_init
18038 #undef TARGET_SCHED_REORDER
18039 #define TARGET_SCHED_REORDER mips_sched_reorder
18040 #undef TARGET_SCHED_REORDER2
18041 #define TARGET_SCHED_REORDER2 mips_sched_reorder2
18042 #undef TARGET_SCHED_VARIABLE_ISSUE
18043 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
18044 #undef TARGET_SCHED_ADJUST_COST
18045 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
18046 #undef TARGET_SCHED_ISSUE_RATE
18047 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
18048 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
18049 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
18050 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
18051 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
18052 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
18053 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
18054 mips_multipass_dfa_lookahead
18055 #undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
18056 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
18057 mips_small_register_classes_for_mode_p
18059 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
18060 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
18062 #undef TARGET_INSERT_ATTRIBUTES
18063 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
18064 #undef TARGET_MERGE_DECL_ATTRIBUTES
18065 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
18066 #undef TARGET_SET_CURRENT_FUNCTION
18067 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
18069 #undef TARGET_VALID_POINTER_MODE
18070 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
18071 #undef TARGET_REGISTER_MOVE_COST
18072 #define TARGET_REGISTER_MOVE_COST mips_register_move_cost
18073 #undef TARGET_MEMORY_MOVE_COST
18074 #define TARGET_MEMORY_MOVE_COST mips_memory_move_cost
18075 #undef TARGET_RTX_COSTS
18076 #define TARGET_RTX_COSTS mips_rtx_costs
18077 #undef TARGET_ADDRESS_COST
18078 #define TARGET_ADDRESS_COST mips_address_cost
18080 #undef TARGET_IN_SMALL_DATA_P
18081 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
18083 #undef TARGET_MACHINE_DEPENDENT_REORG
18084 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
18086 #undef TARGET_PREFERRED_RELOAD_CLASS
18087 #define TARGET_PREFERRED_RELOAD_CLASS mips_preferred_reload_class
18089 #undef TARGET_EXPAND_TO_RTL_HOOK
18090 #define TARGET_EXPAND_TO_RTL_HOOK mips_expand_to_rtl_hook
18091 #undef TARGET_ASM_FILE_START
18092 #define TARGET_ASM_FILE_START mips_file_start
18093 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
18094 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
18095 #undef TARGET_ASM_CODE_END
18096 #define TARGET_ASM_CODE_END mips_code_end
18098 #undef TARGET_INIT_LIBFUNCS
18099 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
18101 #undef TARGET_BUILD_BUILTIN_VA_LIST
18102 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
18103 #undef TARGET_EXPAND_BUILTIN_VA_START
18104 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
18105 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
18106 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
18108 #undef TARGET_PROMOTE_FUNCTION_MODE
18109 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
18110 #undef TARGET_PROMOTE_PROTOTYPES
18111 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
18113 #undef TARGET_FUNCTION_VALUE
18114 #define TARGET_FUNCTION_VALUE mips_function_value
18115 #undef TARGET_LIBCALL_VALUE
18116 #define TARGET_LIBCALL_VALUE mips_libcall_value
18117 #undef TARGET_FUNCTION_VALUE_REGNO_P
18118 #define TARGET_FUNCTION_VALUE_REGNO_P mips_function_value_regno_p
18119 #undef TARGET_RETURN_IN_MEMORY
18120 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
18121 #undef TARGET_RETURN_IN_MSB
18122 #define TARGET_RETURN_IN_MSB mips_return_in_msb
18124 #undef TARGET_ASM_OUTPUT_MI_THUNK
18125 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
18126 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
18127 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
18129 #undef TARGET_PRINT_OPERAND
18130 #define TARGET_PRINT_OPERAND mips_print_operand
18131 #undef TARGET_PRINT_OPERAND_ADDRESS
18132 #define TARGET_PRINT_OPERAND_ADDRESS mips_print_operand_address
18133 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
18134 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mips_print_operand_punct_valid_p
18136 #undef TARGET_SETUP_INCOMING_VARARGS
18137 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
18138 #undef TARGET_STRICT_ARGUMENT_NAMING
18139 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
18140 #undef TARGET_MUST_PASS_IN_STACK
18141 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
18142 #undef TARGET_PASS_BY_REFERENCE
18143 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
18144 #undef TARGET_CALLEE_COPIES
18145 #define TARGET_CALLEE_COPIES mips_callee_copies
18146 #undef TARGET_ARG_PARTIAL_BYTES
18147 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
18148 #undef TARGET_FUNCTION_ARG
18149 #define TARGET_FUNCTION_ARG mips_function_arg
18150 #undef TARGET_FUNCTION_ARG_ADVANCE
18151 #define TARGET_FUNCTION_ARG_ADVANCE mips_function_arg_advance
18152 #undef TARGET_FUNCTION_ARG_BOUNDARY
18153 #define TARGET_FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
18155 #undef TARGET_MODE_REP_EXTENDED
18156 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
18158 #undef TARGET_VECTOR_MODE_SUPPORTED_P
18159 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
18161 #undef TARGET_SCALAR_MODE_SUPPORTED_P
18162 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
18164 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
18165 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE mips_preferred_simd_mode
18167 #undef TARGET_INIT_BUILTINS
18168 #define TARGET_INIT_BUILTINS mips_init_builtins
18169 #undef TARGET_BUILTIN_DECL
18170 #define TARGET_BUILTIN_DECL mips_builtin_decl
18171 #undef TARGET_EXPAND_BUILTIN
18172 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
18174 #undef TARGET_HAVE_TLS
18175 #define TARGET_HAVE_TLS HAVE_AS_TLS
18177 #undef TARGET_CANNOT_FORCE_CONST_MEM
18178 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
18180 #undef TARGET_LEGITIMATE_CONSTANT_P
18181 #define TARGET_LEGITIMATE_CONSTANT_P mips_legitimate_constant_p
18183 #undef TARGET_ENCODE_SECTION_INFO
18184 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
18186 #undef TARGET_ATTRIBUTE_TABLE
18187 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
18188 /* All our function attributes are related to how out-of-line copies should
18189 be compiled or called. They don't in themselves prevent inlining. */
18190 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
18191 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
18193 #undef TARGET_EXTRA_LIVE_ON_ENTRY
18194 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
18196 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
18197 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
18198 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
18199 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
18201 #undef TARGET_COMP_TYPE_ATTRIBUTES
18202 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
18204 #ifdef HAVE_AS_DTPRELWORD
18205 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
18206 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
18208 #undef TARGET_DWARF_REGISTER_SPAN
18209 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
18211 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
18212 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
18214 #undef TARGET_LEGITIMATE_ADDRESS_P
18215 #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p
18217 #undef TARGET_FRAME_POINTER_REQUIRED
18218 #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required
18220 #undef TARGET_CAN_ELIMINATE
18221 #define TARGET_CAN_ELIMINATE mips_can_eliminate
18223 #undef TARGET_CONDITIONAL_REGISTER_USAGE
18224 #define TARGET_CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage
18226 #undef TARGET_TRAMPOLINE_INIT
18227 #define TARGET_TRAMPOLINE_INIT mips_trampoline_init
18229 #undef TARGET_ASM_OUTPUT_SOURCE_FILENAME
18230 #define TARGET_ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
18232 #undef TARGET_SHIFT_TRUNCATION_MASK
18233 #define TARGET_SHIFT_TRUNCATION_MASK mips_shift_truncation_mask
18235 #undef TARGET_PREPARE_PCH_SAVE
18236 #define TARGET_PREPARE_PCH_SAVE mips_prepare_pch_save
18238 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
18239 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK mips_vectorize_vec_perm_const_ok
18241 struct gcc_target targetm = TARGET_INITIALIZER;
18243 #include "gt-mips.h"