1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
5 Free Software Foundation, Inc.
6 Contributed by A. Lichnewsky, lich@inria.inria.fr.
7 Changes by Michael Meissner, meissner@osf.org.
8 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
9 Brendan Eich, brendan@microunity.com.
11 This file is part of GCC.
13 GCC is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GCC is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GCC; see the file COPYING3. If not see
25 <http://www.gnu.org/licenses/>. */
29 #include "coretypes.h"
33 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
36 #include "insn-attr.h"
52 #include "target-def.h"
53 #include "integrate.h"
54 #include "langhooks.h"
55 #include "cfglayout.h"
56 #include "sched-int.h"
59 #include "diagnostic.h"
60 #include "target-globals.h"
63 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
64 #define UNSPEC_ADDRESS_P(X) \
65 (GET_CODE (X) == UNSPEC \
66 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
67 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
69 /* Extract the symbol or label from UNSPEC wrapper X. */
70 #define UNSPEC_ADDRESS(X) \
73 /* Extract the symbol type from UNSPEC wrapper X. */
74 #define UNSPEC_ADDRESS_TYPE(X) \
75 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
77 /* The maximum distance between the top of the stack frame and the
78 value $sp has when we save and restore registers.
80 The value for normal-mode code must be a SMALL_OPERAND and must
81 preserve the maximum stack alignment. We therefore use a value
82 of 0x7ff0 in this case.
84 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
85 up to 0x7f8 bytes and can usually save or restore all the registers
86 that we need to save or restore. (Note that we can only use these
87 instructions for o32, for which the stack alignment is 8 bytes.)
89 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
90 RESTORE are not available. We can then use unextended instructions
91 to save and restore registers, and to allocate and deallocate the top
93 #define MIPS_MAX_FIRST_STACK_STEP \
94 (!TARGET_MIPS16 ? 0x7ff0 \
95 : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
96 : TARGET_64BIT ? 0x100 : 0x400)
98 /* True if INSN is a mips.md pattern or asm statement. */
99 #define USEFUL_INSN_P(INSN) \
100 (NONDEBUG_INSN_P (INSN) \
101 && GET_CODE (PATTERN (INSN)) != USE \
102 && GET_CODE (PATTERN (INSN)) != CLOBBER \
103 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
104 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
106 /* If INSN is a delayed branch sequence, return the first instruction
107 in the sequence, otherwise return INSN itself. */
108 #define SEQ_BEGIN(INSN) \
109 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
110 ? XVECEXP (PATTERN (INSN), 0, 0) \
113 /* Likewise for the last instruction in a delayed branch sequence. */
114 #define SEQ_END(INSN) \
115 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
116 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
119 /* Execute the following loop body with SUBINSN set to each instruction
120 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
121 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
122 for ((SUBINSN) = SEQ_BEGIN (INSN); \
123 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
124 (SUBINSN) = NEXT_INSN (SUBINSN))
126 /* True if bit BIT is set in VALUE. */
127 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
129 /* Return the opcode for a ptr_mode load of the form:
131 l[wd] DEST, OFFSET(BASE). */
132 #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \
133 (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \
138 /* Return the opcode to move register SRC into register DEST. */
139 #define MIPS_MOVE(DEST, SRC) \
140 ((TARGET_64BIT ? 0x2d : 0x21) \
144 /* Return the opcode for:
147 #define MIPS_LUI(DEST, VALUE) \
148 ((0xf << 26) | ((DEST) << 16) | (VALUE))
150 /* Return the opcode to jump to register DEST. */
151 #define MIPS_JR(DEST) \
152 (((DEST) << 21) | 0x8)
154 /* Return the opcode for:
156 bal . + (1 + OFFSET) * 4. */
157 #define MIPS_BAL(OFFSET) \
158 ((0x1 << 26) | (0x11 << 16) | (OFFSET))
160 /* Return the usual opcode for a nop. */
163 /* Classifies an address.
166 A natural register + offset address. The register satisfies
167 mips_valid_base_register_p and the offset is a const_arith_operand.
170 A LO_SUM rtx. The first operand is a valid base register and
171 the second operand is a symbolic address.
174 A signed 16-bit constant address.
177 A constant symbolic address. */
178 enum mips_address_type {
185 /* Enumerates the setting of the -mr10k-cache-barrier option. */
186 enum mips_r10k_cache_barrier_setting {
187 R10K_CACHE_BARRIER_NONE,
188 R10K_CACHE_BARRIER_STORE,
189 R10K_CACHE_BARRIER_LOAD_STORE
192 /* Macros to create an enumeration identifier for a function prototype. */
193 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
194 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
195 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
196 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
198 /* Classifies the prototype of a built-in function. */
199 enum mips_function_type {
200 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
201 #include "config/mips/mips-ftypes.def"
202 #undef DEF_MIPS_FTYPE
206 /* Specifies how a built-in function should be converted into rtl. */
207 enum mips_builtin_type {
208 /* The function corresponds directly to an .md pattern. The return
209 value is mapped to operand 0 and the arguments are mapped to
210 operands 1 and above. */
213 /* The function corresponds directly to an .md pattern. There is no return
214 value and the arguments are mapped to operands 0 and above. */
215 MIPS_BUILTIN_DIRECT_NO_TARGET,
217 /* The function corresponds to a comparison instruction followed by
218 a mips_cond_move_tf_ps pattern. The first two arguments are the
219 values to compare and the second two arguments are the vector
220 operands for the movt.ps or movf.ps instruction (in assembly order). */
224 /* The function corresponds to a V2SF comparison instruction. Operand 0
225 of this instruction is the result of the comparison, which has mode
226 CCV2 or CCV4. The function arguments are mapped to operands 1 and
227 above. The function's return value is an SImode boolean that is
228 true under the following conditions:
230 MIPS_BUILTIN_CMP_ANY: one of the registers is true
231 MIPS_BUILTIN_CMP_ALL: all of the registers are true
232 MIPS_BUILTIN_CMP_LOWER: the first register is true
233 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
234 MIPS_BUILTIN_CMP_ANY,
235 MIPS_BUILTIN_CMP_ALL,
236 MIPS_BUILTIN_CMP_UPPER,
237 MIPS_BUILTIN_CMP_LOWER,
239 /* As above, but the instruction only sets a single $fcc register. */
240 MIPS_BUILTIN_CMP_SINGLE,
242 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
243 MIPS_BUILTIN_BPOSGE32
246 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
247 #define MIPS_FP_CONDITIONS(MACRO) \
265 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
266 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
267 enum mips_fp_condition {
268 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
271 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
272 #define STRINGIFY(X) #X
273 static const char *const mips_fp_conditions[] = {
274 MIPS_FP_CONDITIONS (STRINGIFY)
277 /* Information about a function's frame layout. */
278 struct GTY(()) mips_frame_info {
279 /* The size of the frame in bytes. */
280 HOST_WIDE_INT total_size;
282 /* The number of bytes allocated to variables. */
283 HOST_WIDE_INT var_size;
285 /* The number of bytes allocated to outgoing function arguments. */
286 HOST_WIDE_INT args_size;
288 /* The number of bytes allocated to the .cprestore slot, or 0 if there
290 HOST_WIDE_INT cprestore_size;
292 /* Bit X is set if the function saves or restores GPR X. */
295 /* Likewise FPR X. */
298 /* Likewise doubleword accumulator X ($acX). */
299 unsigned int acc_mask;
301 /* The number of GPRs, FPRs, doubleword accumulators and COP0
305 unsigned int num_acc;
306 unsigned int num_cop0_regs;
308 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
309 save slots from the top of the frame, or zero if no such slots are
311 HOST_WIDE_INT gp_save_offset;
312 HOST_WIDE_INT fp_save_offset;
313 HOST_WIDE_INT acc_save_offset;
314 HOST_WIDE_INT cop0_save_offset;
316 /* Likewise, but giving offsets from the bottom of the frame. */
317 HOST_WIDE_INT gp_sp_offset;
318 HOST_WIDE_INT fp_sp_offset;
319 HOST_WIDE_INT acc_sp_offset;
320 HOST_WIDE_INT cop0_sp_offset;
322 /* Similar, but the value passed to _mcount. */
323 HOST_WIDE_INT ra_fp_offset;
325 /* The offset of arg_pointer_rtx from the bottom of the frame. */
326 HOST_WIDE_INT arg_pointer_offset;
328 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
329 HOST_WIDE_INT hard_frame_pointer_offset;
332 struct GTY(()) machine_function {
333 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
334 rtx mips16_gp_pseudo_rtx;
336 /* The number of extra stack bytes taken up by register varargs.
337 This area is allocated by the callee at the very top of the frame. */
340 /* The current frame information, calculated by mips_compute_frame_info. */
341 struct mips_frame_info frame;
343 /* The register to use as the function's global pointer, or INVALID_REGNUM
344 if the function doesn't need one. */
345 unsigned int global_pointer;
347 /* How many instructions it takes to load a label into $AT, or 0 if
348 this property hasn't yet been calculated. */
349 unsigned int load_label_num_insns;
351 /* True if mips_adjust_insn_length should ignore an instruction's
353 bool ignore_hazard_length_p;
355 /* True if the whole function is suitable for .set noreorder and
357 bool all_noreorder_p;
359 /* True if the function has "inflexible" and "flexible" references
360 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
361 and mips_cfun_has_flexible_gp_ref_p for details. */
362 bool has_inflexible_gp_insn_p;
363 bool has_flexible_gp_insn_p;
365 /* True if the function's prologue must load the global pointer
366 value into pic_offset_table_rtx and store the same value in
367 the function's cprestore slot (if any). Even if this value
368 is currently false, we may decide to set it to true later;
369 see mips_must_initialize_gp_p () for details. */
370 bool must_initialize_gp_p;
372 /* True if the current function must restore $gp after any potential
373 clobber. This value is only meaningful during the first post-epilogue
374 split_insns pass; see mips_must_initialize_gp_p () for details. */
375 bool must_restore_gp_when_clobbered_p;
377 /* True if this is an interrupt handler. */
378 bool interrupt_handler_p;
380 /* True if this is an interrupt handler that uses shadow registers. */
381 bool use_shadow_register_set_p;
383 /* True if this is an interrupt handler that should keep interrupts
385 bool keep_interrupts_masked_p;
387 /* True if this is an interrupt handler that should use DERET
389 bool use_debug_exception_return_p;
392 /* Information about a single argument. */
393 struct mips_arg_info {
394 /* True if the argument is passed in a floating-point register, or
395 would have been if we hadn't run out of registers. */
398 /* The number of words passed in registers, rounded up. */
399 unsigned int reg_words;
401 /* For EABI, the offset of the first register from GP_ARG_FIRST or
402 FP_ARG_FIRST. For other ABIs, the offset of the first register from
403 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
404 comment for details).
406 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
408 unsigned int reg_offset;
410 /* The number of words that must be passed on the stack, rounded up. */
411 unsigned int stack_words;
413 /* The offset from the start of the stack overflow area of the argument's
414 first stack word. Only meaningful when STACK_WORDS is nonzero. */
415 unsigned int stack_offset;
418 /* Information about an address described by mips_address_type.
424 REG is the base register and OFFSET is the constant offset.
427 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
428 is the type of symbol it references.
431 SYMBOL_TYPE is the type of symbol that the address references. */
432 struct mips_address_info {
433 enum mips_address_type type;
436 enum mips_symbol_type symbol_type;
439 /* One stage in a constant building sequence. These sequences have
443 A = A CODE[1] VALUE[1]
444 A = A CODE[2] VALUE[2]
447 where A is an accumulator, each CODE[i] is a binary rtl operation
448 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
449 struct mips_integer_op {
451 unsigned HOST_WIDE_INT value;
454 /* The largest number of operations needed to load an integer constant.
455 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
456 When the lowest bit is clear, we can try, but reject a sequence with
457 an extra SLL at the end. */
458 #define MIPS_MAX_INTEGER_OPS 7
460 /* Information about a MIPS16e SAVE or RESTORE instruction. */
461 struct mips16e_save_restore_info {
462 /* The number of argument registers saved by a SAVE instruction.
463 0 for RESTORE instructions. */
466 /* Bit X is set if the instruction saves or restores GPR X. */
469 /* The total number of bytes to allocate. */
473 /* Costs of various operations on the different architectures. */
475 struct mips_rtx_cost_data
477 unsigned short fp_add;
478 unsigned short fp_mult_sf;
479 unsigned short fp_mult_df;
480 unsigned short fp_div_sf;
481 unsigned short fp_div_df;
482 unsigned short int_mult_si;
483 unsigned short int_mult_di;
484 unsigned short int_div_si;
485 unsigned short int_div_di;
486 unsigned short branch_cost;
487 unsigned short memory_latency;
490 /* Global variables for machine-dependent things. */
492 /* The -G setting, or the configuration's default small-data limit if
493 no -G option is given. */
494 static unsigned int mips_small_data_threshold;
496 /* The number of file directives written by mips_output_filename. */
497 int num_source_filenames;
499 /* The name that appeared in the last .file directive written by
500 mips_output_filename, or "" if mips_output_filename hasn't
501 written anything yet. */
502 const char *current_function_file = "";
504 /* A label counter used by PUT_SDB_BLOCK_START and PUT_SDB_BLOCK_END. */
507 /* Arrays that map GCC register numbers to debugger register numbers. */
508 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
509 int mips_dwarf_regno[FIRST_PSEUDO_REGISTER];
511 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
512 struct mips_asm_switch mips_noreorder = { "reorder", 0 };
513 struct mips_asm_switch mips_nomacro = { "macro", 0 };
514 struct mips_asm_switch mips_noat = { "at", 0 };
516 /* True if we're writing out a branch-likely instruction rather than a
518 static bool mips_branch_likely;
520 /* The current instruction-set architecture. */
521 enum processor mips_arch;
522 const struct mips_cpu_info *mips_arch_info;
524 /* The processor that we should tune the code for. */
525 enum processor mips_tune;
526 const struct mips_cpu_info *mips_tune_info;
528 /* The ISA level associated with mips_arch. */
531 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
532 static const struct mips_cpu_info *mips_isa_option_info;
534 /* Which ABI to use. */
535 int mips_abi = MIPS_ABI_DEFAULT;
537 /* Which cost information to use. */
538 static const struct mips_rtx_cost_data *mips_cost;
540 /* The ambient target flags, excluding MASK_MIPS16. */
541 static int mips_base_target_flags;
543 /* True if MIPS16 is the default mode. */
544 bool mips_base_mips16;
546 /* The ambient values of other global variables. */
547 static int mips_base_schedule_insns; /* flag_schedule_insns */
548 static int mips_base_reorder_blocks_and_partition; /* flag_reorder... */
549 static int mips_base_move_loop_invariants; /* flag_move_loop_invariants */
550 static int mips_base_align_loops; /* align_loops */
551 static int mips_base_align_jumps; /* align_jumps */
552 static int mips_base_align_functions; /* align_functions */
554 /* The -mcode-readable setting. */
555 enum mips_code_readable_setting mips_code_readable = CODE_READABLE_YES;
557 /* The -mr10k-cache-barrier setting. */
558 static enum mips_r10k_cache_barrier_setting mips_r10k_cache_barrier;
560 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
561 bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
563 /* Index C is true if character C is a valid PRINT_OPERAND punctation
565 static bool mips_print_operand_punct[256];
567 static GTY (()) int mips_output_filename_first_time = 1;
569 /* mips_split_p[X] is true if symbols of type X can be split by
570 mips_split_symbol. */
571 bool mips_split_p[NUM_SYMBOL_TYPES];
573 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
574 can be split by mips_split_symbol. */
575 bool mips_split_hi_p[NUM_SYMBOL_TYPES];
577 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
578 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
579 if they are matched by a special .md file pattern. */
580 static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
582 /* Likewise for HIGHs. */
583 static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
585 /* Target state for MIPS16. */
586 struct target_globals *mips16_globals;
588 /* Cached value of can_issue_more. This is cached in mips_variable_issue hook
589 and returned from mips_sched_reorder2. */
590 static int cached_can_issue_more;
592 /* Index R is the smallest register class that contains register R. */
593 const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = {
594 LEA_REGS, LEA_REGS, M16_REGS, V1_REG,
595 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
596 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
597 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
598 M16_REGS, M16_REGS, LEA_REGS, LEA_REGS,
599 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
600 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
601 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
602 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
603 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
604 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
605 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
606 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
607 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
608 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
609 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
610 MD0_REG, MD1_REG, NO_REGS, ST_REGS,
611 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
612 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
613 NO_REGS, FRAME_REGS, FRAME_REGS, NO_REGS,
614 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
615 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
616 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
617 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
618 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
619 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
620 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
621 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
622 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
623 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
624 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
625 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
626 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
627 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
628 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
629 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
630 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
631 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
632 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
633 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
634 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
635 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
636 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
637 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
638 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
639 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
640 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
643 /* The value of TARGET_ATTRIBUTE_TABLE. */
644 static const struct attribute_spec mips_attribute_table[] = {
645 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
647 { "long_call", 0, 0, false, true, true, NULL, false },
648 { "far", 0, 0, false, true, true, NULL, false },
649 { "near", 0, 0, false, true, true, NULL, false },
650 /* We would really like to treat "mips16" and "nomips16" as type
651 attributes, but GCC doesn't provide the hooks we need to support
652 the right conversion rules. As declaration attributes, they affect
653 code generation but don't carry other semantics. */
654 { "mips16", 0, 0, true, false, false, NULL, false },
655 { "nomips16", 0, 0, true, false, false, NULL, false },
656 /* Allow functions to be specified as interrupt handlers */
657 { "interrupt", 0, 0, false, true, true, NULL, false },
658 { "use_shadow_register_set", 0, 0, false, true, true, NULL, false },
659 { "keep_interrupts_masked", 0, 0, false, true, true, NULL, false },
660 { "use_debug_exception_return", 0, 0, false, true, true, NULL, false },
661 { NULL, 0, 0, false, false, false, NULL, false }
664 /* A table describing all the processors GCC knows about. Names are
665 matched in the order listed. The first mention of an ISA level is
666 taken as the canonical name for that ISA.
668 To ease comparison, please keep this table in the same order
669 as GAS's mips_cpu_info_table. Please also make sure that
670 MIPS_ISA_LEVEL_SPEC and MIPS_ARCH_FLOAT_SPEC handle all -march
671 options correctly. */
672 static const struct mips_cpu_info mips_cpu_info_table[] = {
673 /* Entries for generic ISAs. */
674 { "mips1", PROCESSOR_R3000, 1, 0 },
675 { "mips2", PROCESSOR_R6000, 2, 0 },
676 { "mips3", PROCESSOR_R4000, 3, 0 },
677 { "mips4", PROCESSOR_R8000, 4, 0 },
678 /* Prefer not to use branch-likely instructions for generic MIPS32rX
679 and MIPS64rX code. The instructions were officially deprecated
680 in revisions 2 and earlier, but revision 3 is likely to downgrade
681 that to a recommendation to avoid the instructions in code that
682 isn't tuned to a specific processor. */
683 { "mips32", PROCESSOR_4KC, 32, PTF_AVOID_BRANCHLIKELY },
684 { "mips32r2", PROCESSOR_M4K, 33, PTF_AVOID_BRANCHLIKELY },
685 { "mips64", PROCESSOR_5KC, 64, PTF_AVOID_BRANCHLIKELY },
686 /* ??? For now just tune the generic MIPS64r2 for 5KC as well. */
687 { "mips64r2", PROCESSOR_5KC, 65, PTF_AVOID_BRANCHLIKELY },
689 /* MIPS I processors. */
690 { "r3000", PROCESSOR_R3000, 1, 0 },
691 { "r2000", PROCESSOR_R3000, 1, 0 },
692 { "r3900", PROCESSOR_R3900, 1, 0 },
694 /* MIPS II processors. */
695 { "r6000", PROCESSOR_R6000, 2, 0 },
697 /* MIPS III processors. */
698 { "r4000", PROCESSOR_R4000, 3, 0 },
699 { "vr4100", PROCESSOR_R4100, 3, 0 },
700 { "vr4111", PROCESSOR_R4111, 3, 0 },
701 { "vr4120", PROCESSOR_R4120, 3, 0 },
702 { "vr4130", PROCESSOR_R4130, 3, 0 },
703 { "vr4300", PROCESSOR_R4300, 3, 0 },
704 { "r4400", PROCESSOR_R4000, 3, 0 },
705 { "r4600", PROCESSOR_R4600, 3, 0 },
706 { "orion", PROCESSOR_R4600, 3, 0 },
707 { "r4650", PROCESSOR_R4650, 3, 0 },
708 /* ST Loongson 2E/2F processors. */
709 { "loongson2e", PROCESSOR_LOONGSON_2E, 3, PTF_AVOID_BRANCHLIKELY },
710 { "loongson2f", PROCESSOR_LOONGSON_2F, 3, PTF_AVOID_BRANCHLIKELY },
712 /* MIPS IV processors. */
713 { "r8000", PROCESSOR_R8000, 4, 0 },
714 { "r10000", PROCESSOR_R10000, 4, 0 },
715 { "r12000", PROCESSOR_R10000, 4, 0 },
716 { "r14000", PROCESSOR_R10000, 4, 0 },
717 { "r16000", PROCESSOR_R10000, 4, 0 },
718 { "vr5000", PROCESSOR_R5000, 4, 0 },
719 { "vr5400", PROCESSOR_R5400, 4, 0 },
720 { "vr5500", PROCESSOR_R5500, 4, PTF_AVOID_BRANCHLIKELY },
721 { "rm7000", PROCESSOR_R7000, 4, 0 },
722 { "rm9000", PROCESSOR_R9000, 4, 0 },
724 /* MIPS32 processors. */
725 { "4kc", PROCESSOR_4KC, 32, 0 },
726 { "4km", PROCESSOR_4KC, 32, 0 },
727 { "4kp", PROCESSOR_4KP, 32, 0 },
728 { "4ksc", PROCESSOR_4KC, 32, 0 },
730 /* MIPS32 Release 2 processors. */
731 { "m4k", PROCESSOR_M4K, 33, 0 },
732 { "4kec", PROCESSOR_4KC, 33, 0 },
733 { "4kem", PROCESSOR_4KC, 33, 0 },
734 { "4kep", PROCESSOR_4KP, 33, 0 },
735 { "4ksd", PROCESSOR_4KC, 33, 0 },
737 { "24kc", PROCESSOR_24KC, 33, 0 },
738 { "24kf2_1", PROCESSOR_24KF2_1, 33, 0 },
739 { "24kf", PROCESSOR_24KF2_1, 33, 0 },
740 { "24kf1_1", PROCESSOR_24KF1_1, 33, 0 },
741 { "24kfx", PROCESSOR_24KF1_1, 33, 0 },
742 { "24kx", PROCESSOR_24KF1_1, 33, 0 },
744 { "24kec", PROCESSOR_24KC, 33, 0 }, /* 24K with DSP. */
745 { "24kef2_1", PROCESSOR_24KF2_1, 33, 0 },
746 { "24kef", PROCESSOR_24KF2_1, 33, 0 },
747 { "24kef1_1", PROCESSOR_24KF1_1, 33, 0 },
748 { "24kefx", PROCESSOR_24KF1_1, 33, 0 },
749 { "24kex", PROCESSOR_24KF1_1, 33, 0 },
751 { "34kc", PROCESSOR_24KC, 33, 0 }, /* 34K with MT/DSP. */
752 { "34kf2_1", PROCESSOR_24KF2_1, 33, 0 },
753 { "34kf", PROCESSOR_24KF2_1, 33, 0 },
754 { "34kf1_1", PROCESSOR_24KF1_1, 33, 0 },
755 { "34kfx", PROCESSOR_24KF1_1, 33, 0 },
756 { "34kx", PROCESSOR_24KF1_1, 33, 0 },
758 { "74kc", PROCESSOR_74KC, 33, 0 }, /* 74K with DSPr2. */
759 { "74kf2_1", PROCESSOR_74KF2_1, 33, 0 },
760 { "74kf", PROCESSOR_74KF2_1, 33, 0 },
761 { "74kf1_1", PROCESSOR_74KF1_1, 33, 0 },
762 { "74kfx", PROCESSOR_74KF1_1, 33, 0 },
763 { "74kx", PROCESSOR_74KF1_1, 33, 0 },
764 { "74kf3_2", PROCESSOR_74KF3_2, 33, 0 },
766 { "1004kc", PROCESSOR_24KC, 33, 0 }, /* 1004K with MT/DSP. */
767 { "1004kf2_1", PROCESSOR_24KF2_1, 33, 0 },
768 { "1004kf", PROCESSOR_24KF2_1, 33, 0 },
769 { "1004kf1_1", PROCESSOR_24KF1_1, 33, 0 },
771 /* MIPS64 processors. */
772 { "5kc", PROCESSOR_5KC, 64, 0 },
773 { "5kf", PROCESSOR_5KF, 64, 0 },
774 { "20kc", PROCESSOR_20KC, 64, PTF_AVOID_BRANCHLIKELY },
775 { "sb1", PROCESSOR_SB1, 64, PTF_AVOID_BRANCHLIKELY },
776 { "sb1a", PROCESSOR_SB1A, 64, PTF_AVOID_BRANCHLIKELY },
777 { "sr71000", PROCESSOR_SR71000, 64, PTF_AVOID_BRANCHLIKELY },
778 { "xlr", PROCESSOR_XLR, 64, 0 },
779 { "loongson3a", PROCESSOR_LOONGSON_3A, 64, PTF_AVOID_BRANCHLIKELY },
781 /* MIPS64 Release 2 processors. */
782 { "octeon", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY }
785 /* Default costs. If these are used for a processor we should look
786 up the actual costs. */
787 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
788 COSTS_N_INSNS (7), /* fp_mult_sf */ \
789 COSTS_N_INSNS (8), /* fp_mult_df */ \
790 COSTS_N_INSNS (23), /* fp_div_sf */ \
791 COSTS_N_INSNS (36), /* fp_div_df */ \
792 COSTS_N_INSNS (10), /* int_mult_si */ \
793 COSTS_N_INSNS (10), /* int_mult_di */ \
794 COSTS_N_INSNS (69), /* int_div_si */ \
795 COSTS_N_INSNS (69), /* int_div_di */ \
796 2, /* branch_cost */ \
797 4 /* memory_latency */
799 /* Floating-point costs for processors without an FPU. Just assume that
800 all floating-point libcalls are very expensive. */
801 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
802 COSTS_N_INSNS (256), /* fp_mult_sf */ \
803 COSTS_N_INSNS (256), /* fp_mult_df */ \
804 COSTS_N_INSNS (256), /* fp_div_sf */ \
805 COSTS_N_INSNS (256) /* fp_div_df */
807 /* Costs to use when optimizing for size. */
808 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size = {
809 COSTS_N_INSNS (1), /* fp_add */
810 COSTS_N_INSNS (1), /* fp_mult_sf */
811 COSTS_N_INSNS (1), /* fp_mult_df */
812 COSTS_N_INSNS (1), /* fp_div_sf */
813 COSTS_N_INSNS (1), /* fp_div_df */
814 COSTS_N_INSNS (1), /* int_mult_si */
815 COSTS_N_INSNS (1), /* int_mult_di */
816 COSTS_N_INSNS (1), /* int_div_si */
817 COSTS_N_INSNS (1), /* int_div_di */
819 4 /* memory_latency */
822 /* Costs to use when optimizing for speed, indexed by processor. */
823 static const struct mips_rtx_cost_data
824 mips_rtx_cost_data[NUM_PROCESSOR_VALUES] = {
826 COSTS_N_INSNS (2), /* fp_add */
827 COSTS_N_INSNS (4), /* fp_mult_sf */
828 COSTS_N_INSNS (5), /* fp_mult_df */
829 COSTS_N_INSNS (12), /* fp_div_sf */
830 COSTS_N_INSNS (19), /* fp_div_df */
831 COSTS_N_INSNS (12), /* int_mult_si */
832 COSTS_N_INSNS (12), /* int_mult_di */
833 COSTS_N_INSNS (35), /* int_div_si */
834 COSTS_N_INSNS (35), /* int_div_di */
836 4 /* memory_latency */
840 COSTS_N_INSNS (6), /* int_mult_si */
841 COSTS_N_INSNS (6), /* int_mult_di */
842 COSTS_N_INSNS (36), /* int_div_si */
843 COSTS_N_INSNS (36), /* int_div_di */
845 4 /* memory_latency */
849 COSTS_N_INSNS (36), /* int_mult_si */
850 COSTS_N_INSNS (36), /* int_mult_di */
851 COSTS_N_INSNS (37), /* int_div_si */
852 COSTS_N_INSNS (37), /* int_div_di */
854 4 /* memory_latency */
858 COSTS_N_INSNS (4), /* int_mult_si */
859 COSTS_N_INSNS (11), /* int_mult_di */
860 COSTS_N_INSNS (36), /* int_div_si */
861 COSTS_N_INSNS (68), /* int_div_di */
863 4 /* memory_latency */
866 COSTS_N_INSNS (4), /* fp_add */
867 COSTS_N_INSNS (4), /* fp_mult_sf */
868 COSTS_N_INSNS (5), /* fp_mult_df */
869 COSTS_N_INSNS (17), /* fp_div_sf */
870 COSTS_N_INSNS (32), /* fp_div_df */
871 COSTS_N_INSNS (4), /* int_mult_si */
872 COSTS_N_INSNS (11), /* int_mult_di */
873 COSTS_N_INSNS (36), /* int_div_si */
874 COSTS_N_INSNS (68), /* int_div_di */
876 4 /* memory_latency */
879 COSTS_N_INSNS (4), /* fp_add */
880 COSTS_N_INSNS (4), /* fp_mult_sf */
881 COSTS_N_INSNS (5), /* fp_mult_df */
882 COSTS_N_INSNS (17), /* fp_div_sf */
883 COSTS_N_INSNS (32), /* fp_div_df */
884 COSTS_N_INSNS (4), /* int_mult_si */
885 COSTS_N_INSNS (7), /* int_mult_di */
886 COSTS_N_INSNS (42), /* int_div_si */
887 COSTS_N_INSNS (72), /* int_div_di */
889 4 /* memory_latency */
893 COSTS_N_INSNS (5), /* int_mult_si */
894 COSTS_N_INSNS (5), /* int_mult_di */
895 COSTS_N_INSNS (41), /* int_div_si */
896 COSTS_N_INSNS (41), /* int_div_di */
898 4 /* memory_latency */
901 COSTS_N_INSNS (8), /* fp_add */
902 COSTS_N_INSNS (8), /* fp_mult_sf */
903 COSTS_N_INSNS (10), /* fp_mult_df */
904 COSTS_N_INSNS (34), /* fp_div_sf */
905 COSTS_N_INSNS (64), /* fp_div_df */
906 COSTS_N_INSNS (5), /* int_mult_si */
907 COSTS_N_INSNS (5), /* int_mult_di */
908 COSTS_N_INSNS (41), /* int_div_si */
909 COSTS_N_INSNS (41), /* int_div_di */
911 4 /* memory_latency */
914 COSTS_N_INSNS (4), /* fp_add */
915 COSTS_N_INSNS (4), /* fp_mult_sf */
916 COSTS_N_INSNS (5), /* fp_mult_df */
917 COSTS_N_INSNS (17), /* fp_div_sf */
918 COSTS_N_INSNS (32), /* fp_div_df */
919 COSTS_N_INSNS (5), /* int_mult_si */
920 COSTS_N_INSNS (5), /* int_mult_di */
921 COSTS_N_INSNS (41), /* int_div_si */
922 COSTS_N_INSNS (41), /* int_div_di */
924 4 /* memory_latency */
928 COSTS_N_INSNS (5), /* int_mult_si */
929 COSTS_N_INSNS (5), /* int_mult_di */
930 COSTS_N_INSNS (41), /* int_div_si */
931 COSTS_N_INSNS (41), /* int_div_di */
933 4 /* memory_latency */
936 COSTS_N_INSNS (8), /* fp_add */
937 COSTS_N_INSNS (8), /* fp_mult_sf */
938 COSTS_N_INSNS (10), /* fp_mult_df */
939 COSTS_N_INSNS (34), /* fp_div_sf */
940 COSTS_N_INSNS (64), /* fp_div_df */
941 COSTS_N_INSNS (5), /* int_mult_si */
942 COSTS_N_INSNS (5), /* int_mult_di */
943 COSTS_N_INSNS (41), /* int_div_si */
944 COSTS_N_INSNS (41), /* int_div_di */
946 4 /* memory_latency */
949 COSTS_N_INSNS (4), /* fp_add */
950 COSTS_N_INSNS (4), /* fp_mult_sf */
951 COSTS_N_INSNS (5), /* fp_mult_df */
952 COSTS_N_INSNS (17), /* fp_div_sf */
953 COSTS_N_INSNS (32), /* fp_div_df */
954 COSTS_N_INSNS (5), /* int_mult_si */
955 COSTS_N_INSNS (5), /* int_mult_di */
956 COSTS_N_INSNS (41), /* int_div_si */
957 COSTS_N_INSNS (41), /* int_div_di */
959 4 /* memory_latency */
962 COSTS_N_INSNS (6), /* fp_add */
963 COSTS_N_INSNS (6), /* fp_mult_sf */
964 COSTS_N_INSNS (7), /* fp_mult_df */
965 COSTS_N_INSNS (25), /* fp_div_sf */
966 COSTS_N_INSNS (48), /* fp_div_df */
967 COSTS_N_INSNS (5), /* int_mult_si */
968 COSTS_N_INSNS (5), /* int_mult_di */
969 COSTS_N_INSNS (41), /* int_div_si */
970 COSTS_N_INSNS (41), /* int_div_di */
972 4 /* memory_latency */
989 COSTS_N_INSNS (5), /* int_mult_si */
990 COSTS_N_INSNS (5), /* int_mult_di */
991 COSTS_N_INSNS (72), /* int_div_si */
992 COSTS_N_INSNS (72), /* int_div_di */
994 4 /* memory_latency */
997 COSTS_N_INSNS (2), /* fp_add */
998 COSTS_N_INSNS (4), /* fp_mult_sf */
999 COSTS_N_INSNS (5), /* fp_mult_df */
1000 COSTS_N_INSNS (12), /* fp_div_sf */
1001 COSTS_N_INSNS (19), /* fp_div_df */
1002 COSTS_N_INSNS (2), /* int_mult_si */
1003 COSTS_N_INSNS (2), /* int_mult_di */
1004 COSTS_N_INSNS (35), /* int_div_si */
1005 COSTS_N_INSNS (35), /* int_div_di */
1006 1, /* branch_cost */
1007 4 /* memory_latency */
1010 COSTS_N_INSNS (3), /* fp_add */
1011 COSTS_N_INSNS (5), /* fp_mult_sf */
1012 COSTS_N_INSNS (6), /* fp_mult_df */
1013 COSTS_N_INSNS (15), /* fp_div_sf */
1014 COSTS_N_INSNS (16), /* fp_div_df */
1015 COSTS_N_INSNS (17), /* int_mult_si */
1016 COSTS_N_INSNS (17), /* int_mult_di */
1017 COSTS_N_INSNS (38), /* int_div_si */
1018 COSTS_N_INSNS (38), /* int_div_di */
1019 2, /* branch_cost */
1020 6 /* memory_latency */
1023 COSTS_N_INSNS (6), /* fp_add */
1024 COSTS_N_INSNS (7), /* fp_mult_sf */
1025 COSTS_N_INSNS (8), /* fp_mult_df */
1026 COSTS_N_INSNS (23), /* fp_div_sf */
1027 COSTS_N_INSNS (36), /* fp_div_df */
1028 COSTS_N_INSNS (10), /* int_mult_si */
1029 COSTS_N_INSNS (10), /* int_mult_di */
1030 COSTS_N_INSNS (69), /* int_div_si */
1031 COSTS_N_INSNS (69), /* int_div_di */
1032 2, /* branch_cost */
1033 6 /* memory_latency */
1045 /* The only costs that appear to be updated here are
1046 integer multiplication. */
1048 COSTS_N_INSNS (4), /* int_mult_si */
1049 COSTS_N_INSNS (6), /* int_mult_di */
1050 COSTS_N_INSNS (69), /* int_div_si */
1051 COSTS_N_INSNS (69), /* int_div_di */
1052 1, /* branch_cost */
1053 4 /* memory_latency */
1065 COSTS_N_INSNS (6), /* fp_add */
1066 COSTS_N_INSNS (4), /* fp_mult_sf */
1067 COSTS_N_INSNS (5), /* fp_mult_df */
1068 COSTS_N_INSNS (23), /* fp_div_sf */
1069 COSTS_N_INSNS (36), /* fp_div_df */
1070 COSTS_N_INSNS (5), /* int_mult_si */
1071 COSTS_N_INSNS (5), /* int_mult_di */
1072 COSTS_N_INSNS (36), /* int_div_si */
1073 COSTS_N_INSNS (36), /* int_div_di */
1074 1, /* branch_cost */
1075 4 /* memory_latency */
1078 COSTS_N_INSNS (6), /* fp_add */
1079 COSTS_N_INSNS (5), /* fp_mult_sf */
1080 COSTS_N_INSNS (6), /* fp_mult_df */
1081 COSTS_N_INSNS (30), /* fp_div_sf */
1082 COSTS_N_INSNS (59), /* fp_div_df */
1083 COSTS_N_INSNS (3), /* int_mult_si */
1084 COSTS_N_INSNS (4), /* int_mult_di */
1085 COSTS_N_INSNS (42), /* int_div_si */
1086 COSTS_N_INSNS (74), /* int_div_di */
1087 1, /* branch_cost */
1088 4 /* memory_latency */
1091 COSTS_N_INSNS (6), /* fp_add */
1092 COSTS_N_INSNS (5), /* fp_mult_sf */
1093 COSTS_N_INSNS (6), /* fp_mult_df */
1094 COSTS_N_INSNS (30), /* fp_div_sf */
1095 COSTS_N_INSNS (59), /* fp_div_df */
1096 COSTS_N_INSNS (5), /* int_mult_si */
1097 COSTS_N_INSNS (9), /* int_mult_di */
1098 COSTS_N_INSNS (42), /* int_div_si */
1099 COSTS_N_INSNS (74), /* int_div_di */
1100 1, /* branch_cost */
1101 4 /* memory_latency */
1104 /* The only costs that are changed here are
1105 integer multiplication. */
1106 COSTS_N_INSNS (6), /* fp_add */
1107 COSTS_N_INSNS (7), /* fp_mult_sf */
1108 COSTS_N_INSNS (8), /* fp_mult_df */
1109 COSTS_N_INSNS (23), /* fp_div_sf */
1110 COSTS_N_INSNS (36), /* fp_div_df */
1111 COSTS_N_INSNS (5), /* int_mult_si */
1112 COSTS_N_INSNS (9), /* int_mult_di */
1113 COSTS_N_INSNS (69), /* int_div_si */
1114 COSTS_N_INSNS (69), /* int_div_di */
1115 1, /* branch_cost */
1116 4 /* memory_latency */
1122 /* The only costs that are changed here are
1123 integer multiplication. */
1124 COSTS_N_INSNS (6), /* fp_add */
1125 COSTS_N_INSNS (7), /* fp_mult_sf */
1126 COSTS_N_INSNS (8), /* fp_mult_df */
1127 COSTS_N_INSNS (23), /* fp_div_sf */
1128 COSTS_N_INSNS (36), /* fp_div_df */
1129 COSTS_N_INSNS (3), /* int_mult_si */
1130 COSTS_N_INSNS (8), /* int_mult_di */
1131 COSTS_N_INSNS (69), /* int_div_si */
1132 COSTS_N_INSNS (69), /* int_div_di */
1133 1, /* branch_cost */
1134 4 /* memory_latency */
1137 COSTS_N_INSNS (2), /* fp_add */
1138 COSTS_N_INSNS (2), /* fp_mult_sf */
1139 COSTS_N_INSNS (2), /* fp_mult_df */
1140 COSTS_N_INSNS (12), /* fp_div_sf */
1141 COSTS_N_INSNS (19), /* fp_div_df */
1142 COSTS_N_INSNS (5), /* int_mult_si */
1143 COSTS_N_INSNS (9), /* int_mult_di */
1144 COSTS_N_INSNS (34), /* int_div_si */
1145 COSTS_N_INSNS (66), /* int_div_di */
1146 1, /* branch_cost */
1147 4 /* memory_latency */
1150 /* These costs are the same as the SB-1A below. */
1151 COSTS_N_INSNS (4), /* fp_add */
1152 COSTS_N_INSNS (4), /* fp_mult_sf */
1153 COSTS_N_INSNS (4), /* fp_mult_df */
1154 COSTS_N_INSNS (24), /* fp_div_sf */
1155 COSTS_N_INSNS (32), /* fp_div_df */
1156 COSTS_N_INSNS (3), /* int_mult_si */
1157 COSTS_N_INSNS (4), /* int_mult_di */
1158 COSTS_N_INSNS (36), /* int_div_si */
1159 COSTS_N_INSNS (68), /* int_div_di */
1160 1, /* branch_cost */
1161 4 /* memory_latency */
1164 /* These costs are the same as the SB-1 above. */
1165 COSTS_N_INSNS (4), /* fp_add */
1166 COSTS_N_INSNS (4), /* fp_mult_sf */
1167 COSTS_N_INSNS (4), /* fp_mult_df */
1168 COSTS_N_INSNS (24), /* fp_div_sf */
1169 COSTS_N_INSNS (32), /* fp_div_df */
1170 COSTS_N_INSNS (3), /* int_mult_si */
1171 COSTS_N_INSNS (4), /* int_mult_di */
1172 COSTS_N_INSNS (36), /* int_div_si */
1173 COSTS_N_INSNS (68), /* int_div_di */
1174 1, /* branch_cost */
1175 4 /* memory_latency */
1182 COSTS_N_INSNS (8), /* int_mult_si */
1183 COSTS_N_INSNS (8), /* int_mult_di */
1184 COSTS_N_INSNS (72), /* int_div_si */
1185 COSTS_N_INSNS (72), /* int_div_di */
1186 1, /* branch_cost */
1187 4 /* memory_latency */
1191 static rtx mips_find_pic_call_symbol (rtx, rtx);
1192 static int mips_register_move_cost (enum machine_mode, reg_class_t,
1194 static unsigned int mips_function_arg_boundary (enum machine_mode, const_tree);
1196 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1197 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1198 struct GTY (()) mflip_mips16_entry {
1202 static GTY ((param_is (struct mflip_mips16_entry))) htab_t mflip_mips16_htab;
1204 /* Hash table callbacks for mflip_mips16_htab. */
1207 mflip_mips16_htab_hash (const void *entry)
1209 return htab_hash_string (((const struct mflip_mips16_entry *) entry)->name);
1213 mflip_mips16_htab_eq (const void *entry, const void *name)
1215 return strcmp (((const struct mflip_mips16_entry *) entry)->name,
1216 (const char *) name) == 0;
1219 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1220 mode, false if it should next add an attribute for the opposite mode. */
1221 static GTY(()) bool mips16_flipper;
1223 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1224 for -mflip-mips16. Return true if it should use "mips16" and false if
1225 it should use "nomips16". */
1228 mflip_mips16_use_mips16_p (tree decl)
1230 struct mflip_mips16_entry *entry;
1235 /* Use the opposite of the command-line setting for anonymous decls. */
1236 if (!DECL_NAME (decl))
1237 return !mips_base_mips16;
1239 if (!mflip_mips16_htab)
1240 mflip_mips16_htab = htab_create_ggc (37, mflip_mips16_htab_hash,
1241 mflip_mips16_htab_eq, NULL);
1243 name = IDENTIFIER_POINTER (DECL_NAME (decl));
1244 hash = htab_hash_string (name);
1245 slot = htab_find_slot_with_hash (mflip_mips16_htab, name, hash, INSERT);
1246 entry = (struct mflip_mips16_entry *) *slot;
1249 mips16_flipper = !mips16_flipper;
1250 entry = ggc_alloc_mflip_mips16_entry ();
1252 entry->mips16_p = mips16_flipper ? !mips_base_mips16 : mips_base_mips16;
1255 return entry->mips16_p;
1258 /* Predicates to test for presence of "near" and "far"/"long_call"
1259 attributes on the given TYPE. */
1262 mips_near_type_p (const_tree type)
1264 return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL;
1268 mips_far_type_p (const_tree type)
1270 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL
1271 || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL);
1274 /* Similar predicates for "mips16"/"nomips16" function attributes. */
1277 mips_mips16_decl_p (const_tree decl)
1279 return lookup_attribute ("mips16", DECL_ATTRIBUTES (decl)) != NULL;
1283 mips_nomips16_decl_p (const_tree decl)
1285 return lookup_attribute ("nomips16", DECL_ATTRIBUTES (decl)) != NULL;
1288 /* Check if the interrupt attribute is set for a function. */
1291 mips_interrupt_type_p (tree type)
1293 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type)) != NULL;
1296 /* Check if the attribute to use shadow register set is set for a function. */
1299 mips_use_shadow_register_set_p (tree type)
1301 return lookup_attribute ("use_shadow_register_set",
1302 TYPE_ATTRIBUTES (type)) != NULL;
1305 /* Check if the attribute to keep interrupts masked is set for a function. */
1308 mips_keep_interrupts_masked_p (tree type)
1310 return lookup_attribute ("keep_interrupts_masked",
1311 TYPE_ATTRIBUTES (type)) != NULL;
1314 /* Check if the attribute to use debug exception return is set for
1318 mips_use_debug_exception_return_p (tree type)
1320 return lookup_attribute ("use_debug_exception_return",
1321 TYPE_ATTRIBUTES (type)) != NULL;
1324 /* Return true if function DECL is a MIPS16 function. Return the ambient
1325 setting if DECL is null. */
1328 mips_use_mips16_mode_p (tree decl)
1332 /* Nested functions must use the same frame pointer as their
1333 parent and must therefore use the same ISA mode. */
1334 tree parent = decl_function_context (decl);
1337 if (mips_mips16_decl_p (decl))
1339 if (mips_nomips16_decl_p (decl))
1342 return mips_base_mips16;
1345 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1348 mips_comp_type_attributes (const_tree type1, const_tree type2)
1350 /* Disallow mixed near/far attributes. */
1351 if (mips_far_type_p (type1) && mips_near_type_p (type2))
1353 if (mips_near_type_p (type1) && mips_far_type_p (type2))
1358 /* Implement TARGET_INSERT_ATTRIBUTES. */
1361 mips_insert_attributes (tree decl, tree *attributes)
1364 bool mips16_p, nomips16_p;
1366 /* Check for "mips16" and "nomips16" attributes. */
1367 mips16_p = lookup_attribute ("mips16", *attributes) != NULL;
1368 nomips16_p = lookup_attribute ("nomips16", *attributes) != NULL;
1369 if (TREE_CODE (decl) != FUNCTION_DECL)
1372 error ("%qs attribute only applies to functions", "mips16");
1374 error ("%qs attribute only applies to functions", "nomips16");
1378 mips16_p |= mips_mips16_decl_p (decl);
1379 nomips16_p |= mips_nomips16_decl_p (decl);
1380 if (mips16_p || nomips16_p)
1382 /* DECL cannot be simultaneously "mips16" and "nomips16". */
1383 if (mips16_p && nomips16_p)
1384 error ("%qE cannot have both %<mips16%> and "
1385 "%<nomips16%> attributes",
1388 else if (TARGET_FLIP_MIPS16 && !DECL_ARTIFICIAL (decl))
1390 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1391 "mips16" attribute, arbitrarily pick one. We must pick the same
1392 setting for duplicate declarations of a function. */
1393 name = mflip_mips16_use_mips16_p (decl) ? "mips16" : "nomips16";
1394 *attributes = tree_cons (get_identifier (name), NULL, *attributes);
1399 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1402 mips_merge_decl_attributes (tree olddecl, tree newdecl)
1404 /* The decls' "mips16" and "nomips16" attributes must match exactly. */
1405 if (mips_mips16_decl_p (olddecl) != mips_mips16_decl_p (newdecl))
1406 error ("%qE redeclared with conflicting %qs attributes",
1407 DECL_NAME (newdecl), "mips16");
1408 if (mips_nomips16_decl_p (olddecl) != mips_nomips16_decl_p (newdecl))
1409 error ("%qE redeclared with conflicting %qs attributes",
1410 DECL_NAME (newdecl), "nomips16");
1412 return merge_attributes (DECL_ATTRIBUTES (olddecl),
1413 DECL_ATTRIBUTES (newdecl));
1416 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1417 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1420 mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr)
1422 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
1424 *base_ptr = XEXP (x, 0);
1425 *offset_ptr = INTVAL (XEXP (x, 1));
1434 static unsigned int mips_build_integer (struct mips_integer_op *,
1435 unsigned HOST_WIDE_INT);
1437 /* A subroutine of mips_build_integer, with the same interface.
1438 Assume that the final action in the sequence should be a left shift. */
1441 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1443 unsigned int i, shift;
1445 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1446 since signed numbers are easier to load than unsigned ones. */
1448 while ((value & 1) == 0)
1449 value /= 2, shift++;
1451 i = mips_build_integer (codes, value);
1452 codes[i].code = ASHIFT;
1453 codes[i].value = shift;
1457 /* As for mips_build_shift, but assume that the final action will be
1458 an IOR or PLUS operation. */
1461 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1463 unsigned HOST_WIDE_INT high;
1466 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1467 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
1469 /* The constant is too complex to load with a simple LUI/ORI pair,
1470 so we want to give the recursive call as many trailing zeros as
1471 possible. In this case, we know bit 16 is set and that the
1472 low 16 bits form a negative number. If we subtract that number
1473 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1474 i = mips_build_integer (codes, CONST_HIGH_PART (value));
1475 codes[i].code = PLUS;
1476 codes[i].value = CONST_LOW_PART (value);
1480 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1481 bits gives a value with at least 17 trailing zeros. */
1482 i = mips_build_integer (codes, high);
1483 codes[i].code = IOR;
1484 codes[i].value = value & 0xffff;
1489 /* Fill CODES with a sequence of rtl operations to load VALUE.
1490 Return the number of operations needed. */
1493 mips_build_integer (struct mips_integer_op *codes,
1494 unsigned HOST_WIDE_INT value)
1496 if (SMALL_OPERAND (value)
1497 || SMALL_OPERAND_UNSIGNED (value)
1498 || LUI_OPERAND (value))
1500 /* The value can be loaded with a single instruction. */
1501 codes[0].code = UNKNOWN;
1502 codes[0].value = value;
1505 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
1507 /* Either the constant is a simple LUI/ORI combination or its
1508 lowest bit is set. We don't want to shift in this case. */
1509 return mips_build_lower (codes, value);
1511 else if ((value & 0xffff) == 0)
1513 /* The constant will need at least three actions. The lowest
1514 16 bits are clear, so the final action will be a shift. */
1515 return mips_build_shift (codes, value);
1519 /* The final action could be a shift, add or inclusive OR.
1520 Rather than use a complex condition to select the best
1521 approach, try both mips_build_shift and mips_build_lower
1522 and pick the one that gives the shortest sequence.
1523 Note that this case is only used once per constant. */
1524 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1525 unsigned int cost, alt_cost;
1527 cost = mips_build_shift (codes, value);
1528 alt_cost = mips_build_lower (alt_codes, value);
1529 if (alt_cost < cost)
1531 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
1538 /* Return true if symbols of type TYPE require a GOT access. */
1541 mips_got_symbol_type_p (enum mips_symbol_type type)
1545 case SYMBOL_GOT_PAGE_OFST:
1546 case SYMBOL_GOT_DISP:
1554 /* Return true if X is a thread-local symbol. */
1557 mips_tls_symbol_p (rtx x)
1559 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1562 /* Return true if SYMBOL_REF X is associated with a global symbol
1563 (in the STB_GLOBAL sense). */
1566 mips_global_symbol_p (const_rtx x)
1568 const_tree decl = SYMBOL_REF_DECL (x);
1571 return !SYMBOL_REF_LOCAL_P (x) || SYMBOL_REF_EXTERNAL_P (x);
1573 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1574 or weak symbols. Relocations in the object file will be against
1575 the target symbol, so it's that symbol's binding that matters here. */
1576 return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl));
1579 /* Return true if function X is a libgcc MIPS16 stub function. */
1582 mips16_stub_function_p (const_rtx x)
1584 return (GET_CODE (x) == SYMBOL_REF
1585 && strncmp (XSTR (x, 0), "__mips16_", 9) == 0);
1588 /* Return true if function X is a locally-defined and locally-binding
1592 mips16_local_function_p (const_rtx x)
1594 return (GET_CODE (x) == SYMBOL_REF
1595 && SYMBOL_REF_LOCAL_P (x)
1596 && !SYMBOL_REF_EXTERNAL_P (x)
1597 && mips_use_mips16_mode_p (SYMBOL_REF_DECL (x)));
1600 /* Return true if SYMBOL_REF X binds locally. */
1603 mips_symbol_binds_local_p (const_rtx x)
1605 return (SYMBOL_REF_DECL (x)
1606 ? targetm.binds_local_p (SYMBOL_REF_DECL (x))
1607 : SYMBOL_REF_LOCAL_P (x));
1610 /* Return true if rtx constants of mode MODE should be put into a small
1614 mips_rtx_constant_in_small_data_p (enum machine_mode mode)
1616 return (!TARGET_EMBEDDED_DATA
1617 && TARGET_LOCAL_SDATA
1618 && GET_MODE_SIZE (mode) <= mips_small_data_threshold);
1621 /* Return true if X should not be moved directly into register $25.
1622 We need this because many versions of GAS will treat "la $25,foo" as
1623 part of a call sequence and so allow a global "foo" to be lazily bound. */
1626 mips_dangerous_for_la25_p (rtx x)
1628 return (!TARGET_EXPLICIT_RELOCS
1630 && GET_CODE (x) == SYMBOL_REF
1631 && mips_global_symbol_p (x));
1634 /* Return true if calls to X might need $25 to be valid on entry. */
1637 mips_use_pic_fn_addr_reg_p (const_rtx x)
1639 if (!TARGET_USE_PIC_FN_ADDR_REG)
1642 /* MIPS16 stub functions are guaranteed not to use $25. */
1643 if (mips16_stub_function_p (x))
1646 if (GET_CODE (x) == SYMBOL_REF)
1648 /* If PLTs and copy relocations are available, the static linker
1649 will make sure that $25 is valid on entry to the target function. */
1650 if (TARGET_ABICALLS_PIC0)
1653 /* Locally-defined functions use absolute accesses to set up
1654 the global pointer. */
1655 if (TARGET_ABSOLUTE_ABICALLS
1656 && mips_symbol_binds_local_p (x)
1657 && !SYMBOL_REF_EXTERNAL_P (x))
1664 /* Return the method that should be used to access SYMBOL_REF or
1665 LABEL_REF X in context CONTEXT. */
1667 static enum mips_symbol_type
1668 mips_classify_symbol (const_rtx x, enum mips_symbol_context context)
1671 return SYMBOL_GOT_DISP;
1673 if (GET_CODE (x) == LABEL_REF)
1675 /* Only return SYMBOL_PC_RELATIVE if we are generating MIPS16
1676 code and if we know that the label is in the current function's
1677 text section. LABEL_REFs are used for jump tables as well as
1678 text labels, so we must check whether jump tables live in the
1680 if (TARGET_MIPS16_SHORT_JUMP_TABLES
1681 && !LABEL_REF_NONLOCAL_P (x))
1682 return SYMBOL_PC_RELATIVE;
1684 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1685 return SYMBOL_GOT_PAGE_OFST;
1687 return SYMBOL_ABSOLUTE;
1690 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1692 if (SYMBOL_REF_TLS_MODEL (x))
1695 if (CONSTANT_POOL_ADDRESS_P (x))
1697 if (TARGET_MIPS16_TEXT_LOADS)
1698 return SYMBOL_PC_RELATIVE;
1700 if (TARGET_MIPS16_PCREL_LOADS && context == SYMBOL_CONTEXT_MEM)
1701 return SYMBOL_PC_RELATIVE;
1703 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x)))
1704 return SYMBOL_GP_RELATIVE;
1707 /* Do not use small-data accesses for weak symbols; they may end up
1709 if (TARGET_GPOPT && SYMBOL_REF_SMALL_P (x) && !SYMBOL_REF_WEAK (x))
1710 return SYMBOL_GP_RELATIVE;
1712 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1714 if (TARGET_ABICALLS_PIC2
1715 && !(TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x)))
1717 /* There are three cases to consider:
1719 - o32 PIC (either with or without explicit relocs)
1720 - n32/n64 PIC without explicit relocs
1721 - n32/n64 PIC with explicit relocs
1723 In the first case, both local and global accesses will use an
1724 R_MIPS_GOT16 relocation. We must correctly predict which of
1725 the two semantics (local or global) the assembler and linker
1726 will apply. The choice depends on the symbol's binding rather
1727 than its visibility.
1729 In the second case, the assembler will not use R_MIPS_GOT16
1730 relocations, but it chooses between local and global accesses
1731 in the same way as for o32 PIC.
1733 In the third case we have more freedom since both forms of
1734 access will work for any kind of symbol. However, there seems
1735 little point in doing things differently. */
1736 if (mips_global_symbol_p (x))
1737 return SYMBOL_GOT_DISP;
1739 return SYMBOL_GOT_PAGE_OFST;
1742 if (TARGET_MIPS16_PCREL_LOADS && context != SYMBOL_CONTEXT_CALL)
1743 return SYMBOL_FORCE_TO_MEM;
1745 return SYMBOL_ABSOLUTE;
1748 /* Classify the base of symbolic expression X, given that X appears in
1751 static enum mips_symbol_type
1752 mips_classify_symbolic_expression (rtx x, enum mips_symbol_context context)
1756 split_const (x, &x, &offset);
1757 if (UNSPEC_ADDRESS_P (x))
1758 return UNSPEC_ADDRESS_TYPE (x);
1760 return mips_classify_symbol (x, context);
1763 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1764 is the alignment in bytes of SYMBOL_REF X. */
1767 mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset)
1769 HOST_WIDE_INT align;
1771 align = SYMBOL_REF_DECL (x) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x)) : 1;
1772 return IN_RANGE (offset, 0, align - 1);
1775 /* Return true if X is a symbolic constant that can be used in context
1776 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1779 mips_symbolic_constant_p (rtx x, enum mips_symbol_context context,
1780 enum mips_symbol_type *symbol_type)
1784 split_const (x, &x, &offset);
1785 if (UNSPEC_ADDRESS_P (x))
1787 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1788 x = UNSPEC_ADDRESS (x);
1790 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1792 *symbol_type = mips_classify_symbol (x, context);
1793 if (*symbol_type == SYMBOL_TLS)
1799 if (offset == const0_rtx)
1802 /* Check whether a nonzero offset is valid for the underlying
1804 switch (*symbol_type)
1806 case SYMBOL_ABSOLUTE:
1807 case SYMBOL_FORCE_TO_MEM:
1808 case SYMBOL_32_HIGH:
1809 case SYMBOL_64_HIGH:
1812 /* If the target has 64-bit pointers and the object file only
1813 supports 32-bit symbols, the values of those symbols will be
1814 sign-extended. In this case we can't allow an arbitrary offset
1815 in case the 32-bit value X + OFFSET has a different sign from X. */
1816 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1817 return offset_within_block_p (x, INTVAL (offset));
1819 /* In other cases the relocations can handle any offset. */
1822 case SYMBOL_PC_RELATIVE:
1823 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1824 In this case, we no longer have access to the underlying constant,
1825 but the original symbol-based access was known to be valid. */
1826 if (GET_CODE (x) == LABEL_REF)
1831 case SYMBOL_GP_RELATIVE:
1832 /* Make sure that the offset refers to something within the
1833 same object block. This should guarantee that the final
1834 PC- or GP-relative offset is within the 16-bit limit. */
1835 return offset_within_block_p (x, INTVAL (offset));
1837 case SYMBOL_GOT_PAGE_OFST:
1838 case SYMBOL_GOTOFF_PAGE:
1839 /* If the symbol is global, the GOT entry will contain the symbol's
1840 address, and we will apply a 16-bit offset after loading it.
1841 If the symbol is local, the linker should provide enough local
1842 GOT entries for a 16-bit offset, but larger offsets may lead
1844 return SMALL_INT (offset);
1848 /* There is no carry between the HI and LO REL relocations, so the
1849 offset is only valid if we know it won't lead to such a carry. */
1850 return mips_offset_within_alignment_p (x, INTVAL (offset));
1852 case SYMBOL_GOT_DISP:
1853 case SYMBOL_GOTOFF_DISP:
1854 case SYMBOL_GOTOFF_CALL:
1855 case SYMBOL_GOTOFF_LOADGP:
1858 case SYMBOL_GOTTPREL:
1866 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
1867 single instruction. We rely on the fact that, in the worst case,
1868 all instructions involved in a MIPS16 address calculation are usually
1872 mips_symbol_insns_1 (enum mips_symbol_type type, enum machine_mode mode)
1876 case SYMBOL_ABSOLUTE:
1877 /* When using 64-bit symbols, we need 5 preparatory instructions,
1880 lui $at,%highest(symbol)
1881 daddiu $at,$at,%higher(symbol)
1883 daddiu $at,$at,%hi(symbol)
1886 The final address is then $at + %lo(symbol). With 32-bit
1887 symbols we just need a preparatory LUI for normal mode and
1888 a preparatory LI and SLL for MIPS16. */
1889 return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2;
1891 case SYMBOL_GP_RELATIVE:
1892 /* Treat GP-relative accesses as taking a single instruction on
1893 MIPS16 too; the copy of $gp can often be shared. */
1896 case SYMBOL_PC_RELATIVE:
1897 /* PC-relative constants can be only be used with ADDIUPC,
1898 DADDIUPC, LWPC and LDPC. */
1899 if (mode == MAX_MACHINE_MODE
1900 || GET_MODE_SIZE (mode) == 4
1901 || GET_MODE_SIZE (mode) == 8)
1904 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
1907 case SYMBOL_FORCE_TO_MEM:
1908 /* LEAs will be converted into constant-pool references by
1910 if (mode == MAX_MACHINE_MODE)
1913 /* The constant must be loaded and then dereferenced. */
1916 case SYMBOL_GOT_DISP:
1917 /* The constant will have to be loaded from the GOT before it
1918 is used in an address. */
1919 if (mode != MAX_MACHINE_MODE)
1924 case SYMBOL_GOT_PAGE_OFST:
1925 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
1926 local/global classification is accurate. The worst cases are:
1928 (1) For local symbols when generating o32 or o64 code. The assembler
1934 ...and the final address will be $at + %lo(symbol).
1936 (2) For global symbols when -mxgot. The assembler will use:
1938 lui $at,%got_hi(symbol)
1941 ...and the final address will be $at + %got_lo(symbol). */
1944 case SYMBOL_GOTOFF_PAGE:
1945 case SYMBOL_GOTOFF_DISP:
1946 case SYMBOL_GOTOFF_CALL:
1947 case SYMBOL_GOTOFF_LOADGP:
1948 case SYMBOL_32_HIGH:
1949 case SYMBOL_64_HIGH:
1955 case SYMBOL_GOTTPREL:
1958 /* A 16-bit constant formed by a single relocation, or a 32-bit
1959 constant formed from a high 16-bit relocation and a low 16-bit
1960 relocation. Use mips_split_p to determine which. 32-bit
1961 constants need an "lui; addiu" sequence for normal mode and
1962 an "li; sll; addiu" sequence for MIPS16 mode. */
1963 return !mips_split_p[type] ? 1 : TARGET_MIPS16 ? 3 : 2;
1966 /* We don't treat a bare TLS symbol as a constant. */
1972 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
1973 to load symbols of type TYPE into a register. Return 0 if the given
1974 type of symbol cannot be used as an immediate operand.
1976 Otherwise, return the number of instructions needed to load or store
1977 values of mode MODE to or from addresses of type TYPE. Return 0 if
1978 the given type of symbol is not valid in addresses.
1980 In both cases, treat extended MIPS16 instructions as two instructions. */
1983 mips_symbol_insns (enum mips_symbol_type type, enum machine_mode mode)
1985 return mips_symbol_insns_1 (type, mode) * (TARGET_MIPS16 ? 2 : 1);
1988 /* A for_each_rtx callback. Stop the search if *X references a
1989 thread-local symbol. */
1992 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1994 return mips_tls_symbol_p (*x);
1997 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
2000 mips_cannot_force_const_mem (rtx x)
2002 enum mips_symbol_type type;
2005 /* There is no assembler syntax for expressing an address-sized
2007 if (GET_CODE (x) == HIGH)
2010 /* As an optimization, reject constants that mips_legitimize_move
2013 Suppose we have a multi-instruction sequence that loads constant C
2014 into register R. If R does not get allocated a hard register, and
2015 R is used in an operand that allows both registers and memory
2016 references, reload will consider forcing C into memory and using
2017 one of the instruction's memory alternatives. Returning false
2018 here will force it to use an input reload instead. */
2019 if (CONST_INT_P (x) && LEGITIMATE_CONSTANT_P (x))
2022 split_const (x, &base, &offset);
2023 if (mips_symbolic_constant_p (base, SYMBOL_CONTEXT_LEA, &type)
2024 && type != SYMBOL_FORCE_TO_MEM)
2026 /* The same optimization as for CONST_INT. */
2027 if (SMALL_INT (offset) && mips_symbol_insns (type, MAX_MACHINE_MODE) > 0)
2030 /* If MIPS16 constant pools live in the text section, they should
2031 not refer to anything that might need run-time relocation. */
2032 if (TARGET_MIPS16_PCREL_LOADS && mips_got_symbol_type_p (type))
2036 /* TLS symbols must be computed by mips_legitimize_move. */
2037 if (for_each_rtx (&x, &mips_tls_symbol_ref_1, NULL))
2043 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
2044 constants when we're using a per-function constant pool. */
2047 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
2048 const_rtx x ATTRIBUTE_UNUSED)
2050 return !TARGET_MIPS16_PCREL_LOADS;
2053 /* Return true if register REGNO is a valid base register for mode MODE.
2054 STRICT_P is true if REG_OK_STRICT is in effect. */
2057 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode,
2060 if (!HARD_REGISTER_NUM_P (regno))
2064 regno = reg_renumber[regno];
2067 /* These fake registers will be eliminated to either the stack or
2068 hard frame pointer, both of which are usually valid base registers.
2069 Reload deals with the cases where the eliminated form isn't valid. */
2070 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
2073 /* In MIPS16 mode, the stack pointer can only address word and doubleword
2074 values, nothing smaller. There are two problems here:
2076 (a) Instantiating virtual registers can introduce new uses of the
2077 stack pointer. If these virtual registers are valid addresses,
2078 the stack pointer should be too.
2080 (b) Most uses of the stack pointer are not made explicit until
2081 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
2082 We don't know until that stage whether we'll be eliminating to the
2083 stack pointer (which needs the restriction) or the hard frame
2084 pointer (which doesn't).
2086 All in all, it seems more consistent to only enforce this restriction
2087 during and after reload. */
2088 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
2089 return !strict_p || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
2091 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
2094 /* Return true if X is a valid base register for mode MODE.
2095 STRICT_P is true if REG_OK_STRICT is in effect. */
2098 mips_valid_base_register_p (rtx x, enum machine_mode mode, bool strict_p)
2100 if (!strict_p && GET_CODE (x) == SUBREG)
2104 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p));
2107 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2108 can address a value of mode MODE. */
2111 mips_valid_offset_p (rtx x, enum machine_mode mode)
2113 /* Check that X is a signed 16-bit number. */
2114 if (!const_arith_operand (x, Pmode))
2117 /* We may need to split multiword moves, so make sure that every word
2119 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2120 && !SMALL_OPERAND (INTVAL (x) + GET_MODE_SIZE (mode) - UNITS_PER_WORD))
2126 /* Return true if a LO_SUM can address a value of mode MODE when the
2127 LO_SUM symbol has type SYMBOL_TYPE. */
2130 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type, enum machine_mode mode)
2132 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2134 if (mips_symbol_insns (symbol_type, mode) == 0)
2137 /* Check that there is a known low-part relocation. */
2138 if (mips_lo_relocs[symbol_type] == NULL)
2141 /* We may need to split multiword moves, so make sure that each word
2142 can be accessed without inducing a carry. This is mainly needed
2143 for o64, which has historically only guaranteed 64-bit alignment
2144 for 128-bit types. */
2145 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2146 && GET_MODE_BITSIZE (mode) > GET_MODE_ALIGNMENT (mode))
2152 /* Return true if X is a valid address for machine mode MODE. If it is,
2153 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2157 mips_classify_address (struct mips_address_info *info, rtx x,
2158 enum machine_mode mode, bool strict_p)
2160 switch (GET_CODE (x))
2164 info->type = ADDRESS_REG;
2166 info->offset = const0_rtx;
2167 return mips_valid_base_register_p (info->reg, mode, strict_p);
2170 info->type = ADDRESS_REG;
2171 info->reg = XEXP (x, 0);
2172 info->offset = XEXP (x, 1);
2173 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2174 && mips_valid_offset_p (info->offset, mode));
2177 info->type = ADDRESS_LO_SUM;
2178 info->reg = XEXP (x, 0);
2179 info->offset = XEXP (x, 1);
2180 /* We have to trust the creator of the LO_SUM to do something vaguely
2181 sane. Target-independent code that creates a LO_SUM should also
2182 create and verify the matching HIGH. Target-independent code that
2183 adds an offset to a LO_SUM must prove that the offset will not
2184 induce a carry. Failure to do either of these things would be
2185 a bug, and we are not required to check for it here. The MIPS
2186 backend itself should only create LO_SUMs for valid symbolic
2187 constants, with the high part being either a HIGH or a copy
2190 = mips_classify_symbolic_expression (info->offset, SYMBOL_CONTEXT_MEM);
2191 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2192 && mips_valid_lo_sum_p (info->symbol_type, mode));
2195 /* Small-integer addresses don't occur very often, but they
2196 are legitimate if $0 is a valid base register. */
2197 info->type = ADDRESS_CONST_INT;
2198 return !TARGET_MIPS16 && SMALL_INT (x);
2203 info->type = ADDRESS_SYMBOLIC;
2204 return (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_MEM,
2206 && mips_symbol_insns (info->symbol_type, mode) > 0
2207 && !mips_split_p[info->symbol_type]);
2214 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2217 mips_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
2219 struct mips_address_info addr;
2221 return mips_classify_address (&addr, x, mode, strict_p);
2224 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
2227 mips_stack_address_p (rtx x, enum machine_mode mode)
2229 struct mips_address_info addr;
2231 return (mips_classify_address (&addr, x, mode, false)
2232 && addr.type == ADDRESS_REG
2233 && addr.reg == stack_pointer_rtx);
2236 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2237 address instruction. Note that such addresses are not considered
2238 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2239 is so restricted. */
2242 mips_lwxs_address_p (rtx addr)
2245 && GET_CODE (addr) == PLUS
2246 && REG_P (XEXP (addr, 1)))
2248 rtx offset = XEXP (addr, 0);
2249 if (GET_CODE (offset) == MULT
2250 && REG_P (XEXP (offset, 0))
2251 && CONST_INT_P (XEXP (offset, 1))
2252 && INTVAL (XEXP (offset, 1)) == 4)
2258 /* Return true if a value at OFFSET bytes from base register BASE can be
2259 accessed using an unextended MIPS16 instruction. MODE is the mode of
2262 Usually the offset in an unextended instruction is a 5-bit field.
2263 The offset is unsigned and shifted left once for LH and SH, twice
2264 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2265 an 8-bit immediate field that's shifted left twice. */
2268 mips16_unextended_reference_p (enum machine_mode mode, rtx base,
2269 unsigned HOST_WIDE_INT offset)
2271 if (offset % GET_MODE_SIZE (mode) == 0)
2273 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
2274 return offset < 256U * GET_MODE_SIZE (mode);
2275 return offset < 32U * GET_MODE_SIZE (mode);
2280 /* Return the number of instructions needed to load or store a value
2281 of mode MODE at address X. Return 0 if X isn't valid for MODE.
2282 Assume that multiword moves may need to be split into word moves
2283 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2286 For MIPS16 code, count extended instructions as two instructions. */
2289 mips_address_insns (rtx x, enum machine_mode mode, bool might_split_p)
2291 struct mips_address_info addr;
2294 /* BLKmode is used for single unaligned loads and stores and should
2295 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2296 meaningless, so we have to single it out as a special case one way
2298 if (mode != BLKmode && might_split_p)
2299 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2303 if (mips_classify_address (&addr, x, mode, false))
2308 && !mips16_unextended_reference_p (mode, addr.reg,
2309 UINTVAL (addr.offset)))
2313 case ADDRESS_LO_SUM:
2314 return TARGET_MIPS16 ? factor * 2 : factor;
2316 case ADDRESS_CONST_INT:
2319 case ADDRESS_SYMBOLIC:
2320 return factor * mips_symbol_insns (addr.symbol_type, mode);
2325 /* Return the number of instructions needed to load constant X.
2326 Return 0 if X isn't a valid constant. */
2329 mips_const_insns (rtx x)
2331 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2332 enum mips_symbol_type symbol_type;
2335 switch (GET_CODE (x))
2338 if (!mips_symbolic_constant_p (XEXP (x, 0), SYMBOL_CONTEXT_LEA,
2340 || !mips_split_p[symbol_type])
2343 /* This is simply an LUI for normal mode. It is an extended
2344 LI followed by an extended SLL for MIPS16. */
2345 return TARGET_MIPS16 ? 4 : 1;
2349 /* Unsigned 8-bit constants can be loaded using an unextended
2350 LI instruction. Unsigned 16-bit constants can be loaded
2351 using an extended LI. Negative constants must be loaded
2352 using LI and then negated. */
2353 return (IN_RANGE (INTVAL (x), 0, 255) ? 1
2354 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
2355 : IN_RANGE (-INTVAL (x), 0, 255) ? 2
2356 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
2359 return mips_build_integer (codes, INTVAL (x));
2363 /* Allow zeros for normal mode, where we can use $0. */
2364 return !TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0;
2370 /* See if we can refer to X directly. */
2371 if (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_LEA, &symbol_type))
2372 return mips_symbol_insns (symbol_type, MAX_MACHINE_MODE);
2374 /* Otherwise try splitting the constant into a base and offset.
2375 If the offset is a 16-bit value, we can load the base address
2376 into a register and then use (D)ADDIU to add in the offset.
2377 If the offset is larger, we can load the base and offset
2378 into separate registers and add them together with (D)ADDU.
2379 However, the latter is only possible before reload; during
2380 and after reload, we must have the option of forcing the
2381 constant into the pool instead. */
2382 split_const (x, &x, &offset);
2385 int n = mips_const_insns (x);
2388 if (SMALL_INT (offset))
2390 else if (!targetm.cannot_force_const_mem (x))
2391 return n + 1 + mips_build_integer (codes, INTVAL (offset));
2398 return mips_symbol_insns (mips_classify_symbol (x, SYMBOL_CONTEXT_LEA),
2406 /* X is a doubleword constant that can be handled by splitting it into
2407 two words and loading each word separately. Return the number of
2408 instructions required to do this. */
2411 mips_split_const_insns (rtx x)
2413 unsigned int low, high;
2415 low = mips_const_insns (mips_subword (x, false));
2416 high = mips_const_insns (mips_subword (x, true));
2417 gcc_assert (low > 0 && high > 0);
2421 /* Return the number of instructions needed to implement INSN,
2422 given that it loads from or stores to MEM. Count extended
2423 MIPS16 instructions as two instructions. */
2426 mips_load_store_insns (rtx mem, rtx insn)
2428 enum machine_mode mode;
2432 gcc_assert (MEM_P (mem));
2433 mode = GET_MODE (mem);
2435 /* Try to prove that INSN does not need to be split. */
2436 might_split_p = true;
2437 if (GET_MODE_BITSIZE (mode) == 64)
2439 set = single_set (insn);
2440 if (set && !mips_split_64bit_move_p (SET_DEST (set), SET_SRC (set)))
2441 might_split_p = false;
2444 return mips_address_insns (XEXP (mem, 0), mode, might_split_p);
2447 /* Return the number of instructions needed for an integer division. */
2450 mips_idiv_insns (void)
2455 if (TARGET_CHECK_ZERO_DIV)
2457 if (GENERATE_DIVIDE_TRAPS)
2463 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
2468 /* Emit a move from SRC to DEST. Assume that the move expanders can
2469 handle all moves if !can_create_pseudo_p (). The distinction is
2470 important because, unlike emit_move_insn, the move expanders know
2471 how to force Pmode objects into the constant pool even when the
2472 constant pool address is not itself legitimate. */
2475 mips_emit_move (rtx dest, rtx src)
2477 return (can_create_pseudo_p ()
2478 ? emit_move_insn (dest, src)
2479 : emit_move_insn_1 (dest, src));
2482 /* Emit an instruction of the form (set TARGET (CODE OP0)). */
2485 mips_emit_unary (enum rtx_code code, rtx target, rtx op0)
2487 emit_insn (gen_rtx_SET (VOIDmode, target,
2488 gen_rtx_fmt_e (code, GET_MODE (op0), op0)));
2491 /* Compute (CODE OP0) and store the result in a new register of mode MODE.
2492 Return that new register. */
2495 mips_force_unary (enum machine_mode mode, enum rtx_code code, rtx op0)
2499 reg = gen_reg_rtx (mode);
2500 mips_emit_unary (code, reg, op0);
2504 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2507 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
2509 emit_insn (gen_rtx_SET (VOIDmode, target,
2510 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
2513 /* Compute (CODE OP0 OP1) and store the result in a new register
2514 of mode MODE. Return that new register. */
2517 mips_force_binary (enum machine_mode mode, enum rtx_code code, rtx op0, rtx op1)
2521 reg = gen_reg_rtx (mode);
2522 mips_emit_binary (code, reg, op0, op1);
2526 /* Copy VALUE to a register and return that register. If new pseudos
2527 are allowed, copy it into a new register, otherwise use DEST. */
2530 mips_force_temporary (rtx dest, rtx value)
2532 if (can_create_pseudo_p ())
2533 return force_reg (Pmode, value);
2536 mips_emit_move (dest, value);
2541 /* Emit a call sequence with call pattern PATTERN and return the call
2542 instruction itself (which is not necessarily the last instruction
2543 emitted). ORIG_ADDR is the original, unlegitimized address,
2544 ADDR is the legitimized form, and LAZY_P is true if the call
2545 address is lazily-bound. */
2548 mips_emit_call_insn (rtx pattern, rtx orig_addr, rtx addr, bool lazy_p)
2552 insn = emit_call_insn (pattern);
2554 if (TARGET_MIPS16 && mips_use_pic_fn_addr_reg_p (orig_addr))
2556 /* MIPS16 JALRs only take MIPS16 registers. If the target
2557 function requires $25 to be valid on entry, we must copy it
2558 there separately. The move instruction can be put in the
2559 call's delay slot. */
2560 reg = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
2561 emit_insn_before (gen_move_insn (reg, addr), insn);
2562 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
2566 /* Lazy-binding stubs require $gp to be valid on entry. */
2567 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
2571 /* See the comment above load_call<mode> for details. */
2572 use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
2573 gen_rtx_REG (Pmode, GOT_VERSION_REGNUM));
2574 emit_insn (gen_update_got_version ());
2579 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2580 then add CONST_INT OFFSET to the result. */
2583 mips_unspec_address_offset (rtx base, rtx offset,
2584 enum mips_symbol_type symbol_type)
2586 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
2587 UNSPEC_ADDRESS_FIRST + symbol_type);
2588 if (offset != const0_rtx)
2589 base = gen_rtx_PLUS (Pmode, base, offset);
2590 return gen_rtx_CONST (Pmode, base);
2593 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2594 type SYMBOL_TYPE. */
2597 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
2601 split_const (address, &base, &offset);
2602 return mips_unspec_address_offset (base, offset, symbol_type);
2605 /* If OP is an UNSPEC address, return the address to which it refers,
2606 otherwise return OP itself. */
2609 mips_strip_unspec_address (rtx op)
2613 split_const (op, &base, &offset);
2614 if (UNSPEC_ADDRESS_P (base))
2615 op = plus_constant (UNSPEC_ADDRESS (base), INTVAL (offset));
2619 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2620 high part to BASE and return the result. Just return BASE otherwise.
2621 TEMP is as for mips_force_temporary.
2623 The returned expression can be used as the first operand to a LO_SUM. */
2626 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
2627 enum mips_symbol_type symbol_type)
2629 if (mips_split_p[symbol_type])
2631 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
2632 addr = mips_force_temporary (temp, addr);
2633 base = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
2638 /* Return an instruction that copies $gp into register REG. We want
2639 GCC to treat the register's value as constant, so that its value
2640 can be rematerialized on demand. */
2643 gen_load_const_gp (rtx reg)
2645 return (Pmode == SImode
2646 ? gen_load_const_gp_si (reg)
2647 : gen_load_const_gp_di (reg));
2650 /* Return a pseudo register that contains the value of $gp throughout
2651 the current function. Such registers are needed by MIPS16 functions,
2652 for which $gp itself is not a valid base register or addition operand. */
2655 mips16_gp_pseudo_reg (void)
2657 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
2661 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
2663 push_topmost_sequence ();
2665 scan = get_insns ();
2666 while (NEXT_INSN (scan) && !INSN_P (NEXT_INSN (scan)))
2667 scan = NEXT_INSN (scan);
2669 insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
2670 emit_insn_after (insn, scan);
2672 pop_topmost_sequence ();
2675 return cfun->machine->mips16_gp_pseudo_rtx;
2678 /* Return a base register that holds pic_offset_table_rtx.
2679 TEMP, if nonnull, is a scratch Pmode base register. */
2682 mips_pic_base_register (rtx temp)
2685 return pic_offset_table_rtx;
2687 if (currently_expanding_to_rtl)
2688 return mips16_gp_pseudo_reg ();
2690 if (can_create_pseudo_p ())
2691 temp = gen_reg_rtx (Pmode);
2694 /* The first post-reload split exposes all references to $gp
2695 (both uses and definitions). All references must remain
2696 explicit after that point.
2698 It is safe to introduce uses of $gp at any time, so for
2699 simplicity, we do that before the split too. */
2700 mips_emit_move (temp, pic_offset_table_rtx);
2702 emit_insn (gen_load_const_gp (temp));
2706 /* Return the RHS of a load_call<mode> insn. */
2709 mips_unspec_call (rtx reg, rtx symbol)
2713 vec = gen_rtvec (3, reg, symbol, gen_rtx_REG (SImode, GOT_VERSION_REGNUM));
2714 return gen_rtx_UNSPEC (Pmode, vec, UNSPEC_LOAD_CALL);
2717 /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol
2718 reference. Return NULL_RTX otherwise. */
2721 mips_strip_unspec_call (rtx src)
2723 if (GET_CODE (src) == UNSPEC && XINT (src, 1) == UNSPEC_LOAD_CALL)
2724 return mips_strip_unspec_address (XVECEXP (src, 0, 1));
2728 /* Create and return a GOT reference of type TYPE for address ADDR.
2729 TEMP, if nonnull, is a scratch Pmode base register. */
2732 mips_got_load (rtx temp, rtx addr, enum mips_symbol_type type)
2734 rtx base, high, lo_sum_symbol;
2736 base = mips_pic_base_register (temp);
2738 /* If we used the temporary register to load $gp, we can't use
2739 it for the high part as well. */
2740 if (temp != NULL && reg_overlap_mentioned_p (base, temp))
2743 high = mips_unspec_offset_high (temp, base, addr, type);
2744 lo_sum_symbol = mips_unspec_address (addr, type);
2746 if (type == SYMBOL_GOTOFF_CALL)
2747 return mips_unspec_call (high, lo_sum_symbol);
2749 return (Pmode == SImode
2750 ? gen_unspec_gotsi (high, lo_sum_symbol)
2751 : gen_unspec_gotdi (high, lo_sum_symbol));
2754 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2755 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2756 constant in that context and can be split into high and low parts.
2757 If so, and if LOW_OUT is nonnull, emit the high part and store the
2758 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
2760 TEMP is as for mips_force_temporary and is used to load the high
2761 part into a register.
2763 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
2764 a legitimize SET_SRC for an .md pattern, otherwise the low part
2765 is guaranteed to be a legitimate address for mode MODE. */
2768 mips_split_symbol (rtx temp, rtx addr, enum machine_mode mode, rtx *low_out)
2770 enum mips_symbol_context context;
2771 enum mips_symbol_type symbol_type;
2774 context = (mode == MAX_MACHINE_MODE
2775 ? SYMBOL_CONTEXT_LEA
2776 : SYMBOL_CONTEXT_MEM);
2777 if (GET_CODE (addr) == HIGH && context == SYMBOL_CONTEXT_LEA)
2779 addr = XEXP (addr, 0);
2780 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2781 && mips_symbol_insns (symbol_type, mode) > 0
2782 && mips_split_hi_p[symbol_type])
2785 switch (symbol_type)
2787 case SYMBOL_GOT_PAGE_OFST:
2788 /* The high part of a page/ofst pair is loaded from the GOT. */
2789 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_PAGE);
2800 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2801 && mips_symbol_insns (symbol_type, mode) > 0
2802 && mips_split_p[symbol_type])
2805 switch (symbol_type)
2807 case SYMBOL_GOT_DISP:
2808 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
2809 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_DISP);
2812 case SYMBOL_GP_RELATIVE:
2813 high = mips_pic_base_register (temp);
2814 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2818 high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
2819 high = mips_force_temporary (temp, high);
2820 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2829 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2830 mips_force_temporary; it is only needed when OFFSET is not a
2834 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
2836 if (!SMALL_OPERAND (offset))
2842 /* Load the full offset into a register so that we can use
2843 an unextended instruction for the address itself. */
2844 high = GEN_INT (offset);
2849 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
2850 The addition inside the macro CONST_HIGH_PART may cause an
2851 overflow, so we need to force a sign-extension check. */
2852 high = gen_int_mode (CONST_HIGH_PART (offset), Pmode);
2853 offset = CONST_LOW_PART (offset);
2855 high = mips_force_temporary (temp, high);
2856 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
2858 return plus_constant (reg, offset);
2861 /* The __tls_get_attr symbol. */
2862 static GTY(()) rtx mips_tls_symbol;
2864 /* Return an instruction sequence that calls __tls_get_addr. SYM is
2865 the TLS symbol we are referencing and TYPE is the symbol type to use
2866 (either global dynamic or local dynamic). V0 is an RTX for the
2867 return value location. */
2870 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
2874 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
2876 if (!mips_tls_symbol)
2877 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
2879 loc = mips_unspec_address (sym, type);
2883 emit_insn (gen_rtx_SET (Pmode, a0,
2884 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
2885 insn = mips_expand_call (MIPS_CALL_NORMAL, v0, mips_tls_symbol,
2886 const0_rtx, NULL_RTX, false);
2887 RTL_CONST_CALL_P (insn) = 1;
2888 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
2889 insn = get_insns ();
2896 /* Return a pseudo register that contains the current thread pointer. */
2903 tp = gen_reg_rtx (Pmode);
2904 if (Pmode == DImode)
2905 emit_insn (gen_tls_get_tp_di (tp));
2907 emit_insn (gen_tls_get_tp_si (tp));
2911 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
2912 its address. The return value will be both a valid address and a valid
2913 SET_SRC (either a REG or a LO_SUM). */
2916 mips_legitimize_tls_address (rtx loc)
2918 rtx dest, insn, v0, tp, tmp1, tmp2, eqv;
2919 enum tls_model model;
2923 sorry ("MIPS16 TLS");
2924 return gen_reg_rtx (Pmode);
2927 model = SYMBOL_REF_TLS_MODEL (loc);
2928 /* Only TARGET_ABICALLS code can have more than one module; other
2929 code must be be static and should not use a GOT. All TLS models
2930 reduce to local exec in this situation. */
2931 if (!TARGET_ABICALLS)
2932 model = TLS_MODEL_LOCAL_EXEC;
2936 case TLS_MODEL_GLOBAL_DYNAMIC:
2937 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2938 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
2939 dest = gen_reg_rtx (Pmode);
2940 emit_libcall_block (insn, dest, v0, loc);
2943 case TLS_MODEL_LOCAL_DYNAMIC:
2944 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2945 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
2946 tmp1 = gen_reg_rtx (Pmode);
2948 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2949 share the LDM result with other LD model accesses. */
2950 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2952 emit_libcall_block (insn, tmp1, v0, eqv);
2954 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
2955 dest = gen_rtx_LO_SUM (Pmode, tmp2,
2956 mips_unspec_address (loc, SYMBOL_DTPREL));
2959 case TLS_MODEL_INITIAL_EXEC:
2960 tp = mips_get_tp ();
2961 tmp1 = gen_reg_rtx (Pmode);
2962 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
2963 if (Pmode == DImode)
2964 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
2966 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
2967 dest = gen_reg_rtx (Pmode);
2968 emit_insn (gen_add3_insn (dest, tmp1, tp));
2971 case TLS_MODEL_LOCAL_EXEC:
2972 tp = mips_get_tp ();
2973 tmp1 = mips_unspec_offset_high (NULL, tp, loc, SYMBOL_TPREL);
2974 dest = gen_rtx_LO_SUM (Pmode, tmp1,
2975 mips_unspec_address (loc, SYMBOL_TPREL));
2984 /* If X is not a valid address for mode MODE, force it into a register. */
2987 mips_force_address (rtx x, enum machine_mode mode)
2989 if (!mips_legitimate_address_p (mode, x, false))
2990 x = force_reg (Pmode, x);
2994 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
2995 be legitimized in a way that the generic machinery might not expect,
2996 return a new address, otherwise return NULL. MODE is the mode of
2997 the memory being accessed. */
3000 mips_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3001 enum machine_mode mode)
3004 HOST_WIDE_INT offset;
3006 if (mips_tls_symbol_p (x))
3007 return mips_legitimize_tls_address (x);
3009 /* See if the address can split into a high part and a LO_SUM. */
3010 if (mips_split_symbol (NULL, x, mode, &addr))
3011 return mips_force_address (addr, mode);
3013 /* Handle BASE + OFFSET using mips_add_offset. */
3014 mips_split_plus (x, &base, &offset);
3017 if (!mips_valid_base_register_p (base, mode, false))
3018 base = copy_to_mode_reg (Pmode, base);
3019 addr = mips_add_offset (NULL, base, offset);
3020 return mips_force_address (addr, mode);
3026 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
3029 mips_move_integer (rtx temp, rtx dest, unsigned HOST_WIDE_INT value)
3031 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
3032 enum machine_mode mode;
3033 unsigned int i, num_ops;
3036 mode = GET_MODE (dest);
3037 num_ops = mips_build_integer (codes, value);
3039 /* Apply each binary operation to X. Invariant: X is a legitimate
3040 source operand for a SET pattern. */
3041 x = GEN_INT (codes[0].value);
3042 for (i = 1; i < num_ops; i++)
3044 if (!can_create_pseudo_p ())
3046 emit_insn (gen_rtx_SET (VOIDmode, temp, x));
3050 x = force_reg (mode, x);
3051 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
3054 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
3057 /* Subroutine of mips_legitimize_move. Move constant SRC into register
3058 DEST given that SRC satisfies immediate_operand but doesn't satisfy
3062 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
3066 /* Split moves of big integers into smaller pieces. */
3067 if (splittable_const_int_operand (src, mode))
3069 mips_move_integer (dest, dest, INTVAL (src));
3073 /* Split moves of symbolic constants into high/low pairs. */
3074 if (mips_split_symbol (dest, src, MAX_MACHINE_MODE, &src))
3076 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
3080 /* Generate the appropriate access sequences for TLS symbols. */
3081 if (mips_tls_symbol_p (src))
3083 mips_emit_move (dest, mips_legitimize_tls_address (src));
3087 /* If we have (const (plus symbol offset)), and that expression cannot
3088 be forced into memory, load the symbol first and add in the offset.
3089 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
3090 forced into memory, as it usually produces better code. */
3091 split_const (src, &base, &offset);
3092 if (offset != const0_rtx
3093 && (targetm.cannot_force_const_mem (src)
3094 || (!TARGET_MIPS16 && can_create_pseudo_p ())))
3096 base = mips_force_temporary (dest, base);
3097 mips_emit_move (dest, mips_add_offset (NULL, base, INTVAL (offset)));
3101 src = force_const_mem (mode, src);
3103 /* When using explicit relocs, constant pool references are sometimes
3104 not legitimate addresses. */
3105 mips_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0));
3106 mips_emit_move (dest, src);
3109 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
3110 sequence that is valid. */
3113 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
3115 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
3117 mips_emit_move (dest, force_reg (mode, src));
3121 /* We need to deal with constants that would be legitimate
3122 immediate_operands but aren't legitimate move_operands. */
3123 if (CONSTANT_P (src) && !move_operand (src, mode))
3125 mips_legitimize_const_move (mode, dest, src);
3126 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
3132 /* Return true if value X in context CONTEXT is a small-data address
3133 that can be rewritten as a LO_SUM. */
3136 mips_rewrite_small_data_p (rtx x, enum mips_symbol_context context)
3138 enum mips_symbol_type symbol_type;
3140 return (mips_lo_relocs[SYMBOL_GP_RELATIVE]
3141 && !mips_split_p[SYMBOL_GP_RELATIVE]
3142 && mips_symbolic_constant_p (x, context, &symbol_type)
3143 && symbol_type == SYMBOL_GP_RELATIVE);
3146 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
3147 containing MEM, or null if none. */
3150 mips_small_data_pattern_1 (rtx *loc, void *data)
3152 enum mips_symbol_context context;
3154 if (GET_CODE (*loc) == LO_SUM)
3159 if (for_each_rtx (&XEXP (*loc, 0), mips_small_data_pattern_1, *loc))
3164 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3165 return mips_rewrite_small_data_p (*loc, context);
3168 /* Return true if OP refers to small data symbols directly, not through
3172 mips_small_data_pattern_p (rtx op)
3174 return for_each_rtx (&op, mips_small_data_pattern_1, NULL);
3177 /* A for_each_rtx callback, used by mips_rewrite_small_data.
3178 DATA is the containing MEM, or null if none. */
3181 mips_rewrite_small_data_1 (rtx *loc, void *data)
3183 enum mips_symbol_context context;
3187 for_each_rtx (&XEXP (*loc, 0), mips_rewrite_small_data_1, *loc);
3191 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3192 if (mips_rewrite_small_data_p (*loc, context))
3193 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
3195 if (GET_CODE (*loc) == LO_SUM)
3201 /* Rewrite instruction pattern PATTERN so that it refers to small data
3202 using explicit relocations. */
3205 mips_rewrite_small_data (rtx pattern)
3207 pattern = copy_insn (pattern);
3208 for_each_rtx (&pattern, mips_rewrite_small_data_1, NULL);
3212 /* We need a lot of little routines to check the range of MIPS16 immediate
3216 m16_check_op (rtx op, int low, int high, int mask)
3218 return (CONST_INT_P (op)
3219 && IN_RANGE (INTVAL (op), low, high)
3220 && (INTVAL (op) & mask) == 0);
3224 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3226 return m16_check_op (op, 0x1, 0x8, 0);
3230 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3232 return m16_check_op (op, -0x8, 0x7, 0);
3236 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3238 return m16_check_op (op, -0x7, 0x8, 0);
3242 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3244 return m16_check_op (op, -0x10, 0xf, 0);
3248 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3250 return m16_check_op (op, -0xf, 0x10, 0);
3254 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3256 return m16_check_op (op, -0x10 << 2, 0xf << 2, 3);
3260 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3262 return m16_check_op (op, -0xf << 2, 0x10 << 2, 3);
3266 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3268 return m16_check_op (op, -0x80, 0x7f, 0);
3272 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3274 return m16_check_op (op, -0x7f, 0x80, 0);
3278 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3280 return m16_check_op (op, 0x0, 0xff, 0);
3284 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3286 return m16_check_op (op, -0xff, 0x0, 0);
3290 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3292 return m16_check_op (op, -0x1, 0xfe, 0);
3296 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3298 return m16_check_op (op, 0x0, 0xff << 2, 3);
3302 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3304 return m16_check_op (op, -0xff << 2, 0x0, 3);
3308 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3310 return m16_check_op (op, -0x80 << 3, 0x7f << 3, 7);
3314 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3316 return m16_check_op (op, -0x7f << 3, 0x80 << 3, 7);
3319 /* The cost of loading values from the constant pool. It should be
3320 larger than the cost of any constant we want to synthesize inline. */
3321 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3323 /* Return the cost of X when used as an operand to the MIPS16 instruction
3324 that implements CODE. Return -1 if there is no such instruction, or if
3325 X is not a valid immediate operand for it. */
3328 mips16_constant_cost (int code, HOST_WIDE_INT x)
3335 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3336 other shifts are extended. The shift patterns truncate the shift
3337 count to the right size, so there are no out-of-range values. */
3338 if (IN_RANGE (x, 1, 8))
3340 return COSTS_N_INSNS (1);
3343 if (IN_RANGE (x, -128, 127))
3345 if (SMALL_OPERAND (x))
3346 return COSTS_N_INSNS (1);
3350 /* Like LE, but reject the always-true case. */
3354 /* We add 1 to the immediate and use SLT. */
3357 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3360 if (IN_RANGE (x, 0, 255))
3362 if (SMALL_OPERAND_UNSIGNED (x))
3363 return COSTS_N_INSNS (1);
3368 /* Equality comparisons with 0 are cheap. */
3378 /* Return true if there is a non-MIPS16 instruction that implements CODE
3379 and if that instruction accepts X as an immediate operand. */
3382 mips_immediate_operand_p (int code, HOST_WIDE_INT x)
3389 /* All shift counts are truncated to a valid constant. */
3394 /* Likewise rotates, if the target supports rotates at all. */
3400 /* These instructions take 16-bit unsigned immediates. */
3401 return SMALL_OPERAND_UNSIGNED (x);
3406 /* These instructions take 16-bit signed immediates. */
3407 return SMALL_OPERAND (x);
3413 /* The "immediate" forms of these instructions are really
3414 implemented as comparisons with register 0. */
3419 /* Likewise, meaning that the only valid immediate operand is 1. */
3423 /* We add 1 to the immediate and use SLT. */
3424 return SMALL_OPERAND (x + 1);
3427 /* Likewise SLTU, but reject the always-true case. */
3428 return SMALL_OPERAND (x + 1) && x + 1 != 0;
3432 /* The bit position and size are immediate operands. */
3433 return ISA_HAS_EXT_INS;
3436 /* By default assume that $0 can be used for 0. */
3441 /* Return the cost of binary operation X, given that the instruction
3442 sequence for a word-sized or smaller operation has cost SINGLE_COST
3443 and that the sequence of a double-word operation has cost DOUBLE_COST.
3444 If SPEED is true, optimize for speed otherwise optimize for size. */
3447 mips_binary_cost (rtx x, int single_cost, int double_cost, bool speed)
3451 if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2)
3456 + rtx_cost (XEXP (x, 0), SET, speed)
3457 + rtx_cost (XEXP (x, 1), GET_CODE (x), speed));
3460 /* Return the cost of floating-point multiplications of mode MODE. */
3463 mips_fp_mult_cost (enum machine_mode mode)
3465 return mode == DFmode ? mips_cost->fp_mult_df : mips_cost->fp_mult_sf;
3468 /* Return the cost of floating-point divisions of mode MODE. */
3471 mips_fp_div_cost (enum machine_mode mode)
3473 return mode == DFmode ? mips_cost->fp_div_df : mips_cost->fp_div_sf;
3476 /* Return the cost of sign-extending OP to mode MODE, not including the
3477 cost of OP itself. */
3480 mips_sign_extend_cost (enum machine_mode mode, rtx op)
3483 /* Extended loads are as cheap as unextended ones. */
3486 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3487 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3490 if (ISA_HAS_SEB_SEH || GENERATE_MIPS16E)
3491 /* We can use SEB or SEH. */
3492 return COSTS_N_INSNS (1);
3494 /* We need to use a shift left and a shift right. */
3495 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3498 /* Return the cost of zero-extending OP to mode MODE, not including the
3499 cost of OP itself. */
3502 mips_zero_extend_cost (enum machine_mode mode, rtx op)
3505 /* Extended loads are as cheap as unextended ones. */
3508 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3509 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3510 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3512 if (GENERATE_MIPS16E)
3513 /* We can use ZEB or ZEH. */
3514 return COSTS_N_INSNS (1);
3517 /* We need to load 0xff or 0xffff into a register and use AND. */
3518 return COSTS_N_INSNS (GET_MODE (op) == QImode ? 2 : 3);
3520 /* We can use ANDI. */
3521 return COSTS_N_INSNS (1);
3524 /* Implement TARGET_RTX_COSTS. */
3527 mips_rtx_costs (rtx x, int code, int outer_code, int *total, bool speed)
3529 enum machine_mode mode = GET_MODE (x);
3530 bool float_mode_p = FLOAT_MODE_P (mode);
3534 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3535 appear in the instruction stream, and the cost of a comparison is
3536 really the cost of the branch or scc condition. At the time of
3537 writing, GCC only uses an explicit outer COMPARE code when optabs
3538 is testing whether a constant is expensive enough to force into a
3539 register. We want optabs to pass such constants through the MIPS
3540 expanders instead, so make all constants very cheap here. */
3541 if (outer_code == COMPARE)
3543 gcc_assert (CONSTANT_P (x));
3551 /* Treat *clear_upper32-style ANDs as having zero cost in the
3552 second operand. The cost is entirely in the first operand.
3554 ??? This is needed because we would otherwise try to CSE
3555 the constant operand. Although that's the right thing for
3556 instructions that continue to be a register operation throughout
3557 compilation, it is disastrous for instructions that could
3558 later be converted into a memory operation. */
3560 && outer_code == AND
3561 && UINTVAL (x) == 0xffffffff)
3569 cost = mips16_constant_cost (outer_code, INTVAL (x));
3578 /* When not optimizing for size, we care more about the cost
3579 of hot code, and hot code is often in a loop. If a constant
3580 operand needs to be forced into a register, we will often be
3581 able to hoist the constant load out of the loop, so the load
3582 should not contribute to the cost. */
3583 if (speed || mips_immediate_operand_p (outer_code, INTVAL (x)))
3595 if (force_to_mem_operand (x, VOIDmode))
3597 *total = COSTS_N_INSNS (1);
3600 cost = mips_const_insns (x);
3603 /* If the constant is likely to be stored in a GPR, SETs of
3604 single-insn constants are as cheap as register sets; we
3605 never want to CSE them.
3607 Don't reduce the cost of storing a floating-point zero in
3608 FPRs. If we have a zero in an FPR for other reasons, we
3609 can get better cfg-cleanup and delayed-branch results by
3610 using it consistently, rather than using $0 sometimes and
3611 an FPR at other times. Also, moves between floating-point
3612 registers are sometimes cheaper than (D)MTC1 $0. */
3614 && outer_code == SET
3615 && !(float_mode_p && TARGET_HARD_FLOAT))
3617 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3618 want to CSE the constant itself. It is usually better to
3619 have N copies of the last operation in the sequence and one
3620 shared copy of the other operations. (Note that this is
3621 not true for MIPS16 code, where the final operation in the
3622 sequence is often an extended instruction.)
3624 Also, if we have a CONST_INT, we don't know whether it is
3625 for a word or doubleword operation, so we cannot rely on
3626 the result of mips_build_integer. */
3627 else if (!TARGET_MIPS16
3628 && (outer_code == SET || mode == VOIDmode))
3630 *total = COSTS_N_INSNS (cost);
3633 /* The value will need to be fetched from the constant pool. */
3634 *total = CONSTANT_POOL_COST;
3638 /* If the address is legitimate, return the number of
3639 instructions it needs. */
3641 cost = mips_address_insns (addr, mode, true);
3644 *total = COSTS_N_INSNS (cost + 1);
3647 /* Check for a scaled indexed address. */
3648 if (mips_lwxs_address_p (addr))
3650 *total = COSTS_N_INSNS (2);
3653 /* Otherwise use the default handling. */
3657 *total = COSTS_N_INSNS (6);
3661 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1);
3665 /* Check for a *clear_upper32 pattern and treat it like a zero
3666 extension. See the pattern's comment for details. */
3669 && CONST_INT_P (XEXP (x, 1))
3670 && UINTVAL (XEXP (x, 1)) == 0xffffffff)
3672 *total = (mips_zero_extend_cost (mode, XEXP (x, 0))
3673 + rtx_cost (XEXP (x, 0), SET, speed));
3680 /* Double-word operations use two single-word operations. */
3681 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (2),
3690 if (CONSTANT_P (XEXP (x, 1)))
3691 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3694 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (12),
3700 *total = mips_cost->fp_add;
3702 *total = COSTS_N_INSNS (4);
3706 /* Low-part immediates need an extended MIPS16 instruction. */
3707 *total = (COSTS_N_INSNS (TARGET_MIPS16 ? 2 : 1)
3708 + rtx_cost (XEXP (x, 0), SET, speed));
3723 /* Branch comparisons have VOIDmode, so use the first operand's
3725 mode = GET_MODE (XEXP (x, 0));
3726 if (FLOAT_MODE_P (mode))
3728 *total = mips_cost->fp_add;
3731 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3737 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3738 && TARGET_FUSED_MADD
3739 && !HONOR_NANS (mode)
3740 && !HONOR_SIGNED_ZEROS (mode))
3742 /* See if we can use NMADD or NMSUB. See mips.md for the
3743 associated patterns. */
3744 rtx op0 = XEXP (x, 0);
3745 rtx op1 = XEXP (x, 1);
3746 if (GET_CODE (op0) == MULT && GET_CODE (XEXP (op0, 0)) == NEG)
3748 *total = (mips_fp_mult_cost (mode)
3749 + rtx_cost (XEXP (XEXP (op0, 0), 0), SET, speed)
3750 + rtx_cost (XEXP (op0, 1), SET, speed)
3751 + rtx_cost (op1, SET, speed));
3754 if (GET_CODE (op1) == MULT)
3756 *total = (mips_fp_mult_cost (mode)
3757 + rtx_cost (op0, SET, speed)
3758 + rtx_cost (XEXP (op1, 0), SET, speed)
3759 + rtx_cost (XEXP (op1, 1), SET, speed));
3768 /* If this is part of a MADD or MSUB, treat the PLUS as
3771 && TARGET_FUSED_MADD
3772 && GET_CODE (XEXP (x, 0)) == MULT)
3775 *total = mips_cost->fp_add;
3779 /* Double-word operations require three single-word operations and
3780 an SLTU. The MIPS16 version then needs to move the result of
3781 the SLTU from $24 to a MIPS16 register. */
3782 *total = mips_binary_cost (x, COSTS_N_INSNS (1),
3783 COSTS_N_INSNS (TARGET_MIPS16 ? 5 : 4),
3789 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3790 && TARGET_FUSED_MADD
3791 && !HONOR_NANS (mode)
3792 && HONOR_SIGNED_ZEROS (mode))
3794 /* See if we can use NMADD or NMSUB. See mips.md for the
3795 associated patterns. */
3796 rtx op = XEXP (x, 0);
3797 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
3798 && GET_CODE (XEXP (op, 0)) == MULT)
3800 *total = (mips_fp_mult_cost (mode)
3801 + rtx_cost (XEXP (XEXP (op, 0), 0), SET, speed)
3802 + rtx_cost (XEXP (XEXP (op, 0), 1), SET, speed)
3803 + rtx_cost (XEXP (op, 1), SET, speed));
3809 *total = mips_cost->fp_add;
3811 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1);
3816 *total = mips_fp_mult_cost (mode);
3817 else if (mode == DImode && !TARGET_64BIT)
3818 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
3819 where the mulsidi3 always includes an MFHI and an MFLO. */
3821 ? mips_cost->int_mult_si * 3 + 6
3822 : COSTS_N_INSNS (ISA_HAS_MUL3 ? 7 : 9));
3824 *total = (ISA_HAS_MUL3 ? 1 : 2);
3825 else if (mode == DImode)
3826 *total = mips_cost->int_mult_di;
3828 *total = mips_cost->int_mult_si;
3832 /* Check for a reciprocal. */
3835 && flag_unsafe_math_optimizations
3836 && XEXP (x, 0) == CONST1_RTX (mode))
3838 if (outer_code == SQRT || GET_CODE (XEXP (x, 1)) == SQRT)
3839 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
3840 division as being free. */
3841 *total = rtx_cost (XEXP (x, 1), SET, speed);
3843 *total = (mips_fp_div_cost (mode)
3844 + rtx_cost (XEXP (x, 1), SET, speed));
3853 *total = mips_fp_div_cost (mode);
3862 /* It is our responsibility to make division by a power of 2
3863 as cheap as 2 register additions if we want the division
3864 expanders to be used for such operations; see the setting
3865 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
3866 should always produce shorter code than using
3867 expand_sdiv2_pow2. */
3869 && CONST_INT_P (XEXP (x, 1))
3870 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
3872 *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), SET, speed);
3875 *total = COSTS_N_INSNS (mips_idiv_insns ());
3877 else if (mode == DImode)
3878 *total = mips_cost->int_div_di;
3880 *total = mips_cost->int_div_si;
3884 *total = mips_sign_extend_cost (mode, XEXP (x, 0));
3888 *total = mips_zero_extend_cost (mode, XEXP (x, 0));
3892 case UNSIGNED_FLOAT:
3895 case FLOAT_TRUNCATE:
3896 *total = mips_cost->fp_add;
3904 /* Implement TARGET_ADDRESS_COST. */
3907 mips_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED)
3909 return mips_address_insns (addr, SImode, false);
3912 /* Information about a single instruction in a multi-instruction
3914 struct mips_multi_member {
3915 /* True if this is a label, false if it is code. */
3918 /* The output_asm_insn format of the instruction. */
3921 /* The operands to the instruction. */
3922 rtx operands[MAX_RECOG_OPERANDS];
3924 typedef struct mips_multi_member mips_multi_member;
3926 /* Vector definitions for the above. */
3927 DEF_VEC_O(mips_multi_member);
3928 DEF_VEC_ALLOC_O(mips_multi_member, heap);
3930 /* The instructions that make up the current multi-insn sequence. */
3931 static VEC (mips_multi_member, heap) *mips_multi_members;
3933 /* How many instructions (as opposed to labels) are in the current
3934 multi-insn sequence. */
3935 static unsigned int mips_multi_num_insns;
3937 /* Start a new multi-insn sequence. */
3940 mips_multi_start (void)
3942 VEC_truncate (mips_multi_member, mips_multi_members, 0);
3943 mips_multi_num_insns = 0;
3946 /* Add a new, uninitialized member to the current multi-insn sequence. */
3948 static struct mips_multi_member *
3949 mips_multi_add (void)
3951 return VEC_safe_push (mips_multi_member, heap, mips_multi_members, 0);
3954 /* Add a normal insn with the given asm format to the current multi-insn
3955 sequence. The other arguments are a null-terminated list of operands. */
3958 mips_multi_add_insn (const char *format, ...)
3960 struct mips_multi_member *member;
3965 member = mips_multi_add ();
3966 member->is_label_p = false;
3967 member->format = format;
3968 va_start (ap, format);
3970 while ((op = va_arg (ap, rtx)))
3971 member->operands[i++] = op;
3973 mips_multi_num_insns++;
3976 /* Add the given label definition to the current multi-insn sequence.
3977 The definition should include the colon. */
3980 mips_multi_add_label (const char *label)
3982 struct mips_multi_member *member;
3984 member = mips_multi_add ();
3985 member->is_label_p = true;
3986 member->format = label;
3989 /* Return the index of the last member of the current multi-insn sequence. */
3992 mips_multi_last_index (void)
3994 return VEC_length (mips_multi_member, mips_multi_members) - 1;
3997 /* Add a copy of an existing instruction to the current multi-insn
3998 sequence. I is the index of the instruction that should be copied. */
4001 mips_multi_copy_insn (unsigned int i)
4003 struct mips_multi_member *member;
4005 member = mips_multi_add ();
4006 memcpy (member, VEC_index (mips_multi_member, mips_multi_members, i),
4008 gcc_assert (!member->is_label_p);
4011 /* Change the operand of an existing instruction in the current
4012 multi-insn sequence. I is the index of the instruction,
4013 OP is the index of the operand, and X is the new value. */
4016 mips_multi_set_operand (unsigned int i, unsigned int op, rtx x)
4018 VEC_index (mips_multi_member, mips_multi_members, i)->operands[op] = x;
4021 /* Write out the asm code for the current multi-insn sequence. */
4024 mips_multi_write (void)
4026 struct mips_multi_member *member;
4029 FOR_EACH_VEC_ELT (mips_multi_member, mips_multi_members, i, member)
4030 if (member->is_label_p)
4031 fprintf (asm_out_file, "%s\n", member->format);
4033 output_asm_insn (member->format, member->operands);
4036 /* Return one word of double-word value OP, taking into account the fixed
4037 endianness of certain registers. HIGH_P is true to select the high part,
4038 false to select the low part. */
4041 mips_subword (rtx op, bool high_p)
4043 unsigned int byte, offset;
4044 enum machine_mode mode;
4046 mode = GET_MODE (op);
4047 if (mode == VOIDmode)
4048 mode = TARGET_64BIT ? TImode : DImode;
4050 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
4051 byte = UNITS_PER_WORD;
4055 if (FP_REG_RTX_P (op))
4057 /* Paired FPRs are always ordered little-endian. */
4058 offset = (UNITS_PER_WORD < UNITS_PER_HWFPVALUE ? high_p : byte != 0);
4059 return gen_rtx_REG (word_mode, REGNO (op) + offset);
4063 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
4065 return simplify_gen_subreg (word_mode, op, mode, byte);
4068 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
4071 mips_split_64bit_move_p (rtx dest, rtx src)
4076 /* FPR-to-FPR moves can be done in a single instruction, if they're
4078 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
4081 /* Check for floating-point loads and stores. */
4082 if (ISA_HAS_LDC1_SDC1)
4084 if (FP_REG_RTX_P (dest) && MEM_P (src))
4086 if (FP_REG_RTX_P (src) && MEM_P (dest))
4092 /* Split a doubleword move from SRC to DEST. On 32-bit targets,
4093 this function handles 64-bit moves for which mips_split_64bit_move_p
4094 holds. For 64-bit targets, this function handles 128-bit moves. */
4097 mips_split_doubleword_move (rtx dest, rtx src)
4101 if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src))
4103 if (!TARGET_64BIT && GET_MODE (dest) == DImode)
4104 emit_insn (gen_move_doubleword_fprdi (dest, src));
4105 else if (!TARGET_64BIT && GET_MODE (dest) == DFmode)
4106 emit_insn (gen_move_doubleword_fprdf (dest, src));
4107 else if (!TARGET_64BIT && GET_MODE (dest) == V2SFmode)
4108 emit_insn (gen_move_doubleword_fprv2sf (dest, src));
4109 else if (!TARGET_64BIT && GET_MODE (dest) == V2SImode)
4110 emit_insn (gen_move_doubleword_fprv2si (dest, src));
4111 else if (!TARGET_64BIT && GET_MODE (dest) == V4HImode)
4112 emit_insn (gen_move_doubleword_fprv4hi (dest, src));
4113 else if (!TARGET_64BIT && GET_MODE (dest) == V8QImode)
4114 emit_insn (gen_move_doubleword_fprv8qi (dest, src));
4115 else if (TARGET_64BIT && GET_MODE (dest) == TFmode)
4116 emit_insn (gen_move_doubleword_fprtf (dest, src));
4120 else if (REG_P (dest) && REGNO (dest) == MD_REG_FIRST)
4122 low_dest = mips_subword (dest, false);
4123 mips_emit_move (low_dest, mips_subword (src, false));
4125 emit_insn (gen_mthidi_ti (dest, mips_subword (src, true), low_dest));
4127 emit_insn (gen_mthisi_di (dest, mips_subword (src, true), low_dest));
4129 else if (REG_P (src) && REGNO (src) == MD_REG_FIRST)
4131 mips_emit_move (mips_subword (dest, false), mips_subword (src, false));
4133 emit_insn (gen_mfhidi_ti (mips_subword (dest, true), src));
4135 emit_insn (gen_mfhisi_di (mips_subword (dest, true), src));
4139 /* The operation can be split into two normal moves. Decide in
4140 which order to do them. */
4141 low_dest = mips_subword (dest, false);
4142 if (REG_P (low_dest)
4143 && reg_overlap_mentioned_p (low_dest, src))
4145 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4146 mips_emit_move (low_dest, mips_subword (src, false));
4150 mips_emit_move (low_dest, mips_subword (src, false));
4151 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4156 /* Return the appropriate instructions to move SRC into DEST. Assume
4157 that SRC is operand 1 and DEST is operand 0. */
4160 mips_output_move (rtx dest, rtx src)
4162 enum rtx_code dest_code, src_code;
4163 enum machine_mode mode;
4164 enum mips_symbol_type symbol_type;
4167 dest_code = GET_CODE (dest);
4168 src_code = GET_CODE (src);
4169 mode = GET_MODE (dest);
4170 dbl_p = (GET_MODE_SIZE (mode) == 8);
4172 if (dbl_p && mips_split_64bit_move_p (dest, src))
4175 if ((src_code == REG && GP_REG_P (REGNO (src)))
4176 || (!TARGET_MIPS16 && src == CONST0_RTX (mode)))
4178 if (dest_code == REG)
4180 if (GP_REG_P (REGNO (dest)))
4181 return "move\t%0,%z1";
4183 /* Moves to HI are handled by special .md insns. */
4184 if (REGNO (dest) == LO_REGNUM)
4187 if (DSP_ACC_REG_P (REGNO (dest)))
4189 static char retval[] = "mt__\t%z1,%q0";
4191 retval[2] = reg_names[REGNO (dest)][4];
4192 retval[3] = reg_names[REGNO (dest)][5];
4196 if (FP_REG_P (REGNO (dest)))
4197 return dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
4199 if (ALL_COP_REG_P (REGNO (dest)))
4201 static char retval[] = "dmtc_\t%z1,%0";
4203 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4204 return dbl_p ? retval : retval + 1;
4207 if (dest_code == MEM)
4208 switch (GET_MODE_SIZE (mode))
4210 case 1: return "sb\t%z1,%0";
4211 case 2: return "sh\t%z1,%0";
4212 case 4: return "sw\t%z1,%0";
4213 case 8: return "sd\t%z1,%0";
4216 if (dest_code == REG && GP_REG_P (REGNO (dest)))
4218 if (src_code == REG)
4220 /* Moves from HI are handled by special .md insns. */
4221 if (REGNO (src) == LO_REGNUM)
4223 /* When generating VR4120 or VR4130 code, we use MACC and
4224 DMACC instead of MFLO. This avoids both the normal
4225 MIPS III HI/LO hazards and the errata related to
4228 return dbl_p ? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
4232 if (DSP_ACC_REG_P (REGNO (src)))
4234 static char retval[] = "mf__\t%0,%q1";
4236 retval[2] = reg_names[REGNO (src)][4];
4237 retval[3] = reg_names[REGNO (src)][5];
4241 if (FP_REG_P (REGNO (src)))
4242 return dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
4244 if (ALL_COP_REG_P (REGNO (src)))
4246 static char retval[] = "dmfc_\t%0,%1";
4248 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4249 return dbl_p ? retval : retval + 1;
4252 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
4253 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
4256 if (src_code == MEM)
4257 switch (GET_MODE_SIZE (mode))
4259 case 1: return "lbu\t%0,%1";
4260 case 2: return "lhu\t%0,%1";
4261 case 4: return "lw\t%0,%1";
4262 case 8: return "ld\t%0,%1";
4265 if (src_code == CONST_INT)
4267 /* Don't use the X format for the operand itself, because that
4268 will give out-of-range numbers for 64-bit hosts and 32-bit
4271 return "li\t%0,%1\t\t\t# %X1";
4273 if (SMALL_OPERAND_UNSIGNED (INTVAL (src)))
4276 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src)))
4280 if (src_code == HIGH)
4281 return TARGET_MIPS16 ? "#" : "lui\t%0,%h1";
4283 if (CONST_GP_P (src))
4284 return "move\t%0,%1";
4286 if (mips_symbolic_constant_p (src, SYMBOL_CONTEXT_LEA, &symbol_type)
4287 && mips_lo_relocs[symbol_type] != 0)
4289 /* A signed 16-bit constant formed by applying a relocation
4290 operator to a symbolic address. */
4291 gcc_assert (!mips_split_p[symbol_type]);
4292 return "li\t%0,%R1";
4295 if (symbolic_operand (src, VOIDmode))
4297 gcc_assert (TARGET_MIPS16
4298 ? TARGET_MIPS16_TEXT_LOADS
4299 : !TARGET_EXPLICIT_RELOCS);
4300 return dbl_p ? "dla\t%0,%1" : "la\t%0,%1";
4303 if (src_code == REG && FP_REG_P (REGNO (src)))
4305 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4307 if (GET_MODE (dest) == V2SFmode)
4308 return "mov.ps\t%0,%1";
4310 return dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1";
4313 if (dest_code == MEM)
4314 return dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0";
4316 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4318 if (src_code == MEM)
4319 return dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1";
4321 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
4323 static char retval[] = "l_c_\t%0,%1";
4325 retval[1] = (dbl_p ? 'd' : 'w');
4326 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4329 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
4331 static char retval[] = "s_c_\t%1,%0";
4333 retval[1] = (dbl_p ? 'd' : 'w');
4334 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4340 /* Return true if CMP1 is a suitable second operand for integer ordering
4341 test CODE. See also the *sCC patterns in mips.md. */
4344 mips_int_order_operand_ok_p (enum rtx_code code, rtx cmp1)
4350 return reg_or_0_operand (cmp1, VOIDmode);
4354 return !TARGET_MIPS16 && cmp1 == const1_rtx;
4358 return arith_operand (cmp1, VOIDmode);
4361 return sle_operand (cmp1, VOIDmode);
4364 return sleu_operand (cmp1, VOIDmode);
4371 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4372 integer ordering test *CODE, or if an equivalent combination can
4373 be formed by adjusting *CODE and *CMP1. When returning true, update
4374 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4378 mips_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1,
4379 enum machine_mode mode)
4381 HOST_WIDE_INT plus_one;
4383 if (mips_int_order_operand_ok_p (*code, *cmp1))
4386 if (CONST_INT_P (*cmp1))
4390 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4391 if (INTVAL (*cmp1) < plus_one)
4394 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4400 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4404 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4415 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4416 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4417 is nonnull, it's OK to set TARGET to the inverse of the result and
4418 flip *INVERT_PTR instead. */
4421 mips_emit_int_order_test (enum rtx_code code, bool *invert_ptr,
4422 rtx target, rtx cmp0, rtx cmp1)
4424 enum machine_mode mode;
4426 /* First see if there is a MIPS instruction that can do this operation.
4427 If not, try doing the same for the inverse operation. If that also
4428 fails, force CMP1 into a register and try again. */
4429 mode = GET_MODE (cmp0);
4430 if (mips_canonicalize_int_order_test (&code, &cmp1, mode))
4431 mips_emit_binary (code, target, cmp0, cmp1);
4434 enum rtx_code inv_code = reverse_condition (code);
4435 if (!mips_canonicalize_int_order_test (&inv_code, &cmp1, mode))
4437 cmp1 = force_reg (mode, cmp1);
4438 mips_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1);
4440 else if (invert_ptr == 0)
4444 inv_target = mips_force_binary (GET_MODE (target),
4445 inv_code, cmp0, cmp1);
4446 mips_emit_binary (XOR, target, inv_target, const1_rtx);
4450 *invert_ptr = !*invert_ptr;
4451 mips_emit_binary (inv_code, target, cmp0, cmp1);
4456 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4457 The register will have the same mode as CMP0. */
4460 mips_zero_if_equal (rtx cmp0, rtx cmp1)
4462 if (cmp1 == const0_rtx)
4465 if (uns_arith_operand (cmp1, VOIDmode))
4466 return expand_binop (GET_MODE (cmp0), xor_optab,
4467 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4469 return expand_binop (GET_MODE (cmp0), sub_optab,
4470 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4473 /* Convert *CODE into a code that can be used in a floating-point
4474 scc instruction (C.cond.fmt). Return true if the values of
4475 the condition code registers will be inverted, with 0 indicating
4476 that the condition holds. */
4479 mips_reversed_fp_cond (enum rtx_code *code)
4486 *code = reverse_condition_maybe_unordered (*code);
4494 /* Convert a comparison into something that can be used in a branch or
4495 conditional move. On entry, *OP0 and *OP1 are the values being
4496 compared and *CODE is the code used to compare them.
4498 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
4499 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
4500 otherwise any standard branch condition can be used. The standard branch
4503 - EQ or NE between two registers.
4504 - any comparison between a register and zero. */
4507 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
4512 if (GET_MODE_CLASS (GET_MODE (*op0)) == MODE_INT)
4514 if (!need_eq_ne_p && *op1 == const0_rtx)
4516 else if (*code == EQ || *code == NE)
4520 *op0 = mips_zero_if_equal (cmp_op0, cmp_op1);
4524 *op1 = force_reg (GET_MODE (cmp_op0), cmp_op1);
4528 /* The comparison needs a separate scc instruction. Store the
4529 result of the scc in *OP0 and compare it against zero. */
4530 bool invert = false;
4531 *op0 = gen_reg_rtx (GET_MODE (cmp_op0));
4532 mips_emit_int_order_test (*code, &invert, *op0, cmp_op0, cmp_op1);
4533 *code = (invert ? EQ : NE);
4537 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0)))
4539 *op0 = gen_rtx_REG (CCDSPmode, CCDSP_CC_REGNUM);
4540 mips_emit_binary (*code, *op0, cmp_op0, cmp_op1);
4546 enum rtx_code cmp_code;
4548 /* Floating-point tests use a separate C.cond.fmt comparison to
4549 set a condition code register. The branch or conditional move
4550 will then compare that register against zero.
4552 Set CMP_CODE to the code of the comparison instruction and
4553 *CODE to the code that the branch or move should use. */
4555 *code = mips_reversed_fp_cond (&cmp_code) ? EQ : NE;
4557 ? gen_reg_rtx (CCmode)
4558 : gen_rtx_REG (CCmode, FPSW_REGNUM));
4560 mips_emit_binary (cmp_code, *op0, cmp_op0, cmp_op1);
4564 /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2]
4565 and OPERAND[3]. Store the result in OPERANDS[0].
4567 On 64-bit targets, the mode of the comparison and target will always be
4568 SImode, thus possibly narrower than that of the comparison's operands. */
4571 mips_expand_scc (rtx operands[])
4573 rtx target = operands[0];
4574 enum rtx_code code = GET_CODE (operands[1]);
4575 rtx op0 = operands[2];
4576 rtx op1 = operands[3];
4578 gcc_assert (GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT);
4580 if (code == EQ || code == NE)
4583 && reg_imm10_operand (op1, GET_MODE (op1)))
4584 mips_emit_binary (code, target, op0, op1);
4587 rtx zie = mips_zero_if_equal (op0, op1);
4588 mips_emit_binary (code, target, zie, const0_rtx);
4592 mips_emit_int_order_test (code, 0, target, op0, op1);
4595 /* Compare OPERANDS[1] with OPERANDS[2] using comparison code
4596 CODE and jump to OPERANDS[3] if the condition holds. */
4599 mips_expand_conditional_branch (rtx *operands)
4601 enum rtx_code code = GET_CODE (operands[0]);
4602 rtx op0 = operands[1];
4603 rtx op1 = operands[2];
4606 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
4607 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
4608 emit_jump_insn (gen_condjump (condition, operands[3]));
4613 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
4614 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
4617 mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
4618 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
4623 reversed_p = mips_reversed_fp_cond (&cond);
4624 cmp_result = gen_reg_rtx (CCV2mode);
4625 emit_insn (gen_scc_ps (cmp_result,
4626 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
4628 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
4631 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
4635 /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0]
4636 if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
4639 mips_expand_conditional_move (rtx *operands)
4642 enum rtx_code code = GET_CODE (operands[1]);
4643 rtx op0 = XEXP (operands[1], 0);
4644 rtx op1 = XEXP (operands[1], 1);
4646 mips_emit_compare (&code, &op0, &op1, true);
4647 cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
4648 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
4649 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), cond,
4650 operands[2], operands[3])));
4653 /* Perform the comparison in COMPARISON, then trap if the condition holds. */
4656 mips_expand_conditional_trap (rtx comparison)
4659 enum machine_mode mode;
4662 /* MIPS conditional trap instructions don't have GT or LE flavors,
4663 so we must swap the operands and convert to LT and GE respectively. */
4664 code = GET_CODE (comparison);
4671 code = swap_condition (code);
4672 op0 = XEXP (comparison, 1);
4673 op1 = XEXP (comparison, 0);
4677 op0 = XEXP (comparison, 0);
4678 op1 = XEXP (comparison, 1);
4682 mode = GET_MODE (XEXP (comparison, 0));
4683 op0 = force_reg (mode, op0);
4684 if (!arith_operand (op1, mode))
4685 op1 = force_reg (mode, op1);
4687 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
4688 gen_rtx_fmt_ee (code, mode, op0, op1),
4692 /* Initialize *CUM for a call to a function of type FNTYPE. */
4695 mips_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype)
4697 memset (cum, 0, sizeof (*cum));
4698 cum->prototype = (fntype && prototype_p (fntype));
4699 cum->gp_reg_found = (cum->prototype && stdarg_p (fntype));
4702 /* Fill INFO with information about a single argument. CUM is the
4703 cumulative state for earlier arguments. MODE is the mode of this
4704 argument and TYPE is its type (if known). NAMED is true if this
4705 is a named (fixed) argument rather than a variable one. */
4708 mips_get_arg_info (struct mips_arg_info *info, const CUMULATIVE_ARGS *cum,
4709 enum machine_mode mode, const_tree type, bool named)
4711 bool doubleword_aligned_p;
4712 unsigned int num_bytes, num_words, max_regs;
4714 /* Work out the size of the argument. */
4715 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
4716 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4718 /* Decide whether it should go in a floating-point register, assuming
4719 one is free. Later code checks for availability.
4721 The checks against UNITS_PER_FPVALUE handle the soft-float and
4722 single-float cases. */
4726 /* The EABI conventions have traditionally been defined in terms
4727 of TYPE_MODE, regardless of the actual type. */
4728 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
4729 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4730 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4735 /* Only leading floating-point scalars are passed in
4736 floating-point registers. We also handle vector floats the same
4737 say, which is OK because they are not covered by the standard ABI. */
4738 info->fpr_p = (!cum->gp_reg_found
4739 && cum->arg_number < 2
4741 || SCALAR_FLOAT_TYPE_P (type)
4742 || VECTOR_FLOAT_TYPE_P (type))
4743 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4744 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4745 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4750 /* Scalar, complex and vector floating-point types are passed in
4751 floating-point registers, as long as this is a named rather
4752 than a variable argument. */
4753 info->fpr_p = (named
4754 && (type == 0 || FLOAT_TYPE_P (type))
4755 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4756 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4757 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4758 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
4760 /* ??? According to the ABI documentation, the real and imaginary
4761 parts of complex floats should be passed in individual registers.
4762 The real and imaginary parts of stack arguments are supposed
4763 to be contiguous and there should be an extra word of padding
4766 This has two problems. First, it makes it impossible to use a
4767 single "void *" va_list type, since register and stack arguments
4768 are passed differently. (At the time of writing, MIPSpro cannot
4769 handle complex float varargs correctly.) Second, it's unclear
4770 what should happen when there is only one register free.
4772 For now, we assume that named complex floats should go into FPRs
4773 if there are two FPRs free, otherwise they should be passed in the
4774 same way as a struct containing two floats. */
4776 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4777 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
4779 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
4780 info->fpr_p = false;
4790 /* See whether the argument has doubleword alignment. */
4791 doubleword_aligned_p = (mips_function_arg_boundary (mode, type)
4794 /* Set REG_OFFSET to the register count we're interested in.
4795 The EABI allocates the floating-point registers separately,
4796 but the other ABIs allocate them like integer registers. */
4797 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
4801 /* Advance to an even register if the argument is doubleword-aligned. */
4802 if (doubleword_aligned_p)
4803 info->reg_offset += info->reg_offset & 1;
4805 /* Work out the offset of a stack argument. */
4806 info->stack_offset = cum->stack_words;
4807 if (doubleword_aligned_p)
4808 info->stack_offset += info->stack_offset & 1;
4810 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
4812 /* Partition the argument between registers and stack. */
4813 info->reg_words = MIN (num_words, max_regs);
4814 info->stack_words = num_words - info->reg_words;
4817 /* INFO describes a register argument that has the normal format for the
4818 argument's mode. Return the register it uses, assuming that FPRs are
4819 available if HARD_FLOAT_P. */
4822 mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p)
4824 if (!info->fpr_p || !hard_float_p)
4825 return GP_ARG_FIRST + info->reg_offset;
4826 else if (mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info->reg_offset > 0)
4827 /* In o32, the second argument is always passed in $f14
4828 for TARGET_DOUBLE_FLOAT, regardless of whether the
4829 first argument was a word or doubleword. */
4830 return FP_ARG_FIRST + 2;
4832 return FP_ARG_FIRST + info->reg_offset;
4835 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
4838 mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
4840 return !TARGET_OLDABI;
4843 /* Implement TARGET_FUNCTION_ARG. */
4846 mips_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4847 const_tree type, bool named)
4849 struct mips_arg_info info;
4851 /* We will be called with a mode of VOIDmode after the last argument
4852 has been seen. Whatever we return will be passed to the call expander.
4853 If we need a MIPS16 fp_code, return a REG with the code stored as
4855 if (mode == VOIDmode)
4857 if (TARGET_MIPS16 && cum->fp_code != 0)
4858 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
4863 mips_get_arg_info (&info, cum, mode, type, named);
4865 /* Return straight away if the whole argument is passed on the stack. */
4866 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
4869 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
4870 contains a double in its entirety, then that 64-bit chunk is passed
4871 in a floating-point register. */
4873 && TARGET_HARD_FLOAT
4876 && TREE_CODE (type) == RECORD_TYPE
4877 && TYPE_SIZE_UNIT (type)
4878 && host_integerp (TYPE_SIZE_UNIT (type), 1))
4882 /* First check to see if there is any such field. */
4883 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
4884 if (TREE_CODE (field) == FIELD_DECL
4885 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
4886 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
4887 && host_integerp (bit_position (field), 0)
4888 && int_bit_position (field) % BITS_PER_WORD == 0)
4893 /* Now handle the special case by returning a PARALLEL
4894 indicating where each 64-bit chunk goes. INFO.REG_WORDS
4895 chunks are passed in registers. */
4897 HOST_WIDE_INT bitpos;
4900 /* assign_parms checks the mode of ENTRY_PARM, so we must
4901 use the actual mode here. */
4902 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
4905 field = TYPE_FIELDS (type);
4906 for (i = 0; i < info.reg_words; i++)
4910 for (; field; field = DECL_CHAIN (field))
4911 if (TREE_CODE (field) == FIELD_DECL
4912 && int_bit_position (field) >= bitpos)
4916 && int_bit_position (field) == bitpos
4917 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
4918 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
4919 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
4921 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
4924 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4925 GEN_INT (bitpos / BITS_PER_UNIT));
4927 bitpos += BITS_PER_WORD;
4933 /* Handle the n32/n64 conventions for passing complex floating-point
4934 arguments in FPR pairs. The real part goes in the lower register
4935 and the imaginary part goes in the upper register. */
4938 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4941 enum machine_mode inner;
4944 inner = GET_MODE_INNER (mode);
4945 regno = FP_ARG_FIRST + info.reg_offset;
4946 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
4948 /* Real part in registers, imaginary part on stack. */
4949 gcc_assert (info.stack_words == info.reg_words);
4950 return gen_rtx_REG (inner, regno);
4954 gcc_assert (info.stack_words == 0);
4955 real = gen_rtx_EXPR_LIST (VOIDmode,
4956 gen_rtx_REG (inner, regno),
4958 imag = gen_rtx_EXPR_LIST (VOIDmode,
4960 regno + info.reg_words / 2),
4961 GEN_INT (GET_MODE_SIZE (inner)));
4962 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
4966 return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT));
4969 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
4972 mips_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4973 const_tree type, bool named)
4975 struct mips_arg_info info;
4977 mips_get_arg_info (&info, cum, mode, type, named);
4980 cum->gp_reg_found = true;
4982 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
4983 an explanation of what this code does. It assumes that we're using
4984 either the o32 or the o64 ABI, both of which pass at most 2 arguments
4986 if (cum->arg_number < 2 && info.fpr_p)
4987 cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2);
4989 /* Advance the register count. This has the effect of setting
4990 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
4991 argument required us to skip the final GPR and pass the whole
4992 argument on the stack. */
4993 if (mips_abi != ABI_EABI || !info.fpr_p)
4994 cum->num_gprs = info.reg_offset + info.reg_words;
4995 else if (info.reg_words > 0)
4996 cum->num_fprs += MAX_FPRS_PER_FMT;
4998 /* Advance the stack word count. */
4999 if (info.stack_words > 0)
5000 cum->stack_words = info.stack_offset + info.stack_words;
5005 /* Implement TARGET_ARG_PARTIAL_BYTES. */
5008 mips_arg_partial_bytes (CUMULATIVE_ARGS *cum,
5009 enum machine_mode mode, tree type, bool named)
5011 struct mips_arg_info info;
5013 mips_get_arg_info (&info, cum, mode, type, named);
5014 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
5017 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
5018 least PARM_BOUNDARY bits of alignment, but will be given anything up
5019 to STACK_BOUNDARY bits if the type requires it. */
5022 mips_function_arg_boundary (enum machine_mode mode, const_tree type)
5024 unsigned int alignment;
5026 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
5027 if (alignment < PARM_BOUNDARY)
5028 alignment = PARM_BOUNDARY;
5029 if (alignment > STACK_BOUNDARY)
5030 alignment = STACK_BOUNDARY;
5034 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
5035 upward rather than downward. In other words, return true if the
5036 first byte of the stack slot has useful data, false if the last
5040 mips_pad_arg_upward (enum machine_mode mode, const_tree type)
5042 /* On little-endian targets, the first byte of every stack argument
5043 is passed in the first byte of the stack slot. */
5044 if (!BYTES_BIG_ENDIAN)
5047 /* Otherwise, integral types are padded downward: the last byte of a
5048 stack argument is passed in the last byte of the stack slot. */
5050 ? (INTEGRAL_TYPE_P (type)
5051 || POINTER_TYPE_P (type)
5052 || FIXED_POINT_TYPE_P (type))
5053 : (SCALAR_INT_MODE_P (mode)
5054 || ALL_SCALAR_FIXED_POINT_MODE_P (mode)))
5057 /* Big-endian o64 pads floating-point arguments downward. */
5058 if (mips_abi == ABI_O64)
5059 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
5062 /* Other types are padded upward for o32, o64, n32 and n64. */
5063 if (mips_abi != ABI_EABI)
5066 /* Arguments smaller than a stack slot are padded downward. */
5067 if (mode != BLKmode)
5068 return GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY;
5070 return int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT);
5073 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
5074 if the least significant byte of the register has useful data. Return
5075 the opposite if the most significant byte does. */
5078 mips_pad_reg_upward (enum machine_mode mode, tree type)
5080 /* No shifting is required for floating-point arguments. */
5081 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
5082 return !BYTES_BIG_ENDIAN;
5084 /* Otherwise, apply the same padding to register arguments as we do
5085 to stack arguments. */
5086 return mips_pad_arg_upward (mode, type);
5089 /* Return nonzero when an argument must be passed by reference. */
5092 mips_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5093 enum machine_mode mode, const_tree type,
5094 bool named ATTRIBUTE_UNUSED)
5096 if (mips_abi == ABI_EABI)
5100 /* ??? How should SCmode be handled? */
5101 if (mode == DImode || mode == DFmode
5102 || mode == DQmode || mode == UDQmode
5103 || mode == DAmode || mode == UDAmode)
5106 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
5107 return size == -1 || size > UNITS_PER_WORD;
5111 /* If we have a variable-sized parameter, we have no choice. */
5112 return targetm.calls.must_pass_in_stack (mode, type);
5116 /* Implement TARGET_CALLEE_COPIES. */
5119 mips_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5120 enum machine_mode mode ATTRIBUTE_UNUSED,
5121 const_tree type ATTRIBUTE_UNUSED, bool named)
5123 return mips_abi == ABI_EABI && named;
5126 /* See whether VALTYPE is a record whose fields should be returned in
5127 floating-point registers. If so, return the number of fields and
5128 list them in FIELDS (which should have two elements). Return 0
5131 For n32 & n64, a structure with one or two fields is returned in
5132 floating-point registers as long as every field has a floating-point
5136 mips_fpr_return_fields (const_tree valtype, tree *fields)
5144 if (TREE_CODE (valtype) != RECORD_TYPE)
5148 for (field = TYPE_FIELDS (valtype); field != 0; field = DECL_CHAIN (field))
5150 if (TREE_CODE (field) != FIELD_DECL)
5153 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)))
5159 fields[i++] = field;
5164 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
5165 a value in the most significant part of $2/$3 if:
5167 - the target is big-endian;
5169 - the value has a structure or union type (we generalize this to
5170 cover aggregates from other languages too); and
5172 - the structure is not returned in floating-point registers. */
5175 mips_return_in_msb (const_tree valtype)
5179 return (TARGET_NEWABI
5180 && TARGET_BIG_ENDIAN
5181 && AGGREGATE_TYPE_P (valtype)
5182 && mips_fpr_return_fields (valtype, fields) == 0);
5185 /* Return true if the function return value MODE will get returned in a
5186 floating-point register. */
5189 mips_return_mode_in_fpr_p (enum machine_mode mode)
5191 return ((GET_MODE_CLASS (mode) == MODE_FLOAT
5192 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT
5193 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5194 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE);
5197 /* Return the representation of an FPR return register when the
5198 value being returned in FP_RETURN has mode VALUE_MODE and the
5199 return type itself has mode TYPE_MODE. On NewABI targets,
5200 the two modes may be different for structures like:
5202 struct __attribute__((packed)) foo { float f; }
5204 where we return the SFmode value of "f" in FP_RETURN, but where
5205 the structure itself has mode BLKmode. */
5208 mips_return_fpr_single (enum machine_mode type_mode,
5209 enum machine_mode value_mode)
5213 x = gen_rtx_REG (value_mode, FP_RETURN);
5214 if (type_mode != value_mode)
5216 x = gen_rtx_EXPR_LIST (VOIDmode, x, const0_rtx);
5217 x = gen_rtx_PARALLEL (type_mode, gen_rtvec (1, x));
5222 /* Return a composite value in a pair of floating-point registers.
5223 MODE1 and OFFSET1 are the mode and byte offset for the first value,
5224 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
5227 For n32 & n64, $f0 always holds the first value and $f2 the second.
5228 Otherwise the values are packed together as closely as possible. */
5231 mips_return_fpr_pair (enum machine_mode mode,
5232 enum machine_mode mode1, HOST_WIDE_INT offset1,
5233 enum machine_mode mode2, HOST_WIDE_INT offset2)
5237 inc = (TARGET_NEWABI ? 2 : MAX_FPRS_PER_FMT);
5238 return gen_rtx_PARALLEL
5241 gen_rtx_EXPR_LIST (VOIDmode,
5242 gen_rtx_REG (mode1, FP_RETURN),
5244 gen_rtx_EXPR_LIST (VOIDmode,
5245 gen_rtx_REG (mode2, FP_RETURN + inc),
5246 GEN_INT (offset2))));
5250 /* Implement TARGET_FUNCTION_VALUE and TARGET_LIBCALL_VALUE.
5251 For normal calls, VALTYPE is the return type and MODE is VOIDmode.
5252 For libcalls, VALTYPE is null and MODE is the mode of the return value. */
5255 mips_function_value_1 (const_tree valtype, const_tree fn_decl_or_type,
5256 enum machine_mode mode)
5264 if (fn_decl_or_type && DECL_P (fn_decl_or_type))
5265 func = fn_decl_or_type;
5269 mode = TYPE_MODE (valtype);
5270 unsigned_p = TYPE_UNSIGNED (valtype);
5272 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
5273 return values, promote the mode here too. */
5274 mode = promote_function_mode (valtype, mode, &unsigned_p, func, 1);
5276 /* Handle structures whose fields are returned in $f0/$f2. */
5277 switch (mips_fpr_return_fields (valtype, fields))
5280 return mips_return_fpr_single (mode,
5281 TYPE_MODE (TREE_TYPE (fields[0])));
5284 return mips_return_fpr_pair (mode,
5285 TYPE_MODE (TREE_TYPE (fields[0])),
5286 int_byte_position (fields[0]),
5287 TYPE_MODE (TREE_TYPE (fields[1])),
5288 int_byte_position (fields[1]));
5291 /* If a value is passed in the most significant part of a register, see
5292 whether we have to round the mode up to a whole number of words. */
5293 if (mips_return_in_msb (valtype))
5295 HOST_WIDE_INT size = int_size_in_bytes (valtype);
5296 if (size % UNITS_PER_WORD != 0)
5298 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
5299 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
5303 /* For EABI, the class of return register depends entirely on MODE.
5304 For example, "struct { some_type x; }" and "union { some_type x; }"
5305 are returned in the same way as a bare "some_type" would be.
5306 Other ABIs only use FPRs for scalar, complex or vector types. */
5307 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
5308 return gen_rtx_REG (mode, GP_RETURN);
5313 /* Handle long doubles for n32 & n64. */
5315 return mips_return_fpr_pair (mode,
5317 DImode, GET_MODE_SIZE (mode) / 2);
5319 if (mips_return_mode_in_fpr_p (mode))
5321 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5322 return mips_return_fpr_pair (mode,
5323 GET_MODE_INNER (mode), 0,
5324 GET_MODE_INNER (mode),
5325 GET_MODE_SIZE (mode) / 2);
5327 return gen_rtx_REG (mode, FP_RETURN);
5331 return gen_rtx_REG (mode, GP_RETURN);
5334 /* Implement TARGET_FUNCTION_VALUE. */
5337 mips_function_value (const_tree valtype, const_tree fn_decl_or_type,
5338 bool outgoing ATTRIBUTE_UNUSED)
5340 return mips_function_value_1 (valtype, fn_decl_or_type, VOIDmode);
5343 /* Implement TARGET_LIBCALL_VALUE. */
5346 mips_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
5348 return mips_function_value_1 (NULL_TREE, NULL_TREE, mode);
5351 /* Implement TARGET_FUNCTION_VALUE_REGNO_P.
5353 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
5354 Currently, R2 and F0 are only implemented here (C has no complex type). */
5357 mips_function_value_regno_p (const unsigned int regno)
5359 if (regno == GP_RETURN
5360 || regno == FP_RETURN
5361 || (LONG_DOUBLE_TYPE_SIZE == 128
5362 && FP_RETURN != GP_RETURN
5363 && regno == FP_RETURN + 2))
5369 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
5370 all BLKmode objects are returned in memory. Under the n32, n64
5371 and embedded ABIs, small structures are returned in a register.
5372 Objects with varying size must still be returned in memory, of
5376 mips_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
5378 return (TARGET_OLDABI
5379 ? TYPE_MODE (type) == BLKmode
5380 : !IN_RANGE (int_size_in_bytes (type), 0, 2 * UNITS_PER_WORD));
5383 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
5386 mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5387 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5390 CUMULATIVE_ARGS local_cum;
5391 int gp_saved, fp_saved;
5393 /* The caller has advanced CUM up to, but not beyond, the last named
5394 argument. Advance a local copy of CUM past the last "real" named
5395 argument, to find out how many registers are left over. */
5397 mips_function_arg_advance (&local_cum, mode, type, true);
5399 /* Found out how many registers we need to save. */
5400 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
5401 fp_saved = (EABI_FLOAT_VARARGS_P
5402 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
5411 ptr = plus_constant (virtual_incoming_args_rtx,
5412 REG_PARM_STACK_SPACE (cfun->decl)
5413 - gp_saved * UNITS_PER_WORD);
5414 mem = gen_frame_mem (BLKmode, ptr);
5415 set_mem_alias_set (mem, get_varargs_alias_set ());
5417 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
5422 /* We can't use move_block_from_reg, because it will use
5424 enum machine_mode mode;
5427 /* Set OFF to the offset from virtual_incoming_args_rtx of
5428 the first float register. The FP save area lies below
5429 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
5430 off = (-gp_saved * UNITS_PER_WORD) & -UNITS_PER_FPVALUE;
5431 off -= fp_saved * UNITS_PER_FPREG;
5433 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
5435 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS;
5436 i += MAX_FPRS_PER_FMT)
5440 ptr = plus_constant (virtual_incoming_args_rtx, off);
5441 mem = gen_frame_mem (mode, ptr);
5442 set_mem_alias_set (mem, get_varargs_alias_set ());
5443 mips_emit_move (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
5444 off += UNITS_PER_HWFPVALUE;
5448 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
5449 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
5450 + fp_saved * UNITS_PER_FPREG);
5453 /* Implement TARGET_BUILTIN_VA_LIST. */
5456 mips_build_builtin_va_list (void)
5458 if (EABI_FLOAT_VARARGS_P)
5460 /* We keep 3 pointers, and two offsets.
5462 Two pointers are to the overflow area, which starts at the CFA.
5463 One of these is constant, for addressing into the GPR save area
5464 below it. The other is advanced up the stack through the
5467 The third pointer is to the bottom of the GPR save area.
5468 Since the FPR save area is just below it, we can address
5469 FPR slots off this pointer.
5471 We also keep two one-byte offsets, which are to be subtracted
5472 from the constant pointers to yield addresses in the GPR and
5473 FPR save areas. These are downcounted as float or non-float
5474 arguments are used, and when they get to zero, the argument
5475 must be obtained from the overflow region. */
5476 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
5479 record = lang_hooks.types.make_type (RECORD_TYPE);
5481 f_ovfl = build_decl (BUILTINS_LOCATION,
5482 FIELD_DECL, get_identifier ("__overflow_argptr"),
5484 f_gtop = build_decl (BUILTINS_LOCATION,
5485 FIELD_DECL, get_identifier ("__gpr_top"),
5487 f_ftop = build_decl (BUILTINS_LOCATION,
5488 FIELD_DECL, get_identifier ("__fpr_top"),
5490 f_goff = build_decl (BUILTINS_LOCATION,
5491 FIELD_DECL, get_identifier ("__gpr_offset"),
5492 unsigned_char_type_node);
5493 f_foff = build_decl (BUILTINS_LOCATION,
5494 FIELD_DECL, get_identifier ("__fpr_offset"),
5495 unsigned_char_type_node);
5496 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
5497 warn on every user file. */
5498 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
5499 array = build_array_type (unsigned_char_type_node,
5500 build_index_type (index));
5501 f_res = build_decl (BUILTINS_LOCATION,
5502 FIELD_DECL, get_identifier ("__reserved"), array);
5504 DECL_FIELD_CONTEXT (f_ovfl) = record;
5505 DECL_FIELD_CONTEXT (f_gtop) = record;
5506 DECL_FIELD_CONTEXT (f_ftop) = record;
5507 DECL_FIELD_CONTEXT (f_goff) = record;
5508 DECL_FIELD_CONTEXT (f_foff) = record;
5509 DECL_FIELD_CONTEXT (f_res) = record;
5511 TYPE_FIELDS (record) = f_ovfl;
5512 DECL_CHAIN (f_ovfl) = f_gtop;
5513 DECL_CHAIN (f_gtop) = f_ftop;
5514 DECL_CHAIN (f_ftop) = f_goff;
5515 DECL_CHAIN (f_goff) = f_foff;
5516 DECL_CHAIN (f_foff) = f_res;
5518 layout_type (record);
5521 else if (TARGET_IRIX6)
5522 /* On IRIX 6, this type is 'char *'. */
5523 return build_pointer_type (char_type_node);
5525 /* Otherwise, we use 'void *'. */
5526 return ptr_type_node;
5529 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
5532 mips_va_start (tree valist, rtx nextarg)
5534 if (EABI_FLOAT_VARARGS_P)
5536 const CUMULATIVE_ARGS *cum;
5537 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5538 tree ovfl, gtop, ftop, goff, foff;
5540 int gpr_save_area_size;
5541 int fpr_save_area_size;
5544 cum = &crtl->args.info;
5546 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
5548 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
5550 f_ovfl = TYPE_FIELDS (va_list_type_node);
5551 f_gtop = DECL_CHAIN (f_ovfl);
5552 f_ftop = DECL_CHAIN (f_gtop);
5553 f_goff = DECL_CHAIN (f_ftop);
5554 f_foff = DECL_CHAIN (f_goff);
5556 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5558 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
5560 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
5562 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
5564 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
5567 /* Emit code to initialize OVFL, which points to the next varargs
5568 stack argument. CUM->STACK_WORDS gives the number of stack
5569 words used by named arguments. */
5570 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
5571 if (cum->stack_words > 0)
5572 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl), t,
5573 size_int (cum->stack_words * UNITS_PER_WORD));
5574 t = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
5575 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5577 /* Emit code to initialize GTOP, the top of the GPR save area. */
5578 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
5579 t = build2 (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
5580 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5582 /* Emit code to initialize FTOP, the top of the FPR save area.
5583 This address is gpr_save_area_bytes below GTOP, rounded
5584 down to the next fp-aligned boundary. */
5585 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
5586 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
5587 fpr_offset &= -UNITS_PER_FPVALUE;
5589 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ftop), t,
5590 size_int (-fpr_offset));
5591 t = build2 (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
5592 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5594 /* Emit code to initialize GOFF, the offset from GTOP of the
5595 next GPR argument. */
5596 t = build2 (MODIFY_EXPR, TREE_TYPE (goff), goff,
5597 build_int_cst (TREE_TYPE (goff), gpr_save_area_size));
5598 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5600 /* Likewise emit code to initialize FOFF, the offset from FTOP
5601 of the next FPR argument. */
5602 t = build2 (MODIFY_EXPR, TREE_TYPE (foff), foff,
5603 build_int_cst (TREE_TYPE (foff), fpr_save_area_size));
5604 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5608 nextarg = plus_constant (nextarg, -cfun->machine->varargs_size);
5609 std_expand_builtin_va_start (valist, nextarg);
5613 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
5616 mips_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
5622 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
5624 type = build_pointer_type (type);
5626 if (!EABI_FLOAT_VARARGS_P)
5627 addr = std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5630 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5631 tree ovfl, top, off, align;
5632 HOST_WIDE_INT size, rsize, osize;
5635 f_ovfl = TYPE_FIELDS (va_list_type_node);
5636 f_gtop = DECL_CHAIN (f_ovfl);
5637 f_ftop = DECL_CHAIN (f_gtop);
5638 f_goff = DECL_CHAIN (f_ftop);
5639 f_foff = DECL_CHAIN (f_goff);
5643 TOP be the top of the GPR or FPR save area;
5644 OFF be the offset from TOP of the next register;
5645 ADDR_RTX be the address of the argument;
5646 SIZE be the number of bytes in the argument type;
5647 RSIZE be the number of bytes used to store the argument
5648 when it's in the register save area; and
5649 OSIZE be the number of bytes used to store it when it's
5650 in the stack overflow area.
5652 The code we want is:
5654 1: off &= -rsize; // round down
5657 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
5662 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
5663 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
5667 [1] and [9] can sometimes be optimized away. */
5669 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5671 size = int_size_in_bytes (type);
5673 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
5674 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
5676 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop),
5677 unshare_expr (valist), f_ftop, NULL_TREE);
5678 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff),
5679 unshare_expr (valist), f_foff, NULL_TREE);
5681 /* When va_start saves FPR arguments to the stack, each slot
5682 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
5683 argument's precision. */
5684 rsize = UNITS_PER_HWFPVALUE;
5686 /* Overflow arguments are padded to UNITS_PER_WORD bytes
5687 (= PARM_BOUNDARY bits). This can be different from RSIZE
5690 (1) On 32-bit targets when TYPE is a structure such as:
5692 struct s { float f; };
5694 Such structures are passed in paired FPRs, so RSIZE
5695 will be 8 bytes. However, the structure only takes
5696 up 4 bytes of memory, so OSIZE will only be 4.
5698 (2) In combinations such as -mgp64 -msingle-float
5699 -fshort-double. Doubles passed in registers will then take
5700 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
5701 stack take up UNITS_PER_WORD bytes. */
5702 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
5706 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop),
5707 unshare_expr (valist), f_gtop, NULL_TREE);
5708 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff),
5709 unshare_expr (valist), f_goff, NULL_TREE);
5710 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
5711 if (rsize > UNITS_PER_WORD)
5713 /* [1] Emit code for: off &= -rsize. */
5714 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), unshare_expr (off),
5715 build_int_cst (TREE_TYPE (off), -rsize));
5716 gimplify_assign (unshare_expr (off), t, pre_p);
5721 /* [2] Emit code to branch if off == 0. */
5722 t = build2 (NE_EXPR, boolean_type_node, off,
5723 build_int_cst (TREE_TYPE (off), 0));
5724 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
5726 /* [5] Emit code for: off -= rsize. We do this as a form of
5727 post-decrement not available to C. */
5728 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
5729 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
5731 /* [4] Emit code for:
5732 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
5733 t = fold_convert (sizetype, t);
5734 t = fold_build1 (NEGATE_EXPR, sizetype, t);
5735 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (top), top, t);
5736 if (BYTES_BIG_ENDIAN && rsize > size)
5738 u = size_int (rsize - size);
5739 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
5741 COND_EXPR_THEN (addr) = t;
5743 if (osize > UNITS_PER_WORD)
5745 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
5746 u = size_int (osize - 1);
5747 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl),
5748 unshare_expr (ovfl), u);
5749 t = fold_convert (sizetype, t);
5750 u = size_int (-osize);
5751 t = build2 (BIT_AND_EXPR, sizetype, t, u);
5752 t = fold_convert (TREE_TYPE (ovfl), t);
5753 align = build2 (MODIFY_EXPR, TREE_TYPE (ovfl),
5754 unshare_expr (ovfl), t);
5759 /* [10, 11] Emit code for:
5760 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
5762 u = fold_convert (TREE_TYPE (ovfl), build_int_cst (NULL_TREE, osize));
5763 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
5764 if (BYTES_BIG_ENDIAN && osize > size)
5766 u = size_int (osize - size);
5767 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
5770 /* String [9] and [10, 11] together. */
5772 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
5773 COND_EXPR_ELSE (addr) = t;
5775 addr = fold_convert (build_pointer_type (type), addr);
5776 addr = build_va_arg_indirect_ref (addr);
5780 addr = build_va_arg_indirect_ref (addr);
5785 /* Start a definition of function NAME. MIPS16_P indicates whether the
5786 function contains MIPS16 code. */
5789 mips_start_function_definition (const char *name, bool mips16_p)
5792 fprintf (asm_out_file, "\t.set\tmips16\n");
5794 fprintf (asm_out_file, "\t.set\tnomips16\n");
5796 if (!flag_inhibit_size_directive)
5798 fputs ("\t.ent\t", asm_out_file);
5799 assemble_name (asm_out_file, name);
5800 fputs ("\n", asm_out_file);
5803 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, name, "function");
5805 /* Start the definition proper. */
5806 assemble_name (asm_out_file, name);
5807 fputs (":\n", asm_out_file);
5810 /* End a function definition started by mips_start_function_definition. */
5813 mips_end_function_definition (const char *name)
5815 if (!flag_inhibit_size_directive)
5817 fputs ("\t.end\t", asm_out_file);
5818 assemble_name (asm_out_file, name);
5819 fputs ("\n", asm_out_file);
5823 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
5826 mips_ok_for_lazy_binding_p (rtx x)
5828 return (TARGET_USE_GOT
5829 && GET_CODE (x) == SYMBOL_REF
5830 && !SYMBOL_REF_BIND_NOW_P (x)
5831 && !mips_symbol_binds_local_p (x));
5834 /* Load function address ADDR into register DEST. TYPE is as for
5835 mips_expand_call. Return true if we used an explicit lazy-binding
5839 mips_load_call_address (enum mips_call_type type, rtx dest, rtx addr)
5841 /* If we're generating PIC, and this call is to a global function,
5842 try to allow its address to be resolved lazily. This isn't
5843 possible for sibcalls when $gp is call-saved because the value
5844 of $gp on entry to the stub would be our caller's gp, not ours. */
5845 if (TARGET_EXPLICIT_RELOCS
5846 && !(type == MIPS_CALL_SIBCALL && TARGET_CALL_SAVED_GP)
5847 && mips_ok_for_lazy_binding_p (addr))
5849 addr = mips_got_load (dest, addr, SYMBOL_GOTOFF_CALL);
5850 emit_insn (gen_rtx_SET (VOIDmode, dest, addr));
5855 mips_emit_move (dest, addr);
5860 /* Each locally-defined hard-float MIPS16 function has a local symbol
5861 associated with it. This hash table maps the function symbol (FUNC)
5862 to the local symbol (LOCAL). */
5863 struct GTY(()) mips16_local_alias {
5867 static GTY ((param_is (struct mips16_local_alias))) htab_t mips16_local_aliases;
5869 /* Hash table callbacks for mips16_local_aliases. */
5872 mips16_local_aliases_hash (const void *entry)
5874 const struct mips16_local_alias *alias;
5876 alias = (const struct mips16_local_alias *) entry;
5877 return htab_hash_string (XSTR (alias->func, 0));
5881 mips16_local_aliases_eq (const void *entry1, const void *entry2)
5883 const struct mips16_local_alias *alias1, *alias2;
5885 alias1 = (const struct mips16_local_alias *) entry1;
5886 alias2 = (const struct mips16_local_alias *) entry2;
5887 return rtx_equal_p (alias1->func, alias2->func);
5890 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
5891 Return a local alias for it, creating a new one if necessary. */
5894 mips16_local_alias (rtx func)
5896 struct mips16_local_alias *alias, tmp_alias;
5899 /* Create the hash table if this is the first call. */
5900 if (mips16_local_aliases == NULL)
5901 mips16_local_aliases = htab_create_ggc (37, mips16_local_aliases_hash,
5902 mips16_local_aliases_eq, NULL);
5904 /* Look up the function symbol, creating a new entry if need be. */
5905 tmp_alias.func = func;
5906 slot = htab_find_slot (mips16_local_aliases, &tmp_alias, INSERT);
5907 gcc_assert (slot != NULL);
5909 alias = (struct mips16_local_alias *) *slot;
5912 const char *func_name, *local_name;
5915 /* Create a new SYMBOL_REF for the local symbol. The choice of
5916 __fn_local_* is based on the __fn_stub_* names that we've
5917 traditionally used for the non-MIPS16 stub. */
5918 func_name = targetm.strip_name_encoding (XSTR (func, 0));
5919 local_name = ACONCAT (("__fn_local_", func_name, NULL));
5920 local = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (local_name));
5921 SYMBOL_REF_FLAGS (local) = SYMBOL_REF_FLAGS (func) | SYMBOL_FLAG_LOCAL;
5923 /* Create a new structure to represent the mapping. */
5924 alias = ggc_alloc_mips16_local_alias ();
5926 alias->local = local;
5929 return alias->local;
5932 /* A chained list of functions for which mips16_build_call_stub has already
5933 generated a stub. NAME is the name of the function and FP_RET_P is true
5934 if the function returns a value in floating-point registers. */
5935 struct mips16_stub {
5936 struct mips16_stub *next;
5940 static struct mips16_stub *mips16_stubs;
5942 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
5945 mips16_stub_function (const char *name)
5949 x = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
5950 SYMBOL_REF_FLAGS (x) |= (SYMBOL_FLAG_EXTERNAL | SYMBOL_FLAG_FUNCTION);
5954 /* Return the two-character string that identifies floating-point
5955 return mode MODE in the name of a MIPS16 function stub. */
5958 mips16_call_stub_mode_suffix (enum machine_mode mode)
5962 else if (mode == DFmode)
5964 else if (mode == SCmode)
5966 else if (mode == DCmode)
5968 else if (mode == V2SFmode)
5974 /* Write instructions to move a 32-bit value between general register
5975 GPREG and floating-point register FPREG. DIRECTION is 't' to move
5976 from GPREG to FPREG and 'f' to move in the opposite direction. */
5979 mips_output_32bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
5981 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5982 reg_names[gpreg], reg_names[fpreg]);
5985 /* Likewise for 64-bit values. */
5988 mips_output_64bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
5991 fprintf (asm_out_file, "\tdm%cc1\t%s,%s\n", direction,
5992 reg_names[gpreg], reg_names[fpreg]);
5993 else if (TARGET_FLOAT64)
5995 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5996 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
5997 fprintf (asm_out_file, "\tm%chc1\t%s,%s\n", direction,
5998 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg]);
6002 /* Move the least-significant word. */
6003 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6004 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
6005 /* ...then the most significant word. */
6006 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6007 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg + 1]);
6011 /* Write out code to move floating-point arguments into or out of
6012 general registers. FP_CODE is the code describing which arguments
6013 are present (see the comment above the definition of CUMULATIVE_ARGS
6014 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
6017 mips_output_args_xfer (int fp_code, char direction)
6019 unsigned int gparg, fparg, f;
6020 CUMULATIVE_ARGS cum;
6022 /* This code only works for o32 and o64. */
6023 gcc_assert (TARGET_OLDABI);
6025 mips_init_cumulative_args (&cum, NULL);
6027 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
6029 enum machine_mode mode;
6030 struct mips_arg_info info;
6034 else if ((f & 3) == 2)
6039 mips_get_arg_info (&info, &cum, mode, NULL, true);
6040 gparg = mips_arg_regno (&info, false);
6041 fparg = mips_arg_regno (&info, true);
6044 mips_output_32bit_xfer (direction, gparg, fparg);
6046 mips_output_64bit_xfer (direction, gparg, fparg);
6048 mips_function_arg_advance (&cum, mode, NULL, true);
6052 /* Write a MIPS16 stub for the current function. This stub is used
6053 for functions which take arguments in the floating-point registers.
6054 It is normal-mode code that moves the floating-point arguments
6055 into the general registers and then jumps to the MIPS16 code. */
6058 mips16_build_function_stub (void)
6060 const char *fnname, *alias_name, *separator;
6061 char *secname, *stubname;
6066 /* Create the name of the stub, and its unique section. */
6067 symbol = XEXP (DECL_RTL (current_function_decl), 0);
6068 alias = mips16_local_alias (symbol);
6070 fnname = targetm.strip_name_encoding (XSTR (symbol, 0));
6071 alias_name = targetm.strip_name_encoding (XSTR (alias, 0));
6072 secname = ACONCAT ((".mips16.fn.", fnname, NULL));
6073 stubname = ACONCAT (("__fn_stub_", fnname, NULL));
6075 /* Build a decl for the stub. */
6076 stubdecl = build_decl (BUILTINS_LOCATION,
6077 FUNCTION_DECL, get_identifier (stubname),
6078 build_function_type (void_type_node, NULL_TREE));
6079 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
6080 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
6081 RESULT_DECL, NULL_TREE, void_type_node);
6083 /* Output a comment. */
6084 fprintf (asm_out_file, "\t# Stub function for %s (",
6085 current_function_name ());
6087 for (f = (unsigned int) crtl->args.info.fp_code; f != 0; f >>= 2)
6089 fprintf (asm_out_file, "%s%s", separator,
6090 (f & 3) == 1 ? "float" : "double");
6093 fprintf (asm_out_file, ")\n");
6095 /* Start the function definition. */
6096 assemble_start_function (stubdecl, stubname);
6097 mips_start_function_definition (stubname, false);
6099 /* If generating pic2 code, either set up the global pointer or
6101 if (TARGET_ABICALLS_PIC2)
6103 if (TARGET_ABSOLUTE_ABICALLS)
6104 fprintf (asm_out_file, "\t.option\tpic0\n");
6107 output_asm_insn ("%(.cpload\t%^%)", NULL);
6108 /* Emit an R_MIPS_NONE relocation to tell the linker what the
6109 target function is. Use a local GOT access when loading the
6110 symbol, to cut down on the number of unnecessary GOT entries
6111 for stubs that aren't needed. */
6112 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol);
6117 /* Load the address of the MIPS16 function into $25. Do this first so
6118 that targets with coprocessor interlocks can use an MFC1 to fill the
6120 output_asm_insn ("la\t%^,%0", &symbol);
6122 /* Move the arguments from floating-point registers to general registers. */
6123 mips_output_args_xfer (crtl->args.info.fp_code, 'f');
6125 /* Jump to the MIPS16 function. */
6126 output_asm_insn ("jr\t%^", NULL);
6128 if (TARGET_ABICALLS_PIC2 && TARGET_ABSOLUTE_ABICALLS)
6129 fprintf (asm_out_file, "\t.option\tpic2\n");
6131 mips_end_function_definition (stubname);
6133 /* If the linker needs to create a dynamic symbol for the target
6134 function, it will associate the symbol with the stub (which,
6135 unlike the target function, follows the proper calling conventions).
6136 It is therefore useful to have a local alias for the target function,
6137 so that it can still be identified as MIPS16 code. As an optimization,
6138 this symbol can also be used for indirect MIPS16 references from
6139 within this file. */
6140 ASM_OUTPUT_DEF (asm_out_file, alias_name, fnname);
6142 switch_to_section (function_section (current_function_decl));
6145 /* The current function is a MIPS16 function that returns a value in an FPR.
6146 Copy the return value from its soft-float to its hard-float location.
6147 libgcc2 has special non-MIPS16 helper functions for each case. */
6150 mips16_copy_fpr_return_value (void)
6152 rtx fn, insn, retval;
6154 enum machine_mode return_mode;
6157 return_type = DECL_RESULT (current_function_decl);
6158 return_mode = DECL_MODE (return_type);
6160 name = ACONCAT (("__mips16_ret_",
6161 mips16_call_stub_mode_suffix (return_mode),
6163 fn = mips16_stub_function (name);
6165 /* The function takes arguments in $2 (and possibly $3), so calls
6166 to it cannot be lazily bound. */
6167 SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_BIND_NOW;
6169 /* Model the call as something that takes the GPR return value as
6170 argument and returns an "updated" value. */
6171 retval = gen_rtx_REG (return_mode, GP_RETURN);
6172 insn = mips_expand_call (MIPS_CALL_EPILOGUE, retval, fn,
6173 const0_rtx, NULL_RTX, false);
6174 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), retval);
6177 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
6178 RETVAL is the location of the return value, or null if this is
6179 a "call" rather than a "call_value". ARGS_SIZE is the size of the
6180 arguments and FP_CODE is the code built by mips_function_arg;
6181 see the comment before the fp_code field in CUMULATIVE_ARGS for details.
6183 There are three alternatives:
6185 - If a stub was needed, emit the call and return the call insn itself.
6187 - If we can avoid using a stub by redirecting the call, set *FN_PTR
6188 to the new target and return null.
6190 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
6193 A stub is needed for calls to functions that, in normal mode,
6194 receive arguments in FPRs or return values in FPRs. The stub
6195 copies the arguments from their soft-float positions to their
6196 hard-float positions, calls the real function, then copies the
6197 return value from its hard-float position to its soft-float
6200 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
6201 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
6202 automatically redirects the JAL to the stub, otherwise the JAL
6203 continues to call FN directly. */
6206 mips16_build_call_stub (rtx retval, rtx *fn_ptr, rtx args_size, int fp_code)
6210 struct mips16_stub *l;
6213 /* We don't need to do anything if we aren't in MIPS16 mode, or if
6214 we were invoked with the -msoft-float option. */
6215 if (!TARGET_MIPS16 || TARGET_SOFT_FLOAT_ABI)
6218 /* Figure out whether the value might come back in a floating-point
6220 fp_ret_p = retval && mips_return_mode_in_fpr_p (GET_MODE (retval));
6222 /* We don't need to do anything if there were no floating-point
6223 arguments and the value will not be returned in a floating-point
6225 if (fp_code == 0 && !fp_ret_p)
6228 /* We don't need to do anything if this is a call to a special
6229 MIPS16 support function. */
6231 if (mips16_stub_function_p (fn))
6234 /* This code will only work for o32 and o64 abis. The other ABI's
6235 require more sophisticated support. */
6236 gcc_assert (TARGET_OLDABI);
6238 /* If we're calling via a function pointer, use one of the magic
6239 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
6240 Each stub expects the function address to arrive in register $2. */
6241 if (GET_CODE (fn) != SYMBOL_REF
6242 || !call_insn_operand (fn, VOIDmode))
6245 rtx stub_fn, insn, addr;
6248 /* If this is a locally-defined and locally-binding function,
6249 avoid the stub by calling the local alias directly. */
6250 if (mips16_local_function_p (fn))
6252 *fn_ptr = mips16_local_alias (fn);
6256 /* Create a SYMBOL_REF for the libgcc.a function. */
6258 sprintf (buf, "__mips16_call_stub_%s_%d",
6259 mips16_call_stub_mode_suffix (GET_MODE (retval)),
6262 sprintf (buf, "__mips16_call_stub_%d", fp_code);
6263 stub_fn = mips16_stub_function (buf);
6265 /* The function uses $2 as an argument, so calls to it
6266 cannot be lazily bound. */
6267 SYMBOL_REF_FLAGS (stub_fn) |= SYMBOL_FLAG_BIND_NOW;
6269 /* Load the target function into $2. */
6270 addr = gen_rtx_REG (Pmode, GP_REG_FIRST + 2);
6271 lazy_p = mips_load_call_address (MIPS_CALL_NORMAL, addr, fn);
6273 /* Emit the call. */
6274 insn = mips_expand_call (MIPS_CALL_NORMAL, retval, stub_fn,
6275 args_size, NULL_RTX, lazy_p);
6277 /* Tell GCC that this call does indeed use the value of $2. */
6278 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), addr);
6280 /* If we are handling a floating-point return value, we need to
6281 save $18 in the function prologue. Putting a note on the
6282 call will mean that df_regs_ever_live_p ($18) will be true if the
6283 call is not eliminated, and we can check that in the prologue
6286 CALL_INSN_FUNCTION_USAGE (insn) =
6287 gen_rtx_EXPR_LIST (VOIDmode,
6288 gen_rtx_CLOBBER (VOIDmode,
6289 gen_rtx_REG (word_mode, 18)),
6290 CALL_INSN_FUNCTION_USAGE (insn));
6295 /* We know the function we are going to call. If we have already
6296 built a stub, we don't need to do anything further. */
6297 fnname = targetm.strip_name_encoding (XSTR (fn, 0));
6298 for (l = mips16_stubs; l != NULL; l = l->next)
6299 if (strcmp (l->name, fnname) == 0)
6304 const char *separator;
6305 char *secname, *stubname;
6306 tree stubid, stubdecl;
6309 /* If the function does not return in FPRs, the special stub
6313 If the function does return in FPRs, the stub section is named
6314 .mips16.call.fp.FNNAME
6316 Build a decl for the stub. */
6317 secname = ACONCAT ((".mips16.call.", fp_ret_p ? "fp." : "",
6319 stubname = ACONCAT (("__call_stub_", fp_ret_p ? "fp_" : "",
6321 stubid = get_identifier (stubname);
6322 stubdecl = build_decl (BUILTINS_LOCATION,
6323 FUNCTION_DECL, stubid,
6324 build_function_type (void_type_node, NULL_TREE));
6325 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
6326 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
6327 RESULT_DECL, NULL_TREE,
6330 /* Output a comment. */
6331 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
6333 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
6337 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
6339 fprintf (asm_out_file, "%s%s", separator,
6340 (f & 3) == 1 ? "float" : "double");
6343 fprintf (asm_out_file, ")\n");
6345 /* Start the function definition. */
6346 assemble_start_function (stubdecl, stubname);
6347 mips_start_function_definition (stubname, false);
6351 /* Load the address of the MIPS16 function into $25. Do this
6352 first so that targets with coprocessor interlocks can use
6353 an MFC1 to fill the delay slot. */
6354 if (TARGET_EXPLICIT_RELOCS)
6356 output_asm_insn ("lui\t%^,%%hi(%0)", &fn);
6357 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn);
6360 output_asm_insn ("la\t%^,%0", &fn);
6363 /* Move the arguments from general registers to floating-point
6365 mips_output_args_xfer (fp_code, 't');
6369 /* Jump to the previously-loaded address. */
6370 output_asm_insn ("jr\t%^", NULL);
6374 /* Save the return address in $18 and call the non-MIPS16 function.
6375 The stub's caller knows that $18 might be clobbered, even though
6376 $18 is usually a call-saved register. */
6377 fprintf (asm_out_file, "\tmove\t%s,%s\n",
6378 reg_names[GP_REG_FIRST + 18], reg_names[RETURN_ADDR_REGNUM]);
6379 output_asm_insn (MIPS_CALL ("jal", &fn, 0, -1), &fn);
6381 /* Move the result from floating-point registers to
6382 general registers. */
6383 switch (GET_MODE (retval))
6386 mips_output_32bit_xfer ('f', GP_RETURN + TARGET_BIG_ENDIAN,
6388 ? FP_REG_FIRST + MAX_FPRS_PER_FMT
6390 mips_output_32bit_xfer ('f', GP_RETURN + TARGET_LITTLE_ENDIAN,
6391 TARGET_LITTLE_ENDIAN
6392 ? FP_REG_FIRST + MAX_FPRS_PER_FMT
6394 if (GET_MODE (retval) == SCmode && TARGET_64BIT)
6396 /* On 64-bit targets, complex floats are returned in
6397 a single GPR, such that "sd" on a suitably-aligned
6398 target would store the value correctly. */
6399 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
6400 reg_names[GP_RETURN + TARGET_BIG_ENDIAN],
6401 reg_names[GP_RETURN + TARGET_BIG_ENDIAN]);
6402 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
6403 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN],
6404 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN]);
6405 fprintf (asm_out_file, "\tdsrl\t%s,%s,32\n",
6406 reg_names[GP_RETURN + TARGET_BIG_ENDIAN],
6407 reg_names[GP_RETURN + TARGET_BIG_ENDIAN]);
6408 fprintf (asm_out_file, "\tor\t%s,%s,%s\n",
6409 reg_names[GP_RETURN],
6410 reg_names[GP_RETURN],
6411 reg_names[GP_RETURN + 1]);
6416 mips_output_32bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6420 mips_output_64bit_xfer ('f', GP_RETURN + (8 / UNITS_PER_WORD),
6421 FP_REG_FIRST + MAX_FPRS_PER_FMT);
6425 mips_output_64bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6431 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 18]);
6434 #ifdef ASM_DECLARE_FUNCTION_SIZE
6435 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
6438 mips_end_function_definition (stubname);
6440 /* Record this stub. */
6441 l = XNEW (struct mips16_stub);
6442 l->name = xstrdup (fnname);
6443 l->fp_ret_p = fp_ret_p;
6444 l->next = mips16_stubs;
6448 /* If we expect a floating-point return value, but we've built a
6449 stub which does not expect one, then we're in trouble. We can't
6450 use the existing stub, because it won't handle the floating-point
6451 value. We can't build a new stub, because the linker won't know
6452 which stub to use for the various calls in this object file.
6453 Fortunately, this case is illegal, since it means that a function
6454 was declared in two different ways in a single compilation. */
6455 if (fp_ret_p && !l->fp_ret_p)
6456 error ("cannot handle inconsistent calls to %qs", fnname);
6458 if (retval == NULL_RTX)
6459 insn = gen_call_internal_direct (fn, args_size);
6461 insn = gen_call_value_internal_direct (retval, fn, args_size);
6462 insn = mips_emit_call_insn (insn, fn, fn, false);
6464 /* If we are calling a stub which handles a floating-point return
6465 value, we need to arrange to save $18 in the prologue. We do this
6466 by marking the function call as using the register. The prologue
6467 will later see that it is used, and emit code to save it. */
6469 CALL_INSN_FUNCTION_USAGE (insn) =
6470 gen_rtx_EXPR_LIST (VOIDmode,
6471 gen_rtx_CLOBBER (VOIDmode,
6472 gen_rtx_REG (word_mode, 18)),
6473 CALL_INSN_FUNCTION_USAGE (insn));
6478 /* Expand a call of type TYPE. RESULT is where the result will go (null
6479 for "call"s and "sibcall"s), ADDR is the address of the function,
6480 ARGS_SIZE is the size of the arguments and AUX is the value passed
6481 to us by mips_function_arg. LAZY_P is true if this call already
6482 involves a lazily-bound function address (such as when calling
6483 functions through a MIPS16 hard-float stub).
6485 Return the call itself. */
6488 mips_expand_call (enum mips_call_type type, rtx result, rtx addr,
6489 rtx args_size, rtx aux, bool lazy_p)
6491 rtx orig_addr, pattern, insn;
6494 fp_code = aux == 0 ? 0 : (int) GET_MODE (aux);
6495 insn = mips16_build_call_stub (result, &addr, args_size, fp_code);
6498 gcc_assert (!lazy_p && type == MIPS_CALL_NORMAL);
6503 if (!call_insn_operand (addr, VOIDmode))
6505 if (type == MIPS_CALL_EPILOGUE)
6506 addr = MIPS_EPILOGUE_TEMP (Pmode);
6508 addr = gen_reg_rtx (Pmode);
6509 lazy_p |= mips_load_call_address (type, addr, orig_addr);
6514 rtx (*fn) (rtx, rtx);
6516 if (type == MIPS_CALL_SIBCALL)
6517 fn = gen_sibcall_internal;
6519 fn = gen_call_internal;
6521 pattern = fn (addr, args_size);
6523 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
6525 /* Handle return values created by mips_return_fpr_pair. */
6526 rtx (*fn) (rtx, rtx, rtx, rtx);
6529 if (type == MIPS_CALL_SIBCALL)
6530 fn = gen_sibcall_value_multiple_internal;
6532 fn = gen_call_value_multiple_internal;
6534 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
6535 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
6536 pattern = fn (reg1, addr, args_size, reg2);
6540 rtx (*fn) (rtx, rtx, rtx);
6542 if (type == MIPS_CALL_SIBCALL)
6543 fn = gen_sibcall_value_internal;
6545 fn = gen_call_value_internal;
6547 /* Handle return values created by mips_return_fpr_single. */
6548 if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 1)
6549 result = XEXP (XVECEXP (result, 0, 0), 0);
6550 pattern = fn (result, addr, args_size);
6553 return mips_emit_call_insn (pattern, orig_addr, addr, lazy_p);
6556 /* Split call instruction INSN into a $gp-clobbering call and
6557 (where necessary) an instruction to restore $gp from its save slot.
6558 CALL_PATTERN is the pattern of the new call. */
6561 mips_split_call (rtx insn, rtx call_pattern)
6563 emit_call_insn (call_pattern);
6564 if (!find_reg_note (insn, REG_NORETURN, 0))
6565 /* Pick a temporary register that is suitable for both MIPS16 and
6566 non-MIPS16 code. $4 and $5 are used for returning complex double
6567 values in soft-float code, so $6 is the first suitable candidate. */
6568 mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode, GP_ARG_FIRST + 2));
6571 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
6574 mips_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
6576 if (!TARGET_SIBCALLS)
6579 /* Interrupt handlers need special epilogue code and therefore can't
6581 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
6584 /* We can't do a sibcall if the called function is a MIPS16 function
6585 because there is no direct "jx" instruction equivalent to "jalx" to
6586 switch the ISA mode. We only care about cases where the sibling
6587 and normal calls would both be direct. */
6589 && mips_use_mips16_mode_p (decl)
6590 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
6593 /* When -minterlink-mips16 is in effect, assume that non-locally-binding
6594 functions could be MIPS16 ones unless an attribute explicitly tells
6596 if (TARGET_INTERLINK_MIPS16
6598 && (DECL_EXTERNAL (decl) || !targetm.binds_local_p (decl))
6599 && !mips_nomips16_decl_p (decl)
6600 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
6607 /* Emit code to move general operand SRC into condition-code
6608 register DEST given that SCRATCH is a scratch TFmode FPR.
6615 where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */
6618 mips_expand_fcc_reload (rtx dest, rtx src, rtx scratch)
6622 /* Change the source to SFmode. */
6624 src = adjust_address (src, SFmode, 0);
6625 else if (REG_P (src) || GET_CODE (src) == SUBREG)
6626 src = gen_rtx_REG (SFmode, true_regnum (src));
6628 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
6629 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + MAX_FPRS_PER_FMT);
6631 mips_emit_move (copy_rtx (fp1), src);
6632 mips_emit_move (copy_rtx (fp2), CONST0_RTX (SFmode));
6633 emit_insn (gen_slt_sf (dest, fp2, fp1));
6636 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
6637 Assume that the areas do not overlap. */
6640 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
6642 HOST_WIDE_INT offset, delta;
6643 unsigned HOST_WIDE_INT bits;
6645 enum machine_mode mode;
6648 /* Work out how many bits to move at a time. If both operands have
6649 half-word alignment, it is usually better to move in half words.
6650 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
6651 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
6652 Otherwise move word-sized chunks. */
6653 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
6654 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
6655 bits = BITS_PER_WORD / 2;
6657 bits = BITS_PER_WORD;
6659 mode = mode_for_size (bits, MODE_INT, 0);
6660 delta = bits / BITS_PER_UNIT;
6662 /* Allocate a buffer for the temporary registers. */
6663 regs = XALLOCAVEC (rtx, length / delta);
6665 /* Load as many BITS-sized chunks as possible. Use a normal load if
6666 the source has enough alignment, otherwise use left/right pairs. */
6667 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
6669 regs[i] = gen_reg_rtx (mode);
6670 if (MEM_ALIGN (src) >= bits)
6671 mips_emit_move (regs[i], adjust_address (src, mode, offset));
6674 rtx part = adjust_address (src, BLKmode, offset);
6675 if (!mips_expand_ext_as_unaligned_load (regs[i], part, bits, 0))
6680 /* Copy the chunks to the destination. */
6681 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
6682 if (MEM_ALIGN (dest) >= bits)
6683 mips_emit_move (adjust_address (dest, mode, offset), regs[i]);
6686 rtx part = adjust_address (dest, BLKmode, offset);
6687 if (!mips_expand_ins_as_unaligned_store (part, regs[i], bits, 0))
6691 /* Mop up any left-over bytes. */
6692 if (offset < length)
6694 src = adjust_address (src, BLKmode, offset);
6695 dest = adjust_address (dest, BLKmode, offset);
6696 move_by_pieces (dest, src, length - offset,
6697 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
6701 /* Helper function for doing a loop-based block operation on memory
6702 reference MEM. Each iteration of the loop will operate on LENGTH
6705 Create a new base register for use within the loop and point it to
6706 the start of MEM. Create a new memory reference that uses this
6707 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
6710 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
6711 rtx *loop_reg, rtx *loop_mem)
6713 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
6715 /* Although the new mem does not refer to a known location,
6716 it does keep up to LENGTH bytes of alignment. */
6717 *loop_mem = change_address (mem, BLKmode, *loop_reg);
6718 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
6721 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
6722 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
6723 the memory regions do not overlap. */
6726 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length,
6727 HOST_WIDE_INT bytes_per_iter)
6729 rtx label, src_reg, dest_reg, final_src, test;
6730 HOST_WIDE_INT leftover;
6732 leftover = length % bytes_per_iter;
6735 /* Create registers and memory references for use within the loop. */
6736 mips_adjust_block_mem (src, bytes_per_iter, &src_reg, &src);
6737 mips_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest);
6739 /* Calculate the value that SRC_REG should have after the last iteration
6741 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
6744 /* Emit the start of the loop. */
6745 label = gen_label_rtx ();
6748 /* Emit the loop body. */
6749 mips_block_move_straight (dest, src, bytes_per_iter);
6751 /* Move on to the next block. */
6752 mips_emit_move (src_reg, plus_constant (src_reg, bytes_per_iter));
6753 mips_emit_move (dest_reg, plus_constant (dest_reg, bytes_per_iter));
6755 /* Emit the loop condition. */
6756 test = gen_rtx_NE (VOIDmode, src_reg, final_src);
6757 if (Pmode == DImode)
6758 emit_jump_insn (gen_cbranchdi4 (test, src_reg, final_src, label));
6760 emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label));
6762 /* Mop up any left-over bytes. */
6764 mips_block_move_straight (dest, src, leftover);
6767 /* Expand a movmemsi instruction, which copies LENGTH bytes from
6768 memory reference SRC to memory reference DEST. */
6771 mips_expand_block_move (rtx dest, rtx src, rtx length)
6773 if (CONST_INT_P (length))
6775 if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)
6777 mips_block_move_straight (dest, src, INTVAL (length));
6782 mips_block_move_loop (dest, src, INTVAL (length),
6783 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER);
6790 /* Expand a loop of synci insns for the address range [BEGIN, END). */
6793 mips_expand_synci_loop (rtx begin, rtx end)
6795 rtx inc, label, end_label, cmp_result, mask, length;
6797 /* Create end_label. */
6798 end_label = gen_label_rtx ();
6800 /* Check if begin equals end. */
6801 cmp_result = gen_rtx_EQ (VOIDmode, begin, end);
6802 emit_jump_insn (gen_condjump (cmp_result, end_label));
6804 /* Load INC with the cache line size (rdhwr INC,$1). */
6805 inc = gen_reg_rtx (Pmode);
6806 emit_insn (Pmode == SImode
6807 ? gen_rdhwr_synci_step_si (inc)
6808 : gen_rdhwr_synci_step_di (inc));
6810 /* Check if inc is 0. */
6811 cmp_result = gen_rtx_EQ (VOIDmode, inc, const0_rtx);
6812 emit_jump_insn (gen_condjump (cmp_result, end_label));
6814 /* Calculate mask. */
6815 mask = mips_force_unary (Pmode, NEG, inc);
6817 /* Mask out begin by mask. */
6818 begin = mips_force_binary (Pmode, AND, begin, mask);
6820 /* Calculate length. */
6821 length = mips_force_binary (Pmode, MINUS, end, begin);
6823 /* Loop back to here. */
6824 label = gen_label_rtx ();
6827 emit_insn (gen_synci (begin));
6829 /* Update length. */
6830 mips_emit_binary (MINUS, length, length, inc);
6833 mips_emit_binary (PLUS, begin, begin, inc);
6835 /* Check if length is greater than 0. */
6836 cmp_result = gen_rtx_GT (VOIDmode, length, const0_rtx);
6837 emit_jump_insn (gen_condjump (cmp_result, label));
6839 emit_label (end_label);
6842 /* Expand a QI or HI mode atomic memory operation.
6844 GENERATOR contains a pointer to the gen_* function that generates
6845 the SI mode underlying atomic operation using masks that we
6848 RESULT is the return register for the operation. Its value is NULL
6851 MEM is the location of the atomic access.
6853 OLDVAL is the first operand for the operation.
6855 NEWVAL is the optional second operand for the operation. Its value
6856 is NULL if unused. */
6859 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator,
6860 rtx result, rtx mem, rtx oldval, rtx newval)
6862 rtx orig_addr, memsi_addr, memsi, shift, shiftsi, unshifted_mask;
6863 rtx unshifted_mask_reg, mask, inverted_mask, si_op;
6865 enum machine_mode mode;
6867 mode = GET_MODE (mem);
6869 /* Compute the address of the containing SImode value. */
6870 orig_addr = force_reg (Pmode, XEXP (mem, 0));
6871 memsi_addr = mips_force_binary (Pmode, AND, orig_addr,
6872 force_reg (Pmode, GEN_INT (-4)));
6874 /* Create a memory reference for it. */
6875 memsi = gen_rtx_MEM (SImode, memsi_addr);
6876 set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER);
6877 MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem);
6879 /* Work out the byte offset of the QImode or HImode value,
6880 counting from the least significant byte. */
6881 shift = mips_force_binary (Pmode, AND, orig_addr, GEN_INT (3));
6882 if (TARGET_BIG_ENDIAN)
6883 mips_emit_binary (XOR, shift, shift, GEN_INT (mode == QImode ? 3 : 2));
6885 /* Multiply by eight to convert the shift value from bytes to bits. */
6886 mips_emit_binary (ASHIFT, shift, shift, GEN_INT (3));
6888 /* Make the final shift an SImode value, so that it can be used in
6889 SImode operations. */
6890 shiftsi = force_reg (SImode, gen_lowpart (SImode, shift));
6892 /* Set MASK to an inclusive mask of the QImode or HImode value. */
6893 unshifted_mask = GEN_INT (GET_MODE_MASK (mode));
6894 unshifted_mask_reg = force_reg (SImode, unshifted_mask);
6895 mask = mips_force_binary (SImode, ASHIFT, unshifted_mask_reg, shiftsi);
6897 /* Compute the equivalent exclusive mask. */
6898 inverted_mask = gen_reg_rtx (SImode);
6899 emit_insn (gen_rtx_SET (VOIDmode, inverted_mask,
6900 gen_rtx_NOT (SImode, mask)));
6902 /* Shift the old value into place. */
6903 if (oldval != const0_rtx)
6905 oldval = convert_modes (SImode, mode, oldval, true);
6906 oldval = force_reg (SImode, oldval);
6907 oldval = mips_force_binary (SImode, ASHIFT, oldval, shiftsi);
6910 /* Do the same for the new value. */
6911 if (newval && newval != const0_rtx)
6913 newval = convert_modes (SImode, mode, newval, true);
6914 newval = force_reg (SImode, newval);
6915 newval = mips_force_binary (SImode, ASHIFT, newval, shiftsi);
6918 /* Do the SImode atomic access. */
6920 res = gen_reg_rtx (SImode);
6922 si_op = generator.fn_6 (res, memsi, mask, inverted_mask, oldval, newval);
6924 si_op = generator.fn_5 (res, memsi, mask, inverted_mask, oldval);
6926 si_op = generator.fn_4 (memsi, mask, inverted_mask, oldval);
6932 /* Shift and convert the result. */
6933 mips_emit_binary (AND, res, res, mask);
6934 mips_emit_binary (LSHIFTRT, res, res, shiftsi);
6935 mips_emit_move (result, gen_lowpart (GET_MODE (result), res));
6939 /* Return true if it is possible to use left/right accesses for a
6940 bitfield of WIDTH bits starting BITPOS bits into *OP. When
6941 returning true, update *OP, *LEFT and *RIGHT as follows:
6943 *OP is a BLKmode reference to the whole field.
6945 *LEFT is a QImode reference to the first byte if big endian or
6946 the last byte if little endian. This address can be used in the
6947 left-side instructions (LWL, SWL, LDL, SDL).
6949 *RIGHT is a QImode reference to the opposite end of the field and
6950 can be used in the patterning right-side instruction. */
6953 mips_get_unaligned_mem (rtx *op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos,
6954 rtx *left, rtx *right)
6958 /* Check that the operand really is a MEM. Not all the extv and
6959 extzv predicates are checked. */
6963 /* Check that the size is valid. */
6964 if (width != 32 && (!TARGET_64BIT || width != 64))
6967 /* We can only access byte-aligned values. Since we are always passed
6968 a reference to the first byte of the field, it is not necessary to
6969 do anything with BITPOS after this check. */
6970 if (bitpos % BITS_PER_UNIT != 0)
6973 /* Reject aligned bitfields: we want to use a normal load or store
6974 instead of a left/right pair. */
6975 if (MEM_ALIGN (*op) >= width)
6978 /* Adjust *OP to refer to the whole field. This also has the effect
6979 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
6980 *op = adjust_address (*op, BLKmode, 0);
6981 set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
6983 /* Get references to both ends of the field. We deliberately don't
6984 use the original QImode *OP for FIRST since the new BLKmode one
6985 might have a simpler address. */
6986 first = adjust_address (*op, QImode, 0);
6987 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
6989 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
6990 correspond to the MSB and RIGHT to the LSB. */
6991 if (TARGET_BIG_ENDIAN)
6992 *left = first, *right = last;
6994 *left = last, *right = first;
6999 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
7000 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
7001 the operation is the equivalent of:
7003 (set DEST (*_extract SRC WIDTH BITPOS))
7005 Return true on success. */
7008 mips_expand_ext_as_unaligned_load (rtx dest, rtx src, HOST_WIDE_INT width,
7009 HOST_WIDE_INT bitpos)
7011 rtx left, right, temp;
7013 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
7014 be a paradoxical word_mode subreg. This is the only case in which
7015 we allow the destination to be larger than the source. */
7016 if (GET_CODE (dest) == SUBREG
7017 && GET_MODE (dest) == DImode
7018 && GET_MODE (SUBREG_REG (dest)) == SImode)
7019 dest = SUBREG_REG (dest);
7021 /* After the above adjustment, the destination must be the same
7022 width as the source. */
7023 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
7026 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
7029 temp = gen_reg_rtx (GET_MODE (dest));
7030 if (GET_MODE (dest) == DImode)
7032 emit_insn (gen_mov_ldl (temp, src, left));
7033 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
7037 emit_insn (gen_mov_lwl (temp, src, left));
7038 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
7043 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
7044 BITPOS and SRC are the operands passed to the expander; the operation
7045 is the equivalent of:
7047 (set (zero_extract DEST WIDTH BITPOS) SRC)
7049 Return true on success. */
7052 mips_expand_ins_as_unaligned_store (rtx dest, rtx src, HOST_WIDE_INT width,
7053 HOST_WIDE_INT bitpos)
7056 enum machine_mode mode;
7058 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
7061 mode = mode_for_size (width, MODE_INT, 0);
7062 src = gen_lowpart (mode, src);
7065 emit_insn (gen_mov_sdl (dest, src, left));
7066 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
7070 emit_insn (gen_mov_swl (dest, src, left));
7071 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
7076 /* Return true if X is a MEM with the same size as MODE. */
7079 mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
7086 size = MEM_SIZE (x);
7087 return size && INTVAL (size) == GET_MODE_SIZE (mode);
7090 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
7091 source of an "ext" instruction or the destination of an "ins"
7092 instruction. OP must be a register operand and the following
7093 conditions must hold:
7095 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
7096 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7097 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7099 Also reject lengths equal to a word as they are better handled
7100 by the move patterns. */
7103 mips_use_ins_ext_p (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos)
7105 if (!ISA_HAS_EXT_INS
7106 || !register_operand (op, VOIDmode)
7107 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
7110 if (!IN_RANGE (width, 1, GET_MODE_BITSIZE (GET_MODE (op)) - 1))
7113 if (bitpos < 0 || bitpos + width > GET_MODE_BITSIZE (GET_MODE (op)))
7119 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
7120 operation if MAXLEN is the maxium length of consecutive bits that
7121 can make up MASK. MODE is the mode of the operation. See
7122 mask_low_and_shift_len for the actual definition. */
7125 mask_low_and_shift_p (enum machine_mode mode, rtx mask, rtx shift, int maxlen)
7127 return IN_RANGE (mask_low_and_shift_len (mode, mask, shift), 1, maxlen);
7130 /* Return true iff OP1 and OP2 are valid operands together for the
7131 *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider,
7132 see the table in the comment before the pattern. */
7135 and_operands_ok (enum machine_mode mode, rtx op1, rtx op2)
7137 return (memory_operand (op1, mode)
7138 ? and_load_operand (op2, mode)
7139 : and_reg_operand (op2, mode));
7142 /* The canonical form of a mask-low-and-shift-left operation is
7143 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
7144 cleared. Thus we need to shift MASK to the right before checking if it
7145 is a valid mask value. MODE is the mode of the operation. If true
7146 return the length of the mask, otherwise return -1. */
7149 mask_low_and_shift_len (enum machine_mode mode, rtx mask, rtx shift)
7151 HOST_WIDE_INT shval;
7153 shval = INTVAL (shift) & (GET_MODE_BITSIZE (mode) - 1);
7154 return exact_log2 ((UINTVAL (mask) >> shval) + 1);
7157 /* Return true if -msplit-addresses is selected and should be honored.
7159 -msplit-addresses is a half-way house between explicit relocations
7160 and the traditional assembler macros. It can split absolute 32-bit
7161 symbolic constants into a high/lo_sum pair but uses macros for other
7164 Like explicit relocation support for REL targets, it relies
7165 on GNU extensions in the assembler and the linker.
7167 Although this code should work for -O0, it has traditionally
7168 been treated as an optimization. */
7171 mips_split_addresses_p (void)
7173 return (TARGET_SPLIT_ADDRESSES
7177 && !ABI_HAS_64BIT_SYMBOLS);
7180 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
7183 mips_init_relocs (void)
7185 memset (mips_split_p, '\0', sizeof (mips_split_p));
7186 memset (mips_split_hi_p, '\0', sizeof (mips_split_hi_p));
7187 memset (mips_hi_relocs, '\0', sizeof (mips_hi_relocs));
7188 memset (mips_lo_relocs, '\0', sizeof (mips_lo_relocs));
7190 if (ABI_HAS_64BIT_SYMBOLS)
7192 if (TARGET_EXPLICIT_RELOCS)
7194 mips_split_p[SYMBOL_64_HIGH] = true;
7195 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
7196 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
7198 mips_split_p[SYMBOL_64_MID] = true;
7199 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
7200 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
7202 mips_split_p[SYMBOL_64_LOW] = true;
7203 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
7204 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
7206 mips_split_p[SYMBOL_ABSOLUTE] = true;
7207 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
7212 if (TARGET_EXPLICIT_RELOCS || mips_split_addresses_p () || TARGET_MIPS16)
7214 mips_split_p[SYMBOL_ABSOLUTE] = true;
7215 mips_hi_relocs[SYMBOL_ABSOLUTE] = "%hi(";
7216 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
7218 mips_lo_relocs[SYMBOL_32_HIGH] = "%hi(";
7224 /* The high part is provided by a pseudo copy of $gp. */
7225 mips_split_p[SYMBOL_GP_RELATIVE] = true;
7226 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gprel(";
7228 else if (TARGET_EXPLICIT_RELOCS)
7229 /* Small data constants are kept whole until after reload,
7230 then lowered by mips_rewrite_small_data. */
7231 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gp_rel(";
7233 if (TARGET_EXPLICIT_RELOCS)
7235 mips_split_p[SYMBOL_GOT_PAGE_OFST] = true;
7238 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
7239 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%got_ofst(";
7243 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
7244 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%lo(";
7247 /* Expose the use of $28 as soon as possible. */
7248 mips_split_hi_p[SYMBOL_GOT_PAGE_OFST] = true;
7252 /* The HIGH and LO_SUM are matched by special .md patterns. */
7253 mips_split_p[SYMBOL_GOT_DISP] = true;
7255 mips_split_p[SYMBOL_GOTOFF_DISP] = true;
7256 mips_hi_relocs[SYMBOL_GOTOFF_DISP] = "%got_hi(";
7257 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_lo(";
7259 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
7260 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
7261 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
7266 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_disp(";
7268 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got(";
7269 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
7271 /* Expose the use of $28 as soon as possible. */
7272 mips_split_p[SYMBOL_GOT_DISP] = true;
7278 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
7279 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
7280 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
7283 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
7284 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
7286 mips_split_p[SYMBOL_DTPREL] = true;
7287 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
7288 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
7290 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
7292 mips_split_p[SYMBOL_TPREL] = true;
7293 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
7294 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
7296 mips_lo_relocs[SYMBOL_HALF] = "%half(";
7299 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
7300 in context CONTEXT. RELOCS is the array of relocations to use. */
7303 mips_print_operand_reloc (FILE *file, rtx op, enum mips_symbol_context context,
7304 const char **relocs)
7306 enum mips_symbol_type symbol_type;
7309 symbol_type = mips_classify_symbolic_expression (op, context);
7310 gcc_assert (relocs[symbol_type]);
7312 fputs (relocs[symbol_type], file);
7313 output_addr_const (file, mips_strip_unspec_address (op));
7314 for (p = relocs[symbol_type]; *p != 0; p++)
7319 /* Start a new block with the given asm switch enabled. If we need
7320 to print a directive, emit PREFIX before it and SUFFIX after it. */
7323 mips_push_asm_switch_1 (struct mips_asm_switch *asm_switch,
7324 const char *prefix, const char *suffix)
7326 if (asm_switch->nesting_level == 0)
7327 fprintf (asm_out_file, "%s.set\tno%s%s", prefix, asm_switch->name, suffix);
7328 asm_switch->nesting_level++;
7331 /* Likewise, but end a block. */
7334 mips_pop_asm_switch_1 (struct mips_asm_switch *asm_switch,
7335 const char *prefix, const char *suffix)
7337 gcc_assert (asm_switch->nesting_level);
7338 asm_switch->nesting_level--;
7339 if (asm_switch->nesting_level == 0)
7340 fprintf (asm_out_file, "%s.set\t%s%s", prefix, asm_switch->name, suffix);
7343 /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1
7344 that either print a complete line or print nothing. */
7347 mips_push_asm_switch (struct mips_asm_switch *asm_switch)
7349 mips_push_asm_switch_1 (asm_switch, "\t", "\n");
7353 mips_pop_asm_switch (struct mips_asm_switch *asm_switch)
7355 mips_pop_asm_switch_1 (asm_switch, "\t", "\n");
7358 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
7359 The punctuation characters are:
7361 '(' Start a nested ".set noreorder" block.
7362 ')' End a nested ".set noreorder" block.
7363 '[' Start a nested ".set noat" block.
7364 ']' End a nested ".set noat" block.
7365 '<' Start a nested ".set nomacro" block.
7366 '>' End a nested ".set nomacro" block.
7367 '*' Behave like %(%< if generating a delayed-branch sequence.
7368 '#' Print a nop if in a ".set noreorder" block.
7369 '/' Like '#', but do nothing within a delayed-branch sequence.
7370 '?' Print "l" if mips_branch_likely is true
7371 '~' Print a nop if mips_branch_likely is true
7372 '.' Print the name of the register with a hard-wired zero (zero or $0).
7373 '@' Print the name of the assembler temporary register (at or $1).
7374 '^' Print the name of the pic call-through register (t9 or $25).
7375 '+' Print the name of the gp register (usually gp or $28).
7376 '$' Print the name of the stack pointer register (sp or $29).
7378 See also mips_init_print_operand_pucnt. */
7381 mips_print_operand_punctuation (FILE *file, int ch)
7386 mips_push_asm_switch_1 (&mips_noreorder, "", "\n\t");
7390 mips_pop_asm_switch_1 (&mips_noreorder, "\n\t", "");
7394 mips_push_asm_switch_1 (&mips_noat, "", "\n\t");
7398 mips_pop_asm_switch_1 (&mips_noat, "\n\t", "");
7402 mips_push_asm_switch_1 (&mips_nomacro, "", "\n\t");
7406 mips_pop_asm_switch_1 (&mips_nomacro, "\n\t", "");
7410 if (final_sequence != 0)
7412 mips_print_operand_punctuation (file, '(');
7413 mips_print_operand_punctuation (file, '<');
7418 if (mips_noreorder.nesting_level > 0)
7419 fputs ("\n\tnop", file);
7423 /* Print an extra newline so that the delayed insn is separated
7424 from the following ones. This looks neater and is consistent
7425 with non-nop delayed sequences. */
7426 if (mips_noreorder.nesting_level > 0 && final_sequence == 0)
7427 fputs ("\n\tnop\n", file);
7431 if (mips_branch_likely)
7436 if (mips_branch_likely)
7437 fputs ("\n\tnop", file);
7441 fputs (reg_names[GP_REG_FIRST + 0], file);
7445 fputs (reg_names[AT_REGNUM], file);
7449 fputs (reg_names[PIC_FUNCTION_ADDR_REGNUM], file);
7453 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
7457 fputs (reg_names[STACK_POINTER_REGNUM], file);
7466 /* Initialize mips_print_operand_punct. */
7469 mips_init_print_operand_punct (void)
7473 for (p = "()[]<>*#/?~.@^+$"; *p; p++)
7474 mips_print_operand_punct[(unsigned char) *p] = true;
7477 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
7478 associated with condition CODE. Print the condition part of the
7482 mips_print_int_branch_condition (FILE *file, enum rtx_code code, int letter)
7496 /* Conveniently, the MIPS names for these conditions are the same
7497 as their RTL equivalents. */
7498 fputs (GET_RTX_NAME (code), file);
7502 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
7507 /* Likewise floating-point branches. */
7510 mips_print_float_branch_condition (FILE *file, enum rtx_code code, int letter)
7515 fputs ("c1f", file);
7519 fputs ("c1t", file);
7523 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
7528 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
7531 mips_print_operand_punct_valid_p (unsigned char code)
7533 return mips_print_operand_punct[code];
7536 /* Implement TARGET_PRINT_OPERAND. The MIPS-specific operand codes are:
7538 'X' Print CONST_INT OP in hexadecimal format.
7539 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
7540 'd' Print CONST_INT OP in decimal.
7541 'm' Print one less than CONST_INT OP in decimal.
7542 'h' Print the high-part relocation associated with OP, after stripping
7544 'R' Print the low-part relocation associated with OP.
7545 'C' Print the integer branch condition for comparison OP.
7546 'N' Print the inverse of the integer branch condition for comparison OP.
7547 'F' Print the FPU branch condition for comparison OP.
7548 'W' Print the inverse of the FPU branch condition for comparison OP.
7549 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
7550 'z' for (eq:?I ...), 'n' for (ne:?I ...).
7551 't' Like 'T', but with the EQ/NE cases reversed
7552 'Y' Print mips_fp_conditions[INTVAL (OP)]
7553 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
7554 'q' Print a DSP accumulator register.
7555 'D' Print the second part of a double-word register or memory operand.
7556 'L' Print the low-order register in a double-word register operand.
7557 'M' Print high-order register in a double-word register operand.
7558 'z' Print $0 if OP is zero, otherwise print OP normally. */
7561 mips_print_operand (FILE *file, rtx op, int letter)
7565 if (mips_print_operand_punct_valid_p (letter))
7567 mips_print_operand_punctuation (file, letter);
7572 code = GET_CODE (op);
7577 if (CONST_INT_P (op))
7578 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
7580 output_operand_lossage ("invalid use of '%%%c'", letter);
7584 if (CONST_INT_P (op))
7585 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op) & 0xffff);
7587 output_operand_lossage ("invalid use of '%%%c'", letter);
7591 if (CONST_INT_P (op))
7592 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op));
7594 output_operand_lossage ("invalid use of '%%%c'", letter);
7598 if (CONST_INT_P (op))
7599 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op) - 1);
7601 output_operand_lossage ("invalid use of '%%%c'", letter);
7607 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_hi_relocs);
7611 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_lo_relocs);
7615 mips_print_int_branch_condition (file, code, letter);
7619 mips_print_int_branch_condition (file, reverse_condition (code), letter);
7623 mips_print_float_branch_condition (file, code, letter);
7627 mips_print_float_branch_condition (file, reverse_condition (code),
7634 int truth = (code == NE) == (letter == 'T');
7635 fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
7640 if (code == CONST_INT && UINTVAL (op) < ARRAY_SIZE (mips_fp_conditions))
7641 fputs (mips_fp_conditions[UINTVAL (op)], file);
7643 output_operand_lossage ("'%%%c' is not a valid operand prefix",
7650 mips_print_operand (file, op, 0);
7656 if (code == REG && MD_REG_P (REGNO (op)))
7657 fprintf (file, "$ac0");
7658 else if (code == REG && DSP_ACC_REG_P (REGNO (op)))
7659 fprintf (file, "$ac%c", reg_names[REGNO (op)][3]);
7661 output_operand_lossage ("invalid use of '%%%c'", letter);
7669 unsigned int regno = REGNO (op);
7670 if ((letter == 'M' && TARGET_LITTLE_ENDIAN)
7671 || (letter == 'L' && TARGET_BIG_ENDIAN)
7674 else if (letter && letter != 'z' && letter != 'M' && letter != 'L')
7675 output_operand_lossage ("invalid use of '%%%c'", letter);
7676 /* We need to print $0 .. $31 for COP0 registers. */
7677 if (COP0_REG_P (regno))
7678 fprintf (file, "$%s", ®_names[regno][4]);
7680 fprintf (file, "%s", reg_names[regno]);
7686 output_address (plus_constant (XEXP (op, 0), 4));
7687 else if (letter && letter != 'z')
7688 output_operand_lossage ("invalid use of '%%%c'", letter);
7690 output_address (XEXP (op, 0));
7694 if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
7695 fputs (reg_names[GP_REG_FIRST], file);
7696 else if (letter && letter != 'z')
7697 output_operand_lossage ("invalid use of '%%%c'", letter);
7698 else if (CONST_GP_P (op))
7699 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
7701 output_addr_const (file, mips_strip_unspec_address (op));
7707 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
7710 mips_print_operand_address (FILE *file, rtx x)
7712 struct mips_address_info addr;
7714 if (mips_classify_address (&addr, x, word_mode, true))
7718 mips_print_operand (file, addr.offset, 0);
7719 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
7722 case ADDRESS_LO_SUM:
7723 mips_print_operand_reloc (file, addr.offset, SYMBOL_CONTEXT_MEM,
7725 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
7728 case ADDRESS_CONST_INT:
7729 output_addr_const (file, x);
7730 fprintf (file, "(%s)", reg_names[GP_REG_FIRST]);
7733 case ADDRESS_SYMBOLIC:
7734 output_addr_const (file, mips_strip_unspec_address (x));
7740 /* Implement TARGET_ENCODE_SECTION_INFO. */
7743 mips_encode_section_info (tree decl, rtx rtl, int first)
7745 default_encode_section_info (decl, rtl, first);
7747 if (TREE_CODE (decl) == FUNCTION_DECL)
7749 rtx symbol = XEXP (rtl, 0);
7750 tree type = TREE_TYPE (decl);
7752 /* Encode whether the symbol is short or long. */
7753 if ((TARGET_LONG_CALLS && !mips_near_type_p (type))
7754 || mips_far_type_p (type))
7755 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
7759 /* Implement TARGET_SELECT_RTX_SECTION. */
7762 mips_select_rtx_section (enum machine_mode mode, rtx x,
7763 unsigned HOST_WIDE_INT align)
7765 /* ??? Consider using mergeable small data sections. */
7766 if (mips_rtx_constant_in_small_data_p (mode))
7767 return get_named_section (NULL, ".sdata", 0);
7769 return default_elf_select_rtx_section (mode, x, align);
7772 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
7774 The complication here is that, with the combination TARGET_ABICALLS
7775 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
7776 absolute addresses, and should therefore not be included in the
7777 read-only part of a DSO. Handle such cases by selecting a normal
7778 data section instead of a read-only one. The logic apes that in
7779 default_function_rodata_section. */
7782 mips_function_rodata_section (tree decl)
7784 if (!TARGET_ABICALLS || TARGET_ABSOLUTE_ABICALLS || TARGET_GPWORD)
7785 return default_function_rodata_section (decl);
7787 if (decl && DECL_SECTION_NAME (decl))
7789 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7790 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
7792 char *rname = ASTRDUP (name);
7794 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
7796 else if (flag_function_sections
7797 && flag_data_sections
7798 && strncmp (name, ".text.", 6) == 0)
7800 char *rname = ASTRDUP (name);
7801 memcpy (rname + 1, "data", 4);
7802 return get_section (rname, SECTION_WRITE, decl);
7805 return data_section;
7808 /* Implement TARGET_IN_SMALL_DATA_P. */
7811 mips_in_small_data_p (const_tree decl)
7813 unsigned HOST_WIDE_INT size;
7815 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
7818 /* We don't yet generate small-data references for -mabicalls
7819 or VxWorks RTP code. See the related -G handling in
7820 mips_option_override. */
7821 if (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
7824 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
7828 /* Reject anything that isn't in a known small-data section. */
7829 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7830 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
7833 /* If a symbol is defined externally, the assembler will use the
7834 usual -G rules when deciding how to implement macros. */
7835 if (mips_lo_relocs[SYMBOL_GP_RELATIVE] || !DECL_EXTERNAL (decl))
7838 else if (TARGET_EMBEDDED_DATA)
7840 /* Don't put constants into the small data section: we want them
7841 to be in ROM rather than RAM. */
7842 if (TREE_CODE (decl) != VAR_DECL)
7845 if (TREE_READONLY (decl)
7846 && !TREE_SIDE_EFFECTS (decl)
7847 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
7851 /* Enforce -mlocal-sdata. */
7852 if (!TARGET_LOCAL_SDATA && !TREE_PUBLIC (decl))
7855 /* Enforce -mextern-sdata. */
7856 if (!TARGET_EXTERN_SDATA && DECL_P (decl))
7858 if (DECL_EXTERNAL (decl))
7860 if (DECL_COMMON (decl) && DECL_INITIAL (decl) == NULL)
7864 /* We have traditionally not treated zero-sized objects as small data,
7865 so this is now effectively part of the ABI. */
7866 size = int_size_in_bytes (TREE_TYPE (decl));
7867 return size > 0 && size <= mips_small_data_threshold;
7870 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
7871 anchors for small data: the GP register acts as an anchor in that
7872 case. We also don't want to use them for PC-relative accesses,
7873 where the PC acts as an anchor. */
7876 mips_use_anchors_for_symbol_p (const_rtx symbol)
7878 switch (mips_classify_symbol (symbol, SYMBOL_CONTEXT_MEM))
7880 case SYMBOL_PC_RELATIVE:
7881 case SYMBOL_GP_RELATIVE:
7885 return default_use_anchors_for_symbol_p (symbol);
7889 /* The MIPS debug format wants all automatic variables and arguments
7890 to be in terms of the virtual frame pointer (stack pointer before
7891 any adjustment in the function), while the MIPS 3.0 linker wants
7892 the frame pointer to be the stack pointer after the initial
7893 adjustment. So, we do the adjustment here. The arg pointer (which
7894 is eliminated) points to the virtual frame pointer, while the frame
7895 pointer (which may be eliminated) points to the stack pointer after
7896 the initial adjustments. */
7899 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
7901 rtx offset2 = const0_rtx;
7902 rtx reg = eliminate_constant_term (addr, &offset2);
7905 offset = INTVAL (offset2);
7907 if (reg == stack_pointer_rtx
7908 || reg == frame_pointer_rtx
7909 || reg == hard_frame_pointer_rtx)
7911 offset -= cfun->machine->frame.total_size;
7912 if (reg == hard_frame_pointer_rtx)
7913 offset += cfun->machine->frame.hard_frame_pointer_offset;
7916 /* sdbout_parms does not want this to crash for unrecognized cases. */
7918 else if (reg != arg_pointer_rtx)
7919 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
7926 /* Implement ASM_OUTPUT_EXTERNAL. */
7929 mips_output_external (FILE *file, tree decl, const char *name)
7931 default_elf_asm_output_external (file, decl, name);
7933 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
7934 set in order to avoid putting out names that are never really
7936 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
7938 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
7940 /* When using assembler macros, emit .extern directives for
7941 all small-data externs so that the assembler knows how
7944 In most cases it would be safe (though pointless) to emit
7945 .externs for other symbols too. One exception is when an
7946 object is within the -G limit but declared by the user to
7947 be in a section other than .sbss or .sdata. */
7948 fputs ("\t.extern\t", file);
7949 assemble_name (file, name);
7950 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n",
7951 int_size_in_bytes (TREE_TYPE (decl)));
7956 /* Implement TARGET_ASM_OUTPUT_SOURCE_FILENAME. */
7959 mips_output_filename (FILE *stream, const char *name)
7961 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
7963 if (write_symbols == DWARF2_DEBUG)
7965 else if (mips_output_filename_first_time)
7967 mips_output_filename_first_time = 0;
7968 num_source_filenames += 1;
7969 current_function_file = name;
7970 fprintf (stream, "\t.file\t%d ", num_source_filenames);
7971 output_quoted_string (stream, name);
7972 putc ('\n', stream);
7974 /* If we are emitting stabs, let dbxout.c handle this (except for
7975 the mips_output_filename_first_time case). */
7976 else if (write_symbols == DBX_DEBUG)
7978 else if (name != current_function_file
7979 && strcmp (name, current_function_file) != 0)
7981 num_source_filenames += 1;
7982 current_function_file = name;
7983 fprintf (stream, "\t.file\t%d ", num_source_filenames);
7984 output_quoted_string (stream, name);
7985 putc ('\n', stream);
7989 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
7991 static void ATTRIBUTE_UNUSED
7992 mips_output_dwarf_dtprel (FILE *file, int size, rtx x)
7997 fputs ("\t.dtprelword\t", file);
8001 fputs ("\t.dtpreldword\t", file);
8007 output_addr_const (file, x);
8008 fputs ("+0x8000", file);
8011 /* Implement TARGET_DWARF_REGISTER_SPAN. */
8014 mips_dwarf_register_span (rtx reg)
8017 enum machine_mode mode;
8019 /* By default, GCC maps increasing register numbers to increasing
8020 memory locations, but paired FPRs are always little-endian,
8021 regardless of the prevailing endianness. */
8022 mode = GET_MODE (reg);
8023 if (FP_REG_P (REGNO (reg))
8024 && TARGET_BIG_ENDIAN
8025 && MAX_FPRS_PER_FMT > 1
8026 && GET_MODE_SIZE (mode) > UNITS_PER_FPREG)
8028 gcc_assert (GET_MODE_SIZE (mode) == UNITS_PER_HWFPVALUE);
8029 high = mips_subword (reg, true);
8030 low = mips_subword (reg, false);
8031 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, high, low));
8037 /* Implement ASM_OUTPUT_ASCII. */
8040 mips_output_ascii (FILE *stream, const char *string, size_t len)
8046 fprintf (stream, "\t.ascii\t\"");
8047 for (i = 0; i < len; i++)
8051 c = (unsigned char) string[i];
8054 if (c == '\\' || c == '\"')
8056 putc ('\\', stream);
8064 fprintf (stream, "\\%03o", c);
8068 if (cur_pos > 72 && i+1 < len)
8071 fprintf (stream, "\"\n\t.ascii\t\"");
8074 fprintf (stream, "\"\n");
8077 /* Emit either a label, .comm, or .lcomm directive. When using assembler
8078 macros, mark the symbol as written so that mips_asm_output_external
8079 won't emit an .extern for it. STREAM is the output file, NAME is the
8080 name of the symbol, INIT_STRING is the string that should be written
8081 before the symbol and FINAL_STRING is the string that should be
8082 written after it. FINAL_STRING is a printf format that consumes the
8083 remaining arguments. */
8086 mips_declare_object (FILE *stream, const char *name, const char *init_string,
8087 const char *final_string, ...)
8091 fputs (init_string, stream);
8092 assemble_name (stream, name);
8093 va_start (ap, final_string);
8094 vfprintf (stream, final_string, ap);
8097 if (!TARGET_EXPLICIT_RELOCS)
8099 tree name_tree = get_identifier (name);
8100 TREE_ASM_WRITTEN (name_tree) = 1;
8104 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
8105 NAME is the name of the object and ALIGN is the required alignment
8106 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
8107 alignment argument. */
8110 mips_declare_common_object (FILE *stream, const char *name,
8111 const char *init_string,
8112 unsigned HOST_WIDE_INT size,
8113 unsigned int align, bool takes_alignment_p)
8115 if (!takes_alignment_p)
8117 size += (align / BITS_PER_UNIT) - 1;
8118 size -= size % (align / BITS_PER_UNIT);
8119 mips_declare_object (stream, name, init_string,
8120 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
8123 mips_declare_object (stream, name, init_string,
8124 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
8125 size, align / BITS_PER_UNIT);
8128 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
8129 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
8132 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
8133 unsigned HOST_WIDE_INT size,
8136 /* If the target wants uninitialized const declarations in
8137 .rdata then don't put them in .comm. */
8138 if (TARGET_EMBEDDED_DATA
8139 && TARGET_UNINIT_CONST_IN_RODATA
8140 && TREE_CODE (decl) == VAR_DECL
8141 && TREE_READONLY (decl)
8142 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
8144 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
8145 targetm.asm_out.globalize_label (stream, name);
8147 switch_to_section (readonly_data_section);
8148 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
8149 mips_declare_object (stream, name, "",
8150 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
8154 mips_declare_common_object (stream, name, "\n\t.comm\t",
8158 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8159 extern int size_directive_output;
8161 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
8162 definitions except that it uses mips_declare_object to emit the label. */
8165 mips_declare_object_name (FILE *stream, const char *name,
8166 tree decl ATTRIBUTE_UNUSED)
8168 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8169 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
8172 size_directive_output = 0;
8173 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
8177 size_directive_output = 1;
8178 size = int_size_in_bytes (TREE_TYPE (decl));
8179 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8182 mips_declare_object (stream, name, "", ":\n");
8185 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
8188 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
8192 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
8193 if (!flag_inhibit_size_directive
8194 && DECL_SIZE (decl) != 0
8197 && DECL_INITIAL (decl) == error_mark_node
8198 && !size_directive_output)
8202 size_directive_output = 1;
8203 size = int_size_in_bytes (TREE_TYPE (decl));
8204 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8209 /* Return the FOO in the name of the ".mdebug.FOO" section associated
8210 with the current ABI. */
8213 mips_mdebug_abi_name (void)
8226 return TARGET_64BIT ? "eabi64" : "eabi32";
8232 /* Implement TARGET_ASM_FILE_START. */
8235 mips_file_start (void)
8237 default_file_start ();
8239 /* Generate a special section to describe the ABI switches used to
8240 produce the resultant binary. This is unnecessary on IRIX and
8241 causes unwanted warnings from the native linker. */
8244 /* Record the ABI itself. Modern versions of binutils encode
8245 this information in the ELF header flags, but GDB needs the
8246 information in order to correctly debug binaries produced by
8247 older binutils. See the function mips_gdbarch_init in
8249 fprintf (asm_out_file, "\t.section .mdebug.%s\n\t.previous\n",
8250 mips_mdebug_abi_name ());
8252 /* There is no ELF header flag to distinguish long32 forms of the
8253 EABI from long64 forms. Emit a special section to help tools
8254 such as GDB. Do the same for o64, which is sometimes used with
8256 if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
8257 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n"
8258 "\t.previous\n", TARGET_LONG64 ? 64 : 32);
8260 #ifdef HAVE_AS_GNU_ATTRIBUTE
8264 /* No floating-point operations, -mno-float. */
8265 if (TARGET_NO_FLOAT)
8267 /* Soft-float code, -msoft-float. */
8268 else if (!TARGET_HARD_FLOAT_ABI)
8270 /* Single-float code, -msingle-float. */
8271 else if (!TARGET_DOUBLE_FLOAT)
8273 /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64. */
8274 else if (!TARGET_64BIT && TARGET_FLOAT64)
8276 /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */
8280 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n", attr);
8285 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
8286 if (TARGET_ABICALLS)
8288 fprintf (asm_out_file, "\t.abicalls\n");
8289 if (TARGET_ABICALLS_PIC0)
8290 fprintf (asm_out_file, "\t.option\tpic0\n");
8293 if (flag_verbose_asm)
8294 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
8296 mips_small_data_threshold, mips_arch_info->name, mips_isa);
8299 /* Make the last instruction frame-related and note that it performs
8300 the operation described by FRAME_PATTERN. */
8303 mips_set_frame_expr (rtx frame_pattern)
8307 insn = get_last_insn ();
8308 RTX_FRAME_RELATED_P (insn) = 1;
8309 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
8314 /* Return a frame-related rtx that stores REG at MEM.
8315 REG must be a single register. */
8318 mips_frame_set (rtx mem, rtx reg)
8322 /* If we're saving the return address register and the DWARF return
8323 address column differs from the hard register number, adjust the
8324 note reg to refer to the former. */
8325 if (REGNO (reg) == RETURN_ADDR_REGNUM
8326 && DWARF_FRAME_RETURN_COLUMN != RETURN_ADDR_REGNUM)
8327 reg = gen_rtx_REG (GET_MODE (reg), DWARF_FRAME_RETURN_COLUMN);
8329 set = gen_rtx_SET (VOIDmode, mem, reg);
8330 RTX_FRAME_RELATED_P (set) = 1;
8335 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
8336 mips16e_s2_s8_regs[X], it must also save the registers in indexes
8337 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
8338 static const unsigned char mips16e_s2_s8_regs[] = {
8339 30, 23, 22, 21, 20, 19, 18
8341 static const unsigned char mips16e_a0_a3_regs[] = {
8345 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
8346 ordered from the uppermost in memory to the lowest in memory. */
8347 static const unsigned char mips16e_save_restore_regs[] = {
8348 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
8351 /* Return the index of the lowest X in the range [0, SIZE) for which
8352 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
8355 mips16e_find_first_register (unsigned int mask, const unsigned char *regs,
8360 for (i = 0; i < size; i++)
8361 if (BITSET_P (mask, regs[i]))
8367 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
8368 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
8369 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
8370 is true for all indexes (X, SIZE). */
8373 mips16e_mask_registers (unsigned int *mask_ptr, const unsigned char *regs,
8374 unsigned int size, unsigned int *num_regs_ptr)
8378 i = mips16e_find_first_register (*mask_ptr, regs, size);
8379 for (i++; i < size; i++)
8380 if (!BITSET_P (*mask_ptr, regs[i]))
8383 *mask_ptr |= 1 << regs[i];
8387 /* Return a simplified form of X using the register values in REG_VALUES.
8388 REG_VALUES[R] is the last value assigned to hard register R, or null
8389 if R has not been modified.
8391 This function is rather limited, but is good enough for our purposes. */
8394 mips16e_collect_propagate_value (rtx x, rtx *reg_values)
8396 x = avoid_constant_pool_reference (x);
8400 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
8401 return simplify_gen_unary (GET_CODE (x), GET_MODE (x),
8402 x0, GET_MODE (XEXP (x, 0)));
8405 if (ARITHMETIC_P (x))
8407 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
8408 rtx x1 = mips16e_collect_propagate_value (XEXP (x, 1), reg_values);
8409 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), x0, x1);
8413 && reg_values[REGNO (x)]
8414 && !rtx_unstable_p (reg_values[REGNO (x)]))
8415 return reg_values[REGNO (x)];
8420 /* Return true if (set DEST SRC) stores an argument register into its
8421 caller-allocated save slot, storing the number of that argument
8422 register in *REGNO_PTR if so. REG_VALUES is as for
8423 mips16e_collect_propagate_value. */
8426 mips16e_collect_argument_save_p (rtx dest, rtx src, rtx *reg_values,
8427 unsigned int *regno_ptr)
8429 unsigned int argno, regno;
8430 HOST_WIDE_INT offset, required_offset;
8433 /* Check that this is a word-mode store. */
8434 if (!MEM_P (dest) || !REG_P (src) || GET_MODE (dest) != word_mode)
8437 /* Check that the register being saved is an unmodified argument
8439 regno = REGNO (src);
8440 if (!IN_RANGE (regno, GP_ARG_FIRST, GP_ARG_LAST) || reg_values[regno])
8442 argno = regno - GP_ARG_FIRST;
8444 /* Check whether the address is an appropriate stack-pointer or
8445 frame-pointer access. */
8446 addr = mips16e_collect_propagate_value (XEXP (dest, 0), reg_values);
8447 mips_split_plus (addr, &base, &offset);
8448 required_offset = cfun->machine->frame.total_size + argno * UNITS_PER_WORD;
8449 if (base == hard_frame_pointer_rtx)
8450 required_offset -= cfun->machine->frame.hard_frame_pointer_offset;
8451 else if (base != stack_pointer_rtx)
8453 if (offset != required_offset)
8460 /* A subroutine of mips_expand_prologue, called only when generating
8461 MIPS16e SAVE instructions. Search the start of the function for any
8462 instructions that save argument registers into their caller-allocated
8463 save slots. Delete such instructions and return a value N such that
8464 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
8465 instructions redundant. */
8468 mips16e_collect_argument_saves (void)
8470 rtx reg_values[FIRST_PSEUDO_REGISTER];
8471 rtx insn, next, set, dest, src;
8472 unsigned int nargs, regno;
8474 push_topmost_sequence ();
8476 memset (reg_values, 0, sizeof (reg_values));
8477 for (insn = get_insns (); insn; insn = next)
8479 next = NEXT_INSN (insn);
8480 if (NOTE_P (insn) || DEBUG_INSN_P (insn))
8486 set = PATTERN (insn);
8487 if (GET_CODE (set) != SET)
8490 dest = SET_DEST (set);
8491 src = SET_SRC (set);
8492 if (mips16e_collect_argument_save_p (dest, src, reg_values, ®no))
8494 if (!BITSET_P (cfun->machine->frame.mask, regno))
8497 nargs = MAX (nargs, (regno - GP_ARG_FIRST) + 1);
8500 else if (REG_P (dest) && GET_MODE (dest) == word_mode)
8501 reg_values[REGNO (dest)]
8502 = mips16e_collect_propagate_value (src, reg_values);
8506 pop_topmost_sequence ();
8511 /* Return a move between register REGNO and memory location SP + OFFSET.
8512 Make the move a load if RESTORE_P, otherwise make it a frame-related
8516 mips16e_save_restore_reg (bool restore_p, HOST_WIDE_INT offset,
8521 mem = gen_frame_mem (SImode, plus_constant (stack_pointer_rtx, offset));
8522 reg = gen_rtx_REG (SImode, regno);
8524 ? gen_rtx_SET (VOIDmode, reg, mem)
8525 : mips_frame_set (mem, reg));
8528 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
8529 The instruction must:
8531 - Allocate or deallocate SIZE bytes in total; SIZE is known
8534 - Save or restore as many registers in *MASK_PTR as possible.
8535 The instruction saves the first registers at the top of the
8536 allocated area, with the other registers below it.
8538 - Save NARGS argument registers above the allocated area.
8540 (NARGS is always zero if RESTORE_P.)
8542 The SAVE and RESTORE instructions cannot save and restore all general
8543 registers, so there may be some registers left over for the caller to
8544 handle. Destructively modify *MASK_PTR so that it contains the registers
8545 that still need to be saved or restored. The caller can save these
8546 registers in the memory immediately below *OFFSET_PTR, which is a
8547 byte offset from the bottom of the allocated stack area. */
8550 mips16e_build_save_restore (bool restore_p, unsigned int *mask_ptr,
8551 HOST_WIDE_INT *offset_ptr, unsigned int nargs,
8555 HOST_WIDE_INT offset, top_offset;
8556 unsigned int i, regno;
8559 gcc_assert (cfun->machine->frame.num_fp == 0);
8561 /* Calculate the number of elements in the PARALLEL. We need one element
8562 for the stack adjustment, one for each argument register save, and one
8563 for each additional register move. */
8565 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
8566 if (BITSET_P (*mask_ptr, mips16e_save_restore_regs[i]))
8569 /* Create the final PARALLEL. */
8570 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (n));
8573 /* Add the stack pointer adjustment. */
8574 set = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8575 plus_constant (stack_pointer_rtx,
8576 restore_p ? size : -size));
8577 RTX_FRAME_RELATED_P (set) = 1;
8578 XVECEXP (pattern, 0, n++) = set;
8580 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8581 top_offset = restore_p ? size : 0;
8583 /* Save the arguments. */
8584 for (i = 0; i < nargs; i++)
8586 offset = top_offset + i * UNITS_PER_WORD;
8587 set = mips16e_save_restore_reg (restore_p, offset, GP_ARG_FIRST + i);
8588 XVECEXP (pattern, 0, n++) = set;
8591 /* Then fill in the other register moves. */
8592 offset = top_offset;
8593 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
8595 regno = mips16e_save_restore_regs[i];
8596 if (BITSET_P (*mask_ptr, regno))
8598 offset -= UNITS_PER_WORD;
8599 set = mips16e_save_restore_reg (restore_p, offset, regno);
8600 XVECEXP (pattern, 0, n++) = set;
8601 *mask_ptr &= ~(1 << regno);
8605 /* Tell the caller what offset it should use for the remaining registers. */
8606 *offset_ptr = size + (offset - top_offset);
8608 gcc_assert (n == XVECLEN (pattern, 0));
8613 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
8614 pointer. Return true if PATTERN matches the kind of instruction
8615 generated by mips16e_build_save_restore. If INFO is nonnull,
8616 initialize it when returning true. */
8619 mips16e_save_restore_pattern_p (rtx pattern, HOST_WIDE_INT adjust,
8620 struct mips16e_save_restore_info *info)
8622 unsigned int i, nargs, mask, extra;
8623 HOST_WIDE_INT top_offset, save_offset, offset;
8624 rtx set, reg, mem, base;
8627 if (!GENERATE_MIPS16E_SAVE_RESTORE)
8630 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8631 top_offset = adjust > 0 ? adjust : 0;
8633 /* Interpret all other members of the PARALLEL. */
8634 save_offset = top_offset - UNITS_PER_WORD;
8638 for (n = 1; n < XVECLEN (pattern, 0); n++)
8640 /* Check that we have a SET. */
8641 set = XVECEXP (pattern, 0, n);
8642 if (GET_CODE (set) != SET)
8645 /* Check that the SET is a load (if restoring) or a store
8647 mem = adjust > 0 ? SET_SRC (set) : SET_DEST (set);
8651 /* Check that the address is the sum of the stack pointer and a
8652 possibly-zero constant offset. */
8653 mips_split_plus (XEXP (mem, 0), &base, &offset);
8654 if (base != stack_pointer_rtx)
8657 /* Check that SET's other operand is a register. */
8658 reg = adjust > 0 ? SET_DEST (set) : SET_SRC (set);
8662 /* Check for argument saves. */
8663 if (offset == top_offset + nargs * UNITS_PER_WORD
8664 && REGNO (reg) == GP_ARG_FIRST + nargs)
8666 else if (offset == save_offset)
8668 while (mips16e_save_restore_regs[i++] != REGNO (reg))
8669 if (i == ARRAY_SIZE (mips16e_save_restore_regs))
8672 mask |= 1 << REGNO (reg);
8673 save_offset -= UNITS_PER_WORD;
8679 /* Check that the restrictions on register ranges are met. */
8681 mips16e_mask_registers (&mask, mips16e_s2_s8_regs,
8682 ARRAY_SIZE (mips16e_s2_s8_regs), &extra);
8683 mips16e_mask_registers (&mask, mips16e_a0_a3_regs,
8684 ARRAY_SIZE (mips16e_a0_a3_regs), &extra);
8688 /* Make sure that the topmost argument register is not saved twice.
8689 The checks above ensure that the same is then true for the other
8690 argument registers. */
8691 if (nargs > 0 && BITSET_P (mask, GP_ARG_FIRST + nargs - 1))
8694 /* Pass back information, if requested. */
8697 info->nargs = nargs;
8699 info->size = (adjust > 0 ? adjust : -adjust);
8705 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
8706 for the register range [MIN_REG, MAX_REG]. Return a pointer to
8707 the null terminator. */
8710 mips16e_add_register_range (char *s, unsigned int min_reg,
8711 unsigned int max_reg)
8713 if (min_reg != max_reg)
8714 s += sprintf (s, ",%s-%s", reg_names[min_reg], reg_names[max_reg]);
8716 s += sprintf (s, ",%s", reg_names[min_reg]);
8720 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
8721 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
8724 mips16e_output_save_restore (rtx pattern, HOST_WIDE_INT adjust)
8726 static char buffer[300];
8728 struct mips16e_save_restore_info info;
8729 unsigned int i, end;
8732 /* Parse the pattern. */
8733 if (!mips16e_save_restore_pattern_p (pattern, adjust, &info))
8736 /* Add the mnemonic. */
8737 s = strcpy (buffer, adjust > 0 ? "restore\t" : "save\t");
8740 /* Save the arguments. */
8742 s += sprintf (s, "%s-%s,", reg_names[GP_ARG_FIRST],
8743 reg_names[GP_ARG_FIRST + info.nargs - 1]);
8744 else if (info.nargs == 1)
8745 s += sprintf (s, "%s,", reg_names[GP_ARG_FIRST]);
8747 /* Emit the amount of stack space to allocate or deallocate. */
8748 s += sprintf (s, "%d", (int) info.size);
8750 /* Save or restore $16. */
8751 if (BITSET_P (info.mask, 16))
8752 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 16]);
8754 /* Save or restore $17. */
8755 if (BITSET_P (info.mask, 17))
8756 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 17]);
8758 /* Save or restore registers in the range $s2...$s8, which
8759 mips16e_s2_s8_regs lists in decreasing order. Note that this
8760 is a software register range; the hardware registers are not
8761 numbered consecutively. */
8762 end = ARRAY_SIZE (mips16e_s2_s8_regs);
8763 i = mips16e_find_first_register (info.mask, mips16e_s2_s8_regs, end);
8765 s = mips16e_add_register_range (s, mips16e_s2_s8_regs[end - 1],
8766 mips16e_s2_s8_regs[i]);
8768 /* Save or restore registers in the range $a0...$a3. */
8769 end = ARRAY_SIZE (mips16e_a0_a3_regs);
8770 i = mips16e_find_first_register (info.mask, mips16e_a0_a3_regs, end);
8772 s = mips16e_add_register_range (s, mips16e_a0_a3_regs[i],
8773 mips16e_a0_a3_regs[end - 1]);
8775 /* Save or restore $31. */
8776 if (BITSET_P (info.mask, RETURN_ADDR_REGNUM))
8777 s += sprintf (s, ",%s", reg_names[RETURN_ADDR_REGNUM]);
8782 /* Return true if the current function returns its value in a floating-point
8783 register in MIPS16 mode. */
8786 mips16_cfun_returns_in_fpr_p (void)
8788 tree return_type = DECL_RESULT (current_function_decl);
8789 return (TARGET_MIPS16
8790 && TARGET_HARD_FLOAT_ABI
8791 && !aggregate_value_p (return_type, current_function_decl)
8792 && mips_return_mode_in_fpr_p (DECL_MODE (return_type)));
8795 /* Return true if predicate PRED is true for at least one instruction.
8796 Cache the result in *CACHE, and assume that the result is true
8797 if *CACHE is already true. */
8800 mips_find_gp_ref (bool *cache, bool (*pred) (rtx))
8806 push_topmost_sequence ();
8807 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8808 if (USEFUL_INSN_P (insn) && pred (insn))
8813 pop_topmost_sequence ();
8818 /* Return true if INSN refers to the global pointer in an "inflexible" way.
8819 See mips_cfun_has_inflexible_gp_ref_p for details. */
8822 mips_insn_has_inflexible_gp_ref_p (rtx insn)
8824 /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE
8825 indicate that the target could be a traditional MIPS
8826 lazily-binding stub. */
8827 return find_reg_fusage (insn, USE, pic_offset_table_rtx);
8830 /* Return true if the current function refers to the global pointer
8831 in a way that forces $28 to be valid. This means that we can't
8832 change the choice of global pointer, even for NewABI code.
8834 One example of this (and one which needs several checks) is that
8835 $28 must be valid when calling traditional MIPS lazy-binding stubs.
8836 (This restriction does not apply to PLTs.) */
8839 mips_cfun_has_inflexible_gp_ref_p (void)
8841 /* If the function has a nonlocal goto, $28 must hold the correct
8842 global pointer for the target function. That is, the target
8843 of the goto implicitly uses $28. */
8844 if (crtl->has_nonlocal_goto)
8847 if (TARGET_ABICALLS_PIC2)
8849 /* Symbolic accesses implicitly use the global pointer unless
8850 -mexplicit-relocs is in effect. JAL macros to symbolic addresses
8851 might go to traditional MIPS lazy-binding stubs. */
8852 if (!TARGET_EXPLICIT_RELOCS)
8855 /* FUNCTION_PROFILER includes a JAL to _mcount, which again
8856 can be lazily-bound. */
8860 /* MIPS16 functions that return in FPRs need to call an
8861 external libgcc routine. This call is only made explict
8862 during mips_expand_epilogue, and it too might be lazily bound. */
8863 if (mips16_cfun_returns_in_fpr_p ())
8867 return mips_find_gp_ref (&cfun->machine->has_inflexible_gp_insn_p,
8868 mips_insn_has_inflexible_gp_ref_p);
8871 /* Return true if INSN refers to the global pointer in a "flexible" way.
8872 See mips_cfun_has_flexible_gp_ref_p for details. */
8875 mips_insn_has_flexible_gp_ref_p (rtx insn)
8877 return (get_attr_got (insn) != GOT_UNSET
8878 || mips_small_data_pattern_p (PATTERN (insn))
8879 || reg_overlap_mentioned_p (pic_offset_table_rtx, PATTERN (insn)));
8882 /* Return true if the current function references the global pointer,
8883 but if those references do not inherently require the global pointer
8884 to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */
8887 mips_cfun_has_flexible_gp_ref_p (void)
8889 /* Reload can sometimes introduce constant pool references
8890 into a function that otherwise didn't need them. For example,
8891 suppose we have an instruction like:
8893 (set (reg:DF R1) (float:DF (reg:SI R2)))
8895 If R2 turns out to be a constant such as 1, the instruction may
8896 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
8897 the option of using this constant if R2 doesn't get allocated
8900 In cases like these, reload will have added the constant to the
8901 pool but no instruction will yet refer to it. */
8902 if (TARGET_ABICALLS_PIC2 && !reload_completed && crtl->uses_const_pool)
8905 return mips_find_gp_ref (&cfun->machine->has_flexible_gp_insn_p,
8906 mips_insn_has_flexible_gp_ref_p);
8909 /* Return the register that should be used as the global pointer
8910 within this function. Return INVALID_REGNUM if the function
8911 doesn't need a global pointer. */
8914 mips_global_pointer (void)
8918 /* $gp is always available unless we're using a GOT. */
8919 if (!TARGET_USE_GOT)
8920 return GLOBAL_POINTER_REGNUM;
8922 /* If there are inflexible references to $gp, we must use the
8923 standard register. */
8924 if (mips_cfun_has_inflexible_gp_ref_p ())
8925 return GLOBAL_POINTER_REGNUM;
8927 /* If there are no current references to $gp, then the only uses
8928 we can introduce later are those involved in long branches. */
8929 if (TARGET_ABSOLUTE_JUMPS && !mips_cfun_has_flexible_gp_ref_p ())
8930 return INVALID_REGNUM;
8932 /* If the global pointer is call-saved, try to use a call-clobbered
8934 if (TARGET_CALL_SAVED_GP && current_function_is_leaf)
8935 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
8936 if (!df_regs_ever_live_p (regno)
8937 && call_really_used_regs[regno]
8938 && !fixed_regs[regno]
8939 && regno != PIC_FUNCTION_ADDR_REGNUM)
8942 return GLOBAL_POINTER_REGNUM;
8945 /* Return true if the current function's prologue must load the global
8946 pointer value into pic_offset_table_rtx and store the same value in
8947 the function's cprestore slot (if any).
8949 One problem we have to deal with is that, when emitting GOT-based
8950 position independent code, long-branch sequences will need to load
8951 the address of the branch target from the GOT. We don't know until
8952 the very end of compilation whether (and where) the function needs
8953 long branches, so we must ensure that _any_ branch can access the
8954 global pointer in some form. However, we do not want to pessimize
8955 the usual case in which all branches are short.
8957 We handle this as follows:
8959 (1) During reload, we set cfun->machine->global_pointer to
8960 INVALID_REGNUM if we _know_ that the current function
8961 doesn't need a global pointer. This is only valid if
8962 long branches don't need the GOT.
8964 Otherwise, we assume that we might need a global pointer
8965 and pick an appropriate register.
8967 (2) If cfun->machine->global_pointer != INVALID_REGNUM,
8968 we ensure that the global pointer is available at every
8969 block boundary bar entry and exit. We do this in one of two ways:
8971 - If the function has a cprestore slot, we ensure that this
8972 slot is valid at every branch. However, as explained in
8973 point (6) below, there is no guarantee that pic_offset_table_rtx
8974 itself is valid if new uses of the global pointer are introduced
8975 after the first post-epilogue split.
8977 We guarantee that the cprestore slot is valid by loading it
8978 into a fake register, CPRESTORE_SLOT_REGNUM. We then make
8979 this register live at every block boundary bar function entry
8980 and exit. It is then invalid to move the load (and thus the
8981 preceding store) across a block boundary.
8983 - If the function has no cprestore slot, we guarantee that
8984 pic_offset_table_rtx itself is valid at every branch.
8986 See mips_eh_uses for the handling of the register liveness.
8988 (3) During prologue and epilogue generation, we emit "ghost"
8989 placeholder instructions to manipulate the global pointer.
8991 (4) During prologue generation, we set cfun->machine->must_initialize_gp_p
8992 and cfun->machine->must_restore_gp_when_clobbered_p if we already know
8993 that the function needs a global pointer. (There is no need to set
8994 them earlier than this, and doing it as late as possible leads to
8995 fewer false positives.)
8997 (5) If cfun->machine->must_initialize_gp_p is true during a
8998 split_insns pass, we split the ghost instructions into real
8999 instructions. These split instructions can then be optimized in
9000 the usual way. Otherwise, we keep the ghost instructions intact,
9001 and optimize for the case where they aren't needed. We still
9002 have the option of splitting them later, if we need to introduce
9003 new uses of the global pointer.
9005 For example, the scheduler ignores a ghost instruction that
9006 stores $28 to the stack, but it handles the split form of
9007 the ghost instruction as an ordinary store.
9009 (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p
9010 is true during the first post-epilogue split_insns pass, we split
9011 calls and restore_gp patterns into instructions that explicitly
9012 load pic_offset_table_rtx from the cprestore slot. Otherwise,
9013 we split these patterns into instructions that _don't_ load from
9016 If cfun->machine->must_restore_gp_when_clobbered_p is true at the
9017 time of the split, then any instructions that exist at that time
9018 can make free use of pic_offset_table_rtx. However, if we want
9019 to introduce new uses of the global pointer after the split,
9020 we must explicitly load the value from the cprestore slot, since
9021 pic_offset_table_rtx itself might not be valid at a given point
9024 The idea is that we want to be able to delete redundant
9025 loads from the cprestore slot in the usual case where no
9026 long branches are needed.
9028 (7) If cfun->machine->must_initialize_gp_p is still false at the end
9029 of md_reorg, we decide whether the global pointer is needed for
9030 long branches. If so, we set cfun->machine->must_initialize_gp_p
9031 to true and split the ghost instructions into real instructions
9034 Note that the ghost instructions must have a zero length for three reasons:
9036 - Giving the length of the underlying $gp sequence might cause
9037 us to use long branches in cases where they aren't really needed.
9039 - They would perturb things like alignment calculations.
9041 - More importantly, the hazard detection in md_reorg relies on
9042 empty instructions having a zero length.
9044 If we find a long branch and split the ghost instructions at the
9045 end of md_reorg, the split could introduce more long branches.
9046 That isn't a problem though, because we still do the split before
9047 the final shorten_branches pass.
9049 This is extremely ugly, but it seems like the best compromise between
9050 correctness and efficiency. */
9053 mips_must_initialize_gp_p (void)
9055 return cfun->machine->must_initialize_gp_p;
9058 /* Return true if REGNO is a register that is ordinarily call-clobbered
9059 but must nevertheless be preserved by an interrupt handler. */
9062 mips_interrupt_extra_call_saved_reg_p (unsigned int regno)
9064 if (MD_REG_P (regno))
9067 if (TARGET_DSP && DSP_ACC_REG_P (regno))
9070 if (GP_REG_P (regno) && !cfun->machine->use_shadow_register_set_p)
9072 /* $0 is hard-wired. */
9073 if (regno == GP_REG_FIRST)
9076 /* The interrupt handler can treat kernel registers as
9077 scratch registers. */
9078 if (KERNEL_REG_P (regno))
9081 /* The function will return the stack pointer to its original value
9083 if (regno == STACK_POINTER_REGNUM)
9086 /* Otherwise, return true for registers that aren't ordinarily
9088 return call_really_used_regs[regno];
9094 /* Return true if the current function should treat register REGNO
9098 mips_cfun_call_saved_reg_p (unsigned int regno)
9100 /* If the user makes an ordinarily-call-saved register global,
9101 that register is no longer call-saved. */
9102 if (global_regs[regno])
9105 /* Interrupt handlers need to save extra registers. */
9106 if (cfun->machine->interrupt_handler_p
9107 && mips_interrupt_extra_call_saved_reg_p (regno))
9110 /* call_insns preserve $28 unless they explicitly say otherwise,
9111 so call_really_used_regs[] treats $28 as call-saved. However,
9112 we want the ABI property rather than the default call_insn
9114 return (regno == GLOBAL_POINTER_REGNUM
9115 ? TARGET_CALL_SAVED_GP
9116 : !call_really_used_regs[regno]);
9119 /* Return true if the function body might clobber register REGNO.
9120 We know that REGNO is call-saved. */
9123 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno)
9125 /* Some functions should be treated as clobbering all call-saved
9127 if (crtl->saves_all_registers)
9130 /* DF handles cases where a register is explicitly referenced in
9131 the rtl. Incoming values are passed in call-clobbered registers,
9132 so we can assume that any live call-saved register is set within
9134 if (df_regs_ever_live_p (regno))
9137 /* Check for registers that are clobbered by FUNCTION_PROFILER.
9138 These clobbers are not explicit in the rtl. */
9139 if (crtl->profile && MIPS_SAVE_REG_FOR_PROFILING_P (regno))
9142 /* If we're using a call-saved global pointer, the function's
9143 prologue will need to set it up. */
9144 if (cfun->machine->global_pointer == regno)
9147 /* The function's prologue will need to set the frame pointer if
9148 frame_pointer_needed. */
9149 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
9152 /* If a MIPS16 function returns a value in FPRs, its epilogue
9153 will need to call an external libgcc routine. This yet-to-be
9154 generated call_insn will clobber $31. */
9155 if (regno == RETURN_ADDR_REGNUM && mips16_cfun_returns_in_fpr_p ())
9158 /* If REGNO is ordinarily call-clobbered, we must assume that any
9159 called function could modify it. */
9160 if (cfun->machine->interrupt_handler_p
9161 && !current_function_is_leaf
9162 && mips_interrupt_extra_call_saved_reg_p (regno))
9168 /* Return true if the current function must save register REGNO. */
9171 mips_save_reg_p (unsigned int regno)
9173 if (mips_cfun_call_saved_reg_p (regno))
9175 if (mips_cfun_might_clobber_call_saved_reg_p (regno))
9178 /* Save both registers in an FPR pair if either one is used. This is
9179 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
9180 register to be used without the even register. */
9181 if (FP_REG_P (regno)
9182 && MAX_FPRS_PER_FMT == 2
9183 && mips_cfun_might_clobber_call_saved_reg_p (regno + 1))
9187 /* We need to save the incoming return address if __builtin_eh_return
9188 is being used to set a different return address. */
9189 if (regno == RETURN_ADDR_REGNUM && crtl->calls_eh_return)
9195 /* Populate the current function's mips_frame_info structure.
9197 MIPS stack frames look like:
9199 +-------------------------------+
9201 | incoming stack arguments |
9203 +-------------------------------+
9205 | caller-allocated save area |
9206 A | for register arguments |
9208 +-------------------------------+ <-- incoming stack pointer
9210 | callee-allocated save area |
9211 B | for arguments that are |
9212 | split between registers and |
9215 +-------------------------------+ <-- arg_pointer_rtx
9217 C | callee-allocated save area |
9218 | for register varargs |
9220 +-------------------------------+ <-- frame_pointer_rtx
9221 | | + cop0_sp_offset
9222 | COP0 reg save area | + UNITS_PER_WORD
9224 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
9225 | | + UNITS_PER_WORD
9226 | accumulator save area |
9228 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
9229 | | + UNITS_PER_HWFPVALUE
9232 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset
9233 | | + UNITS_PER_WORD
9236 +-------------------------------+ <-- frame_pointer_rtx with
9237 | | \ -fstack-protector
9238 | local variables | | var_size
9240 +-------------------------------+
9242 | $gp save area | | cprestore_size
9244 P +-------------------------------+ <-- hard_frame_pointer_rtx for
9246 | outgoing stack arguments | |
9248 +-------------------------------+ | args_size
9250 | caller-allocated save area | |
9251 | for register arguments | |
9253 +-------------------------------+ <-- stack_pointer_rtx
9254 frame_pointer_rtx without
9256 hard_frame_pointer_rtx for
9259 At least two of A, B and C will be empty.
9261 Dynamic stack allocations such as alloca insert data at point P.
9262 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
9263 hard_frame_pointer_rtx unchanged. */
9266 mips_compute_frame_info (void)
9268 struct mips_frame_info *frame;
9269 HOST_WIDE_INT offset, size;
9270 unsigned int regno, i;
9272 /* Set this function's interrupt properties. */
9273 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
9276 error ("the %<interrupt%> attribute requires a MIPS32r2 processor");
9277 else if (TARGET_HARD_FLOAT)
9278 error ("the %<interrupt%> attribute requires %<-msoft-float%>");
9279 else if (TARGET_MIPS16)
9280 error ("interrupt handlers cannot be MIPS16 functions");
9283 cfun->machine->interrupt_handler_p = true;
9284 cfun->machine->use_shadow_register_set_p =
9285 mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl));
9286 cfun->machine->keep_interrupts_masked_p =
9287 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl));
9288 cfun->machine->use_debug_exception_return_p =
9289 mips_use_debug_exception_return_p (TREE_TYPE
9290 (current_function_decl));
9294 frame = &cfun->machine->frame;
9295 memset (frame, 0, sizeof (*frame));
9296 size = get_frame_size ();
9298 cfun->machine->global_pointer = mips_global_pointer ();
9300 /* The first two blocks contain the outgoing argument area and the $gp save
9301 slot. This area isn't needed in leaf functions, but if the
9302 target-independent frame size is nonzero, we have already committed to
9303 allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */
9304 if ((size == 0 || FRAME_GROWS_DOWNWARD) && current_function_is_leaf)
9306 /* The MIPS 3.0 linker does not like functions that dynamically
9307 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
9308 looks like we are trying to create a second frame pointer to the
9309 function, so allocate some stack space to make it happy. */
9310 if (cfun->calls_alloca)
9311 frame->args_size = REG_PARM_STACK_SPACE (cfun->decl);
9313 frame->args_size = 0;
9314 frame->cprestore_size = 0;
9318 frame->args_size = crtl->outgoing_args_size;
9319 frame->cprestore_size = MIPS_GP_SAVE_AREA_SIZE;
9321 offset = frame->args_size + frame->cprestore_size;
9323 /* Move above the local variables. */
9324 frame->var_size = MIPS_STACK_ALIGN (size);
9325 offset += frame->var_size;
9327 /* Find out which GPRs we need to save. */
9328 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
9329 if (mips_save_reg_p (regno))
9332 frame->mask |= 1 << (regno - GP_REG_FIRST);
9335 /* If this function calls eh_return, we must also save and restore the
9336 EH data registers. */
9337 if (crtl->calls_eh_return)
9338 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; i++)
9341 frame->mask |= 1 << (EH_RETURN_DATA_REGNO (i) - GP_REG_FIRST);
9344 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
9345 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
9346 save all later registers too. */
9347 if (GENERATE_MIPS16E_SAVE_RESTORE)
9349 mips16e_mask_registers (&frame->mask, mips16e_s2_s8_regs,
9350 ARRAY_SIZE (mips16e_s2_s8_regs), &frame->num_gp);
9351 mips16e_mask_registers (&frame->mask, mips16e_a0_a3_regs,
9352 ARRAY_SIZE (mips16e_a0_a3_regs), &frame->num_gp);
9355 /* Move above the GPR save area. */
9356 if (frame->num_gp > 0)
9358 offset += MIPS_STACK_ALIGN (frame->num_gp * UNITS_PER_WORD);
9359 frame->gp_sp_offset = offset - UNITS_PER_WORD;
9362 /* Find out which FPRs we need to save. This loop must iterate over
9363 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
9364 if (TARGET_HARD_FLOAT)
9365 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += MAX_FPRS_PER_FMT)
9366 if (mips_save_reg_p (regno))
9368 frame->num_fp += MAX_FPRS_PER_FMT;
9369 frame->fmask |= ~(~0 << MAX_FPRS_PER_FMT) << (regno - FP_REG_FIRST);
9372 /* Move above the FPR save area. */
9373 if (frame->num_fp > 0)
9375 offset += MIPS_STACK_ALIGN (frame->num_fp * UNITS_PER_FPREG);
9376 frame->fp_sp_offset = offset - UNITS_PER_HWFPVALUE;
9379 /* Add in space for the interrupt context information. */
9380 if (cfun->machine->interrupt_handler_p)
9383 if (mips_save_reg_p (LO_REGNUM) || mips_save_reg_p (HI_REGNUM))
9386 frame->acc_mask |= (1 << 0);
9389 /* Check accumulators 1, 2, 3. */
9390 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
9391 if (mips_save_reg_p (i) || mips_save_reg_p (i + 1))
9394 frame->acc_mask |= 1 << (((i - DSP_ACC_REG_FIRST) / 2) + 1);
9397 /* All interrupt context functions need space to preserve STATUS. */
9398 frame->num_cop0_regs++;
9400 /* If we don't keep interrupts masked, we need to save EPC. */
9401 if (!cfun->machine->keep_interrupts_masked_p)
9402 frame->num_cop0_regs++;
9405 /* Move above the accumulator save area. */
9406 if (frame->num_acc > 0)
9408 /* Each accumulator needs 2 words. */
9409 offset += frame->num_acc * 2 * UNITS_PER_WORD;
9410 frame->acc_sp_offset = offset - UNITS_PER_WORD;
9413 /* Move above the COP0 register save area. */
9414 if (frame->num_cop0_regs > 0)
9416 offset += frame->num_cop0_regs * UNITS_PER_WORD;
9417 frame->cop0_sp_offset = offset - UNITS_PER_WORD;
9420 /* Move above the callee-allocated varargs save area. */
9421 offset += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
9422 frame->arg_pointer_offset = offset;
9424 /* Move above the callee-allocated area for pretend stack arguments. */
9425 offset += crtl->args.pretend_args_size;
9426 frame->total_size = offset;
9428 /* Work out the offsets of the save areas from the top of the frame. */
9429 if (frame->gp_sp_offset > 0)
9430 frame->gp_save_offset = frame->gp_sp_offset - offset;
9431 if (frame->fp_sp_offset > 0)
9432 frame->fp_save_offset = frame->fp_sp_offset - offset;
9433 if (frame->acc_sp_offset > 0)
9434 frame->acc_save_offset = frame->acc_sp_offset - offset;
9435 if (frame->num_cop0_regs > 0)
9436 frame->cop0_save_offset = frame->cop0_sp_offset - offset;
9438 /* MIPS16 code offsets the frame pointer by the size of the outgoing
9439 arguments. This tends to increase the chances of using unextended
9440 instructions for local variables and incoming arguments. */
9442 frame->hard_frame_pointer_offset = frame->args_size;
9445 /* Return the style of GP load sequence that is being used for the
9446 current function. */
9448 enum mips_loadgp_style
9449 mips_current_loadgp_style (void)
9451 if (!TARGET_USE_GOT || cfun->machine->global_pointer == INVALID_REGNUM)
9457 if (TARGET_ABSOLUTE_ABICALLS)
9458 return LOADGP_ABSOLUTE;
9460 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
9463 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
9466 mips_frame_pointer_required (void)
9468 /* If the function contains dynamic stack allocations, we need to
9469 use the frame pointer to access the static parts of the frame. */
9470 if (cfun->calls_alloca)
9473 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
9474 reload may be unable to compute the address of a local variable,
9475 since there is no way to add a large constant to the stack pointer
9476 without using a second temporary register. */
9479 mips_compute_frame_info ();
9480 if (!SMALL_OPERAND (cfun->machine->frame.total_size))
9487 /* Make sure that we're not trying to eliminate to the wrong hard frame
9491 mips_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
9493 return (to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM);
9496 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
9497 or argument pointer. TO is either the stack pointer or hard frame
9501 mips_initial_elimination_offset (int from, int to)
9503 HOST_WIDE_INT offset;
9505 mips_compute_frame_info ();
9507 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */
9510 case FRAME_POINTER_REGNUM:
9511 if (FRAME_GROWS_DOWNWARD)
9512 offset = (cfun->machine->frame.args_size
9513 + cfun->machine->frame.cprestore_size
9514 + cfun->machine->frame.var_size);
9519 case ARG_POINTER_REGNUM:
9520 offset = cfun->machine->frame.arg_pointer_offset;
9527 if (to == HARD_FRAME_POINTER_REGNUM)
9528 offset -= cfun->machine->frame.hard_frame_pointer_offset;
9533 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
9536 mips_extra_live_on_entry (bitmap regs)
9540 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
9541 the global pointer. */
9542 if (!TARGET_ABSOLUTE_ABICALLS)
9543 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
9545 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
9546 the global pointer. */
9548 bitmap_set_bit (regs, MIPS16_PIC_TEMP_REGNUM);
9550 /* See the comment above load_call<mode> for details. */
9551 bitmap_set_bit (regs, GOT_VERSION_REGNUM);
9555 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
9559 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
9564 return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);
9567 /* Emit code to change the current function's return address to
9568 ADDRESS. SCRATCH is available as a scratch register, if needed.
9569 ADDRESS and SCRATCH are both word-mode GPRs. */
9572 mips_set_return_address (rtx address, rtx scratch)
9576 gcc_assert (BITSET_P (cfun->machine->frame.mask, RETURN_ADDR_REGNUM));
9577 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
9578 cfun->machine->frame.gp_sp_offset);
9579 mips_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address);
9582 /* Return true if the current function has a cprestore slot. */
9585 mips_cfun_has_cprestore_slot_p (void)
9587 return (cfun->machine->global_pointer != INVALID_REGNUM
9588 && cfun->machine->frame.cprestore_size > 0);
9591 /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the
9592 cprestore slot. LOAD_P is true if the caller wants to load from
9593 the cprestore slot; it is false if the caller wants to store to
9597 mips_get_cprestore_base_and_offset (rtx *base, HOST_WIDE_INT *offset,
9600 const struct mips_frame_info *frame;
9602 frame = &cfun->machine->frame;
9603 /* .cprestore always uses the stack pointer instead of the frame pointer.
9604 We have a free choice for direct stores for non-MIPS16 functions,
9605 and for MIPS16 functions whose cprestore slot is in range of the
9606 stack pointer. Using the stack pointer would sometimes give more
9607 (early) scheduling freedom, but using the frame pointer would
9608 sometimes give more (late) scheduling freedom. It's hard to
9609 predict which applies to a given function, so let's keep things
9612 Loads must always use the frame pointer in functions that call
9613 alloca, and there's little benefit to using the stack pointer
9615 if (frame_pointer_needed && !(TARGET_CPRESTORE_DIRECTIVE && !load_p))
9617 *base = hard_frame_pointer_rtx;
9618 *offset = frame->args_size - frame->hard_frame_pointer_offset;
9622 *base = stack_pointer_rtx;
9623 *offset = frame->args_size;
9627 /* Return true if X is the load or store address of the cprestore slot;
9628 LOAD_P says which. */
9631 mips_cprestore_address_p (rtx x, bool load_p)
9633 rtx given_base, required_base;
9634 HOST_WIDE_INT given_offset, required_offset;
9636 mips_split_plus (x, &given_base, &given_offset);
9637 mips_get_cprestore_base_and_offset (&required_base, &required_offset, load_p);
9638 return given_base == required_base && given_offset == required_offset;
9641 /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are
9642 going to load from it, false if we are going to store to it.
9643 Use TEMP as a temporary register if need be. */
9646 mips_cprestore_slot (rtx temp, bool load_p)
9649 HOST_WIDE_INT offset;
9651 mips_get_cprestore_base_and_offset (&base, &offset, load_p);
9652 return gen_frame_mem (Pmode, mips_add_offset (temp, base, offset));
9655 /* Emit instructions to save global pointer value GP into cprestore
9656 slot MEM. OFFSET is the offset that MEM applies to the base register.
9658 MEM may not be a legitimate address. If it isn't, TEMP is a
9659 temporary register that can be used, otherwise it is a SCRATCH. */
9662 mips_save_gp_to_cprestore_slot (rtx mem, rtx offset, rtx gp, rtx temp)
9664 if (TARGET_CPRESTORE_DIRECTIVE)
9666 gcc_assert (gp == pic_offset_table_rtx);
9667 emit_insn (gen_cprestore (mem, offset));
9670 mips_emit_move (mips_cprestore_slot (temp, false), gp);
9673 /* Restore $gp from its save slot, using TEMP as a temporary base register
9674 if need be. This function is for o32 and o64 abicalls only.
9676 See mips_must_initialize_gp_p for details about how we manage the
9680 mips_restore_gp_from_cprestore_slot (rtx temp)
9682 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI && epilogue_completed);
9684 if (!cfun->machine->must_restore_gp_when_clobbered_p)
9686 emit_note (NOTE_INSN_DELETED);
9692 mips_emit_move (temp, mips_cprestore_slot (temp, true));
9693 mips_emit_move (pic_offset_table_rtx, temp);
9696 mips_emit_move (pic_offset_table_rtx, mips_cprestore_slot (temp, true));
9697 if (!TARGET_EXPLICIT_RELOCS)
9698 emit_insn (gen_blockage ());
9701 /* A function to save or store a register. The first argument is the
9702 register and the second is the stack slot. */
9703 typedef void (*mips_save_restore_fn) (rtx, rtx);
9705 /* Use FN to save or restore register REGNO. MODE is the register's
9706 mode and OFFSET is the offset of its save slot from the current
9710 mips_save_restore_reg (enum machine_mode mode, int regno,
9711 HOST_WIDE_INT offset, mips_save_restore_fn fn)
9715 mem = gen_frame_mem (mode, plus_constant (stack_pointer_rtx, offset));
9716 fn (gen_rtx_REG (mode, regno), mem);
9719 /* Call FN for each accumlator that is saved by the current function.
9720 SP_OFFSET is the offset of the current stack pointer from the start
9724 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
9726 HOST_WIDE_INT offset;
9729 offset = cfun->machine->frame.acc_sp_offset - sp_offset;
9730 if (BITSET_P (cfun->machine->frame.acc_mask, 0))
9732 mips_save_restore_reg (word_mode, LO_REGNUM, offset, fn);
9733 offset -= UNITS_PER_WORD;
9734 mips_save_restore_reg (word_mode, HI_REGNUM, offset, fn);
9735 offset -= UNITS_PER_WORD;
9738 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
9739 if (BITSET_P (cfun->machine->frame.acc_mask,
9740 ((regno - DSP_ACC_REG_FIRST) / 2) + 1))
9742 mips_save_restore_reg (word_mode, regno, offset, fn);
9743 offset -= UNITS_PER_WORD;
9747 /* Call FN for each register that is saved by the current function.
9748 SP_OFFSET is the offset of the current stack pointer from the start
9752 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset,
9753 mips_save_restore_fn fn)
9755 enum machine_mode fpr_mode;
9756 HOST_WIDE_INT offset;
9759 /* Save registers starting from high to low. The debuggers prefer at least
9760 the return register be stored at func+4, and also it allows us not to
9761 need a nop in the epilogue if at least one register is reloaded in
9762 addition to return address. */
9763 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
9764 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
9765 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
9767 /* Record the ra offset for use by mips_function_profiler. */
9768 if (regno == RETURN_ADDR_REGNUM)
9769 cfun->machine->frame.ra_fp_offset = offset + sp_offset;
9770 mips_save_restore_reg (word_mode, regno, offset, fn);
9771 offset -= UNITS_PER_WORD;
9774 /* This loop must iterate over the same space as its companion in
9775 mips_compute_frame_info. */
9776 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
9777 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
9778 for (regno = FP_REG_LAST - MAX_FPRS_PER_FMT + 1;
9779 regno >= FP_REG_FIRST;
9780 regno -= MAX_FPRS_PER_FMT)
9781 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
9783 mips_save_restore_reg (fpr_mode, regno, offset, fn);
9784 offset -= GET_MODE_SIZE (fpr_mode);
9788 /* Return true if a move between register REGNO and its save slot (MEM)
9789 can be done in a single move. LOAD_P is true if we are loading
9790 from the slot, false if we are storing to it. */
9793 mips_direct_save_slot_move_p (unsigned int regno, rtx mem, bool load_p)
9795 /* There is a specific MIPS16 instruction for saving $31 to the stack. */
9796 if (TARGET_MIPS16 && !load_p && regno == RETURN_ADDR_REGNUM)
9799 return mips_secondary_reload_class (REGNO_REG_CLASS (regno),
9800 GET_MODE (mem), mem, load_p) == NO_REGS;
9803 /* Emit a move from SRC to DEST, given that one of them is a register
9804 save slot and that the other is a register. TEMP is a temporary
9805 GPR of the same mode that is available if need be. */
9808 mips_emit_save_slot_move (rtx dest, rtx src, rtx temp)
9815 regno = REGNO (src);
9820 regno = REGNO (dest);
9824 if (regno == cfun->machine->global_pointer && !mips_must_initialize_gp_p ())
9826 /* We don't yet know whether we'll need this instruction or not.
9827 Postpone the decision by emitting a ghost move. This move
9828 is specifically not frame-related; only the split version is. */
9830 emit_insn (gen_move_gpdi (dest, src));
9832 emit_insn (gen_move_gpsi (dest, src));
9836 if (regno == HI_REGNUM)
9840 mips_emit_move (temp, src);
9842 emit_insn (gen_mthisi_di (gen_rtx_REG (TImode, MD_REG_FIRST),
9843 temp, gen_rtx_REG (DImode, LO_REGNUM)));
9845 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode, MD_REG_FIRST),
9846 temp, gen_rtx_REG (SImode, LO_REGNUM)));
9851 emit_insn (gen_mfhidi_ti (temp,
9852 gen_rtx_REG (TImode, MD_REG_FIRST)));
9854 emit_insn (gen_mfhisi_di (temp,
9855 gen_rtx_REG (DImode, MD_REG_FIRST)));
9856 mips_emit_move (dest, temp);
9859 else if (mips_direct_save_slot_move_p (regno, mem, mem == src))
9860 mips_emit_move (dest, src);
9863 gcc_assert (!reg_overlap_mentioned_p (dest, temp));
9864 mips_emit_move (temp, src);
9865 mips_emit_move (dest, temp);
9868 mips_set_frame_expr (mips_frame_set (dest, src));
9871 /* If we're generating n32 or n64 abicalls, and the current function
9872 does not use $28 as its global pointer, emit a cplocal directive.
9873 Use pic_offset_table_rtx as the argument to the directive. */
9876 mips_output_cplocal (void)
9878 if (!TARGET_EXPLICIT_RELOCS
9879 && mips_must_initialize_gp_p ()
9880 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
9881 output_asm_insn (".cplocal %+", 0);
9884 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
9887 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9891 #ifdef SDB_DEBUGGING_INFO
9892 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
9893 SDB_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
9896 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
9897 floating-point arguments. */
9899 && TARGET_HARD_FLOAT_ABI
9900 && crtl->args.info.fp_code != 0)
9901 mips16_build_function_stub ();
9903 /* Get the function name the same way that toplev.c does before calling
9904 assemble_start_function. This is needed so that the name used here
9905 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
9906 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
9907 mips_start_function_definition (fnname, TARGET_MIPS16);
9909 /* Output MIPS-specific frame information. */
9910 if (!flag_inhibit_size_directive)
9912 const struct mips_frame_info *frame;
9914 frame = &cfun->machine->frame;
9916 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
9918 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
9919 "# vars= " HOST_WIDE_INT_PRINT_DEC
9921 ", args= " HOST_WIDE_INT_PRINT_DEC
9922 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
9923 reg_names[frame_pointer_needed
9924 ? HARD_FRAME_POINTER_REGNUM
9925 : STACK_POINTER_REGNUM],
9926 (frame_pointer_needed
9927 ? frame->total_size - frame->hard_frame_pointer_offset
9928 : frame->total_size),
9929 reg_names[RETURN_ADDR_REGNUM],
9931 frame->num_gp, frame->num_fp,
9933 frame->cprestore_size);
9935 /* .mask MASK, OFFSET. */
9936 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
9937 frame->mask, frame->gp_save_offset);
9939 /* .fmask MASK, OFFSET. */
9940 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
9941 frame->fmask, frame->fp_save_offset);
9944 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
9945 Also emit the ".set noreorder; .set nomacro" sequence for functions
9947 if (mips_must_initialize_gp_p ()
9948 && mips_current_loadgp_style () == LOADGP_OLDABI)
9952 /* This is a fixed-form sequence. The position of the
9953 first two instructions is important because of the
9954 way _gp_disp is defined. */
9955 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
9956 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
9957 output_asm_insn ("sll\t$2,16", 0);
9958 output_asm_insn ("addu\t$2,$3", 0);
9962 /* .cpload must be in a .set noreorder but not a
9963 .set nomacro block. */
9964 mips_push_asm_switch (&mips_noreorder);
9965 output_asm_insn (".cpload\t%^", 0);
9966 if (!cfun->machine->all_noreorder_p)
9967 mips_pop_asm_switch (&mips_noreorder);
9969 mips_push_asm_switch (&mips_nomacro);
9972 else if (cfun->machine->all_noreorder_p)
9974 mips_push_asm_switch (&mips_noreorder);
9975 mips_push_asm_switch (&mips_nomacro);
9978 /* Tell the assembler which register we're using as the global
9979 pointer. This is needed for thunks, since they can use either
9980 explicit relocs or assembler macros. */
9981 mips_output_cplocal ();
9984 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
9987 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
9988 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9992 /* Reinstate the normal $gp. */
9993 SET_REGNO (pic_offset_table_rtx, GLOBAL_POINTER_REGNUM);
9994 mips_output_cplocal ();
9996 if (cfun->machine->all_noreorder_p)
9998 mips_pop_asm_switch (&mips_nomacro);
9999 mips_pop_asm_switch (&mips_noreorder);
10002 /* Get the function name the same way that toplev.c does before calling
10003 assemble_start_function. This is needed so that the name used here
10004 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10005 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
10006 mips_end_function_definition (fnname);
10009 /* Save register REG to MEM. Make the instruction frame-related. */
10012 mips_save_reg (rtx reg, rtx mem)
10014 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
10018 if (mips_split_64bit_move_p (mem, reg))
10019 mips_split_doubleword_move (mem, reg);
10021 mips_emit_move (mem, reg);
10023 x1 = mips_frame_set (mips_subword (mem, false),
10024 mips_subword (reg, false));
10025 x2 = mips_frame_set (mips_subword (mem, true),
10026 mips_subword (reg, true));
10027 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
10030 mips_emit_save_slot_move (mem, reg, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
10033 /* The __gnu_local_gp symbol. */
10035 static GTY(()) rtx mips_gnu_local_gp;
10037 /* If we're generating n32 or n64 abicalls, emit instructions
10038 to set up the global pointer. */
10041 mips_emit_loadgp (void)
10043 rtx addr, offset, incoming_address, base, index, pic_reg;
10045 pic_reg = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
10046 switch (mips_current_loadgp_style ())
10048 case LOADGP_ABSOLUTE:
10049 if (mips_gnu_local_gp == NULL)
10051 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
10052 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
10054 emit_insn (Pmode == SImode
10055 ? gen_loadgp_absolute_si (pic_reg, mips_gnu_local_gp)
10056 : gen_loadgp_absolute_di (pic_reg, mips_gnu_local_gp));
10059 case LOADGP_OLDABI:
10060 /* Added by mips_output_function_prologue. */
10063 case LOADGP_NEWABI:
10064 addr = XEXP (DECL_RTL (current_function_decl), 0);
10065 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
10066 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
10067 emit_insn (Pmode == SImode
10068 ? gen_loadgp_newabi_si (pic_reg, offset, incoming_address)
10069 : gen_loadgp_newabi_di (pic_reg, offset, incoming_address));
10073 base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE));
10074 index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX));
10075 emit_insn (Pmode == SImode
10076 ? gen_loadgp_rtp_si (pic_reg, base, index)
10077 : gen_loadgp_rtp_di (pic_reg, base, index));
10085 emit_insn (gen_copygp_mips16 (pic_offset_table_rtx, pic_reg));
10087 /* Emit a blockage if there are implicit uses of the GP register.
10088 This includes profiled functions, because FUNCTION_PROFILE uses
10090 if (!TARGET_EXPLICIT_RELOCS || crtl->profile)
10091 emit_insn (gen_loadgp_blockage ());
10094 /* A for_each_rtx callback. Stop the search if *X is a kernel register. */
10097 mips_kernel_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
10099 return REG_P (*x) && KERNEL_REG_P (REGNO (*x));
10102 /* Expand the "prologue" pattern. */
10105 mips_expand_prologue (void)
10107 const struct mips_frame_info *frame;
10108 HOST_WIDE_INT size;
10109 unsigned int nargs;
10112 if (cfun->machine->global_pointer != INVALID_REGNUM)
10114 /* Check whether an insn uses pic_offset_table_rtx, either explicitly
10115 or implicitly. If so, we can commit to using a global pointer
10116 straight away, otherwise we need to defer the decision. */
10117 if (mips_cfun_has_inflexible_gp_ref_p ()
10118 || mips_cfun_has_flexible_gp_ref_p ())
10120 cfun->machine->must_initialize_gp_p = true;
10121 cfun->machine->must_restore_gp_when_clobbered_p = true;
10124 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
10127 frame = &cfun->machine->frame;
10128 size = frame->total_size;
10130 if (flag_stack_usage)
10131 current_function_static_stack_size = size;
10133 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
10134 bytes beforehand; this is enough to cover the register save area
10135 without going out of range. */
10136 if (((frame->mask | frame->fmask | frame->acc_mask) != 0)
10137 || frame->num_cop0_regs > 0)
10139 HOST_WIDE_INT step1;
10141 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
10142 if (GENERATE_MIPS16E_SAVE_RESTORE)
10144 HOST_WIDE_INT offset;
10145 unsigned int mask, regno;
10147 /* Try to merge argument stores into the save instruction. */
10148 nargs = mips16e_collect_argument_saves ();
10150 /* Build the save instruction. */
10151 mask = frame->mask;
10152 insn = mips16e_build_save_restore (false, &mask, &offset,
10154 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10157 /* Check if we need to save other registers. */
10158 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
10159 if (BITSET_P (mask, regno - GP_REG_FIRST))
10161 offset -= UNITS_PER_WORD;
10162 mips_save_restore_reg (word_mode, regno,
10163 offset, mips_save_reg);
10168 if (cfun->machine->interrupt_handler_p)
10170 HOST_WIDE_INT offset;
10173 /* If this interrupt is using a shadow register set, we need to
10174 get the stack pointer from the previous register set. */
10175 if (cfun->machine->use_shadow_register_set_p)
10176 emit_insn (gen_mips_rdpgpr (stack_pointer_rtx,
10177 stack_pointer_rtx));
10179 if (!cfun->machine->keep_interrupts_masked_p)
10181 /* Move from COP0 Cause to K0. */
10182 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K0_REG_NUM),
10183 gen_rtx_REG (SImode,
10184 COP0_CAUSE_REG_NUM)));
10185 /* Move from COP0 EPC to K1. */
10186 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
10187 gen_rtx_REG (SImode,
10188 COP0_EPC_REG_NUM)));
10191 /* Allocate the first part of the frame. */
10192 insn = gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx,
10194 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10197 /* Start at the uppermost location for saving. */
10198 offset = frame->cop0_sp_offset - size;
10199 if (!cfun->machine->keep_interrupts_masked_p)
10201 /* Push EPC into its stack slot. */
10202 mem = gen_frame_mem (word_mode,
10203 plus_constant (stack_pointer_rtx,
10205 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
10206 offset -= UNITS_PER_WORD;
10209 /* Move from COP0 Status to K1. */
10210 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
10211 gen_rtx_REG (SImode,
10212 COP0_STATUS_REG_NUM)));
10214 /* Right justify the RIPL in k0. */
10215 if (!cfun->machine->keep_interrupts_masked_p)
10216 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode, K0_REG_NUM),
10217 gen_rtx_REG (SImode, K0_REG_NUM),
10218 GEN_INT (CAUSE_IPL)));
10220 /* Push Status into its stack slot. */
10221 mem = gen_frame_mem (word_mode,
10222 plus_constant (stack_pointer_rtx, offset));
10223 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
10224 offset -= UNITS_PER_WORD;
10226 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
10227 if (!cfun->machine->keep_interrupts_masked_p)
10228 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
10231 gen_rtx_REG (SImode, K0_REG_NUM)));
10233 if (!cfun->machine->keep_interrupts_masked_p)
10234 /* Enable interrupts by clearing the KSU ERL and EXL bits.
10235 IE is already the correct value, so we don't have to do
10236 anything explicit. */
10237 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
10240 gen_rtx_REG (SImode, GP_REG_FIRST)));
10242 /* Disable interrupts by clearing the KSU, ERL, EXL,
10244 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
10247 gen_rtx_REG (SImode, GP_REG_FIRST)));
10251 insn = gen_add3_insn (stack_pointer_rtx,
10254 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10257 mips_for_each_saved_acc (size, mips_save_reg);
10258 mips_for_each_saved_gpr_and_fpr (size, mips_save_reg);
10262 /* Allocate the rest of the frame. */
10265 if (SMALL_OPERAND (-size))
10266 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
10268 GEN_INT (-size)))) = 1;
10271 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
10274 /* There are no instructions to add or subtract registers
10275 from the stack pointer, so use the frame pointer as a
10276 temporary. We should always be using a frame pointer
10277 in this case anyway. */
10278 gcc_assert (frame_pointer_needed);
10279 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
10280 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
10281 hard_frame_pointer_rtx,
10282 MIPS_PROLOGUE_TEMP (Pmode)));
10283 mips_emit_move (stack_pointer_rtx, hard_frame_pointer_rtx);
10286 emit_insn (gen_sub3_insn (stack_pointer_rtx,
10288 MIPS_PROLOGUE_TEMP (Pmode)));
10290 /* Describe the combined effect of the previous instructions. */
10291 mips_set_frame_expr
10292 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
10293 plus_constant (stack_pointer_rtx, -size)));
10297 /* Set up the frame pointer, if we're using one. */
10298 if (frame_pointer_needed)
10300 HOST_WIDE_INT offset;
10302 offset = frame->hard_frame_pointer_offset;
10305 insn = mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
10306 RTX_FRAME_RELATED_P (insn) = 1;
10308 else if (SMALL_OPERAND (offset))
10310 insn = gen_add3_insn (hard_frame_pointer_rtx,
10311 stack_pointer_rtx, GEN_INT (offset));
10312 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10316 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (offset));
10317 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
10318 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
10319 hard_frame_pointer_rtx,
10320 MIPS_PROLOGUE_TEMP (Pmode)));
10321 mips_set_frame_expr
10322 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
10323 plus_constant (stack_pointer_rtx, offset)));
10327 mips_emit_loadgp ();
10329 /* Initialize the $gp save slot. */
10330 if (mips_cfun_has_cprestore_slot_p ())
10332 rtx base, mem, gp, temp;
10333 HOST_WIDE_INT offset;
10335 mips_get_cprestore_base_and_offset (&base, &offset, false);
10336 mem = gen_frame_mem (Pmode, plus_constant (base, offset));
10337 gp = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
10338 temp = (SMALL_OPERAND (offset)
10339 ? gen_rtx_SCRATCH (Pmode)
10340 : MIPS_PROLOGUE_TEMP (Pmode));
10341 emit_insn (gen_potential_cprestore (mem, GEN_INT (offset), gp, temp));
10343 mips_get_cprestore_base_and_offset (&base, &offset, true);
10344 mem = gen_frame_mem (Pmode, plus_constant (base, offset));
10345 emit_insn (gen_use_cprestore (mem));
10348 /* We need to search back to the last use of K0 or K1. */
10349 if (cfun->machine->interrupt_handler_p)
10351 for (insn = get_last_insn (); insn != NULL_RTX; insn = PREV_INSN (insn))
10353 && for_each_rtx (&PATTERN (insn), mips_kernel_reg_p, NULL))
10355 /* Emit a move from K1 to COP0 Status after insn. */
10356 gcc_assert (insn != NULL_RTX);
10357 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
10358 gen_rtx_REG (SImode, K1_REG_NUM)),
10362 /* If we are profiling, make sure no instructions are scheduled before
10363 the call to mcount. */
10365 emit_insn (gen_blockage ());
10368 /* Emit instructions to restore register REG from slot MEM. */
10371 mips_restore_reg (rtx reg, rtx mem)
10373 /* There's no MIPS16 instruction to load $31 directly. Load into
10374 $7 instead and adjust the return insn appropriately. */
10375 if (TARGET_MIPS16 && REGNO (reg) == RETURN_ADDR_REGNUM)
10376 reg = gen_rtx_REG (GET_MODE (reg), GP_REG_FIRST + 7);
10378 mips_emit_save_slot_move (reg, mem, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
10381 /* Emit any instructions needed before a return. */
10384 mips_expand_before_return (void)
10386 /* When using a call-clobbered gp, we start out with unified call
10387 insns that include instructions to restore the gp. We then split
10388 these unified calls after reload. These split calls explicitly
10389 clobber gp, so there is no need to define
10390 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
10392 For consistency, we should also insert an explicit clobber of $28
10393 before return insns, so that the post-reload optimizers know that
10394 the register is not live on exit. */
10395 if (TARGET_CALL_CLOBBERED_GP)
10396 emit_clobber (pic_offset_table_rtx);
10399 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
10403 mips_expand_epilogue (bool sibcall_p)
10405 const struct mips_frame_info *frame;
10406 HOST_WIDE_INT step1, step2;
10407 rtx base, target, insn;
10409 if (!sibcall_p && mips_can_use_return_insn ())
10411 emit_jump_insn (gen_return ());
10415 /* In MIPS16 mode, if the return value should go into a floating-point
10416 register, we need to call a helper routine to copy it over. */
10417 if (mips16_cfun_returns_in_fpr_p ())
10418 mips16_copy_fpr_return_value ();
10420 /* Split the frame into two. STEP1 is the amount of stack we should
10421 deallocate before restoring the registers. STEP2 is the amount we
10422 should deallocate afterwards.
10424 Start off by assuming that no registers need to be restored. */
10425 frame = &cfun->machine->frame;
10426 step1 = frame->total_size;
10429 /* Work out which register holds the frame address. */
10430 if (!frame_pointer_needed)
10431 base = stack_pointer_rtx;
10434 base = hard_frame_pointer_rtx;
10435 step1 -= frame->hard_frame_pointer_offset;
10438 /* If we need to restore registers, deallocate as much stack as
10439 possible in the second step without going out of range. */
10440 if ((frame->mask | frame->fmask | frame->acc_mask) != 0
10441 || frame->num_cop0_regs > 0)
10443 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
10447 /* Set TARGET to BASE + STEP1. */
10453 /* Get an rtx for STEP1 that we can add to BASE. */
10454 adjust = GEN_INT (step1);
10455 if (!SMALL_OPERAND (step1))
10457 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), adjust);
10458 adjust = MIPS_EPILOGUE_TEMP (Pmode);
10461 /* Normal mode code can copy the result straight into $sp. */
10462 if (!TARGET_MIPS16)
10463 target = stack_pointer_rtx;
10465 emit_insn (gen_add3_insn (target, base, adjust));
10468 /* Copy TARGET into the stack pointer. */
10469 if (target != stack_pointer_rtx)
10470 mips_emit_move (stack_pointer_rtx, target);
10472 /* If we're using addressing macros, $gp is implicitly used by all
10473 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
10475 if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS)
10476 emit_insn (gen_blockage ());
10478 if (GENERATE_MIPS16E_SAVE_RESTORE && frame->mask != 0)
10480 unsigned int regno, mask;
10481 HOST_WIDE_INT offset;
10484 /* Generate the restore instruction. */
10485 mask = frame->mask;
10486 restore = mips16e_build_save_restore (true, &mask, &offset, 0, step2);
10488 /* Restore any other registers manually. */
10489 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
10490 if (BITSET_P (mask, regno - GP_REG_FIRST))
10492 offset -= UNITS_PER_WORD;
10493 mips_save_restore_reg (word_mode, regno, offset, mips_restore_reg);
10496 /* Restore the remaining registers and deallocate the final bit
10498 emit_insn (restore);
10502 /* Restore the registers. */
10503 mips_for_each_saved_acc (frame->total_size - step2, mips_restore_reg);
10504 mips_for_each_saved_gpr_and_fpr (frame->total_size - step2,
10507 if (cfun->machine->interrupt_handler_p)
10509 HOST_WIDE_INT offset;
10512 offset = frame->cop0_sp_offset - (frame->total_size - step2);
10513 if (!cfun->machine->keep_interrupts_masked_p)
10515 /* Restore the original EPC. */
10516 mem = gen_frame_mem (word_mode,
10517 plus_constant (stack_pointer_rtx, offset));
10518 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
10519 offset -= UNITS_PER_WORD;
10521 /* Move to COP0 EPC. */
10522 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_EPC_REG_NUM),
10523 gen_rtx_REG (SImode, K0_REG_NUM)));
10526 /* Restore the original Status. */
10527 mem = gen_frame_mem (word_mode,
10528 plus_constant (stack_pointer_rtx, offset));
10529 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
10530 offset -= UNITS_PER_WORD;
10532 /* If we don't use shoadow register set, we need to update SP. */
10533 if (!cfun->machine->use_shadow_register_set_p && step2 > 0)
10534 emit_insn (gen_add3_insn (stack_pointer_rtx,
10538 /* Move to COP0 Status. */
10539 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
10540 gen_rtx_REG (SImode, K0_REG_NUM)));
10544 /* Deallocate the final bit of the frame. */
10546 emit_insn (gen_add3_insn (stack_pointer_rtx,
10552 /* Add in the __builtin_eh_return stack adjustment. We need to
10553 use a temporary in MIPS16 code. */
10554 if (crtl->calls_eh_return)
10558 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
10559 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
10560 MIPS_EPILOGUE_TEMP (Pmode),
10561 EH_RETURN_STACKADJ_RTX));
10562 mips_emit_move (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
10565 emit_insn (gen_add3_insn (stack_pointer_rtx,
10567 EH_RETURN_STACKADJ_RTX));
10572 mips_expand_before_return ();
10573 if (cfun->machine->interrupt_handler_p)
10575 /* Interrupt handlers generate eret or deret. */
10576 if (cfun->machine->use_debug_exception_return_p)
10577 emit_jump_insn (gen_mips_deret ());
10579 emit_jump_insn (gen_mips_eret ());
10583 unsigned int regno;
10585 /* When generating MIPS16 code, the normal
10586 mips_for_each_saved_gpr_and_fpr path will restore the return
10587 address into $7 rather than $31. */
10589 && !GENERATE_MIPS16E_SAVE_RESTORE
10590 && BITSET_P (frame->mask, RETURN_ADDR_REGNUM))
10591 regno = GP_REG_FIRST + 7;
10593 regno = RETURN_ADDR_REGNUM;
10594 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, regno)));
10598 /* Search from the beginning to the first use of K0 or K1. */
10599 if (cfun->machine->interrupt_handler_p
10600 && !cfun->machine->keep_interrupts_masked_p)
10602 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
10604 && for_each_rtx (&PATTERN(insn), mips_kernel_reg_p, NULL))
10606 gcc_assert (insn != NULL_RTX);
10607 /* Insert disable interrupts before the first use of K0 or K1. */
10608 emit_insn_before (gen_mips_di (), insn);
10609 emit_insn_before (gen_mips_ehb (), insn);
10613 /* Return nonzero if this function is known to have a null epilogue.
10614 This allows the optimizer to omit jumps to jumps if no stack
10618 mips_can_use_return_insn (void)
10620 /* Interrupt handlers need to go through the epilogue. */
10621 if (cfun->machine->interrupt_handler_p)
10624 if (!reload_completed)
10630 /* In MIPS16 mode, a function that returns a floating-point value
10631 needs to arrange to copy the return value into the floating-point
10633 if (mips16_cfun_returns_in_fpr_p ())
10636 return cfun->machine->frame.total_size == 0;
10639 /* Return true if register REGNO can store a value of mode MODE.
10640 The result of this function is cached in mips_hard_regno_mode_ok. */
10643 mips_hard_regno_mode_ok_p (unsigned int regno, enum machine_mode mode)
10646 enum mode_class mclass;
10648 if (mode == CCV2mode)
10649 return (ISA_HAS_8CC
10650 && ST_REG_P (regno)
10651 && (regno - ST_REG_FIRST) % 2 == 0);
10653 if (mode == CCV4mode)
10654 return (ISA_HAS_8CC
10655 && ST_REG_P (regno)
10656 && (regno - ST_REG_FIRST) % 4 == 0);
10658 if (mode == CCmode)
10661 return regno == FPSW_REGNUM;
10663 return (ST_REG_P (regno)
10664 || GP_REG_P (regno)
10665 || FP_REG_P (regno));
10668 size = GET_MODE_SIZE (mode);
10669 mclass = GET_MODE_CLASS (mode);
10671 if (GP_REG_P (regno))
10672 return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD;
10674 if (FP_REG_P (regno)
10675 && (((regno - FP_REG_FIRST) % MAX_FPRS_PER_FMT) == 0
10676 || (MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG)))
10678 /* Allow TFmode for CCmode reloads. */
10679 if (mode == TFmode && ISA_HAS_8CC)
10682 /* Allow 64-bit vector modes for Loongson-2E/2F. */
10683 if (TARGET_LOONGSON_VECTORS
10684 && (mode == V2SImode
10685 || mode == V4HImode
10686 || mode == V8QImode
10687 || mode == DImode))
10690 if (mclass == MODE_FLOAT
10691 || mclass == MODE_COMPLEX_FLOAT
10692 || mclass == MODE_VECTOR_FLOAT)
10693 return size <= UNITS_PER_FPVALUE;
10695 /* Allow integer modes that fit into a single register. We need
10696 to put integers into FPRs when using instructions like CVT
10697 and TRUNC. There's no point allowing sizes smaller than a word,
10698 because the FPU has no appropriate load/store instructions. */
10699 if (mclass == MODE_INT)
10700 return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG;
10703 if (ACC_REG_P (regno)
10704 && (INTEGRAL_MODE_P (mode) || ALL_FIXED_POINT_MODE_P (mode)))
10706 if (MD_REG_P (regno))
10708 /* After a multiplication or division, clobbering HI makes
10709 the value of LO unpredictable, and vice versa. This means
10710 that, for all interesting cases, HI and LO are effectively
10713 We model this by requiring that any value that uses HI
10715 if (size <= UNITS_PER_WORD * 2)
10716 return regno == (size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST);
10720 /* DSP accumulators do not have the same restrictions as
10721 HI and LO, so we can treat them as normal doubleword
10723 if (size <= UNITS_PER_WORD)
10726 if (size <= UNITS_PER_WORD * 2
10727 && ((regno - DSP_ACC_REG_FIRST) & 1) == 0)
10732 if (ALL_COP_REG_P (regno))
10733 return mclass == MODE_INT && size <= UNITS_PER_WORD;
10735 if (regno == GOT_VERSION_REGNUM)
10736 return mode == SImode;
10741 /* Implement HARD_REGNO_NREGS. */
10744 mips_hard_regno_nregs (int regno, enum machine_mode mode)
10746 if (ST_REG_P (regno))
10747 /* The size of FP status registers is always 4, because they only hold
10748 CCmode values, and CCmode is always considered to be 4 bytes wide. */
10749 return (GET_MODE_SIZE (mode) + 3) / 4;
10751 if (FP_REG_P (regno))
10752 return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG;
10754 /* All other registers are word-sized. */
10755 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
10758 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
10759 in mips_hard_regno_nregs. */
10762 mips_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
10768 COPY_HARD_REG_SET (left, reg_class_contents[(int) rclass]);
10769 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS]))
10771 size = MIN (size, 4);
10772 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) ST_REGS]);
10774 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS]))
10776 size = MIN (size, UNITS_PER_FPREG);
10777 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]);
10779 if (!hard_reg_set_empty_p (left))
10780 size = MIN (size, UNITS_PER_WORD);
10781 return (GET_MODE_SIZE (mode) + size - 1) / size;
10784 /* Implement CANNOT_CHANGE_MODE_CLASS. */
10787 mips_cannot_change_mode_class (enum machine_mode from ATTRIBUTE_UNUSED,
10788 enum machine_mode to ATTRIBUTE_UNUSED,
10789 enum reg_class rclass)
10791 /* There are several problems with changing the modes of values in
10792 floating-point registers:
10794 - When a multi-word value is stored in paired floating-point
10795 registers, the first register always holds the low word. We
10796 therefore can't allow FPRs to change between single-word and
10797 multi-word modes on big-endian targets.
10799 - GCC assumes that each word of a multiword register can be
10800 accessed individually using SUBREGs. This is not true for
10801 floating-point registers if they are bigger than a word.
10803 - Loading a 32-bit value into a 64-bit floating-point register
10804 will not sign-extend the value, despite what LOAD_EXTEND_OP
10805 says. We can't allow FPRs to change from SImode to a wider
10806 mode on 64-bit targets.
10808 - If the FPU has already interpreted a value in one format, we
10809 must not ask it to treat the value as having a different
10812 We therefore disallow all mode changes involving FPRs. */
10813 return reg_classes_intersect_p (FP_REGS, rclass);
10816 /* Implement target hook small_register_classes_for_mode_p. */
10819 mips_small_register_classes_for_mode_p (enum machine_mode mode
10822 return TARGET_MIPS16;
10825 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
10828 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode)
10833 return TARGET_HARD_FLOAT;
10836 return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT;
10839 return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT;
10846 /* Implement MODES_TIEABLE_P. */
10849 mips_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
10851 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
10852 prefer to put one of them in FPRs. */
10853 return (mode1 == mode2
10854 || (!mips_mode_ok_for_mov_fmt_p (mode1)
10855 && !mips_mode_ok_for_mov_fmt_p (mode2)));
10858 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
10861 mips_preferred_reload_class (rtx x, reg_class_t rclass)
10863 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, rclass))
10866 if (reg_class_subset_p (FP_REGS, rclass)
10867 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x)))
10870 if (reg_class_subset_p (GR_REGS, rclass))
10873 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, rclass))
10879 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
10880 Return a "canonical" class to represent it in later calculations. */
10883 mips_canonicalize_move_class (reg_class_t rclass)
10885 /* All moves involving accumulator registers have the same cost. */
10886 if (reg_class_subset_p (rclass, ACC_REGS))
10889 /* Likewise promote subclasses of general registers to the most
10890 interesting containing class. */
10891 if (TARGET_MIPS16 && reg_class_subset_p (rclass, M16_REGS))
10893 else if (reg_class_subset_p (rclass, GENERAL_REGS))
10894 rclass = GENERAL_REGS;
10899 /* Return the cost of moving a value of mode MODE from a register of
10900 class FROM to a GPR. Return 0 for classes that are unions of other
10901 classes handled by this function. */
10904 mips_move_to_gpr_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
10910 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
10914 /* MFLO and MFHI. */
10922 /* LUI followed by MOVF. */
10928 /* This choice of value is historical. */
10936 /* Return the cost of moving a value of mode MODE from a GPR to a
10937 register of class TO. Return 0 for classes that are unions of
10938 other classes handled by this function. */
10941 mips_move_from_gpr_cost (enum machine_mode mode, reg_class_t to)
10946 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
10950 /* MTLO and MTHI. */
10958 /* A secondary reload through an FPR scratch. */
10959 return (mips_register_move_cost (mode, GENERAL_REGS, FP_REGS)
10960 + mips_register_move_cost (mode, FP_REGS, ST_REGS));
10965 /* This choice of value is historical. */
10973 /* Implement TARGET_REGISTER_MOVE_COST. Return 0 for classes that are the
10974 maximum of the move costs for subclasses; regclass will work out
10975 the maximum for us. */
10978 mips_register_move_cost (enum machine_mode mode,
10979 reg_class_t from, reg_class_t to)
10984 from = mips_canonicalize_move_class (from);
10985 to = mips_canonicalize_move_class (to);
10987 /* Handle moves that can be done without using general-purpose registers. */
10988 if (from == FP_REGS)
10990 if (to == FP_REGS && mips_mode_ok_for_mov_fmt_p (mode))
10994 /* The sequence generated by mips_expand_fcc_reload. */
10998 /* Handle cases in which only one class deviates from the ideal. */
10999 dregs = TARGET_MIPS16 ? M16_REGS : GENERAL_REGS;
11001 return mips_move_from_gpr_cost (mode, to);
11003 return mips_move_to_gpr_cost (mode, from);
11005 /* Handles cases that require a GPR temporary. */
11006 cost1 = mips_move_to_gpr_cost (mode, from);
11009 cost2 = mips_move_from_gpr_cost (mode, to);
11011 return cost1 + cost2;
11017 /* Implement TARGET_MEMORY_MOVE_COST. */
11020 mips_memory_move_cost (enum machine_mode mode, reg_class_t rclass, bool in)
11022 return (mips_cost->memory_latency
11023 + memory_move_secondary_cost (mode, rclass, in));
11026 /* Return the register class required for a secondary register when
11027 copying between one of the registers in RCLASS and value X, which
11028 has mode MODE. X is the source of the move if IN_P, otherwise it
11029 is the destination. Return NO_REGS if no secondary register is
11033 mips_secondary_reload_class (enum reg_class rclass,
11034 enum machine_mode mode, rtx x, bool in_p)
11038 /* If X is a constant that cannot be loaded into $25, it must be loaded
11039 into some other GPR. No other register class allows a direct move. */
11040 if (mips_dangerous_for_la25_p (x))
11041 return reg_class_subset_p (rclass, LEA_REGS) ? NO_REGS : LEA_REGS;
11043 regno = true_regnum (x);
11046 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
11047 if (!reg_class_subset_p (rclass, M16_REGS) && !M16_REG_P (regno))
11053 /* Copying from accumulator registers to anywhere other than a general
11054 register requires a temporary general register. */
11055 if (reg_class_subset_p (rclass, ACC_REGS))
11056 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
11057 if (ACC_REG_P (regno))
11058 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
11060 /* We can only copy a value to a condition code register from a
11061 floating-point register, and even then we require a scratch
11062 floating-point register. We can only copy a value out of a
11063 condition-code register into a general register. */
11064 if (reg_class_subset_p (rclass, ST_REGS))
11068 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
11070 if (ST_REG_P (regno))
11074 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
11077 if (reg_class_subset_p (rclass, FP_REGS))
11080 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8))
11081 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
11082 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
11085 if (GP_REG_P (regno) || x == CONST0_RTX (mode))
11086 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
11089 if (CONSTANT_P (x) && !targetm.cannot_force_const_mem (x))
11090 /* We can force the constant to memory and use lwc1
11091 and ldc1. As above, we will use pairs of lwc1s if
11092 ldc1 is not supported. */
11095 if (FP_REG_P (regno) && mips_mode_ok_for_mov_fmt_p (mode))
11096 /* In this case we can use mov.fmt. */
11099 /* Otherwise, we need to reload through an integer register. */
11102 if (FP_REG_P (regno))
11103 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
11108 /* Implement TARGET_MODE_REP_EXTENDED. */
11111 mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
11113 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
11114 if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
11115 return SIGN_EXTEND;
11120 /* Implement TARGET_VALID_POINTER_MODE. */
11123 mips_valid_pointer_mode (enum machine_mode mode)
11125 return mode == SImode || (TARGET_64BIT && mode == DImode);
11128 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
11131 mips_vector_mode_supported_p (enum machine_mode mode)
11136 return TARGET_PAIRED_SINGLE_FLOAT;
11151 return TARGET_LOONGSON_VECTORS;
11158 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
11161 mips_scalar_mode_supported_p (enum machine_mode mode)
11163 if (ALL_FIXED_POINT_MODE_P (mode)
11164 && GET_MODE_PRECISION (mode) <= 2 * BITS_PER_WORD)
11167 return default_scalar_mode_supported_p (mode);
11170 /* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
11172 static enum machine_mode
11173 mips_preferred_simd_mode (enum machine_mode mode ATTRIBUTE_UNUSED)
11175 if (TARGET_PAIRED_SINGLE_FLOAT
11181 /* Implement TARGET_INIT_LIBFUNCS. */
11184 mips_init_libfuncs (void)
11186 if (TARGET_FIX_VR4120)
11188 /* Register the special divsi3 and modsi3 functions needed to work
11189 around VR4120 division errata. */
11190 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
11191 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
11194 if (TARGET_MIPS16 && TARGET_HARD_FLOAT_ABI)
11196 /* Register the MIPS16 -mhard-float stubs. */
11197 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
11198 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
11199 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
11200 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
11202 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
11203 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
11204 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
11205 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
11206 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
11207 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
11208 set_optab_libfunc (unord_optab, SFmode, "__mips16_unordsf2");
11210 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
11211 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
11212 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__mips16_floatunsisf");
11214 if (TARGET_DOUBLE_FLOAT)
11216 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
11217 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
11218 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
11219 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
11221 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
11222 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
11223 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
11224 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
11225 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
11226 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
11227 set_optab_libfunc (unord_optab, DFmode, "__mips16_unorddf2");
11229 set_conv_libfunc (sext_optab, DFmode, SFmode,
11230 "__mips16_extendsfdf2");
11231 set_conv_libfunc (trunc_optab, SFmode, DFmode,
11232 "__mips16_truncdfsf2");
11233 set_conv_libfunc (sfix_optab, SImode, DFmode,
11234 "__mips16_fix_truncdfsi");
11235 set_conv_libfunc (sfloat_optab, DFmode, SImode,
11236 "__mips16_floatsidf");
11237 set_conv_libfunc (ufloat_optab, DFmode, SImode,
11238 "__mips16_floatunsidf");
11242 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
11243 on an external non-MIPS16 routine to implement __sync_synchronize. */
11245 synchronize_libfunc = init_one_libfunc ("__sync_synchronize");
11248 /* Build up a multi-insn sequence that loads label TARGET into $AT. */
11251 mips_process_load_label (rtx target)
11253 rtx base, gp, intop;
11254 HOST_WIDE_INT offset;
11256 mips_multi_start ();
11260 mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target, 0);
11261 mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target, 0);
11265 mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target, 0);
11266 mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target, 0);
11270 gp = pic_offset_table_rtx;
11271 if (mips_cfun_has_cprestore_slot_p ())
11273 gp = gen_rtx_REG (Pmode, AT_REGNUM);
11274 mips_get_cprestore_base_and_offset (&base, &offset, true);
11275 if (!SMALL_OPERAND (offset))
11277 intop = GEN_INT (CONST_HIGH_PART (offset));
11278 mips_multi_add_insn ("lui\t%0,%1", gp, intop, 0);
11279 mips_multi_add_insn ("addu\t%0,%0,%1", gp, base, 0);
11282 offset = CONST_LOW_PART (offset);
11284 intop = GEN_INT (offset);
11285 if (ISA_HAS_LOAD_DELAY)
11286 mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp, intop, base, 0);
11288 mips_multi_add_insn ("lw\t%0,%1(%2)", gp, intop, base, 0);
11290 if (ISA_HAS_LOAD_DELAY)
11291 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target, gp, 0);
11293 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target, gp, 0);
11294 mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target, 0);
11299 /* Return the number of instructions needed to load a label into $AT. */
11301 static unsigned int
11302 mips_load_label_num_insns (void)
11304 if (cfun->machine->load_label_num_insns == 0)
11306 mips_process_load_label (pc_rtx);
11307 cfun->machine->load_label_num_insns = mips_multi_num_insns;
11309 return cfun->machine->load_label_num_insns;
11312 /* Emit an asm sequence to start a noat block and load the address
11313 of a label into $1. */
11316 mips_output_load_label (rtx target)
11318 mips_push_asm_switch (&mips_noat);
11319 if (TARGET_EXPLICIT_RELOCS)
11321 mips_process_load_label (target);
11322 mips_multi_write ();
11326 if (Pmode == DImode)
11327 output_asm_insn ("dla\t%@,%0", &target);
11329 output_asm_insn ("la\t%@,%0", &target);
11333 /* Return the length of INSN. LENGTH is the initial length computed by
11334 attributes in the machine-description file. */
11337 mips_adjust_insn_length (rtx insn, int length)
11339 /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length
11340 of a PIC long-branch sequence. Substitute the correct value. */
11341 if (length == MAX_PIC_BRANCH_LENGTH
11342 && INSN_CODE (insn) >= 0
11343 && get_attr_type (insn) == TYPE_BRANCH)
11345 /* Add the branch-over instruction and its delay slot, if this
11346 is a conditional branch. */
11347 length = simplejump_p (insn) ? 0 : 8;
11349 /* Load the label into $AT and jump to it. Ignore the delay
11350 slot of the jump. */
11351 length += 4 * mips_load_label_num_insns() + 4;
11354 /* A unconditional jump has an unfilled delay slot if it is not part
11355 of a sequence. A conditional jump normally has a delay slot, but
11356 does not on MIPS16. */
11357 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
11360 /* See how many nops might be needed to avoid hardware hazards. */
11361 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
11362 switch (get_attr_hazard (insn))
11376 /* In order to make it easier to share MIPS16 and non-MIPS16 patterns,
11377 the .md file length attributes are 4-based for both modes.
11378 Adjust the MIPS16 ones here. */
11385 /* Return the assembly code for INSN, which has the operands given by
11386 OPERANDS, and which branches to OPERANDS[0] if some condition is true.
11387 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0]
11388 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
11389 version of BRANCH_IF_TRUE. */
11392 mips_output_conditional_branch (rtx insn, rtx *operands,
11393 const char *branch_if_true,
11394 const char *branch_if_false)
11396 unsigned int length;
11397 rtx taken, not_taken;
11399 gcc_assert (LABEL_P (operands[0]));
11401 length = get_attr_length (insn);
11404 /* Just a simple conditional branch. */
11405 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
11406 return branch_if_true;
11409 /* Generate a reversed branch around a direct jump. This fallback does
11410 not use branch-likely instructions. */
11411 mips_branch_likely = false;
11412 not_taken = gen_label_rtx ();
11413 taken = operands[0];
11415 /* Generate the reversed branch to NOT_TAKEN. */
11416 operands[0] = not_taken;
11417 output_asm_insn (branch_if_false, operands);
11419 /* If INSN has a delay slot, we must provide delay slots for both the
11420 branch to NOT_TAKEN and the conditional jump. We must also ensure
11421 that INSN's delay slot is executed in the appropriate cases. */
11422 if (final_sequence)
11424 /* This first delay slot will always be executed, so use INSN's
11425 delay slot if is not annulled. */
11426 if (!INSN_ANNULLED_BRANCH_P (insn))
11428 final_scan_insn (XVECEXP (final_sequence, 0, 1),
11429 asm_out_file, optimize, 1, NULL);
11430 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
11433 output_asm_insn ("nop", 0);
11434 fprintf (asm_out_file, "\n");
11437 /* Output the unconditional branch to TAKEN. */
11438 if (TARGET_ABSOLUTE_JUMPS)
11439 output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken);
11442 mips_output_load_label (taken);
11443 output_asm_insn ("jr\t%@%]%/", 0);
11446 /* Now deal with its delay slot; see above. */
11447 if (final_sequence)
11449 /* This delay slot will only be executed if the branch is taken.
11450 Use INSN's delay slot if is annulled. */
11451 if (INSN_ANNULLED_BRANCH_P (insn))
11453 final_scan_insn (XVECEXP (final_sequence, 0, 1),
11454 asm_out_file, optimize, 1, NULL);
11455 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
11458 output_asm_insn ("nop", 0);
11459 fprintf (asm_out_file, "\n");
11462 /* Output NOT_TAKEN. */
11463 targetm.asm_out.internal_label (asm_out_file, "L",
11464 CODE_LABEL_NUMBER (not_taken));
11468 /* Return the assembly code for INSN, which branches to OPERANDS[0]
11469 if some ordering condition is true. The condition is given by
11470 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
11471 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
11472 its second is always zero. */
11475 mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
11477 const char *branch[2];
11479 /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true.
11480 Make BRANCH[0] branch on the inverse condition. */
11481 switch (GET_CODE (operands[1]))
11483 /* These cases are equivalent to comparisons against zero. */
11485 inverted_p = !inverted_p;
11486 /* Fall through. */
11488 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%0");
11489 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%0");
11492 /* These cases are always true or always false. */
11494 inverted_p = !inverted_p;
11495 /* Fall through. */
11497 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%0");
11498 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%0");
11502 branch[!inverted_p] = MIPS_BRANCH ("b%C1z", "%2,%0");
11503 branch[inverted_p] = MIPS_BRANCH ("b%N1z", "%2,%0");
11506 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
11509 /* Start a block of code that needs access to the LL, SC and SYNC
11513 mips_start_ll_sc_sync_block (void)
11515 if (!ISA_HAS_LL_SC)
11517 output_asm_insn (".set\tpush", 0);
11518 output_asm_insn (".set\tmips2", 0);
11522 /* End a block started by mips_start_ll_sc_sync_block. */
11525 mips_end_ll_sc_sync_block (void)
11527 if (!ISA_HAS_LL_SC)
11528 output_asm_insn (".set\tpop", 0);
11531 /* Output and/or return the asm template for a sync instruction. */
11534 mips_output_sync (void)
11536 mips_start_ll_sc_sync_block ();
11537 output_asm_insn ("sync", 0);
11538 mips_end_ll_sc_sync_block ();
11542 /* Return the asm template associated with sync_insn1 value TYPE.
11543 IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */
11545 static const char *
11546 mips_sync_insn1_template (enum attr_sync_insn1 type, bool is_64bit_p)
11550 case SYNC_INSN1_MOVE:
11551 return "move\t%0,%z2";
11552 case SYNC_INSN1_LI:
11553 return "li\t%0,%2";
11554 case SYNC_INSN1_ADDU:
11555 return is_64bit_p ? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2";
11556 case SYNC_INSN1_ADDIU:
11557 return is_64bit_p ? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2";
11558 case SYNC_INSN1_SUBU:
11559 return is_64bit_p ? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2";
11560 case SYNC_INSN1_AND:
11561 return "and\t%0,%1,%z2";
11562 case SYNC_INSN1_ANDI:
11563 return "andi\t%0,%1,%2";
11564 case SYNC_INSN1_OR:
11565 return "or\t%0,%1,%z2";
11566 case SYNC_INSN1_ORI:
11567 return "ori\t%0,%1,%2";
11568 case SYNC_INSN1_XOR:
11569 return "xor\t%0,%1,%z2";
11570 case SYNC_INSN1_XORI:
11571 return "xori\t%0,%1,%2";
11573 gcc_unreachable ();
11576 /* Return the asm template associated with sync_insn2 value TYPE. */
11578 static const char *
11579 mips_sync_insn2_template (enum attr_sync_insn2 type)
11583 case SYNC_INSN2_NOP:
11584 gcc_unreachable ();
11585 case SYNC_INSN2_AND:
11586 return "and\t%0,%1,%z2";
11587 case SYNC_INSN2_XOR:
11588 return "xor\t%0,%1,%z2";
11589 case SYNC_INSN2_NOT:
11590 return "nor\t%0,%1,%.";
11592 gcc_unreachable ();
11595 /* OPERANDS are the operands to a sync loop instruction and INDEX is
11596 the value of the one of the sync_* attributes. Return the operand
11597 referred to by the attribute, or DEFAULT_VALUE if the insn doesn't
11598 have the associated attribute. */
11601 mips_get_sync_operand (rtx *operands, int index, rtx default_value)
11604 default_value = operands[index - 1];
11605 return default_value;
11608 /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn
11609 sequence for it. */
11612 mips_process_sync_loop (rtx insn, rtx *operands)
11614 rtx at, mem, oldval, newval, inclusive_mask, exclusive_mask;
11615 rtx required_oldval, insn1_op2, tmp1, tmp2, tmp3;
11616 unsigned int tmp3_insn;
11617 enum attr_sync_insn1 insn1;
11618 enum attr_sync_insn2 insn2;
11621 /* Read an operand from the sync_WHAT attribute and store it in
11622 variable WHAT. DEFAULT is the default value if no attribute
11624 #define READ_OPERAND(WHAT, DEFAULT) \
11625 WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \
11628 /* Read the memory. */
11629 READ_OPERAND (mem, 0);
11631 is_64bit_p = (GET_MODE_BITSIZE (GET_MODE (mem)) == 64);
11633 /* Read the other attributes. */
11634 at = gen_rtx_REG (GET_MODE (mem), AT_REGNUM);
11635 READ_OPERAND (oldval, at);
11636 READ_OPERAND (newval, at);
11637 READ_OPERAND (inclusive_mask, 0);
11638 READ_OPERAND (exclusive_mask, 0);
11639 READ_OPERAND (required_oldval, 0);
11640 READ_OPERAND (insn1_op2, 0);
11641 insn1 = get_attr_sync_insn1 (insn);
11642 insn2 = get_attr_sync_insn2 (insn);
11644 mips_multi_start ();
11646 /* Output the release side of the memory barrier. */
11647 if (get_attr_sync_release_barrier (insn) == SYNC_RELEASE_BARRIER_YES)
11649 if (required_oldval == 0 && TARGET_OCTEON)
11651 /* Octeon doesn't reorder reads, so a full barrier can be
11652 created by using SYNCW to order writes combined with the
11653 write from the following SC. When the SC successfully
11654 completes, we know that all preceding writes are also
11655 committed to the coherent memory system. It is possible
11656 for a single SYNCW to fail, but a pair of them will never
11657 fail, so we use two. */
11658 mips_multi_add_insn ("syncw", NULL);
11659 mips_multi_add_insn ("syncw", NULL);
11662 mips_multi_add_insn ("sync", NULL);
11665 /* Output the branch-back label. */
11666 mips_multi_add_label ("1:");
11668 /* OLDVAL = *MEM. */
11669 mips_multi_add_insn (is_64bit_p ? "lld\t%0,%1" : "ll\t%0,%1",
11670 oldval, mem, NULL);
11672 /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */
11673 if (required_oldval)
11675 if (inclusive_mask == 0)
11679 gcc_assert (oldval != at);
11680 mips_multi_add_insn ("and\t%0,%1,%2",
11681 at, oldval, inclusive_mask, NULL);
11684 mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1, required_oldval, NULL);
11687 /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */
11688 if (exclusive_mask == 0)
11692 gcc_assert (oldval != at);
11693 mips_multi_add_insn ("and\t%0,%1,%z2",
11694 at, oldval, exclusive_mask, NULL);
11698 /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2).
11700 We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit
11701 at least one instruction in that case. */
11702 if (insn1 == SYNC_INSN1_MOVE
11703 && (tmp1 != const0_rtx || insn2 != SYNC_INSN2_NOP))
11707 mips_multi_add_insn (mips_sync_insn1_template (insn1, is_64bit_p),
11708 newval, oldval, insn1_op2, NULL);
11712 /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */
11713 if (insn2 == SYNC_INSN2_NOP)
11717 mips_multi_add_insn (mips_sync_insn2_template (insn2),
11718 newval, tmp2, inclusive_mask, NULL);
11721 tmp3_insn = mips_multi_last_index ();
11723 /* $AT = $TMP1 | $TMP3. */
11724 if (tmp1 == const0_rtx || tmp3 == const0_rtx)
11726 mips_multi_set_operand (tmp3_insn, 0, at);
11731 gcc_assert (tmp1 != tmp3);
11732 mips_multi_add_insn ("or\t%0,%1,%2", at, tmp1, tmp3, NULL);
11735 /* if (!commit (*MEM = $AT)) goto 1.
11737 This will sometimes be a delayed branch; see the write code below
11739 mips_multi_add_insn (is_64bit_p ? "scd\t%0,%1" : "sc\t%0,%1", at, mem, NULL);
11740 mips_multi_add_insn ("beq%?\t%0,%.,1b", at, NULL);
11742 /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */
11743 if (insn1 != SYNC_INSN1_MOVE && insn1 != SYNC_INSN1_LI && tmp3 != newval)
11745 mips_multi_copy_insn (tmp3_insn);
11746 mips_multi_set_operand (mips_multi_last_index (), 0, newval);
11749 mips_multi_add_insn ("nop", NULL);
11751 /* Output the acquire side of the memory barrier. */
11752 if (TARGET_SYNC_AFTER_SC)
11753 mips_multi_add_insn ("sync", NULL);
11755 /* Output the exit label, if needed. */
11756 if (required_oldval)
11757 mips_multi_add_label ("2:");
11759 #undef READ_OPERAND
11762 /* Output and/or return the asm template for sync loop INSN, which has
11763 the operands given by OPERANDS. */
11766 mips_output_sync_loop (rtx insn, rtx *operands)
11768 mips_process_sync_loop (insn, operands);
11770 /* Use branch-likely instructions to work around the LL/SC R10000
11772 mips_branch_likely = TARGET_FIX_R10000;
11774 mips_push_asm_switch (&mips_noreorder);
11775 mips_push_asm_switch (&mips_nomacro);
11776 mips_push_asm_switch (&mips_noat);
11777 mips_start_ll_sc_sync_block ();
11779 mips_multi_write ();
11781 mips_end_ll_sc_sync_block ();
11782 mips_pop_asm_switch (&mips_noat);
11783 mips_pop_asm_switch (&mips_nomacro);
11784 mips_pop_asm_switch (&mips_noreorder);
11789 /* Return the number of individual instructions in sync loop INSN,
11790 which has the operands given by OPERANDS. */
11793 mips_sync_loop_insns (rtx insn, rtx *operands)
11795 mips_process_sync_loop (insn, operands);
11796 return mips_multi_num_insns;
11799 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
11800 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
11802 When working around R4000 and R4400 errata, we need to make sure that
11803 the division is not immediately followed by a shift[1][2]. We also
11804 need to stop the division from being put into a branch delay slot[3].
11805 The easiest way to avoid both problems is to add a nop after the
11806 division. When a divide-by-zero check is needed, this nop can be
11807 used to fill the branch delay slot.
11809 [1] If a double-word or a variable shift executes immediately
11810 after starting an integer division, the shift may give an
11811 incorrect result. See quotations of errata #16 and #28 from
11812 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
11813 in mips.md for details.
11815 [2] A similar bug to [1] exists for all revisions of the
11816 R4000 and the R4400 when run in an MC configuration.
11817 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
11819 "19. In this following sequence:
11821 ddiv (or ddivu or div or divu)
11822 dsll32 (or dsrl32, dsra32)
11824 if an MPT stall occurs, while the divide is slipping the cpu
11825 pipeline, then the following double shift would end up with an
11828 Workaround: The compiler needs to avoid generating any
11829 sequence with divide followed by extended double shift."
11831 This erratum is also present in "MIPS R4400MC Errata, Processor
11832 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
11833 & 3.0" as errata #10 and #4, respectively.
11835 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
11836 (also valid for MIPS R4000MC processors):
11838 "52. R4000SC: This bug does not apply for the R4000PC.
11840 There are two flavors of this bug:
11842 1) If the instruction just after divide takes an RF exception
11843 (tlb-refill, tlb-invalid) and gets an instruction cache
11844 miss (both primary and secondary) and the line which is
11845 currently in secondary cache at this index had the first
11846 data word, where the bits 5..2 are set, then R4000 would
11847 get a wrong result for the div.
11852 ------------------- # end-of page. -tlb-refill
11857 ------------------- # end-of page. -tlb-invalid
11860 2) If the divide is in the taken branch delay slot, where the
11861 target takes RF exception and gets an I-cache miss for the
11862 exception vector or where I-cache miss occurs for the
11863 target address, under the above mentioned scenarios, the
11864 div would get wrong results.
11867 j r2 # to next page mapped or unmapped
11868 div r8,r9 # this bug would be there as long
11869 # as there is an ICache miss and
11870 nop # the "data pattern" is present
11873 beq r0, r0, NextPage # to Next page
11877 This bug is present for div, divu, ddiv, and ddivu
11880 Workaround: For item 1), OS could make sure that the next page
11881 after the divide instruction is also mapped. For item 2), the
11882 compiler could make sure that the divide instruction is not in
11883 the branch delay slot."
11885 These processors have PRId values of 0x00004220 and 0x00004300 for
11886 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
11889 mips_output_division (const char *division, rtx *operands)
11894 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
11896 output_asm_insn (s, operands);
11899 if (TARGET_CHECK_ZERO_DIV)
11903 output_asm_insn (s, operands);
11904 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
11906 else if (GENERATE_DIVIDE_TRAPS)
11908 /* Avoid long replay penalty on load miss by putting the trap before
11911 output_asm_insn ("teq\t%2,%.,7", operands);
11914 output_asm_insn (s, operands);
11915 s = "teq\t%2,%.,7";
11920 output_asm_insn ("%(bne\t%2,%.,1f", operands);
11921 output_asm_insn (s, operands);
11922 s = "break\t7%)\n1:";
11928 /* Return true if IN_INSN is a multiply-add or multiply-subtract
11929 instruction and if OUT_INSN assigns to the accumulator operand. */
11932 mips_linked_madd_p (rtx out_insn, rtx in_insn)
11936 x = single_set (in_insn);
11942 if (GET_CODE (x) == PLUS
11943 && GET_CODE (XEXP (x, 0)) == MULT
11944 && reg_set_p (XEXP (x, 1), out_insn))
11947 if (GET_CODE (x) == MINUS
11948 && GET_CODE (XEXP (x, 1)) == MULT
11949 && reg_set_p (XEXP (x, 0), out_insn))
11955 /* True if the dependency between OUT_INSN and IN_INSN is on the store
11956 data rather than the address. We need this because the cprestore
11957 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
11958 which causes the default routine to abort. We just return false
11962 mips_store_data_bypass_p (rtx out_insn, rtx in_insn)
11964 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
11967 return !store_data_bypass_p (out_insn, in_insn);
11971 /* Variables and flags used in scheduler hooks when tuning for
11975 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
11978 /* If true, then next ALU1/2 instruction will go to ALU1. */
11981 /* If true, then next FALU1/2 unstruction will go to FALU1. */
11984 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
11985 int alu1_core_unit_code;
11986 int alu2_core_unit_code;
11987 int falu1_core_unit_code;
11988 int falu2_core_unit_code;
11990 /* True if current cycle has a multi instruction.
11991 This flag is used in mips_ls2_dfa_post_advance_cycle. */
11992 bool cycle_has_multi_p;
11994 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
11995 These are used in mips_ls2_dfa_post_advance_cycle to initialize
11997 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
11998 instruction to go ALU1. */
11999 rtx alu1_turn_enabled_insn;
12000 rtx alu2_turn_enabled_insn;
12001 rtx falu1_turn_enabled_insn;
12002 rtx falu2_turn_enabled_insn;
12005 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
12006 dependencies have no cost, except on the 20Kc where output-dependence
12007 is treated like input-dependence. */
12010 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
12011 rtx dep ATTRIBUTE_UNUSED, int cost)
12013 if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT
12016 if (REG_NOTE_KIND (link) != 0)
12021 /* Return the number of instructions that can be issued per cycle. */
12024 mips_issue_rate (void)
12028 case PROCESSOR_74KC:
12029 case PROCESSOR_74KF2_1:
12030 case PROCESSOR_74KF1_1:
12031 case PROCESSOR_74KF3_2:
12032 /* The 74k is not strictly quad-issue cpu, but can be seen as one
12033 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
12034 but in reality only a maximum of 3 insns can be issued as
12035 floating-point loads and stores also require a slot in the
12037 case PROCESSOR_R10000:
12038 /* All R10K Processors are quad-issue (being the first MIPS
12039 processors to support this feature). */
12042 case PROCESSOR_20KC:
12043 case PROCESSOR_R4130:
12044 case PROCESSOR_R5400:
12045 case PROCESSOR_R5500:
12046 case PROCESSOR_R7000:
12047 case PROCESSOR_R9000:
12048 case PROCESSOR_OCTEON:
12051 case PROCESSOR_SB1:
12052 case PROCESSOR_SB1A:
12053 /* This is actually 4, but we get better performance if we claim 3.
12054 This is partly because of unwanted speculative code motion with the
12055 larger number, and partly because in most common cases we can't
12056 reach the theoretical max of 4. */
12059 case PROCESSOR_LOONGSON_2E:
12060 case PROCESSOR_LOONGSON_2F:
12061 case PROCESSOR_LOONGSON_3A:
12069 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
12072 mips_ls2_init_dfa_post_cycle_insn (void)
12075 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
12076 mips_ls2.alu1_turn_enabled_insn = get_insns ();
12080 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
12081 mips_ls2.alu2_turn_enabled_insn = get_insns ();
12085 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
12086 mips_ls2.falu1_turn_enabled_insn = get_insns ();
12090 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
12091 mips_ls2.falu2_turn_enabled_insn = get_insns ();
12094 mips_ls2.alu1_core_unit_code = get_cpu_unit_code ("ls2_alu1_core");
12095 mips_ls2.alu2_core_unit_code = get_cpu_unit_code ("ls2_alu2_core");
12096 mips_ls2.falu1_core_unit_code = get_cpu_unit_code ("ls2_falu1_core");
12097 mips_ls2.falu2_core_unit_code = get_cpu_unit_code ("ls2_falu2_core");
12100 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
12101 Init data used in mips_dfa_post_advance_cycle. */
12104 mips_init_dfa_post_cycle_insn (void)
12106 if (TUNE_LOONGSON_2EF)
12107 mips_ls2_init_dfa_post_cycle_insn ();
12110 /* Initialize STATE when scheduling for Loongson 2E/2F.
12111 Support round-robin dispatch scheme by enabling only one of
12112 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
12116 mips_ls2_dfa_post_advance_cycle (state_t state)
12118 if (cpu_unit_reservation_p (state, mips_ls2.alu1_core_unit_code))
12120 /* Though there are no non-pipelined ALU1 insns,
12121 we can get an instruction of type 'multi' before reload. */
12122 gcc_assert (mips_ls2.cycle_has_multi_p);
12123 mips_ls2.alu1_turn_p = false;
12126 mips_ls2.cycle_has_multi_p = false;
12128 if (cpu_unit_reservation_p (state, mips_ls2.alu2_core_unit_code))
12129 /* We have a non-pipelined alu instruction in the core,
12130 adjust round-robin counter. */
12131 mips_ls2.alu1_turn_p = true;
12133 if (mips_ls2.alu1_turn_p)
12135 if (state_transition (state, mips_ls2.alu1_turn_enabled_insn) >= 0)
12136 gcc_unreachable ();
12140 if (state_transition (state, mips_ls2.alu2_turn_enabled_insn) >= 0)
12141 gcc_unreachable ();
12144 if (cpu_unit_reservation_p (state, mips_ls2.falu1_core_unit_code))
12146 /* There are no non-pipelined FALU1 insns. */
12147 gcc_unreachable ();
12148 mips_ls2.falu1_turn_p = false;
12151 if (cpu_unit_reservation_p (state, mips_ls2.falu2_core_unit_code))
12152 /* We have a non-pipelined falu instruction in the core,
12153 adjust round-robin counter. */
12154 mips_ls2.falu1_turn_p = true;
12156 if (mips_ls2.falu1_turn_p)
12158 if (state_transition (state, mips_ls2.falu1_turn_enabled_insn) >= 0)
12159 gcc_unreachable ();
12163 if (state_transition (state, mips_ls2.falu2_turn_enabled_insn) >= 0)
12164 gcc_unreachable ();
12168 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
12169 This hook is being called at the start of each cycle. */
12172 mips_dfa_post_advance_cycle (void)
12174 if (TUNE_LOONGSON_2EF)
12175 mips_ls2_dfa_post_advance_cycle (curr_state);
12178 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
12179 be as wide as the scheduling freedom in the DFA. */
12182 mips_multipass_dfa_lookahead (void)
12184 /* Can schedule up to 4 of the 6 function units in any one cycle. */
12188 if (TUNE_LOONGSON_2EF || TUNE_LOONGSON_3A)
12197 /* Remove the instruction at index LOWER from ready queue READY and
12198 reinsert it in front of the instruction at index HIGHER. LOWER must
12202 mips_promote_ready (rtx *ready, int lower, int higher)
12207 new_head = ready[lower];
12208 for (i = lower; i < higher; i++)
12209 ready[i] = ready[i + 1];
12210 ready[i] = new_head;
12213 /* If the priority of the instruction at POS2 in the ready queue READY
12214 is within LIMIT units of that of the instruction at POS1, swap the
12215 instructions if POS2 is not already less than POS1. */
12218 mips_maybe_swap_ready (rtx *ready, int pos1, int pos2, int limit)
12221 && INSN_PRIORITY (ready[pos1]) + limit >= INSN_PRIORITY (ready[pos2]))
12225 temp = ready[pos1];
12226 ready[pos1] = ready[pos2];
12227 ready[pos2] = temp;
12231 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
12232 that may clobber hi or lo. */
12233 static rtx mips_macc_chains_last_hilo;
12235 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
12236 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
12239 mips_macc_chains_record (rtx insn)
12241 if (get_attr_may_clobber_hilo (insn))
12242 mips_macc_chains_last_hilo = insn;
12245 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
12246 has NREADY elements, looking for a multiply-add or multiply-subtract
12247 instruction that is cumulative with mips_macc_chains_last_hilo.
12248 If there is one, promote it ahead of anything else that might
12249 clobber hi or lo. */
12252 mips_macc_chains_reorder (rtx *ready, int nready)
12256 if (mips_macc_chains_last_hilo != 0)
12257 for (i = nready - 1; i >= 0; i--)
12258 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
12260 for (j = nready - 1; j > i; j--)
12261 if (recog_memoized (ready[j]) >= 0
12262 && get_attr_may_clobber_hilo (ready[j]))
12264 mips_promote_ready (ready, i, j);
12271 /* The last instruction to be scheduled. */
12272 static rtx vr4130_last_insn;
12274 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
12275 points to an rtx that is initially an instruction. Nullify the rtx
12276 if the instruction uses the value of register X. */
12279 vr4130_true_reg_dependence_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
12284 insn_ptr = (rtx *) data;
12287 && reg_referenced_p (x, PATTERN (*insn_ptr)))
12291 /* Return true if there is true register dependence between vr4130_last_insn
12295 vr4130_true_reg_dependence_p (rtx insn)
12297 note_stores (PATTERN (vr4130_last_insn),
12298 vr4130_true_reg_dependence_p_1, &insn);
12302 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
12303 the ready queue and that INSN2 is the instruction after it, return
12304 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
12305 in which INSN1 and INSN2 can probably issue in parallel, but for
12306 which (INSN2, INSN1) should be less sensitive to instruction
12307 alignment than (INSN1, INSN2). See 4130.md for more details. */
12310 vr4130_swap_insns_p (rtx insn1, rtx insn2)
12312 sd_iterator_def sd_it;
12315 /* Check for the following case:
12317 1) there is some other instruction X with an anti dependence on INSN1;
12318 2) X has a higher priority than INSN2; and
12319 3) X is an arithmetic instruction (and thus has no unit restrictions).
12321 If INSN1 is the last instruction blocking X, it would better to
12322 choose (INSN1, X) over (INSN2, INSN1). */
12323 FOR_EACH_DEP (insn1, SD_LIST_FORW, sd_it, dep)
12324 if (DEP_TYPE (dep) == REG_DEP_ANTI
12325 && INSN_PRIORITY (DEP_CON (dep)) > INSN_PRIORITY (insn2)
12326 && recog_memoized (DEP_CON (dep)) >= 0
12327 && get_attr_vr4130_class (DEP_CON (dep)) == VR4130_CLASS_ALU)
12330 if (vr4130_last_insn != 0
12331 && recog_memoized (insn1) >= 0
12332 && recog_memoized (insn2) >= 0)
12334 /* See whether INSN1 and INSN2 use different execution units,
12335 or if they are both ALU-type instructions. If so, they can
12336 probably execute in parallel. */
12337 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
12338 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
12339 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
12341 /* If only one of the instructions has a dependence on
12342 vr4130_last_insn, prefer to schedule the other one first. */
12343 bool dep1_p = vr4130_true_reg_dependence_p (insn1);
12344 bool dep2_p = vr4130_true_reg_dependence_p (insn2);
12345 if (dep1_p != dep2_p)
12348 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
12349 is not an ALU-type instruction and if INSN1 uses the same
12350 execution unit. (Note that if this condition holds, we already
12351 know that INSN2 uses a different execution unit.) */
12352 if (class1 != VR4130_CLASS_ALU
12353 && recog_memoized (vr4130_last_insn) >= 0
12354 && class1 == get_attr_vr4130_class (vr4130_last_insn))
12361 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
12362 queue with at least two instructions. Swap the first two if
12363 vr4130_swap_insns_p says that it could be worthwhile. */
12366 vr4130_reorder (rtx *ready, int nready)
12368 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
12369 mips_promote_ready (ready, nready - 2, nready - 1);
12372 /* Record whether last 74k AGEN instruction was a load or store. */
12373 static enum attr_type mips_last_74k_agen_insn = TYPE_UNKNOWN;
12375 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
12376 resets to TYPE_UNKNOWN state. */
12379 mips_74k_agen_init (rtx insn)
12381 if (!insn || CALL_P (insn) || JUMP_P (insn))
12382 mips_last_74k_agen_insn = TYPE_UNKNOWN;
12385 enum attr_type type = get_attr_type (insn);
12386 if (type == TYPE_LOAD || type == TYPE_STORE)
12387 mips_last_74k_agen_insn = type;
12391 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
12392 loads to be grouped together, and multiple stores to be grouped
12393 together. Swap things around in the ready queue to make this happen. */
12396 mips_74k_agen_reorder (rtx *ready, int nready)
12399 int store_pos, load_pos;
12404 for (i = nready - 1; i >= 0; i--)
12406 rtx insn = ready[i];
12407 if (USEFUL_INSN_P (insn))
12408 switch (get_attr_type (insn))
12411 if (store_pos == -1)
12416 if (load_pos == -1)
12425 if (load_pos == -1 || store_pos == -1)
12428 switch (mips_last_74k_agen_insn)
12431 /* Prefer to schedule loads since they have a higher latency. */
12433 /* Swap loads to the front of the queue. */
12434 mips_maybe_swap_ready (ready, load_pos, store_pos, 4);
12437 /* Swap stores to the front of the queue. */
12438 mips_maybe_swap_ready (ready, store_pos, load_pos, 4);
12445 /* Implement TARGET_SCHED_INIT. */
12448 mips_sched_init (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12449 int max_ready ATTRIBUTE_UNUSED)
12451 mips_macc_chains_last_hilo = 0;
12452 vr4130_last_insn = 0;
12453 mips_74k_agen_init (NULL_RTX);
12455 /* When scheduling for Loongson2, branch instructions go to ALU1,
12456 therefore basic block is most likely to start with round-robin counter
12457 pointed to ALU2. */
12458 mips_ls2.alu1_turn_p = false;
12459 mips_ls2.falu1_turn_p = true;
12462 /* Subroutine used by TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
12465 mips_sched_reorder_1 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12466 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
12468 if (!reload_completed
12469 && TUNE_MACC_CHAINS
12471 mips_macc_chains_reorder (ready, *nreadyp);
12473 if (reload_completed
12475 && !TARGET_VR4130_ALIGN
12477 vr4130_reorder (ready, *nreadyp);
12480 mips_74k_agen_reorder (ready, *nreadyp);
12483 /* Implement TARGET_SCHED_REORDER. */
12486 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12487 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
12489 mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle);
12490 return mips_issue_rate ();
12493 /* Implement TARGET_SCHED_REORDER2. */
12496 mips_sched_reorder2 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12497 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
12499 mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle);
12500 return cached_can_issue_more;
12503 /* Update round-robin counters for ALU1/2 and FALU1/2. */
12506 mips_ls2_variable_issue (rtx insn)
12508 if (mips_ls2.alu1_turn_p)
12510 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu1_core_unit_code))
12511 mips_ls2.alu1_turn_p = false;
12515 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu2_core_unit_code))
12516 mips_ls2.alu1_turn_p = true;
12519 if (mips_ls2.falu1_turn_p)
12521 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu1_core_unit_code))
12522 mips_ls2.falu1_turn_p = false;
12526 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu2_core_unit_code))
12527 mips_ls2.falu1_turn_p = true;
12530 if (recog_memoized (insn) >= 0)
12531 mips_ls2.cycle_has_multi_p |= (get_attr_type (insn) == TYPE_MULTI);
12534 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
12537 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12538 rtx insn, int more)
12540 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
12541 if (USEFUL_INSN_P (insn))
12543 if (get_attr_type (insn) != TYPE_GHOST)
12545 if (!reload_completed && TUNE_MACC_CHAINS)
12546 mips_macc_chains_record (insn);
12547 vr4130_last_insn = insn;
12549 mips_74k_agen_init (insn);
12550 else if (TUNE_LOONGSON_2EF)
12551 mips_ls2_variable_issue (insn);
12554 /* Instructions of type 'multi' should all be split before
12555 the second scheduling pass. */
12556 gcc_assert (!reload_completed
12557 || recog_memoized (insn) < 0
12558 || get_attr_type (insn) != TYPE_MULTI);
12560 cached_can_issue_more = more;
12564 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
12565 return the first operand of the associated PREF or PREFX insn. */
12568 mips_prefetch_cookie (rtx write, rtx locality)
12570 /* store_streamed / load_streamed. */
12571 if (INTVAL (locality) <= 0)
12572 return GEN_INT (INTVAL (write) + 4);
12574 /* store / load. */
12575 if (INTVAL (locality) <= 2)
12578 /* store_retained / load_retained. */
12579 return GEN_INT (INTVAL (write) + 6);
12582 /* Flags that indicate when a built-in function is available.
12584 BUILTIN_AVAIL_NON_MIPS16
12585 The function is available on the current target, but only
12586 in non-MIPS16 mode. */
12587 #define BUILTIN_AVAIL_NON_MIPS16 1
12589 /* Declare an availability predicate for built-in functions that
12590 require non-MIPS16 mode and also require COND to be true.
12591 NAME is the main part of the predicate's name. */
12592 #define AVAIL_NON_MIPS16(NAME, COND) \
12593 static unsigned int \
12594 mips_builtin_avail_##NAME (void) \
12596 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
12599 /* This structure describes a single built-in function. */
12600 struct mips_builtin_description {
12601 /* The code of the main .md file instruction. See mips_builtin_type
12602 for more information. */
12603 enum insn_code icode;
12605 /* The floating-point comparison code to use with ICODE, if any. */
12606 enum mips_fp_condition cond;
12608 /* The name of the built-in function. */
12611 /* Specifies how the function should be expanded. */
12612 enum mips_builtin_type builtin_type;
12614 /* The function's prototype. */
12615 enum mips_function_type function_type;
12617 /* Whether the function is available. */
12618 unsigned int (*avail) (void);
12621 AVAIL_NON_MIPS16 (paired_single, TARGET_PAIRED_SINGLE_FLOAT)
12622 AVAIL_NON_MIPS16 (sb1_paired_single, TARGET_SB1 && TARGET_PAIRED_SINGLE_FLOAT)
12623 AVAIL_NON_MIPS16 (mips3d, TARGET_MIPS3D)
12624 AVAIL_NON_MIPS16 (dsp, TARGET_DSP)
12625 AVAIL_NON_MIPS16 (dspr2, TARGET_DSPR2)
12626 AVAIL_NON_MIPS16 (dsp_32, !TARGET_64BIT && TARGET_DSP)
12627 AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2)
12628 AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS)
12629 AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
12631 /* Construct a mips_builtin_description from the given arguments.
12633 INSN is the name of the associated instruction pattern, without the
12634 leading CODE_FOR_mips_.
12636 CODE is the floating-point condition code associated with the
12637 function. It can be 'f' if the field is not applicable.
12639 NAME is the name of the function itself, without the leading
12642 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
12644 AVAIL is the name of the availability predicate, without the leading
12645 mips_builtin_avail_. */
12646 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
12647 FUNCTION_TYPE, AVAIL) \
12648 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
12649 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
12650 mips_builtin_avail_ ## AVAIL }
12652 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
12653 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
12654 are as for MIPS_BUILTIN. */
12655 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
12656 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
12658 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
12659 are subject to mips_builtin_avail_<AVAIL>. */
12660 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
12661 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
12662 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
12663 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
12664 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
12666 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
12667 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
12668 while the any and all forms are subject to mips_builtin_avail_mips3d. */
12669 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
12670 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
12671 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
12673 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
12674 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
12676 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
12677 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
12679 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
12680 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
12683 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
12684 are subject to mips_builtin_avail_mips3d. */
12685 #define CMP_4S_BUILTINS(INSN, COND) \
12686 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
12687 MIPS_BUILTIN_CMP_ANY, \
12688 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
12689 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
12690 MIPS_BUILTIN_CMP_ALL, \
12691 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
12693 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
12694 instruction requires mips_builtin_avail_<AVAIL>. */
12695 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
12696 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
12697 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
12699 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
12700 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
12703 /* Define all the built-in functions related to C.cond.fmt condition COND. */
12704 #define CMP_BUILTINS(COND) \
12705 MOVTF_BUILTINS (c, COND, paired_single), \
12706 MOVTF_BUILTINS (cabs, COND, mips3d), \
12707 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
12708 CMP_PS_BUILTINS (c, COND, paired_single), \
12709 CMP_PS_BUILTINS (cabs, COND, mips3d), \
12710 CMP_4S_BUILTINS (c, COND), \
12711 CMP_4S_BUILTINS (cabs, COND)
12713 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
12714 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
12715 and AVAIL are as for MIPS_BUILTIN. */
12716 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
12717 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
12718 FUNCTION_TYPE, AVAIL)
12720 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
12721 branch instruction. AVAIL is as for MIPS_BUILTIN. */
12722 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
12723 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
12724 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
12726 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
12727 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
12728 builtin_description field. */
12729 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
12730 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
12731 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
12732 FUNCTION_TYPE, mips_builtin_avail_loongson }
12734 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
12735 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
12736 builtin_description field. */
12737 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
12738 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
12740 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
12741 We use functions of this form when the same insn can be usefully applied
12742 to more than one datatype. */
12743 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
12744 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
12746 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
12747 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
12748 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
12749 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
12750 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
12751 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
12752 #define CODE_FOR_mips_mult CODE_FOR_mulsidi3_32bit
12753 #define CODE_FOR_mips_multu CODE_FOR_umulsidi3_32bit
12755 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
12756 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
12757 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
12758 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
12759 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
12760 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
12761 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
12762 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
12763 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
12764 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
12765 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
12766 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
12767 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
12768 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
12769 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
12770 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
12771 #define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3
12772 #define CODE_FOR_loongson_psllh CODE_FOR_ashlv4hi3
12773 #define CODE_FOR_loongson_psllw CODE_FOR_ashlv2si3
12774 #define CODE_FOR_loongson_psrlh CODE_FOR_lshrv4hi3
12775 #define CODE_FOR_loongson_psrlw CODE_FOR_lshrv2si3
12776 #define CODE_FOR_loongson_psrah CODE_FOR_ashrv4hi3
12777 #define CODE_FOR_loongson_psraw CODE_FOR_ashrv2si3
12778 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
12779 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
12780 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
12781 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
12782 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
12783 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
12784 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
12785 #define CODE_FOR_loongson_punpckhbh CODE_FOR_vec_interleave_highv8qi
12786 #define CODE_FOR_loongson_punpckhhw CODE_FOR_vec_interleave_highv4hi
12787 #define CODE_FOR_loongson_punpckhwd CODE_FOR_vec_interleave_highv2si
12788 #define CODE_FOR_loongson_punpcklbh CODE_FOR_vec_interleave_lowv8qi
12789 #define CODE_FOR_loongson_punpcklhw CODE_FOR_vec_interleave_lowv4hi
12790 #define CODE_FOR_loongson_punpcklwd CODE_FOR_vec_interleave_lowv2si
12792 static const struct mips_builtin_description mips_builtins[] = {
12793 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
12794 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
12795 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
12796 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
12797 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, paired_single),
12798 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, paired_single),
12799 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, paired_single),
12800 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, paired_single),
12802 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT, paired_single),
12803 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
12804 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
12805 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
12806 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, mips3d),
12808 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, mips3d),
12809 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, mips3d),
12810 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
12811 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
12812 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
12813 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
12815 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, mips3d),
12816 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, mips3d),
12817 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
12818 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
12819 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
12820 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
12822 MIPS_FP_CONDITIONS (CMP_BUILTINS),
12824 /* Built-in functions for the SB-1 processor. */
12825 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, sb1_paired_single),
12827 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
12828 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12829 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12830 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
12831 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12832 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12833 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12834 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12835 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
12836 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12837 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12838 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, dsp),
12839 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, dsp),
12840 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, dsp),
12841 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, dsp),
12842 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, dsp),
12843 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, dsp),
12844 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
12845 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
12846 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
12847 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
12848 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, dsp),
12849 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, dsp),
12850 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
12851 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
12852 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
12853 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
12854 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
12855 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
12856 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
12857 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
12858 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
12859 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
12860 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
12861 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
12862 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
12863 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
12864 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
12865 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, dsp),
12866 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
12867 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
12868 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12869 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
12870 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
12871 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, dsp),
12872 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, dsp),
12873 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, dsp),
12874 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, dsp),
12875 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
12876 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
12877 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
12878 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
12879 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
12880 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
12881 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
12882 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
12883 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
12884 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12885 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12886 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12887 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, dsp),
12888 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, dsp),
12889 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_POINTER_SI, dsp),
12890 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_POINTER_SI, dsp),
12891 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_POINTER_SI, dsp),
12892 BPOSGE_BUILTIN (32, dsp),
12894 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
12895 DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, dspr2),
12896 DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12897 DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12898 DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
12899 DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
12900 DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
12901 DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
12902 DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
12903 DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
12904 DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
12905 DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12906 DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12907 DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12908 DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12909 DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12910 DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dspr2),
12911 DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
12912 DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
12913 DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
12914 DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
12915 DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
12916 DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, dspr2),
12917 DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12918 DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12919 DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
12920 DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
12921 DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12922 DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12923 DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12924 DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12925 DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12926 DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12927 DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12928 DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12930 /* Built-in functions for the DSP ASE (32-bit only). */
12931 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
12932 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
12933 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
12934 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
12935 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12936 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12937 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12938 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
12939 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
12940 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12941 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12942 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12943 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12944 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
12945 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
12946 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
12947 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, dsp_32),
12948 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, dsp_32),
12949 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, dsp_32),
12950 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, dsp_32),
12951 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, dsp_32),
12952 DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
12953 DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32),
12954 DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
12955 DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32),
12956 DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, dsp_32),
12957 DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, dsp_32),
12959 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
12960 DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12961 DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12962 DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12963 DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12964 DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12965 DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12966 DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12967 DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12968 DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12970 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
12971 LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI),
12972 LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI),
12973 LOONGSON_BUILTIN (packushb, MIPS_UV8QI_FTYPE_UV4HI_UV4HI),
12974 LOONGSON_BUILTIN_SUFFIX (paddw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12975 LOONGSON_BUILTIN_SUFFIX (paddh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12976 LOONGSON_BUILTIN_SUFFIX (paddb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12977 LOONGSON_BUILTIN_SUFFIX (paddw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
12978 LOONGSON_BUILTIN_SUFFIX (paddh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12979 LOONGSON_BUILTIN_SUFFIX (paddb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
12980 LOONGSON_BUILTIN_SUFFIX (paddd, u, MIPS_UDI_FTYPE_UDI_UDI),
12981 LOONGSON_BUILTIN_SUFFIX (paddd, s, MIPS_DI_FTYPE_DI_DI),
12982 LOONGSON_BUILTIN (paddsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12983 LOONGSON_BUILTIN (paddsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
12984 LOONGSON_BUILTIN (paddush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12985 LOONGSON_BUILTIN (paddusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12986 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_ud, MIPS_UDI_FTYPE_UDI_UDI),
12987 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_uw, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12988 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_uh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12989 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_ub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12990 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_sd, MIPS_DI_FTYPE_DI_DI),
12991 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_sw, MIPS_V2SI_FTYPE_V2SI_V2SI),
12992 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_sh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12993 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_sb, MIPS_V8QI_FTYPE_V8QI_V8QI),
12994 LOONGSON_BUILTIN (pavgh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12995 LOONGSON_BUILTIN (pavgb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12996 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12997 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12998 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12999 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13000 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13001 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13002 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13003 LOONGSON_BUILTIN_SUFFIX (pcmpgth, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13004 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13005 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13006 LOONGSON_BUILTIN_SUFFIX (pcmpgth, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13007 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13008 LOONGSON_BUILTIN_SUFFIX (pextrh, u, MIPS_UV4HI_FTYPE_UV4HI_USI),
13009 LOONGSON_BUILTIN_SUFFIX (pextrh, s, MIPS_V4HI_FTYPE_V4HI_USI),
13010 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13011 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13012 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13013 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13014 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13015 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13016 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13017 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13018 LOONGSON_BUILTIN (pmaddhw, MIPS_V2SI_FTYPE_V4HI_V4HI),
13019 LOONGSON_BUILTIN (pmaxsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13020 LOONGSON_BUILTIN (pmaxub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13021 LOONGSON_BUILTIN (pminsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13022 LOONGSON_BUILTIN (pminub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13023 LOONGSON_BUILTIN_SUFFIX (pmovmskb, u, MIPS_UV8QI_FTYPE_UV8QI),
13024 LOONGSON_BUILTIN_SUFFIX (pmovmskb, s, MIPS_V8QI_FTYPE_V8QI),
13025 LOONGSON_BUILTIN (pmulhuh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13026 LOONGSON_BUILTIN (pmulhh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13027 LOONGSON_BUILTIN (pmullh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13028 LOONGSON_BUILTIN (pmuluw, MIPS_UDI_FTYPE_UV2SI_UV2SI),
13029 LOONGSON_BUILTIN (pasubub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13030 LOONGSON_BUILTIN (biadd, MIPS_UV4HI_FTYPE_UV8QI),
13031 LOONGSON_BUILTIN (psadbh, MIPS_UV4HI_FTYPE_UV8QI_UV8QI),
13032 LOONGSON_BUILTIN_SUFFIX (pshufh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI_UQI),
13033 LOONGSON_BUILTIN_SUFFIX (pshufh, s, MIPS_V4HI_FTYPE_V4HI_V4HI_UQI),
13034 LOONGSON_BUILTIN_SUFFIX (psllh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
13035 LOONGSON_BUILTIN_SUFFIX (psllh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
13036 LOONGSON_BUILTIN_SUFFIX (psllw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
13037 LOONGSON_BUILTIN_SUFFIX (psllw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
13038 LOONGSON_BUILTIN_SUFFIX (psrah, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
13039 LOONGSON_BUILTIN_SUFFIX (psrah, s, MIPS_V4HI_FTYPE_V4HI_UQI),
13040 LOONGSON_BUILTIN_SUFFIX (psraw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
13041 LOONGSON_BUILTIN_SUFFIX (psraw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
13042 LOONGSON_BUILTIN_SUFFIX (psrlh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
13043 LOONGSON_BUILTIN_SUFFIX (psrlh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
13044 LOONGSON_BUILTIN_SUFFIX (psrlw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
13045 LOONGSON_BUILTIN_SUFFIX (psrlw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
13046 LOONGSON_BUILTIN_SUFFIX (psubw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13047 LOONGSON_BUILTIN_SUFFIX (psubh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13048 LOONGSON_BUILTIN_SUFFIX (psubb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13049 LOONGSON_BUILTIN_SUFFIX (psubw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13050 LOONGSON_BUILTIN_SUFFIX (psubh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13051 LOONGSON_BUILTIN_SUFFIX (psubb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13052 LOONGSON_BUILTIN_SUFFIX (psubd, u, MIPS_UDI_FTYPE_UDI_UDI),
13053 LOONGSON_BUILTIN_SUFFIX (psubd, s, MIPS_DI_FTYPE_DI_DI),
13054 LOONGSON_BUILTIN (psubsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13055 LOONGSON_BUILTIN (psubsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
13056 LOONGSON_BUILTIN (psubush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13057 LOONGSON_BUILTIN (psubusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13058 LOONGSON_BUILTIN_SUFFIX (punpckhbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13059 LOONGSON_BUILTIN_SUFFIX (punpckhhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13060 LOONGSON_BUILTIN_SUFFIX (punpckhwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13061 LOONGSON_BUILTIN_SUFFIX (punpckhbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13062 LOONGSON_BUILTIN_SUFFIX (punpckhhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13063 LOONGSON_BUILTIN_SUFFIX (punpckhwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13064 LOONGSON_BUILTIN_SUFFIX (punpcklbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13065 LOONGSON_BUILTIN_SUFFIX (punpcklhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13066 LOONGSON_BUILTIN_SUFFIX (punpcklwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13067 LOONGSON_BUILTIN_SUFFIX (punpcklbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13068 LOONGSON_BUILTIN_SUFFIX (punpcklhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13069 LOONGSON_BUILTIN_SUFFIX (punpcklwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13071 /* Sundry other built-in functions. */
13072 DIRECT_NO_TARGET_BUILTIN (cache, MIPS_VOID_FTYPE_SI_CVPOINTER, cache)
13075 /* Index I is the function declaration for mips_builtins[I], or null if the
13076 function isn't defined on this target. */
13077 static GTY(()) tree mips_builtin_decls[ARRAY_SIZE (mips_builtins)];
13079 /* MODE is a vector mode whose elements have type TYPE. Return the type
13080 of the vector itself. */
13083 mips_builtin_vector_type (tree type, enum machine_mode mode)
13085 static tree types[2 * (int) MAX_MACHINE_MODE];
13088 mode_index = (int) mode;
13090 if (TREE_CODE (type) == INTEGER_TYPE && TYPE_UNSIGNED (type))
13091 mode_index += MAX_MACHINE_MODE;
13093 if (types[mode_index] == NULL_TREE)
13094 types[mode_index] = build_vector_type_for_mode (type, mode);
13095 return types[mode_index];
13098 /* Return a type for 'const volatile void *'. */
13101 mips_build_cvpointer_type (void)
13105 if (cache == NULL_TREE)
13106 cache = build_pointer_type (build_qualified_type
13108 TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE));
13112 /* Source-level argument types. */
13113 #define MIPS_ATYPE_VOID void_type_node
13114 #define MIPS_ATYPE_INT integer_type_node
13115 #define MIPS_ATYPE_POINTER ptr_type_node
13116 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
13118 /* Standard mode-based argument types. */
13119 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
13120 #define MIPS_ATYPE_SI intSI_type_node
13121 #define MIPS_ATYPE_USI unsigned_intSI_type_node
13122 #define MIPS_ATYPE_DI intDI_type_node
13123 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
13124 #define MIPS_ATYPE_SF float_type_node
13125 #define MIPS_ATYPE_DF double_type_node
13127 /* Vector argument types. */
13128 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
13129 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
13130 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
13131 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
13132 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
13133 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
13134 #define MIPS_ATYPE_UV2SI \
13135 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
13136 #define MIPS_ATYPE_UV4HI \
13137 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
13138 #define MIPS_ATYPE_UV8QI \
13139 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
13141 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
13142 their associated MIPS_ATYPEs. */
13143 #define MIPS_FTYPE_ATYPES1(A, B) \
13144 MIPS_ATYPE_##A, MIPS_ATYPE_##B
13146 #define MIPS_FTYPE_ATYPES2(A, B, C) \
13147 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
13149 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
13150 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
13152 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
13153 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
13156 /* Return the function type associated with function prototype TYPE. */
13159 mips_build_function_type (enum mips_function_type type)
13161 static tree types[(int) MIPS_MAX_FTYPE_MAX];
13163 if (types[(int) type] == NULL_TREE)
13166 #define DEF_MIPS_FTYPE(NUM, ARGS) \
13167 case MIPS_FTYPE_NAME##NUM ARGS: \
13168 types[(int) type] \
13169 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
13172 #include "config/mips/mips-ftypes.def"
13173 #undef DEF_MIPS_FTYPE
13175 gcc_unreachable ();
13178 return types[(int) type];
13181 /* Implement TARGET_INIT_BUILTINS. */
13184 mips_init_builtins (void)
13186 const struct mips_builtin_description *d;
13189 /* Iterate through all of the bdesc arrays, initializing all of the
13190 builtin functions. */
13191 for (i = 0; i < ARRAY_SIZE (mips_builtins); i++)
13193 d = &mips_builtins[i];
13195 mips_builtin_decls[i]
13196 = add_builtin_function (d->name,
13197 mips_build_function_type (d->function_type),
13198 i, BUILT_IN_MD, NULL, NULL);
13202 /* Implement TARGET_BUILTIN_DECL. */
13205 mips_builtin_decl (unsigned int code, bool initialize_p ATTRIBUTE_UNUSED)
13207 if (code >= ARRAY_SIZE (mips_builtins))
13208 return error_mark_node;
13209 return mips_builtin_decls[code];
13212 /* Take argument ARGNO from EXP's argument list and convert it into
13213 an expand operand. Store the operand in *OP. */
13216 mips_prepare_builtin_arg (struct expand_operand *op, tree exp,
13217 unsigned int argno)
13222 arg = CALL_EXPR_ARG (exp, argno);
13223 value = expand_normal (arg);
13224 create_input_operand (op, value, TYPE_MODE (TREE_TYPE (arg)));
13227 /* Expand instruction ICODE as part of a built-in function sequence.
13228 Use the first NOPS elements of OPS as the instruction's operands.
13229 HAS_TARGET_P is true if operand 0 is a target; it is false if the
13230 instruction has no target.
13232 Return the target rtx if HAS_TARGET_P, otherwise return const0_rtx. */
13235 mips_expand_builtin_insn (enum insn_code icode, unsigned int nops,
13236 struct expand_operand *ops, bool has_target_p)
13238 if (!maybe_expand_insn (icode, nops, ops))
13240 error ("invalid argument to built-in function");
13241 return has_target_p ? gen_reg_rtx (ops[0].mode) : const0_rtx;
13243 return has_target_p ? ops[0].value : const0_rtx;
13246 /* Expand a floating-point comparison for built-in function call EXP.
13247 The first NARGS arguments are the values to be compared. ICODE is
13248 the .md pattern that does the comparison and COND is the condition
13249 that is being tested. Return an rtx for the result. */
13252 mips_expand_builtin_compare_1 (enum insn_code icode,
13253 enum mips_fp_condition cond,
13254 tree exp, int nargs)
13256 struct expand_operand ops[MAX_RECOG_OPERANDS];
13259 /* The instruction should have a target operand, an operand for each
13260 argument, and an operand for COND. */
13261 gcc_assert (nargs + 2 == insn_data[(int) icode].n_generator_args);
13264 create_output_operand (&ops[opno++], NULL_RTX,
13265 insn_data[(int) icode].operand[0].mode);
13266 for (argno = 0; argno < nargs; argno++)
13267 mips_prepare_builtin_arg (&ops[opno++], exp, argno);
13268 create_integer_operand (&ops[opno++], (int) cond);
13269 return mips_expand_builtin_insn (icode, opno, ops, true);
13272 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
13273 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
13274 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
13275 suggests a good place to put the result. */
13278 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
13281 struct expand_operand ops[MAX_RECOG_OPERANDS];
13284 /* Map any target to operand 0. */
13287 create_output_operand (&ops[opno++], target, TYPE_MODE (TREE_TYPE (exp)));
13289 /* Map the arguments to the other operands. */
13290 gcc_assert (opno + call_expr_nargs (exp)
13291 == insn_data[icode].n_generator_args);
13292 for (argno = 0; argno < call_expr_nargs (exp); argno++)
13293 mips_prepare_builtin_arg (&ops[opno++], exp, argno);
13295 return mips_expand_builtin_insn (icode, opno, ops, has_target_p);
13298 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
13299 function; TYPE says which. EXP is the CALL_EXPR that calls the
13300 function, ICODE is the instruction that should be used to compare
13301 the first two arguments, and COND is the condition it should test.
13302 TARGET, if nonnull, suggests a good place to put the result. */
13305 mips_expand_builtin_movtf (enum mips_builtin_type type,
13306 enum insn_code icode, enum mips_fp_condition cond,
13307 rtx target, tree exp)
13309 struct expand_operand ops[4];
13312 cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp, 2);
13313 create_output_operand (&ops[0], target, TYPE_MODE (TREE_TYPE (exp)));
13314 if (type == MIPS_BUILTIN_MOVT)
13316 mips_prepare_builtin_arg (&ops[2], exp, 2);
13317 mips_prepare_builtin_arg (&ops[1], exp, 3);
13321 mips_prepare_builtin_arg (&ops[1], exp, 2);
13322 mips_prepare_builtin_arg (&ops[2], exp, 3);
13324 create_fixed_operand (&ops[3], cmp_result);
13325 return mips_expand_builtin_insn (CODE_FOR_mips_cond_move_tf_ps,
13329 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
13330 into TARGET otherwise. Return TARGET. */
13333 mips_builtin_branch_and_move (rtx condition, rtx target,
13334 rtx value_if_true, rtx value_if_false)
13336 rtx true_label, done_label;
13338 true_label = gen_label_rtx ();
13339 done_label = gen_label_rtx ();
13341 /* First assume that CONDITION is false. */
13342 mips_emit_move (target, value_if_false);
13344 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
13345 emit_jump_insn (gen_condjump (condition, true_label));
13346 emit_jump_insn (gen_jump (done_label));
13349 /* Fix TARGET if CONDITION is true. */
13350 emit_label (true_label);
13351 mips_emit_move (target, value_if_true);
13353 emit_label (done_label);
13357 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
13358 the CALL_EXPR that calls the function, ICODE is the code of the
13359 comparison instruction, and COND is the condition it should test.
13360 TARGET, if nonnull, suggests a good place to put the boolean result. */
13363 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
13364 enum insn_code icode, enum mips_fp_condition cond,
13365 rtx target, tree exp)
13367 rtx offset, condition, cmp_result;
13369 if (target == 0 || GET_MODE (target) != SImode)
13370 target = gen_reg_rtx (SImode);
13371 cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp,
13372 call_expr_nargs (exp));
13374 /* If the comparison sets more than one register, we define the result
13375 to be 0 if all registers are false and -1 if all registers are true.
13376 The value of the complete result is indeterminate otherwise. */
13377 switch (builtin_type)
13379 case MIPS_BUILTIN_CMP_ALL:
13380 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
13381 return mips_builtin_branch_and_move (condition, target,
13382 const0_rtx, const1_rtx);
13384 case MIPS_BUILTIN_CMP_UPPER:
13385 case MIPS_BUILTIN_CMP_LOWER:
13386 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
13387 condition = gen_single_cc (cmp_result, offset);
13388 return mips_builtin_branch_and_move (condition, target,
13389 const1_rtx, const0_rtx);
13392 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
13393 return mips_builtin_branch_and_move (condition, target,
13394 const1_rtx, const0_rtx);
13398 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
13399 if nonnull, suggests a good place to put the boolean result. */
13402 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
13404 rtx condition, cmp_result;
13407 if (target == 0 || GET_MODE (target) != SImode)
13408 target = gen_reg_rtx (SImode);
13410 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
13412 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
13417 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
13418 return mips_builtin_branch_and_move (condition, target,
13419 const1_rtx, const0_rtx);
13422 /* Implement TARGET_EXPAND_BUILTIN. */
13425 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
13426 enum machine_mode mode, int ignore)
13429 unsigned int fcode, avail;
13430 const struct mips_builtin_description *d;
13432 fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
13433 fcode = DECL_FUNCTION_CODE (fndecl);
13434 gcc_assert (fcode < ARRAY_SIZE (mips_builtins));
13435 d = &mips_builtins[fcode];
13436 avail = d->avail ();
13437 gcc_assert (avail != 0);
13440 error ("built-in function %qE not supported for MIPS16",
13441 DECL_NAME (fndecl));
13442 return ignore ? const0_rtx : CONST0_RTX (mode);
13444 switch (d->builtin_type)
13446 case MIPS_BUILTIN_DIRECT:
13447 return mips_expand_builtin_direct (d->icode, target, exp, true);
13449 case MIPS_BUILTIN_DIRECT_NO_TARGET:
13450 return mips_expand_builtin_direct (d->icode, target, exp, false);
13452 case MIPS_BUILTIN_MOVT:
13453 case MIPS_BUILTIN_MOVF:
13454 return mips_expand_builtin_movtf (d->builtin_type, d->icode,
13455 d->cond, target, exp);
13457 case MIPS_BUILTIN_CMP_ANY:
13458 case MIPS_BUILTIN_CMP_ALL:
13459 case MIPS_BUILTIN_CMP_UPPER:
13460 case MIPS_BUILTIN_CMP_LOWER:
13461 case MIPS_BUILTIN_CMP_SINGLE:
13462 return mips_expand_builtin_compare (d->builtin_type, d->icode,
13463 d->cond, target, exp);
13465 case MIPS_BUILTIN_BPOSGE32:
13466 return mips_expand_builtin_bposge (d->builtin_type, target);
13468 gcc_unreachable ();
13471 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
13472 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
13473 struct mips16_constant {
13474 struct mips16_constant *next;
13477 enum machine_mode mode;
13480 /* Information about an incomplete MIPS16 constant pool. FIRST is the
13481 first constant, HIGHEST_ADDRESS is the highest address that the first
13482 byte of the pool can have, and INSN_ADDRESS is the current instruction
13484 struct mips16_constant_pool {
13485 struct mips16_constant *first;
13486 int highest_address;
13490 /* Add constant VALUE to POOL and return its label. MODE is the
13491 value's mode (used for CONST_INTs, etc.). */
13494 mips16_add_constant (struct mips16_constant_pool *pool,
13495 rtx value, enum machine_mode mode)
13497 struct mips16_constant **p, *c;
13498 bool first_of_size_p;
13500 /* See whether the constant is already in the pool. If so, return the
13501 existing label, otherwise leave P pointing to the place where the
13502 constant should be added.
13504 Keep the pool sorted in increasing order of mode size so that we can
13505 reduce the number of alignments needed. */
13506 first_of_size_p = true;
13507 for (p = &pool->first; *p != 0; p = &(*p)->next)
13509 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
13510 return (*p)->label;
13511 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
13513 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
13514 first_of_size_p = false;
13517 /* In the worst case, the constant needed by the earliest instruction
13518 will end up at the end of the pool. The entire pool must then be
13519 accessible from that instruction.
13521 When adding the first constant, set the pool's highest address to
13522 the address of the first out-of-range byte. Adjust this address
13523 downwards each time a new constant is added. */
13524 if (pool->first == 0)
13525 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
13526 of the instruction with the lowest two bits clear. The base PC
13527 value for LDPC has the lowest three bits clear. Assume the worst
13528 case here; namely that the PC-relative instruction occupies the
13529 last 2 bytes in an aligned word. */
13530 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
13531 pool->highest_address -= GET_MODE_SIZE (mode);
13532 if (first_of_size_p)
13533 /* Take into account the worst possible padding due to alignment. */
13534 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
13536 /* Create a new entry. */
13537 c = XNEW (struct mips16_constant);
13540 c->label = gen_label_rtx ();
13547 /* Output constant VALUE after instruction INSN and return the last
13548 instruction emitted. MODE is the mode of the constant. */
13551 mips16_emit_constants_1 (enum machine_mode mode, rtx value, rtx insn)
13553 if (SCALAR_INT_MODE_P (mode) || ALL_SCALAR_FIXED_POINT_MODE_P (mode))
13555 rtx size = GEN_INT (GET_MODE_SIZE (mode));
13556 return emit_insn_after (gen_consttable_int (value, size), insn);
13559 if (SCALAR_FLOAT_MODE_P (mode))
13560 return emit_insn_after (gen_consttable_float (value), insn);
13562 if (VECTOR_MODE_P (mode))
13566 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
13567 insn = mips16_emit_constants_1 (GET_MODE_INNER (mode),
13568 CONST_VECTOR_ELT (value, i), insn);
13572 gcc_unreachable ();
13575 /* Dump out the constants in CONSTANTS after INSN. */
13578 mips16_emit_constants (struct mips16_constant *constants, rtx insn)
13580 struct mips16_constant *c, *next;
13584 for (c = constants; c != NULL; c = next)
13586 /* If necessary, increase the alignment of PC. */
13587 if (align < GET_MODE_SIZE (c->mode))
13589 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
13590 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
13592 align = GET_MODE_SIZE (c->mode);
13594 insn = emit_label_after (c->label, insn);
13595 insn = mips16_emit_constants_1 (c->mode, c->value, insn);
13601 emit_barrier_after (insn);
13604 /* Return the length of instruction INSN. */
13607 mips16_insn_length (rtx insn)
13611 rtx body = PATTERN (insn);
13612 if (GET_CODE (body) == ADDR_VEC)
13613 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
13614 if (GET_CODE (body) == ADDR_DIFF_VEC)
13615 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
13617 return get_attr_length (insn);
13620 /* If *X is a symbolic constant that refers to the constant pool, add
13621 the constant to POOL and rewrite *X to use the constant's label. */
13624 mips16_rewrite_pool_constant (struct mips16_constant_pool *pool, rtx *x)
13626 rtx base, offset, label;
13628 split_const (*x, &base, &offset);
13629 if (GET_CODE (base) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (base))
13631 label = mips16_add_constant (pool, get_pool_constant (base),
13632 get_pool_mode (base));
13633 base = gen_rtx_LABEL_REF (Pmode, label);
13634 *x = mips_unspec_address_offset (base, offset, SYMBOL_PC_RELATIVE);
13638 /* This structure is used to communicate with mips16_rewrite_pool_refs.
13639 INSN is the instruction we're rewriting and POOL points to the current
13641 struct mips16_rewrite_pool_refs_info {
13643 struct mips16_constant_pool *pool;
13646 /* Rewrite *X so that constant pool references refer to the constant's
13647 label instead. DATA points to a mips16_rewrite_pool_refs_info
13651 mips16_rewrite_pool_refs (rtx *x, void *data)
13653 struct mips16_rewrite_pool_refs_info *info =
13654 (struct mips16_rewrite_pool_refs_info *) data;
13656 if (force_to_mem_operand (*x, Pmode))
13658 rtx mem = force_const_mem (GET_MODE (*x), *x);
13659 validate_change (info->insn, x, mem, false);
13664 mips16_rewrite_pool_constant (info->pool, &XEXP (*x, 0));
13668 if (TARGET_MIPS16_TEXT_LOADS)
13669 mips16_rewrite_pool_constant (info->pool, x);
13671 return GET_CODE (*x) == CONST ? -1 : 0;
13674 /* Return whether CFG is used in mips_reorg. */
13677 mips_cfg_in_reorg (void)
13679 return (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
13680 || TARGET_RELAX_PIC_CALLS);
13683 /* Build MIPS16 constant pools. */
13686 mips16_lay_out_constants (void)
13688 struct mips16_constant_pool pool;
13689 struct mips16_rewrite_pool_refs_info info;
13692 if (!TARGET_MIPS16_PCREL_LOADS)
13695 if (mips_cfg_in_reorg ())
13696 split_all_insns ();
13698 split_all_insns_noflow ();
13700 memset (&pool, 0, sizeof (pool));
13701 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
13703 /* Rewrite constant pool references in INSN. */
13704 if (USEFUL_INSN_P (insn))
13708 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &info);
13711 pool.insn_address += mips16_insn_length (insn);
13713 if (pool.first != NULL)
13715 /* If there are no natural barriers between the first user of
13716 the pool and the highest acceptable address, we'll need to
13717 create a new instruction to jump around the constant pool.
13718 In the worst case, this instruction will be 4 bytes long.
13720 If it's too late to do this transformation after INSN,
13721 do it immediately before INSN. */
13722 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
13726 label = gen_label_rtx ();
13728 jump = emit_jump_insn_before (gen_jump (label), insn);
13729 JUMP_LABEL (jump) = label;
13730 LABEL_NUSES (label) = 1;
13731 barrier = emit_barrier_after (jump);
13733 emit_label_after (label, barrier);
13734 pool.insn_address += 4;
13737 /* See whether the constant pool is now out of range of the first
13738 user. If so, output the constants after the previous barrier.
13739 Note that any instructions between BARRIER and INSN (inclusive)
13740 will use negative offsets to refer to the pool. */
13741 if (pool.insn_address > pool.highest_address)
13743 mips16_emit_constants (pool.first, barrier);
13747 else if (BARRIER_P (insn))
13751 mips16_emit_constants (pool.first, get_last_insn ());
13754 /* Return true if it is worth r10k_simplify_address's while replacing
13755 an address with X. We are looking for constants, and for addresses
13756 at a known offset from the incoming stack pointer. */
13759 r10k_simplified_address_p (rtx x)
13761 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
13763 return x == virtual_incoming_args_rtx || CONSTANT_P (x);
13766 /* X is an expression that appears in INSN. Try to use the UD chains
13767 to simplify it, returning the simplified form on success and the
13768 original form otherwise. Replace the incoming value of $sp with
13769 virtual_incoming_args_rtx (which should never occur in X otherwise). */
13772 r10k_simplify_address (rtx x, rtx insn)
13774 rtx newx, op0, op1, set, def_insn, note;
13776 struct df_link *defs;
13781 op0 = r10k_simplify_address (XEXP (x, 0), insn);
13782 if (op0 != XEXP (x, 0))
13783 newx = simplify_gen_unary (GET_CODE (x), GET_MODE (x),
13784 op0, GET_MODE (XEXP (x, 0)));
13786 else if (BINARY_P (x))
13788 op0 = r10k_simplify_address (XEXP (x, 0), insn);
13789 op1 = r10k_simplify_address (XEXP (x, 1), insn);
13790 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
13791 newx = simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
13793 else if (GET_CODE (x) == LO_SUM)
13795 /* LO_SUMs can be offset from HIGHs, if we know they won't
13796 overflow. See mips_classify_address for the rationale behind
13798 op0 = r10k_simplify_address (XEXP (x, 0), insn);
13799 if (GET_CODE (op0) == HIGH)
13800 newx = XEXP (x, 1);
13802 else if (REG_P (x))
13804 /* Uses are recorded by regno_reg_rtx, not X itself. */
13805 use = df_find_use (insn, regno_reg_rtx[REGNO (x)]);
13807 defs = DF_REF_CHAIN (use);
13809 /* Require a single definition. */
13810 if (defs && defs->next == NULL)
13813 if (DF_REF_IS_ARTIFICIAL (def))
13815 /* Replace the incoming value of $sp with
13816 virtual_incoming_args_rtx. */
13817 if (x == stack_pointer_rtx
13818 && DF_REF_BB (def) == ENTRY_BLOCK_PTR)
13819 newx = virtual_incoming_args_rtx;
13821 else if (dominated_by_p (CDI_DOMINATORS, DF_REF_BB (use),
13824 /* Make sure that DEF_INSN is a single set of REG. */
13825 def_insn = DF_REF_INSN (def);
13826 if (NONJUMP_INSN_P (def_insn))
13828 set = single_set (def_insn);
13829 if (set && rtx_equal_p (SET_DEST (set), x))
13831 /* Prefer to use notes, since the def-use chains
13832 are often shorter. */
13833 note = find_reg_equal_equiv_note (def_insn);
13835 newx = XEXP (note, 0);
13837 newx = SET_SRC (set);
13838 newx = r10k_simplify_address (newx, def_insn);
13844 if (newx && r10k_simplified_address_p (newx))
13849 /* Return true if ADDRESS is known to be an uncached address
13850 on R10K systems. */
13853 r10k_uncached_address_p (unsigned HOST_WIDE_INT address)
13855 unsigned HOST_WIDE_INT upper;
13857 /* Check for KSEG1. */
13858 if (address + 0x60000000 < 0x20000000)
13861 /* Check for uncached XKPHYS addresses. */
13862 if (Pmode == DImode)
13864 upper = (address >> 40) & 0xf9ffff;
13865 if (upper == 0x900000 || upper == 0xb80000)
13871 /* Return true if we can prove that an access to address X in instruction
13872 INSN would be safe from R10K speculation. This X is a general
13873 expression; it might not be a legitimate address. */
13876 r10k_safe_address_p (rtx x, rtx insn)
13879 HOST_WIDE_INT offset_val;
13881 x = r10k_simplify_address (x, insn);
13883 /* Check for references to the stack frame. It doesn't really matter
13884 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
13885 allows us to assume that accesses to any part of the eventual frame
13886 is safe from speculation at any point in the function. */
13887 mips_split_plus (x, &base, &offset_val);
13888 if (base == virtual_incoming_args_rtx
13889 && offset_val >= -cfun->machine->frame.total_size
13890 && offset_val < cfun->machine->frame.args_size)
13893 /* Check for uncached addresses. */
13894 if (CONST_INT_P (x))
13895 return r10k_uncached_address_p (INTVAL (x));
13897 /* Check for accesses to a static object. */
13898 split_const (x, &base, &offset);
13899 return offset_within_block_p (base, INTVAL (offset));
13902 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
13903 an in-range access to an automatic variable, or to an object with
13904 a link-time-constant address. */
13907 r10k_safe_mem_expr_p (tree expr, rtx offset)
13909 if (expr == NULL_TREE
13910 || offset == NULL_RTX
13911 || !CONST_INT_P (offset)
13912 || INTVAL (offset) < 0
13913 || INTVAL (offset) >= int_size_in_bytes (TREE_TYPE (expr)))
13916 while (TREE_CODE (expr) == COMPONENT_REF)
13918 expr = TREE_OPERAND (expr, 0);
13919 if (expr == NULL_TREE)
13923 return DECL_P (expr);
13926 /* A for_each_rtx callback for which DATA points to the instruction
13927 containing *X. Stop the search if we find a MEM that is not safe
13928 from R10K speculation. */
13931 r10k_needs_protection_p_1 (rtx *loc, void *data)
13939 if (r10k_safe_mem_expr_p (MEM_EXPR (mem), MEM_OFFSET (mem)))
13942 if (r10k_safe_address_p (XEXP (mem, 0), (rtx) data))
13948 /* A note_stores callback for which DATA points to an instruction pointer.
13949 If *DATA is nonnull, make it null if it X contains a MEM that is not
13950 safe from R10K speculation. */
13953 r10k_needs_protection_p_store (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
13958 insn_ptr = (rtx *) data;
13959 if (*insn_ptr && for_each_rtx (&x, r10k_needs_protection_p_1, *insn_ptr))
13960 *insn_ptr = NULL_RTX;
13963 /* A for_each_rtx callback that iterates over the pattern of a CALL_INSN.
13964 Return nonzero if the call is not to a declared function. */
13967 r10k_needs_protection_p_call (rtx *loc, void *data ATTRIBUTE_UNUSED)
13976 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DECL (x))
13982 /* Return true if instruction INSN needs to be protected by an R10K
13986 r10k_needs_protection_p (rtx insn)
13989 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_call, NULL);
13991 if (mips_r10k_cache_barrier == R10K_CACHE_BARRIER_STORE)
13993 note_stores (PATTERN (insn), r10k_needs_protection_p_store, &insn);
13994 return insn == NULL_RTX;
13997 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_1, insn);
14000 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
14001 edge is unconditional. */
14004 r10k_protected_bb_p (basic_block bb, sbitmap protected_bbs)
14009 FOR_EACH_EDGE (e, ei, bb->preds)
14010 if (!single_succ_p (e->src)
14011 || !TEST_BIT (protected_bbs, e->src->index)
14012 || (e->flags & EDGE_COMPLEX) != 0)
14017 /* Implement -mr10k-cache-barrier= for the current function. */
14020 r10k_insert_cache_barriers (void)
14022 int *rev_post_order;
14025 sbitmap protected_bbs;
14026 rtx insn, end, unprotected_region;
14030 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
14034 /* Calculate dominators. */
14035 calculate_dominance_info (CDI_DOMINATORS);
14037 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
14038 X is protected by a cache barrier. */
14039 protected_bbs = sbitmap_alloc (last_basic_block);
14040 sbitmap_zero (protected_bbs);
14042 /* Iterate over the basic blocks in reverse post-order. */
14043 rev_post_order = XNEWVEC (int, last_basic_block);
14044 n = pre_and_rev_post_order_compute (NULL, rev_post_order, false);
14045 for (i = 0; i < n; i++)
14047 bb = BASIC_BLOCK (rev_post_order[i]);
14049 /* If this block is only reached by unconditional edges, and if the
14050 source of every edge is protected, the beginning of the block is
14052 if (r10k_protected_bb_p (bb, protected_bbs))
14053 unprotected_region = NULL_RTX;
14055 unprotected_region = pc_rtx;
14056 end = NEXT_INSN (BB_END (bb));
14058 /* UNPROTECTED_REGION is:
14060 - null if we are processing a protected region,
14061 - pc_rtx if we are processing an unprotected region but have
14062 not yet found the first instruction in it
14063 - the first instruction in an unprotected region otherwise. */
14064 for (insn = BB_HEAD (bb); insn != end; insn = NEXT_INSN (insn))
14066 if (unprotected_region && USEFUL_INSN_P (insn))
14068 if (recog_memoized (insn) == CODE_FOR_mips_cache)
14069 /* This CACHE instruction protects the following code. */
14070 unprotected_region = NULL_RTX;
14073 /* See if INSN is the first instruction in this
14074 unprotected region. */
14075 if (unprotected_region == pc_rtx)
14076 unprotected_region = insn;
14078 /* See if INSN needs to be protected. If so,
14079 we must insert a cache barrier somewhere between
14080 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
14081 clear which position is better performance-wise,
14082 but as a tie-breaker, we assume that it is better
14083 to allow delay slots to be back-filled where
14084 possible, and that it is better not to insert
14085 barriers in the middle of already-scheduled code.
14086 We therefore insert the barrier at the beginning
14088 if (r10k_needs_protection_p (insn))
14090 emit_insn_before (gen_r10k_cache_barrier (),
14091 unprotected_region);
14092 unprotected_region = NULL_RTX;
14098 /* The called function is not required to protect the exit path.
14099 The code that follows a call is therefore unprotected. */
14100 unprotected_region = pc_rtx;
14103 /* Record whether the end of this block is protected. */
14104 if (unprotected_region == NULL_RTX)
14105 SET_BIT (protected_bbs, bb->index);
14107 XDELETEVEC (rev_post_order);
14109 sbitmap_free (protected_bbs);
14111 free_dominance_info (CDI_DOMINATORS);
14114 /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX
14115 otherwise. If INSN has two call rtx, then store the second one in
14119 mips_call_expr_from_insn (rtx insn, rtx *second_call)
14124 if (!CALL_P (insn))
14127 x = PATTERN (insn);
14128 if (GET_CODE (x) == PARALLEL)
14130 /* Calls returning complex values have two CALL rtx. Look for the second
14131 one here, and return it via the SECOND_CALL arg. */
14132 x2 = XVECEXP (x, 0, 1);
14133 if (GET_CODE (x2) == SET)
14135 if (GET_CODE (x2) == CALL)
14138 x = XVECEXP (x, 0, 0);
14140 if (GET_CODE (x) == SET)
14142 gcc_assert (GET_CODE (x) == CALL);
14147 /* REG is set in DEF. See if the definition is one of the ways we load a
14148 register with a symbol address for a mips_use_pic_fn_addr_reg_p call. If
14149 it is return the symbol reference of the function, otherwise return
14153 mips_pic_call_symbol_from_set (df_ref def, rtx reg)
14157 if (DF_REF_IS_ARTIFICIAL (def))
14160 def_insn = DF_REF_INSN (def);
14161 set = single_set (def_insn);
14162 if (set && rtx_equal_p (SET_DEST (set), reg))
14164 rtx note, src, symbol;
14166 /* First, look at REG_EQUAL/EQUIV notes. */
14167 note = find_reg_equal_equiv_note (def_insn);
14168 if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF)
14169 return XEXP (note, 0);
14171 /* For %call16 references we don't have REG_EQUAL. */
14172 src = SET_SRC (set);
14173 symbol = mips_strip_unspec_call (src);
14176 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
14180 /* Follow simple register copies. */
14182 return mips_find_pic_call_symbol (def_insn, src);
14188 /* Find the definition of the use of REG in INSN. See if the definition is
14189 one of the ways we load a register with a symbol address for a
14190 mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference of
14191 the function, otherwise return NULL_RTX. */
14194 mips_find_pic_call_symbol (rtx insn, rtx reg)
14197 struct df_link *defs;
14200 use = df_find_use (insn, regno_reg_rtx[REGNO (reg)]);
14203 defs = DF_REF_CHAIN (use);
14206 symbol = mips_pic_call_symbol_from_set (defs->ref, reg);
14210 /* If we have more than one definition, they need to be identical. */
14211 for (defs = defs->next; defs; defs = defs->next)
14215 other = mips_pic_call_symbol_from_set (defs->ref, reg);
14216 if (!rtx_equal_p (symbol, other))
14223 /* Replace the args_size operand of the call expression CALL with the
14224 call-attribute UNSPEC and fill in SYMBOL as the function symbol. */
14227 mips_annotate_pic_call_expr (rtx call, rtx symbol)
14231 args_size = XEXP (call, 1);
14232 XEXP (call, 1) = gen_rtx_UNSPEC (GET_MODE (args_size),
14233 gen_rtvec (2, args_size, symbol),
14237 /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See
14238 if instead of the arg_size argument it contains the call attributes. If
14239 yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function
14240 symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is
14244 mips_get_pic_call_symbol (rtx *operands, int args_size_opno)
14246 rtx args_size, symbol;
14248 if (!TARGET_RELAX_PIC_CALLS || args_size_opno == -1)
14251 args_size = operands[args_size_opno];
14252 if (GET_CODE (args_size) != UNSPEC)
14254 gcc_assert (XINT (args_size, 1) == UNSPEC_CALL_ATTR);
14256 symbol = XVECEXP (args_size, 0, 1);
14257 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
14259 operands[args_size_opno] = symbol;
14263 /* Use DF to annotate PIC indirect calls with the function symbol they
14267 mips_annotate_pic_calls (void)
14273 FOR_BB_INSNS (bb, insn)
14275 rtx call, reg, symbol, second_call;
14278 call = mips_call_expr_from_insn (insn, &second_call);
14281 gcc_assert (MEM_P (XEXP (call, 0)));
14282 reg = XEXP (XEXP (call, 0), 0);
14286 symbol = mips_find_pic_call_symbol (insn, reg);
14289 mips_annotate_pic_call_expr (call, symbol);
14291 mips_annotate_pic_call_expr (second_call, symbol);
14296 /* A temporary variable used by for_each_rtx callbacks, etc. */
14297 static rtx mips_sim_insn;
14299 /* A structure representing the state of the processor pipeline.
14300 Used by the mips_sim_* family of functions. */
14302 /* The maximum number of instructions that can be issued in a cycle.
14303 (Caches mips_issue_rate.) */
14304 unsigned int issue_rate;
14306 /* The current simulation time. */
14309 /* How many more instructions can be issued in the current cycle. */
14310 unsigned int insns_left;
14312 /* LAST_SET[X].INSN is the last instruction to set register X.
14313 LAST_SET[X].TIME is the time at which that instruction was issued.
14314 INSN is null if no instruction has yet set register X. */
14318 } last_set[FIRST_PSEUDO_REGISTER];
14320 /* The pipeline's current DFA state. */
14324 /* Reset STATE to the initial simulation state. */
14327 mips_sim_reset (struct mips_sim *state)
14330 state->insns_left = state->issue_rate;
14331 memset (&state->last_set, 0, sizeof (state->last_set));
14332 state_reset (state->dfa_state);
14335 /* Initialize STATE before its first use. DFA_STATE points to an
14336 allocated but uninitialized DFA state. */
14339 mips_sim_init (struct mips_sim *state, state_t dfa_state)
14341 state->issue_rate = mips_issue_rate ();
14342 state->dfa_state = dfa_state;
14343 mips_sim_reset (state);
14346 /* Advance STATE by one clock cycle. */
14349 mips_sim_next_cycle (struct mips_sim *state)
14352 state->insns_left = state->issue_rate;
14353 state_transition (state->dfa_state, 0);
14356 /* Advance simulation state STATE until instruction INSN can read
14360 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
14362 unsigned int regno, end_regno;
14364 end_regno = END_REGNO (reg);
14365 for (regno = REGNO (reg); regno < end_regno; regno++)
14366 if (state->last_set[regno].insn != 0)
14370 t = (state->last_set[regno].time
14371 + insn_latency (state->last_set[regno].insn, insn));
14372 while (state->time < t)
14373 mips_sim_next_cycle (state);
14377 /* A for_each_rtx callback. If *X is a register, advance simulation state
14378 DATA until mips_sim_insn can read the register's value. */
14381 mips_sim_wait_regs_2 (rtx *x, void *data)
14384 mips_sim_wait_reg ((struct mips_sim *) data, mips_sim_insn, *x);
14388 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
14391 mips_sim_wait_regs_1 (rtx *x, void *data)
14393 for_each_rtx (x, mips_sim_wait_regs_2, data);
14396 /* Advance simulation state STATE until all of INSN's register
14397 dependencies are satisfied. */
14400 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
14402 mips_sim_insn = insn;
14403 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
14406 /* Advance simulation state STATE until the units required by
14407 instruction INSN are available. */
14410 mips_sim_wait_units (struct mips_sim *state, rtx insn)
14414 tmp_state = alloca (state_size ());
14415 while (state->insns_left == 0
14416 || (memcpy (tmp_state, state->dfa_state, state_size ()),
14417 state_transition (tmp_state, insn) >= 0))
14418 mips_sim_next_cycle (state);
14421 /* Advance simulation state STATE until INSN is ready to issue. */
14424 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
14426 mips_sim_wait_regs (state, insn);
14427 mips_sim_wait_units (state, insn);
14430 /* mips_sim_insn has just set X. Update the LAST_SET array
14431 in simulation state DATA. */
14434 mips_sim_record_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
14436 struct mips_sim *state;
14438 state = (struct mips_sim *) data;
14441 unsigned int regno, end_regno;
14443 end_regno = END_REGNO (x);
14444 for (regno = REGNO (x); regno < end_regno; regno++)
14446 state->last_set[regno].insn = mips_sim_insn;
14447 state->last_set[regno].time = state->time;
14452 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
14453 can issue immediately (i.e., that mips_sim_wait_insn has already
14457 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
14459 state_transition (state->dfa_state, insn);
14460 state->insns_left--;
14462 mips_sim_insn = insn;
14463 note_stores (PATTERN (insn), mips_sim_record_set, state);
14466 /* Simulate issuing a NOP in state STATE. */
14469 mips_sim_issue_nop (struct mips_sim *state)
14471 if (state->insns_left == 0)
14472 mips_sim_next_cycle (state);
14473 state->insns_left--;
14476 /* Update simulation state STATE so that it's ready to accept the instruction
14477 after INSN. INSN should be part of the main rtl chain, not a member of a
14481 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
14483 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
14485 mips_sim_issue_nop (state);
14487 switch (GET_CODE (SEQ_BEGIN (insn)))
14491 /* We can't predict the processor state after a call or label. */
14492 mips_sim_reset (state);
14496 /* The delay slots of branch likely instructions are only executed
14497 when the branch is taken. Therefore, if the caller has simulated
14498 the delay slot instruction, STATE does not really reflect the state
14499 of the pipeline for the instruction after the delay slot. Also,
14500 branch likely instructions tend to incur a penalty when not taken,
14501 so there will probably be an extra delay between the branch and
14502 the instruction after the delay slot. */
14503 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
14504 mips_sim_reset (state);
14512 /* The VR4130 pipeline issues aligned pairs of instructions together,
14513 but it stalls the second instruction if it depends on the first.
14514 In order to cut down the amount of logic required, this dependence
14515 check is not based on a full instruction decode. Instead, any non-SPECIAL
14516 instruction is assumed to modify the register specified by bits 20-16
14517 (which is usually the "rt" field).
14519 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
14520 input, so we can end up with a false dependence between the branch
14521 and its delay slot. If this situation occurs in instruction INSN,
14522 try to avoid it by swapping rs and rt. */
14525 vr4130_avoid_branch_rt_conflict (rtx insn)
14529 first = SEQ_BEGIN (insn);
14530 second = SEQ_END (insn);
14532 && NONJUMP_INSN_P (second)
14533 && GET_CODE (PATTERN (first)) == SET
14534 && GET_CODE (SET_DEST (PATTERN (first))) == PC
14535 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
14537 /* Check for the right kind of condition. */
14538 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
14539 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
14540 && REG_P (XEXP (cond, 0))
14541 && REG_P (XEXP (cond, 1))
14542 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
14543 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
14545 /* SECOND mentions the rt register but not the rs register. */
14546 rtx tmp = XEXP (cond, 0);
14547 XEXP (cond, 0) = XEXP (cond, 1);
14548 XEXP (cond, 1) = tmp;
14553 /* Implement -mvr4130-align. Go through each basic block and simulate the
14554 processor pipeline. If we find that a pair of instructions could execute
14555 in parallel, and the first of those instructions is not 8-byte aligned,
14556 insert a nop to make it aligned. */
14559 vr4130_align_insns (void)
14561 struct mips_sim state;
14562 rtx insn, subinsn, last, last2, next;
14567 /* LAST is the last instruction before INSN to have a nonzero length.
14568 LAST2 is the last such instruction before LAST. */
14572 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
14575 mips_sim_init (&state, alloca (state_size ()));
14576 for (insn = get_insns (); insn != 0; insn = next)
14578 unsigned int length;
14580 next = NEXT_INSN (insn);
14582 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
14583 This isn't really related to the alignment pass, but we do it on
14584 the fly to avoid a separate instruction walk. */
14585 vr4130_avoid_branch_rt_conflict (insn);
14587 if (USEFUL_INSN_P (insn))
14588 FOR_EACH_SUBINSN (subinsn, insn)
14590 mips_sim_wait_insn (&state, subinsn);
14592 /* If we want this instruction to issue in parallel with the
14593 previous one, make sure that the previous instruction is
14594 aligned. There are several reasons why this isn't worthwhile
14595 when the second instruction is a call:
14597 - Calls are less likely to be performance critical,
14598 - There's a good chance that the delay slot can execute
14599 in parallel with the call.
14600 - The return address would then be unaligned.
14602 In general, if we're going to insert a nop between instructions
14603 X and Y, it's better to insert it immediately after X. That
14604 way, if the nop makes Y aligned, it will also align any labels
14605 between X and Y. */
14606 if (state.insns_left != state.issue_rate
14607 && !CALL_P (subinsn))
14609 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
14611 /* SUBINSN is the first instruction in INSN and INSN is
14612 aligned. We want to align the previous instruction
14613 instead, so insert a nop between LAST2 and LAST.
14615 Note that LAST could be either a single instruction
14616 or a branch with a delay slot. In the latter case,
14617 LAST, like INSN, is already aligned, but the delay
14618 slot must have some extra delay that stops it from
14619 issuing at the same time as the branch. We therefore
14620 insert a nop before the branch in order to align its
14622 emit_insn_after (gen_nop (), last2);
14625 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
14627 /* SUBINSN is the delay slot of INSN, but INSN is
14628 currently unaligned. Insert a nop between
14629 LAST and INSN to align it. */
14630 emit_insn_after (gen_nop (), last);
14634 mips_sim_issue_insn (&state, subinsn);
14636 mips_sim_finish_insn (&state, insn);
14638 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
14639 length = get_attr_length (insn);
14642 /* If the instruction is an asm statement or multi-instruction
14643 mips.md patern, the length is only an estimate. Insert an
14644 8 byte alignment after it so that the following instructions
14645 can be handled correctly. */
14646 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
14647 && (recog_memoized (insn) < 0 || length >= 8))
14649 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
14650 next = NEXT_INSN (next);
14651 mips_sim_next_cycle (&state);
14654 else if (length & 4)
14655 aligned_p = !aligned_p;
14660 /* See whether INSN is an aligned label. */
14661 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
14667 /* This structure records that the current function has a LO_SUM
14668 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
14669 the largest offset applied to BASE by all such LO_SUMs. */
14670 struct mips_lo_sum_offset {
14672 HOST_WIDE_INT offset;
14675 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
14678 mips_hash_base (rtx base)
14680 int do_not_record_p;
14682 return hash_rtx (base, GET_MODE (base), &do_not_record_p, NULL, false);
14685 /* Hash-table callbacks for mips_lo_sum_offsets. */
14688 mips_lo_sum_offset_hash (const void *entry)
14690 return mips_hash_base (((const struct mips_lo_sum_offset *) entry)->base);
14694 mips_lo_sum_offset_eq (const void *entry, const void *value)
14696 return rtx_equal_p (((const struct mips_lo_sum_offset *) entry)->base,
14697 (const_rtx) value);
14700 /* Look up symbolic constant X in HTAB, which is a hash table of
14701 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
14702 paired with a recorded LO_SUM, otherwise record X in the table. */
14705 mips_lo_sum_offset_lookup (htab_t htab, rtx x, enum insert_option option)
14709 struct mips_lo_sum_offset *entry;
14711 /* Split X into a base and offset. */
14712 split_const (x, &base, &offset);
14713 if (UNSPEC_ADDRESS_P (base))
14714 base = UNSPEC_ADDRESS (base);
14716 /* Look up the base in the hash table. */
14717 slot = htab_find_slot_with_hash (htab, base, mips_hash_base (base), option);
14721 entry = (struct mips_lo_sum_offset *) *slot;
14722 if (option == INSERT)
14726 entry = XNEW (struct mips_lo_sum_offset);
14727 entry->base = base;
14728 entry->offset = INTVAL (offset);
14733 if (INTVAL (offset) > entry->offset)
14734 entry->offset = INTVAL (offset);
14737 return INTVAL (offset) <= entry->offset;
14740 /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table.
14741 Record every LO_SUM in *LOC. */
14744 mips_record_lo_sum (rtx *loc, void *data)
14746 if (GET_CODE (*loc) == LO_SUM)
14747 mips_lo_sum_offset_lookup ((htab_t) data, XEXP (*loc, 1), INSERT);
14751 /* Return true if INSN is a SET of an orphaned high-part relocation.
14752 HTAB is a hash table of mips_lo_sum_offsets that describes all the
14753 LO_SUMs in the current function. */
14756 mips_orphaned_high_part_p (htab_t htab, rtx insn)
14758 enum mips_symbol_type type;
14761 set = single_set (insn);
14764 /* Check for %his. */
14766 if (GET_CODE (x) == HIGH
14767 && absolute_symbolic_operand (XEXP (x, 0), VOIDmode))
14768 return !mips_lo_sum_offset_lookup (htab, XEXP (x, 0), NO_INSERT);
14770 /* Check for local %gots (and %got_pages, which is redundant but OK). */
14771 if (GET_CODE (x) == UNSPEC
14772 && XINT (x, 1) == UNSPEC_LOAD_GOT
14773 && mips_symbolic_constant_p (XVECEXP (x, 0, 1),
14774 SYMBOL_CONTEXT_LEA, &type)
14775 && type == SYMBOL_GOTOFF_PAGE)
14776 return !mips_lo_sum_offset_lookup (htab, XVECEXP (x, 0, 1), NO_INSERT);
14781 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
14782 INSN and a previous instruction, avoid it by inserting nops after
14785 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
14786 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
14787 before using the value of that register. *HILO_DELAY counts the
14788 number of instructions since the last hilo hazard (that is,
14789 the number of instructions since the last MFLO or MFHI).
14791 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
14792 for the next instruction.
14794 LO_REG is an rtx for the LO register, used in dependence checking. */
14797 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
14798 rtx *delayed_reg, rtx lo_reg)
14803 pattern = PATTERN (insn);
14805 /* Do not put the whole function in .set noreorder if it contains
14806 an asm statement. We don't know whether there will be hazards
14807 between the asm statement and the gcc-generated code. */
14808 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
14809 cfun->machine->all_noreorder_p = false;
14811 /* Ignore zero-length instructions (barriers and the like). */
14812 ninsns = get_attr_length (insn) / 4;
14816 /* Work out how many nops are needed. Note that we only care about
14817 registers that are explicitly mentioned in the instruction's pattern.
14818 It doesn't matter that calls use the argument registers or that they
14819 clobber hi and lo. */
14820 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
14821 nops = 2 - *hilo_delay;
14822 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
14827 /* Insert the nops between this instruction and the previous one.
14828 Each new nop takes us further from the last hilo hazard. */
14829 *hilo_delay += nops;
14831 emit_insn_after (gen_hazard_nop (), after);
14833 /* Set up the state for the next instruction. */
14834 *hilo_delay += ninsns;
14836 if (INSN_CODE (insn) >= 0)
14837 switch (get_attr_hazard (insn))
14847 set = single_set (insn);
14849 *delayed_reg = SET_DEST (set);
14854 /* Go through the instruction stream and insert nops where necessary.
14855 Also delete any high-part relocations whose partnering low parts
14856 are now all dead. See if the whole function can then be put into
14857 .set noreorder and .set nomacro. */
14860 mips_reorg_process_insns (void)
14862 rtx insn, last_insn, subinsn, next_insn, lo_reg, delayed_reg;
14866 /* Force all instructions to be split into their final form. */
14867 split_all_insns_noflow ();
14869 /* Recalculate instruction lengths without taking nops into account. */
14870 cfun->machine->ignore_hazard_length_p = true;
14871 shorten_branches (get_insns ());
14873 cfun->machine->all_noreorder_p = true;
14875 /* We don't track MIPS16 PC-relative offsets closely enough to make
14876 a good job of "set .noreorder" code in MIPS16 mode. */
14878 cfun->machine->all_noreorder_p = false;
14880 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
14881 if (!TARGET_EXPLICIT_RELOCS)
14882 cfun->machine->all_noreorder_p = false;
14884 /* Profiled functions can't be all noreorder because the profiler
14885 support uses assembler macros. */
14887 cfun->machine->all_noreorder_p = false;
14889 /* Code compiled with -mfix-vr4120 or -mfix-24k can't be all noreorder
14890 because we rely on the assembler to work around some errata. */
14891 if (TARGET_FIX_VR4120 || TARGET_FIX_24K)
14892 cfun->machine->all_noreorder_p = false;
14894 /* The same is true for -mfix-vr4130 if we might generate MFLO or
14895 MFHI instructions. Note that we avoid using MFLO and MFHI if
14896 the VR4130 MACC and DMACC instructions are available instead;
14897 see the *mfhilo_{si,di}_macc patterns. */
14898 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
14899 cfun->machine->all_noreorder_p = false;
14901 htab = htab_create (37, mips_lo_sum_offset_hash,
14902 mips_lo_sum_offset_eq, free);
14904 /* Make a first pass over the instructions, recording all the LO_SUMs. */
14905 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
14906 FOR_EACH_SUBINSN (subinsn, insn)
14907 if (USEFUL_INSN_P (subinsn))
14908 for_each_rtx (&PATTERN (subinsn), mips_record_lo_sum, htab);
14913 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
14915 /* Make a second pass over the instructions. Delete orphaned
14916 high-part relocations or turn them into NOPs. Avoid hazards
14917 by inserting NOPs. */
14918 for (insn = get_insns (); insn != 0; insn = next_insn)
14920 next_insn = NEXT_INSN (insn);
14921 if (USEFUL_INSN_P (insn))
14923 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
14925 /* If we find an orphaned high-part relocation in a delay
14926 slot, it's easier to turn that instruction into a NOP than
14927 to delete it. The delay slot will be a NOP either way. */
14928 FOR_EACH_SUBINSN (subinsn, insn)
14929 if (INSN_P (subinsn))
14931 if (mips_orphaned_high_part_p (htab, subinsn))
14933 PATTERN (subinsn) = gen_nop ();
14934 INSN_CODE (subinsn) = CODE_FOR_nop;
14936 mips_avoid_hazard (last_insn, subinsn, &hilo_delay,
14937 &delayed_reg, lo_reg);
14943 /* INSN is a single instruction. Delete it if it's an
14944 orphaned high-part relocation. */
14945 if (mips_orphaned_high_part_p (htab, insn))
14946 delete_insn (insn);
14947 /* Also delete cache barriers if the last instruction
14948 was an annulled branch. INSN will not be speculatively
14950 else if (recog_memoized (insn) == CODE_FOR_r10k_cache_barrier
14952 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn)))
14953 delete_insn (insn);
14956 mips_avoid_hazard (last_insn, insn, &hilo_delay,
14957 &delayed_reg, lo_reg);
14964 htab_delete (htab);
14967 /* If we are using a GOT, but have not decided to use a global pointer yet,
14968 see whether we need one to implement long branches. Convert the ghost
14969 global-pointer instructions into real ones if so. */
14972 mips_expand_ghost_gp_insns (void)
14977 /* Quick exit if we already know that we will or won't need a
14979 if (!TARGET_USE_GOT
14980 || cfun->machine->global_pointer == INVALID_REGNUM
14981 || mips_must_initialize_gp_p ())
14984 shorten_branches (get_insns ());
14986 /* Look for a branch that is longer than normal. The normal length for
14987 non-MIPS16 branches is 8, because the length includes the delay slot.
14988 It is 4 for MIPS16, because MIPS16 branches are extended instructions,
14989 but they have no delay slot. */
14990 normal_length = (TARGET_MIPS16 ? 4 : 8);
14991 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
14993 && USEFUL_INSN_P (insn)
14994 && get_attr_length (insn) > normal_length)
14997 if (insn == NULL_RTX)
15000 /* We've now established that we need $gp. */
15001 cfun->machine->must_initialize_gp_p = true;
15002 split_all_insns_noflow ();
15007 /* Subroutine of mips_reorg to manage passes that require DF. */
15010 mips_df_reorg (void)
15012 /* Create def-use chains. */
15013 df_set_flags (DF_EQ_NOTES);
15014 df_chain_add_problem (DF_UD_CHAIN);
15017 if (TARGET_RELAX_PIC_CALLS)
15018 mips_annotate_pic_calls ();
15020 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE)
15021 r10k_insert_cache_barriers ();
15023 df_finish_pass (false);
15026 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
15031 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during
15032 insn splitting in mips16_lay_out_constants, DF insn info is only kept up
15033 to date if the CFG is available. */
15034 if (mips_cfg_in_reorg ())
15035 compute_bb_for_insn ();
15036 mips16_lay_out_constants ();
15037 if (mips_cfg_in_reorg ())
15040 free_bb_for_insn ();
15043 if (optimize > 0 && flag_delayed_branch)
15044 dbr_schedule (get_insns ());
15045 mips_reorg_process_insns ();
15047 && TARGET_EXPLICIT_RELOCS
15049 && TARGET_VR4130_ALIGN)
15050 vr4130_align_insns ();
15051 if (mips_expand_ghost_gp_insns ())
15052 /* The expansion could invalidate some of the VR4130 alignment
15053 optimizations, but this should be an extremely rare case anyhow. */
15054 mips_reorg_process_insns ();
15057 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
15058 in order to avoid duplicating too much logic from elsewhere. */
15061 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
15062 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
15065 rtx this_rtx, temp1, temp2, insn, fnaddr;
15066 bool use_sibcall_p;
15068 /* Pretend to be a post-reload pass while generating rtl. */
15069 reload_completed = 1;
15071 /* Mark the end of the (empty) prologue. */
15072 emit_note (NOTE_INSN_PROLOGUE_END);
15074 /* Determine if we can use a sibcall to call FUNCTION directly. */
15075 fnaddr = XEXP (DECL_RTL (function), 0);
15076 use_sibcall_p = (mips_function_ok_for_sibcall (function, NULL)
15077 && const_call_insn_operand (fnaddr, Pmode));
15079 /* Determine if we need to load FNADDR from the GOT. */
15081 && (mips_got_symbol_type_p
15082 (mips_classify_symbol (fnaddr, SYMBOL_CONTEXT_LEA))))
15084 /* Pick a global pointer. Use a call-clobbered register if
15085 TARGET_CALL_SAVED_GP. */
15086 cfun->machine->global_pointer
15087 = TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM;
15088 cfun->machine->must_initialize_gp_p = true;
15089 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
15091 /* Set up the global pointer for n32 or n64 abicalls. */
15092 mips_emit_loadgp ();
15095 /* We need two temporary registers in some cases. */
15096 temp1 = gen_rtx_REG (Pmode, 2);
15097 temp2 = gen_rtx_REG (Pmode, 3);
15099 /* Find out which register contains the "this" pointer. */
15100 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
15101 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
15103 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST);
15105 /* Add DELTA to THIS_RTX. */
15108 rtx offset = GEN_INT (delta);
15109 if (!SMALL_OPERAND (delta))
15111 mips_emit_move (temp1, offset);
15114 emit_insn (gen_add3_insn (this_rtx, this_rtx, offset));
15117 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
15118 if (vcall_offset != 0)
15122 /* Set TEMP1 to *THIS_RTX. */
15123 mips_emit_move (temp1, gen_rtx_MEM (Pmode, this_rtx));
15125 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
15126 addr = mips_add_offset (temp2, temp1, vcall_offset);
15128 /* Load the offset and add it to THIS_RTX. */
15129 mips_emit_move (temp1, gen_rtx_MEM (Pmode, addr));
15130 emit_insn (gen_add3_insn (this_rtx, this_rtx, temp1));
15133 /* Jump to the target function. Use a sibcall if direct jumps are
15134 allowed, otherwise load the address into a register first. */
15137 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
15138 SIBLING_CALL_P (insn) = 1;
15142 /* This is messy. GAS treats "la $25,foo" as part of a call
15143 sequence and may allow a global "foo" to be lazily bound.
15144 The general move patterns therefore reject this combination.
15146 In this context, lazy binding would actually be OK
15147 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
15148 TARGET_CALL_SAVED_GP; see mips_load_call_address.
15149 We must therefore load the address via a temporary
15150 register if mips_dangerous_for_la25_p.
15152 If we jump to the temporary register rather than $25,
15153 the assembler can use the move insn to fill the jump's
15156 We can use the same technique for MIPS16 code, where $25
15157 is not a valid JR register. */
15158 if (TARGET_USE_PIC_FN_ADDR_REG
15160 && !mips_dangerous_for_la25_p (fnaddr))
15161 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
15162 mips_load_call_address (MIPS_CALL_SIBCALL, temp1, fnaddr);
15164 if (TARGET_USE_PIC_FN_ADDR_REG
15165 && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
15166 mips_emit_move (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
15167 emit_jump_insn (gen_indirect_jump (temp1));
15170 /* Run just enough of rest_of_compilation. This sequence was
15171 "borrowed" from alpha.c. */
15172 insn = get_insns ();
15173 insn_locators_alloc ();
15174 split_all_insns_noflow ();
15175 mips16_lay_out_constants ();
15176 shorten_branches (insn);
15177 final_start_function (insn, file, 1);
15178 final (insn, file, 1);
15179 final_end_function ();
15181 /* Clean up the vars set above. Note that final_end_function resets
15182 the global pointer for us. */
15183 reload_completed = 0;
15186 /* The last argument passed to mips_set_mips16_mode, or negative if the
15187 function hasn't been called yet.
15189 There are two copies of this information. One is saved and restored
15190 by the PCH process while the other is specific to this compiler
15191 invocation. The information calculated by mips_set_mips16_mode
15192 is invalid unless the two variables are the same. */
15193 static int was_mips16_p = -1;
15194 static GTY(()) int was_mips16_pch_p = -1;
15196 /* Set up the target-dependent global state so that it matches the
15197 current function's ISA mode. */
15200 mips_set_mips16_mode (int mips16_p)
15202 if (mips16_p == was_mips16_p
15203 && mips16_p == was_mips16_pch_p)
15206 /* Restore base settings of various flags. */
15207 target_flags = mips_base_target_flags;
15208 flag_schedule_insns = mips_base_schedule_insns;
15209 flag_reorder_blocks_and_partition = mips_base_reorder_blocks_and_partition;
15210 flag_move_loop_invariants = mips_base_move_loop_invariants;
15211 align_loops = mips_base_align_loops;
15212 align_jumps = mips_base_align_jumps;
15213 align_functions = mips_base_align_functions;
15217 /* Switch to MIPS16 mode. */
15218 target_flags |= MASK_MIPS16;
15220 /* Don't run the scheduler before reload, since it tends to
15221 increase register pressure. */
15222 flag_schedule_insns = 0;
15224 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
15225 the whole function to be in a single section. */
15226 flag_reorder_blocks_and_partition = 0;
15228 /* Don't move loop invariants, because it tends to increase
15229 register pressure. It also introduces an extra move in cases
15230 where the constant is the first operand in a two-operand binary
15231 instruction, or when it forms a register argument to a functon
15233 flag_move_loop_invariants = 0;
15235 target_flags |= MASK_EXPLICIT_RELOCS;
15237 /* Experiments suggest we get the best overall section-anchor
15238 results from using the range of an unextended LW or SW. Code
15239 that makes heavy use of byte or short accesses can do better
15240 with ranges of 0...31 and 0...63 respectively, but most code is
15241 sensitive to the range of LW and SW instead. */
15242 targetm.min_anchor_offset = 0;
15243 targetm.max_anchor_offset = 127;
15245 targetm.const_anchor = 0;
15247 /* MIPS16 has no BAL instruction. */
15248 target_flags &= ~MASK_RELAX_PIC_CALLS;
15250 if (flag_pic && !TARGET_OLDABI)
15251 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
15254 sorry ("MIPS16 -mxgot code");
15256 if (TARGET_HARD_FLOAT_ABI && !TARGET_OLDABI)
15257 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
15261 /* Switch to normal (non-MIPS16) mode. */
15262 target_flags &= ~MASK_MIPS16;
15264 /* Provide default values for align_* for 64-bit targets. */
15267 if (align_loops == 0)
15269 if (align_jumps == 0)
15271 if (align_functions == 0)
15272 align_functions = 8;
15275 targetm.min_anchor_offset = -32768;
15276 targetm.max_anchor_offset = 32767;
15278 targetm.const_anchor = 0x8000;
15281 /* (Re)initialize MIPS target internals for new ISA. */
15282 mips_init_relocs ();
15286 if (!mips16_globals)
15287 mips16_globals = save_target_globals ();
15289 restore_target_globals (mips16_globals);
15292 restore_target_globals (&default_target_globals);
15294 was_mips16_p = mips16_p;
15295 was_mips16_pch_p = mips16_p;
15298 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
15299 function should use the MIPS16 ISA and switch modes accordingly. */
15302 mips_set_current_function (tree fndecl)
15304 mips_set_mips16_mode (mips_use_mips16_mode_p (fndecl));
15307 /* Allocate a chunk of memory for per-function machine-dependent data. */
15309 static struct machine_function *
15310 mips_init_machine_status (void)
15312 return ggc_alloc_cleared_machine_function ();
15315 /* Return the processor associated with the given ISA level, or null
15316 if the ISA isn't valid. */
15318 static const struct mips_cpu_info *
15319 mips_cpu_info_from_isa (int isa)
15323 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
15324 if (mips_cpu_info_table[i].isa == isa)
15325 return mips_cpu_info_table + i;
15330 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
15331 with a final "000" replaced by "k". Ignore case.
15333 Note: this function is shared between GCC and GAS. */
15336 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
15338 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
15339 given++, canonical++;
15341 return ((*given == 0 && *canonical == 0)
15342 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
15345 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
15346 CPU name. We've traditionally allowed a lot of variation here.
15348 Note: this function is shared between GCC and GAS. */
15351 mips_matching_cpu_name_p (const char *canonical, const char *given)
15353 /* First see if the name matches exactly, or with a final "000"
15354 turned into "k". */
15355 if (mips_strict_matching_cpu_name_p (canonical, given))
15358 /* If not, try comparing based on numerical designation alone.
15359 See if GIVEN is an unadorned number, or 'r' followed by a number. */
15360 if (TOLOWER (*given) == 'r')
15362 if (!ISDIGIT (*given))
15365 /* Skip over some well-known prefixes in the canonical name,
15366 hoping to find a number there too. */
15367 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
15369 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
15371 else if (TOLOWER (canonical[0]) == 'r')
15374 return mips_strict_matching_cpu_name_p (canonical, given);
15377 /* Return the mips_cpu_info entry for the processor or ISA given
15378 by CPU_STRING. Return null if the string isn't recognized.
15380 A similar function exists in GAS. */
15382 static const struct mips_cpu_info *
15383 mips_parse_cpu (const char *cpu_string)
15388 /* In the past, we allowed upper-case CPU names, but it doesn't
15389 work well with the multilib machinery. */
15390 for (s = cpu_string; *s != 0; s++)
15393 warning (0, "CPU names must be lower case");
15397 /* 'from-abi' selects the most compatible architecture for the given
15398 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
15399 EABIs, we have to decide whether we're using the 32-bit or 64-bit
15401 if (strcasecmp (cpu_string, "from-abi") == 0)
15402 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
15403 : ABI_NEEDS_64BIT_REGS ? 3
15404 : (TARGET_64BIT ? 3 : 1));
15406 /* 'default' has traditionally been a no-op. Probably not very useful. */
15407 if (strcasecmp (cpu_string, "default") == 0)
15410 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
15411 if (mips_matching_cpu_name_p (mips_cpu_info_table[i].name, cpu_string))
15412 return mips_cpu_info_table + i;
15417 /* Set up globals to generate code for the ISA or processor
15418 described by INFO. */
15421 mips_set_architecture (const struct mips_cpu_info *info)
15425 mips_arch_info = info;
15426 mips_arch = info->cpu;
15427 mips_isa = info->isa;
15431 /* Likewise for tuning. */
15434 mips_set_tune (const struct mips_cpu_info *info)
15438 mips_tune_info = info;
15439 mips_tune = info->cpu;
15443 /* Implement TARGET_HANDLE_OPTION. */
15446 mips_handle_option (struct gcc_options *opts, struct gcc_options *opts_set,
15447 const struct cl_decoded_option *decoded,
15448 location_t loc ATTRIBUTE_UNUSED)
15450 size_t code = decoded->opt_index;
15451 const char *arg = decoded->arg;
15453 gcc_assert (opts == &global_options);
15454 gcc_assert (opts_set == &global_options_set);
15459 if (strcmp (arg, "32") == 0)
15461 else if (strcmp (arg, "o64") == 0)
15462 mips_abi = ABI_O64;
15463 else if (strcmp (arg, "n32") == 0)
15464 mips_abi = ABI_N32;
15465 else if (strcmp (arg, "64") == 0)
15467 else if (strcmp (arg, "eabi") == 0)
15468 mips_abi = ABI_EABI;
15475 return mips_parse_cpu (arg) != 0;
15478 mips_isa_option_info = mips_parse_cpu (ACONCAT (("mips", arg, NULL)));
15479 return mips_isa_option_info != 0;
15481 case OPT_mno_flush_func:
15482 mips_cache_flush_func = NULL;
15485 case OPT_mcode_readable_:
15486 if (strcmp (arg, "yes") == 0)
15487 mips_code_readable = CODE_READABLE_YES;
15488 else if (strcmp (arg, "pcrel") == 0)
15489 mips_code_readable = CODE_READABLE_PCREL;
15490 else if (strcmp (arg, "no") == 0)
15491 mips_code_readable = CODE_READABLE_NO;
15496 case OPT_mr10k_cache_barrier_:
15497 if (strcmp (arg, "load-store") == 0)
15498 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_LOAD_STORE;
15499 else if (strcmp (arg, "store") == 0)
15500 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_STORE;
15501 else if (strcmp (arg, "none") == 0)
15502 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE;
15512 /* Implement TARGET_OPTION_OVERRIDE. */
15515 mips_option_override (void)
15517 int i, start, regno, mode;
15519 /* Process flags as though we were generating non-MIPS16 code. */
15520 mips_base_mips16 = TARGET_MIPS16;
15521 target_flags &= ~MASK_MIPS16;
15523 #ifdef SUBTARGET_OVERRIDE_OPTIONS
15524 SUBTARGET_OVERRIDE_OPTIONS;
15527 /* -mno-float overrides -mhard-float and -msoft-float. */
15528 if (TARGET_NO_FLOAT)
15530 target_flags |= MASK_SOFT_FLOAT_ABI;
15531 target_flags_explicit |= MASK_SOFT_FLOAT_ABI;
15534 if (TARGET_FLIP_MIPS16)
15535 TARGET_INTERLINK_MIPS16 = 1;
15537 /* Set the small data limit. */
15538 mips_small_data_threshold = (global_options_set.x_g_switch_value
15540 : MIPS_DEFAULT_GVALUE);
15542 /* The following code determines the architecture and register size.
15543 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
15544 The GAS and GCC code should be kept in sync as much as possible. */
15546 if (mips_arch_string != 0)
15547 mips_set_architecture (mips_parse_cpu (mips_arch_string));
15549 if (mips_isa_option_info != 0)
15551 if (mips_arch_info == 0)
15552 mips_set_architecture (mips_isa_option_info);
15553 else if (mips_arch_info->isa != mips_isa_option_info->isa)
15554 error ("%<-%s%> conflicts with the other architecture options, "
15555 "which specify a %s processor",
15556 mips_isa_option_info->name,
15557 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
15560 if (mips_arch_info == 0)
15562 #ifdef MIPS_CPU_STRING_DEFAULT
15563 mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT));
15565 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
15569 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
15570 error ("%<-march=%s%> is not compatible with the selected ABI",
15571 mips_arch_info->name);
15573 /* Optimize for mips_arch, unless -mtune selects a different processor. */
15574 if (mips_tune_string != 0)
15575 mips_set_tune (mips_parse_cpu (mips_tune_string));
15577 if (mips_tune_info == 0)
15578 mips_set_tune (mips_arch_info);
15580 if ((target_flags_explicit & MASK_64BIT) != 0)
15582 /* The user specified the size of the integer registers. Make sure
15583 it agrees with the ABI and ISA. */
15584 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
15585 error ("%<-mgp64%> used with a 32-bit processor");
15586 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
15587 error ("%<-mgp32%> used with a 64-bit ABI");
15588 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
15589 error ("%<-mgp64%> used with a 32-bit ABI");
15593 /* Infer the integer register size from the ABI and processor.
15594 Restrict ourselves to 32-bit registers if that's all the
15595 processor has, or if the ABI cannot handle 64-bit registers. */
15596 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
15597 target_flags &= ~MASK_64BIT;
15599 target_flags |= MASK_64BIT;
15602 if ((target_flags_explicit & MASK_FLOAT64) != 0)
15604 if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
15605 error ("unsupported combination: %s", "-mfp64 -msingle-float");
15606 else if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
15607 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
15608 else if (!TARGET_64BIT && TARGET_FLOAT64)
15610 if (!ISA_HAS_MXHC1)
15611 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
15612 " the target supports the mfhc1 and mthc1 instructions");
15613 else if (mips_abi != ABI_32)
15614 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
15620 /* -msingle-float selects 32-bit float registers. Otherwise the
15621 float registers should be the same size as the integer ones. */
15622 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
15623 target_flags |= MASK_FLOAT64;
15625 target_flags &= ~MASK_FLOAT64;
15628 /* End of code shared with GAS. */
15630 /* If no -mlong* option was given, infer it from the other options. */
15631 if ((target_flags_explicit & MASK_LONG64) == 0)
15633 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
15634 target_flags |= MASK_LONG64;
15636 target_flags &= ~MASK_LONG64;
15639 if (!TARGET_OLDABI)
15640 flag_pcc_struct_return = 0;
15642 /* Decide which rtx_costs structure to use. */
15644 mips_cost = &mips_rtx_cost_optimize_size;
15646 mips_cost = &mips_rtx_cost_data[mips_tune];
15648 /* If the user hasn't specified a branch cost, use the processor's
15650 if (mips_branch_cost == 0)
15651 mips_branch_cost = mips_cost->branch_cost;
15653 /* If neither -mbranch-likely nor -mno-branch-likely was given
15654 on the command line, set MASK_BRANCHLIKELY based on the target
15655 architecture and tuning flags. Annulled delay slots are a
15656 size win, so we only consider the processor-specific tuning
15657 for !optimize_size. */
15658 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
15660 if (ISA_HAS_BRANCHLIKELY
15662 || (mips_tune_info->tune_flags & PTF_AVOID_BRANCHLIKELY) == 0))
15663 target_flags |= MASK_BRANCHLIKELY;
15665 target_flags &= ~MASK_BRANCHLIKELY;
15667 else if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
15668 warning (0, "the %qs architecture does not support branch-likely"
15669 " instructions", mips_arch_info->name);
15671 /* The effect of -mabicalls isn't defined for the EABI. */
15672 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
15674 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
15675 target_flags &= ~MASK_ABICALLS;
15678 if (TARGET_ABICALLS_PIC2)
15679 /* We need to set flag_pic for executables as well as DSOs
15680 because we may reference symbols that are not defined in
15681 the final executable. (MIPS does not use things like
15682 copy relocs, for example.)
15684 There is a body of code that uses __PIC__ to distinguish
15685 between -mabicalls and -mno-abicalls code. The non-__PIC__
15686 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
15687 long as any indirect jumps use $25. */
15690 /* -mvr4130-align is a "speed over size" optimization: it usually produces
15691 faster code, but at the expense of more nops. Enable it at -O3 and
15693 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
15694 target_flags |= MASK_VR4130_ALIGN;
15696 /* Prefer a call to memcpy over inline code when optimizing for size,
15697 though see MOVE_RATIO in mips.h. */
15698 if (optimize_size && (target_flags_explicit & MASK_MEMCPY) == 0)
15699 target_flags |= MASK_MEMCPY;
15701 /* If we have a nonzero small-data limit, check that the -mgpopt
15702 setting is consistent with the other target flags. */
15703 if (mips_small_data_threshold > 0)
15707 if (!TARGET_EXPLICIT_RELOCS)
15708 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
15710 TARGET_LOCAL_SDATA = false;
15711 TARGET_EXTERN_SDATA = false;
15715 if (TARGET_VXWORKS_RTP)
15716 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
15718 if (TARGET_ABICALLS)
15719 warning (0, "cannot use small-data accesses for %qs",
15724 #ifdef MIPS_TFMODE_FORMAT
15725 REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
15728 /* Make sure that the user didn't turn off paired single support when
15729 MIPS-3D support is requested. */
15731 && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
15732 && !TARGET_PAIRED_SINGLE_FLOAT)
15733 error ("%<-mips3d%> requires %<-mpaired-single%>");
15735 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
15737 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
15739 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
15740 and TARGET_HARD_FLOAT_ABI are both true. */
15741 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT_ABI))
15742 error ("%qs must be used with %qs",
15743 TARGET_MIPS3D ? "-mips3d" : "-mpaired-single",
15744 TARGET_HARD_FLOAT_ABI ? "-mfp64" : "-mhard-float");
15746 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
15748 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_HAS_PAIRED_SINGLE)
15749 warning (0, "the %qs architecture does not support paired-single"
15750 " instructions", mips_arch_info->name);
15752 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
15753 && !TARGET_CACHE_BUILTIN)
15755 error ("%qs requires a target that provides the %qs instruction",
15756 "-mr10k-cache-barrier", "cache");
15757 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE;
15760 /* If TARGET_DSPR2, enable MASK_DSP. */
15762 target_flags |= MASK_DSP;
15764 /* .eh_frame addresses should be the same width as a C pointer.
15765 Most MIPS ABIs support only one pointer size, so the assembler
15766 will usually know exactly how big an .eh_frame address is.
15768 Unfortunately, this is not true of the 64-bit EABI. The ABI was
15769 originally defined to use 64-bit pointers (i.e. it is LP64), and
15770 this is still the default mode. However, we also support an n32-like
15771 ILP32 mode, which is selected by -mlong32. The problem is that the
15772 assembler has traditionally not had an -mlong option, so it has
15773 traditionally not known whether we're using the ILP32 or LP64 form.
15775 As it happens, gas versions up to and including 2.19 use _32-bit_
15776 addresses for EABI64 .cfi_* directives. This is wrong for the
15777 default LP64 mode, so we can't use the directives by default.
15778 Moreover, since gas's current behavior is at odds with gcc's
15779 default behavior, it seems unwise to rely on future versions
15780 of gas behaving the same way. We therefore avoid using .cfi
15781 directives for -mlong32 as well. */
15782 if (mips_abi == ABI_EABI && TARGET_64BIT)
15783 flag_dwarf2_cfi_asm = 0;
15785 /* .cfi_* directives generate a read-only section, so fall back on
15786 manual .eh_frame creation if we need the section to be writable. */
15787 if (TARGET_WRITABLE_EH_FRAME)
15788 flag_dwarf2_cfi_asm = 0;
15790 mips_init_print_operand_punct ();
15792 /* Set up array to map GCC register number to debug register number.
15793 Ignore the special purpose register numbers. */
15795 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
15797 mips_dbx_regno[i] = INVALID_REGNUM;
15798 if (GP_REG_P (i) || FP_REG_P (i) || ALL_COP_REG_P (i))
15799 mips_dwarf_regno[i] = i;
15801 mips_dwarf_regno[i] = INVALID_REGNUM;
15804 start = GP_DBX_FIRST - GP_REG_FIRST;
15805 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
15806 mips_dbx_regno[i] = i + start;
15808 start = FP_DBX_FIRST - FP_REG_FIRST;
15809 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
15810 mips_dbx_regno[i] = i + start;
15812 /* Accumulator debug registers use big-endian ordering. */
15813 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
15814 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
15815 mips_dwarf_regno[HI_REGNUM] = MD_REG_FIRST + 0;
15816 mips_dwarf_regno[LO_REGNUM] = MD_REG_FIRST + 1;
15817 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
15819 mips_dwarf_regno[i + TARGET_LITTLE_ENDIAN] = i;
15820 mips_dwarf_regno[i + TARGET_BIG_ENDIAN] = i + 1;
15823 /* Set up mips_hard_regno_mode_ok. */
15824 for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
15825 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
15826 mips_hard_regno_mode_ok[mode][regno]
15827 = mips_hard_regno_mode_ok_p (regno, (enum machine_mode) mode);
15829 /* Function to allocate machine-dependent function status. */
15830 init_machine_status = &mips_init_machine_status;
15832 /* Default to working around R4000 errata only if the processor
15833 was selected explicitly. */
15834 if ((target_flags_explicit & MASK_FIX_R4000) == 0
15835 && mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
15836 target_flags |= MASK_FIX_R4000;
15838 /* Default to working around R4400 errata only if the processor
15839 was selected explicitly. */
15840 if ((target_flags_explicit & MASK_FIX_R4400) == 0
15841 && mips_matching_cpu_name_p (mips_arch_info->name, "r4400"))
15842 target_flags |= MASK_FIX_R4400;
15844 /* Default to working around R10000 errata only if the processor
15845 was selected explicitly. */
15846 if ((target_flags_explicit & MASK_FIX_R10000) == 0
15847 && mips_matching_cpu_name_p (mips_arch_info->name, "r10000"))
15848 target_flags |= MASK_FIX_R10000;
15850 /* Make sure that branch-likely instructions available when using
15851 -mfix-r10000. The instructions are not available if either:
15853 1. -mno-branch-likely was passed.
15854 2. The selected ISA does not support branch-likely and
15855 the command line does not include -mbranch-likely. */
15856 if (TARGET_FIX_R10000
15857 && ((target_flags_explicit & MASK_BRANCHLIKELY) == 0
15858 ? !ISA_HAS_BRANCHLIKELY
15859 : !TARGET_BRANCHLIKELY))
15860 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
15862 if (TARGET_SYNCI && !ISA_HAS_SYNCI)
15864 warning (0, "the %qs architecture does not support the synci "
15865 "instruction", mips_arch_info->name);
15866 target_flags &= ~MASK_SYNCI;
15869 /* Only optimize PIC indirect calls if they are actually required. */
15870 if (!TARGET_USE_GOT || !TARGET_EXPLICIT_RELOCS)
15871 target_flags &= ~MASK_RELAX_PIC_CALLS;
15873 /* Save base state of options. */
15874 mips_base_target_flags = target_flags;
15875 mips_base_schedule_insns = flag_schedule_insns;
15876 mips_base_reorder_blocks_and_partition = flag_reorder_blocks_and_partition;
15877 mips_base_move_loop_invariants = flag_move_loop_invariants;
15878 mips_base_align_loops = align_loops;
15879 mips_base_align_jumps = align_jumps;
15880 mips_base_align_functions = align_functions;
15882 /* Now select the ISA mode.
15884 Do all CPP-sensitive stuff in non-MIPS16 mode; we'll switch to
15885 MIPS16 mode afterwards if need be. */
15886 mips_set_mips16_mode (false);
15889 /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
15890 static const struct default_options mips_option_optimization_table[] =
15892 { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
15893 { OPT_LEVELS_NONE, 0, NULL, 0 }
15896 /* Swap the register information for registers I and I + 1, which
15897 currently have the wrong endianness. Note that the registers'
15898 fixedness and call-clobberedness might have been set on the
15902 mips_swap_registers (unsigned int i)
15907 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
15908 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
15910 SWAP_INT (fixed_regs[i], fixed_regs[i + 1]);
15911 SWAP_INT (call_used_regs[i], call_used_regs[i + 1]);
15912 SWAP_INT (call_really_used_regs[i], call_really_used_regs[i + 1]);
15913 SWAP_STRING (reg_names[i], reg_names[i + 1]);
15919 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
15922 mips_conditional_register_usage (void)
15927 /* These DSP control register fields are global. */
15928 global_regs[CCDSP_PO_REGNUM] = 1;
15929 global_regs[CCDSP_SC_REGNUM] = 1;
15935 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
15936 fixed_regs[regno] = call_used_regs[regno] = 1;
15938 if (!TARGET_HARD_FLOAT)
15942 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
15943 fixed_regs[regno] = call_used_regs[regno] = 1;
15944 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
15945 fixed_regs[regno] = call_used_regs[regno] = 1;
15947 else if (! ISA_HAS_8CC)
15951 /* We only have a single condition-code register. We implement
15952 this by fixing all the condition-code registers and generating
15953 RTL that refers directly to ST_REG_FIRST. */
15954 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
15955 fixed_regs[regno] = call_used_regs[regno] = 1;
15957 /* In MIPS16 mode, we permit the $t temporary registers to be used
15958 for reload. We prohibit the unused $s registers, since they
15959 are call-saved, and saving them via a MIPS16 register would
15960 probably waste more time than just reloading the value. */
15963 fixed_regs[18] = call_used_regs[18] = 1;
15964 fixed_regs[19] = call_used_regs[19] = 1;
15965 fixed_regs[20] = call_used_regs[20] = 1;
15966 fixed_regs[21] = call_used_regs[21] = 1;
15967 fixed_regs[22] = call_used_regs[22] = 1;
15968 fixed_regs[23] = call_used_regs[23] = 1;
15969 fixed_regs[26] = call_used_regs[26] = 1;
15970 fixed_regs[27] = call_used_regs[27] = 1;
15971 fixed_regs[30] = call_used_regs[30] = 1;
15973 /* $f20-$f23 are call-clobbered for n64. */
15974 if (mips_abi == ABI_64)
15977 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
15978 call_really_used_regs[regno] = call_used_regs[regno] = 1;
15980 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
15982 if (mips_abi == ABI_N32)
15985 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
15986 call_really_used_regs[regno] = call_used_regs[regno] = 1;
15988 /* Make sure that double-register accumulator values are correctly
15989 ordered for the current endianness. */
15990 if (TARGET_LITTLE_ENDIAN)
15992 unsigned int regno;
15994 mips_swap_registers (MD_REG_FIRST);
15995 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno += 2)
15996 mips_swap_registers (regno);
16000 /* Initialize vector TARGET to VALS. */
16003 mips_expand_vector_init (rtx target, rtx vals)
16005 enum machine_mode mode;
16006 enum machine_mode inner;
16007 unsigned int i, n_elts;
16010 mode = GET_MODE (target);
16011 inner = GET_MODE_INNER (mode);
16012 n_elts = GET_MODE_NUNITS (mode);
16014 gcc_assert (VECTOR_MODE_P (mode));
16016 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
16017 for (i = 0; i < n_elts; i++)
16018 emit_move_insn (adjust_address_nv (mem, inner, i * GET_MODE_SIZE (inner)),
16019 XVECEXP (vals, 0, i));
16021 emit_move_insn (target, mem);
16024 /* When generating MIPS16 code, we want to allocate $24 (T_REG) before
16025 other registers for instructions for which it is possible. This
16026 encourages the compiler to use CMP in cases where an XOR would
16027 require some register shuffling. */
16030 mips_order_regs_for_local_alloc (void)
16034 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
16035 reg_alloc_order[i] = i;
16039 /* It really doesn't matter where we put register 0, since it is
16040 a fixed register anyhow. */
16041 reg_alloc_order[0] = 24;
16042 reg_alloc_order[24] = 0;
16046 /* Implement EH_USES. */
16049 mips_eh_uses (unsigned int regno)
16051 if (reload_completed && !TARGET_ABSOLUTE_JUMPS)
16053 /* We need to force certain registers to be live in order to handle
16054 PIC long branches correctly. See mips_must_initialize_gp_p for
16056 if (mips_cfun_has_cprestore_slot_p ())
16058 if (regno == CPRESTORE_SLOT_REGNUM)
16063 if (cfun->machine->global_pointer == regno)
16071 /* Implement EPILOGUE_USES. */
16074 mips_epilogue_uses (unsigned int regno)
16076 /* Say that the epilogue uses the return address register. Note that
16077 in the case of sibcalls, the values "used by the epilogue" are
16078 considered live at the start of the called function. */
16079 if (regno == RETURN_ADDR_REGNUM)
16082 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
16083 See the comment above load_call<mode> for details. */
16084 if (TARGET_USE_GOT && (regno) == GOT_VERSION_REGNUM)
16087 /* An interrupt handler must preserve some registers that are
16088 ordinarily call-clobbered. */
16089 if (cfun->machine->interrupt_handler_p
16090 && mips_interrupt_extra_call_saved_reg_p (regno))
16096 /* A for_each_rtx callback. Stop the search if *X is an AT register. */
16099 mips_at_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
16101 return REG_P (*x) && REGNO (*x) == AT_REGNUM;
16104 /* Return true if INSN needs to be wrapped in ".set noat".
16105 INSN has NOPERANDS operands, stored in OPVEC. */
16108 mips_need_noat_wrapper_p (rtx insn, rtx *opvec, int noperands)
16112 if (recog_memoized (insn) >= 0)
16113 for (i = 0; i < noperands; i++)
16114 if (for_each_rtx (&opvec[i], mips_at_reg_p, NULL))
16119 /* Implement FINAL_PRESCAN_INSN. */
16122 mips_final_prescan_insn (rtx insn, rtx *opvec, int noperands)
16124 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
16125 mips_push_asm_switch (&mips_noat);
16128 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */
16131 mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED, rtx insn,
16132 rtx *opvec, int noperands)
16134 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
16135 mips_pop_asm_switch (&mips_noat);
16138 /* Return the function that is used to expand the <u>mulsidi3 pattern.
16139 EXT_CODE is the code of the extension used. Return NULL if widening
16140 multiplication shouldn't be used. */
16143 mips_mulsidi3_gen_fn (enum rtx_code ext_code)
16147 signed_p = ext_code == SIGN_EXTEND;
16150 /* Don't use widening multiplication with MULT when we have DMUL. Even
16151 with the extension of its input operands DMUL is faster. Note that
16152 the extension is not needed for signed multiplication. In order to
16153 ensure that we always remove the redundant sign-extension in this
16154 case we still expand mulsidi3 for DMUL. */
16156 return signed_p ? gen_mulsidi3_64bit_dmul : NULL;
16157 if (TARGET_FIX_R4000)
16159 return signed_p ? gen_mulsidi3_64bit : gen_umulsidi3_64bit;
16163 if (TARGET_FIX_R4000 && !ISA_HAS_DSP)
16164 return signed_p ? gen_mulsidi3_32bit_r4000 : gen_umulsidi3_32bit_r4000;
16165 return signed_p ? gen_mulsidi3_32bit : gen_umulsidi3_32bit;
16169 /* Return the size in bytes of the trampoline code, padded to
16170 TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target
16171 function address immediately follow. */
16174 mips_trampoline_code_size (void)
16176 if (TARGET_USE_PIC_FN_ADDR_REG)
16178 else if (ptr_mode == DImode)
16180 else if (ISA_HAS_LOAD_DELAY)
16186 /* Implement TARGET_TRAMPOLINE_INIT. */
16189 mips_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
16191 rtx addr, end_addr, high, low, opcode, mem;
16194 HOST_WIDE_INT end_addr_offset, static_chain_offset, target_function_offset;
16196 /* Work out the offsets of the pointers from the start of the
16197 trampoline code. */
16198 end_addr_offset = mips_trampoline_code_size ();
16199 static_chain_offset = end_addr_offset;
16200 target_function_offset = static_chain_offset + GET_MODE_SIZE (ptr_mode);
16202 /* Get pointers to the beginning and end of the code block. */
16203 addr = force_reg (Pmode, XEXP (m_tramp, 0));
16204 end_addr = mips_force_binary (Pmode, PLUS, addr, GEN_INT (end_addr_offset));
16206 #define OP(X) gen_int_mode (X, SImode)
16208 /* Build up the code in TRAMPOLINE. */
16210 if (TARGET_USE_PIC_FN_ADDR_REG)
16212 /* $25 contains the address of the trampoline. Emit code of the form:
16214 l[wd] $1, target_function_offset($25)
16215 l[wd] $static_chain, static_chain_offset($25)
16218 trampoline[i++] = OP (MIPS_LOAD_PTR (AT_REGNUM,
16219 target_function_offset,
16220 PIC_FUNCTION_ADDR_REGNUM));
16221 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
16222 static_chain_offset,
16223 PIC_FUNCTION_ADDR_REGNUM));
16224 trampoline[i++] = OP (MIPS_JR (AT_REGNUM));
16225 trampoline[i++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM, AT_REGNUM));
16227 else if (ptr_mode == DImode)
16229 /* It's too cumbersome to create the full 64-bit address, so let's
16235 1: l[wd] $25, target_function_offset - 12($31)
16236 l[wd] $static_chain, static_chain_offset - 12($31)
16240 where 12 is the offset of "1:" from the start of the code block. */
16241 trampoline[i++] = OP (MIPS_MOVE (AT_REGNUM, RETURN_ADDR_REGNUM));
16242 trampoline[i++] = OP (MIPS_BAL (1));
16243 trampoline[i++] = OP (MIPS_NOP);
16244 trampoline[i++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
16245 target_function_offset - 12,
16246 RETURN_ADDR_REGNUM));
16247 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
16248 static_chain_offset - 12,
16249 RETURN_ADDR_REGNUM));
16250 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
16251 trampoline[i++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM, AT_REGNUM));
16255 /* If the target has load delays, emit:
16257 lui $1, %hi(end_addr)
16258 lw $25, %lo(end_addr + ...)($1)
16259 lw $static_chain, %lo(end_addr + ...)($1)
16265 lui $1, %hi(end_addr)
16266 lw $25, %lo(end_addr + ...)($1)
16268 lw $static_chain, %lo(end_addr + ...)($1). */
16270 /* Split END_ADDR into %hi and %lo values. Trampolines are aligned
16271 to 64 bits, so the %lo value will have the bottom 3 bits clear. */
16272 high = expand_simple_binop (SImode, PLUS, end_addr, GEN_INT (0x8000),
16273 NULL, false, OPTAB_WIDEN);
16274 high = expand_simple_binop (SImode, LSHIFTRT, high, GEN_INT (16),
16275 NULL, false, OPTAB_WIDEN);
16276 low = convert_to_mode (SImode, gen_lowpart (HImode, end_addr), true);
16278 /* Emit the LUI. */
16279 opcode = OP (MIPS_LUI (AT_REGNUM, 0));
16280 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, high,
16281 NULL, false, OPTAB_WIDEN);
16283 /* Emit the load of the target function. */
16284 opcode = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
16285 target_function_offset - end_addr_offset,
16287 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
16288 NULL, false, OPTAB_WIDEN);
16290 /* Emit the JR here, if we can. */
16291 if (!ISA_HAS_LOAD_DELAY)
16292 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
16294 /* Emit the load of the static chain register. */
16295 opcode = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
16296 static_chain_offset - end_addr_offset,
16298 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
16299 NULL, false, OPTAB_WIDEN);
16301 /* Emit the JR, if we couldn't above. */
16302 if (ISA_HAS_LOAD_DELAY)
16304 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
16305 trampoline[i++] = OP (MIPS_NOP);
16311 /* Copy the trampoline code. Leave any padding uninitialized. */
16312 for (j = 0; j < i; j++)
16314 mem = adjust_address (m_tramp, SImode, j * GET_MODE_SIZE (SImode));
16315 mips_emit_move (mem, trampoline[j]);
16318 /* Set up the static chain pointer field. */
16319 mem = adjust_address (m_tramp, ptr_mode, static_chain_offset);
16320 mips_emit_move (mem, chain_value);
16322 /* Set up the target function field. */
16323 mem = adjust_address (m_tramp, ptr_mode, target_function_offset);
16324 mips_emit_move (mem, XEXP (DECL_RTL (fndecl), 0));
16326 /* Flush the code part of the trampoline. */
16327 emit_insn (gen_add3_insn (end_addr, addr, GEN_INT (TRAMPOLINE_SIZE)));
16328 emit_insn (gen_clear_cache (addr, end_addr));
16331 /* Implement FUNCTION_PROFILER. */
16333 void mips_function_profiler (FILE *file)
16336 sorry ("mips16 function profiling");
16337 if (TARGET_LONG_CALLS)
16339 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */
16340 if (Pmode == DImode)
16341 fprintf (file, "\tdla\t%s,_mcount\n", reg_names[3]);
16343 fprintf (file, "\tla\t%s,_mcount\n", reg_names[3]);
16345 mips_push_asm_switch (&mips_noat);
16346 fprintf (file, "\tmove\t%s,%s\t\t# save current return address\n",
16347 reg_names[AT_REGNUM], reg_names[RETURN_ADDR_REGNUM]);
16348 /* _mcount treats $2 as the static chain register. */
16349 if (cfun->static_chain_decl != NULL)
16350 fprintf (file, "\tmove\t%s,%s\n", reg_names[2],
16351 reg_names[STATIC_CHAIN_REGNUM]);
16352 if (TARGET_MCOUNT_RA_ADDRESS)
16354 /* If TARGET_MCOUNT_RA_ADDRESS load $12 with the address of the
16355 ra save location. */
16356 if (cfun->machine->frame.ra_fp_offset == 0)
16357 /* ra not saved, pass zero. */
16358 fprintf (file, "\tmove\t%s,%s\n", reg_names[12], reg_names[0]);
16360 fprintf (file, "\t%s\t%s," HOST_WIDE_INT_PRINT_DEC "(%s)\n",
16361 Pmode == DImode ? "dla" : "la", reg_names[12],
16362 cfun->machine->frame.ra_fp_offset,
16363 reg_names[STACK_POINTER_REGNUM]);
16365 if (!TARGET_NEWABI)
16367 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n",
16368 TARGET_64BIT ? "dsubu" : "subu",
16369 reg_names[STACK_POINTER_REGNUM],
16370 reg_names[STACK_POINTER_REGNUM],
16371 Pmode == DImode ? 16 : 8);
16373 if (TARGET_LONG_CALLS)
16374 fprintf (file, "\tjalr\t%s\n", reg_names[3]);
16376 fprintf (file, "\tjal\t_mcount\n");
16377 mips_pop_asm_switch (&mips_noat);
16378 /* _mcount treats $2 as the static chain register. */
16379 if (cfun->static_chain_decl != NULL)
16380 fprintf (file, "\tmove\t%s,%s\n", reg_names[STATIC_CHAIN_REGNUM],
16384 /* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default
16385 behaviour of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even
16386 when TARGET_LOONGSON_VECTORS is true. */
16388 static unsigned HOST_WIDE_INT
16389 mips_shift_truncation_mask (enum machine_mode mode)
16391 if (TARGET_LOONGSON_VECTORS && VECTOR_MODE_P (mode))
16394 return GET_MODE_BITSIZE (mode) - 1;
16398 /* Initialize the GCC target structure. */
16399 #undef TARGET_ASM_ALIGNED_HI_OP
16400 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
16401 #undef TARGET_ASM_ALIGNED_SI_OP
16402 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
16403 #undef TARGET_ASM_ALIGNED_DI_OP
16404 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
16406 #undef TARGET_OPTION_OVERRIDE
16407 #define TARGET_OPTION_OVERRIDE mips_option_override
16408 #undef TARGET_OPTION_OPTIMIZATION_TABLE
16409 #define TARGET_OPTION_OPTIMIZATION_TABLE mips_option_optimization_table
16411 #undef TARGET_LEGITIMIZE_ADDRESS
16412 #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
16414 #undef TARGET_ASM_FUNCTION_PROLOGUE
16415 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
16416 #undef TARGET_ASM_FUNCTION_EPILOGUE
16417 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
16418 #undef TARGET_ASM_SELECT_RTX_SECTION
16419 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
16420 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
16421 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
16423 #undef TARGET_SCHED_INIT
16424 #define TARGET_SCHED_INIT mips_sched_init
16425 #undef TARGET_SCHED_REORDER
16426 #define TARGET_SCHED_REORDER mips_sched_reorder
16427 #undef TARGET_SCHED_REORDER2
16428 #define TARGET_SCHED_REORDER2 mips_sched_reorder2
16429 #undef TARGET_SCHED_VARIABLE_ISSUE
16430 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
16431 #undef TARGET_SCHED_ADJUST_COST
16432 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
16433 #undef TARGET_SCHED_ISSUE_RATE
16434 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
16435 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
16436 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
16437 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
16438 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
16439 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
16440 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
16441 mips_multipass_dfa_lookahead
16442 #undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
16443 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
16444 mips_small_register_classes_for_mode_p
16446 #undef TARGET_DEFAULT_TARGET_FLAGS
16447 #define TARGET_DEFAULT_TARGET_FLAGS \
16449 | TARGET_CPU_DEFAULT \
16450 | TARGET_ENDIAN_DEFAULT \
16451 | TARGET_FP_EXCEPTIONS_DEFAULT \
16452 | MASK_CHECK_ZERO_DIV \
16454 #undef TARGET_HANDLE_OPTION
16455 #define TARGET_HANDLE_OPTION mips_handle_option
16457 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
16458 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
16460 #undef TARGET_INSERT_ATTRIBUTES
16461 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
16462 #undef TARGET_MERGE_DECL_ATTRIBUTES
16463 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
16464 #undef TARGET_SET_CURRENT_FUNCTION
16465 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
16467 #undef TARGET_VALID_POINTER_MODE
16468 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
16469 #undef TARGET_REGISTER_MOVE_COST
16470 #define TARGET_REGISTER_MOVE_COST mips_register_move_cost
16471 #undef TARGET_MEMORY_MOVE_COST
16472 #define TARGET_MEMORY_MOVE_COST mips_memory_move_cost
16473 #undef TARGET_RTX_COSTS
16474 #define TARGET_RTX_COSTS mips_rtx_costs
16475 #undef TARGET_ADDRESS_COST
16476 #define TARGET_ADDRESS_COST mips_address_cost
16478 #undef TARGET_IN_SMALL_DATA_P
16479 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
16481 #undef TARGET_MACHINE_DEPENDENT_REORG
16482 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
16484 #undef TARGET_PREFERRED_RELOAD_CLASS
16485 #define TARGET_PREFERRED_RELOAD_CLASS mips_preferred_reload_class
16487 #undef TARGET_ASM_FILE_START
16488 #define TARGET_ASM_FILE_START mips_file_start
16489 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
16490 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
16492 #undef TARGET_INIT_LIBFUNCS
16493 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
16495 #undef TARGET_BUILD_BUILTIN_VA_LIST
16496 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
16497 #undef TARGET_EXPAND_BUILTIN_VA_START
16498 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
16499 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
16500 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
16502 #undef TARGET_PROMOTE_FUNCTION_MODE
16503 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
16504 #undef TARGET_PROMOTE_PROTOTYPES
16505 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
16507 #undef TARGET_FUNCTION_VALUE
16508 #define TARGET_FUNCTION_VALUE mips_function_value
16509 #undef TARGET_LIBCALL_VALUE
16510 #define TARGET_LIBCALL_VALUE mips_libcall_value
16511 #undef TARGET_FUNCTION_VALUE_REGNO_P
16512 #define TARGET_FUNCTION_VALUE_REGNO_P mips_function_value_regno_p
16513 #undef TARGET_RETURN_IN_MEMORY
16514 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
16515 #undef TARGET_RETURN_IN_MSB
16516 #define TARGET_RETURN_IN_MSB mips_return_in_msb
16518 #undef TARGET_ASM_OUTPUT_MI_THUNK
16519 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
16520 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
16521 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
16523 #undef TARGET_PRINT_OPERAND
16524 #define TARGET_PRINT_OPERAND mips_print_operand
16525 #undef TARGET_PRINT_OPERAND_ADDRESS
16526 #define TARGET_PRINT_OPERAND_ADDRESS mips_print_operand_address
16527 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
16528 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mips_print_operand_punct_valid_p
16530 #undef TARGET_SETUP_INCOMING_VARARGS
16531 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
16532 #undef TARGET_STRICT_ARGUMENT_NAMING
16533 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
16534 #undef TARGET_MUST_PASS_IN_STACK
16535 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
16536 #undef TARGET_PASS_BY_REFERENCE
16537 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
16538 #undef TARGET_CALLEE_COPIES
16539 #define TARGET_CALLEE_COPIES mips_callee_copies
16540 #undef TARGET_ARG_PARTIAL_BYTES
16541 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
16542 #undef TARGET_FUNCTION_ARG
16543 #define TARGET_FUNCTION_ARG mips_function_arg
16544 #undef TARGET_FUNCTION_ARG_ADVANCE
16545 #define TARGET_FUNCTION_ARG_ADVANCE mips_function_arg_advance
16546 #undef TARGET_FUNCTION_ARG_BOUNDARY
16547 #define TARGET_FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
16549 #undef TARGET_MODE_REP_EXTENDED
16550 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
16552 #undef TARGET_VECTOR_MODE_SUPPORTED_P
16553 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
16555 #undef TARGET_SCALAR_MODE_SUPPORTED_P
16556 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
16558 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
16559 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE mips_preferred_simd_mode
16561 #undef TARGET_INIT_BUILTINS
16562 #define TARGET_INIT_BUILTINS mips_init_builtins
16563 #undef TARGET_BUILTIN_DECL
16564 #define TARGET_BUILTIN_DECL mips_builtin_decl
16565 #undef TARGET_EXPAND_BUILTIN
16566 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
16568 #undef TARGET_HAVE_TLS
16569 #define TARGET_HAVE_TLS HAVE_AS_TLS
16571 #undef TARGET_CANNOT_FORCE_CONST_MEM
16572 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
16574 #undef TARGET_ENCODE_SECTION_INFO
16575 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
16577 #undef TARGET_ATTRIBUTE_TABLE
16578 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
16579 /* All our function attributes are related to how out-of-line copies should
16580 be compiled or called. They don't in themselves prevent inlining. */
16581 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
16582 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
16584 #undef TARGET_EXTRA_LIVE_ON_ENTRY
16585 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
16587 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
16588 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
16589 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
16590 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
16592 #undef TARGET_COMP_TYPE_ATTRIBUTES
16593 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
16595 #ifdef HAVE_AS_DTPRELWORD
16596 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
16597 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
16599 #undef TARGET_DWARF_REGISTER_SPAN
16600 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
16602 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
16603 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
16605 #undef TARGET_LEGITIMATE_ADDRESS_P
16606 #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p
16608 #undef TARGET_FRAME_POINTER_REQUIRED
16609 #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required
16611 #undef TARGET_CAN_ELIMINATE
16612 #define TARGET_CAN_ELIMINATE mips_can_eliminate
16614 #undef TARGET_CONDITIONAL_REGISTER_USAGE
16615 #define TARGET_CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage
16617 #undef TARGET_TRAMPOLINE_INIT
16618 #define TARGET_TRAMPOLINE_INIT mips_trampoline_init
16620 #undef TARGET_ASM_OUTPUT_SOURCE_FILENAME
16621 #define TARGET_ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
16623 #undef TARGET_SHIFT_TRUNCATION_MASK
16624 #define TARGET_SHIFT_TRUNCATION_MASK mips_shift_truncation_mask
16626 struct gcc_target targetm = TARGET_INITIALIZER;
16628 #include "gt-mips.h"