1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989-2014 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky, lich@inria.inria.fr.
4 Changes by Michael Meissner, meissner@osf.org.
5 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 Brendan Eich, brendan@microunity.com.
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
30 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
38 #include "stringpool.h"
39 #include "stor-layout.h"
48 #include "insn-codes.h"
56 #include "hash-table.h"
59 #include "target-def.h"
60 #include "common/common-target.h"
61 #include "langhooks.h"
62 #include "dominance.h"
68 #include "cfgcleanup.h"
70 #include "basic-block.h"
71 #include "sched-int.h"
72 #include "tree-ssa-alias.h"
73 #include "internal-fn.h"
74 #include "gimple-fold.h"
76 #include "gimple-expr.h"
81 #include "diagnostic.h"
82 #include "target-globals.h"
84 #include "tree-pass.h"
87 #include "plugin-api.h"
93 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
94 #define UNSPEC_ADDRESS_P(X) \
95 (GET_CODE (X) == UNSPEC \
96 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
97 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
99 /* Extract the symbol or label from UNSPEC wrapper X. */
100 #define UNSPEC_ADDRESS(X) \
103 /* Extract the symbol type from UNSPEC wrapper X. */
104 #define UNSPEC_ADDRESS_TYPE(X) \
105 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
107 /* The maximum distance between the top of the stack frame and the
108 value $sp has when we save and restore registers.
110 The value for normal-mode code must be a SMALL_OPERAND and must
111 preserve the maximum stack alignment. We therefore use a value
112 of 0x7ff0 in this case.
114 microMIPS LWM and SWM support 12-bit offsets (from -0x800 to 0x7ff),
115 so we use a maximum of 0x7f0 for TARGET_MICROMIPS.
117 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
118 up to 0x7f8 bytes and can usually save or restore all the registers
119 that we need to save or restore. (Note that we can only use these
120 instructions for o32, for which the stack alignment is 8 bytes.)
122 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
123 RESTORE are not available. We can then use unextended instructions
124 to save and restore registers, and to allocate and deallocate the top
125 part of the frame. */
126 #define MIPS_MAX_FIRST_STACK_STEP \
127 (!TARGET_COMPRESSION ? 0x7ff0 \
128 : TARGET_MICROMIPS || GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
129 : TARGET_64BIT ? 0x100 : 0x400)
131 /* True if INSN is a mips.md pattern or asm statement. */
132 /* ??? This test exists through the compiler, perhaps it should be
134 #define USEFUL_INSN_P(INSN) \
135 (NONDEBUG_INSN_P (INSN) \
136 && GET_CODE (PATTERN (INSN)) != USE \
137 && GET_CODE (PATTERN (INSN)) != CLOBBER)
139 /* If INSN is a delayed branch sequence, return the first instruction
140 in the sequence, otherwise return INSN itself. */
141 #define SEQ_BEGIN(INSN) \
142 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
143 ? as_a <rtx_insn *> (XVECEXP (PATTERN (INSN), 0, 0)) \
146 /* Likewise for the last instruction in a delayed branch sequence. */
147 #define SEQ_END(INSN) \
148 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
149 ? as_a <rtx_insn *> (XVECEXP (PATTERN (INSN), \
151 XVECLEN (PATTERN (INSN), 0) - 1)) \
154 /* Execute the following loop body with SUBINSN set to each instruction
155 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
156 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
157 for ((SUBINSN) = SEQ_BEGIN (INSN); \
158 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
159 (SUBINSN) = NEXT_INSN (SUBINSN))
161 /* True if bit BIT is set in VALUE. */
162 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
164 /* Return the opcode for a ptr_mode load of the form:
166 l[wd] DEST, OFFSET(BASE). */
167 #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \
168 (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \
173 /* Return the opcode to move register SRC into register DEST. */
174 #define MIPS_MOVE(DEST, SRC) \
175 ((TARGET_64BIT ? 0x2d : 0x21) \
179 /* Return the opcode for:
182 #define MIPS_LUI(DEST, VALUE) \
183 ((0xf << 26) | ((DEST) << 16) | (VALUE))
185 /* Return the opcode to jump to register DEST. */
186 #define MIPS_JR(DEST) \
187 (((DEST) << 21) | 0x8)
189 /* Return the opcode for:
191 bal . + (1 + OFFSET) * 4. */
192 #define MIPS_BAL(OFFSET) \
193 ((0x1 << 26) | (0x11 << 16) | (OFFSET))
195 /* Return the usual opcode for a nop. */
198 /* Classifies an address.
201 A natural register + offset address. The register satisfies
202 mips_valid_base_register_p and the offset is a const_arith_operand.
205 A LO_SUM rtx. The first operand is a valid base register and
206 the second operand is a symbolic address.
209 A signed 16-bit constant address.
212 A constant symbolic address. */
213 enum mips_address_type {
220 /* Macros to create an enumeration identifier for a function prototype. */
221 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
222 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
223 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
224 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
226 /* Classifies the prototype of a built-in function. */
227 enum mips_function_type {
228 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
229 #include "config/mips/mips-ftypes.def"
230 #undef DEF_MIPS_FTYPE
234 /* Specifies how a built-in function should be converted into rtl. */
235 enum mips_builtin_type {
236 /* The function corresponds directly to an .md pattern. The return
237 value is mapped to operand 0 and the arguments are mapped to
238 operands 1 and above. */
241 /* The function corresponds directly to an .md pattern. There is no return
242 value and the arguments are mapped to operands 0 and above. */
243 MIPS_BUILTIN_DIRECT_NO_TARGET,
245 /* The function corresponds to a comparison instruction followed by
246 a mips_cond_move_tf_ps pattern. The first two arguments are the
247 values to compare and the second two arguments are the vector
248 operands for the movt.ps or movf.ps instruction (in assembly order). */
252 /* The function corresponds to a V2SF comparison instruction. Operand 0
253 of this instruction is the result of the comparison, which has mode
254 CCV2 or CCV4. The function arguments are mapped to operands 1 and
255 above. The function's return value is an SImode boolean that is
256 true under the following conditions:
258 MIPS_BUILTIN_CMP_ANY: one of the registers is true
259 MIPS_BUILTIN_CMP_ALL: all of the registers are true
260 MIPS_BUILTIN_CMP_LOWER: the first register is true
261 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
262 MIPS_BUILTIN_CMP_ANY,
263 MIPS_BUILTIN_CMP_ALL,
264 MIPS_BUILTIN_CMP_UPPER,
265 MIPS_BUILTIN_CMP_LOWER,
267 /* As above, but the instruction only sets a single $fcc register. */
268 MIPS_BUILTIN_CMP_SINGLE,
270 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
271 MIPS_BUILTIN_BPOSGE32
274 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
275 #define MIPS_FP_CONDITIONS(MACRO) \
293 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
294 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
295 enum mips_fp_condition {
296 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
298 #undef DECLARE_MIPS_COND
300 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
301 #define STRINGIFY(X) #X
302 static const char *const mips_fp_conditions[] = {
303 MIPS_FP_CONDITIONS (STRINGIFY)
307 /* A class used to control a comdat-style stub that we output in each
308 translation unit that needs it. */
309 class mips_one_only_stub {
311 virtual ~mips_one_only_stub () {}
313 /* Return the name of the stub. */
314 virtual const char *get_name () = 0;
316 /* Output the body of the function to asm_out_file. */
317 virtual void output_body () = 0;
320 /* Tuning information that is automatically derived from other sources
321 (such as the scheduler). */
323 /* The architecture and tuning settings that this structure describes. */
327 /* True if this structure describes MIPS16 settings. */
330 /* True if the structure has been initialized. */
333 /* True if "MULT $0, $0" is preferable to "MTLO $0; MTHI $0"
334 when optimizing for speed. */
335 bool fast_mult_zero_zero_p;
338 /* Information about a function's frame layout. */
339 struct GTY(()) mips_frame_info {
340 /* The size of the frame in bytes. */
341 HOST_WIDE_INT total_size;
343 /* The number of bytes allocated to variables. */
344 HOST_WIDE_INT var_size;
346 /* The number of bytes allocated to outgoing function arguments. */
347 HOST_WIDE_INT args_size;
349 /* The number of bytes allocated to the .cprestore slot, or 0 if there
351 HOST_WIDE_INT cprestore_size;
353 /* Bit X is set if the function saves or restores GPR X. */
356 /* Likewise FPR X. */
359 /* Likewise doubleword accumulator X ($acX). */
360 unsigned int acc_mask;
362 /* The number of GPRs, FPRs, doubleword accumulators and COP0
366 unsigned int num_acc;
367 unsigned int num_cop0_regs;
369 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
370 save slots from the top of the frame, or zero if no such slots are
372 HOST_WIDE_INT gp_save_offset;
373 HOST_WIDE_INT fp_save_offset;
374 HOST_WIDE_INT acc_save_offset;
375 HOST_WIDE_INT cop0_save_offset;
377 /* Likewise, but giving offsets from the bottom of the frame. */
378 HOST_WIDE_INT gp_sp_offset;
379 HOST_WIDE_INT fp_sp_offset;
380 HOST_WIDE_INT acc_sp_offset;
381 HOST_WIDE_INT cop0_sp_offset;
383 /* Similar, but the value passed to _mcount. */
384 HOST_WIDE_INT ra_fp_offset;
386 /* The offset of arg_pointer_rtx from the bottom of the frame. */
387 HOST_WIDE_INT arg_pointer_offset;
389 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
390 HOST_WIDE_INT hard_frame_pointer_offset;
393 struct GTY(()) machine_function {
394 /* The next floating-point condition-code register to allocate
395 for ISA_HAS_8CC targets, relative to ST_REG_FIRST. */
396 unsigned int next_fcc;
398 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
399 rtx mips16_gp_pseudo_rtx;
401 /* The number of extra stack bytes taken up by register varargs.
402 This area is allocated by the callee at the very top of the frame. */
405 /* The current frame information, calculated by mips_compute_frame_info. */
406 struct mips_frame_info frame;
408 /* The register to use as the function's global pointer, or INVALID_REGNUM
409 if the function doesn't need one. */
410 unsigned int global_pointer;
412 /* How many instructions it takes to load a label into $AT, or 0 if
413 this property hasn't yet been calculated. */
414 unsigned int load_label_num_insns;
416 /* True if mips_adjust_insn_length should ignore an instruction's
418 bool ignore_hazard_length_p;
420 /* True if the whole function is suitable for .set noreorder and
422 bool all_noreorder_p;
424 /* True if the function has "inflexible" and "flexible" references
425 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
426 and mips_cfun_has_flexible_gp_ref_p for details. */
427 bool has_inflexible_gp_insn_p;
428 bool has_flexible_gp_insn_p;
430 /* True if the function's prologue must load the global pointer
431 value into pic_offset_table_rtx and store the same value in
432 the function's cprestore slot (if any). Even if this value
433 is currently false, we may decide to set it to true later;
434 see mips_must_initialize_gp_p () for details. */
435 bool must_initialize_gp_p;
437 /* True if the current function must restore $gp after any potential
438 clobber. This value is only meaningful during the first post-epilogue
439 split_insns pass; see mips_must_initialize_gp_p () for details. */
440 bool must_restore_gp_when_clobbered_p;
442 /* True if this is an interrupt handler. */
443 bool interrupt_handler_p;
445 /* True if this is an interrupt handler that uses shadow registers. */
446 bool use_shadow_register_set_p;
448 /* True if this is an interrupt handler that should keep interrupts
450 bool keep_interrupts_masked_p;
452 /* True if this is an interrupt handler that should use DERET
454 bool use_debug_exception_return_p;
457 /* Information about a single argument. */
458 struct mips_arg_info {
459 /* True if the argument is passed in a floating-point register, or
460 would have been if we hadn't run out of registers. */
463 /* The number of words passed in registers, rounded up. */
464 unsigned int reg_words;
466 /* For EABI, the offset of the first register from GP_ARG_FIRST or
467 FP_ARG_FIRST. For other ABIs, the offset of the first register from
468 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
469 comment for details).
471 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
473 unsigned int reg_offset;
475 /* The number of words that must be passed on the stack, rounded up. */
476 unsigned int stack_words;
478 /* The offset from the start of the stack overflow area of the argument's
479 first stack word. Only meaningful when STACK_WORDS is nonzero. */
480 unsigned int stack_offset;
483 /* Information about an address described by mips_address_type.
489 REG is the base register and OFFSET is the constant offset.
492 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
493 is the type of symbol it references.
496 SYMBOL_TYPE is the type of symbol that the address references. */
497 struct mips_address_info {
498 enum mips_address_type type;
501 enum mips_symbol_type symbol_type;
504 /* One stage in a constant building sequence. These sequences have
508 A = A CODE[1] VALUE[1]
509 A = A CODE[2] VALUE[2]
512 where A is an accumulator, each CODE[i] is a binary rtl operation
513 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
514 struct mips_integer_op {
516 unsigned HOST_WIDE_INT value;
519 /* The largest number of operations needed to load an integer constant.
520 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
521 When the lowest bit is clear, we can try, but reject a sequence with
522 an extra SLL at the end. */
523 #define MIPS_MAX_INTEGER_OPS 7
525 /* Information about a MIPS16e SAVE or RESTORE instruction. */
526 struct mips16e_save_restore_info {
527 /* The number of argument registers saved by a SAVE instruction.
528 0 for RESTORE instructions. */
531 /* Bit X is set if the instruction saves or restores GPR X. */
534 /* The total number of bytes to allocate. */
538 /* Costs of various operations on the different architectures. */
540 struct mips_rtx_cost_data
542 unsigned short fp_add;
543 unsigned short fp_mult_sf;
544 unsigned short fp_mult_df;
545 unsigned short fp_div_sf;
546 unsigned short fp_div_df;
547 unsigned short int_mult_si;
548 unsigned short int_mult_di;
549 unsigned short int_div_si;
550 unsigned short int_div_di;
551 unsigned short branch_cost;
552 unsigned short memory_latency;
555 /* Global variables for machine-dependent things. */
557 /* The -G setting, or the configuration's default small-data limit if
558 no -G option is given. */
559 static unsigned int mips_small_data_threshold;
561 /* The number of file directives written by mips_output_filename. */
562 int num_source_filenames;
564 /* The name that appeared in the last .file directive written by
565 mips_output_filename, or "" if mips_output_filename hasn't
566 written anything yet. */
567 const char *current_function_file = "";
569 /* Arrays that map GCC register numbers to debugger register numbers. */
570 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
571 int mips_dwarf_regno[FIRST_PSEUDO_REGISTER];
573 /* Information about the current function's epilogue, used only while
576 /* A list of queued REG_CFA_RESTORE notes. */
579 /* The CFA is currently defined as CFA_REG + CFA_OFFSET. */
581 HOST_WIDE_INT cfa_offset;
583 /* The offset of the CFA from the stack pointer while restoring
585 HOST_WIDE_INT cfa_restore_sp_offset;
588 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
589 struct mips_asm_switch mips_noreorder = { "reorder", 0 };
590 struct mips_asm_switch mips_nomacro = { "macro", 0 };
591 struct mips_asm_switch mips_noat = { "at", 0 };
593 /* True if we're writing out a branch-likely instruction rather than a
595 static bool mips_branch_likely;
597 /* The current instruction-set architecture. */
598 enum processor mips_arch;
599 const struct mips_cpu_info *mips_arch_info;
601 /* The processor that we should tune the code for. */
602 enum processor mips_tune;
603 const struct mips_cpu_info *mips_tune_info;
605 /* The ISA level associated with mips_arch. */
608 /* The ISA revision level. This is 0 for MIPS I to V and N for
612 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
613 static const struct mips_cpu_info *mips_isa_option_info;
615 /* Which cost information to use. */
616 static const struct mips_rtx_cost_data *mips_cost;
618 /* The ambient target flags, excluding MASK_MIPS16. */
619 static int mips_base_target_flags;
621 /* The default compression mode. */
622 unsigned int mips_base_compression_flags;
624 /* The ambient values of other global variables. */
625 static int mips_base_schedule_insns; /* flag_schedule_insns */
626 static int mips_base_reorder_blocks_and_partition; /* flag_reorder... */
627 static int mips_base_move_loop_invariants; /* flag_move_loop_invariants */
628 static int mips_base_align_loops; /* align_loops */
629 static int mips_base_align_jumps; /* align_jumps */
630 static int mips_base_align_functions; /* align_functions */
632 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
633 bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
635 /* Index C is true if character C is a valid PRINT_OPERAND punctation
637 static bool mips_print_operand_punct[256];
639 static GTY (()) int mips_output_filename_first_time = 1;
641 /* mips_split_p[X] is true if symbols of type X can be split by
642 mips_split_symbol. */
643 bool mips_split_p[NUM_SYMBOL_TYPES];
645 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
646 can be split by mips_split_symbol. */
647 bool mips_split_hi_p[NUM_SYMBOL_TYPES];
649 /* mips_use_pcrel_pool_p[X] is true if symbols of type X should be
650 forced into a PC-relative constant pool. */
651 bool mips_use_pcrel_pool_p[NUM_SYMBOL_TYPES];
653 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
654 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
655 if they are matched by a special .md file pattern. */
656 const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
658 /* Likewise for HIGHs. */
659 const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
661 /* Target state for MIPS16. */
662 struct target_globals *mips16_globals;
664 /* Cached value of can_issue_more. This is cached in mips_variable_issue hook
665 and returned from mips_sched_reorder2. */
666 static int cached_can_issue_more;
668 /* The stubs for various MIPS16 support functions, if used. */
669 static mips_one_only_stub *mips16_rdhwr_stub;
670 static mips_one_only_stub *mips16_get_fcsr_stub;
671 static mips_one_only_stub *mips16_set_fcsr_stub;
673 /* Index R is the smallest register class that contains register R. */
674 const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = {
675 LEA_REGS, LEA_REGS, M16_STORE_REGS, V1_REG,
676 M16_STORE_REGS, M16_STORE_REGS, M16_STORE_REGS, M16_STORE_REGS,
677 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
678 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
679 M16_REGS, M16_STORE_REGS, LEA_REGS, LEA_REGS,
680 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
681 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
682 LEA_REGS, M16_SP_REGS, LEA_REGS, LEA_REGS,
684 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
685 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
686 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
687 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
688 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
689 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
690 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
691 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
692 MD0_REG, MD1_REG, NO_REGS, ST_REGS,
693 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
694 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
695 NO_REGS, FRAME_REGS, FRAME_REGS, NO_REGS,
696 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
697 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
698 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
699 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
700 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
701 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
702 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
703 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
704 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
705 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
706 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
707 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
708 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
709 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
710 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
711 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
712 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
713 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
714 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
715 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
716 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
717 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
718 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
719 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
720 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
721 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
722 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
725 /* The value of TARGET_ATTRIBUTE_TABLE. */
726 static const struct attribute_spec mips_attribute_table[] = {
727 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
729 { "long_call", 0, 0, false, true, true, NULL, false },
730 { "far", 0, 0, false, true, true, NULL, false },
731 { "near", 0, 0, false, true, true, NULL, false },
732 /* We would really like to treat "mips16" and "nomips16" as type
733 attributes, but GCC doesn't provide the hooks we need to support
734 the right conversion rules. As declaration attributes, they affect
735 code generation but don't carry other semantics. */
736 { "mips16", 0, 0, true, false, false, NULL, false },
737 { "nomips16", 0, 0, true, false, false, NULL, false },
738 { "micromips", 0, 0, true, false, false, NULL, false },
739 { "nomicromips", 0, 0, true, false, false, NULL, false },
740 { "nocompression", 0, 0, true, false, false, NULL, false },
741 /* Allow functions to be specified as interrupt handlers */
742 { "interrupt", 0, 0, false, true, true, NULL, false },
743 { "use_shadow_register_set", 0, 0, false, true, true, NULL, false },
744 { "keep_interrupts_masked", 0, 0, false, true, true, NULL, false },
745 { "use_debug_exception_return", 0, 0, false, true, true, NULL, false },
746 { NULL, 0, 0, false, false, false, NULL, false }
749 /* A table describing all the processors GCC knows about; see
750 mips-cpus.def for details. */
751 static const struct mips_cpu_info mips_cpu_info_table[] = {
752 #define MIPS_CPU(NAME, CPU, ISA, FLAGS) \
753 { NAME, CPU, ISA, FLAGS },
754 #include "mips-cpus.def"
758 /* Default costs. If these are used for a processor we should look
759 up the actual costs. */
760 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
761 COSTS_N_INSNS (7), /* fp_mult_sf */ \
762 COSTS_N_INSNS (8), /* fp_mult_df */ \
763 COSTS_N_INSNS (23), /* fp_div_sf */ \
764 COSTS_N_INSNS (36), /* fp_div_df */ \
765 COSTS_N_INSNS (10), /* int_mult_si */ \
766 COSTS_N_INSNS (10), /* int_mult_di */ \
767 COSTS_N_INSNS (69), /* int_div_si */ \
768 COSTS_N_INSNS (69), /* int_div_di */ \
769 2, /* branch_cost */ \
770 4 /* memory_latency */
772 /* Floating-point costs for processors without an FPU. Just assume that
773 all floating-point libcalls are very expensive. */
774 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
775 COSTS_N_INSNS (256), /* fp_mult_sf */ \
776 COSTS_N_INSNS (256), /* fp_mult_df */ \
777 COSTS_N_INSNS (256), /* fp_div_sf */ \
778 COSTS_N_INSNS (256) /* fp_div_df */
780 /* Costs to use when optimizing for size. */
781 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size = {
782 COSTS_N_INSNS (1), /* fp_add */
783 COSTS_N_INSNS (1), /* fp_mult_sf */
784 COSTS_N_INSNS (1), /* fp_mult_df */
785 COSTS_N_INSNS (1), /* fp_div_sf */
786 COSTS_N_INSNS (1), /* fp_div_df */
787 COSTS_N_INSNS (1), /* int_mult_si */
788 COSTS_N_INSNS (1), /* int_mult_di */
789 COSTS_N_INSNS (1), /* int_div_si */
790 COSTS_N_INSNS (1), /* int_div_di */
792 4 /* memory_latency */
795 /* Costs to use when optimizing for speed, indexed by processor. */
796 static const struct mips_rtx_cost_data
797 mips_rtx_cost_data[NUM_PROCESSOR_VALUES] = {
799 COSTS_N_INSNS (2), /* fp_add */
800 COSTS_N_INSNS (4), /* fp_mult_sf */
801 COSTS_N_INSNS (5), /* fp_mult_df */
802 COSTS_N_INSNS (12), /* fp_div_sf */
803 COSTS_N_INSNS (19), /* fp_div_df */
804 COSTS_N_INSNS (12), /* int_mult_si */
805 COSTS_N_INSNS (12), /* int_mult_di */
806 COSTS_N_INSNS (35), /* int_div_si */
807 COSTS_N_INSNS (35), /* int_div_di */
809 4 /* memory_latency */
813 COSTS_N_INSNS (6), /* int_mult_si */
814 COSTS_N_INSNS (6), /* int_mult_di */
815 COSTS_N_INSNS (36), /* int_div_si */
816 COSTS_N_INSNS (36), /* int_div_di */
818 4 /* memory_latency */
822 COSTS_N_INSNS (36), /* int_mult_si */
823 COSTS_N_INSNS (36), /* int_mult_di */
824 COSTS_N_INSNS (37), /* int_div_si */
825 COSTS_N_INSNS (37), /* int_div_di */
827 4 /* memory_latency */
831 COSTS_N_INSNS (4), /* int_mult_si */
832 COSTS_N_INSNS (11), /* int_mult_di */
833 COSTS_N_INSNS (36), /* int_div_si */
834 COSTS_N_INSNS (68), /* int_div_di */
836 4 /* memory_latency */
839 COSTS_N_INSNS (4), /* fp_add */
840 COSTS_N_INSNS (4), /* fp_mult_sf */
841 COSTS_N_INSNS (5), /* fp_mult_df */
842 COSTS_N_INSNS (17), /* fp_div_sf */
843 COSTS_N_INSNS (32), /* fp_div_df */
844 COSTS_N_INSNS (4), /* int_mult_si */
845 COSTS_N_INSNS (11), /* int_mult_di */
846 COSTS_N_INSNS (36), /* int_div_si */
847 COSTS_N_INSNS (68), /* int_div_di */
849 4 /* memory_latency */
852 COSTS_N_INSNS (4), /* fp_add */
853 COSTS_N_INSNS (4), /* fp_mult_sf */
854 COSTS_N_INSNS (5), /* fp_mult_df */
855 COSTS_N_INSNS (17), /* fp_div_sf */
856 COSTS_N_INSNS (32), /* fp_div_df */
857 COSTS_N_INSNS (4), /* int_mult_si */
858 COSTS_N_INSNS (7), /* int_mult_di */
859 COSTS_N_INSNS (42), /* int_div_si */
860 COSTS_N_INSNS (72), /* int_div_di */
862 4 /* memory_latency */
866 COSTS_N_INSNS (5), /* int_mult_si */
867 COSTS_N_INSNS (5), /* int_mult_di */
868 COSTS_N_INSNS (41), /* int_div_si */
869 COSTS_N_INSNS (41), /* int_div_di */
871 4 /* memory_latency */
874 COSTS_N_INSNS (8), /* fp_add */
875 COSTS_N_INSNS (8), /* fp_mult_sf */
876 COSTS_N_INSNS (10), /* fp_mult_df */
877 COSTS_N_INSNS (34), /* fp_div_sf */
878 COSTS_N_INSNS (64), /* fp_div_df */
879 COSTS_N_INSNS (5), /* int_mult_si */
880 COSTS_N_INSNS (5), /* int_mult_di */
881 COSTS_N_INSNS (41), /* int_div_si */
882 COSTS_N_INSNS (41), /* int_div_di */
884 4 /* memory_latency */
887 COSTS_N_INSNS (4), /* fp_add */
888 COSTS_N_INSNS (4), /* fp_mult_sf */
889 COSTS_N_INSNS (5), /* fp_mult_df */
890 COSTS_N_INSNS (17), /* fp_div_sf */
891 COSTS_N_INSNS (32), /* fp_div_df */
892 COSTS_N_INSNS (5), /* int_mult_si */
893 COSTS_N_INSNS (5), /* int_mult_di */
894 COSTS_N_INSNS (41), /* int_div_si */
895 COSTS_N_INSNS (41), /* int_div_di */
897 4 /* memory_latency */
901 COSTS_N_INSNS (5), /* int_mult_si */
902 COSTS_N_INSNS (5), /* int_mult_di */
903 COSTS_N_INSNS (41), /* int_div_si */
904 COSTS_N_INSNS (41), /* int_div_di */
906 4 /* memory_latency */
909 COSTS_N_INSNS (8), /* fp_add */
910 COSTS_N_INSNS (8), /* fp_mult_sf */
911 COSTS_N_INSNS (10), /* fp_mult_df */
912 COSTS_N_INSNS (34), /* fp_div_sf */
913 COSTS_N_INSNS (64), /* fp_div_df */
914 COSTS_N_INSNS (5), /* int_mult_si */
915 COSTS_N_INSNS (5), /* int_mult_di */
916 COSTS_N_INSNS (41), /* int_div_si */
917 COSTS_N_INSNS (41), /* int_div_di */
919 4 /* memory_latency */
922 COSTS_N_INSNS (4), /* fp_add */
923 COSTS_N_INSNS (4), /* fp_mult_sf */
924 COSTS_N_INSNS (5), /* fp_mult_df */
925 COSTS_N_INSNS (17), /* fp_div_sf */
926 COSTS_N_INSNS (32), /* fp_div_df */
927 COSTS_N_INSNS (5), /* int_mult_si */
928 COSTS_N_INSNS (5), /* int_mult_di */
929 COSTS_N_INSNS (41), /* int_div_si */
930 COSTS_N_INSNS (41), /* int_div_di */
932 4 /* memory_latency */
935 COSTS_N_INSNS (6), /* fp_add */
936 COSTS_N_INSNS (6), /* fp_mult_sf */
937 COSTS_N_INSNS (7), /* fp_mult_df */
938 COSTS_N_INSNS (25), /* fp_div_sf */
939 COSTS_N_INSNS (48), /* fp_div_df */
940 COSTS_N_INSNS (5), /* int_mult_si */
941 COSTS_N_INSNS (5), /* int_mult_di */
942 COSTS_N_INSNS (41), /* int_div_si */
943 COSTS_N_INSNS (41), /* int_div_di */
945 4 /* memory_latency */
962 COSTS_N_INSNS (5), /* int_mult_si */
963 COSTS_N_INSNS (5), /* int_mult_di */
964 COSTS_N_INSNS (72), /* int_div_si */
965 COSTS_N_INSNS (72), /* int_div_di */
967 4 /* memory_latency */
972 COSTS_N_INSNS (6), /* int_mult_si */
973 COSTS_N_INSNS (6), /* int_mult_di */
974 COSTS_N_INSNS (18), /* int_div_si */
975 COSTS_N_INSNS (35), /* int_div_di */
977 4 /* memory_latency */
981 COSTS_N_INSNS (6), /* fp_add */
982 COSTS_N_INSNS (6), /* fp_mult_sf */
983 COSTS_N_INSNS (7), /* fp_mult_df */
984 COSTS_N_INSNS (25), /* fp_div_sf */
985 COSTS_N_INSNS (48), /* fp_div_df */
986 COSTS_N_INSNS (6), /* int_mult_si */
987 COSTS_N_INSNS (6), /* int_mult_di */
988 COSTS_N_INSNS (18), /* int_div_si */
989 COSTS_N_INSNS (35), /* int_div_di */
991 4 /* memory_latency */
994 COSTS_N_INSNS (2), /* fp_add */
995 COSTS_N_INSNS (4), /* fp_mult_sf */
996 COSTS_N_INSNS (5), /* fp_mult_df */
997 COSTS_N_INSNS (12), /* fp_div_sf */
998 COSTS_N_INSNS (19), /* fp_div_df */
999 COSTS_N_INSNS (2), /* int_mult_si */
1000 COSTS_N_INSNS (2), /* int_mult_di */
1001 COSTS_N_INSNS (35), /* int_div_si */
1002 COSTS_N_INSNS (35), /* int_div_di */
1003 1, /* branch_cost */
1004 4 /* memory_latency */
1007 COSTS_N_INSNS (3), /* fp_add */
1008 COSTS_N_INSNS (5), /* fp_mult_sf */
1009 COSTS_N_INSNS (6), /* fp_mult_df */
1010 COSTS_N_INSNS (15), /* fp_div_sf */
1011 COSTS_N_INSNS (16), /* fp_div_df */
1012 COSTS_N_INSNS (17), /* int_mult_si */
1013 COSTS_N_INSNS (17), /* int_mult_di */
1014 COSTS_N_INSNS (38), /* int_div_si */
1015 COSTS_N_INSNS (38), /* int_div_di */
1016 2, /* branch_cost */
1017 6 /* memory_latency */
1020 COSTS_N_INSNS (6), /* fp_add */
1021 COSTS_N_INSNS (7), /* fp_mult_sf */
1022 COSTS_N_INSNS (8), /* fp_mult_df */
1023 COSTS_N_INSNS (23), /* fp_div_sf */
1024 COSTS_N_INSNS (36), /* fp_div_df */
1025 COSTS_N_INSNS (10), /* int_mult_si */
1026 COSTS_N_INSNS (10), /* int_mult_di */
1027 COSTS_N_INSNS (69), /* int_div_si */
1028 COSTS_N_INSNS (69), /* int_div_di */
1029 2, /* branch_cost */
1030 6 /* memory_latency */
1042 /* The only costs that appear to be updated here are
1043 integer multiplication. */
1045 COSTS_N_INSNS (4), /* int_mult_si */
1046 COSTS_N_INSNS (6), /* int_mult_di */
1047 COSTS_N_INSNS (69), /* int_div_si */
1048 COSTS_N_INSNS (69), /* int_div_di */
1049 1, /* branch_cost */
1050 4 /* memory_latency */
1065 COSTS_N_INSNS (6), /* fp_add */
1066 COSTS_N_INSNS (4), /* fp_mult_sf */
1067 COSTS_N_INSNS (5), /* fp_mult_df */
1068 COSTS_N_INSNS (23), /* fp_div_sf */
1069 COSTS_N_INSNS (36), /* fp_div_df */
1070 COSTS_N_INSNS (5), /* int_mult_si */
1071 COSTS_N_INSNS (5), /* int_mult_di */
1072 COSTS_N_INSNS (36), /* int_div_si */
1073 COSTS_N_INSNS (36), /* int_div_di */
1074 1, /* branch_cost */
1075 4 /* memory_latency */
1078 COSTS_N_INSNS (6), /* fp_add */
1079 COSTS_N_INSNS (5), /* fp_mult_sf */
1080 COSTS_N_INSNS (6), /* fp_mult_df */
1081 COSTS_N_INSNS (30), /* fp_div_sf */
1082 COSTS_N_INSNS (59), /* fp_div_df */
1083 COSTS_N_INSNS (3), /* int_mult_si */
1084 COSTS_N_INSNS (4), /* int_mult_di */
1085 COSTS_N_INSNS (42), /* int_div_si */
1086 COSTS_N_INSNS (74), /* int_div_di */
1087 1, /* branch_cost */
1088 4 /* memory_latency */
1091 COSTS_N_INSNS (6), /* fp_add */
1092 COSTS_N_INSNS (5), /* fp_mult_sf */
1093 COSTS_N_INSNS (6), /* fp_mult_df */
1094 COSTS_N_INSNS (30), /* fp_div_sf */
1095 COSTS_N_INSNS (59), /* fp_div_df */
1096 COSTS_N_INSNS (5), /* int_mult_si */
1097 COSTS_N_INSNS (9), /* int_mult_di */
1098 COSTS_N_INSNS (42), /* int_div_si */
1099 COSTS_N_INSNS (74), /* int_div_di */
1100 1, /* branch_cost */
1101 4 /* memory_latency */
1104 COSTS_N_INSNS (4), /* fp_add */
1105 COSTS_N_INSNS (4), /* fp_mult_sf */
1106 COSTS_N_INSNS (256), /* fp_mult_df */
1107 COSTS_N_INSNS (8), /* fp_div_sf */
1108 COSTS_N_INSNS (256), /* fp_div_df */
1109 COSTS_N_INSNS (4), /* int_mult_si */
1110 COSTS_N_INSNS (256), /* int_mult_di */
1111 COSTS_N_INSNS (37), /* int_div_si */
1112 COSTS_N_INSNS (256), /* int_div_di */
1113 1, /* branch_cost */
1114 4 /* memory_latency */
1117 /* The only costs that are changed here are
1118 integer multiplication. */
1119 COSTS_N_INSNS (6), /* fp_add */
1120 COSTS_N_INSNS (7), /* fp_mult_sf */
1121 COSTS_N_INSNS (8), /* fp_mult_df */
1122 COSTS_N_INSNS (23), /* fp_div_sf */
1123 COSTS_N_INSNS (36), /* fp_div_df */
1124 COSTS_N_INSNS (5), /* int_mult_si */
1125 COSTS_N_INSNS (9), /* int_mult_di */
1126 COSTS_N_INSNS (69), /* int_div_si */
1127 COSTS_N_INSNS (69), /* int_div_di */
1128 1, /* branch_cost */
1129 4 /* memory_latency */
1135 /* The only costs that are changed here are
1136 integer multiplication. */
1137 COSTS_N_INSNS (6), /* fp_add */
1138 COSTS_N_INSNS (7), /* fp_mult_sf */
1139 COSTS_N_INSNS (8), /* fp_mult_df */
1140 COSTS_N_INSNS (23), /* fp_div_sf */
1141 COSTS_N_INSNS (36), /* fp_div_df */
1142 COSTS_N_INSNS (3), /* int_mult_si */
1143 COSTS_N_INSNS (8), /* int_mult_di */
1144 COSTS_N_INSNS (69), /* int_div_si */
1145 COSTS_N_INSNS (69), /* int_div_di */
1146 1, /* branch_cost */
1147 4 /* memory_latency */
1150 COSTS_N_INSNS (2), /* fp_add */
1151 COSTS_N_INSNS (2), /* fp_mult_sf */
1152 COSTS_N_INSNS (2), /* fp_mult_df */
1153 COSTS_N_INSNS (12), /* fp_div_sf */
1154 COSTS_N_INSNS (19), /* fp_div_df */
1155 COSTS_N_INSNS (5), /* int_mult_si */
1156 COSTS_N_INSNS (9), /* int_mult_di */
1157 COSTS_N_INSNS (34), /* int_div_si */
1158 COSTS_N_INSNS (66), /* int_div_di */
1159 1, /* branch_cost */
1160 4 /* memory_latency */
1163 /* These costs are the same as the SB-1A below. */
1164 COSTS_N_INSNS (4), /* fp_add */
1165 COSTS_N_INSNS (4), /* fp_mult_sf */
1166 COSTS_N_INSNS (4), /* fp_mult_df */
1167 COSTS_N_INSNS (24), /* fp_div_sf */
1168 COSTS_N_INSNS (32), /* fp_div_df */
1169 COSTS_N_INSNS (3), /* int_mult_si */
1170 COSTS_N_INSNS (4), /* int_mult_di */
1171 COSTS_N_INSNS (36), /* int_div_si */
1172 COSTS_N_INSNS (68), /* int_div_di */
1173 1, /* branch_cost */
1174 4 /* memory_latency */
1177 /* These costs are the same as the SB-1 above. */
1178 COSTS_N_INSNS (4), /* fp_add */
1179 COSTS_N_INSNS (4), /* fp_mult_sf */
1180 COSTS_N_INSNS (4), /* fp_mult_df */
1181 COSTS_N_INSNS (24), /* fp_div_sf */
1182 COSTS_N_INSNS (32), /* fp_div_df */
1183 COSTS_N_INSNS (3), /* int_mult_si */
1184 COSTS_N_INSNS (4), /* int_mult_di */
1185 COSTS_N_INSNS (36), /* int_div_si */
1186 COSTS_N_INSNS (68), /* int_div_di */
1187 1, /* branch_cost */
1188 4 /* memory_latency */
1195 COSTS_N_INSNS (8), /* int_mult_si */
1196 COSTS_N_INSNS (8), /* int_mult_di */
1197 COSTS_N_INSNS (72), /* int_div_si */
1198 COSTS_N_INSNS (72), /* int_div_di */
1199 1, /* branch_cost */
1200 4 /* memory_latency */
1203 /* These costs are the same as 5KF above. */
1204 COSTS_N_INSNS (4), /* fp_add */
1205 COSTS_N_INSNS (4), /* fp_mult_sf */
1206 COSTS_N_INSNS (5), /* fp_mult_df */
1207 COSTS_N_INSNS (17), /* fp_div_sf */
1208 COSTS_N_INSNS (32), /* fp_div_df */
1209 COSTS_N_INSNS (4), /* int_mult_si */
1210 COSTS_N_INSNS (11), /* int_mult_di */
1211 COSTS_N_INSNS (36), /* int_div_si */
1212 COSTS_N_INSNS (68), /* int_div_di */
1213 1, /* branch_cost */
1214 4 /* memory_latency */
1217 COSTS_N_INSNS (4), /* fp_add */
1218 COSTS_N_INSNS (5), /* fp_mult_sf */
1219 COSTS_N_INSNS (5), /* fp_mult_df */
1220 COSTS_N_INSNS (17), /* fp_div_sf */
1221 COSTS_N_INSNS (17), /* fp_div_df */
1222 COSTS_N_INSNS (5), /* int_mult_si */
1223 COSTS_N_INSNS (5), /* int_mult_di */
1224 COSTS_N_INSNS (8), /* int_div_si */
1225 COSTS_N_INSNS (8), /* int_div_di */
1226 2, /* branch_cost */
1227 10 /* memory_latency */
1231 static rtx mips_find_pic_call_symbol (rtx_insn *, rtx, bool);
1232 static int mips_register_move_cost (machine_mode, reg_class_t,
1234 static unsigned int mips_function_arg_boundary (machine_mode, const_tree);
1235 static machine_mode mips_get_reg_raw_mode (int regno);
1237 struct mips16_flip_traits : default_hashmap_traits
1239 static hashval_t hash (const char *s) { return htab_hash_string (s); }
1241 equal_keys (const char *a, const char *b)
1243 return !strcmp (a, b);
1247 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1248 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1249 static GTY (()) hash_map<const char *, bool, mips16_flip_traits> *
1252 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1253 mode, false if it should next add an attribute for the opposite mode. */
1254 static GTY(()) bool mips16_flipper;
1256 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1257 for -mflip-mips16. Return true if it should use "mips16" and false if
1258 it should use "nomips16". */
1261 mflip_mips16_use_mips16_p (tree decl)
1264 bool base_is_mips16 = (mips_base_compression_flags & MASK_MIPS16) != 0;
1266 /* Use the opposite of the command-line setting for anonymous decls. */
1267 if (!DECL_NAME (decl))
1268 return !base_is_mips16;
1270 if (!mflip_mips16_htab)
1272 = hash_map<const char *, bool, mips16_flip_traits>::create_ggc (37);
1274 name = IDENTIFIER_POINTER (DECL_NAME (decl));
1277 bool *slot = &mflip_mips16_htab->get_or_insert (name, &existed);
1280 mips16_flipper = !mips16_flipper;
1281 *slot = mips16_flipper ? !base_is_mips16 : base_is_mips16;
1286 /* Predicates to test for presence of "near" and "far"/"long_call"
1287 attributes on the given TYPE. */
1290 mips_near_type_p (const_tree type)
1292 return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL;
1296 mips_far_type_p (const_tree type)
1298 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL
1299 || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL);
1303 /* Check if the interrupt attribute is set for a function. */
1306 mips_interrupt_type_p (tree type)
1308 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type)) != NULL;
1311 /* Check if the attribute to use shadow register set is set for a function. */
1314 mips_use_shadow_register_set_p (tree type)
1316 return lookup_attribute ("use_shadow_register_set",
1317 TYPE_ATTRIBUTES (type)) != NULL;
1320 /* Check if the attribute to keep interrupts masked is set for a function. */
1323 mips_keep_interrupts_masked_p (tree type)
1325 return lookup_attribute ("keep_interrupts_masked",
1326 TYPE_ATTRIBUTES (type)) != NULL;
1329 /* Check if the attribute to use debug exception return is set for
1333 mips_use_debug_exception_return_p (tree type)
1335 return lookup_attribute ("use_debug_exception_return",
1336 TYPE_ATTRIBUTES (type)) != NULL;
1339 /* Return the set of compression modes that are explicitly required
1340 by the attributes in ATTRIBUTES. */
1343 mips_get_compress_on_flags (tree attributes)
1345 unsigned int flags = 0;
1347 if (lookup_attribute ("mips16", attributes) != NULL)
1348 flags |= MASK_MIPS16;
1350 if (lookup_attribute ("micromips", attributes) != NULL)
1351 flags |= MASK_MICROMIPS;
1356 /* Return the set of compression modes that are explicitly forbidden
1357 by the attributes in ATTRIBUTES. */
1360 mips_get_compress_off_flags (tree attributes)
1362 unsigned int flags = 0;
1364 if (lookup_attribute ("nocompression", attributes) != NULL)
1365 flags |= MASK_MIPS16 | MASK_MICROMIPS;
1367 if (lookup_attribute ("nomips16", attributes) != NULL)
1368 flags |= MASK_MIPS16;
1370 if (lookup_attribute ("nomicromips", attributes) != NULL)
1371 flags |= MASK_MICROMIPS;
1376 /* Return the compression mode that should be used for function DECL.
1377 Return the ambient setting if DECL is null. */
1380 mips_get_compress_mode (tree decl)
1382 unsigned int flags, force_on;
1384 flags = mips_base_compression_flags;
1387 /* Nested functions must use the same frame pointer as their
1388 parent and must therefore use the same ISA mode. */
1389 tree parent = decl_function_context (decl);
1392 force_on = mips_get_compress_on_flags (DECL_ATTRIBUTES (decl));
1395 flags &= ~mips_get_compress_off_flags (DECL_ATTRIBUTES (decl));
1400 /* Return the attribute name associated with MASK_MIPS16 and MASK_MICROMIPS
1404 mips_get_compress_on_name (unsigned int flags)
1406 if (flags == MASK_MIPS16)
1411 /* Return the attribute name that forbids MASK_MIPS16 and MASK_MICROMIPS
1415 mips_get_compress_off_name (unsigned int flags)
1417 if (flags == MASK_MIPS16)
1419 if (flags == MASK_MICROMIPS)
1420 return "nomicromips";
1421 return "nocompression";
1424 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1427 mips_comp_type_attributes (const_tree type1, const_tree type2)
1429 /* Disallow mixed near/far attributes. */
1430 if (mips_far_type_p (type1) && mips_near_type_p (type2))
1432 if (mips_near_type_p (type1) && mips_far_type_p (type2))
1437 /* Implement TARGET_INSERT_ATTRIBUTES. */
1440 mips_insert_attributes (tree decl, tree *attributes)
1443 unsigned int compression_flags, nocompression_flags;
1445 /* Check for "mips16" and "nomips16" attributes. */
1446 compression_flags = mips_get_compress_on_flags (*attributes);
1447 nocompression_flags = mips_get_compress_off_flags (*attributes);
1449 if (TREE_CODE (decl) != FUNCTION_DECL)
1451 if (nocompression_flags)
1452 error ("%qs attribute only applies to functions",
1453 mips_get_compress_off_name (nocompression_flags));
1455 if (compression_flags)
1456 error ("%qs attribute only applies to functions",
1457 mips_get_compress_on_name (nocompression_flags));
1461 compression_flags |= mips_get_compress_on_flags (DECL_ATTRIBUTES (decl));
1462 nocompression_flags |=
1463 mips_get_compress_off_flags (DECL_ATTRIBUTES (decl));
1465 if (compression_flags && nocompression_flags)
1466 error ("%qE cannot have both %qs and %qs attributes",
1467 DECL_NAME (decl), mips_get_compress_on_name (compression_flags),
1468 mips_get_compress_off_name (nocompression_flags));
1470 if (compression_flags & MASK_MIPS16
1471 && compression_flags & MASK_MICROMIPS)
1472 error ("%qE cannot have both %qs and %qs attributes",
1473 DECL_NAME (decl), "mips16", "micromips");
1475 if (TARGET_FLIP_MIPS16
1476 && !DECL_ARTIFICIAL (decl)
1477 && compression_flags == 0
1478 && nocompression_flags == 0)
1480 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1481 "mips16" attribute, arbitrarily pick one. We must pick the same
1482 setting for duplicate declarations of a function. */
1483 name = mflip_mips16_use_mips16_p (decl) ? "mips16" : "nomips16";
1484 *attributes = tree_cons (get_identifier (name), NULL, *attributes);
1485 name = "nomicromips";
1486 *attributes = tree_cons (get_identifier (name), NULL, *attributes);
1491 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1494 mips_merge_decl_attributes (tree olddecl, tree newdecl)
1498 diff = (mips_get_compress_on_flags (DECL_ATTRIBUTES (olddecl))
1499 ^ mips_get_compress_on_flags (DECL_ATTRIBUTES (newdecl)));
1501 error ("%qE redeclared with conflicting %qs attributes",
1502 DECL_NAME (newdecl), mips_get_compress_on_name (diff));
1504 diff = (mips_get_compress_off_flags (DECL_ATTRIBUTES (olddecl))
1505 ^ mips_get_compress_off_flags (DECL_ATTRIBUTES (newdecl)));
1507 error ("%qE redeclared with conflicting %qs attributes",
1508 DECL_NAME (newdecl), mips_get_compress_off_name (diff));
1510 return merge_attributes (DECL_ATTRIBUTES (olddecl),
1511 DECL_ATTRIBUTES (newdecl));
1514 /* Implement TARGET_CAN_INLINE_P. */
1517 mips_can_inline_p (tree caller, tree callee)
1519 if (mips_get_compress_mode (callee) != mips_get_compress_mode (caller))
1521 return default_target_can_inline_p (caller, callee);
1524 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1525 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1528 mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr)
1530 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
1532 *base_ptr = XEXP (x, 0);
1533 *offset_ptr = INTVAL (XEXP (x, 1));
1542 static unsigned int mips_build_integer (struct mips_integer_op *,
1543 unsigned HOST_WIDE_INT);
1545 /* A subroutine of mips_build_integer, with the same interface.
1546 Assume that the final action in the sequence should be a left shift. */
1549 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1551 unsigned int i, shift;
1553 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1554 since signed numbers are easier to load than unsigned ones. */
1556 while ((value & 1) == 0)
1557 value /= 2, shift++;
1559 i = mips_build_integer (codes, value);
1560 codes[i].code = ASHIFT;
1561 codes[i].value = shift;
1565 /* As for mips_build_shift, but assume that the final action will be
1566 an IOR or PLUS operation. */
1569 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1571 unsigned HOST_WIDE_INT high;
1574 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1575 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
1577 /* The constant is too complex to load with a simple LUI/ORI pair,
1578 so we want to give the recursive call as many trailing zeros as
1579 possible. In this case, we know bit 16 is set and that the
1580 low 16 bits form a negative number. If we subtract that number
1581 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1582 i = mips_build_integer (codes, CONST_HIGH_PART (value));
1583 codes[i].code = PLUS;
1584 codes[i].value = CONST_LOW_PART (value);
1588 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1589 bits gives a value with at least 17 trailing zeros. */
1590 i = mips_build_integer (codes, high);
1591 codes[i].code = IOR;
1592 codes[i].value = value & 0xffff;
1597 /* Fill CODES with a sequence of rtl operations to load VALUE.
1598 Return the number of operations needed. */
1601 mips_build_integer (struct mips_integer_op *codes,
1602 unsigned HOST_WIDE_INT value)
1604 if (SMALL_OPERAND (value)
1605 || SMALL_OPERAND_UNSIGNED (value)
1606 || LUI_OPERAND (value))
1608 /* The value can be loaded with a single instruction. */
1609 codes[0].code = UNKNOWN;
1610 codes[0].value = value;
1613 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
1615 /* Either the constant is a simple LUI/ORI combination or its
1616 lowest bit is set. We don't want to shift in this case. */
1617 return mips_build_lower (codes, value);
1619 else if ((value & 0xffff) == 0)
1621 /* The constant will need at least three actions. The lowest
1622 16 bits are clear, so the final action will be a shift. */
1623 return mips_build_shift (codes, value);
1627 /* The final action could be a shift, add or inclusive OR.
1628 Rather than use a complex condition to select the best
1629 approach, try both mips_build_shift and mips_build_lower
1630 and pick the one that gives the shortest sequence.
1631 Note that this case is only used once per constant. */
1632 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1633 unsigned int cost, alt_cost;
1635 cost = mips_build_shift (codes, value);
1636 alt_cost = mips_build_lower (alt_codes, value);
1637 if (alt_cost < cost)
1639 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
1646 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
1649 mips_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
1651 return mips_const_insns (x) > 0;
1654 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
1657 mips16_stub_function (const char *name)
1661 x = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
1662 SYMBOL_REF_FLAGS (x) |= (SYMBOL_FLAG_EXTERNAL | SYMBOL_FLAG_FUNCTION);
1666 /* Return a legitimate call address for STUB, given that STUB is a MIPS16
1667 support function. */
1670 mips16_stub_call_address (mips_one_only_stub *stub)
1672 rtx fn = mips16_stub_function (stub->get_name ());
1673 SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_LOCAL;
1674 if (!call_insn_operand (fn, VOIDmode))
1675 fn = force_reg (Pmode, fn);
1679 /* A stub for moving the thread pointer into TLS_GET_TP_REGNUM. */
1681 class mips16_rdhwr_one_only_stub : public mips_one_only_stub
1683 virtual const char *get_name ();
1684 virtual void output_body ();
1688 mips16_rdhwr_one_only_stub::get_name ()
1690 return "__mips16_rdhwr";
1694 mips16_rdhwr_one_only_stub::output_body ()
1696 fprintf (asm_out_file,
1698 "\t.set\tmips32r2\n"
1699 "\t.set\tnoreorder\n"
1705 /* A stub for moving the FCSR into GET_FCSR_REGNUM. */
1706 class mips16_get_fcsr_one_only_stub : public mips_one_only_stub
1708 virtual const char *get_name ();
1709 virtual void output_body ();
1713 mips16_get_fcsr_one_only_stub::get_name ()
1715 return "__mips16_get_fcsr";
1719 mips16_get_fcsr_one_only_stub::output_body ()
1721 fprintf (asm_out_file,
1723 "\tj\t$31\n", reg_names[GET_FCSR_REGNUM]);
1726 /* A stub for moving SET_FCSR_REGNUM into the FCSR. */
1727 class mips16_set_fcsr_one_only_stub : public mips_one_only_stub
1729 virtual const char *get_name ();
1730 virtual void output_body ();
1734 mips16_set_fcsr_one_only_stub::get_name ()
1736 return "__mips16_set_fcsr";
1740 mips16_set_fcsr_one_only_stub::output_body ()
1742 fprintf (asm_out_file,
1744 "\tj\t$31\n", reg_names[SET_FCSR_REGNUM]);
1747 /* Return true if symbols of type TYPE require a GOT access. */
1750 mips_got_symbol_type_p (enum mips_symbol_type type)
1754 case SYMBOL_GOT_PAGE_OFST:
1755 case SYMBOL_GOT_DISP:
1763 /* Return true if X is a thread-local symbol. */
1766 mips_tls_symbol_p (rtx x)
1768 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1771 /* Return true if SYMBOL_REF X is associated with a global symbol
1772 (in the STB_GLOBAL sense). */
1775 mips_global_symbol_p (const_rtx x)
1777 const_tree decl = SYMBOL_REF_DECL (x);
1780 return !SYMBOL_REF_LOCAL_P (x) || SYMBOL_REF_EXTERNAL_P (x);
1782 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1783 or weak symbols. Relocations in the object file will be against
1784 the target symbol, so it's that symbol's binding that matters here. */
1785 return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl));
1788 /* Return true if function X is a libgcc MIPS16 stub function. */
1791 mips16_stub_function_p (const_rtx x)
1793 return (GET_CODE (x) == SYMBOL_REF
1794 && strncmp (XSTR (x, 0), "__mips16_", 9) == 0);
1797 /* Return true if function X is a locally-defined and locally-binding
1801 mips16_local_function_p (const_rtx x)
1803 return (GET_CODE (x) == SYMBOL_REF
1804 && SYMBOL_REF_LOCAL_P (x)
1805 && !SYMBOL_REF_EXTERNAL_P (x)
1806 && (mips_get_compress_mode (SYMBOL_REF_DECL (x)) & MASK_MIPS16));
1809 /* Return true if SYMBOL_REF X binds locally. */
1812 mips_symbol_binds_local_p (const_rtx x)
1814 return (SYMBOL_REF_DECL (x)
1815 ? targetm.binds_local_p (SYMBOL_REF_DECL (x))
1816 : SYMBOL_REF_LOCAL_P (x));
1819 /* Return true if rtx constants of mode MODE should be put into a small
1823 mips_rtx_constant_in_small_data_p (machine_mode mode)
1825 return (!TARGET_EMBEDDED_DATA
1826 && TARGET_LOCAL_SDATA
1827 && GET_MODE_SIZE (mode) <= mips_small_data_threshold);
1830 /* Return true if X should not be moved directly into register $25.
1831 We need this because many versions of GAS will treat "la $25,foo" as
1832 part of a call sequence and so allow a global "foo" to be lazily bound. */
1835 mips_dangerous_for_la25_p (rtx x)
1837 return (!TARGET_EXPLICIT_RELOCS
1839 && GET_CODE (x) == SYMBOL_REF
1840 && mips_global_symbol_p (x));
1843 /* Return true if calls to X might need $25 to be valid on entry. */
1846 mips_use_pic_fn_addr_reg_p (const_rtx x)
1848 if (!TARGET_USE_PIC_FN_ADDR_REG)
1851 /* MIPS16 stub functions are guaranteed not to use $25. */
1852 if (mips16_stub_function_p (x))
1855 if (GET_CODE (x) == SYMBOL_REF)
1857 /* If PLTs and copy relocations are available, the static linker
1858 will make sure that $25 is valid on entry to the target function. */
1859 if (TARGET_ABICALLS_PIC0)
1862 /* Locally-defined functions use absolute accesses to set up
1863 the global pointer. */
1864 if (TARGET_ABSOLUTE_ABICALLS
1865 && mips_symbol_binds_local_p (x)
1866 && !SYMBOL_REF_EXTERNAL_P (x))
1873 /* Return the method that should be used to access SYMBOL_REF or
1874 LABEL_REF X in context CONTEXT. */
1876 static enum mips_symbol_type
1877 mips_classify_symbol (const_rtx x, enum mips_symbol_context context)
1880 return SYMBOL_GOT_DISP;
1882 if (GET_CODE (x) == LABEL_REF)
1884 /* Only return SYMBOL_PC_RELATIVE if we are generating MIPS16
1885 code and if we know that the label is in the current function's
1886 text section. LABEL_REFs are used for jump tables as well as
1887 text labels, so we must check whether jump tables live in the
1889 if (TARGET_MIPS16_SHORT_JUMP_TABLES
1890 && !LABEL_REF_NONLOCAL_P (x))
1891 return SYMBOL_PC_RELATIVE;
1893 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1894 return SYMBOL_GOT_PAGE_OFST;
1896 return SYMBOL_ABSOLUTE;
1899 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1901 if (SYMBOL_REF_TLS_MODEL (x))
1904 if (CONSTANT_POOL_ADDRESS_P (x))
1906 if (TARGET_MIPS16_TEXT_LOADS)
1907 return SYMBOL_PC_RELATIVE;
1909 if (TARGET_MIPS16_PCREL_LOADS && context == SYMBOL_CONTEXT_MEM)
1910 return SYMBOL_PC_RELATIVE;
1912 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x)))
1913 return SYMBOL_GP_RELATIVE;
1916 /* Do not use small-data accesses for weak symbols; they may end up
1918 if (TARGET_GPOPT && SYMBOL_REF_SMALL_P (x) && !SYMBOL_REF_WEAK (x))
1919 return SYMBOL_GP_RELATIVE;
1921 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1923 if (TARGET_ABICALLS_PIC2
1924 && !(TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x)))
1926 /* There are three cases to consider:
1928 - o32 PIC (either with or without explicit relocs)
1929 - n32/n64 PIC without explicit relocs
1930 - n32/n64 PIC with explicit relocs
1932 In the first case, both local and global accesses will use an
1933 R_MIPS_GOT16 relocation. We must correctly predict which of
1934 the two semantics (local or global) the assembler and linker
1935 will apply. The choice depends on the symbol's binding rather
1936 than its visibility.
1938 In the second case, the assembler will not use R_MIPS_GOT16
1939 relocations, but it chooses between local and global accesses
1940 in the same way as for o32 PIC.
1942 In the third case we have more freedom since both forms of
1943 access will work for any kind of symbol. However, there seems
1944 little point in doing things differently. */
1945 if (mips_global_symbol_p (x))
1946 return SYMBOL_GOT_DISP;
1948 return SYMBOL_GOT_PAGE_OFST;
1951 return SYMBOL_ABSOLUTE;
1954 /* Classify the base of symbolic expression X, given that X appears in
1957 static enum mips_symbol_type
1958 mips_classify_symbolic_expression (rtx x, enum mips_symbol_context context)
1962 split_const (x, &x, &offset);
1963 if (UNSPEC_ADDRESS_P (x))
1964 return UNSPEC_ADDRESS_TYPE (x);
1966 return mips_classify_symbol (x, context);
1969 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1970 is the alignment in bytes of SYMBOL_REF X. */
1973 mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset)
1975 HOST_WIDE_INT align;
1977 align = SYMBOL_REF_DECL (x) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x)) : 1;
1978 return IN_RANGE (offset, 0, align - 1);
1981 /* Return true if X is a symbolic constant that can be used in context
1982 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1985 mips_symbolic_constant_p (rtx x, enum mips_symbol_context context,
1986 enum mips_symbol_type *symbol_type)
1990 split_const (x, &x, &offset);
1991 if (UNSPEC_ADDRESS_P (x))
1993 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1994 x = UNSPEC_ADDRESS (x);
1996 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1998 *symbol_type = mips_classify_symbol (x, context);
1999 if (*symbol_type == SYMBOL_TLS)
2005 if (offset == const0_rtx)
2008 /* Check whether a nonzero offset is valid for the underlying
2010 switch (*symbol_type)
2012 case SYMBOL_ABSOLUTE:
2013 case SYMBOL_64_HIGH:
2016 /* If the target has 64-bit pointers and the object file only
2017 supports 32-bit symbols, the values of those symbols will be
2018 sign-extended. In this case we can't allow an arbitrary offset
2019 in case the 32-bit value X + OFFSET has a different sign from X. */
2020 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
2021 return offset_within_block_p (x, INTVAL (offset));
2023 /* In other cases the relocations can handle any offset. */
2026 case SYMBOL_PC_RELATIVE:
2027 /* Allow constant pool references to be converted to LABEL+CONSTANT.
2028 In this case, we no longer have access to the underlying constant,
2029 but the original symbol-based access was known to be valid. */
2030 if (GET_CODE (x) == LABEL_REF)
2035 case SYMBOL_GP_RELATIVE:
2036 /* Make sure that the offset refers to something within the
2037 same object block. This should guarantee that the final
2038 PC- or GP-relative offset is within the 16-bit limit. */
2039 return offset_within_block_p (x, INTVAL (offset));
2041 case SYMBOL_GOT_PAGE_OFST:
2042 case SYMBOL_GOTOFF_PAGE:
2043 /* If the symbol is global, the GOT entry will contain the symbol's
2044 address, and we will apply a 16-bit offset after loading it.
2045 If the symbol is local, the linker should provide enough local
2046 GOT entries for a 16-bit offset, but larger offsets may lead
2048 return SMALL_INT (offset);
2052 /* There is no carry between the HI and LO REL relocations, so the
2053 offset is only valid if we know it won't lead to such a carry. */
2054 return mips_offset_within_alignment_p (x, INTVAL (offset));
2056 case SYMBOL_GOT_DISP:
2057 case SYMBOL_GOTOFF_DISP:
2058 case SYMBOL_GOTOFF_CALL:
2059 case SYMBOL_GOTOFF_LOADGP:
2062 case SYMBOL_GOTTPREL:
2070 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
2071 single instruction. We rely on the fact that, in the worst case,
2072 all instructions involved in a MIPS16 address calculation are usually
2076 mips_symbol_insns_1 (enum mips_symbol_type type, machine_mode mode)
2078 if (mips_use_pcrel_pool_p[(int) type])
2080 if (mode == MAX_MACHINE_MODE)
2081 /* LEAs will be converted into constant-pool references by
2083 type = SYMBOL_PC_RELATIVE;
2085 /* The constant must be loaded and then dereferenced. */
2091 case SYMBOL_ABSOLUTE:
2092 /* When using 64-bit symbols, we need 5 preparatory instructions,
2095 lui $at,%highest(symbol)
2096 daddiu $at,$at,%higher(symbol)
2098 daddiu $at,$at,%hi(symbol)
2101 The final address is then $at + %lo(symbol). With 32-bit
2102 symbols we just need a preparatory LUI for normal mode and
2103 a preparatory LI and SLL for MIPS16. */
2104 return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2;
2106 case SYMBOL_GP_RELATIVE:
2107 /* Treat GP-relative accesses as taking a single instruction on
2108 MIPS16 too; the copy of $gp can often be shared. */
2111 case SYMBOL_PC_RELATIVE:
2112 /* PC-relative constants can be only be used with ADDIUPC,
2113 DADDIUPC, LWPC and LDPC. */
2114 if (mode == MAX_MACHINE_MODE
2115 || GET_MODE_SIZE (mode) == 4
2116 || GET_MODE_SIZE (mode) == 8)
2119 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
2122 case SYMBOL_GOT_DISP:
2123 /* The constant will have to be loaded from the GOT before it
2124 is used in an address. */
2125 if (mode != MAX_MACHINE_MODE)
2130 case SYMBOL_GOT_PAGE_OFST:
2131 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
2132 local/global classification is accurate. The worst cases are:
2134 (1) For local symbols when generating o32 or o64 code. The assembler
2140 ...and the final address will be $at + %lo(symbol).
2142 (2) For global symbols when -mxgot. The assembler will use:
2144 lui $at,%got_hi(symbol)
2147 ...and the final address will be $at + %got_lo(symbol). */
2150 case SYMBOL_GOTOFF_PAGE:
2151 case SYMBOL_GOTOFF_DISP:
2152 case SYMBOL_GOTOFF_CALL:
2153 case SYMBOL_GOTOFF_LOADGP:
2154 case SYMBOL_64_HIGH:
2160 case SYMBOL_GOTTPREL:
2163 /* A 16-bit constant formed by a single relocation, or a 32-bit
2164 constant formed from a high 16-bit relocation and a low 16-bit
2165 relocation. Use mips_split_p to determine which. 32-bit
2166 constants need an "lui; addiu" sequence for normal mode and
2167 an "li; sll; addiu" sequence for MIPS16 mode. */
2168 return !mips_split_p[type] ? 1 : TARGET_MIPS16 ? 3 : 2;
2171 /* We don't treat a bare TLS symbol as a constant. */
2177 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
2178 to load symbols of type TYPE into a register. Return 0 if the given
2179 type of symbol cannot be used as an immediate operand.
2181 Otherwise, return the number of instructions needed to load or store
2182 values of mode MODE to or from addresses of type TYPE. Return 0 if
2183 the given type of symbol is not valid in addresses.
2185 In both cases, instruction counts are based off BASE_INSN_LENGTH. */
2188 mips_symbol_insns (enum mips_symbol_type type, machine_mode mode)
2190 return mips_symbol_insns_1 (type, mode) * (TARGET_MIPS16 ? 2 : 1);
2193 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
2196 mips_cannot_force_const_mem (machine_mode mode, rtx x)
2198 enum mips_symbol_type type;
2201 /* There is no assembler syntax for expressing an address-sized
2203 if (GET_CODE (x) == HIGH)
2206 /* As an optimization, reject constants that mips_legitimize_move
2209 Suppose we have a multi-instruction sequence that loads constant C
2210 into register R. If R does not get allocated a hard register, and
2211 R is used in an operand that allows both registers and memory
2212 references, reload will consider forcing C into memory and using
2213 one of the instruction's memory alternatives. Returning false
2214 here will force it to use an input reload instead. */
2215 if (CONST_INT_P (x) && mips_legitimate_constant_p (mode, x))
2218 split_const (x, &base, &offset);
2219 if (mips_symbolic_constant_p (base, SYMBOL_CONTEXT_LEA, &type))
2221 /* See whether we explicitly want these symbols in the pool. */
2222 if (mips_use_pcrel_pool_p[(int) type])
2225 /* The same optimization as for CONST_INT. */
2226 if (SMALL_INT (offset) && mips_symbol_insns (type, MAX_MACHINE_MODE) > 0)
2229 /* If MIPS16 constant pools live in the text section, they should
2230 not refer to anything that might need run-time relocation. */
2231 if (TARGET_MIPS16_PCREL_LOADS && mips_got_symbol_type_p (type))
2235 /* TLS symbols must be computed by mips_legitimize_move. */
2236 if (tls_referenced_p (x))
2242 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
2243 constants when we're using a per-function constant pool. */
2246 mips_use_blocks_for_constant_p (machine_mode mode ATTRIBUTE_UNUSED,
2247 const_rtx x ATTRIBUTE_UNUSED)
2249 return !TARGET_MIPS16_PCREL_LOADS;
2252 /* Return true if register REGNO is a valid base register for mode MODE.
2253 STRICT_P is true if REG_OK_STRICT is in effect. */
2256 mips_regno_mode_ok_for_base_p (int regno, machine_mode mode,
2259 if (!HARD_REGISTER_NUM_P (regno))
2263 regno = reg_renumber[regno];
2266 /* These fake registers will be eliminated to either the stack or
2267 hard frame pointer, both of which are usually valid base registers.
2268 Reload deals with the cases where the eliminated form isn't valid. */
2269 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
2272 /* In MIPS16 mode, the stack pointer can only address word and doubleword
2273 values, nothing smaller. */
2274 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
2275 return GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
2277 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
2280 /* Return true if X is a valid base register for mode MODE.
2281 STRICT_P is true if REG_OK_STRICT is in effect. */
2284 mips_valid_base_register_p (rtx x, machine_mode mode, bool strict_p)
2286 if (!strict_p && GET_CODE (x) == SUBREG)
2290 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p));
2293 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2294 can address a value of mode MODE. */
2297 mips_valid_offset_p (rtx x, machine_mode mode)
2299 /* Check that X is a signed 16-bit number. */
2300 if (!const_arith_operand (x, Pmode))
2303 /* We may need to split multiword moves, so make sure that every word
2305 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2306 && !SMALL_OPERAND (INTVAL (x) + GET_MODE_SIZE (mode) - UNITS_PER_WORD))
2312 /* Return true if a LO_SUM can address a value of mode MODE when the
2313 LO_SUM symbol has type SYMBOL_TYPE. */
2316 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type, machine_mode mode)
2318 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2320 if (mips_symbol_insns (symbol_type, mode) == 0)
2323 /* Check that there is a known low-part relocation. */
2324 if (mips_lo_relocs[symbol_type] == NULL)
2327 /* We may need to split multiword moves, so make sure that each word
2328 can be accessed without inducing a carry. This is mainly needed
2329 for o64, which has historically only guaranteed 64-bit alignment
2330 for 128-bit types. */
2331 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2332 && GET_MODE_BITSIZE (mode) > GET_MODE_ALIGNMENT (mode))
2338 /* Return true if X is a valid address for machine mode MODE. If it is,
2339 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2343 mips_classify_address (struct mips_address_info *info, rtx x,
2344 machine_mode mode, bool strict_p)
2346 switch (GET_CODE (x))
2350 info->type = ADDRESS_REG;
2352 info->offset = const0_rtx;
2353 return mips_valid_base_register_p (info->reg, mode, strict_p);
2356 info->type = ADDRESS_REG;
2357 info->reg = XEXP (x, 0);
2358 info->offset = XEXP (x, 1);
2359 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2360 && mips_valid_offset_p (info->offset, mode));
2363 info->type = ADDRESS_LO_SUM;
2364 info->reg = XEXP (x, 0);
2365 info->offset = XEXP (x, 1);
2366 /* We have to trust the creator of the LO_SUM to do something vaguely
2367 sane. Target-independent code that creates a LO_SUM should also
2368 create and verify the matching HIGH. Target-independent code that
2369 adds an offset to a LO_SUM must prove that the offset will not
2370 induce a carry. Failure to do either of these things would be
2371 a bug, and we are not required to check for it here. The MIPS
2372 backend itself should only create LO_SUMs for valid symbolic
2373 constants, with the high part being either a HIGH or a copy
2376 = mips_classify_symbolic_expression (info->offset, SYMBOL_CONTEXT_MEM);
2377 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2378 && mips_valid_lo_sum_p (info->symbol_type, mode));
2381 /* Small-integer addresses don't occur very often, but they
2382 are legitimate if $0 is a valid base register. */
2383 info->type = ADDRESS_CONST_INT;
2384 return !TARGET_MIPS16 && SMALL_INT (x);
2389 info->type = ADDRESS_SYMBOLIC;
2390 return (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_MEM,
2392 && mips_symbol_insns (info->symbol_type, mode) > 0
2393 && !mips_split_p[info->symbol_type]);
2400 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2403 mips_legitimate_address_p (machine_mode mode, rtx x, bool strict_p)
2405 struct mips_address_info addr;
2407 return mips_classify_address (&addr, x, mode, strict_p);
2410 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
2413 mips_stack_address_p (rtx x, machine_mode mode)
2415 struct mips_address_info addr;
2417 return (mips_classify_address (&addr, x, mode, false)
2418 && addr.type == ADDRESS_REG
2419 && addr.reg == stack_pointer_rtx);
2422 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2423 address instruction. Note that such addresses are not considered
2424 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2425 is so restricted. */
2428 mips_lwxs_address_p (rtx addr)
2431 && GET_CODE (addr) == PLUS
2432 && REG_P (XEXP (addr, 1)))
2434 rtx offset = XEXP (addr, 0);
2435 if (GET_CODE (offset) == MULT
2436 && REG_P (XEXP (offset, 0))
2437 && CONST_INT_P (XEXP (offset, 1))
2438 && INTVAL (XEXP (offset, 1)) == 4)
2444 /* Return true if ADDR matches the pattern for the L{B,H,W,D}{,U}X load
2445 indexed address instruction. Note that such addresses are
2446 not considered legitimate in the TARGET_LEGITIMATE_ADDRESS_P
2447 sense, because their use is so restricted. */
2450 mips_lx_address_p (rtx addr, machine_mode mode)
2452 if (GET_CODE (addr) != PLUS
2453 || !REG_P (XEXP (addr, 0))
2454 || !REG_P (XEXP (addr, 1)))
2456 if (ISA_HAS_LBX && mode == QImode)
2458 if (ISA_HAS_LHX && mode == HImode)
2460 if (ISA_HAS_LWX && mode == SImode)
2462 if (ISA_HAS_LDX && mode == DImode)
2467 /* Return true if a value at OFFSET bytes from base register BASE can be
2468 accessed using an unextended MIPS16 instruction. MODE is the mode of
2471 Usually the offset in an unextended instruction is a 5-bit field.
2472 The offset is unsigned and shifted left once for LH and SH, twice
2473 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2474 an 8-bit immediate field that's shifted left twice. */
2477 mips16_unextended_reference_p (machine_mode mode, rtx base,
2478 unsigned HOST_WIDE_INT offset)
2480 if (mode != BLKmode && offset % GET_MODE_SIZE (mode) == 0)
2482 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
2483 return offset < 256U * GET_MODE_SIZE (mode);
2484 return offset < 32U * GET_MODE_SIZE (mode);
2489 /* Return the number of instructions needed to load or store a value
2490 of mode MODE at address X, assuming that BASE_INSN_LENGTH is the
2491 length of one instruction. Return 0 if X isn't valid for MODE.
2492 Assume that multiword moves may need to be split into word moves
2493 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2497 mips_address_insns (rtx x, machine_mode mode, bool might_split_p)
2499 struct mips_address_info addr;
2502 /* BLKmode is used for single unaligned loads and stores and should
2503 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2504 meaningless, so we have to single it out as a special case one way
2506 if (mode != BLKmode && might_split_p)
2507 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2511 if (mips_classify_address (&addr, x, mode, false))
2516 && !mips16_unextended_reference_p (mode, addr.reg,
2517 UINTVAL (addr.offset)))
2521 case ADDRESS_LO_SUM:
2522 return TARGET_MIPS16 ? factor * 2 : factor;
2524 case ADDRESS_CONST_INT:
2527 case ADDRESS_SYMBOLIC:
2528 return factor * mips_symbol_insns (addr.symbol_type, mode);
2533 /* Return true if X fits within an unsigned field of BITS bits that is
2534 shifted left SHIFT bits before being used. */
2537 mips_unsigned_immediate_p (unsigned HOST_WIDE_INT x, int bits, int shift = 0)
2539 return (x & ((1 << shift) - 1)) == 0 && x < ((unsigned) 1 << (shift + bits));
2542 /* Return true if X fits within a signed field of BITS bits that is
2543 shifted left SHIFT bits before being used. */
2546 mips_signed_immediate_p (unsigned HOST_WIDE_INT x, int bits, int shift = 0)
2548 x += 1 << (bits + shift - 1);
2549 return mips_unsigned_immediate_p (x, bits, shift);
2552 /* Return true if X is legitimate for accessing values of mode MODE,
2553 if it is based on a MIPS16 register, and if the offset satisfies
2554 OFFSET_PREDICATE. */
2557 m16_based_address_p (rtx x, machine_mode mode,
2558 insn_operand_predicate_fn offset_predicate)
2560 struct mips_address_info addr;
2562 return (mips_classify_address (&addr, x, mode, false)
2563 && addr.type == ADDRESS_REG
2564 && M16_REG_P (REGNO (addr.reg))
2565 && offset_predicate (addr.offset, mode));
2568 /* Return true if X is a legitimate address that conforms to the requirements
2569 for a microMIPS LWSP or SWSP insn. */
2572 lwsp_swsp_address_p (rtx x, machine_mode mode)
2574 struct mips_address_info addr;
2576 return (mips_classify_address (&addr, x, mode, false)
2577 && addr.type == ADDRESS_REG
2578 && REGNO (addr.reg) == STACK_POINTER_REGNUM
2579 && uw5_operand (addr.offset, mode));
2582 /* Return true if X is a legitimate address with a 12-bit offset.
2583 MODE is the mode of the value being accessed. */
2586 umips_12bit_offset_address_p (rtx x, machine_mode mode)
2588 struct mips_address_info addr;
2590 return (mips_classify_address (&addr, x, mode, false)
2591 && addr.type == ADDRESS_REG
2592 && CONST_INT_P (addr.offset)
2593 && UMIPS_12BIT_OFFSET_P (INTVAL (addr.offset)));
2596 /* Return the number of instructions needed to load constant X,
2597 assuming that BASE_INSN_LENGTH is the length of one instruction.
2598 Return 0 if X isn't a valid constant. */
2601 mips_const_insns (rtx x)
2603 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2604 enum mips_symbol_type symbol_type;
2607 switch (GET_CODE (x))
2610 if (!mips_symbolic_constant_p (XEXP (x, 0), SYMBOL_CONTEXT_LEA,
2612 || !mips_split_p[symbol_type])
2615 /* This is simply an LUI for normal mode. It is an extended
2616 LI followed by an extended SLL for MIPS16. */
2617 return TARGET_MIPS16 ? 4 : 1;
2621 /* Unsigned 8-bit constants can be loaded using an unextended
2622 LI instruction. Unsigned 16-bit constants can be loaded
2623 using an extended LI. Negative constants must be loaded
2624 using LI and then negated. */
2625 return (IN_RANGE (INTVAL (x), 0, 255) ? 1
2626 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
2627 : IN_RANGE (-INTVAL (x), 0, 255) ? 2
2628 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
2631 return mips_build_integer (codes, INTVAL (x));
2635 /* Allow zeros for normal mode, where we can use $0. */
2636 return !TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0;
2642 /* See if we can refer to X directly. */
2643 if (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_LEA, &symbol_type))
2644 return mips_symbol_insns (symbol_type, MAX_MACHINE_MODE);
2646 /* Otherwise try splitting the constant into a base and offset.
2647 If the offset is a 16-bit value, we can load the base address
2648 into a register and then use (D)ADDIU to add in the offset.
2649 If the offset is larger, we can load the base and offset
2650 into separate registers and add them together with (D)ADDU.
2651 However, the latter is only possible before reload; during
2652 and after reload, we must have the option of forcing the
2653 constant into the pool instead. */
2654 split_const (x, &x, &offset);
2657 int n = mips_const_insns (x);
2660 if (SMALL_INT (offset))
2662 else if (!targetm.cannot_force_const_mem (GET_MODE (x), x))
2663 return n + 1 + mips_build_integer (codes, INTVAL (offset));
2670 return mips_symbol_insns (mips_classify_symbol (x, SYMBOL_CONTEXT_LEA),
2678 /* X is a doubleword constant that can be handled by splitting it into
2679 two words and loading each word separately. Return the number of
2680 instructions required to do this, assuming that BASE_INSN_LENGTH
2681 is the length of one instruction. */
2684 mips_split_const_insns (rtx x)
2686 unsigned int low, high;
2688 low = mips_const_insns (mips_subword (x, false));
2689 high = mips_const_insns (mips_subword (x, true));
2690 gcc_assert (low > 0 && high > 0);
2694 /* Return the number of instructions needed to implement INSN,
2695 given that it loads from or stores to MEM. Assume that
2696 BASE_INSN_LENGTH is the length of one instruction. */
2699 mips_load_store_insns (rtx mem, rtx_insn *insn)
2705 gcc_assert (MEM_P (mem));
2706 mode = GET_MODE (mem);
2708 /* Try to prove that INSN does not need to be split. */
2709 might_split_p = GET_MODE_SIZE (mode) > UNITS_PER_WORD;
2712 set = single_set (insn);
2713 if (set && !mips_split_move_insn_p (SET_DEST (set), SET_SRC (set), insn))
2714 might_split_p = false;
2717 return mips_address_insns (XEXP (mem, 0), mode, might_split_p);
2720 /* Return the number of instructions needed for an integer division,
2721 assuming that BASE_INSN_LENGTH is the length of one instruction. */
2724 mips_idiv_insns (void)
2729 if (TARGET_CHECK_ZERO_DIV)
2731 if (GENERATE_DIVIDE_TRAPS)
2737 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
2742 /* Emit a move from SRC to DEST. Assume that the move expanders can
2743 handle all moves if !can_create_pseudo_p (). The distinction is
2744 important because, unlike emit_move_insn, the move expanders know
2745 how to force Pmode objects into the constant pool even when the
2746 constant pool address is not itself legitimate. */
2749 mips_emit_move (rtx dest, rtx src)
2751 return (can_create_pseudo_p ()
2752 ? emit_move_insn (dest, src)
2753 : emit_move_insn_1 (dest, src));
2756 /* Emit a move from SRC to DEST, splitting compound moves into individual
2757 instructions. SPLIT_TYPE is the type of split to perform. */
2760 mips_emit_move_or_split (rtx dest, rtx src, enum mips_split_type split_type)
2762 if (mips_split_move_p (dest, src, split_type))
2763 mips_split_move (dest, src, split_type);
2765 mips_emit_move (dest, src);
2768 /* Emit an instruction of the form (set TARGET (CODE OP0)). */
2771 mips_emit_unary (enum rtx_code code, rtx target, rtx op0)
2773 emit_insn (gen_rtx_SET (VOIDmode, target,
2774 gen_rtx_fmt_e (code, GET_MODE (op0), op0)));
2777 /* Compute (CODE OP0) and store the result in a new register of mode MODE.
2778 Return that new register. */
2781 mips_force_unary (machine_mode mode, enum rtx_code code, rtx op0)
2785 reg = gen_reg_rtx (mode);
2786 mips_emit_unary (code, reg, op0);
2790 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2793 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
2795 emit_insn (gen_rtx_SET (VOIDmode, target,
2796 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
2799 /* Compute (CODE OP0 OP1) and store the result in a new register
2800 of mode MODE. Return that new register. */
2803 mips_force_binary (machine_mode mode, enum rtx_code code, rtx op0, rtx op1)
2807 reg = gen_reg_rtx (mode);
2808 mips_emit_binary (code, reg, op0, op1);
2812 /* Copy VALUE to a register and return that register. If new pseudos
2813 are allowed, copy it into a new register, otherwise use DEST. */
2816 mips_force_temporary (rtx dest, rtx value)
2818 if (can_create_pseudo_p ())
2819 return force_reg (Pmode, value);
2822 mips_emit_move (dest, value);
2827 /* Emit a call sequence with call pattern PATTERN and return the call
2828 instruction itself (which is not necessarily the last instruction
2829 emitted). ORIG_ADDR is the original, unlegitimized address,
2830 ADDR is the legitimized form, and LAZY_P is true if the call
2831 address is lazily-bound. */
2834 mips_emit_call_insn (rtx pattern, rtx orig_addr, rtx addr, bool lazy_p)
2839 insn = emit_call_insn (pattern);
2841 if (TARGET_MIPS16 && mips_use_pic_fn_addr_reg_p (orig_addr))
2843 /* MIPS16 JALRs only take MIPS16 registers. If the target
2844 function requires $25 to be valid on entry, we must copy it
2845 there separately. The move instruction can be put in the
2846 call's delay slot. */
2847 reg = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
2848 emit_insn_before (gen_move_insn (reg, addr), insn);
2849 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
2853 /* Lazy-binding stubs require $gp to be valid on entry. */
2854 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
2858 /* See the comment above load_call<mode> for details. */
2859 use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
2860 gen_rtx_REG (Pmode, GOT_VERSION_REGNUM));
2861 emit_insn (gen_update_got_version ());
2865 && TARGET_EXPLICIT_RELOCS
2866 && TARGET_CALL_CLOBBERED_GP)
2868 rtx post_call_tmp_reg = gen_rtx_REG (word_mode, POST_CALL_TMP_REG);
2869 clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), post_call_tmp_reg);
2875 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2876 then add CONST_INT OFFSET to the result. */
2879 mips_unspec_address_offset (rtx base, rtx offset,
2880 enum mips_symbol_type symbol_type)
2882 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
2883 UNSPEC_ADDRESS_FIRST + symbol_type);
2884 if (offset != const0_rtx)
2885 base = gen_rtx_PLUS (Pmode, base, offset);
2886 return gen_rtx_CONST (Pmode, base);
2889 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2890 type SYMBOL_TYPE. */
2893 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
2897 split_const (address, &base, &offset);
2898 return mips_unspec_address_offset (base, offset, symbol_type);
2901 /* If OP is an UNSPEC address, return the address to which it refers,
2902 otherwise return OP itself. */
2905 mips_strip_unspec_address (rtx op)
2909 split_const (op, &base, &offset);
2910 if (UNSPEC_ADDRESS_P (base))
2911 op = plus_constant (Pmode, UNSPEC_ADDRESS (base), INTVAL (offset));
2915 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2916 high part to BASE and return the result. Just return BASE otherwise.
2917 TEMP is as for mips_force_temporary.
2919 The returned expression can be used as the first operand to a LO_SUM. */
2922 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
2923 enum mips_symbol_type symbol_type)
2925 if (mips_split_p[symbol_type])
2927 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
2928 addr = mips_force_temporary (temp, addr);
2929 base = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
2934 /* Return an instruction that copies $gp into register REG. We want
2935 GCC to treat the register's value as constant, so that its value
2936 can be rematerialized on demand. */
2939 gen_load_const_gp (rtx reg)
2941 return PMODE_INSN (gen_load_const_gp, (reg));
2944 /* Return a pseudo register that contains the value of $gp throughout
2945 the current function. Such registers are needed by MIPS16 functions,
2946 for which $gp itself is not a valid base register or addition operand. */
2949 mips16_gp_pseudo_reg (void)
2951 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
2955 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
2957 push_topmost_sequence ();
2959 scan = get_insns ();
2960 while (NEXT_INSN (scan) && !INSN_P (NEXT_INSN (scan)))
2961 scan = NEXT_INSN (scan);
2963 rtx set = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
2964 rtx_insn *insn = emit_insn_after (set, scan);
2965 INSN_LOCATION (insn) = 0;
2967 pop_topmost_sequence ();
2970 return cfun->machine->mips16_gp_pseudo_rtx;
2973 /* Return a base register that holds pic_offset_table_rtx.
2974 TEMP, if nonnull, is a scratch Pmode base register. */
2977 mips_pic_base_register (rtx temp)
2980 return pic_offset_table_rtx;
2982 if (currently_expanding_to_rtl)
2983 return mips16_gp_pseudo_reg ();
2985 if (can_create_pseudo_p ())
2986 temp = gen_reg_rtx (Pmode);
2989 /* The first post-reload split exposes all references to $gp
2990 (both uses and definitions). All references must remain
2991 explicit after that point.
2993 It is safe to introduce uses of $gp at any time, so for
2994 simplicity, we do that before the split too. */
2995 mips_emit_move (temp, pic_offset_table_rtx);
2997 emit_insn (gen_load_const_gp (temp));
3001 /* Return the RHS of a load_call<mode> insn. */
3004 mips_unspec_call (rtx reg, rtx symbol)
3008 vec = gen_rtvec (3, reg, symbol, gen_rtx_REG (SImode, GOT_VERSION_REGNUM));
3009 return gen_rtx_UNSPEC (Pmode, vec, UNSPEC_LOAD_CALL);
3012 /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol
3013 reference. Return NULL_RTX otherwise. */
3016 mips_strip_unspec_call (rtx src)
3018 if (GET_CODE (src) == UNSPEC && XINT (src, 1) == UNSPEC_LOAD_CALL)
3019 return mips_strip_unspec_address (XVECEXP (src, 0, 1));
3023 /* Create and return a GOT reference of type TYPE for address ADDR.
3024 TEMP, if nonnull, is a scratch Pmode base register. */
3027 mips_got_load (rtx temp, rtx addr, enum mips_symbol_type type)
3029 rtx base, high, lo_sum_symbol;
3031 base = mips_pic_base_register (temp);
3033 /* If we used the temporary register to load $gp, we can't use
3034 it for the high part as well. */
3035 if (temp != NULL && reg_overlap_mentioned_p (base, temp))
3038 high = mips_unspec_offset_high (temp, base, addr, type);
3039 lo_sum_symbol = mips_unspec_address (addr, type);
3041 if (type == SYMBOL_GOTOFF_CALL)
3042 return mips_unspec_call (high, lo_sum_symbol);
3044 return PMODE_INSN (gen_unspec_got, (high, lo_sum_symbol));
3047 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
3048 it appears in a MEM of that mode. Return true if ADDR is a legitimate
3049 constant in that context and can be split into high and low parts.
3050 If so, and if LOW_OUT is nonnull, emit the high part and store the
3051 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
3053 TEMP is as for mips_force_temporary and is used to load the high
3054 part into a register.
3056 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
3057 a legitimize SET_SRC for an .md pattern, otherwise the low part
3058 is guaranteed to be a legitimate address for mode MODE. */
3061 mips_split_symbol (rtx temp, rtx addr, machine_mode mode, rtx *low_out)
3063 enum mips_symbol_context context;
3064 enum mips_symbol_type symbol_type;
3067 context = (mode == MAX_MACHINE_MODE
3068 ? SYMBOL_CONTEXT_LEA
3069 : SYMBOL_CONTEXT_MEM);
3070 if (GET_CODE (addr) == HIGH && context == SYMBOL_CONTEXT_LEA)
3072 addr = XEXP (addr, 0);
3073 if (mips_symbolic_constant_p (addr, context, &symbol_type)
3074 && mips_symbol_insns (symbol_type, mode) > 0
3075 && mips_split_hi_p[symbol_type])
3078 switch (symbol_type)
3080 case SYMBOL_GOT_PAGE_OFST:
3081 /* The high part of a page/ofst pair is loaded from the GOT. */
3082 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_PAGE);
3093 if (mips_symbolic_constant_p (addr, context, &symbol_type)
3094 && mips_symbol_insns (symbol_type, mode) > 0
3095 && mips_split_p[symbol_type])
3098 switch (symbol_type)
3100 case SYMBOL_GOT_DISP:
3101 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
3102 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_DISP);
3105 case SYMBOL_GP_RELATIVE:
3106 high = mips_pic_base_register (temp);
3107 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
3111 high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
3112 high = mips_force_temporary (temp, high);
3113 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
3122 /* Return a legitimate address for REG + OFFSET. TEMP is as for
3123 mips_force_temporary; it is only needed when OFFSET is not a
3127 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
3129 if (!SMALL_OPERAND (offset))
3135 /* Load the full offset into a register so that we can use
3136 an unextended instruction for the address itself. */
3137 high = GEN_INT (offset);
3142 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
3143 The addition inside the macro CONST_HIGH_PART may cause an
3144 overflow, so we need to force a sign-extension check. */
3145 high = gen_int_mode (CONST_HIGH_PART (offset), Pmode);
3146 offset = CONST_LOW_PART (offset);
3148 high = mips_force_temporary (temp, high);
3149 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
3151 return plus_constant (Pmode, reg, offset);
3154 /* The __tls_get_attr symbol. */
3155 static GTY(()) rtx mips_tls_symbol;
3157 /* Return an instruction sequence that calls __tls_get_addr. SYM is
3158 the TLS symbol we are referencing and TYPE is the symbol type to use
3159 (either global dynamic or local dynamic). V0 is an RTX for the
3160 return value location. */
3163 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
3167 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
3169 if (!mips_tls_symbol)
3170 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
3172 loc = mips_unspec_address (sym, type);
3176 emit_insn (gen_rtx_SET (Pmode, a0,
3177 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
3178 insn = mips_expand_call (MIPS_CALL_NORMAL, v0, mips_tls_symbol,
3179 const0_rtx, NULL_RTX, false);
3180 RTL_CONST_CALL_P (insn) = 1;
3181 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
3182 insn = get_insns ();
3189 /* Return a pseudo register that contains the current thread pointer. */
3192 mips_expand_thread_pointer (rtx tp)
3198 if (!mips16_rdhwr_stub)
3199 mips16_rdhwr_stub = new mips16_rdhwr_one_only_stub ();
3200 fn = mips16_stub_call_address (mips16_rdhwr_stub);
3201 emit_insn (PMODE_INSN (gen_tls_get_tp_mips16, (tp, fn)));
3204 emit_insn (PMODE_INSN (gen_tls_get_tp, (tp)));
3211 return mips_expand_thread_pointer (gen_reg_rtx (Pmode));
3214 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
3215 its address. The return value will be both a valid address and a valid
3216 SET_SRC (either a REG or a LO_SUM). */
3219 mips_legitimize_tls_address (rtx loc)
3221 rtx dest, insn, v0, tp, tmp1, tmp2, eqv, offset;
3222 enum tls_model model;
3224 model = SYMBOL_REF_TLS_MODEL (loc);
3225 /* Only TARGET_ABICALLS code can have more than one module; other
3226 code must be be static and should not use a GOT. All TLS models
3227 reduce to local exec in this situation. */
3228 if (!TARGET_ABICALLS)
3229 model = TLS_MODEL_LOCAL_EXEC;
3233 case TLS_MODEL_GLOBAL_DYNAMIC:
3234 v0 = gen_rtx_REG (Pmode, GP_RETURN);
3235 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
3236 dest = gen_reg_rtx (Pmode);
3237 emit_libcall_block (insn, dest, v0, loc);
3240 case TLS_MODEL_LOCAL_DYNAMIC:
3241 v0 = gen_rtx_REG (Pmode, GP_RETURN);
3242 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
3243 tmp1 = gen_reg_rtx (Pmode);
3245 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
3246 share the LDM result with other LD model accesses. */
3247 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3249 emit_libcall_block (insn, tmp1, v0, eqv);
3251 offset = mips_unspec_address (loc, SYMBOL_DTPREL);
3252 if (mips_split_p[SYMBOL_DTPREL])
3254 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
3255 dest = gen_rtx_LO_SUM (Pmode, tmp2, offset);
3258 dest = expand_binop (Pmode, add_optab, tmp1, offset,
3259 0, 0, OPTAB_DIRECT);
3262 case TLS_MODEL_INITIAL_EXEC:
3263 tp = mips_get_tp ();
3264 tmp1 = gen_reg_rtx (Pmode);
3265 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
3266 if (Pmode == DImode)
3267 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
3269 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
3270 dest = gen_reg_rtx (Pmode);
3271 emit_insn (gen_add3_insn (dest, tmp1, tp));
3274 case TLS_MODEL_LOCAL_EXEC:
3275 tmp1 = mips_get_tp ();
3276 offset = mips_unspec_address (loc, SYMBOL_TPREL);
3277 if (mips_split_p[SYMBOL_TPREL])
3279 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_TPREL);
3280 dest = gen_rtx_LO_SUM (Pmode, tmp2, offset);
3283 dest = expand_binop (Pmode, add_optab, tmp1, offset,
3284 0, 0, OPTAB_DIRECT);
3293 /* Implement "TARGET = __builtin_mips_get_fcsr ()" for MIPS16,
3297 mips16_expand_get_fcsr (rtx target)
3299 if (!mips16_get_fcsr_stub)
3300 mips16_get_fcsr_stub = new mips16_get_fcsr_one_only_stub ();
3301 rtx fn = mips16_stub_call_address (mips16_get_fcsr_stub);
3302 emit_insn (PMODE_INSN (gen_mips_get_fcsr_mips16, (fn)));
3303 emit_move_insn (target, gen_rtx_REG (SImode, GET_FCSR_REGNUM));
3306 /* Implement __builtin_mips_set_fcsr (TARGET) for MIPS16, using a stub. */
3309 mips16_expand_set_fcsr (rtx newval)
3311 if (!mips16_set_fcsr_stub)
3312 mips16_set_fcsr_stub = new mips16_set_fcsr_one_only_stub ();
3313 rtx fn = mips16_stub_call_address (mips16_set_fcsr_stub);
3314 emit_move_insn (gen_rtx_REG (SImode, SET_FCSR_REGNUM), newval);
3315 emit_insn (PMODE_INSN (gen_mips_set_fcsr_mips16, (fn)));
3318 /* If X is not a valid address for mode MODE, force it into a register. */
3321 mips_force_address (rtx x, machine_mode mode)
3323 if (!mips_legitimate_address_p (mode, x, false))
3324 x = force_reg (Pmode, x);
3328 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
3329 be legitimized in a way that the generic machinery might not expect,
3330 return a new address, otherwise return NULL. MODE is the mode of
3331 the memory being accessed. */
3334 mips_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3338 HOST_WIDE_INT offset;
3340 if (mips_tls_symbol_p (x))
3341 return mips_legitimize_tls_address (x);
3343 /* See if the address can split into a high part and a LO_SUM. */
3344 if (mips_split_symbol (NULL, x, mode, &addr))
3345 return mips_force_address (addr, mode);
3347 /* Handle BASE + OFFSET using mips_add_offset. */
3348 mips_split_plus (x, &base, &offset);
3351 if (!mips_valid_base_register_p (base, mode, false))
3352 base = copy_to_mode_reg (Pmode, base);
3353 addr = mips_add_offset (NULL, base, offset);
3354 return mips_force_address (addr, mode);
3360 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
3363 mips_move_integer (rtx temp, rtx dest, unsigned HOST_WIDE_INT value)
3365 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
3367 unsigned int i, num_ops;
3370 mode = GET_MODE (dest);
3371 num_ops = mips_build_integer (codes, value);
3373 /* Apply each binary operation to X. Invariant: X is a legitimate
3374 source operand for a SET pattern. */
3375 x = GEN_INT (codes[0].value);
3376 for (i = 1; i < num_ops; i++)
3378 if (!can_create_pseudo_p ())
3380 emit_insn (gen_rtx_SET (VOIDmode, temp, x));
3384 x = force_reg (mode, x);
3385 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
3388 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
3391 /* Subroutine of mips_legitimize_move. Move constant SRC into register
3392 DEST given that SRC satisfies immediate_operand but doesn't satisfy
3396 mips_legitimize_const_move (machine_mode mode, rtx dest, rtx src)
3400 /* Split moves of big integers into smaller pieces. */
3401 if (splittable_const_int_operand (src, mode))
3403 mips_move_integer (dest, dest, INTVAL (src));
3407 /* Split moves of symbolic constants into high/low pairs. */
3408 if (mips_split_symbol (dest, src, MAX_MACHINE_MODE, &src))
3410 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
3414 /* Generate the appropriate access sequences for TLS symbols. */
3415 if (mips_tls_symbol_p (src))
3417 mips_emit_move (dest, mips_legitimize_tls_address (src));
3421 /* If we have (const (plus symbol offset)), and that expression cannot
3422 be forced into memory, load the symbol first and add in the offset.
3423 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
3424 forced into memory, as it usually produces better code. */
3425 split_const (src, &base, &offset);
3426 if (offset != const0_rtx
3427 && (targetm.cannot_force_const_mem (mode, src)
3428 || (!TARGET_MIPS16 && can_create_pseudo_p ())))
3430 base = mips_force_temporary (dest, base);
3431 mips_emit_move (dest, mips_add_offset (NULL, base, INTVAL (offset)));
3435 src = force_const_mem (mode, src);
3437 /* When using explicit relocs, constant pool references are sometimes
3438 not legitimate addresses. */
3439 mips_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0));
3440 mips_emit_move (dest, src);
3443 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
3444 sequence that is valid. */
3447 mips_legitimize_move (machine_mode mode, rtx dest, rtx src)
3449 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
3451 mips_emit_move (dest, force_reg (mode, src));
3455 /* We need to deal with constants that would be legitimate
3456 immediate_operands but aren't legitimate move_operands. */
3457 if (CONSTANT_P (src) && !move_operand (src, mode))
3459 mips_legitimize_const_move (mode, dest, src);
3460 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
3466 /* Return true if value X in context CONTEXT is a small-data address
3467 that can be rewritten as a LO_SUM. */
3470 mips_rewrite_small_data_p (rtx x, enum mips_symbol_context context)
3472 enum mips_symbol_type symbol_type;
3474 return (mips_lo_relocs[SYMBOL_GP_RELATIVE]
3475 && !mips_split_p[SYMBOL_GP_RELATIVE]
3476 && mips_symbolic_constant_p (x, context, &symbol_type)
3477 && symbol_type == SYMBOL_GP_RELATIVE);
3480 /* Return true if OP refers to small data symbols directly, not through
3481 a LO_SUM. CONTEXT is the context in which X appears. */
3484 mips_small_data_pattern_1 (rtx x, enum mips_symbol_context context)
3486 subrtx_var_iterator::array_type array;
3487 FOR_EACH_SUBRTX_VAR (iter, array, x, ALL)
3491 /* Ignore things like "g" constraints in asms. We make no particular
3492 guarantee about which symbolic constants are acceptable as asm operands
3493 versus which must be forced into a GPR. */
3494 if (GET_CODE (x) == LO_SUM || GET_CODE (x) == ASM_OPERANDS)
3495 iter.skip_subrtxes ();
3498 if (mips_small_data_pattern_1 (XEXP (x, 0), SYMBOL_CONTEXT_MEM))
3500 iter.skip_subrtxes ();
3502 else if (mips_rewrite_small_data_p (x, context))
3508 /* Return true if OP refers to small data symbols directly, not through
3512 mips_small_data_pattern_p (rtx op)
3514 return mips_small_data_pattern_1 (op, SYMBOL_CONTEXT_LEA);
3517 /* Rewrite *LOC so that it refers to small data using explicit
3518 relocations. CONTEXT is the context in which *LOC appears. */
3521 mips_rewrite_small_data_1 (rtx *loc, enum mips_symbol_context context)
3523 subrtx_ptr_iterator::array_type array;
3524 FOR_EACH_SUBRTX_PTR (iter, array, loc, ALL)
3529 mips_rewrite_small_data_1 (&XEXP (*loc, 0), SYMBOL_CONTEXT_MEM);
3530 iter.skip_subrtxes ();
3532 else if (mips_rewrite_small_data_p (*loc, context))
3534 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
3535 iter.skip_subrtxes ();
3537 else if (GET_CODE (*loc) == LO_SUM)
3538 iter.skip_subrtxes ();
3542 /* Rewrite instruction pattern PATTERN so that it refers to small data
3543 using explicit relocations. */
3546 mips_rewrite_small_data (rtx pattern)
3548 pattern = copy_insn (pattern);
3549 mips_rewrite_small_data_1 (&pattern, SYMBOL_CONTEXT_LEA);
3553 /* The cost of loading values from the constant pool. It should be
3554 larger than the cost of any constant we want to synthesize inline. */
3555 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3557 /* Return the cost of X when used as an operand to the MIPS16 instruction
3558 that implements CODE. Return -1 if there is no such instruction, or if
3559 X is not a valid immediate operand for it. */
3562 mips16_constant_cost (int code, HOST_WIDE_INT x)
3569 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3570 other shifts are extended. The shift patterns truncate the shift
3571 count to the right size, so there are no out-of-range values. */
3572 if (IN_RANGE (x, 1, 8))
3574 return COSTS_N_INSNS (1);
3577 if (IN_RANGE (x, -128, 127))
3579 if (SMALL_OPERAND (x))
3580 return COSTS_N_INSNS (1);
3584 /* Like LE, but reject the always-true case. */
3588 /* We add 1 to the immediate and use SLT. */
3591 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3594 if (IN_RANGE (x, 0, 255))
3596 if (SMALL_OPERAND_UNSIGNED (x))
3597 return COSTS_N_INSNS (1);
3602 /* Equality comparisons with 0 are cheap. */
3612 /* Return true if there is a non-MIPS16 instruction that implements CODE
3613 and if that instruction accepts X as an immediate operand. */
3616 mips_immediate_operand_p (int code, HOST_WIDE_INT x)
3623 /* All shift counts are truncated to a valid constant. */
3628 /* Likewise rotates, if the target supports rotates at all. */
3634 /* These instructions take 16-bit unsigned immediates. */
3635 return SMALL_OPERAND_UNSIGNED (x);
3640 /* These instructions take 16-bit signed immediates. */
3641 return SMALL_OPERAND (x);
3647 /* The "immediate" forms of these instructions are really
3648 implemented as comparisons with register 0. */
3653 /* Likewise, meaning that the only valid immediate operand is 1. */
3657 /* We add 1 to the immediate and use SLT. */
3658 return SMALL_OPERAND (x + 1);
3661 /* Likewise SLTU, but reject the always-true case. */
3662 return SMALL_OPERAND (x + 1) && x + 1 != 0;
3666 /* The bit position and size are immediate operands. */
3667 return ISA_HAS_EXT_INS;
3670 /* By default assume that $0 can be used for 0. */
3675 /* Return the cost of binary operation X, given that the instruction
3676 sequence for a word-sized or smaller operation has cost SINGLE_COST
3677 and that the sequence of a double-word operation has cost DOUBLE_COST.
3678 If SPEED is true, optimize for speed otherwise optimize for size. */
3681 mips_binary_cost (rtx x, int single_cost, int double_cost, bool speed)
3685 if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2)
3690 + set_src_cost (XEXP (x, 0), speed)
3691 + rtx_cost (XEXP (x, 1), GET_CODE (x), 1, speed));
3694 /* Return the cost of floating-point multiplications of mode MODE. */
3697 mips_fp_mult_cost (machine_mode mode)
3699 return mode == DFmode ? mips_cost->fp_mult_df : mips_cost->fp_mult_sf;
3702 /* Return the cost of floating-point divisions of mode MODE. */
3705 mips_fp_div_cost (machine_mode mode)
3707 return mode == DFmode ? mips_cost->fp_div_df : mips_cost->fp_div_sf;
3710 /* Return the cost of sign-extending OP to mode MODE, not including the
3711 cost of OP itself. */
3714 mips_sign_extend_cost (machine_mode mode, rtx op)
3717 /* Extended loads are as cheap as unextended ones. */
3720 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3721 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3724 if (ISA_HAS_SEB_SEH || GENERATE_MIPS16E)
3725 /* We can use SEB or SEH. */
3726 return COSTS_N_INSNS (1);
3728 /* We need to use a shift left and a shift right. */
3729 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3732 /* Return the cost of zero-extending OP to mode MODE, not including the
3733 cost of OP itself. */
3736 mips_zero_extend_cost (machine_mode mode, rtx op)
3739 /* Extended loads are as cheap as unextended ones. */
3742 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3743 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3744 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3746 if (GENERATE_MIPS16E)
3747 /* We can use ZEB or ZEH. */
3748 return COSTS_N_INSNS (1);
3751 /* We need to load 0xff or 0xffff into a register and use AND. */
3752 return COSTS_N_INSNS (GET_MODE (op) == QImode ? 2 : 3);
3754 /* We can use ANDI. */
3755 return COSTS_N_INSNS (1);
3758 /* Return the cost of moving between two registers of mode MODE,
3759 assuming that the move will be in pieces of at most UNITS bytes. */
3762 mips_set_reg_reg_piece_cost (machine_mode mode, unsigned int units)
3764 return COSTS_N_INSNS ((GET_MODE_SIZE (mode) + units - 1) / units);
3767 /* Return the cost of moving between two registers of mode MODE. */
3770 mips_set_reg_reg_cost (machine_mode mode)
3772 switch (GET_MODE_CLASS (mode))
3775 return mips_set_reg_reg_piece_cost (mode, GET_MODE_SIZE (CCmode));
3778 case MODE_COMPLEX_FLOAT:
3779 case MODE_VECTOR_FLOAT:
3780 if (TARGET_HARD_FLOAT)
3781 return mips_set_reg_reg_piece_cost (mode, UNITS_PER_HWFPVALUE);
3785 return mips_set_reg_reg_piece_cost (mode, UNITS_PER_WORD);
3789 /* Implement TARGET_RTX_COSTS. */
3792 mips_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
3793 int *total, bool speed)
3795 machine_mode mode = GET_MODE (x);
3796 bool float_mode_p = FLOAT_MODE_P (mode);
3800 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3801 appear in the instruction stream, and the cost of a comparison is
3802 really the cost of the branch or scc condition. At the time of
3803 writing, GCC only uses an explicit outer COMPARE code when optabs
3804 is testing whether a constant is expensive enough to force into a
3805 register. We want optabs to pass such constants through the MIPS
3806 expanders instead, so make all constants very cheap here. */
3807 if (outer_code == COMPARE)
3809 gcc_assert (CONSTANT_P (x));
3817 /* Treat *clear_upper32-style ANDs as having zero cost in the
3818 second operand. The cost is entirely in the first operand.
3820 ??? This is needed because we would otherwise try to CSE
3821 the constant operand. Although that's the right thing for
3822 instructions that continue to be a register operation throughout
3823 compilation, it is disastrous for instructions that could
3824 later be converted into a memory operation. */
3826 && outer_code == AND
3827 && UINTVAL (x) == 0xffffffff)
3835 cost = mips16_constant_cost (outer_code, INTVAL (x));
3844 /* When not optimizing for size, we care more about the cost
3845 of hot code, and hot code is often in a loop. If a constant
3846 operand needs to be forced into a register, we will often be
3847 able to hoist the constant load out of the loop, so the load
3848 should not contribute to the cost. */
3849 if (speed || mips_immediate_operand_p (outer_code, INTVAL (x)))
3861 if (force_to_mem_operand (x, VOIDmode))
3863 *total = COSTS_N_INSNS (1);
3866 cost = mips_const_insns (x);
3869 /* If the constant is likely to be stored in a GPR, SETs of
3870 single-insn constants are as cheap as register sets; we
3871 never want to CSE them.
3873 Don't reduce the cost of storing a floating-point zero in
3874 FPRs. If we have a zero in an FPR for other reasons, we
3875 can get better cfg-cleanup and delayed-branch results by
3876 using it consistently, rather than using $0 sometimes and
3877 an FPR at other times. Also, moves between floating-point
3878 registers are sometimes cheaper than (D)MTC1 $0. */
3880 && outer_code == SET
3881 && !(float_mode_p && TARGET_HARD_FLOAT))
3883 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3884 want to CSE the constant itself. It is usually better to
3885 have N copies of the last operation in the sequence and one
3886 shared copy of the other operations. (Note that this is
3887 not true for MIPS16 code, where the final operation in the
3888 sequence is often an extended instruction.)
3890 Also, if we have a CONST_INT, we don't know whether it is
3891 for a word or doubleword operation, so we cannot rely on
3892 the result of mips_build_integer. */
3893 else if (!TARGET_MIPS16
3894 && (outer_code == SET || mode == VOIDmode))
3896 *total = COSTS_N_INSNS (cost);
3899 /* The value will need to be fetched from the constant pool. */
3900 *total = CONSTANT_POOL_COST;
3904 /* If the address is legitimate, return the number of
3905 instructions it needs. */
3907 cost = mips_address_insns (addr, mode, true);
3910 *total = COSTS_N_INSNS (cost + 1);
3913 /* Check for a scaled indexed address. */
3914 if (mips_lwxs_address_p (addr)
3915 || mips_lx_address_p (addr, mode))
3917 *total = COSTS_N_INSNS (2);
3920 /* Otherwise use the default handling. */
3924 *total = COSTS_N_INSNS (6);
3928 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1);
3932 /* Check for a *clear_upper32 pattern and treat it like a zero
3933 extension. See the pattern's comment for details. */
3936 && CONST_INT_P (XEXP (x, 1))
3937 && UINTVAL (XEXP (x, 1)) == 0xffffffff)
3939 *total = (mips_zero_extend_cost (mode, XEXP (x, 0))
3940 + set_src_cost (XEXP (x, 0), speed));
3943 if (ISA_HAS_CINS && CONST_INT_P (XEXP (x, 1)))
3945 rtx op = XEXP (x, 0);
3946 if (GET_CODE (op) == ASHIFT
3947 && CONST_INT_P (XEXP (op, 1))
3948 && mask_low_and_shift_p (mode, XEXP (x, 1), XEXP (op, 1), 32))
3950 *total = COSTS_N_INSNS (1) + set_src_cost (XEXP (op, 0), speed);
3954 /* (AND (NOT op0) (NOT op1) is a nor operation that can be done in
3955 a single instruction. */
3957 && GET_CODE (XEXP (x, 0)) == NOT
3958 && GET_CODE (XEXP (x, 1)) == NOT)
3960 cost = GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1;
3961 *total = (COSTS_N_INSNS (cost)
3962 + set_src_cost (XEXP (XEXP (x, 0), 0), speed)
3963 + set_src_cost (XEXP (XEXP (x, 1), 0), speed));
3971 /* Double-word operations use two single-word operations. */
3972 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (2),
3981 if (CONSTANT_P (XEXP (x, 1)))
3982 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3985 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (12),
3991 *total = mips_cost->fp_add;
3993 *total = COSTS_N_INSNS (4);
3997 /* Low-part immediates need an extended MIPS16 instruction. */
3998 *total = (COSTS_N_INSNS (TARGET_MIPS16 ? 2 : 1)
3999 + set_src_cost (XEXP (x, 0), speed));
4014 /* Branch comparisons have VOIDmode, so use the first operand's
4016 mode = GET_MODE (XEXP (x, 0));
4017 if (FLOAT_MODE_P (mode))
4019 *total = mips_cost->fp_add;
4022 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
4028 && (ISA_HAS_NMADD4_NMSUB4 || ISA_HAS_NMADD3_NMSUB3)
4029 && TARGET_FUSED_MADD
4030 && !HONOR_NANS (mode)
4031 && !HONOR_SIGNED_ZEROS (mode))
4033 /* See if we can use NMADD or NMSUB. See mips.md for the
4034 associated patterns. */
4035 rtx op0 = XEXP (x, 0);
4036 rtx op1 = XEXP (x, 1);
4037 if (GET_CODE (op0) == MULT && GET_CODE (XEXP (op0, 0)) == NEG)
4039 *total = (mips_fp_mult_cost (mode)
4040 + set_src_cost (XEXP (XEXP (op0, 0), 0), speed)
4041 + set_src_cost (XEXP (op0, 1), speed)
4042 + set_src_cost (op1, speed));
4045 if (GET_CODE (op1) == MULT)
4047 *total = (mips_fp_mult_cost (mode)
4048 + set_src_cost (op0, speed)
4049 + set_src_cost (XEXP (op1, 0), speed)
4050 + set_src_cost (XEXP (op1, 1), speed));
4059 /* If this is part of a MADD or MSUB, treat the PLUS as
4061 if ((ISA_HAS_FP_MADD4_MSUB4 || ISA_HAS_FP_MADD3_MSUB3)
4062 && TARGET_FUSED_MADD
4063 && GET_CODE (XEXP (x, 0)) == MULT)
4066 *total = mips_cost->fp_add;
4070 /* Double-word operations require three single-word operations and
4071 an SLTU. The MIPS16 version then needs to move the result of
4072 the SLTU from $24 to a MIPS16 register. */
4073 *total = mips_binary_cost (x, COSTS_N_INSNS (1),
4074 COSTS_N_INSNS (TARGET_MIPS16 ? 5 : 4),
4080 && (ISA_HAS_NMADD4_NMSUB4 || ISA_HAS_NMADD3_NMSUB3)
4081 && TARGET_FUSED_MADD
4082 && !HONOR_NANS (mode)
4083 && HONOR_SIGNED_ZEROS (mode))
4085 /* See if we can use NMADD or NMSUB. See mips.md for the
4086 associated patterns. */
4087 rtx op = XEXP (x, 0);
4088 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
4089 && GET_CODE (XEXP (op, 0)) == MULT)
4091 *total = (mips_fp_mult_cost (mode)
4092 + set_src_cost (XEXP (XEXP (op, 0), 0), speed)
4093 + set_src_cost (XEXP (XEXP (op, 0), 1), speed)
4094 + set_src_cost (XEXP (op, 1), speed));
4100 *total = mips_cost->fp_add;
4102 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1);
4107 *total = mips_fp_mult_cost (mode);
4108 else if (mode == DImode && !TARGET_64BIT)
4109 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
4110 where the mulsidi3 always includes an MFHI and an MFLO. */
4112 ? mips_cost->int_mult_si * 3 + 6
4113 : COSTS_N_INSNS (ISA_HAS_MUL3 ? 7 : 9));
4115 *total = COSTS_N_INSNS (ISA_HAS_MUL3 ? 1 : 2) + 1;
4116 else if (mode == DImode)
4117 *total = mips_cost->int_mult_di;
4119 *total = mips_cost->int_mult_si;
4123 /* Check for a reciprocal. */
4125 && ISA_HAS_FP_RECIP_RSQRT (mode)
4126 && flag_unsafe_math_optimizations
4127 && XEXP (x, 0) == CONST1_RTX (mode))
4129 if (outer_code == SQRT || GET_CODE (XEXP (x, 1)) == SQRT)
4130 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
4131 division as being free. */
4132 *total = set_src_cost (XEXP (x, 1), speed);
4134 *total = (mips_fp_div_cost (mode)
4135 + set_src_cost (XEXP (x, 1), speed));
4144 *total = mips_fp_div_cost (mode);
4153 /* It is our responsibility to make division by a power of 2
4154 as cheap as 2 register additions if we want the division
4155 expanders to be used for such operations; see the setting
4156 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
4157 should always produce shorter code than using
4158 expand_sdiv2_pow2. */
4160 && CONST_INT_P (XEXP (x, 1))
4161 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
4163 *total = COSTS_N_INSNS (2) + set_src_cost (XEXP (x, 0), speed);
4166 *total = COSTS_N_INSNS (mips_idiv_insns ());
4168 else if (mode == DImode)
4169 *total = mips_cost->int_div_di;
4171 *total = mips_cost->int_div_si;
4175 *total = mips_sign_extend_cost (mode, XEXP (x, 0));
4179 if (outer_code == SET
4181 && (GET_CODE (XEXP (x, 0)) == TRUNCATE
4182 || GET_CODE (XEXP (x, 0)) == SUBREG)
4183 && GET_MODE (XEXP (x, 0)) == QImode
4184 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
4186 *total = set_src_cost (XEXP (XEXP (x, 0), 0), speed);
4189 *total = mips_zero_extend_cost (mode, XEXP (x, 0));
4193 case UNSIGNED_FLOAT:
4196 case FLOAT_TRUNCATE:
4197 *total = mips_cost->fp_add;
4201 if (register_operand (SET_DEST (x), VOIDmode)
4202 && reg_or_0_operand (SET_SRC (x), VOIDmode))
4204 *total = mips_set_reg_reg_cost (GET_MODE (SET_DEST (x)));
4214 /* Implement TARGET_ADDRESS_COST. */
4217 mips_address_cost (rtx addr, machine_mode mode,
4218 addr_space_t as ATTRIBUTE_UNUSED,
4219 bool speed ATTRIBUTE_UNUSED)
4221 return mips_address_insns (addr, mode, false);
4224 /* Information about a single instruction in a multi-instruction
4226 struct mips_multi_member {
4227 /* True if this is a label, false if it is code. */
4230 /* The output_asm_insn format of the instruction. */
4233 /* The operands to the instruction. */
4234 rtx operands[MAX_RECOG_OPERANDS];
4236 typedef struct mips_multi_member mips_multi_member;
4238 /* The instructions that make up the current multi-insn sequence. */
4239 static vec<mips_multi_member> mips_multi_members;
4241 /* How many instructions (as opposed to labels) are in the current
4242 multi-insn sequence. */
4243 static unsigned int mips_multi_num_insns;
4245 /* Start a new multi-insn sequence. */
4248 mips_multi_start (void)
4250 mips_multi_members.truncate (0);
4251 mips_multi_num_insns = 0;
4254 /* Add a new, uninitialized member to the current multi-insn sequence. */
4256 static struct mips_multi_member *
4257 mips_multi_add (void)
4259 mips_multi_member empty;
4260 return mips_multi_members.safe_push (empty);
4263 /* Add a normal insn with the given asm format to the current multi-insn
4264 sequence. The other arguments are a null-terminated list of operands. */
4267 mips_multi_add_insn (const char *format, ...)
4269 struct mips_multi_member *member;
4274 member = mips_multi_add ();
4275 member->is_label_p = false;
4276 member->format = format;
4277 va_start (ap, format);
4279 while ((op = va_arg (ap, rtx)))
4280 member->operands[i++] = op;
4282 mips_multi_num_insns++;
4285 /* Add the given label definition to the current multi-insn sequence.
4286 The definition should include the colon. */
4289 mips_multi_add_label (const char *label)
4291 struct mips_multi_member *member;
4293 member = mips_multi_add ();
4294 member->is_label_p = true;
4295 member->format = label;
4298 /* Return the index of the last member of the current multi-insn sequence. */
4301 mips_multi_last_index (void)
4303 return mips_multi_members.length () - 1;
4306 /* Add a copy of an existing instruction to the current multi-insn
4307 sequence. I is the index of the instruction that should be copied. */
4310 mips_multi_copy_insn (unsigned int i)
4312 struct mips_multi_member *member;
4314 member = mips_multi_add ();
4315 memcpy (member, &mips_multi_members[i], sizeof (*member));
4316 gcc_assert (!member->is_label_p);
4319 /* Change the operand of an existing instruction in the current
4320 multi-insn sequence. I is the index of the instruction,
4321 OP is the index of the operand, and X is the new value. */
4324 mips_multi_set_operand (unsigned int i, unsigned int op, rtx x)
4326 mips_multi_members[i].operands[op] = x;
4329 /* Write out the asm code for the current multi-insn sequence. */
4332 mips_multi_write (void)
4334 struct mips_multi_member *member;
4337 FOR_EACH_VEC_ELT (mips_multi_members, i, member)
4338 if (member->is_label_p)
4339 fprintf (asm_out_file, "%s\n", member->format);
4341 output_asm_insn (member->format, member->operands);
4344 /* Return one word of double-word value OP, taking into account the fixed
4345 endianness of certain registers. HIGH_P is true to select the high part,
4346 false to select the low part. */
4349 mips_subword (rtx op, bool high_p)
4351 unsigned int byte, offset;
4354 mode = GET_MODE (op);
4355 if (mode == VOIDmode)
4356 mode = TARGET_64BIT ? TImode : DImode;
4358 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
4359 byte = UNITS_PER_WORD;
4363 if (FP_REG_RTX_P (op))
4365 /* Paired FPRs are always ordered little-endian. */
4366 offset = (UNITS_PER_WORD < UNITS_PER_HWFPVALUE ? high_p : byte != 0);
4367 return gen_rtx_REG (word_mode, REGNO (op) + offset);
4371 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
4373 return simplify_gen_subreg (word_mode, op, mode, byte);
4376 /* Return true if SRC should be moved into DEST using "MULT $0, $0".
4377 SPLIT_TYPE is the condition under which moves should be split. */
4380 mips_mult_move_p (rtx dest, rtx src, enum mips_split_type split_type)
4382 return ((split_type != SPLIT_FOR_SPEED
4383 || mips_tuning_info.fast_mult_zero_zero_p)
4384 && src == const0_rtx
4386 && GET_MODE_SIZE (GET_MODE (dest)) == 2 * UNITS_PER_WORD
4387 && (ISA_HAS_DSP_MULT
4388 ? ACC_REG_P (REGNO (dest))
4389 : MD_REG_P (REGNO (dest))));
4392 /* Return true if a move from SRC to DEST should be split into two.
4393 SPLIT_TYPE describes the split condition. */
4396 mips_split_move_p (rtx dest, rtx src, enum mips_split_type split_type)
4398 /* Check whether the move can be done using some variant of MULT $0,$0. */
4399 if (mips_mult_move_p (dest, src, split_type))
4402 /* FPR-to-FPR moves can be done in a single instruction, if they're
4404 unsigned int size = GET_MODE_SIZE (GET_MODE (dest));
4405 if (size == 8 && FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
4408 /* Check for floating-point loads and stores. */
4409 if (size == 8 && ISA_HAS_LDC1_SDC1)
4411 if (FP_REG_RTX_P (dest) && MEM_P (src))
4413 if (FP_REG_RTX_P (src) && MEM_P (dest))
4417 /* Otherwise split all multiword moves. */
4418 return size > UNITS_PER_WORD;
4421 /* Split a move from SRC to DEST, given that mips_split_move_p holds.
4422 SPLIT_TYPE describes the split condition. */
4425 mips_split_move (rtx dest, rtx src, enum mips_split_type split_type)
4429 gcc_checking_assert (mips_split_move_p (dest, src, split_type));
4430 if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src))
4432 if (!TARGET_64BIT && GET_MODE (dest) == DImode)
4433 emit_insn (gen_move_doubleword_fprdi (dest, src));
4434 else if (!TARGET_64BIT && GET_MODE (dest) == DFmode)
4435 emit_insn (gen_move_doubleword_fprdf (dest, src));
4436 else if (!TARGET_64BIT && GET_MODE (dest) == V2SFmode)
4437 emit_insn (gen_move_doubleword_fprv2sf (dest, src));
4438 else if (!TARGET_64BIT && GET_MODE (dest) == V2SImode)
4439 emit_insn (gen_move_doubleword_fprv2si (dest, src));
4440 else if (!TARGET_64BIT && GET_MODE (dest) == V4HImode)
4441 emit_insn (gen_move_doubleword_fprv4hi (dest, src));
4442 else if (!TARGET_64BIT && GET_MODE (dest) == V8QImode)
4443 emit_insn (gen_move_doubleword_fprv8qi (dest, src));
4444 else if (TARGET_64BIT && GET_MODE (dest) == TFmode)
4445 emit_insn (gen_move_doubleword_fprtf (dest, src));
4449 else if (REG_P (dest) && REGNO (dest) == MD_REG_FIRST)
4451 low_dest = mips_subword (dest, false);
4452 mips_emit_move (low_dest, mips_subword (src, false));
4454 emit_insn (gen_mthidi_ti (dest, mips_subword (src, true), low_dest));
4456 emit_insn (gen_mthisi_di (dest, mips_subword (src, true), low_dest));
4458 else if (REG_P (src) && REGNO (src) == MD_REG_FIRST)
4460 mips_emit_move (mips_subword (dest, false), mips_subword (src, false));
4462 emit_insn (gen_mfhidi_ti (mips_subword (dest, true), src));
4464 emit_insn (gen_mfhisi_di (mips_subword (dest, true), src));
4468 /* The operation can be split into two normal moves. Decide in
4469 which order to do them. */
4470 low_dest = mips_subword (dest, false);
4471 if (REG_P (low_dest)
4472 && reg_overlap_mentioned_p (low_dest, src))
4474 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4475 mips_emit_move (low_dest, mips_subword (src, false));
4479 mips_emit_move (low_dest, mips_subword (src, false));
4480 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4485 /* Return the split type for instruction INSN. */
4487 static enum mips_split_type
4488 mips_insn_split_type (rtx insn)
4490 basic_block bb = BLOCK_FOR_INSN (insn);
4493 if (optimize_bb_for_speed_p (bb))
4494 return SPLIT_FOR_SPEED;
4496 return SPLIT_FOR_SIZE;
4498 /* Once CFG information has been removed, we should trust the optimization
4499 decisions made by previous passes and only split where necessary. */
4500 return SPLIT_IF_NECESSARY;
4503 /* Return true if a move from SRC to DEST in INSN should be split. */
4506 mips_split_move_insn_p (rtx dest, rtx src, rtx insn)
4508 return mips_split_move_p (dest, src, mips_insn_split_type (insn));
4511 /* Split a move from SRC to DEST in INSN, given that mips_split_move_insn_p
4515 mips_split_move_insn (rtx dest, rtx src, rtx insn)
4517 mips_split_move (dest, src, mips_insn_split_type (insn));
4520 /* Return the appropriate instructions to move SRC into DEST. Assume
4521 that SRC is operand 1 and DEST is operand 0. */
4524 mips_output_move (rtx dest, rtx src)
4526 enum rtx_code dest_code, src_code;
4528 enum mips_symbol_type symbol_type;
4531 dest_code = GET_CODE (dest);
4532 src_code = GET_CODE (src);
4533 mode = GET_MODE (dest);
4534 dbl_p = (GET_MODE_SIZE (mode) == 8);
4536 if (mips_split_move_p (dest, src, SPLIT_IF_NECESSARY))
4539 if ((src_code == REG && GP_REG_P (REGNO (src)))
4540 || (!TARGET_MIPS16 && src == CONST0_RTX (mode)))
4542 if (dest_code == REG)
4544 if (GP_REG_P (REGNO (dest)))
4545 return "move\t%0,%z1";
4547 if (mips_mult_move_p (dest, src, SPLIT_IF_NECESSARY))
4549 if (ISA_HAS_DSP_MULT)
4550 return "mult\t%q0,%.,%.";
4552 return "mult\t%.,%.";
4555 /* Moves to HI are handled by special .md insns. */
4556 if (REGNO (dest) == LO_REGNUM)
4559 if (DSP_ACC_REG_P (REGNO (dest)))
4561 static char retval[] = "mt__\t%z1,%q0";
4563 retval[2] = reg_names[REGNO (dest)][4];
4564 retval[3] = reg_names[REGNO (dest)][5];
4568 if (FP_REG_P (REGNO (dest)))
4569 return dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
4571 if (ALL_COP_REG_P (REGNO (dest)))
4573 static char retval[] = "dmtc_\t%z1,%0";
4575 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4576 return dbl_p ? retval : retval + 1;
4579 if (dest_code == MEM)
4580 switch (GET_MODE_SIZE (mode))
4582 case 1: return "sb\t%z1,%0";
4583 case 2: return "sh\t%z1,%0";
4584 case 4: return "sw\t%z1,%0";
4585 case 8: return "sd\t%z1,%0";
4588 if (dest_code == REG && GP_REG_P (REGNO (dest)))
4590 if (src_code == REG)
4592 /* Moves from HI are handled by special .md insns. */
4593 if (REGNO (src) == LO_REGNUM)
4595 /* When generating VR4120 or VR4130 code, we use MACC and
4596 DMACC instead of MFLO. This avoids both the normal
4597 MIPS III HI/LO hazards and the errata related to
4600 return dbl_p ? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
4604 if (DSP_ACC_REG_P (REGNO (src)))
4606 static char retval[] = "mf__\t%0,%q1";
4608 retval[2] = reg_names[REGNO (src)][4];
4609 retval[3] = reg_names[REGNO (src)][5];
4613 if (FP_REG_P (REGNO (src)))
4614 return dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
4616 if (ALL_COP_REG_P (REGNO (src)))
4618 static char retval[] = "dmfc_\t%0,%1";
4620 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4621 return dbl_p ? retval : retval + 1;
4625 if (src_code == MEM)
4626 switch (GET_MODE_SIZE (mode))
4628 case 1: return "lbu\t%0,%1";
4629 case 2: return "lhu\t%0,%1";
4630 case 4: return "lw\t%0,%1";
4631 case 8: return "ld\t%0,%1";
4634 if (src_code == CONST_INT)
4636 /* Don't use the X format for the operand itself, because that
4637 will give out-of-range numbers for 64-bit hosts and 32-bit
4640 return "li\t%0,%1\t\t\t# %X1";
4642 if (SMALL_OPERAND_UNSIGNED (INTVAL (src)))
4645 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src)))
4649 if (src_code == HIGH)
4650 return TARGET_MIPS16 ? "#" : "lui\t%0,%h1";
4652 if (CONST_GP_P (src))
4653 return "move\t%0,%1";
4655 if (mips_symbolic_constant_p (src, SYMBOL_CONTEXT_LEA, &symbol_type)
4656 && mips_lo_relocs[symbol_type] != 0)
4658 /* A signed 16-bit constant formed by applying a relocation
4659 operator to a symbolic address. */
4660 gcc_assert (!mips_split_p[symbol_type]);
4661 return "li\t%0,%R1";
4664 if (symbolic_operand (src, VOIDmode))
4666 gcc_assert (TARGET_MIPS16
4667 ? TARGET_MIPS16_TEXT_LOADS
4668 : !TARGET_EXPLICIT_RELOCS);
4669 return dbl_p ? "dla\t%0,%1" : "la\t%0,%1";
4672 if (src_code == REG && FP_REG_P (REGNO (src)))
4674 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4676 if (GET_MODE (dest) == V2SFmode)
4677 return "mov.ps\t%0,%1";
4679 return dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1";
4682 if (dest_code == MEM)
4683 return dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0";
4685 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4687 if (src_code == MEM)
4688 return dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1";
4690 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
4692 static char retval[] = "l_c_\t%0,%1";
4694 retval[1] = (dbl_p ? 'd' : 'w');
4695 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4698 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
4700 static char retval[] = "s_c_\t%1,%0";
4702 retval[1] = (dbl_p ? 'd' : 'w');
4703 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4709 /* Return true if CMP1 is a suitable second operand for integer ordering
4710 test CODE. See also the *sCC patterns in mips.md. */
4713 mips_int_order_operand_ok_p (enum rtx_code code, rtx cmp1)
4719 return reg_or_0_operand (cmp1, VOIDmode);
4723 return !TARGET_MIPS16 && cmp1 == const1_rtx;
4727 return arith_operand (cmp1, VOIDmode);
4730 return sle_operand (cmp1, VOIDmode);
4733 return sleu_operand (cmp1, VOIDmode);
4740 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4741 integer ordering test *CODE, or if an equivalent combination can
4742 be formed by adjusting *CODE and *CMP1. When returning true, update
4743 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4747 mips_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1,
4750 HOST_WIDE_INT plus_one;
4752 if (mips_int_order_operand_ok_p (*code, *cmp1))
4755 if (CONST_INT_P (*cmp1))
4759 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4760 if (INTVAL (*cmp1) < plus_one)
4763 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4769 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4773 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4784 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4785 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4786 is nonnull, it's OK to set TARGET to the inverse of the result and
4787 flip *INVERT_PTR instead. */
4790 mips_emit_int_order_test (enum rtx_code code, bool *invert_ptr,
4791 rtx target, rtx cmp0, rtx cmp1)
4795 /* First see if there is a MIPS instruction that can do this operation.
4796 If not, try doing the same for the inverse operation. If that also
4797 fails, force CMP1 into a register and try again. */
4798 mode = GET_MODE (cmp0);
4799 if (mips_canonicalize_int_order_test (&code, &cmp1, mode))
4800 mips_emit_binary (code, target, cmp0, cmp1);
4803 enum rtx_code inv_code = reverse_condition (code);
4804 if (!mips_canonicalize_int_order_test (&inv_code, &cmp1, mode))
4806 cmp1 = force_reg (mode, cmp1);
4807 mips_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1);
4809 else if (invert_ptr == 0)
4813 inv_target = mips_force_binary (GET_MODE (target),
4814 inv_code, cmp0, cmp1);
4815 mips_emit_binary (XOR, target, inv_target, const1_rtx);
4819 *invert_ptr = !*invert_ptr;
4820 mips_emit_binary (inv_code, target, cmp0, cmp1);
4825 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4826 The register will have the same mode as CMP0. */
4829 mips_zero_if_equal (rtx cmp0, rtx cmp1)
4831 if (cmp1 == const0_rtx)
4834 if (uns_arith_operand (cmp1, VOIDmode))
4835 return expand_binop (GET_MODE (cmp0), xor_optab,
4836 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4838 return expand_binop (GET_MODE (cmp0), sub_optab,
4839 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4842 /* Convert *CODE into a code that can be used in a floating-point
4843 scc instruction (C.cond.fmt). Return true if the values of
4844 the condition code registers will be inverted, with 0 indicating
4845 that the condition holds. */
4848 mips_reversed_fp_cond (enum rtx_code *code)
4855 *code = reverse_condition_maybe_unordered (*code);
4863 /* Allocate a floating-point condition-code register of mode MODE.
4865 These condition code registers are used for certain kinds
4866 of compound operation, such as compare and branches, vconds,
4867 and built-in functions. At expand time, their use is entirely
4868 controlled by MIPS-specific code and is entirely internal
4869 to these compound operations.
4871 We could (and did in the past) expose condition-code values
4872 as pseudo registers and leave the register allocator to pick
4873 appropriate registers. The problem is that it is not practically
4874 possible for the rtl optimizers to guarantee that no spills will
4875 be needed, even when AVOID_CCMODE_COPIES is defined. We would
4876 therefore need spill and reload sequences to handle the worst case.
4878 Although such sequences do exist, they are very expensive and are
4879 not something we'd want to use. This is especially true of CCV2 and
4880 CCV4, where all the shuffling would greatly outweigh whatever benefit
4881 the vectorization itself provides.
4883 The main benefit of having more than one condition-code register
4884 is to allow the pipelining of operations, especially those involving
4885 comparisons and conditional moves. We don't really expect the
4886 registers to be live for long periods, and certainly never want
4887 them to be live across calls.
4889 Also, there should be no penalty attached to using all the available
4890 registers. They are simply bits in the same underlying FPU control
4893 We therefore expose the hardware registers from the outset and use
4894 a simple round-robin allocation scheme. */
4897 mips_allocate_fcc (machine_mode mode)
4899 unsigned int regno, count;
4901 gcc_assert (TARGET_HARD_FLOAT && ISA_HAS_8CC);
4905 else if (mode == CCV2mode)
4907 else if (mode == CCV4mode)
4912 cfun->machine->next_fcc += -cfun->machine->next_fcc & (count - 1);
4913 if (cfun->machine->next_fcc > ST_REG_LAST - ST_REG_FIRST)
4914 cfun->machine->next_fcc = 0;
4915 regno = ST_REG_FIRST + cfun->machine->next_fcc;
4916 cfun->machine->next_fcc += count;
4917 return gen_rtx_REG (mode, regno);
4920 /* Convert a comparison into something that can be used in a branch or
4921 conditional move. On entry, *OP0 and *OP1 are the values being
4922 compared and *CODE is the code used to compare them.
4924 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
4925 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
4926 otherwise any standard branch condition can be used. The standard branch
4929 - EQ or NE between two registers.
4930 - any comparison between a register and zero. */
4933 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
4938 if (GET_MODE_CLASS (GET_MODE (*op0)) == MODE_INT)
4940 if (!need_eq_ne_p && *op1 == const0_rtx)
4942 else if (*code == EQ || *code == NE)
4946 *op0 = mips_zero_if_equal (cmp_op0, cmp_op1);
4950 *op1 = force_reg (GET_MODE (cmp_op0), cmp_op1);
4954 /* The comparison needs a separate scc instruction. Store the
4955 result of the scc in *OP0 and compare it against zero. */
4956 bool invert = false;
4957 *op0 = gen_reg_rtx (GET_MODE (cmp_op0));
4958 mips_emit_int_order_test (*code, &invert, *op0, cmp_op0, cmp_op1);
4959 *code = (invert ? EQ : NE);
4963 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0)))
4965 *op0 = gen_rtx_REG (CCDSPmode, CCDSP_CC_REGNUM);
4966 mips_emit_binary (*code, *op0, cmp_op0, cmp_op1);
4972 enum rtx_code cmp_code;
4974 /* Floating-point tests use a separate C.cond.fmt comparison to
4975 set a condition code register. The branch or conditional move
4976 will then compare that register against zero.
4978 Set CMP_CODE to the code of the comparison instruction and
4979 *CODE to the code that the branch or move should use. */
4981 *code = mips_reversed_fp_cond (&cmp_code) ? EQ : NE;
4983 ? mips_allocate_fcc (CCmode)
4984 : gen_rtx_REG (CCmode, FPSW_REGNUM));
4986 mips_emit_binary (cmp_code, *op0, cmp_op0, cmp_op1);
4990 /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2]
4991 and OPERAND[3]. Store the result in OPERANDS[0].
4993 On 64-bit targets, the mode of the comparison and target will always be
4994 SImode, thus possibly narrower than that of the comparison's operands. */
4997 mips_expand_scc (rtx operands[])
4999 rtx target = operands[0];
5000 enum rtx_code code = GET_CODE (operands[1]);
5001 rtx op0 = operands[2];
5002 rtx op1 = operands[3];
5004 gcc_assert (GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT);
5006 if (code == EQ || code == NE)
5009 && reg_imm10_operand (op1, GET_MODE (op1)))
5010 mips_emit_binary (code, target, op0, op1);
5013 rtx zie = mips_zero_if_equal (op0, op1);
5014 mips_emit_binary (code, target, zie, const0_rtx);
5018 mips_emit_int_order_test (code, 0, target, op0, op1);
5021 /* Compare OPERANDS[1] with OPERANDS[2] using comparison code
5022 CODE and jump to OPERANDS[3] if the condition holds. */
5025 mips_expand_conditional_branch (rtx *operands)
5027 enum rtx_code code = GET_CODE (operands[0]);
5028 rtx op0 = operands[1];
5029 rtx op1 = operands[2];
5032 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
5033 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
5034 emit_jump_insn (gen_condjump (condition, operands[3]));
5039 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
5040 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
5043 mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
5044 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
5049 reversed_p = mips_reversed_fp_cond (&cond);
5050 cmp_result = mips_allocate_fcc (CCV2mode);
5051 emit_insn (gen_scc_ps (cmp_result,
5052 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
5054 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
5057 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
5061 /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0]
5062 if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
5065 mips_expand_conditional_move (rtx *operands)
5068 enum rtx_code code = GET_CODE (operands[1]);
5069 rtx op0 = XEXP (operands[1], 0);
5070 rtx op1 = XEXP (operands[1], 1);
5072 mips_emit_compare (&code, &op0, &op1, true);
5073 cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
5074 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
5075 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), cond,
5076 operands[2], operands[3])));
5079 /* Perform the comparison in COMPARISON, then trap if the condition holds. */
5082 mips_expand_conditional_trap (rtx comparison)
5088 /* MIPS conditional trap instructions don't have GT or LE flavors,
5089 so we must swap the operands and convert to LT and GE respectively. */
5090 code = GET_CODE (comparison);
5097 code = swap_condition (code);
5098 op0 = XEXP (comparison, 1);
5099 op1 = XEXP (comparison, 0);
5103 op0 = XEXP (comparison, 0);
5104 op1 = XEXP (comparison, 1);
5108 mode = GET_MODE (XEXP (comparison, 0));
5109 op0 = force_reg (mode, op0);
5110 if (!arith_operand (op1, mode))
5111 op1 = force_reg (mode, op1);
5113 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
5114 gen_rtx_fmt_ee (code, mode, op0, op1),
5118 /* Initialize *CUM for a call to a function of type FNTYPE. */
5121 mips_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype)
5123 memset (cum, 0, sizeof (*cum));
5124 cum->prototype = (fntype && prototype_p (fntype));
5125 cum->gp_reg_found = (cum->prototype && stdarg_p (fntype));
5128 /* Fill INFO with information about a single argument. CUM is the
5129 cumulative state for earlier arguments. MODE is the mode of this
5130 argument and TYPE is its type (if known). NAMED is true if this
5131 is a named (fixed) argument rather than a variable one. */
5134 mips_get_arg_info (struct mips_arg_info *info, const CUMULATIVE_ARGS *cum,
5135 machine_mode mode, const_tree type, bool named)
5137 bool doubleword_aligned_p;
5138 unsigned int num_bytes, num_words, max_regs;
5140 /* Work out the size of the argument. */
5141 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
5142 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5144 /* Decide whether it should go in a floating-point register, assuming
5145 one is free. Later code checks for availability.
5147 The checks against UNITS_PER_FPVALUE handle the soft-float and
5148 single-float cases. */
5152 /* The EABI conventions have traditionally been defined in terms
5153 of TYPE_MODE, regardless of the actual type. */
5154 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
5155 || mode == V2SFmode)
5156 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
5161 /* Only leading floating-point scalars are passed in
5162 floating-point registers. We also handle vector floats the same
5163 say, which is OK because they are not covered by the standard ABI. */
5164 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT || mode != V2SFmode);
5165 info->fpr_p = (!cum->gp_reg_found
5166 && cum->arg_number < 2
5168 || SCALAR_FLOAT_TYPE_P (type)
5169 || VECTOR_FLOAT_TYPE_P (type))
5170 && (GET_MODE_CLASS (mode) == MODE_FLOAT
5171 || mode == V2SFmode)
5172 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
5177 /* Scalar, complex and vector floating-point types are passed in
5178 floating-point registers, as long as this is a named rather
5179 than a variable argument. */
5180 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT || mode != V2SFmode);
5181 info->fpr_p = (named
5182 && (type == 0 || FLOAT_TYPE_P (type))
5183 && (GET_MODE_CLASS (mode) == MODE_FLOAT
5184 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5185 || mode == V2SFmode)
5186 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
5188 /* ??? According to the ABI documentation, the real and imaginary
5189 parts of complex floats should be passed in individual registers.
5190 The real and imaginary parts of stack arguments are supposed
5191 to be contiguous and there should be an extra word of padding
5194 This has two problems. First, it makes it impossible to use a
5195 single "void *" va_list type, since register and stack arguments
5196 are passed differently. (At the time of writing, MIPSpro cannot
5197 handle complex float varargs correctly.) Second, it's unclear
5198 what should happen when there is only one register free.
5200 For now, we assume that named complex floats should go into FPRs
5201 if there are two FPRs free, otherwise they should be passed in the
5202 same way as a struct containing two floats. */
5204 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5205 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
5207 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
5208 info->fpr_p = false;
5218 /* See whether the argument has doubleword alignment. */
5219 doubleword_aligned_p = (mips_function_arg_boundary (mode, type)
5222 /* Set REG_OFFSET to the register count we're interested in.
5223 The EABI allocates the floating-point registers separately,
5224 but the other ABIs allocate them like integer registers. */
5225 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
5229 /* Advance to an even register if the argument is doubleword-aligned. */
5230 if (doubleword_aligned_p)
5231 info->reg_offset += info->reg_offset & 1;
5233 /* Work out the offset of a stack argument. */
5234 info->stack_offset = cum->stack_words;
5235 if (doubleword_aligned_p)
5236 info->stack_offset += info->stack_offset & 1;
5238 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
5240 /* Partition the argument between registers and stack. */
5241 info->reg_words = MIN (num_words, max_regs);
5242 info->stack_words = num_words - info->reg_words;
5245 /* INFO describes a register argument that has the normal format for the
5246 argument's mode. Return the register it uses, assuming that FPRs are
5247 available if HARD_FLOAT_P. */
5250 mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p)
5252 if (!info->fpr_p || !hard_float_p)
5253 return GP_ARG_FIRST + info->reg_offset;
5254 else if (mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info->reg_offset > 0)
5255 /* In o32, the second argument is always passed in $f14
5256 for TARGET_DOUBLE_FLOAT, regardless of whether the
5257 first argument was a word or doubleword. */
5258 return FP_ARG_FIRST + 2;
5260 return FP_ARG_FIRST + info->reg_offset;
5263 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
5266 mips_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED)
5268 return !TARGET_OLDABI;
5271 /* Implement TARGET_FUNCTION_ARG. */
5274 mips_function_arg (cumulative_args_t cum_v, machine_mode mode,
5275 const_tree type, bool named)
5277 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
5278 struct mips_arg_info info;
5280 /* We will be called with a mode of VOIDmode after the last argument
5281 has been seen. Whatever we return will be passed to the call expander.
5282 If we need a MIPS16 fp_code, return a REG with the code stored as
5284 if (mode == VOIDmode)
5286 if (TARGET_MIPS16 && cum->fp_code != 0)
5287 return gen_rtx_REG ((machine_mode) cum->fp_code, 0);
5292 mips_get_arg_info (&info, cum, mode, type, named);
5294 /* Return straight away if the whole argument is passed on the stack. */
5295 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
5298 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
5299 contains a double in its entirety, then that 64-bit chunk is passed
5300 in a floating-point register. */
5302 && TARGET_HARD_FLOAT
5305 && TREE_CODE (type) == RECORD_TYPE
5306 && TYPE_SIZE_UNIT (type)
5307 && tree_fits_uhwi_p (TYPE_SIZE_UNIT (type)))
5311 /* First check to see if there is any such field. */
5312 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
5313 if (TREE_CODE (field) == FIELD_DECL
5314 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
5315 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
5316 && tree_fits_shwi_p (bit_position (field))
5317 && int_bit_position (field) % BITS_PER_WORD == 0)
5322 /* Now handle the special case by returning a PARALLEL
5323 indicating where each 64-bit chunk goes. INFO.REG_WORDS
5324 chunks are passed in registers. */
5326 HOST_WIDE_INT bitpos;
5329 /* assign_parms checks the mode of ENTRY_PARM, so we must
5330 use the actual mode here. */
5331 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
5334 field = TYPE_FIELDS (type);
5335 for (i = 0; i < info.reg_words; i++)
5339 for (; field; field = DECL_CHAIN (field))
5340 if (TREE_CODE (field) == FIELD_DECL
5341 && int_bit_position (field) >= bitpos)
5345 && int_bit_position (field) == bitpos
5346 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
5347 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
5348 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
5350 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
5353 = gen_rtx_EXPR_LIST (VOIDmode, reg,
5354 GEN_INT (bitpos / BITS_PER_UNIT));
5356 bitpos += BITS_PER_WORD;
5362 /* Handle the n32/n64 conventions for passing complex floating-point
5363 arguments in FPR pairs. The real part goes in the lower register
5364 and the imaginary part goes in the upper register. */
5367 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5373 inner = GET_MODE_INNER (mode);
5374 regno = FP_ARG_FIRST + info.reg_offset;
5375 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
5377 /* Real part in registers, imaginary part on stack. */
5378 gcc_assert (info.stack_words == info.reg_words);
5379 return gen_rtx_REG (inner, regno);
5383 gcc_assert (info.stack_words == 0);
5384 real = gen_rtx_EXPR_LIST (VOIDmode,
5385 gen_rtx_REG (inner, regno),
5387 imag = gen_rtx_EXPR_LIST (VOIDmode,
5389 regno + info.reg_words / 2),
5390 GEN_INT (GET_MODE_SIZE (inner)));
5391 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
5395 return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT));
5398 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
5401 mips_function_arg_advance (cumulative_args_t cum_v, machine_mode mode,
5402 const_tree type, bool named)
5404 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
5405 struct mips_arg_info info;
5407 mips_get_arg_info (&info, cum, mode, type, named);
5410 cum->gp_reg_found = true;
5412 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
5413 an explanation of what this code does. It assumes that we're using
5414 either the o32 or the o64 ABI, both of which pass at most 2 arguments
5416 if (cum->arg_number < 2 && info.fpr_p)
5417 cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2);
5419 /* Advance the register count. This has the effect of setting
5420 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
5421 argument required us to skip the final GPR and pass the whole
5422 argument on the stack. */
5423 if (mips_abi != ABI_EABI || !info.fpr_p)
5424 cum->num_gprs = info.reg_offset + info.reg_words;
5425 else if (info.reg_words > 0)
5426 cum->num_fprs += MAX_FPRS_PER_FMT;
5428 /* Advance the stack word count. */
5429 if (info.stack_words > 0)
5430 cum->stack_words = info.stack_offset + info.stack_words;
5435 /* Implement TARGET_ARG_PARTIAL_BYTES. */
5438 mips_arg_partial_bytes (cumulative_args_t cum,
5439 machine_mode mode, tree type, bool named)
5441 struct mips_arg_info info;
5443 mips_get_arg_info (&info, get_cumulative_args (cum), mode, type, named);
5444 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
5447 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
5448 least PARM_BOUNDARY bits of alignment, but will be given anything up
5449 to STACK_BOUNDARY bits if the type requires it. */
5452 mips_function_arg_boundary (machine_mode mode, const_tree type)
5454 unsigned int alignment;
5456 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
5457 if (alignment < PARM_BOUNDARY)
5458 alignment = PARM_BOUNDARY;
5459 if (alignment > STACK_BOUNDARY)
5460 alignment = STACK_BOUNDARY;
5464 /* Implement TARGET_GET_RAW_RESULT_MODE and TARGET_GET_RAW_ARG_MODE. */
5467 mips_get_reg_raw_mode (int regno)
5469 if (TARGET_FLOATXX && FP_REG_P (regno))
5471 return default_get_reg_raw_mode (regno);
5474 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
5475 upward rather than downward. In other words, return true if the
5476 first byte of the stack slot has useful data, false if the last
5480 mips_pad_arg_upward (machine_mode mode, const_tree type)
5482 /* On little-endian targets, the first byte of every stack argument
5483 is passed in the first byte of the stack slot. */
5484 if (!BYTES_BIG_ENDIAN)
5487 /* Otherwise, integral types are padded downward: the last byte of a
5488 stack argument is passed in the last byte of the stack slot. */
5490 ? (INTEGRAL_TYPE_P (type)
5491 || POINTER_TYPE_P (type)
5492 || FIXED_POINT_TYPE_P (type))
5493 : (SCALAR_INT_MODE_P (mode)
5494 || ALL_SCALAR_FIXED_POINT_MODE_P (mode)))
5497 /* Big-endian o64 pads floating-point arguments downward. */
5498 if (mips_abi == ABI_O64)
5499 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
5502 /* Other types are padded upward for o32, o64, n32 and n64. */
5503 if (mips_abi != ABI_EABI)
5506 /* Arguments smaller than a stack slot are padded downward. */
5507 if (mode != BLKmode)
5508 return GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY;
5510 return int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT);
5513 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
5514 if the least significant byte of the register has useful data. Return
5515 the opposite if the most significant byte does. */
5518 mips_pad_reg_upward (machine_mode mode, tree type)
5520 /* No shifting is required for floating-point arguments. */
5521 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
5522 return !BYTES_BIG_ENDIAN;
5524 /* Otherwise, apply the same padding to register arguments as we do
5525 to stack arguments. */
5526 return mips_pad_arg_upward (mode, type);
5529 /* Return nonzero when an argument must be passed by reference. */
5532 mips_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
5533 machine_mode mode, const_tree type,
5534 bool named ATTRIBUTE_UNUSED)
5536 if (mips_abi == ABI_EABI)
5540 /* ??? How should SCmode be handled? */
5541 if (mode == DImode || mode == DFmode
5542 || mode == DQmode || mode == UDQmode
5543 || mode == DAmode || mode == UDAmode)
5546 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
5547 return size == -1 || size > UNITS_PER_WORD;
5551 /* If we have a variable-sized parameter, we have no choice. */
5552 return targetm.calls.must_pass_in_stack (mode, type);
5556 /* Implement TARGET_CALLEE_COPIES. */
5559 mips_callee_copies (cumulative_args_t cum ATTRIBUTE_UNUSED,
5560 machine_mode mode ATTRIBUTE_UNUSED,
5561 const_tree type ATTRIBUTE_UNUSED, bool named)
5563 return mips_abi == ABI_EABI && named;
5566 /* See whether VALTYPE is a record whose fields should be returned in
5567 floating-point registers. If so, return the number of fields and
5568 list them in FIELDS (which should have two elements). Return 0
5571 For n32 & n64, a structure with one or two fields is returned in
5572 floating-point registers as long as every field has a floating-point
5576 mips_fpr_return_fields (const_tree valtype, tree *fields)
5584 if (TREE_CODE (valtype) != RECORD_TYPE)
5588 for (field = TYPE_FIELDS (valtype); field != 0; field = DECL_CHAIN (field))
5590 if (TREE_CODE (field) != FIELD_DECL)
5593 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)))
5599 fields[i++] = field;
5604 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
5605 a value in the most significant part of $2/$3 if:
5607 - the target is big-endian;
5609 - the value has a structure or union type (we generalize this to
5610 cover aggregates from other languages too); and
5612 - the structure is not returned in floating-point registers. */
5615 mips_return_in_msb (const_tree valtype)
5619 return (TARGET_NEWABI
5620 && TARGET_BIG_ENDIAN
5621 && AGGREGATE_TYPE_P (valtype)
5622 && mips_fpr_return_fields (valtype, fields) == 0);
5625 /* Return true if the function return value MODE will get returned in a
5626 floating-point register. */
5629 mips_return_mode_in_fpr_p (machine_mode mode)
5631 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT || mode != V2SFmode);
5632 return ((GET_MODE_CLASS (mode) == MODE_FLOAT
5634 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5635 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE);
5638 /* Return the representation of an FPR return register when the
5639 value being returned in FP_RETURN has mode VALUE_MODE and the
5640 return type itself has mode TYPE_MODE. On NewABI targets,
5641 the two modes may be different for structures like:
5643 struct __attribute__((packed)) foo { float f; }
5645 where we return the SFmode value of "f" in FP_RETURN, but where
5646 the structure itself has mode BLKmode. */
5649 mips_return_fpr_single (machine_mode type_mode,
5650 machine_mode value_mode)
5654 x = gen_rtx_REG (value_mode, FP_RETURN);
5655 if (type_mode != value_mode)
5657 x = gen_rtx_EXPR_LIST (VOIDmode, x, const0_rtx);
5658 x = gen_rtx_PARALLEL (type_mode, gen_rtvec (1, x));
5663 /* Return a composite value in a pair of floating-point registers.
5664 MODE1 and OFFSET1 are the mode and byte offset for the first value,
5665 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
5668 For n32 & n64, $f0 always holds the first value and $f2 the second.
5669 Otherwise the values are packed together as closely as possible. */
5672 mips_return_fpr_pair (machine_mode mode,
5673 machine_mode mode1, HOST_WIDE_INT offset1,
5674 machine_mode mode2, HOST_WIDE_INT offset2)
5678 inc = (TARGET_NEWABI || mips_abi == ABI_32 ? 2 : MAX_FPRS_PER_FMT);
5679 return gen_rtx_PARALLEL
5682 gen_rtx_EXPR_LIST (VOIDmode,
5683 gen_rtx_REG (mode1, FP_RETURN),
5685 gen_rtx_EXPR_LIST (VOIDmode,
5686 gen_rtx_REG (mode2, FP_RETURN + inc),
5687 GEN_INT (offset2))));
5691 /* Implement TARGET_FUNCTION_VALUE and TARGET_LIBCALL_VALUE.
5692 For normal calls, VALTYPE is the return type and MODE is VOIDmode.
5693 For libcalls, VALTYPE is null and MODE is the mode of the return value. */
5696 mips_function_value_1 (const_tree valtype, const_tree fn_decl_or_type,
5705 if (fn_decl_or_type && DECL_P (fn_decl_or_type))
5706 func = fn_decl_or_type;
5710 mode = TYPE_MODE (valtype);
5711 unsigned_p = TYPE_UNSIGNED (valtype);
5713 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
5714 return values, promote the mode here too. */
5715 mode = promote_function_mode (valtype, mode, &unsigned_p, func, 1);
5717 /* Handle structures whose fields are returned in $f0/$f2. */
5718 switch (mips_fpr_return_fields (valtype, fields))
5721 return mips_return_fpr_single (mode,
5722 TYPE_MODE (TREE_TYPE (fields[0])));
5725 return mips_return_fpr_pair (mode,
5726 TYPE_MODE (TREE_TYPE (fields[0])),
5727 int_byte_position (fields[0]),
5728 TYPE_MODE (TREE_TYPE (fields[1])),
5729 int_byte_position (fields[1]));
5732 /* If a value is passed in the most significant part of a register, see
5733 whether we have to round the mode up to a whole number of words. */
5734 if (mips_return_in_msb (valtype))
5736 HOST_WIDE_INT size = int_size_in_bytes (valtype);
5737 if (size % UNITS_PER_WORD != 0)
5739 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
5740 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
5744 /* For EABI, the class of return register depends entirely on MODE.
5745 For example, "struct { some_type x; }" and "union { some_type x; }"
5746 are returned in the same way as a bare "some_type" would be.
5747 Other ABIs only use FPRs for scalar, complex or vector types. */
5748 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
5749 return gen_rtx_REG (mode, GP_RETURN);
5754 /* Handle long doubles for n32 & n64. */
5756 return mips_return_fpr_pair (mode,
5758 DImode, GET_MODE_SIZE (mode) / 2);
5760 if (mips_return_mode_in_fpr_p (mode))
5762 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5763 return mips_return_fpr_pair (mode,
5764 GET_MODE_INNER (mode), 0,
5765 GET_MODE_INNER (mode),
5766 GET_MODE_SIZE (mode) / 2);
5768 return gen_rtx_REG (mode, FP_RETURN);
5772 return gen_rtx_REG (mode, GP_RETURN);
5775 /* Implement TARGET_FUNCTION_VALUE. */
5778 mips_function_value (const_tree valtype, const_tree fn_decl_or_type,
5779 bool outgoing ATTRIBUTE_UNUSED)
5781 return mips_function_value_1 (valtype, fn_decl_or_type, VOIDmode);
5784 /* Implement TARGET_LIBCALL_VALUE. */
5787 mips_libcall_value (machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
5789 return mips_function_value_1 (NULL_TREE, NULL_TREE, mode);
5792 /* Implement TARGET_FUNCTION_VALUE_REGNO_P.
5794 On the MIPS, R2 R3 and F0 F2 are the only register thus used. */
5797 mips_function_value_regno_p (const unsigned int regno)
5799 /* Most types only require one GPR or one FPR for return values but for
5800 hard-float two FPRs can be used for _Complex types (for all ABIs)
5801 and long doubles (for n64). */
5802 if (regno == GP_RETURN
5803 || regno == FP_RETURN
5804 || (FP_RETURN != GP_RETURN
5805 && regno == FP_RETURN + 2))
5808 /* For o32 FP32, _Complex double will be returned in four 32-bit registers.
5809 This does not apply to o32 FPXX as floating-point function argument and
5810 return registers are described as 64-bit even though floating-point
5811 registers are primarily described as 32-bit internally.
5812 See: mips_get_reg_raw_mode. */
5813 if ((mips_abi == ABI_32 && TARGET_FLOAT32)
5814 && FP_RETURN != GP_RETURN
5815 && (regno == FP_RETURN + 1
5816 || regno == FP_RETURN + 3))
5822 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
5823 all BLKmode objects are returned in memory. Under the n32, n64
5824 and embedded ABIs, small structures are returned in a register.
5825 Objects with varying size must still be returned in memory, of
5829 mips_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
5831 return (TARGET_OLDABI
5832 ? TYPE_MODE (type) == BLKmode
5833 : !IN_RANGE (int_size_in_bytes (type), 0, 2 * UNITS_PER_WORD));
5836 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
5839 mips_setup_incoming_varargs (cumulative_args_t cum, machine_mode mode,
5840 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5843 CUMULATIVE_ARGS local_cum;
5844 int gp_saved, fp_saved;
5846 /* The caller has advanced CUM up to, but not beyond, the last named
5847 argument. Advance a local copy of CUM past the last "real" named
5848 argument, to find out how many registers are left over. */
5849 local_cum = *get_cumulative_args (cum);
5850 mips_function_arg_advance (pack_cumulative_args (&local_cum), mode, type,
5853 /* Found out how many registers we need to save. */
5854 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
5855 fp_saved = (EABI_FLOAT_VARARGS_P
5856 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
5865 ptr = plus_constant (Pmode, virtual_incoming_args_rtx,
5866 REG_PARM_STACK_SPACE (cfun->decl)
5867 - gp_saved * UNITS_PER_WORD);
5868 mem = gen_frame_mem (BLKmode, ptr);
5869 set_mem_alias_set (mem, get_varargs_alias_set ());
5871 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
5876 /* We can't use move_block_from_reg, because it will use
5881 /* Set OFF to the offset from virtual_incoming_args_rtx of
5882 the first float register. The FP save area lies below
5883 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
5884 off = (-gp_saved * UNITS_PER_WORD) & -UNITS_PER_FPVALUE;
5885 off -= fp_saved * UNITS_PER_FPREG;
5887 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
5889 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS;
5890 i += MAX_FPRS_PER_FMT)
5894 ptr = plus_constant (Pmode, virtual_incoming_args_rtx, off);
5895 mem = gen_frame_mem (mode, ptr);
5896 set_mem_alias_set (mem, get_varargs_alias_set ());
5897 mips_emit_move (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
5898 off += UNITS_PER_HWFPVALUE;
5902 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
5903 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
5904 + fp_saved * UNITS_PER_FPREG);
5907 /* Implement TARGET_BUILTIN_VA_LIST. */
5910 mips_build_builtin_va_list (void)
5912 if (EABI_FLOAT_VARARGS_P)
5914 /* We keep 3 pointers, and two offsets.
5916 Two pointers are to the overflow area, which starts at the CFA.
5917 One of these is constant, for addressing into the GPR save area
5918 below it. The other is advanced up the stack through the
5921 The third pointer is to the bottom of the GPR save area.
5922 Since the FPR save area is just below it, we can address
5923 FPR slots off this pointer.
5925 We also keep two one-byte offsets, which are to be subtracted
5926 from the constant pointers to yield addresses in the GPR and
5927 FPR save areas. These are downcounted as float or non-float
5928 arguments are used, and when they get to zero, the argument
5929 must be obtained from the overflow region. */
5930 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
5933 record = lang_hooks.types.make_type (RECORD_TYPE);
5935 f_ovfl = build_decl (BUILTINS_LOCATION,
5936 FIELD_DECL, get_identifier ("__overflow_argptr"),
5938 f_gtop = build_decl (BUILTINS_LOCATION,
5939 FIELD_DECL, get_identifier ("__gpr_top"),
5941 f_ftop = build_decl (BUILTINS_LOCATION,
5942 FIELD_DECL, get_identifier ("__fpr_top"),
5944 f_goff = build_decl (BUILTINS_LOCATION,
5945 FIELD_DECL, get_identifier ("__gpr_offset"),
5946 unsigned_char_type_node);
5947 f_foff = build_decl (BUILTINS_LOCATION,
5948 FIELD_DECL, get_identifier ("__fpr_offset"),
5949 unsigned_char_type_node);
5950 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
5951 warn on every user file. */
5952 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
5953 array = build_array_type (unsigned_char_type_node,
5954 build_index_type (index));
5955 f_res = build_decl (BUILTINS_LOCATION,
5956 FIELD_DECL, get_identifier ("__reserved"), array);
5958 DECL_FIELD_CONTEXT (f_ovfl) = record;
5959 DECL_FIELD_CONTEXT (f_gtop) = record;
5960 DECL_FIELD_CONTEXT (f_ftop) = record;
5961 DECL_FIELD_CONTEXT (f_goff) = record;
5962 DECL_FIELD_CONTEXT (f_foff) = record;
5963 DECL_FIELD_CONTEXT (f_res) = record;
5965 TYPE_FIELDS (record) = f_ovfl;
5966 DECL_CHAIN (f_ovfl) = f_gtop;
5967 DECL_CHAIN (f_gtop) = f_ftop;
5968 DECL_CHAIN (f_ftop) = f_goff;
5969 DECL_CHAIN (f_goff) = f_foff;
5970 DECL_CHAIN (f_foff) = f_res;
5972 layout_type (record);
5976 /* Otherwise, we use 'void *'. */
5977 return ptr_type_node;
5980 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
5983 mips_va_start (tree valist, rtx nextarg)
5985 if (EABI_FLOAT_VARARGS_P)
5987 const CUMULATIVE_ARGS *cum;
5988 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5989 tree ovfl, gtop, ftop, goff, foff;
5991 int gpr_save_area_size;
5992 int fpr_save_area_size;
5995 cum = &crtl->args.info;
5997 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
5999 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
6001 f_ovfl = TYPE_FIELDS (va_list_type_node);
6002 f_gtop = DECL_CHAIN (f_ovfl);
6003 f_ftop = DECL_CHAIN (f_gtop);
6004 f_goff = DECL_CHAIN (f_ftop);
6005 f_foff = DECL_CHAIN (f_goff);
6007 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
6009 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
6011 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
6013 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
6015 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
6018 /* Emit code to initialize OVFL, which points to the next varargs
6019 stack argument. CUM->STACK_WORDS gives the number of stack
6020 words used by named arguments. */
6021 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
6022 if (cum->stack_words > 0)
6023 t = fold_build_pointer_plus_hwi (t, cum->stack_words * UNITS_PER_WORD);
6024 t = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
6025 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6027 /* Emit code to initialize GTOP, the top of the GPR save area. */
6028 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
6029 t = build2 (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
6030 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6032 /* Emit code to initialize FTOP, the top of the FPR save area.
6033 This address is gpr_save_area_bytes below GTOP, rounded
6034 down to the next fp-aligned boundary. */
6035 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
6036 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
6037 fpr_offset &= -UNITS_PER_FPVALUE;
6039 t = fold_build_pointer_plus_hwi (t, -fpr_offset);
6040 t = build2 (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
6041 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6043 /* Emit code to initialize GOFF, the offset from GTOP of the
6044 next GPR argument. */
6045 t = build2 (MODIFY_EXPR, TREE_TYPE (goff), goff,
6046 build_int_cst (TREE_TYPE (goff), gpr_save_area_size));
6047 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6049 /* Likewise emit code to initialize FOFF, the offset from FTOP
6050 of the next FPR argument. */
6051 t = build2 (MODIFY_EXPR, TREE_TYPE (foff), foff,
6052 build_int_cst (TREE_TYPE (foff), fpr_save_area_size));
6053 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6057 nextarg = plus_constant (Pmode, nextarg, -cfun->machine->varargs_size);
6058 std_expand_builtin_va_start (valist, nextarg);
6062 /* Like std_gimplify_va_arg_expr, but apply alignment to zero-sized
6066 mips_std_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
6069 tree addr, t, type_size, rounded_size, valist_tmp;
6070 unsigned HOST_WIDE_INT align, boundary;
6073 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, false);
6075 type = build_pointer_type (type);
6077 align = PARM_BOUNDARY / BITS_PER_UNIT;
6078 boundary = targetm.calls.function_arg_boundary (TYPE_MODE (type), type);
6080 /* When we align parameter on stack for caller, if the parameter
6081 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
6082 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
6083 here with caller. */
6084 if (boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
6085 boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
6087 boundary /= BITS_PER_UNIT;
6089 /* Hoist the valist value into a temporary for the moment. */
6090 valist_tmp = get_initialized_tmp_var (valist, pre_p, NULL);
6092 /* va_list pointer is aligned to PARM_BOUNDARY. If argument actually
6093 requires greater alignment, we must perform dynamic alignment. */
6094 if (boundary > align)
6096 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
6097 fold_build_pointer_plus_hwi (valist_tmp, boundary - 1));
6098 gimplify_and_add (t, pre_p);
6100 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
6101 fold_build2 (BIT_AND_EXPR, TREE_TYPE (valist),
6103 build_int_cst (TREE_TYPE (valist), -boundary)));
6104 gimplify_and_add (t, pre_p);
6109 /* If the actual alignment is less than the alignment of the type,
6110 adjust the type accordingly so that we don't assume strict alignment
6111 when dereferencing the pointer. */
6112 boundary *= BITS_PER_UNIT;
6113 if (boundary < TYPE_ALIGN (type))
6115 type = build_variant_type_copy (type);
6116 TYPE_ALIGN (type) = boundary;
6119 /* Compute the rounded size of the type. */
6120 type_size = size_in_bytes (type);
6121 rounded_size = round_up (type_size, align);
6123 /* Reduce rounded_size so it's sharable with the postqueue. */
6124 gimplify_expr (&rounded_size, pre_p, post_p, is_gimple_val, fb_rvalue);
6128 if (PAD_VARARGS_DOWN && !integer_zerop (rounded_size))
6130 /* Small args are padded downward. */
6131 t = fold_build2_loc (input_location, GT_EXPR, sizetype,
6132 rounded_size, size_int (align));
6133 t = fold_build3 (COND_EXPR, sizetype, t, size_zero_node,
6134 size_binop (MINUS_EXPR, rounded_size, type_size));
6135 addr = fold_build_pointer_plus (addr, t);
6138 /* Compute new value for AP. */
6139 t = fold_build_pointer_plus (valist_tmp, rounded_size);
6140 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
6141 gimplify_and_add (t, pre_p);
6143 addr = fold_convert (build_pointer_type (type), addr);
6146 addr = build_va_arg_indirect_ref (addr);
6148 return build_va_arg_indirect_ref (addr);
6151 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
6154 mips_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
6160 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
6162 type = build_pointer_type (type);
6164 if (!EABI_FLOAT_VARARGS_P)
6165 addr = mips_std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6168 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
6169 tree ovfl, top, off, align;
6170 HOST_WIDE_INT size, rsize, osize;
6173 f_ovfl = TYPE_FIELDS (va_list_type_node);
6174 f_gtop = DECL_CHAIN (f_ovfl);
6175 f_ftop = DECL_CHAIN (f_gtop);
6176 f_goff = DECL_CHAIN (f_ftop);
6177 f_foff = DECL_CHAIN (f_goff);
6181 TOP be the top of the GPR or FPR save area;
6182 OFF be the offset from TOP of the next register;
6183 ADDR_RTX be the address of the argument;
6184 SIZE be the number of bytes in the argument type;
6185 RSIZE be the number of bytes used to store the argument
6186 when it's in the register save area; and
6187 OSIZE be the number of bytes used to store it when it's
6188 in the stack overflow area.
6190 The code we want is:
6192 1: off &= -rsize; // round down
6195 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
6200 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
6201 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
6205 [1] and [9] can sometimes be optimized away. */
6207 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
6209 size = int_size_in_bytes (type);
6211 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
6212 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
6214 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop),
6215 unshare_expr (valist), f_ftop, NULL_TREE);
6216 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff),
6217 unshare_expr (valist), f_foff, NULL_TREE);
6219 /* When va_start saves FPR arguments to the stack, each slot
6220 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
6221 argument's precision. */
6222 rsize = UNITS_PER_HWFPVALUE;
6224 /* Overflow arguments are padded to UNITS_PER_WORD bytes
6225 (= PARM_BOUNDARY bits). This can be different from RSIZE
6228 (1) On 32-bit targets when TYPE is a structure such as:
6230 struct s { float f; };
6232 Such structures are passed in paired FPRs, so RSIZE
6233 will be 8 bytes. However, the structure only takes
6234 up 4 bytes of memory, so OSIZE will only be 4.
6236 (2) In combinations such as -mgp64 -msingle-float
6237 -fshort-double. Doubles passed in registers will then take
6238 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
6239 stack take up UNITS_PER_WORD bytes. */
6240 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
6244 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop),
6245 unshare_expr (valist), f_gtop, NULL_TREE);
6246 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff),
6247 unshare_expr (valist), f_goff, NULL_TREE);
6248 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
6249 if (rsize > UNITS_PER_WORD)
6251 /* [1] Emit code for: off &= -rsize. */
6252 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), unshare_expr (off),
6253 build_int_cst (TREE_TYPE (off), -rsize));
6254 gimplify_assign (unshare_expr (off), t, pre_p);
6259 /* [2] Emit code to branch if off == 0. */
6260 t = build2 (NE_EXPR, boolean_type_node, unshare_expr (off),
6261 build_int_cst (TREE_TYPE (off), 0));
6262 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
6264 /* [5] Emit code for: off -= rsize. We do this as a form of
6265 post-decrement not available to C. */
6266 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
6267 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
6269 /* [4] Emit code for:
6270 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
6271 t = fold_convert (sizetype, t);
6272 t = fold_build1 (NEGATE_EXPR, sizetype, t);
6273 t = fold_build_pointer_plus (top, t);
6274 if (BYTES_BIG_ENDIAN && rsize > size)
6275 t = fold_build_pointer_plus_hwi (t, rsize - size);
6276 COND_EXPR_THEN (addr) = t;
6278 if (osize > UNITS_PER_WORD)
6280 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
6281 t = fold_build_pointer_plus_hwi (unshare_expr (ovfl), osize - 1);
6282 u = build_int_cst (TREE_TYPE (t), -osize);
6283 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t, u);
6284 align = build2 (MODIFY_EXPR, TREE_TYPE (ovfl),
6285 unshare_expr (ovfl), t);
6290 /* [10, 11] Emit code for:
6291 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
6293 u = fold_convert (TREE_TYPE (ovfl), build_int_cst (NULL_TREE, osize));
6294 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
6295 if (BYTES_BIG_ENDIAN && osize > size)
6296 t = fold_build_pointer_plus_hwi (t, osize - size);
6298 /* String [9] and [10, 11] together. */
6300 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
6301 COND_EXPR_ELSE (addr) = t;
6303 addr = fold_convert (build_pointer_type (type), addr);
6304 addr = build_va_arg_indirect_ref (addr);
6308 addr = build_va_arg_indirect_ref (addr);
6313 /* Declare a unique, locally-binding function called NAME, then start
6317 mips_start_unique_function (const char *name)
6321 decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
6322 get_identifier (name),
6323 build_function_type_list (void_type_node, NULL_TREE));
6324 DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
6325 NULL_TREE, void_type_node);
6326 TREE_PUBLIC (decl) = 1;
6327 TREE_STATIC (decl) = 1;
6329 cgraph_node::create (decl)->set_comdat_group (DECL_ASSEMBLER_NAME (decl));
6331 targetm.asm_out.unique_section (decl, 0);
6332 switch_to_section (get_named_section (decl, NULL, 0));
6334 targetm.asm_out.globalize_label (asm_out_file, name);
6335 fputs ("\t.hidden\t", asm_out_file);
6336 assemble_name (asm_out_file, name);
6337 putc ('\n', asm_out_file);
6340 /* Start a definition of function NAME. MIPS16_P indicates whether the
6341 function contains MIPS16 code. */
6344 mips_start_function_definition (const char *name, bool mips16_p)
6347 fprintf (asm_out_file, "\t.set\tmips16\n");
6349 fprintf (asm_out_file, "\t.set\tnomips16\n");
6351 if (TARGET_MICROMIPS)
6352 fprintf (asm_out_file, "\t.set\tmicromips\n");
6353 #ifdef HAVE_GAS_MICROMIPS
6355 fprintf (asm_out_file, "\t.set\tnomicromips\n");
6358 if (!flag_inhibit_size_directive)
6360 fputs ("\t.ent\t", asm_out_file);
6361 assemble_name (asm_out_file, name);
6362 fputs ("\n", asm_out_file);
6365 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, name, "function");
6367 /* Start the definition proper. */
6368 assemble_name (asm_out_file, name);
6369 fputs (":\n", asm_out_file);
6372 /* End a function definition started by mips_start_function_definition. */
6375 mips_end_function_definition (const char *name)
6377 if (!flag_inhibit_size_directive)
6379 fputs ("\t.end\t", asm_out_file);
6380 assemble_name (asm_out_file, name);
6381 fputs ("\n", asm_out_file);
6385 /* If *STUB_PTR points to a stub, output a comdat-style definition for it,
6386 then free *STUB_PTR. */
6389 mips_finish_stub (mips_one_only_stub **stub_ptr)
6391 mips_one_only_stub *stub = *stub_ptr;
6395 const char *name = stub->get_name ();
6396 mips_start_unique_function (name);
6397 mips_start_function_definition (name, false);
6398 stub->output_body ();
6399 mips_end_function_definition (name);
6404 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
6407 mips_ok_for_lazy_binding_p (rtx x)
6409 return (TARGET_USE_GOT
6410 && GET_CODE (x) == SYMBOL_REF
6411 && !SYMBOL_REF_BIND_NOW_P (x)
6412 && !mips_symbol_binds_local_p (x));
6415 /* Load function address ADDR into register DEST. TYPE is as for
6416 mips_expand_call. Return true if we used an explicit lazy-binding
6420 mips_load_call_address (enum mips_call_type type, rtx dest, rtx addr)
6422 /* If we're generating PIC, and this call is to a global function,
6423 try to allow its address to be resolved lazily. This isn't
6424 possible for sibcalls when $gp is call-saved because the value
6425 of $gp on entry to the stub would be our caller's gp, not ours. */
6426 if (TARGET_EXPLICIT_RELOCS
6427 && !(type == MIPS_CALL_SIBCALL && TARGET_CALL_SAVED_GP)
6428 && mips_ok_for_lazy_binding_p (addr))
6430 addr = mips_got_load (dest, addr, SYMBOL_GOTOFF_CALL);
6431 emit_insn (gen_rtx_SET (VOIDmode, dest, addr));
6436 mips_emit_move (dest, addr);
6441 struct local_alias_traits : default_hashmap_traits
6443 static hashval_t hash (rtx);
6444 static bool equal_keys (rtx, rtx);
6447 /* Each locally-defined hard-float MIPS16 function has a local symbol
6448 associated with it. This hash table maps the function symbol (FUNC)
6449 to the local symbol (LOCAL). */
6450 static GTY (()) hash_map<rtx, rtx, local_alias_traits> *mips16_local_aliases;
6452 /* Hash table callbacks for mips16_local_aliases. */
6455 local_alias_traits::hash (rtx func)
6457 return htab_hash_string (XSTR (func, 0));
6461 local_alias_traits::equal_keys (rtx func1, rtx func2)
6463 return rtx_equal_p (func1, func2);
6466 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
6467 Return a local alias for it, creating a new one if necessary. */
6470 mips16_local_alias (rtx func)
6472 /* Create the hash table if this is the first call. */
6473 if (mips16_local_aliases == NULL)
6474 mips16_local_aliases
6475 = hash_map<rtx, rtx, local_alias_traits>::create_ggc (37);
6477 /* Look up the function symbol, creating a new entry if need be. */
6479 rtx *slot = &mips16_local_aliases->get_or_insert (func, &existed);
6480 gcc_assert (slot != NULL);
6484 const char *func_name, *local_name;
6487 /* Create a new SYMBOL_REF for the local symbol. The choice of
6488 __fn_local_* is based on the __fn_stub_* names that we've
6489 traditionally used for the non-MIPS16 stub. */
6490 func_name = targetm.strip_name_encoding (XSTR (func, 0));
6491 local_name = ACONCAT (("__fn_local_", func_name, NULL));
6492 local = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (local_name));
6493 SYMBOL_REF_FLAGS (local) = SYMBOL_REF_FLAGS (func) | SYMBOL_FLAG_LOCAL;
6495 /* Create a new structure to represent the mapping. */
6501 /* A chained list of functions for which mips16_build_call_stub has already
6502 generated a stub. NAME is the name of the function and FP_RET_P is true
6503 if the function returns a value in floating-point registers. */
6504 struct mips16_stub {
6505 struct mips16_stub *next;
6509 static struct mips16_stub *mips16_stubs;
6511 /* Return the two-character string that identifies floating-point
6512 return mode MODE in the name of a MIPS16 function stub. */
6515 mips16_call_stub_mode_suffix (machine_mode mode)
6519 else if (mode == DFmode)
6521 else if (mode == SCmode)
6523 else if (mode == DCmode)
6525 else if (mode == V2SFmode)
6527 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT);
6534 /* Write instructions to move a 32-bit value between general register
6535 GPREG and floating-point register FPREG. DIRECTION is 't' to move
6536 from GPREG to FPREG and 'f' to move in the opposite direction. */
6539 mips_output_32bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
6541 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6542 reg_names[gpreg], reg_names[fpreg]);
6545 /* Likewise for 64-bit values. */
6548 mips_output_64bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
6551 fprintf (asm_out_file, "\tdm%cc1\t%s,%s\n", direction,
6552 reg_names[gpreg], reg_names[fpreg]);
6553 else if (ISA_HAS_MXHC1)
6555 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6556 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
6557 fprintf (asm_out_file, "\tm%chc1\t%s,%s\n", direction,
6558 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg]);
6560 else if (TARGET_FLOATXX && direction == 't')
6562 /* Use the argument save area to move via memory. */
6563 fprintf (asm_out_file, "\tsw\t%s,0($sp)\n", reg_names[gpreg]);
6564 fprintf (asm_out_file, "\tsw\t%s,4($sp)\n", reg_names[gpreg + 1]);
6565 fprintf (asm_out_file, "\tldc1\t%s,0($sp)\n", reg_names[fpreg]);
6567 else if (TARGET_FLOATXX && direction == 'f')
6569 /* Use the argument save area to move via memory. */
6570 fprintf (asm_out_file, "\tsdc1\t%s,0($sp)\n", reg_names[fpreg]);
6571 fprintf (asm_out_file, "\tlw\t%s,0($sp)\n", reg_names[gpreg]);
6572 fprintf (asm_out_file, "\tlw\t%s,4($sp)\n", reg_names[gpreg + 1]);
6576 /* Move the least-significant word. */
6577 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6578 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
6579 /* ...then the most significant word. */
6580 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6581 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg + 1]);
6585 /* Write out code to move floating-point arguments into or out of
6586 general registers. FP_CODE is the code describing which arguments
6587 are present (see the comment above the definition of CUMULATIVE_ARGS
6588 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
6591 mips_output_args_xfer (int fp_code, char direction)
6593 unsigned int gparg, fparg, f;
6594 CUMULATIVE_ARGS cum;
6596 /* This code only works for o32 and o64. */
6597 gcc_assert (TARGET_OLDABI);
6599 mips_init_cumulative_args (&cum, NULL);
6601 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
6604 struct mips_arg_info info;
6608 else if ((f & 3) == 2)
6613 mips_get_arg_info (&info, &cum, mode, NULL, true);
6614 gparg = mips_arg_regno (&info, false);
6615 fparg = mips_arg_regno (&info, true);
6618 mips_output_32bit_xfer (direction, gparg, fparg);
6620 mips_output_64bit_xfer (direction, gparg, fparg);
6622 mips_function_arg_advance (pack_cumulative_args (&cum), mode, NULL, true);
6626 /* Write a MIPS16 stub for the current function. This stub is used
6627 for functions which take arguments in the floating-point registers.
6628 It is normal-mode code that moves the floating-point arguments
6629 into the general registers and then jumps to the MIPS16 code. */
6632 mips16_build_function_stub (void)
6634 const char *fnname, *alias_name, *separator;
6635 char *secname, *stubname;
6640 /* Create the name of the stub, and its unique section. */
6641 symbol = XEXP (DECL_RTL (current_function_decl), 0);
6642 alias = mips16_local_alias (symbol);
6644 fnname = targetm.strip_name_encoding (XSTR (symbol, 0));
6645 alias_name = targetm.strip_name_encoding (XSTR (alias, 0));
6646 secname = ACONCAT ((".mips16.fn.", fnname, NULL));
6647 stubname = ACONCAT (("__fn_stub_", fnname, NULL));
6649 /* Build a decl for the stub. */
6650 stubdecl = build_decl (BUILTINS_LOCATION,
6651 FUNCTION_DECL, get_identifier (stubname),
6652 build_function_type_list (void_type_node, NULL_TREE));
6653 set_decl_section_name (stubdecl, secname);
6654 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
6655 RESULT_DECL, NULL_TREE, void_type_node);
6657 /* Output a comment. */
6658 fprintf (asm_out_file, "\t# Stub function for %s (",
6659 current_function_name ());
6661 for (f = (unsigned int) crtl->args.info.fp_code; f != 0; f >>= 2)
6663 fprintf (asm_out_file, "%s%s", separator,
6664 (f & 3) == 1 ? "float" : "double");
6667 fprintf (asm_out_file, ")\n");
6669 /* Start the function definition. */
6670 assemble_start_function (stubdecl, stubname);
6671 mips_start_function_definition (stubname, false);
6673 /* If generating pic2 code, either set up the global pointer or
6675 if (TARGET_ABICALLS_PIC2)
6677 if (TARGET_ABSOLUTE_ABICALLS)
6678 fprintf (asm_out_file, "\t.option\tpic0\n");
6681 output_asm_insn ("%(.cpload\t%^%)", NULL);
6682 /* Emit an R_MIPS_NONE relocation to tell the linker what the
6683 target function is. Use a local GOT access when loading the
6684 symbol, to cut down on the number of unnecessary GOT entries
6685 for stubs that aren't needed. */
6686 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol);
6691 /* Load the address of the MIPS16 function into $25. Do this first so
6692 that targets with coprocessor interlocks can use an MFC1 to fill the
6694 output_asm_insn ("la\t%^,%0", &symbol);
6696 /* Move the arguments from floating-point registers to general registers. */
6697 mips_output_args_xfer (crtl->args.info.fp_code, 'f');
6699 /* Jump to the MIPS16 function. */
6700 output_asm_insn ("jr\t%^", NULL);
6702 if (TARGET_ABICALLS_PIC2 && TARGET_ABSOLUTE_ABICALLS)
6703 fprintf (asm_out_file, "\t.option\tpic2\n");
6705 mips_end_function_definition (stubname);
6707 /* If the linker needs to create a dynamic symbol for the target
6708 function, it will associate the symbol with the stub (which,
6709 unlike the target function, follows the proper calling conventions).
6710 It is therefore useful to have a local alias for the target function,
6711 so that it can still be identified as MIPS16 code. As an optimization,
6712 this symbol can also be used for indirect MIPS16 references from
6713 within this file. */
6714 ASM_OUTPUT_DEF (asm_out_file, alias_name, fnname);
6716 switch_to_section (function_section (current_function_decl));
6719 /* The current function is a MIPS16 function that returns a value in an FPR.
6720 Copy the return value from its soft-float to its hard-float location.
6721 libgcc2 has special non-MIPS16 helper functions for each case. */
6724 mips16_copy_fpr_return_value (void)
6726 rtx fn, insn, retval;
6728 machine_mode return_mode;
6731 return_type = DECL_RESULT (current_function_decl);
6732 return_mode = DECL_MODE (return_type);
6734 name = ACONCAT (("__mips16_ret_",
6735 mips16_call_stub_mode_suffix (return_mode),
6737 fn = mips16_stub_function (name);
6739 /* The function takes arguments in $2 (and possibly $3), so calls
6740 to it cannot be lazily bound. */
6741 SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_BIND_NOW;
6743 /* Model the call as something that takes the GPR return value as
6744 argument and returns an "updated" value. */
6745 retval = gen_rtx_REG (return_mode, GP_RETURN);
6746 insn = mips_expand_call (MIPS_CALL_EPILOGUE, retval, fn,
6747 const0_rtx, NULL_RTX, false);
6748 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), retval);
6751 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
6752 RETVAL is the location of the return value, or null if this is
6753 a "call" rather than a "call_value". ARGS_SIZE is the size of the
6754 arguments and FP_CODE is the code built by mips_function_arg;
6755 see the comment before the fp_code field in CUMULATIVE_ARGS for details.
6757 There are three alternatives:
6759 - If a stub was needed, emit the call and return the call insn itself.
6761 - If we can avoid using a stub by redirecting the call, set *FN_PTR
6762 to the new target and return null.
6764 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
6767 A stub is needed for calls to functions that, in normal mode,
6768 receive arguments in FPRs or return values in FPRs. The stub
6769 copies the arguments from their soft-float positions to their
6770 hard-float positions, calls the real function, then copies the
6771 return value from its hard-float position to its soft-float
6774 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
6775 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
6776 automatically redirects the JAL to the stub, otherwise the JAL
6777 continues to call FN directly. */
6780 mips16_build_call_stub (rtx retval, rtx *fn_ptr, rtx args_size, int fp_code)
6784 struct mips16_stub *l;
6788 /* We don't need to do anything if we aren't in MIPS16 mode, or if
6789 we were invoked with the -msoft-float option. */
6790 if (!TARGET_MIPS16 || TARGET_SOFT_FLOAT_ABI)
6793 /* Figure out whether the value might come back in a floating-point
6795 fp_ret_p = retval && mips_return_mode_in_fpr_p (GET_MODE (retval));
6797 /* We don't need to do anything if there were no floating-point
6798 arguments and the value will not be returned in a floating-point
6800 if (fp_code == 0 && !fp_ret_p)
6803 /* We don't need to do anything if this is a call to a special
6804 MIPS16 support function. */
6806 if (mips16_stub_function_p (fn))
6809 /* If we're calling a locally-defined MIPS16 function, we know that
6810 it will return values in both the "soft-float" and "hard-float"
6811 registers. There is no need to use a stub to move the latter
6813 if (fp_code == 0 && mips16_local_function_p (fn))
6816 /* This code will only work for o32 and o64 abis. The other ABI's
6817 require more sophisticated support. */
6818 gcc_assert (TARGET_OLDABI);
6820 /* If we're calling via a function pointer, use one of the magic
6821 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
6822 Each stub expects the function address to arrive in register $2. */
6823 if (GET_CODE (fn) != SYMBOL_REF
6824 || !call_insn_operand (fn, VOIDmode))
6831 /* If this is a locally-defined and locally-binding function,
6832 avoid the stub by calling the local alias directly. */
6833 if (mips16_local_function_p (fn))
6835 *fn_ptr = mips16_local_alias (fn);
6839 /* Create a SYMBOL_REF for the libgcc.a function. */
6841 sprintf (buf, "__mips16_call_stub_%s_%d",
6842 mips16_call_stub_mode_suffix (GET_MODE (retval)),
6845 sprintf (buf, "__mips16_call_stub_%d", fp_code);
6846 stub_fn = mips16_stub_function (buf);
6848 /* The function uses $2 as an argument, so calls to it
6849 cannot be lazily bound. */
6850 SYMBOL_REF_FLAGS (stub_fn) |= SYMBOL_FLAG_BIND_NOW;
6852 /* Load the target function into $2. */
6853 addr = gen_rtx_REG (Pmode, GP_REG_FIRST + 2);
6854 lazy_p = mips_load_call_address (MIPS_CALL_NORMAL, addr, fn);
6856 /* Emit the call. */
6857 insn = mips_expand_call (MIPS_CALL_NORMAL, retval, stub_fn,
6858 args_size, NULL_RTX, lazy_p);
6860 /* Tell GCC that this call does indeed use the value of $2. */
6861 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), addr);
6863 /* If we are handling a floating-point return value, we need to
6864 save $18 in the function prologue. Putting a note on the
6865 call will mean that df_regs_ever_live_p ($18) will be true if the
6866 call is not eliminated, and we can check that in the prologue
6869 CALL_INSN_FUNCTION_USAGE (insn) =
6870 gen_rtx_EXPR_LIST (VOIDmode,
6871 gen_rtx_CLOBBER (VOIDmode,
6872 gen_rtx_REG (word_mode, 18)),
6873 CALL_INSN_FUNCTION_USAGE (insn));
6878 /* We know the function we are going to call. If we have already
6879 built a stub, we don't need to do anything further. */
6880 fnname = targetm.strip_name_encoding (XSTR (fn, 0));
6881 for (l = mips16_stubs; l != NULL; l = l->next)
6882 if (strcmp (l->name, fnname) == 0)
6887 const char *separator;
6888 char *secname, *stubname;
6889 tree stubid, stubdecl;
6892 /* If the function does not return in FPRs, the special stub
6896 If the function does return in FPRs, the stub section is named
6897 .mips16.call.fp.FNNAME
6899 Build a decl for the stub. */
6900 secname = ACONCAT ((".mips16.call.", fp_ret_p ? "fp." : "",
6902 stubname = ACONCAT (("__call_stub_", fp_ret_p ? "fp_" : "",
6904 stubid = get_identifier (stubname);
6905 stubdecl = build_decl (BUILTINS_LOCATION,
6906 FUNCTION_DECL, stubid,
6907 build_function_type_list (void_type_node,
6909 set_decl_section_name (stubdecl, secname);
6910 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
6911 RESULT_DECL, NULL_TREE,
6914 /* Output a comment. */
6915 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
6917 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
6921 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
6923 fprintf (asm_out_file, "%s%s", separator,
6924 (f & 3) == 1 ? "float" : "double");
6927 fprintf (asm_out_file, ")\n");
6929 /* Start the function definition. */
6930 assemble_start_function (stubdecl, stubname);
6931 mips_start_function_definition (stubname, false);
6935 fprintf (asm_out_file, "\t.cfi_startproc\n");
6937 /* Create a fake CFA 4 bytes below the stack pointer.
6938 This works around unwinders (like libgcc's) that expect
6939 the CFA for non-signal frames to be unique. */
6940 fprintf (asm_out_file, "\t.cfi_def_cfa 29,-4\n");
6942 /* "Save" $sp in itself so we don't use the fake CFA.
6943 This is: DW_CFA_val_expression r29, { DW_OP_reg29 }. */
6944 fprintf (asm_out_file, "\t.cfi_escape 0x16,29,1,0x6d\n");
6948 /* Load the address of the MIPS16 function into $25. Do this
6949 first so that targets with coprocessor interlocks can use
6950 an MFC1 to fill the delay slot. */
6951 if (TARGET_EXPLICIT_RELOCS)
6953 output_asm_insn ("lui\t%^,%%hi(%0)", &fn);
6954 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn);
6957 output_asm_insn ("la\t%^,%0", &fn);
6960 /* Move the arguments from general registers to floating-point
6962 mips_output_args_xfer (fp_code, 't');
6966 /* Save the return address in $18 and call the non-MIPS16 function.
6967 The stub's caller knows that $18 might be clobbered, even though
6968 $18 is usually a call-saved register. */
6969 fprintf (asm_out_file, "\tmove\t%s,%s\n",
6970 reg_names[GP_REG_FIRST + 18], reg_names[RETURN_ADDR_REGNUM]);
6971 output_asm_insn (MIPS_CALL ("jal", &fn, 0, -1), &fn);
6972 fprintf (asm_out_file, "\t.cfi_register 31,18\n");
6974 /* Move the result from floating-point registers to
6975 general registers. */
6976 switch (GET_MODE (retval))
6979 mips_output_32bit_xfer ('f', GP_RETURN + TARGET_BIG_ENDIAN,
6983 mips_output_32bit_xfer ('f', GP_RETURN + TARGET_LITTLE_ENDIAN,
6984 TARGET_LITTLE_ENDIAN
6987 if (GET_MODE (retval) == SCmode && TARGET_64BIT)
6989 /* On 64-bit targets, complex floats are returned in
6990 a single GPR, such that "sd" on a suitably-aligned
6991 target would store the value correctly. */
6992 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
6993 reg_names[GP_RETURN + TARGET_BIG_ENDIAN],
6994 reg_names[GP_RETURN + TARGET_BIG_ENDIAN]);
6995 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
6996 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN],
6997 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN]);
6998 fprintf (asm_out_file, "\tdsrl\t%s,%s,32\n",
6999 reg_names[GP_RETURN + TARGET_BIG_ENDIAN],
7000 reg_names[GP_RETURN + TARGET_BIG_ENDIAN]);
7001 fprintf (asm_out_file, "\tor\t%s,%s,%s\n",
7002 reg_names[GP_RETURN],
7003 reg_names[GP_RETURN],
7004 reg_names[GP_RETURN + 1]);
7009 mips_output_32bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
7013 mips_output_64bit_xfer ('f', GP_RETURN + (8 / UNITS_PER_WORD),
7018 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT
7019 || GET_MODE (retval) != V2SFmode);
7020 mips_output_64bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
7026 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 18]);
7027 fprintf (asm_out_file, "\t.cfi_endproc\n");
7031 /* Jump to the previously-loaded address. */
7032 output_asm_insn ("jr\t%^", NULL);
7035 #ifdef ASM_DECLARE_FUNCTION_SIZE
7036 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
7039 mips_end_function_definition (stubname);
7041 /* Record this stub. */
7042 l = XNEW (struct mips16_stub);
7043 l->name = xstrdup (fnname);
7044 l->fp_ret_p = fp_ret_p;
7045 l->next = mips16_stubs;
7049 /* If we expect a floating-point return value, but we've built a
7050 stub which does not expect one, then we're in trouble. We can't
7051 use the existing stub, because it won't handle the floating-point
7052 value. We can't build a new stub, because the linker won't know
7053 which stub to use for the various calls in this object file.
7054 Fortunately, this case is illegal, since it means that a function
7055 was declared in two different ways in a single compilation. */
7056 if (fp_ret_p && !l->fp_ret_p)
7057 error ("cannot handle inconsistent calls to %qs", fnname);
7059 if (retval == NULL_RTX)
7060 pattern = gen_call_internal_direct (fn, args_size);
7062 pattern = gen_call_value_internal_direct (retval, fn, args_size);
7063 insn = mips_emit_call_insn (pattern, fn, fn, false);
7065 /* If we are calling a stub which handles a floating-point return
7066 value, we need to arrange to save $18 in the prologue. We do this
7067 by marking the function call as using the register. The prologue
7068 will later see that it is used, and emit code to save it. */
7070 CALL_INSN_FUNCTION_USAGE (insn) =
7071 gen_rtx_EXPR_LIST (VOIDmode,
7072 gen_rtx_CLOBBER (VOIDmode,
7073 gen_rtx_REG (word_mode, 18)),
7074 CALL_INSN_FUNCTION_USAGE (insn));
7079 /* Expand a call of type TYPE. RESULT is where the result will go (null
7080 for "call"s and "sibcall"s), ADDR is the address of the function,
7081 ARGS_SIZE is the size of the arguments and AUX is the value passed
7082 to us by mips_function_arg. LAZY_P is true if this call already
7083 involves a lazily-bound function address (such as when calling
7084 functions through a MIPS16 hard-float stub).
7086 Return the call itself. */
7089 mips_expand_call (enum mips_call_type type, rtx result, rtx addr,
7090 rtx args_size, rtx aux, bool lazy_p)
7092 rtx orig_addr, pattern;
7096 fp_code = aux == 0 ? 0 : (int) GET_MODE (aux);
7097 insn = mips16_build_call_stub (result, &addr, args_size, fp_code);
7100 gcc_assert (!lazy_p && type == MIPS_CALL_NORMAL);
7105 if (!call_insn_operand (addr, VOIDmode))
7107 if (type == MIPS_CALL_EPILOGUE)
7108 addr = MIPS_EPILOGUE_TEMP (Pmode);
7110 addr = gen_reg_rtx (Pmode);
7111 lazy_p |= mips_load_call_address (type, addr, orig_addr);
7116 rtx (*fn) (rtx, rtx);
7118 if (type == MIPS_CALL_SIBCALL)
7119 fn = gen_sibcall_internal;
7121 fn = gen_call_internal;
7123 pattern = fn (addr, args_size);
7125 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
7127 /* Handle return values created by mips_return_fpr_pair. */
7128 rtx (*fn) (rtx, rtx, rtx, rtx);
7131 if (type == MIPS_CALL_SIBCALL)
7132 fn = gen_sibcall_value_multiple_internal;
7134 fn = gen_call_value_multiple_internal;
7136 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
7137 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
7138 pattern = fn (reg1, addr, args_size, reg2);
7142 rtx (*fn) (rtx, rtx, rtx);
7144 if (type == MIPS_CALL_SIBCALL)
7145 fn = gen_sibcall_value_internal;
7147 fn = gen_call_value_internal;
7149 /* Handle return values created by mips_return_fpr_single. */
7150 if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 1)
7151 result = XEXP (XVECEXP (result, 0, 0), 0);
7152 pattern = fn (result, addr, args_size);
7155 return mips_emit_call_insn (pattern, orig_addr, addr, lazy_p);
7158 /* Split call instruction INSN into a $gp-clobbering call and
7159 (where necessary) an instruction to restore $gp from its save slot.
7160 CALL_PATTERN is the pattern of the new call. */
7163 mips_split_call (rtx insn, rtx call_pattern)
7165 emit_call_insn (call_pattern);
7166 if (!find_reg_note (insn, REG_NORETURN, 0))
7167 mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode,
7168 POST_CALL_TMP_REG));
7171 /* Return true if a call to DECL may need to use JALX. */
7174 mips_call_may_need_jalx_p (tree decl)
7176 /* If the current translation unit would use a different mode for DECL,
7177 assume that the call needs JALX. */
7178 if (mips_get_compress_mode (decl) != TARGET_COMPRESSION)
7181 /* mips_get_compress_mode is always accurate for locally-binding
7182 functions in the current translation unit. */
7183 if (!DECL_EXTERNAL (decl) && targetm.binds_local_p (decl))
7186 /* When -minterlink-compressed is in effect, assume that functions
7187 could use a different encoding mode unless an attribute explicitly
7188 tells us otherwise. */
7189 if (TARGET_INTERLINK_COMPRESSED)
7191 if (!TARGET_COMPRESSION
7192 && mips_get_compress_off_flags (DECL_ATTRIBUTES (decl)) ==0)
7194 if (TARGET_COMPRESSION
7195 && mips_get_compress_on_flags (DECL_ATTRIBUTES (decl)) == 0)
7202 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
7205 mips_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
7207 if (!TARGET_SIBCALLS)
7210 /* Interrupt handlers need special epilogue code and therefore can't
7212 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
7215 /* Direct Js are only possible to functions that use the same ISA encoding.
7216 There is no JX counterpoart of JALX. */
7218 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode)
7219 && mips_call_may_need_jalx_p (decl))
7222 /* Sibling calls should not prevent lazy binding. Lazy-binding stubs
7223 require $gp to be valid on entry, so sibcalls can only use stubs
7224 if $gp is call-clobbered. */
7226 && TARGET_CALL_SAVED_GP
7227 && !TARGET_ABICALLS_PIC0
7228 && !targetm.binds_local_p (decl))
7235 /* Implement TARGET_USE_MOVE_BY_PIECES_INFRASTRUCTURE_P. */
7238 mips_use_by_pieces_infrastructure_p (unsigned int size,
7240 enum by_pieces_operation op,
7243 if (op == STORE_BY_PIECES)
7244 return mips_store_by_pieces_p (size, align);
7245 if (op == MOVE_BY_PIECES && HAVE_movmemsi)
7247 /* movmemsi is meant to generate code that is at least as good as
7248 move_by_pieces. However, movmemsi effectively uses a by-pieces
7249 implementation both for moves smaller than a word and for
7250 word-aligned moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT
7251 bytes. We should allow the tree-level optimisers to do such
7252 moves by pieces, as it often exposes other optimization
7253 opportunities. We might as well continue to use movmemsi at
7254 the rtl level though, as it produces better code when
7255 scheduling is disabled (such as at -O). */
7256 if (currently_expanding_to_rtl)
7258 if (align < BITS_PER_WORD)
7259 return size < UNITS_PER_WORD;
7260 return size <= MIPS_MAX_MOVE_BYTES_STRAIGHT;
7263 return default_use_by_pieces_infrastructure_p (size, align, op, speed_p);
7266 /* Implement a handler for STORE_BY_PIECES operations
7267 for TARGET_USE_MOVE_BY_PIECES_INFRASTRUCTURE_P. */
7270 mips_store_by_pieces_p (unsigned HOST_WIDE_INT size, unsigned int align)
7272 /* Storing by pieces involves moving constants into registers
7273 of size MIN (ALIGN, BITS_PER_WORD), then storing them.
7274 We need to decide whether it is cheaper to load the address of
7275 constant data into a register and use a block move instead. */
7277 /* If the data is only byte aligned, then:
7279 (a1) A block move of less than 4 bytes would involve three 3 LBs and
7280 3 SBs. We might as well use 3 single-instruction LIs and 3 SBs
7283 (a2) A block move of 4 bytes from aligned source data can use an
7284 LW/SWL/SWR sequence. This is often better than the 4 LIs and
7285 4 SBs that we would generate when storing by pieces. */
7286 if (align <= BITS_PER_UNIT)
7289 /* If the data is 2-byte aligned, then:
7291 (b1) A block move of less than 4 bytes would use a combination of LBs,
7292 LHs, SBs and SHs. We get better code by using single-instruction
7293 LIs, SBs and SHs instead.
7295 (b2) A block move of 4 bytes from aligned source data would again use
7296 an LW/SWL/SWR sequence. In most cases, loading the address of
7297 the source data would require at least one extra instruction.
7298 It is often more efficient to use 2 single-instruction LIs and
7301 (b3) A block move of up to 3 additional bytes would be like (b1).
7303 (b4) A block move of 8 bytes from aligned source data can use two
7304 LW/SWL/SWR sequences or a single LD/SDL/SDR sequence. Both
7305 sequences are better than the 4 LIs and 4 SHs that we'd generate
7306 when storing by pieces.
7308 The reasoning for higher alignments is similar:
7310 (c1) A block move of less than 4 bytes would be the same as (b1).
7312 (c2) A block move of 4 bytes would use an LW/SW sequence. Again,
7313 loading the address of the source data would typically require
7314 at least one extra instruction. It is generally better to use
7317 (c3) A block move of up to 3 additional bytes would be like (b1).
7319 (c4) A block move of 8 bytes can use two LW/SW sequences or a single
7320 LD/SD sequence, and in these cases we've traditionally preferred
7321 the memory copy over the more bulky constant moves. */
7325 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
7326 Assume that the areas do not overlap. */
7329 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
7331 HOST_WIDE_INT offset, delta;
7332 unsigned HOST_WIDE_INT bits;
7337 /* Work out how many bits to move at a time. If both operands have
7338 half-word alignment, it is usually better to move in half words.
7339 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
7340 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
7341 Otherwise move word-sized chunks. */
7342 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
7343 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
7344 bits = BITS_PER_WORD / 2;
7346 bits = BITS_PER_WORD;
7348 mode = mode_for_size (bits, MODE_INT, 0);
7349 delta = bits / BITS_PER_UNIT;
7351 /* Allocate a buffer for the temporary registers. */
7352 regs = XALLOCAVEC (rtx, length / delta);
7354 /* Load as many BITS-sized chunks as possible. Use a normal load if
7355 the source has enough alignment, otherwise use left/right pairs. */
7356 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
7358 regs[i] = gen_reg_rtx (mode);
7359 if (MEM_ALIGN (src) >= bits)
7360 mips_emit_move (regs[i], adjust_address (src, mode, offset));
7363 rtx part = adjust_address (src, BLKmode, offset);
7364 set_mem_size (part, delta);
7365 if (!mips_expand_ext_as_unaligned_load (regs[i], part, bits, 0, 0))
7370 /* Copy the chunks to the destination. */
7371 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
7372 if (MEM_ALIGN (dest) >= bits)
7373 mips_emit_move (adjust_address (dest, mode, offset), regs[i]);
7376 rtx part = adjust_address (dest, BLKmode, offset);
7377 set_mem_size (part, delta);
7378 if (!mips_expand_ins_as_unaligned_store (part, regs[i], bits, 0))
7382 /* Mop up any left-over bytes. */
7383 if (offset < length)
7385 src = adjust_address (src, BLKmode, offset);
7386 dest = adjust_address (dest, BLKmode, offset);
7387 move_by_pieces (dest, src, length - offset,
7388 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
7392 /* Helper function for doing a loop-based block operation on memory
7393 reference MEM. Each iteration of the loop will operate on LENGTH
7396 Create a new base register for use within the loop and point it to
7397 the start of MEM. Create a new memory reference that uses this
7398 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
7401 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
7402 rtx *loop_reg, rtx *loop_mem)
7404 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
7406 /* Although the new mem does not refer to a known location,
7407 it does keep up to LENGTH bytes of alignment. */
7408 *loop_mem = change_address (mem, BLKmode, *loop_reg);
7409 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
7412 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
7413 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
7414 the memory regions do not overlap. */
7417 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length,
7418 HOST_WIDE_INT bytes_per_iter)
7420 rtx_code_label *label;
7421 rtx src_reg, dest_reg, final_src, test;
7422 HOST_WIDE_INT leftover;
7424 leftover = length % bytes_per_iter;
7427 /* Create registers and memory references for use within the loop. */
7428 mips_adjust_block_mem (src, bytes_per_iter, &src_reg, &src);
7429 mips_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest);
7431 /* Calculate the value that SRC_REG should have after the last iteration
7433 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
7436 /* Emit the start of the loop. */
7437 label = gen_label_rtx ();
7440 /* Emit the loop body. */
7441 mips_block_move_straight (dest, src, bytes_per_iter);
7443 /* Move on to the next block. */
7444 mips_emit_move (src_reg, plus_constant (Pmode, src_reg, bytes_per_iter));
7445 mips_emit_move (dest_reg, plus_constant (Pmode, dest_reg, bytes_per_iter));
7447 /* Emit the loop condition. */
7448 test = gen_rtx_NE (VOIDmode, src_reg, final_src);
7449 if (Pmode == DImode)
7450 emit_jump_insn (gen_cbranchdi4 (test, src_reg, final_src, label));
7452 emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label));
7454 /* Mop up any left-over bytes. */
7456 mips_block_move_straight (dest, src, leftover);
7459 /* Expand a movmemsi instruction, which copies LENGTH bytes from
7460 memory reference SRC to memory reference DEST. */
7463 mips_expand_block_move (rtx dest, rtx src, rtx length)
7465 if (CONST_INT_P (length))
7467 if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)
7469 mips_block_move_straight (dest, src, INTVAL (length));
7474 mips_block_move_loop (dest, src, INTVAL (length),
7475 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER);
7482 /* Expand a loop of synci insns for the address range [BEGIN, END). */
7485 mips_expand_synci_loop (rtx begin, rtx end)
7487 rtx inc, cmp_result, mask, length;
7488 rtx_code_label *label, *end_label;
7490 /* Create end_label. */
7491 end_label = gen_label_rtx ();
7493 /* Check if begin equals end. */
7494 cmp_result = gen_rtx_EQ (VOIDmode, begin, end);
7495 emit_jump_insn (gen_condjump (cmp_result, end_label));
7497 /* Load INC with the cache line size (rdhwr INC,$1). */
7498 inc = gen_reg_rtx (Pmode);
7499 emit_insn (PMODE_INSN (gen_rdhwr_synci_step, (inc)));
7501 /* Check if inc is 0. */
7502 cmp_result = gen_rtx_EQ (VOIDmode, inc, const0_rtx);
7503 emit_jump_insn (gen_condjump (cmp_result, end_label));
7505 /* Calculate mask. */
7506 mask = mips_force_unary (Pmode, NEG, inc);
7508 /* Mask out begin by mask. */
7509 begin = mips_force_binary (Pmode, AND, begin, mask);
7511 /* Calculate length. */
7512 length = mips_force_binary (Pmode, MINUS, end, begin);
7514 /* Loop back to here. */
7515 label = gen_label_rtx ();
7518 emit_insn (gen_synci (begin));
7520 /* Update length. */
7521 mips_emit_binary (MINUS, length, length, inc);
7524 mips_emit_binary (PLUS, begin, begin, inc);
7526 /* Check if length is greater than 0. */
7527 cmp_result = gen_rtx_GT (VOIDmode, length, const0_rtx);
7528 emit_jump_insn (gen_condjump (cmp_result, label));
7530 emit_label (end_label);
7533 /* Expand a QI or HI mode atomic memory operation.
7535 GENERATOR contains a pointer to the gen_* function that generates
7536 the SI mode underlying atomic operation using masks that we
7539 RESULT is the return register for the operation. Its value is NULL
7542 MEM is the location of the atomic access.
7544 OLDVAL is the first operand for the operation.
7546 NEWVAL is the optional second operand for the operation. Its value
7547 is NULL if unused. */
7550 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator,
7551 rtx result, rtx mem, rtx oldval, rtx newval)
7553 rtx orig_addr, memsi_addr, memsi, shift, shiftsi, unshifted_mask;
7554 rtx unshifted_mask_reg, mask, inverted_mask, si_op;
7558 mode = GET_MODE (mem);
7560 /* Compute the address of the containing SImode value. */
7561 orig_addr = force_reg (Pmode, XEXP (mem, 0));
7562 memsi_addr = mips_force_binary (Pmode, AND, orig_addr,
7563 force_reg (Pmode, GEN_INT (-4)));
7565 /* Create a memory reference for it. */
7566 memsi = gen_rtx_MEM (SImode, memsi_addr);
7567 set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER);
7568 MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem);
7570 /* Work out the byte offset of the QImode or HImode value,
7571 counting from the least significant byte. */
7572 shift = mips_force_binary (Pmode, AND, orig_addr, GEN_INT (3));
7573 if (TARGET_BIG_ENDIAN)
7574 mips_emit_binary (XOR, shift, shift, GEN_INT (mode == QImode ? 3 : 2));
7576 /* Multiply by eight to convert the shift value from bytes to bits. */
7577 mips_emit_binary (ASHIFT, shift, shift, GEN_INT (3));
7579 /* Make the final shift an SImode value, so that it can be used in
7580 SImode operations. */
7581 shiftsi = force_reg (SImode, gen_lowpart (SImode, shift));
7583 /* Set MASK to an inclusive mask of the QImode or HImode value. */
7584 unshifted_mask = GEN_INT (GET_MODE_MASK (mode));
7585 unshifted_mask_reg = force_reg (SImode, unshifted_mask);
7586 mask = mips_force_binary (SImode, ASHIFT, unshifted_mask_reg, shiftsi);
7588 /* Compute the equivalent exclusive mask. */
7589 inverted_mask = gen_reg_rtx (SImode);
7590 emit_insn (gen_rtx_SET (VOIDmode, inverted_mask,
7591 gen_rtx_NOT (SImode, mask)));
7593 /* Shift the old value into place. */
7594 if (oldval != const0_rtx)
7596 oldval = convert_modes (SImode, mode, oldval, true);
7597 oldval = force_reg (SImode, oldval);
7598 oldval = mips_force_binary (SImode, ASHIFT, oldval, shiftsi);
7601 /* Do the same for the new value. */
7602 if (newval && newval != const0_rtx)
7604 newval = convert_modes (SImode, mode, newval, true);
7605 newval = force_reg (SImode, newval);
7606 newval = mips_force_binary (SImode, ASHIFT, newval, shiftsi);
7609 /* Do the SImode atomic access. */
7611 res = gen_reg_rtx (SImode);
7613 si_op = generator.fn_6 (res, memsi, mask, inverted_mask, oldval, newval);
7615 si_op = generator.fn_5 (res, memsi, mask, inverted_mask, oldval);
7617 si_op = generator.fn_4 (memsi, mask, inverted_mask, oldval);
7623 /* Shift and convert the result. */
7624 mips_emit_binary (AND, res, res, mask);
7625 mips_emit_binary (LSHIFTRT, res, res, shiftsi);
7626 mips_emit_move (result, gen_lowpart (GET_MODE (result), res));
7630 /* Return true if it is possible to use left/right accesses for a
7631 bitfield of WIDTH bits starting BITPOS bits into BLKmode memory OP.
7632 When returning true, update *LEFT and *RIGHT as follows:
7634 *LEFT is a QImode reference to the first byte if big endian or
7635 the last byte if little endian. This address can be used in the
7636 left-side instructions (LWL, SWL, LDL, SDL).
7638 *RIGHT is a QImode reference to the opposite end of the field and
7639 can be used in the patterning right-side instruction. */
7642 mips_get_unaligned_mem (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos,
7643 rtx *left, rtx *right)
7647 /* Check that the size is valid. */
7648 if (width != 32 && (!TARGET_64BIT || width != 64))
7651 /* We can only access byte-aligned values. Since we are always passed
7652 a reference to the first byte of the field, it is not necessary to
7653 do anything with BITPOS after this check. */
7654 if (bitpos % BITS_PER_UNIT != 0)
7657 /* Reject aligned bitfields: we want to use a normal load or store
7658 instead of a left/right pair. */
7659 if (MEM_ALIGN (op) >= width)
7662 /* Get references to both ends of the field. */
7663 first = adjust_address (op, QImode, 0);
7664 last = adjust_address (op, QImode, width / BITS_PER_UNIT - 1);
7666 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
7667 correspond to the MSB and RIGHT to the LSB. */
7668 if (TARGET_BIG_ENDIAN)
7669 *left = first, *right = last;
7671 *left = last, *right = first;
7676 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
7677 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
7678 the operation is the equivalent of:
7680 (set DEST (*_extract SRC WIDTH BITPOS))
7682 Return true on success. */
7685 mips_expand_ext_as_unaligned_load (rtx dest, rtx src, HOST_WIDE_INT width,
7686 HOST_WIDE_INT bitpos, bool unsigned_p)
7688 rtx left, right, temp;
7689 rtx dest1 = NULL_RTX;
7691 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
7692 be a DImode, create a new temp and emit a zero extend at the end. */
7693 if (GET_MODE (dest) == DImode
7695 && GET_MODE_BITSIZE (SImode) == width)
7698 dest = gen_reg_rtx (SImode);
7701 if (!mips_get_unaligned_mem (src, width, bitpos, &left, &right))
7704 temp = gen_reg_rtx (GET_MODE (dest));
7705 if (GET_MODE (dest) == DImode)
7707 emit_insn (gen_mov_ldl (temp, src, left));
7708 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
7712 emit_insn (gen_mov_lwl (temp, src, left));
7713 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
7716 /* If we were loading 32bits and the original register was DI then
7717 sign/zero extend into the orignal dest. */
7721 emit_insn (gen_zero_extendsidi2 (dest1, dest));
7723 emit_insn (gen_extendsidi2 (dest1, dest));
7728 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
7729 BITPOS and SRC are the operands passed to the expander; the operation
7730 is the equivalent of:
7732 (set (zero_extract DEST WIDTH BITPOS) SRC)
7734 Return true on success. */
7737 mips_expand_ins_as_unaligned_store (rtx dest, rtx src, HOST_WIDE_INT width,
7738 HOST_WIDE_INT bitpos)
7743 if (!mips_get_unaligned_mem (dest, width, bitpos, &left, &right))
7746 mode = mode_for_size (width, MODE_INT, 0);
7747 src = gen_lowpart (mode, src);
7750 emit_insn (gen_mov_sdl (dest, src, left));
7751 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
7755 emit_insn (gen_mov_swl (dest, src, left));
7756 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
7761 /* Return true if X is a MEM with the same size as MODE. */
7764 mips_mem_fits_mode_p (machine_mode mode, rtx x)
7767 && MEM_SIZE_KNOWN_P (x)
7768 && MEM_SIZE (x) == GET_MODE_SIZE (mode));
7771 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
7772 source of an "ext" instruction or the destination of an "ins"
7773 instruction. OP must be a register operand and the following
7774 conditions must hold:
7776 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
7777 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7778 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7780 Also reject lengths equal to a word as they are better handled
7781 by the move patterns. */
7784 mips_use_ins_ext_p (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos)
7786 if (!ISA_HAS_EXT_INS
7787 || !register_operand (op, VOIDmode)
7788 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
7791 if (!IN_RANGE (width, 1, GET_MODE_BITSIZE (GET_MODE (op)) - 1))
7794 if (bitpos < 0 || bitpos + width > GET_MODE_BITSIZE (GET_MODE (op)))
7800 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
7801 operation if MAXLEN is the maxium length of consecutive bits that
7802 can make up MASK. MODE is the mode of the operation. See
7803 mask_low_and_shift_len for the actual definition. */
7806 mask_low_and_shift_p (machine_mode mode, rtx mask, rtx shift, int maxlen)
7808 return IN_RANGE (mask_low_and_shift_len (mode, mask, shift), 1, maxlen);
7811 /* Return true iff OP1 and OP2 are valid operands together for the
7812 *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider,
7813 see the table in the comment before the pattern. */
7816 and_operands_ok (machine_mode mode, rtx op1, rtx op2)
7818 return (memory_operand (op1, mode)
7819 ? and_load_operand (op2, mode)
7820 : and_reg_operand (op2, mode));
7823 /* The canonical form of a mask-low-and-shift-left operation is
7824 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
7825 cleared. Thus we need to shift MASK to the right before checking if it
7826 is a valid mask value. MODE is the mode of the operation. If true
7827 return the length of the mask, otherwise return -1. */
7830 mask_low_and_shift_len (machine_mode mode, rtx mask, rtx shift)
7832 HOST_WIDE_INT shval;
7834 shval = INTVAL (shift) & (GET_MODE_BITSIZE (mode) - 1);
7835 return exact_log2 ((UINTVAL (mask) >> shval) + 1);
7838 /* Return true if -msplit-addresses is selected and should be honored.
7840 -msplit-addresses is a half-way house between explicit relocations
7841 and the traditional assembler macros. It can split absolute 32-bit
7842 symbolic constants into a high/lo_sum pair but uses macros for other
7845 Like explicit relocation support for REL targets, it relies
7846 on GNU extensions in the assembler and the linker.
7848 Although this code should work for -O0, it has traditionally
7849 been treated as an optimization. */
7852 mips_split_addresses_p (void)
7854 return (TARGET_SPLIT_ADDRESSES
7858 && !ABI_HAS_64BIT_SYMBOLS);
7861 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
7864 mips_init_relocs (void)
7866 memset (mips_split_p, '\0', sizeof (mips_split_p));
7867 memset (mips_split_hi_p, '\0', sizeof (mips_split_hi_p));
7868 memset (mips_use_pcrel_pool_p, '\0', sizeof (mips_use_pcrel_pool_p));
7869 memset (mips_hi_relocs, '\0', sizeof (mips_hi_relocs));
7870 memset (mips_lo_relocs, '\0', sizeof (mips_lo_relocs));
7872 if (TARGET_MIPS16_PCREL_LOADS)
7873 mips_use_pcrel_pool_p[SYMBOL_ABSOLUTE] = true;
7876 if (ABI_HAS_64BIT_SYMBOLS)
7878 if (TARGET_EXPLICIT_RELOCS)
7880 mips_split_p[SYMBOL_64_HIGH] = true;
7881 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
7882 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
7884 mips_split_p[SYMBOL_64_MID] = true;
7885 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
7886 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
7888 mips_split_p[SYMBOL_64_LOW] = true;
7889 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
7890 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
7892 mips_split_p[SYMBOL_ABSOLUTE] = true;
7893 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
7898 if (TARGET_EXPLICIT_RELOCS
7899 || mips_split_addresses_p ()
7902 mips_split_p[SYMBOL_ABSOLUTE] = true;
7903 mips_hi_relocs[SYMBOL_ABSOLUTE] = "%hi(";
7904 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
7911 /* The high part is provided by a pseudo copy of $gp. */
7912 mips_split_p[SYMBOL_GP_RELATIVE] = true;
7913 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gprel(";
7915 else if (TARGET_EXPLICIT_RELOCS)
7916 /* Small data constants are kept whole until after reload,
7917 then lowered by mips_rewrite_small_data. */
7918 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gp_rel(";
7920 if (TARGET_EXPLICIT_RELOCS)
7922 mips_split_p[SYMBOL_GOT_PAGE_OFST] = true;
7925 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
7926 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%got_ofst(";
7930 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
7931 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%lo(";
7934 /* Expose the use of $28 as soon as possible. */
7935 mips_split_hi_p[SYMBOL_GOT_PAGE_OFST] = true;
7939 /* The HIGH and LO_SUM are matched by special .md patterns. */
7940 mips_split_p[SYMBOL_GOT_DISP] = true;
7942 mips_split_p[SYMBOL_GOTOFF_DISP] = true;
7943 mips_hi_relocs[SYMBOL_GOTOFF_DISP] = "%got_hi(";
7944 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_lo(";
7946 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
7947 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
7948 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
7953 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_disp(";
7955 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got(";
7956 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
7958 /* Expose the use of $28 as soon as possible. */
7959 mips_split_p[SYMBOL_GOT_DISP] = true;
7965 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
7966 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
7967 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
7970 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
7971 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
7973 if (TARGET_MIPS16_PCREL_LOADS)
7975 mips_use_pcrel_pool_p[SYMBOL_DTPREL] = true;
7976 mips_use_pcrel_pool_p[SYMBOL_TPREL] = true;
7980 mips_split_p[SYMBOL_DTPREL] = true;
7981 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
7982 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
7984 mips_split_p[SYMBOL_TPREL] = true;
7985 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
7986 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
7989 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
7990 mips_lo_relocs[SYMBOL_HALF] = "%half(";
7993 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
7994 in context CONTEXT. RELOCS is the array of relocations to use. */
7997 mips_print_operand_reloc (FILE *file, rtx op, enum mips_symbol_context context,
7998 const char **relocs)
8000 enum mips_symbol_type symbol_type;
8003 symbol_type = mips_classify_symbolic_expression (op, context);
8004 gcc_assert (relocs[symbol_type]);
8006 fputs (relocs[symbol_type], file);
8007 output_addr_const (file, mips_strip_unspec_address (op));
8008 for (p = relocs[symbol_type]; *p != 0; p++)
8013 /* Start a new block with the given asm switch enabled. If we need
8014 to print a directive, emit PREFIX before it and SUFFIX after it. */
8017 mips_push_asm_switch_1 (struct mips_asm_switch *asm_switch,
8018 const char *prefix, const char *suffix)
8020 if (asm_switch->nesting_level == 0)
8021 fprintf (asm_out_file, "%s.set\tno%s%s", prefix, asm_switch->name, suffix);
8022 asm_switch->nesting_level++;
8025 /* Likewise, but end a block. */
8028 mips_pop_asm_switch_1 (struct mips_asm_switch *asm_switch,
8029 const char *prefix, const char *suffix)
8031 gcc_assert (asm_switch->nesting_level);
8032 asm_switch->nesting_level--;
8033 if (asm_switch->nesting_level == 0)
8034 fprintf (asm_out_file, "%s.set\t%s%s", prefix, asm_switch->name, suffix);
8037 /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1
8038 that either print a complete line or print nothing. */
8041 mips_push_asm_switch (struct mips_asm_switch *asm_switch)
8043 mips_push_asm_switch_1 (asm_switch, "\t", "\n");
8047 mips_pop_asm_switch (struct mips_asm_switch *asm_switch)
8049 mips_pop_asm_switch_1 (asm_switch, "\t", "\n");
8052 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
8053 The punctuation characters are:
8055 '(' Start a nested ".set noreorder" block.
8056 ')' End a nested ".set noreorder" block.
8057 '[' Start a nested ".set noat" block.
8058 ']' End a nested ".set noat" block.
8059 '<' Start a nested ".set nomacro" block.
8060 '>' End a nested ".set nomacro" block.
8061 '*' Behave like %(%< if generating a delayed-branch sequence.
8062 '#' Print a nop if in a ".set noreorder" block.
8063 '/' Like '#', but do nothing within a delayed-branch sequence.
8064 '?' Print "l" if mips_branch_likely is true
8065 '~' Print a nop if mips_branch_likely is true
8066 '.' Print the name of the register with a hard-wired zero (zero or $0).
8067 '@' Print the name of the assembler temporary register (at or $1).
8068 '^' Print the name of the pic call-through register (t9 or $25).
8069 '+' Print the name of the gp register (usually gp or $28).
8070 '$' Print the name of the stack pointer register (sp or $29).
8071 ':' Print "c" to use the compact version if the delay slot is a nop.
8072 '!' Print "s" to use the short version if the delay slot contains a
8075 See also mips_init_print_operand_pucnt. */
8078 mips_print_operand_punctuation (FILE *file, int ch)
8083 mips_push_asm_switch_1 (&mips_noreorder, "", "\n\t");
8087 mips_pop_asm_switch_1 (&mips_noreorder, "\n\t", "");
8091 mips_push_asm_switch_1 (&mips_noat, "", "\n\t");
8095 mips_pop_asm_switch_1 (&mips_noat, "\n\t", "");
8099 mips_push_asm_switch_1 (&mips_nomacro, "", "\n\t");
8103 mips_pop_asm_switch_1 (&mips_nomacro, "\n\t", "");
8107 if (final_sequence != 0)
8109 mips_print_operand_punctuation (file, '(');
8110 mips_print_operand_punctuation (file, '<');
8115 if (mips_noreorder.nesting_level > 0)
8116 fputs ("\n\tnop", file);
8120 /* Print an extra newline so that the delayed insn is separated
8121 from the following ones. This looks neater and is consistent
8122 with non-nop delayed sequences. */
8123 if (mips_noreorder.nesting_level > 0 && final_sequence == 0)
8124 fputs ("\n\tnop\n", file);
8128 if (mips_branch_likely)
8133 if (mips_branch_likely)
8134 fputs ("\n\tnop", file);
8138 fputs (reg_names[GP_REG_FIRST + 0], file);
8142 fputs (reg_names[AT_REGNUM], file);
8146 fputs (reg_names[PIC_FUNCTION_ADDR_REGNUM], file);
8150 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
8154 fputs (reg_names[STACK_POINTER_REGNUM], file);
8158 /* When final_sequence is 0, the delay slot will be a nop. We can
8159 use the compact version for microMIPS. */
8160 if (final_sequence == 0)
8165 /* If the delay slot instruction is short, then use the
8167 if (final_sequence == 0
8168 || get_attr_length (final_sequence->insn (1)) == 2)
8178 /* Initialize mips_print_operand_punct. */
8181 mips_init_print_operand_punct (void)
8185 for (p = "()[]<>*#/?~.@^+$:!"; *p; p++)
8186 mips_print_operand_punct[(unsigned char) *p] = true;
8189 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
8190 associated with condition CODE. Print the condition part of the
8194 mips_print_int_branch_condition (FILE *file, enum rtx_code code, int letter)
8208 /* Conveniently, the MIPS names for these conditions are the same
8209 as their RTL equivalents. */
8210 fputs (GET_RTX_NAME (code), file);
8214 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
8219 /* Likewise floating-point branches. */
8222 mips_print_float_branch_condition (FILE *file, enum rtx_code code, int letter)
8227 fputs ("c1f", file);
8231 fputs ("c1t", file);
8235 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
8240 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
8243 mips_print_operand_punct_valid_p (unsigned char code)
8245 return mips_print_operand_punct[code];
8248 /* Implement TARGET_PRINT_OPERAND. The MIPS-specific operand codes are:
8250 'X' Print CONST_INT OP in hexadecimal format.
8251 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
8252 'd' Print CONST_INT OP in decimal.
8253 'm' Print one less than CONST_INT OP in decimal.
8254 'h' Print the high-part relocation associated with OP, after stripping
8256 'R' Print the low-part relocation associated with OP.
8257 'C' Print the integer branch condition for comparison OP.
8258 'N' Print the inverse of the integer branch condition for comparison OP.
8259 'F' Print the FPU branch condition for comparison OP.
8260 'W' Print the inverse of the FPU branch condition for comparison OP.
8261 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
8262 'z' for (eq:?I ...), 'n' for (ne:?I ...).
8263 't' Like 'T', but with the EQ/NE cases reversed
8264 'Y' Print mips_fp_conditions[INTVAL (OP)]
8265 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
8266 'q' Print a DSP accumulator register.
8267 'D' Print the second part of a double-word register or memory operand.
8268 'L' Print the low-order register in a double-word register operand.
8269 'M' Print high-order register in a double-word register operand.
8270 'z' Print $0 if OP is zero, otherwise print OP normally.
8271 'b' Print the address of a memory operand, without offset. */
8274 mips_print_operand (FILE *file, rtx op, int letter)
8278 if (mips_print_operand_punct_valid_p (letter))
8280 mips_print_operand_punctuation (file, letter);
8285 code = GET_CODE (op);
8290 if (CONST_INT_P (op))
8291 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
8293 output_operand_lossage ("invalid use of '%%%c'", letter);
8297 if (CONST_INT_P (op))
8298 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op) & 0xffff);
8300 output_operand_lossage ("invalid use of '%%%c'", letter);
8304 if (CONST_INT_P (op))
8305 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op));
8307 output_operand_lossage ("invalid use of '%%%c'", letter);
8311 if (CONST_INT_P (op))
8312 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op) - 1);
8314 output_operand_lossage ("invalid use of '%%%c'", letter);
8320 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_hi_relocs);
8324 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_lo_relocs);
8328 mips_print_int_branch_condition (file, code, letter);
8332 mips_print_int_branch_condition (file, reverse_condition (code), letter);
8336 mips_print_float_branch_condition (file, code, letter);
8340 mips_print_float_branch_condition (file, reverse_condition (code),
8347 int truth = (code == NE) == (letter == 'T');
8348 fputc ("zfnt"[truth * 2 + ST_REG_P (REGNO (XEXP (op, 0)))], file);
8353 if (code == CONST_INT && UINTVAL (op) < ARRAY_SIZE (mips_fp_conditions))
8354 fputs (mips_fp_conditions[UINTVAL (op)], file);
8356 output_operand_lossage ("'%%%c' is not a valid operand prefix",
8363 mips_print_operand (file, op, 0);
8369 if (code == REG && MD_REG_P (REGNO (op)))
8370 fprintf (file, "$ac0");
8371 else if (code == REG && DSP_ACC_REG_P (REGNO (op)))
8372 fprintf (file, "$ac%c", reg_names[REGNO (op)][3]);
8374 output_operand_lossage ("invalid use of '%%%c'", letter);
8382 unsigned int regno = REGNO (op);
8383 if ((letter == 'M' && TARGET_LITTLE_ENDIAN)
8384 || (letter == 'L' && TARGET_BIG_ENDIAN)
8387 else if (letter && letter != 'z' && letter != 'M' && letter != 'L')
8388 output_operand_lossage ("invalid use of '%%%c'", letter);
8389 /* We need to print $0 .. $31 for COP0 registers. */
8390 if (COP0_REG_P (regno))
8391 fprintf (file, "$%s", ®_names[regno][4]);
8393 fprintf (file, "%s", reg_names[regno]);
8399 output_address (plus_constant (Pmode, XEXP (op, 0), 4));
8400 else if (letter == 'b')
8402 gcc_assert (REG_P (XEXP (op, 0)));
8403 mips_print_operand (file, XEXP (op, 0), 0);
8405 else if (letter && letter != 'z')
8406 output_operand_lossage ("invalid use of '%%%c'", letter);
8408 output_address (XEXP (op, 0));
8412 if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
8413 fputs (reg_names[GP_REG_FIRST], file);
8414 else if (letter && letter != 'z')
8415 output_operand_lossage ("invalid use of '%%%c'", letter);
8416 else if (CONST_GP_P (op))
8417 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
8419 output_addr_const (file, mips_strip_unspec_address (op));
8425 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
8428 mips_print_operand_address (FILE *file, rtx x)
8430 struct mips_address_info addr;
8432 if (mips_classify_address (&addr, x, word_mode, true))
8436 mips_print_operand (file, addr.offset, 0);
8437 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
8440 case ADDRESS_LO_SUM:
8441 mips_print_operand_reloc (file, addr.offset, SYMBOL_CONTEXT_MEM,
8443 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
8446 case ADDRESS_CONST_INT:
8447 output_addr_const (file, x);
8448 fprintf (file, "(%s)", reg_names[GP_REG_FIRST]);
8451 case ADDRESS_SYMBOLIC:
8452 output_addr_const (file, mips_strip_unspec_address (x));
8458 /* Implement TARGET_ENCODE_SECTION_INFO. */
8461 mips_encode_section_info (tree decl, rtx rtl, int first)
8463 default_encode_section_info (decl, rtl, first);
8465 if (TREE_CODE (decl) == FUNCTION_DECL)
8467 rtx symbol = XEXP (rtl, 0);
8468 tree type = TREE_TYPE (decl);
8470 /* Encode whether the symbol is short or long. */
8471 if ((TARGET_LONG_CALLS && !mips_near_type_p (type))
8472 || mips_far_type_p (type))
8473 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
8477 /* Implement TARGET_SELECT_RTX_SECTION. */
8480 mips_select_rtx_section (machine_mode mode, rtx x,
8481 unsigned HOST_WIDE_INT align)
8483 /* ??? Consider using mergeable small data sections. */
8484 if (mips_rtx_constant_in_small_data_p (mode))
8485 return get_named_section (NULL, ".sdata", 0);
8487 return default_elf_select_rtx_section (mode, x, align);
8490 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
8492 The complication here is that, with the combination TARGET_ABICALLS
8493 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
8494 absolute addresses, and should therefore not be included in the
8495 read-only part of a DSO. Handle such cases by selecting a normal
8496 data section instead of a read-only one. The logic apes that in
8497 default_function_rodata_section. */
8500 mips_function_rodata_section (tree decl)
8502 if (!TARGET_ABICALLS || TARGET_ABSOLUTE_ABICALLS || TARGET_GPWORD)
8503 return default_function_rodata_section (decl);
8505 if (decl && DECL_SECTION_NAME (decl))
8507 const char *name = DECL_SECTION_NAME (decl);
8508 if (DECL_COMDAT_GROUP (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
8510 char *rname = ASTRDUP (name);
8512 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
8514 else if (flag_function_sections
8515 && flag_data_sections
8516 && strncmp (name, ".text.", 6) == 0)
8518 char *rname = ASTRDUP (name);
8519 memcpy (rname + 1, "data", 4);
8520 return get_section (rname, SECTION_WRITE, decl);
8523 return data_section;
8526 /* Implement TARGET_IN_SMALL_DATA_P. */
8529 mips_in_small_data_p (const_tree decl)
8531 unsigned HOST_WIDE_INT size;
8533 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
8536 /* We don't yet generate small-data references for -mabicalls
8537 or VxWorks RTP code. See the related -G handling in
8538 mips_option_override. */
8539 if (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
8542 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
8546 /* Reject anything that isn't in a known small-data section. */
8547 name = DECL_SECTION_NAME (decl);
8548 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
8551 /* If a symbol is defined externally, the assembler will use the
8552 usual -G rules when deciding how to implement macros. */
8553 if (mips_lo_relocs[SYMBOL_GP_RELATIVE] || !DECL_EXTERNAL (decl))
8556 else if (TARGET_EMBEDDED_DATA)
8558 /* Don't put constants into the small data section: we want them
8559 to be in ROM rather than RAM. */
8560 if (TREE_CODE (decl) != VAR_DECL)
8563 if (TREE_READONLY (decl)
8564 && !TREE_SIDE_EFFECTS (decl)
8565 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
8569 /* Enforce -mlocal-sdata. */
8570 if (!TARGET_LOCAL_SDATA && !TREE_PUBLIC (decl))
8573 /* Enforce -mextern-sdata. */
8574 if (!TARGET_EXTERN_SDATA && DECL_P (decl))
8576 if (DECL_EXTERNAL (decl))
8578 if (DECL_COMMON (decl) && DECL_INITIAL (decl) == NULL)
8582 /* We have traditionally not treated zero-sized objects as small data,
8583 so this is now effectively part of the ABI. */
8584 size = int_size_in_bytes (TREE_TYPE (decl));
8585 return size > 0 && size <= mips_small_data_threshold;
8588 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
8589 anchors for small data: the GP register acts as an anchor in that
8590 case. We also don't want to use them for PC-relative accesses,
8591 where the PC acts as an anchor. */
8594 mips_use_anchors_for_symbol_p (const_rtx symbol)
8596 switch (mips_classify_symbol (symbol, SYMBOL_CONTEXT_MEM))
8598 case SYMBOL_PC_RELATIVE:
8599 case SYMBOL_GP_RELATIVE:
8603 return default_use_anchors_for_symbol_p (symbol);
8607 /* The MIPS debug format wants all automatic variables and arguments
8608 to be in terms of the virtual frame pointer (stack pointer before
8609 any adjustment in the function), while the MIPS 3.0 linker wants
8610 the frame pointer to be the stack pointer after the initial
8611 adjustment. So, we do the adjustment here. The arg pointer (which
8612 is eliminated) points to the virtual frame pointer, while the frame
8613 pointer (which may be eliminated) points to the stack pointer after
8614 the initial adjustments. */
8617 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
8619 rtx offset2 = const0_rtx;
8620 rtx reg = eliminate_constant_term (addr, &offset2);
8623 offset = INTVAL (offset2);
8625 if (reg == stack_pointer_rtx
8626 || reg == frame_pointer_rtx
8627 || reg == hard_frame_pointer_rtx)
8629 offset -= cfun->machine->frame.total_size;
8630 if (reg == hard_frame_pointer_rtx)
8631 offset += cfun->machine->frame.hard_frame_pointer_offset;
8637 /* Implement ASM_OUTPUT_EXTERNAL. */
8640 mips_output_external (FILE *file, tree decl, const char *name)
8642 default_elf_asm_output_external (file, decl, name);
8644 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
8645 set in order to avoid putting out names that are never really
8647 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
8649 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
8651 /* When using assembler macros, emit .extern directives for
8652 all small-data externs so that the assembler knows how
8655 In most cases it would be safe (though pointless) to emit
8656 .externs for other symbols too. One exception is when an
8657 object is within the -G limit but declared by the user to
8658 be in a section other than .sbss or .sdata. */
8659 fputs ("\t.extern\t", file);
8660 assemble_name (file, name);
8661 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n",
8662 int_size_in_bytes (TREE_TYPE (decl)));
8667 /* Implement TARGET_ASM_OUTPUT_SOURCE_FILENAME. */
8670 mips_output_filename (FILE *stream, const char *name)
8672 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
8674 if (write_symbols == DWARF2_DEBUG)
8676 else if (mips_output_filename_first_time)
8678 mips_output_filename_first_time = 0;
8679 num_source_filenames += 1;
8680 current_function_file = name;
8681 fprintf (stream, "\t.file\t%d ", num_source_filenames);
8682 output_quoted_string (stream, name);
8683 putc ('\n', stream);
8685 /* If we are emitting stabs, let dbxout.c handle this (except for
8686 the mips_output_filename_first_time case). */
8687 else if (write_symbols == DBX_DEBUG)
8689 else if (name != current_function_file
8690 && strcmp (name, current_function_file) != 0)
8692 num_source_filenames += 1;
8693 current_function_file = name;
8694 fprintf (stream, "\t.file\t%d ", num_source_filenames);
8695 output_quoted_string (stream, name);
8696 putc ('\n', stream);
8700 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
8702 static void ATTRIBUTE_UNUSED
8703 mips_output_dwarf_dtprel (FILE *file, int size, rtx x)
8708 fputs ("\t.dtprelword\t", file);
8712 fputs ("\t.dtpreldword\t", file);
8718 output_addr_const (file, x);
8719 fputs ("+0x8000", file);
8722 /* Implement TARGET_DWARF_REGISTER_SPAN. */
8725 mips_dwarf_register_span (rtx reg)
8730 /* TARGET_FLOATXX is implemented as 32-bit floating-point registers but
8731 ensures that double-precision registers are treated as if they were
8732 64-bit physical registers. The code will run correctly with 32-bit or
8733 64-bit registers which means that dwarf information cannot be precise
8734 for all scenarios. We choose to state that the 64-bit values are stored
8735 in a single 64-bit 'piece'. This slightly unusual construct can then be
8736 interpreted as either a pair of registers if the registers are 32-bit or
8737 a single 64-bit register depending on hardware. */
8738 mode = GET_MODE (reg);
8739 if (FP_REG_P (REGNO (reg))
8741 && GET_MODE_SIZE (mode) > UNITS_PER_FPREG)
8743 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, reg));
8745 /* By default, GCC maps increasing register numbers to increasing
8746 memory locations, but paired FPRs are always little-endian,
8747 regardless of the prevailing endianness. */
8748 else if (FP_REG_P (REGNO (reg))
8749 && TARGET_BIG_ENDIAN
8750 && MAX_FPRS_PER_FMT > 1
8751 && GET_MODE_SIZE (mode) > UNITS_PER_FPREG)
8753 gcc_assert (GET_MODE_SIZE (mode) == UNITS_PER_HWFPVALUE);
8754 high = mips_subword (reg, true);
8755 low = mips_subword (reg, false);
8756 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, high, low));
8762 /* Implement TARGET_DWARF_FRAME_REG_MODE. */
8765 mips_dwarf_frame_reg_mode (int regno)
8767 machine_mode mode = default_dwarf_frame_reg_mode (regno);
8769 if (FP_REG_P (regno) && mips_abi == ABI_32 && TARGET_FLOAT64)
8775 /* DSP ALU can bypass data with no delays for the following pairs. */
8776 enum insn_code dspalu_bypass_table[][2] =
8778 {CODE_FOR_mips_addsc, CODE_FOR_mips_addwc},
8779 {CODE_FOR_mips_cmpu_eq_qb, CODE_FOR_mips_pick_qb},
8780 {CODE_FOR_mips_cmpu_lt_qb, CODE_FOR_mips_pick_qb},
8781 {CODE_FOR_mips_cmpu_le_qb, CODE_FOR_mips_pick_qb},
8782 {CODE_FOR_mips_cmp_eq_ph, CODE_FOR_mips_pick_ph},
8783 {CODE_FOR_mips_cmp_lt_ph, CODE_FOR_mips_pick_ph},
8784 {CODE_FOR_mips_cmp_le_ph, CODE_FOR_mips_pick_ph},
8785 {CODE_FOR_mips_wrdsp, CODE_FOR_mips_insv}
8789 mips_dspalu_bypass_p (rtx out_insn, rtx in_insn)
8792 int num_bypass = ARRAY_SIZE (dspalu_bypass_table);
8793 enum insn_code out_icode = (enum insn_code) INSN_CODE (out_insn);
8794 enum insn_code in_icode = (enum insn_code) INSN_CODE (in_insn);
8796 for (i = 0; i < num_bypass; i++)
8798 if (out_icode == dspalu_bypass_table[i][0]
8799 && in_icode == dspalu_bypass_table[i][1])
8805 /* Implement ASM_OUTPUT_ASCII. */
8808 mips_output_ascii (FILE *stream, const char *string, size_t len)
8814 fprintf (stream, "\t.ascii\t\"");
8815 for (i = 0; i < len; i++)
8819 c = (unsigned char) string[i];
8822 if (c == '\\' || c == '\"')
8824 putc ('\\', stream);
8832 fprintf (stream, "\\%03o", c);
8836 if (cur_pos > 72 && i+1 < len)
8839 fprintf (stream, "\"\n\t.ascii\t\"");
8842 fprintf (stream, "\"\n");
8845 /* Return the pseudo-op for full SYMBOL_(D)TPREL address *ADDR.
8846 Update *ADDR with the operand that should be printed. */
8849 mips_output_tls_reloc_directive (rtx *addr)
8851 enum mips_symbol_type type;
8853 type = mips_classify_symbolic_expression (*addr, SYMBOL_CONTEXT_LEA);
8854 *addr = mips_strip_unspec_address (*addr);
8858 return Pmode == SImode ? ".dtprelword\t%0" : ".dtpreldword\t%0";
8861 return Pmode == SImode ? ".tprelword\t%0" : ".tpreldword\t%0";
8868 /* Emit either a label, .comm, or .lcomm directive. When using assembler
8869 macros, mark the symbol as written so that mips_asm_output_external
8870 won't emit an .extern for it. STREAM is the output file, NAME is the
8871 name of the symbol, INIT_STRING is the string that should be written
8872 before the symbol and FINAL_STRING is the string that should be
8873 written after it. FINAL_STRING is a printf format that consumes the
8874 remaining arguments. */
8877 mips_declare_object (FILE *stream, const char *name, const char *init_string,
8878 const char *final_string, ...)
8882 fputs (init_string, stream);
8883 assemble_name (stream, name);
8884 va_start (ap, final_string);
8885 vfprintf (stream, final_string, ap);
8888 if (!TARGET_EXPLICIT_RELOCS)
8890 tree name_tree = get_identifier (name);
8891 TREE_ASM_WRITTEN (name_tree) = 1;
8895 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
8896 NAME is the name of the object and ALIGN is the required alignment
8897 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
8898 alignment argument. */
8901 mips_declare_common_object (FILE *stream, const char *name,
8902 const char *init_string,
8903 unsigned HOST_WIDE_INT size,
8904 unsigned int align, bool takes_alignment_p)
8906 if (!takes_alignment_p)
8908 size += (align / BITS_PER_UNIT) - 1;
8909 size -= size % (align / BITS_PER_UNIT);
8910 mips_declare_object (stream, name, init_string,
8911 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
8914 mips_declare_object (stream, name, init_string,
8915 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
8916 size, align / BITS_PER_UNIT);
8919 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
8920 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
8923 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
8924 unsigned HOST_WIDE_INT size,
8927 /* If the target wants uninitialized const declarations in
8928 .rdata then don't put them in .comm. */
8929 if (TARGET_EMBEDDED_DATA
8930 && TARGET_UNINIT_CONST_IN_RODATA
8931 && TREE_CODE (decl) == VAR_DECL
8932 && TREE_READONLY (decl)
8933 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
8935 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
8936 targetm.asm_out.globalize_label (stream, name);
8938 switch_to_section (readonly_data_section);
8939 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
8940 mips_declare_object (stream, name, "",
8941 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
8945 mips_declare_common_object (stream, name, "\n\t.comm\t",
8949 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8950 extern int size_directive_output;
8952 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
8953 definitions except that it uses mips_declare_object to emit the label. */
8956 mips_declare_object_name (FILE *stream, const char *name,
8957 tree decl ATTRIBUTE_UNUSED)
8959 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8960 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
8963 size_directive_output = 0;
8964 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
8968 size_directive_output = 1;
8969 size = int_size_in_bytes (TREE_TYPE (decl));
8970 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8973 mips_declare_object (stream, name, "", ":\n");
8976 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
8979 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
8983 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
8984 if (!flag_inhibit_size_directive
8985 && DECL_SIZE (decl) != 0
8988 && DECL_INITIAL (decl) == error_mark_node
8989 && !size_directive_output)
8993 size_directive_output = 1;
8994 size = int_size_in_bytes (TREE_TYPE (decl));
8995 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
9000 /* Return the FOO in the name of the ".mdebug.FOO" section associated
9001 with the current ABI. */
9004 mips_mdebug_abi_name (void)
9017 return TARGET_64BIT ? "eabi64" : "eabi32";
9023 /* Implement TARGET_ASM_FILE_START. */
9026 mips_file_start (void)
9028 default_file_start ();
9030 /* Generate a special section to describe the ABI switches used to
9031 produce the resultant binary. */
9033 /* Record the ABI itself. Modern versions of binutils encode
9034 this information in the ELF header flags, but GDB needs the
9035 information in order to correctly debug binaries produced by
9036 older binutils. See the function mips_gdbarch_init in
9038 fprintf (asm_out_file, "\t.section .mdebug.%s\n\t.previous\n",
9039 mips_mdebug_abi_name ());
9041 /* There is no ELF header flag to distinguish long32 forms of the
9042 EABI from long64 forms. Emit a special section to help tools
9043 such as GDB. Do the same for o64, which is sometimes used with
9045 if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
9046 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n"
9047 "\t.previous\n", TARGET_LONG64 ? 64 : 32);
9049 /* Record the NaN encoding. */
9050 if (HAVE_AS_NAN || mips_nan != MIPS_IEEE_754_DEFAULT)
9051 fprintf (asm_out_file, "\t.nan\t%s\n",
9052 mips_nan == MIPS_IEEE_754_2008 ? "2008" : "legacy");
9054 #ifdef HAVE_AS_DOT_MODULE
9055 /* Record the FP ABI. See below for comments. */
9056 if (TARGET_NO_FLOAT)
9057 #ifdef HAVE_AS_GNU_ATTRIBUTE
9058 fputs ("\t.gnu_attribute 4, 0\n", asm_out_file);
9062 else if (!TARGET_HARD_FLOAT_ABI)
9063 fputs ("\t.module\tsoftfloat\n", asm_out_file);
9064 else if (!TARGET_DOUBLE_FLOAT)
9065 fputs ("\t.module\tsinglefloat\n", asm_out_file);
9066 else if (TARGET_FLOATXX)
9067 fputs ("\t.module\tfp=xx\n", asm_out_file);
9068 else if (TARGET_FLOAT64)
9069 fputs ("\t.module\tfp=64\n", asm_out_file);
9071 fputs ("\t.module\tfp=32\n", asm_out_file);
9073 if (TARGET_ODD_SPREG)
9074 fputs ("\t.module\toddspreg\n", asm_out_file);
9076 fputs ("\t.module\tnooddspreg\n", asm_out_file);
9079 #ifdef HAVE_AS_GNU_ATTRIBUTE
9083 /* No floating-point operations, -mno-float. */
9084 if (TARGET_NO_FLOAT)
9086 /* Soft-float code, -msoft-float. */
9087 else if (!TARGET_HARD_FLOAT_ABI)
9089 /* Single-float code, -msingle-float. */
9090 else if (!TARGET_DOUBLE_FLOAT)
9092 /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64.
9094 This case used 12 callee-saved double-precision registers
9095 and is deprecated. */
9096 /* 64-bit or 32-bit FP registers on a 32-bit target, -mfpxx. */
9097 else if (TARGET_FLOATXX)
9099 /* 64-bit FP registers on a 32-bit target, -mfp64 -modd-spreg. */
9100 else if (mips_abi == ABI_32 && TARGET_FLOAT64 && TARGET_ODD_SPREG)
9102 /* 64-bit FP registers on a 32-bit target, -mfp64 -mno-odd-spreg. */
9103 else if (mips_abi == ABI_32 && TARGET_FLOAT64)
9105 /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */
9109 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n", attr);
9114 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
9115 if (TARGET_ABICALLS)
9117 fprintf (asm_out_file, "\t.abicalls\n");
9118 if (TARGET_ABICALLS_PIC0)
9119 fprintf (asm_out_file, "\t.option\tpic0\n");
9122 if (flag_verbose_asm)
9123 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
9125 mips_small_data_threshold, mips_arch_info->name, mips_isa);
9128 /* Implement TARGET_ASM_CODE_END. */
9131 mips_code_end (void)
9133 mips_finish_stub (&mips16_rdhwr_stub);
9134 mips_finish_stub (&mips16_get_fcsr_stub);
9135 mips_finish_stub (&mips16_set_fcsr_stub);
9138 /* Make the last instruction frame-related and note that it performs
9139 the operation described by FRAME_PATTERN. */
9142 mips_set_frame_expr (rtx frame_pattern)
9146 insn = get_last_insn ();
9147 RTX_FRAME_RELATED_P (insn) = 1;
9148 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
9153 /* Return a frame-related rtx that stores REG at MEM.
9154 REG must be a single register. */
9157 mips_frame_set (rtx mem, rtx reg)
9161 set = gen_rtx_SET (VOIDmode, mem, reg);
9162 RTX_FRAME_RELATED_P (set) = 1;
9167 /* Record that the epilogue has restored call-saved register REG. */
9170 mips_add_cfa_restore (rtx reg)
9172 mips_epilogue.cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg,
9173 mips_epilogue.cfa_restores);
9176 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
9177 mips16e_s2_s8_regs[X], it must also save the registers in indexes
9178 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
9179 static const unsigned char mips16e_s2_s8_regs[] = {
9180 30, 23, 22, 21, 20, 19, 18
9182 static const unsigned char mips16e_a0_a3_regs[] = {
9186 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
9187 ordered from the uppermost in memory to the lowest in memory. */
9188 static const unsigned char mips16e_save_restore_regs[] = {
9189 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
9192 /* Return the index of the lowest X in the range [0, SIZE) for which
9193 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
9196 mips16e_find_first_register (unsigned int mask, const unsigned char *regs,
9201 for (i = 0; i < size; i++)
9202 if (BITSET_P (mask, regs[i]))
9208 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
9209 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
9210 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
9211 is true for all indexes (X, SIZE). */
9214 mips16e_mask_registers (unsigned int *mask_ptr, const unsigned char *regs,
9215 unsigned int size, unsigned int *num_regs_ptr)
9219 i = mips16e_find_first_register (*mask_ptr, regs, size);
9220 for (i++; i < size; i++)
9221 if (!BITSET_P (*mask_ptr, regs[i]))
9224 *mask_ptr |= 1 << regs[i];
9228 /* Return a simplified form of X using the register values in REG_VALUES.
9229 REG_VALUES[R] is the last value assigned to hard register R, or null
9230 if R has not been modified.
9232 This function is rather limited, but is good enough for our purposes. */
9235 mips16e_collect_propagate_value (rtx x, rtx *reg_values)
9237 x = avoid_constant_pool_reference (x);
9241 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
9242 return simplify_gen_unary (GET_CODE (x), GET_MODE (x),
9243 x0, GET_MODE (XEXP (x, 0)));
9246 if (ARITHMETIC_P (x))
9248 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
9249 rtx x1 = mips16e_collect_propagate_value (XEXP (x, 1), reg_values);
9250 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), x0, x1);
9254 && reg_values[REGNO (x)]
9255 && !rtx_unstable_p (reg_values[REGNO (x)]))
9256 return reg_values[REGNO (x)];
9261 /* Return true if (set DEST SRC) stores an argument register into its
9262 caller-allocated save slot, storing the number of that argument
9263 register in *REGNO_PTR if so. REG_VALUES is as for
9264 mips16e_collect_propagate_value. */
9267 mips16e_collect_argument_save_p (rtx dest, rtx src, rtx *reg_values,
9268 unsigned int *regno_ptr)
9270 unsigned int argno, regno;
9271 HOST_WIDE_INT offset, required_offset;
9274 /* Check that this is a word-mode store. */
9275 if (!MEM_P (dest) || !REG_P (src) || GET_MODE (dest) != word_mode)
9278 /* Check that the register being saved is an unmodified argument
9280 regno = REGNO (src);
9281 if (!IN_RANGE (regno, GP_ARG_FIRST, GP_ARG_LAST) || reg_values[regno])
9283 argno = regno - GP_ARG_FIRST;
9285 /* Check whether the address is an appropriate stack-pointer or
9286 frame-pointer access. */
9287 addr = mips16e_collect_propagate_value (XEXP (dest, 0), reg_values);
9288 mips_split_plus (addr, &base, &offset);
9289 required_offset = cfun->machine->frame.total_size + argno * UNITS_PER_WORD;
9290 if (base == hard_frame_pointer_rtx)
9291 required_offset -= cfun->machine->frame.hard_frame_pointer_offset;
9292 else if (base != stack_pointer_rtx)
9294 if (offset != required_offset)
9301 /* A subroutine of mips_expand_prologue, called only when generating
9302 MIPS16e SAVE instructions. Search the start of the function for any
9303 instructions that save argument registers into their caller-allocated
9304 save slots. Delete such instructions and return a value N such that
9305 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
9306 instructions redundant. */
9309 mips16e_collect_argument_saves (void)
9311 rtx reg_values[FIRST_PSEUDO_REGISTER];
9312 rtx_insn *insn, *next;
9314 unsigned int nargs, regno;
9316 push_topmost_sequence ();
9318 memset (reg_values, 0, sizeof (reg_values));
9319 for (insn = get_insns (); insn; insn = next)
9321 next = NEXT_INSN (insn);
9322 if (NOTE_P (insn) || DEBUG_INSN_P (insn))
9328 set = PATTERN (insn);
9329 if (GET_CODE (set) != SET)
9332 dest = SET_DEST (set);
9333 src = SET_SRC (set);
9334 if (mips16e_collect_argument_save_p (dest, src, reg_values, ®no))
9336 if (!BITSET_P (cfun->machine->frame.mask, regno))
9339 nargs = MAX (nargs, (regno - GP_ARG_FIRST) + 1);
9342 else if (REG_P (dest) && GET_MODE (dest) == word_mode)
9343 reg_values[REGNO (dest)]
9344 = mips16e_collect_propagate_value (src, reg_values);
9348 pop_topmost_sequence ();
9353 /* Return a move between register REGNO and memory location SP + OFFSET.
9354 REG_PARM_P is true if SP + OFFSET belongs to REG_PARM_STACK_SPACE.
9355 Make the move a load if RESTORE_P, otherwise make it a store. */
9358 mips16e_save_restore_reg (bool restore_p, bool reg_parm_p,
9359 HOST_WIDE_INT offset, unsigned int regno)
9363 mem = gen_frame_mem (SImode, plus_constant (Pmode, stack_pointer_rtx,
9365 reg = gen_rtx_REG (SImode, regno);
9368 mips_add_cfa_restore (reg);
9369 return gen_rtx_SET (VOIDmode, reg, mem);
9372 return gen_rtx_SET (VOIDmode, mem, reg);
9373 return mips_frame_set (mem, reg);
9376 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
9377 The instruction must:
9379 - Allocate or deallocate SIZE bytes in total; SIZE is known
9382 - Save or restore as many registers in *MASK_PTR as possible.
9383 The instruction saves the first registers at the top of the
9384 allocated area, with the other registers below it.
9386 - Save NARGS argument registers above the allocated area.
9388 (NARGS is always zero if RESTORE_P.)
9390 The SAVE and RESTORE instructions cannot save and restore all general
9391 registers, so there may be some registers left over for the caller to
9392 handle. Destructively modify *MASK_PTR so that it contains the registers
9393 that still need to be saved or restored. The caller can save these
9394 registers in the memory immediately below *OFFSET_PTR, which is a
9395 byte offset from the bottom of the allocated stack area. */
9398 mips16e_build_save_restore (bool restore_p, unsigned int *mask_ptr,
9399 HOST_WIDE_INT *offset_ptr, unsigned int nargs,
9403 HOST_WIDE_INT offset, top_offset;
9404 unsigned int i, regno;
9407 gcc_assert (cfun->machine->frame.num_fp == 0);
9409 /* Calculate the number of elements in the PARALLEL. We need one element
9410 for the stack adjustment, one for each argument register save, and one
9411 for each additional register move. */
9413 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
9414 if (BITSET_P (*mask_ptr, mips16e_save_restore_regs[i]))
9417 /* Create the final PARALLEL. */
9418 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (n));
9421 /* Add the stack pointer adjustment. */
9422 set = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
9423 plus_constant (Pmode, stack_pointer_rtx,
9424 restore_p ? size : -size));
9425 RTX_FRAME_RELATED_P (set) = 1;
9426 XVECEXP (pattern, 0, n++) = set;
9428 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
9429 top_offset = restore_p ? size : 0;
9431 /* Save the arguments. */
9432 for (i = 0; i < nargs; i++)
9434 offset = top_offset + i * UNITS_PER_WORD;
9435 set = mips16e_save_restore_reg (restore_p, true, offset,
9437 XVECEXP (pattern, 0, n++) = set;
9440 /* Then fill in the other register moves. */
9441 offset = top_offset;
9442 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
9444 regno = mips16e_save_restore_regs[i];
9445 if (BITSET_P (*mask_ptr, regno))
9447 offset -= UNITS_PER_WORD;
9448 set = mips16e_save_restore_reg (restore_p, false, offset, regno);
9449 XVECEXP (pattern, 0, n++) = set;
9450 *mask_ptr &= ~(1 << regno);
9454 /* Tell the caller what offset it should use for the remaining registers. */
9455 *offset_ptr = size + (offset - top_offset);
9457 gcc_assert (n == XVECLEN (pattern, 0));
9462 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
9463 pointer. Return true if PATTERN matches the kind of instruction
9464 generated by mips16e_build_save_restore. If INFO is nonnull,
9465 initialize it when returning true. */
9468 mips16e_save_restore_pattern_p (rtx pattern, HOST_WIDE_INT adjust,
9469 struct mips16e_save_restore_info *info)
9471 unsigned int i, nargs, mask, extra;
9472 HOST_WIDE_INT top_offset, save_offset, offset;
9473 rtx set, reg, mem, base;
9476 if (!GENERATE_MIPS16E_SAVE_RESTORE)
9479 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
9480 top_offset = adjust > 0 ? adjust : 0;
9482 /* Interpret all other members of the PARALLEL. */
9483 save_offset = top_offset - UNITS_PER_WORD;
9487 for (n = 1; n < XVECLEN (pattern, 0); n++)
9489 /* Check that we have a SET. */
9490 set = XVECEXP (pattern, 0, n);
9491 if (GET_CODE (set) != SET)
9494 /* Check that the SET is a load (if restoring) or a store
9496 mem = adjust > 0 ? SET_SRC (set) : SET_DEST (set);
9500 /* Check that the address is the sum of the stack pointer and a
9501 possibly-zero constant offset. */
9502 mips_split_plus (XEXP (mem, 0), &base, &offset);
9503 if (base != stack_pointer_rtx)
9506 /* Check that SET's other operand is a register. */
9507 reg = adjust > 0 ? SET_DEST (set) : SET_SRC (set);
9511 /* Check for argument saves. */
9512 if (offset == top_offset + nargs * UNITS_PER_WORD
9513 && REGNO (reg) == GP_ARG_FIRST + nargs)
9515 else if (offset == save_offset)
9517 while (mips16e_save_restore_regs[i++] != REGNO (reg))
9518 if (i == ARRAY_SIZE (mips16e_save_restore_regs))
9521 mask |= 1 << REGNO (reg);
9522 save_offset -= UNITS_PER_WORD;
9528 /* Check that the restrictions on register ranges are met. */
9530 mips16e_mask_registers (&mask, mips16e_s2_s8_regs,
9531 ARRAY_SIZE (mips16e_s2_s8_regs), &extra);
9532 mips16e_mask_registers (&mask, mips16e_a0_a3_regs,
9533 ARRAY_SIZE (mips16e_a0_a3_regs), &extra);
9537 /* Make sure that the topmost argument register is not saved twice.
9538 The checks above ensure that the same is then true for the other
9539 argument registers. */
9540 if (nargs > 0 && BITSET_P (mask, GP_ARG_FIRST + nargs - 1))
9543 /* Pass back information, if requested. */
9546 info->nargs = nargs;
9548 info->size = (adjust > 0 ? adjust : -adjust);
9554 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
9555 for the register range [MIN_REG, MAX_REG]. Return a pointer to
9556 the null terminator. */
9559 mips16e_add_register_range (char *s, unsigned int min_reg,
9560 unsigned int max_reg)
9562 if (min_reg != max_reg)
9563 s += sprintf (s, ",%s-%s", reg_names[min_reg], reg_names[max_reg]);
9565 s += sprintf (s, ",%s", reg_names[min_reg]);
9569 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
9570 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
9573 mips16e_output_save_restore (rtx pattern, HOST_WIDE_INT adjust)
9575 static char buffer[300];
9577 struct mips16e_save_restore_info info;
9578 unsigned int i, end;
9581 /* Parse the pattern. */
9582 if (!mips16e_save_restore_pattern_p (pattern, adjust, &info))
9585 /* Add the mnemonic. */
9586 s = strcpy (buffer, adjust > 0 ? "restore\t" : "save\t");
9589 /* Save the arguments. */
9591 s += sprintf (s, "%s-%s,", reg_names[GP_ARG_FIRST],
9592 reg_names[GP_ARG_FIRST + info.nargs - 1]);
9593 else if (info.nargs == 1)
9594 s += sprintf (s, "%s,", reg_names[GP_ARG_FIRST]);
9596 /* Emit the amount of stack space to allocate or deallocate. */
9597 s += sprintf (s, "%d", (int) info.size);
9599 /* Save or restore $16. */
9600 if (BITSET_P (info.mask, 16))
9601 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 16]);
9603 /* Save or restore $17. */
9604 if (BITSET_P (info.mask, 17))
9605 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 17]);
9607 /* Save or restore registers in the range $s2...$s8, which
9608 mips16e_s2_s8_regs lists in decreasing order. Note that this
9609 is a software register range; the hardware registers are not
9610 numbered consecutively. */
9611 end = ARRAY_SIZE (mips16e_s2_s8_regs);
9612 i = mips16e_find_first_register (info.mask, mips16e_s2_s8_regs, end);
9614 s = mips16e_add_register_range (s, mips16e_s2_s8_regs[end - 1],
9615 mips16e_s2_s8_regs[i]);
9617 /* Save or restore registers in the range $a0...$a3. */
9618 end = ARRAY_SIZE (mips16e_a0_a3_regs);
9619 i = mips16e_find_first_register (info.mask, mips16e_a0_a3_regs, end);
9621 s = mips16e_add_register_range (s, mips16e_a0_a3_regs[i],
9622 mips16e_a0_a3_regs[end - 1]);
9624 /* Save or restore $31. */
9625 if (BITSET_P (info.mask, RETURN_ADDR_REGNUM))
9626 s += sprintf (s, ",%s", reg_names[RETURN_ADDR_REGNUM]);
9631 /* Return true if the current function returns its value in a floating-point
9632 register in MIPS16 mode. */
9635 mips16_cfun_returns_in_fpr_p (void)
9637 tree return_type = DECL_RESULT (current_function_decl);
9638 return (TARGET_MIPS16
9639 && TARGET_HARD_FLOAT_ABI
9640 && !aggregate_value_p (return_type, current_function_decl)
9641 && mips_return_mode_in_fpr_p (DECL_MODE (return_type)));
9644 /* Return true if predicate PRED is true for at least one instruction.
9645 Cache the result in *CACHE, and assume that the result is true
9646 if *CACHE is already true. */
9649 mips_find_gp_ref (bool *cache, bool (*pred) (rtx_insn *))
9655 push_topmost_sequence ();
9656 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9657 if (USEFUL_INSN_P (insn) && pred (insn))
9662 pop_topmost_sequence ();
9667 /* Return true if INSN refers to the global pointer in an "inflexible" way.
9668 See mips_cfun_has_inflexible_gp_ref_p for details. */
9671 mips_insn_has_inflexible_gp_ref_p (rtx_insn *insn)
9673 /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE
9674 indicate that the target could be a traditional MIPS
9675 lazily-binding stub. */
9676 return find_reg_fusage (insn, USE, pic_offset_table_rtx);
9679 /* Return true if the current function refers to the global pointer
9680 in a way that forces $28 to be valid. This means that we can't
9681 change the choice of global pointer, even for NewABI code.
9683 One example of this (and one which needs several checks) is that
9684 $28 must be valid when calling traditional MIPS lazy-binding stubs.
9685 (This restriction does not apply to PLTs.) */
9688 mips_cfun_has_inflexible_gp_ref_p (void)
9690 /* If the function has a nonlocal goto, $28 must hold the correct
9691 global pointer for the target function. That is, the target
9692 of the goto implicitly uses $28. */
9693 if (crtl->has_nonlocal_goto)
9696 if (TARGET_ABICALLS_PIC2)
9698 /* Symbolic accesses implicitly use the global pointer unless
9699 -mexplicit-relocs is in effect. JAL macros to symbolic addresses
9700 might go to traditional MIPS lazy-binding stubs. */
9701 if (!TARGET_EXPLICIT_RELOCS)
9704 /* FUNCTION_PROFILER includes a JAL to _mcount, which again
9705 can be lazily-bound. */
9709 /* MIPS16 functions that return in FPRs need to call an
9710 external libgcc routine. This call is only made explict
9711 during mips_expand_epilogue, and it too might be lazily bound. */
9712 if (mips16_cfun_returns_in_fpr_p ())
9716 return mips_find_gp_ref (&cfun->machine->has_inflexible_gp_insn_p,
9717 mips_insn_has_inflexible_gp_ref_p);
9720 /* Return true if INSN refers to the global pointer in a "flexible" way.
9721 See mips_cfun_has_flexible_gp_ref_p for details. */
9724 mips_insn_has_flexible_gp_ref_p (rtx_insn *insn)
9726 return (get_attr_got (insn) != GOT_UNSET
9727 || mips_small_data_pattern_p (PATTERN (insn))
9728 || reg_overlap_mentioned_p (pic_offset_table_rtx, PATTERN (insn)));
9731 /* Return true if the current function references the global pointer,
9732 but if those references do not inherently require the global pointer
9733 to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */
9736 mips_cfun_has_flexible_gp_ref_p (void)
9738 /* Reload can sometimes introduce constant pool references
9739 into a function that otherwise didn't need them. For example,
9740 suppose we have an instruction like:
9742 (set (reg:DF R1) (float:DF (reg:SI R2)))
9744 If R2 turns out to be a constant such as 1, the instruction may
9745 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
9746 the option of using this constant if R2 doesn't get allocated
9749 In cases like these, reload will have added the constant to the
9750 pool but no instruction will yet refer to it. */
9751 if (TARGET_ABICALLS_PIC2 && !reload_completed && crtl->uses_const_pool)
9754 return mips_find_gp_ref (&cfun->machine->has_flexible_gp_insn_p,
9755 mips_insn_has_flexible_gp_ref_p);
9758 /* Return the register that should be used as the global pointer
9759 within this function. Return INVALID_REGNUM if the function
9760 doesn't need a global pointer. */
9763 mips_global_pointer (void)
9767 /* $gp is always available unless we're using a GOT. */
9768 if (!TARGET_USE_GOT)
9769 return GLOBAL_POINTER_REGNUM;
9771 /* If there are inflexible references to $gp, we must use the
9772 standard register. */
9773 if (mips_cfun_has_inflexible_gp_ref_p ())
9774 return GLOBAL_POINTER_REGNUM;
9776 /* If there are no current references to $gp, then the only uses
9777 we can introduce later are those involved in long branches. */
9778 if (TARGET_ABSOLUTE_JUMPS && !mips_cfun_has_flexible_gp_ref_p ())
9779 return INVALID_REGNUM;
9781 /* If the global pointer is call-saved, try to use a call-clobbered
9783 if (TARGET_CALL_SAVED_GP && crtl->is_leaf)
9784 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
9785 if (!df_regs_ever_live_p (regno)
9786 && call_really_used_regs[regno]
9787 && !fixed_regs[regno]
9788 && regno != PIC_FUNCTION_ADDR_REGNUM)
9791 return GLOBAL_POINTER_REGNUM;
9794 /* Return true if the current function's prologue must load the global
9795 pointer value into pic_offset_table_rtx and store the same value in
9796 the function's cprestore slot (if any).
9798 One problem we have to deal with is that, when emitting GOT-based
9799 position independent code, long-branch sequences will need to load
9800 the address of the branch target from the GOT. We don't know until
9801 the very end of compilation whether (and where) the function needs
9802 long branches, so we must ensure that _any_ branch can access the
9803 global pointer in some form. However, we do not want to pessimize
9804 the usual case in which all branches are short.
9806 We handle this as follows:
9808 (1) During reload, we set cfun->machine->global_pointer to
9809 INVALID_REGNUM if we _know_ that the current function
9810 doesn't need a global pointer. This is only valid if
9811 long branches don't need the GOT.
9813 Otherwise, we assume that we might need a global pointer
9814 and pick an appropriate register.
9816 (2) If cfun->machine->global_pointer != INVALID_REGNUM,
9817 we ensure that the global pointer is available at every
9818 block boundary bar entry and exit. We do this in one of two ways:
9820 - If the function has a cprestore slot, we ensure that this
9821 slot is valid at every branch. However, as explained in
9822 point (6) below, there is no guarantee that pic_offset_table_rtx
9823 itself is valid if new uses of the global pointer are introduced
9824 after the first post-epilogue split.
9826 We guarantee that the cprestore slot is valid by loading it
9827 into a fake register, CPRESTORE_SLOT_REGNUM. We then make
9828 this register live at every block boundary bar function entry
9829 and exit. It is then invalid to move the load (and thus the
9830 preceding store) across a block boundary.
9832 - If the function has no cprestore slot, we guarantee that
9833 pic_offset_table_rtx itself is valid at every branch.
9835 See mips_eh_uses for the handling of the register liveness.
9837 (3) During prologue and epilogue generation, we emit "ghost"
9838 placeholder instructions to manipulate the global pointer.
9840 (4) During prologue generation, we set cfun->machine->must_initialize_gp_p
9841 and cfun->machine->must_restore_gp_when_clobbered_p if we already know
9842 that the function needs a global pointer. (There is no need to set
9843 them earlier than this, and doing it as late as possible leads to
9844 fewer false positives.)
9846 (5) If cfun->machine->must_initialize_gp_p is true during a
9847 split_insns pass, we split the ghost instructions into real
9848 instructions. These split instructions can then be optimized in
9849 the usual way. Otherwise, we keep the ghost instructions intact,
9850 and optimize for the case where they aren't needed. We still
9851 have the option of splitting them later, if we need to introduce
9852 new uses of the global pointer.
9854 For example, the scheduler ignores a ghost instruction that
9855 stores $28 to the stack, but it handles the split form of
9856 the ghost instruction as an ordinary store.
9858 (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p
9859 is true during the first post-epilogue split_insns pass, we split
9860 calls and restore_gp patterns into instructions that explicitly
9861 load pic_offset_table_rtx from the cprestore slot. Otherwise,
9862 we split these patterns into instructions that _don't_ load from
9865 If cfun->machine->must_restore_gp_when_clobbered_p is true at the
9866 time of the split, then any instructions that exist at that time
9867 can make free use of pic_offset_table_rtx. However, if we want
9868 to introduce new uses of the global pointer after the split,
9869 we must explicitly load the value from the cprestore slot, since
9870 pic_offset_table_rtx itself might not be valid at a given point
9873 The idea is that we want to be able to delete redundant
9874 loads from the cprestore slot in the usual case where no
9875 long branches are needed.
9877 (7) If cfun->machine->must_initialize_gp_p is still false at the end
9878 of md_reorg, we decide whether the global pointer is needed for
9879 long branches. If so, we set cfun->machine->must_initialize_gp_p
9880 to true and split the ghost instructions into real instructions
9883 Note that the ghost instructions must have a zero length for three reasons:
9885 - Giving the length of the underlying $gp sequence might cause
9886 us to use long branches in cases where they aren't really needed.
9888 - They would perturb things like alignment calculations.
9890 - More importantly, the hazard detection in md_reorg relies on
9891 empty instructions having a zero length.
9893 If we find a long branch and split the ghost instructions at the
9894 end of md_reorg, the split could introduce more long branches.
9895 That isn't a problem though, because we still do the split before
9896 the final shorten_branches pass.
9898 This is extremely ugly, but it seems like the best compromise between
9899 correctness and efficiency. */
9902 mips_must_initialize_gp_p (void)
9904 return cfun->machine->must_initialize_gp_p;
9907 /* Return true if REGNO is a register that is ordinarily call-clobbered
9908 but must nevertheless be preserved by an interrupt handler. */
9911 mips_interrupt_extra_call_saved_reg_p (unsigned int regno)
9913 if (MD_REG_P (regno))
9916 if (TARGET_DSP && DSP_ACC_REG_P (regno))
9919 if (GP_REG_P (regno) && !cfun->machine->use_shadow_register_set_p)
9921 /* $0 is hard-wired. */
9922 if (regno == GP_REG_FIRST)
9925 /* The interrupt handler can treat kernel registers as
9926 scratch registers. */
9927 if (KERNEL_REG_P (regno))
9930 /* The function will return the stack pointer to its original value
9932 if (regno == STACK_POINTER_REGNUM)
9935 /* Otherwise, return true for registers that aren't ordinarily
9937 return call_really_used_regs[regno];
9943 /* Return true if the current function should treat register REGNO
9947 mips_cfun_call_saved_reg_p (unsigned int regno)
9949 /* If the user makes an ordinarily-call-saved register global,
9950 that register is no longer call-saved. */
9951 if (global_regs[regno])
9954 /* Interrupt handlers need to save extra registers. */
9955 if (cfun->machine->interrupt_handler_p
9956 && mips_interrupt_extra_call_saved_reg_p (regno))
9959 /* call_insns preserve $28 unless they explicitly say otherwise,
9960 so call_really_used_regs[] treats $28 as call-saved. However,
9961 we want the ABI property rather than the default call_insn
9963 return (regno == GLOBAL_POINTER_REGNUM
9964 ? TARGET_CALL_SAVED_GP
9965 : !call_really_used_regs[regno]);
9968 /* Return true if the function body might clobber register REGNO.
9969 We know that REGNO is call-saved. */
9972 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno)
9974 /* Some functions should be treated as clobbering all call-saved
9976 if (crtl->saves_all_registers)
9979 /* DF handles cases where a register is explicitly referenced in
9980 the rtl. Incoming values are passed in call-clobbered registers,
9981 so we can assume that any live call-saved register is set within
9983 if (df_regs_ever_live_p (regno))
9986 /* Check for registers that are clobbered by FUNCTION_PROFILER.
9987 These clobbers are not explicit in the rtl. */
9988 if (crtl->profile && MIPS_SAVE_REG_FOR_PROFILING_P (regno))
9991 /* If we're using a call-saved global pointer, the function's
9992 prologue will need to set it up. */
9993 if (cfun->machine->global_pointer == regno)
9996 /* The function's prologue will need to set the frame pointer if
9997 frame_pointer_needed. */
9998 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
10001 /* If a MIPS16 function returns a value in FPRs, its epilogue
10002 will need to call an external libgcc routine. This yet-to-be
10003 generated call_insn will clobber $31. */
10004 if (regno == RETURN_ADDR_REGNUM && mips16_cfun_returns_in_fpr_p ())
10007 /* If REGNO is ordinarily call-clobbered, we must assume that any
10008 called function could modify it. */
10009 if (cfun->machine->interrupt_handler_p
10011 && mips_interrupt_extra_call_saved_reg_p (regno))
10017 /* Return true if the current function must save register REGNO. */
10020 mips_save_reg_p (unsigned int regno)
10022 if (mips_cfun_call_saved_reg_p (regno))
10024 if (mips_cfun_might_clobber_call_saved_reg_p (regno))
10027 /* Save both registers in an FPR pair if either one is used. This is
10028 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
10029 register to be used without the even register. */
10030 if (FP_REG_P (regno)
10031 && MAX_FPRS_PER_FMT == 2
10032 && mips_cfun_might_clobber_call_saved_reg_p (regno + 1))
10036 /* We need to save the incoming return address if __builtin_eh_return
10037 is being used to set a different return address. */
10038 if (regno == RETURN_ADDR_REGNUM && crtl->calls_eh_return)
10044 /* Populate the current function's mips_frame_info structure.
10046 MIPS stack frames look like:
10048 +-------------------------------+
10050 | incoming stack arguments |
10052 +-------------------------------+
10054 | caller-allocated save area |
10055 A | for register arguments |
10057 +-------------------------------+ <-- incoming stack pointer
10059 | callee-allocated save area |
10060 B | for arguments that are |
10061 | split between registers and |
10064 +-------------------------------+ <-- arg_pointer_rtx
10066 C | callee-allocated save area |
10067 | for register varargs |
10069 +-------------------------------+ <-- frame_pointer_rtx
10070 | | + cop0_sp_offset
10071 | COP0 reg save area | + UNITS_PER_WORD
10073 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
10074 | | + UNITS_PER_WORD
10075 | accumulator save area |
10077 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
10078 | | + UNITS_PER_HWFPVALUE
10081 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset
10082 | | + UNITS_PER_WORD
10085 +-------------------------------+ <-- frame_pointer_rtx with
10086 | | \ -fstack-protector
10087 | local variables | | var_size
10089 +-------------------------------+
10091 | $gp save area | | cprestore_size
10093 P +-------------------------------+ <-- hard_frame_pointer_rtx for
10095 | outgoing stack arguments | |
10097 +-------------------------------+ | args_size
10099 | caller-allocated save area | |
10100 | for register arguments | |
10102 +-------------------------------+ <-- stack_pointer_rtx
10103 frame_pointer_rtx without
10105 hard_frame_pointer_rtx for
10108 At least two of A, B and C will be empty.
10110 Dynamic stack allocations such as alloca insert data at point P.
10111 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
10112 hard_frame_pointer_rtx unchanged. */
10115 mips_compute_frame_info (void)
10117 struct mips_frame_info *frame;
10118 HOST_WIDE_INT offset, size;
10119 unsigned int regno, i;
10121 /* Set this function's interrupt properties. */
10122 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
10124 if (mips_isa_rev < 2)
10125 error ("the %<interrupt%> attribute requires a MIPS32r2 processor or greater");
10126 else if (TARGET_HARD_FLOAT)
10127 error ("the %<interrupt%> attribute requires %<-msoft-float%>");
10128 else if (TARGET_MIPS16)
10129 error ("interrupt handlers cannot be MIPS16 functions");
10132 cfun->machine->interrupt_handler_p = true;
10133 cfun->machine->use_shadow_register_set_p =
10134 mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl));
10135 cfun->machine->keep_interrupts_masked_p =
10136 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl));
10137 cfun->machine->use_debug_exception_return_p =
10138 mips_use_debug_exception_return_p (TREE_TYPE
10139 (current_function_decl));
10143 frame = &cfun->machine->frame;
10144 memset (frame, 0, sizeof (*frame));
10145 size = get_frame_size ();
10147 cfun->machine->global_pointer = mips_global_pointer ();
10149 /* The first two blocks contain the outgoing argument area and the $gp save
10150 slot. This area isn't needed in leaf functions, but if the
10151 target-independent frame size is nonzero, we have already committed to
10152 allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */
10153 if ((size == 0 || FRAME_GROWS_DOWNWARD) && crtl->is_leaf)
10155 /* The MIPS 3.0 linker does not like functions that dynamically
10156 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
10157 looks like we are trying to create a second frame pointer to the
10158 function, so allocate some stack space to make it happy. */
10159 if (cfun->calls_alloca)
10160 frame->args_size = REG_PARM_STACK_SPACE (cfun->decl);
10162 frame->args_size = 0;
10163 frame->cprestore_size = 0;
10167 frame->args_size = crtl->outgoing_args_size;
10168 frame->cprestore_size = MIPS_GP_SAVE_AREA_SIZE;
10170 offset = frame->args_size + frame->cprestore_size;
10172 /* Move above the local variables. */
10173 frame->var_size = MIPS_STACK_ALIGN (size);
10174 offset += frame->var_size;
10176 /* Find out which GPRs we need to save. */
10177 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
10178 if (mips_save_reg_p (regno))
10181 frame->mask |= 1 << (regno - GP_REG_FIRST);
10184 /* If this function calls eh_return, we must also save and restore the
10185 EH data registers. */
10186 if (crtl->calls_eh_return)
10187 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; i++)
10190 frame->mask |= 1 << (EH_RETURN_DATA_REGNO (i) - GP_REG_FIRST);
10193 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
10194 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
10195 save all later registers too. */
10196 if (GENERATE_MIPS16E_SAVE_RESTORE)
10198 mips16e_mask_registers (&frame->mask, mips16e_s2_s8_regs,
10199 ARRAY_SIZE (mips16e_s2_s8_regs), &frame->num_gp);
10200 mips16e_mask_registers (&frame->mask, mips16e_a0_a3_regs,
10201 ARRAY_SIZE (mips16e_a0_a3_regs), &frame->num_gp);
10204 /* Move above the GPR save area. */
10205 if (frame->num_gp > 0)
10207 offset += MIPS_STACK_ALIGN (frame->num_gp * UNITS_PER_WORD);
10208 frame->gp_sp_offset = offset - UNITS_PER_WORD;
10211 /* Find out which FPRs we need to save. This loop must iterate over
10212 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
10213 if (TARGET_HARD_FLOAT)
10214 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += MAX_FPRS_PER_FMT)
10215 if (mips_save_reg_p (regno))
10217 frame->num_fp += MAX_FPRS_PER_FMT;
10218 frame->fmask |= ~(~0 << MAX_FPRS_PER_FMT) << (regno - FP_REG_FIRST);
10221 /* Move above the FPR save area. */
10222 if (frame->num_fp > 0)
10224 offset += MIPS_STACK_ALIGN (frame->num_fp * UNITS_PER_FPREG);
10225 frame->fp_sp_offset = offset - UNITS_PER_HWFPVALUE;
10228 /* Add in space for the interrupt context information. */
10229 if (cfun->machine->interrupt_handler_p)
10232 if (mips_save_reg_p (LO_REGNUM) || mips_save_reg_p (HI_REGNUM))
10235 frame->acc_mask |= (1 << 0);
10238 /* Check accumulators 1, 2, 3. */
10239 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
10240 if (mips_save_reg_p (i) || mips_save_reg_p (i + 1))
10243 frame->acc_mask |= 1 << (((i - DSP_ACC_REG_FIRST) / 2) + 1);
10246 /* All interrupt context functions need space to preserve STATUS. */
10247 frame->num_cop0_regs++;
10249 /* If we don't keep interrupts masked, we need to save EPC. */
10250 if (!cfun->machine->keep_interrupts_masked_p)
10251 frame->num_cop0_regs++;
10254 /* Move above the accumulator save area. */
10255 if (frame->num_acc > 0)
10257 /* Each accumulator needs 2 words. */
10258 offset += frame->num_acc * 2 * UNITS_PER_WORD;
10259 frame->acc_sp_offset = offset - UNITS_PER_WORD;
10262 /* Move above the COP0 register save area. */
10263 if (frame->num_cop0_regs > 0)
10265 offset += frame->num_cop0_regs * UNITS_PER_WORD;
10266 frame->cop0_sp_offset = offset - UNITS_PER_WORD;
10269 /* Move above the callee-allocated varargs save area. */
10270 offset += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
10271 frame->arg_pointer_offset = offset;
10273 /* Move above the callee-allocated area for pretend stack arguments. */
10274 offset += crtl->args.pretend_args_size;
10275 frame->total_size = offset;
10277 /* Work out the offsets of the save areas from the top of the frame. */
10278 if (frame->gp_sp_offset > 0)
10279 frame->gp_save_offset = frame->gp_sp_offset - offset;
10280 if (frame->fp_sp_offset > 0)
10281 frame->fp_save_offset = frame->fp_sp_offset - offset;
10282 if (frame->acc_sp_offset > 0)
10283 frame->acc_save_offset = frame->acc_sp_offset - offset;
10284 if (frame->num_cop0_regs > 0)
10285 frame->cop0_save_offset = frame->cop0_sp_offset - offset;
10287 /* MIPS16 code offsets the frame pointer by the size of the outgoing
10288 arguments. This tends to increase the chances of using unextended
10289 instructions for local variables and incoming arguments. */
10291 frame->hard_frame_pointer_offset = frame->args_size;
10294 /* Return the style of GP load sequence that is being used for the
10295 current function. */
10297 enum mips_loadgp_style
10298 mips_current_loadgp_style (void)
10300 if (!TARGET_USE_GOT || cfun->machine->global_pointer == INVALID_REGNUM)
10301 return LOADGP_NONE;
10303 if (TARGET_RTP_PIC)
10306 if (TARGET_ABSOLUTE_ABICALLS)
10307 return LOADGP_ABSOLUTE;
10309 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
10312 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
10315 mips_frame_pointer_required (void)
10317 /* If the function contains dynamic stack allocations, we need to
10318 use the frame pointer to access the static parts of the frame. */
10319 if (cfun->calls_alloca)
10322 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
10323 reload may be unable to compute the address of a local variable,
10324 since there is no way to add a large constant to the stack pointer
10325 without using a second temporary register. */
10328 mips_compute_frame_info ();
10329 if (!SMALL_OPERAND (cfun->machine->frame.total_size))
10336 /* Make sure that we're not trying to eliminate to the wrong hard frame
10340 mips_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
10342 return (to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM);
10345 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
10346 or argument pointer. TO is either the stack pointer or hard frame
10350 mips_initial_elimination_offset (int from, int to)
10352 HOST_WIDE_INT offset;
10354 mips_compute_frame_info ();
10356 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */
10359 case FRAME_POINTER_REGNUM:
10360 if (FRAME_GROWS_DOWNWARD)
10361 offset = (cfun->machine->frame.args_size
10362 + cfun->machine->frame.cprestore_size
10363 + cfun->machine->frame.var_size);
10368 case ARG_POINTER_REGNUM:
10369 offset = cfun->machine->frame.arg_pointer_offset;
10373 gcc_unreachable ();
10376 if (to == HARD_FRAME_POINTER_REGNUM)
10377 offset -= cfun->machine->frame.hard_frame_pointer_offset;
10382 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
10385 mips_extra_live_on_entry (bitmap regs)
10387 if (TARGET_USE_GOT)
10389 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
10390 the global pointer. */
10391 if (!TARGET_ABSOLUTE_ABICALLS)
10392 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
10394 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
10395 the global pointer. */
10397 bitmap_set_bit (regs, MIPS16_PIC_TEMP_REGNUM);
10399 /* See the comment above load_call<mode> for details. */
10400 bitmap_set_bit (regs, GOT_VERSION_REGNUM);
10404 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
10408 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
10413 return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);
10416 /* Emit code to change the current function's return address to
10417 ADDRESS. SCRATCH is available as a scratch register, if needed.
10418 ADDRESS and SCRATCH are both word-mode GPRs. */
10421 mips_set_return_address (rtx address, rtx scratch)
10425 gcc_assert (BITSET_P (cfun->machine->frame.mask, RETURN_ADDR_REGNUM));
10426 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
10427 cfun->machine->frame.gp_sp_offset);
10428 mips_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address);
10431 /* Return true if the current function has a cprestore slot. */
10434 mips_cfun_has_cprestore_slot_p (void)
10436 return (cfun->machine->global_pointer != INVALID_REGNUM
10437 && cfun->machine->frame.cprestore_size > 0);
10440 /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the
10441 cprestore slot. LOAD_P is true if the caller wants to load from
10442 the cprestore slot; it is false if the caller wants to store to
10446 mips_get_cprestore_base_and_offset (rtx *base, HOST_WIDE_INT *offset,
10449 const struct mips_frame_info *frame;
10451 frame = &cfun->machine->frame;
10452 /* .cprestore always uses the stack pointer instead of the frame pointer.
10453 We have a free choice for direct stores for non-MIPS16 functions,
10454 and for MIPS16 functions whose cprestore slot is in range of the
10455 stack pointer. Using the stack pointer would sometimes give more
10456 (early) scheduling freedom, but using the frame pointer would
10457 sometimes give more (late) scheduling freedom. It's hard to
10458 predict which applies to a given function, so let's keep things
10461 Loads must always use the frame pointer in functions that call
10462 alloca, and there's little benefit to using the stack pointer
10464 if (frame_pointer_needed && !(TARGET_CPRESTORE_DIRECTIVE && !load_p))
10466 *base = hard_frame_pointer_rtx;
10467 *offset = frame->args_size - frame->hard_frame_pointer_offset;
10471 *base = stack_pointer_rtx;
10472 *offset = frame->args_size;
10476 /* Return true if X is the load or store address of the cprestore slot;
10477 LOAD_P says which. */
10480 mips_cprestore_address_p (rtx x, bool load_p)
10482 rtx given_base, required_base;
10483 HOST_WIDE_INT given_offset, required_offset;
10485 mips_split_plus (x, &given_base, &given_offset);
10486 mips_get_cprestore_base_and_offset (&required_base, &required_offset, load_p);
10487 return given_base == required_base && given_offset == required_offset;
10490 /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are
10491 going to load from it, false if we are going to store to it.
10492 Use TEMP as a temporary register if need be. */
10495 mips_cprestore_slot (rtx temp, bool load_p)
10498 HOST_WIDE_INT offset;
10500 mips_get_cprestore_base_and_offset (&base, &offset, load_p);
10501 return gen_frame_mem (Pmode, mips_add_offset (temp, base, offset));
10504 /* Emit instructions to save global pointer value GP into cprestore
10505 slot MEM. OFFSET is the offset that MEM applies to the base register.
10507 MEM may not be a legitimate address. If it isn't, TEMP is a
10508 temporary register that can be used, otherwise it is a SCRATCH. */
10511 mips_save_gp_to_cprestore_slot (rtx mem, rtx offset, rtx gp, rtx temp)
10513 if (TARGET_CPRESTORE_DIRECTIVE)
10515 gcc_assert (gp == pic_offset_table_rtx);
10516 emit_insn (PMODE_INSN (gen_cprestore, (mem, offset)));
10519 mips_emit_move (mips_cprestore_slot (temp, false), gp);
10522 /* Restore $gp from its save slot, using TEMP as a temporary base register
10523 if need be. This function is for o32 and o64 abicalls only.
10525 See mips_must_initialize_gp_p for details about how we manage the
10529 mips_restore_gp_from_cprestore_slot (rtx temp)
10531 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI && epilogue_completed);
10533 if (!cfun->machine->must_restore_gp_when_clobbered_p)
10535 emit_note (NOTE_INSN_DELETED);
10541 mips_emit_move (temp, mips_cprestore_slot (temp, true));
10542 mips_emit_move (pic_offset_table_rtx, temp);
10545 mips_emit_move (pic_offset_table_rtx, mips_cprestore_slot (temp, true));
10546 if (!TARGET_EXPLICIT_RELOCS)
10547 emit_insn (gen_blockage ());
10550 /* A function to save or store a register. The first argument is the
10551 register and the second is the stack slot. */
10552 typedef void (*mips_save_restore_fn) (rtx, rtx);
10554 /* Use FN to save or restore register REGNO. MODE is the register's
10555 mode and OFFSET is the offset of its save slot from the current
10559 mips_save_restore_reg (machine_mode mode, int regno,
10560 HOST_WIDE_INT offset, mips_save_restore_fn fn)
10564 mem = gen_frame_mem (mode, plus_constant (Pmode, stack_pointer_rtx,
10566 fn (gen_rtx_REG (mode, regno), mem);
10569 /* Call FN for each accumlator that is saved by the current function.
10570 SP_OFFSET is the offset of the current stack pointer from the start
10574 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
10576 HOST_WIDE_INT offset;
10579 offset = cfun->machine->frame.acc_sp_offset - sp_offset;
10580 if (BITSET_P (cfun->machine->frame.acc_mask, 0))
10582 mips_save_restore_reg (word_mode, LO_REGNUM, offset, fn);
10583 offset -= UNITS_PER_WORD;
10584 mips_save_restore_reg (word_mode, HI_REGNUM, offset, fn);
10585 offset -= UNITS_PER_WORD;
10588 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
10589 if (BITSET_P (cfun->machine->frame.acc_mask,
10590 ((regno - DSP_ACC_REG_FIRST) / 2) + 1))
10592 mips_save_restore_reg (word_mode, regno, offset, fn);
10593 offset -= UNITS_PER_WORD;
10597 /* Save register REG to MEM. Make the instruction frame-related. */
10600 mips_save_reg (rtx reg, rtx mem)
10602 if (GET_MODE (reg) == DFmode
10603 && (!TARGET_FLOAT64
10604 || mips_abi == ABI_32))
10608 mips_emit_move_or_split (mem, reg, SPLIT_IF_NECESSARY);
10610 x1 = mips_frame_set (mips_subword (mem, false),
10611 mips_subword (reg, false));
10612 x2 = mips_frame_set (mips_subword (mem, true),
10613 mips_subword (reg, true));
10614 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
10617 mips_emit_save_slot_move (mem, reg, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
10620 /* Capture the register combinations that are allowed in a SWM or LWM
10621 instruction. The entries are ordered by number of registers set in
10622 the mask. We also ignore the single register encodings because a
10623 normal SW/LW is preferred. */
10625 static const unsigned int umips_swm_mask[17] = {
10626 0xc0ff0000, 0x80ff0000, 0x40ff0000, 0x807f0000,
10627 0x00ff0000, 0x803f0000, 0x007f0000, 0x801f0000,
10628 0x003f0000, 0x800f0000, 0x001f0000, 0x80070000,
10629 0x000f0000, 0x80030000, 0x00070000, 0x80010000,
10633 static const unsigned int umips_swm_encoding[17] = {
10634 25, 24, 9, 23, 8, 22, 7, 21, 6, 20, 5, 19, 4, 18, 3, 17, 2
10637 /* Try to use a microMIPS LWM or SWM instruction to save or restore
10638 as many GPRs in *MASK as possible. *OFFSET is the offset from the
10639 stack pointer of the topmost save slot.
10641 Remove from *MASK all registers that were handled using LWM and SWM.
10642 Update *OFFSET so that it points to the first unused save slot. */
10645 umips_build_save_restore (mips_save_restore_fn fn,
10646 unsigned *mask, HOST_WIDE_INT *offset)
10650 rtx pattern, set, reg, mem;
10651 HOST_WIDE_INT this_offset;
10654 /* Try matching $16 to $31 (s0 to ra). */
10655 for (i = 0; i < ARRAY_SIZE (umips_swm_mask); i++)
10656 if ((*mask & 0xffff0000) == umips_swm_mask[i])
10659 if (i == ARRAY_SIZE (umips_swm_mask))
10662 /* Get the offset of the lowest save slot. */
10663 nregs = (umips_swm_encoding[i] & 0xf) + (umips_swm_encoding[i] >> 4);
10664 this_offset = *offset - UNITS_PER_WORD * (nregs - 1);
10666 /* LWM/SWM can only support offsets from -2048 to 2047. */
10667 if (!UMIPS_12BIT_OFFSET_P (this_offset))
10670 /* Create the final PARALLEL. */
10671 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nregs));
10672 this_base = stack_pointer_rtx;
10674 /* For registers $16-$23 and $30. */
10675 for (j = 0; j < (umips_swm_encoding[i] & 0xf); j++)
10677 HOST_WIDE_INT offset = this_offset + j * UNITS_PER_WORD;
10678 mem = gen_frame_mem (SImode, plus_constant (Pmode, this_base, offset));
10679 unsigned int regno = (j != 8) ? 16 + j : 30;
10680 *mask &= ~(1 << regno);
10681 reg = gen_rtx_REG (SImode, regno);
10682 if (fn == mips_save_reg)
10683 set = mips_frame_set (mem, reg);
10686 set = gen_rtx_SET (VOIDmode, reg, mem);
10687 mips_add_cfa_restore (reg);
10689 XVECEXP (pattern, 0, j) = set;
10692 /* For register $31. */
10693 if (umips_swm_encoding[i] >> 4)
10695 HOST_WIDE_INT offset = this_offset + j * UNITS_PER_WORD;
10696 *mask &= ~(1 << 31);
10697 mem = gen_frame_mem (SImode, plus_constant (Pmode, this_base, offset));
10698 reg = gen_rtx_REG (SImode, 31);
10699 if (fn == mips_save_reg)
10700 set = mips_frame_set (mem, reg);
10703 set = gen_rtx_SET (VOIDmode, reg, mem);
10704 mips_add_cfa_restore (reg);
10706 XVECEXP (pattern, 0, j) = set;
10709 pattern = emit_insn (pattern);
10710 if (fn == mips_save_reg)
10711 RTX_FRAME_RELATED_P (pattern) = 1;
10713 /* Adjust the last offset. */
10714 *offset -= UNITS_PER_WORD * nregs;
10719 /* Call FN for each register that is saved by the current function.
10720 SP_OFFSET is the offset of the current stack pointer from the start
10724 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset,
10725 mips_save_restore_fn fn)
10727 machine_mode fpr_mode;
10729 const struct mips_frame_info *frame = &cfun->machine->frame;
10730 HOST_WIDE_INT offset;
10733 /* Save registers starting from high to low. The debuggers prefer at least
10734 the return register be stored at func+4, and also it allows us not to
10735 need a nop in the epilogue if at least one register is reloaded in
10736 addition to return address. */
10737 offset = frame->gp_sp_offset - sp_offset;
10738 mask = frame->mask;
10740 if (TARGET_MICROMIPS)
10741 umips_build_save_restore (fn, &mask, &offset);
10743 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
10744 if (BITSET_P (mask, regno - GP_REG_FIRST))
10746 /* Record the ra offset for use by mips_function_profiler. */
10747 if (regno == RETURN_ADDR_REGNUM)
10748 cfun->machine->frame.ra_fp_offset = offset + sp_offset;
10749 mips_save_restore_reg (word_mode, regno, offset, fn);
10750 offset -= UNITS_PER_WORD;
10753 /* This loop must iterate over the same space as its companion in
10754 mips_compute_frame_info. */
10755 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
10756 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
10757 for (regno = FP_REG_LAST - MAX_FPRS_PER_FMT + 1;
10758 regno >= FP_REG_FIRST;
10759 regno -= MAX_FPRS_PER_FMT)
10760 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
10762 if (!TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT
10763 && (fixed_regs[regno] || fixed_regs[regno + 1]))
10765 if (fixed_regs[regno])
10766 mips_save_restore_reg (SFmode, regno + 1, offset, fn);
10768 mips_save_restore_reg (SFmode, regno, offset, fn);
10771 mips_save_restore_reg (fpr_mode, regno, offset, fn);
10772 offset -= GET_MODE_SIZE (fpr_mode);
10776 /* Return true if a move between register REGNO and its save slot (MEM)
10777 can be done in a single move. LOAD_P is true if we are loading
10778 from the slot, false if we are storing to it. */
10781 mips_direct_save_slot_move_p (unsigned int regno, rtx mem, bool load_p)
10783 /* There is a specific MIPS16 instruction for saving $31 to the stack. */
10784 if (TARGET_MIPS16 && !load_p && regno == RETURN_ADDR_REGNUM)
10787 return mips_secondary_reload_class (REGNO_REG_CLASS (regno),
10788 GET_MODE (mem), mem, load_p) == NO_REGS;
10791 /* Emit a move from SRC to DEST, given that one of them is a register
10792 save slot and that the other is a register. TEMP is a temporary
10793 GPR of the same mode that is available if need be. */
10796 mips_emit_save_slot_move (rtx dest, rtx src, rtx temp)
10798 unsigned int regno;
10803 regno = REGNO (src);
10808 regno = REGNO (dest);
10812 if (regno == cfun->machine->global_pointer && !mips_must_initialize_gp_p ())
10814 /* We don't yet know whether we'll need this instruction or not.
10815 Postpone the decision by emitting a ghost move. This move
10816 is specifically not frame-related; only the split version is. */
10818 emit_insn (gen_move_gpdi (dest, src));
10820 emit_insn (gen_move_gpsi (dest, src));
10824 if (regno == HI_REGNUM)
10828 mips_emit_move (temp, src);
10830 emit_insn (gen_mthisi_di (gen_rtx_REG (TImode, MD_REG_FIRST),
10831 temp, gen_rtx_REG (DImode, LO_REGNUM)));
10833 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode, MD_REG_FIRST),
10834 temp, gen_rtx_REG (SImode, LO_REGNUM)));
10839 emit_insn (gen_mfhidi_ti (temp,
10840 gen_rtx_REG (TImode, MD_REG_FIRST)));
10842 emit_insn (gen_mfhisi_di (temp,
10843 gen_rtx_REG (DImode, MD_REG_FIRST)));
10844 mips_emit_move (dest, temp);
10847 else if (mips_direct_save_slot_move_p (regno, mem, mem == src))
10848 mips_emit_move (dest, src);
10851 gcc_assert (!reg_overlap_mentioned_p (dest, temp));
10852 mips_emit_move (temp, src);
10853 mips_emit_move (dest, temp);
10856 mips_set_frame_expr (mips_frame_set (dest, src));
10859 /* If we're generating n32 or n64 abicalls, and the current function
10860 does not use $28 as its global pointer, emit a cplocal directive.
10861 Use pic_offset_table_rtx as the argument to the directive. */
10864 mips_output_cplocal (void)
10866 if (!TARGET_EXPLICIT_RELOCS
10867 && mips_must_initialize_gp_p ()
10868 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
10869 output_asm_insn (".cplocal %+", 0);
10872 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
10875 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
10877 const char *fnname;
10879 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
10880 floating-point arguments. */
10882 && TARGET_HARD_FLOAT_ABI
10883 && crtl->args.info.fp_code != 0)
10884 mips16_build_function_stub ();
10886 /* Get the function name the same way that toplev.c does before calling
10887 assemble_start_function. This is needed so that the name used here
10888 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10889 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
10890 mips_start_function_definition (fnname, TARGET_MIPS16);
10892 /* Output MIPS-specific frame information. */
10893 if (!flag_inhibit_size_directive)
10895 const struct mips_frame_info *frame;
10897 frame = &cfun->machine->frame;
10899 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
10901 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
10902 "# vars= " HOST_WIDE_INT_PRINT_DEC
10904 ", args= " HOST_WIDE_INT_PRINT_DEC
10905 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
10906 reg_names[frame_pointer_needed
10907 ? HARD_FRAME_POINTER_REGNUM
10908 : STACK_POINTER_REGNUM],
10909 (frame_pointer_needed
10910 ? frame->total_size - frame->hard_frame_pointer_offset
10911 : frame->total_size),
10912 reg_names[RETURN_ADDR_REGNUM],
10914 frame->num_gp, frame->num_fp,
10916 frame->cprestore_size);
10918 /* .mask MASK, OFFSET. */
10919 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
10920 frame->mask, frame->gp_save_offset);
10922 /* .fmask MASK, OFFSET. */
10923 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
10924 frame->fmask, frame->fp_save_offset);
10927 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
10928 Also emit the ".set noreorder; .set nomacro" sequence for functions
10930 if (mips_must_initialize_gp_p ()
10931 && mips_current_loadgp_style () == LOADGP_OLDABI)
10935 /* This is a fixed-form sequence. The position of the
10936 first two instructions is important because of the
10937 way _gp_disp is defined. */
10938 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
10939 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
10940 output_asm_insn ("sll\t$2,16", 0);
10941 output_asm_insn ("addu\t$2,$3", 0);
10945 /* .cpload must be in a .set noreorder but not a
10946 .set nomacro block. */
10947 mips_push_asm_switch (&mips_noreorder);
10948 output_asm_insn (".cpload\t%^", 0);
10949 if (!cfun->machine->all_noreorder_p)
10950 mips_pop_asm_switch (&mips_noreorder);
10952 mips_push_asm_switch (&mips_nomacro);
10955 else if (cfun->machine->all_noreorder_p)
10957 mips_push_asm_switch (&mips_noreorder);
10958 mips_push_asm_switch (&mips_nomacro);
10961 /* Tell the assembler which register we're using as the global
10962 pointer. This is needed for thunks, since they can use either
10963 explicit relocs or assembler macros. */
10964 mips_output_cplocal ();
10967 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
10970 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
10971 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
10973 const char *fnname;
10975 /* Reinstate the normal $gp. */
10976 SET_REGNO (pic_offset_table_rtx, GLOBAL_POINTER_REGNUM);
10977 mips_output_cplocal ();
10979 if (cfun->machine->all_noreorder_p)
10981 mips_pop_asm_switch (&mips_nomacro);
10982 mips_pop_asm_switch (&mips_noreorder);
10985 /* Get the function name the same way that toplev.c does before calling
10986 assemble_start_function. This is needed so that the name used here
10987 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10988 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
10989 mips_end_function_definition (fnname);
10992 /* Emit an optimisation barrier for accesses to the current frame. */
10995 mips_frame_barrier (void)
10997 emit_clobber (gen_frame_mem (BLKmode, stack_pointer_rtx));
11001 /* The __gnu_local_gp symbol. */
11003 static GTY(()) rtx mips_gnu_local_gp;
11005 /* If we're generating n32 or n64 abicalls, emit instructions
11006 to set up the global pointer. */
11009 mips_emit_loadgp (void)
11011 rtx addr, offset, incoming_address, base, index, pic_reg;
11013 pic_reg = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
11014 switch (mips_current_loadgp_style ())
11016 case LOADGP_ABSOLUTE:
11017 if (mips_gnu_local_gp == NULL)
11019 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
11020 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
11022 emit_insn (PMODE_INSN (gen_loadgp_absolute,
11023 (pic_reg, mips_gnu_local_gp)));
11026 case LOADGP_OLDABI:
11027 /* Added by mips_output_function_prologue. */
11030 case LOADGP_NEWABI:
11031 addr = XEXP (DECL_RTL (current_function_decl), 0);
11032 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
11033 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
11034 emit_insn (PMODE_INSN (gen_loadgp_newabi,
11035 (pic_reg, offset, incoming_address)));
11039 base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE));
11040 index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX));
11041 emit_insn (PMODE_INSN (gen_loadgp_rtp, (pic_reg, base, index)));
11049 emit_insn (PMODE_INSN (gen_copygp_mips16,
11050 (pic_offset_table_rtx, pic_reg)));
11052 /* Emit a blockage if there are implicit uses of the GP register.
11053 This includes profiled functions, because FUNCTION_PROFILE uses
11055 if (!TARGET_EXPLICIT_RELOCS || crtl->profile)
11056 emit_insn (gen_loadgp_blockage ());
11059 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
11061 #if PROBE_INTERVAL > 32768
11062 #error Cannot use indexed addressing mode for stack probing
11065 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
11066 inclusive. These are offsets from the current stack pointer. */
11069 mips_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size)
11072 sorry ("-fstack-check=specific not implemented for MIPS16");
11074 /* See if we have a constant small number of probes to generate. If so,
11075 that's the easy case. */
11076 if (first + size <= 32768)
11080 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
11081 it exceeds SIZE. If only one probe is needed, this will not
11082 generate any code. Then probe at FIRST + SIZE. */
11083 for (i = PROBE_INTERVAL; i < size; i += PROBE_INTERVAL)
11084 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
11087 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
11091 /* Otherwise, do the same as above, but in a loop. Note that we must be
11092 extra careful with variables wrapping around because we might be at
11093 the very top (or the very bottom) of the address space and we have
11094 to be able to handle this case properly; in particular, we use an
11095 equality test for the loop condition. */
11098 HOST_WIDE_INT rounded_size;
11099 rtx r3 = MIPS_PROLOGUE_TEMP (Pmode);
11100 rtx r12 = MIPS_PROLOGUE_TEMP2 (Pmode);
11102 /* Sanity check for the addressing mode we're going to use. */
11103 gcc_assert (first <= 32768);
11106 /* Step 1: round SIZE to the previous multiple of the interval. */
11108 rounded_size = size & -PROBE_INTERVAL;
11111 /* Step 2: compute initial and final value of the loop counter. */
11113 /* TEST_ADDR = SP + FIRST. */
11114 emit_insn (gen_rtx_SET (VOIDmode, r3,
11115 plus_constant (Pmode, stack_pointer_rtx,
11118 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
11119 if (rounded_size > 32768)
11121 emit_move_insn (r12, GEN_INT (rounded_size));
11122 emit_insn (gen_rtx_SET (VOIDmode, r12,
11123 gen_rtx_MINUS (Pmode, r3, r12)));
11126 emit_insn (gen_rtx_SET (VOIDmode, r12,
11127 plus_constant (Pmode, r3, -rounded_size)));
11130 /* Step 3: the loop
11132 while (TEST_ADDR != LAST_ADDR)
11134 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
11138 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
11139 until it is equal to ROUNDED_SIZE. */
11141 emit_insn (PMODE_INSN (gen_probe_stack_range, (r3, r3, r12)));
11144 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
11145 that SIZE is equal to ROUNDED_SIZE. */
11147 if (size != rounded_size)
11148 emit_stack_probe (plus_constant (Pmode, r12, rounded_size - size));
11151 /* Make sure nothing is scheduled before we are done. */
11152 emit_insn (gen_blockage ());
11155 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
11156 absolute addresses. */
11159 mips_output_probe_stack_range (rtx reg1, rtx reg2)
11161 static int labelno = 0;
11162 char loop_lab[32], end_lab[32], tmp[64];
11165 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno);
11166 ASM_GENERATE_INTERNAL_LABEL (end_lab, "LPSRE", labelno++);
11168 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
11170 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
11173 strcpy (tmp, "%(%<beq\t%0,%1,");
11174 output_asm_insn (strcat (tmp, &end_lab[1]), xops);
11176 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
11177 xops[1] = GEN_INT (-PROBE_INTERVAL);
11178 if (TARGET_64BIT && TARGET_LONG64)
11179 output_asm_insn ("daddiu\t%0,%0,%1", xops);
11181 output_asm_insn ("addiu\t%0,%0,%1", xops);
11183 /* Probe at TEST_ADDR and branch. */
11184 fprintf (asm_out_file, "\tb\t");
11185 assemble_name_raw (asm_out_file, loop_lab);
11186 fputc ('\n', asm_out_file);
11188 output_asm_insn ("sd\t$0,0(%0)%)", xops);
11190 output_asm_insn ("sw\t$0,0(%0)%)", xops);
11192 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, end_lab);
11197 /* Return true if X contains a kernel register. */
11200 mips_refers_to_kernel_reg_p (const_rtx x)
11202 subrtx_iterator::array_type array;
11203 FOR_EACH_SUBRTX (iter, array, x, NONCONST)
11204 if (REG_P (*iter) && KERNEL_REG_P (REGNO (*iter)))
11209 /* Expand the "prologue" pattern. */
11212 mips_expand_prologue (void)
11214 const struct mips_frame_info *frame;
11215 HOST_WIDE_INT size;
11216 unsigned int nargs;
11218 if (cfun->machine->global_pointer != INVALID_REGNUM)
11220 /* Check whether an insn uses pic_offset_table_rtx, either explicitly
11221 or implicitly. If so, we can commit to using a global pointer
11222 straight away, otherwise we need to defer the decision. */
11223 if (mips_cfun_has_inflexible_gp_ref_p ()
11224 || mips_cfun_has_flexible_gp_ref_p ())
11226 cfun->machine->must_initialize_gp_p = true;
11227 cfun->machine->must_restore_gp_when_clobbered_p = true;
11230 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
11233 frame = &cfun->machine->frame;
11234 size = frame->total_size;
11236 if (flag_stack_usage_info)
11237 current_function_static_stack_size = size;
11239 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK)
11241 if (crtl->is_leaf && !cfun->calls_alloca)
11243 if (size > PROBE_INTERVAL && size > STACK_CHECK_PROTECT)
11244 mips_emit_probe_stack_range (STACK_CHECK_PROTECT,
11245 size - STACK_CHECK_PROTECT);
11248 mips_emit_probe_stack_range (STACK_CHECK_PROTECT, size);
11251 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
11252 bytes beforehand; this is enough to cover the register save area
11253 without going out of range. */
11254 if (((frame->mask | frame->fmask | frame->acc_mask) != 0)
11255 || frame->num_cop0_regs > 0)
11257 HOST_WIDE_INT step1;
11259 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
11260 if (GENERATE_MIPS16E_SAVE_RESTORE)
11262 HOST_WIDE_INT offset;
11263 unsigned int mask, regno;
11265 /* Try to merge argument stores into the save instruction. */
11266 nargs = mips16e_collect_argument_saves ();
11268 /* Build the save instruction. */
11269 mask = frame->mask;
11270 rtx insn = mips16e_build_save_restore (false, &mask, &offset,
11272 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
11273 mips_frame_barrier ();
11276 /* Check if we need to save other registers. */
11277 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
11278 if (BITSET_P (mask, regno - GP_REG_FIRST))
11280 offset -= UNITS_PER_WORD;
11281 mips_save_restore_reg (word_mode, regno,
11282 offset, mips_save_reg);
11287 if (cfun->machine->interrupt_handler_p)
11289 HOST_WIDE_INT offset;
11292 /* If this interrupt is using a shadow register set, we need to
11293 get the stack pointer from the previous register set. */
11294 if (cfun->machine->use_shadow_register_set_p)
11295 emit_insn (gen_mips_rdpgpr (stack_pointer_rtx,
11296 stack_pointer_rtx));
11298 if (!cfun->machine->keep_interrupts_masked_p)
11300 /* Move from COP0 Cause to K0. */
11301 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K0_REG_NUM),
11302 gen_rtx_REG (SImode,
11303 COP0_CAUSE_REG_NUM)));
11304 /* Move from COP0 EPC to K1. */
11305 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
11306 gen_rtx_REG (SImode,
11307 COP0_EPC_REG_NUM)));
11310 /* Allocate the first part of the frame. */
11311 rtx insn = gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx,
11313 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
11314 mips_frame_barrier ();
11317 /* Start at the uppermost location for saving. */
11318 offset = frame->cop0_sp_offset - size;
11319 if (!cfun->machine->keep_interrupts_masked_p)
11321 /* Push EPC into its stack slot. */
11322 mem = gen_frame_mem (word_mode,
11323 plus_constant (Pmode, stack_pointer_rtx,
11325 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
11326 offset -= UNITS_PER_WORD;
11329 /* Move from COP0 Status to K1. */
11330 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
11331 gen_rtx_REG (SImode,
11332 COP0_STATUS_REG_NUM)));
11334 /* Right justify the RIPL in k0. */
11335 if (!cfun->machine->keep_interrupts_masked_p)
11336 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode, K0_REG_NUM),
11337 gen_rtx_REG (SImode, K0_REG_NUM),
11338 GEN_INT (CAUSE_IPL)));
11340 /* Push Status into its stack slot. */
11341 mem = gen_frame_mem (word_mode,
11342 plus_constant (Pmode, stack_pointer_rtx,
11344 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
11345 offset -= UNITS_PER_WORD;
11347 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
11348 if (!cfun->machine->keep_interrupts_masked_p)
11349 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
11352 gen_rtx_REG (SImode, K0_REG_NUM)));
11354 if (!cfun->machine->keep_interrupts_masked_p)
11355 /* Enable interrupts by clearing the KSU ERL and EXL bits.
11356 IE is already the correct value, so we don't have to do
11357 anything explicit. */
11358 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
11361 gen_rtx_REG (SImode, GP_REG_FIRST)));
11363 /* Disable interrupts by clearing the KSU, ERL, EXL,
11365 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
11368 gen_rtx_REG (SImode, GP_REG_FIRST)));
11372 rtx insn = gen_add3_insn (stack_pointer_rtx,
11375 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
11376 mips_frame_barrier ();
11379 mips_for_each_saved_acc (size, mips_save_reg);
11380 mips_for_each_saved_gpr_and_fpr (size, mips_save_reg);
11384 /* Allocate the rest of the frame. */
11387 if (SMALL_OPERAND (-size))
11388 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
11390 GEN_INT (-size)))) = 1;
11393 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
11396 /* There are no instructions to add or subtract registers
11397 from the stack pointer, so use the frame pointer as a
11398 temporary. We should always be using a frame pointer
11399 in this case anyway. */
11400 gcc_assert (frame_pointer_needed);
11401 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
11402 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
11403 hard_frame_pointer_rtx,
11404 MIPS_PROLOGUE_TEMP (Pmode)));
11405 mips_emit_move (stack_pointer_rtx, hard_frame_pointer_rtx);
11408 emit_insn (gen_sub3_insn (stack_pointer_rtx,
11410 MIPS_PROLOGUE_TEMP (Pmode)));
11412 /* Describe the combined effect of the previous instructions. */
11413 mips_set_frame_expr
11414 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
11415 plus_constant (Pmode, stack_pointer_rtx, -size)));
11417 mips_frame_barrier ();
11420 /* Set up the frame pointer, if we're using one. */
11421 if (frame_pointer_needed)
11423 HOST_WIDE_INT offset;
11425 offset = frame->hard_frame_pointer_offset;
11428 rtx insn = mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
11429 RTX_FRAME_RELATED_P (insn) = 1;
11431 else if (SMALL_OPERAND (offset))
11433 rtx insn = gen_add3_insn (hard_frame_pointer_rtx,
11434 stack_pointer_rtx, GEN_INT (offset));
11435 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
11439 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (offset));
11440 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
11441 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
11442 hard_frame_pointer_rtx,
11443 MIPS_PROLOGUE_TEMP (Pmode)));
11444 mips_set_frame_expr
11445 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
11446 plus_constant (Pmode, stack_pointer_rtx, offset)));
11450 mips_emit_loadgp ();
11452 /* Initialize the $gp save slot. */
11453 if (mips_cfun_has_cprestore_slot_p ())
11455 rtx base, mem, gp, temp;
11456 HOST_WIDE_INT offset;
11458 mips_get_cprestore_base_and_offset (&base, &offset, false);
11459 mem = gen_frame_mem (Pmode, plus_constant (Pmode, base, offset));
11460 gp = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
11461 temp = (SMALL_OPERAND (offset)
11462 ? gen_rtx_SCRATCH (Pmode)
11463 : MIPS_PROLOGUE_TEMP (Pmode));
11464 emit_insn (PMODE_INSN (gen_potential_cprestore,
11465 (mem, GEN_INT (offset), gp, temp)));
11467 mips_get_cprestore_base_and_offset (&base, &offset, true);
11468 mem = gen_frame_mem (Pmode, plus_constant (Pmode, base, offset));
11469 emit_insn (PMODE_INSN (gen_use_cprestore, (mem)));
11472 /* We need to search back to the last use of K0 or K1. */
11473 if (cfun->machine->interrupt_handler_p)
11476 for (insn = get_last_insn (); insn != NULL_RTX; insn = PREV_INSN (insn))
11478 && mips_refers_to_kernel_reg_p (PATTERN (insn)))
11480 /* Emit a move from K1 to COP0 Status after insn. */
11481 gcc_assert (insn != NULL_RTX);
11482 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
11483 gen_rtx_REG (SImode, K1_REG_NUM)),
11487 /* If we are profiling, make sure no instructions are scheduled before
11488 the call to mcount. */
11490 emit_insn (gen_blockage ());
11493 /* Attach all pending register saves to the previous instruction.
11494 Return that instruction. */
11497 mips_epilogue_emit_cfa_restores (void)
11501 insn = get_last_insn ();
11502 gcc_assert (insn && !REG_NOTES (insn));
11503 if (mips_epilogue.cfa_restores)
11505 RTX_FRAME_RELATED_P (insn) = 1;
11506 REG_NOTES (insn) = mips_epilogue.cfa_restores;
11507 mips_epilogue.cfa_restores = 0;
11512 /* Like mips_epilogue_emit_cfa_restores, but also record that the CFA is
11513 now at REG + OFFSET. */
11516 mips_epilogue_set_cfa (rtx reg, HOST_WIDE_INT offset)
11520 insn = mips_epilogue_emit_cfa_restores ();
11521 if (reg != mips_epilogue.cfa_reg || offset != mips_epilogue.cfa_offset)
11523 RTX_FRAME_RELATED_P (insn) = 1;
11524 REG_NOTES (insn) = alloc_reg_note (REG_CFA_DEF_CFA,
11525 plus_constant (Pmode, reg, offset),
11527 mips_epilogue.cfa_reg = reg;
11528 mips_epilogue.cfa_offset = offset;
11532 /* Emit instructions to restore register REG from slot MEM. Also update
11533 the cfa_restores list. */
11536 mips_restore_reg (rtx reg, rtx mem)
11538 /* There's no MIPS16 instruction to load $31 directly. Load into
11539 $7 instead and adjust the return insn appropriately. */
11540 if (TARGET_MIPS16 && REGNO (reg) == RETURN_ADDR_REGNUM)
11541 reg = gen_rtx_REG (GET_MODE (reg), GP_REG_FIRST + 7);
11542 else if (GET_MODE (reg) == DFmode
11543 && (!TARGET_FLOAT64
11544 || mips_abi == ABI_32))
11546 mips_add_cfa_restore (mips_subword (reg, true));
11547 mips_add_cfa_restore (mips_subword (reg, false));
11550 mips_add_cfa_restore (reg);
11552 mips_emit_save_slot_move (reg, mem, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
11553 if (REGNO (reg) == REGNO (mips_epilogue.cfa_reg))
11554 /* The CFA is currently defined in terms of the register whose
11555 value we have just restored. Redefine the CFA in terms of
11556 the stack pointer. */
11557 mips_epilogue_set_cfa (stack_pointer_rtx,
11558 mips_epilogue.cfa_restore_sp_offset);
11561 /* Emit code to set the stack pointer to BASE + OFFSET, given that
11562 BASE + OFFSET is NEW_FRAME_SIZE bytes below the top of the frame.
11563 BASE, if not the stack pointer, is available as a temporary. */
11566 mips_deallocate_stack (rtx base, rtx offset, HOST_WIDE_INT new_frame_size)
11568 if (base == stack_pointer_rtx && offset == const0_rtx)
11571 mips_frame_barrier ();
11572 if (offset == const0_rtx)
11574 emit_move_insn (stack_pointer_rtx, base);
11575 mips_epilogue_set_cfa (stack_pointer_rtx, new_frame_size);
11577 else if (TARGET_MIPS16 && base != stack_pointer_rtx)
11579 emit_insn (gen_add3_insn (base, base, offset));
11580 mips_epilogue_set_cfa (base, new_frame_size);
11581 emit_move_insn (stack_pointer_rtx, base);
11585 emit_insn (gen_add3_insn (stack_pointer_rtx, base, offset));
11586 mips_epilogue_set_cfa (stack_pointer_rtx, new_frame_size);
11590 /* Emit any instructions needed before a return. */
11593 mips_expand_before_return (void)
11595 /* When using a call-clobbered gp, we start out with unified call
11596 insns that include instructions to restore the gp. We then split
11597 these unified calls after reload. These split calls explicitly
11598 clobber gp, so there is no need to define
11599 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
11601 For consistency, we should also insert an explicit clobber of $28
11602 before return insns, so that the post-reload optimizers know that
11603 the register is not live on exit. */
11604 if (TARGET_CALL_CLOBBERED_GP)
11605 emit_clobber (pic_offset_table_rtx);
11608 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
11612 mips_expand_epilogue (bool sibcall_p)
11614 const struct mips_frame_info *frame;
11615 HOST_WIDE_INT step1, step2;
11618 bool use_jraddiusp_p = false;
11620 if (!sibcall_p && mips_can_use_return_insn ())
11622 emit_jump_insn (gen_return ());
11626 /* In MIPS16 mode, if the return value should go into a floating-point
11627 register, we need to call a helper routine to copy it over. */
11628 if (mips16_cfun_returns_in_fpr_p ())
11629 mips16_copy_fpr_return_value ();
11631 /* Split the frame into two. STEP1 is the amount of stack we should
11632 deallocate before restoring the registers. STEP2 is the amount we
11633 should deallocate afterwards.
11635 Start off by assuming that no registers need to be restored. */
11636 frame = &cfun->machine->frame;
11637 step1 = frame->total_size;
11640 /* Work out which register holds the frame address. */
11641 if (!frame_pointer_needed)
11642 base = stack_pointer_rtx;
11645 base = hard_frame_pointer_rtx;
11646 step1 -= frame->hard_frame_pointer_offset;
11648 mips_epilogue.cfa_reg = base;
11649 mips_epilogue.cfa_offset = step1;
11650 mips_epilogue.cfa_restores = NULL_RTX;
11652 /* If we need to restore registers, deallocate as much stack as
11653 possible in the second step without going out of range. */
11654 if ((frame->mask | frame->fmask | frame->acc_mask) != 0
11655 || frame->num_cop0_regs > 0)
11657 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
11661 /* Get an rtx for STEP1 that we can add to BASE. */
11662 adjust = GEN_INT (step1);
11663 if (!SMALL_OPERAND (step1))
11665 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), adjust);
11666 adjust = MIPS_EPILOGUE_TEMP (Pmode);
11668 mips_deallocate_stack (base, adjust, step2);
11670 /* If we're using addressing macros, $gp is implicitly used by all
11671 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
11673 if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS)
11674 emit_insn (gen_blockage ());
11676 mips_epilogue.cfa_restore_sp_offset = step2;
11677 if (GENERATE_MIPS16E_SAVE_RESTORE && frame->mask != 0)
11679 unsigned int regno, mask;
11680 HOST_WIDE_INT offset;
11683 /* Generate the restore instruction. */
11684 mask = frame->mask;
11685 restore = mips16e_build_save_restore (true, &mask, &offset, 0, step2);
11687 /* Restore any other registers manually. */
11688 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
11689 if (BITSET_P (mask, regno - GP_REG_FIRST))
11691 offset -= UNITS_PER_WORD;
11692 mips_save_restore_reg (word_mode, regno, offset, mips_restore_reg);
11695 /* Restore the remaining registers and deallocate the final bit
11697 mips_frame_barrier ();
11698 emit_insn (restore);
11699 mips_epilogue_set_cfa (stack_pointer_rtx, 0);
11703 /* Restore the registers. */
11704 mips_for_each_saved_acc (frame->total_size - step2, mips_restore_reg);
11705 mips_for_each_saved_gpr_and_fpr (frame->total_size - step2,
11708 if (cfun->machine->interrupt_handler_p)
11710 HOST_WIDE_INT offset;
11713 offset = frame->cop0_sp_offset - (frame->total_size - step2);
11714 if (!cfun->machine->keep_interrupts_masked_p)
11716 /* Restore the original EPC. */
11717 mem = gen_frame_mem (word_mode,
11718 plus_constant (Pmode, stack_pointer_rtx,
11720 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
11721 offset -= UNITS_PER_WORD;
11723 /* Move to COP0 EPC. */
11724 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_EPC_REG_NUM),
11725 gen_rtx_REG (SImode, K0_REG_NUM)));
11728 /* Restore the original Status. */
11729 mem = gen_frame_mem (word_mode,
11730 plus_constant (Pmode, stack_pointer_rtx,
11732 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
11733 offset -= UNITS_PER_WORD;
11735 /* If we don't use shadow register set, we need to update SP. */
11736 if (!cfun->machine->use_shadow_register_set_p)
11737 mips_deallocate_stack (stack_pointer_rtx, GEN_INT (step2), 0);
11739 /* The choice of position is somewhat arbitrary in this case. */
11740 mips_epilogue_emit_cfa_restores ();
11742 /* Move to COP0 Status. */
11743 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
11744 gen_rtx_REG (SImode, K0_REG_NUM)));
11746 else if (TARGET_MICROMIPS
11747 && !crtl->calls_eh_return
11750 && mips_unsigned_immediate_p (step2, 5, 2))
11751 use_jraddiusp_p = true;
11753 /* Deallocate the final bit of the frame. */
11754 mips_deallocate_stack (stack_pointer_rtx, GEN_INT (step2), 0);
11757 if (!use_jraddiusp_p)
11758 gcc_assert (!mips_epilogue.cfa_restores);
11760 /* Add in the __builtin_eh_return stack adjustment. We need to
11761 use a temporary in MIPS16 code. */
11762 if (crtl->calls_eh_return)
11766 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
11767 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
11768 MIPS_EPILOGUE_TEMP (Pmode),
11769 EH_RETURN_STACKADJ_RTX));
11770 mips_emit_move (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
11773 emit_insn (gen_add3_insn (stack_pointer_rtx,
11775 EH_RETURN_STACKADJ_RTX));
11780 mips_expand_before_return ();
11781 if (cfun->machine->interrupt_handler_p)
11783 /* Interrupt handlers generate eret or deret. */
11784 if (cfun->machine->use_debug_exception_return_p)
11785 emit_jump_insn (gen_mips_deret ());
11787 emit_jump_insn (gen_mips_eret ());
11793 /* When generating MIPS16 code, the normal
11794 mips_for_each_saved_gpr_and_fpr path will restore the return
11795 address into $7 rather than $31. */
11797 && !GENERATE_MIPS16E_SAVE_RESTORE
11798 && BITSET_P (frame->mask, RETURN_ADDR_REGNUM))
11800 /* simple_returns cannot rely on values that are only available
11801 on paths through the epilogue (because return paths that do
11802 not pass through the epilogue may nevertheless reuse a
11803 simple_return that occurs at the end of the epilogue).
11804 Use a normal return here instead. */
11805 rtx reg = gen_rtx_REG (Pmode, GP_REG_FIRST + 7);
11806 pat = gen_return_internal (reg);
11808 else if (use_jraddiusp_p)
11809 pat = gen_jraddiusp (GEN_INT (step2));
11812 rtx reg = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
11813 pat = gen_simple_return_internal (reg);
11815 emit_jump_insn (pat);
11816 if (use_jraddiusp_p)
11817 mips_epilogue_set_cfa (stack_pointer_rtx, step2);
11821 /* Search from the beginning to the first use of K0 or K1. */
11822 if (cfun->machine->interrupt_handler_p
11823 && !cfun->machine->keep_interrupts_masked_p)
11825 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
11827 && mips_refers_to_kernel_reg_p (PATTERN (insn)))
11829 gcc_assert (insn != NULL_RTX);
11830 /* Insert disable interrupts before the first use of K0 or K1. */
11831 emit_insn_before (gen_mips_di (), insn);
11832 emit_insn_before (gen_mips_ehb (), insn);
11836 /* Return nonzero if this function is known to have a null epilogue.
11837 This allows the optimizer to omit jumps to jumps if no stack
11841 mips_can_use_return_insn (void)
11843 /* Interrupt handlers need to go through the epilogue. */
11844 if (cfun->machine->interrupt_handler_p)
11847 if (!reload_completed)
11853 /* In MIPS16 mode, a function that returns a floating-point value
11854 needs to arrange to copy the return value into the floating-point
11856 if (mips16_cfun_returns_in_fpr_p ())
11859 return cfun->machine->frame.total_size == 0;
11862 /* Return true if register REGNO can store a value of mode MODE.
11863 The result of this function is cached in mips_hard_regno_mode_ok. */
11866 mips_hard_regno_mode_ok_p (unsigned int regno, machine_mode mode)
11869 enum mode_class mclass;
11871 if (mode == CCV2mode)
11872 return (ISA_HAS_8CC
11873 && ST_REG_P (regno)
11874 && (regno - ST_REG_FIRST) % 2 == 0);
11876 if (mode == CCV4mode)
11877 return (ISA_HAS_8CC
11878 && ST_REG_P (regno)
11879 && (regno - ST_REG_FIRST) % 4 == 0);
11881 if (mode == CCmode)
11882 return ISA_HAS_8CC ? ST_REG_P (regno) : regno == FPSW_REGNUM;
11884 size = GET_MODE_SIZE (mode);
11885 mclass = GET_MODE_CLASS (mode);
11887 if (GP_REG_P (regno))
11888 return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD;
11890 if (FP_REG_P (regno)
11891 && (((regno - FP_REG_FIRST) % MAX_FPRS_PER_FMT) == 0
11892 || (MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG)))
11894 /* Deny use of odd-numbered registers for 32-bit data for
11895 the o32 FP64A ABI. */
11896 if (TARGET_O32_FP64A_ABI && size <= 4 && (regno & 1) != 0)
11899 /* Allow 64-bit vector modes for Loongson-2E/2F. */
11900 if (TARGET_LOONGSON_VECTORS
11901 && (mode == V2SImode
11902 || mode == V4HImode
11903 || mode == V8QImode
11904 || mode == DImode))
11907 if (mclass == MODE_FLOAT
11908 || mclass == MODE_COMPLEX_FLOAT
11909 || mclass == MODE_VECTOR_FLOAT)
11910 return size <= UNITS_PER_FPVALUE;
11912 /* Allow integer modes that fit into a single register. We need
11913 to put integers into FPRs when using instructions like CVT
11914 and TRUNC. There's no point allowing sizes smaller than a word,
11915 because the FPU has no appropriate load/store instructions. */
11916 if (mclass == MODE_INT)
11917 return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG;
11920 if (ACC_REG_P (regno)
11921 && (INTEGRAL_MODE_P (mode) || ALL_FIXED_POINT_MODE_P (mode)))
11923 if (MD_REG_P (regno))
11925 /* After a multiplication or division, clobbering HI makes
11926 the value of LO unpredictable, and vice versa. This means
11927 that, for all interesting cases, HI and LO are effectively
11930 We model this by requiring that any value that uses HI
11932 if (size <= UNITS_PER_WORD * 2)
11933 return regno == (size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST);
11937 /* DSP accumulators do not have the same restrictions as
11938 HI and LO, so we can treat them as normal doubleword
11940 if (size <= UNITS_PER_WORD)
11943 if (size <= UNITS_PER_WORD * 2
11944 && ((regno - DSP_ACC_REG_FIRST) & 1) == 0)
11949 if (ALL_COP_REG_P (regno))
11950 return mclass == MODE_INT && size <= UNITS_PER_WORD;
11952 if (regno == GOT_VERSION_REGNUM)
11953 return mode == SImode;
11958 /* Implement HARD_REGNO_NREGS. */
11961 mips_hard_regno_nregs (int regno, machine_mode mode)
11963 if (ST_REG_P (regno))
11964 /* The size of FP status registers is always 4, because they only hold
11965 CCmode values, and CCmode is always considered to be 4 bytes wide. */
11966 return (GET_MODE_SIZE (mode) + 3) / 4;
11968 if (FP_REG_P (regno))
11969 return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG;
11971 /* All other registers are word-sized. */
11972 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
11975 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
11976 in mips_hard_regno_nregs. */
11979 mips_class_max_nregs (enum reg_class rclass, machine_mode mode)
11985 COPY_HARD_REG_SET (left, reg_class_contents[(int) rclass]);
11986 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS]))
11988 if (HARD_REGNO_MODE_OK (ST_REG_FIRST, mode))
11989 size = MIN (size, 4);
11990 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) ST_REGS]);
11992 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS]))
11994 if (HARD_REGNO_MODE_OK (FP_REG_FIRST, mode))
11995 size = MIN (size, UNITS_PER_FPREG);
11996 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]);
11998 if (!hard_reg_set_empty_p (left))
11999 size = MIN (size, UNITS_PER_WORD);
12000 return (GET_MODE_SIZE (mode) + size - 1) / size;
12003 /* Implement CANNOT_CHANGE_MODE_CLASS. */
12006 mips_cannot_change_mode_class (machine_mode from,
12008 enum reg_class rclass)
12010 /* Allow conversions between different Loongson integer vectors,
12011 and between those vectors and DImode. */
12012 if (GET_MODE_SIZE (from) == 8 && GET_MODE_SIZE (to) == 8
12013 && INTEGRAL_MODE_P (from) && INTEGRAL_MODE_P (to))
12016 /* Otherwise, there are several problems with changing the modes of
12017 values in floating-point registers:
12019 - When a multi-word value is stored in paired floating-point
12020 registers, the first register always holds the low word. We
12021 therefore can't allow FPRs to change between single-word and
12022 multi-word modes on big-endian targets.
12024 - GCC assumes that each word of a multiword register can be
12025 accessed individually using SUBREGs. This is not true for
12026 floating-point registers if they are bigger than a word.
12028 - Loading a 32-bit value into a 64-bit floating-point register
12029 will not sign-extend the value, despite what LOAD_EXTEND_OP
12030 says. We can't allow FPRs to change from SImode to a wider
12031 mode on 64-bit targets.
12033 - If the FPU has already interpreted a value in one format, we
12034 must not ask it to treat the value as having a different
12037 We therefore disallow all mode changes involving FPRs. */
12039 return reg_classes_intersect_p (FP_REGS, rclass);
12042 /* Implement target hook small_register_classes_for_mode_p. */
12045 mips_small_register_classes_for_mode_p (machine_mode mode
12048 return TARGET_MIPS16;
12051 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
12054 mips_mode_ok_for_mov_fmt_p (machine_mode mode)
12059 return TARGET_HARD_FLOAT;
12062 return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT;
12065 return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT;
12072 /* Implement MODES_TIEABLE_P. */
12075 mips_modes_tieable_p (machine_mode mode1, machine_mode mode2)
12077 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
12078 prefer to put one of them in FPRs. */
12079 return (mode1 == mode2
12080 || (!mips_mode_ok_for_mov_fmt_p (mode1)
12081 && !mips_mode_ok_for_mov_fmt_p (mode2)));
12084 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
12087 mips_preferred_reload_class (rtx x, reg_class_t rclass)
12089 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, rclass))
12092 if (reg_class_subset_p (FP_REGS, rclass)
12093 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x)))
12096 if (reg_class_subset_p (GR_REGS, rclass))
12099 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, rclass))
12105 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
12106 Return a "canonical" class to represent it in later calculations. */
12109 mips_canonicalize_move_class (reg_class_t rclass)
12111 /* All moves involving accumulator registers have the same cost. */
12112 if (reg_class_subset_p (rclass, ACC_REGS))
12115 /* Likewise promote subclasses of general registers to the most
12116 interesting containing class. */
12117 if (TARGET_MIPS16 && reg_class_subset_p (rclass, M16_REGS))
12119 else if (reg_class_subset_p (rclass, GENERAL_REGS))
12120 rclass = GENERAL_REGS;
12125 /* Return the cost of moving a value from a register of class FROM to a GPR.
12126 Return 0 for classes that are unions of other classes handled by this
12130 mips_move_to_gpr_cost (reg_class_t from)
12136 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
12140 /* MFLO and MFHI. */
12150 /* This choice of value is historical. */
12158 /* Return the cost of moving a value from a GPR to a register of class TO.
12159 Return 0 for classes that are unions of other classes handled by this
12163 mips_move_from_gpr_cost (reg_class_t to)
12169 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
12173 /* MTLO and MTHI. */
12183 /* This choice of value is historical. */
12191 /* Implement TARGET_REGISTER_MOVE_COST. Return 0 for classes that are the
12192 maximum of the move costs for subclasses; regclass will work out
12193 the maximum for us. */
12196 mips_register_move_cost (machine_mode mode,
12197 reg_class_t from, reg_class_t to)
12202 from = mips_canonicalize_move_class (from);
12203 to = mips_canonicalize_move_class (to);
12205 /* Handle moves that can be done without using general-purpose registers. */
12206 if (from == FP_REGS)
12208 if (to == FP_REGS && mips_mode_ok_for_mov_fmt_p (mode))
12213 /* Handle cases in which only one class deviates from the ideal. */
12214 dregs = TARGET_MIPS16 ? M16_REGS : GENERAL_REGS;
12216 return mips_move_from_gpr_cost (to);
12218 return mips_move_to_gpr_cost (from);
12220 /* Handles cases that require a GPR temporary. */
12221 cost1 = mips_move_to_gpr_cost (from);
12224 cost2 = mips_move_from_gpr_cost (to);
12226 return cost1 + cost2;
12232 /* Implement TARGET_REGISTER_PRIORITY. */
12235 mips_register_priority (int hard_regno)
12237 /* Treat MIPS16 registers with higher priority than other regs. */
12239 && TEST_HARD_REG_BIT (reg_class_contents[M16_REGS], hard_regno))
12244 /* Implement TARGET_MEMORY_MOVE_COST. */
12247 mips_memory_move_cost (machine_mode mode, reg_class_t rclass, bool in)
12249 return (mips_cost->memory_latency
12250 + memory_move_secondary_cost (mode, rclass, in));
12253 /* Implement SECONDARY_MEMORY_NEEDED. */
12256 mips_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
12259 /* Ignore spilled pseudos. */
12260 if (lra_in_progress && (class1 == NO_REGS || class2 == NO_REGS))
12263 if (((class1 == FP_REGS) != (class2 == FP_REGS))
12264 && ((TARGET_FLOATXX && !ISA_HAS_MXHC1)
12265 || TARGET_O32_FP64A_ABI)
12266 && GET_MODE_SIZE (mode) >= 8)
12272 /* Return the register class required for a secondary register when
12273 copying between one of the registers in RCLASS and value X, which
12274 has mode MODE. X is the source of the move if IN_P, otherwise it
12275 is the destination. Return NO_REGS if no secondary register is
12279 mips_secondary_reload_class (enum reg_class rclass,
12280 machine_mode mode, rtx x, bool)
12284 /* If X is a constant that cannot be loaded into $25, it must be loaded
12285 into some other GPR. No other register class allows a direct move. */
12286 if (mips_dangerous_for_la25_p (x))
12287 return reg_class_subset_p (rclass, LEA_REGS) ? NO_REGS : LEA_REGS;
12289 regno = true_regnum (x);
12292 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
12293 if (!reg_class_subset_p (rclass, M16_REGS) && !M16_REG_P (regno))
12299 /* Copying from accumulator registers to anywhere other than a general
12300 register requires a temporary general register. */
12301 if (reg_class_subset_p (rclass, ACC_REGS))
12302 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
12303 if (ACC_REG_P (regno))
12304 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
12306 if (reg_class_subset_p (rclass, FP_REGS))
12310 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8)))
12311 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
12312 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
12315 if (GP_REG_P (regno) || x == CONST0_RTX (mode))
12316 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
12319 if (CONSTANT_P (x) && !targetm.cannot_force_const_mem (mode, x))
12320 /* We can force the constant to memory and use lwc1
12321 and ldc1. As above, we will use pairs of lwc1s if
12322 ldc1 is not supported. */
12325 if (FP_REG_P (regno) && mips_mode_ok_for_mov_fmt_p (mode))
12326 /* In this case we can use mov.fmt. */
12329 /* Otherwise, we need to reload through an integer register. */
12332 if (FP_REG_P (regno))
12333 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
12338 /* Implement TARGET_MODE_REP_EXTENDED. */
12341 mips_mode_rep_extended (machine_mode mode, machine_mode mode_rep)
12343 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
12344 if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
12345 return SIGN_EXTEND;
12350 /* Implement TARGET_VALID_POINTER_MODE. */
12353 mips_valid_pointer_mode (machine_mode mode)
12355 return mode == SImode || (TARGET_64BIT && mode == DImode);
12358 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
12361 mips_vector_mode_supported_p (machine_mode mode)
12366 return TARGET_PAIRED_SINGLE_FLOAT;
12381 return TARGET_LOONGSON_VECTORS;
12388 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
12391 mips_scalar_mode_supported_p (machine_mode mode)
12393 if (ALL_FIXED_POINT_MODE_P (mode)
12394 && GET_MODE_PRECISION (mode) <= 2 * BITS_PER_WORD)
12397 return default_scalar_mode_supported_p (mode);
12400 /* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
12402 static machine_mode
12403 mips_preferred_simd_mode (machine_mode mode ATTRIBUTE_UNUSED)
12405 if (TARGET_PAIRED_SINGLE_FLOAT
12411 /* Implement TARGET_INIT_LIBFUNCS. */
12414 mips_init_libfuncs (void)
12416 if (TARGET_FIX_VR4120)
12418 /* Register the special divsi3 and modsi3 functions needed to work
12419 around VR4120 division errata. */
12420 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
12421 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
12424 if (TARGET_MIPS16 && TARGET_HARD_FLOAT_ABI)
12426 /* Register the MIPS16 -mhard-float stubs. */
12427 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
12428 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
12429 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
12430 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
12432 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
12433 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
12434 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
12435 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
12436 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
12437 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
12438 set_optab_libfunc (unord_optab, SFmode, "__mips16_unordsf2");
12440 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
12441 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
12442 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__mips16_floatunsisf");
12444 if (TARGET_DOUBLE_FLOAT)
12446 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
12447 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
12448 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
12449 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
12451 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
12452 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
12453 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
12454 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
12455 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
12456 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
12457 set_optab_libfunc (unord_optab, DFmode, "__mips16_unorddf2");
12459 set_conv_libfunc (sext_optab, DFmode, SFmode,
12460 "__mips16_extendsfdf2");
12461 set_conv_libfunc (trunc_optab, SFmode, DFmode,
12462 "__mips16_truncdfsf2");
12463 set_conv_libfunc (sfix_optab, SImode, DFmode,
12464 "__mips16_fix_truncdfsi");
12465 set_conv_libfunc (sfloat_optab, DFmode, SImode,
12466 "__mips16_floatsidf");
12467 set_conv_libfunc (ufloat_optab, DFmode, SImode,
12468 "__mips16_floatunsidf");
12472 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
12473 on an external non-MIPS16 routine to implement __sync_synchronize.
12474 Similarly for the rest of the ll/sc libfuncs. */
12477 synchronize_libfunc = init_one_libfunc ("__sync_synchronize");
12478 init_sync_libfuncs (UNITS_PER_WORD);
12482 /* Build up a multi-insn sequence that loads label TARGET into $AT. */
12485 mips_process_load_label (rtx target)
12487 rtx base, gp, intop;
12488 HOST_WIDE_INT offset;
12490 mips_multi_start ();
12494 mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target, 0);
12495 mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target, 0);
12499 mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target, 0);
12500 mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target, 0);
12504 gp = pic_offset_table_rtx;
12505 if (mips_cfun_has_cprestore_slot_p ())
12507 gp = gen_rtx_REG (Pmode, AT_REGNUM);
12508 mips_get_cprestore_base_and_offset (&base, &offset, true);
12509 if (!SMALL_OPERAND (offset))
12511 intop = GEN_INT (CONST_HIGH_PART (offset));
12512 mips_multi_add_insn ("lui\t%0,%1", gp, intop, 0);
12513 mips_multi_add_insn ("addu\t%0,%0,%1", gp, base, 0);
12516 offset = CONST_LOW_PART (offset);
12518 intop = GEN_INT (offset);
12519 if (ISA_HAS_LOAD_DELAY)
12520 mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp, intop, base, 0);
12522 mips_multi_add_insn ("lw\t%0,%1(%2)", gp, intop, base, 0);
12524 if (ISA_HAS_LOAD_DELAY)
12525 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target, gp, 0);
12527 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target, gp, 0);
12528 mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target, 0);
12533 /* Return the number of instructions needed to load a label into $AT. */
12535 static unsigned int
12536 mips_load_label_num_insns (void)
12538 if (cfun->machine->load_label_num_insns == 0)
12540 mips_process_load_label (pc_rtx);
12541 cfun->machine->load_label_num_insns = mips_multi_num_insns;
12543 return cfun->machine->load_label_num_insns;
12546 /* Emit an asm sequence to start a noat block and load the address
12547 of a label into $1. */
12550 mips_output_load_label (rtx target)
12552 mips_push_asm_switch (&mips_noat);
12553 if (TARGET_EXPLICIT_RELOCS)
12555 mips_process_load_label (target);
12556 mips_multi_write ();
12560 if (Pmode == DImode)
12561 output_asm_insn ("dla\t%@,%0", &target);
12563 output_asm_insn ("la\t%@,%0", &target);
12567 /* Return the length of INSN. LENGTH is the initial length computed by
12568 attributes in the machine-description file. */
12571 mips_adjust_insn_length (rtx_insn *insn, int length)
12573 /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length
12574 of a PIC long-branch sequence. Substitute the correct value. */
12575 if (length == MAX_PIC_BRANCH_LENGTH
12577 && INSN_CODE (insn) >= 0
12578 && get_attr_type (insn) == TYPE_BRANCH)
12580 /* Add the branch-over instruction and its delay slot, if this
12581 is a conditional branch. */
12582 length = simplejump_p (insn) ? 0 : 8;
12584 /* Add the size of a load into $AT. */
12585 length += BASE_INSN_LENGTH * mips_load_label_num_insns ();
12587 /* Add the length of an indirect jump, ignoring the delay slot. */
12588 length += TARGET_COMPRESSION ? 2 : 4;
12591 /* A unconditional jump has an unfilled delay slot if it is not part
12592 of a sequence. A conditional jump normally has a delay slot, but
12593 does not on MIPS16. */
12594 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
12595 length += TARGET_MIPS16 ? 2 : 4;
12597 /* See how many nops might be needed to avoid hardware hazards. */
12598 if (!cfun->machine->ignore_hazard_length_p
12600 && INSN_CODE (insn) >= 0)
12601 switch (get_attr_hazard (insn))
12607 length += NOP_INSN_LENGTH;
12611 length += NOP_INSN_LENGTH * 2;
12618 /* Return the assembly code for INSN, which has the operands given by
12619 OPERANDS, and which branches to OPERANDS[0] if some condition is true.
12620 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0]
12621 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
12622 version of BRANCH_IF_TRUE. */
12625 mips_output_conditional_branch (rtx_insn *insn, rtx *operands,
12626 const char *branch_if_true,
12627 const char *branch_if_false)
12629 unsigned int length;
12632 gcc_assert (LABEL_P (operands[0]));
12634 length = get_attr_length (insn);
12637 /* Just a simple conditional branch. */
12638 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
12639 return branch_if_true;
12642 /* Generate a reversed branch around a direct jump. This fallback does
12643 not use branch-likely instructions. */
12644 mips_branch_likely = false;
12645 rtx_code_label *not_taken = gen_label_rtx ();
12646 taken = operands[0];
12648 /* Generate the reversed branch to NOT_TAKEN. */
12649 operands[0] = not_taken;
12650 output_asm_insn (branch_if_false, operands);
12652 /* If INSN has a delay slot, we must provide delay slots for both the
12653 branch to NOT_TAKEN and the conditional jump. We must also ensure
12654 that INSN's delay slot is executed in the appropriate cases. */
12655 if (final_sequence)
12657 /* This first delay slot will always be executed, so use INSN's
12658 delay slot if is not annulled. */
12659 if (!INSN_ANNULLED_BRANCH_P (insn))
12661 final_scan_insn (final_sequence->insn (1),
12662 asm_out_file, optimize, 1, NULL);
12663 final_sequence->insn (1)->set_deleted ();
12666 output_asm_insn ("nop", 0);
12667 fprintf (asm_out_file, "\n");
12670 /* Output the unconditional branch to TAKEN. */
12671 if (TARGET_ABSOLUTE_JUMPS)
12672 output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken);
12675 mips_output_load_label (taken);
12676 output_asm_insn ("jr\t%@%]%/", 0);
12679 /* Now deal with its delay slot; see above. */
12680 if (final_sequence)
12682 /* This delay slot will only be executed if the branch is taken.
12683 Use INSN's delay slot if is annulled. */
12684 if (INSN_ANNULLED_BRANCH_P (insn))
12686 final_scan_insn (final_sequence->insn (1),
12687 asm_out_file, optimize, 1, NULL);
12688 final_sequence->insn (1)->set_deleted ();
12691 output_asm_insn ("nop", 0);
12692 fprintf (asm_out_file, "\n");
12695 /* Output NOT_TAKEN. */
12696 targetm.asm_out.internal_label (asm_out_file, "L",
12697 CODE_LABEL_NUMBER (not_taken));
12701 /* Return the assembly code for INSN, which branches to OPERANDS[0]
12702 if some ordering condition is true. The condition is given by
12703 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
12704 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
12705 its second is always zero. */
12708 mips_output_order_conditional_branch (rtx_insn *insn, rtx *operands, bool inverted_p)
12710 const char *branch[2];
12712 /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true.
12713 Make BRANCH[0] branch on the inverse condition. */
12714 switch (GET_CODE (operands[1]))
12716 /* These cases are equivalent to comparisons against zero. */
12718 inverted_p = !inverted_p;
12719 /* Fall through. */
12721 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%0");
12722 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%0");
12725 /* These cases are always true or always false. */
12727 inverted_p = !inverted_p;
12728 /* Fall through. */
12730 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%0");
12731 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%0");
12735 branch[!inverted_p] = MIPS_BRANCH ("b%C1z", "%2,%0");
12736 branch[inverted_p] = MIPS_BRANCH ("b%N1z", "%2,%0");
12739 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
12742 /* Start a block of code that needs access to the LL, SC and SYNC
12746 mips_start_ll_sc_sync_block (void)
12748 if (!ISA_HAS_LL_SC)
12750 output_asm_insn (".set\tpush", 0);
12752 output_asm_insn (".set\tmips3", 0);
12754 output_asm_insn (".set\tmips2", 0);
12758 /* End a block started by mips_start_ll_sc_sync_block. */
12761 mips_end_ll_sc_sync_block (void)
12763 if (!ISA_HAS_LL_SC)
12764 output_asm_insn (".set\tpop", 0);
12767 /* Output and/or return the asm template for a sync instruction. */
12770 mips_output_sync (void)
12772 mips_start_ll_sc_sync_block ();
12773 output_asm_insn ("sync", 0);
12774 mips_end_ll_sc_sync_block ();
12778 /* Return the asm template associated with sync_insn1 value TYPE.
12779 IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */
12781 static const char *
12782 mips_sync_insn1_template (enum attr_sync_insn1 type, bool is_64bit_p)
12786 case SYNC_INSN1_MOVE:
12787 return "move\t%0,%z2";
12788 case SYNC_INSN1_LI:
12789 return "li\t%0,%2";
12790 case SYNC_INSN1_ADDU:
12791 return is_64bit_p ? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2";
12792 case SYNC_INSN1_ADDIU:
12793 return is_64bit_p ? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2";
12794 case SYNC_INSN1_SUBU:
12795 return is_64bit_p ? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2";
12796 case SYNC_INSN1_AND:
12797 return "and\t%0,%1,%z2";
12798 case SYNC_INSN1_ANDI:
12799 return "andi\t%0,%1,%2";
12800 case SYNC_INSN1_OR:
12801 return "or\t%0,%1,%z2";
12802 case SYNC_INSN1_ORI:
12803 return "ori\t%0,%1,%2";
12804 case SYNC_INSN1_XOR:
12805 return "xor\t%0,%1,%z2";
12806 case SYNC_INSN1_XORI:
12807 return "xori\t%0,%1,%2";
12809 gcc_unreachable ();
12812 /* Return the asm template associated with sync_insn2 value TYPE. */
12814 static const char *
12815 mips_sync_insn2_template (enum attr_sync_insn2 type)
12819 case SYNC_INSN2_NOP:
12820 gcc_unreachable ();
12821 case SYNC_INSN2_AND:
12822 return "and\t%0,%1,%z2";
12823 case SYNC_INSN2_XOR:
12824 return "xor\t%0,%1,%z2";
12825 case SYNC_INSN2_NOT:
12826 return "nor\t%0,%1,%.";
12828 gcc_unreachable ();
12831 /* OPERANDS are the operands to a sync loop instruction and INDEX is
12832 the value of the one of the sync_* attributes. Return the operand
12833 referred to by the attribute, or DEFAULT_VALUE if the insn doesn't
12834 have the associated attribute. */
12837 mips_get_sync_operand (rtx *operands, int index, rtx default_value)
12840 default_value = operands[index - 1];
12841 return default_value;
12844 /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn
12845 sequence for it. */
12848 mips_process_sync_loop (rtx_insn *insn, rtx *operands)
12850 rtx at, mem, oldval, newval, inclusive_mask, exclusive_mask;
12851 rtx required_oldval, insn1_op2, tmp1, tmp2, tmp3, cmp;
12852 unsigned int tmp3_insn;
12853 enum attr_sync_insn1 insn1;
12854 enum attr_sync_insn2 insn2;
12857 enum memmodel model;
12859 /* Read an operand from the sync_WHAT attribute and store it in
12860 variable WHAT. DEFAULT is the default value if no attribute
12862 #define READ_OPERAND(WHAT, DEFAULT) \
12863 WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \
12866 /* Read the memory. */
12867 READ_OPERAND (mem, 0);
12869 is_64bit_p = (GET_MODE_BITSIZE (GET_MODE (mem)) == 64);
12871 /* Read the other attributes. */
12872 at = gen_rtx_REG (GET_MODE (mem), AT_REGNUM);
12873 READ_OPERAND (oldval, at);
12874 READ_OPERAND (cmp, 0);
12875 READ_OPERAND (newval, at);
12876 READ_OPERAND (inclusive_mask, 0);
12877 READ_OPERAND (exclusive_mask, 0);
12878 READ_OPERAND (required_oldval, 0);
12879 READ_OPERAND (insn1_op2, 0);
12880 insn1 = get_attr_sync_insn1 (insn);
12881 insn2 = get_attr_sync_insn2 (insn);
12883 /* Don't bother setting CMP result that is never used. */
12884 if (cmp && find_reg_note (insn, REG_UNUSED, cmp))
12887 memmodel_attr = get_attr_sync_memmodel (insn);
12888 switch (memmodel_attr)
12891 model = MEMMODEL_ACQ_REL;
12894 model = MEMMODEL_ACQUIRE;
12897 model = (enum memmodel) INTVAL (operands[memmodel_attr]);
12900 mips_multi_start ();
12902 /* Output the release side of the memory barrier. */
12903 if (need_atomic_barrier_p (model, true))
12905 if (required_oldval == 0 && TARGET_OCTEON)
12907 /* Octeon doesn't reorder reads, so a full barrier can be
12908 created by using SYNCW to order writes combined with the
12909 write from the following SC. When the SC successfully
12910 completes, we know that all preceding writes are also
12911 committed to the coherent memory system. It is possible
12912 for a single SYNCW to fail, but a pair of them will never
12913 fail, so we use two. */
12914 mips_multi_add_insn ("syncw", NULL);
12915 mips_multi_add_insn ("syncw", NULL);
12918 mips_multi_add_insn ("sync", NULL);
12921 /* Output the branch-back label. */
12922 mips_multi_add_label ("1:");
12924 /* OLDVAL = *MEM. */
12925 mips_multi_add_insn (is_64bit_p ? "lld\t%0,%1" : "ll\t%0,%1",
12926 oldval, mem, NULL);
12928 /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */
12929 if (required_oldval)
12931 if (inclusive_mask == 0)
12935 gcc_assert (oldval != at);
12936 mips_multi_add_insn ("and\t%0,%1,%2",
12937 at, oldval, inclusive_mask, NULL);
12940 mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1, required_oldval, NULL);
12942 /* CMP = 0 [delay slot]. */
12944 mips_multi_add_insn ("li\t%0,0", cmp, NULL);
12947 /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */
12948 if (exclusive_mask == 0)
12952 gcc_assert (oldval != at);
12953 mips_multi_add_insn ("and\t%0,%1,%z2",
12954 at, oldval, exclusive_mask, NULL);
12958 /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2).
12960 We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit
12961 at least one instruction in that case. */
12962 if (insn1 == SYNC_INSN1_MOVE
12963 && (tmp1 != const0_rtx || insn2 != SYNC_INSN2_NOP))
12967 mips_multi_add_insn (mips_sync_insn1_template (insn1, is_64bit_p),
12968 newval, oldval, insn1_op2, NULL);
12972 /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */
12973 if (insn2 == SYNC_INSN2_NOP)
12977 mips_multi_add_insn (mips_sync_insn2_template (insn2),
12978 newval, tmp2, inclusive_mask, NULL);
12981 tmp3_insn = mips_multi_last_index ();
12983 /* $AT = $TMP1 | $TMP3. */
12984 if (tmp1 == const0_rtx || tmp3 == const0_rtx)
12986 mips_multi_set_operand (tmp3_insn, 0, at);
12991 gcc_assert (tmp1 != tmp3);
12992 mips_multi_add_insn ("or\t%0,%1,%2", at, tmp1, tmp3, NULL);
12995 /* if (!commit (*MEM = $AT)) goto 1.
12997 This will sometimes be a delayed branch; see the write code below
12999 mips_multi_add_insn (is_64bit_p ? "scd\t%0,%1" : "sc\t%0,%1", at, mem, NULL);
13000 mips_multi_add_insn ("beq%?\t%0,%.,1b", at, NULL);
13002 /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */
13003 if (insn1 != SYNC_INSN1_MOVE && insn1 != SYNC_INSN1_LI && tmp3 != newval)
13005 mips_multi_copy_insn (tmp3_insn);
13006 mips_multi_set_operand (mips_multi_last_index (), 0, newval);
13008 else if (!(required_oldval && cmp))
13009 mips_multi_add_insn ("nop", NULL);
13011 /* CMP = 1 -- either standalone or in a delay slot. */
13012 if (required_oldval && cmp)
13013 mips_multi_add_insn ("li\t%0,1", cmp, NULL);
13015 /* Output the acquire side of the memory barrier. */
13016 if (TARGET_SYNC_AFTER_SC && need_atomic_barrier_p (model, false))
13017 mips_multi_add_insn ("sync", NULL);
13019 /* Output the exit label, if needed. */
13020 if (required_oldval)
13021 mips_multi_add_label ("2:");
13023 #undef READ_OPERAND
13026 /* Output and/or return the asm template for sync loop INSN, which has
13027 the operands given by OPERANDS. */
13030 mips_output_sync_loop (rtx_insn *insn, rtx *operands)
13032 mips_process_sync_loop (insn, operands);
13034 /* Use branch-likely instructions to work around the LL/SC R10000
13036 mips_branch_likely = TARGET_FIX_R10000;
13038 mips_push_asm_switch (&mips_noreorder);
13039 mips_push_asm_switch (&mips_nomacro);
13040 mips_push_asm_switch (&mips_noat);
13041 mips_start_ll_sc_sync_block ();
13043 mips_multi_write ();
13045 mips_end_ll_sc_sync_block ();
13046 mips_pop_asm_switch (&mips_noat);
13047 mips_pop_asm_switch (&mips_nomacro);
13048 mips_pop_asm_switch (&mips_noreorder);
13053 /* Return the number of individual instructions in sync loop INSN,
13054 which has the operands given by OPERANDS. */
13057 mips_sync_loop_insns (rtx_insn *insn, rtx *operands)
13059 mips_process_sync_loop (insn, operands);
13060 return mips_multi_num_insns;
13063 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
13064 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
13066 When working around R4000 and R4400 errata, we need to make sure that
13067 the division is not immediately followed by a shift[1][2]. We also
13068 need to stop the division from being put into a branch delay slot[3].
13069 The easiest way to avoid both problems is to add a nop after the
13070 division. When a divide-by-zero check is needed, this nop can be
13071 used to fill the branch delay slot.
13073 [1] If a double-word or a variable shift executes immediately
13074 after starting an integer division, the shift may give an
13075 incorrect result. See quotations of errata #16 and #28 from
13076 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
13077 in mips.md for details.
13079 [2] A similar bug to [1] exists for all revisions of the
13080 R4000 and the R4400 when run in an MC configuration.
13081 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
13083 "19. In this following sequence:
13085 ddiv (or ddivu or div or divu)
13086 dsll32 (or dsrl32, dsra32)
13088 if an MPT stall occurs, while the divide is slipping the cpu
13089 pipeline, then the following double shift would end up with an
13092 Workaround: The compiler needs to avoid generating any
13093 sequence with divide followed by extended double shift."
13095 This erratum is also present in "MIPS R4400MC Errata, Processor
13096 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
13097 & 3.0" as errata #10 and #4, respectively.
13099 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
13100 (also valid for MIPS R4000MC processors):
13102 "52. R4000SC: This bug does not apply for the R4000PC.
13104 There are two flavors of this bug:
13106 1) If the instruction just after divide takes an RF exception
13107 (tlb-refill, tlb-invalid) and gets an instruction cache
13108 miss (both primary and secondary) and the line which is
13109 currently in secondary cache at this index had the first
13110 data word, where the bits 5..2 are set, then R4000 would
13111 get a wrong result for the div.
13116 ------------------- # end-of page. -tlb-refill
13121 ------------------- # end-of page. -tlb-invalid
13124 2) If the divide is in the taken branch delay slot, where the
13125 target takes RF exception and gets an I-cache miss for the
13126 exception vector or where I-cache miss occurs for the
13127 target address, under the above mentioned scenarios, the
13128 div would get wrong results.
13131 j r2 # to next page mapped or unmapped
13132 div r8,r9 # this bug would be there as long
13133 # as there is an ICache miss and
13134 nop # the "data pattern" is present
13137 beq r0, r0, NextPage # to Next page
13141 This bug is present for div, divu, ddiv, and ddivu
13144 Workaround: For item 1), OS could make sure that the next page
13145 after the divide instruction is also mapped. For item 2), the
13146 compiler could make sure that the divide instruction is not in
13147 the branch delay slot."
13149 These processors have PRId values of 0x00004220 and 0x00004300 for
13150 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
13153 mips_output_division (const char *division, rtx *operands)
13158 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
13160 output_asm_insn (s, operands);
13163 if (TARGET_CHECK_ZERO_DIV)
13167 output_asm_insn (s, operands);
13168 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
13170 else if (GENERATE_DIVIDE_TRAPS)
13172 /* Avoid long replay penalty on load miss by putting the trap before
13175 output_asm_insn ("teq\t%2,%.,7", operands);
13178 output_asm_insn (s, operands);
13179 s = "teq\t%2,%.,7";
13184 output_asm_insn ("%(bne\t%2,%.,1f", operands);
13185 output_asm_insn (s, operands);
13186 s = "break\t7%)\n1:";
13192 /* Return true if destination of IN_INSN is used as add source in
13193 OUT_INSN. Both IN_INSN and OUT_INSN are of type fmadd. Example:
13194 madd.s dst, x, y, z
13195 madd.s a, dst, b, c */
13198 mips_fmadd_bypass (rtx_insn *out_insn, rtx_insn *in_insn)
13200 int dst_reg, src_reg;
13202 gcc_assert (get_attr_type (in_insn) == TYPE_FMADD);
13203 gcc_assert (get_attr_type (out_insn) == TYPE_FMADD);
13205 extract_insn (in_insn);
13206 dst_reg = REG_P (recog_data.operand[0]);
13208 extract_insn (out_insn);
13209 src_reg = REG_P (recog_data.operand[1]);
13211 if (dst_reg == src_reg)
13217 /* Return true if IN_INSN is a multiply-add or multiply-subtract
13218 instruction and if OUT_INSN assigns to the accumulator operand. */
13221 mips_linked_madd_p (rtx_insn *out_insn, rtx_insn *in_insn)
13223 enum attr_accum_in accum_in;
13224 int accum_in_opnum;
13227 if (recog_memoized (in_insn) < 0)
13230 accum_in = get_attr_accum_in (in_insn);
13231 if (accum_in == ACCUM_IN_NONE)
13234 accum_in_opnum = accum_in - ACCUM_IN_0;
13236 extract_insn (in_insn);
13237 gcc_assert (accum_in_opnum < recog_data.n_operands);
13238 accum_in_op = recog_data.operand[accum_in_opnum];
13240 return reg_set_p (accum_in_op, out_insn);
13243 /* True if the dependency between OUT_INSN and IN_INSN is on the store
13244 data rather than the address. We need this because the cprestore
13245 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
13246 which causes the default routine to abort. We just return false
13250 mips_store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
13252 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
13255 return !store_data_bypass_p (out_insn, in_insn);
13259 /* Variables and flags used in scheduler hooks when tuning for
13263 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
13266 /* If true, then next ALU1/2 instruction will go to ALU1. */
13269 /* If true, then next FALU1/2 unstruction will go to FALU1. */
13272 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
13273 int alu1_core_unit_code;
13274 int alu2_core_unit_code;
13275 int falu1_core_unit_code;
13276 int falu2_core_unit_code;
13278 /* True if current cycle has a multi instruction.
13279 This flag is used in mips_ls2_dfa_post_advance_cycle. */
13280 bool cycle_has_multi_p;
13282 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
13283 These are used in mips_ls2_dfa_post_advance_cycle to initialize
13285 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
13286 instruction to go ALU1. */
13287 rtx_insn *alu1_turn_enabled_insn;
13288 rtx_insn *alu2_turn_enabled_insn;
13289 rtx_insn *falu1_turn_enabled_insn;
13290 rtx_insn *falu2_turn_enabled_insn;
13293 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
13294 dependencies have no cost, except on the 20Kc where output-dependence
13295 is treated like input-dependence. */
13298 mips_adjust_cost (rtx_insn *insn ATTRIBUTE_UNUSED, rtx link,
13299 rtx_insn *dep ATTRIBUTE_UNUSED, int cost)
13301 if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT
13304 if (REG_NOTE_KIND (link) != 0)
13309 /* Return the number of instructions that can be issued per cycle. */
13312 mips_issue_rate (void)
13316 case PROCESSOR_74KC:
13317 case PROCESSOR_74KF2_1:
13318 case PROCESSOR_74KF1_1:
13319 case PROCESSOR_74KF3_2:
13320 /* The 74k is not strictly quad-issue cpu, but can be seen as one
13321 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
13322 but in reality only a maximum of 3 insns can be issued as
13323 floating-point loads and stores also require a slot in the
13325 case PROCESSOR_R10000:
13326 /* All R10K Processors are quad-issue (being the first MIPS
13327 processors to support this feature). */
13330 case PROCESSOR_20KC:
13331 case PROCESSOR_R4130:
13332 case PROCESSOR_R5400:
13333 case PROCESSOR_R5500:
13334 case PROCESSOR_R5900:
13335 case PROCESSOR_R7000:
13336 case PROCESSOR_R9000:
13337 case PROCESSOR_OCTEON:
13338 case PROCESSOR_OCTEON2:
13339 case PROCESSOR_OCTEON3:
13342 case PROCESSOR_SB1:
13343 case PROCESSOR_SB1A:
13344 /* This is actually 4, but we get better performance if we claim 3.
13345 This is partly because of unwanted speculative code motion with the
13346 larger number, and partly because in most common cases we can't
13347 reach the theoretical max of 4. */
13350 case PROCESSOR_LOONGSON_2E:
13351 case PROCESSOR_LOONGSON_2F:
13352 case PROCESSOR_LOONGSON_3A:
13353 case PROCESSOR_P5600:
13356 case PROCESSOR_XLP:
13357 return (reload_completed ? 4 : 3);
13364 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
13367 mips_ls2_init_dfa_post_cycle_insn (void)
13370 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
13371 mips_ls2.alu1_turn_enabled_insn = get_insns ();
13375 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
13376 mips_ls2.alu2_turn_enabled_insn = get_insns ();
13380 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
13381 mips_ls2.falu1_turn_enabled_insn = get_insns ();
13385 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
13386 mips_ls2.falu2_turn_enabled_insn = get_insns ();
13389 mips_ls2.alu1_core_unit_code = get_cpu_unit_code ("ls2_alu1_core");
13390 mips_ls2.alu2_core_unit_code = get_cpu_unit_code ("ls2_alu2_core");
13391 mips_ls2.falu1_core_unit_code = get_cpu_unit_code ("ls2_falu1_core");
13392 mips_ls2.falu2_core_unit_code = get_cpu_unit_code ("ls2_falu2_core");
13395 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
13396 Init data used in mips_dfa_post_advance_cycle. */
13399 mips_init_dfa_post_cycle_insn (void)
13401 if (TUNE_LOONGSON_2EF)
13402 mips_ls2_init_dfa_post_cycle_insn ();
13405 /* Initialize STATE when scheduling for Loongson 2E/2F.
13406 Support round-robin dispatch scheme by enabling only one of
13407 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
13411 mips_ls2_dfa_post_advance_cycle (state_t state)
13413 if (cpu_unit_reservation_p (state, mips_ls2.alu1_core_unit_code))
13415 /* Though there are no non-pipelined ALU1 insns,
13416 we can get an instruction of type 'multi' before reload. */
13417 gcc_assert (mips_ls2.cycle_has_multi_p);
13418 mips_ls2.alu1_turn_p = false;
13421 mips_ls2.cycle_has_multi_p = false;
13423 if (cpu_unit_reservation_p (state, mips_ls2.alu2_core_unit_code))
13424 /* We have a non-pipelined alu instruction in the core,
13425 adjust round-robin counter. */
13426 mips_ls2.alu1_turn_p = true;
13428 if (mips_ls2.alu1_turn_p)
13430 if (state_transition (state, mips_ls2.alu1_turn_enabled_insn) >= 0)
13431 gcc_unreachable ();
13435 if (state_transition (state, mips_ls2.alu2_turn_enabled_insn) >= 0)
13436 gcc_unreachable ();
13439 if (cpu_unit_reservation_p (state, mips_ls2.falu1_core_unit_code))
13441 /* There are no non-pipelined FALU1 insns. */
13442 gcc_unreachable ();
13443 mips_ls2.falu1_turn_p = false;
13446 if (cpu_unit_reservation_p (state, mips_ls2.falu2_core_unit_code))
13447 /* We have a non-pipelined falu instruction in the core,
13448 adjust round-robin counter. */
13449 mips_ls2.falu1_turn_p = true;
13451 if (mips_ls2.falu1_turn_p)
13453 if (state_transition (state, mips_ls2.falu1_turn_enabled_insn) >= 0)
13454 gcc_unreachable ();
13458 if (state_transition (state, mips_ls2.falu2_turn_enabled_insn) >= 0)
13459 gcc_unreachable ();
13463 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
13464 This hook is being called at the start of each cycle. */
13467 mips_dfa_post_advance_cycle (void)
13469 if (TUNE_LOONGSON_2EF)
13470 mips_ls2_dfa_post_advance_cycle (curr_state);
13473 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
13474 be as wide as the scheduling freedom in the DFA. */
13477 mips_multipass_dfa_lookahead (void)
13479 /* Can schedule up to 4 of the 6 function units in any one cycle. */
13483 if (TUNE_LOONGSON_2EF || TUNE_LOONGSON_3A)
13495 /* Remove the instruction at index LOWER from ready queue READY and
13496 reinsert it in front of the instruction at index HIGHER. LOWER must
13500 mips_promote_ready (rtx_insn **ready, int lower, int higher)
13502 rtx_insn *new_head;
13505 new_head = ready[lower];
13506 for (i = lower; i < higher; i++)
13507 ready[i] = ready[i + 1];
13508 ready[i] = new_head;
13511 /* If the priority of the instruction at POS2 in the ready queue READY
13512 is within LIMIT units of that of the instruction at POS1, swap the
13513 instructions if POS2 is not already less than POS1. */
13516 mips_maybe_swap_ready (rtx_insn **ready, int pos1, int pos2, int limit)
13519 && INSN_PRIORITY (ready[pos1]) + limit >= INSN_PRIORITY (ready[pos2]))
13523 temp = ready[pos1];
13524 ready[pos1] = ready[pos2];
13525 ready[pos2] = temp;
13529 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
13530 that may clobber hi or lo. */
13531 static rtx_insn *mips_macc_chains_last_hilo;
13533 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
13534 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
13537 mips_macc_chains_record (rtx_insn *insn)
13539 if (get_attr_may_clobber_hilo (insn))
13540 mips_macc_chains_last_hilo = insn;
13543 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
13544 has NREADY elements, looking for a multiply-add or multiply-subtract
13545 instruction that is cumulative with mips_macc_chains_last_hilo.
13546 If there is one, promote it ahead of anything else that might
13547 clobber hi or lo. */
13550 mips_macc_chains_reorder (rtx_insn **ready, int nready)
13554 if (mips_macc_chains_last_hilo != 0)
13555 for (i = nready - 1; i >= 0; i--)
13556 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
13558 for (j = nready - 1; j > i; j--)
13559 if (recog_memoized (ready[j]) >= 0
13560 && get_attr_may_clobber_hilo (ready[j]))
13562 mips_promote_ready (ready, i, j);
13569 /* The last instruction to be scheduled. */
13570 static rtx_insn *vr4130_last_insn;
13572 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
13573 points to an rtx that is initially an instruction. Nullify the rtx
13574 if the instruction uses the value of register X. */
13577 vr4130_true_reg_dependence_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
13582 insn_ptr = (rtx *) data;
13585 && reg_referenced_p (x, PATTERN (*insn_ptr)))
13589 /* Return true if there is true register dependence between vr4130_last_insn
13593 vr4130_true_reg_dependence_p (rtx insn)
13595 note_stores (PATTERN (vr4130_last_insn),
13596 vr4130_true_reg_dependence_p_1, &insn);
13600 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
13601 the ready queue and that INSN2 is the instruction after it, return
13602 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
13603 in which INSN1 and INSN2 can probably issue in parallel, but for
13604 which (INSN2, INSN1) should be less sensitive to instruction
13605 alignment than (INSN1, INSN2). See 4130.md for more details. */
13608 vr4130_swap_insns_p (rtx_insn *insn1, rtx_insn *insn2)
13610 sd_iterator_def sd_it;
13613 /* Check for the following case:
13615 1) there is some other instruction X with an anti dependence on INSN1;
13616 2) X has a higher priority than INSN2; and
13617 3) X is an arithmetic instruction (and thus has no unit restrictions).
13619 If INSN1 is the last instruction blocking X, it would better to
13620 choose (INSN1, X) over (INSN2, INSN1). */
13621 FOR_EACH_DEP (insn1, SD_LIST_FORW, sd_it, dep)
13622 if (DEP_TYPE (dep) == REG_DEP_ANTI
13623 && INSN_PRIORITY (DEP_CON (dep)) > INSN_PRIORITY (insn2)
13624 && recog_memoized (DEP_CON (dep)) >= 0
13625 && get_attr_vr4130_class (DEP_CON (dep)) == VR4130_CLASS_ALU)
13628 if (vr4130_last_insn != 0
13629 && recog_memoized (insn1) >= 0
13630 && recog_memoized (insn2) >= 0)
13632 /* See whether INSN1 and INSN2 use different execution units,
13633 or if they are both ALU-type instructions. If so, they can
13634 probably execute in parallel. */
13635 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
13636 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
13637 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
13639 /* If only one of the instructions has a dependence on
13640 vr4130_last_insn, prefer to schedule the other one first. */
13641 bool dep1_p = vr4130_true_reg_dependence_p (insn1);
13642 bool dep2_p = vr4130_true_reg_dependence_p (insn2);
13643 if (dep1_p != dep2_p)
13646 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
13647 is not an ALU-type instruction and if INSN1 uses the same
13648 execution unit. (Note that if this condition holds, we already
13649 know that INSN2 uses a different execution unit.) */
13650 if (class1 != VR4130_CLASS_ALU
13651 && recog_memoized (vr4130_last_insn) >= 0
13652 && class1 == get_attr_vr4130_class (vr4130_last_insn))
13659 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
13660 queue with at least two instructions. Swap the first two if
13661 vr4130_swap_insns_p says that it could be worthwhile. */
13664 vr4130_reorder (rtx_insn **ready, int nready)
13666 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
13667 mips_promote_ready (ready, nready - 2, nready - 1);
13670 /* Record whether last 74k AGEN instruction was a load or store. */
13671 static enum attr_type mips_last_74k_agen_insn = TYPE_UNKNOWN;
13673 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
13674 resets to TYPE_UNKNOWN state. */
13677 mips_74k_agen_init (rtx_insn *insn)
13679 if (!insn || CALL_P (insn) || JUMP_P (insn))
13680 mips_last_74k_agen_insn = TYPE_UNKNOWN;
13683 enum attr_type type = get_attr_type (insn);
13684 if (type == TYPE_LOAD || type == TYPE_STORE)
13685 mips_last_74k_agen_insn = type;
13689 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
13690 loads to be grouped together, and multiple stores to be grouped
13691 together. Swap things around in the ready queue to make this happen. */
13694 mips_74k_agen_reorder (rtx_insn **ready, int nready)
13697 int store_pos, load_pos;
13702 for (i = nready - 1; i >= 0; i--)
13704 rtx_insn *insn = ready[i];
13705 if (USEFUL_INSN_P (insn))
13706 switch (get_attr_type (insn))
13709 if (store_pos == -1)
13714 if (load_pos == -1)
13723 if (load_pos == -1 || store_pos == -1)
13726 switch (mips_last_74k_agen_insn)
13729 /* Prefer to schedule loads since they have a higher latency. */
13731 /* Swap loads to the front of the queue. */
13732 mips_maybe_swap_ready (ready, load_pos, store_pos, 4);
13735 /* Swap stores to the front of the queue. */
13736 mips_maybe_swap_ready (ready, store_pos, load_pos, 4);
13743 /* Implement TARGET_SCHED_INIT. */
13746 mips_sched_init (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13747 int max_ready ATTRIBUTE_UNUSED)
13749 mips_macc_chains_last_hilo = 0;
13750 vr4130_last_insn = 0;
13751 mips_74k_agen_init (NULL);
13753 /* When scheduling for Loongson2, branch instructions go to ALU1,
13754 therefore basic block is most likely to start with round-robin counter
13755 pointed to ALU2. */
13756 mips_ls2.alu1_turn_p = false;
13757 mips_ls2.falu1_turn_p = true;
13760 /* Subroutine used by TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
13763 mips_sched_reorder_1 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13764 rtx_insn **ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
13766 if (!reload_completed
13767 && TUNE_MACC_CHAINS
13769 mips_macc_chains_reorder (ready, *nreadyp);
13771 if (reload_completed
13773 && !TARGET_VR4130_ALIGN
13775 vr4130_reorder (ready, *nreadyp);
13778 mips_74k_agen_reorder (ready, *nreadyp);
13781 /* Implement TARGET_SCHED_REORDER. */
13784 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13785 rtx_insn **ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
13787 mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle);
13788 return mips_issue_rate ();
13791 /* Implement TARGET_SCHED_REORDER2. */
13794 mips_sched_reorder2 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13795 rtx_insn **ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
13797 mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle);
13798 return cached_can_issue_more;
13801 /* Update round-robin counters for ALU1/2 and FALU1/2. */
13804 mips_ls2_variable_issue (rtx_insn *insn)
13806 if (mips_ls2.alu1_turn_p)
13808 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu1_core_unit_code))
13809 mips_ls2.alu1_turn_p = false;
13813 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu2_core_unit_code))
13814 mips_ls2.alu1_turn_p = true;
13817 if (mips_ls2.falu1_turn_p)
13819 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu1_core_unit_code))
13820 mips_ls2.falu1_turn_p = false;
13824 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu2_core_unit_code))
13825 mips_ls2.falu1_turn_p = true;
13828 if (recog_memoized (insn) >= 0)
13829 mips_ls2.cycle_has_multi_p |= (get_attr_type (insn) == TYPE_MULTI);
13832 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
13835 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13836 rtx_insn *insn, int more)
13838 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
13839 if (USEFUL_INSN_P (insn))
13841 if (get_attr_type (insn) != TYPE_GHOST)
13843 if (!reload_completed && TUNE_MACC_CHAINS)
13844 mips_macc_chains_record (insn);
13845 vr4130_last_insn = insn;
13847 mips_74k_agen_init (insn);
13848 else if (TUNE_LOONGSON_2EF)
13849 mips_ls2_variable_issue (insn);
13852 /* Instructions of type 'multi' should all be split before
13853 the second scheduling pass. */
13854 gcc_assert (!reload_completed
13855 || recog_memoized (insn) < 0
13856 || get_attr_type (insn) != TYPE_MULTI);
13858 cached_can_issue_more = more;
13862 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
13863 return the first operand of the associated PREF or PREFX insn. */
13866 mips_prefetch_cookie (rtx write, rtx locality)
13868 /* store_streamed / load_streamed. */
13869 if (INTVAL (locality) <= 0)
13870 return GEN_INT (INTVAL (write) + 4);
13872 /* store / load. */
13873 if (INTVAL (locality) <= 2)
13876 /* store_retained / load_retained. */
13877 return GEN_INT (INTVAL (write) + 6);
13880 /* Flags that indicate when a built-in function is available.
13882 BUILTIN_AVAIL_NON_MIPS16
13883 The function is available on the current target if !TARGET_MIPS16.
13885 BUILTIN_AVAIL_MIPS16
13886 The function is available on the current target if TARGET_MIPS16. */
13887 #define BUILTIN_AVAIL_NON_MIPS16 1
13888 #define BUILTIN_AVAIL_MIPS16 2
13890 /* Declare an availability predicate for built-in functions that
13891 require non-MIPS16 mode and also require COND to be true.
13892 NAME is the main part of the predicate's name. */
13893 #define AVAIL_NON_MIPS16(NAME, COND) \
13894 static unsigned int \
13895 mips_builtin_avail_##NAME (void) \
13897 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
13900 /* Declare an availability predicate for built-in functions that
13901 support both MIPS16 and non-MIPS16 code and also require COND
13902 to be true. NAME is the main part of the predicate's name. */
13903 #define AVAIL_ALL(NAME, COND) \
13904 static unsigned int \
13905 mips_builtin_avail_##NAME (void) \
13907 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 | BUILTIN_AVAIL_MIPS16 : 0; \
13910 /* This structure describes a single built-in function. */
13911 struct mips_builtin_description {
13912 /* The code of the main .md file instruction. See mips_builtin_type
13913 for more information. */
13914 enum insn_code icode;
13916 /* The floating-point comparison code to use with ICODE, if any. */
13917 enum mips_fp_condition cond;
13919 /* The name of the built-in function. */
13922 /* Specifies how the function should be expanded. */
13923 enum mips_builtin_type builtin_type;
13925 /* The function's prototype. */
13926 enum mips_function_type function_type;
13928 /* Whether the function is available. */
13929 unsigned int (*avail) (void);
13932 AVAIL_ALL (hard_float, TARGET_HARD_FLOAT_ABI)
13933 AVAIL_NON_MIPS16 (paired_single, TARGET_PAIRED_SINGLE_FLOAT)
13934 AVAIL_NON_MIPS16 (sb1_paired_single, TARGET_SB1 && TARGET_PAIRED_SINGLE_FLOAT)
13935 AVAIL_NON_MIPS16 (mips3d, TARGET_MIPS3D)
13936 AVAIL_NON_MIPS16 (dsp, TARGET_DSP)
13937 AVAIL_NON_MIPS16 (dspr2, TARGET_DSPR2)
13938 AVAIL_NON_MIPS16 (dsp_32, !TARGET_64BIT && TARGET_DSP)
13939 AVAIL_NON_MIPS16 (dsp_64, TARGET_64BIT && TARGET_DSP)
13940 AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2)
13941 AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS)
13942 AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
13944 /* Construct a mips_builtin_description from the given arguments.
13946 INSN is the name of the associated instruction pattern, without the
13947 leading CODE_FOR_mips_.
13949 CODE is the floating-point condition code associated with the
13950 function. It can be 'f' if the field is not applicable.
13952 NAME is the name of the function itself, without the leading
13955 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
13957 AVAIL is the name of the availability predicate, without the leading
13958 mips_builtin_avail_. */
13959 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
13960 FUNCTION_TYPE, AVAIL) \
13961 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
13962 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
13963 mips_builtin_avail_ ## AVAIL }
13965 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
13966 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
13967 are as for MIPS_BUILTIN. */
13968 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
13969 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
13971 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
13972 are subject to mips_builtin_avail_<AVAIL>. */
13973 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
13974 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
13975 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
13976 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
13977 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
13979 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
13980 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
13981 while the any and all forms are subject to mips_builtin_avail_mips3d. */
13982 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
13983 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
13984 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
13986 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
13987 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
13989 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
13990 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
13992 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
13993 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
13996 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
13997 are subject to mips_builtin_avail_mips3d. */
13998 #define CMP_4S_BUILTINS(INSN, COND) \
13999 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
14000 MIPS_BUILTIN_CMP_ANY, \
14001 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
14002 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
14003 MIPS_BUILTIN_CMP_ALL, \
14004 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
14006 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
14007 instruction requires mips_builtin_avail_<AVAIL>. */
14008 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
14009 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
14010 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
14012 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
14013 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
14016 /* Define all the built-in functions related to C.cond.fmt condition COND. */
14017 #define CMP_BUILTINS(COND) \
14018 MOVTF_BUILTINS (c, COND, paired_single), \
14019 MOVTF_BUILTINS (cabs, COND, mips3d), \
14020 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
14021 CMP_PS_BUILTINS (c, COND, paired_single), \
14022 CMP_PS_BUILTINS (cabs, COND, mips3d), \
14023 CMP_4S_BUILTINS (c, COND), \
14024 CMP_4S_BUILTINS (cabs, COND)
14026 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
14027 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
14028 and AVAIL are as for MIPS_BUILTIN. */
14029 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
14030 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
14031 FUNCTION_TYPE, AVAIL)
14033 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
14034 branch instruction. AVAIL is as for MIPS_BUILTIN. */
14035 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
14036 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
14037 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
14039 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
14040 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
14041 builtin_description field. */
14042 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
14043 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
14044 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
14045 FUNCTION_TYPE, mips_builtin_avail_loongson }
14047 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
14048 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
14049 builtin_description field. */
14050 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
14051 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
14053 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
14054 We use functions of this form when the same insn can be usefully applied
14055 to more than one datatype. */
14056 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
14057 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
14059 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
14060 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
14061 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
14062 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
14063 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
14064 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
14065 #define CODE_FOR_mips_mult CODE_FOR_mulsidi3_32bit
14066 #define CODE_FOR_mips_multu CODE_FOR_umulsidi3_32bit
14068 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
14069 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
14070 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
14071 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
14072 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
14073 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
14074 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
14075 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
14076 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
14077 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
14078 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
14079 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
14080 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
14081 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
14082 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
14083 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
14084 #define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3
14085 #define CODE_FOR_loongson_psllh CODE_FOR_ashlv4hi3
14086 #define CODE_FOR_loongson_psllw CODE_FOR_ashlv2si3
14087 #define CODE_FOR_loongson_psrlh CODE_FOR_lshrv4hi3
14088 #define CODE_FOR_loongson_psrlw CODE_FOR_lshrv2si3
14089 #define CODE_FOR_loongson_psrah CODE_FOR_ashrv4hi3
14090 #define CODE_FOR_loongson_psraw CODE_FOR_ashrv2si3
14091 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
14092 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
14093 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
14094 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
14095 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
14096 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
14097 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
14099 static const struct mips_builtin_description mips_builtins[] = {
14100 #define MIPS_GET_FCSR 0
14101 DIRECT_BUILTIN (get_fcsr, MIPS_USI_FTYPE_VOID, hard_float),
14102 #define MIPS_SET_FCSR 1
14103 DIRECT_NO_TARGET_BUILTIN (set_fcsr, MIPS_VOID_FTYPE_USI, hard_float),
14105 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
14106 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
14107 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
14108 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
14109 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, paired_single),
14110 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, paired_single),
14111 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, paired_single),
14112 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, paired_single),
14114 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT, paired_single),
14115 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
14116 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
14117 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
14118 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, mips3d),
14120 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, mips3d),
14121 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, mips3d),
14122 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
14123 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
14124 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
14125 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
14127 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, mips3d),
14128 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, mips3d),
14129 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
14130 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
14131 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
14132 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
14134 MIPS_FP_CONDITIONS (CMP_BUILTINS),
14136 /* Built-in functions for the SB-1 processor. */
14137 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, sb1_paired_single),
14139 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
14140 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
14141 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
14142 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
14143 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
14144 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
14145 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
14146 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
14147 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
14148 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
14149 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
14150 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, dsp),
14151 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, dsp),
14152 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, dsp),
14153 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, dsp),
14154 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, dsp),
14155 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, dsp),
14156 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
14157 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
14158 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
14159 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
14160 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, dsp),
14161 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, dsp),
14162 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
14163 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
14164 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
14165 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
14166 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
14167 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
14168 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
14169 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
14170 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
14171 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
14172 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
14173 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
14174 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
14175 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
14176 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
14177 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, dsp),
14178 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
14179 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
14180 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
14181 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
14182 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
14183 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, dsp),
14184 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, dsp),
14185 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, dsp),
14186 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, dsp),
14187 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
14188 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
14189 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
14190 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
14191 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
14192 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
14193 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
14194 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
14195 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
14196 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
14197 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
14198 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
14199 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, dsp),
14200 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, dsp),
14201 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_POINTER_SI, dsp),
14202 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_POINTER_SI, dsp),
14203 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_POINTER_SI, dsp),
14204 BPOSGE_BUILTIN (32, dsp),
14206 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
14207 DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, dspr2),
14208 DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14209 DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14210 DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
14211 DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
14212 DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
14213 DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
14214 DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
14215 DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
14216 DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
14217 DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14218 DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14219 DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, dspr2),
14220 DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14221 DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, dspr2),
14222 DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dspr2),
14223 DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
14224 DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
14225 DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
14226 DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
14227 DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
14228 DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, dspr2),
14229 DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14230 DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14231 DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
14232 DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
14233 DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14234 DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14235 DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
14236 DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
14237 DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14238 DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14239 DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
14240 DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
14242 /* Built-in functions for the DSP ASE (32-bit only). */
14243 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
14244 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
14245 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
14246 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
14247 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
14248 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
14249 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
14250 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
14251 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
14252 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
14253 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
14254 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
14255 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
14256 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
14257 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
14258 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
14259 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, dsp_32),
14260 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, dsp_32),
14261 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, dsp_32),
14262 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, dsp_32),
14263 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, dsp_32),
14264 DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
14265 DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32),
14266 DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
14267 DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32),
14268 DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, dsp_32),
14269 DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, dsp_32),
14271 /* Built-in functions for the DSP ASE (64-bit only). */
14272 DIRECT_BUILTIN (ldx, MIPS_DI_FTYPE_POINTER_SI, dsp_64),
14274 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
14275 DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14276 DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14277 DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14278 DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14279 DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14280 DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14281 DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14282 DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14283 DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14285 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
14286 LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI),
14287 LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI),
14288 LOONGSON_BUILTIN (packushb, MIPS_UV8QI_FTYPE_UV4HI_UV4HI),
14289 LOONGSON_BUILTIN_SUFFIX (paddw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14290 LOONGSON_BUILTIN_SUFFIX (paddh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14291 LOONGSON_BUILTIN_SUFFIX (paddb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14292 LOONGSON_BUILTIN_SUFFIX (paddw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14293 LOONGSON_BUILTIN_SUFFIX (paddh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14294 LOONGSON_BUILTIN_SUFFIX (paddb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14295 LOONGSON_BUILTIN_SUFFIX (paddd, u, MIPS_UDI_FTYPE_UDI_UDI),
14296 LOONGSON_BUILTIN_SUFFIX (paddd, s, MIPS_DI_FTYPE_DI_DI),
14297 LOONGSON_BUILTIN (paddsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14298 LOONGSON_BUILTIN (paddsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
14299 LOONGSON_BUILTIN (paddush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14300 LOONGSON_BUILTIN (paddusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14301 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_ud, MIPS_UDI_FTYPE_UDI_UDI),
14302 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_uw, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14303 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_uh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14304 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_ub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14305 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_sd, MIPS_DI_FTYPE_DI_DI),
14306 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_sw, MIPS_V2SI_FTYPE_V2SI_V2SI),
14307 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_sh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14308 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_sb, MIPS_V8QI_FTYPE_V8QI_V8QI),
14309 LOONGSON_BUILTIN (pavgh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14310 LOONGSON_BUILTIN (pavgb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14311 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14312 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14313 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14314 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14315 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14316 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14317 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14318 LOONGSON_BUILTIN_SUFFIX (pcmpgth, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14319 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14320 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14321 LOONGSON_BUILTIN_SUFFIX (pcmpgth, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14322 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14323 LOONGSON_BUILTIN_SUFFIX (pextrh, u, MIPS_UV4HI_FTYPE_UV4HI_USI),
14324 LOONGSON_BUILTIN_SUFFIX (pextrh, s, MIPS_V4HI_FTYPE_V4HI_USI),
14325 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14326 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14327 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14328 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14329 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14330 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14331 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14332 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14333 LOONGSON_BUILTIN (pmaddhw, MIPS_V2SI_FTYPE_V4HI_V4HI),
14334 LOONGSON_BUILTIN (pmaxsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14335 LOONGSON_BUILTIN (pmaxub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14336 LOONGSON_BUILTIN (pminsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14337 LOONGSON_BUILTIN (pminub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14338 LOONGSON_BUILTIN_SUFFIX (pmovmskb, u, MIPS_UV8QI_FTYPE_UV8QI),
14339 LOONGSON_BUILTIN_SUFFIX (pmovmskb, s, MIPS_V8QI_FTYPE_V8QI),
14340 LOONGSON_BUILTIN (pmulhuh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14341 LOONGSON_BUILTIN (pmulhh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14342 LOONGSON_BUILTIN (pmullh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14343 LOONGSON_BUILTIN (pmuluw, MIPS_UDI_FTYPE_UV2SI_UV2SI),
14344 LOONGSON_BUILTIN (pasubub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14345 LOONGSON_BUILTIN (biadd, MIPS_UV4HI_FTYPE_UV8QI),
14346 LOONGSON_BUILTIN (psadbh, MIPS_UV4HI_FTYPE_UV8QI_UV8QI),
14347 LOONGSON_BUILTIN_SUFFIX (pshufh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
14348 LOONGSON_BUILTIN_SUFFIX (pshufh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
14349 LOONGSON_BUILTIN_SUFFIX (psllh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
14350 LOONGSON_BUILTIN_SUFFIX (psllh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
14351 LOONGSON_BUILTIN_SUFFIX (psllw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
14352 LOONGSON_BUILTIN_SUFFIX (psllw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
14353 LOONGSON_BUILTIN_SUFFIX (psrah, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
14354 LOONGSON_BUILTIN_SUFFIX (psrah, s, MIPS_V4HI_FTYPE_V4HI_UQI),
14355 LOONGSON_BUILTIN_SUFFIX (psraw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
14356 LOONGSON_BUILTIN_SUFFIX (psraw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
14357 LOONGSON_BUILTIN_SUFFIX (psrlh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
14358 LOONGSON_BUILTIN_SUFFIX (psrlh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
14359 LOONGSON_BUILTIN_SUFFIX (psrlw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
14360 LOONGSON_BUILTIN_SUFFIX (psrlw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
14361 LOONGSON_BUILTIN_SUFFIX (psubw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14362 LOONGSON_BUILTIN_SUFFIX (psubh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14363 LOONGSON_BUILTIN_SUFFIX (psubb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14364 LOONGSON_BUILTIN_SUFFIX (psubw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14365 LOONGSON_BUILTIN_SUFFIX (psubh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14366 LOONGSON_BUILTIN_SUFFIX (psubb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14367 LOONGSON_BUILTIN_SUFFIX (psubd, u, MIPS_UDI_FTYPE_UDI_UDI),
14368 LOONGSON_BUILTIN_SUFFIX (psubd, s, MIPS_DI_FTYPE_DI_DI),
14369 LOONGSON_BUILTIN (psubsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14370 LOONGSON_BUILTIN (psubsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
14371 LOONGSON_BUILTIN (psubush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14372 LOONGSON_BUILTIN (psubusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14373 LOONGSON_BUILTIN_SUFFIX (punpckhbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14374 LOONGSON_BUILTIN_SUFFIX (punpckhhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14375 LOONGSON_BUILTIN_SUFFIX (punpckhwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14376 LOONGSON_BUILTIN_SUFFIX (punpckhbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14377 LOONGSON_BUILTIN_SUFFIX (punpckhhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14378 LOONGSON_BUILTIN_SUFFIX (punpckhwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14379 LOONGSON_BUILTIN_SUFFIX (punpcklbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14380 LOONGSON_BUILTIN_SUFFIX (punpcklhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14381 LOONGSON_BUILTIN_SUFFIX (punpcklwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14382 LOONGSON_BUILTIN_SUFFIX (punpcklbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14383 LOONGSON_BUILTIN_SUFFIX (punpcklhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14384 LOONGSON_BUILTIN_SUFFIX (punpcklwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14386 /* Sundry other built-in functions. */
14387 DIRECT_NO_TARGET_BUILTIN (cache, MIPS_VOID_FTYPE_SI_CVPOINTER, cache)
14390 /* Index I is the function declaration for mips_builtins[I], or null if the
14391 function isn't defined on this target. */
14392 static GTY(()) tree mips_builtin_decls[ARRAY_SIZE (mips_builtins)];
14394 /* MODE is a vector mode whose elements have type TYPE. Return the type
14395 of the vector itself. */
14398 mips_builtin_vector_type (tree type, machine_mode mode)
14400 static tree types[2 * (int) MAX_MACHINE_MODE];
14403 mode_index = (int) mode;
14405 if (TREE_CODE (type) == INTEGER_TYPE && TYPE_UNSIGNED (type))
14406 mode_index += MAX_MACHINE_MODE;
14408 if (types[mode_index] == NULL_TREE)
14409 types[mode_index] = build_vector_type_for_mode (type, mode);
14410 return types[mode_index];
14413 /* Return a type for 'const volatile void *'. */
14416 mips_build_cvpointer_type (void)
14420 if (cache == NULL_TREE)
14421 cache = build_pointer_type (build_qualified_type
14423 TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE));
14427 /* Source-level argument types. */
14428 #define MIPS_ATYPE_VOID void_type_node
14429 #define MIPS_ATYPE_INT integer_type_node
14430 #define MIPS_ATYPE_POINTER ptr_type_node
14431 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
14433 /* Standard mode-based argument types. */
14434 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
14435 #define MIPS_ATYPE_SI intSI_type_node
14436 #define MIPS_ATYPE_USI unsigned_intSI_type_node
14437 #define MIPS_ATYPE_DI intDI_type_node
14438 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
14439 #define MIPS_ATYPE_SF float_type_node
14440 #define MIPS_ATYPE_DF double_type_node
14442 /* Vector argument types. */
14443 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
14444 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
14445 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
14446 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
14447 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
14448 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
14449 #define MIPS_ATYPE_UV2SI \
14450 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
14451 #define MIPS_ATYPE_UV4HI \
14452 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
14453 #define MIPS_ATYPE_UV8QI \
14454 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
14456 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
14457 their associated MIPS_ATYPEs. */
14458 #define MIPS_FTYPE_ATYPES1(A, B) \
14459 MIPS_ATYPE_##A, MIPS_ATYPE_##B
14461 #define MIPS_FTYPE_ATYPES2(A, B, C) \
14462 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
14464 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
14465 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
14467 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
14468 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
14471 /* Return the function type associated with function prototype TYPE. */
14474 mips_build_function_type (enum mips_function_type type)
14476 static tree types[(int) MIPS_MAX_FTYPE_MAX];
14478 if (types[(int) type] == NULL_TREE)
14481 #define DEF_MIPS_FTYPE(NUM, ARGS) \
14482 case MIPS_FTYPE_NAME##NUM ARGS: \
14483 types[(int) type] \
14484 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
14487 #include "config/mips/mips-ftypes.def"
14488 #undef DEF_MIPS_FTYPE
14490 gcc_unreachable ();
14493 return types[(int) type];
14496 /* Implement TARGET_INIT_BUILTINS. */
14499 mips_init_builtins (void)
14501 const struct mips_builtin_description *d;
14504 /* Iterate through all of the bdesc arrays, initializing all of the
14505 builtin functions. */
14506 for (i = 0; i < ARRAY_SIZE (mips_builtins); i++)
14508 d = &mips_builtins[i];
14510 mips_builtin_decls[i]
14511 = add_builtin_function (d->name,
14512 mips_build_function_type (d->function_type),
14513 i, BUILT_IN_MD, NULL, NULL);
14517 /* Implement TARGET_BUILTIN_DECL. */
14520 mips_builtin_decl (unsigned int code, bool initialize_p ATTRIBUTE_UNUSED)
14522 if (code >= ARRAY_SIZE (mips_builtins))
14523 return error_mark_node;
14524 return mips_builtin_decls[code];
14527 /* Take argument ARGNO from EXP's argument list and convert it into
14528 an expand operand. Store the operand in *OP. */
14531 mips_prepare_builtin_arg (struct expand_operand *op, tree exp,
14532 unsigned int argno)
14537 arg = CALL_EXPR_ARG (exp, argno);
14538 value = expand_normal (arg);
14539 create_input_operand (op, value, TYPE_MODE (TREE_TYPE (arg)));
14542 /* Expand instruction ICODE as part of a built-in function sequence.
14543 Use the first NOPS elements of OPS as the instruction's operands.
14544 HAS_TARGET_P is true if operand 0 is a target; it is false if the
14545 instruction has no target.
14547 Return the target rtx if HAS_TARGET_P, otherwise return const0_rtx. */
14550 mips_expand_builtin_insn (enum insn_code icode, unsigned int nops,
14551 struct expand_operand *ops, bool has_target_p)
14553 if (!maybe_expand_insn (icode, nops, ops))
14555 error ("invalid argument to built-in function");
14556 return has_target_p ? gen_reg_rtx (ops[0].mode) : const0_rtx;
14558 return has_target_p ? ops[0].value : const0_rtx;
14561 /* Expand a floating-point comparison for built-in function call EXP.
14562 The first NARGS arguments are the values to be compared. ICODE is
14563 the .md pattern that does the comparison and COND is the condition
14564 that is being tested. Return an rtx for the result. */
14567 mips_expand_builtin_compare_1 (enum insn_code icode,
14568 enum mips_fp_condition cond,
14569 tree exp, int nargs)
14571 struct expand_operand ops[MAX_RECOG_OPERANDS];
14575 /* The instruction should have a target operand, an operand for each
14576 argument, and an operand for COND. */
14577 gcc_assert (nargs + 2 == insn_data[(int) icode].n_generator_args);
14579 output = mips_allocate_fcc (insn_data[(int) icode].operand[0].mode);
14581 create_fixed_operand (&ops[opno++], output);
14582 for (argno = 0; argno < nargs; argno++)
14583 mips_prepare_builtin_arg (&ops[opno++], exp, argno);
14584 create_integer_operand (&ops[opno++], (int) cond);
14585 return mips_expand_builtin_insn (icode, opno, ops, true);
14588 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
14589 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
14590 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
14591 suggests a good place to put the result. */
14594 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
14597 struct expand_operand ops[MAX_RECOG_OPERANDS];
14600 /* Map any target to operand 0. */
14603 create_output_operand (&ops[opno++], target, TYPE_MODE (TREE_TYPE (exp)));
14605 /* Map the arguments to the other operands. */
14606 gcc_assert (opno + call_expr_nargs (exp)
14607 == insn_data[icode].n_generator_args);
14608 for (argno = 0; argno < call_expr_nargs (exp); argno++)
14609 mips_prepare_builtin_arg (&ops[opno++], exp, argno);
14611 return mips_expand_builtin_insn (icode, opno, ops, has_target_p);
14614 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
14615 function; TYPE says which. EXP is the CALL_EXPR that calls the
14616 function, ICODE is the instruction that should be used to compare
14617 the first two arguments, and COND is the condition it should test.
14618 TARGET, if nonnull, suggests a good place to put the result. */
14621 mips_expand_builtin_movtf (enum mips_builtin_type type,
14622 enum insn_code icode, enum mips_fp_condition cond,
14623 rtx target, tree exp)
14625 struct expand_operand ops[4];
14628 cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp, 2);
14629 create_output_operand (&ops[0], target, TYPE_MODE (TREE_TYPE (exp)));
14630 if (type == MIPS_BUILTIN_MOVT)
14632 mips_prepare_builtin_arg (&ops[2], exp, 2);
14633 mips_prepare_builtin_arg (&ops[1], exp, 3);
14637 mips_prepare_builtin_arg (&ops[1], exp, 2);
14638 mips_prepare_builtin_arg (&ops[2], exp, 3);
14640 create_fixed_operand (&ops[3], cmp_result);
14641 return mips_expand_builtin_insn (CODE_FOR_mips_cond_move_tf_ps,
14645 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
14646 into TARGET otherwise. Return TARGET. */
14649 mips_builtin_branch_and_move (rtx condition, rtx target,
14650 rtx value_if_true, rtx value_if_false)
14652 rtx_code_label *true_label, *done_label;
14654 true_label = gen_label_rtx ();
14655 done_label = gen_label_rtx ();
14657 /* First assume that CONDITION is false. */
14658 mips_emit_move (target, value_if_false);
14660 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
14661 emit_jump_insn (gen_condjump (condition, true_label));
14662 emit_jump_insn (gen_jump (done_label));
14665 /* Fix TARGET if CONDITION is true. */
14666 emit_label (true_label);
14667 mips_emit_move (target, value_if_true);
14669 emit_label (done_label);
14673 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
14674 the CALL_EXPR that calls the function, ICODE is the code of the
14675 comparison instruction, and COND is the condition it should test.
14676 TARGET, if nonnull, suggests a good place to put the boolean result. */
14679 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
14680 enum insn_code icode, enum mips_fp_condition cond,
14681 rtx target, tree exp)
14683 rtx offset, condition, cmp_result;
14685 if (target == 0 || GET_MODE (target) != SImode)
14686 target = gen_reg_rtx (SImode);
14687 cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp,
14688 call_expr_nargs (exp));
14690 /* If the comparison sets more than one register, we define the result
14691 to be 0 if all registers are false and -1 if all registers are true.
14692 The value of the complete result is indeterminate otherwise. */
14693 switch (builtin_type)
14695 case MIPS_BUILTIN_CMP_ALL:
14696 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
14697 return mips_builtin_branch_and_move (condition, target,
14698 const0_rtx, const1_rtx);
14700 case MIPS_BUILTIN_CMP_UPPER:
14701 case MIPS_BUILTIN_CMP_LOWER:
14702 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
14703 condition = gen_single_cc (cmp_result, offset);
14704 return mips_builtin_branch_and_move (condition, target,
14705 const1_rtx, const0_rtx);
14708 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
14709 return mips_builtin_branch_and_move (condition, target,
14710 const1_rtx, const0_rtx);
14714 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
14715 if nonnull, suggests a good place to put the boolean result. */
14718 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
14720 rtx condition, cmp_result;
14723 if (target == 0 || GET_MODE (target) != SImode)
14724 target = gen_reg_rtx (SImode);
14726 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
14728 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
14733 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
14734 return mips_builtin_branch_and_move (condition, target,
14735 const1_rtx, const0_rtx);
14738 /* Implement TARGET_EXPAND_BUILTIN. */
14741 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
14742 machine_mode mode, int ignore)
14745 unsigned int fcode, avail;
14746 const struct mips_builtin_description *d;
14748 fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
14749 fcode = DECL_FUNCTION_CODE (fndecl);
14750 gcc_assert (fcode < ARRAY_SIZE (mips_builtins));
14751 d = &mips_builtins[fcode];
14752 avail = d->avail ();
14753 gcc_assert (avail != 0);
14754 if (TARGET_MIPS16 && !(avail & BUILTIN_AVAIL_MIPS16))
14756 error ("built-in function %qE not supported for MIPS16",
14757 DECL_NAME (fndecl));
14758 return ignore ? const0_rtx : CONST0_RTX (mode);
14760 switch (d->builtin_type)
14762 case MIPS_BUILTIN_DIRECT:
14763 return mips_expand_builtin_direct (d->icode, target, exp, true);
14765 case MIPS_BUILTIN_DIRECT_NO_TARGET:
14766 return mips_expand_builtin_direct (d->icode, target, exp, false);
14768 case MIPS_BUILTIN_MOVT:
14769 case MIPS_BUILTIN_MOVF:
14770 return mips_expand_builtin_movtf (d->builtin_type, d->icode,
14771 d->cond, target, exp);
14773 case MIPS_BUILTIN_CMP_ANY:
14774 case MIPS_BUILTIN_CMP_ALL:
14775 case MIPS_BUILTIN_CMP_UPPER:
14776 case MIPS_BUILTIN_CMP_LOWER:
14777 case MIPS_BUILTIN_CMP_SINGLE:
14778 return mips_expand_builtin_compare (d->builtin_type, d->icode,
14779 d->cond, target, exp);
14781 case MIPS_BUILTIN_BPOSGE32:
14782 return mips_expand_builtin_bposge (d->builtin_type, target);
14784 gcc_unreachable ();
14787 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
14788 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
14789 struct mips16_constant {
14790 struct mips16_constant *next;
14792 rtx_code_label *label;
14796 /* Information about an incomplete MIPS16 constant pool. FIRST is the
14797 first constant, HIGHEST_ADDRESS is the highest address that the first
14798 byte of the pool can have, and INSN_ADDRESS is the current instruction
14800 struct mips16_constant_pool {
14801 struct mips16_constant *first;
14802 int highest_address;
14806 /* Add constant VALUE to POOL and return its label. MODE is the
14807 value's mode (used for CONST_INTs, etc.). */
14809 static rtx_code_label *
14810 mips16_add_constant (struct mips16_constant_pool *pool,
14811 rtx value, machine_mode mode)
14813 struct mips16_constant **p, *c;
14814 bool first_of_size_p;
14816 /* See whether the constant is already in the pool. If so, return the
14817 existing label, otherwise leave P pointing to the place where the
14818 constant should be added.
14820 Keep the pool sorted in increasing order of mode size so that we can
14821 reduce the number of alignments needed. */
14822 first_of_size_p = true;
14823 for (p = &pool->first; *p != 0; p = &(*p)->next)
14825 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
14826 return (*p)->label;
14827 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
14829 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
14830 first_of_size_p = false;
14833 /* In the worst case, the constant needed by the earliest instruction
14834 will end up at the end of the pool. The entire pool must then be
14835 accessible from that instruction.
14837 When adding the first constant, set the pool's highest address to
14838 the address of the first out-of-range byte. Adjust this address
14839 downwards each time a new constant is added. */
14840 if (pool->first == 0)
14841 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
14842 of the instruction with the lowest two bits clear. The base PC
14843 value for LDPC has the lowest three bits clear. Assume the worst
14844 case here; namely that the PC-relative instruction occupies the
14845 last 2 bytes in an aligned word. */
14846 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
14847 pool->highest_address -= GET_MODE_SIZE (mode);
14848 if (first_of_size_p)
14849 /* Take into account the worst possible padding due to alignment. */
14850 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
14852 /* Create a new entry. */
14853 c = XNEW (struct mips16_constant);
14856 c->label = gen_label_rtx ();
14863 /* Output constant VALUE after instruction INSN and return the last
14864 instruction emitted. MODE is the mode of the constant. */
14867 mips16_emit_constants_1 (machine_mode mode, rtx value, rtx_insn *insn)
14869 if (SCALAR_INT_MODE_P (mode) || ALL_SCALAR_FIXED_POINT_MODE_P (mode))
14871 rtx size = GEN_INT (GET_MODE_SIZE (mode));
14872 return emit_insn_after (gen_consttable_int (value, size), insn);
14875 if (SCALAR_FLOAT_MODE_P (mode))
14876 return emit_insn_after (gen_consttable_float (value), insn);
14878 if (VECTOR_MODE_P (mode))
14882 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
14883 insn = mips16_emit_constants_1 (GET_MODE_INNER (mode),
14884 CONST_VECTOR_ELT (value, i), insn);
14888 gcc_unreachable ();
14891 /* Dump out the constants in CONSTANTS after INSN. */
14894 mips16_emit_constants (struct mips16_constant *constants, rtx_insn *insn)
14896 struct mips16_constant *c, *next;
14900 for (c = constants; c != NULL; c = next)
14902 /* If necessary, increase the alignment of PC. */
14903 if (align < GET_MODE_SIZE (c->mode))
14905 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
14906 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
14908 align = GET_MODE_SIZE (c->mode);
14910 insn = emit_label_after (c->label, insn);
14911 insn = mips16_emit_constants_1 (c->mode, c->value, insn);
14917 emit_barrier_after (insn);
14920 /* Return the length of instruction INSN. */
14923 mips16_insn_length (rtx_insn *insn)
14925 if (JUMP_TABLE_DATA_P (insn))
14927 rtx body = PATTERN (insn);
14928 if (GET_CODE (body) == ADDR_VEC)
14929 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
14930 else if (GET_CODE (body) == ADDR_DIFF_VEC)
14931 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
14933 gcc_unreachable ();
14935 return get_attr_length (insn);
14938 /* If *X is a symbolic constant that refers to the constant pool, add
14939 the constant to POOL and rewrite *X to use the constant's label. */
14942 mips16_rewrite_pool_constant (struct mips16_constant_pool *pool, rtx *x)
14945 rtx_code_label *label;
14947 split_const (*x, &base, &offset);
14948 if (GET_CODE (base) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (base))
14950 label = mips16_add_constant (pool, copy_rtx (get_pool_constant (base)),
14951 get_pool_mode (base));
14952 base = gen_rtx_LABEL_REF (Pmode, label);
14953 *x = mips_unspec_address_offset (base, offset, SYMBOL_PC_RELATIVE);
14957 /* Rewrite INSN so that constant pool references refer to the constant's
14961 mips16_rewrite_pool_refs (rtx_insn *insn, struct mips16_constant_pool *pool)
14963 subrtx_ptr_iterator::array_type array;
14964 FOR_EACH_SUBRTX_PTR (iter, array, &PATTERN (insn), ALL)
14968 if (force_to_mem_operand (*loc, Pmode))
14970 rtx mem = force_const_mem (GET_MODE (*loc), *loc);
14971 validate_change (insn, loc, mem, false);
14976 mips16_rewrite_pool_constant (pool, &XEXP (*loc, 0));
14977 iter.skip_subrtxes ();
14981 if (TARGET_MIPS16_TEXT_LOADS)
14982 mips16_rewrite_pool_constant (pool, loc);
14983 if (GET_CODE (*loc) == CONST
14984 /* Don't rewrite the __mips16_rdwr symbol. */
14985 || (GET_CODE (*loc) == UNSPEC
14986 && XINT (*loc, 1) == UNSPEC_TLS_GET_TP))
14987 iter.skip_subrtxes ();
14992 /* Return whether CFG is used in mips_reorg. */
14995 mips_cfg_in_reorg (void)
14997 return (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
14998 || TARGET_RELAX_PIC_CALLS);
15001 /* Build MIPS16 constant pools. Split the instructions if SPLIT_P,
15002 otherwise assume that they are already split. */
15005 mips16_lay_out_constants (bool split_p)
15007 struct mips16_constant_pool pool;
15008 rtx_insn *insn, *barrier;
15010 if (!TARGET_MIPS16_PCREL_LOADS)
15015 if (mips_cfg_in_reorg ())
15016 split_all_insns ();
15018 split_all_insns_noflow ();
15021 memset (&pool, 0, sizeof (pool));
15022 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
15024 /* Rewrite constant pool references in INSN. */
15025 if (USEFUL_INSN_P (insn))
15026 mips16_rewrite_pool_refs (insn, &pool);
15028 pool.insn_address += mips16_insn_length (insn);
15030 if (pool.first != NULL)
15032 /* If there are no natural barriers between the first user of
15033 the pool and the highest acceptable address, we'll need to
15034 create a new instruction to jump around the constant pool.
15035 In the worst case, this instruction will be 4 bytes long.
15037 If it's too late to do this transformation after INSN,
15038 do it immediately before INSN. */
15039 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
15041 rtx_code_label *label;
15044 label = gen_label_rtx ();
15046 jump = emit_jump_insn_before (gen_jump (label), insn);
15047 JUMP_LABEL (jump) = label;
15048 LABEL_NUSES (label) = 1;
15049 barrier = emit_barrier_after (jump);
15051 emit_label_after (label, barrier);
15052 pool.insn_address += 4;
15055 /* See whether the constant pool is now out of range of the first
15056 user. If so, output the constants after the previous barrier.
15057 Note that any instructions between BARRIER and INSN (inclusive)
15058 will use negative offsets to refer to the pool. */
15059 if (pool.insn_address > pool.highest_address)
15061 mips16_emit_constants (pool.first, barrier);
15065 else if (BARRIER_P (insn))
15069 mips16_emit_constants (pool.first, get_last_insn ());
15072 /* Return true if it is worth r10k_simplify_address's while replacing
15073 an address with X. We are looking for constants, and for addresses
15074 at a known offset from the incoming stack pointer. */
15077 r10k_simplified_address_p (rtx x)
15079 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
15081 return x == virtual_incoming_args_rtx || CONSTANT_P (x);
15084 /* X is an expression that appears in INSN. Try to use the UD chains
15085 to simplify it, returning the simplified form on success and the
15086 original form otherwise. Replace the incoming value of $sp with
15087 virtual_incoming_args_rtx (which should never occur in X otherwise). */
15090 r10k_simplify_address (rtx x, rtx_insn *insn)
15092 rtx newx, op0, op1, set, note;
15093 rtx_insn *def_insn;
15095 struct df_link *defs;
15100 op0 = r10k_simplify_address (XEXP (x, 0), insn);
15101 if (op0 != XEXP (x, 0))
15102 newx = simplify_gen_unary (GET_CODE (x), GET_MODE (x),
15103 op0, GET_MODE (XEXP (x, 0)));
15105 else if (BINARY_P (x))
15107 op0 = r10k_simplify_address (XEXP (x, 0), insn);
15108 op1 = r10k_simplify_address (XEXP (x, 1), insn);
15109 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
15110 newx = simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
15112 else if (GET_CODE (x) == LO_SUM)
15114 /* LO_SUMs can be offset from HIGHs, if we know they won't
15115 overflow. See mips_classify_address for the rationale behind
15117 op0 = r10k_simplify_address (XEXP (x, 0), insn);
15118 if (GET_CODE (op0) == HIGH)
15119 newx = XEXP (x, 1);
15121 else if (REG_P (x))
15123 /* Uses are recorded by regno_reg_rtx, not X itself. */
15124 use = df_find_use (insn, regno_reg_rtx[REGNO (x)]);
15126 defs = DF_REF_CHAIN (use);
15128 /* Require a single definition. */
15129 if (defs && defs->next == NULL)
15132 if (DF_REF_IS_ARTIFICIAL (def))
15134 /* Replace the incoming value of $sp with
15135 virtual_incoming_args_rtx. */
15136 if (x == stack_pointer_rtx
15137 && DF_REF_BB (def) == ENTRY_BLOCK_PTR_FOR_FN (cfun))
15138 newx = virtual_incoming_args_rtx;
15140 else if (dominated_by_p (CDI_DOMINATORS, DF_REF_BB (use),
15143 /* Make sure that DEF_INSN is a single set of REG. */
15144 def_insn = DF_REF_INSN (def);
15145 if (NONJUMP_INSN_P (def_insn))
15147 set = single_set (def_insn);
15148 if (set && rtx_equal_p (SET_DEST (set), x))
15150 /* Prefer to use notes, since the def-use chains
15151 are often shorter. */
15152 note = find_reg_equal_equiv_note (def_insn);
15154 newx = XEXP (note, 0);
15156 newx = SET_SRC (set);
15157 newx = r10k_simplify_address (newx, def_insn);
15163 if (newx && r10k_simplified_address_p (newx))
15168 /* Return true if ADDRESS is known to be an uncached address
15169 on R10K systems. */
15172 r10k_uncached_address_p (unsigned HOST_WIDE_INT address)
15174 unsigned HOST_WIDE_INT upper;
15176 /* Check for KSEG1. */
15177 if (address + 0x60000000 < 0x20000000)
15180 /* Check for uncached XKPHYS addresses. */
15181 if (Pmode == DImode)
15183 upper = (address >> 40) & 0xf9ffff;
15184 if (upper == 0x900000 || upper == 0xb80000)
15190 /* Return true if we can prove that an access to address X in instruction
15191 INSN would be safe from R10K speculation. This X is a general
15192 expression; it might not be a legitimate address. */
15195 r10k_safe_address_p (rtx x, rtx_insn *insn)
15198 HOST_WIDE_INT offset_val;
15200 x = r10k_simplify_address (x, insn);
15202 /* Check for references to the stack frame. It doesn't really matter
15203 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
15204 allows us to assume that accesses to any part of the eventual frame
15205 is safe from speculation at any point in the function. */
15206 mips_split_plus (x, &base, &offset_val);
15207 if (base == virtual_incoming_args_rtx
15208 && offset_val >= -cfun->machine->frame.total_size
15209 && offset_val < cfun->machine->frame.args_size)
15212 /* Check for uncached addresses. */
15213 if (CONST_INT_P (x))
15214 return r10k_uncached_address_p (INTVAL (x));
15216 /* Check for accesses to a static object. */
15217 split_const (x, &base, &offset);
15218 return offset_within_block_p (base, INTVAL (offset));
15221 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
15222 an in-range access to an automatic variable, or to an object with
15223 a link-time-constant address. */
15226 r10k_safe_mem_expr_p (tree expr, unsigned HOST_WIDE_INT offset)
15228 HOST_WIDE_INT bitoffset, bitsize;
15229 tree inner, var_offset;
15231 int unsigned_p, volatile_p;
15233 inner = get_inner_reference (expr, &bitsize, &bitoffset, &var_offset, &mode,
15234 &unsigned_p, &volatile_p, false);
15235 if (!DECL_P (inner) || !DECL_SIZE_UNIT (inner) || var_offset)
15238 offset += bitoffset / BITS_PER_UNIT;
15239 return offset < tree_to_uhwi (DECL_SIZE_UNIT (inner));
15242 /* Return true if X contains a MEM that is not safe from R10K speculation.
15243 INSN is the instruction that contains X. */
15246 r10k_needs_protection_p_1 (rtx x, rtx_insn *insn)
15248 subrtx_var_iterator::array_type array;
15249 FOR_EACH_SUBRTX_VAR (iter, array, x, NONCONST)
15254 if ((MEM_EXPR (mem)
15255 && MEM_OFFSET_KNOWN_P (mem)
15256 && r10k_safe_mem_expr_p (MEM_EXPR (mem), MEM_OFFSET (mem)))
15257 || r10k_safe_address_p (XEXP (mem, 0), insn))
15258 iter.skip_subrtxes ();
15266 /* A note_stores callback for which DATA points to an instruction pointer.
15267 If *DATA is nonnull, make it null if it X contains a MEM that is not
15268 safe from R10K speculation. */
15271 r10k_needs_protection_p_store (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
15274 rtx_insn **insn_ptr;
15276 insn_ptr = (rtx_insn **) data;
15277 if (*insn_ptr && r10k_needs_protection_p_1 (x, *insn_ptr))
15281 /* X is the pattern of a call instruction. Return true if the call is
15282 not to a declared function. */
15285 r10k_needs_protection_p_call (const_rtx x)
15287 subrtx_iterator::array_type array;
15288 FOR_EACH_SUBRTX (iter, array, x, NONCONST)
15290 const_rtx mem = *iter;
15293 const_rtx addr = XEXP (mem, 0);
15294 if (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_DECL (addr))
15295 iter.skip_subrtxes ();
15303 /* Return true if instruction INSN needs to be protected by an R10K
15307 r10k_needs_protection_p (rtx_insn *insn)
15310 return r10k_needs_protection_p_call (PATTERN (insn));
15312 if (mips_r10k_cache_barrier == R10K_CACHE_BARRIER_STORE)
15314 note_stores (PATTERN (insn), r10k_needs_protection_p_store, &insn);
15315 return insn == NULL_RTX;
15318 return r10k_needs_protection_p_1 (PATTERN (insn), insn);
15321 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
15322 edge is unconditional. */
15325 r10k_protected_bb_p (basic_block bb, sbitmap protected_bbs)
15330 FOR_EACH_EDGE (e, ei, bb->preds)
15331 if (!single_succ_p (e->src)
15332 || !bitmap_bit_p (protected_bbs, e->src->index)
15333 || (e->flags & EDGE_COMPLEX) != 0)
15338 /* Implement -mr10k-cache-barrier= for the current function. */
15341 r10k_insert_cache_barriers (void)
15343 int *rev_post_order;
15346 sbitmap protected_bbs;
15347 rtx_insn *insn, *end;
15348 rtx unprotected_region;
15352 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
15356 /* Calculate dominators. */
15357 calculate_dominance_info (CDI_DOMINATORS);
15359 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
15360 X is protected by a cache barrier. */
15361 protected_bbs = sbitmap_alloc (last_basic_block_for_fn (cfun));
15362 bitmap_clear (protected_bbs);
15364 /* Iterate over the basic blocks in reverse post-order. */
15365 rev_post_order = XNEWVEC (int, last_basic_block_for_fn (cfun));
15366 n = pre_and_rev_post_order_compute (NULL, rev_post_order, false);
15367 for (i = 0; i < n; i++)
15369 bb = BASIC_BLOCK_FOR_FN (cfun, rev_post_order[i]);
15371 /* If this block is only reached by unconditional edges, and if the
15372 source of every edge is protected, the beginning of the block is
15374 if (r10k_protected_bb_p (bb, protected_bbs))
15375 unprotected_region = NULL_RTX;
15377 unprotected_region = pc_rtx;
15378 end = NEXT_INSN (BB_END (bb));
15380 /* UNPROTECTED_REGION is:
15382 - null if we are processing a protected region,
15383 - pc_rtx if we are processing an unprotected region but have
15384 not yet found the first instruction in it
15385 - the first instruction in an unprotected region otherwise. */
15386 for (insn = BB_HEAD (bb); insn != end; insn = NEXT_INSN (insn))
15388 if (unprotected_region && USEFUL_INSN_P (insn))
15390 if (recog_memoized (insn) == CODE_FOR_mips_cache)
15391 /* This CACHE instruction protects the following code. */
15392 unprotected_region = NULL_RTX;
15395 /* See if INSN is the first instruction in this
15396 unprotected region. */
15397 if (unprotected_region == pc_rtx)
15398 unprotected_region = insn;
15400 /* See if INSN needs to be protected. If so,
15401 we must insert a cache barrier somewhere between
15402 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
15403 clear which position is better performance-wise,
15404 but as a tie-breaker, we assume that it is better
15405 to allow delay slots to be back-filled where
15406 possible, and that it is better not to insert
15407 barriers in the middle of already-scheduled code.
15408 We therefore insert the barrier at the beginning
15410 if (r10k_needs_protection_p (insn))
15412 emit_insn_before (gen_r10k_cache_barrier (),
15413 unprotected_region);
15414 unprotected_region = NULL_RTX;
15420 /* The called function is not required to protect the exit path.
15421 The code that follows a call is therefore unprotected. */
15422 unprotected_region = pc_rtx;
15425 /* Record whether the end of this block is protected. */
15426 if (unprotected_region == NULL_RTX)
15427 bitmap_set_bit (protected_bbs, bb->index);
15429 XDELETEVEC (rev_post_order);
15431 sbitmap_free (protected_bbs);
15433 free_dominance_info (CDI_DOMINATORS);
15436 /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX
15437 otherwise. If INSN has two call rtx, then store the second one in
15441 mips_call_expr_from_insn (rtx_insn *insn, rtx *second_call)
15446 if (!CALL_P (insn))
15449 x = PATTERN (insn);
15450 if (GET_CODE (x) == PARALLEL)
15452 /* Calls returning complex values have two CALL rtx. Look for the second
15453 one here, and return it via the SECOND_CALL arg. */
15454 x2 = XVECEXP (x, 0, 1);
15455 if (GET_CODE (x2) == SET)
15457 if (GET_CODE (x2) == CALL)
15460 x = XVECEXP (x, 0, 0);
15462 if (GET_CODE (x) == SET)
15464 gcc_assert (GET_CODE (x) == CALL);
15469 /* REG is set in DEF. See if the definition is one of the ways we load a
15470 register with a symbol address for a mips_use_pic_fn_addr_reg_p call.
15471 If it is, return the symbol reference of the function, otherwise return
15474 If RECURSE_P is true, use mips_find_pic_call_symbol to interpret
15475 the values of source registers, otherwise treat such registers as
15476 having an unknown value. */
15479 mips_pic_call_symbol_from_set (df_ref def, rtx reg, bool recurse_p)
15481 rtx_insn *def_insn;
15484 if (DF_REF_IS_ARTIFICIAL (def))
15487 def_insn = DF_REF_INSN (def);
15488 set = single_set (def_insn);
15489 if (set && rtx_equal_p (SET_DEST (set), reg))
15491 rtx note, src, symbol;
15493 /* First see whether the source is a plain symbol. This is used
15494 when calling symbols that are not lazily bound. */
15495 src = SET_SRC (set);
15496 if (GET_CODE (src) == SYMBOL_REF)
15499 /* Handle %call16 references. */
15500 symbol = mips_strip_unspec_call (src);
15503 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
15507 /* If we have something more complicated, look for a
15508 REG_EQUAL or REG_EQUIV note. */
15509 note = find_reg_equal_equiv_note (def_insn);
15510 if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF)
15511 return XEXP (note, 0);
15513 /* Follow at most one simple register copy. Such copies are
15514 interesting in cases like:
15518 locally_binding_fn (...);
15523 locally_binding_fn (...);
15525 locally_binding_fn (...);
15527 where the load of locally_binding_fn can legitimately be
15528 hoisted or shared. However, we do not expect to see complex
15529 chains of copies, so a full worklist solution to the problem
15530 would probably be overkill. */
15531 if (recurse_p && REG_P (src))
15532 return mips_find_pic_call_symbol (def_insn, src, false);
15538 /* Find the definition of the use of REG in INSN. See if the definition
15539 is one of the ways we load a register with a symbol address for a
15540 mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference
15541 of the function, otherwise return NULL_RTX. RECURSE_P is as for
15542 mips_pic_call_symbol_from_set. */
15545 mips_find_pic_call_symbol (rtx_insn *insn, rtx reg, bool recurse_p)
15548 struct df_link *defs;
15551 use = df_find_use (insn, regno_reg_rtx[REGNO (reg)]);
15554 defs = DF_REF_CHAIN (use);
15557 symbol = mips_pic_call_symbol_from_set (defs->ref, reg, recurse_p);
15561 /* If we have more than one definition, they need to be identical. */
15562 for (defs = defs->next; defs; defs = defs->next)
15566 other = mips_pic_call_symbol_from_set (defs->ref, reg, recurse_p);
15567 if (!rtx_equal_p (symbol, other))
15574 /* Replace the args_size operand of the call expression CALL with the
15575 call-attribute UNSPEC and fill in SYMBOL as the function symbol. */
15578 mips_annotate_pic_call_expr (rtx call, rtx symbol)
15582 args_size = XEXP (call, 1);
15583 XEXP (call, 1) = gen_rtx_UNSPEC (GET_MODE (args_size),
15584 gen_rtvec (2, args_size, symbol),
15588 /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See
15589 if instead of the arg_size argument it contains the call attributes. If
15590 yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function
15591 symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is
15595 mips_get_pic_call_symbol (rtx *operands, int args_size_opno)
15597 rtx args_size, symbol;
15599 if (!TARGET_RELAX_PIC_CALLS || args_size_opno == -1)
15602 args_size = operands[args_size_opno];
15603 if (GET_CODE (args_size) != UNSPEC)
15605 gcc_assert (XINT (args_size, 1) == UNSPEC_CALL_ATTR);
15607 symbol = XVECEXP (args_size, 0, 1);
15608 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
15610 operands[args_size_opno] = symbol;
15614 /* Use DF to annotate PIC indirect calls with the function symbol they
15618 mips_annotate_pic_calls (void)
15623 FOR_EACH_BB_FN (bb, cfun)
15624 FOR_BB_INSNS (bb, insn)
15626 rtx call, reg, symbol, second_call;
15629 call = mips_call_expr_from_insn (insn, &second_call);
15632 gcc_assert (MEM_P (XEXP (call, 0)));
15633 reg = XEXP (XEXP (call, 0), 0);
15637 symbol = mips_find_pic_call_symbol (insn, reg, true);
15640 mips_annotate_pic_call_expr (call, symbol);
15642 mips_annotate_pic_call_expr (second_call, symbol);
15647 /* A temporary variable used by note_uses callbacks, etc. */
15648 static rtx_insn *mips_sim_insn;
15650 /* A structure representing the state of the processor pipeline.
15651 Used by the mips_sim_* family of functions. */
15653 /* The maximum number of instructions that can be issued in a cycle.
15654 (Caches mips_issue_rate.) */
15655 unsigned int issue_rate;
15657 /* The current simulation time. */
15660 /* How many more instructions can be issued in the current cycle. */
15661 unsigned int insns_left;
15663 /* LAST_SET[X].INSN is the last instruction to set register X.
15664 LAST_SET[X].TIME is the time at which that instruction was issued.
15665 INSN is null if no instruction has yet set register X. */
15669 } last_set[FIRST_PSEUDO_REGISTER];
15671 /* The pipeline's current DFA state. */
15675 /* Reset STATE to the initial simulation state. */
15678 mips_sim_reset (struct mips_sim *state)
15680 curr_state = state->dfa_state;
15683 state->insns_left = state->issue_rate;
15684 memset (&state->last_set, 0, sizeof (state->last_set));
15685 state_reset (curr_state);
15687 targetm.sched.init (0, false, 0);
15688 advance_state (curr_state);
15691 /* Initialize STATE before its first use. DFA_STATE points to an
15692 allocated but uninitialized DFA state. */
15695 mips_sim_init (struct mips_sim *state, state_t dfa_state)
15697 if (targetm.sched.init_dfa_pre_cycle_insn)
15698 targetm.sched.init_dfa_pre_cycle_insn ();
15700 if (targetm.sched.init_dfa_post_cycle_insn)
15701 targetm.sched.init_dfa_post_cycle_insn ();
15703 state->issue_rate = mips_issue_rate ();
15704 state->dfa_state = dfa_state;
15705 mips_sim_reset (state);
15708 /* Advance STATE by one clock cycle. */
15711 mips_sim_next_cycle (struct mips_sim *state)
15713 curr_state = state->dfa_state;
15716 state->insns_left = state->issue_rate;
15717 advance_state (curr_state);
15720 /* Advance simulation state STATE until instruction INSN can read
15724 mips_sim_wait_reg (struct mips_sim *state, rtx_insn *insn, rtx reg)
15726 unsigned int regno, end_regno;
15728 end_regno = END_REGNO (reg);
15729 for (regno = REGNO (reg); regno < end_regno; regno++)
15730 if (state->last_set[regno].insn != 0)
15734 t = (state->last_set[regno].time
15735 + insn_latency (state->last_set[regno].insn, insn));
15736 while (state->time < t)
15737 mips_sim_next_cycle (state);
15741 /* A note_uses callback. For each register in *X, advance simulation
15742 state DATA until mips_sim_insn can read the register's value. */
15745 mips_sim_wait_regs_1 (rtx *x, void *data)
15747 subrtx_var_iterator::array_type array;
15748 FOR_EACH_SUBRTX_VAR (iter, array, *x, NONCONST)
15750 mips_sim_wait_reg ((struct mips_sim *) data, mips_sim_insn, *iter);
15753 /* Advance simulation state STATE until all of INSN's register
15754 dependencies are satisfied. */
15757 mips_sim_wait_regs (struct mips_sim *state, rtx_insn *insn)
15759 mips_sim_insn = insn;
15760 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
15763 /* Advance simulation state STATE until the units required by
15764 instruction INSN are available. */
15767 mips_sim_wait_units (struct mips_sim *state, rtx_insn *insn)
15771 tmp_state = alloca (state_size ());
15772 while (state->insns_left == 0
15773 || (memcpy (tmp_state, state->dfa_state, state_size ()),
15774 state_transition (tmp_state, insn) >= 0))
15775 mips_sim_next_cycle (state);
15778 /* Advance simulation state STATE until INSN is ready to issue. */
15781 mips_sim_wait_insn (struct mips_sim *state, rtx_insn *insn)
15783 mips_sim_wait_regs (state, insn);
15784 mips_sim_wait_units (state, insn);
15787 /* mips_sim_insn has just set X. Update the LAST_SET array
15788 in simulation state DATA. */
15791 mips_sim_record_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
15793 struct mips_sim *state;
15795 state = (struct mips_sim *) data;
15798 unsigned int regno, end_regno;
15800 end_regno = END_REGNO (x);
15801 for (regno = REGNO (x); regno < end_regno; regno++)
15803 state->last_set[regno].insn = mips_sim_insn;
15804 state->last_set[regno].time = state->time;
15809 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
15810 can issue immediately (i.e., that mips_sim_wait_insn has already
15814 mips_sim_issue_insn (struct mips_sim *state, rtx_insn *insn)
15816 curr_state = state->dfa_state;
15818 state_transition (curr_state, insn);
15819 state->insns_left = targetm.sched.variable_issue (0, false, insn,
15820 state->insns_left);
15822 mips_sim_insn = insn;
15823 note_stores (PATTERN (insn), mips_sim_record_set, state);
15826 /* Simulate issuing a NOP in state STATE. */
15829 mips_sim_issue_nop (struct mips_sim *state)
15831 if (state->insns_left == 0)
15832 mips_sim_next_cycle (state);
15833 state->insns_left--;
15836 /* Update simulation state STATE so that it's ready to accept the instruction
15837 after INSN. INSN should be part of the main rtl chain, not a member of a
15841 mips_sim_finish_insn (struct mips_sim *state, rtx_insn *insn)
15843 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
15845 mips_sim_issue_nop (state);
15847 switch (GET_CODE (SEQ_BEGIN (insn)))
15851 /* We can't predict the processor state after a call or label. */
15852 mips_sim_reset (state);
15856 /* The delay slots of branch likely instructions are only executed
15857 when the branch is taken. Therefore, if the caller has simulated
15858 the delay slot instruction, STATE does not really reflect the state
15859 of the pipeline for the instruction after the delay slot. Also,
15860 branch likely instructions tend to incur a penalty when not taken,
15861 so there will probably be an extra delay between the branch and
15862 the instruction after the delay slot. */
15863 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
15864 mips_sim_reset (state);
15872 /* Use simulator state STATE to calculate the execution time of
15873 instruction sequence SEQ. */
15875 static unsigned int
15876 mips_seq_time (struct mips_sim *state, rtx_insn *seq)
15878 mips_sim_reset (state);
15879 for (rtx_insn *insn = seq; insn; insn = NEXT_INSN (insn))
15881 mips_sim_wait_insn (state, insn);
15882 mips_sim_issue_insn (state, insn);
15884 return state->time;
15887 /* Return the execution-time cost of mips_tuning_info.fast_mult_zero_zero_p
15888 setting SETTING, using STATE to simulate instruction sequences. */
15890 static unsigned int
15891 mips_mult_zero_zero_cost (struct mips_sim *state, bool setting)
15893 mips_tuning_info.fast_mult_zero_zero_p = setting;
15896 machine_mode dword_mode = TARGET_64BIT ? TImode : DImode;
15897 rtx hilo = gen_rtx_REG (dword_mode, MD_REG_FIRST);
15898 mips_emit_move_or_split (hilo, const0_rtx, SPLIT_FOR_SPEED);
15900 /* If the target provides mulsidi3_32bit then that's the most likely
15901 consumer of the result. Test for bypasses. */
15902 if (dword_mode == DImode && HAVE_maddsidi4)
15904 rtx gpr = gen_rtx_REG (SImode, GP_REG_FIRST + 4);
15905 emit_insn (gen_maddsidi4 (hilo, gpr, gpr, hilo));
15908 unsigned int time = mips_seq_time (state, get_insns ());
15913 /* Check the relative speeds of "MULT $0,$0" and "MTLO $0; MTHI $0"
15914 and set up mips_tuning_info.fast_mult_zero_zero_p accordingly.
15915 Prefer MULT -- which is shorter -- in the event of a tie. */
15918 mips_set_fast_mult_zero_zero_p (struct mips_sim *state)
15921 /* No MTLO or MTHI available. */
15922 mips_tuning_info.fast_mult_zero_zero_p = true;
15925 unsigned int true_time = mips_mult_zero_zero_cost (state, true);
15926 unsigned int false_time = mips_mult_zero_zero_cost (state, false);
15927 mips_tuning_info.fast_mult_zero_zero_p = (true_time <= false_time);
15931 /* Set up costs based on the current architecture and tuning settings. */
15934 mips_set_tuning_info (void)
15936 if (mips_tuning_info.initialized_p
15937 && mips_tuning_info.arch == mips_arch
15938 && mips_tuning_info.tune == mips_tune
15939 && mips_tuning_info.mips16_p == TARGET_MIPS16)
15942 mips_tuning_info.arch = mips_arch;
15943 mips_tuning_info.tune = mips_tune;
15944 mips_tuning_info.mips16_p = TARGET_MIPS16;
15945 mips_tuning_info.initialized_p = true;
15949 struct mips_sim state;
15950 mips_sim_init (&state, alloca (state_size ()));
15952 mips_set_fast_mult_zero_zero_p (&state);
15957 /* Implement TARGET_EXPAND_TO_RTL_HOOK. */
15960 mips_expand_to_rtl_hook (void)
15962 /* We need to call this at a point where we can safely create sequences
15963 of instructions, so TARGET_OVERRIDE_OPTIONS is too early. We also
15964 need to call it at a point where the DFA infrastructure is not
15965 already in use, so we can't just call it lazily on demand.
15967 At present, mips_tuning_info is only needed during post-expand
15968 RTL passes such as split_insns, so this hook should be early enough.
15969 We may need to move the call elsewhere if mips_tuning_info starts
15970 to be used for other things (such as rtx_costs, or expanders that
15971 could be called during gimple optimization). */
15972 mips_set_tuning_info ();
15975 /* The VR4130 pipeline issues aligned pairs of instructions together,
15976 but it stalls the second instruction if it depends on the first.
15977 In order to cut down the amount of logic required, this dependence
15978 check is not based on a full instruction decode. Instead, any non-SPECIAL
15979 instruction is assumed to modify the register specified by bits 20-16
15980 (which is usually the "rt" field).
15982 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
15983 input, so we can end up with a false dependence between the branch
15984 and its delay slot. If this situation occurs in instruction INSN,
15985 try to avoid it by swapping rs and rt. */
15988 vr4130_avoid_branch_rt_conflict (rtx_insn *insn)
15990 rtx_insn *first, *second;
15992 first = SEQ_BEGIN (insn);
15993 second = SEQ_END (insn);
15995 && NONJUMP_INSN_P (second)
15996 && GET_CODE (PATTERN (first)) == SET
15997 && GET_CODE (SET_DEST (PATTERN (first))) == PC
15998 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
16000 /* Check for the right kind of condition. */
16001 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
16002 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
16003 && REG_P (XEXP (cond, 0))
16004 && REG_P (XEXP (cond, 1))
16005 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
16006 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
16008 /* SECOND mentions the rt register but not the rs register. */
16009 rtx tmp = XEXP (cond, 0);
16010 XEXP (cond, 0) = XEXP (cond, 1);
16011 XEXP (cond, 1) = tmp;
16016 /* Implement -mvr4130-align. Go through each basic block and simulate the
16017 processor pipeline. If we find that a pair of instructions could execute
16018 in parallel, and the first of those instructions is not 8-byte aligned,
16019 insert a nop to make it aligned. */
16022 vr4130_align_insns (void)
16024 struct mips_sim state;
16025 rtx_insn *insn, *subinsn, *last, *last2, *next;
16030 /* LAST is the last instruction before INSN to have a nonzero length.
16031 LAST2 is the last such instruction before LAST. */
16035 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
16038 mips_sim_init (&state, alloca (state_size ()));
16039 for (insn = get_insns (); insn != 0; insn = next)
16041 unsigned int length;
16043 next = NEXT_INSN (insn);
16045 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
16046 This isn't really related to the alignment pass, but we do it on
16047 the fly to avoid a separate instruction walk. */
16048 vr4130_avoid_branch_rt_conflict (insn);
16050 length = get_attr_length (insn);
16051 if (length > 0 && USEFUL_INSN_P (insn))
16052 FOR_EACH_SUBINSN (subinsn, insn)
16054 mips_sim_wait_insn (&state, subinsn);
16056 /* If we want this instruction to issue in parallel with the
16057 previous one, make sure that the previous instruction is
16058 aligned. There are several reasons why this isn't worthwhile
16059 when the second instruction is a call:
16061 - Calls are less likely to be performance critical,
16062 - There's a good chance that the delay slot can execute
16063 in parallel with the call.
16064 - The return address would then be unaligned.
16066 In general, if we're going to insert a nop between instructions
16067 X and Y, it's better to insert it immediately after X. That
16068 way, if the nop makes Y aligned, it will also align any labels
16069 between X and Y. */
16070 if (state.insns_left != state.issue_rate
16071 && !CALL_P (subinsn))
16073 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
16075 /* SUBINSN is the first instruction in INSN and INSN is
16076 aligned. We want to align the previous instruction
16077 instead, so insert a nop between LAST2 and LAST.
16079 Note that LAST could be either a single instruction
16080 or a branch with a delay slot. In the latter case,
16081 LAST, like INSN, is already aligned, but the delay
16082 slot must have some extra delay that stops it from
16083 issuing at the same time as the branch. We therefore
16084 insert a nop before the branch in order to align its
16086 gcc_assert (last2);
16087 emit_insn_after (gen_nop (), last2);
16090 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
16092 /* SUBINSN is the delay slot of INSN, but INSN is
16093 currently unaligned. Insert a nop between
16094 LAST and INSN to align it. */
16096 emit_insn_after (gen_nop (), last);
16100 mips_sim_issue_insn (&state, subinsn);
16102 mips_sim_finish_insn (&state, insn);
16104 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
16105 length = get_attr_length (insn);
16108 /* If the instruction is an asm statement or multi-instruction
16109 mips.md patern, the length is only an estimate. Insert an
16110 8 byte alignment after it so that the following instructions
16111 can be handled correctly. */
16112 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
16113 && (recog_memoized (insn) < 0 || length >= 8))
16115 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
16116 next = NEXT_INSN (next);
16117 mips_sim_next_cycle (&state);
16120 else if (length & 4)
16121 aligned_p = !aligned_p;
16126 /* See whether INSN is an aligned label. */
16127 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
16133 /* This structure records that the current function has a LO_SUM
16134 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
16135 the largest offset applied to BASE by all such LO_SUMs. */
16136 struct mips_lo_sum_offset {
16138 HOST_WIDE_INT offset;
16141 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
16144 mips_hash_base (rtx base)
16146 int do_not_record_p;
16148 return hash_rtx (base, GET_MODE (base), &do_not_record_p, NULL, false);
16151 /* Hashtable helpers. */
16153 struct mips_lo_sum_offset_hasher : typed_free_remove <mips_lo_sum_offset>
16155 typedef mips_lo_sum_offset value_type;
16156 typedef rtx_def compare_type;
16157 static inline hashval_t hash (const value_type *);
16158 static inline bool equal (const value_type *, const compare_type *);
16161 /* Hash-table callbacks for mips_lo_sum_offsets. */
16164 mips_lo_sum_offset_hasher::hash (const value_type *entry)
16166 return mips_hash_base (entry->base);
16170 mips_lo_sum_offset_hasher::equal (const value_type *entry,
16171 const compare_type *value)
16173 return rtx_equal_p (entry->base, value);
16176 typedef hash_table<mips_lo_sum_offset_hasher> mips_offset_table;
16178 /* Look up symbolic constant X in HTAB, which is a hash table of
16179 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
16180 paired with a recorded LO_SUM, otherwise record X in the table. */
16183 mips_lo_sum_offset_lookup (mips_offset_table *htab, rtx x,
16184 enum insert_option option)
16187 mips_lo_sum_offset **slot;
16188 struct mips_lo_sum_offset *entry;
16190 /* Split X into a base and offset. */
16191 split_const (x, &base, &offset);
16192 if (UNSPEC_ADDRESS_P (base))
16193 base = UNSPEC_ADDRESS (base);
16195 /* Look up the base in the hash table. */
16196 slot = htab->find_slot_with_hash (base, mips_hash_base (base), option);
16200 entry = (struct mips_lo_sum_offset *) *slot;
16201 if (option == INSERT)
16205 entry = XNEW (struct mips_lo_sum_offset);
16206 entry->base = base;
16207 entry->offset = INTVAL (offset);
16212 if (INTVAL (offset) > entry->offset)
16213 entry->offset = INTVAL (offset);
16216 return INTVAL (offset) <= entry->offset;
16219 /* Search X for LO_SUMs and record them in HTAB. */
16222 mips_record_lo_sums (const_rtx x, mips_offset_table *htab)
16224 subrtx_iterator::array_type array;
16225 FOR_EACH_SUBRTX (iter, array, x, NONCONST)
16226 if (GET_CODE (*iter) == LO_SUM)
16227 mips_lo_sum_offset_lookup (htab, XEXP (*iter, 1), INSERT);
16230 /* Return true if INSN is a SET of an orphaned high-part relocation.
16231 HTAB is a hash table of mips_lo_sum_offsets that describes all the
16232 LO_SUMs in the current function. */
16235 mips_orphaned_high_part_p (mips_offset_table *htab, rtx_insn *insn)
16237 enum mips_symbol_type type;
16240 set = single_set (insn);
16243 /* Check for %his. */
16245 if (GET_CODE (x) == HIGH
16246 && absolute_symbolic_operand (XEXP (x, 0), VOIDmode))
16247 return !mips_lo_sum_offset_lookup (htab, XEXP (x, 0), NO_INSERT);
16249 /* Check for local %gots (and %got_pages, which is redundant but OK). */
16250 if (GET_CODE (x) == UNSPEC
16251 && XINT (x, 1) == UNSPEC_LOAD_GOT
16252 && mips_symbolic_constant_p (XVECEXP (x, 0, 1),
16253 SYMBOL_CONTEXT_LEA, &type)
16254 && type == SYMBOL_GOTOFF_PAGE)
16255 return !mips_lo_sum_offset_lookup (htab, XVECEXP (x, 0, 1), NO_INSERT);
16260 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
16261 INSN and a previous instruction, avoid it by inserting nops after
16264 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
16265 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
16266 before using the value of that register. *HILO_DELAY counts the
16267 number of instructions since the last hilo hazard (that is,
16268 the number of instructions since the last MFLO or MFHI).
16270 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
16271 for the next instruction.
16273 LO_REG is an rtx for the LO register, used in dependence checking. */
16276 mips_avoid_hazard (rtx_insn *after, rtx_insn *insn, int *hilo_delay,
16277 rtx *delayed_reg, rtx lo_reg)
16282 pattern = PATTERN (insn);
16284 /* Do not put the whole function in .set noreorder if it contains
16285 an asm statement. We don't know whether there will be hazards
16286 between the asm statement and the gcc-generated code. */
16287 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
16288 cfun->machine->all_noreorder_p = false;
16290 /* Ignore zero-length instructions (barriers and the like). */
16291 ninsns = get_attr_length (insn) / 4;
16295 /* Work out how many nops are needed. Note that we only care about
16296 registers that are explicitly mentioned in the instruction's pattern.
16297 It doesn't matter that calls use the argument registers or that they
16298 clobber hi and lo. */
16299 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
16300 nops = 2 - *hilo_delay;
16301 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
16306 /* Insert the nops between this instruction and the previous one.
16307 Each new nop takes us further from the last hilo hazard. */
16308 *hilo_delay += nops;
16310 emit_insn_after (gen_hazard_nop (), after);
16312 /* Set up the state for the next instruction. */
16313 *hilo_delay += ninsns;
16315 if (INSN_CODE (insn) >= 0)
16316 switch (get_attr_hazard (insn))
16326 set = single_set (insn);
16328 *delayed_reg = SET_DEST (set);
16333 /* Go through the instruction stream and insert nops where necessary.
16334 Also delete any high-part relocations whose partnering low parts
16335 are now all dead. See if the whole function can then be put into
16336 .set noreorder and .set nomacro. */
16339 mips_reorg_process_insns (void)
16341 rtx_insn *insn, *last_insn, *subinsn, *next_insn;
16342 rtx lo_reg, delayed_reg;
16345 /* Force all instructions to be split into their final form. */
16346 split_all_insns_noflow ();
16348 /* Recalculate instruction lengths without taking nops into account. */
16349 cfun->machine->ignore_hazard_length_p = true;
16350 shorten_branches (get_insns ());
16352 cfun->machine->all_noreorder_p = true;
16354 /* We don't track MIPS16 PC-relative offsets closely enough to make
16355 a good job of "set .noreorder" code in MIPS16 mode. */
16357 cfun->machine->all_noreorder_p = false;
16359 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
16360 if (!TARGET_EXPLICIT_RELOCS)
16361 cfun->machine->all_noreorder_p = false;
16363 /* Profiled functions can't be all noreorder because the profiler
16364 support uses assembler macros. */
16366 cfun->machine->all_noreorder_p = false;
16368 /* Code compiled with -mfix-vr4120, -mfix-rm7000 or -mfix-24k can't be
16369 all noreorder because we rely on the assembler to work around some
16370 errata. The R5900 too has several bugs. */
16371 if (TARGET_FIX_VR4120
16372 || TARGET_FIX_RM7000
16374 || TARGET_MIPS5900)
16375 cfun->machine->all_noreorder_p = false;
16377 /* The same is true for -mfix-vr4130 if we might generate MFLO or
16378 MFHI instructions. Note that we avoid using MFLO and MFHI if
16379 the VR4130 MACC and DMACC instructions are available instead;
16380 see the *mfhilo_{si,di}_macc patterns. */
16381 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
16382 cfun->machine->all_noreorder_p = false;
16384 mips_offset_table htab (37);
16386 /* Make a first pass over the instructions, recording all the LO_SUMs. */
16387 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
16388 FOR_EACH_SUBINSN (subinsn, insn)
16389 if (USEFUL_INSN_P (subinsn))
16391 rtx body = PATTERN (insn);
16392 int noperands = asm_noperands (body);
16393 if (noperands >= 0)
16395 rtx *ops = XALLOCAVEC (rtx, noperands);
16396 bool *used = XALLOCAVEC (bool, noperands);
16397 const char *string = decode_asm_operands (body, ops, NULL, NULL,
16399 get_referenced_operands (string, used, noperands);
16400 for (int i = 0; i < noperands; ++i)
16402 mips_record_lo_sums (ops[i], &htab);
16405 mips_record_lo_sums (PATTERN (subinsn), &htab);
16411 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
16413 /* Make a second pass over the instructions. Delete orphaned
16414 high-part relocations or turn them into NOPs. Avoid hazards
16415 by inserting NOPs. */
16416 for (insn = get_insns (); insn != 0; insn = next_insn)
16418 next_insn = NEXT_INSN (insn);
16419 if (USEFUL_INSN_P (insn))
16421 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
16423 /* If we find an orphaned high-part relocation in a delay
16424 slot, it's easier to turn that instruction into a NOP than
16425 to delete it. The delay slot will be a NOP either way. */
16426 FOR_EACH_SUBINSN (subinsn, insn)
16427 if (INSN_P (subinsn))
16429 if (mips_orphaned_high_part_p (&htab, subinsn))
16431 PATTERN (subinsn) = gen_nop ();
16432 INSN_CODE (subinsn) = CODE_FOR_nop;
16434 mips_avoid_hazard (last_insn, subinsn, &hilo_delay,
16435 &delayed_reg, lo_reg);
16441 /* INSN is a single instruction. Delete it if it's an
16442 orphaned high-part relocation. */
16443 if (mips_orphaned_high_part_p (&htab, insn))
16444 delete_insn (insn);
16445 /* Also delete cache barriers if the last instruction
16446 was an annulled branch. INSN will not be speculatively
16448 else if (recog_memoized (insn) == CODE_FOR_r10k_cache_barrier
16450 && JUMP_P (SEQ_BEGIN (last_insn))
16451 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn)))
16452 delete_insn (insn);
16455 mips_avoid_hazard (last_insn, insn, &hilo_delay,
16456 &delayed_reg, lo_reg);
16464 /* Return true if the function has a long branch instruction. */
16467 mips_has_long_branch_p (void)
16469 rtx_insn *insn, *subinsn;
16472 /* We need up-to-date instruction lengths. */
16473 shorten_branches (get_insns ());
16475 /* Look for a branch that is longer than normal. The normal length for
16476 non-MIPS16 branches is 8, because the length includes the delay slot.
16477 It is 4 for MIPS16, because MIPS16 branches are extended instructions,
16478 but they have no delay slot. */
16479 normal_length = (TARGET_MIPS16 ? 4 : 8);
16480 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
16481 FOR_EACH_SUBINSN (subinsn, insn)
16482 if (JUMP_P (subinsn)
16483 && get_attr_length (subinsn) > normal_length
16484 && (any_condjump_p (subinsn) || any_uncondjump_p (subinsn)))
16490 /* If we are using a GOT, but have not decided to use a global pointer yet,
16491 see whether we need one to implement long branches. Convert the ghost
16492 global-pointer instructions into real ones if so. */
16495 mips_expand_ghost_gp_insns (void)
16497 /* Quick exit if we already know that we will or won't need a
16499 if (!TARGET_USE_GOT
16500 || cfun->machine->global_pointer == INVALID_REGNUM
16501 || mips_must_initialize_gp_p ())
16504 /* Run a full check for long branches. */
16505 if (!mips_has_long_branch_p ())
16508 /* We've now established that we need $gp. */
16509 cfun->machine->must_initialize_gp_p = true;
16510 split_all_insns_noflow ();
16515 /* Subroutine of mips_reorg to manage passes that require DF. */
16518 mips_df_reorg (void)
16520 /* Create def-use chains. */
16521 df_set_flags (DF_EQ_NOTES);
16522 df_chain_add_problem (DF_UD_CHAIN);
16525 if (TARGET_RELAX_PIC_CALLS)
16526 mips_annotate_pic_calls ();
16528 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE)
16529 r10k_insert_cache_barriers ();
16531 df_finish_pass (false);
16534 /* Emit code to load LABEL_REF SRC into MIPS16 register DEST. This is
16535 called very late in mips_reorg, but the caller is required to run
16536 mips16_lay_out_constants on the result. */
16539 mips16_load_branch_target (rtx dest, rtx src)
16541 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
16545 if (mips_cfun_has_cprestore_slot_p ())
16546 mips_emit_move (dest, mips_cprestore_slot (dest, true));
16548 mips_emit_move (dest, pic_offset_table_rtx);
16549 page = mips_unspec_address (src, SYMBOL_GOTOFF_PAGE);
16550 low = mips_unspec_address (src, SYMBOL_GOT_PAGE_OFST);
16551 emit_insn (gen_rtx_SET (VOIDmode, dest,
16552 PMODE_INSN (gen_unspec_got, (dest, page))));
16553 emit_insn (gen_rtx_SET (VOIDmode, dest,
16554 gen_rtx_LO_SUM (Pmode, dest, low)));
16558 src = mips_unspec_address (src, SYMBOL_ABSOLUTE);
16559 mips_emit_move (dest, src);
16563 /* If we're compiling a MIPS16 function, look for and split any long branches.
16564 This must be called after all other instruction modifications in
16568 mips16_split_long_branches (void)
16570 bool something_changed;
16572 if (!TARGET_MIPS16)
16575 /* Loop until the alignments for all targets are sufficient. */
16580 shorten_branches (get_insns ());
16581 something_changed = false;
16582 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
16584 && get_attr_length (insn) > 4
16585 && (any_condjump_p (insn) || any_uncondjump_p (insn)))
16587 rtx old_label, temp, saved_temp;
16588 rtx_code_label *new_label;
16590 rtx_insn *jump, *jump_sequence;
16594 /* Free up a MIPS16 register by saving it in $1. */
16595 saved_temp = gen_rtx_REG (Pmode, AT_REGNUM);
16596 temp = gen_rtx_REG (Pmode, GP_REG_FIRST + 2);
16597 emit_move_insn (saved_temp, temp);
16599 /* Load the branch target into TEMP. */
16600 old_label = JUMP_LABEL (insn);
16601 target = gen_rtx_LABEL_REF (Pmode, old_label);
16602 mips16_load_branch_target (temp, target);
16604 /* Jump to the target and restore the register's
16606 jump = emit_jump_insn (PMODE_INSN (gen_indirect_jump_and_restore,
16607 (temp, temp, saved_temp)));
16608 JUMP_LABEL (jump) = old_label;
16609 LABEL_NUSES (old_label)++;
16611 /* Rewrite any symbolic references that are supposed to use
16612 a PC-relative constant pool. */
16613 mips16_lay_out_constants (false);
16615 if (simplejump_p (insn))
16616 /* We're going to replace INSN with a longer form. */
16620 /* Create a branch-around label for the original
16622 new_label = gen_label_rtx ();
16623 emit_label (new_label);
16626 jump_sequence = get_insns ();
16629 emit_insn_after (jump_sequence, insn);
16631 invert_jump (insn, new_label, false);
16633 delete_insn (insn);
16634 something_changed = true;
16637 while (something_changed);
16640 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
16645 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during
16646 insn splitting in mips16_lay_out_constants, DF insn info is only kept up
16647 to date if the CFG is available. */
16648 if (mips_cfg_in_reorg ())
16649 compute_bb_for_insn ();
16650 mips16_lay_out_constants (true);
16651 if (mips_cfg_in_reorg ())
16654 free_bb_for_insn ();
16658 /* We use a machine specific pass to do a second machine dependent reorg
16659 pass after delay branch scheduling. */
16661 static unsigned int
16662 mips_machine_reorg2 (void)
16664 mips_reorg_process_insns ();
16666 && TARGET_EXPLICIT_RELOCS
16668 && TARGET_VR4130_ALIGN)
16669 vr4130_align_insns ();
16670 if (mips_expand_ghost_gp_insns ())
16671 /* The expansion could invalidate some of the VR4130 alignment
16672 optimizations, but this should be an extremely rare case anyhow. */
16673 mips_reorg_process_insns ();
16674 mips16_split_long_branches ();
16680 const pass_data pass_data_mips_machine_reorg2 =
16682 RTL_PASS, /* type */
16683 "mach2", /* name */
16684 OPTGROUP_NONE, /* optinfo_flags */
16685 TV_MACH_DEP, /* tv_id */
16686 0, /* properties_required */
16687 0, /* properties_provided */
16688 0, /* properties_destroyed */
16689 0, /* todo_flags_start */
16690 0, /* todo_flags_finish */
16693 class pass_mips_machine_reorg2 : public rtl_opt_pass
16696 pass_mips_machine_reorg2(gcc::context *ctxt)
16697 : rtl_opt_pass(pass_data_mips_machine_reorg2, ctxt)
16700 /* opt_pass methods: */
16701 virtual unsigned int execute (function *) { return mips_machine_reorg2 (); }
16703 }; // class pass_mips_machine_reorg2
16705 } // anon namespace
16708 make_pass_mips_machine_reorg2 (gcc::context *ctxt)
16710 return new pass_mips_machine_reorg2 (ctxt);
16714 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
16715 in order to avoid duplicating too much logic from elsewhere. */
16718 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
16719 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
16722 rtx this_rtx, temp1, temp2, fnaddr;
16724 bool use_sibcall_p;
16726 /* Pretend to be a post-reload pass while generating rtl. */
16727 reload_completed = 1;
16729 /* Mark the end of the (empty) prologue. */
16730 emit_note (NOTE_INSN_PROLOGUE_END);
16732 /* Determine if we can use a sibcall to call FUNCTION directly. */
16733 fnaddr = XEXP (DECL_RTL (function), 0);
16734 use_sibcall_p = (mips_function_ok_for_sibcall (function, NULL)
16735 && const_call_insn_operand (fnaddr, Pmode));
16737 /* Determine if we need to load FNADDR from the GOT. */
16739 && (mips_got_symbol_type_p
16740 (mips_classify_symbol (fnaddr, SYMBOL_CONTEXT_LEA))))
16742 /* Pick a global pointer. Use a call-clobbered register if
16743 TARGET_CALL_SAVED_GP. */
16744 cfun->machine->global_pointer
16745 = TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM;
16746 cfun->machine->must_initialize_gp_p = true;
16747 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
16749 /* Set up the global pointer for n32 or n64 abicalls. */
16750 mips_emit_loadgp ();
16753 /* We need two temporary registers in some cases. */
16754 temp1 = gen_rtx_REG (Pmode, 2);
16755 temp2 = gen_rtx_REG (Pmode, 3);
16757 /* Find out which register contains the "this" pointer. */
16758 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
16759 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
16761 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST);
16763 /* Add DELTA to THIS_RTX. */
16766 rtx offset = GEN_INT (delta);
16767 if (!SMALL_OPERAND (delta))
16769 mips_emit_move (temp1, offset);
16772 emit_insn (gen_add3_insn (this_rtx, this_rtx, offset));
16775 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
16776 if (vcall_offset != 0)
16780 /* Set TEMP1 to *THIS_RTX. */
16781 mips_emit_move (temp1, gen_rtx_MEM (Pmode, this_rtx));
16783 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
16784 addr = mips_add_offset (temp2, temp1, vcall_offset);
16786 /* Load the offset and add it to THIS_RTX. */
16787 mips_emit_move (temp1, gen_rtx_MEM (Pmode, addr));
16788 emit_insn (gen_add3_insn (this_rtx, this_rtx, temp1));
16791 /* Jump to the target function. Use a sibcall if direct jumps are
16792 allowed, otherwise load the address into a register first. */
16795 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
16796 SIBLING_CALL_P (insn) = 1;
16800 /* This is messy. GAS treats "la $25,foo" as part of a call
16801 sequence and may allow a global "foo" to be lazily bound.
16802 The general move patterns therefore reject this combination.
16804 In this context, lazy binding would actually be OK
16805 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
16806 TARGET_CALL_SAVED_GP; see mips_load_call_address.
16807 We must therefore load the address via a temporary
16808 register if mips_dangerous_for_la25_p.
16810 If we jump to the temporary register rather than $25,
16811 the assembler can use the move insn to fill the jump's
16814 We can use the same technique for MIPS16 code, where $25
16815 is not a valid JR register. */
16816 if (TARGET_USE_PIC_FN_ADDR_REG
16818 && !mips_dangerous_for_la25_p (fnaddr))
16819 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
16820 mips_load_call_address (MIPS_CALL_SIBCALL, temp1, fnaddr);
16822 if (TARGET_USE_PIC_FN_ADDR_REG
16823 && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
16824 mips_emit_move (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
16825 emit_jump_insn (gen_indirect_jump (temp1));
16828 /* Run just enough of rest_of_compilation. This sequence was
16829 "borrowed" from alpha.c. */
16830 insn = get_insns ();
16831 split_all_insns_noflow ();
16832 mips16_lay_out_constants (true);
16833 shorten_branches (insn);
16834 final_start_function (insn, file, 1);
16835 final (insn, file, 1);
16836 final_end_function ();
16838 /* Clean up the vars set above. Note that final_end_function resets
16839 the global pointer for us. */
16840 reload_completed = 0;
16844 /* The last argument passed to mips_set_compression_mode,
16845 or negative if the function hasn't been called yet. */
16846 static unsigned int old_compression_mode = -1;
16848 /* Set up the target-dependent global state for ISA mode COMPRESSION_MODE,
16849 which is either MASK_MIPS16 or MASK_MICROMIPS. */
16852 mips_set_compression_mode (unsigned int compression_mode)
16855 if (compression_mode == old_compression_mode)
16858 /* Restore base settings of various flags. */
16859 target_flags = mips_base_target_flags;
16860 flag_schedule_insns = mips_base_schedule_insns;
16861 flag_reorder_blocks_and_partition = mips_base_reorder_blocks_and_partition;
16862 flag_move_loop_invariants = mips_base_move_loop_invariants;
16863 align_loops = mips_base_align_loops;
16864 align_jumps = mips_base_align_jumps;
16865 align_functions = mips_base_align_functions;
16866 target_flags &= ~(MASK_MIPS16 | MASK_MICROMIPS);
16867 target_flags |= compression_mode;
16869 if (compression_mode & MASK_MIPS16)
16871 /* Switch to MIPS16 mode. */
16872 target_flags |= MASK_MIPS16;
16874 /* Turn off SYNCI if it was on, MIPS16 doesn't support it. */
16875 target_flags &= ~MASK_SYNCI;
16877 /* Don't run the scheduler before reload, since it tends to
16878 increase register pressure. */
16879 flag_schedule_insns = 0;
16881 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
16882 the whole function to be in a single section. */
16883 flag_reorder_blocks_and_partition = 0;
16885 /* Don't move loop invariants, because it tends to increase
16886 register pressure. It also introduces an extra move in cases
16887 where the constant is the first operand in a two-operand binary
16888 instruction, or when it forms a register argument to a functon
16890 flag_move_loop_invariants = 0;
16892 target_flags |= MASK_EXPLICIT_RELOCS;
16894 /* Experiments suggest we get the best overall section-anchor
16895 results from using the range of an unextended LW or SW. Code
16896 that makes heavy use of byte or short accesses can do better
16897 with ranges of 0...31 and 0...63 respectively, but most code is
16898 sensitive to the range of LW and SW instead. */
16899 targetm.min_anchor_offset = 0;
16900 targetm.max_anchor_offset = 127;
16902 targetm.const_anchor = 0;
16904 /* MIPS16 has no BAL instruction. */
16905 target_flags &= ~MASK_RELAX_PIC_CALLS;
16907 /* The R4000 errata don't apply to any known MIPS16 cores.
16908 It's simpler to make the R4000 fixes and MIPS16 mode
16909 mutually exclusive. */
16910 target_flags &= ~MASK_FIX_R4000;
16912 if (flag_pic && !TARGET_OLDABI)
16913 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
16916 sorry ("MIPS16 -mxgot code");
16918 if (TARGET_HARD_FLOAT_ABI && !TARGET_OLDABI)
16919 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
16923 /* Switch to microMIPS or the standard encoding. */
16925 if (TARGET_MICROMIPS)
16926 /* Avoid branch likely. */
16927 target_flags &= ~MASK_BRANCHLIKELY;
16929 /* Provide default values for align_* for 64-bit targets. */
16932 if (align_loops == 0)
16934 if (align_jumps == 0)
16936 if (align_functions == 0)
16937 align_functions = 8;
16940 targetm.min_anchor_offset = -32768;
16941 targetm.max_anchor_offset = 32767;
16943 targetm.const_anchor = 0x8000;
16946 /* (Re)initialize MIPS target internals for new ISA. */
16947 mips_init_relocs ();
16949 if (compression_mode & MASK_MIPS16)
16951 if (!mips16_globals)
16952 mips16_globals = save_target_globals_default_opts ();
16954 restore_target_globals (mips16_globals);
16957 restore_target_globals (&default_target_globals);
16959 old_compression_mode = compression_mode;
16962 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
16963 function should use the MIPS16 or microMIPS ISA and switch modes
16967 mips_set_current_function (tree fndecl)
16969 mips_set_compression_mode (mips_get_compress_mode (fndecl));
16972 /* Allocate a chunk of memory for per-function machine-dependent data. */
16974 static struct machine_function *
16975 mips_init_machine_status (void)
16977 return ggc_cleared_alloc<machine_function> ();
16980 /* Return the processor associated with the given ISA level, or null
16981 if the ISA isn't valid. */
16983 static const struct mips_cpu_info *
16984 mips_cpu_info_from_isa (int isa)
16988 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
16989 if (mips_cpu_info_table[i].isa == isa)
16990 return mips_cpu_info_table + i;
16995 /* Return a mips_cpu_info entry determined by an option valued
16998 static const struct mips_cpu_info *
16999 mips_cpu_info_from_opt (int opt)
17003 case MIPS_ARCH_OPTION_FROM_ABI:
17004 /* 'from-abi' selects the most compatible architecture for the
17005 given ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit
17006 ABIs. For the EABIs, we have to decide whether we're using
17007 the 32-bit or 64-bit version. */
17008 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
17009 : ABI_NEEDS_64BIT_REGS ? 3
17010 : (TARGET_64BIT ? 3 : 1));
17012 case MIPS_ARCH_OPTION_NATIVE:
17013 gcc_unreachable ();
17016 return &mips_cpu_info_table[opt];
17020 /* Return a default mips_cpu_info entry, given that no -march= option
17021 was explicitly specified. */
17023 static const struct mips_cpu_info *
17024 mips_default_arch (void)
17026 #if defined (MIPS_CPU_STRING_DEFAULT)
17028 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
17029 if (strcmp (mips_cpu_info_table[i].name, MIPS_CPU_STRING_DEFAULT) == 0)
17030 return mips_cpu_info_table + i;
17031 gcc_unreachable ();
17032 #elif defined (MIPS_ISA_DEFAULT)
17033 return mips_cpu_info_from_isa (MIPS_ISA_DEFAULT);
17035 /* 'from-abi' makes a good default: you get whatever the ABI
17037 return mips_cpu_info_from_opt (MIPS_ARCH_OPTION_FROM_ABI);
17041 /* Set up globals to generate code for the ISA or processor
17042 described by INFO. */
17045 mips_set_architecture (const struct mips_cpu_info *info)
17049 mips_arch_info = info;
17050 mips_arch = info->cpu;
17051 mips_isa = info->isa;
17055 mips_isa_rev = (mips_isa & 31) + 1;
17059 /* Likewise for tuning. */
17062 mips_set_tune (const struct mips_cpu_info *info)
17066 mips_tune_info = info;
17067 mips_tune = info->cpu;
17071 /* Implement TARGET_OPTION_OVERRIDE. */
17074 mips_option_override (void)
17076 int i, start, regno, mode;
17078 if (global_options_set.x_mips_isa_option)
17079 mips_isa_option_info = &mips_cpu_info_table[mips_isa_option];
17081 #ifdef SUBTARGET_OVERRIDE_OPTIONS
17082 SUBTARGET_OVERRIDE_OPTIONS;
17085 /* MIPS16 and microMIPS cannot coexist. */
17086 if (TARGET_MICROMIPS && TARGET_MIPS16)
17087 error ("unsupported combination: %s", "-mips16 -mmicromips");
17089 /* Save the base compression state and process flags as though we
17090 were generating uncompressed code. */
17091 mips_base_compression_flags = TARGET_COMPRESSION;
17092 target_flags &= ~TARGET_COMPRESSION;
17094 /* -mno-float overrides -mhard-float and -msoft-float. */
17095 if (TARGET_NO_FLOAT)
17097 target_flags |= MASK_SOFT_FLOAT_ABI;
17098 target_flags_explicit |= MASK_SOFT_FLOAT_ABI;
17101 if (TARGET_FLIP_MIPS16)
17102 TARGET_INTERLINK_COMPRESSED = 1;
17104 /* Set the small data limit. */
17105 mips_small_data_threshold = (global_options_set.x_g_switch_value
17107 : MIPS_DEFAULT_GVALUE);
17109 /* The following code determines the architecture and register size.
17110 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
17111 The GAS and GCC code should be kept in sync as much as possible. */
17113 if (global_options_set.x_mips_arch_option)
17114 mips_set_architecture (mips_cpu_info_from_opt (mips_arch_option));
17116 if (mips_isa_option_info != 0)
17118 if (mips_arch_info == 0)
17119 mips_set_architecture (mips_isa_option_info);
17120 else if (mips_arch_info->isa != mips_isa_option_info->isa)
17121 error ("%<-%s%> conflicts with the other architecture options, "
17122 "which specify a %s processor",
17123 mips_isa_option_info->name,
17124 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
17127 if (mips_arch_info == 0)
17128 mips_set_architecture (mips_default_arch ());
17130 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
17131 error ("%<-march=%s%> is not compatible with the selected ABI",
17132 mips_arch_info->name);
17134 /* Optimize for mips_arch, unless -mtune selects a different processor. */
17135 if (global_options_set.x_mips_tune_option)
17136 mips_set_tune (mips_cpu_info_from_opt (mips_tune_option));
17138 if (mips_tune_info == 0)
17139 mips_set_tune (mips_arch_info);
17141 if ((target_flags_explicit & MASK_64BIT) != 0)
17143 /* The user specified the size of the integer registers. Make sure
17144 it agrees with the ABI and ISA. */
17145 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
17146 error ("%<-mgp64%> used with a 32-bit processor");
17147 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
17148 error ("%<-mgp32%> used with a 64-bit ABI");
17149 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
17150 error ("%<-mgp64%> used with a 32-bit ABI");
17154 /* Infer the integer register size from the ABI and processor.
17155 Restrict ourselves to 32-bit registers if that's all the
17156 processor has, or if the ABI cannot handle 64-bit registers. */
17157 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
17158 target_flags &= ~MASK_64BIT;
17160 target_flags |= MASK_64BIT;
17163 if ((target_flags_explicit & MASK_FLOAT64) != 0)
17165 if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
17166 error ("unsupported combination: %s", "-mfp64 -msingle-float");
17167 else if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
17168 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
17169 else if (!TARGET_64BIT && TARGET_FLOAT64)
17171 if (!ISA_HAS_MXHC1)
17172 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
17173 " the target supports the mfhc1 and mthc1 instructions");
17174 else if (mips_abi != ABI_32)
17175 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
17181 /* -msingle-float selects 32-bit float registers. Otherwise the
17182 float registers should be the same size as the integer ones. */
17183 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
17184 target_flags |= MASK_FLOAT64;
17186 target_flags &= ~MASK_FLOAT64;
17189 if (mips_abi != ABI_32 && TARGET_FLOATXX)
17190 error ("%<-mfpxx%> can only be used with the o32 ABI");
17191 else if (ISA_MIPS1 && !TARGET_FLOAT32)
17192 error ("%<-march=%s%> requires %<-mfp32%>", mips_arch_info->name);
17193 else if (TARGET_FLOATXX && !mips_lra_flag)
17194 error ("%<-mfpxx%> requires %<-mlra%>");
17196 /* End of code shared with GAS. */
17198 /* The R5900 FPU only supports single precision. */
17199 if (TARGET_MIPS5900 && TARGET_HARD_FLOAT_ABI && TARGET_DOUBLE_FLOAT)
17200 error ("unsupported combination: %s",
17201 "-march=r5900 -mhard-float -mdouble-float");
17203 /* If a -mlong* option was given, check that it matches the ABI,
17204 otherwise infer the -mlong* setting from the other options. */
17205 if ((target_flags_explicit & MASK_LONG64) != 0)
17209 if (mips_abi == ABI_N32)
17210 error ("%qs is incompatible with %qs", "-mabi=n32", "-mlong64");
17211 else if (mips_abi == ABI_32)
17212 error ("%qs is incompatible with %qs", "-mabi=32", "-mlong64");
17213 else if (mips_abi == ABI_O64 && TARGET_ABICALLS)
17214 /* We have traditionally allowed non-abicalls code to use
17215 an LP64 form of o64. However, it would take a bit more
17216 effort to support the combination of 32-bit GOT entries
17217 and 64-bit pointers, so we treat the abicalls case as
17219 error ("the combination of %qs and %qs is incompatible with %qs",
17220 "-mabi=o64", "-mabicalls", "-mlong64");
17224 if (mips_abi == ABI_64)
17225 error ("%qs is incompatible with %qs", "-mabi=64", "-mlong32");
17230 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
17231 target_flags |= MASK_LONG64;
17233 target_flags &= ~MASK_LONG64;
17236 if (!TARGET_OLDABI)
17237 flag_pcc_struct_return = 0;
17239 /* Decide which rtx_costs structure to use. */
17241 mips_cost = &mips_rtx_cost_optimize_size;
17243 mips_cost = &mips_rtx_cost_data[mips_tune];
17245 /* If the user hasn't specified a branch cost, use the processor's
17247 if (mips_branch_cost == 0)
17248 mips_branch_cost = mips_cost->branch_cost;
17250 /* If neither -mbranch-likely nor -mno-branch-likely was given
17251 on the command line, set MASK_BRANCHLIKELY based on the target
17252 architecture and tuning flags. Annulled delay slots are a
17253 size win, so we only consider the processor-specific tuning
17254 for !optimize_size. */
17255 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
17257 if (ISA_HAS_BRANCHLIKELY
17259 || (mips_tune_info->tune_flags & PTF_AVOID_BRANCHLIKELY) == 0))
17260 target_flags |= MASK_BRANCHLIKELY;
17262 target_flags &= ~MASK_BRANCHLIKELY;
17264 else if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
17265 warning (0, "the %qs architecture does not support branch-likely"
17266 " instructions", mips_arch_info->name);
17268 /* If the user hasn't specified -mimadd or -mno-imadd set
17269 MASK_IMADD based on the target architecture and tuning
17271 if ((target_flags_explicit & MASK_IMADD) == 0)
17273 if (ISA_HAS_MADD_MSUB &&
17274 (mips_tune_info->tune_flags & PTF_AVOID_IMADD) == 0)
17275 target_flags |= MASK_IMADD;
17277 target_flags &= ~MASK_IMADD;
17279 else if (TARGET_IMADD && !ISA_HAS_MADD_MSUB)
17280 warning (0, "the %qs architecture does not support madd or msub"
17281 " instructions", mips_arch_info->name);
17283 /* If neither -modd-spreg nor -mno-odd-spreg was given on the command
17284 line, set MASK_ODD_SPREG based on the ISA and ABI. */
17285 if ((target_flags_explicit & MASK_ODD_SPREG) == 0)
17287 /* Disable TARGET_ODD_SPREG when using the o32 FPXX ABI. */
17288 if (!ISA_HAS_ODD_SPREG || TARGET_FLOATXX)
17289 target_flags &= ~MASK_ODD_SPREG;
17291 target_flags |= MASK_ODD_SPREG;
17293 else if (TARGET_ODD_SPREG && !ISA_HAS_ODD_SPREG)
17294 warning (0, "the %qs architecture does not support odd single-precision"
17295 " registers", mips_arch_info->name);
17297 if (!TARGET_ODD_SPREG && TARGET_64BIT)
17299 error ("unsupported combination: %s", "-mgp64 -mno-odd-spreg");
17300 /* Allow compilation to continue further even though invalid output
17301 will be produced. */
17302 target_flags |= MASK_ODD_SPREG;
17305 /* The effect of -mabicalls isn't defined for the EABI. */
17306 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
17308 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
17309 target_flags &= ~MASK_ABICALLS;
17312 /* PIC requires -mabicalls. */
17315 if (mips_abi == ABI_EABI)
17316 error ("cannot generate position-independent code for %qs",
17318 else if (!TARGET_ABICALLS)
17319 error ("position-independent code requires %qs", "-mabicalls");
17322 if (TARGET_ABICALLS_PIC2)
17323 /* We need to set flag_pic for executables as well as DSOs
17324 because we may reference symbols that are not defined in
17325 the final executable. (MIPS does not use things like
17326 copy relocs, for example.)
17328 There is a body of code that uses __PIC__ to distinguish
17329 between -mabicalls and -mno-abicalls code. The non-__PIC__
17330 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
17331 long as any indirect jumps use $25. */
17334 /* -mvr4130-align is a "speed over size" optimization: it usually produces
17335 faster code, but at the expense of more nops. Enable it at -O3 and
17337 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
17338 target_flags |= MASK_VR4130_ALIGN;
17340 /* Prefer a call to memcpy over inline code when optimizing for size,
17341 though see MOVE_RATIO in mips.h. */
17342 if (optimize_size && (target_flags_explicit & MASK_MEMCPY) == 0)
17343 target_flags |= MASK_MEMCPY;
17345 /* If we have a nonzero small-data limit, check that the -mgpopt
17346 setting is consistent with the other target flags. */
17347 if (mips_small_data_threshold > 0)
17351 if (!TARGET_EXPLICIT_RELOCS)
17352 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
17354 TARGET_LOCAL_SDATA = false;
17355 TARGET_EXTERN_SDATA = false;
17359 if (TARGET_VXWORKS_RTP)
17360 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
17362 if (TARGET_ABICALLS)
17363 warning (0, "cannot use small-data accesses for %qs",
17368 /* Pre-IEEE 754-2008 MIPS hardware has a quirky almost-IEEE format
17369 for all its floating point. */
17370 if (mips_nan != MIPS_IEEE_754_2008)
17372 REAL_MODE_FORMAT (SFmode) = &mips_single_format;
17373 REAL_MODE_FORMAT (DFmode) = &mips_double_format;
17374 REAL_MODE_FORMAT (TFmode) = &mips_quad_format;
17377 /* Make sure that the user didn't turn off paired single support when
17378 MIPS-3D support is requested. */
17380 && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
17381 && !TARGET_PAIRED_SINGLE_FLOAT)
17382 error ("%<-mips3d%> requires %<-mpaired-single%>");
17384 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
17386 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
17388 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
17389 and TARGET_HARD_FLOAT_ABI are both true. */
17390 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT_ABI))
17392 error ("%qs must be used with %qs",
17393 TARGET_MIPS3D ? "-mips3d" : "-mpaired-single",
17394 TARGET_HARD_FLOAT_ABI ? "-mfp64" : "-mhard-float");
17395 target_flags &= ~MASK_PAIRED_SINGLE_FLOAT;
17399 /* Make sure that -mpaired-single is only used on ISAs that support it.
17400 We must disable it otherwise since it relies on other ISA properties
17401 like ISA_HAS_8CC having their normal values. */
17402 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_HAS_PAIRED_SINGLE)
17404 error ("the %qs architecture does not support paired-single"
17405 " instructions", mips_arch_info->name);
17406 target_flags &= ~MASK_PAIRED_SINGLE_FLOAT;
17410 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
17411 && !TARGET_CACHE_BUILTIN)
17413 error ("%qs requires a target that provides the %qs instruction",
17414 "-mr10k-cache-barrier", "cache");
17415 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE;
17418 /* If TARGET_DSPR2, enable TARGET_DSP. */
17422 /* .eh_frame addresses should be the same width as a C pointer.
17423 Most MIPS ABIs support only one pointer size, so the assembler
17424 will usually know exactly how big an .eh_frame address is.
17426 Unfortunately, this is not true of the 64-bit EABI. The ABI was
17427 originally defined to use 64-bit pointers (i.e. it is LP64), and
17428 this is still the default mode. However, we also support an n32-like
17429 ILP32 mode, which is selected by -mlong32. The problem is that the
17430 assembler has traditionally not had an -mlong option, so it has
17431 traditionally not known whether we're using the ILP32 or LP64 form.
17433 As it happens, gas versions up to and including 2.19 use _32-bit_
17434 addresses for EABI64 .cfi_* directives. This is wrong for the
17435 default LP64 mode, so we can't use the directives by default.
17436 Moreover, since gas's current behavior is at odds with gcc's
17437 default behavior, it seems unwise to rely on future versions
17438 of gas behaving the same way. We therefore avoid using .cfi
17439 directives for -mlong32 as well. */
17440 if (mips_abi == ABI_EABI && TARGET_64BIT)
17441 flag_dwarf2_cfi_asm = 0;
17443 /* .cfi_* directives generate a read-only section, so fall back on
17444 manual .eh_frame creation if we need the section to be writable. */
17445 if (TARGET_WRITABLE_EH_FRAME)
17446 flag_dwarf2_cfi_asm = 0;
17448 mips_init_print_operand_punct ();
17450 /* Set up array to map GCC register number to debug register number.
17451 Ignore the special purpose register numbers. */
17453 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
17455 mips_dbx_regno[i] = IGNORED_DWARF_REGNUM;
17456 if (GP_REG_P (i) || FP_REG_P (i) || ALL_COP_REG_P (i))
17457 mips_dwarf_regno[i] = i;
17459 mips_dwarf_regno[i] = INVALID_REGNUM;
17462 start = GP_DBX_FIRST - GP_REG_FIRST;
17463 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
17464 mips_dbx_regno[i] = i + start;
17466 start = FP_DBX_FIRST - FP_REG_FIRST;
17467 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
17468 mips_dbx_regno[i] = i + start;
17470 /* Accumulator debug registers use big-endian ordering. */
17471 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
17472 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
17473 mips_dwarf_regno[HI_REGNUM] = MD_REG_FIRST + 0;
17474 mips_dwarf_regno[LO_REGNUM] = MD_REG_FIRST + 1;
17475 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
17477 mips_dwarf_regno[i + TARGET_LITTLE_ENDIAN] = i;
17478 mips_dwarf_regno[i + TARGET_BIG_ENDIAN] = i + 1;
17481 /* Set up mips_hard_regno_mode_ok. */
17482 for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
17483 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
17484 mips_hard_regno_mode_ok[mode][regno]
17485 = mips_hard_regno_mode_ok_p (regno, (machine_mode) mode);
17487 /* Function to allocate machine-dependent function status. */
17488 init_machine_status = &mips_init_machine_status;
17490 /* Default to working around R4000 errata only if the processor
17491 was selected explicitly. */
17492 if ((target_flags_explicit & MASK_FIX_R4000) == 0
17493 && strcmp (mips_arch_info->name, "r4000") == 0)
17494 target_flags |= MASK_FIX_R4000;
17496 /* Default to working around R4400 errata only if the processor
17497 was selected explicitly. */
17498 if ((target_flags_explicit & MASK_FIX_R4400) == 0
17499 && strcmp (mips_arch_info->name, "r4400") == 0)
17500 target_flags |= MASK_FIX_R4400;
17502 /* Default to working around R10000 errata only if the processor
17503 was selected explicitly. */
17504 if ((target_flags_explicit & MASK_FIX_R10000) == 0
17505 && strcmp (mips_arch_info->name, "r10000") == 0)
17506 target_flags |= MASK_FIX_R10000;
17508 /* Make sure that branch-likely instructions available when using
17509 -mfix-r10000. The instructions are not available if either:
17511 1. -mno-branch-likely was passed.
17512 2. The selected ISA does not support branch-likely and
17513 the command line does not include -mbranch-likely. */
17514 if (TARGET_FIX_R10000
17515 && ((target_flags_explicit & MASK_BRANCHLIKELY) == 0
17516 ? !ISA_HAS_BRANCHLIKELY
17517 : !TARGET_BRANCHLIKELY))
17518 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
17520 if (TARGET_SYNCI && !ISA_HAS_SYNCI)
17522 warning (0, "the %qs architecture does not support the synci "
17523 "instruction", mips_arch_info->name);
17524 target_flags &= ~MASK_SYNCI;
17527 /* Only optimize PIC indirect calls if they are actually required. */
17528 if (!TARGET_USE_GOT || !TARGET_EXPLICIT_RELOCS)
17529 target_flags &= ~MASK_RELAX_PIC_CALLS;
17531 /* Save base state of options. */
17532 mips_base_target_flags = target_flags;
17533 mips_base_schedule_insns = flag_schedule_insns;
17534 mips_base_reorder_blocks_and_partition = flag_reorder_blocks_and_partition;
17535 mips_base_move_loop_invariants = flag_move_loop_invariants;
17536 mips_base_align_loops = align_loops;
17537 mips_base_align_jumps = align_jumps;
17538 mips_base_align_functions = align_functions;
17540 /* Now select the ISA mode.
17542 Do all CPP-sensitive stuff in uncompressed mode; we'll switch modes
17543 later if required. */
17544 mips_set_compression_mode (0);
17546 /* We register a second machine specific reorg pass after delay slot
17547 filling. Registering the pass must be done at start up. It's
17548 convenient to do it here. */
17549 opt_pass *new_pass = make_pass_mips_machine_reorg2 (g);
17550 struct register_pass_info insert_pass_mips_machine_reorg2 =
17552 new_pass, /* pass */
17553 "dbr", /* reference_pass_name */
17554 1, /* ref_pass_instance_number */
17555 PASS_POS_INSERT_AFTER /* po_op */
17557 register_pass (&insert_pass_mips_machine_reorg2);
17559 if (TARGET_HARD_FLOAT_ABI && TARGET_MIPS5900)
17560 REAL_MODE_FORMAT (SFmode) = &spu_single_format;
17563 /* Swap the register information for registers I and I + 1, which
17564 currently have the wrong endianness. Note that the registers'
17565 fixedness and call-clobberedness might have been set on the
17569 mips_swap_registers (unsigned int i)
17574 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
17575 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
17577 SWAP_INT (fixed_regs[i], fixed_regs[i + 1]);
17578 SWAP_INT (call_used_regs[i], call_used_regs[i + 1]);
17579 SWAP_INT (call_really_used_regs[i], call_really_used_regs[i + 1]);
17580 SWAP_STRING (reg_names[i], reg_names[i + 1]);
17586 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
17589 mips_conditional_register_usage (void)
17594 /* These DSP control register fields are global. */
17595 global_regs[CCDSP_PO_REGNUM] = 1;
17596 global_regs[CCDSP_SC_REGNUM] = 1;
17599 AND_COMPL_HARD_REG_SET (accessible_reg_set,
17600 reg_class_contents[(int) DSP_ACC_REGS]);
17602 if (!TARGET_HARD_FLOAT)
17604 AND_COMPL_HARD_REG_SET (accessible_reg_set,
17605 reg_class_contents[(int) FP_REGS]);
17606 AND_COMPL_HARD_REG_SET (accessible_reg_set,
17607 reg_class_contents[(int) ST_REGS]);
17609 else if (!ISA_HAS_8CC)
17611 /* We only have a single condition-code register. We implement
17612 this by fixing all the condition-code registers and generating
17613 RTL that refers directly to ST_REG_FIRST. */
17614 AND_COMPL_HARD_REG_SET (accessible_reg_set,
17615 reg_class_contents[(int) ST_REGS]);
17616 SET_HARD_REG_BIT (accessible_reg_set, FPSW_REGNUM);
17617 fixed_regs[FPSW_REGNUM] = call_used_regs[FPSW_REGNUM] = 1;
17621 /* In MIPS16 mode, we prohibit the unused $s registers, since they
17622 are call-saved, and saving them via a MIPS16 register would
17623 probably waste more time than just reloading the value.
17625 We permit the $t temporary registers when optimizing for speed
17626 but not when optimizing for space because using them results in
17627 code that is larger (but faster) then not using them. We do
17628 allow $24 (t8) because it is used in CMP and CMPI instructions
17629 and $25 (t9) because it is used as the function call address in
17632 fixed_regs[18] = call_used_regs[18] = 1;
17633 fixed_regs[19] = call_used_regs[19] = 1;
17634 fixed_regs[20] = call_used_regs[20] = 1;
17635 fixed_regs[21] = call_used_regs[21] = 1;
17636 fixed_regs[22] = call_used_regs[22] = 1;
17637 fixed_regs[23] = call_used_regs[23] = 1;
17638 fixed_regs[26] = call_used_regs[26] = 1;
17639 fixed_regs[27] = call_used_regs[27] = 1;
17640 fixed_regs[30] = call_used_regs[30] = 1;
17643 fixed_regs[8] = call_used_regs[8] = 1;
17644 fixed_regs[9] = call_used_regs[9] = 1;
17645 fixed_regs[10] = call_used_regs[10] = 1;
17646 fixed_regs[11] = call_used_regs[11] = 1;
17647 fixed_regs[12] = call_used_regs[12] = 1;
17648 fixed_regs[13] = call_used_regs[13] = 1;
17649 fixed_regs[14] = call_used_regs[14] = 1;
17650 fixed_regs[15] = call_used_regs[15] = 1;
17653 /* Do not allow HI and LO to be treated as register operands.
17654 There are no MTHI or MTLO instructions (or any real need
17655 for them) and one-way registers cannot easily be reloaded. */
17656 AND_COMPL_HARD_REG_SET (operand_reg_set,
17657 reg_class_contents[(int) MD_REGS]);
17659 /* $f20-$f23 are call-clobbered for n64. */
17660 if (mips_abi == ABI_64)
17663 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
17664 call_really_used_regs[regno] = call_used_regs[regno] = 1;
17666 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
17667 for n32 and o32 FP64. */
17668 if (mips_abi == ABI_N32
17669 || (mips_abi == ABI_32
17670 && TARGET_FLOAT64))
17673 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
17674 call_really_used_regs[regno] = call_used_regs[regno] = 1;
17676 /* Make sure that double-register accumulator values are correctly
17677 ordered for the current endianness. */
17678 if (TARGET_LITTLE_ENDIAN)
17680 unsigned int regno;
17682 mips_swap_registers (MD_REG_FIRST);
17683 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno += 2)
17684 mips_swap_registers (regno);
17688 /* Implement EH_USES. */
17691 mips_eh_uses (unsigned int regno)
17693 if (reload_completed && !TARGET_ABSOLUTE_JUMPS)
17695 /* We need to force certain registers to be live in order to handle
17696 PIC long branches correctly. See mips_must_initialize_gp_p for
17698 if (mips_cfun_has_cprestore_slot_p ())
17700 if (regno == CPRESTORE_SLOT_REGNUM)
17705 if (cfun->machine->global_pointer == regno)
17713 /* Implement EPILOGUE_USES. */
17716 mips_epilogue_uses (unsigned int regno)
17718 /* Say that the epilogue uses the return address register. Note that
17719 in the case of sibcalls, the values "used by the epilogue" are
17720 considered live at the start of the called function. */
17721 if (regno == RETURN_ADDR_REGNUM)
17724 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
17725 See the comment above load_call<mode> for details. */
17726 if (TARGET_USE_GOT && (regno) == GOT_VERSION_REGNUM)
17729 /* An interrupt handler must preserve some registers that are
17730 ordinarily call-clobbered. */
17731 if (cfun->machine->interrupt_handler_p
17732 && mips_interrupt_extra_call_saved_reg_p (regno))
17738 /* Return true if INSN needs to be wrapped in ".set noat".
17739 INSN has NOPERANDS operands, stored in OPVEC. */
17742 mips_need_noat_wrapper_p (rtx_insn *insn, rtx *opvec, int noperands)
17744 if (recog_memoized (insn) >= 0)
17746 subrtx_iterator::array_type array;
17747 for (int i = 0; i < noperands; i++)
17748 FOR_EACH_SUBRTX (iter, array, opvec[i], NONCONST)
17749 if (REG_P (*iter) && REGNO (*iter) == AT_REGNUM)
17755 /* Implement FINAL_PRESCAN_INSN. */
17758 mips_final_prescan_insn (rtx_insn *insn, rtx *opvec, int noperands)
17760 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
17761 mips_push_asm_switch (&mips_noat);
17764 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */
17767 mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED, rtx_insn *insn,
17768 rtx *opvec, int noperands)
17770 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
17771 mips_pop_asm_switch (&mips_noat);
17774 /* Return the function that is used to expand the <u>mulsidi3 pattern.
17775 EXT_CODE is the code of the extension used. Return NULL if widening
17776 multiplication shouldn't be used. */
17779 mips_mulsidi3_gen_fn (enum rtx_code ext_code)
17783 signed_p = ext_code == SIGN_EXTEND;
17786 /* Don't use widening multiplication with MULT when we have DMUL. Even
17787 with the extension of its input operands DMUL is faster. Note that
17788 the extension is not needed for signed multiplication. In order to
17789 ensure that we always remove the redundant sign-extension in this
17790 case we still expand mulsidi3 for DMUL. */
17792 return signed_p ? gen_mulsidi3_64bit_dmul : NULL;
17795 ? gen_mulsidi3_64bit_mips16
17796 : gen_umulsidi3_64bit_mips16);
17797 if (TARGET_FIX_R4000)
17799 return signed_p ? gen_mulsidi3_64bit : gen_umulsidi3_64bit;
17805 ? gen_mulsidi3_32bit_mips16
17806 : gen_umulsidi3_32bit_mips16);
17807 if (TARGET_FIX_R4000 && !ISA_HAS_DSP)
17808 return signed_p ? gen_mulsidi3_32bit_r4000 : gen_umulsidi3_32bit_r4000;
17809 return signed_p ? gen_mulsidi3_32bit : gen_umulsidi3_32bit;
17813 /* Return true if PATTERN matches the kind of instruction generated by
17814 umips_build_save_restore. SAVE_P is true for store. */
17817 umips_save_restore_pattern_p (bool save_p, rtx pattern)
17821 HOST_WIDE_INT first_offset = 0;
17822 rtx first_base = 0;
17823 unsigned int regmask = 0;
17825 for (n = 0; n < XVECLEN (pattern, 0); n++)
17827 rtx set, reg, mem, this_base;
17828 HOST_WIDE_INT this_offset;
17830 /* Check that we have a SET. */
17831 set = XVECEXP (pattern, 0, n);
17832 if (GET_CODE (set) != SET)
17835 /* Check that the SET is a load (if restoring) or a store
17837 mem = save_p ? SET_DEST (set) : SET_SRC (set);
17838 if (!MEM_P (mem) || MEM_VOLATILE_P (mem))
17841 /* Check that the address is the sum of base and a possibly-zero
17842 constant offset. Determine if the offset is in range. */
17843 mips_split_plus (XEXP (mem, 0), &this_base, &this_offset);
17844 if (!REG_P (this_base))
17849 if (!UMIPS_12BIT_OFFSET_P (this_offset))
17851 first_base = this_base;
17852 first_offset = this_offset;
17856 /* Check that the save slots are consecutive. */
17857 if (REGNO (this_base) != REGNO (first_base)
17858 || this_offset != first_offset + UNITS_PER_WORD * n)
17862 /* Check that SET's other operand is a register. */
17863 reg = save_p ? SET_SRC (set) : SET_DEST (set);
17867 regmask |= 1 << REGNO (reg);
17870 for (i = 0; i < ARRAY_SIZE (umips_swm_mask); i++)
17871 if (regmask == umips_swm_mask[i])
17877 /* Return the assembly instruction for microMIPS LWM or SWM.
17878 SAVE_P and PATTERN are as for umips_save_restore_pattern_p. */
17881 umips_output_save_restore (bool save_p, rtx pattern)
17883 static char buffer[300];
17886 HOST_WIDE_INT offset;
17887 rtx base, mem, set, last_set, last_reg;
17889 /* Parse the pattern. */
17890 gcc_assert (umips_save_restore_pattern_p (save_p, pattern));
17892 s = strcpy (buffer, save_p ? "swm\t" : "lwm\t");
17894 n = XVECLEN (pattern, 0);
17896 set = XVECEXP (pattern, 0, 0);
17897 mem = save_p ? SET_DEST (set) : SET_SRC (set);
17898 mips_split_plus (XEXP (mem, 0), &base, &offset);
17900 last_set = XVECEXP (pattern, 0, n - 1);
17901 last_reg = save_p ? SET_SRC (last_set) : SET_DEST (last_set);
17903 if (REGNO (last_reg) == 31)
17906 gcc_assert (n <= 9);
17910 s += sprintf (s, "%s,", reg_names[16]);
17912 s += sprintf (s, "%s-%s,", reg_names[16], reg_names[15 + n]);
17914 s += sprintf (s, "%s-%s,%s,", reg_names[16], reg_names[23],
17917 if (REGNO (last_reg) == 31)
17918 s += sprintf (s, "%s,", reg_names[31]);
17920 s += sprintf (s, "%d(%s)", (int)offset, reg_names[REGNO (base)]);
17924 /* Return true if MEM1 and MEM2 use the same base register, and the
17925 offset of MEM2 equals the offset of MEM1 plus 4. FIRST_REG is the
17926 register into (from) which the contents of MEM1 will be loaded
17927 (stored), depending on the value of LOAD_P.
17928 SWAP_P is true when the 1st and 2nd instructions are swapped. */
17931 umips_load_store_pair_p_1 (bool load_p, bool swap_p,
17932 rtx first_reg, rtx mem1, rtx mem2)
17935 HOST_WIDE_INT offset1, offset2;
17937 if (!MEM_P (mem1) || !MEM_P (mem2))
17940 mips_split_plus (XEXP (mem1, 0), &base1, &offset1);
17941 mips_split_plus (XEXP (mem2, 0), &base2, &offset2);
17943 if (!REG_P (base1) || !rtx_equal_p (base1, base2))
17946 /* Avoid invalid load pair instructions. */
17947 if (load_p && REGNO (first_reg) == REGNO (base1))
17950 /* We must avoid this case for anti-dependence.
17953 first_reg is $2, but the base is $3. */
17956 && REGNO (first_reg) + 1 == REGNO (base1))
17959 if (offset2 != offset1 + 4)
17962 if (!UMIPS_12BIT_OFFSET_P (offset1))
17968 /* OPERANDS describes the operands to a pair of SETs, in the order
17969 dest1, src1, dest2, src2. Return true if the operands can be used
17970 in an LWP or SWP instruction; LOAD_P says which. */
17973 umips_load_store_pair_p (bool load_p, rtx *operands)
17975 rtx reg1, reg2, mem1, mem2;
17979 reg1 = operands[0];
17980 reg2 = operands[2];
17981 mem1 = operands[1];
17982 mem2 = operands[3];
17986 reg1 = operands[1];
17987 reg2 = operands[3];
17988 mem1 = operands[0];
17989 mem2 = operands[2];
17992 if (REGNO (reg2) == REGNO (reg1) + 1)
17993 return umips_load_store_pair_p_1 (load_p, false, reg1, mem1, mem2);
17995 if (REGNO (reg1) == REGNO (reg2) + 1)
17996 return umips_load_store_pair_p_1 (load_p, true, reg2, mem2, mem1);
18001 /* Return the assembly instruction for a microMIPS LWP or SWP in which
18002 the first register is REG and the first memory slot is MEM.
18003 LOAD_P is true for LWP. */
18006 umips_output_load_store_pair_1 (bool load_p, rtx reg, rtx mem)
18008 rtx ops[] = {reg, mem};
18011 output_asm_insn ("lwp\t%0,%1", ops);
18013 output_asm_insn ("swp\t%0,%1", ops);
18016 /* Output the assembly instruction for a microMIPS LWP or SWP instruction.
18017 LOAD_P and OPERANDS are as for umips_load_store_pair_p. */
18020 umips_output_load_store_pair (bool load_p, rtx *operands)
18022 rtx reg1, reg2, mem1, mem2;
18025 reg1 = operands[0];
18026 reg2 = operands[2];
18027 mem1 = operands[1];
18028 mem2 = operands[3];
18032 reg1 = operands[1];
18033 reg2 = operands[3];
18034 mem1 = operands[0];
18035 mem2 = operands[2];
18038 if (REGNO (reg2) == REGNO (reg1) + 1)
18040 umips_output_load_store_pair_1 (load_p, reg1, mem1);
18044 gcc_assert (REGNO (reg1) == REGNO (reg2) + 1);
18045 umips_output_load_store_pair_1 (load_p, reg2, mem2);
18048 /* Return true if REG1 and REG2 match the criteria for a movep insn. */
18051 umips_movep_target_p (rtx reg1, rtx reg2)
18053 int regno1, regno2, pair;
18055 static const int match[8] = {
18056 0x00000060, /* 5, 6 */
18057 0x000000a0, /* 5, 7 */
18058 0x000000c0, /* 6, 7 */
18059 0x00200010, /* 4, 21 */
18060 0x00400010, /* 4, 22 */
18061 0x00000030, /* 4, 5 */
18062 0x00000050, /* 4, 6 */
18063 0x00000090 /* 4, 7 */
18066 if (!REG_P (reg1) || !REG_P (reg2))
18069 regno1 = REGNO (reg1);
18070 regno2 = REGNO (reg2);
18072 if (!GP_REG_P (regno1) || !GP_REG_P (regno2))
18075 pair = (1 << regno1) | (1 << regno2);
18077 for (i = 0; i < ARRAY_SIZE (match); i++)
18078 if (pair == match[i])
18084 /* Return the size in bytes of the trampoline code, padded to
18085 TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target
18086 function address immediately follow. */
18089 mips_trampoline_code_size (void)
18091 if (TARGET_USE_PIC_FN_ADDR_REG)
18093 else if (ptr_mode == DImode)
18095 else if (ISA_HAS_LOAD_DELAY)
18101 /* Implement TARGET_TRAMPOLINE_INIT. */
18104 mips_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
18106 rtx addr, end_addr, high, low, opcode, mem;
18109 HOST_WIDE_INT end_addr_offset, static_chain_offset, target_function_offset;
18111 /* Work out the offsets of the pointers from the start of the
18112 trampoline code. */
18113 end_addr_offset = mips_trampoline_code_size ();
18114 static_chain_offset = end_addr_offset;
18115 target_function_offset = static_chain_offset + GET_MODE_SIZE (ptr_mode);
18117 /* Get pointers to the beginning and end of the code block. */
18118 addr = force_reg (Pmode, XEXP (m_tramp, 0));
18119 end_addr = mips_force_binary (Pmode, PLUS, addr, GEN_INT (end_addr_offset));
18121 #define OP(X) gen_int_mode (X, SImode)
18123 /* Build up the code in TRAMPOLINE. */
18125 if (TARGET_USE_PIC_FN_ADDR_REG)
18127 /* $25 contains the address of the trampoline. Emit code of the form:
18129 l[wd] $1, target_function_offset($25)
18130 l[wd] $static_chain, static_chain_offset($25)
18133 trampoline[i++] = OP (MIPS_LOAD_PTR (AT_REGNUM,
18134 target_function_offset,
18135 PIC_FUNCTION_ADDR_REGNUM));
18136 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
18137 static_chain_offset,
18138 PIC_FUNCTION_ADDR_REGNUM));
18139 trampoline[i++] = OP (MIPS_JR (AT_REGNUM));
18140 trampoline[i++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM, AT_REGNUM));
18142 else if (ptr_mode == DImode)
18144 /* It's too cumbersome to create the full 64-bit address, so let's
18150 1: l[wd] $25, target_function_offset - 12($31)
18151 l[wd] $static_chain, static_chain_offset - 12($31)
18155 where 12 is the offset of "1:" from the start of the code block. */
18156 trampoline[i++] = OP (MIPS_MOVE (AT_REGNUM, RETURN_ADDR_REGNUM));
18157 trampoline[i++] = OP (MIPS_BAL (1));
18158 trampoline[i++] = OP (MIPS_NOP);
18159 trampoline[i++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
18160 target_function_offset - 12,
18161 RETURN_ADDR_REGNUM));
18162 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
18163 static_chain_offset - 12,
18164 RETURN_ADDR_REGNUM));
18165 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
18166 trampoline[i++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM, AT_REGNUM));
18170 /* If the target has load delays, emit:
18172 lui $1, %hi(end_addr)
18173 lw $25, %lo(end_addr + ...)($1)
18174 lw $static_chain, %lo(end_addr + ...)($1)
18180 lui $1, %hi(end_addr)
18181 lw $25, %lo(end_addr + ...)($1)
18183 lw $static_chain, %lo(end_addr + ...)($1). */
18185 /* Split END_ADDR into %hi and %lo values. Trampolines are aligned
18186 to 64 bits, so the %lo value will have the bottom 3 bits clear. */
18187 high = expand_simple_binop (SImode, PLUS, end_addr, GEN_INT (0x8000),
18188 NULL, false, OPTAB_WIDEN);
18189 high = expand_simple_binop (SImode, LSHIFTRT, high, GEN_INT (16),
18190 NULL, false, OPTAB_WIDEN);
18191 low = convert_to_mode (SImode, gen_lowpart (HImode, end_addr), true);
18193 /* Emit the LUI. */
18194 opcode = OP (MIPS_LUI (AT_REGNUM, 0));
18195 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, high,
18196 NULL, false, OPTAB_WIDEN);
18198 /* Emit the load of the target function. */
18199 opcode = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
18200 target_function_offset - end_addr_offset,
18202 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
18203 NULL, false, OPTAB_WIDEN);
18205 /* Emit the JR here, if we can. */
18206 if (!ISA_HAS_LOAD_DELAY)
18207 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
18209 /* Emit the load of the static chain register. */
18210 opcode = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
18211 static_chain_offset - end_addr_offset,
18213 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
18214 NULL, false, OPTAB_WIDEN);
18216 /* Emit the JR, if we couldn't above. */
18217 if (ISA_HAS_LOAD_DELAY)
18219 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
18220 trampoline[i++] = OP (MIPS_NOP);
18226 /* Copy the trampoline code. Leave any padding uninitialized. */
18227 for (j = 0; j < i; j++)
18229 mem = adjust_address (m_tramp, SImode, j * GET_MODE_SIZE (SImode));
18230 mips_emit_move (mem, trampoline[j]);
18233 /* Set up the static chain pointer field. */
18234 mem = adjust_address (m_tramp, ptr_mode, static_chain_offset);
18235 mips_emit_move (mem, chain_value);
18237 /* Set up the target function field. */
18238 mem = adjust_address (m_tramp, ptr_mode, target_function_offset);
18239 mips_emit_move (mem, XEXP (DECL_RTL (fndecl), 0));
18241 /* Flush the code part of the trampoline. */
18242 emit_insn (gen_add3_insn (end_addr, addr, GEN_INT (TRAMPOLINE_SIZE)));
18243 emit_insn (gen_clear_cache (addr, end_addr));
18246 /* Implement FUNCTION_PROFILER. */
18248 void mips_function_profiler (FILE *file)
18251 sorry ("mips16 function profiling");
18252 if (TARGET_LONG_CALLS)
18254 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */
18255 if (Pmode == DImode)
18256 fprintf (file, "\tdla\t%s,_mcount\n", reg_names[3]);
18258 fprintf (file, "\tla\t%s,_mcount\n", reg_names[3]);
18260 mips_push_asm_switch (&mips_noat);
18261 fprintf (file, "\tmove\t%s,%s\t\t# save current return address\n",
18262 reg_names[AT_REGNUM], reg_names[RETURN_ADDR_REGNUM]);
18263 /* _mcount treats $2 as the static chain register. */
18264 if (cfun->static_chain_decl != NULL)
18265 fprintf (file, "\tmove\t%s,%s\n", reg_names[2],
18266 reg_names[STATIC_CHAIN_REGNUM]);
18267 if (TARGET_MCOUNT_RA_ADDRESS)
18269 /* If TARGET_MCOUNT_RA_ADDRESS load $12 with the address of the
18270 ra save location. */
18271 if (cfun->machine->frame.ra_fp_offset == 0)
18272 /* ra not saved, pass zero. */
18273 fprintf (file, "\tmove\t%s,%s\n", reg_names[12], reg_names[0]);
18275 fprintf (file, "\t%s\t%s," HOST_WIDE_INT_PRINT_DEC "(%s)\n",
18276 Pmode == DImode ? "dla" : "la", reg_names[12],
18277 cfun->machine->frame.ra_fp_offset,
18278 reg_names[STACK_POINTER_REGNUM]);
18280 if (!TARGET_NEWABI)
18282 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n",
18283 TARGET_64BIT ? "dsubu" : "subu",
18284 reg_names[STACK_POINTER_REGNUM],
18285 reg_names[STACK_POINTER_REGNUM],
18286 Pmode == DImode ? 16 : 8);
18288 if (TARGET_LONG_CALLS)
18289 fprintf (file, "\tjalr\t%s\n", reg_names[3]);
18291 fprintf (file, "\tjal\t_mcount\n");
18292 mips_pop_asm_switch (&mips_noat);
18293 /* _mcount treats $2 as the static chain register. */
18294 if (cfun->static_chain_decl != NULL)
18295 fprintf (file, "\tmove\t%s,%s\n", reg_names[STATIC_CHAIN_REGNUM],
18299 /* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default
18300 behaviour of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even
18301 when TARGET_LOONGSON_VECTORS is true. */
18303 static unsigned HOST_WIDE_INT
18304 mips_shift_truncation_mask (machine_mode mode)
18306 if (TARGET_LOONGSON_VECTORS && VECTOR_MODE_P (mode))
18309 return GET_MODE_BITSIZE (mode) - 1;
18312 /* Implement TARGET_PREPARE_PCH_SAVE. */
18315 mips_prepare_pch_save (void)
18317 /* We are called in a context where the current MIPS16 vs. non-MIPS16
18318 setting should be irrelevant. The question then is: which setting
18319 makes most sense at load time?
18321 The PCH is loaded before the first token is read. We should never
18322 have switched into MIPS16 mode by that point, and thus should not
18323 have populated mips16_globals. Nor can we load the entire contents
18324 of mips16_globals from the PCH file, because mips16_globals contains
18325 a combination of GGC and non-GGC data.
18327 There is therefore no point in trying save the GGC part of
18328 mips16_globals to the PCH file, or to preserve MIPS16ness across
18329 the PCH save and load. The loading compiler would not have access
18330 to the non-GGC parts of mips16_globals (either from the PCH file,
18331 or from a copy that the loading compiler generated itself) and would
18332 have to call target_reinit anyway.
18334 It therefore seems best to switch back to non-MIPS16 mode at
18335 save time, and to ensure that mips16_globals remains null after
18337 mips_set_compression_mode (0);
18338 mips16_globals = 0;
18341 /* Generate or test for an insn that supports a constant permutation. */
18343 #define MAX_VECT_LEN 8
18345 struct expand_vec_perm_d
18347 rtx target, op0, op1;
18348 unsigned char perm[MAX_VECT_LEN];
18349 machine_mode vmode;
18350 unsigned char nelt;
18355 /* Construct (set target (vec_select op0 (parallel perm))) and
18356 return true if that's a valid instruction in the active ISA. */
18359 mips_expand_vselect (rtx target, rtx op0,
18360 const unsigned char *perm, unsigned nelt)
18362 rtx rperm[MAX_VECT_LEN], x;
18366 for (i = 0; i < nelt; ++i)
18367 rperm[i] = GEN_INT (perm[i]);
18369 x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (nelt, rperm));
18370 x = gen_rtx_VEC_SELECT (GET_MODE (target), op0, x);
18371 x = gen_rtx_SET (VOIDmode, target, x);
18373 insn = emit_insn (x);
18374 if (recog_memoized (insn) < 0)
18376 remove_insn (insn);
18382 /* Similar, but generate a vec_concat from op0 and op1 as well. */
18385 mips_expand_vselect_vconcat (rtx target, rtx op0, rtx op1,
18386 const unsigned char *perm, unsigned nelt)
18388 machine_mode v2mode;
18391 v2mode = GET_MODE_2XWIDER_MODE (GET_MODE (op0));
18392 x = gen_rtx_VEC_CONCAT (v2mode, op0, op1);
18393 return mips_expand_vselect (target, x, perm, nelt);
18396 /* Recognize patterns for even-odd extraction. */
18399 mips_expand_vpc_loongson_even_odd (struct expand_vec_perm_d *d)
18401 unsigned i, odd, nelt = d->nelt;
18402 rtx t0, t1, t2, t3;
18404 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
18406 /* Even-odd for V2SI/V2SFmode is matched by interleave directly. */
18413 for (i = 1; i < nelt; ++i)
18414 if (d->perm[i] != i * 2 + odd)
18420 /* We need 2*log2(N)-1 operations to achieve odd/even with interleave. */
18421 t0 = gen_reg_rtx (d->vmode);
18422 t1 = gen_reg_rtx (d->vmode);
18426 emit_insn (gen_loongson_punpckhhw (t0, d->op0, d->op1));
18427 emit_insn (gen_loongson_punpcklhw (t1, d->op0, d->op1));
18429 emit_insn (gen_loongson_punpckhhw (d->target, t1, t0));
18431 emit_insn (gen_loongson_punpcklhw (d->target, t1, t0));
18435 t2 = gen_reg_rtx (d->vmode);
18436 t3 = gen_reg_rtx (d->vmode);
18437 emit_insn (gen_loongson_punpckhbh (t0, d->op0, d->op1));
18438 emit_insn (gen_loongson_punpcklbh (t1, d->op0, d->op1));
18439 emit_insn (gen_loongson_punpckhbh (t2, t1, t0));
18440 emit_insn (gen_loongson_punpcklbh (t3, t1, t0));
18442 emit_insn (gen_loongson_punpckhbh (d->target, t3, t2));
18444 emit_insn (gen_loongson_punpcklbh (d->target, t3, t2));
18448 gcc_unreachable ();
18453 /* Recognize patterns for the Loongson PSHUFH instruction. */
18456 mips_expand_vpc_loongson_pshufh (struct expand_vec_perm_d *d)
18461 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
18463 if (d->vmode != V4HImode)
18468 /* Convert the selector into the packed 8-bit form for pshufh. */
18469 /* Recall that loongson is little-endian only. No big-endian
18470 adjustment required. */
18471 for (i = mask = 0; i < 4; i++)
18472 mask |= (d->perm[i] & 3) << (i * 2);
18473 rmask = force_reg (SImode, GEN_INT (mask));
18475 if (d->one_vector_p)
18476 emit_insn (gen_loongson_pshufh (d->target, d->op0, rmask));
18479 rtx t0, t1, x, merge, rmerge[4];
18481 t0 = gen_reg_rtx (V4HImode);
18482 t1 = gen_reg_rtx (V4HImode);
18483 emit_insn (gen_loongson_pshufh (t1, d->op1, rmask));
18484 emit_insn (gen_loongson_pshufh (t0, d->op0, rmask));
18486 for (i = 0; i < 4; ++i)
18487 rmerge[i] = (d->perm[i] & 4 ? constm1_rtx : const0_rtx);
18488 merge = gen_rtx_CONST_VECTOR (V4HImode, gen_rtvec_v (4, rmerge));
18489 merge = force_reg (V4HImode, merge);
18491 x = gen_rtx_AND (V4HImode, merge, t1);
18492 emit_insn (gen_rtx_SET (VOIDmode, t1, x));
18494 x = gen_rtx_NOT (V4HImode, merge);
18495 x = gen_rtx_AND (V4HImode, x, t0);
18496 emit_insn (gen_rtx_SET (VOIDmode, t0, x));
18498 x = gen_rtx_IOR (V4HImode, t0, t1);
18499 emit_insn (gen_rtx_SET (VOIDmode, d->target, x));
18505 /* Recognize broadcast patterns for the Loongson. */
18508 mips_expand_vpc_loongson_bcast (struct expand_vec_perm_d *d)
18513 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
18515 /* Note that we've already matched V2SI via punpck and V4HI via pshufh. */
18516 if (d->vmode != V8QImode)
18518 if (!d->one_vector_p)
18522 for (i = 1; i < 8; ++i)
18523 if (d->perm[i] != elt)
18529 /* With one interleave we put two of the desired element adjacent. */
18530 t0 = gen_reg_rtx (V8QImode);
18532 emit_insn (gen_loongson_punpcklbh (t0, d->op0, d->op0));
18534 emit_insn (gen_loongson_punpckhbh (t0, d->op0, d->op0));
18536 /* Shuffle that one HImode element into all locations. */
18539 t1 = gen_reg_rtx (V4HImode);
18540 emit_insn (gen_loongson_pshufh (t1, gen_lowpart (V4HImode, t0),
18541 force_reg (SImode, GEN_INT (elt))));
18543 emit_move_insn (d->target, gen_lowpart (V8QImode, t1));
18548 mips_expand_vec_perm_const_1 (struct expand_vec_perm_d *d)
18550 unsigned int i, nelt = d->nelt;
18551 unsigned char perm2[MAX_VECT_LEN];
18553 if (d->one_vector_p)
18555 /* Try interleave with alternating operands. */
18556 memcpy (perm2, d->perm, sizeof(perm2));
18557 for (i = 1; i < nelt; i += 2)
18559 if (mips_expand_vselect_vconcat (d->target, d->op0, d->op1, perm2, nelt))
18564 if (mips_expand_vselect_vconcat (d->target, d->op0, d->op1,
18568 /* Try again with swapped operands. */
18569 for (i = 0; i < nelt; ++i)
18570 perm2[i] = (d->perm[i] + nelt) & (2 * nelt - 1);
18571 if (mips_expand_vselect_vconcat (d->target, d->op1, d->op0, perm2, nelt))
18575 if (mips_expand_vpc_loongson_even_odd (d))
18577 if (mips_expand_vpc_loongson_pshufh (d))
18579 if (mips_expand_vpc_loongson_bcast (d))
18584 /* Expand a vec_perm_const pattern. */
18587 mips_expand_vec_perm_const (rtx operands[4])
18589 struct expand_vec_perm_d d;
18590 int i, nelt, which;
18591 unsigned char orig_perm[MAX_VECT_LEN];
18595 d.target = operands[0];
18596 d.op0 = operands[1];
18597 d.op1 = operands[2];
18600 d.vmode = GET_MODE (d.target);
18601 gcc_assert (VECTOR_MODE_P (d.vmode));
18602 d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
18603 d.testing_p = false;
18605 for (i = which = 0; i < nelt; ++i)
18607 rtx e = XVECEXP (sel, 0, i);
18608 int ei = INTVAL (e) & (2 * nelt - 1);
18609 which |= (ei < nelt ? 1 : 2);
18612 memcpy (d.perm, orig_perm, MAX_VECT_LEN);
18620 d.one_vector_p = false;
18621 if (!rtx_equal_p (d.op0, d.op1))
18626 for (i = 0; i < nelt; ++i)
18627 d.perm[i] &= nelt - 1;
18629 d.one_vector_p = true;
18634 d.one_vector_p = true;
18638 ok = mips_expand_vec_perm_const_1 (&d);
18640 /* If we were given a two-vector permutation which just happened to
18641 have both input vectors equal, we folded this into a one-vector
18642 permutation. There are several loongson patterns that are matched
18643 via direct vec_select+vec_concat expansion, but we do not have
18644 support in mips_expand_vec_perm_const_1 to guess the adjustment
18645 that should be made for a single operand. Just try again with
18646 the original permutation. */
18647 if (!ok && which == 3)
18649 d.op0 = operands[1];
18650 d.op1 = operands[2];
18651 d.one_vector_p = false;
18652 memcpy (d.perm, orig_perm, MAX_VECT_LEN);
18653 ok = mips_expand_vec_perm_const_1 (&d);
18659 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST_OK. */
18662 mips_vectorize_vec_perm_const_ok (machine_mode vmode,
18663 const unsigned char *sel)
18665 struct expand_vec_perm_d d;
18666 unsigned int i, nelt, which;
18670 d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
18671 d.testing_p = true;
18672 memcpy (d.perm, sel, nelt);
18674 /* Categorize the set of elements in the selector. */
18675 for (i = which = 0; i < nelt; ++i)
18677 unsigned char e = d.perm[i];
18678 gcc_assert (e < 2 * nelt);
18679 which |= (e < nelt ? 1 : 2);
18682 /* For all elements from second vector, fold the elements to first. */
18684 for (i = 0; i < nelt; ++i)
18687 /* Check whether the mask can be applied to the vector type. */
18688 d.one_vector_p = (which != 3);
18690 d.target = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 1);
18691 d.op1 = d.op0 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 2);
18692 if (!d.one_vector_p)
18693 d.op1 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 3);
18696 ret = mips_expand_vec_perm_const_1 (&d);
18702 /* Expand an integral vector unpack operation. */
18705 mips_expand_vec_unpack (rtx operands[2], bool unsigned_p, bool high_p)
18707 machine_mode imode = GET_MODE (operands[1]);
18708 rtx (*unpack) (rtx, rtx, rtx);
18709 rtx (*cmpgt) (rtx, rtx, rtx);
18710 rtx tmp, dest, zero;
18716 unpack = gen_loongson_punpckhbh;
18718 unpack = gen_loongson_punpcklbh;
18719 cmpgt = gen_loongson_pcmpgtb;
18723 unpack = gen_loongson_punpckhhw;
18725 unpack = gen_loongson_punpcklhw;
18726 cmpgt = gen_loongson_pcmpgth;
18729 gcc_unreachable ();
18732 zero = force_reg (imode, CONST0_RTX (imode));
18737 tmp = gen_reg_rtx (imode);
18738 emit_insn (cmpgt (tmp, zero, operands[1]));
18741 dest = gen_reg_rtx (imode);
18742 emit_insn (unpack (dest, operands[1], tmp));
18744 emit_move_insn (operands[0], gen_lowpart (GET_MODE (operands[0]), dest));
18747 /* A subroutine of mips_expand_vec_init, match constant vector elements. */
18750 mips_constant_elt_p (rtx x)
18752 return CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE;
18755 /* A subroutine of mips_expand_vec_init, expand via broadcast. */
18758 mips_expand_vi_broadcast (machine_mode vmode, rtx target, rtx elt)
18760 struct expand_vec_perm_d d;
18764 if (elt != const0_rtx)
18765 elt = force_reg (GET_MODE_INNER (vmode), elt);
18767 elt = gen_lowpart (DImode, elt);
18769 t1 = gen_reg_rtx (vmode);
18773 emit_insn (gen_loongson_vec_init1_v8qi (t1, elt));
18776 emit_insn (gen_loongson_vec_init1_v4hi (t1, elt));
18779 gcc_unreachable ();
18782 memset (&d, 0, sizeof (d));
18787 d.nelt = GET_MODE_NUNITS (vmode);
18788 d.one_vector_p = true;
18790 ok = mips_expand_vec_perm_const_1 (&d);
18794 /* A subroutine of mips_expand_vec_init, replacing all of the non-constant
18795 elements of VALS with zeros, copy the constant vector to TARGET. */
18798 mips_expand_vi_constant (machine_mode vmode, unsigned nelt,
18799 rtx target, rtx vals)
18801 rtvec vec = shallow_copy_rtvec (XVEC (vals, 0));
18804 for (i = 0; i < nelt; ++i)
18806 if (!mips_constant_elt_p (RTVEC_ELT (vec, i)))
18807 RTVEC_ELT (vec, i) = const0_rtx;
18810 emit_move_insn (target, gen_rtx_CONST_VECTOR (vmode, vec));
18814 /* A subroutine of mips_expand_vec_init, expand via pinsrh. */
18817 mips_expand_vi_loongson_one_pinsrh (rtx target, rtx vals, unsigned one_var)
18819 mips_expand_vi_constant (V4HImode, 4, target, vals);
18821 emit_insn (gen_vec_setv4hi (target, target, XVECEXP (vals, 0, one_var),
18822 GEN_INT (one_var)));
18825 /* A subroutine of mips_expand_vec_init, expand anything via memory. */
18828 mips_expand_vi_general (machine_mode vmode, machine_mode imode,
18829 unsigned nelt, unsigned nvar, rtx target, rtx vals)
18831 rtx mem = assign_stack_temp (vmode, GET_MODE_SIZE (vmode));
18832 unsigned int i, isize = GET_MODE_SIZE (imode);
18835 mips_expand_vi_constant (vmode, nelt, mem, vals);
18837 for (i = 0; i < nelt; ++i)
18839 rtx x = XVECEXP (vals, 0, i);
18840 if (!mips_constant_elt_p (x))
18841 emit_move_insn (adjust_address (mem, imode, i * isize), x);
18844 emit_move_insn (target, mem);
18847 /* Expand a vector initialization. */
18850 mips_expand_vector_init (rtx target, rtx vals)
18852 machine_mode vmode = GET_MODE (target);
18853 machine_mode imode = GET_MODE_INNER (vmode);
18854 unsigned i, nelt = GET_MODE_NUNITS (vmode);
18855 unsigned nvar = 0, one_var = -1u;
18856 bool all_same = true;
18859 for (i = 0; i < nelt; ++i)
18861 x = XVECEXP (vals, 0, i);
18862 if (!mips_constant_elt_p (x))
18863 nvar++, one_var = i;
18864 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
18868 /* Load constants from the pool, or whatever's handy. */
18871 emit_move_insn (target, gen_rtx_CONST_VECTOR (vmode, XVEC (vals, 0)));
18875 /* For two-part initialization, always use CONCAT. */
18878 rtx op0 = force_reg (imode, XVECEXP (vals, 0, 0));
18879 rtx op1 = force_reg (imode, XVECEXP (vals, 0, 1));
18880 x = gen_rtx_VEC_CONCAT (vmode, op0, op1);
18881 emit_insn (gen_rtx_SET (VOIDmode, target, x));
18885 /* Loongson is the only cpu with vectors with more elements. */
18886 gcc_assert (TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS);
18888 /* If all values are identical, broadcast the value. */
18891 mips_expand_vi_broadcast (vmode, target, XVECEXP (vals, 0, 0));
18895 /* If we've only got one non-variable V4HImode, use PINSRH. */
18896 if (nvar == 1 && vmode == V4HImode)
18898 mips_expand_vi_loongson_one_pinsrh (target, vals, one_var);
18902 mips_expand_vi_general (vmode, imode, nelt, nvar, target, vals);
18905 /* Expand a vector reduction. */
18908 mips_expand_vec_reduc (rtx target, rtx in, rtx (*gen)(rtx, rtx, rtx))
18910 machine_mode vmode = GET_MODE (in);
18911 unsigned char perm2[2];
18912 rtx last, next, fold, x;
18916 fold = gen_reg_rtx (vmode);
18920 /* Use PUL/PLU to produce { L, H } op { H, L }.
18921 By reversing the pair order, rather than a pure interleave high,
18922 we avoid erroneous exceptional conditions that we might otherwise
18923 produce from the computation of H op H. */
18926 ok = mips_expand_vselect_vconcat (fold, last, last, perm2, 2);
18931 /* Use interleave to produce { H, L } op { H, H }. */
18932 emit_insn (gen_loongson_punpckhwd (fold, last, last));
18936 /* Perform the first reduction with interleave,
18937 and subsequent reductions with shifts. */
18938 emit_insn (gen_loongson_punpckhwd_hi (fold, last, last));
18940 next = gen_reg_rtx (vmode);
18941 emit_insn (gen (next, last, fold));
18944 fold = gen_reg_rtx (vmode);
18945 x = force_reg (SImode, GEN_INT (16));
18946 emit_insn (gen_vec_shr_v4hi (fold, last, x));
18950 emit_insn (gen_loongson_punpckhwd_qi (fold, last, last));
18952 next = gen_reg_rtx (vmode);
18953 emit_insn (gen (next, last, fold));
18956 fold = gen_reg_rtx (vmode);
18957 x = force_reg (SImode, GEN_INT (16));
18958 emit_insn (gen_vec_shr_v8qi (fold, last, x));
18960 next = gen_reg_rtx (vmode);
18961 emit_insn (gen (next, last, fold));
18964 fold = gen_reg_rtx (vmode);
18965 x = force_reg (SImode, GEN_INT (8));
18966 emit_insn (gen_vec_shr_v8qi (fold, last, x));
18970 gcc_unreachable ();
18973 emit_insn (gen (target, last, fold));
18976 /* Expand a vector minimum/maximum. */
18979 mips_expand_vec_minmax (rtx target, rtx op0, rtx op1,
18980 rtx (*cmp) (rtx, rtx, rtx), bool min_p)
18982 machine_mode vmode = GET_MODE (target);
18985 tc = gen_reg_rtx (vmode);
18986 t0 = gen_reg_rtx (vmode);
18987 t1 = gen_reg_rtx (vmode);
18990 emit_insn (cmp (tc, op0, op1));
18992 x = gen_rtx_AND (vmode, tc, (min_p ? op1 : op0));
18993 emit_insn (gen_rtx_SET (VOIDmode, t0, x));
18995 x = gen_rtx_NOT (vmode, tc);
18996 x = gen_rtx_AND (vmode, x, (min_p ? op0 : op1));
18997 emit_insn (gen_rtx_SET (VOIDmode, t1, x));
18999 x = gen_rtx_IOR (vmode, t0, t1);
19000 emit_insn (gen_rtx_SET (VOIDmode, target, x));
19003 /* Implement HARD_REGNO_CALLER_SAVE_MODE. */
19006 mips_hard_regno_caller_save_mode (unsigned int regno,
19007 unsigned int nregs,
19010 /* For performance, avoid saving/restoring upper parts of a register
19011 by returning MODE as save mode when the mode is known. */
19012 if (mode == VOIDmode)
19013 return choose_hard_reg_mode (regno, nregs, false);
19018 /* Implement TARGET_CASE_VALUES_THRESHOLD. */
19021 mips_case_values_threshold (void)
19023 /* In MIPS16 mode using a larger case threshold generates smaller code. */
19024 if (TARGET_MIPS16 && optimize_size)
19027 return default_case_values_threshold ();
19030 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
19033 mips_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
19035 if (!TARGET_HARD_FLOAT_ABI)
19037 tree exceptions_var = create_tmp_var (MIPS_ATYPE_USI, NULL);
19038 tree fcsr_orig_var = create_tmp_var (MIPS_ATYPE_USI, NULL);
19039 tree fcsr_mod_var = create_tmp_var (MIPS_ATYPE_USI, NULL);
19040 tree get_fcsr = mips_builtin_decls[MIPS_GET_FCSR];
19041 tree set_fcsr = mips_builtin_decls[MIPS_SET_FCSR];
19042 tree get_fcsr_hold_call = build_call_expr (get_fcsr, 0);
19043 tree hold_assign_orig = build2 (MODIFY_EXPR, MIPS_ATYPE_USI,
19044 fcsr_orig_var, get_fcsr_hold_call);
19045 tree hold_mod_val = build2 (BIT_AND_EXPR, MIPS_ATYPE_USI, fcsr_orig_var,
19046 build_int_cst (MIPS_ATYPE_USI, 0xfffff003));
19047 tree hold_assign_mod = build2 (MODIFY_EXPR, MIPS_ATYPE_USI,
19048 fcsr_mod_var, hold_mod_val);
19049 tree set_fcsr_hold_call = build_call_expr (set_fcsr, 1, fcsr_mod_var);
19050 tree hold_all = build2 (COMPOUND_EXPR, MIPS_ATYPE_USI,
19051 hold_assign_orig, hold_assign_mod);
19052 *hold = build2 (COMPOUND_EXPR, void_type_node, hold_all,
19053 set_fcsr_hold_call);
19055 *clear = build_call_expr (set_fcsr, 1, fcsr_mod_var);
19057 tree get_fcsr_update_call = build_call_expr (get_fcsr, 0);
19058 *update = build2 (MODIFY_EXPR, MIPS_ATYPE_USI,
19059 exceptions_var, get_fcsr_update_call);
19060 tree set_fcsr_update_call = build_call_expr (set_fcsr, 1, fcsr_orig_var);
19061 *update = build2 (COMPOUND_EXPR, void_type_node, *update,
19062 set_fcsr_update_call);
19063 tree atomic_feraiseexcept
19064 = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT);
19065 tree int_exceptions_var = fold_convert (integer_type_node,
19067 tree atomic_feraiseexcept_call = build_call_expr (atomic_feraiseexcept,
19068 1, int_exceptions_var);
19069 *update = build2 (COMPOUND_EXPR, void_type_node, *update,
19070 atomic_feraiseexcept_call);
19073 /* Implement TARGET_SPILL_CLASS. */
19076 mips_spill_class (reg_class_t rclass ATTRIBUTE_UNUSED,
19077 machine_mode mode ATTRIBUTE_UNUSED)
19084 /* Implement TARGET_LRA_P. */
19089 return mips_lra_flag;
19092 /* Initialize the GCC target structure. */
19093 #undef TARGET_ASM_ALIGNED_HI_OP
19094 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
19095 #undef TARGET_ASM_ALIGNED_SI_OP
19096 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
19097 #undef TARGET_ASM_ALIGNED_DI_OP
19098 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
19100 #undef TARGET_OPTION_OVERRIDE
19101 #define TARGET_OPTION_OVERRIDE mips_option_override
19103 #undef TARGET_LEGITIMIZE_ADDRESS
19104 #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
19106 #undef TARGET_ASM_FUNCTION_PROLOGUE
19107 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
19108 #undef TARGET_ASM_FUNCTION_EPILOGUE
19109 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
19110 #undef TARGET_ASM_SELECT_RTX_SECTION
19111 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
19112 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
19113 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
19115 #undef TARGET_SCHED_INIT
19116 #define TARGET_SCHED_INIT mips_sched_init
19117 #undef TARGET_SCHED_REORDER
19118 #define TARGET_SCHED_REORDER mips_sched_reorder
19119 #undef TARGET_SCHED_REORDER2
19120 #define TARGET_SCHED_REORDER2 mips_sched_reorder2
19121 #undef TARGET_SCHED_VARIABLE_ISSUE
19122 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
19123 #undef TARGET_SCHED_ADJUST_COST
19124 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
19125 #undef TARGET_SCHED_ISSUE_RATE
19126 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
19127 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
19128 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
19129 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
19130 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
19131 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
19132 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
19133 mips_multipass_dfa_lookahead
19134 #undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
19135 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
19136 mips_small_register_classes_for_mode_p
19138 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
19139 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
19141 #undef TARGET_INSERT_ATTRIBUTES
19142 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
19143 #undef TARGET_MERGE_DECL_ATTRIBUTES
19144 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
19145 #undef TARGET_CAN_INLINE_P
19146 #define TARGET_CAN_INLINE_P mips_can_inline_p
19147 #undef TARGET_SET_CURRENT_FUNCTION
19148 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
19150 #undef TARGET_VALID_POINTER_MODE
19151 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
19152 #undef TARGET_REGISTER_MOVE_COST
19153 #define TARGET_REGISTER_MOVE_COST mips_register_move_cost
19154 #undef TARGET_REGISTER_PRIORITY
19155 #define TARGET_REGISTER_PRIORITY mips_register_priority
19156 #undef TARGET_MEMORY_MOVE_COST
19157 #define TARGET_MEMORY_MOVE_COST mips_memory_move_cost
19158 #undef TARGET_RTX_COSTS
19159 #define TARGET_RTX_COSTS mips_rtx_costs
19160 #undef TARGET_ADDRESS_COST
19161 #define TARGET_ADDRESS_COST mips_address_cost
19163 #undef TARGET_IN_SMALL_DATA_P
19164 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
19166 #undef TARGET_MACHINE_DEPENDENT_REORG
19167 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
19169 #undef TARGET_PREFERRED_RELOAD_CLASS
19170 #define TARGET_PREFERRED_RELOAD_CLASS mips_preferred_reload_class
19172 #undef TARGET_EXPAND_TO_RTL_HOOK
19173 #define TARGET_EXPAND_TO_RTL_HOOK mips_expand_to_rtl_hook
19174 #undef TARGET_ASM_FILE_START
19175 #define TARGET_ASM_FILE_START mips_file_start
19176 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
19177 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
19178 #undef TARGET_ASM_CODE_END
19179 #define TARGET_ASM_CODE_END mips_code_end
19181 #undef TARGET_INIT_LIBFUNCS
19182 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
19184 #undef TARGET_BUILD_BUILTIN_VA_LIST
19185 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
19186 #undef TARGET_EXPAND_BUILTIN_VA_START
19187 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
19188 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
19189 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
19191 #undef TARGET_PROMOTE_FUNCTION_MODE
19192 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
19193 #undef TARGET_PROMOTE_PROTOTYPES
19194 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
19196 #undef TARGET_FUNCTION_VALUE
19197 #define TARGET_FUNCTION_VALUE mips_function_value
19198 #undef TARGET_LIBCALL_VALUE
19199 #define TARGET_LIBCALL_VALUE mips_libcall_value
19200 #undef TARGET_FUNCTION_VALUE_REGNO_P
19201 #define TARGET_FUNCTION_VALUE_REGNO_P mips_function_value_regno_p
19202 #undef TARGET_RETURN_IN_MEMORY
19203 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
19204 #undef TARGET_RETURN_IN_MSB
19205 #define TARGET_RETURN_IN_MSB mips_return_in_msb
19207 #undef TARGET_ASM_OUTPUT_MI_THUNK
19208 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
19209 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
19210 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
19212 #undef TARGET_PRINT_OPERAND
19213 #define TARGET_PRINT_OPERAND mips_print_operand
19214 #undef TARGET_PRINT_OPERAND_ADDRESS
19215 #define TARGET_PRINT_OPERAND_ADDRESS mips_print_operand_address
19216 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
19217 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mips_print_operand_punct_valid_p
19219 #undef TARGET_SETUP_INCOMING_VARARGS
19220 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
19221 #undef TARGET_STRICT_ARGUMENT_NAMING
19222 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
19223 #undef TARGET_MUST_PASS_IN_STACK
19224 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
19225 #undef TARGET_PASS_BY_REFERENCE
19226 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
19227 #undef TARGET_CALLEE_COPIES
19228 #define TARGET_CALLEE_COPIES mips_callee_copies
19229 #undef TARGET_ARG_PARTIAL_BYTES
19230 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
19231 #undef TARGET_FUNCTION_ARG
19232 #define TARGET_FUNCTION_ARG mips_function_arg
19233 #undef TARGET_FUNCTION_ARG_ADVANCE
19234 #define TARGET_FUNCTION_ARG_ADVANCE mips_function_arg_advance
19235 #undef TARGET_FUNCTION_ARG_BOUNDARY
19236 #define TARGET_FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
19237 #undef TARGET_GET_RAW_RESULT_MODE
19238 #define TARGET_GET_RAW_RESULT_MODE mips_get_reg_raw_mode
19239 #undef TARGET_GET_RAW_ARG_MODE
19240 #define TARGET_GET_RAW_ARG_MODE mips_get_reg_raw_mode
19242 #undef TARGET_MODE_REP_EXTENDED
19243 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
19245 #undef TARGET_VECTOR_MODE_SUPPORTED_P
19246 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
19248 #undef TARGET_SCALAR_MODE_SUPPORTED_P
19249 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
19251 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
19252 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE mips_preferred_simd_mode
19254 #undef TARGET_INIT_BUILTINS
19255 #define TARGET_INIT_BUILTINS mips_init_builtins
19256 #undef TARGET_BUILTIN_DECL
19257 #define TARGET_BUILTIN_DECL mips_builtin_decl
19258 #undef TARGET_EXPAND_BUILTIN
19259 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
19261 #undef TARGET_HAVE_TLS
19262 #define TARGET_HAVE_TLS HAVE_AS_TLS
19264 #undef TARGET_CANNOT_FORCE_CONST_MEM
19265 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
19267 #undef TARGET_LEGITIMATE_CONSTANT_P
19268 #define TARGET_LEGITIMATE_CONSTANT_P mips_legitimate_constant_p
19270 #undef TARGET_ENCODE_SECTION_INFO
19271 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
19273 #undef TARGET_ATTRIBUTE_TABLE
19274 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
19275 /* All our function attributes are related to how out-of-line copies should
19276 be compiled or called. They don't in themselves prevent inlining. */
19277 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
19278 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
19280 #undef TARGET_EXTRA_LIVE_ON_ENTRY
19281 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
19283 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
19284 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
19285 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
19286 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
19288 #undef TARGET_COMP_TYPE_ATTRIBUTES
19289 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
19291 #ifdef HAVE_AS_DTPRELWORD
19292 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
19293 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
19295 #undef TARGET_DWARF_REGISTER_SPAN
19296 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
19297 #undef TARGET_DWARF_FRAME_REG_MODE
19298 #define TARGET_DWARF_FRAME_REG_MODE mips_dwarf_frame_reg_mode
19300 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
19301 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
19303 #undef TARGET_LEGITIMATE_ADDRESS_P
19304 #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p
19306 #undef TARGET_FRAME_POINTER_REQUIRED
19307 #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required
19309 #undef TARGET_CAN_ELIMINATE
19310 #define TARGET_CAN_ELIMINATE mips_can_eliminate
19312 #undef TARGET_CONDITIONAL_REGISTER_USAGE
19313 #define TARGET_CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage
19315 #undef TARGET_TRAMPOLINE_INIT
19316 #define TARGET_TRAMPOLINE_INIT mips_trampoline_init
19318 #undef TARGET_ASM_OUTPUT_SOURCE_FILENAME
19319 #define TARGET_ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
19321 #undef TARGET_SHIFT_TRUNCATION_MASK
19322 #define TARGET_SHIFT_TRUNCATION_MASK mips_shift_truncation_mask
19324 #undef TARGET_PREPARE_PCH_SAVE
19325 #define TARGET_PREPARE_PCH_SAVE mips_prepare_pch_save
19327 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
19328 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK mips_vectorize_vec_perm_const_ok
19330 #undef TARGET_CASE_VALUES_THRESHOLD
19331 #define TARGET_CASE_VALUES_THRESHOLD mips_case_values_threshold
19333 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
19334 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV mips_atomic_assign_expand_fenv
19336 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
19337 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
19339 #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
19340 #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
19341 mips_use_by_pieces_infrastructure_p
19343 #undef TARGET_SPILL_CLASS
19344 #define TARGET_SPILL_CLASS mips_spill_class
19345 #undef TARGET_LRA_P
19346 #define TARGET_LRA_P mips_lra_p
19348 struct gcc_target targetm = TARGET_INITIALIZER;
19350 #include "gt-mips.h"