1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989-2013 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky, lich@inria.inria.fr.
4 Changes by Michael Meissner, meissner@osf.org.
5 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 Brendan Eich, brendan@microunity.com.
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
30 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
46 #include "hash-table.h"
49 #include "target-def.h"
50 #include "common/common-target.h"
51 #include "langhooks.h"
52 #include "sched-int.h"
55 #include "diagnostic.h"
56 #include "target-globals.h"
58 #include "tree-pass.h"
61 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
62 #define UNSPEC_ADDRESS_P(X) \
63 (GET_CODE (X) == UNSPEC \
64 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
65 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
67 /* Extract the symbol or label from UNSPEC wrapper X. */
68 #define UNSPEC_ADDRESS(X) \
71 /* Extract the symbol type from UNSPEC wrapper X. */
72 #define UNSPEC_ADDRESS_TYPE(X) \
73 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
75 /* The maximum distance between the top of the stack frame and the
76 value $sp has when we save and restore registers.
78 The value for normal-mode code must be a SMALL_OPERAND and must
79 preserve the maximum stack alignment. We therefore use a value
80 of 0x7ff0 in this case.
82 microMIPS LWM and SWM support 12-bit offsets (from -0x800 to 0x7ff),
83 so we use a maximum of 0x7f0 for TARGET_MICROMIPS.
85 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
86 up to 0x7f8 bytes and can usually save or restore all the registers
87 that we need to save or restore. (Note that we can only use these
88 instructions for o32, for which the stack alignment is 8 bytes.)
90 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
91 RESTORE are not available. We can then use unextended instructions
92 to save and restore registers, and to allocate and deallocate the top
94 #define MIPS_MAX_FIRST_STACK_STEP \
95 (!TARGET_COMPRESSION ? 0x7ff0 \
96 : TARGET_MICROMIPS || GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
97 : TARGET_64BIT ? 0x100 : 0x400)
99 /* True if INSN is a mips.md pattern or asm statement. */
100 /* ??? This test exists through the compiler, perhaps it should be
102 #define USEFUL_INSN_P(INSN) \
103 (NONDEBUG_INSN_P (INSN) \
104 && GET_CODE (PATTERN (INSN)) != USE \
105 && GET_CODE (PATTERN (INSN)) != CLOBBER)
107 /* If INSN is a delayed branch sequence, return the first instruction
108 in the sequence, otherwise return INSN itself. */
109 #define SEQ_BEGIN(INSN) \
110 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
111 ? XVECEXP (PATTERN (INSN), 0, 0) \
114 /* Likewise for the last instruction in a delayed branch sequence. */
115 #define SEQ_END(INSN) \
116 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
117 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
120 /* Execute the following loop body with SUBINSN set to each instruction
121 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
122 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
123 for ((SUBINSN) = SEQ_BEGIN (INSN); \
124 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
125 (SUBINSN) = NEXT_INSN (SUBINSN))
127 /* True if bit BIT is set in VALUE. */
128 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
130 /* Return the opcode for a ptr_mode load of the form:
132 l[wd] DEST, OFFSET(BASE). */
133 #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \
134 (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \
139 /* Return the opcode to move register SRC into register DEST. */
140 #define MIPS_MOVE(DEST, SRC) \
141 ((TARGET_64BIT ? 0x2d : 0x21) \
145 /* Return the opcode for:
148 #define MIPS_LUI(DEST, VALUE) \
149 ((0xf << 26) | ((DEST) << 16) | (VALUE))
151 /* Return the opcode to jump to register DEST. */
152 #define MIPS_JR(DEST) \
153 (((DEST) << 21) | 0x8)
155 /* Return the opcode for:
157 bal . + (1 + OFFSET) * 4. */
158 #define MIPS_BAL(OFFSET) \
159 ((0x1 << 26) | (0x11 << 16) | (OFFSET))
161 /* Return the usual opcode for a nop. */
164 /* Classifies an address.
167 A natural register + offset address. The register satisfies
168 mips_valid_base_register_p and the offset is a const_arith_operand.
171 A LO_SUM rtx. The first operand is a valid base register and
172 the second operand is a symbolic address.
175 A signed 16-bit constant address.
178 A constant symbolic address. */
179 enum mips_address_type {
186 /* Macros to create an enumeration identifier for a function prototype. */
187 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
188 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
189 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
190 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
192 /* Classifies the prototype of a built-in function. */
193 enum mips_function_type {
194 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
195 #include "config/mips/mips-ftypes.def"
196 #undef DEF_MIPS_FTYPE
200 /* Specifies how a built-in function should be converted into rtl. */
201 enum mips_builtin_type {
202 /* The function corresponds directly to an .md pattern. The return
203 value is mapped to operand 0 and the arguments are mapped to
204 operands 1 and above. */
207 /* The function corresponds directly to an .md pattern. There is no return
208 value and the arguments are mapped to operands 0 and above. */
209 MIPS_BUILTIN_DIRECT_NO_TARGET,
211 /* The function corresponds to a comparison instruction followed by
212 a mips_cond_move_tf_ps pattern. The first two arguments are the
213 values to compare and the second two arguments are the vector
214 operands for the movt.ps or movf.ps instruction (in assembly order). */
218 /* The function corresponds to a V2SF comparison instruction. Operand 0
219 of this instruction is the result of the comparison, which has mode
220 CCV2 or CCV4. The function arguments are mapped to operands 1 and
221 above. The function's return value is an SImode boolean that is
222 true under the following conditions:
224 MIPS_BUILTIN_CMP_ANY: one of the registers is true
225 MIPS_BUILTIN_CMP_ALL: all of the registers are true
226 MIPS_BUILTIN_CMP_LOWER: the first register is true
227 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
228 MIPS_BUILTIN_CMP_ANY,
229 MIPS_BUILTIN_CMP_ALL,
230 MIPS_BUILTIN_CMP_UPPER,
231 MIPS_BUILTIN_CMP_LOWER,
233 /* As above, but the instruction only sets a single $fcc register. */
234 MIPS_BUILTIN_CMP_SINGLE,
236 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
237 MIPS_BUILTIN_BPOSGE32
240 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
241 #define MIPS_FP_CONDITIONS(MACRO) \
259 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
260 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
261 enum mips_fp_condition {
262 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
265 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
266 #define STRINGIFY(X) #X
267 static const char *const mips_fp_conditions[] = {
268 MIPS_FP_CONDITIONS (STRINGIFY)
271 /* Tuning information that is automatically derived from other sources
272 (such as the scheduler). */
274 /* The architecture and tuning settings that this structure describes. */
278 /* True if this structure describes MIPS16 settings. */
281 /* True if the structure has been initialized. */
284 /* True if "MULT $0, $0" is preferable to "MTLO $0; MTHI $0"
285 when optimizing for speed. */
286 bool fast_mult_zero_zero_p;
289 /* Information about a function's frame layout. */
290 struct GTY(()) mips_frame_info {
291 /* The size of the frame in bytes. */
292 HOST_WIDE_INT total_size;
294 /* The number of bytes allocated to variables. */
295 HOST_WIDE_INT var_size;
297 /* The number of bytes allocated to outgoing function arguments. */
298 HOST_WIDE_INT args_size;
300 /* The number of bytes allocated to the .cprestore slot, or 0 if there
302 HOST_WIDE_INT cprestore_size;
304 /* Bit X is set if the function saves or restores GPR X. */
307 /* Likewise FPR X. */
310 /* Likewise doubleword accumulator X ($acX). */
311 unsigned int acc_mask;
313 /* The number of GPRs, FPRs, doubleword accumulators and COP0
317 unsigned int num_acc;
318 unsigned int num_cop0_regs;
320 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
321 save slots from the top of the frame, or zero if no such slots are
323 HOST_WIDE_INT gp_save_offset;
324 HOST_WIDE_INT fp_save_offset;
325 HOST_WIDE_INT acc_save_offset;
326 HOST_WIDE_INT cop0_save_offset;
328 /* Likewise, but giving offsets from the bottom of the frame. */
329 HOST_WIDE_INT gp_sp_offset;
330 HOST_WIDE_INT fp_sp_offset;
331 HOST_WIDE_INT acc_sp_offset;
332 HOST_WIDE_INT cop0_sp_offset;
334 /* Similar, but the value passed to _mcount. */
335 HOST_WIDE_INT ra_fp_offset;
337 /* The offset of arg_pointer_rtx from the bottom of the frame. */
338 HOST_WIDE_INT arg_pointer_offset;
340 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
341 HOST_WIDE_INT hard_frame_pointer_offset;
344 struct GTY(()) machine_function {
345 /* The next floating-point condition-code register to allocate
346 for ISA_HAS_8CC targets, relative to ST_REG_FIRST. */
347 unsigned int next_fcc;
349 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
350 rtx mips16_gp_pseudo_rtx;
352 /* The number of extra stack bytes taken up by register varargs.
353 This area is allocated by the callee at the very top of the frame. */
356 /* The current frame information, calculated by mips_compute_frame_info. */
357 struct mips_frame_info frame;
359 /* The register to use as the function's global pointer, or INVALID_REGNUM
360 if the function doesn't need one. */
361 unsigned int global_pointer;
363 /* How many instructions it takes to load a label into $AT, or 0 if
364 this property hasn't yet been calculated. */
365 unsigned int load_label_num_insns;
367 /* True if mips_adjust_insn_length should ignore an instruction's
369 bool ignore_hazard_length_p;
371 /* True if the whole function is suitable for .set noreorder and
373 bool all_noreorder_p;
375 /* True if the function has "inflexible" and "flexible" references
376 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
377 and mips_cfun_has_flexible_gp_ref_p for details. */
378 bool has_inflexible_gp_insn_p;
379 bool has_flexible_gp_insn_p;
381 /* True if the function's prologue must load the global pointer
382 value into pic_offset_table_rtx and store the same value in
383 the function's cprestore slot (if any). Even if this value
384 is currently false, we may decide to set it to true later;
385 see mips_must_initialize_gp_p () for details. */
386 bool must_initialize_gp_p;
388 /* True if the current function must restore $gp after any potential
389 clobber. This value is only meaningful during the first post-epilogue
390 split_insns pass; see mips_must_initialize_gp_p () for details. */
391 bool must_restore_gp_when_clobbered_p;
393 /* True if this is an interrupt handler. */
394 bool interrupt_handler_p;
396 /* True if this is an interrupt handler that uses shadow registers. */
397 bool use_shadow_register_set_p;
399 /* True if this is an interrupt handler that should keep interrupts
401 bool keep_interrupts_masked_p;
403 /* True if this is an interrupt handler that should use DERET
405 bool use_debug_exception_return_p;
408 /* Information about a single argument. */
409 struct mips_arg_info {
410 /* True if the argument is passed in a floating-point register, or
411 would have been if we hadn't run out of registers. */
414 /* The number of words passed in registers, rounded up. */
415 unsigned int reg_words;
417 /* For EABI, the offset of the first register from GP_ARG_FIRST or
418 FP_ARG_FIRST. For other ABIs, the offset of the first register from
419 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
420 comment for details).
422 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
424 unsigned int reg_offset;
426 /* The number of words that must be passed on the stack, rounded up. */
427 unsigned int stack_words;
429 /* The offset from the start of the stack overflow area of the argument's
430 first stack word. Only meaningful when STACK_WORDS is nonzero. */
431 unsigned int stack_offset;
434 /* Information about an address described by mips_address_type.
440 REG is the base register and OFFSET is the constant offset.
443 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
444 is the type of symbol it references.
447 SYMBOL_TYPE is the type of symbol that the address references. */
448 struct mips_address_info {
449 enum mips_address_type type;
452 enum mips_symbol_type symbol_type;
455 /* One stage in a constant building sequence. These sequences have
459 A = A CODE[1] VALUE[1]
460 A = A CODE[2] VALUE[2]
463 where A is an accumulator, each CODE[i] is a binary rtl operation
464 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
465 struct mips_integer_op {
467 unsigned HOST_WIDE_INT value;
470 /* The largest number of operations needed to load an integer constant.
471 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
472 When the lowest bit is clear, we can try, but reject a sequence with
473 an extra SLL at the end. */
474 #define MIPS_MAX_INTEGER_OPS 7
476 /* Information about a MIPS16e SAVE or RESTORE instruction. */
477 struct mips16e_save_restore_info {
478 /* The number of argument registers saved by a SAVE instruction.
479 0 for RESTORE instructions. */
482 /* Bit X is set if the instruction saves or restores GPR X. */
485 /* The total number of bytes to allocate. */
489 /* Costs of various operations on the different architectures. */
491 struct mips_rtx_cost_data
493 unsigned short fp_add;
494 unsigned short fp_mult_sf;
495 unsigned short fp_mult_df;
496 unsigned short fp_div_sf;
497 unsigned short fp_div_df;
498 unsigned short int_mult_si;
499 unsigned short int_mult_di;
500 unsigned short int_div_si;
501 unsigned short int_div_di;
502 unsigned short branch_cost;
503 unsigned short memory_latency;
506 /* Global variables for machine-dependent things. */
508 /* The -G setting, or the configuration's default small-data limit if
509 no -G option is given. */
510 static unsigned int mips_small_data_threshold;
512 /* The number of file directives written by mips_output_filename. */
513 int num_source_filenames;
515 /* The name that appeared in the last .file directive written by
516 mips_output_filename, or "" if mips_output_filename hasn't
517 written anything yet. */
518 const char *current_function_file = "";
520 /* Arrays that map GCC register numbers to debugger register numbers. */
521 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
522 int mips_dwarf_regno[FIRST_PSEUDO_REGISTER];
524 /* Information about the current function's epilogue, used only while
527 /* A list of queued REG_CFA_RESTORE notes. */
530 /* The CFA is currently defined as CFA_REG + CFA_OFFSET. */
532 HOST_WIDE_INT cfa_offset;
534 /* The offset of the CFA from the stack pointer while restoring
536 HOST_WIDE_INT cfa_restore_sp_offset;
539 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
540 struct mips_asm_switch mips_noreorder = { "reorder", 0 };
541 struct mips_asm_switch mips_nomacro = { "macro", 0 };
542 struct mips_asm_switch mips_noat = { "at", 0 };
544 /* True if we're writing out a branch-likely instruction rather than a
546 static bool mips_branch_likely;
548 /* The current instruction-set architecture. */
549 enum processor mips_arch;
550 const struct mips_cpu_info *mips_arch_info;
552 /* The processor that we should tune the code for. */
553 enum processor mips_tune;
554 const struct mips_cpu_info *mips_tune_info;
556 /* The ISA level associated with mips_arch. */
559 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
560 static const struct mips_cpu_info *mips_isa_option_info;
562 /* Which cost information to use. */
563 static const struct mips_rtx_cost_data *mips_cost;
565 /* The ambient target flags, excluding MASK_MIPS16. */
566 static int mips_base_target_flags;
568 /* The default compression mode. */
569 unsigned int mips_base_compression_flags;
571 /* The ambient values of other global variables. */
572 static int mips_base_schedule_insns; /* flag_schedule_insns */
573 static int mips_base_reorder_blocks_and_partition; /* flag_reorder... */
574 static int mips_base_move_loop_invariants; /* flag_move_loop_invariants */
575 static int mips_base_align_loops; /* align_loops */
576 static int mips_base_align_jumps; /* align_jumps */
577 static int mips_base_align_functions; /* align_functions */
579 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
580 bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
582 /* Index C is true if character C is a valid PRINT_OPERAND punctation
584 static bool mips_print_operand_punct[256];
586 static GTY (()) int mips_output_filename_first_time = 1;
588 /* mips_split_p[X] is true if symbols of type X can be split by
589 mips_split_symbol. */
590 bool mips_split_p[NUM_SYMBOL_TYPES];
592 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
593 can be split by mips_split_symbol. */
594 bool mips_split_hi_p[NUM_SYMBOL_TYPES];
596 /* mips_use_pcrel_pool_p[X] is true if symbols of type X should be
597 forced into a PC-relative constant pool. */
598 bool mips_use_pcrel_pool_p[NUM_SYMBOL_TYPES];
600 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
601 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
602 if they are matched by a special .md file pattern. */
603 const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
605 /* Likewise for HIGHs. */
606 const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
608 /* Target state for MIPS16. */
609 struct target_globals *mips16_globals;
611 /* Cached value of can_issue_more. This is cached in mips_variable_issue hook
612 and returned from mips_sched_reorder2. */
613 static int cached_can_issue_more;
615 /* True if the output uses __mips16_rdhwr. */
616 static bool mips_need_mips16_rdhwr_p;
618 /* Index R is the smallest register class that contains register R. */
619 const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = {
620 LEA_REGS, LEA_REGS, M16_REGS, V1_REG,
621 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
622 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
623 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
624 M16_REGS, M16_REGS, LEA_REGS, LEA_REGS,
625 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
626 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
627 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
628 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
629 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
630 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
631 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
632 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
633 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
634 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
635 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
636 MD0_REG, MD1_REG, NO_REGS, ST_REGS,
637 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
638 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
639 NO_REGS, FRAME_REGS, FRAME_REGS, NO_REGS,
640 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
641 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
642 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
643 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
644 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
645 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
646 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
647 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
648 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
649 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
650 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
651 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
652 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
653 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
654 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
655 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
656 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
657 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
658 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
659 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
660 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
661 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
662 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
663 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
664 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
665 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
666 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
669 /* The value of TARGET_ATTRIBUTE_TABLE. */
670 static const struct attribute_spec mips_attribute_table[] = {
671 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
673 { "long_call", 0, 0, false, true, true, NULL, false },
674 { "far", 0, 0, false, true, true, NULL, false },
675 { "near", 0, 0, false, true, true, NULL, false },
676 /* We would really like to treat "mips16" and "nomips16" as type
677 attributes, but GCC doesn't provide the hooks we need to support
678 the right conversion rules. As declaration attributes, they affect
679 code generation but don't carry other semantics. */
680 { "mips16", 0, 0, true, false, false, NULL, false },
681 { "nomips16", 0, 0, true, false, false, NULL, false },
682 { "micromips", 0, 0, true, false, false, NULL, false },
683 { "nomicromips", 0, 0, true, false, false, NULL, false },
684 { "nocompression", 0, 0, true, false, false, NULL, false },
685 /* Allow functions to be specified as interrupt handlers */
686 { "interrupt", 0, 0, false, true, true, NULL, false },
687 { "use_shadow_register_set", 0, 0, false, true, true, NULL, false },
688 { "keep_interrupts_masked", 0, 0, false, true, true, NULL, false },
689 { "use_debug_exception_return", 0, 0, false, true, true, NULL, false },
690 { NULL, 0, 0, false, false, false, NULL, false }
693 /* A table describing all the processors GCC knows about; see
694 mips-cpus.def for details. */
695 static const struct mips_cpu_info mips_cpu_info_table[] = {
696 #define MIPS_CPU(NAME, CPU, ISA, FLAGS) \
697 { NAME, CPU, ISA, FLAGS },
698 #include "mips-cpus.def"
702 /* Default costs. If these are used for a processor we should look
703 up the actual costs. */
704 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
705 COSTS_N_INSNS (7), /* fp_mult_sf */ \
706 COSTS_N_INSNS (8), /* fp_mult_df */ \
707 COSTS_N_INSNS (23), /* fp_div_sf */ \
708 COSTS_N_INSNS (36), /* fp_div_df */ \
709 COSTS_N_INSNS (10), /* int_mult_si */ \
710 COSTS_N_INSNS (10), /* int_mult_di */ \
711 COSTS_N_INSNS (69), /* int_div_si */ \
712 COSTS_N_INSNS (69), /* int_div_di */ \
713 2, /* branch_cost */ \
714 4 /* memory_latency */
716 /* Floating-point costs for processors without an FPU. Just assume that
717 all floating-point libcalls are very expensive. */
718 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
719 COSTS_N_INSNS (256), /* fp_mult_sf */ \
720 COSTS_N_INSNS (256), /* fp_mult_df */ \
721 COSTS_N_INSNS (256), /* fp_div_sf */ \
722 COSTS_N_INSNS (256) /* fp_div_df */
724 /* Costs to use when optimizing for size. */
725 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size = {
726 COSTS_N_INSNS (1), /* fp_add */
727 COSTS_N_INSNS (1), /* fp_mult_sf */
728 COSTS_N_INSNS (1), /* fp_mult_df */
729 COSTS_N_INSNS (1), /* fp_div_sf */
730 COSTS_N_INSNS (1), /* fp_div_df */
731 COSTS_N_INSNS (1), /* int_mult_si */
732 COSTS_N_INSNS (1), /* int_mult_di */
733 COSTS_N_INSNS (1), /* int_div_si */
734 COSTS_N_INSNS (1), /* int_div_di */
736 4 /* memory_latency */
739 /* Costs to use when optimizing for speed, indexed by processor. */
740 static const struct mips_rtx_cost_data
741 mips_rtx_cost_data[NUM_PROCESSOR_VALUES] = {
743 COSTS_N_INSNS (2), /* fp_add */
744 COSTS_N_INSNS (4), /* fp_mult_sf */
745 COSTS_N_INSNS (5), /* fp_mult_df */
746 COSTS_N_INSNS (12), /* fp_div_sf */
747 COSTS_N_INSNS (19), /* fp_div_df */
748 COSTS_N_INSNS (12), /* int_mult_si */
749 COSTS_N_INSNS (12), /* int_mult_di */
750 COSTS_N_INSNS (35), /* int_div_si */
751 COSTS_N_INSNS (35), /* int_div_di */
753 4 /* memory_latency */
757 COSTS_N_INSNS (6), /* int_mult_si */
758 COSTS_N_INSNS (6), /* int_mult_di */
759 COSTS_N_INSNS (36), /* int_div_si */
760 COSTS_N_INSNS (36), /* int_div_di */
762 4 /* memory_latency */
766 COSTS_N_INSNS (36), /* int_mult_si */
767 COSTS_N_INSNS (36), /* int_mult_di */
768 COSTS_N_INSNS (37), /* int_div_si */
769 COSTS_N_INSNS (37), /* int_div_di */
771 4 /* memory_latency */
775 COSTS_N_INSNS (4), /* int_mult_si */
776 COSTS_N_INSNS (11), /* int_mult_di */
777 COSTS_N_INSNS (36), /* int_div_si */
778 COSTS_N_INSNS (68), /* int_div_di */
780 4 /* memory_latency */
783 COSTS_N_INSNS (4), /* fp_add */
784 COSTS_N_INSNS (4), /* fp_mult_sf */
785 COSTS_N_INSNS (5), /* fp_mult_df */
786 COSTS_N_INSNS (17), /* fp_div_sf */
787 COSTS_N_INSNS (32), /* fp_div_df */
788 COSTS_N_INSNS (4), /* int_mult_si */
789 COSTS_N_INSNS (11), /* int_mult_di */
790 COSTS_N_INSNS (36), /* int_div_si */
791 COSTS_N_INSNS (68), /* int_div_di */
793 4 /* memory_latency */
796 COSTS_N_INSNS (4), /* fp_add */
797 COSTS_N_INSNS (4), /* fp_mult_sf */
798 COSTS_N_INSNS (5), /* fp_mult_df */
799 COSTS_N_INSNS (17), /* fp_div_sf */
800 COSTS_N_INSNS (32), /* fp_div_df */
801 COSTS_N_INSNS (4), /* int_mult_si */
802 COSTS_N_INSNS (7), /* int_mult_di */
803 COSTS_N_INSNS (42), /* int_div_si */
804 COSTS_N_INSNS (72), /* int_div_di */
806 4 /* memory_latency */
810 COSTS_N_INSNS (5), /* int_mult_si */
811 COSTS_N_INSNS (5), /* int_mult_di */
812 COSTS_N_INSNS (41), /* int_div_si */
813 COSTS_N_INSNS (41), /* int_div_di */
815 4 /* memory_latency */
818 COSTS_N_INSNS (8), /* fp_add */
819 COSTS_N_INSNS (8), /* fp_mult_sf */
820 COSTS_N_INSNS (10), /* fp_mult_df */
821 COSTS_N_INSNS (34), /* fp_div_sf */
822 COSTS_N_INSNS (64), /* fp_div_df */
823 COSTS_N_INSNS (5), /* int_mult_si */
824 COSTS_N_INSNS (5), /* int_mult_di */
825 COSTS_N_INSNS (41), /* int_div_si */
826 COSTS_N_INSNS (41), /* int_div_di */
828 4 /* memory_latency */
831 COSTS_N_INSNS (4), /* fp_add */
832 COSTS_N_INSNS (4), /* fp_mult_sf */
833 COSTS_N_INSNS (5), /* fp_mult_df */
834 COSTS_N_INSNS (17), /* fp_div_sf */
835 COSTS_N_INSNS (32), /* fp_div_df */
836 COSTS_N_INSNS (5), /* int_mult_si */
837 COSTS_N_INSNS (5), /* int_mult_di */
838 COSTS_N_INSNS (41), /* int_div_si */
839 COSTS_N_INSNS (41), /* int_div_di */
841 4 /* memory_latency */
845 COSTS_N_INSNS (5), /* int_mult_si */
846 COSTS_N_INSNS (5), /* int_mult_di */
847 COSTS_N_INSNS (41), /* int_div_si */
848 COSTS_N_INSNS (41), /* int_div_di */
850 4 /* memory_latency */
853 COSTS_N_INSNS (8), /* fp_add */
854 COSTS_N_INSNS (8), /* fp_mult_sf */
855 COSTS_N_INSNS (10), /* fp_mult_df */
856 COSTS_N_INSNS (34), /* fp_div_sf */
857 COSTS_N_INSNS (64), /* fp_div_df */
858 COSTS_N_INSNS (5), /* int_mult_si */
859 COSTS_N_INSNS (5), /* int_mult_di */
860 COSTS_N_INSNS (41), /* int_div_si */
861 COSTS_N_INSNS (41), /* int_div_di */
863 4 /* memory_latency */
866 COSTS_N_INSNS (4), /* fp_add */
867 COSTS_N_INSNS (4), /* fp_mult_sf */
868 COSTS_N_INSNS (5), /* fp_mult_df */
869 COSTS_N_INSNS (17), /* fp_div_sf */
870 COSTS_N_INSNS (32), /* fp_div_df */
871 COSTS_N_INSNS (5), /* int_mult_si */
872 COSTS_N_INSNS (5), /* int_mult_di */
873 COSTS_N_INSNS (41), /* int_div_si */
874 COSTS_N_INSNS (41), /* int_div_di */
876 4 /* memory_latency */
879 COSTS_N_INSNS (6), /* fp_add */
880 COSTS_N_INSNS (6), /* fp_mult_sf */
881 COSTS_N_INSNS (7), /* fp_mult_df */
882 COSTS_N_INSNS (25), /* fp_div_sf */
883 COSTS_N_INSNS (48), /* fp_div_df */
884 COSTS_N_INSNS (5), /* int_mult_si */
885 COSTS_N_INSNS (5), /* int_mult_di */
886 COSTS_N_INSNS (41), /* int_div_si */
887 COSTS_N_INSNS (41), /* int_div_di */
889 4 /* memory_latency */
906 COSTS_N_INSNS (5), /* int_mult_si */
907 COSTS_N_INSNS (5), /* int_mult_di */
908 COSTS_N_INSNS (72), /* int_div_si */
909 COSTS_N_INSNS (72), /* int_div_di */
911 4 /* memory_latency */
916 COSTS_N_INSNS (6), /* int_mult_si */
917 COSTS_N_INSNS (6), /* int_mult_di */
918 COSTS_N_INSNS (18), /* int_div_si */
919 COSTS_N_INSNS (35), /* int_div_di */
921 4 /* memory_latency */
924 COSTS_N_INSNS (2), /* fp_add */
925 COSTS_N_INSNS (4), /* fp_mult_sf */
926 COSTS_N_INSNS (5), /* fp_mult_df */
927 COSTS_N_INSNS (12), /* fp_div_sf */
928 COSTS_N_INSNS (19), /* fp_div_df */
929 COSTS_N_INSNS (2), /* int_mult_si */
930 COSTS_N_INSNS (2), /* int_mult_di */
931 COSTS_N_INSNS (35), /* int_div_si */
932 COSTS_N_INSNS (35), /* int_div_di */
934 4 /* memory_latency */
937 COSTS_N_INSNS (3), /* fp_add */
938 COSTS_N_INSNS (5), /* fp_mult_sf */
939 COSTS_N_INSNS (6), /* fp_mult_df */
940 COSTS_N_INSNS (15), /* fp_div_sf */
941 COSTS_N_INSNS (16), /* fp_div_df */
942 COSTS_N_INSNS (17), /* int_mult_si */
943 COSTS_N_INSNS (17), /* int_mult_di */
944 COSTS_N_INSNS (38), /* int_div_si */
945 COSTS_N_INSNS (38), /* int_div_di */
947 6 /* memory_latency */
950 COSTS_N_INSNS (6), /* fp_add */
951 COSTS_N_INSNS (7), /* fp_mult_sf */
952 COSTS_N_INSNS (8), /* fp_mult_df */
953 COSTS_N_INSNS (23), /* fp_div_sf */
954 COSTS_N_INSNS (36), /* fp_div_df */
955 COSTS_N_INSNS (10), /* int_mult_si */
956 COSTS_N_INSNS (10), /* int_mult_di */
957 COSTS_N_INSNS (69), /* int_div_si */
958 COSTS_N_INSNS (69), /* int_div_di */
960 6 /* memory_latency */
972 /* The only costs that appear to be updated here are
973 integer multiplication. */
975 COSTS_N_INSNS (4), /* int_mult_si */
976 COSTS_N_INSNS (6), /* int_mult_di */
977 COSTS_N_INSNS (69), /* int_div_si */
978 COSTS_N_INSNS (69), /* int_div_di */
980 4 /* memory_latency */
995 COSTS_N_INSNS (6), /* fp_add */
996 COSTS_N_INSNS (4), /* fp_mult_sf */
997 COSTS_N_INSNS (5), /* fp_mult_df */
998 COSTS_N_INSNS (23), /* fp_div_sf */
999 COSTS_N_INSNS (36), /* fp_div_df */
1000 COSTS_N_INSNS (5), /* int_mult_si */
1001 COSTS_N_INSNS (5), /* int_mult_di */
1002 COSTS_N_INSNS (36), /* int_div_si */
1003 COSTS_N_INSNS (36), /* int_div_di */
1004 1, /* branch_cost */
1005 4 /* memory_latency */
1008 COSTS_N_INSNS (6), /* fp_add */
1009 COSTS_N_INSNS (5), /* fp_mult_sf */
1010 COSTS_N_INSNS (6), /* fp_mult_df */
1011 COSTS_N_INSNS (30), /* fp_div_sf */
1012 COSTS_N_INSNS (59), /* fp_div_df */
1013 COSTS_N_INSNS (3), /* int_mult_si */
1014 COSTS_N_INSNS (4), /* int_mult_di */
1015 COSTS_N_INSNS (42), /* int_div_si */
1016 COSTS_N_INSNS (74), /* int_div_di */
1017 1, /* branch_cost */
1018 4 /* memory_latency */
1021 COSTS_N_INSNS (6), /* fp_add */
1022 COSTS_N_INSNS (5), /* fp_mult_sf */
1023 COSTS_N_INSNS (6), /* fp_mult_df */
1024 COSTS_N_INSNS (30), /* fp_div_sf */
1025 COSTS_N_INSNS (59), /* fp_div_df */
1026 COSTS_N_INSNS (5), /* int_mult_si */
1027 COSTS_N_INSNS (9), /* int_mult_di */
1028 COSTS_N_INSNS (42), /* int_div_si */
1029 COSTS_N_INSNS (74), /* int_div_di */
1030 1, /* branch_cost */
1031 4 /* memory_latency */
1034 COSTS_N_INSNS (4), /* fp_add */
1035 COSTS_N_INSNS (4), /* fp_mult_sf */
1036 COSTS_N_INSNS (256), /* fp_mult_df */
1037 COSTS_N_INSNS (8), /* fp_div_sf */
1038 COSTS_N_INSNS (256), /* fp_div_df */
1039 COSTS_N_INSNS (4), /* int_mult_si */
1040 COSTS_N_INSNS (256), /* int_mult_di */
1041 COSTS_N_INSNS (37), /* int_div_si */
1042 COSTS_N_INSNS (256), /* int_div_di */
1043 1, /* branch_cost */
1044 4 /* memory_latency */
1047 /* The only costs that are changed here are
1048 integer multiplication. */
1049 COSTS_N_INSNS (6), /* fp_add */
1050 COSTS_N_INSNS (7), /* fp_mult_sf */
1051 COSTS_N_INSNS (8), /* fp_mult_df */
1052 COSTS_N_INSNS (23), /* fp_div_sf */
1053 COSTS_N_INSNS (36), /* fp_div_df */
1054 COSTS_N_INSNS (5), /* int_mult_si */
1055 COSTS_N_INSNS (9), /* int_mult_di */
1056 COSTS_N_INSNS (69), /* int_div_si */
1057 COSTS_N_INSNS (69), /* int_div_di */
1058 1, /* branch_cost */
1059 4 /* memory_latency */
1065 /* The only costs that are changed here are
1066 integer multiplication. */
1067 COSTS_N_INSNS (6), /* fp_add */
1068 COSTS_N_INSNS (7), /* fp_mult_sf */
1069 COSTS_N_INSNS (8), /* fp_mult_df */
1070 COSTS_N_INSNS (23), /* fp_div_sf */
1071 COSTS_N_INSNS (36), /* fp_div_df */
1072 COSTS_N_INSNS (3), /* int_mult_si */
1073 COSTS_N_INSNS (8), /* int_mult_di */
1074 COSTS_N_INSNS (69), /* int_div_si */
1075 COSTS_N_INSNS (69), /* int_div_di */
1076 1, /* branch_cost */
1077 4 /* memory_latency */
1080 COSTS_N_INSNS (2), /* fp_add */
1081 COSTS_N_INSNS (2), /* fp_mult_sf */
1082 COSTS_N_INSNS (2), /* fp_mult_df */
1083 COSTS_N_INSNS (12), /* fp_div_sf */
1084 COSTS_N_INSNS (19), /* fp_div_df */
1085 COSTS_N_INSNS (5), /* int_mult_si */
1086 COSTS_N_INSNS (9), /* int_mult_di */
1087 COSTS_N_INSNS (34), /* int_div_si */
1088 COSTS_N_INSNS (66), /* int_div_di */
1089 1, /* branch_cost */
1090 4 /* memory_latency */
1093 /* These costs are the same as the SB-1A below. */
1094 COSTS_N_INSNS (4), /* fp_add */
1095 COSTS_N_INSNS (4), /* fp_mult_sf */
1096 COSTS_N_INSNS (4), /* fp_mult_df */
1097 COSTS_N_INSNS (24), /* fp_div_sf */
1098 COSTS_N_INSNS (32), /* fp_div_df */
1099 COSTS_N_INSNS (3), /* int_mult_si */
1100 COSTS_N_INSNS (4), /* int_mult_di */
1101 COSTS_N_INSNS (36), /* int_div_si */
1102 COSTS_N_INSNS (68), /* int_div_di */
1103 1, /* branch_cost */
1104 4 /* memory_latency */
1107 /* These costs are the same as the SB-1 above. */
1108 COSTS_N_INSNS (4), /* fp_add */
1109 COSTS_N_INSNS (4), /* fp_mult_sf */
1110 COSTS_N_INSNS (4), /* fp_mult_df */
1111 COSTS_N_INSNS (24), /* fp_div_sf */
1112 COSTS_N_INSNS (32), /* fp_div_df */
1113 COSTS_N_INSNS (3), /* int_mult_si */
1114 COSTS_N_INSNS (4), /* int_mult_di */
1115 COSTS_N_INSNS (36), /* int_div_si */
1116 COSTS_N_INSNS (68), /* int_div_di */
1117 1, /* branch_cost */
1118 4 /* memory_latency */
1125 COSTS_N_INSNS (8), /* int_mult_si */
1126 COSTS_N_INSNS (8), /* int_mult_di */
1127 COSTS_N_INSNS (72), /* int_div_si */
1128 COSTS_N_INSNS (72), /* int_div_di */
1129 1, /* branch_cost */
1130 4 /* memory_latency */
1133 /* These costs are the same as 5KF above. */
1134 COSTS_N_INSNS (4), /* fp_add */
1135 COSTS_N_INSNS (4), /* fp_mult_sf */
1136 COSTS_N_INSNS (5), /* fp_mult_df */
1137 COSTS_N_INSNS (17), /* fp_div_sf */
1138 COSTS_N_INSNS (32), /* fp_div_df */
1139 COSTS_N_INSNS (4), /* int_mult_si */
1140 COSTS_N_INSNS (11), /* int_mult_di */
1141 COSTS_N_INSNS (36), /* int_div_si */
1142 COSTS_N_INSNS (68), /* int_div_di */
1143 1, /* branch_cost */
1144 4 /* memory_latency */
1148 static rtx mips_find_pic_call_symbol (rtx, rtx, bool);
1149 static int mips_register_move_cost (enum machine_mode, reg_class_t,
1151 static unsigned int mips_function_arg_boundary (enum machine_mode, const_tree);
1153 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1154 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1155 struct GTY (()) mflip_mips16_entry {
1159 static GTY ((param_is (struct mflip_mips16_entry))) htab_t mflip_mips16_htab;
1161 /* Hash table callbacks for mflip_mips16_htab. */
1164 mflip_mips16_htab_hash (const void *entry)
1166 return htab_hash_string (((const struct mflip_mips16_entry *) entry)->name);
1170 mflip_mips16_htab_eq (const void *entry, const void *name)
1172 return strcmp (((const struct mflip_mips16_entry *) entry)->name,
1173 (const char *) name) == 0;
1176 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1177 mode, false if it should next add an attribute for the opposite mode. */
1178 static GTY(()) bool mips16_flipper;
1180 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1181 for -mflip-mips16. Return true if it should use "mips16" and false if
1182 it should use "nomips16". */
1185 mflip_mips16_use_mips16_p (tree decl)
1187 struct mflip_mips16_entry *entry;
1191 bool base_is_mips16 = (mips_base_compression_flags & MASK_MIPS16) != 0;
1193 /* Use the opposite of the command-line setting for anonymous decls. */
1194 if (!DECL_NAME (decl))
1195 return !base_is_mips16;
1197 if (!mflip_mips16_htab)
1198 mflip_mips16_htab = htab_create_ggc (37, mflip_mips16_htab_hash,
1199 mflip_mips16_htab_eq, NULL);
1201 name = IDENTIFIER_POINTER (DECL_NAME (decl));
1202 hash = htab_hash_string (name);
1203 slot = htab_find_slot_with_hash (mflip_mips16_htab, name, hash, INSERT);
1204 entry = (struct mflip_mips16_entry *) *slot;
1207 mips16_flipper = !mips16_flipper;
1208 entry = ggc_alloc_mflip_mips16_entry ();
1210 entry->mips16_p = mips16_flipper ? !base_is_mips16 : base_is_mips16;
1213 return entry->mips16_p;
1216 /* Predicates to test for presence of "near" and "far"/"long_call"
1217 attributes on the given TYPE. */
1220 mips_near_type_p (const_tree type)
1222 return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL;
1226 mips_far_type_p (const_tree type)
1228 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL
1229 || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL);
1233 /* Check if the interrupt attribute is set for a function. */
1236 mips_interrupt_type_p (tree type)
1238 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type)) != NULL;
1241 /* Check if the attribute to use shadow register set is set for a function. */
1244 mips_use_shadow_register_set_p (tree type)
1246 return lookup_attribute ("use_shadow_register_set",
1247 TYPE_ATTRIBUTES (type)) != NULL;
1250 /* Check if the attribute to keep interrupts masked is set for a function. */
1253 mips_keep_interrupts_masked_p (tree type)
1255 return lookup_attribute ("keep_interrupts_masked",
1256 TYPE_ATTRIBUTES (type)) != NULL;
1259 /* Check if the attribute to use debug exception return is set for
1263 mips_use_debug_exception_return_p (tree type)
1265 return lookup_attribute ("use_debug_exception_return",
1266 TYPE_ATTRIBUTES (type)) != NULL;
1269 /* Return the set of compression modes that are explicitly required
1270 by the attributes in ATTRIBUTES. */
1273 mips_get_compress_on_flags (tree attributes)
1275 unsigned int flags = 0;
1277 if (lookup_attribute ("mips16", attributes) != NULL)
1278 flags |= MASK_MIPS16;
1280 if (lookup_attribute ("micromips", attributes) != NULL)
1281 flags |= MASK_MICROMIPS;
1286 /* Return the set of compression modes that are explicitly forbidden
1287 by the attributes in ATTRIBUTES. */
1290 mips_get_compress_off_flags (tree attributes)
1292 unsigned int flags = 0;
1294 if (lookup_attribute ("nocompression", attributes) != NULL)
1295 flags |= MASK_MIPS16 | MASK_MICROMIPS;
1297 if (lookup_attribute ("nomips16", attributes) != NULL)
1298 flags |= MASK_MIPS16;
1300 if (lookup_attribute ("nomicromips", attributes) != NULL)
1301 flags |= MASK_MICROMIPS;
1306 /* Return the compression mode that should be used for function DECL.
1307 Return the ambient setting if DECL is null. */
1310 mips_get_compress_mode (tree decl)
1312 unsigned int flags, force_on;
1314 flags = mips_base_compression_flags;
1317 /* Nested functions must use the same frame pointer as their
1318 parent and must therefore use the same ISA mode. */
1319 tree parent = decl_function_context (decl);
1322 force_on = mips_get_compress_on_flags (DECL_ATTRIBUTES (decl));
1325 flags &= ~mips_get_compress_off_flags (DECL_ATTRIBUTES (decl));
1330 /* Return the attribute name associated with MASK_MIPS16 and MASK_MICROMIPS
1334 mips_get_compress_on_name (unsigned int flags)
1336 if (flags == MASK_MIPS16)
1341 /* Return the attribute name that forbids MASK_MIPS16 and MASK_MICROMIPS
1345 mips_get_compress_off_name (unsigned int flags)
1347 if (flags == MASK_MIPS16)
1349 if (flags == MASK_MICROMIPS)
1350 return "nomicromips";
1351 return "nocompression";
1354 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1357 mips_comp_type_attributes (const_tree type1, const_tree type2)
1359 /* Disallow mixed near/far attributes. */
1360 if (mips_far_type_p (type1) && mips_near_type_p (type2))
1362 if (mips_near_type_p (type1) && mips_far_type_p (type2))
1367 /* Implement TARGET_INSERT_ATTRIBUTES. */
1370 mips_insert_attributes (tree decl, tree *attributes)
1373 unsigned int compression_flags, nocompression_flags;
1375 /* Check for "mips16" and "nomips16" attributes. */
1376 compression_flags = mips_get_compress_on_flags (*attributes);
1377 nocompression_flags = mips_get_compress_off_flags (*attributes);
1379 if (TREE_CODE (decl) != FUNCTION_DECL)
1381 if (nocompression_flags)
1382 error ("%qs attribute only applies to functions",
1383 mips_get_compress_off_name (nocompression_flags));
1385 if (compression_flags)
1386 error ("%qs attribute only applies to functions",
1387 mips_get_compress_on_name (nocompression_flags));
1391 compression_flags |= mips_get_compress_on_flags (DECL_ATTRIBUTES (decl));
1392 nocompression_flags |=
1393 mips_get_compress_off_flags (DECL_ATTRIBUTES (decl));
1395 if (compression_flags && nocompression_flags)
1396 error ("%qE cannot have both %qs and %qs attributes",
1397 DECL_NAME (decl), mips_get_compress_on_name (compression_flags),
1398 mips_get_compress_off_name (nocompression_flags));
1400 if (compression_flags & MASK_MIPS16
1401 && compression_flags & MASK_MICROMIPS)
1402 error ("%qE cannot have both %qs and %qs attributes",
1403 DECL_NAME (decl), "mips16", "micromips");
1405 if (TARGET_FLIP_MIPS16
1406 && !DECL_ARTIFICIAL (decl)
1407 && compression_flags == 0
1408 && nocompression_flags == 0)
1410 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1411 "mips16" attribute, arbitrarily pick one. We must pick the same
1412 setting for duplicate declarations of a function. */
1413 name = mflip_mips16_use_mips16_p (decl) ? "mips16" : "nomips16";
1414 *attributes = tree_cons (get_identifier (name), NULL, *attributes);
1415 name = "nomicromips";
1416 *attributes = tree_cons (get_identifier (name), NULL, *attributes);
1421 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1424 mips_merge_decl_attributes (tree olddecl, tree newdecl)
1428 diff = (mips_get_compress_on_flags (DECL_ATTRIBUTES (olddecl))
1429 ^ mips_get_compress_on_flags (DECL_ATTRIBUTES (newdecl)));
1431 error ("%qE redeclared with conflicting %qs attributes",
1432 DECL_NAME (newdecl), mips_get_compress_on_name (diff));
1434 diff = (mips_get_compress_off_flags (DECL_ATTRIBUTES (olddecl))
1435 ^ mips_get_compress_off_flags (DECL_ATTRIBUTES (newdecl)));
1437 error ("%qE redeclared with conflicting %qs attributes",
1438 DECL_NAME (newdecl), mips_get_compress_off_name (diff));
1440 return merge_attributes (DECL_ATTRIBUTES (olddecl),
1441 DECL_ATTRIBUTES (newdecl));
1444 /* Implement TARGET_CAN_INLINE_P. */
1447 mips_can_inline_p (tree caller, tree callee)
1449 if (mips_get_compress_mode (callee) != mips_get_compress_mode (caller))
1451 return default_target_can_inline_p (caller, callee);
1454 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1455 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1458 mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr)
1460 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
1462 *base_ptr = XEXP (x, 0);
1463 *offset_ptr = INTVAL (XEXP (x, 1));
1472 static unsigned int mips_build_integer (struct mips_integer_op *,
1473 unsigned HOST_WIDE_INT);
1475 /* A subroutine of mips_build_integer, with the same interface.
1476 Assume that the final action in the sequence should be a left shift. */
1479 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1481 unsigned int i, shift;
1483 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1484 since signed numbers are easier to load than unsigned ones. */
1486 while ((value & 1) == 0)
1487 value /= 2, shift++;
1489 i = mips_build_integer (codes, value);
1490 codes[i].code = ASHIFT;
1491 codes[i].value = shift;
1495 /* As for mips_build_shift, but assume that the final action will be
1496 an IOR or PLUS operation. */
1499 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1501 unsigned HOST_WIDE_INT high;
1504 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1505 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
1507 /* The constant is too complex to load with a simple LUI/ORI pair,
1508 so we want to give the recursive call as many trailing zeros as
1509 possible. In this case, we know bit 16 is set and that the
1510 low 16 bits form a negative number. If we subtract that number
1511 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1512 i = mips_build_integer (codes, CONST_HIGH_PART (value));
1513 codes[i].code = PLUS;
1514 codes[i].value = CONST_LOW_PART (value);
1518 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1519 bits gives a value with at least 17 trailing zeros. */
1520 i = mips_build_integer (codes, high);
1521 codes[i].code = IOR;
1522 codes[i].value = value & 0xffff;
1527 /* Fill CODES with a sequence of rtl operations to load VALUE.
1528 Return the number of operations needed. */
1531 mips_build_integer (struct mips_integer_op *codes,
1532 unsigned HOST_WIDE_INT value)
1534 if (SMALL_OPERAND (value)
1535 || SMALL_OPERAND_UNSIGNED (value)
1536 || LUI_OPERAND (value))
1538 /* The value can be loaded with a single instruction. */
1539 codes[0].code = UNKNOWN;
1540 codes[0].value = value;
1543 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
1545 /* Either the constant is a simple LUI/ORI combination or its
1546 lowest bit is set. We don't want to shift in this case. */
1547 return mips_build_lower (codes, value);
1549 else if ((value & 0xffff) == 0)
1551 /* The constant will need at least three actions. The lowest
1552 16 bits are clear, so the final action will be a shift. */
1553 return mips_build_shift (codes, value);
1557 /* The final action could be a shift, add or inclusive OR.
1558 Rather than use a complex condition to select the best
1559 approach, try both mips_build_shift and mips_build_lower
1560 and pick the one that gives the shortest sequence.
1561 Note that this case is only used once per constant. */
1562 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1563 unsigned int cost, alt_cost;
1565 cost = mips_build_shift (codes, value);
1566 alt_cost = mips_build_lower (alt_codes, value);
1567 if (alt_cost < cost)
1569 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
1576 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
1579 mips_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
1581 return mips_const_insns (x) > 0;
1584 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
1587 mips16_stub_function (const char *name)
1591 x = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
1592 SYMBOL_REF_FLAGS (x) |= (SYMBOL_FLAG_EXTERNAL | SYMBOL_FLAG_FUNCTION);
1596 /* Return true if symbols of type TYPE require a GOT access. */
1599 mips_got_symbol_type_p (enum mips_symbol_type type)
1603 case SYMBOL_GOT_PAGE_OFST:
1604 case SYMBOL_GOT_DISP:
1612 /* Return true if X is a thread-local symbol. */
1615 mips_tls_symbol_p (rtx x)
1617 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1620 /* Return true if SYMBOL_REF X is associated with a global symbol
1621 (in the STB_GLOBAL sense). */
1624 mips_global_symbol_p (const_rtx x)
1626 const_tree decl = SYMBOL_REF_DECL (x);
1629 return !SYMBOL_REF_LOCAL_P (x) || SYMBOL_REF_EXTERNAL_P (x);
1631 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1632 or weak symbols. Relocations in the object file will be against
1633 the target symbol, so it's that symbol's binding that matters here. */
1634 return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl));
1637 /* Return true if function X is a libgcc MIPS16 stub function. */
1640 mips16_stub_function_p (const_rtx x)
1642 return (GET_CODE (x) == SYMBOL_REF
1643 && strncmp (XSTR (x, 0), "__mips16_", 9) == 0);
1646 /* Return true if function X is a locally-defined and locally-binding
1650 mips16_local_function_p (const_rtx x)
1652 return (GET_CODE (x) == SYMBOL_REF
1653 && SYMBOL_REF_LOCAL_P (x)
1654 && !SYMBOL_REF_EXTERNAL_P (x)
1655 && (mips_get_compress_mode (SYMBOL_REF_DECL (x)) & MASK_MIPS16));
1658 /* Return true if SYMBOL_REF X binds locally. */
1661 mips_symbol_binds_local_p (const_rtx x)
1663 return (SYMBOL_REF_DECL (x)
1664 ? targetm.binds_local_p (SYMBOL_REF_DECL (x))
1665 : SYMBOL_REF_LOCAL_P (x));
1668 /* Return true if rtx constants of mode MODE should be put into a small
1672 mips_rtx_constant_in_small_data_p (enum machine_mode mode)
1674 return (!TARGET_EMBEDDED_DATA
1675 && TARGET_LOCAL_SDATA
1676 && GET_MODE_SIZE (mode) <= mips_small_data_threshold);
1679 /* Return true if X should not be moved directly into register $25.
1680 We need this because many versions of GAS will treat "la $25,foo" as
1681 part of a call sequence and so allow a global "foo" to be lazily bound. */
1684 mips_dangerous_for_la25_p (rtx x)
1686 return (!TARGET_EXPLICIT_RELOCS
1688 && GET_CODE (x) == SYMBOL_REF
1689 && mips_global_symbol_p (x));
1692 /* Return true if calls to X might need $25 to be valid on entry. */
1695 mips_use_pic_fn_addr_reg_p (const_rtx x)
1697 if (!TARGET_USE_PIC_FN_ADDR_REG)
1700 /* MIPS16 stub functions are guaranteed not to use $25. */
1701 if (mips16_stub_function_p (x))
1704 if (GET_CODE (x) == SYMBOL_REF)
1706 /* If PLTs and copy relocations are available, the static linker
1707 will make sure that $25 is valid on entry to the target function. */
1708 if (TARGET_ABICALLS_PIC0)
1711 /* Locally-defined functions use absolute accesses to set up
1712 the global pointer. */
1713 if (TARGET_ABSOLUTE_ABICALLS
1714 && mips_symbol_binds_local_p (x)
1715 && !SYMBOL_REF_EXTERNAL_P (x))
1722 /* Return the method that should be used to access SYMBOL_REF or
1723 LABEL_REF X in context CONTEXT. */
1725 static enum mips_symbol_type
1726 mips_classify_symbol (const_rtx x, enum mips_symbol_context context)
1729 return SYMBOL_GOT_DISP;
1731 if (GET_CODE (x) == LABEL_REF)
1733 /* Only return SYMBOL_PC_RELATIVE if we are generating MIPS16
1734 code and if we know that the label is in the current function's
1735 text section. LABEL_REFs are used for jump tables as well as
1736 text labels, so we must check whether jump tables live in the
1738 if (TARGET_MIPS16_SHORT_JUMP_TABLES
1739 && !LABEL_REF_NONLOCAL_P (x))
1740 return SYMBOL_PC_RELATIVE;
1742 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1743 return SYMBOL_GOT_PAGE_OFST;
1745 return SYMBOL_ABSOLUTE;
1748 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1750 if (SYMBOL_REF_TLS_MODEL (x))
1753 if (CONSTANT_POOL_ADDRESS_P (x))
1755 if (TARGET_MIPS16_TEXT_LOADS)
1756 return SYMBOL_PC_RELATIVE;
1758 if (TARGET_MIPS16_PCREL_LOADS && context == SYMBOL_CONTEXT_MEM)
1759 return SYMBOL_PC_RELATIVE;
1761 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x)))
1762 return SYMBOL_GP_RELATIVE;
1765 /* Do not use small-data accesses for weak symbols; they may end up
1767 if (TARGET_GPOPT && SYMBOL_REF_SMALL_P (x) && !SYMBOL_REF_WEAK (x))
1768 return SYMBOL_GP_RELATIVE;
1770 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1772 if (TARGET_ABICALLS_PIC2
1773 && !(TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x)))
1775 /* There are three cases to consider:
1777 - o32 PIC (either with or without explicit relocs)
1778 - n32/n64 PIC without explicit relocs
1779 - n32/n64 PIC with explicit relocs
1781 In the first case, both local and global accesses will use an
1782 R_MIPS_GOT16 relocation. We must correctly predict which of
1783 the two semantics (local or global) the assembler and linker
1784 will apply. The choice depends on the symbol's binding rather
1785 than its visibility.
1787 In the second case, the assembler will not use R_MIPS_GOT16
1788 relocations, but it chooses between local and global accesses
1789 in the same way as for o32 PIC.
1791 In the third case we have more freedom since both forms of
1792 access will work for any kind of symbol. However, there seems
1793 little point in doing things differently. */
1794 if (mips_global_symbol_p (x))
1795 return SYMBOL_GOT_DISP;
1797 return SYMBOL_GOT_PAGE_OFST;
1800 return SYMBOL_ABSOLUTE;
1803 /* Classify the base of symbolic expression X, given that X appears in
1806 static enum mips_symbol_type
1807 mips_classify_symbolic_expression (rtx x, enum mips_symbol_context context)
1811 split_const (x, &x, &offset);
1812 if (UNSPEC_ADDRESS_P (x))
1813 return UNSPEC_ADDRESS_TYPE (x);
1815 return mips_classify_symbol (x, context);
1818 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1819 is the alignment in bytes of SYMBOL_REF X. */
1822 mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset)
1824 HOST_WIDE_INT align;
1826 align = SYMBOL_REF_DECL (x) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x)) : 1;
1827 return IN_RANGE (offset, 0, align - 1);
1830 /* Return true if X is a symbolic constant that can be used in context
1831 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1834 mips_symbolic_constant_p (rtx x, enum mips_symbol_context context,
1835 enum mips_symbol_type *symbol_type)
1839 split_const (x, &x, &offset);
1840 if (UNSPEC_ADDRESS_P (x))
1842 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1843 x = UNSPEC_ADDRESS (x);
1845 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1847 *symbol_type = mips_classify_symbol (x, context);
1848 if (*symbol_type == SYMBOL_TLS)
1854 if (offset == const0_rtx)
1857 /* Check whether a nonzero offset is valid for the underlying
1859 switch (*symbol_type)
1861 case SYMBOL_ABSOLUTE:
1862 case SYMBOL_64_HIGH:
1865 /* If the target has 64-bit pointers and the object file only
1866 supports 32-bit symbols, the values of those symbols will be
1867 sign-extended. In this case we can't allow an arbitrary offset
1868 in case the 32-bit value X + OFFSET has a different sign from X. */
1869 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1870 return offset_within_block_p (x, INTVAL (offset));
1872 /* In other cases the relocations can handle any offset. */
1875 case SYMBOL_PC_RELATIVE:
1876 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1877 In this case, we no longer have access to the underlying constant,
1878 but the original symbol-based access was known to be valid. */
1879 if (GET_CODE (x) == LABEL_REF)
1884 case SYMBOL_GP_RELATIVE:
1885 /* Make sure that the offset refers to something within the
1886 same object block. This should guarantee that the final
1887 PC- or GP-relative offset is within the 16-bit limit. */
1888 return offset_within_block_p (x, INTVAL (offset));
1890 case SYMBOL_GOT_PAGE_OFST:
1891 case SYMBOL_GOTOFF_PAGE:
1892 /* If the symbol is global, the GOT entry will contain the symbol's
1893 address, and we will apply a 16-bit offset after loading it.
1894 If the symbol is local, the linker should provide enough local
1895 GOT entries for a 16-bit offset, but larger offsets may lead
1897 return SMALL_INT (offset);
1901 /* There is no carry between the HI and LO REL relocations, so the
1902 offset is only valid if we know it won't lead to such a carry. */
1903 return mips_offset_within_alignment_p (x, INTVAL (offset));
1905 case SYMBOL_GOT_DISP:
1906 case SYMBOL_GOTOFF_DISP:
1907 case SYMBOL_GOTOFF_CALL:
1908 case SYMBOL_GOTOFF_LOADGP:
1911 case SYMBOL_GOTTPREL:
1919 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
1920 single instruction. We rely on the fact that, in the worst case,
1921 all instructions involved in a MIPS16 address calculation are usually
1925 mips_symbol_insns_1 (enum mips_symbol_type type, enum machine_mode mode)
1927 if (mips_use_pcrel_pool_p[(int) type])
1929 if (mode == MAX_MACHINE_MODE)
1930 /* LEAs will be converted into constant-pool references by
1932 type = SYMBOL_PC_RELATIVE;
1934 /* The constant must be loaded and then dereferenced. */
1940 case SYMBOL_ABSOLUTE:
1941 /* When using 64-bit symbols, we need 5 preparatory instructions,
1944 lui $at,%highest(symbol)
1945 daddiu $at,$at,%higher(symbol)
1947 daddiu $at,$at,%hi(symbol)
1950 The final address is then $at + %lo(symbol). With 32-bit
1951 symbols we just need a preparatory LUI for normal mode and
1952 a preparatory LI and SLL for MIPS16. */
1953 return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2;
1955 case SYMBOL_GP_RELATIVE:
1956 /* Treat GP-relative accesses as taking a single instruction on
1957 MIPS16 too; the copy of $gp can often be shared. */
1960 case SYMBOL_PC_RELATIVE:
1961 /* PC-relative constants can be only be used with ADDIUPC,
1962 DADDIUPC, LWPC and LDPC. */
1963 if (mode == MAX_MACHINE_MODE
1964 || GET_MODE_SIZE (mode) == 4
1965 || GET_MODE_SIZE (mode) == 8)
1968 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
1971 case SYMBOL_GOT_DISP:
1972 /* The constant will have to be loaded from the GOT before it
1973 is used in an address. */
1974 if (mode != MAX_MACHINE_MODE)
1979 case SYMBOL_GOT_PAGE_OFST:
1980 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
1981 local/global classification is accurate. The worst cases are:
1983 (1) For local symbols when generating o32 or o64 code. The assembler
1989 ...and the final address will be $at + %lo(symbol).
1991 (2) For global symbols when -mxgot. The assembler will use:
1993 lui $at,%got_hi(symbol)
1996 ...and the final address will be $at + %got_lo(symbol). */
1999 case SYMBOL_GOTOFF_PAGE:
2000 case SYMBOL_GOTOFF_DISP:
2001 case SYMBOL_GOTOFF_CALL:
2002 case SYMBOL_GOTOFF_LOADGP:
2003 case SYMBOL_64_HIGH:
2009 case SYMBOL_GOTTPREL:
2012 /* A 16-bit constant formed by a single relocation, or a 32-bit
2013 constant formed from a high 16-bit relocation and a low 16-bit
2014 relocation. Use mips_split_p to determine which. 32-bit
2015 constants need an "lui; addiu" sequence for normal mode and
2016 an "li; sll; addiu" sequence for MIPS16 mode. */
2017 return !mips_split_p[type] ? 1 : TARGET_MIPS16 ? 3 : 2;
2020 /* We don't treat a bare TLS symbol as a constant. */
2026 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
2027 to load symbols of type TYPE into a register. Return 0 if the given
2028 type of symbol cannot be used as an immediate operand.
2030 Otherwise, return the number of instructions needed to load or store
2031 values of mode MODE to or from addresses of type TYPE. Return 0 if
2032 the given type of symbol is not valid in addresses.
2034 In both cases, instruction counts are based off BASE_INSN_LENGTH. */
2037 mips_symbol_insns (enum mips_symbol_type type, enum machine_mode mode)
2039 return mips_symbol_insns_1 (type, mode) * (TARGET_MIPS16 ? 2 : 1);
2042 /* A for_each_rtx callback. Stop the search if *X references a
2043 thread-local symbol. */
2046 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
2048 return mips_tls_symbol_p (*x);
2051 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
2054 mips_cannot_force_const_mem (enum machine_mode mode, rtx x)
2056 enum mips_symbol_type type;
2059 /* There is no assembler syntax for expressing an address-sized
2061 if (GET_CODE (x) == HIGH)
2064 /* As an optimization, reject constants that mips_legitimize_move
2067 Suppose we have a multi-instruction sequence that loads constant C
2068 into register R. If R does not get allocated a hard register, and
2069 R is used in an operand that allows both registers and memory
2070 references, reload will consider forcing C into memory and using
2071 one of the instruction's memory alternatives. Returning false
2072 here will force it to use an input reload instead. */
2073 if (CONST_INT_P (x) && mips_legitimate_constant_p (mode, x))
2076 split_const (x, &base, &offset);
2077 if (mips_symbolic_constant_p (base, SYMBOL_CONTEXT_LEA, &type))
2079 /* See whether we explicitly want these symbols in the pool. */
2080 if (mips_use_pcrel_pool_p[(int) type])
2083 /* The same optimization as for CONST_INT. */
2084 if (SMALL_INT (offset) && mips_symbol_insns (type, MAX_MACHINE_MODE) > 0)
2087 /* If MIPS16 constant pools live in the text section, they should
2088 not refer to anything that might need run-time relocation. */
2089 if (TARGET_MIPS16_PCREL_LOADS && mips_got_symbol_type_p (type))
2093 /* TLS symbols must be computed by mips_legitimize_move. */
2094 if (for_each_rtx (&x, &mips_tls_symbol_ref_1, NULL))
2100 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
2101 constants when we're using a per-function constant pool. */
2104 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
2105 const_rtx x ATTRIBUTE_UNUSED)
2107 return !TARGET_MIPS16_PCREL_LOADS;
2110 /* Return true if register REGNO is a valid base register for mode MODE.
2111 STRICT_P is true if REG_OK_STRICT is in effect. */
2114 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode,
2117 if (!HARD_REGISTER_NUM_P (regno))
2121 regno = reg_renumber[regno];
2124 /* These fake registers will be eliminated to either the stack or
2125 hard frame pointer, both of which are usually valid base registers.
2126 Reload deals with the cases where the eliminated form isn't valid. */
2127 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
2130 /* In MIPS16 mode, the stack pointer can only address word and doubleword
2131 values, nothing smaller. There are two problems here:
2133 (a) Instantiating virtual registers can introduce new uses of the
2134 stack pointer. If these virtual registers are valid addresses,
2135 the stack pointer should be too.
2137 (b) Most uses of the stack pointer are not made explicit until
2138 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
2139 We don't know until that stage whether we'll be eliminating to the
2140 stack pointer (which needs the restriction) or the hard frame
2141 pointer (which doesn't).
2143 All in all, it seems more consistent to only enforce this restriction
2144 during and after reload. */
2145 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
2146 return !strict_p || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
2148 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
2151 /* Return true if X is a valid base register for mode MODE.
2152 STRICT_P is true if REG_OK_STRICT is in effect. */
2155 mips_valid_base_register_p (rtx x, enum machine_mode mode, bool strict_p)
2157 if (!strict_p && GET_CODE (x) == SUBREG)
2161 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p));
2164 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2165 can address a value of mode MODE. */
2168 mips_valid_offset_p (rtx x, enum machine_mode mode)
2170 /* Check that X is a signed 16-bit number. */
2171 if (!const_arith_operand (x, Pmode))
2174 /* We may need to split multiword moves, so make sure that every word
2176 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2177 && !SMALL_OPERAND (INTVAL (x) + GET_MODE_SIZE (mode) - UNITS_PER_WORD))
2183 /* Return true if a LO_SUM can address a value of mode MODE when the
2184 LO_SUM symbol has type SYMBOL_TYPE. */
2187 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type, enum machine_mode mode)
2189 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2191 if (mips_symbol_insns (symbol_type, mode) == 0)
2194 /* Check that there is a known low-part relocation. */
2195 if (mips_lo_relocs[symbol_type] == NULL)
2198 /* We may need to split multiword moves, so make sure that each word
2199 can be accessed without inducing a carry. This is mainly needed
2200 for o64, which has historically only guaranteed 64-bit alignment
2201 for 128-bit types. */
2202 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2203 && GET_MODE_BITSIZE (mode) > GET_MODE_ALIGNMENT (mode))
2209 /* Return true if X is a valid address for machine mode MODE. If it is,
2210 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2214 mips_classify_address (struct mips_address_info *info, rtx x,
2215 enum machine_mode mode, bool strict_p)
2217 switch (GET_CODE (x))
2221 info->type = ADDRESS_REG;
2223 info->offset = const0_rtx;
2224 return mips_valid_base_register_p (info->reg, mode, strict_p);
2227 info->type = ADDRESS_REG;
2228 info->reg = XEXP (x, 0);
2229 info->offset = XEXP (x, 1);
2230 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2231 && mips_valid_offset_p (info->offset, mode));
2234 info->type = ADDRESS_LO_SUM;
2235 info->reg = XEXP (x, 0);
2236 info->offset = XEXP (x, 1);
2237 /* We have to trust the creator of the LO_SUM to do something vaguely
2238 sane. Target-independent code that creates a LO_SUM should also
2239 create and verify the matching HIGH. Target-independent code that
2240 adds an offset to a LO_SUM must prove that the offset will not
2241 induce a carry. Failure to do either of these things would be
2242 a bug, and we are not required to check for it here. The MIPS
2243 backend itself should only create LO_SUMs for valid symbolic
2244 constants, with the high part being either a HIGH or a copy
2247 = mips_classify_symbolic_expression (info->offset, SYMBOL_CONTEXT_MEM);
2248 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2249 && mips_valid_lo_sum_p (info->symbol_type, mode));
2252 /* Small-integer addresses don't occur very often, but they
2253 are legitimate if $0 is a valid base register. */
2254 info->type = ADDRESS_CONST_INT;
2255 return !TARGET_MIPS16 && SMALL_INT (x);
2260 info->type = ADDRESS_SYMBOLIC;
2261 return (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_MEM,
2263 && mips_symbol_insns (info->symbol_type, mode) > 0
2264 && !mips_split_p[info->symbol_type]);
2271 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2274 mips_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
2276 struct mips_address_info addr;
2278 return mips_classify_address (&addr, x, mode, strict_p);
2281 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
2284 mips_stack_address_p (rtx x, enum machine_mode mode)
2286 struct mips_address_info addr;
2288 return (mips_classify_address (&addr, x, mode, false)
2289 && addr.type == ADDRESS_REG
2290 && addr.reg == stack_pointer_rtx);
2293 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2294 address instruction. Note that such addresses are not considered
2295 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2296 is so restricted. */
2299 mips_lwxs_address_p (rtx addr)
2302 && GET_CODE (addr) == PLUS
2303 && REG_P (XEXP (addr, 1)))
2305 rtx offset = XEXP (addr, 0);
2306 if (GET_CODE (offset) == MULT
2307 && REG_P (XEXP (offset, 0))
2308 && CONST_INT_P (XEXP (offset, 1))
2309 && INTVAL (XEXP (offset, 1)) == 4)
2315 /* Return true if ADDR matches the pattern for the L{B,H,W,D}{,U}X load
2316 indexed address instruction. Note that such addresses are
2317 not considered legitimate in the TARGET_LEGITIMATE_ADDRESS_P
2318 sense, because their use is so restricted. */
2321 mips_lx_address_p (rtx addr, enum machine_mode mode)
2323 if (GET_CODE (addr) != PLUS
2324 || !REG_P (XEXP (addr, 0))
2325 || !REG_P (XEXP (addr, 1)))
2327 if (ISA_HAS_LBX && mode == QImode)
2329 if (ISA_HAS_LHX && mode == HImode)
2331 if (ISA_HAS_LWX && mode == SImode)
2333 if (ISA_HAS_LDX && mode == DImode)
2338 /* Return true if a value at OFFSET bytes from base register BASE can be
2339 accessed using an unextended MIPS16 instruction. MODE is the mode of
2342 Usually the offset in an unextended instruction is a 5-bit field.
2343 The offset is unsigned and shifted left once for LH and SH, twice
2344 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2345 an 8-bit immediate field that's shifted left twice. */
2348 mips16_unextended_reference_p (enum machine_mode mode, rtx base,
2349 unsigned HOST_WIDE_INT offset)
2351 if (mode != BLKmode && offset % GET_MODE_SIZE (mode) == 0)
2353 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
2354 return offset < 256U * GET_MODE_SIZE (mode);
2355 return offset < 32U * GET_MODE_SIZE (mode);
2360 /* Return the number of instructions needed to load or store a value
2361 of mode MODE at address X, assuming that BASE_INSN_LENGTH is the
2362 length of one instruction. Return 0 if X isn't valid for MODE.
2363 Assume that multiword moves may need to be split into word moves
2364 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2368 mips_address_insns (rtx x, enum machine_mode mode, bool might_split_p)
2370 struct mips_address_info addr;
2373 /* BLKmode is used for single unaligned loads and stores and should
2374 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2375 meaningless, so we have to single it out as a special case one way
2377 if (mode != BLKmode && might_split_p)
2378 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2382 if (mips_classify_address (&addr, x, mode, false))
2387 && !mips16_unextended_reference_p (mode, addr.reg,
2388 UINTVAL (addr.offset)))
2392 case ADDRESS_LO_SUM:
2393 return TARGET_MIPS16 ? factor * 2 : factor;
2395 case ADDRESS_CONST_INT:
2398 case ADDRESS_SYMBOLIC:
2399 return factor * mips_symbol_insns (addr.symbol_type, mode);
2404 /* Return true if X fits within an unsigned field of BITS bits that is
2405 shifted left SHIFT bits before being used. */
2408 mips_unsigned_immediate_p (unsigned HOST_WIDE_INT x, int bits, int shift = 0)
2410 return (x & ((1 << shift) - 1)) == 0 && x < ((unsigned) 1 << (shift + bits));
2413 /* Return true if X fits within a signed field of BITS bits that is
2414 shifted left SHIFT bits before being used. */
2417 mips_signed_immediate_p (unsigned HOST_WIDE_INT x, int bits, int shift = 0)
2419 x += 1 << (bits + shift - 1);
2420 return mips_unsigned_immediate_p (x, bits, shift);
2423 /* Return true if X is legitimate for accessing values of mode MODE,
2424 if it is based on a MIPS16 register, and if the offset satisfies
2425 OFFSET_PREDICATE. */
2428 m16_based_address_p (rtx x, enum machine_mode mode,
2429 insn_operand_predicate_fn offset_predicate)
2431 struct mips_address_info addr;
2433 return (mips_classify_address (&addr, x, mode, false)
2434 && addr.type == ADDRESS_REG
2435 && M16_REG_P (REGNO (addr.reg))
2436 && offset_predicate (addr.offset, mode));
2439 /* Return true if X is a legitimate address that conforms to the requirements
2440 for a microMIPS LWSP or SWSP insn. */
2443 lwsp_swsp_address_p (rtx x, enum machine_mode mode)
2445 struct mips_address_info addr;
2447 return (mips_classify_address (&addr, x, mode, false)
2448 && addr.type == ADDRESS_REG
2449 && REGNO (addr.reg) == STACK_POINTER_REGNUM
2450 && uw5_operand (addr.offset, mode));
2453 /* Return true if X is a legitimate address with a 12-bit offset.
2454 MODE is the mode of the value being accessed. */
2457 umips_12bit_offset_address_p (rtx x, enum machine_mode mode)
2459 struct mips_address_info addr;
2461 return (mips_classify_address (&addr, x, mode, false)
2462 && addr.type == ADDRESS_REG
2463 && CONST_INT_P (addr.offset)
2464 && UMIPS_12BIT_OFFSET_P (INTVAL (addr.offset)));
2467 /* Return the number of instructions needed to load constant X,
2468 assuming that BASE_INSN_LENGTH is the length of one instruction.
2469 Return 0 if X isn't a valid constant. */
2472 mips_const_insns (rtx x)
2474 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2475 enum mips_symbol_type symbol_type;
2478 switch (GET_CODE (x))
2481 if (!mips_symbolic_constant_p (XEXP (x, 0), SYMBOL_CONTEXT_LEA,
2483 || !mips_split_p[symbol_type])
2486 /* This is simply an LUI for normal mode. It is an extended
2487 LI followed by an extended SLL for MIPS16. */
2488 return TARGET_MIPS16 ? 4 : 1;
2492 /* Unsigned 8-bit constants can be loaded using an unextended
2493 LI instruction. Unsigned 16-bit constants can be loaded
2494 using an extended LI. Negative constants must be loaded
2495 using LI and then negated. */
2496 return (IN_RANGE (INTVAL (x), 0, 255) ? 1
2497 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
2498 : IN_RANGE (-INTVAL (x), 0, 255) ? 2
2499 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
2502 return mips_build_integer (codes, INTVAL (x));
2506 /* Allow zeros for normal mode, where we can use $0. */
2507 return !TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0;
2513 /* See if we can refer to X directly. */
2514 if (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_LEA, &symbol_type))
2515 return mips_symbol_insns (symbol_type, MAX_MACHINE_MODE);
2517 /* Otherwise try splitting the constant into a base and offset.
2518 If the offset is a 16-bit value, we can load the base address
2519 into a register and then use (D)ADDIU to add in the offset.
2520 If the offset is larger, we can load the base and offset
2521 into separate registers and add them together with (D)ADDU.
2522 However, the latter is only possible before reload; during
2523 and after reload, we must have the option of forcing the
2524 constant into the pool instead. */
2525 split_const (x, &x, &offset);
2528 int n = mips_const_insns (x);
2531 if (SMALL_INT (offset))
2533 else if (!targetm.cannot_force_const_mem (GET_MODE (x), x))
2534 return n + 1 + mips_build_integer (codes, INTVAL (offset));
2541 return mips_symbol_insns (mips_classify_symbol (x, SYMBOL_CONTEXT_LEA),
2549 /* X is a doubleword constant that can be handled by splitting it into
2550 two words and loading each word separately. Return the number of
2551 instructions required to do this, assuming that BASE_INSN_LENGTH
2552 is the length of one instruction. */
2555 mips_split_const_insns (rtx x)
2557 unsigned int low, high;
2559 low = mips_const_insns (mips_subword (x, false));
2560 high = mips_const_insns (mips_subword (x, true));
2561 gcc_assert (low > 0 && high > 0);
2565 /* Return the number of instructions needed to implement INSN,
2566 given that it loads from or stores to MEM. Assume that
2567 BASE_INSN_LENGTH is the length of one instruction. */
2570 mips_load_store_insns (rtx mem, rtx insn)
2572 enum machine_mode mode;
2576 gcc_assert (MEM_P (mem));
2577 mode = GET_MODE (mem);
2579 /* Try to prove that INSN does not need to be split. */
2580 might_split_p = GET_MODE_SIZE (mode) > UNITS_PER_WORD;
2583 set = single_set (insn);
2584 if (set && !mips_split_move_insn_p (SET_DEST (set), SET_SRC (set), insn))
2585 might_split_p = false;
2588 return mips_address_insns (XEXP (mem, 0), mode, might_split_p);
2591 /* Return the number of instructions needed for an integer division,
2592 assuming that BASE_INSN_LENGTH is the length of one instruction. */
2595 mips_idiv_insns (void)
2600 if (TARGET_CHECK_ZERO_DIV)
2602 if (GENERATE_DIVIDE_TRAPS)
2608 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
2613 /* Emit a move from SRC to DEST. Assume that the move expanders can
2614 handle all moves if !can_create_pseudo_p (). The distinction is
2615 important because, unlike emit_move_insn, the move expanders know
2616 how to force Pmode objects into the constant pool even when the
2617 constant pool address is not itself legitimate. */
2620 mips_emit_move (rtx dest, rtx src)
2622 return (can_create_pseudo_p ()
2623 ? emit_move_insn (dest, src)
2624 : emit_move_insn_1 (dest, src));
2627 /* Emit a move from SRC to DEST, splitting compound moves into individual
2628 instructions. SPLIT_TYPE is the type of split to perform. */
2631 mips_emit_move_or_split (rtx dest, rtx src, enum mips_split_type split_type)
2633 if (mips_split_move_p (dest, src, split_type))
2634 mips_split_move (dest, src, split_type);
2636 mips_emit_move (dest, src);
2639 /* Emit an instruction of the form (set TARGET (CODE OP0)). */
2642 mips_emit_unary (enum rtx_code code, rtx target, rtx op0)
2644 emit_insn (gen_rtx_SET (VOIDmode, target,
2645 gen_rtx_fmt_e (code, GET_MODE (op0), op0)));
2648 /* Compute (CODE OP0) and store the result in a new register of mode MODE.
2649 Return that new register. */
2652 mips_force_unary (enum machine_mode mode, enum rtx_code code, rtx op0)
2656 reg = gen_reg_rtx (mode);
2657 mips_emit_unary (code, reg, op0);
2661 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2664 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
2666 emit_insn (gen_rtx_SET (VOIDmode, target,
2667 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
2670 /* Compute (CODE OP0 OP1) and store the result in a new register
2671 of mode MODE. Return that new register. */
2674 mips_force_binary (enum machine_mode mode, enum rtx_code code, rtx op0, rtx op1)
2678 reg = gen_reg_rtx (mode);
2679 mips_emit_binary (code, reg, op0, op1);
2683 /* Copy VALUE to a register and return that register. If new pseudos
2684 are allowed, copy it into a new register, otherwise use DEST. */
2687 mips_force_temporary (rtx dest, rtx value)
2689 if (can_create_pseudo_p ())
2690 return force_reg (Pmode, value);
2693 mips_emit_move (dest, value);
2698 /* Emit a call sequence with call pattern PATTERN and return the call
2699 instruction itself (which is not necessarily the last instruction
2700 emitted). ORIG_ADDR is the original, unlegitimized address,
2701 ADDR is the legitimized form, and LAZY_P is true if the call
2702 address is lazily-bound. */
2705 mips_emit_call_insn (rtx pattern, rtx orig_addr, rtx addr, bool lazy_p)
2709 insn = emit_call_insn (pattern);
2711 if (TARGET_MIPS16 && mips_use_pic_fn_addr_reg_p (orig_addr))
2713 /* MIPS16 JALRs only take MIPS16 registers. If the target
2714 function requires $25 to be valid on entry, we must copy it
2715 there separately. The move instruction can be put in the
2716 call's delay slot. */
2717 reg = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
2718 emit_insn_before (gen_move_insn (reg, addr), insn);
2719 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
2723 /* Lazy-binding stubs require $gp to be valid on entry. */
2724 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
2728 /* See the comment above load_call<mode> for details. */
2729 use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
2730 gen_rtx_REG (Pmode, GOT_VERSION_REGNUM));
2731 emit_insn (gen_update_got_version ());
2736 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2737 then add CONST_INT OFFSET to the result. */
2740 mips_unspec_address_offset (rtx base, rtx offset,
2741 enum mips_symbol_type symbol_type)
2743 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
2744 UNSPEC_ADDRESS_FIRST + symbol_type);
2745 if (offset != const0_rtx)
2746 base = gen_rtx_PLUS (Pmode, base, offset);
2747 return gen_rtx_CONST (Pmode, base);
2750 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2751 type SYMBOL_TYPE. */
2754 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
2758 split_const (address, &base, &offset);
2759 return mips_unspec_address_offset (base, offset, symbol_type);
2762 /* If OP is an UNSPEC address, return the address to which it refers,
2763 otherwise return OP itself. */
2766 mips_strip_unspec_address (rtx op)
2770 split_const (op, &base, &offset);
2771 if (UNSPEC_ADDRESS_P (base))
2772 op = plus_constant (Pmode, UNSPEC_ADDRESS (base), INTVAL (offset));
2776 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2777 high part to BASE and return the result. Just return BASE otherwise.
2778 TEMP is as for mips_force_temporary.
2780 The returned expression can be used as the first operand to a LO_SUM. */
2783 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
2784 enum mips_symbol_type symbol_type)
2786 if (mips_split_p[symbol_type])
2788 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
2789 addr = mips_force_temporary (temp, addr);
2790 base = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
2795 /* Return an instruction that copies $gp into register REG. We want
2796 GCC to treat the register's value as constant, so that its value
2797 can be rematerialized on demand. */
2800 gen_load_const_gp (rtx reg)
2802 return PMODE_INSN (gen_load_const_gp, (reg));
2805 /* Return a pseudo register that contains the value of $gp throughout
2806 the current function. Such registers are needed by MIPS16 functions,
2807 for which $gp itself is not a valid base register or addition operand. */
2810 mips16_gp_pseudo_reg (void)
2812 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
2816 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
2818 push_topmost_sequence ();
2820 scan = get_insns ();
2821 while (NEXT_INSN (scan) && !INSN_P (NEXT_INSN (scan)))
2822 scan = NEXT_INSN (scan);
2824 insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
2825 insn = emit_insn_after (insn, scan);
2826 INSN_LOCATION (insn) = 0;
2828 pop_topmost_sequence ();
2831 return cfun->machine->mips16_gp_pseudo_rtx;
2834 /* Return a base register that holds pic_offset_table_rtx.
2835 TEMP, if nonnull, is a scratch Pmode base register. */
2838 mips_pic_base_register (rtx temp)
2841 return pic_offset_table_rtx;
2843 if (currently_expanding_to_rtl)
2844 return mips16_gp_pseudo_reg ();
2846 if (can_create_pseudo_p ())
2847 temp = gen_reg_rtx (Pmode);
2850 /* The first post-reload split exposes all references to $gp
2851 (both uses and definitions). All references must remain
2852 explicit after that point.
2854 It is safe to introduce uses of $gp at any time, so for
2855 simplicity, we do that before the split too. */
2856 mips_emit_move (temp, pic_offset_table_rtx);
2858 emit_insn (gen_load_const_gp (temp));
2862 /* Return the RHS of a load_call<mode> insn. */
2865 mips_unspec_call (rtx reg, rtx symbol)
2869 vec = gen_rtvec (3, reg, symbol, gen_rtx_REG (SImode, GOT_VERSION_REGNUM));
2870 return gen_rtx_UNSPEC (Pmode, vec, UNSPEC_LOAD_CALL);
2873 /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol
2874 reference. Return NULL_RTX otherwise. */
2877 mips_strip_unspec_call (rtx src)
2879 if (GET_CODE (src) == UNSPEC && XINT (src, 1) == UNSPEC_LOAD_CALL)
2880 return mips_strip_unspec_address (XVECEXP (src, 0, 1));
2884 /* Create and return a GOT reference of type TYPE for address ADDR.
2885 TEMP, if nonnull, is a scratch Pmode base register. */
2888 mips_got_load (rtx temp, rtx addr, enum mips_symbol_type type)
2890 rtx base, high, lo_sum_symbol;
2892 base = mips_pic_base_register (temp);
2894 /* If we used the temporary register to load $gp, we can't use
2895 it for the high part as well. */
2896 if (temp != NULL && reg_overlap_mentioned_p (base, temp))
2899 high = mips_unspec_offset_high (temp, base, addr, type);
2900 lo_sum_symbol = mips_unspec_address (addr, type);
2902 if (type == SYMBOL_GOTOFF_CALL)
2903 return mips_unspec_call (high, lo_sum_symbol);
2905 return PMODE_INSN (gen_unspec_got, (high, lo_sum_symbol));
2908 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2909 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2910 constant in that context and can be split into high and low parts.
2911 If so, and if LOW_OUT is nonnull, emit the high part and store the
2912 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
2914 TEMP is as for mips_force_temporary and is used to load the high
2915 part into a register.
2917 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
2918 a legitimize SET_SRC for an .md pattern, otherwise the low part
2919 is guaranteed to be a legitimate address for mode MODE. */
2922 mips_split_symbol (rtx temp, rtx addr, enum machine_mode mode, rtx *low_out)
2924 enum mips_symbol_context context;
2925 enum mips_symbol_type symbol_type;
2928 context = (mode == MAX_MACHINE_MODE
2929 ? SYMBOL_CONTEXT_LEA
2930 : SYMBOL_CONTEXT_MEM);
2931 if (GET_CODE (addr) == HIGH && context == SYMBOL_CONTEXT_LEA)
2933 addr = XEXP (addr, 0);
2934 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2935 && mips_symbol_insns (symbol_type, mode) > 0
2936 && mips_split_hi_p[symbol_type])
2939 switch (symbol_type)
2941 case SYMBOL_GOT_PAGE_OFST:
2942 /* The high part of a page/ofst pair is loaded from the GOT. */
2943 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_PAGE);
2954 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2955 && mips_symbol_insns (symbol_type, mode) > 0
2956 && mips_split_p[symbol_type])
2959 switch (symbol_type)
2961 case SYMBOL_GOT_DISP:
2962 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
2963 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_DISP);
2966 case SYMBOL_GP_RELATIVE:
2967 high = mips_pic_base_register (temp);
2968 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2972 high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
2973 high = mips_force_temporary (temp, high);
2974 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2983 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2984 mips_force_temporary; it is only needed when OFFSET is not a
2988 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
2990 if (!SMALL_OPERAND (offset))
2996 /* Load the full offset into a register so that we can use
2997 an unextended instruction for the address itself. */
2998 high = GEN_INT (offset);
3003 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
3004 The addition inside the macro CONST_HIGH_PART may cause an
3005 overflow, so we need to force a sign-extension check. */
3006 high = gen_int_mode (CONST_HIGH_PART (offset), Pmode);
3007 offset = CONST_LOW_PART (offset);
3009 high = mips_force_temporary (temp, high);
3010 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
3012 return plus_constant (Pmode, reg, offset);
3015 /* The __tls_get_attr symbol. */
3016 static GTY(()) rtx mips_tls_symbol;
3018 /* Return an instruction sequence that calls __tls_get_addr. SYM is
3019 the TLS symbol we are referencing and TYPE is the symbol type to use
3020 (either global dynamic or local dynamic). V0 is an RTX for the
3021 return value location. */
3024 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
3028 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
3030 if (!mips_tls_symbol)
3031 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
3033 loc = mips_unspec_address (sym, type);
3037 emit_insn (gen_rtx_SET (Pmode, a0,
3038 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
3039 insn = mips_expand_call (MIPS_CALL_NORMAL, v0, mips_tls_symbol,
3040 const0_rtx, NULL_RTX, false);
3041 RTL_CONST_CALL_P (insn) = 1;
3042 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
3043 insn = get_insns ();
3050 /* Return a pseudo register that contains the current thread pointer. */
3053 mips_expand_thread_pointer (rtx tp)
3059 mips_need_mips16_rdhwr_p = true;
3060 fn = mips16_stub_function ("__mips16_rdhwr");
3061 SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_LOCAL;
3062 if (!call_insn_operand (fn, VOIDmode))
3063 fn = force_reg (Pmode, fn);
3064 emit_insn (PMODE_INSN (gen_tls_get_tp_mips16, (tp, fn)));
3067 emit_insn (PMODE_INSN (gen_tls_get_tp, (tp)));
3074 return mips_expand_thread_pointer (gen_reg_rtx (Pmode));
3077 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
3078 its address. The return value will be both a valid address and a valid
3079 SET_SRC (either a REG or a LO_SUM). */
3082 mips_legitimize_tls_address (rtx loc)
3084 rtx dest, insn, v0, tp, tmp1, tmp2, eqv, offset;
3085 enum tls_model model;
3087 model = SYMBOL_REF_TLS_MODEL (loc);
3088 /* Only TARGET_ABICALLS code can have more than one module; other
3089 code must be be static and should not use a GOT. All TLS models
3090 reduce to local exec in this situation. */
3091 if (!TARGET_ABICALLS)
3092 model = TLS_MODEL_LOCAL_EXEC;
3096 case TLS_MODEL_GLOBAL_DYNAMIC:
3097 v0 = gen_rtx_REG (Pmode, GP_RETURN);
3098 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
3099 dest = gen_reg_rtx (Pmode);
3100 emit_libcall_block (insn, dest, v0, loc);
3103 case TLS_MODEL_LOCAL_DYNAMIC:
3104 v0 = gen_rtx_REG (Pmode, GP_RETURN);
3105 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
3106 tmp1 = gen_reg_rtx (Pmode);
3108 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
3109 share the LDM result with other LD model accesses. */
3110 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3112 emit_libcall_block (insn, tmp1, v0, eqv);
3114 offset = mips_unspec_address (loc, SYMBOL_DTPREL);
3115 if (mips_split_p[SYMBOL_DTPREL])
3117 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
3118 dest = gen_rtx_LO_SUM (Pmode, tmp2, offset);
3121 dest = expand_binop (Pmode, add_optab, tmp1, offset,
3122 0, 0, OPTAB_DIRECT);
3125 case TLS_MODEL_INITIAL_EXEC:
3126 tp = mips_get_tp ();
3127 tmp1 = gen_reg_rtx (Pmode);
3128 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
3129 if (Pmode == DImode)
3130 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
3132 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
3133 dest = gen_reg_rtx (Pmode);
3134 emit_insn (gen_add3_insn (dest, tmp1, tp));
3137 case TLS_MODEL_LOCAL_EXEC:
3138 tmp1 = mips_get_tp ();
3139 offset = mips_unspec_address (loc, SYMBOL_TPREL);
3140 if (mips_split_p[SYMBOL_TPREL])
3142 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_TPREL);
3143 dest = gen_rtx_LO_SUM (Pmode, tmp2, offset);
3146 dest = expand_binop (Pmode, add_optab, tmp1, offset,
3147 0, 0, OPTAB_DIRECT);
3156 /* If X is not a valid address for mode MODE, force it into a register. */
3159 mips_force_address (rtx x, enum machine_mode mode)
3161 if (!mips_legitimate_address_p (mode, x, false))
3162 x = force_reg (Pmode, x);
3166 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
3167 be legitimized in a way that the generic machinery might not expect,
3168 return a new address, otherwise return NULL. MODE is the mode of
3169 the memory being accessed. */
3172 mips_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3173 enum machine_mode mode)
3176 HOST_WIDE_INT offset;
3178 if (mips_tls_symbol_p (x))
3179 return mips_legitimize_tls_address (x);
3181 /* See if the address can split into a high part and a LO_SUM. */
3182 if (mips_split_symbol (NULL, x, mode, &addr))
3183 return mips_force_address (addr, mode);
3185 /* Handle BASE + OFFSET using mips_add_offset. */
3186 mips_split_plus (x, &base, &offset);
3189 if (!mips_valid_base_register_p (base, mode, false))
3190 base = copy_to_mode_reg (Pmode, base);
3191 addr = mips_add_offset (NULL, base, offset);
3192 return mips_force_address (addr, mode);
3198 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
3201 mips_move_integer (rtx temp, rtx dest, unsigned HOST_WIDE_INT value)
3203 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
3204 enum machine_mode mode;
3205 unsigned int i, num_ops;
3208 mode = GET_MODE (dest);
3209 num_ops = mips_build_integer (codes, value);
3211 /* Apply each binary operation to X. Invariant: X is a legitimate
3212 source operand for a SET pattern. */
3213 x = GEN_INT (codes[0].value);
3214 for (i = 1; i < num_ops; i++)
3216 if (!can_create_pseudo_p ())
3218 emit_insn (gen_rtx_SET (VOIDmode, temp, x));
3222 x = force_reg (mode, x);
3223 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
3226 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
3229 /* Subroutine of mips_legitimize_move. Move constant SRC into register
3230 DEST given that SRC satisfies immediate_operand but doesn't satisfy
3234 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
3238 /* Split moves of big integers into smaller pieces. */
3239 if (splittable_const_int_operand (src, mode))
3241 mips_move_integer (dest, dest, INTVAL (src));
3245 /* Split moves of symbolic constants into high/low pairs. */
3246 if (mips_split_symbol (dest, src, MAX_MACHINE_MODE, &src))
3248 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
3252 /* Generate the appropriate access sequences for TLS symbols. */
3253 if (mips_tls_symbol_p (src))
3255 mips_emit_move (dest, mips_legitimize_tls_address (src));
3259 /* If we have (const (plus symbol offset)), and that expression cannot
3260 be forced into memory, load the symbol first and add in the offset.
3261 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
3262 forced into memory, as it usually produces better code. */
3263 split_const (src, &base, &offset);
3264 if (offset != const0_rtx
3265 && (targetm.cannot_force_const_mem (mode, src)
3266 || (!TARGET_MIPS16 && can_create_pseudo_p ())))
3268 base = mips_force_temporary (dest, base);
3269 mips_emit_move (dest, mips_add_offset (NULL, base, INTVAL (offset)));
3273 src = force_const_mem (mode, src);
3275 /* When using explicit relocs, constant pool references are sometimes
3276 not legitimate addresses. */
3277 mips_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0));
3278 mips_emit_move (dest, src);
3281 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
3282 sequence that is valid. */
3285 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
3287 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
3289 mips_emit_move (dest, force_reg (mode, src));
3293 /* We need to deal with constants that would be legitimate
3294 immediate_operands but aren't legitimate move_operands. */
3295 if (CONSTANT_P (src) && !move_operand (src, mode))
3297 mips_legitimize_const_move (mode, dest, src);
3298 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
3304 /* Return true if value X in context CONTEXT is a small-data address
3305 that can be rewritten as a LO_SUM. */
3308 mips_rewrite_small_data_p (rtx x, enum mips_symbol_context context)
3310 enum mips_symbol_type symbol_type;
3312 return (mips_lo_relocs[SYMBOL_GP_RELATIVE]
3313 && !mips_split_p[SYMBOL_GP_RELATIVE]
3314 && mips_symbolic_constant_p (x, context, &symbol_type)
3315 && symbol_type == SYMBOL_GP_RELATIVE);
3318 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
3319 containing MEM, or null if none. */
3322 mips_small_data_pattern_1 (rtx *loc, void *data)
3324 enum mips_symbol_context context;
3326 /* Ignore things like "g" constraints in asms. We make no particular
3327 guarantee about which symbolic constants are acceptable as asm operands
3328 versus which must be forced into a GPR. */
3329 if (GET_CODE (*loc) == LO_SUM || GET_CODE (*loc) == ASM_OPERANDS)
3334 if (for_each_rtx (&XEXP (*loc, 0), mips_small_data_pattern_1, *loc))
3339 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3340 return mips_rewrite_small_data_p (*loc, context);
3343 /* Return true if OP refers to small data symbols directly, not through
3347 mips_small_data_pattern_p (rtx op)
3349 return for_each_rtx (&op, mips_small_data_pattern_1, NULL);
3352 /* A for_each_rtx callback, used by mips_rewrite_small_data.
3353 DATA is the containing MEM, or null if none. */
3356 mips_rewrite_small_data_1 (rtx *loc, void *data)
3358 enum mips_symbol_context context;
3362 for_each_rtx (&XEXP (*loc, 0), mips_rewrite_small_data_1, *loc);
3366 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3367 if (mips_rewrite_small_data_p (*loc, context))
3368 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
3370 if (GET_CODE (*loc) == LO_SUM)
3376 /* Rewrite instruction pattern PATTERN so that it refers to small data
3377 using explicit relocations. */
3380 mips_rewrite_small_data (rtx pattern)
3382 pattern = copy_insn (pattern);
3383 for_each_rtx (&pattern, mips_rewrite_small_data_1, NULL);
3387 /* The cost of loading values from the constant pool. It should be
3388 larger than the cost of any constant we want to synthesize inline. */
3389 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3391 /* Return the cost of X when used as an operand to the MIPS16 instruction
3392 that implements CODE. Return -1 if there is no such instruction, or if
3393 X is not a valid immediate operand for it. */
3396 mips16_constant_cost (int code, HOST_WIDE_INT x)
3403 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3404 other shifts are extended. The shift patterns truncate the shift
3405 count to the right size, so there are no out-of-range values. */
3406 if (IN_RANGE (x, 1, 8))
3408 return COSTS_N_INSNS (1);
3411 if (IN_RANGE (x, -128, 127))
3413 if (SMALL_OPERAND (x))
3414 return COSTS_N_INSNS (1);
3418 /* Like LE, but reject the always-true case. */
3422 /* We add 1 to the immediate and use SLT. */
3425 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3428 if (IN_RANGE (x, 0, 255))
3430 if (SMALL_OPERAND_UNSIGNED (x))
3431 return COSTS_N_INSNS (1);
3436 /* Equality comparisons with 0 are cheap. */
3446 /* Return true if there is a non-MIPS16 instruction that implements CODE
3447 and if that instruction accepts X as an immediate operand. */
3450 mips_immediate_operand_p (int code, HOST_WIDE_INT x)
3457 /* All shift counts are truncated to a valid constant. */
3462 /* Likewise rotates, if the target supports rotates at all. */
3468 /* These instructions take 16-bit unsigned immediates. */
3469 return SMALL_OPERAND_UNSIGNED (x);
3474 /* These instructions take 16-bit signed immediates. */
3475 return SMALL_OPERAND (x);
3481 /* The "immediate" forms of these instructions are really
3482 implemented as comparisons with register 0. */
3487 /* Likewise, meaning that the only valid immediate operand is 1. */
3491 /* We add 1 to the immediate and use SLT. */
3492 return SMALL_OPERAND (x + 1);
3495 /* Likewise SLTU, but reject the always-true case. */
3496 return SMALL_OPERAND (x + 1) && x + 1 != 0;
3500 /* The bit position and size are immediate operands. */
3501 return ISA_HAS_EXT_INS;
3504 /* By default assume that $0 can be used for 0. */
3509 /* Return the cost of binary operation X, given that the instruction
3510 sequence for a word-sized or smaller operation has cost SINGLE_COST
3511 and that the sequence of a double-word operation has cost DOUBLE_COST.
3512 If SPEED is true, optimize for speed otherwise optimize for size. */
3515 mips_binary_cost (rtx x, int single_cost, int double_cost, bool speed)
3519 if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2)
3524 + set_src_cost (XEXP (x, 0), speed)
3525 + rtx_cost (XEXP (x, 1), GET_CODE (x), 1, speed));
3528 /* Return the cost of floating-point multiplications of mode MODE. */
3531 mips_fp_mult_cost (enum machine_mode mode)
3533 return mode == DFmode ? mips_cost->fp_mult_df : mips_cost->fp_mult_sf;
3536 /* Return the cost of floating-point divisions of mode MODE. */
3539 mips_fp_div_cost (enum machine_mode mode)
3541 return mode == DFmode ? mips_cost->fp_div_df : mips_cost->fp_div_sf;
3544 /* Return the cost of sign-extending OP to mode MODE, not including the
3545 cost of OP itself. */
3548 mips_sign_extend_cost (enum machine_mode mode, rtx op)
3551 /* Extended loads are as cheap as unextended ones. */
3554 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3555 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3558 if (ISA_HAS_SEB_SEH || GENERATE_MIPS16E)
3559 /* We can use SEB or SEH. */
3560 return COSTS_N_INSNS (1);
3562 /* We need to use a shift left and a shift right. */
3563 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3566 /* Return the cost of zero-extending OP to mode MODE, not including the
3567 cost of OP itself. */
3570 mips_zero_extend_cost (enum machine_mode mode, rtx op)
3573 /* Extended loads are as cheap as unextended ones. */
3576 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3577 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3578 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3580 if (GENERATE_MIPS16E)
3581 /* We can use ZEB or ZEH. */
3582 return COSTS_N_INSNS (1);
3585 /* We need to load 0xff or 0xffff into a register and use AND. */
3586 return COSTS_N_INSNS (GET_MODE (op) == QImode ? 2 : 3);
3588 /* We can use ANDI. */
3589 return COSTS_N_INSNS (1);
3592 /* Return the cost of moving between two registers of mode MODE,
3593 assuming that the move will be in pieces of at most UNITS bytes. */
3596 mips_set_reg_reg_piece_cost (enum machine_mode mode, unsigned int units)
3598 return COSTS_N_INSNS ((GET_MODE_SIZE (mode) + units - 1) / units);
3601 /* Return the cost of moving between two registers of mode MODE. */
3604 mips_set_reg_reg_cost (enum machine_mode mode)
3606 switch (GET_MODE_CLASS (mode))
3609 return mips_set_reg_reg_piece_cost (mode, GET_MODE_SIZE (CCmode));
3612 case MODE_COMPLEX_FLOAT:
3613 case MODE_VECTOR_FLOAT:
3614 if (TARGET_HARD_FLOAT)
3615 return mips_set_reg_reg_piece_cost (mode, UNITS_PER_HWFPVALUE);
3619 return mips_set_reg_reg_piece_cost (mode, UNITS_PER_WORD);
3623 /* Return the cost of an operand X that can be trucated for free.
3624 SPEED says whether we're optimizing for size or speed. */
3627 mips_truncated_op_cost (rtx x, bool speed)
3629 if (GET_CODE (x) == TRUNCATE)
3631 return set_src_cost (x, speed);
3634 /* Implement TARGET_RTX_COSTS. */
3637 mips_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
3638 int *total, bool speed)
3640 enum machine_mode mode = GET_MODE (x);
3641 bool float_mode_p = FLOAT_MODE_P (mode);
3645 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3646 appear in the instruction stream, and the cost of a comparison is
3647 really the cost of the branch or scc condition. At the time of
3648 writing, GCC only uses an explicit outer COMPARE code when optabs
3649 is testing whether a constant is expensive enough to force into a
3650 register. We want optabs to pass such constants through the MIPS
3651 expanders instead, so make all constants very cheap here. */
3652 if (outer_code == COMPARE)
3654 gcc_assert (CONSTANT_P (x));
3662 /* Treat *clear_upper32-style ANDs as having zero cost in the
3663 second operand. The cost is entirely in the first operand.
3665 ??? This is needed because we would otherwise try to CSE
3666 the constant operand. Although that's the right thing for
3667 instructions that continue to be a register operation throughout
3668 compilation, it is disastrous for instructions that could
3669 later be converted into a memory operation. */
3671 && outer_code == AND
3672 && UINTVAL (x) == 0xffffffff)
3680 cost = mips16_constant_cost (outer_code, INTVAL (x));
3689 /* When not optimizing for size, we care more about the cost
3690 of hot code, and hot code is often in a loop. If a constant
3691 operand needs to be forced into a register, we will often be
3692 able to hoist the constant load out of the loop, so the load
3693 should not contribute to the cost. */
3694 if (speed || mips_immediate_operand_p (outer_code, INTVAL (x)))
3706 if (force_to_mem_operand (x, VOIDmode))
3708 *total = COSTS_N_INSNS (1);
3711 cost = mips_const_insns (x);
3714 /* If the constant is likely to be stored in a GPR, SETs of
3715 single-insn constants are as cheap as register sets; we
3716 never want to CSE them.
3718 Don't reduce the cost of storing a floating-point zero in
3719 FPRs. If we have a zero in an FPR for other reasons, we
3720 can get better cfg-cleanup and delayed-branch results by
3721 using it consistently, rather than using $0 sometimes and
3722 an FPR at other times. Also, moves between floating-point
3723 registers are sometimes cheaper than (D)MTC1 $0. */
3725 && outer_code == SET
3726 && !(float_mode_p && TARGET_HARD_FLOAT))
3728 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3729 want to CSE the constant itself. It is usually better to
3730 have N copies of the last operation in the sequence and one
3731 shared copy of the other operations. (Note that this is
3732 not true for MIPS16 code, where the final operation in the
3733 sequence is often an extended instruction.)
3735 Also, if we have a CONST_INT, we don't know whether it is
3736 for a word or doubleword operation, so we cannot rely on
3737 the result of mips_build_integer. */
3738 else if (!TARGET_MIPS16
3739 && (outer_code == SET || mode == VOIDmode))
3741 *total = COSTS_N_INSNS (cost);
3744 /* The value will need to be fetched from the constant pool. */
3745 *total = CONSTANT_POOL_COST;
3749 /* If the address is legitimate, return the number of
3750 instructions it needs. */
3752 cost = mips_address_insns (addr, mode, true);
3755 *total = COSTS_N_INSNS (cost + 1);
3758 /* Check for a scaled indexed address. */
3759 if (mips_lwxs_address_p (addr)
3760 || mips_lx_address_p (addr, mode))
3762 *total = COSTS_N_INSNS (2);
3765 /* Otherwise use the default handling. */
3769 *total = COSTS_N_INSNS (6);
3773 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1);
3777 /* Check for a *clear_upper32 pattern and treat it like a zero
3778 extension. See the pattern's comment for details. */
3781 && CONST_INT_P (XEXP (x, 1))
3782 && UINTVAL (XEXP (x, 1)) == 0xffffffff)
3784 *total = (mips_zero_extend_cost (mode, XEXP (x, 0))
3785 + set_src_cost (XEXP (x, 0), speed));
3788 if (ISA_HAS_CINS && CONST_INT_P (XEXP (x, 1)))
3790 rtx op = XEXP (x, 0);
3791 if (GET_CODE (op) == ASHIFT
3792 && CONST_INT_P (XEXP (op, 1))
3793 && mask_low_and_shift_p (mode, XEXP (x, 1), XEXP (op, 1), 32))
3795 *total = COSTS_N_INSNS (1) + set_src_cost (XEXP (op, 0), speed);
3799 /* (AND (NOT op0) (NOT op1) is a nor operation that can be done in
3800 a single instruction. */
3802 && GET_CODE (XEXP (x, 0)) == NOT
3803 && GET_CODE (XEXP (x, 1)) == NOT)
3805 cost = GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1;
3806 *total = (COSTS_N_INSNS (cost)
3807 + set_src_cost (XEXP (XEXP (x, 0), 0), speed)
3808 + set_src_cost (XEXP (XEXP (x, 1), 0), speed));
3816 /* Double-word operations use two single-word operations. */
3817 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (2),
3826 if (CONSTANT_P (XEXP (x, 1)))
3827 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3830 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (12),
3836 *total = mips_cost->fp_add;
3838 *total = COSTS_N_INSNS (4);
3842 /* Low-part immediates need an extended MIPS16 instruction. */
3843 *total = (COSTS_N_INSNS (TARGET_MIPS16 ? 2 : 1)
3844 + set_src_cost (XEXP (x, 0), speed));
3859 /* Branch comparisons have VOIDmode, so use the first operand's
3861 mode = GET_MODE (XEXP (x, 0));
3862 if (FLOAT_MODE_P (mode))
3864 *total = mips_cost->fp_add;
3867 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3873 && (ISA_HAS_NMADD4_NMSUB4 || ISA_HAS_NMADD3_NMSUB3)
3874 && TARGET_FUSED_MADD
3875 && !HONOR_NANS (mode)
3876 && !HONOR_SIGNED_ZEROS (mode))
3878 /* See if we can use NMADD or NMSUB. See mips.md for the
3879 associated patterns. */
3880 rtx op0 = XEXP (x, 0);
3881 rtx op1 = XEXP (x, 1);
3882 if (GET_CODE (op0) == MULT && GET_CODE (XEXP (op0, 0)) == NEG)
3884 *total = (mips_fp_mult_cost (mode)
3885 + set_src_cost (XEXP (XEXP (op0, 0), 0), speed)
3886 + set_src_cost (XEXP (op0, 1), speed)
3887 + set_src_cost (op1, speed));
3890 if (GET_CODE (op1) == MULT)
3892 *total = (mips_fp_mult_cost (mode)
3893 + set_src_cost (op0, speed)
3894 + set_src_cost (XEXP (op1, 0), speed)
3895 + set_src_cost (XEXP (op1, 1), speed));
3904 /* If this is part of a MADD or MSUB, treat the PLUS as
3906 if ((ISA_HAS_FP_MADD4_MSUB4 || ISA_HAS_FP_MADD3_MSUB3)
3907 && TARGET_FUSED_MADD
3908 && GET_CODE (XEXP (x, 0)) == MULT)
3911 *total = mips_cost->fp_add;
3915 /* Double-word operations require three single-word operations and
3916 an SLTU. The MIPS16 version then needs to move the result of
3917 the SLTU from $24 to a MIPS16 register. */
3918 *total = mips_binary_cost (x, COSTS_N_INSNS (1),
3919 COSTS_N_INSNS (TARGET_MIPS16 ? 5 : 4),
3925 && (ISA_HAS_NMADD4_NMSUB4 || ISA_HAS_NMADD3_NMSUB3)
3926 && TARGET_FUSED_MADD
3927 && !HONOR_NANS (mode)
3928 && HONOR_SIGNED_ZEROS (mode))
3930 /* See if we can use NMADD or NMSUB. See mips.md for the
3931 associated patterns. */
3932 rtx op = XEXP (x, 0);
3933 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
3934 && GET_CODE (XEXP (op, 0)) == MULT)
3936 *total = (mips_fp_mult_cost (mode)
3937 + set_src_cost (XEXP (XEXP (op, 0), 0), speed)
3938 + set_src_cost (XEXP (XEXP (op, 0), 1), speed)
3939 + set_src_cost (XEXP (op, 1), speed));
3945 *total = mips_cost->fp_add;
3947 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1);
3952 *total = mips_fp_mult_cost (mode);
3953 else if (mode == DImode && !TARGET_64BIT)
3954 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
3955 where the mulsidi3 always includes an MFHI and an MFLO. */
3957 ? mips_cost->int_mult_si * 3 + 6
3958 : COSTS_N_INSNS (ISA_HAS_MUL3 ? 7 : 9));
3960 *total = COSTS_N_INSNS (ISA_HAS_MUL3 ? 1 : 2) + 1;
3961 else if (mode == DImode)
3962 *total = mips_cost->int_mult_di;
3964 *total = mips_cost->int_mult_si;
3968 /* Check for a reciprocal. */
3971 && flag_unsafe_math_optimizations
3972 && XEXP (x, 0) == CONST1_RTX (mode))
3974 if (outer_code == SQRT || GET_CODE (XEXP (x, 1)) == SQRT)
3975 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
3976 division as being free. */
3977 *total = set_src_cost (XEXP (x, 1), speed);
3979 *total = (mips_fp_div_cost (mode)
3980 + set_src_cost (XEXP (x, 1), speed));
3989 *total = mips_fp_div_cost (mode);
3998 /* It is our responsibility to make division by a power of 2
3999 as cheap as 2 register additions if we want the division
4000 expanders to be used for such operations; see the setting
4001 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
4002 should always produce shorter code than using
4003 expand_sdiv2_pow2. */
4005 && CONST_INT_P (XEXP (x, 1))
4006 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
4008 *total = COSTS_N_INSNS (2) + set_src_cost (XEXP (x, 0), speed);
4011 *total = COSTS_N_INSNS (mips_idiv_insns ());
4013 else if (mode == DImode)
4014 *total = mips_cost->int_div_di;
4016 *total = mips_cost->int_div_si;
4020 *total = mips_sign_extend_cost (mode, XEXP (x, 0));
4024 if (outer_code == SET
4026 && GET_MODE (XEXP (x, 0)) == QImode
4027 && GET_CODE (XEXP (x, 0)) == PLUS)
4029 rtx plus = XEXP (x, 0);
4030 *total = (COSTS_N_INSNS (1)
4031 + mips_truncated_op_cost (XEXP (plus, 0), speed)
4032 + mips_truncated_op_cost (XEXP (plus, 1), speed));
4035 *total = mips_zero_extend_cost (mode, XEXP (x, 0));
4039 case UNSIGNED_FLOAT:
4042 case FLOAT_TRUNCATE:
4043 *total = mips_cost->fp_add;
4047 if (register_operand (SET_DEST (x), VOIDmode)
4048 && reg_or_0_operand (SET_SRC (x), VOIDmode))
4050 *total = mips_set_reg_reg_cost (GET_MODE (SET_DEST (x)));
4060 /* Implement TARGET_ADDRESS_COST. */
4063 mips_address_cost (rtx addr, enum machine_mode mode,
4064 addr_space_t as ATTRIBUTE_UNUSED,
4065 bool speed ATTRIBUTE_UNUSED)
4067 return mips_address_insns (addr, mode, false);
4070 /* Information about a single instruction in a multi-instruction
4072 struct mips_multi_member {
4073 /* True if this is a label, false if it is code. */
4076 /* The output_asm_insn format of the instruction. */
4079 /* The operands to the instruction. */
4080 rtx operands[MAX_RECOG_OPERANDS];
4082 typedef struct mips_multi_member mips_multi_member;
4084 /* The instructions that make up the current multi-insn sequence. */
4085 static vec<mips_multi_member> mips_multi_members;
4087 /* How many instructions (as opposed to labels) are in the current
4088 multi-insn sequence. */
4089 static unsigned int mips_multi_num_insns;
4091 /* Start a new multi-insn sequence. */
4094 mips_multi_start (void)
4096 mips_multi_members.truncate (0);
4097 mips_multi_num_insns = 0;
4100 /* Add a new, uninitialized member to the current multi-insn sequence. */
4102 static struct mips_multi_member *
4103 mips_multi_add (void)
4105 mips_multi_member empty;
4106 return mips_multi_members.safe_push (empty);
4109 /* Add a normal insn with the given asm format to the current multi-insn
4110 sequence. The other arguments are a null-terminated list of operands. */
4113 mips_multi_add_insn (const char *format, ...)
4115 struct mips_multi_member *member;
4120 member = mips_multi_add ();
4121 member->is_label_p = false;
4122 member->format = format;
4123 va_start (ap, format);
4125 while ((op = va_arg (ap, rtx)))
4126 member->operands[i++] = op;
4128 mips_multi_num_insns++;
4131 /* Add the given label definition to the current multi-insn sequence.
4132 The definition should include the colon. */
4135 mips_multi_add_label (const char *label)
4137 struct mips_multi_member *member;
4139 member = mips_multi_add ();
4140 member->is_label_p = true;
4141 member->format = label;
4144 /* Return the index of the last member of the current multi-insn sequence. */
4147 mips_multi_last_index (void)
4149 return mips_multi_members.length () - 1;
4152 /* Add a copy of an existing instruction to the current multi-insn
4153 sequence. I is the index of the instruction that should be copied. */
4156 mips_multi_copy_insn (unsigned int i)
4158 struct mips_multi_member *member;
4160 member = mips_multi_add ();
4161 memcpy (member, &mips_multi_members[i], sizeof (*member));
4162 gcc_assert (!member->is_label_p);
4165 /* Change the operand of an existing instruction in the current
4166 multi-insn sequence. I is the index of the instruction,
4167 OP is the index of the operand, and X is the new value. */
4170 mips_multi_set_operand (unsigned int i, unsigned int op, rtx x)
4172 mips_multi_members[i].operands[op] = x;
4175 /* Write out the asm code for the current multi-insn sequence. */
4178 mips_multi_write (void)
4180 struct mips_multi_member *member;
4183 FOR_EACH_VEC_ELT (mips_multi_members, i, member)
4184 if (member->is_label_p)
4185 fprintf (asm_out_file, "%s\n", member->format);
4187 output_asm_insn (member->format, member->operands);
4190 /* Return one word of double-word value OP, taking into account the fixed
4191 endianness of certain registers. HIGH_P is true to select the high part,
4192 false to select the low part. */
4195 mips_subword (rtx op, bool high_p)
4197 unsigned int byte, offset;
4198 enum machine_mode mode;
4200 mode = GET_MODE (op);
4201 if (mode == VOIDmode)
4202 mode = TARGET_64BIT ? TImode : DImode;
4204 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
4205 byte = UNITS_PER_WORD;
4209 if (FP_REG_RTX_P (op))
4211 /* Paired FPRs are always ordered little-endian. */
4212 offset = (UNITS_PER_WORD < UNITS_PER_HWFPVALUE ? high_p : byte != 0);
4213 return gen_rtx_REG (word_mode, REGNO (op) + offset);
4217 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
4219 return simplify_gen_subreg (word_mode, op, mode, byte);
4222 /* Return true if SRC should be moved into DEST using "MULT $0, $0".
4223 SPLIT_TYPE is the condition under which moves should be split. */
4226 mips_mult_move_p (rtx dest, rtx src, enum mips_split_type split_type)
4228 return ((split_type != SPLIT_FOR_SPEED
4229 || mips_tuning_info.fast_mult_zero_zero_p)
4230 && src == const0_rtx
4232 && GET_MODE_SIZE (GET_MODE (dest)) == 2 * UNITS_PER_WORD
4233 && (ISA_HAS_DSP_MULT
4234 ? ACC_REG_P (REGNO (dest))
4235 : MD_REG_P (REGNO (dest))));
4238 /* Return true if a move from SRC to DEST should be split into two.
4239 SPLIT_TYPE describes the split condition. */
4242 mips_split_move_p (rtx dest, rtx src, enum mips_split_type split_type)
4244 /* Check whether the move can be done using some variant of MULT $0,$0. */
4245 if (mips_mult_move_p (dest, src, split_type))
4248 /* FPR-to-FPR moves can be done in a single instruction, if they're
4250 unsigned int size = GET_MODE_SIZE (GET_MODE (dest));
4251 if (size == 8 && FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
4254 /* Check for floating-point loads and stores. */
4255 if (size == 8 && ISA_HAS_LDC1_SDC1)
4257 if (FP_REG_RTX_P (dest) && MEM_P (src))
4259 if (FP_REG_RTX_P (src) && MEM_P (dest))
4263 /* Otherwise split all multiword moves. */
4264 return size > UNITS_PER_WORD;
4267 /* Split a move from SRC to DEST, given that mips_split_move_p holds.
4268 SPLIT_TYPE describes the split condition. */
4271 mips_split_move (rtx dest, rtx src, enum mips_split_type split_type)
4275 gcc_checking_assert (mips_split_move_p (dest, src, split_type));
4276 if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src))
4278 if (!TARGET_64BIT && GET_MODE (dest) == DImode)
4279 emit_insn (gen_move_doubleword_fprdi (dest, src));
4280 else if (!TARGET_64BIT && GET_MODE (dest) == DFmode)
4281 emit_insn (gen_move_doubleword_fprdf (dest, src));
4282 else if (!TARGET_64BIT && GET_MODE (dest) == V2SFmode)
4283 emit_insn (gen_move_doubleword_fprv2sf (dest, src));
4284 else if (!TARGET_64BIT && GET_MODE (dest) == V2SImode)
4285 emit_insn (gen_move_doubleword_fprv2si (dest, src));
4286 else if (!TARGET_64BIT && GET_MODE (dest) == V4HImode)
4287 emit_insn (gen_move_doubleword_fprv4hi (dest, src));
4288 else if (!TARGET_64BIT && GET_MODE (dest) == V8QImode)
4289 emit_insn (gen_move_doubleword_fprv8qi (dest, src));
4290 else if (TARGET_64BIT && GET_MODE (dest) == TFmode)
4291 emit_insn (gen_move_doubleword_fprtf (dest, src));
4295 else if (REG_P (dest) && REGNO (dest) == MD_REG_FIRST)
4297 low_dest = mips_subword (dest, false);
4298 mips_emit_move (low_dest, mips_subword (src, false));
4300 emit_insn (gen_mthidi_ti (dest, mips_subword (src, true), low_dest));
4302 emit_insn (gen_mthisi_di (dest, mips_subword (src, true), low_dest));
4304 else if (REG_P (src) && REGNO (src) == MD_REG_FIRST)
4306 mips_emit_move (mips_subword (dest, false), mips_subword (src, false));
4308 emit_insn (gen_mfhidi_ti (mips_subword (dest, true), src));
4310 emit_insn (gen_mfhisi_di (mips_subword (dest, true), src));
4314 /* The operation can be split into two normal moves. Decide in
4315 which order to do them. */
4316 low_dest = mips_subword (dest, false);
4317 if (REG_P (low_dest)
4318 && reg_overlap_mentioned_p (low_dest, src))
4320 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4321 mips_emit_move (low_dest, mips_subword (src, false));
4325 mips_emit_move (low_dest, mips_subword (src, false));
4326 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4331 /* Return the split type for instruction INSN. */
4333 static enum mips_split_type
4334 mips_insn_split_type (rtx insn)
4336 basic_block bb = BLOCK_FOR_INSN (insn);
4339 if (optimize_bb_for_speed_p (bb))
4340 return SPLIT_FOR_SPEED;
4342 return SPLIT_FOR_SIZE;
4344 /* Once CFG information has been removed, we should trust the optimization
4345 decisions made by previous passes and only split where necessary. */
4346 return SPLIT_IF_NECESSARY;
4349 /* Return true if a move from SRC to DEST in INSN should be split. */
4352 mips_split_move_insn_p (rtx dest, rtx src, rtx insn)
4354 return mips_split_move_p (dest, src, mips_insn_split_type (insn));
4357 /* Split a move from SRC to DEST in INSN, given that mips_split_move_insn_p
4361 mips_split_move_insn (rtx dest, rtx src, rtx insn)
4363 mips_split_move (dest, src, mips_insn_split_type (insn));
4366 /* Return the appropriate instructions to move SRC into DEST. Assume
4367 that SRC is operand 1 and DEST is operand 0. */
4370 mips_output_move (rtx dest, rtx src)
4372 enum rtx_code dest_code, src_code;
4373 enum machine_mode mode;
4374 enum mips_symbol_type symbol_type;
4377 dest_code = GET_CODE (dest);
4378 src_code = GET_CODE (src);
4379 mode = GET_MODE (dest);
4380 dbl_p = (GET_MODE_SIZE (mode) == 8);
4382 if (mips_split_move_p (dest, src, SPLIT_IF_NECESSARY))
4385 if ((src_code == REG && GP_REG_P (REGNO (src)))
4386 || (!TARGET_MIPS16 && src == CONST0_RTX (mode)))
4388 if (dest_code == REG)
4390 if (GP_REG_P (REGNO (dest)))
4391 return "move\t%0,%z1";
4393 if (mips_mult_move_p (dest, src, SPLIT_IF_NECESSARY))
4395 if (ISA_HAS_DSP_MULT)
4396 return "mult\t%q0,%.,%.";
4398 return "mult\t%.,%.";
4401 /* Moves to HI are handled by special .md insns. */
4402 if (REGNO (dest) == LO_REGNUM)
4405 if (DSP_ACC_REG_P (REGNO (dest)))
4407 static char retval[] = "mt__\t%z1,%q0";
4409 retval[2] = reg_names[REGNO (dest)][4];
4410 retval[3] = reg_names[REGNO (dest)][5];
4414 if (FP_REG_P (REGNO (dest)))
4415 return dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
4417 if (ALL_COP_REG_P (REGNO (dest)))
4419 static char retval[] = "dmtc_\t%z1,%0";
4421 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4422 return dbl_p ? retval : retval + 1;
4425 if (dest_code == MEM)
4426 switch (GET_MODE_SIZE (mode))
4428 case 1: return "sb\t%z1,%0";
4429 case 2: return "sh\t%z1,%0";
4430 case 4: return "sw\t%z1,%0";
4431 case 8: return "sd\t%z1,%0";
4434 if (dest_code == REG && GP_REG_P (REGNO (dest)))
4436 if (src_code == REG)
4438 /* Moves from HI are handled by special .md insns. */
4439 if (REGNO (src) == LO_REGNUM)
4441 /* When generating VR4120 or VR4130 code, we use MACC and
4442 DMACC instead of MFLO. This avoids both the normal
4443 MIPS III HI/LO hazards and the errata related to
4446 return dbl_p ? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
4450 if (DSP_ACC_REG_P (REGNO (src)))
4452 static char retval[] = "mf__\t%0,%q1";
4454 retval[2] = reg_names[REGNO (src)][4];
4455 retval[3] = reg_names[REGNO (src)][5];
4459 if (FP_REG_P (REGNO (src)))
4460 return dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
4462 if (ALL_COP_REG_P (REGNO (src)))
4464 static char retval[] = "dmfc_\t%0,%1";
4466 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4467 return dbl_p ? retval : retval + 1;
4471 if (src_code == MEM)
4472 switch (GET_MODE_SIZE (mode))
4474 case 1: return "lbu\t%0,%1";
4475 case 2: return "lhu\t%0,%1";
4476 case 4: return "lw\t%0,%1";
4477 case 8: return "ld\t%0,%1";
4480 if (src_code == CONST_INT)
4482 /* Don't use the X format for the operand itself, because that
4483 will give out-of-range numbers for 64-bit hosts and 32-bit
4486 return "li\t%0,%1\t\t\t# %X1";
4488 if (SMALL_OPERAND_UNSIGNED (INTVAL (src)))
4491 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src)))
4495 if (src_code == HIGH)
4496 return TARGET_MIPS16 ? "#" : "lui\t%0,%h1";
4498 if (CONST_GP_P (src))
4499 return "move\t%0,%1";
4501 if (mips_symbolic_constant_p (src, SYMBOL_CONTEXT_LEA, &symbol_type)
4502 && mips_lo_relocs[symbol_type] != 0)
4504 /* A signed 16-bit constant formed by applying a relocation
4505 operator to a symbolic address. */
4506 gcc_assert (!mips_split_p[symbol_type]);
4507 return "li\t%0,%R1";
4510 if (symbolic_operand (src, VOIDmode))
4512 gcc_assert (TARGET_MIPS16
4513 ? TARGET_MIPS16_TEXT_LOADS
4514 : !TARGET_EXPLICIT_RELOCS);
4515 return dbl_p ? "dla\t%0,%1" : "la\t%0,%1";
4518 if (src_code == REG && FP_REG_P (REGNO (src)))
4520 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4522 if (GET_MODE (dest) == V2SFmode)
4523 return "mov.ps\t%0,%1";
4525 return dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1";
4528 if (dest_code == MEM)
4529 return dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0";
4531 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4533 if (src_code == MEM)
4534 return dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1";
4536 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
4538 static char retval[] = "l_c_\t%0,%1";
4540 retval[1] = (dbl_p ? 'd' : 'w');
4541 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4544 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
4546 static char retval[] = "s_c_\t%1,%0";
4548 retval[1] = (dbl_p ? 'd' : 'w');
4549 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4555 /* Return true if CMP1 is a suitable second operand for integer ordering
4556 test CODE. See also the *sCC patterns in mips.md. */
4559 mips_int_order_operand_ok_p (enum rtx_code code, rtx cmp1)
4565 return reg_or_0_operand (cmp1, VOIDmode);
4569 return !TARGET_MIPS16 && cmp1 == const1_rtx;
4573 return arith_operand (cmp1, VOIDmode);
4576 return sle_operand (cmp1, VOIDmode);
4579 return sleu_operand (cmp1, VOIDmode);
4586 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4587 integer ordering test *CODE, or if an equivalent combination can
4588 be formed by adjusting *CODE and *CMP1. When returning true, update
4589 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4593 mips_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1,
4594 enum machine_mode mode)
4596 HOST_WIDE_INT plus_one;
4598 if (mips_int_order_operand_ok_p (*code, *cmp1))
4601 if (CONST_INT_P (*cmp1))
4605 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4606 if (INTVAL (*cmp1) < plus_one)
4609 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4615 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4619 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4630 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4631 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4632 is nonnull, it's OK to set TARGET to the inverse of the result and
4633 flip *INVERT_PTR instead. */
4636 mips_emit_int_order_test (enum rtx_code code, bool *invert_ptr,
4637 rtx target, rtx cmp0, rtx cmp1)
4639 enum machine_mode mode;
4641 /* First see if there is a MIPS instruction that can do this operation.
4642 If not, try doing the same for the inverse operation. If that also
4643 fails, force CMP1 into a register and try again. */
4644 mode = GET_MODE (cmp0);
4645 if (mips_canonicalize_int_order_test (&code, &cmp1, mode))
4646 mips_emit_binary (code, target, cmp0, cmp1);
4649 enum rtx_code inv_code = reverse_condition (code);
4650 if (!mips_canonicalize_int_order_test (&inv_code, &cmp1, mode))
4652 cmp1 = force_reg (mode, cmp1);
4653 mips_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1);
4655 else if (invert_ptr == 0)
4659 inv_target = mips_force_binary (GET_MODE (target),
4660 inv_code, cmp0, cmp1);
4661 mips_emit_binary (XOR, target, inv_target, const1_rtx);
4665 *invert_ptr = !*invert_ptr;
4666 mips_emit_binary (inv_code, target, cmp0, cmp1);
4671 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4672 The register will have the same mode as CMP0. */
4675 mips_zero_if_equal (rtx cmp0, rtx cmp1)
4677 if (cmp1 == const0_rtx)
4680 if (uns_arith_operand (cmp1, VOIDmode))
4681 return expand_binop (GET_MODE (cmp0), xor_optab,
4682 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4684 return expand_binop (GET_MODE (cmp0), sub_optab,
4685 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4688 /* Convert *CODE into a code that can be used in a floating-point
4689 scc instruction (C.cond.fmt). Return true if the values of
4690 the condition code registers will be inverted, with 0 indicating
4691 that the condition holds. */
4694 mips_reversed_fp_cond (enum rtx_code *code)
4701 *code = reverse_condition_maybe_unordered (*code);
4709 /* Allocate a floating-point condition-code register of mode MODE.
4711 These condition code registers are used for certain kinds
4712 of compound operation, such as compare and branches, vconds,
4713 and built-in functions. At expand time, their use is entirely
4714 controlled by MIPS-specific code and is entirely internal
4715 to these compound operations.
4717 We could (and did in the past) expose condition-code values
4718 as pseudo registers and leave the register allocator to pick
4719 appropriate registers. The problem is that it is not practically
4720 possible for the rtl optimizers to guarantee that no spills will
4721 be needed, even when AVOID_CCMODE_COPIES is defined. We would
4722 therefore need spill and reload sequences to handle the worst case.
4724 Although such sequences do exist, they are very expensive and are
4725 not something we'd want to use. This is especially true of CCV2 and
4726 CCV4, where all the shuffling would greatly outweigh whatever benefit
4727 the vectorization itself provides.
4729 The main benefit of having more than one condition-code register
4730 is to allow the pipelining of operations, especially those involving
4731 comparisons and conditional moves. We don't really expect the
4732 registers to be live for long periods, and certainly never want
4733 them to be live across calls.
4735 Also, there should be no penalty attached to using all the available
4736 registers. They are simply bits in the same underlying FPU control
4739 We therefore expose the hardware registers from the outset and use
4740 a simple round-robin allocation scheme. */
4743 mips_allocate_fcc (enum machine_mode mode)
4745 unsigned int regno, count;
4747 gcc_assert (TARGET_HARD_FLOAT && ISA_HAS_8CC);
4751 else if (mode == CCV2mode)
4753 else if (mode == CCV4mode)
4758 cfun->machine->next_fcc += -cfun->machine->next_fcc & (count - 1);
4759 if (cfun->machine->next_fcc > ST_REG_LAST - ST_REG_FIRST)
4760 cfun->machine->next_fcc = 0;
4761 regno = ST_REG_FIRST + cfun->machine->next_fcc;
4762 cfun->machine->next_fcc += count;
4763 return gen_rtx_REG (mode, regno);
4766 /* Convert a comparison into something that can be used in a branch or
4767 conditional move. On entry, *OP0 and *OP1 are the values being
4768 compared and *CODE is the code used to compare them.
4770 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
4771 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
4772 otherwise any standard branch condition can be used. The standard branch
4775 - EQ or NE between two registers.
4776 - any comparison between a register and zero. */
4779 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
4784 if (GET_MODE_CLASS (GET_MODE (*op0)) == MODE_INT)
4786 if (!need_eq_ne_p && *op1 == const0_rtx)
4788 else if (*code == EQ || *code == NE)
4792 *op0 = mips_zero_if_equal (cmp_op0, cmp_op1);
4796 *op1 = force_reg (GET_MODE (cmp_op0), cmp_op1);
4800 /* The comparison needs a separate scc instruction. Store the
4801 result of the scc in *OP0 and compare it against zero. */
4802 bool invert = false;
4803 *op0 = gen_reg_rtx (GET_MODE (cmp_op0));
4804 mips_emit_int_order_test (*code, &invert, *op0, cmp_op0, cmp_op1);
4805 *code = (invert ? EQ : NE);
4809 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0)))
4811 *op0 = gen_rtx_REG (CCDSPmode, CCDSP_CC_REGNUM);
4812 mips_emit_binary (*code, *op0, cmp_op0, cmp_op1);
4818 enum rtx_code cmp_code;
4820 /* Floating-point tests use a separate C.cond.fmt comparison to
4821 set a condition code register. The branch or conditional move
4822 will then compare that register against zero.
4824 Set CMP_CODE to the code of the comparison instruction and
4825 *CODE to the code that the branch or move should use. */
4827 *code = mips_reversed_fp_cond (&cmp_code) ? EQ : NE;
4829 ? mips_allocate_fcc (CCmode)
4830 : gen_rtx_REG (CCmode, FPSW_REGNUM));
4832 mips_emit_binary (cmp_code, *op0, cmp_op0, cmp_op1);
4836 /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2]
4837 and OPERAND[3]. Store the result in OPERANDS[0].
4839 On 64-bit targets, the mode of the comparison and target will always be
4840 SImode, thus possibly narrower than that of the comparison's operands. */
4843 mips_expand_scc (rtx operands[])
4845 rtx target = operands[0];
4846 enum rtx_code code = GET_CODE (operands[1]);
4847 rtx op0 = operands[2];
4848 rtx op1 = operands[3];
4850 gcc_assert (GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT);
4852 if (code == EQ || code == NE)
4855 && reg_imm10_operand (op1, GET_MODE (op1)))
4856 mips_emit_binary (code, target, op0, op1);
4859 rtx zie = mips_zero_if_equal (op0, op1);
4860 mips_emit_binary (code, target, zie, const0_rtx);
4864 mips_emit_int_order_test (code, 0, target, op0, op1);
4867 /* Compare OPERANDS[1] with OPERANDS[2] using comparison code
4868 CODE and jump to OPERANDS[3] if the condition holds. */
4871 mips_expand_conditional_branch (rtx *operands)
4873 enum rtx_code code = GET_CODE (operands[0]);
4874 rtx op0 = operands[1];
4875 rtx op1 = operands[2];
4878 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
4879 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
4880 emit_jump_insn (gen_condjump (condition, operands[3]));
4885 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
4886 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
4889 mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
4890 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
4895 reversed_p = mips_reversed_fp_cond (&cond);
4896 cmp_result = mips_allocate_fcc (CCV2mode);
4897 emit_insn (gen_scc_ps (cmp_result,
4898 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
4900 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
4903 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
4907 /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0]
4908 if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
4911 mips_expand_conditional_move (rtx *operands)
4914 enum rtx_code code = GET_CODE (operands[1]);
4915 rtx op0 = XEXP (operands[1], 0);
4916 rtx op1 = XEXP (operands[1], 1);
4918 mips_emit_compare (&code, &op0, &op1, true);
4919 cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
4920 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
4921 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), cond,
4922 operands[2], operands[3])));
4925 /* Perform the comparison in COMPARISON, then trap if the condition holds. */
4928 mips_expand_conditional_trap (rtx comparison)
4931 enum machine_mode mode;
4934 /* MIPS conditional trap instructions don't have GT or LE flavors,
4935 so we must swap the operands and convert to LT and GE respectively. */
4936 code = GET_CODE (comparison);
4943 code = swap_condition (code);
4944 op0 = XEXP (comparison, 1);
4945 op1 = XEXP (comparison, 0);
4949 op0 = XEXP (comparison, 0);
4950 op1 = XEXP (comparison, 1);
4954 mode = GET_MODE (XEXP (comparison, 0));
4955 op0 = force_reg (mode, op0);
4956 if (!arith_operand (op1, mode))
4957 op1 = force_reg (mode, op1);
4959 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
4960 gen_rtx_fmt_ee (code, mode, op0, op1),
4964 /* Initialize *CUM for a call to a function of type FNTYPE. */
4967 mips_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype)
4969 memset (cum, 0, sizeof (*cum));
4970 cum->prototype = (fntype && prototype_p (fntype));
4971 cum->gp_reg_found = (cum->prototype && stdarg_p (fntype));
4974 /* Fill INFO with information about a single argument. CUM is the
4975 cumulative state for earlier arguments. MODE is the mode of this
4976 argument and TYPE is its type (if known). NAMED is true if this
4977 is a named (fixed) argument rather than a variable one. */
4980 mips_get_arg_info (struct mips_arg_info *info, const CUMULATIVE_ARGS *cum,
4981 enum machine_mode mode, const_tree type, bool named)
4983 bool doubleword_aligned_p;
4984 unsigned int num_bytes, num_words, max_regs;
4986 /* Work out the size of the argument. */
4987 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
4988 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4990 /* Decide whether it should go in a floating-point register, assuming
4991 one is free. Later code checks for availability.
4993 The checks against UNITS_PER_FPVALUE handle the soft-float and
4994 single-float cases. */
4998 /* The EABI conventions have traditionally been defined in terms
4999 of TYPE_MODE, regardless of the actual type. */
5000 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
5001 || mode == V2SFmode)
5002 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
5007 /* Only leading floating-point scalars are passed in
5008 floating-point registers. We also handle vector floats the same
5009 say, which is OK because they are not covered by the standard ABI. */
5010 info->fpr_p = (!cum->gp_reg_found
5011 && cum->arg_number < 2
5013 || SCALAR_FLOAT_TYPE_P (type)
5014 || VECTOR_FLOAT_TYPE_P (type))
5015 && (GET_MODE_CLASS (mode) == MODE_FLOAT
5016 || mode == V2SFmode)
5017 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
5022 /* Scalar, complex and vector floating-point types are passed in
5023 floating-point registers, as long as this is a named rather
5024 than a variable argument. */
5025 info->fpr_p = (named
5026 && (type == 0 || FLOAT_TYPE_P (type))
5027 && (GET_MODE_CLASS (mode) == MODE_FLOAT
5028 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5029 || mode == V2SFmode)
5030 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
5032 /* ??? According to the ABI documentation, the real and imaginary
5033 parts of complex floats should be passed in individual registers.
5034 The real and imaginary parts of stack arguments are supposed
5035 to be contiguous and there should be an extra word of padding
5038 This has two problems. First, it makes it impossible to use a
5039 single "void *" va_list type, since register and stack arguments
5040 are passed differently. (At the time of writing, MIPSpro cannot
5041 handle complex float varargs correctly.) Second, it's unclear
5042 what should happen when there is only one register free.
5044 For now, we assume that named complex floats should go into FPRs
5045 if there are two FPRs free, otherwise they should be passed in the
5046 same way as a struct containing two floats. */
5048 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5049 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
5051 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
5052 info->fpr_p = false;
5062 /* See whether the argument has doubleword alignment. */
5063 doubleword_aligned_p = (mips_function_arg_boundary (mode, type)
5066 /* Set REG_OFFSET to the register count we're interested in.
5067 The EABI allocates the floating-point registers separately,
5068 but the other ABIs allocate them like integer registers. */
5069 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
5073 /* Advance to an even register if the argument is doubleword-aligned. */
5074 if (doubleword_aligned_p)
5075 info->reg_offset += info->reg_offset & 1;
5077 /* Work out the offset of a stack argument. */
5078 info->stack_offset = cum->stack_words;
5079 if (doubleword_aligned_p)
5080 info->stack_offset += info->stack_offset & 1;
5082 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
5084 /* Partition the argument between registers and stack. */
5085 info->reg_words = MIN (num_words, max_regs);
5086 info->stack_words = num_words - info->reg_words;
5089 /* INFO describes a register argument that has the normal format for the
5090 argument's mode. Return the register it uses, assuming that FPRs are
5091 available if HARD_FLOAT_P. */
5094 mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p)
5096 if (!info->fpr_p || !hard_float_p)
5097 return GP_ARG_FIRST + info->reg_offset;
5098 else if (mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info->reg_offset > 0)
5099 /* In o32, the second argument is always passed in $f14
5100 for TARGET_DOUBLE_FLOAT, regardless of whether the
5101 first argument was a word or doubleword. */
5102 return FP_ARG_FIRST + 2;
5104 return FP_ARG_FIRST + info->reg_offset;
5107 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
5110 mips_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED)
5112 return !TARGET_OLDABI;
5115 /* Implement TARGET_FUNCTION_ARG. */
5118 mips_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
5119 const_tree type, bool named)
5121 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
5122 struct mips_arg_info info;
5124 /* We will be called with a mode of VOIDmode after the last argument
5125 has been seen. Whatever we return will be passed to the call expander.
5126 If we need a MIPS16 fp_code, return a REG with the code stored as
5128 if (mode == VOIDmode)
5130 if (TARGET_MIPS16 && cum->fp_code != 0)
5131 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
5136 mips_get_arg_info (&info, cum, mode, type, named);
5138 /* Return straight away if the whole argument is passed on the stack. */
5139 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
5142 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
5143 contains a double in its entirety, then that 64-bit chunk is passed
5144 in a floating-point register. */
5146 && TARGET_HARD_FLOAT
5149 && TREE_CODE (type) == RECORD_TYPE
5150 && TYPE_SIZE_UNIT (type)
5151 && host_integerp (TYPE_SIZE_UNIT (type), 1))
5155 /* First check to see if there is any such field. */
5156 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
5157 if (TREE_CODE (field) == FIELD_DECL
5158 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
5159 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
5160 && host_integerp (bit_position (field), 0)
5161 && int_bit_position (field) % BITS_PER_WORD == 0)
5166 /* Now handle the special case by returning a PARALLEL
5167 indicating where each 64-bit chunk goes. INFO.REG_WORDS
5168 chunks are passed in registers. */
5170 HOST_WIDE_INT bitpos;
5173 /* assign_parms checks the mode of ENTRY_PARM, so we must
5174 use the actual mode here. */
5175 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
5178 field = TYPE_FIELDS (type);
5179 for (i = 0; i < info.reg_words; i++)
5183 for (; field; field = DECL_CHAIN (field))
5184 if (TREE_CODE (field) == FIELD_DECL
5185 && int_bit_position (field) >= bitpos)
5189 && int_bit_position (field) == bitpos
5190 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
5191 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
5192 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
5194 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
5197 = gen_rtx_EXPR_LIST (VOIDmode, reg,
5198 GEN_INT (bitpos / BITS_PER_UNIT));
5200 bitpos += BITS_PER_WORD;
5206 /* Handle the n32/n64 conventions for passing complex floating-point
5207 arguments in FPR pairs. The real part goes in the lower register
5208 and the imaginary part goes in the upper register. */
5211 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5214 enum machine_mode inner;
5217 inner = GET_MODE_INNER (mode);
5218 regno = FP_ARG_FIRST + info.reg_offset;
5219 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
5221 /* Real part in registers, imaginary part on stack. */
5222 gcc_assert (info.stack_words == info.reg_words);
5223 return gen_rtx_REG (inner, regno);
5227 gcc_assert (info.stack_words == 0);
5228 real = gen_rtx_EXPR_LIST (VOIDmode,
5229 gen_rtx_REG (inner, regno),
5231 imag = gen_rtx_EXPR_LIST (VOIDmode,
5233 regno + info.reg_words / 2),
5234 GEN_INT (GET_MODE_SIZE (inner)));
5235 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
5239 return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT));
5242 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
5245 mips_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
5246 const_tree type, bool named)
5248 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
5249 struct mips_arg_info info;
5251 mips_get_arg_info (&info, cum, mode, type, named);
5254 cum->gp_reg_found = true;
5256 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
5257 an explanation of what this code does. It assumes that we're using
5258 either the o32 or the o64 ABI, both of which pass at most 2 arguments
5260 if (cum->arg_number < 2 && info.fpr_p)
5261 cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2);
5263 /* Advance the register count. This has the effect of setting
5264 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
5265 argument required us to skip the final GPR and pass the whole
5266 argument on the stack. */
5267 if (mips_abi != ABI_EABI || !info.fpr_p)
5268 cum->num_gprs = info.reg_offset + info.reg_words;
5269 else if (info.reg_words > 0)
5270 cum->num_fprs += MAX_FPRS_PER_FMT;
5272 /* Advance the stack word count. */
5273 if (info.stack_words > 0)
5274 cum->stack_words = info.stack_offset + info.stack_words;
5279 /* Implement TARGET_ARG_PARTIAL_BYTES. */
5282 mips_arg_partial_bytes (cumulative_args_t cum,
5283 enum machine_mode mode, tree type, bool named)
5285 struct mips_arg_info info;
5287 mips_get_arg_info (&info, get_cumulative_args (cum), mode, type, named);
5288 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
5291 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
5292 least PARM_BOUNDARY bits of alignment, but will be given anything up
5293 to STACK_BOUNDARY bits if the type requires it. */
5296 mips_function_arg_boundary (enum machine_mode mode, const_tree type)
5298 unsigned int alignment;
5300 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
5301 if (alignment < PARM_BOUNDARY)
5302 alignment = PARM_BOUNDARY;
5303 if (alignment > STACK_BOUNDARY)
5304 alignment = STACK_BOUNDARY;
5308 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
5309 upward rather than downward. In other words, return true if the
5310 first byte of the stack slot has useful data, false if the last
5314 mips_pad_arg_upward (enum machine_mode mode, const_tree type)
5316 /* On little-endian targets, the first byte of every stack argument
5317 is passed in the first byte of the stack slot. */
5318 if (!BYTES_BIG_ENDIAN)
5321 /* Otherwise, integral types are padded downward: the last byte of a
5322 stack argument is passed in the last byte of the stack slot. */
5324 ? (INTEGRAL_TYPE_P (type)
5325 || POINTER_TYPE_P (type)
5326 || FIXED_POINT_TYPE_P (type))
5327 : (SCALAR_INT_MODE_P (mode)
5328 || ALL_SCALAR_FIXED_POINT_MODE_P (mode)))
5331 /* Big-endian o64 pads floating-point arguments downward. */
5332 if (mips_abi == ABI_O64)
5333 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
5336 /* Other types are padded upward for o32, o64, n32 and n64. */
5337 if (mips_abi != ABI_EABI)
5340 /* Arguments smaller than a stack slot are padded downward. */
5341 if (mode != BLKmode)
5342 return GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY;
5344 return int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT);
5347 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
5348 if the least significant byte of the register has useful data. Return
5349 the opposite if the most significant byte does. */
5352 mips_pad_reg_upward (enum machine_mode mode, tree type)
5354 /* No shifting is required for floating-point arguments. */
5355 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
5356 return !BYTES_BIG_ENDIAN;
5358 /* Otherwise, apply the same padding to register arguments as we do
5359 to stack arguments. */
5360 return mips_pad_arg_upward (mode, type);
5363 /* Return nonzero when an argument must be passed by reference. */
5366 mips_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
5367 enum machine_mode mode, const_tree type,
5368 bool named ATTRIBUTE_UNUSED)
5370 if (mips_abi == ABI_EABI)
5374 /* ??? How should SCmode be handled? */
5375 if (mode == DImode || mode == DFmode
5376 || mode == DQmode || mode == UDQmode
5377 || mode == DAmode || mode == UDAmode)
5380 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
5381 return size == -1 || size > UNITS_PER_WORD;
5385 /* If we have a variable-sized parameter, we have no choice. */
5386 return targetm.calls.must_pass_in_stack (mode, type);
5390 /* Implement TARGET_CALLEE_COPIES. */
5393 mips_callee_copies (cumulative_args_t cum ATTRIBUTE_UNUSED,
5394 enum machine_mode mode ATTRIBUTE_UNUSED,
5395 const_tree type ATTRIBUTE_UNUSED, bool named)
5397 return mips_abi == ABI_EABI && named;
5400 /* See whether VALTYPE is a record whose fields should be returned in
5401 floating-point registers. If so, return the number of fields and
5402 list them in FIELDS (which should have two elements). Return 0
5405 For n32 & n64, a structure with one or two fields is returned in
5406 floating-point registers as long as every field has a floating-point
5410 mips_fpr_return_fields (const_tree valtype, tree *fields)
5418 if (TREE_CODE (valtype) != RECORD_TYPE)
5422 for (field = TYPE_FIELDS (valtype); field != 0; field = DECL_CHAIN (field))
5424 if (TREE_CODE (field) != FIELD_DECL)
5427 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)))
5433 fields[i++] = field;
5438 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
5439 a value in the most significant part of $2/$3 if:
5441 - the target is big-endian;
5443 - the value has a structure or union type (we generalize this to
5444 cover aggregates from other languages too); and
5446 - the structure is not returned in floating-point registers. */
5449 mips_return_in_msb (const_tree valtype)
5453 return (TARGET_NEWABI
5454 && TARGET_BIG_ENDIAN
5455 && AGGREGATE_TYPE_P (valtype)
5456 && mips_fpr_return_fields (valtype, fields) == 0);
5459 /* Return true if the function return value MODE will get returned in a
5460 floating-point register. */
5463 mips_return_mode_in_fpr_p (enum machine_mode mode)
5465 return ((GET_MODE_CLASS (mode) == MODE_FLOAT
5467 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5468 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE);
5471 /* Return the representation of an FPR return register when the
5472 value being returned in FP_RETURN has mode VALUE_MODE and the
5473 return type itself has mode TYPE_MODE. On NewABI targets,
5474 the two modes may be different for structures like:
5476 struct __attribute__((packed)) foo { float f; }
5478 where we return the SFmode value of "f" in FP_RETURN, but where
5479 the structure itself has mode BLKmode. */
5482 mips_return_fpr_single (enum machine_mode type_mode,
5483 enum machine_mode value_mode)
5487 x = gen_rtx_REG (value_mode, FP_RETURN);
5488 if (type_mode != value_mode)
5490 x = gen_rtx_EXPR_LIST (VOIDmode, x, const0_rtx);
5491 x = gen_rtx_PARALLEL (type_mode, gen_rtvec (1, x));
5496 /* Return a composite value in a pair of floating-point registers.
5497 MODE1 and OFFSET1 are the mode and byte offset for the first value,
5498 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
5501 For n32 & n64, $f0 always holds the first value and $f2 the second.
5502 Otherwise the values are packed together as closely as possible. */
5505 mips_return_fpr_pair (enum machine_mode mode,
5506 enum machine_mode mode1, HOST_WIDE_INT offset1,
5507 enum machine_mode mode2, HOST_WIDE_INT offset2)
5511 inc = (TARGET_NEWABI ? 2 : MAX_FPRS_PER_FMT);
5512 return gen_rtx_PARALLEL
5515 gen_rtx_EXPR_LIST (VOIDmode,
5516 gen_rtx_REG (mode1, FP_RETURN),
5518 gen_rtx_EXPR_LIST (VOIDmode,
5519 gen_rtx_REG (mode2, FP_RETURN + inc),
5520 GEN_INT (offset2))));
5524 /* Implement TARGET_FUNCTION_VALUE and TARGET_LIBCALL_VALUE.
5525 For normal calls, VALTYPE is the return type and MODE is VOIDmode.
5526 For libcalls, VALTYPE is null and MODE is the mode of the return value. */
5529 mips_function_value_1 (const_tree valtype, const_tree fn_decl_or_type,
5530 enum machine_mode mode)
5538 if (fn_decl_or_type && DECL_P (fn_decl_or_type))
5539 func = fn_decl_or_type;
5543 mode = TYPE_MODE (valtype);
5544 unsigned_p = TYPE_UNSIGNED (valtype);
5546 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
5547 return values, promote the mode here too. */
5548 mode = promote_function_mode (valtype, mode, &unsigned_p, func, 1);
5550 /* Handle structures whose fields are returned in $f0/$f2. */
5551 switch (mips_fpr_return_fields (valtype, fields))
5554 return mips_return_fpr_single (mode,
5555 TYPE_MODE (TREE_TYPE (fields[0])));
5558 return mips_return_fpr_pair (mode,
5559 TYPE_MODE (TREE_TYPE (fields[0])),
5560 int_byte_position (fields[0]),
5561 TYPE_MODE (TREE_TYPE (fields[1])),
5562 int_byte_position (fields[1]));
5565 /* If a value is passed in the most significant part of a register, see
5566 whether we have to round the mode up to a whole number of words. */
5567 if (mips_return_in_msb (valtype))
5569 HOST_WIDE_INT size = int_size_in_bytes (valtype);
5570 if (size % UNITS_PER_WORD != 0)
5572 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
5573 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
5577 /* For EABI, the class of return register depends entirely on MODE.
5578 For example, "struct { some_type x; }" and "union { some_type x; }"
5579 are returned in the same way as a bare "some_type" would be.
5580 Other ABIs only use FPRs for scalar, complex or vector types. */
5581 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
5582 return gen_rtx_REG (mode, GP_RETURN);
5587 /* Handle long doubles for n32 & n64. */
5589 return mips_return_fpr_pair (mode,
5591 DImode, GET_MODE_SIZE (mode) / 2);
5593 if (mips_return_mode_in_fpr_p (mode))
5595 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5596 return mips_return_fpr_pair (mode,
5597 GET_MODE_INNER (mode), 0,
5598 GET_MODE_INNER (mode),
5599 GET_MODE_SIZE (mode) / 2);
5601 return gen_rtx_REG (mode, FP_RETURN);
5605 return gen_rtx_REG (mode, GP_RETURN);
5608 /* Implement TARGET_FUNCTION_VALUE. */
5611 mips_function_value (const_tree valtype, const_tree fn_decl_or_type,
5612 bool outgoing ATTRIBUTE_UNUSED)
5614 return mips_function_value_1 (valtype, fn_decl_or_type, VOIDmode);
5617 /* Implement TARGET_LIBCALL_VALUE. */
5620 mips_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
5622 return mips_function_value_1 (NULL_TREE, NULL_TREE, mode);
5625 /* Implement TARGET_FUNCTION_VALUE_REGNO_P.
5627 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
5628 Currently, R2 and F0 are only implemented here (C has no complex type). */
5631 mips_function_value_regno_p (const unsigned int regno)
5633 if (regno == GP_RETURN
5634 || regno == FP_RETURN
5635 || (LONG_DOUBLE_TYPE_SIZE == 128
5636 && FP_RETURN != GP_RETURN
5637 && regno == FP_RETURN + 2))
5643 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
5644 all BLKmode objects are returned in memory. Under the n32, n64
5645 and embedded ABIs, small structures are returned in a register.
5646 Objects with varying size must still be returned in memory, of
5650 mips_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
5652 return (TARGET_OLDABI
5653 ? TYPE_MODE (type) == BLKmode
5654 : !IN_RANGE (int_size_in_bytes (type), 0, 2 * UNITS_PER_WORD));
5657 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
5660 mips_setup_incoming_varargs (cumulative_args_t cum, enum machine_mode mode,
5661 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5664 CUMULATIVE_ARGS local_cum;
5665 int gp_saved, fp_saved;
5667 /* The caller has advanced CUM up to, but not beyond, the last named
5668 argument. Advance a local copy of CUM past the last "real" named
5669 argument, to find out how many registers are left over. */
5670 local_cum = *get_cumulative_args (cum);
5671 mips_function_arg_advance (pack_cumulative_args (&local_cum), mode, type,
5674 /* Found out how many registers we need to save. */
5675 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
5676 fp_saved = (EABI_FLOAT_VARARGS_P
5677 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
5686 ptr = plus_constant (Pmode, virtual_incoming_args_rtx,
5687 REG_PARM_STACK_SPACE (cfun->decl)
5688 - gp_saved * UNITS_PER_WORD);
5689 mem = gen_frame_mem (BLKmode, ptr);
5690 set_mem_alias_set (mem, get_varargs_alias_set ());
5692 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
5697 /* We can't use move_block_from_reg, because it will use
5699 enum machine_mode mode;
5702 /* Set OFF to the offset from virtual_incoming_args_rtx of
5703 the first float register. The FP save area lies below
5704 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
5705 off = (-gp_saved * UNITS_PER_WORD) & -UNITS_PER_FPVALUE;
5706 off -= fp_saved * UNITS_PER_FPREG;
5708 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
5710 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS;
5711 i += MAX_FPRS_PER_FMT)
5715 ptr = plus_constant (Pmode, virtual_incoming_args_rtx, off);
5716 mem = gen_frame_mem (mode, ptr);
5717 set_mem_alias_set (mem, get_varargs_alias_set ());
5718 mips_emit_move (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
5719 off += UNITS_PER_HWFPVALUE;
5723 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
5724 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
5725 + fp_saved * UNITS_PER_FPREG);
5728 /* Implement TARGET_BUILTIN_VA_LIST. */
5731 mips_build_builtin_va_list (void)
5733 if (EABI_FLOAT_VARARGS_P)
5735 /* We keep 3 pointers, and two offsets.
5737 Two pointers are to the overflow area, which starts at the CFA.
5738 One of these is constant, for addressing into the GPR save area
5739 below it. The other is advanced up the stack through the
5742 The third pointer is to the bottom of the GPR save area.
5743 Since the FPR save area is just below it, we can address
5744 FPR slots off this pointer.
5746 We also keep two one-byte offsets, which are to be subtracted
5747 from the constant pointers to yield addresses in the GPR and
5748 FPR save areas. These are downcounted as float or non-float
5749 arguments are used, and when they get to zero, the argument
5750 must be obtained from the overflow region. */
5751 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
5754 record = lang_hooks.types.make_type (RECORD_TYPE);
5756 f_ovfl = build_decl (BUILTINS_LOCATION,
5757 FIELD_DECL, get_identifier ("__overflow_argptr"),
5759 f_gtop = build_decl (BUILTINS_LOCATION,
5760 FIELD_DECL, get_identifier ("__gpr_top"),
5762 f_ftop = build_decl (BUILTINS_LOCATION,
5763 FIELD_DECL, get_identifier ("__fpr_top"),
5765 f_goff = build_decl (BUILTINS_LOCATION,
5766 FIELD_DECL, get_identifier ("__gpr_offset"),
5767 unsigned_char_type_node);
5768 f_foff = build_decl (BUILTINS_LOCATION,
5769 FIELD_DECL, get_identifier ("__fpr_offset"),
5770 unsigned_char_type_node);
5771 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
5772 warn on every user file. */
5773 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
5774 array = build_array_type (unsigned_char_type_node,
5775 build_index_type (index));
5776 f_res = build_decl (BUILTINS_LOCATION,
5777 FIELD_DECL, get_identifier ("__reserved"), array);
5779 DECL_FIELD_CONTEXT (f_ovfl) = record;
5780 DECL_FIELD_CONTEXT (f_gtop) = record;
5781 DECL_FIELD_CONTEXT (f_ftop) = record;
5782 DECL_FIELD_CONTEXT (f_goff) = record;
5783 DECL_FIELD_CONTEXT (f_foff) = record;
5784 DECL_FIELD_CONTEXT (f_res) = record;
5786 TYPE_FIELDS (record) = f_ovfl;
5787 DECL_CHAIN (f_ovfl) = f_gtop;
5788 DECL_CHAIN (f_gtop) = f_ftop;
5789 DECL_CHAIN (f_ftop) = f_goff;
5790 DECL_CHAIN (f_goff) = f_foff;
5791 DECL_CHAIN (f_foff) = f_res;
5793 layout_type (record);
5797 /* Otherwise, we use 'void *'. */
5798 return ptr_type_node;
5801 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
5804 mips_va_start (tree valist, rtx nextarg)
5806 if (EABI_FLOAT_VARARGS_P)
5808 const CUMULATIVE_ARGS *cum;
5809 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5810 tree ovfl, gtop, ftop, goff, foff;
5812 int gpr_save_area_size;
5813 int fpr_save_area_size;
5816 cum = &crtl->args.info;
5818 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
5820 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
5822 f_ovfl = TYPE_FIELDS (va_list_type_node);
5823 f_gtop = DECL_CHAIN (f_ovfl);
5824 f_ftop = DECL_CHAIN (f_gtop);
5825 f_goff = DECL_CHAIN (f_ftop);
5826 f_foff = DECL_CHAIN (f_goff);
5828 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5830 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
5832 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
5834 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
5836 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
5839 /* Emit code to initialize OVFL, which points to the next varargs
5840 stack argument. CUM->STACK_WORDS gives the number of stack
5841 words used by named arguments. */
5842 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
5843 if (cum->stack_words > 0)
5844 t = fold_build_pointer_plus_hwi (t, cum->stack_words * UNITS_PER_WORD);
5845 t = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
5846 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5848 /* Emit code to initialize GTOP, the top of the GPR save area. */
5849 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
5850 t = build2 (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
5851 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5853 /* Emit code to initialize FTOP, the top of the FPR save area.
5854 This address is gpr_save_area_bytes below GTOP, rounded
5855 down to the next fp-aligned boundary. */
5856 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
5857 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
5858 fpr_offset &= -UNITS_PER_FPVALUE;
5860 t = fold_build_pointer_plus_hwi (t, -fpr_offset);
5861 t = build2 (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
5862 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5864 /* Emit code to initialize GOFF, the offset from GTOP of the
5865 next GPR argument. */
5866 t = build2 (MODIFY_EXPR, TREE_TYPE (goff), goff,
5867 build_int_cst (TREE_TYPE (goff), gpr_save_area_size));
5868 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5870 /* Likewise emit code to initialize FOFF, the offset from FTOP
5871 of the next FPR argument. */
5872 t = build2 (MODIFY_EXPR, TREE_TYPE (foff), foff,
5873 build_int_cst (TREE_TYPE (foff), fpr_save_area_size));
5874 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5878 nextarg = plus_constant (Pmode, nextarg, -cfun->machine->varargs_size);
5879 std_expand_builtin_va_start (valist, nextarg);
5883 /* Like std_gimplify_va_arg_expr, but apply alignment to zero-sized
5887 mips_std_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
5890 tree addr, t, type_size, rounded_size, valist_tmp;
5891 unsigned HOST_WIDE_INT align, boundary;
5894 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, false);
5896 type = build_pointer_type (type);
5898 align = PARM_BOUNDARY / BITS_PER_UNIT;
5899 boundary = targetm.calls.function_arg_boundary (TYPE_MODE (type), type);
5901 /* When we align parameter on stack for caller, if the parameter
5902 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
5903 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
5904 here with caller. */
5905 if (boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
5906 boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
5908 boundary /= BITS_PER_UNIT;
5910 /* Hoist the valist value into a temporary for the moment. */
5911 valist_tmp = get_initialized_tmp_var (valist, pre_p, NULL);
5913 /* va_list pointer is aligned to PARM_BOUNDARY. If argument actually
5914 requires greater alignment, we must perform dynamic alignment. */
5915 if (boundary > align)
5917 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
5918 fold_build_pointer_plus_hwi (valist_tmp, boundary - 1));
5919 gimplify_and_add (t, pre_p);
5921 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
5922 fold_build2 (BIT_AND_EXPR, TREE_TYPE (valist),
5924 build_int_cst (TREE_TYPE (valist), -boundary)));
5925 gimplify_and_add (t, pre_p);
5930 /* If the actual alignment is less than the alignment of the type,
5931 adjust the type accordingly so that we don't assume strict alignment
5932 when dereferencing the pointer. */
5933 boundary *= BITS_PER_UNIT;
5934 if (boundary < TYPE_ALIGN (type))
5936 type = build_variant_type_copy (type);
5937 TYPE_ALIGN (type) = boundary;
5940 /* Compute the rounded size of the type. */
5941 type_size = size_in_bytes (type);
5942 rounded_size = round_up (type_size, align);
5944 /* Reduce rounded_size so it's sharable with the postqueue. */
5945 gimplify_expr (&rounded_size, pre_p, post_p, is_gimple_val, fb_rvalue);
5949 if (PAD_VARARGS_DOWN && !integer_zerop (rounded_size))
5951 /* Small args are padded downward. */
5952 t = fold_build2_loc (input_location, GT_EXPR, sizetype,
5953 rounded_size, size_int (align));
5954 t = fold_build3 (COND_EXPR, sizetype, t, size_zero_node,
5955 size_binop (MINUS_EXPR, rounded_size, type_size));
5956 addr = fold_build_pointer_plus (addr, t);
5959 /* Compute new value for AP. */
5960 t = fold_build_pointer_plus (valist_tmp, rounded_size);
5961 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
5962 gimplify_and_add (t, pre_p);
5964 addr = fold_convert (build_pointer_type (type), addr);
5967 addr = build_va_arg_indirect_ref (addr);
5969 return build_va_arg_indirect_ref (addr);
5972 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
5975 mips_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
5981 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
5983 type = build_pointer_type (type);
5985 if (!EABI_FLOAT_VARARGS_P)
5986 addr = mips_std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5989 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5990 tree ovfl, top, off, align;
5991 HOST_WIDE_INT size, rsize, osize;
5994 f_ovfl = TYPE_FIELDS (va_list_type_node);
5995 f_gtop = DECL_CHAIN (f_ovfl);
5996 f_ftop = DECL_CHAIN (f_gtop);
5997 f_goff = DECL_CHAIN (f_ftop);
5998 f_foff = DECL_CHAIN (f_goff);
6002 TOP be the top of the GPR or FPR save area;
6003 OFF be the offset from TOP of the next register;
6004 ADDR_RTX be the address of the argument;
6005 SIZE be the number of bytes in the argument type;
6006 RSIZE be the number of bytes used to store the argument
6007 when it's in the register save area; and
6008 OSIZE be the number of bytes used to store it when it's
6009 in the stack overflow area.
6011 The code we want is:
6013 1: off &= -rsize; // round down
6016 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
6021 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
6022 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
6026 [1] and [9] can sometimes be optimized away. */
6028 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
6030 size = int_size_in_bytes (type);
6032 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
6033 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
6035 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop),
6036 unshare_expr (valist), f_ftop, NULL_TREE);
6037 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff),
6038 unshare_expr (valist), f_foff, NULL_TREE);
6040 /* When va_start saves FPR arguments to the stack, each slot
6041 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
6042 argument's precision. */
6043 rsize = UNITS_PER_HWFPVALUE;
6045 /* Overflow arguments are padded to UNITS_PER_WORD bytes
6046 (= PARM_BOUNDARY bits). This can be different from RSIZE
6049 (1) On 32-bit targets when TYPE is a structure such as:
6051 struct s { float f; };
6053 Such structures are passed in paired FPRs, so RSIZE
6054 will be 8 bytes. However, the structure only takes
6055 up 4 bytes of memory, so OSIZE will only be 4.
6057 (2) In combinations such as -mgp64 -msingle-float
6058 -fshort-double. Doubles passed in registers will then take
6059 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
6060 stack take up UNITS_PER_WORD bytes. */
6061 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
6065 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop),
6066 unshare_expr (valist), f_gtop, NULL_TREE);
6067 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff),
6068 unshare_expr (valist), f_goff, NULL_TREE);
6069 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
6070 if (rsize > UNITS_PER_WORD)
6072 /* [1] Emit code for: off &= -rsize. */
6073 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), unshare_expr (off),
6074 build_int_cst (TREE_TYPE (off), -rsize));
6075 gimplify_assign (unshare_expr (off), t, pre_p);
6080 /* [2] Emit code to branch if off == 0. */
6081 t = build2 (NE_EXPR, boolean_type_node, unshare_expr (off),
6082 build_int_cst (TREE_TYPE (off), 0));
6083 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
6085 /* [5] Emit code for: off -= rsize. We do this as a form of
6086 post-decrement not available to C. */
6087 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
6088 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
6090 /* [4] Emit code for:
6091 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
6092 t = fold_convert (sizetype, t);
6093 t = fold_build1 (NEGATE_EXPR, sizetype, t);
6094 t = fold_build_pointer_plus (top, t);
6095 if (BYTES_BIG_ENDIAN && rsize > size)
6096 t = fold_build_pointer_plus_hwi (t, rsize - size);
6097 COND_EXPR_THEN (addr) = t;
6099 if (osize > UNITS_PER_WORD)
6101 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
6102 t = fold_build_pointer_plus_hwi (unshare_expr (ovfl), osize - 1);
6103 u = build_int_cst (TREE_TYPE (t), -osize);
6104 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t, u);
6105 align = build2 (MODIFY_EXPR, TREE_TYPE (ovfl),
6106 unshare_expr (ovfl), t);
6111 /* [10, 11] Emit code for:
6112 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
6114 u = fold_convert (TREE_TYPE (ovfl), build_int_cst (NULL_TREE, osize));
6115 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
6116 if (BYTES_BIG_ENDIAN && osize > size)
6117 t = fold_build_pointer_plus_hwi (t, osize - size);
6119 /* String [9] and [10, 11] together. */
6121 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
6122 COND_EXPR_ELSE (addr) = t;
6124 addr = fold_convert (build_pointer_type (type), addr);
6125 addr = build_va_arg_indirect_ref (addr);
6129 addr = build_va_arg_indirect_ref (addr);
6134 /* Declare a unique, locally-binding function called NAME, then start
6138 mips_start_unique_function (const char *name)
6142 decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
6143 get_identifier (name),
6144 build_function_type_list (void_type_node, NULL_TREE));
6145 DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
6146 NULL_TREE, void_type_node);
6147 TREE_PUBLIC (decl) = 1;
6148 TREE_STATIC (decl) = 1;
6150 DECL_COMDAT_GROUP (decl) = DECL_ASSEMBLER_NAME (decl);
6152 targetm.asm_out.unique_section (decl, 0);
6153 switch_to_section (get_named_section (decl, NULL, 0));
6155 targetm.asm_out.globalize_label (asm_out_file, name);
6156 fputs ("\t.hidden\t", asm_out_file);
6157 assemble_name (asm_out_file, name);
6158 putc ('\n', asm_out_file);
6161 /* Start a definition of function NAME. MIPS16_P indicates whether the
6162 function contains MIPS16 code. */
6165 mips_start_function_definition (const char *name, bool mips16_p)
6168 fprintf (asm_out_file, "\t.set\tmips16\n");
6170 fprintf (asm_out_file, "\t.set\tnomips16\n");
6172 if (TARGET_MICROMIPS)
6173 fprintf (asm_out_file, "\t.set\tmicromips\n");
6174 #ifdef HAVE_GAS_MICROMIPS
6176 fprintf (asm_out_file, "\t.set\tnomicromips\n");
6179 if (!flag_inhibit_size_directive)
6181 fputs ("\t.ent\t", asm_out_file);
6182 assemble_name (asm_out_file, name);
6183 fputs ("\n", asm_out_file);
6186 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, name, "function");
6188 /* Start the definition proper. */
6189 assemble_name (asm_out_file, name);
6190 fputs (":\n", asm_out_file);
6193 /* End a function definition started by mips_start_function_definition. */
6196 mips_end_function_definition (const char *name)
6198 if (!flag_inhibit_size_directive)
6200 fputs ("\t.end\t", asm_out_file);
6201 assemble_name (asm_out_file, name);
6202 fputs ("\n", asm_out_file);
6206 /* Output a definition of the __mips16_rdhwr function. */
6209 mips_output_mips16_rdhwr (void)
6213 name = "__mips16_rdhwr";
6214 mips_start_unique_function (name);
6215 mips_start_function_definition (name, false);
6216 fprintf (asm_out_file,
6218 "\t.set\tmips32r2\n"
6219 "\t.set\tnoreorder\n"
6223 mips_end_function_definition (name);
6226 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
6229 mips_ok_for_lazy_binding_p (rtx x)
6231 return (TARGET_USE_GOT
6232 && GET_CODE (x) == SYMBOL_REF
6233 && !SYMBOL_REF_BIND_NOW_P (x)
6234 && !mips_symbol_binds_local_p (x));
6237 /* Load function address ADDR into register DEST. TYPE is as for
6238 mips_expand_call. Return true if we used an explicit lazy-binding
6242 mips_load_call_address (enum mips_call_type type, rtx dest, rtx addr)
6244 /* If we're generating PIC, and this call is to a global function,
6245 try to allow its address to be resolved lazily. This isn't
6246 possible for sibcalls when $gp is call-saved because the value
6247 of $gp on entry to the stub would be our caller's gp, not ours. */
6248 if (TARGET_EXPLICIT_RELOCS
6249 && !(type == MIPS_CALL_SIBCALL && TARGET_CALL_SAVED_GP)
6250 && mips_ok_for_lazy_binding_p (addr))
6252 addr = mips_got_load (dest, addr, SYMBOL_GOTOFF_CALL);
6253 emit_insn (gen_rtx_SET (VOIDmode, dest, addr));
6258 mips_emit_move (dest, addr);
6263 /* Each locally-defined hard-float MIPS16 function has a local symbol
6264 associated with it. This hash table maps the function symbol (FUNC)
6265 to the local symbol (LOCAL). */
6266 struct GTY(()) mips16_local_alias {
6270 static GTY ((param_is (struct mips16_local_alias))) htab_t mips16_local_aliases;
6272 /* Hash table callbacks for mips16_local_aliases. */
6275 mips16_local_aliases_hash (const void *entry)
6277 const struct mips16_local_alias *alias;
6279 alias = (const struct mips16_local_alias *) entry;
6280 return htab_hash_string (XSTR (alias->func, 0));
6284 mips16_local_aliases_eq (const void *entry1, const void *entry2)
6286 const struct mips16_local_alias *alias1, *alias2;
6288 alias1 = (const struct mips16_local_alias *) entry1;
6289 alias2 = (const struct mips16_local_alias *) entry2;
6290 return rtx_equal_p (alias1->func, alias2->func);
6293 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
6294 Return a local alias for it, creating a new one if necessary. */
6297 mips16_local_alias (rtx func)
6299 struct mips16_local_alias *alias, tmp_alias;
6302 /* Create the hash table if this is the first call. */
6303 if (mips16_local_aliases == NULL)
6304 mips16_local_aliases = htab_create_ggc (37, mips16_local_aliases_hash,
6305 mips16_local_aliases_eq, NULL);
6307 /* Look up the function symbol, creating a new entry if need be. */
6308 tmp_alias.func = func;
6309 slot = htab_find_slot (mips16_local_aliases, &tmp_alias, INSERT);
6310 gcc_assert (slot != NULL);
6312 alias = (struct mips16_local_alias *) *slot;
6315 const char *func_name, *local_name;
6318 /* Create a new SYMBOL_REF for the local symbol. The choice of
6319 __fn_local_* is based on the __fn_stub_* names that we've
6320 traditionally used for the non-MIPS16 stub. */
6321 func_name = targetm.strip_name_encoding (XSTR (func, 0));
6322 local_name = ACONCAT (("__fn_local_", func_name, NULL));
6323 local = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (local_name));
6324 SYMBOL_REF_FLAGS (local) = SYMBOL_REF_FLAGS (func) | SYMBOL_FLAG_LOCAL;
6326 /* Create a new structure to represent the mapping. */
6327 alias = ggc_alloc_mips16_local_alias ();
6329 alias->local = local;
6332 return alias->local;
6335 /* A chained list of functions for which mips16_build_call_stub has already
6336 generated a stub. NAME is the name of the function and FP_RET_P is true
6337 if the function returns a value in floating-point registers. */
6338 struct mips16_stub {
6339 struct mips16_stub *next;
6343 static struct mips16_stub *mips16_stubs;
6345 /* Return the two-character string that identifies floating-point
6346 return mode MODE in the name of a MIPS16 function stub. */
6349 mips16_call_stub_mode_suffix (enum machine_mode mode)
6353 else if (mode == DFmode)
6355 else if (mode == SCmode)
6357 else if (mode == DCmode)
6359 else if (mode == V2SFmode)
6365 /* Write instructions to move a 32-bit value between general register
6366 GPREG and floating-point register FPREG. DIRECTION is 't' to move
6367 from GPREG to FPREG and 'f' to move in the opposite direction. */
6370 mips_output_32bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
6372 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6373 reg_names[gpreg], reg_names[fpreg]);
6376 /* Likewise for 64-bit values. */
6379 mips_output_64bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
6382 fprintf (asm_out_file, "\tdm%cc1\t%s,%s\n", direction,
6383 reg_names[gpreg], reg_names[fpreg]);
6384 else if (TARGET_FLOAT64)
6386 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6387 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
6388 fprintf (asm_out_file, "\tm%chc1\t%s,%s\n", direction,
6389 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg]);
6393 /* Move the least-significant word. */
6394 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6395 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
6396 /* ...then the most significant word. */
6397 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6398 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg + 1]);
6402 /* Write out code to move floating-point arguments into or out of
6403 general registers. FP_CODE is the code describing which arguments
6404 are present (see the comment above the definition of CUMULATIVE_ARGS
6405 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
6408 mips_output_args_xfer (int fp_code, char direction)
6410 unsigned int gparg, fparg, f;
6411 CUMULATIVE_ARGS cum;
6413 /* This code only works for o32 and o64. */
6414 gcc_assert (TARGET_OLDABI);
6416 mips_init_cumulative_args (&cum, NULL);
6418 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
6420 enum machine_mode mode;
6421 struct mips_arg_info info;
6425 else if ((f & 3) == 2)
6430 mips_get_arg_info (&info, &cum, mode, NULL, true);
6431 gparg = mips_arg_regno (&info, false);
6432 fparg = mips_arg_regno (&info, true);
6435 mips_output_32bit_xfer (direction, gparg, fparg);
6437 mips_output_64bit_xfer (direction, gparg, fparg);
6439 mips_function_arg_advance (pack_cumulative_args (&cum), mode, NULL, true);
6443 /* Write a MIPS16 stub for the current function. This stub is used
6444 for functions which take arguments in the floating-point registers.
6445 It is normal-mode code that moves the floating-point arguments
6446 into the general registers and then jumps to the MIPS16 code. */
6449 mips16_build_function_stub (void)
6451 const char *fnname, *alias_name, *separator;
6452 char *secname, *stubname;
6457 /* Create the name of the stub, and its unique section. */
6458 symbol = XEXP (DECL_RTL (current_function_decl), 0);
6459 alias = mips16_local_alias (symbol);
6461 fnname = targetm.strip_name_encoding (XSTR (symbol, 0));
6462 alias_name = targetm.strip_name_encoding (XSTR (alias, 0));
6463 secname = ACONCAT ((".mips16.fn.", fnname, NULL));
6464 stubname = ACONCAT (("__fn_stub_", fnname, NULL));
6466 /* Build a decl for the stub. */
6467 stubdecl = build_decl (BUILTINS_LOCATION,
6468 FUNCTION_DECL, get_identifier (stubname),
6469 build_function_type_list (void_type_node, NULL_TREE));
6470 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
6471 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
6472 RESULT_DECL, NULL_TREE, void_type_node);
6474 /* Output a comment. */
6475 fprintf (asm_out_file, "\t# Stub function for %s (",
6476 current_function_name ());
6478 for (f = (unsigned int) crtl->args.info.fp_code; f != 0; f >>= 2)
6480 fprintf (asm_out_file, "%s%s", separator,
6481 (f & 3) == 1 ? "float" : "double");
6484 fprintf (asm_out_file, ")\n");
6486 /* Start the function definition. */
6487 assemble_start_function (stubdecl, stubname);
6488 mips_start_function_definition (stubname, false);
6490 /* If generating pic2 code, either set up the global pointer or
6492 if (TARGET_ABICALLS_PIC2)
6494 if (TARGET_ABSOLUTE_ABICALLS)
6495 fprintf (asm_out_file, "\t.option\tpic0\n");
6498 output_asm_insn ("%(.cpload\t%^%)", NULL);
6499 /* Emit an R_MIPS_NONE relocation to tell the linker what the
6500 target function is. Use a local GOT access when loading the
6501 symbol, to cut down on the number of unnecessary GOT entries
6502 for stubs that aren't needed. */
6503 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol);
6508 /* Load the address of the MIPS16 function into $25. Do this first so
6509 that targets with coprocessor interlocks can use an MFC1 to fill the
6511 output_asm_insn ("la\t%^,%0", &symbol);
6513 /* Move the arguments from floating-point registers to general registers. */
6514 mips_output_args_xfer (crtl->args.info.fp_code, 'f');
6516 /* Jump to the MIPS16 function. */
6517 output_asm_insn ("jr\t%^", NULL);
6519 if (TARGET_ABICALLS_PIC2 && TARGET_ABSOLUTE_ABICALLS)
6520 fprintf (asm_out_file, "\t.option\tpic2\n");
6522 mips_end_function_definition (stubname);
6524 /* If the linker needs to create a dynamic symbol for the target
6525 function, it will associate the symbol with the stub (which,
6526 unlike the target function, follows the proper calling conventions).
6527 It is therefore useful to have a local alias for the target function,
6528 so that it can still be identified as MIPS16 code. As an optimization,
6529 this symbol can also be used for indirect MIPS16 references from
6530 within this file. */
6531 ASM_OUTPUT_DEF (asm_out_file, alias_name, fnname);
6533 switch_to_section (function_section (current_function_decl));
6536 /* The current function is a MIPS16 function that returns a value in an FPR.
6537 Copy the return value from its soft-float to its hard-float location.
6538 libgcc2 has special non-MIPS16 helper functions for each case. */
6541 mips16_copy_fpr_return_value (void)
6543 rtx fn, insn, retval;
6545 enum machine_mode return_mode;
6548 return_type = DECL_RESULT (current_function_decl);
6549 return_mode = DECL_MODE (return_type);
6551 name = ACONCAT (("__mips16_ret_",
6552 mips16_call_stub_mode_suffix (return_mode),
6554 fn = mips16_stub_function (name);
6556 /* The function takes arguments in $2 (and possibly $3), so calls
6557 to it cannot be lazily bound. */
6558 SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_BIND_NOW;
6560 /* Model the call as something that takes the GPR return value as
6561 argument and returns an "updated" value. */
6562 retval = gen_rtx_REG (return_mode, GP_RETURN);
6563 insn = mips_expand_call (MIPS_CALL_EPILOGUE, retval, fn,
6564 const0_rtx, NULL_RTX, false);
6565 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), retval);
6568 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
6569 RETVAL is the location of the return value, or null if this is
6570 a "call" rather than a "call_value". ARGS_SIZE is the size of the
6571 arguments and FP_CODE is the code built by mips_function_arg;
6572 see the comment before the fp_code field in CUMULATIVE_ARGS for details.
6574 There are three alternatives:
6576 - If a stub was needed, emit the call and return the call insn itself.
6578 - If we can avoid using a stub by redirecting the call, set *FN_PTR
6579 to the new target and return null.
6581 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
6584 A stub is needed for calls to functions that, in normal mode,
6585 receive arguments in FPRs or return values in FPRs. The stub
6586 copies the arguments from their soft-float positions to their
6587 hard-float positions, calls the real function, then copies the
6588 return value from its hard-float position to its soft-float
6591 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
6592 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
6593 automatically redirects the JAL to the stub, otherwise the JAL
6594 continues to call FN directly. */
6597 mips16_build_call_stub (rtx retval, rtx *fn_ptr, rtx args_size, int fp_code)
6601 struct mips16_stub *l;
6604 /* We don't need to do anything if we aren't in MIPS16 mode, or if
6605 we were invoked with the -msoft-float option. */
6606 if (!TARGET_MIPS16 || TARGET_SOFT_FLOAT_ABI)
6609 /* Figure out whether the value might come back in a floating-point
6611 fp_ret_p = retval && mips_return_mode_in_fpr_p (GET_MODE (retval));
6613 /* We don't need to do anything if there were no floating-point
6614 arguments and the value will not be returned in a floating-point
6616 if (fp_code == 0 && !fp_ret_p)
6619 /* We don't need to do anything if this is a call to a special
6620 MIPS16 support function. */
6622 if (mips16_stub_function_p (fn))
6625 /* If we're calling a locally-defined MIPS16 function, we know that
6626 it will return values in both the "soft-float" and "hard-float"
6627 registers. There is no need to use a stub to move the latter
6629 if (fp_code == 0 && mips16_local_function_p (fn))
6632 /* This code will only work for o32 and o64 abis. The other ABI's
6633 require more sophisticated support. */
6634 gcc_assert (TARGET_OLDABI);
6636 /* If we're calling via a function pointer, use one of the magic
6637 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
6638 Each stub expects the function address to arrive in register $2. */
6639 if (GET_CODE (fn) != SYMBOL_REF
6640 || !call_insn_operand (fn, VOIDmode))
6643 rtx stub_fn, insn, addr;
6646 /* If this is a locally-defined and locally-binding function,
6647 avoid the stub by calling the local alias directly. */
6648 if (mips16_local_function_p (fn))
6650 *fn_ptr = mips16_local_alias (fn);
6654 /* Create a SYMBOL_REF for the libgcc.a function. */
6656 sprintf (buf, "__mips16_call_stub_%s_%d",
6657 mips16_call_stub_mode_suffix (GET_MODE (retval)),
6660 sprintf (buf, "__mips16_call_stub_%d", fp_code);
6661 stub_fn = mips16_stub_function (buf);
6663 /* The function uses $2 as an argument, so calls to it
6664 cannot be lazily bound. */
6665 SYMBOL_REF_FLAGS (stub_fn) |= SYMBOL_FLAG_BIND_NOW;
6667 /* Load the target function into $2. */
6668 addr = gen_rtx_REG (Pmode, GP_REG_FIRST + 2);
6669 lazy_p = mips_load_call_address (MIPS_CALL_NORMAL, addr, fn);
6671 /* Emit the call. */
6672 insn = mips_expand_call (MIPS_CALL_NORMAL, retval, stub_fn,
6673 args_size, NULL_RTX, lazy_p);
6675 /* Tell GCC that this call does indeed use the value of $2. */
6676 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), addr);
6678 /* If we are handling a floating-point return value, we need to
6679 save $18 in the function prologue. Putting a note on the
6680 call will mean that df_regs_ever_live_p ($18) will be true if the
6681 call is not eliminated, and we can check that in the prologue
6684 CALL_INSN_FUNCTION_USAGE (insn) =
6685 gen_rtx_EXPR_LIST (VOIDmode,
6686 gen_rtx_CLOBBER (VOIDmode,
6687 gen_rtx_REG (word_mode, 18)),
6688 CALL_INSN_FUNCTION_USAGE (insn));
6693 /* We know the function we are going to call. If we have already
6694 built a stub, we don't need to do anything further. */
6695 fnname = targetm.strip_name_encoding (XSTR (fn, 0));
6696 for (l = mips16_stubs; l != NULL; l = l->next)
6697 if (strcmp (l->name, fnname) == 0)
6702 const char *separator;
6703 char *secname, *stubname;
6704 tree stubid, stubdecl;
6707 /* If the function does not return in FPRs, the special stub
6711 If the function does return in FPRs, the stub section is named
6712 .mips16.call.fp.FNNAME
6714 Build a decl for the stub. */
6715 secname = ACONCAT ((".mips16.call.", fp_ret_p ? "fp." : "",
6717 stubname = ACONCAT (("__call_stub_", fp_ret_p ? "fp_" : "",
6719 stubid = get_identifier (stubname);
6720 stubdecl = build_decl (BUILTINS_LOCATION,
6721 FUNCTION_DECL, stubid,
6722 build_function_type_list (void_type_node,
6724 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
6725 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
6726 RESULT_DECL, NULL_TREE,
6729 /* Output a comment. */
6730 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
6732 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
6736 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
6738 fprintf (asm_out_file, "%s%s", separator,
6739 (f & 3) == 1 ? "float" : "double");
6742 fprintf (asm_out_file, ")\n");
6744 /* Start the function definition. */
6745 assemble_start_function (stubdecl, stubname);
6746 mips_start_function_definition (stubname, false);
6750 fprintf (asm_out_file, "\t.cfi_startproc\n");
6752 /* Create a fake CFA 4 bytes below the stack pointer.
6753 This works around unwinders (like libgcc's) that expect
6754 the CFA for non-signal frames to be unique. */
6755 fprintf (asm_out_file, "\t.cfi_def_cfa 29,-4\n");
6757 /* "Save" $sp in itself so we don't use the fake CFA.
6758 This is: DW_CFA_val_expression r29, { DW_OP_reg29 }. */
6759 fprintf (asm_out_file, "\t.cfi_escape 0x16,29,1,0x6d\n");
6763 /* Load the address of the MIPS16 function into $25. Do this
6764 first so that targets with coprocessor interlocks can use
6765 an MFC1 to fill the delay slot. */
6766 if (TARGET_EXPLICIT_RELOCS)
6768 output_asm_insn ("lui\t%^,%%hi(%0)", &fn);
6769 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn);
6772 output_asm_insn ("la\t%^,%0", &fn);
6775 /* Move the arguments from general registers to floating-point
6777 mips_output_args_xfer (fp_code, 't');
6781 /* Save the return address in $18 and call the non-MIPS16 function.
6782 The stub's caller knows that $18 might be clobbered, even though
6783 $18 is usually a call-saved register. */
6784 fprintf (asm_out_file, "\tmove\t%s,%s\n",
6785 reg_names[GP_REG_FIRST + 18], reg_names[RETURN_ADDR_REGNUM]);
6786 output_asm_insn (MIPS_CALL ("jal", &fn, 0, -1), &fn);
6787 fprintf (asm_out_file, "\t.cfi_register 31,18\n");
6789 /* Move the result from floating-point registers to
6790 general registers. */
6791 switch (GET_MODE (retval))
6794 mips_output_32bit_xfer ('f', GP_RETURN + TARGET_BIG_ENDIAN,
6796 ? FP_REG_FIRST + MAX_FPRS_PER_FMT
6798 mips_output_32bit_xfer ('f', GP_RETURN + TARGET_LITTLE_ENDIAN,
6799 TARGET_LITTLE_ENDIAN
6800 ? FP_REG_FIRST + MAX_FPRS_PER_FMT
6802 if (GET_MODE (retval) == SCmode && TARGET_64BIT)
6804 /* On 64-bit targets, complex floats are returned in
6805 a single GPR, such that "sd" on a suitably-aligned
6806 target would store the value correctly. */
6807 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
6808 reg_names[GP_RETURN + TARGET_BIG_ENDIAN],
6809 reg_names[GP_RETURN + TARGET_BIG_ENDIAN]);
6810 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
6811 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN],
6812 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN]);
6813 fprintf (asm_out_file, "\tdsrl\t%s,%s,32\n",
6814 reg_names[GP_RETURN + TARGET_BIG_ENDIAN],
6815 reg_names[GP_RETURN + TARGET_BIG_ENDIAN]);
6816 fprintf (asm_out_file, "\tor\t%s,%s,%s\n",
6817 reg_names[GP_RETURN],
6818 reg_names[GP_RETURN],
6819 reg_names[GP_RETURN + 1]);
6824 mips_output_32bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6828 mips_output_64bit_xfer ('f', GP_RETURN + (8 / UNITS_PER_WORD),
6829 FP_REG_FIRST + MAX_FPRS_PER_FMT);
6833 mips_output_64bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6839 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 18]);
6840 fprintf (asm_out_file, "\t.cfi_endproc\n");
6844 /* Jump to the previously-loaded address. */
6845 output_asm_insn ("jr\t%^", NULL);
6848 #ifdef ASM_DECLARE_FUNCTION_SIZE
6849 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
6852 mips_end_function_definition (stubname);
6854 /* Record this stub. */
6855 l = XNEW (struct mips16_stub);
6856 l->name = xstrdup (fnname);
6857 l->fp_ret_p = fp_ret_p;
6858 l->next = mips16_stubs;
6862 /* If we expect a floating-point return value, but we've built a
6863 stub which does not expect one, then we're in trouble. We can't
6864 use the existing stub, because it won't handle the floating-point
6865 value. We can't build a new stub, because the linker won't know
6866 which stub to use for the various calls in this object file.
6867 Fortunately, this case is illegal, since it means that a function
6868 was declared in two different ways in a single compilation. */
6869 if (fp_ret_p && !l->fp_ret_p)
6870 error ("cannot handle inconsistent calls to %qs", fnname);
6872 if (retval == NULL_RTX)
6873 insn = gen_call_internal_direct (fn, args_size);
6875 insn = gen_call_value_internal_direct (retval, fn, args_size);
6876 insn = mips_emit_call_insn (insn, fn, fn, false);
6878 /* If we are calling a stub which handles a floating-point return
6879 value, we need to arrange to save $18 in the prologue. We do this
6880 by marking the function call as using the register. The prologue
6881 will later see that it is used, and emit code to save it. */
6883 CALL_INSN_FUNCTION_USAGE (insn) =
6884 gen_rtx_EXPR_LIST (VOIDmode,
6885 gen_rtx_CLOBBER (VOIDmode,
6886 gen_rtx_REG (word_mode, 18)),
6887 CALL_INSN_FUNCTION_USAGE (insn));
6892 /* Expand a call of type TYPE. RESULT is where the result will go (null
6893 for "call"s and "sibcall"s), ADDR is the address of the function,
6894 ARGS_SIZE is the size of the arguments and AUX is the value passed
6895 to us by mips_function_arg. LAZY_P is true if this call already
6896 involves a lazily-bound function address (such as when calling
6897 functions through a MIPS16 hard-float stub).
6899 Return the call itself. */
6902 mips_expand_call (enum mips_call_type type, rtx result, rtx addr,
6903 rtx args_size, rtx aux, bool lazy_p)
6905 rtx orig_addr, pattern, insn;
6908 fp_code = aux == 0 ? 0 : (int) GET_MODE (aux);
6909 insn = mips16_build_call_stub (result, &addr, args_size, fp_code);
6912 gcc_assert (!lazy_p && type == MIPS_CALL_NORMAL);
6917 if (!call_insn_operand (addr, VOIDmode))
6919 if (type == MIPS_CALL_EPILOGUE)
6920 addr = MIPS_EPILOGUE_TEMP (Pmode);
6922 addr = gen_reg_rtx (Pmode);
6923 lazy_p |= mips_load_call_address (type, addr, orig_addr);
6928 rtx (*fn) (rtx, rtx);
6930 if (type == MIPS_CALL_SIBCALL)
6931 fn = gen_sibcall_internal;
6933 fn = gen_call_internal;
6935 pattern = fn (addr, args_size);
6937 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
6939 /* Handle return values created by mips_return_fpr_pair. */
6940 rtx (*fn) (rtx, rtx, rtx, rtx);
6943 if (type == MIPS_CALL_SIBCALL)
6944 fn = gen_sibcall_value_multiple_internal;
6946 fn = gen_call_value_multiple_internal;
6948 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
6949 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
6950 pattern = fn (reg1, addr, args_size, reg2);
6954 rtx (*fn) (rtx, rtx, rtx);
6956 if (type == MIPS_CALL_SIBCALL)
6957 fn = gen_sibcall_value_internal;
6959 fn = gen_call_value_internal;
6961 /* Handle return values created by mips_return_fpr_single. */
6962 if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 1)
6963 result = XEXP (XVECEXP (result, 0, 0), 0);
6964 pattern = fn (result, addr, args_size);
6967 return mips_emit_call_insn (pattern, orig_addr, addr, lazy_p);
6970 /* Split call instruction INSN into a $gp-clobbering call and
6971 (where necessary) an instruction to restore $gp from its save slot.
6972 CALL_PATTERN is the pattern of the new call. */
6975 mips_split_call (rtx insn, rtx call_pattern)
6977 emit_call_insn (call_pattern);
6978 if (!find_reg_note (insn, REG_NORETURN, 0))
6979 /* Pick a temporary register that is suitable for both MIPS16 and
6980 non-MIPS16 code. $4 and $5 are used for returning complex double
6981 values in soft-float code, so $6 is the first suitable candidate. */
6982 mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode, GP_ARG_FIRST + 2));
6985 /* Return true if a call to DECL may need to use JALX. */
6988 mips_call_may_need_jalx_p (tree decl)
6990 /* If the current translation unit would use a different mode for DECL,
6991 assume that the call needs JALX. */
6992 if (mips_get_compress_mode (decl) != TARGET_COMPRESSION)
6995 /* mips_get_compress_mode is always accurate for locally-binding
6996 functions in the current translation unit. */
6997 if (!DECL_EXTERNAL (decl) && targetm.binds_local_p (decl))
7000 /* When -minterlink-compressed is in effect, assume that functions
7001 could use a different encoding mode unless an attribute explicitly
7002 tells us otherwise. */
7003 if (TARGET_INTERLINK_COMPRESSED)
7005 if (!TARGET_COMPRESSION
7006 && mips_get_compress_off_flags (DECL_ATTRIBUTES (decl)) ==0)
7008 if (TARGET_COMPRESSION
7009 && mips_get_compress_on_flags (DECL_ATTRIBUTES (decl)) == 0)
7016 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
7019 mips_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
7021 if (!TARGET_SIBCALLS)
7024 /* Interrupt handlers need special epilogue code and therefore can't
7026 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
7029 /* Direct Js are only possible to functions that use the same ISA encoding.
7030 There is no JX counterpoart of JALX. */
7032 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode)
7033 && mips_call_may_need_jalx_p (decl))
7036 /* Sibling calls should not prevent lazy binding. Lazy-binding stubs
7037 require $gp to be valid on entry, so sibcalls can only use stubs
7038 if $gp is call-clobbered. */
7040 && TARGET_CALL_SAVED_GP
7041 && !TARGET_ABICALLS_PIC0
7042 && !targetm.binds_local_p (decl))
7049 /* Emit code to move general operand SRC into condition-code
7050 register DEST given that SCRATCH is a scratch TFmode FPR.
7057 where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */
7060 mips_expand_fcc_reload (rtx dest, rtx src, rtx scratch)
7064 /* Change the source to SFmode. */
7066 src = adjust_address (src, SFmode, 0);
7067 else if (REG_P (src) || GET_CODE (src) == SUBREG)
7068 src = gen_rtx_REG (SFmode, true_regnum (src));
7070 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
7071 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + MAX_FPRS_PER_FMT);
7073 mips_emit_move (copy_rtx (fp1), src);
7074 mips_emit_move (copy_rtx (fp2), CONST0_RTX (SFmode));
7075 emit_insn (gen_slt_sf (dest, fp2, fp1));
7078 /* Implement MOVE_BY_PIECES_P. */
7081 mips_move_by_pieces_p (unsigned HOST_WIDE_INT size, unsigned int align)
7085 /* movmemsi is meant to generate code that is at least as good as
7086 move_by_pieces. However, movmemsi effectively uses a by-pieces
7087 implementation both for moves smaller than a word and for
7088 word-aligned moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT
7089 bytes. We should allow the tree-level optimisers to do such
7090 moves by pieces, as it often exposes other optimization
7091 opportunities. We might as well continue to use movmemsi at
7092 the rtl level though, as it produces better code when
7093 scheduling is disabled (such as at -O). */
7094 if (currently_expanding_to_rtl)
7096 if (align < BITS_PER_WORD)
7097 return size < UNITS_PER_WORD;
7098 return size <= MIPS_MAX_MOVE_BYTES_STRAIGHT;
7100 /* The default value. If this becomes a target hook, we should
7101 call the default definition instead. */
7102 return (move_by_pieces_ninsns (size, align, MOVE_MAX_PIECES + 1)
7103 < (unsigned int) MOVE_RATIO (optimize_insn_for_speed_p ()));
7106 /* Implement STORE_BY_PIECES_P. */
7109 mips_store_by_pieces_p (unsigned HOST_WIDE_INT size, unsigned int align)
7111 /* Storing by pieces involves moving constants into registers
7112 of size MIN (ALIGN, BITS_PER_WORD), then storing them.
7113 We need to decide whether it is cheaper to load the address of
7114 constant data into a register and use a block move instead. */
7116 /* If the data is only byte aligned, then:
7118 (a1) A block move of less than 4 bytes would involve three 3 LBs and
7119 3 SBs. We might as well use 3 single-instruction LIs and 3 SBs
7122 (a2) A block move of 4 bytes from aligned source data can use an
7123 LW/SWL/SWR sequence. This is often better than the 4 LIs and
7124 4 SBs that we would generate when storing by pieces. */
7125 if (align <= BITS_PER_UNIT)
7128 /* If the data is 2-byte aligned, then:
7130 (b1) A block move of less than 4 bytes would use a combination of LBs,
7131 LHs, SBs and SHs. We get better code by using single-instruction
7132 LIs, SBs and SHs instead.
7134 (b2) A block move of 4 bytes from aligned source data would again use
7135 an LW/SWL/SWR sequence. In most cases, loading the address of
7136 the source data would require at least one extra instruction.
7137 It is often more efficient to use 2 single-instruction LIs and
7140 (b3) A block move of up to 3 additional bytes would be like (b1).
7142 (b4) A block move of 8 bytes from aligned source data can use two
7143 LW/SWL/SWR sequences or a single LD/SDL/SDR sequence. Both
7144 sequences are better than the 4 LIs and 4 SHs that we'd generate
7145 when storing by pieces.
7147 The reasoning for higher alignments is similar:
7149 (c1) A block move of less than 4 bytes would be the same as (b1).
7151 (c2) A block move of 4 bytes would use an LW/SW sequence. Again,
7152 loading the address of the source data would typically require
7153 at least one extra instruction. It is generally better to use
7156 (c3) A block move of up to 3 additional bytes would be like (b1).
7158 (c4) A block move of 8 bytes can use two LW/SW sequences or a single
7159 LD/SD sequence, and in these cases we've traditionally preferred
7160 the memory copy over the more bulky constant moves. */
7164 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
7165 Assume that the areas do not overlap. */
7168 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
7170 HOST_WIDE_INT offset, delta;
7171 unsigned HOST_WIDE_INT bits;
7173 enum machine_mode mode;
7176 /* Work out how many bits to move at a time. If both operands have
7177 half-word alignment, it is usually better to move in half words.
7178 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
7179 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
7180 Otherwise move word-sized chunks. */
7181 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
7182 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
7183 bits = BITS_PER_WORD / 2;
7185 bits = BITS_PER_WORD;
7187 mode = mode_for_size (bits, MODE_INT, 0);
7188 delta = bits / BITS_PER_UNIT;
7190 /* Allocate a buffer for the temporary registers. */
7191 regs = XALLOCAVEC (rtx, length / delta);
7193 /* Load as many BITS-sized chunks as possible. Use a normal load if
7194 the source has enough alignment, otherwise use left/right pairs. */
7195 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
7197 regs[i] = gen_reg_rtx (mode);
7198 if (MEM_ALIGN (src) >= bits)
7199 mips_emit_move (regs[i], adjust_address (src, mode, offset));
7202 rtx part = adjust_address (src, BLKmode, offset);
7203 set_mem_size (part, delta);
7204 if (!mips_expand_ext_as_unaligned_load (regs[i], part, bits, 0, 0))
7209 /* Copy the chunks to the destination. */
7210 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
7211 if (MEM_ALIGN (dest) >= bits)
7212 mips_emit_move (adjust_address (dest, mode, offset), regs[i]);
7215 rtx part = adjust_address (dest, BLKmode, offset);
7216 set_mem_size (part, delta);
7217 if (!mips_expand_ins_as_unaligned_store (part, regs[i], bits, 0))
7221 /* Mop up any left-over bytes. */
7222 if (offset < length)
7224 src = adjust_address (src, BLKmode, offset);
7225 dest = adjust_address (dest, BLKmode, offset);
7226 move_by_pieces (dest, src, length - offset,
7227 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
7231 /* Helper function for doing a loop-based block operation on memory
7232 reference MEM. Each iteration of the loop will operate on LENGTH
7235 Create a new base register for use within the loop and point it to
7236 the start of MEM. Create a new memory reference that uses this
7237 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
7240 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
7241 rtx *loop_reg, rtx *loop_mem)
7243 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
7245 /* Although the new mem does not refer to a known location,
7246 it does keep up to LENGTH bytes of alignment. */
7247 *loop_mem = change_address (mem, BLKmode, *loop_reg);
7248 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
7251 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
7252 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
7253 the memory regions do not overlap. */
7256 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length,
7257 HOST_WIDE_INT bytes_per_iter)
7259 rtx label, src_reg, dest_reg, final_src, test;
7260 HOST_WIDE_INT leftover;
7262 leftover = length % bytes_per_iter;
7265 /* Create registers and memory references for use within the loop. */
7266 mips_adjust_block_mem (src, bytes_per_iter, &src_reg, &src);
7267 mips_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest);
7269 /* Calculate the value that SRC_REG should have after the last iteration
7271 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
7274 /* Emit the start of the loop. */
7275 label = gen_label_rtx ();
7278 /* Emit the loop body. */
7279 mips_block_move_straight (dest, src, bytes_per_iter);
7281 /* Move on to the next block. */
7282 mips_emit_move (src_reg, plus_constant (Pmode, src_reg, bytes_per_iter));
7283 mips_emit_move (dest_reg, plus_constant (Pmode, dest_reg, bytes_per_iter));
7285 /* Emit the loop condition. */
7286 test = gen_rtx_NE (VOIDmode, src_reg, final_src);
7287 if (Pmode == DImode)
7288 emit_jump_insn (gen_cbranchdi4 (test, src_reg, final_src, label));
7290 emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label));
7292 /* Mop up any left-over bytes. */
7294 mips_block_move_straight (dest, src, leftover);
7297 /* Expand a movmemsi instruction, which copies LENGTH bytes from
7298 memory reference SRC to memory reference DEST. */
7301 mips_expand_block_move (rtx dest, rtx src, rtx length)
7303 if (CONST_INT_P (length))
7305 if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)
7307 mips_block_move_straight (dest, src, INTVAL (length));
7312 mips_block_move_loop (dest, src, INTVAL (length),
7313 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER);
7320 /* Expand a loop of synci insns for the address range [BEGIN, END). */
7323 mips_expand_synci_loop (rtx begin, rtx end)
7325 rtx inc, label, end_label, cmp_result, mask, length;
7327 /* Create end_label. */
7328 end_label = gen_label_rtx ();
7330 /* Check if begin equals end. */
7331 cmp_result = gen_rtx_EQ (VOIDmode, begin, end);
7332 emit_jump_insn (gen_condjump (cmp_result, end_label));
7334 /* Load INC with the cache line size (rdhwr INC,$1). */
7335 inc = gen_reg_rtx (Pmode);
7336 emit_insn (PMODE_INSN (gen_rdhwr_synci_step, (inc)));
7338 /* Check if inc is 0. */
7339 cmp_result = gen_rtx_EQ (VOIDmode, inc, const0_rtx);
7340 emit_jump_insn (gen_condjump (cmp_result, end_label));
7342 /* Calculate mask. */
7343 mask = mips_force_unary (Pmode, NEG, inc);
7345 /* Mask out begin by mask. */
7346 begin = mips_force_binary (Pmode, AND, begin, mask);
7348 /* Calculate length. */
7349 length = mips_force_binary (Pmode, MINUS, end, begin);
7351 /* Loop back to here. */
7352 label = gen_label_rtx ();
7355 emit_insn (gen_synci (begin));
7357 /* Update length. */
7358 mips_emit_binary (MINUS, length, length, inc);
7361 mips_emit_binary (PLUS, begin, begin, inc);
7363 /* Check if length is greater than 0. */
7364 cmp_result = gen_rtx_GT (VOIDmode, length, const0_rtx);
7365 emit_jump_insn (gen_condjump (cmp_result, label));
7367 emit_label (end_label);
7370 /* Expand a QI or HI mode atomic memory operation.
7372 GENERATOR contains a pointer to the gen_* function that generates
7373 the SI mode underlying atomic operation using masks that we
7376 RESULT is the return register for the operation. Its value is NULL
7379 MEM is the location of the atomic access.
7381 OLDVAL is the first operand for the operation.
7383 NEWVAL is the optional second operand for the operation. Its value
7384 is NULL if unused. */
7387 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator,
7388 rtx result, rtx mem, rtx oldval, rtx newval)
7390 rtx orig_addr, memsi_addr, memsi, shift, shiftsi, unshifted_mask;
7391 rtx unshifted_mask_reg, mask, inverted_mask, si_op;
7393 enum machine_mode mode;
7395 mode = GET_MODE (mem);
7397 /* Compute the address of the containing SImode value. */
7398 orig_addr = force_reg (Pmode, XEXP (mem, 0));
7399 memsi_addr = mips_force_binary (Pmode, AND, orig_addr,
7400 force_reg (Pmode, GEN_INT (-4)));
7402 /* Create a memory reference for it. */
7403 memsi = gen_rtx_MEM (SImode, memsi_addr);
7404 set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER);
7405 MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem);
7407 /* Work out the byte offset of the QImode or HImode value,
7408 counting from the least significant byte. */
7409 shift = mips_force_binary (Pmode, AND, orig_addr, GEN_INT (3));
7410 if (TARGET_BIG_ENDIAN)
7411 mips_emit_binary (XOR, shift, shift, GEN_INT (mode == QImode ? 3 : 2));
7413 /* Multiply by eight to convert the shift value from bytes to bits. */
7414 mips_emit_binary (ASHIFT, shift, shift, GEN_INT (3));
7416 /* Make the final shift an SImode value, so that it can be used in
7417 SImode operations. */
7418 shiftsi = force_reg (SImode, gen_lowpart (SImode, shift));
7420 /* Set MASK to an inclusive mask of the QImode or HImode value. */
7421 unshifted_mask = GEN_INT (GET_MODE_MASK (mode));
7422 unshifted_mask_reg = force_reg (SImode, unshifted_mask);
7423 mask = mips_force_binary (SImode, ASHIFT, unshifted_mask_reg, shiftsi);
7425 /* Compute the equivalent exclusive mask. */
7426 inverted_mask = gen_reg_rtx (SImode);
7427 emit_insn (gen_rtx_SET (VOIDmode, inverted_mask,
7428 gen_rtx_NOT (SImode, mask)));
7430 /* Shift the old value into place. */
7431 if (oldval != const0_rtx)
7433 oldval = convert_modes (SImode, mode, oldval, true);
7434 oldval = force_reg (SImode, oldval);
7435 oldval = mips_force_binary (SImode, ASHIFT, oldval, shiftsi);
7438 /* Do the same for the new value. */
7439 if (newval && newval != const0_rtx)
7441 newval = convert_modes (SImode, mode, newval, true);
7442 newval = force_reg (SImode, newval);
7443 newval = mips_force_binary (SImode, ASHIFT, newval, shiftsi);
7446 /* Do the SImode atomic access. */
7448 res = gen_reg_rtx (SImode);
7450 si_op = generator.fn_6 (res, memsi, mask, inverted_mask, oldval, newval);
7452 si_op = generator.fn_5 (res, memsi, mask, inverted_mask, oldval);
7454 si_op = generator.fn_4 (memsi, mask, inverted_mask, oldval);
7460 /* Shift and convert the result. */
7461 mips_emit_binary (AND, res, res, mask);
7462 mips_emit_binary (LSHIFTRT, res, res, shiftsi);
7463 mips_emit_move (result, gen_lowpart (GET_MODE (result), res));
7467 /* Return true if it is possible to use left/right accesses for a
7468 bitfield of WIDTH bits starting BITPOS bits into BLKmode memory OP.
7469 When returning true, update *LEFT and *RIGHT as follows:
7471 *LEFT is a QImode reference to the first byte if big endian or
7472 the last byte if little endian. This address can be used in the
7473 left-side instructions (LWL, SWL, LDL, SDL).
7475 *RIGHT is a QImode reference to the opposite end of the field and
7476 can be used in the patterning right-side instruction. */
7479 mips_get_unaligned_mem (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos,
7480 rtx *left, rtx *right)
7484 /* Check that the size is valid. */
7485 if (width != 32 && (!TARGET_64BIT || width != 64))
7488 /* We can only access byte-aligned values. Since we are always passed
7489 a reference to the first byte of the field, it is not necessary to
7490 do anything with BITPOS after this check. */
7491 if (bitpos % BITS_PER_UNIT != 0)
7494 /* Reject aligned bitfields: we want to use a normal load or store
7495 instead of a left/right pair. */
7496 if (MEM_ALIGN (op) >= width)
7499 /* Get references to both ends of the field. */
7500 first = adjust_address (op, QImode, 0);
7501 last = adjust_address (op, QImode, width / BITS_PER_UNIT - 1);
7503 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
7504 correspond to the MSB and RIGHT to the LSB. */
7505 if (TARGET_BIG_ENDIAN)
7506 *left = first, *right = last;
7508 *left = last, *right = first;
7513 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
7514 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
7515 the operation is the equivalent of:
7517 (set DEST (*_extract SRC WIDTH BITPOS))
7519 Return true on success. */
7522 mips_expand_ext_as_unaligned_load (rtx dest, rtx src, HOST_WIDE_INT width,
7523 HOST_WIDE_INT bitpos, bool unsigned_p)
7525 rtx left, right, temp;
7526 rtx dest1 = NULL_RTX;
7528 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
7529 be a DImode, create a new temp and emit a zero extend at the end. */
7530 if (GET_MODE (dest) == DImode
7532 && GET_MODE_BITSIZE (SImode) == width)
7535 dest = gen_reg_rtx (SImode);
7538 if (!mips_get_unaligned_mem (src, width, bitpos, &left, &right))
7541 temp = gen_reg_rtx (GET_MODE (dest));
7542 if (GET_MODE (dest) == DImode)
7544 emit_insn (gen_mov_ldl (temp, src, left));
7545 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
7549 emit_insn (gen_mov_lwl (temp, src, left));
7550 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
7553 /* If we were loading 32bits and the original register was DI then
7554 sign/zero extend into the orignal dest. */
7558 emit_insn (gen_zero_extendsidi2 (dest1, dest));
7560 emit_insn (gen_extendsidi2 (dest1, dest));
7565 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
7566 BITPOS and SRC are the operands passed to the expander; the operation
7567 is the equivalent of:
7569 (set (zero_extract DEST WIDTH BITPOS) SRC)
7571 Return true on success. */
7574 mips_expand_ins_as_unaligned_store (rtx dest, rtx src, HOST_WIDE_INT width,
7575 HOST_WIDE_INT bitpos)
7578 enum machine_mode mode;
7580 if (!mips_get_unaligned_mem (dest, width, bitpos, &left, &right))
7583 mode = mode_for_size (width, MODE_INT, 0);
7584 src = gen_lowpart (mode, src);
7587 emit_insn (gen_mov_sdl (dest, src, left));
7588 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
7592 emit_insn (gen_mov_swl (dest, src, left));
7593 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
7598 /* Return true if X is a MEM with the same size as MODE. */
7601 mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
7604 && MEM_SIZE_KNOWN_P (x)
7605 && MEM_SIZE (x) == GET_MODE_SIZE (mode));
7608 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
7609 source of an "ext" instruction or the destination of an "ins"
7610 instruction. OP must be a register operand and the following
7611 conditions must hold:
7613 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
7614 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7615 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7617 Also reject lengths equal to a word as they are better handled
7618 by the move patterns. */
7621 mips_use_ins_ext_p (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos)
7623 if (!ISA_HAS_EXT_INS
7624 || !register_operand (op, VOIDmode)
7625 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
7628 if (!IN_RANGE (width, 1, GET_MODE_BITSIZE (GET_MODE (op)) - 1))
7631 if (bitpos < 0 || bitpos + width > GET_MODE_BITSIZE (GET_MODE (op)))
7637 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
7638 operation if MAXLEN is the maxium length of consecutive bits that
7639 can make up MASK. MODE is the mode of the operation. See
7640 mask_low_and_shift_len for the actual definition. */
7643 mask_low_and_shift_p (enum machine_mode mode, rtx mask, rtx shift, int maxlen)
7645 return IN_RANGE (mask_low_and_shift_len (mode, mask, shift), 1, maxlen);
7648 /* Return true iff OP1 and OP2 are valid operands together for the
7649 *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider,
7650 see the table in the comment before the pattern. */
7653 and_operands_ok (enum machine_mode mode, rtx op1, rtx op2)
7655 return (memory_operand (op1, mode)
7656 ? and_load_operand (op2, mode)
7657 : and_reg_operand (op2, mode));
7660 /* The canonical form of a mask-low-and-shift-left operation is
7661 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
7662 cleared. Thus we need to shift MASK to the right before checking if it
7663 is a valid mask value. MODE is the mode of the operation. If true
7664 return the length of the mask, otherwise return -1. */
7667 mask_low_and_shift_len (enum machine_mode mode, rtx mask, rtx shift)
7669 HOST_WIDE_INT shval;
7671 shval = INTVAL (shift) & (GET_MODE_BITSIZE (mode) - 1);
7672 return exact_log2 ((UINTVAL (mask) >> shval) + 1);
7675 /* Return true if -msplit-addresses is selected and should be honored.
7677 -msplit-addresses is a half-way house between explicit relocations
7678 and the traditional assembler macros. It can split absolute 32-bit
7679 symbolic constants into a high/lo_sum pair but uses macros for other
7682 Like explicit relocation support for REL targets, it relies
7683 on GNU extensions in the assembler and the linker.
7685 Although this code should work for -O0, it has traditionally
7686 been treated as an optimization. */
7689 mips_split_addresses_p (void)
7691 return (TARGET_SPLIT_ADDRESSES
7695 && !ABI_HAS_64BIT_SYMBOLS);
7698 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
7701 mips_init_relocs (void)
7703 memset (mips_split_p, '\0', sizeof (mips_split_p));
7704 memset (mips_split_hi_p, '\0', sizeof (mips_split_hi_p));
7705 memset (mips_use_pcrel_pool_p, '\0', sizeof (mips_use_pcrel_pool_p));
7706 memset (mips_hi_relocs, '\0', sizeof (mips_hi_relocs));
7707 memset (mips_lo_relocs, '\0', sizeof (mips_lo_relocs));
7709 if (TARGET_MIPS16_PCREL_LOADS)
7710 mips_use_pcrel_pool_p[SYMBOL_ABSOLUTE] = true;
7713 if (ABI_HAS_64BIT_SYMBOLS)
7715 if (TARGET_EXPLICIT_RELOCS)
7717 mips_split_p[SYMBOL_64_HIGH] = true;
7718 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
7719 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
7721 mips_split_p[SYMBOL_64_MID] = true;
7722 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
7723 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
7725 mips_split_p[SYMBOL_64_LOW] = true;
7726 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
7727 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
7729 mips_split_p[SYMBOL_ABSOLUTE] = true;
7730 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
7735 if (TARGET_EXPLICIT_RELOCS
7736 || mips_split_addresses_p ()
7739 mips_split_p[SYMBOL_ABSOLUTE] = true;
7740 mips_hi_relocs[SYMBOL_ABSOLUTE] = "%hi(";
7741 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
7748 /* The high part is provided by a pseudo copy of $gp. */
7749 mips_split_p[SYMBOL_GP_RELATIVE] = true;
7750 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gprel(";
7752 else if (TARGET_EXPLICIT_RELOCS)
7753 /* Small data constants are kept whole until after reload,
7754 then lowered by mips_rewrite_small_data. */
7755 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gp_rel(";
7757 if (TARGET_EXPLICIT_RELOCS)
7759 mips_split_p[SYMBOL_GOT_PAGE_OFST] = true;
7762 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
7763 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%got_ofst(";
7767 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
7768 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%lo(";
7771 /* Expose the use of $28 as soon as possible. */
7772 mips_split_hi_p[SYMBOL_GOT_PAGE_OFST] = true;
7776 /* The HIGH and LO_SUM are matched by special .md patterns. */
7777 mips_split_p[SYMBOL_GOT_DISP] = true;
7779 mips_split_p[SYMBOL_GOTOFF_DISP] = true;
7780 mips_hi_relocs[SYMBOL_GOTOFF_DISP] = "%got_hi(";
7781 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_lo(";
7783 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
7784 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
7785 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
7790 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_disp(";
7792 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got(";
7793 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
7795 /* Expose the use of $28 as soon as possible. */
7796 mips_split_p[SYMBOL_GOT_DISP] = true;
7802 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
7803 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
7804 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
7807 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
7808 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
7810 if (TARGET_MIPS16_PCREL_LOADS)
7812 mips_use_pcrel_pool_p[SYMBOL_DTPREL] = true;
7813 mips_use_pcrel_pool_p[SYMBOL_TPREL] = true;
7817 mips_split_p[SYMBOL_DTPREL] = true;
7818 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
7819 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
7821 mips_split_p[SYMBOL_TPREL] = true;
7822 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
7823 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
7826 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
7827 mips_lo_relocs[SYMBOL_HALF] = "%half(";
7830 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
7831 in context CONTEXT. RELOCS is the array of relocations to use. */
7834 mips_print_operand_reloc (FILE *file, rtx op, enum mips_symbol_context context,
7835 const char **relocs)
7837 enum mips_symbol_type symbol_type;
7840 symbol_type = mips_classify_symbolic_expression (op, context);
7841 gcc_assert (relocs[symbol_type]);
7843 fputs (relocs[symbol_type], file);
7844 output_addr_const (file, mips_strip_unspec_address (op));
7845 for (p = relocs[symbol_type]; *p != 0; p++)
7850 /* Start a new block with the given asm switch enabled. If we need
7851 to print a directive, emit PREFIX before it and SUFFIX after it. */
7854 mips_push_asm_switch_1 (struct mips_asm_switch *asm_switch,
7855 const char *prefix, const char *suffix)
7857 if (asm_switch->nesting_level == 0)
7858 fprintf (asm_out_file, "%s.set\tno%s%s", prefix, asm_switch->name, suffix);
7859 asm_switch->nesting_level++;
7862 /* Likewise, but end a block. */
7865 mips_pop_asm_switch_1 (struct mips_asm_switch *asm_switch,
7866 const char *prefix, const char *suffix)
7868 gcc_assert (asm_switch->nesting_level);
7869 asm_switch->nesting_level--;
7870 if (asm_switch->nesting_level == 0)
7871 fprintf (asm_out_file, "%s.set\t%s%s", prefix, asm_switch->name, suffix);
7874 /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1
7875 that either print a complete line or print nothing. */
7878 mips_push_asm_switch (struct mips_asm_switch *asm_switch)
7880 mips_push_asm_switch_1 (asm_switch, "\t", "\n");
7884 mips_pop_asm_switch (struct mips_asm_switch *asm_switch)
7886 mips_pop_asm_switch_1 (asm_switch, "\t", "\n");
7889 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
7890 The punctuation characters are:
7892 '(' Start a nested ".set noreorder" block.
7893 ')' End a nested ".set noreorder" block.
7894 '[' Start a nested ".set noat" block.
7895 ']' End a nested ".set noat" block.
7896 '<' Start a nested ".set nomacro" block.
7897 '>' End a nested ".set nomacro" block.
7898 '*' Behave like %(%< if generating a delayed-branch sequence.
7899 '#' Print a nop if in a ".set noreorder" block.
7900 '/' Like '#', but do nothing within a delayed-branch sequence.
7901 '?' Print "l" if mips_branch_likely is true
7902 '~' Print a nop if mips_branch_likely is true
7903 '.' Print the name of the register with a hard-wired zero (zero or $0).
7904 '@' Print the name of the assembler temporary register (at or $1).
7905 '^' Print the name of the pic call-through register (t9 or $25).
7906 '+' Print the name of the gp register (usually gp or $28).
7907 '$' Print the name of the stack pointer register (sp or $29).
7908 ':' Print "c" to use the compact version if the delay slot is a nop.
7909 '!' Print "s" to use the short version if the delay slot contains a
7912 See also mips_init_print_operand_pucnt. */
7915 mips_print_operand_punctuation (FILE *file, int ch)
7920 mips_push_asm_switch_1 (&mips_noreorder, "", "\n\t");
7924 mips_pop_asm_switch_1 (&mips_noreorder, "\n\t", "");
7928 mips_push_asm_switch_1 (&mips_noat, "", "\n\t");
7932 mips_pop_asm_switch_1 (&mips_noat, "\n\t", "");
7936 mips_push_asm_switch_1 (&mips_nomacro, "", "\n\t");
7940 mips_pop_asm_switch_1 (&mips_nomacro, "\n\t", "");
7944 if (final_sequence != 0)
7946 mips_print_operand_punctuation (file, '(');
7947 mips_print_operand_punctuation (file, '<');
7952 if (mips_noreorder.nesting_level > 0)
7953 fputs ("\n\tnop", file);
7957 /* Print an extra newline so that the delayed insn is separated
7958 from the following ones. This looks neater and is consistent
7959 with non-nop delayed sequences. */
7960 if (mips_noreorder.nesting_level > 0 && final_sequence == 0)
7961 fputs ("\n\tnop\n", file);
7965 if (mips_branch_likely)
7970 if (mips_branch_likely)
7971 fputs ("\n\tnop", file);
7975 fputs (reg_names[GP_REG_FIRST + 0], file);
7979 fputs (reg_names[AT_REGNUM], file);
7983 fputs (reg_names[PIC_FUNCTION_ADDR_REGNUM], file);
7987 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
7991 fputs (reg_names[STACK_POINTER_REGNUM], file);
7995 /* When final_sequence is 0, the delay slot will be a nop. We can
7996 use the compact version for microMIPS. */
7997 if (final_sequence == 0)
8002 /* If the delay slot instruction is short, then use the
8004 if (final_sequence == 0
8005 || get_attr_length (XVECEXP (final_sequence, 0, 1)) == 2)
8015 /* Initialize mips_print_operand_punct. */
8018 mips_init_print_operand_punct (void)
8022 for (p = "()[]<>*#/?~.@^+$:!"; *p; p++)
8023 mips_print_operand_punct[(unsigned char) *p] = true;
8026 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
8027 associated with condition CODE. Print the condition part of the
8031 mips_print_int_branch_condition (FILE *file, enum rtx_code code, int letter)
8045 /* Conveniently, the MIPS names for these conditions are the same
8046 as their RTL equivalents. */
8047 fputs (GET_RTX_NAME (code), file);
8051 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
8056 /* Likewise floating-point branches. */
8059 mips_print_float_branch_condition (FILE *file, enum rtx_code code, int letter)
8064 fputs ("c1f", file);
8068 fputs ("c1t", file);
8072 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
8077 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
8080 mips_print_operand_punct_valid_p (unsigned char code)
8082 return mips_print_operand_punct[code];
8085 /* Implement TARGET_PRINT_OPERAND. The MIPS-specific operand codes are:
8087 'X' Print CONST_INT OP in hexadecimal format.
8088 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
8089 'd' Print CONST_INT OP in decimal.
8090 'm' Print one less than CONST_INT OP in decimal.
8091 'h' Print the high-part relocation associated with OP, after stripping
8093 'R' Print the low-part relocation associated with OP.
8094 'C' Print the integer branch condition for comparison OP.
8095 'N' Print the inverse of the integer branch condition for comparison OP.
8096 'F' Print the FPU branch condition for comparison OP.
8097 'W' Print the inverse of the FPU branch condition for comparison OP.
8098 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
8099 'z' for (eq:?I ...), 'n' for (ne:?I ...).
8100 't' Like 'T', but with the EQ/NE cases reversed
8101 'Y' Print mips_fp_conditions[INTVAL (OP)]
8102 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
8103 'q' Print a DSP accumulator register.
8104 'D' Print the second part of a double-word register or memory operand.
8105 'L' Print the low-order register in a double-word register operand.
8106 'M' Print high-order register in a double-word register operand.
8107 'z' Print $0 if OP is zero, otherwise print OP normally.
8108 'b' Print the address of a memory operand, without offset. */
8111 mips_print_operand (FILE *file, rtx op, int letter)
8115 if (mips_print_operand_punct_valid_p (letter))
8117 mips_print_operand_punctuation (file, letter);
8122 code = GET_CODE (op);
8127 if (CONST_INT_P (op))
8128 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
8130 output_operand_lossage ("invalid use of '%%%c'", letter);
8134 if (CONST_INT_P (op))
8135 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op) & 0xffff);
8137 output_operand_lossage ("invalid use of '%%%c'", letter);
8141 if (CONST_INT_P (op))
8142 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op));
8144 output_operand_lossage ("invalid use of '%%%c'", letter);
8148 if (CONST_INT_P (op))
8149 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op) - 1);
8151 output_operand_lossage ("invalid use of '%%%c'", letter);
8157 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_hi_relocs);
8161 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_lo_relocs);
8165 mips_print_int_branch_condition (file, code, letter);
8169 mips_print_int_branch_condition (file, reverse_condition (code), letter);
8173 mips_print_float_branch_condition (file, code, letter);
8177 mips_print_float_branch_condition (file, reverse_condition (code),
8184 int truth = (code == NE) == (letter == 'T');
8185 fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
8190 if (code == CONST_INT && UINTVAL (op) < ARRAY_SIZE (mips_fp_conditions))
8191 fputs (mips_fp_conditions[UINTVAL (op)], file);
8193 output_operand_lossage ("'%%%c' is not a valid operand prefix",
8200 mips_print_operand (file, op, 0);
8206 if (code == REG && MD_REG_P (REGNO (op)))
8207 fprintf (file, "$ac0");
8208 else if (code == REG && DSP_ACC_REG_P (REGNO (op)))
8209 fprintf (file, "$ac%c", reg_names[REGNO (op)][3]);
8211 output_operand_lossage ("invalid use of '%%%c'", letter);
8219 unsigned int regno = REGNO (op);
8220 if ((letter == 'M' && TARGET_LITTLE_ENDIAN)
8221 || (letter == 'L' && TARGET_BIG_ENDIAN)
8224 else if (letter && letter != 'z' && letter != 'M' && letter != 'L')
8225 output_operand_lossage ("invalid use of '%%%c'", letter);
8226 /* We need to print $0 .. $31 for COP0 registers. */
8227 if (COP0_REG_P (regno))
8228 fprintf (file, "$%s", ®_names[regno][4]);
8230 fprintf (file, "%s", reg_names[regno]);
8236 output_address (plus_constant (Pmode, XEXP (op, 0), 4));
8237 else if (letter == 'b')
8239 gcc_assert (REG_P (XEXP (op, 0)));
8240 mips_print_operand (file, XEXP (op, 0), 0);
8242 else if (letter && letter != 'z')
8243 output_operand_lossage ("invalid use of '%%%c'", letter);
8245 output_address (XEXP (op, 0));
8249 if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
8250 fputs (reg_names[GP_REG_FIRST], file);
8251 else if (letter && letter != 'z')
8252 output_operand_lossage ("invalid use of '%%%c'", letter);
8253 else if (CONST_GP_P (op))
8254 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
8256 output_addr_const (file, mips_strip_unspec_address (op));
8262 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
8265 mips_print_operand_address (FILE *file, rtx x)
8267 struct mips_address_info addr;
8269 if (mips_classify_address (&addr, x, word_mode, true))
8273 mips_print_operand (file, addr.offset, 0);
8274 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
8277 case ADDRESS_LO_SUM:
8278 mips_print_operand_reloc (file, addr.offset, SYMBOL_CONTEXT_MEM,
8280 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
8283 case ADDRESS_CONST_INT:
8284 output_addr_const (file, x);
8285 fprintf (file, "(%s)", reg_names[GP_REG_FIRST]);
8288 case ADDRESS_SYMBOLIC:
8289 output_addr_const (file, mips_strip_unspec_address (x));
8295 /* Implement TARGET_ENCODE_SECTION_INFO. */
8298 mips_encode_section_info (tree decl, rtx rtl, int first)
8300 default_encode_section_info (decl, rtl, first);
8302 if (TREE_CODE (decl) == FUNCTION_DECL)
8304 rtx symbol = XEXP (rtl, 0);
8305 tree type = TREE_TYPE (decl);
8307 /* Encode whether the symbol is short or long. */
8308 if ((TARGET_LONG_CALLS && !mips_near_type_p (type))
8309 || mips_far_type_p (type))
8310 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
8314 /* Implement TARGET_SELECT_RTX_SECTION. */
8317 mips_select_rtx_section (enum machine_mode mode, rtx x,
8318 unsigned HOST_WIDE_INT align)
8320 /* ??? Consider using mergeable small data sections. */
8321 if (mips_rtx_constant_in_small_data_p (mode))
8322 return get_named_section (NULL, ".sdata", 0);
8324 return default_elf_select_rtx_section (mode, x, align);
8327 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
8329 The complication here is that, with the combination TARGET_ABICALLS
8330 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
8331 absolute addresses, and should therefore not be included in the
8332 read-only part of a DSO. Handle such cases by selecting a normal
8333 data section instead of a read-only one. The logic apes that in
8334 default_function_rodata_section. */
8337 mips_function_rodata_section (tree decl)
8339 if (!TARGET_ABICALLS || TARGET_ABSOLUTE_ABICALLS || TARGET_GPWORD)
8340 return default_function_rodata_section (decl);
8342 if (decl && DECL_SECTION_NAME (decl))
8344 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
8345 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
8347 char *rname = ASTRDUP (name);
8349 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
8351 else if (flag_function_sections
8352 && flag_data_sections
8353 && strncmp (name, ".text.", 6) == 0)
8355 char *rname = ASTRDUP (name);
8356 memcpy (rname + 1, "data", 4);
8357 return get_section (rname, SECTION_WRITE, decl);
8360 return data_section;
8363 /* Implement TARGET_IN_SMALL_DATA_P. */
8366 mips_in_small_data_p (const_tree decl)
8368 unsigned HOST_WIDE_INT size;
8370 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
8373 /* We don't yet generate small-data references for -mabicalls
8374 or VxWorks RTP code. See the related -G handling in
8375 mips_option_override. */
8376 if (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
8379 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
8383 /* Reject anything that isn't in a known small-data section. */
8384 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
8385 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
8388 /* If a symbol is defined externally, the assembler will use the
8389 usual -G rules when deciding how to implement macros. */
8390 if (mips_lo_relocs[SYMBOL_GP_RELATIVE] || !DECL_EXTERNAL (decl))
8393 else if (TARGET_EMBEDDED_DATA)
8395 /* Don't put constants into the small data section: we want them
8396 to be in ROM rather than RAM. */
8397 if (TREE_CODE (decl) != VAR_DECL)
8400 if (TREE_READONLY (decl)
8401 && !TREE_SIDE_EFFECTS (decl)
8402 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
8406 /* Enforce -mlocal-sdata. */
8407 if (!TARGET_LOCAL_SDATA && !TREE_PUBLIC (decl))
8410 /* Enforce -mextern-sdata. */
8411 if (!TARGET_EXTERN_SDATA && DECL_P (decl))
8413 if (DECL_EXTERNAL (decl))
8415 if (DECL_COMMON (decl) && DECL_INITIAL (decl) == NULL)
8419 /* We have traditionally not treated zero-sized objects as small data,
8420 so this is now effectively part of the ABI. */
8421 size = int_size_in_bytes (TREE_TYPE (decl));
8422 return size > 0 && size <= mips_small_data_threshold;
8425 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
8426 anchors for small data: the GP register acts as an anchor in that
8427 case. We also don't want to use them for PC-relative accesses,
8428 where the PC acts as an anchor. */
8431 mips_use_anchors_for_symbol_p (const_rtx symbol)
8433 switch (mips_classify_symbol (symbol, SYMBOL_CONTEXT_MEM))
8435 case SYMBOL_PC_RELATIVE:
8436 case SYMBOL_GP_RELATIVE:
8440 return default_use_anchors_for_symbol_p (symbol);
8444 /* The MIPS debug format wants all automatic variables and arguments
8445 to be in terms of the virtual frame pointer (stack pointer before
8446 any adjustment in the function), while the MIPS 3.0 linker wants
8447 the frame pointer to be the stack pointer after the initial
8448 adjustment. So, we do the adjustment here. The arg pointer (which
8449 is eliminated) points to the virtual frame pointer, while the frame
8450 pointer (which may be eliminated) points to the stack pointer after
8451 the initial adjustments. */
8454 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
8456 rtx offset2 = const0_rtx;
8457 rtx reg = eliminate_constant_term (addr, &offset2);
8460 offset = INTVAL (offset2);
8462 if (reg == stack_pointer_rtx
8463 || reg == frame_pointer_rtx
8464 || reg == hard_frame_pointer_rtx)
8466 offset -= cfun->machine->frame.total_size;
8467 if (reg == hard_frame_pointer_rtx)
8468 offset += cfun->machine->frame.hard_frame_pointer_offset;
8474 /* Implement ASM_OUTPUT_EXTERNAL. */
8477 mips_output_external (FILE *file, tree decl, const char *name)
8479 default_elf_asm_output_external (file, decl, name);
8481 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
8482 set in order to avoid putting out names that are never really
8484 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
8486 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
8488 /* When using assembler macros, emit .extern directives for
8489 all small-data externs so that the assembler knows how
8492 In most cases it would be safe (though pointless) to emit
8493 .externs for other symbols too. One exception is when an
8494 object is within the -G limit but declared by the user to
8495 be in a section other than .sbss or .sdata. */
8496 fputs ("\t.extern\t", file);
8497 assemble_name (file, name);
8498 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n",
8499 int_size_in_bytes (TREE_TYPE (decl)));
8504 /* Implement TARGET_ASM_OUTPUT_SOURCE_FILENAME. */
8507 mips_output_filename (FILE *stream, const char *name)
8509 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
8511 if (write_symbols == DWARF2_DEBUG)
8513 else if (mips_output_filename_first_time)
8515 mips_output_filename_first_time = 0;
8516 num_source_filenames += 1;
8517 current_function_file = name;
8518 fprintf (stream, "\t.file\t%d ", num_source_filenames);
8519 output_quoted_string (stream, name);
8520 putc ('\n', stream);
8522 /* If we are emitting stabs, let dbxout.c handle this (except for
8523 the mips_output_filename_first_time case). */
8524 else if (write_symbols == DBX_DEBUG)
8526 else if (name != current_function_file
8527 && strcmp (name, current_function_file) != 0)
8529 num_source_filenames += 1;
8530 current_function_file = name;
8531 fprintf (stream, "\t.file\t%d ", num_source_filenames);
8532 output_quoted_string (stream, name);
8533 putc ('\n', stream);
8537 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
8539 static void ATTRIBUTE_UNUSED
8540 mips_output_dwarf_dtprel (FILE *file, int size, rtx x)
8545 fputs ("\t.dtprelword\t", file);
8549 fputs ("\t.dtpreldword\t", file);
8555 output_addr_const (file, x);
8556 fputs ("+0x8000", file);
8559 /* Implement TARGET_DWARF_REGISTER_SPAN. */
8562 mips_dwarf_register_span (rtx reg)
8565 enum machine_mode mode;
8567 /* By default, GCC maps increasing register numbers to increasing
8568 memory locations, but paired FPRs are always little-endian,
8569 regardless of the prevailing endianness. */
8570 mode = GET_MODE (reg);
8571 if (FP_REG_P (REGNO (reg))
8572 && TARGET_BIG_ENDIAN
8573 && MAX_FPRS_PER_FMT > 1
8574 && GET_MODE_SIZE (mode) > UNITS_PER_FPREG)
8576 gcc_assert (GET_MODE_SIZE (mode) == UNITS_PER_HWFPVALUE);
8577 high = mips_subword (reg, true);
8578 low = mips_subword (reg, false);
8579 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, high, low));
8585 /* DSP ALU can bypass data with no delays for the following pairs. */
8586 enum insn_code dspalu_bypass_table[][2] =
8588 {CODE_FOR_mips_addsc, CODE_FOR_mips_addwc},
8589 {CODE_FOR_mips_cmpu_eq_qb, CODE_FOR_mips_pick_qb},
8590 {CODE_FOR_mips_cmpu_lt_qb, CODE_FOR_mips_pick_qb},
8591 {CODE_FOR_mips_cmpu_le_qb, CODE_FOR_mips_pick_qb},
8592 {CODE_FOR_mips_cmp_eq_ph, CODE_FOR_mips_pick_ph},
8593 {CODE_FOR_mips_cmp_lt_ph, CODE_FOR_mips_pick_ph},
8594 {CODE_FOR_mips_cmp_le_ph, CODE_FOR_mips_pick_ph},
8595 {CODE_FOR_mips_wrdsp, CODE_FOR_mips_insv}
8599 mips_dspalu_bypass_p (rtx out_insn, rtx in_insn)
8602 int num_bypass = ARRAY_SIZE (dspalu_bypass_table);
8603 enum insn_code out_icode = (enum insn_code) INSN_CODE (out_insn);
8604 enum insn_code in_icode = (enum insn_code) INSN_CODE (in_insn);
8606 for (i = 0; i < num_bypass; i++)
8608 if (out_icode == dspalu_bypass_table[i][0]
8609 && in_icode == dspalu_bypass_table[i][1])
8615 /* Implement ASM_OUTPUT_ASCII. */
8618 mips_output_ascii (FILE *stream, const char *string, size_t len)
8624 fprintf (stream, "\t.ascii\t\"");
8625 for (i = 0; i < len; i++)
8629 c = (unsigned char) string[i];
8632 if (c == '\\' || c == '\"')
8634 putc ('\\', stream);
8642 fprintf (stream, "\\%03o", c);
8646 if (cur_pos > 72 && i+1 < len)
8649 fprintf (stream, "\"\n\t.ascii\t\"");
8652 fprintf (stream, "\"\n");
8655 /* Return the pseudo-op for full SYMBOL_(D)TPREL address *ADDR.
8656 Update *ADDR with the operand that should be printed. */
8659 mips_output_tls_reloc_directive (rtx *addr)
8661 enum mips_symbol_type type;
8663 type = mips_classify_symbolic_expression (*addr, SYMBOL_CONTEXT_LEA);
8664 *addr = mips_strip_unspec_address (*addr);
8668 return Pmode == SImode ? ".dtprelword\t%0" : ".dtpreldword\t%0";
8671 return Pmode == SImode ? ".tprelword\t%0" : ".tpreldword\t%0";
8678 /* Emit either a label, .comm, or .lcomm directive. When using assembler
8679 macros, mark the symbol as written so that mips_asm_output_external
8680 won't emit an .extern for it. STREAM is the output file, NAME is the
8681 name of the symbol, INIT_STRING is the string that should be written
8682 before the symbol and FINAL_STRING is the string that should be
8683 written after it. FINAL_STRING is a printf format that consumes the
8684 remaining arguments. */
8687 mips_declare_object (FILE *stream, const char *name, const char *init_string,
8688 const char *final_string, ...)
8692 fputs (init_string, stream);
8693 assemble_name (stream, name);
8694 va_start (ap, final_string);
8695 vfprintf (stream, final_string, ap);
8698 if (!TARGET_EXPLICIT_RELOCS)
8700 tree name_tree = get_identifier (name);
8701 TREE_ASM_WRITTEN (name_tree) = 1;
8705 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
8706 NAME is the name of the object and ALIGN is the required alignment
8707 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
8708 alignment argument. */
8711 mips_declare_common_object (FILE *stream, const char *name,
8712 const char *init_string,
8713 unsigned HOST_WIDE_INT size,
8714 unsigned int align, bool takes_alignment_p)
8716 if (!takes_alignment_p)
8718 size += (align / BITS_PER_UNIT) - 1;
8719 size -= size % (align / BITS_PER_UNIT);
8720 mips_declare_object (stream, name, init_string,
8721 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
8724 mips_declare_object (stream, name, init_string,
8725 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
8726 size, align / BITS_PER_UNIT);
8729 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
8730 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
8733 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
8734 unsigned HOST_WIDE_INT size,
8737 /* If the target wants uninitialized const declarations in
8738 .rdata then don't put them in .comm. */
8739 if (TARGET_EMBEDDED_DATA
8740 && TARGET_UNINIT_CONST_IN_RODATA
8741 && TREE_CODE (decl) == VAR_DECL
8742 && TREE_READONLY (decl)
8743 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
8745 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
8746 targetm.asm_out.globalize_label (stream, name);
8748 switch_to_section (readonly_data_section);
8749 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
8750 mips_declare_object (stream, name, "",
8751 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
8755 mips_declare_common_object (stream, name, "\n\t.comm\t",
8759 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8760 extern int size_directive_output;
8762 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
8763 definitions except that it uses mips_declare_object to emit the label. */
8766 mips_declare_object_name (FILE *stream, const char *name,
8767 tree decl ATTRIBUTE_UNUSED)
8769 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8770 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
8773 size_directive_output = 0;
8774 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
8778 size_directive_output = 1;
8779 size = int_size_in_bytes (TREE_TYPE (decl));
8780 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8783 mips_declare_object (stream, name, "", ":\n");
8786 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
8789 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
8793 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
8794 if (!flag_inhibit_size_directive
8795 && DECL_SIZE (decl) != 0
8798 && DECL_INITIAL (decl) == error_mark_node
8799 && !size_directive_output)
8803 size_directive_output = 1;
8804 size = int_size_in_bytes (TREE_TYPE (decl));
8805 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8810 /* Return the FOO in the name of the ".mdebug.FOO" section associated
8811 with the current ABI. */
8814 mips_mdebug_abi_name (void)
8827 return TARGET_64BIT ? "eabi64" : "eabi32";
8833 /* Implement TARGET_ASM_FILE_START. */
8836 mips_file_start (void)
8838 default_file_start ();
8840 /* Generate a special section to describe the ABI switches used to
8841 produce the resultant binary. */
8843 /* Record the ABI itself. Modern versions of binutils encode
8844 this information in the ELF header flags, but GDB needs the
8845 information in order to correctly debug binaries produced by
8846 older binutils. See the function mips_gdbarch_init in
8848 fprintf (asm_out_file, "\t.section .mdebug.%s\n\t.previous\n",
8849 mips_mdebug_abi_name ());
8851 /* There is no ELF header flag to distinguish long32 forms of the
8852 EABI from long64 forms. Emit a special section to help tools
8853 such as GDB. Do the same for o64, which is sometimes used with
8855 if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
8856 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n"
8857 "\t.previous\n", TARGET_LONG64 ? 64 : 32);
8859 /* Record the NaN encoding. */
8860 if (HAVE_AS_NAN || mips_nan != MIPS_IEEE_754_DEFAULT)
8861 fprintf (asm_out_file, "\t.nan\t%s\n",
8862 mips_nan == MIPS_IEEE_754_2008 ? "2008" : "legacy");
8864 #ifdef HAVE_AS_GNU_ATTRIBUTE
8868 /* No floating-point operations, -mno-float. */
8869 if (TARGET_NO_FLOAT)
8871 /* Soft-float code, -msoft-float. */
8872 else if (!TARGET_HARD_FLOAT_ABI)
8874 /* Single-float code, -msingle-float. */
8875 else if (!TARGET_DOUBLE_FLOAT)
8877 /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64. */
8878 else if (!TARGET_64BIT && TARGET_FLOAT64)
8880 /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */
8884 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n", attr);
8888 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
8889 if (TARGET_ABICALLS)
8891 fprintf (asm_out_file, "\t.abicalls\n");
8892 if (TARGET_ABICALLS_PIC0)
8893 fprintf (asm_out_file, "\t.option\tpic0\n");
8896 if (flag_verbose_asm)
8897 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
8899 mips_small_data_threshold, mips_arch_info->name, mips_isa);
8902 /* Implement TARGET_ASM_CODE_END. */
8905 mips_code_end (void)
8907 if (mips_need_mips16_rdhwr_p)
8908 mips_output_mips16_rdhwr ();
8911 /* Make the last instruction frame-related and note that it performs
8912 the operation described by FRAME_PATTERN. */
8915 mips_set_frame_expr (rtx frame_pattern)
8919 insn = get_last_insn ();
8920 RTX_FRAME_RELATED_P (insn) = 1;
8921 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
8926 /* Return a frame-related rtx that stores REG at MEM.
8927 REG must be a single register. */
8930 mips_frame_set (rtx mem, rtx reg)
8934 set = gen_rtx_SET (VOIDmode, mem, reg);
8935 RTX_FRAME_RELATED_P (set) = 1;
8940 /* Record that the epilogue has restored call-saved register REG. */
8943 mips_add_cfa_restore (rtx reg)
8945 mips_epilogue.cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg,
8946 mips_epilogue.cfa_restores);
8949 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
8950 mips16e_s2_s8_regs[X], it must also save the registers in indexes
8951 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
8952 static const unsigned char mips16e_s2_s8_regs[] = {
8953 30, 23, 22, 21, 20, 19, 18
8955 static const unsigned char mips16e_a0_a3_regs[] = {
8959 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
8960 ordered from the uppermost in memory to the lowest in memory. */
8961 static const unsigned char mips16e_save_restore_regs[] = {
8962 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
8965 /* Return the index of the lowest X in the range [0, SIZE) for which
8966 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
8969 mips16e_find_first_register (unsigned int mask, const unsigned char *regs,
8974 for (i = 0; i < size; i++)
8975 if (BITSET_P (mask, regs[i]))
8981 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
8982 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
8983 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
8984 is true for all indexes (X, SIZE). */
8987 mips16e_mask_registers (unsigned int *mask_ptr, const unsigned char *regs,
8988 unsigned int size, unsigned int *num_regs_ptr)
8992 i = mips16e_find_first_register (*mask_ptr, regs, size);
8993 for (i++; i < size; i++)
8994 if (!BITSET_P (*mask_ptr, regs[i]))
8997 *mask_ptr |= 1 << regs[i];
9001 /* Return a simplified form of X using the register values in REG_VALUES.
9002 REG_VALUES[R] is the last value assigned to hard register R, or null
9003 if R has not been modified.
9005 This function is rather limited, but is good enough for our purposes. */
9008 mips16e_collect_propagate_value (rtx x, rtx *reg_values)
9010 x = avoid_constant_pool_reference (x);
9014 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
9015 return simplify_gen_unary (GET_CODE (x), GET_MODE (x),
9016 x0, GET_MODE (XEXP (x, 0)));
9019 if (ARITHMETIC_P (x))
9021 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
9022 rtx x1 = mips16e_collect_propagate_value (XEXP (x, 1), reg_values);
9023 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), x0, x1);
9027 && reg_values[REGNO (x)]
9028 && !rtx_unstable_p (reg_values[REGNO (x)]))
9029 return reg_values[REGNO (x)];
9034 /* Return true if (set DEST SRC) stores an argument register into its
9035 caller-allocated save slot, storing the number of that argument
9036 register in *REGNO_PTR if so. REG_VALUES is as for
9037 mips16e_collect_propagate_value. */
9040 mips16e_collect_argument_save_p (rtx dest, rtx src, rtx *reg_values,
9041 unsigned int *regno_ptr)
9043 unsigned int argno, regno;
9044 HOST_WIDE_INT offset, required_offset;
9047 /* Check that this is a word-mode store. */
9048 if (!MEM_P (dest) || !REG_P (src) || GET_MODE (dest) != word_mode)
9051 /* Check that the register being saved is an unmodified argument
9053 regno = REGNO (src);
9054 if (!IN_RANGE (regno, GP_ARG_FIRST, GP_ARG_LAST) || reg_values[regno])
9056 argno = regno - GP_ARG_FIRST;
9058 /* Check whether the address is an appropriate stack-pointer or
9059 frame-pointer access. */
9060 addr = mips16e_collect_propagate_value (XEXP (dest, 0), reg_values);
9061 mips_split_plus (addr, &base, &offset);
9062 required_offset = cfun->machine->frame.total_size + argno * UNITS_PER_WORD;
9063 if (base == hard_frame_pointer_rtx)
9064 required_offset -= cfun->machine->frame.hard_frame_pointer_offset;
9065 else if (base != stack_pointer_rtx)
9067 if (offset != required_offset)
9074 /* A subroutine of mips_expand_prologue, called only when generating
9075 MIPS16e SAVE instructions. Search the start of the function for any
9076 instructions that save argument registers into their caller-allocated
9077 save slots. Delete such instructions and return a value N such that
9078 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
9079 instructions redundant. */
9082 mips16e_collect_argument_saves (void)
9084 rtx reg_values[FIRST_PSEUDO_REGISTER];
9085 rtx insn, next, set, dest, src;
9086 unsigned int nargs, regno;
9088 push_topmost_sequence ();
9090 memset (reg_values, 0, sizeof (reg_values));
9091 for (insn = get_insns (); insn; insn = next)
9093 next = NEXT_INSN (insn);
9094 if (NOTE_P (insn) || DEBUG_INSN_P (insn))
9100 set = PATTERN (insn);
9101 if (GET_CODE (set) != SET)
9104 dest = SET_DEST (set);
9105 src = SET_SRC (set);
9106 if (mips16e_collect_argument_save_p (dest, src, reg_values, ®no))
9108 if (!BITSET_P (cfun->machine->frame.mask, regno))
9111 nargs = MAX (nargs, (regno - GP_ARG_FIRST) + 1);
9114 else if (REG_P (dest) && GET_MODE (dest) == word_mode)
9115 reg_values[REGNO (dest)]
9116 = mips16e_collect_propagate_value (src, reg_values);
9120 pop_topmost_sequence ();
9125 /* Return a move between register REGNO and memory location SP + OFFSET.
9126 REG_PARM_P is true if SP + OFFSET belongs to REG_PARM_STACK_SPACE.
9127 Make the move a load if RESTORE_P, otherwise make it a store. */
9130 mips16e_save_restore_reg (bool restore_p, bool reg_parm_p,
9131 HOST_WIDE_INT offset, unsigned int regno)
9135 mem = gen_frame_mem (SImode, plus_constant (Pmode, stack_pointer_rtx,
9137 reg = gen_rtx_REG (SImode, regno);
9140 mips_add_cfa_restore (reg);
9141 return gen_rtx_SET (VOIDmode, reg, mem);
9144 return gen_rtx_SET (VOIDmode, mem, reg);
9145 return mips_frame_set (mem, reg);
9148 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
9149 The instruction must:
9151 - Allocate or deallocate SIZE bytes in total; SIZE is known
9154 - Save or restore as many registers in *MASK_PTR as possible.
9155 The instruction saves the first registers at the top of the
9156 allocated area, with the other registers below it.
9158 - Save NARGS argument registers above the allocated area.
9160 (NARGS is always zero if RESTORE_P.)
9162 The SAVE and RESTORE instructions cannot save and restore all general
9163 registers, so there may be some registers left over for the caller to
9164 handle. Destructively modify *MASK_PTR so that it contains the registers
9165 that still need to be saved or restored. The caller can save these
9166 registers in the memory immediately below *OFFSET_PTR, which is a
9167 byte offset from the bottom of the allocated stack area. */
9170 mips16e_build_save_restore (bool restore_p, unsigned int *mask_ptr,
9171 HOST_WIDE_INT *offset_ptr, unsigned int nargs,
9175 HOST_WIDE_INT offset, top_offset;
9176 unsigned int i, regno;
9179 gcc_assert (cfun->machine->frame.num_fp == 0);
9181 /* Calculate the number of elements in the PARALLEL. We need one element
9182 for the stack adjustment, one for each argument register save, and one
9183 for each additional register move. */
9185 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
9186 if (BITSET_P (*mask_ptr, mips16e_save_restore_regs[i]))
9189 /* Create the final PARALLEL. */
9190 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (n));
9193 /* Add the stack pointer adjustment. */
9194 set = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
9195 plus_constant (Pmode, stack_pointer_rtx,
9196 restore_p ? size : -size));
9197 RTX_FRAME_RELATED_P (set) = 1;
9198 XVECEXP (pattern, 0, n++) = set;
9200 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
9201 top_offset = restore_p ? size : 0;
9203 /* Save the arguments. */
9204 for (i = 0; i < nargs; i++)
9206 offset = top_offset + i * UNITS_PER_WORD;
9207 set = mips16e_save_restore_reg (restore_p, true, offset,
9209 XVECEXP (pattern, 0, n++) = set;
9212 /* Then fill in the other register moves. */
9213 offset = top_offset;
9214 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
9216 regno = mips16e_save_restore_regs[i];
9217 if (BITSET_P (*mask_ptr, regno))
9219 offset -= UNITS_PER_WORD;
9220 set = mips16e_save_restore_reg (restore_p, false, offset, regno);
9221 XVECEXP (pattern, 0, n++) = set;
9222 *mask_ptr &= ~(1 << regno);
9226 /* Tell the caller what offset it should use for the remaining registers. */
9227 *offset_ptr = size + (offset - top_offset);
9229 gcc_assert (n == XVECLEN (pattern, 0));
9234 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
9235 pointer. Return true if PATTERN matches the kind of instruction
9236 generated by mips16e_build_save_restore. If INFO is nonnull,
9237 initialize it when returning true. */
9240 mips16e_save_restore_pattern_p (rtx pattern, HOST_WIDE_INT adjust,
9241 struct mips16e_save_restore_info *info)
9243 unsigned int i, nargs, mask, extra;
9244 HOST_WIDE_INT top_offset, save_offset, offset;
9245 rtx set, reg, mem, base;
9248 if (!GENERATE_MIPS16E_SAVE_RESTORE)
9251 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
9252 top_offset = adjust > 0 ? adjust : 0;
9254 /* Interpret all other members of the PARALLEL. */
9255 save_offset = top_offset - UNITS_PER_WORD;
9259 for (n = 1; n < XVECLEN (pattern, 0); n++)
9261 /* Check that we have a SET. */
9262 set = XVECEXP (pattern, 0, n);
9263 if (GET_CODE (set) != SET)
9266 /* Check that the SET is a load (if restoring) or a store
9268 mem = adjust > 0 ? SET_SRC (set) : SET_DEST (set);
9272 /* Check that the address is the sum of the stack pointer and a
9273 possibly-zero constant offset. */
9274 mips_split_plus (XEXP (mem, 0), &base, &offset);
9275 if (base != stack_pointer_rtx)
9278 /* Check that SET's other operand is a register. */
9279 reg = adjust > 0 ? SET_DEST (set) : SET_SRC (set);
9283 /* Check for argument saves. */
9284 if (offset == top_offset + nargs * UNITS_PER_WORD
9285 && REGNO (reg) == GP_ARG_FIRST + nargs)
9287 else if (offset == save_offset)
9289 while (mips16e_save_restore_regs[i++] != REGNO (reg))
9290 if (i == ARRAY_SIZE (mips16e_save_restore_regs))
9293 mask |= 1 << REGNO (reg);
9294 save_offset -= UNITS_PER_WORD;
9300 /* Check that the restrictions on register ranges are met. */
9302 mips16e_mask_registers (&mask, mips16e_s2_s8_regs,
9303 ARRAY_SIZE (mips16e_s2_s8_regs), &extra);
9304 mips16e_mask_registers (&mask, mips16e_a0_a3_regs,
9305 ARRAY_SIZE (mips16e_a0_a3_regs), &extra);
9309 /* Make sure that the topmost argument register is not saved twice.
9310 The checks above ensure that the same is then true for the other
9311 argument registers. */
9312 if (nargs > 0 && BITSET_P (mask, GP_ARG_FIRST + nargs - 1))
9315 /* Pass back information, if requested. */
9318 info->nargs = nargs;
9320 info->size = (adjust > 0 ? adjust : -adjust);
9326 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
9327 for the register range [MIN_REG, MAX_REG]. Return a pointer to
9328 the null terminator. */
9331 mips16e_add_register_range (char *s, unsigned int min_reg,
9332 unsigned int max_reg)
9334 if (min_reg != max_reg)
9335 s += sprintf (s, ",%s-%s", reg_names[min_reg], reg_names[max_reg]);
9337 s += sprintf (s, ",%s", reg_names[min_reg]);
9341 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
9342 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
9345 mips16e_output_save_restore (rtx pattern, HOST_WIDE_INT adjust)
9347 static char buffer[300];
9349 struct mips16e_save_restore_info info;
9350 unsigned int i, end;
9353 /* Parse the pattern. */
9354 if (!mips16e_save_restore_pattern_p (pattern, adjust, &info))
9357 /* Add the mnemonic. */
9358 s = strcpy (buffer, adjust > 0 ? "restore\t" : "save\t");
9361 /* Save the arguments. */
9363 s += sprintf (s, "%s-%s,", reg_names[GP_ARG_FIRST],
9364 reg_names[GP_ARG_FIRST + info.nargs - 1]);
9365 else if (info.nargs == 1)
9366 s += sprintf (s, "%s,", reg_names[GP_ARG_FIRST]);
9368 /* Emit the amount of stack space to allocate or deallocate. */
9369 s += sprintf (s, "%d", (int) info.size);
9371 /* Save or restore $16. */
9372 if (BITSET_P (info.mask, 16))
9373 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 16]);
9375 /* Save or restore $17. */
9376 if (BITSET_P (info.mask, 17))
9377 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 17]);
9379 /* Save or restore registers in the range $s2...$s8, which
9380 mips16e_s2_s8_regs lists in decreasing order. Note that this
9381 is a software register range; the hardware registers are not
9382 numbered consecutively. */
9383 end = ARRAY_SIZE (mips16e_s2_s8_regs);
9384 i = mips16e_find_first_register (info.mask, mips16e_s2_s8_regs, end);
9386 s = mips16e_add_register_range (s, mips16e_s2_s8_regs[end - 1],
9387 mips16e_s2_s8_regs[i]);
9389 /* Save or restore registers in the range $a0...$a3. */
9390 end = ARRAY_SIZE (mips16e_a0_a3_regs);
9391 i = mips16e_find_first_register (info.mask, mips16e_a0_a3_regs, end);
9393 s = mips16e_add_register_range (s, mips16e_a0_a3_regs[i],
9394 mips16e_a0_a3_regs[end - 1]);
9396 /* Save or restore $31. */
9397 if (BITSET_P (info.mask, RETURN_ADDR_REGNUM))
9398 s += sprintf (s, ",%s", reg_names[RETURN_ADDR_REGNUM]);
9403 /* Return true if the current function returns its value in a floating-point
9404 register in MIPS16 mode. */
9407 mips16_cfun_returns_in_fpr_p (void)
9409 tree return_type = DECL_RESULT (current_function_decl);
9410 return (TARGET_MIPS16
9411 && TARGET_HARD_FLOAT_ABI
9412 && !aggregate_value_p (return_type, current_function_decl)
9413 && mips_return_mode_in_fpr_p (DECL_MODE (return_type)));
9416 /* Return true if predicate PRED is true for at least one instruction.
9417 Cache the result in *CACHE, and assume that the result is true
9418 if *CACHE is already true. */
9421 mips_find_gp_ref (bool *cache, bool (*pred) (rtx))
9427 push_topmost_sequence ();
9428 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9429 if (USEFUL_INSN_P (insn) && pred (insn))
9434 pop_topmost_sequence ();
9439 /* Return true if INSN refers to the global pointer in an "inflexible" way.
9440 See mips_cfun_has_inflexible_gp_ref_p for details. */
9443 mips_insn_has_inflexible_gp_ref_p (rtx insn)
9445 /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE
9446 indicate that the target could be a traditional MIPS
9447 lazily-binding stub. */
9448 return find_reg_fusage (insn, USE, pic_offset_table_rtx);
9451 /* Return true if the current function refers to the global pointer
9452 in a way that forces $28 to be valid. This means that we can't
9453 change the choice of global pointer, even for NewABI code.
9455 One example of this (and one which needs several checks) is that
9456 $28 must be valid when calling traditional MIPS lazy-binding stubs.
9457 (This restriction does not apply to PLTs.) */
9460 mips_cfun_has_inflexible_gp_ref_p (void)
9462 /* If the function has a nonlocal goto, $28 must hold the correct
9463 global pointer for the target function. That is, the target
9464 of the goto implicitly uses $28. */
9465 if (crtl->has_nonlocal_goto)
9468 if (TARGET_ABICALLS_PIC2)
9470 /* Symbolic accesses implicitly use the global pointer unless
9471 -mexplicit-relocs is in effect. JAL macros to symbolic addresses
9472 might go to traditional MIPS lazy-binding stubs. */
9473 if (!TARGET_EXPLICIT_RELOCS)
9476 /* FUNCTION_PROFILER includes a JAL to _mcount, which again
9477 can be lazily-bound. */
9481 /* MIPS16 functions that return in FPRs need to call an
9482 external libgcc routine. This call is only made explict
9483 during mips_expand_epilogue, and it too might be lazily bound. */
9484 if (mips16_cfun_returns_in_fpr_p ())
9488 return mips_find_gp_ref (&cfun->machine->has_inflexible_gp_insn_p,
9489 mips_insn_has_inflexible_gp_ref_p);
9492 /* Return true if INSN refers to the global pointer in a "flexible" way.
9493 See mips_cfun_has_flexible_gp_ref_p for details. */
9496 mips_insn_has_flexible_gp_ref_p (rtx insn)
9498 return (get_attr_got (insn) != GOT_UNSET
9499 || mips_small_data_pattern_p (PATTERN (insn))
9500 || reg_overlap_mentioned_p (pic_offset_table_rtx, PATTERN (insn)));
9503 /* Return true if the current function references the global pointer,
9504 but if those references do not inherently require the global pointer
9505 to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */
9508 mips_cfun_has_flexible_gp_ref_p (void)
9510 /* Reload can sometimes introduce constant pool references
9511 into a function that otherwise didn't need them. For example,
9512 suppose we have an instruction like:
9514 (set (reg:DF R1) (float:DF (reg:SI R2)))
9516 If R2 turns out to be a constant such as 1, the instruction may
9517 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
9518 the option of using this constant if R2 doesn't get allocated
9521 In cases like these, reload will have added the constant to the
9522 pool but no instruction will yet refer to it. */
9523 if (TARGET_ABICALLS_PIC2 && !reload_completed && crtl->uses_const_pool)
9526 return mips_find_gp_ref (&cfun->machine->has_flexible_gp_insn_p,
9527 mips_insn_has_flexible_gp_ref_p);
9530 /* Return the register that should be used as the global pointer
9531 within this function. Return INVALID_REGNUM if the function
9532 doesn't need a global pointer. */
9535 mips_global_pointer (void)
9539 /* $gp is always available unless we're using a GOT. */
9540 if (!TARGET_USE_GOT)
9541 return GLOBAL_POINTER_REGNUM;
9543 /* If there are inflexible references to $gp, we must use the
9544 standard register. */
9545 if (mips_cfun_has_inflexible_gp_ref_p ())
9546 return GLOBAL_POINTER_REGNUM;
9548 /* If there are no current references to $gp, then the only uses
9549 we can introduce later are those involved in long branches. */
9550 if (TARGET_ABSOLUTE_JUMPS && !mips_cfun_has_flexible_gp_ref_p ())
9551 return INVALID_REGNUM;
9553 /* If the global pointer is call-saved, try to use a call-clobbered
9555 if (TARGET_CALL_SAVED_GP && crtl->is_leaf)
9556 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
9557 if (!df_regs_ever_live_p (regno)
9558 && call_really_used_regs[regno]
9559 && !fixed_regs[regno]
9560 && regno != PIC_FUNCTION_ADDR_REGNUM)
9563 return GLOBAL_POINTER_REGNUM;
9566 /* Return true if the current function's prologue must load the global
9567 pointer value into pic_offset_table_rtx and store the same value in
9568 the function's cprestore slot (if any).
9570 One problem we have to deal with is that, when emitting GOT-based
9571 position independent code, long-branch sequences will need to load
9572 the address of the branch target from the GOT. We don't know until
9573 the very end of compilation whether (and where) the function needs
9574 long branches, so we must ensure that _any_ branch can access the
9575 global pointer in some form. However, we do not want to pessimize
9576 the usual case in which all branches are short.
9578 We handle this as follows:
9580 (1) During reload, we set cfun->machine->global_pointer to
9581 INVALID_REGNUM if we _know_ that the current function
9582 doesn't need a global pointer. This is only valid if
9583 long branches don't need the GOT.
9585 Otherwise, we assume that we might need a global pointer
9586 and pick an appropriate register.
9588 (2) If cfun->machine->global_pointer != INVALID_REGNUM,
9589 we ensure that the global pointer is available at every
9590 block boundary bar entry and exit. We do this in one of two ways:
9592 - If the function has a cprestore slot, we ensure that this
9593 slot is valid at every branch. However, as explained in
9594 point (6) below, there is no guarantee that pic_offset_table_rtx
9595 itself is valid if new uses of the global pointer are introduced
9596 after the first post-epilogue split.
9598 We guarantee that the cprestore slot is valid by loading it
9599 into a fake register, CPRESTORE_SLOT_REGNUM. We then make
9600 this register live at every block boundary bar function entry
9601 and exit. It is then invalid to move the load (and thus the
9602 preceding store) across a block boundary.
9604 - If the function has no cprestore slot, we guarantee that
9605 pic_offset_table_rtx itself is valid at every branch.
9607 See mips_eh_uses for the handling of the register liveness.
9609 (3) During prologue and epilogue generation, we emit "ghost"
9610 placeholder instructions to manipulate the global pointer.
9612 (4) During prologue generation, we set cfun->machine->must_initialize_gp_p
9613 and cfun->machine->must_restore_gp_when_clobbered_p if we already know
9614 that the function needs a global pointer. (There is no need to set
9615 them earlier than this, and doing it as late as possible leads to
9616 fewer false positives.)
9618 (5) If cfun->machine->must_initialize_gp_p is true during a
9619 split_insns pass, we split the ghost instructions into real
9620 instructions. These split instructions can then be optimized in
9621 the usual way. Otherwise, we keep the ghost instructions intact,
9622 and optimize for the case where they aren't needed. We still
9623 have the option of splitting them later, if we need to introduce
9624 new uses of the global pointer.
9626 For example, the scheduler ignores a ghost instruction that
9627 stores $28 to the stack, but it handles the split form of
9628 the ghost instruction as an ordinary store.
9630 (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p
9631 is true during the first post-epilogue split_insns pass, we split
9632 calls and restore_gp patterns into instructions that explicitly
9633 load pic_offset_table_rtx from the cprestore slot. Otherwise,
9634 we split these patterns into instructions that _don't_ load from
9637 If cfun->machine->must_restore_gp_when_clobbered_p is true at the
9638 time of the split, then any instructions that exist at that time
9639 can make free use of pic_offset_table_rtx. However, if we want
9640 to introduce new uses of the global pointer after the split,
9641 we must explicitly load the value from the cprestore slot, since
9642 pic_offset_table_rtx itself might not be valid at a given point
9645 The idea is that we want to be able to delete redundant
9646 loads from the cprestore slot in the usual case where no
9647 long branches are needed.
9649 (7) If cfun->machine->must_initialize_gp_p is still false at the end
9650 of md_reorg, we decide whether the global pointer is needed for
9651 long branches. If so, we set cfun->machine->must_initialize_gp_p
9652 to true and split the ghost instructions into real instructions
9655 Note that the ghost instructions must have a zero length for three reasons:
9657 - Giving the length of the underlying $gp sequence might cause
9658 us to use long branches in cases where they aren't really needed.
9660 - They would perturb things like alignment calculations.
9662 - More importantly, the hazard detection in md_reorg relies on
9663 empty instructions having a zero length.
9665 If we find a long branch and split the ghost instructions at the
9666 end of md_reorg, the split could introduce more long branches.
9667 That isn't a problem though, because we still do the split before
9668 the final shorten_branches pass.
9670 This is extremely ugly, but it seems like the best compromise between
9671 correctness and efficiency. */
9674 mips_must_initialize_gp_p (void)
9676 return cfun->machine->must_initialize_gp_p;
9679 /* Return true if REGNO is a register that is ordinarily call-clobbered
9680 but must nevertheless be preserved by an interrupt handler. */
9683 mips_interrupt_extra_call_saved_reg_p (unsigned int regno)
9685 if (MD_REG_P (regno))
9688 if (TARGET_DSP && DSP_ACC_REG_P (regno))
9691 if (GP_REG_P (regno) && !cfun->machine->use_shadow_register_set_p)
9693 /* $0 is hard-wired. */
9694 if (regno == GP_REG_FIRST)
9697 /* The interrupt handler can treat kernel registers as
9698 scratch registers. */
9699 if (KERNEL_REG_P (regno))
9702 /* The function will return the stack pointer to its original value
9704 if (regno == STACK_POINTER_REGNUM)
9707 /* Otherwise, return true for registers that aren't ordinarily
9709 return call_really_used_regs[regno];
9715 /* Return true if the current function should treat register REGNO
9719 mips_cfun_call_saved_reg_p (unsigned int regno)
9721 /* If the user makes an ordinarily-call-saved register global,
9722 that register is no longer call-saved. */
9723 if (global_regs[regno])
9726 /* Interrupt handlers need to save extra registers. */
9727 if (cfun->machine->interrupt_handler_p
9728 && mips_interrupt_extra_call_saved_reg_p (regno))
9731 /* call_insns preserve $28 unless they explicitly say otherwise,
9732 so call_really_used_regs[] treats $28 as call-saved. However,
9733 we want the ABI property rather than the default call_insn
9735 return (regno == GLOBAL_POINTER_REGNUM
9736 ? TARGET_CALL_SAVED_GP
9737 : !call_really_used_regs[regno]);
9740 /* Return true if the function body might clobber register REGNO.
9741 We know that REGNO is call-saved. */
9744 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno)
9746 /* Some functions should be treated as clobbering all call-saved
9748 if (crtl->saves_all_registers)
9751 /* DF handles cases where a register is explicitly referenced in
9752 the rtl. Incoming values are passed in call-clobbered registers,
9753 so we can assume that any live call-saved register is set within
9755 if (df_regs_ever_live_p (regno))
9758 /* Check for registers that are clobbered by FUNCTION_PROFILER.
9759 These clobbers are not explicit in the rtl. */
9760 if (crtl->profile && MIPS_SAVE_REG_FOR_PROFILING_P (regno))
9763 /* If we're using a call-saved global pointer, the function's
9764 prologue will need to set it up. */
9765 if (cfun->machine->global_pointer == regno)
9768 /* The function's prologue will need to set the frame pointer if
9769 frame_pointer_needed. */
9770 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
9773 /* If a MIPS16 function returns a value in FPRs, its epilogue
9774 will need to call an external libgcc routine. This yet-to-be
9775 generated call_insn will clobber $31. */
9776 if (regno == RETURN_ADDR_REGNUM && mips16_cfun_returns_in_fpr_p ())
9779 /* If REGNO is ordinarily call-clobbered, we must assume that any
9780 called function could modify it. */
9781 if (cfun->machine->interrupt_handler_p
9783 && mips_interrupt_extra_call_saved_reg_p (regno))
9789 /* Return true if the current function must save register REGNO. */
9792 mips_save_reg_p (unsigned int regno)
9794 if (mips_cfun_call_saved_reg_p (regno))
9796 if (mips_cfun_might_clobber_call_saved_reg_p (regno))
9799 /* Save both registers in an FPR pair if either one is used. This is
9800 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
9801 register to be used without the even register. */
9802 if (FP_REG_P (regno)
9803 && MAX_FPRS_PER_FMT == 2
9804 && mips_cfun_might_clobber_call_saved_reg_p (regno + 1))
9808 /* We need to save the incoming return address if __builtin_eh_return
9809 is being used to set a different return address. */
9810 if (regno == RETURN_ADDR_REGNUM && crtl->calls_eh_return)
9816 /* Populate the current function's mips_frame_info structure.
9818 MIPS stack frames look like:
9820 +-------------------------------+
9822 | incoming stack arguments |
9824 +-------------------------------+
9826 | caller-allocated save area |
9827 A | for register arguments |
9829 +-------------------------------+ <-- incoming stack pointer
9831 | callee-allocated save area |
9832 B | for arguments that are |
9833 | split between registers and |
9836 +-------------------------------+ <-- arg_pointer_rtx
9838 C | callee-allocated save area |
9839 | for register varargs |
9841 +-------------------------------+ <-- frame_pointer_rtx
9842 | | + cop0_sp_offset
9843 | COP0 reg save area | + UNITS_PER_WORD
9845 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
9846 | | + UNITS_PER_WORD
9847 | accumulator save area |
9849 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
9850 | | + UNITS_PER_HWFPVALUE
9853 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset
9854 | | + UNITS_PER_WORD
9857 +-------------------------------+ <-- frame_pointer_rtx with
9858 | | \ -fstack-protector
9859 | local variables | | var_size
9861 +-------------------------------+
9863 | $gp save area | | cprestore_size
9865 P +-------------------------------+ <-- hard_frame_pointer_rtx for
9867 | outgoing stack arguments | |
9869 +-------------------------------+ | args_size
9871 | caller-allocated save area | |
9872 | for register arguments | |
9874 +-------------------------------+ <-- stack_pointer_rtx
9875 frame_pointer_rtx without
9877 hard_frame_pointer_rtx for
9880 At least two of A, B and C will be empty.
9882 Dynamic stack allocations such as alloca insert data at point P.
9883 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
9884 hard_frame_pointer_rtx unchanged. */
9887 mips_compute_frame_info (void)
9889 struct mips_frame_info *frame;
9890 HOST_WIDE_INT offset, size;
9891 unsigned int regno, i;
9893 /* Set this function's interrupt properties. */
9894 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
9897 error ("the %<interrupt%> attribute requires a MIPS32r2 processor");
9898 else if (TARGET_HARD_FLOAT)
9899 error ("the %<interrupt%> attribute requires %<-msoft-float%>");
9900 else if (TARGET_MIPS16)
9901 error ("interrupt handlers cannot be MIPS16 functions");
9904 cfun->machine->interrupt_handler_p = true;
9905 cfun->machine->use_shadow_register_set_p =
9906 mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl));
9907 cfun->machine->keep_interrupts_masked_p =
9908 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl));
9909 cfun->machine->use_debug_exception_return_p =
9910 mips_use_debug_exception_return_p (TREE_TYPE
9911 (current_function_decl));
9915 frame = &cfun->machine->frame;
9916 memset (frame, 0, sizeof (*frame));
9917 size = get_frame_size ();
9919 cfun->machine->global_pointer = mips_global_pointer ();
9921 /* The first two blocks contain the outgoing argument area and the $gp save
9922 slot. This area isn't needed in leaf functions, but if the
9923 target-independent frame size is nonzero, we have already committed to
9924 allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */
9925 if ((size == 0 || FRAME_GROWS_DOWNWARD) && crtl->is_leaf)
9927 /* The MIPS 3.0 linker does not like functions that dynamically
9928 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
9929 looks like we are trying to create a second frame pointer to the
9930 function, so allocate some stack space to make it happy. */
9931 if (cfun->calls_alloca)
9932 frame->args_size = REG_PARM_STACK_SPACE (cfun->decl);
9934 frame->args_size = 0;
9935 frame->cprestore_size = 0;
9939 frame->args_size = crtl->outgoing_args_size;
9940 frame->cprestore_size = MIPS_GP_SAVE_AREA_SIZE;
9942 offset = frame->args_size + frame->cprestore_size;
9944 /* Move above the local variables. */
9945 frame->var_size = MIPS_STACK_ALIGN (size);
9946 offset += frame->var_size;
9948 /* Find out which GPRs we need to save. */
9949 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
9950 if (mips_save_reg_p (regno))
9953 frame->mask |= 1 << (regno - GP_REG_FIRST);
9956 /* If this function calls eh_return, we must also save and restore the
9957 EH data registers. */
9958 if (crtl->calls_eh_return)
9959 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; i++)
9962 frame->mask |= 1 << (EH_RETURN_DATA_REGNO (i) - GP_REG_FIRST);
9965 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
9966 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
9967 save all later registers too. */
9968 if (GENERATE_MIPS16E_SAVE_RESTORE)
9970 mips16e_mask_registers (&frame->mask, mips16e_s2_s8_regs,
9971 ARRAY_SIZE (mips16e_s2_s8_regs), &frame->num_gp);
9972 mips16e_mask_registers (&frame->mask, mips16e_a0_a3_regs,
9973 ARRAY_SIZE (mips16e_a0_a3_regs), &frame->num_gp);
9976 /* Move above the GPR save area. */
9977 if (frame->num_gp > 0)
9979 offset += MIPS_STACK_ALIGN (frame->num_gp * UNITS_PER_WORD);
9980 frame->gp_sp_offset = offset - UNITS_PER_WORD;
9983 /* Find out which FPRs we need to save. This loop must iterate over
9984 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
9985 if (TARGET_HARD_FLOAT)
9986 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += MAX_FPRS_PER_FMT)
9987 if (mips_save_reg_p (regno))
9989 frame->num_fp += MAX_FPRS_PER_FMT;
9990 frame->fmask |= ~(~0 << MAX_FPRS_PER_FMT) << (regno - FP_REG_FIRST);
9993 /* Move above the FPR save area. */
9994 if (frame->num_fp > 0)
9996 offset += MIPS_STACK_ALIGN (frame->num_fp * UNITS_PER_FPREG);
9997 frame->fp_sp_offset = offset - UNITS_PER_HWFPVALUE;
10000 /* Add in space for the interrupt context information. */
10001 if (cfun->machine->interrupt_handler_p)
10004 if (mips_save_reg_p (LO_REGNUM) || mips_save_reg_p (HI_REGNUM))
10007 frame->acc_mask |= (1 << 0);
10010 /* Check accumulators 1, 2, 3. */
10011 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
10012 if (mips_save_reg_p (i) || mips_save_reg_p (i + 1))
10015 frame->acc_mask |= 1 << (((i - DSP_ACC_REG_FIRST) / 2) + 1);
10018 /* All interrupt context functions need space to preserve STATUS. */
10019 frame->num_cop0_regs++;
10021 /* If we don't keep interrupts masked, we need to save EPC. */
10022 if (!cfun->machine->keep_interrupts_masked_p)
10023 frame->num_cop0_regs++;
10026 /* Move above the accumulator save area. */
10027 if (frame->num_acc > 0)
10029 /* Each accumulator needs 2 words. */
10030 offset += frame->num_acc * 2 * UNITS_PER_WORD;
10031 frame->acc_sp_offset = offset - UNITS_PER_WORD;
10034 /* Move above the COP0 register save area. */
10035 if (frame->num_cop0_regs > 0)
10037 offset += frame->num_cop0_regs * UNITS_PER_WORD;
10038 frame->cop0_sp_offset = offset - UNITS_PER_WORD;
10041 /* Move above the callee-allocated varargs save area. */
10042 offset += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
10043 frame->arg_pointer_offset = offset;
10045 /* Move above the callee-allocated area for pretend stack arguments. */
10046 offset += crtl->args.pretend_args_size;
10047 frame->total_size = offset;
10049 /* Work out the offsets of the save areas from the top of the frame. */
10050 if (frame->gp_sp_offset > 0)
10051 frame->gp_save_offset = frame->gp_sp_offset - offset;
10052 if (frame->fp_sp_offset > 0)
10053 frame->fp_save_offset = frame->fp_sp_offset - offset;
10054 if (frame->acc_sp_offset > 0)
10055 frame->acc_save_offset = frame->acc_sp_offset - offset;
10056 if (frame->num_cop0_regs > 0)
10057 frame->cop0_save_offset = frame->cop0_sp_offset - offset;
10059 /* MIPS16 code offsets the frame pointer by the size of the outgoing
10060 arguments. This tends to increase the chances of using unextended
10061 instructions for local variables and incoming arguments. */
10063 frame->hard_frame_pointer_offset = frame->args_size;
10066 /* Return the style of GP load sequence that is being used for the
10067 current function. */
10069 enum mips_loadgp_style
10070 mips_current_loadgp_style (void)
10072 if (!TARGET_USE_GOT || cfun->machine->global_pointer == INVALID_REGNUM)
10073 return LOADGP_NONE;
10075 if (TARGET_RTP_PIC)
10078 if (TARGET_ABSOLUTE_ABICALLS)
10079 return LOADGP_ABSOLUTE;
10081 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
10084 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
10087 mips_frame_pointer_required (void)
10089 /* If the function contains dynamic stack allocations, we need to
10090 use the frame pointer to access the static parts of the frame. */
10091 if (cfun->calls_alloca)
10094 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
10095 reload may be unable to compute the address of a local variable,
10096 since there is no way to add a large constant to the stack pointer
10097 without using a second temporary register. */
10100 mips_compute_frame_info ();
10101 if (!SMALL_OPERAND (cfun->machine->frame.total_size))
10108 /* Make sure that we're not trying to eliminate to the wrong hard frame
10112 mips_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
10114 return (to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM);
10117 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
10118 or argument pointer. TO is either the stack pointer or hard frame
10122 mips_initial_elimination_offset (int from, int to)
10124 HOST_WIDE_INT offset;
10126 mips_compute_frame_info ();
10128 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */
10131 case FRAME_POINTER_REGNUM:
10132 if (FRAME_GROWS_DOWNWARD)
10133 offset = (cfun->machine->frame.args_size
10134 + cfun->machine->frame.cprestore_size
10135 + cfun->machine->frame.var_size);
10140 case ARG_POINTER_REGNUM:
10141 offset = cfun->machine->frame.arg_pointer_offset;
10145 gcc_unreachable ();
10148 if (to == HARD_FRAME_POINTER_REGNUM)
10149 offset -= cfun->machine->frame.hard_frame_pointer_offset;
10154 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
10157 mips_extra_live_on_entry (bitmap regs)
10159 if (TARGET_USE_GOT)
10161 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
10162 the global pointer. */
10163 if (!TARGET_ABSOLUTE_ABICALLS)
10164 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
10166 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
10167 the global pointer. */
10169 bitmap_set_bit (regs, MIPS16_PIC_TEMP_REGNUM);
10171 /* See the comment above load_call<mode> for details. */
10172 bitmap_set_bit (regs, GOT_VERSION_REGNUM);
10176 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
10180 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
10185 return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);
10188 /* Emit code to change the current function's return address to
10189 ADDRESS. SCRATCH is available as a scratch register, if needed.
10190 ADDRESS and SCRATCH are both word-mode GPRs. */
10193 mips_set_return_address (rtx address, rtx scratch)
10197 gcc_assert (BITSET_P (cfun->machine->frame.mask, RETURN_ADDR_REGNUM));
10198 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
10199 cfun->machine->frame.gp_sp_offset);
10200 mips_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address);
10203 /* Return true if the current function has a cprestore slot. */
10206 mips_cfun_has_cprestore_slot_p (void)
10208 return (cfun->machine->global_pointer != INVALID_REGNUM
10209 && cfun->machine->frame.cprestore_size > 0);
10212 /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the
10213 cprestore slot. LOAD_P is true if the caller wants to load from
10214 the cprestore slot; it is false if the caller wants to store to
10218 mips_get_cprestore_base_and_offset (rtx *base, HOST_WIDE_INT *offset,
10221 const struct mips_frame_info *frame;
10223 frame = &cfun->machine->frame;
10224 /* .cprestore always uses the stack pointer instead of the frame pointer.
10225 We have a free choice for direct stores for non-MIPS16 functions,
10226 and for MIPS16 functions whose cprestore slot is in range of the
10227 stack pointer. Using the stack pointer would sometimes give more
10228 (early) scheduling freedom, but using the frame pointer would
10229 sometimes give more (late) scheduling freedom. It's hard to
10230 predict which applies to a given function, so let's keep things
10233 Loads must always use the frame pointer in functions that call
10234 alloca, and there's little benefit to using the stack pointer
10236 if (frame_pointer_needed && !(TARGET_CPRESTORE_DIRECTIVE && !load_p))
10238 *base = hard_frame_pointer_rtx;
10239 *offset = frame->args_size - frame->hard_frame_pointer_offset;
10243 *base = stack_pointer_rtx;
10244 *offset = frame->args_size;
10248 /* Return true if X is the load or store address of the cprestore slot;
10249 LOAD_P says which. */
10252 mips_cprestore_address_p (rtx x, bool load_p)
10254 rtx given_base, required_base;
10255 HOST_WIDE_INT given_offset, required_offset;
10257 mips_split_plus (x, &given_base, &given_offset);
10258 mips_get_cprestore_base_and_offset (&required_base, &required_offset, load_p);
10259 return given_base == required_base && given_offset == required_offset;
10262 /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are
10263 going to load from it, false if we are going to store to it.
10264 Use TEMP as a temporary register if need be. */
10267 mips_cprestore_slot (rtx temp, bool load_p)
10270 HOST_WIDE_INT offset;
10272 mips_get_cprestore_base_and_offset (&base, &offset, load_p);
10273 return gen_frame_mem (Pmode, mips_add_offset (temp, base, offset));
10276 /* Emit instructions to save global pointer value GP into cprestore
10277 slot MEM. OFFSET is the offset that MEM applies to the base register.
10279 MEM may not be a legitimate address. If it isn't, TEMP is a
10280 temporary register that can be used, otherwise it is a SCRATCH. */
10283 mips_save_gp_to_cprestore_slot (rtx mem, rtx offset, rtx gp, rtx temp)
10285 if (TARGET_CPRESTORE_DIRECTIVE)
10287 gcc_assert (gp == pic_offset_table_rtx);
10288 emit_insn (PMODE_INSN (gen_cprestore, (mem, offset)));
10291 mips_emit_move (mips_cprestore_slot (temp, false), gp);
10294 /* Restore $gp from its save slot, using TEMP as a temporary base register
10295 if need be. This function is for o32 and o64 abicalls only.
10297 See mips_must_initialize_gp_p for details about how we manage the
10301 mips_restore_gp_from_cprestore_slot (rtx temp)
10303 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI && epilogue_completed);
10305 if (!cfun->machine->must_restore_gp_when_clobbered_p)
10307 emit_note (NOTE_INSN_DELETED);
10313 mips_emit_move (temp, mips_cprestore_slot (temp, true));
10314 mips_emit_move (pic_offset_table_rtx, temp);
10317 mips_emit_move (pic_offset_table_rtx, mips_cprestore_slot (temp, true));
10318 if (!TARGET_EXPLICIT_RELOCS)
10319 emit_insn (gen_blockage ());
10322 /* A function to save or store a register. The first argument is the
10323 register and the second is the stack slot. */
10324 typedef void (*mips_save_restore_fn) (rtx, rtx);
10326 /* Use FN to save or restore register REGNO. MODE is the register's
10327 mode and OFFSET is the offset of its save slot from the current
10331 mips_save_restore_reg (enum machine_mode mode, int regno,
10332 HOST_WIDE_INT offset, mips_save_restore_fn fn)
10336 mem = gen_frame_mem (mode, plus_constant (Pmode, stack_pointer_rtx,
10338 fn (gen_rtx_REG (mode, regno), mem);
10341 /* Call FN for each accumlator that is saved by the current function.
10342 SP_OFFSET is the offset of the current stack pointer from the start
10346 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
10348 HOST_WIDE_INT offset;
10351 offset = cfun->machine->frame.acc_sp_offset - sp_offset;
10352 if (BITSET_P (cfun->machine->frame.acc_mask, 0))
10354 mips_save_restore_reg (word_mode, LO_REGNUM, offset, fn);
10355 offset -= UNITS_PER_WORD;
10356 mips_save_restore_reg (word_mode, HI_REGNUM, offset, fn);
10357 offset -= UNITS_PER_WORD;
10360 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
10361 if (BITSET_P (cfun->machine->frame.acc_mask,
10362 ((regno - DSP_ACC_REG_FIRST) / 2) + 1))
10364 mips_save_restore_reg (word_mode, regno, offset, fn);
10365 offset -= UNITS_PER_WORD;
10369 /* Save register REG to MEM. Make the instruction frame-related. */
10372 mips_save_reg (rtx reg, rtx mem)
10374 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
10378 mips_emit_move_or_split (mem, reg, SPLIT_IF_NECESSARY);
10380 x1 = mips_frame_set (mips_subword (mem, false),
10381 mips_subword (reg, false));
10382 x2 = mips_frame_set (mips_subword (mem, true),
10383 mips_subword (reg, true));
10384 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
10387 mips_emit_save_slot_move (mem, reg, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
10390 /* Capture the register combinations that are allowed in a SWM or LWM
10391 instruction. The entries are ordered by number of registers set in
10392 the mask. We also ignore the single register encodings because a
10393 normal SW/LW is preferred. */
10395 static const unsigned int umips_swm_mask[17] = {
10396 0xc0ff0000, 0x80ff0000, 0x40ff0000, 0x807f0000,
10397 0x00ff0000, 0x803f0000, 0x007f0000, 0x801f0000,
10398 0x003f0000, 0x800f0000, 0x001f0000, 0x80070000,
10399 0x000f0000, 0x80030000, 0x00070000, 0x80010000,
10403 static const unsigned int umips_swm_encoding[17] = {
10404 25, 24, 9, 23, 8, 22, 7, 21, 6, 20, 5, 19, 4, 18, 3, 17, 2
10407 /* Try to use a microMIPS LWM or SWM instruction to save or restore
10408 as many GPRs in *MASK as possible. *OFFSET is the offset from the
10409 stack pointer of the topmost save slot.
10411 Remove from *MASK all registers that were handled using LWM and SWM.
10412 Update *OFFSET so that it points to the first unused save slot. */
10415 umips_build_save_restore (mips_save_restore_fn fn,
10416 unsigned *mask, HOST_WIDE_INT *offset)
10420 rtx pattern, set, reg, mem;
10421 HOST_WIDE_INT this_offset;
10424 /* Try matching $16 to $31 (s0 to ra). */
10425 for (i = 0; i < ARRAY_SIZE (umips_swm_mask); i++)
10426 if ((*mask & 0xffff0000) == umips_swm_mask[i])
10429 if (i == ARRAY_SIZE (umips_swm_mask))
10432 /* Get the offset of the lowest save slot. */
10433 nregs = (umips_swm_encoding[i] & 0xf) + (umips_swm_encoding[i] >> 4);
10434 this_offset = *offset - UNITS_PER_WORD * (nregs - 1);
10436 /* LWM/SWM can only support offsets from -2048 to 2047. */
10437 if (!UMIPS_12BIT_OFFSET_P (this_offset))
10440 /* Create the final PARALLEL. */
10441 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nregs));
10442 this_base = stack_pointer_rtx;
10444 /* For registers $16-$23 and $30. */
10445 for (j = 0; j < (umips_swm_encoding[i] & 0xf); j++)
10447 HOST_WIDE_INT offset = this_offset + j * UNITS_PER_WORD;
10448 mem = gen_frame_mem (SImode, plus_constant (Pmode, this_base, offset));
10449 unsigned int regno = (j != 8) ? 16 + j : 30;
10450 *mask &= ~(1 << regno);
10451 reg = gen_rtx_REG (SImode, regno);
10452 if (fn == mips_save_reg)
10453 set = mips_frame_set (mem, reg);
10456 set = gen_rtx_SET (VOIDmode, reg, mem);
10457 mips_add_cfa_restore (reg);
10459 XVECEXP (pattern, 0, j) = set;
10462 /* For register $31. */
10463 if (umips_swm_encoding[i] >> 4)
10465 HOST_WIDE_INT offset = this_offset + j * UNITS_PER_WORD;
10466 *mask &= ~(1 << 31);
10467 mem = gen_frame_mem (SImode, plus_constant (Pmode, this_base, offset));
10468 reg = gen_rtx_REG (SImode, 31);
10469 if (fn == mips_save_reg)
10470 set = mips_frame_set (mem, reg);
10473 set = gen_rtx_SET (VOIDmode, reg, mem);
10474 mips_add_cfa_restore (reg);
10476 XVECEXP (pattern, 0, j) = set;
10479 pattern = emit_insn (pattern);
10480 if (fn == mips_save_reg)
10481 RTX_FRAME_RELATED_P (pattern) = 1;
10483 /* Adjust the last offset. */
10484 *offset -= UNITS_PER_WORD * nregs;
10489 /* Call FN for each register that is saved by the current function.
10490 SP_OFFSET is the offset of the current stack pointer from the start
10494 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset,
10495 mips_save_restore_fn fn)
10497 enum machine_mode fpr_mode;
10499 const struct mips_frame_info *frame = &cfun->machine->frame;
10500 HOST_WIDE_INT offset;
10503 /* Save registers starting from high to low. The debuggers prefer at least
10504 the return register be stored at func+4, and also it allows us not to
10505 need a nop in the epilogue if at least one register is reloaded in
10506 addition to return address. */
10507 offset = frame->gp_sp_offset - sp_offset;
10508 mask = frame->mask;
10510 if (TARGET_MICROMIPS)
10511 umips_build_save_restore (fn, &mask, &offset);
10513 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
10514 if (BITSET_P (mask, regno - GP_REG_FIRST))
10516 /* Record the ra offset for use by mips_function_profiler. */
10517 if (regno == RETURN_ADDR_REGNUM)
10518 cfun->machine->frame.ra_fp_offset = offset + sp_offset;
10519 mips_save_restore_reg (word_mode, regno, offset, fn);
10520 offset -= UNITS_PER_WORD;
10523 /* This loop must iterate over the same space as its companion in
10524 mips_compute_frame_info. */
10525 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
10526 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
10527 for (regno = FP_REG_LAST - MAX_FPRS_PER_FMT + 1;
10528 regno >= FP_REG_FIRST;
10529 regno -= MAX_FPRS_PER_FMT)
10530 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
10532 mips_save_restore_reg (fpr_mode, regno, offset, fn);
10533 offset -= GET_MODE_SIZE (fpr_mode);
10537 /* Return true if a move between register REGNO and its save slot (MEM)
10538 can be done in a single move. LOAD_P is true if we are loading
10539 from the slot, false if we are storing to it. */
10542 mips_direct_save_slot_move_p (unsigned int regno, rtx mem, bool load_p)
10544 /* There is a specific MIPS16 instruction for saving $31 to the stack. */
10545 if (TARGET_MIPS16 && !load_p && regno == RETURN_ADDR_REGNUM)
10548 return mips_secondary_reload_class (REGNO_REG_CLASS (regno),
10549 GET_MODE (mem), mem, load_p) == NO_REGS;
10552 /* Emit a move from SRC to DEST, given that one of them is a register
10553 save slot and that the other is a register. TEMP is a temporary
10554 GPR of the same mode that is available if need be. */
10557 mips_emit_save_slot_move (rtx dest, rtx src, rtx temp)
10559 unsigned int regno;
10564 regno = REGNO (src);
10569 regno = REGNO (dest);
10573 if (regno == cfun->machine->global_pointer && !mips_must_initialize_gp_p ())
10575 /* We don't yet know whether we'll need this instruction or not.
10576 Postpone the decision by emitting a ghost move. This move
10577 is specifically not frame-related; only the split version is. */
10579 emit_insn (gen_move_gpdi (dest, src));
10581 emit_insn (gen_move_gpsi (dest, src));
10585 if (regno == HI_REGNUM)
10589 mips_emit_move (temp, src);
10591 emit_insn (gen_mthisi_di (gen_rtx_REG (TImode, MD_REG_FIRST),
10592 temp, gen_rtx_REG (DImode, LO_REGNUM)));
10594 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode, MD_REG_FIRST),
10595 temp, gen_rtx_REG (SImode, LO_REGNUM)));
10600 emit_insn (gen_mfhidi_ti (temp,
10601 gen_rtx_REG (TImode, MD_REG_FIRST)));
10603 emit_insn (gen_mfhisi_di (temp,
10604 gen_rtx_REG (DImode, MD_REG_FIRST)));
10605 mips_emit_move (dest, temp);
10608 else if (mips_direct_save_slot_move_p (regno, mem, mem == src))
10609 mips_emit_move (dest, src);
10612 gcc_assert (!reg_overlap_mentioned_p (dest, temp));
10613 mips_emit_move (temp, src);
10614 mips_emit_move (dest, temp);
10617 mips_set_frame_expr (mips_frame_set (dest, src));
10620 /* If we're generating n32 or n64 abicalls, and the current function
10621 does not use $28 as its global pointer, emit a cplocal directive.
10622 Use pic_offset_table_rtx as the argument to the directive. */
10625 mips_output_cplocal (void)
10627 if (!TARGET_EXPLICIT_RELOCS
10628 && mips_must_initialize_gp_p ()
10629 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
10630 output_asm_insn (".cplocal %+", 0);
10633 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
10636 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
10638 const char *fnname;
10640 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
10641 floating-point arguments. */
10643 && TARGET_HARD_FLOAT_ABI
10644 && crtl->args.info.fp_code != 0)
10645 mips16_build_function_stub ();
10647 /* Get the function name the same way that toplev.c does before calling
10648 assemble_start_function. This is needed so that the name used here
10649 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10650 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
10651 mips_start_function_definition (fnname, TARGET_MIPS16);
10653 /* Output MIPS-specific frame information. */
10654 if (!flag_inhibit_size_directive)
10656 const struct mips_frame_info *frame;
10658 frame = &cfun->machine->frame;
10660 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
10662 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
10663 "# vars= " HOST_WIDE_INT_PRINT_DEC
10665 ", args= " HOST_WIDE_INT_PRINT_DEC
10666 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
10667 reg_names[frame_pointer_needed
10668 ? HARD_FRAME_POINTER_REGNUM
10669 : STACK_POINTER_REGNUM],
10670 (frame_pointer_needed
10671 ? frame->total_size - frame->hard_frame_pointer_offset
10672 : frame->total_size),
10673 reg_names[RETURN_ADDR_REGNUM],
10675 frame->num_gp, frame->num_fp,
10677 frame->cprestore_size);
10679 /* .mask MASK, OFFSET. */
10680 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
10681 frame->mask, frame->gp_save_offset);
10683 /* .fmask MASK, OFFSET. */
10684 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
10685 frame->fmask, frame->fp_save_offset);
10688 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
10689 Also emit the ".set noreorder; .set nomacro" sequence for functions
10691 if (mips_must_initialize_gp_p ()
10692 && mips_current_loadgp_style () == LOADGP_OLDABI)
10696 /* This is a fixed-form sequence. The position of the
10697 first two instructions is important because of the
10698 way _gp_disp is defined. */
10699 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
10700 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
10701 output_asm_insn ("sll\t$2,16", 0);
10702 output_asm_insn ("addu\t$2,$3", 0);
10706 /* .cpload must be in a .set noreorder but not a
10707 .set nomacro block. */
10708 mips_push_asm_switch (&mips_noreorder);
10709 output_asm_insn (".cpload\t%^", 0);
10710 if (!cfun->machine->all_noreorder_p)
10711 mips_pop_asm_switch (&mips_noreorder);
10713 mips_push_asm_switch (&mips_nomacro);
10716 else if (cfun->machine->all_noreorder_p)
10718 mips_push_asm_switch (&mips_noreorder);
10719 mips_push_asm_switch (&mips_nomacro);
10722 /* Tell the assembler which register we're using as the global
10723 pointer. This is needed for thunks, since they can use either
10724 explicit relocs or assembler macros. */
10725 mips_output_cplocal ();
10728 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
10731 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
10732 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
10734 const char *fnname;
10736 /* Reinstate the normal $gp. */
10737 SET_REGNO (pic_offset_table_rtx, GLOBAL_POINTER_REGNUM);
10738 mips_output_cplocal ();
10740 if (cfun->machine->all_noreorder_p)
10742 mips_pop_asm_switch (&mips_nomacro);
10743 mips_pop_asm_switch (&mips_noreorder);
10746 /* Get the function name the same way that toplev.c does before calling
10747 assemble_start_function. This is needed so that the name used here
10748 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10749 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
10750 mips_end_function_definition (fnname);
10753 /* Emit an optimisation barrier for accesses to the current frame. */
10756 mips_frame_barrier (void)
10758 emit_clobber (gen_frame_mem (BLKmode, stack_pointer_rtx));
10762 /* The __gnu_local_gp symbol. */
10764 static GTY(()) rtx mips_gnu_local_gp;
10766 /* If we're generating n32 or n64 abicalls, emit instructions
10767 to set up the global pointer. */
10770 mips_emit_loadgp (void)
10772 rtx addr, offset, incoming_address, base, index, pic_reg;
10774 pic_reg = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
10775 switch (mips_current_loadgp_style ())
10777 case LOADGP_ABSOLUTE:
10778 if (mips_gnu_local_gp == NULL)
10780 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
10781 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
10783 emit_insn (PMODE_INSN (gen_loadgp_absolute,
10784 (pic_reg, mips_gnu_local_gp)));
10787 case LOADGP_OLDABI:
10788 /* Added by mips_output_function_prologue. */
10791 case LOADGP_NEWABI:
10792 addr = XEXP (DECL_RTL (current_function_decl), 0);
10793 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
10794 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
10795 emit_insn (PMODE_INSN (gen_loadgp_newabi,
10796 (pic_reg, offset, incoming_address)));
10800 base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE));
10801 index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX));
10802 emit_insn (PMODE_INSN (gen_loadgp_rtp, (pic_reg, base, index)));
10810 emit_insn (PMODE_INSN (gen_copygp_mips16,
10811 (pic_offset_table_rtx, pic_reg)));
10813 /* Emit a blockage if there are implicit uses of the GP register.
10814 This includes profiled functions, because FUNCTION_PROFILE uses
10816 if (!TARGET_EXPLICIT_RELOCS || crtl->profile)
10817 emit_insn (gen_loadgp_blockage ());
10820 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
10822 #if PROBE_INTERVAL > 32768
10823 #error Cannot use indexed addressing mode for stack probing
10826 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
10827 inclusive. These are offsets from the current stack pointer. */
10830 mips_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size)
10833 sorry ("-fstack-check=specific not implemented for MIPS16");
10835 /* See if we have a constant small number of probes to generate. If so,
10836 that's the easy case. */
10837 if (first + size <= 32768)
10841 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
10842 it exceeds SIZE. If only one probe is needed, this will not
10843 generate any code. Then probe at FIRST + SIZE. */
10844 for (i = PROBE_INTERVAL; i < size; i += PROBE_INTERVAL)
10845 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
10848 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
10852 /* Otherwise, do the same as above, but in a loop. Note that we must be
10853 extra careful with variables wrapping around because we might be at
10854 the very top (or the very bottom) of the address space and we have
10855 to be able to handle this case properly; in particular, we use an
10856 equality test for the loop condition. */
10859 HOST_WIDE_INT rounded_size;
10860 rtx r3 = MIPS_PROLOGUE_TEMP (Pmode);
10861 rtx r12 = MIPS_PROLOGUE_TEMP2 (Pmode);
10863 /* Sanity check for the addressing mode we're going to use. */
10864 gcc_assert (first <= 32768);
10867 /* Step 1: round SIZE to the previous multiple of the interval. */
10869 rounded_size = size & -PROBE_INTERVAL;
10872 /* Step 2: compute initial and final value of the loop counter. */
10874 /* TEST_ADDR = SP + FIRST. */
10875 emit_insn (gen_rtx_SET (VOIDmode, r3,
10876 plus_constant (Pmode, stack_pointer_rtx,
10879 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
10880 if (rounded_size > 32768)
10882 emit_move_insn (r12, GEN_INT (rounded_size));
10883 emit_insn (gen_rtx_SET (VOIDmode, r12,
10884 gen_rtx_MINUS (Pmode, r3, r12)));
10887 emit_insn (gen_rtx_SET (VOIDmode, r12,
10888 plus_constant (Pmode, r3, -rounded_size)));
10891 /* Step 3: the loop
10893 while (TEST_ADDR != LAST_ADDR)
10895 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
10899 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
10900 until it is equal to ROUNDED_SIZE. */
10902 emit_insn (PMODE_INSN (gen_probe_stack_range, (r3, r3, r12)));
10905 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
10906 that SIZE is equal to ROUNDED_SIZE. */
10908 if (size != rounded_size)
10909 emit_stack_probe (plus_constant (Pmode, r12, rounded_size - size));
10912 /* Make sure nothing is scheduled before we are done. */
10913 emit_insn (gen_blockage ());
10916 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
10917 absolute addresses. */
10920 mips_output_probe_stack_range (rtx reg1, rtx reg2)
10922 static int labelno = 0;
10923 char loop_lab[32], end_lab[32], tmp[64];
10926 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno);
10927 ASM_GENERATE_INTERNAL_LABEL (end_lab, "LPSRE", labelno++);
10929 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
10931 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
10934 strcpy (tmp, "%(%<beq\t%0,%1,");
10935 output_asm_insn (strcat (tmp, &end_lab[1]), xops);
10937 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
10938 xops[1] = GEN_INT (-PROBE_INTERVAL);
10939 if (TARGET_64BIT && TARGET_LONG64)
10940 output_asm_insn ("daddiu\t%0,%0,%1", xops);
10942 output_asm_insn ("addiu\t%0,%0,%1", xops);
10944 /* Probe at TEST_ADDR and branch. */
10945 fprintf (asm_out_file, "\tb\t");
10946 assemble_name_raw (asm_out_file, loop_lab);
10947 fputc ('\n', asm_out_file);
10949 output_asm_insn ("sd\t$0,0(%0)%)", xops);
10951 output_asm_insn ("sw\t$0,0(%0)%)", xops);
10953 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, end_lab);
10958 /* A for_each_rtx callback. Stop the search if *X is a kernel register. */
10961 mips_kernel_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
10963 return REG_P (*x) && KERNEL_REG_P (REGNO (*x));
10966 /* Expand the "prologue" pattern. */
10969 mips_expand_prologue (void)
10971 const struct mips_frame_info *frame;
10972 HOST_WIDE_INT size;
10973 unsigned int nargs;
10976 if (cfun->machine->global_pointer != INVALID_REGNUM)
10978 /* Check whether an insn uses pic_offset_table_rtx, either explicitly
10979 or implicitly. If so, we can commit to using a global pointer
10980 straight away, otherwise we need to defer the decision. */
10981 if (mips_cfun_has_inflexible_gp_ref_p ()
10982 || mips_cfun_has_flexible_gp_ref_p ())
10984 cfun->machine->must_initialize_gp_p = true;
10985 cfun->machine->must_restore_gp_when_clobbered_p = true;
10988 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
10991 frame = &cfun->machine->frame;
10992 size = frame->total_size;
10994 if (flag_stack_usage_info)
10995 current_function_static_stack_size = size;
10997 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK)
10999 if (crtl->is_leaf && !cfun->calls_alloca)
11001 if (size > PROBE_INTERVAL && size > STACK_CHECK_PROTECT)
11002 mips_emit_probe_stack_range (STACK_CHECK_PROTECT,
11003 size - STACK_CHECK_PROTECT);
11006 mips_emit_probe_stack_range (STACK_CHECK_PROTECT, size);
11009 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
11010 bytes beforehand; this is enough to cover the register save area
11011 without going out of range. */
11012 if (((frame->mask | frame->fmask | frame->acc_mask) != 0)
11013 || frame->num_cop0_regs > 0)
11015 HOST_WIDE_INT step1;
11017 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
11018 if (GENERATE_MIPS16E_SAVE_RESTORE)
11020 HOST_WIDE_INT offset;
11021 unsigned int mask, regno;
11023 /* Try to merge argument stores into the save instruction. */
11024 nargs = mips16e_collect_argument_saves ();
11026 /* Build the save instruction. */
11027 mask = frame->mask;
11028 insn = mips16e_build_save_restore (false, &mask, &offset,
11030 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
11031 mips_frame_barrier ();
11034 /* Check if we need to save other registers. */
11035 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
11036 if (BITSET_P (mask, regno - GP_REG_FIRST))
11038 offset -= UNITS_PER_WORD;
11039 mips_save_restore_reg (word_mode, regno,
11040 offset, mips_save_reg);
11045 if (cfun->machine->interrupt_handler_p)
11047 HOST_WIDE_INT offset;
11050 /* If this interrupt is using a shadow register set, we need to
11051 get the stack pointer from the previous register set. */
11052 if (cfun->machine->use_shadow_register_set_p)
11053 emit_insn (gen_mips_rdpgpr (stack_pointer_rtx,
11054 stack_pointer_rtx));
11056 if (!cfun->machine->keep_interrupts_masked_p)
11058 /* Move from COP0 Cause to K0. */
11059 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K0_REG_NUM),
11060 gen_rtx_REG (SImode,
11061 COP0_CAUSE_REG_NUM)));
11062 /* Move from COP0 EPC to K1. */
11063 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
11064 gen_rtx_REG (SImode,
11065 COP0_EPC_REG_NUM)));
11068 /* Allocate the first part of the frame. */
11069 insn = gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx,
11071 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
11072 mips_frame_barrier ();
11075 /* Start at the uppermost location for saving. */
11076 offset = frame->cop0_sp_offset - size;
11077 if (!cfun->machine->keep_interrupts_masked_p)
11079 /* Push EPC into its stack slot. */
11080 mem = gen_frame_mem (word_mode,
11081 plus_constant (Pmode, stack_pointer_rtx,
11083 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
11084 offset -= UNITS_PER_WORD;
11087 /* Move from COP0 Status to K1. */
11088 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
11089 gen_rtx_REG (SImode,
11090 COP0_STATUS_REG_NUM)));
11092 /* Right justify the RIPL in k0. */
11093 if (!cfun->machine->keep_interrupts_masked_p)
11094 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode, K0_REG_NUM),
11095 gen_rtx_REG (SImode, K0_REG_NUM),
11096 GEN_INT (CAUSE_IPL)));
11098 /* Push Status into its stack slot. */
11099 mem = gen_frame_mem (word_mode,
11100 plus_constant (Pmode, stack_pointer_rtx,
11102 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
11103 offset -= UNITS_PER_WORD;
11105 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
11106 if (!cfun->machine->keep_interrupts_masked_p)
11107 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
11110 gen_rtx_REG (SImode, K0_REG_NUM)));
11112 if (!cfun->machine->keep_interrupts_masked_p)
11113 /* Enable interrupts by clearing the KSU ERL and EXL bits.
11114 IE is already the correct value, so we don't have to do
11115 anything explicit. */
11116 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
11119 gen_rtx_REG (SImode, GP_REG_FIRST)));
11121 /* Disable interrupts by clearing the KSU, ERL, EXL,
11123 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
11126 gen_rtx_REG (SImode, GP_REG_FIRST)));
11130 insn = gen_add3_insn (stack_pointer_rtx,
11133 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
11134 mips_frame_barrier ();
11137 mips_for_each_saved_acc (size, mips_save_reg);
11138 mips_for_each_saved_gpr_and_fpr (size, mips_save_reg);
11142 /* Allocate the rest of the frame. */
11145 if (SMALL_OPERAND (-size))
11146 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
11148 GEN_INT (-size)))) = 1;
11151 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
11154 /* There are no instructions to add or subtract registers
11155 from the stack pointer, so use the frame pointer as a
11156 temporary. We should always be using a frame pointer
11157 in this case anyway. */
11158 gcc_assert (frame_pointer_needed);
11159 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
11160 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
11161 hard_frame_pointer_rtx,
11162 MIPS_PROLOGUE_TEMP (Pmode)));
11163 mips_emit_move (stack_pointer_rtx, hard_frame_pointer_rtx);
11166 emit_insn (gen_sub3_insn (stack_pointer_rtx,
11168 MIPS_PROLOGUE_TEMP (Pmode)));
11170 /* Describe the combined effect of the previous instructions. */
11171 mips_set_frame_expr
11172 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
11173 plus_constant (Pmode, stack_pointer_rtx, -size)));
11175 mips_frame_barrier ();
11178 /* Set up the frame pointer, if we're using one. */
11179 if (frame_pointer_needed)
11181 HOST_WIDE_INT offset;
11183 offset = frame->hard_frame_pointer_offset;
11186 insn = mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
11187 RTX_FRAME_RELATED_P (insn) = 1;
11189 else if (SMALL_OPERAND (offset))
11191 insn = gen_add3_insn (hard_frame_pointer_rtx,
11192 stack_pointer_rtx, GEN_INT (offset));
11193 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
11197 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (offset));
11198 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
11199 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
11200 hard_frame_pointer_rtx,
11201 MIPS_PROLOGUE_TEMP (Pmode)));
11202 mips_set_frame_expr
11203 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
11204 plus_constant (Pmode, stack_pointer_rtx, offset)));
11208 mips_emit_loadgp ();
11210 /* Initialize the $gp save slot. */
11211 if (mips_cfun_has_cprestore_slot_p ())
11213 rtx base, mem, gp, temp;
11214 HOST_WIDE_INT offset;
11216 mips_get_cprestore_base_and_offset (&base, &offset, false);
11217 mem = gen_frame_mem (Pmode, plus_constant (Pmode, base, offset));
11218 gp = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
11219 temp = (SMALL_OPERAND (offset)
11220 ? gen_rtx_SCRATCH (Pmode)
11221 : MIPS_PROLOGUE_TEMP (Pmode));
11222 emit_insn (PMODE_INSN (gen_potential_cprestore,
11223 (mem, GEN_INT (offset), gp, temp)));
11225 mips_get_cprestore_base_and_offset (&base, &offset, true);
11226 mem = gen_frame_mem (Pmode, plus_constant (Pmode, base, offset));
11227 emit_insn (PMODE_INSN (gen_use_cprestore, (mem)));
11230 /* We need to search back to the last use of K0 or K1. */
11231 if (cfun->machine->interrupt_handler_p)
11233 for (insn = get_last_insn (); insn != NULL_RTX; insn = PREV_INSN (insn))
11235 && for_each_rtx (&PATTERN (insn), mips_kernel_reg_p, NULL))
11237 /* Emit a move from K1 to COP0 Status after insn. */
11238 gcc_assert (insn != NULL_RTX);
11239 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
11240 gen_rtx_REG (SImode, K1_REG_NUM)),
11244 /* If we are profiling, make sure no instructions are scheduled before
11245 the call to mcount. */
11247 emit_insn (gen_blockage ());
11250 /* Attach all pending register saves to the previous instruction.
11251 Return that instruction. */
11254 mips_epilogue_emit_cfa_restores (void)
11258 insn = get_last_insn ();
11259 gcc_assert (insn && !REG_NOTES (insn));
11260 if (mips_epilogue.cfa_restores)
11262 RTX_FRAME_RELATED_P (insn) = 1;
11263 REG_NOTES (insn) = mips_epilogue.cfa_restores;
11264 mips_epilogue.cfa_restores = 0;
11269 /* Like mips_epilogue_emit_cfa_restores, but also record that the CFA is
11270 now at REG + OFFSET. */
11273 mips_epilogue_set_cfa (rtx reg, HOST_WIDE_INT offset)
11277 insn = mips_epilogue_emit_cfa_restores ();
11278 if (reg != mips_epilogue.cfa_reg || offset != mips_epilogue.cfa_offset)
11280 RTX_FRAME_RELATED_P (insn) = 1;
11281 REG_NOTES (insn) = alloc_reg_note (REG_CFA_DEF_CFA,
11282 plus_constant (Pmode, reg, offset),
11284 mips_epilogue.cfa_reg = reg;
11285 mips_epilogue.cfa_offset = offset;
11289 /* Emit instructions to restore register REG from slot MEM. Also update
11290 the cfa_restores list. */
11293 mips_restore_reg (rtx reg, rtx mem)
11295 /* There's no MIPS16 instruction to load $31 directly. Load into
11296 $7 instead and adjust the return insn appropriately. */
11297 if (TARGET_MIPS16 && REGNO (reg) == RETURN_ADDR_REGNUM)
11298 reg = gen_rtx_REG (GET_MODE (reg), GP_REG_FIRST + 7);
11299 else if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
11301 mips_add_cfa_restore (mips_subword (reg, true));
11302 mips_add_cfa_restore (mips_subword (reg, false));
11305 mips_add_cfa_restore (reg);
11307 mips_emit_save_slot_move (reg, mem, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
11308 if (REGNO (reg) == REGNO (mips_epilogue.cfa_reg))
11309 /* The CFA is currently defined in terms of the register whose
11310 value we have just restored. Redefine the CFA in terms of
11311 the stack pointer. */
11312 mips_epilogue_set_cfa (stack_pointer_rtx,
11313 mips_epilogue.cfa_restore_sp_offset);
11316 /* Emit code to set the stack pointer to BASE + OFFSET, given that
11317 BASE + OFFSET is NEW_FRAME_SIZE bytes below the top of the frame.
11318 BASE, if not the stack pointer, is available as a temporary. */
11321 mips_deallocate_stack (rtx base, rtx offset, HOST_WIDE_INT new_frame_size)
11323 if (base == stack_pointer_rtx && offset == const0_rtx)
11326 mips_frame_barrier ();
11327 if (offset == const0_rtx)
11329 emit_move_insn (stack_pointer_rtx, base);
11330 mips_epilogue_set_cfa (stack_pointer_rtx, new_frame_size);
11332 else if (TARGET_MIPS16 && base != stack_pointer_rtx)
11334 emit_insn (gen_add3_insn (base, base, offset));
11335 mips_epilogue_set_cfa (base, new_frame_size);
11336 emit_move_insn (stack_pointer_rtx, base);
11340 emit_insn (gen_add3_insn (stack_pointer_rtx, base, offset));
11341 mips_epilogue_set_cfa (stack_pointer_rtx, new_frame_size);
11345 /* Emit any instructions needed before a return. */
11348 mips_expand_before_return (void)
11350 /* When using a call-clobbered gp, we start out with unified call
11351 insns that include instructions to restore the gp. We then split
11352 these unified calls after reload. These split calls explicitly
11353 clobber gp, so there is no need to define
11354 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
11356 For consistency, we should also insert an explicit clobber of $28
11357 before return insns, so that the post-reload optimizers know that
11358 the register is not live on exit. */
11359 if (TARGET_CALL_CLOBBERED_GP)
11360 emit_clobber (pic_offset_table_rtx);
11363 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
11367 mips_expand_epilogue (bool sibcall_p)
11369 const struct mips_frame_info *frame;
11370 HOST_WIDE_INT step1, step2;
11371 rtx base, adjust, insn;
11372 bool use_jraddiusp_p = false;
11374 if (!sibcall_p && mips_can_use_return_insn ())
11376 emit_jump_insn (gen_return ());
11380 /* In MIPS16 mode, if the return value should go into a floating-point
11381 register, we need to call a helper routine to copy it over. */
11382 if (mips16_cfun_returns_in_fpr_p ())
11383 mips16_copy_fpr_return_value ();
11385 /* Split the frame into two. STEP1 is the amount of stack we should
11386 deallocate before restoring the registers. STEP2 is the amount we
11387 should deallocate afterwards.
11389 Start off by assuming that no registers need to be restored. */
11390 frame = &cfun->machine->frame;
11391 step1 = frame->total_size;
11394 /* Work out which register holds the frame address. */
11395 if (!frame_pointer_needed)
11396 base = stack_pointer_rtx;
11399 base = hard_frame_pointer_rtx;
11400 step1 -= frame->hard_frame_pointer_offset;
11402 mips_epilogue.cfa_reg = base;
11403 mips_epilogue.cfa_offset = step1;
11404 mips_epilogue.cfa_restores = NULL_RTX;
11406 /* If we need to restore registers, deallocate as much stack as
11407 possible in the second step without going out of range. */
11408 if ((frame->mask | frame->fmask | frame->acc_mask) != 0
11409 || frame->num_cop0_regs > 0)
11411 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
11415 /* Get an rtx for STEP1 that we can add to BASE. */
11416 adjust = GEN_INT (step1);
11417 if (!SMALL_OPERAND (step1))
11419 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), adjust);
11420 adjust = MIPS_EPILOGUE_TEMP (Pmode);
11422 mips_deallocate_stack (base, adjust, step2);
11424 /* If we're using addressing macros, $gp is implicitly used by all
11425 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
11427 if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS)
11428 emit_insn (gen_blockage ());
11430 mips_epilogue.cfa_restore_sp_offset = step2;
11431 if (GENERATE_MIPS16E_SAVE_RESTORE && frame->mask != 0)
11433 unsigned int regno, mask;
11434 HOST_WIDE_INT offset;
11437 /* Generate the restore instruction. */
11438 mask = frame->mask;
11439 restore = mips16e_build_save_restore (true, &mask, &offset, 0, step2);
11441 /* Restore any other registers manually. */
11442 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
11443 if (BITSET_P (mask, regno - GP_REG_FIRST))
11445 offset -= UNITS_PER_WORD;
11446 mips_save_restore_reg (word_mode, regno, offset, mips_restore_reg);
11449 /* Restore the remaining registers and deallocate the final bit
11451 mips_frame_barrier ();
11452 emit_insn (restore);
11453 mips_epilogue_set_cfa (stack_pointer_rtx, 0);
11457 /* Restore the registers. */
11458 mips_for_each_saved_acc (frame->total_size - step2, mips_restore_reg);
11459 mips_for_each_saved_gpr_and_fpr (frame->total_size - step2,
11462 if (cfun->machine->interrupt_handler_p)
11464 HOST_WIDE_INT offset;
11467 offset = frame->cop0_sp_offset - (frame->total_size - step2);
11468 if (!cfun->machine->keep_interrupts_masked_p)
11470 /* Restore the original EPC. */
11471 mem = gen_frame_mem (word_mode,
11472 plus_constant (Pmode, stack_pointer_rtx,
11474 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
11475 offset -= UNITS_PER_WORD;
11477 /* Move to COP0 EPC. */
11478 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_EPC_REG_NUM),
11479 gen_rtx_REG (SImode, K0_REG_NUM)));
11482 /* Restore the original Status. */
11483 mem = gen_frame_mem (word_mode,
11484 plus_constant (Pmode, stack_pointer_rtx,
11486 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
11487 offset -= UNITS_PER_WORD;
11489 /* If we don't use shadow register set, we need to update SP. */
11490 if (!cfun->machine->use_shadow_register_set_p)
11491 mips_deallocate_stack (stack_pointer_rtx, GEN_INT (step2), 0);
11493 /* The choice of position is somewhat arbitrary in this case. */
11494 mips_epilogue_emit_cfa_restores ();
11496 /* Move to COP0 Status. */
11497 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
11498 gen_rtx_REG (SImode, K0_REG_NUM)));
11500 else if (TARGET_MICROMIPS
11501 && !crtl->calls_eh_return
11504 && mips_unsigned_immediate_p (step2, 5, 2))
11505 use_jraddiusp_p = true;
11507 /* Deallocate the final bit of the frame. */
11508 mips_deallocate_stack (stack_pointer_rtx, GEN_INT (step2), 0);
11511 if (!use_jraddiusp_p)
11512 gcc_assert (!mips_epilogue.cfa_restores);
11514 /* Add in the __builtin_eh_return stack adjustment. We need to
11515 use a temporary in MIPS16 code. */
11516 if (crtl->calls_eh_return)
11520 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
11521 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
11522 MIPS_EPILOGUE_TEMP (Pmode),
11523 EH_RETURN_STACKADJ_RTX));
11524 mips_emit_move (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
11527 emit_insn (gen_add3_insn (stack_pointer_rtx,
11529 EH_RETURN_STACKADJ_RTX));
11534 mips_expand_before_return ();
11535 if (cfun->machine->interrupt_handler_p)
11537 /* Interrupt handlers generate eret or deret. */
11538 if (cfun->machine->use_debug_exception_return_p)
11539 emit_jump_insn (gen_mips_deret ());
11541 emit_jump_insn (gen_mips_eret ());
11547 /* When generating MIPS16 code, the normal
11548 mips_for_each_saved_gpr_and_fpr path will restore the return
11549 address into $7 rather than $31. */
11551 && !GENERATE_MIPS16E_SAVE_RESTORE
11552 && BITSET_P (frame->mask, RETURN_ADDR_REGNUM))
11554 /* simple_returns cannot rely on values that are only available
11555 on paths through the epilogue (because return paths that do
11556 not pass through the epilogue may nevertheless reuse a
11557 simple_return that occurs at the end of the epilogue).
11558 Use a normal return here instead. */
11559 rtx reg = gen_rtx_REG (Pmode, GP_REG_FIRST + 7);
11560 pat = gen_return_internal (reg);
11562 else if (use_jraddiusp_p)
11563 pat = gen_jraddiusp (GEN_INT (step2));
11566 rtx reg = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
11567 pat = gen_simple_return_internal (reg);
11569 emit_jump_insn (pat);
11570 if (use_jraddiusp_p)
11571 mips_epilogue_set_cfa (stack_pointer_rtx, step2);
11575 /* Search from the beginning to the first use of K0 or K1. */
11576 if (cfun->machine->interrupt_handler_p
11577 && !cfun->machine->keep_interrupts_masked_p)
11579 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
11581 && for_each_rtx (&PATTERN(insn), mips_kernel_reg_p, NULL))
11583 gcc_assert (insn != NULL_RTX);
11584 /* Insert disable interrupts before the first use of K0 or K1. */
11585 emit_insn_before (gen_mips_di (), insn);
11586 emit_insn_before (gen_mips_ehb (), insn);
11590 /* Return nonzero if this function is known to have a null epilogue.
11591 This allows the optimizer to omit jumps to jumps if no stack
11595 mips_can_use_return_insn (void)
11597 /* Interrupt handlers need to go through the epilogue. */
11598 if (cfun->machine->interrupt_handler_p)
11601 if (!reload_completed)
11607 /* In MIPS16 mode, a function that returns a floating-point value
11608 needs to arrange to copy the return value into the floating-point
11610 if (mips16_cfun_returns_in_fpr_p ())
11613 return cfun->machine->frame.total_size == 0;
11616 /* Return true if register REGNO can store a value of mode MODE.
11617 The result of this function is cached in mips_hard_regno_mode_ok. */
11620 mips_hard_regno_mode_ok_p (unsigned int regno, enum machine_mode mode)
11623 enum mode_class mclass;
11625 if (mode == CCV2mode)
11626 return (ISA_HAS_8CC
11627 && ST_REG_P (regno)
11628 && (regno - ST_REG_FIRST) % 2 == 0);
11630 if (mode == CCV4mode)
11631 return (ISA_HAS_8CC
11632 && ST_REG_P (regno)
11633 && (regno - ST_REG_FIRST) % 4 == 0);
11635 if (mode == CCmode)
11636 return ISA_HAS_8CC ? ST_REG_P (regno) : regno == FPSW_REGNUM;
11638 size = GET_MODE_SIZE (mode);
11639 mclass = GET_MODE_CLASS (mode);
11641 if (GP_REG_P (regno))
11642 return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD;
11644 if (FP_REG_P (regno)
11645 && (((regno - FP_REG_FIRST) % MAX_FPRS_PER_FMT) == 0
11646 || (MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG)))
11648 /* Allow 64-bit vector modes for Loongson-2E/2F. */
11649 if (TARGET_LOONGSON_VECTORS
11650 && (mode == V2SImode
11651 || mode == V4HImode
11652 || mode == V8QImode
11653 || mode == DImode))
11656 if (mclass == MODE_FLOAT
11657 || mclass == MODE_COMPLEX_FLOAT
11658 || mclass == MODE_VECTOR_FLOAT)
11659 return size <= UNITS_PER_FPVALUE;
11661 /* Allow integer modes that fit into a single register. We need
11662 to put integers into FPRs when using instructions like CVT
11663 and TRUNC. There's no point allowing sizes smaller than a word,
11664 because the FPU has no appropriate load/store instructions. */
11665 if (mclass == MODE_INT)
11666 return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG;
11669 if (ACC_REG_P (regno)
11670 && (INTEGRAL_MODE_P (mode) || ALL_FIXED_POINT_MODE_P (mode)))
11672 if (MD_REG_P (regno))
11674 /* After a multiplication or division, clobbering HI makes
11675 the value of LO unpredictable, and vice versa. This means
11676 that, for all interesting cases, HI and LO are effectively
11679 We model this by requiring that any value that uses HI
11681 if (size <= UNITS_PER_WORD * 2)
11682 return regno == (size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST);
11686 /* DSP accumulators do not have the same restrictions as
11687 HI and LO, so we can treat them as normal doubleword
11689 if (size <= UNITS_PER_WORD)
11692 if (size <= UNITS_PER_WORD * 2
11693 && ((regno - DSP_ACC_REG_FIRST) & 1) == 0)
11698 if (ALL_COP_REG_P (regno))
11699 return mclass == MODE_INT && size <= UNITS_PER_WORD;
11701 if (regno == GOT_VERSION_REGNUM)
11702 return mode == SImode;
11707 /* Implement HARD_REGNO_NREGS. */
11710 mips_hard_regno_nregs (int regno, enum machine_mode mode)
11712 if (ST_REG_P (regno))
11713 /* The size of FP status registers is always 4, because they only hold
11714 CCmode values, and CCmode is always considered to be 4 bytes wide. */
11715 return (GET_MODE_SIZE (mode) + 3) / 4;
11717 if (FP_REG_P (regno))
11718 return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG;
11720 /* All other registers are word-sized. */
11721 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
11724 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
11725 in mips_hard_regno_nregs. */
11728 mips_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
11734 COPY_HARD_REG_SET (left, reg_class_contents[(int) rclass]);
11735 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS]))
11737 if (HARD_REGNO_MODE_OK (ST_REG_FIRST, mode))
11738 size = MIN (size, 4);
11739 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) ST_REGS]);
11741 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS]))
11743 if (HARD_REGNO_MODE_OK (FP_REG_FIRST, mode))
11744 size = MIN (size, UNITS_PER_FPREG);
11745 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]);
11747 if (!hard_reg_set_empty_p (left))
11748 size = MIN (size, UNITS_PER_WORD);
11749 return (GET_MODE_SIZE (mode) + size - 1) / size;
11752 /* Implement CANNOT_CHANGE_MODE_CLASS. */
11755 mips_cannot_change_mode_class (enum machine_mode from,
11756 enum machine_mode to,
11757 enum reg_class rclass)
11759 /* Allow conversions between different Loongson integer vectors,
11760 and between those vectors and DImode. */
11761 if (GET_MODE_SIZE (from) == 8 && GET_MODE_SIZE (to) == 8
11762 && INTEGRAL_MODE_P (from) && INTEGRAL_MODE_P (to))
11765 /* Otherwise, there are several problems with changing the modes of
11766 values in floating-point registers:
11768 - When a multi-word value is stored in paired floating-point
11769 registers, the first register always holds the low word. We
11770 therefore can't allow FPRs to change between single-word and
11771 multi-word modes on big-endian targets.
11773 - GCC assumes that each word of a multiword register can be
11774 accessed individually using SUBREGs. This is not true for
11775 floating-point registers if they are bigger than a word.
11777 - Loading a 32-bit value into a 64-bit floating-point register
11778 will not sign-extend the value, despite what LOAD_EXTEND_OP
11779 says. We can't allow FPRs to change from SImode to a wider
11780 mode on 64-bit targets.
11782 - If the FPU has already interpreted a value in one format, we
11783 must not ask it to treat the value as having a different
11786 We therefore disallow all mode changes involving FPRs. */
11788 return reg_classes_intersect_p (FP_REGS, rclass);
11791 /* Implement target hook small_register_classes_for_mode_p. */
11794 mips_small_register_classes_for_mode_p (enum machine_mode mode
11797 return TARGET_MIPS16;
11800 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
11803 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode)
11808 return TARGET_HARD_FLOAT;
11811 return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT;
11814 return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT;
11821 /* Implement MODES_TIEABLE_P. */
11824 mips_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
11826 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
11827 prefer to put one of them in FPRs. */
11828 return (mode1 == mode2
11829 || (!mips_mode_ok_for_mov_fmt_p (mode1)
11830 && !mips_mode_ok_for_mov_fmt_p (mode2)));
11833 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
11836 mips_preferred_reload_class (rtx x, reg_class_t rclass)
11838 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, rclass))
11841 if (reg_class_subset_p (FP_REGS, rclass)
11842 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x)))
11845 if (reg_class_subset_p (GR_REGS, rclass))
11848 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, rclass))
11854 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
11855 Return a "canonical" class to represent it in later calculations. */
11858 mips_canonicalize_move_class (reg_class_t rclass)
11860 /* All moves involving accumulator registers have the same cost. */
11861 if (reg_class_subset_p (rclass, ACC_REGS))
11864 /* Likewise promote subclasses of general registers to the most
11865 interesting containing class. */
11866 if (TARGET_MIPS16 && reg_class_subset_p (rclass, M16_REGS))
11868 else if (reg_class_subset_p (rclass, GENERAL_REGS))
11869 rclass = GENERAL_REGS;
11874 /* Return the cost of moving a value of mode MODE from a register of
11875 class FROM to a GPR. Return 0 for classes that are unions of other
11876 classes handled by this function. */
11879 mips_move_to_gpr_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
11885 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
11889 /* MFLO and MFHI. */
11897 /* LUI followed by MOVF. */
11903 /* This choice of value is historical. */
11911 /* Return the cost of moving a value of mode MODE from a GPR to a
11912 register of class TO. Return 0 for classes that are unions of
11913 other classes handled by this function. */
11916 mips_move_from_gpr_cost (enum machine_mode mode, reg_class_t to)
11921 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
11925 /* MTLO and MTHI. */
11933 /* A secondary reload through an FPR scratch. */
11934 return (mips_register_move_cost (mode, GENERAL_REGS, FP_REGS)
11935 + mips_register_move_cost (mode, FP_REGS, ST_REGS));
11940 /* This choice of value is historical. */
11948 /* Implement TARGET_REGISTER_MOVE_COST. Return 0 for classes that are the
11949 maximum of the move costs for subclasses; regclass will work out
11950 the maximum for us. */
11953 mips_register_move_cost (enum machine_mode mode,
11954 reg_class_t from, reg_class_t to)
11959 from = mips_canonicalize_move_class (from);
11960 to = mips_canonicalize_move_class (to);
11962 /* Handle moves that can be done without using general-purpose registers. */
11963 if (from == FP_REGS)
11965 if (to == FP_REGS && mips_mode_ok_for_mov_fmt_p (mode))
11969 /* The sequence generated by mips_expand_fcc_reload. */
11973 /* Handle cases in which only one class deviates from the ideal. */
11974 dregs = TARGET_MIPS16 ? M16_REGS : GENERAL_REGS;
11976 return mips_move_from_gpr_cost (mode, to);
11978 return mips_move_to_gpr_cost (mode, from);
11980 /* Handles cases that require a GPR temporary. */
11981 cost1 = mips_move_to_gpr_cost (mode, from);
11984 cost2 = mips_move_from_gpr_cost (mode, to);
11986 return cost1 + cost2;
11992 /* Implement TARGET_MEMORY_MOVE_COST. */
11995 mips_memory_move_cost (enum machine_mode mode, reg_class_t rclass, bool in)
11997 return (mips_cost->memory_latency
11998 + memory_move_secondary_cost (mode, rclass, in));
12001 /* Return the register class required for a secondary register when
12002 copying between one of the registers in RCLASS and value X, which
12003 has mode MODE. X is the source of the move if IN_P, otherwise it
12004 is the destination. Return NO_REGS if no secondary register is
12008 mips_secondary_reload_class (enum reg_class rclass,
12009 enum machine_mode mode, rtx x, bool in_p)
12013 /* If X is a constant that cannot be loaded into $25, it must be loaded
12014 into some other GPR. No other register class allows a direct move. */
12015 if (mips_dangerous_for_la25_p (x))
12016 return reg_class_subset_p (rclass, LEA_REGS) ? NO_REGS : LEA_REGS;
12018 regno = true_regnum (x);
12021 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
12022 if (!reg_class_subset_p (rclass, M16_REGS) && !M16_REG_P (regno))
12028 /* Copying from accumulator registers to anywhere other than a general
12029 register requires a temporary general register. */
12030 if (reg_class_subset_p (rclass, ACC_REGS))
12031 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
12032 if (ACC_REG_P (regno))
12033 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
12035 /* We can only copy a value to a condition code register from a
12036 floating-point register, and even then we require a scratch
12037 floating-point register. We can only copy a value out of a
12038 condition-code register into a general register. */
12039 if (reg_class_subset_p (rclass, ST_REGS))
12043 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
12045 if (ST_REG_P (regno))
12049 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
12052 if (reg_class_subset_p (rclass, FP_REGS))
12055 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8))
12056 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
12057 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
12060 if (GP_REG_P (regno) || x == CONST0_RTX (mode))
12061 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
12064 if (CONSTANT_P (x) && !targetm.cannot_force_const_mem (mode, x))
12065 /* We can force the constant to memory and use lwc1
12066 and ldc1. As above, we will use pairs of lwc1s if
12067 ldc1 is not supported. */
12070 if (FP_REG_P (regno) && mips_mode_ok_for_mov_fmt_p (mode))
12071 /* In this case we can use mov.fmt. */
12074 /* Otherwise, we need to reload through an integer register. */
12077 if (FP_REG_P (regno))
12078 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
12083 /* Implement TARGET_MODE_REP_EXTENDED. */
12086 mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
12088 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
12089 if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
12090 return SIGN_EXTEND;
12095 /* Implement TARGET_VALID_POINTER_MODE. */
12098 mips_valid_pointer_mode (enum machine_mode mode)
12100 return mode == SImode || (TARGET_64BIT && mode == DImode);
12103 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
12106 mips_vector_mode_supported_p (enum machine_mode mode)
12111 return TARGET_PAIRED_SINGLE_FLOAT;
12126 return TARGET_LOONGSON_VECTORS;
12133 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
12136 mips_scalar_mode_supported_p (enum machine_mode mode)
12138 if (ALL_FIXED_POINT_MODE_P (mode)
12139 && GET_MODE_PRECISION (mode) <= 2 * BITS_PER_WORD)
12142 return default_scalar_mode_supported_p (mode);
12145 /* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
12147 static enum machine_mode
12148 mips_preferred_simd_mode (enum machine_mode mode ATTRIBUTE_UNUSED)
12150 if (TARGET_PAIRED_SINGLE_FLOAT
12156 /* Implement TARGET_INIT_LIBFUNCS. */
12159 mips_init_libfuncs (void)
12161 if (TARGET_FIX_VR4120)
12163 /* Register the special divsi3 and modsi3 functions needed to work
12164 around VR4120 division errata. */
12165 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
12166 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
12169 if (TARGET_MIPS16 && TARGET_HARD_FLOAT_ABI)
12171 /* Register the MIPS16 -mhard-float stubs. */
12172 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
12173 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
12174 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
12175 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
12177 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
12178 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
12179 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
12180 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
12181 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
12182 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
12183 set_optab_libfunc (unord_optab, SFmode, "__mips16_unordsf2");
12185 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
12186 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
12187 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__mips16_floatunsisf");
12189 if (TARGET_DOUBLE_FLOAT)
12191 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
12192 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
12193 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
12194 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
12196 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
12197 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
12198 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
12199 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
12200 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
12201 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
12202 set_optab_libfunc (unord_optab, DFmode, "__mips16_unorddf2");
12204 set_conv_libfunc (sext_optab, DFmode, SFmode,
12205 "__mips16_extendsfdf2");
12206 set_conv_libfunc (trunc_optab, SFmode, DFmode,
12207 "__mips16_truncdfsf2");
12208 set_conv_libfunc (sfix_optab, SImode, DFmode,
12209 "__mips16_fix_truncdfsi");
12210 set_conv_libfunc (sfloat_optab, DFmode, SImode,
12211 "__mips16_floatsidf");
12212 set_conv_libfunc (ufloat_optab, DFmode, SImode,
12213 "__mips16_floatunsidf");
12217 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
12218 on an external non-MIPS16 routine to implement __sync_synchronize.
12219 Similarly for the rest of the ll/sc libfuncs. */
12222 synchronize_libfunc = init_one_libfunc ("__sync_synchronize");
12223 init_sync_libfuncs (UNITS_PER_WORD);
12227 /* Build up a multi-insn sequence that loads label TARGET into $AT. */
12230 mips_process_load_label (rtx target)
12232 rtx base, gp, intop;
12233 HOST_WIDE_INT offset;
12235 mips_multi_start ();
12239 mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target, 0);
12240 mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target, 0);
12244 mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target, 0);
12245 mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target, 0);
12249 gp = pic_offset_table_rtx;
12250 if (mips_cfun_has_cprestore_slot_p ())
12252 gp = gen_rtx_REG (Pmode, AT_REGNUM);
12253 mips_get_cprestore_base_and_offset (&base, &offset, true);
12254 if (!SMALL_OPERAND (offset))
12256 intop = GEN_INT (CONST_HIGH_PART (offset));
12257 mips_multi_add_insn ("lui\t%0,%1", gp, intop, 0);
12258 mips_multi_add_insn ("addu\t%0,%0,%1", gp, base, 0);
12261 offset = CONST_LOW_PART (offset);
12263 intop = GEN_INT (offset);
12264 if (ISA_HAS_LOAD_DELAY)
12265 mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp, intop, base, 0);
12267 mips_multi_add_insn ("lw\t%0,%1(%2)", gp, intop, base, 0);
12269 if (ISA_HAS_LOAD_DELAY)
12270 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target, gp, 0);
12272 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target, gp, 0);
12273 mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target, 0);
12278 /* Return the number of instructions needed to load a label into $AT. */
12280 static unsigned int
12281 mips_load_label_num_insns (void)
12283 if (cfun->machine->load_label_num_insns == 0)
12285 mips_process_load_label (pc_rtx);
12286 cfun->machine->load_label_num_insns = mips_multi_num_insns;
12288 return cfun->machine->load_label_num_insns;
12291 /* Emit an asm sequence to start a noat block and load the address
12292 of a label into $1. */
12295 mips_output_load_label (rtx target)
12297 mips_push_asm_switch (&mips_noat);
12298 if (TARGET_EXPLICIT_RELOCS)
12300 mips_process_load_label (target);
12301 mips_multi_write ();
12305 if (Pmode == DImode)
12306 output_asm_insn ("dla\t%@,%0", &target);
12308 output_asm_insn ("la\t%@,%0", &target);
12312 /* Return the length of INSN. LENGTH is the initial length computed by
12313 attributes in the machine-description file. */
12316 mips_adjust_insn_length (rtx insn, int length)
12318 /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length
12319 of a PIC long-branch sequence. Substitute the correct value. */
12320 if (length == MAX_PIC_BRANCH_LENGTH
12322 && INSN_CODE (insn) >= 0
12323 && get_attr_type (insn) == TYPE_BRANCH)
12325 /* Add the branch-over instruction and its delay slot, if this
12326 is a conditional branch. */
12327 length = simplejump_p (insn) ? 0 : 8;
12329 /* Add the size of a load into $AT. */
12330 length += BASE_INSN_LENGTH * mips_load_label_num_insns ();
12332 /* Add the length of an indirect jump, ignoring the delay slot. */
12333 length += TARGET_COMPRESSION ? 2 : 4;
12336 /* A unconditional jump has an unfilled delay slot if it is not part
12337 of a sequence. A conditional jump normally has a delay slot, but
12338 does not on MIPS16. */
12339 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
12340 length += TARGET_MIPS16 ? 2 : 4;
12342 /* See how many nops might be needed to avoid hardware hazards. */
12343 if (!cfun->machine->ignore_hazard_length_p
12345 && INSN_CODE (insn) >= 0)
12346 switch (get_attr_hazard (insn))
12352 length += NOP_INSN_LENGTH;
12356 length += NOP_INSN_LENGTH * 2;
12363 /* Return the assembly code for INSN, which has the operands given by
12364 OPERANDS, and which branches to OPERANDS[0] if some condition is true.
12365 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0]
12366 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
12367 version of BRANCH_IF_TRUE. */
12370 mips_output_conditional_branch (rtx insn, rtx *operands,
12371 const char *branch_if_true,
12372 const char *branch_if_false)
12374 unsigned int length;
12375 rtx taken, not_taken;
12377 gcc_assert (LABEL_P (operands[0]));
12379 length = get_attr_length (insn);
12382 /* Just a simple conditional branch. */
12383 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
12384 return branch_if_true;
12387 /* Generate a reversed branch around a direct jump. This fallback does
12388 not use branch-likely instructions. */
12389 mips_branch_likely = false;
12390 not_taken = gen_label_rtx ();
12391 taken = operands[0];
12393 /* Generate the reversed branch to NOT_TAKEN. */
12394 operands[0] = not_taken;
12395 output_asm_insn (branch_if_false, operands);
12397 /* If INSN has a delay slot, we must provide delay slots for both the
12398 branch to NOT_TAKEN and the conditional jump. We must also ensure
12399 that INSN's delay slot is executed in the appropriate cases. */
12400 if (final_sequence)
12402 /* This first delay slot will always be executed, so use INSN's
12403 delay slot if is not annulled. */
12404 if (!INSN_ANNULLED_BRANCH_P (insn))
12406 final_scan_insn (XVECEXP (final_sequence, 0, 1),
12407 asm_out_file, optimize, 1, NULL);
12408 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
12411 output_asm_insn ("nop", 0);
12412 fprintf (asm_out_file, "\n");
12415 /* Output the unconditional branch to TAKEN. */
12416 if (TARGET_ABSOLUTE_JUMPS)
12417 output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken);
12420 mips_output_load_label (taken);
12421 output_asm_insn ("jr\t%@%]%/", 0);
12424 /* Now deal with its delay slot; see above. */
12425 if (final_sequence)
12427 /* This delay slot will only be executed if the branch is taken.
12428 Use INSN's delay slot if is annulled. */
12429 if (INSN_ANNULLED_BRANCH_P (insn))
12431 final_scan_insn (XVECEXP (final_sequence, 0, 1),
12432 asm_out_file, optimize, 1, NULL);
12433 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
12436 output_asm_insn ("nop", 0);
12437 fprintf (asm_out_file, "\n");
12440 /* Output NOT_TAKEN. */
12441 targetm.asm_out.internal_label (asm_out_file, "L",
12442 CODE_LABEL_NUMBER (not_taken));
12446 /* Return the assembly code for INSN, which branches to OPERANDS[0]
12447 if some ordering condition is true. The condition is given by
12448 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
12449 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
12450 its second is always zero. */
12453 mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
12455 const char *branch[2];
12457 /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true.
12458 Make BRANCH[0] branch on the inverse condition. */
12459 switch (GET_CODE (operands[1]))
12461 /* These cases are equivalent to comparisons against zero. */
12463 inverted_p = !inverted_p;
12464 /* Fall through. */
12466 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%0");
12467 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%0");
12470 /* These cases are always true or always false. */
12472 inverted_p = !inverted_p;
12473 /* Fall through. */
12475 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%0");
12476 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%0");
12480 branch[!inverted_p] = MIPS_BRANCH ("b%C1z", "%2,%0");
12481 branch[inverted_p] = MIPS_BRANCH ("b%N1z", "%2,%0");
12484 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
12487 /* Start a block of code that needs access to the LL, SC and SYNC
12491 mips_start_ll_sc_sync_block (void)
12493 if (!ISA_HAS_LL_SC)
12495 output_asm_insn (".set\tpush", 0);
12497 output_asm_insn (".set\tmips3", 0);
12499 output_asm_insn (".set\tmips2", 0);
12503 /* End a block started by mips_start_ll_sc_sync_block. */
12506 mips_end_ll_sc_sync_block (void)
12508 if (!ISA_HAS_LL_SC)
12509 output_asm_insn (".set\tpop", 0);
12512 /* Output and/or return the asm template for a sync instruction. */
12515 mips_output_sync (void)
12517 mips_start_ll_sc_sync_block ();
12518 output_asm_insn ("sync", 0);
12519 mips_end_ll_sc_sync_block ();
12523 /* Return the asm template associated with sync_insn1 value TYPE.
12524 IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */
12526 static const char *
12527 mips_sync_insn1_template (enum attr_sync_insn1 type, bool is_64bit_p)
12531 case SYNC_INSN1_MOVE:
12532 return "move\t%0,%z2";
12533 case SYNC_INSN1_LI:
12534 return "li\t%0,%2";
12535 case SYNC_INSN1_ADDU:
12536 return is_64bit_p ? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2";
12537 case SYNC_INSN1_ADDIU:
12538 return is_64bit_p ? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2";
12539 case SYNC_INSN1_SUBU:
12540 return is_64bit_p ? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2";
12541 case SYNC_INSN1_AND:
12542 return "and\t%0,%1,%z2";
12543 case SYNC_INSN1_ANDI:
12544 return "andi\t%0,%1,%2";
12545 case SYNC_INSN1_OR:
12546 return "or\t%0,%1,%z2";
12547 case SYNC_INSN1_ORI:
12548 return "ori\t%0,%1,%2";
12549 case SYNC_INSN1_XOR:
12550 return "xor\t%0,%1,%z2";
12551 case SYNC_INSN1_XORI:
12552 return "xori\t%0,%1,%2";
12554 gcc_unreachable ();
12557 /* Return the asm template associated with sync_insn2 value TYPE. */
12559 static const char *
12560 mips_sync_insn2_template (enum attr_sync_insn2 type)
12564 case SYNC_INSN2_NOP:
12565 gcc_unreachable ();
12566 case SYNC_INSN2_AND:
12567 return "and\t%0,%1,%z2";
12568 case SYNC_INSN2_XOR:
12569 return "xor\t%0,%1,%z2";
12570 case SYNC_INSN2_NOT:
12571 return "nor\t%0,%1,%.";
12573 gcc_unreachable ();
12576 /* OPERANDS are the operands to a sync loop instruction and INDEX is
12577 the value of the one of the sync_* attributes. Return the operand
12578 referred to by the attribute, or DEFAULT_VALUE if the insn doesn't
12579 have the associated attribute. */
12582 mips_get_sync_operand (rtx *operands, int index, rtx default_value)
12585 default_value = operands[index - 1];
12586 return default_value;
12589 /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn
12590 sequence for it. */
12593 mips_process_sync_loop (rtx insn, rtx *operands)
12595 rtx at, mem, oldval, newval, inclusive_mask, exclusive_mask;
12596 rtx required_oldval, insn1_op2, tmp1, tmp2, tmp3, cmp;
12597 unsigned int tmp3_insn;
12598 enum attr_sync_insn1 insn1;
12599 enum attr_sync_insn2 insn2;
12602 enum memmodel model;
12604 /* Read an operand from the sync_WHAT attribute and store it in
12605 variable WHAT. DEFAULT is the default value if no attribute
12607 #define READ_OPERAND(WHAT, DEFAULT) \
12608 WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \
12611 /* Read the memory. */
12612 READ_OPERAND (mem, 0);
12614 is_64bit_p = (GET_MODE_BITSIZE (GET_MODE (mem)) == 64);
12616 /* Read the other attributes. */
12617 at = gen_rtx_REG (GET_MODE (mem), AT_REGNUM);
12618 READ_OPERAND (oldval, at);
12619 READ_OPERAND (cmp, 0);
12620 READ_OPERAND (newval, at);
12621 READ_OPERAND (inclusive_mask, 0);
12622 READ_OPERAND (exclusive_mask, 0);
12623 READ_OPERAND (required_oldval, 0);
12624 READ_OPERAND (insn1_op2, 0);
12625 insn1 = get_attr_sync_insn1 (insn);
12626 insn2 = get_attr_sync_insn2 (insn);
12628 /* Don't bother setting CMP result that is never used. */
12629 if (cmp && find_reg_note (insn, REG_UNUSED, cmp))
12632 memmodel_attr = get_attr_sync_memmodel (insn);
12633 switch (memmodel_attr)
12636 model = MEMMODEL_ACQ_REL;
12639 model = MEMMODEL_ACQUIRE;
12642 model = (enum memmodel) INTVAL (operands[memmodel_attr]);
12645 mips_multi_start ();
12647 /* Output the release side of the memory barrier. */
12648 if (need_atomic_barrier_p (model, true))
12650 if (required_oldval == 0 && TARGET_OCTEON)
12652 /* Octeon doesn't reorder reads, so a full barrier can be
12653 created by using SYNCW to order writes combined with the
12654 write from the following SC. When the SC successfully
12655 completes, we know that all preceding writes are also
12656 committed to the coherent memory system. It is possible
12657 for a single SYNCW to fail, but a pair of them will never
12658 fail, so we use two. */
12659 mips_multi_add_insn ("syncw", NULL);
12660 mips_multi_add_insn ("syncw", NULL);
12663 mips_multi_add_insn ("sync", NULL);
12666 /* Output the branch-back label. */
12667 mips_multi_add_label ("1:");
12669 /* OLDVAL = *MEM. */
12670 mips_multi_add_insn (is_64bit_p ? "lld\t%0,%1" : "ll\t%0,%1",
12671 oldval, mem, NULL);
12673 /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */
12674 if (required_oldval)
12676 if (inclusive_mask == 0)
12680 gcc_assert (oldval != at);
12681 mips_multi_add_insn ("and\t%0,%1,%2",
12682 at, oldval, inclusive_mask, NULL);
12685 mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1, required_oldval, NULL);
12687 /* CMP = 0 [delay slot]. */
12689 mips_multi_add_insn ("li\t%0,0", cmp, NULL);
12692 /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */
12693 if (exclusive_mask == 0)
12697 gcc_assert (oldval != at);
12698 mips_multi_add_insn ("and\t%0,%1,%z2",
12699 at, oldval, exclusive_mask, NULL);
12703 /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2).
12705 We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit
12706 at least one instruction in that case. */
12707 if (insn1 == SYNC_INSN1_MOVE
12708 && (tmp1 != const0_rtx || insn2 != SYNC_INSN2_NOP))
12712 mips_multi_add_insn (mips_sync_insn1_template (insn1, is_64bit_p),
12713 newval, oldval, insn1_op2, NULL);
12717 /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */
12718 if (insn2 == SYNC_INSN2_NOP)
12722 mips_multi_add_insn (mips_sync_insn2_template (insn2),
12723 newval, tmp2, inclusive_mask, NULL);
12726 tmp3_insn = mips_multi_last_index ();
12728 /* $AT = $TMP1 | $TMP3. */
12729 if (tmp1 == const0_rtx || tmp3 == const0_rtx)
12731 mips_multi_set_operand (tmp3_insn, 0, at);
12736 gcc_assert (tmp1 != tmp3);
12737 mips_multi_add_insn ("or\t%0,%1,%2", at, tmp1, tmp3, NULL);
12740 /* if (!commit (*MEM = $AT)) goto 1.
12742 This will sometimes be a delayed branch; see the write code below
12744 mips_multi_add_insn (is_64bit_p ? "scd\t%0,%1" : "sc\t%0,%1", at, mem, NULL);
12745 mips_multi_add_insn ("beq%?\t%0,%.,1b", at, NULL);
12747 /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */
12748 if (insn1 != SYNC_INSN1_MOVE && insn1 != SYNC_INSN1_LI && tmp3 != newval)
12750 mips_multi_copy_insn (tmp3_insn);
12751 mips_multi_set_operand (mips_multi_last_index (), 0, newval);
12753 else if (!(required_oldval && cmp))
12754 mips_multi_add_insn ("nop", NULL);
12756 /* CMP = 1 -- either standalone or in a delay slot. */
12757 if (required_oldval && cmp)
12758 mips_multi_add_insn ("li\t%0,1", cmp, NULL);
12760 /* Output the acquire side of the memory barrier. */
12761 if (TARGET_SYNC_AFTER_SC && need_atomic_barrier_p (model, false))
12762 mips_multi_add_insn ("sync", NULL);
12764 /* Output the exit label, if needed. */
12765 if (required_oldval)
12766 mips_multi_add_label ("2:");
12768 #undef READ_OPERAND
12771 /* Output and/or return the asm template for sync loop INSN, which has
12772 the operands given by OPERANDS. */
12775 mips_output_sync_loop (rtx insn, rtx *operands)
12777 mips_process_sync_loop (insn, operands);
12779 /* Use branch-likely instructions to work around the LL/SC R10000
12781 mips_branch_likely = TARGET_FIX_R10000;
12783 mips_push_asm_switch (&mips_noreorder);
12784 mips_push_asm_switch (&mips_nomacro);
12785 mips_push_asm_switch (&mips_noat);
12786 mips_start_ll_sc_sync_block ();
12788 mips_multi_write ();
12790 mips_end_ll_sc_sync_block ();
12791 mips_pop_asm_switch (&mips_noat);
12792 mips_pop_asm_switch (&mips_nomacro);
12793 mips_pop_asm_switch (&mips_noreorder);
12798 /* Return the number of individual instructions in sync loop INSN,
12799 which has the operands given by OPERANDS. */
12802 mips_sync_loop_insns (rtx insn, rtx *operands)
12804 mips_process_sync_loop (insn, operands);
12805 return mips_multi_num_insns;
12808 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
12809 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
12811 When working around R4000 and R4400 errata, we need to make sure that
12812 the division is not immediately followed by a shift[1][2]. We also
12813 need to stop the division from being put into a branch delay slot[3].
12814 The easiest way to avoid both problems is to add a nop after the
12815 division. When a divide-by-zero check is needed, this nop can be
12816 used to fill the branch delay slot.
12818 [1] If a double-word or a variable shift executes immediately
12819 after starting an integer division, the shift may give an
12820 incorrect result. See quotations of errata #16 and #28 from
12821 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
12822 in mips.md for details.
12824 [2] A similar bug to [1] exists for all revisions of the
12825 R4000 and the R4400 when run in an MC configuration.
12826 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
12828 "19. In this following sequence:
12830 ddiv (or ddivu or div or divu)
12831 dsll32 (or dsrl32, dsra32)
12833 if an MPT stall occurs, while the divide is slipping the cpu
12834 pipeline, then the following double shift would end up with an
12837 Workaround: The compiler needs to avoid generating any
12838 sequence with divide followed by extended double shift."
12840 This erratum is also present in "MIPS R4400MC Errata, Processor
12841 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
12842 & 3.0" as errata #10 and #4, respectively.
12844 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
12845 (also valid for MIPS R4000MC processors):
12847 "52. R4000SC: This bug does not apply for the R4000PC.
12849 There are two flavors of this bug:
12851 1) If the instruction just after divide takes an RF exception
12852 (tlb-refill, tlb-invalid) and gets an instruction cache
12853 miss (both primary and secondary) and the line which is
12854 currently in secondary cache at this index had the first
12855 data word, where the bits 5..2 are set, then R4000 would
12856 get a wrong result for the div.
12861 ------------------- # end-of page. -tlb-refill
12866 ------------------- # end-of page. -tlb-invalid
12869 2) If the divide is in the taken branch delay slot, where the
12870 target takes RF exception and gets an I-cache miss for the
12871 exception vector or where I-cache miss occurs for the
12872 target address, under the above mentioned scenarios, the
12873 div would get wrong results.
12876 j r2 # to next page mapped or unmapped
12877 div r8,r9 # this bug would be there as long
12878 # as there is an ICache miss and
12879 nop # the "data pattern" is present
12882 beq r0, r0, NextPage # to Next page
12886 This bug is present for div, divu, ddiv, and ddivu
12889 Workaround: For item 1), OS could make sure that the next page
12890 after the divide instruction is also mapped. For item 2), the
12891 compiler could make sure that the divide instruction is not in
12892 the branch delay slot."
12894 These processors have PRId values of 0x00004220 and 0x00004300 for
12895 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
12898 mips_output_division (const char *division, rtx *operands)
12903 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
12905 output_asm_insn (s, operands);
12908 if (TARGET_CHECK_ZERO_DIV)
12912 output_asm_insn (s, operands);
12913 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
12915 else if (GENERATE_DIVIDE_TRAPS)
12917 /* Avoid long replay penalty on load miss by putting the trap before
12920 output_asm_insn ("teq\t%2,%.,7", operands);
12923 output_asm_insn (s, operands);
12924 s = "teq\t%2,%.,7";
12929 output_asm_insn ("%(bne\t%2,%.,1f", operands);
12930 output_asm_insn (s, operands);
12931 s = "break\t7%)\n1:";
12937 /* Return true if IN_INSN is a multiply-add or multiply-subtract
12938 instruction and if OUT_INSN assigns to the accumulator operand. */
12941 mips_linked_madd_p (rtx out_insn, rtx in_insn)
12943 enum attr_accum_in accum_in;
12944 int accum_in_opnum;
12947 if (recog_memoized (in_insn) < 0)
12950 accum_in = get_attr_accum_in (in_insn);
12951 if (accum_in == ACCUM_IN_NONE)
12954 accum_in_opnum = accum_in - ACCUM_IN_0;
12956 extract_insn (in_insn);
12957 gcc_assert (accum_in_opnum < recog_data.n_operands);
12958 accum_in_op = recog_data.operand[accum_in_opnum];
12960 return reg_set_p (accum_in_op, out_insn);
12963 /* True if the dependency between OUT_INSN and IN_INSN is on the store
12964 data rather than the address. We need this because the cprestore
12965 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
12966 which causes the default routine to abort. We just return false
12970 mips_store_data_bypass_p (rtx out_insn, rtx in_insn)
12972 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
12975 return !store_data_bypass_p (out_insn, in_insn);
12979 /* Variables and flags used in scheduler hooks when tuning for
12983 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
12986 /* If true, then next ALU1/2 instruction will go to ALU1. */
12989 /* If true, then next FALU1/2 unstruction will go to FALU1. */
12992 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
12993 int alu1_core_unit_code;
12994 int alu2_core_unit_code;
12995 int falu1_core_unit_code;
12996 int falu2_core_unit_code;
12998 /* True if current cycle has a multi instruction.
12999 This flag is used in mips_ls2_dfa_post_advance_cycle. */
13000 bool cycle_has_multi_p;
13002 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
13003 These are used in mips_ls2_dfa_post_advance_cycle to initialize
13005 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
13006 instruction to go ALU1. */
13007 rtx alu1_turn_enabled_insn;
13008 rtx alu2_turn_enabled_insn;
13009 rtx falu1_turn_enabled_insn;
13010 rtx falu2_turn_enabled_insn;
13013 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
13014 dependencies have no cost, except on the 20Kc where output-dependence
13015 is treated like input-dependence. */
13018 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
13019 rtx dep ATTRIBUTE_UNUSED, int cost)
13021 if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT
13024 if (REG_NOTE_KIND (link) != 0)
13029 /* Return the number of instructions that can be issued per cycle. */
13032 mips_issue_rate (void)
13036 case PROCESSOR_74KC:
13037 case PROCESSOR_74KF2_1:
13038 case PROCESSOR_74KF1_1:
13039 case PROCESSOR_74KF3_2:
13040 /* The 74k is not strictly quad-issue cpu, but can be seen as one
13041 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
13042 but in reality only a maximum of 3 insns can be issued as
13043 floating-point loads and stores also require a slot in the
13045 case PROCESSOR_R10000:
13046 /* All R10K Processors are quad-issue (being the first MIPS
13047 processors to support this feature). */
13050 case PROCESSOR_20KC:
13051 case PROCESSOR_R4130:
13052 case PROCESSOR_R5400:
13053 case PROCESSOR_R5500:
13054 case PROCESSOR_R5900:
13055 case PROCESSOR_R7000:
13056 case PROCESSOR_R9000:
13057 case PROCESSOR_OCTEON:
13058 case PROCESSOR_OCTEON2:
13061 case PROCESSOR_SB1:
13062 case PROCESSOR_SB1A:
13063 /* This is actually 4, but we get better performance if we claim 3.
13064 This is partly because of unwanted speculative code motion with the
13065 larger number, and partly because in most common cases we can't
13066 reach the theoretical max of 4. */
13069 case PROCESSOR_LOONGSON_2E:
13070 case PROCESSOR_LOONGSON_2F:
13071 case PROCESSOR_LOONGSON_3A:
13074 case PROCESSOR_XLP:
13075 return (reload_completed ? 4 : 3);
13082 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
13085 mips_ls2_init_dfa_post_cycle_insn (void)
13088 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
13089 mips_ls2.alu1_turn_enabled_insn = get_insns ();
13093 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
13094 mips_ls2.alu2_turn_enabled_insn = get_insns ();
13098 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
13099 mips_ls2.falu1_turn_enabled_insn = get_insns ();
13103 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
13104 mips_ls2.falu2_turn_enabled_insn = get_insns ();
13107 mips_ls2.alu1_core_unit_code = get_cpu_unit_code ("ls2_alu1_core");
13108 mips_ls2.alu2_core_unit_code = get_cpu_unit_code ("ls2_alu2_core");
13109 mips_ls2.falu1_core_unit_code = get_cpu_unit_code ("ls2_falu1_core");
13110 mips_ls2.falu2_core_unit_code = get_cpu_unit_code ("ls2_falu2_core");
13113 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
13114 Init data used in mips_dfa_post_advance_cycle. */
13117 mips_init_dfa_post_cycle_insn (void)
13119 if (TUNE_LOONGSON_2EF)
13120 mips_ls2_init_dfa_post_cycle_insn ();
13123 /* Initialize STATE when scheduling for Loongson 2E/2F.
13124 Support round-robin dispatch scheme by enabling only one of
13125 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
13129 mips_ls2_dfa_post_advance_cycle (state_t state)
13131 if (cpu_unit_reservation_p (state, mips_ls2.alu1_core_unit_code))
13133 /* Though there are no non-pipelined ALU1 insns,
13134 we can get an instruction of type 'multi' before reload. */
13135 gcc_assert (mips_ls2.cycle_has_multi_p);
13136 mips_ls2.alu1_turn_p = false;
13139 mips_ls2.cycle_has_multi_p = false;
13141 if (cpu_unit_reservation_p (state, mips_ls2.alu2_core_unit_code))
13142 /* We have a non-pipelined alu instruction in the core,
13143 adjust round-robin counter. */
13144 mips_ls2.alu1_turn_p = true;
13146 if (mips_ls2.alu1_turn_p)
13148 if (state_transition (state, mips_ls2.alu1_turn_enabled_insn) >= 0)
13149 gcc_unreachable ();
13153 if (state_transition (state, mips_ls2.alu2_turn_enabled_insn) >= 0)
13154 gcc_unreachable ();
13157 if (cpu_unit_reservation_p (state, mips_ls2.falu1_core_unit_code))
13159 /* There are no non-pipelined FALU1 insns. */
13160 gcc_unreachable ();
13161 mips_ls2.falu1_turn_p = false;
13164 if (cpu_unit_reservation_p (state, mips_ls2.falu2_core_unit_code))
13165 /* We have a non-pipelined falu instruction in the core,
13166 adjust round-robin counter. */
13167 mips_ls2.falu1_turn_p = true;
13169 if (mips_ls2.falu1_turn_p)
13171 if (state_transition (state, mips_ls2.falu1_turn_enabled_insn) >= 0)
13172 gcc_unreachable ();
13176 if (state_transition (state, mips_ls2.falu2_turn_enabled_insn) >= 0)
13177 gcc_unreachable ();
13181 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
13182 This hook is being called at the start of each cycle. */
13185 mips_dfa_post_advance_cycle (void)
13187 if (TUNE_LOONGSON_2EF)
13188 mips_ls2_dfa_post_advance_cycle (curr_state);
13191 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
13192 be as wide as the scheduling freedom in the DFA. */
13195 mips_multipass_dfa_lookahead (void)
13197 /* Can schedule up to 4 of the 6 function units in any one cycle. */
13201 if (TUNE_LOONGSON_2EF || TUNE_LOONGSON_3A)
13210 /* Remove the instruction at index LOWER from ready queue READY and
13211 reinsert it in front of the instruction at index HIGHER. LOWER must
13215 mips_promote_ready (rtx *ready, int lower, int higher)
13220 new_head = ready[lower];
13221 for (i = lower; i < higher; i++)
13222 ready[i] = ready[i + 1];
13223 ready[i] = new_head;
13226 /* If the priority of the instruction at POS2 in the ready queue READY
13227 is within LIMIT units of that of the instruction at POS1, swap the
13228 instructions if POS2 is not already less than POS1. */
13231 mips_maybe_swap_ready (rtx *ready, int pos1, int pos2, int limit)
13234 && INSN_PRIORITY (ready[pos1]) + limit >= INSN_PRIORITY (ready[pos2]))
13238 temp = ready[pos1];
13239 ready[pos1] = ready[pos2];
13240 ready[pos2] = temp;
13244 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
13245 that may clobber hi or lo. */
13246 static rtx mips_macc_chains_last_hilo;
13248 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
13249 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
13252 mips_macc_chains_record (rtx insn)
13254 if (get_attr_may_clobber_hilo (insn))
13255 mips_macc_chains_last_hilo = insn;
13258 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
13259 has NREADY elements, looking for a multiply-add or multiply-subtract
13260 instruction that is cumulative with mips_macc_chains_last_hilo.
13261 If there is one, promote it ahead of anything else that might
13262 clobber hi or lo. */
13265 mips_macc_chains_reorder (rtx *ready, int nready)
13269 if (mips_macc_chains_last_hilo != 0)
13270 for (i = nready - 1; i >= 0; i--)
13271 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
13273 for (j = nready - 1; j > i; j--)
13274 if (recog_memoized (ready[j]) >= 0
13275 && get_attr_may_clobber_hilo (ready[j]))
13277 mips_promote_ready (ready, i, j);
13284 /* The last instruction to be scheduled. */
13285 static rtx vr4130_last_insn;
13287 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
13288 points to an rtx that is initially an instruction. Nullify the rtx
13289 if the instruction uses the value of register X. */
13292 vr4130_true_reg_dependence_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
13297 insn_ptr = (rtx *) data;
13300 && reg_referenced_p (x, PATTERN (*insn_ptr)))
13304 /* Return true if there is true register dependence between vr4130_last_insn
13308 vr4130_true_reg_dependence_p (rtx insn)
13310 note_stores (PATTERN (vr4130_last_insn),
13311 vr4130_true_reg_dependence_p_1, &insn);
13315 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
13316 the ready queue and that INSN2 is the instruction after it, return
13317 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
13318 in which INSN1 and INSN2 can probably issue in parallel, but for
13319 which (INSN2, INSN1) should be less sensitive to instruction
13320 alignment than (INSN1, INSN2). See 4130.md for more details. */
13323 vr4130_swap_insns_p (rtx insn1, rtx insn2)
13325 sd_iterator_def sd_it;
13328 /* Check for the following case:
13330 1) there is some other instruction X with an anti dependence on INSN1;
13331 2) X has a higher priority than INSN2; and
13332 3) X is an arithmetic instruction (and thus has no unit restrictions).
13334 If INSN1 is the last instruction blocking X, it would better to
13335 choose (INSN1, X) over (INSN2, INSN1). */
13336 FOR_EACH_DEP (insn1, SD_LIST_FORW, sd_it, dep)
13337 if (DEP_TYPE (dep) == REG_DEP_ANTI
13338 && INSN_PRIORITY (DEP_CON (dep)) > INSN_PRIORITY (insn2)
13339 && recog_memoized (DEP_CON (dep)) >= 0
13340 && get_attr_vr4130_class (DEP_CON (dep)) == VR4130_CLASS_ALU)
13343 if (vr4130_last_insn != 0
13344 && recog_memoized (insn1) >= 0
13345 && recog_memoized (insn2) >= 0)
13347 /* See whether INSN1 and INSN2 use different execution units,
13348 or if they are both ALU-type instructions. If so, they can
13349 probably execute in parallel. */
13350 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
13351 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
13352 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
13354 /* If only one of the instructions has a dependence on
13355 vr4130_last_insn, prefer to schedule the other one first. */
13356 bool dep1_p = vr4130_true_reg_dependence_p (insn1);
13357 bool dep2_p = vr4130_true_reg_dependence_p (insn2);
13358 if (dep1_p != dep2_p)
13361 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
13362 is not an ALU-type instruction and if INSN1 uses the same
13363 execution unit. (Note that if this condition holds, we already
13364 know that INSN2 uses a different execution unit.) */
13365 if (class1 != VR4130_CLASS_ALU
13366 && recog_memoized (vr4130_last_insn) >= 0
13367 && class1 == get_attr_vr4130_class (vr4130_last_insn))
13374 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
13375 queue with at least two instructions. Swap the first two if
13376 vr4130_swap_insns_p says that it could be worthwhile. */
13379 vr4130_reorder (rtx *ready, int nready)
13381 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
13382 mips_promote_ready (ready, nready - 2, nready - 1);
13385 /* Record whether last 74k AGEN instruction was a load or store. */
13386 static enum attr_type mips_last_74k_agen_insn = TYPE_UNKNOWN;
13388 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
13389 resets to TYPE_UNKNOWN state. */
13392 mips_74k_agen_init (rtx insn)
13394 if (!insn || CALL_P (insn) || JUMP_P (insn))
13395 mips_last_74k_agen_insn = TYPE_UNKNOWN;
13398 enum attr_type type = get_attr_type (insn);
13399 if (type == TYPE_LOAD || type == TYPE_STORE)
13400 mips_last_74k_agen_insn = type;
13404 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
13405 loads to be grouped together, and multiple stores to be grouped
13406 together. Swap things around in the ready queue to make this happen. */
13409 mips_74k_agen_reorder (rtx *ready, int nready)
13412 int store_pos, load_pos;
13417 for (i = nready - 1; i >= 0; i--)
13419 rtx insn = ready[i];
13420 if (USEFUL_INSN_P (insn))
13421 switch (get_attr_type (insn))
13424 if (store_pos == -1)
13429 if (load_pos == -1)
13438 if (load_pos == -1 || store_pos == -1)
13441 switch (mips_last_74k_agen_insn)
13444 /* Prefer to schedule loads since they have a higher latency. */
13446 /* Swap loads to the front of the queue. */
13447 mips_maybe_swap_ready (ready, load_pos, store_pos, 4);
13450 /* Swap stores to the front of the queue. */
13451 mips_maybe_swap_ready (ready, store_pos, load_pos, 4);
13458 /* Implement TARGET_SCHED_INIT. */
13461 mips_sched_init (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13462 int max_ready ATTRIBUTE_UNUSED)
13464 mips_macc_chains_last_hilo = 0;
13465 vr4130_last_insn = 0;
13466 mips_74k_agen_init (NULL_RTX);
13468 /* When scheduling for Loongson2, branch instructions go to ALU1,
13469 therefore basic block is most likely to start with round-robin counter
13470 pointed to ALU2. */
13471 mips_ls2.alu1_turn_p = false;
13472 mips_ls2.falu1_turn_p = true;
13475 /* Subroutine used by TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
13478 mips_sched_reorder_1 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13479 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
13481 if (!reload_completed
13482 && TUNE_MACC_CHAINS
13484 mips_macc_chains_reorder (ready, *nreadyp);
13486 if (reload_completed
13488 && !TARGET_VR4130_ALIGN
13490 vr4130_reorder (ready, *nreadyp);
13493 mips_74k_agen_reorder (ready, *nreadyp);
13496 /* Implement TARGET_SCHED_REORDER. */
13499 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13500 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
13502 mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle);
13503 return mips_issue_rate ();
13506 /* Implement TARGET_SCHED_REORDER2. */
13509 mips_sched_reorder2 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13510 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
13512 mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle);
13513 return cached_can_issue_more;
13516 /* Update round-robin counters for ALU1/2 and FALU1/2. */
13519 mips_ls2_variable_issue (rtx insn)
13521 if (mips_ls2.alu1_turn_p)
13523 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu1_core_unit_code))
13524 mips_ls2.alu1_turn_p = false;
13528 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu2_core_unit_code))
13529 mips_ls2.alu1_turn_p = true;
13532 if (mips_ls2.falu1_turn_p)
13534 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu1_core_unit_code))
13535 mips_ls2.falu1_turn_p = false;
13539 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu2_core_unit_code))
13540 mips_ls2.falu1_turn_p = true;
13543 if (recog_memoized (insn) >= 0)
13544 mips_ls2.cycle_has_multi_p |= (get_attr_type (insn) == TYPE_MULTI);
13547 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
13550 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13551 rtx insn, int more)
13553 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
13554 if (USEFUL_INSN_P (insn))
13556 if (get_attr_type (insn) != TYPE_GHOST)
13558 if (!reload_completed && TUNE_MACC_CHAINS)
13559 mips_macc_chains_record (insn);
13560 vr4130_last_insn = insn;
13562 mips_74k_agen_init (insn);
13563 else if (TUNE_LOONGSON_2EF)
13564 mips_ls2_variable_issue (insn);
13567 /* Instructions of type 'multi' should all be split before
13568 the second scheduling pass. */
13569 gcc_assert (!reload_completed
13570 || recog_memoized (insn) < 0
13571 || get_attr_type (insn) != TYPE_MULTI);
13573 cached_can_issue_more = more;
13577 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
13578 return the first operand of the associated PREF or PREFX insn. */
13581 mips_prefetch_cookie (rtx write, rtx locality)
13583 /* store_streamed / load_streamed. */
13584 if (INTVAL (locality) <= 0)
13585 return GEN_INT (INTVAL (write) + 4);
13587 /* store / load. */
13588 if (INTVAL (locality) <= 2)
13591 /* store_retained / load_retained. */
13592 return GEN_INT (INTVAL (write) + 6);
13595 /* Flags that indicate when a built-in function is available.
13597 BUILTIN_AVAIL_NON_MIPS16
13598 The function is available on the current target, but only
13599 in non-MIPS16 mode. */
13600 #define BUILTIN_AVAIL_NON_MIPS16 1
13602 /* Declare an availability predicate for built-in functions that
13603 require non-MIPS16 mode and also require COND to be true.
13604 NAME is the main part of the predicate's name. */
13605 #define AVAIL_NON_MIPS16(NAME, COND) \
13606 static unsigned int \
13607 mips_builtin_avail_##NAME (void) \
13609 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
13612 /* This structure describes a single built-in function. */
13613 struct mips_builtin_description {
13614 /* The code of the main .md file instruction. See mips_builtin_type
13615 for more information. */
13616 enum insn_code icode;
13618 /* The floating-point comparison code to use with ICODE, if any. */
13619 enum mips_fp_condition cond;
13621 /* The name of the built-in function. */
13624 /* Specifies how the function should be expanded. */
13625 enum mips_builtin_type builtin_type;
13627 /* The function's prototype. */
13628 enum mips_function_type function_type;
13630 /* Whether the function is available. */
13631 unsigned int (*avail) (void);
13634 AVAIL_NON_MIPS16 (paired_single, TARGET_PAIRED_SINGLE_FLOAT)
13635 AVAIL_NON_MIPS16 (sb1_paired_single, TARGET_SB1 && TARGET_PAIRED_SINGLE_FLOAT)
13636 AVAIL_NON_MIPS16 (mips3d, TARGET_MIPS3D)
13637 AVAIL_NON_MIPS16 (dsp, TARGET_DSP)
13638 AVAIL_NON_MIPS16 (dspr2, TARGET_DSPR2)
13639 AVAIL_NON_MIPS16 (dsp_32, !TARGET_64BIT && TARGET_DSP)
13640 AVAIL_NON_MIPS16 (dsp_64, TARGET_64BIT && TARGET_DSP)
13641 AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2)
13642 AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS)
13643 AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
13645 /* Construct a mips_builtin_description from the given arguments.
13647 INSN is the name of the associated instruction pattern, without the
13648 leading CODE_FOR_mips_.
13650 CODE is the floating-point condition code associated with the
13651 function. It can be 'f' if the field is not applicable.
13653 NAME is the name of the function itself, without the leading
13656 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
13658 AVAIL is the name of the availability predicate, without the leading
13659 mips_builtin_avail_. */
13660 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
13661 FUNCTION_TYPE, AVAIL) \
13662 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
13663 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
13664 mips_builtin_avail_ ## AVAIL }
13666 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
13667 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
13668 are as for MIPS_BUILTIN. */
13669 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
13670 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
13672 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
13673 are subject to mips_builtin_avail_<AVAIL>. */
13674 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
13675 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
13676 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
13677 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
13678 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
13680 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
13681 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
13682 while the any and all forms are subject to mips_builtin_avail_mips3d. */
13683 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
13684 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
13685 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
13687 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
13688 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
13690 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
13691 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
13693 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
13694 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
13697 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
13698 are subject to mips_builtin_avail_mips3d. */
13699 #define CMP_4S_BUILTINS(INSN, COND) \
13700 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
13701 MIPS_BUILTIN_CMP_ANY, \
13702 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
13703 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
13704 MIPS_BUILTIN_CMP_ALL, \
13705 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
13707 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
13708 instruction requires mips_builtin_avail_<AVAIL>. */
13709 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
13710 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
13711 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
13713 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
13714 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
13717 /* Define all the built-in functions related to C.cond.fmt condition COND. */
13718 #define CMP_BUILTINS(COND) \
13719 MOVTF_BUILTINS (c, COND, paired_single), \
13720 MOVTF_BUILTINS (cabs, COND, mips3d), \
13721 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
13722 CMP_PS_BUILTINS (c, COND, paired_single), \
13723 CMP_PS_BUILTINS (cabs, COND, mips3d), \
13724 CMP_4S_BUILTINS (c, COND), \
13725 CMP_4S_BUILTINS (cabs, COND)
13727 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
13728 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
13729 and AVAIL are as for MIPS_BUILTIN. */
13730 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
13731 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
13732 FUNCTION_TYPE, AVAIL)
13734 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
13735 branch instruction. AVAIL is as for MIPS_BUILTIN. */
13736 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
13737 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
13738 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
13740 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
13741 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
13742 builtin_description field. */
13743 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
13744 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
13745 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
13746 FUNCTION_TYPE, mips_builtin_avail_loongson }
13748 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
13749 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
13750 builtin_description field. */
13751 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
13752 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
13754 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
13755 We use functions of this form when the same insn can be usefully applied
13756 to more than one datatype. */
13757 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
13758 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
13760 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
13761 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
13762 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
13763 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
13764 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
13765 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
13766 #define CODE_FOR_mips_mult CODE_FOR_mulsidi3_32bit
13767 #define CODE_FOR_mips_multu CODE_FOR_umulsidi3_32bit
13769 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
13770 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
13771 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
13772 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
13773 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
13774 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
13775 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
13776 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
13777 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
13778 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
13779 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
13780 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
13781 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
13782 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
13783 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
13784 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
13785 #define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3
13786 #define CODE_FOR_loongson_psllh CODE_FOR_ashlv4hi3
13787 #define CODE_FOR_loongson_psllw CODE_FOR_ashlv2si3
13788 #define CODE_FOR_loongson_psrlh CODE_FOR_lshrv4hi3
13789 #define CODE_FOR_loongson_psrlw CODE_FOR_lshrv2si3
13790 #define CODE_FOR_loongson_psrah CODE_FOR_ashrv4hi3
13791 #define CODE_FOR_loongson_psraw CODE_FOR_ashrv2si3
13792 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
13793 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
13794 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
13795 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
13796 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
13797 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
13798 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
13800 static const struct mips_builtin_description mips_builtins[] = {
13801 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13802 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13803 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13804 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13805 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, paired_single),
13806 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, paired_single),
13807 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, paired_single),
13808 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, paired_single),
13810 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT, paired_single),
13811 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13812 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13813 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
13814 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, mips3d),
13816 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, mips3d),
13817 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, mips3d),
13818 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
13819 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
13820 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
13821 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13823 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, mips3d),
13824 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, mips3d),
13825 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
13826 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
13827 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
13828 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13830 MIPS_FP_CONDITIONS (CMP_BUILTINS),
13832 /* Built-in functions for the SB-1 processor. */
13833 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, sb1_paired_single),
13835 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
13836 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13837 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13838 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
13839 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13840 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13841 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13842 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13843 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
13844 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13845 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13846 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, dsp),
13847 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, dsp),
13848 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, dsp),
13849 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, dsp),
13850 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, dsp),
13851 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, dsp),
13852 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
13853 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
13854 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
13855 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
13856 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, dsp),
13857 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, dsp),
13858 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
13859 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
13860 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
13861 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
13862 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
13863 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
13864 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
13865 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
13866 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
13867 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
13868 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
13869 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
13870 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
13871 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
13872 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
13873 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, dsp),
13874 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
13875 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
13876 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13877 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
13878 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
13879 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, dsp),
13880 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, dsp),
13881 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, dsp),
13882 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, dsp),
13883 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
13884 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
13885 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
13886 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
13887 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
13888 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
13889 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
13890 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
13891 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
13892 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13893 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13894 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13895 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, dsp),
13896 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, dsp),
13897 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_POINTER_SI, dsp),
13898 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_POINTER_SI, dsp),
13899 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_POINTER_SI, dsp),
13900 BPOSGE_BUILTIN (32, dsp),
13902 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
13903 DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, dspr2),
13904 DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13905 DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13906 DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
13907 DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
13908 DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
13909 DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
13910 DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
13911 DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
13912 DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
13913 DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13914 DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13915 DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13916 DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13917 DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13918 DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dspr2),
13919 DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
13920 DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
13921 DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
13922 DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
13923 DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
13924 DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, dspr2),
13925 DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13926 DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13927 DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
13928 DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
13929 DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13930 DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13931 DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13932 DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13933 DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13934 DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13935 DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13936 DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13938 /* Built-in functions for the DSP ASE (32-bit only). */
13939 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
13940 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
13941 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
13942 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
13943 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13944 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13945 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13946 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
13947 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
13948 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13949 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13950 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13951 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13952 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
13953 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
13954 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
13955 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, dsp_32),
13956 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, dsp_32),
13957 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, dsp_32),
13958 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, dsp_32),
13959 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, dsp_32),
13960 DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
13961 DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32),
13962 DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
13963 DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32),
13964 DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, dsp_32),
13965 DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, dsp_32),
13967 /* Built-in functions for the DSP ASE (64-bit only). */
13968 DIRECT_BUILTIN (ldx, MIPS_DI_FTYPE_POINTER_SI, dsp_64),
13970 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
13971 DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13972 DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13973 DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13974 DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13975 DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13976 DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13977 DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13978 DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13979 DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13981 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
13982 LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI),
13983 LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI),
13984 LOONGSON_BUILTIN (packushb, MIPS_UV8QI_FTYPE_UV4HI_UV4HI),
13985 LOONGSON_BUILTIN_SUFFIX (paddw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13986 LOONGSON_BUILTIN_SUFFIX (paddh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13987 LOONGSON_BUILTIN_SUFFIX (paddb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13988 LOONGSON_BUILTIN_SUFFIX (paddw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13989 LOONGSON_BUILTIN_SUFFIX (paddh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13990 LOONGSON_BUILTIN_SUFFIX (paddb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13991 LOONGSON_BUILTIN_SUFFIX (paddd, u, MIPS_UDI_FTYPE_UDI_UDI),
13992 LOONGSON_BUILTIN_SUFFIX (paddd, s, MIPS_DI_FTYPE_DI_DI),
13993 LOONGSON_BUILTIN (paddsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13994 LOONGSON_BUILTIN (paddsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
13995 LOONGSON_BUILTIN (paddush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13996 LOONGSON_BUILTIN (paddusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13997 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_ud, MIPS_UDI_FTYPE_UDI_UDI),
13998 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_uw, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13999 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_uh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14000 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_ub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14001 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_sd, MIPS_DI_FTYPE_DI_DI),
14002 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_sw, MIPS_V2SI_FTYPE_V2SI_V2SI),
14003 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_sh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14004 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_sb, MIPS_V8QI_FTYPE_V8QI_V8QI),
14005 LOONGSON_BUILTIN (pavgh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14006 LOONGSON_BUILTIN (pavgb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14007 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14008 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14009 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14010 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14011 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14012 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14013 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14014 LOONGSON_BUILTIN_SUFFIX (pcmpgth, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14015 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14016 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14017 LOONGSON_BUILTIN_SUFFIX (pcmpgth, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14018 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14019 LOONGSON_BUILTIN_SUFFIX (pextrh, u, MIPS_UV4HI_FTYPE_UV4HI_USI),
14020 LOONGSON_BUILTIN_SUFFIX (pextrh, s, MIPS_V4HI_FTYPE_V4HI_USI),
14021 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14022 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14023 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14024 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14025 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14026 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14027 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14028 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14029 LOONGSON_BUILTIN (pmaddhw, MIPS_V2SI_FTYPE_V4HI_V4HI),
14030 LOONGSON_BUILTIN (pmaxsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14031 LOONGSON_BUILTIN (pmaxub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14032 LOONGSON_BUILTIN (pminsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14033 LOONGSON_BUILTIN (pminub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14034 LOONGSON_BUILTIN_SUFFIX (pmovmskb, u, MIPS_UV8QI_FTYPE_UV8QI),
14035 LOONGSON_BUILTIN_SUFFIX (pmovmskb, s, MIPS_V8QI_FTYPE_V8QI),
14036 LOONGSON_BUILTIN (pmulhuh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14037 LOONGSON_BUILTIN (pmulhh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14038 LOONGSON_BUILTIN (pmullh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14039 LOONGSON_BUILTIN (pmuluw, MIPS_UDI_FTYPE_UV2SI_UV2SI),
14040 LOONGSON_BUILTIN (pasubub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14041 LOONGSON_BUILTIN (biadd, MIPS_UV4HI_FTYPE_UV8QI),
14042 LOONGSON_BUILTIN (psadbh, MIPS_UV4HI_FTYPE_UV8QI_UV8QI),
14043 LOONGSON_BUILTIN_SUFFIX (pshufh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
14044 LOONGSON_BUILTIN_SUFFIX (pshufh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
14045 LOONGSON_BUILTIN_SUFFIX (psllh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
14046 LOONGSON_BUILTIN_SUFFIX (psllh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
14047 LOONGSON_BUILTIN_SUFFIX (psllw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
14048 LOONGSON_BUILTIN_SUFFIX (psllw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
14049 LOONGSON_BUILTIN_SUFFIX (psrah, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
14050 LOONGSON_BUILTIN_SUFFIX (psrah, s, MIPS_V4HI_FTYPE_V4HI_UQI),
14051 LOONGSON_BUILTIN_SUFFIX (psraw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
14052 LOONGSON_BUILTIN_SUFFIX (psraw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
14053 LOONGSON_BUILTIN_SUFFIX (psrlh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
14054 LOONGSON_BUILTIN_SUFFIX (psrlh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
14055 LOONGSON_BUILTIN_SUFFIX (psrlw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
14056 LOONGSON_BUILTIN_SUFFIX (psrlw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
14057 LOONGSON_BUILTIN_SUFFIX (psubw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14058 LOONGSON_BUILTIN_SUFFIX (psubh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14059 LOONGSON_BUILTIN_SUFFIX (psubb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14060 LOONGSON_BUILTIN_SUFFIX (psubw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14061 LOONGSON_BUILTIN_SUFFIX (psubh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14062 LOONGSON_BUILTIN_SUFFIX (psubb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14063 LOONGSON_BUILTIN_SUFFIX (psubd, u, MIPS_UDI_FTYPE_UDI_UDI),
14064 LOONGSON_BUILTIN_SUFFIX (psubd, s, MIPS_DI_FTYPE_DI_DI),
14065 LOONGSON_BUILTIN (psubsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14066 LOONGSON_BUILTIN (psubsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
14067 LOONGSON_BUILTIN (psubush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14068 LOONGSON_BUILTIN (psubusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14069 LOONGSON_BUILTIN_SUFFIX (punpckhbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14070 LOONGSON_BUILTIN_SUFFIX (punpckhhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14071 LOONGSON_BUILTIN_SUFFIX (punpckhwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14072 LOONGSON_BUILTIN_SUFFIX (punpckhbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14073 LOONGSON_BUILTIN_SUFFIX (punpckhhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14074 LOONGSON_BUILTIN_SUFFIX (punpckhwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14075 LOONGSON_BUILTIN_SUFFIX (punpcklbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14076 LOONGSON_BUILTIN_SUFFIX (punpcklhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14077 LOONGSON_BUILTIN_SUFFIX (punpcklwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14078 LOONGSON_BUILTIN_SUFFIX (punpcklbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14079 LOONGSON_BUILTIN_SUFFIX (punpcklhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14080 LOONGSON_BUILTIN_SUFFIX (punpcklwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14082 /* Sundry other built-in functions. */
14083 DIRECT_NO_TARGET_BUILTIN (cache, MIPS_VOID_FTYPE_SI_CVPOINTER, cache)
14086 /* Index I is the function declaration for mips_builtins[I], or null if the
14087 function isn't defined on this target. */
14088 static GTY(()) tree mips_builtin_decls[ARRAY_SIZE (mips_builtins)];
14090 /* MODE is a vector mode whose elements have type TYPE. Return the type
14091 of the vector itself. */
14094 mips_builtin_vector_type (tree type, enum machine_mode mode)
14096 static tree types[2 * (int) MAX_MACHINE_MODE];
14099 mode_index = (int) mode;
14101 if (TREE_CODE (type) == INTEGER_TYPE && TYPE_UNSIGNED (type))
14102 mode_index += MAX_MACHINE_MODE;
14104 if (types[mode_index] == NULL_TREE)
14105 types[mode_index] = build_vector_type_for_mode (type, mode);
14106 return types[mode_index];
14109 /* Return a type for 'const volatile void *'. */
14112 mips_build_cvpointer_type (void)
14116 if (cache == NULL_TREE)
14117 cache = build_pointer_type (build_qualified_type
14119 TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE));
14123 /* Source-level argument types. */
14124 #define MIPS_ATYPE_VOID void_type_node
14125 #define MIPS_ATYPE_INT integer_type_node
14126 #define MIPS_ATYPE_POINTER ptr_type_node
14127 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
14129 /* Standard mode-based argument types. */
14130 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
14131 #define MIPS_ATYPE_SI intSI_type_node
14132 #define MIPS_ATYPE_USI unsigned_intSI_type_node
14133 #define MIPS_ATYPE_DI intDI_type_node
14134 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
14135 #define MIPS_ATYPE_SF float_type_node
14136 #define MIPS_ATYPE_DF double_type_node
14138 /* Vector argument types. */
14139 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
14140 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
14141 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
14142 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
14143 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
14144 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
14145 #define MIPS_ATYPE_UV2SI \
14146 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
14147 #define MIPS_ATYPE_UV4HI \
14148 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
14149 #define MIPS_ATYPE_UV8QI \
14150 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
14152 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
14153 their associated MIPS_ATYPEs. */
14154 #define MIPS_FTYPE_ATYPES1(A, B) \
14155 MIPS_ATYPE_##A, MIPS_ATYPE_##B
14157 #define MIPS_FTYPE_ATYPES2(A, B, C) \
14158 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
14160 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
14161 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
14163 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
14164 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
14167 /* Return the function type associated with function prototype TYPE. */
14170 mips_build_function_type (enum mips_function_type type)
14172 static tree types[(int) MIPS_MAX_FTYPE_MAX];
14174 if (types[(int) type] == NULL_TREE)
14177 #define DEF_MIPS_FTYPE(NUM, ARGS) \
14178 case MIPS_FTYPE_NAME##NUM ARGS: \
14179 types[(int) type] \
14180 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
14183 #include "config/mips/mips-ftypes.def"
14184 #undef DEF_MIPS_FTYPE
14186 gcc_unreachable ();
14189 return types[(int) type];
14192 /* Implement TARGET_INIT_BUILTINS. */
14195 mips_init_builtins (void)
14197 const struct mips_builtin_description *d;
14200 /* Iterate through all of the bdesc arrays, initializing all of the
14201 builtin functions. */
14202 for (i = 0; i < ARRAY_SIZE (mips_builtins); i++)
14204 d = &mips_builtins[i];
14206 mips_builtin_decls[i]
14207 = add_builtin_function (d->name,
14208 mips_build_function_type (d->function_type),
14209 i, BUILT_IN_MD, NULL, NULL);
14213 /* Implement TARGET_BUILTIN_DECL. */
14216 mips_builtin_decl (unsigned int code, bool initialize_p ATTRIBUTE_UNUSED)
14218 if (code >= ARRAY_SIZE (mips_builtins))
14219 return error_mark_node;
14220 return mips_builtin_decls[code];
14223 /* Take argument ARGNO from EXP's argument list and convert it into
14224 an expand operand. Store the operand in *OP. */
14227 mips_prepare_builtin_arg (struct expand_operand *op, tree exp,
14228 unsigned int argno)
14233 arg = CALL_EXPR_ARG (exp, argno);
14234 value = expand_normal (arg);
14235 create_input_operand (op, value, TYPE_MODE (TREE_TYPE (arg)));
14238 /* Expand instruction ICODE as part of a built-in function sequence.
14239 Use the first NOPS elements of OPS as the instruction's operands.
14240 HAS_TARGET_P is true if operand 0 is a target; it is false if the
14241 instruction has no target.
14243 Return the target rtx if HAS_TARGET_P, otherwise return const0_rtx. */
14246 mips_expand_builtin_insn (enum insn_code icode, unsigned int nops,
14247 struct expand_operand *ops, bool has_target_p)
14249 if (!maybe_expand_insn (icode, nops, ops))
14251 error ("invalid argument to built-in function");
14252 return has_target_p ? gen_reg_rtx (ops[0].mode) : const0_rtx;
14254 return has_target_p ? ops[0].value : const0_rtx;
14257 /* Expand a floating-point comparison for built-in function call EXP.
14258 The first NARGS arguments are the values to be compared. ICODE is
14259 the .md pattern that does the comparison and COND is the condition
14260 that is being tested. Return an rtx for the result. */
14263 mips_expand_builtin_compare_1 (enum insn_code icode,
14264 enum mips_fp_condition cond,
14265 tree exp, int nargs)
14267 struct expand_operand ops[MAX_RECOG_OPERANDS];
14271 /* The instruction should have a target operand, an operand for each
14272 argument, and an operand for COND. */
14273 gcc_assert (nargs + 2 == insn_data[(int) icode].n_generator_args);
14275 output = mips_allocate_fcc (insn_data[(int) icode].operand[0].mode);
14277 create_fixed_operand (&ops[opno++], output);
14278 for (argno = 0; argno < nargs; argno++)
14279 mips_prepare_builtin_arg (&ops[opno++], exp, argno);
14280 create_integer_operand (&ops[opno++], (int) cond);
14281 return mips_expand_builtin_insn (icode, opno, ops, true);
14284 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
14285 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
14286 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
14287 suggests a good place to put the result. */
14290 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
14293 struct expand_operand ops[MAX_RECOG_OPERANDS];
14296 /* Map any target to operand 0. */
14299 create_output_operand (&ops[opno++], target, TYPE_MODE (TREE_TYPE (exp)));
14301 /* Map the arguments to the other operands. */
14302 gcc_assert (opno + call_expr_nargs (exp)
14303 == insn_data[icode].n_generator_args);
14304 for (argno = 0; argno < call_expr_nargs (exp); argno++)
14305 mips_prepare_builtin_arg (&ops[opno++], exp, argno);
14307 return mips_expand_builtin_insn (icode, opno, ops, has_target_p);
14310 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
14311 function; TYPE says which. EXP is the CALL_EXPR that calls the
14312 function, ICODE is the instruction that should be used to compare
14313 the first two arguments, and COND is the condition it should test.
14314 TARGET, if nonnull, suggests a good place to put the result. */
14317 mips_expand_builtin_movtf (enum mips_builtin_type type,
14318 enum insn_code icode, enum mips_fp_condition cond,
14319 rtx target, tree exp)
14321 struct expand_operand ops[4];
14324 cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp, 2);
14325 create_output_operand (&ops[0], target, TYPE_MODE (TREE_TYPE (exp)));
14326 if (type == MIPS_BUILTIN_MOVT)
14328 mips_prepare_builtin_arg (&ops[2], exp, 2);
14329 mips_prepare_builtin_arg (&ops[1], exp, 3);
14333 mips_prepare_builtin_arg (&ops[1], exp, 2);
14334 mips_prepare_builtin_arg (&ops[2], exp, 3);
14336 create_fixed_operand (&ops[3], cmp_result);
14337 return mips_expand_builtin_insn (CODE_FOR_mips_cond_move_tf_ps,
14341 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
14342 into TARGET otherwise. Return TARGET. */
14345 mips_builtin_branch_and_move (rtx condition, rtx target,
14346 rtx value_if_true, rtx value_if_false)
14348 rtx true_label, done_label;
14350 true_label = gen_label_rtx ();
14351 done_label = gen_label_rtx ();
14353 /* First assume that CONDITION is false. */
14354 mips_emit_move (target, value_if_false);
14356 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
14357 emit_jump_insn (gen_condjump (condition, true_label));
14358 emit_jump_insn (gen_jump (done_label));
14361 /* Fix TARGET if CONDITION is true. */
14362 emit_label (true_label);
14363 mips_emit_move (target, value_if_true);
14365 emit_label (done_label);
14369 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
14370 the CALL_EXPR that calls the function, ICODE is the code of the
14371 comparison instruction, and COND is the condition it should test.
14372 TARGET, if nonnull, suggests a good place to put the boolean result. */
14375 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
14376 enum insn_code icode, enum mips_fp_condition cond,
14377 rtx target, tree exp)
14379 rtx offset, condition, cmp_result;
14381 if (target == 0 || GET_MODE (target) != SImode)
14382 target = gen_reg_rtx (SImode);
14383 cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp,
14384 call_expr_nargs (exp));
14386 /* If the comparison sets more than one register, we define the result
14387 to be 0 if all registers are false and -1 if all registers are true.
14388 The value of the complete result is indeterminate otherwise. */
14389 switch (builtin_type)
14391 case MIPS_BUILTIN_CMP_ALL:
14392 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
14393 return mips_builtin_branch_and_move (condition, target,
14394 const0_rtx, const1_rtx);
14396 case MIPS_BUILTIN_CMP_UPPER:
14397 case MIPS_BUILTIN_CMP_LOWER:
14398 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
14399 condition = gen_single_cc (cmp_result, offset);
14400 return mips_builtin_branch_and_move (condition, target,
14401 const1_rtx, const0_rtx);
14404 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
14405 return mips_builtin_branch_and_move (condition, target,
14406 const1_rtx, const0_rtx);
14410 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
14411 if nonnull, suggests a good place to put the boolean result. */
14414 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
14416 rtx condition, cmp_result;
14419 if (target == 0 || GET_MODE (target) != SImode)
14420 target = gen_reg_rtx (SImode);
14422 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
14424 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
14429 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
14430 return mips_builtin_branch_and_move (condition, target,
14431 const1_rtx, const0_rtx);
14434 /* Implement TARGET_EXPAND_BUILTIN. */
14437 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
14438 enum machine_mode mode, int ignore)
14441 unsigned int fcode, avail;
14442 const struct mips_builtin_description *d;
14444 fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
14445 fcode = DECL_FUNCTION_CODE (fndecl);
14446 gcc_assert (fcode < ARRAY_SIZE (mips_builtins));
14447 d = &mips_builtins[fcode];
14448 avail = d->avail ();
14449 gcc_assert (avail != 0);
14452 error ("built-in function %qE not supported for MIPS16",
14453 DECL_NAME (fndecl));
14454 return ignore ? const0_rtx : CONST0_RTX (mode);
14456 switch (d->builtin_type)
14458 case MIPS_BUILTIN_DIRECT:
14459 return mips_expand_builtin_direct (d->icode, target, exp, true);
14461 case MIPS_BUILTIN_DIRECT_NO_TARGET:
14462 return mips_expand_builtin_direct (d->icode, target, exp, false);
14464 case MIPS_BUILTIN_MOVT:
14465 case MIPS_BUILTIN_MOVF:
14466 return mips_expand_builtin_movtf (d->builtin_type, d->icode,
14467 d->cond, target, exp);
14469 case MIPS_BUILTIN_CMP_ANY:
14470 case MIPS_BUILTIN_CMP_ALL:
14471 case MIPS_BUILTIN_CMP_UPPER:
14472 case MIPS_BUILTIN_CMP_LOWER:
14473 case MIPS_BUILTIN_CMP_SINGLE:
14474 return mips_expand_builtin_compare (d->builtin_type, d->icode,
14475 d->cond, target, exp);
14477 case MIPS_BUILTIN_BPOSGE32:
14478 return mips_expand_builtin_bposge (d->builtin_type, target);
14480 gcc_unreachable ();
14483 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
14484 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
14485 struct mips16_constant {
14486 struct mips16_constant *next;
14489 enum machine_mode mode;
14492 /* Information about an incomplete MIPS16 constant pool. FIRST is the
14493 first constant, HIGHEST_ADDRESS is the highest address that the first
14494 byte of the pool can have, and INSN_ADDRESS is the current instruction
14496 struct mips16_constant_pool {
14497 struct mips16_constant *first;
14498 int highest_address;
14502 /* Add constant VALUE to POOL and return its label. MODE is the
14503 value's mode (used for CONST_INTs, etc.). */
14506 mips16_add_constant (struct mips16_constant_pool *pool,
14507 rtx value, enum machine_mode mode)
14509 struct mips16_constant **p, *c;
14510 bool first_of_size_p;
14512 /* See whether the constant is already in the pool. If so, return the
14513 existing label, otherwise leave P pointing to the place where the
14514 constant should be added.
14516 Keep the pool sorted in increasing order of mode size so that we can
14517 reduce the number of alignments needed. */
14518 first_of_size_p = true;
14519 for (p = &pool->first; *p != 0; p = &(*p)->next)
14521 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
14522 return (*p)->label;
14523 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
14525 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
14526 first_of_size_p = false;
14529 /* In the worst case, the constant needed by the earliest instruction
14530 will end up at the end of the pool. The entire pool must then be
14531 accessible from that instruction.
14533 When adding the first constant, set the pool's highest address to
14534 the address of the first out-of-range byte. Adjust this address
14535 downwards each time a new constant is added. */
14536 if (pool->first == 0)
14537 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
14538 of the instruction with the lowest two bits clear. The base PC
14539 value for LDPC has the lowest three bits clear. Assume the worst
14540 case here; namely that the PC-relative instruction occupies the
14541 last 2 bytes in an aligned word. */
14542 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
14543 pool->highest_address -= GET_MODE_SIZE (mode);
14544 if (first_of_size_p)
14545 /* Take into account the worst possible padding due to alignment. */
14546 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
14548 /* Create a new entry. */
14549 c = XNEW (struct mips16_constant);
14552 c->label = gen_label_rtx ();
14559 /* Output constant VALUE after instruction INSN and return the last
14560 instruction emitted. MODE is the mode of the constant. */
14563 mips16_emit_constants_1 (enum machine_mode mode, rtx value, rtx insn)
14565 if (SCALAR_INT_MODE_P (mode) || ALL_SCALAR_FIXED_POINT_MODE_P (mode))
14567 rtx size = GEN_INT (GET_MODE_SIZE (mode));
14568 return emit_insn_after (gen_consttable_int (value, size), insn);
14571 if (SCALAR_FLOAT_MODE_P (mode))
14572 return emit_insn_after (gen_consttable_float (value), insn);
14574 if (VECTOR_MODE_P (mode))
14578 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
14579 insn = mips16_emit_constants_1 (GET_MODE_INNER (mode),
14580 CONST_VECTOR_ELT (value, i), insn);
14584 gcc_unreachable ();
14587 /* Dump out the constants in CONSTANTS after INSN. */
14590 mips16_emit_constants (struct mips16_constant *constants, rtx insn)
14592 struct mips16_constant *c, *next;
14596 for (c = constants; c != NULL; c = next)
14598 /* If necessary, increase the alignment of PC. */
14599 if (align < GET_MODE_SIZE (c->mode))
14601 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
14602 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
14604 align = GET_MODE_SIZE (c->mode);
14606 insn = emit_label_after (c->label, insn);
14607 insn = mips16_emit_constants_1 (c->mode, c->value, insn);
14613 emit_barrier_after (insn);
14616 /* Return the length of instruction INSN. */
14619 mips16_insn_length (rtx insn)
14621 if (JUMP_TABLE_DATA_P (insn))
14623 rtx body = PATTERN (insn);
14624 if (GET_CODE (body) == ADDR_VEC)
14625 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
14626 else if (GET_CODE (body) == ADDR_DIFF_VEC)
14627 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
14629 gcc_unreachable ();
14631 return get_attr_length (insn);
14634 /* If *X is a symbolic constant that refers to the constant pool, add
14635 the constant to POOL and rewrite *X to use the constant's label. */
14638 mips16_rewrite_pool_constant (struct mips16_constant_pool *pool, rtx *x)
14640 rtx base, offset, label;
14642 split_const (*x, &base, &offset);
14643 if (GET_CODE (base) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (base))
14645 label = mips16_add_constant (pool, copy_rtx (get_pool_constant (base)),
14646 get_pool_mode (base));
14647 base = gen_rtx_LABEL_REF (Pmode, label);
14648 *x = mips_unspec_address_offset (base, offset, SYMBOL_PC_RELATIVE);
14652 /* This structure is used to communicate with mips16_rewrite_pool_refs.
14653 INSN is the instruction we're rewriting and POOL points to the current
14655 struct mips16_rewrite_pool_refs_info {
14657 struct mips16_constant_pool *pool;
14660 /* Rewrite *X so that constant pool references refer to the constant's
14661 label instead. DATA points to a mips16_rewrite_pool_refs_info
14665 mips16_rewrite_pool_refs (rtx *x, void *data)
14667 struct mips16_rewrite_pool_refs_info *info =
14668 (struct mips16_rewrite_pool_refs_info *) data;
14670 if (force_to_mem_operand (*x, Pmode))
14672 rtx mem = force_const_mem (GET_MODE (*x), *x);
14673 validate_change (info->insn, x, mem, false);
14678 mips16_rewrite_pool_constant (info->pool, &XEXP (*x, 0));
14682 /* Don't rewrite the __mips16_rdwr symbol. */
14683 if (GET_CODE (*x) == UNSPEC && XINT (*x, 1) == UNSPEC_TLS_GET_TP)
14686 if (TARGET_MIPS16_TEXT_LOADS)
14687 mips16_rewrite_pool_constant (info->pool, x);
14689 return GET_CODE (*x) == CONST ? -1 : 0;
14692 /* Return whether CFG is used in mips_reorg. */
14695 mips_cfg_in_reorg (void)
14697 return (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
14698 || TARGET_RELAX_PIC_CALLS);
14701 /* Build MIPS16 constant pools. Split the instructions if SPLIT_P,
14702 otherwise assume that they are already split. */
14705 mips16_lay_out_constants (bool split_p)
14707 struct mips16_constant_pool pool;
14708 struct mips16_rewrite_pool_refs_info info;
14711 if (!TARGET_MIPS16_PCREL_LOADS)
14716 if (mips_cfg_in_reorg ())
14717 split_all_insns ();
14719 split_all_insns_noflow ();
14722 memset (&pool, 0, sizeof (pool));
14723 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
14725 /* Rewrite constant pool references in INSN. */
14726 if (USEFUL_INSN_P (insn))
14730 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &info);
14733 pool.insn_address += mips16_insn_length (insn);
14735 if (pool.first != NULL)
14737 /* If there are no natural barriers between the first user of
14738 the pool and the highest acceptable address, we'll need to
14739 create a new instruction to jump around the constant pool.
14740 In the worst case, this instruction will be 4 bytes long.
14742 If it's too late to do this transformation after INSN,
14743 do it immediately before INSN. */
14744 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
14748 label = gen_label_rtx ();
14750 jump = emit_jump_insn_before (gen_jump (label), insn);
14751 JUMP_LABEL (jump) = label;
14752 LABEL_NUSES (label) = 1;
14753 barrier = emit_barrier_after (jump);
14755 emit_label_after (label, barrier);
14756 pool.insn_address += 4;
14759 /* See whether the constant pool is now out of range of the first
14760 user. If so, output the constants after the previous barrier.
14761 Note that any instructions between BARRIER and INSN (inclusive)
14762 will use negative offsets to refer to the pool. */
14763 if (pool.insn_address > pool.highest_address)
14765 mips16_emit_constants (pool.first, barrier);
14769 else if (BARRIER_P (insn))
14773 mips16_emit_constants (pool.first, get_last_insn ());
14776 /* Return true if it is worth r10k_simplify_address's while replacing
14777 an address with X. We are looking for constants, and for addresses
14778 at a known offset from the incoming stack pointer. */
14781 r10k_simplified_address_p (rtx x)
14783 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
14785 return x == virtual_incoming_args_rtx || CONSTANT_P (x);
14788 /* X is an expression that appears in INSN. Try to use the UD chains
14789 to simplify it, returning the simplified form on success and the
14790 original form otherwise. Replace the incoming value of $sp with
14791 virtual_incoming_args_rtx (which should never occur in X otherwise). */
14794 r10k_simplify_address (rtx x, rtx insn)
14796 rtx newx, op0, op1, set, def_insn, note;
14798 struct df_link *defs;
14803 op0 = r10k_simplify_address (XEXP (x, 0), insn);
14804 if (op0 != XEXP (x, 0))
14805 newx = simplify_gen_unary (GET_CODE (x), GET_MODE (x),
14806 op0, GET_MODE (XEXP (x, 0)));
14808 else if (BINARY_P (x))
14810 op0 = r10k_simplify_address (XEXP (x, 0), insn);
14811 op1 = r10k_simplify_address (XEXP (x, 1), insn);
14812 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
14813 newx = simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
14815 else if (GET_CODE (x) == LO_SUM)
14817 /* LO_SUMs can be offset from HIGHs, if we know they won't
14818 overflow. See mips_classify_address for the rationale behind
14820 op0 = r10k_simplify_address (XEXP (x, 0), insn);
14821 if (GET_CODE (op0) == HIGH)
14822 newx = XEXP (x, 1);
14824 else if (REG_P (x))
14826 /* Uses are recorded by regno_reg_rtx, not X itself. */
14827 use = df_find_use (insn, regno_reg_rtx[REGNO (x)]);
14829 defs = DF_REF_CHAIN (use);
14831 /* Require a single definition. */
14832 if (defs && defs->next == NULL)
14835 if (DF_REF_IS_ARTIFICIAL (def))
14837 /* Replace the incoming value of $sp with
14838 virtual_incoming_args_rtx. */
14839 if (x == stack_pointer_rtx
14840 && DF_REF_BB (def) == ENTRY_BLOCK_PTR)
14841 newx = virtual_incoming_args_rtx;
14843 else if (dominated_by_p (CDI_DOMINATORS, DF_REF_BB (use),
14846 /* Make sure that DEF_INSN is a single set of REG. */
14847 def_insn = DF_REF_INSN (def);
14848 if (NONJUMP_INSN_P (def_insn))
14850 set = single_set (def_insn);
14851 if (set && rtx_equal_p (SET_DEST (set), x))
14853 /* Prefer to use notes, since the def-use chains
14854 are often shorter. */
14855 note = find_reg_equal_equiv_note (def_insn);
14857 newx = XEXP (note, 0);
14859 newx = SET_SRC (set);
14860 newx = r10k_simplify_address (newx, def_insn);
14866 if (newx && r10k_simplified_address_p (newx))
14871 /* Return true if ADDRESS is known to be an uncached address
14872 on R10K systems. */
14875 r10k_uncached_address_p (unsigned HOST_WIDE_INT address)
14877 unsigned HOST_WIDE_INT upper;
14879 /* Check for KSEG1. */
14880 if (address + 0x60000000 < 0x20000000)
14883 /* Check for uncached XKPHYS addresses. */
14884 if (Pmode == DImode)
14886 upper = (address >> 40) & 0xf9ffff;
14887 if (upper == 0x900000 || upper == 0xb80000)
14893 /* Return true if we can prove that an access to address X in instruction
14894 INSN would be safe from R10K speculation. This X is a general
14895 expression; it might not be a legitimate address. */
14898 r10k_safe_address_p (rtx x, rtx insn)
14901 HOST_WIDE_INT offset_val;
14903 x = r10k_simplify_address (x, insn);
14905 /* Check for references to the stack frame. It doesn't really matter
14906 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
14907 allows us to assume that accesses to any part of the eventual frame
14908 is safe from speculation at any point in the function. */
14909 mips_split_plus (x, &base, &offset_val);
14910 if (base == virtual_incoming_args_rtx
14911 && offset_val >= -cfun->machine->frame.total_size
14912 && offset_val < cfun->machine->frame.args_size)
14915 /* Check for uncached addresses. */
14916 if (CONST_INT_P (x))
14917 return r10k_uncached_address_p (INTVAL (x));
14919 /* Check for accesses to a static object. */
14920 split_const (x, &base, &offset);
14921 return offset_within_block_p (base, INTVAL (offset));
14924 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
14925 an in-range access to an automatic variable, or to an object with
14926 a link-time-constant address. */
14929 r10k_safe_mem_expr_p (tree expr, HOST_WIDE_INT offset)
14931 HOST_WIDE_INT bitoffset, bitsize;
14932 tree inner, var_offset;
14933 enum machine_mode mode;
14934 int unsigned_p, volatile_p;
14936 inner = get_inner_reference (expr, &bitsize, &bitoffset, &var_offset, &mode,
14937 &unsigned_p, &volatile_p, false);
14938 if (!DECL_P (inner) || !DECL_SIZE_UNIT (inner) || var_offset)
14941 offset += bitoffset / BITS_PER_UNIT;
14942 return offset >= 0 && offset < tree_low_cst (DECL_SIZE_UNIT (inner), 1);
14945 /* A for_each_rtx callback for which DATA points to the instruction
14946 containing *X. Stop the search if we find a MEM that is not safe
14947 from R10K speculation. */
14950 r10k_needs_protection_p_1 (rtx *loc, void *data)
14959 && MEM_OFFSET_KNOWN_P (mem)
14960 && r10k_safe_mem_expr_p (MEM_EXPR (mem), MEM_OFFSET (mem)))
14963 if (r10k_safe_address_p (XEXP (mem, 0), (rtx) data))
14969 /* A note_stores callback for which DATA points to an instruction pointer.
14970 If *DATA is nonnull, make it null if it X contains a MEM that is not
14971 safe from R10K speculation. */
14974 r10k_needs_protection_p_store (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
14979 insn_ptr = (rtx *) data;
14980 if (*insn_ptr && for_each_rtx (&x, r10k_needs_protection_p_1, *insn_ptr))
14981 *insn_ptr = NULL_RTX;
14984 /* A for_each_rtx callback that iterates over the pattern of a CALL_INSN.
14985 Return nonzero if the call is not to a declared function. */
14988 r10k_needs_protection_p_call (rtx *loc, void *data ATTRIBUTE_UNUSED)
14997 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DECL (x))
15003 /* Return true if instruction INSN needs to be protected by an R10K
15007 r10k_needs_protection_p (rtx insn)
15010 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_call, NULL);
15012 if (mips_r10k_cache_barrier == R10K_CACHE_BARRIER_STORE)
15014 note_stores (PATTERN (insn), r10k_needs_protection_p_store, &insn);
15015 return insn == NULL_RTX;
15018 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_1, insn);
15021 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
15022 edge is unconditional. */
15025 r10k_protected_bb_p (basic_block bb, sbitmap protected_bbs)
15030 FOR_EACH_EDGE (e, ei, bb->preds)
15031 if (!single_succ_p (e->src)
15032 || !bitmap_bit_p (protected_bbs, e->src->index)
15033 || (e->flags & EDGE_COMPLEX) != 0)
15038 /* Implement -mr10k-cache-barrier= for the current function. */
15041 r10k_insert_cache_barriers (void)
15043 int *rev_post_order;
15046 sbitmap protected_bbs;
15047 rtx insn, end, unprotected_region;
15051 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
15055 /* Calculate dominators. */
15056 calculate_dominance_info (CDI_DOMINATORS);
15058 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
15059 X is protected by a cache barrier. */
15060 protected_bbs = sbitmap_alloc (last_basic_block);
15061 bitmap_clear (protected_bbs);
15063 /* Iterate over the basic blocks in reverse post-order. */
15064 rev_post_order = XNEWVEC (int, last_basic_block);
15065 n = pre_and_rev_post_order_compute (NULL, rev_post_order, false);
15066 for (i = 0; i < n; i++)
15068 bb = BASIC_BLOCK (rev_post_order[i]);
15070 /* If this block is only reached by unconditional edges, and if the
15071 source of every edge is protected, the beginning of the block is
15073 if (r10k_protected_bb_p (bb, protected_bbs))
15074 unprotected_region = NULL_RTX;
15076 unprotected_region = pc_rtx;
15077 end = NEXT_INSN (BB_END (bb));
15079 /* UNPROTECTED_REGION is:
15081 - null if we are processing a protected region,
15082 - pc_rtx if we are processing an unprotected region but have
15083 not yet found the first instruction in it
15084 - the first instruction in an unprotected region otherwise. */
15085 for (insn = BB_HEAD (bb); insn != end; insn = NEXT_INSN (insn))
15087 if (unprotected_region && USEFUL_INSN_P (insn))
15089 if (recog_memoized (insn) == CODE_FOR_mips_cache)
15090 /* This CACHE instruction protects the following code. */
15091 unprotected_region = NULL_RTX;
15094 /* See if INSN is the first instruction in this
15095 unprotected region. */
15096 if (unprotected_region == pc_rtx)
15097 unprotected_region = insn;
15099 /* See if INSN needs to be protected. If so,
15100 we must insert a cache barrier somewhere between
15101 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
15102 clear which position is better performance-wise,
15103 but as a tie-breaker, we assume that it is better
15104 to allow delay slots to be back-filled where
15105 possible, and that it is better not to insert
15106 barriers in the middle of already-scheduled code.
15107 We therefore insert the barrier at the beginning
15109 if (r10k_needs_protection_p (insn))
15111 emit_insn_before (gen_r10k_cache_barrier (),
15112 unprotected_region);
15113 unprotected_region = NULL_RTX;
15119 /* The called function is not required to protect the exit path.
15120 The code that follows a call is therefore unprotected. */
15121 unprotected_region = pc_rtx;
15124 /* Record whether the end of this block is protected. */
15125 if (unprotected_region == NULL_RTX)
15126 bitmap_set_bit (protected_bbs, bb->index);
15128 XDELETEVEC (rev_post_order);
15130 sbitmap_free (protected_bbs);
15132 free_dominance_info (CDI_DOMINATORS);
15135 /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX
15136 otherwise. If INSN has two call rtx, then store the second one in
15140 mips_call_expr_from_insn (rtx insn, rtx *second_call)
15145 if (!CALL_P (insn))
15148 x = PATTERN (insn);
15149 if (GET_CODE (x) == PARALLEL)
15151 /* Calls returning complex values have two CALL rtx. Look for the second
15152 one here, and return it via the SECOND_CALL arg. */
15153 x2 = XVECEXP (x, 0, 1);
15154 if (GET_CODE (x2) == SET)
15156 if (GET_CODE (x2) == CALL)
15159 x = XVECEXP (x, 0, 0);
15161 if (GET_CODE (x) == SET)
15163 gcc_assert (GET_CODE (x) == CALL);
15168 /* REG is set in DEF. See if the definition is one of the ways we load a
15169 register with a symbol address for a mips_use_pic_fn_addr_reg_p call.
15170 If it is, return the symbol reference of the function, otherwise return
15173 If RECURSE_P is true, use mips_find_pic_call_symbol to interpret
15174 the values of source registers, otherwise treat such registers as
15175 having an unknown value. */
15178 mips_pic_call_symbol_from_set (df_ref def, rtx reg, bool recurse_p)
15182 if (DF_REF_IS_ARTIFICIAL (def))
15185 def_insn = DF_REF_INSN (def);
15186 set = single_set (def_insn);
15187 if (set && rtx_equal_p (SET_DEST (set), reg))
15189 rtx note, src, symbol;
15191 /* First see whether the source is a plain symbol. This is used
15192 when calling symbols that are not lazily bound. */
15193 src = SET_SRC (set);
15194 if (GET_CODE (src) == SYMBOL_REF)
15197 /* Handle %call16 references. */
15198 symbol = mips_strip_unspec_call (src);
15201 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
15205 /* If we have something more complicated, look for a
15206 REG_EQUAL or REG_EQUIV note. */
15207 note = find_reg_equal_equiv_note (def_insn);
15208 if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF)
15209 return XEXP (note, 0);
15211 /* Follow at most one simple register copy. Such copies are
15212 interesting in cases like:
15216 locally_binding_fn (...);
15221 locally_binding_fn (...);
15223 locally_binding_fn (...);
15225 where the load of locally_binding_fn can legitimately be
15226 hoisted or shared. However, we do not expect to see complex
15227 chains of copies, so a full worklist solution to the problem
15228 would probably be overkill. */
15229 if (recurse_p && REG_P (src))
15230 return mips_find_pic_call_symbol (def_insn, src, false);
15236 /* Find the definition of the use of REG in INSN. See if the definition
15237 is one of the ways we load a register with a symbol address for a
15238 mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference
15239 of the function, otherwise return NULL_RTX. RECURSE_P is as for
15240 mips_pic_call_symbol_from_set. */
15243 mips_find_pic_call_symbol (rtx insn, rtx reg, bool recurse_p)
15246 struct df_link *defs;
15249 use = df_find_use (insn, regno_reg_rtx[REGNO (reg)]);
15252 defs = DF_REF_CHAIN (use);
15255 symbol = mips_pic_call_symbol_from_set (defs->ref, reg, recurse_p);
15259 /* If we have more than one definition, they need to be identical. */
15260 for (defs = defs->next; defs; defs = defs->next)
15264 other = mips_pic_call_symbol_from_set (defs->ref, reg, recurse_p);
15265 if (!rtx_equal_p (symbol, other))
15272 /* Replace the args_size operand of the call expression CALL with the
15273 call-attribute UNSPEC and fill in SYMBOL as the function symbol. */
15276 mips_annotate_pic_call_expr (rtx call, rtx symbol)
15280 args_size = XEXP (call, 1);
15281 XEXP (call, 1) = gen_rtx_UNSPEC (GET_MODE (args_size),
15282 gen_rtvec (2, args_size, symbol),
15286 /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See
15287 if instead of the arg_size argument it contains the call attributes. If
15288 yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function
15289 symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is
15293 mips_get_pic_call_symbol (rtx *operands, int args_size_opno)
15295 rtx args_size, symbol;
15297 if (!TARGET_RELAX_PIC_CALLS || args_size_opno == -1)
15300 args_size = operands[args_size_opno];
15301 if (GET_CODE (args_size) != UNSPEC)
15303 gcc_assert (XINT (args_size, 1) == UNSPEC_CALL_ATTR);
15305 symbol = XVECEXP (args_size, 0, 1);
15306 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
15308 operands[args_size_opno] = symbol;
15312 /* Use DF to annotate PIC indirect calls with the function symbol they
15316 mips_annotate_pic_calls (void)
15322 FOR_BB_INSNS (bb, insn)
15324 rtx call, reg, symbol, second_call;
15327 call = mips_call_expr_from_insn (insn, &second_call);
15330 gcc_assert (MEM_P (XEXP (call, 0)));
15331 reg = XEXP (XEXP (call, 0), 0);
15335 symbol = mips_find_pic_call_symbol (insn, reg, true);
15338 mips_annotate_pic_call_expr (call, symbol);
15340 mips_annotate_pic_call_expr (second_call, symbol);
15345 /* A temporary variable used by for_each_rtx callbacks, etc. */
15346 static rtx mips_sim_insn;
15348 /* A structure representing the state of the processor pipeline.
15349 Used by the mips_sim_* family of functions. */
15351 /* The maximum number of instructions that can be issued in a cycle.
15352 (Caches mips_issue_rate.) */
15353 unsigned int issue_rate;
15355 /* The current simulation time. */
15358 /* How many more instructions can be issued in the current cycle. */
15359 unsigned int insns_left;
15361 /* LAST_SET[X].INSN is the last instruction to set register X.
15362 LAST_SET[X].TIME is the time at which that instruction was issued.
15363 INSN is null if no instruction has yet set register X. */
15367 } last_set[FIRST_PSEUDO_REGISTER];
15369 /* The pipeline's current DFA state. */
15373 /* Reset STATE to the initial simulation state. */
15376 mips_sim_reset (struct mips_sim *state)
15378 curr_state = state->dfa_state;
15381 state->insns_left = state->issue_rate;
15382 memset (&state->last_set, 0, sizeof (state->last_set));
15383 state_reset (curr_state);
15385 targetm.sched.init (0, false, 0);
15386 advance_state (curr_state);
15389 /* Initialize STATE before its first use. DFA_STATE points to an
15390 allocated but uninitialized DFA state. */
15393 mips_sim_init (struct mips_sim *state, state_t dfa_state)
15395 if (targetm.sched.init_dfa_pre_cycle_insn)
15396 targetm.sched.init_dfa_pre_cycle_insn ();
15398 if (targetm.sched.init_dfa_post_cycle_insn)
15399 targetm.sched.init_dfa_post_cycle_insn ();
15401 state->issue_rate = mips_issue_rate ();
15402 state->dfa_state = dfa_state;
15403 mips_sim_reset (state);
15406 /* Advance STATE by one clock cycle. */
15409 mips_sim_next_cycle (struct mips_sim *state)
15411 curr_state = state->dfa_state;
15414 state->insns_left = state->issue_rate;
15415 advance_state (curr_state);
15418 /* Advance simulation state STATE until instruction INSN can read
15422 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
15424 unsigned int regno, end_regno;
15426 end_regno = END_REGNO (reg);
15427 for (regno = REGNO (reg); regno < end_regno; regno++)
15428 if (state->last_set[regno].insn != 0)
15432 t = (state->last_set[regno].time
15433 + insn_latency (state->last_set[regno].insn, insn));
15434 while (state->time < t)
15435 mips_sim_next_cycle (state);
15439 /* A for_each_rtx callback. If *X is a register, advance simulation state
15440 DATA until mips_sim_insn can read the register's value. */
15443 mips_sim_wait_regs_2 (rtx *x, void *data)
15446 mips_sim_wait_reg ((struct mips_sim *) data, mips_sim_insn, *x);
15450 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
15453 mips_sim_wait_regs_1 (rtx *x, void *data)
15455 for_each_rtx (x, mips_sim_wait_regs_2, data);
15458 /* Advance simulation state STATE until all of INSN's register
15459 dependencies are satisfied. */
15462 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
15464 mips_sim_insn = insn;
15465 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
15468 /* Advance simulation state STATE until the units required by
15469 instruction INSN are available. */
15472 mips_sim_wait_units (struct mips_sim *state, rtx insn)
15476 tmp_state = alloca (state_size ());
15477 while (state->insns_left == 0
15478 || (memcpy (tmp_state, state->dfa_state, state_size ()),
15479 state_transition (tmp_state, insn) >= 0))
15480 mips_sim_next_cycle (state);
15483 /* Advance simulation state STATE until INSN is ready to issue. */
15486 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
15488 mips_sim_wait_regs (state, insn);
15489 mips_sim_wait_units (state, insn);
15492 /* mips_sim_insn has just set X. Update the LAST_SET array
15493 in simulation state DATA. */
15496 mips_sim_record_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
15498 struct mips_sim *state;
15500 state = (struct mips_sim *) data;
15503 unsigned int regno, end_regno;
15505 end_regno = END_REGNO (x);
15506 for (regno = REGNO (x); regno < end_regno; regno++)
15508 state->last_set[regno].insn = mips_sim_insn;
15509 state->last_set[regno].time = state->time;
15514 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
15515 can issue immediately (i.e., that mips_sim_wait_insn has already
15519 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
15521 curr_state = state->dfa_state;
15523 state_transition (curr_state, insn);
15524 state->insns_left = targetm.sched.variable_issue (0, false, insn,
15525 state->insns_left);
15527 mips_sim_insn = insn;
15528 note_stores (PATTERN (insn), mips_sim_record_set, state);
15531 /* Simulate issuing a NOP in state STATE. */
15534 mips_sim_issue_nop (struct mips_sim *state)
15536 if (state->insns_left == 0)
15537 mips_sim_next_cycle (state);
15538 state->insns_left--;
15541 /* Update simulation state STATE so that it's ready to accept the instruction
15542 after INSN. INSN should be part of the main rtl chain, not a member of a
15546 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
15548 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
15550 mips_sim_issue_nop (state);
15552 switch (GET_CODE (SEQ_BEGIN (insn)))
15556 /* We can't predict the processor state after a call or label. */
15557 mips_sim_reset (state);
15561 /* The delay slots of branch likely instructions are only executed
15562 when the branch is taken. Therefore, if the caller has simulated
15563 the delay slot instruction, STATE does not really reflect the state
15564 of the pipeline for the instruction after the delay slot. Also,
15565 branch likely instructions tend to incur a penalty when not taken,
15566 so there will probably be an extra delay between the branch and
15567 the instruction after the delay slot. */
15568 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
15569 mips_sim_reset (state);
15577 /* Use simulator state STATE to calculate the execution time of
15578 instruction sequence SEQ. */
15580 static unsigned int
15581 mips_seq_time (struct mips_sim *state, rtx seq)
15583 mips_sim_reset (state);
15584 for (rtx insn = seq; insn; insn = NEXT_INSN (insn))
15586 mips_sim_wait_insn (state, insn);
15587 mips_sim_issue_insn (state, insn);
15589 return state->time;
15592 /* Return the execution-time cost of mips_tuning_info.fast_mult_zero_zero_p
15593 setting SETTING, using STATE to simulate instruction sequences. */
15595 static unsigned int
15596 mips_mult_zero_zero_cost (struct mips_sim *state, bool setting)
15598 mips_tuning_info.fast_mult_zero_zero_p = setting;
15601 enum machine_mode dword_mode = TARGET_64BIT ? TImode : DImode;
15602 rtx hilo = gen_rtx_REG (dword_mode, MD_REG_FIRST);
15603 mips_emit_move_or_split (hilo, const0_rtx, SPLIT_FOR_SPEED);
15605 /* If the target provides mulsidi3_32bit then that's the most likely
15606 consumer of the result. Test for bypasses. */
15607 if (dword_mode == DImode && HAVE_maddsidi4)
15609 rtx gpr = gen_rtx_REG (SImode, GP_REG_FIRST + 4);
15610 emit_insn (gen_maddsidi4 (hilo, gpr, gpr, hilo));
15613 unsigned int time = mips_seq_time (state, get_insns ());
15618 /* Check the relative speeds of "MULT $0,$0" and "MTLO $0; MTHI $0"
15619 and set up mips_tuning_info.fast_mult_zero_zero_p accordingly.
15620 Prefer MULT -- which is shorter -- in the event of a tie. */
15623 mips_set_fast_mult_zero_zero_p (struct mips_sim *state)
15626 /* No MTLO or MTHI available. */
15627 mips_tuning_info.fast_mult_zero_zero_p = true;
15630 unsigned int true_time = mips_mult_zero_zero_cost (state, true);
15631 unsigned int false_time = mips_mult_zero_zero_cost (state, false);
15632 mips_tuning_info.fast_mult_zero_zero_p = (true_time <= false_time);
15636 /* Set up costs based on the current architecture and tuning settings. */
15639 mips_set_tuning_info (void)
15641 if (mips_tuning_info.initialized_p
15642 && mips_tuning_info.arch == mips_arch
15643 && mips_tuning_info.tune == mips_tune
15644 && mips_tuning_info.mips16_p == TARGET_MIPS16)
15647 mips_tuning_info.arch = mips_arch;
15648 mips_tuning_info.tune = mips_tune;
15649 mips_tuning_info.mips16_p = TARGET_MIPS16;
15650 mips_tuning_info.initialized_p = true;
15654 struct mips_sim state;
15655 mips_sim_init (&state, alloca (state_size ()));
15657 mips_set_fast_mult_zero_zero_p (&state);
15662 /* Implement TARGET_EXPAND_TO_RTL_HOOK. */
15665 mips_expand_to_rtl_hook (void)
15667 /* We need to call this at a point where we can safely create sequences
15668 of instructions, so TARGET_OVERRIDE_OPTIONS is too early. We also
15669 need to call it at a point where the DFA infrastructure is not
15670 already in use, so we can't just call it lazily on demand.
15672 At present, mips_tuning_info is only needed during post-expand
15673 RTL passes such as split_insns, so this hook should be early enough.
15674 We may need to move the call elsewhere if mips_tuning_info starts
15675 to be used for other things (such as rtx_costs, or expanders that
15676 could be called during gimple optimization). */
15677 mips_set_tuning_info ();
15680 /* The VR4130 pipeline issues aligned pairs of instructions together,
15681 but it stalls the second instruction if it depends on the first.
15682 In order to cut down the amount of logic required, this dependence
15683 check is not based on a full instruction decode. Instead, any non-SPECIAL
15684 instruction is assumed to modify the register specified by bits 20-16
15685 (which is usually the "rt" field).
15687 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
15688 input, so we can end up with a false dependence between the branch
15689 and its delay slot. If this situation occurs in instruction INSN,
15690 try to avoid it by swapping rs and rt. */
15693 vr4130_avoid_branch_rt_conflict (rtx insn)
15697 first = SEQ_BEGIN (insn);
15698 second = SEQ_END (insn);
15700 && NONJUMP_INSN_P (second)
15701 && GET_CODE (PATTERN (first)) == SET
15702 && GET_CODE (SET_DEST (PATTERN (first))) == PC
15703 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
15705 /* Check for the right kind of condition. */
15706 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
15707 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
15708 && REG_P (XEXP (cond, 0))
15709 && REG_P (XEXP (cond, 1))
15710 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
15711 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
15713 /* SECOND mentions the rt register but not the rs register. */
15714 rtx tmp = XEXP (cond, 0);
15715 XEXP (cond, 0) = XEXP (cond, 1);
15716 XEXP (cond, 1) = tmp;
15721 /* Implement -mvr4130-align. Go through each basic block and simulate the
15722 processor pipeline. If we find that a pair of instructions could execute
15723 in parallel, and the first of those instructions is not 8-byte aligned,
15724 insert a nop to make it aligned. */
15727 vr4130_align_insns (void)
15729 struct mips_sim state;
15730 rtx insn, subinsn, last, last2, next;
15735 /* LAST is the last instruction before INSN to have a nonzero length.
15736 LAST2 is the last such instruction before LAST. */
15740 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
15743 mips_sim_init (&state, alloca (state_size ()));
15744 for (insn = get_insns (); insn != 0; insn = next)
15746 unsigned int length;
15748 next = NEXT_INSN (insn);
15750 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
15751 This isn't really related to the alignment pass, but we do it on
15752 the fly to avoid a separate instruction walk. */
15753 vr4130_avoid_branch_rt_conflict (insn);
15755 length = get_attr_length (insn);
15756 if (length > 0 && USEFUL_INSN_P (insn))
15757 FOR_EACH_SUBINSN (subinsn, insn)
15759 mips_sim_wait_insn (&state, subinsn);
15761 /* If we want this instruction to issue in parallel with the
15762 previous one, make sure that the previous instruction is
15763 aligned. There are several reasons why this isn't worthwhile
15764 when the second instruction is a call:
15766 - Calls are less likely to be performance critical,
15767 - There's a good chance that the delay slot can execute
15768 in parallel with the call.
15769 - The return address would then be unaligned.
15771 In general, if we're going to insert a nop between instructions
15772 X and Y, it's better to insert it immediately after X. That
15773 way, if the nop makes Y aligned, it will also align any labels
15774 between X and Y. */
15775 if (state.insns_left != state.issue_rate
15776 && !CALL_P (subinsn))
15778 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
15780 /* SUBINSN is the first instruction in INSN and INSN is
15781 aligned. We want to align the previous instruction
15782 instead, so insert a nop between LAST2 and LAST.
15784 Note that LAST could be either a single instruction
15785 or a branch with a delay slot. In the latter case,
15786 LAST, like INSN, is already aligned, but the delay
15787 slot must have some extra delay that stops it from
15788 issuing at the same time as the branch. We therefore
15789 insert a nop before the branch in order to align its
15791 gcc_assert (last2);
15792 emit_insn_after (gen_nop (), last2);
15795 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
15797 /* SUBINSN is the delay slot of INSN, but INSN is
15798 currently unaligned. Insert a nop between
15799 LAST and INSN to align it. */
15801 emit_insn_after (gen_nop (), last);
15805 mips_sim_issue_insn (&state, subinsn);
15807 mips_sim_finish_insn (&state, insn);
15809 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
15810 length = get_attr_length (insn);
15813 /* If the instruction is an asm statement or multi-instruction
15814 mips.md patern, the length is only an estimate. Insert an
15815 8 byte alignment after it so that the following instructions
15816 can be handled correctly. */
15817 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
15818 && (recog_memoized (insn) < 0 || length >= 8))
15820 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
15821 next = NEXT_INSN (next);
15822 mips_sim_next_cycle (&state);
15825 else if (length & 4)
15826 aligned_p = !aligned_p;
15831 /* See whether INSN is an aligned label. */
15832 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
15838 /* This structure records that the current function has a LO_SUM
15839 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
15840 the largest offset applied to BASE by all such LO_SUMs. */
15841 struct mips_lo_sum_offset {
15843 HOST_WIDE_INT offset;
15846 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
15849 mips_hash_base (rtx base)
15851 int do_not_record_p;
15853 return hash_rtx (base, GET_MODE (base), &do_not_record_p, NULL, false);
15856 /* Hashtable helpers. */
15858 struct mips_lo_sum_offset_hasher : typed_free_remove <mips_lo_sum_offset>
15860 typedef mips_lo_sum_offset value_type;
15861 typedef rtx_def compare_type;
15862 static inline hashval_t hash (const value_type *);
15863 static inline bool equal (const value_type *, const compare_type *);
15866 /* Hash-table callbacks for mips_lo_sum_offsets. */
15869 mips_lo_sum_offset_hasher::hash (const value_type *entry)
15871 return mips_hash_base (entry->base);
15875 mips_lo_sum_offset_hasher::equal (const value_type *entry,
15876 const compare_type *value)
15878 return rtx_equal_p (entry->base, value);
15881 typedef hash_table <mips_lo_sum_offset_hasher> mips_offset_table;
15883 /* Look up symbolic constant X in HTAB, which is a hash table of
15884 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
15885 paired with a recorded LO_SUM, otherwise record X in the table. */
15888 mips_lo_sum_offset_lookup (mips_offset_table htab, rtx x,
15889 enum insert_option option)
15892 mips_lo_sum_offset **slot;
15893 struct mips_lo_sum_offset *entry;
15895 /* Split X into a base and offset. */
15896 split_const (x, &base, &offset);
15897 if (UNSPEC_ADDRESS_P (base))
15898 base = UNSPEC_ADDRESS (base);
15900 /* Look up the base in the hash table. */
15901 slot = htab.find_slot_with_hash (base, mips_hash_base (base), option);
15905 entry = (struct mips_lo_sum_offset *) *slot;
15906 if (option == INSERT)
15910 entry = XNEW (struct mips_lo_sum_offset);
15911 entry->base = base;
15912 entry->offset = INTVAL (offset);
15917 if (INTVAL (offset) > entry->offset)
15918 entry->offset = INTVAL (offset);
15921 return INTVAL (offset) <= entry->offset;
15924 /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table.
15925 Record every LO_SUM in *LOC. */
15928 mips_record_lo_sum (rtx *loc, void *data)
15930 if (GET_CODE (*loc) == LO_SUM)
15931 mips_lo_sum_offset_lookup (*(mips_offset_table*) data,
15932 XEXP (*loc, 1), INSERT);
15936 /* Return true if INSN is a SET of an orphaned high-part relocation.
15937 HTAB is a hash table of mips_lo_sum_offsets that describes all the
15938 LO_SUMs in the current function. */
15941 mips_orphaned_high_part_p (mips_offset_table htab, rtx insn)
15943 enum mips_symbol_type type;
15946 set = single_set (insn);
15949 /* Check for %his. */
15951 if (GET_CODE (x) == HIGH
15952 && absolute_symbolic_operand (XEXP (x, 0), VOIDmode))
15953 return !mips_lo_sum_offset_lookup (htab, XEXP (x, 0), NO_INSERT);
15955 /* Check for local %gots (and %got_pages, which is redundant but OK). */
15956 if (GET_CODE (x) == UNSPEC
15957 && XINT (x, 1) == UNSPEC_LOAD_GOT
15958 && mips_symbolic_constant_p (XVECEXP (x, 0, 1),
15959 SYMBOL_CONTEXT_LEA, &type)
15960 && type == SYMBOL_GOTOFF_PAGE)
15961 return !mips_lo_sum_offset_lookup (htab, XVECEXP (x, 0, 1), NO_INSERT);
15966 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
15967 INSN and a previous instruction, avoid it by inserting nops after
15970 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
15971 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
15972 before using the value of that register. *HILO_DELAY counts the
15973 number of instructions since the last hilo hazard (that is,
15974 the number of instructions since the last MFLO or MFHI).
15976 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
15977 for the next instruction.
15979 LO_REG is an rtx for the LO register, used in dependence checking. */
15982 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
15983 rtx *delayed_reg, rtx lo_reg)
15988 pattern = PATTERN (insn);
15990 /* Do not put the whole function in .set noreorder if it contains
15991 an asm statement. We don't know whether there will be hazards
15992 between the asm statement and the gcc-generated code. */
15993 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
15994 cfun->machine->all_noreorder_p = false;
15996 /* Ignore zero-length instructions (barriers and the like). */
15997 ninsns = get_attr_length (insn) / 4;
16001 /* Work out how many nops are needed. Note that we only care about
16002 registers that are explicitly mentioned in the instruction's pattern.
16003 It doesn't matter that calls use the argument registers or that they
16004 clobber hi and lo. */
16005 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
16006 nops = 2 - *hilo_delay;
16007 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
16012 /* Insert the nops between this instruction and the previous one.
16013 Each new nop takes us further from the last hilo hazard. */
16014 *hilo_delay += nops;
16016 emit_insn_after (gen_hazard_nop (), after);
16018 /* Set up the state for the next instruction. */
16019 *hilo_delay += ninsns;
16021 if (INSN_CODE (insn) >= 0)
16022 switch (get_attr_hazard (insn))
16032 set = single_set (insn);
16034 *delayed_reg = SET_DEST (set);
16039 /* Go through the instruction stream and insert nops where necessary.
16040 Also delete any high-part relocations whose partnering low parts
16041 are now all dead. See if the whole function can then be put into
16042 .set noreorder and .set nomacro. */
16045 mips_reorg_process_insns (void)
16047 rtx insn, last_insn, subinsn, next_insn, lo_reg, delayed_reg;
16049 mips_offset_table htab;
16051 /* Force all instructions to be split into their final form. */
16052 split_all_insns_noflow ();
16054 /* Recalculate instruction lengths without taking nops into account. */
16055 cfun->machine->ignore_hazard_length_p = true;
16056 shorten_branches (get_insns ());
16058 cfun->machine->all_noreorder_p = true;
16060 /* We don't track MIPS16 PC-relative offsets closely enough to make
16061 a good job of "set .noreorder" code in MIPS16 mode. */
16063 cfun->machine->all_noreorder_p = false;
16065 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
16066 if (!TARGET_EXPLICIT_RELOCS)
16067 cfun->machine->all_noreorder_p = false;
16069 /* Profiled functions can't be all noreorder because the profiler
16070 support uses assembler macros. */
16072 cfun->machine->all_noreorder_p = false;
16074 /* Code compiled with -mfix-vr4120 or -mfix-24k can't be all noreorder
16075 because we rely on the assembler to work around some errata.
16076 The r5900 too has several bugs. */
16077 if (TARGET_FIX_VR4120 || TARGET_FIX_24K || TARGET_MIPS5900)
16078 cfun->machine->all_noreorder_p = false;
16080 /* The same is true for -mfix-vr4130 if we might generate MFLO or
16081 MFHI instructions. Note that we avoid using MFLO and MFHI if
16082 the VR4130 MACC and DMACC instructions are available instead;
16083 see the *mfhilo_{si,di}_macc patterns. */
16084 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
16085 cfun->machine->all_noreorder_p = false;
16089 /* Make a first pass over the instructions, recording all the LO_SUMs. */
16090 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
16091 FOR_EACH_SUBINSN (subinsn, insn)
16092 if (USEFUL_INSN_P (subinsn))
16093 for_each_rtx (&PATTERN (subinsn), mips_record_lo_sum, &htab);
16098 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
16100 /* Make a second pass over the instructions. Delete orphaned
16101 high-part relocations or turn them into NOPs. Avoid hazards
16102 by inserting NOPs. */
16103 for (insn = get_insns (); insn != 0; insn = next_insn)
16105 next_insn = NEXT_INSN (insn);
16106 if (USEFUL_INSN_P (insn))
16108 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
16110 /* If we find an orphaned high-part relocation in a delay
16111 slot, it's easier to turn that instruction into a NOP than
16112 to delete it. The delay slot will be a NOP either way. */
16113 FOR_EACH_SUBINSN (subinsn, insn)
16114 if (INSN_P (subinsn))
16116 if (mips_orphaned_high_part_p (htab, subinsn))
16118 PATTERN (subinsn) = gen_nop ();
16119 INSN_CODE (subinsn) = CODE_FOR_nop;
16121 mips_avoid_hazard (last_insn, subinsn, &hilo_delay,
16122 &delayed_reg, lo_reg);
16128 /* INSN is a single instruction. Delete it if it's an
16129 orphaned high-part relocation. */
16130 if (mips_orphaned_high_part_p (htab, insn))
16131 delete_insn (insn);
16132 /* Also delete cache barriers if the last instruction
16133 was an annulled branch. INSN will not be speculatively
16135 else if (recog_memoized (insn) == CODE_FOR_r10k_cache_barrier
16137 && JUMP_P (SEQ_BEGIN (last_insn))
16138 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn)))
16139 delete_insn (insn);
16142 mips_avoid_hazard (last_insn, insn, &hilo_delay,
16143 &delayed_reg, lo_reg);
16153 /* Return true if the function has a long branch instruction. */
16156 mips_has_long_branch_p (void)
16161 /* We need up-to-date instruction lengths. */
16162 shorten_branches (get_insns ());
16164 /* Look for a branch that is longer than normal. The normal length for
16165 non-MIPS16 branches is 8, because the length includes the delay slot.
16166 It is 4 for MIPS16, because MIPS16 branches are extended instructions,
16167 but they have no delay slot. */
16168 normal_length = (TARGET_MIPS16 ? 4 : 8);
16169 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
16170 FOR_EACH_SUBINSN (subinsn, insn)
16171 if (JUMP_P (subinsn)
16172 && get_attr_length (subinsn) > normal_length
16173 && (any_condjump_p (subinsn) || any_uncondjump_p (subinsn)))
16179 /* If we are using a GOT, but have not decided to use a global pointer yet,
16180 see whether we need one to implement long branches. Convert the ghost
16181 global-pointer instructions into real ones if so. */
16184 mips_expand_ghost_gp_insns (void)
16186 /* Quick exit if we already know that we will or won't need a
16188 if (!TARGET_USE_GOT
16189 || cfun->machine->global_pointer == INVALID_REGNUM
16190 || mips_must_initialize_gp_p ())
16193 /* Run a full check for long branches. */
16194 if (!mips_has_long_branch_p ())
16197 /* We've now established that we need $gp. */
16198 cfun->machine->must_initialize_gp_p = true;
16199 split_all_insns_noflow ();
16204 /* Subroutine of mips_reorg to manage passes that require DF. */
16207 mips_df_reorg (void)
16209 /* Create def-use chains. */
16210 df_set_flags (DF_EQ_NOTES);
16211 df_chain_add_problem (DF_UD_CHAIN);
16214 if (TARGET_RELAX_PIC_CALLS)
16215 mips_annotate_pic_calls ();
16217 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE)
16218 r10k_insert_cache_barriers ();
16220 df_finish_pass (false);
16223 /* Emit code to load LABEL_REF SRC into MIPS16 register DEST. This is
16224 called very late in mips_reorg, but the caller is required to run
16225 mips16_lay_out_constants on the result. */
16228 mips16_load_branch_target (rtx dest, rtx src)
16230 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
16234 if (mips_cfun_has_cprestore_slot_p ())
16235 mips_emit_move (dest, mips_cprestore_slot (dest, true));
16237 mips_emit_move (dest, pic_offset_table_rtx);
16238 page = mips_unspec_address (src, SYMBOL_GOTOFF_PAGE);
16239 low = mips_unspec_address (src, SYMBOL_GOT_PAGE_OFST);
16240 emit_insn (gen_rtx_SET (VOIDmode, dest,
16241 PMODE_INSN (gen_unspec_got, (dest, page))));
16242 emit_insn (gen_rtx_SET (VOIDmode, dest,
16243 gen_rtx_LO_SUM (Pmode, dest, low)));
16247 src = mips_unspec_address (src, SYMBOL_ABSOLUTE);
16248 mips_emit_move (dest, src);
16252 /* If we're compiling a MIPS16 function, look for and split any long branches.
16253 This must be called after all other instruction modifications in
16257 mips16_split_long_branches (void)
16259 bool something_changed;
16261 if (!TARGET_MIPS16)
16264 /* Loop until the alignments for all targets are sufficient. */
16269 shorten_branches (get_insns ());
16270 something_changed = false;
16271 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
16273 && get_attr_length (insn) > 4
16274 && (any_condjump_p (insn) || any_uncondjump_p (insn)))
16276 rtx old_label, new_label, temp, saved_temp;
16277 rtx target, jump, jump_sequence;
16281 /* Free up a MIPS16 register by saving it in $1. */
16282 saved_temp = gen_rtx_REG (Pmode, AT_REGNUM);
16283 temp = gen_rtx_REG (Pmode, GP_REG_FIRST + 2);
16284 emit_move_insn (saved_temp, temp);
16286 /* Load the branch target into TEMP. */
16287 old_label = JUMP_LABEL (insn);
16288 target = gen_rtx_LABEL_REF (Pmode, old_label);
16289 mips16_load_branch_target (temp, target);
16291 /* Jump to the target and restore the register's
16293 jump = emit_jump_insn (PMODE_INSN (gen_indirect_jump_and_restore,
16294 (temp, temp, saved_temp)));
16295 JUMP_LABEL (jump) = old_label;
16296 LABEL_NUSES (old_label)++;
16298 /* Rewrite any symbolic references that are supposed to use
16299 a PC-relative constant pool. */
16300 mips16_lay_out_constants (false);
16302 if (simplejump_p (insn))
16303 /* We're going to replace INSN with a longer form. */
16304 new_label = NULL_RTX;
16307 /* Create a branch-around label for the original
16309 new_label = gen_label_rtx ();
16310 emit_label (new_label);
16313 jump_sequence = get_insns ();
16316 emit_insn_after (jump_sequence, insn);
16318 invert_jump (insn, new_label, false);
16320 delete_insn (insn);
16321 something_changed = true;
16324 while (something_changed);
16327 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
16332 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during
16333 insn splitting in mips16_lay_out_constants, DF insn info is only kept up
16334 to date if the CFG is available. */
16335 if (mips_cfg_in_reorg ())
16336 compute_bb_for_insn ();
16337 mips16_lay_out_constants (true);
16338 if (mips_cfg_in_reorg ())
16341 free_bb_for_insn ();
16345 /* We use a machine specific pass to do a second machine dependent reorg
16346 pass after delay branch scheduling. */
16348 static unsigned int
16349 mips_machine_reorg2 (void)
16351 mips_reorg_process_insns ();
16353 && TARGET_EXPLICIT_RELOCS
16355 && TARGET_VR4130_ALIGN)
16356 vr4130_align_insns ();
16357 if (mips_expand_ghost_gp_insns ())
16358 /* The expansion could invalidate some of the VR4130 alignment
16359 optimizations, but this should be an extremely rare case anyhow. */
16360 mips_reorg_process_insns ();
16361 mips16_split_long_branches ();
16367 const pass_data pass_data_mips_machine_reorg2 =
16369 RTL_PASS, /* type */
16370 "mach2", /* name */
16371 OPTGROUP_NONE, /* optinfo_flags */
16372 false, /* has_gate */
16373 true, /* has_execute */
16374 TV_MACH_DEP, /* tv_id */
16375 0, /* properties_required */
16376 0, /* properties_provided */
16377 0, /* properties_destroyed */
16378 0, /* todo_flags_start */
16379 TODO_verify_rtl_sharing, /* todo_flags_finish */
16382 class pass_mips_machine_reorg2 : public rtl_opt_pass
16385 pass_mips_machine_reorg2(gcc::context *ctxt)
16386 : rtl_opt_pass(pass_data_mips_machine_reorg2, ctxt)
16389 /* opt_pass methods: */
16390 unsigned int execute () { return mips_machine_reorg2 (); }
16392 }; // class pass_mips_machine_reorg2
16394 } // anon namespace
16397 make_pass_mips_machine_reorg2 (gcc::context *ctxt)
16399 return new pass_mips_machine_reorg2 (ctxt);
16403 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
16404 in order to avoid duplicating too much logic from elsewhere. */
16407 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
16408 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
16411 rtx this_rtx, temp1, temp2, insn, fnaddr;
16412 bool use_sibcall_p;
16414 /* Pretend to be a post-reload pass while generating rtl. */
16415 reload_completed = 1;
16417 /* Mark the end of the (empty) prologue. */
16418 emit_note (NOTE_INSN_PROLOGUE_END);
16420 /* Determine if we can use a sibcall to call FUNCTION directly. */
16421 fnaddr = XEXP (DECL_RTL (function), 0);
16422 use_sibcall_p = (mips_function_ok_for_sibcall (function, NULL)
16423 && const_call_insn_operand (fnaddr, Pmode));
16425 /* Determine if we need to load FNADDR from the GOT. */
16427 && (mips_got_symbol_type_p
16428 (mips_classify_symbol (fnaddr, SYMBOL_CONTEXT_LEA))))
16430 /* Pick a global pointer. Use a call-clobbered register if
16431 TARGET_CALL_SAVED_GP. */
16432 cfun->machine->global_pointer
16433 = TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM;
16434 cfun->machine->must_initialize_gp_p = true;
16435 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
16437 /* Set up the global pointer for n32 or n64 abicalls. */
16438 mips_emit_loadgp ();
16441 /* We need two temporary registers in some cases. */
16442 temp1 = gen_rtx_REG (Pmode, 2);
16443 temp2 = gen_rtx_REG (Pmode, 3);
16445 /* Find out which register contains the "this" pointer. */
16446 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
16447 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
16449 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST);
16451 /* Add DELTA to THIS_RTX. */
16454 rtx offset = GEN_INT (delta);
16455 if (!SMALL_OPERAND (delta))
16457 mips_emit_move (temp1, offset);
16460 emit_insn (gen_add3_insn (this_rtx, this_rtx, offset));
16463 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
16464 if (vcall_offset != 0)
16468 /* Set TEMP1 to *THIS_RTX. */
16469 mips_emit_move (temp1, gen_rtx_MEM (Pmode, this_rtx));
16471 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
16472 addr = mips_add_offset (temp2, temp1, vcall_offset);
16474 /* Load the offset and add it to THIS_RTX. */
16475 mips_emit_move (temp1, gen_rtx_MEM (Pmode, addr));
16476 emit_insn (gen_add3_insn (this_rtx, this_rtx, temp1));
16479 /* Jump to the target function. Use a sibcall if direct jumps are
16480 allowed, otherwise load the address into a register first. */
16483 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
16484 SIBLING_CALL_P (insn) = 1;
16488 /* This is messy. GAS treats "la $25,foo" as part of a call
16489 sequence and may allow a global "foo" to be lazily bound.
16490 The general move patterns therefore reject this combination.
16492 In this context, lazy binding would actually be OK
16493 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
16494 TARGET_CALL_SAVED_GP; see mips_load_call_address.
16495 We must therefore load the address via a temporary
16496 register if mips_dangerous_for_la25_p.
16498 If we jump to the temporary register rather than $25,
16499 the assembler can use the move insn to fill the jump's
16502 We can use the same technique for MIPS16 code, where $25
16503 is not a valid JR register. */
16504 if (TARGET_USE_PIC_FN_ADDR_REG
16506 && !mips_dangerous_for_la25_p (fnaddr))
16507 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
16508 mips_load_call_address (MIPS_CALL_SIBCALL, temp1, fnaddr);
16510 if (TARGET_USE_PIC_FN_ADDR_REG
16511 && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
16512 mips_emit_move (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
16513 emit_jump_insn (gen_indirect_jump (temp1));
16516 /* Run just enough of rest_of_compilation. This sequence was
16517 "borrowed" from alpha.c. */
16518 insn = get_insns ();
16519 split_all_insns_noflow ();
16520 mips16_lay_out_constants (true);
16521 shorten_branches (insn);
16522 final_start_function (insn, file, 1);
16523 final (insn, file, 1);
16524 final_end_function ();
16526 /* Clean up the vars set above. Note that final_end_function resets
16527 the global pointer for us. */
16528 reload_completed = 0;
16532 /* The last argument passed to mips_set_compression_mode,
16533 or negative if the function hasn't been called yet. */
16534 static unsigned int old_compression_mode = -1;
16536 /* Set up the target-dependent global state for ISA mode COMPRESSION_MODE,
16537 which is either MASK_MIPS16 or MASK_MICROMIPS. */
16540 mips_set_compression_mode (unsigned int compression_mode)
16543 if (compression_mode == old_compression_mode)
16546 /* Restore base settings of various flags. */
16547 target_flags = mips_base_target_flags;
16548 flag_schedule_insns = mips_base_schedule_insns;
16549 flag_reorder_blocks_and_partition = mips_base_reorder_blocks_and_partition;
16550 flag_move_loop_invariants = mips_base_move_loop_invariants;
16551 align_loops = mips_base_align_loops;
16552 align_jumps = mips_base_align_jumps;
16553 align_functions = mips_base_align_functions;
16554 target_flags &= ~(MASK_MIPS16 | MASK_MICROMIPS);
16555 target_flags |= compression_mode;
16557 if (compression_mode & MASK_MIPS16)
16559 /* Switch to MIPS16 mode. */
16560 target_flags |= MASK_MIPS16;
16562 /* Turn off SYNCI if it was on, MIPS16 doesn't support it. */
16563 target_flags &= ~MASK_SYNCI;
16565 /* Don't run the scheduler before reload, since it tends to
16566 increase register pressure. */
16567 flag_schedule_insns = 0;
16569 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
16570 the whole function to be in a single section. */
16571 flag_reorder_blocks_and_partition = 0;
16573 /* Don't move loop invariants, because it tends to increase
16574 register pressure. It also introduces an extra move in cases
16575 where the constant is the first operand in a two-operand binary
16576 instruction, or when it forms a register argument to a functon
16578 flag_move_loop_invariants = 0;
16580 target_flags |= MASK_EXPLICIT_RELOCS;
16582 /* Experiments suggest we get the best overall section-anchor
16583 results from using the range of an unextended LW or SW. Code
16584 that makes heavy use of byte or short accesses can do better
16585 with ranges of 0...31 and 0...63 respectively, but most code is
16586 sensitive to the range of LW and SW instead. */
16587 targetm.min_anchor_offset = 0;
16588 targetm.max_anchor_offset = 127;
16590 targetm.const_anchor = 0;
16592 /* MIPS16 has no BAL instruction. */
16593 target_flags &= ~MASK_RELAX_PIC_CALLS;
16595 /* The R4000 errata don't apply to any known MIPS16 cores.
16596 It's simpler to make the R4000 fixes and MIPS16 mode
16597 mutually exclusive. */
16598 target_flags &= ~MASK_FIX_R4000;
16600 if (flag_pic && !TARGET_OLDABI)
16601 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
16604 sorry ("MIPS16 -mxgot code");
16606 if (TARGET_HARD_FLOAT_ABI && !TARGET_OLDABI)
16607 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
16611 /* Switch to microMIPS or the standard encoding. */
16613 if (TARGET_MICROMIPS)
16614 /* Avoid branch likely. */
16615 target_flags &= ~MASK_BRANCHLIKELY;
16617 /* Provide default values for align_* for 64-bit targets. */
16620 if (align_loops == 0)
16622 if (align_jumps == 0)
16624 if (align_functions == 0)
16625 align_functions = 8;
16628 targetm.min_anchor_offset = -32768;
16629 targetm.max_anchor_offset = 32767;
16631 targetm.const_anchor = 0x8000;
16634 /* (Re)initialize MIPS target internals for new ISA. */
16635 mips_init_relocs ();
16637 if (compression_mode & MASK_MIPS16)
16639 if (!mips16_globals)
16640 mips16_globals = save_target_globals_default_opts ();
16642 restore_target_globals (mips16_globals);
16645 restore_target_globals (&default_target_globals);
16647 old_compression_mode = compression_mode;
16650 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
16651 function should use the MIPS16 or microMIPS ISA and switch modes
16655 mips_set_current_function (tree fndecl)
16657 mips_set_compression_mode (mips_get_compress_mode (fndecl));
16660 /* Allocate a chunk of memory for per-function machine-dependent data. */
16662 static struct machine_function *
16663 mips_init_machine_status (void)
16665 return ggc_alloc_cleared_machine_function ();
16668 /* Return the processor associated with the given ISA level, or null
16669 if the ISA isn't valid. */
16671 static const struct mips_cpu_info *
16672 mips_cpu_info_from_isa (int isa)
16676 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
16677 if (mips_cpu_info_table[i].isa == isa)
16678 return mips_cpu_info_table + i;
16683 /* Return a mips_cpu_info entry determined by an option valued
16686 static const struct mips_cpu_info *
16687 mips_cpu_info_from_opt (int opt)
16691 case MIPS_ARCH_OPTION_FROM_ABI:
16692 /* 'from-abi' selects the most compatible architecture for the
16693 given ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit
16694 ABIs. For the EABIs, we have to decide whether we're using
16695 the 32-bit or 64-bit version. */
16696 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
16697 : ABI_NEEDS_64BIT_REGS ? 3
16698 : (TARGET_64BIT ? 3 : 1));
16700 case MIPS_ARCH_OPTION_NATIVE:
16701 gcc_unreachable ();
16704 return &mips_cpu_info_table[opt];
16708 /* Return a default mips_cpu_info entry, given that no -march= option
16709 was explicitly specified. */
16711 static const struct mips_cpu_info *
16712 mips_default_arch (void)
16714 #if defined (MIPS_CPU_STRING_DEFAULT)
16716 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
16717 if (strcmp (mips_cpu_info_table[i].name, MIPS_CPU_STRING_DEFAULT) == 0)
16718 return mips_cpu_info_table + i;
16719 gcc_unreachable ();
16720 #elif defined (MIPS_ISA_DEFAULT)
16721 return mips_cpu_info_from_isa (MIPS_ISA_DEFAULT);
16723 /* 'from-abi' makes a good default: you get whatever the ABI
16725 return mips_cpu_info_from_opt (MIPS_ARCH_OPTION_FROM_ABI);
16729 /* Set up globals to generate code for the ISA or processor
16730 described by INFO. */
16733 mips_set_architecture (const struct mips_cpu_info *info)
16737 mips_arch_info = info;
16738 mips_arch = info->cpu;
16739 mips_isa = info->isa;
16743 /* Likewise for tuning. */
16746 mips_set_tune (const struct mips_cpu_info *info)
16750 mips_tune_info = info;
16751 mips_tune = info->cpu;
16755 /* Implement TARGET_OPTION_OVERRIDE. */
16758 mips_option_override (void)
16760 int i, start, regno, mode;
16762 if (global_options_set.x_mips_isa_option)
16763 mips_isa_option_info = &mips_cpu_info_table[mips_isa_option];
16765 #ifdef SUBTARGET_OVERRIDE_OPTIONS
16766 SUBTARGET_OVERRIDE_OPTIONS;
16769 /* MIPS16 and microMIPS cannot coexist. */
16770 if (TARGET_MICROMIPS && TARGET_MIPS16)
16771 error ("unsupported combination: %s", "-mips16 -mmicromips");
16773 /* Save the base compression state and process flags as though we
16774 were generating uncompressed code. */
16775 mips_base_compression_flags = TARGET_COMPRESSION;
16776 target_flags &= ~TARGET_COMPRESSION;
16778 /* -mno-float overrides -mhard-float and -msoft-float. */
16779 if (TARGET_NO_FLOAT)
16781 target_flags |= MASK_SOFT_FLOAT_ABI;
16782 target_flags_explicit |= MASK_SOFT_FLOAT_ABI;
16785 if (TARGET_FLIP_MIPS16)
16786 TARGET_INTERLINK_COMPRESSED = 1;
16788 /* Set the small data limit. */
16789 mips_small_data_threshold = (global_options_set.x_g_switch_value
16791 : MIPS_DEFAULT_GVALUE);
16793 /* The following code determines the architecture and register size.
16794 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
16795 The GAS and GCC code should be kept in sync as much as possible. */
16797 if (global_options_set.x_mips_arch_option)
16798 mips_set_architecture (mips_cpu_info_from_opt (mips_arch_option));
16800 if (mips_isa_option_info != 0)
16802 if (mips_arch_info == 0)
16803 mips_set_architecture (mips_isa_option_info);
16804 else if (mips_arch_info->isa != mips_isa_option_info->isa)
16805 error ("%<-%s%> conflicts with the other architecture options, "
16806 "which specify a %s processor",
16807 mips_isa_option_info->name,
16808 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
16811 if (mips_arch_info == 0)
16812 mips_set_architecture (mips_default_arch ());
16814 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
16815 error ("%<-march=%s%> is not compatible with the selected ABI",
16816 mips_arch_info->name);
16818 /* Optimize for mips_arch, unless -mtune selects a different processor. */
16819 if (global_options_set.x_mips_tune_option)
16820 mips_set_tune (mips_cpu_info_from_opt (mips_tune_option));
16822 if (mips_tune_info == 0)
16823 mips_set_tune (mips_arch_info);
16825 if ((target_flags_explicit & MASK_64BIT) != 0)
16827 /* The user specified the size of the integer registers. Make sure
16828 it agrees with the ABI and ISA. */
16829 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
16830 error ("%<-mgp64%> used with a 32-bit processor");
16831 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
16832 error ("%<-mgp32%> used with a 64-bit ABI");
16833 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
16834 error ("%<-mgp64%> used with a 32-bit ABI");
16838 /* Infer the integer register size from the ABI and processor.
16839 Restrict ourselves to 32-bit registers if that's all the
16840 processor has, or if the ABI cannot handle 64-bit registers. */
16841 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
16842 target_flags &= ~MASK_64BIT;
16844 target_flags |= MASK_64BIT;
16847 if ((target_flags_explicit & MASK_FLOAT64) != 0)
16849 if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
16850 error ("unsupported combination: %s", "-mfp64 -msingle-float");
16851 else if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
16852 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
16853 else if (!TARGET_64BIT && TARGET_FLOAT64)
16855 if (!ISA_HAS_MXHC1)
16856 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
16857 " the target supports the mfhc1 and mthc1 instructions");
16858 else if (mips_abi != ABI_32)
16859 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
16865 /* -msingle-float selects 32-bit float registers. Otherwise the
16866 float registers should be the same size as the integer ones. */
16867 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
16868 target_flags |= MASK_FLOAT64;
16870 target_flags &= ~MASK_FLOAT64;
16873 /* End of code shared with GAS. */
16875 /* The R5900 FPU only supports single precision. */
16876 if (TARGET_MIPS5900 && TARGET_HARD_FLOAT_ABI && TARGET_DOUBLE_FLOAT)
16877 error ("unsupported combination: %s",
16878 "-march=r5900 -mhard-float -mdouble-float");
16880 /* If a -mlong* option was given, check that it matches the ABI,
16881 otherwise infer the -mlong* setting from the other options. */
16882 if ((target_flags_explicit & MASK_LONG64) != 0)
16886 if (mips_abi == ABI_N32)
16887 error ("%qs is incompatible with %qs", "-mabi=n32", "-mlong64");
16888 else if (mips_abi == ABI_32)
16889 error ("%qs is incompatible with %qs", "-mabi=32", "-mlong64");
16890 else if (mips_abi == ABI_O64 && TARGET_ABICALLS)
16891 /* We have traditionally allowed non-abicalls code to use
16892 an LP64 form of o64. However, it would take a bit more
16893 effort to support the combination of 32-bit GOT entries
16894 and 64-bit pointers, so we treat the abicalls case as
16896 error ("the combination of %qs and %qs is incompatible with %qs",
16897 "-mabi=o64", "-mabicalls", "-mlong64");
16901 if (mips_abi == ABI_64)
16902 error ("%qs is incompatible with %qs", "-mabi=64", "-mlong32");
16907 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
16908 target_flags |= MASK_LONG64;
16910 target_flags &= ~MASK_LONG64;
16913 if (!TARGET_OLDABI)
16914 flag_pcc_struct_return = 0;
16916 /* Decide which rtx_costs structure to use. */
16918 mips_cost = &mips_rtx_cost_optimize_size;
16920 mips_cost = &mips_rtx_cost_data[mips_tune];
16922 /* If the user hasn't specified a branch cost, use the processor's
16924 if (mips_branch_cost == 0)
16925 mips_branch_cost = mips_cost->branch_cost;
16927 /* If neither -mbranch-likely nor -mno-branch-likely was given
16928 on the command line, set MASK_BRANCHLIKELY based on the target
16929 architecture and tuning flags. Annulled delay slots are a
16930 size win, so we only consider the processor-specific tuning
16931 for !optimize_size. */
16932 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
16934 if (ISA_HAS_BRANCHLIKELY
16936 || (mips_tune_info->tune_flags & PTF_AVOID_BRANCHLIKELY) == 0))
16937 target_flags |= MASK_BRANCHLIKELY;
16939 target_flags &= ~MASK_BRANCHLIKELY;
16941 else if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
16942 warning (0, "the %qs architecture does not support branch-likely"
16943 " instructions", mips_arch_info->name);
16945 /* If the user hasn't specified -mimadd or -mno-imadd set
16946 MASK_IMADD based on the target architecture and tuning
16948 if ((target_flags_explicit & MASK_IMADD) == 0)
16950 if (ISA_HAS_MADD_MSUB &&
16951 (mips_tune_info->tune_flags & PTF_AVOID_IMADD) == 0)
16952 target_flags |= MASK_IMADD;
16954 target_flags &= ~MASK_IMADD;
16956 else if (TARGET_IMADD && !ISA_HAS_MADD_MSUB)
16957 warning (0, "the %qs architecture does not support madd or msub"
16958 " instructions", mips_arch_info->name);
16960 /* The effect of -mabicalls isn't defined for the EABI. */
16961 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
16963 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
16964 target_flags &= ~MASK_ABICALLS;
16967 /* PIC requires -mabicalls. */
16970 if (mips_abi == ABI_EABI)
16971 error ("cannot generate position-independent code for %qs",
16973 else if (!TARGET_ABICALLS)
16974 error ("position-independent code requires %qs", "-mabicalls");
16977 if (TARGET_ABICALLS_PIC2)
16978 /* We need to set flag_pic for executables as well as DSOs
16979 because we may reference symbols that are not defined in
16980 the final executable. (MIPS does not use things like
16981 copy relocs, for example.)
16983 There is a body of code that uses __PIC__ to distinguish
16984 between -mabicalls and -mno-abicalls code. The non-__PIC__
16985 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
16986 long as any indirect jumps use $25. */
16989 /* -mvr4130-align is a "speed over size" optimization: it usually produces
16990 faster code, but at the expense of more nops. Enable it at -O3 and
16992 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
16993 target_flags |= MASK_VR4130_ALIGN;
16995 /* Prefer a call to memcpy over inline code when optimizing for size,
16996 though see MOVE_RATIO in mips.h. */
16997 if (optimize_size && (target_flags_explicit & MASK_MEMCPY) == 0)
16998 target_flags |= MASK_MEMCPY;
17000 /* If we have a nonzero small-data limit, check that the -mgpopt
17001 setting is consistent with the other target flags. */
17002 if (mips_small_data_threshold > 0)
17006 if (!TARGET_EXPLICIT_RELOCS)
17007 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
17009 TARGET_LOCAL_SDATA = false;
17010 TARGET_EXTERN_SDATA = false;
17014 if (TARGET_VXWORKS_RTP)
17015 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
17017 if (TARGET_ABICALLS)
17018 warning (0, "cannot use small-data accesses for %qs",
17023 /* Pre-IEEE 754-2008 MIPS hardware has a quirky almost-IEEE format
17024 for all its floating point. */
17025 if (mips_nan != MIPS_IEEE_754_2008)
17027 REAL_MODE_FORMAT (SFmode) = &mips_single_format;
17028 REAL_MODE_FORMAT (DFmode) = &mips_double_format;
17029 REAL_MODE_FORMAT (TFmode) = &mips_quad_format;
17032 /* Make sure that the user didn't turn off paired single support when
17033 MIPS-3D support is requested. */
17035 && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
17036 && !TARGET_PAIRED_SINGLE_FLOAT)
17037 error ("%<-mips3d%> requires %<-mpaired-single%>");
17039 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
17041 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
17043 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
17044 and TARGET_HARD_FLOAT_ABI are both true. */
17045 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT_ABI))
17046 error ("%qs must be used with %qs",
17047 TARGET_MIPS3D ? "-mips3d" : "-mpaired-single",
17048 TARGET_HARD_FLOAT_ABI ? "-mfp64" : "-mhard-float");
17050 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
17052 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_HAS_PAIRED_SINGLE)
17053 warning (0, "the %qs architecture does not support paired-single"
17054 " instructions", mips_arch_info->name);
17056 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
17057 && !TARGET_CACHE_BUILTIN)
17059 error ("%qs requires a target that provides the %qs instruction",
17060 "-mr10k-cache-barrier", "cache");
17061 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE;
17064 /* If TARGET_DSPR2, enable MASK_DSP. */
17066 target_flags |= MASK_DSP;
17068 /* .eh_frame addresses should be the same width as a C pointer.
17069 Most MIPS ABIs support only one pointer size, so the assembler
17070 will usually know exactly how big an .eh_frame address is.
17072 Unfortunately, this is not true of the 64-bit EABI. The ABI was
17073 originally defined to use 64-bit pointers (i.e. it is LP64), and
17074 this is still the default mode. However, we also support an n32-like
17075 ILP32 mode, which is selected by -mlong32. The problem is that the
17076 assembler has traditionally not had an -mlong option, so it has
17077 traditionally not known whether we're using the ILP32 or LP64 form.
17079 As it happens, gas versions up to and including 2.19 use _32-bit_
17080 addresses for EABI64 .cfi_* directives. This is wrong for the
17081 default LP64 mode, so we can't use the directives by default.
17082 Moreover, since gas's current behavior is at odds with gcc's
17083 default behavior, it seems unwise to rely on future versions
17084 of gas behaving the same way. We therefore avoid using .cfi
17085 directives for -mlong32 as well. */
17086 if (mips_abi == ABI_EABI && TARGET_64BIT)
17087 flag_dwarf2_cfi_asm = 0;
17089 /* .cfi_* directives generate a read-only section, so fall back on
17090 manual .eh_frame creation if we need the section to be writable. */
17091 if (TARGET_WRITABLE_EH_FRAME)
17092 flag_dwarf2_cfi_asm = 0;
17094 mips_init_print_operand_punct ();
17096 /* Set up array to map GCC register number to debug register number.
17097 Ignore the special purpose register numbers. */
17099 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
17101 mips_dbx_regno[i] = IGNORED_DWARF_REGNUM;
17102 if (GP_REG_P (i) || FP_REG_P (i) || ALL_COP_REG_P (i))
17103 mips_dwarf_regno[i] = i;
17105 mips_dwarf_regno[i] = INVALID_REGNUM;
17108 start = GP_DBX_FIRST - GP_REG_FIRST;
17109 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
17110 mips_dbx_regno[i] = i + start;
17112 start = FP_DBX_FIRST - FP_REG_FIRST;
17113 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
17114 mips_dbx_regno[i] = i + start;
17116 /* Accumulator debug registers use big-endian ordering. */
17117 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
17118 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
17119 mips_dwarf_regno[HI_REGNUM] = MD_REG_FIRST + 0;
17120 mips_dwarf_regno[LO_REGNUM] = MD_REG_FIRST + 1;
17121 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
17123 mips_dwarf_regno[i + TARGET_LITTLE_ENDIAN] = i;
17124 mips_dwarf_regno[i + TARGET_BIG_ENDIAN] = i + 1;
17127 /* Set up mips_hard_regno_mode_ok. */
17128 for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
17129 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
17130 mips_hard_regno_mode_ok[mode][regno]
17131 = mips_hard_regno_mode_ok_p (regno, (enum machine_mode) mode);
17133 /* Function to allocate machine-dependent function status. */
17134 init_machine_status = &mips_init_machine_status;
17136 /* Default to working around R4000 errata only if the processor
17137 was selected explicitly. */
17138 if ((target_flags_explicit & MASK_FIX_R4000) == 0
17139 && strcmp (mips_arch_info->name, "r4000") == 0)
17140 target_flags |= MASK_FIX_R4000;
17142 /* Default to working around R4400 errata only if the processor
17143 was selected explicitly. */
17144 if ((target_flags_explicit & MASK_FIX_R4400) == 0
17145 && strcmp (mips_arch_info->name, "r4400") == 0)
17146 target_flags |= MASK_FIX_R4400;
17148 /* Default to working around R10000 errata only if the processor
17149 was selected explicitly. */
17150 if ((target_flags_explicit & MASK_FIX_R10000) == 0
17151 && strcmp (mips_arch_info->name, "r10000") == 0)
17152 target_flags |= MASK_FIX_R10000;
17154 /* Make sure that branch-likely instructions available when using
17155 -mfix-r10000. The instructions are not available if either:
17157 1. -mno-branch-likely was passed.
17158 2. The selected ISA does not support branch-likely and
17159 the command line does not include -mbranch-likely. */
17160 if (TARGET_FIX_R10000
17161 && ((target_flags_explicit & MASK_BRANCHLIKELY) == 0
17162 ? !ISA_HAS_BRANCHLIKELY
17163 : !TARGET_BRANCHLIKELY))
17164 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
17166 if (TARGET_SYNCI && !ISA_HAS_SYNCI)
17168 warning (0, "the %qs architecture does not support the synci "
17169 "instruction", mips_arch_info->name);
17170 target_flags &= ~MASK_SYNCI;
17173 /* Only optimize PIC indirect calls if they are actually required. */
17174 if (!TARGET_USE_GOT || !TARGET_EXPLICIT_RELOCS)
17175 target_flags &= ~MASK_RELAX_PIC_CALLS;
17177 /* Save base state of options. */
17178 mips_base_target_flags = target_flags;
17179 mips_base_schedule_insns = flag_schedule_insns;
17180 mips_base_reorder_blocks_and_partition = flag_reorder_blocks_and_partition;
17181 mips_base_move_loop_invariants = flag_move_loop_invariants;
17182 mips_base_align_loops = align_loops;
17183 mips_base_align_jumps = align_jumps;
17184 mips_base_align_functions = align_functions;
17186 /* Now select the ISA mode.
17188 Do all CPP-sensitive stuff in uncompressed mode; we'll switch modes
17189 later if required. */
17190 mips_set_compression_mode (0);
17192 /* We register a second machine specific reorg pass after delay slot
17193 filling. Registering the pass must be done at start up. It's
17194 convenient to do it here. */
17195 opt_pass *new_pass = make_pass_mips_machine_reorg2 (g);
17196 struct register_pass_info insert_pass_mips_machine_reorg2 =
17198 new_pass, /* pass */
17199 "dbr", /* reference_pass_name */
17200 1, /* ref_pass_instance_number */
17201 PASS_POS_INSERT_AFTER /* po_op */
17203 register_pass (&insert_pass_mips_machine_reorg2);
17205 if (TARGET_HARD_FLOAT_ABI && TARGET_MIPS5900)
17206 REAL_MODE_FORMAT (SFmode) = &spu_single_format;
17209 /* Swap the register information for registers I and I + 1, which
17210 currently have the wrong endianness. Note that the registers'
17211 fixedness and call-clobberedness might have been set on the
17215 mips_swap_registers (unsigned int i)
17220 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
17221 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
17223 SWAP_INT (fixed_regs[i], fixed_regs[i + 1]);
17224 SWAP_INT (call_used_regs[i], call_used_regs[i + 1]);
17225 SWAP_INT (call_really_used_regs[i], call_really_used_regs[i + 1]);
17226 SWAP_STRING (reg_names[i], reg_names[i + 1]);
17232 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
17235 mips_conditional_register_usage (void)
17240 /* These DSP control register fields are global. */
17241 global_regs[CCDSP_PO_REGNUM] = 1;
17242 global_regs[CCDSP_SC_REGNUM] = 1;
17245 AND_COMPL_HARD_REG_SET (accessible_reg_set,
17246 reg_class_contents[(int) DSP_ACC_REGS]);
17248 if (!TARGET_HARD_FLOAT)
17250 AND_COMPL_HARD_REG_SET (accessible_reg_set,
17251 reg_class_contents[(int) FP_REGS]);
17252 AND_COMPL_HARD_REG_SET (accessible_reg_set,
17253 reg_class_contents[(int) ST_REGS]);
17255 else if (!ISA_HAS_8CC)
17257 /* We only have a single condition-code register. We implement
17258 this by fixing all the condition-code registers and generating
17259 RTL that refers directly to ST_REG_FIRST. */
17260 AND_COMPL_HARD_REG_SET (accessible_reg_set,
17261 reg_class_contents[(int) ST_REGS]);
17262 SET_HARD_REG_BIT (accessible_reg_set, FPSW_REGNUM);
17263 fixed_regs[FPSW_REGNUM] = call_used_regs[FPSW_REGNUM] = 1;
17267 /* In MIPS16 mode, we prohibit the unused $s registers, since they
17268 are call-saved, and saving them via a MIPS16 register would
17269 probably waste more time than just reloading the value.
17271 We permit the $t temporary registers when optimizing for speed
17272 but not when optimizing for space because using them results in
17273 code that is larger (but faster) then not using them. We do
17274 allow $24 (t8) because it is used in CMP and CMPI instructions
17275 and $25 (t9) because it is used as the function call address in
17278 fixed_regs[18] = call_used_regs[18] = 1;
17279 fixed_regs[19] = call_used_regs[19] = 1;
17280 fixed_regs[20] = call_used_regs[20] = 1;
17281 fixed_regs[21] = call_used_regs[21] = 1;
17282 fixed_regs[22] = call_used_regs[22] = 1;
17283 fixed_regs[23] = call_used_regs[23] = 1;
17284 fixed_regs[26] = call_used_regs[26] = 1;
17285 fixed_regs[27] = call_used_regs[27] = 1;
17286 fixed_regs[30] = call_used_regs[30] = 1;
17289 fixed_regs[8] = call_used_regs[8] = 1;
17290 fixed_regs[9] = call_used_regs[9] = 1;
17291 fixed_regs[10] = call_used_regs[10] = 1;
17292 fixed_regs[11] = call_used_regs[11] = 1;
17293 fixed_regs[12] = call_used_regs[12] = 1;
17294 fixed_regs[13] = call_used_regs[13] = 1;
17295 fixed_regs[14] = call_used_regs[14] = 1;
17296 fixed_regs[15] = call_used_regs[15] = 1;
17299 /* Do not allow HI and LO to be treated as register operands.
17300 There are no MTHI or MTLO instructions (or any real need
17301 for them) and one-way registers cannot easily be reloaded. */
17302 AND_COMPL_HARD_REG_SET (operand_reg_set,
17303 reg_class_contents[(int) MD_REGS]);
17305 /* $f20-$f23 are call-clobbered for n64. */
17306 if (mips_abi == ABI_64)
17309 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
17310 call_really_used_regs[regno] = call_used_regs[regno] = 1;
17312 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
17314 if (mips_abi == ABI_N32)
17317 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
17318 call_really_used_regs[regno] = call_used_regs[regno] = 1;
17320 /* Make sure that double-register accumulator values are correctly
17321 ordered for the current endianness. */
17322 if (TARGET_LITTLE_ENDIAN)
17324 unsigned int regno;
17326 mips_swap_registers (MD_REG_FIRST);
17327 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno += 2)
17328 mips_swap_registers (regno);
17332 /* When generating MIPS16 code, we want to allocate $24 (T_REG) before
17333 other registers for instructions for which it is possible. This
17334 encourages the compiler to use CMP in cases where an XOR would
17335 require some register shuffling. */
17338 mips_order_regs_for_local_alloc (void)
17342 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
17343 reg_alloc_order[i] = i;
17347 /* It really doesn't matter where we put register 0, since it is
17348 a fixed register anyhow. */
17349 reg_alloc_order[0] = 24;
17350 reg_alloc_order[24] = 0;
17354 /* Implement EH_USES. */
17357 mips_eh_uses (unsigned int regno)
17359 if (reload_completed && !TARGET_ABSOLUTE_JUMPS)
17361 /* We need to force certain registers to be live in order to handle
17362 PIC long branches correctly. See mips_must_initialize_gp_p for
17364 if (mips_cfun_has_cprestore_slot_p ())
17366 if (regno == CPRESTORE_SLOT_REGNUM)
17371 if (cfun->machine->global_pointer == regno)
17379 /* Implement EPILOGUE_USES. */
17382 mips_epilogue_uses (unsigned int regno)
17384 /* Say that the epilogue uses the return address register. Note that
17385 in the case of sibcalls, the values "used by the epilogue" are
17386 considered live at the start of the called function. */
17387 if (regno == RETURN_ADDR_REGNUM)
17390 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
17391 See the comment above load_call<mode> for details. */
17392 if (TARGET_USE_GOT && (regno) == GOT_VERSION_REGNUM)
17395 /* An interrupt handler must preserve some registers that are
17396 ordinarily call-clobbered. */
17397 if (cfun->machine->interrupt_handler_p
17398 && mips_interrupt_extra_call_saved_reg_p (regno))
17404 /* A for_each_rtx callback. Stop the search if *X is an AT register. */
17407 mips_at_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
17409 return REG_P (*x) && REGNO (*x) == AT_REGNUM;
17412 /* Return true if INSN needs to be wrapped in ".set noat".
17413 INSN has NOPERANDS operands, stored in OPVEC. */
17416 mips_need_noat_wrapper_p (rtx insn, rtx *opvec, int noperands)
17420 if (recog_memoized (insn) >= 0)
17421 for (i = 0; i < noperands; i++)
17422 if (for_each_rtx (&opvec[i], mips_at_reg_p, NULL))
17427 /* Implement FINAL_PRESCAN_INSN. */
17430 mips_final_prescan_insn (rtx insn, rtx *opvec, int noperands)
17432 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
17433 mips_push_asm_switch (&mips_noat);
17436 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */
17439 mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED, rtx insn,
17440 rtx *opvec, int noperands)
17442 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
17443 mips_pop_asm_switch (&mips_noat);
17446 /* Return the function that is used to expand the <u>mulsidi3 pattern.
17447 EXT_CODE is the code of the extension used. Return NULL if widening
17448 multiplication shouldn't be used. */
17451 mips_mulsidi3_gen_fn (enum rtx_code ext_code)
17455 signed_p = ext_code == SIGN_EXTEND;
17458 /* Don't use widening multiplication with MULT when we have DMUL. Even
17459 with the extension of its input operands DMUL is faster. Note that
17460 the extension is not needed for signed multiplication. In order to
17461 ensure that we always remove the redundant sign-extension in this
17462 case we still expand mulsidi3 for DMUL. */
17464 return signed_p ? gen_mulsidi3_64bit_dmul : NULL;
17467 ? gen_mulsidi3_64bit_mips16
17468 : gen_umulsidi3_64bit_mips16);
17469 if (TARGET_FIX_R4000)
17471 return signed_p ? gen_mulsidi3_64bit : gen_umulsidi3_64bit;
17477 ? gen_mulsidi3_32bit_mips16
17478 : gen_umulsidi3_32bit_mips16);
17479 if (TARGET_FIX_R4000 && !ISA_HAS_DSP)
17480 return signed_p ? gen_mulsidi3_32bit_r4000 : gen_umulsidi3_32bit_r4000;
17481 return signed_p ? gen_mulsidi3_32bit : gen_umulsidi3_32bit;
17485 /* Return true if PATTERN matches the kind of instruction generated by
17486 umips_build_save_restore. SAVE_P is true for store. */
17489 umips_save_restore_pattern_p (bool save_p, rtx pattern)
17493 HOST_WIDE_INT first_offset = 0;
17494 rtx first_base = 0;
17495 unsigned int regmask = 0;
17497 for (n = 0; n < XVECLEN (pattern, 0); n++)
17499 rtx set, reg, mem, this_base;
17500 HOST_WIDE_INT this_offset;
17502 /* Check that we have a SET. */
17503 set = XVECEXP (pattern, 0, n);
17504 if (GET_CODE (set) != SET)
17507 /* Check that the SET is a load (if restoring) or a store
17509 mem = save_p ? SET_DEST (set) : SET_SRC (set);
17510 if (!MEM_P (mem) || MEM_VOLATILE_P (mem))
17513 /* Check that the address is the sum of base and a possibly-zero
17514 constant offset. Determine if the offset is in range. */
17515 mips_split_plus (XEXP (mem, 0), &this_base, &this_offset);
17516 if (!REG_P (this_base))
17521 if (!UMIPS_12BIT_OFFSET_P (this_offset))
17523 first_base = this_base;
17524 first_offset = this_offset;
17528 /* Check that the save slots are consecutive. */
17529 if (REGNO (this_base) != REGNO (first_base)
17530 || this_offset != first_offset + UNITS_PER_WORD * n)
17534 /* Check that SET's other operand is a register. */
17535 reg = save_p ? SET_SRC (set) : SET_DEST (set);
17539 regmask |= 1 << REGNO (reg);
17542 for (i = 0; i < ARRAY_SIZE (umips_swm_mask); i++)
17543 if (regmask == umips_swm_mask[i])
17549 /* Return the assembly instruction for microMIPS LWM or SWM.
17550 SAVE_P and PATTERN are as for umips_save_restore_pattern_p. */
17553 umips_output_save_restore (bool save_p, rtx pattern)
17555 static char buffer[300];
17558 HOST_WIDE_INT offset;
17559 rtx base, mem, set, last_set, last_reg;
17561 /* Parse the pattern. */
17562 gcc_assert (umips_save_restore_pattern_p (save_p, pattern));
17564 s = strcpy (buffer, save_p ? "swm\t" : "lwm\t");
17566 n = XVECLEN (pattern, 0);
17568 set = XVECEXP (pattern, 0, 0);
17569 mem = save_p ? SET_DEST (set) : SET_SRC (set);
17570 mips_split_plus (XEXP (mem, 0), &base, &offset);
17572 last_set = XVECEXP (pattern, 0, n - 1);
17573 last_reg = save_p ? SET_SRC (last_set) : SET_DEST (last_set);
17575 if (REGNO (last_reg) == 31)
17578 gcc_assert (n <= 9);
17582 s += sprintf (s, "%s,", reg_names[16]);
17584 s += sprintf (s, "%s-%s,", reg_names[16], reg_names[15 + n]);
17586 s += sprintf (s, "%s-%s,%s,", reg_names[16], reg_names[23],
17589 if (REGNO (last_reg) == 31)
17590 s += sprintf (s, "%s,", reg_names[31]);
17592 s += sprintf (s, "%d(%s)", (int)offset, reg_names[REGNO (base)]);
17596 /* Return true if MEM1 and MEM2 use the same base register, and the
17597 offset of MEM2 equals the offset of MEM1 plus 4. FIRST_REG is the
17598 register into (from) which the contents of MEM1 will be loaded
17599 (stored), depending on the value of LOAD_P.
17600 SWAP_P is true when the 1st and 2nd instructions are swapped. */
17603 umips_load_store_pair_p_1 (bool load_p, bool swap_p,
17604 rtx first_reg, rtx mem1, rtx mem2)
17607 HOST_WIDE_INT offset1, offset2;
17609 if (!MEM_P (mem1) || !MEM_P (mem2))
17612 mips_split_plus (XEXP (mem1, 0), &base1, &offset1);
17613 mips_split_plus (XEXP (mem2, 0), &base2, &offset2);
17615 if (!REG_P (base1) || !rtx_equal_p (base1, base2))
17618 /* Avoid invalid load pair instructions. */
17619 if (load_p && REGNO (first_reg) == REGNO (base1))
17622 /* We must avoid this case for anti-dependence.
17625 first_reg is $2, but the base is $3. */
17628 && REGNO (first_reg) + 1 == REGNO (base1))
17631 if (offset2 != offset1 + 4)
17634 if (!UMIPS_12BIT_OFFSET_P (offset1))
17640 /* OPERANDS describes the operands to a pair of SETs, in the order
17641 dest1, src1, dest2, src2. Return true if the operands can be used
17642 in an LWP or SWP instruction; LOAD_P says which. */
17645 umips_load_store_pair_p (bool load_p, rtx *operands)
17647 rtx reg1, reg2, mem1, mem2;
17651 reg1 = operands[0];
17652 reg2 = operands[2];
17653 mem1 = operands[1];
17654 mem2 = operands[3];
17658 reg1 = operands[1];
17659 reg2 = operands[3];
17660 mem1 = operands[0];
17661 mem2 = operands[2];
17664 if (REGNO (reg2) == REGNO (reg1) + 1)
17665 return umips_load_store_pair_p_1 (load_p, false, reg1, mem1, mem2);
17667 if (REGNO (reg1) == REGNO (reg2) + 1)
17668 return umips_load_store_pair_p_1 (load_p, true, reg2, mem2, mem1);
17673 /* Return the assembly instruction for a microMIPS LWP or SWP in which
17674 the first register is REG and the first memory slot is MEM.
17675 LOAD_P is true for LWP. */
17678 umips_output_load_store_pair_1 (bool load_p, rtx reg, rtx mem)
17680 rtx ops[] = {reg, mem};
17683 output_asm_insn ("lwp\t%0,%1", ops);
17685 output_asm_insn ("swp\t%0,%1", ops);
17688 /* Output the assembly instruction for a microMIPS LWP or SWP instruction.
17689 LOAD_P and OPERANDS are as for umips_load_store_pair_p. */
17692 umips_output_load_store_pair (bool load_p, rtx *operands)
17694 rtx reg1, reg2, mem1, mem2;
17697 reg1 = operands[0];
17698 reg2 = operands[2];
17699 mem1 = operands[1];
17700 mem2 = operands[3];
17704 reg1 = operands[1];
17705 reg2 = operands[3];
17706 mem1 = operands[0];
17707 mem2 = operands[2];
17710 if (REGNO (reg2) == REGNO (reg1) + 1)
17712 umips_output_load_store_pair_1 (load_p, reg1, mem1);
17716 gcc_assert (REGNO (reg1) == REGNO (reg2) + 1);
17717 umips_output_load_store_pair_1 (load_p, reg2, mem2);
17720 /* Return true if REG1 and REG2 match the criteria for a movep insn. */
17723 umips_movep_target_p (rtx reg1, rtx reg2)
17725 int regno1, regno2, pair;
17727 static const int match[8] = {
17728 0x00000060, /* 5, 6 */
17729 0x000000a0, /* 5, 7 */
17730 0x000000c0, /* 6, 7 */
17731 0x00200010, /* 4, 21 */
17732 0x00400010, /* 4, 22 */
17733 0x00000030, /* 4, 5 */
17734 0x00000050, /* 4, 6 */
17735 0x00000090 /* 4, 7 */
17738 if (!REG_P (reg1) || !REG_P (reg2))
17741 regno1 = REGNO (reg1);
17742 regno2 = REGNO (reg2);
17744 if (!GP_REG_P (regno1) || !GP_REG_P (regno2))
17747 pair = (1 << regno1) | (1 << regno2);
17749 for (i = 0; i < ARRAY_SIZE (match); i++)
17750 if (pair == match[i])
17756 /* Return the size in bytes of the trampoline code, padded to
17757 TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target
17758 function address immediately follow. */
17761 mips_trampoline_code_size (void)
17763 if (TARGET_USE_PIC_FN_ADDR_REG)
17765 else if (ptr_mode == DImode)
17767 else if (ISA_HAS_LOAD_DELAY)
17773 /* Implement TARGET_TRAMPOLINE_INIT. */
17776 mips_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
17778 rtx addr, end_addr, high, low, opcode, mem;
17781 HOST_WIDE_INT end_addr_offset, static_chain_offset, target_function_offset;
17783 /* Work out the offsets of the pointers from the start of the
17784 trampoline code. */
17785 end_addr_offset = mips_trampoline_code_size ();
17786 static_chain_offset = end_addr_offset;
17787 target_function_offset = static_chain_offset + GET_MODE_SIZE (ptr_mode);
17789 /* Get pointers to the beginning and end of the code block. */
17790 addr = force_reg (Pmode, XEXP (m_tramp, 0));
17791 end_addr = mips_force_binary (Pmode, PLUS, addr, GEN_INT (end_addr_offset));
17793 #define OP(X) gen_int_mode (X, SImode)
17795 /* Build up the code in TRAMPOLINE. */
17797 if (TARGET_USE_PIC_FN_ADDR_REG)
17799 /* $25 contains the address of the trampoline. Emit code of the form:
17801 l[wd] $1, target_function_offset($25)
17802 l[wd] $static_chain, static_chain_offset($25)
17805 trampoline[i++] = OP (MIPS_LOAD_PTR (AT_REGNUM,
17806 target_function_offset,
17807 PIC_FUNCTION_ADDR_REGNUM));
17808 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
17809 static_chain_offset,
17810 PIC_FUNCTION_ADDR_REGNUM));
17811 trampoline[i++] = OP (MIPS_JR (AT_REGNUM));
17812 trampoline[i++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM, AT_REGNUM));
17814 else if (ptr_mode == DImode)
17816 /* It's too cumbersome to create the full 64-bit address, so let's
17822 1: l[wd] $25, target_function_offset - 12($31)
17823 l[wd] $static_chain, static_chain_offset - 12($31)
17827 where 12 is the offset of "1:" from the start of the code block. */
17828 trampoline[i++] = OP (MIPS_MOVE (AT_REGNUM, RETURN_ADDR_REGNUM));
17829 trampoline[i++] = OP (MIPS_BAL (1));
17830 trampoline[i++] = OP (MIPS_NOP);
17831 trampoline[i++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
17832 target_function_offset - 12,
17833 RETURN_ADDR_REGNUM));
17834 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
17835 static_chain_offset - 12,
17836 RETURN_ADDR_REGNUM));
17837 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
17838 trampoline[i++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM, AT_REGNUM));
17842 /* If the target has load delays, emit:
17844 lui $1, %hi(end_addr)
17845 lw $25, %lo(end_addr + ...)($1)
17846 lw $static_chain, %lo(end_addr + ...)($1)
17852 lui $1, %hi(end_addr)
17853 lw $25, %lo(end_addr + ...)($1)
17855 lw $static_chain, %lo(end_addr + ...)($1). */
17857 /* Split END_ADDR into %hi and %lo values. Trampolines are aligned
17858 to 64 bits, so the %lo value will have the bottom 3 bits clear. */
17859 high = expand_simple_binop (SImode, PLUS, end_addr, GEN_INT (0x8000),
17860 NULL, false, OPTAB_WIDEN);
17861 high = expand_simple_binop (SImode, LSHIFTRT, high, GEN_INT (16),
17862 NULL, false, OPTAB_WIDEN);
17863 low = convert_to_mode (SImode, gen_lowpart (HImode, end_addr), true);
17865 /* Emit the LUI. */
17866 opcode = OP (MIPS_LUI (AT_REGNUM, 0));
17867 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, high,
17868 NULL, false, OPTAB_WIDEN);
17870 /* Emit the load of the target function. */
17871 opcode = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
17872 target_function_offset - end_addr_offset,
17874 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
17875 NULL, false, OPTAB_WIDEN);
17877 /* Emit the JR here, if we can. */
17878 if (!ISA_HAS_LOAD_DELAY)
17879 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
17881 /* Emit the load of the static chain register. */
17882 opcode = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
17883 static_chain_offset - end_addr_offset,
17885 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
17886 NULL, false, OPTAB_WIDEN);
17888 /* Emit the JR, if we couldn't above. */
17889 if (ISA_HAS_LOAD_DELAY)
17891 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
17892 trampoline[i++] = OP (MIPS_NOP);
17898 /* Copy the trampoline code. Leave any padding uninitialized. */
17899 for (j = 0; j < i; j++)
17901 mem = adjust_address (m_tramp, SImode, j * GET_MODE_SIZE (SImode));
17902 mips_emit_move (mem, trampoline[j]);
17905 /* Set up the static chain pointer field. */
17906 mem = adjust_address (m_tramp, ptr_mode, static_chain_offset);
17907 mips_emit_move (mem, chain_value);
17909 /* Set up the target function field. */
17910 mem = adjust_address (m_tramp, ptr_mode, target_function_offset);
17911 mips_emit_move (mem, XEXP (DECL_RTL (fndecl), 0));
17913 /* Flush the code part of the trampoline. */
17914 emit_insn (gen_add3_insn (end_addr, addr, GEN_INT (TRAMPOLINE_SIZE)));
17915 emit_insn (gen_clear_cache (addr, end_addr));
17918 /* Implement FUNCTION_PROFILER. */
17920 void mips_function_profiler (FILE *file)
17923 sorry ("mips16 function profiling");
17924 if (TARGET_LONG_CALLS)
17926 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */
17927 if (Pmode == DImode)
17928 fprintf (file, "\tdla\t%s,_mcount\n", reg_names[3]);
17930 fprintf (file, "\tla\t%s,_mcount\n", reg_names[3]);
17932 mips_push_asm_switch (&mips_noat);
17933 fprintf (file, "\tmove\t%s,%s\t\t# save current return address\n",
17934 reg_names[AT_REGNUM], reg_names[RETURN_ADDR_REGNUM]);
17935 /* _mcount treats $2 as the static chain register. */
17936 if (cfun->static_chain_decl != NULL)
17937 fprintf (file, "\tmove\t%s,%s\n", reg_names[2],
17938 reg_names[STATIC_CHAIN_REGNUM]);
17939 if (TARGET_MCOUNT_RA_ADDRESS)
17941 /* If TARGET_MCOUNT_RA_ADDRESS load $12 with the address of the
17942 ra save location. */
17943 if (cfun->machine->frame.ra_fp_offset == 0)
17944 /* ra not saved, pass zero. */
17945 fprintf (file, "\tmove\t%s,%s\n", reg_names[12], reg_names[0]);
17947 fprintf (file, "\t%s\t%s," HOST_WIDE_INT_PRINT_DEC "(%s)\n",
17948 Pmode == DImode ? "dla" : "la", reg_names[12],
17949 cfun->machine->frame.ra_fp_offset,
17950 reg_names[STACK_POINTER_REGNUM]);
17952 if (!TARGET_NEWABI)
17954 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n",
17955 TARGET_64BIT ? "dsubu" : "subu",
17956 reg_names[STACK_POINTER_REGNUM],
17957 reg_names[STACK_POINTER_REGNUM],
17958 Pmode == DImode ? 16 : 8);
17960 if (TARGET_LONG_CALLS)
17961 fprintf (file, "\tjalr\t%s\n", reg_names[3]);
17963 fprintf (file, "\tjal\t_mcount\n");
17964 mips_pop_asm_switch (&mips_noat);
17965 /* _mcount treats $2 as the static chain register. */
17966 if (cfun->static_chain_decl != NULL)
17967 fprintf (file, "\tmove\t%s,%s\n", reg_names[STATIC_CHAIN_REGNUM],
17971 /* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default
17972 behaviour of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even
17973 when TARGET_LOONGSON_VECTORS is true. */
17975 static unsigned HOST_WIDE_INT
17976 mips_shift_truncation_mask (enum machine_mode mode)
17978 if (TARGET_LOONGSON_VECTORS && VECTOR_MODE_P (mode))
17981 return GET_MODE_BITSIZE (mode) - 1;
17984 /* Implement TARGET_PREPARE_PCH_SAVE. */
17987 mips_prepare_pch_save (void)
17989 /* We are called in a context where the current MIPS16 vs. non-MIPS16
17990 setting should be irrelevant. The question then is: which setting
17991 makes most sense at load time?
17993 The PCH is loaded before the first token is read. We should never
17994 have switched into MIPS16 mode by that point, and thus should not
17995 have populated mips16_globals. Nor can we load the entire contents
17996 of mips16_globals from the PCH file, because mips16_globals contains
17997 a combination of GGC and non-GGC data.
17999 There is therefore no point in trying save the GGC part of
18000 mips16_globals to the PCH file, or to preserve MIPS16ness across
18001 the PCH save and load. The loading compiler would not have access
18002 to the non-GGC parts of mips16_globals (either from the PCH file,
18003 or from a copy that the loading compiler generated itself) and would
18004 have to call target_reinit anyway.
18006 It therefore seems best to switch back to non-MIPS16 mode at
18007 save time, and to ensure that mips16_globals remains null after
18009 mips_set_compression_mode (0);
18010 mips16_globals = 0;
18013 /* Generate or test for an insn that supports a constant permutation. */
18015 #define MAX_VECT_LEN 8
18017 struct expand_vec_perm_d
18019 rtx target, op0, op1;
18020 unsigned char perm[MAX_VECT_LEN];
18021 enum machine_mode vmode;
18022 unsigned char nelt;
18027 /* Construct (set target (vec_select op0 (parallel perm))) and
18028 return true if that's a valid instruction in the active ISA. */
18031 mips_expand_vselect (rtx target, rtx op0,
18032 const unsigned char *perm, unsigned nelt)
18034 rtx rperm[MAX_VECT_LEN], x;
18037 for (i = 0; i < nelt; ++i)
18038 rperm[i] = GEN_INT (perm[i]);
18040 x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (nelt, rperm));
18041 x = gen_rtx_VEC_SELECT (GET_MODE (target), op0, x);
18042 x = gen_rtx_SET (VOIDmode, target, x);
18045 if (recog_memoized (x) < 0)
18053 /* Similar, but generate a vec_concat from op0 and op1 as well. */
18056 mips_expand_vselect_vconcat (rtx target, rtx op0, rtx op1,
18057 const unsigned char *perm, unsigned nelt)
18059 enum machine_mode v2mode;
18062 v2mode = GET_MODE_2XWIDER_MODE (GET_MODE (op0));
18063 x = gen_rtx_VEC_CONCAT (v2mode, op0, op1);
18064 return mips_expand_vselect (target, x, perm, nelt);
18067 /* Recognize patterns for even-odd extraction. */
18070 mips_expand_vpc_loongson_even_odd (struct expand_vec_perm_d *d)
18072 unsigned i, odd, nelt = d->nelt;
18073 rtx t0, t1, t2, t3;
18075 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
18077 /* Even-odd for V2SI/V2SFmode is matched by interleave directly. */
18084 for (i = 1; i < nelt; ++i)
18085 if (d->perm[i] != i * 2 + odd)
18091 /* We need 2*log2(N)-1 operations to achieve odd/even with interleave. */
18092 t0 = gen_reg_rtx (d->vmode);
18093 t1 = gen_reg_rtx (d->vmode);
18097 emit_insn (gen_loongson_punpckhhw (t0, d->op0, d->op1));
18098 emit_insn (gen_loongson_punpcklhw (t1, d->op0, d->op1));
18100 emit_insn (gen_loongson_punpckhhw (d->target, t1, t0));
18102 emit_insn (gen_loongson_punpcklhw (d->target, t1, t0));
18106 t2 = gen_reg_rtx (d->vmode);
18107 t3 = gen_reg_rtx (d->vmode);
18108 emit_insn (gen_loongson_punpckhbh (t0, d->op0, d->op1));
18109 emit_insn (gen_loongson_punpcklbh (t1, d->op0, d->op1));
18110 emit_insn (gen_loongson_punpckhbh (t2, t1, t0));
18111 emit_insn (gen_loongson_punpcklbh (t3, t1, t0));
18113 emit_insn (gen_loongson_punpckhbh (d->target, t3, t2));
18115 emit_insn (gen_loongson_punpcklbh (d->target, t3, t2));
18119 gcc_unreachable ();
18124 /* Recognize patterns for the Loongson PSHUFH instruction. */
18127 mips_expand_vpc_loongson_pshufh (struct expand_vec_perm_d *d)
18132 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
18134 if (d->vmode != V4HImode)
18139 /* Convert the selector into the packed 8-bit form for pshufh. */
18140 /* Recall that loongson is little-endian only. No big-endian
18141 adjustment required. */
18142 for (i = mask = 0; i < 4; i++)
18143 mask |= (d->perm[i] & 3) << (i * 2);
18144 rmask = force_reg (SImode, GEN_INT (mask));
18146 if (d->one_vector_p)
18147 emit_insn (gen_loongson_pshufh (d->target, d->op0, rmask));
18150 rtx t0, t1, x, merge, rmerge[4];
18152 t0 = gen_reg_rtx (V4HImode);
18153 t1 = gen_reg_rtx (V4HImode);
18154 emit_insn (gen_loongson_pshufh (t1, d->op1, rmask));
18155 emit_insn (gen_loongson_pshufh (t0, d->op0, rmask));
18157 for (i = 0; i < 4; ++i)
18158 rmerge[i] = (d->perm[i] & 4 ? constm1_rtx : const0_rtx);
18159 merge = gen_rtx_CONST_VECTOR (V4HImode, gen_rtvec_v (4, rmerge));
18160 merge = force_reg (V4HImode, merge);
18162 x = gen_rtx_AND (V4HImode, merge, t1);
18163 emit_insn (gen_rtx_SET (VOIDmode, t1, x));
18165 x = gen_rtx_NOT (V4HImode, merge);
18166 x = gen_rtx_AND (V4HImode, x, t0);
18167 emit_insn (gen_rtx_SET (VOIDmode, t0, x));
18169 x = gen_rtx_IOR (V4HImode, t0, t1);
18170 emit_insn (gen_rtx_SET (VOIDmode, d->target, x));
18176 /* Recognize broadcast patterns for the Loongson. */
18179 mips_expand_vpc_loongson_bcast (struct expand_vec_perm_d *d)
18184 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
18186 /* Note that we've already matched V2SI via punpck and V4HI via pshufh. */
18187 if (d->vmode != V8QImode)
18189 if (!d->one_vector_p)
18193 for (i = 1; i < 8; ++i)
18194 if (d->perm[i] != elt)
18200 /* With one interleave we put two of the desired element adjacent. */
18201 t0 = gen_reg_rtx (V8QImode);
18203 emit_insn (gen_loongson_punpcklbh (t0, d->op0, d->op0));
18205 emit_insn (gen_loongson_punpckhbh (t0, d->op0, d->op0));
18207 /* Shuffle that one HImode element into all locations. */
18210 t1 = gen_reg_rtx (V4HImode);
18211 emit_insn (gen_loongson_pshufh (t1, gen_lowpart (V4HImode, t0),
18212 force_reg (SImode, GEN_INT (elt))));
18214 emit_move_insn (d->target, gen_lowpart (V8QImode, t1));
18219 mips_expand_vec_perm_const_1 (struct expand_vec_perm_d *d)
18221 unsigned int i, nelt = d->nelt;
18222 unsigned char perm2[MAX_VECT_LEN];
18224 if (d->one_vector_p)
18226 /* Try interleave with alternating operands. */
18227 memcpy (perm2, d->perm, sizeof(perm2));
18228 for (i = 1; i < nelt; i += 2)
18230 if (mips_expand_vselect_vconcat (d->target, d->op0, d->op1, perm2, nelt))
18235 if (mips_expand_vselect_vconcat (d->target, d->op0, d->op1,
18239 /* Try again with swapped operands. */
18240 for (i = 0; i < nelt; ++i)
18241 perm2[i] = (d->perm[i] + nelt) & (2 * nelt - 1);
18242 if (mips_expand_vselect_vconcat (d->target, d->op1, d->op0, perm2, nelt))
18246 if (mips_expand_vpc_loongson_even_odd (d))
18248 if (mips_expand_vpc_loongson_pshufh (d))
18250 if (mips_expand_vpc_loongson_bcast (d))
18255 /* Expand a vec_perm_const pattern. */
18258 mips_expand_vec_perm_const (rtx operands[4])
18260 struct expand_vec_perm_d d;
18261 int i, nelt, which;
18262 unsigned char orig_perm[MAX_VECT_LEN];
18266 d.target = operands[0];
18267 d.op0 = operands[1];
18268 d.op1 = operands[2];
18271 d.vmode = GET_MODE (d.target);
18272 gcc_assert (VECTOR_MODE_P (d.vmode));
18273 d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
18274 d.testing_p = false;
18276 for (i = which = 0; i < nelt; ++i)
18278 rtx e = XVECEXP (sel, 0, i);
18279 int ei = INTVAL (e) & (2 * nelt - 1);
18280 which |= (ei < nelt ? 1 : 2);
18283 memcpy (d.perm, orig_perm, MAX_VECT_LEN);
18291 d.one_vector_p = false;
18292 if (!rtx_equal_p (d.op0, d.op1))
18297 for (i = 0; i < nelt; ++i)
18298 d.perm[i] &= nelt - 1;
18300 d.one_vector_p = true;
18305 d.one_vector_p = true;
18309 ok = mips_expand_vec_perm_const_1 (&d);
18311 /* If we were given a two-vector permutation which just happened to
18312 have both input vectors equal, we folded this into a one-vector
18313 permutation. There are several loongson patterns that are matched
18314 via direct vec_select+vec_concat expansion, but we do not have
18315 support in mips_expand_vec_perm_const_1 to guess the adjustment
18316 that should be made for a single operand. Just try again with
18317 the original permutation. */
18318 if (!ok && which == 3)
18320 d.op0 = operands[1];
18321 d.op1 = operands[2];
18322 d.one_vector_p = false;
18323 memcpy (d.perm, orig_perm, MAX_VECT_LEN);
18324 ok = mips_expand_vec_perm_const_1 (&d);
18330 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST_OK. */
18333 mips_vectorize_vec_perm_const_ok (enum machine_mode vmode,
18334 const unsigned char *sel)
18336 struct expand_vec_perm_d d;
18337 unsigned int i, nelt, which;
18341 d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
18342 d.testing_p = true;
18343 memcpy (d.perm, sel, nelt);
18345 /* Categorize the set of elements in the selector. */
18346 for (i = which = 0; i < nelt; ++i)
18348 unsigned char e = d.perm[i];
18349 gcc_assert (e < 2 * nelt);
18350 which |= (e < nelt ? 1 : 2);
18353 /* For all elements from second vector, fold the elements to first. */
18355 for (i = 0; i < nelt; ++i)
18358 /* Check whether the mask can be applied to the vector type. */
18359 d.one_vector_p = (which != 3);
18361 d.target = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 1);
18362 d.op1 = d.op0 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 2);
18363 if (!d.one_vector_p)
18364 d.op1 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 3);
18367 ret = mips_expand_vec_perm_const_1 (&d);
18373 /* Expand an integral vector unpack operation. */
18376 mips_expand_vec_unpack (rtx operands[2], bool unsigned_p, bool high_p)
18378 enum machine_mode imode = GET_MODE (operands[1]);
18379 rtx (*unpack) (rtx, rtx, rtx);
18380 rtx (*cmpgt) (rtx, rtx, rtx);
18381 rtx tmp, dest, zero;
18387 unpack = gen_loongson_punpckhbh;
18389 unpack = gen_loongson_punpcklbh;
18390 cmpgt = gen_loongson_pcmpgtb;
18394 unpack = gen_loongson_punpckhhw;
18396 unpack = gen_loongson_punpcklhw;
18397 cmpgt = gen_loongson_pcmpgth;
18400 gcc_unreachable ();
18403 zero = force_reg (imode, CONST0_RTX (imode));
18408 tmp = gen_reg_rtx (imode);
18409 emit_insn (cmpgt (tmp, zero, operands[1]));
18412 dest = gen_reg_rtx (imode);
18413 emit_insn (unpack (dest, operands[1], tmp));
18415 emit_move_insn (operands[0], gen_lowpart (GET_MODE (operands[0]), dest));
18418 /* A subroutine of mips_expand_vec_init, match constant vector elements. */
18421 mips_constant_elt_p (rtx x)
18423 return CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE;
18426 /* A subroutine of mips_expand_vec_init, expand via broadcast. */
18429 mips_expand_vi_broadcast (enum machine_mode vmode, rtx target, rtx elt)
18431 struct expand_vec_perm_d d;
18435 if (elt != const0_rtx)
18436 elt = force_reg (GET_MODE_INNER (vmode), elt);
18438 elt = gen_lowpart (DImode, elt);
18440 t1 = gen_reg_rtx (vmode);
18444 emit_insn (gen_loongson_vec_init1_v8qi (t1, elt));
18447 emit_insn (gen_loongson_vec_init1_v4hi (t1, elt));
18450 gcc_unreachable ();
18453 memset (&d, 0, sizeof (d));
18458 d.nelt = GET_MODE_NUNITS (vmode);
18459 d.one_vector_p = true;
18461 ok = mips_expand_vec_perm_const_1 (&d);
18465 /* A subroutine of mips_expand_vec_init, replacing all of the non-constant
18466 elements of VALS with zeros, copy the constant vector to TARGET. */
18469 mips_expand_vi_constant (enum machine_mode vmode, unsigned nelt,
18470 rtx target, rtx vals)
18472 rtvec vec = shallow_copy_rtvec (XVEC (vals, 0));
18475 for (i = 0; i < nelt; ++i)
18477 if (!mips_constant_elt_p (RTVEC_ELT (vec, i)))
18478 RTVEC_ELT (vec, i) = const0_rtx;
18481 emit_move_insn (target, gen_rtx_CONST_VECTOR (vmode, vec));
18485 /* A subroutine of mips_expand_vec_init, expand via pinsrh. */
18488 mips_expand_vi_loongson_one_pinsrh (rtx target, rtx vals, unsigned one_var)
18490 mips_expand_vi_constant (V4HImode, 4, target, vals);
18492 emit_insn (gen_vec_setv4hi (target, target, XVECEXP (vals, 0, one_var),
18493 GEN_INT (one_var)));
18496 /* A subroutine of mips_expand_vec_init, expand anything via memory. */
18499 mips_expand_vi_general (enum machine_mode vmode, enum machine_mode imode,
18500 unsigned nelt, unsigned nvar, rtx target, rtx vals)
18502 rtx mem = assign_stack_temp (vmode, GET_MODE_SIZE (vmode));
18503 unsigned int i, isize = GET_MODE_SIZE (imode);
18506 mips_expand_vi_constant (vmode, nelt, mem, vals);
18508 for (i = 0; i < nelt; ++i)
18510 rtx x = XVECEXP (vals, 0, i);
18511 if (!mips_constant_elt_p (x))
18512 emit_move_insn (adjust_address (mem, imode, i * isize), x);
18515 emit_move_insn (target, mem);
18518 /* Expand a vector initialization. */
18521 mips_expand_vector_init (rtx target, rtx vals)
18523 enum machine_mode vmode = GET_MODE (target);
18524 enum machine_mode imode = GET_MODE_INNER (vmode);
18525 unsigned i, nelt = GET_MODE_NUNITS (vmode);
18526 unsigned nvar = 0, one_var = -1u;
18527 bool all_same = true;
18530 for (i = 0; i < nelt; ++i)
18532 x = XVECEXP (vals, 0, i);
18533 if (!mips_constant_elt_p (x))
18534 nvar++, one_var = i;
18535 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
18539 /* Load constants from the pool, or whatever's handy. */
18542 emit_move_insn (target, gen_rtx_CONST_VECTOR (vmode, XVEC (vals, 0)));
18546 /* For two-part initialization, always use CONCAT. */
18549 rtx op0 = force_reg (imode, XVECEXP (vals, 0, 0));
18550 rtx op1 = force_reg (imode, XVECEXP (vals, 0, 1));
18551 x = gen_rtx_VEC_CONCAT (vmode, op0, op1);
18552 emit_insn (gen_rtx_SET (VOIDmode, target, x));
18556 /* Loongson is the only cpu with vectors with more elements. */
18557 gcc_assert (TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS);
18559 /* If all values are identical, broadcast the value. */
18562 mips_expand_vi_broadcast (vmode, target, XVECEXP (vals, 0, 0));
18566 /* If we've only got one non-variable V4HImode, use PINSRH. */
18567 if (nvar == 1 && vmode == V4HImode)
18569 mips_expand_vi_loongson_one_pinsrh (target, vals, one_var);
18573 mips_expand_vi_general (vmode, imode, nelt, nvar, target, vals);
18576 /* Expand a vector reduction. */
18579 mips_expand_vec_reduc (rtx target, rtx in, rtx (*gen)(rtx, rtx, rtx))
18581 enum machine_mode vmode = GET_MODE (in);
18582 unsigned char perm2[2];
18583 rtx last, next, fold, x;
18587 fold = gen_reg_rtx (vmode);
18591 /* Use PUL/PLU to produce { L, H } op { H, L }.
18592 By reversing the pair order, rather than a pure interleave high,
18593 we avoid erroneous exceptional conditions that we might otherwise
18594 produce from the computation of H op H. */
18597 ok = mips_expand_vselect_vconcat (fold, last, last, perm2, 2);
18602 /* Use interleave to produce { H, L } op { H, H }. */
18603 emit_insn (gen_loongson_punpckhwd (fold, last, last));
18607 /* Perform the first reduction with interleave,
18608 and subsequent reductions with shifts. */
18609 emit_insn (gen_loongson_punpckhwd_hi (fold, last, last));
18611 next = gen_reg_rtx (vmode);
18612 emit_insn (gen (next, last, fold));
18615 fold = gen_reg_rtx (vmode);
18616 x = force_reg (SImode, GEN_INT (16));
18617 emit_insn (gen_vec_shr_v4hi (fold, last, x));
18621 emit_insn (gen_loongson_punpckhwd_qi (fold, last, last));
18623 next = gen_reg_rtx (vmode);
18624 emit_insn (gen (next, last, fold));
18627 fold = gen_reg_rtx (vmode);
18628 x = force_reg (SImode, GEN_INT (16));
18629 emit_insn (gen_vec_shr_v8qi (fold, last, x));
18631 next = gen_reg_rtx (vmode);
18632 emit_insn (gen (next, last, fold));
18635 fold = gen_reg_rtx (vmode);
18636 x = force_reg (SImode, GEN_INT (8));
18637 emit_insn (gen_vec_shr_v8qi (fold, last, x));
18641 gcc_unreachable ();
18644 emit_insn (gen (target, last, fold));
18647 /* Expand a vector minimum/maximum. */
18650 mips_expand_vec_minmax (rtx target, rtx op0, rtx op1,
18651 rtx (*cmp) (rtx, rtx, rtx), bool min_p)
18653 enum machine_mode vmode = GET_MODE (target);
18656 tc = gen_reg_rtx (vmode);
18657 t0 = gen_reg_rtx (vmode);
18658 t1 = gen_reg_rtx (vmode);
18661 emit_insn (cmp (tc, op0, op1));
18663 x = gen_rtx_AND (vmode, tc, (min_p ? op1 : op0));
18664 emit_insn (gen_rtx_SET (VOIDmode, t0, x));
18666 x = gen_rtx_NOT (vmode, tc);
18667 x = gen_rtx_AND (vmode, x, (min_p ? op0 : op1));
18668 emit_insn (gen_rtx_SET (VOIDmode, t1, x));
18670 x = gen_rtx_IOR (vmode, t0, t1);
18671 emit_insn (gen_rtx_SET (VOIDmode, target, x));
18674 /* Implement TARGET_CASE_VALUES_THRESHOLD. */
18677 mips_case_values_threshold (void)
18679 /* In MIPS16 mode using a larger case threshold generates smaller code. */
18680 if (TARGET_MIPS16 && optimize_size)
18683 return default_case_values_threshold ();
18686 /* Initialize the GCC target structure. */
18687 #undef TARGET_ASM_ALIGNED_HI_OP
18688 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
18689 #undef TARGET_ASM_ALIGNED_SI_OP
18690 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
18691 #undef TARGET_ASM_ALIGNED_DI_OP
18692 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
18694 #undef TARGET_OPTION_OVERRIDE
18695 #define TARGET_OPTION_OVERRIDE mips_option_override
18697 #undef TARGET_LEGITIMIZE_ADDRESS
18698 #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
18700 #undef TARGET_ASM_FUNCTION_PROLOGUE
18701 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
18702 #undef TARGET_ASM_FUNCTION_EPILOGUE
18703 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
18704 #undef TARGET_ASM_SELECT_RTX_SECTION
18705 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
18706 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
18707 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
18709 #undef TARGET_SCHED_INIT
18710 #define TARGET_SCHED_INIT mips_sched_init
18711 #undef TARGET_SCHED_REORDER
18712 #define TARGET_SCHED_REORDER mips_sched_reorder
18713 #undef TARGET_SCHED_REORDER2
18714 #define TARGET_SCHED_REORDER2 mips_sched_reorder2
18715 #undef TARGET_SCHED_VARIABLE_ISSUE
18716 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
18717 #undef TARGET_SCHED_ADJUST_COST
18718 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
18719 #undef TARGET_SCHED_ISSUE_RATE
18720 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
18721 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
18722 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
18723 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
18724 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
18725 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
18726 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
18727 mips_multipass_dfa_lookahead
18728 #undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
18729 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
18730 mips_small_register_classes_for_mode_p
18732 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
18733 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
18735 #undef TARGET_INSERT_ATTRIBUTES
18736 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
18737 #undef TARGET_MERGE_DECL_ATTRIBUTES
18738 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
18739 #undef TARGET_CAN_INLINE_P
18740 #define TARGET_CAN_INLINE_P mips_can_inline_p
18741 #undef TARGET_SET_CURRENT_FUNCTION
18742 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
18744 #undef TARGET_VALID_POINTER_MODE
18745 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
18746 #undef TARGET_REGISTER_MOVE_COST
18747 #define TARGET_REGISTER_MOVE_COST mips_register_move_cost
18748 #undef TARGET_MEMORY_MOVE_COST
18749 #define TARGET_MEMORY_MOVE_COST mips_memory_move_cost
18750 #undef TARGET_RTX_COSTS
18751 #define TARGET_RTX_COSTS mips_rtx_costs
18752 #undef TARGET_ADDRESS_COST
18753 #define TARGET_ADDRESS_COST mips_address_cost
18755 #undef TARGET_IN_SMALL_DATA_P
18756 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
18758 #undef TARGET_MACHINE_DEPENDENT_REORG
18759 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
18761 #undef TARGET_PREFERRED_RELOAD_CLASS
18762 #define TARGET_PREFERRED_RELOAD_CLASS mips_preferred_reload_class
18764 #undef TARGET_EXPAND_TO_RTL_HOOK
18765 #define TARGET_EXPAND_TO_RTL_HOOK mips_expand_to_rtl_hook
18766 #undef TARGET_ASM_FILE_START
18767 #define TARGET_ASM_FILE_START mips_file_start
18768 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
18769 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
18770 #undef TARGET_ASM_CODE_END
18771 #define TARGET_ASM_CODE_END mips_code_end
18773 #undef TARGET_INIT_LIBFUNCS
18774 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
18776 #undef TARGET_BUILD_BUILTIN_VA_LIST
18777 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
18778 #undef TARGET_EXPAND_BUILTIN_VA_START
18779 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
18780 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
18781 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
18783 #undef TARGET_PROMOTE_FUNCTION_MODE
18784 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
18785 #undef TARGET_PROMOTE_PROTOTYPES
18786 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
18788 #undef TARGET_FUNCTION_VALUE
18789 #define TARGET_FUNCTION_VALUE mips_function_value
18790 #undef TARGET_LIBCALL_VALUE
18791 #define TARGET_LIBCALL_VALUE mips_libcall_value
18792 #undef TARGET_FUNCTION_VALUE_REGNO_P
18793 #define TARGET_FUNCTION_VALUE_REGNO_P mips_function_value_regno_p
18794 #undef TARGET_RETURN_IN_MEMORY
18795 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
18796 #undef TARGET_RETURN_IN_MSB
18797 #define TARGET_RETURN_IN_MSB mips_return_in_msb
18799 #undef TARGET_ASM_OUTPUT_MI_THUNK
18800 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
18801 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
18802 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
18804 #undef TARGET_PRINT_OPERAND
18805 #define TARGET_PRINT_OPERAND mips_print_operand
18806 #undef TARGET_PRINT_OPERAND_ADDRESS
18807 #define TARGET_PRINT_OPERAND_ADDRESS mips_print_operand_address
18808 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
18809 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mips_print_operand_punct_valid_p
18811 #undef TARGET_SETUP_INCOMING_VARARGS
18812 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
18813 #undef TARGET_STRICT_ARGUMENT_NAMING
18814 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
18815 #undef TARGET_MUST_PASS_IN_STACK
18816 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
18817 #undef TARGET_PASS_BY_REFERENCE
18818 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
18819 #undef TARGET_CALLEE_COPIES
18820 #define TARGET_CALLEE_COPIES mips_callee_copies
18821 #undef TARGET_ARG_PARTIAL_BYTES
18822 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
18823 #undef TARGET_FUNCTION_ARG
18824 #define TARGET_FUNCTION_ARG mips_function_arg
18825 #undef TARGET_FUNCTION_ARG_ADVANCE
18826 #define TARGET_FUNCTION_ARG_ADVANCE mips_function_arg_advance
18827 #undef TARGET_FUNCTION_ARG_BOUNDARY
18828 #define TARGET_FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
18830 #undef TARGET_MODE_REP_EXTENDED
18831 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
18833 #undef TARGET_VECTOR_MODE_SUPPORTED_P
18834 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
18836 #undef TARGET_SCALAR_MODE_SUPPORTED_P
18837 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
18839 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
18840 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE mips_preferred_simd_mode
18842 #undef TARGET_INIT_BUILTINS
18843 #define TARGET_INIT_BUILTINS mips_init_builtins
18844 #undef TARGET_BUILTIN_DECL
18845 #define TARGET_BUILTIN_DECL mips_builtin_decl
18846 #undef TARGET_EXPAND_BUILTIN
18847 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
18849 #undef TARGET_HAVE_TLS
18850 #define TARGET_HAVE_TLS HAVE_AS_TLS
18852 #undef TARGET_CANNOT_FORCE_CONST_MEM
18853 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
18855 #undef TARGET_LEGITIMATE_CONSTANT_P
18856 #define TARGET_LEGITIMATE_CONSTANT_P mips_legitimate_constant_p
18858 #undef TARGET_ENCODE_SECTION_INFO
18859 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
18861 #undef TARGET_ATTRIBUTE_TABLE
18862 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
18863 /* All our function attributes are related to how out-of-line copies should
18864 be compiled or called. They don't in themselves prevent inlining. */
18865 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
18866 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
18868 #undef TARGET_EXTRA_LIVE_ON_ENTRY
18869 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
18871 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
18872 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
18873 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
18874 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
18876 #undef TARGET_COMP_TYPE_ATTRIBUTES
18877 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
18879 #ifdef HAVE_AS_DTPRELWORD
18880 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
18881 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
18883 #undef TARGET_DWARF_REGISTER_SPAN
18884 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
18886 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
18887 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
18889 #undef TARGET_LEGITIMATE_ADDRESS_P
18890 #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p
18892 #undef TARGET_FRAME_POINTER_REQUIRED
18893 #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required
18895 #undef TARGET_CAN_ELIMINATE
18896 #define TARGET_CAN_ELIMINATE mips_can_eliminate
18898 #undef TARGET_CONDITIONAL_REGISTER_USAGE
18899 #define TARGET_CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage
18901 #undef TARGET_TRAMPOLINE_INIT
18902 #define TARGET_TRAMPOLINE_INIT mips_trampoline_init
18904 #undef TARGET_ASM_OUTPUT_SOURCE_FILENAME
18905 #define TARGET_ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
18907 #undef TARGET_SHIFT_TRUNCATION_MASK
18908 #define TARGET_SHIFT_TRUNCATION_MASK mips_shift_truncation_mask
18910 #undef TARGET_PREPARE_PCH_SAVE
18911 #define TARGET_PREPARE_PCH_SAVE mips_prepare_pch_save
18913 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
18914 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK mips_vectorize_vec_perm_const_ok
18916 #undef TARGET_CASE_VALUES_THRESHOLD
18917 #define TARGET_CASE_VALUES_THRESHOLD mips_case_values_threshold
18919 struct gcc_target targetm = TARGET_INITIALIZER;
18921 #include "gt-mips.h"