1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989-2014 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky, lich@inria.inria.fr.
4 Changes by Michael Meissner, meissner@osf.org.
5 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 Brendan Eich, brendan@microunity.com.
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
30 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
38 #include "stringpool.h"
39 #include "stor-layout.h"
50 #include "hash-table.h"
53 #include "target-def.h"
54 #include "common/common-target.h"
55 #include "langhooks.h"
56 #include "sched-int.h"
58 #include "basic-block.h"
59 #include "tree-ssa-alias.h"
60 #include "internal-fn.h"
61 #include "gimple-fold.h"
63 #include "gimple-expr.h"
68 #include "diagnostic.h"
69 #include "target-globals.h"
71 #include "tree-pass.h"
76 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
77 #define UNSPEC_ADDRESS_P(X) \
78 (GET_CODE (X) == UNSPEC \
79 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
80 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
82 /* Extract the symbol or label from UNSPEC wrapper X. */
83 #define UNSPEC_ADDRESS(X) \
86 /* Extract the symbol type from UNSPEC wrapper X. */
87 #define UNSPEC_ADDRESS_TYPE(X) \
88 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
90 /* The maximum distance between the top of the stack frame and the
91 value $sp has when we save and restore registers.
93 The value for normal-mode code must be a SMALL_OPERAND and must
94 preserve the maximum stack alignment. We therefore use a value
95 of 0x7ff0 in this case.
97 microMIPS LWM and SWM support 12-bit offsets (from -0x800 to 0x7ff),
98 so we use a maximum of 0x7f0 for TARGET_MICROMIPS.
100 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
101 up to 0x7f8 bytes and can usually save or restore all the registers
102 that we need to save or restore. (Note that we can only use these
103 instructions for o32, for which the stack alignment is 8 bytes.)
105 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
106 RESTORE are not available. We can then use unextended instructions
107 to save and restore registers, and to allocate and deallocate the top
108 part of the frame. */
109 #define MIPS_MAX_FIRST_STACK_STEP \
110 (!TARGET_COMPRESSION ? 0x7ff0 \
111 : TARGET_MICROMIPS || GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
112 : TARGET_64BIT ? 0x100 : 0x400)
114 /* True if INSN is a mips.md pattern or asm statement. */
115 /* ??? This test exists through the compiler, perhaps it should be
117 #define USEFUL_INSN_P(INSN) \
118 (NONDEBUG_INSN_P (INSN) \
119 && GET_CODE (PATTERN (INSN)) != USE \
120 && GET_CODE (PATTERN (INSN)) != CLOBBER)
122 /* If INSN is a delayed branch sequence, return the first instruction
123 in the sequence, otherwise return INSN itself. */
124 #define SEQ_BEGIN(INSN) \
125 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
126 ? as_a <rtx_insn *> (XVECEXP (PATTERN (INSN), 0, 0)) \
129 /* Likewise for the last instruction in a delayed branch sequence. */
130 #define SEQ_END(INSN) \
131 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
132 ? as_a <rtx_insn *> (XVECEXP (PATTERN (INSN), \
134 XVECLEN (PATTERN (INSN), 0) - 1)) \
137 /* Execute the following loop body with SUBINSN set to each instruction
138 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
139 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
140 for ((SUBINSN) = SEQ_BEGIN (INSN); \
141 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
142 (SUBINSN) = NEXT_INSN (SUBINSN))
144 /* True if bit BIT is set in VALUE. */
145 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
147 /* Return the opcode for a ptr_mode load of the form:
149 l[wd] DEST, OFFSET(BASE). */
150 #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \
151 (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \
156 /* Return the opcode to move register SRC into register DEST. */
157 #define MIPS_MOVE(DEST, SRC) \
158 ((TARGET_64BIT ? 0x2d : 0x21) \
162 /* Return the opcode for:
165 #define MIPS_LUI(DEST, VALUE) \
166 ((0xf << 26) | ((DEST) << 16) | (VALUE))
168 /* Return the opcode to jump to register DEST. */
169 #define MIPS_JR(DEST) \
170 (((DEST) << 21) | 0x8)
172 /* Return the opcode for:
174 bal . + (1 + OFFSET) * 4. */
175 #define MIPS_BAL(OFFSET) \
176 ((0x1 << 26) | (0x11 << 16) | (OFFSET))
178 /* Return the usual opcode for a nop. */
181 /* Classifies an address.
184 A natural register + offset address. The register satisfies
185 mips_valid_base_register_p and the offset is a const_arith_operand.
188 A LO_SUM rtx. The first operand is a valid base register and
189 the second operand is a symbolic address.
192 A signed 16-bit constant address.
195 A constant symbolic address. */
196 enum mips_address_type {
203 /* Macros to create an enumeration identifier for a function prototype. */
204 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
205 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
206 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
207 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
209 /* Classifies the prototype of a built-in function. */
210 enum mips_function_type {
211 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
212 #include "config/mips/mips-ftypes.def"
213 #undef DEF_MIPS_FTYPE
217 /* Specifies how a built-in function should be converted into rtl. */
218 enum mips_builtin_type {
219 /* The function corresponds directly to an .md pattern. The return
220 value is mapped to operand 0 and the arguments are mapped to
221 operands 1 and above. */
224 /* The function corresponds directly to an .md pattern. There is no return
225 value and the arguments are mapped to operands 0 and above. */
226 MIPS_BUILTIN_DIRECT_NO_TARGET,
228 /* The function corresponds to a comparison instruction followed by
229 a mips_cond_move_tf_ps pattern. The first two arguments are the
230 values to compare and the second two arguments are the vector
231 operands for the movt.ps or movf.ps instruction (in assembly order). */
235 /* The function corresponds to a V2SF comparison instruction. Operand 0
236 of this instruction is the result of the comparison, which has mode
237 CCV2 or CCV4. The function arguments are mapped to operands 1 and
238 above. The function's return value is an SImode boolean that is
239 true under the following conditions:
241 MIPS_BUILTIN_CMP_ANY: one of the registers is true
242 MIPS_BUILTIN_CMP_ALL: all of the registers are true
243 MIPS_BUILTIN_CMP_LOWER: the first register is true
244 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
245 MIPS_BUILTIN_CMP_ANY,
246 MIPS_BUILTIN_CMP_ALL,
247 MIPS_BUILTIN_CMP_UPPER,
248 MIPS_BUILTIN_CMP_LOWER,
250 /* As above, but the instruction only sets a single $fcc register. */
251 MIPS_BUILTIN_CMP_SINGLE,
253 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
254 MIPS_BUILTIN_BPOSGE32
257 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
258 #define MIPS_FP_CONDITIONS(MACRO) \
276 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
277 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
278 enum mips_fp_condition {
279 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
281 #undef DECLARE_MIPS_COND
283 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
284 #define STRINGIFY(X) #X
285 static const char *const mips_fp_conditions[] = {
286 MIPS_FP_CONDITIONS (STRINGIFY)
290 /* A class used to control a comdat-style stub that we output in each
291 translation unit that needs it. */
292 class mips_one_only_stub {
294 virtual ~mips_one_only_stub () {}
296 /* Return the name of the stub. */
297 virtual const char *get_name () = 0;
299 /* Output the body of the function to asm_out_file. */
300 virtual void output_body () = 0;
303 /* Tuning information that is automatically derived from other sources
304 (such as the scheduler). */
306 /* The architecture and tuning settings that this structure describes. */
310 /* True if this structure describes MIPS16 settings. */
313 /* True if the structure has been initialized. */
316 /* True if "MULT $0, $0" is preferable to "MTLO $0; MTHI $0"
317 when optimizing for speed. */
318 bool fast_mult_zero_zero_p;
321 /* Information about a function's frame layout. */
322 struct GTY(()) mips_frame_info {
323 /* The size of the frame in bytes. */
324 HOST_WIDE_INT total_size;
326 /* The number of bytes allocated to variables. */
327 HOST_WIDE_INT var_size;
329 /* The number of bytes allocated to outgoing function arguments. */
330 HOST_WIDE_INT args_size;
332 /* The number of bytes allocated to the .cprestore slot, or 0 if there
334 HOST_WIDE_INT cprestore_size;
336 /* Bit X is set if the function saves or restores GPR X. */
339 /* Likewise FPR X. */
342 /* Likewise doubleword accumulator X ($acX). */
343 unsigned int acc_mask;
345 /* The number of GPRs, FPRs, doubleword accumulators and COP0
349 unsigned int num_acc;
350 unsigned int num_cop0_regs;
352 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
353 save slots from the top of the frame, or zero if no such slots are
355 HOST_WIDE_INT gp_save_offset;
356 HOST_WIDE_INT fp_save_offset;
357 HOST_WIDE_INT acc_save_offset;
358 HOST_WIDE_INT cop0_save_offset;
360 /* Likewise, but giving offsets from the bottom of the frame. */
361 HOST_WIDE_INT gp_sp_offset;
362 HOST_WIDE_INT fp_sp_offset;
363 HOST_WIDE_INT acc_sp_offset;
364 HOST_WIDE_INT cop0_sp_offset;
366 /* Similar, but the value passed to _mcount. */
367 HOST_WIDE_INT ra_fp_offset;
369 /* The offset of arg_pointer_rtx from the bottom of the frame. */
370 HOST_WIDE_INT arg_pointer_offset;
372 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
373 HOST_WIDE_INT hard_frame_pointer_offset;
376 struct GTY(()) machine_function {
377 /* The next floating-point condition-code register to allocate
378 for ISA_HAS_8CC targets, relative to ST_REG_FIRST. */
379 unsigned int next_fcc;
381 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
382 rtx mips16_gp_pseudo_rtx;
384 /* The number of extra stack bytes taken up by register varargs.
385 This area is allocated by the callee at the very top of the frame. */
388 /* The current frame information, calculated by mips_compute_frame_info. */
389 struct mips_frame_info frame;
391 /* The register to use as the function's global pointer, or INVALID_REGNUM
392 if the function doesn't need one. */
393 unsigned int global_pointer;
395 /* How many instructions it takes to load a label into $AT, or 0 if
396 this property hasn't yet been calculated. */
397 unsigned int load_label_num_insns;
399 /* True if mips_adjust_insn_length should ignore an instruction's
401 bool ignore_hazard_length_p;
403 /* True if the whole function is suitable for .set noreorder and
405 bool all_noreorder_p;
407 /* True if the function has "inflexible" and "flexible" references
408 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
409 and mips_cfun_has_flexible_gp_ref_p for details. */
410 bool has_inflexible_gp_insn_p;
411 bool has_flexible_gp_insn_p;
413 /* True if the function's prologue must load the global pointer
414 value into pic_offset_table_rtx and store the same value in
415 the function's cprestore slot (if any). Even if this value
416 is currently false, we may decide to set it to true later;
417 see mips_must_initialize_gp_p () for details. */
418 bool must_initialize_gp_p;
420 /* True if the current function must restore $gp after any potential
421 clobber. This value is only meaningful during the first post-epilogue
422 split_insns pass; see mips_must_initialize_gp_p () for details. */
423 bool must_restore_gp_when_clobbered_p;
425 /* True if this is an interrupt handler. */
426 bool interrupt_handler_p;
428 /* True if this is an interrupt handler that uses shadow registers. */
429 bool use_shadow_register_set_p;
431 /* True if this is an interrupt handler that should keep interrupts
433 bool keep_interrupts_masked_p;
435 /* True if this is an interrupt handler that should use DERET
437 bool use_debug_exception_return_p;
440 /* Information about a single argument. */
441 struct mips_arg_info {
442 /* True if the argument is passed in a floating-point register, or
443 would have been if we hadn't run out of registers. */
446 /* The number of words passed in registers, rounded up. */
447 unsigned int reg_words;
449 /* For EABI, the offset of the first register from GP_ARG_FIRST or
450 FP_ARG_FIRST. For other ABIs, the offset of the first register from
451 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
452 comment for details).
454 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
456 unsigned int reg_offset;
458 /* The number of words that must be passed on the stack, rounded up. */
459 unsigned int stack_words;
461 /* The offset from the start of the stack overflow area of the argument's
462 first stack word. Only meaningful when STACK_WORDS is nonzero. */
463 unsigned int stack_offset;
466 /* Information about an address described by mips_address_type.
472 REG is the base register and OFFSET is the constant offset.
475 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
476 is the type of symbol it references.
479 SYMBOL_TYPE is the type of symbol that the address references. */
480 struct mips_address_info {
481 enum mips_address_type type;
484 enum mips_symbol_type symbol_type;
487 /* One stage in a constant building sequence. These sequences have
491 A = A CODE[1] VALUE[1]
492 A = A CODE[2] VALUE[2]
495 where A is an accumulator, each CODE[i] is a binary rtl operation
496 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
497 struct mips_integer_op {
499 unsigned HOST_WIDE_INT value;
502 /* The largest number of operations needed to load an integer constant.
503 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
504 When the lowest bit is clear, we can try, but reject a sequence with
505 an extra SLL at the end. */
506 #define MIPS_MAX_INTEGER_OPS 7
508 /* Information about a MIPS16e SAVE or RESTORE instruction. */
509 struct mips16e_save_restore_info {
510 /* The number of argument registers saved by a SAVE instruction.
511 0 for RESTORE instructions. */
514 /* Bit X is set if the instruction saves or restores GPR X. */
517 /* The total number of bytes to allocate. */
521 /* Costs of various operations on the different architectures. */
523 struct mips_rtx_cost_data
525 unsigned short fp_add;
526 unsigned short fp_mult_sf;
527 unsigned short fp_mult_df;
528 unsigned short fp_div_sf;
529 unsigned short fp_div_df;
530 unsigned short int_mult_si;
531 unsigned short int_mult_di;
532 unsigned short int_div_si;
533 unsigned short int_div_di;
534 unsigned short branch_cost;
535 unsigned short memory_latency;
538 /* Global variables for machine-dependent things. */
540 /* The -G setting, or the configuration's default small-data limit if
541 no -G option is given. */
542 static unsigned int mips_small_data_threshold;
544 /* The number of file directives written by mips_output_filename. */
545 int num_source_filenames;
547 /* The name that appeared in the last .file directive written by
548 mips_output_filename, or "" if mips_output_filename hasn't
549 written anything yet. */
550 const char *current_function_file = "";
552 /* Arrays that map GCC register numbers to debugger register numbers. */
553 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
554 int mips_dwarf_regno[FIRST_PSEUDO_REGISTER];
556 /* Information about the current function's epilogue, used only while
559 /* A list of queued REG_CFA_RESTORE notes. */
562 /* The CFA is currently defined as CFA_REG + CFA_OFFSET. */
564 HOST_WIDE_INT cfa_offset;
566 /* The offset of the CFA from the stack pointer while restoring
568 HOST_WIDE_INT cfa_restore_sp_offset;
571 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
572 struct mips_asm_switch mips_noreorder = { "reorder", 0 };
573 struct mips_asm_switch mips_nomacro = { "macro", 0 };
574 struct mips_asm_switch mips_noat = { "at", 0 };
576 /* True if we're writing out a branch-likely instruction rather than a
578 static bool mips_branch_likely;
580 /* The current instruction-set architecture. */
581 enum processor mips_arch;
582 const struct mips_cpu_info *mips_arch_info;
584 /* The processor that we should tune the code for. */
585 enum processor mips_tune;
586 const struct mips_cpu_info *mips_tune_info;
588 /* The ISA level associated with mips_arch. */
591 /* The ISA revision level. This is 0 for MIPS I to V and N for
595 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
596 static const struct mips_cpu_info *mips_isa_option_info;
598 /* Which cost information to use. */
599 static const struct mips_rtx_cost_data *mips_cost;
601 /* The ambient target flags, excluding MASK_MIPS16. */
602 static int mips_base_target_flags;
604 /* The default compression mode. */
605 unsigned int mips_base_compression_flags;
607 /* The ambient values of other global variables. */
608 static int mips_base_schedule_insns; /* flag_schedule_insns */
609 static int mips_base_reorder_blocks_and_partition; /* flag_reorder... */
610 static int mips_base_move_loop_invariants; /* flag_move_loop_invariants */
611 static int mips_base_align_loops; /* align_loops */
612 static int mips_base_align_jumps; /* align_jumps */
613 static int mips_base_align_functions; /* align_functions */
615 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
616 bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
618 /* Index C is true if character C is a valid PRINT_OPERAND punctation
620 static bool mips_print_operand_punct[256];
622 static GTY (()) int mips_output_filename_first_time = 1;
624 /* mips_split_p[X] is true if symbols of type X can be split by
625 mips_split_symbol. */
626 bool mips_split_p[NUM_SYMBOL_TYPES];
628 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
629 can be split by mips_split_symbol. */
630 bool mips_split_hi_p[NUM_SYMBOL_TYPES];
632 /* mips_use_pcrel_pool_p[X] is true if symbols of type X should be
633 forced into a PC-relative constant pool. */
634 bool mips_use_pcrel_pool_p[NUM_SYMBOL_TYPES];
636 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
637 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
638 if they are matched by a special .md file pattern. */
639 const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
641 /* Likewise for HIGHs. */
642 const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
644 /* Target state for MIPS16. */
645 struct target_globals *mips16_globals;
647 /* Cached value of can_issue_more. This is cached in mips_variable_issue hook
648 and returned from mips_sched_reorder2. */
649 static int cached_can_issue_more;
651 /* The stubs for various MIPS16 support functions, if used. */
652 static mips_one_only_stub *mips16_rdhwr_stub;
653 static mips_one_only_stub *mips16_get_fcsr_stub;
654 static mips_one_only_stub *mips16_set_fcsr_stub;
656 /* Index R is the smallest register class that contains register R. */
657 const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = {
658 LEA_REGS, LEA_REGS, M16_STORE_REGS, V1_REG,
659 M16_STORE_REGS, M16_STORE_REGS, M16_STORE_REGS, M16_STORE_REGS,
660 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
661 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
662 M16_REGS, M16_STORE_REGS, LEA_REGS, LEA_REGS,
663 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
664 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
665 LEA_REGS, M16_SP_REGS, LEA_REGS, LEA_REGS,
667 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
668 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
669 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
670 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
671 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
672 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
673 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
674 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
675 MD0_REG, MD1_REG, NO_REGS, ST_REGS,
676 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
677 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
678 NO_REGS, FRAME_REGS, FRAME_REGS, NO_REGS,
679 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
680 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
681 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
682 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
683 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
684 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
685 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
686 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
687 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
688 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
689 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
690 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
691 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
692 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
693 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
694 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
695 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
696 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
697 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
698 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
699 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
700 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
701 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
702 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
703 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
704 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
705 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
708 /* The value of TARGET_ATTRIBUTE_TABLE. */
709 static const struct attribute_spec mips_attribute_table[] = {
710 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
712 { "long_call", 0, 0, false, true, true, NULL, false },
713 { "far", 0, 0, false, true, true, NULL, false },
714 { "near", 0, 0, false, true, true, NULL, false },
715 /* We would really like to treat "mips16" and "nomips16" as type
716 attributes, but GCC doesn't provide the hooks we need to support
717 the right conversion rules. As declaration attributes, they affect
718 code generation but don't carry other semantics. */
719 { "mips16", 0, 0, true, false, false, NULL, false },
720 { "nomips16", 0, 0, true, false, false, NULL, false },
721 { "micromips", 0, 0, true, false, false, NULL, false },
722 { "nomicromips", 0, 0, true, false, false, NULL, false },
723 { "nocompression", 0, 0, true, false, false, NULL, false },
724 /* Allow functions to be specified as interrupt handlers */
725 { "interrupt", 0, 0, false, true, true, NULL, false },
726 { "use_shadow_register_set", 0, 0, false, true, true, NULL, false },
727 { "keep_interrupts_masked", 0, 0, false, true, true, NULL, false },
728 { "use_debug_exception_return", 0, 0, false, true, true, NULL, false },
729 { NULL, 0, 0, false, false, false, NULL, false }
732 /* A table describing all the processors GCC knows about; see
733 mips-cpus.def for details. */
734 static const struct mips_cpu_info mips_cpu_info_table[] = {
735 #define MIPS_CPU(NAME, CPU, ISA, FLAGS) \
736 { NAME, CPU, ISA, FLAGS },
737 #include "mips-cpus.def"
741 /* Default costs. If these are used for a processor we should look
742 up the actual costs. */
743 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
744 COSTS_N_INSNS (7), /* fp_mult_sf */ \
745 COSTS_N_INSNS (8), /* fp_mult_df */ \
746 COSTS_N_INSNS (23), /* fp_div_sf */ \
747 COSTS_N_INSNS (36), /* fp_div_df */ \
748 COSTS_N_INSNS (10), /* int_mult_si */ \
749 COSTS_N_INSNS (10), /* int_mult_di */ \
750 COSTS_N_INSNS (69), /* int_div_si */ \
751 COSTS_N_INSNS (69), /* int_div_di */ \
752 2, /* branch_cost */ \
753 4 /* memory_latency */
755 /* Floating-point costs for processors without an FPU. Just assume that
756 all floating-point libcalls are very expensive. */
757 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
758 COSTS_N_INSNS (256), /* fp_mult_sf */ \
759 COSTS_N_INSNS (256), /* fp_mult_df */ \
760 COSTS_N_INSNS (256), /* fp_div_sf */ \
761 COSTS_N_INSNS (256) /* fp_div_df */
763 /* Costs to use when optimizing for size. */
764 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size = {
765 COSTS_N_INSNS (1), /* fp_add */
766 COSTS_N_INSNS (1), /* fp_mult_sf */
767 COSTS_N_INSNS (1), /* fp_mult_df */
768 COSTS_N_INSNS (1), /* fp_div_sf */
769 COSTS_N_INSNS (1), /* fp_div_df */
770 COSTS_N_INSNS (1), /* int_mult_si */
771 COSTS_N_INSNS (1), /* int_mult_di */
772 COSTS_N_INSNS (1), /* int_div_si */
773 COSTS_N_INSNS (1), /* int_div_di */
775 4 /* memory_latency */
778 /* Costs to use when optimizing for speed, indexed by processor. */
779 static const struct mips_rtx_cost_data
780 mips_rtx_cost_data[NUM_PROCESSOR_VALUES] = {
782 COSTS_N_INSNS (2), /* fp_add */
783 COSTS_N_INSNS (4), /* fp_mult_sf */
784 COSTS_N_INSNS (5), /* fp_mult_df */
785 COSTS_N_INSNS (12), /* fp_div_sf */
786 COSTS_N_INSNS (19), /* fp_div_df */
787 COSTS_N_INSNS (12), /* int_mult_si */
788 COSTS_N_INSNS (12), /* int_mult_di */
789 COSTS_N_INSNS (35), /* int_div_si */
790 COSTS_N_INSNS (35), /* int_div_di */
792 4 /* memory_latency */
796 COSTS_N_INSNS (6), /* int_mult_si */
797 COSTS_N_INSNS (6), /* int_mult_di */
798 COSTS_N_INSNS (36), /* int_div_si */
799 COSTS_N_INSNS (36), /* int_div_di */
801 4 /* memory_latency */
805 COSTS_N_INSNS (36), /* int_mult_si */
806 COSTS_N_INSNS (36), /* int_mult_di */
807 COSTS_N_INSNS (37), /* int_div_si */
808 COSTS_N_INSNS (37), /* int_div_di */
810 4 /* memory_latency */
814 COSTS_N_INSNS (4), /* int_mult_si */
815 COSTS_N_INSNS (11), /* int_mult_di */
816 COSTS_N_INSNS (36), /* int_div_si */
817 COSTS_N_INSNS (68), /* int_div_di */
819 4 /* memory_latency */
822 COSTS_N_INSNS (4), /* fp_add */
823 COSTS_N_INSNS (4), /* fp_mult_sf */
824 COSTS_N_INSNS (5), /* fp_mult_df */
825 COSTS_N_INSNS (17), /* fp_div_sf */
826 COSTS_N_INSNS (32), /* fp_div_df */
827 COSTS_N_INSNS (4), /* int_mult_si */
828 COSTS_N_INSNS (11), /* int_mult_di */
829 COSTS_N_INSNS (36), /* int_div_si */
830 COSTS_N_INSNS (68), /* int_div_di */
832 4 /* memory_latency */
835 COSTS_N_INSNS (4), /* fp_add */
836 COSTS_N_INSNS (4), /* fp_mult_sf */
837 COSTS_N_INSNS (5), /* fp_mult_df */
838 COSTS_N_INSNS (17), /* fp_div_sf */
839 COSTS_N_INSNS (32), /* fp_div_df */
840 COSTS_N_INSNS (4), /* int_mult_si */
841 COSTS_N_INSNS (7), /* int_mult_di */
842 COSTS_N_INSNS (42), /* int_div_si */
843 COSTS_N_INSNS (72), /* int_div_di */
845 4 /* memory_latency */
849 COSTS_N_INSNS (5), /* int_mult_si */
850 COSTS_N_INSNS (5), /* int_mult_di */
851 COSTS_N_INSNS (41), /* int_div_si */
852 COSTS_N_INSNS (41), /* int_div_di */
854 4 /* memory_latency */
857 COSTS_N_INSNS (8), /* fp_add */
858 COSTS_N_INSNS (8), /* fp_mult_sf */
859 COSTS_N_INSNS (10), /* fp_mult_df */
860 COSTS_N_INSNS (34), /* fp_div_sf */
861 COSTS_N_INSNS (64), /* fp_div_df */
862 COSTS_N_INSNS (5), /* int_mult_si */
863 COSTS_N_INSNS (5), /* int_mult_di */
864 COSTS_N_INSNS (41), /* int_div_si */
865 COSTS_N_INSNS (41), /* int_div_di */
867 4 /* memory_latency */
870 COSTS_N_INSNS (4), /* fp_add */
871 COSTS_N_INSNS (4), /* fp_mult_sf */
872 COSTS_N_INSNS (5), /* fp_mult_df */
873 COSTS_N_INSNS (17), /* fp_div_sf */
874 COSTS_N_INSNS (32), /* fp_div_df */
875 COSTS_N_INSNS (5), /* int_mult_si */
876 COSTS_N_INSNS (5), /* int_mult_di */
877 COSTS_N_INSNS (41), /* int_div_si */
878 COSTS_N_INSNS (41), /* int_div_di */
880 4 /* memory_latency */
884 COSTS_N_INSNS (5), /* int_mult_si */
885 COSTS_N_INSNS (5), /* int_mult_di */
886 COSTS_N_INSNS (41), /* int_div_si */
887 COSTS_N_INSNS (41), /* int_div_di */
889 4 /* memory_latency */
892 COSTS_N_INSNS (8), /* fp_add */
893 COSTS_N_INSNS (8), /* fp_mult_sf */
894 COSTS_N_INSNS (10), /* fp_mult_df */
895 COSTS_N_INSNS (34), /* fp_div_sf */
896 COSTS_N_INSNS (64), /* fp_div_df */
897 COSTS_N_INSNS (5), /* int_mult_si */
898 COSTS_N_INSNS (5), /* int_mult_di */
899 COSTS_N_INSNS (41), /* int_div_si */
900 COSTS_N_INSNS (41), /* int_div_di */
902 4 /* memory_latency */
905 COSTS_N_INSNS (4), /* fp_add */
906 COSTS_N_INSNS (4), /* fp_mult_sf */
907 COSTS_N_INSNS (5), /* fp_mult_df */
908 COSTS_N_INSNS (17), /* fp_div_sf */
909 COSTS_N_INSNS (32), /* fp_div_df */
910 COSTS_N_INSNS (5), /* int_mult_si */
911 COSTS_N_INSNS (5), /* int_mult_di */
912 COSTS_N_INSNS (41), /* int_div_si */
913 COSTS_N_INSNS (41), /* int_div_di */
915 4 /* memory_latency */
918 COSTS_N_INSNS (6), /* fp_add */
919 COSTS_N_INSNS (6), /* fp_mult_sf */
920 COSTS_N_INSNS (7), /* fp_mult_df */
921 COSTS_N_INSNS (25), /* fp_div_sf */
922 COSTS_N_INSNS (48), /* fp_div_df */
923 COSTS_N_INSNS (5), /* int_mult_si */
924 COSTS_N_INSNS (5), /* int_mult_di */
925 COSTS_N_INSNS (41), /* int_div_si */
926 COSTS_N_INSNS (41), /* int_div_di */
928 4 /* memory_latency */
945 COSTS_N_INSNS (5), /* int_mult_si */
946 COSTS_N_INSNS (5), /* int_mult_di */
947 COSTS_N_INSNS (72), /* int_div_si */
948 COSTS_N_INSNS (72), /* int_div_di */
950 4 /* memory_latency */
955 COSTS_N_INSNS (6), /* int_mult_si */
956 COSTS_N_INSNS (6), /* int_mult_di */
957 COSTS_N_INSNS (18), /* int_div_si */
958 COSTS_N_INSNS (35), /* int_div_di */
960 4 /* memory_latency */
963 COSTS_N_INSNS (2), /* fp_add */
964 COSTS_N_INSNS (4), /* fp_mult_sf */
965 COSTS_N_INSNS (5), /* fp_mult_df */
966 COSTS_N_INSNS (12), /* fp_div_sf */
967 COSTS_N_INSNS (19), /* fp_div_df */
968 COSTS_N_INSNS (2), /* int_mult_si */
969 COSTS_N_INSNS (2), /* int_mult_di */
970 COSTS_N_INSNS (35), /* int_div_si */
971 COSTS_N_INSNS (35), /* int_div_di */
973 4 /* memory_latency */
976 COSTS_N_INSNS (3), /* fp_add */
977 COSTS_N_INSNS (5), /* fp_mult_sf */
978 COSTS_N_INSNS (6), /* fp_mult_df */
979 COSTS_N_INSNS (15), /* fp_div_sf */
980 COSTS_N_INSNS (16), /* fp_div_df */
981 COSTS_N_INSNS (17), /* int_mult_si */
982 COSTS_N_INSNS (17), /* int_mult_di */
983 COSTS_N_INSNS (38), /* int_div_si */
984 COSTS_N_INSNS (38), /* int_div_di */
986 6 /* memory_latency */
989 COSTS_N_INSNS (6), /* fp_add */
990 COSTS_N_INSNS (7), /* fp_mult_sf */
991 COSTS_N_INSNS (8), /* fp_mult_df */
992 COSTS_N_INSNS (23), /* fp_div_sf */
993 COSTS_N_INSNS (36), /* fp_div_df */
994 COSTS_N_INSNS (10), /* int_mult_si */
995 COSTS_N_INSNS (10), /* int_mult_di */
996 COSTS_N_INSNS (69), /* int_div_si */
997 COSTS_N_INSNS (69), /* int_div_di */
999 6 /* memory_latency */
1011 /* The only costs that appear to be updated here are
1012 integer multiplication. */
1014 COSTS_N_INSNS (4), /* int_mult_si */
1015 COSTS_N_INSNS (6), /* int_mult_di */
1016 COSTS_N_INSNS (69), /* int_div_si */
1017 COSTS_N_INSNS (69), /* int_div_di */
1018 1, /* branch_cost */
1019 4 /* memory_latency */
1034 COSTS_N_INSNS (6), /* fp_add */
1035 COSTS_N_INSNS (4), /* fp_mult_sf */
1036 COSTS_N_INSNS (5), /* fp_mult_df */
1037 COSTS_N_INSNS (23), /* fp_div_sf */
1038 COSTS_N_INSNS (36), /* fp_div_df */
1039 COSTS_N_INSNS (5), /* int_mult_si */
1040 COSTS_N_INSNS (5), /* int_mult_di */
1041 COSTS_N_INSNS (36), /* int_div_si */
1042 COSTS_N_INSNS (36), /* int_div_di */
1043 1, /* branch_cost */
1044 4 /* memory_latency */
1047 COSTS_N_INSNS (6), /* fp_add */
1048 COSTS_N_INSNS (5), /* fp_mult_sf */
1049 COSTS_N_INSNS (6), /* fp_mult_df */
1050 COSTS_N_INSNS (30), /* fp_div_sf */
1051 COSTS_N_INSNS (59), /* fp_div_df */
1052 COSTS_N_INSNS (3), /* int_mult_si */
1053 COSTS_N_INSNS (4), /* int_mult_di */
1054 COSTS_N_INSNS (42), /* int_div_si */
1055 COSTS_N_INSNS (74), /* int_div_di */
1056 1, /* branch_cost */
1057 4 /* memory_latency */
1060 COSTS_N_INSNS (6), /* fp_add */
1061 COSTS_N_INSNS (5), /* fp_mult_sf */
1062 COSTS_N_INSNS (6), /* fp_mult_df */
1063 COSTS_N_INSNS (30), /* fp_div_sf */
1064 COSTS_N_INSNS (59), /* fp_div_df */
1065 COSTS_N_INSNS (5), /* int_mult_si */
1066 COSTS_N_INSNS (9), /* int_mult_di */
1067 COSTS_N_INSNS (42), /* int_div_si */
1068 COSTS_N_INSNS (74), /* int_div_di */
1069 1, /* branch_cost */
1070 4 /* memory_latency */
1073 COSTS_N_INSNS (4), /* fp_add */
1074 COSTS_N_INSNS (4), /* fp_mult_sf */
1075 COSTS_N_INSNS (256), /* fp_mult_df */
1076 COSTS_N_INSNS (8), /* fp_div_sf */
1077 COSTS_N_INSNS (256), /* fp_div_df */
1078 COSTS_N_INSNS (4), /* int_mult_si */
1079 COSTS_N_INSNS (256), /* int_mult_di */
1080 COSTS_N_INSNS (37), /* int_div_si */
1081 COSTS_N_INSNS (256), /* int_div_di */
1082 1, /* branch_cost */
1083 4 /* memory_latency */
1086 /* The only costs that are changed here are
1087 integer multiplication. */
1088 COSTS_N_INSNS (6), /* fp_add */
1089 COSTS_N_INSNS (7), /* fp_mult_sf */
1090 COSTS_N_INSNS (8), /* fp_mult_df */
1091 COSTS_N_INSNS (23), /* fp_div_sf */
1092 COSTS_N_INSNS (36), /* fp_div_df */
1093 COSTS_N_INSNS (5), /* int_mult_si */
1094 COSTS_N_INSNS (9), /* int_mult_di */
1095 COSTS_N_INSNS (69), /* int_div_si */
1096 COSTS_N_INSNS (69), /* int_div_di */
1097 1, /* branch_cost */
1098 4 /* memory_latency */
1104 /* The only costs that are changed here are
1105 integer multiplication. */
1106 COSTS_N_INSNS (6), /* fp_add */
1107 COSTS_N_INSNS (7), /* fp_mult_sf */
1108 COSTS_N_INSNS (8), /* fp_mult_df */
1109 COSTS_N_INSNS (23), /* fp_div_sf */
1110 COSTS_N_INSNS (36), /* fp_div_df */
1111 COSTS_N_INSNS (3), /* int_mult_si */
1112 COSTS_N_INSNS (8), /* int_mult_di */
1113 COSTS_N_INSNS (69), /* int_div_si */
1114 COSTS_N_INSNS (69), /* int_div_di */
1115 1, /* branch_cost */
1116 4 /* memory_latency */
1119 COSTS_N_INSNS (2), /* fp_add */
1120 COSTS_N_INSNS (2), /* fp_mult_sf */
1121 COSTS_N_INSNS (2), /* fp_mult_df */
1122 COSTS_N_INSNS (12), /* fp_div_sf */
1123 COSTS_N_INSNS (19), /* fp_div_df */
1124 COSTS_N_INSNS (5), /* int_mult_si */
1125 COSTS_N_INSNS (9), /* int_mult_di */
1126 COSTS_N_INSNS (34), /* int_div_si */
1127 COSTS_N_INSNS (66), /* int_div_di */
1128 1, /* branch_cost */
1129 4 /* memory_latency */
1132 /* These costs are the same as the SB-1A below. */
1133 COSTS_N_INSNS (4), /* fp_add */
1134 COSTS_N_INSNS (4), /* fp_mult_sf */
1135 COSTS_N_INSNS (4), /* fp_mult_df */
1136 COSTS_N_INSNS (24), /* fp_div_sf */
1137 COSTS_N_INSNS (32), /* fp_div_df */
1138 COSTS_N_INSNS (3), /* int_mult_si */
1139 COSTS_N_INSNS (4), /* int_mult_di */
1140 COSTS_N_INSNS (36), /* int_div_si */
1141 COSTS_N_INSNS (68), /* int_div_di */
1142 1, /* branch_cost */
1143 4 /* memory_latency */
1146 /* These costs are the same as the SB-1 above. */
1147 COSTS_N_INSNS (4), /* fp_add */
1148 COSTS_N_INSNS (4), /* fp_mult_sf */
1149 COSTS_N_INSNS (4), /* fp_mult_df */
1150 COSTS_N_INSNS (24), /* fp_div_sf */
1151 COSTS_N_INSNS (32), /* fp_div_df */
1152 COSTS_N_INSNS (3), /* int_mult_si */
1153 COSTS_N_INSNS (4), /* int_mult_di */
1154 COSTS_N_INSNS (36), /* int_div_si */
1155 COSTS_N_INSNS (68), /* int_div_di */
1156 1, /* branch_cost */
1157 4 /* memory_latency */
1164 COSTS_N_INSNS (8), /* int_mult_si */
1165 COSTS_N_INSNS (8), /* int_mult_di */
1166 COSTS_N_INSNS (72), /* int_div_si */
1167 COSTS_N_INSNS (72), /* int_div_di */
1168 1, /* branch_cost */
1169 4 /* memory_latency */
1172 /* These costs are the same as 5KF above. */
1173 COSTS_N_INSNS (4), /* fp_add */
1174 COSTS_N_INSNS (4), /* fp_mult_sf */
1175 COSTS_N_INSNS (5), /* fp_mult_df */
1176 COSTS_N_INSNS (17), /* fp_div_sf */
1177 COSTS_N_INSNS (32), /* fp_div_df */
1178 COSTS_N_INSNS (4), /* int_mult_si */
1179 COSTS_N_INSNS (11), /* int_mult_di */
1180 COSTS_N_INSNS (36), /* int_div_si */
1181 COSTS_N_INSNS (68), /* int_div_di */
1182 1, /* branch_cost */
1183 4 /* memory_latency */
1186 COSTS_N_INSNS (4), /* fp_add */
1187 COSTS_N_INSNS (5), /* fp_mult_sf */
1188 COSTS_N_INSNS (5), /* fp_mult_df */
1189 COSTS_N_INSNS (17), /* fp_div_sf */
1190 COSTS_N_INSNS (17), /* fp_div_df */
1191 COSTS_N_INSNS (5), /* int_mult_si */
1192 COSTS_N_INSNS (5), /* int_mult_di */
1193 COSTS_N_INSNS (8), /* int_div_si */
1194 COSTS_N_INSNS (8), /* int_div_di */
1195 2, /* branch_cost */
1196 10 /* memory_latency */
1200 static rtx mips_find_pic_call_symbol (rtx_insn *, rtx, bool);
1201 static int mips_register_move_cost (enum machine_mode, reg_class_t,
1203 static unsigned int mips_function_arg_boundary (enum machine_mode, const_tree);
1205 struct mips16_flip_traits : default_hashmap_traits
1207 static hashval_t hash (const char *s) { return htab_hash_string (s); }
1209 equal_keys (const char *a, const char *b)
1211 return !strcmp (a, b);
1215 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1216 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1217 static GTY (()) hash_map<const char *, bool, mips16_flip_traits> *
1220 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1221 mode, false if it should next add an attribute for the opposite mode. */
1222 static GTY(()) bool mips16_flipper;
1224 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1225 for -mflip-mips16. Return true if it should use "mips16" and false if
1226 it should use "nomips16". */
1229 mflip_mips16_use_mips16_p (tree decl)
1232 bool base_is_mips16 = (mips_base_compression_flags & MASK_MIPS16) != 0;
1234 /* Use the opposite of the command-line setting for anonymous decls. */
1235 if (!DECL_NAME (decl))
1236 return !base_is_mips16;
1238 if (!mflip_mips16_htab)
1240 = hash_map<const char *, bool, mips16_flip_traits>::create_ggc (37);
1242 name = IDENTIFIER_POINTER (DECL_NAME (decl));
1245 bool *slot = &mflip_mips16_htab->get_or_insert (name, &existed);
1248 mips16_flipper = !mips16_flipper;
1249 *slot = mips16_flipper ? !base_is_mips16 : base_is_mips16;
1254 /* Predicates to test for presence of "near" and "far"/"long_call"
1255 attributes on the given TYPE. */
1258 mips_near_type_p (const_tree type)
1260 return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL;
1264 mips_far_type_p (const_tree type)
1266 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL
1267 || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL);
1271 /* Check if the interrupt attribute is set for a function. */
1274 mips_interrupt_type_p (tree type)
1276 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type)) != NULL;
1279 /* Check if the attribute to use shadow register set is set for a function. */
1282 mips_use_shadow_register_set_p (tree type)
1284 return lookup_attribute ("use_shadow_register_set",
1285 TYPE_ATTRIBUTES (type)) != NULL;
1288 /* Check if the attribute to keep interrupts masked is set for a function. */
1291 mips_keep_interrupts_masked_p (tree type)
1293 return lookup_attribute ("keep_interrupts_masked",
1294 TYPE_ATTRIBUTES (type)) != NULL;
1297 /* Check if the attribute to use debug exception return is set for
1301 mips_use_debug_exception_return_p (tree type)
1303 return lookup_attribute ("use_debug_exception_return",
1304 TYPE_ATTRIBUTES (type)) != NULL;
1307 /* Return the set of compression modes that are explicitly required
1308 by the attributes in ATTRIBUTES. */
1311 mips_get_compress_on_flags (tree attributes)
1313 unsigned int flags = 0;
1315 if (lookup_attribute ("mips16", attributes) != NULL)
1316 flags |= MASK_MIPS16;
1318 if (lookup_attribute ("micromips", attributes) != NULL)
1319 flags |= MASK_MICROMIPS;
1324 /* Return the set of compression modes that are explicitly forbidden
1325 by the attributes in ATTRIBUTES. */
1328 mips_get_compress_off_flags (tree attributes)
1330 unsigned int flags = 0;
1332 if (lookup_attribute ("nocompression", attributes) != NULL)
1333 flags |= MASK_MIPS16 | MASK_MICROMIPS;
1335 if (lookup_attribute ("nomips16", attributes) != NULL)
1336 flags |= MASK_MIPS16;
1338 if (lookup_attribute ("nomicromips", attributes) != NULL)
1339 flags |= MASK_MICROMIPS;
1344 /* Return the compression mode that should be used for function DECL.
1345 Return the ambient setting if DECL is null. */
1348 mips_get_compress_mode (tree decl)
1350 unsigned int flags, force_on;
1352 flags = mips_base_compression_flags;
1355 /* Nested functions must use the same frame pointer as their
1356 parent and must therefore use the same ISA mode. */
1357 tree parent = decl_function_context (decl);
1360 force_on = mips_get_compress_on_flags (DECL_ATTRIBUTES (decl));
1363 flags &= ~mips_get_compress_off_flags (DECL_ATTRIBUTES (decl));
1368 /* Return the attribute name associated with MASK_MIPS16 and MASK_MICROMIPS
1372 mips_get_compress_on_name (unsigned int flags)
1374 if (flags == MASK_MIPS16)
1379 /* Return the attribute name that forbids MASK_MIPS16 and MASK_MICROMIPS
1383 mips_get_compress_off_name (unsigned int flags)
1385 if (flags == MASK_MIPS16)
1387 if (flags == MASK_MICROMIPS)
1388 return "nomicromips";
1389 return "nocompression";
1392 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1395 mips_comp_type_attributes (const_tree type1, const_tree type2)
1397 /* Disallow mixed near/far attributes. */
1398 if (mips_far_type_p (type1) && mips_near_type_p (type2))
1400 if (mips_near_type_p (type1) && mips_far_type_p (type2))
1405 /* Implement TARGET_INSERT_ATTRIBUTES. */
1408 mips_insert_attributes (tree decl, tree *attributes)
1411 unsigned int compression_flags, nocompression_flags;
1413 /* Check for "mips16" and "nomips16" attributes. */
1414 compression_flags = mips_get_compress_on_flags (*attributes);
1415 nocompression_flags = mips_get_compress_off_flags (*attributes);
1417 if (TREE_CODE (decl) != FUNCTION_DECL)
1419 if (nocompression_flags)
1420 error ("%qs attribute only applies to functions",
1421 mips_get_compress_off_name (nocompression_flags));
1423 if (compression_flags)
1424 error ("%qs attribute only applies to functions",
1425 mips_get_compress_on_name (nocompression_flags));
1429 compression_flags |= mips_get_compress_on_flags (DECL_ATTRIBUTES (decl));
1430 nocompression_flags |=
1431 mips_get_compress_off_flags (DECL_ATTRIBUTES (decl));
1433 if (compression_flags && nocompression_flags)
1434 error ("%qE cannot have both %qs and %qs attributes",
1435 DECL_NAME (decl), mips_get_compress_on_name (compression_flags),
1436 mips_get_compress_off_name (nocompression_flags));
1438 if (compression_flags & MASK_MIPS16
1439 && compression_flags & MASK_MICROMIPS)
1440 error ("%qE cannot have both %qs and %qs attributes",
1441 DECL_NAME (decl), "mips16", "micromips");
1443 if (TARGET_FLIP_MIPS16
1444 && !DECL_ARTIFICIAL (decl)
1445 && compression_flags == 0
1446 && nocompression_flags == 0)
1448 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1449 "mips16" attribute, arbitrarily pick one. We must pick the same
1450 setting for duplicate declarations of a function. */
1451 name = mflip_mips16_use_mips16_p (decl) ? "mips16" : "nomips16";
1452 *attributes = tree_cons (get_identifier (name), NULL, *attributes);
1453 name = "nomicromips";
1454 *attributes = tree_cons (get_identifier (name), NULL, *attributes);
1459 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1462 mips_merge_decl_attributes (tree olddecl, tree newdecl)
1466 diff = (mips_get_compress_on_flags (DECL_ATTRIBUTES (olddecl))
1467 ^ mips_get_compress_on_flags (DECL_ATTRIBUTES (newdecl)));
1469 error ("%qE redeclared with conflicting %qs attributes",
1470 DECL_NAME (newdecl), mips_get_compress_on_name (diff));
1472 diff = (mips_get_compress_off_flags (DECL_ATTRIBUTES (olddecl))
1473 ^ mips_get_compress_off_flags (DECL_ATTRIBUTES (newdecl)));
1475 error ("%qE redeclared with conflicting %qs attributes",
1476 DECL_NAME (newdecl), mips_get_compress_off_name (diff));
1478 return merge_attributes (DECL_ATTRIBUTES (olddecl),
1479 DECL_ATTRIBUTES (newdecl));
1482 /* Implement TARGET_CAN_INLINE_P. */
1485 mips_can_inline_p (tree caller, tree callee)
1487 if (mips_get_compress_mode (callee) != mips_get_compress_mode (caller))
1489 return default_target_can_inline_p (caller, callee);
1492 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1493 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1496 mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr)
1498 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
1500 *base_ptr = XEXP (x, 0);
1501 *offset_ptr = INTVAL (XEXP (x, 1));
1510 static unsigned int mips_build_integer (struct mips_integer_op *,
1511 unsigned HOST_WIDE_INT);
1513 /* A subroutine of mips_build_integer, with the same interface.
1514 Assume that the final action in the sequence should be a left shift. */
1517 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1519 unsigned int i, shift;
1521 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1522 since signed numbers are easier to load than unsigned ones. */
1524 while ((value & 1) == 0)
1525 value /= 2, shift++;
1527 i = mips_build_integer (codes, value);
1528 codes[i].code = ASHIFT;
1529 codes[i].value = shift;
1533 /* As for mips_build_shift, but assume that the final action will be
1534 an IOR or PLUS operation. */
1537 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1539 unsigned HOST_WIDE_INT high;
1542 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1543 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
1545 /* The constant is too complex to load with a simple LUI/ORI pair,
1546 so we want to give the recursive call as many trailing zeros as
1547 possible. In this case, we know bit 16 is set and that the
1548 low 16 bits form a negative number. If we subtract that number
1549 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1550 i = mips_build_integer (codes, CONST_HIGH_PART (value));
1551 codes[i].code = PLUS;
1552 codes[i].value = CONST_LOW_PART (value);
1556 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1557 bits gives a value with at least 17 trailing zeros. */
1558 i = mips_build_integer (codes, high);
1559 codes[i].code = IOR;
1560 codes[i].value = value & 0xffff;
1565 /* Fill CODES with a sequence of rtl operations to load VALUE.
1566 Return the number of operations needed. */
1569 mips_build_integer (struct mips_integer_op *codes,
1570 unsigned HOST_WIDE_INT value)
1572 if (SMALL_OPERAND (value)
1573 || SMALL_OPERAND_UNSIGNED (value)
1574 || LUI_OPERAND (value))
1576 /* The value can be loaded with a single instruction. */
1577 codes[0].code = UNKNOWN;
1578 codes[0].value = value;
1581 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
1583 /* Either the constant is a simple LUI/ORI combination or its
1584 lowest bit is set. We don't want to shift in this case. */
1585 return mips_build_lower (codes, value);
1587 else if ((value & 0xffff) == 0)
1589 /* The constant will need at least three actions. The lowest
1590 16 bits are clear, so the final action will be a shift. */
1591 return mips_build_shift (codes, value);
1595 /* The final action could be a shift, add or inclusive OR.
1596 Rather than use a complex condition to select the best
1597 approach, try both mips_build_shift and mips_build_lower
1598 and pick the one that gives the shortest sequence.
1599 Note that this case is only used once per constant. */
1600 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1601 unsigned int cost, alt_cost;
1603 cost = mips_build_shift (codes, value);
1604 alt_cost = mips_build_lower (alt_codes, value);
1605 if (alt_cost < cost)
1607 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
1614 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
1617 mips_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
1619 return mips_const_insns (x) > 0;
1622 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
1625 mips16_stub_function (const char *name)
1629 x = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
1630 SYMBOL_REF_FLAGS (x) |= (SYMBOL_FLAG_EXTERNAL | SYMBOL_FLAG_FUNCTION);
1634 /* Return a legitimate call address for STUB, given that STUB is a MIPS16
1635 support function. */
1638 mips16_stub_call_address (mips_one_only_stub *stub)
1640 rtx fn = mips16_stub_function (stub->get_name ());
1641 SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_LOCAL;
1642 if (!call_insn_operand (fn, VOIDmode))
1643 fn = force_reg (Pmode, fn);
1647 /* A stub for moving the thread pointer into TLS_GET_TP_REGNUM. */
1649 class mips16_rdhwr_one_only_stub : public mips_one_only_stub
1651 virtual const char *get_name ();
1652 virtual void output_body ();
1656 mips16_rdhwr_one_only_stub::get_name ()
1658 return "__mips16_rdhwr";
1662 mips16_rdhwr_one_only_stub::output_body ()
1664 fprintf (asm_out_file,
1666 "\t.set\tmips32r2\n"
1667 "\t.set\tnoreorder\n"
1673 /* A stub for moving the FCSR into GET_FCSR_REGNUM. */
1674 class mips16_get_fcsr_one_only_stub : public mips_one_only_stub
1676 virtual const char *get_name ();
1677 virtual void output_body ();
1681 mips16_get_fcsr_one_only_stub::get_name ()
1683 return "__mips16_get_fcsr";
1687 mips16_get_fcsr_one_only_stub::output_body ()
1689 fprintf (asm_out_file,
1691 "\tj\t$31\n", reg_names[GET_FCSR_REGNUM]);
1694 /* A stub for moving SET_FCSR_REGNUM into the FCSR. */
1695 class mips16_set_fcsr_one_only_stub : public mips_one_only_stub
1697 virtual const char *get_name ();
1698 virtual void output_body ();
1702 mips16_set_fcsr_one_only_stub::get_name ()
1704 return "__mips16_set_fcsr";
1708 mips16_set_fcsr_one_only_stub::output_body ()
1710 fprintf (asm_out_file,
1712 "\tj\t$31\n", reg_names[SET_FCSR_REGNUM]);
1715 /* Return true if symbols of type TYPE require a GOT access. */
1718 mips_got_symbol_type_p (enum mips_symbol_type type)
1722 case SYMBOL_GOT_PAGE_OFST:
1723 case SYMBOL_GOT_DISP:
1731 /* Return true if X is a thread-local symbol. */
1734 mips_tls_symbol_p (rtx x)
1736 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1739 /* Return true if SYMBOL_REF X is associated with a global symbol
1740 (in the STB_GLOBAL sense). */
1743 mips_global_symbol_p (const_rtx x)
1745 const_tree decl = SYMBOL_REF_DECL (x);
1748 return !SYMBOL_REF_LOCAL_P (x) || SYMBOL_REF_EXTERNAL_P (x);
1750 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1751 or weak symbols. Relocations in the object file will be against
1752 the target symbol, so it's that symbol's binding that matters here. */
1753 return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl));
1756 /* Return true if function X is a libgcc MIPS16 stub function. */
1759 mips16_stub_function_p (const_rtx x)
1761 return (GET_CODE (x) == SYMBOL_REF
1762 && strncmp (XSTR (x, 0), "__mips16_", 9) == 0);
1765 /* Return true if function X is a locally-defined and locally-binding
1769 mips16_local_function_p (const_rtx x)
1771 return (GET_CODE (x) == SYMBOL_REF
1772 && SYMBOL_REF_LOCAL_P (x)
1773 && !SYMBOL_REF_EXTERNAL_P (x)
1774 && (mips_get_compress_mode (SYMBOL_REF_DECL (x)) & MASK_MIPS16));
1777 /* Return true if SYMBOL_REF X binds locally. */
1780 mips_symbol_binds_local_p (const_rtx x)
1782 return (SYMBOL_REF_DECL (x)
1783 ? targetm.binds_local_p (SYMBOL_REF_DECL (x))
1784 : SYMBOL_REF_LOCAL_P (x));
1787 /* Return true if rtx constants of mode MODE should be put into a small
1791 mips_rtx_constant_in_small_data_p (enum machine_mode mode)
1793 return (!TARGET_EMBEDDED_DATA
1794 && TARGET_LOCAL_SDATA
1795 && GET_MODE_SIZE (mode) <= mips_small_data_threshold);
1798 /* Return true if X should not be moved directly into register $25.
1799 We need this because many versions of GAS will treat "la $25,foo" as
1800 part of a call sequence and so allow a global "foo" to be lazily bound. */
1803 mips_dangerous_for_la25_p (rtx x)
1805 return (!TARGET_EXPLICIT_RELOCS
1807 && GET_CODE (x) == SYMBOL_REF
1808 && mips_global_symbol_p (x));
1811 /* Return true if calls to X might need $25 to be valid on entry. */
1814 mips_use_pic_fn_addr_reg_p (const_rtx x)
1816 if (!TARGET_USE_PIC_FN_ADDR_REG)
1819 /* MIPS16 stub functions are guaranteed not to use $25. */
1820 if (mips16_stub_function_p (x))
1823 if (GET_CODE (x) == SYMBOL_REF)
1825 /* If PLTs and copy relocations are available, the static linker
1826 will make sure that $25 is valid on entry to the target function. */
1827 if (TARGET_ABICALLS_PIC0)
1830 /* Locally-defined functions use absolute accesses to set up
1831 the global pointer. */
1832 if (TARGET_ABSOLUTE_ABICALLS
1833 && mips_symbol_binds_local_p (x)
1834 && !SYMBOL_REF_EXTERNAL_P (x))
1841 /* Return the method that should be used to access SYMBOL_REF or
1842 LABEL_REF X in context CONTEXT. */
1844 static enum mips_symbol_type
1845 mips_classify_symbol (const_rtx x, enum mips_symbol_context context)
1848 return SYMBOL_GOT_DISP;
1850 if (GET_CODE (x) == LABEL_REF)
1852 /* Only return SYMBOL_PC_RELATIVE if we are generating MIPS16
1853 code and if we know that the label is in the current function's
1854 text section. LABEL_REFs are used for jump tables as well as
1855 text labels, so we must check whether jump tables live in the
1857 if (TARGET_MIPS16_SHORT_JUMP_TABLES
1858 && !LABEL_REF_NONLOCAL_P (x))
1859 return SYMBOL_PC_RELATIVE;
1861 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1862 return SYMBOL_GOT_PAGE_OFST;
1864 return SYMBOL_ABSOLUTE;
1867 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1869 if (SYMBOL_REF_TLS_MODEL (x))
1872 if (CONSTANT_POOL_ADDRESS_P (x))
1874 if (TARGET_MIPS16_TEXT_LOADS)
1875 return SYMBOL_PC_RELATIVE;
1877 if (TARGET_MIPS16_PCREL_LOADS && context == SYMBOL_CONTEXT_MEM)
1878 return SYMBOL_PC_RELATIVE;
1880 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x)))
1881 return SYMBOL_GP_RELATIVE;
1884 /* Do not use small-data accesses for weak symbols; they may end up
1886 if (TARGET_GPOPT && SYMBOL_REF_SMALL_P (x) && !SYMBOL_REF_WEAK (x))
1887 return SYMBOL_GP_RELATIVE;
1889 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1891 if (TARGET_ABICALLS_PIC2
1892 && !(TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x)))
1894 /* There are three cases to consider:
1896 - o32 PIC (either with or without explicit relocs)
1897 - n32/n64 PIC without explicit relocs
1898 - n32/n64 PIC with explicit relocs
1900 In the first case, both local and global accesses will use an
1901 R_MIPS_GOT16 relocation. We must correctly predict which of
1902 the two semantics (local or global) the assembler and linker
1903 will apply. The choice depends on the symbol's binding rather
1904 than its visibility.
1906 In the second case, the assembler will not use R_MIPS_GOT16
1907 relocations, but it chooses between local and global accesses
1908 in the same way as for o32 PIC.
1910 In the third case we have more freedom since both forms of
1911 access will work for any kind of symbol. However, there seems
1912 little point in doing things differently. */
1913 if (mips_global_symbol_p (x))
1914 return SYMBOL_GOT_DISP;
1916 return SYMBOL_GOT_PAGE_OFST;
1919 return SYMBOL_ABSOLUTE;
1922 /* Classify the base of symbolic expression X, given that X appears in
1925 static enum mips_symbol_type
1926 mips_classify_symbolic_expression (rtx x, enum mips_symbol_context context)
1930 split_const (x, &x, &offset);
1931 if (UNSPEC_ADDRESS_P (x))
1932 return UNSPEC_ADDRESS_TYPE (x);
1934 return mips_classify_symbol (x, context);
1937 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1938 is the alignment in bytes of SYMBOL_REF X. */
1941 mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset)
1943 HOST_WIDE_INT align;
1945 align = SYMBOL_REF_DECL (x) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x)) : 1;
1946 return IN_RANGE (offset, 0, align - 1);
1949 /* Return true if X is a symbolic constant that can be used in context
1950 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1953 mips_symbolic_constant_p (rtx x, enum mips_symbol_context context,
1954 enum mips_symbol_type *symbol_type)
1958 split_const (x, &x, &offset);
1959 if (UNSPEC_ADDRESS_P (x))
1961 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1962 x = UNSPEC_ADDRESS (x);
1964 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1966 *symbol_type = mips_classify_symbol (x, context);
1967 if (*symbol_type == SYMBOL_TLS)
1973 if (offset == const0_rtx)
1976 /* Check whether a nonzero offset is valid for the underlying
1978 switch (*symbol_type)
1980 case SYMBOL_ABSOLUTE:
1981 case SYMBOL_64_HIGH:
1984 /* If the target has 64-bit pointers and the object file only
1985 supports 32-bit symbols, the values of those symbols will be
1986 sign-extended. In this case we can't allow an arbitrary offset
1987 in case the 32-bit value X + OFFSET has a different sign from X. */
1988 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1989 return offset_within_block_p (x, INTVAL (offset));
1991 /* In other cases the relocations can handle any offset. */
1994 case SYMBOL_PC_RELATIVE:
1995 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1996 In this case, we no longer have access to the underlying constant,
1997 but the original symbol-based access was known to be valid. */
1998 if (GET_CODE (x) == LABEL_REF)
2003 case SYMBOL_GP_RELATIVE:
2004 /* Make sure that the offset refers to something within the
2005 same object block. This should guarantee that the final
2006 PC- or GP-relative offset is within the 16-bit limit. */
2007 return offset_within_block_p (x, INTVAL (offset));
2009 case SYMBOL_GOT_PAGE_OFST:
2010 case SYMBOL_GOTOFF_PAGE:
2011 /* If the symbol is global, the GOT entry will contain the symbol's
2012 address, and we will apply a 16-bit offset after loading it.
2013 If the symbol is local, the linker should provide enough local
2014 GOT entries for a 16-bit offset, but larger offsets may lead
2016 return SMALL_INT (offset);
2020 /* There is no carry between the HI and LO REL relocations, so the
2021 offset is only valid if we know it won't lead to such a carry. */
2022 return mips_offset_within_alignment_p (x, INTVAL (offset));
2024 case SYMBOL_GOT_DISP:
2025 case SYMBOL_GOTOFF_DISP:
2026 case SYMBOL_GOTOFF_CALL:
2027 case SYMBOL_GOTOFF_LOADGP:
2030 case SYMBOL_GOTTPREL:
2038 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
2039 single instruction. We rely on the fact that, in the worst case,
2040 all instructions involved in a MIPS16 address calculation are usually
2044 mips_symbol_insns_1 (enum mips_symbol_type type, enum machine_mode mode)
2046 if (mips_use_pcrel_pool_p[(int) type])
2048 if (mode == MAX_MACHINE_MODE)
2049 /* LEAs will be converted into constant-pool references by
2051 type = SYMBOL_PC_RELATIVE;
2053 /* The constant must be loaded and then dereferenced. */
2059 case SYMBOL_ABSOLUTE:
2060 /* When using 64-bit symbols, we need 5 preparatory instructions,
2063 lui $at,%highest(symbol)
2064 daddiu $at,$at,%higher(symbol)
2066 daddiu $at,$at,%hi(symbol)
2069 The final address is then $at + %lo(symbol). With 32-bit
2070 symbols we just need a preparatory LUI for normal mode and
2071 a preparatory LI and SLL for MIPS16. */
2072 return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2;
2074 case SYMBOL_GP_RELATIVE:
2075 /* Treat GP-relative accesses as taking a single instruction on
2076 MIPS16 too; the copy of $gp can often be shared. */
2079 case SYMBOL_PC_RELATIVE:
2080 /* PC-relative constants can be only be used with ADDIUPC,
2081 DADDIUPC, LWPC and LDPC. */
2082 if (mode == MAX_MACHINE_MODE
2083 || GET_MODE_SIZE (mode) == 4
2084 || GET_MODE_SIZE (mode) == 8)
2087 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
2090 case SYMBOL_GOT_DISP:
2091 /* The constant will have to be loaded from the GOT before it
2092 is used in an address. */
2093 if (mode != MAX_MACHINE_MODE)
2098 case SYMBOL_GOT_PAGE_OFST:
2099 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
2100 local/global classification is accurate. The worst cases are:
2102 (1) For local symbols when generating o32 or o64 code. The assembler
2108 ...and the final address will be $at + %lo(symbol).
2110 (2) For global symbols when -mxgot. The assembler will use:
2112 lui $at,%got_hi(symbol)
2115 ...and the final address will be $at + %got_lo(symbol). */
2118 case SYMBOL_GOTOFF_PAGE:
2119 case SYMBOL_GOTOFF_DISP:
2120 case SYMBOL_GOTOFF_CALL:
2121 case SYMBOL_GOTOFF_LOADGP:
2122 case SYMBOL_64_HIGH:
2128 case SYMBOL_GOTTPREL:
2131 /* A 16-bit constant formed by a single relocation, or a 32-bit
2132 constant formed from a high 16-bit relocation and a low 16-bit
2133 relocation. Use mips_split_p to determine which. 32-bit
2134 constants need an "lui; addiu" sequence for normal mode and
2135 an "li; sll; addiu" sequence for MIPS16 mode. */
2136 return !mips_split_p[type] ? 1 : TARGET_MIPS16 ? 3 : 2;
2139 /* We don't treat a bare TLS symbol as a constant. */
2145 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
2146 to load symbols of type TYPE into a register. Return 0 if the given
2147 type of symbol cannot be used as an immediate operand.
2149 Otherwise, return the number of instructions needed to load or store
2150 values of mode MODE to or from addresses of type TYPE. Return 0 if
2151 the given type of symbol is not valid in addresses.
2153 In both cases, instruction counts are based off BASE_INSN_LENGTH. */
2156 mips_symbol_insns (enum mips_symbol_type type, enum machine_mode mode)
2158 return mips_symbol_insns_1 (type, mode) * (TARGET_MIPS16 ? 2 : 1);
2161 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
2164 mips_cannot_force_const_mem (enum machine_mode mode, rtx x)
2166 enum mips_symbol_type type;
2169 /* There is no assembler syntax for expressing an address-sized
2171 if (GET_CODE (x) == HIGH)
2174 /* As an optimization, reject constants that mips_legitimize_move
2177 Suppose we have a multi-instruction sequence that loads constant C
2178 into register R. If R does not get allocated a hard register, and
2179 R is used in an operand that allows both registers and memory
2180 references, reload will consider forcing C into memory and using
2181 one of the instruction's memory alternatives. Returning false
2182 here will force it to use an input reload instead. */
2183 if (CONST_INT_P (x) && mips_legitimate_constant_p (mode, x))
2186 split_const (x, &base, &offset);
2187 if (mips_symbolic_constant_p (base, SYMBOL_CONTEXT_LEA, &type))
2189 /* See whether we explicitly want these symbols in the pool. */
2190 if (mips_use_pcrel_pool_p[(int) type])
2193 /* The same optimization as for CONST_INT. */
2194 if (SMALL_INT (offset) && mips_symbol_insns (type, MAX_MACHINE_MODE) > 0)
2197 /* If MIPS16 constant pools live in the text section, they should
2198 not refer to anything that might need run-time relocation. */
2199 if (TARGET_MIPS16_PCREL_LOADS && mips_got_symbol_type_p (type))
2203 /* TLS symbols must be computed by mips_legitimize_move. */
2204 if (tls_referenced_p (x))
2210 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
2211 constants when we're using a per-function constant pool. */
2214 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
2215 const_rtx x ATTRIBUTE_UNUSED)
2217 return !TARGET_MIPS16_PCREL_LOADS;
2220 /* Return true if register REGNO is a valid base register for mode MODE.
2221 STRICT_P is true if REG_OK_STRICT is in effect. */
2224 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode,
2227 if (!HARD_REGISTER_NUM_P (regno))
2231 regno = reg_renumber[regno];
2234 /* These fake registers will be eliminated to either the stack or
2235 hard frame pointer, both of which are usually valid base registers.
2236 Reload deals with the cases where the eliminated form isn't valid. */
2237 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
2240 /* In MIPS16 mode, the stack pointer can only address word and doubleword
2241 values, nothing smaller. */
2242 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
2243 return GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
2245 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
2248 /* Return true if X is a valid base register for mode MODE.
2249 STRICT_P is true if REG_OK_STRICT is in effect. */
2252 mips_valid_base_register_p (rtx x, enum machine_mode mode, bool strict_p)
2254 if (!strict_p && GET_CODE (x) == SUBREG)
2258 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p));
2261 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2262 can address a value of mode MODE. */
2265 mips_valid_offset_p (rtx x, enum machine_mode mode)
2267 /* Check that X is a signed 16-bit number. */
2268 if (!const_arith_operand (x, Pmode))
2271 /* We may need to split multiword moves, so make sure that every word
2273 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2274 && !SMALL_OPERAND (INTVAL (x) + GET_MODE_SIZE (mode) - UNITS_PER_WORD))
2280 /* Return true if a LO_SUM can address a value of mode MODE when the
2281 LO_SUM symbol has type SYMBOL_TYPE. */
2284 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type, enum machine_mode mode)
2286 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2288 if (mips_symbol_insns (symbol_type, mode) == 0)
2291 /* Check that there is a known low-part relocation. */
2292 if (mips_lo_relocs[symbol_type] == NULL)
2295 /* We may need to split multiword moves, so make sure that each word
2296 can be accessed without inducing a carry. This is mainly needed
2297 for o64, which has historically only guaranteed 64-bit alignment
2298 for 128-bit types. */
2299 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2300 && GET_MODE_BITSIZE (mode) > GET_MODE_ALIGNMENT (mode))
2306 /* Return true if X is a valid address for machine mode MODE. If it is,
2307 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2311 mips_classify_address (struct mips_address_info *info, rtx x,
2312 enum machine_mode mode, bool strict_p)
2314 switch (GET_CODE (x))
2318 info->type = ADDRESS_REG;
2320 info->offset = const0_rtx;
2321 return mips_valid_base_register_p (info->reg, mode, strict_p);
2324 info->type = ADDRESS_REG;
2325 info->reg = XEXP (x, 0);
2326 info->offset = XEXP (x, 1);
2327 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2328 && mips_valid_offset_p (info->offset, mode));
2331 info->type = ADDRESS_LO_SUM;
2332 info->reg = XEXP (x, 0);
2333 info->offset = XEXP (x, 1);
2334 /* We have to trust the creator of the LO_SUM to do something vaguely
2335 sane. Target-independent code that creates a LO_SUM should also
2336 create and verify the matching HIGH. Target-independent code that
2337 adds an offset to a LO_SUM must prove that the offset will not
2338 induce a carry. Failure to do either of these things would be
2339 a bug, and we are not required to check for it here. The MIPS
2340 backend itself should only create LO_SUMs for valid symbolic
2341 constants, with the high part being either a HIGH or a copy
2344 = mips_classify_symbolic_expression (info->offset, SYMBOL_CONTEXT_MEM);
2345 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2346 && mips_valid_lo_sum_p (info->symbol_type, mode));
2349 /* Small-integer addresses don't occur very often, but they
2350 are legitimate if $0 is a valid base register. */
2351 info->type = ADDRESS_CONST_INT;
2352 return !TARGET_MIPS16 && SMALL_INT (x);
2357 info->type = ADDRESS_SYMBOLIC;
2358 return (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_MEM,
2360 && mips_symbol_insns (info->symbol_type, mode) > 0
2361 && !mips_split_p[info->symbol_type]);
2368 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2371 mips_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
2373 struct mips_address_info addr;
2375 return mips_classify_address (&addr, x, mode, strict_p);
2378 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
2381 mips_stack_address_p (rtx x, enum machine_mode mode)
2383 struct mips_address_info addr;
2385 return (mips_classify_address (&addr, x, mode, false)
2386 && addr.type == ADDRESS_REG
2387 && addr.reg == stack_pointer_rtx);
2390 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2391 address instruction. Note that such addresses are not considered
2392 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2393 is so restricted. */
2396 mips_lwxs_address_p (rtx addr)
2399 && GET_CODE (addr) == PLUS
2400 && REG_P (XEXP (addr, 1)))
2402 rtx offset = XEXP (addr, 0);
2403 if (GET_CODE (offset) == MULT
2404 && REG_P (XEXP (offset, 0))
2405 && CONST_INT_P (XEXP (offset, 1))
2406 && INTVAL (XEXP (offset, 1)) == 4)
2412 /* Return true if ADDR matches the pattern for the L{B,H,W,D}{,U}X load
2413 indexed address instruction. Note that such addresses are
2414 not considered legitimate in the TARGET_LEGITIMATE_ADDRESS_P
2415 sense, because their use is so restricted. */
2418 mips_lx_address_p (rtx addr, enum machine_mode mode)
2420 if (GET_CODE (addr) != PLUS
2421 || !REG_P (XEXP (addr, 0))
2422 || !REG_P (XEXP (addr, 1)))
2424 if (ISA_HAS_LBX && mode == QImode)
2426 if (ISA_HAS_LHX && mode == HImode)
2428 if (ISA_HAS_LWX && mode == SImode)
2430 if (ISA_HAS_LDX && mode == DImode)
2435 /* Return true if a value at OFFSET bytes from base register BASE can be
2436 accessed using an unextended MIPS16 instruction. MODE is the mode of
2439 Usually the offset in an unextended instruction is a 5-bit field.
2440 The offset is unsigned and shifted left once for LH and SH, twice
2441 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2442 an 8-bit immediate field that's shifted left twice. */
2445 mips16_unextended_reference_p (enum machine_mode mode, rtx base,
2446 unsigned HOST_WIDE_INT offset)
2448 if (mode != BLKmode && offset % GET_MODE_SIZE (mode) == 0)
2450 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
2451 return offset < 256U * GET_MODE_SIZE (mode);
2452 return offset < 32U * GET_MODE_SIZE (mode);
2457 /* Return the number of instructions needed to load or store a value
2458 of mode MODE at address X, assuming that BASE_INSN_LENGTH is the
2459 length of one instruction. Return 0 if X isn't valid for MODE.
2460 Assume that multiword moves may need to be split into word moves
2461 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2465 mips_address_insns (rtx x, enum machine_mode mode, bool might_split_p)
2467 struct mips_address_info addr;
2470 /* BLKmode is used for single unaligned loads and stores and should
2471 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2472 meaningless, so we have to single it out as a special case one way
2474 if (mode != BLKmode && might_split_p)
2475 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2479 if (mips_classify_address (&addr, x, mode, false))
2484 && !mips16_unextended_reference_p (mode, addr.reg,
2485 UINTVAL (addr.offset)))
2489 case ADDRESS_LO_SUM:
2490 return TARGET_MIPS16 ? factor * 2 : factor;
2492 case ADDRESS_CONST_INT:
2495 case ADDRESS_SYMBOLIC:
2496 return factor * mips_symbol_insns (addr.symbol_type, mode);
2501 /* Return true if X fits within an unsigned field of BITS bits that is
2502 shifted left SHIFT bits before being used. */
2505 mips_unsigned_immediate_p (unsigned HOST_WIDE_INT x, int bits, int shift = 0)
2507 return (x & ((1 << shift) - 1)) == 0 && x < ((unsigned) 1 << (shift + bits));
2510 /* Return true if X fits within a signed field of BITS bits that is
2511 shifted left SHIFT bits before being used. */
2514 mips_signed_immediate_p (unsigned HOST_WIDE_INT x, int bits, int shift = 0)
2516 x += 1 << (bits + shift - 1);
2517 return mips_unsigned_immediate_p (x, bits, shift);
2520 /* Return true if X is legitimate for accessing values of mode MODE,
2521 if it is based on a MIPS16 register, and if the offset satisfies
2522 OFFSET_PREDICATE. */
2525 m16_based_address_p (rtx x, enum machine_mode mode,
2526 insn_operand_predicate_fn offset_predicate)
2528 struct mips_address_info addr;
2530 return (mips_classify_address (&addr, x, mode, false)
2531 && addr.type == ADDRESS_REG
2532 && M16_REG_P (REGNO (addr.reg))
2533 && offset_predicate (addr.offset, mode));
2536 /* Return true if X is a legitimate address that conforms to the requirements
2537 for a microMIPS LWSP or SWSP insn. */
2540 lwsp_swsp_address_p (rtx x, enum machine_mode mode)
2542 struct mips_address_info addr;
2544 return (mips_classify_address (&addr, x, mode, false)
2545 && addr.type == ADDRESS_REG
2546 && REGNO (addr.reg) == STACK_POINTER_REGNUM
2547 && uw5_operand (addr.offset, mode));
2550 /* Return true if X is a legitimate address with a 12-bit offset.
2551 MODE is the mode of the value being accessed. */
2554 umips_12bit_offset_address_p (rtx x, enum machine_mode mode)
2556 struct mips_address_info addr;
2558 return (mips_classify_address (&addr, x, mode, false)
2559 && addr.type == ADDRESS_REG
2560 && CONST_INT_P (addr.offset)
2561 && UMIPS_12BIT_OFFSET_P (INTVAL (addr.offset)));
2564 /* Return the number of instructions needed to load constant X,
2565 assuming that BASE_INSN_LENGTH is the length of one instruction.
2566 Return 0 if X isn't a valid constant. */
2569 mips_const_insns (rtx x)
2571 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2572 enum mips_symbol_type symbol_type;
2575 switch (GET_CODE (x))
2578 if (!mips_symbolic_constant_p (XEXP (x, 0), SYMBOL_CONTEXT_LEA,
2580 || !mips_split_p[symbol_type])
2583 /* This is simply an LUI for normal mode. It is an extended
2584 LI followed by an extended SLL for MIPS16. */
2585 return TARGET_MIPS16 ? 4 : 1;
2589 /* Unsigned 8-bit constants can be loaded using an unextended
2590 LI instruction. Unsigned 16-bit constants can be loaded
2591 using an extended LI. Negative constants must be loaded
2592 using LI and then negated. */
2593 return (IN_RANGE (INTVAL (x), 0, 255) ? 1
2594 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
2595 : IN_RANGE (-INTVAL (x), 0, 255) ? 2
2596 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
2599 return mips_build_integer (codes, INTVAL (x));
2603 /* Allow zeros for normal mode, where we can use $0. */
2604 return !TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0;
2610 /* See if we can refer to X directly. */
2611 if (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_LEA, &symbol_type))
2612 return mips_symbol_insns (symbol_type, MAX_MACHINE_MODE);
2614 /* Otherwise try splitting the constant into a base and offset.
2615 If the offset is a 16-bit value, we can load the base address
2616 into a register and then use (D)ADDIU to add in the offset.
2617 If the offset is larger, we can load the base and offset
2618 into separate registers and add them together with (D)ADDU.
2619 However, the latter is only possible before reload; during
2620 and after reload, we must have the option of forcing the
2621 constant into the pool instead. */
2622 split_const (x, &x, &offset);
2625 int n = mips_const_insns (x);
2628 if (SMALL_INT (offset))
2630 else if (!targetm.cannot_force_const_mem (GET_MODE (x), x))
2631 return n + 1 + mips_build_integer (codes, INTVAL (offset));
2638 return mips_symbol_insns (mips_classify_symbol (x, SYMBOL_CONTEXT_LEA),
2646 /* X is a doubleword constant that can be handled by splitting it into
2647 two words and loading each word separately. Return the number of
2648 instructions required to do this, assuming that BASE_INSN_LENGTH
2649 is the length of one instruction. */
2652 mips_split_const_insns (rtx x)
2654 unsigned int low, high;
2656 low = mips_const_insns (mips_subword (x, false));
2657 high = mips_const_insns (mips_subword (x, true));
2658 gcc_assert (low > 0 && high > 0);
2662 /* Return the number of instructions needed to implement INSN,
2663 given that it loads from or stores to MEM. Assume that
2664 BASE_INSN_LENGTH is the length of one instruction. */
2667 mips_load_store_insns (rtx mem, rtx_insn *insn)
2669 enum machine_mode mode;
2673 gcc_assert (MEM_P (mem));
2674 mode = GET_MODE (mem);
2676 /* Try to prove that INSN does not need to be split. */
2677 might_split_p = GET_MODE_SIZE (mode) > UNITS_PER_WORD;
2680 set = single_set (insn);
2681 if (set && !mips_split_move_insn_p (SET_DEST (set), SET_SRC (set), insn))
2682 might_split_p = false;
2685 return mips_address_insns (XEXP (mem, 0), mode, might_split_p);
2688 /* Return the number of instructions needed for an integer division,
2689 assuming that BASE_INSN_LENGTH is the length of one instruction. */
2692 mips_idiv_insns (void)
2697 if (TARGET_CHECK_ZERO_DIV)
2699 if (GENERATE_DIVIDE_TRAPS)
2705 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
2710 /* Emit a move from SRC to DEST. Assume that the move expanders can
2711 handle all moves if !can_create_pseudo_p (). The distinction is
2712 important because, unlike emit_move_insn, the move expanders know
2713 how to force Pmode objects into the constant pool even when the
2714 constant pool address is not itself legitimate. */
2717 mips_emit_move (rtx dest, rtx src)
2719 return (can_create_pseudo_p ()
2720 ? emit_move_insn (dest, src)
2721 : emit_move_insn_1 (dest, src));
2724 /* Emit a move from SRC to DEST, splitting compound moves into individual
2725 instructions. SPLIT_TYPE is the type of split to perform. */
2728 mips_emit_move_or_split (rtx dest, rtx src, enum mips_split_type split_type)
2730 if (mips_split_move_p (dest, src, split_type))
2731 mips_split_move (dest, src, split_type);
2733 mips_emit_move (dest, src);
2736 /* Emit an instruction of the form (set TARGET (CODE OP0)). */
2739 mips_emit_unary (enum rtx_code code, rtx target, rtx op0)
2741 emit_insn (gen_rtx_SET (VOIDmode, target,
2742 gen_rtx_fmt_e (code, GET_MODE (op0), op0)));
2745 /* Compute (CODE OP0) and store the result in a new register of mode MODE.
2746 Return that new register. */
2749 mips_force_unary (enum machine_mode mode, enum rtx_code code, rtx op0)
2753 reg = gen_reg_rtx (mode);
2754 mips_emit_unary (code, reg, op0);
2758 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2761 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
2763 emit_insn (gen_rtx_SET (VOIDmode, target,
2764 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
2767 /* Compute (CODE OP0 OP1) and store the result in a new register
2768 of mode MODE. Return that new register. */
2771 mips_force_binary (enum machine_mode mode, enum rtx_code code, rtx op0, rtx op1)
2775 reg = gen_reg_rtx (mode);
2776 mips_emit_binary (code, reg, op0, op1);
2780 /* Copy VALUE to a register and return that register. If new pseudos
2781 are allowed, copy it into a new register, otherwise use DEST. */
2784 mips_force_temporary (rtx dest, rtx value)
2786 if (can_create_pseudo_p ())
2787 return force_reg (Pmode, value);
2790 mips_emit_move (dest, value);
2795 /* Emit a call sequence with call pattern PATTERN and return the call
2796 instruction itself (which is not necessarily the last instruction
2797 emitted). ORIG_ADDR is the original, unlegitimized address,
2798 ADDR is the legitimized form, and LAZY_P is true if the call
2799 address is lazily-bound. */
2802 mips_emit_call_insn (rtx pattern, rtx orig_addr, rtx addr, bool lazy_p)
2807 insn = emit_call_insn (pattern);
2809 if (TARGET_MIPS16 && mips_use_pic_fn_addr_reg_p (orig_addr))
2811 /* MIPS16 JALRs only take MIPS16 registers. If the target
2812 function requires $25 to be valid on entry, we must copy it
2813 there separately. The move instruction can be put in the
2814 call's delay slot. */
2815 reg = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
2816 emit_insn_before (gen_move_insn (reg, addr), insn);
2817 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
2821 /* Lazy-binding stubs require $gp to be valid on entry. */
2822 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
2826 /* See the comment above load_call<mode> for details. */
2827 use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
2828 gen_rtx_REG (Pmode, GOT_VERSION_REGNUM));
2829 emit_insn (gen_update_got_version ());
2833 && TARGET_EXPLICIT_RELOCS
2834 && TARGET_CALL_CLOBBERED_GP)
2836 rtx post_call_tmp_reg = gen_rtx_REG (word_mode, POST_CALL_TMP_REG);
2837 clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), post_call_tmp_reg);
2843 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2844 then add CONST_INT OFFSET to the result. */
2847 mips_unspec_address_offset (rtx base, rtx offset,
2848 enum mips_symbol_type symbol_type)
2850 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
2851 UNSPEC_ADDRESS_FIRST + symbol_type);
2852 if (offset != const0_rtx)
2853 base = gen_rtx_PLUS (Pmode, base, offset);
2854 return gen_rtx_CONST (Pmode, base);
2857 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2858 type SYMBOL_TYPE. */
2861 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
2865 split_const (address, &base, &offset);
2866 return mips_unspec_address_offset (base, offset, symbol_type);
2869 /* If OP is an UNSPEC address, return the address to which it refers,
2870 otherwise return OP itself. */
2873 mips_strip_unspec_address (rtx op)
2877 split_const (op, &base, &offset);
2878 if (UNSPEC_ADDRESS_P (base))
2879 op = plus_constant (Pmode, UNSPEC_ADDRESS (base), INTVAL (offset));
2883 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2884 high part to BASE and return the result. Just return BASE otherwise.
2885 TEMP is as for mips_force_temporary.
2887 The returned expression can be used as the first operand to a LO_SUM. */
2890 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
2891 enum mips_symbol_type symbol_type)
2893 if (mips_split_p[symbol_type])
2895 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
2896 addr = mips_force_temporary (temp, addr);
2897 base = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
2902 /* Return an instruction that copies $gp into register REG. We want
2903 GCC to treat the register's value as constant, so that its value
2904 can be rematerialized on demand. */
2907 gen_load_const_gp (rtx reg)
2909 return PMODE_INSN (gen_load_const_gp, (reg));
2912 /* Return a pseudo register that contains the value of $gp throughout
2913 the current function. Such registers are needed by MIPS16 functions,
2914 for which $gp itself is not a valid base register or addition operand. */
2917 mips16_gp_pseudo_reg (void)
2919 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
2923 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
2925 push_topmost_sequence ();
2927 scan = get_insns ();
2928 while (NEXT_INSN (scan) && !INSN_P (NEXT_INSN (scan)))
2929 scan = NEXT_INSN (scan);
2931 rtx set = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
2932 rtx_insn *insn = emit_insn_after (set, scan);
2933 INSN_LOCATION (insn) = 0;
2935 pop_topmost_sequence ();
2938 return cfun->machine->mips16_gp_pseudo_rtx;
2941 /* Return a base register that holds pic_offset_table_rtx.
2942 TEMP, if nonnull, is a scratch Pmode base register. */
2945 mips_pic_base_register (rtx temp)
2948 return pic_offset_table_rtx;
2950 if (currently_expanding_to_rtl)
2951 return mips16_gp_pseudo_reg ();
2953 if (can_create_pseudo_p ())
2954 temp = gen_reg_rtx (Pmode);
2957 /* The first post-reload split exposes all references to $gp
2958 (both uses and definitions). All references must remain
2959 explicit after that point.
2961 It is safe to introduce uses of $gp at any time, so for
2962 simplicity, we do that before the split too. */
2963 mips_emit_move (temp, pic_offset_table_rtx);
2965 emit_insn (gen_load_const_gp (temp));
2969 /* Return the RHS of a load_call<mode> insn. */
2972 mips_unspec_call (rtx reg, rtx symbol)
2976 vec = gen_rtvec (3, reg, symbol, gen_rtx_REG (SImode, GOT_VERSION_REGNUM));
2977 return gen_rtx_UNSPEC (Pmode, vec, UNSPEC_LOAD_CALL);
2980 /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol
2981 reference. Return NULL_RTX otherwise. */
2984 mips_strip_unspec_call (rtx src)
2986 if (GET_CODE (src) == UNSPEC && XINT (src, 1) == UNSPEC_LOAD_CALL)
2987 return mips_strip_unspec_address (XVECEXP (src, 0, 1));
2991 /* Create and return a GOT reference of type TYPE for address ADDR.
2992 TEMP, if nonnull, is a scratch Pmode base register. */
2995 mips_got_load (rtx temp, rtx addr, enum mips_symbol_type type)
2997 rtx base, high, lo_sum_symbol;
2999 base = mips_pic_base_register (temp);
3001 /* If we used the temporary register to load $gp, we can't use
3002 it for the high part as well. */
3003 if (temp != NULL && reg_overlap_mentioned_p (base, temp))
3006 high = mips_unspec_offset_high (temp, base, addr, type);
3007 lo_sum_symbol = mips_unspec_address (addr, type);
3009 if (type == SYMBOL_GOTOFF_CALL)
3010 return mips_unspec_call (high, lo_sum_symbol);
3012 return PMODE_INSN (gen_unspec_got, (high, lo_sum_symbol));
3015 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
3016 it appears in a MEM of that mode. Return true if ADDR is a legitimate
3017 constant in that context and can be split into high and low parts.
3018 If so, and if LOW_OUT is nonnull, emit the high part and store the
3019 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
3021 TEMP is as for mips_force_temporary and is used to load the high
3022 part into a register.
3024 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
3025 a legitimize SET_SRC for an .md pattern, otherwise the low part
3026 is guaranteed to be a legitimate address for mode MODE. */
3029 mips_split_symbol (rtx temp, rtx addr, enum machine_mode mode, rtx *low_out)
3031 enum mips_symbol_context context;
3032 enum mips_symbol_type symbol_type;
3035 context = (mode == MAX_MACHINE_MODE
3036 ? SYMBOL_CONTEXT_LEA
3037 : SYMBOL_CONTEXT_MEM);
3038 if (GET_CODE (addr) == HIGH && context == SYMBOL_CONTEXT_LEA)
3040 addr = XEXP (addr, 0);
3041 if (mips_symbolic_constant_p (addr, context, &symbol_type)
3042 && mips_symbol_insns (symbol_type, mode) > 0
3043 && mips_split_hi_p[symbol_type])
3046 switch (symbol_type)
3048 case SYMBOL_GOT_PAGE_OFST:
3049 /* The high part of a page/ofst pair is loaded from the GOT. */
3050 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_PAGE);
3061 if (mips_symbolic_constant_p (addr, context, &symbol_type)
3062 && mips_symbol_insns (symbol_type, mode) > 0
3063 && mips_split_p[symbol_type])
3066 switch (symbol_type)
3068 case SYMBOL_GOT_DISP:
3069 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
3070 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_DISP);
3073 case SYMBOL_GP_RELATIVE:
3074 high = mips_pic_base_register (temp);
3075 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
3079 high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
3080 high = mips_force_temporary (temp, high);
3081 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
3090 /* Return a legitimate address for REG + OFFSET. TEMP is as for
3091 mips_force_temporary; it is only needed when OFFSET is not a
3095 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
3097 if (!SMALL_OPERAND (offset))
3103 /* Load the full offset into a register so that we can use
3104 an unextended instruction for the address itself. */
3105 high = GEN_INT (offset);
3110 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
3111 The addition inside the macro CONST_HIGH_PART may cause an
3112 overflow, so we need to force a sign-extension check. */
3113 high = gen_int_mode (CONST_HIGH_PART (offset), Pmode);
3114 offset = CONST_LOW_PART (offset);
3116 high = mips_force_temporary (temp, high);
3117 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
3119 return plus_constant (Pmode, reg, offset);
3122 /* The __tls_get_attr symbol. */
3123 static GTY(()) rtx mips_tls_symbol;
3125 /* Return an instruction sequence that calls __tls_get_addr. SYM is
3126 the TLS symbol we are referencing and TYPE is the symbol type to use
3127 (either global dynamic or local dynamic). V0 is an RTX for the
3128 return value location. */
3131 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
3135 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
3137 if (!mips_tls_symbol)
3138 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
3140 loc = mips_unspec_address (sym, type);
3144 emit_insn (gen_rtx_SET (Pmode, a0,
3145 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
3146 insn = mips_expand_call (MIPS_CALL_NORMAL, v0, mips_tls_symbol,
3147 const0_rtx, NULL_RTX, false);
3148 RTL_CONST_CALL_P (insn) = 1;
3149 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
3150 insn = get_insns ();
3157 /* Return a pseudo register that contains the current thread pointer. */
3160 mips_expand_thread_pointer (rtx tp)
3166 if (!mips16_rdhwr_stub)
3167 mips16_rdhwr_stub = new mips16_rdhwr_one_only_stub ();
3168 fn = mips16_stub_call_address (mips16_rdhwr_stub);
3169 emit_insn (PMODE_INSN (gen_tls_get_tp_mips16, (tp, fn)));
3172 emit_insn (PMODE_INSN (gen_tls_get_tp, (tp)));
3179 return mips_expand_thread_pointer (gen_reg_rtx (Pmode));
3182 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
3183 its address. The return value will be both a valid address and a valid
3184 SET_SRC (either a REG or a LO_SUM). */
3187 mips_legitimize_tls_address (rtx loc)
3189 rtx dest, insn, v0, tp, tmp1, tmp2, eqv, offset;
3190 enum tls_model model;
3192 model = SYMBOL_REF_TLS_MODEL (loc);
3193 /* Only TARGET_ABICALLS code can have more than one module; other
3194 code must be be static and should not use a GOT. All TLS models
3195 reduce to local exec in this situation. */
3196 if (!TARGET_ABICALLS)
3197 model = TLS_MODEL_LOCAL_EXEC;
3201 case TLS_MODEL_GLOBAL_DYNAMIC:
3202 v0 = gen_rtx_REG (Pmode, GP_RETURN);
3203 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
3204 dest = gen_reg_rtx (Pmode);
3205 emit_libcall_block (insn, dest, v0, loc);
3208 case TLS_MODEL_LOCAL_DYNAMIC:
3209 v0 = gen_rtx_REG (Pmode, GP_RETURN);
3210 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
3211 tmp1 = gen_reg_rtx (Pmode);
3213 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
3214 share the LDM result with other LD model accesses. */
3215 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3217 emit_libcall_block (insn, tmp1, v0, eqv);
3219 offset = mips_unspec_address (loc, SYMBOL_DTPREL);
3220 if (mips_split_p[SYMBOL_DTPREL])
3222 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
3223 dest = gen_rtx_LO_SUM (Pmode, tmp2, offset);
3226 dest = expand_binop (Pmode, add_optab, tmp1, offset,
3227 0, 0, OPTAB_DIRECT);
3230 case TLS_MODEL_INITIAL_EXEC:
3231 tp = mips_get_tp ();
3232 tmp1 = gen_reg_rtx (Pmode);
3233 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
3234 if (Pmode == DImode)
3235 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
3237 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
3238 dest = gen_reg_rtx (Pmode);
3239 emit_insn (gen_add3_insn (dest, tmp1, tp));
3242 case TLS_MODEL_LOCAL_EXEC:
3243 tmp1 = mips_get_tp ();
3244 offset = mips_unspec_address (loc, SYMBOL_TPREL);
3245 if (mips_split_p[SYMBOL_TPREL])
3247 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_TPREL);
3248 dest = gen_rtx_LO_SUM (Pmode, tmp2, offset);
3251 dest = expand_binop (Pmode, add_optab, tmp1, offset,
3252 0, 0, OPTAB_DIRECT);
3261 /* Implement "TARGET = __builtin_mips_get_fcsr ()" for MIPS16,
3265 mips16_expand_get_fcsr (rtx target)
3267 if (!mips16_get_fcsr_stub)
3268 mips16_get_fcsr_stub = new mips16_get_fcsr_one_only_stub ();
3269 rtx fn = mips16_stub_call_address (mips16_get_fcsr_stub);
3270 emit_insn (PMODE_INSN (gen_mips_get_fcsr_mips16, (fn)));
3271 emit_move_insn (target, gen_rtx_REG (SImode, GET_FCSR_REGNUM));
3274 /* Implement __builtin_mips_set_fcsr (TARGET) for MIPS16, using a stub. */
3277 mips16_expand_set_fcsr (rtx newval)
3279 if (!mips16_set_fcsr_stub)
3280 mips16_set_fcsr_stub = new mips16_set_fcsr_one_only_stub ();
3281 rtx fn = mips16_stub_call_address (mips16_set_fcsr_stub);
3282 emit_move_insn (gen_rtx_REG (SImode, SET_FCSR_REGNUM), newval);
3283 emit_insn (PMODE_INSN (gen_mips_set_fcsr_mips16, (fn)));
3286 /* If X is not a valid address for mode MODE, force it into a register. */
3289 mips_force_address (rtx x, enum machine_mode mode)
3291 if (!mips_legitimate_address_p (mode, x, false))
3292 x = force_reg (Pmode, x);
3296 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
3297 be legitimized in a way that the generic machinery might not expect,
3298 return a new address, otherwise return NULL. MODE is the mode of
3299 the memory being accessed. */
3302 mips_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3303 enum machine_mode mode)
3306 HOST_WIDE_INT offset;
3308 if (mips_tls_symbol_p (x))
3309 return mips_legitimize_tls_address (x);
3311 /* See if the address can split into a high part and a LO_SUM. */
3312 if (mips_split_symbol (NULL, x, mode, &addr))
3313 return mips_force_address (addr, mode);
3315 /* Handle BASE + OFFSET using mips_add_offset. */
3316 mips_split_plus (x, &base, &offset);
3319 if (!mips_valid_base_register_p (base, mode, false))
3320 base = copy_to_mode_reg (Pmode, base);
3321 addr = mips_add_offset (NULL, base, offset);
3322 return mips_force_address (addr, mode);
3328 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
3331 mips_move_integer (rtx temp, rtx dest, unsigned HOST_WIDE_INT value)
3333 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
3334 enum machine_mode mode;
3335 unsigned int i, num_ops;
3338 mode = GET_MODE (dest);
3339 num_ops = mips_build_integer (codes, value);
3341 /* Apply each binary operation to X. Invariant: X is a legitimate
3342 source operand for a SET pattern. */
3343 x = GEN_INT (codes[0].value);
3344 for (i = 1; i < num_ops; i++)
3346 if (!can_create_pseudo_p ())
3348 emit_insn (gen_rtx_SET (VOIDmode, temp, x));
3352 x = force_reg (mode, x);
3353 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
3356 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
3359 /* Subroutine of mips_legitimize_move. Move constant SRC into register
3360 DEST given that SRC satisfies immediate_operand but doesn't satisfy
3364 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
3368 /* Split moves of big integers into smaller pieces. */
3369 if (splittable_const_int_operand (src, mode))
3371 mips_move_integer (dest, dest, INTVAL (src));
3375 /* Split moves of symbolic constants into high/low pairs. */
3376 if (mips_split_symbol (dest, src, MAX_MACHINE_MODE, &src))
3378 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
3382 /* Generate the appropriate access sequences for TLS symbols. */
3383 if (mips_tls_symbol_p (src))
3385 mips_emit_move (dest, mips_legitimize_tls_address (src));
3389 /* If we have (const (plus symbol offset)), and that expression cannot
3390 be forced into memory, load the symbol first and add in the offset.
3391 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
3392 forced into memory, as it usually produces better code. */
3393 split_const (src, &base, &offset);
3394 if (offset != const0_rtx
3395 && (targetm.cannot_force_const_mem (mode, src)
3396 || (!TARGET_MIPS16 && can_create_pseudo_p ())))
3398 base = mips_force_temporary (dest, base);
3399 mips_emit_move (dest, mips_add_offset (NULL, base, INTVAL (offset)));
3403 src = force_const_mem (mode, src);
3405 /* When using explicit relocs, constant pool references are sometimes
3406 not legitimate addresses. */
3407 mips_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0));
3408 mips_emit_move (dest, src);
3411 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
3412 sequence that is valid. */
3415 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
3417 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
3419 mips_emit_move (dest, force_reg (mode, src));
3423 /* We need to deal with constants that would be legitimate
3424 immediate_operands but aren't legitimate move_operands. */
3425 if (CONSTANT_P (src) && !move_operand (src, mode))
3427 mips_legitimize_const_move (mode, dest, src);
3428 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
3434 /* Return true if value X in context CONTEXT is a small-data address
3435 that can be rewritten as a LO_SUM. */
3438 mips_rewrite_small_data_p (rtx x, enum mips_symbol_context context)
3440 enum mips_symbol_type symbol_type;
3442 return (mips_lo_relocs[SYMBOL_GP_RELATIVE]
3443 && !mips_split_p[SYMBOL_GP_RELATIVE]
3444 && mips_symbolic_constant_p (x, context, &symbol_type)
3445 && symbol_type == SYMBOL_GP_RELATIVE);
3448 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
3449 containing MEM, or null if none. */
3452 mips_small_data_pattern_1 (rtx *loc, void *data)
3454 enum mips_symbol_context context;
3456 /* Ignore things like "g" constraints in asms. We make no particular
3457 guarantee about which symbolic constants are acceptable as asm operands
3458 versus which must be forced into a GPR. */
3459 if (GET_CODE (*loc) == LO_SUM || GET_CODE (*loc) == ASM_OPERANDS)
3464 if (for_each_rtx (&XEXP (*loc, 0), mips_small_data_pattern_1, *loc))
3469 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3470 return mips_rewrite_small_data_p (*loc, context);
3473 /* Return true if OP refers to small data symbols directly, not through
3477 mips_small_data_pattern_p (rtx op)
3479 return for_each_rtx (&op, mips_small_data_pattern_1, NULL);
3482 /* A for_each_rtx callback, used by mips_rewrite_small_data.
3483 DATA is the containing MEM, or null if none. */
3486 mips_rewrite_small_data_1 (rtx *loc, void *data)
3488 enum mips_symbol_context context;
3492 for_each_rtx (&XEXP (*loc, 0), mips_rewrite_small_data_1, *loc);
3496 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3497 if (mips_rewrite_small_data_p (*loc, context))
3498 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
3500 if (GET_CODE (*loc) == LO_SUM)
3506 /* Rewrite instruction pattern PATTERN so that it refers to small data
3507 using explicit relocations. */
3510 mips_rewrite_small_data (rtx pattern)
3512 pattern = copy_insn (pattern);
3513 for_each_rtx (&pattern, mips_rewrite_small_data_1, NULL);
3517 /* The cost of loading values from the constant pool. It should be
3518 larger than the cost of any constant we want to synthesize inline. */
3519 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3521 /* Return the cost of X when used as an operand to the MIPS16 instruction
3522 that implements CODE. Return -1 if there is no such instruction, or if
3523 X is not a valid immediate operand for it. */
3526 mips16_constant_cost (int code, HOST_WIDE_INT x)
3533 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3534 other shifts are extended. The shift patterns truncate the shift
3535 count to the right size, so there are no out-of-range values. */
3536 if (IN_RANGE (x, 1, 8))
3538 return COSTS_N_INSNS (1);
3541 if (IN_RANGE (x, -128, 127))
3543 if (SMALL_OPERAND (x))
3544 return COSTS_N_INSNS (1);
3548 /* Like LE, but reject the always-true case. */
3552 /* We add 1 to the immediate and use SLT. */
3555 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3558 if (IN_RANGE (x, 0, 255))
3560 if (SMALL_OPERAND_UNSIGNED (x))
3561 return COSTS_N_INSNS (1);
3566 /* Equality comparisons with 0 are cheap. */
3576 /* Return true if there is a non-MIPS16 instruction that implements CODE
3577 and if that instruction accepts X as an immediate operand. */
3580 mips_immediate_operand_p (int code, HOST_WIDE_INT x)
3587 /* All shift counts are truncated to a valid constant. */
3592 /* Likewise rotates, if the target supports rotates at all. */
3598 /* These instructions take 16-bit unsigned immediates. */
3599 return SMALL_OPERAND_UNSIGNED (x);
3604 /* These instructions take 16-bit signed immediates. */
3605 return SMALL_OPERAND (x);
3611 /* The "immediate" forms of these instructions are really
3612 implemented as comparisons with register 0. */
3617 /* Likewise, meaning that the only valid immediate operand is 1. */
3621 /* We add 1 to the immediate and use SLT. */
3622 return SMALL_OPERAND (x + 1);
3625 /* Likewise SLTU, but reject the always-true case. */
3626 return SMALL_OPERAND (x + 1) && x + 1 != 0;
3630 /* The bit position and size are immediate operands. */
3631 return ISA_HAS_EXT_INS;
3634 /* By default assume that $0 can be used for 0. */
3639 /* Return the cost of binary operation X, given that the instruction
3640 sequence for a word-sized or smaller operation has cost SINGLE_COST
3641 and that the sequence of a double-word operation has cost DOUBLE_COST.
3642 If SPEED is true, optimize for speed otherwise optimize for size. */
3645 mips_binary_cost (rtx x, int single_cost, int double_cost, bool speed)
3649 if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2)
3654 + set_src_cost (XEXP (x, 0), speed)
3655 + rtx_cost (XEXP (x, 1), GET_CODE (x), 1, speed));
3658 /* Return the cost of floating-point multiplications of mode MODE. */
3661 mips_fp_mult_cost (enum machine_mode mode)
3663 return mode == DFmode ? mips_cost->fp_mult_df : mips_cost->fp_mult_sf;
3666 /* Return the cost of floating-point divisions of mode MODE. */
3669 mips_fp_div_cost (enum machine_mode mode)
3671 return mode == DFmode ? mips_cost->fp_div_df : mips_cost->fp_div_sf;
3674 /* Return the cost of sign-extending OP to mode MODE, not including the
3675 cost of OP itself. */
3678 mips_sign_extend_cost (enum machine_mode mode, rtx op)
3681 /* Extended loads are as cheap as unextended ones. */
3684 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3685 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3688 if (ISA_HAS_SEB_SEH || GENERATE_MIPS16E)
3689 /* We can use SEB or SEH. */
3690 return COSTS_N_INSNS (1);
3692 /* We need to use a shift left and a shift right. */
3693 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3696 /* Return the cost of zero-extending OP to mode MODE, not including the
3697 cost of OP itself. */
3700 mips_zero_extend_cost (enum machine_mode mode, rtx op)
3703 /* Extended loads are as cheap as unextended ones. */
3706 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3707 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3708 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3710 if (GENERATE_MIPS16E)
3711 /* We can use ZEB or ZEH. */
3712 return COSTS_N_INSNS (1);
3715 /* We need to load 0xff or 0xffff into a register and use AND. */
3716 return COSTS_N_INSNS (GET_MODE (op) == QImode ? 2 : 3);
3718 /* We can use ANDI. */
3719 return COSTS_N_INSNS (1);
3722 /* Return the cost of moving between two registers of mode MODE,
3723 assuming that the move will be in pieces of at most UNITS bytes. */
3726 mips_set_reg_reg_piece_cost (enum machine_mode mode, unsigned int units)
3728 return COSTS_N_INSNS ((GET_MODE_SIZE (mode) + units - 1) / units);
3731 /* Return the cost of moving between two registers of mode MODE. */
3734 mips_set_reg_reg_cost (enum machine_mode mode)
3736 switch (GET_MODE_CLASS (mode))
3739 return mips_set_reg_reg_piece_cost (mode, GET_MODE_SIZE (CCmode));
3742 case MODE_COMPLEX_FLOAT:
3743 case MODE_VECTOR_FLOAT:
3744 if (TARGET_HARD_FLOAT)
3745 return mips_set_reg_reg_piece_cost (mode, UNITS_PER_HWFPVALUE);
3749 return mips_set_reg_reg_piece_cost (mode, UNITS_PER_WORD);
3753 /* Implement TARGET_RTX_COSTS. */
3756 mips_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
3757 int *total, bool speed)
3759 enum machine_mode mode = GET_MODE (x);
3760 bool float_mode_p = FLOAT_MODE_P (mode);
3764 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3765 appear in the instruction stream, and the cost of a comparison is
3766 really the cost of the branch or scc condition. At the time of
3767 writing, GCC only uses an explicit outer COMPARE code when optabs
3768 is testing whether a constant is expensive enough to force into a
3769 register. We want optabs to pass such constants through the MIPS
3770 expanders instead, so make all constants very cheap here. */
3771 if (outer_code == COMPARE)
3773 gcc_assert (CONSTANT_P (x));
3781 /* Treat *clear_upper32-style ANDs as having zero cost in the
3782 second operand. The cost is entirely in the first operand.
3784 ??? This is needed because we would otherwise try to CSE
3785 the constant operand. Although that's the right thing for
3786 instructions that continue to be a register operation throughout
3787 compilation, it is disastrous for instructions that could
3788 later be converted into a memory operation. */
3790 && outer_code == AND
3791 && UINTVAL (x) == 0xffffffff)
3799 cost = mips16_constant_cost (outer_code, INTVAL (x));
3808 /* When not optimizing for size, we care more about the cost
3809 of hot code, and hot code is often in a loop. If a constant
3810 operand needs to be forced into a register, we will often be
3811 able to hoist the constant load out of the loop, so the load
3812 should not contribute to the cost. */
3813 if (speed || mips_immediate_operand_p (outer_code, INTVAL (x)))
3825 if (force_to_mem_operand (x, VOIDmode))
3827 *total = COSTS_N_INSNS (1);
3830 cost = mips_const_insns (x);
3833 /* If the constant is likely to be stored in a GPR, SETs of
3834 single-insn constants are as cheap as register sets; we
3835 never want to CSE them.
3837 Don't reduce the cost of storing a floating-point zero in
3838 FPRs. If we have a zero in an FPR for other reasons, we
3839 can get better cfg-cleanup and delayed-branch results by
3840 using it consistently, rather than using $0 sometimes and
3841 an FPR at other times. Also, moves between floating-point
3842 registers are sometimes cheaper than (D)MTC1 $0. */
3844 && outer_code == SET
3845 && !(float_mode_p && TARGET_HARD_FLOAT))
3847 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3848 want to CSE the constant itself. It is usually better to
3849 have N copies of the last operation in the sequence and one
3850 shared copy of the other operations. (Note that this is
3851 not true for MIPS16 code, where the final operation in the
3852 sequence is often an extended instruction.)
3854 Also, if we have a CONST_INT, we don't know whether it is
3855 for a word or doubleword operation, so we cannot rely on
3856 the result of mips_build_integer. */
3857 else if (!TARGET_MIPS16
3858 && (outer_code == SET || mode == VOIDmode))
3860 *total = COSTS_N_INSNS (cost);
3863 /* The value will need to be fetched from the constant pool. */
3864 *total = CONSTANT_POOL_COST;
3868 /* If the address is legitimate, return the number of
3869 instructions it needs. */
3871 cost = mips_address_insns (addr, mode, true);
3874 *total = COSTS_N_INSNS (cost + 1);
3877 /* Check for a scaled indexed address. */
3878 if (mips_lwxs_address_p (addr)
3879 || mips_lx_address_p (addr, mode))
3881 *total = COSTS_N_INSNS (2);
3884 /* Otherwise use the default handling. */
3888 *total = COSTS_N_INSNS (6);
3892 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1);
3896 /* Check for a *clear_upper32 pattern and treat it like a zero
3897 extension. See the pattern's comment for details. */
3900 && CONST_INT_P (XEXP (x, 1))
3901 && UINTVAL (XEXP (x, 1)) == 0xffffffff)
3903 *total = (mips_zero_extend_cost (mode, XEXP (x, 0))
3904 + set_src_cost (XEXP (x, 0), speed));
3907 if (ISA_HAS_CINS && CONST_INT_P (XEXP (x, 1)))
3909 rtx op = XEXP (x, 0);
3910 if (GET_CODE (op) == ASHIFT
3911 && CONST_INT_P (XEXP (op, 1))
3912 && mask_low_and_shift_p (mode, XEXP (x, 1), XEXP (op, 1), 32))
3914 *total = COSTS_N_INSNS (1) + set_src_cost (XEXP (op, 0), speed);
3918 /* (AND (NOT op0) (NOT op1) is a nor operation that can be done in
3919 a single instruction. */
3921 && GET_CODE (XEXP (x, 0)) == NOT
3922 && GET_CODE (XEXP (x, 1)) == NOT)
3924 cost = GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1;
3925 *total = (COSTS_N_INSNS (cost)
3926 + set_src_cost (XEXP (XEXP (x, 0), 0), speed)
3927 + set_src_cost (XEXP (XEXP (x, 1), 0), speed));
3935 /* Double-word operations use two single-word operations. */
3936 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (2),
3945 if (CONSTANT_P (XEXP (x, 1)))
3946 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3949 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (12),
3955 *total = mips_cost->fp_add;
3957 *total = COSTS_N_INSNS (4);
3961 /* Low-part immediates need an extended MIPS16 instruction. */
3962 *total = (COSTS_N_INSNS (TARGET_MIPS16 ? 2 : 1)
3963 + set_src_cost (XEXP (x, 0), speed));
3978 /* Branch comparisons have VOIDmode, so use the first operand's
3980 mode = GET_MODE (XEXP (x, 0));
3981 if (FLOAT_MODE_P (mode))
3983 *total = mips_cost->fp_add;
3986 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3992 && (ISA_HAS_NMADD4_NMSUB4 || ISA_HAS_NMADD3_NMSUB3)
3993 && TARGET_FUSED_MADD
3994 && !HONOR_NANS (mode)
3995 && !HONOR_SIGNED_ZEROS (mode))
3997 /* See if we can use NMADD or NMSUB. See mips.md for the
3998 associated patterns. */
3999 rtx op0 = XEXP (x, 0);
4000 rtx op1 = XEXP (x, 1);
4001 if (GET_CODE (op0) == MULT && GET_CODE (XEXP (op0, 0)) == NEG)
4003 *total = (mips_fp_mult_cost (mode)
4004 + set_src_cost (XEXP (XEXP (op0, 0), 0), speed)
4005 + set_src_cost (XEXP (op0, 1), speed)
4006 + set_src_cost (op1, speed));
4009 if (GET_CODE (op1) == MULT)
4011 *total = (mips_fp_mult_cost (mode)
4012 + set_src_cost (op0, speed)
4013 + set_src_cost (XEXP (op1, 0), speed)
4014 + set_src_cost (XEXP (op1, 1), speed));
4023 /* If this is part of a MADD or MSUB, treat the PLUS as
4025 if ((ISA_HAS_FP_MADD4_MSUB4 || ISA_HAS_FP_MADD3_MSUB3)
4026 && TARGET_FUSED_MADD
4027 && GET_CODE (XEXP (x, 0)) == MULT)
4030 *total = mips_cost->fp_add;
4034 /* Double-word operations require three single-word operations and
4035 an SLTU. The MIPS16 version then needs to move the result of
4036 the SLTU from $24 to a MIPS16 register. */
4037 *total = mips_binary_cost (x, COSTS_N_INSNS (1),
4038 COSTS_N_INSNS (TARGET_MIPS16 ? 5 : 4),
4044 && (ISA_HAS_NMADD4_NMSUB4 || ISA_HAS_NMADD3_NMSUB3)
4045 && TARGET_FUSED_MADD
4046 && !HONOR_NANS (mode)
4047 && HONOR_SIGNED_ZEROS (mode))
4049 /* See if we can use NMADD or NMSUB. See mips.md for the
4050 associated patterns. */
4051 rtx op = XEXP (x, 0);
4052 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
4053 && GET_CODE (XEXP (op, 0)) == MULT)
4055 *total = (mips_fp_mult_cost (mode)
4056 + set_src_cost (XEXP (XEXP (op, 0), 0), speed)
4057 + set_src_cost (XEXP (XEXP (op, 0), 1), speed)
4058 + set_src_cost (XEXP (op, 1), speed));
4064 *total = mips_cost->fp_add;
4066 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1);
4071 *total = mips_fp_mult_cost (mode);
4072 else if (mode == DImode && !TARGET_64BIT)
4073 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
4074 where the mulsidi3 always includes an MFHI and an MFLO. */
4076 ? mips_cost->int_mult_si * 3 + 6
4077 : COSTS_N_INSNS (ISA_HAS_MUL3 ? 7 : 9));
4079 *total = COSTS_N_INSNS (ISA_HAS_MUL3 ? 1 : 2) + 1;
4080 else if (mode == DImode)
4081 *total = mips_cost->int_mult_di;
4083 *total = mips_cost->int_mult_si;
4087 /* Check for a reciprocal. */
4089 && ISA_HAS_FP_RECIP_RSQRT (mode)
4090 && flag_unsafe_math_optimizations
4091 && XEXP (x, 0) == CONST1_RTX (mode))
4093 if (outer_code == SQRT || GET_CODE (XEXP (x, 1)) == SQRT)
4094 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
4095 division as being free. */
4096 *total = set_src_cost (XEXP (x, 1), speed);
4098 *total = (mips_fp_div_cost (mode)
4099 + set_src_cost (XEXP (x, 1), speed));
4108 *total = mips_fp_div_cost (mode);
4117 /* It is our responsibility to make division by a power of 2
4118 as cheap as 2 register additions if we want the division
4119 expanders to be used for such operations; see the setting
4120 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
4121 should always produce shorter code than using
4122 expand_sdiv2_pow2. */
4124 && CONST_INT_P (XEXP (x, 1))
4125 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
4127 *total = COSTS_N_INSNS (2) + set_src_cost (XEXP (x, 0), speed);
4130 *total = COSTS_N_INSNS (mips_idiv_insns ());
4132 else if (mode == DImode)
4133 *total = mips_cost->int_div_di;
4135 *total = mips_cost->int_div_si;
4139 *total = mips_sign_extend_cost (mode, XEXP (x, 0));
4143 if (outer_code == SET
4145 && (GET_CODE (XEXP (x, 0)) == TRUNCATE
4146 || GET_CODE (XEXP (x, 0)) == SUBREG)
4147 && GET_MODE (XEXP (x, 0)) == QImode
4148 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
4150 *total = set_src_cost (XEXP (XEXP (x, 0), 0), speed);
4153 *total = mips_zero_extend_cost (mode, XEXP (x, 0));
4157 case UNSIGNED_FLOAT:
4160 case FLOAT_TRUNCATE:
4161 *total = mips_cost->fp_add;
4165 if (register_operand (SET_DEST (x), VOIDmode)
4166 && reg_or_0_operand (SET_SRC (x), VOIDmode))
4168 *total = mips_set_reg_reg_cost (GET_MODE (SET_DEST (x)));
4178 /* Implement TARGET_ADDRESS_COST. */
4181 mips_address_cost (rtx addr, enum machine_mode mode,
4182 addr_space_t as ATTRIBUTE_UNUSED,
4183 bool speed ATTRIBUTE_UNUSED)
4185 return mips_address_insns (addr, mode, false);
4188 /* Information about a single instruction in a multi-instruction
4190 struct mips_multi_member {
4191 /* True if this is a label, false if it is code. */
4194 /* The output_asm_insn format of the instruction. */
4197 /* The operands to the instruction. */
4198 rtx operands[MAX_RECOG_OPERANDS];
4200 typedef struct mips_multi_member mips_multi_member;
4202 /* The instructions that make up the current multi-insn sequence. */
4203 static vec<mips_multi_member> mips_multi_members;
4205 /* How many instructions (as opposed to labels) are in the current
4206 multi-insn sequence. */
4207 static unsigned int mips_multi_num_insns;
4209 /* Start a new multi-insn sequence. */
4212 mips_multi_start (void)
4214 mips_multi_members.truncate (0);
4215 mips_multi_num_insns = 0;
4218 /* Add a new, uninitialized member to the current multi-insn sequence. */
4220 static struct mips_multi_member *
4221 mips_multi_add (void)
4223 mips_multi_member empty;
4224 return mips_multi_members.safe_push (empty);
4227 /* Add a normal insn with the given asm format to the current multi-insn
4228 sequence. The other arguments are a null-terminated list of operands. */
4231 mips_multi_add_insn (const char *format, ...)
4233 struct mips_multi_member *member;
4238 member = mips_multi_add ();
4239 member->is_label_p = false;
4240 member->format = format;
4241 va_start (ap, format);
4243 while ((op = va_arg (ap, rtx)))
4244 member->operands[i++] = op;
4246 mips_multi_num_insns++;
4249 /* Add the given label definition to the current multi-insn sequence.
4250 The definition should include the colon. */
4253 mips_multi_add_label (const char *label)
4255 struct mips_multi_member *member;
4257 member = mips_multi_add ();
4258 member->is_label_p = true;
4259 member->format = label;
4262 /* Return the index of the last member of the current multi-insn sequence. */
4265 mips_multi_last_index (void)
4267 return mips_multi_members.length () - 1;
4270 /* Add a copy of an existing instruction to the current multi-insn
4271 sequence. I is the index of the instruction that should be copied. */
4274 mips_multi_copy_insn (unsigned int i)
4276 struct mips_multi_member *member;
4278 member = mips_multi_add ();
4279 memcpy (member, &mips_multi_members[i], sizeof (*member));
4280 gcc_assert (!member->is_label_p);
4283 /* Change the operand of an existing instruction in the current
4284 multi-insn sequence. I is the index of the instruction,
4285 OP is the index of the operand, and X is the new value. */
4288 mips_multi_set_operand (unsigned int i, unsigned int op, rtx x)
4290 mips_multi_members[i].operands[op] = x;
4293 /* Write out the asm code for the current multi-insn sequence. */
4296 mips_multi_write (void)
4298 struct mips_multi_member *member;
4301 FOR_EACH_VEC_ELT (mips_multi_members, i, member)
4302 if (member->is_label_p)
4303 fprintf (asm_out_file, "%s\n", member->format);
4305 output_asm_insn (member->format, member->operands);
4308 /* Return one word of double-word value OP, taking into account the fixed
4309 endianness of certain registers. HIGH_P is true to select the high part,
4310 false to select the low part. */
4313 mips_subword (rtx op, bool high_p)
4315 unsigned int byte, offset;
4316 enum machine_mode mode;
4318 mode = GET_MODE (op);
4319 if (mode == VOIDmode)
4320 mode = TARGET_64BIT ? TImode : DImode;
4322 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
4323 byte = UNITS_PER_WORD;
4327 if (FP_REG_RTX_P (op))
4329 /* Paired FPRs are always ordered little-endian. */
4330 offset = (UNITS_PER_WORD < UNITS_PER_HWFPVALUE ? high_p : byte != 0);
4331 return gen_rtx_REG (word_mode, REGNO (op) + offset);
4335 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
4337 return simplify_gen_subreg (word_mode, op, mode, byte);
4340 /* Return true if SRC should be moved into DEST using "MULT $0, $0".
4341 SPLIT_TYPE is the condition under which moves should be split. */
4344 mips_mult_move_p (rtx dest, rtx src, enum mips_split_type split_type)
4346 return ((split_type != SPLIT_FOR_SPEED
4347 || mips_tuning_info.fast_mult_zero_zero_p)
4348 && src == const0_rtx
4350 && GET_MODE_SIZE (GET_MODE (dest)) == 2 * UNITS_PER_WORD
4351 && (ISA_HAS_DSP_MULT
4352 ? ACC_REG_P (REGNO (dest))
4353 : MD_REG_P (REGNO (dest))));
4356 /* Return true if a move from SRC to DEST should be split into two.
4357 SPLIT_TYPE describes the split condition. */
4360 mips_split_move_p (rtx dest, rtx src, enum mips_split_type split_type)
4362 /* Check whether the move can be done using some variant of MULT $0,$0. */
4363 if (mips_mult_move_p (dest, src, split_type))
4366 /* FPR-to-FPR moves can be done in a single instruction, if they're
4368 unsigned int size = GET_MODE_SIZE (GET_MODE (dest));
4369 if (size == 8 && FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
4372 /* Check for floating-point loads and stores. */
4373 if (size == 8 && ISA_HAS_LDC1_SDC1)
4375 if (FP_REG_RTX_P (dest) && MEM_P (src))
4377 if (FP_REG_RTX_P (src) && MEM_P (dest))
4381 /* Otherwise split all multiword moves. */
4382 return size > UNITS_PER_WORD;
4385 /* Split a move from SRC to DEST, given that mips_split_move_p holds.
4386 SPLIT_TYPE describes the split condition. */
4389 mips_split_move (rtx dest, rtx src, enum mips_split_type split_type)
4393 gcc_checking_assert (mips_split_move_p (dest, src, split_type));
4394 if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src))
4396 if (!TARGET_64BIT && GET_MODE (dest) == DImode)
4397 emit_insn (gen_move_doubleword_fprdi (dest, src));
4398 else if (!TARGET_64BIT && GET_MODE (dest) == DFmode)
4399 emit_insn (gen_move_doubleword_fprdf (dest, src));
4400 else if (!TARGET_64BIT && GET_MODE (dest) == V2SFmode)
4401 emit_insn (gen_move_doubleword_fprv2sf (dest, src));
4402 else if (!TARGET_64BIT && GET_MODE (dest) == V2SImode)
4403 emit_insn (gen_move_doubleword_fprv2si (dest, src));
4404 else if (!TARGET_64BIT && GET_MODE (dest) == V4HImode)
4405 emit_insn (gen_move_doubleword_fprv4hi (dest, src));
4406 else if (!TARGET_64BIT && GET_MODE (dest) == V8QImode)
4407 emit_insn (gen_move_doubleword_fprv8qi (dest, src));
4408 else if (TARGET_64BIT && GET_MODE (dest) == TFmode)
4409 emit_insn (gen_move_doubleword_fprtf (dest, src));
4413 else if (REG_P (dest) && REGNO (dest) == MD_REG_FIRST)
4415 low_dest = mips_subword (dest, false);
4416 mips_emit_move (low_dest, mips_subword (src, false));
4418 emit_insn (gen_mthidi_ti (dest, mips_subword (src, true), low_dest));
4420 emit_insn (gen_mthisi_di (dest, mips_subword (src, true), low_dest));
4422 else if (REG_P (src) && REGNO (src) == MD_REG_FIRST)
4424 mips_emit_move (mips_subword (dest, false), mips_subword (src, false));
4426 emit_insn (gen_mfhidi_ti (mips_subword (dest, true), src));
4428 emit_insn (gen_mfhisi_di (mips_subword (dest, true), src));
4432 /* The operation can be split into two normal moves. Decide in
4433 which order to do them. */
4434 low_dest = mips_subword (dest, false);
4435 if (REG_P (low_dest)
4436 && reg_overlap_mentioned_p (low_dest, src))
4438 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4439 mips_emit_move (low_dest, mips_subword (src, false));
4443 mips_emit_move (low_dest, mips_subword (src, false));
4444 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4449 /* Return the split type for instruction INSN. */
4451 static enum mips_split_type
4452 mips_insn_split_type (rtx insn)
4454 basic_block bb = BLOCK_FOR_INSN (insn);
4457 if (optimize_bb_for_speed_p (bb))
4458 return SPLIT_FOR_SPEED;
4460 return SPLIT_FOR_SIZE;
4462 /* Once CFG information has been removed, we should trust the optimization
4463 decisions made by previous passes and only split where necessary. */
4464 return SPLIT_IF_NECESSARY;
4467 /* Return true if a move from SRC to DEST in INSN should be split. */
4470 mips_split_move_insn_p (rtx dest, rtx src, rtx insn)
4472 return mips_split_move_p (dest, src, mips_insn_split_type (insn));
4475 /* Split a move from SRC to DEST in INSN, given that mips_split_move_insn_p
4479 mips_split_move_insn (rtx dest, rtx src, rtx insn)
4481 mips_split_move (dest, src, mips_insn_split_type (insn));
4484 /* Return the appropriate instructions to move SRC into DEST. Assume
4485 that SRC is operand 1 and DEST is operand 0. */
4488 mips_output_move (rtx dest, rtx src)
4490 enum rtx_code dest_code, src_code;
4491 enum machine_mode mode;
4492 enum mips_symbol_type symbol_type;
4495 dest_code = GET_CODE (dest);
4496 src_code = GET_CODE (src);
4497 mode = GET_MODE (dest);
4498 dbl_p = (GET_MODE_SIZE (mode) == 8);
4500 if (mips_split_move_p (dest, src, SPLIT_IF_NECESSARY))
4503 if ((src_code == REG && GP_REG_P (REGNO (src)))
4504 || (!TARGET_MIPS16 && src == CONST0_RTX (mode)))
4506 if (dest_code == REG)
4508 if (GP_REG_P (REGNO (dest)))
4509 return "move\t%0,%z1";
4511 if (mips_mult_move_p (dest, src, SPLIT_IF_NECESSARY))
4513 if (ISA_HAS_DSP_MULT)
4514 return "mult\t%q0,%.,%.";
4516 return "mult\t%.,%.";
4519 /* Moves to HI are handled by special .md insns. */
4520 if (REGNO (dest) == LO_REGNUM)
4523 if (DSP_ACC_REG_P (REGNO (dest)))
4525 static char retval[] = "mt__\t%z1,%q0";
4527 retval[2] = reg_names[REGNO (dest)][4];
4528 retval[3] = reg_names[REGNO (dest)][5];
4532 if (FP_REG_P (REGNO (dest)))
4533 return dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
4535 if (ALL_COP_REG_P (REGNO (dest)))
4537 static char retval[] = "dmtc_\t%z1,%0";
4539 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4540 return dbl_p ? retval : retval + 1;
4543 if (dest_code == MEM)
4544 switch (GET_MODE_SIZE (mode))
4546 case 1: return "sb\t%z1,%0";
4547 case 2: return "sh\t%z1,%0";
4548 case 4: return "sw\t%z1,%0";
4549 case 8: return "sd\t%z1,%0";
4552 if (dest_code == REG && GP_REG_P (REGNO (dest)))
4554 if (src_code == REG)
4556 /* Moves from HI are handled by special .md insns. */
4557 if (REGNO (src) == LO_REGNUM)
4559 /* When generating VR4120 or VR4130 code, we use MACC and
4560 DMACC instead of MFLO. This avoids both the normal
4561 MIPS III HI/LO hazards and the errata related to
4564 return dbl_p ? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
4568 if (DSP_ACC_REG_P (REGNO (src)))
4570 static char retval[] = "mf__\t%0,%q1";
4572 retval[2] = reg_names[REGNO (src)][4];
4573 retval[3] = reg_names[REGNO (src)][5];
4577 if (FP_REG_P (REGNO (src)))
4578 return dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
4580 if (ALL_COP_REG_P (REGNO (src)))
4582 static char retval[] = "dmfc_\t%0,%1";
4584 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4585 return dbl_p ? retval : retval + 1;
4589 if (src_code == MEM)
4590 switch (GET_MODE_SIZE (mode))
4592 case 1: return "lbu\t%0,%1";
4593 case 2: return "lhu\t%0,%1";
4594 case 4: return "lw\t%0,%1";
4595 case 8: return "ld\t%0,%1";
4598 if (src_code == CONST_INT)
4600 /* Don't use the X format for the operand itself, because that
4601 will give out-of-range numbers for 64-bit hosts and 32-bit
4604 return "li\t%0,%1\t\t\t# %X1";
4606 if (SMALL_OPERAND_UNSIGNED (INTVAL (src)))
4609 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src)))
4613 if (src_code == HIGH)
4614 return TARGET_MIPS16 ? "#" : "lui\t%0,%h1";
4616 if (CONST_GP_P (src))
4617 return "move\t%0,%1";
4619 if (mips_symbolic_constant_p (src, SYMBOL_CONTEXT_LEA, &symbol_type)
4620 && mips_lo_relocs[symbol_type] != 0)
4622 /* A signed 16-bit constant formed by applying a relocation
4623 operator to a symbolic address. */
4624 gcc_assert (!mips_split_p[symbol_type]);
4625 return "li\t%0,%R1";
4628 if (symbolic_operand (src, VOIDmode))
4630 gcc_assert (TARGET_MIPS16
4631 ? TARGET_MIPS16_TEXT_LOADS
4632 : !TARGET_EXPLICIT_RELOCS);
4633 return dbl_p ? "dla\t%0,%1" : "la\t%0,%1";
4636 if (src_code == REG && FP_REG_P (REGNO (src)))
4638 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4640 if (GET_MODE (dest) == V2SFmode)
4641 return "mov.ps\t%0,%1";
4643 return dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1";
4646 if (dest_code == MEM)
4647 return dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0";
4649 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4651 if (src_code == MEM)
4652 return dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1";
4654 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
4656 static char retval[] = "l_c_\t%0,%1";
4658 retval[1] = (dbl_p ? 'd' : 'w');
4659 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4662 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
4664 static char retval[] = "s_c_\t%1,%0";
4666 retval[1] = (dbl_p ? 'd' : 'w');
4667 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4673 /* Return true if CMP1 is a suitable second operand for integer ordering
4674 test CODE. See also the *sCC patterns in mips.md. */
4677 mips_int_order_operand_ok_p (enum rtx_code code, rtx cmp1)
4683 return reg_or_0_operand (cmp1, VOIDmode);
4687 return !TARGET_MIPS16 && cmp1 == const1_rtx;
4691 return arith_operand (cmp1, VOIDmode);
4694 return sle_operand (cmp1, VOIDmode);
4697 return sleu_operand (cmp1, VOIDmode);
4704 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4705 integer ordering test *CODE, or if an equivalent combination can
4706 be formed by adjusting *CODE and *CMP1. When returning true, update
4707 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4711 mips_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1,
4712 enum machine_mode mode)
4714 HOST_WIDE_INT plus_one;
4716 if (mips_int_order_operand_ok_p (*code, *cmp1))
4719 if (CONST_INT_P (*cmp1))
4723 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4724 if (INTVAL (*cmp1) < plus_one)
4727 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4733 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4737 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4748 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4749 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4750 is nonnull, it's OK to set TARGET to the inverse of the result and
4751 flip *INVERT_PTR instead. */
4754 mips_emit_int_order_test (enum rtx_code code, bool *invert_ptr,
4755 rtx target, rtx cmp0, rtx cmp1)
4757 enum machine_mode mode;
4759 /* First see if there is a MIPS instruction that can do this operation.
4760 If not, try doing the same for the inverse operation. If that also
4761 fails, force CMP1 into a register and try again. */
4762 mode = GET_MODE (cmp0);
4763 if (mips_canonicalize_int_order_test (&code, &cmp1, mode))
4764 mips_emit_binary (code, target, cmp0, cmp1);
4767 enum rtx_code inv_code = reverse_condition (code);
4768 if (!mips_canonicalize_int_order_test (&inv_code, &cmp1, mode))
4770 cmp1 = force_reg (mode, cmp1);
4771 mips_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1);
4773 else if (invert_ptr == 0)
4777 inv_target = mips_force_binary (GET_MODE (target),
4778 inv_code, cmp0, cmp1);
4779 mips_emit_binary (XOR, target, inv_target, const1_rtx);
4783 *invert_ptr = !*invert_ptr;
4784 mips_emit_binary (inv_code, target, cmp0, cmp1);
4789 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4790 The register will have the same mode as CMP0. */
4793 mips_zero_if_equal (rtx cmp0, rtx cmp1)
4795 if (cmp1 == const0_rtx)
4798 if (uns_arith_operand (cmp1, VOIDmode))
4799 return expand_binop (GET_MODE (cmp0), xor_optab,
4800 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4802 return expand_binop (GET_MODE (cmp0), sub_optab,
4803 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4806 /* Convert *CODE into a code that can be used in a floating-point
4807 scc instruction (C.cond.fmt). Return true if the values of
4808 the condition code registers will be inverted, with 0 indicating
4809 that the condition holds. */
4812 mips_reversed_fp_cond (enum rtx_code *code)
4819 *code = reverse_condition_maybe_unordered (*code);
4827 /* Allocate a floating-point condition-code register of mode MODE.
4829 These condition code registers are used for certain kinds
4830 of compound operation, such as compare and branches, vconds,
4831 and built-in functions. At expand time, their use is entirely
4832 controlled by MIPS-specific code and is entirely internal
4833 to these compound operations.
4835 We could (and did in the past) expose condition-code values
4836 as pseudo registers and leave the register allocator to pick
4837 appropriate registers. The problem is that it is not practically
4838 possible for the rtl optimizers to guarantee that no spills will
4839 be needed, even when AVOID_CCMODE_COPIES is defined. We would
4840 therefore need spill and reload sequences to handle the worst case.
4842 Although such sequences do exist, they are very expensive and are
4843 not something we'd want to use. This is especially true of CCV2 and
4844 CCV4, where all the shuffling would greatly outweigh whatever benefit
4845 the vectorization itself provides.
4847 The main benefit of having more than one condition-code register
4848 is to allow the pipelining of operations, especially those involving
4849 comparisons and conditional moves. We don't really expect the
4850 registers to be live for long periods, and certainly never want
4851 them to be live across calls.
4853 Also, there should be no penalty attached to using all the available
4854 registers. They are simply bits in the same underlying FPU control
4857 We therefore expose the hardware registers from the outset and use
4858 a simple round-robin allocation scheme. */
4861 mips_allocate_fcc (enum machine_mode mode)
4863 unsigned int regno, count;
4865 gcc_assert (TARGET_HARD_FLOAT && ISA_HAS_8CC);
4869 else if (mode == CCV2mode)
4871 else if (mode == CCV4mode)
4876 cfun->machine->next_fcc += -cfun->machine->next_fcc & (count - 1);
4877 if (cfun->machine->next_fcc > ST_REG_LAST - ST_REG_FIRST)
4878 cfun->machine->next_fcc = 0;
4879 regno = ST_REG_FIRST + cfun->machine->next_fcc;
4880 cfun->machine->next_fcc += count;
4881 return gen_rtx_REG (mode, regno);
4884 /* Convert a comparison into something that can be used in a branch or
4885 conditional move. On entry, *OP0 and *OP1 are the values being
4886 compared and *CODE is the code used to compare them.
4888 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
4889 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
4890 otherwise any standard branch condition can be used. The standard branch
4893 - EQ or NE between two registers.
4894 - any comparison between a register and zero. */
4897 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
4902 if (GET_MODE_CLASS (GET_MODE (*op0)) == MODE_INT)
4904 if (!need_eq_ne_p && *op1 == const0_rtx)
4906 else if (*code == EQ || *code == NE)
4910 *op0 = mips_zero_if_equal (cmp_op0, cmp_op1);
4914 *op1 = force_reg (GET_MODE (cmp_op0), cmp_op1);
4918 /* The comparison needs a separate scc instruction. Store the
4919 result of the scc in *OP0 and compare it against zero. */
4920 bool invert = false;
4921 *op0 = gen_reg_rtx (GET_MODE (cmp_op0));
4922 mips_emit_int_order_test (*code, &invert, *op0, cmp_op0, cmp_op1);
4923 *code = (invert ? EQ : NE);
4927 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0)))
4929 *op0 = gen_rtx_REG (CCDSPmode, CCDSP_CC_REGNUM);
4930 mips_emit_binary (*code, *op0, cmp_op0, cmp_op1);
4936 enum rtx_code cmp_code;
4938 /* Floating-point tests use a separate C.cond.fmt comparison to
4939 set a condition code register. The branch or conditional move
4940 will then compare that register against zero.
4942 Set CMP_CODE to the code of the comparison instruction and
4943 *CODE to the code that the branch or move should use. */
4945 *code = mips_reversed_fp_cond (&cmp_code) ? EQ : NE;
4947 ? mips_allocate_fcc (CCmode)
4948 : gen_rtx_REG (CCmode, FPSW_REGNUM));
4950 mips_emit_binary (cmp_code, *op0, cmp_op0, cmp_op1);
4954 /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2]
4955 and OPERAND[3]. Store the result in OPERANDS[0].
4957 On 64-bit targets, the mode of the comparison and target will always be
4958 SImode, thus possibly narrower than that of the comparison's operands. */
4961 mips_expand_scc (rtx operands[])
4963 rtx target = operands[0];
4964 enum rtx_code code = GET_CODE (operands[1]);
4965 rtx op0 = operands[2];
4966 rtx op1 = operands[3];
4968 gcc_assert (GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT);
4970 if (code == EQ || code == NE)
4973 && reg_imm10_operand (op1, GET_MODE (op1)))
4974 mips_emit_binary (code, target, op0, op1);
4977 rtx zie = mips_zero_if_equal (op0, op1);
4978 mips_emit_binary (code, target, zie, const0_rtx);
4982 mips_emit_int_order_test (code, 0, target, op0, op1);
4985 /* Compare OPERANDS[1] with OPERANDS[2] using comparison code
4986 CODE and jump to OPERANDS[3] if the condition holds. */
4989 mips_expand_conditional_branch (rtx *operands)
4991 enum rtx_code code = GET_CODE (operands[0]);
4992 rtx op0 = operands[1];
4993 rtx op1 = operands[2];
4996 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
4997 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
4998 emit_jump_insn (gen_condjump (condition, operands[3]));
5003 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
5004 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
5007 mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
5008 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
5013 reversed_p = mips_reversed_fp_cond (&cond);
5014 cmp_result = mips_allocate_fcc (CCV2mode);
5015 emit_insn (gen_scc_ps (cmp_result,
5016 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
5018 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
5021 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
5025 /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0]
5026 if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
5029 mips_expand_conditional_move (rtx *operands)
5032 enum rtx_code code = GET_CODE (operands[1]);
5033 rtx op0 = XEXP (operands[1], 0);
5034 rtx op1 = XEXP (operands[1], 1);
5036 mips_emit_compare (&code, &op0, &op1, true);
5037 cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
5038 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
5039 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), cond,
5040 operands[2], operands[3])));
5043 /* Perform the comparison in COMPARISON, then trap if the condition holds. */
5046 mips_expand_conditional_trap (rtx comparison)
5049 enum machine_mode mode;
5052 /* MIPS conditional trap instructions don't have GT or LE flavors,
5053 so we must swap the operands and convert to LT and GE respectively. */
5054 code = GET_CODE (comparison);
5061 code = swap_condition (code);
5062 op0 = XEXP (comparison, 1);
5063 op1 = XEXP (comparison, 0);
5067 op0 = XEXP (comparison, 0);
5068 op1 = XEXP (comparison, 1);
5072 mode = GET_MODE (XEXP (comparison, 0));
5073 op0 = force_reg (mode, op0);
5074 if (!arith_operand (op1, mode))
5075 op1 = force_reg (mode, op1);
5077 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
5078 gen_rtx_fmt_ee (code, mode, op0, op1),
5082 /* Initialize *CUM for a call to a function of type FNTYPE. */
5085 mips_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype)
5087 memset (cum, 0, sizeof (*cum));
5088 cum->prototype = (fntype && prototype_p (fntype));
5089 cum->gp_reg_found = (cum->prototype && stdarg_p (fntype));
5092 /* Fill INFO with information about a single argument. CUM is the
5093 cumulative state for earlier arguments. MODE is the mode of this
5094 argument and TYPE is its type (if known). NAMED is true if this
5095 is a named (fixed) argument rather than a variable one. */
5098 mips_get_arg_info (struct mips_arg_info *info, const CUMULATIVE_ARGS *cum,
5099 enum machine_mode mode, const_tree type, bool named)
5101 bool doubleword_aligned_p;
5102 unsigned int num_bytes, num_words, max_regs;
5104 /* Work out the size of the argument. */
5105 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
5106 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5108 /* Decide whether it should go in a floating-point register, assuming
5109 one is free. Later code checks for availability.
5111 The checks against UNITS_PER_FPVALUE handle the soft-float and
5112 single-float cases. */
5116 /* The EABI conventions have traditionally been defined in terms
5117 of TYPE_MODE, regardless of the actual type. */
5118 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
5119 || mode == V2SFmode)
5120 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
5125 /* Only leading floating-point scalars are passed in
5126 floating-point registers. We also handle vector floats the same
5127 say, which is OK because they are not covered by the standard ABI. */
5128 info->fpr_p = (!cum->gp_reg_found
5129 && cum->arg_number < 2
5131 || SCALAR_FLOAT_TYPE_P (type)
5132 || VECTOR_FLOAT_TYPE_P (type))
5133 && (GET_MODE_CLASS (mode) == MODE_FLOAT
5134 || mode == V2SFmode)
5135 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
5140 /* Scalar, complex and vector floating-point types are passed in
5141 floating-point registers, as long as this is a named rather
5142 than a variable argument. */
5143 info->fpr_p = (named
5144 && (type == 0 || FLOAT_TYPE_P (type))
5145 && (GET_MODE_CLASS (mode) == MODE_FLOAT
5146 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5147 || mode == V2SFmode)
5148 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
5150 /* ??? According to the ABI documentation, the real and imaginary
5151 parts of complex floats should be passed in individual registers.
5152 The real and imaginary parts of stack arguments are supposed
5153 to be contiguous and there should be an extra word of padding
5156 This has two problems. First, it makes it impossible to use a
5157 single "void *" va_list type, since register and stack arguments
5158 are passed differently. (At the time of writing, MIPSpro cannot
5159 handle complex float varargs correctly.) Second, it's unclear
5160 what should happen when there is only one register free.
5162 For now, we assume that named complex floats should go into FPRs
5163 if there are two FPRs free, otherwise they should be passed in the
5164 same way as a struct containing two floats. */
5166 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5167 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
5169 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
5170 info->fpr_p = false;
5180 /* See whether the argument has doubleword alignment. */
5181 doubleword_aligned_p = (mips_function_arg_boundary (mode, type)
5184 /* Set REG_OFFSET to the register count we're interested in.
5185 The EABI allocates the floating-point registers separately,
5186 but the other ABIs allocate them like integer registers. */
5187 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
5191 /* Advance to an even register if the argument is doubleword-aligned. */
5192 if (doubleword_aligned_p)
5193 info->reg_offset += info->reg_offset & 1;
5195 /* Work out the offset of a stack argument. */
5196 info->stack_offset = cum->stack_words;
5197 if (doubleword_aligned_p)
5198 info->stack_offset += info->stack_offset & 1;
5200 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
5202 /* Partition the argument between registers and stack. */
5203 info->reg_words = MIN (num_words, max_regs);
5204 info->stack_words = num_words - info->reg_words;
5207 /* INFO describes a register argument that has the normal format for the
5208 argument's mode. Return the register it uses, assuming that FPRs are
5209 available if HARD_FLOAT_P. */
5212 mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p)
5214 if (!info->fpr_p || !hard_float_p)
5215 return GP_ARG_FIRST + info->reg_offset;
5216 else if (mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info->reg_offset > 0)
5217 /* In o32, the second argument is always passed in $f14
5218 for TARGET_DOUBLE_FLOAT, regardless of whether the
5219 first argument was a word or doubleword. */
5220 return FP_ARG_FIRST + 2;
5222 return FP_ARG_FIRST + info->reg_offset;
5225 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
5228 mips_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED)
5230 return !TARGET_OLDABI;
5233 /* Implement TARGET_FUNCTION_ARG. */
5236 mips_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
5237 const_tree type, bool named)
5239 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
5240 struct mips_arg_info info;
5242 /* We will be called with a mode of VOIDmode after the last argument
5243 has been seen. Whatever we return will be passed to the call expander.
5244 If we need a MIPS16 fp_code, return a REG with the code stored as
5246 if (mode == VOIDmode)
5248 if (TARGET_MIPS16 && cum->fp_code != 0)
5249 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
5254 mips_get_arg_info (&info, cum, mode, type, named);
5256 /* Return straight away if the whole argument is passed on the stack. */
5257 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
5260 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
5261 contains a double in its entirety, then that 64-bit chunk is passed
5262 in a floating-point register. */
5264 && TARGET_HARD_FLOAT
5267 && TREE_CODE (type) == RECORD_TYPE
5268 && TYPE_SIZE_UNIT (type)
5269 && tree_fits_uhwi_p (TYPE_SIZE_UNIT (type)))
5273 /* First check to see if there is any such field. */
5274 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
5275 if (TREE_CODE (field) == FIELD_DECL
5276 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
5277 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
5278 && tree_fits_shwi_p (bit_position (field))
5279 && int_bit_position (field) % BITS_PER_WORD == 0)
5284 /* Now handle the special case by returning a PARALLEL
5285 indicating where each 64-bit chunk goes. INFO.REG_WORDS
5286 chunks are passed in registers. */
5288 HOST_WIDE_INT bitpos;
5291 /* assign_parms checks the mode of ENTRY_PARM, so we must
5292 use the actual mode here. */
5293 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
5296 field = TYPE_FIELDS (type);
5297 for (i = 0; i < info.reg_words; i++)
5301 for (; field; field = DECL_CHAIN (field))
5302 if (TREE_CODE (field) == FIELD_DECL
5303 && int_bit_position (field) >= bitpos)
5307 && int_bit_position (field) == bitpos
5308 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
5309 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
5310 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
5312 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
5315 = gen_rtx_EXPR_LIST (VOIDmode, reg,
5316 GEN_INT (bitpos / BITS_PER_UNIT));
5318 bitpos += BITS_PER_WORD;
5324 /* Handle the n32/n64 conventions for passing complex floating-point
5325 arguments in FPR pairs. The real part goes in the lower register
5326 and the imaginary part goes in the upper register. */
5329 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5332 enum machine_mode inner;
5335 inner = GET_MODE_INNER (mode);
5336 regno = FP_ARG_FIRST + info.reg_offset;
5337 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
5339 /* Real part in registers, imaginary part on stack. */
5340 gcc_assert (info.stack_words == info.reg_words);
5341 return gen_rtx_REG (inner, regno);
5345 gcc_assert (info.stack_words == 0);
5346 real = gen_rtx_EXPR_LIST (VOIDmode,
5347 gen_rtx_REG (inner, regno),
5349 imag = gen_rtx_EXPR_LIST (VOIDmode,
5351 regno + info.reg_words / 2),
5352 GEN_INT (GET_MODE_SIZE (inner)));
5353 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
5357 return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT));
5360 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
5363 mips_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
5364 const_tree type, bool named)
5366 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
5367 struct mips_arg_info info;
5369 mips_get_arg_info (&info, cum, mode, type, named);
5372 cum->gp_reg_found = true;
5374 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
5375 an explanation of what this code does. It assumes that we're using
5376 either the o32 or the o64 ABI, both of which pass at most 2 arguments
5378 if (cum->arg_number < 2 && info.fpr_p)
5379 cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2);
5381 /* Advance the register count. This has the effect of setting
5382 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
5383 argument required us to skip the final GPR and pass the whole
5384 argument on the stack. */
5385 if (mips_abi != ABI_EABI || !info.fpr_p)
5386 cum->num_gprs = info.reg_offset + info.reg_words;
5387 else if (info.reg_words > 0)
5388 cum->num_fprs += MAX_FPRS_PER_FMT;
5390 /* Advance the stack word count. */
5391 if (info.stack_words > 0)
5392 cum->stack_words = info.stack_offset + info.stack_words;
5397 /* Implement TARGET_ARG_PARTIAL_BYTES. */
5400 mips_arg_partial_bytes (cumulative_args_t cum,
5401 enum machine_mode mode, tree type, bool named)
5403 struct mips_arg_info info;
5405 mips_get_arg_info (&info, get_cumulative_args (cum), mode, type, named);
5406 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
5409 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
5410 least PARM_BOUNDARY bits of alignment, but will be given anything up
5411 to STACK_BOUNDARY bits if the type requires it. */
5414 mips_function_arg_boundary (enum machine_mode mode, const_tree type)
5416 unsigned int alignment;
5418 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
5419 if (alignment < PARM_BOUNDARY)
5420 alignment = PARM_BOUNDARY;
5421 if (alignment > STACK_BOUNDARY)
5422 alignment = STACK_BOUNDARY;
5426 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
5427 upward rather than downward. In other words, return true if the
5428 first byte of the stack slot has useful data, false if the last
5432 mips_pad_arg_upward (enum machine_mode mode, const_tree type)
5434 /* On little-endian targets, the first byte of every stack argument
5435 is passed in the first byte of the stack slot. */
5436 if (!BYTES_BIG_ENDIAN)
5439 /* Otherwise, integral types are padded downward: the last byte of a
5440 stack argument is passed in the last byte of the stack slot. */
5442 ? (INTEGRAL_TYPE_P (type)
5443 || POINTER_TYPE_P (type)
5444 || FIXED_POINT_TYPE_P (type))
5445 : (SCALAR_INT_MODE_P (mode)
5446 || ALL_SCALAR_FIXED_POINT_MODE_P (mode)))
5449 /* Big-endian o64 pads floating-point arguments downward. */
5450 if (mips_abi == ABI_O64)
5451 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
5454 /* Other types are padded upward for o32, o64, n32 and n64. */
5455 if (mips_abi != ABI_EABI)
5458 /* Arguments smaller than a stack slot are padded downward. */
5459 if (mode != BLKmode)
5460 return GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY;
5462 return int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT);
5465 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
5466 if the least significant byte of the register has useful data. Return
5467 the opposite if the most significant byte does. */
5470 mips_pad_reg_upward (enum machine_mode mode, tree type)
5472 /* No shifting is required for floating-point arguments. */
5473 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
5474 return !BYTES_BIG_ENDIAN;
5476 /* Otherwise, apply the same padding to register arguments as we do
5477 to stack arguments. */
5478 return mips_pad_arg_upward (mode, type);
5481 /* Return nonzero when an argument must be passed by reference. */
5484 mips_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
5485 enum machine_mode mode, const_tree type,
5486 bool named ATTRIBUTE_UNUSED)
5488 if (mips_abi == ABI_EABI)
5492 /* ??? How should SCmode be handled? */
5493 if (mode == DImode || mode == DFmode
5494 || mode == DQmode || mode == UDQmode
5495 || mode == DAmode || mode == UDAmode)
5498 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
5499 return size == -1 || size > UNITS_PER_WORD;
5503 /* If we have a variable-sized parameter, we have no choice. */
5504 return targetm.calls.must_pass_in_stack (mode, type);
5508 /* Implement TARGET_CALLEE_COPIES. */
5511 mips_callee_copies (cumulative_args_t cum ATTRIBUTE_UNUSED,
5512 enum machine_mode mode ATTRIBUTE_UNUSED,
5513 const_tree type ATTRIBUTE_UNUSED, bool named)
5515 return mips_abi == ABI_EABI && named;
5518 /* See whether VALTYPE is a record whose fields should be returned in
5519 floating-point registers. If so, return the number of fields and
5520 list them in FIELDS (which should have two elements). Return 0
5523 For n32 & n64, a structure with one or two fields is returned in
5524 floating-point registers as long as every field has a floating-point
5528 mips_fpr_return_fields (const_tree valtype, tree *fields)
5536 if (TREE_CODE (valtype) != RECORD_TYPE)
5540 for (field = TYPE_FIELDS (valtype); field != 0; field = DECL_CHAIN (field))
5542 if (TREE_CODE (field) != FIELD_DECL)
5545 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)))
5551 fields[i++] = field;
5556 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
5557 a value in the most significant part of $2/$3 if:
5559 - the target is big-endian;
5561 - the value has a structure or union type (we generalize this to
5562 cover aggregates from other languages too); and
5564 - the structure is not returned in floating-point registers. */
5567 mips_return_in_msb (const_tree valtype)
5571 return (TARGET_NEWABI
5572 && TARGET_BIG_ENDIAN
5573 && AGGREGATE_TYPE_P (valtype)
5574 && mips_fpr_return_fields (valtype, fields) == 0);
5577 /* Return true if the function return value MODE will get returned in a
5578 floating-point register. */
5581 mips_return_mode_in_fpr_p (enum machine_mode mode)
5583 return ((GET_MODE_CLASS (mode) == MODE_FLOAT
5585 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5586 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE);
5589 /* Return the representation of an FPR return register when the
5590 value being returned in FP_RETURN has mode VALUE_MODE and the
5591 return type itself has mode TYPE_MODE. On NewABI targets,
5592 the two modes may be different for structures like:
5594 struct __attribute__((packed)) foo { float f; }
5596 where we return the SFmode value of "f" in FP_RETURN, but where
5597 the structure itself has mode BLKmode. */
5600 mips_return_fpr_single (enum machine_mode type_mode,
5601 enum machine_mode value_mode)
5605 x = gen_rtx_REG (value_mode, FP_RETURN);
5606 if (type_mode != value_mode)
5608 x = gen_rtx_EXPR_LIST (VOIDmode, x, const0_rtx);
5609 x = gen_rtx_PARALLEL (type_mode, gen_rtvec (1, x));
5614 /* Return a composite value in a pair of floating-point registers.
5615 MODE1 and OFFSET1 are the mode and byte offset for the first value,
5616 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
5619 For n32 & n64, $f0 always holds the first value and $f2 the second.
5620 Otherwise the values are packed together as closely as possible. */
5623 mips_return_fpr_pair (enum machine_mode mode,
5624 enum machine_mode mode1, HOST_WIDE_INT offset1,
5625 enum machine_mode mode2, HOST_WIDE_INT offset2)
5629 inc = (TARGET_NEWABI ? 2 : MAX_FPRS_PER_FMT);
5630 return gen_rtx_PARALLEL
5633 gen_rtx_EXPR_LIST (VOIDmode,
5634 gen_rtx_REG (mode1, FP_RETURN),
5636 gen_rtx_EXPR_LIST (VOIDmode,
5637 gen_rtx_REG (mode2, FP_RETURN + inc),
5638 GEN_INT (offset2))));
5642 /* Implement TARGET_FUNCTION_VALUE and TARGET_LIBCALL_VALUE.
5643 For normal calls, VALTYPE is the return type and MODE is VOIDmode.
5644 For libcalls, VALTYPE is null and MODE is the mode of the return value. */
5647 mips_function_value_1 (const_tree valtype, const_tree fn_decl_or_type,
5648 enum machine_mode mode)
5656 if (fn_decl_or_type && DECL_P (fn_decl_or_type))
5657 func = fn_decl_or_type;
5661 mode = TYPE_MODE (valtype);
5662 unsigned_p = TYPE_UNSIGNED (valtype);
5664 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
5665 return values, promote the mode here too. */
5666 mode = promote_function_mode (valtype, mode, &unsigned_p, func, 1);
5668 /* Handle structures whose fields are returned in $f0/$f2. */
5669 switch (mips_fpr_return_fields (valtype, fields))
5672 return mips_return_fpr_single (mode,
5673 TYPE_MODE (TREE_TYPE (fields[0])));
5676 return mips_return_fpr_pair (mode,
5677 TYPE_MODE (TREE_TYPE (fields[0])),
5678 int_byte_position (fields[0]),
5679 TYPE_MODE (TREE_TYPE (fields[1])),
5680 int_byte_position (fields[1]));
5683 /* If a value is passed in the most significant part of a register, see
5684 whether we have to round the mode up to a whole number of words. */
5685 if (mips_return_in_msb (valtype))
5687 HOST_WIDE_INT size = int_size_in_bytes (valtype);
5688 if (size % UNITS_PER_WORD != 0)
5690 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
5691 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
5695 /* For EABI, the class of return register depends entirely on MODE.
5696 For example, "struct { some_type x; }" and "union { some_type x; }"
5697 are returned in the same way as a bare "some_type" would be.
5698 Other ABIs only use FPRs for scalar, complex or vector types. */
5699 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
5700 return gen_rtx_REG (mode, GP_RETURN);
5705 /* Handle long doubles for n32 & n64. */
5707 return mips_return_fpr_pair (mode,
5709 DImode, GET_MODE_SIZE (mode) / 2);
5711 if (mips_return_mode_in_fpr_p (mode))
5713 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5714 return mips_return_fpr_pair (mode,
5715 GET_MODE_INNER (mode), 0,
5716 GET_MODE_INNER (mode),
5717 GET_MODE_SIZE (mode) / 2);
5719 return gen_rtx_REG (mode, FP_RETURN);
5723 return gen_rtx_REG (mode, GP_RETURN);
5726 /* Implement TARGET_FUNCTION_VALUE. */
5729 mips_function_value (const_tree valtype, const_tree fn_decl_or_type,
5730 bool outgoing ATTRIBUTE_UNUSED)
5732 return mips_function_value_1 (valtype, fn_decl_or_type, VOIDmode);
5735 /* Implement TARGET_LIBCALL_VALUE. */
5738 mips_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
5740 return mips_function_value_1 (NULL_TREE, NULL_TREE, mode);
5743 /* Implement TARGET_FUNCTION_VALUE_REGNO_P.
5745 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
5746 Currently, R2 and F0 are only implemented here (C has no complex type). */
5749 mips_function_value_regno_p (const unsigned int regno)
5751 if (regno == GP_RETURN
5752 || regno == FP_RETURN
5753 || (LONG_DOUBLE_TYPE_SIZE == 128
5754 && FP_RETURN != GP_RETURN
5755 && regno == FP_RETURN + 2))
5761 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
5762 all BLKmode objects are returned in memory. Under the n32, n64
5763 and embedded ABIs, small structures are returned in a register.
5764 Objects with varying size must still be returned in memory, of
5768 mips_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
5770 return (TARGET_OLDABI
5771 ? TYPE_MODE (type) == BLKmode
5772 : !IN_RANGE (int_size_in_bytes (type), 0, 2 * UNITS_PER_WORD));
5775 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
5778 mips_setup_incoming_varargs (cumulative_args_t cum, enum machine_mode mode,
5779 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5782 CUMULATIVE_ARGS local_cum;
5783 int gp_saved, fp_saved;
5785 /* The caller has advanced CUM up to, but not beyond, the last named
5786 argument. Advance a local copy of CUM past the last "real" named
5787 argument, to find out how many registers are left over. */
5788 local_cum = *get_cumulative_args (cum);
5789 mips_function_arg_advance (pack_cumulative_args (&local_cum), mode, type,
5792 /* Found out how many registers we need to save. */
5793 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
5794 fp_saved = (EABI_FLOAT_VARARGS_P
5795 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
5804 ptr = plus_constant (Pmode, virtual_incoming_args_rtx,
5805 REG_PARM_STACK_SPACE (cfun->decl)
5806 - gp_saved * UNITS_PER_WORD);
5807 mem = gen_frame_mem (BLKmode, ptr);
5808 set_mem_alias_set (mem, get_varargs_alias_set ());
5810 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
5815 /* We can't use move_block_from_reg, because it will use
5817 enum machine_mode mode;
5820 /* Set OFF to the offset from virtual_incoming_args_rtx of
5821 the first float register. The FP save area lies below
5822 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
5823 off = (-gp_saved * UNITS_PER_WORD) & -UNITS_PER_FPVALUE;
5824 off -= fp_saved * UNITS_PER_FPREG;
5826 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
5828 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS;
5829 i += MAX_FPRS_PER_FMT)
5833 ptr = plus_constant (Pmode, virtual_incoming_args_rtx, off);
5834 mem = gen_frame_mem (mode, ptr);
5835 set_mem_alias_set (mem, get_varargs_alias_set ());
5836 mips_emit_move (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
5837 off += UNITS_PER_HWFPVALUE;
5841 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
5842 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
5843 + fp_saved * UNITS_PER_FPREG);
5846 /* Implement TARGET_BUILTIN_VA_LIST. */
5849 mips_build_builtin_va_list (void)
5851 if (EABI_FLOAT_VARARGS_P)
5853 /* We keep 3 pointers, and two offsets.
5855 Two pointers are to the overflow area, which starts at the CFA.
5856 One of these is constant, for addressing into the GPR save area
5857 below it. The other is advanced up the stack through the
5860 The third pointer is to the bottom of the GPR save area.
5861 Since the FPR save area is just below it, we can address
5862 FPR slots off this pointer.
5864 We also keep two one-byte offsets, which are to be subtracted
5865 from the constant pointers to yield addresses in the GPR and
5866 FPR save areas. These are downcounted as float or non-float
5867 arguments are used, and when they get to zero, the argument
5868 must be obtained from the overflow region. */
5869 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
5872 record = lang_hooks.types.make_type (RECORD_TYPE);
5874 f_ovfl = build_decl (BUILTINS_LOCATION,
5875 FIELD_DECL, get_identifier ("__overflow_argptr"),
5877 f_gtop = build_decl (BUILTINS_LOCATION,
5878 FIELD_DECL, get_identifier ("__gpr_top"),
5880 f_ftop = build_decl (BUILTINS_LOCATION,
5881 FIELD_DECL, get_identifier ("__fpr_top"),
5883 f_goff = build_decl (BUILTINS_LOCATION,
5884 FIELD_DECL, get_identifier ("__gpr_offset"),
5885 unsigned_char_type_node);
5886 f_foff = build_decl (BUILTINS_LOCATION,
5887 FIELD_DECL, get_identifier ("__fpr_offset"),
5888 unsigned_char_type_node);
5889 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
5890 warn on every user file. */
5891 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
5892 array = build_array_type (unsigned_char_type_node,
5893 build_index_type (index));
5894 f_res = build_decl (BUILTINS_LOCATION,
5895 FIELD_DECL, get_identifier ("__reserved"), array);
5897 DECL_FIELD_CONTEXT (f_ovfl) = record;
5898 DECL_FIELD_CONTEXT (f_gtop) = record;
5899 DECL_FIELD_CONTEXT (f_ftop) = record;
5900 DECL_FIELD_CONTEXT (f_goff) = record;
5901 DECL_FIELD_CONTEXT (f_foff) = record;
5902 DECL_FIELD_CONTEXT (f_res) = record;
5904 TYPE_FIELDS (record) = f_ovfl;
5905 DECL_CHAIN (f_ovfl) = f_gtop;
5906 DECL_CHAIN (f_gtop) = f_ftop;
5907 DECL_CHAIN (f_ftop) = f_goff;
5908 DECL_CHAIN (f_goff) = f_foff;
5909 DECL_CHAIN (f_foff) = f_res;
5911 layout_type (record);
5915 /* Otherwise, we use 'void *'. */
5916 return ptr_type_node;
5919 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
5922 mips_va_start (tree valist, rtx nextarg)
5924 if (EABI_FLOAT_VARARGS_P)
5926 const CUMULATIVE_ARGS *cum;
5927 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5928 tree ovfl, gtop, ftop, goff, foff;
5930 int gpr_save_area_size;
5931 int fpr_save_area_size;
5934 cum = &crtl->args.info;
5936 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
5938 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
5940 f_ovfl = TYPE_FIELDS (va_list_type_node);
5941 f_gtop = DECL_CHAIN (f_ovfl);
5942 f_ftop = DECL_CHAIN (f_gtop);
5943 f_goff = DECL_CHAIN (f_ftop);
5944 f_foff = DECL_CHAIN (f_goff);
5946 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5948 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
5950 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
5952 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
5954 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
5957 /* Emit code to initialize OVFL, which points to the next varargs
5958 stack argument. CUM->STACK_WORDS gives the number of stack
5959 words used by named arguments. */
5960 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
5961 if (cum->stack_words > 0)
5962 t = fold_build_pointer_plus_hwi (t, cum->stack_words * UNITS_PER_WORD);
5963 t = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
5964 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5966 /* Emit code to initialize GTOP, the top of the GPR save area. */
5967 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
5968 t = build2 (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
5969 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5971 /* Emit code to initialize FTOP, the top of the FPR save area.
5972 This address is gpr_save_area_bytes below GTOP, rounded
5973 down to the next fp-aligned boundary. */
5974 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
5975 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
5976 fpr_offset &= -UNITS_PER_FPVALUE;
5978 t = fold_build_pointer_plus_hwi (t, -fpr_offset);
5979 t = build2 (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
5980 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5982 /* Emit code to initialize GOFF, the offset from GTOP of the
5983 next GPR argument. */
5984 t = build2 (MODIFY_EXPR, TREE_TYPE (goff), goff,
5985 build_int_cst (TREE_TYPE (goff), gpr_save_area_size));
5986 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5988 /* Likewise emit code to initialize FOFF, the offset from FTOP
5989 of the next FPR argument. */
5990 t = build2 (MODIFY_EXPR, TREE_TYPE (foff), foff,
5991 build_int_cst (TREE_TYPE (foff), fpr_save_area_size));
5992 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5996 nextarg = plus_constant (Pmode, nextarg, -cfun->machine->varargs_size);
5997 std_expand_builtin_va_start (valist, nextarg);
6001 /* Like std_gimplify_va_arg_expr, but apply alignment to zero-sized
6005 mips_std_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
6008 tree addr, t, type_size, rounded_size, valist_tmp;
6009 unsigned HOST_WIDE_INT align, boundary;
6012 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, false);
6014 type = build_pointer_type (type);
6016 align = PARM_BOUNDARY / BITS_PER_UNIT;
6017 boundary = targetm.calls.function_arg_boundary (TYPE_MODE (type), type);
6019 /* When we align parameter on stack for caller, if the parameter
6020 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
6021 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
6022 here with caller. */
6023 if (boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
6024 boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
6026 boundary /= BITS_PER_UNIT;
6028 /* Hoist the valist value into a temporary for the moment. */
6029 valist_tmp = get_initialized_tmp_var (valist, pre_p, NULL);
6031 /* va_list pointer is aligned to PARM_BOUNDARY. If argument actually
6032 requires greater alignment, we must perform dynamic alignment. */
6033 if (boundary > align)
6035 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
6036 fold_build_pointer_plus_hwi (valist_tmp, boundary - 1));
6037 gimplify_and_add (t, pre_p);
6039 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
6040 fold_build2 (BIT_AND_EXPR, TREE_TYPE (valist),
6042 build_int_cst (TREE_TYPE (valist), -boundary)));
6043 gimplify_and_add (t, pre_p);
6048 /* If the actual alignment is less than the alignment of the type,
6049 adjust the type accordingly so that we don't assume strict alignment
6050 when dereferencing the pointer. */
6051 boundary *= BITS_PER_UNIT;
6052 if (boundary < TYPE_ALIGN (type))
6054 type = build_variant_type_copy (type);
6055 TYPE_ALIGN (type) = boundary;
6058 /* Compute the rounded size of the type. */
6059 type_size = size_in_bytes (type);
6060 rounded_size = round_up (type_size, align);
6062 /* Reduce rounded_size so it's sharable with the postqueue. */
6063 gimplify_expr (&rounded_size, pre_p, post_p, is_gimple_val, fb_rvalue);
6067 if (PAD_VARARGS_DOWN && !integer_zerop (rounded_size))
6069 /* Small args are padded downward. */
6070 t = fold_build2_loc (input_location, GT_EXPR, sizetype,
6071 rounded_size, size_int (align));
6072 t = fold_build3 (COND_EXPR, sizetype, t, size_zero_node,
6073 size_binop (MINUS_EXPR, rounded_size, type_size));
6074 addr = fold_build_pointer_plus (addr, t);
6077 /* Compute new value for AP. */
6078 t = fold_build_pointer_plus (valist_tmp, rounded_size);
6079 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
6080 gimplify_and_add (t, pre_p);
6082 addr = fold_convert (build_pointer_type (type), addr);
6085 addr = build_va_arg_indirect_ref (addr);
6087 return build_va_arg_indirect_ref (addr);
6090 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
6093 mips_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
6099 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
6101 type = build_pointer_type (type);
6103 if (!EABI_FLOAT_VARARGS_P)
6104 addr = mips_std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6107 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
6108 tree ovfl, top, off, align;
6109 HOST_WIDE_INT size, rsize, osize;
6112 f_ovfl = TYPE_FIELDS (va_list_type_node);
6113 f_gtop = DECL_CHAIN (f_ovfl);
6114 f_ftop = DECL_CHAIN (f_gtop);
6115 f_goff = DECL_CHAIN (f_ftop);
6116 f_foff = DECL_CHAIN (f_goff);
6120 TOP be the top of the GPR or FPR save area;
6121 OFF be the offset from TOP of the next register;
6122 ADDR_RTX be the address of the argument;
6123 SIZE be the number of bytes in the argument type;
6124 RSIZE be the number of bytes used to store the argument
6125 when it's in the register save area; and
6126 OSIZE be the number of bytes used to store it when it's
6127 in the stack overflow area.
6129 The code we want is:
6131 1: off &= -rsize; // round down
6134 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
6139 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
6140 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
6144 [1] and [9] can sometimes be optimized away. */
6146 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
6148 size = int_size_in_bytes (type);
6150 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
6151 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
6153 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop),
6154 unshare_expr (valist), f_ftop, NULL_TREE);
6155 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff),
6156 unshare_expr (valist), f_foff, NULL_TREE);
6158 /* When va_start saves FPR arguments to the stack, each slot
6159 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
6160 argument's precision. */
6161 rsize = UNITS_PER_HWFPVALUE;
6163 /* Overflow arguments are padded to UNITS_PER_WORD bytes
6164 (= PARM_BOUNDARY bits). This can be different from RSIZE
6167 (1) On 32-bit targets when TYPE is a structure such as:
6169 struct s { float f; };
6171 Such structures are passed in paired FPRs, so RSIZE
6172 will be 8 bytes. However, the structure only takes
6173 up 4 bytes of memory, so OSIZE will only be 4.
6175 (2) In combinations such as -mgp64 -msingle-float
6176 -fshort-double. Doubles passed in registers will then take
6177 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
6178 stack take up UNITS_PER_WORD bytes. */
6179 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
6183 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop),
6184 unshare_expr (valist), f_gtop, NULL_TREE);
6185 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff),
6186 unshare_expr (valist), f_goff, NULL_TREE);
6187 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
6188 if (rsize > UNITS_PER_WORD)
6190 /* [1] Emit code for: off &= -rsize. */
6191 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), unshare_expr (off),
6192 build_int_cst (TREE_TYPE (off), -rsize));
6193 gimplify_assign (unshare_expr (off), t, pre_p);
6198 /* [2] Emit code to branch if off == 0. */
6199 t = build2 (NE_EXPR, boolean_type_node, unshare_expr (off),
6200 build_int_cst (TREE_TYPE (off), 0));
6201 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
6203 /* [5] Emit code for: off -= rsize. We do this as a form of
6204 post-decrement not available to C. */
6205 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
6206 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
6208 /* [4] Emit code for:
6209 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
6210 t = fold_convert (sizetype, t);
6211 t = fold_build1 (NEGATE_EXPR, sizetype, t);
6212 t = fold_build_pointer_plus (top, t);
6213 if (BYTES_BIG_ENDIAN && rsize > size)
6214 t = fold_build_pointer_plus_hwi (t, rsize - size);
6215 COND_EXPR_THEN (addr) = t;
6217 if (osize > UNITS_PER_WORD)
6219 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
6220 t = fold_build_pointer_plus_hwi (unshare_expr (ovfl), osize - 1);
6221 u = build_int_cst (TREE_TYPE (t), -osize);
6222 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t, u);
6223 align = build2 (MODIFY_EXPR, TREE_TYPE (ovfl),
6224 unshare_expr (ovfl), t);
6229 /* [10, 11] Emit code for:
6230 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
6232 u = fold_convert (TREE_TYPE (ovfl), build_int_cst (NULL_TREE, osize));
6233 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
6234 if (BYTES_BIG_ENDIAN && osize > size)
6235 t = fold_build_pointer_plus_hwi (t, osize - size);
6237 /* String [9] and [10, 11] together. */
6239 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
6240 COND_EXPR_ELSE (addr) = t;
6242 addr = fold_convert (build_pointer_type (type), addr);
6243 addr = build_va_arg_indirect_ref (addr);
6247 addr = build_va_arg_indirect_ref (addr);
6252 /* Declare a unique, locally-binding function called NAME, then start
6256 mips_start_unique_function (const char *name)
6260 decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
6261 get_identifier (name),
6262 build_function_type_list (void_type_node, NULL_TREE));
6263 DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
6264 NULL_TREE, void_type_node);
6265 TREE_PUBLIC (decl) = 1;
6266 TREE_STATIC (decl) = 1;
6268 cgraph_node::create (decl)->set_comdat_group (DECL_ASSEMBLER_NAME (decl));
6270 targetm.asm_out.unique_section (decl, 0);
6271 switch_to_section (get_named_section (decl, NULL, 0));
6273 targetm.asm_out.globalize_label (asm_out_file, name);
6274 fputs ("\t.hidden\t", asm_out_file);
6275 assemble_name (asm_out_file, name);
6276 putc ('\n', asm_out_file);
6279 /* Start a definition of function NAME. MIPS16_P indicates whether the
6280 function contains MIPS16 code. */
6283 mips_start_function_definition (const char *name, bool mips16_p)
6286 fprintf (asm_out_file, "\t.set\tmips16\n");
6288 fprintf (asm_out_file, "\t.set\tnomips16\n");
6290 if (TARGET_MICROMIPS)
6291 fprintf (asm_out_file, "\t.set\tmicromips\n");
6292 #ifdef HAVE_GAS_MICROMIPS
6294 fprintf (asm_out_file, "\t.set\tnomicromips\n");
6297 if (!flag_inhibit_size_directive)
6299 fputs ("\t.ent\t", asm_out_file);
6300 assemble_name (asm_out_file, name);
6301 fputs ("\n", asm_out_file);
6304 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, name, "function");
6306 /* Start the definition proper. */
6307 assemble_name (asm_out_file, name);
6308 fputs (":\n", asm_out_file);
6311 /* End a function definition started by mips_start_function_definition. */
6314 mips_end_function_definition (const char *name)
6316 if (!flag_inhibit_size_directive)
6318 fputs ("\t.end\t", asm_out_file);
6319 assemble_name (asm_out_file, name);
6320 fputs ("\n", asm_out_file);
6324 /* If *STUB_PTR points to a stub, output a comdat-style definition for it,
6325 then free *STUB_PTR. */
6328 mips_finish_stub (mips_one_only_stub **stub_ptr)
6330 mips_one_only_stub *stub = *stub_ptr;
6334 const char *name = stub->get_name ();
6335 mips_start_unique_function (name);
6336 mips_start_function_definition (name, false);
6337 stub->output_body ();
6338 mips_end_function_definition (name);
6343 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
6346 mips_ok_for_lazy_binding_p (rtx x)
6348 return (TARGET_USE_GOT
6349 && GET_CODE (x) == SYMBOL_REF
6350 && !SYMBOL_REF_BIND_NOW_P (x)
6351 && !mips_symbol_binds_local_p (x));
6354 /* Load function address ADDR into register DEST. TYPE is as for
6355 mips_expand_call. Return true if we used an explicit lazy-binding
6359 mips_load_call_address (enum mips_call_type type, rtx dest, rtx addr)
6361 /* If we're generating PIC, and this call is to a global function,
6362 try to allow its address to be resolved lazily. This isn't
6363 possible for sibcalls when $gp is call-saved because the value
6364 of $gp on entry to the stub would be our caller's gp, not ours. */
6365 if (TARGET_EXPLICIT_RELOCS
6366 && !(type == MIPS_CALL_SIBCALL && TARGET_CALL_SAVED_GP)
6367 && mips_ok_for_lazy_binding_p (addr))
6369 addr = mips_got_load (dest, addr, SYMBOL_GOTOFF_CALL);
6370 emit_insn (gen_rtx_SET (VOIDmode, dest, addr));
6375 mips_emit_move (dest, addr);
6380 struct local_alias_traits : default_hashmap_traits
6382 static hashval_t hash (rtx);
6383 static bool equal_keys (rtx, rtx);
6386 /* Each locally-defined hard-float MIPS16 function has a local symbol
6387 associated with it. This hash table maps the function symbol (FUNC)
6388 to the local symbol (LOCAL). */
6389 static GTY (()) hash_map<rtx, rtx, local_alias_traits> *mips16_local_aliases;
6391 /* Hash table callbacks for mips16_local_aliases. */
6394 local_alias_traits::hash (rtx func)
6396 return htab_hash_string (XSTR (func, 0));
6400 local_alias_traits::equal_keys (rtx func1, rtx func2)
6402 return rtx_equal_p (func1, func2);
6405 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
6406 Return a local alias for it, creating a new one if necessary. */
6409 mips16_local_alias (rtx func)
6411 /* Create the hash table if this is the first call. */
6412 if (mips16_local_aliases == NULL)
6413 mips16_local_aliases
6414 = hash_map<rtx, rtx, local_alias_traits>::create_ggc (37);
6416 /* Look up the function symbol, creating a new entry if need be. */
6418 rtx *slot = &mips16_local_aliases->get_or_insert (func, &existed);
6419 gcc_assert (slot != NULL);
6423 const char *func_name, *local_name;
6426 /* Create a new SYMBOL_REF for the local symbol. The choice of
6427 __fn_local_* is based on the __fn_stub_* names that we've
6428 traditionally used for the non-MIPS16 stub. */
6429 func_name = targetm.strip_name_encoding (XSTR (func, 0));
6430 local_name = ACONCAT (("__fn_local_", func_name, NULL));
6431 local = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (local_name));
6432 SYMBOL_REF_FLAGS (local) = SYMBOL_REF_FLAGS (func) | SYMBOL_FLAG_LOCAL;
6434 /* Create a new structure to represent the mapping. */
6440 /* A chained list of functions for which mips16_build_call_stub has already
6441 generated a stub. NAME is the name of the function and FP_RET_P is true
6442 if the function returns a value in floating-point registers. */
6443 struct mips16_stub {
6444 struct mips16_stub *next;
6448 static struct mips16_stub *mips16_stubs;
6450 /* Return the two-character string that identifies floating-point
6451 return mode MODE in the name of a MIPS16 function stub. */
6454 mips16_call_stub_mode_suffix (enum machine_mode mode)
6458 else if (mode == DFmode)
6460 else if (mode == SCmode)
6462 else if (mode == DCmode)
6464 else if (mode == V2SFmode)
6470 /* Write instructions to move a 32-bit value between general register
6471 GPREG and floating-point register FPREG. DIRECTION is 't' to move
6472 from GPREG to FPREG and 'f' to move in the opposite direction. */
6475 mips_output_32bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
6477 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6478 reg_names[gpreg], reg_names[fpreg]);
6481 /* Likewise for 64-bit values. */
6484 mips_output_64bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
6487 fprintf (asm_out_file, "\tdm%cc1\t%s,%s\n", direction,
6488 reg_names[gpreg], reg_names[fpreg]);
6489 else if (TARGET_FLOAT64)
6491 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6492 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
6493 fprintf (asm_out_file, "\tm%chc1\t%s,%s\n", direction,
6494 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg]);
6498 /* Move the least-significant word. */
6499 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6500 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
6501 /* ...then the most significant word. */
6502 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6503 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg + 1]);
6507 /* Write out code to move floating-point arguments into or out of
6508 general registers. FP_CODE is the code describing which arguments
6509 are present (see the comment above the definition of CUMULATIVE_ARGS
6510 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
6513 mips_output_args_xfer (int fp_code, char direction)
6515 unsigned int gparg, fparg, f;
6516 CUMULATIVE_ARGS cum;
6518 /* This code only works for o32 and o64. */
6519 gcc_assert (TARGET_OLDABI);
6521 mips_init_cumulative_args (&cum, NULL);
6523 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
6525 enum machine_mode mode;
6526 struct mips_arg_info info;
6530 else if ((f & 3) == 2)
6535 mips_get_arg_info (&info, &cum, mode, NULL, true);
6536 gparg = mips_arg_regno (&info, false);
6537 fparg = mips_arg_regno (&info, true);
6540 mips_output_32bit_xfer (direction, gparg, fparg);
6542 mips_output_64bit_xfer (direction, gparg, fparg);
6544 mips_function_arg_advance (pack_cumulative_args (&cum), mode, NULL, true);
6548 /* Write a MIPS16 stub for the current function. This stub is used
6549 for functions which take arguments in the floating-point registers.
6550 It is normal-mode code that moves the floating-point arguments
6551 into the general registers and then jumps to the MIPS16 code. */
6554 mips16_build_function_stub (void)
6556 const char *fnname, *alias_name, *separator;
6557 char *secname, *stubname;
6562 /* Create the name of the stub, and its unique section. */
6563 symbol = XEXP (DECL_RTL (current_function_decl), 0);
6564 alias = mips16_local_alias (symbol);
6566 fnname = targetm.strip_name_encoding (XSTR (symbol, 0));
6567 alias_name = targetm.strip_name_encoding (XSTR (alias, 0));
6568 secname = ACONCAT ((".mips16.fn.", fnname, NULL));
6569 stubname = ACONCAT (("__fn_stub_", fnname, NULL));
6571 /* Build a decl for the stub. */
6572 stubdecl = build_decl (BUILTINS_LOCATION,
6573 FUNCTION_DECL, get_identifier (stubname),
6574 build_function_type_list (void_type_node, NULL_TREE));
6575 set_decl_section_name (stubdecl, secname);
6576 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
6577 RESULT_DECL, NULL_TREE, void_type_node);
6579 /* Output a comment. */
6580 fprintf (asm_out_file, "\t# Stub function for %s (",
6581 current_function_name ());
6583 for (f = (unsigned int) crtl->args.info.fp_code; f != 0; f >>= 2)
6585 fprintf (asm_out_file, "%s%s", separator,
6586 (f & 3) == 1 ? "float" : "double");
6589 fprintf (asm_out_file, ")\n");
6591 /* Start the function definition. */
6592 assemble_start_function (stubdecl, stubname);
6593 mips_start_function_definition (stubname, false);
6595 /* If generating pic2 code, either set up the global pointer or
6597 if (TARGET_ABICALLS_PIC2)
6599 if (TARGET_ABSOLUTE_ABICALLS)
6600 fprintf (asm_out_file, "\t.option\tpic0\n");
6603 output_asm_insn ("%(.cpload\t%^%)", NULL);
6604 /* Emit an R_MIPS_NONE relocation to tell the linker what the
6605 target function is. Use a local GOT access when loading the
6606 symbol, to cut down on the number of unnecessary GOT entries
6607 for stubs that aren't needed. */
6608 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol);
6613 /* Load the address of the MIPS16 function into $25. Do this first so
6614 that targets with coprocessor interlocks can use an MFC1 to fill the
6616 output_asm_insn ("la\t%^,%0", &symbol);
6618 /* Move the arguments from floating-point registers to general registers. */
6619 mips_output_args_xfer (crtl->args.info.fp_code, 'f');
6621 /* Jump to the MIPS16 function. */
6622 output_asm_insn ("jr\t%^", NULL);
6624 if (TARGET_ABICALLS_PIC2 && TARGET_ABSOLUTE_ABICALLS)
6625 fprintf (asm_out_file, "\t.option\tpic2\n");
6627 mips_end_function_definition (stubname);
6629 /* If the linker needs to create a dynamic symbol for the target
6630 function, it will associate the symbol with the stub (which,
6631 unlike the target function, follows the proper calling conventions).
6632 It is therefore useful to have a local alias for the target function,
6633 so that it can still be identified as MIPS16 code. As an optimization,
6634 this symbol can also be used for indirect MIPS16 references from
6635 within this file. */
6636 ASM_OUTPUT_DEF (asm_out_file, alias_name, fnname);
6638 switch_to_section (function_section (current_function_decl));
6641 /* The current function is a MIPS16 function that returns a value in an FPR.
6642 Copy the return value from its soft-float to its hard-float location.
6643 libgcc2 has special non-MIPS16 helper functions for each case. */
6646 mips16_copy_fpr_return_value (void)
6648 rtx fn, insn, retval;
6650 enum machine_mode return_mode;
6653 return_type = DECL_RESULT (current_function_decl);
6654 return_mode = DECL_MODE (return_type);
6656 name = ACONCAT (("__mips16_ret_",
6657 mips16_call_stub_mode_suffix (return_mode),
6659 fn = mips16_stub_function (name);
6661 /* The function takes arguments in $2 (and possibly $3), so calls
6662 to it cannot be lazily bound. */
6663 SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_BIND_NOW;
6665 /* Model the call as something that takes the GPR return value as
6666 argument and returns an "updated" value. */
6667 retval = gen_rtx_REG (return_mode, GP_RETURN);
6668 insn = mips_expand_call (MIPS_CALL_EPILOGUE, retval, fn,
6669 const0_rtx, NULL_RTX, false);
6670 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), retval);
6673 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
6674 RETVAL is the location of the return value, or null if this is
6675 a "call" rather than a "call_value". ARGS_SIZE is the size of the
6676 arguments and FP_CODE is the code built by mips_function_arg;
6677 see the comment before the fp_code field in CUMULATIVE_ARGS for details.
6679 There are three alternatives:
6681 - If a stub was needed, emit the call and return the call insn itself.
6683 - If we can avoid using a stub by redirecting the call, set *FN_PTR
6684 to the new target and return null.
6686 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
6689 A stub is needed for calls to functions that, in normal mode,
6690 receive arguments in FPRs or return values in FPRs. The stub
6691 copies the arguments from their soft-float positions to their
6692 hard-float positions, calls the real function, then copies the
6693 return value from its hard-float position to its soft-float
6696 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
6697 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
6698 automatically redirects the JAL to the stub, otherwise the JAL
6699 continues to call FN directly. */
6702 mips16_build_call_stub (rtx retval, rtx *fn_ptr, rtx args_size, int fp_code)
6706 struct mips16_stub *l;
6710 /* We don't need to do anything if we aren't in MIPS16 mode, or if
6711 we were invoked with the -msoft-float option. */
6712 if (!TARGET_MIPS16 || TARGET_SOFT_FLOAT_ABI)
6715 /* Figure out whether the value might come back in a floating-point
6717 fp_ret_p = retval && mips_return_mode_in_fpr_p (GET_MODE (retval));
6719 /* We don't need to do anything if there were no floating-point
6720 arguments and the value will not be returned in a floating-point
6722 if (fp_code == 0 && !fp_ret_p)
6725 /* We don't need to do anything if this is a call to a special
6726 MIPS16 support function. */
6728 if (mips16_stub_function_p (fn))
6731 /* If we're calling a locally-defined MIPS16 function, we know that
6732 it will return values in both the "soft-float" and "hard-float"
6733 registers. There is no need to use a stub to move the latter
6735 if (fp_code == 0 && mips16_local_function_p (fn))
6738 /* This code will only work for o32 and o64 abis. The other ABI's
6739 require more sophisticated support. */
6740 gcc_assert (TARGET_OLDABI);
6742 /* If we're calling via a function pointer, use one of the magic
6743 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
6744 Each stub expects the function address to arrive in register $2. */
6745 if (GET_CODE (fn) != SYMBOL_REF
6746 || !call_insn_operand (fn, VOIDmode))
6753 /* If this is a locally-defined and locally-binding function,
6754 avoid the stub by calling the local alias directly. */
6755 if (mips16_local_function_p (fn))
6757 *fn_ptr = mips16_local_alias (fn);
6761 /* Create a SYMBOL_REF for the libgcc.a function. */
6763 sprintf (buf, "__mips16_call_stub_%s_%d",
6764 mips16_call_stub_mode_suffix (GET_MODE (retval)),
6767 sprintf (buf, "__mips16_call_stub_%d", fp_code);
6768 stub_fn = mips16_stub_function (buf);
6770 /* The function uses $2 as an argument, so calls to it
6771 cannot be lazily bound. */
6772 SYMBOL_REF_FLAGS (stub_fn) |= SYMBOL_FLAG_BIND_NOW;
6774 /* Load the target function into $2. */
6775 addr = gen_rtx_REG (Pmode, GP_REG_FIRST + 2);
6776 lazy_p = mips_load_call_address (MIPS_CALL_NORMAL, addr, fn);
6778 /* Emit the call. */
6779 insn = mips_expand_call (MIPS_CALL_NORMAL, retval, stub_fn,
6780 args_size, NULL_RTX, lazy_p);
6782 /* Tell GCC that this call does indeed use the value of $2. */
6783 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), addr);
6785 /* If we are handling a floating-point return value, we need to
6786 save $18 in the function prologue. Putting a note on the
6787 call will mean that df_regs_ever_live_p ($18) will be true if the
6788 call is not eliminated, and we can check that in the prologue
6791 CALL_INSN_FUNCTION_USAGE (insn) =
6792 gen_rtx_EXPR_LIST (VOIDmode,
6793 gen_rtx_CLOBBER (VOIDmode,
6794 gen_rtx_REG (word_mode, 18)),
6795 CALL_INSN_FUNCTION_USAGE (insn));
6800 /* We know the function we are going to call. If we have already
6801 built a stub, we don't need to do anything further. */
6802 fnname = targetm.strip_name_encoding (XSTR (fn, 0));
6803 for (l = mips16_stubs; l != NULL; l = l->next)
6804 if (strcmp (l->name, fnname) == 0)
6809 const char *separator;
6810 char *secname, *stubname;
6811 tree stubid, stubdecl;
6814 /* If the function does not return in FPRs, the special stub
6818 If the function does return in FPRs, the stub section is named
6819 .mips16.call.fp.FNNAME
6821 Build a decl for the stub. */
6822 secname = ACONCAT ((".mips16.call.", fp_ret_p ? "fp." : "",
6824 stubname = ACONCAT (("__call_stub_", fp_ret_p ? "fp_" : "",
6826 stubid = get_identifier (stubname);
6827 stubdecl = build_decl (BUILTINS_LOCATION,
6828 FUNCTION_DECL, stubid,
6829 build_function_type_list (void_type_node,
6831 set_decl_section_name (stubdecl, secname);
6832 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
6833 RESULT_DECL, NULL_TREE,
6836 /* Output a comment. */
6837 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
6839 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
6843 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
6845 fprintf (asm_out_file, "%s%s", separator,
6846 (f & 3) == 1 ? "float" : "double");
6849 fprintf (asm_out_file, ")\n");
6851 /* Start the function definition. */
6852 assemble_start_function (stubdecl, stubname);
6853 mips_start_function_definition (stubname, false);
6857 fprintf (asm_out_file, "\t.cfi_startproc\n");
6859 /* Create a fake CFA 4 bytes below the stack pointer.
6860 This works around unwinders (like libgcc's) that expect
6861 the CFA for non-signal frames to be unique. */
6862 fprintf (asm_out_file, "\t.cfi_def_cfa 29,-4\n");
6864 /* "Save" $sp in itself so we don't use the fake CFA.
6865 This is: DW_CFA_val_expression r29, { DW_OP_reg29 }. */
6866 fprintf (asm_out_file, "\t.cfi_escape 0x16,29,1,0x6d\n");
6870 /* Load the address of the MIPS16 function into $25. Do this
6871 first so that targets with coprocessor interlocks can use
6872 an MFC1 to fill the delay slot. */
6873 if (TARGET_EXPLICIT_RELOCS)
6875 output_asm_insn ("lui\t%^,%%hi(%0)", &fn);
6876 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn);
6879 output_asm_insn ("la\t%^,%0", &fn);
6882 /* Move the arguments from general registers to floating-point
6884 mips_output_args_xfer (fp_code, 't');
6888 /* Save the return address in $18 and call the non-MIPS16 function.
6889 The stub's caller knows that $18 might be clobbered, even though
6890 $18 is usually a call-saved register. */
6891 fprintf (asm_out_file, "\tmove\t%s,%s\n",
6892 reg_names[GP_REG_FIRST + 18], reg_names[RETURN_ADDR_REGNUM]);
6893 output_asm_insn (MIPS_CALL ("jal", &fn, 0, -1), &fn);
6894 fprintf (asm_out_file, "\t.cfi_register 31,18\n");
6896 /* Move the result from floating-point registers to
6897 general registers. */
6898 switch (GET_MODE (retval))
6901 mips_output_32bit_xfer ('f', GP_RETURN + TARGET_BIG_ENDIAN,
6903 ? FP_REG_FIRST + MAX_FPRS_PER_FMT
6905 mips_output_32bit_xfer ('f', GP_RETURN + TARGET_LITTLE_ENDIAN,
6906 TARGET_LITTLE_ENDIAN
6907 ? FP_REG_FIRST + MAX_FPRS_PER_FMT
6909 if (GET_MODE (retval) == SCmode && TARGET_64BIT)
6911 /* On 64-bit targets, complex floats are returned in
6912 a single GPR, such that "sd" on a suitably-aligned
6913 target would store the value correctly. */
6914 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
6915 reg_names[GP_RETURN + TARGET_BIG_ENDIAN],
6916 reg_names[GP_RETURN + TARGET_BIG_ENDIAN]);
6917 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
6918 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN],
6919 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN]);
6920 fprintf (asm_out_file, "\tdsrl\t%s,%s,32\n",
6921 reg_names[GP_RETURN + TARGET_BIG_ENDIAN],
6922 reg_names[GP_RETURN + TARGET_BIG_ENDIAN]);
6923 fprintf (asm_out_file, "\tor\t%s,%s,%s\n",
6924 reg_names[GP_RETURN],
6925 reg_names[GP_RETURN],
6926 reg_names[GP_RETURN + 1]);
6931 mips_output_32bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6935 mips_output_64bit_xfer ('f', GP_RETURN + (8 / UNITS_PER_WORD),
6936 FP_REG_FIRST + MAX_FPRS_PER_FMT);
6940 mips_output_64bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6946 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 18]);
6947 fprintf (asm_out_file, "\t.cfi_endproc\n");
6951 /* Jump to the previously-loaded address. */
6952 output_asm_insn ("jr\t%^", NULL);
6955 #ifdef ASM_DECLARE_FUNCTION_SIZE
6956 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
6959 mips_end_function_definition (stubname);
6961 /* Record this stub. */
6962 l = XNEW (struct mips16_stub);
6963 l->name = xstrdup (fnname);
6964 l->fp_ret_p = fp_ret_p;
6965 l->next = mips16_stubs;
6969 /* If we expect a floating-point return value, but we've built a
6970 stub which does not expect one, then we're in trouble. We can't
6971 use the existing stub, because it won't handle the floating-point
6972 value. We can't build a new stub, because the linker won't know
6973 which stub to use for the various calls in this object file.
6974 Fortunately, this case is illegal, since it means that a function
6975 was declared in two different ways in a single compilation. */
6976 if (fp_ret_p && !l->fp_ret_p)
6977 error ("cannot handle inconsistent calls to %qs", fnname);
6979 if (retval == NULL_RTX)
6980 pattern = gen_call_internal_direct (fn, args_size);
6982 pattern = gen_call_value_internal_direct (retval, fn, args_size);
6983 insn = mips_emit_call_insn (pattern, fn, fn, false);
6985 /* If we are calling a stub which handles a floating-point return
6986 value, we need to arrange to save $18 in the prologue. We do this
6987 by marking the function call as using the register. The prologue
6988 will later see that it is used, and emit code to save it. */
6990 CALL_INSN_FUNCTION_USAGE (insn) =
6991 gen_rtx_EXPR_LIST (VOIDmode,
6992 gen_rtx_CLOBBER (VOIDmode,
6993 gen_rtx_REG (word_mode, 18)),
6994 CALL_INSN_FUNCTION_USAGE (insn));
6999 /* Expand a call of type TYPE. RESULT is where the result will go (null
7000 for "call"s and "sibcall"s), ADDR is the address of the function,
7001 ARGS_SIZE is the size of the arguments and AUX is the value passed
7002 to us by mips_function_arg. LAZY_P is true if this call already
7003 involves a lazily-bound function address (such as when calling
7004 functions through a MIPS16 hard-float stub).
7006 Return the call itself. */
7009 mips_expand_call (enum mips_call_type type, rtx result, rtx addr,
7010 rtx args_size, rtx aux, bool lazy_p)
7012 rtx orig_addr, pattern;
7016 fp_code = aux == 0 ? 0 : (int) GET_MODE (aux);
7017 insn = mips16_build_call_stub (result, &addr, args_size, fp_code);
7020 gcc_assert (!lazy_p && type == MIPS_CALL_NORMAL);
7025 if (!call_insn_operand (addr, VOIDmode))
7027 if (type == MIPS_CALL_EPILOGUE)
7028 addr = MIPS_EPILOGUE_TEMP (Pmode);
7030 addr = gen_reg_rtx (Pmode);
7031 lazy_p |= mips_load_call_address (type, addr, orig_addr);
7036 rtx (*fn) (rtx, rtx);
7038 if (type == MIPS_CALL_SIBCALL)
7039 fn = gen_sibcall_internal;
7041 fn = gen_call_internal;
7043 pattern = fn (addr, args_size);
7045 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
7047 /* Handle return values created by mips_return_fpr_pair. */
7048 rtx (*fn) (rtx, rtx, rtx, rtx);
7051 if (type == MIPS_CALL_SIBCALL)
7052 fn = gen_sibcall_value_multiple_internal;
7054 fn = gen_call_value_multiple_internal;
7056 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
7057 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
7058 pattern = fn (reg1, addr, args_size, reg2);
7062 rtx (*fn) (rtx, rtx, rtx);
7064 if (type == MIPS_CALL_SIBCALL)
7065 fn = gen_sibcall_value_internal;
7067 fn = gen_call_value_internal;
7069 /* Handle return values created by mips_return_fpr_single. */
7070 if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 1)
7071 result = XEXP (XVECEXP (result, 0, 0), 0);
7072 pattern = fn (result, addr, args_size);
7075 return mips_emit_call_insn (pattern, orig_addr, addr, lazy_p);
7078 /* Split call instruction INSN into a $gp-clobbering call and
7079 (where necessary) an instruction to restore $gp from its save slot.
7080 CALL_PATTERN is the pattern of the new call. */
7083 mips_split_call (rtx insn, rtx call_pattern)
7085 emit_call_insn (call_pattern);
7086 if (!find_reg_note (insn, REG_NORETURN, 0))
7087 mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode,
7088 POST_CALL_TMP_REG));
7091 /* Return true if a call to DECL may need to use JALX. */
7094 mips_call_may_need_jalx_p (tree decl)
7096 /* If the current translation unit would use a different mode for DECL,
7097 assume that the call needs JALX. */
7098 if (mips_get_compress_mode (decl) != TARGET_COMPRESSION)
7101 /* mips_get_compress_mode is always accurate for locally-binding
7102 functions in the current translation unit. */
7103 if (!DECL_EXTERNAL (decl) && targetm.binds_local_p (decl))
7106 /* When -minterlink-compressed is in effect, assume that functions
7107 could use a different encoding mode unless an attribute explicitly
7108 tells us otherwise. */
7109 if (TARGET_INTERLINK_COMPRESSED)
7111 if (!TARGET_COMPRESSION
7112 && mips_get_compress_off_flags (DECL_ATTRIBUTES (decl)) ==0)
7114 if (TARGET_COMPRESSION
7115 && mips_get_compress_on_flags (DECL_ATTRIBUTES (decl)) == 0)
7122 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
7125 mips_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
7127 if (!TARGET_SIBCALLS)
7130 /* Interrupt handlers need special epilogue code and therefore can't
7132 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
7135 /* Direct Js are only possible to functions that use the same ISA encoding.
7136 There is no JX counterpoart of JALX. */
7138 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode)
7139 && mips_call_may_need_jalx_p (decl))
7142 /* Sibling calls should not prevent lazy binding. Lazy-binding stubs
7143 require $gp to be valid on entry, so sibcalls can only use stubs
7144 if $gp is call-clobbered. */
7146 && TARGET_CALL_SAVED_GP
7147 && !TARGET_ABICALLS_PIC0
7148 && !targetm.binds_local_p (decl))
7155 /* Implement MOVE_BY_PIECES_P. */
7158 mips_move_by_pieces_p (unsigned HOST_WIDE_INT size, unsigned int align)
7162 /* movmemsi is meant to generate code that is at least as good as
7163 move_by_pieces. However, movmemsi effectively uses a by-pieces
7164 implementation both for moves smaller than a word and for
7165 word-aligned moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT
7166 bytes. We should allow the tree-level optimisers to do such
7167 moves by pieces, as it often exposes other optimization
7168 opportunities. We might as well continue to use movmemsi at
7169 the rtl level though, as it produces better code when
7170 scheduling is disabled (such as at -O). */
7171 if (currently_expanding_to_rtl)
7173 if (align < BITS_PER_WORD)
7174 return size < UNITS_PER_WORD;
7175 return size <= MIPS_MAX_MOVE_BYTES_STRAIGHT;
7177 /* The default value. If this becomes a target hook, we should
7178 call the default definition instead. */
7179 return (move_by_pieces_ninsns (size, align, MOVE_MAX_PIECES + 1)
7180 < (unsigned int) MOVE_RATIO (optimize_insn_for_speed_p ()));
7183 /* Implement STORE_BY_PIECES_P. */
7186 mips_store_by_pieces_p (unsigned HOST_WIDE_INT size, unsigned int align)
7188 /* Storing by pieces involves moving constants into registers
7189 of size MIN (ALIGN, BITS_PER_WORD), then storing them.
7190 We need to decide whether it is cheaper to load the address of
7191 constant data into a register and use a block move instead. */
7193 /* If the data is only byte aligned, then:
7195 (a1) A block move of less than 4 bytes would involve three 3 LBs and
7196 3 SBs. We might as well use 3 single-instruction LIs and 3 SBs
7199 (a2) A block move of 4 bytes from aligned source data can use an
7200 LW/SWL/SWR sequence. This is often better than the 4 LIs and
7201 4 SBs that we would generate when storing by pieces. */
7202 if (align <= BITS_PER_UNIT)
7205 /* If the data is 2-byte aligned, then:
7207 (b1) A block move of less than 4 bytes would use a combination of LBs,
7208 LHs, SBs and SHs. We get better code by using single-instruction
7209 LIs, SBs and SHs instead.
7211 (b2) A block move of 4 bytes from aligned source data would again use
7212 an LW/SWL/SWR sequence. In most cases, loading the address of
7213 the source data would require at least one extra instruction.
7214 It is often more efficient to use 2 single-instruction LIs and
7217 (b3) A block move of up to 3 additional bytes would be like (b1).
7219 (b4) A block move of 8 bytes from aligned source data can use two
7220 LW/SWL/SWR sequences or a single LD/SDL/SDR sequence. Both
7221 sequences are better than the 4 LIs and 4 SHs that we'd generate
7222 when storing by pieces.
7224 The reasoning for higher alignments is similar:
7226 (c1) A block move of less than 4 bytes would be the same as (b1).
7228 (c2) A block move of 4 bytes would use an LW/SW sequence. Again,
7229 loading the address of the source data would typically require
7230 at least one extra instruction. It is generally better to use
7233 (c3) A block move of up to 3 additional bytes would be like (b1).
7235 (c4) A block move of 8 bytes can use two LW/SW sequences or a single
7236 LD/SD sequence, and in these cases we've traditionally preferred
7237 the memory copy over the more bulky constant moves. */
7241 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
7242 Assume that the areas do not overlap. */
7245 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
7247 HOST_WIDE_INT offset, delta;
7248 unsigned HOST_WIDE_INT bits;
7250 enum machine_mode mode;
7253 /* Work out how many bits to move at a time. If both operands have
7254 half-word alignment, it is usually better to move in half words.
7255 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
7256 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
7257 Otherwise move word-sized chunks. */
7258 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
7259 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
7260 bits = BITS_PER_WORD / 2;
7262 bits = BITS_PER_WORD;
7264 mode = mode_for_size (bits, MODE_INT, 0);
7265 delta = bits / BITS_PER_UNIT;
7267 /* Allocate a buffer for the temporary registers. */
7268 regs = XALLOCAVEC (rtx, length / delta);
7270 /* Load as many BITS-sized chunks as possible. Use a normal load if
7271 the source has enough alignment, otherwise use left/right pairs. */
7272 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
7274 regs[i] = gen_reg_rtx (mode);
7275 if (MEM_ALIGN (src) >= bits)
7276 mips_emit_move (regs[i], adjust_address (src, mode, offset));
7279 rtx part = adjust_address (src, BLKmode, offset);
7280 set_mem_size (part, delta);
7281 if (!mips_expand_ext_as_unaligned_load (regs[i], part, bits, 0, 0))
7286 /* Copy the chunks to the destination. */
7287 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
7288 if (MEM_ALIGN (dest) >= bits)
7289 mips_emit_move (adjust_address (dest, mode, offset), regs[i]);
7292 rtx part = adjust_address (dest, BLKmode, offset);
7293 set_mem_size (part, delta);
7294 if (!mips_expand_ins_as_unaligned_store (part, regs[i], bits, 0))
7298 /* Mop up any left-over bytes. */
7299 if (offset < length)
7301 src = adjust_address (src, BLKmode, offset);
7302 dest = adjust_address (dest, BLKmode, offset);
7303 move_by_pieces (dest, src, length - offset,
7304 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
7308 /* Helper function for doing a loop-based block operation on memory
7309 reference MEM. Each iteration of the loop will operate on LENGTH
7312 Create a new base register for use within the loop and point it to
7313 the start of MEM. Create a new memory reference that uses this
7314 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
7317 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
7318 rtx *loop_reg, rtx *loop_mem)
7320 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
7322 /* Although the new mem does not refer to a known location,
7323 it does keep up to LENGTH bytes of alignment. */
7324 *loop_mem = change_address (mem, BLKmode, *loop_reg);
7325 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
7328 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
7329 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
7330 the memory regions do not overlap. */
7333 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length,
7334 HOST_WIDE_INT bytes_per_iter)
7336 rtx_code_label *label;
7337 rtx src_reg, dest_reg, final_src, test;
7338 HOST_WIDE_INT leftover;
7340 leftover = length % bytes_per_iter;
7343 /* Create registers and memory references for use within the loop. */
7344 mips_adjust_block_mem (src, bytes_per_iter, &src_reg, &src);
7345 mips_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest);
7347 /* Calculate the value that SRC_REG should have after the last iteration
7349 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
7352 /* Emit the start of the loop. */
7353 label = gen_label_rtx ();
7356 /* Emit the loop body. */
7357 mips_block_move_straight (dest, src, bytes_per_iter);
7359 /* Move on to the next block. */
7360 mips_emit_move (src_reg, plus_constant (Pmode, src_reg, bytes_per_iter));
7361 mips_emit_move (dest_reg, plus_constant (Pmode, dest_reg, bytes_per_iter));
7363 /* Emit the loop condition. */
7364 test = gen_rtx_NE (VOIDmode, src_reg, final_src);
7365 if (Pmode == DImode)
7366 emit_jump_insn (gen_cbranchdi4 (test, src_reg, final_src, label));
7368 emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label));
7370 /* Mop up any left-over bytes. */
7372 mips_block_move_straight (dest, src, leftover);
7375 /* Expand a movmemsi instruction, which copies LENGTH bytes from
7376 memory reference SRC to memory reference DEST. */
7379 mips_expand_block_move (rtx dest, rtx src, rtx length)
7381 if (CONST_INT_P (length))
7383 if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)
7385 mips_block_move_straight (dest, src, INTVAL (length));
7390 mips_block_move_loop (dest, src, INTVAL (length),
7391 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER);
7398 /* Expand a loop of synci insns for the address range [BEGIN, END). */
7401 mips_expand_synci_loop (rtx begin, rtx end)
7403 rtx inc, cmp_result, mask, length;
7404 rtx_code_label *label, *end_label;
7406 /* Create end_label. */
7407 end_label = gen_label_rtx ();
7409 /* Check if begin equals end. */
7410 cmp_result = gen_rtx_EQ (VOIDmode, begin, end);
7411 emit_jump_insn (gen_condjump (cmp_result, end_label));
7413 /* Load INC with the cache line size (rdhwr INC,$1). */
7414 inc = gen_reg_rtx (Pmode);
7415 emit_insn (PMODE_INSN (gen_rdhwr_synci_step, (inc)));
7417 /* Check if inc is 0. */
7418 cmp_result = gen_rtx_EQ (VOIDmode, inc, const0_rtx);
7419 emit_jump_insn (gen_condjump (cmp_result, end_label));
7421 /* Calculate mask. */
7422 mask = mips_force_unary (Pmode, NEG, inc);
7424 /* Mask out begin by mask. */
7425 begin = mips_force_binary (Pmode, AND, begin, mask);
7427 /* Calculate length. */
7428 length = mips_force_binary (Pmode, MINUS, end, begin);
7430 /* Loop back to here. */
7431 label = gen_label_rtx ();
7434 emit_insn (gen_synci (begin));
7436 /* Update length. */
7437 mips_emit_binary (MINUS, length, length, inc);
7440 mips_emit_binary (PLUS, begin, begin, inc);
7442 /* Check if length is greater than 0. */
7443 cmp_result = gen_rtx_GT (VOIDmode, length, const0_rtx);
7444 emit_jump_insn (gen_condjump (cmp_result, label));
7446 emit_label (end_label);
7449 /* Expand a QI or HI mode atomic memory operation.
7451 GENERATOR contains a pointer to the gen_* function that generates
7452 the SI mode underlying atomic operation using masks that we
7455 RESULT is the return register for the operation. Its value is NULL
7458 MEM is the location of the atomic access.
7460 OLDVAL is the first operand for the operation.
7462 NEWVAL is the optional second operand for the operation. Its value
7463 is NULL if unused. */
7466 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator,
7467 rtx result, rtx mem, rtx oldval, rtx newval)
7469 rtx orig_addr, memsi_addr, memsi, shift, shiftsi, unshifted_mask;
7470 rtx unshifted_mask_reg, mask, inverted_mask, si_op;
7472 enum machine_mode mode;
7474 mode = GET_MODE (mem);
7476 /* Compute the address of the containing SImode value. */
7477 orig_addr = force_reg (Pmode, XEXP (mem, 0));
7478 memsi_addr = mips_force_binary (Pmode, AND, orig_addr,
7479 force_reg (Pmode, GEN_INT (-4)));
7481 /* Create a memory reference for it. */
7482 memsi = gen_rtx_MEM (SImode, memsi_addr);
7483 set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER);
7484 MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem);
7486 /* Work out the byte offset of the QImode or HImode value,
7487 counting from the least significant byte. */
7488 shift = mips_force_binary (Pmode, AND, orig_addr, GEN_INT (3));
7489 if (TARGET_BIG_ENDIAN)
7490 mips_emit_binary (XOR, shift, shift, GEN_INT (mode == QImode ? 3 : 2));
7492 /* Multiply by eight to convert the shift value from bytes to bits. */
7493 mips_emit_binary (ASHIFT, shift, shift, GEN_INT (3));
7495 /* Make the final shift an SImode value, so that it can be used in
7496 SImode operations. */
7497 shiftsi = force_reg (SImode, gen_lowpart (SImode, shift));
7499 /* Set MASK to an inclusive mask of the QImode or HImode value. */
7500 unshifted_mask = GEN_INT (GET_MODE_MASK (mode));
7501 unshifted_mask_reg = force_reg (SImode, unshifted_mask);
7502 mask = mips_force_binary (SImode, ASHIFT, unshifted_mask_reg, shiftsi);
7504 /* Compute the equivalent exclusive mask. */
7505 inverted_mask = gen_reg_rtx (SImode);
7506 emit_insn (gen_rtx_SET (VOIDmode, inverted_mask,
7507 gen_rtx_NOT (SImode, mask)));
7509 /* Shift the old value into place. */
7510 if (oldval != const0_rtx)
7512 oldval = convert_modes (SImode, mode, oldval, true);
7513 oldval = force_reg (SImode, oldval);
7514 oldval = mips_force_binary (SImode, ASHIFT, oldval, shiftsi);
7517 /* Do the same for the new value. */
7518 if (newval && newval != const0_rtx)
7520 newval = convert_modes (SImode, mode, newval, true);
7521 newval = force_reg (SImode, newval);
7522 newval = mips_force_binary (SImode, ASHIFT, newval, shiftsi);
7525 /* Do the SImode atomic access. */
7527 res = gen_reg_rtx (SImode);
7529 si_op = generator.fn_6 (res, memsi, mask, inverted_mask, oldval, newval);
7531 si_op = generator.fn_5 (res, memsi, mask, inverted_mask, oldval);
7533 si_op = generator.fn_4 (memsi, mask, inverted_mask, oldval);
7539 /* Shift and convert the result. */
7540 mips_emit_binary (AND, res, res, mask);
7541 mips_emit_binary (LSHIFTRT, res, res, shiftsi);
7542 mips_emit_move (result, gen_lowpart (GET_MODE (result), res));
7546 /* Return true if it is possible to use left/right accesses for a
7547 bitfield of WIDTH bits starting BITPOS bits into BLKmode memory OP.
7548 When returning true, update *LEFT and *RIGHT as follows:
7550 *LEFT is a QImode reference to the first byte if big endian or
7551 the last byte if little endian. This address can be used in the
7552 left-side instructions (LWL, SWL, LDL, SDL).
7554 *RIGHT is a QImode reference to the opposite end of the field and
7555 can be used in the patterning right-side instruction. */
7558 mips_get_unaligned_mem (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos,
7559 rtx *left, rtx *right)
7563 /* Check that the size is valid. */
7564 if (width != 32 && (!TARGET_64BIT || width != 64))
7567 /* We can only access byte-aligned values. Since we are always passed
7568 a reference to the first byte of the field, it is not necessary to
7569 do anything with BITPOS after this check. */
7570 if (bitpos % BITS_PER_UNIT != 0)
7573 /* Reject aligned bitfields: we want to use a normal load or store
7574 instead of a left/right pair. */
7575 if (MEM_ALIGN (op) >= width)
7578 /* Get references to both ends of the field. */
7579 first = adjust_address (op, QImode, 0);
7580 last = adjust_address (op, QImode, width / BITS_PER_UNIT - 1);
7582 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
7583 correspond to the MSB and RIGHT to the LSB. */
7584 if (TARGET_BIG_ENDIAN)
7585 *left = first, *right = last;
7587 *left = last, *right = first;
7592 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
7593 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
7594 the operation is the equivalent of:
7596 (set DEST (*_extract SRC WIDTH BITPOS))
7598 Return true on success. */
7601 mips_expand_ext_as_unaligned_load (rtx dest, rtx src, HOST_WIDE_INT width,
7602 HOST_WIDE_INT bitpos, bool unsigned_p)
7604 rtx left, right, temp;
7605 rtx dest1 = NULL_RTX;
7607 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
7608 be a DImode, create a new temp and emit a zero extend at the end. */
7609 if (GET_MODE (dest) == DImode
7611 && GET_MODE_BITSIZE (SImode) == width)
7614 dest = gen_reg_rtx (SImode);
7617 if (!mips_get_unaligned_mem (src, width, bitpos, &left, &right))
7620 temp = gen_reg_rtx (GET_MODE (dest));
7621 if (GET_MODE (dest) == DImode)
7623 emit_insn (gen_mov_ldl (temp, src, left));
7624 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
7628 emit_insn (gen_mov_lwl (temp, src, left));
7629 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
7632 /* If we were loading 32bits and the original register was DI then
7633 sign/zero extend into the orignal dest. */
7637 emit_insn (gen_zero_extendsidi2 (dest1, dest));
7639 emit_insn (gen_extendsidi2 (dest1, dest));
7644 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
7645 BITPOS and SRC are the operands passed to the expander; the operation
7646 is the equivalent of:
7648 (set (zero_extract DEST WIDTH BITPOS) SRC)
7650 Return true on success. */
7653 mips_expand_ins_as_unaligned_store (rtx dest, rtx src, HOST_WIDE_INT width,
7654 HOST_WIDE_INT bitpos)
7657 enum machine_mode mode;
7659 if (!mips_get_unaligned_mem (dest, width, bitpos, &left, &right))
7662 mode = mode_for_size (width, MODE_INT, 0);
7663 src = gen_lowpart (mode, src);
7666 emit_insn (gen_mov_sdl (dest, src, left));
7667 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
7671 emit_insn (gen_mov_swl (dest, src, left));
7672 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
7677 /* Return true if X is a MEM with the same size as MODE. */
7680 mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
7683 && MEM_SIZE_KNOWN_P (x)
7684 && MEM_SIZE (x) == GET_MODE_SIZE (mode));
7687 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
7688 source of an "ext" instruction or the destination of an "ins"
7689 instruction. OP must be a register operand and the following
7690 conditions must hold:
7692 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
7693 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7694 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7696 Also reject lengths equal to a word as they are better handled
7697 by the move patterns. */
7700 mips_use_ins_ext_p (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos)
7702 if (!ISA_HAS_EXT_INS
7703 || !register_operand (op, VOIDmode)
7704 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
7707 if (!IN_RANGE (width, 1, GET_MODE_BITSIZE (GET_MODE (op)) - 1))
7710 if (bitpos < 0 || bitpos + width > GET_MODE_BITSIZE (GET_MODE (op)))
7716 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
7717 operation if MAXLEN is the maxium length of consecutive bits that
7718 can make up MASK. MODE is the mode of the operation. See
7719 mask_low_and_shift_len for the actual definition. */
7722 mask_low_and_shift_p (enum machine_mode mode, rtx mask, rtx shift, int maxlen)
7724 return IN_RANGE (mask_low_and_shift_len (mode, mask, shift), 1, maxlen);
7727 /* Return true iff OP1 and OP2 are valid operands together for the
7728 *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider,
7729 see the table in the comment before the pattern. */
7732 and_operands_ok (enum machine_mode mode, rtx op1, rtx op2)
7734 return (memory_operand (op1, mode)
7735 ? and_load_operand (op2, mode)
7736 : and_reg_operand (op2, mode));
7739 /* The canonical form of a mask-low-and-shift-left operation is
7740 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
7741 cleared. Thus we need to shift MASK to the right before checking if it
7742 is a valid mask value. MODE is the mode of the operation. If true
7743 return the length of the mask, otherwise return -1. */
7746 mask_low_and_shift_len (enum machine_mode mode, rtx mask, rtx shift)
7748 HOST_WIDE_INT shval;
7750 shval = INTVAL (shift) & (GET_MODE_BITSIZE (mode) - 1);
7751 return exact_log2 ((UINTVAL (mask) >> shval) + 1);
7754 /* Return true if -msplit-addresses is selected and should be honored.
7756 -msplit-addresses is a half-way house between explicit relocations
7757 and the traditional assembler macros. It can split absolute 32-bit
7758 symbolic constants into a high/lo_sum pair but uses macros for other
7761 Like explicit relocation support for REL targets, it relies
7762 on GNU extensions in the assembler and the linker.
7764 Although this code should work for -O0, it has traditionally
7765 been treated as an optimization. */
7768 mips_split_addresses_p (void)
7770 return (TARGET_SPLIT_ADDRESSES
7774 && !ABI_HAS_64BIT_SYMBOLS);
7777 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
7780 mips_init_relocs (void)
7782 memset (mips_split_p, '\0', sizeof (mips_split_p));
7783 memset (mips_split_hi_p, '\0', sizeof (mips_split_hi_p));
7784 memset (mips_use_pcrel_pool_p, '\0', sizeof (mips_use_pcrel_pool_p));
7785 memset (mips_hi_relocs, '\0', sizeof (mips_hi_relocs));
7786 memset (mips_lo_relocs, '\0', sizeof (mips_lo_relocs));
7788 if (TARGET_MIPS16_PCREL_LOADS)
7789 mips_use_pcrel_pool_p[SYMBOL_ABSOLUTE] = true;
7792 if (ABI_HAS_64BIT_SYMBOLS)
7794 if (TARGET_EXPLICIT_RELOCS)
7796 mips_split_p[SYMBOL_64_HIGH] = true;
7797 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
7798 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
7800 mips_split_p[SYMBOL_64_MID] = true;
7801 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
7802 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
7804 mips_split_p[SYMBOL_64_LOW] = true;
7805 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
7806 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
7808 mips_split_p[SYMBOL_ABSOLUTE] = true;
7809 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
7814 if (TARGET_EXPLICIT_RELOCS
7815 || mips_split_addresses_p ()
7818 mips_split_p[SYMBOL_ABSOLUTE] = true;
7819 mips_hi_relocs[SYMBOL_ABSOLUTE] = "%hi(";
7820 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
7827 /* The high part is provided by a pseudo copy of $gp. */
7828 mips_split_p[SYMBOL_GP_RELATIVE] = true;
7829 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gprel(";
7831 else if (TARGET_EXPLICIT_RELOCS)
7832 /* Small data constants are kept whole until after reload,
7833 then lowered by mips_rewrite_small_data. */
7834 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gp_rel(";
7836 if (TARGET_EXPLICIT_RELOCS)
7838 mips_split_p[SYMBOL_GOT_PAGE_OFST] = true;
7841 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
7842 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%got_ofst(";
7846 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
7847 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%lo(";
7850 /* Expose the use of $28 as soon as possible. */
7851 mips_split_hi_p[SYMBOL_GOT_PAGE_OFST] = true;
7855 /* The HIGH and LO_SUM are matched by special .md patterns. */
7856 mips_split_p[SYMBOL_GOT_DISP] = true;
7858 mips_split_p[SYMBOL_GOTOFF_DISP] = true;
7859 mips_hi_relocs[SYMBOL_GOTOFF_DISP] = "%got_hi(";
7860 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_lo(";
7862 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
7863 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
7864 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
7869 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_disp(";
7871 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got(";
7872 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
7874 /* Expose the use of $28 as soon as possible. */
7875 mips_split_p[SYMBOL_GOT_DISP] = true;
7881 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
7882 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
7883 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
7886 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
7887 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
7889 if (TARGET_MIPS16_PCREL_LOADS)
7891 mips_use_pcrel_pool_p[SYMBOL_DTPREL] = true;
7892 mips_use_pcrel_pool_p[SYMBOL_TPREL] = true;
7896 mips_split_p[SYMBOL_DTPREL] = true;
7897 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
7898 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
7900 mips_split_p[SYMBOL_TPREL] = true;
7901 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
7902 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
7905 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
7906 mips_lo_relocs[SYMBOL_HALF] = "%half(";
7909 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
7910 in context CONTEXT. RELOCS is the array of relocations to use. */
7913 mips_print_operand_reloc (FILE *file, rtx op, enum mips_symbol_context context,
7914 const char **relocs)
7916 enum mips_symbol_type symbol_type;
7919 symbol_type = mips_classify_symbolic_expression (op, context);
7920 gcc_assert (relocs[symbol_type]);
7922 fputs (relocs[symbol_type], file);
7923 output_addr_const (file, mips_strip_unspec_address (op));
7924 for (p = relocs[symbol_type]; *p != 0; p++)
7929 /* Start a new block with the given asm switch enabled. If we need
7930 to print a directive, emit PREFIX before it and SUFFIX after it. */
7933 mips_push_asm_switch_1 (struct mips_asm_switch *asm_switch,
7934 const char *prefix, const char *suffix)
7936 if (asm_switch->nesting_level == 0)
7937 fprintf (asm_out_file, "%s.set\tno%s%s", prefix, asm_switch->name, suffix);
7938 asm_switch->nesting_level++;
7941 /* Likewise, but end a block. */
7944 mips_pop_asm_switch_1 (struct mips_asm_switch *asm_switch,
7945 const char *prefix, const char *suffix)
7947 gcc_assert (asm_switch->nesting_level);
7948 asm_switch->nesting_level--;
7949 if (asm_switch->nesting_level == 0)
7950 fprintf (asm_out_file, "%s.set\t%s%s", prefix, asm_switch->name, suffix);
7953 /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1
7954 that either print a complete line or print nothing. */
7957 mips_push_asm_switch (struct mips_asm_switch *asm_switch)
7959 mips_push_asm_switch_1 (asm_switch, "\t", "\n");
7963 mips_pop_asm_switch (struct mips_asm_switch *asm_switch)
7965 mips_pop_asm_switch_1 (asm_switch, "\t", "\n");
7968 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
7969 The punctuation characters are:
7971 '(' Start a nested ".set noreorder" block.
7972 ')' End a nested ".set noreorder" block.
7973 '[' Start a nested ".set noat" block.
7974 ']' End a nested ".set noat" block.
7975 '<' Start a nested ".set nomacro" block.
7976 '>' End a nested ".set nomacro" block.
7977 '*' Behave like %(%< if generating a delayed-branch sequence.
7978 '#' Print a nop if in a ".set noreorder" block.
7979 '/' Like '#', but do nothing within a delayed-branch sequence.
7980 '?' Print "l" if mips_branch_likely is true
7981 '~' Print a nop if mips_branch_likely is true
7982 '.' Print the name of the register with a hard-wired zero (zero or $0).
7983 '@' Print the name of the assembler temporary register (at or $1).
7984 '^' Print the name of the pic call-through register (t9 or $25).
7985 '+' Print the name of the gp register (usually gp or $28).
7986 '$' Print the name of the stack pointer register (sp or $29).
7987 ':' Print "c" to use the compact version if the delay slot is a nop.
7988 '!' Print "s" to use the short version if the delay slot contains a
7991 See also mips_init_print_operand_pucnt. */
7994 mips_print_operand_punctuation (FILE *file, int ch)
7999 mips_push_asm_switch_1 (&mips_noreorder, "", "\n\t");
8003 mips_pop_asm_switch_1 (&mips_noreorder, "\n\t", "");
8007 mips_push_asm_switch_1 (&mips_noat, "", "\n\t");
8011 mips_pop_asm_switch_1 (&mips_noat, "\n\t", "");
8015 mips_push_asm_switch_1 (&mips_nomacro, "", "\n\t");
8019 mips_pop_asm_switch_1 (&mips_nomacro, "\n\t", "");
8023 if (final_sequence != 0)
8025 mips_print_operand_punctuation (file, '(');
8026 mips_print_operand_punctuation (file, '<');
8031 if (mips_noreorder.nesting_level > 0)
8032 fputs ("\n\tnop", file);
8036 /* Print an extra newline so that the delayed insn is separated
8037 from the following ones. This looks neater and is consistent
8038 with non-nop delayed sequences. */
8039 if (mips_noreorder.nesting_level > 0 && final_sequence == 0)
8040 fputs ("\n\tnop\n", file);
8044 if (mips_branch_likely)
8049 if (mips_branch_likely)
8050 fputs ("\n\tnop", file);
8054 fputs (reg_names[GP_REG_FIRST + 0], file);
8058 fputs (reg_names[AT_REGNUM], file);
8062 fputs (reg_names[PIC_FUNCTION_ADDR_REGNUM], file);
8066 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
8070 fputs (reg_names[STACK_POINTER_REGNUM], file);
8074 /* When final_sequence is 0, the delay slot will be a nop. We can
8075 use the compact version for microMIPS. */
8076 if (final_sequence == 0)
8081 /* If the delay slot instruction is short, then use the
8083 if (final_sequence == 0
8084 || get_attr_length (final_sequence->insn (1)) == 2)
8094 /* Initialize mips_print_operand_punct. */
8097 mips_init_print_operand_punct (void)
8101 for (p = "()[]<>*#/?~.@^+$:!"; *p; p++)
8102 mips_print_operand_punct[(unsigned char) *p] = true;
8105 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
8106 associated with condition CODE. Print the condition part of the
8110 mips_print_int_branch_condition (FILE *file, enum rtx_code code, int letter)
8124 /* Conveniently, the MIPS names for these conditions are the same
8125 as their RTL equivalents. */
8126 fputs (GET_RTX_NAME (code), file);
8130 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
8135 /* Likewise floating-point branches. */
8138 mips_print_float_branch_condition (FILE *file, enum rtx_code code, int letter)
8143 fputs ("c1f", file);
8147 fputs ("c1t", file);
8151 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
8156 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
8159 mips_print_operand_punct_valid_p (unsigned char code)
8161 return mips_print_operand_punct[code];
8164 /* Implement TARGET_PRINT_OPERAND. The MIPS-specific operand codes are:
8166 'X' Print CONST_INT OP in hexadecimal format.
8167 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
8168 'd' Print CONST_INT OP in decimal.
8169 'm' Print one less than CONST_INT OP in decimal.
8170 'h' Print the high-part relocation associated with OP, after stripping
8172 'R' Print the low-part relocation associated with OP.
8173 'C' Print the integer branch condition for comparison OP.
8174 'N' Print the inverse of the integer branch condition for comparison OP.
8175 'F' Print the FPU branch condition for comparison OP.
8176 'W' Print the inverse of the FPU branch condition for comparison OP.
8177 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
8178 'z' for (eq:?I ...), 'n' for (ne:?I ...).
8179 't' Like 'T', but with the EQ/NE cases reversed
8180 'Y' Print mips_fp_conditions[INTVAL (OP)]
8181 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
8182 'q' Print a DSP accumulator register.
8183 'D' Print the second part of a double-word register or memory operand.
8184 'L' Print the low-order register in a double-word register operand.
8185 'M' Print high-order register in a double-word register operand.
8186 'z' Print $0 if OP is zero, otherwise print OP normally.
8187 'b' Print the address of a memory operand, without offset. */
8190 mips_print_operand (FILE *file, rtx op, int letter)
8194 if (mips_print_operand_punct_valid_p (letter))
8196 mips_print_operand_punctuation (file, letter);
8201 code = GET_CODE (op);
8206 if (CONST_INT_P (op))
8207 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
8209 output_operand_lossage ("invalid use of '%%%c'", letter);
8213 if (CONST_INT_P (op))
8214 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op) & 0xffff);
8216 output_operand_lossage ("invalid use of '%%%c'", letter);
8220 if (CONST_INT_P (op))
8221 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op));
8223 output_operand_lossage ("invalid use of '%%%c'", letter);
8227 if (CONST_INT_P (op))
8228 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op) - 1);
8230 output_operand_lossage ("invalid use of '%%%c'", letter);
8236 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_hi_relocs);
8240 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_lo_relocs);
8244 mips_print_int_branch_condition (file, code, letter);
8248 mips_print_int_branch_condition (file, reverse_condition (code), letter);
8252 mips_print_float_branch_condition (file, code, letter);
8256 mips_print_float_branch_condition (file, reverse_condition (code),
8263 int truth = (code == NE) == (letter == 'T');
8264 fputc ("zfnt"[truth * 2 + ST_REG_P (REGNO (XEXP (op, 0)))], file);
8269 if (code == CONST_INT && UINTVAL (op) < ARRAY_SIZE (mips_fp_conditions))
8270 fputs (mips_fp_conditions[UINTVAL (op)], file);
8272 output_operand_lossage ("'%%%c' is not a valid operand prefix",
8279 mips_print_operand (file, op, 0);
8285 if (code == REG && MD_REG_P (REGNO (op)))
8286 fprintf (file, "$ac0");
8287 else if (code == REG && DSP_ACC_REG_P (REGNO (op)))
8288 fprintf (file, "$ac%c", reg_names[REGNO (op)][3]);
8290 output_operand_lossage ("invalid use of '%%%c'", letter);
8298 unsigned int regno = REGNO (op);
8299 if ((letter == 'M' && TARGET_LITTLE_ENDIAN)
8300 || (letter == 'L' && TARGET_BIG_ENDIAN)
8303 else if (letter && letter != 'z' && letter != 'M' && letter != 'L')
8304 output_operand_lossage ("invalid use of '%%%c'", letter);
8305 /* We need to print $0 .. $31 for COP0 registers. */
8306 if (COP0_REG_P (regno))
8307 fprintf (file, "$%s", ®_names[regno][4]);
8309 fprintf (file, "%s", reg_names[regno]);
8315 output_address (plus_constant (Pmode, XEXP (op, 0), 4));
8316 else if (letter == 'b')
8318 gcc_assert (REG_P (XEXP (op, 0)));
8319 mips_print_operand (file, XEXP (op, 0), 0);
8321 else if (letter && letter != 'z')
8322 output_operand_lossage ("invalid use of '%%%c'", letter);
8324 output_address (XEXP (op, 0));
8328 if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
8329 fputs (reg_names[GP_REG_FIRST], file);
8330 else if (letter && letter != 'z')
8331 output_operand_lossage ("invalid use of '%%%c'", letter);
8332 else if (CONST_GP_P (op))
8333 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
8335 output_addr_const (file, mips_strip_unspec_address (op));
8341 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
8344 mips_print_operand_address (FILE *file, rtx x)
8346 struct mips_address_info addr;
8348 if (mips_classify_address (&addr, x, word_mode, true))
8352 mips_print_operand (file, addr.offset, 0);
8353 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
8356 case ADDRESS_LO_SUM:
8357 mips_print_operand_reloc (file, addr.offset, SYMBOL_CONTEXT_MEM,
8359 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
8362 case ADDRESS_CONST_INT:
8363 output_addr_const (file, x);
8364 fprintf (file, "(%s)", reg_names[GP_REG_FIRST]);
8367 case ADDRESS_SYMBOLIC:
8368 output_addr_const (file, mips_strip_unspec_address (x));
8374 /* Implement TARGET_ENCODE_SECTION_INFO. */
8377 mips_encode_section_info (tree decl, rtx rtl, int first)
8379 default_encode_section_info (decl, rtl, first);
8381 if (TREE_CODE (decl) == FUNCTION_DECL)
8383 rtx symbol = XEXP (rtl, 0);
8384 tree type = TREE_TYPE (decl);
8386 /* Encode whether the symbol is short or long. */
8387 if ((TARGET_LONG_CALLS && !mips_near_type_p (type))
8388 || mips_far_type_p (type))
8389 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
8393 /* Implement TARGET_SELECT_RTX_SECTION. */
8396 mips_select_rtx_section (enum machine_mode mode, rtx x,
8397 unsigned HOST_WIDE_INT align)
8399 /* ??? Consider using mergeable small data sections. */
8400 if (mips_rtx_constant_in_small_data_p (mode))
8401 return get_named_section (NULL, ".sdata", 0);
8403 return default_elf_select_rtx_section (mode, x, align);
8406 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
8408 The complication here is that, with the combination TARGET_ABICALLS
8409 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
8410 absolute addresses, and should therefore not be included in the
8411 read-only part of a DSO. Handle such cases by selecting a normal
8412 data section instead of a read-only one. The logic apes that in
8413 default_function_rodata_section. */
8416 mips_function_rodata_section (tree decl)
8418 if (!TARGET_ABICALLS || TARGET_ABSOLUTE_ABICALLS || TARGET_GPWORD)
8419 return default_function_rodata_section (decl);
8421 if (decl && DECL_SECTION_NAME (decl))
8423 const char *name = DECL_SECTION_NAME (decl);
8424 if (DECL_COMDAT_GROUP (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
8426 char *rname = ASTRDUP (name);
8428 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
8430 else if (flag_function_sections
8431 && flag_data_sections
8432 && strncmp (name, ".text.", 6) == 0)
8434 char *rname = ASTRDUP (name);
8435 memcpy (rname + 1, "data", 4);
8436 return get_section (rname, SECTION_WRITE, decl);
8439 return data_section;
8442 /* Implement TARGET_IN_SMALL_DATA_P. */
8445 mips_in_small_data_p (const_tree decl)
8447 unsigned HOST_WIDE_INT size;
8449 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
8452 /* We don't yet generate small-data references for -mabicalls
8453 or VxWorks RTP code. See the related -G handling in
8454 mips_option_override. */
8455 if (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
8458 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
8462 /* Reject anything that isn't in a known small-data section. */
8463 name = DECL_SECTION_NAME (decl);
8464 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
8467 /* If a symbol is defined externally, the assembler will use the
8468 usual -G rules when deciding how to implement macros. */
8469 if (mips_lo_relocs[SYMBOL_GP_RELATIVE] || !DECL_EXTERNAL (decl))
8472 else if (TARGET_EMBEDDED_DATA)
8474 /* Don't put constants into the small data section: we want them
8475 to be in ROM rather than RAM. */
8476 if (TREE_CODE (decl) != VAR_DECL)
8479 if (TREE_READONLY (decl)
8480 && !TREE_SIDE_EFFECTS (decl)
8481 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
8485 /* Enforce -mlocal-sdata. */
8486 if (!TARGET_LOCAL_SDATA && !TREE_PUBLIC (decl))
8489 /* Enforce -mextern-sdata. */
8490 if (!TARGET_EXTERN_SDATA && DECL_P (decl))
8492 if (DECL_EXTERNAL (decl))
8494 if (DECL_COMMON (decl) && DECL_INITIAL (decl) == NULL)
8498 /* We have traditionally not treated zero-sized objects as small data,
8499 so this is now effectively part of the ABI. */
8500 size = int_size_in_bytes (TREE_TYPE (decl));
8501 return size > 0 && size <= mips_small_data_threshold;
8504 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
8505 anchors for small data: the GP register acts as an anchor in that
8506 case. We also don't want to use them for PC-relative accesses,
8507 where the PC acts as an anchor. */
8510 mips_use_anchors_for_symbol_p (const_rtx symbol)
8512 switch (mips_classify_symbol (symbol, SYMBOL_CONTEXT_MEM))
8514 case SYMBOL_PC_RELATIVE:
8515 case SYMBOL_GP_RELATIVE:
8519 return default_use_anchors_for_symbol_p (symbol);
8523 /* The MIPS debug format wants all automatic variables and arguments
8524 to be in terms of the virtual frame pointer (stack pointer before
8525 any adjustment in the function), while the MIPS 3.0 linker wants
8526 the frame pointer to be the stack pointer after the initial
8527 adjustment. So, we do the adjustment here. The arg pointer (which
8528 is eliminated) points to the virtual frame pointer, while the frame
8529 pointer (which may be eliminated) points to the stack pointer after
8530 the initial adjustments. */
8533 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
8535 rtx offset2 = const0_rtx;
8536 rtx reg = eliminate_constant_term (addr, &offset2);
8539 offset = INTVAL (offset2);
8541 if (reg == stack_pointer_rtx
8542 || reg == frame_pointer_rtx
8543 || reg == hard_frame_pointer_rtx)
8545 offset -= cfun->machine->frame.total_size;
8546 if (reg == hard_frame_pointer_rtx)
8547 offset += cfun->machine->frame.hard_frame_pointer_offset;
8553 /* Implement ASM_OUTPUT_EXTERNAL. */
8556 mips_output_external (FILE *file, tree decl, const char *name)
8558 default_elf_asm_output_external (file, decl, name);
8560 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
8561 set in order to avoid putting out names that are never really
8563 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
8565 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
8567 /* When using assembler macros, emit .extern directives for
8568 all small-data externs so that the assembler knows how
8571 In most cases it would be safe (though pointless) to emit
8572 .externs for other symbols too. One exception is when an
8573 object is within the -G limit but declared by the user to
8574 be in a section other than .sbss or .sdata. */
8575 fputs ("\t.extern\t", file);
8576 assemble_name (file, name);
8577 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n",
8578 int_size_in_bytes (TREE_TYPE (decl)));
8583 /* Implement TARGET_ASM_OUTPUT_SOURCE_FILENAME. */
8586 mips_output_filename (FILE *stream, const char *name)
8588 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
8590 if (write_symbols == DWARF2_DEBUG)
8592 else if (mips_output_filename_first_time)
8594 mips_output_filename_first_time = 0;
8595 num_source_filenames += 1;
8596 current_function_file = name;
8597 fprintf (stream, "\t.file\t%d ", num_source_filenames);
8598 output_quoted_string (stream, name);
8599 putc ('\n', stream);
8601 /* If we are emitting stabs, let dbxout.c handle this (except for
8602 the mips_output_filename_first_time case). */
8603 else if (write_symbols == DBX_DEBUG)
8605 else if (name != current_function_file
8606 && strcmp (name, current_function_file) != 0)
8608 num_source_filenames += 1;
8609 current_function_file = name;
8610 fprintf (stream, "\t.file\t%d ", num_source_filenames);
8611 output_quoted_string (stream, name);
8612 putc ('\n', stream);
8616 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
8618 static void ATTRIBUTE_UNUSED
8619 mips_output_dwarf_dtprel (FILE *file, int size, rtx x)
8624 fputs ("\t.dtprelword\t", file);
8628 fputs ("\t.dtpreldword\t", file);
8634 output_addr_const (file, x);
8635 fputs ("+0x8000", file);
8638 /* Implement TARGET_DWARF_REGISTER_SPAN. */
8641 mips_dwarf_register_span (rtx reg)
8644 enum machine_mode mode;
8646 /* By default, GCC maps increasing register numbers to increasing
8647 memory locations, but paired FPRs are always little-endian,
8648 regardless of the prevailing endianness. */
8649 mode = GET_MODE (reg);
8650 if (FP_REG_P (REGNO (reg))
8651 && TARGET_BIG_ENDIAN
8652 && MAX_FPRS_PER_FMT > 1
8653 && GET_MODE_SIZE (mode) > UNITS_PER_FPREG)
8655 gcc_assert (GET_MODE_SIZE (mode) == UNITS_PER_HWFPVALUE);
8656 high = mips_subword (reg, true);
8657 low = mips_subword (reg, false);
8658 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, high, low));
8664 /* DSP ALU can bypass data with no delays for the following pairs. */
8665 enum insn_code dspalu_bypass_table[][2] =
8667 {CODE_FOR_mips_addsc, CODE_FOR_mips_addwc},
8668 {CODE_FOR_mips_cmpu_eq_qb, CODE_FOR_mips_pick_qb},
8669 {CODE_FOR_mips_cmpu_lt_qb, CODE_FOR_mips_pick_qb},
8670 {CODE_FOR_mips_cmpu_le_qb, CODE_FOR_mips_pick_qb},
8671 {CODE_FOR_mips_cmp_eq_ph, CODE_FOR_mips_pick_ph},
8672 {CODE_FOR_mips_cmp_lt_ph, CODE_FOR_mips_pick_ph},
8673 {CODE_FOR_mips_cmp_le_ph, CODE_FOR_mips_pick_ph},
8674 {CODE_FOR_mips_wrdsp, CODE_FOR_mips_insv}
8678 mips_dspalu_bypass_p (rtx out_insn, rtx in_insn)
8681 int num_bypass = ARRAY_SIZE (dspalu_bypass_table);
8682 enum insn_code out_icode = (enum insn_code) INSN_CODE (out_insn);
8683 enum insn_code in_icode = (enum insn_code) INSN_CODE (in_insn);
8685 for (i = 0; i < num_bypass; i++)
8687 if (out_icode == dspalu_bypass_table[i][0]
8688 && in_icode == dspalu_bypass_table[i][1])
8694 /* Implement ASM_OUTPUT_ASCII. */
8697 mips_output_ascii (FILE *stream, const char *string, size_t len)
8703 fprintf (stream, "\t.ascii\t\"");
8704 for (i = 0; i < len; i++)
8708 c = (unsigned char) string[i];
8711 if (c == '\\' || c == '\"')
8713 putc ('\\', stream);
8721 fprintf (stream, "\\%03o", c);
8725 if (cur_pos > 72 && i+1 < len)
8728 fprintf (stream, "\"\n\t.ascii\t\"");
8731 fprintf (stream, "\"\n");
8734 /* Return the pseudo-op for full SYMBOL_(D)TPREL address *ADDR.
8735 Update *ADDR with the operand that should be printed. */
8738 mips_output_tls_reloc_directive (rtx *addr)
8740 enum mips_symbol_type type;
8742 type = mips_classify_symbolic_expression (*addr, SYMBOL_CONTEXT_LEA);
8743 *addr = mips_strip_unspec_address (*addr);
8747 return Pmode == SImode ? ".dtprelword\t%0" : ".dtpreldword\t%0";
8750 return Pmode == SImode ? ".tprelword\t%0" : ".tpreldword\t%0";
8757 /* Emit either a label, .comm, or .lcomm directive. When using assembler
8758 macros, mark the symbol as written so that mips_asm_output_external
8759 won't emit an .extern for it. STREAM is the output file, NAME is the
8760 name of the symbol, INIT_STRING is the string that should be written
8761 before the symbol and FINAL_STRING is the string that should be
8762 written after it. FINAL_STRING is a printf format that consumes the
8763 remaining arguments. */
8766 mips_declare_object (FILE *stream, const char *name, const char *init_string,
8767 const char *final_string, ...)
8771 fputs (init_string, stream);
8772 assemble_name (stream, name);
8773 va_start (ap, final_string);
8774 vfprintf (stream, final_string, ap);
8777 if (!TARGET_EXPLICIT_RELOCS)
8779 tree name_tree = get_identifier (name);
8780 TREE_ASM_WRITTEN (name_tree) = 1;
8784 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
8785 NAME is the name of the object and ALIGN is the required alignment
8786 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
8787 alignment argument. */
8790 mips_declare_common_object (FILE *stream, const char *name,
8791 const char *init_string,
8792 unsigned HOST_WIDE_INT size,
8793 unsigned int align, bool takes_alignment_p)
8795 if (!takes_alignment_p)
8797 size += (align / BITS_PER_UNIT) - 1;
8798 size -= size % (align / BITS_PER_UNIT);
8799 mips_declare_object (stream, name, init_string,
8800 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
8803 mips_declare_object (stream, name, init_string,
8804 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
8805 size, align / BITS_PER_UNIT);
8808 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
8809 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
8812 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
8813 unsigned HOST_WIDE_INT size,
8816 /* If the target wants uninitialized const declarations in
8817 .rdata then don't put them in .comm. */
8818 if (TARGET_EMBEDDED_DATA
8819 && TARGET_UNINIT_CONST_IN_RODATA
8820 && TREE_CODE (decl) == VAR_DECL
8821 && TREE_READONLY (decl)
8822 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
8824 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
8825 targetm.asm_out.globalize_label (stream, name);
8827 switch_to_section (readonly_data_section);
8828 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
8829 mips_declare_object (stream, name, "",
8830 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
8834 mips_declare_common_object (stream, name, "\n\t.comm\t",
8838 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8839 extern int size_directive_output;
8841 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
8842 definitions except that it uses mips_declare_object to emit the label. */
8845 mips_declare_object_name (FILE *stream, const char *name,
8846 tree decl ATTRIBUTE_UNUSED)
8848 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8849 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
8852 size_directive_output = 0;
8853 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
8857 size_directive_output = 1;
8858 size = int_size_in_bytes (TREE_TYPE (decl));
8859 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8862 mips_declare_object (stream, name, "", ":\n");
8865 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
8868 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
8872 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
8873 if (!flag_inhibit_size_directive
8874 && DECL_SIZE (decl) != 0
8877 && DECL_INITIAL (decl) == error_mark_node
8878 && !size_directive_output)
8882 size_directive_output = 1;
8883 size = int_size_in_bytes (TREE_TYPE (decl));
8884 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8889 /* Return the FOO in the name of the ".mdebug.FOO" section associated
8890 with the current ABI. */
8893 mips_mdebug_abi_name (void)
8906 return TARGET_64BIT ? "eabi64" : "eabi32";
8912 /* Implement TARGET_ASM_FILE_START. */
8915 mips_file_start (void)
8917 default_file_start ();
8919 /* Generate a special section to describe the ABI switches used to
8920 produce the resultant binary. */
8922 /* Record the ABI itself. Modern versions of binutils encode
8923 this information in the ELF header flags, but GDB needs the
8924 information in order to correctly debug binaries produced by
8925 older binutils. See the function mips_gdbarch_init in
8927 fprintf (asm_out_file, "\t.section .mdebug.%s\n\t.previous\n",
8928 mips_mdebug_abi_name ());
8930 /* There is no ELF header flag to distinguish long32 forms of the
8931 EABI from long64 forms. Emit a special section to help tools
8932 such as GDB. Do the same for o64, which is sometimes used with
8934 if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
8935 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n"
8936 "\t.previous\n", TARGET_LONG64 ? 64 : 32);
8938 /* Record the NaN encoding. */
8939 if (HAVE_AS_NAN || mips_nan != MIPS_IEEE_754_DEFAULT)
8940 fprintf (asm_out_file, "\t.nan\t%s\n",
8941 mips_nan == MIPS_IEEE_754_2008 ? "2008" : "legacy");
8943 #ifdef HAVE_AS_GNU_ATTRIBUTE
8947 /* No floating-point operations, -mno-float. */
8948 if (TARGET_NO_FLOAT)
8950 /* Soft-float code, -msoft-float. */
8951 else if (!TARGET_HARD_FLOAT_ABI)
8953 /* Single-float code, -msingle-float. */
8954 else if (!TARGET_DOUBLE_FLOAT)
8956 /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64. */
8957 else if (!TARGET_64BIT && TARGET_FLOAT64)
8959 /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */
8963 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n", attr);
8967 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
8968 if (TARGET_ABICALLS)
8970 fprintf (asm_out_file, "\t.abicalls\n");
8971 if (TARGET_ABICALLS_PIC0)
8972 fprintf (asm_out_file, "\t.option\tpic0\n");
8975 if (flag_verbose_asm)
8976 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
8978 mips_small_data_threshold, mips_arch_info->name, mips_isa);
8981 /* Implement TARGET_ASM_CODE_END. */
8984 mips_code_end (void)
8986 mips_finish_stub (&mips16_rdhwr_stub);
8987 mips_finish_stub (&mips16_get_fcsr_stub);
8988 mips_finish_stub (&mips16_set_fcsr_stub);
8991 /* Make the last instruction frame-related and note that it performs
8992 the operation described by FRAME_PATTERN. */
8995 mips_set_frame_expr (rtx frame_pattern)
8999 insn = get_last_insn ();
9000 RTX_FRAME_RELATED_P (insn) = 1;
9001 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
9006 /* Return a frame-related rtx that stores REG at MEM.
9007 REG must be a single register. */
9010 mips_frame_set (rtx mem, rtx reg)
9014 set = gen_rtx_SET (VOIDmode, mem, reg);
9015 RTX_FRAME_RELATED_P (set) = 1;
9020 /* Record that the epilogue has restored call-saved register REG. */
9023 mips_add_cfa_restore (rtx reg)
9025 mips_epilogue.cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg,
9026 mips_epilogue.cfa_restores);
9029 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
9030 mips16e_s2_s8_regs[X], it must also save the registers in indexes
9031 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
9032 static const unsigned char mips16e_s2_s8_regs[] = {
9033 30, 23, 22, 21, 20, 19, 18
9035 static const unsigned char mips16e_a0_a3_regs[] = {
9039 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
9040 ordered from the uppermost in memory to the lowest in memory. */
9041 static const unsigned char mips16e_save_restore_regs[] = {
9042 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
9045 /* Return the index of the lowest X in the range [0, SIZE) for which
9046 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
9049 mips16e_find_first_register (unsigned int mask, const unsigned char *regs,
9054 for (i = 0; i < size; i++)
9055 if (BITSET_P (mask, regs[i]))
9061 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
9062 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
9063 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
9064 is true for all indexes (X, SIZE). */
9067 mips16e_mask_registers (unsigned int *mask_ptr, const unsigned char *regs,
9068 unsigned int size, unsigned int *num_regs_ptr)
9072 i = mips16e_find_first_register (*mask_ptr, regs, size);
9073 for (i++; i < size; i++)
9074 if (!BITSET_P (*mask_ptr, regs[i]))
9077 *mask_ptr |= 1 << regs[i];
9081 /* Return a simplified form of X using the register values in REG_VALUES.
9082 REG_VALUES[R] is the last value assigned to hard register R, or null
9083 if R has not been modified.
9085 This function is rather limited, but is good enough for our purposes. */
9088 mips16e_collect_propagate_value (rtx x, rtx *reg_values)
9090 x = avoid_constant_pool_reference (x);
9094 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
9095 return simplify_gen_unary (GET_CODE (x), GET_MODE (x),
9096 x0, GET_MODE (XEXP (x, 0)));
9099 if (ARITHMETIC_P (x))
9101 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
9102 rtx x1 = mips16e_collect_propagate_value (XEXP (x, 1), reg_values);
9103 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), x0, x1);
9107 && reg_values[REGNO (x)]
9108 && !rtx_unstable_p (reg_values[REGNO (x)]))
9109 return reg_values[REGNO (x)];
9114 /* Return true if (set DEST SRC) stores an argument register into its
9115 caller-allocated save slot, storing the number of that argument
9116 register in *REGNO_PTR if so. REG_VALUES is as for
9117 mips16e_collect_propagate_value. */
9120 mips16e_collect_argument_save_p (rtx dest, rtx src, rtx *reg_values,
9121 unsigned int *regno_ptr)
9123 unsigned int argno, regno;
9124 HOST_WIDE_INT offset, required_offset;
9127 /* Check that this is a word-mode store. */
9128 if (!MEM_P (dest) || !REG_P (src) || GET_MODE (dest) != word_mode)
9131 /* Check that the register being saved is an unmodified argument
9133 regno = REGNO (src);
9134 if (!IN_RANGE (regno, GP_ARG_FIRST, GP_ARG_LAST) || reg_values[regno])
9136 argno = regno - GP_ARG_FIRST;
9138 /* Check whether the address is an appropriate stack-pointer or
9139 frame-pointer access. */
9140 addr = mips16e_collect_propagate_value (XEXP (dest, 0), reg_values);
9141 mips_split_plus (addr, &base, &offset);
9142 required_offset = cfun->machine->frame.total_size + argno * UNITS_PER_WORD;
9143 if (base == hard_frame_pointer_rtx)
9144 required_offset -= cfun->machine->frame.hard_frame_pointer_offset;
9145 else if (base != stack_pointer_rtx)
9147 if (offset != required_offset)
9154 /* A subroutine of mips_expand_prologue, called only when generating
9155 MIPS16e SAVE instructions. Search the start of the function for any
9156 instructions that save argument registers into their caller-allocated
9157 save slots. Delete such instructions and return a value N such that
9158 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
9159 instructions redundant. */
9162 mips16e_collect_argument_saves (void)
9164 rtx reg_values[FIRST_PSEUDO_REGISTER];
9165 rtx_insn *insn, *next;
9167 unsigned int nargs, regno;
9169 push_topmost_sequence ();
9171 memset (reg_values, 0, sizeof (reg_values));
9172 for (insn = get_insns (); insn; insn = next)
9174 next = NEXT_INSN (insn);
9175 if (NOTE_P (insn) || DEBUG_INSN_P (insn))
9181 set = PATTERN (insn);
9182 if (GET_CODE (set) != SET)
9185 dest = SET_DEST (set);
9186 src = SET_SRC (set);
9187 if (mips16e_collect_argument_save_p (dest, src, reg_values, ®no))
9189 if (!BITSET_P (cfun->machine->frame.mask, regno))
9192 nargs = MAX (nargs, (regno - GP_ARG_FIRST) + 1);
9195 else if (REG_P (dest) && GET_MODE (dest) == word_mode)
9196 reg_values[REGNO (dest)]
9197 = mips16e_collect_propagate_value (src, reg_values);
9201 pop_topmost_sequence ();
9206 /* Return a move between register REGNO and memory location SP + OFFSET.
9207 REG_PARM_P is true if SP + OFFSET belongs to REG_PARM_STACK_SPACE.
9208 Make the move a load if RESTORE_P, otherwise make it a store. */
9211 mips16e_save_restore_reg (bool restore_p, bool reg_parm_p,
9212 HOST_WIDE_INT offset, unsigned int regno)
9216 mem = gen_frame_mem (SImode, plus_constant (Pmode, stack_pointer_rtx,
9218 reg = gen_rtx_REG (SImode, regno);
9221 mips_add_cfa_restore (reg);
9222 return gen_rtx_SET (VOIDmode, reg, mem);
9225 return gen_rtx_SET (VOIDmode, mem, reg);
9226 return mips_frame_set (mem, reg);
9229 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
9230 The instruction must:
9232 - Allocate or deallocate SIZE bytes in total; SIZE is known
9235 - Save or restore as many registers in *MASK_PTR as possible.
9236 The instruction saves the first registers at the top of the
9237 allocated area, with the other registers below it.
9239 - Save NARGS argument registers above the allocated area.
9241 (NARGS is always zero if RESTORE_P.)
9243 The SAVE and RESTORE instructions cannot save and restore all general
9244 registers, so there may be some registers left over for the caller to
9245 handle. Destructively modify *MASK_PTR so that it contains the registers
9246 that still need to be saved or restored. The caller can save these
9247 registers in the memory immediately below *OFFSET_PTR, which is a
9248 byte offset from the bottom of the allocated stack area. */
9251 mips16e_build_save_restore (bool restore_p, unsigned int *mask_ptr,
9252 HOST_WIDE_INT *offset_ptr, unsigned int nargs,
9256 HOST_WIDE_INT offset, top_offset;
9257 unsigned int i, regno;
9260 gcc_assert (cfun->machine->frame.num_fp == 0);
9262 /* Calculate the number of elements in the PARALLEL. We need one element
9263 for the stack adjustment, one for each argument register save, and one
9264 for each additional register move. */
9266 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
9267 if (BITSET_P (*mask_ptr, mips16e_save_restore_regs[i]))
9270 /* Create the final PARALLEL. */
9271 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (n));
9274 /* Add the stack pointer adjustment. */
9275 set = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
9276 plus_constant (Pmode, stack_pointer_rtx,
9277 restore_p ? size : -size));
9278 RTX_FRAME_RELATED_P (set) = 1;
9279 XVECEXP (pattern, 0, n++) = set;
9281 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
9282 top_offset = restore_p ? size : 0;
9284 /* Save the arguments. */
9285 for (i = 0; i < nargs; i++)
9287 offset = top_offset + i * UNITS_PER_WORD;
9288 set = mips16e_save_restore_reg (restore_p, true, offset,
9290 XVECEXP (pattern, 0, n++) = set;
9293 /* Then fill in the other register moves. */
9294 offset = top_offset;
9295 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
9297 regno = mips16e_save_restore_regs[i];
9298 if (BITSET_P (*mask_ptr, regno))
9300 offset -= UNITS_PER_WORD;
9301 set = mips16e_save_restore_reg (restore_p, false, offset, regno);
9302 XVECEXP (pattern, 0, n++) = set;
9303 *mask_ptr &= ~(1 << regno);
9307 /* Tell the caller what offset it should use for the remaining registers. */
9308 *offset_ptr = size + (offset - top_offset);
9310 gcc_assert (n == XVECLEN (pattern, 0));
9315 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
9316 pointer. Return true if PATTERN matches the kind of instruction
9317 generated by mips16e_build_save_restore. If INFO is nonnull,
9318 initialize it when returning true. */
9321 mips16e_save_restore_pattern_p (rtx pattern, HOST_WIDE_INT adjust,
9322 struct mips16e_save_restore_info *info)
9324 unsigned int i, nargs, mask, extra;
9325 HOST_WIDE_INT top_offset, save_offset, offset;
9326 rtx set, reg, mem, base;
9329 if (!GENERATE_MIPS16E_SAVE_RESTORE)
9332 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
9333 top_offset = adjust > 0 ? adjust : 0;
9335 /* Interpret all other members of the PARALLEL. */
9336 save_offset = top_offset - UNITS_PER_WORD;
9340 for (n = 1; n < XVECLEN (pattern, 0); n++)
9342 /* Check that we have a SET. */
9343 set = XVECEXP (pattern, 0, n);
9344 if (GET_CODE (set) != SET)
9347 /* Check that the SET is a load (if restoring) or a store
9349 mem = adjust > 0 ? SET_SRC (set) : SET_DEST (set);
9353 /* Check that the address is the sum of the stack pointer and a
9354 possibly-zero constant offset. */
9355 mips_split_plus (XEXP (mem, 0), &base, &offset);
9356 if (base != stack_pointer_rtx)
9359 /* Check that SET's other operand is a register. */
9360 reg = adjust > 0 ? SET_DEST (set) : SET_SRC (set);
9364 /* Check for argument saves. */
9365 if (offset == top_offset + nargs * UNITS_PER_WORD
9366 && REGNO (reg) == GP_ARG_FIRST + nargs)
9368 else if (offset == save_offset)
9370 while (mips16e_save_restore_regs[i++] != REGNO (reg))
9371 if (i == ARRAY_SIZE (mips16e_save_restore_regs))
9374 mask |= 1 << REGNO (reg);
9375 save_offset -= UNITS_PER_WORD;
9381 /* Check that the restrictions on register ranges are met. */
9383 mips16e_mask_registers (&mask, mips16e_s2_s8_regs,
9384 ARRAY_SIZE (mips16e_s2_s8_regs), &extra);
9385 mips16e_mask_registers (&mask, mips16e_a0_a3_regs,
9386 ARRAY_SIZE (mips16e_a0_a3_regs), &extra);
9390 /* Make sure that the topmost argument register is not saved twice.
9391 The checks above ensure that the same is then true for the other
9392 argument registers. */
9393 if (nargs > 0 && BITSET_P (mask, GP_ARG_FIRST + nargs - 1))
9396 /* Pass back information, if requested. */
9399 info->nargs = nargs;
9401 info->size = (adjust > 0 ? adjust : -adjust);
9407 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
9408 for the register range [MIN_REG, MAX_REG]. Return a pointer to
9409 the null terminator. */
9412 mips16e_add_register_range (char *s, unsigned int min_reg,
9413 unsigned int max_reg)
9415 if (min_reg != max_reg)
9416 s += sprintf (s, ",%s-%s", reg_names[min_reg], reg_names[max_reg]);
9418 s += sprintf (s, ",%s", reg_names[min_reg]);
9422 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
9423 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
9426 mips16e_output_save_restore (rtx pattern, HOST_WIDE_INT adjust)
9428 static char buffer[300];
9430 struct mips16e_save_restore_info info;
9431 unsigned int i, end;
9434 /* Parse the pattern. */
9435 if (!mips16e_save_restore_pattern_p (pattern, adjust, &info))
9438 /* Add the mnemonic. */
9439 s = strcpy (buffer, adjust > 0 ? "restore\t" : "save\t");
9442 /* Save the arguments. */
9444 s += sprintf (s, "%s-%s,", reg_names[GP_ARG_FIRST],
9445 reg_names[GP_ARG_FIRST + info.nargs - 1]);
9446 else if (info.nargs == 1)
9447 s += sprintf (s, "%s,", reg_names[GP_ARG_FIRST]);
9449 /* Emit the amount of stack space to allocate or deallocate. */
9450 s += sprintf (s, "%d", (int) info.size);
9452 /* Save or restore $16. */
9453 if (BITSET_P (info.mask, 16))
9454 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 16]);
9456 /* Save or restore $17. */
9457 if (BITSET_P (info.mask, 17))
9458 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 17]);
9460 /* Save or restore registers in the range $s2...$s8, which
9461 mips16e_s2_s8_regs lists in decreasing order. Note that this
9462 is a software register range; the hardware registers are not
9463 numbered consecutively. */
9464 end = ARRAY_SIZE (mips16e_s2_s8_regs);
9465 i = mips16e_find_first_register (info.mask, mips16e_s2_s8_regs, end);
9467 s = mips16e_add_register_range (s, mips16e_s2_s8_regs[end - 1],
9468 mips16e_s2_s8_regs[i]);
9470 /* Save or restore registers in the range $a0...$a3. */
9471 end = ARRAY_SIZE (mips16e_a0_a3_regs);
9472 i = mips16e_find_first_register (info.mask, mips16e_a0_a3_regs, end);
9474 s = mips16e_add_register_range (s, mips16e_a0_a3_regs[i],
9475 mips16e_a0_a3_regs[end - 1]);
9477 /* Save or restore $31. */
9478 if (BITSET_P (info.mask, RETURN_ADDR_REGNUM))
9479 s += sprintf (s, ",%s", reg_names[RETURN_ADDR_REGNUM]);
9484 /* Return true if the current function returns its value in a floating-point
9485 register in MIPS16 mode. */
9488 mips16_cfun_returns_in_fpr_p (void)
9490 tree return_type = DECL_RESULT (current_function_decl);
9491 return (TARGET_MIPS16
9492 && TARGET_HARD_FLOAT_ABI
9493 && !aggregate_value_p (return_type, current_function_decl)
9494 && mips_return_mode_in_fpr_p (DECL_MODE (return_type)));
9497 /* Return true if predicate PRED is true for at least one instruction.
9498 Cache the result in *CACHE, and assume that the result is true
9499 if *CACHE is already true. */
9502 mips_find_gp_ref (bool *cache, bool (*pred) (rtx_insn *))
9508 push_topmost_sequence ();
9509 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9510 if (USEFUL_INSN_P (insn) && pred (insn))
9515 pop_topmost_sequence ();
9520 /* Return true if INSN refers to the global pointer in an "inflexible" way.
9521 See mips_cfun_has_inflexible_gp_ref_p for details. */
9524 mips_insn_has_inflexible_gp_ref_p (rtx_insn *insn)
9526 /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE
9527 indicate that the target could be a traditional MIPS
9528 lazily-binding stub. */
9529 return find_reg_fusage (insn, USE, pic_offset_table_rtx);
9532 /* Return true if the current function refers to the global pointer
9533 in a way that forces $28 to be valid. This means that we can't
9534 change the choice of global pointer, even for NewABI code.
9536 One example of this (and one which needs several checks) is that
9537 $28 must be valid when calling traditional MIPS lazy-binding stubs.
9538 (This restriction does not apply to PLTs.) */
9541 mips_cfun_has_inflexible_gp_ref_p (void)
9543 /* If the function has a nonlocal goto, $28 must hold the correct
9544 global pointer for the target function. That is, the target
9545 of the goto implicitly uses $28. */
9546 if (crtl->has_nonlocal_goto)
9549 if (TARGET_ABICALLS_PIC2)
9551 /* Symbolic accesses implicitly use the global pointer unless
9552 -mexplicit-relocs is in effect. JAL macros to symbolic addresses
9553 might go to traditional MIPS lazy-binding stubs. */
9554 if (!TARGET_EXPLICIT_RELOCS)
9557 /* FUNCTION_PROFILER includes a JAL to _mcount, which again
9558 can be lazily-bound. */
9562 /* MIPS16 functions that return in FPRs need to call an
9563 external libgcc routine. This call is only made explict
9564 during mips_expand_epilogue, and it too might be lazily bound. */
9565 if (mips16_cfun_returns_in_fpr_p ())
9569 return mips_find_gp_ref (&cfun->machine->has_inflexible_gp_insn_p,
9570 mips_insn_has_inflexible_gp_ref_p);
9573 /* Return true if INSN refers to the global pointer in a "flexible" way.
9574 See mips_cfun_has_flexible_gp_ref_p for details. */
9577 mips_insn_has_flexible_gp_ref_p (rtx_insn *insn)
9579 return (get_attr_got (insn) != GOT_UNSET
9580 || mips_small_data_pattern_p (PATTERN (insn))
9581 || reg_overlap_mentioned_p (pic_offset_table_rtx, PATTERN (insn)));
9584 /* Return true if the current function references the global pointer,
9585 but if those references do not inherently require the global pointer
9586 to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */
9589 mips_cfun_has_flexible_gp_ref_p (void)
9591 /* Reload can sometimes introduce constant pool references
9592 into a function that otherwise didn't need them. For example,
9593 suppose we have an instruction like:
9595 (set (reg:DF R1) (float:DF (reg:SI R2)))
9597 If R2 turns out to be a constant such as 1, the instruction may
9598 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
9599 the option of using this constant if R2 doesn't get allocated
9602 In cases like these, reload will have added the constant to the
9603 pool but no instruction will yet refer to it. */
9604 if (TARGET_ABICALLS_PIC2 && !reload_completed && crtl->uses_const_pool)
9607 return mips_find_gp_ref (&cfun->machine->has_flexible_gp_insn_p,
9608 mips_insn_has_flexible_gp_ref_p);
9611 /* Return the register that should be used as the global pointer
9612 within this function. Return INVALID_REGNUM if the function
9613 doesn't need a global pointer. */
9616 mips_global_pointer (void)
9620 /* $gp is always available unless we're using a GOT. */
9621 if (!TARGET_USE_GOT)
9622 return GLOBAL_POINTER_REGNUM;
9624 /* If there are inflexible references to $gp, we must use the
9625 standard register. */
9626 if (mips_cfun_has_inflexible_gp_ref_p ())
9627 return GLOBAL_POINTER_REGNUM;
9629 /* If there are no current references to $gp, then the only uses
9630 we can introduce later are those involved in long branches. */
9631 if (TARGET_ABSOLUTE_JUMPS && !mips_cfun_has_flexible_gp_ref_p ())
9632 return INVALID_REGNUM;
9634 /* If the global pointer is call-saved, try to use a call-clobbered
9636 if (TARGET_CALL_SAVED_GP && crtl->is_leaf)
9637 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
9638 if (!df_regs_ever_live_p (regno)
9639 && call_really_used_regs[regno]
9640 && !fixed_regs[regno]
9641 && regno != PIC_FUNCTION_ADDR_REGNUM)
9644 return GLOBAL_POINTER_REGNUM;
9647 /* Return true if the current function's prologue must load the global
9648 pointer value into pic_offset_table_rtx and store the same value in
9649 the function's cprestore slot (if any).
9651 One problem we have to deal with is that, when emitting GOT-based
9652 position independent code, long-branch sequences will need to load
9653 the address of the branch target from the GOT. We don't know until
9654 the very end of compilation whether (and where) the function needs
9655 long branches, so we must ensure that _any_ branch can access the
9656 global pointer in some form. However, we do not want to pessimize
9657 the usual case in which all branches are short.
9659 We handle this as follows:
9661 (1) During reload, we set cfun->machine->global_pointer to
9662 INVALID_REGNUM if we _know_ that the current function
9663 doesn't need a global pointer. This is only valid if
9664 long branches don't need the GOT.
9666 Otherwise, we assume that we might need a global pointer
9667 and pick an appropriate register.
9669 (2) If cfun->machine->global_pointer != INVALID_REGNUM,
9670 we ensure that the global pointer is available at every
9671 block boundary bar entry and exit. We do this in one of two ways:
9673 - If the function has a cprestore slot, we ensure that this
9674 slot is valid at every branch. However, as explained in
9675 point (6) below, there is no guarantee that pic_offset_table_rtx
9676 itself is valid if new uses of the global pointer are introduced
9677 after the first post-epilogue split.
9679 We guarantee that the cprestore slot is valid by loading it
9680 into a fake register, CPRESTORE_SLOT_REGNUM. We then make
9681 this register live at every block boundary bar function entry
9682 and exit. It is then invalid to move the load (and thus the
9683 preceding store) across a block boundary.
9685 - If the function has no cprestore slot, we guarantee that
9686 pic_offset_table_rtx itself is valid at every branch.
9688 See mips_eh_uses for the handling of the register liveness.
9690 (3) During prologue and epilogue generation, we emit "ghost"
9691 placeholder instructions to manipulate the global pointer.
9693 (4) During prologue generation, we set cfun->machine->must_initialize_gp_p
9694 and cfun->machine->must_restore_gp_when_clobbered_p if we already know
9695 that the function needs a global pointer. (There is no need to set
9696 them earlier than this, and doing it as late as possible leads to
9697 fewer false positives.)
9699 (5) If cfun->machine->must_initialize_gp_p is true during a
9700 split_insns pass, we split the ghost instructions into real
9701 instructions. These split instructions can then be optimized in
9702 the usual way. Otherwise, we keep the ghost instructions intact,
9703 and optimize for the case where they aren't needed. We still
9704 have the option of splitting them later, if we need to introduce
9705 new uses of the global pointer.
9707 For example, the scheduler ignores a ghost instruction that
9708 stores $28 to the stack, but it handles the split form of
9709 the ghost instruction as an ordinary store.
9711 (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p
9712 is true during the first post-epilogue split_insns pass, we split
9713 calls and restore_gp patterns into instructions that explicitly
9714 load pic_offset_table_rtx from the cprestore slot. Otherwise,
9715 we split these patterns into instructions that _don't_ load from
9718 If cfun->machine->must_restore_gp_when_clobbered_p is true at the
9719 time of the split, then any instructions that exist at that time
9720 can make free use of pic_offset_table_rtx. However, if we want
9721 to introduce new uses of the global pointer after the split,
9722 we must explicitly load the value from the cprestore slot, since
9723 pic_offset_table_rtx itself might not be valid at a given point
9726 The idea is that we want to be able to delete redundant
9727 loads from the cprestore slot in the usual case where no
9728 long branches are needed.
9730 (7) If cfun->machine->must_initialize_gp_p is still false at the end
9731 of md_reorg, we decide whether the global pointer is needed for
9732 long branches. If so, we set cfun->machine->must_initialize_gp_p
9733 to true and split the ghost instructions into real instructions
9736 Note that the ghost instructions must have a zero length for three reasons:
9738 - Giving the length of the underlying $gp sequence might cause
9739 us to use long branches in cases where they aren't really needed.
9741 - They would perturb things like alignment calculations.
9743 - More importantly, the hazard detection in md_reorg relies on
9744 empty instructions having a zero length.
9746 If we find a long branch and split the ghost instructions at the
9747 end of md_reorg, the split could introduce more long branches.
9748 That isn't a problem though, because we still do the split before
9749 the final shorten_branches pass.
9751 This is extremely ugly, but it seems like the best compromise between
9752 correctness and efficiency. */
9755 mips_must_initialize_gp_p (void)
9757 return cfun->machine->must_initialize_gp_p;
9760 /* Return true if REGNO is a register that is ordinarily call-clobbered
9761 but must nevertheless be preserved by an interrupt handler. */
9764 mips_interrupt_extra_call_saved_reg_p (unsigned int regno)
9766 if (MD_REG_P (regno))
9769 if (TARGET_DSP && DSP_ACC_REG_P (regno))
9772 if (GP_REG_P (regno) && !cfun->machine->use_shadow_register_set_p)
9774 /* $0 is hard-wired. */
9775 if (regno == GP_REG_FIRST)
9778 /* The interrupt handler can treat kernel registers as
9779 scratch registers. */
9780 if (KERNEL_REG_P (regno))
9783 /* The function will return the stack pointer to its original value
9785 if (regno == STACK_POINTER_REGNUM)
9788 /* Otherwise, return true for registers that aren't ordinarily
9790 return call_really_used_regs[regno];
9796 /* Return true if the current function should treat register REGNO
9800 mips_cfun_call_saved_reg_p (unsigned int regno)
9802 /* If the user makes an ordinarily-call-saved register global,
9803 that register is no longer call-saved. */
9804 if (global_regs[regno])
9807 /* Interrupt handlers need to save extra registers. */
9808 if (cfun->machine->interrupt_handler_p
9809 && mips_interrupt_extra_call_saved_reg_p (regno))
9812 /* call_insns preserve $28 unless they explicitly say otherwise,
9813 so call_really_used_regs[] treats $28 as call-saved. However,
9814 we want the ABI property rather than the default call_insn
9816 return (regno == GLOBAL_POINTER_REGNUM
9817 ? TARGET_CALL_SAVED_GP
9818 : !call_really_used_regs[regno]);
9821 /* Return true if the function body might clobber register REGNO.
9822 We know that REGNO is call-saved. */
9825 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno)
9827 /* Some functions should be treated as clobbering all call-saved
9829 if (crtl->saves_all_registers)
9832 /* DF handles cases where a register is explicitly referenced in
9833 the rtl. Incoming values are passed in call-clobbered registers,
9834 so we can assume that any live call-saved register is set within
9836 if (df_regs_ever_live_p (regno))
9839 /* Check for registers that are clobbered by FUNCTION_PROFILER.
9840 These clobbers are not explicit in the rtl. */
9841 if (crtl->profile && MIPS_SAVE_REG_FOR_PROFILING_P (regno))
9844 /* If we're using a call-saved global pointer, the function's
9845 prologue will need to set it up. */
9846 if (cfun->machine->global_pointer == regno)
9849 /* The function's prologue will need to set the frame pointer if
9850 frame_pointer_needed. */
9851 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
9854 /* If a MIPS16 function returns a value in FPRs, its epilogue
9855 will need to call an external libgcc routine. This yet-to-be
9856 generated call_insn will clobber $31. */
9857 if (regno == RETURN_ADDR_REGNUM && mips16_cfun_returns_in_fpr_p ())
9860 /* If REGNO is ordinarily call-clobbered, we must assume that any
9861 called function could modify it. */
9862 if (cfun->machine->interrupt_handler_p
9864 && mips_interrupt_extra_call_saved_reg_p (regno))
9870 /* Return true if the current function must save register REGNO. */
9873 mips_save_reg_p (unsigned int regno)
9875 if (mips_cfun_call_saved_reg_p (regno))
9877 if (mips_cfun_might_clobber_call_saved_reg_p (regno))
9880 /* Save both registers in an FPR pair if either one is used. This is
9881 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
9882 register to be used without the even register. */
9883 if (FP_REG_P (regno)
9884 && MAX_FPRS_PER_FMT == 2
9885 && mips_cfun_might_clobber_call_saved_reg_p (regno + 1))
9889 /* We need to save the incoming return address if __builtin_eh_return
9890 is being used to set a different return address. */
9891 if (regno == RETURN_ADDR_REGNUM && crtl->calls_eh_return)
9897 /* Populate the current function's mips_frame_info structure.
9899 MIPS stack frames look like:
9901 +-------------------------------+
9903 | incoming stack arguments |
9905 +-------------------------------+
9907 | caller-allocated save area |
9908 A | for register arguments |
9910 +-------------------------------+ <-- incoming stack pointer
9912 | callee-allocated save area |
9913 B | for arguments that are |
9914 | split between registers and |
9917 +-------------------------------+ <-- arg_pointer_rtx
9919 C | callee-allocated save area |
9920 | for register varargs |
9922 +-------------------------------+ <-- frame_pointer_rtx
9923 | | + cop0_sp_offset
9924 | COP0 reg save area | + UNITS_PER_WORD
9926 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
9927 | | + UNITS_PER_WORD
9928 | accumulator save area |
9930 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
9931 | | + UNITS_PER_HWFPVALUE
9934 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset
9935 | | + UNITS_PER_WORD
9938 +-------------------------------+ <-- frame_pointer_rtx with
9939 | | \ -fstack-protector
9940 | local variables | | var_size
9942 +-------------------------------+
9944 | $gp save area | | cprestore_size
9946 P +-------------------------------+ <-- hard_frame_pointer_rtx for
9948 | outgoing stack arguments | |
9950 +-------------------------------+ | args_size
9952 | caller-allocated save area | |
9953 | for register arguments | |
9955 +-------------------------------+ <-- stack_pointer_rtx
9956 frame_pointer_rtx without
9958 hard_frame_pointer_rtx for
9961 At least two of A, B and C will be empty.
9963 Dynamic stack allocations such as alloca insert data at point P.
9964 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
9965 hard_frame_pointer_rtx unchanged. */
9968 mips_compute_frame_info (void)
9970 struct mips_frame_info *frame;
9971 HOST_WIDE_INT offset, size;
9972 unsigned int regno, i;
9974 /* Set this function's interrupt properties. */
9975 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
9977 if (mips_isa_rev < 2)
9978 error ("the %<interrupt%> attribute requires a MIPS32r2 processor or greater");
9979 else if (TARGET_HARD_FLOAT)
9980 error ("the %<interrupt%> attribute requires %<-msoft-float%>");
9981 else if (TARGET_MIPS16)
9982 error ("interrupt handlers cannot be MIPS16 functions");
9985 cfun->machine->interrupt_handler_p = true;
9986 cfun->machine->use_shadow_register_set_p =
9987 mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl));
9988 cfun->machine->keep_interrupts_masked_p =
9989 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl));
9990 cfun->machine->use_debug_exception_return_p =
9991 mips_use_debug_exception_return_p (TREE_TYPE
9992 (current_function_decl));
9996 frame = &cfun->machine->frame;
9997 memset (frame, 0, sizeof (*frame));
9998 size = get_frame_size ();
10000 cfun->machine->global_pointer = mips_global_pointer ();
10002 /* The first two blocks contain the outgoing argument area and the $gp save
10003 slot. This area isn't needed in leaf functions, but if the
10004 target-independent frame size is nonzero, we have already committed to
10005 allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */
10006 if ((size == 0 || FRAME_GROWS_DOWNWARD) && crtl->is_leaf)
10008 /* The MIPS 3.0 linker does not like functions that dynamically
10009 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
10010 looks like we are trying to create a second frame pointer to the
10011 function, so allocate some stack space to make it happy. */
10012 if (cfun->calls_alloca)
10013 frame->args_size = REG_PARM_STACK_SPACE (cfun->decl);
10015 frame->args_size = 0;
10016 frame->cprestore_size = 0;
10020 frame->args_size = crtl->outgoing_args_size;
10021 frame->cprestore_size = MIPS_GP_SAVE_AREA_SIZE;
10023 offset = frame->args_size + frame->cprestore_size;
10025 /* Move above the local variables. */
10026 frame->var_size = MIPS_STACK_ALIGN (size);
10027 offset += frame->var_size;
10029 /* Find out which GPRs we need to save. */
10030 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
10031 if (mips_save_reg_p (regno))
10034 frame->mask |= 1 << (regno - GP_REG_FIRST);
10037 /* If this function calls eh_return, we must also save and restore the
10038 EH data registers. */
10039 if (crtl->calls_eh_return)
10040 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; i++)
10043 frame->mask |= 1 << (EH_RETURN_DATA_REGNO (i) - GP_REG_FIRST);
10046 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
10047 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
10048 save all later registers too. */
10049 if (GENERATE_MIPS16E_SAVE_RESTORE)
10051 mips16e_mask_registers (&frame->mask, mips16e_s2_s8_regs,
10052 ARRAY_SIZE (mips16e_s2_s8_regs), &frame->num_gp);
10053 mips16e_mask_registers (&frame->mask, mips16e_a0_a3_regs,
10054 ARRAY_SIZE (mips16e_a0_a3_regs), &frame->num_gp);
10057 /* Move above the GPR save area. */
10058 if (frame->num_gp > 0)
10060 offset += MIPS_STACK_ALIGN (frame->num_gp * UNITS_PER_WORD);
10061 frame->gp_sp_offset = offset - UNITS_PER_WORD;
10064 /* Find out which FPRs we need to save. This loop must iterate over
10065 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
10066 if (TARGET_HARD_FLOAT)
10067 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += MAX_FPRS_PER_FMT)
10068 if (mips_save_reg_p (regno))
10070 frame->num_fp += MAX_FPRS_PER_FMT;
10071 frame->fmask |= ~(~0 << MAX_FPRS_PER_FMT) << (regno - FP_REG_FIRST);
10074 /* Move above the FPR save area. */
10075 if (frame->num_fp > 0)
10077 offset += MIPS_STACK_ALIGN (frame->num_fp * UNITS_PER_FPREG);
10078 frame->fp_sp_offset = offset - UNITS_PER_HWFPVALUE;
10081 /* Add in space for the interrupt context information. */
10082 if (cfun->machine->interrupt_handler_p)
10085 if (mips_save_reg_p (LO_REGNUM) || mips_save_reg_p (HI_REGNUM))
10088 frame->acc_mask |= (1 << 0);
10091 /* Check accumulators 1, 2, 3. */
10092 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
10093 if (mips_save_reg_p (i) || mips_save_reg_p (i + 1))
10096 frame->acc_mask |= 1 << (((i - DSP_ACC_REG_FIRST) / 2) + 1);
10099 /* All interrupt context functions need space to preserve STATUS. */
10100 frame->num_cop0_regs++;
10102 /* If we don't keep interrupts masked, we need to save EPC. */
10103 if (!cfun->machine->keep_interrupts_masked_p)
10104 frame->num_cop0_regs++;
10107 /* Move above the accumulator save area. */
10108 if (frame->num_acc > 0)
10110 /* Each accumulator needs 2 words. */
10111 offset += frame->num_acc * 2 * UNITS_PER_WORD;
10112 frame->acc_sp_offset = offset - UNITS_PER_WORD;
10115 /* Move above the COP0 register save area. */
10116 if (frame->num_cop0_regs > 0)
10118 offset += frame->num_cop0_regs * UNITS_PER_WORD;
10119 frame->cop0_sp_offset = offset - UNITS_PER_WORD;
10122 /* Move above the callee-allocated varargs save area. */
10123 offset += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
10124 frame->arg_pointer_offset = offset;
10126 /* Move above the callee-allocated area for pretend stack arguments. */
10127 offset += crtl->args.pretend_args_size;
10128 frame->total_size = offset;
10130 /* Work out the offsets of the save areas from the top of the frame. */
10131 if (frame->gp_sp_offset > 0)
10132 frame->gp_save_offset = frame->gp_sp_offset - offset;
10133 if (frame->fp_sp_offset > 0)
10134 frame->fp_save_offset = frame->fp_sp_offset - offset;
10135 if (frame->acc_sp_offset > 0)
10136 frame->acc_save_offset = frame->acc_sp_offset - offset;
10137 if (frame->num_cop0_regs > 0)
10138 frame->cop0_save_offset = frame->cop0_sp_offset - offset;
10140 /* MIPS16 code offsets the frame pointer by the size of the outgoing
10141 arguments. This tends to increase the chances of using unextended
10142 instructions for local variables and incoming arguments. */
10144 frame->hard_frame_pointer_offset = frame->args_size;
10147 /* Return the style of GP load sequence that is being used for the
10148 current function. */
10150 enum mips_loadgp_style
10151 mips_current_loadgp_style (void)
10153 if (!TARGET_USE_GOT || cfun->machine->global_pointer == INVALID_REGNUM)
10154 return LOADGP_NONE;
10156 if (TARGET_RTP_PIC)
10159 if (TARGET_ABSOLUTE_ABICALLS)
10160 return LOADGP_ABSOLUTE;
10162 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
10165 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
10168 mips_frame_pointer_required (void)
10170 /* If the function contains dynamic stack allocations, we need to
10171 use the frame pointer to access the static parts of the frame. */
10172 if (cfun->calls_alloca)
10175 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
10176 reload may be unable to compute the address of a local variable,
10177 since there is no way to add a large constant to the stack pointer
10178 without using a second temporary register. */
10181 mips_compute_frame_info ();
10182 if (!SMALL_OPERAND (cfun->machine->frame.total_size))
10189 /* Make sure that we're not trying to eliminate to the wrong hard frame
10193 mips_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
10195 return (to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM);
10198 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
10199 or argument pointer. TO is either the stack pointer or hard frame
10203 mips_initial_elimination_offset (int from, int to)
10205 HOST_WIDE_INT offset;
10207 mips_compute_frame_info ();
10209 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */
10212 case FRAME_POINTER_REGNUM:
10213 if (FRAME_GROWS_DOWNWARD)
10214 offset = (cfun->machine->frame.args_size
10215 + cfun->machine->frame.cprestore_size
10216 + cfun->machine->frame.var_size);
10221 case ARG_POINTER_REGNUM:
10222 offset = cfun->machine->frame.arg_pointer_offset;
10226 gcc_unreachable ();
10229 if (to == HARD_FRAME_POINTER_REGNUM)
10230 offset -= cfun->machine->frame.hard_frame_pointer_offset;
10235 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
10238 mips_extra_live_on_entry (bitmap regs)
10240 if (TARGET_USE_GOT)
10242 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
10243 the global pointer. */
10244 if (!TARGET_ABSOLUTE_ABICALLS)
10245 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
10247 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
10248 the global pointer. */
10250 bitmap_set_bit (regs, MIPS16_PIC_TEMP_REGNUM);
10252 /* See the comment above load_call<mode> for details. */
10253 bitmap_set_bit (regs, GOT_VERSION_REGNUM);
10257 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
10261 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
10266 return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);
10269 /* Emit code to change the current function's return address to
10270 ADDRESS. SCRATCH is available as a scratch register, if needed.
10271 ADDRESS and SCRATCH are both word-mode GPRs. */
10274 mips_set_return_address (rtx address, rtx scratch)
10278 gcc_assert (BITSET_P (cfun->machine->frame.mask, RETURN_ADDR_REGNUM));
10279 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
10280 cfun->machine->frame.gp_sp_offset);
10281 mips_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address);
10284 /* Return true if the current function has a cprestore slot. */
10287 mips_cfun_has_cprestore_slot_p (void)
10289 return (cfun->machine->global_pointer != INVALID_REGNUM
10290 && cfun->machine->frame.cprestore_size > 0);
10293 /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the
10294 cprestore slot. LOAD_P is true if the caller wants to load from
10295 the cprestore slot; it is false if the caller wants to store to
10299 mips_get_cprestore_base_and_offset (rtx *base, HOST_WIDE_INT *offset,
10302 const struct mips_frame_info *frame;
10304 frame = &cfun->machine->frame;
10305 /* .cprestore always uses the stack pointer instead of the frame pointer.
10306 We have a free choice for direct stores for non-MIPS16 functions,
10307 and for MIPS16 functions whose cprestore slot is in range of the
10308 stack pointer. Using the stack pointer would sometimes give more
10309 (early) scheduling freedom, but using the frame pointer would
10310 sometimes give more (late) scheduling freedom. It's hard to
10311 predict which applies to a given function, so let's keep things
10314 Loads must always use the frame pointer in functions that call
10315 alloca, and there's little benefit to using the stack pointer
10317 if (frame_pointer_needed && !(TARGET_CPRESTORE_DIRECTIVE && !load_p))
10319 *base = hard_frame_pointer_rtx;
10320 *offset = frame->args_size - frame->hard_frame_pointer_offset;
10324 *base = stack_pointer_rtx;
10325 *offset = frame->args_size;
10329 /* Return true if X is the load or store address of the cprestore slot;
10330 LOAD_P says which. */
10333 mips_cprestore_address_p (rtx x, bool load_p)
10335 rtx given_base, required_base;
10336 HOST_WIDE_INT given_offset, required_offset;
10338 mips_split_plus (x, &given_base, &given_offset);
10339 mips_get_cprestore_base_and_offset (&required_base, &required_offset, load_p);
10340 return given_base == required_base && given_offset == required_offset;
10343 /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are
10344 going to load from it, false if we are going to store to it.
10345 Use TEMP as a temporary register if need be. */
10348 mips_cprestore_slot (rtx temp, bool load_p)
10351 HOST_WIDE_INT offset;
10353 mips_get_cprestore_base_and_offset (&base, &offset, load_p);
10354 return gen_frame_mem (Pmode, mips_add_offset (temp, base, offset));
10357 /* Emit instructions to save global pointer value GP into cprestore
10358 slot MEM. OFFSET is the offset that MEM applies to the base register.
10360 MEM may not be a legitimate address. If it isn't, TEMP is a
10361 temporary register that can be used, otherwise it is a SCRATCH. */
10364 mips_save_gp_to_cprestore_slot (rtx mem, rtx offset, rtx gp, rtx temp)
10366 if (TARGET_CPRESTORE_DIRECTIVE)
10368 gcc_assert (gp == pic_offset_table_rtx);
10369 emit_insn (PMODE_INSN (gen_cprestore, (mem, offset)));
10372 mips_emit_move (mips_cprestore_slot (temp, false), gp);
10375 /* Restore $gp from its save slot, using TEMP as a temporary base register
10376 if need be. This function is for o32 and o64 abicalls only.
10378 See mips_must_initialize_gp_p for details about how we manage the
10382 mips_restore_gp_from_cprestore_slot (rtx temp)
10384 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI && epilogue_completed);
10386 if (!cfun->machine->must_restore_gp_when_clobbered_p)
10388 emit_note (NOTE_INSN_DELETED);
10394 mips_emit_move (temp, mips_cprestore_slot (temp, true));
10395 mips_emit_move (pic_offset_table_rtx, temp);
10398 mips_emit_move (pic_offset_table_rtx, mips_cprestore_slot (temp, true));
10399 if (!TARGET_EXPLICIT_RELOCS)
10400 emit_insn (gen_blockage ());
10403 /* A function to save or store a register. The first argument is the
10404 register and the second is the stack slot. */
10405 typedef void (*mips_save_restore_fn) (rtx, rtx);
10407 /* Use FN to save or restore register REGNO. MODE is the register's
10408 mode and OFFSET is the offset of its save slot from the current
10412 mips_save_restore_reg (enum machine_mode mode, int regno,
10413 HOST_WIDE_INT offset, mips_save_restore_fn fn)
10417 mem = gen_frame_mem (mode, plus_constant (Pmode, stack_pointer_rtx,
10419 fn (gen_rtx_REG (mode, regno), mem);
10422 /* Call FN for each accumlator that is saved by the current function.
10423 SP_OFFSET is the offset of the current stack pointer from the start
10427 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
10429 HOST_WIDE_INT offset;
10432 offset = cfun->machine->frame.acc_sp_offset - sp_offset;
10433 if (BITSET_P (cfun->machine->frame.acc_mask, 0))
10435 mips_save_restore_reg (word_mode, LO_REGNUM, offset, fn);
10436 offset -= UNITS_PER_WORD;
10437 mips_save_restore_reg (word_mode, HI_REGNUM, offset, fn);
10438 offset -= UNITS_PER_WORD;
10441 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
10442 if (BITSET_P (cfun->machine->frame.acc_mask,
10443 ((regno - DSP_ACC_REG_FIRST) / 2) + 1))
10445 mips_save_restore_reg (word_mode, regno, offset, fn);
10446 offset -= UNITS_PER_WORD;
10450 /* Save register REG to MEM. Make the instruction frame-related. */
10453 mips_save_reg (rtx reg, rtx mem)
10455 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
10459 mips_emit_move_or_split (mem, reg, SPLIT_IF_NECESSARY);
10461 x1 = mips_frame_set (mips_subword (mem, false),
10462 mips_subword (reg, false));
10463 x2 = mips_frame_set (mips_subword (mem, true),
10464 mips_subword (reg, true));
10465 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
10468 mips_emit_save_slot_move (mem, reg, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
10471 /* Capture the register combinations that are allowed in a SWM or LWM
10472 instruction. The entries are ordered by number of registers set in
10473 the mask. We also ignore the single register encodings because a
10474 normal SW/LW is preferred. */
10476 static const unsigned int umips_swm_mask[17] = {
10477 0xc0ff0000, 0x80ff0000, 0x40ff0000, 0x807f0000,
10478 0x00ff0000, 0x803f0000, 0x007f0000, 0x801f0000,
10479 0x003f0000, 0x800f0000, 0x001f0000, 0x80070000,
10480 0x000f0000, 0x80030000, 0x00070000, 0x80010000,
10484 static const unsigned int umips_swm_encoding[17] = {
10485 25, 24, 9, 23, 8, 22, 7, 21, 6, 20, 5, 19, 4, 18, 3, 17, 2
10488 /* Try to use a microMIPS LWM or SWM instruction to save or restore
10489 as many GPRs in *MASK as possible. *OFFSET is the offset from the
10490 stack pointer of the topmost save slot.
10492 Remove from *MASK all registers that were handled using LWM and SWM.
10493 Update *OFFSET so that it points to the first unused save slot. */
10496 umips_build_save_restore (mips_save_restore_fn fn,
10497 unsigned *mask, HOST_WIDE_INT *offset)
10501 rtx pattern, set, reg, mem;
10502 HOST_WIDE_INT this_offset;
10505 /* Try matching $16 to $31 (s0 to ra). */
10506 for (i = 0; i < ARRAY_SIZE (umips_swm_mask); i++)
10507 if ((*mask & 0xffff0000) == umips_swm_mask[i])
10510 if (i == ARRAY_SIZE (umips_swm_mask))
10513 /* Get the offset of the lowest save slot. */
10514 nregs = (umips_swm_encoding[i] & 0xf) + (umips_swm_encoding[i] >> 4);
10515 this_offset = *offset - UNITS_PER_WORD * (nregs - 1);
10517 /* LWM/SWM can only support offsets from -2048 to 2047. */
10518 if (!UMIPS_12BIT_OFFSET_P (this_offset))
10521 /* Create the final PARALLEL. */
10522 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nregs));
10523 this_base = stack_pointer_rtx;
10525 /* For registers $16-$23 and $30. */
10526 for (j = 0; j < (umips_swm_encoding[i] & 0xf); j++)
10528 HOST_WIDE_INT offset = this_offset + j * UNITS_PER_WORD;
10529 mem = gen_frame_mem (SImode, plus_constant (Pmode, this_base, offset));
10530 unsigned int regno = (j != 8) ? 16 + j : 30;
10531 *mask &= ~(1 << regno);
10532 reg = gen_rtx_REG (SImode, regno);
10533 if (fn == mips_save_reg)
10534 set = mips_frame_set (mem, reg);
10537 set = gen_rtx_SET (VOIDmode, reg, mem);
10538 mips_add_cfa_restore (reg);
10540 XVECEXP (pattern, 0, j) = set;
10543 /* For register $31. */
10544 if (umips_swm_encoding[i] >> 4)
10546 HOST_WIDE_INT offset = this_offset + j * UNITS_PER_WORD;
10547 *mask &= ~(1 << 31);
10548 mem = gen_frame_mem (SImode, plus_constant (Pmode, this_base, offset));
10549 reg = gen_rtx_REG (SImode, 31);
10550 if (fn == mips_save_reg)
10551 set = mips_frame_set (mem, reg);
10554 set = gen_rtx_SET (VOIDmode, reg, mem);
10555 mips_add_cfa_restore (reg);
10557 XVECEXP (pattern, 0, j) = set;
10560 pattern = emit_insn (pattern);
10561 if (fn == mips_save_reg)
10562 RTX_FRAME_RELATED_P (pattern) = 1;
10564 /* Adjust the last offset. */
10565 *offset -= UNITS_PER_WORD * nregs;
10570 /* Call FN for each register that is saved by the current function.
10571 SP_OFFSET is the offset of the current stack pointer from the start
10575 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset,
10576 mips_save_restore_fn fn)
10578 enum machine_mode fpr_mode;
10580 const struct mips_frame_info *frame = &cfun->machine->frame;
10581 HOST_WIDE_INT offset;
10584 /* Save registers starting from high to low. The debuggers prefer at least
10585 the return register be stored at func+4, and also it allows us not to
10586 need a nop in the epilogue if at least one register is reloaded in
10587 addition to return address. */
10588 offset = frame->gp_sp_offset - sp_offset;
10589 mask = frame->mask;
10591 if (TARGET_MICROMIPS)
10592 umips_build_save_restore (fn, &mask, &offset);
10594 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
10595 if (BITSET_P (mask, regno - GP_REG_FIRST))
10597 /* Record the ra offset for use by mips_function_profiler. */
10598 if (regno == RETURN_ADDR_REGNUM)
10599 cfun->machine->frame.ra_fp_offset = offset + sp_offset;
10600 mips_save_restore_reg (word_mode, regno, offset, fn);
10601 offset -= UNITS_PER_WORD;
10604 /* This loop must iterate over the same space as its companion in
10605 mips_compute_frame_info. */
10606 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
10607 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
10608 for (regno = FP_REG_LAST - MAX_FPRS_PER_FMT + 1;
10609 regno >= FP_REG_FIRST;
10610 regno -= MAX_FPRS_PER_FMT)
10611 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
10613 mips_save_restore_reg (fpr_mode, regno, offset, fn);
10614 offset -= GET_MODE_SIZE (fpr_mode);
10618 /* Return true if a move between register REGNO and its save slot (MEM)
10619 can be done in a single move. LOAD_P is true if we are loading
10620 from the slot, false if we are storing to it. */
10623 mips_direct_save_slot_move_p (unsigned int regno, rtx mem, bool load_p)
10625 /* There is a specific MIPS16 instruction for saving $31 to the stack. */
10626 if (TARGET_MIPS16 && !load_p && regno == RETURN_ADDR_REGNUM)
10629 return mips_secondary_reload_class (REGNO_REG_CLASS (regno),
10630 GET_MODE (mem), mem, load_p) == NO_REGS;
10633 /* Emit a move from SRC to DEST, given that one of them is a register
10634 save slot and that the other is a register. TEMP is a temporary
10635 GPR of the same mode that is available if need be. */
10638 mips_emit_save_slot_move (rtx dest, rtx src, rtx temp)
10640 unsigned int regno;
10645 regno = REGNO (src);
10650 regno = REGNO (dest);
10654 if (regno == cfun->machine->global_pointer && !mips_must_initialize_gp_p ())
10656 /* We don't yet know whether we'll need this instruction or not.
10657 Postpone the decision by emitting a ghost move. This move
10658 is specifically not frame-related; only the split version is. */
10660 emit_insn (gen_move_gpdi (dest, src));
10662 emit_insn (gen_move_gpsi (dest, src));
10666 if (regno == HI_REGNUM)
10670 mips_emit_move (temp, src);
10672 emit_insn (gen_mthisi_di (gen_rtx_REG (TImode, MD_REG_FIRST),
10673 temp, gen_rtx_REG (DImode, LO_REGNUM)));
10675 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode, MD_REG_FIRST),
10676 temp, gen_rtx_REG (SImode, LO_REGNUM)));
10681 emit_insn (gen_mfhidi_ti (temp,
10682 gen_rtx_REG (TImode, MD_REG_FIRST)));
10684 emit_insn (gen_mfhisi_di (temp,
10685 gen_rtx_REG (DImode, MD_REG_FIRST)));
10686 mips_emit_move (dest, temp);
10689 else if (mips_direct_save_slot_move_p (regno, mem, mem == src))
10690 mips_emit_move (dest, src);
10693 gcc_assert (!reg_overlap_mentioned_p (dest, temp));
10694 mips_emit_move (temp, src);
10695 mips_emit_move (dest, temp);
10698 mips_set_frame_expr (mips_frame_set (dest, src));
10701 /* If we're generating n32 or n64 abicalls, and the current function
10702 does not use $28 as its global pointer, emit a cplocal directive.
10703 Use pic_offset_table_rtx as the argument to the directive. */
10706 mips_output_cplocal (void)
10708 if (!TARGET_EXPLICIT_RELOCS
10709 && mips_must_initialize_gp_p ()
10710 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
10711 output_asm_insn (".cplocal %+", 0);
10714 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
10717 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
10719 const char *fnname;
10721 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
10722 floating-point arguments. */
10724 && TARGET_HARD_FLOAT_ABI
10725 && crtl->args.info.fp_code != 0)
10726 mips16_build_function_stub ();
10728 /* Get the function name the same way that toplev.c does before calling
10729 assemble_start_function. This is needed so that the name used here
10730 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10731 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
10732 mips_start_function_definition (fnname, TARGET_MIPS16);
10734 /* Output MIPS-specific frame information. */
10735 if (!flag_inhibit_size_directive)
10737 const struct mips_frame_info *frame;
10739 frame = &cfun->machine->frame;
10741 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
10743 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
10744 "# vars= " HOST_WIDE_INT_PRINT_DEC
10746 ", args= " HOST_WIDE_INT_PRINT_DEC
10747 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
10748 reg_names[frame_pointer_needed
10749 ? HARD_FRAME_POINTER_REGNUM
10750 : STACK_POINTER_REGNUM],
10751 (frame_pointer_needed
10752 ? frame->total_size - frame->hard_frame_pointer_offset
10753 : frame->total_size),
10754 reg_names[RETURN_ADDR_REGNUM],
10756 frame->num_gp, frame->num_fp,
10758 frame->cprestore_size);
10760 /* .mask MASK, OFFSET. */
10761 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
10762 frame->mask, frame->gp_save_offset);
10764 /* .fmask MASK, OFFSET. */
10765 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
10766 frame->fmask, frame->fp_save_offset);
10769 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
10770 Also emit the ".set noreorder; .set nomacro" sequence for functions
10772 if (mips_must_initialize_gp_p ()
10773 && mips_current_loadgp_style () == LOADGP_OLDABI)
10777 /* This is a fixed-form sequence. The position of the
10778 first two instructions is important because of the
10779 way _gp_disp is defined. */
10780 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
10781 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
10782 output_asm_insn ("sll\t$2,16", 0);
10783 output_asm_insn ("addu\t$2,$3", 0);
10787 /* .cpload must be in a .set noreorder but not a
10788 .set nomacro block. */
10789 mips_push_asm_switch (&mips_noreorder);
10790 output_asm_insn (".cpload\t%^", 0);
10791 if (!cfun->machine->all_noreorder_p)
10792 mips_pop_asm_switch (&mips_noreorder);
10794 mips_push_asm_switch (&mips_nomacro);
10797 else if (cfun->machine->all_noreorder_p)
10799 mips_push_asm_switch (&mips_noreorder);
10800 mips_push_asm_switch (&mips_nomacro);
10803 /* Tell the assembler which register we're using as the global
10804 pointer. This is needed for thunks, since they can use either
10805 explicit relocs or assembler macros. */
10806 mips_output_cplocal ();
10809 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
10812 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
10813 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
10815 const char *fnname;
10817 /* Reinstate the normal $gp. */
10818 SET_REGNO (pic_offset_table_rtx, GLOBAL_POINTER_REGNUM);
10819 mips_output_cplocal ();
10821 if (cfun->machine->all_noreorder_p)
10823 mips_pop_asm_switch (&mips_nomacro);
10824 mips_pop_asm_switch (&mips_noreorder);
10827 /* Get the function name the same way that toplev.c does before calling
10828 assemble_start_function. This is needed so that the name used here
10829 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10830 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
10831 mips_end_function_definition (fnname);
10834 /* Emit an optimisation barrier for accesses to the current frame. */
10837 mips_frame_barrier (void)
10839 emit_clobber (gen_frame_mem (BLKmode, stack_pointer_rtx));
10843 /* The __gnu_local_gp symbol. */
10845 static GTY(()) rtx mips_gnu_local_gp;
10847 /* If we're generating n32 or n64 abicalls, emit instructions
10848 to set up the global pointer. */
10851 mips_emit_loadgp (void)
10853 rtx addr, offset, incoming_address, base, index, pic_reg;
10855 pic_reg = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
10856 switch (mips_current_loadgp_style ())
10858 case LOADGP_ABSOLUTE:
10859 if (mips_gnu_local_gp == NULL)
10861 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
10862 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
10864 emit_insn (PMODE_INSN (gen_loadgp_absolute,
10865 (pic_reg, mips_gnu_local_gp)));
10868 case LOADGP_OLDABI:
10869 /* Added by mips_output_function_prologue. */
10872 case LOADGP_NEWABI:
10873 addr = XEXP (DECL_RTL (current_function_decl), 0);
10874 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
10875 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
10876 emit_insn (PMODE_INSN (gen_loadgp_newabi,
10877 (pic_reg, offset, incoming_address)));
10881 base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE));
10882 index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX));
10883 emit_insn (PMODE_INSN (gen_loadgp_rtp, (pic_reg, base, index)));
10891 emit_insn (PMODE_INSN (gen_copygp_mips16,
10892 (pic_offset_table_rtx, pic_reg)));
10894 /* Emit a blockage if there are implicit uses of the GP register.
10895 This includes profiled functions, because FUNCTION_PROFILE uses
10897 if (!TARGET_EXPLICIT_RELOCS || crtl->profile)
10898 emit_insn (gen_loadgp_blockage ());
10901 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
10903 #if PROBE_INTERVAL > 32768
10904 #error Cannot use indexed addressing mode for stack probing
10907 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
10908 inclusive. These are offsets from the current stack pointer. */
10911 mips_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size)
10914 sorry ("-fstack-check=specific not implemented for MIPS16");
10916 /* See if we have a constant small number of probes to generate. If so,
10917 that's the easy case. */
10918 if (first + size <= 32768)
10922 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
10923 it exceeds SIZE. If only one probe is needed, this will not
10924 generate any code. Then probe at FIRST + SIZE. */
10925 for (i = PROBE_INTERVAL; i < size; i += PROBE_INTERVAL)
10926 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
10929 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
10933 /* Otherwise, do the same as above, but in a loop. Note that we must be
10934 extra careful with variables wrapping around because we might be at
10935 the very top (or the very bottom) of the address space and we have
10936 to be able to handle this case properly; in particular, we use an
10937 equality test for the loop condition. */
10940 HOST_WIDE_INT rounded_size;
10941 rtx r3 = MIPS_PROLOGUE_TEMP (Pmode);
10942 rtx r12 = MIPS_PROLOGUE_TEMP2 (Pmode);
10944 /* Sanity check for the addressing mode we're going to use. */
10945 gcc_assert (first <= 32768);
10948 /* Step 1: round SIZE to the previous multiple of the interval. */
10950 rounded_size = size & -PROBE_INTERVAL;
10953 /* Step 2: compute initial and final value of the loop counter. */
10955 /* TEST_ADDR = SP + FIRST. */
10956 emit_insn (gen_rtx_SET (VOIDmode, r3,
10957 plus_constant (Pmode, stack_pointer_rtx,
10960 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
10961 if (rounded_size > 32768)
10963 emit_move_insn (r12, GEN_INT (rounded_size));
10964 emit_insn (gen_rtx_SET (VOIDmode, r12,
10965 gen_rtx_MINUS (Pmode, r3, r12)));
10968 emit_insn (gen_rtx_SET (VOIDmode, r12,
10969 plus_constant (Pmode, r3, -rounded_size)));
10972 /* Step 3: the loop
10974 while (TEST_ADDR != LAST_ADDR)
10976 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
10980 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
10981 until it is equal to ROUNDED_SIZE. */
10983 emit_insn (PMODE_INSN (gen_probe_stack_range, (r3, r3, r12)));
10986 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
10987 that SIZE is equal to ROUNDED_SIZE. */
10989 if (size != rounded_size)
10990 emit_stack_probe (plus_constant (Pmode, r12, rounded_size - size));
10993 /* Make sure nothing is scheduled before we are done. */
10994 emit_insn (gen_blockage ());
10997 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
10998 absolute addresses. */
11001 mips_output_probe_stack_range (rtx reg1, rtx reg2)
11003 static int labelno = 0;
11004 char loop_lab[32], end_lab[32], tmp[64];
11007 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno);
11008 ASM_GENERATE_INTERNAL_LABEL (end_lab, "LPSRE", labelno++);
11010 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
11012 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
11015 strcpy (tmp, "%(%<beq\t%0,%1,");
11016 output_asm_insn (strcat (tmp, &end_lab[1]), xops);
11018 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
11019 xops[1] = GEN_INT (-PROBE_INTERVAL);
11020 if (TARGET_64BIT && TARGET_LONG64)
11021 output_asm_insn ("daddiu\t%0,%0,%1", xops);
11023 output_asm_insn ("addiu\t%0,%0,%1", xops);
11025 /* Probe at TEST_ADDR and branch. */
11026 fprintf (asm_out_file, "\tb\t");
11027 assemble_name_raw (asm_out_file, loop_lab);
11028 fputc ('\n', asm_out_file);
11030 output_asm_insn ("sd\t$0,0(%0)%)", xops);
11032 output_asm_insn ("sw\t$0,0(%0)%)", xops);
11034 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, end_lab);
11039 /* A for_each_rtx callback. Stop the search if *X is a kernel register. */
11042 mips_kernel_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
11044 return REG_P (*x) && KERNEL_REG_P (REGNO (*x));
11047 /* Expand the "prologue" pattern. */
11050 mips_expand_prologue (void)
11052 const struct mips_frame_info *frame;
11053 HOST_WIDE_INT size;
11054 unsigned int nargs;
11056 if (cfun->machine->global_pointer != INVALID_REGNUM)
11058 /* Check whether an insn uses pic_offset_table_rtx, either explicitly
11059 or implicitly. If so, we can commit to using a global pointer
11060 straight away, otherwise we need to defer the decision. */
11061 if (mips_cfun_has_inflexible_gp_ref_p ()
11062 || mips_cfun_has_flexible_gp_ref_p ())
11064 cfun->machine->must_initialize_gp_p = true;
11065 cfun->machine->must_restore_gp_when_clobbered_p = true;
11068 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
11071 frame = &cfun->machine->frame;
11072 size = frame->total_size;
11074 if (flag_stack_usage_info)
11075 current_function_static_stack_size = size;
11077 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK)
11079 if (crtl->is_leaf && !cfun->calls_alloca)
11081 if (size > PROBE_INTERVAL && size > STACK_CHECK_PROTECT)
11082 mips_emit_probe_stack_range (STACK_CHECK_PROTECT,
11083 size - STACK_CHECK_PROTECT);
11086 mips_emit_probe_stack_range (STACK_CHECK_PROTECT, size);
11089 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
11090 bytes beforehand; this is enough to cover the register save area
11091 without going out of range. */
11092 if (((frame->mask | frame->fmask | frame->acc_mask) != 0)
11093 || frame->num_cop0_regs > 0)
11095 HOST_WIDE_INT step1;
11097 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
11098 if (GENERATE_MIPS16E_SAVE_RESTORE)
11100 HOST_WIDE_INT offset;
11101 unsigned int mask, regno;
11103 /* Try to merge argument stores into the save instruction. */
11104 nargs = mips16e_collect_argument_saves ();
11106 /* Build the save instruction. */
11107 mask = frame->mask;
11108 rtx insn = mips16e_build_save_restore (false, &mask, &offset,
11110 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
11111 mips_frame_barrier ();
11114 /* Check if we need to save other registers. */
11115 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
11116 if (BITSET_P (mask, regno - GP_REG_FIRST))
11118 offset -= UNITS_PER_WORD;
11119 mips_save_restore_reg (word_mode, regno,
11120 offset, mips_save_reg);
11125 if (cfun->machine->interrupt_handler_p)
11127 HOST_WIDE_INT offset;
11130 /* If this interrupt is using a shadow register set, we need to
11131 get the stack pointer from the previous register set. */
11132 if (cfun->machine->use_shadow_register_set_p)
11133 emit_insn (gen_mips_rdpgpr (stack_pointer_rtx,
11134 stack_pointer_rtx));
11136 if (!cfun->machine->keep_interrupts_masked_p)
11138 /* Move from COP0 Cause to K0. */
11139 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K0_REG_NUM),
11140 gen_rtx_REG (SImode,
11141 COP0_CAUSE_REG_NUM)));
11142 /* Move from COP0 EPC to K1. */
11143 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
11144 gen_rtx_REG (SImode,
11145 COP0_EPC_REG_NUM)));
11148 /* Allocate the first part of the frame. */
11149 rtx insn = gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx,
11151 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
11152 mips_frame_barrier ();
11155 /* Start at the uppermost location for saving. */
11156 offset = frame->cop0_sp_offset - size;
11157 if (!cfun->machine->keep_interrupts_masked_p)
11159 /* Push EPC into its stack slot. */
11160 mem = gen_frame_mem (word_mode,
11161 plus_constant (Pmode, stack_pointer_rtx,
11163 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
11164 offset -= UNITS_PER_WORD;
11167 /* Move from COP0 Status to K1. */
11168 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
11169 gen_rtx_REG (SImode,
11170 COP0_STATUS_REG_NUM)));
11172 /* Right justify the RIPL in k0. */
11173 if (!cfun->machine->keep_interrupts_masked_p)
11174 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode, K0_REG_NUM),
11175 gen_rtx_REG (SImode, K0_REG_NUM),
11176 GEN_INT (CAUSE_IPL)));
11178 /* Push Status into its stack slot. */
11179 mem = gen_frame_mem (word_mode,
11180 plus_constant (Pmode, stack_pointer_rtx,
11182 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
11183 offset -= UNITS_PER_WORD;
11185 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
11186 if (!cfun->machine->keep_interrupts_masked_p)
11187 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
11190 gen_rtx_REG (SImode, K0_REG_NUM)));
11192 if (!cfun->machine->keep_interrupts_masked_p)
11193 /* Enable interrupts by clearing the KSU ERL and EXL bits.
11194 IE is already the correct value, so we don't have to do
11195 anything explicit. */
11196 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
11199 gen_rtx_REG (SImode, GP_REG_FIRST)));
11201 /* Disable interrupts by clearing the KSU, ERL, EXL,
11203 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
11206 gen_rtx_REG (SImode, GP_REG_FIRST)));
11210 rtx insn = gen_add3_insn (stack_pointer_rtx,
11213 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
11214 mips_frame_barrier ();
11217 mips_for_each_saved_acc (size, mips_save_reg);
11218 mips_for_each_saved_gpr_and_fpr (size, mips_save_reg);
11222 /* Allocate the rest of the frame. */
11225 if (SMALL_OPERAND (-size))
11226 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
11228 GEN_INT (-size)))) = 1;
11231 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
11234 /* There are no instructions to add or subtract registers
11235 from the stack pointer, so use the frame pointer as a
11236 temporary. We should always be using a frame pointer
11237 in this case anyway. */
11238 gcc_assert (frame_pointer_needed);
11239 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
11240 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
11241 hard_frame_pointer_rtx,
11242 MIPS_PROLOGUE_TEMP (Pmode)));
11243 mips_emit_move (stack_pointer_rtx, hard_frame_pointer_rtx);
11246 emit_insn (gen_sub3_insn (stack_pointer_rtx,
11248 MIPS_PROLOGUE_TEMP (Pmode)));
11250 /* Describe the combined effect of the previous instructions. */
11251 mips_set_frame_expr
11252 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
11253 plus_constant (Pmode, stack_pointer_rtx, -size)));
11255 mips_frame_barrier ();
11258 /* Set up the frame pointer, if we're using one. */
11259 if (frame_pointer_needed)
11261 HOST_WIDE_INT offset;
11263 offset = frame->hard_frame_pointer_offset;
11266 rtx insn = mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
11267 RTX_FRAME_RELATED_P (insn) = 1;
11269 else if (SMALL_OPERAND (offset))
11271 rtx insn = gen_add3_insn (hard_frame_pointer_rtx,
11272 stack_pointer_rtx, GEN_INT (offset));
11273 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
11277 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (offset));
11278 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
11279 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
11280 hard_frame_pointer_rtx,
11281 MIPS_PROLOGUE_TEMP (Pmode)));
11282 mips_set_frame_expr
11283 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
11284 plus_constant (Pmode, stack_pointer_rtx, offset)));
11288 mips_emit_loadgp ();
11290 /* Initialize the $gp save slot. */
11291 if (mips_cfun_has_cprestore_slot_p ())
11293 rtx base, mem, gp, temp;
11294 HOST_WIDE_INT offset;
11296 mips_get_cprestore_base_and_offset (&base, &offset, false);
11297 mem = gen_frame_mem (Pmode, plus_constant (Pmode, base, offset));
11298 gp = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
11299 temp = (SMALL_OPERAND (offset)
11300 ? gen_rtx_SCRATCH (Pmode)
11301 : MIPS_PROLOGUE_TEMP (Pmode));
11302 emit_insn (PMODE_INSN (gen_potential_cprestore,
11303 (mem, GEN_INT (offset), gp, temp)));
11305 mips_get_cprestore_base_and_offset (&base, &offset, true);
11306 mem = gen_frame_mem (Pmode, plus_constant (Pmode, base, offset));
11307 emit_insn (PMODE_INSN (gen_use_cprestore, (mem)));
11310 /* We need to search back to the last use of K0 or K1. */
11311 if (cfun->machine->interrupt_handler_p)
11314 for (insn = get_last_insn (); insn != NULL_RTX; insn = PREV_INSN (insn))
11316 && for_each_rtx (&PATTERN (insn), mips_kernel_reg_p, NULL))
11318 /* Emit a move from K1 to COP0 Status after insn. */
11319 gcc_assert (insn != NULL_RTX);
11320 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
11321 gen_rtx_REG (SImode, K1_REG_NUM)),
11325 /* If we are profiling, make sure no instructions are scheduled before
11326 the call to mcount. */
11328 emit_insn (gen_blockage ());
11331 /* Attach all pending register saves to the previous instruction.
11332 Return that instruction. */
11335 mips_epilogue_emit_cfa_restores (void)
11339 insn = get_last_insn ();
11340 gcc_assert (insn && !REG_NOTES (insn));
11341 if (mips_epilogue.cfa_restores)
11343 RTX_FRAME_RELATED_P (insn) = 1;
11344 REG_NOTES (insn) = mips_epilogue.cfa_restores;
11345 mips_epilogue.cfa_restores = 0;
11350 /* Like mips_epilogue_emit_cfa_restores, but also record that the CFA is
11351 now at REG + OFFSET. */
11354 mips_epilogue_set_cfa (rtx reg, HOST_WIDE_INT offset)
11358 insn = mips_epilogue_emit_cfa_restores ();
11359 if (reg != mips_epilogue.cfa_reg || offset != mips_epilogue.cfa_offset)
11361 RTX_FRAME_RELATED_P (insn) = 1;
11362 REG_NOTES (insn) = alloc_reg_note (REG_CFA_DEF_CFA,
11363 plus_constant (Pmode, reg, offset),
11365 mips_epilogue.cfa_reg = reg;
11366 mips_epilogue.cfa_offset = offset;
11370 /* Emit instructions to restore register REG from slot MEM. Also update
11371 the cfa_restores list. */
11374 mips_restore_reg (rtx reg, rtx mem)
11376 /* There's no MIPS16 instruction to load $31 directly. Load into
11377 $7 instead and adjust the return insn appropriately. */
11378 if (TARGET_MIPS16 && REGNO (reg) == RETURN_ADDR_REGNUM)
11379 reg = gen_rtx_REG (GET_MODE (reg), GP_REG_FIRST + 7);
11380 else if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
11382 mips_add_cfa_restore (mips_subword (reg, true));
11383 mips_add_cfa_restore (mips_subword (reg, false));
11386 mips_add_cfa_restore (reg);
11388 mips_emit_save_slot_move (reg, mem, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
11389 if (REGNO (reg) == REGNO (mips_epilogue.cfa_reg))
11390 /* The CFA is currently defined in terms of the register whose
11391 value we have just restored. Redefine the CFA in terms of
11392 the stack pointer. */
11393 mips_epilogue_set_cfa (stack_pointer_rtx,
11394 mips_epilogue.cfa_restore_sp_offset);
11397 /* Emit code to set the stack pointer to BASE + OFFSET, given that
11398 BASE + OFFSET is NEW_FRAME_SIZE bytes below the top of the frame.
11399 BASE, if not the stack pointer, is available as a temporary. */
11402 mips_deallocate_stack (rtx base, rtx offset, HOST_WIDE_INT new_frame_size)
11404 if (base == stack_pointer_rtx && offset == const0_rtx)
11407 mips_frame_barrier ();
11408 if (offset == const0_rtx)
11410 emit_move_insn (stack_pointer_rtx, base);
11411 mips_epilogue_set_cfa (stack_pointer_rtx, new_frame_size);
11413 else if (TARGET_MIPS16 && base != stack_pointer_rtx)
11415 emit_insn (gen_add3_insn (base, base, offset));
11416 mips_epilogue_set_cfa (base, new_frame_size);
11417 emit_move_insn (stack_pointer_rtx, base);
11421 emit_insn (gen_add3_insn (stack_pointer_rtx, base, offset));
11422 mips_epilogue_set_cfa (stack_pointer_rtx, new_frame_size);
11426 /* Emit any instructions needed before a return. */
11429 mips_expand_before_return (void)
11431 /* When using a call-clobbered gp, we start out with unified call
11432 insns that include instructions to restore the gp. We then split
11433 these unified calls after reload. These split calls explicitly
11434 clobber gp, so there is no need to define
11435 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
11437 For consistency, we should also insert an explicit clobber of $28
11438 before return insns, so that the post-reload optimizers know that
11439 the register is not live on exit. */
11440 if (TARGET_CALL_CLOBBERED_GP)
11441 emit_clobber (pic_offset_table_rtx);
11444 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
11448 mips_expand_epilogue (bool sibcall_p)
11450 const struct mips_frame_info *frame;
11451 HOST_WIDE_INT step1, step2;
11454 bool use_jraddiusp_p = false;
11456 if (!sibcall_p && mips_can_use_return_insn ())
11458 emit_jump_insn (gen_return ());
11462 /* In MIPS16 mode, if the return value should go into a floating-point
11463 register, we need to call a helper routine to copy it over. */
11464 if (mips16_cfun_returns_in_fpr_p ())
11465 mips16_copy_fpr_return_value ();
11467 /* Split the frame into two. STEP1 is the amount of stack we should
11468 deallocate before restoring the registers. STEP2 is the amount we
11469 should deallocate afterwards.
11471 Start off by assuming that no registers need to be restored. */
11472 frame = &cfun->machine->frame;
11473 step1 = frame->total_size;
11476 /* Work out which register holds the frame address. */
11477 if (!frame_pointer_needed)
11478 base = stack_pointer_rtx;
11481 base = hard_frame_pointer_rtx;
11482 step1 -= frame->hard_frame_pointer_offset;
11484 mips_epilogue.cfa_reg = base;
11485 mips_epilogue.cfa_offset = step1;
11486 mips_epilogue.cfa_restores = NULL_RTX;
11488 /* If we need to restore registers, deallocate as much stack as
11489 possible in the second step without going out of range. */
11490 if ((frame->mask | frame->fmask | frame->acc_mask) != 0
11491 || frame->num_cop0_regs > 0)
11493 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
11497 /* Get an rtx for STEP1 that we can add to BASE. */
11498 adjust = GEN_INT (step1);
11499 if (!SMALL_OPERAND (step1))
11501 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), adjust);
11502 adjust = MIPS_EPILOGUE_TEMP (Pmode);
11504 mips_deallocate_stack (base, adjust, step2);
11506 /* If we're using addressing macros, $gp is implicitly used by all
11507 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
11509 if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS)
11510 emit_insn (gen_blockage ());
11512 mips_epilogue.cfa_restore_sp_offset = step2;
11513 if (GENERATE_MIPS16E_SAVE_RESTORE && frame->mask != 0)
11515 unsigned int regno, mask;
11516 HOST_WIDE_INT offset;
11519 /* Generate the restore instruction. */
11520 mask = frame->mask;
11521 restore = mips16e_build_save_restore (true, &mask, &offset, 0, step2);
11523 /* Restore any other registers manually. */
11524 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
11525 if (BITSET_P (mask, regno - GP_REG_FIRST))
11527 offset -= UNITS_PER_WORD;
11528 mips_save_restore_reg (word_mode, regno, offset, mips_restore_reg);
11531 /* Restore the remaining registers and deallocate the final bit
11533 mips_frame_barrier ();
11534 emit_insn (restore);
11535 mips_epilogue_set_cfa (stack_pointer_rtx, 0);
11539 /* Restore the registers. */
11540 mips_for_each_saved_acc (frame->total_size - step2, mips_restore_reg);
11541 mips_for_each_saved_gpr_and_fpr (frame->total_size - step2,
11544 if (cfun->machine->interrupt_handler_p)
11546 HOST_WIDE_INT offset;
11549 offset = frame->cop0_sp_offset - (frame->total_size - step2);
11550 if (!cfun->machine->keep_interrupts_masked_p)
11552 /* Restore the original EPC. */
11553 mem = gen_frame_mem (word_mode,
11554 plus_constant (Pmode, stack_pointer_rtx,
11556 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
11557 offset -= UNITS_PER_WORD;
11559 /* Move to COP0 EPC. */
11560 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_EPC_REG_NUM),
11561 gen_rtx_REG (SImode, K0_REG_NUM)));
11564 /* Restore the original Status. */
11565 mem = gen_frame_mem (word_mode,
11566 plus_constant (Pmode, stack_pointer_rtx,
11568 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
11569 offset -= UNITS_PER_WORD;
11571 /* If we don't use shadow register set, we need to update SP. */
11572 if (!cfun->machine->use_shadow_register_set_p)
11573 mips_deallocate_stack (stack_pointer_rtx, GEN_INT (step2), 0);
11575 /* The choice of position is somewhat arbitrary in this case. */
11576 mips_epilogue_emit_cfa_restores ();
11578 /* Move to COP0 Status. */
11579 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
11580 gen_rtx_REG (SImode, K0_REG_NUM)));
11582 else if (TARGET_MICROMIPS
11583 && !crtl->calls_eh_return
11586 && mips_unsigned_immediate_p (step2, 5, 2))
11587 use_jraddiusp_p = true;
11589 /* Deallocate the final bit of the frame. */
11590 mips_deallocate_stack (stack_pointer_rtx, GEN_INT (step2), 0);
11593 if (!use_jraddiusp_p)
11594 gcc_assert (!mips_epilogue.cfa_restores);
11596 /* Add in the __builtin_eh_return stack adjustment. We need to
11597 use a temporary in MIPS16 code. */
11598 if (crtl->calls_eh_return)
11602 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
11603 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
11604 MIPS_EPILOGUE_TEMP (Pmode),
11605 EH_RETURN_STACKADJ_RTX));
11606 mips_emit_move (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
11609 emit_insn (gen_add3_insn (stack_pointer_rtx,
11611 EH_RETURN_STACKADJ_RTX));
11616 mips_expand_before_return ();
11617 if (cfun->machine->interrupt_handler_p)
11619 /* Interrupt handlers generate eret or deret. */
11620 if (cfun->machine->use_debug_exception_return_p)
11621 emit_jump_insn (gen_mips_deret ());
11623 emit_jump_insn (gen_mips_eret ());
11629 /* When generating MIPS16 code, the normal
11630 mips_for_each_saved_gpr_and_fpr path will restore the return
11631 address into $7 rather than $31. */
11633 && !GENERATE_MIPS16E_SAVE_RESTORE
11634 && BITSET_P (frame->mask, RETURN_ADDR_REGNUM))
11636 /* simple_returns cannot rely on values that are only available
11637 on paths through the epilogue (because return paths that do
11638 not pass through the epilogue may nevertheless reuse a
11639 simple_return that occurs at the end of the epilogue).
11640 Use a normal return here instead. */
11641 rtx reg = gen_rtx_REG (Pmode, GP_REG_FIRST + 7);
11642 pat = gen_return_internal (reg);
11644 else if (use_jraddiusp_p)
11645 pat = gen_jraddiusp (GEN_INT (step2));
11648 rtx reg = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
11649 pat = gen_simple_return_internal (reg);
11651 emit_jump_insn (pat);
11652 if (use_jraddiusp_p)
11653 mips_epilogue_set_cfa (stack_pointer_rtx, step2);
11657 /* Search from the beginning to the first use of K0 or K1. */
11658 if (cfun->machine->interrupt_handler_p
11659 && !cfun->machine->keep_interrupts_masked_p)
11661 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
11663 && for_each_rtx (&PATTERN(insn), mips_kernel_reg_p, NULL))
11665 gcc_assert (insn != NULL_RTX);
11666 /* Insert disable interrupts before the first use of K0 or K1. */
11667 emit_insn_before (gen_mips_di (), insn);
11668 emit_insn_before (gen_mips_ehb (), insn);
11672 /* Return nonzero if this function is known to have a null epilogue.
11673 This allows the optimizer to omit jumps to jumps if no stack
11677 mips_can_use_return_insn (void)
11679 /* Interrupt handlers need to go through the epilogue. */
11680 if (cfun->machine->interrupt_handler_p)
11683 if (!reload_completed)
11689 /* In MIPS16 mode, a function that returns a floating-point value
11690 needs to arrange to copy the return value into the floating-point
11692 if (mips16_cfun_returns_in_fpr_p ())
11695 return cfun->machine->frame.total_size == 0;
11698 /* Return true if register REGNO can store a value of mode MODE.
11699 The result of this function is cached in mips_hard_regno_mode_ok. */
11702 mips_hard_regno_mode_ok_p (unsigned int regno, enum machine_mode mode)
11705 enum mode_class mclass;
11707 if (mode == CCV2mode)
11708 return (ISA_HAS_8CC
11709 && ST_REG_P (regno)
11710 && (regno - ST_REG_FIRST) % 2 == 0);
11712 if (mode == CCV4mode)
11713 return (ISA_HAS_8CC
11714 && ST_REG_P (regno)
11715 && (regno - ST_REG_FIRST) % 4 == 0);
11717 if (mode == CCmode)
11718 return ISA_HAS_8CC ? ST_REG_P (regno) : regno == FPSW_REGNUM;
11720 size = GET_MODE_SIZE (mode);
11721 mclass = GET_MODE_CLASS (mode);
11723 if (GP_REG_P (regno))
11724 return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD;
11726 if (FP_REG_P (regno)
11727 && (((regno - FP_REG_FIRST) % MAX_FPRS_PER_FMT) == 0
11728 || (MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG)))
11730 /* Allow 64-bit vector modes for Loongson-2E/2F. */
11731 if (TARGET_LOONGSON_VECTORS
11732 && (mode == V2SImode
11733 || mode == V4HImode
11734 || mode == V8QImode
11735 || mode == DImode))
11738 if (mclass == MODE_FLOAT
11739 || mclass == MODE_COMPLEX_FLOAT
11740 || mclass == MODE_VECTOR_FLOAT)
11741 return size <= UNITS_PER_FPVALUE;
11743 /* Allow integer modes that fit into a single register. We need
11744 to put integers into FPRs when using instructions like CVT
11745 and TRUNC. There's no point allowing sizes smaller than a word,
11746 because the FPU has no appropriate load/store instructions. */
11747 if (mclass == MODE_INT)
11748 return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG;
11751 if (ACC_REG_P (regno)
11752 && (INTEGRAL_MODE_P (mode) || ALL_FIXED_POINT_MODE_P (mode)))
11754 if (MD_REG_P (regno))
11756 /* After a multiplication or division, clobbering HI makes
11757 the value of LO unpredictable, and vice versa. This means
11758 that, for all interesting cases, HI and LO are effectively
11761 We model this by requiring that any value that uses HI
11763 if (size <= UNITS_PER_WORD * 2)
11764 return regno == (size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST);
11768 /* DSP accumulators do not have the same restrictions as
11769 HI and LO, so we can treat them as normal doubleword
11771 if (size <= UNITS_PER_WORD)
11774 if (size <= UNITS_PER_WORD * 2
11775 && ((regno - DSP_ACC_REG_FIRST) & 1) == 0)
11780 if (ALL_COP_REG_P (regno))
11781 return mclass == MODE_INT && size <= UNITS_PER_WORD;
11783 if (regno == GOT_VERSION_REGNUM)
11784 return mode == SImode;
11789 /* Implement HARD_REGNO_NREGS. */
11792 mips_hard_regno_nregs (int regno, enum machine_mode mode)
11794 if (ST_REG_P (regno))
11795 /* The size of FP status registers is always 4, because they only hold
11796 CCmode values, and CCmode is always considered to be 4 bytes wide. */
11797 return (GET_MODE_SIZE (mode) + 3) / 4;
11799 if (FP_REG_P (regno))
11800 return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG;
11802 /* All other registers are word-sized. */
11803 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
11806 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
11807 in mips_hard_regno_nregs. */
11810 mips_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
11816 COPY_HARD_REG_SET (left, reg_class_contents[(int) rclass]);
11817 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS]))
11819 if (HARD_REGNO_MODE_OK (ST_REG_FIRST, mode))
11820 size = MIN (size, 4);
11821 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) ST_REGS]);
11823 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS]))
11825 if (HARD_REGNO_MODE_OK (FP_REG_FIRST, mode))
11826 size = MIN (size, UNITS_PER_FPREG);
11827 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]);
11829 if (!hard_reg_set_empty_p (left))
11830 size = MIN (size, UNITS_PER_WORD);
11831 return (GET_MODE_SIZE (mode) + size - 1) / size;
11834 /* Implement CANNOT_CHANGE_MODE_CLASS. */
11837 mips_cannot_change_mode_class (enum machine_mode from,
11838 enum machine_mode to,
11839 enum reg_class rclass)
11841 /* Allow conversions between different Loongson integer vectors,
11842 and between those vectors and DImode. */
11843 if (GET_MODE_SIZE (from) == 8 && GET_MODE_SIZE (to) == 8
11844 && INTEGRAL_MODE_P (from) && INTEGRAL_MODE_P (to))
11847 /* Otherwise, there are several problems with changing the modes of
11848 values in floating-point registers:
11850 - When a multi-word value is stored in paired floating-point
11851 registers, the first register always holds the low word. We
11852 therefore can't allow FPRs to change between single-word and
11853 multi-word modes on big-endian targets.
11855 - GCC assumes that each word of a multiword register can be
11856 accessed individually using SUBREGs. This is not true for
11857 floating-point registers if they are bigger than a word.
11859 - Loading a 32-bit value into a 64-bit floating-point register
11860 will not sign-extend the value, despite what LOAD_EXTEND_OP
11861 says. We can't allow FPRs to change from SImode to a wider
11862 mode on 64-bit targets.
11864 - If the FPU has already interpreted a value in one format, we
11865 must not ask it to treat the value as having a different
11868 We therefore disallow all mode changes involving FPRs. */
11870 return reg_classes_intersect_p (FP_REGS, rclass);
11873 /* Implement target hook small_register_classes_for_mode_p. */
11876 mips_small_register_classes_for_mode_p (enum machine_mode mode
11879 return TARGET_MIPS16;
11882 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
11885 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode)
11890 return TARGET_HARD_FLOAT;
11893 return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT;
11896 return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT;
11903 /* Implement MODES_TIEABLE_P. */
11906 mips_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
11908 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
11909 prefer to put one of them in FPRs. */
11910 return (mode1 == mode2
11911 || (!mips_mode_ok_for_mov_fmt_p (mode1)
11912 && !mips_mode_ok_for_mov_fmt_p (mode2)));
11915 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
11918 mips_preferred_reload_class (rtx x, reg_class_t rclass)
11920 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, rclass))
11923 if (reg_class_subset_p (FP_REGS, rclass)
11924 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x)))
11927 if (reg_class_subset_p (GR_REGS, rclass))
11930 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, rclass))
11936 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
11937 Return a "canonical" class to represent it in later calculations. */
11940 mips_canonicalize_move_class (reg_class_t rclass)
11942 /* All moves involving accumulator registers have the same cost. */
11943 if (reg_class_subset_p (rclass, ACC_REGS))
11946 /* Likewise promote subclasses of general registers to the most
11947 interesting containing class. */
11948 if (TARGET_MIPS16 && reg_class_subset_p (rclass, M16_REGS))
11950 else if (reg_class_subset_p (rclass, GENERAL_REGS))
11951 rclass = GENERAL_REGS;
11956 /* Return the cost of moving a value from a register of class FROM to a GPR.
11957 Return 0 for classes that are unions of other classes handled by this
11961 mips_move_to_gpr_cost (reg_class_t from)
11967 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
11971 /* MFLO and MFHI. */
11981 /* This choice of value is historical. */
11989 /* Return the cost of moving a value from a GPR to a register of class TO.
11990 Return 0 for classes that are unions of other classes handled by this
11994 mips_move_from_gpr_cost (reg_class_t to)
12000 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
12004 /* MTLO and MTHI. */
12014 /* This choice of value is historical. */
12022 /* Implement TARGET_REGISTER_MOVE_COST. Return 0 for classes that are the
12023 maximum of the move costs for subclasses; regclass will work out
12024 the maximum for us. */
12027 mips_register_move_cost (enum machine_mode mode,
12028 reg_class_t from, reg_class_t to)
12033 from = mips_canonicalize_move_class (from);
12034 to = mips_canonicalize_move_class (to);
12036 /* Handle moves that can be done without using general-purpose registers. */
12037 if (from == FP_REGS)
12039 if (to == FP_REGS && mips_mode_ok_for_mov_fmt_p (mode))
12044 /* Handle cases in which only one class deviates from the ideal. */
12045 dregs = TARGET_MIPS16 ? M16_REGS : GENERAL_REGS;
12047 return mips_move_from_gpr_cost (to);
12049 return mips_move_to_gpr_cost (from);
12051 /* Handles cases that require a GPR temporary. */
12052 cost1 = mips_move_to_gpr_cost (from);
12055 cost2 = mips_move_from_gpr_cost (to);
12057 return cost1 + cost2;
12063 /* Implement TARGET_REGISTER_PRIORITY. */
12066 mips_register_priority (int hard_regno)
12068 /* Treat MIPS16 registers with higher priority than other regs. */
12070 && TEST_HARD_REG_BIT (reg_class_contents[M16_REGS], hard_regno))
12075 /* Implement TARGET_MEMORY_MOVE_COST. */
12078 mips_memory_move_cost (enum machine_mode mode, reg_class_t rclass, bool in)
12080 return (mips_cost->memory_latency
12081 + memory_move_secondary_cost (mode, rclass, in));
12084 /* Return the register class required for a secondary register when
12085 copying between one of the registers in RCLASS and value X, which
12086 has mode MODE. X is the source of the move if IN_P, otherwise it
12087 is the destination. Return NO_REGS if no secondary register is
12091 mips_secondary_reload_class (enum reg_class rclass,
12092 enum machine_mode mode, rtx x, bool)
12096 /* If X is a constant that cannot be loaded into $25, it must be loaded
12097 into some other GPR. No other register class allows a direct move. */
12098 if (mips_dangerous_for_la25_p (x))
12099 return reg_class_subset_p (rclass, LEA_REGS) ? NO_REGS : LEA_REGS;
12101 regno = true_regnum (x);
12104 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
12105 if (!reg_class_subset_p (rclass, M16_REGS) && !M16_REG_P (regno))
12111 /* Copying from accumulator registers to anywhere other than a general
12112 register requires a temporary general register. */
12113 if (reg_class_subset_p (rclass, ACC_REGS))
12114 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
12115 if (ACC_REG_P (regno))
12116 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
12118 if (reg_class_subset_p (rclass, FP_REGS))
12122 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8)))
12123 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
12124 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
12127 if (GP_REG_P (regno) || x == CONST0_RTX (mode))
12128 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
12131 if (CONSTANT_P (x) && !targetm.cannot_force_const_mem (mode, x))
12132 /* We can force the constant to memory and use lwc1
12133 and ldc1. As above, we will use pairs of lwc1s if
12134 ldc1 is not supported. */
12137 if (FP_REG_P (regno) && mips_mode_ok_for_mov_fmt_p (mode))
12138 /* In this case we can use mov.fmt. */
12141 /* Otherwise, we need to reload through an integer register. */
12144 if (FP_REG_P (regno))
12145 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
12150 /* Implement TARGET_MODE_REP_EXTENDED. */
12153 mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
12155 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
12156 if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
12157 return SIGN_EXTEND;
12162 /* Implement TARGET_VALID_POINTER_MODE. */
12165 mips_valid_pointer_mode (enum machine_mode mode)
12167 return mode == SImode || (TARGET_64BIT && mode == DImode);
12170 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
12173 mips_vector_mode_supported_p (enum machine_mode mode)
12178 return TARGET_PAIRED_SINGLE_FLOAT;
12193 return TARGET_LOONGSON_VECTORS;
12200 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
12203 mips_scalar_mode_supported_p (enum machine_mode mode)
12205 if (ALL_FIXED_POINT_MODE_P (mode)
12206 && GET_MODE_PRECISION (mode) <= 2 * BITS_PER_WORD)
12209 return default_scalar_mode_supported_p (mode);
12212 /* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
12214 static enum machine_mode
12215 mips_preferred_simd_mode (enum machine_mode mode ATTRIBUTE_UNUSED)
12217 if (TARGET_PAIRED_SINGLE_FLOAT
12223 /* Implement TARGET_INIT_LIBFUNCS. */
12226 mips_init_libfuncs (void)
12228 if (TARGET_FIX_VR4120)
12230 /* Register the special divsi3 and modsi3 functions needed to work
12231 around VR4120 division errata. */
12232 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
12233 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
12236 if (TARGET_MIPS16 && TARGET_HARD_FLOAT_ABI)
12238 /* Register the MIPS16 -mhard-float stubs. */
12239 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
12240 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
12241 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
12242 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
12244 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
12245 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
12246 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
12247 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
12248 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
12249 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
12250 set_optab_libfunc (unord_optab, SFmode, "__mips16_unordsf2");
12252 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
12253 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
12254 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__mips16_floatunsisf");
12256 if (TARGET_DOUBLE_FLOAT)
12258 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
12259 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
12260 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
12261 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
12263 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
12264 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
12265 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
12266 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
12267 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
12268 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
12269 set_optab_libfunc (unord_optab, DFmode, "__mips16_unorddf2");
12271 set_conv_libfunc (sext_optab, DFmode, SFmode,
12272 "__mips16_extendsfdf2");
12273 set_conv_libfunc (trunc_optab, SFmode, DFmode,
12274 "__mips16_truncdfsf2");
12275 set_conv_libfunc (sfix_optab, SImode, DFmode,
12276 "__mips16_fix_truncdfsi");
12277 set_conv_libfunc (sfloat_optab, DFmode, SImode,
12278 "__mips16_floatsidf");
12279 set_conv_libfunc (ufloat_optab, DFmode, SImode,
12280 "__mips16_floatunsidf");
12284 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
12285 on an external non-MIPS16 routine to implement __sync_synchronize.
12286 Similarly for the rest of the ll/sc libfuncs. */
12289 synchronize_libfunc = init_one_libfunc ("__sync_synchronize");
12290 init_sync_libfuncs (UNITS_PER_WORD);
12294 /* Build up a multi-insn sequence that loads label TARGET into $AT. */
12297 mips_process_load_label (rtx target)
12299 rtx base, gp, intop;
12300 HOST_WIDE_INT offset;
12302 mips_multi_start ();
12306 mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target, 0);
12307 mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target, 0);
12311 mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target, 0);
12312 mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target, 0);
12316 gp = pic_offset_table_rtx;
12317 if (mips_cfun_has_cprestore_slot_p ())
12319 gp = gen_rtx_REG (Pmode, AT_REGNUM);
12320 mips_get_cprestore_base_and_offset (&base, &offset, true);
12321 if (!SMALL_OPERAND (offset))
12323 intop = GEN_INT (CONST_HIGH_PART (offset));
12324 mips_multi_add_insn ("lui\t%0,%1", gp, intop, 0);
12325 mips_multi_add_insn ("addu\t%0,%0,%1", gp, base, 0);
12328 offset = CONST_LOW_PART (offset);
12330 intop = GEN_INT (offset);
12331 if (ISA_HAS_LOAD_DELAY)
12332 mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp, intop, base, 0);
12334 mips_multi_add_insn ("lw\t%0,%1(%2)", gp, intop, base, 0);
12336 if (ISA_HAS_LOAD_DELAY)
12337 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target, gp, 0);
12339 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target, gp, 0);
12340 mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target, 0);
12345 /* Return the number of instructions needed to load a label into $AT. */
12347 static unsigned int
12348 mips_load_label_num_insns (void)
12350 if (cfun->machine->load_label_num_insns == 0)
12352 mips_process_load_label (pc_rtx);
12353 cfun->machine->load_label_num_insns = mips_multi_num_insns;
12355 return cfun->machine->load_label_num_insns;
12358 /* Emit an asm sequence to start a noat block and load the address
12359 of a label into $1. */
12362 mips_output_load_label (rtx target)
12364 mips_push_asm_switch (&mips_noat);
12365 if (TARGET_EXPLICIT_RELOCS)
12367 mips_process_load_label (target);
12368 mips_multi_write ();
12372 if (Pmode == DImode)
12373 output_asm_insn ("dla\t%@,%0", &target);
12375 output_asm_insn ("la\t%@,%0", &target);
12379 /* Return the length of INSN. LENGTH is the initial length computed by
12380 attributes in the machine-description file. */
12383 mips_adjust_insn_length (rtx_insn *insn, int length)
12385 /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length
12386 of a PIC long-branch sequence. Substitute the correct value. */
12387 if (length == MAX_PIC_BRANCH_LENGTH
12389 && INSN_CODE (insn) >= 0
12390 && get_attr_type (insn) == TYPE_BRANCH)
12392 /* Add the branch-over instruction and its delay slot, if this
12393 is a conditional branch. */
12394 length = simplejump_p (insn) ? 0 : 8;
12396 /* Add the size of a load into $AT. */
12397 length += BASE_INSN_LENGTH * mips_load_label_num_insns ();
12399 /* Add the length of an indirect jump, ignoring the delay slot. */
12400 length += TARGET_COMPRESSION ? 2 : 4;
12403 /* A unconditional jump has an unfilled delay slot if it is not part
12404 of a sequence. A conditional jump normally has a delay slot, but
12405 does not on MIPS16. */
12406 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
12407 length += TARGET_MIPS16 ? 2 : 4;
12409 /* See how many nops might be needed to avoid hardware hazards. */
12410 if (!cfun->machine->ignore_hazard_length_p
12412 && INSN_CODE (insn) >= 0)
12413 switch (get_attr_hazard (insn))
12419 length += NOP_INSN_LENGTH;
12423 length += NOP_INSN_LENGTH * 2;
12430 /* Return the assembly code for INSN, which has the operands given by
12431 OPERANDS, and which branches to OPERANDS[0] if some condition is true.
12432 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0]
12433 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
12434 version of BRANCH_IF_TRUE. */
12437 mips_output_conditional_branch (rtx_insn *insn, rtx *operands,
12438 const char *branch_if_true,
12439 const char *branch_if_false)
12441 unsigned int length;
12444 gcc_assert (LABEL_P (operands[0]));
12446 length = get_attr_length (insn);
12449 /* Just a simple conditional branch. */
12450 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
12451 return branch_if_true;
12454 /* Generate a reversed branch around a direct jump. This fallback does
12455 not use branch-likely instructions. */
12456 mips_branch_likely = false;
12457 rtx_code_label *not_taken = gen_label_rtx ();
12458 taken = operands[0];
12460 /* Generate the reversed branch to NOT_TAKEN. */
12461 operands[0] = not_taken;
12462 output_asm_insn (branch_if_false, operands);
12464 /* If INSN has a delay slot, we must provide delay slots for both the
12465 branch to NOT_TAKEN and the conditional jump. We must also ensure
12466 that INSN's delay slot is executed in the appropriate cases. */
12467 if (final_sequence)
12469 /* This first delay slot will always be executed, so use INSN's
12470 delay slot if is not annulled. */
12471 if (!INSN_ANNULLED_BRANCH_P (insn))
12473 final_scan_insn (final_sequence->insn (1),
12474 asm_out_file, optimize, 1, NULL);
12475 final_sequence->insn (1)->set_deleted ();
12478 output_asm_insn ("nop", 0);
12479 fprintf (asm_out_file, "\n");
12482 /* Output the unconditional branch to TAKEN. */
12483 if (TARGET_ABSOLUTE_JUMPS)
12484 output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken);
12487 mips_output_load_label (taken);
12488 output_asm_insn ("jr\t%@%]%/", 0);
12491 /* Now deal with its delay slot; see above. */
12492 if (final_sequence)
12494 /* This delay slot will only be executed if the branch is taken.
12495 Use INSN's delay slot if is annulled. */
12496 if (INSN_ANNULLED_BRANCH_P (insn))
12498 final_scan_insn (final_sequence->insn (1),
12499 asm_out_file, optimize, 1, NULL);
12500 final_sequence->insn (1)->set_deleted ();
12503 output_asm_insn ("nop", 0);
12504 fprintf (asm_out_file, "\n");
12507 /* Output NOT_TAKEN. */
12508 targetm.asm_out.internal_label (asm_out_file, "L",
12509 CODE_LABEL_NUMBER (not_taken));
12513 /* Return the assembly code for INSN, which branches to OPERANDS[0]
12514 if some ordering condition is true. The condition is given by
12515 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
12516 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
12517 its second is always zero. */
12520 mips_output_order_conditional_branch (rtx_insn *insn, rtx *operands, bool inverted_p)
12522 const char *branch[2];
12524 /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true.
12525 Make BRANCH[0] branch on the inverse condition. */
12526 switch (GET_CODE (operands[1]))
12528 /* These cases are equivalent to comparisons against zero. */
12530 inverted_p = !inverted_p;
12531 /* Fall through. */
12533 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%0");
12534 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%0");
12537 /* These cases are always true or always false. */
12539 inverted_p = !inverted_p;
12540 /* Fall through. */
12542 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%0");
12543 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%0");
12547 branch[!inverted_p] = MIPS_BRANCH ("b%C1z", "%2,%0");
12548 branch[inverted_p] = MIPS_BRANCH ("b%N1z", "%2,%0");
12551 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
12554 /* Start a block of code that needs access to the LL, SC and SYNC
12558 mips_start_ll_sc_sync_block (void)
12560 if (!ISA_HAS_LL_SC)
12562 output_asm_insn (".set\tpush", 0);
12564 output_asm_insn (".set\tmips3", 0);
12566 output_asm_insn (".set\tmips2", 0);
12570 /* End a block started by mips_start_ll_sc_sync_block. */
12573 mips_end_ll_sc_sync_block (void)
12575 if (!ISA_HAS_LL_SC)
12576 output_asm_insn (".set\tpop", 0);
12579 /* Output and/or return the asm template for a sync instruction. */
12582 mips_output_sync (void)
12584 mips_start_ll_sc_sync_block ();
12585 output_asm_insn ("sync", 0);
12586 mips_end_ll_sc_sync_block ();
12590 /* Return the asm template associated with sync_insn1 value TYPE.
12591 IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */
12593 static const char *
12594 mips_sync_insn1_template (enum attr_sync_insn1 type, bool is_64bit_p)
12598 case SYNC_INSN1_MOVE:
12599 return "move\t%0,%z2";
12600 case SYNC_INSN1_LI:
12601 return "li\t%0,%2";
12602 case SYNC_INSN1_ADDU:
12603 return is_64bit_p ? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2";
12604 case SYNC_INSN1_ADDIU:
12605 return is_64bit_p ? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2";
12606 case SYNC_INSN1_SUBU:
12607 return is_64bit_p ? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2";
12608 case SYNC_INSN1_AND:
12609 return "and\t%0,%1,%z2";
12610 case SYNC_INSN1_ANDI:
12611 return "andi\t%0,%1,%2";
12612 case SYNC_INSN1_OR:
12613 return "or\t%0,%1,%z2";
12614 case SYNC_INSN1_ORI:
12615 return "ori\t%0,%1,%2";
12616 case SYNC_INSN1_XOR:
12617 return "xor\t%0,%1,%z2";
12618 case SYNC_INSN1_XORI:
12619 return "xori\t%0,%1,%2";
12621 gcc_unreachable ();
12624 /* Return the asm template associated with sync_insn2 value TYPE. */
12626 static const char *
12627 mips_sync_insn2_template (enum attr_sync_insn2 type)
12631 case SYNC_INSN2_NOP:
12632 gcc_unreachable ();
12633 case SYNC_INSN2_AND:
12634 return "and\t%0,%1,%z2";
12635 case SYNC_INSN2_XOR:
12636 return "xor\t%0,%1,%z2";
12637 case SYNC_INSN2_NOT:
12638 return "nor\t%0,%1,%.";
12640 gcc_unreachable ();
12643 /* OPERANDS are the operands to a sync loop instruction and INDEX is
12644 the value of the one of the sync_* attributes. Return the operand
12645 referred to by the attribute, or DEFAULT_VALUE if the insn doesn't
12646 have the associated attribute. */
12649 mips_get_sync_operand (rtx *operands, int index, rtx default_value)
12652 default_value = operands[index - 1];
12653 return default_value;
12656 /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn
12657 sequence for it. */
12660 mips_process_sync_loop (rtx_insn *insn, rtx *operands)
12662 rtx at, mem, oldval, newval, inclusive_mask, exclusive_mask;
12663 rtx required_oldval, insn1_op2, tmp1, tmp2, tmp3, cmp;
12664 unsigned int tmp3_insn;
12665 enum attr_sync_insn1 insn1;
12666 enum attr_sync_insn2 insn2;
12669 enum memmodel model;
12671 /* Read an operand from the sync_WHAT attribute and store it in
12672 variable WHAT. DEFAULT is the default value if no attribute
12674 #define READ_OPERAND(WHAT, DEFAULT) \
12675 WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \
12678 /* Read the memory. */
12679 READ_OPERAND (mem, 0);
12681 is_64bit_p = (GET_MODE_BITSIZE (GET_MODE (mem)) == 64);
12683 /* Read the other attributes. */
12684 at = gen_rtx_REG (GET_MODE (mem), AT_REGNUM);
12685 READ_OPERAND (oldval, at);
12686 READ_OPERAND (cmp, 0);
12687 READ_OPERAND (newval, at);
12688 READ_OPERAND (inclusive_mask, 0);
12689 READ_OPERAND (exclusive_mask, 0);
12690 READ_OPERAND (required_oldval, 0);
12691 READ_OPERAND (insn1_op2, 0);
12692 insn1 = get_attr_sync_insn1 (insn);
12693 insn2 = get_attr_sync_insn2 (insn);
12695 /* Don't bother setting CMP result that is never used. */
12696 if (cmp && find_reg_note (insn, REG_UNUSED, cmp))
12699 memmodel_attr = get_attr_sync_memmodel (insn);
12700 switch (memmodel_attr)
12703 model = MEMMODEL_ACQ_REL;
12706 model = MEMMODEL_ACQUIRE;
12709 model = (enum memmodel) INTVAL (operands[memmodel_attr]);
12712 mips_multi_start ();
12714 /* Output the release side of the memory barrier. */
12715 if (need_atomic_barrier_p (model, true))
12717 if (required_oldval == 0 && TARGET_OCTEON)
12719 /* Octeon doesn't reorder reads, so a full barrier can be
12720 created by using SYNCW to order writes combined with the
12721 write from the following SC. When the SC successfully
12722 completes, we know that all preceding writes are also
12723 committed to the coherent memory system. It is possible
12724 for a single SYNCW to fail, but a pair of them will never
12725 fail, so we use two. */
12726 mips_multi_add_insn ("syncw", NULL);
12727 mips_multi_add_insn ("syncw", NULL);
12730 mips_multi_add_insn ("sync", NULL);
12733 /* Output the branch-back label. */
12734 mips_multi_add_label ("1:");
12736 /* OLDVAL = *MEM. */
12737 mips_multi_add_insn (is_64bit_p ? "lld\t%0,%1" : "ll\t%0,%1",
12738 oldval, mem, NULL);
12740 /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */
12741 if (required_oldval)
12743 if (inclusive_mask == 0)
12747 gcc_assert (oldval != at);
12748 mips_multi_add_insn ("and\t%0,%1,%2",
12749 at, oldval, inclusive_mask, NULL);
12752 mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1, required_oldval, NULL);
12754 /* CMP = 0 [delay slot]. */
12756 mips_multi_add_insn ("li\t%0,0", cmp, NULL);
12759 /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */
12760 if (exclusive_mask == 0)
12764 gcc_assert (oldval != at);
12765 mips_multi_add_insn ("and\t%0,%1,%z2",
12766 at, oldval, exclusive_mask, NULL);
12770 /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2).
12772 We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit
12773 at least one instruction in that case. */
12774 if (insn1 == SYNC_INSN1_MOVE
12775 && (tmp1 != const0_rtx || insn2 != SYNC_INSN2_NOP))
12779 mips_multi_add_insn (mips_sync_insn1_template (insn1, is_64bit_p),
12780 newval, oldval, insn1_op2, NULL);
12784 /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */
12785 if (insn2 == SYNC_INSN2_NOP)
12789 mips_multi_add_insn (mips_sync_insn2_template (insn2),
12790 newval, tmp2, inclusive_mask, NULL);
12793 tmp3_insn = mips_multi_last_index ();
12795 /* $AT = $TMP1 | $TMP3. */
12796 if (tmp1 == const0_rtx || tmp3 == const0_rtx)
12798 mips_multi_set_operand (tmp3_insn, 0, at);
12803 gcc_assert (tmp1 != tmp3);
12804 mips_multi_add_insn ("or\t%0,%1,%2", at, tmp1, tmp3, NULL);
12807 /* if (!commit (*MEM = $AT)) goto 1.
12809 This will sometimes be a delayed branch; see the write code below
12811 mips_multi_add_insn (is_64bit_p ? "scd\t%0,%1" : "sc\t%0,%1", at, mem, NULL);
12812 mips_multi_add_insn ("beq%?\t%0,%.,1b", at, NULL);
12814 /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */
12815 if (insn1 != SYNC_INSN1_MOVE && insn1 != SYNC_INSN1_LI && tmp3 != newval)
12817 mips_multi_copy_insn (tmp3_insn);
12818 mips_multi_set_operand (mips_multi_last_index (), 0, newval);
12820 else if (!(required_oldval && cmp))
12821 mips_multi_add_insn ("nop", NULL);
12823 /* CMP = 1 -- either standalone or in a delay slot. */
12824 if (required_oldval && cmp)
12825 mips_multi_add_insn ("li\t%0,1", cmp, NULL);
12827 /* Output the acquire side of the memory barrier. */
12828 if (TARGET_SYNC_AFTER_SC && need_atomic_barrier_p (model, false))
12829 mips_multi_add_insn ("sync", NULL);
12831 /* Output the exit label, if needed. */
12832 if (required_oldval)
12833 mips_multi_add_label ("2:");
12835 #undef READ_OPERAND
12838 /* Output and/or return the asm template for sync loop INSN, which has
12839 the operands given by OPERANDS. */
12842 mips_output_sync_loop (rtx_insn *insn, rtx *operands)
12844 mips_process_sync_loop (insn, operands);
12846 /* Use branch-likely instructions to work around the LL/SC R10000
12848 mips_branch_likely = TARGET_FIX_R10000;
12850 mips_push_asm_switch (&mips_noreorder);
12851 mips_push_asm_switch (&mips_nomacro);
12852 mips_push_asm_switch (&mips_noat);
12853 mips_start_ll_sc_sync_block ();
12855 mips_multi_write ();
12857 mips_end_ll_sc_sync_block ();
12858 mips_pop_asm_switch (&mips_noat);
12859 mips_pop_asm_switch (&mips_nomacro);
12860 mips_pop_asm_switch (&mips_noreorder);
12865 /* Return the number of individual instructions in sync loop INSN,
12866 which has the operands given by OPERANDS. */
12869 mips_sync_loop_insns (rtx_insn *insn, rtx *operands)
12871 mips_process_sync_loop (insn, operands);
12872 return mips_multi_num_insns;
12875 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
12876 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
12878 When working around R4000 and R4400 errata, we need to make sure that
12879 the division is not immediately followed by a shift[1][2]. We also
12880 need to stop the division from being put into a branch delay slot[3].
12881 The easiest way to avoid both problems is to add a nop after the
12882 division. When a divide-by-zero check is needed, this nop can be
12883 used to fill the branch delay slot.
12885 [1] If a double-word or a variable shift executes immediately
12886 after starting an integer division, the shift may give an
12887 incorrect result. See quotations of errata #16 and #28 from
12888 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
12889 in mips.md for details.
12891 [2] A similar bug to [1] exists for all revisions of the
12892 R4000 and the R4400 when run in an MC configuration.
12893 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
12895 "19. In this following sequence:
12897 ddiv (or ddivu or div or divu)
12898 dsll32 (or dsrl32, dsra32)
12900 if an MPT stall occurs, while the divide is slipping the cpu
12901 pipeline, then the following double shift would end up with an
12904 Workaround: The compiler needs to avoid generating any
12905 sequence with divide followed by extended double shift."
12907 This erratum is also present in "MIPS R4400MC Errata, Processor
12908 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
12909 & 3.0" as errata #10 and #4, respectively.
12911 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
12912 (also valid for MIPS R4000MC processors):
12914 "52. R4000SC: This bug does not apply for the R4000PC.
12916 There are two flavors of this bug:
12918 1) If the instruction just after divide takes an RF exception
12919 (tlb-refill, tlb-invalid) and gets an instruction cache
12920 miss (both primary and secondary) and the line which is
12921 currently in secondary cache at this index had the first
12922 data word, where the bits 5..2 are set, then R4000 would
12923 get a wrong result for the div.
12928 ------------------- # end-of page. -tlb-refill
12933 ------------------- # end-of page. -tlb-invalid
12936 2) If the divide is in the taken branch delay slot, where the
12937 target takes RF exception and gets an I-cache miss for the
12938 exception vector or where I-cache miss occurs for the
12939 target address, under the above mentioned scenarios, the
12940 div would get wrong results.
12943 j r2 # to next page mapped or unmapped
12944 div r8,r9 # this bug would be there as long
12945 # as there is an ICache miss and
12946 nop # the "data pattern" is present
12949 beq r0, r0, NextPage # to Next page
12953 This bug is present for div, divu, ddiv, and ddivu
12956 Workaround: For item 1), OS could make sure that the next page
12957 after the divide instruction is also mapped. For item 2), the
12958 compiler could make sure that the divide instruction is not in
12959 the branch delay slot."
12961 These processors have PRId values of 0x00004220 and 0x00004300 for
12962 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
12965 mips_output_division (const char *division, rtx *operands)
12970 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
12972 output_asm_insn (s, operands);
12975 if (TARGET_CHECK_ZERO_DIV)
12979 output_asm_insn (s, operands);
12980 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
12982 else if (GENERATE_DIVIDE_TRAPS)
12984 /* Avoid long replay penalty on load miss by putting the trap before
12987 output_asm_insn ("teq\t%2,%.,7", operands);
12990 output_asm_insn (s, operands);
12991 s = "teq\t%2,%.,7";
12996 output_asm_insn ("%(bne\t%2,%.,1f", operands);
12997 output_asm_insn (s, operands);
12998 s = "break\t7%)\n1:";
13004 /* Return true if destination of IN_INSN is used as add source in
13005 OUT_INSN. Both IN_INSN and OUT_INSN are of type fmadd. Example:
13006 madd.s dst, x, y, z
13007 madd.s a, dst, b, c */
13010 mips_fmadd_bypass (rtx_insn *out_insn, rtx_insn *in_insn)
13012 int dst_reg, src_reg;
13014 gcc_assert (get_attr_type (in_insn) == TYPE_FMADD);
13015 gcc_assert (get_attr_type (out_insn) == TYPE_FMADD);
13017 extract_insn (in_insn);
13018 dst_reg = REG_P (recog_data.operand[0]);
13020 extract_insn (out_insn);
13021 src_reg = REG_P (recog_data.operand[1]);
13023 if (dst_reg == src_reg)
13029 /* Return true if IN_INSN is a multiply-add or multiply-subtract
13030 instruction and if OUT_INSN assigns to the accumulator operand. */
13033 mips_linked_madd_p (rtx_insn *out_insn, rtx_insn *in_insn)
13035 enum attr_accum_in accum_in;
13036 int accum_in_opnum;
13039 if (recog_memoized (in_insn) < 0)
13042 accum_in = get_attr_accum_in (in_insn);
13043 if (accum_in == ACCUM_IN_NONE)
13046 accum_in_opnum = accum_in - ACCUM_IN_0;
13048 extract_insn (in_insn);
13049 gcc_assert (accum_in_opnum < recog_data.n_operands);
13050 accum_in_op = recog_data.operand[accum_in_opnum];
13052 return reg_set_p (accum_in_op, out_insn);
13055 /* True if the dependency between OUT_INSN and IN_INSN is on the store
13056 data rather than the address. We need this because the cprestore
13057 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
13058 which causes the default routine to abort. We just return false
13062 mips_store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
13064 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
13067 return !store_data_bypass_p (out_insn, in_insn);
13071 /* Variables and flags used in scheduler hooks when tuning for
13075 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
13078 /* If true, then next ALU1/2 instruction will go to ALU1. */
13081 /* If true, then next FALU1/2 unstruction will go to FALU1. */
13084 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
13085 int alu1_core_unit_code;
13086 int alu2_core_unit_code;
13087 int falu1_core_unit_code;
13088 int falu2_core_unit_code;
13090 /* True if current cycle has a multi instruction.
13091 This flag is used in mips_ls2_dfa_post_advance_cycle. */
13092 bool cycle_has_multi_p;
13094 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
13095 These are used in mips_ls2_dfa_post_advance_cycle to initialize
13097 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
13098 instruction to go ALU1. */
13099 rtx_insn *alu1_turn_enabled_insn;
13100 rtx_insn *alu2_turn_enabled_insn;
13101 rtx_insn *falu1_turn_enabled_insn;
13102 rtx_insn *falu2_turn_enabled_insn;
13105 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
13106 dependencies have no cost, except on the 20Kc where output-dependence
13107 is treated like input-dependence. */
13110 mips_adjust_cost (rtx_insn *insn ATTRIBUTE_UNUSED, rtx link,
13111 rtx_insn *dep ATTRIBUTE_UNUSED, int cost)
13113 if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT
13116 if (REG_NOTE_KIND (link) != 0)
13121 /* Return the number of instructions that can be issued per cycle. */
13124 mips_issue_rate (void)
13128 case PROCESSOR_74KC:
13129 case PROCESSOR_74KF2_1:
13130 case PROCESSOR_74KF1_1:
13131 case PROCESSOR_74KF3_2:
13132 /* The 74k is not strictly quad-issue cpu, but can be seen as one
13133 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
13134 but in reality only a maximum of 3 insns can be issued as
13135 floating-point loads and stores also require a slot in the
13137 case PROCESSOR_R10000:
13138 /* All R10K Processors are quad-issue (being the first MIPS
13139 processors to support this feature). */
13142 case PROCESSOR_20KC:
13143 case PROCESSOR_R4130:
13144 case PROCESSOR_R5400:
13145 case PROCESSOR_R5500:
13146 case PROCESSOR_R5900:
13147 case PROCESSOR_R7000:
13148 case PROCESSOR_R9000:
13149 case PROCESSOR_OCTEON:
13150 case PROCESSOR_OCTEON2:
13153 case PROCESSOR_SB1:
13154 case PROCESSOR_SB1A:
13155 /* This is actually 4, but we get better performance if we claim 3.
13156 This is partly because of unwanted speculative code motion with the
13157 larger number, and partly because in most common cases we can't
13158 reach the theoretical max of 4. */
13161 case PROCESSOR_LOONGSON_2E:
13162 case PROCESSOR_LOONGSON_2F:
13163 case PROCESSOR_LOONGSON_3A:
13164 case PROCESSOR_P5600:
13167 case PROCESSOR_XLP:
13168 return (reload_completed ? 4 : 3);
13175 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
13178 mips_ls2_init_dfa_post_cycle_insn (void)
13181 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
13182 mips_ls2.alu1_turn_enabled_insn = get_insns ();
13186 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
13187 mips_ls2.alu2_turn_enabled_insn = get_insns ();
13191 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
13192 mips_ls2.falu1_turn_enabled_insn = get_insns ();
13196 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
13197 mips_ls2.falu2_turn_enabled_insn = get_insns ();
13200 mips_ls2.alu1_core_unit_code = get_cpu_unit_code ("ls2_alu1_core");
13201 mips_ls2.alu2_core_unit_code = get_cpu_unit_code ("ls2_alu2_core");
13202 mips_ls2.falu1_core_unit_code = get_cpu_unit_code ("ls2_falu1_core");
13203 mips_ls2.falu2_core_unit_code = get_cpu_unit_code ("ls2_falu2_core");
13206 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
13207 Init data used in mips_dfa_post_advance_cycle. */
13210 mips_init_dfa_post_cycle_insn (void)
13212 if (TUNE_LOONGSON_2EF)
13213 mips_ls2_init_dfa_post_cycle_insn ();
13216 /* Initialize STATE when scheduling for Loongson 2E/2F.
13217 Support round-robin dispatch scheme by enabling only one of
13218 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
13222 mips_ls2_dfa_post_advance_cycle (state_t state)
13224 if (cpu_unit_reservation_p (state, mips_ls2.alu1_core_unit_code))
13226 /* Though there are no non-pipelined ALU1 insns,
13227 we can get an instruction of type 'multi' before reload. */
13228 gcc_assert (mips_ls2.cycle_has_multi_p);
13229 mips_ls2.alu1_turn_p = false;
13232 mips_ls2.cycle_has_multi_p = false;
13234 if (cpu_unit_reservation_p (state, mips_ls2.alu2_core_unit_code))
13235 /* We have a non-pipelined alu instruction in the core,
13236 adjust round-robin counter. */
13237 mips_ls2.alu1_turn_p = true;
13239 if (mips_ls2.alu1_turn_p)
13241 if (state_transition (state, mips_ls2.alu1_turn_enabled_insn) >= 0)
13242 gcc_unreachable ();
13246 if (state_transition (state, mips_ls2.alu2_turn_enabled_insn) >= 0)
13247 gcc_unreachable ();
13250 if (cpu_unit_reservation_p (state, mips_ls2.falu1_core_unit_code))
13252 /* There are no non-pipelined FALU1 insns. */
13253 gcc_unreachable ();
13254 mips_ls2.falu1_turn_p = false;
13257 if (cpu_unit_reservation_p (state, mips_ls2.falu2_core_unit_code))
13258 /* We have a non-pipelined falu instruction in the core,
13259 adjust round-robin counter. */
13260 mips_ls2.falu1_turn_p = true;
13262 if (mips_ls2.falu1_turn_p)
13264 if (state_transition (state, mips_ls2.falu1_turn_enabled_insn) >= 0)
13265 gcc_unreachable ();
13269 if (state_transition (state, mips_ls2.falu2_turn_enabled_insn) >= 0)
13270 gcc_unreachable ();
13274 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
13275 This hook is being called at the start of each cycle. */
13278 mips_dfa_post_advance_cycle (void)
13280 if (TUNE_LOONGSON_2EF)
13281 mips_ls2_dfa_post_advance_cycle (curr_state);
13284 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
13285 be as wide as the scheduling freedom in the DFA. */
13288 mips_multipass_dfa_lookahead (void)
13290 /* Can schedule up to 4 of the 6 function units in any one cycle. */
13294 if (TUNE_LOONGSON_2EF || TUNE_LOONGSON_3A)
13306 /* Remove the instruction at index LOWER from ready queue READY and
13307 reinsert it in front of the instruction at index HIGHER. LOWER must
13311 mips_promote_ready (rtx_insn **ready, int lower, int higher)
13313 rtx_insn *new_head;
13316 new_head = ready[lower];
13317 for (i = lower; i < higher; i++)
13318 ready[i] = ready[i + 1];
13319 ready[i] = new_head;
13322 /* If the priority of the instruction at POS2 in the ready queue READY
13323 is within LIMIT units of that of the instruction at POS1, swap the
13324 instructions if POS2 is not already less than POS1. */
13327 mips_maybe_swap_ready (rtx_insn **ready, int pos1, int pos2, int limit)
13330 && INSN_PRIORITY (ready[pos1]) + limit >= INSN_PRIORITY (ready[pos2]))
13334 temp = ready[pos1];
13335 ready[pos1] = ready[pos2];
13336 ready[pos2] = temp;
13340 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
13341 that may clobber hi or lo. */
13342 static rtx_insn *mips_macc_chains_last_hilo;
13344 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
13345 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
13348 mips_macc_chains_record (rtx_insn *insn)
13350 if (get_attr_may_clobber_hilo (insn))
13351 mips_macc_chains_last_hilo = insn;
13354 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
13355 has NREADY elements, looking for a multiply-add or multiply-subtract
13356 instruction that is cumulative with mips_macc_chains_last_hilo.
13357 If there is one, promote it ahead of anything else that might
13358 clobber hi or lo. */
13361 mips_macc_chains_reorder (rtx_insn **ready, int nready)
13365 if (mips_macc_chains_last_hilo != 0)
13366 for (i = nready - 1; i >= 0; i--)
13367 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
13369 for (j = nready - 1; j > i; j--)
13370 if (recog_memoized (ready[j]) >= 0
13371 && get_attr_may_clobber_hilo (ready[j]))
13373 mips_promote_ready (ready, i, j);
13380 /* The last instruction to be scheduled. */
13381 static rtx_insn *vr4130_last_insn;
13383 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
13384 points to an rtx that is initially an instruction. Nullify the rtx
13385 if the instruction uses the value of register X. */
13388 vr4130_true_reg_dependence_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
13393 insn_ptr = (rtx *) data;
13396 && reg_referenced_p (x, PATTERN (*insn_ptr)))
13400 /* Return true if there is true register dependence between vr4130_last_insn
13404 vr4130_true_reg_dependence_p (rtx insn)
13406 note_stores (PATTERN (vr4130_last_insn),
13407 vr4130_true_reg_dependence_p_1, &insn);
13411 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
13412 the ready queue and that INSN2 is the instruction after it, return
13413 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
13414 in which INSN1 and INSN2 can probably issue in parallel, but for
13415 which (INSN2, INSN1) should be less sensitive to instruction
13416 alignment than (INSN1, INSN2). See 4130.md for more details. */
13419 vr4130_swap_insns_p (rtx_insn *insn1, rtx_insn *insn2)
13421 sd_iterator_def sd_it;
13424 /* Check for the following case:
13426 1) there is some other instruction X with an anti dependence on INSN1;
13427 2) X has a higher priority than INSN2; and
13428 3) X is an arithmetic instruction (and thus has no unit restrictions).
13430 If INSN1 is the last instruction blocking X, it would better to
13431 choose (INSN1, X) over (INSN2, INSN1). */
13432 FOR_EACH_DEP (insn1, SD_LIST_FORW, sd_it, dep)
13433 if (DEP_TYPE (dep) == REG_DEP_ANTI
13434 && INSN_PRIORITY (DEP_CON (dep)) > INSN_PRIORITY (insn2)
13435 && recog_memoized (DEP_CON (dep)) >= 0
13436 && get_attr_vr4130_class (DEP_CON (dep)) == VR4130_CLASS_ALU)
13439 if (vr4130_last_insn != 0
13440 && recog_memoized (insn1) >= 0
13441 && recog_memoized (insn2) >= 0)
13443 /* See whether INSN1 and INSN2 use different execution units,
13444 or if they are both ALU-type instructions. If so, they can
13445 probably execute in parallel. */
13446 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
13447 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
13448 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
13450 /* If only one of the instructions has a dependence on
13451 vr4130_last_insn, prefer to schedule the other one first. */
13452 bool dep1_p = vr4130_true_reg_dependence_p (insn1);
13453 bool dep2_p = vr4130_true_reg_dependence_p (insn2);
13454 if (dep1_p != dep2_p)
13457 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
13458 is not an ALU-type instruction and if INSN1 uses the same
13459 execution unit. (Note that if this condition holds, we already
13460 know that INSN2 uses a different execution unit.) */
13461 if (class1 != VR4130_CLASS_ALU
13462 && recog_memoized (vr4130_last_insn) >= 0
13463 && class1 == get_attr_vr4130_class (vr4130_last_insn))
13470 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
13471 queue with at least two instructions. Swap the first two if
13472 vr4130_swap_insns_p says that it could be worthwhile. */
13475 vr4130_reorder (rtx_insn **ready, int nready)
13477 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
13478 mips_promote_ready (ready, nready - 2, nready - 1);
13481 /* Record whether last 74k AGEN instruction was a load or store. */
13482 static enum attr_type mips_last_74k_agen_insn = TYPE_UNKNOWN;
13484 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
13485 resets to TYPE_UNKNOWN state. */
13488 mips_74k_agen_init (rtx_insn *insn)
13490 if (!insn || CALL_P (insn) || JUMP_P (insn))
13491 mips_last_74k_agen_insn = TYPE_UNKNOWN;
13494 enum attr_type type = get_attr_type (insn);
13495 if (type == TYPE_LOAD || type == TYPE_STORE)
13496 mips_last_74k_agen_insn = type;
13500 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
13501 loads to be grouped together, and multiple stores to be grouped
13502 together. Swap things around in the ready queue to make this happen. */
13505 mips_74k_agen_reorder (rtx_insn **ready, int nready)
13508 int store_pos, load_pos;
13513 for (i = nready - 1; i >= 0; i--)
13515 rtx_insn *insn = ready[i];
13516 if (USEFUL_INSN_P (insn))
13517 switch (get_attr_type (insn))
13520 if (store_pos == -1)
13525 if (load_pos == -1)
13534 if (load_pos == -1 || store_pos == -1)
13537 switch (mips_last_74k_agen_insn)
13540 /* Prefer to schedule loads since they have a higher latency. */
13542 /* Swap loads to the front of the queue. */
13543 mips_maybe_swap_ready (ready, load_pos, store_pos, 4);
13546 /* Swap stores to the front of the queue. */
13547 mips_maybe_swap_ready (ready, store_pos, load_pos, 4);
13554 /* Implement TARGET_SCHED_INIT. */
13557 mips_sched_init (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13558 int max_ready ATTRIBUTE_UNUSED)
13560 mips_macc_chains_last_hilo = 0;
13561 vr4130_last_insn = 0;
13562 mips_74k_agen_init (NULL);
13564 /* When scheduling for Loongson2, branch instructions go to ALU1,
13565 therefore basic block is most likely to start with round-robin counter
13566 pointed to ALU2. */
13567 mips_ls2.alu1_turn_p = false;
13568 mips_ls2.falu1_turn_p = true;
13571 /* Subroutine used by TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
13574 mips_sched_reorder_1 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13575 rtx_insn **ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
13577 if (!reload_completed
13578 && TUNE_MACC_CHAINS
13580 mips_macc_chains_reorder (ready, *nreadyp);
13582 if (reload_completed
13584 && !TARGET_VR4130_ALIGN
13586 vr4130_reorder (ready, *nreadyp);
13589 mips_74k_agen_reorder (ready, *nreadyp);
13592 /* Implement TARGET_SCHED_REORDER. */
13595 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13596 rtx_insn **ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
13598 mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle);
13599 return mips_issue_rate ();
13602 /* Implement TARGET_SCHED_REORDER2. */
13605 mips_sched_reorder2 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13606 rtx_insn **ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
13608 mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle);
13609 return cached_can_issue_more;
13612 /* Update round-robin counters for ALU1/2 and FALU1/2. */
13615 mips_ls2_variable_issue (rtx_insn *insn)
13617 if (mips_ls2.alu1_turn_p)
13619 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu1_core_unit_code))
13620 mips_ls2.alu1_turn_p = false;
13624 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu2_core_unit_code))
13625 mips_ls2.alu1_turn_p = true;
13628 if (mips_ls2.falu1_turn_p)
13630 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu1_core_unit_code))
13631 mips_ls2.falu1_turn_p = false;
13635 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu2_core_unit_code))
13636 mips_ls2.falu1_turn_p = true;
13639 if (recog_memoized (insn) >= 0)
13640 mips_ls2.cycle_has_multi_p |= (get_attr_type (insn) == TYPE_MULTI);
13643 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
13646 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13647 rtx_insn *insn, int more)
13649 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
13650 if (USEFUL_INSN_P (insn))
13652 if (get_attr_type (insn) != TYPE_GHOST)
13654 if (!reload_completed && TUNE_MACC_CHAINS)
13655 mips_macc_chains_record (insn);
13656 vr4130_last_insn = insn;
13658 mips_74k_agen_init (insn);
13659 else if (TUNE_LOONGSON_2EF)
13660 mips_ls2_variable_issue (insn);
13663 /* Instructions of type 'multi' should all be split before
13664 the second scheduling pass. */
13665 gcc_assert (!reload_completed
13666 || recog_memoized (insn) < 0
13667 || get_attr_type (insn) != TYPE_MULTI);
13669 cached_can_issue_more = more;
13673 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
13674 return the first operand of the associated PREF or PREFX insn. */
13677 mips_prefetch_cookie (rtx write, rtx locality)
13679 /* store_streamed / load_streamed. */
13680 if (INTVAL (locality) <= 0)
13681 return GEN_INT (INTVAL (write) + 4);
13683 /* store / load. */
13684 if (INTVAL (locality) <= 2)
13687 /* store_retained / load_retained. */
13688 return GEN_INT (INTVAL (write) + 6);
13691 /* Flags that indicate when a built-in function is available.
13693 BUILTIN_AVAIL_NON_MIPS16
13694 The function is available on the current target if !TARGET_MIPS16.
13696 BUILTIN_AVAIL_MIPS16
13697 The function is available on the current target if TARGET_MIPS16. */
13698 #define BUILTIN_AVAIL_NON_MIPS16 1
13699 #define BUILTIN_AVAIL_MIPS16 2
13701 /* Declare an availability predicate for built-in functions that
13702 require non-MIPS16 mode and also require COND to be true.
13703 NAME is the main part of the predicate's name. */
13704 #define AVAIL_NON_MIPS16(NAME, COND) \
13705 static unsigned int \
13706 mips_builtin_avail_##NAME (void) \
13708 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
13711 /* Declare an availability predicate for built-in functions that
13712 support both MIPS16 and non-MIPS16 code and also require COND
13713 to be true. NAME is the main part of the predicate's name. */
13714 #define AVAIL_ALL(NAME, COND) \
13715 static unsigned int \
13716 mips_builtin_avail_##NAME (void) \
13718 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 | BUILTIN_AVAIL_MIPS16 : 0; \
13721 /* This structure describes a single built-in function. */
13722 struct mips_builtin_description {
13723 /* The code of the main .md file instruction. See mips_builtin_type
13724 for more information. */
13725 enum insn_code icode;
13727 /* The floating-point comparison code to use with ICODE, if any. */
13728 enum mips_fp_condition cond;
13730 /* The name of the built-in function. */
13733 /* Specifies how the function should be expanded. */
13734 enum mips_builtin_type builtin_type;
13736 /* The function's prototype. */
13737 enum mips_function_type function_type;
13739 /* Whether the function is available. */
13740 unsigned int (*avail) (void);
13743 AVAIL_ALL (hard_float, TARGET_HARD_FLOAT_ABI)
13744 AVAIL_NON_MIPS16 (paired_single, TARGET_PAIRED_SINGLE_FLOAT)
13745 AVAIL_NON_MIPS16 (sb1_paired_single, TARGET_SB1 && TARGET_PAIRED_SINGLE_FLOAT)
13746 AVAIL_NON_MIPS16 (mips3d, TARGET_MIPS3D)
13747 AVAIL_NON_MIPS16 (dsp, TARGET_DSP)
13748 AVAIL_NON_MIPS16 (dspr2, TARGET_DSPR2)
13749 AVAIL_NON_MIPS16 (dsp_32, !TARGET_64BIT && TARGET_DSP)
13750 AVAIL_NON_MIPS16 (dsp_64, TARGET_64BIT && TARGET_DSP)
13751 AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2)
13752 AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS)
13753 AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
13755 /* Construct a mips_builtin_description from the given arguments.
13757 INSN is the name of the associated instruction pattern, without the
13758 leading CODE_FOR_mips_.
13760 CODE is the floating-point condition code associated with the
13761 function. It can be 'f' if the field is not applicable.
13763 NAME is the name of the function itself, without the leading
13766 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
13768 AVAIL is the name of the availability predicate, without the leading
13769 mips_builtin_avail_. */
13770 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
13771 FUNCTION_TYPE, AVAIL) \
13772 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
13773 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
13774 mips_builtin_avail_ ## AVAIL }
13776 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
13777 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
13778 are as for MIPS_BUILTIN. */
13779 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
13780 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
13782 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
13783 are subject to mips_builtin_avail_<AVAIL>. */
13784 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
13785 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
13786 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
13787 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
13788 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
13790 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
13791 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
13792 while the any and all forms are subject to mips_builtin_avail_mips3d. */
13793 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
13794 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
13795 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
13797 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
13798 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
13800 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
13801 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
13803 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
13804 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
13807 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
13808 are subject to mips_builtin_avail_mips3d. */
13809 #define CMP_4S_BUILTINS(INSN, COND) \
13810 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
13811 MIPS_BUILTIN_CMP_ANY, \
13812 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
13813 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
13814 MIPS_BUILTIN_CMP_ALL, \
13815 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
13817 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
13818 instruction requires mips_builtin_avail_<AVAIL>. */
13819 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
13820 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
13821 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
13823 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
13824 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
13827 /* Define all the built-in functions related to C.cond.fmt condition COND. */
13828 #define CMP_BUILTINS(COND) \
13829 MOVTF_BUILTINS (c, COND, paired_single), \
13830 MOVTF_BUILTINS (cabs, COND, mips3d), \
13831 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
13832 CMP_PS_BUILTINS (c, COND, paired_single), \
13833 CMP_PS_BUILTINS (cabs, COND, mips3d), \
13834 CMP_4S_BUILTINS (c, COND), \
13835 CMP_4S_BUILTINS (cabs, COND)
13837 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
13838 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
13839 and AVAIL are as for MIPS_BUILTIN. */
13840 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
13841 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
13842 FUNCTION_TYPE, AVAIL)
13844 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
13845 branch instruction. AVAIL is as for MIPS_BUILTIN. */
13846 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
13847 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
13848 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
13850 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
13851 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
13852 builtin_description field. */
13853 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
13854 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
13855 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
13856 FUNCTION_TYPE, mips_builtin_avail_loongson }
13858 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
13859 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
13860 builtin_description field. */
13861 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
13862 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
13864 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
13865 We use functions of this form when the same insn can be usefully applied
13866 to more than one datatype. */
13867 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
13868 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
13870 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
13871 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
13872 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
13873 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
13874 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
13875 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
13876 #define CODE_FOR_mips_mult CODE_FOR_mulsidi3_32bit
13877 #define CODE_FOR_mips_multu CODE_FOR_umulsidi3_32bit
13879 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
13880 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
13881 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
13882 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
13883 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
13884 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
13885 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
13886 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
13887 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
13888 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
13889 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
13890 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
13891 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
13892 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
13893 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
13894 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
13895 #define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3
13896 #define CODE_FOR_loongson_psllh CODE_FOR_ashlv4hi3
13897 #define CODE_FOR_loongson_psllw CODE_FOR_ashlv2si3
13898 #define CODE_FOR_loongson_psrlh CODE_FOR_lshrv4hi3
13899 #define CODE_FOR_loongson_psrlw CODE_FOR_lshrv2si3
13900 #define CODE_FOR_loongson_psrah CODE_FOR_ashrv4hi3
13901 #define CODE_FOR_loongson_psraw CODE_FOR_ashrv2si3
13902 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
13903 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
13904 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
13905 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
13906 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
13907 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
13908 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
13910 static const struct mips_builtin_description mips_builtins[] = {
13911 #define MIPS_GET_FCSR 0
13912 DIRECT_BUILTIN (get_fcsr, MIPS_USI_FTYPE_VOID, hard_float),
13913 #define MIPS_SET_FCSR 1
13914 DIRECT_NO_TARGET_BUILTIN (set_fcsr, MIPS_VOID_FTYPE_USI, hard_float),
13916 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13917 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13918 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13919 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13920 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, paired_single),
13921 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, paired_single),
13922 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, paired_single),
13923 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, paired_single),
13925 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT, paired_single),
13926 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13927 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13928 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
13929 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, mips3d),
13931 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, mips3d),
13932 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, mips3d),
13933 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
13934 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
13935 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
13936 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13938 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, mips3d),
13939 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, mips3d),
13940 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
13941 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
13942 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
13943 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13945 MIPS_FP_CONDITIONS (CMP_BUILTINS),
13947 /* Built-in functions for the SB-1 processor. */
13948 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, sb1_paired_single),
13950 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
13951 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13952 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13953 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
13954 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13955 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13956 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13957 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13958 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
13959 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13960 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13961 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, dsp),
13962 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, dsp),
13963 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, dsp),
13964 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, dsp),
13965 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, dsp),
13966 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, dsp),
13967 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
13968 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
13969 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
13970 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
13971 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, dsp),
13972 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, dsp),
13973 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
13974 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
13975 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
13976 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
13977 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
13978 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
13979 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
13980 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
13981 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
13982 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
13983 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
13984 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
13985 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
13986 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
13987 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
13988 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, dsp),
13989 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
13990 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
13991 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13992 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
13993 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
13994 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, dsp),
13995 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, dsp),
13996 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, dsp),
13997 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, dsp),
13998 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
13999 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
14000 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
14001 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
14002 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
14003 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
14004 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
14005 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
14006 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
14007 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
14008 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
14009 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
14010 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, dsp),
14011 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, dsp),
14012 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_POINTER_SI, dsp),
14013 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_POINTER_SI, dsp),
14014 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_POINTER_SI, dsp),
14015 BPOSGE_BUILTIN (32, dsp),
14017 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
14018 DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, dspr2),
14019 DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14020 DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14021 DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
14022 DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
14023 DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
14024 DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
14025 DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
14026 DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
14027 DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
14028 DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14029 DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14030 DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, dspr2),
14031 DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14032 DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, dspr2),
14033 DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dspr2),
14034 DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
14035 DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
14036 DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
14037 DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
14038 DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
14039 DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, dspr2),
14040 DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14041 DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14042 DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
14043 DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
14044 DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14045 DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14046 DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
14047 DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
14048 DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14049 DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14050 DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
14051 DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
14053 /* Built-in functions for the DSP ASE (32-bit only). */
14054 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
14055 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
14056 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
14057 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
14058 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
14059 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
14060 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
14061 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
14062 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
14063 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
14064 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
14065 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
14066 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
14067 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
14068 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
14069 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
14070 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, dsp_32),
14071 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, dsp_32),
14072 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, dsp_32),
14073 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, dsp_32),
14074 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, dsp_32),
14075 DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
14076 DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32),
14077 DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
14078 DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32),
14079 DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, dsp_32),
14080 DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, dsp_32),
14082 /* Built-in functions for the DSP ASE (64-bit only). */
14083 DIRECT_BUILTIN (ldx, MIPS_DI_FTYPE_POINTER_SI, dsp_64),
14085 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
14086 DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14087 DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14088 DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14089 DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14090 DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14091 DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14092 DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14093 DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14094 DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14096 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
14097 LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI),
14098 LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI),
14099 LOONGSON_BUILTIN (packushb, MIPS_UV8QI_FTYPE_UV4HI_UV4HI),
14100 LOONGSON_BUILTIN_SUFFIX (paddw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14101 LOONGSON_BUILTIN_SUFFIX (paddh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14102 LOONGSON_BUILTIN_SUFFIX (paddb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14103 LOONGSON_BUILTIN_SUFFIX (paddw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14104 LOONGSON_BUILTIN_SUFFIX (paddh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14105 LOONGSON_BUILTIN_SUFFIX (paddb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14106 LOONGSON_BUILTIN_SUFFIX (paddd, u, MIPS_UDI_FTYPE_UDI_UDI),
14107 LOONGSON_BUILTIN_SUFFIX (paddd, s, MIPS_DI_FTYPE_DI_DI),
14108 LOONGSON_BUILTIN (paddsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14109 LOONGSON_BUILTIN (paddsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
14110 LOONGSON_BUILTIN (paddush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14111 LOONGSON_BUILTIN (paddusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14112 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_ud, MIPS_UDI_FTYPE_UDI_UDI),
14113 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_uw, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14114 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_uh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14115 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_ub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14116 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_sd, MIPS_DI_FTYPE_DI_DI),
14117 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_sw, MIPS_V2SI_FTYPE_V2SI_V2SI),
14118 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_sh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14119 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_sb, MIPS_V8QI_FTYPE_V8QI_V8QI),
14120 LOONGSON_BUILTIN (pavgh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14121 LOONGSON_BUILTIN (pavgb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14122 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14123 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14124 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14125 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14126 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14127 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14128 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14129 LOONGSON_BUILTIN_SUFFIX (pcmpgth, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14130 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14131 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14132 LOONGSON_BUILTIN_SUFFIX (pcmpgth, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14133 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14134 LOONGSON_BUILTIN_SUFFIX (pextrh, u, MIPS_UV4HI_FTYPE_UV4HI_USI),
14135 LOONGSON_BUILTIN_SUFFIX (pextrh, s, MIPS_V4HI_FTYPE_V4HI_USI),
14136 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14137 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14138 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14139 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14140 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14141 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14142 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14143 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14144 LOONGSON_BUILTIN (pmaddhw, MIPS_V2SI_FTYPE_V4HI_V4HI),
14145 LOONGSON_BUILTIN (pmaxsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14146 LOONGSON_BUILTIN (pmaxub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14147 LOONGSON_BUILTIN (pminsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14148 LOONGSON_BUILTIN (pminub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14149 LOONGSON_BUILTIN_SUFFIX (pmovmskb, u, MIPS_UV8QI_FTYPE_UV8QI),
14150 LOONGSON_BUILTIN_SUFFIX (pmovmskb, s, MIPS_V8QI_FTYPE_V8QI),
14151 LOONGSON_BUILTIN (pmulhuh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14152 LOONGSON_BUILTIN (pmulhh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14153 LOONGSON_BUILTIN (pmullh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14154 LOONGSON_BUILTIN (pmuluw, MIPS_UDI_FTYPE_UV2SI_UV2SI),
14155 LOONGSON_BUILTIN (pasubub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14156 LOONGSON_BUILTIN (biadd, MIPS_UV4HI_FTYPE_UV8QI),
14157 LOONGSON_BUILTIN (psadbh, MIPS_UV4HI_FTYPE_UV8QI_UV8QI),
14158 LOONGSON_BUILTIN_SUFFIX (pshufh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
14159 LOONGSON_BUILTIN_SUFFIX (pshufh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
14160 LOONGSON_BUILTIN_SUFFIX (psllh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
14161 LOONGSON_BUILTIN_SUFFIX (psllh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
14162 LOONGSON_BUILTIN_SUFFIX (psllw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
14163 LOONGSON_BUILTIN_SUFFIX (psllw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
14164 LOONGSON_BUILTIN_SUFFIX (psrah, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
14165 LOONGSON_BUILTIN_SUFFIX (psrah, s, MIPS_V4HI_FTYPE_V4HI_UQI),
14166 LOONGSON_BUILTIN_SUFFIX (psraw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
14167 LOONGSON_BUILTIN_SUFFIX (psraw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
14168 LOONGSON_BUILTIN_SUFFIX (psrlh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
14169 LOONGSON_BUILTIN_SUFFIX (psrlh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
14170 LOONGSON_BUILTIN_SUFFIX (psrlw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
14171 LOONGSON_BUILTIN_SUFFIX (psrlw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
14172 LOONGSON_BUILTIN_SUFFIX (psubw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14173 LOONGSON_BUILTIN_SUFFIX (psubh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14174 LOONGSON_BUILTIN_SUFFIX (psubb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14175 LOONGSON_BUILTIN_SUFFIX (psubw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14176 LOONGSON_BUILTIN_SUFFIX (psubh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14177 LOONGSON_BUILTIN_SUFFIX (psubb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14178 LOONGSON_BUILTIN_SUFFIX (psubd, u, MIPS_UDI_FTYPE_UDI_UDI),
14179 LOONGSON_BUILTIN_SUFFIX (psubd, s, MIPS_DI_FTYPE_DI_DI),
14180 LOONGSON_BUILTIN (psubsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14181 LOONGSON_BUILTIN (psubsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
14182 LOONGSON_BUILTIN (psubush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14183 LOONGSON_BUILTIN (psubusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14184 LOONGSON_BUILTIN_SUFFIX (punpckhbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14185 LOONGSON_BUILTIN_SUFFIX (punpckhhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14186 LOONGSON_BUILTIN_SUFFIX (punpckhwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14187 LOONGSON_BUILTIN_SUFFIX (punpckhbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14188 LOONGSON_BUILTIN_SUFFIX (punpckhhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14189 LOONGSON_BUILTIN_SUFFIX (punpckhwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14190 LOONGSON_BUILTIN_SUFFIX (punpcklbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14191 LOONGSON_BUILTIN_SUFFIX (punpcklhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14192 LOONGSON_BUILTIN_SUFFIX (punpcklwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14193 LOONGSON_BUILTIN_SUFFIX (punpcklbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14194 LOONGSON_BUILTIN_SUFFIX (punpcklhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14195 LOONGSON_BUILTIN_SUFFIX (punpcklwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14197 /* Sundry other built-in functions. */
14198 DIRECT_NO_TARGET_BUILTIN (cache, MIPS_VOID_FTYPE_SI_CVPOINTER, cache)
14201 /* Index I is the function declaration for mips_builtins[I], or null if the
14202 function isn't defined on this target. */
14203 static GTY(()) tree mips_builtin_decls[ARRAY_SIZE (mips_builtins)];
14205 /* MODE is a vector mode whose elements have type TYPE. Return the type
14206 of the vector itself. */
14209 mips_builtin_vector_type (tree type, enum machine_mode mode)
14211 static tree types[2 * (int) MAX_MACHINE_MODE];
14214 mode_index = (int) mode;
14216 if (TREE_CODE (type) == INTEGER_TYPE && TYPE_UNSIGNED (type))
14217 mode_index += MAX_MACHINE_MODE;
14219 if (types[mode_index] == NULL_TREE)
14220 types[mode_index] = build_vector_type_for_mode (type, mode);
14221 return types[mode_index];
14224 /* Return a type for 'const volatile void *'. */
14227 mips_build_cvpointer_type (void)
14231 if (cache == NULL_TREE)
14232 cache = build_pointer_type (build_qualified_type
14234 TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE));
14238 /* Source-level argument types. */
14239 #define MIPS_ATYPE_VOID void_type_node
14240 #define MIPS_ATYPE_INT integer_type_node
14241 #define MIPS_ATYPE_POINTER ptr_type_node
14242 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
14244 /* Standard mode-based argument types. */
14245 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
14246 #define MIPS_ATYPE_SI intSI_type_node
14247 #define MIPS_ATYPE_USI unsigned_intSI_type_node
14248 #define MIPS_ATYPE_DI intDI_type_node
14249 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
14250 #define MIPS_ATYPE_SF float_type_node
14251 #define MIPS_ATYPE_DF double_type_node
14253 /* Vector argument types. */
14254 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
14255 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
14256 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
14257 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
14258 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
14259 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
14260 #define MIPS_ATYPE_UV2SI \
14261 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
14262 #define MIPS_ATYPE_UV4HI \
14263 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
14264 #define MIPS_ATYPE_UV8QI \
14265 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
14267 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
14268 their associated MIPS_ATYPEs. */
14269 #define MIPS_FTYPE_ATYPES1(A, B) \
14270 MIPS_ATYPE_##A, MIPS_ATYPE_##B
14272 #define MIPS_FTYPE_ATYPES2(A, B, C) \
14273 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
14275 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
14276 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
14278 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
14279 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
14282 /* Return the function type associated with function prototype TYPE. */
14285 mips_build_function_type (enum mips_function_type type)
14287 static tree types[(int) MIPS_MAX_FTYPE_MAX];
14289 if (types[(int) type] == NULL_TREE)
14292 #define DEF_MIPS_FTYPE(NUM, ARGS) \
14293 case MIPS_FTYPE_NAME##NUM ARGS: \
14294 types[(int) type] \
14295 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
14298 #include "config/mips/mips-ftypes.def"
14299 #undef DEF_MIPS_FTYPE
14301 gcc_unreachable ();
14304 return types[(int) type];
14307 /* Implement TARGET_INIT_BUILTINS. */
14310 mips_init_builtins (void)
14312 const struct mips_builtin_description *d;
14315 /* Iterate through all of the bdesc arrays, initializing all of the
14316 builtin functions. */
14317 for (i = 0; i < ARRAY_SIZE (mips_builtins); i++)
14319 d = &mips_builtins[i];
14321 mips_builtin_decls[i]
14322 = add_builtin_function (d->name,
14323 mips_build_function_type (d->function_type),
14324 i, BUILT_IN_MD, NULL, NULL);
14328 /* Implement TARGET_BUILTIN_DECL. */
14331 mips_builtin_decl (unsigned int code, bool initialize_p ATTRIBUTE_UNUSED)
14333 if (code >= ARRAY_SIZE (mips_builtins))
14334 return error_mark_node;
14335 return mips_builtin_decls[code];
14338 /* Take argument ARGNO from EXP's argument list and convert it into
14339 an expand operand. Store the operand in *OP. */
14342 mips_prepare_builtin_arg (struct expand_operand *op, tree exp,
14343 unsigned int argno)
14348 arg = CALL_EXPR_ARG (exp, argno);
14349 value = expand_normal (arg);
14350 create_input_operand (op, value, TYPE_MODE (TREE_TYPE (arg)));
14353 /* Expand instruction ICODE as part of a built-in function sequence.
14354 Use the first NOPS elements of OPS as the instruction's operands.
14355 HAS_TARGET_P is true if operand 0 is a target; it is false if the
14356 instruction has no target.
14358 Return the target rtx if HAS_TARGET_P, otherwise return const0_rtx. */
14361 mips_expand_builtin_insn (enum insn_code icode, unsigned int nops,
14362 struct expand_operand *ops, bool has_target_p)
14364 if (!maybe_expand_insn (icode, nops, ops))
14366 error ("invalid argument to built-in function");
14367 return has_target_p ? gen_reg_rtx (ops[0].mode) : const0_rtx;
14369 return has_target_p ? ops[0].value : const0_rtx;
14372 /* Expand a floating-point comparison for built-in function call EXP.
14373 The first NARGS arguments are the values to be compared. ICODE is
14374 the .md pattern that does the comparison and COND is the condition
14375 that is being tested. Return an rtx for the result. */
14378 mips_expand_builtin_compare_1 (enum insn_code icode,
14379 enum mips_fp_condition cond,
14380 tree exp, int nargs)
14382 struct expand_operand ops[MAX_RECOG_OPERANDS];
14386 /* The instruction should have a target operand, an operand for each
14387 argument, and an operand for COND. */
14388 gcc_assert (nargs + 2 == insn_data[(int) icode].n_generator_args);
14390 output = mips_allocate_fcc (insn_data[(int) icode].operand[0].mode);
14392 create_fixed_operand (&ops[opno++], output);
14393 for (argno = 0; argno < nargs; argno++)
14394 mips_prepare_builtin_arg (&ops[opno++], exp, argno);
14395 create_integer_operand (&ops[opno++], (int) cond);
14396 return mips_expand_builtin_insn (icode, opno, ops, true);
14399 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
14400 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
14401 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
14402 suggests a good place to put the result. */
14405 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
14408 struct expand_operand ops[MAX_RECOG_OPERANDS];
14411 /* Map any target to operand 0. */
14414 create_output_operand (&ops[opno++], target, TYPE_MODE (TREE_TYPE (exp)));
14416 /* Map the arguments to the other operands. */
14417 gcc_assert (opno + call_expr_nargs (exp)
14418 == insn_data[icode].n_generator_args);
14419 for (argno = 0; argno < call_expr_nargs (exp); argno++)
14420 mips_prepare_builtin_arg (&ops[opno++], exp, argno);
14422 return mips_expand_builtin_insn (icode, opno, ops, has_target_p);
14425 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
14426 function; TYPE says which. EXP is the CALL_EXPR that calls the
14427 function, ICODE is the instruction that should be used to compare
14428 the first two arguments, and COND is the condition it should test.
14429 TARGET, if nonnull, suggests a good place to put the result. */
14432 mips_expand_builtin_movtf (enum mips_builtin_type type,
14433 enum insn_code icode, enum mips_fp_condition cond,
14434 rtx target, tree exp)
14436 struct expand_operand ops[4];
14439 cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp, 2);
14440 create_output_operand (&ops[0], target, TYPE_MODE (TREE_TYPE (exp)));
14441 if (type == MIPS_BUILTIN_MOVT)
14443 mips_prepare_builtin_arg (&ops[2], exp, 2);
14444 mips_prepare_builtin_arg (&ops[1], exp, 3);
14448 mips_prepare_builtin_arg (&ops[1], exp, 2);
14449 mips_prepare_builtin_arg (&ops[2], exp, 3);
14451 create_fixed_operand (&ops[3], cmp_result);
14452 return mips_expand_builtin_insn (CODE_FOR_mips_cond_move_tf_ps,
14456 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
14457 into TARGET otherwise. Return TARGET. */
14460 mips_builtin_branch_and_move (rtx condition, rtx target,
14461 rtx value_if_true, rtx value_if_false)
14463 rtx_code_label *true_label, *done_label;
14465 true_label = gen_label_rtx ();
14466 done_label = gen_label_rtx ();
14468 /* First assume that CONDITION is false. */
14469 mips_emit_move (target, value_if_false);
14471 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
14472 emit_jump_insn (gen_condjump (condition, true_label));
14473 emit_jump_insn (gen_jump (done_label));
14476 /* Fix TARGET if CONDITION is true. */
14477 emit_label (true_label);
14478 mips_emit_move (target, value_if_true);
14480 emit_label (done_label);
14484 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
14485 the CALL_EXPR that calls the function, ICODE is the code of the
14486 comparison instruction, and COND is the condition it should test.
14487 TARGET, if nonnull, suggests a good place to put the boolean result. */
14490 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
14491 enum insn_code icode, enum mips_fp_condition cond,
14492 rtx target, tree exp)
14494 rtx offset, condition, cmp_result;
14496 if (target == 0 || GET_MODE (target) != SImode)
14497 target = gen_reg_rtx (SImode);
14498 cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp,
14499 call_expr_nargs (exp));
14501 /* If the comparison sets more than one register, we define the result
14502 to be 0 if all registers are false and -1 if all registers are true.
14503 The value of the complete result is indeterminate otherwise. */
14504 switch (builtin_type)
14506 case MIPS_BUILTIN_CMP_ALL:
14507 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
14508 return mips_builtin_branch_and_move (condition, target,
14509 const0_rtx, const1_rtx);
14511 case MIPS_BUILTIN_CMP_UPPER:
14512 case MIPS_BUILTIN_CMP_LOWER:
14513 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
14514 condition = gen_single_cc (cmp_result, offset);
14515 return mips_builtin_branch_and_move (condition, target,
14516 const1_rtx, const0_rtx);
14519 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
14520 return mips_builtin_branch_and_move (condition, target,
14521 const1_rtx, const0_rtx);
14525 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
14526 if nonnull, suggests a good place to put the boolean result. */
14529 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
14531 rtx condition, cmp_result;
14534 if (target == 0 || GET_MODE (target) != SImode)
14535 target = gen_reg_rtx (SImode);
14537 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
14539 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
14544 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
14545 return mips_builtin_branch_and_move (condition, target,
14546 const1_rtx, const0_rtx);
14549 /* Implement TARGET_EXPAND_BUILTIN. */
14552 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
14553 enum machine_mode mode, int ignore)
14556 unsigned int fcode, avail;
14557 const struct mips_builtin_description *d;
14559 fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
14560 fcode = DECL_FUNCTION_CODE (fndecl);
14561 gcc_assert (fcode < ARRAY_SIZE (mips_builtins));
14562 d = &mips_builtins[fcode];
14563 avail = d->avail ();
14564 gcc_assert (avail != 0);
14565 if (TARGET_MIPS16 && !(avail & BUILTIN_AVAIL_MIPS16))
14567 error ("built-in function %qE not supported for MIPS16",
14568 DECL_NAME (fndecl));
14569 return ignore ? const0_rtx : CONST0_RTX (mode);
14571 switch (d->builtin_type)
14573 case MIPS_BUILTIN_DIRECT:
14574 return mips_expand_builtin_direct (d->icode, target, exp, true);
14576 case MIPS_BUILTIN_DIRECT_NO_TARGET:
14577 return mips_expand_builtin_direct (d->icode, target, exp, false);
14579 case MIPS_BUILTIN_MOVT:
14580 case MIPS_BUILTIN_MOVF:
14581 return mips_expand_builtin_movtf (d->builtin_type, d->icode,
14582 d->cond, target, exp);
14584 case MIPS_BUILTIN_CMP_ANY:
14585 case MIPS_BUILTIN_CMP_ALL:
14586 case MIPS_BUILTIN_CMP_UPPER:
14587 case MIPS_BUILTIN_CMP_LOWER:
14588 case MIPS_BUILTIN_CMP_SINGLE:
14589 return mips_expand_builtin_compare (d->builtin_type, d->icode,
14590 d->cond, target, exp);
14592 case MIPS_BUILTIN_BPOSGE32:
14593 return mips_expand_builtin_bposge (d->builtin_type, target);
14595 gcc_unreachable ();
14598 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
14599 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
14600 struct mips16_constant {
14601 struct mips16_constant *next;
14603 rtx_code_label *label;
14604 enum machine_mode mode;
14607 /* Information about an incomplete MIPS16 constant pool. FIRST is the
14608 first constant, HIGHEST_ADDRESS is the highest address that the first
14609 byte of the pool can have, and INSN_ADDRESS is the current instruction
14611 struct mips16_constant_pool {
14612 struct mips16_constant *first;
14613 int highest_address;
14617 /* Add constant VALUE to POOL and return its label. MODE is the
14618 value's mode (used for CONST_INTs, etc.). */
14620 static rtx_code_label *
14621 mips16_add_constant (struct mips16_constant_pool *pool,
14622 rtx value, enum machine_mode mode)
14624 struct mips16_constant **p, *c;
14625 bool first_of_size_p;
14627 /* See whether the constant is already in the pool. If so, return the
14628 existing label, otherwise leave P pointing to the place where the
14629 constant should be added.
14631 Keep the pool sorted in increasing order of mode size so that we can
14632 reduce the number of alignments needed. */
14633 first_of_size_p = true;
14634 for (p = &pool->first; *p != 0; p = &(*p)->next)
14636 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
14637 return (*p)->label;
14638 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
14640 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
14641 first_of_size_p = false;
14644 /* In the worst case, the constant needed by the earliest instruction
14645 will end up at the end of the pool. The entire pool must then be
14646 accessible from that instruction.
14648 When adding the first constant, set the pool's highest address to
14649 the address of the first out-of-range byte. Adjust this address
14650 downwards each time a new constant is added. */
14651 if (pool->first == 0)
14652 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
14653 of the instruction with the lowest two bits clear. The base PC
14654 value for LDPC has the lowest three bits clear. Assume the worst
14655 case here; namely that the PC-relative instruction occupies the
14656 last 2 bytes in an aligned word. */
14657 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
14658 pool->highest_address -= GET_MODE_SIZE (mode);
14659 if (first_of_size_p)
14660 /* Take into account the worst possible padding due to alignment. */
14661 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
14663 /* Create a new entry. */
14664 c = XNEW (struct mips16_constant);
14667 c->label = gen_label_rtx ();
14674 /* Output constant VALUE after instruction INSN and return the last
14675 instruction emitted. MODE is the mode of the constant. */
14678 mips16_emit_constants_1 (enum machine_mode mode, rtx value, rtx_insn *insn)
14680 if (SCALAR_INT_MODE_P (mode) || ALL_SCALAR_FIXED_POINT_MODE_P (mode))
14682 rtx size = GEN_INT (GET_MODE_SIZE (mode));
14683 return emit_insn_after (gen_consttable_int (value, size), insn);
14686 if (SCALAR_FLOAT_MODE_P (mode))
14687 return emit_insn_after (gen_consttable_float (value), insn);
14689 if (VECTOR_MODE_P (mode))
14693 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
14694 insn = mips16_emit_constants_1 (GET_MODE_INNER (mode),
14695 CONST_VECTOR_ELT (value, i), insn);
14699 gcc_unreachable ();
14702 /* Dump out the constants in CONSTANTS after INSN. */
14705 mips16_emit_constants (struct mips16_constant *constants, rtx_insn *insn)
14707 struct mips16_constant *c, *next;
14711 for (c = constants; c != NULL; c = next)
14713 /* If necessary, increase the alignment of PC. */
14714 if (align < GET_MODE_SIZE (c->mode))
14716 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
14717 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
14719 align = GET_MODE_SIZE (c->mode);
14721 insn = emit_label_after (c->label, insn);
14722 insn = mips16_emit_constants_1 (c->mode, c->value, insn);
14728 emit_barrier_after (insn);
14731 /* Return the length of instruction INSN. */
14734 mips16_insn_length (rtx_insn *insn)
14736 if (JUMP_TABLE_DATA_P (insn))
14738 rtx body = PATTERN (insn);
14739 if (GET_CODE (body) == ADDR_VEC)
14740 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
14741 else if (GET_CODE (body) == ADDR_DIFF_VEC)
14742 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
14744 gcc_unreachable ();
14746 return get_attr_length (insn);
14749 /* If *X is a symbolic constant that refers to the constant pool, add
14750 the constant to POOL and rewrite *X to use the constant's label. */
14753 mips16_rewrite_pool_constant (struct mips16_constant_pool *pool, rtx *x)
14756 rtx_code_label *label;
14758 split_const (*x, &base, &offset);
14759 if (GET_CODE (base) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (base))
14761 label = mips16_add_constant (pool, copy_rtx (get_pool_constant (base)),
14762 get_pool_mode (base));
14763 base = gen_rtx_LABEL_REF (Pmode, label);
14764 *x = mips_unspec_address_offset (base, offset, SYMBOL_PC_RELATIVE);
14768 /* This structure is used to communicate with mips16_rewrite_pool_refs.
14769 INSN is the instruction we're rewriting and POOL points to the current
14771 struct mips16_rewrite_pool_refs_info {
14773 struct mips16_constant_pool *pool;
14776 /* Rewrite *X so that constant pool references refer to the constant's
14777 label instead. DATA points to a mips16_rewrite_pool_refs_info
14781 mips16_rewrite_pool_refs (rtx *x, void *data)
14783 struct mips16_rewrite_pool_refs_info *info =
14784 (struct mips16_rewrite_pool_refs_info *) data;
14786 if (force_to_mem_operand (*x, Pmode))
14788 rtx mem = force_const_mem (GET_MODE (*x), *x);
14789 validate_change (info->insn, x, mem, false);
14794 mips16_rewrite_pool_constant (info->pool, &XEXP (*x, 0));
14798 /* Don't rewrite the __mips16_rdwr symbol. */
14799 if (GET_CODE (*x) == UNSPEC && XINT (*x, 1) == UNSPEC_TLS_GET_TP)
14802 if (TARGET_MIPS16_TEXT_LOADS)
14803 mips16_rewrite_pool_constant (info->pool, x);
14805 return GET_CODE (*x) == CONST ? -1 : 0;
14808 /* Return whether CFG is used in mips_reorg. */
14811 mips_cfg_in_reorg (void)
14813 return (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
14814 || TARGET_RELAX_PIC_CALLS);
14817 /* Build MIPS16 constant pools. Split the instructions if SPLIT_P,
14818 otherwise assume that they are already split. */
14821 mips16_lay_out_constants (bool split_p)
14823 struct mips16_constant_pool pool;
14824 struct mips16_rewrite_pool_refs_info info;
14825 rtx_insn *insn, *barrier;
14827 if (!TARGET_MIPS16_PCREL_LOADS)
14832 if (mips_cfg_in_reorg ())
14833 split_all_insns ();
14835 split_all_insns_noflow ();
14838 memset (&pool, 0, sizeof (pool));
14839 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
14841 /* Rewrite constant pool references in INSN. */
14842 if (USEFUL_INSN_P (insn))
14846 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &info);
14849 pool.insn_address += mips16_insn_length (insn);
14851 if (pool.first != NULL)
14853 /* If there are no natural barriers between the first user of
14854 the pool and the highest acceptable address, we'll need to
14855 create a new instruction to jump around the constant pool.
14856 In the worst case, this instruction will be 4 bytes long.
14858 If it's too late to do this transformation after INSN,
14859 do it immediately before INSN. */
14860 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
14862 rtx_code_label *label;
14865 label = gen_label_rtx ();
14867 jump = emit_jump_insn_before (gen_jump (label), insn);
14868 JUMP_LABEL (jump) = label;
14869 LABEL_NUSES (label) = 1;
14870 barrier = emit_barrier_after (jump);
14872 emit_label_after (label, barrier);
14873 pool.insn_address += 4;
14876 /* See whether the constant pool is now out of range of the first
14877 user. If so, output the constants after the previous barrier.
14878 Note that any instructions between BARRIER and INSN (inclusive)
14879 will use negative offsets to refer to the pool. */
14880 if (pool.insn_address > pool.highest_address)
14882 mips16_emit_constants (pool.first, barrier);
14886 else if (BARRIER_P (insn))
14890 mips16_emit_constants (pool.first, get_last_insn ());
14893 /* Return true if it is worth r10k_simplify_address's while replacing
14894 an address with X. We are looking for constants, and for addresses
14895 at a known offset from the incoming stack pointer. */
14898 r10k_simplified_address_p (rtx x)
14900 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
14902 return x == virtual_incoming_args_rtx || CONSTANT_P (x);
14905 /* X is an expression that appears in INSN. Try to use the UD chains
14906 to simplify it, returning the simplified form on success and the
14907 original form otherwise. Replace the incoming value of $sp with
14908 virtual_incoming_args_rtx (which should never occur in X otherwise). */
14911 r10k_simplify_address (rtx x, rtx_insn *insn)
14913 rtx newx, op0, op1, set, note;
14914 rtx_insn *def_insn;
14916 struct df_link *defs;
14921 op0 = r10k_simplify_address (XEXP (x, 0), insn);
14922 if (op0 != XEXP (x, 0))
14923 newx = simplify_gen_unary (GET_CODE (x), GET_MODE (x),
14924 op0, GET_MODE (XEXP (x, 0)));
14926 else if (BINARY_P (x))
14928 op0 = r10k_simplify_address (XEXP (x, 0), insn);
14929 op1 = r10k_simplify_address (XEXP (x, 1), insn);
14930 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
14931 newx = simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
14933 else if (GET_CODE (x) == LO_SUM)
14935 /* LO_SUMs can be offset from HIGHs, if we know they won't
14936 overflow. See mips_classify_address for the rationale behind
14938 op0 = r10k_simplify_address (XEXP (x, 0), insn);
14939 if (GET_CODE (op0) == HIGH)
14940 newx = XEXP (x, 1);
14942 else if (REG_P (x))
14944 /* Uses are recorded by regno_reg_rtx, not X itself. */
14945 use = df_find_use (insn, regno_reg_rtx[REGNO (x)]);
14947 defs = DF_REF_CHAIN (use);
14949 /* Require a single definition. */
14950 if (defs && defs->next == NULL)
14953 if (DF_REF_IS_ARTIFICIAL (def))
14955 /* Replace the incoming value of $sp with
14956 virtual_incoming_args_rtx. */
14957 if (x == stack_pointer_rtx
14958 && DF_REF_BB (def) == ENTRY_BLOCK_PTR_FOR_FN (cfun))
14959 newx = virtual_incoming_args_rtx;
14961 else if (dominated_by_p (CDI_DOMINATORS, DF_REF_BB (use),
14964 /* Make sure that DEF_INSN is a single set of REG. */
14965 def_insn = DF_REF_INSN (def);
14966 if (NONJUMP_INSN_P (def_insn))
14968 set = single_set (def_insn);
14969 if (set && rtx_equal_p (SET_DEST (set), x))
14971 /* Prefer to use notes, since the def-use chains
14972 are often shorter. */
14973 note = find_reg_equal_equiv_note (def_insn);
14975 newx = XEXP (note, 0);
14977 newx = SET_SRC (set);
14978 newx = r10k_simplify_address (newx, def_insn);
14984 if (newx && r10k_simplified_address_p (newx))
14989 /* Return true if ADDRESS is known to be an uncached address
14990 on R10K systems. */
14993 r10k_uncached_address_p (unsigned HOST_WIDE_INT address)
14995 unsigned HOST_WIDE_INT upper;
14997 /* Check for KSEG1. */
14998 if (address + 0x60000000 < 0x20000000)
15001 /* Check for uncached XKPHYS addresses. */
15002 if (Pmode == DImode)
15004 upper = (address >> 40) & 0xf9ffff;
15005 if (upper == 0x900000 || upper == 0xb80000)
15011 /* Return true if we can prove that an access to address X in instruction
15012 INSN would be safe from R10K speculation. This X is a general
15013 expression; it might not be a legitimate address. */
15016 r10k_safe_address_p (rtx x, rtx_insn *insn)
15019 HOST_WIDE_INT offset_val;
15021 x = r10k_simplify_address (x, insn);
15023 /* Check for references to the stack frame. It doesn't really matter
15024 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
15025 allows us to assume that accesses to any part of the eventual frame
15026 is safe from speculation at any point in the function. */
15027 mips_split_plus (x, &base, &offset_val);
15028 if (base == virtual_incoming_args_rtx
15029 && offset_val >= -cfun->machine->frame.total_size
15030 && offset_val < cfun->machine->frame.args_size)
15033 /* Check for uncached addresses. */
15034 if (CONST_INT_P (x))
15035 return r10k_uncached_address_p (INTVAL (x));
15037 /* Check for accesses to a static object. */
15038 split_const (x, &base, &offset);
15039 return offset_within_block_p (base, INTVAL (offset));
15042 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
15043 an in-range access to an automatic variable, or to an object with
15044 a link-time-constant address. */
15047 r10k_safe_mem_expr_p (tree expr, unsigned HOST_WIDE_INT offset)
15049 HOST_WIDE_INT bitoffset, bitsize;
15050 tree inner, var_offset;
15051 enum machine_mode mode;
15052 int unsigned_p, volatile_p;
15054 inner = get_inner_reference (expr, &bitsize, &bitoffset, &var_offset, &mode,
15055 &unsigned_p, &volatile_p, false);
15056 if (!DECL_P (inner) || !DECL_SIZE_UNIT (inner) || var_offset)
15059 offset += bitoffset / BITS_PER_UNIT;
15060 return offset < tree_to_uhwi (DECL_SIZE_UNIT (inner));
15063 /* A for_each_rtx callback for which DATA points to the instruction
15064 containing *X. Stop the search if we find a MEM that is not safe
15065 from R10K speculation. */
15068 r10k_needs_protection_p_1 (rtx *loc, void *data)
15077 && MEM_OFFSET_KNOWN_P (mem)
15078 && r10k_safe_mem_expr_p (MEM_EXPR (mem), MEM_OFFSET (mem)))
15081 if (r10k_safe_address_p (XEXP (mem, 0), (rtx_insn *) data))
15087 /* A note_stores callback for which DATA points to an instruction pointer.
15088 If *DATA is nonnull, make it null if it X contains a MEM that is not
15089 safe from R10K speculation. */
15092 r10k_needs_protection_p_store (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
15095 rtx_insn **insn_ptr;
15097 insn_ptr = (rtx_insn **) data;
15098 if (*insn_ptr && for_each_rtx (&x, r10k_needs_protection_p_1, *insn_ptr))
15102 /* A for_each_rtx callback that iterates over the pattern of a CALL_INSN.
15103 Return nonzero if the call is not to a declared function. */
15106 r10k_needs_protection_p_call (rtx *loc, void *data ATTRIBUTE_UNUSED)
15115 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DECL (x))
15121 /* Return true if instruction INSN needs to be protected by an R10K
15125 r10k_needs_protection_p (rtx_insn *insn)
15128 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_call, NULL);
15130 if (mips_r10k_cache_barrier == R10K_CACHE_BARRIER_STORE)
15132 note_stores (PATTERN (insn), r10k_needs_protection_p_store, &insn);
15133 return insn == NULL_RTX;
15136 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_1, insn);
15139 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
15140 edge is unconditional. */
15143 r10k_protected_bb_p (basic_block bb, sbitmap protected_bbs)
15148 FOR_EACH_EDGE (e, ei, bb->preds)
15149 if (!single_succ_p (e->src)
15150 || !bitmap_bit_p (protected_bbs, e->src->index)
15151 || (e->flags & EDGE_COMPLEX) != 0)
15156 /* Implement -mr10k-cache-barrier= for the current function. */
15159 r10k_insert_cache_barriers (void)
15161 int *rev_post_order;
15164 sbitmap protected_bbs;
15165 rtx_insn *insn, *end;
15166 rtx unprotected_region;
15170 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
15174 /* Calculate dominators. */
15175 calculate_dominance_info (CDI_DOMINATORS);
15177 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
15178 X is protected by a cache barrier. */
15179 protected_bbs = sbitmap_alloc (last_basic_block_for_fn (cfun));
15180 bitmap_clear (protected_bbs);
15182 /* Iterate over the basic blocks in reverse post-order. */
15183 rev_post_order = XNEWVEC (int, last_basic_block_for_fn (cfun));
15184 n = pre_and_rev_post_order_compute (NULL, rev_post_order, false);
15185 for (i = 0; i < n; i++)
15187 bb = BASIC_BLOCK_FOR_FN (cfun, rev_post_order[i]);
15189 /* If this block is only reached by unconditional edges, and if the
15190 source of every edge is protected, the beginning of the block is
15192 if (r10k_protected_bb_p (bb, protected_bbs))
15193 unprotected_region = NULL_RTX;
15195 unprotected_region = pc_rtx;
15196 end = NEXT_INSN (BB_END (bb));
15198 /* UNPROTECTED_REGION is:
15200 - null if we are processing a protected region,
15201 - pc_rtx if we are processing an unprotected region but have
15202 not yet found the first instruction in it
15203 - the first instruction in an unprotected region otherwise. */
15204 for (insn = BB_HEAD (bb); insn != end; insn = NEXT_INSN (insn))
15206 if (unprotected_region && USEFUL_INSN_P (insn))
15208 if (recog_memoized (insn) == CODE_FOR_mips_cache)
15209 /* This CACHE instruction protects the following code. */
15210 unprotected_region = NULL_RTX;
15213 /* See if INSN is the first instruction in this
15214 unprotected region. */
15215 if (unprotected_region == pc_rtx)
15216 unprotected_region = insn;
15218 /* See if INSN needs to be protected. If so,
15219 we must insert a cache barrier somewhere between
15220 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
15221 clear which position is better performance-wise,
15222 but as a tie-breaker, we assume that it is better
15223 to allow delay slots to be back-filled where
15224 possible, and that it is better not to insert
15225 barriers in the middle of already-scheduled code.
15226 We therefore insert the barrier at the beginning
15228 if (r10k_needs_protection_p (insn))
15230 emit_insn_before (gen_r10k_cache_barrier (),
15231 unprotected_region);
15232 unprotected_region = NULL_RTX;
15238 /* The called function is not required to protect the exit path.
15239 The code that follows a call is therefore unprotected. */
15240 unprotected_region = pc_rtx;
15243 /* Record whether the end of this block is protected. */
15244 if (unprotected_region == NULL_RTX)
15245 bitmap_set_bit (protected_bbs, bb->index);
15247 XDELETEVEC (rev_post_order);
15249 sbitmap_free (protected_bbs);
15251 free_dominance_info (CDI_DOMINATORS);
15254 /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX
15255 otherwise. If INSN has two call rtx, then store the second one in
15259 mips_call_expr_from_insn (rtx_insn *insn, rtx *second_call)
15264 if (!CALL_P (insn))
15267 x = PATTERN (insn);
15268 if (GET_CODE (x) == PARALLEL)
15270 /* Calls returning complex values have two CALL rtx. Look for the second
15271 one here, and return it via the SECOND_CALL arg. */
15272 x2 = XVECEXP (x, 0, 1);
15273 if (GET_CODE (x2) == SET)
15275 if (GET_CODE (x2) == CALL)
15278 x = XVECEXP (x, 0, 0);
15280 if (GET_CODE (x) == SET)
15282 gcc_assert (GET_CODE (x) == CALL);
15287 /* REG is set in DEF. See if the definition is one of the ways we load a
15288 register with a symbol address for a mips_use_pic_fn_addr_reg_p call.
15289 If it is, return the symbol reference of the function, otherwise return
15292 If RECURSE_P is true, use mips_find_pic_call_symbol to interpret
15293 the values of source registers, otherwise treat such registers as
15294 having an unknown value. */
15297 mips_pic_call_symbol_from_set (df_ref def, rtx reg, bool recurse_p)
15299 rtx_insn *def_insn;
15302 if (DF_REF_IS_ARTIFICIAL (def))
15305 def_insn = DF_REF_INSN (def);
15306 set = single_set (def_insn);
15307 if (set && rtx_equal_p (SET_DEST (set), reg))
15309 rtx note, src, symbol;
15311 /* First see whether the source is a plain symbol. This is used
15312 when calling symbols that are not lazily bound. */
15313 src = SET_SRC (set);
15314 if (GET_CODE (src) == SYMBOL_REF)
15317 /* Handle %call16 references. */
15318 symbol = mips_strip_unspec_call (src);
15321 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
15325 /* If we have something more complicated, look for a
15326 REG_EQUAL or REG_EQUIV note. */
15327 note = find_reg_equal_equiv_note (def_insn);
15328 if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF)
15329 return XEXP (note, 0);
15331 /* Follow at most one simple register copy. Such copies are
15332 interesting in cases like:
15336 locally_binding_fn (...);
15341 locally_binding_fn (...);
15343 locally_binding_fn (...);
15345 where the load of locally_binding_fn can legitimately be
15346 hoisted or shared. However, we do not expect to see complex
15347 chains of copies, so a full worklist solution to the problem
15348 would probably be overkill. */
15349 if (recurse_p && REG_P (src))
15350 return mips_find_pic_call_symbol (def_insn, src, false);
15356 /* Find the definition of the use of REG in INSN. See if the definition
15357 is one of the ways we load a register with a symbol address for a
15358 mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference
15359 of the function, otherwise return NULL_RTX. RECURSE_P is as for
15360 mips_pic_call_symbol_from_set. */
15363 mips_find_pic_call_symbol (rtx_insn *insn, rtx reg, bool recurse_p)
15366 struct df_link *defs;
15369 use = df_find_use (insn, regno_reg_rtx[REGNO (reg)]);
15372 defs = DF_REF_CHAIN (use);
15375 symbol = mips_pic_call_symbol_from_set (defs->ref, reg, recurse_p);
15379 /* If we have more than one definition, they need to be identical. */
15380 for (defs = defs->next; defs; defs = defs->next)
15384 other = mips_pic_call_symbol_from_set (defs->ref, reg, recurse_p);
15385 if (!rtx_equal_p (symbol, other))
15392 /* Replace the args_size operand of the call expression CALL with the
15393 call-attribute UNSPEC and fill in SYMBOL as the function symbol. */
15396 mips_annotate_pic_call_expr (rtx call, rtx symbol)
15400 args_size = XEXP (call, 1);
15401 XEXP (call, 1) = gen_rtx_UNSPEC (GET_MODE (args_size),
15402 gen_rtvec (2, args_size, symbol),
15406 /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See
15407 if instead of the arg_size argument it contains the call attributes. If
15408 yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function
15409 symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is
15413 mips_get_pic_call_symbol (rtx *operands, int args_size_opno)
15415 rtx args_size, symbol;
15417 if (!TARGET_RELAX_PIC_CALLS || args_size_opno == -1)
15420 args_size = operands[args_size_opno];
15421 if (GET_CODE (args_size) != UNSPEC)
15423 gcc_assert (XINT (args_size, 1) == UNSPEC_CALL_ATTR);
15425 symbol = XVECEXP (args_size, 0, 1);
15426 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
15428 operands[args_size_opno] = symbol;
15432 /* Use DF to annotate PIC indirect calls with the function symbol they
15436 mips_annotate_pic_calls (void)
15441 FOR_EACH_BB_FN (bb, cfun)
15442 FOR_BB_INSNS (bb, insn)
15444 rtx call, reg, symbol, second_call;
15447 call = mips_call_expr_from_insn (insn, &second_call);
15450 gcc_assert (MEM_P (XEXP (call, 0)));
15451 reg = XEXP (XEXP (call, 0), 0);
15455 symbol = mips_find_pic_call_symbol (insn, reg, true);
15458 mips_annotate_pic_call_expr (call, symbol);
15460 mips_annotate_pic_call_expr (second_call, symbol);
15465 /* A temporary variable used by for_each_rtx callbacks, etc. */
15466 static rtx_insn *mips_sim_insn;
15468 /* A structure representing the state of the processor pipeline.
15469 Used by the mips_sim_* family of functions. */
15471 /* The maximum number of instructions that can be issued in a cycle.
15472 (Caches mips_issue_rate.) */
15473 unsigned int issue_rate;
15475 /* The current simulation time. */
15478 /* How many more instructions can be issued in the current cycle. */
15479 unsigned int insns_left;
15481 /* LAST_SET[X].INSN is the last instruction to set register X.
15482 LAST_SET[X].TIME is the time at which that instruction was issued.
15483 INSN is null if no instruction has yet set register X. */
15487 } last_set[FIRST_PSEUDO_REGISTER];
15489 /* The pipeline's current DFA state. */
15493 /* Reset STATE to the initial simulation state. */
15496 mips_sim_reset (struct mips_sim *state)
15498 curr_state = state->dfa_state;
15501 state->insns_left = state->issue_rate;
15502 memset (&state->last_set, 0, sizeof (state->last_set));
15503 state_reset (curr_state);
15505 targetm.sched.init (0, false, 0);
15506 advance_state (curr_state);
15509 /* Initialize STATE before its first use. DFA_STATE points to an
15510 allocated but uninitialized DFA state. */
15513 mips_sim_init (struct mips_sim *state, state_t dfa_state)
15515 if (targetm.sched.init_dfa_pre_cycle_insn)
15516 targetm.sched.init_dfa_pre_cycle_insn ();
15518 if (targetm.sched.init_dfa_post_cycle_insn)
15519 targetm.sched.init_dfa_post_cycle_insn ();
15521 state->issue_rate = mips_issue_rate ();
15522 state->dfa_state = dfa_state;
15523 mips_sim_reset (state);
15526 /* Advance STATE by one clock cycle. */
15529 mips_sim_next_cycle (struct mips_sim *state)
15531 curr_state = state->dfa_state;
15534 state->insns_left = state->issue_rate;
15535 advance_state (curr_state);
15538 /* Advance simulation state STATE until instruction INSN can read
15542 mips_sim_wait_reg (struct mips_sim *state, rtx_insn *insn, rtx reg)
15544 unsigned int regno, end_regno;
15546 end_regno = END_REGNO (reg);
15547 for (regno = REGNO (reg); regno < end_regno; regno++)
15548 if (state->last_set[regno].insn != 0)
15552 t = (state->last_set[regno].time
15553 + insn_latency (state->last_set[regno].insn, insn));
15554 while (state->time < t)
15555 mips_sim_next_cycle (state);
15559 /* A for_each_rtx callback. If *X is a register, advance simulation state
15560 DATA until mips_sim_insn can read the register's value. */
15563 mips_sim_wait_regs_2 (rtx *x, void *data)
15566 mips_sim_wait_reg ((struct mips_sim *) data, mips_sim_insn, *x);
15570 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
15573 mips_sim_wait_regs_1 (rtx *x, void *data)
15575 for_each_rtx (x, mips_sim_wait_regs_2, data);
15578 /* Advance simulation state STATE until all of INSN's register
15579 dependencies are satisfied. */
15582 mips_sim_wait_regs (struct mips_sim *state, rtx_insn *insn)
15584 mips_sim_insn = insn;
15585 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
15588 /* Advance simulation state STATE until the units required by
15589 instruction INSN are available. */
15592 mips_sim_wait_units (struct mips_sim *state, rtx_insn *insn)
15596 tmp_state = alloca (state_size ());
15597 while (state->insns_left == 0
15598 || (memcpy (tmp_state, state->dfa_state, state_size ()),
15599 state_transition (tmp_state, insn) >= 0))
15600 mips_sim_next_cycle (state);
15603 /* Advance simulation state STATE until INSN is ready to issue. */
15606 mips_sim_wait_insn (struct mips_sim *state, rtx_insn *insn)
15608 mips_sim_wait_regs (state, insn);
15609 mips_sim_wait_units (state, insn);
15612 /* mips_sim_insn has just set X. Update the LAST_SET array
15613 in simulation state DATA. */
15616 mips_sim_record_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
15618 struct mips_sim *state;
15620 state = (struct mips_sim *) data;
15623 unsigned int regno, end_regno;
15625 end_regno = END_REGNO (x);
15626 for (regno = REGNO (x); regno < end_regno; regno++)
15628 state->last_set[regno].insn = mips_sim_insn;
15629 state->last_set[regno].time = state->time;
15634 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
15635 can issue immediately (i.e., that mips_sim_wait_insn has already
15639 mips_sim_issue_insn (struct mips_sim *state, rtx_insn *insn)
15641 curr_state = state->dfa_state;
15643 state_transition (curr_state, insn);
15644 state->insns_left = targetm.sched.variable_issue (0, false, insn,
15645 state->insns_left);
15647 mips_sim_insn = insn;
15648 note_stores (PATTERN (insn), mips_sim_record_set, state);
15651 /* Simulate issuing a NOP in state STATE. */
15654 mips_sim_issue_nop (struct mips_sim *state)
15656 if (state->insns_left == 0)
15657 mips_sim_next_cycle (state);
15658 state->insns_left--;
15661 /* Update simulation state STATE so that it's ready to accept the instruction
15662 after INSN. INSN should be part of the main rtl chain, not a member of a
15666 mips_sim_finish_insn (struct mips_sim *state, rtx_insn *insn)
15668 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
15670 mips_sim_issue_nop (state);
15672 switch (GET_CODE (SEQ_BEGIN (insn)))
15676 /* We can't predict the processor state after a call or label. */
15677 mips_sim_reset (state);
15681 /* The delay slots of branch likely instructions are only executed
15682 when the branch is taken. Therefore, if the caller has simulated
15683 the delay slot instruction, STATE does not really reflect the state
15684 of the pipeline for the instruction after the delay slot. Also,
15685 branch likely instructions tend to incur a penalty when not taken,
15686 so there will probably be an extra delay between the branch and
15687 the instruction after the delay slot. */
15688 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
15689 mips_sim_reset (state);
15697 /* Use simulator state STATE to calculate the execution time of
15698 instruction sequence SEQ. */
15700 static unsigned int
15701 mips_seq_time (struct mips_sim *state, rtx_insn *seq)
15703 mips_sim_reset (state);
15704 for (rtx_insn *insn = seq; insn; insn = NEXT_INSN (insn))
15706 mips_sim_wait_insn (state, insn);
15707 mips_sim_issue_insn (state, insn);
15709 return state->time;
15712 /* Return the execution-time cost of mips_tuning_info.fast_mult_zero_zero_p
15713 setting SETTING, using STATE to simulate instruction sequences. */
15715 static unsigned int
15716 mips_mult_zero_zero_cost (struct mips_sim *state, bool setting)
15718 mips_tuning_info.fast_mult_zero_zero_p = setting;
15721 enum machine_mode dword_mode = TARGET_64BIT ? TImode : DImode;
15722 rtx hilo = gen_rtx_REG (dword_mode, MD_REG_FIRST);
15723 mips_emit_move_or_split (hilo, const0_rtx, SPLIT_FOR_SPEED);
15725 /* If the target provides mulsidi3_32bit then that's the most likely
15726 consumer of the result. Test for bypasses. */
15727 if (dword_mode == DImode && HAVE_maddsidi4)
15729 rtx gpr = gen_rtx_REG (SImode, GP_REG_FIRST + 4);
15730 emit_insn (gen_maddsidi4 (hilo, gpr, gpr, hilo));
15733 unsigned int time = mips_seq_time (state, get_insns ());
15738 /* Check the relative speeds of "MULT $0,$0" and "MTLO $0; MTHI $0"
15739 and set up mips_tuning_info.fast_mult_zero_zero_p accordingly.
15740 Prefer MULT -- which is shorter -- in the event of a tie. */
15743 mips_set_fast_mult_zero_zero_p (struct mips_sim *state)
15746 /* No MTLO or MTHI available. */
15747 mips_tuning_info.fast_mult_zero_zero_p = true;
15750 unsigned int true_time = mips_mult_zero_zero_cost (state, true);
15751 unsigned int false_time = mips_mult_zero_zero_cost (state, false);
15752 mips_tuning_info.fast_mult_zero_zero_p = (true_time <= false_time);
15756 /* Set up costs based on the current architecture and tuning settings. */
15759 mips_set_tuning_info (void)
15761 if (mips_tuning_info.initialized_p
15762 && mips_tuning_info.arch == mips_arch
15763 && mips_tuning_info.tune == mips_tune
15764 && mips_tuning_info.mips16_p == TARGET_MIPS16)
15767 mips_tuning_info.arch = mips_arch;
15768 mips_tuning_info.tune = mips_tune;
15769 mips_tuning_info.mips16_p = TARGET_MIPS16;
15770 mips_tuning_info.initialized_p = true;
15774 struct mips_sim state;
15775 mips_sim_init (&state, alloca (state_size ()));
15777 mips_set_fast_mult_zero_zero_p (&state);
15782 /* Implement TARGET_EXPAND_TO_RTL_HOOK. */
15785 mips_expand_to_rtl_hook (void)
15787 /* We need to call this at a point where we can safely create sequences
15788 of instructions, so TARGET_OVERRIDE_OPTIONS is too early. We also
15789 need to call it at a point where the DFA infrastructure is not
15790 already in use, so we can't just call it lazily on demand.
15792 At present, mips_tuning_info is only needed during post-expand
15793 RTL passes such as split_insns, so this hook should be early enough.
15794 We may need to move the call elsewhere if mips_tuning_info starts
15795 to be used for other things (such as rtx_costs, or expanders that
15796 could be called during gimple optimization). */
15797 mips_set_tuning_info ();
15800 /* The VR4130 pipeline issues aligned pairs of instructions together,
15801 but it stalls the second instruction if it depends on the first.
15802 In order to cut down the amount of logic required, this dependence
15803 check is not based on a full instruction decode. Instead, any non-SPECIAL
15804 instruction is assumed to modify the register specified by bits 20-16
15805 (which is usually the "rt" field).
15807 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
15808 input, so we can end up with a false dependence between the branch
15809 and its delay slot. If this situation occurs in instruction INSN,
15810 try to avoid it by swapping rs and rt. */
15813 vr4130_avoid_branch_rt_conflict (rtx_insn *insn)
15815 rtx_insn *first, *second;
15817 first = SEQ_BEGIN (insn);
15818 second = SEQ_END (insn);
15820 && NONJUMP_INSN_P (second)
15821 && GET_CODE (PATTERN (first)) == SET
15822 && GET_CODE (SET_DEST (PATTERN (first))) == PC
15823 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
15825 /* Check for the right kind of condition. */
15826 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
15827 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
15828 && REG_P (XEXP (cond, 0))
15829 && REG_P (XEXP (cond, 1))
15830 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
15831 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
15833 /* SECOND mentions the rt register but not the rs register. */
15834 rtx tmp = XEXP (cond, 0);
15835 XEXP (cond, 0) = XEXP (cond, 1);
15836 XEXP (cond, 1) = tmp;
15841 /* Implement -mvr4130-align. Go through each basic block and simulate the
15842 processor pipeline. If we find that a pair of instructions could execute
15843 in parallel, and the first of those instructions is not 8-byte aligned,
15844 insert a nop to make it aligned. */
15847 vr4130_align_insns (void)
15849 struct mips_sim state;
15850 rtx_insn *insn, *subinsn, *last, *last2, *next;
15855 /* LAST is the last instruction before INSN to have a nonzero length.
15856 LAST2 is the last such instruction before LAST. */
15860 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
15863 mips_sim_init (&state, alloca (state_size ()));
15864 for (insn = get_insns (); insn != 0; insn = next)
15866 unsigned int length;
15868 next = NEXT_INSN (insn);
15870 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
15871 This isn't really related to the alignment pass, but we do it on
15872 the fly to avoid a separate instruction walk. */
15873 vr4130_avoid_branch_rt_conflict (insn);
15875 length = get_attr_length (insn);
15876 if (length > 0 && USEFUL_INSN_P (insn))
15877 FOR_EACH_SUBINSN (subinsn, insn)
15879 mips_sim_wait_insn (&state, subinsn);
15881 /* If we want this instruction to issue in parallel with the
15882 previous one, make sure that the previous instruction is
15883 aligned. There are several reasons why this isn't worthwhile
15884 when the second instruction is a call:
15886 - Calls are less likely to be performance critical,
15887 - There's a good chance that the delay slot can execute
15888 in parallel with the call.
15889 - The return address would then be unaligned.
15891 In general, if we're going to insert a nop between instructions
15892 X and Y, it's better to insert it immediately after X. That
15893 way, if the nop makes Y aligned, it will also align any labels
15894 between X and Y. */
15895 if (state.insns_left != state.issue_rate
15896 && !CALL_P (subinsn))
15898 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
15900 /* SUBINSN is the first instruction in INSN and INSN is
15901 aligned. We want to align the previous instruction
15902 instead, so insert a nop between LAST2 and LAST.
15904 Note that LAST could be either a single instruction
15905 or a branch with a delay slot. In the latter case,
15906 LAST, like INSN, is already aligned, but the delay
15907 slot must have some extra delay that stops it from
15908 issuing at the same time as the branch. We therefore
15909 insert a nop before the branch in order to align its
15911 gcc_assert (last2);
15912 emit_insn_after (gen_nop (), last2);
15915 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
15917 /* SUBINSN is the delay slot of INSN, but INSN is
15918 currently unaligned. Insert a nop between
15919 LAST and INSN to align it. */
15921 emit_insn_after (gen_nop (), last);
15925 mips_sim_issue_insn (&state, subinsn);
15927 mips_sim_finish_insn (&state, insn);
15929 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
15930 length = get_attr_length (insn);
15933 /* If the instruction is an asm statement or multi-instruction
15934 mips.md patern, the length is only an estimate. Insert an
15935 8 byte alignment after it so that the following instructions
15936 can be handled correctly. */
15937 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
15938 && (recog_memoized (insn) < 0 || length >= 8))
15940 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
15941 next = NEXT_INSN (next);
15942 mips_sim_next_cycle (&state);
15945 else if (length & 4)
15946 aligned_p = !aligned_p;
15951 /* See whether INSN is an aligned label. */
15952 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
15958 /* This structure records that the current function has a LO_SUM
15959 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
15960 the largest offset applied to BASE by all such LO_SUMs. */
15961 struct mips_lo_sum_offset {
15963 HOST_WIDE_INT offset;
15966 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
15969 mips_hash_base (rtx base)
15971 int do_not_record_p;
15973 return hash_rtx (base, GET_MODE (base), &do_not_record_p, NULL, false);
15976 /* Hashtable helpers. */
15978 struct mips_lo_sum_offset_hasher : typed_free_remove <mips_lo_sum_offset>
15980 typedef mips_lo_sum_offset value_type;
15981 typedef rtx_def compare_type;
15982 static inline hashval_t hash (const value_type *);
15983 static inline bool equal (const value_type *, const compare_type *);
15986 /* Hash-table callbacks for mips_lo_sum_offsets. */
15989 mips_lo_sum_offset_hasher::hash (const value_type *entry)
15991 return mips_hash_base (entry->base);
15995 mips_lo_sum_offset_hasher::equal (const value_type *entry,
15996 const compare_type *value)
15998 return rtx_equal_p (entry->base, value);
16001 typedef hash_table<mips_lo_sum_offset_hasher> mips_offset_table;
16003 /* Look up symbolic constant X in HTAB, which is a hash table of
16004 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
16005 paired with a recorded LO_SUM, otherwise record X in the table. */
16008 mips_lo_sum_offset_lookup (mips_offset_table *htab, rtx x,
16009 enum insert_option option)
16012 mips_lo_sum_offset **slot;
16013 struct mips_lo_sum_offset *entry;
16015 /* Split X into a base and offset. */
16016 split_const (x, &base, &offset);
16017 if (UNSPEC_ADDRESS_P (base))
16018 base = UNSPEC_ADDRESS (base);
16020 /* Look up the base in the hash table. */
16021 slot = htab->find_slot_with_hash (base, mips_hash_base (base), option);
16025 entry = (struct mips_lo_sum_offset *) *slot;
16026 if (option == INSERT)
16030 entry = XNEW (struct mips_lo_sum_offset);
16031 entry->base = base;
16032 entry->offset = INTVAL (offset);
16037 if (INTVAL (offset) > entry->offset)
16038 entry->offset = INTVAL (offset);
16041 return INTVAL (offset) <= entry->offset;
16044 /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table.
16045 Record every LO_SUM in *LOC. */
16048 mips_record_lo_sum (rtx *loc, void *data)
16050 if (GET_CODE (*loc) == LO_SUM)
16051 mips_lo_sum_offset_lookup ((mips_offset_table*) data,
16052 XEXP (*loc, 1), INSERT);
16056 /* Return true if INSN is a SET of an orphaned high-part relocation.
16057 HTAB is a hash table of mips_lo_sum_offsets that describes all the
16058 LO_SUMs in the current function. */
16061 mips_orphaned_high_part_p (mips_offset_table *htab, rtx_insn *insn)
16063 enum mips_symbol_type type;
16066 set = single_set (insn);
16069 /* Check for %his. */
16071 if (GET_CODE (x) == HIGH
16072 && absolute_symbolic_operand (XEXP (x, 0), VOIDmode))
16073 return !mips_lo_sum_offset_lookup (htab, XEXP (x, 0), NO_INSERT);
16075 /* Check for local %gots (and %got_pages, which is redundant but OK). */
16076 if (GET_CODE (x) == UNSPEC
16077 && XINT (x, 1) == UNSPEC_LOAD_GOT
16078 && mips_symbolic_constant_p (XVECEXP (x, 0, 1),
16079 SYMBOL_CONTEXT_LEA, &type)
16080 && type == SYMBOL_GOTOFF_PAGE)
16081 return !mips_lo_sum_offset_lookup (htab, XVECEXP (x, 0, 1), NO_INSERT);
16086 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
16087 INSN and a previous instruction, avoid it by inserting nops after
16090 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
16091 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
16092 before using the value of that register. *HILO_DELAY counts the
16093 number of instructions since the last hilo hazard (that is,
16094 the number of instructions since the last MFLO or MFHI).
16096 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
16097 for the next instruction.
16099 LO_REG is an rtx for the LO register, used in dependence checking. */
16102 mips_avoid_hazard (rtx_insn *after, rtx_insn *insn, int *hilo_delay,
16103 rtx *delayed_reg, rtx lo_reg)
16108 pattern = PATTERN (insn);
16110 /* Do not put the whole function in .set noreorder if it contains
16111 an asm statement. We don't know whether there will be hazards
16112 between the asm statement and the gcc-generated code. */
16113 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
16114 cfun->machine->all_noreorder_p = false;
16116 /* Ignore zero-length instructions (barriers and the like). */
16117 ninsns = get_attr_length (insn) / 4;
16121 /* Work out how many nops are needed. Note that we only care about
16122 registers that are explicitly mentioned in the instruction's pattern.
16123 It doesn't matter that calls use the argument registers or that they
16124 clobber hi and lo. */
16125 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
16126 nops = 2 - *hilo_delay;
16127 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
16132 /* Insert the nops between this instruction and the previous one.
16133 Each new nop takes us further from the last hilo hazard. */
16134 *hilo_delay += nops;
16136 emit_insn_after (gen_hazard_nop (), after);
16138 /* Set up the state for the next instruction. */
16139 *hilo_delay += ninsns;
16141 if (INSN_CODE (insn) >= 0)
16142 switch (get_attr_hazard (insn))
16152 set = single_set (insn);
16154 *delayed_reg = SET_DEST (set);
16159 /* Go through the instruction stream and insert nops where necessary.
16160 Also delete any high-part relocations whose partnering low parts
16161 are now all dead. See if the whole function can then be put into
16162 .set noreorder and .set nomacro. */
16165 mips_reorg_process_insns (void)
16167 rtx_insn *insn, *last_insn, *subinsn, *next_insn;
16168 rtx lo_reg, delayed_reg;
16171 /* Force all instructions to be split into their final form. */
16172 split_all_insns_noflow ();
16174 /* Recalculate instruction lengths without taking nops into account. */
16175 cfun->machine->ignore_hazard_length_p = true;
16176 shorten_branches (get_insns ());
16178 cfun->machine->all_noreorder_p = true;
16180 /* We don't track MIPS16 PC-relative offsets closely enough to make
16181 a good job of "set .noreorder" code in MIPS16 mode. */
16183 cfun->machine->all_noreorder_p = false;
16185 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
16186 if (!TARGET_EXPLICIT_RELOCS)
16187 cfun->machine->all_noreorder_p = false;
16189 /* Profiled functions can't be all noreorder because the profiler
16190 support uses assembler macros. */
16192 cfun->machine->all_noreorder_p = false;
16194 /* Code compiled with -mfix-vr4120, -mfix-rm7000 or -mfix-24k can't be
16195 all noreorder because we rely on the assembler to work around some
16196 errata. The R5900 too has several bugs. */
16197 if (TARGET_FIX_VR4120
16198 || TARGET_FIX_RM7000
16200 || TARGET_MIPS5900)
16201 cfun->machine->all_noreorder_p = false;
16203 /* The same is true for -mfix-vr4130 if we might generate MFLO or
16204 MFHI instructions. Note that we avoid using MFLO and MFHI if
16205 the VR4130 MACC and DMACC instructions are available instead;
16206 see the *mfhilo_{si,di}_macc patterns. */
16207 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
16208 cfun->machine->all_noreorder_p = false;
16210 mips_offset_table htab (37);
16212 /* Make a first pass over the instructions, recording all the LO_SUMs. */
16213 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
16214 FOR_EACH_SUBINSN (subinsn, insn)
16215 if (USEFUL_INSN_P (subinsn))
16217 rtx body = PATTERN (insn);
16218 int noperands = asm_noperands (body);
16219 if (noperands >= 0)
16221 rtx *ops = XALLOCAVEC (rtx, noperands);
16222 bool *used = XALLOCAVEC (bool, noperands);
16223 const char *string = decode_asm_operands (body, ops, NULL, NULL,
16225 get_referenced_operands (string, used, noperands);
16226 for (int i = 0; i < noperands; ++i)
16228 for_each_rtx (&ops[i], mips_record_lo_sum, &htab);
16231 for_each_rtx (&PATTERN (subinsn), mips_record_lo_sum, &htab);
16237 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
16239 /* Make a second pass over the instructions. Delete orphaned
16240 high-part relocations or turn them into NOPs. Avoid hazards
16241 by inserting NOPs. */
16242 for (insn = get_insns (); insn != 0; insn = next_insn)
16244 next_insn = NEXT_INSN (insn);
16245 if (USEFUL_INSN_P (insn))
16247 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
16249 /* If we find an orphaned high-part relocation in a delay
16250 slot, it's easier to turn that instruction into a NOP than
16251 to delete it. The delay slot will be a NOP either way. */
16252 FOR_EACH_SUBINSN (subinsn, insn)
16253 if (INSN_P (subinsn))
16255 if (mips_orphaned_high_part_p (&htab, subinsn))
16257 PATTERN (subinsn) = gen_nop ();
16258 INSN_CODE (subinsn) = CODE_FOR_nop;
16260 mips_avoid_hazard (last_insn, subinsn, &hilo_delay,
16261 &delayed_reg, lo_reg);
16267 /* INSN is a single instruction. Delete it if it's an
16268 orphaned high-part relocation. */
16269 if (mips_orphaned_high_part_p (&htab, insn))
16270 delete_insn (insn);
16271 /* Also delete cache barriers if the last instruction
16272 was an annulled branch. INSN will not be speculatively
16274 else if (recog_memoized (insn) == CODE_FOR_r10k_cache_barrier
16276 && JUMP_P (SEQ_BEGIN (last_insn))
16277 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn)))
16278 delete_insn (insn);
16281 mips_avoid_hazard (last_insn, insn, &hilo_delay,
16282 &delayed_reg, lo_reg);
16290 /* Return true if the function has a long branch instruction. */
16293 mips_has_long_branch_p (void)
16295 rtx_insn *insn, *subinsn;
16298 /* We need up-to-date instruction lengths. */
16299 shorten_branches (get_insns ());
16301 /* Look for a branch that is longer than normal. The normal length for
16302 non-MIPS16 branches is 8, because the length includes the delay slot.
16303 It is 4 for MIPS16, because MIPS16 branches are extended instructions,
16304 but they have no delay slot. */
16305 normal_length = (TARGET_MIPS16 ? 4 : 8);
16306 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
16307 FOR_EACH_SUBINSN (subinsn, insn)
16308 if (JUMP_P (subinsn)
16309 && get_attr_length (subinsn) > normal_length
16310 && (any_condjump_p (subinsn) || any_uncondjump_p (subinsn)))
16316 /* If we are using a GOT, but have not decided to use a global pointer yet,
16317 see whether we need one to implement long branches. Convert the ghost
16318 global-pointer instructions into real ones if so. */
16321 mips_expand_ghost_gp_insns (void)
16323 /* Quick exit if we already know that we will or won't need a
16325 if (!TARGET_USE_GOT
16326 || cfun->machine->global_pointer == INVALID_REGNUM
16327 || mips_must_initialize_gp_p ())
16330 /* Run a full check for long branches. */
16331 if (!mips_has_long_branch_p ())
16334 /* We've now established that we need $gp. */
16335 cfun->machine->must_initialize_gp_p = true;
16336 split_all_insns_noflow ();
16341 /* Subroutine of mips_reorg to manage passes that require DF. */
16344 mips_df_reorg (void)
16346 /* Create def-use chains. */
16347 df_set_flags (DF_EQ_NOTES);
16348 df_chain_add_problem (DF_UD_CHAIN);
16351 if (TARGET_RELAX_PIC_CALLS)
16352 mips_annotate_pic_calls ();
16354 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE)
16355 r10k_insert_cache_barriers ();
16357 df_finish_pass (false);
16360 /* Emit code to load LABEL_REF SRC into MIPS16 register DEST. This is
16361 called very late in mips_reorg, but the caller is required to run
16362 mips16_lay_out_constants on the result. */
16365 mips16_load_branch_target (rtx dest, rtx src)
16367 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
16371 if (mips_cfun_has_cprestore_slot_p ())
16372 mips_emit_move (dest, mips_cprestore_slot (dest, true));
16374 mips_emit_move (dest, pic_offset_table_rtx);
16375 page = mips_unspec_address (src, SYMBOL_GOTOFF_PAGE);
16376 low = mips_unspec_address (src, SYMBOL_GOT_PAGE_OFST);
16377 emit_insn (gen_rtx_SET (VOIDmode, dest,
16378 PMODE_INSN (gen_unspec_got, (dest, page))));
16379 emit_insn (gen_rtx_SET (VOIDmode, dest,
16380 gen_rtx_LO_SUM (Pmode, dest, low)));
16384 src = mips_unspec_address (src, SYMBOL_ABSOLUTE);
16385 mips_emit_move (dest, src);
16389 /* If we're compiling a MIPS16 function, look for and split any long branches.
16390 This must be called after all other instruction modifications in
16394 mips16_split_long_branches (void)
16396 bool something_changed;
16398 if (!TARGET_MIPS16)
16401 /* Loop until the alignments for all targets are sufficient. */
16406 shorten_branches (get_insns ());
16407 something_changed = false;
16408 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
16410 && get_attr_length (insn) > 4
16411 && (any_condjump_p (insn) || any_uncondjump_p (insn)))
16413 rtx old_label, temp, saved_temp;
16414 rtx_code_label *new_label;
16416 rtx_insn *jump, *jump_sequence;
16420 /* Free up a MIPS16 register by saving it in $1. */
16421 saved_temp = gen_rtx_REG (Pmode, AT_REGNUM);
16422 temp = gen_rtx_REG (Pmode, GP_REG_FIRST + 2);
16423 emit_move_insn (saved_temp, temp);
16425 /* Load the branch target into TEMP. */
16426 old_label = JUMP_LABEL (insn);
16427 target = gen_rtx_LABEL_REF (Pmode, old_label);
16428 mips16_load_branch_target (temp, target);
16430 /* Jump to the target and restore the register's
16432 jump = emit_jump_insn (PMODE_INSN (gen_indirect_jump_and_restore,
16433 (temp, temp, saved_temp)));
16434 JUMP_LABEL (jump) = old_label;
16435 LABEL_NUSES (old_label)++;
16437 /* Rewrite any symbolic references that are supposed to use
16438 a PC-relative constant pool. */
16439 mips16_lay_out_constants (false);
16441 if (simplejump_p (insn))
16442 /* We're going to replace INSN with a longer form. */
16446 /* Create a branch-around label for the original
16448 new_label = gen_label_rtx ();
16449 emit_label (new_label);
16452 jump_sequence = get_insns ();
16455 emit_insn_after (jump_sequence, insn);
16457 invert_jump (insn, new_label, false);
16459 delete_insn (insn);
16460 something_changed = true;
16463 while (something_changed);
16466 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
16471 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during
16472 insn splitting in mips16_lay_out_constants, DF insn info is only kept up
16473 to date if the CFG is available. */
16474 if (mips_cfg_in_reorg ())
16475 compute_bb_for_insn ();
16476 mips16_lay_out_constants (true);
16477 if (mips_cfg_in_reorg ())
16480 free_bb_for_insn ();
16484 /* We use a machine specific pass to do a second machine dependent reorg
16485 pass after delay branch scheduling. */
16487 static unsigned int
16488 mips_machine_reorg2 (void)
16490 mips_reorg_process_insns ();
16492 && TARGET_EXPLICIT_RELOCS
16494 && TARGET_VR4130_ALIGN)
16495 vr4130_align_insns ();
16496 if (mips_expand_ghost_gp_insns ())
16497 /* The expansion could invalidate some of the VR4130 alignment
16498 optimizations, but this should be an extremely rare case anyhow. */
16499 mips_reorg_process_insns ();
16500 mips16_split_long_branches ();
16506 const pass_data pass_data_mips_machine_reorg2 =
16508 RTL_PASS, /* type */
16509 "mach2", /* name */
16510 OPTGROUP_NONE, /* optinfo_flags */
16511 TV_MACH_DEP, /* tv_id */
16512 0, /* properties_required */
16513 0, /* properties_provided */
16514 0, /* properties_destroyed */
16515 0, /* todo_flags_start */
16516 0, /* todo_flags_finish */
16519 class pass_mips_machine_reorg2 : public rtl_opt_pass
16522 pass_mips_machine_reorg2(gcc::context *ctxt)
16523 : rtl_opt_pass(pass_data_mips_machine_reorg2, ctxt)
16526 /* opt_pass methods: */
16527 virtual unsigned int execute (function *) { return mips_machine_reorg2 (); }
16529 }; // class pass_mips_machine_reorg2
16531 } // anon namespace
16534 make_pass_mips_machine_reorg2 (gcc::context *ctxt)
16536 return new pass_mips_machine_reorg2 (ctxt);
16540 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
16541 in order to avoid duplicating too much logic from elsewhere. */
16544 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
16545 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
16548 rtx this_rtx, temp1, temp2, fnaddr;
16550 bool use_sibcall_p;
16552 /* Pretend to be a post-reload pass while generating rtl. */
16553 reload_completed = 1;
16555 /* Mark the end of the (empty) prologue. */
16556 emit_note (NOTE_INSN_PROLOGUE_END);
16558 /* Determine if we can use a sibcall to call FUNCTION directly. */
16559 fnaddr = XEXP (DECL_RTL (function), 0);
16560 use_sibcall_p = (mips_function_ok_for_sibcall (function, NULL)
16561 && const_call_insn_operand (fnaddr, Pmode));
16563 /* Determine if we need to load FNADDR from the GOT. */
16565 && (mips_got_symbol_type_p
16566 (mips_classify_symbol (fnaddr, SYMBOL_CONTEXT_LEA))))
16568 /* Pick a global pointer. Use a call-clobbered register if
16569 TARGET_CALL_SAVED_GP. */
16570 cfun->machine->global_pointer
16571 = TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM;
16572 cfun->machine->must_initialize_gp_p = true;
16573 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
16575 /* Set up the global pointer for n32 or n64 abicalls. */
16576 mips_emit_loadgp ();
16579 /* We need two temporary registers in some cases. */
16580 temp1 = gen_rtx_REG (Pmode, 2);
16581 temp2 = gen_rtx_REG (Pmode, 3);
16583 /* Find out which register contains the "this" pointer. */
16584 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
16585 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
16587 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST);
16589 /* Add DELTA to THIS_RTX. */
16592 rtx offset = GEN_INT (delta);
16593 if (!SMALL_OPERAND (delta))
16595 mips_emit_move (temp1, offset);
16598 emit_insn (gen_add3_insn (this_rtx, this_rtx, offset));
16601 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
16602 if (vcall_offset != 0)
16606 /* Set TEMP1 to *THIS_RTX. */
16607 mips_emit_move (temp1, gen_rtx_MEM (Pmode, this_rtx));
16609 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
16610 addr = mips_add_offset (temp2, temp1, vcall_offset);
16612 /* Load the offset and add it to THIS_RTX. */
16613 mips_emit_move (temp1, gen_rtx_MEM (Pmode, addr));
16614 emit_insn (gen_add3_insn (this_rtx, this_rtx, temp1));
16617 /* Jump to the target function. Use a sibcall if direct jumps are
16618 allowed, otherwise load the address into a register first. */
16621 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
16622 SIBLING_CALL_P (insn) = 1;
16626 /* This is messy. GAS treats "la $25,foo" as part of a call
16627 sequence and may allow a global "foo" to be lazily bound.
16628 The general move patterns therefore reject this combination.
16630 In this context, lazy binding would actually be OK
16631 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
16632 TARGET_CALL_SAVED_GP; see mips_load_call_address.
16633 We must therefore load the address via a temporary
16634 register if mips_dangerous_for_la25_p.
16636 If we jump to the temporary register rather than $25,
16637 the assembler can use the move insn to fill the jump's
16640 We can use the same technique for MIPS16 code, where $25
16641 is not a valid JR register. */
16642 if (TARGET_USE_PIC_FN_ADDR_REG
16644 && !mips_dangerous_for_la25_p (fnaddr))
16645 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
16646 mips_load_call_address (MIPS_CALL_SIBCALL, temp1, fnaddr);
16648 if (TARGET_USE_PIC_FN_ADDR_REG
16649 && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
16650 mips_emit_move (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
16651 emit_jump_insn (gen_indirect_jump (temp1));
16654 /* Run just enough of rest_of_compilation. This sequence was
16655 "borrowed" from alpha.c. */
16656 insn = get_insns ();
16657 split_all_insns_noflow ();
16658 mips16_lay_out_constants (true);
16659 shorten_branches (insn);
16660 final_start_function (insn, file, 1);
16661 final (insn, file, 1);
16662 final_end_function ();
16664 /* Clean up the vars set above. Note that final_end_function resets
16665 the global pointer for us. */
16666 reload_completed = 0;
16670 /* The last argument passed to mips_set_compression_mode,
16671 or negative if the function hasn't been called yet. */
16672 static unsigned int old_compression_mode = -1;
16674 /* Set up the target-dependent global state for ISA mode COMPRESSION_MODE,
16675 which is either MASK_MIPS16 or MASK_MICROMIPS. */
16678 mips_set_compression_mode (unsigned int compression_mode)
16681 if (compression_mode == old_compression_mode)
16684 /* Restore base settings of various flags. */
16685 target_flags = mips_base_target_flags;
16686 flag_schedule_insns = mips_base_schedule_insns;
16687 flag_reorder_blocks_and_partition = mips_base_reorder_blocks_and_partition;
16688 flag_move_loop_invariants = mips_base_move_loop_invariants;
16689 align_loops = mips_base_align_loops;
16690 align_jumps = mips_base_align_jumps;
16691 align_functions = mips_base_align_functions;
16692 target_flags &= ~(MASK_MIPS16 | MASK_MICROMIPS);
16693 target_flags |= compression_mode;
16695 if (compression_mode & MASK_MIPS16)
16697 /* Switch to MIPS16 mode. */
16698 target_flags |= MASK_MIPS16;
16700 /* Turn off SYNCI if it was on, MIPS16 doesn't support it. */
16701 target_flags &= ~MASK_SYNCI;
16703 /* Don't run the scheduler before reload, since it tends to
16704 increase register pressure. */
16705 flag_schedule_insns = 0;
16707 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
16708 the whole function to be in a single section. */
16709 flag_reorder_blocks_and_partition = 0;
16711 /* Don't move loop invariants, because it tends to increase
16712 register pressure. It also introduces an extra move in cases
16713 where the constant is the first operand in a two-operand binary
16714 instruction, or when it forms a register argument to a functon
16716 flag_move_loop_invariants = 0;
16718 target_flags |= MASK_EXPLICIT_RELOCS;
16720 /* Experiments suggest we get the best overall section-anchor
16721 results from using the range of an unextended LW or SW. Code
16722 that makes heavy use of byte or short accesses can do better
16723 with ranges of 0...31 and 0...63 respectively, but most code is
16724 sensitive to the range of LW and SW instead. */
16725 targetm.min_anchor_offset = 0;
16726 targetm.max_anchor_offset = 127;
16728 targetm.const_anchor = 0;
16730 /* MIPS16 has no BAL instruction. */
16731 target_flags &= ~MASK_RELAX_PIC_CALLS;
16733 /* The R4000 errata don't apply to any known MIPS16 cores.
16734 It's simpler to make the R4000 fixes and MIPS16 mode
16735 mutually exclusive. */
16736 target_flags &= ~MASK_FIX_R4000;
16738 if (flag_pic && !TARGET_OLDABI)
16739 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
16742 sorry ("MIPS16 -mxgot code");
16744 if (TARGET_HARD_FLOAT_ABI && !TARGET_OLDABI)
16745 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
16749 /* Switch to microMIPS or the standard encoding. */
16751 if (TARGET_MICROMIPS)
16752 /* Avoid branch likely. */
16753 target_flags &= ~MASK_BRANCHLIKELY;
16755 /* Provide default values for align_* for 64-bit targets. */
16758 if (align_loops == 0)
16760 if (align_jumps == 0)
16762 if (align_functions == 0)
16763 align_functions = 8;
16766 targetm.min_anchor_offset = -32768;
16767 targetm.max_anchor_offset = 32767;
16769 targetm.const_anchor = 0x8000;
16772 /* (Re)initialize MIPS target internals for new ISA. */
16773 mips_init_relocs ();
16775 if (compression_mode & MASK_MIPS16)
16777 if (!mips16_globals)
16778 mips16_globals = save_target_globals_default_opts ();
16780 restore_target_globals (mips16_globals);
16783 restore_target_globals (&default_target_globals);
16785 old_compression_mode = compression_mode;
16788 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
16789 function should use the MIPS16 or microMIPS ISA and switch modes
16793 mips_set_current_function (tree fndecl)
16795 mips_set_compression_mode (mips_get_compress_mode (fndecl));
16798 /* Allocate a chunk of memory for per-function machine-dependent data. */
16800 static struct machine_function *
16801 mips_init_machine_status (void)
16803 return ggc_cleared_alloc<machine_function> ();
16806 /* Return the processor associated with the given ISA level, or null
16807 if the ISA isn't valid. */
16809 static const struct mips_cpu_info *
16810 mips_cpu_info_from_isa (int isa)
16814 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
16815 if (mips_cpu_info_table[i].isa == isa)
16816 return mips_cpu_info_table + i;
16821 /* Return a mips_cpu_info entry determined by an option valued
16824 static const struct mips_cpu_info *
16825 mips_cpu_info_from_opt (int opt)
16829 case MIPS_ARCH_OPTION_FROM_ABI:
16830 /* 'from-abi' selects the most compatible architecture for the
16831 given ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit
16832 ABIs. For the EABIs, we have to decide whether we're using
16833 the 32-bit or 64-bit version. */
16834 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
16835 : ABI_NEEDS_64BIT_REGS ? 3
16836 : (TARGET_64BIT ? 3 : 1));
16838 case MIPS_ARCH_OPTION_NATIVE:
16839 gcc_unreachable ();
16842 return &mips_cpu_info_table[opt];
16846 /* Return a default mips_cpu_info entry, given that no -march= option
16847 was explicitly specified. */
16849 static const struct mips_cpu_info *
16850 mips_default_arch (void)
16852 #if defined (MIPS_CPU_STRING_DEFAULT)
16854 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
16855 if (strcmp (mips_cpu_info_table[i].name, MIPS_CPU_STRING_DEFAULT) == 0)
16856 return mips_cpu_info_table + i;
16857 gcc_unreachable ();
16858 #elif defined (MIPS_ISA_DEFAULT)
16859 return mips_cpu_info_from_isa (MIPS_ISA_DEFAULT);
16861 /* 'from-abi' makes a good default: you get whatever the ABI
16863 return mips_cpu_info_from_opt (MIPS_ARCH_OPTION_FROM_ABI);
16867 /* Set up globals to generate code for the ISA or processor
16868 described by INFO. */
16871 mips_set_architecture (const struct mips_cpu_info *info)
16875 mips_arch_info = info;
16876 mips_arch = info->cpu;
16877 mips_isa = info->isa;
16881 mips_isa_rev = (mips_isa & 31) + 1;
16885 /* Likewise for tuning. */
16888 mips_set_tune (const struct mips_cpu_info *info)
16892 mips_tune_info = info;
16893 mips_tune = info->cpu;
16897 /* Implement TARGET_OPTION_OVERRIDE. */
16900 mips_option_override (void)
16902 int i, start, regno, mode;
16904 if (global_options_set.x_mips_isa_option)
16905 mips_isa_option_info = &mips_cpu_info_table[mips_isa_option];
16907 #ifdef SUBTARGET_OVERRIDE_OPTIONS
16908 SUBTARGET_OVERRIDE_OPTIONS;
16911 /* MIPS16 and microMIPS cannot coexist. */
16912 if (TARGET_MICROMIPS && TARGET_MIPS16)
16913 error ("unsupported combination: %s", "-mips16 -mmicromips");
16915 /* Save the base compression state and process flags as though we
16916 were generating uncompressed code. */
16917 mips_base_compression_flags = TARGET_COMPRESSION;
16918 target_flags &= ~TARGET_COMPRESSION;
16920 /* -mno-float overrides -mhard-float and -msoft-float. */
16921 if (TARGET_NO_FLOAT)
16923 target_flags |= MASK_SOFT_FLOAT_ABI;
16924 target_flags_explicit |= MASK_SOFT_FLOAT_ABI;
16927 if (TARGET_FLIP_MIPS16)
16928 TARGET_INTERLINK_COMPRESSED = 1;
16930 /* Set the small data limit. */
16931 mips_small_data_threshold = (global_options_set.x_g_switch_value
16933 : MIPS_DEFAULT_GVALUE);
16935 /* The following code determines the architecture and register size.
16936 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
16937 The GAS and GCC code should be kept in sync as much as possible. */
16939 if (global_options_set.x_mips_arch_option)
16940 mips_set_architecture (mips_cpu_info_from_opt (mips_arch_option));
16942 if (mips_isa_option_info != 0)
16944 if (mips_arch_info == 0)
16945 mips_set_architecture (mips_isa_option_info);
16946 else if (mips_arch_info->isa != mips_isa_option_info->isa)
16947 error ("%<-%s%> conflicts with the other architecture options, "
16948 "which specify a %s processor",
16949 mips_isa_option_info->name,
16950 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
16953 if (mips_arch_info == 0)
16954 mips_set_architecture (mips_default_arch ());
16956 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
16957 error ("%<-march=%s%> is not compatible with the selected ABI",
16958 mips_arch_info->name);
16960 /* Optimize for mips_arch, unless -mtune selects a different processor. */
16961 if (global_options_set.x_mips_tune_option)
16962 mips_set_tune (mips_cpu_info_from_opt (mips_tune_option));
16964 if (mips_tune_info == 0)
16965 mips_set_tune (mips_arch_info);
16967 if ((target_flags_explicit & MASK_64BIT) != 0)
16969 /* The user specified the size of the integer registers. Make sure
16970 it agrees with the ABI and ISA. */
16971 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
16972 error ("%<-mgp64%> used with a 32-bit processor");
16973 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
16974 error ("%<-mgp32%> used with a 64-bit ABI");
16975 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
16976 error ("%<-mgp64%> used with a 32-bit ABI");
16980 /* Infer the integer register size from the ABI and processor.
16981 Restrict ourselves to 32-bit registers if that's all the
16982 processor has, or if the ABI cannot handle 64-bit registers. */
16983 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
16984 target_flags &= ~MASK_64BIT;
16986 target_flags |= MASK_64BIT;
16989 if ((target_flags_explicit & MASK_FLOAT64) != 0)
16991 if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
16992 error ("unsupported combination: %s", "-mfp64 -msingle-float");
16993 else if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
16994 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
16995 else if (!TARGET_64BIT && TARGET_FLOAT64)
16997 if (!ISA_HAS_MXHC1)
16998 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
16999 " the target supports the mfhc1 and mthc1 instructions");
17000 else if (mips_abi != ABI_32)
17001 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
17007 /* -msingle-float selects 32-bit float registers. Otherwise the
17008 float registers should be the same size as the integer ones. */
17009 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
17010 target_flags |= MASK_FLOAT64;
17012 target_flags &= ~MASK_FLOAT64;
17015 /* End of code shared with GAS. */
17017 /* The R5900 FPU only supports single precision. */
17018 if (TARGET_MIPS5900 && TARGET_HARD_FLOAT_ABI && TARGET_DOUBLE_FLOAT)
17019 error ("unsupported combination: %s",
17020 "-march=r5900 -mhard-float -mdouble-float");
17022 /* If a -mlong* option was given, check that it matches the ABI,
17023 otherwise infer the -mlong* setting from the other options. */
17024 if ((target_flags_explicit & MASK_LONG64) != 0)
17028 if (mips_abi == ABI_N32)
17029 error ("%qs is incompatible with %qs", "-mabi=n32", "-mlong64");
17030 else if (mips_abi == ABI_32)
17031 error ("%qs is incompatible with %qs", "-mabi=32", "-mlong64");
17032 else if (mips_abi == ABI_O64 && TARGET_ABICALLS)
17033 /* We have traditionally allowed non-abicalls code to use
17034 an LP64 form of o64. However, it would take a bit more
17035 effort to support the combination of 32-bit GOT entries
17036 and 64-bit pointers, so we treat the abicalls case as
17038 error ("the combination of %qs and %qs is incompatible with %qs",
17039 "-mabi=o64", "-mabicalls", "-mlong64");
17043 if (mips_abi == ABI_64)
17044 error ("%qs is incompatible with %qs", "-mabi=64", "-mlong32");
17049 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
17050 target_flags |= MASK_LONG64;
17052 target_flags &= ~MASK_LONG64;
17055 if (!TARGET_OLDABI)
17056 flag_pcc_struct_return = 0;
17058 /* Decide which rtx_costs structure to use. */
17060 mips_cost = &mips_rtx_cost_optimize_size;
17062 mips_cost = &mips_rtx_cost_data[mips_tune];
17064 /* If the user hasn't specified a branch cost, use the processor's
17066 if (mips_branch_cost == 0)
17067 mips_branch_cost = mips_cost->branch_cost;
17069 /* If neither -mbranch-likely nor -mno-branch-likely was given
17070 on the command line, set MASK_BRANCHLIKELY based on the target
17071 architecture and tuning flags. Annulled delay slots are a
17072 size win, so we only consider the processor-specific tuning
17073 for !optimize_size. */
17074 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
17076 if (ISA_HAS_BRANCHLIKELY
17078 || (mips_tune_info->tune_flags & PTF_AVOID_BRANCHLIKELY) == 0))
17079 target_flags |= MASK_BRANCHLIKELY;
17081 target_flags &= ~MASK_BRANCHLIKELY;
17083 else if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
17084 warning (0, "the %qs architecture does not support branch-likely"
17085 " instructions", mips_arch_info->name);
17087 /* If the user hasn't specified -mimadd or -mno-imadd set
17088 MASK_IMADD based on the target architecture and tuning
17090 if ((target_flags_explicit & MASK_IMADD) == 0)
17092 if (ISA_HAS_MADD_MSUB &&
17093 (mips_tune_info->tune_flags & PTF_AVOID_IMADD) == 0)
17094 target_flags |= MASK_IMADD;
17096 target_flags &= ~MASK_IMADD;
17098 else if (TARGET_IMADD && !ISA_HAS_MADD_MSUB)
17099 warning (0, "the %qs architecture does not support madd or msub"
17100 " instructions", mips_arch_info->name);
17102 /* The effect of -mabicalls isn't defined for the EABI. */
17103 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
17105 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
17106 target_flags &= ~MASK_ABICALLS;
17109 /* PIC requires -mabicalls. */
17112 if (mips_abi == ABI_EABI)
17113 error ("cannot generate position-independent code for %qs",
17115 else if (!TARGET_ABICALLS)
17116 error ("position-independent code requires %qs", "-mabicalls");
17119 if (TARGET_ABICALLS_PIC2)
17120 /* We need to set flag_pic for executables as well as DSOs
17121 because we may reference symbols that are not defined in
17122 the final executable. (MIPS does not use things like
17123 copy relocs, for example.)
17125 There is a body of code that uses __PIC__ to distinguish
17126 between -mabicalls and -mno-abicalls code. The non-__PIC__
17127 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
17128 long as any indirect jumps use $25. */
17131 /* -mvr4130-align is a "speed over size" optimization: it usually produces
17132 faster code, but at the expense of more nops. Enable it at -O3 and
17134 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
17135 target_flags |= MASK_VR4130_ALIGN;
17137 /* Prefer a call to memcpy over inline code when optimizing for size,
17138 though see MOVE_RATIO in mips.h. */
17139 if (optimize_size && (target_flags_explicit & MASK_MEMCPY) == 0)
17140 target_flags |= MASK_MEMCPY;
17142 /* If we have a nonzero small-data limit, check that the -mgpopt
17143 setting is consistent with the other target flags. */
17144 if (mips_small_data_threshold > 0)
17148 if (!TARGET_EXPLICIT_RELOCS)
17149 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
17151 TARGET_LOCAL_SDATA = false;
17152 TARGET_EXTERN_SDATA = false;
17156 if (TARGET_VXWORKS_RTP)
17157 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
17159 if (TARGET_ABICALLS)
17160 warning (0, "cannot use small-data accesses for %qs",
17165 /* Pre-IEEE 754-2008 MIPS hardware has a quirky almost-IEEE format
17166 for all its floating point. */
17167 if (mips_nan != MIPS_IEEE_754_2008)
17169 REAL_MODE_FORMAT (SFmode) = &mips_single_format;
17170 REAL_MODE_FORMAT (DFmode) = &mips_double_format;
17171 REAL_MODE_FORMAT (TFmode) = &mips_quad_format;
17174 /* Make sure that the user didn't turn off paired single support when
17175 MIPS-3D support is requested. */
17177 && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
17178 && !TARGET_PAIRED_SINGLE_FLOAT)
17179 error ("%<-mips3d%> requires %<-mpaired-single%>");
17181 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
17183 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
17185 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
17186 and TARGET_HARD_FLOAT_ABI are both true. */
17187 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT_ABI))
17189 error ("%qs must be used with %qs",
17190 TARGET_MIPS3D ? "-mips3d" : "-mpaired-single",
17191 TARGET_HARD_FLOAT_ABI ? "-mfp64" : "-mhard-float");
17192 target_flags &= ~MASK_PAIRED_SINGLE_FLOAT;
17196 /* Make sure that -mpaired-single is only used on ISAs that support it.
17197 We must disable it otherwise since it relies on other ISA properties
17198 like ISA_HAS_8CC having their normal values. */
17199 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_HAS_PAIRED_SINGLE)
17201 error ("the %qs architecture does not support paired-single"
17202 " instructions", mips_arch_info->name);
17203 target_flags &= ~MASK_PAIRED_SINGLE_FLOAT;
17207 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
17208 && !TARGET_CACHE_BUILTIN)
17210 error ("%qs requires a target that provides the %qs instruction",
17211 "-mr10k-cache-barrier", "cache");
17212 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE;
17215 /* If TARGET_DSPR2, enable TARGET_DSP. */
17219 /* .eh_frame addresses should be the same width as a C pointer.
17220 Most MIPS ABIs support only one pointer size, so the assembler
17221 will usually know exactly how big an .eh_frame address is.
17223 Unfortunately, this is not true of the 64-bit EABI. The ABI was
17224 originally defined to use 64-bit pointers (i.e. it is LP64), and
17225 this is still the default mode. However, we also support an n32-like
17226 ILP32 mode, which is selected by -mlong32. The problem is that the
17227 assembler has traditionally not had an -mlong option, so it has
17228 traditionally not known whether we're using the ILP32 or LP64 form.
17230 As it happens, gas versions up to and including 2.19 use _32-bit_
17231 addresses for EABI64 .cfi_* directives. This is wrong for the
17232 default LP64 mode, so we can't use the directives by default.
17233 Moreover, since gas's current behavior is at odds with gcc's
17234 default behavior, it seems unwise to rely on future versions
17235 of gas behaving the same way. We therefore avoid using .cfi
17236 directives for -mlong32 as well. */
17237 if (mips_abi == ABI_EABI && TARGET_64BIT)
17238 flag_dwarf2_cfi_asm = 0;
17240 /* .cfi_* directives generate a read-only section, so fall back on
17241 manual .eh_frame creation if we need the section to be writable. */
17242 if (TARGET_WRITABLE_EH_FRAME)
17243 flag_dwarf2_cfi_asm = 0;
17245 mips_init_print_operand_punct ();
17247 /* Set up array to map GCC register number to debug register number.
17248 Ignore the special purpose register numbers. */
17250 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
17252 mips_dbx_regno[i] = IGNORED_DWARF_REGNUM;
17253 if (GP_REG_P (i) || FP_REG_P (i) || ALL_COP_REG_P (i))
17254 mips_dwarf_regno[i] = i;
17256 mips_dwarf_regno[i] = INVALID_REGNUM;
17259 start = GP_DBX_FIRST - GP_REG_FIRST;
17260 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
17261 mips_dbx_regno[i] = i + start;
17263 start = FP_DBX_FIRST - FP_REG_FIRST;
17264 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
17265 mips_dbx_regno[i] = i + start;
17267 /* Accumulator debug registers use big-endian ordering. */
17268 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
17269 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
17270 mips_dwarf_regno[HI_REGNUM] = MD_REG_FIRST + 0;
17271 mips_dwarf_regno[LO_REGNUM] = MD_REG_FIRST + 1;
17272 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
17274 mips_dwarf_regno[i + TARGET_LITTLE_ENDIAN] = i;
17275 mips_dwarf_regno[i + TARGET_BIG_ENDIAN] = i + 1;
17278 /* Set up mips_hard_regno_mode_ok. */
17279 for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
17280 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
17281 mips_hard_regno_mode_ok[mode][regno]
17282 = mips_hard_regno_mode_ok_p (regno, (enum machine_mode) mode);
17284 /* Function to allocate machine-dependent function status. */
17285 init_machine_status = &mips_init_machine_status;
17287 /* Default to working around R4000 errata only if the processor
17288 was selected explicitly. */
17289 if ((target_flags_explicit & MASK_FIX_R4000) == 0
17290 && strcmp (mips_arch_info->name, "r4000") == 0)
17291 target_flags |= MASK_FIX_R4000;
17293 /* Default to working around R4400 errata only if the processor
17294 was selected explicitly. */
17295 if ((target_flags_explicit & MASK_FIX_R4400) == 0
17296 && strcmp (mips_arch_info->name, "r4400") == 0)
17297 target_flags |= MASK_FIX_R4400;
17299 /* Default to working around R10000 errata only if the processor
17300 was selected explicitly. */
17301 if ((target_flags_explicit & MASK_FIX_R10000) == 0
17302 && strcmp (mips_arch_info->name, "r10000") == 0)
17303 target_flags |= MASK_FIX_R10000;
17305 /* Make sure that branch-likely instructions available when using
17306 -mfix-r10000. The instructions are not available if either:
17308 1. -mno-branch-likely was passed.
17309 2. The selected ISA does not support branch-likely and
17310 the command line does not include -mbranch-likely. */
17311 if (TARGET_FIX_R10000
17312 && ((target_flags_explicit & MASK_BRANCHLIKELY) == 0
17313 ? !ISA_HAS_BRANCHLIKELY
17314 : !TARGET_BRANCHLIKELY))
17315 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
17317 if (TARGET_SYNCI && !ISA_HAS_SYNCI)
17319 warning (0, "the %qs architecture does not support the synci "
17320 "instruction", mips_arch_info->name);
17321 target_flags &= ~MASK_SYNCI;
17324 /* Only optimize PIC indirect calls if they are actually required. */
17325 if (!TARGET_USE_GOT || !TARGET_EXPLICIT_RELOCS)
17326 target_flags &= ~MASK_RELAX_PIC_CALLS;
17328 /* Save base state of options. */
17329 mips_base_target_flags = target_flags;
17330 mips_base_schedule_insns = flag_schedule_insns;
17331 mips_base_reorder_blocks_and_partition = flag_reorder_blocks_and_partition;
17332 mips_base_move_loop_invariants = flag_move_loop_invariants;
17333 mips_base_align_loops = align_loops;
17334 mips_base_align_jumps = align_jumps;
17335 mips_base_align_functions = align_functions;
17337 /* Now select the ISA mode.
17339 Do all CPP-sensitive stuff in uncompressed mode; we'll switch modes
17340 later if required. */
17341 mips_set_compression_mode (0);
17343 /* We register a second machine specific reorg pass after delay slot
17344 filling. Registering the pass must be done at start up. It's
17345 convenient to do it here. */
17346 opt_pass *new_pass = make_pass_mips_machine_reorg2 (g);
17347 struct register_pass_info insert_pass_mips_machine_reorg2 =
17349 new_pass, /* pass */
17350 "dbr", /* reference_pass_name */
17351 1, /* ref_pass_instance_number */
17352 PASS_POS_INSERT_AFTER /* po_op */
17354 register_pass (&insert_pass_mips_machine_reorg2);
17356 if (TARGET_HARD_FLOAT_ABI && TARGET_MIPS5900)
17357 REAL_MODE_FORMAT (SFmode) = &spu_single_format;
17360 /* Swap the register information for registers I and I + 1, which
17361 currently have the wrong endianness. Note that the registers'
17362 fixedness and call-clobberedness might have been set on the
17366 mips_swap_registers (unsigned int i)
17371 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
17372 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
17374 SWAP_INT (fixed_regs[i], fixed_regs[i + 1]);
17375 SWAP_INT (call_used_regs[i], call_used_regs[i + 1]);
17376 SWAP_INT (call_really_used_regs[i], call_really_used_regs[i + 1]);
17377 SWAP_STRING (reg_names[i], reg_names[i + 1]);
17383 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
17386 mips_conditional_register_usage (void)
17391 /* These DSP control register fields are global. */
17392 global_regs[CCDSP_PO_REGNUM] = 1;
17393 global_regs[CCDSP_SC_REGNUM] = 1;
17396 AND_COMPL_HARD_REG_SET (accessible_reg_set,
17397 reg_class_contents[(int) DSP_ACC_REGS]);
17399 if (!TARGET_HARD_FLOAT)
17401 AND_COMPL_HARD_REG_SET (accessible_reg_set,
17402 reg_class_contents[(int) FP_REGS]);
17403 AND_COMPL_HARD_REG_SET (accessible_reg_set,
17404 reg_class_contents[(int) ST_REGS]);
17406 else if (!ISA_HAS_8CC)
17408 /* We only have a single condition-code register. We implement
17409 this by fixing all the condition-code registers and generating
17410 RTL that refers directly to ST_REG_FIRST. */
17411 AND_COMPL_HARD_REG_SET (accessible_reg_set,
17412 reg_class_contents[(int) ST_REGS]);
17413 SET_HARD_REG_BIT (accessible_reg_set, FPSW_REGNUM);
17414 fixed_regs[FPSW_REGNUM] = call_used_regs[FPSW_REGNUM] = 1;
17418 /* In MIPS16 mode, we prohibit the unused $s registers, since they
17419 are call-saved, and saving them via a MIPS16 register would
17420 probably waste more time than just reloading the value.
17422 We permit the $t temporary registers when optimizing for speed
17423 but not when optimizing for space because using them results in
17424 code that is larger (but faster) then not using them. We do
17425 allow $24 (t8) because it is used in CMP and CMPI instructions
17426 and $25 (t9) because it is used as the function call address in
17429 fixed_regs[18] = call_used_regs[18] = 1;
17430 fixed_regs[19] = call_used_regs[19] = 1;
17431 fixed_regs[20] = call_used_regs[20] = 1;
17432 fixed_regs[21] = call_used_regs[21] = 1;
17433 fixed_regs[22] = call_used_regs[22] = 1;
17434 fixed_regs[23] = call_used_regs[23] = 1;
17435 fixed_regs[26] = call_used_regs[26] = 1;
17436 fixed_regs[27] = call_used_regs[27] = 1;
17437 fixed_regs[30] = call_used_regs[30] = 1;
17440 fixed_regs[8] = call_used_regs[8] = 1;
17441 fixed_regs[9] = call_used_regs[9] = 1;
17442 fixed_regs[10] = call_used_regs[10] = 1;
17443 fixed_regs[11] = call_used_regs[11] = 1;
17444 fixed_regs[12] = call_used_regs[12] = 1;
17445 fixed_regs[13] = call_used_regs[13] = 1;
17446 fixed_regs[14] = call_used_regs[14] = 1;
17447 fixed_regs[15] = call_used_regs[15] = 1;
17450 /* Do not allow HI and LO to be treated as register operands.
17451 There are no MTHI or MTLO instructions (or any real need
17452 for them) and one-way registers cannot easily be reloaded. */
17453 AND_COMPL_HARD_REG_SET (operand_reg_set,
17454 reg_class_contents[(int) MD_REGS]);
17456 /* $f20-$f23 are call-clobbered for n64. */
17457 if (mips_abi == ABI_64)
17460 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
17461 call_really_used_regs[regno] = call_used_regs[regno] = 1;
17463 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
17465 if (mips_abi == ABI_N32)
17468 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
17469 call_really_used_regs[regno] = call_used_regs[regno] = 1;
17471 /* Make sure that double-register accumulator values are correctly
17472 ordered for the current endianness. */
17473 if (TARGET_LITTLE_ENDIAN)
17475 unsigned int regno;
17477 mips_swap_registers (MD_REG_FIRST);
17478 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno += 2)
17479 mips_swap_registers (regno);
17483 /* Implement EH_USES. */
17486 mips_eh_uses (unsigned int regno)
17488 if (reload_completed && !TARGET_ABSOLUTE_JUMPS)
17490 /* We need to force certain registers to be live in order to handle
17491 PIC long branches correctly. See mips_must_initialize_gp_p for
17493 if (mips_cfun_has_cprestore_slot_p ())
17495 if (regno == CPRESTORE_SLOT_REGNUM)
17500 if (cfun->machine->global_pointer == regno)
17508 /* Implement EPILOGUE_USES. */
17511 mips_epilogue_uses (unsigned int regno)
17513 /* Say that the epilogue uses the return address register. Note that
17514 in the case of sibcalls, the values "used by the epilogue" are
17515 considered live at the start of the called function. */
17516 if (regno == RETURN_ADDR_REGNUM)
17519 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
17520 See the comment above load_call<mode> for details. */
17521 if (TARGET_USE_GOT && (regno) == GOT_VERSION_REGNUM)
17524 /* An interrupt handler must preserve some registers that are
17525 ordinarily call-clobbered. */
17526 if (cfun->machine->interrupt_handler_p
17527 && mips_interrupt_extra_call_saved_reg_p (regno))
17533 /* A for_each_rtx callback. Stop the search if *X is an AT register. */
17536 mips_at_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
17538 return REG_P (*x) && REGNO (*x) == AT_REGNUM;
17541 /* Return true if INSN needs to be wrapped in ".set noat".
17542 INSN has NOPERANDS operands, stored in OPVEC. */
17545 mips_need_noat_wrapper_p (rtx_insn *insn, rtx *opvec, int noperands)
17549 if (recog_memoized (insn) >= 0)
17550 for (i = 0; i < noperands; i++)
17551 if (for_each_rtx (&opvec[i], mips_at_reg_p, NULL))
17556 /* Implement FINAL_PRESCAN_INSN. */
17559 mips_final_prescan_insn (rtx_insn *insn, rtx *opvec, int noperands)
17561 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
17562 mips_push_asm_switch (&mips_noat);
17565 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */
17568 mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED, rtx_insn *insn,
17569 rtx *opvec, int noperands)
17571 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
17572 mips_pop_asm_switch (&mips_noat);
17575 /* Return the function that is used to expand the <u>mulsidi3 pattern.
17576 EXT_CODE is the code of the extension used. Return NULL if widening
17577 multiplication shouldn't be used. */
17580 mips_mulsidi3_gen_fn (enum rtx_code ext_code)
17584 signed_p = ext_code == SIGN_EXTEND;
17587 /* Don't use widening multiplication with MULT when we have DMUL. Even
17588 with the extension of its input operands DMUL is faster. Note that
17589 the extension is not needed for signed multiplication. In order to
17590 ensure that we always remove the redundant sign-extension in this
17591 case we still expand mulsidi3 for DMUL. */
17593 return signed_p ? gen_mulsidi3_64bit_dmul : NULL;
17596 ? gen_mulsidi3_64bit_mips16
17597 : gen_umulsidi3_64bit_mips16);
17598 if (TARGET_FIX_R4000)
17600 return signed_p ? gen_mulsidi3_64bit : gen_umulsidi3_64bit;
17606 ? gen_mulsidi3_32bit_mips16
17607 : gen_umulsidi3_32bit_mips16);
17608 if (TARGET_FIX_R4000 && !ISA_HAS_DSP)
17609 return signed_p ? gen_mulsidi3_32bit_r4000 : gen_umulsidi3_32bit_r4000;
17610 return signed_p ? gen_mulsidi3_32bit : gen_umulsidi3_32bit;
17614 /* Return true if PATTERN matches the kind of instruction generated by
17615 umips_build_save_restore. SAVE_P is true for store. */
17618 umips_save_restore_pattern_p (bool save_p, rtx pattern)
17622 HOST_WIDE_INT first_offset = 0;
17623 rtx first_base = 0;
17624 unsigned int regmask = 0;
17626 for (n = 0; n < XVECLEN (pattern, 0); n++)
17628 rtx set, reg, mem, this_base;
17629 HOST_WIDE_INT this_offset;
17631 /* Check that we have a SET. */
17632 set = XVECEXP (pattern, 0, n);
17633 if (GET_CODE (set) != SET)
17636 /* Check that the SET is a load (if restoring) or a store
17638 mem = save_p ? SET_DEST (set) : SET_SRC (set);
17639 if (!MEM_P (mem) || MEM_VOLATILE_P (mem))
17642 /* Check that the address is the sum of base and a possibly-zero
17643 constant offset. Determine if the offset is in range. */
17644 mips_split_plus (XEXP (mem, 0), &this_base, &this_offset);
17645 if (!REG_P (this_base))
17650 if (!UMIPS_12BIT_OFFSET_P (this_offset))
17652 first_base = this_base;
17653 first_offset = this_offset;
17657 /* Check that the save slots are consecutive. */
17658 if (REGNO (this_base) != REGNO (first_base)
17659 || this_offset != first_offset + UNITS_PER_WORD * n)
17663 /* Check that SET's other operand is a register. */
17664 reg = save_p ? SET_SRC (set) : SET_DEST (set);
17668 regmask |= 1 << REGNO (reg);
17671 for (i = 0; i < ARRAY_SIZE (umips_swm_mask); i++)
17672 if (regmask == umips_swm_mask[i])
17678 /* Return the assembly instruction for microMIPS LWM or SWM.
17679 SAVE_P and PATTERN are as for umips_save_restore_pattern_p. */
17682 umips_output_save_restore (bool save_p, rtx pattern)
17684 static char buffer[300];
17687 HOST_WIDE_INT offset;
17688 rtx base, mem, set, last_set, last_reg;
17690 /* Parse the pattern. */
17691 gcc_assert (umips_save_restore_pattern_p (save_p, pattern));
17693 s = strcpy (buffer, save_p ? "swm\t" : "lwm\t");
17695 n = XVECLEN (pattern, 0);
17697 set = XVECEXP (pattern, 0, 0);
17698 mem = save_p ? SET_DEST (set) : SET_SRC (set);
17699 mips_split_plus (XEXP (mem, 0), &base, &offset);
17701 last_set = XVECEXP (pattern, 0, n - 1);
17702 last_reg = save_p ? SET_SRC (last_set) : SET_DEST (last_set);
17704 if (REGNO (last_reg) == 31)
17707 gcc_assert (n <= 9);
17711 s += sprintf (s, "%s,", reg_names[16]);
17713 s += sprintf (s, "%s-%s,", reg_names[16], reg_names[15 + n]);
17715 s += sprintf (s, "%s-%s,%s,", reg_names[16], reg_names[23],
17718 if (REGNO (last_reg) == 31)
17719 s += sprintf (s, "%s,", reg_names[31]);
17721 s += sprintf (s, "%d(%s)", (int)offset, reg_names[REGNO (base)]);
17725 /* Return true if MEM1 and MEM2 use the same base register, and the
17726 offset of MEM2 equals the offset of MEM1 plus 4. FIRST_REG is the
17727 register into (from) which the contents of MEM1 will be loaded
17728 (stored), depending on the value of LOAD_P.
17729 SWAP_P is true when the 1st and 2nd instructions are swapped. */
17732 umips_load_store_pair_p_1 (bool load_p, bool swap_p,
17733 rtx first_reg, rtx mem1, rtx mem2)
17736 HOST_WIDE_INT offset1, offset2;
17738 if (!MEM_P (mem1) || !MEM_P (mem2))
17741 mips_split_plus (XEXP (mem1, 0), &base1, &offset1);
17742 mips_split_plus (XEXP (mem2, 0), &base2, &offset2);
17744 if (!REG_P (base1) || !rtx_equal_p (base1, base2))
17747 /* Avoid invalid load pair instructions. */
17748 if (load_p && REGNO (first_reg) == REGNO (base1))
17751 /* We must avoid this case for anti-dependence.
17754 first_reg is $2, but the base is $3. */
17757 && REGNO (first_reg) + 1 == REGNO (base1))
17760 if (offset2 != offset1 + 4)
17763 if (!UMIPS_12BIT_OFFSET_P (offset1))
17769 /* OPERANDS describes the operands to a pair of SETs, in the order
17770 dest1, src1, dest2, src2. Return true if the operands can be used
17771 in an LWP or SWP instruction; LOAD_P says which. */
17774 umips_load_store_pair_p (bool load_p, rtx *operands)
17776 rtx reg1, reg2, mem1, mem2;
17780 reg1 = operands[0];
17781 reg2 = operands[2];
17782 mem1 = operands[1];
17783 mem2 = operands[3];
17787 reg1 = operands[1];
17788 reg2 = operands[3];
17789 mem1 = operands[0];
17790 mem2 = operands[2];
17793 if (REGNO (reg2) == REGNO (reg1) + 1)
17794 return umips_load_store_pair_p_1 (load_p, false, reg1, mem1, mem2);
17796 if (REGNO (reg1) == REGNO (reg2) + 1)
17797 return umips_load_store_pair_p_1 (load_p, true, reg2, mem2, mem1);
17802 /* Return the assembly instruction for a microMIPS LWP or SWP in which
17803 the first register is REG and the first memory slot is MEM.
17804 LOAD_P is true for LWP. */
17807 umips_output_load_store_pair_1 (bool load_p, rtx reg, rtx mem)
17809 rtx ops[] = {reg, mem};
17812 output_asm_insn ("lwp\t%0,%1", ops);
17814 output_asm_insn ("swp\t%0,%1", ops);
17817 /* Output the assembly instruction for a microMIPS LWP or SWP instruction.
17818 LOAD_P and OPERANDS are as for umips_load_store_pair_p. */
17821 umips_output_load_store_pair (bool load_p, rtx *operands)
17823 rtx reg1, reg2, mem1, mem2;
17826 reg1 = operands[0];
17827 reg2 = operands[2];
17828 mem1 = operands[1];
17829 mem2 = operands[3];
17833 reg1 = operands[1];
17834 reg2 = operands[3];
17835 mem1 = operands[0];
17836 mem2 = operands[2];
17839 if (REGNO (reg2) == REGNO (reg1) + 1)
17841 umips_output_load_store_pair_1 (load_p, reg1, mem1);
17845 gcc_assert (REGNO (reg1) == REGNO (reg2) + 1);
17846 umips_output_load_store_pair_1 (load_p, reg2, mem2);
17849 /* Return true if REG1 and REG2 match the criteria for a movep insn. */
17852 umips_movep_target_p (rtx reg1, rtx reg2)
17854 int regno1, regno2, pair;
17856 static const int match[8] = {
17857 0x00000060, /* 5, 6 */
17858 0x000000a0, /* 5, 7 */
17859 0x000000c0, /* 6, 7 */
17860 0x00200010, /* 4, 21 */
17861 0x00400010, /* 4, 22 */
17862 0x00000030, /* 4, 5 */
17863 0x00000050, /* 4, 6 */
17864 0x00000090 /* 4, 7 */
17867 if (!REG_P (reg1) || !REG_P (reg2))
17870 regno1 = REGNO (reg1);
17871 regno2 = REGNO (reg2);
17873 if (!GP_REG_P (regno1) || !GP_REG_P (regno2))
17876 pair = (1 << regno1) | (1 << regno2);
17878 for (i = 0; i < ARRAY_SIZE (match); i++)
17879 if (pair == match[i])
17885 /* Return the size in bytes of the trampoline code, padded to
17886 TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target
17887 function address immediately follow. */
17890 mips_trampoline_code_size (void)
17892 if (TARGET_USE_PIC_FN_ADDR_REG)
17894 else if (ptr_mode == DImode)
17896 else if (ISA_HAS_LOAD_DELAY)
17902 /* Implement TARGET_TRAMPOLINE_INIT. */
17905 mips_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
17907 rtx addr, end_addr, high, low, opcode, mem;
17910 HOST_WIDE_INT end_addr_offset, static_chain_offset, target_function_offset;
17912 /* Work out the offsets of the pointers from the start of the
17913 trampoline code. */
17914 end_addr_offset = mips_trampoline_code_size ();
17915 static_chain_offset = end_addr_offset;
17916 target_function_offset = static_chain_offset + GET_MODE_SIZE (ptr_mode);
17918 /* Get pointers to the beginning and end of the code block. */
17919 addr = force_reg (Pmode, XEXP (m_tramp, 0));
17920 end_addr = mips_force_binary (Pmode, PLUS, addr, GEN_INT (end_addr_offset));
17922 #define OP(X) gen_int_mode (X, SImode)
17924 /* Build up the code in TRAMPOLINE. */
17926 if (TARGET_USE_PIC_FN_ADDR_REG)
17928 /* $25 contains the address of the trampoline. Emit code of the form:
17930 l[wd] $1, target_function_offset($25)
17931 l[wd] $static_chain, static_chain_offset($25)
17934 trampoline[i++] = OP (MIPS_LOAD_PTR (AT_REGNUM,
17935 target_function_offset,
17936 PIC_FUNCTION_ADDR_REGNUM));
17937 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
17938 static_chain_offset,
17939 PIC_FUNCTION_ADDR_REGNUM));
17940 trampoline[i++] = OP (MIPS_JR (AT_REGNUM));
17941 trampoline[i++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM, AT_REGNUM));
17943 else if (ptr_mode == DImode)
17945 /* It's too cumbersome to create the full 64-bit address, so let's
17951 1: l[wd] $25, target_function_offset - 12($31)
17952 l[wd] $static_chain, static_chain_offset - 12($31)
17956 where 12 is the offset of "1:" from the start of the code block. */
17957 trampoline[i++] = OP (MIPS_MOVE (AT_REGNUM, RETURN_ADDR_REGNUM));
17958 trampoline[i++] = OP (MIPS_BAL (1));
17959 trampoline[i++] = OP (MIPS_NOP);
17960 trampoline[i++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
17961 target_function_offset - 12,
17962 RETURN_ADDR_REGNUM));
17963 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
17964 static_chain_offset - 12,
17965 RETURN_ADDR_REGNUM));
17966 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
17967 trampoline[i++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM, AT_REGNUM));
17971 /* If the target has load delays, emit:
17973 lui $1, %hi(end_addr)
17974 lw $25, %lo(end_addr + ...)($1)
17975 lw $static_chain, %lo(end_addr + ...)($1)
17981 lui $1, %hi(end_addr)
17982 lw $25, %lo(end_addr + ...)($1)
17984 lw $static_chain, %lo(end_addr + ...)($1). */
17986 /* Split END_ADDR into %hi and %lo values. Trampolines are aligned
17987 to 64 bits, so the %lo value will have the bottom 3 bits clear. */
17988 high = expand_simple_binop (SImode, PLUS, end_addr, GEN_INT (0x8000),
17989 NULL, false, OPTAB_WIDEN);
17990 high = expand_simple_binop (SImode, LSHIFTRT, high, GEN_INT (16),
17991 NULL, false, OPTAB_WIDEN);
17992 low = convert_to_mode (SImode, gen_lowpart (HImode, end_addr), true);
17994 /* Emit the LUI. */
17995 opcode = OP (MIPS_LUI (AT_REGNUM, 0));
17996 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, high,
17997 NULL, false, OPTAB_WIDEN);
17999 /* Emit the load of the target function. */
18000 opcode = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
18001 target_function_offset - end_addr_offset,
18003 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
18004 NULL, false, OPTAB_WIDEN);
18006 /* Emit the JR here, if we can. */
18007 if (!ISA_HAS_LOAD_DELAY)
18008 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
18010 /* Emit the load of the static chain register. */
18011 opcode = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
18012 static_chain_offset - end_addr_offset,
18014 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
18015 NULL, false, OPTAB_WIDEN);
18017 /* Emit the JR, if we couldn't above. */
18018 if (ISA_HAS_LOAD_DELAY)
18020 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
18021 trampoline[i++] = OP (MIPS_NOP);
18027 /* Copy the trampoline code. Leave any padding uninitialized. */
18028 for (j = 0; j < i; j++)
18030 mem = adjust_address (m_tramp, SImode, j * GET_MODE_SIZE (SImode));
18031 mips_emit_move (mem, trampoline[j]);
18034 /* Set up the static chain pointer field. */
18035 mem = adjust_address (m_tramp, ptr_mode, static_chain_offset);
18036 mips_emit_move (mem, chain_value);
18038 /* Set up the target function field. */
18039 mem = adjust_address (m_tramp, ptr_mode, target_function_offset);
18040 mips_emit_move (mem, XEXP (DECL_RTL (fndecl), 0));
18042 /* Flush the code part of the trampoline. */
18043 emit_insn (gen_add3_insn (end_addr, addr, GEN_INT (TRAMPOLINE_SIZE)));
18044 emit_insn (gen_clear_cache (addr, end_addr));
18047 /* Implement FUNCTION_PROFILER. */
18049 void mips_function_profiler (FILE *file)
18052 sorry ("mips16 function profiling");
18053 if (TARGET_LONG_CALLS)
18055 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */
18056 if (Pmode == DImode)
18057 fprintf (file, "\tdla\t%s,_mcount\n", reg_names[3]);
18059 fprintf (file, "\tla\t%s,_mcount\n", reg_names[3]);
18061 mips_push_asm_switch (&mips_noat);
18062 fprintf (file, "\tmove\t%s,%s\t\t# save current return address\n",
18063 reg_names[AT_REGNUM], reg_names[RETURN_ADDR_REGNUM]);
18064 /* _mcount treats $2 as the static chain register. */
18065 if (cfun->static_chain_decl != NULL)
18066 fprintf (file, "\tmove\t%s,%s\n", reg_names[2],
18067 reg_names[STATIC_CHAIN_REGNUM]);
18068 if (TARGET_MCOUNT_RA_ADDRESS)
18070 /* If TARGET_MCOUNT_RA_ADDRESS load $12 with the address of the
18071 ra save location. */
18072 if (cfun->machine->frame.ra_fp_offset == 0)
18073 /* ra not saved, pass zero. */
18074 fprintf (file, "\tmove\t%s,%s\n", reg_names[12], reg_names[0]);
18076 fprintf (file, "\t%s\t%s," HOST_WIDE_INT_PRINT_DEC "(%s)\n",
18077 Pmode == DImode ? "dla" : "la", reg_names[12],
18078 cfun->machine->frame.ra_fp_offset,
18079 reg_names[STACK_POINTER_REGNUM]);
18081 if (!TARGET_NEWABI)
18083 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n",
18084 TARGET_64BIT ? "dsubu" : "subu",
18085 reg_names[STACK_POINTER_REGNUM],
18086 reg_names[STACK_POINTER_REGNUM],
18087 Pmode == DImode ? 16 : 8);
18089 if (TARGET_LONG_CALLS)
18090 fprintf (file, "\tjalr\t%s\n", reg_names[3]);
18092 fprintf (file, "\tjal\t_mcount\n");
18093 mips_pop_asm_switch (&mips_noat);
18094 /* _mcount treats $2 as the static chain register. */
18095 if (cfun->static_chain_decl != NULL)
18096 fprintf (file, "\tmove\t%s,%s\n", reg_names[STATIC_CHAIN_REGNUM],
18100 /* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default
18101 behaviour of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even
18102 when TARGET_LOONGSON_VECTORS is true. */
18104 static unsigned HOST_WIDE_INT
18105 mips_shift_truncation_mask (enum machine_mode mode)
18107 if (TARGET_LOONGSON_VECTORS && VECTOR_MODE_P (mode))
18110 return GET_MODE_BITSIZE (mode) - 1;
18113 /* Implement TARGET_PREPARE_PCH_SAVE. */
18116 mips_prepare_pch_save (void)
18118 /* We are called in a context where the current MIPS16 vs. non-MIPS16
18119 setting should be irrelevant. The question then is: which setting
18120 makes most sense at load time?
18122 The PCH is loaded before the first token is read. We should never
18123 have switched into MIPS16 mode by that point, and thus should not
18124 have populated mips16_globals. Nor can we load the entire contents
18125 of mips16_globals from the PCH file, because mips16_globals contains
18126 a combination of GGC and non-GGC data.
18128 There is therefore no point in trying save the GGC part of
18129 mips16_globals to the PCH file, or to preserve MIPS16ness across
18130 the PCH save and load. The loading compiler would not have access
18131 to the non-GGC parts of mips16_globals (either from the PCH file,
18132 or from a copy that the loading compiler generated itself) and would
18133 have to call target_reinit anyway.
18135 It therefore seems best to switch back to non-MIPS16 mode at
18136 save time, and to ensure that mips16_globals remains null after
18138 mips_set_compression_mode (0);
18139 mips16_globals = 0;
18142 /* Generate or test for an insn that supports a constant permutation. */
18144 #define MAX_VECT_LEN 8
18146 struct expand_vec_perm_d
18148 rtx target, op0, op1;
18149 unsigned char perm[MAX_VECT_LEN];
18150 enum machine_mode vmode;
18151 unsigned char nelt;
18156 /* Construct (set target (vec_select op0 (parallel perm))) and
18157 return true if that's a valid instruction in the active ISA. */
18160 mips_expand_vselect (rtx target, rtx op0,
18161 const unsigned char *perm, unsigned nelt)
18163 rtx rperm[MAX_VECT_LEN], x;
18167 for (i = 0; i < nelt; ++i)
18168 rperm[i] = GEN_INT (perm[i]);
18170 x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (nelt, rperm));
18171 x = gen_rtx_VEC_SELECT (GET_MODE (target), op0, x);
18172 x = gen_rtx_SET (VOIDmode, target, x);
18174 insn = emit_insn (x);
18175 if (recog_memoized (insn) < 0)
18177 remove_insn (insn);
18183 /* Similar, but generate a vec_concat from op0 and op1 as well. */
18186 mips_expand_vselect_vconcat (rtx target, rtx op0, rtx op1,
18187 const unsigned char *perm, unsigned nelt)
18189 enum machine_mode v2mode;
18192 v2mode = GET_MODE_2XWIDER_MODE (GET_MODE (op0));
18193 x = gen_rtx_VEC_CONCAT (v2mode, op0, op1);
18194 return mips_expand_vselect (target, x, perm, nelt);
18197 /* Recognize patterns for even-odd extraction. */
18200 mips_expand_vpc_loongson_even_odd (struct expand_vec_perm_d *d)
18202 unsigned i, odd, nelt = d->nelt;
18203 rtx t0, t1, t2, t3;
18205 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
18207 /* Even-odd for V2SI/V2SFmode is matched by interleave directly. */
18214 for (i = 1; i < nelt; ++i)
18215 if (d->perm[i] != i * 2 + odd)
18221 /* We need 2*log2(N)-1 operations to achieve odd/even with interleave. */
18222 t0 = gen_reg_rtx (d->vmode);
18223 t1 = gen_reg_rtx (d->vmode);
18227 emit_insn (gen_loongson_punpckhhw (t0, d->op0, d->op1));
18228 emit_insn (gen_loongson_punpcklhw (t1, d->op0, d->op1));
18230 emit_insn (gen_loongson_punpckhhw (d->target, t1, t0));
18232 emit_insn (gen_loongson_punpcklhw (d->target, t1, t0));
18236 t2 = gen_reg_rtx (d->vmode);
18237 t3 = gen_reg_rtx (d->vmode);
18238 emit_insn (gen_loongson_punpckhbh (t0, d->op0, d->op1));
18239 emit_insn (gen_loongson_punpcklbh (t1, d->op0, d->op1));
18240 emit_insn (gen_loongson_punpckhbh (t2, t1, t0));
18241 emit_insn (gen_loongson_punpcklbh (t3, t1, t0));
18243 emit_insn (gen_loongson_punpckhbh (d->target, t3, t2));
18245 emit_insn (gen_loongson_punpcklbh (d->target, t3, t2));
18249 gcc_unreachable ();
18254 /* Recognize patterns for the Loongson PSHUFH instruction. */
18257 mips_expand_vpc_loongson_pshufh (struct expand_vec_perm_d *d)
18262 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
18264 if (d->vmode != V4HImode)
18269 /* Convert the selector into the packed 8-bit form for pshufh. */
18270 /* Recall that loongson is little-endian only. No big-endian
18271 adjustment required. */
18272 for (i = mask = 0; i < 4; i++)
18273 mask |= (d->perm[i] & 3) << (i * 2);
18274 rmask = force_reg (SImode, GEN_INT (mask));
18276 if (d->one_vector_p)
18277 emit_insn (gen_loongson_pshufh (d->target, d->op0, rmask));
18280 rtx t0, t1, x, merge, rmerge[4];
18282 t0 = gen_reg_rtx (V4HImode);
18283 t1 = gen_reg_rtx (V4HImode);
18284 emit_insn (gen_loongson_pshufh (t1, d->op1, rmask));
18285 emit_insn (gen_loongson_pshufh (t0, d->op0, rmask));
18287 for (i = 0; i < 4; ++i)
18288 rmerge[i] = (d->perm[i] & 4 ? constm1_rtx : const0_rtx);
18289 merge = gen_rtx_CONST_VECTOR (V4HImode, gen_rtvec_v (4, rmerge));
18290 merge = force_reg (V4HImode, merge);
18292 x = gen_rtx_AND (V4HImode, merge, t1);
18293 emit_insn (gen_rtx_SET (VOIDmode, t1, x));
18295 x = gen_rtx_NOT (V4HImode, merge);
18296 x = gen_rtx_AND (V4HImode, x, t0);
18297 emit_insn (gen_rtx_SET (VOIDmode, t0, x));
18299 x = gen_rtx_IOR (V4HImode, t0, t1);
18300 emit_insn (gen_rtx_SET (VOIDmode, d->target, x));
18306 /* Recognize broadcast patterns for the Loongson. */
18309 mips_expand_vpc_loongson_bcast (struct expand_vec_perm_d *d)
18314 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
18316 /* Note that we've already matched V2SI via punpck and V4HI via pshufh. */
18317 if (d->vmode != V8QImode)
18319 if (!d->one_vector_p)
18323 for (i = 1; i < 8; ++i)
18324 if (d->perm[i] != elt)
18330 /* With one interleave we put two of the desired element adjacent. */
18331 t0 = gen_reg_rtx (V8QImode);
18333 emit_insn (gen_loongson_punpcklbh (t0, d->op0, d->op0));
18335 emit_insn (gen_loongson_punpckhbh (t0, d->op0, d->op0));
18337 /* Shuffle that one HImode element into all locations. */
18340 t1 = gen_reg_rtx (V4HImode);
18341 emit_insn (gen_loongson_pshufh (t1, gen_lowpart (V4HImode, t0),
18342 force_reg (SImode, GEN_INT (elt))));
18344 emit_move_insn (d->target, gen_lowpart (V8QImode, t1));
18349 mips_expand_vec_perm_const_1 (struct expand_vec_perm_d *d)
18351 unsigned int i, nelt = d->nelt;
18352 unsigned char perm2[MAX_VECT_LEN];
18354 if (d->one_vector_p)
18356 /* Try interleave with alternating operands. */
18357 memcpy (perm2, d->perm, sizeof(perm2));
18358 for (i = 1; i < nelt; i += 2)
18360 if (mips_expand_vselect_vconcat (d->target, d->op0, d->op1, perm2, nelt))
18365 if (mips_expand_vselect_vconcat (d->target, d->op0, d->op1,
18369 /* Try again with swapped operands. */
18370 for (i = 0; i < nelt; ++i)
18371 perm2[i] = (d->perm[i] + nelt) & (2 * nelt - 1);
18372 if (mips_expand_vselect_vconcat (d->target, d->op1, d->op0, perm2, nelt))
18376 if (mips_expand_vpc_loongson_even_odd (d))
18378 if (mips_expand_vpc_loongson_pshufh (d))
18380 if (mips_expand_vpc_loongson_bcast (d))
18385 /* Expand a vec_perm_const pattern. */
18388 mips_expand_vec_perm_const (rtx operands[4])
18390 struct expand_vec_perm_d d;
18391 int i, nelt, which;
18392 unsigned char orig_perm[MAX_VECT_LEN];
18396 d.target = operands[0];
18397 d.op0 = operands[1];
18398 d.op1 = operands[2];
18401 d.vmode = GET_MODE (d.target);
18402 gcc_assert (VECTOR_MODE_P (d.vmode));
18403 d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
18404 d.testing_p = false;
18406 for (i = which = 0; i < nelt; ++i)
18408 rtx e = XVECEXP (sel, 0, i);
18409 int ei = INTVAL (e) & (2 * nelt - 1);
18410 which |= (ei < nelt ? 1 : 2);
18413 memcpy (d.perm, orig_perm, MAX_VECT_LEN);
18421 d.one_vector_p = false;
18422 if (!rtx_equal_p (d.op0, d.op1))
18427 for (i = 0; i < nelt; ++i)
18428 d.perm[i] &= nelt - 1;
18430 d.one_vector_p = true;
18435 d.one_vector_p = true;
18439 ok = mips_expand_vec_perm_const_1 (&d);
18441 /* If we were given a two-vector permutation which just happened to
18442 have both input vectors equal, we folded this into a one-vector
18443 permutation. There are several loongson patterns that are matched
18444 via direct vec_select+vec_concat expansion, but we do not have
18445 support in mips_expand_vec_perm_const_1 to guess the adjustment
18446 that should be made for a single operand. Just try again with
18447 the original permutation. */
18448 if (!ok && which == 3)
18450 d.op0 = operands[1];
18451 d.op1 = operands[2];
18452 d.one_vector_p = false;
18453 memcpy (d.perm, orig_perm, MAX_VECT_LEN);
18454 ok = mips_expand_vec_perm_const_1 (&d);
18460 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST_OK. */
18463 mips_vectorize_vec_perm_const_ok (enum machine_mode vmode,
18464 const unsigned char *sel)
18466 struct expand_vec_perm_d d;
18467 unsigned int i, nelt, which;
18471 d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
18472 d.testing_p = true;
18473 memcpy (d.perm, sel, nelt);
18475 /* Categorize the set of elements in the selector. */
18476 for (i = which = 0; i < nelt; ++i)
18478 unsigned char e = d.perm[i];
18479 gcc_assert (e < 2 * nelt);
18480 which |= (e < nelt ? 1 : 2);
18483 /* For all elements from second vector, fold the elements to first. */
18485 for (i = 0; i < nelt; ++i)
18488 /* Check whether the mask can be applied to the vector type. */
18489 d.one_vector_p = (which != 3);
18491 d.target = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 1);
18492 d.op1 = d.op0 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 2);
18493 if (!d.one_vector_p)
18494 d.op1 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 3);
18497 ret = mips_expand_vec_perm_const_1 (&d);
18503 /* Expand an integral vector unpack operation. */
18506 mips_expand_vec_unpack (rtx operands[2], bool unsigned_p, bool high_p)
18508 enum machine_mode imode = GET_MODE (operands[1]);
18509 rtx (*unpack) (rtx, rtx, rtx);
18510 rtx (*cmpgt) (rtx, rtx, rtx);
18511 rtx tmp, dest, zero;
18517 unpack = gen_loongson_punpckhbh;
18519 unpack = gen_loongson_punpcklbh;
18520 cmpgt = gen_loongson_pcmpgtb;
18524 unpack = gen_loongson_punpckhhw;
18526 unpack = gen_loongson_punpcklhw;
18527 cmpgt = gen_loongson_pcmpgth;
18530 gcc_unreachable ();
18533 zero = force_reg (imode, CONST0_RTX (imode));
18538 tmp = gen_reg_rtx (imode);
18539 emit_insn (cmpgt (tmp, zero, operands[1]));
18542 dest = gen_reg_rtx (imode);
18543 emit_insn (unpack (dest, operands[1], tmp));
18545 emit_move_insn (operands[0], gen_lowpart (GET_MODE (operands[0]), dest));
18548 /* A subroutine of mips_expand_vec_init, match constant vector elements. */
18551 mips_constant_elt_p (rtx x)
18553 return CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE;
18556 /* A subroutine of mips_expand_vec_init, expand via broadcast. */
18559 mips_expand_vi_broadcast (enum machine_mode vmode, rtx target, rtx elt)
18561 struct expand_vec_perm_d d;
18565 if (elt != const0_rtx)
18566 elt = force_reg (GET_MODE_INNER (vmode), elt);
18568 elt = gen_lowpart (DImode, elt);
18570 t1 = gen_reg_rtx (vmode);
18574 emit_insn (gen_loongson_vec_init1_v8qi (t1, elt));
18577 emit_insn (gen_loongson_vec_init1_v4hi (t1, elt));
18580 gcc_unreachable ();
18583 memset (&d, 0, sizeof (d));
18588 d.nelt = GET_MODE_NUNITS (vmode);
18589 d.one_vector_p = true;
18591 ok = mips_expand_vec_perm_const_1 (&d);
18595 /* A subroutine of mips_expand_vec_init, replacing all of the non-constant
18596 elements of VALS with zeros, copy the constant vector to TARGET. */
18599 mips_expand_vi_constant (enum machine_mode vmode, unsigned nelt,
18600 rtx target, rtx vals)
18602 rtvec vec = shallow_copy_rtvec (XVEC (vals, 0));
18605 for (i = 0; i < nelt; ++i)
18607 if (!mips_constant_elt_p (RTVEC_ELT (vec, i)))
18608 RTVEC_ELT (vec, i) = const0_rtx;
18611 emit_move_insn (target, gen_rtx_CONST_VECTOR (vmode, vec));
18615 /* A subroutine of mips_expand_vec_init, expand via pinsrh. */
18618 mips_expand_vi_loongson_one_pinsrh (rtx target, rtx vals, unsigned one_var)
18620 mips_expand_vi_constant (V4HImode, 4, target, vals);
18622 emit_insn (gen_vec_setv4hi (target, target, XVECEXP (vals, 0, one_var),
18623 GEN_INT (one_var)));
18626 /* A subroutine of mips_expand_vec_init, expand anything via memory. */
18629 mips_expand_vi_general (enum machine_mode vmode, enum machine_mode imode,
18630 unsigned nelt, unsigned nvar, rtx target, rtx vals)
18632 rtx mem = assign_stack_temp (vmode, GET_MODE_SIZE (vmode));
18633 unsigned int i, isize = GET_MODE_SIZE (imode);
18636 mips_expand_vi_constant (vmode, nelt, mem, vals);
18638 for (i = 0; i < nelt; ++i)
18640 rtx x = XVECEXP (vals, 0, i);
18641 if (!mips_constant_elt_p (x))
18642 emit_move_insn (adjust_address (mem, imode, i * isize), x);
18645 emit_move_insn (target, mem);
18648 /* Expand a vector initialization. */
18651 mips_expand_vector_init (rtx target, rtx vals)
18653 enum machine_mode vmode = GET_MODE (target);
18654 enum machine_mode imode = GET_MODE_INNER (vmode);
18655 unsigned i, nelt = GET_MODE_NUNITS (vmode);
18656 unsigned nvar = 0, one_var = -1u;
18657 bool all_same = true;
18660 for (i = 0; i < nelt; ++i)
18662 x = XVECEXP (vals, 0, i);
18663 if (!mips_constant_elt_p (x))
18664 nvar++, one_var = i;
18665 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
18669 /* Load constants from the pool, or whatever's handy. */
18672 emit_move_insn (target, gen_rtx_CONST_VECTOR (vmode, XVEC (vals, 0)));
18676 /* For two-part initialization, always use CONCAT. */
18679 rtx op0 = force_reg (imode, XVECEXP (vals, 0, 0));
18680 rtx op1 = force_reg (imode, XVECEXP (vals, 0, 1));
18681 x = gen_rtx_VEC_CONCAT (vmode, op0, op1);
18682 emit_insn (gen_rtx_SET (VOIDmode, target, x));
18686 /* Loongson is the only cpu with vectors with more elements. */
18687 gcc_assert (TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS);
18689 /* If all values are identical, broadcast the value. */
18692 mips_expand_vi_broadcast (vmode, target, XVECEXP (vals, 0, 0));
18696 /* If we've only got one non-variable V4HImode, use PINSRH. */
18697 if (nvar == 1 && vmode == V4HImode)
18699 mips_expand_vi_loongson_one_pinsrh (target, vals, one_var);
18703 mips_expand_vi_general (vmode, imode, nelt, nvar, target, vals);
18706 /* Expand a vector reduction. */
18709 mips_expand_vec_reduc (rtx target, rtx in, rtx (*gen)(rtx, rtx, rtx))
18711 enum machine_mode vmode = GET_MODE (in);
18712 unsigned char perm2[2];
18713 rtx last, next, fold, x;
18717 fold = gen_reg_rtx (vmode);
18721 /* Use PUL/PLU to produce { L, H } op { H, L }.
18722 By reversing the pair order, rather than a pure interleave high,
18723 we avoid erroneous exceptional conditions that we might otherwise
18724 produce from the computation of H op H. */
18727 ok = mips_expand_vselect_vconcat (fold, last, last, perm2, 2);
18732 /* Use interleave to produce { H, L } op { H, H }. */
18733 emit_insn (gen_loongson_punpckhwd (fold, last, last));
18737 /* Perform the first reduction with interleave,
18738 and subsequent reductions with shifts. */
18739 emit_insn (gen_loongson_punpckhwd_hi (fold, last, last));
18741 next = gen_reg_rtx (vmode);
18742 emit_insn (gen (next, last, fold));
18745 fold = gen_reg_rtx (vmode);
18746 x = force_reg (SImode, GEN_INT (16));
18747 emit_insn (gen_vec_shr_v4hi (fold, last, x));
18751 emit_insn (gen_loongson_punpckhwd_qi (fold, last, last));
18753 next = gen_reg_rtx (vmode);
18754 emit_insn (gen (next, last, fold));
18757 fold = gen_reg_rtx (vmode);
18758 x = force_reg (SImode, GEN_INT (16));
18759 emit_insn (gen_vec_shr_v8qi (fold, last, x));
18761 next = gen_reg_rtx (vmode);
18762 emit_insn (gen (next, last, fold));
18765 fold = gen_reg_rtx (vmode);
18766 x = force_reg (SImode, GEN_INT (8));
18767 emit_insn (gen_vec_shr_v8qi (fold, last, x));
18771 gcc_unreachable ();
18774 emit_insn (gen (target, last, fold));
18777 /* Expand a vector minimum/maximum. */
18780 mips_expand_vec_minmax (rtx target, rtx op0, rtx op1,
18781 rtx (*cmp) (rtx, rtx, rtx), bool min_p)
18783 enum machine_mode vmode = GET_MODE (target);
18786 tc = gen_reg_rtx (vmode);
18787 t0 = gen_reg_rtx (vmode);
18788 t1 = gen_reg_rtx (vmode);
18791 emit_insn (cmp (tc, op0, op1));
18793 x = gen_rtx_AND (vmode, tc, (min_p ? op1 : op0));
18794 emit_insn (gen_rtx_SET (VOIDmode, t0, x));
18796 x = gen_rtx_NOT (vmode, tc);
18797 x = gen_rtx_AND (vmode, x, (min_p ? op0 : op1));
18798 emit_insn (gen_rtx_SET (VOIDmode, t1, x));
18800 x = gen_rtx_IOR (vmode, t0, t1);
18801 emit_insn (gen_rtx_SET (VOIDmode, target, x));
18804 /* Implement TARGET_CASE_VALUES_THRESHOLD. */
18807 mips_case_values_threshold (void)
18809 /* In MIPS16 mode using a larger case threshold generates smaller code. */
18810 if (TARGET_MIPS16 && optimize_size)
18813 return default_case_values_threshold ();
18816 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
18819 mips_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
18821 if (!TARGET_HARD_FLOAT_ABI)
18823 tree exceptions_var = create_tmp_var (MIPS_ATYPE_USI, NULL);
18824 tree fcsr_orig_var = create_tmp_var (MIPS_ATYPE_USI, NULL);
18825 tree fcsr_mod_var = create_tmp_var (MIPS_ATYPE_USI, NULL);
18826 tree get_fcsr = mips_builtin_decls[MIPS_GET_FCSR];
18827 tree set_fcsr = mips_builtin_decls[MIPS_SET_FCSR];
18828 tree get_fcsr_hold_call = build_call_expr (get_fcsr, 0);
18829 tree hold_assign_orig = build2 (MODIFY_EXPR, MIPS_ATYPE_USI,
18830 fcsr_orig_var, get_fcsr_hold_call);
18831 tree hold_mod_val = build2 (BIT_AND_EXPR, MIPS_ATYPE_USI, fcsr_orig_var,
18832 build_int_cst (MIPS_ATYPE_USI, 0xfffff003));
18833 tree hold_assign_mod = build2 (MODIFY_EXPR, MIPS_ATYPE_USI,
18834 fcsr_mod_var, hold_mod_val);
18835 tree set_fcsr_hold_call = build_call_expr (set_fcsr, 1, fcsr_mod_var);
18836 tree hold_all = build2 (COMPOUND_EXPR, MIPS_ATYPE_USI,
18837 hold_assign_orig, hold_assign_mod);
18838 *hold = build2 (COMPOUND_EXPR, void_type_node, hold_all,
18839 set_fcsr_hold_call);
18841 *clear = build_call_expr (set_fcsr, 1, fcsr_mod_var);
18843 tree get_fcsr_update_call = build_call_expr (get_fcsr, 0);
18844 *update = build2 (MODIFY_EXPR, MIPS_ATYPE_USI,
18845 exceptions_var, get_fcsr_update_call);
18846 tree set_fcsr_update_call = build_call_expr (set_fcsr, 1, fcsr_orig_var);
18847 *update = build2 (COMPOUND_EXPR, void_type_node, *update,
18848 set_fcsr_update_call);
18849 tree atomic_feraiseexcept
18850 = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT);
18851 tree int_exceptions_var = fold_convert (integer_type_node,
18853 tree atomic_feraiseexcept_call = build_call_expr (atomic_feraiseexcept,
18854 1, int_exceptions_var);
18855 *update = build2 (COMPOUND_EXPR, void_type_node, *update,
18856 atomic_feraiseexcept_call);
18859 /* Implement TARGET_SPILL_CLASS. */
18862 mips_spill_class (reg_class_t rclass ATTRIBUTE_UNUSED,
18863 enum machine_mode mode ATTRIBUTE_UNUSED)
18870 /* Implement TARGET_LRA_P. */
18875 return mips_lra_flag;
18878 /* Initialize the GCC target structure. */
18879 #undef TARGET_ASM_ALIGNED_HI_OP
18880 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
18881 #undef TARGET_ASM_ALIGNED_SI_OP
18882 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
18883 #undef TARGET_ASM_ALIGNED_DI_OP
18884 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
18886 #undef TARGET_OPTION_OVERRIDE
18887 #define TARGET_OPTION_OVERRIDE mips_option_override
18889 #undef TARGET_LEGITIMIZE_ADDRESS
18890 #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
18892 #undef TARGET_ASM_FUNCTION_PROLOGUE
18893 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
18894 #undef TARGET_ASM_FUNCTION_EPILOGUE
18895 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
18896 #undef TARGET_ASM_SELECT_RTX_SECTION
18897 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
18898 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
18899 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
18901 #undef TARGET_SCHED_INIT
18902 #define TARGET_SCHED_INIT mips_sched_init
18903 #undef TARGET_SCHED_REORDER
18904 #define TARGET_SCHED_REORDER mips_sched_reorder
18905 #undef TARGET_SCHED_REORDER2
18906 #define TARGET_SCHED_REORDER2 mips_sched_reorder2
18907 #undef TARGET_SCHED_VARIABLE_ISSUE
18908 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
18909 #undef TARGET_SCHED_ADJUST_COST
18910 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
18911 #undef TARGET_SCHED_ISSUE_RATE
18912 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
18913 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
18914 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
18915 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
18916 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
18917 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
18918 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
18919 mips_multipass_dfa_lookahead
18920 #undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
18921 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
18922 mips_small_register_classes_for_mode_p
18924 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
18925 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
18927 #undef TARGET_INSERT_ATTRIBUTES
18928 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
18929 #undef TARGET_MERGE_DECL_ATTRIBUTES
18930 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
18931 #undef TARGET_CAN_INLINE_P
18932 #define TARGET_CAN_INLINE_P mips_can_inline_p
18933 #undef TARGET_SET_CURRENT_FUNCTION
18934 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
18936 #undef TARGET_VALID_POINTER_MODE
18937 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
18938 #undef TARGET_REGISTER_MOVE_COST
18939 #define TARGET_REGISTER_MOVE_COST mips_register_move_cost
18940 #undef TARGET_REGISTER_PRIORITY
18941 #define TARGET_REGISTER_PRIORITY mips_register_priority
18942 #undef TARGET_MEMORY_MOVE_COST
18943 #define TARGET_MEMORY_MOVE_COST mips_memory_move_cost
18944 #undef TARGET_RTX_COSTS
18945 #define TARGET_RTX_COSTS mips_rtx_costs
18946 #undef TARGET_ADDRESS_COST
18947 #define TARGET_ADDRESS_COST mips_address_cost
18949 #undef TARGET_IN_SMALL_DATA_P
18950 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
18952 #undef TARGET_MACHINE_DEPENDENT_REORG
18953 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
18955 #undef TARGET_PREFERRED_RELOAD_CLASS
18956 #define TARGET_PREFERRED_RELOAD_CLASS mips_preferred_reload_class
18958 #undef TARGET_EXPAND_TO_RTL_HOOK
18959 #define TARGET_EXPAND_TO_RTL_HOOK mips_expand_to_rtl_hook
18960 #undef TARGET_ASM_FILE_START
18961 #define TARGET_ASM_FILE_START mips_file_start
18962 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
18963 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
18964 #undef TARGET_ASM_CODE_END
18965 #define TARGET_ASM_CODE_END mips_code_end
18967 #undef TARGET_INIT_LIBFUNCS
18968 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
18970 #undef TARGET_BUILD_BUILTIN_VA_LIST
18971 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
18972 #undef TARGET_EXPAND_BUILTIN_VA_START
18973 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
18974 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
18975 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
18977 #undef TARGET_PROMOTE_FUNCTION_MODE
18978 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
18979 #undef TARGET_PROMOTE_PROTOTYPES
18980 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
18982 #undef TARGET_FUNCTION_VALUE
18983 #define TARGET_FUNCTION_VALUE mips_function_value
18984 #undef TARGET_LIBCALL_VALUE
18985 #define TARGET_LIBCALL_VALUE mips_libcall_value
18986 #undef TARGET_FUNCTION_VALUE_REGNO_P
18987 #define TARGET_FUNCTION_VALUE_REGNO_P mips_function_value_regno_p
18988 #undef TARGET_RETURN_IN_MEMORY
18989 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
18990 #undef TARGET_RETURN_IN_MSB
18991 #define TARGET_RETURN_IN_MSB mips_return_in_msb
18993 #undef TARGET_ASM_OUTPUT_MI_THUNK
18994 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
18995 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
18996 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
18998 #undef TARGET_PRINT_OPERAND
18999 #define TARGET_PRINT_OPERAND mips_print_operand
19000 #undef TARGET_PRINT_OPERAND_ADDRESS
19001 #define TARGET_PRINT_OPERAND_ADDRESS mips_print_operand_address
19002 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
19003 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mips_print_operand_punct_valid_p
19005 #undef TARGET_SETUP_INCOMING_VARARGS
19006 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
19007 #undef TARGET_STRICT_ARGUMENT_NAMING
19008 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
19009 #undef TARGET_MUST_PASS_IN_STACK
19010 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
19011 #undef TARGET_PASS_BY_REFERENCE
19012 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
19013 #undef TARGET_CALLEE_COPIES
19014 #define TARGET_CALLEE_COPIES mips_callee_copies
19015 #undef TARGET_ARG_PARTIAL_BYTES
19016 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
19017 #undef TARGET_FUNCTION_ARG
19018 #define TARGET_FUNCTION_ARG mips_function_arg
19019 #undef TARGET_FUNCTION_ARG_ADVANCE
19020 #define TARGET_FUNCTION_ARG_ADVANCE mips_function_arg_advance
19021 #undef TARGET_FUNCTION_ARG_BOUNDARY
19022 #define TARGET_FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
19024 #undef TARGET_MODE_REP_EXTENDED
19025 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
19027 #undef TARGET_VECTOR_MODE_SUPPORTED_P
19028 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
19030 #undef TARGET_SCALAR_MODE_SUPPORTED_P
19031 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
19033 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
19034 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE mips_preferred_simd_mode
19036 #undef TARGET_INIT_BUILTINS
19037 #define TARGET_INIT_BUILTINS mips_init_builtins
19038 #undef TARGET_BUILTIN_DECL
19039 #define TARGET_BUILTIN_DECL mips_builtin_decl
19040 #undef TARGET_EXPAND_BUILTIN
19041 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
19043 #undef TARGET_HAVE_TLS
19044 #define TARGET_HAVE_TLS HAVE_AS_TLS
19046 #undef TARGET_CANNOT_FORCE_CONST_MEM
19047 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
19049 #undef TARGET_LEGITIMATE_CONSTANT_P
19050 #define TARGET_LEGITIMATE_CONSTANT_P mips_legitimate_constant_p
19052 #undef TARGET_ENCODE_SECTION_INFO
19053 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
19055 #undef TARGET_ATTRIBUTE_TABLE
19056 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
19057 /* All our function attributes are related to how out-of-line copies should
19058 be compiled or called. They don't in themselves prevent inlining. */
19059 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
19060 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
19062 #undef TARGET_EXTRA_LIVE_ON_ENTRY
19063 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
19065 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
19066 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
19067 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
19068 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
19070 #undef TARGET_COMP_TYPE_ATTRIBUTES
19071 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
19073 #ifdef HAVE_AS_DTPRELWORD
19074 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
19075 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
19077 #undef TARGET_DWARF_REGISTER_SPAN
19078 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
19080 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
19081 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
19083 #undef TARGET_LEGITIMATE_ADDRESS_P
19084 #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p
19086 #undef TARGET_FRAME_POINTER_REQUIRED
19087 #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required
19089 #undef TARGET_CAN_ELIMINATE
19090 #define TARGET_CAN_ELIMINATE mips_can_eliminate
19092 #undef TARGET_CONDITIONAL_REGISTER_USAGE
19093 #define TARGET_CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage
19095 #undef TARGET_TRAMPOLINE_INIT
19096 #define TARGET_TRAMPOLINE_INIT mips_trampoline_init
19098 #undef TARGET_ASM_OUTPUT_SOURCE_FILENAME
19099 #define TARGET_ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
19101 #undef TARGET_SHIFT_TRUNCATION_MASK
19102 #define TARGET_SHIFT_TRUNCATION_MASK mips_shift_truncation_mask
19104 #undef TARGET_PREPARE_PCH_SAVE
19105 #define TARGET_PREPARE_PCH_SAVE mips_prepare_pch_save
19107 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
19108 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK mips_vectorize_vec_perm_const_ok
19110 #undef TARGET_CASE_VALUES_THRESHOLD
19111 #define TARGET_CASE_VALUES_THRESHOLD mips_case_values_threshold
19113 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
19114 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV mips_atomic_assign_expand_fenv
19116 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
19117 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
19119 #undef TARGET_SPILL_CLASS
19120 #define TARGET_SPILL_CLASS mips_spill_class
19121 #undef TARGET_LRA_P
19122 #define TARGET_LRA_P mips_lra_p
19124 struct gcc_target targetm = TARGET_INITIALIZER;
19126 #include "gt-mips.h"