1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989-2014 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky, lich@inria.inria.fr.
4 Changes by Michael Meissner, meissner@osf.org.
5 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 Brendan Eich, brendan@microunity.com.
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
30 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
38 #include "stringpool.h"
39 #include "stor-layout.h"
50 #include "hash-table.h"
53 #include "target-def.h"
54 #include "common/common-target.h"
55 #include "langhooks.h"
56 #include "sched-int.h"
57 #include "pointer-set.h"
59 #include "basic-block.h"
60 #include "tree-ssa-alias.h"
61 #include "internal-fn.h"
62 #include "gimple-fold.h"
64 #include "gimple-expr.h"
69 #include "diagnostic.h"
70 #include "target-globals.h"
72 #include "tree-pass.h"
75 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
76 #define UNSPEC_ADDRESS_P(X) \
77 (GET_CODE (X) == UNSPEC \
78 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
79 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
81 /* Extract the symbol or label from UNSPEC wrapper X. */
82 #define UNSPEC_ADDRESS(X) \
85 /* Extract the symbol type from UNSPEC wrapper X. */
86 #define UNSPEC_ADDRESS_TYPE(X) \
87 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
89 /* The maximum distance between the top of the stack frame and the
90 value $sp has when we save and restore registers.
92 The value for normal-mode code must be a SMALL_OPERAND and must
93 preserve the maximum stack alignment. We therefore use a value
94 of 0x7ff0 in this case.
96 microMIPS LWM and SWM support 12-bit offsets (from -0x800 to 0x7ff),
97 so we use a maximum of 0x7f0 for TARGET_MICROMIPS.
99 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
100 up to 0x7f8 bytes and can usually save or restore all the registers
101 that we need to save or restore. (Note that we can only use these
102 instructions for o32, for which the stack alignment is 8 bytes.)
104 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
105 RESTORE are not available. We can then use unextended instructions
106 to save and restore registers, and to allocate and deallocate the top
107 part of the frame. */
108 #define MIPS_MAX_FIRST_STACK_STEP \
109 (!TARGET_COMPRESSION ? 0x7ff0 \
110 : TARGET_MICROMIPS || GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
111 : TARGET_64BIT ? 0x100 : 0x400)
113 /* True if INSN is a mips.md pattern or asm statement. */
114 /* ??? This test exists through the compiler, perhaps it should be
116 #define USEFUL_INSN_P(INSN) \
117 (NONDEBUG_INSN_P (INSN) \
118 && GET_CODE (PATTERN (INSN)) != USE \
119 && GET_CODE (PATTERN (INSN)) != CLOBBER)
121 /* If INSN is a delayed branch sequence, return the first instruction
122 in the sequence, otherwise return INSN itself. */
123 #define SEQ_BEGIN(INSN) \
124 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
125 ? XVECEXP (PATTERN (INSN), 0, 0) \
128 /* Likewise for the last instruction in a delayed branch sequence. */
129 #define SEQ_END(INSN) \
130 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
131 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
134 /* Execute the following loop body with SUBINSN set to each instruction
135 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
136 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
137 for ((SUBINSN) = SEQ_BEGIN (INSN); \
138 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
139 (SUBINSN) = NEXT_INSN (SUBINSN))
141 /* True if bit BIT is set in VALUE. */
142 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
144 /* Return the opcode for a ptr_mode load of the form:
146 l[wd] DEST, OFFSET(BASE). */
147 #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \
148 (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \
153 /* Return the opcode to move register SRC into register DEST. */
154 #define MIPS_MOVE(DEST, SRC) \
155 ((TARGET_64BIT ? 0x2d : 0x21) \
159 /* Return the opcode for:
162 #define MIPS_LUI(DEST, VALUE) \
163 ((0xf << 26) | ((DEST) << 16) | (VALUE))
165 /* Return the opcode to jump to register DEST. */
166 #define MIPS_JR(DEST) \
167 (((DEST) << 21) | 0x8)
169 /* Return the opcode for:
171 bal . + (1 + OFFSET) * 4. */
172 #define MIPS_BAL(OFFSET) \
173 ((0x1 << 26) | (0x11 << 16) | (OFFSET))
175 /* Return the usual opcode for a nop. */
178 /* Classifies an address.
181 A natural register + offset address. The register satisfies
182 mips_valid_base_register_p and the offset is a const_arith_operand.
185 A LO_SUM rtx. The first operand is a valid base register and
186 the second operand is a symbolic address.
189 A signed 16-bit constant address.
192 A constant symbolic address. */
193 enum mips_address_type {
200 /* Macros to create an enumeration identifier for a function prototype. */
201 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
202 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
203 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
204 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
206 /* Classifies the prototype of a built-in function. */
207 enum mips_function_type {
208 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
209 #include "config/mips/mips-ftypes.def"
210 #undef DEF_MIPS_FTYPE
214 /* Specifies how a built-in function should be converted into rtl. */
215 enum mips_builtin_type {
216 /* The function corresponds directly to an .md pattern. The return
217 value is mapped to operand 0 and the arguments are mapped to
218 operands 1 and above. */
221 /* The function corresponds directly to an .md pattern. There is no return
222 value and the arguments are mapped to operands 0 and above. */
223 MIPS_BUILTIN_DIRECT_NO_TARGET,
225 /* The function corresponds to a comparison instruction followed by
226 a mips_cond_move_tf_ps pattern. The first two arguments are the
227 values to compare and the second two arguments are the vector
228 operands for the movt.ps or movf.ps instruction (in assembly order). */
232 /* The function corresponds to a V2SF comparison instruction. Operand 0
233 of this instruction is the result of the comparison, which has mode
234 CCV2 or CCV4. The function arguments are mapped to operands 1 and
235 above. The function's return value is an SImode boolean that is
236 true under the following conditions:
238 MIPS_BUILTIN_CMP_ANY: one of the registers is true
239 MIPS_BUILTIN_CMP_ALL: all of the registers are true
240 MIPS_BUILTIN_CMP_LOWER: the first register is true
241 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
242 MIPS_BUILTIN_CMP_ANY,
243 MIPS_BUILTIN_CMP_ALL,
244 MIPS_BUILTIN_CMP_UPPER,
245 MIPS_BUILTIN_CMP_LOWER,
247 /* As above, but the instruction only sets a single $fcc register. */
248 MIPS_BUILTIN_CMP_SINGLE,
250 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
251 MIPS_BUILTIN_BPOSGE32
254 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
255 #define MIPS_FP_CONDITIONS(MACRO) \
273 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
274 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
275 enum mips_fp_condition {
276 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
278 #undef DECLARE_MIPS_COND
280 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
281 #define STRINGIFY(X) #X
282 static const char *const mips_fp_conditions[] = {
283 MIPS_FP_CONDITIONS (STRINGIFY)
287 /* A class used to control a comdat-style stub that we output in each
288 translation unit that needs it. */
289 class mips_one_only_stub {
291 virtual ~mips_one_only_stub () {}
293 /* Return the name of the stub. */
294 virtual const char *get_name () = 0;
296 /* Output the body of the function to asm_out_file. */
297 virtual void output_body () = 0;
300 /* Tuning information that is automatically derived from other sources
301 (such as the scheduler). */
303 /* The architecture and tuning settings that this structure describes. */
307 /* True if this structure describes MIPS16 settings. */
310 /* True if the structure has been initialized. */
313 /* True if "MULT $0, $0" is preferable to "MTLO $0; MTHI $0"
314 when optimizing for speed. */
315 bool fast_mult_zero_zero_p;
318 /* Information about a function's frame layout. */
319 struct GTY(()) mips_frame_info {
320 /* The size of the frame in bytes. */
321 HOST_WIDE_INT total_size;
323 /* The number of bytes allocated to variables. */
324 HOST_WIDE_INT var_size;
326 /* The number of bytes allocated to outgoing function arguments. */
327 HOST_WIDE_INT args_size;
329 /* The number of bytes allocated to the .cprestore slot, or 0 if there
331 HOST_WIDE_INT cprestore_size;
333 /* Bit X is set if the function saves or restores GPR X. */
336 /* Likewise FPR X. */
339 /* Likewise doubleword accumulator X ($acX). */
340 unsigned int acc_mask;
342 /* The number of GPRs, FPRs, doubleword accumulators and COP0
346 unsigned int num_acc;
347 unsigned int num_cop0_regs;
349 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
350 save slots from the top of the frame, or zero if no such slots are
352 HOST_WIDE_INT gp_save_offset;
353 HOST_WIDE_INT fp_save_offset;
354 HOST_WIDE_INT acc_save_offset;
355 HOST_WIDE_INT cop0_save_offset;
357 /* Likewise, but giving offsets from the bottom of the frame. */
358 HOST_WIDE_INT gp_sp_offset;
359 HOST_WIDE_INT fp_sp_offset;
360 HOST_WIDE_INT acc_sp_offset;
361 HOST_WIDE_INT cop0_sp_offset;
363 /* Similar, but the value passed to _mcount. */
364 HOST_WIDE_INT ra_fp_offset;
366 /* The offset of arg_pointer_rtx from the bottom of the frame. */
367 HOST_WIDE_INT arg_pointer_offset;
369 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
370 HOST_WIDE_INT hard_frame_pointer_offset;
373 struct GTY(()) machine_function {
374 /* The next floating-point condition-code register to allocate
375 for ISA_HAS_8CC targets, relative to ST_REG_FIRST. */
376 unsigned int next_fcc;
378 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
379 rtx mips16_gp_pseudo_rtx;
381 /* The number of extra stack bytes taken up by register varargs.
382 This area is allocated by the callee at the very top of the frame. */
385 /* The current frame information, calculated by mips_compute_frame_info. */
386 struct mips_frame_info frame;
388 /* The register to use as the function's global pointer, or INVALID_REGNUM
389 if the function doesn't need one. */
390 unsigned int global_pointer;
392 /* How many instructions it takes to load a label into $AT, or 0 if
393 this property hasn't yet been calculated. */
394 unsigned int load_label_num_insns;
396 /* True if mips_adjust_insn_length should ignore an instruction's
398 bool ignore_hazard_length_p;
400 /* True if the whole function is suitable for .set noreorder and
402 bool all_noreorder_p;
404 /* True if the function has "inflexible" and "flexible" references
405 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
406 and mips_cfun_has_flexible_gp_ref_p for details. */
407 bool has_inflexible_gp_insn_p;
408 bool has_flexible_gp_insn_p;
410 /* True if the function's prologue must load the global pointer
411 value into pic_offset_table_rtx and store the same value in
412 the function's cprestore slot (if any). Even if this value
413 is currently false, we may decide to set it to true later;
414 see mips_must_initialize_gp_p () for details. */
415 bool must_initialize_gp_p;
417 /* True if the current function must restore $gp after any potential
418 clobber. This value is only meaningful during the first post-epilogue
419 split_insns pass; see mips_must_initialize_gp_p () for details. */
420 bool must_restore_gp_when_clobbered_p;
422 /* True if this is an interrupt handler. */
423 bool interrupt_handler_p;
425 /* True if this is an interrupt handler that uses shadow registers. */
426 bool use_shadow_register_set_p;
428 /* True if this is an interrupt handler that should keep interrupts
430 bool keep_interrupts_masked_p;
432 /* True if this is an interrupt handler that should use DERET
434 bool use_debug_exception_return_p;
437 /* Information about a single argument. */
438 struct mips_arg_info {
439 /* True if the argument is passed in a floating-point register, or
440 would have been if we hadn't run out of registers. */
443 /* The number of words passed in registers, rounded up. */
444 unsigned int reg_words;
446 /* For EABI, the offset of the first register from GP_ARG_FIRST or
447 FP_ARG_FIRST. For other ABIs, the offset of the first register from
448 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
449 comment for details).
451 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
453 unsigned int reg_offset;
455 /* The number of words that must be passed on the stack, rounded up. */
456 unsigned int stack_words;
458 /* The offset from the start of the stack overflow area of the argument's
459 first stack word. Only meaningful when STACK_WORDS is nonzero. */
460 unsigned int stack_offset;
463 /* Information about an address described by mips_address_type.
469 REG is the base register and OFFSET is the constant offset.
472 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
473 is the type of symbol it references.
476 SYMBOL_TYPE is the type of symbol that the address references. */
477 struct mips_address_info {
478 enum mips_address_type type;
481 enum mips_symbol_type symbol_type;
484 /* One stage in a constant building sequence. These sequences have
488 A = A CODE[1] VALUE[1]
489 A = A CODE[2] VALUE[2]
492 where A is an accumulator, each CODE[i] is a binary rtl operation
493 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
494 struct mips_integer_op {
496 unsigned HOST_WIDE_INT value;
499 /* The largest number of operations needed to load an integer constant.
500 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
501 When the lowest bit is clear, we can try, but reject a sequence with
502 an extra SLL at the end. */
503 #define MIPS_MAX_INTEGER_OPS 7
505 /* Information about a MIPS16e SAVE or RESTORE instruction. */
506 struct mips16e_save_restore_info {
507 /* The number of argument registers saved by a SAVE instruction.
508 0 for RESTORE instructions. */
511 /* Bit X is set if the instruction saves or restores GPR X. */
514 /* The total number of bytes to allocate. */
518 /* Costs of various operations on the different architectures. */
520 struct mips_rtx_cost_data
522 unsigned short fp_add;
523 unsigned short fp_mult_sf;
524 unsigned short fp_mult_df;
525 unsigned short fp_div_sf;
526 unsigned short fp_div_df;
527 unsigned short int_mult_si;
528 unsigned short int_mult_di;
529 unsigned short int_div_si;
530 unsigned short int_div_di;
531 unsigned short branch_cost;
532 unsigned short memory_latency;
535 /* Global variables for machine-dependent things. */
537 /* The -G setting, or the configuration's default small-data limit if
538 no -G option is given. */
539 static unsigned int mips_small_data_threshold;
541 /* The number of file directives written by mips_output_filename. */
542 int num_source_filenames;
544 /* The name that appeared in the last .file directive written by
545 mips_output_filename, or "" if mips_output_filename hasn't
546 written anything yet. */
547 const char *current_function_file = "";
549 /* Arrays that map GCC register numbers to debugger register numbers. */
550 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
551 int mips_dwarf_regno[FIRST_PSEUDO_REGISTER];
553 /* Information about the current function's epilogue, used only while
556 /* A list of queued REG_CFA_RESTORE notes. */
559 /* The CFA is currently defined as CFA_REG + CFA_OFFSET. */
561 HOST_WIDE_INT cfa_offset;
563 /* The offset of the CFA from the stack pointer while restoring
565 HOST_WIDE_INT cfa_restore_sp_offset;
568 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
569 struct mips_asm_switch mips_noreorder = { "reorder", 0 };
570 struct mips_asm_switch mips_nomacro = { "macro", 0 };
571 struct mips_asm_switch mips_noat = { "at", 0 };
573 /* True if we're writing out a branch-likely instruction rather than a
575 static bool mips_branch_likely;
577 /* The current instruction-set architecture. */
578 enum processor mips_arch;
579 const struct mips_cpu_info *mips_arch_info;
581 /* The processor that we should tune the code for. */
582 enum processor mips_tune;
583 const struct mips_cpu_info *mips_tune_info;
585 /* The ISA level associated with mips_arch. */
588 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
589 static const struct mips_cpu_info *mips_isa_option_info;
591 /* Which cost information to use. */
592 static const struct mips_rtx_cost_data *mips_cost;
594 /* The ambient target flags, excluding MASK_MIPS16. */
595 static int mips_base_target_flags;
597 /* The default compression mode. */
598 unsigned int mips_base_compression_flags;
600 /* The ambient values of other global variables. */
601 static int mips_base_schedule_insns; /* flag_schedule_insns */
602 static int mips_base_reorder_blocks_and_partition; /* flag_reorder... */
603 static int mips_base_move_loop_invariants; /* flag_move_loop_invariants */
604 static int mips_base_align_loops; /* align_loops */
605 static int mips_base_align_jumps; /* align_jumps */
606 static int mips_base_align_functions; /* align_functions */
608 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
609 bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
611 /* Index C is true if character C is a valid PRINT_OPERAND punctation
613 static bool mips_print_operand_punct[256];
615 static GTY (()) int mips_output_filename_first_time = 1;
617 /* mips_split_p[X] is true if symbols of type X can be split by
618 mips_split_symbol. */
619 bool mips_split_p[NUM_SYMBOL_TYPES];
621 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
622 can be split by mips_split_symbol. */
623 bool mips_split_hi_p[NUM_SYMBOL_TYPES];
625 /* mips_use_pcrel_pool_p[X] is true if symbols of type X should be
626 forced into a PC-relative constant pool. */
627 bool mips_use_pcrel_pool_p[NUM_SYMBOL_TYPES];
629 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
630 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
631 if they are matched by a special .md file pattern. */
632 const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
634 /* Likewise for HIGHs. */
635 const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
637 /* Target state for MIPS16. */
638 struct target_globals *mips16_globals;
640 /* Cached value of can_issue_more. This is cached in mips_variable_issue hook
641 and returned from mips_sched_reorder2. */
642 static int cached_can_issue_more;
644 /* The stubs for various MIPS16 support functions, if used. */
645 static mips_one_only_stub *mips16_rdhwr_stub;
646 static mips_one_only_stub *mips16_get_fcsr_stub;
647 static mips_one_only_stub *mips16_set_fcsr_stub;
649 /* Index R is the smallest register class that contains register R. */
650 const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = {
651 LEA_REGS, LEA_REGS, M16_STORE_REGS, V1_REG,
652 M16_STORE_REGS, M16_STORE_REGS, M16_STORE_REGS, M16_STORE_REGS,
653 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
654 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
655 M16_REGS, M16_STORE_REGS, LEA_REGS, LEA_REGS,
656 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
657 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
658 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
660 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
661 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
662 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
663 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
664 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
665 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
666 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
667 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
668 MD0_REG, MD1_REG, NO_REGS, ST_REGS,
669 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
670 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
671 NO_REGS, FRAME_REGS, FRAME_REGS, NO_REGS,
672 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
673 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
674 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
675 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
676 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
677 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
678 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
679 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
680 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
681 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
682 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
683 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
684 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
685 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
686 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
687 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
688 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
689 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
690 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
691 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
692 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
693 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
694 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
695 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
696 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
697 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
698 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
701 /* The value of TARGET_ATTRIBUTE_TABLE. */
702 static const struct attribute_spec mips_attribute_table[] = {
703 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
705 { "long_call", 0, 0, false, true, true, NULL, false },
706 { "far", 0, 0, false, true, true, NULL, false },
707 { "near", 0, 0, false, true, true, NULL, false },
708 /* We would really like to treat "mips16" and "nomips16" as type
709 attributes, but GCC doesn't provide the hooks we need to support
710 the right conversion rules. As declaration attributes, they affect
711 code generation but don't carry other semantics. */
712 { "mips16", 0, 0, true, false, false, NULL, false },
713 { "nomips16", 0, 0, true, false, false, NULL, false },
714 { "micromips", 0, 0, true, false, false, NULL, false },
715 { "nomicromips", 0, 0, true, false, false, NULL, false },
716 { "nocompression", 0, 0, true, false, false, NULL, false },
717 /* Allow functions to be specified as interrupt handlers */
718 { "interrupt", 0, 0, false, true, true, NULL, false },
719 { "use_shadow_register_set", 0, 0, false, true, true, NULL, false },
720 { "keep_interrupts_masked", 0, 0, false, true, true, NULL, false },
721 { "use_debug_exception_return", 0, 0, false, true, true, NULL, false },
722 { NULL, 0, 0, false, false, false, NULL, false }
725 /* A table describing all the processors GCC knows about; see
726 mips-cpus.def for details. */
727 static const struct mips_cpu_info mips_cpu_info_table[] = {
728 #define MIPS_CPU(NAME, CPU, ISA, FLAGS) \
729 { NAME, CPU, ISA, FLAGS },
730 #include "mips-cpus.def"
734 /* Default costs. If these are used for a processor we should look
735 up the actual costs. */
736 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
737 COSTS_N_INSNS (7), /* fp_mult_sf */ \
738 COSTS_N_INSNS (8), /* fp_mult_df */ \
739 COSTS_N_INSNS (23), /* fp_div_sf */ \
740 COSTS_N_INSNS (36), /* fp_div_df */ \
741 COSTS_N_INSNS (10), /* int_mult_si */ \
742 COSTS_N_INSNS (10), /* int_mult_di */ \
743 COSTS_N_INSNS (69), /* int_div_si */ \
744 COSTS_N_INSNS (69), /* int_div_di */ \
745 2, /* branch_cost */ \
746 4 /* memory_latency */
748 /* Floating-point costs for processors without an FPU. Just assume that
749 all floating-point libcalls are very expensive. */
750 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
751 COSTS_N_INSNS (256), /* fp_mult_sf */ \
752 COSTS_N_INSNS (256), /* fp_mult_df */ \
753 COSTS_N_INSNS (256), /* fp_div_sf */ \
754 COSTS_N_INSNS (256) /* fp_div_df */
756 /* Costs to use when optimizing for size. */
757 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size = {
758 COSTS_N_INSNS (1), /* fp_add */
759 COSTS_N_INSNS (1), /* fp_mult_sf */
760 COSTS_N_INSNS (1), /* fp_mult_df */
761 COSTS_N_INSNS (1), /* fp_div_sf */
762 COSTS_N_INSNS (1), /* fp_div_df */
763 COSTS_N_INSNS (1), /* int_mult_si */
764 COSTS_N_INSNS (1), /* int_mult_di */
765 COSTS_N_INSNS (1), /* int_div_si */
766 COSTS_N_INSNS (1), /* int_div_di */
768 4 /* memory_latency */
771 /* Costs to use when optimizing for speed, indexed by processor. */
772 static const struct mips_rtx_cost_data
773 mips_rtx_cost_data[NUM_PROCESSOR_VALUES] = {
775 COSTS_N_INSNS (2), /* fp_add */
776 COSTS_N_INSNS (4), /* fp_mult_sf */
777 COSTS_N_INSNS (5), /* fp_mult_df */
778 COSTS_N_INSNS (12), /* fp_div_sf */
779 COSTS_N_INSNS (19), /* fp_div_df */
780 COSTS_N_INSNS (12), /* int_mult_si */
781 COSTS_N_INSNS (12), /* int_mult_di */
782 COSTS_N_INSNS (35), /* int_div_si */
783 COSTS_N_INSNS (35), /* int_div_di */
785 4 /* memory_latency */
789 COSTS_N_INSNS (6), /* int_mult_si */
790 COSTS_N_INSNS (6), /* int_mult_di */
791 COSTS_N_INSNS (36), /* int_div_si */
792 COSTS_N_INSNS (36), /* int_div_di */
794 4 /* memory_latency */
798 COSTS_N_INSNS (36), /* int_mult_si */
799 COSTS_N_INSNS (36), /* int_mult_di */
800 COSTS_N_INSNS (37), /* int_div_si */
801 COSTS_N_INSNS (37), /* int_div_di */
803 4 /* memory_latency */
807 COSTS_N_INSNS (4), /* int_mult_si */
808 COSTS_N_INSNS (11), /* int_mult_di */
809 COSTS_N_INSNS (36), /* int_div_si */
810 COSTS_N_INSNS (68), /* int_div_di */
812 4 /* memory_latency */
815 COSTS_N_INSNS (4), /* fp_add */
816 COSTS_N_INSNS (4), /* fp_mult_sf */
817 COSTS_N_INSNS (5), /* fp_mult_df */
818 COSTS_N_INSNS (17), /* fp_div_sf */
819 COSTS_N_INSNS (32), /* fp_div_df */
820 COSTS_N_INSNS (4), /* int_mult_si */
821 COSTS_N_INSNS (11), /* int_mult_di */
822 COSTS_N_INSNS (36), /* int_div_si */
823 COSTS_N_INSNS (68), /* int_div_di */
825 4 /* memory_latency */
828 COSTS_N_INSNS (4), /* fp_add */
829 COSTS_N_INSNS (4), /* fp_mult_sf */
830 COSTS_N_INSNS (5), /* fp_mult_df */
831 COSTS_N_INSNS (17), /* fp_div_sf */
832 COSTS_N_INSNS (32), /* fp_div_df */
833 COSTS_N_INSNS (4), /* int_mult_si */
834 COSTS_N_INSNS (7), /* int_mult_di */
835 COSTS_N_INSNS (42), /* int_div_si */
836 COSTS_N_INSNS (72), /* int_div_di */
838 4 /* memory_latency */
842 COSTS_N_INSNS (5), /* int_mult_si */
843 COSTS_N_INSNS (5), /* int_mult_di */
844 COSTS_N_INSNS (41), /* int_div_si */
845 COSTS_N_INSNS (41), /* int_div_di */
847 4 /* memory_latency */
850 COSTS_N_INSNS (8), /* fp_add */
851 COSTS_N_INSNS (8), /* fp_mult_sf */
852 COSTS_N_INSNS (10), /* fp_mult_df */
853 COSTS_N_INSNS (34), /* fp_div_sf */
854 COSTS_N_INSNS (64), /* fp_div_df */
855 COSTS_N_INSNS (5), /* int_mult_si */
856 COSTS_N_INSNS (5), /* int_mult_di */
857 COSTS_N_INSNS (41), /* int_div_si */
858 COSTS_N_INSNS (41), /* int_div_di */
860 4 /* memory_latency */
863 COSTS_N_INSNS (4), /* fp_add */
864 COSTS_N_INSNS (4), /* fp_mult_sf */
865 COSTS_N_INSNS (5), /* fp_mult_df */
866 COSTS_N_INSNS (17), /* fp_div_sf */
867 COSTS_N_INSNS (32), /* fp_div_df */
868 COSTS_N_INSNS (5), /* int_mult_si */
869 COSTS_N_INSNS (5), /* int_mult_di */
870 COSTS_N_INSNS (41), /* int_div_si */
871 COSTS_N_INSNS (41), /* int_div_di */
873 4 /* memory_latency */
877 COSTS_N_INSNS (5), /* int_mult_si */
878 COSTS_N_INSNS (5), /* int_mult_di */
879 COSTS_N_INSNS (41), /* int_div_si */
880 COSTS_N_INSNS (41), /* int_div_di */
882 4 /* memory_latency */
885 COSTS_N_INSNS (8), /* fp_add */
886 COSTS_N_INSNS (8), /* fp_mult_sf */
887 COSTS_N_INSNS (10), /* fp_mult_df */
888 COSTS_N_INSNS (34), /* fp_div_sf */
889 COSTS_N_INSNS (64), /* fp_div_df */
890 COSTS_N_INSNS (5), /* int_mult_si */
891 COSTS_N_INSNS (5), /* int_mult_di */
892 COSTS_N_INSNS (41), /* int_div_si */
893 COSTS_N_INSNS (41), /* int_div_di */
895 4 /* memory_latency */
898 COSTS_N_INSNS (4), /* fp_add */
899 COSTS_N_INSNS (4), /* fp_mult_sf */
900 COSTS_N_INSNS (5), /* fp_mult_df */
901 COSTS_N_INSNS (17), /* fp_div_sf */
902 COSTS_N_INSNS (32), /* fp_div_df */
903 COSTS_N_INSNS (5), /* int_mult_si */
904 COSTS_N_INSNS (5), /* int_mult_di */
905 COSTS_N_INSNS (41), /* int_div_si */
906 COSTS_N_INSNS (41), /* int_div_di */
908 4 /* memory_latency */
911 COSTS_N_INSNS (6), /* fp_add */
912 COSTS_N_INSNS (6), /* fp_mult_sf */
913 COSTS_N_INSNS (7), /* fp_mult_df */
914 COSTS_N_INSNS (25), /* fp_div_sf */
915 COSTS_N_INSNS (48), /* fp_div_df */
916 COSTS_N_INSNS (5), /* int_mult_si */
917 COSTS_N_INSNS (5), /* int_mult_di */
918 COSTS_N_INSNS (41), /* int_div_si */
919 COSTS_N_INSNS (41), /* int_div_di */
921 4 /* memory_latency */
938 COSTS_N_INSNS (5), /* int_mult_si */
939 COSTS_N_INSNS (5), /* int_mult_di */
940 COSTS_N_INSNS (72), /* int_div_si */
941 COSTS_N_INSNS (72), /* int_div_di */
943 4 /* memory_latency */
948 COSTS_N_INSNS (6), /* int_mult_si */
949 COSTS_N_INSNS (6), /* int_mult_di */
950 COSTS_N_INSNS (18), /* int_div_si */
951 COSTS_N_INSNS (35), /* int_div_di */
953 4 /* memory_latency */
956 COSTS_N_INSNS (2), /* fp_add */
957 COSTS_N_INSNS (4), /* fp_mult_sf */
958 COSTS_N_INSNS (5), /* fp_mult_df */
959 COSTS_N_INSNS (12), /* fp_div_sf */
960 COSTS_N_INSNS (19), /* fp_div_df */
961 COSTS_N_INSNS (2), /* int_mult_si */
962 COSTS_N_INSNS (2), /* int_mult_di */
963 COSTS_N_INSNS (35), /* int_div_si */
964 COSTS_N_INSNS (35), /* int_div_di */
966 4 /* memory_latency */
969 COSTS_N_INSNS (3), /* fp_add */
970 COSTS_N_INSNS (5), /* fp_mult_sf */
971 COSTS_N_INSNS (6), /* fp_mult_df */
972 COSTS_N_INSNS (15), /* fp_div_sf */
973 COSTS_N_INSNS (16), /* fp_div_df */
974 COSTS_N_INSNS (17), /* int_mult_si */
975 COSTS_N_INSNS (17), /* int_mult_di */
976 COSTS_N_INSNS (38), /* int_div_si */
977 COSTS_N_INSNS (38), /* int_div_di */
979 6 /* memory_latency */
982 COSTS_N_INSNS (6), /* fp_add */
983 COSTS_N_INSNS (7), /* fp_mult_sf */
984 COSTS_N_INSNS (8), /* fp_mult_df */
985 COSTS_N_INSNS (23), /* fp_div_sf */
986 COSTS_N_INSNS (36), /* fp_div_df */
987 COSTS_N_INSNS (10), /* int_mult_si */
988 COSTS_N_INSNS (10), /* int_mult_di */
989 COSTS_N_INSNS (69), /* int_div_si */
990 COSTS_N_INSNS (69), /* int_div_di */
992 6 /* memory_latency */
1004 /* The only costs that appear to be updated here are
1005 integer multiplication. */
1007 COSTS_N_INSNS (4), /* int_mult_si */
1008 COSTS_N_INSNS (6), /* int_mult_di */
1009 COSTS_N_INSNS (69), /* int_div_si */
1010 COSTS_N_INSNS (69), /* int_div_di */
1011 1, /* branch_cost */
1012 4 /* memory_latency */
1027 COSTS_N_INSNS (6), /* fp_add */
1028 COSTS_N_INSNS (4), /* fp_mult_sf */
1029 COSTS_N_INSNS (5), /* fp_mult_df */
1030 COSTS_N_INSNS (23), /* fp_div_sf */
1031 COSTS_N_INSNS (36), /* fp_div_df */
1032 COSTS_N_INSNS (5), /* int_mult_si */
1033 COSTS_N_INSNS (5), /* int_mult_di */
1034 COSTS_N_INSNS (36), /* int_div_si */
1035 COSTS_N_INSNS (36), /* int_div_di */
1036 1, /* branch_cost */
1037 4 /* memory_latency */
1040 COSTS_N_INSNS (6), /* fp_add */
1041 COSTS_N_INSNS (5), /* fp_mult_sf */
1042 COSTS_N_INSNS (6), /* fp_mult_df */
1043 COSTS_N_INSNS (30), /* fp_div_sf */
1044 COSTS_N_INSNS (59), /* fp_div_df */
1045 COSTS_N_INSNS (3), /* int_mult_si */
1046 COSTS_N_INSNS (4), /* int_mult_di */
1047 COSTS_N_INSNS (42), /* int_div_si */
1048 COSTS_N_INSNS (74), /* int_div_di */
1049 1, /* branch_cost */
1050 4 /* memory_latency */
1053 COSTS_N_INSNS (6), /* fp_add */
1054 COSTS_N_INSNS (5), /* fp_mult_sf */
1055 COSTS_N_INSNS (6), /* fp_mult_df */
1056 COSTS_N_INSNS (30), /* fp_div_sf */
1057 COSTS_N_INSNS (59), /* fp_div_df */
1058 COSTS_N_INSNS (5), /* int_mult_si */
1059 COSTS_N_INSNS (9), /* int_mult_di */
1060 COSTS_N_INSNS (42), /* int_div_si */
1061 COSTS_N_INSNS (74), /* int_div_di */
1062 1, /* branch_cost */
1063 4 /* memory_latency */
1066 COSTS_N_INSNS (4), /* fp_add */
1067 COSTS_N_INSNS (4), /* fp_mult_sf */
1068 COSTS_N_INSNS (256), /* fp_mult_df */
1069 COSTS_N_INSNS (8), /* fp_div_sf */
1070 COSTS_N_INSNS (256), /* fp_div_df */
1071 COSTS_N_INSNS (4), /* int_mult_si */
1072 COSTS_N_INSNS (256), /* int_mult_di */
1073 COSTS_N_INSNS (37), /* int_div_si */
1074 COSTS_N_INSNS (256), /* int_div_di */
1075 1, /* branch_cost */
1076 4 /* memory_latency */
1079 /* The only costs that are changed here are
1080 integer multiplication. */
1081 COSTS_N_INSNS (6), /* fp_add */
1082 COSTS_N_INSNS (7), /* fp_mult_sf */
1083 COSTS_N_INSNS (8), /* fp_mult_df */
1084 COSTS_N_INSNS (23), /* fp_div_sf */
1085 COSTS_N_INSNS (36), /* fp_div_df */
1086 COSTS_N_INSNS (5), /* int_mult_si */
1087 COSTS_N_INSNS (9), /* int_mult_di */
1088 COSTS_N_INSNS (69), /* int_div_si */
1089 COSTS_N_INSNS (69), /* int_div_di */
1090 1, /* branch_cost */
1091 4 /* memory_latency */
1097 /* The only costs that are changed here are
1098 integer multiplication. */
1099 COSTS_N_INSNS (6), /* fp_add */
1100 COSTS_N_INSNS (7), /* fp_mult_sf */
1101 COSTS_N_INSNS (8), /* fp_mult_df */
1102 COSTS_N_INSNS (23), /* fp_div_sf */
1103 COSTS_N_INSNS (36), /* fp_div_df */
1104 COSTS_N_INSNS (3), /* int_mult_si */
1105 COSTS_N_INSNS (8), /* int_mult_di */
1106 COSTS_N_INSNS (69), /* int_div_si */
1107 COSTS_N_INSNS (69), /* int_div_di */
1108 1, /* branch_cost */
1109 4 /* memory_latency */
1112 COSTS_N_INSNS (2), /* fp_add */
1113 COSTS_N_INSNS (2), /* fp_mult_sf */
1114 COSTS_N_INSNS (2), /* fp_mult_df */
1115 COSTS_N_INSNS (12), /* fp_div_sf */
1116 COSTS_N_INSNS (19), /* fp_div_df */
1117 COSTS_N_INSNS (5), /* int_mult_si */
1118 COSTS_N_INSNS (9), /* int_mult_di */
1119 COSTS_N_INSNS (34), /* int_div_si */
1120 COSTS_N_INSNS (66), /* int_div_di */
1121 1, /* branch_cost */
1122 4 /* memory_latency */
1125 /* These costs are the same as the SB-1A below. */
1126 COSTS_N_INSNS (4), /* fp_add */
1127 COSTS_N_INSNS (4), /* fp_mult_sf */
1128 COSTS_N_INSNS (4), /* fp_mult_df */
1129 COSTS_N_INSNS (24), /* fp_div_sf */
1130 COSTS_N_INSNS (32), /* fp_div_df */
1131 COSTS_N_INSNS (3), /* int_mult_si */
1132 COSTS_N_INSNS (4), /* int_mult_di */
1133 COSTS_N_INSNS (36), /* int_div_si */
1134 COSTS_N_INSNS (68), /* int_div_di */
1135 1, /* branch_cost */
1136 4 /* memory_latency */
1139 /* These costs are the same as the SB-1 above. */
1140 COSTS_N_INSNS (4), /* fp_add */
1141 COSTS_N_INSNS (4), /* fp_mult_sf */
1142 COSTS_N_INSNS (4), /* fp_mult_df */
1143 COSTS_N_INSNS (24), /* fp_div_sf */
1144 COSTS_N_INSNS (32), /* fp_div_df */
1145 COSTS_N_INSNS (3), /* int_mult_si */
1146 COSTS_N_INSNS (4), /* int_mult_di */
1147 COSTS_N_INSNS (36), /* int_div_si */
1148 COSTS_N_INSNS (68), /* int_div_di */
1149 1, /* branch_cost */
1150 4 /* memory_latency */
1157 COSTS_N_INSNS (8), /* int_mult_si */
1158 COSTS_N_INSNS (8), /* int_mult_di */
1159 COSTS_N_INSNS (72), /* int_div_si */
1160 COSTS_N_INSNS (72), /* int_div_di */
1161 1, /* branch_cost */
1162 4 /* memory_latency */
1165 /* These costs are the same as 5KF above. */
1166 COSTS_N_INSNS (4), /* fp_add */
1167 COSTS_N_INSNS (4), /* fp_mult_sf */
1168 COSTS_N_INSNS (5), /* fp_mult_df */
1169 COSTS_N_INSNS (17), /* fp_div_sf */
1170 COSTS_N_INSNS (32), /* fp_div_df */
1171 COSTS_N_INSNS (4), /* int_mult_si */
1172 COSTS_N_INSNS (11), /* int_mult_di */
1173 COSTS_N_INSNS (36), /* int_div_si */
1174 COSTS_N_INSNS (68), /* int_div_di */
1175 1, /* branch_cost */
1176 4 /* memory_latency */
1180 static rtx mips_find_pic_call_symbol (rtx, rtx, bool);
1181 static int mips_register_move_cost (enum machine_mode, reg_class_t,
1183 static unsigned int mips_function_arg_boundary (enum machine_mode, const_tree);
1185 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1186 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1187 struct GTY (()) mflip_mips16_entry {
1191 static GTY ((param_is (struct mflip_mips16_entry))) htab_t mflip_mips16_htab;
1193 /* Hash table callbacks for mflip_mips16_htab. */
1196 mflip_mips16_htab_hash (const void *entry)
1198 return htab_hash_string (((const struct mflip_mips16_entry *) entry)->name);
1202 mflip_mips16_htab_eq (const void *entry, const void *name)
1204 return strcmp (((const struct mflip_mips16_entry *) entry)->name,
1205 (const char *) name) == 0;
1208 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1209 mode, false if it should next add an attribute for the opposite mode. */
1210 static GTY(()) bool mips16_flipper;
1212 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1213 for -mflip-mips16. Return true if it should use "mips16" and false if
1214 it should use "nomips16". */
1217 mflip_mips16_use_mips16_p (tree decl)
1219 struct mflip_mips16_entry *entry;
1223 bool base_is_mips16 = (mips_base_compression_flags & MASK_MIPS16) != 0;
1225 /* Use the opposite of the command-line setting for anonymous decls. */
1226 if (!DECL_NAME (decl))
1227 return !base_is_mips16;
1229 if (!mflip_mips16_htab)
1230 mflip_mips16_htab = htab_create_ggc (37, mflip_mips16_htab_hash,
1231 mflip_mips16_htab_eq, NULL);
1233 name = IDENTIFIER_POINTER (DECL_NAME (decl));
1234 hash = htab_hash_string (name);
1235 slot = htab_find_slot_with_hash (mflip_mips16_htab, name, hash, INSERT);
1236 entry = (struct mflip_mips16_entry *) *slot;
1239 mips16_flipper = !mips16_flipper;
1240 entry = ggc_alloc_mflip_mips16_entry ();
1242 entry->mips16_p = mips16_flipper ? !base_is_mips16 : base_is_mips16;
1245 return entry->mips16_p;
1248 /* Predicates to test for presence of "near" and "far"/"long_call"
1249 attributes on the given TYPE. */
1252 mips_near_type_p (const_tree type)
1254 return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL;
1258 mips_far_type_p (const_tree type)
1260 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL
1261 || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL);
1265 /* Check if the interrupt attribute is set for a function. */
1268 mips_interrupt_type_p (tree type)
1270 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type)) != NULL;
1273 /* Check if the attribute to use shadow register set is set for a function. */
1276 mips_use_shadow_register_set_p (tree type)
1278 return lookup_attribute ("use_shadow_register_set",
1279 TYPE_ATTRIBUTES (type)) != NULL;
1282 /* Check if the attribute to keep interrupts masked is set for a function. */
1285 mips_keep_interrupts_masked_p (tree type)
1287 return lookup_attribute ("keep_interrupts_masked",
1288 TYPE_ATTRIBUTES (type)) != NULL;
1291 /* Check if the attribute to use debug exception return is set for
1295 mips_use_debug_exception_return_p (tree type)
1297 return lookup_attribute ("use_debug_exception_return",
1298 TYPE_ATTRIBUTES (type)) != NULL;
1301 /* Return the set of compression modes that are explicitly required
1302 by the attributes in ATTRIBUTES. */
1305 mips_get_compress_on_flags (tree attributes)
1307 unsigned int flags = 0;
1309 if (lookup_attribute ("mips16", attributes) != NULL)
1310 flags |= MASK_MIPS16;
1312 if (lookup_attribute ("micromips", attributes) != NULL)
1313 flags |= MASK_MICROMIPS;
1318 /* Return the set of compression modes that are explicitly forbidden
1319 by the attributes in ATTRIBUTES. */
1322 mips_get_compress_off_flags (tree attributes)
1324 unsigned int flags = 0;
1326 if (lookup_attribute ("nocompression", attributes) != NULL)
1327 flags |= MASK_MIPS16 | MASK_MICROMIPS;
1329 if (lookup_attribute ("nomips16", attributes) != NULL)
1330 flags |= MASK_MIPS16;
1332 if (lookup_attribute ("nomicromips", attributes) != NULL)
1333 flags |= MASK_MICROMIPS;
1338 /* Return the compression mode that should be used for function DECL.
1339 Return the ambient setting if DECL is null. */
1342 mips_get_compress_mode (tree decl)
1344 unsigned int flags, force_on;
1346 flags = mips_base_compression_flags;
1349 /* Nested functions must use the same frame pointer as their
1350 parent and must therefore use the same ISA mode. */
1351 tree parent = decl_function_context (decl);
1354 force_on = mips_get_compress_on_flags (DECL_ATTRIBUTES (decl));
1357 flags &= ~mips_get_compress_off_flags (DECL_ATTRIBUTES (decl));
1362 /* Return the attribute name associated with MASK_MIPS16 and MASK_MICROMIPS
1366 mips_get_compress_on_name (unsigned int flags)
1368 if (flags == MASK_MIPS16)
1373 /* Return the attribute name that forbids MASK_MIPS16 and MASK_MICROMIPS
1377 mips_get_compress_off_name (unsigned int flags)
1379 if (flags == MASK_MIPS16)
1381 if (flags == MASK_MICROMIPS)
1382 return "nomicromips";
1383 return "nocompression";
1386 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1389 mips_comp_type_attributes (const_tree type1, const_tree type2)
1391 /* Disallow mixed near/far attributes. */
1392 if (mips_far_type_p (type1) && mips_near_type_p (type2))
1394 if (mips_near_type_p (type1) && mips_far_type_p (type2))
1399 /* Implement TARGET_INSERT_ATTRIBUTES. */
1402 mips_insert_attributes (tree decl, tree *attributes)
1405 unsigned int compression_flags, nocompression_flags;
1407 /* Check for "mips16" and "nomips16" attributes. */
1408 compression_flags = mips_get_compress_on_flags (*attributes);
1409 nocompression_flags = mips_get_compress_off_flags (*attributes);
1411 if (TREE_CODE (decl) != FUNCTION_DECL)
1413 if (nocompression_flags)
1414 error ("%qs attribute only applies to functions",
1415 mips_get_compress_off_name (nocompression_flags));
1417 if (compression_flags)
1418 error ("%qs attribute only applies to functions",
1419 mips_get_compress_on_name (nocompression_flags));
1423 compression_flags |= mips_get_compress_on_flags (DECL_ATTRIBUTES (decl));
1424 nocompression_flags |=
1425 mips_get_compress_off_flags (DECL_ATTRIBUTES (decl));
1427 if (compression_flags && nocompression_flags)
1428 error ("%qE cannot have both %qs and %qs attributes",
1429 DECL_NAME (decl), mips_get_compress_on_name (compression_flags),
1430 mips_get_compress_off_name (nocompression_flags));
1432 if (compression_flags & MASK_MIPS16
1433 && compression_flags & MASK_MICROMIPS)
1434 error ("%qE cannot have both %qs and %qs attributes",
1435 DECL_NAME (decl), "mips16", "micromips");
1437 if (TARGET_FLIP_MIPS16
1438 && !DECL_ARTIFICIAL (decl)
1439 && compression_flags == 0
1440 && nocompression_flags == 0)
1442 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1443 "mips16" attribute, arbitrarily pick one. We must pick the same
1444 setting for duplicate declarations of a function. */
1445 name = mflip_mips16_use_mips16_p (decl) ? "mips16" : "nomips16";
1446 *attributes = tree_cons (get_identifier (name), NULL, *attributes);
1447 name = "nomicromips";
1448 *attributes = tree_cons (get_identifier (name), NULL, *attributes);
1453 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1456 mips_merge_decl_attributes (tree olddecl, tree newdecl)
1460 diff = (mips_get_compress_on_flags (DECL_ATTRIBUTES (olddecl))
1461 ^ mips_get_compress_on_flags (DECL_ATTRIBUTES (newdecl)));
1463 error ("%qE redeclared with conflicting %qs attributes",
1464 DECL_NAME (newdecl), mips_get_compress_on_name (diff));
1466 diff = (mips_get_compress_off_flags (DECL_ATTRIBUTES (olddecl))
1467 ^ mips_get_compress_off_flags (DECL_ATTRIBUTES (newdecl)));
1469 error ("%qE redeclared with conflicting %qs attributes",
1470 DECL_NAME (newdecl), mips_get_compress_off_name (diff));
1472 return merge_attributes (DECL_ATTRIBUTES (olddecl),
1473 DECL_ATTRIBUTES (newdecl));
1476 /* Implement TARGET_CAN_INLINE_P. */
1479 mips_can_inline_p (tree caller, tree callee)
1481 if (mips_get_compress_mode (callee) != mips_get_compress_mode (caller))
1483 return default_target_can_inline_p (caller, callee);
1486 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1487 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1490 mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr)
1492 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
1494 *base_ptr = XEXP (x, 0);
1495 *offset_ptr = INTVAL (XEXP (x, 1));
1504 static unsigned int mips_build_integer (struct mips_integer_op *,
1505 unsigned HOST_WIDE_INT);
1507 /* A subroutine of mips_build_integer, with the same interface.
1508 Assume that the final action in the sequence should be a left shift. */
1511 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1513 unsigned int i, shift;
1515 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1516 since signed numbers are easier to load than unsigned ones. */
1518 while ((value & 1) == 0)
1519 value /= 2, shift++;
1521 i = mips_build_integer (codes, value);
1522 codes[i].code = ASHIFT;
1523 codes[i].value = shift;
1527 /* As for mips_build_shift, but assume that the final action will be
1528 an IOR or PLUS operation. */
1531 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1533 unsigned HOST_WIDE_INT high;
1536 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1537 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
1539 /* The constant is too complex to load with a simple LUI/ORI pair,
1540 so we want to give the recursive call as many trailing zeros as
1541 possible. In this case, we know bit 16 is set and that the
1542 low 16 bits form a negative number. If we subtract that number
1543 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1544 i = mips_build_integer (codes, CONST_HIGH_PART (value));
1545 codes[i].code = PLUS;
1546 codes[i].value = CONST_LOW_PART (value);
1550 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1551 bits gives a value with at least 17 trailing zeros. */
1552 i = mips_build_integer (codes, high);
1553 codes[i].code = IOR;
1554 codes[i].value = value & 0xffff;
1559 /* Fill CODES with a sequence of rtl operations to load VALUE.
1560 Return the number of operations needed. */
1563 mips_build_integer (struct mips_integer_op *codes,
1564 unsigned HOST_WIDE_INT value)
1566 if (SMALL_OPERAND (value)
1567 || SMALL_OPERAND_UNSIGNED (value)
1568 || LUI_OPERAND (value))
1570 /* The value can be loaded with a single instruction. */
1571 codes[0].code = UNKNOWN;
1572 codes[0].value = value;
1575 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
1577 /* Either the constant is a simple LUI/ORI combination or its
1578 lowest bit is set. We don't want to shift in this case. */
1579 return mips_build_lower (codes, value);
1581 else if ((value & 0xffff) == 0)
1583 /* The constant will need at least three actions. The lowest
1584 16 bits are clear, so the final action will be a shift. */
1585 return mips_build_shift (codes, value);
1589 /* The final action could be a shift, add or inclusive OR.
1590 Rather than use a complex condition to select the best
1591 approach, try both mips_build_shift and mips_build_lower
1592 and pick the one that gives the shortest sequence.
1593 Note that this case is only used once per constant. */
1594 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1595 unsigned int cost, alt_cost;
1597 cost = mips_build_shift (codes, value);
1598 alt_cost = mips_build_lower (alt_codes, value);
1599 if (alt_cost < cost)
1601 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
1608 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
1611 mips_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
1613 return mips_const_insns (x) > 0;
1616 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
1619 mips16_stub_function (const char *name)
1623 x = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
1624 SYMBOL_REF_FLAGS (x) |= (SYMBOL_FLAG_EXTERNAL | SYMBOL_FLAG_FUNCTION);
1628 /* Return a legitimate call address for STUB, given that STUB is a MIPS16
1629 support function. */
1632 mips16_stub_call_address (mips_one_only_stub *stub)
1634 rtx fn = mips16_stub_function (stub->get_name ());
1635 SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_LOCAL;
1636 if (!call_insn_operand (fn, VOIDmode))
1637 fn = force_reg (Pmode, fn);
1641 /* A stub for moving the thread pointer into TLS_GET_TP_REGNUM. */
1643 class mips16_rdhwr_one_only_stub : public mips_one_only_stub
1645 virtual const char *get_name ();
1646 virtual void output_body ();
1650 mips16_rdhwr_one_only_stub::get_name ()
1652 return "__mips16_rdhwr";
1656 mips16_rdhwr_one_only_stub::output_body ()
1658 fprintf (asm_out_file,
1660 "\t.set\tmips32r2\n"
1661 "\t.set\tnoreorder\n"
1667 /* A stub for moving the FCSR into GET_FCSR_REGNUM. */
1668 class mips16_get_fcsr_one_only_stub : public mips_one_only_stub
1670 virtual const char *get_name ();
1671 virtual void output_body ();
1675 mips16_get_fcsr_one_only_stub::get_name ()
1677 return "__mips16_get_fcsr";
1681 mips16_get_fcsr_one_only_stub::output_body ()
1683 fprintf (asm_out_file,
1685 "\tj\t$31\n", reg_names[GET_FCSR_REGNUM]);
1688 /* A stub for moving SET_FCSR_REGNUM into the FCSR. */
1689 class mips16_set_fcsr_one_only_stub : public mips_one_only_stub
1691 virtual const char *get_name ();
1692 virtual void output_body ();
1696 mips16_set_fcsr_one_only_stub::get_name ()
1698 return "__mips16_set_fcsr";
1702 mips16_set_fcsr_one_only_stub::output_body ()
1704 fprintf (asm_out_file,
1706 "\tj\t$31\n", reg_names[SET_FCSR_REGNUM]);
1709 /* Return true if symbols of type TYPE require a GOT access. */
1712 mips_got_symbol_type_p (enum mips_symbol_type type)
1716 case SYMBOL_GOT_PAGE_OFST:
1717 case SYMBOL_GOT_DISP:
1725 /* Return true if X is a thread-local symbol. */
1728 mips_tls_symbol_p (rtx x)
1730 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1733 /* Return true if SYMBOL_REF X is associated with a global symbol
1734 (in the STB_GLOBAL sense). */
1737 mips_global_symbol_p (const_rtx x)
1739 const_tree decl = SYMBOL_REF_DECL (x);
1742 return !SYMBOL_REF_LOCAL_P (x) || SYMBOL_REF_EXTERNAL_P (x);
1744 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1745 or weak symbols. Relocations in the object file will be against
1746 the target symbol, so it's that symbol's binding that matters here. */
1747 return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl));
1750 /* Return true if function X is a libgcc MIPS16 stub function. */
1753 mips16_stub_function_p (const_rtx x)
1755 return (GET_CODE (x) == SYMBOL_REF
1756 && strncmp (XSTR (x, 0), "__mips16_", 9) == 0);
1759 /* Return true if function X is a locally-defined and locally-binding
1763 mips16_local_function_p (const_rtx x)
1765 return (GET_CODE (x) == SYMBOL_REF
1766 && SYMBOL_REF_LOCAL_P (x)
1767 && !SYMBOL_REF_EXTERNAL_P (x)
1768 && (mips_get_compress_mode (SYMBOL_REF_DECL (x)) & MASK_MIPS16));
1771 /* Return true if SYMBOL_REF X binds locally. */
1774 mips_symbol_binds_local_p (const_rtx x)
1776 return (SYMBOL_REF_DECL (x)
1777 ? targetm.binds_local_p (SYMBOL_REF_DECL (x))
1778 : SYMBOL_REF_LOCAL_P (x));
1781 /* Return true if rtx constants of mode MODE should be put into a small
1785 mips_rtx_constant_in_small_data_p (enum machine_mode mode)
1787 return (!TARGET_EMBEDDED_DATA
1788 && TARGET_LOCAL_SDATA
1789 && GET_MODE_SIZE (mode) <= mips_small_data_threshold);
1792 /* Return true if X should not be moved directly into register $25.
1793 We need this because many versions of GAS will treat "la $25,foo" as
1794 part of a call sequence and so allow a global "foo" to be lazily bound. */
1797 mips_dangerous_for_la25_p (rtx x)
1799 return (!TARGET_EXPLICIT_RELOCS
1801 && GET_CODE (x) == SYMBOL_REF
1802 && mips_global_symbol_p (x));
1805 /* Return true if calls to X might need $25 to be valid on entry. */
1808 mips_use_pic_fn_addr_reg_p (const_rtx x)
1810 if (!TARGET_USE_PIC_FN_ADDR_REG)
1813 /* MIPS16 stub functions are guaranteed not to use $25. */
1814 if (mips16_stub_function_p (x))
1817 if (GET_CODE (x) == SYMBOL_REF)
1819 /* If PLTs and copy relocations are available, the static linker
1820 will make sure that $25 is valid on entry to the target function. */
1821 if (TARGET_ABICALLS_PIC0)
1824 /* Locally-defined functions use absolute accesses to set up
1825 the global pointer. */
1826 if (TARGET_ABSOLUTE_ABICALLS
1827 && mips_symbol_binds_local_p (x)
1828 && !SYMBOL_REF_EXTERNAL_P (x))
1835 /* Return the method that should be used to access SYMBOL_REF or
1836 LABEL_REF X in context CONTEXT. */
1838 static enum mips_symbol_type
1839 mips_classify_symbol (const_rtx x, enum mips_symbol_context context)
1842 return SYMBOL_GOT_DISP;
1844 if (GET_CODE (x) == LABEL_REF)
1846 /* Only return SYMBOL_PC_RELATIVE if we are generating MIPS16
1847 code and if we know that the label is in the current function's
1848 text section. LABEL_REFs are used for jump tables as well as
1849 text labels, so we must check whether jump tables live in the
1851 if (TARGET_MIPS16_SHORT_JUMP_TABLES
1852 && !LABEL_REF_NONLOCAL_P (x))
1853 return SYMBOL_PC_RELATIVE;
1855 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1856 return SYMBOL_GOT_PAGE_OFST;
1858 return SYMBOL_ABSOLUTE;
1861 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1863 if (SYMBOL_REF_TLS_MODEL (x))
1866 if (CONSTANT_POOL_ADDRESS_P (x))
1868 if (TARGET_MIPS16_TEXT_LOADS)
1869 return SYMBOL_PC_RELATIVE;
1871 if (TARGET_MIPS16_PCREL_LOADS && context == SYMBOL_CONTEXT_MEM)
1872 return SYMBOL_PC_RELATIVE;
1874 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x)))
1875 return SYMBOL_GP_RELATIVE;
1878 /* Do not use small-data accesses for weak symbols; they may end up
1880 if (TARGET_GPOPT && SYMBOL_REF_SMALL_P (x) && !SYMBOL_REF_WEAK (x))
1881 return SYMBOL_GP_RELATIVE;
1883 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1885 if (TARGET_ABICALLS_PIC2
1886 && !(TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x)))
1888 /* There are three cases to consider:
1890 - o32 PIC (either with or without explicit relocs)
1891 - n32/n64 PIC without explicit relocs
1892 - n32/n64 PIC with explicit relocs
1894 In the first case, both local and global accesses will use an
1895 R_MIPS_GOT16 relocation. We must correctly predict which of
1896 the two semantics (local or global) the assembler and linker
1897 will apply. The choice depends on the symbol's binding rather
1898 than its visibility.
1900 In the second case, the assembler will not use R_MIPS_GOT16
1901 relocations, but it chooses between local and global accesses
1902 in the same way as for o32 PIC.
1904 In the third case we have more freedom since both forms of
1905 access will work for any kind of symbol. However, there seems
1906 little point in doing things differently. */
1907 if (mips_global_symbol_p (x))
1908 return SYMBOL_GOT_DISP;
1910 return SYMBOL_GOT_PAGE_OFST;
1913 return SYMBOL_ABSOLUTE;
1916 /* Classify the base of symbolic expression X, given that X appears in
1919 static enum mips_symbol_type
1920 mips_classify_symbolic_expression (rtx x, enum mips_symbol_context context)
1924 split_const (x, &x, &offset);
1925 if (UNSPEC_ADDRESS_P (x))
1926 return UNSPEC_ADDRESS_TYPE (x);
1928 return mips_classify_symbol (x, context);
1931 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1932 is the alignment in bytes of SYMBOL_REF X. */
1935 mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset)
1937 HOST_WIDE_INT align;
1939 align = SYMBOL_REF_DECL (x) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x)) : 1;
1940 return IN_RANGE (offset, 0, align - 1);
1943 /* Return true if X is a symbolic constant that can be used in context
1944 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1947 mips_symbolic_constant_p (rtx x, enum mips_symbol_context context,
1948 enum mips_symbol_type *symbol_type)
1952 split_const (x, &x, &offset);
1953 if (UNSPEC_ADDRESS_P (x))
1955 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1956 x = UNSPEC_ADDRESS (x);
1958 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1960 *symbol_type = mips_classify_symbol (x, context);
1961 if (*symbol_type == SYMBOL_TLS)
1967 if (offset == const0_rtx)
1970 /* Check whether a nonzero offset is valid for the underlying
1972 switch (*symbol_type)
1974 case SYMBOL_ABSOLUTE:
1975 case SYMBOL_64_HIGH:
1978 /* If the target has 64-bit pointers and the object file only
1979 supports 32-bit symbols, the values of those symbols will be
1980 sign-extended. In this case we can't allow an arbitrary offset
1981 in case the 32-bit value X + OFFSET has a different sign from X. */
1982 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1983 return offset_within_block_p (x, INTVAL (offset));
1985 /* In other cases the relocations can handle any offset. */
1988 case SYMBOL_PC_RELATIVE:
1989 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1990 In this case, we no longer have access to the underlying constant,
1991 but the original symbol-based access was known to be valid. */
1992 if (GET_CODE (x) == LABEL_REF)
1997 case SYMBOL_GP_RELATIVE:
1998 /* Make sure that the offset refers to something within the
1999 same object block. This should guarantee that the final
2000 PC- or GP-relative offset is within the 16-bit limit. */
2001 return offset_within_block_p (x, INTVAL (offset));
2003 case SYMBOL_GOT_PAGE_OFST:
2004 case SYMBOL_GOTOFF_PAGE:
2005 /* If the symbol is global, the GOT entry will contain the symbol's
2006 address, and we will apply a 16-bit offset after loading it.
2007 If the symbol is local, the linker should provide enough local
2008 GOT entries for a 16-bit offset, but larger offsets may lead
2010 return SMALL_INT (offset);
2014 /* There is no carry between the HI and LO REL relocations, so the
2015 offset is only valid if we know it won't lead to such a carry. */
2016 return mips_offset_within_alignment_p (x, INTVAL (offset));
2018 case SYMBOL_GOT_DISP:
2019 case SYMBOL_GOTOFF_DISP:
2020 case SYMBOL_GOTOFF_CALL:
2021 case SYMBOL_GOTOFF_LOADGP:
2024 case SYMBOL_GOTTPREL:
2032 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
2033 single instruction. We rely on the fact that, in the worst case,
2034 all instructions involved in a MIPS16 address calculation are usually
2038 mips_symbol_insns_1 (enum mips_symbol_type type, enum machine_mode mode)
2040 if (mips_use_pcrel_pool_p[(int) type])
2042 if (mode == MAX_MACHINE_MODE)
2043 /* LEAs will be converted into constant-pool references by
2045 type = SYMBOL_PC_RELATIVE;
2047 /* The constant must be loaded and then dereferenced. */
2053 case SYMBOL_ABSOLUTE:
2054 /* When using 64-bit symbols, we need 5 preparatory instructions,
2057 lui $at,%highest(symbol)
2058 daddiu $at,$at,%higher(symbol)
2060 daddiu $at,$at,%hi(symbol)
2063 The final address is then $at + %lo(symbol). With 32-bit
2064 symbols we just need a preparatory LUI for normal mode and
2065 a preparatory LI and SLL for MIPS16. */
2066 return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2;
2068 case SYMBOL_GP_RELATIVE:
2069 /* Treat GP-relative accesses as taking a single instruction on
2070 MIPS16 too; the copy of $gp can often be shared. */
2073 case SYMBOL_PC_RELATIVE:
2074 /* PC-relative constants can be only be used with ADDIUPC,
2075 DADDIUPC, LWPC and LDPC. */
2076 if (mode == MAX_MACHINE_MODE
2077 || GET_MODE_SIZE (mode) == 4
2078 || GET_MODE_SIZE (mode) == 8)
2081 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
2084 case SYMBOL_GOT_DISP:
2085 /* The constant will have to be loaded from the GOT before it
2086 is used in an address. */
2087 if (mode != MAX_MACHINE_MODE)
2092 case SYMBOL_GOT_PAGE_OFST:
2093 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
2094 local/global classification is accurate. The worst cases are:
2096 (1) For local symbols when generating o32 or o64 code. The assembler
2102 ...and the final address will be $at + %lo(symbol).
2104 (2) For global symbols when -mxgot. The assembler will use:
2106 lui $at,%got_hi(symbol)
2109 ...and the final address will be $at + %got_lo(symbol). */
2112 case SYMBOL_GOTOFF_PAGE:
2113 case SYMBOL_GOTOFF_DISP:
2114 case SYMBOL_GOTOFF_CALL:
2115 case SYMBOL_GOTOFF_LOADGP:
2116 case SYMBOL_64_HIGH:
2122 case SYMBOL_GOTTPREL:
2125 /* A 16-bit constant formed by a single relocation, or a 32-bit
2126 constant formed from a high 16-bit relocation and a low 16-bit
2127 relocation. Use mips_split_p to determine which. 32-bit
2128 constants need an "lui; addiu" sequence for normal mode and
2129 an "li; sll; addiu" sequence for MIPS16 mode. */
2130 return !mips_split_p[type] ? 1 : TARGET_MIPS16 ? 3 : 2;
2133 /* We don't treat a bare TLS symbol as a constant. */
2139 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
2140 to load symbols of type TYPE into a register. Return 0 if the given
2141 type of symbol cannot be used as an immediate operand.
2143 Otherwise, return the number of instructions needed to load or store
2144 values of mode MODE to or from addresses of type TYPE. Return 0 if
2145 the given type of symbol is not valid in addresses.
2147 In both cases, instruction counts are based off BASE_INSN_LENGTH. */
2150 mips_symbol_insns (enum mips_symbol_type type, enum machine_mode mode)
2152 return mips_symbol_insns_1 (type, mode) * (TARGET_MIPS16 ? 2 : 1);
2155 /* A for_each_rtx callback. Stop the search if *X references a
2156 thread-local symbol. */
2159 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
2161 return mips_tls_symbol_p (*x);
2164 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
2167 mips_cannot_force_const_mem (enum machine_mode mode, rtx x)
2169 enum mips_symbol_type type;
2172 /* There is no assembler syntax for expressing an address-sized
2174 if (GET_CODE (x) == HIGH)
2177 /* As an optimization, reject constants that mips_legitimize_move
2180 Suppose we have a multi-instruction sequence that loads constant C
2181 into register R. If R does not get allocated a hard register, and
2182 R is used in an operand that allows both registers and memory
2183 references, reload will consider forcing C into memory and using
2184 one of the instruction's memory alternatives. Returning false
2185 here will force it to use an input reload instead. */
2186 if (CONST_INT_P (x) && mips_legitimate_constant_p (mode, x))
2189 split_const (x, &base, &offset);
2190 if (mips_symbolic_constant_p (base, SYMBOL_CONTEXT_LEA, &type))
2192 /* See whether we explicitly want these symbols in the pool. */
2193 if (mips_use_pcrel_pool_p[(int) type])
2196 /* The same optimization as for CONST_INT. */
2197 if (SMALL_INT (offset) && mips_symbol_insns (type, MAX_MACHINE_MODE) > 0)
2200 /* If MIPS16 constant pools live in the text section, they should
2201 not refer to anything that might need run-time relocation. */
2202 if (TARGET_MIPS16_PCREL_LOADS && mips_got_symbol_type_p (type))
2206 /* TLS symbols must be computed by mips_legitimize_move. */
2207 if (for_each_rtx (&x, &mips_tls_symbol_ref_1, NULL))
2213 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
2214 constants when we're using a per-function constant pool. */
2217 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
2218 const_rtx x ATTRIBUTE_UNUSED)
2220 return !TARGET_MIPS16_PCREL_LOADS;
2223 /* Return true if register REGNO is a valid base register for mode MODE.
2224 STRICT_P is true if REG_OK_STRICT is in effect. */
2227 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode,
2230 if (!HARD_REGISTER_NUM_P (regno))
2234 regno = reg_renumber[regno];
2237 /* These fake registers will be eliminated to either the stack or
2238 hard frame pointer, both of which are usually valid base registers.
2239 Reload deals with the cases where the eliminated form isn't valid. */
2240 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
2243 /* In MIPS16 mode, the stack pointer can only address word and doubleword
2244 values, nothing smaller. There are two problems here:
2246 (a) Instantiating virtual registers can introduce new uses of the
2247 stack pointer. If these virtual registers are valid addresses,
2248 the stack pointer should be too.
2250 (b) Most uses of the stack pointer are not made explicit until
2251 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
2252 We don't know until that stage whether we'll be eliminating to the
2253 stack pointer (which needs the restriction) or the hard frame
2254 pointer (which doesn't).
2256 All in all, it seems more consistent to only enforce this restriction
2257 during and after reload. */
2258 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
2259 return !strict_p || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
2261 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
2264 /* Return true if X is a valid base register for mode MODE.
2265 STRICT_P is true if REG_OK_STRICT is in effect. */
2268 mips_valid_base_register_p (rtx x, enum machine_mode mode, bool strict_p)
2270 if (!strict_p && GET_CODE (x) == SUBREG)
2274 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p));
2277 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2278 can address a value of mode MODE. */
2281 mips_valid_offset_p (rtx x, enum machine_mode mode)
2283 /* Check that X is a signed 16-bit number. */
2284 if (!const_arith_operand (x, Pmode))
2287 /* We may need to split multiword moves, so make sure that every word
2289 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2290 && !SMALL_OPERAND (INTVAL (x) + GET_MODE_SIZE (mode) - UNITS_PER_WORD))
2296 /* Return true if a LO_SUM can address a value of mode MODE when the
2297 LO_SUM symbol has type SYMBOL_TYPE. */
2300 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type, enum machine_mode mode)
2302 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2304 if (mips_symbol_insns (symbol_type, mode) == 0)
2307 /* Check that there is a known low-part relocation. */
2308 if (mips_lo_relocs[symbol_type] == NULL)
2311 /* We may need to split multiword moves, so make sure that each word
2312 can be accessed without inducing a carry. This is mainly needed
2313 for o64, which has historically only guaranteed 64-bit alignment
2314 for 128-bit types. */
2315 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2316 && GET_MODE_BITSIZE (mode) > GET_MODE_ALIGNMENT (mode))
2322 /* Return true if X is a valid address for machine mode MODE. If it is,
2323 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2327 mips_classify_address (struct mips_address_info *info, rtx x,
2328 enum machine_mode mode, bool strict_p)
2330 switch (GET_CODE (x))
2334 info->type = ADDRESS_REG;
2336 info->offset = const0_rtx;
2337 return mips_valid_base_register_p (info->reg, mode, strict_p);
2340 info->type = ADDRESS_REG;
2341 info->reg = XEXP (x, 0);
2342 info->offset = XEXP (x, 1);
2343 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2344 && mips_valid_offset_p (info->offset, mode));
2347 info->type = ADDRESS_LO_SUM;
2348 info->reg = XEXP (x, 0);
2349 info->offset = XEXP (x, 1);
2350 /* We have to trust the creator of the LO_SUM to do something vaguely
2351 sane. Target-independent code that creates a LO_SUM should also
2352 create and verify the matching HIGH. Target-independent code that
2353 adds an offset to a LO_SUM must prove that the offset will not
2354 induce a carry. Failure to do either of these things would be
2355 a bug, and we are not required to check for it here. The MIPS
2356 backend itself should only create LO_SUMs for valid symbolic
2357 constants, with the high part being either a HIGH or a copy
2360 = mips_classify_symbolic_expression (info->offset, SYMBOL_CONTEXT_MEM);
2361 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2362 && mips_valid_lo_sum_p (info->symbol_type, mode));
2365 /* Small-integer addresses don't occur very often, but they
2366 are legitimate if $0 is a valid base register. */
2367 info->type = ADDRESS_CONST_INT;
2368 return !TARGET_MIPS16 && SMALL_INT (x);
2373 info->type = ADDRESS_SYMBOLIC;
2374 return (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_MEM,
2376 && mips_symbol_insns (info->symbol_type, mode) > 0
2377 && !mips_split_p[info->symbol_type]);
2384 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2387 mips_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
2389 struct mips_address_info addr;
2391 return mips_classify_address (&addr, x, mode, strict_p);
2394 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
2397 mips_stack_address_p (rtx x, enum machine_mode mode)
2399 struct mips_address_info addr;
2401 return (mips_classify_address (&addr, x, mode, false)
2402 && addr.type == ADDRESS_REG
2403 && addr.reg == stack_pointer_rtx);
2406 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2407 address instruction. Note that such addresses are not considered
2408 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2409 is so restricted. */
2412 mips_lwxs_address_p (rtx addr)
2415 && GET_CODE (addr) == PLUS
2416 && REG_P (XEXP (addr, 1)))
2418 rtx offset = XEXP (addr, 0);
2419 if (GET_CODE (offset) == MULT
2420 && REG_P (XEXP (offset, 0))
2421 && CONST_INT_P (XEXP (offset, 1))
2422 && INTVAL (XEXP (offset, 1)) == 4)
2428 /* Return true if ADDR matches the pattern for the L{B,H,W,D}{,U}X load
2429 indexed address instruction. Note that such addresses are
2430 not considered legitimate in the TARGET_LEGITIMATE_ADDRESS_P
2431 sense, because their use is so restricted. */
2434 mips_lx_address_p (rtx addr, enum machine_mode mode)
2436 if (GET_CODE (addr) != PLUS
2437 || !REG_P (XEXP (addr, 0))
2438 || !REG_P (XEXP (addr, 1)))
2440 if (ISA_HAS_LBX && mode == QImode)
2442 if (ISA_HAS_LHX && mode == HImode)
2444 if (ISA_HAS_LWX && mode == SImode)
2446 if (ISA_HAS_LDX && mode == DImode)
2451 /* Return true if a value at OFFSET bytes from base register BASE can be
2452 accessed using an unextended MIPS16 instruction. MODE is the mode of
2455 Usually the offset in an unextended instruction is a 5-bit field.
2456 The offset is unsigned and shifted left once for LH and SH, twice
2457 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2458 an 8-bit immediate field that's shifted left twice. */
2461 mips16_unextended_reference_p (enum machine_mode mode, rtx base,
2462 unsigned HOST_WIDE_INT offset)
2464 if (mode != BLKmode && offset % GET_MODE_SIZE (mode) == 0)
2466 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
2467 return offset < 256U * GET_MODE_SIZE (mode);
2468 return offset < 32U * GET_MODE_SIZE (mode);
2473 /* Return the number of instructions needed to load or store a value
2474 of mode MODE at address X, assuming that BASE_INSN_LENGTH is the
2475 length of one instruction. Return 0 if X isn't valid for MODE.
2476 Assume that multiword moves may need to be split into word moves
2477 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2481 mips_address_insns (rtx x, enum machine_mode mode, bool might_split_p)
2483 struct mips_address_info addr;
2486 /* BLKmode is used for single unaligned loads and stores and should
2487 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2488 meaningless, so we have to single it out as a special case one way
2490 if (mode != BLKmode && might_split_p)
2491 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2495 if (mips_classify_address (&addr, x, mode, false))
2500 && !mips16_unextended_reference_p (mode, addr.reg,
2501 UINTVAL (addr.offset)))
2505 case ADDRESS_LO_SUM:
2506 return TARGET_MIPS16 ? factor * 2 : factor;
2508 case ADDRESS_CONST_INT:
2511 case ADDRESS_SYMBOLIC:
2512 return factor * mips_symbol_insns (addr.symbol_type, mode);
2517 /* Return true if X fits within an unsigned field of BITS bits that is
2518 shifted left SHIFT bits before being used. */
2521 mips_unsigned_immediate_p (unsigned HOST_WIDE_INT x, int bits, int shift = 0)
2523 return (x & ((1 << shift) - 1)) == 0 && x < ((unsigned) 1 << (shift + bits));
2526 /* Return true if X fits within a signed field of BITS bits that is
2527 shifted left SHIFT bits before being used. */
2530 mips_signed_immediate_p (unsigned HOST_WIDE_INT x, int bits, int shift = 0)
2532 x += 1 << (bits + shift - 1);
2533 return mips_unsigned_immediate_p (x, bits, shift);
2536 /* Return true if X is legitimate for accessing values of mode MODE,
2537 if it is based on a MIPS16 register, and if the offset satisfies
2538 OFFSET_PREDICATE. */
2541 m16_based_address_p (rtx x, enum machine_mode mode,
2542 insn_operand_predicate_fn offset_predicate)
2544 struct mips_address_info addr;
2546 return (mips_classify_address (&addr, x, mode, false)
2547 && addr.type == ADDRESS_REG
2548 && M16_REG_P (REGNO (addr.reg))
2549 && offset_predicate (addr.offset, mode));
2552 /* Return true if X is a legitimate address that conforms to the requirements
2553 for a microMIPS LWSP or SWSP insn. */
2556 lwsp_swsp_address_p (rtx x, enum machine_mode mode)
2558 struct mips_address_info addr;
2560 return (mips_classify_address (&addr, x, mode, false)
2561 && addr.type == ADDRESS_REG
2562 && REGNO (addr.reg) == STACK_POINTER_REGNUM
2563 && uw5_operand (addr.offset, mode));
2566 /* Return true if X is a legitimate address with a 12-bit offset.
2567 MODE is the mode of the value being accessed. */
2570 umips_12bit_offset_address_p (rtx x, enum machine_mode mode)
2572 struct mips_address_info addr;
2574 return (mips_classify_address (&addr, x, mode, false)
2575 && addr.type == ADDRESS_REG
2576 && CONST_INT_P (addr.offset)
2577 && UMIPS_12BIT_OFFSET_P (INTVAL (addr.offset)));
2580 /* Return the number of instructions needed to load constant X,
2581 assuming that BASE_INSN_LENGTH is the length of one instruction.
2582 Return 0 if X isn't a valid constant. */
2585 mips_const_insns (rtx x)
2587 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2588 enum mips_symbol_type symbol_type;
2591 switch (GET_CODE (x))
2594 if (!mips_symbolic_constant_p (XEXP (x, 0), SYMBOL_CONTEXT_LEA,
2596 || !mips_split_p[symbol_type])
2599 /* This is simply an LUI for normal mode. It is an extended
2600 LI followed by an extended SLL for MIPS16. */
2601 return TARGET_MIPS16 ? 4 : 1;
2605 /* Unsigned 8-bit constants can be loaded using an unextended
2606 LI instruction. Unsigned 16-bit constants can be loaded
2607 using an extended LI. Negative constants must be loaded
2608 using LI and then negated. */
2609 return (IN_RANGE (INTVAL (x), 0, 255) ? 1
2610 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
2611 : IN_RANGE (-INTVAL (x), 0, 255) ? 2
2612 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
2615 return mips_build_integer (codes, INTVAL (x));
2619 /* Allow zeros for normal mode, where we can use $0. */
2620 return !TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0;
2626 /* See if we can refer to X directly. */
2627 if (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_LEA, &symbol_type))
2628 return mips_symbol_insns (symbol_type, MAX_MACHINE_MODE);
2630 /* Otherwise try splitting the constant into a base and offset.
2631 If the offset is a 16-bit value, we can load the base address
2632 into a register and then use (D)ADDIU to add in the offset.
2633 If the offset is larger, we can load the base and offset
2634 into separate registers and add them together with (D)ADDU.
2635 However, the latter is only possible before reload; during
2636 and after reload, we must have the option of forcing the
2637 constant into the pool instead. */
2638 split_const (x, &x, &offset);
2641 int n = mips_const_insns (x);
2644 if (SMALL_INT (offset))
2646 else if (!targetm.cannot_force_const_mem (GET_MODE (x), x))
2647 return n + 1 + mips_build_integer (codes, INTVAL (offset));
2654 return mips_symbol_insns (mips_classify_symbol (x, SYMBOL_CONTEXT_LEA),
2662 /* X is a doubleword constant that can be handled by splitting it into
2663 two words and loading each word separately. Return the number of
2664 instructions required to do this, assuming that BASE_INSN_LENGTH
2665 is the length of one instruction. */
2668 mips_split_const_insns (rtx x)
2670 unsigned int low, high;
2672 low = mips_const_insns (mips_subword (x, false));
2673 high = mips_const_insns (mips_subword (x, true));
2674 gcc_assert (low > 0 && high > 0);
2678 /* Return the number of instructions needed to implement INSN,
2679 given that it loads from or stores to MEM. Assume that
2680 BASE_INSN_LENGTH is the length of one instruction. */
2683 mips_load_store_insns (rtx mem, rtx insn)
2685 enum machine_mode mode;
2689 gcc_assert (MEM_P (mem));
2690 mode = GET_MODE (mem);
2692 /* Try to prove that INSN does not need to be split. */
2693 might_split_p = GET_MODE_SIZE (mode) > UNITS_PER_WORD;
2696 set = single_set (insn);
2697 if (set && !mips_split_move_insn_p (SET_DEST (set), SET_SRC (set), insn))
2698 might_split_p = false;
2701 return mips_address_insns (XEXP (mem, 0), mode, might_split_p);
2704 /* Return the number of instructions needed for an integer division,
2705 assuming that BASE_INSN_LENGTH is the length of one instruction. */
2708 mips_idiv_insns (void)
2713 if (TARGET_CHECK_ZERO_DIV)
2715 if (GENERATE_DIVIDE_TRAPS)
2721 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
2726 /* Emit a move from SRC to DEST. Assume that the move expanders can
2727 handle all moves if !can_create_pseudo_p (). The distinction is
2728 important because, unlike emit_move_insn, the move expanders know
2729 how to force Pmode objects into the constant pool even when the
2730 constant pool address is not itself legitimate. */
2733 mips_emit_move (rtx dest, rtx src)
2735 return (can_create_pseudo_p ()
2736 ? emit_move_insn (dest, src)
2737 : emit_move_insn_1 (dest, src));
2740 /* Emit a move from SRC to DEST, splitting compound moves into individual
2741 instructions. SPLIT_TYPE is the type of split to perform. */
2744 mips_emit_move_or_split (rtx dest, rtx src, enum mips_split_type split_type)
2746 if (mips_split_move_p (dest, src, split_type))
2747 mips_split_move (dest, src, split_type);
2749 mips_emit_move (dest, src);
2752 /* Emit an instruction of the form (set TARGET (CODE OP0)). */
2755 mips_emit_unary (enum rtx_code code, rtx target, rtx op0)
2757 emit_insn (gen_rtx_SET (VOIDmode, target,
2758 gen_rtx_fmt_e (code, GET_MODE (op0), op0)));
2761 /* Compute (CODE OP0) and store the result in a new register of mode MODE.
2762 Return that new register. */
2765 mips_force_unary (enum machine_mode mode, enum rtx_code code, rtx op0)
2769 reg = gen_reg_rtx (mode);
2770 mips_emit_unary (code, reg, op0);
2774 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2777 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
2779 emit_insn (gen_rtx_SET (VOIDmode, target,
2780 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
2783 /* Compute (CODE OP0 OP1) and store the result in a new register
2784 of mode MODE. Return that new register. */
2787 mips_force_binary (enum machine_mode mode, enum rtx_code code, rtx op0, rtx op1)
2791 reg = gen_reg_rtx (mode);
2792 mips_emit_binary (code, reg, op0, op1);
2796 /* Copy VALUE to a register and return that register. If new pseudos
2797 are allowed, copy it into a new register, otherwise use DEST. */
2800 mips_force_temporary (rtx dest, rtx value)
2802 if (can_create_pseudo_p ())
2803 return force_reg (Pmode, value);
2806 mips_emit_move (dest, value);
2811 /* Emit a call sequence with call pattern PATTERN and return the call
2812 instruction itself (which is not necessarily the last instruction
2813 emitted). ORIG_ADDR is the original, unlegitimized address,
2814 ADDR is the legitimized form, and LAZY_P is true if the call
2815 address is lazily-bound. */
2818 mips_emit_call_insn (rtx pattern, rtx orig_addr, rtx addr, bool lazy_p)
2822 insn = emit_call_insn (pattern);
2824 if (TARGET_MIPS16 && mips_use_pic_fn_addr_reg_p (orig_addr))
2826 /* MIPS16 JALRs only take MIPS16 registers. If the target
2827 function requires $25 to be valid on entry, we must copy it
2828 there separately. The move instruction can be put in the
2829 call's delay slot. */
2830 reg = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
2831 emit_insn_before (gen_move_insn (reg, addr), insn);
2832 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
2836 /* Lazy-binding stubs require $gp to be valid on entry. */
2837 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
2841 /* See the comment above load_call<mode> for details. */
2842 use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
2843 gen_rtx_REG (Pmode, GOT_VERSION_REGNUM));
2844 emit_insn (gen_update_got_version ());
2849 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2850 then add CONST_INT OFFSET to the result. */
2853 mips_unspec_address_offset (rtx base, rtx offset,
2854 enum mips_symbol_type symbol_type)
2856 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
2857 UNSPEC_ADDRESS_FIRST + symbol_type);
2858 if (offset != const0_rtx)
2859 base = gen_rtx_PLUS (Pmode, base, offset);
2860 return gen_rtx_CONST (Pmode, base);
2863 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2864 type SYMBOL_TYPE. */
2867 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
2871 split_const (address, &base, &offset);
2872 return mips_unspec_address_offset (base, offset, symbol_type);
2875 /* If OP is an UNSPEC address, return the address to which it refers,
2876 otherwise return OP itself. */
2879 mips_strip_unspec_address (rtx op)
2883 split_const (op, &base, &offset);
2884 if (UNSPEC_ADDRESS_P (base))
2885 op = plus_constant (Pmode, UNSPEC_ADDRESS (base), INTVAL (offset));
2889 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2890 high part to BASE and return the result. Just return BASE otherwise.
2891 TEMP is as for mips_force_temporary.
2893 The returned expression can be used as the first operand to a LO_SUM. */
2896 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
2897 enum mips_symbol_type symbol_type)
2899 if (mips_split_p[symbol_type])
2901 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
2902 addr = mips_force_temporary (temp, addr);
2903 base = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
2908 /* Return an instruction that copies $gp into register REG. We want
2909 GCC to treat the register's value as constant, so that its value
2910 can be rematerialized on demand. */
2913 gen_load_const_gp (rtx reg)
2915 return PMODE_INSN (gen_load_const_gp, (reg));
2918 /* Return a pseudo register that contains the value of $gp throughout
2919 the current function. Such registers are needed by MIPS16 functions,
2920 for which $gp itself is not a valid base register or addition operand. */
2923 mips16_gp_pseudo_reg (void)
2925 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
2929 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
2931 push_topmost_sequence ();
2933 scan = get_insns ();
2934 while (NEXT_INSN (scan) && !INSN_P (NEXT_INSN (scan)))
2935 scan = NEXT_INSN (scan);
2937 insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
2938 insn = emit_insn_after (insn, scan);
2939 INSN_LOCATION (insn) = 0;
2941 pop_topmost_sequence ();
2944 return cfun->machine->mips16_gp_pseudo_rtx;
2947 /* Return a base register that holds pic_offset_table_rtx.
2948 TEMP, if nonnull, is a scratch Pmode base register. */
2951 mips_pic_base_register (rtx temp)
2954 return pic_offset_table_rtx;
2956 if (currently_expanding_to_rtl)
2957 return mips16_gp_pseudo_reg ();
2959 if (can_create_pseudo_p ())
2960 temp = gen_reg_rtx (Pmode);
2963 /* The first post-reload split exposes all references to $gp
2964 (both uses and definitions). All references must remain
2965 explicit after that point.
2967 It is safe to introduce uses of $gp at any time, so for
2968 simplicity, we do that before the split too. */
2969 mips_emit_move (temp, pic_offset_table_rtx);
2971 emit_insn (gen_load_const_gp (temp));
2975 /* Return the RHS of a load_call<mode> insn. */
2978 mips_unspec_call (rtx reg, rtx symbol)
2982 vec = gen_rtvec (3, reg, symbol, gen_rtx_REG (SImode, GOT_VERSION_REGNUM));
2983 return gen_rtx_UNSPEC (Pmode, vec, UNSPEC_LOAD_CALL);
2986 /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol
2987 reference. Return NULL_RTX otherwise. */
2990 mips_strip_unspec_call (rtx src)
2992 if (GET_CODE (src) == UNSPEC && XINT (src, 1) == UNSPEC_LOAD_CALL)
2993 return mips_strip_unspec_address (XVECEXP (src, 0, 1));
2997 /* Create and return a GOT reference of type TYPE for address ADDR.
2998 TEMP, if nonnull, is a scratch Pmode base register. */
3001 mips_got_load (rtx temp, rtx addr, enum mips_symbol_type type)
3003 rtx base, high, lo_sum_symbol;
3005 base = mips_pic_base_register (temp);
3007 /* If we used the temporary register to load $gp, we can't use
3008 it for the high part as well. */
3009 if (temp != NULL && reg_overlap_mentioned_p (base, temp))
3012 high = mips_unspec_offset_high (temp, base, addr, type);
3013 lo_sum_symbol = mips_unspec_address (addr, type);
3015 if (type == SYMBOL_GOTOFF_CALL)
3016 return mips_unspec_call (high, lo_sum_symbol);
3018 return PMODE_INSN (gen_unspec_got, (high, lo_sum_symbol));
3021 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
3022 it appears in a MEM of that mode. Return true if ADDR is a legitimate
3023 constant in that context and can be split into high and low parts.
3024 If so, and if LOW_OUT is nonnull, emit the high part and store the
3025 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
3027 TEMP is as for mips_force_temporary and is used to load the high
3028 part into a register.
3030 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
3031 a legitimize SET_SRC for an .md pattern, otherwise the low part
3032 is guaranteed to be a legitimate address for mode MODE. */
3035 mips_split_symbol (rtx temp, rtx addr, enum machine_mode mode, rtx *low_out)
3037 enum mips_symbol_context context;
3038 enum mips_symbol_type symbol_type;
3041 context = (mode == MAX_MACHINE_MODE
3042 ? SYMBOL_CONTEXT_LEA
3043 : SYMBOL_CONTEXT_MEM);
3044 if (GET_CODE (addr) == HIGH && context == SYMBOL_CONTEXT_LEA)
3046 addr = XEXP (addr, 0);
3047 if (mips_symbolic_constant_p (addr, context, &symbol_type)
3048 && mips_symbol_insns (symbol_type, mode) > 0
3049 && mips_split_hi_p[symbol_type])
3052 switch (symbol_type)
3054 case SYMBOL_GOT_PAGE_OFST:
3055 /* The high part of a page/ofst pair is loaded from the GOT. */
3056 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_PAGE);
3067 if (mips_symbolic_constant_p (addr, context, &symbol_type)
3068 && mips_symbol_insns (symbol_type, mode) > 0
3069 && mips_split_p[symbol_type])
3072 switch (symbol_type)
3074 case SYMBOL_GOT_DISP:
3075 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
3076 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_DISP);
3079 case SYMBOL_GP_RELATIVE:
3080 high = mips_pic_base_register (temp);
3081 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
3085 high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
3086 high = mips_force_temporary (temp, high);
3087 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
3096 /* Return a legitimate address for REG + OFFSET. TEMP is as for
3097 mips_force_temporary; it is only needed when OFFSET is not a
3101 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
3103 if (!SMALL_OPERAND (offset))
3109 /* Load the full offset into a register so that we can use
3110 an unextended instruction for the address itself. */
3111 high = GEN_INT (offset);
3116 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
3117 The addition inside the macro CONST_HIGH_PART may cause an
3118 overflow, so we need to force a sign-extension check. */
3119 high = gen_int_mode (CONST_HIGH_PART (offset), Pmode);
3120 offset = CONST_LOW_PART (offset);
3122 high = mips_force_temporary (temp, high);
3123 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
3125 return plus_constant (Pmode, reg, offset);
3128 /* The __tls_get_attr symbol. */
3129 static GTY(()) rtx mips_tls_symbol;
3131 /* Return an instruction sequence that calls __tls_get_addr. SYM is
3132 the TLS symbol we are referencing and TYPE is the symbol type to use
3133 (either global dynamic or local dynamic). V0 is an RTX for the
3134 return value location. */
3137 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
3141 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
3143 if (!mips_tls_symbol)
3144 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
3146 loc = mips_unspec_address (sym, type);
3150 emit_insn (gen_rtx_SET (Pmode, a0,
3151 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
3152 insn = mips_expand_call (MIPS_CALL_NORMAL, v0, mips_tls_symbol,
3153 const0_rtx, NULL_RTX, false);
3154 RTL_CONST_CALL_P (insn) = 1;
3155 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
3156 insn = get_insns ();
3163 /* Return a pseudo register that contains the current thread pointer. */
3166 mips_expand_thread_pointer (rtx tp)
3172 if (!mips16_rdhwr_stub)
3173 mips16_rdhwr_stub = new mips16_rdhwr_one_only_stub ();
3174 fn = mips16_stub_call_address (mips16_rdhwr_stub);
3175 emit_insn (PMODE_INSN (gen_tls_get_tp_mips16, (tp, fn)));
3178 emit_insn (PMODE_INSN (gen_tls_get_tp, (tp)));
3185 return mips_expand_thread_pointer (gen_reg_rtx (Pmode));
3188 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
3189 its address. The return value will be both a valid address and a valid
3190 SET_SRC (either a REG or a LO_SUM). */
3193 mips_legitimize_tls_address (rtx loc)
3195 rtx dest, insn, v0, tp, tmp1, tmp2, eqv, offset;
3196 enum tls_model model;
3198 model = SYMBOL_REF_TLS_MODEL (loc);
3199 /* Only TARGET_ABICALLS code can have more than one module; other
3200 code must be be static and should not use a GOT. All TLS models
3201 reduce to local exec in this situation. */
3202 if (!TARGET_ABICALLS)
3203 model = TLS_MODEL_LOCAL_EXEC;
3207 case TLS_MODEL_GLOBAL_DYNAMIC:
3208 v0 = gen_rtx_REG (Pmode, GP_RETURN);
3209 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
3210 dest = gen_reg_rtx (Pmode);
3211 emit_libcall_block (insn, dest, v0, loc);
3214 case TLS_MODEL_LOCAL_DYNAMIC:
3215 v0 = gen_rtx_REG (Pmode, GP_RETURN);
3216 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
3217 tmp1 = gen_reg_rtx (Pmode);
3219 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
3220 share the LDM result with other LD model accesses. */
3221 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3223 emit_libcall_block (insn, tmp1, v0, eqv);
3225 offset = mips_unspec_address (loc, SYMBOL_DTPREL);
3226 if (mips_split_p[SYMBOL_DTPREL])
3228 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
3229 dest = gen_rtx_LO_SUM (Pmode, tmp2, offset);
3232 dest = expand_binop (Pmode, add_optab, tmp1, offset,
3233 0, 0, OPTAB_DIRECT);
3236 case TLS_MODEL_INITIAL_EXEC:
3237 tp = mips_get_tp ();
3238 tmp1 = gen_reg_rtx (Pmode);
3239 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
3240 if (Pmode == DImode)
3241 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
3243 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
3244 dest = gen_reg_rtx (Pmode);
3245 emit_insn (gen_add3_insn (dest, tmp1, tp));
3248 case TLS_MODEL_LOCAL_EXEC:
3249 tmp1 = mips_get_tp ();
3250 offset = mips_unspec_address (loc, SYMBOL_TPREL);
3251 if (mips_split_p[SYMBOL_TPREL])
3253 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_TPREL);
3254 dest = gen_rtx_LO_SUM (Pmode, tmp2, offset);
3257 dest = expand_binop (Pmode, add_optab, tmp1, offset,
3258 0, 0, OPTAB_DIRECT);
3267 /* Implement "TARGET = __builtin_mips_get_fcsr ()" for MIPS16,
3271 mips16_expand_get_fcsr (rtx target)
3273 if (!mips16_get_fcsr_stub)
3274 mips16_get_fcsr_stub = new mips16_get_fcsr_one_only_stub ();
3275 rtx fn = mips16_stub_call_address (mips16_get_fcsr_stub);
3276 emit_insn (PMODE_INSN (gen_mips_get_fcsr_mips16, (fn)));
3277 emit_move_insn (target, gen_rtx_REG (SImode, GET_FCSR_REGNUM));
3280 /* Implement __builtin_mips_set_fcsr (TARGET) for MIPS16, using a stub. */
3283 mips16_expand_set_fcsr (rtx newval)
3285 if (!mips16_set_fcsr_stub)
3286 mips16_set_fcsr_stub = new mips16_set_fcsr_one_only_stub ();
3287 rtx fn = mips16_stub_call_address (mips16_set_fcsr_stub);
3288 emit_move_insn (gen_rtx_REG (SImode, SET_FCSR_REGNUM), newval);
3289 emit_insn (PMODE_INSN (gen_mips_set_fcsr_mips16, (fn)));
3292 /* If X is not a valid address for mode MODE, force it into a register. */
3295 mips_force_address (rtx x, enum machine_mode mode)
3297 if (!mips_legitimate_address_p (mode, x, false))
3298 x = force_reg (Pmode, x);
3302 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
3303 be legitimized in a way that the generic machinery might not expect,
3304 return a new address, otherwise return NULL. MODE is the mode of
3305 the memory being accessed. */
3308 mips_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3309 enum machine_mode mode)
3312 HOST_WIDE_INT offset;
3314 if (mips_tls_symbol_p (x))
3315 return mips_legitimize_tls_address (x);
3317 /* See if the address can split into a high part and a LO_SUM. */
3318 if (mips_split_symbol (NULL, x, mode, &addr))
3319 return mips_force_address (addr, mode);
3321 /* Handle BASE + OFFSET using mips_add_offset. */
3322 mips_split_plus (x, &base, &offset);
3325 if (!mips_valid_base_register_p (base, mode, false))
3326 base = copy_to_mode_reg (Pmode, base);
3327 addr = mips_add_offset (NULL, base, offset);
3328 return mips_force_address (addr, mode);
3334 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
3337 mips_move_integer (rtx temp, rtx dest, unsigned HOST_WIDE_INT value)
3339 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
3340 enum machine_mode mode;
3341 unsigned int i, num_ops;
3344 mode = GET_MODE (dest);
3345 num_ops = mips_build_integer (codes, value);
3347 /* Apply each binary operation to X. Invariant: X is a legitimate
3348 source operand for a SET pattern. */
3349 x = GEN_INT (codes[0].value);
3350 for (i = 1; i < num_ops; i++)
3352 if (!can_create_pseudo_p ())
3354 emit_insn (gen_rtx_SET (VOIDmode, temp, x));
3358 x = force_reg (mode, x);
3359 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
3362 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
3365 /* Subroutine of mips_legitimize_move. Move constant SRC into register
3366 DEST given that SRC satisfies immediate_operand but doesn't satisfy
3370 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
3374 /* Split moves of big integers into smaller pieces. */
3375 if (splittable_const_int_operand (src, mode))
3377 mips_move_integer (dest, dest, INTVAL (src));
3381 /* Split moves of symbolic constants into high/low pairs. */
3382 if (mips_split_symbol (dest, src, MAX_MACHINE_MODE, &src))
3384 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
3388 /* Generate the appropriate access sequences for TLS symbols. */
3389 if (mips_tls_symbol_p (src))
3391 mips_emit_move (dest, mips_legitimize_tls_address (src));
3395 /* If we have (const (plus symbol offset)), and that expression cannot
3396 be forced into memory, load the symbol first and add in the offset.
3397 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
3398 forced into memory, as it usually produces better code. */
3399 split_const (src, &base, &offset);
3400 if (offset != const0_rtx
3401 && (targetm.cannot_force_const_mem (mode, src)
3402 || (!TARGET_MIPS16 && can_create_pseudo_p ())))
3404 base = mips_force_temporary (dest, base);
3405 mips_emit_move (dest, mips_add_offset (NULL, base, INTVAL (offset)));
3409 src = force_const_mem (mode, src);
3411 /* When using explicit relocs, constant pool references are sometimes
3412 not legitimate addresses. */
3413 mips_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0));
3414 mips_emit_move (dest, src);
3417 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
3418 sequence that is valid. */
3421 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
3423 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
3425 mips_emit_move (dest, force_reg (mode, src));
3429 /* We need to deal with constants that would be legitimate
3430 immediate_operands but aren't legitimate move_operands. */
3431 if (CONSTANT_P (src) && !move_operand (src, mode))
3433 mips_legitimize_const_move (mode, dest, src);
3434 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
3440 /* Return true if value X in context CONTEXT is a small-data address
3441 that can be rewritten as a LO_SUM. */
3444 mips_rewrite_small_data_p (rtx x, enum mips_symbol_context context)
3446 enum mips_symbol_type symbol_type;
3448 return (mips_lo_relocs[SYMBOL_GP_RELATIVE]
3449 && !mips_split_p[SYMBOL_GP_RELATIVE]
3450 && mips_symbolic_constant_p (x, context, &symbol_type)
3451 && symbol_type == SYMBOL_GP_RELATIVE);
3454 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
3455 containing MEM, or null if none. */
3458 mips_small_data_pattern_1 (rtx *loc, void *data)
3460 enum mips_symbol_context context;
3462 /* Ignore things like "g" constraints in asms. We make no particular
3463 guarantee about which symbolic constants are acceptable as asm operands
3464 versus which must be forced into a GPR. */
3465 if (GET_CODE (*loc) == LO_SUM || GET_CODE (*loc) == ASM_OPERANDS)
3470 if (for_each_rtx (&XEXP (*loc, 0), mips_small_data_pattern_1, *loc))
3475 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3476 return mips_rewrite_small_data_p (*loc, context);
3479 /* Return true if OP refers to small data symbols directly, not through
3483 mips_small_data_pattern_p (rtx op)
3485 return for_each_rtx (&op, mips_small_data_pattern_1, NULL);
3488 /* A for_each_rtx callback, used by mips_rewrite_small_data.
3489 DATA is the containing MEM, or null if none. */
3492 mips_rewrite_small_data_1 (rtx *loc, void *data)
3494 enum mips_symbol_context context;
3498 for_each_rtx (&XEXP (*loc, 0), mips_rewrite_small_data_1, *loc);
3502 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3503 if (mips_rewrite_small_data_p (*loc, context))
3504 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
3506 if (GET_CODE (*loc) == LO_SUM)
3512 /* Rewrite instruction pattern PATTERN so that it refers to small data
3513 using explicit relocations. */
3516 mips_rewrite_small_data (rtx pattern)
3518 pattern = copy_insn (pattern);
3519 for_each_rtx (&pattern, mips_rewrite_small_data_1, NULL);
3523 /* The cost of loading values from the constant pool. It should be
3524 larger than the cost of any constant we want to synthesize inline. */
3525 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3527 /* Return the cost of X when used as an operand to the MIPS16 instruction
3528 that implements CODE. Return -1 if there is no such instruction, or if
3529 X is not a valid immediate operand for it. */
3532 mips16_constant_cost (int code, HOST_WIDE_INT x)
3539 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3540 other shifts are extended. The shift patterns truncate the shift
3541 count to the right size, so there are no out-of-range values. */
3542 if (IN_RANGE (x, 1, 8))
3544 return COSTS_N_INSNS (1);
3547 if (IN_RANGE (x, -128, 127))
3549 if (SMALL_OPERAND (x))
3550 return COSTS_N_INSNS (1);
3554 /* Like LE, but reject the always-true case. */
3558 /* We add 1 to the immediate and use SLT. */
3561 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3564 if (IN_RANGE (x, 0, 255))
3566 if (SMALL_OPERAND_UNSIGNED (x))
3567 return COSTS_N_INSNS (1);
3572 /* Equality comparisons with 0 are cheap. */
3582 /* Return true if there is a non-MIPS16 instruction that implements CODE
3583 and if that instruction accepts X as an immediate operand. */
3586 mips_immediate_operand_p (int code, HOST_WIDE_INT x)
3593 /* All shift counts are truncated to a valid constant. */
3598 /* Likewise rotates, if the target supports rotates at all. */
3604 /* These instructions take 16-bit unsigned immediates. */
3605 return SMALL_OPERAND_UNSIGNED (x);
3610 /* These instructions take 16-bit signed immediates. */
3611 return SMALL_OPERAND (x);
3617 /* The "immediate" forms of these instructions are really
3618 implemented as comparisons with register 0. */
3623 /* Likewise, meaning that the only valid immediate operand is 1. */
3627 /* We add 1 to the immediate and use SLT. */
3628 return SMALL_OPERAND (x + 1);
3631 /* Likewise SLTU, but reject the always-true case. */
3632 return SMALL_OPERAND (x + 1) && x + 1 != 0;
3636 /* The bit position and size are immediate operands. */
3637 return ISA_HAS_EXT_INS;
3640 /* By default assume that $0 can be used for 0. */
3645 /* Return the cost of binary operation X, given that the instruction
3646 sequence for a word-sized or smaller operation has cost SINGLE_COST
3647 and that the sequence of a double-word operation has cost DOUBLE_COST.
3648 If SPEED is true, optimize for speed otherwise optimize for size. */
3651 mips_binary_cost (rtx x, int single_cost, int double_cost, bool speed)
3655 if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2)
3660 + set_src_cost (XEXP (x, 0), speed)
3661 + rtx_cost (XEXP (x, 1), GET_CODE (x), 1, speed));
3664 /* Return the cost of floating-point multiplications of mode MODE. */
3667 mips_fp_mult_cost (enum machine_mode mode)
3669 return mode == DFmode ? mips_cost->fp_mult_df : mips_cost->fp_mult_sf;
3672 /* Return the cost of floating-point divisions of mode MODE. */
3675 mips_fp_div_cost (enum machine_mode mode)
3677 return mode == DFmode ? mips_cost->fp_div_df : mips_cost->fp_div_sf;
3680 /* Return the cost of sign-extending OP to mode MODE, not including the
3681 cost of OP itself. */
3684 mips_sign_extend_cost (enum machine_mode mode, rtx op)
3687 /* Extended loads are as cheap as unextended ones. */
3690 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3691 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3694 if (ISA_HAS_SEB_SEH || GENERATE_MIPS16E)
3695 /* We can use SEB or SEH. */
3696 return COSTS_N_INSNS (1);
3698 /* We need to use a shift left and a shift right. */
3699 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3702 /* Return the cost of zero-extending OP to mode MODE, not including the
3703 cost of OP itself. */
3706 mips_zero_extend_cost (enum machine_mode mode, rtx op)
3709 /* Extended loads are as cheap as unextended ones. */
3712 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3713 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3714 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3716 if (GENERATE_MIPS16E)
3717 /* We can use ZEB or ZEH. */
3718 return COSTS_N_INSNS (1);
3721 /* We need to load 0xff or 0xffff into a register and use AND. */
3722 return COSTS_N_INSNS (GET_MODE (op) == QImode ? 2 : 3);
3724 /* We can use ANDI. */
3725 return COSTS_N_INSNS (1);
3728 /* Return the cost of moving between two registers of mode MODE,
3729 assuming that the move will be in pieces of at most UNITS bytes. */
3732 mips_set_reg_reg_piece_cost (enum machine_mode mode, unsigned int units)
3734 return COSTS_N_INSNS ((GET_MODE_SIZE (mode) + units - 1) / units);
3737 /* Return the cost of moving between two registers of mode MODE. */
3740 mips_set_reg_reg_cost (enum machine_mode mode)
3742 switch (GET_MODE_CLASS (mode))
3745 return mips_set_reg_reg_piece_cost (mode, GET_MODE_SIZE (CCmode));
3748 case MODE_COMPLEX_FLOAT:
3749 case MODE_VECTOR_FLOAT:
3750 if (TARGET_HARD_FLOAT)
3751 return mips_set_reg_reg_piece_cost (mode, UNITS_PER_HWFPVALUE);
3755 return mips_set_reg_reg_piece_cost (mode, UNITS_PER_WORD);
3759 /* Implement TARGET_RTX_COSTS. */
3762 mips_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
3763 int *total, bool speed)
3765 enum machine_mode mode = GET_MODE (x);
3766 bool float_mode_p = FLOAT_MODE_P (mode);
3770 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3771 appear in the instruction stream, and the cost of a comparison is
3772 really the cost of the branch or scc condition. At the time of
3773 writing, GCC only uses an explicit outer COMPARE code when optabs
3774 is testing whether a constant is expensive enough to force into a
3775 register. We want optabs to pass such constants through the MIPS
3776 expanders instead, so make all constants very cheap here. */
3777 if (outer_code == COMPARE)
3779 gcc_assert (CONSTANT_P (x));
3787 /* Treat *clear_upper32-style ANDs as having zero cost in the
3788 second operand. The cost is entirely in the first operand.
3790 ??? This is needed because we would otherwise try to CSE
3791 the constant operand. Although that's the right thing for
3792 instructions that continue to be a register operation throughout
3793 compilation, it is disastrous for instructions that could
3794 later be converted into a memory operation. */
3796 && outer_code == AND
3797 && UINTVAL (x) == 0xffffffff)
3805 cost = mips16_constant_cost (outer_code, INTVAL (x));
3814 /* When not optimizing for size, we care more about the cost
3815 of hot code, and hot code is often in a loop. If a constant
3816 operand needs to be forced into a register, we will often be
3817 able to hoist the constant load out of the loop, so the load
3818 should not contribute to the cost. */
3819 if (speed || mips_immediate_operand_p (outer_code, INTVAL (x)))
3831 if (force_to_mem_operand (x, VOIDmode))
3833 *total = COSTS_N_INSNS (1);
3836 cost = mips_const_insns (x);
3839 /* If the constant is likely to be stored in a GPR, SETs of
3840 single-insn constants are as cheap as register sets; we
3841 never want to CSE them.
3843 Don't reduce the cost of storing a floating-point zero in
3844 FPRs. If we have a zero in an FPR for other reasons, we
3845 can get better cfg-cleanup and delayed-branch results by
3846 using it consistently, rather than using $0 sometimes and
3847 an FPR at other times. Also, moves between floating-point
3848 registers are sometimes cheaper than (D)MTC1 $0. */
3850 && outer_code == SET
3851 && !(float_mode_p && TARGET_HARD_FLOAT))
3853 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3854 want to CSE the constant itself. It is usually better to
3855 have N copies of the last operation in the sequence and one
3856 shared copy of the other operations. (Note that this is
3857 not true for MIPS16 code, where the final operation in the
3858 sequence is often an extended instruction.)
3860 Also, if we have a CONST_INT, we don't know whether it is
3861 for a word or doubleword operation, so we cannot rely on
3862 the result of mips_build_integer. */
3863 else if (!TARGET_MIPS16
3864 && (outer_code == SET || mode == VOIDmode))
3866 *total = COSTS_N_INSNS (cost);
3869 /* The value will need to be fetched from the constant pool. */
3870 *total = CONSTANT_POOL_COST;
3874 /* If the address is legitimate, return the number of
3875 instructions it needs. */
3877 cost = mips_address_insns (addr, mode, true);
3880 *total = COSTS_N_INSNS (cost + 1);
3883 /* Check for a scaled indexed address. */
3884 if (mips_lwxs_address_p (addr)
3885 || mips_lx_address_p (addr, mode))
3887 *total = COSTS_N_INSNS (2);
3890 /* Otherwise use the default handling. */
3894 *total = COSTS_N_INSNS (6);
3898 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1);
3902 /* Check for a *clear_upper32 pattern and treat it like a zero
3903 extension. See the pattern's comment for details. */
3906 && CONST_INT_P (XEXP (x, 1))
3907 && UINTVAL (XEXP (x, 1)) == 0xffffffff)
3909 *total = (mips_zero_extend_cost (mode, XEXP (x, 0))
3910 + set_src_cost (XEXP (x, 0), speed));
3913 if (ISA_HAS_CINS && CONST_INT_P (XEXP (x, 1)))
3915 rtx op = XEXP (x, 0);
3916 if (GET_CODE (op) == ASHIFT
3917 && CONST_INT_P (XEXP (op, 1))
3918 && mask_low_and_shift_p (mode, XEXP (x, 1), XEXP (op, 1), 32))
3920 *total = COSTS_N_INSNS (1) + set_src_cost (XEXP (op, 0), speed);
3924 /* (AND (NOT op0) (NOT op1) is a nor operation that can be done in
3925 a single instruction. */
3927 && GET_CODE (XEXP (x, 0)) == NOT
3928 && GET_CODE (XEXP (x, 1)) == NOT)
3930 cost = GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1;
3931 *total = (COSTS_N_INSNS (cost)
3932 + set_src_cost (XEXP (XEXP (x, 0), 0), speed)
3933 + set_src_cost (XEXP (XEXP (x, 1), 0), speed));
3941 /* Double-word operations use two single-word operations. */
3942 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (2),
3951 if (CONSTANT_P (XEXP (x, 1)))
3952 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3955 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (12),
3961 *total = mips_cost->fp_add;
3963 *total = COSTS_N_INSNS (4);
3967 /* Low-part immediates need an extended MIPS16 instruction. */
3968 *total = (COSTS_N_INSNS (TARGET_MIPS16 ? 2 : 1)
3969 + set_src_cost (XEXP (x, 0), speed));
3984 /* Branch comparisons have VOIDmode, so use the first operand's
3986 mode = GET_MODE (XEXP (x, 0));
3987 if (FLOAT_MODE_P (mode))
3989 *total = mips_cost->fp_add;
3992 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3998 && (ISA_HAS_NMADD4_NMSUB4 || ISA_HAS_NMADD3_NMSUB3)
3999 && TARGET_FUSED_MADD
4000 && !HONOR_NANS (mode)
4001 && !HONOR_SIGNED_ZEROS (mode))
4003 /* See if we can use NMADD or NMSUB. See mips.md for the
4004 associated patterns. */
4005 rtx op0 = XEXP (x, 0);
4006 rtx op1 = XEXP (x, 1);
4007 if (GET_CODE (op0) == MULT && GET_CODE (XEXP (op0, 0)) == NEG)
4009 *total = (mips_fp_mult_cost (mode)
4010 + set_src_cost (XEXP (XEXP (op0, 0), 0), speed)
4011 + set_src_cost (XEXP (op0, 1), speed)
4012 + set_src_cost (op1, speed));
4015 if (GET_CODE (op1) == MULT)
4017 *total = (mips_fp_mult_cost (mode)
4018 + set_src_cost (op0, speed)
4019 + set_src_cost (XEXP (op1, 0), speed)
4020 + set_src_cost (XEXP (op1, 1), speed));
4029 /* If this is part of a MADD or MSUB, treat the PLUS as
4031 if ((ISA_HAS_FP_MADD4_MSUB4 || ISA_HAS_FP_MADD3_MSUB3)
4032 && TARGET_FUSED_MADD
4033 && GET_CODE (XEXP (x, 0)) == MULT)
4036 *total = mips_cost->fp_add;
4040 /* Double-word operations require three single-word operations and
4041 an SLTU. The MIPS16 version then needs to move the result of
4042 the SLTU from $24 to a MIPS16 register. */
4043 *total = mips_binary_cost (x, COSTS_N_INSNS (1),
4044 COSTS_N_INSNS (TARGET_MIPS16 ? 5 : 4),
4050 && (ISA_HAS_NMADD4_NMSUB4 || ISA_HAS_NMADD3_NMSUB3)
4051 && TARGET_FUSED_MADD
4052 && !HONOR_NANS (mode)
4053 && HONOR_SIGNED_ZEROS (mode))
4055 /* See if we can use NMADD or NMSUB. See mips.md for the
4056 associated patterns. */
4057 rtx op = XEXP (x, 0);
4058 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
4059 && GET_CODE (XEXP (op, 0)) == MULT)
4061 *total = (mips_fp_mult_cost (mode)
4062 + set_src_cost (XEXP (XEXP (op, 0), 0), speed)
4063 + set_src_cost (XEXP (XEXP (op, 0), 1), speed)
4064 + set_src_cost (XEXP (op, 1), speed));
4070 *total = mips_cost->fp_add;
4072 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1);
4077 *total = mips_fp_mult_cost (mode);
4078 else if (mode == DImode && !TARGET_64BIT)
4079 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
4080 where the mulsidi3 always includes an MFHI and an MFLO. */
4082 ? mips_cost->int_mult_si * 3 + 6
4083 : COSTS_N_INSNS (ISA_HAS_MUL3 ? 7 : 9));
4085 *total = COSTS_N_INSNS (ISA_HAS_MUL3 ? 1 : 2) + 1;
4086 else if (mode == DImode)
4087 *total = mips_cost->int_mult_di;
4089 *total = mips_cost->int_mult_si;
4093 /* Check for a reciprocal. */
4095 && ISA_HAS_FP_RECIP_RSQRT (mode)
4096 && flag_unsafe_math_optimizations
4097 && XEXP (x, 0) == CONST1_RTX (mode))
4099 if (outer_code == SQRT || GET_CODE (XEXP (x, 1)) == SQRT)
4100 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
4101 division as being free. */
4102 *total = set_src_cost (XEXP (x, 1), speed);
4104 *total = (mips_fp_div_cost (mode)
4105 + set_src_cost (XEXP (x, 1), speed));
4114 *total = mips_fp_div_cost (mode);
4123 /* It is our responsibility to make division by a power of 2
4124 as cheap as 2 register additions if we want the division
4125 expanders to be used for such operations; see the setting
4126 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
4127 should always produce shorter code than using
4128 expand_sdiv2_pow2. */
4130 && CONST_INT_P (XEXP (x, 1))
4131 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
4133 *total = COSTS_N_INSNS (2) + set_src_cost (XEXP (x, 0), speed);
4136 *total = COSTS_N_INSNS (mips_idiv_insns ());
4138 else if (mode == DImode)
4139 *total = mips_cost->int_div_di;
4141 *total = mips_cost->int_div_si;
4145 *total = mips_sign_extend_cost (mode, XEXP (x, 0));
4149 if (outer_code == SET
4151 && (GET_CODE (XEXP (x, 0)) == TRUNCATE
4152 || GET_CODE (XEXP (x, 0)) == SUBREG)
4153 && GET_MODE (XEXP (x, 0)) == QImode
4154 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
4156 *total = set_src_cost (XEXP (XEXP (x, 0), 0), speed);
4159 *total = mips_zero_extend_cost (mode, XEXP (x, 0));
4163 case UNSIGNED_FLOAT:
4166 case FLOAT_TRUNCATE:
4167 *total = mips_cost->fp_add;
4171 if (register_operand (SET_DEST (x), VOIDmode)
4172 && reg_or_0_operand (SET_SRC (x), VOIDmode))
4174 *total = mips_set_reg_reg_cost (GET_MODE (SET_DEST (x)));
4184 /* Implement TARGET_ADDRESS_COST. */
4187 mips_address_cost (rtx addr, enum machine_mode mode,
4188 addr_space_t as ATTRIBUTE_UNUSED,
4189 bool speed ATTRIBUTE_UNUSED)
4191 return mips_address_insns (addr, mode, false);
4194 /* Information about a single instruction in a multi-instruction
4196 struct mips_multi_member {
4197 /* True if this is a label, false if it is code. */
4200 /* The output_asm_insn format of the instruction. */
4203 /* The operands to the instruction. */
4204 rtx operands[MAX_RECOG_OPERANDS];
4206 typedef struct mips_multi_member mips_multi_member;
4208 /* The instructions that make up the current multi-insn sequence. */
4209 static vec<mips_multi_member> mips_multi_members;
4211 /* How many instructions (as opposed to labels) are in the current
4212 multi-insn sequence. */
4213 static unsigned int mips_multi_num_insns;
4215 /* Start a new multi-insn sequence. */
4218 mips_multi_start (void)
4220 mips_multi_members.truncate (0);
4221 mips_multi_num_insns = 0;
4224 /* Add a new, uninitialized member to the current multi-insn sequence. */
4226 static struct mips_multi_member *
4227 mips_multi_add (void)
4229 mips_multi_member empty;
4230 return mips_multi_members.safe_push (empty);
4233 /* Add a normal insn with the given asm format to the current multi-insn
4234 sequence. The other arguments are a null-terminated list of operands. */
4237 mips_multi_add_insn (const char *format, ...)
4239 struct mips_multi_member *member;
4244 member = mips_multi_add ();
4245 member->is_label_p = false;
4246 member->format = format;
4247 va_start (ap, format);
4249 while ((op = va_arg (ap, rtx)))
4250 member->operands[i++] = op;
4252 mips_multi_num_insns++;
4255 /* Add the given label definition to the current multi-insn sequence.
4256 The definition should include the colon. */
4259 mips_multi_add_label (const char *label)
4261 struct mips_multi_member *member;
4263 member = mips_multi_add ();
4264 member->is_label_p = true;
4265 member->format = label;
4268 /* Return the index of the last member of the current multi-insn sequence. */
4271 mips_multi_last_index (void)
4273 return mips_multi_members.length () - 1;
4276 /* Add a copy of an existing instruction to the current multi-insn
4277 sequence. I is the index of the instruction that should be copied. */
4280 mips_multi_copy_insn (unsigned int i)
4282 struct mips_multi_member *member;
4284 member = mips_multi_add ();
4285 memcpy (member, &mips_multi_members[i], sizeof (*member));
4286 gcc_assert (!member->is_label_p);
4289 /* Change the operand of an existing instruction in the current
4290 multi-insn sequence. I is the index of the instruction,
4291 OP is the index of the operand, and X is the new value. */
4294 mips_multi_set_operand (unsigned int i, unsigned int op, rtx x)
4296 mips_multi_members[i].operands[op] = x;
4299 /* Write out the asm code for the current multi-insn sequence. */
4302 mips_multi_write (void)
4304 struct mips_multi_member *member;
4307 FOR_EACH_VEC_ELT (mips_multi_members, i, member)
4308 if (member->is_label_p)
4309 fprintf (asm_out_file, "%s\n", member->format);
4311 output_asm_insn (member->format, member->operands);
4314 /* Return one word of double-word value OP, taking into account the fixed
4315 endianness of certain registers. HIGH_P is true to select the high part,
4316 false to select the low part. */
4319 mips_subword (rtx op, bool high_p)
4321 unsigned int byte, offset;
4322 enum machine_mode mode;
4324 mode = GET_MODE (op);
4325 if (mode == VOIDmode)
4326 mode = TARGET_64BIT ? TImode : DImode;
4328 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
4329 byte = UNITS_PER_WORD;
4333 if (FP_REG_RTX_P (op))
4335 /* Paired FPRs are always ordered little-endian. */
4336 offset = (UNITS_PER_WORD < UNITS_PER_HWFPVALUE ? high_p : byte != 0);
4337 return gen_rtx_REG (word_mode, REGNO (op) + offset);
4341 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
4343 return simplify_gen_subreg (word_mode, op, mode, byte);
4346 /* Return true if SRC should be moved into DEST using "MULT $0, $0".
4347 SPLIT_TYPE is the condition under which moves should be split. */
4350 mips_mult_move_p (rtx dest, rtx src, enum mips_split_type split_type)
4352 return ((split_type != SPLIT_FOR_SPEED
4353 || mips_tuning_info.fast_mult_zero_zero_p)
4354 && src == const0_rtx
4356 && GET_MODE_SIZE (GET_MODE (dest)) == 2 * UNITS_PER_WORD
4357 && (ISA_HAS_DSP_MULT
4358 ? ACC_REG_P (REGNO (dest))
4359 : MD_REG_P (REGNO (dest))));
4362 /* Return true if a move from SRC to DEST should be split into two.
4363 SPLIT_TYPE describes the split condition. */
4366 mips_split_move_p (rtx dest, rtx src, enum mips_split_type split_type)
4368 /* Check whether the move can be done using some variant of MULT $0,$0. */
4369 if (mips_mult_move_p (dest, src, split_type))
4372 /* FPR-to-FPR moves can be done in a single instruction, if they're
4374 unsigned int size = GET_MODE_SIZE (GET_MODE (dest));
4375 if (size == 8 && FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
4378 /* Check for floating-point loads and stores. */
4379 if (size == 8 && ISA_HAS_LDC1_SDC1)
4381 if (FP_REG_RTX_P (dest) && MEM_P (src))
4383 if (FP_REG_RTX_P (src) && MEM_P (dest))
4387 /* Otherwise split all multiword moves. */
4388 return size > UNITS_PER_WORD;
4391 /* Split a move from SRC to DEST, given that mips_split_move_p holds.
4392 SPLIT_TYPE describes the split condition. */
4395 mips_split_move (rtx dest, rtx src, enum mips_split_type split_type)
4399 gcc_checking_assert (mips_split_move_p (dest, src, split_type));
4400 if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src))
4402 if (!TARGET_64BIT && GET_MODE (dest) == DImode)
4403 emit_insn (gen_move_doubleword_fprdi (dest, src));
4404 else if (!TARGET_64BIT && GET_MODE (dest) == DFmode)
4405 emit_insn (gen_move_doubleword_fprdf (dest, src));
4406 else if (!TARGET_64BIT && GET_MODE (dest) == V2SFmode)
4407 emit_insn (gen_move_doubleword_fprv2sf (dest, src));
4408 else if (!TARGET_64BIT && GET_MODE (dest) == V2SImode)
4409 emit_insn (gen_move_doubleword_fprv2si (dest, src));
4410 else if (!TARGET_64BIT && GET_MODE (dest) == V4HImode)
4411 emit_insn (gen_move_doubleword_fprv4hi (dest, src));
4412 else if (!TARGET_64BIT && GET_MODE (dest) == V8QImode)
4413 emit_insn (gen_move_doubleword_fprv8qi (dest, src));
4414 else if (TARGET_64BIT && GET_MODE (dest) == TFmode)
4415 emit_insn (gen_move_doubleword_fprtf (dest, src));
4419 else if (REG_P (dest) && REGNO (dest) == MD_REG_FIRST)
4421 low_dest = mips_subword (dest, false);
4422 mips_emit_move (low_dest, mips_subword (src, false));
4424 emit_insn (gen_mthidi_ti (dest, mips_subword (src, true), low_dest));
4426 emit_insn (gen_mthisi_di (dest, mips_subword (src, true), low_dest));
4428 else if (REG_P (src) && REGNO (src) == MD_REG_FIRST)
4430 mips_emit_move (mips_subword (dest, false), mips_subword (src, false));
4432 emit_insn (gen_mfhidi_ti (mips_subword (dest, true), src));
4434 emit_insn (gen_mfhisi_di (mips_subword (dest, true), src));
4438 /* The operation can be split into two normal moves. Decide in
4439 which order to do them. */
4440 low_dest = mips_subword (dest, false);
4441 if (REG_P (low_dest)
4442 && reg_overlap_mentioned_p (low_dest, src))
4444 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4445 mips_emit_move (low_dest, mips_subword (src, false));
4449 mips_emit_move (low_dest, mips_subword (src, false));
4450 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4455 /* Return the split type for instruction INSN. */
4457 static enum mips_split_type
4458 mips_insn_split_type (rtx insn)
4460 basic_block bb = BLOCK_FOR_INSN (insn);
4463 if (optimize_bb_for_speed_p (bb))
4464 return SPLIT_FOR_SPEED;
4466 return SPLIT_FOR_SIZE;
4468 /* Once CFG information has been removed, we should trust the optimization
4469 decisions made by previous passes and only split where necessary. */
4470 return SPLIT_IF_NECESSARY;
4473 /* Return true if a move from SRC to DEST in INSN should be split. */
4476 mips_split_move_insn_p (rtx dest, rtx src, rtx insn)
4478 return mips_split_move_p (dest, src, mips_insn_split_type (insn));
4481 /* Split a move from SRC to DEST in INSN, given that mips_split_move_insn_p
4485 mips_split_move_insn (rtx dest, rtx src, rtx insn)
4487 mips_split_move (dest, src, mips_insn_split_type (insn));
4490 /* Return the appropriate instructions to move SRC into DEST. Assume
4491 that SRC is operand 1 and DEST is operand 0. */
4494 mips_output_move (rtx dest, rtx src)
4496 enum rtx_code dest_code, src_code;
4497 enum machine_mode mode;
4498 enum mips_symbol_type symbol_type;
4501 dest_code = GET_CODE (dest);
4502 src_code = GET_CODE (src);
4503 mode = GET_MODE (dest);
4504 dbl_p = (GET_MODE_SIZE (mode) == 8);
4506 if (mips_split_move_p (dest, src, SPLIT_IF_NECESSARY))
4509 if ((src_code == REG && GP_REG_P (REGNO (src)))
4510 || (!TARGET_MIPS16 && src == CONST0_RTX (mode)))
4512 if (dest_code == REG)
4514 if (GP_REG_P (REGNO (dest)))
4515 return "move\t%0,%z1";
4517 if (mips_mult_move_p (dest, src, SPLIT_IF_NECESSARY))
4519 if (ISA_HAS_DSP_MULT)
4520 return "mult\t%q0,%.,%.";
4522 return "mult\t%.,%.";
4525 /* Moves to HI are handled by special .md insns. */
4526 if (REGNO (dest) == LO_REGNUM)
4529 if (DSP_ACC_REG_P (REGNO (dest)))
4531 static char retval[] = "mt__\t%z1,%q0";
4533 retval[2] = reg_names[REGNO (dest)][4];
4534 retval[3] = reg_names[REGNO (dest)][5];
4538 if (FP_REG_P (REGNO (dest)))
4539 return dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
4541 if (ALL_COP_REG_P (REGNO (dest)))
4543 static char retval[] = "dmtc_\t%z1,%0";
4545 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4546 return dbl_p ? retval : retval + 1;
4549 if (dest_code == MEM)
4550 switch (GET_MODE_SIZE (mode))
4552 case 1: return "sb\t%z1,%0";
4553 case 2: return "sh\t%z1,%0";
4554 case 4: return "sw\t%z1,%0";
4555 case 8: return "sd\t%z1,%0";
4558 if (dest_code == REG && GP_REG_P (REGNO (dest)))
4560 if (src_code == REG)
4562 /* Moves from HI are handled by special .md insns. */
4563 if (REGNO (src) == LO_REGNUM)
4565 /* When generating VR4120 or VR4130 code, we use MACC and
4566 DMACC instead of MFLO. This avoids both the normal
4567 MIPS III HI/LO hazards and the errata related to
4570 return dbl_p ? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
4574 if (DSP_ACC_REG_P (REGNO (src)))
4576 static char retval[] = "mf__\t%0,%q1";
4578 retval[2] = reg_names[REGNO (src)][4];
4579 retval[3] = reg_names[REGNO (src)][5];
4583 if (FP_REG_P (REGNO (src)))
4584 return dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
4586 if (ALL_COP_REG_P (REGNO (src)))
4588 static char retval[] = "dmfc_\t%0,%1";
4590 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4591 return dbl_p ? retval : retval + 1;
4595 if (src_code == MEM)
4596 switch (GET_MODE_SIZE (mode))
4598 case 1: return "lbu\t%0,%1";
4599 case 2: return "lhu\t%0,%1";
4600 case 4: return "lw\t%0,%1";
4601 case 8: return "ld\t%0,%1";
4604 if (src_code == CONST_INT)
4606 /* Don't use the X format for the operand itself, because that
4607 will give out-of-range numbers for 64-bit hosts and 32-bit
4610 return "li\t%0,%1\t\t\t# %X1";
4612 if (SMALL_OPERAND_UNSIGNED (INTVAL (src)))
4615 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src)))
4619 if (src_code == HIGH)
4620 return TARGET_MIPS16 ? "#" : "lui\t%0,%h1";
4622 if (CONST_GP_P (src))
4623 return "move\t%0,%1";
4625 if (mips_symbolic_constant_p (src, SYMBOL_CONTEXT_LEA, &symbol_type)
4626 && mips_lo_relocs[symbol_type] != 0)
4628 /* A signed 16-bit constant formed by applying a relocation
4629 operator to a symbolic address. */
4630 gcc_assert (!mips_split_p[symbol_type]);
4631 return "li\t%0,%R1";
4634 if (symbolic_operand (src, VOIDmode))
4636 gcc_assert (TARGET_MIPS16
4637 ? TARGET_MIPS16_TEXT_LOADS
4638 : !TARGET_EXPLICIT_RELOCS);
4639 return dbl_p ? "dla\t%0,%1" : "la\t%0,%1";
4642 if (src_code == REG && FP_REG_P (REGNO (src)))
4644 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4646 if (GET_MODE (dest) == V2SFmode)
4647 return "mov.ps\t%0,%1";
4649 return dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1";
4652 if (dest_code == MEM)
4653 return dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0";
4655 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4657 if (src_code == MEM)
4658 return dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1";
4660 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
4662 static char retval[] = "l_c_\t%0,%1";
4664 retval[1] = (dbl_p ? 'd' : 'w');
4665 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4668 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
4670 static char retval[] = "s_c_\t%1,%0";
4672 retval[1] = (dbl_p ? 'd' : 'w');
4673 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4679 /* Return true if CMP1 is a suitable second operand for integer ordering
4680 test CODE. See also the *sCC patterns in mips.md. */
4683 mips_int_order_operand_ok_p (enum rtx_code code, rtx cmp1)
4689 return reg_or_0_operand (cmp1, VOIDmode);
4693 return !TARGET_MIPS16 && cmp1 == const1_rtx;
4697 return arith_operand (cmp1, VOIDmode);
4700 return sle_operand (cmp1, VOIDmode);
4703 return sleu_operand (cmp1, VOIDmode);
4710 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4711 integer ordering test *CODE, or if an equivalent combination can
4712 be formed by adjusting *CODE and *CMP1. When returning true, update
4713 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4717 mips_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1,
4718 enum machine_mode mode)
4720 HOST_WIDE_INT plus_one;
4722 if (mips_int_order_operand_ok_p (*code, *cmp1))
4725 if (CONST_INT_P (*cmp1))
4729 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4730 if (INTVAL (*cmp1) < plus_one)
4733 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4739 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4743 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4754 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4755 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4756 is nonnull, it's OK to set TARGET to the inverse of the result and
4757 flip *INVERT_PTR instead. */
4760 mips_emit_int_order_test (enum rtx_code code, bool *invert_ptr,
4761 rtx target, rtx cmp0, rtx cmp1)
4763 enum machine_mode mode;
4765 /* First see if there is a MIPS instruction that can do this operation.
4766 If not, try doing the same for the inverse operation. If that also
4767 fails, force CMP1 into a register and try again. */
4768 mode = GET_MODE (cmp0);
4769 if (mips_canonicalize_int_order_test (&code, &cmp1, mode))
4770 mips_emit_binary (code, target, cmp0, cmp1);
4773 enum rtx_code inv_code = reverse_condition (code);
4774 if (!mips_canonicalize_int_order_test (&inv_code, &cmp1, mode))
4776 cmp1 = force_reg (mode, cmp1);
4777 mips_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1);
4779 else if (invert_ptr == 0)
4783 inv_target = mips_force_binary (GET_MODE (target),
4784 inv_code, cmp0, cmp1);
4785 mips_emit_binary (XOR, target, inv_target, const1_rtx);
4789 *invert_ptr = !*invert_ptr;
4790 mips_emit_binary (inv_code, target, cmp0, cmp1);
4795 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4796 The register will have the same mode as CMP0. */
4799 mips_zero_if_equal (rtx cmp0, rtx cmp1)
4801 if (cmp1 == const0_rtx)
4804 if (uns_arith_operand (cmp1, VOIDmode))
4805 return expand_binop (GET_MODE (cmp0), xor_optab,
4806 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4808 return expand_binop (GET_MODE (cmp0), sub_optab,
4809 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4812 /* Convert *CODE into a code that can be used in a floating-point
4813 scc instruction (C.cond.fmt). Return true if the values of
4814 the condition code registers will be inverted, with 0 indicating
4815 that the condition holds. */
4818 mips_reversed_fp_cond (enum rtx_code *code)
4825 *code = reverse_condition_maybe_unordered (*code);
4833 /* Allocate a floating-point condition-code register of mode MODE.
4835 These condition code registers are used for certain kinds
4836 of compound operation, such as compare and branches, vconds,
4837 and built-in functions. At expand time, their use is entirely
4838 controlled by MIPS-specific code and is entirely internal
4839 to these compound operations.
4841 We could (and did in the past) expose condition-code values
4842 as pseudo registers and leave the register allocator to pick
4843 appropriate registers. The problem is that it is not practically
4844 possible for the rtl optimizers to guarantee that no spills will
4845 be needed, even when AVOID_CCMODE_COPIES is defined. We would
4846 therefore need spill and reload sequences to handle the worst case.
4848 Although such sequences do exist, they are very expensive and are
4849 not something we'd want to use. This is especially true of CCV2 and
4850 CCV4, where all the shuffling would greatly outweigh whatever benefit
4851 the vectorization itself provides.
4853 The main benefit of having more than one condition-code register
4854 is to allow the pipelining of operations, especially those involving
4855 comparisons and conditional moves. We don't really expect the
4856 registers to be live for long periods, and certainly never want
4857 them to be live across calls.
4859 Also, there should be no penalty attached to using all the available
4860 registers. They are simply bits in the same underlying FPU control
4863 We therefore expose the hardware registers from the outset and use
4864 a simple round-robin allocation scheme. */
4867 mips_allocate_fcc (enum machine_mode mode)
4869 unsigned int regno, count;
4871 gcc_assert (TARGET_HARD_FLOAT && ISA_HAS_8CC);
4875 else if (mode == CCV2mode)
4877 else if (mode == CCV4mode)
4882 cfun->machine->next_fcc += -cfun->machine->next_fcc & (count - 1);
4883 if (cfun->machine->next_fcc > ST_REG_LAST - ST_REG_FIRST)
4884 cfun->machine->next_fcc = 0;
4885 regno = ST_REG_FIRST + cfun->machine->next_fcc;
4886 cfun->machine->next_fcc += count;
4887 return gen_rtx_REG (mode, regno);
4890 /* Convert a comparison into something that can be used in a branch or
4891 conditional move. On entry, *OP0 and *OP1 are the values being
4892 compared and *CODE is the code used to compare them.
4894 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
4895 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
4896 otherwise any standard branch condition can be used. The standard branch
4899 - EQ or NE between two registers.
4900 - any comparison between a register and zero. */
4903 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
4908 if (GET_MODE_CLASS (GET_MODE (*op0)) == MODE_INT)
4910 if (!need_eq_ne_p && *op1 == const0_rtx)
4912 else if (*code == EQ || *code == NE)
4916 *op0 = mips_zero_if_equal (cmp_op0, cmp_op1);
4920 *op1 = force_reg (GET_MODE (cmp_op0), cmp_op1);
4924 /* The comparison needs a separate scc instruction. Store the
4925 result of the scc in *OP0 and compare it against zero. */
4926 bool invert = false;
4927 *op0 = gen_reg_rtx (GET_MODE (cmp_op0));
4928 mips_emit_int_order_test (*code, &invert, *op0, cmp_op0, cmp_op1);
4929 *code = (invert ? EQ : NE);
4933 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0)))
4935 *op0 = gen_rtx_REG (CCDSPmode, CCDSP_CC_REGNUM);
4936 mips_emit_binary (*code, *op0, cmp_op0, cmp_op1);
4942 enum rtx_code cmp_code;
4944 /* Floating-point tests use a separate C.cond.fmt comparison to
4945 set a condition code register. The branch or conditional move
4946 will then compare that register against zero.
4948 Set CMP_CODE to the code of the comparison instruction and
4949 *CODE to the code that the branch or move should use. */
4951 *code = mips_reversed_fp_cond (&cmp_code) ? EQ : NE;
4953 ? mips_allocate_fcc (CCmode)
4954 : gen_rtx_REG (CCmode, FPSW_REGNUM));
4956 mips_emit_binary (cmp_code, *op0, cmp_op0, cmp_op1);
4960 /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2]
4961 and OPERAND[3]. Store the result in OPERANDS[0].
4963 On 64-bit targets, the mode of the comparison and target will always be
4964 SImode, thus possibly narrower than that of the comparison's operands. */
4967 mips_expand_scc (rtx operands[])
4969 rtx target = operands[0];
4970 enum rtx_code code = GET_CODE (operands[1]);
4971 rtx op0 = operands[2];
4972 rtx op1 = operands[3];
4974 gcc_assert (GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT);
4976 if (code == EQ || code == NE)
4979 && reg_imm10_operand (op1, GET_MODE (op1)))
4980 mips_emit_binary (code, target, op0, op1);
4983 rtx zie = mips_zero_if_equal (op0, op1);
4984 mips_emit_binary (code, target, zie, const0_rtx);
4988 mips_emit_int_order_test (code, 0, target, op0, op1);
4991 /* Compare OPERANDS[1] with OPERANDS[2] using comparison code
4992 CODE and jump to OPERANDS[3] if the condition holds. */
4995 mips_expand_conditional_branch (rtx *operands)
4997 enum rtx_code code = GET_CODE (operands[0]);
4998 rtx op0 = operands[1];
4999 rtx op1 = operands[2];
5002 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
5003 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
5004 emit_jump_insn (gen_condjump (condition, operands[3]));
5009 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
5010 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
5013 mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
5014 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
5019 reversed_p = mips_reversed_fp_cond (&cond);
5020 cmp_result = mips_allocate_fcc (CCV2mode);
5021 emit_insn (gen_scc_ps (cmp_result,
5022 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
5024 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
5027 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
5031 /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0]
5032 if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
5035 mips_expand_conditional_move (rtx *operands)
5038 enum rtx_code code = GET_CODE (operands[1]);
5039 rtx op0 = XEXP (operands[1], 0);
5040 rtx op1 = XEXP (operands[1], 1);
5042 mips_emit_compare (&code, &op0, &op1, true);
5043 cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
5044 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
5045 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), cond,
5046 operands[2], operands[3])));
5049 /* Perform the comparison in COMPARISON, then trap if the condition holds. */
5052 mips_expand_conditional_trap (rtx comparison)
5055 enum machine_mode mode;
5058 /* MIPS conditional trap instructions don't have GT or LE flavors,
5059 so we must swap the operands and convert to LT and GE respectively. */
5060 code = GET_CODE (comparison);
5067 code = swap_condition (code);
5068 op0 = XEXP (comparison, 1);
5069 op1 = XEXP (comparison, 0);
5073 op0 = XEXP (comparison, 0);
5074 op1 = XEXP (comparison, 1);
5078 mode = GET_MODE (XEXP (comparison, 0));
5079 op0 = force_reg (mode, op0);
5080 if (!arith_operand (op1, mode))
5081 op1 = force_reg (mode, op1);
5083 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
5084 gen_rtx_fmt_ee (code, mode, op0, op1),
5088 /* Initialize *CUM for a call to a function of type FNTYPE. */
5091 mips_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype)
5093 memset (cum, 0, sizeof (*cum));
5094 cum->prototype = (fntype && prototype_p (fntype));
5095 cum->gp_reg_found = (cum->prototype && stdarg_p (fntype));
5098 /* Fill INFO with information about a single argument. CUM is the
5099 cumulative state for earlier arguments. MODE is the mode of this
5100 argument and TYPE is its type (if known). NAMED is true if this
5101 is a named (fixed) argument rather than a variable one. */
5104 mips_get_arg_info (struct mips_arg_info *info, const CUMULATIVE_ARGS *cum,
5105 enum machine_mode mode, const_tree type, bool named)
5107 bool doubleword_aligned_p;
5108 unsigned int num_bytes, num_words, max_regs;
5110 /* Work out the size of the argument. */
5111 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
5112 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5114 /* Decide whether it should go in a floating-point register, assuming
5115 one is free. Later code checks for availability.
5117 The checks against UNITS_PER_FPVALUE handle the soft-float and
5118 single-float cases. */
5122 /* The EABI conventions have traditionally been defined in terms
5123 of TYPE_MODE, regardless of the actual type. */
5124 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
5125 || mode == V2SFmode)
5126 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
5131 /* Only leading floating-point scalars are passed in
5132 floating-point registers. We also handle vector floats the same
5133 say, which is OK because they are not covered by the standard ABI. */
5134 info->fpr_p = (!cum->gp_reg_found
5135 && cum->arg_number < 2
5137 || SCALAR_FLOAT_TYPE_P (type)
5138 || VECTOR_FLOAT_TYPE_P (type))
5139 && (GET_MODE_CLASS (mode) == MODE_FLOAT
5140 || mode == V2SFmode)
5141 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
5146 /* Scalar, complex and vector floating-point types are passed in
5147 floating-point registers, as long as this is a named rather
5148 than a variable argument. */
5149 info->fpr_p = (named
5150 && (type == 0 || FLOAT_TYPE_P (type))
5151 && (GET_MODE_CLASS (mode) == MODE_FLOAT
5152 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5153 || mode == V2SFmode)
5154 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
5156 /* ??? According to the ABI documentation, the real and imaginary
5157 parts of complex floats should be passed in individual registers.
5158 The real and imaginary parts of stack arguments are supposed
5159 to be contiguous and there should be an extra word of padding
5162 This has two problems. First, it makes it impossible to use a
5163 single "void *" va_list type, since register and stack arguments
5164 are passed differently. (At the time of writing, MIPSpro cannot
5165 handle complex float varargs correctly.) Second, it's unclear
5166 what should happen when there is only one register free.
5168 For now, we assume that named complex floats should go into FPRs
5169 if there are two FPRs free, otherwise they should be passed in the
5170 same way as a struct containing two floats. */
5172 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5173 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
5175 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
5176 info->fpr_p = false;
5186 /* See whether the argument has doubleword alignment. */
5187 doubleword_aligned_p = (mips_function_arg_boundary (mode, type)
5190 /* Set REG_OFFSET to the register count we're interested in.
5191 The EABI allocates the floating-point registers separately,
5192 but the other ABIs allocate them like integer registers. */
5193 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
5197 /* Advance to an even register if the argument is doubleword-aligned. */
5198 if (doubleword_aligned_p)
5199 info->reg_offset += info->reg_offset & 1;
5201 /* Work out the offset of a stack argument. */
5202 info->stack_offset = cum->stack_words;
5203 if (doubleword_aligned_p)
5204 info->stack_offset += info->stack_offset & 1;
5206 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
5208 /* Partition the argument between registers and stack. */
5209 info->reg_words = MIN (num_words, max_regs);
5210 info->stack_words = num_words - info->reg_words;
5213 /* INFO describes a register argument that has the normal format for the
5214 argument's mode. Return the register it uses, assuming that FPRs are
5215 available if HARD_FLOAT_P. */
5218 mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p)
5220 if (!info->fpr_p || !hard_float_p)
5221 return GP_ARG_FIRST + info->reg_offset;
5222 else if (mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info->reg_offset > 0)
5223 /* In o32, the second argument is always passed in $f14
5224 for TARGET_DOUBLE_FLOAT, regardless of whether the
5225 first argument was a word or doubleword. */
5226 return FP_ARG_FIRST + 2;
5228 return FP_ARG_FIRST + info->reg_offset;
5231 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
5234 mips_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED)
5236 return !TARGET_OLDABI;
5239 /* Implement TARGET_FUNCTION_ARG. */
5242 mips_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
5243 const_tree type, bool named)
5245 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
5246 struct mips_arg_info info;
5248 /* We will be called with a mode of VOIDmode after the last argument
5249 has been seen. Whatever we return will be passed to the call expander.
5250 If we need a MIPS16 fp_code, return a REG with the code stored as
5252 if (mode == VOIDmode)
5254 if (TARGET_MIPS16 && cum->fp_code != 0)
5255 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
5260 mips_get_arg_info (&info, cum, mode, type, named);
5262 /* Return straight away if the whole argument is passed on the stack. */
5263 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
5266 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
5267 contains a double in its entirety, then that 64-bit chunk is passed
5268 in a floating-point register. */
5270 && TARGET_HARD_FLOAT
5273 && TREE_CODE (type) == RECORD_TYPE
5274 && TYPE_SIZE_UNIT (type)
5275 && tree_fits_uhwi_p (TYPE_SIZE_UNIT (type)))
5279 /* First check to see if there is any such field. */
5280 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
5281 if (TREE_CODE (field) == FIELD_DECL
5282 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
5283 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
5284 && tree_fits_shwi_p (bit_position (field))
5285 && int_bit_position (field) % BITS_PER_WORD == 0)
5290 /* Now handle the special case by returning a PARALLEL
5291 indicating where each 64-bit chunk goes. INFO.REG_WORDS
5292 chunks are passed in registers. */
5294 HOST_WIDE_INT bitpos;
5297 /* assign_parms checks the mode of ENTRY_PARM, so we must
5298 use the actual mode here. */
5299 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
5302 field = TYPE_FIELDS (type);
5303 for (i = 0; i < info.reg_words; i++)
5307 for (; field; field = DECL_CHAIN (field))
5308 if (TREE_CODE (field) == FIELD_DECL
5309 && int_bit_position (field) >= bitpos)
5313 && int_bit_position (field) == bitpos
5314 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
5315 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
5316 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
5318 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
5321 = gen_rtx_EXPR_LIST (VOIDmode, reg,
5322 GEN_INT (bitpos / BITS_PER_UNIT));
5324 bitpos += BITS_PER_WORD;
5330 /* Handle the n32/n64 conventions for passing complex floating-point
5331 arguments in FPR pairs. The real part goes in the lower register
5332 and the imaginary part goes in the upper register. */
5335 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5338 enum machine_mode inner;
5341 inner = GET_MODE_INNER (mode);
5342 regno = FP_ARG_FIRST + info.reg_offset;
5343 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
5345 /* Real part in registers, imaginary part on stack. */
5346 gcc_assert (info.stack_words == info.reg_words);
5347 return gen_rtx_REG (inner, regno);
5351 gcc_assert (info.stack_words == 0);
5352 real = gen_rtx_EXPR_LIST (VOIDmode,
5353 gen_rtx_REG (inner, regno),
5355 imag = gen_rtx_EXPR_LIST (VOIDmode,
5357 regno + info.reg_words / 2),
5358 GEN_INT (GET_MODE_SIZE (inner)));
5359 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
5363 return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT));
5366 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
5369 mips_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
5370 const_tree type, bool named)
5372 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
5373 struct mips_arg_info info;
5375 mips_get_arg_info (&info, cum, mode, type, named);
5378 cum->gp_reg_found = true;
5380 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
5381 an explanation of what this code does. It assumes that we're using
5382 either the o32 or the o64 ABI, both of which pass at most 2 arguments
5384 if (cum->arg_number < 2 && info.fpr_p)
5385 cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2);
5387 /* Advance the register count. This has the effect of setting
5388 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
5389 argument required us to skip the final GPR and pass the whole
5390 argument on the stack. */
5391 if (mips_abi != ABI_EABI || !info.fpr_p)
5392 cum->num_gprs = info.reg_offset + info.reg_words;
5393 else if (info.reg_words > 0)
5394 cum->num_fprs += MAX_FPRS_PER_FMT;
5396 /* Advance the stack word count. */
5397 if (info.stack_words > 0)
5398 cum->stack_words = info.stack_offset + info.stack_words;
5403 /* Implement TARGET_ARG_PARTIAL_BYTES. */
5406 mips_arg_partial_bytes (cumulative_args_t cum,
5407 enum machine_mode mode, tree type, bool named)
5409 struct mips_arg_info info;
5411 mips_get_arg_info (&info, get_cumulative_args (cum), mode, type, named);
5412 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
5415 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
5416 least PARM_BOUNDARY bits of alignment, but will be given anything up
5417 to STACK_BOUNDARY bits if the type requires it. */
5420 mips_function_arg_boundary (enum machine_mode mode, const_tree type)
5422 unsigned int alignment;
5424 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
5425 if (alignment < PARM_BOUNDARY)
5426 alignment = PARM_BOUNDARY;
5427 if (alignment > STACK_BOUNDARY)
5428 alignment = STACK_BOUNDARY;
5432 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
5433 upward rather than downward. In other words, return true if the
5434 first byte of the stack slot has useful data, false if the last
5438 mips_pad_arg_upward (enum machine_mode mode, const_tree type)
5440 /* On little-endian targets, the first byte of every stack argument
5441 is passed in the first byte of the stack slot. */
5442 if (!BYTES_BIG_ENDIAN)
5445 /* Otherwise, integral types are padded downward: the last byte of a
5446 stack argument is passed in the last byte of the stack slot. */
5448 ? (INTEGRAL_TYPE_P (type)
5449 || POINTER_TYPE_P (type)
5450 || FIXED_POINT_TYPE_P (type))
5451 : (SCALAR_INT_MODE_P (mode)
5452 || ALL_SCALAR_FIXED_POINT_MODE_P (mode)))
5455 /* Big-endian o64 pads floating-point arguments downward. */
5456 if (mips_abi == ABI_O64)
5457 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
5460 /* Other types are padded upward for o32, o64, n32 and n64. */
5461 if (mips_abi != ABI_EABI)
5464 /* Arguments smaller than a stack slot are padded downward. */
5465 if (mode != BLKmode)
5466 return GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY;
5468 return int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT);
5471 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
5472 if the least significant byte of the register has useful data. Return
5473 the opposite if the most significant byte does. */
5476 mips_pad_reg_upward (enum machine_mode mode, tree type)
5478 /* No shifting is required for floating-point arguments. */
5479 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
5480 return !BYTES_BIG_ENDIAN;
5482 /* Otherwise, apply the same padding to register arguments as we do
5483 to stack arguments. */
5484 return mips_pad_arg_upward (mode, type);
5487 /* Return nonzero when an argument must be passed by reference. */
5490 mips_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
5491 enum machine_mode mode, const_tree type,
5492 bool named ATTRIBUTE_UNUSED)
5494 if (mips_abi == ABI_EABI)
5498 /* ??? How should SCmode be handled? */
5499 if (mode == DImode || mode == DFmode
5500 || mode == DQmode || mode == UDQmode
5501 || mode == DAmode || mode == UDAmode)
5504 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
5505 return size == -1 || size > UNITS_PER_WORD;
5509 /* If we have a variable-sized parameter, we have no choice. */
5510 return targetm.calls.must_pass_in_stack (mode, type);
5514 /* Implement TARGET_CALLEE_COPIES. */
5517 mips_callee_copies (cumulative_args_t cum ATTRIBUTE_UNUSED,
5518 enum machine_mode mode ATTRIBUTE_UNUSED,
5519 const_tree type ATTRIBUTE_UNUSED, bool named)
5521 return mips_abi == ABI_EABI && named;
5524 /* See whether VALTYPE is a record whose fields should be returned in
5525 floating-point registers. If so, return the number of fields and
5526 list them in FIELDS (which should have two elements). Return 0
5529 For n32 & n64, a structure with one or two fields is returned in
5530 floating-point registers as long as every field has a floating-point
5534 mips_fpr_return_fields (const_tree valtype, tree *fields)
5542 if (TREE_CODE (valtype) != RECORD_TYPE)
5546 for (field = TYPE_FIELDS (valtype); field != 0; field = DECL_CHAIN (field))
5548 if (TREE_CODE (field) != FIELD_DECL)
5551 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)))
5557 fields[i++] = field;
5562 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
5563 a value in the most significant part of $2/$3 if:
5565 - the target is big-endian;
5567 - the value has a structure or union type (we generalize this to
5568 cover aggregates from other languages too); and
5570 - the structure is not returned in floating-point registers. */
5573 mips_return_in_msb (const_tree valtype)
5577 return (TARGET_NEWABI
5578 && TARGET_BIG_ENDIAN
5579 && AGGREGATE_TYPE_P (valtype)
5580 && mips_fpr_return_fields (valtype, fields) == 0);
5583 /* Return true if the function return value MODE will get returned in a
5584 floating-point register. */
5587 mips_return_mode_in_fpr_p (enum machine_mode mode)
5589 return ((GET_MODE_CLASS (mode) == MODE_FLOAT
5591 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5592 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE);
5595 /* Return the representation of an FPR return register when the
5596 value being returned in FP_RETURN has mode VALUE_MODE and the
5597 return type itself has mode TYPE_MODE. On NewABI targets,
5598 the two modes may be different for structures like:
5600 struct __attribute__((packed)) foo { float f; }
5602 where we return the SFmode value of "f" in FP_RETURN, but where
5603 the structure itself has mode BLKmode. */
5606 mips_return_fpr_single (enum machine_mode type_mode,
5607 enum machine_mode value_mode)
5611 x = gen_rtx_REG (value_mode, FP_RETURN);
5612 if (type_mode != value_mode)
5614 x = gen_rtx_EXPR_LIST (VOIDmode, x, const0_rtx);
5615 x = gen_rtx_PARALLEL (type_mode, gen_rtvec (1, x));
5620 /* Return a composite value in a pair of floating-point registers.
5621 MODE1 and OFFSET1 are the mode and byte offset for the first value,
5622 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
5625 For n32 & n64, $f0 always holds the first value and $f2 the second.
5626 Otherwise the values are packed together as closely as possible. */
5629 mips_return_fpr_pair (enum machine_mode mode,
5630 enum machine_mode mode1, HOST_WIDE_INT offset1,
5631 enum machine_mode mode2, HOST_WIDE_INT offset2)
5635 inc = (TARGET_NEWABI ? 2 : MAX_FPRS_PER_FMT);
5636 return gen_rtx_PARALLEL
5639 gen_rtx_EXPR_LIST (VOIDmode,
5640 gen_rtx_REG (mode1, FP_RETURN),
5642 gen_rtx_EXPR_LIST (VOIDmode,
5643 gen_rtx_REG (mode2, FP_RETURN + inc),
5644 GEN_INT (offset2))));
5648 /* Implement TARGET_FUNCTION_VALUE and TARGET_LIBCALL_VALUE.
5649 For normal calls, VALTYPE is the return type and MODE is VOIDmode.
5650 For libcalls, VALTYPE is null and MODE is the mode of the return value. */
5653 mips_function_value_1 (const_tree valtype, const_tree fn_decl_or_type,
5654 enum machine_mode mode)
5662 if (fn_decl_or_type && DECL_P (fn_decl_or_type))
5663 func = fn_decl_or_type;
5667 mode = TYPE_MODE (valtype);
5668 unsigned_p = TYPE_UNSIGNED (valtype);
5670 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
5671 return values, promote the mode here too. */
5672 mode = promote_function_mode (valtype, mode, &unsigned_p, func, 1);
5674 /* Handle structures whose fields are returned in $f0/$f2. */
5675 switch (mips_fpr_return_fields (valtype, fields))
5678 return mips_return_fpr_single (mode,
5679 TYPE_MODE (TREE_TYPE (fields[0])));
5682 return mips_return_fpr_pair (mode,
5683 TYPE_MODE (TREE_TYPE (fields[0])),
5684 int_byte_position (fields[0]),
5685 TYPE_MODE (TREE_TYPE (fields[1])),
5686 int_byte_position (fields[1]));
5689 /* If a value is passed in the most significant part of a register, see
5690 whether we have to round the mode up to a whole number of words. */
5691 if (mips_return_in_msb (valtype))
5693 HOST_WIDE_INT size = int_size_in_bytes (valtype);
5694 if (size % UNITS_PER_WORD != 0)
5696 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
5697 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
5701 /* For EABI, the class of return register depends entirely on MODE.
5702 For example, "struct { some_type x; }" and "union { some_type x; }"
5703 are returned in the same way as a bare "some_type" would be.
5704 Other ABIs only use FPRs for scalar, complex or vector types. */
5705 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
5706 return gen_rtx_REG (mode, GP_RETURN);
5711 /* Handle long doubles for n32 & n64. */
5713 return mips_return_fpr_pair (mode,
5715 DImode, GET_MODE_SIZE (mode) / 2);
5717 if (mips_return_mode_in_fpr_p (mode))
5719 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5720 return mips_return_fpr_pair (mode,
5721 GET_MODE_INNER (mode), 0,
5722 GET_MODE_INNER (mode),
5723 GET_MODE_SIZE (mode) / 2);
5725 return gen_rtx_REG (mode, FP_RETURN);
5729 return gen_rtx_REG (mode, GP_RETURN);
5732 /* Implement TARGET_FUNCTION_VALUE. */
5735 mips_function_value (const_tree valtype, const_tree fn_decl_or_type,
5736 bool outgoing ATTRIBUTE_UNUSED)
5738 return mips_function_value_1 (valtype, fn_decl_or_type, VOIDmode);
5741 /* Implement TARGET_LIBCALL_VALUE. */
5744 mips_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
5746 return mips_function_value_1 (NULL_TREE, NULL_TREE, mode);
5749 /* Implement TARGET_FUNCTION_VALUE_REGNO_P.
5751 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
5752 Currently, R2 and F0 are only implemented here (C has no complex type). */
5755 mips_function_value_regno_p (const unsigned int regno)
5757 if (regno == GP_RETURN
5758 || regno == FP_RETURN
5759 || (LONG_DOUBLE_TYPE_SIZE == 128
5760 && FP_RETURN != GP_RETURN
5761 && regno == FP_RETURN + 2))
5767 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
5768 all BLKmode objects are returned in memory. Under the n32, n64
5769 and embedded ABIs, small structures are returned in a register.
5770 Objects with varying size must still be returned in memory, of
5774 mips_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
5776 return (TARGET_OLDABI
5777 ? TYPE_MODE (type) == BLKmode
5778 : !IN_RANGE (int_size_in_bytes (type), 0, 2 * UNITS_PER_WORD));
5781 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
5784 mips_setup_incoming_varargs (cumulative_args_t cum, enum machine_mode mode,
5785 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5788 CUMULATIVE_ARGS local_cum;
5789 int gp_saved, fp_saved;
5791 /* The caller has advanced CUM up to, but not beyond, the last named
5792 argument. Advance a local copy of CUM past the last "real" named
5793 argument, to find out how many registers are left over. */
5794 local_cum = *get_cumulative_args (cum);
5795 mips_function_arg_advance (pack_cumulative_args (&local_cum), mode, type,
5798 /* Found out how many registers we need to save. */
5799 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
5800 fp_saved = (EABI_FLOAT_VARARGS_P
5801 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
5810 ptr = plus_constant (Pmode, virtual_incoming_args_rtx,
5811 REG_PARM_STACK_SPACE (cfun->decl)
5812 - gp_saved * UNITS_PER_WORD);
5813 mem = gen_frame_mem (BLKmode, ptr);
5814 set_mem_alias_set (mem, get_varargs_alias_set ());
5816 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
5821 /* We can't use move_block_from_reg, because it will use
5823 enum machine_mode mode;
5826 /* Set OFF to the offset from virtual_incoming_args_rtx of
5827 the first float register. The FP save area lies below
5828 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
5829 off = (-gp_saved * UNITS_PER_WORD) & -UNITS_PER_FPVALUE;
5830 off -= fp_saved * UNITS_PER_FPREG;
5832 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
5834 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS;
5835 i += MAX_FPRS_PER_FMT)
5839 ptr = plus_constant (Pmode, virtual_incoming_args_rtx, off);
5840 mem = gen_frame_mem (mode, ptr);
5841 set_mem_alias_set (mem, get_varargs_alias_set ());
5842 mips_emit_move (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
5843 off += UNITS_PER_HWFPVALUE;
5847 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
5848 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
5849 + fp_saved * UNITS_PER_FPREG);
5852 /* Implement TARGET_BUILTIN_VA_LIST. */
5855 mips_build_builtin_va_list (void)
5857 if (EABI_FLOAT_VARARGS_P)
5859 /* We keep 3 pointers, and two offsets.
5861 Two pointers are to the overflow area, which starts at the CFA.
5862 One of these is constant, for addressing into the GPR save area
5863 below it. The other is advanced up the stack through the
5866 The third pointer is to the bottom of the GPR save area.
5867 Since the FPR save area is just below it, we can address
5868 FPR slots off this pointer.
5870 We also keep two one-byte offsets, which are to be subtracted
5871 from the constant pointers to yield addresses in the GPR and
5872 FPR save areas. These are downcounted as float or non-float
5873 arguments are used, and when they get to zero, the argument
5874 must be obtained from the overflow region. */
5875 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
5878 record = lang_hooks.types.make_type (RECORD_TYPE);
5880 f_ovfl = build_decl (BUILTINS_LOCATION,
5881 FIELD_DECL, get_identifier ("__overflow_argptr"),
5883 f_gtop = build_decl (BUILTINS_LOCATION,
5884 FIELD_DECL, get_identifier ("__gpr_top"),
5886 f_ftop = build_decl (BUILTINS_LOCATION,
5887 FIELD_DECL, get_identifier ("__fpr_top"),
5889 f_goff = build_decl (BUILTINS_LOCATION,
5890 FIELD_DECL, get_identifier ("__gpr_offset"),
5891 unsigned_char_type_node);
5892 f_foff = build_decl (BUILTINS_LOCATION,
5893 FIELD_DECL, get_identifier ("__fpr_offset"),
5894 unsigned_char_type_node);
5895 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
5896 warn on every user file. */
5897 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
5898 array = build_array_type (unsigned_char_type_node,
5899 build_index_type (index));
5900 f_res = build_decl (BUILTINS_LOCATION,
5901 FIELD_DECL, get_identifier ("__reserved"), array);
5903 DECL_FIELD_CONTEXT (f_ovfl) = record;
5904 DECL_FIELD_CONTEXT (f_gtop) = record;
5905 DECL_FIELD_CONTEXT (f_ftop) = record;
5906 DECL_FIELD_CONTEXT (f_goff) = record;
5907 DECL_FIELD_CONTEXT (f_foff) = record;
5908 DECL_FIELD_CONTEXT (f_res) = record;
5910 TYPE_FIELDS (record) = f_ovfl;
5911 DECL_CHAIN (f_ovfl) = f_gtop;
5912 DECL_CHAIN (f_gtop) = f_ftop;
5913 DECL_CHAIN (f_ftop) = f_goff;
5914 DECL_CHAIN (f_goff) = f_foff;
5915 DECL_CHAIN (f_foff) = f_res;
5917 layout_type (record);
5921 /* Otherwise, we use 'void *'. */
5922 return ptr_type_node;
5925 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
5928 mips_va_start (tree valist, rtx nextarg)
5930 if (EABI_FLOAT_VARARGS_P)
5932 const CUMULATIVE_ARGS *cum;
5933 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5934 tree ovfl, gtop, ftop, goff, foff;
5936 int gpr_save_area_size;
5937 int fpr_save_area_size;
5940 cum = &crtl->args.info;
5942 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
5944 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
5946 f_ovfl = TYPE_FIELDS (va_list_type_node);
5947 f_gtop = DECL_CHAIN (f_ovfl);
5948 f_ftop = DECL_CHAIN (f_gtop);
5949 f_goff = DECL_CHAIN (f_ftop);
5950 f_foff = DECL_CHAIN (f_goff);
5952 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5954 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
5956 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
5958 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
5960 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
5963 /* Emit code to initialize OVFL, which points to the next varargs
5964 stack argument. CUM->STACK_WORDS gives the number of stack
5965 words used by named arguments. */
5966 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
5967 if (cum->stack_words > 0)
5968 t = fold_build_pointer_plus_hwi (t, cum->stack_words * UNITS_PER_WORD);
5969 t = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
5970 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5972 /* Emit code to initialize GTOP, the top of the GPR save area. */
5973 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
5974 t = build2 (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
5975 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5977 /* Emit code to initialize FTOP, the top of the FPR save area.
5978 This address is gpr_save_area_bytes below GTOP, rounded
5979 down to the next fp-aligned boundary. */
5980 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
5981 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
5982 fpr_offset &= -UNITS_PER_FPVALUE;
5984 t = fold_build_pointer_plus_hwi (t, -fpr_offset);
5985 t = build2 (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
5986 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5988 /* Emit code to initialize GOFF, the offset from GTOP of the
5989 next GPR argument. */
5990 t = build2 (MODIFY_EXPR, TREE_TYPE (goff), goff,
5991 build_int_cst (TREE_TYPE (goff), gpr_save_area_size));
5992 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5994 /* Likewise emit code to initialize FOFF, the offset from FTOP
5995 of the next FPR argument. */
5996 t = build2 (MODIFY_EXPR, TREE_TYPE (foff), foff,
5997 build_int_cst (TREE_TYPE (foff), fpr_save_area_size));
5998 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6002 nextarg = plus_constant (Pmode, nextarg, -cfun->machine->varargs_size);
6003 std_expand_builtin_va_start (valist, nextarg);
6007 /* Like std_gimplify_va_arg_expr, but apply alignment to zero-sized
6011 mips_std_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
6014 tree addr, t, type_size, rounded_size, valist_tmp;
6015 unsigned HOST_WIDE_INT align, boundary;
6018 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, false);
6020 type = build_pointer_type (type);
6022 align = PARM_BOUNDARY / BITS_PER_UNIT;
6023 boundary = targetm.calls.function_arg_boundary (TYPE_MODE (type), type);
6025 /* When we align parameter on stack for caller, if the parameter
6026 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
6027 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
6028 here with caller. */
6029 if (boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
6030 boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
6032 boundary /= BITS_PER_UNIT;
6034 /* Hoist the valist value into a temporary for the moment. */
6035 valist_tmp = get_initialized_tmp_var (valist, pre_p, NULL);
6037 /* va_list pointer is aligned to PARM_BOUNDARY. If argument actually
6038 requires greater alignment, we must perform dynamic alignment. */
6039 if (boundary > align)
6041 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
6042 fold_build_pointer_plus_hwi (valist_tmp, boundary - 1));
6043 gimplify_and_add (t, pre_p);
6045 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
6046 fold_build2 (BIT_AND_EXPR, TREE_TYPE (valist),
6048 build_int_cst (TREE_TYPE (valist), -boundary)));
6049 gimplify_and_add (t, pre_p);
6054 /* If the actual alignment is less than the alignment of the type,
6055 adjust the type accordingly so that we don't assume strict alignment
6056 when dereferencing the pointer. */
6057 boundary *= BITS_PER_UNIT;
6058 if (boundary < TYPE_ALIGN (type))
6060 type = build_variant_type_copy (type);
6061 TYPE_ALIGN (type) = boundary;
6064 /* Compute the rounded size of the type. */
6065 type_size = size_in_bytes (type);
6066 rounded_size = round_up (type_size, align);
6068 /* Reduce rounded_size so it's sharable with the postqueue. */
6069 gimplify_expr (&rounded_size, pre_p, post_p, is_gimple_val, fb_rvalue);
6073 if (PAD_VARARGS_DOWN && !integer_zerop (rounded_size))
6075 /* Small args are padded downward. */
6076 t = fold_build2_loc (input_location, GT_EXPR, sizetype,
6077 rounded_size, size_int (align));
6078 t = fold_build3 (COND_EXPR, sizetype, t, size_zero_node,
6079 size_binop (MINUS_EXPR, rounded_size, type_size));
6080 addr = fold_build_pointer_plus (addr, t);
6083 /* Compute new value for AP. */
6084 t = fold_build_pointer_plus (valist_tmp, rounded_size);
6085 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
6086 gimplify_and_add (t, pre_p);
6088 addr = fold_convert (build_pointer_type (type), addr);
6091 addr = build_va_arg_indirect_ref (addr);
6093 return build_va_arg_indirect_ref (addr);
6096 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
6099 mips_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
6105 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
6107 type = build_pointer_type (type);
6109 if (!EABI_FLOAT_VARARGS_P)
6110 addr = mips_std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6113 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
6114 tree ovfl, top, off, align;
6115 HOST_WIDE_INT size, rsize, osize;
6118 f_ovfl = TYPE_FIELDS (va_list_type_node);
6119 f_gtop = DECL_CHAIN (f_ovfl);
6120 f_ftop = DECL_CHAIN (f_gtop);
6121 f_goff = DECL_CHAIN (f_ftop);
6122 f_foff = DECL_CHAIN (f_goff);
6126 TOP be the top of the GPR or FPR save area;
6127 OFF be the offset from TOP of the next register;
6128 ADDR_RTX be the address of the argument;
6129 SIZE be the number of bytes in the argument type;
6130 RSIZE be the number of bytes used to store the argument
6131 when it's in the register save area; and
6132 OSIZE be the number of bytes used to store it when it's
6133 in the stack overflow area.
6135 The code we want is:
6137 1: off &= -rsize; // round down
6140 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
6145 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
6146 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
6150 [1] and [9] can sometimes be optimized away. */
6152 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
6154 size = int_size_in_bytes (type);
6156 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
6157 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
6159 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop),
6160 unshare_expr (valist), f_ftop, NULL_TREE);
6161 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff),
6162 unshare_expr (valist), f_foff, NULL_TREE);
6164 /* When va_start saves FPR arguments to the stack, each slot
6165 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
6166 argument's precision. */
6167 rsize = UNITS_PER_HWFPVALUE;
6169 /* Overflow arguments are padded to UNITS_PER_WORD bytes
6170 (= PARM_BOUNDARY bits). This can be different from RSIZE
6173 (1) On 32-bit targets when TYPE is a structure such as:
6175 struct s { float f; };
6177 Such structures are passed in paired FPRs, so RSIZE
6178 will be 8 bytes. However, the structure only takes
6179 up 4 bytes of memory, so OSIZE will only be 4.
6181 (2) In combinations such as -mgp64 -msingle-float
6182 -fshort-double. Doubles passed in registers will then take
6183 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
6184 stack take up UNITS_PER_WORD bytes. */
6185 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
6189 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop),
6190 unshare_expr (valist), f_gtop, NULL_TREE);
6191 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff),
6192 unshare_expr (valist), f_goff, NULL_TREE);
6193 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
6194 if (rsize > UNITS_PER_WORD)
6196 /* [1] Emit code for: off &= -rsize. */
6197 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), unshare_expr (off),
6198 build_int_cst (TREE_TYPE (off), -rsize));
6199 gimplify_assign (unshare_expr (off), t, pre_p);
6204 /* [2] Emit code to branch if off == 0. */
6205 t = build2 (NE_EXPR, boolean_type_node, unshare_expr (off),
6206 build_int_cst (TREE_TYPE (off), 0));
6207 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
6209 /* [5] Emit code for: off -= rsize. We do this as a form of
6210 post-decrement not available to C. */
6211 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
6212 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
6214 /* [4] Emit code for:
6215 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
6216 t = fold_convert (sizetype, t);
6217 t = fold_build1 (NEGATE_EXPR, sizetype, t);
6218 t = fold_build_pointer_plus (top, t);
6219 if (BYTES_BIG_ENDIAN && rsize > size)
6220 t = fold_build_pointer_plus_hwi (t, rsize - size);
6221 COND_EXPR_THEN (addr) = t;
6223 if (osize > UNITS_PER_WORD)
6225 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
6226 t = fold_build_pointer_plus_hwi (unshare_expr (ovfl), osize - 1);
6227 u = build_int_cst (TREE_TYPE (t), -osize);
6228 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t, u);
6229 align = build2 (MODIFY_EXPR, TREE_TYPE (ovfl),
6230 unshare_expr (ovfl), t);
6235 /* [10, 11] Emit code for:
6236 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
6238 u = fold_convert (TREE_TYPE (ovfl), build_int_cst (NULL_TREE, osize));
6239 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
6240 if (BYTES_BIG_ENDIAN && osize > size)
6241 t = fold_build_pointer_plus_hwi (t, osize - size);
6243 /* String [9] and [10, 11] together. */
6245 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
6246 COND_EXPR_ELSE (addr) = t;
6248 addr = fold_convert (build_pointer_type (type), addr);
6249 addr = build_va_arg_indirect_ref (addr);
6253 addr = build_va_arg_indirect_ref (addr);
6258 /* Declare a unique, locally-binding function called NAME, then start
6262 mips_start_unique_function (const char *name)
6266 decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
6267 get_identifier (name),
6268 build_function_type_list (void_type_node, NULL_TREE));
6269 DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
6270 NULL_TREE, void_type_node);
6271 TREE_PUBLIC (decl) = 1;
6272 TREE_STATIC (decl) = 1;
6274 DECL_COMDAT_GROUP (decl) = DECL_ASSEMBLER_NAME (decl);
6276 targetm.asm_out.unique_section (decl, 0);
6277 switch_to_section (get_named_section (decl, NULL, 0));
6279 targetm.asm_out.globalize_label (asm_out_file, name);
6280 fputs ("\t.hidden\t", asm_out_file);
6281 assemble_name (asm_out_file, name);
6282 putc ('\n', asm_out_file);
6285 /* Start a definition of function NAME. MIPS16_P indicates whether the
6286 function contains MIPS16 code. */
6289 mips_start_function_definition (const char *name, bool mips16_p)
6292 fprintf (asm_out_file, "\t.set\tmips16\n");
6294 fprintf (asm_out_file, "\t.set\tnomips16\n");
6296 if (TARGET_MICROMIPS)
6297 fprintf (asm_out_file, "\t.set\tmicromips\n");
6298 #ifdef HAVE_GAS_MICROMIPS
6300 fprintf (asm_out_file, "\t.set\tnomicromips\n");
6303 if (!flag_inhibit_size_directive)
6305 fputs ("\t.ent\t", asm_out_file);
6306 assemble_name (asm_out_file, name);
6307 fputs ("\n", asm_out_file);
6310 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, name, "function");
6312 /* Start the definition proper. */
6313 assemble_name (asm_out_file, name);
6314 fputs (":\n", asm_out_file);
6317 /* End a function definition started by mips_start_function_definition. */
6320 mips_end_function_definition (const char *name)
6322 if (!flag_inhibit_size_directive)
6324 fputs ("\t.end\t", asm_out_file);
6325 assemble_name (asm_out_file, name);
6326 fputs ("\n", asm_out_file);
6330 /* If *STUB_PTR points to a stub, output a comdat-style definition for it,
6331 then free *STUB_PTR. */
6334 mips_finish_stub (mips_one_only_stub **stub_ptr)
6336 mips_one_only_stub *stub = *stub_ptr;
6340 const char *name = stub->get_name ();
6341 mips_start_unique_function (name);
6342 mips_start_function_definition (name, false);
6343 stub->output_body ();
6344 mips_end_function_definition (name);
6349 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
6352 mips_ok_for_lazy_binding_p (rtx x)
6354 return (TARGET_USE_GOT
6355 && GET_CODE (x) == SYMBOL_REF
6356 && !SYMBOL_REF_BIND_NOW_P (x)
6357 && !mips_symbol_binds_local_p (x));
6360 /* Load function address ADDR into register DEST. TYPE is as for
6361 mips_expand_call. Return true if we used an explicit lazy-binding
6365 mips_load_call_address (enum mips_call_type type, rtx dest, rtx addr)
6367 /* If we're generating PIC, and this call is to a global function,
6368 try to allow its address to be resolved lazily. This isn't
6369 possible for sibcalls when $gp is call-saved because the value
6370 of $gp on entry to the stub would be our caller's gp, not ours. */
6371 if (TARGET_EXPLICIT_RELOCS
6372 && !(type == MIPS_CALL_SIBCALL && TARGET_CALL_SAVED_GP)
6373 && mips_ok_for_lazy_binding_p (addr))
6375 addr = mips_got_load (dest, addr, SYMBOL_GOTOFF_CALL);
6376 emit_insn (gen_rtx_SET (VOIDmode, dest, addr));
6381 mips_emit_move (dest, addr);
6386 /* Each locally-defined hard-float MIPS16 function has a local symbol
6387 associated with it. This hash table maps the function symbol (FUNC)
6388 to the local symbol (LOCAL). */
6389 struct GTY(()) mips16_local_alias {
6393 static GTY ((param_is (struct mips16_local_alias))) htab_t mips16_local_aliases;
6395 /* Hash table callbacks for mips16_local_aliases. */
6398 mips16_local_aliases_hash (const void *entry)
6400 const struct mips16_local_alias *alias;
6402 alias = (const struct mips16_local_alias *) entry;
6403 return htab_hash_string (XSTR (alias->func, 0));
6407 mips16_local_aliases_eq (const void *entry1, const void *entry2)
6409 const struct mips16_local_alias *alias1, *alias2;
6411 alias1 = (const struct mips16_local_alias *) entry1;
6412 alias2 = (const struct mips16_local_alias *) entry2;
6413 return rtx_equal_p (alias1->func, alias2->func);
6416 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
6417 Return a local alias for it, creating a new one if necessary. */
6420 mips16_local_alias (rtx func)
6422 struct mips16_local_alias *alias, tmp_alias;
6425 /* Create the hash table if this is the first call. */
6426 if (mips16_local_aliases == NULL)
6427 mips16_local_aliases = htab_create_ggc (37, mips16_local_aliases_hash,
6428 mips16_local_aliases_eq, NULL);
6430 /* Look up the function symbol, creating a new entry if need be. */
6431 tmp_alias.func = func;
6432 slot = htab_find_slot (mips16_local_aliases, &tmp_alias, INSERT);
6433 gcc_assert (slot != NULL);
6435 alias = (struct mips16_local_alias *) *slot;
6438 const char *func_name, *local_name;
6441 /* Create a new SYMBOL_REF for the local symbol. The choice of
6442 __fn_local_* is based on the __fn_stub_* names that we've
6443 traditionally used for the non-MIPS16 stub. */
6444 func_name = targetm.strip_name_encoding (XSTR (func, 0));
6445 local_name = ACONCAT (("__fn_local_", func_name, NULL));
6446 local = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (local_name));
6447 SYMBOL_REF_FLAGS (local) = SYMBOL_REF_FLAGS (func) | SYMBOL_FLAG_LOCAL;
6449 /* Create a new structure to represent the mapping. */
6450 alias = ggc_alloc_mips16_local_alias ();
6452 alias->local = local;
6455 return alias->local;
6458 /* A chained list of functions for which mips16_build_call_stub has already
6459 generated a stub. NAME is the name of the function and FP_RET_P is true
6460 if the function returns a value in floating-point registers. */
6461 struct mips16_stub {
6462 struct mips16_stub *next;
6466 static struct mips16_stub *mips16_stubs;
6468 /* Return the two-character string that identifies floating-point
6469 return mode MODE in the name of a MIPS16 function stub. */
6472 mips16_call_stub_mode_suffix (enum machine_mode mode)
6476 else if (mode == DFmode)
6478 else if (mode == SCmode)
6480 else if (mode == DCmode)
6482 else if (mode == V2SFmode)
6488 /* Write instructions to move a 32-bit value between general register
6489 GPREG and floating-point register FPREG. DIRECTION is 't' to move
6490 from GPREG to FPREG and 'f' to move in the opposite direction. */
6493 mips_output_32bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
6495 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6496 reg_names[gpreg], reg_names[fpreg]);
6499 /* Likewise for 64-bit values. */
6502 mips_output_64bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
6505 fprintf (asm_out_file, "\tdm%cc1\t%s,%s\n", direction,
6506 reg_names[gpreg], reg_names[fpreg]);
6507 else if (TARGET_FLOAT64)
6509 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6510 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
6511 fprintf (asm_out_file, "\tm%chc1\t%s,%s\n", direction,
6512 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg]);
6516 /* Move the least-significant word. */
6517 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6518 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
6519 /* ...then the most significant word. */
6520 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6521 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg + 1]);
6525 /* Write out code to move floating-point arguments into or out of
6526 general registers. FP_CODE is the code describing which arguments
6527 are present (see the comment above the definition of CUMULATIVE_ARGS
6528 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
6531 mips_output_args_xfer (int fp_code, char direction)
6533 unsigned int gparg, fparg, f;
6534 CUMULATIVE_ARGS cum;
6536 /* This code only works for o32 and o64. */
6537 gcc_assert (TARGET_OLDABI);
6539 mips_init_cumulative_args (&cum, NULL);
6541 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
6543 enum machine_mode mode;
6544 struct mips_arg_info info;
6548 else if ((f & 3) == 2)
6553 mips_get_arg_info (&info, &cum, mode, NULL, true);
6554 gparg = mips_arg_regno (&info, false);
6555 fparg = mips_arg_regno (&info, true);
6558 mips_output_32bit_xfer (direction, gparg, fparg);
6560 mips_output_64bit_xfer (direction, gparg, fparg);
6562 mips_function_arg_advance (pack_cumulative_args (&cum), mode, NULL, true);
6566 /* Write a MIPS16 stub for the current function. This stub is used
6567 for functions which take arguments in the floating-point registers.
6568 It is normal-mode code that moves the floating-point arguments
6569 into the general registers and then jumps to the MIPS16 code. */
6572 mips16_build_function_stub (void)
6574 const char *fnname, *alias_name, *separator;
6575 char *secname, *stubname;
6580 /* Create the name of the stub, and its unique section. */
6581 symbol = XEXP (DECL_RTL (current_function_decl), 0);
6582 alias = mips16_local_alias (symbol);
6584 fnname = targetm.strip_name_encoding (XSTR (symbol, 0));
6585 alias_name = targetm.strip_name_encoding (XSTR (alias, 0));
6586 secname = ACONCAT ((".mips16.fn.", fnname, NULL));
6587 stubname = ACONCAT (("__fn_stub_", fnname, NULL));
6589 /* Build a decl for the stub. */
6590 stubdecl = build_decl (BUILTINS_LOCATION,
6591 FUNCTION_DECL, get_identifier (stubname),
6592 build_function_type_list (void_type_node, NULL_TREE));
6593 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
6594 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
6595 RESULT_DECL, NULL_TREE, void_type_node);
6597 /* Output a comment. */
6598 fprintf (asm_out_file, "\t# Stub function for %s (",
6599 current_function_name ());
6601 for (f = (unsigned int) crtl->args.info.fp_code; f != 0; f >>= 2)
6603 fprintf (asm_out_file, "%s%s", separator,
6604 (f & 3) == 1 ? "float" : "double");
6607 fprintf (asm_out_file, ")\n");
6609 /* Start the function definition. */
6610 assemble_start_function (stubdecl, stubname);
6611 mips_start_function_definition (stubname, false);
6613 /* If generating pic2 code, either set up the global pointer or
6615 if (TARGET_ABICALLS_PIC2)
6617 if (TARGET_ABSOLUTE_ABICALLS)
6618 fprintf (asm_out_file, "\t.option\tpic0\n");
6621 output_asm_insn ("%(.cpload\t%^%)", NULL);
6622 /* Emit an R_MIPS_NONE relocation to tell the linker what the
6623 target function is. Use a local GOT access when loading the
6624 symbol, to cut down on the number of unnecessary GOT entries
6625 for stubs that aren't needed. */
6626 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol);
6631 /* Load the address of the MIPS16 function into $25. Do this first so
6632 that targets with coprocessor interlocks can use an MFC1 to fill the
6634 output_asm_insn ("la\t%^,%0", &symbol);
6636 /* Move the arguments from floating-point registers to general registers. */
6637 mips_output_args_xfer (crtl->args.info.fp_code, 'f');
6639 /* Jump to the MIPS16 function. */
6640 output_asm_insn ("jr\t%^", NULL);
6642 if (TARGET_ABICALLS_PIC2 && TARGET_ABSOLUTE_ABICALLS)
6643 fprintf (asm_out_file, "\t.option\tpic2\n");
6645 mips_end_function_definition (stubname);
6647 /* If the linker needs to create a dynamic symbol for the target
6648 function, it will associate the symbol with the stub (which,
6649 unlike the target function, follows the proper calling conventions).
6650 It is therefore useful to have a local alias for the target function,
6651 so that it can still be identified as MIPS16 code. As an optimization,
6652 this symbol can also be used for indirect MIPS16 references from
6653 within this file. */
6654 ASM_OUTPUT_DEF (asm_out_file, alias_name, fnname);
6656 switch_to_section (function_section (current_function_decl));
6659 /* The current function is a MIPS16 function that returns a value in an FPR.
6660 Copy the return value from its soft-float to its hard-float location.
6661 libgcc2 has special non-MIPS16 helper functions for each case. */
6664 mips16_copy_fpr_return_value (void)
6666 rtx fn, insn, retval;
6668 enum machine_mode return_mode;
6671 return_type = DECL_RESULT (current_function_decl);
6672 return_mode = DECL_MODE (return_type);
6674 name = ACONCAT (("__mips16_ret_",
6675 mips16_call_stub_mode_suffix (return_mode),
6677 fn = mips16_stub_function (name);
6679 /* The function takes arguments in $2 (and possibly $3), so calls
6680 to it cannot be lazily bound. */
6681 SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_BIND_NOW;
6683 /* Model the call as something that takes the GPR return value as
6684 argument and returns an "updated" value. */
6685 retval = gen_rtx_REG (return_mode, GP_RETURN);
6686 insn = mips_expand_call (MIPS_CALL_EPILOGUE, retval, fn,
6687 const0_rtx, NULL_RTX, false);
6688 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), retval);
6691 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
6692 RETVAL is the location of the return value, or null if this is
6693 a "call" rather than a "call_value". ARGS_SIZE is the size of the
6694 arguments and FP_CODE is the code built by mips_function_arg;
6695 see the comment before the fp_code field in CUMULATIVE_ARGS for details.
6697 There are three alternatives:
6699 - If a stub was needed, emit the call and return the call insn itself.
6701 - If we can avoid using a stub by redirecting the call, set *FN_PTR
6702 to the new target and return null.
6704 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
6707 A stub is needed for calls to functions that, in normal mode,
6708 receive arguments in FPRs or return values in FPRs. The stub
6709 copies the arguments from their soft-float positions to their
6710 hard-float positions, calls the real function, then copies the
6711 return value from its hard-float position to its soft-float
6714 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
6715 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
6716 automatically redirects the JAL to the stub, otherwise the JAL
6717 continues to call FN directly. */
6720 mips16_build_call_stub (rtx retval, rtx *fn_ptr, rtx args_size, int fp_code)
6724 struct mips16_stub *l;
6727 /* We don't need to do anything if we aren't in MIPS16 mode, or if
6728 we were invoked with the -msoft-float option. */
6729 if (!TARGET_MIPS16 || TARGET_SOFT_FLOAT_ABI)
6732 /* Figure out whether the value might come back in a floating-point
6734 fp_ret_p = retval && mips_return_mode_in_fpr_p (GET_MODE (retval));
6736 /* We don't need to do anything if there were no floating-point
6737 arguments and the value will not be returned in a floating-point
6739 if (fp_code == 0 && !fp_ret_p)
6742 /* We don't need to do anything if this is a call to a special
6743 MIPS16 support function. */
6745 if (mips16_stub_function_p (fn))
6748 /* If we're calling a locally-defined MIPS16 function, we know that
6749 it will return values in both the "soft-float" and "hard-float"
6750 registers. There is no need to use a stub to move the latter
6752 if (fp_code == 0 && mips16_local_function_p (fn))
6755 /* This code will only work for o32 and o64 abis. The other ABI's
6756 require more sophisticated support. */
6757 gcc_assert (TARGET_OLDABI);
6759 /* If we're calling via a function pointer, use one of the magic
6760 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
6761 Each stub expects the function address to arrive in register $2. */
6762 if (GET_CODE (fn) != SYMBOL_REF
6763 || !call_insn_operand (fn, VOIDmode))
6766 rtx stub_fn, insn, addr;
6769 /* If this is a locally-defined and locally-binding function,
6770 avoid the stub by calling the local alias directly. */
6771 if (mips16_local_function_p (fn))
6773 *fn_ptr = mips16_local_alias (fn);
6777 /* Create a SYMBOL_REF for the libgcc.a function. */
6779 sprintf (buf, "__mips16_call_stub_%s_%d",
6780 mips16_call_stub_mode_suffix (GET_MODE (retval)),
6783 sprintf (buf, "__mips16_call_stub_%d", fp_code);
6784 stub_fn = mips16_stub_function (buf);
6786 /* The function uses $2 as an argument, so calls to it
6787 cannot be lazily bound. */
6788 SYMBOL_REF_FLAGS (stub_fn) |= SYMBOL_FLAG_BIND_NOW;
6790 /* Load the target function into $2. */
6791 addr = gen_rtx_REG (Pmode, GP_REG_FIRST + 2);
6792 lazy_p = mips_load_call_address (MIPS_CALL_NORMAL, addr, fn);
6794 /* Emit the call. */
6795 insn = mips_expand_call (MIPS_CALL_NORMAL, retval, stub_fn,
6796 args_size, NULL_RTX, lazy_p);
6798 /* Tell GCC that this call does indeed use the value of $2. */
6799 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), addr);
6801 /* If we are handling a floating-point return value, we need to
6802 save $18 in the function prologue. Putting a note on the
6803 call will mean that df_regs_ever_live_p ($18) will be true if the
6804 call is not eliminated, and we can check that in the prologue
6807 CALL_INSN_FUNCTION_USAGE (insn) =
6808 gen_rtx_EXPR_LIST (VOIDmode,
6809 gen_rtx_CLOBBER (VOIDmode,
6810 gen_rtx_REG (word_mode, 18)),
6811 CALL_INSN_FUNCTION_USAGE (insn));
6816 /* We know the function we are going to call. If we have already
6817 built a stub, we don't need to do anything further. */
6818 fnname = targetm.strip_name_encoding (XSTR (fn, 0));
6819 for (l = mips16_stubs; l != NULL; l = l->next)
6820 if (strcmp (l->name, fnname) == 0)
6825 const char *separator;
6826 char *secname, *stubname;
6827 tree stubid, stubdecl;
6830 /* If the function does not return in FPRs, the special stub
6834 If the function does return in FPRs, the stub section is named
6835 .mips16.call.fp.FNNAME
6837 Build a decl for the stub. */
6838 secname = ACONCAT ((".mips16.call.", fp_ret_p ? "fp." : "",
6840 stubname = ACONCAT (("__call_stub_", fp_ret_p ? "fp_" : "",
6842 stubid = get_identifier (stubname);
6843 stubdecl = build_decl (BUILTINS_LOCATION,
6844 FUNCTION_DECL, stubid,
6845 build_function_type_list (void_type_node,
6847 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
6848 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
6849 RESULT_DECL, NULL_TREE,
6852 /* Output a comment. */
6853 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
6855 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
6859 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
6861 fprintf (asm_out_file, "%s%s", separator,
6862 (f & 3) == 1 ? "float" : "double");
6865 fprintf (asm_out_file, ")\n");
6867 /* Start the function definition. */
6868 assemble_start_function (stubdecl, stubname);
6869 mips_start_function_definition (stubname, false);
6873 fprintf (asm_out_file, "\t.cfi_startproc\n");
6875 /* Create a fake CFA 4 bytes below the stack pointer.
6876 This works around unwinders (like libgcc's) that expect
6877 the CFA for non-signal frames to be unique. */
6878 fprintf (asm_out_file, "\t.cfi_def_cfa 29,-4\n");
6880 /* "Save" $sp in itself so we don't use the fake CFA.
6881 This is: DW_CFA_val_expression r29, { DW_OP_reg29 }. */
6882 fprintf (asm_out_file, "\t.cfi_escape 0x16,29,1,0x6d\n");
6886 /* Load the address of the MIPS16 function into $25. Do this
6887 first so that targets with coprocessor interlocks can use
6888 an MFC1 to fill the delay slot. */
6889 if (TARGET_EXPLICIT_RELOCS)
6891 output_asm_insn ("lui\t%^,%%hi(%0)", &fn);
6892 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn);
6895 output_asm_insn ("la\t%^,%0", &fn);
6898 /* Move the arguments from general registers to floating-point
6900 mips_output_args_xfer (fp_code, 't');
6904 /* Save the return address in $18 and call the non-MIPS16 function.
6905 The stub's caller knows that $18 might be clobbered, even though
6906 $18 is usually a call-saved register. */
6907 fprintf (asm_out_file, "\tmove\t%s,%s\n",
6908 reg_names[GP_REG_FIRST + 18], reg_names[RETURN_ADDR_REGNUM]);
6909 output_asm_insn (MIPS_CALL ("jal", &fn, 0, -1), &fn);
6910 fprintf (asm_out_file, "\t.cfi_register 31,18\n");
6912 /* Move the result from floating-point registers to
6913 general registers. */
6914 switch (GET_MODE (retval))
6917 mips_output_32bit_xfer ('f', GP_RETURN + TARGET_BIG_ENDIAN,
6919 ? FP_REG_FIRST + MAX_FPRS_PER_FMT
6921 mips_output_32bit_xfer ('f', GP_RETURN + TARGET_LITTLE_ENDIAN,
6922 TARGET_LITTLE_ENDIAN
6923 ? FP_REG_FIRST + MAX_FPRS_PER_FMT
6925 if (GET_MODE (retval) == SCmode && TARGET_64BIT)
6927 /* On 64-bit targets, complex floats are returned in
6928 a single GPR, such that "sd" on a suitably-aligned
6929 target would store the value correctly. */
6930 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
6931 reg_names[GP_RETURN + TARGET_BIG_ENDIAN],
6932 reg_names[GP_RETURN + TARGET_BIG_ENDIAN]);
6933 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
6934 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN],
6935 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN]);
6936 fprintf (asm_out_file, "\tdsrl\t%s,%s,32\n",
6937 reg_names[GP_RETURN + TARGET_BIG_ENDIAN],
6938 reg_names[GP_RETURN + TARGET_BIG_ENDIAN]);
6939 fprintf (asm_out_file, "\tor\t%s,%s,%s\n",
6940 reg_names[GP_RETURN],
6941 reg_names[GP_RETURN],
6942 reg_names[GP_RETURN + 1]);
6947 mips_output_32bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6951 mips_output_64bit_xfer ('f', GP_RETURN + (8 / UNITS_PER_WORD),
6952 FP_REG_FIRST + MAX_FPRS_PER_FMT);
6956 mips_output_64bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6962 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 18]);
6963 fprintf (asm_out_file, "\t.cfi_endproc\n");
6967 /* Jump to the previously-loaded address. */
6968 output_asm_insn ("jr\t%^", NULL);
6971 #ifdef ASM_DECLARE_FUNCTION_SIZE
6972 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
6975 mips_end_function_definition (stubname);
6977 /* Record this stub. */
6978 l = XNEW (struct mips16_stub);
6979 l->name = xstrdup (fnname);
6980 l->fp_ret_p = fp_ret_p;
6981 l->next = mips16_stubs;
6985 /* If we expect a floating-point return value, but we've built a
6986 stub which does not expect one, then we're in trouble. We can't
6987 use the existing stub, because it won't handle the floating-point
6988 value. We can't build a new stub, because the linker won't know
6989 which stub to use for the various calls in this object file.
6990 Fortunately, this case is illegal, since it means that a function
6991 was declared in two different ways in a single compilation. */
6992 if (fp_ret_p && !l->fp_ret_p)
6993 error ("cannot handle inconsistent calls to %qs", fnname);
6995 if (retval == NULL_RTX)
6996 insn = gen_call_internal_direct (fn, args_size);
6998 insn = gen_call_value_internal_direct (retval, fn, args_size);
6999 insn = mips_emit_call_insn (insn, fn, fn, false);
7001 /* If we are calling a stub which handles a floating-point return
7002 value, we need to arrange to save $18 in the prologue. We do this
7003 by marking the function call as using the register. The prologue
7004 will later see that it is used, and emit code to save it. */
7006 CALL_INSN_FUNCTION_USAGE (insn) =
7007 gen_rtx_EXPR_LIST (VOIDmode,
7008 gen_rtx_CLOBBER (VOIDmode,
7009 gen_rtx_REG (word_mode, 18)),
7010 CALL_INSN_FUNCTION_USAGE (insn));
7015 /* Expand a call of type TYPE. RESULT is where the result will go (null
7016 for "call"s and "sibcall"s), ADDR is the address of the function,
7017 ARGS_SIZE is the size of the arguments and AUX is the value passed
7018 to us by mips_function_arg. LAZY_P is true if this call already
7019 involves a lazily-bound function address (such as when calling
7020 functions through a MIPS16 hard-float stub).
7022 Return the call itself. */
7025 mips_expand_call (enum mips_call_type type, rtx result, rtx addr,
7026 rtx args_size, rtx aux, bool lazy_p)
7028 rtx orig_addr, pattern, insn;
7031 fp_code = aux == 0 ? 0 : (int) GET_MODE (aux);
7032 insn = mips16_build_call_stub (result, &addr, args_size, fp_code);
7035 gcc_assert (!lazy_p && type == MIPS_CALL_NORMAL);
7040 if (!call_insn_operand (addr, VOIDmode))
7042 if (type == MIPS_CALL_EPILOGUE)
7043 addr = MIPS_EPILOGUE_TEMP (Pmode);
7045 addr = gen_reg_rtx (Pmode);
7046 lazy_p |= mips_load_call_address (type, addr, orig_addr);
7051 rtx (*fn) (rtx, rtx);
7053 if (type == MIPS_CALL_SIBCALL)
7054 fn = gen_sibcall_internal;
7056 fn = gen_call_internal;
7058 pattern = fn (addr, args_size);
7060 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
7062 /* Handle return values created by mips_return_fpr_pair. */
7063 rtx (*fn) (rtx, rtx, rtx, rtx);
7066 if (type == MIPS_CALL_SIBCALL)
7067 fn = gen_sibcall_value_multiple_internal;
7069 fn = gen_call_value_multiple_internal;
7071 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
7072 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
7073 pattern = fn (reg1, addr, args_size, reg2);
7077 rtx (*fn) (rtx, rtx, rtx);
7079 if (type == MIPS_CALL_SIBCALL)
7080 fn = gen_sibcall_value_internal;
7082 fn = gen_call_value_internal;
7084 /* Handle return values created by mips_return_fpr_single. */
7085 if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 1)
7086 result = XEXP (XVECEXP (result, 0, 0), 0);
7087 pattern = fn (result, addr, args_size);
7090 return mips_emit_call_insn (pattern, orig_addr, addr, lazy_p);
7093 /* Split call instruction INSN into a $gp-clobbering call and
7094 (where necessary) an instruction to restore $gp from its save slot.
7095 CALL_PATTERN is the pattern of the new call. */
7098 mips_split_call (rtx insn, rtx call_pattern)
7100 emit_call_insn (call_pattern);
7101 if (!find_reg_note (insn, REG_NORETURN, 0))
7102 /* Pick a temporary register that is suitable for both MIPS16 and
7103 non-MIPS16 code. $4 and $5 are used for returning complex double
7104 values in soft-float code, so $6 is the first suitable candidate. */
7105 mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode, GP_ARG_FIRST + 2));
7108 /* Return true if a call to DECL may need to use JALX. */
7111 mips_call_may_need_jalx_p (tree decl)
7113 /* If the current translation unit would use a different mode for DECL,
7114 assume that the call needs JALX. */
7115 if (mips_get_compress_mode (decl) != TARGET_COMPRESSION)
7118 /* mips_get_compress_mode is always accurate for locally-binding
7119 functions in the current translation unit. */
7120 if (!DECL_EXTERNAL (decl) && targetm.binds_local_p (decl))
7123 /* When -minterlink-compressed is in effect, assume that functions
7124 could use a different encoding mode unless an attribute explicitly
7125 tells us otherwise. */
7126 if (TARGET_INTERLINK_COMPRESSED)
7128 if (!TARGET_COMPRESSION
7129 && mips_get_compress_off_flags (DECL_ATTRIBUTES (decl)) ==0)
7131 if (TARGET_COMPRESSION
7132 && mips_get_compress_on_flags (DECL_ATTRIBUTES (decl)) == 0)
7139 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
7142 mips_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
7144 if (!TARGET_SIBCALLS)
7147 /* Interrupt handlers need special epilogue code and therefore can't
7149 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
7152 /* Direct Js are only possible to functions that use the same ISA encoding.
7153 There is no JX counterpoart of JALX. */
7155 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode)
7156 && mips_call_may_need_jalx_p (decl))
7159 /* Sibling calls should not prevent lazy binding. Lazy-binding stubs
7160 require $gp to be valid on entry, so sibcalls can only use stubs
7161 if $gp is call-clobbered. */
7163 && TARGET_CALL_SAVED_GP
7164 && !TARGET_ABICALLS_PIC0
7165 && !targetm.binds_local_p (decl))
7172 /* Emit code to move general operand SRC into condition-code
7173 register DEST given that SCRATCH is a scratch TFmode FPR.
7180 where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */
7183 mips_expand_fcc_reload (rtx dest, rtx src, rtx scratch)
7187 /* Change the source to SFmode. */
7189 src = adjust_address (src, SFmode, 0);
7190 else if (REG_P (src) || GET_CODE (src) == SUBREG)
7191 src = gen_rtx_REG (SFmode, true_regnum (src));
7193 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
7194 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + MAX_FPRS_PER_FMT);
7196 mips_emit_move (copy_rtx (fp1), src);
7197 mips_emit_move (copy_rtx (fp2), CONST0_RTX (SFmode));
7198 emit_insn (gen_slt_sf (dest, fp2, fp1));
7201 /* Implement MOVE_BY_PIECES_P. */
7204 mips_move_by_pieces_p (unsigned HOST_WIDE_INT size, unsigned int align)
7208 /* movmemsi is meant to generate code that is at least as good as
7209 move_by_pieces. However, movmemsi effectively uses a by-pieces
7210 implementation both for moves smaller than a word and for
7211 word-aligned moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT
7212 bytes. We should allow the tree-level optimisers to do such
7213 moves by pieces, as it often exposes other optimization
7214 opportunities. We might as well continue to use movmemsi at
7215 the rtl level though, as it produces better code when
7216 scheduling is disabled (such as at -O). */
7217 if (currently_expanding_to_rtl)
7219 if (align < BITS_PER_WORD)
7220 return size < UNITS_PER_WORD;
7221 return size <= MIPS_MAX_MOVE_BYTES_STRAIGHT;
7223 /* The default value. If this becomes a target hook, we should
7224 call the default definition instead. */
7225 return (move_by_pieces_ninsns (size, align, MOVE_MAX_PIECES + 1)
7226 < (unsigned int) MOVE_RATIO (optimize_insn_for_speed_p ()));
7229 /* Implement STORE_BY_PIECES_P. */
7232 mips_store_by_pieces_p (unsigned HOST_WIDE_INT size, unsigned int align)
7234 /* Storing by pieces involves moving constants into registers
7235 of size MIN (ALIGN, BITS_PER_WORD), then storing them.
7236 We need to decide whether it is cheaper to load the address of
7237 constant data into a register and use a block move instead. */
7239 /* If the data is only byte aligned, then:
7241 (a1) A block move of less than 4 bytes would involve three 3 LBs and
7242 3 SBs. We might as well use 3 single-instruction LIs and 3 SBs
7245 (a2) A block move of 4 bytes from aligned source data can use an
7246 LW/SWL/SWR sequence. This is often better than the 4 LIs and
7247 4 SBs that we would generate when storing by pieces. */
7248 if (align <= BITS_PER_UNIT)
7251 /* If the data is 2-byte aligned, then:
7253 (b1) A block move of less than 4 bytes would use a combination of LBs,
7254 LHs, SBs and SHs. We get better code by using single-instruction
7255 LIs, SBs and SHs instead.
7257 (b2) A block move of 4 bytes from aligned source data would again use
7258 an LW/SWL/SWR sequence. In most cases, loading the address of
7259 the source data would require at least one extra instruction.
7260 It is often more efficient to use 2 single-instruction LIs and
7263 (b3) A block move of up to 3 additional bytes would be like (b1).
7265 (b4) A block move of 8 bytes from aligned source data can use two
7266 LW/SWL/SWR sequences or a single LD/SDL/SDR sequence. Both
7267 sequences are better than the 4 LIs and 4 SHs that we'd generate
7268 when storing by pieces.
7270 The reasoning for higher alignments is similar:
7272 (c1) A block move of less than 4 bytes would be the same as (b1).
7274 (c2) A block move of 4 bytes would use an LW/SW sequence. Again,
7275 loading the address of the source data would typically require
7276 at least one extra instruction. It is generally better to use
7279 (c3) A block move of up to 3 additional bytes would be like (b1).
7281 (c4) A block move of 8 bytes can use two LW/SW sequences or a single
7282 LD/SD sequence, and in these cases we've traditionally preferred
7283 the memory copy over the more bulky constant moves. */
7287 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
7288 Assume that the areas do not overlap. */
7291 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
7293 HOST_WIDE_INT offset, delta;
7294 unsigned HOST_WIDE_INT bits;
7296 enum machine_mode mode;
7299 /* Work out how many bits to move at a time. If both operands have
7300 half-word alignment, it is usually better to move in half words.
7301 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
7302 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
7303 Otherwise move word-sized chunks. */
7304 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
7305 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
7306 bits = BITS_PER_WORD / 2;
7308 bits = BITS_PER_WORD;
7310 mode = mode_for_size (bits, MODE_INT, 0);
7311 delta = bits / BITS_PER_UNIT;
7313 /* Allocate a buffer for the temporary registers. */
7314 regs = XALLOCAVEC (rtx, length / delta);
7316 /* Load as many BITS-sized chunks as possible. Use a normal load if
7317 the source has enough alignment, otherwise use left/right pairs. */
7318 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
7320 regs[i] = gen_reg_rtx (mode);
7321 if (MEM_ALIGN (src) >= bits)
7322 mips_emit_move (regs[i], adjust_address (src, mode, offset));
7325 rtx part = adjust_address (src, BLKmode, offset);
7326 set_mem_size (part, delta);
7327 if (!mips_expand_ext_as_unaligned_load (regs[i], part, bits, 0, 0))
7332 /* Copy the chunks to the destination. */
7333 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
7334 if (MEM_ALIGN (dest) >= bits)
7335 mips_emit_move (adjust_address (dest, mode, offset), regs[i]);
7338 rtx part = adjust_address (dest, BLKmode, offset);
7339 set_mem_size (part, delta);
7340 if (!mips_expand_ins_as_unaligned_store (part, regs[i], bits, 0))
7344 /* Mop up any left-over bytes. */
7345 if (offset < length)
7347 src = adjust_address (src, BLKmode, offset);
7348 dest = adjust_address (dest, BLKmode, offset);
7349 move_by_pieces (dest, src, length - offset,
7350 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
7354 /* Helper function for doing a loop-based block operation on memory
7355 reference MEM. Each iteration of the loop will operate on LENGTH
7358 Create a new base register for use within the loop and point it to
7359 the start of MEM. Create a new memory reference that uses this
7360 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
7363 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
7364 rtx *loop_reg, rtx *loop_mem)
7366 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
7368 /* Although the new mem does not refer to a known location,
7369 it does keep up to LENGTH bytes of alignment. */
7370 *loop_mem = change_address (mem, BLKmode, *loop_reg);
7371 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
7374 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
7375 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
7376 the memory regions do not overlap. */
7379 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length,
7380 HOST_WIDE_INT bytes_per_iter)
7382 rtx label, src_reg, dest_reg, final_src, test;
7383 HOST_WIDE_INT leftover;
7385 leftover = length % bytes_per_iter;
7388 /* Create registers and memory references for use within the loop. */
7389 mips_adjust_block_mem (src, bytes_per_iter, &src_reg, &src);
7390 mips_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest);
7392 /* Calculate the value that SRC_REG should have after the last iteration
7394 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
7397 /* Emit the start of the loop. */
7398 label = gen_label_rtx ();
7401 /* Emit the loop body. */
7402 mips_block_move_straight (dest, src, bytes_per_iter);
7404 /* Move on to the next block. */
7405 mips_emit_move (src_reg, plus_constant (Pmode, src_reg, bytes_per_iter));
7406 mips_emit_move (dest_reg, plus_constant (Pmode, dest_reg, bytes_per_iter));
7408 /* Emit the loop condition. */
7409 test = gen_rtx_NE (VOIDmode, src_reg, final_src);
7410 if (Pmode == DImode)
7411 emit_jump_insn (gen_cbranchdi4 (test, src_reg, final_src, label));
7413 emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label));
7415 /* Mop up any left-over bytes. */
7417 mips_block_move_straight (dest, src, leftover);
7420 /* Expand a movmemsi instruction, which copies LENGTH bytes from
7421 memory reference SRC to memory reference DEST. */
7424 mips_expand_block_move (rtx dest, rtx src, rtx length)
7426 if (CONST_INT_P (length))
7428 if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)
7430 mips_block_move_straight (dest, src, INTVAL (length));
7435 mips_block_move_loop (dest, src, INTVAL (length),
7436 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER);
7443 /* Expand a loop of synci insns for the address range [BEGIN, END). */
7446 mips_expand_synci_loop (rtx begin, rtx end)
7448 rtx inc, label, end_label, cmp_result, mask, length;
7450 /* Create end_label. */
7451 end_label = gen_label_rtx ();
7453 /* Check if begin equals end. */
7454 cmp_result = gen_rtx_EQ (VOIDmode, begin, end);
7455 emit_jump_insn (gen_condjump (cmp_result, end_label));
7457 /* Load INC with the cache line size (rdhwr INC,$1). */
7458 inc = gen_reg_rtx (Pmode);
7459 emit_insn (PMODE_INSN (gen_rdhwr_synci_step, (inc)));
7461 /* Check if inc is 0. */
7462 cmp_result = gen_rtx_EQ (VOIDmode, inc, const0_rtx);
7463 emit_jump_insn (gen_condjump (cmp_result, end_label));
7465 /* Calculate mask. */
7466 mask = mips_force_unary (Pmode, NEG, inc);
7468 /* Mask out begin by mask. */
7469 begin = mips_force_binary (Pmode, AND, begin, mask);
7471 /* Calculate length. */
7472 length = mips_force_binary (Pmode, MINUS, end, begin);
7474 /* Loop back to here. */
7475 label = gen_label_rtx ();
7478 emit_insn (gen_synci (begin));
7480 /* Update length. */
7481 mips_emit_binary (MINUS, length, length, inc);
7484 mips_emit_binary (PLUS, begin, begin, inc);
7486 /* Check if length is greater than 0. */
7487 cmp_result = gen_rtx_GT (VOIDmode, length, const0_rtx);
7488 emit_jump_insn (gen_condjump (cmp_result, label));
7490 emit_label (end_label);
7493 /* Expand a QI or HI mode atomic memory operation.
7495 GENERATOR contains a pointer to the gen_* function that generates
7496 the SI mode underlying atomic operation using masks that we
7499 RESULT is the return register for the operation. Its value is NULL
7502 MEM is the location of the atomic access.
7504 OLDVAL is the first operand for the operation.
7506 NEWVAL is the optional second operand for the operation. Its value
7507 is NULL if unused. */
7510 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator,
7511 rtx result, rtx mem, rtx oldval, rtx newval)
7513 rtx orig_addr, memsi_addr, memsi, shift, shiftsi, unshifted_mask;
7514 rtx unshifted_mask_reg, mask, inverted_mask, si_op;
7516 enum machine_mode mode;
7518 mode = GET_MODE (mem);
7520 /* Compute the address of the containing SImode value. */
7521 orig_addr = force_reg (Pmode, XEXP (mem, 0));
7522 memsi_addr = mips_force_binary (Pmode, AND, orig_addr,
7523 force_reg (Pmode, GEN_INT (-4)));
7525 /* Create a memory reference for it. */
7526 memsi = gen_rtx_MEM (SImode, memsi_addr);
7527 set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER);
7528 MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem);
7530 /* Work out the byte offset of the QImode or HImode value,
7531 counting from the least significant byte. */
7532 shift = mips_force_binary (Pmode, AND, orig_addr, GEN_INT (3));
7533 if (TARGET_BIG_ENDIAN)
7534 mips_emit_binary (XOR, shift, shift, GEN_INT (mode == QImode ? 3 : 2));
7536 /* Multiply by eight to convert the shift value from bytes to bits. */
7537 mips_emit_binary (ASHIFT, shift, shift, GEN_INT (3));
7539 /* Make the final shift an SImode value, so that it can be used in
7540 SImode operations. */
7541 shiftsi = force_reg (SImode, gen_lowpart (SImode, shift));
7543 /* Set MASK to an inclusive mask of the QImode or HImode value. */
7544 unshifted_mask = GEN_INT (GET_MODE_MASK (mode));
7545 unshifted_mask_reg = force_reg (SImode, unshifted_mask);
7546 mask = mips_force_binary (SImode, ASHIFT, unshifted_mask_reg, shiftsi);
7548 /* Compute the equivalent exclusive mask. */
7549 inverted_mask = gen_reg_rtx (SImode);
7550 emit_insn (gen_rtx_SET (VOIDmode, inverted_mask,
7551 gen_rtx_NOT (SImode, mask)));
7553 /* Shift the old value into place. */
7554 if (oldval != const0_rtx)
7556 oldval = convert_modes (SImode, mode, oldval, true);
7557 oldval = force_reg (SImode, oldval);
7558 oldval = mips_force_binary (SImode, ASHIFT, oldval, shiftsi);
7561 /* Do the same for the new value. */
7562 if (newval && newval != const0_rtx)
7564 newval = convert_modes (SImode, mode, newval, true);
7565 newval = force_reg (SImode, newval);
7566 newval = mips_force_binary (SImode, ASHIFT, newval, shiftsi);
7569 /* Do the SImode atomic access. */
7571 res = gen_reg_rtx (SImode);
7573 si_op = generator.fn_6 (res, memsi, mask, inverted_mask, oldval, newval);
7575 si_op = generator.fn_5 (res, memsi, mask, inverted_mask, oldval);
7577 si_op = generator.fn_4 (memsi, mask, inverted_mask, oldval);
7583 /* Shift and convert the result. */
7584 mips_emit_binary (AND, res, res, mask);
7585 mips_emit_binary (LSHIFTRT, res, res, shiftsi);
7586 mips_emit_move (result, gen_lowpart (GET_MODE (result), res));
7590 /* Return true if it is possible to use left/right accesses for a
7591 bitfield of WIDTH bits starting BITPOS bits into BLKmode memory OP.
7592 When returning true, update *LEFT and *RIGHT as follows:
7594 *LEFT is a QImode reference to the first byte if big endian or
7595 the last byte if little endian. This address can be used in the
7596 left-side instructions (LWL, SWL, LDL, SDL).
7598 *RIGHT is a QImode reference to the opposite end of the field and
7599 can be used in the patterning right-side instruction. */
7602 mips_get_unaligned_mem (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos,
7603 rtx *left, rtx *right)
7607 /* Check that the size is valid. */
7608 if (width != 32 && (!TARGET_64BIT || width != 64))
7611 /* We can only access byte-aligned values. Since we are always passed
7612 a reference to the first byte of the field, it is not necessary to
7613 do anything with BITPOS after this check. */
7614 if (bitpos % BITS_PER_UNIT != 0)
7617 /* Reject aligned bitfields: we want to use a normal load or store
7618 instead of a left/right pair. */
7619 if (MEM_ALIGN (op) >= width)
7622 /* Get references to both ends of the field. */
7623 first = adjust_address (op, QImode, 0);
7624 last = adjust_address (op, QImode, width / BITS_PER_UNIT - 1);
7626 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
7627 correspond to the MSB and RIGHT to the LSB. */
7628 if (TARGET_BIG_ENDIAN)
7629 *left = first, *right = last;
7631 *left = last, *right = first;
7636 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
7637 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
7638 the operation is the equivalent of:
7640 (set DEST (*_extract SRC WIDTH BITPOS))
7642 Return true on success. */
7645 mips_expand_ext_as_unaligned_load (rtx dest, rtx src, HOST_WIDE_INT width,
7646 HOST_WIDE_INT bitpos, bool unsigned_p)
7648 rtx left, right, temp;
7649 rtx dest1 = NULL_RTX;
7651 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
7652 be a DImode, create a new temp and emit a zero extend at the end. */
7653 if (GET_MODE (dest) == DImode
7655 && GET_MODE_BITSIZE (SImode) == width)
7658 dest = gen_reg_rtx (SImode);
7661 if (!mips_get_unaligned_mem (src, width, bitpos, &left, &right))
7664 temp = gen_reg_rtx (GET_MODE (dest));
7665 if (GET_MODE (dest) == DImode)
7667 emit_insn (gen_mov_ldl (temp, src, left));
7668 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
7672 emit_insn (gen_mov_lwl (temp, src, left));
7673 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
7676 /* If we were loading 32bits and the original register was DI then
7677 sign/zero extend into the orignal dest. */
7681 emit_insn (gen_zero_extendsidi2 (dest1, dest));
7683 emit_insn (gen_extendsidi2 (dest1, dest));
7688 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
7689 BITPOS and SRC are the operands passed to the expander; the operation
7690 is the equivalent of:
7692 (set (zero_extract DEST WIDTH BITPOS) SRC)
7694 Return true on success. */
7697 mips_expand_ins_as_unaligned_store (rtx dest, rtx src, HOST_WIDE_INT width,
7698 HOST_WIDE_INT bitpos)
7701 enum machine_mode mode;
7703 if (!mips_get_unaligned_mem (dest, width, bitpos, &left, &right))
7706 mode = mode_for_size (width, MODE_INT, 0);
7707 src = gen_lowpart (mode, src);
7710 emit_insn (gen_mov_sdl (dest, src, left));
7711 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
7715 emit_insn (gen_mov_swl (dest, src, left));
7716 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
7721 /* Return true if X is a MEM with the same size as MODE. */
7724 mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
7727 && MEM_SIZE_KNOWN_P (x)
7728 && MEM_SIZE (x) == GET_MODE_SIZE (mode));
7731 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
7732 source of an "ext" instruction or the destination of an "ins"
7733 instruction. OP must be a register operand and the following
7734 conditions must hold:
7736 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
7737 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7738 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7740 Also reject lengths equal to a word as they are better handled
7741 by the move patterns. */
7744 mips_use_ins_ext_p (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos)
7746 if (!ISA_HAS_EXT_INS
7747 || !register_operand (op, VOIDmode)
7748 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
7751 if (!IN_RANGE (width, 1, GET_MODE_BITSIZE (GET_MODE (op)) - 1))
7754 if (bitpos < 0 || bitpos + width > GET_MODE_BITSIZE (GET_MODE (op)))
7760 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
7761 operation if MAXLEN is the maxium length of consecutive bits that
7762 can make up MASK. MODE is the mode of the operation. See
7763 mask_low_and_shift_len for the actual definition. */
7766 mask_low_and_shift_p (enum machine_mode mode, rtx mask, rtx shift, int maxlen)
7768 return IN_RANGE (mask_low_and_shift_len (mode, mask, shift), 1, maxlen);
7771 /* Return true iff OP1 and OP2 are valid operands together for the
7772 *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider,
7773 see the table in the comment before the pattern. */
7776 and_operands_ok (enum machine_mode mode, rtx op1, rtx op2)
7778 return (memory_operand (op1, mode)
7779 ? and_load_operand (op2, mode)
7780 : and_reg_operand (op2, mode));
7783 /* The canonical form of a mask-low-and-shift-left operation is
7784 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
7785 cleared. Thus we need to shift MASK to the right before checking if it
7786 is a valid mask value. MODE is the mode of the operation. If true
7787 return the length of the mask, otherwise return -1. */
7790 mask_low_and_shift_len (enum machine_mode mode, rtx mask, rtx shift)
7792 HOST_WIDE_INT shval;
7794 shval = INTVAL (shift) & (GET_MODE_BITSIZE (mode) - 1);
7795 return exact_log2 ((UINTVAL (mask) >> shval) + 1);
7798 /* Return true if -msplit-addresses is selected and should be honored.
7800 -msplit-addresses is a half-way house between explicit relocations
7801 and the traditional assembler macros. It can split absolute 32-bit
7802 symbolic constants into a high/lo_sum pair but uses macros for other
7805 Like explicit relocation support for REL targets, it relies
7806 on GNU extensions in the assembler and the linker.
7808 Although this code should work for -O0, it has traditionally
7809 been treated as an optimization. */
7812 mips_split_addresses_p (void)
7814 return (TARGET_SPLIT_ADDRESSES
7818 && !ABI_HAS_64BIT_SYMBOLS);
7821 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
7824 mips_init_relocs (void)
7826 memset (mips_split_p, '\0', sizeof (mips_split_p));
7827 memset (mips_split_hi_p, '\0', sizeof (mips_split_hi_p));
7828 memset (mips_use_pcrel_pool_p, '\0', sizeof (mips_use_pcrel_pool_p));
7829 memset (mips_hi_relocs, '\0', sizeof (mips_hi_relocs));
7830 memset (mips_lo_relocs, '\0', sizeof (mips_lo_relocs));
7832 if (TARGET_MIPS16_PCREL_LOADS)
7833 mips_use_pcrel_pool_p[SYMBOL_ABSOLUTE] = true;
7836 if (ABI_HAS_64BIT_SYMBOLS)
7838 if (TARGET_EXPLICIT_RELOCS)
7840 mips_split_p[SYMBOL_64_HIGH] = true;
7841 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
7842 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
7844 mips_split_p[SYMBOL_64_MID] = true;
7845 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
7846 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
7848 mips_split_p[SYMBOL_64_LOW] = true;
7849 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
7850 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
7852 mips_split_p[SYMBOL_ABSOLUTE] = true;
7853 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
7858 if (TARGET_EXPLICIT_RELOCS
7859 || mips_split_addresses_p ()
7862 mips_split_p[SYMBOL_ABSOLUTE] = true;
7863 mips_hi_relocs[SYMBOL_ABSOLUTE] = "%hi(";
7864 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
7871 /* The high part is provided by a pseudo copy of $gp. */
7872 mips_split_p[SYMBOL_GP_RELATIVE] = true;
7873 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gprel(";
7875 else if (TARGET_EXPLICIT_RELOCS)
7876 /* Small data constants are kept whole until after reload,
7877 then lowered by mips_rewrite_small_data. */
7878 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gp_rel(";
7880 if (TARGET_EXPLICIT_RELOCS)
7882 mips_split_p[SYMBOL_GOT_PAGE_OFST] = true;
7885 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
7886 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%got_ofst(";
7890 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
7891 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%lo(";
7894 /* Expose the use of $28 as soon as possible. */
7895 mips_split_hi_p[SYMBOL_GOT_PAGE_OFST] = true;
7899 /* The HIGH and LO_SUM are matched by special .md patterns. */
7900 mips_split_p[SYMBOL_GOT_DISP] = true;
7902 mips_split_p[SYMBOL_GOTOFF_DISP] = true;
7903 mips_hi_relocs[SYMBOL_GOTOFF_DISP] = "%got_hi(";
7904 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_lo(";
7906 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
7907 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
7908 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
7913 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_disp(";
7915 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got(";
7916 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
7918 /* Expose the use of $28 as soon as possible. */
7919 mips_split_p[SYMBOL_GOT_DISP] = true;
7925 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
7926 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
7927 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
7930 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
7931 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
7933 if (TARGET_MIPS16_PCREL_LOADS)
7935 mips_use_pcrel_pool_p[SYMBOL_DTPREL] = true;
7936 mips_use_pcrel_pool_p[SYMBOL_TPREL] = true;
7940 mips_split_p[SYMBOL_DTPREL] = true;
7941 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
7942 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
7944 mips_split_p[SYMBOL_TPREL] = true;
7945 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
7946 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
7949 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
7950 mips_lo_relocs[SYMBOL_HALF] = "%half(";
7953 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
7954 in context CONTEXT. RELOCS is the array of relocations to use. */
7957 mips_print_operand_reloc (FILE *file, rtx op, enum mips_symbol_context context,
7958 const char **relocs)
7960 enum mips_symbol_type symbol_type;
7963 symbol_type = mips_classify_symbolic_expression (op, context);
7964 gcc_assert (relocs[symbol_type]);
7966 fputs (relocs[symbol_type], file);
7967 output_addr_const (file, mips_strip_unspec_address (op));
7968 for (p = relocs[symbol_type]; *p != 0; p++)
7973 /* Start a new block with the given asm switch enabled. If we need
7974 to print a directive, emit PREFIX before it and SUFFIX after it. */
7977 mips_push_asm_switch_1 (struct mips_asm_switch *asm_switch,
7978 const char *prefix, const char *suffix)
7980 if (asm_switch->nesting_level == 0)
7981 fprintf (asm_out_file, "%s.set\tno%s%s", prefix, asm_switch->name, suffix);
7982 asm_switch->nesting_level++;
7985 /* Likewise, but end a block. */
7988 mips_pop_asm_switch_1 (struct mips_asm_switch *asm_switch,
7989 const char *prefix, const char *suffix)
7991 gcc_assert (asm_switch->nesting_level);
7992 asm_switch->nesting_level--;
7993 if (asm_switch->nesting_level == 0)
7994 fprintf (asm_out_file, "%s.set\t%s%s", prefix, asm_switch->name, suffix);
7997 /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1
7998 that either print a complete line or print nothing. */
8001 mips_push_asm_switch (struct mips_asm_switch *asm_switch)
8003 mips_push_asm_switch_1 (asm_switch, "\t", "\n");
8007 mips_pop_asm_switch (struct mips_asm_switch *asm_switch)
8009 mips_pop_asm_switch_1 (asm_switch, "\t", "\n");
8012 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
8013 The punctuation characters are:
8015 '(' Start a nested ".set noreorder" block.
8016 ')' End a nested ".set noreorder" block.
8017 '[' Start a nested ".set noat" block.
8018 ']' End a nested ".set noat" block.
8019 '<' Start a nested ".set nomacro" block.
8020 '>' End a nested ".set nomacro" block.
8021 '*' Behave like %(%< if generating a delayed-branch sequence.
8022 '#' Print a nop if in a ".set noreorder" block.
8023 '/' Like '#', but do nothing within a delayed-branch sequence.
8024 '?' Print "l" if mips_branch_likely is true
8025 '~' Print a nop if mips_branch_likely is true
8026 '.' Print the name of the register with a hard-wired zero (zero or $0).
8027 '@' Print the name of the assembler temporary register (at or $1).
8028 '^' Print the name of the pic call-through register (t9 or $25).
8029 '+' Print the name of the gp register (usually gp or $28).
8030 '$' Print the name of the stack pointer register (sp or $29).
8031 ':' Print "c" to use the compact version if the delay slot is a nop.
8032 '!' Print "s" to use the short version if the delay slot contains a
8035 See also mips_init_print_operand_pucnt. */
8038 mips_print_operand_punctuation (FILE *file, int ch)
8043 mips_push_asm_switch_1 (&mips_noreorder, "", "\n\t");
8047 mips_pop_asm_switch_1 (&mips_noreorder, "\n\t", "");
8051 mips_push_asm_switch_1 (&mips_noat, "", "\n\t");
8055 mips_pop_asm_switch_1 (&mips_noat, "\n\t", "");
8059 mips_push_asm_switch_1 (&mips_nomacro, "", "\n\t");
8063 mips_pop_asm_switch_1 (&mips_nomacro, "\n\t", "");
8067 if (final_sequence != 0)
8069 mips_print_operand_punctuation (file, '(');
8070 mips_print_operand_punctuation (file, '<');
8075 if (mips_noreorder.nesting_level > 0)
8076 fputs ("\n\tnop", file);
8080 /* Print an extra newline so that the delayed insn is separated
8081 from the following ones. This looks neater and is consistent
8082 with non-nop delayed sequences. */
8083 if (mips_noreorder.nesting_level > 0 && final_sequence == 0)
8084 fputs ("\n\tnop\n", file);
8088 if (mips_branch_likely)
8093 if (mips_branch_likely)
8094 fputs ("\n\tnop", file);
8098 fputs (reg_names[GP_REG_FIRST + 0], file);
8102 fputs (reg_names[AT_REGNUM], file);
8106 fputs (reg_names[PIC_FUNCTION_ADDR_REGNUM], file);
8110 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
8114 fputs (reg_names[STACK_POINTER_REGNUM], file);
8118 /* When final_sequence is 0, the delay slot will be a nop. We can
8119 use the compact version for microMIPS. */
8120 if (final_sequence == 0)
8125 /* If the delay slot instruction is short, then use the
8127 if (final_sequence == 0
8128 || get_attr_length (XVECEXP (final_sequence, 0, 1)) == 2)
8138 /* Initialize mips_print_operand_punct. */
8141 mips_init_print_operand_punct (void)
8145 for (p = "()[]<>*#/?~.@^+$:!"; *p; p++)
8146 mips_print_operand_punct[(unsigned char) *p] = true;
8149 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
8150 associated with condition CODE. Print the condition part of the
8154 mips_print_int_branch_condition (FILE *file, enum rtx_code code, int letter)
8168 /* Conveniently, the MIPS names for these conditions are the same
8169 as their RTL equivalents. */
8170 fputs (GET_RTX_NAME (code), file);
8174 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
8179 /* Likewise floating-point branches. */
8182 mips_print_float_branch_condition (FILE *file, enum rtx_code code, int letter)
8187 fputs ("c1f", file);
8191 fputs ("c1t", file);
8195 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
8200 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
8203 mips_print_operand_punct_valid_p (unsigned char code)
8205 return mips_print_operand_punct[code];
8208 /* Implement TARGET_PRINT_OPERAND. The MIPS-specific operand codes are:
8210 'X' Print CONST_INT OP in hexadecimal format.
8211 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
8212 'd' Print CONST_INT OP in decimal.
8213 'm' Print one less than CONST_INT OP in decimal.
8214 'h' Print the high-part relocation associated with OP, after stripping
8216 'R' Print the low-part relocation associated with OP.
8217 'C' Print the integer branch condition for comparison OP.
8218 'N' Print the inverse of the integer branch condition for comparison OP.
8219 'F' Print the FPU branch condition for comparison OP.
8220 'W' Print the inverse of the FPU branch condition for comparison OP.
8221 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
8222 'z' for (eq:?I ...), 'n' for (ne:?I ...).
8223 't' Like 'T', but with the EQ/NE cases reversed
8224 'Y' Print mips_fp_conditions[INTVAL (OP)]
8225 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
8226 'q' Print a DSP accumulator register.
8227 'D' Print the second part of a double-word register or memory operand.
8228 'L' Print the low-order register in a double-word register operand.
8229 'M' Print high-order register in a double-word register operand.
8230 'z' Print $0 if OP is zero, otherwise print OP normally.
8231 'b' Print the address of a memory operand, without offset. */
8234 mips_print_operand (FILE *file, rtx op, int letter)
8238 if (mips_print_operand_punct_valid_p (letter))
8240 mips_print_operand_punctuation (file, letter);
8245 code = GET_CODE (op);
8250 if (CONST_INT_P (op))
8251 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
8253 output_operand_lossage ("invalid use of '%%%c'", letter);
8257 if (CONST_INT_P (op))
8258 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op) & 0xffff);
8260 output_operand_lossage ("invalid use of '%%%c'", letter);
8264 if (CONST_INT_P (op))
8265 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op));
8267 output_operand_lossage ("invalid use of '%%%c'", letter);
8271 if (CONST_INT_P (op))
8272 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op) - 1);
8274 output_operand_lossage ("invalid use of '%%%c'", letter);
8280 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_hi_relocs);
8284 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_lo_relocs);
8288 mips_print_int_branch_condition (file, code, letter);
8292 mips_print_int_branch_condition (file, reverse_condition (code), letter);
8296 mips_print_float_branch_condition (file, code, letter);
8300 mips_print_float_branch_condition (file, reverse_condition (code),
8307 int truth = (code == NE) == (letter == 'T');
8308 fputc ("zfnt"[truth * 2 + ST_REG_P (REGNO (XEXP (op, 0)))], file);
8313 if (code == CONST_INT && UINTVAL (op) < ARRAY_SIZE (mips_fp_conditions))
8314 fputs (mips_fp_conditions[UINTVAL (op)], file);
8316 output_operand_lossage ("'%%%c' is not a valid operand prefix",
8323 mips_print_operand (file, op, 0);
8329 if (code == REG && MD_REG_P (REGNO (op)))
8330 fprintf (file, "$ac0");
8331 else if (code == REG && DSP_ACC_REG_P (REGNO (op)))
8332 fprintf (file, "$ac%c", reg_names[REGNO (op)][3]);
8334 output_operand_lossage ("invalid use of '%%%c'", letter);
8342 unsigned int regno = REGNO (op);
8343 if ((letter == 'M' && TARGET_LITTLE_ENDIAN)
8344 || (letter == 'L' && TARGET_BIG_ENDIAN)
8347 else if (letter && letter != 'z' && letter != 'M' && letter != 'L')
8348 output_operand_lossage ("invalid use of '%%%c'", letter);
8349 /* We need to print $0 .. $31 for COP0 registers. */
8350 if (COP0_REG_P (regno))
8351 fprintf (file, "$%s", ®_names[regno][4]);
8353 fprintf (file, "%s", reg_names[regno]);
8359 output_address (plus_constant (Pmode, XEXP (op, 0), 4));
8360 else if (letter == 'b')
8362 gcc_assert (REG_P (XEXP (op, 0)));
8363 mips_print_operand (file, XEXP (op, 0), 0);
8365 else if (letter && letter != 'z')
8366 output_operand_lossage ("invalid use of '%%%c'", letter);
8368 output_address (XEXP (op, 0));
8372 if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
8373 fputs (reg_names[GP_REG_FIRST], file);
8374 else if (letter && letter != 'z')
8375 output_operand_lossage ("invalid use of '%%%c'", letter);
8376 else if (CONST_GP_P (op))
8377 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
8379 output_addr_const (file, mips_strip_unspec_address (op));
8385 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
8388 mips_print_operand_address (FILE *file, rtx x)
8390 struct mips_address_info addr;
8392 if (mips_classify_address (&addr, x, word_mode, true))
8396 mips_print_operand (file, addr.offset, 0);
8397 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
8400 case ADDRESS_LO_SUM:
8401 mips_print_operand_reloc (file, addr.offset, SYMBOL_CONTEXT_MEM,
8403 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
8406 case ADDRESS_CONST_INT:
8407 output_addr_const (file, x);
8408 fprintf (file, "(%s)", reg_names[GP_REG_FIRST]);
8411 case ADDRESS_SYMBOLIC:
8412 output_addr_const (file, mips_strip_unspec_address (x));
8418 /* Implement TARGET_ENCODE_SECTION_INFO. */
8421 mips_encode_section_info (tree decl, rtx rtl, int first)
8423 default_encode_section_info (decl, rtl, first);
8425 if (TREE_CODE (decl) == FUNCTION_DECL)
8427 rtx symbol = XEXP (rtl, 0);
8428 tree type = TREE_TYPE (decl);
8430 /* Encode whether the symbol is short or long. */
8431 if ((TARGET_LONG_CALLS && !mips_near_type_p (type))
8432 || mips_far_type_p (type))
8433 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
8437 /* Implement TARGET_SELECT_RTX_SECTION. */
8440 mips_select_rtx_section (enum machine_mode mode, rtx x,
8441 unsigned HOST_WIDE_INT align)
8443 /* ??? Consider using mergeable small data sections. */
8444 if (mips_rtx_constant_in_small_data_p (mode))
8445 return get_named_section (NULL, ".sdata", 0);
8447 return default_elf_select_rtx_section (mode, x, align);
8450 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
8452 The complication here is that, with the combination TARGET_ABICALLS
8453 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
8454 absolute addresses, and should therefore not be included in the
8455 read-only part of a DSO. Handle such cases by selecting a normal
8456 data section instead of a read-only one. The logic apes that in
8457 default_function_rodata_section. */
8460 mips_function_rodata_section (tree decl)
8462 if (!TARGET_ABICALLS || TARGET_ABSOLUTE_ABICALLS || TARGET_GPWORD)
8463 return default_function_rodata_section (decl);
8465 if (decl && DECL_SECTION_NAME (decl))
8467 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
8468 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
8470 char *rname = ASTRDUP (name);
8472 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
8474 else if (flag_function_sections
8475 && flag_data_sections
8476 && strncmp (name, ".text.", 6) == 0)
8478 char *rname = ASTRDUP (name);
8479 memcpy (rname + 1, "data", 4);
8480 return get_section (rname, SECTION_WRITE, decl);
8483 return data_section;
8486 /* Implement TARGET_IN_SMALL_DATA_P. */
8489 mips_in_small_data_p (const_tree decl)
8491 unsigned HOST_WIDE_INT size;
8493 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
8496 /* We don't yet generate small-data references for -mabicalls
8497 or VxWorks RTP code. See the related -G handling in
8498 mips_option_override. */
8499 if (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
8502 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
8506 /* Reject anything that isn't in a known small-data section. */
8507 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
8508 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
8511 /* If a symbol is defined externally, the assembler will use the
8512 usual -G rules when deciding how to implement macros. */
8513 if (mips_lo_relocs[SYMBOL_GP_RELATIVE] || !DECL_EXTERNAL (decl))
8516 else if (TARGET_EMBEDDED_DATA)
8518 /* Don't put constants into the small data section: we want them
8519 to be in ROM rather than RAM. */
8520 if (TREE_CODE (decl) != VAR_DECL)
8523 if (TREE_READONLY (decl)
8524 && !TREE_SIDE_EFFECTS (decl)
8525 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
8529 /* Enforce -mlocal-sdata. */
8530 if (!TARGET_LOCAL_SDATA && !TREE_PUBLIC (decl))
8533 /* Enforce -mextern-sdata. */
8534 if (!TARGET_EXTERN_SDATA && DECL_P (decl))
8536 if (DECL_EXTERNAL (decl))
8538 if (DECL_COMMON (decl) && DECL_INITIAL (decl) == NULL)
8542 /* We have traditionally not treated zero-sized objects as small data,
8543 so this is now effectively part of the ABI. */
8544 size = int_size_in_bytes (TREE_TYPE (decl));
8545 return size > 0 && size <= mips_small_data_threshold;
8548 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
8549 anchors for small data: the GP register acts as an anchor in that
8550 case. We also don't want to use them for PC-relative accesses,
8551 where the PC acts as an anchor. */
8554 mips_use_anchors_for_symbol_p (const_rtx symbol)
8556 switch (mips_classify_symbol (symbol, SYMBOL_CONTEXT_MEM))
8558 case SYMBOL_PC_RELATIVE:
8559 case SYMBOL_GP_RELATIVE:
8563 return default_use_anchors_for_symbol_p (symbol);
8567 /* The MIPS debug format wants all automatic variables and arguments
8568 to be in terms of the virtual frame pointer (stack pointer before
8569 any adjustment in the function), while the MIPS 3.0 linker wants
8570 the frame pointer to be the stack pointer after the initial
8571 adjustment. So, we do the adjustment here. The arg pointer (which
8572 is eliminated) points to the virtual frame pointer, while the frame
8573 pointer (which may be eliminated) points to the stack pointer after
8574 the initial adjustments. */
8577 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
8579 rtx offset2 = const0_rtx;
8580 rtx reg = eliminate_constant_term (addr, &offset2);
8583 offset = INTVAL (offset2);
8585 if (reg == stack_pointer_rtx
8586 || reg == frame_pointer_rtx
8587 || reg == hard_frame_pointer_rtx)
8589 offset -= cfun->machine->frame.total_size;
8590 if (reg == hard_frame_pointer_rtx)
8591 offset += cfun->machine->frame.hard_frame_pointer_offset;
8597 /* Implement ASM_OUTPUT_EXTERNAL. */
8600 mips_output_external (FILE *file, tree decl, const char *name)
8602 default_elf_asm_output_external (file, decl, name);
8604 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
8605 set in order to avoid putting out names that are never really
8607 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
8609 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
8611 /* When using assembler macros, emit .extern directives for
8612 all small-data externs so that the assembler knows how
8615 In most cases it would be safe (though pointless) to emit
8616 .externs for other symbols too. One exception is when an
8617 object is within the -G limit but declared by the user to
8618 be in a section other than .sbss or .sdata. */
8619 fputs ("\t.extern\t", file);
8620 assemble_name (file, name);
8621 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n",
8622 int_size_in_bytes (TREE_TYPE (decl)));
8627 /* Implement TARGET_ASM_OUTPUT_SOURCE_FILENAME. */
8630 mips_output_filename (FILE *stream, const char *name)
8632 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
8634 if (write_symbols == DWARF2_DEBUG)
8636 else if (mips_output_filename_first_time)
8638 mips_output_filename_first_time = 0;
8639 num_source_filenames += 1;
8640 current_function_file = name;
8641 fprintf (stream, "\t.file\t%d ", num_source_filenames);
8642 output_quoted_string (stream, name);
8643 putc ('\n', stream);
8645 /* If we are emitting stabs, let dbxout.c handle this (except for
8646 the mips_output_filename_first_time case). */
8647 else if (write_symbols == DBX_DEBUG)
8649 else if (name != current_function_file
8650 && strcmp (name, current_function_file) != 0)
8652 num_source_filenames += 1;
8653 current_function_file = name;
8654 fprintf (stream, "\t.file\t%d ", num_source_filenames);
8655 output_quoted_string (stream, name);
8656 putc ('\n', stream);
8660 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
8662 static void ATTRIBUTE_UNUSED
8663 mips_output_dwarf_dtprel (FILE *file, int size, rtx x)
8668 fputs ("\t.dtprelword\t", file);
8672 fputs ("\t.dtpreldword\t", file);
8678 output_addr_const (file, x);
8679 fputs ("+0x8000", file);
8682 /* Implement TARGET_DWARF_REGISTER_SPAN. */
8685 mips_dwarf_register_span (rtx reg)
8688 enum machine_mode mode;
8690 /* By default, GCC maps increasing register numbers to increasing
8691 memory locations, but paired FPRs are always little-endian,
8692 regardless of the prevailing endianness. */
8693 mode = GET_MODE (reg);
8694 if (FP_REG_P (REGNO (reg))
8695 && TARGET_BIG_ENDIAN
8696 && MAX_FPRS_PER_FMT > 1
8697 && GET_MODE_SIZE (mode) > UNITS_PER_FPREG)
8699 gcc_assert (GET_MODE_SIZE (mode) == UNITS_PER_HWFPVALUE);
8700 high = mips_subword (reg, true);
8701 low = mips_subword (reg, false);
8702 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, high, low));
8708 /* DSP ALU can bypass data with no delays for the following pairs. */
8709 enum insn_code dspalu_bypass_table[][2] =
8711 {CODE_FOR_mips_addsc, CODE_FOR_mips_addwc},
8712 {CODE_FOR_mips_cmpu_eq_qb, CODE_FOR_mips_pick_qb},
8713 {CODE_FOR_mips_cmpu_lt_qb, CODE_FOR_mips_pick_qb},
8714 {CODE_FOR_mips_cmpu_le_qb, CODE_FOR_mips_pick_qb},
8715 {CODE_FOR_mips_cmp_eq_ph, CODE_FOR_mips_pick_ph},
8716 {CODE_FOR_mips_cmp_lt_ph, CODE_FOR_mips_pick_ph},
8717 {CODE_FOR_mips_cmp_le_ph, CODE_FOR_mips_pick_ph},
8718 {CODE_FOR_mips_wrdsp, CODE_FOR_mips_insv}
8722 mips_dspalu_bypass_p (rtx out_insn, rtx in_insn)
8725 int num_bypass = ARRAY_SIZE (dspalu_bypass_table);
8726 enum insn_code out_icode = (enum insn_code) INSN_CODE (out_insn);
8727 enum insn_code in_icode = (enum insn_code) INSN_CODE (in_insn);
8729 for (i = 0; i < num_bypass; i++)
8731 if (out_icode == dspalu_bypass_table[i][0]
8732 && in_icode == dspalu_bypass_table[i][1])
8738 /* Implement ASM_OUTPUT_ASCII. */
8741 mips_output_ascii (FILE *stream, const char *string, size_t len)
8747 fprintf (stream, "\t.ascii\t\"");
8748 for (i = 0; i < len; i++)
8752 c = (unsigned char) string[i];
8755 if (c == '\\' || c == '\"')
8757 putc ('\\', stream);
8765 fprintf (stream, "\\%03o", c);
8769 if (cur_pos > 72 && i+1 < len)
8772 fprintf (stream, "\"\n\t.ascii\t\"");
8775 fprintf (stream, "\"\n");
8778 /* Return the pseudo-op for full SYMBOL_(D)TPREL address *ADDR.
8779 Update *ADDR with the operand that should be printed. */
8782 mips_output_tls_reloc_directive (rtx *addr)
8784 enum mips_symbol_type type;
8786 type = mips_classify_symbolic_expression (*addr, SYMBOL_CONTEXT_LEA);
8787 *addr = mips_strip_unspec_address (*addr);
8791 return Pmode == SImode ? ".dtprelword\t%0" : ".dtpreldword\t%0";
8794 return Pmode == SImode ? ".tprelword\t%0" : ".tpreldword\t%0";
8801 /* Emit either a label, .comm, or .lcomm directive. When using assembler
8802 macros, mark the symbol as written so that mips_asm_output_external
8803 won't emit an .extern for it. STREAM is the output file, NAME is the
8804 name of the symbol, INIT_STRING is the string that should be written
8805 before the symbol and FINAL_STRING is the string that should be
8806 written after it. FINAL_STRING is a printf format that consumes the
8807 remaining arguments. */
8810 mips_declare_object (FILE *stream, const char *name, const char *init_string,
8811 const char *final_string, ...)
8815 fputs (init_string, stream);
8816 assemble_name (stream, name);
8817 va_start (ap, final_string);
8818 vfprintf (stream, final_string, ap);
8821 if (!TARGET_EXPLICIT_RELOCS)
8823 tree name_tree = get_identifier (name);
8824 TREE_ASM_WRITTEN (name_tree) = 1;
8828 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
8829 NAME is the name of the object and ALIGN is the required alignment
8830 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
8831 alignment argument. */
8834 mips_declare_common_object (FILE *stream, const char *name,
8835 const char *init_string,
8836 unsigned HOST_WIDE_INT size,
8837 unsigned int align, bool takes_alignment_p)
8839 if (!takes_alignment_p)
8841 size += (align / BITS_PER_UNIT) - 1;
8842 size -= size % (align / BITS_PER_UNIT);
8843 mips_declare_object (stream, name, init_string,
8844 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
8847 mips_declare_object (stream, name, init_string,
8848 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
8849 size, align / BITS_PER_UNIT);
8852 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
8853 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
8856 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
8857 unsigned HOST_WIDE_INT size,
8860 /* If the target wants uninitialized const declarations in
8861 .rdata then don't put them in .comm. */
8862 if (TARGET_EMBEDDED_DATA
8863 && TARGET_UNINIT_CONST_IN_RODATA
8864 && TREE_CODE (decl) == VAR_DECL
8865 && TREE_READONLY (decl)
8866 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
8868 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
8869 targetm.asm_out.globalize_label (stream, name);
8871 switch_to_section (readonly_data_section);
8872 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
8873 mips_declare_object (stream, name, "",
8874 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
8878 mips_declare_common_object (stream, name, "\n\t.comm\t",
8882 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8883 extern int size_directive_output;
8885 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
8886 definitions except that it uses mips_declare_object to emit the label. */
8889 mips_declare_object_name (FILE *stream, const char *name,
8890 tree decl ATTRIBUTE_UNUSED)
8892 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8893 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
8896 size_directive_output = 0;
8897 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
8901 size_directive_output = 1;
8902 size = int_size_in_bytes (TREE_TYPE (decl));
8903 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8906 mips_declare_object (stream, name, "", ":\n");
8909 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
8912 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
8916 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
8917 if (!flag_inhibit_size_directive
8918 && DECL_SIZE (decl) != 0
8921 && DECL_INITIAL (decl) == error_mark_node
8922 && !size_directive_output)
8926 size_directive_output = 1;
8927 size = int_size_in_bytes (TREE_TYPE (decl));
8928 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8933 /* Return the FOO in the name of the ".mdebug.FOO" section associated
8934 with the current ABI. */
8937 mips_mdebug_abi_name (void)
8950 return TARGET_64BIT ? "eabi64" : "eabi32";
8956 /* Implement TARGET_ASM_FILE_START. */
8959 mips_file_start (void)
8961 default_file_start ();
8963 /* Generate a special section to describe the ABI switches used to
8964 produce the resultant binary. */
8966 /* Record the ABI itself. Modern versions of binutils encode
8967 this information in the ELF header flags, but GDB needs the
8968 information in order to correctly debug binaries produced by
8969 older binutils. See the function mips_gdbarch_init in
8971 fprintf (asm_out_file, "\t.section .mdebug.%s\n\t.previous\n",
8972 mips_mdebug_abi_name ());
8974 /* There is no ELF header flag to distinguish long32 forms of the
8975 EABI from long64 forms. Emit a special section to help tools
8976 such as GDB. Do the same for o64, which is sometimes used with
8978 if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
8979 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n"
8980 "\t.previous\n", TARGET_LONG64 ? 64 : 32);
8982 /* Record the NaN encoding. */
8983 if (HAVE_AS_NAN || mips_nan != MIPS_IEEE_754_DEFAULT)
8984 fprintf (asm_out_file, "\t.nan\t%s\n",
8985 mips_nan == MIPS_IEEE_754_2008 ? "2008" : "legacy");
8987 #ifdef HAVE_AS_GNU_ATTRIBUTE
8991 /* No floating-point operations, -mno-float. */
8992 if (TARGET_NO_FLOAT)
8994 /* Soft-float code, -msoft-float. */
8995 else if (!TARGET_HARD_FLOAT_ABI)
8997 /* Single-float code, -msingle-float. */
8998 else if (!TARGET_DOUBLE_FLOAT)
9000 /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64. */
9001 else if (!TARGET_64BIT && TARGET_FLOAT64)
9003 /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */
9007 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n", attr);
9011 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
9012 if (TARGET_ABICALLS)
9014 fprintf (asm_out_file, "\t.abicalls\n");
9015 if (TARGET_ABICALLS_PIC0)
9016 fprintf (asm_out_file, "\t.option\tpic0\n");
9019 if (flag_verbose_asm)
9020 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
9022 mips_small_data_threshold, mips_arch_info->name, mips_isa);
9025 /* Implement TARGET_ASM_CODE_END. */
9028 mips_code_end (void)
9030 mips_finish_stub (&mips16_rdhwr_stub);
9031 mips_finish_stub (&mips16_get_fcsr_stub);
9032 mips_finish_stub (&mips16_set_fcsr_stub);
9035 /* Make the last instruction frame-related and note that it performs
9036 the operation described by FRAME_PATTERN. */
9039 mips_set_frame_expr (rtx frame_pattern)
9043 insn = get_last_insn ();
9044 RTX_FRAME_RELATED_P (insn) = 1;
9045 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
9050 /* Return a frame-related rtx that stores REG at MEM.
9051 REG must be a single register. */
9054 mips_frame_set (rtx mem, rtx reg)
9058 set = gen_rtx_SET (VOIDmode, mem, reg);
9059 RTX_FRAME_RELATED_P (set) = 1;
9064 /* Record that the epilogue has restored call-saved register REG. */
9067 mips_add_cfa_restore (rtx reg)
9069 mips_epilogue.cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg,
9070 mips_epilogue.cfa_restores);
9073 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
9074 mips16e_s2_s8_regs[X], it must also save the registers in indexes
9075 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
9076 static const unsigned char mips16e_s2_s8_regs[] = {
9077 30, 23, 22, 21, 20, 19, 18
9079 static const unsigned char mips16e_a0_a3_regs[] = {
9083 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
9084 ordered from the uppermost in memory to the lowest in memory. */
9085 static const unsigned char mips16e_save_restore_regs[] = {
9086 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
9089 /* Return the index of the lowest X in the range [0, SIZE) for which
9090 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
9093 mips16e_find_first_register (unsigned int mask, const unsigned char *regs,
9098 for (i = 0; i < size; i++)
9099 if (BITSET_P (mask, regs[i]))
9105 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
9106 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
9107 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
9108 is true for all indexes (X, SIZE). */
9111 mips16e_mask_registers (unsigned int *mask_ptr, const unsigned char *regs,
9112 unsigned int size, unsigned int *num_regs_ptr)
9116 i = mips16e_find_first_register (*mask_ptr, regs, size);
9117 for (i++; i < size; i++)
9118 if (!BITSET_P (*mask_ptr, regs[i]))
9121 *mask_ptr |= 1 << regs[i];
9125 /* Return a simplified form of X using the register values in REG_VALUES.
9126 REG_VALUES[R] is the last value assigned to hard register R, or null
9127 if R has not been modified.
9129 This function is rather limited, but is good enough for our purposes. */
9132 mips16e_collect_propagate_value (rtx x, rtx *reg_values)
9134 x = avoid_constant_pool_reference (x);
9138 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
9139 return simplify_gen_unary (GET_CODE (x), GET_MODE (x),
9140 x0, GET_MODE (XEXP (x, 0)));
9143 if (ARITHMETIC_P (x))
9145 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
9146 rtx x1 = mips16e_collect_propagate_value (XEXP (x, 1), reg_values);
9147 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), x0, x1);
9151 && reg_values[REGNO (x)]
9152 && !rtx_unstable_p (reg_values[REGNO (x)]))
9153 return reg_values[REGNO (x)];
9158 /* Return true if (set DEST SRC) stores an argument register into its
9159 caller-allocated save slot, storing the number of that argument
9160 register in *REGNO_PTR if so. REG_VALUES is as for
9161 mips16e_collect_propagate_value. */
9164 mips16e_collect_argument_save_p (rtx dest, rtx src, rtx *reg_values,
9165 unsigned int *regno_ptr)
9167 unsigned int argno, regno;
9168 HOST_WIDE_INT offset, required_offset;
9171 /* Check that this is a word-mode store. */
9172 if (!MEM_P (dest) || !REG_P (src) || GET_MODE (dest) != word_mode)
9175 /* Check that the register being saved is an unmodified argument
9177 regno = REGNO (src);
9178 if (!IN_RANGE (regno, GP_ARG_FIRST, GP_ARG_LAST) || reg_values[regno])
9180 argno = regno - GP_ARG_FIRST;
9182 /* Check whether the address is an appropriate stack-pointer or
9183 frame-pointer access. */
9184 addr = mips16e_collect_propagate_value (XEXP (dest, 0), reg_values);
9185 mips_split_plus (addr, &base, &offset);
9186 required_offset = cfun->machine->frame.total_size + argno * UNITS_PER_WORD;
9187 if (base == hard_frame_pointer_rtx)
9188 required_offset -= cfun->machine->frame.hard_frame_pointer_offset;
9189 else if (base != stack_pointer_rtx)
9191 if (offset != required_offset)
9198 /* A subroutine of mips_expand_prologue, called only when generating
9199 MIPS16e SAVE instructions. Search the start of the function for any
9200 instructions that save argument registers into their caller-allocated
9201 save slots. Delete such instructions and return a value N such that
9202 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
9203 instructions redundant. */
9206 mips16e_collect_argument_saves (void)
9208 rtx reg_values[FIRST_PSEUDO_REGISTER];
9209 rtx insn, next, set, dest, src;
9210 unsigned int nargs, regno;
9212 push_topmost_sequence ();
9214 memset (reg_values, 0, sizeof (reg_values));
9215 for (insn = get_insns (); insn; insn = next)
9217 next = NEXT_INSN (insn);
9218 if (NOTE_P (insn) || DEBUG_INSN_P (insn))
9224 set = PATTERN (insn);
9225 if (GET_CODE (set) != SET)
9228 dest = SET_DEST (set);
9229 src = SET_SRC (set);
9230 if (mips16e_collect_argument_save_p (dest, src, reg_values, ®no))
9232 if (!BITSET_P (cfun->machine->frame.mask, regno))
9235 nargs = MAX (nargs, (regno - GP_ARG_FIRST) + 1);
9238 else if (REG_P (dest) && GET_MODE (dest) == word_mode)
9239 reg_values[REGNO (dest)]
9240 = mips16e_collect_propagate_value (src, reg_values);
9244 pop_topmost_sequence ();
9249 /* Return a move between register REGNO and memory location SP + OFFSET.
9250 REG_PARM_P is true if SP + OFFSET belongs to REG_PARM_STACK_SPACE.
9251 Make the move a load if RESTORE_P, otherwise make it a store. */
9254 mips16e_save_restore_reg (bool restore_p, bool reg_parm_p,
9255 HOST_WIDE_INT offset, unsigned int regno)
9259 mem = gen_frame_mem (SImode, plus_constant (Pmode, stack_pointer_rtx,
9261 reg = gen_rtx_REG (SImode, regno);
9264 mips_add_cfa_restore (reg);
9265 return gen_rtx_SET (VOIDmode, reg, mem);
9268 return gen_rtx_SET (VOIDmode, mem, reg);
9269 return mips_frame_set (mem, reg);
9272 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
9273 The instruction must:
9275 - Allocate or deallocate SIZE bytes in total; SIZE is known
9278 - Save or restore as many registers in *MASK_PTR as possible.
9279 The instruction saves the first registers at the top of the
9280 allocated area, with the other registers below it.
9282 - Save NARGS argument registers above the allocated area.
9284 (NARGS is always zero if RESTORE_P.)
9286 The SAVE and RESTORE instructions cannot save and restore all general
9287 registers, so there may be some registers left over for the caller to
9288 handle. Destructively modify *MASK_PTR so that it contains the registers
9289 that still need to be saved or restored. The caller can save these
9290 registers in the memory immediately below *OFFSET_PTR, which is a
9291 byte offset from the bottom of the allocated stack area. */
9294 mips16e_build_save_restore (bool restore_p, unsigned int *mask_ptr,
9295 HOST_WIDE_INT *offset_ptr, unsigned int nargs,
9299 HOST_WIDE_INT offset, top_offset;
9300 unsigned int i, regno;
9303 gcc_assert (cfun->machine->frame.num_fp == 0);
9305 /* Calculate the number of elements in the PARALLEL. We need one element
9306 for the stack adjustment, one for each argument register save, and one
9307 for each additional register move. */
9309 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
9310 if (BITSET_P (*mask_ptr, mips16e_save_restore_regs[i]))
9313 /* Create the final PARALLEL. */
9314 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (n));
9317 /* Add the stack pointer adjustment. */
9318 set = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
9319 plus_constant (Pmode, stack_pointer_rtx,
9320 restore_p ? size : -size));
9321 RTX_FRAME_RELATED_P (set) = 1;
9322 XVECEXP (pattern, 0, n++) = set;
9324 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
9325 top_offset = restore_p ? size : 0;
9327 /* Save the arguments. */
9328 for (i = 0; i < nargs; i++)
9330 offset = top_offset + i * UNITS_PER_WORD;
9331 set = mips16e_save_restore_reg (restore_p, true, offset,
9333 XVECEXP (pattern, 0, n++) = set;
9336 /* Then fill in the other register moves. */
9337 offset = top_offset;
9338 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
9340 regno = mips16e_save_restore_regs[i];
9341 if (BITSET_P (*mask_ptr, regno))
9343 offset -= UNITS_PER_WORD;
9344 set = mips16e_save_restore_reg (restore_p, false, offset, regno);
9345 XVECEXP (pattern, 0, n++) = set;
9346 *mask_ptr &= ~(1 << regno);
9350 /* Tell the caller what offset it should use for the remaining registers. */
9351 *offset_ptr = size + (offset - top_offset);
9353 gcc_assert (n == XVECLEN (pattern, 0));
9358 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
9359 pointer. Return true if PATTERN matches the kind of instruction
9360 generated by mips16e_build_save_restore. If INFO is nonnull,
9361 initialize it when returning true. */
9364 mips16e_save_restore_pattern_p (rtx pattern, HOST_WIDE_INT adjust,
9365 struct mips16e_save_restore_info *info)
9367 unsigned int i, nargs, mask, extra;
9368 HOST_WIDE_INT top_offset, save_offset, offset;
9369 rtx set, reg, mem, base;
9372 if (!GENERATE_MIPS16E_SAVE_RESTORE)
9375 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
9376 top_offset = adjust > 0 ? adjust : 0;
9378 /* Interpret all other members of the PARALLEL. */
9379 save_offset = top_offset - UNITS_PER_WORD;
9383 for (n = 1; n < XVECLEN (pattern, 0); n++)
9385 /* Check that we have a SET. */
9386 set = XVECEXP (pattern, 0, n);
9387 if (GET_CODE (set) != SET)
9390 /* Check that the SET is a load (if restoring) or a store
9392 mem = adjust > 0 ? SET_SRC (set) : SET_DEST (set);
9396 /* Check that the address is the sum of the stack pointer and a
9397 possibly-zero constant offset. */
9398 mips_split_plus (XEXP (mem, 0), &base, &offset);
9399 if (base != stack_pointer_rtx)
9402 /* Check that SET's other operand is a register. */
9403 reg = adjust > 0 ? SET_DEST (set) : SET_SRC (set);
9407 /* Check for argument saves. */
9408 if (offset == top_offset + nargs * UNITS_PER_WORD
9409 && REGNO (reg) == GP_ARG_FIRST + nargs)
9411 else if (offset == save_offset)
9413 while (mips16e_save_restore_regs[i++] != REGNO (reg))
9414 if (i == ARRAY_SIZE (mips16e_save_restore_regs))
9417 mask |= 1 << REGNO (reg);
9418 save_offset -= UNITS_PER_WORD;
9424 /* Check that the restrictions on register ranges are met. */
9426 mips16e_mask_registers (&mask, mips16e_s2_s8_regs,
9427 ARRAY_SIZE (mips16e_s2_s8_regs), &extra);
9428 mips16e_mask_registers (&mask, mips16e_a0_a3_regs,
9429 ARRAY_SIZE (mips16e_a0_a3_regs), &extra);
9433 /* Make sure that the topmost argument register is not saved twice.
9434 The checks above ensure that the same is then true for the other
9435 argument registers. */
9436 if (nargs > 0 && BITSET_P (mask, GP_ARG_FIRST + nargs - 1))
9439 /* Pass back information, if requested. */
9442 info->nargs = nargs;
9444 info->size = (adjust > 0 ? adjust : -adjust);
9450 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
9451 for the register range [MIN_REG, MAX_REG]. Return a pointer to
9452 the null terminator. */
9455 mips16e_add_register_range (char *s, unsigned int min_reg,
9456 unsigned int max_reg)
9458 if (min_reg != max_reg)
9459 s += sprintf (s, ",%s-%s", reg_names[min_reg], reg_names[max_reg]);
9461 s += sprintf (s, ",%s", reg_names[min_reg]);
9465 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
9466 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
9469 mips16e_output_save_restore (rtx pattern, HOST_WIDE_INT adjust)
9471 static char buffer[300];
9473 struct mips16e_save_restore_info info;
9474 unsigned int i, end;
9477 /* Parse the pattern. */
9478 if (!mips16e_save_restore_pattern_p (pattern, adjust, &info))
9481 /* Add the mnemonic. */
9482 s = strcpy (buffer, adjust > 0 ? "restore\t" : "save\t");
9485 /* Save the arguments. */
9487 s += sprintf (s, "%s-%s,", reg_names[GP_ARG_FIRST],
9488 reg_names[GP_ARG_FIRST + info.nargs - 1]);
9489 else if (info.nargs == 1)
9490 s += sprintf (s, "%s,", reg_names[GP_ARG_FIRST]);
9492 /* Emit the amount of stack space to allocate or deallocate. */
9493 s += sprintf (s, "%d", (int) info.size);
9495 /* Save or restore $16. */
9496 if (BITSET_P (info.mask, 16))
9497 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 16]);
9499 /* Save or restore $17. */
9500 if (BITSET_P (info.mask, 17))
9501 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 17]);
9503 /* Save or restore registers in the range $s2...$s8, which
9504 mips16e_s2_s8_regs lists in decreasing order. Note that this
9505 is a software register range; the hardware registers are not
9506 numbered consecutively. */
9507 end = ARRAY_SIZE (mips16e_s2_s8_regs);
9508 i = mips16e_find_first_register (info.mask, mips16e_s2_s8_regs, end);
9510 s = mips16e_add_register_range (s, mips16e_s2_s8_regs[end - 1],
9511 mips16e_s2_s8_regs[i]);
9513 /* Save or restore registers in the range $a0...$a3. */
9514 end = ARRAY_SIZE (mips16e_a0_a3_regs);
9515 i = mips16e_find_first_register (info.mask, mips16e_a0_a3_regs, end);
9517 s = mips16e_add_register_range (s, mips16e_a0_a3_regs[i],
9518 mips16e_a0_a3_regs[end - 1]);
9520 /* Save or restore $31. */
9521 if (BITSET_P (info.mask, RETURN_ADDR_REGNUM))
9522 s += sprintf (s, ",%s", reg_names[RETURN_ADDR_REGNUM]);
9527 /* Return true if the current function returns its value in a floating-point
9528 register in MIPS16 mode. */
9531 mips16_cfun_returns_in_fpr_p (void)
9533 tree return_type = DECL_RESULT (current_function_decl);
9534 return (TARGET_MIPS16
9535 && TARGET_HARD_FLOAT_ABI
9536 && !aggregate_value_p (return_type, current_function_decl)
9537 && mips_return_mode_in_fpr_p (DECL_MODE (return_type)));
9540 /* Return true if predicate PRED is true for at least one instruction.
9541 Cache the result in *CACHE, and assume that the result is true
9542 if *CACHE is already true. */
9545 mips_find_gp_ref (bool *cache, bool (*pred) (rtx))
9551 push_topmost_sequence ();
9552 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9553 if (USEFUL_INSN_P (insn) && pred (insn))
9558 pop_topmost_sequence ();
9563 /* Return true if INSN refers to the global pointer in an "inflexible" way.
9564 See mips_cfun_has_inflexible_gp_ref_p for details. */
9567 mips_insn_has_inflexible_gp_ref_p (rtx insn)
9569 /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE
9570 indicate that the target could be a traditional MIPS
9571 lazily-binding stub. */
9572 return find_reg_fusage (insn, USE, pic_offset_table_rtx);
9575 /* Return true if the current function refers to the global pointer
9576 in a way that forces $28 to be valid. This means that we can't
9577 change the choice of global pointer, even for NewABI code.
9579 One example of this (and one which needs several checks) is that
9580 $28 must be valid when calling traditional MIPS lazy-binding stubs.
9581 (This restriction does not apply to PLTs.) */
9584 mips_cfun_has_inflexible_gp_ref_p (void)
9586 /* If the function has a nonlocal goto, $28 must hold the correct
9587 global pointer for the target function. That is, the target
9588 of the goto implicitly uses $28. */
9589 if (crtl->has_nonlocal_goto)
9592 if (TARGET_ABICALLS_PIC2)
9594 /* Symbolic accesses implicitly use the global pointer unless
9595 -mexplicit-relocs is in effect. JAL macros to symbolic addresses
9596 might go to traditional MIPS lazy-binding stubs. */
9597 if (!TARGET_EXPLICIT_RELOCS)
9600 /* FUNCTION_PROFILER includes a JAL to _mcount, which again
9601 can be lazily-bound. */
9605 /* MIPS16 functions that return in FPRs need to call an
9606 external libgcc routine. This call is only made explict
9607 during mips_expand_epilogue, and it too might be lazily bound. */
9608 if (mips16_cfun_returns_in_fpr_p ())
9612 return mips_find_gp_ref (&cfun->machine->has_inflexible_gp_insn_p,
9613 mips_insn_has_inflexible_gp_ref_p);
9616 /* Return true if INSN refers to the global pointer in a "flexible" way.
9617 See mips_cfun_has_flexible_gp_ref_p for details. */
9620 mips_insn_has_flexible_gp_ref_p (rtx insn)
9622 return (get_attr_got (insn) != GOT_UNSET
9623 || mips_small_data_pattern_p (PATTERN (insn))
9624 || reg_overlap_mentioned_p (pic_offset_table_rtx, PATTERN (insn)));
9627 /* Return true if the current function references the global pointer,
9628 but if those references do not inherently require the global pointer
9629 to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */
9632 mips_cfun_has_flexible_gp_ref_p (void)
9634 /* Reload can sometimes introduce constant pool references
9635 into a function that otherwise didn't need them. For example,
9636 suppose we have an instruction like:
9638 (set (reg:DF R1) (float:DF (reg:SI R2)))
9640 If R2 turns out to be a constant such as 1, the instruction may
9641 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
9642 the option of using this constant if R2 doesn't get allocated
9645 In cases like these, reload will have added the constant to the
9646 pool but no instruction will yet refer to it. */
9647 if (TARGET_ABICALLS_PIC2 && !reload_completed && crtl->uses_const_pool)
9650 return mips_find_gp_ref (&cfun->machine->has_flexible_gp_insn_p,
9651 mips_insn_has_flexible_gp_ref_p);
9654 /* Return the register that should be used as the global pointer
9655 within this function. Return INVALID_REGNUM if the function
9656 doesn't need a global pointer. */
9659 mips_global_pointer (void)
9663 /* $gp is always available unless we're using a GOT. */
9664 if (!TARGET_USE_GOT)
9665 return GLOBAL_POINTER_REGNUM;
9667 /* If there are inflexible references to $gp, we must use the
9668 standard register. */
9669 if (mips_cfun_has_inflexible_gp_ref_p ())
9670 return GLOBAL_POINTER_REGNUM;
9672 /* If there are no current references to $gp, then the only uses
9673 we can introduce later are those involved in long branches. */
9674 if (TARGET_ABSOLUTE_JUMPS && !mips_cfun_has_flexible_gp_ref_p ())
9675 return INVALID_REGNUM;
9677 /* If the global pointer is call-saved, try to use a call-clobbered
9679 if (TARGET_CALL_SAVED_GP && crtl->is_leaf)
9680 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
9681 if (!df_regs_ever_live_p (regno)
9682 && call_really_used_regs[regno]
9683 && !fixed_regs[regno]
9684 && regno != PIC_FUNCTION_ADDR_REGNUM)
9687 return GLOBAL_POINTER_REGNUM;
9690 /* Return true if the current function's prologue must load the global
9691 pointer value into pic_offset_table_rtx and store the same value in
9692 the function's cprestore slot (if any).
9694 One problem we have to deal with is that, when emitting GOT-based
9695 position independent code, long-branch sequences will need to load
9696 the address of the branch target from the GOT. We don't know until
9697 the very end of compilation whether (and where) the function needs
9698 long branches, so we must ensure that _any_ branch can access the
9699 global pointer in some form. However, we do not want to pessimize
9700 the usual case in which all branches are short.
9702 We handle this as follows:
9704 (1) During reload, we set cfun->machine->global_pointer to
9705 INVALID_REGNUM if we _know_ that the current function
9706 doesn't need a global pointer. This is only valid if
9707 long branches don't need the GOT.
9709 Otherwise, we assume that we might need a global pointer
9710 and pick an appropriate register.
9712 (2) If cfun->machine->global_pointer != INVALID_REGNUM,
9713 we ensure that the global pointer is available at every
9714 block boundary bar entry and exit. We do this in one of two ways:
9716 - If the function has a cprestore slot, we ensure that this
9717 slot is valid at every branch. However, as explained in
9718 point (6) below, there is no guarantee that pic_offset_table_rtx
9719 itself is valid if new uses of the global pointer are introduced
9720 after the first post-epilogue split.
9722 We guarantee that the cprestore slot is valid by loading it
9723 into a fake register, CPRESTORE_SLOT_REGNUM. We then make
9724 this register live at every block boundary bar function entry
9725 and exit. It is then invalid to move the load (and thus the
9726 preceding store) across a block boundary.
9728 - If the function has no cprestore slot, we guarantee that
9729 pic_offset_table_rtx itself is valid at every branch.
9731 See mips_eh_uses for the handling of the register liveness.
9733 (3) During prologue and epilogue generation, we emit "ghost"
9734 placeholder instructions to manipulate the global pointer.
9736 (4) During prologue generation, we set cfun->machine->must_initialize_gp_p
9737 and cfun->machine->must_restore_gp_when_clobbered_p if we already know
9738 that the function needs a global pointer. (There is no need to set
9739 them earlier than this, and doing it as late as possible leads to
9740 fewer false positives.)
9742 (5) If cfun->machine->must_initialize_gp_p is true during a
9743 split_insns pass, we split the ghost instructions into real
9744 instructions. These split instructions can then be optimized in
9745 the usual way. Otherwise, we keep the ghost instructions intact,
9746 and optimize for the case where they aren't needed. We still
9747 have the option of splitting them later, if we need to introduce
9748 new uses of the global pointer.
9750 For example, the scheduler ignores a ghost instruction that
9751 stores $28 to the stack, but it handles the split form of
9752 the ghost instruction as an ordinary store.
9754 (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p
9755 is true during the first post-epilogue split_insns pass, we split
9756 calls and restore_gp patterns into instructions that explicitly
9757 load pic_offset_table_rtx from the cprestore slot. Otherwise,
9758 we split these patterns into instructions that _don't_ load from
9761 If cfun->machine->must_restore_gp_when_clobbered_p is true at the
9762 time of the split, then any instructions that exist at that time
9763 can make free use of pic_offset_table_rtx. However, if we want
9764 to introduce new uses of the global pointer after the split,
9765 we must explicitly load the value from the cprestore slot, since
9766 pic_offset_table_rtx itself might not be valid at a given point
9769 The idea is that we want to be able to delete redundant
9770 loads from the cprestore slot in the usual case where no
9771 long branches are needed.
9773 (7) If cfun->machine->must_initialize_gp_p is still false at the end
9774 of md_reorg, we decide whether the global pointer is needed for
9775 long branches. If so, we set cfun->machine->must_initialize_gp_p
9776 to true and split the ghost instructions into real instructions
9779 Note that the ghost instructions must have a zero length for three reasons:
9781 - Giving the length of the underlying $gp sequence might cause
9782 us to use long branches in cases where they aren't really needed.
9784 - They would perturb things like alignment calculations.
9786 - More importantly, the hazard detection in md_reorg relies on
9787 empty instructions having a zero length.
9789 If we find a long branch and split the ghost instructions at the
9790 end of md_reorg, the split could introduce more long branches.
9791 That isn't a problem though, because we still do the split before
9792 the final shorten_branches pass.
9794 This is extremely ugly, but it seems like the best compromise between
9795 correctness and efficiency. */
9798 mips_must_initialize_gp_p (void)
9800 return cfun->machine->must_initialize_gp_p;
9803 /* Return true if REGNO is a register that is ordinarily call-clobbered
9804 but must nevertheless be preserved by an interrupt handler. */
9807 mips_interrupt_extra_call_saved_reg_p (unsigned int regno)
9809 if (MD_REG_P (regno))
9812 if (TARGET_DSP && DSP_ACC_REG_P (regno))
9815 if (GP_REG_P (regno) && !cfun->machine->use_shadow_register_set_p)
9817 /* $0 is hard-wired. */
9818 if (regno == GP_REG_FIRST)
9821 /* The interrupt handler can treat kernel registers as
9822 scratch registers. */
9823 if (KERNEL_REG_P (regno))
9826 /* The function will return the stack pointer to its original value
9828 if (regno == STACK_POINTER_REGNUM)
9831 /* Otherwise, return true for registers that aren't ordinarily
9833 return call_really_used_regs[regno];
9839 /* Return true if the current function should treat register REGNO
9843 mips_cfun_call_saved_reg_p (unsigned int regno)
9845 /* If the user makes an ordinarily-call-saved register global,
9846 that register is no longer call-saved. */
9847 if (global_regs[regno])
9850 /* Interrupt handlers need to save extra registers. */
9851 if (cfun->machine->interrupt_handler_p
9852 && mips_interrupt_extra_call_saved_reg_p (regno))
9855 /* call_insns preserve $28 unless they explicitly say otherwise,
9856 so call_really_used_regs[] treats $28 as call-saved. However,
9857 we want the ABI property rather than the default call_insn
9859 return (regno == GLOBAL_POINTER_REGNUM
9860 ? TARGET_CALL_SAVED_GP
9861 : !call_really_used_regs[regno]);
9864 /* Return true if the function body might clobber register REGNO.
9865 We know that REGNO is call-saved. */
9868 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno)
9870 /* Some functions should be treated as clobbering all call-saved
9872 if (crtl->saves_all_registers)
9875 /* DF handles cases where a register is explicitly referenced in
9876 the rtl. Incoming values are passed in call-clobbered registers,
9877 so we can assume that any live call-saved register is set within
9879 if (df_regs_ever_live_p (regno))
9882 /* Check for registers that are clobbered by FUNCTION_PROFILER.
9883 These clobbers are not explicit in the rtl. */
9884 if (crtl->profile && MIPS_SAVE_REG_FOR_PROFILING_P (regno))
9887 /* If we're using a call-saved global pointer, the function's
9888 prologue will need to set it up. */
9889 if (cfun->machine->global_pointer == regno)
9892 /* The function's prologue will need to set the frame pointer if
9893 frame_pointer_needed. */
9894 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
9897 /* If a MIPS16 function returns a value in FPRs, its epilogue
9898 will need to call an external libgcc routine. This yet-to-be
9899 generated call_insn will clobber $31. */
9900 if (regno == RETURN_ADDR_REGNUM && mips16_cfun_returns_in_fpr_p ())
9903 /* If REGNO is ordinarily call-clobbered, we must assume that any
9904 called function could modify it. */
9905 if (cfun->machine->interrupt_handler_p
9907 && mips_interrupt_extra_call_saved_reg_p (regno))
9913 /* Return true if the current function must save register REGNO. */
9916 mips_save_reg_p (unsigned int regno)
9918 if (mips_cfun_call_saved_reg_p (regno))
9920 if (mips_cfun_might_clobber_call_saved_reg_p (regno))
9923 /* Save both registers in an FPR pair if either one is used. This is
9924 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
9925 register to be used without the even register. */
9926 if (FP_REG_P (regno)
9927 && MAX_FPRS_PER_FMT == 2
9928 && mips_cfun_might_clobber_call_saved_reg_p (regno + 1))
9932 /* We need to save the incoming return address if __builtin_eh_return
9933 is being used to set a different return address. */
9934 if (regno == RETURN_ADDR_REGNUM && crtl->calls_eh_return)
9940 /* Populate the current function's mips_frame_info structure.
9942 MIPS stack frames look like:
9944 +-------------------------------+
9946 | incoming stack arguments |
9948 +-------------------------------+
9950 | caller-allocated save area |
9951 A | for register arguments |
9953 +-------------------------------+ <-- incoming stack pointer
9955 | callee-allocated save area |
9956 B | for arguments that are |
9957 | split between registers and |
9960 +-------------------------------+ <-- arg_pointer_rtx
9962 C | callee-allocated save area |
9963 | for register varargs |
9965 +-------------------------------+ <-- frame_pointer_rtx
9966 | | + cop0_sp_offset
9967 | COP0 reg save area | + UNITS_PER_WORD
9969 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
9970 | | + UNITS_PER_WORD
9971 | accumulator save area |
9973 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
9974 | | + UNITS_PER_HWFPVALUE
9977 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset
9978 | | + UNITS_PER_WORD
9981 +-------------------------------+ <-- frame_pointer_rtx with
9982 | | \ -fstack-protector
9983 | local variables | | var_size
9985 +-------------------------------+
9987 | $gp save area | | cprestore_size
9989 P +-------------------------------+ <-- hard_frame_pointer_rtx for
9991 | outgoing stack arguments | |
9993 +-------------------------------+ | args_size
9995 | caller-allocated save area | |
9996 | for register arguments | |
9998 +-------------------------------+ <-- stack_pointer_rtx
9999 frame_pointer_rtx without
10001 hard_frame_pointer_rtx for
10004 At least two of A, B and C will be empty.
10006 Dynamic stack allocations such as alloca insert data at point P.
10007 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
10008 hard_frame_pointer_rtx unchanged. */
10011 mips_compute_frame_info (void)
10013 struct mips_frame_info *frame;
10014 HOST_WIDE_INT offset, size;
10015 unsigned int regno, i;
10017 /* Set this function's interrupt properties. */
10018 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
10021 error ("the %<interrupt%> attribute requires a MIPS32r2 processor");
10022 else if (TARGET_HARD_FLOAT)
10023 error ("the %<interrupt%> attribute requires %<-msoft-float%>");
10024 else if (TARGET_MIPS16)
10025 error ("interrupt handlers cannot be MIPS16 functions");
10028 cfun->machine->interrupt_handler_p = true;
10029 cfun->machine->use_shadow_register_set_p =
10030 mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl));
10031 cfun->machine->keep_interrupts_masked_p =
10032 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl));
10033 cfun->machine->use_debug_exception_return_p =
10034 mips_use_debug_exception_return_p (TREE_TYPE
10035 (current_function_decl));
10039 frame = &cfun->machine->frame;
10040 memset (frame, 0, sizeof (*frame));
10041 size = get_frame_size ();
10043 cfun->machine->global_pointer = mips_global_pointer ();
10045 /* The first two blocks contain the outgoing argument area and the $gp save
10046 slot. This area isn't needed in leaf functions, but if the
10047 target-independent frame size is nonzero, we have already committed to
10048 allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */
10049 if ((size == 0 || FRAME_GROWS_DOWNWARD) && crtl->is_leaf)
10051 /* The MIPS 3.0 linker does not like functions that dynamically
10052 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
10053 looks like we are trying to create a second frame pointer to the
10054 function, so allocate some stack space to make it happy. */
10055 if (cfun->calls_alloca)
10056 frame->args_size = REG_PARM_STACK_SPACE (cfun->decl);
10058 frame->args_size = 0;
10059 frame->cprestore_size = 0;
10063 frame->args_size = crtl->outgoing_args_size;
10064 frame->cprestore_size = MIPS_GP_SAVE_AREA_SIZE;
10066 offset = frame->args_size + frame->cprestore_size;
10068 /* Move above the local variables. */
10069 frame->var_size = MIPS_STACK_ALIGN (size);
10070 offset += frame->var_size;
10072 /* Find out which GPRs we need to save. */
10073 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
10074 if (mips_save_reg_p (regno))
10077 frame->mask |= 1 << (regno - GP_REG_FIRST);
10080 /* If this function calls eh_return, we must also save and restore the
10081 EH data registers. */
10082 if (crtl->calls_eh_return)
10083 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; i++)
10086 frame->mask |= 1 << (EH_RETURN_DATA_REGNO (i) - GP_REG_FIRST);
10089 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
10090 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
10091 save all later registers too. */
10092 if (GENERATE_MIPS16E_SAVE_RESTORE)
10094 mips16e_mask_registers (&frame->mask, mips16e_s2_s8_regs,
10095 ARRAY_SIZE (mips16e_s2_s8_regs), &frame->num_gp);
10096 mips16e_mask_registers (&frame->mask, mips16e_a0_a3_regs,
10097 ARRAY_SIZE (mips16e_a0_a3_regs), &frame->num_gp);
10100 /* Move above the GPR save area. */
10101 if (frame->num_gp > 0)
10103 offset += MIPS_STACK_ALIGN (frame->num_gp * UNITS_PER_WORD);
10104 frame->gp_sp_offset = offset - UNITS_PER_WORD;
10107 /* Find out which FPRs we need to save. This loop must iterate over
10108 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
10109 if (TARGET_HARD_FLOAT)
10110 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += MAX_FPRS_PER_FMT)
10111 if (mips_save_reg_p (regno))
10113 frame->num_fp += MAX_FPRS_PER_FMT;
10114 frame->fmask |= ~(~0 << MAX_FPRS_PER_FMT) << (regno - FP_REG_FIRST);
10117 /* Move above the FPR save area. */
10118 if (frame->num_fp > 0)
10120 offset += MIPS_STACK_ALIGN (frame->num_fp * UNITS_PER_FPREG);
10121 frame->fp_sp_offset = offset - UNITS_PER_HWFPVALUE;
10124 /* Add in space for the interrupt context information. */
10125 if (cfun->machine->interrupt_handler_p)
10128 if (mips_save_reg_p (LO_REGNUM) || mips_save_reg_p (HI_REGNUM))
10131 frame->acc_mask |= (1 << 0);
10134 /* Check accumulators 1, 2, 3. */
10135 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
10136 if (mips_save_reg_p (i) || mips_save_reg_p (i + 1))
10139 frame->acc_mask |= 1 << (((i - DSP_ACC_REG_FIRST) / 2) + 1);
10142 /* All interrupt context functions need space to preserve STATUS. */
10143 frame->num_cop0_regs++;
10145 /* If we don't keep interrupts masked, we need to save EPC. */
10146 if (!cfun->machine->keep_interrupts_masked_p)
10147 frame->num_cop0_regs++;
10150 /* Move above the accumulator save area. */
10151 if (frame->num_acc > 0)
10153 /* Each accumulator needs 2 words. */
10154 offset += frame->num_acc * 2 * UNITS_PER_WORD;
10155 frame->acc_sp_offset = offset - UNITS_PER_WORD;
10158 /* Move above the COP0 register save area. */
10159 if (frame->num_cop0_regs > 0)
10161 offset += frame->num_cop0_regs * UNITS_PER_WORD;
10162 frame->cop0_sp_offset = offset - UNITS_PER_WORD;
10165 /* Move above the callee-allocated varargs save area. */
10166 offset += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
10167 frame->arg_pointer_offset = offset;
10169 /* Move above the callee-allocated area for pretend stack arguments. */
10170 offset += crtl->args.pretend_args_size;
10171 frame->total_size = offset;
10173 /* Work out the offsets of the save areas from the top of the frame. */
10174 if (frame->gp_sp_offset > 0)
10175 frame->gp_save_offset = frame->gp_sp_offset - offset;
10176 if (frame->fp_sp_offset > 0)
10177 frame->fp_save_offset = frame->fp_sp_offset - offset;
10178 if (frame->acc_sp_offset > 0)
10179 frame->acc_save_offset = frame->acc_sp_offset - offset;
10180 if (frame->num_cop0_regs > 0)
10181 frame->cop0_save_offset = frame->cop0_sp_offset - offset;
10183 /* MIPS16 code offsets the frame pointer by the size of the outgoing
10184 arguments. This tends to increase the chances of using unextended
10185 instructions for local variables and incoming arguments. */
10187 frame->hard_frame_pointer_offset = frame->args_size;
10190 /* Return the style of GP load sequence that is being used for the
10191 current function. */
10193 enum mips_loadgp_style
10194 mips_current_loadgp_style (void)
10196 if (!TARGET_USE_GOT || cfun->machine->global_pointer == INVALID_REGNUM)
10197 return LOADGP_NONE;
10199 if (TARGET_RTP_PIC)
10202 if (TARGET_ABSOLUTE_ABICALLS)
10203 return LOADGP_ABSOLUTE;
10205 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
10208 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
10211 mips_frame_pointer_required (void)
10213 /* If the function contains dynamic stack allocations, we need to
10214 use the frame pointer to access the static parts of the frame. */
10215 if (cfun->calls_alloca)
10218 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
10219 reload may be unable to compute the address of a local variable,
10220 since there is no way to add a large constant to the stack pointer
10221 without using a second temporary register. */
10224 mips_compute_frame_info ();
10225 if (!SMALL_OPERAND (cfun->machine->frame.total_size))
10232 /* Make sure that we're not trying to eliminate to the wrong hard frame
10236 mips_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
10238 return (to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM);
10241 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
10242 or argument pointer. TO is either the stack pointer or hard frame
10246 mips_initial_elimination_offset (int from, int to)
10248 HOST_WIDE_INT offset;
10250 mips_compute_frame_info ();
10252 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */
10255 case FRAME_POINTER_REGNUM:
10256 if (FRAME_GROWS_DOWNWARD)
10257 offset = (cfun->machine->frame.args_size
10258 + cfun->machine->frame.cprestore_size
10259 + cfun->machine->frame.var_size);
10264 case ARG_POINTER_REGNUM:
10265 offset = cfun->machine->frame.arg_pointer_offset;
10269 gcc_unreachable ();
10272 if (to == HARD_FRAME_POINTER_REGNUM)
10273 offset -= cfun->machine->frame.hard_frame_pointer_offset;
10278 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
10281 mips_extra_live_on_entry (bitmap regs)
10283 if (TARGET_USE_GOT)
10285 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
10286 the global pointer. */
10287 if (!TARGET_ABSOLUTE_ABICALLS)
10288 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
10290 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
10291 the global pointer. */
10293 bitmap_set_bit (regs, MIPS16_PIC_TEMP_REGNUM);
10295 /* See the comment above load_call<mode> for details. */
10296 bitmap_set_bit (regs, GOT_VERSION_REGNUM);
10300 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
10304 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
10309 return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);
10312 /* Emit code to change the current function's return address to
10313 ADDRESS. SCRATCH is available as a scratch register, if needed.
10314 ADDRESS and SCRATCH are both word-mode GPRs. */
10317 mips_set_return_address (rtx address, rtx scratch)
10321 gcc_assert (BITSET_P (cfun->machine->frame.mask, RETURN_ADDR_REGNUM));
10322 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
10323 cfun->machine->frame.gp_sp_offset);
10324 mips_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address);
10327 /* Return true if the current function has a cprestore slot. */
10330 mips_cfun_has_cprestore_slot_p (void)
10332 return (cfun->machine->global_pointer != INVALID_REGNUM
10333 && cfun->machine->frame.cprestore_size > 0);
10336 /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the
10337 cprestore slot. LOAD_P is true if the caller wants to load from
10338 the cprestore slot; it is false if the caller wants to store to
10342 mips_get_cprestore_base_and_offset (rtx *base, HOST_WIDE_INT *offset,
10345 const struct mips_frame_info *frame;
10347 frame = &cfun->machine->frame;
10348 /* .cprestore always uses the stack pointer instead of the frame pointer.
10349 We have a free choice for direct stores for non-MIPS16 functions,
10350 and for MIPS16 functions whose cprestore slot is in range of the
10351 stack pointer. Using the stack pointer would sometimes give more
10352 (early) scheduling freedom, but using the frame pointer would
10353 sometimes give more (late) scheduling freedom. It's hard to
10354 predict which applies to a given function, so let's keep things
10357 Loads must always use the frame pointer in functions that call
10358 alloca, and there's little benefit to using the stack pointer
10360 if (frame_pointer_needed && !(TARGET_CPRESTORE_DIRECTIVE && !load_p))
10362 *base = hard_frame_pointer_rtx;
10363 *offset = frame->args_size - frame->hard_frame_pointer_offset;
10367 *base = stack_pointer_rtx;
10368 *offset = frame->args_size;
10372 /* Return true if X is the load or store address of the cprestore slot;
10373 LOAD_P says which. */
10376 mips_cprestore_address_p (rtx x, bool load_p)
10378 rtx given_base, required_base;
10379 HOST_WIDE_INT given_offset, required_offset;
10381 mips_split_plus (x, &given_base, &given_offset);
10382 mips_get_cprestore_base_and_offset (&required_base, &required_offset, load_p);
10383 return given_base == required_base && given_offset == required_offset;
10386 /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are
10387 going to load from it, false if we are going to store to it.
10388 Use TEMP as a temporary register if need be. */
10391 mips_cprestore_slot (rtx temp, bool load_p)
10394 HOST_WIDE_INT offset;
10396 mips_get_cprestore_base_and_offset (&base, &offset, load_p);
10397 return gen_frame_mem (Pmode, mips_add_offset (temp, base, offset));
10400 /* Emit instructions to save global pointer value GP into cprestore
10401 slot MEM. OFFSET is the offset that MEM applies to the base register.
10403 MEM may not be a legitimate address. If it isn't, TEMP is a
10404 temporary register that can be used, otherwise it is a SCRATCH. */
10407 mips_save_gp_to_cprestore_slot (rtx mem, rtx offset, rtx gp, rtx temp)
10409 if (TARGET_CPRESTORE_DIRECTIVE)
10411 gcc_assert (gp == pic_offset_table_rtx);
10412 emit_insn (PMODE_INSN (gen_cprestore, (mem, offset)));
10415 mips_emit_move (mips_cprestore_slot (temp, false), gp);
10418 /* Restore $gp from its save slot, using TEMP as a temporary base register
10419 if need be. This function is for o32 and o64 abicalls only.
10421 See mips_must_initialize_gp_p for details about how we manage the
10425 mips_restore_gp_from_cprestore_slot (rtx temp)
10427 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI && epilogue_completed);
10429 if (!cfun->machine->must_restore_gp_when_clobbered_p)
10431 emit_note (NOTE_INSN_DELETED);
10437 mips_emit_move (temp, mips_cprestore_slot (temp, true));
10438 mips_emit_move (pic_offset_table_rtx, temp);
10441 mips_emit_move (pic_offset_table_rtx, mips_cprestore_slot (temp, true));
10442 if (!TARGET_EXPLICIT_RELOCS)
10443 emit_insn (gen_blockage ());
10446 /* A function to save or store a register. The first argument is the
10447 register and the second is the stack slot. */
10448 typedef void (*mips_save_restore_fn) (rtx, rtx);
10450 /* Use FN to save or restore register REGNO. MODE is the register's
10451 mode and OFFSET is the offset of its save slot from the current
10455 mips_save_restore_reg (enum machine_mode mode, int regno,
10456 HOST_WIDE_INT offset, mips_save_restore_fn fn)
10460 mem = gen_frame_mem (mode, plus_constant (Pmode, stack_pointer_rtx,
10462 fn (gen_rtx_REG (mode, regno), mem);
10465 /* Call FN for each accumlator that is saved by the current function.
10466 SP_OFFSET is the offset of the current stack pointer from the start
10470 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
10472 HOST_WIDE_INT offset;
10475 offset = cfun->machine->frame.acc_sp_offset - sp_offset;
10476 if (BITSET_P (cfun->machine->frame.acc_mask, 0))
10478 mips_save_restore_reg (word_mode, LO_REGNUM, offset, fn);
10479 offset -= UNITS_PER_WORD;
10480 mips_save_restore_reg (word_mode, HI_REGNUM, offset, fn);
10481 offset -= UNITS_PER_WORD;
10484 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
10485 if (BITSET_P (cfun->machine->frame.acc_mask,
10486 ((regno - DSP_ACC_REG_FIRST) / 2) + 1))
10488 mips_save_restore_reg (word_mode, regno, offset, fn);
10489 offset -= UNITS_PER_WORD;
10493 /* Save register REG to MEM. Make the instruction frame-related. */
10496 mips_save_reg (rtx reg, rtx mem)
10498 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
10502 mips_emit_move_or_split (mem, reg, SPLIT_IF_NECESSARY);
10504 x1 = mips_frame_set (mips_subword (mem, false),
10505 mips_subword (reg, false));
10506 x2 = mips_frame_set (mips_subword (mem, true),
10507 mips_subword (reg, true));
10508 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
10511 mips_emit_save_slot_move (mem, reg, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
10514 /* Capture the register combinations that are allowed in a SWM or LWM
10515 instruction. The entries are ordered by number of registers set in
10516 the mask. We also ignore the single register encodings because a
10517 normal SW/LW is preferred. */
10519 static const unsigned int umips_swm_mask[17] = {
10520 0xc0ff0000, 0x80ff0000, 0x40ff0000, 0x807f0000,
10521 0x00ff0000, 0x803f0000, 0x007f0000, 0x801f0000,
10522 0x003f0000, 0x800f0000, 0x001f0000, 0x80070000,
10523 0x000f0000, 0x80030000, 0x00070000, 0x80010000,
10527 static const unsigned int umips_swm_encoding[17] = {
10528 25, 24, 9, 23, 8, 22, 7, 21, 6, 20, 5, 19, 4, 18, 3, 17, 2
10531 /* Try to use a microMIPS LWM or SWM instruction to save or restore
10532 as many GPRs in *MASK as possible. *OFFSET is the offset from the
10533 stack pointer of the topmost save slot.
10535 Remove from *MASK all registers that were handled using LWM and SWM.
10536 Update *OFFSET so that it points to the first unused save slot. */
10539 umips_build_save_restore (mips_save_restore_fn fn,
10540 unsigned *mask, HOST_WIDE_INT *offset)
10544 rtx pattern, set, reg, mem;
10545 HOST_WIDE_INT this_offset;
10548 /* Try matching $16 to $31 (s0 to ra). */
10549 for (i = 0; i < ARRAY_SIZE (umips_swm_mask); i++)
10550 if ((*mask & 0xffff0000) == umips_swm_mask[i])
10553 if (i == ARRAY_SIZE (umips_swm_mask))
10556 /* Get the offset of the lowest save slot. */
10557 nregs = (umips_swm_encoding[i] & 0xf) + (umips_swm_encoding[i] >> 4);
10558 this_offset = *offset - UNITS_PER_WORD * (nregs - 1);
10560 /* LWM/SWM can only support offsets from -2048 to 2047. */
10561 if (!UMIPS_12BIT_OFFSET_P (this_offset))
10564 /* Create the final PARALLEL. */
10565 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nregs));
10566 this_base = stack_pointer_rtx;
10568 /* For registers $16-$23 and $30. */
10569 for (j = 0; j < (umips_swm_encoding[i] & 0xf); j++)
10571 HOST_WIDE_INT offset = this_offset + j * UNITS_PER_WORD;
10572 mem = gen_frame_mem (SImode, plus_constant (Pmode, this_base, offset));
10573 unsigned int regno = (j != 8) ? 16 + j : 30;
10574 *mask &= ~(1 << regno);
10575 reg = gen_rtx_REG (SImode, regno);
10576 if (fn == mips_save_reg)
10577 set = mips_frame_set (mem, reg);
10580 set = gen_rtx_SET (VOIDmode, reg, mem);
10581 mips_add_cfa_restore (reg);
10583 XVECEXP (pattern, 0, j) = set;
10586 /* For register $31. */
10587 if (umips_swm_encoding[i] >> 4)
10589 HOST_WIDE_INT offset = this_offset + j * UNITS_PER_WORD;
10590 *mask &= ~(1 << 31);
10591 mem = gen_frame_mem (SImode, plus_constant (Pmode, this_base, offset));
10592 reg = gen_rtx_REG (SImode, 31);
10593 if (fn == mips_save_reg)
10594 set = mips_frame_set (mem, reg);
10597 set = gen_rtx_SET (VOIDmode, reg, mem);
10598 mips_add_cfa_restore (reg);
10600 XVECEXP (pattern, 0, j) = set;
10603 pattern = emit_insn (pattern);
10604 if (fn == mips_save_reg)
10605 RTX_FRAME_RELATED_P (pattern) = 1;
10607 /* Adjust the last offset. */
10608 *offset -= UNITS_PER_WORD * nregs;
10613 /* Call FN for each register that is saved by the current function.
10614 SP_OFFSET is the offset of the current stack pointer from the start
10618 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset,
10619 mips_save_restore_fn fn)
10621 enum machine_mode fpr_mode;
10623 const struct mips_frame_info *frame = &cfun->machine->frame;
10624 HOST_WIDE_INT offset;
10627 /* Save registers starting from high to low. The debuggers prefer at least
10628 the return register be stored at func+4, and also it allows us not to
10629 need a nop in the epilogue if at least one register is reloaded in
10630 addition to return address. */
10631 offset = frame->gp_sp_offset - sp_offset;
10632 mask = frame->mask;
10634 if (TARGET_MICROMIPS)
10635 umips_build_save_restore (fn, &mask, &offset);
10637 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
10638 if (BITSET_P (mask, regno - GP_REG_FIRST))
10640 /* Record the ra offset for use by mips_function_profiler. */
10641 if (regno == RETURN_ADDR_REGNUM)
10642 cfun->machine->frame.ra_fp_offset = offset + sp_offset;
10643 mips_save_restore_reg (word_mode, regno, offset, fn);
10644 offset -= UNITS_PER_WORD;
10647 /* This loop must iterate over the same space as its companion in
10648 mips_compute_frame_info. */
10649 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
10650 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
10651 for (regno = FP_REG_LAST - MAX_FPRS_PER_FMT + 1;
10652 regno >= FP_REG_FIRST;
10653 regno -= MAX_FPRS_PER_FMT)
10654 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
10656 mips_save_restore_reg (fpr_mode, regno, offset, fn);
10657 offset -= GET_MODE_SIZE (fpr_mode);
10661 /* Return true if a move between register REGNO and its save slot (MEM)
10662 can be done in a single move. LOAD_P is true if we are loading
10663 from the slot, false if we are storing to it. */
10666 mips_direct_save_slot_move_p (unsigned int regno, rtx mem, bool load_p)
10668 /* There is a specific MIPS16 instruction for saving $31 to the stack. */
10669 if (TARGET_MIPS16 && !load_p && regno == RETURN_ADDR_REGNUM)
10672 return mips_secondary_reload_class (REGNO_REG_CLASS (regno),
10673 GET_MODE (mem), mem, load_p) == NO_REGS;
10676 /* Emit a move from SRC to DEST, given that one of them is a register
10677 save slot and that the other is a register. TEMP is a temporary
10678 GPR of the same mode that is available if need be. */
10681 mips_emit_save_slot_move (rtx dest, rtx src, rtx temp)
10683 unsigned int regno;
10688 regno = REGNO (src);
10693 regno = REGNO (dest);
10697 if (regno == cfun->machine->global_pointer && !mips_must_initialize_gp_p ())
10699 /* We don't yet know whether we'll need this instruction or not.
10700 Postpone the decision by emitting a ghost move. This move
10701 is specifically not frame-related; only the split version is. */
10703 emit_insn (gen_move_gpdi (dest, src));
10705 emit_insn (gen_move_gpsi (dest, src));
10709 if (regno == HI_REGNUM)
10713 mips_emit_move (temp, src);
10715 emit_insn (gen_mthisi_di (gen_rtx_REG (TImode, MD_REG_FIRST),
10716 temp, gen_rtx_REG (DImode, LO_REGNUM)));
10718 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode, MD_REG_FIRST),
10719 temp, gen_rtx_REG (SImode, LO_REGNUM)));
10724 emit_insn (gen_mfhidi_ti (temp,
10725 gen_rtx_REG (TImode, MD_REG_FIRST)));
10727 emit_insn (gen_mfhisi_di (temp,
10728 gen_rtx_REG (DImode, MD_REG_FIRST)));
10729 mips_emit_move (dest, temp);
10732 else if (mips_direct_save_slot_move_p (regno, mem, mem == src))
10733 mips_emit_move (dest, src);
10736 gcc_assert (!reg_overlap_mentioned_p (dest, temp));
10737 mips_emit_move (temp, src);
10738 mips_emit_move (dest, temp);
10741 mips_set_frame_expr (mips_frame_set (dest, src));
10744 /* If we're generating n32 or n64 abicalls, and the current function
10745 does not use $28 as its global pointer, emit a cplocal directive.
10746 Use pic_offset_table_rtx as the argument to the directive. */
10749 mips_output_cplocal (void)
10751 if (!TARGET_EXPLICIT_RELOCS
10752 && mips_must_initialize_gp_p ()
10753 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
10754 output_asm_insn (".cplocal %+", 0);
10757 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
10760 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
10762 const char *fnname;
10764 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
10765 floating-point arguments. */
10767 && TARGET_HARD_FLOAT_ABI
10768 && crtl->args.info.fp_code != 0)
10769 mips16_build_function_stub ();
10771 /* Get the function name the same way that toplev.c does before calling
10772 assemble_start_function. This is needed so that the name used here
10773 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10774 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
10775 mips_start_function_definition (fnname, TARGET_MIPS16);
10777 /* Output MIPS-specific frame information. */
10778 if (!flag_inhibit_size_directive)
10780 const struct mips_frame_info *frame;
10782 frame = &cfun->machine->frame;
10784 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
10786 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
10787 "# vars= " HOST_WIDE_INT_PRINT_DEC
10789 ", args= " HOST_WIDE_INT_PRINT_DEC
10790 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
10791 reg_names[frame_pointer_needed
10792 ? HARD_FRAME_POINTER_REGNUM
10793 : STACK_POINTER_REGNUM],
10794 (frame_pointer_needed
10795 ? frame->total_size - frame->hard_frame_pointer_offset
10796 : frame->total_size),
10797 reg_names[RETURN_ADDR_REGNUM],
10799 frame->num_gp, frame->num_fp,
10801 frame->cprestore_size);
10803 /* .mask MASK, OFFSET. */
10804 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
10805 frame->mask, frame->gp_save_offset);
10807 /* .fmask MASK, OFFSET. */
10808 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
10809 frame->fmask, frame->fp_save_offset);
10812 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
10813 Also emit the ".set noreorder; .set nomacro" sequence for functions
10815 if (mips_must_initialize_gp_p ()
10816 && mips_current_loadgp_style () == LOADGP_OLDABI)
10820 /* This is a fixed-form sequence. The position of the
10821 first two instructions is important because of the
10822 way _gp_disp is defined. */
10823 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
10824 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
10825 output_asm_insn ("sll\t$2,16", 0);
10826 output_asm_insn ("addu\t$2,$3", 0);
10830 /* .cpload must be in a .set noreorder but not a
10831 .set nomacro block. */
10832 mips_push_asm_switch (&mips_noreorder);
10833 output_asm_insn (".cpload\t%^", 0);
10834 if (!cfun->machine->all_noreorder_p)
10835 mips_pop_asm_switch (&mips_noreorder);
10837 mips_push_asm_switch (&mips_nomacro);
10840 else if (cfun->machine->all_noreorder_p)
10842 mips_push_asm_switch (&mips_noreorder);
10843 mips_push_asm_switch (&mips_nomacro);
10846 /* Tell the assembler which register we're using as the global
10847 pointer. This is needed for thunks, since they can use either
10848 explicit relocs or assembler macros. */
10849 mips_output_cplocal ();
10852 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
10855 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
10856 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
10858 const char *fnname;
10860 /* Reinstate the normal $gp. */
10861 SET_REGNO (pic_offset_table_rtx, GLOBAL_POINTER_REGNUM);
10862 mips_output_cplocal ();
10864 if (cfun->machine->all_noreorder_p)
10866 mips_pop_asm_switch (&mips_nomacro);
10867 mips_pop_asm_switch (&mips_noreorder);
10870 /* Get the function name the same way that toplev.c does before calling
10871 assemble_start_function. This is needed so that the name used here
10872 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10873 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
10874 mips_end_function_definition (fnname);
10877 /* Emit an optimisation barrier for accesses to the current frame. */
10880 mips_frame_barrier (void)
10882 emit_clobber (gen_frame_mem (BLKmode, stack_pointer_rtx));
10886 /* The __gnu_local_gp symbol. */
10888 static GTY(()) rtx mips_gnu_local_gp;
10890 /* If we're generating n32 or n64 abicalls, emit instructions
10891 to set up the global pointer. */
10894 mips_emit_loadgp (void)
10896 rtx addr, offset, incoming_address, base, index, pic_reg;
10898 pic_reg = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
10899 switch (mips_current_loadgp_style ())
10901 case LOADGP_ABSOLUTE:
10902 if (mips_gnu_local_gp == NULL)
10904 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
10905 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
10907 emit_insn (PMODE_INSN (gen_loadgp_absolute,
10908 (pic_reg, mips_gnu_local_gp)));
10911 case LOADGP_OLDABI:
10912 /* Added by mips_output_function_prologue. */
10915 case LOADGP_NEWABI:
10916 addr = XEXP (DECL_RTL (current_function_decl), 0);
10917 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
10918 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
10919 emit_insn (PMODE_INSN (gen_loadgp_newabi,
10920 (pic_reg, offset, incoming_address)));
10924 base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE));
10925 index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX));
10926 emit_insn (PMODE_INSN (gen_loadgp_rtp, (pic_reg, base, index)));
10934 emit_insn (PMODE_INSN (gen_copygp_mips16,
10935 (pic_offset_table_rtx, pic_reg)));
10937 /* Emit a blockage if there are implicit uses of the GP register.
10938 This includes profiled functions, because FUNCTION_PROFILE uses
10940 if (!TARGET_EXPLICIT_RELOCS || crtl->profile)
10941 emit_insn (gen_loadgp_blockage ());
10944 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
10946 #if PROBE_INTERVAL > 32768
10947 #error Cannot use indexed addressing mode for stack probing
10950 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
10951 inclusive. These are offsets from the current stack pointer. */
10954 mips_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size)
10957 sorry ("-fstack-check=specific not implemented for MIPS16");
10959 /* See if we have a constant small number of probes to generate. If so,
10960 that's the easy case. */
10961 if (first + size <= 32768)
10965 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
10966 it exceeds SIZE. If only one probe is needed, this will not
10967 generate any code. Then probe at FIRST + SIZE. */
10968 for (i = PROBE_INTERVAL; i < size; i += PROBE_INTERVAL)
10969 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
10972 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
10976 /* Otherwise, do the same as above, but in a loop. Note that we must be
10977 extra careful with variables wrapping around because we might be at
10978 the very top (or the very bottom) of the address space and we have
10979 to be able to handle this case properly; in particular, we use an
10980 equality test for the loop condition. */
10983 HOST_WIDE_INT rounded_size;
10984 rtx r3 = MIPS_PROLOGUE_TEMP (Pmode);
10985 rtx r12 = MIPS_PROLOGUE_TEMP2 (Pmode);
10987 /* Sanity check for the addressing mode we're going to use. */
10988 gcc_assert (first <= 32768);
10991 /* Step 1: round SIZE to the previous multiple of the interval. */
10993 rounded_size = size & -PROBE_INTERVAL;
10996 /* Step 2: compute initial and final value of the loop counter. */
10998 /* TEST_ADDR = SP + FIRST. */
10999 emit_insn (gen_rtx_SET (VOIDmode, r3,
11000 plus_constant (Pmode, stack_pointer_rtx,
11003 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
11004 if (rounded_size > 32768)
11006 emit_move_insn (r12, GEN_INT (rounded_size));
11007 emit_insn (gen_rtx_SET (VOIDmode, r12,
11008 gen_rtx_MINUS (Pmode, r3, r12)));
11011 emit_insn (gen_rtx_SET (VOIDmode, r12,
11012 plus_constant (Pmode, r3, -rounded_size)));
11015 /* Step 3: the loop
11017 while (TEST_ADDR != LAST_ADDR)
11019 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
11023 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
11024 until it is equal to ROUNDED_SIZE. */
11026 emit_insn (PMODE_INSN (gen_probe_stack_range, (r3, r3, r12)));
11029 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
11030 that SIZE is equal to ROUNDED_SIZE. */
11032 if (size != rounded_size)
11033 emit_stack_probe (plus_constant (Pmode, r12, rounded_size - size));
11036 /* Make sure nothing is scheduled before we are done. */
11037 emit_insn (gen_blockage ());
11040 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
11041 absolute addresses. */
11044 mips_output_probe_stack_range (rtx reg1, rtx reg2)
11046 static int labelno = 0;
11047 char loop_lab[32], end_lab[32], tmp[64];
11050 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno);
11051 ASM_GENERATE_INTERNAL_LABEL (end_lab, "LPSRE", labelno++);
11053 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
11055 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
11058 strcpy (tmp, "%(%<beq\t%0,%1,");
11059 output_asm_insn (strcat (tmp, &end_lab[1]), xops);
11061 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
11062 xops[1] = GEN_INT (-PROBE_INTERVAL);
11063 if (TARGET_64BIT && TARGET_LONG64)
11064 output_asm_insn ("daddiu\t%0,%0,%1", xops);
11066 output_asm_insn ("addiu\t%0,%0,%1", xops);
11068 /* Probe at TEST_ADDR and branch. */
11069 fprintf (asm_out_file, "\tb\t");
11070 assemble_name_raw (asm_out_file, loop_lab);
11071 fputc ('\n', asm_out_file);
11073 output_asm_insn ("sd\t$0,0(%0)%)", xops);
11075 output_asm_insn ("sw\t$0,0(%0)%)", xops);
11077 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, end_lab);
11082 /* A for_each_rtx callback. Stop the search if *X is a kernel register. */
11085 mips_kernel_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
11087 return REG_P (*x) && KERNEL_REG_P (REGNO (*x));
11090 /* Expand the "prologue" pattern. */
11093 mips_expand_prologue (void)
11095 const struct mips_frame_info *frame;
11096 HOST_WIDE_INT size;
11097 unsigned int nargs;
11100 if (cfun->machine->global_pointer != INVALID_REGNUM)
11102 /* Check whether an insn uses pic_offset_table_rtx, either explicitly
11103 or implicitly. If so, we can commit to using a global pointer
11104 straight away, otherwise we need to defer the decision. */
11105 if (mips_cfun_has_inflexible_gp_ref_p ()
11106 || mips_cfun_has_flexible_gp_ref_p ())
11108 cfun->machine->must_initialize_gp_p = true;
11109 cfun->machine->must_restore_gp_when_clobbered_p = true;
11112 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
11115 frame = &cfun->machine->frame;
11116 size = frame->total_size;
11118 if (flag_stack_usage_info)
11119 current_function_static_stack_size = size;
11121 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK)
11123 if (crtl->is_leaf && !cfun->calls_alloca)
11125 if (size > PROBE_INTERVAL && size > STACK_CHECK_PROTECT)
11126 mips_emit_probe_stack_range (STACK_CHECK_PROTECT,
11127 size - STACK_CHECK_PROTECT);
11130 mips_emit_probe_stack_range (STACK_CHECK_PROTECT, size);
11133 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
11134 bytes beforehand; this is enough to cover the register save area
11135 without going out of range. */
11136 if (((frame->mask | frame->fmask | frame->acc_mask) != 0)
11137 || frame->num_cop0_regs > 0)
11139 HOST_WIDE_INT step1;
11141 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
11142 if (GENERATE_MIPS16E_SAVE_RESTORE)
11144 HOST_WIDE_INT offset;
11145 unsigned int mask, regno;
11147 /* Try to merge argument stores into the save instruction. */
11148 nargs = mips16e_collect_argument_saves ();
11150 /* Build the save instruction. */
11151 mask = frame->mask;
11152 insn = mips16e_build_save_restore (false, &mask, &offset,
11154 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
11155 mips_frame_barrier ();
11158 /* Check if we need to save other registers. */
11159 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
11160 if (BITSET_P (mask, regno - GP_REG_FIRST))
11162 offset -= UNITS_PER_WORD;
11163 mips_save_restore_reg (word_mode, regno,
11164 offset, mips_save_reg);
11169 if (cfun->machine->interrupt_handler_p)
11171 HOST_WIDE_INT offset;
11174 /* If this interrupt is using a shadow register set, we need to
11175 get the stack pointer from the previous register set. */
11176 if (cfun->machine->use_shadow_register_set_p)
11177 emit_insn (gen_mips_rdpgpr (stack_pointer_rtx,
11178 stack_pointer_rtx));
11180 if (!cfun->machine->keep_interrupts_masked_p)
11182 /* Move from COP0 Cause to K0. */
11183 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K0_REG_NUM),
11184 gen_rtx_REG (SImode,
11185 COP0_CAUSE_REG_NUM)));
11186 /* Move from COP0 EPC to K1. */
11187 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
11188 gen_rtx_REG (SImode,
11189 COP0_EPC_REG_NUM)));
11192 /* Allocate the first part of the frame. */
11193 insn = gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx,
11195 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
11196 mips_frame_barrier ();
11199 /* Start at the uppermost location for saving. */
11200 offset = frame->cop0_sp_offset - size;
11201 if (!cfun->machine->keep_interrupts_masked_p)
11203 /* Push EPC into its stack slot. */
11204 mem = gen_frame_mem (word_mode,
11205 plus_constant (Pmode, stack_pointer_rtx,
11207 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
11208 offset -= UNITS_PER_WORD;
11211 /* Move from COP0 Status to K1. */
11212 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
11213 gen_rtx_REG (SImode,
11214 COP0_STATUS_REG_NUM)));
11216 /* Right justify the RIPL in k0. */
11217 if (!cfun->machine->keep_interrupts_masked_p)
11218 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode, K0_REG_NUM),
11219 gen_rtx_REG (SImode, K0_REG_NUM),
11220 GEN_INT (CAUSE_IPL)));
11222 /* Push Status into its stack slot. */
11223 mem = gen_frame_mem (word_mode,
11224 plus_constant (Pmode, stack_pointer_rtx,
11226 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
11227 offset -= UNITS_PER_WORD;
11229 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
11230 if (!cfun->machine->keep_interrupts_masked_p)
11231 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
11234 gen_rtx_REG (SImode, K0_REG_NUM)));
11236 if (!cfun->machine->keep_interrupts_masked_p)
11237 /* Enable interrupts by clearing the KSU ERL and EXL bits.
11238 IE is already the correct value, so we don't have to do
11239 anything explicit. */
11240 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
11243 gen_rtx_REG (SImode, GP_REG_FIRST)));
11245 /* Disable interrupts by clearing the KSU, ERL, EXL,
11247 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
11250 gen_rtx_REG (SImode, GP_REG_FIRST)));
11254 insn = gen_add3_insn (stack_pointer_rtx,
11257 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
11258 mips_frame_barrier ();
11261 mips_for_each_saved_acc (size, mips_save_reg);
11262 mips_for_each_saved_gpr_and_fpr (size, mips_save_reg);
11266 /* Allocate the rest of the frame. */
11269 if (SMALL_OPERAND (-size))
11270 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
11272 GEN_INT (-size)))) = 1;
11275 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
11278 /* There are no instructions to add or subtract registers
11279 from the stack pointer, so use the frame pointer as a
11280 temporary. We should always be using a frame pointer
11281 in this case anyway. */
11282 gcc_assert (frame_pointer_needed);
11283 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
11284 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
11285 hard_frame_pointer_rtx,
11286 MIPS_PROLOGUE_TEMP (Pmode)));
11287 mips_emit_move (stack_pointer_rtx, hard_frame_pointer_rtx);
11290 emit_insn (gen_sub3_insn (stack_pointer_rtx,
11292 MIPS_PROLOGUE_TEMP (Pmode)));
11294 /* Describe the combined effect of the previous instructions. */
11295 mips_set_frame_expr
11296 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
11297 plus_constant (Pmode, stack_pointer_rtx, -size)));
11299 mips_frame_barrier ();
11302 /* Set up the frame pointer, if we're using one. */
11303 if (frame_pointer_needed)
11305 HOST_WIDE_INT offset;
11307 offset = frame->hard_frame_pointer_offset;
11310 insn = mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
11311 RTX_FRAME_RELATED_P (insn) = 1;
11313 else if (SMALL_OPERAND (offset))
11315 insn = gen_add3_insn (hard_frame_pointer_rtx,
11316 stack_pointer_rtx, GEN_INT (offset));
11317 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
11321 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (offset));
11322 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
11323 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
11324 hard_frame_pointer_rtx,
11325 MIPS_PROLOGUE_TEMP (Pmode)));
11326 mips_set_frame_expr
11327 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
11328 plus_constant (Pmode, stack_pointer_rtx, offset)));
11332 mips_emit_loadgp ();
11334 /* Initialize the $gp save slot. */
11335 if (mips_cfun_has_cprestore_slot_p ())
11337 rtx base, mem, gp, temp;
11338 HOST_WIDE_INT offset;
11340 mips_get_cprestore_base_and_offset (&base, &offset, false);
11341 mem = gen_frame_mem (Pmode, plus_constant (Pmode, base, offset));
11342 gp = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
11343 temp = (SMALL_OPERAND (offset)
11344 ? gen_rtx_SCRATCH (Pmode)
11345 : MIPS_PROLOGUE_TEMP (Pmode));
11346 emit_insn (PMODE_INSN (gen_potential_cprestore,
11347 (mem, GEN_INT (offset), gp, temp)));
11349 mips_get_cprestore_base_and_offset (&base, &offset, true);
11350 mem = gen_frame_mem (Pmode, plus_constant (Pmode, base, offset));
11351 emit_insn (PMODE_INSN (gen_use_cprestore, (mem)));
11354 /* We need to search back to the last use of K0 or K1. */
11355 if (cfun->machine->interrupt_handler_p)
11357 for (insn = get_last_insn (); insn != NULL_RTX; insn = PREV_INSN (insn))
11359 && for_each_rtx (&PATTERN (insn), mips_kernel_reg_p, NULL))
11361 /* Emit a move from K1 to COP0 Status after insn. */
11362 gcc_assert (insn != NULL_RTX);
11363 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
11364 gen_rtx_REG (SImode, K1_REG_NUM)),
11368 /* If we are profiling, make sure no instructions are scheduled before
11369 the call to mcount. */
11371 emit_insn (gen_blockage ());
11374 /* Attach all pending register saves to the previous instruction.
11375 Return that instruction. */
11378 mips_epilogue_emit_cfa_restores (void)
11382 insn = get_last_insn ();
11383 gcc_assert (insn && !REG_NOTES (insn));
11384 if (mips_epilogue.cfa_restores)
11386 RTX_FRAME_RELATED_P (insn) = 1;
11387 REG_NOTES (insn) = mips_epilogue.cfa_restores;
11388 mips_epilogue.cfa_restores = 0;
11393 /* Like mips_epilogue_emit_cfa_restores, but also record that the CFA is
11394 now at REG + OFFSET. */
11397 mips_epilogue_set_cfa (rtx reg, HOST_WIDE_INT offset)
11401 insn = mips_epilogue_emit_cfa_restores ();
11402 if (reg != mips_epilogue.cfa_reg || offset != mips_epilogue.cfa_offset)
11404 RTX_FRAME_RELATED_P (insn) = 1;
11405 REG_NOTES (insn) = alloc_reg_note (REG_CFA_DEF_CFA,
11406 plus_constant (Pmode, reg, offset),
11408 mips_epilogue.cfa_reg = reg;
11409 mips_epilogue.cfa_offset = offset;
11413 /* Emit instructions to restore register REG from slot MEM. Also update
11414 the cfa_restores list. */
11417 mips_restore_reg (rtx reg, rtx mem)
11419 /* There's no MIPS16 instruction to load $31 directly. Load into
11420 $7 instead and adjust the return insn appropriately. */
11421 if (TARGET_MIPS16 && REGNO (reg) == RETURN_ADDR_REGNUM)
11422 reg = gen_rtx_REG (GET_MODE (reg), GP_REG_FIRST + 7);
11423 else if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
11425 mips_add_cfa_restore (mips_subword (reg, true));
11426 mips_add_cfa_restore (mips_subword (reg, false));
11429 mips_add_cfa_restore (reg);
11431 mips_emit_save_slot_move (reg, mem, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
11432 if (REGNO (reg) == REGNO (mips_epilogue.cfa_reg))
11433 /* The CFA is currently defined in terms of the register whose
11434 value we have just restored. Redefine the CFA in terms of
11435 the stack pointer. */
11436 mips_epilogue_set_cfa (stack_pointer_rtx,
11437 mips_epilogue.cfa_restore_sp_offset);
11440 /* Emit code to set the stack pointer to BASE + OFFSET, given that
11441 BASE + OFFSET is NEW_FRAME_SIZE bytes below the top of the frame.
11442 BASE, if not the stack pointer, is available as a temporary. */
11445 mips_deallocate_stack (rtx base, rtx offset, HOST_WIDE_INT new_frame_size)
11447 if (base == stack_pointer_rtx && offset == const0_rtx)
11450 mips_frame_barrier ();
11451 if (offset == const0_rtx)
11453 emit_move_insn (stack_pointer_rtx, base);
11454 mips_epilogue_set_cfa (stack_pointer_rtx, new_frame_size);
11456 else if (TARGET_MIPS16 && base != stack_pointer_rtx)
11458 emit_insn (gen_add3_insn (base, base, offset));
11459 mips_epilogue_set_cfa (base, new_frame_size);
11460 emit_move_insn (stack_pointer_rtx, base);
11464 emit_insn (gen_add3_insn (stack_pointer_rtx, base, offset));
11465 mips_epilogue_set_cfa (stack_pointer_rtx, new_frame_size);
11469 /* Emit any instructions needed before a return. */
11472 mips_expand_before_return (void)
11474 /* When using a call-clobbered gp, we start out with unified call
11475 insns that include instructions to restore the gp. We then split
11476 these unified calls after reload. These split calls explicitly
11477 clobber gp, so there is no need to define
11478 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
11480 For consistency, we should also insert an explicit clobber of $28
11481 before return insns, so that the post-reload optimizers know that
11482 the register is not live on exit. */
11483 if (TARGET_CALL_CLOBBERED_GP)
11484 emit_clobber (pic_offset_table_rtx);
11487 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
11491 mips_expand_epilogue (bool sibcall_p)
11493 const struct mips_frame_info *frame;
11494 HOST_WIDE_INT step1, step2;
11495 rtx base, adjust, insn;
11496 bool use_jraddiusp_p = false;
11498 if (!sibcall_p && mips_can_use_return_insn ())
11500 emit_jump_insn (gen_return ());
11504 /* In MIPS16 mode, if the return value should go into a floating-point
11505 register, we need to call a helper routine to copy it over. */
11506 if (mips16_cfun_returns_in_fpr_p ())
11507 mips16_copy_fpr_return_value ();
11509 /* Split the frame into two. STEP1 is the amount of stack we should
11510 deallocate before restoring the registers. STEP2 is the amount we
11511 should deallocate afterwards.
11513 Start off by assuming that no registers need to be restored. */
11514 frame = &cfun->machine->frame;
11515 step1 = frame->total_size;
11518 /* Work out which register holds the frame address. */
11519 if (!frame_pointer_needed)
11520 base = stack_pointer_rtx;
11523 base = hard_frame_pointer_rtx;
11524 step1 -= frame->hard_frame_pointer_offset;
11526 mips_epilogue.cfa_reg = base;
11527 mips_epilogue.cfa_offset = step1;
11528 mips_epilogue.cfa_restores = NULL_RTX;
11530 /* If we need to restore registers, deallocate as much stack as
11531 possible in the second step without going out of range. */
11532 if ((frame->mask | frame->fmask | frame->acc_mask) != 0
11533 || frame->num_cop0_regs > 0)
11535 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
11539 /* Get an rtx for STEP1 that we can add to BASE. */
11540 adjust = GEN_INT (step1);
11541 if (!SMALL_OPERAND (step1))
11543 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), adjust);
11544 adjust = MIPS_EPILOGUE_TEMP (Pmode);
11546 mips_deallocate_stack (base, adjust, step2);
11548 /* If we're using addressing macros, $gp is implicitly used by all
11549 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
11551 if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS)
11552 emit_insn (gen_blockage ());
11554 mips_epilogue.cfa_restore_sp_offset = step2;
11555 if (GENERATE_MIPS16E_SAVE_RESTORE && frame->mask != 0)
11557 unsigned int regno, mask;
11558 HOST_WIDE_INT offset;
11561 /* Generate the restore instruction. */
11562 mask = frame->mask;
11563 restore = mips16e_build_save_restore (true, &mask, &offset, 0, step2);
11565 /* Restore any other registers manually. */
11566 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
11567 if (BITSET_P (mask, regno - GP_REG_FIRST))
11569 offset -= UNITS_PER_WORD;
11570 mips_save_restore_reg (word_mode, regno, offset, mips_restore_reg);
11573 /* Restore the remaining registers and deallocate the final bit
11575 mips_frame_barrier ();
11576 emit_insn (restore);
11577 mips_epilogue_set_cfa (stack_pointer_rtx, 0);
11581 /* Restore the registers. */
11582 mips_for_each_saved_acc (frame->total_size - step2, mips_restore_reg);
11583 mips_for_each_saved_gpr_and_fpr (frame->total_size - step2,
11586 if (cfun->machine->interrupt_handler_p)
11588 HOST_WIDE_INT offset;
11591 offset = frame->cop0_sp_offset - (frame->total_size - step2);
11592 if (!cfun->machine->keep_interrupts_masked_p)
11594 /* Restore the original EPC. */
11595 mem = gen_frame_mem (word_mode,
11596 plus_constant (Pmode, stack_pointer_rtx,
11598 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
11599 offset -= UNITS_PER_WORD;
11601 /* Move to COP0 EPC. */
11602 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_EPC_REG_NUM),
11603 gen_rtx_REG (SImode, K0_REG_NUM)));
11606 /* Restore the original Status. */
11607 mem = gen_frame_mem (word_mode,
11608 plus_constant (Pmode, stack_pointer_rtx,
11610 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
11611 offset -= UNITS_PER_WORD;
11613 /* If we don't use shadow register set, we need to update SP. */
11614 if (!cfun->machine->use_shadow_register_set_p)
11615 mips_deallocate_stack (stack_pointer_rtx, GEN_INT (step2), 0);
11617 /* The choice of position is somewhat arbitrary in this case. */
11618 mips_epilogue_emit_cfa_restores ();
11620 /* Move to COP0 Status. */
11621 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
11622 gen_rtx_REG (SImode, K0_REG_NUM)));
11624 else if (TARGET_MICROMIPS
11625 && !crtl->calls_eh_return
11628 && mips_unsigned_immediate_p (step2, 5, 2))
11629 use_jraddiusp_p = true;
11631 /* Deallocate the final bit of the frame. */
11632 mips_deallocate_stack (stack_pointer_rtx, GEN_INT (step2), 0);
11635 if (!use_jraddiusp_p)
11636 gcc_assert (!mips_epilogue.cfa_restores);
11638 /* Add in the __builtin_eh_return stack adjustment. We need to
11639 use a temporary in MIPS16 code. */
11640 if (crtl->calls_eh_return)
11644 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
11645 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
11646 MIPS_EPILOGUE_TEMP (Pmode),
11647 EH_RETURN_STACKADJ_RTX));
11648 mips_emit_move (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
11651 emit_insn (gen_add3_insn (stack_pointer_rtx,
11653 EH_RETURN_STACKADJ_RTX));
11658 mips_expand_before_return ();
11659 if (cfun->machine->interrupt_handler_p)
11661 /* Interrupt handlers generate eret or deret. */
11662 if (cfun->machine->use_debug_exception_return_p)
11663 emit_jump_insn (gen_mips_deret ());
11665 emit_jump_insn (gen_mips_eret ());
11671 /* When generating MIPS16 code, the normal
11672 mips_for_each_saved_gpr_and_fpr path will restore the return
11673 address into $7 rather than $31. */
11675 && !GENERATE_MIPS16E_SAVE_RESTORE
11676 && BITSET_P (frame->mask, RETURN_ADDR_REGNUM))
11678 /* simple_returns cannot rely on values that are only available
11679 on paths through the epilogue (because return paths that do
11680 not pass through the epilogue may nevertheless reuse a
11681 simple_return that occurs at the end of the epilogue).
11682 Use a normal return here instead. */
11683 rtx reg = gen_rtx_REG (Pmode, GP_REG_FIRST + 7);
11684 pat = gen_return_internal (reg);
11686 else if (use_jraddiusp_p)
11687 pat = gen_jraddiusp (GEN_INT (step2));
11690 rtx reg = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
11691 pat = gen_simple_return_internal (reg);
11693 emit_jump_insn (pat);
11694 if (use_jraddiusp_p)
11695 mips_epilogue_set_cfa (stack_pointer_rtx, step2);
11699 /* Search from the beginning to the first use of K0 or K1. */
11700 if (cfun->machine->interrupt_handler_p
11701 && !cfun->machine->keep_interrupts_masked_p)
11703 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
11705 && for_each_rtx (&PATTERN(insn), mips_kernel_reg_p, NULL))
11707 gcc_assert (insn != NULL_RTX);
11708 /* Insert disable interrupts before the first use of K0 or K1. */
11709 emit_insn_before (gen_mips_di (), insn);
11710 emit_insn_before (gen_mips_ehb (), insn);
11714 /* Return nonzero if this function is known to have a null epilogue.
11715 This allows the optimizer to omit jumps to jumps if no stack
11719 mips_can_use_return_insn (void)
11721 /* Interrupt handlers need to go through the epilogue. */
11722 if (cfun->machine->interrupt_handler_p)
11725 if (!reload_completed)
11731 /* In MIPS16 mode, a function that returns a floating-point value
11732 needs to arrange to copy the return value into the floating-point
11734 if (mips16_cfun_returns_in_fpr_p ())
11737 return cfun->machine->frame.total_size == 0;
11740 /* Return true if register REGNO can store a value of mode MODE.
11741 The result of this function is cached in mips_hard_regno_mode_ok. */
11744 mips_hard_regno_mode_ok_p (unsigned int regno, enum machine_mode mode)
11747 enum mode_class mclass;
11749 if (mode == CCV2mode)
11750 return (ISA_HAS_8CC
11751 && ST_REG_P (regno)
11752 && (regno - ST_REG_FIRST) % 2 == 0);
11754 if (mode == CCV4mode)
11755 return (ISA_HAS_8CC
11756 && ST_REG_P (regno)
11757 && (regno - ST_REG_FIRST) % 4 == 0);
11759 if (mode == CCmode)
11760 return ISA_HAS_8CC ? ST_REG_P (regno) : regno == FPSW_REGNUM;
11762 size = GET_MODE_SIZE (mode);
11763 mclass = GET_MODE_CLASS (mode);
11765 if (GP_REG_P (regno))
11766 return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD;
11768 if (FP_REG_P (regno)
11769 && (((regno - FP_REG_FIRST) % MAX_FPRS_PER_FMT) == 0
11770 || (MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG)))
11772 /* Allow 64-bit vector modes for Loongson-2E/2F. */
11773 if (TARGET_LOONGSON_VECTORS
11774 && (mode == V2SImode
11775 || mode == V4HImode
11776 || mode == V8QImode
11777 || mode == DImode))
11780 if (mclass == MODE_FLOAT
11781 || mclass == MODE_COMPLEX_FLOAT
11782 || mclass == MODE_VECTOR_FLOAT)
11783 return size <= UNITS_PER_FPVALUE;
11785 /* Allow integer modes that fit into a single register. We need
11786 to put integers into FPRs when using instructions like CVT
11787 and TRUNC. There's no point allowing sizes smaller than a word,
11788 because the FPU has no appropriate load/store instructions. */
11789 if (mclass == MODE_INT)
11790 return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG;
11793 if (ACC_REG_P (regno)
11794 && (INTEGRAL_MODE_P (mode) || ALL_FIXED_POINT_MODE_P (mode)))
11796 if (MD_REG_P (regno))
11798 /* After a multiplication or division, clobbering HI makes
11799 the value of LO unpredictable, and vice versa. This means
11800 that, for all interesting cases, HI and LO are effectively
11803 We model this by requiring that any value that uses HI
11805 if (size <= UNITS_PER_WORD * 2)
11806 return regno == (size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST);
11810 /* DSP accumulators do not have the same restrictions as
11811 HI and LO, so we can treat them as normal doubleword
11813 if (size <= UNITS_PER_WORD)
11816 if (size <= UNITS_PER_WORD * 2
11817 && ((regno - DSP_ACC_REG_FIRST) & 1) == 0)
11822 if (ALL_COP_REG_P (regno))
11823 return mclass == MODE_INT && size <= UNITS_PER_WORD;
11825 if (regno == GOT_VERSION_REGNUM)
11826 return mode == SImode;
11831 /* Implement HARD_REGNO_NREGS. */
11834 mips_hard_regno_nregs (int regno, enum machine_mode mode)
11836 if (ST_REG_P (regno))
11837 /* The size of FP status registers is always 4, because they only hold
11838 CCmode values, and CCmode is always considered to be 4 bytes wide. */
11839 return (GET_MODE_SIZE (mode) + 3) / 4;
11841 if (FP_REG_P (regno))
11842 return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG;
11844 /* All other registers are word-sized. */
11845 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
11848 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
11849 in mips_hard_regno_nregs. */
11852 mips_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
11858 COPY_HARD_REG_SET (left, reg_class_contents[(int) rclass]);
11859 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS]))
11861 if (HARD_REGNO_MODE_OK (ST_REG_FIRST, mode))
11862 size = MIN (size, 4);
11863 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) ST_REGS]);
11865 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS]))
11867 if (HARD_REGNO_MODE_OK (FP_REG_FIRST, mode))
11868 size = MIN (size, UNITS_PER_FPREG);
11869 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]);
11871 if (!hard_reg_set_empty_p (left))
11872 size = MIN (size, UNITS_PER_WORD);
11873 return (GET_MODE_SIZE (mode) + size - 1) / size;
11876 /* Implement CANNOT_CHANGE_MODE_CLASS. */
11879 mips_cannot_change_mode_class (enum machine_mode from,
11880 enum machine_mode to,
11881 enum reg_class rclass)
11883 /* Allow conversions between different Loongson integer vectors,
11884 and between those vectors and DImode. */
11885 if (GET_MODE_SIZE (from) == 8 && GET_MODE_SIZE (to) == 8
11886 && INTEGRAL_MODE_P (from) && INTEGRAL_MODE_P (to))
11889 /* Otherwise, there are several problems with changing the modes of
11890 values in floating-point registers:
11892 - When a multi-word value is stored in paired floating-point
11893 registers, the first register always holds the low word. We
11894 therefore can't allow FPRs to change between single-word and
11895 multi-word modes on big-endian targets.
11897 - GCC assumes that each word of a multiword register can be
11898 accessed individually using SUBREGs. This is not true for
11899 floating-point registers if they are bigger than a word.
11901 - Loading a 32-bit value into a 64-bit floating-point register
11902 will not sign-extend the value, despite what LOAD_EXTEND_OP
11903 says. We can't allow FPRs to change from SImode to a wider
11904 mode on 64-bit targets.
11906 - If the FPU has already interpreted a value in one format, we
11907 must not ask it to treat the value as having a different
11910 We therefore disallow all mode changes involving FPRs. */
11912 return reg_classes_intersect_p (FP_REGS, rclass);
11915 /* Implement target hook small_register_classes_for_mode_p. */
11918 mips_small_register_classes_for_mode_p (enum machine_mode mode
11921 return TARGET_MIPS16;
11924 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
11927 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode)
11932 return TARGET_HARD_FLOAT;
11935 return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT;
11938 return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT;
11945 /* Implement MODES_TIEABLE_P. */
11948 mips_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
11950 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
11951 prefer to put one of them in FPRs. */
11952 return (mode1 == mode2
11953 || (!mips_mode_ok_for_mov_fmt_p (mode1)
11954 && !mips_mode_ok_for_mov_fmt_p (mode2)));
11957 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
11960 mips_preferred_reload_class (rtx x, reg_class_t rclass)
11962 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, rclass))
11965 if (reg_class_subset_p (FP_REGS, rclass)
11966 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x)))
11969 if (reg_class_subset_p (GR_REGS, rclass))
11972 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, rclass))
11978 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
11979 Return a "canonical" class to represent it in later calculations. */
11982 mips_canonicalize_move_class (reg_class_t rclass)
11984 /* All moves involving accumulator registers have the same cost. */
11985 if (reg_class_subset_p (rclass, ACC_REGS))
11988 /* Likewise promote subclasses of general registers to the most
11989 interesting containing class. */
11990 if (TARGET_MIPS16 && reg_class_subset_p (rclass, M16_REGS))
11992 else if (reg_class_subset_p (rclass, GENERAL_REGS))
11993 rclass = GENERAL_REGS;
11998 /* Return the cost of moving a value of mode MODE from a register of
11999 class FROM to a GPR. Return 0 for classes that are unions of other
12000 classes handled by this function. */
12003 mips_move_to_gpr_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
12010 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
12014 /* MFLO and MFHI. */
12022 /* LUI followed by MOVF. */
12028 /* This choice of value is historical. */
12036 /* Return the cost of moving a value of mode MODE from a GPR to a
12037 register of class TO. Return 0 for classes that are unions of
12038 other classes handled by this function. */
12041 mips_move_from_gpr_cost (enum machine_mode mode, reg_class_t to)
12047 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
12051 /* MTLO and MTHI. */
12059 /* A secondary reload through an FPR scratch. */
12060 return (mips_register_move_cost (mode, GENERAL_REGS, FP_REGS)
12061 + mips_register_move_cost (mode, FP_REGS, ST_REGS));
12066 /* This choice of value is historical. */
12074 /* Implement TARGET_REGISTER_MOVE_COST. Return 0 for classes that are the
12075 maximum of the move costs for subclasses; regclass will work out
12076 the maximum for us. */
12079 mips_register_move_cost (enum machine_mode mode,
12080 reg_class_t from, reg_class_t to)
12085 from = mips_canonicalize_move_class (from);
12086 to = mips_canonicalize_move_class (to);
12088 /* Handle moves that can be done without using general-purpose registers. */
12089 if (from == FP_REGS)
12091 if (to == FP_REGS && mips_mode_ok_for_mov_fmt_p (mode))
12095 /* The sequence generated by mips_expand_fcc_reload. */
12099 /* Handle cases in which only one class deviates from the ideal. */
12100 dregs = TARGET_MIPS16 ? M16_REGS : GENERAL_REGS;
12102 return mips_move_from_gpr_cost (mode, to);
12104 return mips_move_to_gpr_cost (mode, from);
12106 /* Handles cases that require a GPR temporary. */
12107 cost1 = mips_move_to_gpr_cost (mode, from);
12110 cost2 = mips_move_from_gpr_cost (mode, to);
12112 return cost1 + cost2;
12118 /* Implement TARGET_MEMORY_MOVE_COST. */
12121 mips_memory_move_cost (enum machine_mode mode, reg_class_t rclass, bool in)
12123 return (mips_cost->memory_latency
12124 + memory_move_secondary_cost (mode, rclass, in));
12127 /* Return the register class required for a secondary register when
12128 copying between one of the registers in RCLASS and value X, which
12129 has mode MODE. X is the source of the move if IN_P, otherwise it
12130 is the destination. Return NO_REGS if no secondary register is
12134 mips_secondary_reload_class (enum reg_class rclass,
12135 enum machine_mode mode, rtx x, bool in_p)
12139 /* If X is a constant that cannot be loaded into $25, it must be loaded
12140 into some other GPR. No other register class allows a direct move. */
12141 if (mips_dangerous_for_la25_p (x))
12142 return reg_class_subset_p (rclass, LEA_REGS) ? NO_REGS : LEA_REGS;
12144 regno = true_regnum (x);
12147 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
12148 if (!reg_class_subset_p (rclass, M16_REGS) && !M16_REG_P (regno))
12154 /* Copying from accumulator registers to anywhere other than a general
12155 register requires a temporary general register. */
12156 if (reg_class_subset_p (rclass, ACC_REGS))
12157 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
12158 if (ACC_REG_P (regno))
12159 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
12161 /* We can only copy a value to a condition code register from a
12162 floating-point register, and even then we require a scratch
12163 floating-point register. We can only copy a value out of a
12164 condition-code register into a general register. */
12165 if (reg_class_subset_p (rclass, ST_REGS))
12169 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
12171 if (ST_REG_P (regno))
12175 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
12178 if (reg_class_subset_p (rclass, FP_REGS))
12181 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8))
12182 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
12183 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
12186 if (GP_REG_P (regno) || x == CONST0_RTX (mode))
12187 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
12190 if (CONSTANT_P (x) && !targetm.cannot_force_const_mem (mode, x))
12191 /* We can force the constant to memory and use lwc1
12192 and ldc1. As above, we will use pairs of lwc1s if
12193 ldc1 is not supported. */
12196 if (FP_REG_P (regno) && mips_mode_ok_for_mov_fmt_p (mode))
12197 /* In this case we can use mov.fmt. */
12200 /* Otherwise, we need to reload through an integer register. */
12203 if (FP_REG_P (regno))
12204 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
12209 /* Implement TARGET_MODE_REP_EXTENDED. */
12212 mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
12214 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
12215 if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
12216 return SIGN_EXTEND;
12221 /* Implement TARGET_VALID_POINTER_MODE. */
12224 mips_valid_pointer_mode (enum machine_mode mode)
12226 return mode == SImode || (TARGET_64BIT && mode == DImode);
12229 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
12232 mips_vector_mode_supported_p (enum machine_mode mode)
12237 return TARGET_PAIRED_SINGLE_FLOAT;
12252 return TARGET_LOONGSON_VECTORS;
12259 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
12262 mips_scalar_mode_supported_p (enum machine_mode mode)
12264 if (ALL_FIXED_POINT_MODE_P (mode)
12265 && GET_MODE_PRECISION (mode) <= 2 * BITS_PER_WORD)
12268 return default_scalar_mode_supported_p (mode);
12271 /* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
12273 static enum machine_mode
12274 mips_preferred_simd_mode (enum machine_mode mode ATTRIBUTE_UNUSED)
12276 if (TARGET_PAIRED_SINGLE_FLOAT
12282 /* Implement TARGET_INIT_LIBFUNCS. */
12285 mips_init_libfuncs (void)
12287 if (TARGET_FIX_VR4120)
12289 /* Register the special divsi3 and modsi3 functions needed to work
12290 around VR4120 division errata. */
12291 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
12292 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
12295 if (TARGET_MIPS16 && TARGET_HARD_FLOAT_ABI)
12297 /* Register the MIPS16 -mhard-float stubs. */
12298 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
12299 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
12300 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
12301 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
12303 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
12304 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
12305 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
12306 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
12307 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
12308 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
12309 set_optab_libfunc (unord_optab, SFmode, "__mips16_unordsf2");
12311 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
12312 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
12313 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__mips16_floatunsisf");
12315 if (TARGET_DOUBLE_FLOAT)
12317 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
12318 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
12319 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
12320 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
12322 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
12323 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
12324 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
12325 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
12326 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
12327 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
12328 set_optab_libfunc (unord_optab, DFmode, "__mips16_unorddf2");
12330 set_conv_libfunc (sext_optab, DFmode, SFmode,
12331 "__mips16_extendsfdf2");
12332 set_conv_libfunc (trunc_optab, SFmode, DFmode,
12333 "__mips16_truncdfsf2");
12334 set_conv_libfunc (sfix_optab, SImode, DFmode,
12335 "__mips16_fix_truncdfsi");
12336 set_conv_libfunc (sfloat_optab, DFmode, SImode,
12337 "__mips16_floatsidf");
12338 set_conv_libfunc (ufloat_optab, DFmode, SImode,
12339 "__mips16_floatunsidf");
12343 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
12344 on an external non-MIPS16 routine to implement __sync_synchronize.
12345 Similarly for the rest of the ll/sc libfuncs. */
12348 synchronize_libfunc = init_one_libfunc ("__sync_synchronize");
12349 init_sync_libfuncs (UNITS_PER_WORD);
12353 /* Build up a multi-insn sequence that loads label TARGET into $AT. */
12356 mips_process_load_label (rtx target)
12358 rtx base, gp, intop;
12359 HOST_WIDE_INT offset;
12361 mips_multi_start ();
12365 mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target, 0);
12366 mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target, 0);
12370 mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target, 0);
12371 mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target, 0);
12375 gp = pic_offset_table_rtx;
12376 if (mips_cfun_has_cprestore_slot_p ())
12378 gp = gen_rtx_REG (Pmode, AT_REGNUM);
12379 mips_get_cprestore_base_and_offset (&base, &offset, true);
12380 if (!SMALL_OPERAND (offset))
12382 intop = GEN_INT (CONST_HIGH_PART (offset));
12383 mips_multi_add_insn ("lui\t%0,%1", gp, intop, 0);
12384 mips_multi_add_insn ("addu\t%0,%0,%1", gp, base, 0);
12387 offset = CONST_LOW_PART (offset);
12389 intop = GEN_INT (offset);
12390 if (ISA_HAS_LOAD_DELAY)
12391 mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp, intop, base, 0);
12393 mips_multi_add_insn ("lw\t%0,%1(%2)", gp, intop, base, 0);
12395 if (ISA_HAS_LOAD_DELAY)
12396 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target, gp, 0);
12398 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target, gp, 0);
12399 mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target, 0);
12404 /* Return the number of instructions needed to load a label into $AT. */
12406 static unsigned int
12407 mips_load_label_num_insns (void)
12409 if (cfun->machine->load_label_num_insns == 0)
12411 mips_process_load_label (pc_rtx);
12412 cfun->machine->load_label_num_insns = mips_multi_num_insns;
12414 return cfun->machine->load_label_num_insns;
12417 /* Emit an asm sequence to start a noat block and load the address
12418 of a label into $1. */
12421 mips_output_load_label (rtx target)
12423 mips_push_asm_switch (&mips_noat);
12424 if (TARGET_EXPLICIT_RELOCS)
12426 mips_process_load_label (target);
12427 mips_multi_write ();
12431 if (Pmode == DImode)
12432 output_asm_insn ("dla\t%@,%0", &target);
12434 output_asm_insn ("la\t%@,%0", &target);
12438 /* Return the length of INSN. LENGTH is the initial length computed by
12439 attributes in the machine-description file. */
12442 mips_adjust_insn_length (rtx insn, int length)
12444 /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length
12445 of a PIC long-branch sequence. Substitute the correct value. */
12446 if (length == MAX_PIC_BRANCH_LENGTH
12448 && INSN_CODE (insn) >= 0
12449 && get_attr_type (insn) == TYPE_BRANCH)
12451 /* Add the branch-over instruction and its delay slot, if this
12452 is a conditional branch. */
12453 length = simplejump_p (insn) ? 0 : 8;
12455 /* Add the size of a load into $AT. */
12456 length += BASE_INSN_LENGTH * mips_load_label_num_insns ();
12458 /* Add the length of an indirect jump, ignoring the delay slot. */
12459 length += TARGET_COMPRESSION ? 2 : 4;
12462 /* A unconditional jump has an unfilled delay slot if it is not part
12463 of a sequence. A conditional jump normally has a delay slot, but
12464 does not on MIPS16. */
12465 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
12466 length += TARGET_MIPS16 ? 2 : 4;
12468 /* See how many nops might be needed to avoid hardware hazards. */
12469 if (!cfun->machine->ignore_hazard_length_p
12471 && INSN_CODE (insn) >= 0)
12472 switch (get_attr_hazard (insn))
12478 length += NOP_INSN_LENGTH;
12482 length += NOP_INSN_LENGTH * 2;
12489 /* Return the assembly code for INSN, which has the operands given by
12490 OPERANDS, and which branches to OPERANDS[0] if some condition is true.
12491 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0]
12492 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
12493 version of BRANCH_IF_TRUE. */
12496 mips_output_conditional_branch (rtx insn, rtx *operands,
12497 const char *branch_if_true,
12498 const char *branch_if_false)
12500 unsigned int length;
12501 rtx taken, not_taken;
12503 gcc_assert (LABEL_P (operands[0]));
12505 length = get_attr_length (insn);
12508 /* Just a simple conditional branch. */
12509 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
12510 return branch_if_true;
12513 /* Generate a reversed branch around a direct jump. This fallback does
12514 not use branch-likely instructions. */
12515 mips_branch_likely = false;
12516 not_taken = gen_label_rtx ();
12517 taken = operands[0];
12519 /* Generate the reversed branch to NOT_TAKEN. */
12520 operands[0] = not_taken;
12521 output_asm_insn (branch_if_false, operands);
12523 /* If INSN has a delay slot, we must provide delay slots for both the
12524 branch to NOT_TAKEN and the conditional jump. We must also ensure
12525 that INSN's delay slot is executed in the appropriate cases. */
12526 if (final_sequence)
12528 /* This first delay slot will always be executed, so use INSN's
12529 delay slot if is not annulled. */
12530 if (!INSN_ANNULLED_BRANCH_P (insn))
12532 final_scan_insn (XVECEXP (final_sequence, 0, 1),
12533 asm_out_file, optimize, 1, NULL);
12534 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
12537 output_asm_insn ("nop", 0);
12538 fprintf (asm_out_file, "\n");
12541 /* Output the unconditional branch to TAKEN. */
12542 if (TARGET_ABSOLUTE_JUMPS)
12543 output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken);
12546 mips_output_load_label (taken);
12547 output_asm_insn ("jr\t%@%]%/", 0);
12550 /* Now deal with its delay slot; see above. */
12551 if (final_sequence)
12553 /* This delay slot will only be executed if the branch is taken.
12554 Use INSN's delay slot if is annulled. */
12555 if (INSN_ANNULLED_BRANCH_P (insn))
12557 final_scan_insn (XVECEXP (final_sequence, 0, 1),
12558 asm_out_file, optimize, 1, NULL);
12559 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
12562 output_asm_insn ("nop", 0);
12563 fprintf (asm_out_file, "\n");
12566 /* Output NOT_TAKEN. */
12567 targetm.asm_out.internal_label (asm_out_file, "L",
12568 CODE_LABEL_NUMBER (not_taken));
12572 /* Return the assembly code for INSN, which branches to OPERANDS[0]
12573 if some ordering condition is true. The condition is given by
12574 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
12575 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
12576 its second is always zero. */
12579 mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
12581 const char *branch[2];
12583 /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true.
12584 Make BRANCH[0] branch on the inverse condition. */
12585 switch (GET_CODE (operands[1]))
12587 /* These cases are equivalent to comparisons against zero. */
12589 inverted_p = !inverted_p;
12590 /* Fall through. */
12592 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%0");
12593 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%0");
12596 /* These cases are always true or always false. */
12598 inverted_p = !inverted_p;
12599 /* Fall through. */
12601 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%0");
12602 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%0");
12606 branch[!inverted_p] = MIPS_BRANCH ("b%C1z", "%2,%0");
12607 branch[inverted_p] = MIPS_BRANCH ("b%N1z", "%2,%0");
12610 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
12613 /* Start a block of code that needs access to the LL, SC and SYNC
12617 mips_start_ll_sc_sync_block (void)
12619 if (!ISA_HAS_LL_SC)
12621 output_asm_insn (".set\tpush", 0);
12623 output_asm_insn (".set\tmips3", 0);
12625 output_asm_insn (".set\tmips2", 0);
12629 /* End a block started by mips_start_ll_sc_sync_block. */
12632 mips_end_ll_sc_sync_block (void)
12634 if (!ISA_HAS_LL_SC)
12635 output_asm_insn (".set\tpop", 0);
12638 /* Output and/or return the asm template for a sync instruction. */
12641 mips_output_sync (void)
12643 mips_start_ll_sc_sync_block ();
12644 output_asm_insn ("sync", 0);
12645 mips_end_ll_sc_sync_block ();
12649 /* Return the asm template associated with sync_insn1 value TYPE.
12650 IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */
12652 static const char *
12653 mips_sync_insn1_template (enum attr_sync_insn1 type, bool is_64bit_p)
12657 case SYNC_INSN1_MOVE:
12658 return "move\t%0,%z2";
12659 case SYNC_INSN1_LI:
12660 return "li\t%0,%2";
12661 case SYNC_INSN1_ADDU:
12662 return is_64bit_p ? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2";
12663 case SYNC_INSN1_ADDIU:
12664 return is_64bit_p ? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2";
12665 case SYNC_INSN1_SUBU:
12666 return is_64bit_p ? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2";
12667 case SYNC_INSN1_AND:
12668 return "and\t%0,%1,%z2";
12669 case SYNC_INSN1_ANDI:
12670 return "andi\t%0,%1,%2";
12671 case SYNC_INSN1_OR:
12672 return "or\t%0,%1,%z2";
12673 case SYNC_INSN1_ORI:
12674 return "ori\t%0,%1,%2";
12675 case SYNC_INSN1_XOR:
12676 return "xor\t%0,%1,%z2";
12677 case SYNC_INSN1_XORI:
12678 return "xori\t%0,%1,%2";
12680 gcc_unreachable ();
12683 /* Return the asm template associated with sync_insn2 value TYPE. */
12685 static const char *
12686 mips_sync_insn2_template (enum attr_sync_insn2 type)
12690 case SYNC_INSN2_NOP:
12691 gcc_unreachable ();
12692 case SYNC_INSN2_AND:
12693 return "and\t%0,%1,%z2";
12694 case SYNC_INSN2_XOR:
12695 return "xor\t%0,%1,%z2";
12696 case SYNC_INSN2_NOT:
12697 return "nor\t%0,%1,%.";
12699 gcc_unreachable ();
12702 /* OPERANDS are the operands to a sync loop instruction and INDEX is
12703 the value of the one of the sync_* attributes. Return the operand
12704 referred to by the attribute, or DEFAULT_VALUE if the insn doesn't
12705 have the associated attribute. */
12708 mips_get_sync_operand (rtx *operands, int index, rtx default_value)
12711 default_value = operands[index - 1];
12712 return default_value;
12715 /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn
12716 sequence for it. */
12719 mips_process_sync_loop (rtx insn, rtx *operands)
12721 rtx at, mem, oldval, newval, inclusive_mask, exclusive_mask;
12722 rtx required_oldval, insn1_op2, tmp1, tmp2, tmp3, cmp;
12723 unsigned int tmp3_insn;
12724 enum attr_sync_insn1 insn1;
12725 enum attr_sync_insn2 insn2;
12728 enum memmodel model;
12730 /* Read an operand from the sync_WHAT attribute and store it in
12731 variable WHAT. DEFAULT is the default value if no attribute
12733 #define READ_OPERAND(WHAT, DEFAULT) \
12734 WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \
12737 /* Read the memory. */
12738 READ_OPERAND (mem, 0);
12740 is_64bit_p = (GET_MODE_BITSIZE (GET_MODE (mem)) == 64);
12742 /* Read the other attributes. */
12743 at = gen_rtx_REG (GET_MODE (mem), AT_REGNUM);
12744 READ_OPERAND (oldval, at);
12745 READ_OPERAND (cmp, 0);
12746 READ_OPERAND (newval, at);
12747 READ_OPERAND (inclusive_mask, 0);
12748 READ_OPERAND (exclusive_mask, 0);
12749 READ_OPERAND (required_oldval, 0);
12750 READ_OPERAND (insn1_op2, 0);
12751 insn1 = get_attr_sync_insn1 (insn);
12752 insn2 = get_attr_sync_insn2 (insn);
12754 /* Don't bother setting CMP result that is never used. */
12755 if (cmp && find_reg_note (insn, REG_UNUSED, cmp))
12758 memmodel_attr = get_attr_sync_memmodel (insn);
12759 switch (memmodel_attr)
12762 model = MEMMODEL_ACQ_REL;
12765 model = MEMMODEL_ACQUIRE;
12768 model = (enum memmodel) INTVAL (operands[memmodel_attr]);
12771 mips_multi_start ();
12773 /* Output the release side of the memory barrier. */
12774 if (need_atomic_barrier_p (model, true))
12776 if (required_oldval == 0 && TARGET_OCTEON)
12778 /* Octeon doesn't reorder reads, so a full barrier can be
12779 created by using SYNCW to order writes combined with the
12780 write from the following SC. When the SC successfully
12781 completes, we know that all preceding writes are also
12782 committed to the coherent memory system. It is possible
12783 for a single SYNCW to fail, but a pair of them will never
12784 fail, so we use two. */
12785 mips_multi_add_insn ("syncw", NULL);
12786 mips_multi_add_insn ("syncw", NULL);
12789 mips_multi_add_insn ("sync", NULL);
12792 /* Output the branch-back label. */
12793 mips_multi_add_label ("1:");
12795 /* OLDVAL = *MEM. */
12796 mips_multi_add_insn (is_64bit_p ? "lld\t%0,%1" : "ll\t%0,%1",
12797 oldval, mem, NULL);
12799 /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */
12800 if (required_oldval)
12802 if (inclusive_mask == 0)
12806 gcc_assert (oldval != at);
12807 mips_multi_add_insn ("and\t%0,%1,%2",
12808 at, oldval, inclusive_mask, NULL);
12811 mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1, required_oldval, NULL);
12813 /* CMP = 0 [delay slot]. */
12815 mips_multi_add_insn ("li\t%0,0", cmp, NULL);
12818 /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */
12819 if (exclusive_mask == 0)
12823 gcc_assert (oldval != at);
12824 mips_multi_add_insn ("and\t%0,%1,%z2",
12825 at, oldval, exclusive_mask, NULL);
12829 /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2).
12831 We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit
12832 at least one instruction in that case. */
12833 if (insn1 == SYNC_INSN1_MOVE
12834 && (tmp1 != const0_rtx || insn2 != SYNC_INSN2_NOP))
12838 mips_multi_add_insn (mips_sync_insn1_template (insn1, is_64bit_p),
12839 newval, oldval, insn1_op2, NULL);
12843 /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */
12844 if (insn2 == SYNC_INSN2_NOP)
12848 mips_multi_add_insn (mips_sync_insn2_template (insn2),
12849 newval, tmp2, inclusive_mask, NULL);
12852 tmp3_insn = mips_multi_last_index ();
12854 /* $AT = $TMP1 | $TMP3. */
12855 if (tmp1 == const0_rtx || tmp3 == const0_rtx)
12857 mips_multi_set_operand (tmp3_insn, 0, at);
12862 gcc_assert (tmp1 != tmp3);
12863 mips_multi_add_insn ("or\t%0,%1,%2", at, tmp1, tmp3, NULL);
12866 /* if (!commit (*MEM = $AT)) goto 1.
12868 This will sometimes be a delayed branch; see the write code below
12870 mips_multi_add_insn (is_64bit_p ? "scd\t%0,%1" : "sc\t%0,%1", at, mem, NULL);
12871 mips_multi_add_insn ("beq%?\t%0,%.,1b", at, NULL);
12873 /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */
12874 if (insn1 != SYNC_INSN1_MOVE && insn1 != SYNC_INSN1_LI && tmp3 != newval)
12876 mips_multi_copy_insn (tmp3_insn);
12877 mips_multi_set_operand (mips_multi_last_index (), 0, newval);
12879 else if (!(required_oldval && cmp))
12880 mips_multi_add_insn ("nop", NULL);
12882 /* CMP = 1 -- either standalone or in a delay slot. */
12883 if (required_oldval && cmp)
12884 mips_multi_add_insn ("li\t%0,1", cmp, NULL);
12886 /* Output the acquire side of the memory barrier. */
12887 if (TARGET_SYNC_AFTER_SC && need_atomic_barrier_p (model, false))
12888 mips_multi_add_insn ("sync", NULL);
12890 /* Output the exit label, if needed. */
12891 if (required_oldval)
12892 mips_multi_add_label ("2:");
12894 #undef READ_OPERAND
12897 /* Output and/or return the asm template for sync loop INSN, which has
12898 the operands given by OPERANDS. */
12901 mips_output_sync_loop (rtx insn, rtx *operands)
12903 mips_process_sync_loop (insn, operands);
12905 /* Use branch-likely instructions to work around the LL/SC R10000
12907 mips_branch_likely = TARGET_FIX_R10000;
12909 mips_push_asm_switch (&mips_noreorder);
12910 mips_push_asm_switch (&mips_nomacro);
12911 mips_push_asm_switch (&mips_noat);
12912 mips_start_ll_sc_sync_block ();
12914 mips_multi_write ();
12916 mips_end_ll_sc_sync_block ();
12917 mips_pop_asm_switch (&mips_noat);
12918 mips_pop_asm_switch (&mips_nomacro);
12919 mips_pop_asm_switch (&mips_noreorder);
12924 /* Return the number of individual instructions in sync loop INSN,
12925 which has the operands given by OPERANDS. */
12928 mips_sync_loop_insns (rtx insn, rtx *operands)
12930 mips_process_sync_loop (insn, operands);
12931 return mips_multi_num_insns;
12934 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
12935 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
12937 When working around R4000 and R4400 errata, we need to make sure that
12938 the division is not immediately followed by a shift[1][2]. We also
12939 need to stop the division from being put into a branch delay slot[3].
12940 The easiest way to avoid both problems is to add a nop after the
12941 division. When a divide-by-zero check is needed, this nop can be
12942 used to fill the branch delay slot.
12944 [1] If a double-word or a variable shift executes immediately
12945 after starting an integer division, the shift may give an
12946 incorrect result. See quotations of errata #16 and #28 from
12947 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
12948 in mips.md for details.
12950 [2] A similar bug to [1] exists for all revisions of the
12951 R4000 and the R4400 when run in an MC configuration.
12952 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
12954 "19. In this following sequence:
12956 ddiv (or ddivu or div or divu)
12957 dsll32 (or dsrl32, dsra32)
12959 if an MPT stall occurs, while the divide is slipping the cpu
12960 pipeline, then the following double shift would end up with an
12963 Workaround: The compiler needs to avoid generating any
12964 sequence with divide followed by extended double shift."
12966 This erratum is also present in "MIPS R4400MC Errata, Processor
12967 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
12968 & 3.0" as errata #10 and #4, respectively.
12970 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
12971 (also valid for MIPS R4000MC processors):
12973 "52. R4000SC: This bug does not apply for the R4000PC.
12975 There are two flavors of this bug:
12977 1) If the instruction just after divide takes an RF exception
12978 (tlb-refill, tlb-invalid) and gets an instruction cache
12979 miss (both primary and secondary) and the line which is
12980 currently in secondary cache at this index had the first
12981 data word, where the bits 5..2 are set, then R4000 would
12982 get a wrong result for the div.
12987 ------------------- # end-of page. -tlb-refill
12992 ------------------- # end-of page. -tlb-invalid
12995 2) If the divide is in the taken branch delay slot, where the
12996 target takes RF exception and gets an I-cache miss for the
12997 exception vector or where I-cache miss occurs for the
12998 target address, under the above mentioned scenarios, the
12999 div would get wrong results.
13002 j r2 # to next page mapped or unmapped
13003 div r8,r9 # this bug would be there as long
13004 # as there is an ICache miss and
13005 nop # the "data pattern" is present
13008 beq r0, r0, NextPage # to Next page
13012 This bug is present for div, divu, ddiv, and ddivu
13015 Workaround: For item 1), OS could make sure that the next page
13016 after the divide instruction is also mapped. For item 2), the
13017 compiler could make sure that the divide instruction is not in
13018 the branch delay slot."
13020 These processors have PRId values of 0x00004220 and 0x00004300 for
13021 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
13024 mips_output_division (const char *division, rtx *operands)
13029 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
13031 output_asm_insn (s, operands);
13034 if (TARGET_CHECK_ZERO_DIV)
13038 output_asm_insn (s, operands);
13039 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
13041 else if (GENERATE_DIVIDE_TRAPS)
13043 /* Avoid long replay penalty on load miss by putting the trap before
13046 output_asm_insn ("teq\t%2,%.,7", operands);
13049 output_asm_insn (s, operands);
13050 s = "teq\t%2,%.,7";
13055 output_asm_insn ("%(bne\t%2,%.,1f", operands);
13056 output_asm_insn (s, operands);
13057 s = "break\t7%)\n1:";
13063 /* Return true if IN_INSN is a multiply-add or multiply-subtract
13064 instruction and if OUT_INSN assigns to the accumulator operand. */
13067 mips_linked_madd_p (rtx out_insn, rtx in_insn)
13069 enum attr_accum_in accum_in;
13070 int accum_in_opnum;
13073 if (recog_memoized (in_insn) < 0)
13076 accum_in = get_attr_accum_in (in_insn);
13077 if (accum_in == ACCUM_IN_NONE)
13080 accum_in_opnum = accum_in - ACCUM_IN_0;
13082 extract_insn (in_insn);
13083 gcc_assert (accum_in_opnum < recog_data.n_operands);
13084 accum_in_op = recog_data.operand[accum_in_opnum];
13086 return reg_set_p (accum_in_op, out_insn);
13089 /* True if the dependency between OUT_INSN and IN_INSN is on the store
13090 data rather than the address. We need this because the cprestore
13091 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
13092 which causes the default routine to abort. We just return false
13096 mips_store_data_bypass_p (rtx out_insn, rtx in_insn)
13098 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
13101 return !store_data_bypass_p (out_insn, in_insn);
13105 /* Variables and flags used in scheduler hooks when tuning for
13109 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
13112 /* If true, then next ALU1/2 instruction will go to ALU1. */
13115 /* If true, then next FALU1/2 unstruction will go to FALU1. */
13118 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
13119 int alu1_core_unit_code;
13120 int alu2_core_unit_code;
13121 int falu1_core_unit_code;
13122 int falu2_core_unit_code;
13124 /* True if current cycle has a multi instruction.
13125 This flag is used in mips_ls2_dfa_post_advance_cycle. */
13126 bool cycle_has_multi_p;
13128 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
13129 These are used in mips_ls2_dfa_post_advance_cycle to initialize
13131 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
13132 instruction to go ALU1. */
13133 rtx alu1_turn_enabled_insn;
13134 rtx alu2_turn_enabled_insn;
13135 rtx falu1_turn_enabled_insn;
13136 rtx falu2_turn_enabled_insn;
13139 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
13140 dependencies have no cost, except on the 20Kc where output-dependence
13141 is treated like input-dependence. */
13144 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
13145 rtx dep ATTRIBUTE_UNUSED, int cost)
13147 if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT
13150 if (REG_NOTE_KIND (link) != 0)
13155 /* Return the number of instructions that can be issued per cycle. */
13158 mips_issue_rate (void)
13162 case PROCESSOR_74KC:
13163 case PROCESSOR_74KF2_1:
13164 case PROCESSOR_74KF1_1:
13165 case PROCESSOR_74KF3_2:
13166 /* The 74k is not strictly quad-issue cpu, but can be seen as one
13167 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
13168 but in reality only a maximum of 3 insns can be issued as
13169 floating-point loads and stores also require a slot in the
13171 case PROCESSOR_R10000:
13172 /* All R10K Processors are quad-issue (being the first MIPS
13173 processors to support this feature). */
13176 case PROCESSOR_20KC:
13177 case PROCESSOR_R4130:
13178 case PROCESSOR_R5400:
13179 case PROCESSOR_R5500:
13180 case PROCESSOR_R5900:
13181 case PROCESSOR_R7000:
13182 case PROCESSOR_R9000:
13183 case PROCESSOR_OCTEON:
13184 case PROCESSOR_OCTEON2:
13187 case PROCESSOR_SB1:
13188 case PROCESSOR_SB1A:
13189 /* This is actually 4, but we get better performance if we claim 3.
13190 This is partly because of unwanted speculative code motion with the
13191 larger number, and partly because in most common cases we can't
13192 reach the theoretical max of 4. */
13195 case PROCESSOR_LOONGSON_2E:
13196 case PROCESSOR_LOONGSON_2F:
13197 case PROCESSOR_LOONGSON_3A:
13200 case PROCESSOR_XLP:
13201 return (reload_completed ? 4 : 3);
13208 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
13211 mips_ls2_init_dfa_post_cycle_insn (void)
13214 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
13215 mips_ls2.alu1_turn_enabled_insn = get_insns ();
13219 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
13220 mips_ls2.alu2_turn_enabled_insn = get_insns ();
13224 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
13225 mips_ls2.falu1_turn_enabled_insn = get_insns ();
13229 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
13230 mips_ls2.falu2_turn_enabled_insn = get_insns ();
13233 mips_ls2.alu1_core_unit_code = get_cpu_unit_code ("ls2_alu1_core");
13234 mips_ls2.alu2_core_unit_code = get_cpu_unit_code ("ls2_alu2_core");
13235 mips_ls2.falu1_core_unit_code = get_cpu_unit_code ("ls2_falu1_core");
13236 mips_ls2.falu2_core_unit_code = get_cpu_unit_code ("ls2_falu2_core");
13239 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
13240 Init data used in mips_dfa_post_advance_cycle. */
13243 mips_init_dfa_post_cycle_insn (void)
13245 if (TUNE_LOONGSON_2EF)
13246 mips_ls2_init_dfa_post_cycle_insn ();
13249 /* Initialize STATE when scheduling for Loongson 2E/2F.
13250 Support round-robin dispatch scheme by enabling only one of
13251 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
13255 mips_ls2_dfa_post_advance_cycle (state_t state)
13257 if (cpu_unit_reservation_p (state, mips_ls2.alu1_core_unit_code))
13259 /* Though there are no non-pipelined ALU1 insns,
13260 we can get an instruction of type 'multi' before reload. */
13261 gcc_assert (mips_ls2.cycle_has_multi_p);
13262 mips_ls2.alu1_turn_p = false;
13265 mips_ls2.cycle_has_multi_p = false;
13267 if (cpu_unit_reservation_p (state, mips_ls2.alu2_core_unit_code))
13268 /* We have a non-pipelined alu instruction in the core,
13269 adjust round-robin counter. */
13270 mips_ls2.alu1_turn_p = true;
13272 if (mips_ls2.alu1_turn_p)
13274 if (state_transition (state, mips_ls2.alu1_turn_enabled_insn) >= 0)
13275 gcc_unreachable ();
13279 if (state_transition (state, mips_ls2.alu2_turn_enabled_insn) >= 0)
13280 gcc_unreachable ();
13283 if (cpu_unit_reservation_p (state, mips_ls2.falu1_core_unit_code))
13285 /* There are no non-pipelined FALU1 insns. */
13286 gcc_unreachable ();
13287 mips_ls2.falu1_turn_p = false;
13290 if (cpu_unit_reservation_p (state, mips_ls2.falu2_core_unit_code))
13291 /* We have a non-pipelined falu instruction in the core,
13292 adjust round-robin counter. */
13293 mips_ls2.falu1_turn_p = true;
13295 if (mips_ls2.falu1_turn_p)
13297 if (state_transition (state, mips_ls2.falu1_turn_enabled_insn) >= 0)
13298 gcc_unreachable ();
13302 if (state_transition (state, mips_ls2.falu2_turn_enabled_insn) >= 0)
13303 gcc_unreachable ();
13307 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
13308 This hook is being called at the start of each cycle. */
13311 mips_dfa_post_advance_cycle (void)
13313 if (TUNE_LOONGSON_2EF)
13314 mips_ls2_dfa_post_advance_cycle (curr_state);
13317 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
13318 be as wide as the scheduling freedom in the DFA. */
13321 mips_multipass_dfa_lookahead (void)
13323 /* Can schedule up to 4 of the 6 function units in any one cycle. */
13327 if (TUNE_LOONGSON_2EF || TUNE_LOONGSON_3A)
13336 /* Remove the instruction at index LOWER from ready queue READY and
13337 reinsert it in front of the instruction at index HIGHER. LOWER must
13341 mips_promote_ready (rtx *ready, int lower, int higher)
13346 new_head = ready[lower];
13347 for (i = lower; i < higher; i++)
13348 ready[i] = ready[i + 1];
13349 ready[i] = new_head;
13352 /* If the priority of the instruction at POS2 in the ready queue READY
13353 is within LIMIT units of that of the instruction at POS1, swap the
13354 instructions if POS2 is not already less than POS1. */
13357 mips_maybe_swap_ready (rtx *ready, int pos1, int pos2, int limit)
13360 && INSN_PRIORITY (ready[pos1]) + limit >= INSN_PRIORITY (ready[pos2]))
13364 temp = ready[pos1];
13365 ready[pos1] = ready[pos2];
13366 ready[pos2] = temp;
13370 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
13371 that may clobber hi or lo. */
13372 static rtx mips_macc_chains_last_hilo;
13374 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
13375 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
13378 mips_macc_chains_record (rtx insn)
13380 if (get_attr_may_clobber_hilo (insn))
13381 mips_macc_chains_last_hilo = insn;
13384 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
13385 has NREADY elements, looking for a multiply-add or multiply-subtract
13386 instruction that is cumulative with mips_macc_chains_last_hilo.
13387 If there is one, promote it ahead of anything else that might
13388 clobber hi or lo. */
13391 mips_macc_chains_reorder (rtx *ready, int nready)
13395 if (mips_macc_chains_last_hilo != 0)
13396 for (i = nready - 1; i >= 0; i--)
13397 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
13399 for (j = nready - 1; j > i; j--)
13400 if (recog_memoized (ready[j]) >= 0
13401 && get_attr_may_clobber_hilo (ready[j]))
13403 mips_promote_ready (ready, i, j);
13410 /* The last instruction to be scheduled. */
13411 static rtx vr4130_last_insn;
13413 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
13414 points to an rtx that is initially an instruction. Nullify the rtx
13415 if the instruction uses the value of register X. */
13418 vr4130_true_reg_dependence_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
13423 insn_ptr = (rtx *) data;
13426 && reg_referenced_p (x, PATTERN (*insn_ptr)))
13430 /* Return true if there is true register dependence between vr4130_last_insn
13434 vr4130_true_reg_dependence_p (rtx insn)
13436 note_stores (PATTERN (vr4130_last_insn),
13437 vr4130_true_reg_dependence_p_1, &insn);
13441 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
13442 the ready queue and that INSN2 is the instruction after it, return
13443 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
13444 in which INSN1 and INSN2 can probably issue in parallel, but for
13445 which (INSN2, INSN1) should be less sensitive to instruction
13446 alignment than (INSN1, INSN2). See 4130.md for more details. */
13449 vr4130_swap_insns_p (rtx insn1, rtx insn2)
13451 sd_iterator_def sd_it;
13454 /* Check for the following case:
13456 1) there is some other instruction X with an anti dependence on INSN1;
13457 2) X has a higher priority than INSN2; and
13458 3) X is an arithmetic instruction (and thus has no unit restrictions).
13460 If INSN1 is the last instruction blocking X, it would better to
13461 choose (INSN1, X) over (INSN2, INSN1). */
13462 FOR_EACH_DEP (insn1, SD_LIST_FORW, sd_it, dep)
13463 if (DEP_TYPE (dep) == REG_DEP_ANTI
13464 && INSN_PRIORITY (DEP_CON (dep)) > INSN_PRIORITY (insn2)
13465 && recog_memoized (DEP_CON (dep)) >= 0
13466 && get_attr_vr4130_class (DEP_CON (dep)) == VR4130_CLASS_ALU)
13469 if (vr4130_last_insn != 0
13470 && recog_memoized (insn1) >= 0
13471 && recog_memoized (insn2) >= 0)
13473 /* See whether INSN1 and INSN2 use different execution units,
13474 or if they are both ALU-type instructions. If so, they can
13475 probably execute in parallel. */
13476 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
13477 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
13478 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
13480 /* If only one of the instructions has a dependence on
13481 vr4130_last_insn, prefer to schedule the other one first. */
13482 bool dep1_p = vr4130_true_reg_dependence_p (insn1);
13483 bool dep2_p = vr4130_true_reg_dependence_p (insn2);
13484 if (dep1_p != dep2_p)
13487 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
13488 is not an ALU-type instruction and if INSN1 uses the same
13489 execution unit. (Note that if this condition holds, we already
13490 know that INSN2 uses a different execution unit.) */
13491 if (class1 != VR4130_CLASS_ALU
13492 && recog_memoized (vr4130_last_insn) >= 0
13493 && class1 == get_attr_vr4130_class (vr4130_last_insn))
13500 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
13501 queue with at least two instructions. Swap the first two if
13502 vr4130_swap_insns_p says that it could be worthwhile. */
13505 vr4130_reorder (rtx *ready, int nready)
13507 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
13508 mips_promote_ready (ready, nready - 2, nready - 1);
13511 /* Record whether last 74k AGEN instruction was a load or store. */
13512 static enum attr_type mips_last_74k_agen_insn = TYPE_UNKNOWN;
13514 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
13515 resets to TYPE_UNKNOWN state. */
13518 mips_74k_agen_init (rtx insn)
13520 if (!insn || CALL_P (insn) || JUMP_P (insn))
13521 mips_last_74k_agen_insn = TYPE_UNKNOWN;
13524 enum attr_type type = get_attr_type (insn);
13525 if (type == TYPE_LOAD || type == TYPE_STORE)
13526 mips_last_74k_agen_insn = type;
13530 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
13531 loads to be grouped together, and multiple stores to be grouped
13532 together. Swap things around in the ready queue to make this happen. */
13535 mips_74k_agen_reorder (rtx *ready, int nready)
13538 int store_pos, load_pos;
13543 for (i = nready - 1; i >= 0; i--)
13545 rtx insn = ready[i];
13546 if (USEFUL_INSN_P (insn))
13547 switch (get_attr_type (insn))
13550 if (store_pos == -1)
13555 if (load_pos == -1)
13564 if (load_pos == -1 || store_pos == -1)
13567 switch (mips_last_74k_agen_insn)
13570 /* Prefer to schedule loads since they have a higher latency. */
13572 /* Swap loads to the front of the queue. */
13573 mips_maybe_swap_ready (ready, load_pos, store_pos, 4);
13576 /* Swap stores to the front of the queue. */
13577 mips_maybe_swap_ready (ready, store_pos, load_pos, 4);
13584 /* Implement TARGET_SCHED_INIT. */
13587 mips_sched_init (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13588 int max_ready ATTRIBUTE_UNUSED)
13590 mips_macc_chains_last_hilo = 0;
13591 vr4130_last_insn = 0;
13592 mips_74k_agen_init (NULL_RTX);
13594 /* When scheduling for Loongson2, branch instructions go to ALU1,
13595 therefore basic block is most likely to start with round-robin counter
13596 pointed to ALU2. */
13597 mips_ls2.alu1_turn_p = false;
13598 mips_ls2.falu1_turn_p = true;
13601 /* Subroutine used by TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
13604 mips_sched_reorder_1 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13605 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
13607 if (!reload_completed
13608 && TUNE_MACC_CHAINS
13610 mips_macc_chains_reorder (ready, *nreadyp);
13612 if (reload_completed
13614 && !TARGET_VR4130_ALIGN
13616 vr4130_reorder (ready, *nreadyp);
13619 mips_74k_agen_reorder (ready, *nreadyp);
13622 /* Implement TARGET_SCHED_REORDER. */
13625 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13626 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
13628 mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle);
13629 return mips_issue_rate ();
13632 /* Implement TARGET_SCHED_REORDER2. */
13635 mips_sched_reorder2 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13636 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
13638 mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle);
13639 return cached_can_issue_more;
13642 /* Update round-robin counters for ALU1/2 and FALU1/2. */
13645 mips_ls2_variable_issue (rtx insn)
13647 if (mips_ls2.alu1_turn_p)
13649 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu1_core_unit_code))
13650 mips_ls2.alu1_turn_p = false;
13654 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu2_core_unit_code))
13655 mips_ls2.alu1_turn_p = true;
13658 if (mips_ls2.falu1_turn_p)
13660 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu1_core_unit_code))
13661 mips_ls2.falu1_turn_p = false;
13665 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu2_core_unit_code))
13666 mips_ls2.falu1_turn_p = true;
13669 if (recog_memoized (insn) >= 0)
13670 mips_ls2.cycle_has_multi_p |= (get_attr_type (insn) == TYPE_MULTI);
13673 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
13676 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13677 rtx insn, int more)
13679 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
13680 if (USEFUL_INSN_P (insn))
13682 if (get_attr_type (insn) != TYPE_GHOST)
13684 if (!reload_completed && TUNE_MACC_CHAINS)
13685 mips_macc_chains_record (insn);
13686 vr4130_last_insn = insn;
13688 mips_74k_agen_init (insn);
13689 else if (TUNE_LOONGSON_2EF)
13690 mips_ls2_variable_issue (insn);
13693 /* Instructions of type 'multi' should all be split before
13694 the second scheduling pass. */
13695 gcc_assert (!reload_completed
13696 || recog_memoized (insn) < 0
13697 || get_attr_type (insn) != TYPE_MULTI);
13699 cached_can_issue_more = more;
13703 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
13704 return the first operand of the associated PREF or PREFX insn. */
13707 mips_prefetch_cookie (rtx write, rtx locality)
13709 /* store_streamed / load_streamed. */
13710 if (INTVAL (locality) <= 0)
13711 return GEN_INT (INTVAL (write) + 4);
13713 /* store / load. */
13714 if (INTVAL (locality) <= 2)
13717 /* store_retained / load_retained. */
13718 return GEN_INT (INTVAL (write) + 6);
13721 /* Flags that indicate when a built-in function is available.
13723 BUILTIN_AVAIL_NON_MIPS16
13724 The function is available on the current target if !TARGET_MIPS16.
13726 BUILTIN_AVAIL_MIPS16
13727 The function is available on the current target if TARGET_MIPS16. */
13728 #define BUILTIN_AVAIL_NON_MIPS16 1
13729 #define BUILTIN_AVAIL_MIPS16 2
13731 /* Declare an availability predicate for built-in functions that
13732 require non-MIPS16 mode and also require COND to be true.
13733 NAME is the main part of the predicate's name. */
13734 #define AVAIL_NON_MIPS16(NAME, COND) \
13735 static unsigned int \
13736 mips_builtin_avail_##NAME (void) \
13738 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
13741 /* Declare an availability predicate for built-in functions that
13742 support both MIPS16 and non-MIPS16 code and also require COND
13743 to be true. NAME is the main part of the predicate's name. */
13744 #define AVAIL_ALL(NAME, COND) \
13745 static unsigned int \
13746 mips_builtin_avail_##NAME (void) \
13748 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 | BUILTIN_AVAIL_MIPS16 : 0; \
13751 /* This structure describes a single built-in function. */
13752 struct mips_builtin_description {
13753 /* The code of the main .md file instruction. See mips_builtin_type
13754 for more information. */
13755 enum insn_code icode;
13757 /* The floating-point comparison code to use with ICODE, if any. */
13758 enum mips_fp_condition cond;
13760 /* The name of the built-in function. */
13763 /* Specifies how the function should be expanded. */
13764 enum mips_builtin_type builtin_type;
13766 /* The function's prototype. */
13767 enum mips_function_type function_type;
13769 /* Whether the function is available. */
13770 unsigned int (*avail) (void);
13773 AVAIL_ALL (hard_float, TARGET_HARD_FLOAT_ABI)
13774 AVAIL_NON_MIPS16 (paired_single, TARGET_PAIRED_SINGLE_FLOAT)
13775 AVAIL_NON_MIPS16 (sb1_paired_single, TARGET_SB1 && TARGET_PAIRED_SINGLE_FLOAT)
13776 AVAIL_NON_MIPS16 (mips3d, TARGET_MIPS3D)
13777 AVAIL_NON_MIPS16 (dsp, TARGET_DSP)
13778 AVAIL_NON_MIPS16 (dspr2, TARGET_DSPR2)
13779 AVAIL_NON_MIPS16 (dsp_32, !TARGET_64BIT && TARGET_DSP)
13780 AVAIL_NON_MIPS16 (dsp_64, TARGET_64BIT && TARGET_DSP)
13781 AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2)
13782 AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS)
13783 AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
13785 /* Construct a mips_builtin_description from the given arguments.
13787 INSN is the name of the associated instruction pattern, without the
13788 leading CODE_FOR_mips_.
13790 CODE is the floating-point condition code associated with the
13791 function. It can be 'f' if the field is not applicable.
13793 NAME is the name of the function itself, without the leading
13796 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
13798 AVAIL is the name of the availability predicate, without the leading
13799 mips_builtin_avail_. */
13800 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
13801 FUNCTION_TYPE, AVAIL) \
13802 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
13803 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
13804 mips_builtin_avail_ ## AVAIL }
13806 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
13807 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
13808 are as for MIPS_BUILTIN. */
13809 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
13810 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
13812 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
13813 are subject to mips_builtin_avail_<AVAIL>. */
13814 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
13815 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
13816 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
13817 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
13818 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
13820 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
13821 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
13822 while the any and all forms are subject to mips_builtin_avail_mips3d. */
13823 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
13824 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
13825 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
13827 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
13828 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
13830 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
13831 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
13833 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
13834 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
13837 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
13838 are subject to mips_builtin_avail_mips3d. */
13839 #define CMP_4S_BUILTINS(INSN, COND) \
13840 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
13841 MIPS_BUILTIN_CMP_ANY, \
13842 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
13843 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
13844 MIPS_BUILTIN_CMP_ALL, \
13845 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
13847 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
13848 instruction requires mips_builtin_avail_<AVAIL>. */
13849 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
13850 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
13851 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
13853 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
13854 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
13857 /* Define all the built-in functions related to C.cond.fmt condition COND. */
13858 #define CMP_BUILTINS(COND) \
13859 MOVTF_BUILTINS (c, COND, paired_single), \
13860 MOVTF_BUILTINS (cabs, COND, mips3d), \
13861 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
13862 CMP_PS_BUILTINS (c, COND, paired_single), \
13863 CMP_PS_BUILTINS (cabs, COND, mips3d), \
13864 CMP_4S_BUILTINS (c, COND), \
13865 CMP_4S_BUILTINS (cabs, COND)
13867 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
13868 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
13869 and AVAIL are as for MIPS_BUILTIN. */
13870 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
13871 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
13872 FUNCTION_TYPE, AVAIL)
13874 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
13875 branch instruction. AVAIL is as for MIPS_BUILTIN. */
13876 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
13877 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
13878 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
13880 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
13881 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
13882 builtin_description field. */
13883 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
13884 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
13885 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
13886 FUNCTION_TYPE, mips_builtin_avail_loongson }
13888 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
13889 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
13890 builtin_description field. */
13891 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
13892 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
13894 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
13895 We use functions of this form when the same insn can be usefully applied
13896 to more than one datatype. */
13897 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
13898 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
13900 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
13901 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
13902 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
13903 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
13904 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
13905 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
13906 #define CODE_FOR_mips_mult CODE_FOR_mulsidi3_32bit
13907 #define CODE_FOR_mips_multu CODE_FOR_umulsidi3_32bit
13909 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
13910 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
13911 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
13912 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
13913 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
13914 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
13915 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
13916 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
13917 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
13918 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
13919 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
13920 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
13921 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
13922 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
13923 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
13924 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
13925 #define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3
13926 #define CODE_FOR_loongson_psllh CODE_FOR_ashlv4hi3
13927 #define CODE_FOR_loongson_psllw CODE_FOR_ashlv2si3
13928 #define CODE_FOR_loongson_psrlh CODE_FOR_lshrv4hi3
13929 #define CODE_FOR_loongson_psrlw CODE_FOR_lshrv2si3
13930 #define CODE_FOR_loongson_psrah CODE_FOR_ashrv4hi3
13931 #define CODE_FOR_loongson_psraw CODE_FOR_ashrv2si3
13932 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
13933 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
13934 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
13935 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
13936 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
13937 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
13938 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
13940 static const struct mips_builtin_description mips_builtins[] = {
13941 #define MIPS_GET_FCSR 0
13942 DIRECT_BUILTIN (get_fcsr, MIPS_USI_FTYPE_VOID, hard_float),
13943 #define MIPS_SET_FCSR 1
13944 DIRECT_NO_TARGET_BUILTIN (set_fcsr, MIPS_VOID_FTYPE_USI, hard_float),
13946 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13947 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13948 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13949 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13950 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, paired_single),
13951 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, paired_single),
13952 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, paired_single),
13953 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, paired_single),
13955 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT, paired_single),
13956 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13957 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13958 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
13959 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, mips3d),
13961 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, mips3d),
13962 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, mips3d),
13963 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
13964 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
13965 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
13966 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13968 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, mips3d),
13969 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, mips3d),
13970 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
13971 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
13972 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
13973 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13975 MIPS_FP_CONDITIONS (CMP_BUILTINS),
13977 /* Built-in functions for the SB-1 processor. */
13978 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, sb1_paired_single),
13980 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
13981 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13982 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13983 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
13984 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13985 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13986 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13987 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13988 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
13989 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13990 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13991 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, dsp),
13992 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, dsp),
13993 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, dsp),
13994 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, dsp),
13995 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, dsp),
13996 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, dsp),
13997 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
13998 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
13999 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
14000 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
14001 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, dsp),
14002 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, dsp),
14003 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
14004 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
14005 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
14006 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
14007 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
14008 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
14009 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
14010 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
14011 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
14012 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
14013 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
14014 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
14015 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
14016 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
14017 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
14018 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, dsp),
14019 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
14020 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
14021 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
14022 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
14023 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
14024 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, dsp),
14025 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, dsp),
14026 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, dsp),
14027 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, dsp),
14028 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
14029 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
14030 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
14031 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
14032 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
14033 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
14034 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
14035 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
14036 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
14037 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
14038 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
14039 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
14040 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, dsp),
14041 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, dsp),
14042 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_POINTER_SI, dsp),
14043 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_POINTER_SI, dsp),
14044 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_POINTER_SI, dsp),
14045 BPOSGE_BUILTIN (32, dsp),
14047 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
14048 DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, dspr2),
14049 DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14050 DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14051 DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
14052 DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
14053 DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
14054 DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
14055 DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
14056 DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
14057 DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
14058 DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14059 DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14060 DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, dspr2),
14061 DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14062 DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, dspr2),
14063 DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dspr2),
14064 DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
14065 DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
14066 DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
14067 DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
14068 DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
14069 DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, dspr2),
14070 DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14071 DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14072 DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
14073 DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
14074 DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14075 DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14076 DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
14077 DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
14078 DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14079 DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14080 DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
14081 DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
14083 /* Built-in functions for the DSP ASE (32-bit only). */
14084 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
14085 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
14086 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
14087 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
14088 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
14089 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
14090 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
14091 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
14092 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
14093 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
14094 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
14095 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
14096 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
14097 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
14098 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
14099 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
14100 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, dsp_32),
14101 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, dsp_32),
14102 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, dsp_32),
14103 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, dsp_32),
14104 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, dsp_32),
14105 DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
14106 DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32),
14107 DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
14108 DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32),
14109 DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, dsp_32),
14110 DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, dsp_32),
14112 /* Built-in functions for the DSP ASE (64-bit only). */
14113 DIRECT_BUILTIN (ldx, MIPS_DI_FTYPE_POINTER_SI, dsp_64),
14115 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
14116 DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14117 DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14118 DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14119 DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14120 DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14121 DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14122 DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14123 DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14124 DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14126 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
14127 LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI),
14128 LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI),
14129 LOONGSON_BUILTIN (packushb, MIPS_UV8QI_FTYPE_UV4HI_UV4HI),
14130 LOONGSON_BUILTIN_SUFFIX (paddw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14131 LOONGSON_BUILTIN_SUFFIX (paddh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14132 LOONGSON_BUILTIN_SUFFIX (paddb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14133 LOONGSON_BUILTIN_SUFFIX (paddw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14134 LOONGSON_BUILTIN_SUFFIX (paddh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14135 LOONGSON_BUILTIN_SUFFIX (paddb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14136 LOONGSON_BUILTIN_SUFFIX (paddd, u, MIPS_UDI_FTYPE_UDI_UDI),
14137 LOONGSON_BUILTIN_SUFFIX (paddd, s, MIPS_DI_FTYPE_DI_DI),
14138 LOONGSON_BUILTIN (paddsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14139 LOONGSON_BUILTIN (paddsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
14140 LOONGSON_BUILTIN (paddush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14141 LOONGSON_BUILTIN (paddusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14142 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_ud, MIPS_UDI_FTYPE_UDI_UDI),
14143 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_uw, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14144 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_uh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14145 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_ub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14146 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_sd, MIPS_DI_FTYPE_DI_DI),
14147 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_sw, MIPS_V2SI_FTYPE_V2SI_V2SI),
14148 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_sh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14149 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_sb, MIPS_V8QI_FTYPE_V8QI_V8QI),
14150 LOONGSON_BUILTIN (pavgh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14151 LOONGSON_BUILTIN (pavgb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14152 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14153 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14154 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14155 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14156 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14157 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14158 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14159 LOONGSON_BUILTIN_SUFFIX (pcmpgth, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14160 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14161 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14162 LOONGSON_BUILTIN_SUFFIX (pcmpgth, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14163 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14164 LOONGSON_BUILTIN_SUFFIX (pextrh, u, MIPS_UV4HI_FTYPE_UV4HI_USI),
14165 LOONGSON_BUILTIN_SUFFIX (pextrh, s, MIPS_V4HI_FTYPE_V4HI_USI),
14166 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14167 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14168 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14169 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14170 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14171 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14172 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14173 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14174 LOONGSON_BUILTIN (pmaddhw, MIPS_V2SI_FTYPE_V4HI_V4HI),
14175 LOONGSON_BUILTIN (pmaxsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14176 LOONGSON_BUILTIN (pmaxub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14177 LOONGSON_BUILTIN (pminsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14178 LOONGSON_BUILTIN (pminub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14179 LOONGSON_BUILTIN_SUFFIX (pmovmskb, u, MIPS_UV8QI_FTYPE_UV8QI),
14180 LOONGSON_BUILTIN_SUFFIX (pmovmskb, s, MIPS_V8QI_FTYPE_V8QI),
14181 LOONGSON_BUILTIN (pmulhuh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14182 LOONGSON_BUILTIN (pmulhh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14183 LOONGSON_BUILTIN (pmullh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14184 LOONGSON_BUILTIN (pmuluw, MIPS_UDI_FTYPE_UV2SI_UV2SI),
14185 LOONGSON_BUILTIN (pasubub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14186 LOONGSON_BUILTIN (biadd, MIPS_UV4HI_FTYPE_UV8QI),
14187 LOONGSON_BUILTIN (psadbh, MIPS_UV4HI_FTYPE_UV8QI_UV8QI),
14188 LOONGSON_BUILTIN_SUFFIX (pshufh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
14189 LOONGSON_BUILTIN_SUFFIX (pshufh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
14190 LOONGSON_BUILTIN_SUFFIX (psllh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
14191 LOONGSON_BUILTIN_SUFFIX (psllh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
14192 LOONGSON_BUILTIN_SUFFIX (psllw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
14193 LOONGSON_BUILTIN_SUFFIX (psllw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
14194 LOONGSON_BUILTIN_SUFFIX (psrah, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
14195 LOONGSON_BUILTIN_SUFFIX (psrah, s, MIPS_V4HI_FTYPE_V4HI_UQI),
14196 LOONGSON_BUILTIN_SUFFIX (psraw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
14197 LOONGSON_BUILTIN_SUFFIX (psraw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
14198 LOONGSON_BUILTIN_SUFFIX (psrlh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
14199 LOONGSON_BUILTIN_SUFFIX (psrlh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
14200 LOONGSON_BUILTIN_SUFFIX (psrlw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
14201 LOONGSON_BUILTIN_SUFFIX (psrlw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
14202 LOONGSON_BUILTIN_SUFFIX (psubw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14203 LOONGSON_BUILTIN_SUFFIX (psubh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14204 LOONGSON_BUILTIN_SUFFIX (psubb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14205 LOONGSON_BUILTIN_SUFFIX (psubw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14206 LOONGSON_BUILTIN_SUFFIX (psubh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14207 LOONGSON_BUILTIN_SUFFIX (psubb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14208 LOONGSON_BUILTIN_SUFFIX (psubd, u, MIPS_UDI_FTYPE_UDI_UDI),
14209 LOONGSON_BUILTIN_SUFFIX (psubd, s, MIPS_DI_FTYPE_DI_DI),
14210 LOONGSON_BUILTIN (psubsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14211 LOONGSON_BUILTIN (psubsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
14212 LOONGSON_BUILTIN (psubush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14213 LOONGSON_BUILTIN (psubusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14214 LOONGSON_BUILTIN_SUFFIX (punpckhbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14215 LOONGSON_BUILTIN_SUFFIX (punpckhhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14216 LOONGSON_BUILTIN_SUFFIX (punpckhwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14217 LOONGSON_BUILTIN_SUFFIX (punpckhbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14218 LOONGSON_BUILTIN_SUFFIX (punpckhhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14219 LOONGSON_BUILTIN_SUFFIX (punpckhwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14220 LOONGSON_BUILTIN_SUFFIX (punpcklbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14221 LOONGSON_BUILTIN_SUFFIX (punpcklhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14222 LOONGSON_BUILTIN_SUFFIX (punpcklwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14223 LOONGSON_BUILTIN_SUFFIX (punpcklbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14224 LOONGSON_BUILTIN_SUFFIX (punpcklhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14225 LOONGSON_BUILTIN_SUFFIX (punpcklwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14227 /* Sundry other built-in functions. */
14228 DIRECT_NO_TARGET_BUILTIN (cache, MIPS_VOID_FTYPE_SI_CVPOINTER, cache)
14231 /* Index I is the function declaration for mips_builtins[I], or null if the
14232 function isn't defined on this target. */
14233 static GTY(()) tree mips_builtin_decls[ARRAY_SIZE (mips_builtins)];
14235 /* MODE is a vector mode whose elements have type TYPE. Return the type
14236 of the vector itself. */
14239 mips_builtin_vector_type (tree type, enum machine_mode mode)
14241 static tree types[2 * (int) MAX_MACHINE_MODE];
14244 mode_index = (int) mode;
14246 if (TREE_CODE (type) == INTEGER_TYPE && TYPE_UNSIGNED (type))
14247 mode_index += MAX_MACHINE_MODE;
14249 if (types[mode_index] == NULL_TREE)
14250 types[mode_index] = build_vector_type_for_mode (type, mode);
14251 return types[mode_index];
14254 /* Return a type for 'const volatile void *'. */
14257 mips_build_cvpointer_type (void)
14261 if (cache == NULL_TREE)
14262 cache = build_pointer_type (build_qualified_type
14264 TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE));
14268 /* Source-level argument types. */
14269 #define MIPS_ATYPE_VOID void_type_node
14270 #define MIPS_ATYPE_INT integer_type_node
14271 #define MIPS_ATYPE_POINTER ptr_type_node
14272 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
14274 /* Standard mode-based argument types. */
14275 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
14276 #define MIPS_ATYPE_SI intSI_type_node
14277 #define MIPS_ATYPE_USI unsigned_intSI_type_node
14278 #define MIPS_ATYPE_DI intDI_type_node
14279 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
14280 #define MIPS_ATYPE_SF float_type_node
14281 #define MIPS_ATYPE_DF double_type_node
14283 /* Vector argument types. */
14284 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
14285 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
14286 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
14287 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
14288 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
14289 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
14290 #define MIPS_ATYPE_UV2SI \
14291 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
14292 #define MIPS_ATYPE_UV4HI \
14293 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
14294 #define MIPS_ATYPE_UV8QI \
14295 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
14297 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
14298 their associated MIPS_ATYPEs. */
14299 #define MIPS_FTYPE_ATYPES1(A, B) \
14300 MIPS_ATYPE_##A, MIPS_ATYPE_##B
14302 #define MIPS_FTYPE_ATYPES2(A, B, C) \
14303 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
14305 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
14306 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
14308 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
14309 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
14312 /* Return the function type associated with function prototype TYPE. */
14315 mips_build_function_type (enum mips_function_type type)
14317 static tree types[(int) MIPS_MAX_FTYPE_MAX];
14319 if (types[(int) type] == NULL_TREE)
14322 #define DEF_MIPS_FTYPE(NUM, ARGS) \
14323 case MIPS_FTYPE_NAME##NUM ARGS: \
14324 types[(int) type] \
14325 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
14328 #include "config/mips/mips-ftypes.def"
14329 #undef DEF_MIPS_FTYPE
14331 gcc_unreachable ();
14334 return types[(int) type];
14337 /* Implement TARGET_INIT_BUILTINS. */
14340 mips_init_builtins (void)
14342 const struct mips_builtin_description *d;
14345 /* Iterate through all of the bdesc arrays, initializing all of the
14346 builtin functions. */
14347 for (i = 0; i < ARRAY_SIZE (mips_builtins); i++)
14349 d = &mips_builtins[i];
14351 mips_builtin_decls[i]
14352 = add_builtin_function (d->name,
14353 mips_build_function_type (d->function_type),
14354 i, BUILT_IN_MD, NULL, NULL);
14358 /* Implement TARGET_BUILTIN_DECL. */
14361 mips_builtin_decl (unsigned int code, bool initialize_p ATTRIBUTE_UNUSED)
14363 if (code >= ARRAY_SIZE (mips_builtins))
14364 return error_mark_node;
14365 return mips_builtin_decls[code];
14368 /* Take argument ARGNO from EXP's argument list and convert it into
14369 an expand operand. Store the operand in *OP. */
14372 mips_prepare_builtin_arg (struct expand_operand *op, tree exp,
14373 unsigned int argno)
14378 arg = CALL_EXPR_ARG (exp, argno);
14379 value = expand_normal (arg);
14380 create_input_operand (op, value, TYPE_MODE (TREE_TYPE (arg)));
14383 /* Expand instruction ICODE as part of a built-in function sequence.
14384 Use the first NOPS elements of OPS as the instruction's operands.
14385 HAS_TARGET_P is true if operand 0 is a target; it is false if the
14386 instruction has no target.
14388 Return the target rtx if HAS_TARGET_P, otherwise return const0_rtx. */
14391 mips_expand_builtin_insn (enum insn_code icode, unsigned int nops,
14392 struct expand_operand *ops, bool has_target_p)
14394 if (!maybe_expand_insn (icode, nops, ops))
14396 error ("invalid argument to built-in function");
14397 return has_target_p ? gen_reg_rtx (ops[0].mode) : const0_rtx;
14399 return has_target_p ? ops[0].value : const0_rtx;
14402 /* Expand a floating-point comparison for built-in function call EXP.
14403 The first NARGS arguments are the values to be compared. ICODE is
14404 the .md pattern that does the comparison and COND is the condition
14405 that is being tested. Return an rtx for the result. */
14408 mips_expand_builtin_compare_1 (enum insn_code icode,
14409 enum mips_fp_condition cond,
14410 tree exp, int nargs)
14412 struct expand_operand ops[MAX_RECOG_OPERANDS];
14416 /* The instruction should have a target operand, an operand for each
14417 argument, and an operand for COND. */
14418 gcc_assert (nargs + 2 == insn_data[(int) icode].n_generator_args);
14420 output = mips_allocate_fcc (insn_data[(int) icode].operand[0].mode);
14422 create_fixed_operand (&ops[opno++], output);
14423 for (argno = 0; argno < nargs; argno++)
14424 mips_prepare_builtin_arg (&ops[opno++], exp, argno);
14425 create_integer_operand (&ops[opno++], (int) cond);
14426 return mips_expand_builtin_insn (icode, opno, ops, true);
14429 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
14430 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
14431 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
14432 suggests a good place to put the result. */
14435 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
14438 struct expand_operand ops[MAX_RECOG_OPERANDS];
14441 /* Map any target to operand 0. */
14444 create_output_operand (&ops[opno++], target, TYPE_MODE (TREE_TYPE (exp)));
14446 /* Map the arguments to the other operands. */
14447 gcc_assert (opno + call_expr_nargs (exp)
14448 == insn_data[icode].n_generator_args);
14449 for (argno = 0; argno < call_expr_nargs (exp); argno++)
14450 mips_prepare_builtin_arg (&ops[opno++], exp, argno);
14452 return mips_expand_builtin_insn (icode, opno, ops, has_target_p);
14455 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
14456 function; TYPE says which. EXP is the CALL_EXPR that calls the
14457 function, ICODE is the instruction that should be used to compare
14458 the first two arguments, and COND is the condition it should test.
14459 TARGET, if nonnull, suggests a good place to put the result. */
14462 mips_expand_builtin_movtf (enum mips_builtin_type type,
14463 enum insn_code icode, enum mips_fp_condition cond,
14464 rtx target, tree exp)
14466 struct expand_operand ops[4];
14469 cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp, 2);
14470 create_output_operand (&ops[0], target, TYPE_MODE (TREE_TYPE (exp)));
14471 if (type == MIPS_BUILTIN_MOVT)
14473 mips_prepare_builtin_arg (&ops[2], exp, 2);
14474 mips_prepare_builtin_arg (&ops[1], exp, 3);
14478 mips_prepare_builtin_arg (&ops[1], exp, 2);
14479 mips_prepare_builtin_arg (&ops[2], exp, 3);
14481 create_fixed_operand (&ops[3], cmp_result);
14482 return mips_expand_builtin_insn (CODE_FOR_mips_cond_move_tf_ps,
14486 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
14487 into TARGET otherwise. Return TARGET. */
14490 mips_builtin_branch_and_move (rtx condition, rtx target,
14491 rtx value_if_true, rtx value_if_false)
14493 rtx true_label, done_label;
14495 true_label = gen_label_rtx ();
14496 done_label = gen_label_rtx ();
14498 /* First assume that CONDITION is false. */
14499 mips_emit_move (target, value_if_false);
14501 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
14502 emit_jump_insn (gen_condjump (condition, true_label));
14503 emit_jump_insn (gen_jump (done_label));
14506 /* Fix TARGET if CONDITION is true. */
14507 emit_label (true_label);
14508 mips_emit_move (target, value_if_true);
14510 emit_label (done_label);
14514 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
14515 the CALL_EXPR that calls the function, ICODE is the code of the
14516 comparison instruction, and COND is the condition it should test.
14517 TARGET, if nonnull, suggests a good place to put the boolean result. */
14520 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
14521 enum insn_code icode, enum mips_fp_condition cond,
14522 rtx target, tree exp)
14524 rtx offset, condition, cmp_result;
14526 if (target == 0 || GET_MODE (target) != SImode)
14527 target = gen_reg_rtx (SImode);
14528 cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp,
14529 call_expr_nargs (exp));
14531 /* If the comparison sets more than one register, we define the result
14532 to be 0 if all registers are false and -1 if all registers are true.
14533 The value of the complete result is indeterminate otherwise. */
14534 switch (builtin_type)
14536 case MIPS_BUILTIN_CMP_ALL:
14537 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
14538 return mips_builtin_branch_and_move (condition, target,
14539 const0_rtx, const1_rtx);
14541 case MIPS_BUILTIN_CMP_UPPER:
14542 case MIPS_BUILTIN_CMP_LOWER:
14543 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
14544 condition = gen_single_cc (cmp_result, offset);
14545 return mips_builtin_branch_and_move (condition, target,
14546 const1_rtx, const0_rtx);
14549 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
14550 return mips_builtin_branch_and_move (condition, target,
14551 const1_rtx, const0_rtx);
14555 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
14556 if nonnull, suggests a good place to put the boolean result. */
14559 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
14561 rtx condition, cmp_result;
14564 if (target == 0 || GET_MODE (target) != SImode)
14565 target = gen_reg_rtx (SImode);
14567 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
14569 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
14574 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
14575 return mips_builtin_branch_and_move (condition, target,
14576 const1_rtx, const0_rtx);
14579 /* Implement TARGET_EXPAND_BUILTIN. */
14582 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
14583 enum machine_mode mode, int ignore)
14586 unsigned int fcode, avail;
14587 const struct mips_builtin_description *d;
14589 fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
14590 fcode = DECL_FUNCTION_CODE (fndecl);
14591 gcc_assert (fcode < ARRAY_SIZE (mips_builtins));
14592 d = &mips_builtins[fcode];
14593 avail = d->avail ();
14594 gcc_assert (avail != 0);
14595 if (TARGET_MIPS16 && !(avail & BUILTIN_AVAIL_MIPS16))
14597 error ("built-in function %qE not supported for MIPS16",
14598 DECL_NAME (fndecl));
14599 return ignore ? const0_rtx : CONST0_RTX (mode);
14601 switch (d->builtin_type)
14603 case MIPS_BUILTIN_DIRECT:
14604 return mips_expand_builtin_direct (d->icode, target, exp, true);
14606 case MIPS_BUILTIN_DIRECT_NO_TARGET:
14607 return mips_expand_builtin_direct (d->icode, target, exp, false);
14609 case MIPS_BUILTIN_MOVT:
14610 case MIPS_BUILTIN_MOVF:
14611 return mips_expand_builtin_movtf (d->builtin_type, d->icode,
14612 d->cond, target, exp);
14614 case MIPS_BUILTIN_CMP_ANY:
14615 case MIPS_BUILTIN_CMP_ALL:
14616 case MIPS_BUILTIN_CMP_UPPER:
14617 case MIPS_BUILTIN_CMP_LOWER:
14618 case MIPS_BUILTIN_CMP_SINGLE:
14619 return mips_expand_builtin_compare (d->builtin_type, d->icode,
14620 d->cond, target, exp);
14622 case MIPS_BUILTIN_BPOSGE32:
14623 return mips_expand_builtin_bposge (d->builtin_type, target);
14625 gcc_unreachable ();
14628 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
14629 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
14630 struct mips16_constant {
14631 struct mips16_constant *next;
14634 enum machine_mode mode;
14637 /* Information about an incomplete MIPS16 constant pool. FIRST is the
14638 first constant, HIGHEST_ADDRESS is the highest address that the first
14639 byte of the pool can have, and INSN_ADDRESS is the current instruction
14641 struct mips16_constant_pool {
14642 struct mips16_constant *first;
14643 int highest_address;
14647 /* Add constant VALUE to POOL and return its label. MODE is the
14648 value's mode (used for CONST_INTs, etc.). */
14651 mips16_add_constant (struct mips16_constant_pool *pool,
14652 rtx value, enum machine_mode mode)
14654 struct mips16_constant **p, *c;
14655 bool first_of_size_p;
14657 /* See whether the constant is already in the pool. If so, return the
14658 existing label, otherwise leave P pointing to the place where the
14659 constant should be added.
14661 Keep the pool sorted in increasing order of mode size so that we can
14662 reduce the number of alignments needed. */
14663 first_of_size_p = true;
14664 for (p = &pool->first; *p != 0; p = &(*p)->next)
14666 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
14667 return (*p)->label;
14668 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
14670 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
14671 first_of_size_p = false;
14674 /* In the worst case, the constant needed by the earliest instruction
14675 will end up at the end of the pool. The entire pool must then be
14676 accessible from that instruction.
14678 When adding the first constant, set the pool's highest address to
14679 the address of the first out-of-range byte. Adjust this address
14680 downwards each time a new constant is added. */
14681 if (pool->first == 0)
14682 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
14683 of the instruction with the lowest two bits clear. The base PC
14684 value for LDPC has the lowest three bits clear. Assume the worst
14685 case here; namely that the PC-relative instruction occupies the
14686 last 2 bytes in an aligned word. */
14687 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
14688 pool->highest_address -= GET_MODE_SIZE (mode);
14689 if (first_of_size_p)
14690 /* Take into account the worst possible padding due to alignment. */
14691 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
14693 /* Create a new entry. */
14694 c = XNEW (struct mips16_constant);
14697 c->label = gen_label_rtx ();
14704 /* Output constant VALUE after instruction INSN and return the last
14705 instruction emitted. MODE is the mode of the constant. */
14708 mips16_emit_constants_1 (enum machine_mode mode, rtx value, rtx insn)
14710 if (SCALAR_INT_MODE_P (mode) || ALL_SCALAR_FIXED_POINT_MODE_P (mode))
14712 rtx size = GEN_INT (GET_MODE_SIZE (mode));
14713 return emit_insn_after (gen_consttable_int (value, size), insn);
14716 if (SCALAR_FLOAT_MODE_P (mode))
14717 return emit_insn_after (gen_consttable_float (value), insn);
14719 if (VECTOR_MODE_P (mode))
14723 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
14724 insn = mips16_emit_constants_1 (GET_MODE_INNER (mode),
14725 CONST_VECTOR_ELT (value, i), insn);
14729 gcc_unreachable ();
14732 /* Dump out the constants in CONSTANTS after INSN. */
14735 mips16_emit_constants (struct mips16_constant *constants, rtx insn)
14737 struct mips16_constant *c, *next;
14741 for (c = constants; c != NULL; c = next)
14743 /* If necessary, increase the alignment of PC. */
14744 if (align < GET_MODE_SIZE (c->mode))
14746 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
14747 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
14749 align = GET_MODE_SIZE (c->mode);
14751 insn = emit_label_after (c->label, insn);
14752 insn = mips16_emit_constants_1 (c->mode, c->value, insn);
14758 emit_barrier_after (insn);
14761 /* Return the length of instruction INSN. */
14764 mips16_insn_length (rtx insn)
14766 if (JUMP_TABLE_DATA_P (insn))
14768 rtx body = PATTERN (insn);
14769 if (GET_CODE (body) == ADDR_VEC)
14770 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
14771 else if (GET_CODE (body) == ADDR_DIFF_VEC)
14772 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
14774 gcc_unreachable ();
14776 return get_attr_length (insn);
14779 /* If *X is a symbolic constant that refers to the constant pool, add
14780 the constant to POOL and rewrite *X to use the constant's label. */
14783 mips16_rewrite_pool_constant (struct mips16_constant_pool *pool, rtx *x)
14785 rtx base, offset, label;
14787 split_const (*x, &base, &offset);
14788 if (GET_CODE (base) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (base))
14790 label = mips16_add_constant (pool, copy_rtx (get_pool_constant (base)),
14791 get_pool_mode (base));
14792 base = gen_rtx_LABEL_REF (Pmode, label);
14793 *x = mips_unspec_address_offset (base, offset, SYMBOL_PC_RELATIVE);
14797 /* This structure is used to communicate with mips16_rewrite_pool_refs.
14798 INSN is the instruction we're rewriting and POOL points to the current
14800 struct mips16_rewrite_pool_refs_info {
14802 struct mips16_constant_pool *pool;
14805 /* Rewrite *X so that constant pool references refer to the constant's
14806 label instead. DATA points to a mips16_rewrite_pool_refs_info
14810 mips16_rewrite_pool_refs (rtx *x, void *data)
14812 struct mips16_rewrite_pool_refs_info *info =
14813 (struct mips16_rewrite_pool_refs_info *) data;
14815 if (force_to_mem_operand (*x, Pmode))
14817 rtx mem = force_const_mem (GET_MODE (*x), *x);
14818 validate_change (info->insn, x, mem, false);
14823 mips16_rewrite_pool_constant (info->pool, &XEXP (*x, 0));
14827 /* Don't rewrite the __mips16_rdwr symbol. */
14828 if (GET_CODE (*x) == UNSPEC && XINT (*x, 1) == UNSPEC_TLS_GET_TP)
14831 if (TARGET_MIPS16_TEXT_LOADS)
14832 mips16_rewrite_pool_constant (info->pool, x);
14834 return GET_CODE (*x) == CONST ? -1 : 0;
14837 /* Return whether CFG is used in mips_reorg. */
14840 mips_cfg_in_reorg (void)
14842 return (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
14843 || TARGET_RELAX_PIC_CALLS);
14846 /* Build MIPS16 constant pools. Split the instructions if SPLIT_P,
14847 otherwise assume that they are already split. */
14850 mips16_lay_out_constants (bool split_p)
14852 struct mips16_constant_pool pool;
14853 struct mips16_rewrite_pool_refs_info info;
14856 if (!TARGET_MIPS16_PCREL_LOADS)
14861 if (mips_cfg_in_reorg ())
14862 split_all_insns ();
14864 split_all_insns_noflow ();
14867 memset (&pool, 0, sizeof (pool));
14868 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
14870 /* Rewrite constant pool references in INSN. */
14871 if (USEFUL_INSN_P (insn))
14875 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &info);
14878 pool.insn_address += mips16_insn_length (insn);
14880 if (pool.first != NULL)
14882 /* If there are no natural barriers between the first user of
14883 the pool and the highest acceptable address, we'll need to
14884 create a new instruction to jump around the constant pool.
14885 In the worst case, this instruction will be 4 bytes long.
14887 If it's too late to do this transformation after INSN,
14888 do it immediately before INSN. */
14889 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
14893 label = gen_label_rtx ();
14895 jump = emit_jump_insn_before (gen_jump (label), insn);
14896 JUMP_LABEL (jump) = label;
14897 LABEL_NUSES (label) = 1;
14898 barrier = emit_barrier_after (jump);
14900 emit_label_after (label, barrier);
14901 pool.insn_address += 4;
14904 /* See whether the constant pool is now out of range of the first
14905 user. If so, output the constants after the previous barrier.
14906 Note that any instructions between BARRIER and INSN (inclusive)
14907 will use negative offsets to refer to the pool. */
14908 if (pool.insn_address > pool.highest_address)
14910 mips16_emit_constants (pool.first, barrier);
14914 else if (BARRIER_P (insn))
14918 mips16_emit_constants (pool.first, get_last_insn ());
14921 /* Return true if it is worth r10k_simplify_address's while replacing
14922 an address with X. We are looking for constants, and for addresses
14923 at a known offset from the incoming stack pointer. */
14926 r10k_simplified_address_p (rtx x)
14928 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
14930 return x == virtual_incoming_args_rtx || CONSTANT_P (x);
14933 /* X is an expression that appears in INSN. Try to use the UD chains
14934 to simplify it, returning the simplified form on success and the
14935 original form otherwise. Replace the incoming value of $sp with
14936 virtual_incoming_args_rtx (which should never occur in X otherwise). */
14939 r10k_simplify_address (rtx x, rtx insn)
14941 rtx newx, op0, op1, set, def_insn, note;
14943 struct df_link *defs;
14948 op0 = r10k_simplify_address (XEXP (x, 0), insn);
14949 if (op0 != XEXP (x, 0))
14950 newx = simplify_gen_unary (GET_CODE (x), GET_MODE (x),
14951 op0, GET_MODE (XEXP (x, 0)));
14953 else if (BINARY_P (x))
14955 op0 = r10k_simplify_address (XEXP (x, 0), insn);
14956 op1 = r10k_simplify_address (XEXP (x, 1), insn);
14957 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
14958 newx = simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
14960 else if (GET_CODE (x) == LO_SUM)
14962 /* LO_SUMs can be offset from HIGHs, if we know they won't
14963 overflow. See mips_classify_address for the rationale behind
14965 op0 = r10k_simplify_address (XEXP (x, 0), insn);
14966 if (GET_CODE (op0) == HIGH)
14967 newx = XEXP (x, 1);
14969 else if (REG_P (x))
14971 /* Uses are recorded by regno_reg_rtx, not X itself. */
14972 use = df_find_use (insn, regno_reg_rtx[REGNO (x)]);
14974 defs = DF_REF_CHAIN (use);
14976 /* Require a single definition. */
14977 if (defs && defs->next == NULL)
14980 if (DF_REF_IS_ARTIFICIAL (def))
14982 /* Replace the incoming value of $sp with
14983 virtual_incoming_args_rtx. */
14984 if (x == stack_pointer_rtx
14985 && DF_REF_BB (def) == ENTRY_BLOCK_PTR_FOR_FN (cfun))
14986 newx = virtual_incoming_args_rtx;
14988 else if (dominated_by_p (CDI_DOMINATORS, DF_REF_BB (use),
14991 /* Make sure that DEF_INSN is a single set of REG. */
14992 def_insn = DF_REF_INSN (def);
14993 if (NONJUMP_INSN_P (def_insn))
14995 set = single_set (def_insn);
14996 if (set && rtx_equal_p (SET_DEST (set), x))
14998 /* Prefer to use notes, since the def-use chains
14999 are often shorter. */
15000 note = find_reg_equal_equiv_note (def_insn);
15002 newx = XEXP (note, 0);
15004 newx = SET_SRC (set);
15005 newx = r10k_simplify_address (newx, def_insn);
15011 if (newx && r10k_simplified_address_p (newx))
15016 /* Return true if ADDRESS is known to be an uncached address
15017 on R10K systems. */
15020 r10k_uncached_address_p (unsigned HOST_WIDE_INT address)
15022 unsigned HOST_WIDE_INT upper;
15024 /* Check for KSEG1. */
15025 if (address + 0x60000000 < 0x20000000)
15028 /* Check for uncached XKPHYS addresses. */
15029 if (Pmode == DImode)
15031 upper = (address >> 40) & 0xf9ffff;
15032 if (upper == 0x900000 || upper == 0xb80000)
15038 /* Return true if we can prove that an access to address X in instruction
15039 INSN would be safe from R10K speculation. This X is a general
15040 expression; it might not be a legitimate address. */
15043 r10k_safe_address_p (rtx x, rtx insn)
15046 HOST_WIDE_INT offset_val;
15048 x = r10k_simplify_address (x, insn);
15050 /* Check for references to the stack frame. It doesn't really matter
15051 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
15052 allows us to assume that accesses to any part of the eventual frame
15053 is safe from speculation at any point in the function. */
15054 mips_split_plus (x, &base, &offset_val);
15055 if (base == virtual_incoming_args_rtx
15056 && offset_val >= -cfun->machine->frame.total_size
15057 && offset_val < cfun->machine->frame.args_size)
15060 /* Check for uncached addresses. */
15061 if (CONST_INT_P (x))
15062 return r10k_uncached_address_p (INTVAL (x));
15064 /* Check for accesses to a static object. */
15065 split_const (x, &base, &offset);
15066 return offset_within_block_p (base, INTVAL (offset));
15069 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
15070 an in-range access to an automatic variable, or to an object with
15071 a link-time-constant address. */
15074 r10k_safe_mem_expr_p (tree expr, unsigned HOST_WIDE_INT offset)
15076 HOST_WIDE_INT bitoffset, bitsize;
15077 tree inner, var_offset;
15078 enum machine_mode mode;
15079 int unsigned_p, volatile_p;
15081 inner = get_inner_reference (expr, &bitsize, &bitoffset, &var_offset, &mode,
15082 &unsigned_p, &volatile_p, false);
15083 if (!DECL_P (inner) || !DECL_SIZE_UNIT (inner) || var_offset)
15086 offset += bitoffset / BITS_PER_UNIT;
15087 return offset < tree_to_uhwi (DECL_SIZE_UNIT (inner));
15090 /* A for_each_rtx callback for which DATA points to the instruction
15091 containing *X. Stop the search if we find a MEM that is not safe
15092 from R10K speculation. */
15095 r10k_needs_protection_p_1 (rtx *loc, void *data)
15104 && MEM_OFFSET_KNOWN_P (mem)
15105 && r10k_safe_mem_expr_p (MEM_EXPR (mem), MEM_OFFSET (mem)))
15108 if (r10k_safe_address_p (XEXP (mem, 0), (rtx) data))
15114 /* A note_stores callback for which DATA points to an instruction pointer.
15115 If *DATA is nonnull, make it null if it X contains a MEM that is not
15116 safe from R10K speculation. */
15119 r10k_needs_protection_p_store (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
15124 insn_ptr = (rtx *) data;
15125 if (*insn_ptr && for_each_rtx (&x, r10k_needs_protection_p_1, *insn_ptr))
15126 *insn_ptr = NULL_RTX;
15129 /* A for_each_rtx callback that iterates over the pattern of a CALL_INSN.
15130 Return nonzero if the call is not to a declared function. */
15133 r10k_needs_protection_p_call (rtx *loc, void *data ATTRIBUTE_UNUSED)
15142 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DECL (x))
15148 /* Return true if instruction INSN needs to be protected by an R10K
15152 r10k_needs_protection_p (rtx insn)
15155 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_call, NULL);
15157 if (mips_r10k_cache_barrier == R10K_CACHE_BARRIER_STORE)
15159 note_stores (PATTERN (insn), r10k_needs_protection_p_store, &insn);
15160 return insn == NULL_RTX;
15163 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_1, insn);
15166 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
15167 edge is unconditional. */
15170 r10k_protected_bb_p (basic_block bb, sbitmap protected_bbs)
15175 FOR_EACH_EDGE (e, ei, bb->preds)
15176 if (!single_succ_p (e->src)
15177 || !bitmap_bit_p (protected_bbs, e->src->index)
15178 || (e->flags & EDGE_COMPLEX) != 0)
15183 /* Implement -mr10k-cache-barrier= for the current function. */
15186 r10k_insert_cache_barriers (void)
15188 int *rev_post_order;
15191 sbitmap protected_bbs;
15192 rtx insn, end, unprotected_region;
15196 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
15200 /* Calculate dominators. */
15201 calculate_dominance_info (CDI_DOMINATORS);
15203 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
15204 X is protected by a cache barrier. */
15205 protected_bbs = sbitmap_alloc (last_basic_block_for_fn (cfun));
15206 bitmap_clear (protected_bbs);
15208 /* Iterate over the basic blocks in reverse post-order. */
15209 rev_post_order = XNEWVEC (int, last_basic_block_for_fn (cfun));
15210 n = pre_and_rev_post_order_compute (NULL, rev_post_order, false);
15211 for (i = 0; i < n; i++)
15213 bb = BASIC_BLOCK_FOR_FN (cfun, rev_post_order[i]);
15215 /* If this block is only reached by unconditional edges, and if the
15216 source of every edge is protected, the beginning of the block is
15218 if (r10k_protected_bb_p (bb, protected_bbs))
15219 unprotected_region = NULL_RTX;
15221 unprotected_region = pc_rtx;
15222 end = NEXT_INSN (BB_END (bb));
15224 /* UNPROTECTED_REGION is:
15226 - null if we are processing a protected region,
15227 - pc_rtx if we are processing an unprotected region but have
15228 not yet found the first instruction in it
15229 - the first instruction in an unprotected region otherwise. */
15230 for (insn = BB_HEAD (bb); insn != end; insn = NEXT_INSN (insn))
15232 if (unprotected_region && USEFUL_INSN_P (insn))
15234 if (recog_memoized (insn) == CODE_FOR_mips_cache)
15235 /* This CACHE instruction protects the following code. */
15236 unprotected_region = NULL_RTX;
15239 /* See if INSN is the first instruction in this
15240 unprotected region. */
15241 if (unprotected_region == pc_rtx)
15242 unprotected_region = insn;
15244 /* See if INSN needs to be protected. If so,
15245 we must insert a cache barrier somewhere between
15246 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
15247 clear which position is better performance-wise,
15248 but as a tie-breaker, we assume that it is better
15249 to allow delay slots to be back-filled where
15250 possible, and that it is better not to insert
15251 barriers in the middle of already-scheduled code.
15252 We therefore insert the barrier at the beginning
15254 if (r10k_needs_protection_p (insn))
15256 emit_insn_before (gen_r10k_cache_barrier (),
15257 unprotected_region);
15258 unprotected_region = NULL_RTX;
15264 /* The called function is not required to protect the exit path.
15265 The code that follows a call is therefore unprotected. */
15266 unprotected_region = pc_rtx;
15269 /* Record whether the end of this block is protected. */
15270 if (unprotected_region == NULL_RTX)
15271 bitmap_set_bit (protected_bbs, bb->index);
15273 XDELETEVEC (rev_post_order);
15275 sbitmap_free (protected_bbs);
15277 free_dominance_info (CDI_DOMINATORS);
15280 /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX
15281 otherwise. If INSN has two call rtx, then store the second one in
15285 mips_call_expr_from_insn (rtx insn, rtx *second_call)
15290 if (!CALL_P (insn))
15293 x = PATTERN (insn);
15294 if (GET_CODE (x) == PARALLEL)
15296 /* Calls returning complex values have two CALL rtx. Look for the second
15297 one here, and return it via the SECOND_CALL arg. */
15298 x2 = XVECEXP (x, 0, 1);
15299 if (GET_CODE (x2) == SET)
15301 if (GET_CODE (x2) == CALL)
15304 x = XVECEXP (x, 0, 0);
15306 if (GET_CODE (x) == SET)
15308 gcc_assert (GET_CODE (x) == CALL);
15313 /* REG is set in DEF. See if the definition is one of the ways we load a
15314 register with a symbol address for a mips_use_pic_fn_addr_reg_p call.
15315 If it is, return the symbol reference of the function, otherwise return
15318 If RECURSE_P is true, use mips_find_pic_call_symbol to interpret
15319 the values of source registers, otherwise treat such registers as
15320 having an unknown value. */
15323 mips_pic_call_symbol_from_set (df_ref def, rtx reg, bool recurse_p)
15327 if (DF_REF_IS_ARTIFICIAL (def))
15330 def_insn = DF_REF_INSN (def);
15331 set = single_set (def_insn);
15332 if (set && rtx_equal_p (SET_DEST (set), reg))
15334 rtx note, src, symbol;
15336 /* First see whether the source is a plain symbol. This is used
15337 when calling symbols that are not lazily bound. */
15338 src = SET_SRC (set);
15339 if (GET_CODE (src) == SYMBOL_REF)
15342 /* Handle %call16 references. */
15343 symbol = mips_strip_unspec_call (src);
15346 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
15350 /* If we have something more complicated, look for a
15351 REG_EQUAL or REG_EQUIV note. */
15352 note = find_reg_equal_equiv_note (def_insn);
15353 if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF)
15354 return XEXP (note, 0);
15356 /* Follow at most one simple register copy. Such copies are
15357 interesting in cases like:
15361 locally_binding_fn (...);
15366 locally_binding_fn (...);
15368 locally_binding_fn (...);
15370 where the load of locally_binding_fn can legitimately be
15371 hoisted or shared. However, we do not expect to see complex
15372 chains of copies, so a full worklist solution to the problem
15373 would probably be overkill. */
15374 if (recurse_p && REG_P (src))
15375 return mips_find_pic_call_symbol (def_insn, src, false);
15381 /* Find the definition of the use of REG in INSN. See if the definition
15382 is one of the ways we load a register with a symbol address for a
15383 mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference
15384 of the function, otherwise return NULL_RTX. RECURSE_P is as for
15385 mips_pic_call_symbol_from_set. */
15388 mips_find_pic_call_symbol (rtx insn, rtx reg, bool recurse_p)
15391 struct df_link *defs;
15394 use = df_find_use (insn, regno_reg_rtx[REGNO (reg)]);
15397 defs = DF_REF_CHAIN (use);
15400 symbol = mips_pic_call_symbol_from_set (defs->ref, reg, recurse_p);
15404 /* If we have more than one definition, they need to be identical. */
15405 for (defs = defs->next; defs; defs = defs->next)
15409 other = mips_pic_call_symbol_from_set (defs->ref, reg, recurse_p);
15410 if (!rtx_equal_p (symbol, other))
15417 /* Replace the args_size operand of the call expression CALL with the
15418 call-attribute UNSPEC and fill in SYMBOL as the function symbol. */
15421 mips_annotate_pic_call_expr (rtx call, rtx symbol)
15425 args_size = XEXP (call, 1);
15426 XEXP (call, 1) = gen_rtx_UNSPEC (GET_MODE (args_size),
15427 gen_rtvec (2, args_size, symbol),
15431 /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See
15432 if instead of the arg_size argument it contains the call attributes. If
15433 yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function
15434 symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is
15438 mips_get_pic_call_symbol (rtx *operands, int args_size_opno)
15440 rtx args_size, symbol;
15442 if (!TARGET_RELAX_PIC_CALLS || args_size_opno == -1)
15445 args_size = operands[args_size_opno];
15446 if (GET_CODE (args_size) != UNSPEC)
15448 gcc_assert (XINT (args_size, 1) == UNSPEC_CALL_ATTR);
15450 symbol = XVECEXP (args_size, 0, 1);
15451 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
15453 operands[args_size_opno] = symbol;
15457 /* Use DF to annotate PIC indirect calls with the function symbol they
15461 mips_annotate_pic_calls (void)
15466 FOR_EACH_BB_FN (bb, cfun)
15467 FOR_BB_INSNS (bb, insn)
15469 rtx call, reg, symbol, second_call;
15472 call = mips_call_expr_from_insn (insn, &second_call);
15475 gcc_assert (MEM_P (XEXP (call, 0)));
15476 reg = XEXP (XEXP (call, 0), 0);
15480 symbol = mips_find_pic_call_symbol (insn, reg, true);
15483 mips_annotate_pic_call_expr (call, symbol);
15485 mips_annotate_pic_call_expr (second_call, symbol);
15490 /* A temporary variable used by for_each_rtx callbacks, etc. */
15491 static rtx mips_sim_insn;
15493 /* A structure representing the state of the processor pipeline.
15494 Used by the mips_sim_* family of functions. */
15496 /* The maximum number of instructions that can be issued in a cycle.
15497 (Caches mips_issue_rate.) */
15498 unsigned int issue_rate;
15500 /* The current simulation time. */
15503 /* How many more instructions can be issued in the current cycle. */
15504 unsigned int insns_left;
15506 /* LAST_SET[X].INSN is the last instruction to set register X.
15507 LAST_SET[X].TIME is the time at which that instruction was issued.
15508 INSN is null if no instruction has yet set register X. */
15512 } last_set[FIRST_PSEUDO_REGISTER];
15514 /* The pipeline's current DFA state. */
15518 /* Reset STATE to the initial simulation state. */
15521 mips_sim_reset (struct mips_sim *state)
15523 curr_state = state->dfa_state;
15526 state->insns_left = state->issue_rate;
15527 memset (&state->last_set, 0, sizeof (state->last_set));
15528 state_reset (curr_state);
15530 targetm.sched.init (0, false, 0);
15531 advance_state (curr_state);
15534 /* Initialize STATE before its first use. DFA_STATE points to an
15535 allocated but uninitialized DFA state. */
15538 mips_sim_init (struct mips_sim *state, state_t dfa_state)
15540 if (targetm.sched.init_dfa_pre_cycle_insn)
15541 targetm.sched.init_dfa_pre_cycle_insn ();
15543 if (targetm.sched.init_dfa_post_cycle_insn)
15544 targetm.sched.init_dfa_post_cycle_insn ();
15546 state->issue_rate = mips_issue_rate ();
15547 state->dfa_state = dfa_state;
15548 mips_sim_reset (state);
15551 /* Advance STATE by one clock cycle. */
15554 mips_sim_next_cycle (struct mips_sim *state)
15556 curr_state = state->dfa_state;
15559 state->insns_left = state->issue_rate;
15560 advance_state (curr_state);
15563 /* Advance simulation state STATE until instruction INSN can read
15567 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
15569 unsigned int regno, end_regno;
15571 end_regno = END_REGNO (reg);
15572 for (regno = REGNO (reg); regno < end_regno; regno++)
15573 if (state->last_set[regno].insn != 0)
15577 t = (state->last_set[regno].time
15578 + insn_latency (state->last_set[regno].insn, insn));
15579 while (state->time < t)
15580 mips_sim_next_cycle (state);
15584 /* A for_each_rtx callback. If *X is a register, advance simulation state
15585 DATA until mips_sim_insn can read the register's value. */
15588 mips_sim_wait_regs_2 (rtx *x, void *data)
15591 mips_sim_wait_reg ((struct mips_sim *) data, mips_sim_insn, *x);
15595 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
15598 mips_sim_wait_regs_1 (rtx *x, void *data)
15600 for_each_rtx (x, mips_sim_wait_regs_2, data);
15603 /* Advance simulation state STATE until all of INSN's register
15604 dependencies are satisfied. */
15607 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
15609 mips_sim_insn = insn;
15610 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
15613 /* Advance simulation state STATE until the units required by
15614 instruction INSN are available. */
15617 mips_sim_wait_units (struct mips_sim *state, rtx insn)
15621 tmp_state = alloca (state_size ());
15622 while (state->insns_left == 0
15623 || (memcpy (tmp_state, state->dfa_state, state_size ()),
15624 state_transition (tmp_state, insn) >= 0))
15625 mips_sim_next_cycle (state);
15628 /* Advance simulation state STATE until INSN is ready to issue. */
15631 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
15633 mips_sim_wait_regs (state, insn);
15634 mips_sim_wait_units (state, insn);
15637 /* mips_sim_insn has just set X. Update the LAST_SET array
15638 in simulation state DATA. */
15641 mips_sim_record_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
15643 struct mips_sim *state;
15645 state = (struct mips_sim *) data;
15648 unsigned int regno, end_regno;
15650 end_regno = END_REGNO (x);
15651 for (regno = REGNO (x); regno < end_regno; regno++)
15653 state->last_set[regno].insn = mips_sim_insn;
15654 state->last_set[regno].time = state->time;
15659 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
15660 can issue immediately (i.e., that mips_sim_wait_insn has already
15664 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
15666 curr_state = state->dfa_state;
15668 state_transition (curr_state, insn);
15669 state->insns_left = targetm.sched.variable_issue (0, false, insn,
15670 state->insns_left);
15672 mips_sim_insn = insn;
15673 note_stores (PATTERN (insn), mips_sim_record_set, state);
15676 /* Simulate issuing a NOP in state STATE. */
15679 mips_sim_issue_nop (struct mips_sim *state)
15681 if (state->insns_left == 0)
15682 mips_sim_next_cycle (state);
15683 state->insns_left--;
15686 /* Update simulation state STATE so that it's ready to accept the instruction
15687 after INSN. INSN should be part of the main rtl chain, not a member of a
15691 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
15693 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
15695 mips_sim_issue_nop (state);
15697 switch (GET_CODE (SEQ_BEGIN (insn)))
15701 /* We can't predict the processor state after a call or label. */
15702 mips_sim_reset (state);
15706 /* The delay slots of branch likely instructions are only executed
15707 when the branch is taken. Therefore, if the caller has simulated
15708 the delay slot instruction, STATE does not really reflect the state
15709 of the pipeline for the instruction after the delay slot. Also,
15710 branch likely instructions tend to incur a penalty when not taken,
15711 so there will probably be an extra delay between the branch and
15712 the instruction after the delay slot. */
15713 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
15714 mips_sim_reset (state);
15722 /* Use simulator state STATE to calculate the execution time of
15723 instruction sequence SEQ. */
15725 static unsigned int
15726 mips_seq_time (struct mips_sim *state, rtx seq)
15728 mips_sim_reset (state);
15729 for (rtx insn = seq; insn; insn = NEXT_INSN (insn))
15731 mips_sim_wait_insn (state, insn);
15732 mips_sim_issue_insn (state, insn);
15734 return state->time;
15737 /* Return the execution-time cost of mips_tuning_info.fast_mult_zero_zero_p
15738 setting SETTING, using STATE to simulate instruction sequences. */
15740 static unsigned int
15741 mips_mult_zero_zero_cost (struct mips_sim *state, bool setting)
15743 mips_tuning_info.fast_mult_zero_zero_p = setting;
15746 enum machine_mode dword_mode = TARGET_64BIT ? TImode : DImode;
15747 rtx hilo = gen_rtx_REG (dword_mode, MD_REG_FIRST);
15748 mips_emit_move_or_split (hilo, const0_rtx, SPLIT_FOR_SPEED);
15750 /* If the target provides mulsidi3_32bit then that's the most likely
15751 consumer of the result. Test for bypasses. */
15752 if (dword_mode == DImode && HAVE_maddsidi4)
15754 rtx gpr = gen_rtx_REG (SImode, GP_REG_FIRST + 4);
15755 emit_insn (gen_maddsidi4 (hilo, gpr, gpr, hilo));
15758 unsigned int time = mips_seq_time (state, get_insns ());
15763 /* Check the relative speeds of "MULT $0,$0" and "MTLO $0; MTHI $0"
15764 and set up mips_tuning_info.fast_mult_zero_zero_p accordingly.
15765 Prefer MULT -- which is shorter -- in the event of a tie. */
15768 mips_set_fast_mult_zero_zero_p (struct mips_sim *state)
15771 /* No MTLO or MTHI available. */
15772 mips_tuning_info.fast_mult_zero_zero_p = true;
15775 unsigned int true_time = mips_mult_zero_zero_cost (state, true);
15776 unsigned int false_time = mips_mult_zero_zero_cost (state, false);
15777 mips_tuning_info.fast_mult_zero_zero_p = (true_time <= false_time);
15781 /* Set up costs based on the current architecture and tuning settings. */
15784 mips_set_tuning_info (void)
15786 if (mips_tuning_info.initialized_p
15787 && mips_tuning_info.arch == mips_arch
15788 && mips_tuning_info.tune == mips_tune
15789 && mips_tuning_info.mips16_p == TARGET_MIPS16)
15792 mips_tuning_info.arch = mips_arch;
15793 mips_tuning_info.tune = mips_tune;
15794 mips_tuning_info.mips16_p = TARGET_MIPS16;
15795 mips_tuning_info.initialized_p = true;
15799 struct mips_sim state;
15800 mips_sim_init (&state, alloca (state_size ()));
15802 mips_set_fast_mult_zero_zero_p (&state);
15807 /* Implement TARGET_EXPAND_TO_RTL_HOOK. */
15810 mips_expand_to_rtl_hook (void)
15812 /* We need to call this at a point where we can safely create sequences
15813 of instructions, so TARGET_OVERRIDE_OPTIONS is too early. We also
15814 need to call it at a point where the DFA infrastructure is not
15815 already in use, so we can't just call it lazily on demand.
15817 At present, mips_tuning_info is only needed during post-expand
15818 RTL passes such as split_insns, so this hook should be early enough.
15819 We may need to move the call elsewhere if mips_tuning_info starts
15820 to be used for other things (such as rtx_costs, or expanders that
15821 could be called during gimple optimization). */
15822 mips_set_tuning_info ();
15825 /* The VR4130 pipeline issues aligned pairs of instructions together,
15826 but it stalls the second instruction if it depends on the first.
15827 In order to cut down the amount of logic required, this dependence
15828 check is not based on a full instruction decode. Instead, any non-SPECIAL
15829 instruction is assumed to modify the register specified by bits 20-16
15830 (which is usually the "rt" field).
15832 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
15833 input, so we can end up with a false dependence between the branch
15834 and its delay slot. If this situation occurs in instruction INSN,
15835 try to avoid it by swapping rs and rt. */
15838 vr4130_avoid_branch_rt_conflict (rtx insn)
15842 first = SEQ_BEGIN (insn);
15843 second = SEQ_END (insn);
15845 && NONJUMP_INSN_P (second)
15846 && GET_CODE (PATTERN (first)) == SET
15847 && GET_CODE (SET_DEST (PATTERN (first))) == PC
15848 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
15850 /* Check for the right kind of condition. */
15851 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
15852 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
15853 && REG_P (XEXP (cond, 0))
15854 && REG_P (XEXP (cond, 1))
15855 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
15856 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
15858 /* SECOND mentions the rt register but not the rs register. */
15859 rtx tmp = XEXP (cond, 0);
15860 XEXP (cond, 0) = XEXP (cond, 1);
15861 XEXP (cond, 1) = tmp;
15866 /* Implement -mvr4130-align. Go through each basic block and simulate the
15867 processor pipeline. If we find that a pair of instructions could execute
15868 in parallel, and the first of those instructions is not 8-byte aligned,
15869 insert a nop to make it aligned. */
15872 vr4130_align_insns (void)
15874 struct mips_sim state;
15875 rtx insn, subinsn, last, last2, next;
15880 /* LAST is the last instruction before INSN to have a nonzero length.
15881 LAST2 is the last such instruction before LAST. */
15885 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
15888 mips_sim_init (&state, alloca (state_size ()));
15889 for (insn = get_insns (); insn != 0; insn = next)
15891 unsigned int length;
15893 next = NEXT_INSN (insn);
15895 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
15896 This isn't really related to the alignment pass, but we do it on
15897 the fly to avoid a separate instruction walk. */
15898 vr4130_avoid_branch_rt_conflict (insn);
15900 length = get_attr_length (insn);
15901 if (length > 0 && USEFUL_INSN_P (insn))
15902 FOR_EACH_SUBINSN (subinsn, insn)
15904 mips_sim_wait_insn (&state, subinsn);
15906 /* If we want this instruction to issue in parallel with the
15907 previous one, make sure that the previous instruction is
15908 aligned. There are several reasons why this isn't worthwhile
15909 when the second instruction is a call:
15911 - Calls are less likely to be performance critical,
15912 - There's a good chance that the delay slot can execute
15913 in parallel with the call.
15914 - The return address would then be unaligned.
15916 In general, if we're going to insert a nop between instructions
15917 X and Y, it's better to insert it immediately after X. That
15918 way, if the nop makes Y aligned, it will also align any labels
15919 between X and Y. */
15920 if (state.insns_left != state.issue_rate
15921 && !CALL_P (subinsn))
15923 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
15925 /* SUBINSN is the first instruction in INSN and INSN is
15926 aligned. We want to align the previous instruction
15927 instead, so insert a nop between LAST2 and LAST.
15929 Note that LAST could be either a single instruction
15930 or a branch with a delay slot. In the latter case,
15931 LAST, like INSN, is already aligned, but the delay
15932 slot must have some extra delay that stops it from
15933 issuing at the same time as the branch. We therefore
15934 insert a nop before the branch in order to align its
15936 gcc_assert (last2);
15937 emit_insn_after (gen_nop (), last2);
15940 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
15942 /* SUBINSN is the delay slot of INSN, but INSN is
15943 currently unaligned. Insert a nop between
15944 LAST and INSN to align it. */
15946 emit_insn_after (gen_nop (), last);
15950 mips_sim_issue_insn (&state, subinsn);
15952 mips_sim_finish_insn (&state, insn);
15954 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
15955 length = get_attr_length (insn);
15958 /* If the instruction is an asm statement or multi-instruction
15959 mips.md patern, the length is only an estimate. Insert an
15960 8 byte alignment after it so that the following instructions
15961 can be handled correctly. */
15962 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
15963 && (recog_memoized (insn) < 0 || length >= 8))
15965 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
15966 next = NEXT_INSN (next);
15967 mips_sim_next_cycle (&state);
15970 else if (length & 4)
15971 aligned_p = !aligned_p;
15976 /* See whether INSN is an aligned label. */
15977 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
15983 /* This structure records that the current function has a LO_SUM
15984 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
15985 the largest offset applied to BASE by all such LO_SUMs. */
15986 struct mips_lo_sum_offset {
15988 HOST_WIDE_INT offset;
15991 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
15994 mips_hash_base (rtx base)
15996 int do_not_record_p;
15998 return hash_rtx (base, GET_MODE (base), &do_not_record_p, NULL, false);
16001 /* Hashtable helpers. */
16003 struct mips_lo_sum_offset_hasher : typed_free_remove <mips_lo_sum_offset>
16005 typedef mips_lo_sum_offset value_type;
16006 typedef rtx_def compare_type;
16007 static inline hashval_t hash (const value_type *);
16008 static inline bool equal (const value_type *, const compare_type *);
16011 /* Hash-table callbacks for mips_lo_sum_offsets. */
16014 mips_lo_sum_offset_hasher::hash (const value_type *entry)
16016 return mips_hash_base (entry->base);
16020 mips_lo_sum_offset_hasher::equal (const value_type *entry,
16021 const compare_type *value)
16023 return rtx_equal_p (entry->base, value);
16026 typedef hash_table <mips_lo_sum_offset_hasher> mips_offset_table;
16028 /* Look up symbolic constant X in HTAB, which is a hash table of
16029 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
16030 paired with a recorded LO_SUM, otherwise record X in the table. */
16033 mips_lo_sum_offset_lookup (mips_offset_table htab, rtx x,
16034 enum insert_option option)
16037 mips_lo_sum_offset **slot;
16038 struct mips_lo_sum_offset *entry;
16040 /* Split X into a base and offset. */
16041 split_const (x, &base, &offset);
16042 if (UNSPEC_ADDRESS_P (base))
16043 base = UNSPEC_ADDRESS (base);
16045 /* Look up the base in the hash table. */
16046 slot = htab.find_slot_with_hash (base, mips_hash_base (base), option);
16050 entry = (struct mips_lo_sum_offset *) *slot;
16051 if (option == INSERT)
16055 entry = XNEW (struct mips_lo_sum_offset);
16056 entry->base = base;
16057 entry->offset = INTVAL (offset);
16062 if (INTVAL (offset) > entry->offset)
16063 entry->offset = INTVAL (offset);
16066 return INTVAL (offset) <= entry->offset;
16069 /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table.
16070 Record every LO_SUM in *LOC. */
16073 mips_record_lo_sum (rtx *loc, void *data)
16075 if (GET_CODE (*loc) == LO_SUM)
16076 mips_lo_sum_offset_lookup (*(mips_offset_table*) data,
16077 XEXP (*loc, 1), INSERT);
16081 /* Return true if INSN is a SET of an orphaned high-part relocation.
16082 HTAB is a hash table of mips_lo_sum_offsets that describes all the
16083 LO_SUMs in the current function. */
16086 mips_orphaned_high_part_p (mips_offset_table htab, rtx insn)
16088 enum mips_symbol_type type;
16091 set = single_set (insn);
16094 /* Check for %his. */
16096 if (GET_CODE (x) == HIGH
16097 && absolute_symbolic_operand (XEXP (x, 0), VOIDmode))
16098 return !mips_lo_sum_offset_lookup (htab, XEXP (x, 0), NO_INSERT);
16100 /* Check for local %gots (and %got_pages, which is redundant but OK). */
16101 if (GET_CODE (x) == UNSPEC
16102 && XINT (x, 1) == UNSPEC_LOAD_GOT
16103 && mips_symbolic_constant_p (XVECEXP (x, 0, 1),
16104 SYMBOL_CONTEXT_LEA, &type)
16105 && type == SYMBOL_GOTOFF_PAGE)
16106 return !mips_lo_sum_offset_lookup (htab, XVECEXP (x, 0, 1), NO_INSERT);
16111 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
16112 INSN and a previous instruction, avoid it by inserting nops after
16115 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
16116 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
16117 before using the value of that register. *HILO_DELAY counts the
16118 number of instructions since the last hilo hazard (that is,
16119 the number of instructions since the last MFLO or MFHI).
16121 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
16122 for the next instruction.
16124 LO_REG is an rtx for the LO register, used in dependence checking. */
16127 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
16128 rtx *delayed_reg, rtx lo_reg)
16133 pattern = PATTERN (insn);
16135 /* Do not put the whole function in .set noreorder if it contains
16136 an asm statement. We don't know whether there will be hazards
16137 between the asm statement and the gcc-generated code. */
16138 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
16139 cfun->machine->all_noreorder_p = false;
16141 /* Ignore zero-length instructions (barriers and the like). */
16142 ninsns = get_attr_length (insn) / 4;
16146 /* Work out how many nops are needed. Note that we only care about
16147 registers that are explicitly mentioned in the instruction's pattern.
16148 It doesn't matter that calls use the argument registers or that they
16149 clobber hi and lo. */
16150 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
16151 nops = 2 - *hilo_delay;
16152 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
16157 /* Insert the nops between this instruction and the previous one.
16158 Each new nop takes us further from the last hilo hazard. */
16159 *hilo_delay += nops;
16161 emit_insn_after (gen_hazard_nop (), after);
16163 /* Set up the state for the next instruction. */
16164 *hilo_delay += ninsns;
16166 if (INSN_CODE (insn) >= 0)
16167 switch (get_attr_hazard (insn))
16177 set = single_set (insn);
16179 *delayed_reg = SET_DEST (set);
16184 /* Go through the instruction stream and insert nops where necessary.
16185 Also delete any high-part relocations whose partnering low parts
16186 are now all dead. See if the whole function can then be put into
16187 .set noreorder and .set nomacro. */
16190 mips_reorg_process_insns (void)
16192 rtx insn, last_insn, subinsn, next_insn, lo_reg, delayed_reg;
16194 mips_offset_table htab;
16196 /* Force all instructions to be split into their final form. */
16197 split_all_insns_noflow ();
16199 /* Recalculate instruction lengths without taking nops into account. */
16200 cfun->machine->ignore_hazard_length_p = true;
16201 shorten_branches (get_insns ());
16203 cfun->machine->all_noreorder_p = true;
16205 /* We don't track MIPS16 PC-relative offsets closely enough to make
16206 a good job of "set .noreorder" code in MIPS16 mode. */
16208 cfun->machine->all_noreorder_p = false;
16210 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
16211 if (!TARGET_EXPLICIT_RELOCS)
16212 cfun->machine->all_noreorder_p = false;
16214 /* Profiled functions can't be all noreorder because the profiler
16215 support uses assembler macros. */
16217 cfun->machine->all_noreorder_p = false;
16219 /* Code compiled with -mfix-vr4120, -mfix-rm7000 or -mfix-24k can't be
16220 all noreorder because we rely on the assembler to work around some
16221 errata. The R5900 too has several bugs. */
16222 if (TARGET_FIX_VR4120
16223 || TARGET_FIX_RM7000
16225 || TARGET_MIPS5900)
16226 cfun->machine->all_noreorder_p = false;
16228 /* The same is true for -mfix-vr4130 if we might generate MFLO or
16229 MFHI instructions. Note that we avoid using MFLO and MFHI if
16230 the VR4130 MACC and DMACC instructions are available instead;
16231 see the *mfhilo_{si,di}_macc patterns. */
16232 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
16233 cfun->machine->all_noreorder_p = false;
16237 /* Make a first pass over the instructions, recording all the LO_SUMs. */
16238 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
16239 FOR_EACH_SUBINSN (subinsn, insn)
16240 if (USEFUL_INSN_P (subinsn))
16242 rtx body = PATTERN (insn);
16243 int noperands = asm_noperands (body);
16244 if (noperands >= 0)
16246 rtx *ops = XALLOCAVEC (rtx, noperands);
16247 bool *used = XALLOCAVEC (bool, noperands);
16248 const char *string = decode_asm_operands (body, ops, NULL, NULL,
16250 get_referenced_operands (string, used, noperands);
16251 for (int i = 0; i < noperands; ++i)
16253 for_each_rtx (&ops[i], mips_record_lo_sum, &htab);
16256 for_each_rtx (&PATTERN (subinsn), mips_record_lo_sum, &htab);
16262 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
16264 /* Make a second pass over the instructions. Delete orphaned
16265 high-part relocations or turn them into NOPs. Avoid hazards
16266 by inserting NOPs. */
16267 for (insn = get_insns (); insn != 0; insn = next_insn)
16269 next_insn = NEXT_INSN (insn);
16270 if (USEFUL_INSN_P (insn))
16272 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
16274 /* If we find an orphaned high-part relocation in a delay
16275 slot, it's easier to turn that instruction into a NOP than
16276 to delete it. The delay slot will be a NOP either way. */
16277 FOR_EACH_SUBINSN (subinsn, insn)
16278 if (INSN_P (subinsn))
16280 if (mips_orphaned_high_part_p (htab, subinsn))
16282 PATTERN (subinsn) = gen_nop ();
16283 INSN_CODE (subinsn) = CODE_FOR_nop;
16285 mips_avoid_hazard (last_insn, subinsn, &hilo_delay,
16286 &delayed_reg, lo_reg);
16292 /* INSN is a single instruction. Delete it if it's an
16293 orphaned high-part relocation. */
16294 if (mips_orphaned_high_part_p (htab, insn))
16295 delete_insn (insn);
16296 /* Also delete cache barriers if the last instruction
16297 was an annulled branch. INSN will not be speculatively
16299 else if (recog_memoized (insn) == CODE_FOR_r10k_cache_barrier
16301 && JUMP_P (SEQ_BEGIN (last_insn))
16302 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn)))
16303 delete_insn (insn);
16306 mips_avoid_hazard (last_insn, insn, &hilo_delay,
16307 &delayed_reg, lo_reg);
16317 /* Return true if the function has a long branch instruction. */
16320 mips_has_long_branch_p (void)
16325 /* We need up-to-date instruction lengths. */
16326 shorten_branches (get_insns ());
16328 /* Look for a branch that is longer than normal. The normal length for
16329 non-MIPS16 branches is 8, because the length includes the delay slot.
16330 It is 4 for MIPS16, because MIPS16 branches are extended instructions,
16331 but they have no delay slot. */
16332 normal_length = (TARGET_MIPS16 ? 4 : 8);
16333 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
16334 FOR_EACH_SUBINSN (subinsn, insn)
16335 if (JUMP_P (subinsn)
16336 && get_attr_length (subinsn) > normal_length
16337 && (any_condjump_p (subinsn) || any_uncondjump_p (subinsn)))
16343 /* If we are using a GOT, but have not decided to use a global pointer yet,
16344 see whether we need one to implement long branches. Convert the ghost
16345 global-pointer instructions into real ones if so. */
16348 mips_expand_ghost_gp_insns (void)
16350 /* Quick exit if we already know that we will or won't need a
16352 if (!TARGET_USE_GOT
16353 || cfun->machine->global_pointer == INVALID_REGNUM
16354 || mips_must_initialize_gp_p ())
16357 /* Run a full check for long branches. */
16358 if (!mips_has_long_branch_p ())
16361 /* We've now established that we need $gp. */
16362 cfun->machine->must_initialize_gp_p = true;
16363 split_all_insns_noflow ();
16368 /* Subroutine of mips_reorg to manage passes that require DF. */
16371 mips_df_reorg (void)
16373 /* Create def-use chains. */
16374 df_set_flags (DF_EQ_NOTES);
16375 df_chain_add_problem (DF_UD_CHAIN);
16378 if (TARGET_RELAX_PIC_CALLS)
16379 mips_annotate_pic_calls ();
16381 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE)
16382 r10k_insert_cache_barriers ();
16384 df_finish_pass (false);
16387 /* Emit code to load LABEL_REF SRC into MIPS16 register DEST. This is
16388 called very late in mips_reorg, but the caller is required to run
16389 mips16_lay_out_constants on the result. */
16392 mips16_load_branch_target (rtx dest, rtx src)
16394 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
16398 if (mips_cfun_has_cprestore_slot_p ())
16399 mips_emit_move (dest, mips_cprestore_slot (dest, true));
16401 mips_emit_move (dest, pic_offset_table_rtx);
16402 page = mips_unspec_address (src, SYMBOL_GOTOFF_PAGE);
16403 low = mips_unspec_address (src, SYMBOL_GOT_PAGE_OFST);
16404 emit_insn (gen_rtx_SET (VOIDmode, dest,
16405 PMODE_INSN (gen_unspec_got, (dest, page))));
16406 emit_insn (gen_rtx_SET (VOIDmode, dest,
16407 gen_rtx_LO_SUM (Pmode, dest, low)));
16411 src = mips_unspec_address (src, SYMBOL_ABSOLUTE);
16412 mips_emit_move (dest, src);
16416 /* If we're compiling a MIPS16 function, look for and split any long branches.
16417 This must be called after all other instruction modifications in
16421 mips16_split_long_branches (void)
16423 bool something_changed;
16425 if (!TARGET_MIPS16)
16428 /* Loop until the alignments for all targets are sufficient. */
16433 shorten_branches (get_insns ());
16434 something_changed = false;
16435 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
16437 && get_attr_length (insn) > 4
16438 && (any_condjump_p (insn) || any_uncondjump_p (insn)))
16440 rtx old_label, new_label, temp, saved_temp;
16441 rtx target, jump, jump_sequence;
16445 /* Free up a MIPS16 register by saving it in $1. */
16446 saved_temp = gen_rtx_REG (Pmode, AT_REGNUM);
16447 temp = gen_rtx_REG (Pmode, GP_REG_FIRST + 2);
16448 emit_move_insn (saved_temp, temp);
16450 /* Load the branch target into TEMP. */
16451 old_label = JUMP_LABEL (insn);
16452 target = gen_rtx_LABEL_REF (Pmode, old_label);
16453 mips16_load_branch_target (temp, target);
16455 /* Jump to the target and restore the register's
16457 jump = emit_jump_insn (PMODE_INSN (gen_indirect_jump_and_restore,
16458 (temp, temp, saved_temp)));
16459 JUMP_LABEL (jump) = old_label;
16460 LABEL_NUSES (old_label)++;
16462 /* Rewrite any symbolic references that are supposed to use
16463 a PC-relative constant pool. */
16464 mips16_lay_out_constants (false);
16466 if (simplejump_p (insn))
16467 /* We're going to replace INSN with a longer form. */
16468 new_label = NULL_RTX;
16471 /* Create a branch-around label for the original
16473 new_label = gen_label_rtx ();
16474 emit_label (new_label);
16477 jump_sequence = get_insns ();
16480 emit_insn_after (jump_sequence, insn);
16482 invert_jump (insn, new_label, false);
16484 delete_insn (insn);
16485 something_changed = true;
16488 while (something_changed);
16491 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
16496 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during
16497 insn splitting in mips16_lay_out_constants, DF insn info is only kept up
16498 to date if the CFG is available. */
16499 if (mips_cfg_in_reorg ())
16500 compute_bb_for_insn ();
16501 mips16_lay_out_constants (true);
16502 if (mips_cfg_in_reorg ())
16505 free_bb_for_insn ();
16509 /* We use a machine specific pass to do a second machine dependent reorg
16510 pass after delay branch scheduling. */
16512 static unsigned int
16513 mips_machine_reorg2 (void)
16515 mips_reorg_process_insns ();
16517 && TARGET_EXPLICIT_RELOCS
16519 && TARGET_VR4130_ALIGN)
16520 vr4130_align_insns ();
16521 if (mips_expand_ghost_gp_insns ())
16522 /* The expansion could invalidate some of the VR4130 alignment
16523 optimizations, but this should be an extremely rare case anyhow. */
16524 mips_reorg_process_insns ();
16525 mips16_split_long_branches ();
16531 const pass_data pass_data_mips_machine_reorg2 =
16533 RTL_PASS, /* type */
16534 "mach2", /* name */
16535 OPTGROUP_NONE, /* optinfo_flags */
16536 false, /* has_gate */
16537 true, /* has_execute */
16538 TV_MACH_DEP, /* tv_id */
16539 0, /* properties_required */
16540 0, /* properties_provided */
16541 0, /* properties_destroyed */
16542 0, /* todo_flags_start */
16543 TODO_verify_rtl_sharing, /* todo_flags_finish */
16546 class pass_mips_machine_reorg2 : public rtl_opt_pass
16549 pass_mips_machine_reorg2(gcc::context *ctxt)
16550 : rtl_opt_pass(pass_data_mips_machine_reorg2, ctxt)
16553 /* opt_pass methods: */
16554 unsigned int execute () { return mips_machine_reorg2 (); }
16556 }; // class pass_mips_machine_reorg2
16558 } // anon namespace
16561 make_pass_mips_machine_reorg2 (gcc::context *ctxt)
16563 return new pass_mips_machine_reorg2 (ctxt);
16567 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
16568 in order to avoid duplicating too much logic from elsewhere. */
16571 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
16572 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
16575 rtx this_rtx, temp1, temp2, insn, fnaddr;
16576 bool use_sibcall_p;
16578 /* Pretend to be a post-reload pass while generating rtl. */
16579 reload_completed = 1;
16581 /* Mark the end of the (empty) prologue. */
16582 emit_note (NOTE_INSN_PROLOGUE_END);
16584 /* Determine if we can use a sibcall to call FUNCTION directly. */
16585 fnaddr = XEXP (DECL_RTL (function), 0);
16586 use_sibcall_p = (mips_function_ok_for_sibcall (function, NULL)
16587 && const_call_insn_operand (fnaddr, Pmode));
16589 /* Determine if we need to load FNADDR from the GOT. */
16591 && (mips_got_symbol_type_p
16592 (mips_classify_symbol (fnaddr, SYMBOL_CONTEXT_LEA))))
16594 /* Pick a global pointer. Use a call-clobbered register if
16595 TARGET_CALL_SAVED_GP. */
16596 cfun->machine->global_pointer
16597 = TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM;
16598 cfun->machine->must_initialize_gp_p = true;
16599 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
16601 /* Set up the global pointer for n32 or n64 abicalls. */
16602 mips_emit_loadgp ();
16605 /* We need two temporary registers in some cases. */
16606 temp1 = gen_rtx_REG (Pmode, 2);
16607 temp2 = gen_rtx_REG (Pmode, 3);
16609 /* Find out which register contains the "this" pointer. */
16610 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
16611 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
16613 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST);
16615 /* Add DELTA to THIS_RTX. */
16618 rtx offset = GEN_INT (delta);
16619 if (!SMALL_OPERAND (delta))
16621 mips_emit_move (temp1, offset);
16624 emit_insn (gen_add3_insn (this_rtx, this_rtx, offset));
16627 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
16628 if (vcall_offset != 0)
16632 /* Set TEMP1 to *THIS_RTX. */
16633 mips_emit_move (temp1, gen_rtx_MEM (Pmode, this_rtx));
16635 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
16636 addr = mips_add_offset (temp2, temp1, vcall_offset);
16638 /* Load the offset and add it to THIS_RTX. */
16639 mips_emit_move (temp1, gen_rtx_MEM (Pmode, addr));
16640 emit_insn (gen_add3_insn (this_rtx, this_rtx, temp1));
16643 /* Jump to the target function. Use a sibcall if direct jumps are
16644 allowed, otherwise load the address into a register first. */
16647 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
16648 SIBLING_CALL_P (insn) = 1;
16652 /* This is messy. GAS treats "la $25,foo" as part of a call
16653 sequence and may allow a global "foo" to be lazily bound.
16654 The general move patterns therefore reject this combination.
16656 In this context, lazy binding would actually be OK
16657 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
16658 TARGET_CALL_SAVED_GP; see mips_load_call_address.
16659 We must therefore load the address via a temporary
16660 register if mips_dangerous_for_la25_p.
16662 If we jump to the temporary register rather than $25,
16663 the assembler can use the move insn to fill the jump's
16666 We can use the same technique for MIPS16 code, where $25
16667 is not a valid JR register. */
16668 if (TARGET_USE_PIC_FN_ADDR_REG
16670 && !mips_dangerous_for_la25_p (fnaddr))
16671 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
16672 mips_load_call_address (MIPS_CALL_SIBCALL, temp1, fnaddr);
16674 if (TARGET_USE_PIC_FN_ADDR_REG
16675 && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
16676 mips_emit_move (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
16677 emit_jump_insn (gen_indirect_jump (temp1));
16680 /* Run just enough of rest_of_compilation. This sequence was
16681 "borrowed" from alpha.c. */
16682 insn = get_insns ();
16683 split_all_insns_noflow ();
16684 mips16_lay_out_constants (true);
16685 shorten_branches (insn);
16686 final_start_function (insn, file, 1);
16687 final (insn, file, 1);
16688 final_end_function ();
16690 /* Clean up the vars set above. Note that final_end_function resets
16691 the global pointer for us. */
16692 reload_completed = 0;
16696 /* The last argument passed to mips_set_compression_mode,
16697 or negative if the function hasn't been called yet. */
16698 static unsigned int old_compression_mode = -1;
16700 /* Set up the target-dependent global state for ISA mode COMPRESSION_MODE,
16701 which is either MASK_MIPS16 or MASK_MICROMIPS. */
16704 mips_set_compression_mode (unsigned int compression_mode)
16707 if (compression_mode == old_compression_mode)
16710 /* Restore base settings of various flags. */
16711 target_flags = mips_base_target_flags;
16712 flag_schedule_insns = mips_base_schedule_insns;
16713 flag_reorder_blocks_and_partition = mips_base_reorder_blocks_and_partition;
16714 flag_move_loop_invariants = mips_base_move_loop_invariants;
16715 align_loops = mips_base_align_loops;
16716 align_jumps = mips_base_align_jumps;
16717 align_functions = mips_base_align_functions;
16718 target_flags &= ~(MASK_MIPS16 | MASK_MICROMIPS);
16719 target_flags |= compression_mode;
16721 if (compression_mode & MASK_MIPS16)
16723 /* Switch to MIPS16 mode. */
16724 target_flags |= MASK_MIPS16;
16726 /* Turn off SYNCI if it was on, MIPS16 doesn't support it. */
16727 target_flags &= ~MASK_SYNCI;
16729 /* Don't run the scheduler before reload, since it tends to
16730 increase register pressure. */
16731 flag_schedule_insns = 0;
16733 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
16734 the whole function to be in a single section. */
16735 flag_reorder_blocks_and_partition = 0;
16737 /* Don't move loop invariants, because it tends to increase
16738 register pressure. It also introduces an extra move in cases
16739 where the constant is the first operand in a two-operand binary
16740 instruction, or when it forms a register argument to a functon
16742 flag_move_loop_invariants = 0;
16744 target_flags |= MASK_EXPLICIT_RELOCS;
16746 /* Experiments suggest we get the best overall section-anchor
16747 results from using the range of an unextended LW or SW. Code
16748 that makes heavy use of byte or short accesses can do better
16749 with ranges of 0...31 and 0...63 respectively, but most code is
16750 sensitive to the range of LW and SW instead. */
16751 targetm.min_anchor_offset = 0;
16752 targetm.max_anchor_offset = 127;
16754 targetm.const_anchor = 0;
16756 /* MIPS16 has no BAL instruction. */
16757 target_flags &= ~MASK_RELAX_PIC_CALLS;
16759 /* The R4000 errata don't apply to any known MIPS16 cores.
16760 It's simpler to make the R4000 fixes and MIPS16 mode
16761 mutually exclusive. */
16762 target_flags &= ~MASK_FIX_R4000;
16764 if (flag_pic && !TARGET_OLDABI)
16765 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
16768 sorry ("MIPS16 -mxgot code");
16770 if (TARGET_HARD_FLOAT_ABI && !TARGET_OLDABI)
16771 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
16775 /* Switch to microMIPS or the standard encoding. */
16777 if (TARGET_MICROMIPS)
16778 /* Avoid branch likely. */
16779 target_flags &= ~MASK_BRANCHLIKELY;
16781 /* Provide default values for align_* for 64-bit targets. */
16784 if (align_loops == 0)
16786 if (align_jumps == 0)
16788 if (align_functions == 0)
16789 align_functions = 8;
16792 targetm.min_anchor_offset = -32768;
16793 targetm.max_anchor_offset = 32767;
16795 targetm.const_anchor = 0x8000;
16798 /* (Re)initialize MIPS target internals for new ISA. */
16799 mips_init_relocs ();
16801 if (compression_mode & MASK_MIPS16)
16803 if (!mips16_globals)
16804 mips16_globals = save_target_globals_default_opts ();
16806 restore_target_globals (mips16_globals);
16809 restore_target_globals (&default_target_globals);
16811 old_compression_mode = compression_mode;
16814 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
16815 function should use the MIPS16 or microMIPS ISA and switch modes
16819 mips_set_current_function (tree fndecl)
16821 mips_set_compression_mode (mips_get_compress_mode (fndecl));
16824 /* Allocate a chunk of memory for per-function machine-dependent data. */
16826 static struct machine_function *
16827 mips_init_machine_status (void)
16829 return ggc_alloc_cleared_machine_function ();
16832 /* Return the processor associated with the given ISA level, or null
16833 if the ISA isn't valid. */
16835 static const struct mips_cpu_info *
16836 mips_cpu_info_from_isa (int isa)
16840 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
16841 if (mips_cpu_info_table[i].isa == isa)
16842 return mips_cpu_info_table + i;
16847 /* Return a mips_cpu_info entry determined by an option valued
16850 static const struct mips_cpu_info *
16851 mips_cpu_info_from_opt (int opt)
16855 case MIPS_ARCH_OPTION_FROM_ABI:
16856 /* 'from-abi' selects the most compatible architecture for the
16857 given ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit
16858 ABIs. For the EABIs, we have to decide whether we're using
16859 the 32-bit or 64-bit version. */
16860 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
16861 : ABI_NEEDS_64BIT_REGS ? 3
16862 : (TARGET_64BIT ? 3 : 1));
16864 case MIPS_ARCH_OPTION_NATIVE:
16865 gcc_unreachable ();
16868 return &mips_cpu_info_table[opt];
16872 /* Return a default mips_cpu_info entry, given that no -march= option
16873 was explicitly specified. */
16875 static const struct mips_cpu_info *
16876 mips_default_arch (void)
16878 #if defined (MIPS_CPU_STRING_DEFAULT)
16880 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
16881 if (strcmp (mips_cpu_info_table[i].name, MIPS_CPU_STRING_DEFAULT) == 0)
16882 return mips_cpu_info_table + i;
16883 gcc_unreachable ();
16884 #elif defined (MIPS_ISA_DEFAULT)
16885 return mips_cpu_info_from_isa (MIPS_ISA_DEFAULT);
16887 /* 'from-abi' makes a good default: you get whatever the ABI
16889 return mips_cpu_info_from_opt (MIPS_ARCH_OPTION_FROM_ABI);
16893 /* Set up globals to generate code for the ISA or processor
16894 described by INFO. */
16897 mips_set_architecture (const struct mips_cpu_info *info)
16901 mips_arch_info = info;
16902 mips_arch = info->cpu;
16903 mips_isa = info->isa;
16907 /* Likewise for tuning. */
16910 mips_set_tune (const struct mips_cpu_info *info)
16914 mips_tune_info = info;
16915 mips_tune = info->cpu;
16919 /* Implement TARGET_OPTION_OVERRIDE. */
16922 mips_option_override (void)
16924 int i, start, regno, mode;
16926 if (global_options_set.x_mips_isa_option)
16927 mips_isa_option_info = &mips_cpu_info_table[mips_isa_option];
16929 #ifdef SUBTARGET_OVERRIDE_OPTIONS
16930 SUBTARGET_OVERRIDE_OPTIONS;
16933 /* MIPS16 and microMIPS cannot coexist. */
16934 if (TARGET_MICROMIPS && TARGET_MIPS16)
16935 error ("unsupported combination: %s", "-mips16 -mmicromips");
16937 /* Save the base compression state and process flags as though we
16938 were generating uncompressed code. */
16939 mips_base_compression_flags = TARGET_COMPRESSION;
16940 target_flags &= ~TARGET_COMPRESSION;
16942 /* -mno-float overrides -mhard-float and -msoft-float. */
16943 if (TARGET_NO_FLOAT)
16945 target_flags |= MASK_SOFT_FLOAT_ABI;
16946 target_flags_explicit |= MASK_SOFT_FLOAT_ABI;
16949 if (TARGET_FLIP_MIPS16)
16950 TARGET_INTERLINK_COMPRESSED = 1;
16952 /* Set the small data limit. */
16953 mips_small_data_threshold = (global_options_set.x_g_switch_value
16955 : MIPS_DEFAULT_GVALUE);
16957 /* The following code determines the architecture and register size.
16958 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
16959 The GAS and GCC code should be kept in sync as much as possible. */
16961 if (global_options_set.x_mips_arch_option)
16962 mips_set_architecture (mips_cpu_info_from_opt (mips_arch_option));
16964 if (mips_isa_option_info != 0)
16966 if (mips_arch_info == 0)
16967 mips_set_architecture (mips_isa_option_info);
16968 else if (mips_arch_info->isa != mips_isa_option_info->isa)
16969 error ("%<-%s%> conflicts with the other architecture options, "
16970 "which specify a %s processor",
16971 mips_isa_option_info->name,
16972 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
16975 if (mips_arch_info == 0)
16976 mips_set_architecture (mips_default_arch ());
16978 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
16979 error ("%<-march=%s%> is not compatible with the selected ABI",
16980 mips_arch_info->name);
16982 /* Optimize for mips_arch, unless -mtune selects a different processor. */
16983 if (global_options_set.x_mips_tune_option)
16984 mips_set_tune (mips_cpu_info_from_opt (mips_tune_option));
16986 if (mips_tune_info == 0)
16987 mips_set_tune (mips_arch_info);
16989 if ((target_flags_explicit & MASK_64BIT) != 0)
16991 /* The user specified the size of the integer registers. Make sure
16992 it agrees with the ABI and ISA. */
16993 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
16994 error ("%<-mgp64%> used with a 32-bit processor");
16995 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
16996 error ("%<-mgp32%> used with a 64-bit ABI");
16997 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
16998 error ("%<-mgp64%> used with a 32-bit ABI");
17002 /* Infer the integer register size from the ABI and processor.
17003 Restrict ourselves to 32-bit registers if that's all the
17004 processor has, or if the ABI cannot handle 64-bit registers. */
17005 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
17006 target_flags &= ~MASK_64BIT;
17008 target_flags |= MASK_64BIT;
17011 if ((target_flags_explicit & MASK_FLOAT64) != 0)
17013 if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
17014 error ("unsupported combination: %s", "-mfp64 -msingle-float");
17015 else if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
17016 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
17017 else if (!TARGET_64BIT && TARGET_FLOAT64)
17019 if (!ISA_HAS_MXHC1)
17020 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
17021 " the target supports the mfhc1 and mthc1 instructions");
17022 else if (mips_abi != ABI_32)
17023 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
17029 /* -msingle-float selects 32-bit float registers. Otherwise the
17030 float registers should be the same size as the integer ones. */
17031 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
17032 target_flags |= MASK_FLOAT64;
17034 target_flags &= ~MASK_FLOAT64;
17037 /* End of code shared with GAS. */
17039 /* The R5900 FPU only supports single precision. */
17040 if (TARGET_MIPS5900 && TARGET_HARD_FLOAT_ABI && TARGET_DOUBLE_FLOAT)
17041 error ("unsupported combination: %s",
17042 "-march=r5900 -mhard-float -mdouble-float");
17044 /* If a -mlong* option was given, check that it matches the ABI,
17045 otherwise infer the -mlong* setting from the other options. */
17046 if ((target_flags_explicit & MASK_LONG64) != 0)
17050 if (mips_abi == ABI_N32)
17051 error ("%qs is incompatible with %qs", "-mabi=n32", "-mlong64");
17052 else if (mips_abi == ABI_32)
17053 error ("%qs is incompatible with %qs", "-mabi=32", "-mlong64");
17054 else if (mips_abi == ABI_O64 && TARGET_ABICALLS)
17055 /* We have traditionally allowed non-abicalls code to use
17056 an LP64 form of o64. However, it would take a bit more
17057 effort to support the combination of 32-bit GOT entries
17058 and 64-bit pointers, so we treat the abicalls case as
17060 error ("the combination of %qs and %qs is incompatible with %qs",
17061 "-mabi=o64", "-mabicalls", "-mlong64");
17065 if (mips_abi == ABI_64)
17066 error ("%qs is incompatible with %qs", "-mabi=64", "-mlong32");
17071 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
17072 target_flags |= MASK_LONG64;
17074 target_flags &= ~MASK_LONG64;
17077 if (!TARGET_OLDABI)
17078 flag_pcc_struct_return = 0;
17080 /* Decide which rtx_costs structure to use. */
17082 mips_cost = &mips_rtx_cost_optimize_size;
17084 mips_cost = &mips_rtx_cost_data[mips_tune];
17086 /* If the user hasn't specified a branch cost, use the processor's
17088 if (mips_branch_cost == 0)
17089 mips_branch_cost = mips_cost->branch_cost;
17091 /* If neither -mbranch-likely nor -mno-branch-likely was given
17092 on the command line, set MASK_BRANCHLIKELY based on the target
17093 architecture and tuning flags. Annulled delay slots are a
17094 size win, so we only consider the processor-specific tuning
17095 for !optimize_size. */
17096 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
17098 if (ISA_HAS_BRANCHLIKELY
17100 || (mips_tune_info->tune_flags & PTF_AVOID_BRANCHLIKELY) == 0))
17101 target_flags |= MASK_BRANCHLIKELY;
17103 target_flags &= ~MASK_BRANCHLIKELY;
17105 else if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
17106 warning (0, "the %qs architecture does not support branch-likely"
17107 " instructions", mips_arch_info->name);
17109 /* If the user hasn't specified -mimadd or -mno-imadd set
17110 MASK_IMADD based on the target architecture and tuning
17112 if ((target_flags_explicit & MASK_IMADD) == 0)
17114 if (ISA_HAS_MADD_MSUB &&
17115 (mips_tune_info->tune_flags & PTF_AVOID_IMADD) == 0)
17116 target_flags |= MASK_IMADD;
17118 target_flags &= ~MASK_IMADD;
17120 else if (TARGET_IMADD && !ISA_HAS_MADD_MSUB)
17121 warning (0, "the %qs architecture does not support madd or msub"
17122 " instructions", mips_arch_info->name);
17124 /* The effect of -mabicalls isn't defined for the EABI. */
17125 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
17127 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
17128 target_flags &= ~MASK_ABICALLS;
17131 /* PIC requires -mabicalls. */
17134 if (mips_abi == ABI_EABI)
17135 error ("cannot generate position-independent code for %qs",
17137 else if (!TARGET_ABICALLS)
17138 error ("position-independent code requires %qs", "-mabicalls");
17141 if (TARGET_ABICALLS_PIC2)
17142 /* We need to set flag_pic for executables as well as DSOs
17143 because we may reference symbols that are not defined in
17144 the final executable. (MIPS does not use things like
17145 copy relocs, for example.)
17147 There is a body of code that uses __PIC__ to distinguish
17148 between -mabicalls and -mno-abicalls code. The non-__PIC__
17149 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
17150 long as any indirect jumps use $25. */
17153 /* -mvr4130-align is a "speed over size" optimization: it usually produces
17154 faster code, but at the expense of more nops. Enable it at -O3 and
17156 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
17157 target_flags |= MASK_VR4130_ALIGN;
17159 /* Prefer a call to memcpy over inline code when optimizing for size,
17160 though see MOVE_RATIO in mips.h. */
17161 if (optimize_size && (target_flags_explicit & MASK_MEMCPY) == 0)
17162 target_flags |= MASK_MEMCPY;
17164 /* If we have a nonzero small-data limit, check that the -mgpopt
17165 setting is consistent with the other target flags. */
17166 if (mips_small_data_threshold > 0)
17170 if (!TARGET_EXPLICIT_RELOCS)
17171 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
17173 TARGET_LOCAL_SDATA = false;
17174 TARGET_EXTERN_SDATA = false;
17178 if (TARGET_VXWORKS_RTP)
17179 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
17181 if (TARGET_ABICALLS)
17182 warning (0, "cannot use small-data accesses for %qs",
17187 /* Pre-IEEE 754-2008 MIPS hardware has a quirky almost-IEEE format
17188 for all its floating point. */
17189 if (mips_nan != MIPS_IEEE_754_2008)
17191 REAL_MODE_FORMAT (SFmode) = &mips_single_format;
17192 REAL_MODE_FORMAT (DFmode) = &mips_double_format;
17193 REAL_MODE_FORMAT (TFmode) = &mips_quad_format;
17196 /* Make sure that the user didn't turn off paired single support when
17197 MIPS-3D support is requested. */
17199 && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
17200 && !TARGET_PAIRED_SINGLE_FLOAT)
17201 error ("%<-mips3d%> requires %<-mpaired-single%>");
17203 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
17205 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
17207 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
17208 and TARGET_HARD_FLOAT_ABI are both true. */
17209 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT_ABI))
17211 error ("%qs must be used with %qs",
17212 TARGET_MIPS3D ? "-mips3d" : "-mpaired-single",
17213 TARGET_HARD_FLOAT_ABI ? "-mfp64" : "-mhard-float");
17214 target_flags &= ~MASK_PAIRED_SINGLE_FLOAT;
17218 /* Make sure that -mpaired-single is only used on ISAs that support it.
17219 We must disable it otherwise since it relies on other ISA properties
17220 like ISA_HAS_8CC having their normal values. */
17221 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_HAS_PAIRED_SINGLE)
17223 error ("the %qs architecture does not support paired-single"
17224 " instructions", mips_arch_info->name);
17225 target_flags &= ~MASK_PAIRED_SINGLE_FLOAT;
17229 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
17230 && !TARGET_CACHE_BUILTIN)
17232 error ("%qs requires a target that provides the %qs instruction",
17233 "-mr10k-cache-barrier", "cache");
17234 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE;
17237 /* If TARGET_DSPR2, enable TARGET_DSP. */
17241 /* .eh_frame addresses should be the same width as a C pointer.
17242 Most MIPS ABIs support only one pointer size, so the assembler
17243 will usually know exactly how big an .eh_frame address is.
17245 Unfortunately, this is not true of the 64-bit EABI. The ABI was
17246 originally defined to use 64-bit pointers (i.e. it is LP64), and
17247 this is still the default mode. However, we also support an n32-like
17248 ILP32 mode, which is selected by -mlong32. The problem is that the
17249 assembler has traditionally not had an -mlong option, so it has
17250 traditionally not known whether we're using the ILP32 or LP64 form.
17252 As it happens, gas versions up to and including 2.19 use _32-bit_
17253 addresses for EABI64 .cfi_* directives. This is wrong for the
17254 default LP64 mode, so we can't use the directives by default.
17255 Moreover, since gas's current behavior is at odds with gcc's
17256 default behavior, it seems unwise to rely on future versions
17257 of gas behaving the same way. We therefore avoid using .cfi
17258 directives for -mlong32 as well. */
17259 if (mips_abi == ABI_EABI && TARGET_64BIT)
17260 flag_dwarf2_cfi_asm = 0;
17262 /* .cfi_* directives generate a read-only section, so fall back on
17263 manual .eh_frame creation if we need the section to be writable. */
17264 if (TARGET_WRITABLE_EH_FRAME)
17265 flag_dwarf2_cfi_asm = 0;
17267 mips_init_print_operand_punct ();
17269 /* Set up array to map GCC register number to debug register number.
17270 Ignore the special purpose register numbers. */
17272 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
17274 mips_dbx_regno[i] = IGNORED_DWARF_REGNUM;
17275 if (GP_REG_P (i) || FP_REG_P (i) || ALL_COP_REG_P (i))
17276 mips_dwarf_regno[i] = i;
17278 mips_dwarf_regno[i] = INVALID_REGNUM;
17281 start = GP_DBX_FIRST - GP_REG_FIRST;
17282 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
17283 mips_dbx_regno[i] = i + start;
17285 start = FP_DBX_FIRST - FP_REG_FIRST;
17286 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
17287 mips_dbx_regno[i] = i + start;
17289 /* Accumulator debug registers use big-endian ordering. */
17290 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
17291 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
17292 mips_dwarf_regno[HI_REGNUM] = MD_REG_FIRST + 0;
17293 mips_dwarf_regno[LO_REGNUM] = MD_REG_FIRST + 1;
17294 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
17296 mips_dwarf_regno[i + TARGET_LITTLE_ENDIAN] = i;
17297 mips_dwarf_regno[i + TARGET_BIG_ENDIAN] = i + 1;
17300 /* Set up mips_hard_regno_mode_ok. */
17301 for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
17302 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
17303 mips_hard_regno_mode_ok[mode][regno]
17304 = mips_hard_regno_mode_ok_p (regno, (enum machine_mode) mode);
17306 /* Function to allocate machine-dependent function status. */
17307 init_machine_status = &mips_init_machine_status;
17309 /* Default to working around R4000 errata only if the processor
17310 was selected explicitly. */
17311 if ((target_flags_explicit & MASK_FIX_R4000) == 0
17312 && strcmp (mips_arch_info->name, "r4000") == 0)
17313 target_flags |= MASK_FIX_R4000;
17315 /* Default to working around R4400 errata only if the processor
17316 was selected explicitly. */
17317 if ((target_flags_explicit & MASK_FIX_R4400) == 0
17318 && strcmp (mips_arch_info->name, "r4400") == 0)
17319 target_flags |= MASK_FIX_R4400;
17321 /* Default to working around R10000 errata only if the processor
17322 was selected explicitly. */
17323 if ((target_flags_explicit & MASK_FIX_R10000) == 0
17324 && strcmp (mips_arch_info->name, "r10000") == 0)
17325 target_flags |= MASK_FIX_R10000;
17327 /* Make sure that branch-likely instructions available when using
17328 -mfix-r10000. The instructions are not available if either:
17330 1. -mno-branch-likely was passed.
17331 2. The selected ISA does not support branch-likely and
17332 the command line does not include -mbranch-likely. */
17333 if (TARGET_FIX_R10000
17334 && ((target_flags_explicit & MASK_BRANCHLIKELY) == 0
17335 ? !ISA_HAS_BRANCHLIKELY
17336 : !TARGET_BRANCHLIKELY))
17337 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
17339 if (TARGET_SYNCI && !ISA_HAS_SYNCI)
17341 warning (0, "the %qs architecture does not support the synci "
17342 "instruction", mips_arch_info->name);
17343 target_flags &= ~MASK_SYNCI;
17346 /* Only optimize PIC indirect calls if they are actually required. */
17347 if (!TARGET_USE_GOT || !TARGET_EXPLICIT_RELOCS)
17348 target_flags &= ~MASK_RELAX_PIC_CALLS;
17350 /* Save base state of options. */
17351 mips_base_target_flags = target_flags;
17352 mips_base_schedule_insns = flag_schedule_insns;
17353 mips_base_reorder_blocks_and_partition = flag_reorder_blocks_and_partition;
17354 mips_base_move_loop_invariants = flag_move_loop_invariants;
17355 mips_base_align_loops = align_loops;
17356 mips_base_align_jumps = align_jumps;
17357 mips_base_align_functions = align_functions;
17359 /* Now select the ISA mode.
17361 Do all CPP-sensitive stuff in uncompressed mode; we'll switch modes
17362 later if required. */
17363 mips_set_compression_mode (0);
17365 /* We register a second machine specific reorg pass after delay slot
17366 filling. Registering the pass must be done at start up. It's
17367 convenient to do it here. */
17368 opt_pass *new_pass = make_pass_mips_machine_reorg2 (g);
17369 struct register_pass_info insert_pass_mips_machine_reorg2 =
17371 new_pass, /* pass */
17372 "dbr", /* reference_pass_name */
17373 1, /* ref_pass_instance_number */
17374 PASS_POS_INSERT_AFTER /* po_op */
17376 register_pass (&insert_pass_mips_machine_reorg2);
17378 if (TARGET_HARD_FLOAT_ABI && TARGET_MIPS5900)
17379 REAL_MODE_FORMAT (SFmode) = &spu_single_format;
17382 /* Swap the register information for registers I and I + 1, which
17383 currently have the wrong endianness. Note that the registers'
17384 fixedness and call-clobberedness might have been set on the
17388 mips_swap_registers (unsigned int i)
17393 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
17394 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
17396 SWAP_INT (fixed_regs[i], fixed_regs[i + 1]);
17397 SWAP_INT (call_used_regs[i], call_used_regs[i + 1]);
17398 SWAP_INT (call_really_used_regs[i], call_really_used_regs[i + 1]);
17399 SWAP_STRING (reg_names[i], reg_names[i + 1]);
17405 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
17408 mips_conditional_register_usage (void)
17413 /* These DSP control register fields are global. */
17414 global_regs[CCDSP_PO_REGNUM] = 1;
17415 global_regs[CCDSP_SC_REGNUM] = 1;
17418 AND_COMPL_HARD_REG_SET (accessible_reg_set,
17419 reg_class_contents[(int) DSP_ACC_REGS]);
17421 if (!TARGET_HARD_FLOAT)
17423 AND_COMPL_HARD_REG_SET (accessible_reg_set,
17424 reg_class_contents[(int) FP_REGS]);
17425 AND_COMPL_HARD_REG_SET (accessible_reg_set,
17426 reg_class_contents[(int) ST_REGS]);
17428 else if (!ISA_HAS_8CC)
17430 /* We only have a single condition-code register. We implement
17431 this by fixing all the condition-code registers and generating
17432 RTL that refers directly to ST_REG_FIRST. */
17433 AND_COMPL_HARD_REG_SET (accessible_reg_set,
17434 reg_class_contents[(int) ST_REGS]);
17435 SET_HARD_REG_BIT (accessible_reg_set, FPSW_REGNUM);
17436 fixed_regs[FPSW_REGNUM] = call_used_regs[FPSW_REGNUM] = 1;
17440 /* In MIPS16 mode, we prohibit the unused $s registers, since they
17441 are call-saved, and saving them via a MIPS16 register would
17442 probably waste more time than just reloading the value.
17444 We permit the $t temporary registers when optimizing for speed
17445 but not when optimizing for space because using them results in
17446 code that is larger (but faster) then not using them. We do
17447 allow $24 (t8) because it is used in CMP and CMPI instructions
17448 and $25 (t9) because it is used as the function call address in
17451 fixed_regs[18] = call_used_regs[18] = 1;
17452 fixed_regs[19] = call_used_regs[19] = 1;
17453 fixed_regs[20] = call_used_regs[20] = 1;
17454 fixed_regs[21] = call_used_regs[21] = 1;
17455 fixed_regs[22] = call_used_regs[22] = 1;
17456 fixed_regs[23] = call_used_regs[23] = 1;
17457 fixed_regs[26] = call_used_regs[26] = 1;
17458 fixed_regs[27] = call_used_regs[27] = 1;
17459 fixed_regs[30] = call_used_regs[30] = 1;
17462 fixed_regs[8] = call_used_regs[8] = 1;
17463 fixed_regs[9] = call_used_regs[9] = 1;
17464 fixed_regs[10] = call_used_regs[10] = 1;
17465 fixed_regs[11] = call_used_regs[11] = 1;
17466 fixed_regs[12] = call_used_regs[12] = 1;
17467 fixed_regs[13] = call_used_regs[13] = 1;
17468 fixed_regs[14] = call_used_regs[14] = 1;
17469 fixed_regs[15] = call_used_regs[15] = 1;
17472 /* Do not allow HI and LO to be treated as register operands.
17473 There are no MTHI or MTLO instructions (or any real need
17474 for them) and one-way registers cannot easily be reloaded. */
17475 AND_COMPL_HARD_REG_SET (operand_reg_set,
17476 reg_class_contents[(int) MD_REGS]);
17478 /* $f20-$f23 are call-clobbered for n64. */
17479 if (mips_abi == ABI_64)
17482 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
17483 call_really_used_regs[regno] = call_used_regs[regno] = 1;
17485 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
17487 if (mips_abi == ABI_N32)
17490 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
17491 call_really_used_regs[regno] = call_used_regs[regno] = 1;
17493 /* Make sure that double-register accumulator values are correctly
17494 ordered for the current endianness. */
17495 if (TARGET_LITTLE_ENDIAN)
17497 unsigned int regno;
17499 mips_swap_registers (MD_REG_FIRST);
17500 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno += 2)
17501 mips_swap_registers (regno);
17505 /* When generating MIPS16 code, we want to allocate $24 (T_REG) before
17506 other registers for instructions for which it is possible. This
17507 encourages the compiler to use CMP in cases where an XOR would
17508 require some register shuffling. */
17511 mips_order_regs_for_local_alloc (void)
17515 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
17516 reg_alloc_order[i] = i;
17520 /* It really doesn't matter where we put register 0, since it is
17521 a fixed register anyhow. */
17522 reg_alloc_order[0] = 24;
17523 reg_alloc_order[24] = 0;
17527 /* Implement EH_USES. */
17530 mips_eh_uses (unsigned int regno)
17532 if (reload_completed && !TARGET_ABSOLUTE_JUMPS)
17534 /* We need to force certain registers to be live in order to handle
17535 PIC long branches correctly. See mips_must_initialize_gp_p for
17537 if (mips_cfun_has_cprestore_slot_p ())
17539 if (regno == CPRESTORE_SLOT_REGNUM)
17544 if (cfun->machine->global_pointer == regno)
17552 /* Implement EPILOGUE_USES. */
17555 mips_epilogue_uses (unsigned int regno)
17557 /* Say that the epilogue uses the return address register. Note that
17558 in the case of sibcalls, the values "used by the epilogue" are
17559 considered live at the start of the called function. */
17560 if (regno == RETURN_ADDR_REGNUM)
17563 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
17564 See the comment above load_call<mode> for details. */
17565 if (TARGET_USE_GOT && (regno) == GOT_VERSION_REGNUM)
17568 /* An interrupt handler must preserve some registers that are
17569 ordinarily call-clobbered. */
17570 if (cfun->machine->interrupt_handler_p
17571 && mips_interrupt_extra_call_saved_reg_p (regno))
17577 /* A for_each_rtx callback. Stop the search if *X is an AT register. */
17580 mips_at_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
17582 return REG_P (*x) && REGNO (*x) == AT_REGNUM;
17585 /* Return true if INSN needs to be wrapped in ".set noat".
17586 INSN has NOPERANDS operands, stored in OPVEC. */
17589 mips_need_noat_wrapper_p (rtx insn, rtx *opvec, int noperands)
17593 if (recog_memoized (insn) >= 0)
17594 for (i = 0; i < noperands; i++)
17595 if (for_each_rtx (&opvec[i], mips_at_reg_p, NULL))
17600 /* Implement FINAL_PRESCAN_INSN. */
17603 mips_final_prescan_insn (rtx insn, rtx *opvec, int noperands)
17605 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
17606 mips_push_asm_switch (&mips_noat);
17609 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */
17612 mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED, rtx insn,
17613 rtx *opvec, int noperands)
17615 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
17616 mips_pop_asm_switch (&mips_noat);
17619 /* Return the function that is used to expand the <u>mulsidi3 pattern.
17620 EXT_CODE is the code of the extension used. Return NULL if widening
17621 multiplication shouldn't be used. */
17624 mips_mulsidi3_gen_fn (enum rtx_code ext_code)
17628 signed_p = ext_code == SIGN_EXTEND;
17631 /* Don't use widening multiplication with MULT when we have DMUL. Even
17632 with the extension of its input operands DMUL is faster. Note that
17633 the extension is not needed for signed multiplication. In order to
17634 ensure that we always remove the redundant sign-extension in this
17635 case we still expand mulsidi3 for DMUL. */
17637 return signed_p ? gen_mulsidi3_64bit_dmul : NULL;
17640 ? gen_mulsidi3_64bit_mips16
17641 : gen_umulsidi3_64bit_mips16);
17642 if (TARGET_FIX_R4000)
17644 return signed_p ? gen_mulsidi3_64bit : gen_umulsidi3_64bit;
17650 ? gen_mulsidi3_32bit_mips16
17651 : gen_umulsidi3_32bit_mips16);
17652 if (TARGET_FIX_R4000 && !ISA_HAS_DSP)
17653 return signed_p ? gen_mulsidi3_32bit_r4000 : gen_umulsidi3_32bit_r4000;
17654 return signed_p ? gen_mulsidi3_32bit : gen_umulsidi3_32bit;
17658 /* Return true if PATTERN matches the kind of instruction generated by
17659 umips_build_save_restore. SAVE_P is true for store. */
17662 umips_save_restore_pattern_p (bool save_p, rtx pattern)
17666 HOST_WIDE_INT first_offset = 0;
17667 rtx first_base = 0;
17668 unsigned int regmask = 0;
17670 for (n = 0; n < XVECLEN (pattern, 0); n++)
17672 rtx set, reg, mem, this_base;
17673 HOST_WIDE_INT this_offset;
17675 /* Check that we have a SET. */
17676 set = XVECEXP (pattern, 0, n);
17677 if (GET_CODE (set) != SET)
17680 /* Check that the SET is a load (if restoring) or a store
17682 mem = save_p ? SET_DEST (set) : SET_SRC (set);
17683 if (!MEM_P (mem) || MEM_VOLATILE_P (mem))
17686 /* Check that the address is the sum of base and a possibly-zero
17687 constant offset. Determine if the offset is in range. */
17688 mips_split_plus (XEXP (mem, 0), &this_base, &this_offset);
17689 if (!REG_P (this_base))
17694 if (!UMIPS_12BIT_OFFSET_P (this_offset))
17696 first_base = this_base;
17697 first_offset = this_offset;
17701 /* Check that the save slots are consecutive. */
17702 if (REGNO (this_base) != REGNO (first_base)
17703 || this_offset != first_offset + UNITS_PER_WORD * n)
17707 /* Check that SET's other operand is a register. */
17708 reg = save_p ? SET_SRC (set) : SET_DEST (set);
17712 regmask |= 1 << REGNO (reg);
17715 for (i = 0; i < ARRAY_SIZE (umips_swm_mask); i++)
17716 if (regmask == umips_swm_mask[i])
17722 /* Return the assembly instruction for microMIPS LWM or SWM.
17723 SAVE_P and PATTERN are as for umips_save_restore_pattern_p. */
17726 umips_output_save_restore (bool save_p, rtx pattern)
17728 static char buffer[300];
17731 HOST_WIDE_INT offset;
17732 rtx base, mem, set, last_set, last_reg;
17734 /* Parse the pattern. */
17735 gcc_assert (umips_save_restore_pattern_p (save_p, pattern));
17737 s = strcpy (buffer, save_p ? "swm\t" : "lwm\t");
17739 n = XVECLEN (pattern, 0);
17741 set = XVECEXP (pattern, 0, 0);
17742 mem = save_p ? SET_DEST (set) : SET_SRC (set);
17743 mips_split_plus (XEXP (mem, 0), &base, &offset);
17745 last_set = XVECEXP (pattern, 0, n - 1);
17746 last_reg = save_p ? SET_SRC (last_set) : SET_DEST (last_set);
17748 if (REGNO (last_reg) == 31)
17751 gcc_assert (n <= 9);
17755 s += sprintf (s, "%s,", reg_names[16]);
17757 s += sprintf (s, "%s-%s,", reg_names[16], reg_names[15 + n]);
17759 s += sprintf (s, "%s-%s,%s,", reg_names[16], reg_names[23],
17762 if (REGNO (last_reg) == 31)
17763 s += sprintf (s, "%s,", reg_names[31]);
17765 s += sprintf (s, "%d(%s)", (int)offset, reg_names[REGNO (base)]);
17769 /* Return true if MEM1 and MEM2 use the same base register, and the
17770 offset of MEM2 equals the offset of MEM1 plus 4. FIRST_REG is the
17771 register into (from) which the contents of MEM1 will be loaded
17772 (stored), depending on the value of LOAD_P.
17773 SWAP_P is true when the 1st and 2nd instructions are swapped. */
17776 umips_load_store_pair_p_1 (bool load_p, bool swap_p,
17777 rtx first_reg, rtx mem1, rtx mem2)
17780 HOST_WIDE_INT offset1, offset2;
17782 if (!MEM_P (mem1) || !MEM_P (mem2))
17785 mips_split_plus (XEXP (mem1, 0), &base1, &offset1);
17786 mips_split_plus (XEXP (mem2, 0), &base2, &offset2);
17788 if (!REG_P (base1) || !rtx_equal_p (base1, base2))
17791 /* Avoid invalid load pair instructions. */
17792 if (load_p && REGNO (first_reg) == REGNO (base1))
17795 /* We must avoid this case for anti-dependence.
17798 first_reg is $2, but the base is $3. */
17801 && REGNO (first_reg) + 1 == REGNO (base1))
17804 if (offset2 != offset1 + 4)
17807 if (!UMIPS_12BIT_OFFSET_P (offset1))
17813 /* OPERANDS describes the operands to a pair of SETs, in the order
17814 dest1, src1, dest2, src2. Return true if the operands can be used
17815 in an LWP or SWP instruction; LOAD_P says which. */
17818 umips_load_store_pair_p (bool load_p, rtx *operands)
17820 rtx reg1, reg2, mem1, mem2;
17824 reg1 = operands[0];
17825 reg2 = operands[2];
17826 mem1 = operands[1];
17827 mem2 = operands[3];
17831 reg1 = operands[1];
17832 reg2 = operands[3];
17833 mem1 = operands[0];
17834 mem2 = operands[2];
17837 if (REGNO (reg2) == REGNO (reg1) + 1)
17838 return umips_load_store_pair_p_1 (load_p, false, reg1, mem1, mem2);
17840 if (REGNO (reg1) == REGNO (reg2) + 1)
17841 return umips_load_store_pair_p_1 (load_p, true, reg2, mem2, mem1);
17846 /* Return the assembly instruction for a microMIPS LWP or SWP in which
17847 the first register is REG and the first memory slot is MEM.
17848 LOAD_P is true for LWP. */
17851 umips_output_load_store_pair_1 (bool load_p, rtx reg, rtx mem)
17853 rtx ops[] = {reg, mem};
17856 output_asm_insn ("lwp\t%0,%1", ops);
17858 output_asm_insn ("swp\t%0,%1", ops);
17861 /* Output the assembly instruction for a microMIPS LWP or SWP instruction.
17862 LOAD_P and OPERANDS are as for umips_load_store_pair_p. */
17865 umips_output_load_store_pair (bool load_p, rtx *operands)
17867 rtx reg1, reg2, mem1, mem2;
17870 reg1 = operands[0];
17871 reg2 = operands[2];
17872 mem1 = operands[1];
17873 mem2 = operands[3];
17877 reg1 = operands[1];
17878 reg2 = operands[3];
17879 mem1 = operands[0];
17880 mem2 = operands[2];
17883 if (REGNO (reg2) == REGNO (reg1) + 1)
17885 umips_output_load_store_pair_1 (load_p, reg1, mem1);
17889 gcc_assert (REGNO (reg1) == REGNO (reg2) + 1);
17890 umips_output_load_store_pair_1 (load_p, reg2, mem2);
17893 /* Return true if REG1 and REG2 match the criteria for a movep insn. */
17896 umips_movep_target_p (rtx reg1, rtx reg2)
17898 int regno1, regno2, pair;
17900 static const int match[8] = {
17901 0x00000060, /* 5, 6 */
17902 0x000000a0, /* 5, 7 */
17903 0x000000c0, /* 6, 7 */
17904 0x00200010, /* 4, 21 */
17905 0x00400010, /* 4, 22 */
17906 0x00000030, /* 4, 5 */
17907 0x00000050, /* 4, 6 */
17908 0x00000090 /* 4, 7 */
17911 if (!REG_P (reg1) || !REG_P (reg2))
17914 regno1 = REGNO (reg1);
17915 regno2 = REGNO (reg2);
17917 if (!GP_REG_P (regno1) || !GP_REG_P (regno2))
17920 pair = (1 << regno1) | (1 << regno2);
17922 for (i = 0; i < ARRAY_SIZE (match); i++)
17923 if (pair == match[i])
17929 /* Return the size in bytes of the trampoline code, padded to
17930 TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target
17931 function address immediately follow. */
17934 mips_trampoline_code_size (void)
17936 if (TARGET_USE_PIC_FN_ADDR_REG)
17938 else if (ptr_mode == DImode)
17940 else if (ISA_HAS_LOAD_DELAY)
17946 /* Implement TARGET_TRAMPOLINE_INIT. */
17949 mips_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
17951 rtx addr, end_addr, high, low, opcode, mem;
17954 HOST_WIDE_INT end_addr_offset, static_chain_offset, target_function_offset;
17956 /* Work out the offsets of the pointers from the start of the
17957 trampoline code. */
17958 end_addr_offset = mips_trampoline_code_size ();
17959 static_chain_offset = end_addr_offset;
17960 target_function_offset = static_chain_offset + GET_MODE_SIZE (ptr_mode);
17962 /* Get pointers to the beginning and end of the code block. */
17963 addr = force_reg (Pmode, XEXP (m_tramp, 0));
17964 end_addr = mips_force_binary (Pmode, PLUS, addr, GEN_INT (end_addr_offset));
17966 #define OP(X) gen_int_mode (X, SImode)
17968 /* Build up the code in TRAMPOLINE. */
17970 if (TARGET_USE_PIC_FN_ADDR_REG)
17972 /* $25 contains the address of the trampoline. Emit code of the form:
17974 l[wd] $1, target_function_offset($25)
17975 l[wd] $static_chain, static_chain_offset($25)
17978 trampoline[i++] = OP (MIPS_LOAD_PTR (AT_REGNUM,
17979 target_function_offset,
17980 PIC_FUNCTION_ADDR_REGNUM));
17981 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
17982 static_chain_offset,
17983 PIC_FUNCTION_ADDR_REGNUM));
17984 trampoline[i++] = OP (MIPS_JR (AT_REGNUM));
17985 trampoline[i++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM, AT_REGNUM));
17987 else if (ptr_mode == DImode)
17989 /* It's too cumbersome to create the full 64-bit address, so let's
17995 1: l[wd] $25, target_function_offset - 12($31)
17996 l[wd] $static_chain, static_chain_offset - 12($31)
18000 where 12 is the offset of "1:" from the start of the code block. */
18001 trampoline[i++] = OP (MIPS_MOVE (AT_REGNUM, RETURN_ADDR_REGNUM));
18002 trampoline[i++] = OP (MIPS_BAL (1));
18003 trampoline[i++] = OP (MIPS_NOP);
18004 trampoline[i++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
18005 target_function_offset - 12,
18006 RETURN_ADDR_REGNUM));
18007 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
18008 static_chain_offset - 12,
18009 RETURN_ADDR_REGNUM));
18010 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
18011 trampoline[i++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM, AT_REGNUM));
18015 /* If the target has load delays, emit:
18017 lui $1, %hi(end_addr)
18018 lw $25, %lo(end_addr + ...)($1)
18019 lw $static_chain, %lo(end_addr + ...)($1)
18025 lui $1, %hi(end_addr)
18026 lw $25, %lo(end_addr + ...)($1)
18028 lw $static_chain, %lo(end_addr + ...)($1). */
18030 /* Split END_ADDR into %hi and %lo values. Trampolines are aligned
18031 to 64 bits, so the %lo value will have the bottom 3 bits clear. */
18032 high = expand_simple_binop (SImode, PLUS, end_addr, GEN_INT (0x8000),
18033 NULL, false, OPTAB_WIDEN);
18034 high = expand_simple_binop (SImode, LSHIFTRT, high, GEN_INT (16),
18035 NULL, false, OPTAB_WIDEN);
18036 low = convert_to_mode (SImode, gen_lowpart (HImode, end_addr), true);
18038 /* Emit the LUI. */
18039 opcode = OP (MIPS_LUI (AT_REGNUM, 0));
18040 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, high,
18041 NULL, false, OPTAB_WIDEN);
18043 /* Emit the load of the target function. */
18044 opcode = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
18045 target_function_offset - end_addr_offset,
18047 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
18048 NULL, false, OPTAB_WIDEN);
18050 /* Emit the JR here, if we can. */
18051 if (!ISA_HAS_LOAD_DELAY)
18052 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
18054 /* Emit the load of the static chain register. */
18055 opcode = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
18056 static_chain_offset - end_addr_offset,
18058 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
18059 NULL, false, OPTAB_WIDEN);
18061 /* Emit the JR, if we couldn't above. */
18062 if (ISA_HAS_LOAD_DELAY)
18064 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
18065 trampoline[i++] = OP (MIPS_NOP);
18071 /* Copy the trampoline code. Leave any padding uninitialized. */
18072 for (j = 0; j < i; j++)
18074 mem = adjust_address (m_tramp, SImode, j * GET_MODE_SIZE (SImode));
18075 mips_emit_move (mem, trampoline[j]);
18078 /* Set up the static chain pointer field. */
18079 mem = adjust_address (m_tramp, ptr_mode, static_chain_offset);
18080 mips_emit_move (mem, chain_value);
18082 /* Set up the target function field. */
18083 mem = adjust_address (m_tramp, ptr_mode, target_function_offset);
18084 mips_emit_move (mem, XEXP (DECL_RTL (fndecl), 0));
18086 /* Flush the code part of the trampoline. */
18087 emit_insn (gen_add3_insn (end_addr, addr, GEN_INT (TRAMPOLINE_SIZE)));
18088 emit_insn (gen_clear_cache (addr, end_addr));
18091 /* Implement FUNCTION_PROFILER. */
18093 void mips_function_profiler (FILE *file)
18096 sorry ("mips16 function profiling");
18097 if (TARGET_LONG_CALLS)
18099 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */
18100 if (Pmode == DImode)
18101 fprintf (file, "\tdla\t%s,_mcount\n", reg_names[3]);
18103 fprintf (file, "\tla\t%s,_mcount\n", reg_names[3]);
18105 mips_push_asm_switch (&mips_noat);
18106 fprintf (file, "\tmove\t%s,%s\t\t# save current return address\n",
18107 reg_names[AT_REGNUM], reg_names[RETURN_ADDR_REGNUM]);
18108 /* _mcount treats $2 as the static chain register. */
18109 if (cfun->static_chain_decl != NULL)
18110 fprintf (file, "\tmove\t%s,%s\n", reg_names[2],
18111 reg_names[STATIC_CHAIN_REGNUM]);
18112 if (TARGET_MCOUNT_RA_ADDRESS)
18114 /* If TARGET_MCOUNT_RA_ADDRESS load $12 with the address of the
18115 ra save location. */
18116 if (cfun->machine->frame.ra_fp_offset == 0)
18117 /* ra not saved, pass zero. */
18118 fprintf (file, "\tmove\t%s,%s\n", reg_names[12], reg_names[0]);
18120 fprintf (file, "\t%s\t%s," HOST_WIDE_INT_PRINT_DEC "(%s)\n",
18121 Pmode == DImode ? "dla" : "la", reg_names[12],
18122 cfun->machine->frame.ra_fp_offset,
18123 reg_names[STACK_POINTER_REGNUM]);
18125 if (!TARGET_NEWABI)
18127 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n",
18128 TARGET_64BIT ? "dsubu" : "subu",
18129 reg_names[STACK_POINTER_REGNUM],
18130 reg_names[STACK_POINTER_REGNUM],
18131 Pmode == DImode ? 16 : 8);
18133 if (TARGET_LONG_CALLS)
18134 fprintf (file, "\tjalr\t%s\n", reg_names[3]);
18136 fprintf (file, "\tjal\t_mcount\n");
18137 mips_pop_asm_switch (&mips_noat);
18138 /* _mcount treats $2 as the static chain register. */
18139 if (cfun->static_chain_decl != NULL)
18140 fprintf (file, "\tmove\t%s,%s\n", reg_names[STATIC_CHAIN_REGNUM],
18144 /* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default
18145 behaviour of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even
18146 when TARGET_LOONGSON_VECTORS is true. */
18148 static unsigned HOST_WIDE_INT
18149 mips_shift_truncation_mask (enum machine_mode mode)
18151 if (TARGET_LOONGSON_VECTORS && VECTOR_MODE_P (mode))
18154 return GET_MODE_BITSIZE (mode) - 1;
18157 /* Implement TARGET_PREPARE_PCH_SAVE. */
18160 mips_prepare_pch_save (void)
18162 /* We are called in a context where the current MIPS16 vs. non-MIPS16
18163 setting should be irrelevant. The question then is: which setting
18164 makes most sense at load time?
18166 The PCH is loaded before the first token is read. We should never
18167 have switched into MIPS16 mode by that point, and thus should not
18168 have populated mips16_globals. Nor can we load the entire contents
18169 of mips16_globals from the PCH file, because mips16_globals contains
18170 a combination of GGC and non-GGC data.
18172 There is therefore no point in trying save the GGC part of
18173 mips16_globals to the PCH file, or to preserve MIPS16ness across
18174 the PCH save and load. The loading compiler would not have access
18175 to the non-GGC parts of mips16_globals (either from the PCH file,
18176 or from a copy that the loading compiler generated itself) and would
18177 have to call target_reinit anyway.
18179 It therefore seems best to switch back to non-MIPS16 mode at
18180 save time, and to ensure that mips16_globals remains null after
18182 mips_set_compression_mode (0);
18183 mips16_globals = 0;
18186 /* Generate or test for an insn that supports a constant permutation. */
18188 #define MAX_VECT_LEN 8
18190 struct expand_vec_perm_d
18192 rtx target, op0, op1;
18193 unsigned char perm[MAX_VECT_LEN];
18194 enum machine_mode vmode;
18195 unsigned char nelt;
18200 /* Construct (set target (vec_select op0 (parallel perm))) and
18201 return true if that's a valid instruction in the active ISA. */
18204 mips_expand_vselect (rtx target, rtx op0,
18205 const unsigned char *perm, unsigned nelt)
18207 rtx rperm[MAX_VECT_LEN], x;
18210 for (i = 0; i < nelt; ++i)
18211 rperm[i] = GEN_INT (perm[i]);
18213 x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (nelt, rperm));
18214 x = gen_rtx_VEC_SELECT (GET_MODE (target), op0, x);
18215 x = gen_rtx_SET (VOIDmode, target, x);
18218 if (recog_memoized (x) < 0)
18226 /* Similar, but generate a vec_concat from op0 and op1 as well. */
18229 mips_expand_vselect_vconcat (rtx target, rtx op0, rtx op1,
18230 const unsigned char *perm, unsigned nelt)
18232 enum machine_mode v2mode;
18235 v2mode = GET_MODE_2XWIDER_MODE (GET_MODE (op0));
18236 x = gen_rtx_VEC_CONCAT (v2mode, op0, op1);
18237 return mips_expand_vselect (target, x, perm, nelt);
18240 /* Recognize patterns for even-odd extraction. */
18243 mips_expand_vpc_loongson_even_odd (struct expand_vec_perm_d *d)
18245 unsigned i, odd, nelt = d->nelt;
18246 rtx t0, t1, t2, t3;
18248 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
18250 /* Even-odd for V2SI/V2SFmode is matched by interleave directly. */
18257 for (i = 1; i < nelt; ++i)
18258 if (d->perm[i] != i * 2 + odd)
18264 /* We need 2*log2(N)-1 operations to achieve odd/even with interleave. */
18265 t0 = gen_reg_rtx (d->vmode);
18266 t1 = gen_reg_rtx (d->vmode);
18270 emit_insn (gen_loongson_punpckhhw (t0, d->op0, d->op1));
18271 emit_insn (gen_loongson_punpcklhw (t1, d->op0, d->op1));
18273 emit_insn (gen_loongson_punpckhhw (d->target, t1, t0));
18275 emit_insn (gen_loongson_punpcklhw (d->target, t1, t0));
18279 t2 = gen_reg_rtx (d->vmode);
18280 t3 = gen_reg_rtx (d->vmode);
18281 emit_insn (gen_loongson_punpckhbh (t0, d->op0, d->op1));
18282 emit_insn (gen_loongson_punpcklbh (t1, d->op0, d->op1));
18283 emit_insn (gen_loongson_punpckhbh (t2, t1, t0));
18284 emit_insn (gen_loongson_punpcklbh (t3, t1, t0));
18286 emit_insn (gen_loongson_punpckhbh (d->target, t3, t2));
18288 emit_insn (gen_loongson_punpcklbh (d->target, t3, t2));
18292 gcc_unreachable ();
18297 /* Recognize patterns for the Loongson PSHUFH instruction. */
18300 mips_expand_vpc_loongson_pshufh (struct expand_vec_perm_d *d)
18305 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
18307 if (d->vmode != V4HImode)
18312 /* Convert the selector into the packed 8-bit form for pshufh. */
18313 /* Recall that loongson is little-endian only. No big-endian
18314 adjustment required. */
18315 for (i = mask = 0; i < 4; i++)
18316 mask |= (d->perm[i] & 3) << (i * 2);
18317 rmask = force_reg (SImode, GEN_INT (mask));
18319 if (d->one_vector_p)
18320 emit_insn (gen_loongson_pshufh (d->target, d->op0, rmask));
18323 rtx t0, t1, x, merge, rmerge[4];
18325 t0 = gen_reg_rtx (V4HImode);
18326 t1 = gen_reg_rtx (V4HImode);
18327 emit_insn (gen_loongson_pshufh (t1, d->op1, rmask));
18328 emit_insn (gen_loongson_pshufh (t0, d->op0, rmask));
18330 for (i = 0; i < 4; ++i)
18331 rmerge[i] = (d->perm[i] & 4 ? constm1_rtx : const0_rtx);
18332 merge = gen_rtx_CONST_VECTOR (V4HImode, gen_rtvec_v (4, rmerge));
18333 merge = force_reg (V4HImode, merge);
18335 x = gen_rtx_AND (V4HImode, merge, t1);
18336 emit_insn (gen_rtx_SET (VOIDmode, t1, x));
18338 x = gen_rtx_NOT (V4HImode, merge);
18339 x = gen_rtx_AND (V4HImode, x, t0);
18340 emit_insn (gen_rtx_SET (VOIDmode, t0, x));
18342 x = gen_rtx_IOR (V4HImode, t0, t1);
18343 emit_insn (gen_rtx_SET (VOIDmode, d->target, x));
18349 /* Recognize broadcast patterns for the Loongson. */
18352 mips_expand_vpc_loongson_bcast (struct expand_vec_perm_d *d)
18357 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
18359 /* Note that we've already matched V2SI via punpck and V4HI via pshufh. */
18360 if (d->vmode != V8QImode)
18362 if (!d->one_vector_p)
18366 for (i = 1; i < 8; ++i)
18367 if (d->perm[i] != elt)
18373 /* With one interleave we put two of the desired element adjacent. */
18374 t0 = gen_reg_rtx (V8QImode);
18376 emit_insn (gen_loongson_punpcklbh (t0, d->op0, d->op0));
18378 emit_insn (gen_loongson_punpckhbh (t0, d->op0, d->op0));
18380 /* Shuffle that one HImode element into all locations. */
18383 t1 = gen_reg_rtx (V4HImode);
18384 emit_insn (gen_loongson_pshufh (t1, gen_lowpart (V4HImode, t0),
18385 force_reg (SImode, GEN_INT (elt))));
18387 emit_move_insn (d->target, gen_lowpart (V8QImode, t1));
18392 mips_expand_vec_perm_const_1 (struct expand_vec_perm_d *d)
18394 unsigned int i, nelt = d->nelt;
18395 unsigned char perm2[MAX_VECT_LEN];
18397 if (d->one_vector_p)
18399 /* Try interleave with alternating operands. */
18400 memcpy (perm2, d->perm, sizeof(perm2));
18401 for (i = 1; i < nelt; i += 2)
18403 if (mips_expand_vselect_vconcat (d->target, d->op0, d->op1, perm2, nelt))
18408 if (mips_expand_vselect_vconcat (d->target, d->op0, d->op1,
18412 /* Try again with swapped operands. */
18413 for (i = 0; i < nelt; ++i)
18414 perm2[i] = (d->perm[i] + nelt) & (2 * nelt - 1);
18415 if (mips_expand_vselect_vconcat (d->target, d->op1, d->op0, perm2, nelt))
18419 if (mips_expand_vpc_loongson_even_odd (d))
18421 if (mips_expand_vpc_loongson_pshufh (d))
18423 if (mips_expand_vpc_loongson_bcast (d))
18428 /* Expand a vec_perm_const pattern. */
18431 mips_expand_vec_perm_const (rtx operands[4])
18433 struct expand_vec_perm_d d;
18434 int i, nelt, which;
18435 unsigned char orig_perm[MAX_VECT_LEN];
18439 d.target = operands[0];
18440 d.op0 = operands[1];
18441 d.op1 = operands[2];
18444 d.vmode = GET_MODE (d.target);
18445 gcc_assert (VECTOR_MODE_P (d.vmode));
18446 d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
18447 d.testing_p = false;
18449 for (i = which = 0; i < nelt; ++i)
18451 rtx e = XVECEXP (sel, 0, i);
18452 int ei = INTVAL (e) & (2 * nelt - 1);
18453 which |= (ei < nelt ? 1 : 2);
18456 memcpy (d.perm, orig_perm, MAX_VECT_LEN);
18464 d.one_vector_p = false;
18465 if (!rtx_equal_p (d.op0, d.op1))
18470 for (i = 0; i < nelt; ++i)
18471 d.perm[i] &= nelt - 1;
18473 d.one_vector_p = true;
18478 d.one_vector_p = true;
18482 ok = mips_expand_vec_perm_const_1 (&d);
18484 /* If we were given a two-vector permutation which just happened to
18485 have both input vectors equal, we folded this into a one-vector
18486 permutation. There are several loongson patterns that are matched
18487 via direct vec_select+vec_concat expansion, but we do not have
18488 support in mips_expand_vec_perm_const_1 to guess the adjustment
18489 that should be made for a single operand. Just try again with
18490 the original permutation. */
18491 if (!ok && which == 3)
18493 d.op0 = operands[1];
18494 d.op1 = operands[2];
18495 d.one_vector_p = false;
18496 memcpy (d.perm, orig_perm, MAX_VECT_LEN);
18497 ok = mips_expand_vec_perm_const_1 (&d);
18503 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST_OK. */
18506 mips_vectorize_vec_perm_const_ok (enum machine_mode vmode,
18507 const unsigned char *sel)
18509 struct expand_vec_perm_d d;
18510 unsigned int i, nelt, which;
18514 d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
18515 d.testing_p = true;
18516 memcpy (d.perm, sel, nelt);
18518 /* Categorize the set of elements in the selector. */
18519 for (i = which = 0; i < nelt; ++i)
18521 unsigned char e = d.perm[i];
18522 gcc_assert (e < 2 * nelt);
18523 which |= (e < nelt ? 1 : 2);
18526 /* For all elements from second vector, fold the elements to first. */
18528 for (i = 0; i < nelt; ++i)
18531 /* Check whether the mask can be applied to the vector type. */
18532 d.one_vector_p = (which != 3);
18534 d.target = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 1);
18535 d.op1 = d.op0 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 2);
18536 if (!d.one_vector_p)
18537 d.op1 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 3);
18540 ret = mips_expand_vec_perm_const_1 (&d);
18546 /* Expand an integral vector unpack operation. */
18549 mips_expand_vec_unpack (rtx operands[2], bool unsigned_p, bool high_p)
18551 enum machine_mode imode = GET_MODE (operands[1]);
18552 rtx (*unpack) (rtx, rtx, rtx);
18553 rtx (*cmpgt) (rtx, rtx, rtx);
18554 rtx tmp, dest, zero;
18560 unpack = gen_loongson_punpckhbh;
18562 unpack = gen_loongson_punpcklbh;
18563 cmpgt = gen_loongson_pcmpgtb;
18567 unpack = gen_loongson_punpckhhw;
18569 unpack = gen_loongson_punpcklhw;
18570 cmpgt = gen_loongson_pcmpgth;
18573 gcc_unreachable ();
18576 zero = force_reg (imode, CONST0_RTX (imode));
18581 tmp = gen_reg_rtx (imode);
18582 emit_insn (cmpgt (tmp, zero, operands[1]));
18585 dest = gen_reg_rtx (imode);
18586 emit_insn (unpack (dest, operands[1], tmp));
18588 emit_move_insn (operands[0], gen_lowpart (GET_MODE (operands[0]), dest));
18591 /* A subroutine of mips_expand_vec_init, match constant vector elements. */
18594 mips_constant_elt_p (rtx x)
18596 return CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE;
18599 /* A subroutine of mips_expand_vec_init, expand via broadcast. */
18602 mips_expand_vi_broadcast (enum machine_mode vmode, rtx target, rtx elt)
18604 struct expand_vec_perm_d d;
18608 if (elt != const0_rtx)
18609 elt = force_reg (GET_MODE_INNER (vmode), elt);
18611 elt = gen_lowpart (DImode, elt);
18613 t1 = gen_reg_rtx (vmode);
18617 emit_insn (gen_loongson_vec_init1_v8qi (t1, elt));
18620 emit_insn (gen_loongson_vec_init1_v4hi (t1, elt));
18623 gcc_unreachable ();
18626 memset (&d, 0, sizeof (d));
18631 d.nelt = GET_MODE_NUNITS (vmode);
18632 d.one_vector_p = true;
18634 ok = mips_expand_vec_perm_const_1 (&d);
18638 /* A subroutine of mips_expand_vec_init, replacing all of the non-constant
18639 elements of VALS with zeros, copy the constant vector to TARGET. */
18642 mips_expand_vi_constant (enum machine_mode vmode, unsigned nelt,
18643 rtx target, rtx vals)
18645 rtvec vec = shallow_copy_rtvec (XVEC (vals, 0));
18648 for (i = 0; i < nelt; ++i)
18650 if (!mips_constant_elt_p (RTVEC_ELT (vec, i)))
18651 RTVEC_ELT (vec, i) = const0_rtx;
18654 emit_move_insn (target, gen_rtx_CONST_VECTOR (vmode, vec));
18658 /* A subroutine of mips_expand_vec_init, expand via pinsrh. */
18661 mips_expand_vi_loongson_one_pinsrh (rtx target, rtx vals, unsigned one_var)
18663 mips_expand_vi_constant (V4HImode, 4, target, vals);
18665 emit_insn (gen_vec_setv4hi (target, target, XVECEXP (vals, 0, one_var),
18666 GEN_INT (one_var)));
18669 /* A subroutine of mips_expand_vec_init, expand anything via memory. */
18672 mips_expand_vi_general (enum machine_mode vmode, enum machine_mode imode,
18673 unsigned nelt, unsigned nvar, rtx target, rtx vals)
18675 rtx mem = assign_stack_temp (vmode, GET_MODE_SIZE (vmode));
18676 unsigned int i, isize = GET_MODE_SIZE (imode);
18679 mips_expand_vi_constant (vmode, nelt, mem, vals);
18681 for (i = 0; i < nelt; ++i)
18683 rtx x = XVECEXP (vals, 0, i);
18684 if (!mips_constant_elt_p (x))
18685 emit_move_insn (adjust_address (mem, imode, i * isize), x);
18688 emit_move_insn (target, mem);
18691 /* Expand a vector initialization. */
18694 mips_expand_vector_init (rtx target, rtx vals)
18696 enum machine_mode vmode = GET_MODE (target);
18697 enum machine_mode imode = GET_MODE_INNER (vmode);
18698 unsigned i, nelt = GET_MODE_NUNITS (vmode);
18699 unsigned nvar = 0, one_var = -1u;
18700 bool all_same = true;
18703 for (i = 0; i < nelt; ++i)
18705 x = XVECEXP (vals, 0, i);
18706 if (!mips_constant_elt_p (x))
18707 nvar++, one_var = i;
18708 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
18712 /* Load constants from the pool, or whatever's handy. */
18715 emit_move_insn (target, gen_rtx_CONST_VECTOR (vmode, XVEC (vals, 0)));
18719 /* For two-part initialization, always use CONCAT. */
18722 rtx op0 = force_reg (imode, XVECEXP (vals, 0, 0));
18723 rtx op1 = force_reg (imode, XVECEXP (vals, 0, 1));
18724 x = gen_rtx_VEC_CONCAT (vmode, op0, op1);
18725 emit_insn (gen_rtx_SET (VOIDmode, target, x));
18729 /* Loongson is the only cpu with vectors with more elements. */
18730 gcc_assert (TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS);
18732 /* If all values are identical, broadcast the value. */
18735 mips_expand_vi_broadcast (vmode, target, XVECEXP (vals, 0, 0));
18739 /* If we've only got one non-variable V4HImode, use PINSRH. */
18740 if (nvar == 1 && vmode == V4HImode)
18742 mips_expand_vi_loongson_one_pinsrh (target, vals, one_var);
18746 mips_expand_vi_general (vmode, imode, nelt, nvar, target, vals);
18749 /* Expand a vector reduction. */
18752 mips_expand_vec_reduc (rtx target, rtx in, rtx (*gen)(rtx, rtx, rtx))
18754 enum machine_mode vmode = GET_MODE (in);
18755 unsigned char perm2[2];
18756 rtx last, next, fold, x;
18760 fold = gen_reg_rtx (vmode);
18764 /* Use PUL/PLU to produce { L, H } op { H, L }.
18765 By reversing the pair order, rather than a pure interleave high,
18766 we avoid erroneous exceptional conditions that we might otherwise
18767 produce from the computation of H op H. */
18770 ok = mips_expand_vselect_vconcat (fold, last, last, perm2, 2);
18775 /* Use interleave to produce { H, L } op { H, H }. */
18776 emit_insn (gen_loongson_punpckhwd (fold, last, last));
18780 /* Perform the first reduction with interleave,
18781 and subsequent reductions with shifts. */
18782 emit_insn (gen_loongson_punpckhwd_hi (fold, last, last));
18784 next = gen_reg_rtx (vmode);
18785 emit_insn (gen (next, last, fold));
18788 fold = gen_reg_rtx (vmode);
18789 x = force_reg (SImode, GEN_INT (16));
18790 emit_insn (gen_vec_shr_v4hi (fold, last, x));
18794 emit_insn (gen_loongson_punpckhwd_qi (fold, last, last));
18796 next = gen_reg_rtx (vmode);
18797 emit_insn (gen (next, last, fold));
18800 fold = gen_reg_rtx (vmode);
18801 x = force_reg (SImode, GEN_INT (16));
18802 emit_insn (gen_vec_shr_v8qi (fold, last, x));
18804 next = gen_reg_rtx (vmode);
18805 emit_insn (gen (next, last, fold));
18808 fold = gen_reg_rtx (vmode);
18809 x = force_reg (SImode, GEN_INT (8));
18810 emit_insn (gen_vec_shr_v8qi (fold, last, x));
18814 gcc_unreachable ();
18817 emit_insn (gen (target, last, fold));
18820 /* Expand a vector minimum/maximum. */
18823 mips_expand_vec_minmax (rtx target, rtx op0, rtx op1,
18824 rtx (*cmp) (rtx, rtx, rtx), bool min_p)
18826 enum machine_mode vmode = GET_MODE (target);
18829 tc = gen_reg_rtx (vmode);
18830 t0 = gen_reg_rtx (vmode);
18831 t1 = gen_reg_rtx (vmode);
18834 emit_insn (cmp (tc, op0, op1));
18836 x = gen_rtx_AND (vmode, tc, (min_p ? op1 : op0));
18837 emit_insn (gen_rtx_SET (VOIDmode, t0, x));
18839 x = gen_rtx_NOT (vmode, tc);
18840 x = gen_rtx_AND (vmode, x, (min_p ? op0 : op1));
18841 emit_insn (gen_rtx_SET (VOIDmode, t1, x));
18843 x = gen_rtx_IOR (vmode, t0, t1);
18844 emit_insn (gen_rtx_SET (VOIDmode, target, x));
18847 /* Implement TARGET_CASE_VALUES_THRESHOLD. */
18850 mips_case_values_threshold (void)
18852 /* In MIPS16 mode using a larger case threshold generates smaller code. */
18853 if (TARGET_MIPS16 && optimize_size)
18856 return default_case_values_threshold ();
18859 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
18862 mips_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
18864 if (!TARGET_HARD_FLOAT_ABI)
18866 tree exceptions_var = create_tmp_var (MIPS_ATYPE_USI, NULL);
18867 tree fcsr_orig_var = create_tmp_var (MIPS_ATYPE_USI, NULL);
18868 tree fcsr_mod_var = create_tmp_var (MIPS_ATYPE_USI, NULL);
18869 tree get_fcsr = mips_builtin_decls[MIPS_GET_FCSR];
18870 tree set_fcsr = mips_builtin_decls[MIPS_SET_FCSR];
18871 tree get_fcsr_hold_call = build_call_expr (get_fcsr, 0);
18872 tree hold_assign_orig = build2 (MODIFY_EXPR, MIPS_ATYPE_USI,
18873 fcsr_orig_var, get_fcsr_hold_call);
18874 tree hold_mod_val = build2 (BIT_AND_EXPR, MIPS_ATYPE_USI, fcsr_orig_var,
18875 build_int_cst (MIPS_ATYPE_USI, 0xfffff003));
18876 tree hold_assign_mod = build2 (MODIFY_EXPR, MIPS_ATYPE_USI,
18877 fcsr_mod_var, hold_mod_val);
18878 tree set_fcsr_hold_call = build_call_expr (set_fcsr, 1, fcsr_mod_var);
18879 tree hold_all = build2 (COMPOUND_EXPR, MIPS_ATYPE_USI,
18880 hold_assign_orig, hold_assign_mod);
18881 *hold = build2 (COMPOUND_EXPR, void_type_node, hold_all,
18882 set_fcsr_hold_call);
18884 *clear = build_call_expr (set_fcsr, 1, fcsr_mod_var);
18886 tree get_fcsr_update_call = build_call_expr (get_fcsr, 0);
18887 *update = build2 (MODIFY_EXPR, MIPS_ATYPE_USI,
18888 exceptions_var, get_fcsr_update_call);
18889 tree set_fcsr_update_call = build_call_expr (set_fcsr, 1, fcsr_orig_var);
18890 *update = build2 (COMPOUND_EXPR, void_type_node, *update,
18891 set_fcsr_update_call);
18892 tree atomic_feraiseexcept
18893 = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT);
18894 tree int_exceptions_var = fold_convert (integer_type_node,
18896 tree atomic_feraiseexcept_call = build_call_expr (atomic_feraiseexcept,
18897 1, int_exceptions_var);
18898 *update = build2 (COMPOUND_EXPR, void_type_node, *update,
18899 atomic_feraiseexcept_call);
18902 /* Initialize the GCC target structure. */
18903 #undef TARGET_ASM_ALIGNED_HI_OP
18904 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
18905 #undef TARGET_ASM_ALIGNED_SI_OP
18906 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
18907 #undef TARGET_ASM_ALIGNED_DI_OP
18908 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
18910 #undef TARGET_OPTION_OVERRIDE
18911 #define TARGET_OPTION_OVERRIDE mips_option_override
18913 #undef TARGET_LEGITIMIZE_ADDRESS
18914 #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
18916 #undef TARGET_ASM_FUNCTION_PROLOGUE
18917 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
18918 #undef TARGET_ASM_FUNCTION_EPILOGUE
18919 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
18920 #undef TARGET_ASM_SELECT_RTX_SECTION
18921 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
18922 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
18923 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
18925 #undef TARGET_SCHED_INIT
18926 #define TARGET_SCHED_INIT mips_sched_init
18927 #undef TARGET_SCHED_REORDER
18928 #define TARGET_SCHED_REORDER mips_sched_reorder
18929 #undef TARGET_SCHED_REORDER2
18930 #define TARGET_SCHED_REORDER2 mips_sched_reorder2
18931 #undef TARGET_SCHED_VARIABLE_ISSUE
18932 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
18933 #undef TARGET_SCHED_ADJUST_COST
18934 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
18935 #undef TARGET_SCHED_ISSUE_RATE
18936 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
18937 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
18938 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
18939 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
18940 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
18941 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
18942 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
18943 mips_multipass_dfa_lookahead
18944 #undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
18945 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
18946 mips_small_register_classes_for_mode_p
18948 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
18949 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
18951 #undef TARGET_INSERT_ATTRIBUTES
18952 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
18953 #undef TARGET_MERGE_DECL_ATTRIBUTES
18954 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
18955 #undef TARGET_CAN_INLINE_P
18956 #define TARGET_CAN_INLINE_P mips_can_inline_p
18957 #undef TARGET_SET_CURRENT_FUNCTION
18958 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
18960 #undef TARGET_VALID_POINTER_MODE
18961 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
18962 #undef TARGET_REGISTER_MOVE_COST
18963 #define TARGET_REGISTER_MOVE_COST mips_register_move_cost
18964 #undef TARGET_MEMORY_MOVE_COST
18965 #define TARGET_MEMORY_MOVE_COST mips_memory_move_cost
18966 #undef TARGET_RTX_COSTS
18967 #define TARGET_RTX_COSTS mips_rtx_costs
18968 #undef TARGET_ADDRESS_COST
18969 #define TARGET_ADDRESS_COST mips_address_cost
18971 #undef TARGET_IN_SMALL_DATA_P
18972 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
18974 #undef TARGET_MACHINE_DEPENDENT_REORG
18975 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
18977 #undef TARGET_PREFERRED_RELOAD_CLASS
18978 #define TARGET_PREFERRED_RELOAD_CLASS mips_preferred_reload_class
18980 #undef TARGET_EXPAND_TO_RTL_HOOK
18981 #define TARGET_EXPAND_TO_RTL_HOOK mips_expand_to_rtl_hook
18982 #undef TARGET_ASM_FILE_START
18983 #define TARGET_ASM_FILE_START mips_file_start
18984 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
18985 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
18986 #undef TARGET_ASM_CODE_END
18987 #define TARGET_ASM_CODE_END mips_code_end
18989 #undef TARGET_INIT_LIBFUNCS
18990 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
18992 #undef TARGET_BUILD_BUILTIN_VA_LIST
18993 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
18994 #undef TARGET_EXPAND_BUILTIN_VA_START
18995 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
18996 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
18997 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
18999 #undef TARGET_PROMOTE_FUNCTION_MODE
19000 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
19001 #undef TARGET_PROMOTE_PROTOTYPES
19002 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
19004 #undef TARGET_FUNCTION_VALUE
19005 #define TARGET_FUNCTION_VALUE mips_function_value
19006 #undef TARGET_LIBCALL_VALUE
19007 #define TARGET_LIBCALL_VALUE mips_libcall_value
19008 #undef TARGET_FUNCTION_VALUE_REGNO_P
19009 #define TARGET_FUNCTION_VALUE_REGNO_P mips_function_value_regno_p
19010 #undef TARGET_RETURN_IN_MEMORY
19011 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
19012 #undef TARGET_RETURN_IN_MSB
19013 #define TARGET_RETURN_IN_MSB mips_return_in_msb
19015 #undef TARGET_ASM_OUTPUT_MI_THUNK
19016 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
19017 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
19018 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
19020 #undef TARGET_PRINT_OPERAND
19021 #define TARGET_PRINT_OPERAND mips_print_operand
19022 #undef TARGET_PRINT_OPERAND_ADDRESS
19023 #define TARGET_PRINT_OPERAND_ADDRESS mips_print_operand_address
19024 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
19025 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mips_print_operand_punct_valid_p
19027 #undef TARGET_SETUP_INCOMING_VARARGS
19028 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
19029 #undef TARGET_STRICT_ARGUMENT_NAMING
19030 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
19031 #undef TARGET_MUST_PASS_IN_STACK
19032 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
19033 #undef TARGET_PASS_BY_REFERENCE
19034 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
19035 #undef TARGET_CALLEE_COPIES
19036 #define TARGET_CALLEE_COPIES mips_callee_copies
19037 #undef TARGET_ARG_PARTIAL_BYTES
19038 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
19039 #undef TARGET_FUNCTION_ARG
19040 #define TARGET_FUNCTION_ARG mips_function_arg
19041 #undef TARGET_FUNCTION_ARG_ADVANCE
19042 #define TARGET_FUNCTION_ARG_ADVANCE mips_function_arg_advance
19043 #undef TARGET_FUNCTION_ARG_BOUNDARY
19044 #define TARGET_FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
19046 #undef TARGET_MODE_REP_EXTENDED
19047 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
19049 #undef TARGET_VECTOR_MODE_SUPPORTED_P
19050 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
19052 #undef TARGET_SCALAR_MODE_SUPPORTED_P
19053 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
19055 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
19056 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE mips_preferred_simd_mode
19058 #undef TARGET_INIT_BUILTINS
19059 #define TARGET_INIT_BUILTINS mips_init_builtins
19060 #undef TARGET_BUILTIN_DECL
19061 #define TARGET_BUILTIN_DECL mips_builtin_decl
19062 #undef TARGET_EXPAND_BUILTIN
19063 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
19065 #undef TARGET_HAVE_TLS
19066 #define TARGET_HAVE_TLS HAVE_AS_TLS
19068 #undef TARGET_CANNOT_FORCE_CONST_MEM
19069 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
19071 #undef TARGET_LEGITIMATE_CONSTANT_P
19072 #define TARGET_LEGITIMATE_CONSTANT_P mips_legitimate_constant_p
19074 #undef TARGET_ENCODE_SECTION_INFO
19075 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
19077 #undef TARGET_ATTRIBUTE_TABLE
19078 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
19079 /* All our function attributes are related to how out-of-line copies should
19080 be compiled or called. They don't in themselves prevent inlining. */
19081 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
19082 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
19084 #undef TARGET_EXTRA_LIVE_ON_ENTRY
19085 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
19087 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
19088 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
19089 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
19090 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
19092 #undef TARGET_COMP_TYPE_ATTRIBUTES
19093 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
19095 #ifdef HAVE_AS_DTPRELWORD
19096 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
19097 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
19099 #undef TARGET_DWARF_REGISTER_SPAN
19100 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
19102 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
19103 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
19105 #undef TARGET_LEGITIMATE_ADDRESS_P
19106 #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p
19108 #undef TARGET_FRAME_POINTER_REQUIRED
19109 #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required
19111 #undef TARGET_CAN_ELIMINATE
19112 #define TARGET_CAN_ELIMINATE mips_can_eliminate
19114 #undef TARGET_CONDITIONAL_REGISTER_USAGE
19115 #define TARGET_CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage
19117 #undef TARGET_TRAMPOLINE_INIT
19118 #define TARGET_TRAMPOLINE_INIT mips_trampoline_init
19120 #undef TARGET_ASM_OUTPUT_SOURCE_FILENAME
19121 #define TARGET_ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
19123 #undef TARGET_SHIFT_TRUNCATION_MASK
19124 #define TARGET_SHIFT_TRUNCATION_MASK mips_shift_truncation_mask
19126 #undef TARGET_PREPARE_PCH_SAVE
19127 #define TARGET_PREPARE_PCH_SAVE mips_prepare_pch_save
19129 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
19130 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK mips_vectorize_vec_perm_const_ok
19132 #undef TARGET_CASE_VALUES_THRESHOLD
19133 #define TARGET_CASE_VALUES_THRESHOLD mips_case_values_threshold
19135 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
19136 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV mips_atomic_assign_expand_fenv
19138 struct gcc_target targetm = TARGET_INITIALIZER;
19140 #include "gt-mips.h"