1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989-2016 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky, lich@inria.inria.fr.
4 Changes by Michael Meissner, meissner@osf.org.
5 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 Brendan Eich, brendan@microunity.com.
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
36 #include "stringpool.h"
42 #include "diagnostic.h"
43 #include "insn-attr.h"
46 #include "fold-const.h"
48 #include "stor-layout.h"
54 #include "common/common-target.h"
55 #include "langhooks.h"
58 #include "sched-int.h"
60 #include "target-globals.h"
61 #include "tree-pass.h"
66 /* This file should be included last. */
67 #include "target-def.h"
69 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
70 #define UNSPEC_ADDRESS_P(X) \
71 (GET_CODE (X) == UNSPEC \
72 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
73 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
75 /* Extract the symbol or label from UNSPEC wrapper X. */
76 #define UNSPEC_ADDRESS(X) \
79 /* Extract the symbol type from UNSPEC wrapper X. */
80 #define UNSPEC_ADDRESS_TYPE(X) \
81 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
83 /* The maximum distance between the top of the stack frame and the
84 value $sp has when we save and restore registers.
86 The value for normal-mode code must be a SMALL_OPERAND and must
87 preserve the maximum stack alignment. We therefore use a value
88 of 0x7ff0 in this case.
90 microMIPS LWM and SWM support 12-bit offsets (from -0x800 to 0x7ff),
91 so we use a maximum of 0x7f0 for TARGET_MICROMIPS.
93 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
94 up to 0x7f8 bytes and can usually save or restore all the registers
95 that we need to save or restore. (Note that we can only use these
96 instructions for o32, for which the stack alignment is 8 bytes.)
98 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
99 RESTORE are not available. We can then use unextended instructions
100 to save and restore registers, and to allocate and deallocate the top
101 part of the frame. */
102 #define MIPS_MAX_FIRST_STACK_STEP \
103 (!TARGET_COMPRESSION ? 0x7ff0 \
104 : TARGET_MICROMIPS || GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
105 : TARGET_64BIT ? 0x100 : 0x400)
107 /* True if INSN is a mips.md pattern or asm statement. */
108 /* ??? This test exists through the compiler, perhaps it should be
110 #define USEFUL_INSN_P(INSN) \
111 (NONDEBUG_INSN_P (INSN) \
112 && GET_CODE (PATTERN (INSN)) != USE \
113 && GET_CODE (PATTERN (INSN)) != CLOBBER)
115 /* If INSN is a delayed branch sequence, return the first instruction
116 in the sequence, otherwise return INSN itself. */
117 #define SEQ_BEGIN(INSN) \
118 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
119 ? as_a <rtx_insn *> (XVECEXP (PATTERN (INSN), 0, 0)) \
122 /* Likewise for the last instruction in a delayed branch sequence. */
123 #define SEQ_END(INSN) \
124 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
125 ? as_a <rtx_insn *> (XVECEXP (PATTERN (INSN), \
127 XVECLEN (PATTERN (INSN), 0) - 1)) \
130 /* Execute the following loop body with SUBINSN set to each instruction
131 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
132 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
133 for ((SUBINSN) = SEQ_BEGIN (INSN); \
134 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
135 (SUBINSN) = NEXT_INSN (SUBINSN))
137 /* True if bit BIT is set in VALUE. */
138 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
140 /* Return the opcode for a ptr_mode load of the form:
142 l[wd] DEST, OFFSET(BASE). */
143 #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \
144 (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \
149 /* Return the opcode to move register SRC into register DEST. */
150 #define MIPS_MOVE(DEST, SRC) \
151 ((TARGET_64BIT ? 0x2d : 0x21) \
155 /* Return the opcode for:
158 #define MIPS_LUI(DEST, VALUE) \
159 ((0xf << 26) | ((DEST) << 16) | (VALUE))
161 /* Return the opcode to jump to register DEST. When the JR opcode is not
162 available use JALR $0, DEST. */
163 #define MIPS_JR(DEST) \
164 (TARGET_CB_ALWAYS ? ((0x1b << 27) | ((DEST) << 16)) \
165 : (((DEST) << 21) | (ISA_HAS_JR ? 0x8 : 0x9)))
167 /* Return the opcode for:
169 bal . + (1 + OFFSET) * 4. */
170 #define MIPS_BAL(OFFSET) \
171 ((0x1 << 26) | (0x11 << 16) | (OFFSET))
173 /* Return the usual opcode for a nop. */
176 /* Classifies an address.
179 A natural register + offset address. The register satisfies
180 mips_valid_base_register_p and the offset is a const_arith_operand.
183 A LO_SUM rtx. The first operand is a valid base register and
184 the second operand is a symbolic address.
187 A signed 16-bit constant address.
190 A constant symbolic address. */
191 enum mips_address_type {
198 /* Macros to create an enumeration identifier for a function prototype. */
199 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
200 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
201 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
202 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
204 /* Classifies the prototype of a built-in function. */
205 enum mips_function_type {
206 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
207 #include "config/mips/mips-ftypes.def"
208 #undef DEF_MIPS_FTYPE
212 /* Specifies how a built-in function should be converted into rtl. */
213 enum mips_builtin_type {
214 /* The function corresponds directly to an .md pattern. The return
215 value is mapped to operand 0 and the arguments are mapped to
216 operands 1 and above. */
219 /* The function corresponds directly to an .md pattern. There is no return
220 value and the arguments are mapped to operands 0 and above. */
221 MIPS_BUILTIN_DIRECT_NO_TARGET,
223 /* The function corresponds to a comparison instruction followed by
224 a mips_cond_move_tf_ps pattern. The first two arguments are the
225 values to compare and the second two arguments are the vector
226 operands for the movt.ps or movf.ps instruction (in assembly order). */
230 /* The function corresponds to a V2SF comparison instruction. Operand 0
231 of this instruction is the result of the comparison, which has mode
232 CCV2 or CCV4. The function arguments are mapped to operands 1 and
233 above. The function's return value is an SImode boolean that is
234 true under the following conditions:
236 MIPS_BUILTIN_CMP_ANY: one of the registers is true
237 MIPS_BUILTIN_CMP_ALL: all of the registers are true
238 MIPS_BUILTIN_CMP_LOWER: the first register is true
239 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
240 MIPS_BUILTIN_CMP_ANY,
241 MIPS_BUILTIN_CMP_ALL,
242 MIPS_BUILTIN_CMP_UPPER,
243 MIPS_BUILTIN_CMP_LOWER,
245 /* As above, but the instruction only sets a single $fcc register. */
246 MIPS_BUILTIN_CMP_SINGLE,
248 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
249 MIPS_BUILTIN_BPOSGE32
252 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
253 #define MIPS_FP_CONDITIONS(MACRO) \
271 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
272 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
273 enum mips_fp_condition {
274 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
276 #undef DECLARE_MIPS_COND
278 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
279 #define STRINGIFY(X) #X
280 static const char *const mips_fp_conditions[] = {
281 MIPS_FP_CONDITIONS (STRINGIFY)
285 /* A class used to control a comdat-style stub that we output in each
286 translation unit that needs it. */
287 class mips_one_only_stub {
289 virtual ~mips_one_only_stub () {}
291 /* Return the name of the stub. */
292 virtual const char *get_name () = 0;
294 /* Output the body of the function to asm_out_file. */
295 virtual void output_body () = 0;
298 /* Tuning information that is automatically derived from other sources
299 (such as the scheduler). */
301 /* The architecture and tuning settings that this structure describes. */
305 /* True if this structure describes MIPS16 settings. */
308 /* True if the structure has been initialized. */
311 /* True if "MULT $0, $0" is preferable to "MTLO $0; MTHI $0"
312 when optimizing for speed. */
313 bool fast_mult_zero_zero_p;
316 /* Information about a single argument. */
317 struct mips_arg_info {
318 /* True if the argument is passed in a floating-point register, or
319 would have been if we hadn't run out of registers. */
322 /* The number of words passed in registers, rounded up. */
323 unsigned int reg_words;
325 /* For EABI, the offset of the first register from GP_ARG_FIRST or
326 FP_ARG_FIRST. For other ABIs, the offset of the first register from
327 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
328 comment for details).
330 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
332 unsigned int reg_offset;
334 /* The number of words that must be passed on the stack, rounded up. */
335 unsigned int stack_words;
337 /* The offset from the start of the stack overflow area of the argument's
338 first stack word. Only meaningful when STACK_WORDS is nonzero. */
339 unsigned int stack_offset;
342 /* Information about an address described by mips_address_type.
348 REG is the base register and OFFSET is the constant offset.
351 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
352 is the type of symbol it references.
355 SYMBOL_TYPE is the type of symbol that the address references. */
356 struct mips_address_info {
357 enum mips_address_type type;
360 enum mips_symbol_type symbol_type;
363 /* One stage in a constant building sequence. These sequences have
367 A = A CODE[1] VALUE[1]
368 A = A CODE[2] VALUE[2]
371 where A is an accumulator, each CODE[i] is a binary rtl operation
372 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
373 struct mips_integer_op {
375 unsigned HOST_WIDE_INT value;
378 /* The largest number of operations needed to load an integer constant.
379 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
380 When the lowest bit is clear, we can try, but reject a sequence with
381 an extra SLL at the end. */
382 #define MIPS_MAX_INTEGER_OPS 7
384 /* Information about a MIPS16e SAVE or RESTORE instruction. */
385 struct mips16e_save_restore_info {
386 /* The number of argument registers saved by a SAVE instruction.
387 0 for RESTORE instructions. */
390 /* Bit X is set if the instruction saves or restores GPR X. */
393 /* The total number of bytes to allocate. */
397 /* Costs of various operations on the different architectures. */
399 struct mips_rtx_cost_data
401 unsigned short fp_add;
402 unsigned short fp_mult_sf;
403 unsigned short fp_mult_df;
404 unsigned short fp_div_sf;
405 unsigned short fp_div_df;
406 unsigned short int_mult_si;
407 unsigned short int_mult_di;
408 unsigned short int_div_si;
409 unsigned short int_div_di;
410 unsigned short branch_cost;
411 unsigned short memory_latency;
414 /* Global variables for machine-dependent things. */
416 /* The -G setting, or the configuration's default small-data limit if
417 no -G option is given. */
418 static unsigned int mips_small_data_threshold;
420 /* The number of file directives written by mips_output_filename. */
421 int num_source_filenames;
423 /* The name that appeared in the last .file directive written by
424 mips_output_filename, or "" if mips_output_filename hasn't
425 written anything yet. */
426 const char *current_function_file = "";
428 /* Arrays that map GCC register numbers to debugger register numbers. */
429 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
430 int mips_dwarf_regno[FIRST_PSEUDO_REGISTER];
432 /* Information about the current function's epilogue, used only while
435 /* A list of queued REG_CFA_RESTORE notes. */
438 /* The CFA is currently defined as CFA_REG + CFA_OFFSET. */
440 HOST_WIDE_INT cfa_offset;
442 /* The offset of the CFA from the stack pointer while restoring
444 HOST_WIDE_INT cfa_restore_sp_offset;
447 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
448 struct mips_asm_switch mips_noreorder = { "reorder", 0 };
449 struct mips_asm_switch mips_nomacro = { "macro", 0 };
450 struct mips_asm_switch mips_noat = { "at", 0 };
452 /* True if we're writing out a branch-likely instruction rather than a
454 static bool mips_branch_likely;
456 /* The current instruction-set architecture. */
457 enum processor mips_arch;
458 const struct mips_cpu_info *mips_arch_info;
460 /* The processor that we should tune the code for. */
461 enum processor mips_tune;
462 const struct mips_cpu_info *mips_tune_info;
464 /* The ISA level associated with mips_arch. */
467 /* The ISA revision level. This is 0 for MIPS I to V and N for
471 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
472 static const struct mips_cpu_info *mips_isa_option_info;
474 /* Which cost information to use. */
475 static const struct mips_rtx_cost_data *mips_cost;
477 /* The ambient target flags, excluding MASK_MIPS16. */
478 static int mips_base_target_flags;
480 /* The default compression mode. */
481 unsigned int mips_base_compression_flags;
483 /* The ambient values of other global variables. */
484 static int mips_base_schedule_insns; /* flag_schedule_insns */
485 static int mips_base_reorder_blocks_and_partition; /* flag_reorder... */
486 static int mips_base_move_loop_invariants; /* flag_move_loop_invariants */
487 static int mips_base_align_loops; /* align_loops */
488 static int mips_base_align_jumps; /* align_jumps */
489 static int mips_base_align_functions; /* align_functions */
491 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
492 bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
494 /* Index C is true if character C is a valid PRINT_OPERAND punctation
496 static bool mips_print_operand_punct[256];
498 static GTY (()) int mips_output_filename_first_time = 1;
500 /* mips_split_p[X] is true if symbols of type X can be split by
501 mips_split_symbol. */
502 bool mips_split_p[NUM_SYMBOL_TYPES];
504 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
505 can be split by mips_split_symbol. */
506 bool mips_split_hi_p[NUM_SYMBOL_TYPES];
508 /* mips_use_pcrel_pool_p[X] is true if symbols of type X should be
509 forced into a PC-relative constant pool. */
510 bool mips_use_pcrel_pool_p[NUM_SYMBOL_TYPES];
512 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
513 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
514 if they are matched by a special .md file pattern. */
515 const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
517 /* Likewise for HIGHs. */
518 const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
520 /* Target state for MIPS16. */
521 struct target_globals *mips16_globals;
523 /* Target state for MICROMIPS. */
524 struct target_globals *micromips_globals;
526 /* Cached value of can_issue_more. This is cached in mips_variable_issue hook
527 and returned from mips_sched_reorder2. */
528 static int cached_can_issue_more;
530 /* The stubs for various MIPS16 support functions, if used. */
531 static mips_one_only_stub *mips16_rdhwr_stub;
532 static mips_one_only_stub *mips16_get_fcsr_stub;
533 static mips_one_only_stub *mips16_set_fcsr_stub;
535 /* Index R is the smallest register class that contains register R. */
536 const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = {
537 LEA_REGS, LEA_REGS, M16_STORE_REGS, V1_REG,
538 M16_STORE_REGS, M16_STORE_REGS, M16_STORE_REGS, M16_STORE_REGS,
539 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
540 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
541 M16_REGS, M16_STORE_REGS, LEA_REGS, LEA_REGS,
542 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
543 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
544 LEA_REGS, M16_SP_REGS, LEA_REGS, LEA_REGS,
546 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
547 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
548 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
549 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
550 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
551 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
552 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
553 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
554 MD0_REG, MD1_REG, NO_REGS, ST_REGS,
555 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
556 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
557 NO_REGS, FRAME_REGS, FRAME_REGS, NO_REGS,
558 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
559 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
560 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
561 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
562 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
563 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
564 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
565 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
566 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
567 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
568 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
569 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
570 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
571 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
572 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
573 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
574 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
575 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
576 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
577 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
578 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
579 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
580 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
581 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
582 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
583 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
584 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
587 static tree mips_handle_interrupt_attr (tree *, tree, tree, int, bool *);
588 static tree mips_handle_use_shadow_register_set_attr (tree *, tree, tree, int,
591 /* The value of TARGET_ATTRIBUTE_TABLE. */
592 static const struct attribute_spec mips_attribute_table[] = {
593 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
595 { "long_call", 0, 0, false, true, true, NULL, false },
596 { "far", 0, 0, false, true, true, NULL, false },
597 { "near", 0, 0, false, true, true, NULL, false },
598 /* We would really like to treat "mips16" and "nomips16" as type
599 attributes, but GCC doesn't provide the hooks we need to support
600 the right conversion rules. As declaration attributes, they affect
601 code generation but don't carry other semantics. */
602 { "mips16", 0, 0, true, false, false, NULL, false },
603 { "nomips16", 0, 0, true, false, false, NULL, false },
604 { "micromips", 0, 0, true, false, false, NULL, false },
605 { "nomicromips", 0, 0, true, false, false, NULL, false },
606 { "nocompression", 0, 0, true, false, false, NULL, false },
607 /* Allow functions to be specified as interrupt handlers */
608 { "interrupt", 0, 1, false, true, true, mips_handle_interrupt_attr,
610 { "use_shadow_register_set", 0, 1, false, true, true,
611 mips_handle_use_shadow_register_set_attr, false },
612 { "keep_interrupts_masked", 0, 0, false, true, true, NULL, false },
613 { "use_debug_exception_return", 0, 0, false, true, true, NULL, false },
614 { NULL, 0, 0, false, false, false, NULL, false }
617 /* A table describing all the processors GCC knows about; see
618 mips-cpus.def for details. */
619 static const struct mips_cpu_info mips_cpu_info_table[] = {
620 #define MIPS_CPU(NAME, CPU, ISA, FLAGS) \
621 { NAME, CPU, ISA, FLAGS },
622 #include "mips-cpus.def"
626 /* Default costs. If these are used for a processor we should look
627 up the actual costs. */
628 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
629 COSTS_N_INSNS (7), /* fp_mult_sf */ \
630 COSTS_N_INSNS (8), /* fp_mult_df */ \
631 COSTS_N_INSNS (23), /* fp_div_sf */ \
632 COSTS_N_INSNS (36), /* fp_div_df */ \
633 COSTS_N_INSNS (10), /* int_mult_si */ \
634 COSTS_N_INSNS (10), /* int_mult_di */ \
635 COSTS_N_INSNS (69), /* int_div_si */ \
636 COSTS_N_INSNS (69), /* int_div_di */ \
637 2, /* branch_cost */ \
638 4 /* memory_latency */
640 /* Floating-point costs for processors without an FPU. Just assume that
641 all floating-point libcalls are very expensive. */
642 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
643 COSTS_N_INSNS (256), /* fp_mult_sf */ \
644 COSTS_N_INSNS (256), /* fp_mult_df */ \
645 COSTS_N_INSNS (256), /* fp_div_sf */ \
646 COSTS_N_INSNS (256) /* fp_div_df */
648 /* Costs to use when optimizing for size. */
649 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size = {
650 COSTS_N_INSNS (1), /* fp_add */
651 COSTS_N_INSNS (1), /* fp_mult_sf */
652 COSTS_N_INSNS (1), /* fp_mult_df */
653 COSTS_N_INSNS (1), /* fp_div_sf */
654 COSTS_N_INSNS (1), /* fp_div_df */
655 COSTS_N_INSNS (1), /* int_mult_si */
656 COSTS_N_INSNS (1), /* int_mult_di */
657 COSTS_N_INSNS (1), /* int_div_si */
658 COSTS_N_INSNS (1), /* int_div_di */
660 4 /* memory_latency */
663 /* Costs to use when optimizing for speed, indexed by processor. */
664 static const struct mips_rtx_cost_data
665 mips_rtx_cost_data[NUM_PROCESSOR_VALUES] = {
667 COSTS_N_INSNS (2), /* fp_add */
668 COSTS_N_INSNS (4), /* fp_mult_sf */
669 COSTS_N_INSNS (5), /* fp_mult_df */
670 COSTS_N_INSNS (12), /* fp_div_sf */
671 COSTS_N_INSNS (19), /* fp_div_df */
672 COSTS_N_INSNS (12), /* int_mult_si */
673 COSTS_N_INSNS (12), /* int_mult_di */
674 COSTS_N_INSNS (35), /* int_div_si */
675 COSTS_N_INSNS (35), /* int_div_di */
677 4 /* memory_latency */
681 COSTS_N_INSNS (6), /* int_mult_si */
682 COSTS_N_INSNS (6), /* int_mult_di */
683 COSTS_N_INSNS (36), /* int_div_si */
684 COSTS_N_INSNS (36), /* int_div_di */
686 4 /* memory_latency */
690 COSTS_N_INSNS (36), /* int_mult_si */
691 COSTS_N_INSNS (36), /* int_mult_di */
692 COSTS_N_INSNS (37), /* int_div_si */
693 COSTS_N_INSNS (37), /* int_div_di */
695 4 /* memory_latency */
699 COSTS_N_INSNS (4), /* int_mult_si */
700 COSTS_N_INSNS (11), /* int_mult_di */
701 COSTS_N_INSNS (36), /* int_div_si */
702 COSTS_N_INSNS (68), /* int_div_di */
704 4 /* memory_latency */
707 COSTS_N_INSNS (4), /* fp_add */
708 COSTS_N_INSNS (4), /* fp_mult_sf */
709 COSTS_N_INSNS (5), /* fp_mult_df */
710 COSTS_N_INSNS (17), /* fp_div_sf */
711 COSTS_N_INSNS (32), /* fp_div_df */
712 COSTS_N_INSNS (4), /* int_mult_si */
713 COSTS_N_INSNS (11), /* int_mult_di */
714 COSTS_N_INSNS (36), /* int_div_si */
715 COSTS_N_INSNS (68), /* int_div_di */
717 4 /* memory_latency */
720 COSTS_N_INSNS (4), /* fp_add */
721 COSTS_N_INSNS (4), /* fp_mult_sf */
722 COSTS_N_INSNS (5), /* fp_mult_df */
723 COSTS_N_INSNS (17), /* fp_div_sf */
724 COSTS_N_INSNS (32), /* fp_div_df */
725 COSTS_N_INSNS (4), /* int_mult_si */
726 COSTS_N_INSNS (7), /* int_mult_di */
727 COSTS_N_INSNS (42), /* int_div_si */
728 COSTS_N_INSNS (72), /* int_div_di */
730 4 /* memory_latency */
734 COSTS_N_INSNS (5), /* int_mult_si */
735 COSTS_N_INSNS (5), /* int_mult_di */
736 COSTS_N_INSNS (41), /* int_div_si */
737 COSTS_N_INSNS (41), /* int_div_di */
739 4 /* memory_latency */
742 COSTS_N_INSNS (8), /* fp_add */
743 COSTS_N_INSNS (8), /* fp_mult_sf */
744 COSTS_N_INSNS (10), /* fp_mult_df */
745 COSTS_N_INSNS (34), /* fp_div_sf */
746 COSTS_N_INSNS (64), /* fp_div_df */
747 COSTS_N_INSNS (5), /* int_mult_si */
748 COSTS_N_INSNS (5), /* int_mult_di */
749 COSTS_N_INSNS (41), /* int_div_si */
750 COSTS_N_INSNS (41), /* int_div_di */
752 4 /* memory_latency */
755 COSTS_N_INSNS (4), /* fp_add */
756 COSTS_N_INSNS (4), /* fp_mult_sf */
757 COSTS_N_INSNS (5), /* fp_mult_df */
758 COSTS_N_INSNS (17), /* fp_div_sf */
759 COSTS_N_INSNS (32), /* fp_div_df */
760 COSTS_N_INSNS (5), /* int_mult_si */
761 COSTS_N_INSNS (5), /* int_mult_di */
762 COSTS_N_INSNS (41), /* int_div_si */
763 COSTS_N_INSNS (41), /* int_div_di */
765 4 /* memory_latency */
769 COSTS_N_INSNS (5), /* int_mult_si */
770 COSTS_N_INSNS (5), /* int_mult_di */
771 COSTS_N_INSNS (41), /* int_div_si */
772 COSTS_N_INSNS (41), /* int_div_di */
774 4 /* memory_latency */
777 COSTS_N_INSNS (8), /* fp_add */
778 COSTS_N_INSNS (8), /* fp_mult_sf */
779 COSTS_N_INSNS (10), /* fp_mult_df */
780 COSTS_N_INSNS (34), /* fp_div_sf */
781 COSTS_N_INSNS (64), /* fp_div_df */
782 COSTS_N_INSNS (5), /* int_mult_si */
783 COSTS_N_INSNS (5), /* int_mult_di */
784 COSTS_N_INSNS (41), /* int_div_si */
785 COSTS_N_INSNS (41), /* int_div_di */
787 4 /* memory_latency */
790 COSTS_N_INSNS (4), /* fp_add */
791 COSTS_N_INSNS (4), /* fp_mult_sf */
792 COSTS_N_INSNS (5), /* fp_mult_df */
793 COSTS_N_INSNS (17), /* fp_div_sf */
794 COSTS_N_INSNS (32), /* fp_div_df */
795 COSTS_N_INSNS (5), /* int_mult_si */
796 COSTS_N_INSNS (5), /* int_mult_di */
797 COSTS_N_INSNS (41), /* int_div_si */
798 COSTS_N_INSNS (41), /* int_div_di */
800 4 /* memory_latency */
803 COSTS_N_INSNS (6), /* fp_add */
804 COSTS_N_INSNS (6), /* fp_mult_sf */
805 COSTS_N_INSNS (7), /* fp_mult_df */
806 COSTS_N_INSNS (25), /* fp_div_sf */
807 COSTS_N_INSNS (48), /* fp_div_df */
808 COSTS_N_INSNS (5), /* int_mult_si */
809 COSTS_N_INSNS (5), /* int_mult_di */
810 COSTS_N_INSNS (41), /* int_div_si */
811 COSTS_N_INSNS (41), /* int_div_di */
813 4 /* memory_latency */
830 COSTS_N_INSNS (5), /* int_mult_si */
831 COSTS_N_INSNS (5), /* int_mult_di */
832 COSTS_N_INSNS (72), /* int_div_si */
833 COSTS_N_INSNS (72), /* int_div_di */
835 4 /* memory_latency */
840 COSTS_N_INSNS (6), /* int_mult_si */
841 COSTS_N_INSNS (6), /* int_mult_di */
842 COSTS_N_INSNS (18), /* int_div_si */
843 COSTS_N_INSNS (35), /* int_div_di */
845 4 /* memory_latency */
849 COSTS_N_INSNS (6), /* fp_add */
850 COSTS_N_INSNS (6), /* fp_mult_sf */
851 COSTS_N_INSNS (7), /* fp_mult_df */
852 COSTS_N_INSNS (25), /* fp_div_sf */
853 COSTS_N_INSNS (48), /* fp_div_df */
854 COSTS_N_INSNS (6), /* int_mult_si */
855 COSTS_N_INSNS (6), /* int_mult_di */
856 COSTS_N_INSNS (18), /* int_div_si */
857 COSTS_N_INSNS (35), /* int_div_di */
859 4 /* memory_latency */
862 COSTS_N_INSNS (2), /* fp_add */
863 COSTS_N_INSNS (4), /* fp_mult_sf */
864 COSTS_N_INSNS (5), /* fp_mult_df */
865 COSTS_N_INSNS (12), /* fp_div_sf */
866 COSTS_N_INSNS (19), /* fp_div_df */
867 COSTS_N_INSNS (2), /* int_mult_si */
868 COSTS_N_INSNS (2), /* int_mult_di */
869 COSTS_N_INSNS (35), /* int_div_si */
870 COSTS_N_INSNS (35), /* int_div_di */
872 4 /* memory_latency */
875 COSTS_N_INSNS (3), /* fp_add */
876 COSTS_N_INSNS (5), /* fp_mult_sf */
877 COSTS_N_INSNS (6), /* fp_mult_df */
878 COSTS_N_INSNS (15), /* fp_div_sf */
879 COSTS_N_INSNS (16), /* fp_div_df */
880 COSTS_N_INSNS (17), /* int_mult_si */
881 COSTS_N_INSNS (17), /* int_mult_di */
882 COSTS_N_INSNS (38), /* int_div_si */
883 COSTS_N_INSNS (38), /* int_div_di */
885 6 /* memory_latency */
888 COSTS_N_INSNS (6), /* fp_add */
889 COSTS_N_INSNS (7), /* fp_mult_sf */
890 COSTS_N_INSNS (8), /* fp_mult_df */
891 COSTS_N_INSNS (23), /* fp_div_sf */
892 COSTS_N_INSNS (36), /* fp_div_df */
893 COSTS_N_INSNS (10), /* int_mult_si */
894 COSTS_N_INSNS (10), /* int_mult_di */
895 COSTS_N_INSNS (69), /* int_div_si */
896 COSTS_N_INSNS (69), /* int_div_di */
898 6 /* memory_latency */
910 /* The only costs that appear to be updated here are
911 integer multiplication. */
913 COSTS_N_INSNS (4), /* int_mult_si */
914 COSTS_N_INSNS (6), /* int_mult_di */
915 COSTS_N_INSNS (69), /* int_div_si */
916 COSTS_N_INSNS (69), /* int_div_di */
918 4 /* memory_latency */
933 COSTS_N_INSNS (6), /* fp_add */
934 COSTS_N_INSNS (4), /* fp_mult_sf */
935 COSTS_N_INSNS (5), /* fp_mult_df */
936 COSTS_N_INSNS (23), /* fp_div_sf */
937 COSTS_N_INSNS (36), /* fp_div_df */
938 COSTS_N_INSNS (5), /* int_mult_si */
939 COSTS_N_INSNS (5), /* int_mult_di */
940 COSTS_N_INSNS (36), /* int_div_si */
941 COSTS_N_INSNS (36), /* int_div_di */
943 4 /* memory_latency */
946 COSTS_N_INSNS (6), /* fp_add */
947 COSTS_N_INSNS (5), /* fp_mult_sf */
948 COSTS_N_INSNS (6), /* fp_mult_df */
949 COSTS_N_INSNS (30), /* fp_div_sf */
950 COSTS_N_INSNS (59), /* fp_div_df */
951 COSTS_N_INSNS (3), /* int_mult_si */
952 COSTS_N_INSNS (4), /* int_mult_di */
953 COSTS_N_INSNS (42), /* int_div_si */
954 COSTS_N_INSNS (74), /* int_div_di */
956 4 /* memory_latency */
959 COSTS_N_INSNS (6), /* fp_add */
960 COSTS_N_INSNS (5), /* fp_mult_sf */
961 COSTS_N_INSNS (6), /* fp_mult_df */
962 COSTS_N_INSNS (30), /* fp_div_sf */
963 COSTS_N_INSNS (59), /* fp_div_df */
964 COSTS_N_INSNS (5), /* int_mult_si */
965 COSTS_N_INSNS (9), /* int_mult_di */
966 COSTS_N_INSNS (42), /* int_div_si */
967 COSTS_N_INSNS (74), /* int_div_di */
969 4 /* memory_latency */
972 COSTS_N_INSNS (4), /* fp_add */
973 COSTS_N_INSNS (4), /* fp_mult_sf */
974 COSTS_N_INSNS (256), /* fp_mult_df */
975 COSTS_N_INSNS (8), /* fp_div_sf */
976 COSTS_N_INSNS (256), /* fp_div_df */
977 COSTS_N_INSNS (4), /* int_mult_si */
978 COSTS_N_INSNS (256), /* int_mult_di */
979 COSTS_N_INSNS (37), /* int_div_si */
980 COSTS_N_INSNS (256), /* int_div_di */
982 4 /* memory_latency */
985 /* The only costs that are changed here are
986 integer multiplication. */
987 COSTS_N_INSNS (6), /* fp_add */
988 COSTS_N_INSNS (7), /* fp_mult_sf */
989 COSTS_N_INSNS (8), /* fp_mult_df */
990 COSTS_N_INSNS (23), /* fp_div_sf */
991 COSTS_N_INSNS (36), /* fp_div_df */
992 COSTS_N_INSNS (5), /* int_mult_si */
993 COSTS_N_INSNS (9), /* int_mult_di */
994 COSTS_N_INSNS (69), /* int_div_si */
995 COSTS_N_INSNS (69), /* int_div_di */
997 4 /* memory_latency */
1003 /* The only costs that are changed here are
1004 integer multiplication. */
1005 COSTS_N_INSNS (6), /* fp_add */
1006 COSTS_N_INSNS (7), /* fp_mult_sf */
1007 COSTS_N_INSNS (8), /* fp_mult_df */
1008 COSTS_N_INSNS (23), /* fp_div_sf */
1009 COSTS_N_INSNS (36), /* fp_div_df */
1010 COSTS_N_INSNS (3), /* int_mult_si */
1011 COSTS_N_INSNS (8), /* int_mult_di */
1012 COSTS_N_INSNS (69), /* int_div_si */
1013 COSTS_N_INSNS (69), /* int_div_di */
1014 1, /* branch_cost */
1015 4 /* memory_latency */
1018 COSTS_N_INSNS (2), /* fp_add */
1019 COSTS_N_INSNS (2), /* fp_mult_sf */
1020 COSTS_N_INSNS (2), /* fp_mult_df */
1021 COSTS_N_INSNS (12), /* fp_div_sf */
1022 COSTS_N_INSNS (19), /* fp_div_df */
1023 COSTS_N_INSNS (5), /* int_mult_si */
1024 COSTS_N_INSNS (9), /* int_mult_di */
1025 COSTS_N_INSNS (34), /* int_div_si */
1026 COSTS_N_INSNS (66), /* int_div_di */
1027 1, /* branch_cost */
1028 4 /* memory_latency */
1031 /* These costs are the same as the SB-1A below. */
1032 COSTS_N_INSNS (4), /* fp_add */
1033 COSTS_N_INSNS (4), /* fp_mult_sf */
1034 COSTS_N_INSNS (4), /* fp_mult_df */
1035 COSTS_N_INSNS (24), /* fp_div_sf */
1036 COSTS_N_INSNS (32), /* fp_div_df */
1037 COSTS_N_INSNS (3), /* int_mult_si */
1038 COSTS_N_INSNS (4), /* int_mult_di */
1039 COSTS_N_INSNS (36), /* int_div_si */
1040 COSTS_N_INSNS (68), /* int_div_di */
1041 1, /* branch_cost */
1042 4 /* memory_latency */
1045 /* These costs are the same as the SB-1 above. */
1046 COSTS_N_INSNS (4), /* fp_add */
1047 COSTS_N_INSNS (4), /* fp_mult_sf */
1048 COSTS_N_INSNS (4), /* fp_mult_df */
1049 COSTS_N_INSNS (24), /* fp_div_sf */
1050 COSTS_N_INSNS (32), /* fp_div_df */
1051 COSTS_N_INSNS (3), /* int_mult_si */
1052 COSTS_N_INSNS (4), /* int_mult_di */
1053 COSTS_N_INSNS (36), /* int_div_si */
1054 COSTS_N_INSNS (68), /* int_div_di */
1055 1, /* branch_cost */
1056 4 /* memory_latency */
1063 COSTS_N_INSNS (8), /* int_mult_si */
1064 COSTS_N_INSNS (8), /* int_mult_di */
1065 COSTS_N_INSNS (72), /* int_div_si */
1066 COSTS_N_INSNS (72), /* int_div_di */
1067 1, /* branch_cost */
1068 4 /* memory_latency */
1071 /* These costs are the same as 5KF above. */
1072 COSTS_N_INSNS (4), /* fp_add */
1073 COSTS_N_INSNS (4), /* fp_mult_sf */
1074 COSTS_N_INSNS (5), /* fp_mult_df */
1075 COSTS_N_INSNS (17), /* fp_div_sf */
1076 COSTS_N_INSNS (32), /* fp_div_df */
1077 COSTS_N_INSNS (4), /* int_mult_si */
1078 COSTS_N_INSNS (11), /* int_mult_di */
1079 COSTS_N_INSNS (36), /* int_div_si */
1080 COSTS_N_INSNS (68), /* int_div_di */
1081 1, /* branch_cost */
1082 4 /* memory_latency */
1085 COSTS_N_INSNS (4), /* fp_add */
1086 COSTS_N_INSNS (5), /* fp_mult_sf */
1087 COSTS_N_INSNS (5), /* fp_mult_df */
1088 COSTS_N_INSNS (17), /* fp_div_sf */
1089 COSTS_N_INSNS (17), /* fp_div_df */
1090 COSTS_N_INSNS (5), /* int_mult_si */
1091 COSTS_N_INSNS (5), /* int_mult_di */
1092 COSTS_N_INSNS (8), /* int_div_si */
1093 COSTS_N_INSNS (8), /* int_div_di */
1094 2, /* branch_cost */
1095 4 /* memory_latency */
1098 COSTS_N_INSNS (4), /* fp_add */
1099 COSTS_N_INSNS (4), /* fp_mult_sf */
1100 COSTS_N_INSNS (5), /* fp_mult_df */
1101 COSTS_N_INSNS (17), /* fp_div_sf */
1102 COSTS_N_INSNS (32), /* fp_div_df */
1103 COSTS_N_INSNS (5), /* int_mult_si */
1104 COSTS_N_INSNS (5), /* int_mult_di */
1105 COSTS_N_INSNS (34), /* int_div_si */
1106 COSTS_N_INSNS (68), /* int_div_di */
1107 1, /* branch_cost */
1108 4 /* memory_latency */
1111 COSTS_N_INSNS (4), /* fp_add */
1112 COSTS_N_INSNS (5), /* fp_mult_sf */
1113 COSTS_N_INSNS (5), /* fp_mult_df */
1114 COSTS_N_INSNS (32), /* fp_div_sf */
1115 COSTS_N_INSNS (32), /* fp_div_df */
1116 COSTS_N_INSNS (5), /* int_mult_si */
1117 COSTS_N_INSNS (5), /* int_mult_di */
1118 COSTS_N_INSNS (36), /* int_div_si */
1119 COSTS_N_INSNS (36), /* int_div_di */
1120 2, /* branch_cost */
1121 4 /* memory_latency */
1125 static rtx mips_find_pic_call_symbol (rtx_insn *, rtx, bool);
1126 static int mips_register_move_cost (machine_mode, reg_class_t,
1128 static unsigned int mips_function_arg_boundary (machine_mode, const_tree);
1129 static machine_mode mips_get_reg_raw_mode (int regno);
1131 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1132 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1133 static GTY (()) hash_map<nofree_string_hash, bool> *mflip_mips16_htab;
1135 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1136 mode, false if it should next add an attribute for the opposite mode. */
1137 static GTY(()) bool mips16_flipper;
1139 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1140 for -mflip-mips16. Return true if it should use "mips16" and false if
1141 it should use "nomips16". */
1144 mflip_mips16_use_mips16_p (tree decl)
1147 bool base_is_mips16 = (mips_base_compression_flags & MASK_MIPS16) != 0;
1149 /* Use the opposite of the command-line setting for anonymous decls. */
1150 if (!DECL_NAME (decl))
1151 return !base_is_mips16;
1153 if (!mflip_mips16_htab)
1154 mflip_mips16_htab = hash_map<nofree_string_hash, bool>::create_ggc (37);
1156 name = IDENTIFIER_POINTER (DECL_NAME (decl));
1159 bool *slot = &mflip_mips16_htab->get_or_insert (name, &existed);
1162 mips16_flipper = !mips16_flipper;
1163 *slot = mips16_flipper ? !base_is_mips16 : base_is_mips16;
1168 /* Predicates to test for presence of "near" and "far"/"long_call"
1169 attributes on the given TYPE. */
1172 mips_near_type_p (const_tree type)
1174 return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL;
1178 mips_far_type_p (const_tree type)
1180 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL
1181 || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL);
1185 /* Check if the interrupt attribute is set for a function. */
1188 mips_interrupt_type_p (tree type)
1190 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type)) != NULL;
1193 /* Return the mask for the "interrupt" attribute. */
1195 static enum mips_int_mask
1196 mips_interrupt_mask (tree type)
1198 tree attr = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type));
1202 /* For missing attributes or no arguments then return 'eic' as a safe
1205 return INT_MASK_EIC;
1207 args = TREE_VALUE (attr);
1210 return INT_MASK_EIC;
1212 cst = TREE_VALUE (args);
1214 if (strcmp (TREE_STRING_POINTER (cst), "eic") == 0)
1215 return INT_MASK_EIC;
1217 /* The validation code in mips_handle_interrupt_attr guarantees that the
1218 argument is now in the form:
1219 vector=(sw0|sw1|hw0|hw1|hw2|hw3|hw4|hw5). */
1220 str = TREE_STRING_POINTER (cst);
1222 gcc_assert (strlen (str) == strlen ("vector=sw0"));
1225 return (enum mips_int_mask) (INT_MASK_SW0 + (str[9] - '0'));
1227 return (enum mips_int_mask) (INT_MASK_HW0 + (str[9] - '0'));
1230 /* Return the mips_shadow_set if the "use_shadow_register_set" attribute is
1231 set for a function. */
1233 static enum mips_shadow_set
1234 mips_use_shadow_register_set (tree type)
1236 tree attr = lookup_attribute ("use_shadow_register_set",
1237 TYPE_ATTRIBUTES (type));
1240 /* The validation code in mips_handle_use_shadow_register_set_attr guarantees
1241 that if an argument is present then it means: Assume the shadow register
1242 set has a valid stack pointer in it. */
1244 return SHADOW_SET_NO;
1246 args = TREE_VALUE (attr);
1249 return SHADOW_SET_YES;
1251 return SHADOW_SET_INTSTACK;
1254 /* Check if the attribute to keep interrupts masked is set for a function. */
1257 mips_keep_interrupts_masked_p (tree type)
1259 return lookup_attribute ("keep_interrupts_masked",
1260 TYPE_ATTRIBUTES (type)) != NULL;
1263 /* Check if the attribute to use debug exception return is set for
1267 mips_use_debug_exception_return_p (tree type)
1269 return lookup_attribute ("use_debug_exception_return",
1270 TYPE_ATTRIBUTES (type)) != NULL;
1273 /* Return the set of compression modes that are explicitly required
1274 by the attributes in ATTRIBUTES. */
1277 mips_get_compress_on_flags (tree attributes)
1279 unsigned int flags = 0;
1281 if (lookup_attribute ("mips16", attributes) != NULL)
1282 flags |= MASK_MIPS16;
1284 if (lookup_attribute ("micromips", attributes) != NULL)
1285 flags |= MASK_MICROMIPS;
1290 /* Return the set of compression modes that are explicitly forbidden
1291 by the attributes in ATTRIBUTES. */
1294 mips_get_compress_off_flags (tree attributes)
1296 unsigned int flags = 0;
1298 if (lookup_attribute ("nocompression", attributes) != NULL)
1299 flags |= MASK_MIPS16 | MASK_MICROMIPS;
1301 if (lookup_attribute ("nomips16", attributes) != NULL)
1302 flags |= MASK_MIPS16;
1304 if (lookup_attribute ("nomicromips", attributes) != NULL)
1305 flags |= MASK_MICROMIPS;
1310 /* Return the compression mode that should be used for function DECL.
1311 Return the ambient setting if DECL is null. */
1314 mips_get_compress_mode (tree decl)
1316 unsigned int flags, force_on;
1318 flags = mips_base_compression_flags;
1321 /* Nested functions must use the same frame pointer as their
1322 parent and must therefore use the same ISA mode. */
1323 tree parent = decl_function_context (decl);
1326 force_on = mips_get_compress_on_flags (DECL_ATTRIBUTES (decl));
1329 flags &= ~mips_get_compress_off_flags (DECL_ATTRIBUTES (decl));
1334 /* Return the attribute name associated with MASK_MIPS16 and MASK_MICROMIPS
1338 mips_get_compress_on_name (unsigned int flags)
1340 if (flags == MASK_MIPS16)
1345 /* Return the attribute name that forbids MASK_MIPS16 and MASK_MICROMIPS
1349 mips_get_compress_off_name (unsigned int flags)
1351 if (flags == MASK_MIPS16)
1353 if (flags == MASK_MICROMIPS)
1354 return "nomicromips";
1355 return "nocompression";
1358 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1361 mips_comp_type_attributes (const_tree type1, const_tree type2)
1363 /* Disallow mixed near/far attributes. */
1364 if (mips_far_type_p (type1) && mips_near_type_p (type2))
1366 if (mips_near_type_p (type1) && mips_far_type_p (type2))
1371 /* Implement TARGET_INSERT_ATTRIBUTES. */
1374 mips_insert_attributes (tree decl, tree *attributes)
1377 unsigned int compression_flags, nocompression_flags;
1379 /* Check for "mips16" and "nomips16" attributes. */
1380 compression_flags = mips_get_compress_on_flags (*attributes);
1381 nocompression_flags = mips_get_compress_off_flags (*attributes);
1383 if (TREE_CODE (decl) != FUNCTION_DECL)
1385 if (nocompression_flags)
1386 error ("%qs attribute only applies to functions",
1387 mips_get_compress_off_name (nocompression_flags));
1389 if (compression_flags)
1390 error ("%qs attribute only applies to functions",
1391 mips_get_compress_on_name (nocompression_flags));
1395 compression_flags |= mips_get_compress_on_flags (DECL_ATTRIBUTES (decl));
1396 nocompression_flags |=
1397 mips_get_compress_off_flags (DECL_ATTRIBUTES (decl));
1399 if (compression_flags && nocompression_flags)
1400 error ("%qE cannot have both %qs and %qs attributes",
1401 DECL_NAME (decl), mips_get_compress_on_name (compression_flags),
1402 mips_get_compress_off_name (nocompression_flags));
1404 if (compression_flags & MASK_MIPS16
1405 && compression_flags & MASK_MICROMIPS)
1406 error ("%qE cannot have both %qs and %qs attributes",
1407 DECL_NAME (decl), "mips16", "micromips");
1409 if (TARGET_FLIP_MIPS16
1410 && !DECL_ARTIFICIAL (decl)
1411 && compression_flags == 0
1412 && nocompression_flags == 0)
1414 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1415 "mips16" attribute, arbitrarily pick one. We must pick the same
1416 setting for duplicate declarations of a function. */
1417 name = mflip_mips16_use_mips16_p (decl) ? "mips16" : "nomips16";
1418 *attributes = tree_cons (get_identifier (name), NULL, *attributes);
1419 name = "nomicromips";
1420 *attributes = tree_cons (get_identifier (name), NULL, *attributes);
1425 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1428 mips_merge_decl_attributes (tree olddecl, tree newdecl)
1432 diff = (mips_get_compress_on_flags (DECL_ATTRIBUTES (olddecl))
1433 ^ mips_get_compress_on_flags (DECL_ATTRIBUTES (newdecl)));
1435 error ("%qE redeclared with conflicting %qs attributes",
1436 DECL_NAME (newdecl), mips_get_compress_on_name (diff));
1438 diff = (mips_get_compress_off_flags (DECL_ATTRIBUTES (olddecl))
1439 ^ mips_get_compress_off_flags (DECL_ATTRIBUTES (newdecl)));
1441 error ("%qE redeclared with conflicting %qs attributes",
1442 DECL_NAME (newdecl), mips_get_compress_off_name (diff));
1444 return merge_attributes (DECL_ATTRIBUTES (olddecl),
1445 DECL_ATTRIBUTES (newdecl));
1448 /* Implement TARGET_CAN_INLINE_P. */
1451 mips_can_inline_p (tree caller, tree callee)
1453 if (mips_get_compress_mode (callee) != mips_get_compress_mode (caller))
1455 return default_target_can_inline_p (caller, callee);
1458 /* Handle an "interrupt" attribute with an optional argument. */
1461 mips_handle_interrupt_attr (tree *node ATTRIBUTE_UNUSED, tree name, tree args,
1462 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
1464 /* Check for an argument. */
1465 if (is_attribute_p ("interrupt", name) && args != NULL)
1469 cst = TREE_VALUE (args);
1470 if (TREE_CODE (cst) != STRING_CST)
1472 warning (OPT_Wattributes,
1473 "%qE attribute requires a string argument",
1475 *no_add_attrs = true;
1477 else if (strcmp (TREE_STRING_POINTER (cst), "eic") != 0
1478 && strncmp (TREE_STRING_POINTER (cst), "vector=", 7) != 0)
1480 warning (OPT_Wattributes,
1481 "argument to %qE attribute is neither eic, nor "
1482 "vector=<line>", name);
1483 *no_add_attrs = true;
1485 else if (strncmp (TREE_STRING_POINTER (cst), "vector=", 7) == 0)
1487 const char *arg = TREE_STRING_POINTER (cst) + 7;
1489 /* Acceptable names are: sw0,sw1,hw0,hw1,hw2,hw3,hw4,hw5. */
1490 if (strlen (arg) != 3
1491 || (arg[0] != 's' && arg[0] != 'h')
1493 || (arg[0] == 's' && arg[2] != '0' && arg[2] != '1')
1494 || (arg[0] == 'h' && (arg[2] < '0' || arg[2] > '5')))
1496 warning (OPT_Wattributes,
1497 "interrupt vector to %qE attribute is not "
1498 "vector=(sw0|sw1|hw0|hw1|hw2|hw3|hw4|hw5)",
1500 *no_add_attrs = true;
1510 /* Handle a "use_shadow_register_set" attribute with an optional argument. */
1513 mips_handle_use_shadow_register_set_attr (tree *node ATTRIBUTE_UNUSED,
1514 tree name, tree args,
1515 int flags ATTRIBUTE_UNUSED,
1518 /* Check for an argument. */
1519 if (is_attribute_p ("use_shadow_register_set", name) && args != NULL)
1523 cst = TREE_VALUE (args);
1524 if (TREE_CODE (cst) != STRING_CST)
1526 warning (OPT_Wattributes,
1527 "%qE attribute requires a string argument",
1529 *no_add_attrs = true;
1531 else if (strcmp (TREE_STRING_POINTER (cst), "intstack") != 0)
1533 warning (OPT_Wattributes,
1534 "argument to %qE attribute is not intstack", name);
1535 *no_add_attrs = true;
1544 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1545 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1548 mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr)
1550 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
1552 *base_ptr = XEXP (x, 0);
1553 *offset_ptr = INTVAL (XEXP (x, 1));
1562 static unsigned int mips_build_integer (struct mips_integer_op *,
1563 unsigned HOST_WIDE_INT);
1565 /* A subroutine of mips_build_integer, with the same interface.
1566 Assume that the final action in the sequence should be a left shift. */
1569 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1571 unsigned int i, shift;
1573 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1574 since signed numbers are easier to load than unsigned ones. */
1576 while ((value & 1) == 0)
1577 value /= 2, shift++;
1579 i = mips_build_integer (codes, value);
1580 codes[i].code = ASHIFT;
1581 codes[i].value = shift;
1585 /* As for mips_build_shift, but assume that the final action will be
1586 an IOR or PLUS operation. */
1589 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1591 unsigned HOST_WIDE_INT high;
1594 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1595 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
1597 /* The constant is too complex to load with a simple LUI/ORI pair,
1598 so we want to give the recursive call as many trailing zeros as
1599 possible. In this case, we know bit 16 is set and that the
1600 low 16 bits form a negative number. If we subtract that number
1601 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1602 i = mips_build_integer (codes, CONST_HIGH_PART (value));
1603 codes[i].code = PLUS;
1604 codes[i].value = CONST_LOW_PART (value);
1608 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1609 bits gives a value with at least 17 trailing zeros. */
1610 i = mips_build_integer (codes, high);
1611 codes[i].code = IOR;
1612 codes[i].value = value & 0xffff;
1617 /* Fill CODES with a sequence of rtl operations to load VALUE.
1618 Return the number of operations needed. */
1621 mips_build_integer (struct mips_integer_op *codes,
1622 unsigned HOST_WIDE_INT value)
1624 if (SMALL_OPERAND (value)
1625 || SMALL_OPERAND_UNSIGNED (value)
1626 || LUI_OPERAND (value))
1628 /* The value can be loaded with a single instruction. */
1629 codes[0].code = UNKNOWN;
1630 codes[0].value = value;
1633 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
1635 /* Either the constant is a simple LUI/ORI combination or its
1636 lowest bit is set. We don't want to shift in this case. */
1637 return mips_build_lower (codes, value);
1639 else if ((value & 0xffff) == 0)
1641 /* The constant will need at least three actions. The lowest
1642 16 bits are clear, so the final action will be a shift. */
1643 return mips_build_shift (codes, value);
1647 /* The final action could be a shift, add or inclusive OR.
1648 Rather than use a complex condition to select the best
1649 approach, try both mips_build_shift and mips_build_lower
1650 and pick the one that gives the shortest sequence.
1651 Note that this case is only used once per constant. */
1652 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1653 unsigned int cost, alt_cost;
1655 cost = mips_build_shift (codes, value);
1656 alt_cost = mips_build_lower (alt_codes, value);
1657 if (alt_cost < cost)
1659 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
1666 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
1669 mips_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
1671 return mips_const_insns (x) > 0;
1674 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
1677 mips16_stub_function (const char *name)
1681 x = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
1682 SYMBOL_REF_FLAGS (x) |= (SYMBOL_FLAG_EXTERNAL | SYMBOL_FLAG_FUNCTION);
1686 /* Return a legitimate call address for STUB, given that STUB is a MIPS16
1687 support function. */
1690 mips16_stub_call_address (mips_one_only_stub *stub)
1692 rtx fn = mips16_stub_function (stub->get_name ());
1693 SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_LOCAL;
1694 if (!call_insn_operand (fn, VOIDmode))
1695 fn = force_reg (Pmode, fn);
1699 /* A stub for moving the thread pointer into TLS_GET_TP_REGNUM. */
1701 class mips16_rdhwr_one_only_stub : public mips_one_only_stub
1703 virtual const char *get_name ();
1704 virtual void output_body ();
1708 mips16_rdhwr_one_only_stub::get_name ()
1710 return "__mips16_rdhwr";
1714 mips16_rdhwr_one_only_stub::output_body ()
1716 fprintf (asm_out_file,
1718 "\t.set\tmips32r2\n"
1719 "\t.set\tnoreorder\n"
1725 /* A stub for moving the FCSR into GET_FCSR_REGNUM. */
1726 class mips16_get_fcsr_one_only_stub : public mips_one_only_stub
1728 virtual const char *get_name ();
1729 virtual void output_body ();
1733 mips16_get_fcsr_one_only_stub::get_name ()
1735 return "__mips16_get_fcsr";
1739 mips16_get_fcsr_one_only_stub::output_body ()
1741 fprintf (asm_out_file,
1743 "\tj\t$31\n", reg_names[GET_FCSR_REGNUM]);
1746 /* A stub for moving SET_FCSR_REGNUM into the FCSR. */
1747 class mips16_set_fcsr_one_only_stub : public mips_one_only_stub
1749 virtual const char *get_name ();
1750 virtual void output_body ();
1754 mips16_set_fcsr_one_only_stub::get_name ()
1756 return "__mips16_set_fcsr";
1760 mips16_set_fcsr_one_only_stub::output_body ()
1762 fprintf (asm_out_file,
1764 "\tj\t$31\n", reg_names[SET_FCSR_REGNUM]);
1767 /* Return true if symbols of type TYPE require a GOT access. */
1770 mips_got_symbol_type_p (enum mips_symbol_type type)
1774 case SYMBOL_GOT_PAGE_OFST:
1775 case SYMBOL_GOT_DISP:
1783 /* Return true if X is a thread-local symbol. */
1786 mips_tls_symbol_p (rtx x)
1788 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1791 /* Return true if SYMBOL_REF X is associated with a global symbol
1792 (in the STB_GLOBAL sense). */
1795 mips_global_symbol_p (const_rtx x)
1797 const_tree decl = SYMBOL_REF_DECL (x);
1800 return !SYMBOL_REF_LOCAL_P (x) || SYMBOL_REF_EXTERNAL_P (x);
1802 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1803 or weak symbols. Relocations in the object file will be against
1804 the target symbol, so it's that symbol's binding that matters here. */
1805 return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl));
1808 /* Return true if function X is a libgcc MIPS16 stub function. */
1811 mips16_stub_function_p (const_rtx x)
1813 return (GET_CODE (x) == SYMBOL_REF
1814 && strncmp (XSTR (x, 0), "__mips16_", 9) == 0);
1817 /* Return true if function X is a locally-defined and locally-binding
1821 mips16_local_function_p (const_rtx x)
1823 return (GET_CODE (x) == SYMBOL_REF
1824 && SYMBOL_REF_LOCAL_P (x)
1825 && !SYMBOL_REF_EXTERNAL_P (x)
1826 && (mips_get_compress_mode (SYMBOL_REF_DECL (x)) & MASK_MIPS16));
1829 /* Return true if SYMBOL_REF X binds locally. */
1832 mips_symbol_binds_local_p (const_rtx x)
1834 return (SYMBOL_REF_DECL (x)
1835 ? targetm.binds_local_p (SYMBOL_REF_DECL (x))
1836 : SYMBOL_REF_LOCAL_P (x));
1839 /* Return true if rtx constants of mode MODE should be put into a small
1843 mips_rtx_constant_in_small_data_p (machine_mode mode)
1845 return (!TARGET_EMBEDDED_DATA
1846 && TARGET_LOCAL_SDATA
1847 && GET_MODE_SIZE (mode) <= mips_small_data_threshold);
1850 /* Return true if X should not be moved directly into register $25.
1851 We need this because many versions of GAS will treat "la $25,foo" as
1852 part of a call sequence and so allow a global "foo" to be lazily bound. */
1855 mips_dangerous_for_la25_p (rtx x)
1857 return (!TARGET_EXPLICIT_RELOCS
1859 && GET_CODE (x) == SYMBOL_REF
1860 && mips_global_symbol_p (x));
1863 /* Return true if calls to X might need $25 to be valid on entry. */
1866 mips_use_pic_fn_addr_reg_p (const_rtx x)
1868 if (!TARGET_USE_PIC_FN_ADDR_REG)
1871 /* MIPS16 stub functions are guaranteed not to use $25. */
1872 if (mips16_stub_function_p (x))
1875 if (GET_CODE (x) == SYMBOL_REF)
1877 /* If PLTs and copy relocations are available, the static linker
1878 will make sure that $25 is valid on entry to the target function. */
1879 if (TARGET_ABICALLS_PIC0)
1882 /* Locally-defined functions use absolute accesses to set up
1883 the global pointer. */
1884 if (TARGET_ABSOLUTE_ABICALLS
1885 && mips_symbol_binds_local_p (x)
1886 && !SYMBOL_REF_EXTERNAL_P (x))
1893 /* Return the method that should be used to access SYMBOL_REF or
1894 LABEL_REF X in context CONTEXT. */
1896 static enum mips_symbol_type
1897 mips_classify_symbol (const_rtx x, enum mips_symbol_context context)
1900 return SYMBOL_GOT_DISP;
1902 if (GET_CODE (x) == LABEL_REF)
1904 /* Only return SYMBOL_PC_RELATIVE if we are generating MIPS16
1905 code and if we know that the label is in the current function's
1906 text section. LABEL_REFs are used for jump tables as well as
1907 text labels, so we must check whether jump tables live in the
1909 if (TARGET_MIPS16_SHORT_JUMP_TABLES
1910 && !LABEL_REF_NONLOCAL_P (x))
1911 return SYMBOL_PC_RELATIVE;
1913 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1914 return SYMBOL_GOT_PAGE_OFST;
1916 return SYMBOL_ABSOLUTE;
1919 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1921 if (SYMBOL_REF_TLS_MODEL (x))
1924 if (CONSTANT_POOL_ADDRESS_P (x))
1926 if (TARGET_MIPS16_TEXT_LOADS)
1927 return SYMBOL_PC_RELATIVE;
1929 if (TARGET_MIPS16_PCREL_LOADS && context == SYMBOL_CONTEXT_MEM)
1930 return SYMBOL_PC_RELATIVE;
1932 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x)))
1933 return SYMBOL_GP_RELATIVE;
1936 /* Do not use small-data accesses for weak symbols; they may end up
1938 if (TARGET_GPOPT && SYMBOL_REF_SMALL_P (x) && !SYMBOL_REF_WEAK (x))
1939 return SYMBOL_GP_RELATIVE;
1941 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1943 if (TARGET_ABICALLS_PIC2
1944 && !(TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x)))
1946 /* There are three cases to consider:
1948 - o32 PIC (either with or without explicit relocs)
1949 - n32/n64 PIC without explicit relocs
1950 - n32/n64 PIC with explicit relocs
1952 In the first case, both local and global accesses will use an
1953 R_MIPS_GOT16 relocation. We must correctly predict which of
1954 the two semantics (local or global) the assembler and linker
1955 will apply. The choice depends on the symbol's binding rather
1956 than its visibility.
1958 In the second case, the assembler will not use R_MIPS_GOT16
1959 relocations, but it chooses between local and global accesses
1960 in the same way as for o32 PIC.
1962 In the third case we have more freedom since both forms of
1963 access will work for any kind of symbol. However, there seems
1964 little point in doing things differently. */
1965 if (mips_global_symbol_p (x))
1966 return SYMBOL_GOT_DISP;
1968 return SYMBOL_GOT_PAGE_OFST;
1971 return SYMBOL_ABSOLUTE;
1974 /* Classify the base of symbolic expression X, given that X appears in
1977 static enum mips_symbol_type
1978 mips_classify_symbolic_expression (rtx x, enum mips_symbol_context context)
1982 split_const (x, &x, &offset);
1983 if (UNSPEC_ADDRESS_P (x))
1984 return UNSPEC_ADDRESS_TYPE (x);
1986 return mips_classify_symbol (x, context);
1989 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1990 is the alignment in bytes of SYMBOL_REF X. */
1993 mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset)
1995 HOST_WIDE_INT align;
1997 align = SYMBOL_REF_DECL (x) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x)) : 1;
1998 return IN_RANGE (offset, 0, align - 1);
2001 /* Return true if X is a symbolic constant that can be used in context
2002 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
2005 mips_symbolic_constant_p (rtx x, enum mips_symbol_context context,
2006 enum mips_symbol_type *symbol_type)
2010 split_const (x, &x, &offset);
2011 if (UNSPEC_ADDRESS_P (x))
2013 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
2014 x = UNSPEC_ADDRESS (x);
2016 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
2018 *symbol_type = mips_classify_symbol (x, context);
2019 if (*symbol_type == SYMBOL_TLS)
2025 if (offset == const0_rtx)
2028 /* Check whether a nonzero offset is valid for the underlying
2030 switch (*symbol_type)
2032 case SYMBOL_ABSOLUTE:
2033 case SYMBOL_64_HIGH:
2036 /* If the target has 64-bit pointers and the object file only
2037 supports 32-bit symbols, the values of those symbols will be
2038 sign-extended. In this case we can't allow an arbitrary offset
2039 in case the 32-bit value X + OFFSET has a different sign from X. */
2040 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
2041 return offset_within_block_p (x, INTVAL (offset));
2043 /* In other cases the relocations can handle any offset. */
2046 case SYMBOL_PC_RELATIVE:
2047 /* Allow constant pool references to be converted to LABEL+CONSTANT.
2048 In this case, we no longer have access to the underlying constant,
2049 but the original symbol-based access was known to be valid. */
2050 if (GET_CODE (x) == LABEL_REF)
2055 case SYMBOL_GP_RELATIVE:
2056 /* Make sure that the offset refers to something within the
2057 same object block. This should guarantee that the final
2058 PC- or GP-relative offset is within the 16-bit limit. */
2059 return offset_within_block_p (x, INTVAL (offset));
2061 case SYMBOL_GOT_PAGE_OFST:
2062 case SYMBOL_GOTOFF_PAGE:
2063 /* If the symbol is global, the GOT entry will contain the symbol's
2064 address, and we will apply a 16-bit offset after loading it.
2065 If the symbol is local, the linker should provide enough local
2066 GOT entries for a 16-bit offset, but larger offsets may lead
2068 return SMALL_INT (offset);
2072 /* There is no carry between the HI and LO REL relocations, so the
2073 offset is only valid if we know it won't lead to such a carry. */
2074 return mips_offset_within_alignment_p (x, INTVAL (offset));
2076 case SYMBOL_GOT_DISP:
2077 case SYMBOL_GOTOFF_DISP:
2078 case SYMBOL_GOTOFF_CALL:
2079 case SYMBOL_GOTOFF_LOADGP:
2082 case SYMBOL_GOTTPREL:
2090 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
2091 single instruction. We rely on the fact that, in the worst case,
2092 all instructions involved in a MIPS16 address calculation are usually
2096 mips_symbol_insns_1 (enum mips_symbol_type type, machine_mode mode)
2098 if (mips_use_pcrel_pool_p[(int) type])
2100 if (mode == MAX_MACHINE_MODE)
2101 /* LEAs will be converted into constant-pool references by
2103 type = SYMBOL_PC_RELATIVE;
2105 /* The constant must be loaded and then dereferenced. */
2111 case SYMBOL_ABSOLUTE:
2112 /* When using 64-bit symbols, we need 5 preparatory instructions,
2115 lui $at,%highest(symbol)
2116 daddiu $at,$at,%higher(symbol)
2118 daddiu $at,$at,%hi(symbol)
2121 The final address is then $at + %lo(symbol). With 32-bit
2122 symbols we just need a preparatory LUI for normal mode and
2123 a preparatory LI and SLL for MIPS16. */
2124 return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2;
2126 case SYMBOL_GP_RELATIVE:
2127 /* Treat GP-relative accesses as taking a single instruction on
2128 MIPS16 too; the copy of $gp can often be shared. */
2131 case SYMBOL_PC_RELATIVE:
2132 /* PC-relative constants can be only be used with ADDIUPC,
2133 DADDIUPC, LWPC and LDPC. */
2134 if (mode == MAX_MACHINE_MODE
2135 || GET_MODE_SIZE (mode) == 4
2136 || GET_MODE_SIZE (mode) == 8)
2139 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
2142 case SYMBOL_GOT_DISP:
2143 /* The constant will have to be loaded from the GOT before it
2144 is used in an address. */
2145 if (mode != MAX_MACHINE_MODE)
2150 case SYMBOL_GOT_PAGE_OFST:
2151 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
2152 local/global classification is accurate. The worst cases are:
2154 (1) For local symbols when generating o32 or o64 code. The assembler
2160 ...and the final address will be $at + %lo(symbol).
2162 (2) For global symbols when -mxgot. The assembler will use:
2164 lui $at,%got_hi(symbol)
2167 ...and the final address will be $at + %got_lo(symbol). */
2170 case SYMBOL_GOTOFF_PAGE:
2171 case SYMBOL_GOTOFF_DISP:
2172 case SYMBOL_GOTOFF_CALL:
2173 case SYMBOL_GOTOFF_LOADGP:
2174 case SYMBOL_64_HIGH:
2180 case SYMBOL_GOTTPREL:
2183 /* A 16-bit constant formed by a single relocation, or a 32-bit
2184 constant formed from a high 16-bit relocation and a low 16-bit
2185 relocation. Use mips_split_p to determine which. 32-bit
2186 constants need an "lui; addiu" sequence for normal mode and
2187 an "li; sll; addiu" sequence for MIPS16 mode. */
2188 return !mips_split_p[type] ? 1 : TARGET_MIPS16 ? 3 : 2;
2191 /* We don't treat a bare TLS symbol as a constant. */
2197 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
2198 to load symbols of type TYPE into a register. Return 0 if the given
2199 type of symbol cannot be used as an immediate operand.
2201 Otherwise, return the number of instructions needed to load or store
2202 values of mode MODE to or from addresses of type TYPE. Return 0 if
2203 the given type of symbol is not valid in addresses.
2205 In both cases, instruction counts are based off BASE_INSN_LENGTH. */
2208 mips_symbol_insns (enum mips_symbol_type type, machine_mode mode)
2210 return mips_symbol_insns_1 (type, mode) * (TARGET_MIPS16 ? 2 : 1);
2213 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
2216 mips_cannot_force_const_mem (machine_mode mode, rtx x)
2218 enum mips_symbol_type type;
2221 /* There is no assembler syntax for expressing an address-sized
2223 if (GET_CODE (x) == HIGH)
2226 /* As an optimization, reject constants that mips_legitimize_move
2229 Suppose we have a multi-instruction sequence that loads constant C
2230 into register R. If R does not get allocated a hard register, and
2231 R is used in an operand that allows both registers and memory
2232 references, reload will consider forcing C into memory and using
2233 one of the instruction's memory alternatives. Returning false
2234 here will force it to use an input reload instead. */
2235 if (CONST_INT_P (x) && mips_legitimate_constant_p (mode, x))
2238 split_const (x, &base, &offset);
2239 if (mips_symbolic_constant_p (base, SYMBOL_CONTEXT_LEA, &type))
2241 /* See whether we explicitly want these symbols in the pool. */
2242 if (mips_use_pcrel_pool_p[(int) type])
2245 /* The same optimization as for CONST_INT. */
2246 if (SMALL_INT (offset) && mips_symbol_insns (type, MAX_MACHINE_MODE) > 0)
2249 /* If MIPS16 constant pools live in the text section, they should
2250 not refer to anything that might need run-time relocation. */
2251 if (TARGET_MIPS16_PCREL_LOADS && mips_got_symbol_type_p (type))
2255 /* TLS symbols must be computed by mips_legitimize_move. */
2256 if (tls_referenced_p (x))
2262 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
2263 constants when we're using a per-function constant pool. */
2266 mips_use_blocks_for_constant_p (machine_mode mode ATTRIBUTE_UNUSED,
2267 const_rtx x ATTRIBUTE_UNUSED)
2269 return !TARGET_MIPS16_PCREL_LOADS;
2272 /* Return true if register REGNO is a valid base register for mode MODE.
2273 STRICT_P is true if REG_OK_STRICT is in effect. */
2276 mips_regno_mode_ok_for_base_p (int regno, machine_mode mode,
2279 if (!HARD_REGISTER_NUM_P (regno))
2283 regno = reg_renumber[regno];
2286 /* These fake registers will be eliminated to either the stack or
2287 hard frame pointer, both of which are usually valid base registers.
2288 Reload deals with the cases where the eliminated form isn't valid. */
2289 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
2292 /* In MIPS16 mode, the stack pointer can only address word and doubleword
2293 values, nothing smaller. */
2294 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
2295 return GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
2297 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
2300 /* Return true if X is a valid base register for mode MODE.
2301 STRICT_P is true if REG_OK_STRICT is in effect. */
2304 mips_valid_base_register_p (rtx x, machine_mode mode, bool strict_p)
2306 if (!strict_p && GET_CODE (x) == SUBREG)
2310 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p));
2313 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2314 can address a value of mode MODE. */
2317 mips_valid_offset_p (rtx x, machine_mode mode)
2319 /* Check that X is a signed 16-bit number. */
2320 if (!const_arith_operand (x, Pmode))
2323 /* We may need to split multiword moves, so make sure that every word
2325 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2326 && !SMALL_OPERAND (INTVAL (x) + GET_MODE_SIZE (mode) - UNITS_PER_WORD))
2332 /* Return true if a LO_SUM can address a value of mode MODE when the
2333 LO_SUM symbol has type SYMBOL_TYPE. */
2336 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type, machine_mode mode)
2338 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2340 if (mips_symbol_insns (symbol_type, mode) == 0)
2343 /* Check that there is a known low-part relocation. */
2344 if (mips_lo_relocs[symbol_type] == NULL)
2347 /* We may need to split multiword moves, so make sure that each word
2348 can be accessed without inducing a carry. This is mainly needed
2349 for o64, which has historically only guaranteed 64-bit alignment
2350 for 128-bit types. */
2351 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2352 && GET_MODE_BITSIZE (mode) > GET_MODE_ALIGNMENT (mode))
2358 /* Return true if X is a valid address for machine mode MODE. If it is,
2359 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2363 mips_classify_address (struct mips_address_info *info, rtx x,
2364 machine_mode mode, bool strict_p)
2366 switch (GET_CODE (x))
2370 info->type = ADDRESS_REG;
2372 info->offset = const0_rtx;
2373 return mips_valid_base_register_p (info->reg, mode, strict_p);
2376 info->type = ADDRESS_REG;
2377 info->reg = XEXP (x, 0);
2378 info->offset = XEXP (x, 1);
2379 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2380 && mips_valid_offset_p (info->offset, mode));
2383 info->type = ADDRESS_LO_SUM;
2384 info->reg = XEXP (x, 0);
2385 info->offset = XEXP (x, 1);
2386 /* We have to trust the creator of the LO_SUM to do something vaguely
2387 sane. Target-independent code that creates a LO_SUM should also
2388 create and verify the matching HIGH. Target-independent code that
2389 adds an offset to a LO_SUM must prove that the offset will not
2390 induce a carry. Failure to do either of these things would be
2391 a bug, and we are not required to check for it here. The MIPS
2392 backend itself should only create LO_SUMs for valid symbolic
2393 constants, with the high part being either a HIGH or a copy
2396 = mips_classify_symbolic_expression (info->offset, SYMBOL_CONTEXT_MEM);
2397 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2398 && mips_valid_lo_sum_p (info->symbol_type, mode));
2401 /* Small-integer addresses don't occur very often, but they
2402 are legitimate if $0 is a valid base register. */
2403 info->type = ADDRESS_CONST_INT;
2404 return !TARGET_MIPS16 && SMALL_INT (x);
2409 info->type = ADDRESS_SYMBOLIC;
2410 return (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_MEM,
2412 && mips_symbol_insns (info->symbol_type, mode) > 0
2413 && !mips_split_p[info->symbol_type]);
2420 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2423 mips_legitimate_address_p (machine_mode mode, rtx x, bool strict_p)
2425 struct mips_address_info addr;
2427 return mips_classify_address (&addr, x, mode, strict_p);
2430 /* Return true if X is a legitimate $sp-based address for mode MODE. */
2433 mips_stack_address_p (rtx x, machine_mode mode)
2435 struct mips_address_info addr;
2437 return (mips_classify_address (&addr, x, mode, false)
2438 && addr.type == ADDRESS_REG
2439 && addr.reg == stack_pointer_rtx);
2442 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2443 address instruction. Note that such addresses are not considered
2444 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2445 is so restricted. */
2448 mips_lwxs_address_p (rtx addr)
2451 && GET_CODE (addr) == PLUS
2452 && REG_P (XEXP (addr, 1)))
2454 rtx offset = XEXP (addr, 0);
2455 if (GET_CODE (offset) == MULT
2456 && REG_P (XEXP (offset, 0))
2457 && CONST_INT_P (XEXP (offset, 1))
2458 && INTVAL (XEXP (offset, 1)) == 4)
2464 /* Return true if ADDR matches the pattern for the L{B,H,W,D}{,U}X load
2465 indexed address instruction. Note that such addresses are
2466 not considered legitimate in the TARGET_LEGITIMATE_ADDRESS_P
2467 sense, because their use is so restricted. */
2470 mips_lx_address_p (rtx addr, machine_mode mode)
2472 if (GET_CODE (addr) != PLUS
2473 || !REG_P (XEXP (addr, 0))
2474 || !REG_P (XEXP (addr, 1)))
2476 if (ISA_HAS_LBX && mode == QImode)
2478 if (ISA_HAS_LHX && mode == HImode)
2480 if (ISA_HAS_LWX && mode == SImode)
2482 if (ISA_HAS_LDX && mode == DImode)
2487 /* Return true if a value at OFFSET bytes from base register BASE can be
2488 accessed using an unextended MIPS16 instruction. MODE is the mode of
2491 Usually the offset in an unextended instruction is a 5-bit field.
2492 The offset is unsigned and shifted left once for LH and SH, twice
2493 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2494 an 8-bit immediate field that's shifted left twice. */
2497 mips16_unextended_reference_p (machine_mode mode, rtx base,
2498 unsigned HOST_WIDE_INT offset)
2500 if (mode != BLKmode && offset % GET_MODE_SIZE (mode) == 0)
2502 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
2503 return offset < 256U * GET_MODE_SIZE (mode);
2504 return offset < 32U * GET_MODE_SIZE (mode);
2509 /* Return the number of instructions needed to load or store a value
2510 of mode MODE at address X, assuming that BASE_INSN_LENGTH is the
2511 length of one instruction. Return 0 if X isn't valid for MODE.
2512 Assume that multiword moves may need to be split into word moves
2513 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2517 mips_address_insns (rtx x, machine_mode mode, bool might_split_p)
2519 struct mips_address_info addr;
2522 /* BLKmode is used for single unaligned loads and stores and should
2523 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2524 meaningless, so we have to single it out as a special case one way
2526 if (mode != BLKmode && might_split_p)
2527 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2531 if (mips_classify_address (&addr, x, mode, false))
2536 && !mips16_unextended_reference_p (mode, addr.reg,
2537 UINTVAL (addr.offset)))
2541 case ADDRESS_LO_SUM:
2542 return TARGET_MIPS16 ? factor * 2 : factor;
2544 case ADDRESS_CONST_INT:
2547 case ADDRESS_SYMBOLIC:
2548 return factor * mips_symbol_insns (addr.symbol_type, mode);
2553 /* Return true if X fits within an unsigned field of BITS bits that is
2554 shifted left SHIFT bits before being used. */
2557 mips_unsigned_immediate_p (unsigned HOST_WIDE_INT x, int bits, int shift = 0)
2559 return (x & ((1 << shift) - 1)) == 0 && x < ((unsigned) 1 << (shift + bits));
2562 /* Return true if X fits within a signed field of BITS bits that is
2563 shifted left SHIFT bits before being used. */
2566 mips_signed_immediate_p (unsigned HOST_WIDE_INT x, int bits, int shift = 0)
2568 x += 1 << (bits + shift - 1);
2569 return mips_unsigned_immediate_p (x, bits, shift);
2572 /* Return true if X is legitimate for accessing values of mode MODE,
2573 if it is based on a MIPS16 register, and if the offset satisfies
2574 OFFSET_PREDICATE. */
2577 m16_based_address_p (rtx x, machine_mode mode,
2578 insn_operand_predicate_fn offset_predicate)
2580 struct mips_address_info addr;
2582 return (mips_classify_address (&addr, x, mode, false)
2583 && addr.type == ADDRESS_REG
2584 && M16_REG_P (REGNO (addr.reg))
2585 && offset_predicate (addr.offset, mode));
2588 /* Return true if X is a legitimate address that conforms to the requirements
2589 for a microMIPS LWSP or SWSP insn. */
2592 lwsp_swsp_address_p (rtx x, machine_mode mode)
2594 struct mips_address_info addr;
2596 return (mips_classify_address (&addr, x, mode, false)
2597 && addr.type == ADDRESS_REG
2598 && REGNO (addr.reg) == STACK_POINTER_REGNUM
2599 && uw5_operand (addr.offset, mode));
2602 /* Return true if X is a legitimate address with a 12-bit offset.
2603 MODE is the mode of the value being accessed. */
2606 umips_12bit_offset_address_p (rtx x, machine_mode mode)
2608 struct mips_address_info addr;
2610 return (mips_classify_address (&addr, x, mode, false)
2611 && addr.type == ADDRESS_REG
2612 && CONST_INT_P (addr.offset)
2613 && UMIPS_12BIT_OFFSET_P (INTVAL (addr.offset)));
2616 /* Return true if X is a legitimate address with a 9-bit offset.
2617 MODE is the mode of the value being accessed. */
2620 mips_9bit_offset_address_p (rtx x, machine_mode mode)
2622 struct mips_address_info addr;
2624 return (mips_classify_address (&addr, x, mode, false)
2625 && addr.type == ADDRESS_REG
2626 && CONST_INT_P (addr.offset)
2627 && MIPS_9BIT_OFFSET_P (INTVAL (addr.offset)));
2630 /* Return the number of instructions needed to load constant X,
2631 assuming that BASE_INSN_LENGTH is the length of one instruction.
2632 Return 0 if X isn't a valid constant. */
2635 mips_const_insns (rtx x)
2637 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2638 enum mips_symbol_type symbol_type;
2641 switch (GET_CODE (x))
2644 if (!mips_symbolic_constant_p (XEXP (x, 0), SYMBOL_CONTEXT_LEA,
2646 || !mips_split_p[symbol_type])
2649 /* This is simply an LUI for normal mode. It is an extended
2650 LI followed by an extended SLL for MIPS16. */
2651 return TARGET_MIPS16 ? 4 : 1;
2655 /* Unsigned 8-bit constants can be loaded using an unextended
2656 LI instruction. Unsigned 16-bit constants can be loaded
2657 using an extended LI. Negative constants must be loaded
2658 using LI and then negated. */
2659 return (IN_RANGE (INTVAL (x), 0, 255) ? 1
2660 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
2661 : IN_RANGE (-INTVAL (x), 0, 255) ? 2
2662 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
2665 return mips_build_integer (codes, INTVAL (x));
2669 /* Allow zeros for normal mode, where we can use $0. */
2670 return !TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0;
2676 /* See if we can refer to X directly. */
2677 if (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_LEA, &symbol_type))
2678 return mips_symbol_insns (symbol_type, MAX_MACHINE_MODE);
2680 /* Otherwise try splitting the constant into a base and offset.
2681 If the offset is a 16-bit value, we can load the base address
2682 into a register and then use (D)ADDIU to add in the offset.
2683 If the offset is larger, we can load the base and offset
2684 into separate registers and add them together with (D)ADDU.
2685 However, the latter is only possible before reload; during
2686 and after reload, we must have the option of forcing the
2687 constant into the pool instead. */
2688 split_const (x, &x, &offset);
2691 int n = mips_const_insns (x);
2694 if (SMALL_INT (offset))
2696 else if (!targetm.cannot_force_const_mem (GET_MODE (x), x))
2697 return n + 1 + mips_build_integer (codes, INTVAL (offset));
2704 return mips_symbol_insns (mips_classify_symbol (x, SYMBOL_CONTEXT_LEA),
2712 /* X is a doubleword constant that can be handled by splitting it into
2713 two words and loading each word separately. Return the number of
2714 instructions required to do this, assuming that BASE_INSN_LENGTH
2715 is the length of one instruction. */
2718 mips_split_const_insns (rtx x)
2720 unsigned int low, high;
2722 low = mips_const_insns (mips_subword (x, false));
2723 high = mips_const_insns (mips_subword (x, true));
2724 gcc_assert (low > 0 && high > 0);
2728 /* Return the number of instructions needed to implement INSN,
2729 given that it loads from or stores to MEM. Assume that
2730 BASE_INSN_LENGTH is the length of one instruction. */
2733 mips_load_store_insns (rtx mem, rtx_insn *insn)
2739 gcc_assert (MEM_P (mem));
2740 mode = GET_MODE (mem);
2742 /* Try to prove that INSN does not need to be split. */
2743 might_split_p = GET_MODE_SIZE (mode) > UNITS_PER_WORD;
2746 set = single_set (insn);
2747 if (set && !mips_split_move_insn_p (SET_DEST (set), SET_SRC (set), insn))
2748 might_split_p = false;
2751 return mips_address_insns (XEXP (mem, 0), mode, might_split_p);
2754 /* Return the number of instructions needed for an integer division,
2755 assuming that BASE_INSN_LENGTH is the length of one instruction. */
2758 mips_idiv_insns (void)
2763 if (TARGET_CHECK_ZERO_DIV)
2765 if (GENERATE_DIVIDE_TRAPS)
2771 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
2776 /* Emit a move from SRC to DEST. Assume that the move expanders can
2777 handle all moves if !can_create_pseudo_p (). The distinction is
2778 important because, unlike emit_move_insn, the move expanders know
2779 how to force Pmode objects into the constant pool even when the
2780 constant pool address is not itself legitimate. */
2783 mips_emit_move (rtx dest, rtx src)
2785 return (can_create_pseudo_p ()
2786 ? emit_move_insn (dest, src)
2787 : emit_move_insn_1 (dest, src));
2790 /* Emit a move from SRC to DEST, splitting compound moves into individual
2791 instructions. SPLIT_TYPE is the type of split to perform. */
2794 mips_emit_move_or_split (rtx dest, rtx src, enum mips_split_type split_type)
2796 if (mips_split_move_p (dest, src, split_type))
2797 mips_split_move (dest, src, split_type);
2799 mips_emit_move (dest, src);
2802 /* Emit an instruction of the form (set TARGET (CODE OP0)). */
2805 mips_emit_unary (enum rtx_code code, rtx target, rtx op0)
2807 emit_insn (gen_rtx_SET (target, gen_rtx_fmt_e (code, GET_MODE (op0), op0)));
2810 /* Compute (CODE OP0) and store the result in a new register of mode MODE.
2811 Return that new register. */
2814 mips_force_unary (machine_mode mode, enum rtx_code code, rtx op0)
2818 reg = gen_reg_rtx (mode);
2819 mips_emit_unary (code, reg, op0);
2823 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2826 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
2828 emit_insn (gen_rtx_SET (target, gen_rtx_fmt_ee (code, GET_MODE (target),
2832 /* Compute (CODE OP0 OP1) and store the result in a new register
2833 of mode MODE. Return that new register. */
2836 mips_force_binary (machine_mode mode, enum rtx_code code, rtx op0, rtx op1)
2840 reg = gen_reg_rtx (mode);
2841 mips_emit_binary (code, reg, op0, op1);
2845 /* Copy VALUE to a register and return that register. If new pseudos
2846 are allowed, copy it into a new register, otherwise use DEST. */
2849 mips_force_temporary (rtx dest, rtx value)
2851 if (can_create_pseudo_p ())
2852 return force_reg (Pmode, value);
2855 mips_emit_move (dest, value);
2860 /* Emit a call sequence with call pattern PATTERN and return the call
2861 instruction itself (which is not necessarily the last instruction
2862 emitted). ORIG_ADDR is the original, unlegitimized address,
2863 ADDR is the legitimized form, and LAZY_P is true if the call
2864 address is lazily-bound. */
2867 mips_emit_call_insn (rtx pattern, rtx orig_addr, rtx addr, bool lazy_p)
2872 insn = emit_call_insn (pattern);
2874 if (TARGET_MIPS16 && mips_use_pic_fn_addr_reg_p (orig_addr))
2876 /* MIPS16 JALRs only take MIPS16 registers. If the target
2877 function requires $25 to be valid on entry, we must copy it
2878 there separately. The move instruction can be put in the
2879 call's delay slot. */
2880 reg = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
2881 emit_insn_before (gen_move_insn (reg, addr), insn);
2882 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
2886 /* Lazy-binding stubs require $gp to be valid on entry. */
2887 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
2891 /* See the comment above load_call<mode> for details. */
2892 use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
2893 gen_rtx_REG (Pmode, GOT_VERSION_REGNUM));
2894 emit_insn (gen_update_got_version ());
2898 && TARGET_EXPLICIT_RELOCS
2899 && TARGET_CALL_CLOBBERED_GP)
2901 rtx post_call_tmp_reg = gen_rtx_REG (word_mode, POST_CALL_TMP_REG);
2902 clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), post_call_tmp_reg);
2908 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2909 then add CONST_INT OFFSET to the result. */
2912 mips_unspec_address_offset (rtx base, rtx offset,
2913 enum mips_symbol_type symbol_type)
2915 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
2916 UNSPEC_ADDRESS_FIRST + symbol_type);
2917 if (offset != const0_rtx)
2918 base = gen_rtx_PLUS (Pmode, base, offset);
2919 return gen_rtx_CONST (Pmode, base);
2922 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2923 type SYMBOL_TYPE. */
2926 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
2930 split_const (address, &base, &offset);
2931 return mips_unspec_address_offset (base, offset, symbol_type);
2934 /* If OP is an UNSPEC address, return the address to which it refers,
2935 otherwise return OP itself. */
2938 mips_strip_unspec_address (rtx op)
2942 split_const (op, &base, &offset);
2943 if (UNSPEC_ADDRESS_P (base))
2944 op = plus_constant (Pmode, UNSPEC_ADDRESS (base), INTVAL (offset));
2948 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2949 high part to BASE and return the result. Just return BASE otherwise.
2950 TEMP is as for mips_force_temporary.
2952 The returned expression can be used as the first operand to a LO_SUM. */
2955 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
2956 enum mips_symbol_type symbol_type)
2958 if (mips_split_p[symbol_type])
2960 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
2961 addr = mips_force_temporary (temp, addr);
2962 base = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
2967 /* Return an instruction that copies $gp into register REG. We want
2968 GCC to treat the register's value as constant, so that its value
2969 can be rematerialized on demand. */
2972 gen_load_const_gp (rtx reg)
2974 return PMODE_INSN (gen_load_const_gp, (reg));
2977 /* Return a pseudo register that contains the value of $gp throughout
2978 the current function. Such registers are needed by MIPS16 functions,
2979 for which $gp itself is not a valid base register or addition operand. */
2982 mips16_gp_pseudo_reg (void)
2984 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
2988 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
2990 push_topmost_sequence ();
2992 scan = get_insns ();
2993 while (NEXT_INSN (scan) && !INSN_P (NEXT_INSN (scan)))
2994 scan = NEXT_INSN (scan);
2996 rtx set = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
2997 rtx_insn *insn = emit_insn_after (set, scan);
2998 INSN_LOCATION (insn) = 0;
3000 pop_topmost_sequence ();
3003 return cfun->machine->mips16_gp_pseudo_rtx;
3006 /* Return a base register that holds pic_offset_table_rtx.
3007 TEMP, if nonnull, is a scratch Pmode base register. */
3010 mips_pic_base_register (rtx temp)
3013 return pic_offset_table_rtx;
3015 if (currently_expanding_to_rtl)
3016 return mips16_gp_pseudo_reg ();
3018 if (can_create_pseudo_p ())
3019 temp = gen_reg_rtx (Pmode);
3022 /* The first post-reload split exposes all references to $gp
3023 (both uses and definitions). All references must remain
3024 explicit after that point.
3026 It is safe to introduce uses of $gp at any time, so for
3027 simplicity, we do that before the split too. */
3028 mips_emit_move (temp, pic_offset_table_rtx);
3030 emit_insn (gen_load_const_gp (temp));
3034 /* Return the RHS of a load_call<mode> insn. */
3037 mips_unspec_call (rtx reg, rtx symbol)
3041 vec = gen_rtvec (3, reg, symbol, gen_rtx_REG (SImode, GOT_VERSION_REGNUM));
3042 return gen_rtx_UNSPEC (Pmode, vec, UNSPEC_LOAD_CALL);
3045 /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol
3046 reference. Return NULL_RTX otherwise. */
3049 mips_strip_unspec_call (rtx src)
3051 if (GET_CODE (src) == UNSPEC && XINT (src, 1) == UNSPEC_LOAD_CALL)
3052 return mips_strip_unspec_address (XVECEXP (src, 0, 1));
3056 /* Create and return a GOT reference of type TYPE for address ADDR.
3057 TEMP, if nonnull, is a scratch Pmode base register. */
3060 mips_got_load (rtx temp, rtx addr, enum mips_symbol_type type)
3062 rtx base, high, lo_sum_symbol;
3064 base = mips_pic_base_register (temp);
3066 /* If we used the temporary register to load $gp, we can't use
3067 it for the high part as well. */
3068 if (temp != NULL && reg_overlap_mentioned_p (base, temp))
3071 high = mips_unspec_offset_high (temp, base, addr, type);
3072 lo_sum_symbol = mips_unspec_address (addr, type);
3074 if (type == SYMBOL_GOTOFF_CALL)
3075 return mips_unspec_call (high, lo_sum_symbol);
3077 return PMODE_INSN (gen_unspec_got, (high, lo_sum_symbol));
3080 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
3081 it appears in a MEM of that mode. Return true if ADDR is a legitimate
3082 constant in that context and can be split into high and low parts.
3083 If so, and if LOW_OUT is nonnull, emit the high part and store the
3084 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
3086 TEMP is as for mips_force_temporary and is used to load the high
3087 part into a register.
3089 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
3090 a legitimize SET_SRC for an .md pattern, otherwise the low part
3091 is guaranteed to be a legitimate address for mode MODE. */
3094 mips_split_symbol (rtx temp, rtx addr, machine_mode mode, rtx *low_out)
3096 enum mips_symbol_context context;
3097 enum mips_symbol_type symbol_type;
3100 context = (mode == MAX_MACHINE_MODE
3101 ? SYMBOL_CONTEXT_LEA
3102 : SYMBOL_CONTEXT_MEM);
3103 if (GET_CODE (addr) == HIGH && context == SYMBOL_CONTEXT_LEA)
3105 addr = XEXP (addr, 0);
3106 if (mips_symbolic_constant_p (addr, context, &symbol_type)
3107 && mips_symbol_insns (symbol_type, mode) > 0
3108 && mips_split_hi_p[symbol_type])
3111 switch (symbol_type)
3113 case SYMBOL_GOT_PAGE_OFST:
3114 /* The high part of a page/ofst pair is loaded from the GOT. */
3115 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_PAGE);
3126 if (mips_symbolic_constant_p (addr, context, &symbol_type)
3127 && mips_symbol_insns (symbol_type, mode) > 0
3128 && mips_split_p[symbol_type])
3131 switch (symbol_type)
3133 case SYMBOL_GOT_DISP:
3134 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
3135 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_DISP);
3138 case SYMBOL_GP_RELATIVE:
3139 high = mips_pic_base_register (temp);
3140 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
3144 high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
3145 high = mips_force_temporary (temp, high);
3146 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
3155 /* Return a legitimate address for REG + OFFSET. TEMP is as for
3156 mips_force_temporary; it is only needed when OFFSET is not a
3160 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
3162 if (!SMALL_OPERAND (offset))
3168 /* Load the full offset into a register so that we can use
3169 an unextended instruction for the address itself. */
3170 high = GEN_INT (offset);
3175 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
3176 The addition inside the macro CONST_HIGH_PART may cause an
3177 overflow, so we need to force a sign-extension check. */
3178 high = gen_int_mode (CONST_HIGH_PART (offset), Pmode);
3179 offset = CONST_LOW_PART (offset);
3181 high = mips_force_temporary (temp, high);
3182 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
3184 return plus_constant (Pmode, reg, offset);
3187 /* The __tls_get_attr symbol. */
3188 static GTY(()) rtx mips_tls_symbol;
3190 /* Return an instruction sequence that calls __tls_get_addr. SYM is
3191 the TLS symbol we are referencing and TYPE is the symbol type to use
3192 (either global dynamic or local dynamic). V0 is an RTX for the
3193 return value location. */
3196 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
3200 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
3202 if (!mips_tls_symbol)
3203 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
3205 loc = mips_unspec_address (sym, type);
3209 emit_insn (gen_rtx_SET (a0, gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx,
3211 insn = mips_expand_call (MIPS_CALL_NORMAL, v0, mips_tls_symbol,
3212 const0_rtx, NULL_RTX, false);
3213 RTL_CONST_CALL_P (insn) = 1;
3214 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
3215 insn = get_insns ();
3222 /* Return a pseudo register that contains the current thread pointer. */
3225 mips_expand_thread_pointer (rtx tp)
3231 if (!mips16_rdhwr_stub)
3232 mips16_rdhwr_stub = new mips16_rdhwr_one_only_stub ();
3233 fn = mips16_stub_call_address (mips16_rdhwr_stub);
3234 emit_insn (PMODE_INSN (gen_tls_get_tp_mips16, (tp, fn)));
3237 emit_insn (PMODE_INSN (gen_tls_get_tp, (tp)));
3244 return mips_expand_thread_pointer (gen_reg_rtx (Pmode));
3247 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
3248 its address. The return value will be both a valid address and a valid
3249 SET_SRC (either a REG or a LO_SUM). */
3252 mips_legitimize_tls_address (rtx loc)
3254 rtx dest, insn, v0, tp, tmp1, tmp2, eqv, offset;
3255 enum tls_model model;
3257 model = SYMBOL_REF_TLS_MODEL (loc);
3258 /* Only TARGET_ABICALLS code can have more than one module; other
3259 code must be static and should not use a GOT. All TLS models
3260 reduce to local exec in this situation. */
3261 if (!TARGET_ABICALLS)
3262 model = TLS_MODEL_LOCAL_EXEC;
3266 case TLS_MODEL_GLOBAL_DYNAMIC:
3267 v0 = gen_rtx_REG (Pmode, GP_RETURN);
3268 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
3269 dest = gen_reg_rtx (Pmode);
3270 emit_libcall_block (insn, dest, v0, loc);
3273 case TLS_MODEL_LOCAL_DYNAMIC:
3274 v0 = gen_rtx_REG (Pmode, GP_RETURN);
3275 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
3276 tmp1 = gen_reg_rtx (Pmode);
3278 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
3279 share the LDM result with other LD model accesses. */
3280 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3282 emit_libcall_block (insn, tmp1, v0, eqv);
3284 offset = mips_unspec_address (loc, SYMBOL_DTPREL);
3285 if (mips_split_p[SYMBOL_DTPREL])
3287 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
3288 dest = gen_rtx_LO_SUM (Pmode, tmp2, offset);
3291 dest = expand_binop (Pmode, add_optab, tmp1, offset,
3292 0, 0, OPTAB_DIRECT);
3295 case TLS_MODEL_INITIAL_EXEC:
3296 tp = mips_get_tp ();
3297 tmp1 = gen_reg_rtx (Pmode);
3298 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
3299 if (Pmode == DImode)
3300 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
3302 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
3303 dest = gen_reg_rtx (Pmode);
3304 emit_insn (gen_add3_insn (dest, tmp1, tp));
3307 case TLS_MODEL_LOCAL_EXEC:
3308 tmp1 = mips_get_tp ();
3309 offset = mips_unspec_address (loc, SYMBOL_TPREL);
3310 if (mips_split_p[SYMBOL_TPREL])
3312 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_TPREL);
3313 dest = gen_rtx_LO_SUM (Pmode, tmp2, offset);
3316 dest = expand_binop (Pmode, add_optab, tmp1, offset,
3317 0, 0, OPTAB_DIRECT);
3326 /* Implement "TARGET = __builtin_mips_get_fcsr ()" for MIPS16,
3330 mips16_expand_get_fcsr (rtx target)
3332 if (!mips16_get_fcsr_stub)
3333 mips16_get_fcsr_stub = new mips16_get_fcsr_one_only_stub ();
3334 rtx fn = mips16_stub_call_address (mips16_get_fcsr_stub);
3335 emit_insn (PMODE_INSN (gen_mips_get_fcsr_mips16, (fn)));
3336 emit_move_insn (target, gen_rtx_REG (SImode, GET_FCSR_REGNUM));
3339 /* Implement __builtin_mips_set_fcsr (TARGET) for MIPS16, using a stub. */
3342 mips16_expand_set_fcsr (rtx newval)
3344 if (!mips16_set_fcsr_stub)
3345 mips16_set_fcsr_stub = new mips16_set_fcsr_one_only_stub ();
3346 rtx fn = mips16_stub_call_address (mips16_set_fcsr_stub);
3347 emit_move_insn (gen_rtx_REG (SImode, SET_FCSR_REGNUM), newval);
3348 emit_insn (PMODE_INSN (gen_mips_set_fcsr_mips16, (fn)));
3351 /* If X is not a valid address for mode MODE, force it into a register. */
3354 mips_force_address (rtx x, machine_mode mode)
3356 if (!mips_legitimate_address_p (mode, x, false))
3357 x = force_reg (Pmode, x);
3361 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
3362 be legitimized in a way that the generic machinery might not expect,
3363 return a new address, otherwise return NULL. MODE is the mode of
3364 the memory being accessed. */
3367 mips_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3371 HOST_WIDE_INT offset;
3373 if (mips_tls_symbol_p (x))
3374 return mips_legitimize_tls_address (x);
3376 /* See if the address can split into a high part and a LO_SUM. */
3377 if (mips_split_symbol (NULL, x, mode, &addr))
3378 return mips_force_address (addr, mode);
3380 /* Handle BASE + OFFSET using mips_add_offset. */
3381 mips_split_plus (x, &base, &offset);
3384 if (!mips_valid_base_register_p (base, mode, false))
3385 base = copy_to_mode_reg (Pmode, base);
3386 addr = mips_add_offset (NULL, base, offset);
3387 return mips_force_address (addr, mode);
3393 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
3396 mips_move_integer (rtx temp, rtx dest, unsigned HOST_WIDE_INT value)
3398 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
3400 unsigned int i, num_ops;
3403 mode = GET_MODE (dest);
3404 num_ops = mips_build_integer (codes, value);
3406 /* Apply each binary operation to X. Invariant: X is a legitimate
3407 source operand for a SET pattern. */
3408 x = GEN_INT (codes[0].value);
3409 for (i = 1; i < num_ops; i++)
3411 if (!can_create_pseudo_p ())
3413 emit_insn (gen_rtx_SET (temp, x));
3417 x = force_reg (mode, x);
3418 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
3421 emit_insn (gen_rtx_SET (dest, x));
3424 /* Subroutine of mips_legitimize_move. Move constant SRC into register
3425 DEST given that SRC satisfies immediate_operand but doesn't satisfy
3429 mips_legitimize_const_move (machine_mode mode, rtx dest, rtx src)
3433 /* Split moves of big integers into smaller pieces. */
3434 if (splittable_const_int_operand (src, mode))
3436 mips_move_integer (dest, dest, INTVAL (src));
3440 /* Split moves of symbolic constants into high/low pairs. */
3441 if (mips_split_symbol (dest, src, MAX_MACHINE_MODE, &src))
3443 emit_insn (gen_rtx_SET (dest, src));
3447 /* Generate the appropriate access sequences for TLS symbols. */
3448 if (mips_tls_symbol_p (src))
3450 mips_emit_move (dest, mips_legitimize_tls_address (src));
3454 /* If we have (const (plus symbol offset)), and that expression cannot
3455 be forced into memory, load the symbol first and add in the offset.
3456 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
3457 forced into memory, as it usually produces better code. */
3458 split_const (src, &base, &offset);
3459 if (offset != const0_rtx
3460 && (targetm.cannot_force_const_mem (mode, src)
3461 || (!TARGET_MIPS16 && can_create_pseudo_p ())))
3463 base = mips_force_temporary (dest, base);
3464 mips_emit_move (dest, mips_add_offset (NULL, base, INTVAL (offset)));
3468 src = force_const_mem (mode, src);
3470 /* When using explicit relocs, constant pool references are sometimes
3471 not legitimate addresses. */
3472 mips_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0));
3473 mips_emit_move (dest, src);
3476 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
3477 sequence that is valid. */
3480 mips_legitimize_move (machine_mode mode, rtx dest, rtx src)
3482 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
3484 mips_emit_move (dest, force_reg (mode, src));
3488 /* We need to deal with constants that would be legitimate
3489 immediate_operands but aren't legitimate move_operands. */
3490 if (CONSTANT_P (src) && !move_operand (src, mode))
3492 mips_legitimize_const_move (mode, dest, src);
3493 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
3499 /* Return true if value X in context CONTEXT is a small-data address
3500 that can be rewritten as a LO_SUM. */
3503 mips_rewrite_small_data_p (rtx x, enum mips_symbol_context context)
3505 enum mips_symbol_type symbol_type;
3507 return (mips_lo_relocs[SYMBOL_GP_RELATIVE]
3508 && !mips_split_p[SYMBOL_GP_RELATIVE]
3509 && mips_symbolic_constant_p (x, context, &symbol_type)
3510 && symbol_type == SYMBOL_GP_RELATIVE);
3513 /* Return true if OP refers to small data symbols directly, not through
3514 a LO_SUM. CONTEXT is the context in which X appears. */
3517 mips_small_data_pattern_1 (rtx x, enum mips_symbol_context context)
3519 subrtx_var_iterator::array_type array;
3520 FOR_EACH_SUBRTX_VAR (iter, array, x, ALL)
3524 /* Ignore things like "g" constraints in asms. We make no particular
3525 guarantee about which symbolic constants are acceptable as asm operands
3526 versus which must be forced into a GPR. */
3527 if (GET_CODE (x) == LO_SUM || GET_CODE (x) == ASM_OPERANDS)
3528 iter.skip_subrtxes ();
3531 if (mips_small_data_pattern_1 (XEXP (x, 0), SYMBOL_CONTEXT_MEM))
3533 iter.skip_subrtxes ();
3535 else if (mips_rewrite_small_data_p (x, context))
3541 /* Return true if OP refers to small data symbols directly, not through
3545 mips_small_data_pattern_p (rtx op)
3547 return mips_small_data_pattern_1 (op, SYMBOL_CONTEXT_LEA);
3550 /* Rewrite *LOC so that it refers to small data using explicit
3551 relocations. CONTEXT is the context in which *LOC appears. */
3554 mips_rewrite_small_data_1 (rtx *loc, enum mips_symbol_context context)
3556 subrtx_ptr_iterator::array_type array;
3557 FOR_EACH_SUBRTX_PTR (iter, array, loc, ALL)
3562 mips_rewrite_small_data_1 (&XEXP (*loc, 0), SYMBOL_CONTEXT_MEM);
3563 iter.skip_subrtxes ();
3565 else if (mips_rewrite_small_data_p (*loc, context))
3567 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
3568 iter.skip_subrtxes ();
3570 else if (GET_CODE (*loc) == LO_SUM)
3571 iter.skip_subrtxes ();
3575 /* Rewrite instruction pattern PATTERN so that it refers to small data
3576 using explicit relocations. */
3579 mips_rewrite_small_data (rtx pattern)
3581 pattern = copy_insn (pattern);
3582 mips_rewrite_small_data_1 (&pattern, SYMBOL_CONTEXT_LEA);
3586 /* The cost of loading values from the constant pool. It should be
3587 larger than the cost of any constant we want to synthesize inline. */
3588 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3590 /* Return the cost of X when used as an operand to the MIPS16 instruction
3591 that implements CODE. Return -1 if there is no such instruction, or if
3592 X is not a valid immediate operand for it. */
3595 mips16_constant_cost (int code, HOST_WIDE_INT x)
3602 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3603 other shifts are extended. The shift patterns truncate the shift
3604 count to the right size, so there are no out-of-range values. */
3605 if (IN_RANGE (x, 1, 8))
3607 return COSTS_N_INSNS (1);
3610 if (IN_RANGE (x, -128, 127))
3612 if (SMALL_OPERAND (x))
3613 return COSTS_N_INSNS (1);
3617 /* Like LE, but reject the always-true case. */
3621 /* We add 1 to the immediate and use SLT. */
3624 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3627 if (IN_RANGE (x, 0, 255))
3629 if (SMALL_OPERAND_UNSIGNED (x))
3630 return COSTS_N_INSNS (1);
3635 /* Equality comparisons with 0 are cheap. */
3645 /* Return true if there is a non-MIPS16 instruction that implements CODE
3646 and if that instruction accepts X as an immediate operand. */
3649 mips_immediate_operand_p (int code, HOST_WIDE_INT x)
3656 /* All shift counts are truncated to a valid constant. */
3661 /* Likewise rotates, if the target supports rotates at all. */
3667 /* These instructions take 16-bit unsigned immediates. */
3668 return SMALL_OPERAND_UNSIGNED (x);
3673 /* These instructions take 16-bit signed immediates. */
3674 return SMALL_OPERAND (x);
3680 /* The "immediate" forms of these instructions are really
3681 implemented as comparisons with register 0. */
3686 /* Likewise, meaning that the only valid immediate operand is 1. */
3690 /* We add 1 to the immediate and use SLT. */
3691 return SMALL_OPERAND (x + 1);
3694 /* Likewise SLTU, but reject the always-true case. */
3695 return SMALL_OPERAND (x + 1) && x + 1 != 0;
3699 /* The bit position and size are immediate operands. */
3700 return ISA_HAS_EXT_INS;
3703 /* By default assume that $0 can be used for 0. */
3708 /* Return the cost of binary operation X, given that the instruction
3709 sequence for a word-sized or smaller operation has cost SINGLE_COST
3710 and that the sequence of a double-word operation has cost DOUBLE_COST.
3711 If SPEED is true, optimize for speed otherwise optimize for size. */
3714 mips_binary_cost (rtx x, int single_cost, int double_cost, bool speed)
3718 if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2)
3723 + set_src_cost (XEXP (x, 0), GET_MODE (x), speed)
3724 + rtx_cost (XEXP (x, 1), GET_MODE (x), GET_CODE (x), 1, speed));
3727 /* Return the cost of floating-point multiplications of mode MODE. */
3730 mips_fp_mult_cost (machine_mode mode)
3732 return mode == DFmode ? mips_cost->fp_mult_df : mips_cost->fp_mult_sf;
3735 /* Return the cost of floating-point divisions of mode MODE. */
3738 mips_fp_div_cost (machine_mode mode)
3740 return mode == DFmode ? mips_cost->fp_div_df : mips_cost->fp_div_sf;
3743 /* Return the cost of sign-extending OP to mode MODE, not including the
3744 cost of OP itself. */
3747 mips_sign_extend_cost (machine_mode mode, rtx op)
3750 /* Extended loads are as cheap as unextended ones. */
3753 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3754 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3757 if (ISA_HAS_SEB_SEH || GENERATE_MIPS16E)
3758 /* We can use SEB or SEH. */
3759 return COSTS_N_INSNS (1);
3761 /* We need to use a shift left and a shift right. */
3762 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3765 /* Return the cost of zero-extending OP to mode MODE, not including the
3766 cost of OP itself. */
3769 mips_zero_extend_cost (machine_mode mode, rtx op)
3772 /* Extended loads are as cheap as unextended ones. */
3775 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3776 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3777 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3779 if (GENERATE_MIPS16E)
3780 /* We can use ZEB or ZEH. */
3781 return COSTS_N_INSNS (1);
3784 /* We need to load 0xff or 0xffff into a register and use AND. */
3785 return COSTS_N_INSNS (GET_MODE (op) == QImode ? 2 : 3);
3787 /* We can use ANDI. */
3788 return COSTS_N_INSNS (1);
3791 /* Return the cost of moving between two registers of mode MODE,
3792 assuming that the move will be in pieces of at most UNITS bytes. */
3795 mips_set_reg_reg_piece_cost (machine_mode mode, unsigned int units)
3797 return COSTS_N_INSNS ((GET_MODE_SIZE (mode) + units - 1) / units);
3800 /* Return the cost of moving between two registers of mode MODE. */
3803 mips_set_reg_reg_cost (machine_mode mode)
3805 switch (GET_MODE_CLASS (mode))
3808 return mips_set_reg_reg_piece_cost (mode, GET_MODE_SIZE (CCmode));
3811 case MODE_COMPLEX_FLOAT:
3812 case MODE_VECTOR_FLOAT:
3813 if (TARGET_HARD_FLOAT)
3814 return mips_set_reg_reg_piece_cost (mode, UNITS_PER_HWFPVALUE);
3818 return mips_set_reg_reg_piece_cost (mode, UNITS_PER_WORD);
3822 /* Implement TARGET_RTX_COSTS. */
3825 mips_rtx_costs (rtx x, machine_mode mode, int outer_code,
3826 int opno ATTRIBUTE_UNUSED, int *total, bool speed)
3828 int code = GET_CODE (x);
3829 bool float_mode_p = FLOAT_MODE_P (mode);
3833 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3834 appear in the instruction stream, and the cost of a comparison is
3835 really the cost of the branch or scc condition. At the time of
3836 writing, GCC only uses an explicit outer COMPARE code when optabs
3837 is testing whether a constant is expensive enough to force into a
3838 register. We want optabs to pass such constants through the MIPS
3839 expanders instead, so make all constants very cheap here. */
3840 if (outer_code == COMPARE)
3842 gcc_assert (CONSTANT_P (x));
3850 /* Treat *clear_upper32-style ANDs as having zero cost in the
3851 second operand. The cost is entirely in the first operand.
3853 ??? This is needed because we would otherwise try to CSE
3854 the constant operand. Although that's the right thing for
3855 instructions that continue to be a register operation throughout
3856 compilation, it is disastrous for instructions that could
3857 later be converted into a memory operation. */
3859 && outer_code == AND
3860 && UINTVAL (x) == 0xffffffff)
3868 cost = mips16_constant_cost (outer_code, INTVAL (x));
3877 /* When not optimizing for size, we care more about the cost
3878 of hot code, and hot code is often in a loop. If a constant
3879 operand needs to be forced into a register, we will often be
3880 able to hoist the constant load out of the loop, so the load
3881 should not contribute to the cost. */
3882 if (speed || mips_immediate_operand_p (outer_code, INTVAL (x)))
3894 if (force_to_mem_operand (x, VOIDmode))
3896 *total = COSTS_N_INSNS (1);
3899 cost = mips_const_insns (x);
3902 /* If the constant is likely to be stored in a GPR, SETs of
3903 single-insn constants are as cheap as register sets; we
3904 never want to CSE them.
3906 Don't reduce the cost of storing a floating-point zero in
3907 FPRs. If we have a zero in an FPR for other reasons, we
3908 can get better cfg-cleanup and delayed-branch results by
3909 using it consistently, rather than using $0 sometimes and
3910 an FPR at other times. Also, moves between floating-point
3911 registers are sometimes cheaper than (D)MTC1 $0. */
3913 && outer_code == SET
3914 && !(float_mode_p && TARGET_HARD_FLOAT))
3916 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3917 want to CSE the constant itself. It is usually better to
3918 have N copies of the last operation in the sequence and one
3919 shared copy of the other operations. (Note that this is
3920 not true for MIPS16 code, where the final operation in the
3921 sequence is often an extended instruction.)
3923 Also, if we have a CONST_INT, we don't know whether it is
3924 for a word or doubleword operation, so we cannot rely on
3925 the result of mips_build_integer. */
3926 else if (!TARGET_MIPS16
3927 && (outer_code == SET || GET_MODE (x) == VOIDmode))
3929 *total = COSTS_N_INSNS (cost);
3932 /* The value will need to be fetched from the constant pool. */
3933 *total = CONSTANT_POOL_COST;
3937 /* If the address is legitimate, return the number of
3938 instructions it needs. */
3940 cost = mips_address_insns (addr, mode, true);
3943 *total = COSTS_N_INSNS (cost + 1);
3946 /* Check for a scaled indexed address. */
3947 if (mips_lwxs_address_p (addr)
3948 || mips_lx_address_p (addr, mode))
3950 *total = COSTS_N_INSNS (2);
3953 /* Otherwise use the default handling. */
3957 *total = COSTS_N_INSNS (6);
3961 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1);
3965 /* Check for a *clear_upper32 pattern and treat it like a zero
3966 extension. See the pattern's comment for details. */
3969 && CONST_INT_P (XEXP (x, 1))
3970 && UINTVAL (XEXP (x, 1)) == 0xffffffff)
3972 *total = (mips_zero_extend_cost (mode, XEXP (x, 0))
3973 + set_src_cost (XEXP (x, 0), mode, speed));
3976 if (ISA_HAS_CINS && CONST_INT_P (XEXP (x, 1)))
3978 rtx op = XEXP (x, 0);
3979 if (GET_CODE (op) == ASHIFT
3980 && CONST_INT_P (XEXP (op, 1))
3981 && mask_low_and_shift_p (mode, XEXP (x, 1), XEXP (op, 1), 32))
3983 *total = COSTS_N_INSNS (1);
3984 *total += set_src_cost (XEXP (op, 0), mode, speed);
3988 /* (AND (NOT op0) (NOT op1) is a nor operation that can be done in
3989 a single instruction. */
3991 && GET_CODE (XEXP (x, 0)) == NOT
3992 && GET_CODE (XEXP (x, 1)) == NOT)
3994 cost = GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1;
3995 *total = (COSTS_N_INSNS (cost)
3996 + set_src_cost (XEXP (XEXP (x, 0), 0), mode, speed)
3997 + set_src_cost (XEXP (XEXP (x, 1), 0), mode, speed));
4005 /* Double-word operations use two single-word operations. */
4006 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (2),
4015 if (CONSTANT_P (XEXP (x, 1)))
4016 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
4019 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (12),
4025 *total = mips_cost->fp_add;
4027 *total = COSTS_N_INSNS (4);
4031 /* Low-part immediates need an extended MIPS16 instruction. */
4032 *total = (COSTS_N_INSNS (TARGET_MIPS16 ? 2 : 1)
4033 + set_src_cost (XEXP (x, 0), mode, speed));
4048 /* Branch comparisons have VOIDmode, so use the first operand's
4050 mode = GET_MODE (XEXP (x, 0));
4051 if (FLOAT_MODE_P (mode))
4053 *total = mips_cost->fp_add;
4056 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
4061 if (float_mode_p && ISA_HAS_UNFUSED_MADD4 && !HONOR_SIGNED_ZEROS (mode))
4063 /* See if we can use NMADD or NMSUB via the *nmadd4<mode>_fastmath
4064 or *nmsub4<mode>_fastmath patterns. These patterns check for
4065 HONOR_SIGNED_ZEROS so we check here too. */
4066 rtx op0 = XEXP (x, 0);
4067 rtx op1 = XEXP (x, 1);
4068 if (GET_CODE (op0) == MULT && GET_CODE (XEXP (op0, 0)) == NEG)
4070 *total = (mips_fp_mult_cost (mode)
4071 + set_src_cost (XEXP (XEXP (op0, 0), 0), mode, speed)
4072 + set_src_cost (XEXP (op0, 1), mode, speed)
4073 + set_src_cost (op1, mode, speed));
4076 if (GET_CODE (op1) == MULT)
4078 *total = (mips_fp_mult_cost (mode)
4079 + set_src_cost (op0, mode, speed)
4080 + set_src_cost (XEXP (op1, 0), mode, speed)
4081 + set_src_cost (XEXP (op1, 1), mode, speed));
4090 /* If this is part of a MADD or MSUB, treat the PLUS as
4092 if (ISA_HAS_UNFUSED_MADD4 && GET_CODE (XEXP (x, 0)) == MULT)
4095 *total = mips_cost->fp_add;
4099 /* If it's an add + mult (which is equivalent to shift left) and
4100 it's immediate operand satisfies const_immlsa_operand predicate. */
4101 if (((ISA_HAS_LSA && mode == SImode)
4102 || (ISA_HAS_DLSA && mode == DImode))
4103 && GET_CODE (XEXP (x, 0)) == MULT)
4105 rtx op2 = XEXP (XEXP (x, 0), 1);
4106 if (const_immlsa_operand (op2, mode))
4108 *total = (COSTS_N_INSNS (1)
4109 + set_src_cost (XEXP (XEXP (x, 0), 0), mode, speed)
4110 + set_src_cost (XEXP (x, 1), mode, speed));
4115 /* Double-word operations require three single-word operations and
4116 an SLTU. The MIPS16 version then needs to move the result of
4117 the SLTU from $24 to a MIPS16 register. */
4118 *total = mips_binary_cost (x, COSTS_N_INSNS (1),
4119 COSTS_N_INSNS (TARGET_MIPS16 ? 5 : 4),
4124 if (float_mode_p && ISA_HAS_UNFUSED_MADD4)
4126 /* See if we can use NMADD or NMSUB via the *nmadd4<mode> or
4127 *nmsub4<mode> patterns. */
4128 rtx op = XEXP (x, 0);
4129 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
4130 && GET_CODE (XEXP (op, 0)) == MULT)
4132 *total = (mips_fp_mult_cost (mode)
4133 + set_src_cost (XEXP (XEXP (op, 0), 0), mode, speed)
4134 + set_src_cost (XEXP (XEXP (op, 0), 1), mode, speed)
4135 + set_src_cost (XEXP (op, 1), mode, speed));
4141 *total = mips_cost->fp_add;
4143 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1);
4147 *total = mips_fp_mult_cost (mode);
4152 *total = mips_fp_mult_cost (mode);
4153 else if (mode == DImode && !TARGET_64BIT)
4154 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
4155 where the mulsidi3 always includes an MFHI and an MFLO. */
4157 ? mips_cost->int_mult_si * 3 + 6
4158 : COSTS_N_INSNS (ISA_HAS_MUL3 ? 7 : 9));
4160 *total = COSTS_N_INSNS ((ISA_HAS_MUL3 || ISA_HAS_R6MUL) ? 1 : 2) + 1;
4161 else if (mode == DImode)
4162 *total = mips_cost->int_mult_di;
4164 *total = mips_cost->int_mult_si;
4168 /* Check for a reciprocal. */
4170 && ISA_HAS_FP_RECIP_RSQRT (mode)
4171 && flag_unsafe_math_optimizations
4172 && XEXP (x, 0) == CONST1_RTX (mode))
4174 if (outer_code == SQRT || GET_CODE (XEXP (x, 1)) == SQRT)
4175 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
4176 division as being free. */
4177 *total = set_src_cost (XEXP (x, 1), mode, speed);
4179 *total = (mips_fp_div_cost (mode)
4180 + set_src_cost (XEXP (x, 1), mode, speed));
4189 *total = mips_fp_div_cost (mode);
4198 /* It is our responsibility to make division by a power of 2
4199 as cheap as 2 register additions if we want the division
4200 expanders to be used for such operations; see the setting
4201 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
4202 should always produce shorter code than using
4203 expand_sdiv2_pow2. */
4205 && CONST_INT_P (XEXP (x, 1))
4206 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
4208 *total = COSTS_N_INSNS (2);
4209 *total += set_src_cost (XEXP (x, 0), mode, speed);
4212 *total = COSTS_N_INSNS (mips_idiv_insns ());
4214 else if (mode == DImode)
4215 *total = mips_cost->int_div_di;
4217 *total = mips_cost->int_div_si;
4221 *total = mips_sign_extend_cost (mode, XEXP (x, 0));
4225 if (outer_code == SET
4227 && (GET_CODE (XEXP (x, 0)) == TRUNCATE
4228 || GET_CODE (XEXP (x, 0)) == SUBREG)
4229 && GET_MODE (XEXP (x, 0)) == QImode
4230 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
4232 *total = set_src_cost (XEXP (XEXP (x, 0), 0), VOIDmode, speed);
4235 *total = mips_zero_extend_cost (mode, XEXP (x, 0));
4238 /* Costings for highpart multiplies. Matching patterns of the form:
4240 (lshiftrt:DI (mult:DI (sign_extend:DI (...)
4241 (sign_extend:DI (...))
4245 && (GET_CODE (XEXP (x, 0)) == ASHIFTRT
4246 || GET_CODE (XEXP (x, 0)) == LSHIFTRT)
4247 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4248 && ((INTVAL (XEXP (XEXP (x, 0), 1)) == 32
4249 && GET_MODE (XEXP (x, 0)) == DImode)
4251 && INTVAL (XEXP (XEXP (x, 0), 1)) == 64
4252 && GET_MODE (XEXP (x, 0)) == TImode))
4253 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
4254 && ((GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND
4255 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == SIGN_EXTEND)
4256 || (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
4257 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1))
4261 *total = COSTS_N_INSNS (1) + 1;
4262 else if (mode == DImode)
4263 *total = mips_cost->int_mult_di;
4265 *total = mips_cost->int_mult_si;
4267 /* Sign extension is free, zero extension costs for DImode when
4268 on a 64bit core / when DMUL is present. */
4269 for (int i = 0; i < 2; ++i)
4271 rtx op = XEXP (XEXP (XEXP (x, 0), 0), i);
4273 && GET_CODE (op) == ZERO_EXTEND
4274 && GET_MODE (op) == DImode)
4275 *total += rtx_cost (op, DImode, MULT, i, speed);
4277 *total += rtx_cost (XEXP (op, 0), VOIDmode, GET_CODE (op),
4286 case UNSIGNED_FLOAT:
4289 case FLOAT_TRUNCATE:
4290 *total = mips_cost->fp_add;
4294 if (register_operand (SET_DEST (x), VOIDmode)
4295 && reg_or_0_operand (SET_SRC (x), VOIDmode))
4297 *total = mips_set_reg_reg_cost (GET_MODE (SET_DEST (x)));
4307 /* Implement TARGET_ADDRESS_COST. */
4310 mips_address_cost (rtx addr, machine_mode mode,
4311 addr_space_t as ATTRIBUTE_UNUSED,
4312 bool speed ATTRIBUTE_UNUSED)
4314 return mips_address_insns (addr, mode, false);
4317 /* Implement TARGET_NO_SPECULATION_IN_DELAY_SLOTS_P. */
4320 mips_no_speculation_in_delay_slots_p ()
4322 return TARGET_CB_MAYBE;
4325 /* Information about a single instruction in a multi-instruction
4327 struct mips_multi_member {
4328 /* True if this is a label, false if it is code. */
4331 /* The output_asm_insn format of the instruction. */
4334 /* The operands to the instruction. */
4335 rtx operands[MAX_RECOG_OPERANDS];
4337 typedef struct mips_multi_member mips_multi_member;
4339 /* The instructions that make up the current multi-insn sequence. */
4340 static vec<mips_multi_member> mips_multi_members;
4342 /* How many instructions (as opposed to labels) are in the current
4343 multi-insn sequence. */
4344 static unsigned int mips_multi_num_insns;
4346 /* Start a new multi-insn sequence. */
4349 mips_multi_start (void)
4351 mips_multi_members.truncate (0);
4352 mips_multi_num_insns = 0;
4355 /* Add a new, uninitialized member to the current multi-insn sequence. */
4357 static struct mips_multi_member *
4358 mips_multi_add (void)
4360 mips_multi_member empty;
4361 return mips_multi_members.safe_push (empty);
4364 /* Add a normal insn with the given asm format to the current multi-insn
4365 sequence. The other arguments are a null-terminated list of operands. */
4368 mips_multi_add_insn (const char *format, ...)
4370 struct mips_multi_member *member;
4375 member = mips_multi_add ();
4376 member->is_label_p = false;
4377 member->format = format;
4378 va_start (ap, format);
4380 while ((op = va_arg (ap, rtx)))
4381 member->operands[i++] = op;
4383 mips_multi_num_insns++;
4386 /* Add the given label definition to the current multi-insn sequence.
4387 The definition should include the colon. */
4390 mips_multi_add_label (const char *label)
4392 struct mips_multi_member *member;
4394 member = mips_multi_add ();
4395 member->is_label_p = true;
4396 member->format = label;
4399 /* Return the index of the last member of the current multi-insn sequence. */
4402 mips_multi_last_index (void)
4404 return mips_multi_members.length () - 1;
4407 /* Add a copy of an existing instruction to the current multi-insn
4408 sequence. I is the index of the instruction that should be copied. */
4411 mips_multi_copy_insn (unsigned int i)
4413 struct mips_multi_member *member;
4415 member = mips_multi_add ();
4416 memcpy (member, &mips_multi_members[i], sizeof (*member));
4417 gcc_assert (!member->is_label_p);
4420 /* Change the operand of an existing instruction in the current
4421 multi-insn sequence. I is the index of the instruction,
4422 OP is the index of the operand, and X is the new value. */
4425 mips_multi_set_operand (unsigned int i, unsigned int op, rtx x)
4427 mips_multi_members[i].operands[op] = x;
4430 /* Write out the asm code for the current multi-insn sequence. */
4433 mips_multi_write (void)
4435 struct mips_multi_member *member;
4438 FOR_EACH_VEC_ELT (mips_multi_members, i, member)
4439 if (member->is_label_p)
4440 fprintf (asm_out_file, "%s\n", member->format);
4442 output_asm_insn (member->format, member->operands);
4445 /* Return one word of double-word value OP, taking into account the fixed
4446 endianness of certain registers. HIGH_P is true to select the high part,
4447 false to select the low part. */
4450 mips_subword (rtx op, bool high_p)
4452 unsigned int byte, offset;
4455 mode = GET_MODE (op);
4456 if (mode == VOIDmode)
4457 mode = TARGET_64BIT ? TImode : DImode;
4459 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
4460 byte = UNITS_PER_WORD;
4464 if (FP_REG_RTX_P (op))
4466 /* Paired FPRs are always ordered little-endian. */
4467 offset = (UNITS_PER_WORD < UNITS_PER_HWFPVALUE ? high_p : byte != 0);
4468 return gen_rtx_REG (word_mode, REGNO (op) + offset);
4472 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
4474 return simplify_gen_subreg (word_mode, op, mode, byte);
4477 /* Return true if SRC should be moved into DEST using "MULT $0, $0".
4478 SPLIT_TYPE is the condition under which moves should be split. */
4481 mips_mult_move_p (rtx dest, rtx src, enum mips_split_type split_type)
4483 return ((split_type != SPLIT_FOR_SPEED
4484 || mips_tuning_info.fast_mult_zero_zero_p)
4485 && src == const0_rtx
4487 && GET_MODE_SIZE (GET_MODE (dest)) == 2 * UNITS_PER_WORD
4488 && (ISA_HAS_DSP_MULT
4489 ? ACC_REG_P (REGNO (dest))
4490 : MD_REG_P (REGNO (dest))));
4493 /* Return true if a move from SRC to DEST should be split into two.
4494 SPLIT_TYPE describes the split condition. */
4497 mips_split_move_p (rtx dest, rtx src, enum mips_split_type split_type)
4499 /* Check whether the move can be done using some variant of MULT $0,$0. */
4500 if (mips_mult_move_p (dest, src, split_type))
4503 /* FPR-to-FPR moves can be done in a single instruction, if they're
4505 unsigned int size = GET_MODE_SIZE (GET_MODE (dest));
4506 if (size == 8 && FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
4509 /* Check for floating-point loads and stores. */
4510 if (size == 8 && ISA_HAS_LDC1_SDC1)
4512 if (FP_REG_RTX_P (dest) && MEM_P (src))
4514 if (FP_REG_RTX_P (src) && MEM_P (dest))
4518 /* Otherwise split all multiword moves. */
4519 return size > UNITS_PER_WORD;
4522 /* Split a move from SRC to DEST, given that mips_split_move_p holds.
4523 SPLIT_TYPE describes the split condition. */
4526 mips_split_move (rtx dest, rtx src, enum mips_split_type split_type)
4530 gcc_checking_assert (mips_split_move_p (dest, src, split_type));
4531 if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src))
4533 if (!TARGET_64BIT && GET_MODE (dest) == DImode)
4534 emit_insn (gen_move_doubleword_fprdi (dest, src));
4535 else if (!TARGET_64BIT && GET_MODE (dest) == DFmode)
4536 emit_insn (gen_move_doubleword_fprdf (dest, src));
4537 else if (!TARGET_64BIT && GET_MODE (dest) == V2SFmode)
4538 emit_insn (gen_move_doubleword_fprv2sf (dest, src));
4539 else if (!TARGET_64BIT && GET_MODE (dest) == V2SImode)
4540 emit_insn (gen_move_doubleword_fprv2si (dest, src));
4541 else if (!TARGET_64BIT && GET_MODE (dest) == V4HImode)
4542 emit_insn (gen_move_doubleword_fprv4hi (dest, src));
4543 else if (!TARGET_64BIT && GET_MODE (dest) == V8QImode)
4544 emit_insn (gen_move_doubleword_fprv8qi (dest, src));
4545 else if (TARGET_64BIT && GET_MODE (dest) == TFmode)
4546 emit_insn (gen_move_doubleword_fprtf (dest, src));
4550 else if (REG_P (dest) && REGNO (dest) == MD_REG_FIRST)
4552 low_dest = mips_subword (dest, false);
4553 mips_emit_move (low_dest, mips_subword (src, false));
4555 emit_insn (gen_mthidi_ti (dest, mips_subword (src, true), low_dest));
4557 emit_insn (gen_mthisi_di (dest, mips_subword (src, true), low_dest));
4559 else if (REG_P (src) && REGNO (src) == MD_REG_FIRST)
4561 mips_emit_move (mips_subword (dest, false), mips_subword (src, false));
4563 emit_insn (gen_mfhidi_ti (mips_subword (dest, true), src));
4565 emit_insn (gen_mfhisi_di (mips_subword (dest, true), src));
4569 /* The operation can be split into two normal moves. Decide in
4570 which order to do them. */
4571 low_dest = mips_subword (dest, false);
4572 if (REG_P (low_dest)
4573 && reg_overlap_mentioned_p (low_dest, src))
4575 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4576 mips_emit_move (low_dest, mips_subword (src, false));
4580 mips_emit_move (low_dest, mips_subword (src, false));
4581 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4586 /* Return the split type for instruction INSN. */
4588 static enum mips_split_type
4589 mips_insn_split_type (rtx insn)
4591 basic_block bb = BLOCK_FOR_INSN (insn);
4594 if (optimize_bb_for_speed_p (bb))
4595 return SPLIT_FOR_SPEED;
4597 return SPLIT_FOR_SIZE;
4599 /* Once CFG information has been removed, we should trust the optimization
4600 decisions made by previous passes and only split where necessary. */
4601 return SPLIT_IF_NECESSARY;
4604 /* Return true if a move from SRC to DEST in INSN should be split. */
4607 mips_split_move_insn_p (rtx dest, rtx src, rtx insn)
4609 return mips_split_move_p (dest, src, mips_insn_split_type (insn));
4612 /* Split a move from SRC to DEST in INSN, given that mips_split_move_insn_p
4616 mips_split_move_insn (rtx dest, rtx src, rtx insn)
4618 mips_split_move (dest, src, mips_insn_split_type (insn));
4621 /* Return the appropriate instructions to move SRC into DEST. Assume
4622 that SRC is operand 1 and DEST is operand 0. */
4625 mips_output_move (rtx dest, rtx src)
4627 enum rtx_code dest_code, src_code;
4629 enum mips_symbol_type symbol_type;
4632 dest_code = GET_CODE (dest);
4633 src_code = GET_CODE (src);
4634 mode = GET_MODE (dest);
4635 dbl_p = (GET_MODE_SIZE (mode) == 8);
4637 if (mips_split_move_p (dest, src, SPLIT_IF_NECESSARY))
4640 if ((src_code == REG && GP_REG_P (REGNO (src)))
4641 || (!TARGET_MIPS16 && src == CONST0_RTX (mode)))
4643 if (dest_code == REG)
4645 if (GP_REG_P (REGNO (dest)))
4646 return "move\t%0,%z1";
4648 if (mips_mult_move_p (dest, src, SPLIT_IF_NECESSARY))
4650 if (ISA_HAS_DSP_MULT)
4651 return "mult\t%q0,%.,%.";
4653 return "mult\t%.,%.";
4656 /* Moves to HI are handled by special .md insns. */
4657 if (REGNO (dest) == LO_REGNUM)
4660 if (DSP_ACC_REG_P (REGNO (dest)))
4662 static char retval[] = "mt__\t%z1,%q0";
4664 retval[2] = reg_names[REGNO (dest)][4];
4665 retval[3] = reg_names[REGNO (dest)][5];
4669 if (FP_REG_P (REGNO (dest)))
4670 return dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
4672 if (ALL_COP_REG_P (REGNO (dest)))
4674 static char retval[] = "dmtc_\t%z1,%0";
4676 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4677 return dbl_p ? retval : retval + 1;
4680 if (dest_code == MEM)
4681 switch (GET_MODE_SIZE (mode))
4683 case 1: return "sb\t%z1,%0";
4684 case 2: return "sh\t%z1,%0";
4685 case 4: return "sw\t%z1,%0";
4686 case 8: return "sd\t%z1,%0";
4689 if (dest_code == REG && GP_REG_P (REGNO (dest)))
4691 if (src_code == REG)
4693 /* Moves from HI are handled by special .md insns. */
4694 if (REGNO (src) == LO_REGNUM)
4696 /* When generating VR4120 or VR4130 code, we use MACC and
4697 DMACC instead of MFLO. This avoids both the normal
4698 MIPS III HI/LO hazards and the errata related to
4701 return dbl_p ? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
4705 if (DSP_ACC_REG_P (REGNO (src)))
4707 static char retval[] = "mf__\t%0,%q1";
4709 retval[2] = reg_names[REGNO (src)][4];
4710 retval[3] = reg_names[REGNO (src)][5];
4714 if (FP_REG_P (REGNO (src)))
4715 return dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
4717 if (ALL_COP_REG_P (REGNO (src)))
4719 static char retval[] = "dmfc_\t%0,%1";
4721 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4722 return dbl_p ? retval : retval + 1;
4726 if (src_code == MEM)
4727 switch (GET_MODE_SIZE (mode))
4729 case 1: return "lbu\t%0,%1";
4730 case 2: return "lhu\t%0,%1";
4731 case 4: return "lw\t%0,%1";
4732 case 8: return "ld\t%0,%1";
4735 if (src_code == CONST_INT)
4737 /* Don't use the X format for the operand itself, because that
4738 will give out-of-range numbers for 64-bit hosts and 32-bit
4741 return "li\t%0,%1\t\t\t# %X1";
4743 if (SMALL_OPERAND_UNSIGNED (INTVAL (src)))
4746 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src)))
4750 if (src_code == HIGH)
4751 return TARGET_MIPS16 ? "#" : "lui\t%0,%h1";
4753 if (CONST_GP_P (src))
4754 return "move\t%0,%1";
4756 if (mips_symbolic_constant_p (src, SYMBOL_CONTEXT_LEA, &symbol_type)
4757 && mips_lo_relocs[symbol_type] != 0)
4759 /* A signed 16-bit constant formed by applying a relocation
4760 operator to a symbolic address. */
4761 gcc_assert (!mips_split_p[symbol_type]);
4762 return "li\t%0,%R1";
4765 if (symbolic_operand (src, VOIDmode))
4767 gcc_assert (TARGET_MIPS16
4768 ? TARGET_MIPS16_TEXT_LOADS
4769 : !TARGET_EXPLICIT_RELOCS);
4770 return dbl_p ? "dla\t%0,%1" : "la\t%0,%1";
4773 if (src_code == REG && FP_REG_P (REGNO (src)))
4775 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4777 if (GET_MODE (dest) == V2SFmode)
4778 return "mov.ps\t%0,%1";
4780 return dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1";
4783 if (dest_code == MEM)
4784 return dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0";
4786 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4788 if (src_code == MEM)
4789 return dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1";
4791 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
4793 static char retval[] = "l_c_\t%0,%1";
4795 retval[1] = (dbl_p ? 'd' : 'w');
4796 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4799 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
4801 static char retval[] = "s_c_\t%1,%0";
4803 retval[1] = (dbl_p ? 'd' : 'w');
4804 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4810 /* Return true if CMP1 is a suitable second operand for integer ordering
4811 test CODE. See also the *sCC patterns in mips.md. */
4814 mips_int_order_operand_ok_p (enum rtx_code code, rtx cmp1)
4820 return reg_or_0_operand (cmp1, VOIDmode);
4824 return !TARGET_MIPS16 && cmp1 == const1_rtx;
4828 return arith_operand (cmp1, VOIDmode);
4831 return sle_operand (cmp1, VOIDmode);
4834 return sleu_operand (cmp1, VOIDmode);
4841 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4842 integer ordering test *CODE, or if an equivalent combination can
4843 be formed by adjusting *CODE and *CMP1. When returning true, update
4844 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4848 mips_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1,
4851 HOST_WIDE_INT plus_one;
4853 if (mips_int_order_operand_ok_p (*code, *cmp1))
4856 if (CONST_INT_P (*cmp1))
4860 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4861 if (INTVAL (*cmp1) < plus_one)
4864 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4870 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4874 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4885 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4886 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4887 is nonnull, it's OK to set TARGET to the inverse of the result and
4888 flip *INVERT_PTR instead. */
4891 mips_emit_int_order_test (enum rtx_code code, bool *invert_ptr,
4892 rtx target, rtx cmp0, rtx cmp1)
4896 /* First see if there is a MIPS instruction that can do this operation.
4897 If not, try doing the same for the inverse operation. If that also
4898 fails, force CMP1 into a register and try again. */
4899 mode = GET_MODE (cmp0);
4900 if (mips_canonicalize_int_order_test (&code, &cmp1, mode))
4901 mips_emit_binary (code, target, cmp0, cmp1);
4904 enum rtx_code inv_code = reverse_condition (code);
4905 if (!mips_canonicalize_int_order_test (&inv_code, &cmp1, mode))
4907 cmp1 = force_reg (mode, cmp1);
4908 mips_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1);
4910 else if (invert_ptr == 0)
4914 inv_target = mips_force_binary (GET_MODE (target),
4915 inv_code, cmp0, cmp1);
4916 mips_emit_binary (XOR, target, inv_target, const1_rtx);
4920 *invert_ptr = !*invert_ptr;
4921 mips_emit_binary (inv_code, target, cmp0, cmp1);
4926 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4927 The register will have the same mode as CMP0. */
4930 mips_zero_if_equal (rtx cmp0, rtx cmp1)
4932 if (cmp1 == const0_rtx)
4935 if (uns_arith_operand (cmp1, VOIDmode))
4936 return expand_binop (GET_MODE (cmp0), xor_optab,
4937 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4939 return expand_binop (GET_MODE (cmp0), sub_optab,
4940 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4943 /* Convert *CODE into a code that can be used in a floating-point
4944 scc instruction (C.cond.fmt). Return true if the values of
4945 the condition code registers will be inverted, with 0 indicating
4946 that the condition holds. */
4949 mips_reversed_fp_cond (enum rtx_code *code)
4956 *code = reverse_condition_maybe_unordered (*code);
4964 /* Allocate a floating-point condition-code register of mode MODE.
4966 These condition code registers are used for certain kinds
4967 of compound operation, such as compare and branches, vconds,
4968 and built-in functions. At expand time, their use is entirely
4969 controlled by MIPS-specific code and is entirely internal
4970 to these compound operations.
4972 We could (and did in the past) expose condition-code values
4973 as pseudo registers and leave the register allocator to pick
4974 appropriate registers. The problem is that it is not practically
4975 possible for the rtl optimizers to guarantee that no spills will
4976 be needed, even when AVOID_CCMODE_COPIES is defined. We would
4977 therefore need spill and reload sequences to handle the worst case.
4979 Although such sequences do exist, they are very expensive and are
4980 not something we'd want to use. This is especially true of CCV2 and
4981 CCV4, where all the shuffling would greatly outweigh whatever benefit
4982 the vectorization itself provides.
4984 The main benefit of having more than one condition-code register
4985 is to allow the pipelining of operations, especially those involving
4986 comparisons and conditional moves. We don't really expect the
4987 registers to be live for long periods, and certainly never want
4988 them to be live across calls.
4990 Also, there should be no penalty attached to using all the available
4991 registers. They are simply bits in the same underlying FPU control
4994 We therefore expose the hardware registers from the outset and use
4995 a simple round-robin allocation scheme. */
4998 mips_allocate_fcc (machine_mode mode)
5000 unsigned int regno, count;
5002 gcc_assert (TARGET_HARD_FLOAT && ISA_HAS_8CC);
5006 else if (mode == CCV2mode)
5008 else if (mode == CCV4mode)
5013 cfun->machine->next_fcc += -cfun->machine->next_fcc & (count - 1);
5014 if (cfun->machine->next_fcc > ST_REG_LAST - ST_REG_FIRST)
5015 cfun->machine->next_fcc = 0;
5016 regno = ST_REG_FIRST + cfun->machine->next_fcc;
5017 cfun->machine->next_fcc += count;
5018 return gen_rtx_REG (mode, regno);
5021 /* Convert a comparison into something that can be used in a branch or
5022 conditional move. On entry, *OP0 and *OP1 are the values being
5023 compared and *CODE is the code used to compare them.
5025 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
5026 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
5027 otherwise any standard branch condition can be used. The standard branch
5030 - EQ or NE between two registers.
5031 - any comparison between a register and zero.
5032 - if compact branches are available then any condition is valid. */
5035 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
5040 if (GET_MODE_CLASS (GET_MODE (*op0)) == MODE_INT)
5042 if (!need_eq_ne_p && *op1 == const0_rtx)
5044 else if (*code == EQ || *code == NE)
5048 *op0 = mips_zero_if_equal (cmp_op0, cmp_op1);
5052 *op1 = force_reg (GET_MODE (cmp_op0), cmp_op1);
5054 else if (!need_eq_ne_p && TARGET_CB_MAYBE)
5084 *op1 = force_reg (GET_MODE (cmp_op0), cmp_op1);
5094 /* The comparison needs a separate scc instruction. Store the
5095 result of the scc in *OP0 and compare it against zero. */
5096 bool invert = false;
5097 *op0 = gen_reg_rtx (GET_MODE (cmp_op0));
5098 mips_emit_int_order_test (*code, &invert, *op0, cmp_op0, cmp_op1);
5099 *code = (invert ? EQ : NE);
5103 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0)))
5105 *op0 = gen_rtx_REG (CCDSPmode, CCDSP_CC_REGNUM);
5106 mips_emit_binary (*code, *op0, cmp_op0, cmp_op1);
5112 enum rtx_code cmp_code;
5114 /* Floating-point tests use a separate C.cond.fmt or CMP.cond.fmt
5115 comparison to set a register. The branch or conditional move will
5116 then compare that register against zero.
5118 Set CMP_CODE to the code of the comparison instruction and
5119 *CODE to the code that the branch or move should use. */
5123 /* All FP conditions can be implemented directly with CMP.cond.fmt
5124 or by reversing the operands. */
5126 *op0 = gen_reg_rtx (CCFmode);
5130 /* Three FP conditions cannot be implemented by reversing the
5131 operands for C.cond.fmt, instead a reversed condition code is
5132 required and a test for false. */
5133 *code = mips_reversed_fp_cond (&cmp_code) ? EQ : NE;
5135 *op0 = mips_allocate_fcc (CCmode);
5137 *op0 = gen_rtx_REG (CCmode, FPSW_REGNUM);
5141 mips_emit_binary (cmp_code, *op0, cmp_op0, cmp_op1);
5145 /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2]
5146 and OPERAND[3]. Store the result in OPERANDS[0].
5148 On 64-bit targets, the mode of the comparison and target will always be
5149 SImode, thus possibly narrower than that of the comparison's operands. */
5152 mips_expand_scc (rtx operands[])
5154 rtx target = operands[0];
5155 enum rtx_code code = GET_CODE (operands[1]);
5156 rtx op0 = operands[2];
5157 rtx op1 = operands[3];
5159 gcc_assert (GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT);
5161 if (code == EQ || code == NE)
5164 && reg_imm10_operand (op1, GET_MODE (op1)))
5165 mips_emit_binary (code, target, op0, op1);
5168 rtx zie = mips_zero_if_equal (op0, op1);
5169 mips_emit_binary (code, target, zie, const0_rtx);
5173 mips_emit_int_order_test (code, 0, target, op0, op1);
5176 /* Compare OPERANDS[1] with OPERANDS[2] using comparison code
5177 CODE and jump to OPERANDS[3] if the condition holds. */
5180 mips_expand_conditional_branch (rtx *operands)
5182 enum rtx_code code = GET_CODE (operands[0]);
5183 rtx op0 = operands[1];
5184 rtx op1 = operands[2];
5187 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
5188 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
5189 emit_jump_insn (gen_condjump (condition, operands[3]));
5194 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
5195 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
5198 mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
5199 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
5204 reversed_p = mips_reversed_fp_cond (&cond);
5205 cmp_result = mips_allocate_fcc (CCV2mode);
5206 emit_insn (gen_scc_ps (cmp_result,
5207 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
5209 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
5212 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
5216 /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0]
5217 if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
5220 mips_expand_conditional_move (rtx *operands)
5223 enum rtx_code code = GET_CODE (operands[1]);
5224 rtx op0 = XEXP (operands[1], 0);
5225 rtx op1 = XEXP (operands[1], 1);
5227 mips_emit_compare (&code, &op0, &op1, true);
5228 cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
5230 /* There is no direct support for general conditional GP move involving
5231 two registers using SEL. */
5233 && INTEGRAL_MODE_P (GET_MODE (operands[2]))
5234 && register_operand (operands[2], VOIDmode)
5235 && register_operand (operands[3], VOIDmode))
5237 machine_mode mode = GET_MODE (operands[0]);
5238 rtx temp = gen_reg_rtx (mode);
5239 rtx temp2 = gen_reg_rtx (mode);
5241 emit_insn (gen_rtx_SET (temp,
5242 gen_rtx_IF_THEN_ELSE (mode, cond,
5243 operands[2], const0_rtx)));
5245 /* Flip the test for the second operand. */
5246 cond = gen_rtx_fmt_ee ((code == EQ) ? NE : EQ, GET_MODE (op0), op0, op1);
5248 emit_insn (gen_rtx_SET (temp2,
5249 gen_rtx_IF_THEN_ELSE (mode, cond,
5250 operands[3], const0_rtx)));
5252 /* Merge the two results, at least one is guaranteed to be zero. */
5253 emit_insn (gen_rtx_SET (operands[0], gen_rtx_IOR (mode, temp, temp2)));
5257 if (FLOAT_MODE_P (GET_MODE (operands[2])) && !ISA_HAS_SEL)
5259 operands[2] = force_reg (GET_MODE (operands[0]), operands[2]);
5260 operands[3] = force_reg (GET_MODE (operands[0]), operands[3]);
5263 emit_insn (gen_rtx_SET (operands[0],
5264 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), cond,
5265 operands[2], operands[3])));
5269 /* Perform the comparison in COMPARISON, then trap if the condition holds. */
5272 mips_expand_conditional_trap (rtx comparison)
5278 /* MIPS conditional trap instructions don't have GT or LE flavors,
5279 so we must swap the operands and convert to LT and GE respectively. */
5280 code = GET_CODE (comparison);
5287 code = swap_condition (code);
5288 op0 = XEXP (comparison, 1);
5289 op1 = XEXP (comparison, 0);
5293 op0 = XEXP (comparison, 0);
5294 op1 = XEXP (comparison, 1);
5298 mode = GET_MODE (XEXP (comparison, 0));
5299 op0 = force_reg (mode, op0);
5300 if (!(ISA_HAS_COND_TRAPI
5301 ? arith_operand (op1, mode)
5302 : reg_or_0_operand (op1, mode)))
5303 op1 = force_reg (mode, op1);
5305 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
5306 gen_rtx_fmt_ee (code, mode, op0, op1),
5310 /* Initialize *CUM for a call to a function of type FNTYPE. */
5313 mips_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype)
5315 memset (cum, 0, sizeof (*cum));
5316 cum->prototype = (fntype && prototype_p (fntype));
5317 cum->gp_reg_found = (cum->prototype && stdarg_p (fntype));
5320 /* Fill INFO with information about a single argument. CUM is the
5321 cumulative state for earlier arguments. MODE is the mode of this
5322 argument and TYPE is its type (if known). NAMED is true if this
5323 is a named (fixed) argument rather than a variable one. */
5326 mips_get_arg_info (struct mips_arg_info *info, const CUMULATIVE_ARGS *cum,
5327 machine_mode mode, const_tree type, bool named)
5329 bool doubleword_aligned_p;
5330 unsigned int num_bytes, num_words, max_regs;
5332 /* Work out the size of the argument. */
5333 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
5334 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5336 /* Decide whether it should go in a floating-point register, assuming
5337 one is free. Later code checks for availability.
5339 The checks against UNITS_PER_FPVALUE handle the soft-float and
5340 single-float cases. */
5344 /* The EABI conventions have traditionally been defined in terms
5345 of TYPE_MODE, regardless of the actual type. */
5346 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
5347 || mode == V2SFmode)
5348 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
5353 /* Only leading floating-point scalars are passed in
5354 floating-point registers. We also handle vector floats the same
5355 say, which is OK because they are not covered by the standard ABI. */
5356 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT || mode != V2SFmode);
5357 info->fpr_p = (!cum->gp_reg_found
5358 && cum->arg_number < 2
5360 || SCALAR_FLOAT_TYPE_P (type)
5361 || VECTOR_FLOAT_TYPE_P (type))
5362 && (GET_MODE_CLASS (mode) == MODE_FLOAT
5363 || mode == V2SFmode)
5364 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
5369 /* Scalar, complex and vector floating-point types are passed in
5370 floating-point registers, as long as this is a named rather
5371 than a variable argument. */
5372 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT || mode != V2SFmode);
5373 info->fpr_p = (named
5374 && (type == 0 || FLOAT_TYPE_P (type))
5375 && (GET_MODE_CLASS (mode) == MODE_FLOAT
5376 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5377 || mode == V2SFmode)
5378 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
5380 /* ??? According to the ABI documentation, the real and imaginary
5381 parts of complex floats should be passed in individual registers.
5382 The real and imaginary parts of stack arguments are supposed
5383 to be contiguous and there should be an extra word of padding
5386 This has two problems. First, it makes it impossible to use a
5387 single "void *" va_list type, since register and stack arguments
5388 are passed differently. (At the time of writing, MIPSpro cannot
5389 handle complex float varargs correctly.) Second, it's unclear
5390 what should happen when there is only one register free.
5392 For now, we assume that named complex floats should go into FPRs
5393 if there are two FPRs free, otherwise they should be passed in the
5394 same way as a struct containing two floats. */
5396 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5397 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
5399 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
5400 info->fpr_p = false;
5410 /* See whether the argument has doubleword alignment. */
5411 doubleword_aligned_p = (mips_function_arg_boundary (mode, type)
5414 /* Set REG_OFFSET to the register count we're interested in.
5415 The EABI allocates the floating-point registers separately,
5416 but the other ABIs allocate them like integer registers. */
5417 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
5421 /* Advance to an even register if the argument is doubleword-aligned. */
5422 if (doubleword_aligned_p)
5423 info->reg_offset += info->reg_offset & 1;
5425 /* Work out the offset of a stack argument. */
5426 info->stack_offset = cum->stack_words;
5427 if (doubleword_aligned_p)
5428 info->stack_offset += info->stack_offset & 1;
5430 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
5432 /* Partition the argument between registers and stack. */
5433 info->reg_words = MIN (num_words, max_regs);
5434 info->stack_words = num_words - info->reg_words;
5437 /* INFO describes a register argument that has the normal format for the
5438 argument's mode. Return the register it uses, assuming that FPRs are
5439 available if HARD_FLOAT_P. */
5442 mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p)
5444 if (!info->fpr_p || !hard_float_p)
5445 return GP_ARG_FIRST + info->reg_offset;
5446 else if (mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info->reg_offset > 0)
5447 /* In o32, the second argument is always passed in $f14
5448 for TARGET_DOUBLE_FLOAT, regardless of whether the
5449 first argument was a word or doubleword. */
5450 return FP_ARG_FIRST + 2;
5452 return FP_ARG_FIRST + info->reg_offset;
5455 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
5458 mips_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED)
5460 return !TARGET_OLDABI;
5463 /* Implement TARGET_FUNCTION_ARG. */
5466 mips_function_arg (cumulative_args_t cum_v, machine_mode mode,
5467 const_tree type, bool named)
5469 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
5470 struct mips_arg_info info;
5472 /* We will be called with a mode of VOIDmode after the last argument
5473 has been seen. Whatever we return will be passed to the call expander.
5474 If we need a MIPS16 fp_code, return a REG with the code stored as
5476 if (mode == VOIDmode)
5478 if (TARGET_MIPS16 && cum->fp_code != 0)
5479 return gen_rtx_REG ((machine_mode) cum->fp_code, 0);
5484 mips_get_arg_info (&info, cum, mode, type, named);
5486 /* Return straight away if the whole argument is passed on the stack. */
5487 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
5490 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
5491 contains a double in its entirety, then that 64-bit chunk is passed
5492 in a floating-point register. */
5494 && TARGET_HARD_FLOAT
5497 && TREE_CODE (type) == RECORD_TYPE
5498 && TYPE_SIZE_UNIT (type)
5499 && tree_fits_uhwi_p (TYPE_SIZE_UNIT (type)))
5503 /* First check to see if there is any such field. */
5504 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
5505 if (TREE_CODE (field) == FIELD_DECL
5506 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
5507 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
5508 && tree_fits_shwi_p (bit_position (field))
5509 && int_bit_position (field) % BITS_PER_WORD == 0)
5514 /* Now handle the special case by returning a PARALLEL
5515 indicating where each 64-bit chunk goes. INFO.REG_WORDS
5516 chunks are passed in registers. */
5518 HOST_WIDE_INT bitpos;
5521 /* assign_parms checks the mode of ENTRY_PARM, so we must
5522 use the actual mode here. */
5523 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
5526 field = TYPE_FIELDS (type);
5527 for (i = 0; i < info.reg_words; i++)
5531 for (; field; field = DECL_CHAIN (field))
5532 if (TREE_CODE (field) == FIELD_DECL
5533 && int_bit_position (field) >= bitpos)
5537 && int_bit_position (field) == bitpos
5538 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
5539 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
5540 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
5542 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
5545 = gen_rtx_EXPR_LIST (VOIDmode, reg,
5546 GEN_INT (bitpos / BITS_PER_UNIT));
5548 bitpos += BITS_PER_WORD;
5554 /* Handle the n32/n64 conventions for passing complex floating-point
5555 arguments in FPR pairs. The real part goes in the lower register
5556 and the imaginary part goes in the upper register. */
5559 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5565 inner = GET_MODE_INNER (mode);
5566 regno = FP_ARG_FIRST + info.reg_offset;
5567 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
5569 /* Real part in registers, imaginary part on stack. */
5570 gcc_assert (info.stack_words == info.reg_words);
5571 return gen_rtx_REG (inner, regno);
5575 gcc_assert (info.stack_words == 0);
5576 real = gen_rtx_EXPR_LIST (VOIDmode,
5577 gen_rtx_REG (inner, regno),
5579 imag = gen_rtx_EXPR_LIST (VOIDmode,
5581 regno + info.reg_words / 2),
5582 GEN_INT (GET_MODE_SIZE (inner)));
5583 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
5587 return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT));
5590 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
5593 mips_function_arg_advance (cumulative_args_t cum_v, machine_mode mode,
5594 const_tree type, bool named)
5596 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
5597 struct mips_arg_info info;
5599 mips_get_arg_info (&info, cum, mode, type, named);
5602 cum->gp_reg_found = true;
5604 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
5605 an explanation of what this code does. It assumes that we're using
5606 either the o32 or the o64 ABI, both of which pass at most 2 arguments
5608 if (cum->arg_number < 2 && info.fpr_p)
5609 cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2);
5611 /* Advance the register count. This has the effect of setting
5612 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
5613 argument required us to skip the final GPR and pass the whole
5614 argument on the stack. */
5615 if (mips_abi != ABI_EABI || !info.fpr_p)
5616 cum->num_gprs = info.reg_offset + info.reg_words;
5617 else if (info.reg_words > 0)
5618 cum->num_fprs += MAX_FPRS_PER_FMT;
5620 /* Advance the stack word count. */
5621 if (info.stack_words > 0)
5622 cum->stack_words = info.stack_offset + info.stack_words;
5627 /* Implement TARGET_ARG_PARTIAL_BYTES. */
5630 mips_arg_partial_bytes (cumulative_args_t cum,
5631 machine_mode mode, tree type, bool named)
5633 struct mips_arg_info info;
5635 mips_get_arg_info (&info, get_cumulative_args (cum), mode, type, named);
5636 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
5639 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
5640 least PARM_BOUNDARY bits of alignment, but will be given anything up
5641 to STACK_BOUNDARY bits if the type requires it. */
5644 mips_function_arg_boundary (machine_mode mode, const_tree type)
5646 unsigned int alignment;
5648 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
5649 if (alignment < PARM_BOUNDARY)
5650 alignment = PARM_BOUNDARY;
5651 if (alignment > STACK_BOUNDARY)
5652 alignment = STACK_BOUNDARY;
5656 /* Implement TARGET_GET_RAW_RESULT_MODE and TARGET_GET_RAW_ARG_MODE. */
5659 mips_get_reg_raw_mode (int regno)
5661 if (TARGET_FLOATXX && FP_REG_P (regno))
5663 return default_get_reg_raw_mode (regno);
5666 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
5667 upward rather than downward. In other words, return true if the
5668 first byte of the stack slot has useful data, false if the last
5672 mips_pad_arg_upward (machine_mode mode, const_tree type)
5674 /* On little-endian targets, the first byte of every stack argument
5675 is passed in the first byte of the stack slot. */
5676 if (!BYTES_BIG_ENDIAN)
5679 /* Otherwise, integral types are padded downward: the last byte of a
5680 stack argument is passed in the last byte of the stack slot. */
5682 ? (INTEGRAL_TYPE_P (type)
5683 || POINTER_TYPE_P (type)
5684 || FIXED_POINT_TYPE_P (type))
5685 : (SCALAR_INT_MODE_P (mode)
5686 || ALL_SCALAR_FIXED_POINT_MODE_P (mode)))
5689 /* Big-endian o64 pads floating-point arguments downward. */
5690 if (mips_abi == ABI_O64)
5691 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
5694 /* Other types are padded upward for o32, o64, n32 and n64. */
5695 if (mips_abi != ABI_EABI)
5698 /* Arguments smaller than a stack slot are padded downward. */
5699 if (mode != BLKmode)
5700 return GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY;
5702 return int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT);
5705 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
5706 if the least significant byte of the register has useful data. Return
5707 the opposite if the most significant byte does. */
5710 mips_pad_reg_upward (machine_mode mode, tree type)
5712 /* No shifting is required for floating-point arguments. */
5713 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
5714 return !BYTES_BIG_ENDIAN;
5716 /* Otherwise, apply the same padding to register arguments as we do
5717 to stack arguments. */
5718 return mips_pad_arg_upward (mode, type);
5721 /* Return nonzero when an argument must be passed by reference. */
5724 mips_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
5725 machine_mode mode, const_tree type,
5726 bool named ATTRIBUTE_UNUSED)
5728 if (mips_abi == ABI_EABI)
5732 /* ??? How should SCmode be handled? */
5733 if (mode == DImode || mode == DFmode
5734 || mode == DQmode || mode == UDQmode
5735 || mode == DAmode || mode == UDAmode)
5738 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
5739 return size == -1 || size > UNITS_PER_WORD;
5743 /* If we have a variable-sized parameter, we have no choice. */
5744 return targetm.calls.must_pass_in_stack (mode, type);
5748 /* Implement TARGET_CALLEE_COPIES. */
5751 mips_callee_copies (cumulative_args_t cum ATTRIBUTE_UNUSED,
5752 machine_mode mode ATTRIBUTE_UNUSED,
5753 const_tree type ATTRIBUTE_UNUSED, bool named)
5755 return mips_abi == ABI_EABI && named;
5758 /* See whether VALTYPE is a record whose fields should be returned in
5759 floating-point registers. If so, return the number of fields and
5760 list them in FIELDS (which should have two elements). Return 0
5763 For n32 & n64, a structure with one or two fields is returned in
5764 floating-point registers as long as every field has a floating-point
5768 mips_fpr_return_fields (const_tree valtype, tree *fields)
5776 if (TREE_CODE (valtype) != RECORD_TYPE)
5780 for (field = TYPE_FIELDS (valtype); field != 0; field = DECL_CHAIN (field))
5782 if (TREE_CODE (field) != FIELD_DECL)
5785 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)))
5791 fields[i++] = field;
5796 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
5797 a value in the most significant part of $2/$3 if:
5799 - the target is big-endian;
5801 - the value has a structure or union type (we generalize this to
5802 cover aggregates from other languages too); and
5804 - the structure is not returned in floating-point registers. */
5807 mips_return_in_msb (const_tree valtype)
5811 return (TARGET_NEWABI
5812 && TARGET_BIG_ENDIAN
5813 && AGGREGATE_TYPE_P (valtype)
5814 && mips_fpr_return_fields (valtype, fields) == 0);
5817 /* Return true if the function return value MODE will get returned in a
5818 floating-point register. */
5821 mips_return_mode_in_fpr_p (machine_mode mode)
5823 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT || mode != V2SFmode);
5824 return ((GET_MODE_CLASS (mode) == MODE_FLOAT
5826 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5827 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE);
5830 /* Return the representation of an FPR return register when the
5831 value being returned in FP_RETURN has mode VALUE_MODE and the
5832 return type itself has mode TYPE_MODE. On NewABI targets,
5833 the two modes may be different for structures like:
5835 struct __attribute__((packed)) foo { float f; }
5837 where we return the SFmode value of "f" in FP_RETURN, but where
5838 the structure itself has mode BLKmode. */
5841 mips_return_fpr_single (machine_mode type_mode,
5842 machine_mode value_mode)
5846 x = gen_rtx_REG (value_mode, FP_RETURN);
5847 if (type_mode != value_mode)
5849 x = gen_rtx_EXPR_LIST (VOIDmode, x, const0_rtx);
5850 x = gen_rtx_PARALLEL (type_mode, gen_rtvec (1, x));
5855 /* Return a composite value in a pair of floating-point registers.
5856 MODE1 and OFFSET1 are the mode and byte offset for the first value,
5857 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
5860 For n32 & n64, $f0 always holds the first value and $f2 the second.
5861 Otherwise the values are packed together as closely as possible. */
5864 mips_return_fpr_pair (machine_mode mode,
5865 machine_mode mode1, HOST_WIDE_INT offset1,
5866 machine_mode mode2, HOST_WIDE_INT offset2)
5870 inc = (TARGET_NEWABI || mips_abi == ABI_32 ? 2 : MAX_FPRS_PER_FMT);
5871 return gen_rtx_PARALLEL
5874 gen_rtx_EXPR_LIST (VOIDmode,
5875 gen_rtx_REG (mode1, FP_RETURN),
5877 gen_rtx_EXPR_LIST (VOIDmode,
5878 gen_rtx_REG (mode2, FP_RETURN + inc),
5879 GEN_INT (offset2))));
5883 /* Implement TARGET_FUNCTION_VALUE and TARGET_LIBCALL_VALUE.
5884 For normal calls, VALTYPE is the return type and MODE is VOIDmode.
5885 For libcalls, VALTYPE is null and MODE is the mode of the return value. */
5888 mips_function_value_1 (const_tree valtype, const_tree fn_decl_or_type,
5897 if (fn_decl_or_type && DECL_P (fn_decl_or_type))
5898 func = fn_decl_or_type;
5902 mode = TYPE_MODE (valtype);
5903 unsigned_p = TYPE_UNSIGNED (valtype);
5905 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
5906 return values, promote the mode here too. */
5907 mode = promote_function_mode (valtype, mode, &unsigned_p, func, 1);
5909 /* Handle structures whose fields are returned in $f0/$f2. */
5910 switch (mips_fpr_return_fields (valtype, fields))
5913 return mips_return_fpr_single (mode,
5914 TYPE_MODE (TREE_TYPE (fields[0])));
5917 return mips_return_fpr_pair (mode,
5918 TYPE_MODE (TREE_TYPE (fields[0])),
5919 int_byte_position (fields[0]),
5920 TYPE_MODE (TREE_TYPE (fields[1])),
5921 int_byte_position (fields[1]));
5924 /* If a value is passed in the most significant part of a register, see
5925 whether we have to round the mode up to a whole number of words. */
5926 if (mips_return_in_msb (valtype))
5928 HOST_WIDE_INT size = int_size_in_bytes (valtype);
5929 if (size % UNITS_PER_WORD != 0)
5931 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
5932 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
5936 /* For EABI, the class of return register depends entirely on MODE.
5937 For example, "struct { some_type x; }" and "union { some_type x; }"
5938 are returned in the same way as a bare "some_type" would be.
5939 Other ABIs only use FPRs for scalar, complex or vector types. */
5940 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
5941 return gen_rtx_REG (mode, GP_RETURN);
5946 /* Handle long doubles for n32 & n64. */
5948 return mips_return_fpr_pair (mode,
5950 DImode, GET_MODE_SIZE (mode) / 2);
5952 if (mips_return_mode_in_fpr_p (mode))
5954 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5955 return mips_return_fpr_pair (mode,
5956 GET_MODE_INNER (mode), 0,
5957 GET_MODE_INNER (mode),
5958 GET_MODE_SIZE (mode) / 2);
5960 return gen_rtx_REG (mode, FP_RETURN);
5964 return gen_rtx_REG (mode, GP_RETURN);
5967 /* Implement TARGET_FUNCTION_VALUE. */
5970 mips_function_value (const_tree valtype, const_tree fn_decl_or_type,
5971 bool outgoing ATTRIBUTE_UNUSED)
5973 return mips_function_value_1 (valtype, fn_decl_or_type, VOIDmode);
5976 /* Implement TARGET_LIBCALL_VALUE. */
5979 mips_libcall_value (machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
5981 return mips_function_value_1 (NULL_TREE, NULL_TREE, mode);
5984 /* Implement TARGET_FUNCTION_VALUE_REGNO_P.
5986 On the MIPS, R2 R3 and F0 F2 are the only register thus used. */
5989 mips_function_value_regno_p (const unsigned int regno)
5991 /* Most types only require one GPR or one FPR for return values but for
5992 hard-float two FPRs can be used for _Complex types (for all ABIs)
5993 and long doubles (for n64). */
5994 if (regno == GP_RETURN
5995 || regno == FP_RETURN
5996 || (FP_RETURN != GP_RETURN
5997 && regno == FP_RETURN + 2))
6000 /* For o32 FP32, _Complex double will be returned in four 32-bit registers.
6001 This does not apply to o32 FPXX as floating-point function argument and
6002 return registers are described as 64-bit even though floating-point
6003 registers are primarily described as 32-bit internally.
6004 See: mips_get_reg_raw_mode. */
6005 if ((mips_abi == ABI_32 && TARGET_FLOAT32)
6006 && FP_RETURN != GP_RETURN
6007 && (regno == FP_RETURN + 1
6008 || regno == FP_RETURN + 3))
6014 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
6015 all BLKmode objects are returned in memory. Under the n32, n64
6016 and embedded ABIs, small structures are returned in a register.
6017 Objects with varying size must still be returned in memory, of
6021 mips_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
6023 return (TARGET_OLDABI
6024 ? TYPE_MODE (type) == BLKmode
6025 : !IN_RANGE (int_size_in_bytes (type), 0, 2 * UNITS_PER_WORD));
6028 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
6031 mips_setup_incoming_varargs (cumulative_args_t cum, machine_mode mode,
6032 tree type, int *pretend_size ATTRIBUTE_UNUSED,
6035 CUMULATIVE_ARGS local_cum;
6036 int gp_saved, fp_saved;
6038 /* The caller has advanced CUM up to, but not beyond, the last named
6039 argument. Advance a local copy of CUM past the last "real" named
6040 argument, to find out how many registers are left over. */
6041 local_cum = *get_cumulative_args (cum);
6042 mips_function_arg_advance (pack_cumulative_args (&local_cum), mode, type,
6045 /* Found out how many registers we need to save. */
6046 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
6047 fp_saved = (EABI_FLOAT_VARARGS_P
6048 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
6057 ptr = plus_constant (Pmode, virtual_incoming_args_rtx,
6058 REG_PARM_STACK_SPACE (cfun->decl)
6059 - gp_saved * UNITS_PER_WORD);
6060 mem = gen_frame_mem (BLKmode, ptr);
6061 set_mem_alias_set (mem, get_varargs_alias_set ());
6063 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
6068 /* We can't use move_block_from_reg, because it will use
6073 /* Set OFF to the offset from virtual_incoming_args_rtx of
6074 the first float register. The FP save area lies below
6075 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
6076 off = ROUND_DOWN (-gp_saved * UNITS_PER_WORD, UNITS_PER_FPVALUE);
6077 off -= fp_saved * UNITS_PER_FPREG;
6079 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
6081 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS;
6082 i += MAX_FPRS_PER_FMT)
6086 ptr = plus_constant (Pmode, virtual_incoming_args_rtx, off);
6087 mem = gen_frame_mem (mode, ptr);
6088 set_mem_alias_set (mem, get_varargs_alias_set ());
6089 mips_emit_move (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
6090 off += UNITS_PER_HWFPVALUE;
6094 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
6095 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
6096 + fp_saved * UNITS_PER_FPREG);
6099 /* Implement TARGET_BUILTIN_VA_LIST. */
6102 mips_build_builtin_va_list (void)
6104 if (EABI_FLOAT_VARARGS_P)
6106 /* We keep 3 pointers, and two offsets.
6108 Two pointers are to the overflow area, which starts at the CFA.
6109 One of these is constant, for addressing into the GPR save area
6110 below it. The other is advanced up the stack through the
6113 The third pointer is to the bottom of the GPR save area.
6114 Since the FPR save area is just below it, we can address
6115 FPR slots off this pointer.
6117 We also keep two one-byte offsets, which are to be subtracted
6118 from the constant pointers to yield addresses in the GPR and
6119 FPR save areas. These are downcounted as float or non-float
6120 arguments are used, and when they get to zero, the argument
6121 must be obtained from the overflow region. */
6122 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
6125 record = lang_hooks.types.make_type (RECORD_TYPE);
6127 f_ovfl = build_decl (BUILTINS_LOCATION,
6128 FIELD_DECL, get_identifier ("__overflow_argptr"),
6130 f_gtop = build_decl (BUILTINS_LOCATION,
6131 FIELD_DECL, get_identifier ("__gpr_top"),
6133 f_ftop = build_decl (BUILTINS_LOCATION,
6134 FIELD_DECL, get_identifier ("__fpr_top"),
6136 f_goff = build_decl (BUILTINS_LOCATION,
6137 FIELD_DECL, get_identifier ("__gpr_offset"),
6138 unsigned_char_type_node);
6139 f_foff = build_decl (BUILTINS_LOCATION,
6140 FIELD_DECL, get_identifier ("__fpr_offset"),
6141 unsigned_char_type_node);
6142 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
6143 warn on every user file. */
6144 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
6145 array = build_array_type (unsigned_char_type_node,
6146 build_index_type (index));
6147 f_res = build_decl (BUILTINS_LOCATION,
6148 FIELD_DECL, get_identifier ("__reserved"), array);
6150 DECL_FIELD_CONTEXT (f_ovfl) = record;
6151 DECL_FIELD_CONTEXT (f_gtop) = record;
6152 DECL_FIELD_CONTEXT (f_ftop) = record;
6153 DECL_FIELD_CONTEXT (f_goff) = record;
6154 DECL_FIELD_CONTEXT (f_foff) = record;
6155 DECL_FIELD_CONTEXT (f_res) = record;
6157 TYPE_FIELDS (record) = f_ovfl;
6158 DECL_CHAIN (f_ovfl) = f_gtop;
6159 DECL_CHAIN (f_gtop) = f_ftop;
6160 DECL_CHAIN (f_ftop) = f_goff;
6161 DECL_CHAIN (f_goff) = f_foff;
6162 DECL_CHAIN (f_foff) = f_res;
6164 layout_type (record);
6168 /* Otherwise, we use 'void *'. */
6169 return ptr_type_node;
6172 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
6175 mips_va_start (tree valist, rtx nextarg)
6177 if (EABI_FLOAT_VARARGS_P)
6179 const CUMULATIVE_ARGS *cum;
6180 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
6181 tree ovfl, gtop, ftop, goff, foff;
6183 int gpr_save_area_size;
6184 int fpr_save_area_size;
6187 cum = &crtl->args.info;
6189 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
6191 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
6193 f_ovfl = TYPE_FIELDS (va_list_type_node);
6194 f_gtop = DECL_CHAIN (f_ovfl);
6195 f_ftop = DECL_CHAIN (f_gtop);
6196 f_goff = DECL_CHAIN (f_ftop);
6197 f_foff = DECL_CHAIN (f_goff);
6199 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
6201 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
6203 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
6205 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
6207 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
6210 /* Emit code to initialize OVFL, which points to the next varargs
6211 stack argument. CUM->STACK_WORDS gives the number of stack
6212 words used by named arguments. */
6213 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
6214 if (cum->stack_words > 0)
6215 t = fold_build_pointer_plus_hwi (t, cum->stack_words * UNITS_PER_WORD);
6216 t = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
6217 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6219 /* Emit code to initialize GTOP, the top of the GPR save area. */
6220 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
6221 t = build2 (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
6222 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6224 /* Emit code to initialize FTOP, the top of the FPR save area.
6225 This address is gpr_save_area_bytes below GTOP, rounded
6226 down to the next fp-aligned boundary. */
6227 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
6228 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
6229 fpr_offset &= -UNITS_PER_FPVALUE;
6231 t = fold_build_pointer_plus_hwi (t, -fpr_offset);
6232 t = build2 (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
6233 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6235 /* Emit code to initialize GOFF, the offset from GTOP of the
6236 next GPR argument. */
6237 t = build2 (MODIFY_EXPR, TREE_TYPE (goff), goff,
6238 build_int_cst (TREE_TYPE (goff), gpr_save_area_size));
6239 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6241 /* Likewise emit code to initialize FOFF, the offset from FTOP
6242 of the next FPR argument. */
6243 t = build2 (MODIFY_EXPR, TREE_TYPE (foff), foff,
6244 build_int_cst (TREE_TYPE (foff), fpr_save_area_size));
6245 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6249 nextarg = plus_constant (Pmode, nextarg, -cfun->machine->varargs_size);
6250 std_expand_builtin_va_start (valist, nextarg);
6254 /* Like std_gimplify_va_arg_expr, but apply alignment to zero-sized
6258 mips_std_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
6261 tree addr, t, type_size, rounded_size, valist_tmp;
6262 unsigned HOST_WIDE_INT align, boundary;
6265 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, false);
6267 type = build_pointer_type (type);
6269 align = PARM_BOUNDARY / BITS_PER_UNIT;
6270 boundary = targetm.calls.function_arg_boundary (TYPE_MODE (type), type);
6272 /* When we align parameter on stack for caller, if the parameter
6273 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
6274 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
6275 here with caller. */
6276 if (boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
6277 boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
6279 boundary /= BITS_PER_UNIT;
6281 /* Hoist the valist value into a temporary for the moment. */
6282 valist_tmp = get_initialized_tmp_var (valist, pre_p, NULL);
6284 /* va_list pointer is aligned to PARM_BOUNDARY. If argument actually
6285 requires greater alignment, we must perform dynamic alignment. */
6286 if (boundary > align)
6288 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
6289 fold_build_pointer_plus_hwi (valist_tmp, boundary - 1));
6290 gimplify_and_add (t, pre_p);
6292 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
6293 fold_build2 (BIT_AND_EXPR, TREE_TYPE (valist),
6295 build_int_cst (TREE_TYPE (valist), -boundary)));
6296 gimplify_and_add (t, pre_p);
6301 /* If the actual alignment is less than the alignment of the type,
6302 adjust the type accordingly so that we don't assume strict alignment
6303 when dereferencing the pointer. */
6304 boundary *= BITS_PER_UNIT;
6305 if (boundary < TYPE_ALIGN (type))
6307 type = build_variant_type_copy (type);
6308 TYPE_ALIGN (type) = boundary;
6311 /* Compute the rounded size of the type. */
6312 type_size = size_in_bytes (type);
6313 rounded_size = round_up (type_size, align);
6315 /* Reduce rounded_size so it's sharable with the postqueue. */
6316 gimplify_expr (&rounded_size, pre_p, post_p, is_gimple_val, fb_rvalue);
6320 if (PAD_VARARGS_DOWN && !integer_zerop (rounded_size))
6322 /* Small args are padded downward. */
6323 t = fold_build2_loc (input_location, GT_EXPR, sizetype,
6324 rounded_size, size_int (align));
6325 t = fold_build3 (COND_EXPR, sizetype, t, size_zero_node,
6326 size_binop (MINUS_EXPR, rounded_size, type_size));
6327 addr = fold_build_pointer_plus (addr, t);
6330 /* Compute new value for AP. */
6331 t = fold_build_pointer_plus (valist_tmp, rounded_size);
6332 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
6333 gimplify_and_add (t, pre_p);
6335 addr = fold_convert (build_pointer_type (type), addr);
6338 addr = build_va_arg_indirect_ref (addr);
6340 return build_va_arg_indirect_ref (addr);
6343 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
6346 mips_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
6352 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
6354 type = build_pointer_type (type);
6356 if (!EABI_FLOAT_VARARGS_P)
6357 addr = mips_std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6360 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
6361 tree ovfl, top, off, align;
6362 HOST_WIDE_INT size, rsize, osize;
6365 f_ovfl = TYPE_FIELDS (va_list_type_node);
6366 f_gtop = DECL_CHAIN (f_ovfl);
6367 f_ftop = DECL_CHAIN (f_gtop);
6368 f_goff = DECL_CHAIN (f_ftop);
6369 f_foff = DECL_CHAIN (f_goff);
6373 TOP be the top of the GPR or FPR save area;
6374 OFF be the offset from TOP of the next register;
6375 ADDR_RTX be the address of the argument;
6376 SIZE be the number of bytes in the argument type;
6377 RSIZE be the number of bytes used to store the argument
6378 when it's in the register save area; and
6379 OSIZE be the number of bytes used to store it when it's
6380 in the stack overflow area.
6382 The code we want is:
6384 1: off &= -rsize; // round down
6387 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
6392 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
6393 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
6397 [1] and [9] can sometimes be optimized away. */
6399 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
6401 size = int_size_in_bytes (type);
6403 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
6404 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
6406 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop),
6407 unshare_expr (valist), f_ftop, NULL_TREE);
6408 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff),
6409 unshare_expr (valist), f_foff, NULL_TREE);
6411 /* When va_start saves FPR arguments to the stack, each slot
6412 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
6413 argument's precision. */
6414 rsize = UNITS_PER_HWFPVALUE;
6416 /* Overflow arguments are padded to UNITS_PER_WORD bytes
6417 (= PARM_BOUNDARY bits). This can be different from RSIZE
6420 (1) On 32-bit targets when TYPE is a structure such as:
6422 struct s { float f; };
6424 Such structures are passed in paired FPRs, so RSIZE
6425 will be 8 bytes. However, the structure only takes
6426 up 4 bytes of memory, so OSIZE will only be 4.
6428 (2) In combinations such as -mgp64 -msingle-float
6429 -fshort-double. Doubles passed in registers will then take
6430 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
6431 stack take up UNITS_PER_WORD bytes. */
6432 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
6436 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop),
6437 unshare_expr (valist), f_gtop, NULL_TREE);
6438 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff),
6439 unshare_expr (valist), f_goff, NULL_TREE);
6440 rsize = ROUND_UP (size, UNITS_PER_WORD);
6441 if (rsize > UNITS_PER_WORD)
6443 /* [1] Emit code for: off &= -rsize. */
6444 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), unshare_expr (off),
6445 build_int_cst (TREE_TYPE (off), -rsize));
6446 gimplify_assign (unshare_expr (off), t, pre_p);
6451 /* [2] Emit code to branch if off == 0. */
6452 t = build2 (NE_EXPR, boolean_type_node, unshare_expr (off),
6453 build_int_cst (TREE_TYPE (off), 0));
6454 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
6456 /* [5] Emit code for: off -= rsize. We do this as a form of
6457 post-decrement not available to C. */
6458 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
6459 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
6461 /* [4] Emit code for:
6462 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
6463 t = fold_convert (sizetype, t);
6464 t = fold_build1 (NEGATE_EXPR, sizetype, t);
6465 t = fold_build_pointer_plus (top, t);
6466 if (BYTES_BIG_ENDIAN && rsize > size)
6467 t = fold_build_pointer_plus_hwi (t, rsize - size);
6468 COND_EXPR_THEN (addr) = t;
6470 if (osize > UNITS_PER_WORD)
6472 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
6473 t = fold_build_pointer_plus_hwi (unshare_expr (ovfl), osize - 1);
6474 u = build_int_cst (TREE_TYPE (t), -osize);
6475 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t, u);
6476 align = build2 (MODIFY_EXPR, TREE_TYPE (ovfl),
6477 unshare_expr (ovfl), t);
6482 /* [10, 11] Emit code for:
6483 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
6485 u = fold_convert (TREE_TYPE (ovfl), build_int_cst (NULL_TREE, osize));
6486 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
6487 if (BYTES_BIG_ENDIAN && osize > size)
6488 t = fold_build_pointer_plus_hwi (t, osize - size);
6490 /* String [9] and [10, 11] together. */
6492 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
6493 COND_EXPR_ELSE (addr) = t;
6495 addr = fold_convert (build_pointer_type (type), addr);
6496 addr = build_va_arg_indirect_ref (addr);
6500 addr = build_va_arg_indirect_ref (addr);
6505 /* Declare a unique, locally-binding function called NAME, then start
6509 mips_start_unique_function (const char *name)
6513 decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
6514 get_identifier (name),
6515 build_function_type_list (void_type_node, NULL_TREE));
6516 DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
6517 NULL_TREE, void_type_node);
6518 TREE_PUBLIC (decl) = 1;
6519 TREE_STATIC (decl) = 1;
6521 cgraph_node::create (decl)->set_comdat_group (DECL_ASSEMBLER_NAME (decl));
6523 targetm.asm_out.unique_section (decl, 0);
6524 switch_to_section (get_named_section (decl, NULL, 0));
6526 targetm.asm_out.globalize_label (asm_out_file, name);
6527 fputs ("\t.hidden\t", asm_out_file);
6528 assemble_name (asm_out_file, name);
6529 putc ('\n', asm_out_file);
6532 /* Start a definition of function NAME. MIPS16_P indicates whether the
6533 function contains MIPS16 code. */
6536 mips_start_function_definition (const char *name, bool mips16_p)
6539 fprintf (asm_out_file, "\t.set\tmips16\n");
6541 fprintf (asm_out_file, "\t.set\tnomips16\n");
6543 if (TARGET_MICROMIPS)
6544 fprintf (asm_out_file, "\t.set\tmicromips\n");
6545 #ifdef HAVE_GAS_MICROMIPS
6547 fprintf (asm_out_file, "\t.set\tnomicromips\n");
6550 if (!flag_inhibit_size_directive)
6552 fputs ("\t.ent\t", asm_out_file);
6553 assemble_name (asm_out_file, name);
6554 fputs ("\n", asm_out_file);
6557 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, name, "function");
6559 /* Start the definition proper. */
6560 assemble_name (asm_out_file, name);
6561 fputs (":\n", asm_out_file);
6564 /* End a function definition started by mips_start_function_definition. */
6567 mips_end_function_definition (const char *name)
6569 if (!flag_inhibit_size_directive)
6571 fputs ("\t.end\t", asm_out_file);
6572 assemble_name (asm_out_file, name);
6573 fputs ("\n", asm_out_file);
6577 /* If *STUB_PTR points to a stub, output a comdat-style definition for it,
6578 then free *STUB_PTR. */
6581 mips_finish_stub (mips_one_only_stub **stub_ptr)
6583 mips_one_only_stub *stub = *stub_ptr;
6587 const char *name = stub->get_name ();
6588 mips_start_unique_function (name);
6589 mips_start_function_definition (name, false);
6590 stub->output_body ();
6591 mips_end_function_definition (name);
6596 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
6599 mips_ok_for_lazy_binding_p (rtx x)
6601 return (TARGET_USE_GOT
6602 && GET_CODE (x) == SYMBOL_REF
6603 && !SYMBOL_REF_BIND_NOW_P (x)
6604 && !mips_symbol_binds_local_p (x));
6607 /* Load function address ADDR into register DEST. TYPE is as for
6608 mips_expand_call. Return true if we used an explicit lazy-binding
6612 mips_load_call_address (enum mips_call_type type, rtx dest, rtx addr)
6614 /* If we're generating PIC, and this call is to a global function,
6615 try to allow its address to be resolved lazily. This isn't
6616 possible for sibcalls when $gp is call-saved because the value
6617 of $gp on entry to the stub would be our caller's gp, not ours. */
6618 if (TARGET_EXPLICIT_RELOCS
6619 && !(type == MIPS_CALL_SIBCALL && TARGET_CALL_SAVED_GP)
6620 && mips_ok_for_lazy_binding_p (addr))
6622 addr = mips_got_load (dest, addr, SYMBOL_GOTOFF_CALL);
6623 emit_insn (gen_rtx_SET (dest, addr));
6628 mips_emit_move (dest, addr);
6633 /* Each locally-defined hard-float MIPS16 function has a local symbol
6634 associated with it. This hash table maps the function symbol (FUNC)
6635 to the local symbol (LOCAL). */
6636 static GTY (()) hash_map<nofree_string_hash, rtx> *mips16_local_aliases;
6638 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
6639 Return a local alias for it, creating a new one if necessary. */
6642 mips16_local_alias (rtx func)
6644 /* Create the hash table if this is the first call. */
6645 if (mips16_local_aliases == NULL)
6646 mips16_local_aliases = hash_map<nofree_string_hash, rtx>::create_ggc (37);
6648 /* Look up the function symbol, creating a new entry if need be. */
6650 const char *func_name = XSTR (func, 0);
6651 rtx *slot = &mips16_local_aliases->get_or_insert (func_name, &existed);
6652 gcc_assert (slot != NULL);
6658 /* Create a new SYMBOL_REF for the local symbol. The choice of
6659 __fn_local_* is based on the __fn_stub_* names that we've
6660 traditionally used for the non-MIPS16 stub. */
6661 func_name = targetm.strip_name_encoding (XSTR (func, 0));
6662 const char *local_name = ACONCAT (("__fn_local_", func_name, NULL));
6663 local = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (local_name));
6664 SYMBOL_REF_FLAGS (local) = SYMBOL_REF_FLAGS (func) | SYMBOL_FLAG_LOCAL;
6666 /* Create a new structure to represent the mapping. */
6672 /* A chained list of functions for which mips16_build_call_stub has already
6673 generated a stub. NAME is the name of the function and FP_RET_P is true
6674 if the function returns a value in floating-point registers. */
6675 struct mips16_stub {
6676 struct mips16_stub *next;
6680 static struct mips16_stub *mips16_stubs;
6682 /* Return the two-character string that identifies floating-point
6683 return mode MODE in the name of a MIPS16 function stub. */
6686 mips16_call_stub_mode_suffix (machine_mode mode)
6690 else if (mode == DFmode)
6692 else if (mode == SCmode)
6694 else if (mode == DCmode)
6696 else if (mode == V2SFmode)
6698 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT);
6705 /* Write instructions to move a 32-bit value between general register
6706 GPREG and floating-point register FPREG. DIRECTION is 't' to move
6707 from GPREG to FPREG and 'f' to move in the opposite direction. */
6710 mips_output_32bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
6712 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6713 reg_names[gpreg], reg_names[fpreg]);
6716 /* Likewise for 64-bit values. */
6719 mips_output_64bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
6722 fprintf (asm_out_file, "\tdm%cc1\t%s,%s\n", direction,
6723 reg_names[gpreg], reg_names[fpreg]);
6724 else if (ISA_HAS_MXHC1)
6726 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6727 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
6728 fprintf (asm_out_file, "\tm%chc1\t%s,%s\n", direction,
6729 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg]);
6731 else if (TARGET_FLOATXX && direction == 't')
6733 /* Use the argument save area to move via memory. */
6734 fprintf (asm_out_file, "\tsw\t%s,0($sp)\n", reg_names[gpreg]);
6735 fprintf (asm_out_file, "\tsw\t%s,4($sp)\n", reg_names[gpreg + 1]);
6736 fprintf (asm_out_file, "\tldc1\t%s,0($sp)\n", reg_names[fpreg]);
6738 else if (TARGET_FLOATXX && direction == 'f')
6740 /* Use the argument save area to move via memory. */
6741 fprintf (asm_out_file, "\tsdc1\t%s,0($sp)\n", reg_names[fpreg]);
6742 fprintf (asm_out_file, "\tlw\t%s,0($sp)\n", reg_names[gpreg]);
6743 fprintf (asm_out_file, "\tlw\t%s,4($sp)\n", reg_names[gpreg + 1]);
6747 /* Move the least-significant word. */
6748 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6749 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
6750 /* ...then the most significant word. */
6751 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6752 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg + 1]);
6756 /* Write out code to move floating-point arguments into or out of
6757 general registers. FP_CODE is the code describing which arguments
6758 are present (see the comment above the definition of CUMULATIVE_ARGS
6759 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
6762 mips_output_args_xfer (int fp_code, char direction)
6764 unsigned int gparg, fparg, f;
6765 CUMULATIVE_ARGS cum;
6767 /* This code only works for o32 and o64. */
6768 gcc_assert (TARGET_OLDABI);
6770 mips_init_cumulative_args (&cum, NULL);
6772 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
6775 struct mips_arg_info info;
6779 else if ((f & 3) == 2)
6784 mips_get_arg_info (&info, &cum, mode, NULL, true);
6785 gparg = mips_arg_regno (&info, false);
6786 fparg = mips_arg_regno (&info, true);
6789 mips_output_32bit_xfer (direction, gparg, fparg);
6791 mips_output_64bit_xfer (direction, gparg, fparg);
6793 mips_function_arg_advance (pack_cumulative_args (&cum), mode, NULL, true);
6797 /* Write a MIPS16 stub for the current function. This stub is used
6798 for functions which take arguments in the floating-point registers.
6799 It is normal-mode code that moves the floating-point arguments
6800 into the general registers and then jumps to the MIPS16 code. */
6803 mips16_build_function_stub (void)
6805 const char *fnname, *alias_name, *separator;
6806 char *secname, *stubname;
6811 /* Create the name of the stub, and its unique section. */
6812 symbol = XEXP (DECL_RTL (current_function_decl), 0);
6813 alias = mips16_local_alias (symbol);
6815 fnname = targetm.strip_name_encoding (XSTR (symbol, 0));
6816 alias_name = targetm.strip_name_encoding (XSTR (alias, 0));
6817 secname = ACONCAT ((".mips16.fn.", fnname, NULL));
6818 stubname = ACONCAT (("__fn_stub_", fnname, NULL));
6820 /* Build a decl for the stub. */
6821 stubdecl = build_decl (BUILTINS_LOCATION,
6822 FUNCTION_DECL, get_identifier (stubname),
6823 build_function_type_list (void_type_node, NULL_TREE));
6824 set_decl_section_name (stubdecl, secname);
6825 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
6826 RESULT_DECL, NULL_TREE, void_type_node);
6828 /* Output a comment. */
6829 fprintf (asm_out_file, "\t# Stub function for %s (",
6830 current_function_name ());
6832 for (f = (unsigned int) crtl->args.info.fp_code; f != 0; f >>= 2)
6834 fprintf (asm_out_file, "%s%s", separator,
6835 (f & 3) == 1 ? "float" : "double");
6838 fprintf (asm_out_file, ")\n");
6840 /* Start the function definition. */
6841 assemble_start_function (stubdecl, stubname);
6842 mips_start_function_definition (stubname, false);
6844 /* If generating pic2 code, either set up the global pointer or
6846 if (TARGET_ABICALLS_PIC2)
6848 if (TARGET_ABSOLUTE_ABICALLS)
6849 fprintf (asm_out_file, "\t.option\tpic0\n");
6852 output_asm_insn ("%(.cpload\t%^%)", NULL);
6853 /* Emit an R_MIPS_NONE relocation to tell the linker what the
6854 target function is. Use a local GOT access when loading the
6855 symbol, to cut down on the number of unnecessary GOT entries
6856 for stubs that aren't needed. */
6857 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol);
6862 /* Load the address of the MIPS16 function into $25. Do this first so
6863 that targets with coprocessor interlocks can use an MFC1 to fill the
6865 output_asm_insn ("la\t%^,%0", &symbol);
6867 /* Move the arguments from floating-point registers to general registers. */
6868 mips_output_args_xfer (crtl->args.info.fp_code, 'f');
6870 /* Jump to the MIPS16 function. */
6871 output_asm_insn ("jr\t%^", NULL);
6873 if (TARGET_ABICALLS_PIC2 && TARGET_ABSOLUTE_ABICALLS)
6874 fprintf (asm_out_file, "\t.option\tpic2\n");
6876 mips_end_function_definition (stubname);
6878 /* If the linker needs to create a dynamic symbol for the target
6879 function, it will associate the symbol with the stub (which,
6880 unlike the target function, follows the proper calling conventions).
6881 It is therefore useful to have a local alias for the target function,
6882 so that it can still be identified as MIPS16 code. As an optimization,
6883 this symbol can also be used for indirect MIPS16 references from
6884 within this file. */
6885 ASM_OUTPUT_DEF (asm_out_file, alias_name, fnname);
6887 switch_to_section (function_section (current_function_decl));
6890 /* The current function is a MIPS16 function that returns a value in an FPR.
6891 Copy the return value from its soft-float to its hard-float location.
6892 libgcc2 has special non-MIPS16 helper functions for each case. */
6895 mips16_copy_fpr_return_value (void)
6897 rtx fn, insn, retval;
6899 machine_mode return_mode;
6902 return_type = DECL_RESULT (current_function_decl);
6903 return_mode = DECL_MODE (return_type);
6905 name = ACONCAT (("__mips16_ret_",
6906 mips16_call_stub_mode_suffix (return_mode),
6908 fn = mips16_stub_function (name);
6910 /* The function takes arguments in $2 (and possibly $3), so calls
6911 to it cannot be lazily bound. */
6912 SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_BIND_NOW;
6914 /* Model the call as something that takes the GPR return value as
6915 argument and returns an "updated" value. */
6916 retval = gen_rtx_REG (return_mode, GP_RETURN);
6917 insn = mips_expand_call (MIPS_CALL_EPILOGUE, retval, fn,
6918 const0_rtx, NULL_RTX, false);
6919 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), retval);
6922 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
6923 RETVAL is the location of the return value, or null if this is
6924 a "call" rather than a "call_value". ARGS_SIZE is the size of the
6925 arguments and FP_CODE is the code built by mips_function_arg;
6926 see the comment before the fp_code field in CUMULATIVE_ARGS for details.
6928 There are three alternatives:
6930 - If a stub was needed, emit the call and return the call insn itself.
6932 - If we can avoid using a stub by redirecting the call, set *FN_PTR
6933 to the new target and return null.
6935 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
6938 A stub is needed for calls to functions that, in normal mode,
6939 receive arguments in FPRs or return values in FPRs. The stub
6940 copies the arguments from their soft-float positions to their
6941 hard-float positions, calls the real function, then copies the
6942 return value from its hard-float position to its soft-float
6945 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
6946 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
6947 automatically redirects the JAL to the stub, otherwise the JAL
6948 continues to call FN directly. */
6951 mips16_build_call_stub (rtx retval, rtx *fn_ptr, rtx args_size, int fp_code)
6955 struct mips16_stub *l;
6959 /* We don't need to do anything if we aren't in MIPS16 mode, or if
6960 we were invoked with the -msoft-float option. */
6961 if (!TARGET_MIPS16 || TARGET_SOFT_FLOAT_ABI)
6964 /* Figure out whether the value might come back in a floating-point
6966 fp_ret_p = retval && mips_return_mode_in_fpr_p (GET_MODE (retval));
6968 /* We don't need to do anything if there were no floating-point
6969 arguments and the value will not be returned in a floating-point
6971 if (fp_code == 0 && !fp_ret_p)
6974 /* We don't need to do anything if this is a call to a special
6975 MIPS16 support function. */
6977 if (mips16_stub_function_p (fn))
6980 /* If we're calling a locally-defined MIPS16 function, we know that
6981 it will return values in both the "soft-float" and "hard-float"
6982 registers. There is no need to use a stub to move the latter
6984 if (fp_code == 0 && mips16_local_function_p (fn))
6987 /* This code will only work for o32 and o64 abis. The other ABI's
6988 require more sophisticated support. */
6989 gcc_assert (TARGET_OLDABI);
6991 /* If we're calling via a function pointer, use one of the magic
6992 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
6993 Each stub expects the function address to arrive in register $2. */
6994 if (GET_CODE (fn) != SYMBOL_REF
6995 || !call_insn_operand (fn, VOIDmode))
7002 /* If this is a locally-defined and locally-binding function,
7003 avoid the stub by calling the local alias directly. */
7004 if (mips16_local_function_p (fn))
7006 *fn_ptr = mips16_local_alias (fn);
7010 /* Create a SYMBOL_REF for the libgcc.a function. */
7012 sprintf (buf, "__mips16_call_stub_%s_%d",
7013 mips16_call_stub_mode_suffix (GET_MODE (retval)),
7016 sprintf (buf, "__mips16_call_stub_%d", fp_code);
7017 stub_fn = mips16_stub_function (buf);
7019 /* The function uses $2 as an argument, so calls to it
7020 cannot be lazily bound. */
7021 SYMBOL_REF_FLAGS (stub_fn) |= SYMBOL_FLAG_BIND_NOW;
7023 /* Load the target function into $2. */
7024 addr = gen_rtx_REG (Pmode, GP_REG_FIRST + 2);
7025 lazy_p = mips_load_call_address (MIPS_CALL_NORMAL, addr, fn);
7027 /* Emit the call. */
7028 insn = mips_expand_call (MIPS_CALL_NORMAL, retval, stub_fn,
7029 args_size, NULL_RTX, lazy_p);
7031 /* Tell GCC that this call does indeed use the value of $2. */
7032 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), addr);
7034 /* If we are handling a floating-point return value, we need to
7035 save $18 in the function prologue. Putting a note on the
7036 call will mean that df_regs_ever_live_p ($18) will be true if the
7037 call is not eliminated, and we can check that in the prologue
7040 CALL_INSN_FUNCTION_USAGE (insn) =
7041 gen_rtx_EXPR_LIST (VOIDmode,
7042 gen_rtx_CLOBBER (VOIDmode,
7043 gen_rtx_REG (word_mode, 18)),
7044 CALL_INSN_FUNCTION_USAGE (insn));
7049 /* We know the function we are going to call. If we have already
7050 built a stub, we don't need to do anything further. */
7051 fnname = targetm.strip_name_encoding (XSTR (fn, 0));
7052 for (l = mips16_stubs; l != NULL; l = l->next)
7053 if (strcmp (l->name, fnname) == 0)
7058 const char *separator;
7059 char *secname, *stubname;
7060 tree stubid, stubdecl;
7063 /* If the function does not return in FPRs, the special stub
7067 If the function does return in FPRs, the stub section is named
7068 .mips16.call.fp.FNNAME
7070 Build a decl for the stub. */
7071 secname = ACONCAT ((".mips16.call.", fp_ret_p ? "fp." : "",
7073 stubname = ACONCAT (("__call_stub_", fp_ret_p ? "fp_" : "",
7075 stubid = get_identifier (stubname);
7076 stubdecl = build_decl (BUILTINS_LOCATION,
7077 FUNCTION_DECL, stubid,
7078 build_function_type_list (void_type_node,
7080 set_decl_section_name (stubdecl, secname);
7081 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
7082 RESULT_DECL, NULL_TREE,
7085 /* Output a comment. */
7086 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
7088 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
7092 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
7094 fprintf (asm_out_file, "%s%s", separator,
7095 (f & 3) == 1 ? "float" : "double");
7098 fprintf (asm_out_file, ")\n");
7100 /* Start the function definition. */
7101 assemble_start_function (stubdecl, stubname);
7102 mips_start_function_definition (stubname, false);
7106 fprintf (asm_out_file, "\t.cfi_startproc\n");
7108 /* Create a fake CFA 4 bytes below the stack pointer.
7109 This works around unwinders (like libgcc's) that expect
7110 the CFA for non-signal frames to be unique. */
7111 fprintf (asm_out_file, "\t.cfi_def_cfa 29,-4\n");
7113 /* "Save" $sp in itself so we don't use the fake CFA.
7114 This is: DW_CFA_val_expression r29, { DW_OP_reg29 }. */
7115 fprintf (asm_out_file, "\t.cfi_escape 0x16,29,1,0x6d\n");
7117 /* Save the return address in $18. The stub's caller knows
7118 that $18 might be clobbered, even though $18 is usually
7119 a call-saved register.
7121 Do it early on in case the last move to a floating-point
7122 register can be scheduled into the delay slot of the
7123 call we are about to make. */
7124 fprintf (asm_out_file, "\tmove\t%s,%s\n",
7125 reg_names[GP_REG_FIRST + 18],
7126 reg_names[RETURN_ADDR_REGNUM]);
7130 /* Load the address of the MIPS16 function into $25. Do this
7131 first so that targets with coprocessor interlocks can use
7132 an MFC1 to fill the delay slot. */
7133 if (TARGET_EXPLICIT_RELOCS)
7135 output_asm_insn ("lui\t%^,%%hi(%0)", &fn);
7136 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn);
7139 output_asm_insn ("la\t%^,%0", &fn);
7142 /* Move the arguments from general registers to floating-point
7144 mips_output_args_xfer (fp_code, 't');
7148 /* Now call the non-MIPS16 function. */
7149 output_asm_insn (mips_output_jump (&fn, 0, -1, true), &fn);
7150 fprintf (asm_out_file, "\t.cfi_register 31,18\n");
7152 /* Move the result from floating-point registers to
7153 general registers. */
7154 switch (GET_MODE (retval))
7157 mips_output_32bit_xfer ('f', GP_RETURN + TARGET_BIG_ENDIAN,
7161 mips_output_32bit_xfer ('f', GP_RETURN + TARGET_LITTLE_ENDIAN,
7162 TARGET_LITTLE_ENDIAN
7165 if (GET_MODE (retval) == SCmode && TARGET_64BIT)
7167 /* On 64-bit targets, complex floats are returned in
7168 a single GPR, such that "sd" on a suitably-aligned
7169 target would store the value correctly. */
7170 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
7171 reg_names[GP_RETURN + TARGET_BIG_ENDIAN],
7172 reg_names[GP_RETURN + TARGET_BIG_ENDIAN]);
7173 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
7174 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN],
7175 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN]);
7176 fprintf (asm_out_file, "\tdsrl\t%s,%s,32\n",
7177 reg_names[GP_RETURN + TARGET_BIG_ENDIAN],
7178 reg_names[GP_RETURN + TARGET_BIG_ENDIAN]);
7179 fprintf (asm_out_file, "\tor\t%s,%s,%s\n",
7180 reg_names[GP_RETURN],
7181 reg_names[GP_RETURN],
7182 reg_names[GP_RETURN + 1]);
7187 mips_output_32bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
7191 mips_output_64bit_xfer ('f', GP_RETURN + (8 / UNITS_PER_WORD),
7196 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT
7197 || GET_MODE (retval) != V2SFmode);
7198 mips_output_64bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
7204 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 18]);
7205 fprintf (asm_out_file, "\t.cfi_endproc\n");
7209 /* Jump to the previously-loaded address. */
7210 output_asm_insn ("jr\t%^", NULL);
7213 #ifdef ASM_DECLARE_FUNCTION_SIZE
7214 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
7217 mips_end_function_definition (stubname);
7219 /* Record this stub. */
7220 l = XNEW (struct mips16_stub);
7221 l->name = xstrdup (fnname);
7222 l->fp_ret_p = fp_ret_p;
7223 l->next = mips16_stubs;
7227 /* If we expect a floating-point return value, but we've built a
7228 stub which does not expect one, then we're in trouble. We can't
7229 use the existing stub, because it won't handle the floating-point
7230 value. We can't build a new stub, because the linker won't know
7231 which stub to use for the various calls in this object file.
7232 Fortunately, this case is illegal, since it means that a function
7233 was declared in two different ways in a single compilation. */
7234 if (fp_ret_p && !l->fp_ret_p)
7235 error ("cannot handle inconsistent calls to %qs", fnname);
7237 if (retval == NULL_RTX)
7238 pattern = gen_call_internal_direct (fn, args_size);
7240 pattern = gen_call_value_internal_direct (retval, fn, args_size);
7241 insn = mips_emit_call_insn (pattern, fn, fn, false);
7243 /* If we are calling a stub which handles a floating-point return
7244 value, we need to arrange to save $18 in the prologue. We do this
7245 by marking the function call as using the register. The prologue
7246 will later see that it is used, and emit code to save it. */
7248 CALL_INSN_FUNCTION_USAGE (insn) =
7249 gen_rtx_EXPR_LIST (VOIDmode,
7250 gen_rtx_CLOBBER (VOIDmode,
7251 gen_rtx_REG (word_mode, 18)),
7252 CALL_INSN_FUNCTION_USAGE (insn));
7257 /* Expand a call of type TYPE. RESULT is where the result will go (null
7258 for "call"s and "sibcall"s), ADDR is the address of the function,
7259 ARGS_SIZE is the size of the arguments and AUX is the value passed
7260 to us by mips_function_arg. LAZY_P is true if this call already
7261 involves a lazily-bound function address (such as when calling
7262 functions through a MIPS16 hard-float stub).
7264 Return the call itself. */
7267 mips_expand_call (enum mips_call_type type, rtx result, rtx addr,
7268 rtx args_size, rtx aux, bool lazy_p)
7270 rtx orig_addr, pattern;
7274 fp_code = aux == 0 ? 0 : (int) GET_MODE (aux);
7275 insn = mips16_build_call_stub (result, &addr, args_size, fp_code);
7278 gcc_assert (!lazy_p && type == MIPS_CALL_NORMAL);
7283 if (!call_insn_operand (addr, VOIDmode))
7285 if (type == MIPS_CALL_EPILOGUE)
7286 addr = MIPS_EPILOGUE_TEMP (Pmode);
7288 addr = gen_reg_rtx (Pmode);
7289 lazy_p |= mips_load_call_address (type, addr, orig_addr);
7294 rtx (*fn) (rtx, rtx);
7296 if (type == MIPS_CALL_SIBCALL)
7297 fn = gen_sibcall_internal;
7299 fn = gen_call_internal;
7301 pattern = fn (addr, args_size);
7303 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
7305 /* Handle return values created by mips_return_fpr_pair. */
7306 rtx (*fn) (rtx, rtx, rtx, rtx);
7309 if (type == MIPS_CALL_SIBCALL)
7310 fn = gen_sibcall_value_multiple_internal;
7312 fn = gen_call_value_multiple_internal;
7314 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
7315 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
7316 pattern = fn (reg1, addr, args_size, reg2);
7320 rtx (*fn) (rtx, rtx, rtx);
7322 if (type == MIPS_CALL_SIBCALL)
7323 fn = gen_sibcall_value_internal;
7325 fn = gen_call_value_internal;
7327 /* Handle return values created by mips_return_fpr_single. */
7328 if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 1)
7329 result = XEXP (XVECEXP (result, 0, 0), 0);
7330 pattern = fn (result, addr, args_size);
7333 return mips_emit_call_insn (pattern, orig_addr, addr, lazy_p);
7336 /* Split call instruction INSN into a $gp-clobbering call and
7337 (where necessary) an instruction to restore $gp from its save slot.
7338 CALL_PATTERN is the pattern of the new call. */
7341 mips_split_call (rtx insn, rtx call_pattern)
7343 emit_call_insn (call_pattern);
7344 if (!find_reg_note (insn, REG_NORETURN, 0))
7345 mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode,
7346 POST_CALL_TMP_REG));
7349 /* Return true if a call to DECL may need to use JALX. */
7352 mips_call_may_need_jalx_p (tree decl)
7354 /* If the current translation unit would use a different mode for DECL,
7355 assume that the call needs JALX. */
7356 if (mips_get_compress_mode (decl) != TARGET_COMPRESSION)
7359 /* mips_get_compress_mode is always accurate for locally-binding
7360 functions in the current translation unit. */
7361 if (!DECL_EXTERNAL (decl) && targetm.binds_local_p (decl))
7364 /* When -minterlink-compressed is in effect, assume that functions
7365 could use a different encoding mode unless an attribute explicitly
7366 tells us otherwise. */
7367 if (TARGET_INTERLINK_COMPRESSED)
7369 if (!TARGET_COMPRESSION
7370 && mips_get_compress_off_flags (DECL_ATTRIBUTES (decl)) ==0)
7372 if (TARGET_COMPRESSION
7373 && mips_get_compress_on_flags (DECL_ATTRIBUTES (decl)) == 0)
7380 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
7383 mips_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
7385 if (!TARGET_SIBCALLS)
7388 /* Interrupt handlers need special epilogue code and therefore can't
7390 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
7393 /* Direct Js are only possible to functions that use the same ISA encoding.
7394 There is no JX counterpoart of JALX. */
7396 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode)
7397 && mips_call_may_need_jalx_p (decl))
7400 /* Sibling calls should not prevent lazy binding. Lazy-binding stubs
7401 require $gp to be valid on entry, so sibcalls can only use stubs
7402 if $gp is call-clobbered. */
7404 && TARGET_CALL_SAVED_GP
7405 && !TARGET_ABICALLS_PIC0
7406 && !targetm.binds_local_p (decl))
7413 /* Implement TARGET_USE_MOVE_BY_PIECES_INFRASTRUCTURE_P. */
7416 mips_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT size,
7418 enum by_pieces_operation op,
7421 if (op == STORE_BY_PIECES)
7422 return mips_store_by_pieces_p (size, align);
7423 if (op == MOVE_BY_PIECES && HAVE_movmemsi)
7425 /* movmemsi is meant to generate code that is at least as good as
7426 move_by_pieces. However, movmemsi effectively uses a by-pieces
7427 implementation both for moves smaller than a word and for
7428 word-aligned moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT
7429 bytes. We should allow the tree-level optimisers to do such
7430 moves by pieces, as it often exposes other optimization
7431 opportunities. We might as well continue to use movmemsi at
7432 the rtl level though, as it produces better code when
7433 scheduling is disabled (such as at -O). */
7434 if (currently_expanding_to_rtl)
7436 if (align < BITS_PER_WORD)
7437 return size < UNITS_PER_WORD;
7438 return size <= MIPS_MAX_MOVE_BYTES_STRAIGHT;
7441 return default_use_by_pieces_infrastructure_p (size, align, op, speed_p);
7444 /* Implement a handler for STORE_BY_PIECES operations
7445 for TARGET_USE_MOVE_BY_PIECES_INFRASTRUCTURE_P. */
7448 mips_store_by_pieces_p (unsigned HOST_WIDE_INT size, unsigned int align)
7450 /* Storing by pieces involves moving constants into registers
7451 of size MIN (ALIGN, BITS_PER_WORD), then storing them.
7452 We need to decide whether it is cheaper to load the address of
7453 constant data into a register and use a block move instead. */
7455 /* If the data is only byte aligned, then:
7457 (a1) A block move of less than 4 bytes would involve three 3 LBs and
7458 3 SBs. We might as well use 3 single-instruction LIs and 3 SBs
7461 (a2) A block move of 4 bytes from aligned source data can use an
7462 LW/SWL/SWR sequence. This is often better than the 4 LIs and
7463 4 SBs that we would generate when storing by pieces. */
7464 if (align <= BITS_PER_UNIT)
7467 /* If the data is 2-byte aligned, then:
7469 (b1) A block move of less than 4 bytes would use a combination of LBs,
7470 LHs, SBs and SHs. We get better code by using single-instruction
7471 LIs, SBs and SHs instead.
7473 (b2) A block move of 4 bytes from aligned source data would again use
7474 an LW/SWL/SWR sequence. In most cases, loading the address of
7475 the source data would require at least one extra instruction.
7476 It is often more efficient to use 2 single-instruction LIs and
7479 (b3) A block move of up to 3 additional bytes would be like (b1).
7481 (b4) A block move of 8 bytes from aligned source data can use two
7482 LW/SWL/SWR sequences or a single LD/SDL/SDR sequence. Both
7483 sequences are better than the 4 LIs and 4 SHs that we'd generate
7484 when storing by pieces.
7486 The reasoning for higher alignments is similar:
7488 (c1) A block move of less than 4 bytes would be the same as (b1).
7490 (c2) A block move of 4 bytes would use an LW/SW sequence. Again,
7491 loading the address of the source data would typically require
7492 at least one extra instruction. It is generally better to use
7495 (c3) A block move of up to 3 additional bytes would be like (b1).
7497 (c4) A block move of 8 bytes can use two LW/SW sequences or a single
7498 LD/SD sequence, and in these cases we've traditionally preferred
7499 the memory copy over the more bulky constant moves. */
7503 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
7504 Assume that the areas do not overlap. */
7507 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
7509 HOST_WIDE_INT offset, delta;
7510 unsigned HOST_WIDE_INT bits;
7515 /* Work out how many bits to move at a time. If both operands have
7516 half-word alignment, it is usually better to move in half words.
7517 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
7518 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
7519 Otherwise move word-sized chunks.
7521 For ISA_HAS_LWL_LWR we rely on the lwl/lwr & swl/swr load. Otherwise
7522 picking the minimum of alignment or BITS_PER_WORD gets us the
7523 desired size for bits. */
7525 if (!ISA_HAS_LWL_LWR)
7526 bits = MIN (BITS_PER_WORD, MIN (MEM_ALIGN (src), MEM_ALIGN (dest)));
7529 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
7530 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
7531 bits = BITS_PER_WORD / 2;
7533 bits = BITS_PER_WORD;
7536 mode = mode_for_size (bits, MODE_INT, 0);
7537 delta = bits / BITS_PER_UNIT;
7539 /* Allocate a buffer for the temporary registers. */
7540 regs = XALLOCAVEC (rtx, length / delta);
7542 /* Load as many BITS-sized chunks as possible. Use a normal load if
7543 the source has enough alignment, otherwise use left/right pairs. */
7544 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
7546 regs[i] = gen_reg_rtx (mode);
7547 if (MEM_ALIGN (src) >= bits)
7548 mips_emit_move (regs[i], adjust_address (src, mode, offset));
7551 rtx part = adjust_address (src, BLKmode, offset);
7552 set_mem_size (part, delta);
7553 if (!mips_expand_ext_as_unaligned_load (regs[i], part, bits, 0, 0))
7558 /* Copy the chunks to the destination. */
7559 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
7560 if (MEM_ALIGN (dest) >= bits)
7561 mips_emit_move (adjust_address (dest, mode, offset), regs[i]);
7564 rtx part = adjust_address (dest, BLKmode, offset);
7565 set_mem_size (part, delta);
7566 if (!mips_expand_ins_as_unaligned_store (part, regs[i], bits, 0))
7570 /* Mop up any left-over bytes. */
7571 if (offset < length)
7573 src = adjust_address (src, BLKmode, offset);
7574 dest = adjust_address (dest, BLKmode, offset);
7575 move_by_pieces (dest, src, length - offset,
7576 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
7580 /* Helper function for doing a loop-based block operation on memory
7581 reference MEM. Each iteration of the loop will operate on LENGTH
7584 Create a new base register for use within the loop and point it to
7585 the start of MEM. Create a new memory reference that uses this
7586 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
7589 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
7590 rtx *loop_reg, rtx *loop_mem)
7592 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
7594 /* Although the new mem does not refer to a known location,
7595 it does keep up to LENGTH bytes of alignment. */
7596 *loop_mem = change_address (mem, BLKmode, *loop_reg);
7597 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
7600 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
7601 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
7602 the memory regions do not overlap. */
7605 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length,
7606 HOST_WIDE_INT bytes_per_iter)
7608 rtx_code_label *label;
7609 rtx src_reg, dest_reg, final_src, test;
7610 HOST_WIDE_INT leftover;
7612 leftover = length % bytes_per_iter;
7615 /* Create registers and memory references for use within the loop. */
7616 mips_adjust_block_mem (src, bytes_per_iter, &src_reg, &src);
7617 mips_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest);
7619 /* Calculate the value that SRC_REG should have after the last iteration
7621 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
7624 /* Emit the start of the loop. */
7625 label = gen_label_rtx ();
7628 /* Emit the loop body. */
7629 mips_block_move_straight (dest, src, bytes_per_iter);
7631 /* Move on to the next block. */
7632 mips_emit_move (src_reg, plus_constant (Pmode, src_reg, bytes_per_iter));
7633 mips_emit_move (dest_reg, plus_constant (Pmode, dest_reg, bytes_per_iter));
7635 /* Emit the loop condition. */
7636 test = gen_rtx_NE (VOIDmode, src_reg, final_src);
7637 if (Pmode == DImode)
7638 emit_jump_insn (gen_cbranchdi4 (test, src_reg, final_src, label));
7640 emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label));
7642 /* Mop up any left-over bytes. */
7644 mips_block_move_straight (dest, src, leftover);
7647 /* Expand a movmemsi instruction, which copies LENGTH bytes from
7648 memory reference SRC to memory reference DEST. */
7651 mips_expand_block_move (rtx dest, rtx src, rtx length)
7653 if (!ISA_HAS_LWL_LWR
7654 && (MEM_ALIGN (src) < MIPS_MIN_MOVE_MEM_ALIGN
7655 || MEM_ALIGN (dest) < MIPS_MIN_MOVE_MEM_ALIGN))
7658 if (CONST_INT_P (length))
7660 if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)
7662 mips_block_move_straight (dest, src, INTVAL (length));
7667 mips_block_move_loop (dest, src, INTVAL (length),
7668 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER);
7675 /* Expand a loop of synci insns for the address range [BEGIN, END). */
7678 mips_expand_synci_loop (rtx begin, rtx end)
7680 rtx inc, cmp_result, mask, length;
7681 rtx_code_label *label, *end_label;
7683 /* Create end_label. */
7684 end_label = gen_label_rtx ();
7686 /* Check if begin equals end. */
7687 cmp_result = gen_rtx_EQ (VOIDmode, begin, end);
7688 emit_jump_insn (gen_condjump (cmp_result, end_label));
7690 /* Load INC with the cache line size (rdhwr INC,$1). */
7691 inc = gen_reg_rtx (Pmode);
7692 emit_insn (PMODE_INSN (gen_rdhwr_synci_step, (inc)));
7694 /* Check if inc is 0. */
7695 cmp_result = gen_rtx_EQ (VOIDmode, inc, const0_rtx);
7696 emit_jump_insn (gen_condjump (cmp_result, end_label));
7698 /* Calculate mask. */
7699 mask = mips_force_unary (Pmode, NEG, inc);
7701 /* Mask out begin by mask. */
7702 begin = mips_force_binary (Pmode, AND, begin, mask);
7704 /* Calculate length. */
7705 length = mips_force_binary (Pmode, MINUS, end, begin);
7707 /* Loop back to here. */
7708 label = gen_label_rtx ();
7711 emit_insn (gen_synci (begin));
7713 /* Update length. */
7714 mips_emit_binary (MINUS, length, length, inc);
7717 mips_emit_binary (PLUS, begin, begin, inc);
7719 /* Check if length is greater than 0. */
7720 cmp_result = gen_rtx_GT (VOIDmode, length, const0_rtx);
7721 emit_jump_insn (gen_condjump (cmp_result, label));
7723 emit_label (end_label);
7726 /* Expand a QI or HI mode atomic memory operation.
7728 GENERATOR contains a pointer to the gen_* function that generates
7729 the SI mode underlying atomic operation using masks that we
7732 RESULT is the return register for the operation. Its value is NULL
7735 MEM is the location of the atomic access.
7737 OLDVAL is the first operand for the operation.
7739 NEWVAL is the optional second operand for the operation. Its value
7740 is NULL if unused. */
7743 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator,
7744 rtx result, rtx mem, rtx oldval, rtx newval)
7746 rtx orig_addr, memsi_addr, memsi, shift, shiftsi, unshifted_mask;
7747 rtx unshifted_mask_reg, mask, inverted_mask, si_op;
7751 mode = GET_MODE (mem);
7753 /* Compute the address of the containing SImode value. */
7754 orig_addr = force_reg (Pmode, XEXP (mem, 0));
7755 memsi_addr = mips_force_binary (Pmode, AND, orig_addr,
7756 force_reg (Pmode, GEN_INT (-4)));
7758 /* Create a memory reference for it. */
7759 memsi = gen_rtx_MEM (SImode, memsi_addr);
7760 set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER);
7761 MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem);
7763 /* Work out the byte offset of the QImode or HImode value,
7764 counting from the least significant byte. */
7765 shift = mips_force_binary (Pmode, AND, orig_addr, GEN_INT (3));
7766 if (TARGET_BIG_ENDIAN)
7767 mips_emit_binary (XOR, shift, shift, GEN_INT (mode == QImode ? 3 : 2));
7769 /* Multiply by eight to convert the shift value from bytes to bits. */
7770 mips_emit_binary (ASHIFT, shift, shift, GEN_INT (3));
7772 /* Make the final shift an SImode value, so that it can be used in
7773 SImode operations. */
7774 shiftsi = force_reg (SImode, gen_lowpart (SImode, shift));
7776 /* Set MASK to an inclusive mask of the QImode or HImode value. */
7777 unshifted_mask = GEN_INT (GET_MODE_MASK (mode));
7778 unshifted_mask_reg = force_reg (SImode, unshifted_mask);
7779 mask = mips_force_binary (SImode, ASHIFT, unshifted_mask_reg, shiftsi);
7781 /* Compute the equivalent exclusive mask. */
7782 inverted_mask = gen_reg_rtx (SImode);
7783 emit_insn (gen_rtx_SET (inverted_mask, gen_rtx_NOT (SImode, mask)));
7785 /* Shift the old value into place. */
7786 if (oldval != const0_rtx)
7788 oldval = convert_modes (SImode, mode, oldval, true);
7789 oldval = force_reg (SImode, oldval);
7790 oldval = mips_force_binary (SImode, ASHIFT, oldval, shiftsi);
7793 /* Do the same for the new value. */
7794 if (newval && newval != const0_rtx)
7796 newval = convert_modes (SImode, mode, newval, true);
7797 newval = force_reg (SImode, newval);
7798 newval = mips_force_binary (SImode, ASHIFT, newval, shiftsi);
7801 /* Do the SImode atomic access. */
7803 res = gen_reg_rtx (SImode);
7805 si_op = generator.fn_6 (res, memsi, mask, inverted_mask, oldval, newval);
7807 si_op = generator.fn_5 (res, memsi, mask, inverted_mask, oldval);
7809 si_op = generator.fn_4 (memsi, mask, inverted_mask, oldval);
7815 /* Shift and convert the result. */
7816 mips_emit_binary (AND, res, res, mask);
7817 mips_emit_binary (LSHIFTRT, res, res, shiftsi);
7818 mips_emit_move (result, gen_lowpart (GET_MODE (result), res));
7822 /* Return true if it is possible to use left/right accesses for a
7823 bitfield of WIDTH bits starting BITPOS bits into BLKmode memory OP.
7824 When returning true, update *LEFT and *RIGHT as follows:
7826 *LEFT is a QImode reference to the first byte if big endian or
7827 the last byte if little endian. This address can be used in the
7828 left-side instructions (LWL, SWL, LDL, SDL).
7830 *RIGHT is a QImode reference to the opposite end of the field and
7831 can be used in the patterning right-side instruction. */
7834 mips_get_unaligned_mem (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos,
7835 rtx *left, rtx *right)
7839 /* Check that the size is valid. */
7840 if (width != 32 && (!TARGET_64BIT || width != 64))
7843 /* We can only access byte-aligned values. Since we are always passed
7844 a reference to the first byte of the field, it is not necessary to
7845 do anything with BITPOS after this check. */
7846 if (bitpos % BITS_PER_UNIT != 0)
7849 /* Reject aligned bitfields: we want to use a normal load or store
7850 instead of a left/right pair. */
7851 if (MEM_ALIGN (op) >= width)
7854 /* Get references to both ends of the field. */
7855 first = adjust_address (op, QImode, 0);
7856 last = adjust_address (op, QImode, width / BITS_PER_UNIT - 1);
7858 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
7859 correspond to the MSB and RIGHT to the LSB. */
7860 if (TARGET_BIG_ENDIAN)
7861 *left = first, *right = last;
7863 *left = last, *right = first;
7868 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
7869 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
7870 the operation is the equivalent of:
7872 (set DEST (*_extract SRC WIDTH BITPOS))
7874 Return true on success. */
7877 mips_expand_ext_as_unaligned_load (rtx dest, rtx src, HOST_WIDE_INT width,
7878 HOST_WIDE_INT bitpos, bool unsigned_p)
7880 rtx left, right, temp;
7881 rtx dest1 = NULL_RTX;
7883 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
7884 be a DImode, create a new temp and emit a zero extend at the end. */
7885 if (GET_MODE (dest) == DImode
7887 && GET_MODE_BITSIZE (SImode) == width)
7890 dest = gen_reg_rtx (SImode);
7893 if (!mips_get_unaligned_mem (src, width, bitpos, &left, &right))
7896 temp = gen_reg_rtx (GET_MODE (dest));
7897 if (GET_MODE (dest) == DImode)
7899 emit_insn (gen_mov_ldl (temp, src, left));
7900 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
7904 emit_insn (gen_mov_lwl (temp, src, left));
7905 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
7908 /* If we were loading 32bits and the original register was DI then
7909 sign/zero extend into the orignal dest. */
7913 emit_insn (gen_zero_extendsidi2 (dest1, dest));
7915 emit_insn (gen_extendsidi2 (dest1, dest));
7920 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
7921 BITPOS and SRC are the operands passed to the expander; the operation
7922 is the equivalent of:
7924 (set (zero_extract DEST WIDTH BITPOS) SRC)
7926 Return true on success. */
7929 mips_expand_ins_as_unaligned_store (rtx dest, rtx src, HOST_WIDE_INT width,
7930 HOST_WIDE_INT bitpos)
7935 if (!mips_get_unaligned_mem (dest, width, bitpos, &left, &right))
7938 mode = mode_for_size (width, MODE_INT, 0);
7939 src = gen_lowpart (mode, src);
7942 emit_insn (gen_mov_sdl (dest, src, left));
7943 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
7947 emit_insn (gen_mov_swl (dest, src, left));
7948 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
7953 /* Return true if X is a MEM with the same size as MODE. */
7956 mips_mem_fits_mode_p (machine_mode mode, rtx x)
7959 && MEM_SIZE_KNOWN_P (x)
7960 && MEM_SIZE (x) == GET_MODE_SIZE (mode));
7963 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
7964 source of an "ext" instruction or the destination of an "ins"
7965 instruction. OP must be a register operand and the following
7966 conditions must hold:
7968 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
7969 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7970 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7972 Also reject lengths equal to a word as they are better handled
7973 by the move patterns. */
7976 mips_use_ins_ext_p (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos)
7978 if (!ISA_HAS_EXT_INS
7979 || !register_operand (op, VOIDmode)
7980 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
7983 if (!IN_RANGE (width, 1, GET_MODE_BITSIZE (GET_MODE (op)) - 1))
7986 if (bitpos < 0 || bitpos + width > GET_MODE_BITSIZE (GET_MODE (op)))
7992 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
7993 operation if MAXLEN is the maxium length of consecutive bits that
7994 can make up MASK. MODE is the mode of the operation. See
7995 mask_low_and_shift_len for the actual definition. */
7998 mask_low_and_shift_p (machine_mode mode, rtx mask, rtx shift, int maxlen)
8000 return IN_RANGE (mask_low_and_shift_len (mode, mask, shift), 1, maxlen);
8003 /* Return true iff OP1 and OP2 are valid operands together for the
8004 *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider,
8005 see the table in the comment before the pattern. */
8008 and_operands_ok (machine_mode mode, rtx op1, rtx op2)
8011 if (memory_operand (op1, mode))
8013 if (TARGET_MIPS16) {
8014 struct mips_address_info addr;
8015 if (!mips_classify_address (&addr, op1, mode, false))
8018 return and_load_operand (op2, mode);
8021 return and_reg_operand (op2, mode);
8024 /* The canonical form of a mask-low-and-shift-left operation is
8025 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
8026 cleared. Thus we need to shift MASK to the right before checking if it
8027 is a valid mask value. MODE is the mode of the operation. If true
8028 return the length of the mask, otherwise return -1. */
8031 mask_low_and_shift_len (machine_mode mode, rtx mask, rtx shift)
8033 HOST_WIDE_INT shval;
8035 shval = INTVAL (shift) & (GET_MODE_BITSIZE (mode) - 1);
8036 return exact_log2 ((UINTVAL (mask) >> shval) + 1);
8039 /* Return true if -msplit-addresses is selected and should be honored.
8041 -msplit-addresses is a half-way house between explicit relocations
8042 and the traditional assembler macros. It can split absolute 32-bit
8043 symbolic constants into a high/lo_sum pair but uses macros for other
8046 Like explicit relocation support for REL targets, it relies
8047 on GNU extensions in the assembler and the linker.
8049 Although this code should work for -O0, it has traditionally
8050 been treated as an optimization. */
8053 mips_split_addresses_p (void)
8055 return (TARGET_SPLIT_ADDRESSES
8059 && !ABI_HAS_64BIT_SYMBOLS);
8062 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
8065 mips_init_relocs (void)
8067 memset (mips_split_p, '\0', sizeof (mips_split_p));
8068 memset (mips_split_hi_p, '\0', sizeof (mips_split_hi_p));
8069 memset (mips_use_pcrel_pool_p, '\0', sizeof (mips_use_pcrel_pool_p));
8070 memset (mips_hi_relocs, '\0', sizeof (mips_hi_relocs));
8071 memset (mips_lo_relocs, '\0', sizeof (mips_lo_relocs));
8073 if (TARGET_MIPS16_PCREL_LOADS)
8074 mips_use_pcrel_pool_p[SYMBOL_ABSOLUTE] = true;
8077 if (ABI_HAS_64BIT_SYMBOLS)
8079 if (TARGET_EXPLICIT_RELOCS)
8081 mips_split_p[SYMBOL_64_HIGH] = true;
8082 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
8083 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
8085 mips_split_p[SYMBOL_64_MID] = true;
8086 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
8087 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
8089 mips_split_p[SYMBOL_64_LOW] = true;
8090 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
8091 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
8093 mips_split_p[SYMBOL_ABSOLUTE] = true;
8094 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
8099 if (TARGET_EXPLICIT_RELOCS
8100 || mips_split_addresses_p ()
8103 mips_split_p[SYMBOL_ABSOLUTE] = true;
8104 mips_hi_relocs[SYMBOL_ABSOLUTE] = "%hi(";
8105 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
8112 /* The high part is provided by a pseudo copy of $gp. */
8113 mips_split_p[SYMBOL_GP_RELATIVE] = true;
8114 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gprel(";
8116 else if (TARGET_EXPLICIT_RELOCS)
8117 /* Small data constants are kept whole until after reload,
8118 then lowered by mips_rewrite_small_data. */
8119 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gp_rel(";
8121 if (TARGET_EXPLICIT_RELOCS)
8123 mips_split_p[SYMBOL_GOT_PAGE_OFST] = true;
8126 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
8127 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%got_ofst(";
8131 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
8132 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%lo(";
8135 /* Expose the use of $28 as soon as possible. */
8136 mips_split_hi_p[SYMBOL_GOT_PAGE_OFST] = true;
8140 /* The HIGH and LO_SUM are matched by special .md patterns. */
8141 mips_split_p[SYMBOL_GOT_DISP] = true;
8143 mips_split_p[SYMBOL_GOTOFF_DISP] = true;
8144 mips_hi_relocs[SYMBOL_GOTOFF_DISP] = "%got_hi(";
8145 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_lo(";
8147 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
8148 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
8149 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
8154 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_disp(";
8156 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got(";
8157 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
8159 /* Expose the use of $28 as soon as possible. */
8160 mips_split_p[SYMBOL_GOT_DISP] = true;
8166 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
8167 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
8168 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
8171 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
8172 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
8174 if (TARGET_MIPS16_PCREL_LOADS)
8176 mips_use_pcrel_pool_p[SYMBOL_DTPREL] = true;
8177 mips_use_pcrel_pool_p[SYMBOL_TPREL] = true;
8181 mips_split_p[SYMBOL_DTPREL] = true;
8182 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
8183 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
8185 mips_split_p[SYMBOL_TPREL] = true;
8186 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
8187 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
8190 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
8191 mips_lo_relocs[SYMBOL_HALF] = "%half(";
8194 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
8195 in context CONTEXT. RELOCS is the array of relocations to use. */
8198 mips_print_operand_reloc (FILE *file, rtx op, enum mips_symbol_context context,
8199 const char **relocs)
8201 enum mips_symbol_type symbol_type;
8204 symbol_type = mips_classify_symbolic_expression (op, context);
8205 gcc_assert (relocs[symbol_type]);
8207 fputs (relocs[symbol_type], file);
8208 output_addr_const (file, mips_strip_unspec_address (op));
8209 for (p = relocs[symbol_type]; *p != 0; p++)
8214 /* Start a new block with the given asm switch enabled. If we need
8215 to print a directive, emit PREFIX before it and SUFFIX after it. */
8218 mips_push_asm_switch_1 (struct mips_asm_switch *asm_switch,
8219 const char *prefix, const char *suffix)
8221 if (asm_switch->nesting_level == 0)
8222 fprintf (asm_out_file, "%s.set\tno%s%s", prefix, asm_switch->name, suffix);
8223 asm_switch->nesting_level++;
8226 /* Likewise, but end a block. */
8229 mips_pop_asm_switch_1 (struct mips_asm_switch *asm_switch,
8230 const char *prefix, const char *suffix)
8232 gcc_assert (asm_switch->nesting_level);
8233 asm_switch->nesting_level--;
8234 if (asm_switch->nesting_level == 0)
8235 fprintf (asm_out_file, "%s.set\t%s%s", prefix, asm_switch->name, suffix);
8238 /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1
8239 that either print a complete line or print nothing. */
8242 mips_push_asm_switch (struct mips_asm_switch *asm_switch)
8244 mips_push_asm_switch_1 (asm_switch, "\t", "\n");
8248 mips_pop_asm_switch (struct mips_asm_switch *asm_switch)
8250 mips_pop_asm_switch_1 (asm_switch, "\t", "\n");
8253 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
8254 The punctuation characters are:
8256 '(' Start a nested ".set noreorder" block.
8257 ')' End a nested ".set noreorder" block.
8258 '[' Start a nested ".set noat" block.
8259 ']' End a nested ".set noat" block.
8260 '<' Start a nested ".set nomacro" block.
8261 '>' End a nested ".set nomacro" block.
8262 '*' Behave like %(%< if generating a delayed-branch sequence.
8263 '#' Print a nop if in a ".set noreorder" block.
8264 '/' Like '#', but do nothing within a delayed-branch sequence.
8265 '?' Print "l" if mips_branch_likely is true
8266 '~' Print a nop if mips_branch_likely is true
8267 '.' Print the name of the register with a hard-wired zero (zero or $0).
8268 '@' Print the name of the assembler temporary register (at or $1).
8269 '^' Print the name of the pic call-through register (t9 or $25).
8270 '+' Print the name of the gp register (usually gp or $28).
8271 '$' Print the name of the stack pointer register (sp or $29).
8272 ':' Print "c" to use the compact version if the delay slot is a nop.
8273 '!' Print "s" to use the short version if the delay slot contains a
8276 See also mips_init_print_operand_punct. */
8279 mips_print_operand_punctuation (FILE *file, int ch)
8284 mips_push_asm_switch_1 (&mips_noreorder, "", "\n\t");
8288 mips_pop_asm_switch_1 (&mips_noreorder, "\n\t", "");
8292 mips_push_asm_switch_1 (&mips_noat, "", "\n\t");
8296 mips_pop_asm_switch_1 (&mips_noat, "\n\t", "");
8300 mips_push_asm_switch_1 (&mips_nomacro, "", "\n\t");
8304 mips_pop_asm_switch_1 (&mips_nomacro, "\n\t", "");
8308 if (final_sequence != 0)
8310 mips_print_operand_punctuation (file, '(');
8311 mips_print_operand_punctuation (file, '<');
8316 if (mips_noreorder.nesting_level > 0)
8317 fputs ("\n\tnop", file);
8321 /* Print an extra newline so that the delayed insn is separated
8322 from the following ones. This looks neater and is consistent
8323 with non-nop delayed sequences. */
8324 if (mips_noreorder.nesting_level > 0 && final_sequence == 0)
8325 fputs ("\n\tnop\n", file);
8329 if (mips_branch_likely)
8334 if (mips_branch_likely)
8335 fputs ("\n\tnop", file);
8339 fputs (reg_names[GP_REG_FIRST + 0], file);
8343 fputs (reg_names[AT_REGNUM], file);
8347 fputs (reg_names[PIC_FUNCTION_ADDR_REGNUM], file);
8351 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
8355 fputs (reg_names[STACK_POINTER_REGNUM], file);
8359 /* When final_sequence is 0, the delay slot will be a nop. We can
8360 use the compact version where available. The %: formatter will
8361 only be present if a compact form of the branch is available. */
8362 if (final_sequence == 0)
8367 /* If the delay slot instruction is short, then use the
8369 if (TARGET_MICROMIPS && !TARGET_INTERLINK_COMPRESSED && mips_isa_rev <= 5
8370 && (final_sequence == 0
8371 || get_attr_length (final_sequence->insn (1)) == 2))
8381 /* Initialize mips_print_operand_punct. */
8384 mips_init_print_operand_punct (void)
8388 for (p = "()[]<>*#/?~.@^+$:!"; *p; p++)
8389 mips_print_operand_punct[(unsigned char) *p] = true;
8392 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
8393 associated with condition CODE. Print the condition part of the
8397 mips_print_int_branch_condition (FILE *file, enum rtx_code code, int letter)
8411 /* Conveniently, the MIPS names for these conditions are the same
8412 as their RTL equivalents. */
8413 fputs (GET_RTX_NAME (code), file);
8417 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
8422 /* Likewise floating-point branches. */
8425 mips_print_float_branch_condition (FILE *file, enum rtx_code code, int letter)
8431 fputs ("c1eqz", file);
8433 fputs ("c1f", file);
8438 fputs ("c1nez", file);
8440 fputs ("c1t", file);
8444 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
8449 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
8452 mips_print_operand_punct_valid_p (unsigned char code)
8454 return mips_print_operand_punct[code];
8457 /* Implement TARGET_PRINT_OPERAND. The MIPS-specific operand codes are:
8459 'X' Print CONST_INT OP in hexadecimal format.
8460 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
8461 'd' Print CONST_INT OP in decimal.
8462 'm' Print one less than CONST_INT OP in decimal.
8463 'h' Print the high-part relocation associated with OP, after stripping
8465 'R' Print the low-part relocation associated with OP.
8466 'C' Print the integer branch condition for comparison OP.
8467 'N' Print the inverse of the integer branch condition for comparison OP.
8468 'F' Print the FPU branch condition for comparison OP.
8469 'W' Print the inverse of the FPU branch condition for comparison OP.
8470 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
8471 'z' for (eq:?I ...), 'n' for (ne:?I ...).
8472 't' Like 'T', but with the EQ/NE cases reversed
8473 'Y' Print mips_fp_conditions[INTVAL (OP)]
8474 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
8475 'q' Print a DSP accumulator register.
8476 'D' Print the second part of a double-word register or memory operand.
8477 'L' Print the low-order register in a double-word register operand.
8478 'M' Print high-order register in a double-word register operand.
8479 'z' Print $0 if OP is zero, otherwise print OP normally.
8480 'b' Print the address of a memory operand, without offset. */
8483 mips_print_operand (FILE *file, rtx op, int letter)
8487 if (mips_print_operand_punct_valid_p (letter))
8489 mips_print_operand_punctuation (file, letter);
8494 code = GET_CODE (op);
8499 if (CONST_INT_P (op))
8500 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
8502 output_operand_lossage ("invalid use of '%%%c'", letter);
8506 if (CONST_INT_P (op))
8507 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op) & 0xffff);
8509 output_operand_lossage ("invalid use of '%%%c'", letter);
8513 if (CONST_INT_P (op))
8514 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op));
8516 output_operand_lossage ("invalid use of '%%%c'", letter);
8520 if (CONST_INT_P (op))
8521 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op) - 1);
8523 output_operand_lossage ("invalid use of '%%%c'", letter);
8529 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_hi_relocs);
8533 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_lo_relocs);
8537 mips_print_int_branch_condition (file, code, letter);
8541 mips_print_int_branch_condition (file, reverse_condition (code), letter);
8545 mips_print_float_branch_condition (file, code, letter);
8549 mips_print_float_branch_condition (file, reverse_condition (code),
8556 int truth = (code == NE) == (letter == 'T');
8557 fputc ("zfnt"[truth * 2 + ST_REG_P (REGNO (XEXP (op, 0)))], file);
8562 if (code == CONST_INT && UINTVAL (op) < ARRAY_SIZE (mips_fp_conditions))
8563 fputs (mips_fp_conditions[UINTVAL (op)], file);
8565 output_operand_lossage ("'%%%c' is not a valid operand prefix",
8570 if (ISA_HAS_8CC || ISA_HAS_CCF)
8572 mips_print_operand (file, op, 0);
8578 if (code == REG && MD_REG_P (REGNO (op)))
8579 fprintf (file, "$ac0");
8580 else if (code == REG && DSP_ACC_REG_P (REGNO (op)))
8581 fprintf (file, "$ac%c", reg_names[REGNO (op)][3]);
8583 output_operand_lossage ("invalid use of '%%%c'", letter);
8591 unsigned int regno = REGNO (op);
8592 if ((letter == 'M' && TARGET_LITTLE_ENDIAN)
8593 || (letter == 'L' && TARGET_BIG_ENDIAN)
8596 else if (letter && letter != 'z' && letter != 'M' && letter != 'L')
8597 output_operand_lossage ("invalid use of '%%%c'", letter);
8598 /* We need to print $0 .. $31 for COP0 registers. */
8599 if (COP0_REG_P (regno))
8600 fprintf (file, "$%s", ®_names[regno][4]);
8602 fprintf (file, "%s", reg_names[regno]);
8608 output_address (GET_MODE (op), plus_constant (Pmode,
8610 else if (letter == 'b')
8612 gcc_assert (REG_P (XEXP (op, 0)));
8613 mips_print_operand (file, XEXP (op, 0), 0);
8615 else if (letter && letter != 'z')
8616 output_operand_lossage ("invalid use of '%%%c'", letter);
8618 output_address (GET_MODE (op), XEXP (op, 0));
8622 if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
8623 fputs (reg_names[GP_REG_FIRST], file);
8624 else if (letter && letter != 'z')
8625 output_operand_lossage ("invalid use of '%%%c'", letter);
8626 else if (CONST_GP_P (op))
8627 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
8629 output_addr_const (file, mips_strip_unspec_address (op));
8635 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
8638 mips_print_operand_address (FILE *file, machine_mode /*mode*/, rtx x)
8640 struct mips_address_info addr;
8642 if (mips_classify_address (&addr, x, word_mode, true))
8646 mips_print_operand (file, addr.offset, 0);
8647 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
8650 case ADDRESS_LO_SUM:
8651 mips_print_operand_reloc (file, addr.offset, SYMBOL_CONTEXT_MEM,
8653 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
8656 case ADDRESS_CONST_INT:
8657 output_addr_const (file, x);
8658 fprintf (file, "(%s)", reg_names[GP_REG_FIRST]);
8661 case ADDRESS_SYMBOLIC:
8662 output_addr_const (file, mips_strip_unspec_address (x));
8668 /* Implement TARGET_ENCODE_SECTION_INFO. */
8671 mips_encode_section_info (tree decl, rtx rtl, int first)
8673 default_encode_section_info (decl, rtl, first);
8675 if (TREE_CODE (decl) == FUNCTION_DECL)
8677 rtx symbol = XEXP (rtl, 0);
8678 tree type = TREE_TYPE (decl);
8680 /* Encode whether the symbol is short or long. */
8681 if ((TARGET_LONG_CALLS && !mips_near_type_p (type))
8682 || mips_far_type_p (type))
8683 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
8687 /* Implement TARGET_SELECT_RTX_SECTION. */
8690 mips_select_rtx_section (machine_mode mode, rtx x,
8691 unsigned HOST_WIDE_INT align)
8693 /* ??? Consider using mergeable small data sections. */
8694 if (mips_rtx_constant_in_small_data_p (mode))
8695 return get_named_section (NULL, ".sdata", 0);
8697 return default_elf_select_rtx_section (mode, x, align);
8700 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
8702 The complication here is that, with the combination TARGET_ABICALLS
8703 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
8704 absolute addresses, and should therefore not be included in the
8705 read-only part of a DSO. Handle such cases by selecting a normal
8706 data section instead of a read-only one. The logic apes that in
8707 default_function_rodata_section. */
8710 mips_function_rodata_section (tree decl)
8712 if (!TARGET_ABICALLS || TARGET_ABSOLUTE_ABICALLS || TARGET_GPWORD)
8713 return default_function_rodata_section (decl);
8715 if (decl && DECL_SECTION_NAME (decl))
8717 const char *name = DECL_SECTION_NAME (decl);
8718 if (DECL_COMDAT_GROUP (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
8720 char *rname = ASTRDUP (name);
8722 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
8724 else if (flag_function_sections
8725 && flag_data_sections
8726 && strncmp (name, ".text.", 6) == 0)
8728 char *rname = ASTRDUP (name);
8729 memcpy (rname + 1, "data", 4);
8730 return get_section (rname, SECTION_WRITE, decl);
8733 return data_section;
8736 /* Implement TARGET_IN_SMALL_DATA_P. */
8739 mips_in_small_data_p (const_tree decl)
8741 unsigned HOST_WIDE_INT size;
8743 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
8746 /* We don't yet generate small-data references for -mabicalls
8747 or VxWorks RTP code. See the related -G handling in
8748 mips_option_override. */
8749 if (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
8752 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
8756 /* Reject anything that isn't in a known small-data section. */
8757 name = DECL_SECTION_NAME (decl);
8758 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
8761 /* If a symbol is defined externally, the assembler will use the
8762 usual -G rules when deciding how to implement macros. */
8763 if (mips_lo_relocs[SYMBOL_GP_RELATIVE] || !DECL_EXTERNAL (decl))
8766 else if (TARGET_EMBEDDED_DATA)
8768 /* Don't put constants into the small data section: we want them
8769 to be in ROM rather than RAM. */
8770 if (TREE_CODE (decl) != VAR_DECL)
8773 if (TREE_READONLY (decl)
8774 && !TREE_SIDE_EFFECTS (decl)
8775 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
8779 /* Enforce -mlocal-sdata. */
8780 if (!TARGET_LOCAL_SDATA && !TREE_PUBLIC (decl))
8783 /* Enforce -mextern-sdata. */
8784 if (!TARGET_EXTERN_SDATA && DECL_P (decl))
8786 if (DECL_EXTERNAL (decl))
8788 if (DECL_COMMON (decl) && DECL_INITIAL (decl) == NULL)
8792 /* We have traditionally not treated zero-sized objects as small data,
8793 so this is now effectively part of the ABI. */
8794 size = int_size_in_bytes (TREE_TYPE (decl));
8795 return size > 0 && size <= mips_small_data_threshold;
8798 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
8799 anchors for small data: the GP register acts as an anchor in that
8800 case. We also don't want to use them for PC-relative accesses,
8801 where the PC acts as an anchor. */
8804 mips_use_anchors_for_symbol_p (const_rtx symbol)
8806 switch (mips_classify_symbol (symbol, SYMBOL_CONTEXT_MEM))
8808 case SYMBOL_PC_RELATIVE:
8809 case SYMBOL_GP_RELATIVE:
8813 return default_use_anchors_for_symbol_p (symbol);
8817 /* The MIPS debug format wants all automatic variables and arguments
8818 to be in terms of the virtual frame pointer (stack pointer before
8819 any adjustment in the function), while the MIPS 3.0 linker wants
8820 the frame pointer to be the stack pointer after the initial
8821 adjustment. So, we do the adjustment here. The arg pointer (which
8822 is eliminated) points to the virtual frame pointer, while the frame
8823 pointer (which may be eliminated) points to the stack pointer after
8824 the initial adjustments. */
8827 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
8829 rtx offset2 = const0_rtx;
8830 rtx reg = eliminate_constant_term (addr, &offset2);
8833 offset = INTVAL (offset2);
8835 if (reg == stack_pointer_rtx
8836 || reg == frame_pointer_rtx
8837 || reg == hard_frame_pointer_rtx)
8839 offset -= cfun->machine->frame.total_size;
8840 if (reg == hard_frame_pointer_rtx)
8841 offset += cfun->machine->frame.hard_frame_pointer_offset;
8847 /* Implement ASM_OUTPUT_EXTERNAL. */
8850 mips_output_external (FILE *file, tree decl, const char *name)
8852 default_elf_asm_output_external (file, decl, name);
8854 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
8855 set in order to avoid putting out names that are never really
8857 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
8859 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
8861 /* When using assembler macros, emit .extern directives for
8862 all small-data externs so that the assembler knows how
8865 In most cases it would be safe (though pointless) to emit
8866 .externs for other symbols too. One exception is when an
8867 object is within the -G limit but declared by the user to
8868 be in a section other than .sbss or .sdata. */
8869 fputs ("\t.extern\t", file);
8870 assemble_name (file, name);
8871 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n",
8872 int_size_in_bytes (TREE_TYPE (decl)));
8877 /* Implement TARGET_ASM_OUTPUT_SOURCE_FILENAME. */
8880 mips_output_filename (FILE *stream, const char *name)
8882 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
8884 if (write_symbols == DWARF2_DEBUG)
8886 else if (mips_output_filename_first_time)
8888 mips_output_filename_first_time = 0;
8889 num_source_filenames += 1;
8890 current_function_file = name;
8891 fprintf (stream, "\t.file\t%d ", num_source_filenames);
8892 output_quoted_string (stream, name);
8893 putc ('\n', stream);
8895 /* If we are emitting stabs, let dbxout.c handle this (except for
8896 the mips_output_filename_first_time case). */
8897 else if (write_symbols == DBX_DEBUG)
8899 else if (name != current_function_file
8900 && strcmp (name, current_function_file) != 0)
8902 num_source_filenames += 1;
8903 current_function_file = name;
8904 fprintf (stream, "\t.file\t%d ", num_source_filenames);
8905 output_quoted_string (stream, name);
8906 putc ('\n', stream);
8910 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
8912 static void ATTRIBUTE_UNUSED
8913 mips_output_dwarf_dtprel (FILE *file, int size, rtx x)
8918 fputs ("\t.dtprelword\t", file);
8922 fputs ("\t.dtpreldword\t", file);
8928 output_addr_const (file, x);
8929 fputs ("+0x8000", file);
8932 /* Implement TARGET_DWARF_REGISTER_SPAN. */
8935 mips_dwarf_register_span (rtx reg)
8940 /* TARGET_FLOATXX is implemented as 32-bit floating-point registers but
8941 ensures that double-precision registers are treated as if they were
8942 64-bit physical registers. The code will run correctly with 32-bit or
8943 64-bit registers which means that dwarf information cannot be precise
8944 for all scenarios. We choose to state that the 64-bit values are stored
8945 in a single 64-bit 'piece'. This slightly unusual construct can then be
8946 interpreted as either a pair of registers if the registers are 32-bit or
8947 a single 64-bit register depending on hardware. */
8948 mode = GET_MODE (reg);
8949 if (FP_REG_P (REGNO (reg))
8951 && GET_MODE_SIZE (mode) > UNITS_PER_FPREG)
8953 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, reg));
8955 /* By default, GCC maps increasing register numbers to increasing
8956 memory locations, but paired FPRs are always little-endian,
8957 regardless of the prevailing endianness. */
8958 else if (FP_REG_P (REGNO (reg))
8959 && TARGET_BIG_ENDIAN
8960 && MAX_FPRS_PER_FMT > 1
8961 && GET_MODE_SIZE (mode) > UNITS_PER_FPREG)
8963 gcc_assert (GET_MODE_SIZE (mode) == UNITS_PER_HWFPVALUE);
8964 high = mips_subword (reg, true);
8965 low = mips_subword (reg, false);
8966 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, high, low));
8972 /* Implement TARGET_DWARF_FRAME_REG_MODE. */
8975 mips_dwarf_frame_reg_mode (int regno)
8977 machine_mode mode = default_dwarf_frame_reg_mode (regno);
8979 if (FP_REG_P (regno) && mips_abi == ABI_32 && TARGET_FLOAT64)
8985 /* DSP ALU can bypass data with no delays for the following pairs. */
8986 enum insn_code dspalu_bypass_table[][2] =
8988 {CODE_FOR_mips_addsc, CODE_FOR_mips_addwc},
8989 {CODE_FOR_mips_cmpu_eq_qb, CODE_FOR_mips_pick_qb},
8990 {CODE_FOR_mips_cmpu_lt_qb, CODE_FOR_mips_pick_qb},
8991 {CODE_FOR_mips_cmpu_le_qb, CODE_FOR_mips_pick_qb},
8992 {CODE_FOR_mips_cmp_eq_ph, CODE_FOR_mips_pick_ph},
8993 {CODE_FOR_mips_cmp_lt_ph, CODE_FOR_mips_pick_ph},
8994 {CODE_FOR_mips_cmp_le_ph, CODE_FOR_mips_pick_ph},
8995 {CODE_FOR_mips_wrdsp, CODE_FOR_mips_insv}
8999 mips_dspalu_bypass_p (rtx out_insn, rtx in_insn)
9002 int num_bypass = ARRAY_SIZE (dspalu_bypass_table);
9003 enum insn_code out_icode = (enum insn_code) INSN_CODE (out_insn);
9004 enum insn_code in_icode = (enum insn_code) INSN_CODE (in_insn);
9006 for (i = 0; i < num_bypass; i++)
9008 if (out_icode == dspalu_bypass_table[i][0]
9009 && in_icode == dspalu_bypass_table[i][1])
9015 /* Implement ASM_OUTPUT_ASCII. */
9018 mips_output_ascii (FILE *stream, const char *string, size_t len)
9024 fprintf (stream, "\t.ascii\t\"");
9025 for (i = 0; i < len; i++)
9029 c = (unsigned char) string[i];
9032 if (c == '\\' || c == '\"')
9034 putc ('\\', stream);
9042 fprintf (stream, "\\%03o", c);
9046 if (cur_pos > 72 && i+1 < len)
9049 fprintf (stream, "\"\n\t.ascii\t\"");
9052 fprintf (stream, "\"\n");
9055 /* Return the pseudo-op for full SYMBOL_(D)TPREL address *ADDR.
9056 Update *ADDR with the operand that should be printed. */
9059 mips_output_tls_reloc_directive (rtx *addr)
9061 enum mips_symbol_type type;
9063 type = mips_classify_symbolic_expression (*addr, SYMBOL_CONTEXT_LEA);
9064 *addr = mips_strip_unspec_address (*addr);
9068 return Pmode == SImode ? ".dtprelword\t%0" : ".dtpreldword\t%0";
9071 return Pmode == SImode ? ".tprelword\t%0" : ".tpreldword\t%0";
9078 /* Emit either a label, .comm, or .lcomm directive. When using assembler
9079 macros, mark the symbol as written so that mips_asm_output_external
9080 won't emit an .extern for it. STREAM is the output file, NAME is the
9081 name of the symbol, INIT_STRING is the string that should be written
9082 before the symbol and FINAL_STRING is the string that should be
9083 written after it. FINAL_STRING is a printf format that consumes the
9084 remaining arguments. */
9087 mips_declare_object (FILE *stream, const char *name, const char *init_string,
9088 const char *final_string, ...)
9092 fputs (init_string, stream);
9093 assemble_name (stream, name);
9094 va_start (ap, final_string);
9095 vfprintf (stream, final_string, ap);
9098 if (!TARGET_EXPLICIT_RELOCS)
9100 tree name_tree = get_identifier (name);
9101 TREE_ASM_WRITTEN (name_tree) = 1;
9105 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
9106 NAME is the name of the object and ALIGN is the required alignment
9107 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
9108 alignment argument. */
9111 mips_declare_common_object (FILE *stream, const char *name,
9112 const char *init_string,
9113 unsigned HOST_WIDE_INT size,
9114 unsigned int align, bool takes_alignment_p)
9116 if (!takes_alignment_p)
9118 size += (align / BITS_PER_UNIT) - 1;
9119 size -= size % (align / BITS_PER_UNIT);
9120 mips_declare_object (stream, name, init_string,
9121 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
9124 mips_declare_object (stream, name, init_string,
9125 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
9126 size, align / BITS_PER_UNIT);
9129 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
9130 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
9133 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
9134 unsigned HOST_WIDE_INT size,
9137 /* If the target wants uninitialized const declarations in
9138 .rdata then don't put them in .comm. */
9139 if (TARGET_EMBEDDED_DATA
9140 && TARGET_UNINIT_CONST_IN_RODATA
9141 && TREE_CODE (decl) == VAR_DECL
9142 && TREE_READONLY (decl)
9143 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
9145 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
9146 targetm.asm_out.globalize_label (stream, name);
9148 switch_to_section (readonly_data_section);
9149 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
9150 mips_declare_object (stream, name, "",
9151 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
9155 mips_declare_common_object (stream, name, "\n\t.comm\t",
9159 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
9160 extern int size_directive_output;
9162 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
9163 definitions except that it uses mips_declare_object to emit the label. */
9166 mips_declare_object_name (FILE *stream, const char *name,
9167 tree decl ATTRIBUTE_UNUSED)
9169 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
9170 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
9173 size_directive_output = 0;
9174 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
9178 size_directive_output = 1;
9179 size = int_size_in_bytes (TREE_TYPE (decl));
9180 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
9183 mips_declare_object (stream, name, "", ":\n");
9186 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
9189 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
9193 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
9194 if (!flag_inhibit_size_directive
9195 && DECL_SIZE (decl) != 0
9198 && DECL_INITIAL (decl) == error_mark_node
9199 && !size_directive_output)
9203 size_directive_output = 1;
9204 size = int_size_in_bytes (TREE_TYPE (decl));
9205 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
9210 /* Return the FOO in the name of the ".mdebug.FOO" section associated
9211 with the current ABI. */
9214 mips_mdebug_abi_name (void)
9227 return TARGET_64BIT ? "eabi64" : "eabi32";
9233 /* Implement TARGET_ASM_FILE_START. */
9236 mips_file_start (void)
9238 default_file_start ();
9240 /* Generate a special section to describe the ABI switches used to
9241 produce the resultant binary. */
9243 /* Record the ABI itself. Modern versions of binutils encode
9244 this information in the ELF header flags, but GDB needs the
9245 information in order to correctly debug binaries produced by
9246 older binutils. See the function mips_gdbarch_init in
9248 fprintf (asm_out_file, "\t.section .mdebug.%s\n\t.previous\n",
9249 mips_mdebug_abi_name ());
9251 /* There is no ELF header flag to distinguish long32 forms of the
9252 EABI from long64 forms. Emit a special section to help tools
9253 such as GDB. Do the same for o64, which is sometimes used with
9255 if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
9256 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n"
9257 "\t.previous\n", TARGET_LONG64 ? 64 : 32);
9259 /* Record the NaN encoding. */
9260 if (HAVE_AS_NAN || mips_nan != MIPS_IEEE_754_DEFAULT)
9261 fprintf (asm_out_file, "\t.nan\t%s\n",
9262 mips_nan == MIPS_IEEE_754_2008 ? "2008" : "legacy");
9264 #ifdef HAVE_AS_DOT_MODULE
9265 /* Record the FP ABI. See below for comments. */
9266 if (TARGET_NO_FLOAT)
9267 #ifdef HAVE_AS_GNU_ATTRIBUTE
9268 fputs ("\t.gnu_attribute 4, 0\n", asm_out_file);
9272 else if (!TARGET_HARD_FLOAT_ABI)
9273 fputs ("\t.module\tsoftfloat\n", asm_out_file);
9274 else if (!TARGET_DOUBLE_FLOAT)
9275 fputs ("\t.module\tsinglefloat\n", asm_out_file);
9276 else if (TARGET_FLOATXX)
9277 fputs ("\t.module\tfp=xx\n", asm_out_file);
9278 else if (TARGET_FLOAT64)
9279 fputs ("\t.module\tfp=64\n", asm_out_file);
9281 fputs ("\t.module\tfp=32\n", asm_out_file);
9283 if (TARGET_ODD_SPREG)
9284 fputs ("\t.module\toddspreg\n", asm_out_file);
9286 fputs ("\t.module\tnooddspreg\n", asm_out_file);
9289 #ifdef HAVE_AS_GNU_ATTRIBUTE
9293 /* No floating-point operations, -mno-float. */
9294 if (TARGET_NO_FLOAT)
9296 /* Soft-float code, -msoft-float. */
9297 else if (!TARGET_HARD_FLOAT_ABI)
9299 /* Single-float code, -msingle-float. */
9300 else if (!TARGET_DOUBLE_FLOAT)
9302 /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64.
9304 This case used 12 callee-saved double-precision registers
9305 and is deprecated. */
9306 /* 64-bit or 32-bit FP registers on a 32-bit target, -mfpxx. */
9307 else if (TARGET_FLOATXX)
9309 /* 64-bit FP registers on a 32-bit target, -mfp64 -modd-spreg. */
9310 else if (mips_abi == ABI_32 && TARGET_FLOAT64 && TARGET_ODD_SPREG)
9312 /* 64-bit FP registers on a 32-bit target, -mfp64 -mno-odd-spreg. */
9313 else if (mips_abi == ABI_32 && TARGET_FLOAT64)
9315 /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */
9319 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n", attr);
9324 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
9325 if (TARGET_ABICALLS)
9327 fprintf (asm_out_file, "\t.abicalls\n");
9328 if (TARGET_ABICALLS_PIC0)
9329 fprintf (asm_out_file, "\t.option\tpic0\n");
9332 if (flag_verbose_asm)
9333 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
9335 mips_small_data_threshold, mips_arch_info->name, mips_isa);
9338 /* Implement TARGET_ASM_CODE_END. */
9341 mips_code_end (void)
9343 mips_finish_stub (&mips16_rdhwr_stub);
9344 mips_finish_stub (&mips16_get_fcsr_stub);
9345 mips_finish_stub (&mips16_set_fcsr_stub);
9348 /* Make the last instruction frame-related and note that it performs
9349 the operation described by FRAME_PATTERN. */
9352 mips_set_frame_expr (rtx frame_pattern)
9356 insn = get_last_insn ();
9357 RTX_FRAME_RELATED_P (insn) = 1;
9358 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
9363 /* Return a frame-related rtx that stores REG at MEM.
9364 REG must be a single register. */
9367 mips_frame_set (rtx mem, rtx reg)
9371 set = gen_rtx_SET (mem, reg);
9372 RTX_FRAME_RELATED_P (set) = 1;
9377 /* Record that the epilogue has restored call-saved register REG. */
9380 mips_add_cfa_restore (rtx reg)
9382 mips_epilogue.cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg,
9383 mips_epilogue.cfa_restores);
9386 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
9387 mips16e_s2_s8_regs[X], it must also save the registers in indexes
9388 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
9389 static const unsigned char mips16e_s2_s8_regs[] = {
9390 30, 23, 22, 21, 20, 19, 18
9392 static const unsigned char mips16e_a0_a3_regs[] = {
9396 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
9397 ordered from the uppermost in memory to the lowest in memory. */
9398 static const unsigned char mips16e_save_restore_regs[] = {
9399 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
9402 /* Return the index of the lowest X in the range [0, SIZE) for which
9403 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
9406 mips16e_find_first_register (unsigned int mask, const unsigned char *regs,
9411 for (i = 0; i < size; i++)
9412 if (BITSET_P (mask, regs[i]))
9418 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
9419 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
9420 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
9421 is true for all indexes (X, SIZE). */
9424 mips16e_mask_registers (unsigned int *mask_ptr, const unsigned char *regs,
9425 unsigned int size, unsigned int *num_regs_ptr)
9429 i = mips16e_find_first_register (*mask_ptr, regs, size);
9430 for (i++; i < size; i++)
9431 if (!BITSET_P (*mask_ptr, regs[i]))
9434 *mask_ptr |= 1 << regs[i];
9438 /* Return a simplified form of X using the register values in REG_VALUES.
9439 REG_VALUES[R] is the last value assigned to hard register R, or null
9440 if R has not been modified.
9442 This function is rather limited, but is good enough for our purposes. */
9445 mips16e_collect_propagate_value (rtx x, rtx *reg_values)
9447 x = avoid_constant_pool_reference (x);
9451 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
9452 return simplify_gen_unary (GET_CODE (x), GET_MODE (x),
9453 x0, GET_MODE (XEXP (x, 0)));
9456 if (ARITHMETIC_P (x))
9458 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
9459 rtx x1 = mips16e_collect_propagate_value (XEXP (x, 1), reg_values);
9460 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), x0, x1);
9464 && reg_values[REGNO (x)]
9465 && !rtx_unstable_p (reg_values[REGNO (x)]))
9466 return reg_values[REGNO (x)];
9471 /* Return true if (set DEST SRC) stores an argument register into its
9472 caller-allocated save slot, storing the number of that argument
9473 register in *REGNO_PTR if so. REG_VALUES is as for
9474 mips16e_collect_propagate_value. */
9477 mips16e_collect_argument_save_p (rtx dest, rtx src, rtx *reg_values,
9478 unsigned int *regno_ptr)
9480 unsigned int argno, regno;
9481 HOST_WIDE_INT offset, required_offset;
9484 /* Check that this is a word-mode store. */
9485 if (!MEM_P (dest) || !REG_P (src) || GET_MODE (dest) != word_mode)
9488 /* Check that the register being saved is an unmodified argument
9490 regno = REGNO (src);
9491 if (!IN_RANGE (regno, GP_ARG_FIRST, GP_ARG_LAST) || reg_values[regno])
9493 argno = regno - GP_ARG_FIRST;
9495 /* Check whether the address is an appropriate stack-pointer or
9496 frame-pointer access. */
9497 addr = mips16e_collect_propagate_value (XEXP (dest, 0), reg_values);
9498 mips_split_plus (addr, &base, &offset);
9499 required_offset = cfun->machine->frame.total_size + argno * UNITS_PER_WORD;
9500 if (base == hard_frame_pointer_rtx)
9501 required_offset -= cfun->machine->frame.hard_frame_pointer_offset;
9502 else if (base != stack_pointer_rtx)
9504 if (offset != required_offset)
9511 /* A subroutine of mips_expand_prologue, called only when generating
9512 MIPS16e SAVE instructions. Search the start of the function for any
9513 instructions that save argument registers into their caller-allocated
9514 save slots. Delete such instructions and return a value N such that
9515 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
9516 instructions redundant. */
9519 mips16e_collect_argument_saves (void)
9521 rtx reg_values[FIRST_PSEUDO_REGISTER];
9522 rtx_insn *insn, *next;
9524 unsigned int nargs, regno;
9526 push_topmost_sequence ();
9528 memset (reg_values, 0, sizeof (reg_values));
9529 for (insn = get_insns (); insn; insn = next)
9531 next = NEXT_INSN (insn);
9532 if (NOTE_P (insn) || DEBUG_INSN_P (insn))
9538 set = PATTERN (insn);
9539 if (GET_CODE (set) != SET)
9542 dest = SET_DEST (set);
9543 src = SET_SRC (set);
9544 if (mips16e_collect_argument_save_p (dest, src, reg_values, ®no))
9546 if (!BITSET_P (cfun->machine->frame.mask, regno))
9549 nargs = MAX (nargs, (regno - GP_ARG_FIRST) + 1);
9552 else if (REG_P (dest) && GET_MODE (dest) == word_mode)
9553 reg_values[REGNO (dest)]
9554 = mips16e_collect_propagate_value (src, reg_values);
9558 pop_topmost_sequence ();
9563 /* Return a move between register REGNO and memory location SP + OFFSET.
9564 REG_PARM_P is true if SP + OFFSET belongs to REG_PARM_STACK_SPACE.
9565 Make the move a load if RESTORE_P, otherwise make it a store. */
9568 mips16e_save_restore_reg (bool restore_p, bool reg_parm_p,
9569 HOST_WIDE_INT offset, unsigned int regno)
9573 mem = gen_frame_mem (SImode, plus_constant (Pmode, stack_pointer_rtx,
9575 reg = gen_rtx_REG (SImode, regno);
9578 mips_add_cfa_restore (reg);
9579 return gen_rtx_SET (reg, mem);
9582 return gen_rtx_SET (mem, reg);
9583 return mips_frame_set (mem, reg);
9586 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
9587 The instruction must:
9589 - Allocate or deallocate SIZE bytes in total; SIZE is known
9592 - Save or restore as many registers in *MASK_PTR as possible.
9593 The instruction saves the first registers at the top of the
9594 allocated area, with the other registers below it.
9596 - Save NARGS argument registers above the allocated area.
9598 (NARGS is always zero if RESTORE_P.)
9600 The SAVE and RESTORE instructions cannot save and restore all general
9601 registers, so there may be some registers left over for the caller to
9602 handle. Destructively modify *MASK_PTR so that it contains the registers
9603 that still need to be saved or restored. The caller can save these
9604 registers in the memory immediately below *OFFSET_PTR, which is a
9605 byte offset from the bottom of the allocated stack area. */
9608 mips16e_build_save_restore (bool restore_p, unsigned int *mask_ptr,
9609 HOST_WIDE_INT *offset_ptr, unsigned int nargs,
9613 HOST_WIDE_INT offset, top_offset;
9614 unsigned int i, regno;
9617 gcc_assert (cfun->machine->frame.num_fp == 0);
9619 /* Calculate the number of elements in the PARALLEL. We need one element
9620 for the stack adjustment, one for each argument register save, and one
9621 for each additional register move. */
9623 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
9624 if (BITSET_P (*mask_ptr, mips16e_save_restore_regs[i]))
9627 /* Create the final PARALLEL. */
9628 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (n));
9631 /* Add the stack pointer adjustment. */
9632 set = gen_rtx_SET (stack_pointer_rtx,
9633 plus_constant (Pmode, stack_pointer_rtx,
9634 restore_p ? size : -size));
9635 RTX_FRAME_RELATED_P (set) = 1;
9636 XVECEXP (pattern, 0, n++) = set;
9638 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
9639 top_offset = restore_p ? size : 0;
9641 /* Save the arguments. */
9642 for (i = 0; i < nargs; i++)
9644 offset = top_offset + i * UNITS_PER_WORD;
9645 set = mips16e_save_restore_reg (restore_p, true, offset,
9647 XVECEXP (pattern, 0, n++) = set;
9650 /* Then fill in the other register moves. */
9651 offset = top_offset;
9652 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
9654 regno = mips16e_save_restore_regs[i];
9655 if (BITSET_P (*mask_ptr, regno))
9657 offset -= UNITS_PER_WORD;
9658 set = mips16e_save_restore_reg (restore_p, false, offset, regno);
9659 XVECEXP (pattern, 0, n++) = set;
9660 *mask_ptr &= ~(1 << regno);
9664 /* Tell the caller what offset it should use for the remaining registers. */
9665 *offset_ptr = size + (offset - top_offset);
9667 gcc_assert (n == XVECLEN (pattern, 0));
9672 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
9673 pointer. Return true if PATTERN matches the kind of instruction
9674 generated by mips16e_build_save_restore. If INFO is nonnull,
9675 initialize it when returning true. */
9678 mips16e_save_restore_pattern_p (rtx pattern, HOST_WIDE_INT adjust,
9679 struct mips16e_save_restore_info *info)
9681 unsigned int i, nargs, mask, extra;
9682 HOST_WIDE_INT top_offset, save_offset, offset;
9683 rtx set, reg, mem, base;
9686 if (!GENERATE_MIPS16E_SAVE_RESTORE)
9689 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
9690 top_offset = adjust > 0 ? adjust : 0;
9692 /* Interpret all other members of the PARALLEL. */
9693 save_offset = top_offset - UNITS_PER_WORD;
9697 for (n = 1; n < XVECLEN (pattern, 0); n++)
9699 /* Check that we have a SET. */
9700 set = XVECEXP (pattern, 0, n);
9701 if (GET_CODE (set) != SET)
9704 /* Check that the SET is a load (if restoring) or a store
9706 mem = adjust > 0 ? SET_SRC (set) : SET_DEST (set);
9710 /* Check that the address is the sum of the stack pointer and a
9711 possibly-zero constant offset. */
9712 mips_split_plus (XEXP (mem, 0), &base, &offset);
9713 if (base != stack_pointer_rtx)
9716 /* Check that SET's other operand is a register. */
9717 reg = adjust > 0 ? SET_DEST (set) : SET_SRC (set);
9721 /* Check for argument saves. */
9722 if (offset == top_offset + nargs * UNITS_PER_WORD
9723 && REGNO (reg) == GP_ARG_FIRST + nargs)
9725 else if (offset == save_offset)
9727 while (mips16e_save_restore_regs[i++] != REGNO (reg))
9728 if (i == ARRAY_SIZE (mips16e_save_restore_regs))
9731 mask |= 1 << REGNO (reg);
9732 save_offset -= UNITS_PER_WORD;
9738 /* Check that the restrictions on register ranges are met. */
9740 mips16e_mask_registers (&mask, mips16e_s2_s8_regs,
9741 ARRAY_SIZE (mips16e_s2_s8_regs), &extra);
9742 mips16e_mask_registers (&mask, mips16e_a0_a3_regs,
9743 ARRAY_SIZE (mips16e_a0_a3_regs), &extra);
9747 /* Make sure that the topmost argument register is not saved twice.
9748 The checks above ensure that the same is then true for the other
9749 argument registers. */
9750 if (nargs > 0 && BITSET_P (mask, GP_ARG_FIRST + nargs - 1))
9753 /* Pass back information, if requested. */
9756 info->nargs = nargs;
9758 info->size = (adjust > 0 ? adjust : -adjust);
9764 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
9765 for the register range [MIN_REG, MAX_REG]. Return a pointer to
9766 the null terminator. */
9769 mips16e_add_register_range (char *s, unsigned int min_reg,
9770 unsigned int max_reg)
9772 if (min_reg != max_reg)
9773 s += sprintf (s, ",%s-%s", reg_names[min_reg], reg_names[max_reg]);
9775 s += sprintf (s, ",%s", reg_names[min_reg]);
9779 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
9780 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
9783 mips16e_output_save_restore (rtx pattern, HOST_WIDE_INT adjust)
9785 static char buffer[300];
9787 struct mips16e_save_restore_info info;
9788 unsigned int i, end;
9791 /* Parse the pattern. */
9792 if (!mips16e_save_restore_pattern_p (pattern, adjust, &info))
9795 /* Add the mnemonic. */
9796 s = strcpy (buffer, adjust > 0 ? "restore\t" : "save\t");
9799 /* Save the arguments. */
9801 s += sprintf (s, "%s-%s,", reg_names[GP_ARG_FIRST],
9802 reg_names[GP_ARG_FIRST + info.nargs - 1]);
9803 else if (info.nargs == 1)
9804 s += sprintf (s, "%s,", reg_names[GP_ARG_FIRST]);
9806 /* Emit the amount of stack space to allocate or deallocate. */
9807 s += sprintf (s, "%d", (int) info.size);
9809 /* Save or restore $16. */
9810 if (BITSET_P (info.mask, 16))
9811 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 16]);
9813 /* Save or restore $17. */
9814 if (BITSET_P (info.mask, 17))
9815 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 17]);
9817 /* Save or restore registers in the range $s2...$s8, which
9818 mips16e_s2_s8_regs lists in decreasing order. Note that this
9819 is a software register range; the hardware registers are not
9820 numbered consecutively. */
9821 end = ARRAY_SIZE (mips16e_s2_s8_regs);
9822 i = mips16e_find_first_register (info.mask, mips16e_s2_s8_regs, end);
9824 s = mips16e_add_register_range (s, mips16e_s2_s8_regs[end - 1],
9825 mips16e_s2_s8_regs[i]);
9827 /* Save or restore registers in the range $a0...$a3. */
9828 end = ARRAY_SIZE (mips16e_a0_a3_regs);
9829 i = mips16e_find_first_register (info.mask, mips16e_a0_a3_regs, end);
9831 s = mips16e_add_register_range (s, mips16e_a0_a3_regs[i],
9832 mips16e_a0_a3_regs[end - 1]);
9834 /* Save or restore $31. */
9835 if (BITSET_P (info.mask, RETURN_ADDR_REGNUM))
9836 s += sprintf (s, ",%s", reg_names[RETURN_ADDR_REGNUM]);
9841 /* Return true if the current function returns its value in a floating-point
9842 register in MIPS16 mode. */
9845 mips16_cfun_returns_in_fpr_p (void)
9847 tree return_type = DECL_RESULT (current_function_decl);
9848 return (TARGET_MIPS16
9849 && TARGET_HARD_FLOAT_ABI
9850 && !aggregate_value_p (return_type, current_function_decl)
9851 && mips_return_mode_in_fpr_p (DECL_MODE (return_type)));
9854 /* Return true if predicate PRED is true for at least one instruction.
9855 Cache the result in *CACHE, and assume that the result is true
9856 if *CACHE is already true. */
9859 mips_find_gp_ref (bool *cache, bool (*pred) (rtx_insn *))
9861 rtx_insn *insn, *subinsn;
9865 push_topmost_sequence ();
9866 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9867 FOR_EACH_SUBINSN (subinsn, insn)
9868 if (USEFUL_INSN_P (subinsn) && pred (subinsn))
9873 pop_topmost_sequence ();
9878 /* Return true if INSN refers to the global pointer in an "inflexible" way.
9879 See mips_cfun_has_inflexible_gp_ref_p for details. */
9882 mips_insn_has_inflexible_gp_ref_p (rtx_insn *insn)
9884 /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE
9885 indicate that the target could be a traditional MIPS
9886 lazily-binding stub. */
9887 return find_reg_fusage (insn, USE, pic_offset_table_rtx);
9890 /* Return true if the current function refers to the global pointer
9891 in a way that forces $28 to be valid. This means that we can't
9892 change the choice of global pointer, even for NewABI code.
9894 One example of this (and one which needs several checks) is that
9895 $28 must be valid when calling traditional MIPS lazy-binding stubs.
9896 (This restriction does not apply to PLTs.) */
9899 mips_cfun_has_inflexible_gp_ref_p (void)
9901 /* If the function has a nonlocal goto, $28 must hold the correct
9902 global pointer for the target function. That is, the target
9903 of the goto implicitly uses $28. */
9904 if (crtl->has_nonlocal_goto)
9907 if (TARGET_ABICALLS_PIC2)
9909 /* Symbolic accesses implicitly use the global pointer unless
9910 -mexplicit-relocs is in effect. JAL macros to symbolic addresses
9911 might go to traditional MIPS lazy-binding stubs. */
9912 if (!TARGET_EXPLICIT_RELOCS)
9915 /* FUNCTION_PROFILER includes a JAL to _mcount, which again
9916 can be lazily-bound. */
9920 /* MIPS16 functions that return in FPRs need to call an
9921 external libgcc routine. This call is only made explict
9922 during mips_expand_epilogue, and it too might be lazily bound. */
9923 if (mips16_cfun_returns_in_fpr_p ())
9927 return mips_find_gp_ref (&cfun->machine->has_inflexible_gp_insn_p,
9928 mips_insn_has_inflexible_gp_ref_p);
9931 /* Return true if INSN refers to the global pointer in a "flexible" way.
9932 See mips_cfun_has_flexible_gp_ref_p for details. */
9935 mips_insn_has_flexible_gp_ref_p (rtx_insn *insn)
9937 return (get_attr_got (insn) != GOT_UNSET
9938 || mips_small_data_pattern_p (PATTERN (insn))
9939 || reg_overlap_mentioned_p (pic_offset_table_rtx, PATTERN (insn)));
9942 /* Return true if the current function references the global pointer,
9943 but if those references do not inherently require the global pointer
9944 to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */
9947 mips_cfun_has_flexible_gp_ref_p (void)
9949 /* Reload can sometimes introduce constant pool references
9950 into a function that otherwise didn't need them. For example,
9951 suppose we have an instruction like:
9953 (set (reg:DF R1) (float:DF (reg:SI R2)))
9955 If R2 turns out to be a constant such as 1, the instruction may
9956 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
9957 the option of using this constant if R2 doesn't get allocated
9960 In cases like these, reload will have added the constant to the
9961 pool but no instruction will yet refer to it. */
9962 if (TARGET_ABICALLS_PIC2 && !reload_completed && crtl->uses_const_pool)
9965 return mips_find_gp_ref (&cfun->machine->has_flexible_gp_insn_p,
9966 mips_insn_has_flexible_gp_ref_p);
9969 /* Return the register that should be used as the global pointer
9970 within this function. Return INVALID_REGNUM if the function
9971 doesn't need a global pointer. */
9974 mips_global_pointer (void)
9978 /* $gp is always available unless we're using a GOT. */
9979 if (!TARGET_USE_GOT)
9980 return GLOBAL_POINTER_REGNUM;
9982 /* If there are inflexible references to $gp, we must use the
9983 standard register. */
9984 if (mips_cfun_has_inflexible_gp_ref_p ())
9985 return GLOBAL_POINTER_REGNUM;
9987 /* If there are no current references to $gp, then the only uses
9988 we can introduce later are those involved in long branches. */
9989 if (TARGET_ABSOLUTE_JUMPS && !mips_cfun_has_flexible_gp_ref_p ())
9990 return INVALID_REGNUM;
9992 /* If the global pointer is call-saved, try to use a call-clobbered
9994 if (TARGET_CALL_SAVED_GP && crtl->is_leaf)
9995 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
9996 if (!df_regs_ever_live_p (regno)
9997 && call_really_used_regs[regno]
9998 && !fixed_regs[regno]
9999 && regno != PIC_FUNCTION_ADDR_REGNUM)
10002 return GLOBAL_POINTER_REGNUM;
10005 /* Return true if the current function's prologue must load the global
10006 pointer value into pic_offset_table_rtx and store the same value in
10007 the function's cprestore slot (if any).
10009 One problem we have to deal with is that, when emitting GOT-based
10010 position independent code, long-branch sequences will need to load
10011 the address of the branch target from the GOT. We don't know until
10012 the very end of compilation whether (and where) the function needs
10013 long branches, so we must ensure that _any_ branch can access the
10014 global pointer in some form. However, we do not want to pessimize
10015 the usual case in which all branches are short.
10017 We handle this as follows:
10019 (1) During reload, we set cfun->machine->global_pointer to
10020 INVALID_REGNUM if we _know_ that the current function
10021 doesn't need a global pointer. This is only valid if
10022 long branches don't need the GOT.
10024 Otherwise, we assume that we might need a global pointer
10025 and pick an appropriate register.
10027 (2) If cfun->machine->global_pointer != INVALID_REGNUM,
10028 we ensure that the global pointer is available at every
10029 block boundary bar entry and exit. We do this in one of two ways:
10031 - If the function has a cprestore slot, we ensure that this
10032 slot is valid at every branch. However, as explained in
10033 point (6) below, there is no guarantee that pic_offset_table_rtx
10034 itself is valid if new uses of the global pointer are introduced
10035 after the first post-epilogue split.
10037 We guarantee that the cprestore slot is valid by loading it
10038 into a fake register, CPRESTORE_SLOT_REGNUM. We then make
10039 this register live at every block boundary bar function entry
10040 and exit. It is then invalid to move the load (and thus the
10041 preceding store) across a block boundary.
10043 - If the function has no cprestore slot, we guarantee that
10044 pic_offset_table_rtx itself is valid at every branch.
10046 See mips_eh_uses for the handling of the register liveness.
10048 (3) During prologue and epilogue generation, we emit "ghost"
10049 placeholder instructions to manipulate the global pointer.
10051 (4) During prologue generation, we set cfun->machine->must_initialize_gp_p
10052 and cfun->machine->must_restore_gp_when_clobbered_p if we already know
10053 that the function needs a global pointer. (There is no need to set
10054 them earlier than this, and doing it as late as possible leads to
10055 fewer false positives.)
10057 (5) If cfun->machine->must_initialize_gp_p is true during a
10058 split_insns pass, we split the ghost instructions into real
10059 instructions. These split instructions can then be optimized in
10060 the usual way. Otherwise, we keep the ghost instructions intact,
10061 and optimize for the case where they aren't needed. We still
10062 have the option of splitting them later, if we need to introduce
10063 new uses of the global pointer.
10065 For example, the scheduler ignores a ghost instruction that
10066 stores $28 to the stack, but it handles the split form of
10067 the ghost instruction as an ordinary store.
10069 (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p
10070 is true during the first post-epilogue split_insns pass, we split
10071 calls and restore_gp patterns into instructions that explicitly
10072 load pic_offset_table_rtx from the cprestore slot. Otherwise,
10073 we split these patterns into instructions that _don't_ load from
10074 the cprestore slot.
10076 If cfun->machine->must_restore_gp_when_clobbered_p is true at the
10077 time of the split, then any instructions that exist at that time
10078 can make free use of pic_offset_table_rtx. However, if we want
10079 to introduce new uses of the global pointer after the split,
10080 we must explicitly load the value from the cprestore slot, since
10081 pic_offset_table_rtx itself might not be valid at a given point
10084 The idea is that we want to be able to delete redundant
10085 loads from the cprestore slot in the usual case where no
10086 long branches are needed.
10088 (7) If cfun->machine->must_initialize_gp_p is still false at the end
10089 of md_reorg, we decide whether the global pointer is needed for
10090 long branches. If so, we set cfun->machine->must_initialize_gp_p
10091 to true and split the ghost instructions into real instructions
10094 Note that the ghost instructions must have a zero length for three reasons:
10096 - Giving the length of the underlying $gp sequence might cause
10097 us to use long branches in cases where they aren't really needed.
10099 - They would perturb things like alignment calculations.
10101 - More importantly, the hazard detection in md_reorg relies on
10102 empty instructions having a zero length.
10104 If we find a long branch and split the ghost instructions at the
10105 end of md_reorg, the split could introduce more long branches.
10106 That isn't a problem though, because we still do the split before
10107 the final shorten_branches pass.
10109 This is extremely ugly, but it seems like the best compromise between
10110 correctness and efficiency. */
10113 mips_must_initialize_gp_p (void)
10115 return cfun->machine->must_initialize_gp_p;
10118 /* Return true if REGNO is a register that is ordinarily call-clobbered
10119 but must nevertheless be preserved by an interrupt handler. */
10122 mips_interrupt_extra_call_saved_reg_p (unsigned int regno)
10124 if ((ISA_HAS_HILO || TARGET_DSP)
10125 && MD_REG_P (regno))
10128 if (TARGET_DSP && DSP_ACC_REG_P (regno))
10131 if (GP_REG_P (regno)
10132 && cfun->machine->use_shadow_register_set == SHADOW_SET_NO)
10134 /* $0 is hard-wired. */
10135 if (regno == GP_REG_FIRST)
10138 /* The interrupt handler can treat kernel registers as
10139 scratch registers. */
10140 if (KERNEL_REG_P (regno))
10143 /* The function will return the stack pointer to its original value
10145 if (regno == STACK_POINTER_REGNUM)
10148 /* Otherwise, return true for registers that aren't ordinarily
10150 return call_really_used_regs[regno];
10156 /* Return true if the current function should treat register REGNO
10160 mips_cfun_call_saved_reg_p (unsigned int regno)
10162 /* If the user makes an ordinarily-call-saved register global,
10163 that register is no longer call-saved. */
10164 if (global_regs[regno])
10167 /* Interrupt handlers need to save extra registers. */
10168 if (cfun->machine->interrupt_handler_p
10169 && mips_interrupt_extra_call_saved_reg_p (regno))
10172 /* call_insns preserve $28 unless they explicitly say otherwise,
10173 so call_really_used_regs[] treats $28 as call-saved. However,
10174 we want the ABI property rather than the default call_insn
10176 return (regno == GLOBAL_POINTER_REGNUM
10177 ? TARGET_CALL_SAVED_GP
10178 : !call_really_used_regs[regno]);
10181 /* Return true if the function body might clobber register REGNO.
10182 We know that REGNO is call-saved. */
10185 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno)
10187 /* Some functions should be treated as clobbering all call-saved
10189 if (crtl->saves_all_registers)
10192 /* DF handles cases where a register is explicitly referenced in
10193 the rtl. Incoming values are passed in call-clobbered registers,
10194 so we can assume that any live call-saved register is set within
10196 if (df_regs_ever_live_p (regno))
10199 /* Check for registers that are clobbered by FUNCTION_PROFILER.
10200 These clobbers are not explicit in the rtl. */
10201 if (crtl->profile && MIPS_SAVE_REG_FOR_PROFILING_P (regno))
10204 /* If we're using a call-saved global pointer, the function's
10205 prologue will need to set it up. */
10206 if (cfun->machine->global_pointer == regno)
10209 /* The function's prologue will need to set the frame pointer if
10210 frame_pointer_needed. */
10211 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
10214 /* If a MIPS16 function returns a value in FPRs, its epilogue
10215 will need to call an external libgcc routine. This yet-to-be
10216 generated call_insn will clobber $31. */
10217 if (regno == RETURN_ADDR_REGNUM && mips16_cfun_returns_in_fpr_p ())
10220 /* If REGNO is ordinarily call-clobbered, we must assume that any
10221 called function could modify it. */
10222 if (cfun->machine->interrupt_handler_p
10224 && mips_interrupt_extra_call_saved_reg_p (regno))
10230 /* Return true if the current function must save register REGNO. */
10233 mips_save_reg_p (unsigned int regno)
10235 if (mips_cfun_call_saved_reg_p (regno))
10237 if (mips_cfun_might_clobber_call_saved_reg_p (regno))
10240 /* Save both registers in an FPR pair if either one is used. This is
10241 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
10242 register to be used without the even register. */
10243 if (FP_REG_P (regno)
10244 && MAX_FPRS_PER_FMT == 2
10245 && mips_cfun_might_clobber_call_saved_reg_p (regno + 1))
10249 /* We need to save the incoming return address if __builtin_eh_return
10250 is being used to set a different return address. */
10251 if (regno == RETURN_ADDR_REGNUM && crtl->calls_eh_return)
10257 /* Populate the current function's mips_frame_info structure.
10259 MIPS stack frames look like:
10261 +-------------------------------+
10263 | incoming stack arguments |
10265 +-------------------------------+
10267 | caller-allocated save area |
10268 A | for register arguments |
10270 +-------------------------------+ <-- incoming stack pointer
10272 | callee-allocated save area |
10273 B | for arguments that are |
10274 | split between registers and |
10277 +-------------------------------+ <-- arg_pointer_rtx
10279 C | callee-allocated save area |
10280 | for register varargs |
10282 +-------------------------------+ <-- frame_pointer_rtx
10283 | | + cop0_sp_offset
10284 | COP0 reg save area | + UNITS_PER_WORD
10286 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
10287 | | + UNITS_PER_WORD
10288 | accumulator save area |
10290 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
10291 | | + UNITS_PER_HWFPVALUE
10294 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset
10295 | | + UNITS_PER_WORD
10298 +-------------------------------+ <-- frame_pointer_rtx with
10299 | | \ -fstack-protector
10300 | local variables | | var_size
10302 +-------------------------------+
10304 | $gp save area | | cprestore_size
10306 P +-------------------------------+ <-- hard_frame_pointer_rtx for
10308 | outgoing stack arguments | |
10310 +-------------------------------+ | args_size
10312 | caller-allocated save area | |
10313 | for register arguments | |
10315 +-------------------------------+ <-- stack_pointer_rtx
10316 frame_pointer_rtx without
10318 hard_frame_pointer_rtx for
10321 At least two of A, B and C will be empty.
10323 Dynamic stack allocations such as alloca insert data at point P.
10324 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
10325 hard_frame_pointer_rtx unchanged. */
10328 mips_compute_frame_info (void)
10330 struct mips_frame_info *frame;
10331 HOST_WIDE_INT offset, size;
10332 unsigned int regno, i;
10334 /* Skip re-computing the frame info after reload completed. */
10335 if (reload_completed)
10338 /* Set this function's interrupt properties. */
10339 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
10341 if (mips_isa_rev < 2)
10342 error ("the %<interrupt%> attribute requires a MIPS32r2 processor or greater");
10343 else if (TARGET_MIPS16)
10344 error ("interrupt handlers cannot be MIPS16 functions");
10347 cfun->machine->interrupt_handler_p = true;
10348 cfun->machine->int_mask =
10349 mips_interrupt_mask (TREE_TYPE (current_function_decl));
10350 cfun->machine->use_shadow_register_set =
10351 mips_use_shadow_register_set (TREE_TYPE (current_function_decl));
10352 cfun->machine->keep_interrupts_masked_p =
10353 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl));
10354 cfun->machine->use_debug_exception_return_p =
10355 mips_use_debug_exception_return_p (TREE_TYPE
10356 (current_function_decl));
10360 frame = &cfun->machine->frame;
10361 memset (frame, 0, sizeof (*frame));
10362 size = get_frame_size ();
10364 /* The first two blocks contain the outgoing argument area and the $gp save
10365 slot. This area isn't needed in leaf functions. We can also skip it
10366 if we know that none of the called functions will use this space.
10368 But if the target-independent frame size is nonzero, we have already
10369 committed to allocating these in STARTING_FRAME_OFFSET for
10370 !FRAME_GROWS_DOWNWARD. */
10372 if ((size == 0 || FRAME_GROWS_DOWNWARD)
10373 && (crtl->is_leaf || (cfun->machine->optimize_call_stack && !flag_pic)))
10375 /* The MIPS 3.0 linker does not like functions that dynamically
10376 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
10377 looks like we are trying to create a second frame pointer to the
10378 function, so allocate some stack space to make it happy. */
10379 if (cfun->calls_alloca)
10380 frame->args_size = REG_PARM_STACK_SPACE (cfun->decl);
10382 frame->args_size = 0;
10383 frame->cprestore_size = 0;
10387 frame->args_size = crtl->outgoing_args_size;
10388 frame->cprestore_size = MIPS_GP_SAVE_AREA_SIZE;
10391 /* MIPS16 code offsets the frame pointer by the size of the outgoing
10392 arguments. This tends to increase the chances of using unextended
10393 instructions for local variables and incoming arguments. */
10395 frame->hard_frame_pointer_offset = frame->args_size;
10397 /* PR 69129 / 69012: Beware of a possible race condition. mips_global_pointer
10398 might call mips_cfun_has_inflexible_gp_ref_p which in turn can call
10399 mips_find_gp_ref which will iterate over the current insn sequence.
10400 If any of these insns use the cprestore_save_slot_operand or
10401 cprestore_load_slot_operand predicates in order to be recognised then
10402 they will call mips_cprestore_address_p which calls
10403 mips_get_cprestore_base_and_offset which expects the frame information
10404 to be filled in... In fact mips_get_cprestore_base_and_offset only
10405 needs the args_size and hard_frame_pointer_offset fields to be filled
10406 in, which is why the global_pointer field is initialised here and not
10408 cfun->machine->global_pointer = mips_global_pointer ();
10410 offset = frame->args_size + frame->cprestore_size;
10412 /* Move above the local variables. */
10413 frame->var_size = MIPS_STACK_ALIGN (size);
10414 offset += frame->var_size;
10416 /* Find out which GPRs we need to save. */
10417 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
10418 if (mips_save_reg_p (regno))
10421 frame->mask |= 1 << (regno - GP_REG_FIRST);
10424 /* If this function calls eh_return, we must also save and restore the
10425 EH data registers. */
10426 if (crtl->calls_eh_return)
10427 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; i++)
10430 frame->mask |= 1 << (EH_RETURN_DATA_REGNO (i) - GP_REG_FIRST);
10433 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
10434 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
10435 save all later registers too. */
10436 if (GENERATE_MIPS16E_SAVE_RESTORE)
10438 mips16e_mask_registers (&frame->mask, mips16e_s2_s8_regs,
10439 ARRAY_SIZE (mips16e_s2_s8_regs), &frame->num_gp);
10440 mips16e_mask_registers (&frame->mask, mips16e_a0_a3_regs,
10441 ARRAY_SIZE (mips16e_a0_a3_regs), &frame->num_gp);
10444 /* Move above the GPR save area. */
10445 if (frame->num_gp > 0)
10447 offset += MIPS_STACK_ALIGN (frame->num_gp * UNITS_PER_WORD);
10448 frame->gp_sp_offset = offset - UNITS_PER_WORD;
10451 /* Find out which FPRs we need to save. This loop must iterate over
10452 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
10453 if (TARGET_HARD_FLOAT)
10454 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += MAX_FPRS_PER_FMT)
10455 if (mips_save_reg_p (regno))
10457 frame->num_fp += MAX_FPRS_PER_FMT;
10458 frame->fmask |= ~(~0U << MAX_FPRS_PER_FMT) << (regno - FP_REG_FIRST);
10461 /* Move above the FPR save area. */
10462 if (frame->num_fp > 0)
10464 offset += MIPS_STACK_ALIGN (frame->num_fp * UNITS_PER_FPREG);
10465 frame->fp_sp_offset = offset - UNITS_PER_HWFPVALUE;
10468 /* Add in space for the interrupt context information. */
10469 if (cfun->machine->interrupt_handler_p)
10472 if (mips_save_reg_p (LO_REGNUM) || mips_save_reg_p (HI_REGNUM))
10475 frame->acc_mask |= (1 << 0);
10478 /* Check accumulators 1, 2, 3. */
10479 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
10480 if (mips_save_reg_p (i) || mips_save_reg_p (i + 1))
10483 frame->acc_mask |= 1 << (((i - DSP_ACC_REG_FIRST) / 2) + 1);
10486 /* All interrupt context functions need space to preserve STATUS. */
10487 frame->num_cop0_regs++;
10489 /* We need to save EPC regardless of whether interrupts remain masked
10490 as exceptions will corrupt EPC. */
10491 frame->num_cop0_regs++;
10494 /* Move above the accumulator save area. */
10495 if (frame->num_acc > 0)
10497 /* Each accumulator needs 2 words. */
10498 offset += frame->num_acc * 2 * UNITS_PER_WORD;
10499 frame->acc_sp_offset = offset - UNITS_PER_WORD;
10502 /* Move above the COP0 register save area. */
10503 if (frame->num_cop0_regs > 0)
10505 offset += frame->num_cop0_regs * UNITS_PER_WORD;
10506 frame->cop0_sp_offset = offset - UNITS_PER_WORD;
10509 /* Determine if we can save the callee-saved registers in the frame
10510 header. Restrict this to functions where there is no other reason
10511 to allocate stack space so that we can eliminate the instructions
10512 that modify the stack pointer. */
10516 && flag_frame_header_optimization
10517 && !MAIN_NAME_P (DECL_NAME (current_function_decl))
10518 && cfun->machine->varargs_size == 0
10519 && crtl->args.pretend_args_size == 0
10520 && frame->var_size == 0
10521 && frame->num_acc == 0
10522 && frame->num_cop0_regs == 0
10523 && frame->num_fp == 0
10524 && frame->num_gp > 0
10525 && frame->num_gp <= MAX_ARGS_IN_REGISTERS
10526 && !GENERATE_MIPS16E_SAVE_RESTORE
10527 && !cfun->machine->interrupt_handler_p
10528 && cfun->machine->does_not_use_frame_header
10529 && cfun->machine->optimize_call_stack
10530 && !cfun->machine->callers_may_not_allocate_frame
10531 && !mips_cfun_has_cprestore_slot_p ())
10534 frame->gp_sp_offset = REG_PARM_STACK_SPACE(cfun) - UNITS_PER_WORD;
10535 cfun->machine->use_frame_header_for_callee_saved_regs = true;
10538 /* Move above the callee-allocated varargs save area. */
10539 offset += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
10540 frame->arg_pointer_offset = offset;
10542 /* Move above the callee-allocated area for pretend stack arguments. */
10543 offset += crtl->args.pretend_args_size;
10544 frame->total_size = offset;
10546 /* Work out the offsets of the save areas from the top of the frame. */
10547 if (frame->gp_sp_offset > 0)
10548 frame->gp_save_offset = frame->gp_sp_offset - offset;
10549 if (frame->fp_sp_offset > 0)
10550 frame->fp_save_offset = frame->fp_sp_offset - offset;
10551 if (frame->acc_sp_offset > 0)
10552 frame->acc_save_offset = frame->acc_sp_offset - offset;
10553 if (frame->num_cop0_regs > 0)
10554 frame->cop0_save_offset = frame->cop0_sp_offset - offset;
10557 /* Return the style of GP load sequence that is being used for the
10558 current function. */
10560 enum mips_loadgp_style
10561 mips_current_loadgp_style (void)
10563 if (!TARGET_USE_GOT || cfun->machine->global_pointer == INVALID_REGNUM)
10564 return LOADGP_NONE;
10566 if (TARGET_RTP_PIC)
10569 if (TARGET_ABSOLUTE_ABICALLS)
10570 return LOADGP_ABSOLUTE;
10572 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
10575 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
10578 mips_frame_pointer_required (void)
10580 /* If the function contains dynamic stack allocations, we need to
10581 use the frame pointer to access the static parts of the frame. */
10582 if (cfun->calls_alloca)
10585 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
10586 reload may be unable to compute the address of a local variable,
10587 since there is no way to add a large constant to the stack pointer
10588 without using a second temporary register. */
10591 mips_compute_frame_info ();
10592 if (!SMALL_OPERAND (cfun->machine->frame.total_size))
10599 /* Make sure that we're not trying to eliminate to the wrong hard frame
10603 mips_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
10605 return (to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM);
10608 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
10609 or argument pointer. TO is either the stack pointer or hard frame
10613 mips_initial_elimination_offset (int from, int to)
10615 HOST_WIDE_INT offset;
10617 mips_compute_frame_info ();
10619 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */
10622 case FRAME_POINTER_REGNUM:
10623 if (FRAME_GROWS_DOWNWARD)
10624 offset = (cfun->machine->frame.args_size
10625 + cfun->machine->frame.cprestore_size
10626 + cfun->machine->frame.var_size);
10631 case ARG_POINTER_REGNUM:
10632 offset = cfun->machine->frame.arg_pointer_offset;
10636 gcc_unreachable ();
10639 if (to == HARD_FRAME_POINTER_REGNUM)
10640 offset -= cfun->machine->frame.hard_frame_pointer_offset;
10645 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
10648 mips_extra_live_on_entry (bitmap regs)
10650 if (TARGET_USE_GOT)
10652 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
10653 the global pointer. */
10654 if (!TARGET_ABSOLUTE_ABICALLS)
10655 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
10657 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
10658 the global pointer. */
10660 bitmap_set_bit (regs, MIPS16_PIC_TEMP_REGNUM);
10662 /* See the comment above load_call<mode> for details. */
10663 bitmap_set_bit (regs, GOT_VERSION_REGNUM);
10667 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
10671 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
10676 return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);
10679 /* Emit code to change the current function's return address to
10680 ADDRESS. SCRATCH is available as a scratch register, if needed.
10681 ADDRESS and SCRATCH are both word-mode GPRs. */
10684 mips_set_return_address (rtx address, rtx scratch)
10688 gcc_assert (BITSET_P (cfun->machine->frame.mask, RETURN_ADDR_REGNUM));
10689 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
10690 cfun->machine->frame.gp_sp_offset);
10691 mips_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address);
10694 /* Return true if the current function has a cprestore slot. */
10697 mips_cfun_has_cprestore_slot_p (void)
10699 return (cfun->machine->global_pointer != INVALID_REGNUM
10700 && cfun->machine->frame.cprestore_size > 0);
10703 /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the
10704 cprestore slot. LOAD_P is true if the caller wants to load from
10705 the cprestore slot; it is false if the caller wants to store to
10709 mips_get_cprestore_base_and_offset (rtx *base, HOST_WIDE_INT *offset,
10712 const struct mips_frame_info *frame;
10714 frame = &cfun->machine->frame;
10715 /* .cprestore always uses the stack pointer instead of the frame pointer.
10716 We have a free choice for direct stores for non-MIPS16 functions,
10717 and for MIPS16 functions whose cprestore slot is in range of the
10718 stack pointer. Using the stack pointer would sometimes give more
10719 (early) scheduling freedom, but using the frame pointer would
10720 sometimes give more (late) scheduling freedom. It's hard to
10721 predict which applies to a given function, so let's keep things
10724 Loads must always use the frame pointer in functions that call
10725 alloca, and there's little benefit to using the stack pointer
10727 if (frame_pointer_needed && !(TARGET_CPRESTORE_DIRECTIVE && !load_p))
10729 *base = hard_frame_pointer_rtx;
10730 *offset = frame->args_size - frame->hard_frame_pointer_offset;
10734 *base = stack_pointer_rtx;
10735 *offset = frame->args_size;
10739 /* Return true if X is the load or store address of the cprestore slot;
10740 LOAD_P says which. */
10743 mips_cprestore_address_p (rtx x, bool load_p)
10745 rtx given_base, required_base;
10746 HOST_WIDE_INT given_offset, required_offset;
10748 mips_split_plus (x, &given_base, &given_offset);
10749 mips_get_cprestore_base_and_offset (&required_base, &required_offset, load_p);
10750 return given_base == required_base && given_offset == required_offset;
10753 /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are
10754 going to load from it, false if we are going to store to it.
10755 Use TEMP as a temporary register if need be. */
10758 mips_cprestore_slot (rtx temp, bool load_p)
10761 HOST_WIDE_INT offset;
10763 mips_get_cprestore_base_and_offset (&base, &offset, load_p);
10764 return gen_frame_mem (Pmode, mips_add_offset (temp, base, offset));
10767 /* Emit instructions to save global pointer value GP into cprestore
10768 slot MEM. OFFSET is the offset that MEM applies to the base register.
10770 MEM may not be a legitimate address. If it isn't, TEMP is a
10771 temporary register that can be used, otherwise it is a SCRATCH. */
10774 mips_save_gp_to_cprestore_slot (rtx mem, rtx offset, rtx gp, rtx temp)
10776 if (TARGET_CPRESTORE_DIRECTIVE)
10778 gcc_assert (gp == pic_offset_table_rtx);
10779 emit_insn (PMODE_INSN (gen_cprestore, (mem, offset)));
10782 mips_emit_move (mips_cprestore_slot (temp, false), gp);
10785 /* Restore $gp from its save slot, using TEMP as a temporary base register
10786 if need be. This function is for o32 and o64 abicalls only.
10788 See mips_must_initialize_gp_p for details about how we manage the
10792 mips_restore_gp_from_cprestore_slot (rtx temp)
10794 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI && epilogue_completed);
10796 if (!cfun->machine->must_restore_gp_when_clobbered_p)
10798 emit_note (NOTE_INSN_DELETED);
10804 mips_emit_move (temp, mips_cprestore_slot (temp, true));
10805 mips_emit_move (pic_offset_table_rtx, temp);
10808 mips_emit_move (pic_offset_table_rtx, mips_cprestore_slot (temp, true));
10809 if (!TARGET_EXPLICIT_RELOCS)
10810 emit_insn (gen_blockage ());
10813 /* A function to save or store a register. The first argument is the
10814 register and the second is the stack slot. */
10815 typedef void (*mips_save_restore_fn) (rtx, rtx);
10817 /* Use FN to save or restore register REGNO. MODE is the register's
10818 mode and OFFSET is the offset of its save slot from the current
10822 mips_save_restore_reg (machine_mode mode, int regno,
10823 HOST_WIDE_INT offset, mips_save_restore_fn fn)
10827 mem = gen_frame_mem (mode, plus_constant (Pmode, stack_pointer_rtx,
10829 fn (gen_rtx_REG (mode, regno), mem);
10832 /* Call FN for each accumlator that is saved by the current function.
10833 SP_OFFSET is the offset of the current stack pointer from the start
10837 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
10839 HOST_WIDE_INT offset;
10842 offset = cfun->machine->frame.acc_sp_offset - sp_offset;
10843 if (BITSET_P (cfun->machine->frame.acc_mask, 0))
10845 mips_save_restore_reg (word_mode, LO_REGNUM, offset, fn);
10846 offset -= UNITS_PER_WORD;
10847 mips_save_restore_reg (word_mode, HI_REGNUM, offset, fn);
10848 offset -= UNITS_PER_WORD;
10851 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
10852 if (BITSET_P (cfun->machine->frame.acc_mask,
10853 ((regno - DSP_ACC_REG_FIRST) / 2) + 1))
10855 mips_save_restore_reg (word_mode, regno, offset, fn);
10856 offset -= UNITS_PER_WORD;
10860 /* Save register REG to MEM. Make the instruction frame-related. */
10863 mips_save_reg (rtx reg, rtx mem)
10865 if (GET_MODE (reg) == DFmode
10866 && (!TARGET_FLOAT64
10867 || mips_abi == ABI_32))
10871 mips_emit_move_or_split (mem, reg, SPLIT_IF_NECESSARY);
10873 x1 = mips_frame_set (mips_subword (mem, false),
10874 mips_subword (reg, false));
10875 x2 = mips_frame_set (mips_subword (mem, true),
10876 mips_subword (reg, true));
10877 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
10880 mips_emit_save_slot_move (mem, reg, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
10883 /* Capture the register combinations that are allowed in a SWM or LWM
10884 instruction. The entries are ordered by number of registers set in
10885 the mask. We also ignore the single register encodings because a
10886 normal SW/LW is preferred. */
10888 static const unsigned int umips_swm_mask[17] = {
10889 0xc0ff0000, 0x80ff0000, 0x40ff0000, 0x807f0000,
10890 0x00ff0000, 0x803f0000, 0x007f0000, 0x801f0000,
10891 0x003f0000, 0x800f0000, 0x001f0000, 0x80070000,
10892 0x000f0000, 0x80030000, 0x00070000, 0x80010000,
10896 static const unsigned int umips_swm_encoding[17] = {
10897 25, 24, 9, 23, 8, 22, 7, 21, 6, 20, 5, 19, 4, 18, 3, 17, 2
10900 /* Try to use a microMIPS LWM or SWM instruction to save or restore
10901 as many GPRs in *MASK as possible. *OFFSET is the offset from the
10902 stack pointer of the topmost save slot.
10904 Remove from *MASK all registers that were handled using LWM and SWM.
10905 Update *OFFSET so that it points to the first unused save slot. */
10908 umips_build_save_restore (mips_save_restore_fn fn,
10909 unsigned *mask, HOST_WIDE_INT *offset)
10913 rtx pattern, set, reg, mem;
10914 HOST_WIDE_INT this_offset;
10917 /* Try matching $16 to $31 (s0 to ra). */
10918 for (i = 0; i < ARRAY_SIZE (umips_swm_mask); i++)
10919 if ((*mask & 0xffff0000) == umips_swm_mask[i])
10922 if (i == ARRAY_SIZE (umips_swm_mask))
10925 /* Get the offset of the lowest save slot. */
10926 nregs = (umips_swm_encoding[i] & 0xf) + (umips_swm_encoding[i] >> 4);
10927 this_offset = *offset - UNITS_PER_WORD * (nregs - 1);
10929 /* LWM/SWM can only support offsets from -2048 to 2047. */
10930 if (!UMIPS_12BIT_OFFSET_P (this_offset))
10933 /* Create the final PARALLEL. */
10934 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nregs));
10935 this_base = stack_pointer_rtx;
10937 /* For registers $16-$23 and $30. */
10938 for (j = 0; j < (umips_swm_encoding[i] & 0xf); j++)
10940 HOST_WIDE_INT offset = this_offset + j * UNITS_PER_WORD;
10941 mem = gen_frame_mem (SImode, plus_constant (Pmode, this_base, offset));
10942 unsigned int regno = (j != 8) ? 16 + j : 30;
10943 *mask &= ~(1 << regno);
10944 reg = gen_rtx_REG (SImode, regno);
10945 if (fn == mips_save_reg)
10946 set = mips_frame_set (mem, reg);
10949 set = gen_rtx_SET (reg, mem);
10950 mips_add_cfa_restore (reg);
10952 XVECEXP (pattern, 0, j) = set;
10955 /* For register $31. */
10956 if (umips_swm_encoding[i] >> 4)
10958 HOST_WIDE_INT offset = this_offset + j * UNITS_PER_WORD;
10959 *mask &= ~(1 << 31);
10960 mem = gen_frame_mem (SImode, plus_constant (Pmode, this_base, offset));
10961 reg = gen_rtx_REG (SImode, 31);
10962 if (fn == mips_save_reg)
10963 set = mips_frame_set (mem, reg);
10966 set = gen_rtx_SET (reg, mem);
10967 mips_add_cfa_restore (reg);
10969 XVECEXP (pattern, 0, j) = set;
10972 pattern = emit_insn (pattern);
10973 if (fn == mips_save_reg)
10974 RTX_FRAME_RELATED_P (pattern) = 1;
10976 /* Adjust the last offset. */
10977 *offset -= UNITS_PER_WORD * nregs;
10982 /* Call FN for each register that is saved by the current function.
10983 SP_OFFSET is the offset of the current stack pointer from the start
10987 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset,
10988 mips_save_restore_fn fn)
10990 machine_mode fpr_mode;
10992 const struct mips_frame_info *frame = &cfun->machine->frame;
10993 HOST_WIDE_INT offset;
10996 /* Save registers starting from high to low. The debuggers prefer at least
10997 the return register be stored at func+4, and also it allows us not to
10998 need a nop in the epilogue if at least one register is reloaded in
10999 addition to return address. */
11000 offset = frame->gp_sp_offset - sp_offset;
11001 mask = frame->mask;
11003 if (TARGET_MICROMIPS)
11004 umips_build_save_restore (fn, &mask, &offset);
11006 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
11007 if (BITSET_P (mask, regno - GP_REG_FIRST))
11009 /* Record the ra offset for use by mips_function_profiler. */
11010 if (regno == RETURN_ADDR_REGNUM)
11011 cfun->machine->frame.ra_fp_offset = offset + sp_offset;
11012 mips_save_restore_reg (word_mode, regno, offset, fn);
11013 offset -= UNITS_PER_WORD;
11016 /* This loop must iterate over the same space as its companion in
11017 mips_compute_frame_info. */
11018 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
11019 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
11020 for (regno = FP_REG_LAST - MAX_FPRS_PER_FMT + 1;
11021 regno >= FP_REG_FIRST;
11022 regno -= MAX_FPRS_PER_FMT)
11023 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
11025 if (!TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT
11026 && (fixed_regs[regno] || fixed_regs[regno + 1]))
11028 if (fixed_regs[regno])
11029 mips_save_restore_reg (SFmode, regno + 1, offset, fn);
11031 mips_save_restore_reg (SFmode, regno, offset, fn);
11034 mips_save_restore_reg (fpr_mode, regno, offset, fn);
11035 offset -= GET_MODE_SIZE (fpr_mode);
11039 /* Return true if a move between register REGNO and its save slot (MEM)
11040 can be done in a single move. LOAD_P is true if we are loading
11041 from the slot, false if we are storing to it. */
11044 mips_direct_save_slot_move_p (unsigned int regno, rtx mem, bool load_p)
11046 /* There is a specific MIPS16 instruction for saving $31 to the stack. */
11047 if (TARGET_MIPS16 && !load_p && regno == RETURN_ADDR_REGNUM)
11050 return mips_secondary_reload_class (REGNO_REG_CLASS (regno),
11051 GET_MODE (mem), mem, load_p) == NO_REGS;
11054 /* Emit a move from SRC to DEST, given that one of them is a register
11055 save slot and that the other is a register. TEMP is a temporary
11056 GPR of the same mode that is available if need be. */
11059 mips_emit_save_slot_move (rtx dest, rtx src, rtx temp)
11061 unsigned int regno;
11066 regno = REGNO (src);
11071 regno = REGNO (dest);
11075 if (regno == cfun->machine->global_pointer && !mips_must_initialize_gp_p ())
11077 /* We don't yet know whether we'll need this instruction or not.
11078 Postpone the decision by emitting a ghost move. This move
11079 is specifically not frame-related; only the split version is. */
11081 emit_insn (gen_move_gpdi (dest, src));
11083 emit_insn (gen_move_gpsi (dest, src));
11087 if (regno == HI_REGNUM)
11091 mips_emit_move (temp, src);
11093 emit_insn (gen_mthidi_ti (gen_rtx_REG (TImode, MD_REG_FIRST),
11094 temp, gen_rtx_REG (DImode, LO_REGNUM)));
11096 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode, MD_REG_FIRST),
11097 temp, gen_rtx_REG (SImode, LO_REGNUM)));
11102 emit_insn (gen_mfhidi_ti (temp,
11103 gen_rtx_REG (TImode, MD_REG_FIRST)));
11105 emit_insn (gen_mfhisi_di (temp,
11106 gen_rtx_REG (DImode, MD_REG_FIRST)));
11107 mips_emit_move (dest, temp);
11110 else if (mips_direct_save_slot_move_p (regno, mem, mem == src))
11111 mips_emit_move (dest, src);
11114 gcc_assert (!reg_overlap_mentioned_p (dest, temp));
11115 mips_emit_move (temp, src);
11116 mips_emit_move (dest, temp);
11119 mips_set_frame_expr (mips_frame_set (dest, src));
11122 /* If we're generating n32 or n64 abicalls, and the current function
11123 does not use $28 as its global pointer, emit a cplocal directive.
11124 Use pic_offset_table_rtx as the argument to the directive. */
11127 mips_output_cplocal (void)
11129 if (!TARGET_EXPLICIT_RELOCS
11130 && mips_must_initialize_gp_p ()
11131 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
11132 output_asm_insn (".cplocal %+", 0);
11135 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
11138 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
11140 const char *fnname;
11142 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
11143 floating-point arguments. */
11145 && TARGET_HARD_FLOAT_ABI
11146 && crtl->args.info.fp_code != 0)
11147 mips16_build_function_stub ();
11149 /* Get the function name the same way that toplev.c does before calling
11150 assemble_start_function. This is needed so that the name used here
11151 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
11152 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
11153 mips_start_function_definition (fnname, TARGET_MIPS16);
11155 /* Output MIPS-specific frame information. */
11156 if (!flag_inhibit_size_directive)
11158 const struct mips_frame_info *frame;
11160 frame = &cfun->machine->frame;
11162 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
11164 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
11165 "# vars= " HOST_WIDE_INT_PRINT_DEC
11167 ", args= " HOST_WIDE_INT_PRINT_DEC
11168 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
11169 reg_names[frame_pointer_needed
11170 ? HARD_FRAME_POINTER_REGNUM
11171 : STACK_POINTER_REGNUM],
11172 (frame_pointer_needed
11173 ? frame->total_size - frame->hard_frame_pointer_offset
11174 : frame->total_size),
11175 reg_names[RETURN_ADDR_REGNUM],
11177 frame->num_gp, frame->num_fp,
11179 frame->cprestore_size);
11181 /* .mask MASK, OFFSET. */
11182 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
11183 frame->mask, frame->gp_save_offset);
11185 /* .fmask MASK, OFFSET. */
11186 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
11187 frame->fmask, frame->fp_save_offset);
11190 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
11191 Also emit the ".set noreorder; .set nomacro" sequence for functions
11193 if (mips_must_initialize_gp_p ()
11194 && mips_current_loadgp_style () == LOADGP_OLDABI)
11198 /* This is a fixed-form sequence. The position of the
11199 first two instructions is important because of the
11200 way _gp_disp is defined. */
11201 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
11202 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
11203 output_asm_insn ("sll\t$2,16", 0);
11204 output_asm_insn ("addu\t$2,$3", 0);
11208 /* .cpload must be in a .set noreorder but not a
11209 .set nomacro block. */
11210 mips_push_asm_switch (&mips_noreorder);
11211 output_asm_insn (".cpload\t%^", 0);
11212 if (!cfun->machine->all_noreorder_p)
11213 mips_pop_asm_switch (&mips_noreorder);
11215 mips_push_asm_switch (&mips_nomacro);
11218 else if (cfun->machine->all_noreorder_p)
11220 mips_push_asm_switch (&mips_noreorder);
11221 mips_push_asm_switch (&mips_nomacro);
11224 /* Tell the assembler which register we're using as the global
11225 pointer. This is needed for thunks, since they can use either
11226 explicit relocs or assembler macros. */
11227 mips_output_cplocal ();
11230 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
11233 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
11234 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
11236 const char *fnname;
11238 /* Reinstate the normal $gp. */
11239 SET_REGNO (pic_offset_table_rtx, GLOBAL_POINTER_REGNUM);
11240 mips_output_cplocal ();
11242 if (cfun->machine->all_noreorder_p)
11244 mips_pop_asm_switch (&mips_nomacro);
11245 mips_pop_asm_switch (&mips_noreorder);
11248 /* Get the function name the same way that toplev.c does before calling
11249 assemble_start_function. This is needed so that the name used here
11250 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
11251 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
11252 mips_end_function_definition (fnname);
11255 /* Emit an optimisation barrier for accesses to the current frame. */
11258 mips_frame_barrier (void)
11260 emit_clobber (gen_frame_mem (BLKmode, stack_pointer_rtx));
11264 /* The __gnu_local_gp symbol. */
11266 static GTY(()) rtx mips_gnu_local_gp;
11268 /* If we're generating n32 or n64 abicalls, emit instructions
11269 to set up the global pointer. */
11272 mips_emit_loadgp (void)
11274 rtx addr, offset, incoming_address, base, index, pic_reg;
11276 pic_reg = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
11277 switch (mips_current_loadgp_style ())
11279 case LOADGP_ABSOLUTE:
11280 if (mips_gnu_local_gp == NULL)
11282 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
11283 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
11285 emit_insn (PMODE_INSN (gen_loadgp_absolute,
11286 (pic_reg, mips_gnu_local_gp)));
11289 case LOADGP_OLDABI:
11290 /* Added by mips_output_function_prologue. */
11293 case LOADGP_NEWABI:
11294 addr = XEXP (DECL_RTL (current_function_decl), 0);
11295 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
11296 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
11297 emit_insn (PMODE_INSN (gen_loadgp_newabi,
11298 (pic_reg, offset, incoming_address)));
11302 base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE));
11303 index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX));
11304 emit_insn (PMODE_INSN (gen_loadgp_rtp, (pic_reg, base, index)));
11312 emit_insn (PMODE_INSN (gen_copygp_mips16,
11313 (pic_offset_table_rtx, pic_reg)));
11315 /* Emit a blockage if there are implicit uses of the GP register.
11316 This includes profiled functions, because FUNCTION_PROFILE uses
11318 if (!TARGET_EXPLICIT_RELOCS || crtl->profile)
11319 emit_insn (gen_loadgp_blockage ());
11322 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
11324 #if PROBE_INTERVAL > 32768
11325 #error Cannot use indexed addressing mode for stack probing
11328 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
11329 inclusive. These are offsets from the current stack pointer. */
11332 mips_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size)
11335 sorry ("-fstack-check=specific not implemented for MIPS16");
11337 /* See if we have a constant small number of probes to generate. If so,
11338 that's the easy case. */
11339 if (first + size <= 32768)
11343 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
11344 it exceeds SIZE. If only one probe is needed, this will not
11345 generate any code. Then probe at FIRST + SIZE. */
11346 for (i = PROBE_INTERVAL; i < size; i += PROBE_INTERVAL)
11347 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
11350 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
11354 /* Otherwise, do the same as above, but in a loop. Note that we must be
11355 extra careful with variables wrapping around because we might be at
11356 the very top (or the very bottom) of the address space and we have
11357 to be able to handle this case properly; in particular, we use an
11358 equality test for the loop condition. */
11361 HOST_WIDE_INT rounded_size;
11362 rtx r3 = MIPS_PROLOGUE_TEMP (Pmode);
11363 rtx r12 = MIPS_PROLOGUE_TEMP2 (Pmode);
11365 /* Sanity check for the addressing mode we're going to use. */
11366 gcc_assert (first <= 32768);
11369 /* Step 1: round SIZE to the previous multiple of the interval. */
11371 rounded_size = ROUND_DOWN (size, PROBE_INTERVAL);
11374 /* Step 2: compute initial and final value of the loop counter. */
11376 /* TEST_ADDR = SP + FIRST. */
11377 emit_insn (gen_rtx_SET (r3, plus_constant (Pmode, stack_pointer_rtx,
11380 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
11381 if (rounded_size > 32768)
11383 emit_move_insn (r12, GEN_INT (rounded_size));
11384 emit_insn (gen_rtx_SET (r12, gen_rtx_MINUS (Pmode, r3, r12)));
11387 emit_insn (gen_rtx_SET (r12, plus_constant (Pmode, r3,
11391 /* Step 3: the loop
11395 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
11398 while (TEST_ADDR != LAST_ADDR)
11400 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
11401 until it is equal to ROUNDED_SIZE. */
11403 emit_insn (PMODE_INSN (gen_probe_stack_range, (r3, r3, r12)));
11406 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
11407 that SIZE is equal to ROUNDED_SIZE. */
11409 if (size != rounded_size)
11410 emit_stack_probe (plus_constant (Pmode, r12, rounded_size - size));
11413 /* Make sure nothing is scheduled before we are done. */
11414 emit_insn (gen_blockage ());
11417 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
11418 absolute addresses. */
11421 mips_output_probe_stack_range (rtx reg1, rtx reg2)
11423 static int labelno = 0;
11424 char loop_lab[32], tmp[64];
11427 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno++);
11430 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
11432 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
11434 xops[1] = GEN_INT (-PROBE_INTERVAL);
11435 if (TARGET_64BIT && TARGET_LONG64)
11436 output_asm_insn ("daddiu\t%0,%0,%1", xops);
11438 output_asm_insn ("addiu\t%0,%0,%1", xops);
11440 /* Probe at TEST_ADDR, test if TEST_ADDR == LAST_ADDR and branch. */
11442 strcpy (tmp, "%(%<bne\t%0,%1,");
11443 output_asm_insn (strcat (tmp, &loop_lab[1]), xops);
11445 output_asm_insn ("sd\t$0,0(%0)%)", xops);
11447 output_asm_insn ("sw\t$0,0(%0)%)", xops);
11452 /* Return true if X contains a kernel register. */
11455 mips_refers_to_kernel_reg_p (const_rtx x)
11457 subrtx_iterator::array_type array;
11458 FOR_EACH_SUBRTX (iter, array, x, NONCONST)
11459 if (REG_P (*iter) && KERNEL_REG_P (REGNO (*iter)))
11464 /* Expand the "prologue" pattern. */
11467 mips_expand_prologue (void)
11469 const struct mips_frame_info *frame;
11470 HOST_WIDE_INT size;
11471 unsigned int nargs;
11473 if (cfun->machine->global_pointer != INVALID_REGNUM)
11475 /* Check whether an insn uses pic_offset_table_rtx, either explicitly
11476 or implicitly. If so, we can commit to using a global pointer
11477 straight away, otherwise we need to defer the decision. */
11478 if (mips_cfun_has_inflexible_gp_ref_p ()
11479 || mips_cfun_has_flexible_gp_ref_p ())
11481 cfun->machine->must_initialize_gp_p = true;
11482 cfun->machine->must_restore_gp_when_clobbered_p = true;
11485 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
11488 frame = &cfun->machine->frame;
11489 size = frame->total_size;
11491 if (flag_stack_usage_info)
11492 current_function_static_stack_size = size;
11494 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK)
11496 if (crtl->is_leaf && !cfun->calls_alloca)
11498 if (size > PROBE_INTERVAL && size > STACK_CHECK_PROTECT)
11499 mips_emit_probe_stack_range (STACK_CHECK_PROTECT,
11500 size - STACK_CHECK_PROTECT);
11503 mips_emit_probe_stack_range (STACK_CHECK_PROTECT, size);
11506 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
11507 bytes beforehand; this is enough to cover the register save area
11508 without going out of range. */
11509 if (((frame->mask | frame->fmask | frame->acc_mask) != 0)
11510 || frame->num_cop0_regs > 0)
11512 HOST_WIDE_INT step1;
11514 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
11515 if (GENERATE_MIPS16E_SAVE_RESTORE)
11517 HOST_WIDE_INT offset;
11518 unsigned int mask, regno;
11520 /* Try to merge argument stores into the save instruction. */
11521 nargs = mips16e_collect_argument_saves ();
11523 /* Build the save instruction. */
11524 mask = frame->mask;
11525 rtx insn = mips16e_build_save_restore (false, &mask, &offset,
11527 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
11528 mips_frame_barrier ();
11531 /* Check if we need to save other registers. */
11532 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
11533 if (BITSET_P (mask, regno - GP_REG_FIRST))
11535 offset -= UNITS_PER_WORD;
11536 mips_save_restore_reg (word_mode, regno,
11537 offset, mips_save_reg);
11542 if (cfun->machine->interrupt_handler_p)
11544 HOST_WIDE_INT offset;
11547 /* If this interrupt is using a shadow register set, we need to
11548 get the stack pointer from the previous register set. */
11549 if (cfun->machine->use_shadow_register_set == SHADOW_SET_YES)
11550 emit_insn (PMODE_INSN (gen_mips_rdpgpr, (stack_pointer_rtx,
11551 stack_pointer_rtx)));
11553 if (!cfun->machine->keep_interrupts_masked_p)
11555 if (cfun->machine->int_mask == INT_MASK_EIC)
11556 /* Move from COP0 Cause to K0. */
11557 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K0_REG_NUM),
11558 gen_rtx_REG (SImode, COP0_CAUSE_REG_NUM)));
11560 /* Move from COP0 EPC to K1. */
11561 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
11562 gen_rtx_REG (SImode,
11563 COP0_EPC_REG_NUM)));
11565 /* Allocate the first part of the frame. */
11566 rtx insn = gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx,
11568 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
11569 mips_frame_barrier ();
11572 /* Start at the uppermost location for saving. */
11573 offset = frame->cop0_sp_offset - size;
11575 /* Push EPC into its stack slot. */
11576 mem = gen_frame_mem (word_mode,
11577 plus_constant (Pmode, stack_pointer_rtx,
11579 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
11580 offset -= UNITS_PER_WORD;
11582 /* Move from COP0 Status to K1. */
11583 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
11584 gen_rtx_REG (SImode,
11585 COP0_STATUS_REG_NUM)));
11587 /* Right justify the RIPL in k0. */
11588 if (!cfun->machine->keep_interrupts_masked_p
11589 && cfun->machine->int_mask == INT_MASK_EIC)
11590 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode, K0_REG_NUM),
11591 gen_rtx_REG (SImode, K0_REG_NUM),
11592 GEN_INT (CAUSE_IPL)));
11594 /* Push Status into its stack slot. */
11595 mem = gen_frame_mem (word_mode,
11596 plus_constant (Pmode, stack_pointer_rtx,
11598 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
11599 offset -= UNITS_PER_WORD;
11601 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
11602 if (!cfun->machine->keep_interrupts_masked_p
11603 && cfun->machine->int_mask == INT_MASK_EIC)
11604 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
11607 gen_rtx_REG (SImode, K0_REG_NUM)));
11609 /* Clear all interrupt mask bits up to and including the
11610 handler's interrupt line. */
11611 if (!cfun->machine->keep_interrupts_masked_p
11612 && cfun->machine->int_mask != INT_MASK_EIC)
11613 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
11614 GEN_INT (cfun->machine->int_mask + 1),
11616 gen_rtx_REG (SImode, GP_REG_FIRST)));
11618 if (!cfun->machine->keep_interrupts_masked_p)
11619 /* Enable interrupts by clearing the KSU ERL and EXL bits.
11620 IE is already the correct value, so we don't have to do
11621 anything explicit. */
11622 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
11625 gen_rtx_REG (SImode, GP_REG_FIRST)));
11627 /* Disable interrupts by clearing the KSU, ERL, EXL,
11629 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
11632 gen_rtx_REG (SImode, GP_REG_FIRST)));
11634 if (TARGET_HARD_FLOAT)
11635 /* Disable COP1 for hard-float. This will lead to an exception
11636 if floating-point code is executed in an ISR. */
11637 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
11640 gen_rtx_REG (SImode, GP_REG_FIRST)));
11646 rtx insn = gen_add3_insn (stack_pointer_rtx,
11649 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
11650 mips_frame_barrier ();
11654 mips_for_each_saved_acc (size, mips_save_reg);
11655 mips_for_each_saved_gpr_and_fpr (size, mips_save_reg);
11659 /* Allocate the rest of the frame. */
11662 if (SMALL_OPERAND (-size))
11663 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
11665 GEN_INT (-size)))) = 1;
11668 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
11671 /* There are no instructions to add or subtract registers
11672 from the stack pointer, so use the frame pointer as a
11673 temporary. We should always be using a frame pointer
11674 in this case anyway. */
11675 gcc_assert (frame_pointer_needed);
11676 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
11677 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
11678 hard_frame_pointer_rtx,
11679 MIPS_PROLOGUE_TEMP (Pmode)));
11680 mips_emit_move (stack_pointer_rtx, hard_frame_pointer_rtx);
11683 emit_insn (gen_sub3_insn (stack_pointer_rtx,
11685 MIPS_PROLOGUE_TEMP (Pmode)));
11687 /* Describe the combined effect of the previous instructions. */
11688 mips_set_frame_expr
11689 (gen_rtx_SET (stack_pointer_rtx,
11690 plus_constant (Pmode, stack_pointer_rtx, -size)));
11692 mips_frame_barrier ();
11695 /* Set up the frame pointer, if we're using one. */
11696 if (frame_pointer_needed)
11698 HOST_WIDE_INT offset;
11700 offset = frame->hard_frame_pointer_offset;
11703 rtx insn = mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
11704 RTX_FRAME_RELATED_P (insn) = 1;
11706 else if (SMALL_OPERAND (offset))
11708 rtx insn = gen_add3_insn (hard_frame_pointer_rtx,
11709 stack_pointer_rtx, GEN_INT (offset));
11710 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
11714 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (offset));
11715 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
11716 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
11717 hard_frame_pointer_rtx,
11718 MIPS_PROLOGUE_TEMP (Pmode)));
11719 mips_set_frame_expr
11720 (gen_rtx_SET (hard_frame_pointer_rtx,
11721 plus_constant (Pmode, stack_pointer_rtx, offset)));
11725 mips_emit_loadgp ();
11727 /* Initialize the $gp save slot. */
11728 if (mips_cfun_has_cprestore_slot_p ())
11730 rtx base, mem, gp, temp;
11731 HOST_WIDE_INT offset;
11733 mips_get_cprestore_base_and_offset (&base, &offset, false);
11734 mem = gen_frame_mem (Pmode, plus_constant (Pmode, base, offset));
11735 gp = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
11736 temp = (SMALL_OPERAND (offset)
11737 ? gen_rtx_SCRATCH (Pmode)
11738 : MIPS_PROLOGUE_TEMP (Pmode));
11739 emit_insn (PMODE_INSN (gen_potential_cprestore,
11740 (mem, GEN_INT (offset), gp, temp)));
11742 mips_get_cprestore_base_and_offset (&base, &offset, true);
11743 mem = gen_frame_mem (Pmode, plus_constant (Pmode, base, offset));
11744 emit_insn (PMODE_INSN (gen_use_cprestore, (mem)));
11747 /* We need to search back to the last use of K0 or K1. */
11748 if (cfun->machine->interrupt_handler_p)
11751 for (insn = get_last_insn (); insn != NULL_RTX; insn = PREV_INSN (insn))
11753 && mips_refers_to_kernel_reg_p (PATTERN (insn)))
11755 /* Emit a move from K1 to COP0 Status after insn. */
11756 gcc_assert (insn != NULL_RTX);
11757 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
11758 gen_rtx_REG (SImode, K1_REG_NUM)),
11762 /* If we are profiling, make sure no instructions are scheduled before
11763 the call to mcount. */
11765 emit_insn (gen_blockage ());
11768 /* Attach all pending register saves to the previous instruction.
11769 Return that instruction. */
11772 mips_epilogue_emit_cfa_restores (void)
11776 insn = get_last_insn ();
11777 if (mips_epilogue.cfa_restores)
11779 gcc_assert (insn && !REG_NOTES (insn));
11780 RTX_FRAME_RELATED_P (insn) = 1;
11781 REG_NOTES (insn) = mips_epilogue.cfa_restores;
11782 mips_epilogue.cfa_restores = 0;
11787 /* Like mips_epilogue_emit_cfa_restores, but also record that the CFA is
11788 now at REG + OFFSET. */
11791 mips_epilogue_set_cfa (rtx reg, HOST_WIDE_INT offset)
11795 insn = mips_epilogue_emit_cfa_restores ();
11796 if (reg != mips_epilogue.cfa_reg || offset != mips_epilogue.cfa_offset)
11798 RTX_FRAME_RELATED_P (insn) = 1;
11799 REG_NOTES (insn) = alloc_reg_note (REG_CFA_DEF_CFA,
11800 plus_constant (Pmode, reg, offset),
11802 mips_epilogue.cfa_reg = reg;
11803 mips_epilogue.cfa_offset = offset;
11807 /* Emit instructions to restore register REG from slot MEM. Also update
11808 the cfa_restores list. */
11811 mips_restore_reg (rtx reg, rtx mem)
11813 /* There's no MIPS16 instruction to load $31 directly. Load into
11814 $7 instead and adjust the return insn appropriately. */
11815 if (TARGET_MIPS16 && REGNO (reg) == RETURN_ADDR_REGNUM)
11816 reg = gen_rtx_REG (GET_MODE (reg), GP_REG_FIRST + 7);
11817 else if (GET_MODE (reg) == DFmode
11818 && (!TARGET_FLOAT64
11819 || mips_abi == ABI_32))
11821 mips_add_cfa_restore (mips_subword (reg, true));
11822 mips_add_cfa_restore (mips_subword (reg, false));
11825 mips_add_cfa_restore (reg);
11827 mips_emit_save_slot_move (reg, mem, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
11828 if (REGNO (reg) == REGNO (mips_epilogue.cfa_reg))
11829 /* The CFA is currently defined in terms of the register whose
11830 value we have just restored. Redefine the CFA in terms of
11831 the stack pointer. */
11832 mips_epilogue_set_cfa (stack_pointer_rtx,
11833 mips_epilogue.cfa_restore_sp_offset);
11836 /* Emit code to set the stack pointer to BASE + OFFSET, given that
11837 BASE + OFFSET is NEW_FRAME_SIZE bytes below the top of the frame.
11838 BASE, if not the stack pointer, is available as a temporary. */
11841 mips_deallocate_stack (rtx base, rtx offset, HOST_WIDE_INT new_frame_size)
11843 if (base == stack_pointer_rtx && offset == const0_rtx)
11846 mips_frame_barrier ();
11847 if (offset == const0_rtx)
11849 emit_move_insn (stack_pointer_rtx, base);
11850 mips_epilogue_set_cfa (stack_pointer_rtx, new_frame_size);
11852 else if (TARGET_MIPS16 && base != stack_pointer_rtx)
11854 emit_insn (gen_add3_insn (base, base, offset));
11855 mips_epilogue_set_cfa (base, new_frame_size);
11856 emit_move_insn (stack_pointer_rtx, base);
11860 emit_insn (gen_add3_insn (stack_pointer_rtx, base, offset));
11861 mips_epilogue_set_cfa (stack_pointer_rtx, new_frame_size);
11865 /* Emit any instructions needed before a return. */
11868 mips_expand_before_return (void)
11870 /* When using a call-clobbered gp, we start out with unified call
11871 insns that include instructions to restore the gp. We then split
11872 these unified calls after reload. These split calls explicitly
11873 clobber gp, so there is no need to define
11874 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
11876 For consistency, we should also insert an explicit clobber of $28
11877 before return insns, so that the post-reload optimizers know that
11878 the register is not live on exit. */
11879 if (TARGET_CALL_CLOBBERED_GP)
11880 emit_clobber (pic_offset_table_rtx);
11883 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
11887 mips_expand_epilogue (bool sibcall_p)
11889 const struct mips_frame_info *frame;
11890 HOST_WIDE_INT step1, step2;
11893 bool use_jraddiusp_p = false;
11895 if (!sibcall_p && mips_can_use_return_insn ())
11897 emit_jump_insn (gen_return ());
11901 /* In MIPS16 mode, if the return value should go into a floating-point
11902 register, we need to call a helper routine to copy it over. */
11903 if (mips16_cfun_returns_in_fpr_p ())
11904 mips16_copy_fpr_return_value ();
11906 /* Split the frame into two. STEP1 is the amount of stack we should
11907 deallocate before restoring the registers. STEP2 is the amount we
11908 should deallocate afterwards.
11910 Start off by assuming that no registers need to be restored. */
11911 frame = &cfun->machine->frame;
11912 step1 = frame->total_size;
11915 /* Work out which register holds the frame address. */
11916 if (!frame_pointer_needed)
11917 base = stack_pointer_rtx;
11920 base = hard_frame_pointer_rtx;
11921 step1 -= frame->hard_frame_pointer_offset;
11923 mips_epilogue.cfa_reg = base;
11924 mips_epilogue.cfa_offset = step1;
11925 mips_epilogue.cfa_restores = NULL_RTX;
11927 /* If we need to restore registers, deallocate as much stack as
11928 possible in the second step without going out of range. */
11929 if ((frame->mask | frame->fmask | frame->acc_mask) != 0
11930 || frame->num_cop0_regs > 0)
11932 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
11936 /* Get an rtx for STEP1 that we can add to BASE. */
11937 adjust = GEN_INT (step1);
11938 if (!SMALL_OPERAND (step1))
11940 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), adjust);
11941 adjust = MIPS_EPILOGUE_TEMP (Pmode);
11943 mips_deallocate_stack (base, adjust, step2);
11945 /* If we're using addressing macros, $gp is implicitly used by all
11946 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
11948 if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS)
11949 emit_insn (gen_blockage ());
11951 mips_epilogue.cfa_restore_sp_offset = step2;
11952 if (GENERATE_MIPS16E_SAVE_RESTORE && frame->mask != 0)
11954 unsigned int regno, mask;
11955 HOST_WIDE_INT offset;
11958 /* Generate the restore instruction. */
11959 mask = frame->mask;
11960 restore = mips16e_build_save_restore (true, &mask, &offset, 0, step2);
11962 /* Restore any other registers manually. */
11963 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
11964 if (BITSET_P (mask, regno - GP_REG_FIRST))
11966 offset -= UNITS_PER_WORD;
11967 mips_save_restore_reg (word_mode, regno, offset, mips_restore_reg);
11970 /* Restore the remaining registers and deallocate the final bit
11972 mips_frame_barrier ();
11973 emit_insn (restore);
11974 mips_epilogue_set_cfa (stack_pointer_rtx, 0);
11978 /* Restore the registers. */
11979 mips_for_each_saved_acc (frame->total_size - step2, mips_restore_reg);
11980 mips_for_each_saved_gpr_and_fpr (frame->total_size - step2,
11983 if (cfun->machine->interrupt_handler_p)
11985 HOST_WIDE_INT offset;
11988 offset = frame->cop0_sp_offset - (frame->total_size - step2);
11990 /* Restore the original EPC. */
11991 mem = gen_frame_mem (word_mode,
11992 plus_constant (Pmode, stack_pointer_rtx,
11994 mips_emit_move (gen_rtx_REG (word_mode, K1_REG_NUM), mem);
11995 offset -= UNITS_PER_WORD;
11997 /* Move to COP0 EPC. */
11998 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_EPC_REG_NUM),
11999 gen_rtx_REG (SImode, K1_REG_NUM)));
12001 /* Restore the original Status. */
12002 mem = gen_frame_mem (word_mode,
12003 plus_constant (Pmode, stack_pointer_rtx,
12005 mips_emit_move (gen_rtx_REG (word_mode, K1_REG_NUM), mem);
12006 offset -= UNITS_PER_WORD;
12008 /* If we don't use shadow register set, we need to update SP. */
12009 if (cfun->machine->use_shadow_register_set == SHADOW_SET_NO)
12010 mips_deallocate_stack (stack_pointer_rtx, GEN_INT (step2), 0);
12012 /* The choice of position is somewhat arbitrary in this case. */
12013 mips_epilogue_emit_cfa_restores ();
12015 /* Move to COP0 Status. */
12016 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
12017 gen_rtx_REG (SImode, K1_REG_NUM)));
12019 else if (TARGET_MICROMIPS
12020 && !crtl->calls_eh_return
12023 && mips_unsigned_immediate_p (step2, 5, 2))
12024 use_jraddiusp_p = true;
12026 /* Deallocate the final bit of the frame. */
12027 mips_deallocate_stack (stack_pointer_rtx, GEN_INT (step2), 0);
12030 if (cfun->machine->use_frame_header_for_callee_saved_regs)
12031 mips_epilogue_emit_cfa_restores ();
12032 else if (!use_jraddiusp_p)
12033 gcc_assert (!mips_epilogue.cfa_restores);
12035 /* Add in the __builtin_eh_return stack adjustment. We need to
12036 use a temporary in MIPS16 code. */
12037 if (crtl->calls_eh_return)
12041 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
12042 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
12043 MIPS_EPILOGUE_TEMP (Pmode),
12044 EH_RETURN_STACKADJ_RTX));
12045 mips_emit_move (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
12048 emit_insn (gen_add3_insn (stack_pointer_rtx,
12050 EH_RETURN_STACKADJ_RTX));
12055 mips_expand_before_return ();
12056 if (cfun->machine->interrupt_handler_p)
12058 /* Interrupt handlers generate eret or deret. */
12059 if (cfun->machine->use_debug_exception_return_p)
12060 emit_jump_insn (gen_mips_deret ());
12062 emit_jump_insn (gen_mips_eret ());
12068 /* When generating MIPS16 code, the normal
12069 mips_for_each_saved_gpr_and_fpr path will restore the return
12070 address into $7 rather than $31. */
12072 && !GENERATE_MIPS16E_SAVE_RESTORE
12073 && BITSET_P (frame->mask, RETURN_ADDR_REGNUM))
12075 /* simple_returns cannot rely on values that are only available
12076 on paths through the epilogue (because return paths that do
12077 not pass through the epilogue may nevertheless reuse a
12078 simple_return that occurs at the end of the epilogue).
12079 Use a normal return here instead. */
12080 rtx reg = gen_rtx_REG (Pmode, GP_REG_FIRST + 7);
12081 pat = gen_return_internal (reg);
12083 else if (use_jraddiusp_p)
12084 pat = gen_jraddiusp (GEN_INT (step2));
12087 rtx reg = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
12088 pat = gen_simple_return_internal (reg);
12090 emit_jump_insn (pat);
12091 if (use_jraddiusp_p)
12092 mips_epilogue_set_cfa (stack_pointer_rtx, step2);
12096 /* Search from the beginning to the first use of K0 or K1. */
12097 if (cfun->machine->interrupt_handler_p
12098 && !cfun->machine->keep_interrupts_masked_p)
12100 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
12102 && mips_refers_to_kernel_reg_p (PATTERN (insn)))
12104 gcc_assert (insn != NULL_RTX);
12105 /* Insert disable interrupts before the first use of K0 or K1. */
12106 emit_insn_before (gen_mips_di (), insn);
12107 emit_insn_before (gen_mips_ehb (), insn);
12111 /* Return nonzero if this function is known to have a null epilogue.
12112 This allows the optimizer to omit jumps to jumps if no stack
12116 mips_can_use_return_insn (void)
12118 /* Interrupt handlers need to go through the epilogue. */
12119 if (cfun->machine->interrupt_handler_p)
12122 if (!reload_completed)
12128 /* In MIPS16 mode, a function that returns a floating-point value
12129 needs to arrange to copy the return value into the floating-point
12131 if (mips16_cfun_returns_in_fpr_p ())
12134 return (cfun->machine->frame.total_size == 0
12135 && !cfun->machine->use_frame_header_for_callee_saved_regs);
12138 /* Return true if register REGNO can store a value of mode MODE.
12139 The result of this function is cached in mips_hard_regno_mode_ok. */
12142 mips_hard_regno_mode_ok_p (unsigned int regno, machine_mode mode)
12145 enum mode_class mclass;
12147 if (mode == CCV2mode)
12148 return (ISA_HAS_8CC
12149 && ST_REG_P (regno)
12150 && (regno - ST_REG_FIRST) % 2 == 0);
12152 if (mode == CCV4mode)
12153 return (ISA_HAS_8CC
12154 && ST_REG_P (regno)
12155 && (regno - ST_REG_FIRST) % 4 == 0);
12157 if (mode == CCmode)
12158 return ISA_HAS_8CC ? ST_REG_P (regno) : regno == FPSW_REGNUM;
12160 size = GET_MODE_SIZE (mode);
12161 mclass = GET_MODE_CLASS (mode);
12163 if (GP_REG_P (regno) && mode != CCFmode)
12164 return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD;
12166 if (FP_REG_P (regno)
12167 && (((regno - FP_REG_FIRST) % MAX_FPRS_PER_FMT) == 0
12168 || (MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG)))
12170 /* Deny use of odd-numbered registers for 32-bit data for
12171 the o32 FP64A ABI. */
12172 if (TARGET_O32_FP64A_ABI && size <= 4 && (regno & 1) != 0)
12175 /* The FPXX ABI requires double-precision values to be placed in
12176 even-numbered registers. Disallow odd-numbered registers with
12177 CCFmode because CCFmode double-precision compares will write a
12178 64-bit value to a register. */
12179 if (mode == CCFmode)
12180 return !(TARGET_FLOATXX && (regno & 1) != 0);
12182 /* Allow 64-bit vector modes for Loongson-2E/2F. */
12183 if (TARGET_LOONGSON_VECTORS
12184 && (mode == V2SImode
12185 || mode == V4HImode
12186 || mode == V8QImode
12187 || mode == DImode))
12190 if (mclass == MODE_FLOAT
12191 || mclass == MODE_COMPLEX_FLOAT
12192 || mclass == MODE_VECTOR_FLOAT)
12193 return size <= UNITS_PER_FPVALUE;
12195 /* Allow integer modes that fit into a single register. We need
12196 to put integers into FPRs when using instructions like CVT
12197 and TRUNC. There's no point allowing sizes smaller than a word,
12198 because the FPU has no appropriate load/store instructions. */
12199 if (mclass == MODE_INT)
12200 return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG;
12203 /* Don't allow vector modes in accumulators. */
12204 if (ACC_REG_P (regno)
12205 && !VECTOR_MODE_P (mode)
12206 && (INTEGRAL_MODE_P (mode) || ALL_FIXED_POINT_MODE_P (mode)))
12208 if (MD_REG_P (regno))
12210 /* After a multiplication or division, clobbering HI makes
12211 the value of LO unpredictable, and vice versa. This means
12212 that, for all interesting cases, HI and LO are effectively
12215 We model this by requiring that any value that uses HI
12217 if (size <= UNITS_PER_WORD * 2)
12218 return regno == (size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST);
12222 /* DSP accumulators do not have the same restrictions as
12223 HI and LO, so we can treat them as normal doubleword
12225 if (size <= UNITS_PER_WORD)
12228 if (size <= UNITS_PER_WORD * 2
12229 && ((regno - DSP_ACC_REG_FIRST) & 1) == 0)
12234 if (ALL_COP_REG_P (regno))
12235 return mclass == MODE_INT && size <= UNITS_PER_WORD;
12237 if (regno == GOT_VERSION_REGNUM)
12238 return mode == SImode;
12243 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
12246 mips_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
12247 unsigned int new_reg)
12249 /* Interrupt functions can only use registers that have already been
12250 saved by the prologue, even if they would normally be call-clobbered. */
12251 if (cfun->machine->interrupt_handler_p && !df_regs_ever_live_p (new_reg))
12257 /* Return nonzero if register REGNO can be used as a scratch register
12261 mips_hard_regno_scratch_ok (unsigned int regno)
12263 /* See mips_hard_regno_rename_ok. */
12264 if (cfun->machine->interrupt_handler_p && !df_regs_ever_live_p (regno))
12270 /* Implement HARD_REGNO_NREGS. */
12273 mips_hard_regno_nregs (int regno, machine_mode mode)
12275 if (ST_REG_P (regno))
12276 /* The size of FP status registers is always 4, because they only hold
12277 CCmode values, and CCmode is always considered to be 4 bytes wide. */
12278 return (GET_MODE_SIZE (mode) + 3) / 4;
12280 if (FP_REG_P (regno))
12281 return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG;
12283 /* All other registers are word-sized. */
12284 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
12287 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
12288 in mips_hard_regno_nregs. */
12291 mips_class_max_nregs (enum reg_class rclass, machine_mode mode)
12297 COPY_HARD_REG_SET (left, reg_class_contents[(int) rclass]);
12298 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS]))
12300 if (HARD_REGNO_MODE_OK (ST_REG_FIRST, mode))
12301 size = MIN (size, 4);
12302 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) ST_REGS]);
12304 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS]))
12306 if (HARD_REGNO_MODE_OK (FP_REG_FIRST, mode))
12307 size = MIN (size, UNITS_PER_FPREG);
12308 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]);
12310 if (!hard_reg_set_empty_p (left))
12311 size = MIN (size, UNITS_PER_WORD);
12312 return (GET_MODE_SIZE (mode) + size - 1) / size;
12315 /* Implement CANNOT_CHANGE_MODE_CLASS. */
12318 mips_cannot_change_mode_class (machine_mode from,
12320 enum reg_class rclass)
12322 /* Allow conversions between different Loongson integer vectors,
12323 and between those vectors and DImode. */
12324 if (GET_MODE_SIZE (from) == 8 && GET_MODE_SIZE (to) == 8
12325 && INTEGRAL_MODE_P (from) && INTEGRAL_MODE_P (to))
12328 /* Otherwise, there are several problems with changing the modes of
12329 values in floating-point registers:
12331 - When a multi-word value is stored in paired floating-point
12332 registers, the first register always holds the low word. We
12333 therefore can't allow FPRs to change between single-word and
12334 multi-word modes on big-endian targets.
12336 - GCC assumes that each word of a multiword register can be
12337 accessed individually using SUBREGs. This is not true for
12338 floating-point registers if they are bigger than a word.
12340 - Loading a 32-bit value into a 64-bit floating-point register
12341 will not sign-extend the value, despite what LOAD_EXTEND_OP
12342 says. We can't allow FPRs to change from SImode to a wider
12343 mode on 64-bit targets.
12345 - If the FPU has already interpreted a value in one format, we
12346 must not ask it to treat the value as having a different
12349 We therefore disallow all mode changes involving FPRs. */
12351 return reg_classes_intersect_p (FP_REGS, rclass);
12354 /* Implement target hook small_register_classes_for_mode_p. */
12357 mips_small_register_classes_for_mode_p (machine_mode mode
12360 return TARGET_MIPS16;
12363 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
12366 mips_mode_ok_for_mov_fmt_p (machine_mode mode)
12372 return TARGET_HARD_FLOAT;
12375 return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT;
12378 return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT;
12385 /* Implement MODES_TIEABLE_P. */
12388 mips_modes_tieable_p (machine_mode mode1, machine_mode mode2)
12390 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
12391 prefer to put one of them in FPRs. */
12392 return (mode1 == mode2
12393 || (!mips_mode_ok_for_mov_fmt_p (mode1)
12394 && !mips_mode_ok_for_mov_fmt_p (mode2)));
12397 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
12400 mips_preferred_reload_class (rtx x, reg_class_t rclass)
12402 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, rclass))
12405 if (reg_class_subset_p (FP_REGS, rclass)
12406 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x)))
12409 if (reg_class_subset_p (GR_REGS, rclass))
12412 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, rclass))
12418 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
12419 Return a "canonical" class to represent it in later calculations. */
12422 mips_canonicalize_move_class (reg_class_t rclass)
12424 /* All moves involving accumulator registers have the same cost. */
12425 if (reg_class_subset_p (rclass, ACC_REGS))
12428 /* Likewise promote subclasses of general registers to the most
12429 interesting containing class. */
12430 if (TARGET_MIPS16 && reg_class_subset_p (rclass, M16_REGS))
12432 else if (reg_class_subset_p (rclass, GENERAL_REGS))
12433 rclass = GENERAL_REGS;
12438 /* Return the cost of moving a value from a register of class FROM to a GPR.
12439 Return 0 for classes that are unions of other classes handled by this
12443 mips_move_to_gpr_cost (reg_class_t from)
12449 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
12453 /* MFLO and MFHI. */
12463 /* This choice of value is historical. */
12471 /* Return the cost of moving a value from a GPR to a register of class TO.
12472 Return 0 for classes that are unions of other classes handled by this
12476 mips_move_from_gpr_cost (reg_class_t to)
12482 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
12486 /* MTLO and MTHI. */
12496 /* This choice of value is historical. */
12504 /* Implement TARGET_REGISTER_MOVE_COST. Return 0 for classes that are the
12505 maximum of the move costs for subclasses; regclass will work out
12506 the maximum for us. */
12509 mips_register_move_cost (machine_mode mode,
12510 reg_class_t from, reg_class_t to)
12515 from = mips_canonicalize_move_class (from);
12516 to = mips_canonicalize_move_class (to);
12518 /* Handle moves that can be done without using general-purpose registers. */
12519 if (from == FP_REGS)
12521 if (to == FP_REGS && mips_mode_ok_for_mov_fmt_p (mode))
12526 /* Handle cases in which only one class deviates from the ideal. */
12527 dregs = TARGET_MIPS16 ? M16_REGS : GENERAL_REGS;
12529 return mips_move_from_gpr_cost (to);
12531 return mips_move_to_gpr_cost (from);
12533 /* Handles cases that require a GPR temporary. */
12534 cost1 = mips_move_to_gpr_cost (from);
12537 cost2 = mips_move_from_gpr_cost (to);
12539 return cost1 + cost2;
12545 /* Implement TARGET_REGISTER_PRIORITY. */
12548 mips_register_priority (int hard_regno)
12550 /* Treat MIPS16 registers with higher priority than other regs. */
12552 && TEST_HARD_REG_BIT (reg_class_contents[M16_REGS], hard_regno))
12557 /* Implement TARGET_MEMORY_MOVE_COST. */
12560 mips_memory_move_cost (machine_mode mode, reg_class_t rclass, bool in)
12562 return (mips_cost->memory_latency
12563 + memory_move_secondary_cost (mode, rclass, in));
12566 /* Implement SECONDARY_MEMORY_NEEDED. */
12569 mips_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
12572 /* Ignore spilled pseudos. */
12573 if (lra_in_progress && (class1 == NO_REGS || class2 == NO_REGS))
12576 if (((class1 == FP_REGS) != (class2 == FP_REGS))
12577 && ((TARGET_FLOATXX && !ISA_HAS_MXHC1)
12578 || TARGET_O32_FP64A_ABI)
12579 && GET_MODE_SIZE (mode) >= 8)
12585 /* Return the register class required for a secondary register when
12586 copying between one of the registers in RCLASS and value X, which
12587 has mode MODE. X is the source of the move if IN_P, otherwise it
12588 is the destination. Return NO_REGS if no secondary register is
12592 mips_secondary_reload_class (enum reg_class rclass,
12593 machine_mode mode, rtx x, bool)
12597 /* If X is a constant that cannot be loaded into $25, it must be loaded
12598 into some other GPR. No other register class allows a direct move. */
12599 if (mips_dangerous_for_la25_p (x))
12600 return reg_class_subset_p (rclass, LEA_REGS) ? NO_REGS : LEA_REGS;
12602 regno = true_regnum (x);
12605 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
12606 if (!reg_class_subset_p (rclass, M16_REGS) && !M16_REG_P (regno))
12612 /* Copying from accumulator registers to anywhere other than a general
12613 register requires a temporary general register. */
12614 if (reg_class_subset_p (rclass, ACC_REGS))
12615 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
12616 if (ACC_REG_P (regno))
12617 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
12619 if (reg_class_subset_p (rclass, FP_REGS))
12623 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8)))
12624 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
12625 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
12628 if (GP_REG_P (regno) || x == CONST0_RTX (mode))
12629 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
12632 if (CONSTANT_P (x) && !targetm.cannot_force_const_mem (mode, x))
12633 /* We can force the constant to memory and use lwc1
12634 and ldc1. As above, we will use pairs of lwc1s if
12635 ldc1 is not supported. */
12638 if (FP_REG_P (regno) && mips_mode_ok_for_mov_fmt_p (mode))
12639 /* In this case we can use mov.fmt. */
12642 /* Otherwise, we need to reload through an integer register. */
12645 if (FP_REG_P (regno))
12646 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
12651 /* Implement TARGET_MODE_REP_EXTENDED. */
12654 mips_mode_rep_extended (machine_mode mode, machine_mode mode_rep)
12656 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
12657 if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
12658 return SIGN_EXTEND;
12663 /* Implement TARGET_VALID_POINTER_MODE. */
12666 mips_valid_pointer_mode (machine_mode mode)
12668 return mode == SImode || (TARGET_64BIT && mode == DImode);
12671 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
12674 mips_vector_mode_supported_p (machine_mode mode)
12679 return TARGET_PAIRED_SINGLE_FLOAT;
12694 return TARGET_LOONGSON_VECTORS;
12701 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
12704 mips_scalar_mode_supported_p (machine_mode mode)
12706 if (ALL_FIXED_POINT_MODE_P (mode)
12707 && GET_MODE_PRECISION (mode) <= 2 * BITS_PER_WORD)
12710 return default_scalar_mode_supported_p (mode);
12713 /* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
12715 static machine_mode
12716 mips_preferred_simd_mode (machine_mode mode ATTRIBUTE_UNUSED)
12718 if (TARGET_PAIRED_SINGLE_FLOAT
12724 /* Implement TARGET_INIT_LIBFUNCS. */
12727 mips_init_libfuncs (void)
12729 if (TARGET_FIX_VR4120)
12731 /* Register the special divsi3 and modsi3 functions needed to work
12732 around VR4120 division errata. */
12733 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
12734 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
12737 if (TARGET_MIPS16 && TARGET_HARD_FLOAT_ABI)
12739 /* Register the MIPS16 -mhard-float stubs. */
12740 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
12741 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
12742 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
12743 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
12745 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
12746 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
12747 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
12748 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
12749 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
12750 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
12751 set_optab_libfunc (unord_optab, SFmode, "__mips16_unordsf2");
12753 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
12754 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
12755 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__mips16_floatunsisf");
12757 if (TARGET_DOUBLE_FLOAT)
12759 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
12760 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
12761 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
12762 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
12764 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
12765 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
12766 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
12767 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
12768 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
12769 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
12770 set_optab_libfunc (unord_optab, DFmode, "__mips16_unorddf2");
12772 set_conv_libfunc (sext_optab, DFmode, SFmode,
12773 "__mips16_extendsfdf2");
12774 set_conv_libfunc (trunc_optab, SFmode, DFmode,
12775 "__mips16_truncdfsf2");
12776 set_conv_libfunc (sfix_optab, SImode, DFmode,
12777 "__mips16_fix_truncdfsi");
12778 set_conv_libfunc (sfloat_optab, DFmode, SImode,
12779 "__mips16_floatsidf");
12780 set_conv_libfunc (ufloat_optab, DFmode, SImode,
12781 "__mips16_floatunsidf");
12785 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
12786 on an external non-MIPS16 routine to implement __sync_synchronize.
12787 Similarly for the rest of the ll/sc libfuncs. */
12790 synchronize_libfunc = init_one_libfunc ("__sync_synchronize");
12791 init_sync_libfuncs (UNITS_PER_WORD);
12795 /* Build up a multi-insn sequence that loads label TARGET into $AT. */
12798 mips_process_load_label (rtx target)
12800 rtx base, gp, intop;
12801 HOST_WIDE_INT offset;
12803 mips_multi_start ();
12807 mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target, 0);
12808 mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target, 0);
12812 mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target, 0);
12813 mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target, 0);
12817 gp = pic_offset_table_rtx;
12818 if (mips_cfun_has_cprestore_slot_p ())
12820 gp = gen_rtx_REG (Pmode, AT_REGNUM);
12821 mips_get_cprestore_base_and_offset (&base, &offset, true);
12822 if (!SMALL_OPERAND (offset))
12824 intop = GEN_INT (CONST_HIGH_PART (offset));
12825 mips_multi_add_insn ("lui\t%0,%1", gp, intop, 0);
12826 mips_multi_add_insn ("addu\t%0,%0,%1", gp, base, 0);
12829 offset = CONST_LOW_PART (offset);
12831 intop = GEN_INT (offset);
12832 if (ISA_HAS_LOAD_DELAY)
12833 mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp, intop, base, 0);
12835 mips_multi_add_insn ("lw\t%0,%1(%2)", gp, intop, base, 0);
12837 if (ISA_HAS_LOAD_DELAY)
12838 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target, gp, 0);
12840 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target, gp, 0);
12841 mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target, 0);
12846 /* Return the number of instructions needed to load a label into $AT. */
12848 static unsigned int
12849 mips_load_label_num_insns (void)
12851 if (cfun->machine->load_label_num_insns == 0)
12853 mips_process_load_label (pc_rtx);
12854 cfun->machine->load_label_num_insns = mips_multi_num_insns;
12856 return cfun->machine->load_label_num_insns;
12859 /* Emit an asm sequence to start a noat block and load the address
12860 of a label into $1. */
12863 mips_output_load_label (rtx target)
12865 mips_push_asm_switch (&mips_noat);
12866 if (TARGET_EXPLICIT_RELOCS)
12868 mips_process_load_label (target);
12869 mips_multi_write ();
12873 if (Pmode == DImode)
12874 output_asm_insn ("dla\t%@,%0", &target);
12876 output_asm_insn ("la\t%@,%0", &target);
12880 /* Return the length of INSN. LENGTH is the initial length computed by
12881 attributes in the machine-description file. */
12884 mips_adjust_insn_length (rtx_insn *insn, int length)
12886 /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length
12887 of a PIC long-branch sequence. Substitute the correct value. */
12888 if (length == MAX_PIC_BRANCH_LENGTH
12890 && INSN_CODE (insn) >= 0
12891 && get_attr_type (insn) == TYPE_BRANCH)
12893 /* Add the branch-over instruction and its delay slot, if this
12894 is a conditional branch. */
12895 length = simplejump_p (insn) ? 0 : 8;
12897 /* Add the size of a load into $AT. */
12898 length += BASE_INSN_LENGTH * mips_load_label_num_insns ();
12900 /* Add the length of an indirect jump, ignoring the delay slot. */
12901 length += TARGET_COMPRESSION ? 2 : 4;
12904 /* A unconditional jump has an unfilled delay slot if it is not part
12905 of a sequence. A conditional jump normally has a delay slot, but
12906 does not on MIPS16. */
12907 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
12908 length += TARGET_MIPS16 ? 2 : 4;
12910 /* See how many nops might be needed to avoid hardware hazards. */
12911 if (!cfun->machine->ignore_hazard_length_p
12913 && INSN_CODE (insn) >= 0)
12914 switch (get_attr_hazard (insn))
12920 case HAZARD_FORBIDDEN_SLOT:
12921 length += NOP_INSN_LENGTH;
12925 length += NOP_INSN_LENGTH * 2;
12932 /* Return the asm template for a call. OPERANDS are the operands, TARGET_OPNO
12933 is the operand number of the target. SIZE_OPNO is the operand number of
12934 the argument size operand that can optionally hold the call attributes. If
12935 SIZE_OPNO is not -1 and the call is indirect, use the function symbol from
12936 the call attributes to attach a R_MIPS_JALR relocation to the call. LINK_P
12937 indicates whether the jump is a call and needs to set the link register.
12939 When generating GOT code without explicit relocation operators, all calls
12940 should use assembly macros. Otherwise, all indirect calls should use "jr"
12941 or "jalr"; we will arrange to restore $gp afterwards if necessary. Finally,
12942 we can only generate direct calls for -mabicalls by temporarily switching
12945 For microMIPS jal(r), we try to generate jal(r)s when a 16-bit
12946 instruction is in the delay slot of jal(r).
12948 Where compact branches are available, we try to use them if the delay slot
12949 has a NOP (or equivalently delay slots were not enabled for the instruction
12953 mips_output_jump (rtx *operands, int target_opno, int size_opno, bool link_p)
12955 static char buffer[300];
12957 bool reg_p = REG_P (operands[target_opno]);
12959 const char *and_link = link_p ? "al" : "";
12960 const char *reg = reg_p ? "r" : "";
12961 const char *compact = "";
12962 const char *nop = "%/";
12963 const char *short_delay = link_p ? "%!" : "";
12964 const char *insn_name = TARGET_CB_NEVER || reg_p ? "j" : "b";
12966 /* Compact branches can only be described when the ISA has support for them
12967 as both the compact formatter '%:' and the delay slot NOP formatter '%/'
12968 work as a mutually exclusive pair. I.e. a NOP is never required if a
12969 compact form is available. */
12970 if (!final_sequence
12971 && (TARGET_CB_MAYBE
12972 || (ISA_HAS_JRC && !link_p && reg_p)))
12978 if (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS)
12979 sprintf (s, "%%*%s%s\t%%%d%%/", insn_name, and_link, target_opno);
12982 if (!reg_p && TARGET_ABICALLS_PIC2)
12983 s += sprintf (s, ".option\tpic0\n\t");
12985 if (reg_p && mips_get_pic_call_symbol (operands, size_opno))
12987 s += sprintf (s, "%%*.reloc\t1f,R_MIPS_JALR,%%%d\n1:\t", size_opno);
12988 /* Not sure why this shouldn't permit a short delay but it did not
12989 allow it before so we still don't allow it. */
12993 s += sprintf (s, "%%*");
12995 s += sprintf (s, "%s%s%s%s%s\t%%%d%s", insn_name, and_link, reg, compact, short_delay,
12998 if (!reg_p && TARGET_ABICALLS_PIC2)
12999 s += sprintf (s, "\n\t.option\tpic2");
13004 /* Return the assembly code for INSN, which has the operands given by
13005 OPERANDS, and which branches to OPERANDS[0] if some condition is true.
13006 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0]
13007 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
13008 version of BRANCH_IF_TRUE. */
13011 mips_output_conditional_branch (rtx_insn *insn, rtx *operands,
13012 const char *branch_if_true,
13013 const char *branch_if_false)
13015 unsigned int length;
13018 gcc_assert (LABEL_P (operands[0]));
13020 length = get_attr_length (insn);
13023 /* Just a simple conditional branch. */
13024 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
13025 return branch_if_true;
13028 /* Generate a reversed branch around a direct jump. This fallback does
13029 not use branch-likely instructions. */
13030 mips_branch_likely = false;
13031 rtx_code_label *not_taken = gen_label_rtx ();
13032 taken = operands[0];
13034 /* Generate the reversed branch to NOT_TAKEN. */
13035 operands[0] = not_taken;
13036 output_asm_insn (branch_if_false, operands);
13038 /* If INSN has a delay slot, we must provide delay slots for both the
13039 branch to NOT_TAKEN and the conditional jump. We must also ensure
13040 that INSN's delay slot is executed in the appropriate cases. */
13041 if (final_sequence)
13043 /* This first delay slot will always be executed, so use INSN's
13044 delay slot if is not annulled. */
13045 if (!INSN_ANNULLED_BRANCH_P (insn))
13047 final_scan_insn (final_sequence->insn (1),
13048 asm_out_file, optimize, 1, NULL);
13049 final_sequence->insn (1)->set_deleted ();
13052 output_asm_insn ("nop", 0);
13053 fprintf (asm_out_file, "\n");
13056 /* Output the unconditional branch to TAKEN. */
13057 if (TARGET_ABSOLUTE_JUMPS && TARGET_CB_MAYBE)
13059 /* Add a hazard nop. */
13060 if (!final_sequence)
13062 output_asm_insn ("nop\t\t# hazard nop", 0);
13063 fprintf (asm_out_file, "\n");
13065 output_asm_insn (MIPS_ABSOLUTE_JUMP ("bc\t%0"), &taken);
13067 else if (TARGET_ABSOLUTE_JUMPS)
13068 output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken);
13071 mips_output_load_label (taken);
13072 if (TARGET_CB_MAYBE)
13073 output_asm_insn ("jrc\t%@%]", 0);
13075 output_asm_insn ("jr\t%@%]%/", 0);
13078 /* Now deal with its delay slot; see above. */
13079 if (final_sequence)
13081 /* This delay slot will only be executed if the branch is taken.
13082 Use INSN's delay slot if is annulled. */
13083 if (INSN_ANNULLED_BRANCH_P (insn))
13085 final_scan_insn (final_sequence->insn (1),
13086 asm_out_file, optimize, 1, NULL);
13087 final_sequence->insn (1)->set_deleted ();
13089 else if (TARGET_CB_NEVER)
13090 output_asm_insn ("nop", 0);
13091 fprintf (asm_out_file, "\n");
13094 /* Output NOT_TAKEN. */
13095 targetm.asm_out.internal_label (asm_out_file, "L",
13096 CODE_LABEL_NUMBER (not_taken));
13100 /* Return the assembly code for INSN, which branches to OPERANDS[0]
13101 if some equality condition is true. The condition is given by
13102 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
13103 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
13104 OPERANDS[3] is the second operand and may be zero or a register. */
13107 mips_output_equal_conditional_branch (rtx_insn* insn, rtx *operands,
13110 const char *branch[2];
13111 /* For a simple BNEZ or BEQZ microMIPSr3 branch. */
13112 if (TARGET_MICROMIPS
13113 && mips_isa_rev <= 5
13114 && operands[3] == const0_rtx
13115 && get_attr_length (insn) <= 8)
13117 if (mips_cb == MIPS_CB_OPTIMAL)
13119 branch[!inverted_p] = "%*b%C1z%:\t%2,%0";
13120 branch[inverted_p] = "%*b%N1z%:\t%2,%0";
13124 branch[!inverted_p] = "%*b%C1z\t%2,%0%/";
13125 branch[inverted_p] = "%*b%N1z\t%2,%0%/";
13128 else if (TARGET_CB_MAYBE)
13130 if (operands[3] == const0_rtx)
13132 branch[!inverted_p] = MIPS_BRANCH_C ("b%C1z", "%2,%0");
13133 branch[inverted_p] = MIPS_BRANCH_C ("b%N1z", "%2,%0");
13135 else if (REGNO (operands[2]) != REGNO (operands[3]))
13137 branch[!inverted_p] = MIPS_BRANCH_C ("b%C1", "%2,%3,%0");
13138 branch[inverted_p] = MIPS_BRANCH_C ("b%N1", "%2,%3,%0");
13142 /* This case is degenerate. It should not happen, but does. */
13143 if (GET_CODE (operands[1]) == NE)
13144 inverted_p = !inverted_p;
13146 branch[!inverted_p] = MIPS_BRANCH_C ("b", "%0");
13147 branch[inverted_p] = "%*\t\t# branch never";
13152 branch[!inverted_p] = MIPS_BRANCH ("b%C1", "%2,%z3,%0");
13153 branch[inverted_p] = MIPS_BRANCH ("b%N1", "%2,%z3,%0");
13156 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
13159 /* Return the assembly code for INSN, which branches to OPERANDS[0]
13160 if some ordering condition is true. The condition is given by
13161 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
13162 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
13163 OPERANDS[3] is the second operand and may be zero or a register. */
13166 mips_output_order_conditional_branch (rtx_insn *insn, rtx *operands,
13169 const char *branch[2];
13171 /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true.
13172 Make BRANCH[0] branch on the inverse condition. */
13173 if (operands[3] != const0_rtx)
13175 /* Handle degenerate cases that should not, but do, occur. */
13176 if (REGNO (operands[2]) == REGNO (operands[3]))
13178 switch (GET_CODE (operands[1]))
13182 inverted_p = !inverted_p;
13183 /* Fall through. */
13186 branch[!inverted_p] = MIPS_BRANCH_C ("b", "%0");
13187 branch[inverted_p] = "%*\t\t# branch never";
13190 gcc_unreachable ();
13195 branch[!inverted_p] = MIPS_BRANCH_C ("b%C1", "%2,%3,%0");
13196 branch[inverted_p] = MIPS_BRANCH_C ("b%N1", "%2,%3,%0");
13201 switch (GET_CODE (operands[1]))
13203 /* These cases are equivalent to comparisons against zero. */
13205 inverted_p = !inverted_p;
13206 /* Fall through. */
13208 if (TARGET_CB_MAYBE)
13210 branch[!inverted_p] = MIPS_BRANCH_C ("bnez", "%2,%0");
13211 branch[inverted_p] = MIPS_BRANCH_C ("beqz", "%2,%0");
13215 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%0");
13216 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%0");
13220 /* These cases are always true or always false. */
13222 inverted_p = !inverted_p;
13223 /* Fall through. */
13225 if (TARGET_CB_MAYBE)
13227 branch[!inverted_p] = MIPS_BRANCH_C ("b", "%0");
13228 branch[inverted_p] = "%*\t\t# branch never";
13232 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%0");
13233 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%0");
13238 if (TARGET_CB_MAYBE)
13240 branch[!inverted_p] = MIPS_BRANCH_C ("b%C1z", "%2,%0");
13241 branch[inverted_p] = MIPS_BRANCH_C ("b%N1z", "%2,%0");
13245 branch[!inverted_p] = MIPS_BRANCH ("b%C1z", "%2,%0");
13246 branch[inverted_p] = MIPS_BRANCH ("b%N1z", "%2,%0");
13251 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
13254 /* Start a block of code that needs access to the LL, SC and SYNC
13258 mips_start_ll_sc_sync_block (void)
13260 if (!ISA_HAS_LL_SC)
13262 output_asm_insn (".set\tpush", 0);
13264 output_asm_insn (".set\tmips3", 0);
13266 output_asm_insn (".set\tmips2", 0);
13270 /* End a block started by mips_start_ll_sc_sync_block. */
13273 mips_end_ll_sc_sync_block (void)
13275 if (!ISA_HAS_LL_SC)
13276 output_asm_insn (".set\tpop", 0);
13279 /* Output and/or return the asm template for a sync instruction. */
13282 mips_output_sync (void)
13284 mips_start_ll_sc_sync_block ();
13285 output_asm_insn ("sync", 0);
13286 mips_end_ll_sc_sync_block ();
13290 /* Return the asm template associated with sync_insn1 value TYPE.
13291 IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */
13293 static const char *
13294 mips_sync_insn1_template (enum attr_sync_insn1 type, bool is_64bit_p)
13298 case SYNC_INSN1_MOVE:
13299 return "move\t%0,%z2";
13300 case SYNC_INSN1_LI:
13301 return "li\t%0,%2";
13302 case SYNC_INSN1_ADDU:
13303 return is_64bit_p ? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2";
13304 case SYNC_INSN1_ADDIU:
13305 return is_64bit_p ? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2";
13306 case SYNC_INSN1_SUBU:
13307 return is_64bit_p ? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2";
13308 case SYNC_INSN1_AND:
13309 return "and\t%0,%1,%z2";
13310 case SYNC_INSN1_ANDI:
13311 return "andi\t%0,%1,%2";
13312 case SYNC_INSN1_OR:
13313 return "or\t%0,%1,%z2";
13314 case SYNC_INSN1_ORI:
13315 return "ori\t%0,%1,%2";
13316 case SYNC_INSN1_XOR:
13317 return "xor\t%0,%1,%z2";
13318 case SYNC_INSN1_XORI:
13319 return "xori\t%0,%1,%2";
13321 gcc_unreachable ();
13324 /* Return the asm template associated with sync_insn2 value TYPE. */
13326 static const char *
13327 mips_sync_insn2_template (enum attr_sync_insn2 type)
13331 case SYNC_INSN2_NOP:
13332 gcc_unreachable ();
13333 case SYNC_INSN2_AND:
13334 return "and\t%0,%1,%z2";
13335 case SYNC_INSN2_XOR:
13336 return "xor\t%0,%1,%z2";
13337 case SYNC_INSN2_NOT:
13338 return "nor\t%0,%1,%.";
13340 gcc_unreachable ();
13343 /* OPERANDS are the operands to a sync loop instruction and INDEX is
13344 the value of the one of the sync_* attributes. Return the operand
13345 referred to by the attribute, or DEFAULT_VALUE if the insn doesn't
13346 have the associated attribute. */
13349 mips_get_sync_operand (rtx *operands, int index, rtx default_value)
13352 default_value = operands[index - 1];
13353 return default_value;
13356 /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn
13357 sequence for it. */
13360 mips_process_sync_loop (rtx_insn *insn, rtx *operands)
13362 rtx at, mem, oldval, newval, inclusive_mask, exclusive_mask;
13363 rtx required_oldval, insn1_op2, tmp1, tmp2, tmp3, cmp;
13364 unsigned int tmp3_insn;
13365 enum attr_sync_insn1 insn1;
13366 enum attr_sync_insn2 insn2;
13369 enum memmodel model;
13371 /* Read an operand from the sync_WHAT attribute and store it in
13372 variable WHAT. DEFAULT is the default value if no attribute
13374 #define READ_OPERAND(WHAT, DEFAULT) \
13375 WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \
13378 /* Read the memory. */
13379 READ_OPERAND (mem, 0);
13381 is_64bit_p = (GET_MODE_BITSIZE (GET_MODE (mem)) == 64);
13383 /* Read the other attributes. */
13384 at = gen_rtx_REG (GET_MODE (mem), AT_REGNUM);
13385 READ_OPERAND (oldval, at);
13386 READ_OPERAND (cmp, 0);
13387 READ_OPERAND (newval, at);
13388 READ_OPERAND (inclusive_mask, 0);
13389 READ_OPERAND (exclusive_mask, 0);
13390 READ_OPERAND (required_oldval, 0);
13391 READ_OPERAND (insn1_op2, 0);
13392 insn1 = get_attr_sync_insn1 (insn);
13393 insn2 = get_attr_sync_insn2 (insn);
13395 /* Don't bother setting CMP result that is never used. */
13396 if (cmp && find_reg_note (insn, REG_UNUSED, cmp))
13399 memmodel_attr = get_attr_sync_memmodel (insn);
13400 switch (memmodel_attr)
13403 model = MEMMODEL_ACQ_REL;
13406 model = MEMMODEL_ACQUIRE;
13409 model = memmodel_from_int (INTVAL (operands[memmodel_attr]));
13412 mips_multi_start ();
13414 /* Output the release side of the memory barrier. */
13415 if (need_atomic_barrier_p (model, true))
13417 if (required_oldval == 0 && TARGET_OCTEON)
13419 /* Octeon doesn't reorder reads, so a full barrier can be
13420 created by using SYNCW to order writes combined with the
13421 write from the following SC. When the SC successfully
13422 completes, we know that all preceding writes are also
13423 committed to the coherent memory system. It is possible
13424 for a single SYNCW to fail, but a pair of them will never
13425 fail, so we use two. */
13426 mips_multi_add_insn ("syncw", NULL);
13427 mips_multi_add_insn ("syncw", NULL);
13430 mips_multi_add_insn ("sync", NULL);
13433 /* Output the branch-back label. */
13434 mips_multi_add_label ("1:");
13436 /* OLDVAL = *MEM. */
13437 mips_multi_add_insn (is_64bit_p ? "lld\t%0,%1" : "ll\t%0,%1",
13438 oldval, mem, NULL);
13440 /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */
13441 if (required_oldval)
13443 if (inclusive_mask == 0)
13447 gcc_assert (oldval != at);
13448 mips_multi_add_insn ("and\t%0,%1,%2",
13449 at, oldval, inclusive_mask, NULL);
13452 if (TARGET_CB_NEVER)
13453 mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1, required_oldval, NULL);
13455 /* CMP = 0 [delay slot]. */
13457 mips_multi_add_insn ("li\t%0,0", cmp, NULL);
13459 if (TARGET_CB_MAYBE && required_oldval == const0_rtx)
13460 mips_multi_add_insn ("bnezc\t%0,2f", tmp1, NULL);
13461 else if (TARGET_CB_MAYBE)
13462 mips_multi_add_insn ("bnec\t%0,%1,2f", tmp1, required_oldval, NULL);
13466 /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */
13467 if (exclusive_mask == 0)
13471 gcc_assert (oldval != at);
13472 mips_multi_add_insn ("and\t%0,%1,%z2",
13473 at, oldval, exclusive_mask, NULL);
13477 /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2).
13479 We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit
13480 at least one instruction in that case. */
13481 if (insn1 == SYNC_INSN1_MOVE
13482 && (tmp1 != const0_rtx || insn2 != SYNC_INSN2_NOP))
13486 mips_multi_add_insn (mips_sync_insn1_template (insn1, is_64bit_p),
13487 newval, oldval, insn1_op2, NULL);
13491 /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */
13492 if (insn2 == SYNC_INSN2_NOP)
13496 mips_multi_add_insn (mips_sync_insn2_template (insn2),
13497 newval, tmp2, inclusive_mask, NULL);
13500 tmp3_insn = mips_multi_last_index ();
13502 /* $AT = $TMP1 | $TMP3. */
13503 if (tmp1 == const0_rtx || tmp3 == const0_rtx)
13505 mips_multi_set_operand (tmp3_insn, 0, at);
13510 gcc_assert (tmp1 != tmp3);
13511 mips_multi_add_insn ("or\t%0,%1,%2", at, tmp1, tmp3, NULL);
13514 /* if (!commit (*MEM = $AT)) goto 1.
13516 This will sometimes be a delayed branch; see the write code below
13518 mips_multi_add_insn (is_64bit_p ? "scd\t%0,%1" : "sc\t%0,%1", at, mem, NULL);
13520 /* When using branch likely (-mfix-r10000), the delay slot instruction
13521 will be annulled on false. The normal delay slot instructions
13522 calculate the overall result of the atomic operation and must not
13523 be annulled. To ensure this behavior unconditionally use a NOP
13524 in the delay slot for the branch likely case. */
13526 if (TARGET_CB_MAYBE)
13527 mips_multi_add_insn ("beqzc\t%0,1b", at, NULL);
13529 mips_multi_add_insn ("beq%?\t%0,%.,1b%~", at, NULL);
13531 /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */
13532 if (insn1 != SYNC_INSN1_MOVE && insn1 != SYNC_INSN1_LI && tmp3 != newval)
13534 mips_multi_copy_insn (tmp3_insn);
13535 mips_multi_set_operand (mips_multi_last_index (), 0, newval);
13537 else if (!(required_oldval && cmp) && !mips_branch_likely)
13538 mips_multi_add_insn ("nop", NULL);
13540 /* CMP = 1 -- either standalone or in a delay slot. */
13541 if (required_oldval && cmp)
13542 mips_multi_add_insn ("li\t%0,1", cmp, NULL);
13544 /* Output the acquire side of the memory barrier. */
13545 if (TARGET_SYNC_AFTER_SC && need_atomic_barrier_p (model, false))
13546 mips_multi_add_insn ("sync", NULL);
13548 /* Output the exit label, if needed. */
13549 if (required_oldval)
13550 mips_multi_add_label ("2:");
13552 #undef READ_OPERAND
13555 /* Output and/or return the asm template for sync loop INSN, which has
13556 the operands given by OPERANDS. */
13559 mips_output_sync_loop (rtx_insn *insn, rtx *operands)
13561 /* Use branch-likely instructions to work around the LL/SC R10000
13563 mips_branch_likely = TARGET_FIX_R10000;
13565 mips_process_sync_loop (insn, operands);
13567 mips_push_asm_switch (&mips_noreorder);
13568 mips_push_asm_switch (&mips_nomacro);
13569 mips_push_asm_switch (&mips_noat);
13570 mips_start_ll_sc_sync_block ();
13572 mips_multi_write ();
13574 mips_end_ll_sc_sync_block ();
13575 mips_pop_asm_switch (&mips_noat);
13576 mips_pop_asm_switch (&mips_nomacro);
13577 mips_pop_asm_switch (&mips_noreorder);
13582 /* Return the number of individual instructions in sync loop INSN,
13583 which has the operands given by OPERANDS. */
13586 mips_sync_loop_insns (rtx_insn *insn, rtx *operands)
13588 /* Use branch-likely instructions to work around the LL/SC R10000
13590 mips_branch_likely = TARGET_FIX_R10000;
13591 mips_process_sync_loop (insn, operands);
13592 return mips_multi_num_insns;
13595 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
13596 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
13598 When working around R4000 and R4400 errata, we need to make sure that
13599 the division is not immediately followed by a shift[1][2]. We also
13600 need to stop the division from being put into a branch delay slot[3].
13601 The easiest way to avoid both problems is to add a nop after the
13602 division. When a divide-by-zero check is needed, this nop can be
13603 used to fill the branch delay slot.
13605 [1] If a double-word or a variable shift executes immediately
13606 after starting an integer division, the shift may give an
13607 incorrect result. See quotations of errata #16 and #28 from
13608 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
13609 in mips.md for details.
13611 [2] A similar bug to [1] exists for all revisions of the
13612 R4000 and the R4400 when run in an MC configuration.
13613 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
13615 "19. In this following sequence:
13617 ddiv (or ddivu or div or divu)
13618 dsll32 (or dsrl32, dsra32)
13620 if an MPT stall occurs, while the divide is slipping the cpu
13621 pipeline, then the following double shift would end up with an
13624 Workaround: The compiler needs to avoid generating any
13625 sequence with divide followed by extended double shift."
13627 This erratum is also present in "MIPS R4400MC Errata, Processor
13628 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
13629 & 3.0" as errata #10 and #4, respectively.
13631 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
13632 (also valid for MIPS R4000MC processors):
13634 "52. R4000SC: This bug does not apply for the R4000PC.
13636 There are two flavors of this bug:
13638 1) If the instruction just after divide takes an RF exception
13639 (tlb-refill, tlb-invalid) and gets an instruction cache
13640 miss (both primary and secondary) and the line which is
13641 currently in secondary cache at this index had the first
13642 data word, where the bits 5..2 are set, then R4000 would
13643 get a wrong result for the div.
13648 ------------------- # end-of page. -tlb-refill
13653 ------------------- # end-of page. -tlb-invalid
13656 2) If the divide is in the taken branch delay slot, where the
13657 target takes RF exception and gets an I-cache miss for the
13658 exception vector or where I-cache miss occurs for the
13659 target address, under the above mentioned scenarios, the
13660 div would get wrong results.
13663 j r2 # to next page mapped or unmapped
13664 div r8,r9 # this bug would be there as long
13665 # as there is an ICache miss and
13666 nop # the "data pattern" is present
13669 beq r0, r0, NextPage # to Next page
13673 This bug is present for div, divu, ddiv, and ddivu
13676 Workaround: For item 1), OS could make sure that the next page
13677 after the divide instruction is also mapped. For item 2), the
13678 compiler could make sure that the divide instruction is not in
13679 the branch delay slot."
13681 These processors have PRId values of 0x00004220 and 0x00004300 for
13682 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
13685 mips_output_division (const char *division, rtx *operands)
13690 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
13692 output_asm_insn (s, operands);
13695 if (TARGET_CHECK_ZERO_DIV)
13699 output_asm_insn (s, operands);
13700 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
13702 else if (GENERATE_DIVIDE_TRAPS)
13704 /* Avoid long replay penalty on load miss by putting the trap before
13707 output_asm_insn ("teq\t%2,%.,7", operands);
13710 output_asm_insn (s, operands);
13711 s = "teq\t%2,%.,7";
13716 if (flag_delayed_branch)
13718 output_asm_insn ("%(bne\t%2,%.,1f", operands);
13719 output_asm_insn (s, operands);
13720 s = "break\t7%)\n1:";
13724 output_asm_insn (s, operands);
13725 s = "bne\t%2,%.,1f\n\tnop\n\tbreak\t7\n1:";
13732 /* Return true if destination of IN_INSN is used as add source in
13733 OUT_INSN. Both IN_INSN and OUT_INSN are of type fmadd. Example:
13734 madd.s dst, x, y, z
13735 madd.s a, dst, b, c */
13738 mips_fmadd_bypass (rtx_insn *out_insn, rtx_insn *in_insn)
13740 int dst_reg, src_reg;
13742 gcc_assert (get_attr_type (in_insn) == TYPE_FMADD);
13743 gcc_assert (get_attr_type (out_insn) == TYPE_FMADD);
13745 extract_insn (in_insn);
13746 dst_reg = REG_P (recog_data.operand[0]);
13748 extract_insn (out_insn);
13749 src_reg = REG_P (recog_data.operand[1]);
13751 if (dst_reg == src_reg)
13757 /* Return true if IN_INSN is a multiply-add or multiply-subtract
13758 instruction and if OUT_INSN assigns to the accumulator operand. */
13761 mips_linked_madd_p (rtx_insn *out_insn, rtx_insn *in_insn)
13763 enum attr_accum_in accum_in;
13764 int accum_in_opnum;
13767 if (recog_memoized (in_insn) < 0)
13770 accum_in = get_attr_accum_in (in_insn);
13771 if (accum_in == ACCUM_IN_NONE)
13774 accum_in_opnum = accum_in - ACCUM_IN_0;
13776 extract_insn (in_insn);
13777 gcc_assert (accum_in_opnum < recog_data.n_operands);
13778 accum_in_op = recog_data.operand[accum_in_opnum];
13780 return reg_set_p (accum_in_op, out_insn);
13783 /* True if the dependency between OUT_INSN and IN_INSN is on the store
13784 data rather than the address. We need this because the cprestore
13785 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
13786 which causes the default routine to abort. We just return false
13790 mips_store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
13792 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
13795 return store_data_bypass_p (out_insn, in_insn);
13799 /* Variables and flags used in scheduler hooks when tuning for
13803 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
13806 /* If true, then next ALU1/2 instruction will go to ALU1. */
13809 /* If true, then next FALU1/2 unstruction will go to FALU1. */
13812 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
13813 int alu1_core_unit_code;
13814 int alu2_core_unit_code;
13815 int falu1_core_unit_code;
13816 int falu2_core_unit_code;
13818 /* True if current cycle has a multi instruction.
13819 This flag is used in mips_ls2_dfa_post_advance_cycle. */
13820 bool cycle_has_multi_p;
13822 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
13823 These are used in mips_ls2_dfa_post_advance_cycle to initialize
13825 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
13826 instruction to go ALU1. */
13827 rtx_insn *alu1_turn_enabled_insn;
13828 rtx_insn *alu2_turn_enabled_insn;
13829 rtx_insn *falu1_turn_enabled_insn;
13830 rtx_insn *falu2_turn_enabled_insn;
13833 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
13834 dependencies have no cost, except on the 20Kc where output-dependence
13835 is treated like input-dependence. */
13838 mips_adjust_cost (rtx_insn *insn ATTRIBUTE_UNUSED, rtx link,
13839 rtx_insn *dep ATTRIBUTE_UNUSED, int cost)
13841 if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT
13844 if (REG_NOTE_KIND (link) != 0)
13849 /* Return the number of instructions that can be issued per cycle. */
13852 mips_issue_rate (void)
13856 case PROCESSOR_74KC:
13857 case PROCESSOR_74KF2_1:
13858 case PROCESSOR_74KF1_1:
13859 case PROCESSOR_74KF3_2:
13860 /* The 74k is not strictly quad-issue cpu, but can be seen as one
13861 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
13862 but in reality only a maximum of 3 insns can be issued as
13863 floating-point loads and stores also require a slot in the
13865 case PROCESSOR_R10000:
13866 /* All R10K Processors are quad-issue (being the first MIPS
13867 processors to support this feature). */
13870 case PROCESSOR_20KC:
13871 case PROCESSOR_R4130:
13872 case PROCESSOR_R5400:
13873 case PROCESSOR_R5500:
13874 case PROCESSOR_R5900:
13875 case PROCESSOR_R7000:
13876 case PROCESSOR_R9000:
13877 case PROCESSOR_OCTEON:
13878 case PROCESSOR_OCTEON2:
13879 case PROCESSOR_OCTEON3:
13880 case PROCESSOR_I6400:
13883 case PROCESSOR_SB1:
13884 case PROCESSOR_SB1A:
13885 /* This is actually 4, but we get better performance if we claim 3.
13886 This is partly because of unwanted speculative code motion with the
13887 larger number, and partly because in most common cases we can't
13888 reach the theoretical max of 4. */
13891 case PROCESSOR_LOONGSON_2E:
13892 case PROCESSOR_LOONGSON_2F:
13893 case PROCESSOR_LOONGSON_3A:
13894 case PROCESSOR_P5600:
13897 case PROCESSOR_XLP:
13898 return (reload_completed ? 4 : 3);
13905 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
13908 mips_ls2_init_dfa_post_cycle_insn (void)
13911 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
13912 mips_ls2.alu1_turn_enabled_insn = get_insns ();
13916 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
13917 mips_ls2.alu2_turn_enabled_insn = get_insns ();
13921 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
13922 mips_ls2.falu1_turn_enabled_insn = get_insns ();
13926 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
13927 mips_ls2.falu2_turn_enabled_insn = get_insns ();
13930 mips_ls2.alu1_core_unit_code = get_cpu_unit_code ("ls2_alu1_core");
13931 mips_ls2.alu2_core_unit_code = get_cpu_unit_code ("ls2_alu2_core");
13932 mips_ls2.falu1_core_unit_code = get_cpu_unit_code ("ls2_falu1_core");
13933 mips_ls2.falu2_core_unit_code = get_cpu_unit_code ("ls2_falu2_core");
13936 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
13937 Init data used in mips_dfa_post_advance_cycle. */
13940 mips_init_dfa_post_cycle_insn (void)
13942 if (TUNE_LOONGSON_2EF)
13943 mips_ls2_init_dfa_post_cycle_insn ();
13946 /* Initialize STATE when scheduling for Loongson 2E/2F.
13947 Support round-robin dispatch scheme by enabling only one of
13948 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
13952 mips_ls2_dfa_post_advance_cycle (state_t state)
13954 if (cpu_unit_reservation_p (state, mips_ls2.alu1_core_unit_code))
13956 /* Though there are no non-pipelined ALU1 insns,
13957 we can get an instruction of type 'multi' before reload. */
13958 gcc_assert (mips_ls2.cycle_has_multi_p);
13959 mips_ls2.alu1_turn_p = false;
13962 mips_ls2.cycle_has_multi_p = false;
13964 if (cpu_unit_reservation_p (state, mips_ls2.alu2_core_unit_code))
13965 /* We have a non-pipelined alu instruction in the core,
13966 adjust round-robin counter. */
13967 mips_ls2.alu1_turn_p = true;
13969 if (mips_ls2.alu1_turn_p)
13971 if (state_transition (state, mips_ls2.alu1_turn_enabled_insn) >= 0)
13972 gcc_unreachable ();
13976 if (state_transition (state, mips_ls2.alu2_turn_enabled_insn) >= 0)
13977 gcc_unreachable ();
13980 if (cpu_unit_reservation_p (state, mips_ls2.falu1_core_unit_code))
13982 /* There are no non-pipelined FALU1 insns. */
13983 gcc_unreachable ();
13984 mips_ls2.falu1_turn_p = false;
13987 if (cpu_unit_reservation_p (state, mips_ls2.falu2_core_unit_code))
13988 /* We have a non-pipelined falu instruction in the core,
13989 adjust round-robin counter. */
13990 mips_ls2.falu1_turn_p = true;
13992 if (mips_ls2.falu1_turn_p)
13994 if (state_transition (state, mips_ls2.falu1_turn_enabled_insn) >= 0)
13995 gcc_unreachable ();
13999 if (state_transition (state, mips_ls2.falu2_turn_enabled_insn) >= 0)
14000 gcc_unreachable ();
14004 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
14005 This hook is being called at the start of each cycle. */
14008 mips_dfa_post_advance_cycle (void)
14010 if (TUNE_LOONGSON_2EF)
14011 mips_ls2_dfa_post_advance_cycle (curr_state);
14014 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
14015 be as wide as the scheduling freedom in the DFA. */
14018 mips_multipass_dfa_lookahead (void)
14020 /* Can schedule up to 4 of the 6 function units in any one cycle. */
14024 if (TUNE_LOONGSON_2EF || TUNE_LOONGSON_3A)
14030 if (TUNE_P5600 || TUNE_I6400)
14036 /* Remove the instruction at index LOWER from ready queue READY and
14037 reinsert it in front of the instruction at index HIGHER. LOWER must
14041 mips_promote_ready (rtx_insn **ready, int lower, int higher)
14043 rtx_insn *new_head;
14046 new_head = ready[lower];
14047 for (i = lower; i < higher; i++)
14048 ready[i] = ready[i + 1];
14049 ready[i] = new_head;
14052 /* If the priority of the instruction at POS2 in the ready queue READY
14053 is within LIMIT units of that of the instruction at POS1, swap the
14054 instructions if POS2 is not already less than POS1. */
14057 mips_maybe_swap_ready (rtx_insn **ready, int pos1, int pos2, int limit)
14060 && INSN_PRIORITY (ready[pos1]) + limit >= INSN_PRIORITY (ready[pos2]))
14064 temp = ready[pos1];
14065 ready[pos1] = ready[pos2];
14066 ready[pos2] = temp;
14070 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
14071 that may clobber hi or lo. */
14072 static rtx_insn *mips_macc_chains_last_hilo;
14074 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
14075 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
14078 mips_macc_chains_record (rtx_insn *insn)
14080 if (get_attr_may_clobber_hilo (insn))
14081 mips_macc_chains_last_hilo = insn;
14084 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
14085 has NREADY elements, looking for a multiply-add or multiply-subtract
14086 instruction that is cumulative with mips_macc_chains_last_hilo.
14087 If there is one, promote it ahead of anything else that might
14088 clobber hi or lo. */
14091 mips_macc_chains_reorder (rtx_insn **ready, int nready)
14095 if (mips_macc_chains_last_hilo != 0)
14096 for (i = nready - 1; i >= 0; i--)
14097 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
14099 for (j = nready - 1; j > i; j--)
14100 if (recog_memoized (ready[j]) >= 0
14101 && get_attr_may_clobber_hilo (ready[j]))
14103 mips_promote_ready (ready, i, j);
14110 /* The last instruction to be scheduled. */
14111 static rtx_insn *vr4130_last_insn;
14113 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
14114 points to an rtx that is initially an instruction. Nullify the rtx
14115 if the instruction uses the value of register X. */
14118 vr4130_true_reg_dependence_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
14123 insn_ptr = (rtx *) data;
14126 && reg_referenced_p (x, PATTERN (*insn_ptr)))
14130 /* Return true if there is true register dependence between vr4130_last_insn
14134 vr4130_true_reg_dependence_p (rtx insn)
14136 note_stores (PATTERN (vr4130_last_insn),
14137 vr4130_true_reg_dependence_p_1, &insn);
14141 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
14142 the ready queue and that INSN2 is the instruction after it, return
14143 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
14144 in which INSN1 and INSN2 can probably issue in parallel, but for
14145 which (INSN2, INSN1) should be less sensitive to instruction
14146 alignment than (INSN1, INSN2). See 4130.md for more details. */
14149 vr4130_swap_insns_p (rtx_insn *insn1, rtx_insn *insn2)
14151 sd_iterator_def sd_it;
14154 /* Check for the following case:
14156 1) there is some other instruction X with an anti dependence on INSN1;
14157 2) X has a higher priority than INSN2; and
14158 3) X is an arithmetic instruction (and thus has no unit restrictions).
14160 If INSN1 is the last instruction blocking X, it would better to
14161 choose (INSN1, X) over (INSN2, INSN1). */
14162 FOR_EACH_DEP (insn1, SD_LIST_FORW, sd_it, dep)
14163 if (DEP_TYPE (dep) == REG_DEP_ANTI
14164 && INSN_PRIORITY (DEP_CON (dep)) > INSN_PRIORITY (insn2)
14165 && recog_memoized (DEP_CON (dep)) >= 0
14166 && get_attr_vr4130_class (DEP_CON (dep)) == VR4130_CLASS_ALU)
14169 if (vr4130_last_insn != 0
14170 && recog_memoized (insn1) >= 0
14171 && recog_memoized (insn2) >= 0)
14173 /* See whether INSN1 and INSN2 use different execution units,
14174 or if they are both ALU-type instructions. If so, they can
14175 probably execute in parallel. */
14176 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
14177 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
14178 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
14180 /* If only one of the instructions has a dependence on
14181 vr4130_last_insn, prefer to schedule the other one first. */
14182 bool dep1_p = vr4130_true_reg_dependence_p (insn1);
14183 bool dep2_p = vr4130_true_reg_dependence_p (insn2);
14184 if (dep1_p != dep2_p)
14187 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
14188 is not an ALU-type instruction and if INSN1 uses the same
14189 execution unit. (Note that if this condition holds, we already
14190 know that INSN2 uses a different execution unit.) */
14191 if (class1 != VR4130_CLASS_ALU
14192 && recog_memoized (vr4130_last_insn) >= 0
14193 && class1 == get_attr_vr4130_class (vr4130_last_insn))
14200 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
14201 queue with at least two instructions. Swap the first two if
14202 vr4130_swap_insns_p says that it could be worthwhile. */
14205 vr4130_reorder (rtx_insn **ready, int nready)
14207 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
14208 mips_promote_ready (ready, nready - 2, nready - 1);
14211 /* Record whether last 74k AGEN instruction was a load or store. */
14212 static enum attr_type mips_last_74k_agen_insn = TYPE_UNKNOWN;
14214 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
14215 resets to TYPE_UNKNOWN state. */
14218 mips_74k_agen_init (rtx_insn *insn)
14220 if (!insn || CALL_P (insn) || JUMP_P (insn))
14221 mips_last_74k_agen_insn = TYPE_UNKNOWN;
14224 enum attr_type type = get_attr_type (insn);
14225 if (type == TYPE_LOAD || type == TYPE_STORE)
14226 mips_last_74k_agen_insn = type;
14230 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
14231 loads to be grouped together, and multiple stores to be grouped
14232 together. Swap things around in the ready queue to make this happen. */
14235 mips_74k_agen_reorder (rtx_insn **ready, int nready)
14238 int store_pos, load_pos;
14243 for (i = nready - 1; i >= 0; i--)
14245 rtx_insn *insn = ready[i];
14246 if (USEFUL_INSN_P (insn))
14247 switch (get_attr_type (insn))
14250 if (store_pos == -1)
14255 if (load_pos == -1)
14264 if (load_pos == -1 || store_pos == -1)
14267 switch (mips_last_74k_agen_insn)
14270 /* Prefer to schedule loads since they have a higher latency. */
14272 /* Swap loads to the front of the queue. */
14273 mips_maybe_swap_ready (ready, load_pos, store_pos, 4);
14276 /* Swap stores to the front of the queue. */
14277 mips_maybe_swap_ready (ready, store_pos, load_pos, 4);
14284 /* Implement TARGET_SCHED_INIT. */
14287 mips_sched_init (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
14288 int max_ready ATTRIBUTE_UNUSED)
14290 mips_macc_chains_last_hilo = 0;
14291 vr4130_last_insn = 0;
14292 mips_74k_agen_init (NULL);
14294 /* When scheduling for Loongson2, branch instructions go to ALU1,
14295 therefore basic block is most likely to start with round-robin counter
14296 pointed to ALU2. */
14297 mips_ls2.alu1_turn_p = false;
14298 mips_ls2.falu1_turn_p = true;
14301 /* Subroutine used by TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
14304 mips_sched_reorder_1 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
14305 rtx_insn **ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
14307 if (!reload_completed
14308 && TUNE_MACC_CHAINS
14310 mips_macc_chains_reorder (ready, *nreadyp);
14312 if (reload_completed
14314 && !TARGET_VR4130_ALIGN
14316 vr4130_reorder (ready, *nreadyp);
14319 mips_74k_agen_reorder (ready, *nreadyp);
14322 /* Implement TARGET_SCHED_REORDER. */
14325 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
14326 rtx_insn **ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
14328 mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle);
14329 return mips_issue_rate ();
14332 /* Implement TARGET_SCHED_REORDER2. */
14335 mips_sched_reorder2 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
14336 rtx_insn **ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
14338 mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle);
14339 return cached_can_issue_more;
14342 /* Update round-robin counters for ALU1/2 and FALU1/2. */
14345 mips_ls2_variable_issue (rtx_insn *insn)
14347 if (mips_ls2.alu1_turn_p)
14349 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu1_core_unit_code))
14350 mips_ls2.alu1_turn_p = false;
14354 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu2_core_unit_code))
14355 mips_ls2.alu1_turn_p = true;
14358 if (mips_ls2.falu1_turn_p)
14360 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu1_core_unit_code))
14361 mips_ls2.falu1_turn_p = false;
14365 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu2_core_unit_code))
14366 mips_ls2.falu1_turn_p = true;
14369 if (recog_memoized (insn) >= 0)
14370 mips_ls2.cycle_has_multi_p |= (get_attr_type (insn) == TYPE_MULTI);
14373 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
14376 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
14377 rtx_insn *insn, int more)
14379 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
14380 if (USEFUL_INSN_P (insn))
14382 if (get_attr_type (insn) != TYPE_GHOST)
14384 if (!reload_completed && TUNE_MACC_CHAINS)
14385 mips_macc_chains_record (insn);
14386 vr4130_last_insn = insn;
14388 mips_74k_agen_init (insn);
14389 else if (TUNE_LOONGSON_2EF)
14390 mips_ls2_variable_issue (insn);
14393 /* Instructions of type 'multi' should all be split before
14394 the second scheduling pass. */
14395 gcc_assert (!reload_completed
14396 || recog_memoized (insn) < 0
14397 || get_attr_type (insn) != TYPE_MULTI);
14399 cached_can_issue_more = more;
14403 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
14404 return the first operand of the associated PREF or PREFX insn. */
14407 mips_prefetch_cookie (rtx write, rtx locality)
14409 /* store_streamed / load_streamed. */
14410 if (INTVAL (locality) <= 0)
14411 return GEN_INT (INTVAL (write) + 4);
14413 /* store / load. */
14414 if (INTVAL (locality) <= 2)
14417 /* store_retained / load_retained. */
14418 return GEN_INT (INTVAL (write) + 6);
14421 /* Flags that indicate when a built-in function is available.
14423 BUILTIN_AVAIL_NON_MIPS16
14424 The function is available on the current target if !TARGET_MIPS16.
14426 BUILTIN_AVAIL_MIPS16
14427 The function is available on the current target if TARGET_MIPS16. */
14428 #define BUILTIN_AVAIL_NON_MIPS16 1
14429 #define BUILTIN_AVAIL_MIPS16 2
14431 /* Declare an availability predicate for built-in functions that
14432 require non-MIPS16 mode and also require COND to be true.
14433 NAME is the main part of the predicate's name. */
14434 #define AVAIL_NON_MIPS16(NAME, COND) \
14435 static unsigned int \
14436 mips_builtin_avail_##NAME (void) \
14438 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
14441 /* Declare an availability predicate for built-in functions that
14442 support both MIPS16 and non-MIPS16 code and also require COND
14443 to be true. NAME is the main part of the predicate's name. */
14444 #define AVAIL_ALL(NAME, COND) \
14445 static unsigned int \
14446 mips_builtin_avail_##NAME (void) \
14448 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 | BUILTIN_AVAIL_MIPS16 : 0; \
14451 /* This structure describes a single built-in function. */
14452 struct mips_builtin_description {
14453 /* The code of the main .md file instruction. See mips_builtin_type
14454 for more information. */
14455 enum insn_code icode;
14457 /* The floating-point comparison code to use with ICODE, if any. */
14458 enum mips_fp_condition cond;
14460 /* The name of the built-in function. */
14463 /* Specifies how the function should be expanded. */
14464 enum mips_builtin_type builtin_type;
14466 /* The function's prototype. */
14467 enum mips_function_type function_type;
14469 /* Whether the function is available. */
14470 unsigned int (*avail) (void);
14473 AVAIL_ALL (hard_float, TARGET_HARD_FLOAT_ABI)
14474 AVAIL_NON_MIPS16 (paired_single, TARGET_PAIRED_SINGLE_FLOAT)
14475 AVAIL_NON_MIPS16 (sb1_paired_single, TARGET_SB1 && TARGET_PAIRED_SINGLE_FLOAT)
14476 AVAIL_NON_MIPS16 (mips3d, TARGET_MIPS3D)
14477 AVAIL_NON_MIPS16 (dsp, TARGET_DSP)
14478 AVAIL_NON_MIPS16 (dspr2, TARGET_DSPR2)
14479 AVAIL_NON_MIPS16 (dsp_32, !TARGET_64BIT && TARGET_DSP)
14480 AVAIL_NON_MIPS16 (dsp_64, TARGET_64BIT && TARGET_DSP)
14481 AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2)
14482 AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS)
14483 AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
14485 /* Construct a mips_builtin_description from the given arguments.
14487 INSN is the name of the associated instruction pattern, without the
14488 leading CODE_FOR_mips_.
14490 CODE is the floating-point condition code associated with the
14491 function. It can be 'f' if the field is not applicable.
14493 NAME is the name of the function itself, without the leading
14496 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
14498 AVAIL is the name of the availability predicate, without the leading
14499 mips_builtin_avail_. */
14500 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
14501 FUNCTION_TYPE, AVAIL) \
14502 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
14503 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
14504 mips_builtin_avail_ ## AVAIL }
14506 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
14507 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
14508 are as for MIPS_BUILTIN. */
14509 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
14510 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
14512 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
14513 are subject to mips_builtin_avail_<AVAIL>. */
14514 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
14515 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
14516 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
14517 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
14518 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
14520 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
14521 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
14522 while the any and all forms are subject to mips_builtin_avail_mips3d. */
14523 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
14524 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
14525 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
14527 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
14528 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
14530 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
14531 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
14533 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
14534 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
14537 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
14538 are subject to mips_builtin_avail_mips3d. */
14539 #define CMP_4S_BUILTINS(INSN, COND) \
14540 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
14541 MIPS_BUILTIN_CMP_ANY, \
14542 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
14543 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
14544 MIPS_BUILTIN_CMP_ALL, \
14545 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
14547 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
14548 instruction requires mips_builtin_avail_<AVAIL>. */
14549 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
14550 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
14551 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
14553 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
14554 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
14557 /* Define all the built-in functions related to C.cond.fmt condition COND. */
14558 #define CMP_BUILTINS(COND) \
14559 MOVTF_BUILTINS (c, COND, paired_single), \
14560 MOVTF_BUILTINS (cabs, COND, mips3d), \
14561 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
14562 CMP_PS_BUILTINS (c, COND, paired_single), \
14563 CMP_PS_BUILTINS (cabs, COND, mips3d), \
14564 CMP_4S_BUILTINS (c, COND), \
14565 CMP_4S_BUILTINS (cabs, COND)
14567 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
14568 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
14569 and AVAIL are as for MIPS_BUILTIN. */
14570 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
14571 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
14572 FUNCTION_TYPE, AVAIL)
14574 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
14575 branch instruction. AVAIL is as for MIPS_BUILTIN. */
14576 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
14577 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
14578 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
14580 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
14581 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
14582 builtin_description field. */
14583 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
14584 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
14585 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
14586 FUNCTION_TYPE, mips_builtin_avail_loongson }
14588 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
14589 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
14590 builtin_description field. */
14591 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
14592 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
14594 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
14595 We use functions of this form when the same insn can be usefully applied
14596 to more than one datatype. */
14597 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
14598 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
14600 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
14601 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
14602 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
14603 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
14604 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
14605 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
14606 #define CODE_FOR_mips_mult CODE_FOR_mulsidi3_32bit
14607 #define CODE_FOR_mips_multu CODE_FOR_umulsidi3_32bit
14609 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
14610 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
14611 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
14612 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
14613 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
14614 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
14615 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
14616 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
14617 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
14618 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
14619 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
14620 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
14621 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
14622 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
14623 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
14624 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
14625 #define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3
14626 #define CODE_FOR_loongson_psllh CODE_FOR_ashlv4hi3
14627 #define CODE_FOR_loongson_psllw CODE_FOR_ashlv2si3
14628 #define CODE_FOR_loongson_psrlh CODE_FOR_lshrv4hi3
14629 #define CODE_FOR_loongson_psrlw CODE_FOR_lshrv2si3
14630 #define CODE_FOR_loongson_psrah CODE_FOR_ashrv4hi3
14631 #define CODE_FOR_loongson_psraw CODE_FOR_ashrv2si3
14632 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
14633 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
14634 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
14635 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
14636 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
14637 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
14638 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
14640 static const struct mips_builtin_description mips_builtins[] = {
14641 #define MIPS_GET_FCSR 0
14642 DIRECT_BUILTIN (get_fcsr, MIPS_USI_FTYPE_VOID, hard_float),
14643 #define MIPS_SET_FCSR 1
14644 DIRECT_NO_TARGET_BUILTIN (set_fcsr, MIPS_VOID_FTYPE_USI, hard_float),
14646 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
14647 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
14648 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
14649 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
14650 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, paired_single),
14651 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, paired_single),
14652 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, paired_single),
14653 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, paired_single),
14655 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT, paired_single),
14656 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
14657 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
14658 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
14659 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, mips3d),
14661 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, mips3d),
14662 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, mips3d),
14663 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
14664 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
14665 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
14666 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
14668 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, mips3d),
14669 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, mips3d),
14670 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
14671 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
14672 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
14673 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
14675 MIPS_FP_CONDITIONS (CMP_BUILTINS),
14677 /* Built-in functions for the SB-1 processor. */
14678 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, sb1_paired_single),
14680 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
14681 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
14682 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
14683 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
14684 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
14685 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
14686 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
14687 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
14688 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
14689 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
14690 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
14691 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, dsp),
14692 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, dsp),
14693 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, dsp),
14694 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, dsp),
14695 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, dsp),
14696 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, dsp),
14697 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
14698 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
14699 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
14700 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
14701 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, dsp),
14702 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, dsp),
14703 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
14704 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
14705 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
14706 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
14707 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
14708 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
14709 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
14710 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
14711 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
14712 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
14713 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
14714 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
14715 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
14716 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
14717 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
14718 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, dsp),
14719 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
14720 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
14721 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
14722 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
14723 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
14724 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, dsp),
14725 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, dsp),
14726 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, dsp),
14727 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, dsp),
14728 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
14729 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
14730 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
14731 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
14732 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
14733 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
14734 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
14735 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
14736 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
14737 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
14738 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
14739 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
14740 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, dsp),
14741 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, dsp),
14742 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_POINTER_SI, dsp),
14743 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_POINTER_SI, dsp),
14744 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_POINTER_SI, dsp),
14745 BPOSGE_BUILTIN (32, dsp),
14747 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
14748 DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, dspr2),
14749 DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14750 DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14751 DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
14752 DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
14753 DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
14754 DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
14755 DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
14756 DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
14757 DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
14758 DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14759 DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14760 DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, dspr2),
14761 DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14762 DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, dspr2),
14763 DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dspr2),
14764 DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
14765 DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
14766 DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
14767 DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
14768 DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
14769 DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, dspr2),
14770 DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14771 DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14772 DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
14773 DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
14774 DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14775 DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14776 DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
14777 DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
14778 DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14779 DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14780 DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
14781 DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
14783 /* Built-in functions for the DSP ASE (32-bit only). */
14784 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
14785 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
14786 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
14787 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
14788 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
14789 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
14790 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
14791 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
14792 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
14793 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
14794 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
14795 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
14796 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
14797 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
14798 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
14799 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
14800 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, dsp_32),
14801 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, dsp_32),
14802 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, dsp_32),
14803 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, dsp_32),
14804 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, dsp_32),
14805 DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
14806 DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32),
14807 DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
14808 DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32),
14809 DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, dsp_32),
14810 DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, dsp_32),
14812 /* Built-in functions for the DSP ASE (64-bit only). */
14813 DIRECT_BUILTIN (ldx, MIPS_DI_FTYPE_POINTER_SI, dsp_64),
14815 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
14816 DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14817 DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14818 DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14819 DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14820 DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14821 DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14822 DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14823 DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14824 DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14826 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
14827 LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI),
14828 LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI),
14829 LOONGSON_BUILTIN (packushb, MIPS_UV8QI_FTYPE_UV4HI_UV4HI),
14830 LOONGSON_BUILTIN_SUFFIX (paddw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14831 LOONGSON_BUILTIN_SUFFIX (paddh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14832 LOONGSON_BUILTIN_SUFFIX (paddb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14833 LOONGSON_BUILTIN_SUFFIX (paddw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14834 LOONGSON_BUILTIN_SUFFIX (paddh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14835 LOONGSON_BUILTIN_SUFFIX (paddb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14836 LOONGSON_BUILTIN_SUFFIX (paddd, u, MIPS_UDI_FTYPE_UDI_UDI),
14837 LOONGSON_BUILTIN_SUFFIX (paddd, s, MIPS_DI_FTYPE_DI_DI),
14838 LOONGSON_BUILTIN (paddsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14839 LOONGSON_BUILTIN (paddsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
14840 LOONGSON_BUILTIN (paddush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14841 LOONGSON_BUILTIN (paddusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14842 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_ud, MIPS_UDI_FTYPE_UDI_UDI),
14843 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_uw, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14844 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_uh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14845 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_ub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14846 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_sd, MIPS_DI_FTYPE_DI_DI),
14847 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_sw, MIPS_V2SI_FTYPE_V2SI_V2SI),
14848 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_sh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14849 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_sb, MIPS_V8QI_FTYPE_V8QI_V8QI),
14850 LOONGSON_BUILTIN (pavgh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14851 LOONGSON_BUILTIN (pavgb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14852 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14853 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14854 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14855 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14856 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14857 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14858 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14859 LOONGSON_BUILTIN_SUFFIX (pcmpgth, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14860 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14861 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14862 LOONGSON_BUILTIN_SUFFIX (pcmpgth, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14863 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14864 LOONGSON_BUILTIN_SUFFIX (pextrh, u, MIPS_UV4HI_FTYPE_UV4HI_USI),
14865 LOONGSON_BUILTIN_SUFFIX (pextrh, s, MIPS_V4HI_FTYPE_V4HI_USI),
14866 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14867 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14868 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14869 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14870 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14871 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14872 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14873 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14874 LOONGSON_BUILTIN (pmaddhw, MIPS_V2SI_FTYPE_V4HI_V4HI),
14875 LOONGSON_BUILTIN (pmaxsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14876 LOONGSON_BUILTIN (pmaxub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14877 LOONGSON_BUILTIN (pminsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14878 LOONGSON_BUILTIN (pminub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14879 LOONGSON_BUILTIN_SUFFIX (pmovmskb, u, MIPS_UV8QI_FTYPE_UV8QI),
14880 LOONGSON_BUILTIN_SUFFIX (pmovmskb, s, MIPS_V8QI_FTYPE_V8QI),
14881 LOONGSON_BUILTIN (pmulhuh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14882 LOONGSON_BUILTIN (pmulhh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14883 LOONGSON_BUILTIN (pmullh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14884 LOONGSON_BUILTIN (pmuluw, MIPS_UDI_FTYPE_UV2SI_UV2SI),
14885 LOONGSON_BUILTIN (pasubub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14886 LOONGSON_BUILTIN (biadd, MIPS_UV4HI_FTYPE_UV8QI),
14887 LOONGSON_BUILTIN (psadbh, MIPS_UV4HI_FTYPE_UV8QI_UV8QI),
14888 LOONGSON_BUILTIN_SUFFIX (pshufh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
14889 LOONGSON_BUILTIN_SUFFIX (pshufh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
14890 LOONGSON_BUILTIN_SUFFIX (psllh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
14891 LOONGSON_BUILTIN_SUFFIX (psllh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
14892 LOONGSON_BUILTIN_SUFFIX (psllw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
14893 LOONGSON_BUILTIN_SUFFIX (psllw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
14894 LOONGSON_BUILTIN_SUFFIX (psrah, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
14895 LOONGSON_BUILTIN_SUFFIX (psrah, s, MIPS_V4HI_FTYPE_V4HI_UQI),
14896 LOONGSON_BUILTIN_SUFFIX (psraw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
14897 LOONGSON_BUILTIN_SUFFIX (psraw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
14898 LOONGSON_BUILTIN_SUFFIX (psrlh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
14899 LOONGSON_BUILTIN_SUFFIX (psrlh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
14900 LOONGSON_BUILTIN_SUFFIX (psrlw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
14901 LOONGSON_BUILTIN_SUFFIX (psrlw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
14902 LOONGSON_BUILTIN_SUFFIX (psubw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14903 LOONGSON_BUILTIN_SUFFIX (psubh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14904 LOONGSON_BUILTIN_SUFFIX (psubb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14905 LOONGSON_BUILTIN_SUFFIX (psubw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14906 LOONGSON_BUILTIN_SUFFIX (psubh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14907 LOONGSON_BUILTIN_SUFFIX (psubb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14908 LOONGSON_BUILTIN_SUFFIX (psubd, u, MIPS_UDI_FTYPE_UDI_UDI),
14909 LOONGSON_BUILTIN_SUFFIX (psubd, s, MIPS_DI_FTYPE_DI_DI),
14910 LOONGSON_BUILTIN (psubsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14911 LOONGSON_BUILTIN (psubsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
14912 LOONGSON_BUILTIN (psubush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14913 LOONGSON_BUILTIN (psubusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14914 LOONGSON_BUILTIN_SUFFIX (punpckhbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14915 LOONGSON_BUILTIN_SUFFIX (punpckhhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14916 LOONGSON_BUILTIN_SUFFIX (punpckhwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14917 LOONGSON_BUILTIN_SUFFIX (punpckhbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14918 LOONGSON_BUILTIN_SUFFIX (punpckhhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14919 LOONGSON_BUILTIN_SUFFIX (punpckhwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14920 LOONGSON_BUILTIN_SUFFIX (punpcklbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14921 LOONGSON_BUILTIN_SUFFIX (punpcklhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14922 LOONGSON_BUILTIN_SUFFIX (punpcklwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14923 LOONGSON_BUILTIN_SUFFIX (punpcklbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14924 LOONGSON_BUILTIN_SUFFIX (punpcklhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14925 LOONGSON_BUILTIN_SUFFIX (punpcklwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14927 /* Sundry other built-in functions. */
14928 DIRECT_NO_TARGET_BUILTIN (cache, MIPS_VOID_FTYPE_SI_CVPOINTER, cache)
14931 /* Index I is the function declaration for mips_builtins[I], or null if the
14932 function isn't defined on this target. */
14933 static GTY(()) tree mips_builtin_decls[ARRAY_SIZE (mips_builtins)];
14935 /* MODE is a vector mode whose elements have type TYPE. Return the type
14936 of the vector itself. */
14939 mips_builtin_vector_type (tree type, machine_mode mode)
14941 static tree types[2 * (int) MAX_MACHINE_MODE];
14944 mode_index = (int) mode;
14946 if (TREE_CODE (type) == INTEGER_TYPE && TYPE_UNSIGNED (type))
14947 mode_index += MAX_MACHINE_MODE;
14949 if (types[mode_index] == NULL_TREE)
14950 types[mode_index] = build_vector_type_for_mode (type, mode);
14951 return types[mode_index];
14954 /* Return a type for 'const volatile void *'. */
14957 mips_build_cvpointer_type (void)
14961 if (cache == NULL_TREE)
14962 cache = build_pointer_type (build_qualified_type
14964 TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE));
14968 /* Source-level argument types. */
14969 #define MIPS_ATYPE_VOID void_type_node
14970 #define MIPS_ATYPE_INT integer_type_node
14971 #define MIPS_ATYPE_POINTER ptr_type_node
14972 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
14974 /* Standard mode-based argument types. */
14975 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
14976 #define MIPS_ATYPE_SI intSI_type_node
14977 #define MIPS_ATYPE_USI unsigned_intSI_type_node
14978 #define MIPS_ATYPE_DI intDI_type_node
14979 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
14980 #define MIPS_ATYPE_SF float_type_node
14981 #define MIPS_ATYPE_DF double_type_node
14983 /* Vector argument types. */
14984 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
14985 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
14986 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
14987 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
14988 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
14989 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
14990 #define MIPS_ATYPE_UV2SI \
14991 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
14992 #define MIPS_ATYPE_UV4HI \
14993 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
14994 #define MIPS_ATYPE_UV8QI \
14995 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
14997 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
14998 their associated MIPS_ATYPEs. */
14999 #define MIPS_FTYPE_ATYPES1(A, B) \
15000 MIPS_ATYPE_##A, MIPS_ATYPE_##B
15002 #define MIPS_FTYPE_ATYPES2(A, B, C) \
15003 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
15005 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
15006 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
15008 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
15009 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
15012 /* Return the function type associated with function prototype TYPE. */
15015 mips_build_function_type (enum mips_function_type type)
15017 static tree types[(int) MIPS_MAX_FTYPE_MAX];
15019 if (types[(int) type] == NULL_TREE)
15022 #define DEF_MIPS_FTYPE(NUM, ARGS) \
15023 case MIPS_FTYPE_NAME##NUM ARGS: \
15024 types[(int) type] \
15025 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
15028 #include "config/mips/mips-ftypes.def"
15029 #undef DEF_MIPS_FTYPE
15031 gcc_unreachable ();
15034 return types[(int) type];
15037 /* Implement TARGET_INIT_BUILTINS. */
15040 mips_init_builtins (void)
15042 const struct mips_builtin_description *d;
15045 /* Iterate through all of the bdesc arrays, initializing all of the
15046 builtin functions. */
15047 for (i = 0; i < ARRAY_SIZE (mips_builtins); i++)
15049 d = &mips_builtins[i];
15051 mips_builtin_decls[i]
15052 = add_builtin_function (d->name,
15053 mips_build_function_type (d->function_type),
15054 i, BUILT_IN_MD, NULL, NULL);
15058 /* Implement TARGET_BUILTIN_DECL. */
15061 mips_builtin_decl (unsigned int code, bool initialize_p ATTRIBUTE_UNUSED)
15063 if (code >= ARRAY_SIZE (mips_builtins))
15064 return error_mark_node;
15065 return mips_builtin_decls[code];
15068 /* Take argument ARGNO from EXP's argument list and convert it into
15069 an expand operand. Store the operand in *OP. */
15072 mips_prepare_builtin_arg (struct expand_operand *op, tree exp,
15073 unsigned int argno)
15078 arg = CALL_EXPR_ARG (exp, argno);
15079 value = expand_normal (arg);
15080 create_input_operand (op, value, TYPE_MODE (TREE_TYPE (arg)));
15083 /* Expand instruction ICODE as part of a built-in function sequence.
15084 Use the first NOPS elements of OPS as the instruction's operands.
15085 HAS_TARGET_P is true if operand 0 is a target; it is false if the
15086 instruction has no target.
15088 Return the target rtx if HAS_TARGET_P, otherwise return const0_rtx. */
15091 mips_expand_builtin_insn (enum insn_code icode, unsigned int nops,
15092 struct expand_operand *ops, bool has_target_p)
15094 if (!maybe_expand_insn (icode, nops, ops))
15096 error ("invalid argument to built-in function");
15097 return has_target_p ? gen_reg_rtx (ops[0].mode) : const0_rtx;
15099 return has_target_p ? ops[0].value : const0_rtx;
15102 /* Expand a floating-point comparison for built-in function call EXP.
15103 The first NARGS arguments are the values to be compared. ICODE is
15104 the .md pattern that does the comparison and COND is the condition
15105 that is being tested. Return an rtx for the result. */
15108 mips_expand_builtin_compare_1 (enum insn_code icode,
15109 enum mips_fp_condition cond,
15110 tree exp, int nargs)
15112 struct expand_operand ops[MAX_RECOG_OPERANDS];
15116 /* The instruction should have a target operand, an operand for each
15117 argument, and an operand for COND. */
15118 gcc_assert (nargs + 2 == insn_data[(int) icode].n_generator_args);
15120 output = mips_allocate_fcc (insn_data[(int) icode].operand[0].mode);
15122 create_fixed_operand (&ops[opno++], output);
15123 for (argno = 0; argno < nargs; argno++)
15124 mips_prepare_builtin_arg (&ops[opno++], exp, argno);
15125 create_integer_operand (&ops[opno++], (int) cond);
15126 return mips_expand_builtin_insn (icode, opno, ops, true);
15129 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
15130 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
15131 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
15132 suggests a good place to put the result. */
15135 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
15138 struct expand_operand ops[MAX_RECOG_OPERANDS];
15141 /* Map any target to operand 0. */
15144 create_output_operand (&ops[opno++], target, TYPE_MODE (TREE_TYPE (exp)));
15146 /* Map the arguments to the other operands. */
15147 gcc_assert (opno + call_expr_nargs (exp)
15148 == insn_data[icode].n_generator_args);
15149 for (argno = 0; argno < call_expr_nargs (exp); argno++)
15150 mips_prepare_builtin_arg (&ops[opno++], exp, argno);
15152 return mips_expand_builtin_insn (icode, opno, ops, has_target_p);
15155 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
15156 function; TYPE says which. EXP is the CALL_EXPR that calls the
15157 function, ICODE is the instruction that should be used to compare
15158 the first two arguments, and COND is the condition it should test.
15159 TARGET, if nonnull, suggests a good place to put the result. */
15162 mips_expand_builtin_movtf (enum mips_builtin_type type,
15163 enum insn_code icode, enum mips_fp_condition cond,
15164 rtx target, tree exp)
15166 struct expand_operand ops[4];
15169 cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp, 2);
15170 create_output_operand (&ops[0], target, TYPE_MODE (TREE_TYPE (exp)));
15171 if (type == MIPS_BUILTIN_MOVT)
15173 mips_prepare_builtin_arg (&ops[2], exp, 2);
15174 mips_prepare_builtin_arg (&ops[1], exp, 3);
15178 mips_prepare_builtin_arg (&ops[1], exp, 2);
15179 mips_prepare_builtin_arg (&ops[2], exp, 3);
15181 create_fixed_operand (&ops[3], cmp_result);
15182 return mips_expand_builtin_insn (CODE_FOR_mips_cond_move_tf_ps,
15186 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
15187 into TARGET otherwise. Return TARGET. */
15190 mips_builtin_branch_and_move (rtx condition, rtx target,
15191 rtx value_if_true, rtx value_if_false)
15193 rtx_code_label *true_label, *done_label;
15195 true_label = gen_label_rtx ();
15196 done_label = gen_label_rtx ();
15198 /* First assume that CONDITION is false. */
15199 mips_emit_move (target, value_if_false);
15201 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
15202 emit_jump_insn (gen_condjump (condition, true_label));
15203 emit_jump_insn (gen_jump (done_label));
15206 /* Fix TARGET if CONDITION is true. */
15207 emit_label (true_label);
15208 mips_emit_move (target, value_if_true);
15210 emit_label (done_label);
15214 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
15215 the CALL_EXPR that calls the function, ICODE is the code of the
15216 comparison instruction, and COND is the condition it should test.
15217 TARGET, if nonnull, suggests a good place to put the boolean result. */
15220 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
15221 enum insn_code icode, enum mips_fp_condition cond,
15222 rtx target, tree exp)
15224 rtx offset, condition, cmp_result;
15226 if (target == 0 || GET_MODE (target) != SImode)
15227 target = gen_reg_rtx (SImode);
15228 cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp,
15229 call_expr_nargs (exp));
15231 /* If the comparison sets more than one register, we define the result
15232 to be 0 if all registers are false and -1 if all registers are true.
15233 The value of the complete result is indeterminate otherwise. */
15234 switch (builtin_type)
15236 case MIPS_BUILTIN_CMP_ALL:
15237 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
15238 return mips_builtin_branch_and_move (condition, target,
15239 const0_rtx, const1_rtx);
15241 case MIPS_BUILTIN_CMP_UPPER:
15242 case MIPS_BUILTIN_CMP_LOWER:
15243 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
15244 condition = gen_single_cc (cmp_result, offset);
15245 return mips_builtin_branch_and_move (condition, target,
15246 const1_rtx, const0_rtx);
15249 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
15250 return mips_builtin_branch_and_move (condition, target,
15251 const1_rtx, const0_rtx);
15255 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
15256 if nonnull, suggests a good place to put the boolean result. */
15259 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
15261 rtx condition, cmp_result;
15264 if (target == 0 || GET_MODE (target) != SImode)
15265 target = gen_reg_rtx (SImode);
15267 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
15269 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
15274 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
15275 return mips_builtin_branch_and_move (condition, target,
15276 const1_rtx, const0_rtx);
15279 /* Implement TARGET_EXPAND_BUILTIN. */
15282 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
15283 machine_mode mode, int ignore)
15286 unsigned int fcode, avail;
15287 const struct mips_builtin_description *d;
15289 fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
15290 fcode = DECL_FUNCTION_CODE (fndecl);
15291 gcc_assert (fcode < ARRAY_SIZE (mips_builtins));
15292 d = &mips_builtins[fcode];
15293 avail = d->avail ();
15294 gcc_assert (avail != 0);
15295 if (TARGET_MIPS16 && !(avail & BUILTIN_AVAIL_MIPS16))
15297 error ("built-in function %qE not supported for MIPS16",
15298 DECL_NAME (fndecl));
15299 return ignore ? const0_rtx : CONST0_RTX (mode);
15301 switch (d->builtin_type)
15303 case MIPS_BUILTIN_DIRECT:
15304 return mips_expand_builtin_direct (d->icode, target, exp, true);
15306 case MIPS_BUILTIN_DIRECT_NO_TARGET:
15307 return mips_expand_builtin_direct (d->icode, target, exp, false);
15309 case MIPS_BUILTIN_MOVT:
15310 case MIPS_BUILTIN_MOVF:
15311 return mips_expand_builtin_movtf (d->builtin_type, d->icode,
15312 d->cond, target, exp);
15314 case MIPS_BUILTIN_CMP_ANY:
15315 case MIPS_BUILTIN_CMP_ALL:
15316 case MIPS_BUILTIN_CMP_UPPER:
15317 case MIPS_BUILTIN_CMP_LOWER:
15318 case MIPS_BUILTIN_CMP_SINGLE:
15319 return mips_expand_builtin_compare (d->builtin_type, d->icode,
15320 d->cond, target, exp);
15322 case MIPS_BUILTIN_BPOSGE32:
15323 return mips_expand_builtin_bposge (d->builtin_type, target);
15325 gcc_unreachable ();
15328 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
15329 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
15330 struct mips16_constant {
15331 struct mips16_constant *next;
15333 rtx_code_label *label;
15337 /* Information about an incomplete MIPS16 constant pool. FIRST is the
15338 first constant, HIGHEST_ADDRESS is the highest address that the first
15339 byte of the pool can have, and INSN_ADDRESS is the current instruction
15341 struct mips16_constant_pool {
15342 struct mips16_constant *first;
15343 int highest_address;
15347 /* Add constant VALUE to POOL and return its label. MODE is the
15348 value's mode (used for CONST_INTs, etc.). */
15350 static rtx_code_label *
15351 mips16_add_constant (struct mips16_constant_pool *pool,
15352 rtx value, machine_mode mode)
15354 struct mips16_constant **p, *c;
15355 bool first_of_size_p;
15357 /* See whether the constant is already in the pool. If so, return the
15358 existing label, otherwise leave P pointing to the place where the
15359 constant should be added.
15361 Keep the pool sorted in increasing order of mode size so that we can
15362 reduce the number of alignments needed. */
15363 first_of_size_p = true;
15364 for (p = &pool->first; *p != 0; p = &(*p)->next)
15366 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
15367 return (*p)->label;
15368 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
15370 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
15371 first_of_size_p = false;
15374 /* In the worst case, the constant needed by the earliest instruction
15375 will end up at the end of the pool. The entire pool must then be
15376 accessible from that instruction.
15378 When adding the first constant, set the pool's highest address to
15379 the address of the first out-of-range byte. Adjust this address
15380 downwards each time a new constant is added. */
15381 if (pool->first == 0)
15382 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
15383 of the instruction with the lowest two bits clear. The base PC
15384 value for LDPC has the lowest three bits clear. Assume the worst
15385 case here; namely that the PC-relative instruction occupies the
15386 last 2 bytes in an aligned word. */
15387 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
15388 pool->highest_address -= GET_MODE_SIZE (mode);
15389 if (first_of_size_p)
15390 /* Take into account the worst possible padding due to alignment. */
15391 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
15393 /* Create a new entry. */
15394 c = XNEW (struct mips16_constant);
15397 c->label = gen_label_rtx ();
15404 /* Output constant VALUE after instruction INSN and return the last
15405 instruction emitted. MODE is the mode of the constant. */
15408 mips16_emit_constants_1 (machine_mode mode, rtx value, rtx_insn *insn)
15410 if (SCALAR_INT_MODE_P (mode) || ALL_SCALAR_FIXED_POINT_MODE_P (mode))
15412 rtx size = GEN_INT (GET_MODE_SIZE (mode));
15413 return emit_insn_after (gen_consttable_int (value, size), insn);
15416 if (SCALAR_FLOAT_MODE_P (mode))
15417 return emit_insn_after (gen_consttable_float (value), insn);
15419 if (VECTOR_MODE_P (mode))
15423 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
15424 insn = mips16_emit_constants_1 (GET_MODE_INNER (mode),
15425 CONST_VECTOR_ELT (value, i), insn);
15429 gcc_unreachable ();
15432 /* Dump out the constants in CONSTANTS after INSN. */
15435 mips16_emit_constants (struct mips16_constant *constants, rtx_insn *insn)
15437 struct mips16_constant *c, *next;
15441 for (c = constants; c != NULL; c = next)
15443 /* If necessary, increase the alignment of PC. */
15444 if (align < GET_MODE_SIZE (c->mode))
15446 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
15447 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
15449 align = GET_MODE_SIZE (c->mode);
15451 insn = emit_label_after (c->label, insn);
15452 insn = mips16_emit_constants_1 (c->mode, c->value, insn);
15458 emit_barrier_after (insn);
15461 /* Return the length of instruction INSN. */
15464 mips16_insn_length (rtx_insn *insn)
15466 if (JUMP_TABLE_DATA_P (insn))
15468 rtx body = PATTERN (insn);
15469 if (GET_CODE (body) == ADDR_VEC)
15470 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
15471 else if (GET_CODE (body) == ADDR_DIFF_VEC)
15472 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
15474 gcc_unreachable ();
15476 return get_attr_length (insn);
15479 /* If *X is a symbolic constant that refers to the constant pool, add
15480 the constant to POOL and rewrite *X to use the constant's label. */
15483 mips16_rewrite_pool_constant (struct mips16_constant_pool *pool, rtx *x)
15486 rtx_code_label *label;
15488 split_const (*x, &base, &offset);
15489 if (GET_CODE (base) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (base))
15491 label = mips16_add_constant (pool, copy_rtx (get_pool_constant (base)),
15492 get_pool_mode (base));
15493 base = gen_rtx_LABEL_REF (Pmode, label);
15494 *x = mips_unspec_address_offset (base, offset, SYMBOL_PC_RELATIVE);
15498 /* Rewrite INSN so that constant pool references refer to the constant's
15502 mips16_rewrite_pool_refs (rtx_insn *insn, struct mips16_constant_pool *pool)
15504 subrtx_ptr_iterator::array_type array;
15505 FOR_EACH_SUBRTX_PTR (iter, array, &PATTERN (insn), ALL)
15509 if (force_to_mem_operand (*loc, Pmode))
15511 rtx mem = force_const_mem (GET_MODE (*loc), *loc);
15512 validate_change (insn, loc, mem, false);
15517 mips16_rewrite_pool_constant (pool, &XEXP (*loc, 0));
15518 iter.skip_subrtxes ();
15522 if (TARGET_MIPS16_TEXT_LOADS)
15523 mips16_rewrite_pool_constant (pool, loc);
15524 if (GET_CODE (*loc) == CONST
15525 /* Don't rewrite the __mips16_rdwr symbol. */
15526 || (GET_CODE (*loc) == UNSPEC
15527 && XINT (*loc, 1) == UNSPEC_TLS_GET_TP))
15528 iter.skip_subrtxes ();
15533 /* Return whether CFG is used in mips_reorg. */
15536 mips_cfg_in_reorg (void)
15538 return (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
15539 || TARGET_RELAX_PIC_CALLS);
15542 /* Build MIPS16 constant pools. Split the instructions if SPLIT_P,
15543 otherwise assume that they are already split. */
15546 mips16_lay_out_constants (bool split_p)
15548 struct mips16_constant_pool pool;
15549 rtx_insn *insn, *barrier;
15551 if (!TARGET_MIPS16_PCREL_LOADS)
15556 if (mips_cfg_in_reorg ())
15557 split_all_insns ();
15559 split_all_insns_noflow ();
15562 memset (&pool, 0, sizeof (pool));
15563 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
15565 /* Rewrite constant pool references in INSN. */
15566 if (USEFUL_INSN_P (insn))
15567 mips16_rewrite_pool_refs (insn, &pool);
15569 pool.insn_address += mips16_insn_length (insn);
15571 if (pool.first != NULL)
15573 /* If there are no natural barriers between the first user of
15574 the pool and the highest acceptable address, we'll need to
15575 create a new instruction to jump around the constant pool.
15576 In the worst case, this instruction will be 4 bytes long.
15578 If it's too late to do this transformation after INSN,
15579 do it immediately before INSN. */
15580 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
15582 rtx_code_label *label;
15585 label = gen_label_rtx ();
15587 jump = emit_jump_insn_before (gen_jump (label), insn);
15588 JUMP_LABEL (jump) = label;
15589 LABEL_NUSES (label) = 1;
15590 barrier = emit_barrier_after (jump);
15592 emit_label_after (label, barrier);
15593 pool.insn_address += 4;
15596 /* See whether the constant pool is now out of range of the first
15597 user. If so, output the constants after the previous barrier.
15598 Note that any instructions between BARRIER and INSN (inclusive)
15599 will use negative offsets to refer to the pool. */
15600 if (pool.insn_address > pool.highest_address)
15602 mips16_emit_constants (pool.first, barrier);
15606 else if (BARRIER_P (insn))
15610 mips16_emit_constants (pool.first, get_last_insn ());
15613 /* Return true if it is worth r10k_simplify_address's while replacing
15614 an address with X. We are looking for constants, and for addresses
15615 at a known offset from the incoming stack pointer. */
15618 r10k_simplified_address_p (rtx x)
15620 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
15622 return x == virtual_incoming_args_rtx || CONSTANT_P (x);
15625 /* X is an expression that appears in INSN. Try to use the UD chains
15626 to simplify it, returning the simplified form on success and the
15627 original form otherwise. Replace the incoming value of $sp with
15628 virtual_incoming_args_rtx (which should never occur in X otherwise). */
15631 r10k_simplify_address (rtx x, rtx_insn *insn)
15633 rtx newx, op0, op1, set, note;
15634 rtx_insn *def_insn;
15636 struct df_link *defs;
15641 op0 = r10k_simplify_address (XEXP (x, 0), insn);
15642 if (op0 != XEXP (x, 0))
15643 newx = simplify_gen_unary (GET_CODE (x), GET_MODE (x),
15644 op0, GET_MODE (XEXP (x, 0)));
15646 else if (BINARY_P (x))
15648 op0 = r10k_simplify_address (XEXP (x, 0), insn);
15649 op1 = r10k_simplify_address (XEXP (x, 1), insn);
15650 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
15651 newx = simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
15653 else if (GET_CODE (x) == LO_SUM)
15655 /* LO_SUMs can be offset from HIGHs, if we know they won't
15656 overflow. See mips_classify_address for the rationale behind
15658 op0 = r10k_simplify_address (XEXP (x, 0), insn);
15659 if (GET_CODE (op0) == HIGH)
15660 newx = XEXP (x, 1);
15662 else if (REG_P (x))
15664 /* Uses are recorded by regno_reg_rtx, not X itself. */
15665 use = df_find_use (insn, regno_reg_rtx[REGNO (x)]);
15667 defs = DF_REF_CHAIN (use);
15669 /* Require a single definition. */
15670 if (defs && defs->next == NULL)
15673 if (DF_REF_IS_ARTIFICIAL (def))
15675 /* Replace the incoming value of $sp with
15676 virtual_incoming_args_rtx. */
15677 if (x == stack_pointer_rtx
15678 && DF_REF_BB (def) == ENTRY_BLOCK_PTR_FOR_FN (cfun))
15679 newx = virtual_incoming_args_rtx;
15681 else if (dominated_by_p (CDI_DOMINATORS, DF_REF_BB (use),
15684 /* Make sure that DEF_INSN is a single set of REG. */
15685 def_insn = DF_REF_INSN (def);
15686 if (NONJUMP_INSN_P (def_insn))
15688 set = single_set (def_insn);
15689 if (set && rtx_equal_p (SET_DEST (set), x))
15691 /* Prefer to use notes, since the def-use chains
15692 are often shorter. */
15693 note = find_reg_equal_equiv_note (def_insn);
15695 newx = XEXP (note, 0);
15697 newx = SET_SRC (set);
15698 newx = r10k_simplify_address (newx, def_insn);
15704 if (newx && r10k_simplified_address_p (newx))
15709 /* Return true if ADDRESS is known to be an uncached address
15710 on R10K systems. */
15713 r10k_uncached_address_p (unsigned HOST_WIDE_INT address)
15715 unsigned HOST_WIDE_INT upper;
15717 /* Check for KSEG1. */
15718 if (address + 0x60000000 < 0x20000000)
15721 /* Check for uncached XKPHYS addresses. */
15722 if (Pmode == DImode)
15724 upper = (address >> 40) & 0xf9ffff;
15725 if (upper == 0x900000 || upper == 0xb80000)
15731 /* Return true if we can prove that an access to address X in instruction
15732 INSN would be safe from R10K speculation. This X is a general
15733 expression; it might not be a legitimate address. */
15736 r10k_safe_address_p (rtx x, rtx_insn *insn)
15739 HOST_WIDE_INT offset_val;
15741 x = r10k_simplify_address (x, insn);
15743 /* Check for references to the stack frame. It doesn't really matter
15744 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
15745 allows us to assume that accesses to any part of the eventual frame
15746 is safe from speculation at any point in the function. */
15747 mips_split_plus (x, &base, &offset_val);
15748 if (base == virtual_incoming_args_rtx
15749 && offset_val >= -cfun->machine->frame.total_size
15750 && offset_val < cfun->machine->frame.args_size)
15753 /* Check for uncached addresses. */
15754 if (CONST_INT_P (x))
15755 return r10k_uncached_address_p (INTVAL (x));
15757 /* Check for accesses to a static object. */
15758 split_const (x, &base, &offset);
15759 return offset_within_block_p (base, INTVAL (offset));
15762 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
15763 an in-range access to an automatic variable, or to an object with
15764 a link-time-constant address. */
15767 r10k_safe_mem_expr_p (tree expr, unsigned HOST_WIDE_INT offset)
15769 HOST_WIDE_INT bitoffset, bitsize;
15770 tree inner, var_offset;
15772 int unsigned_p, reverse_p, volatile_p;
15774 inner = get_inner_reference (expr, &bitsize, &bitoffset, &var_offset, &mode,
15775 &unsigned_p, &reverse_p, &volatile_p, false);
15776 if (!DECL_P (inner) || !DECL_SIZE_UNIT (inner) || var_offset)
15779 offset += bitoffset / BITS_PER_UNIT;
15780 return offset < tree_to_uhwi (DECL_SIZE_UNIT (inner));
15783 /* Return true if X contains a MEM that is not safe from R10K speculation.
15784 INSN is the instruction that contains X. */
15787 r10k_needs_protection_p_1 (rtx x, rtx_insn *insn)
15789 subrtx_var_iterator::array_type array;
15790 FOR_EACH_SUBRTX_VAR (iter, array, x, NONCONST)
15795 if ((MEM_EXPR (mem)
15796 && MEM_OFFSET_KNOWN_P (mem)
15797 && r10k_safe_mem_expr_p (MEM_EXPR (mem), MEM_OFFSET (mem)))
15798 || r10k_safe_address_p (XEXP (mem, 0), insn))
15799 iter.skip_subrtxes ();
15807 /* A note_stores callback for which DATA points to an instruction pointer.
15808 If *DATA is nonnull, make it null if it X contains a MEM that is not
15809 safe from R10K speculation. */
15812 r10k_needs_protection_p_store (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
15815 rtx_insn **insn_ptr;
15817 insn_ptr = (rtx_insn **) data;
15818 if (*insn_ptr && r10k_needs_protection_p_1 (x, *insn_ptr))
15822 /* X is the pattern of a call instruction. Return true if the call is
15823 not to a declared function. */
15826 r10k_needs_protection_p_call (const_rtx x)
15828 subrtx_iterator::array_type array;
15829 FOR_EACH_SUBRTX (iter, array, x, NONCONST)
15831 const_rtx mem = *iter;
15834 const_rtx addr = XEXP (mem, 0);
15835 if (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_DECL (addr))
15836 iter.skip_subrtxes ();
15844 /* Return true if instruction INSN needs to be protected by an R10K
15848 r10k_needs_protection_p (rtx_insn *insn)
15851 return r10k_needs_protection_p_call (PATTERN (insn));
15853 if (mips_r10k_cache_barrier == R10K_CACHE_BARRIER_STORE)
15855 note_stores (PATTERN (insn), r10k_needs_protection_p_store, &insn);
15856 return insn == NULL_RTX;
15859 return r10k_needs_protection_p_1 (PATTERN (insn), insn);
15862 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
15863 edge is unconditional. */
15866 r10k_protected_bb_p (basic_block bb, sbitmap protected_bbs)
15871 FOR_EACH_EDGE (e, ei, bb->preds)
15872 if (!single_succ_p (e->src)
15873 || !bitmap_bit_p (protected_bbs, e->src->index)
15874 || (e->flags & EDGE_COMPLEX) != 0)
15879 /* Implement -mr10k-cache-barrier= for the current function. */
15882 r10k_insert_cache_barriers (void)
15884 int *rev_post_order;
15887 sbitmap protected_bbs;
15888 rtx_insn *insn, *end;
15889 rtx unprotected_region;
15893 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
15897 /* Calculate dominators. */
15898 calculate_dominance_info (CDI_DOMINATORS);
15900 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
15901 X is protected by a cache barrier. */
15902 protected_bbs = sbitmap_alloc (last_basic_block_for_fn (cfun));
15903 bitmap_clear (protected_bbs);
15905 /* Iterate over the basic blocks in reverse post-order. */
15906 rev_post_order = XNEWVEC (int, last_basic_block_for_fn (cfun));
15907 n = pre_and_rev_post_order_compute (NULL, rev_post_order, false);
15908 for (i = 0; i < n; i++)
15910 bb = BASIC_BLOCK_FOR_FN (cfun, rev_post_order[i]);
15912 /* If this block is only reached by unconditional edges, and if the
15913 source of every edge is protected, the beginning of the block is
15915 if (r10k_protected_bb_p (bb, protected_bbs))
15916 unprotected_region = NULL_RTX;
15918 unprotected_region = pc_rtx;
15919 end = NEXT_INSN (BB_END (bb));
15921 /* UNPROTECTED_REGION is:
15923 - null if we are processing a protected region,
15924 - pc_rtx if we are processing an unprotected region but have
15925 not yet found the first instruction in it
15926 - the first instruction in an unprotected region otherwise. */
15927 for (insn = BB_HEAD (bb); insn != end; insn = NEXT_INSN (insn))
15929 if (unprotected_region && USEFUL_INSN_P (insn))
15931 if (recog_memoized (insn) == CODE_FOR_mips_cache)
15932 /* This CACHE instruction protects the following code. */
15933 unprotected_region = NULL_RTX;
15936 /* See if INSN is the first instruction in this
15937 unprotected region. */
15938 if (unprotected_region == pc_rtx)
15939 unprotected_region = insn;
15941 /* See if INSN needs to be protected. If so,
15942 we must insert a cache barrier somewhere between
15943 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
15944 clear which position is better performance-wise,
15945 but as a tie-breaker, we assume that it is better
15946 to allow delay slots to be back-filled where
15947 possible, and that it is better not to insert
15948 barriers in the middle of already-scheduled code.
15949 We therefore insert the barrier at the beginning
15951 if (r10k_needs_protection_p (insn))
15953 emit_insn_before (gen_r10k_cache_barrier (),
15954 unprotected_region);
15955 unprotected_region = NULL_RTX;
15961 /* The called function is not required to protect the exit path.
15962 The code that follows a call is therefore unprotected. */
15963 unprotected_region = pc_rtx;
15966 /* Record whether the end of this block is protected. */
15967 if (unprotected_region == NULL_RTX)
15968 bitmap_set_bit (protected_bbs, bb->index);
15970 XDELETEVEC (rev_post_order);
15972 sbitmap_free (protected_bbs);
15974 free_dominance_info (CDI_DOMINATORS);
15977 /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX
15978 otherwise. If INSN has two call rtx, then store the second one in
15982 mips_call_expr_from_insn (rtx_insn *insn, rtx *second_call)
15987 if (!CALL_P (insn))
15990 x = PATTERN (insn);
15991 if (GET_CODE (x) == PARALLEL)
15993 /* Calls returning complex values have two CALL rtx. Look for the second
15994 one here, and return it via the SECOND_CALL arg. */
15995 x2 = XVECEXP (x, 0, 1);
15996 if (GET_CODE (x2) == SET)
15998 if (GET_CODE (x2) == CALL)
16001 x = XVECEXP (x, 0, 0);
16003 if (GET_CODE (x) == SET)
16005 gcc_assert (GET_CODE (x) == CALL);
16010 /* REG is set in DEF. See if the definition is one of the ways we load a
16011 register with a symbol address for a mips_use_pic_fn_addr_reg_p call.
16012 If it is, return the symbol reference of the function, otherwise return
16015 If RECURSE_P is true, use mips_find_pic_call_symbol to interpret
16016 the values of source registers, otherwise treat such registers as
16017 having an unknown value. */
16020 mips_pic_call_symbol_from_set (df_ref def, rtx reg, bool recurse_p)
16022 rtx_insn *def_insn;
16025 if (DF_REF_IS_ARTIFICIAL (def))
16028 def_insn = DF_REF_INSN (def);
16029 set = single_set (def_insn);
16030 if (set && rtx_equal_p (SET_DEST (set), reg))
16032 rtx note, src, symbol;
16034 /* First see whether the source is a plain symbol. This is used
16035 when calling symbols that are not lazily bound. */
16036 src = SET_SRC (set);
16037 if (GET_CODE (src) == SYMBOL_REF)
16040 /* Handle %call16 references. */
16041 symbol = mips_strip_unspec_call (src);
16044 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
16048 /* If we have something more complicated, look for a
16049 REG_EQUAL or REG_EQUIV note. */
16050 note = find_reg_equal_equiv_note (def_insn);
16051 if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF)
16052 return XEXP (note, 0);
16054 /* Follow at most one simple register copy. Such copies are
16055 interesting in cases like:
16059 locally_binding_fn (...);
16064 locally_binding_fn (...);
16066 locally_binding_fn (...);
16068 where the load of locally_binding_fn can legitimately be
16069 hoisted or shared. However, we do not expect to see complex
16070 chains of copies, so a full worklist solution to the problem
16071 would probably be overkill. */
16072 if (recurse_p && REG_P (src))
16073 return mips_find_pic_call_symbol (def_insn, src, false);
16079 /* Find the definition of the use of REG in INSN. See if the definition
16080 is one of the ways we load a register with a symbol address for a
16081 mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference
16082 of the function, otherwise return NULL_RTX. RECURSE_P is as for
16083 mips_pic_call_symbol_from_set. */
16086 mips_find_pic_call_symbol (rtx_insn *insn, rtx reg, bool recurse_p)
16089 struct df_link *defs;
16092 use = df_find_use (insn, regno_reg_rtx[REGNO (reg)]);
16095 defs = DF_REF_CHAIN (use);
16098 symbol = mips_pic_call_symbol_from_set (defs->ref, reg, recurse_p);
16102 /* If we have more than one definition, they need to be identical. */
16103 for (defs = defs->next; defs; defs = defs->next)
16107 other = mips_pic_call_symbol_from_set (defs->ref, reg, recurse_p);
16108 if (!rtx_equal_p (symbol, other))
16115 /* Replace the args_size operand of the call expression CALL with the
16116 call-attribute UNSPEC and fill in SYMBOL as the function symbol. */
16119 mips_annotate_pic_call_expr (rtx call, rtx symbol)
16123 args_size = XEXP (call, 1);
16124 XEXP (call, 1) = gen_rtx_UNSPEC (GET_MODE (args_size),
16125 gen_rtvec (2, args_size, symbol),
16129 /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See
16130 if instead of the arg_size argument it contains the call attributes. If
16131 yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function
16132 symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is
16136 mips_get_pic_call_symbol (rtx *operands, int args_size_opno)
16138 rtx args_size, symbol;
16140 if (!TARGET_RELAX_PIC_CALLS || args_size_opno == -1)
16143 args_size = operands[args_size_opno];
16144 if (GET_CODE (args_size) != UNSPEC)
16146 gcc_assert (XINT (args_size, 1) == UNSPEC_CALL_ATTR);
16148 symbol = XVECEXP (args_size, 0, 1);
16149 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
16151 operands[args_size_opno] = symbol;
16155 /* Use DF to annotate PIC indirect calls with the function symbol they
16159 mips_annotate_pic_calls (void)
16164 FOR_EACH_BB_FN (bb, cfun)
16165 FOR_BB_INSNS (bb, insn)
16167 rtx call, reg, symbol, second_call;
16170 call = mips_call_expr_from_insn (insn, &second_call);
16173 gcc_assert (MEM_P (XEXP (call, 0)));
16174 reg = XEXP (XEXP (call, 0), 0);
16178 symbol = mips_find_pic_call_symbol (insn, reg, true);
16181 mips_annotate_pic_call_expr (call, symbol);
16183 mips_annotate_pic_call_expr (second_call, symbol);
16188 /* A temporary variable used by note_uses callbacks, etc. */
16189 static rtx_insn *mips_sim_insn;
16191 /* A structure representing the state of the processor pipeline.
16192 Used by the mips_sim_* family of functions. */
16194 /* The maximum number of instructions that can be issued in a cycle.
16195 (Caches mips_issue_rate.) */
16196 unsigned int issue_rate;
16198 /* The current simulation time. */
16201 /* How many more instructions can be issued in the current cycle. */
16202 unsigned int insns_left;
16204 /* LAST_SET[X].INSN is the last instruction to set register X.
16205 LAST_SET[X].TIME is the time at which that instruction was issued.
16206 INSN is null if no instruction has yet set register X. */
16210 } last_set[FIRST_PSEUDO_REGISTER];
16212 /* The pipeline's current DFA state. */
16216 /* Reset STATE to the initial simulation state. */
16219 mips_sim_reset (struct mips_sim *state)
16221 curr_state = state->dfa_state;
16224 state->insns_left = state->issue_rate;
16225 memset (&state->last_set, 0, sizeof (state->last_set));
16226 state_reset (curr_state);
16228 targetm.sched.init (0, false, 0);
16229 advance_state (curr_state);
16232 /* Initialize STATE before its first use. DFA_STATE points to an
16233 allocated but uninitialized DFA state. */
16236 mips_sim_init (struct mips_sim *state, state_t dfa_state)
16238 if (targetm.sched.init_dfa_pre_cycle_insn)
16239 targetm.sched.init_dfa_pre_cycle_insn ();
16241 if (targetm.sched.init_dfa_post_cycle_insn)
16242 targetm.sched.init_dfa_post_cycle_insn ();
16244 state->issue_rate = mips_issue_rate ();
16245 state->dfa_state = dfa_state;
16246 mips_sim_reset (state);
16249 /* Advance STATE by one clock cycle. */
16252 mips_sim_next_cycle (struct mips_sim *state)
16254 curr_state = state->dfa_state;
16257 state->insns_left = state->issue_rate;
16258 advance_state (curr_state);
16261 /* Advance simulation state STATE until instruction INSN can read
16265 mips_sim_wait_reg (struct mips_sim *state, rtx_insn *insn, rtx reg)
16267 unsigned int regno, end_regno;
16269 end_regno = END_REGNO (reg);
16270 for (regno = REGNO (reg); regno < end_regno; regno++)
16271 if (state->last_set[regno].insn != 0)
16275 t = (state->last_set[regno].time
16276 + insn_latency (state->last_set[regno].insn, insn));
16277 while (state->time < t)
16278 mips_sim_next_cycle (state);
16282 /* A note_uses callback. For each register in *X, advance simulation
16283 state DATA until mips_sim_insn can read the register's value. */
16286 mips_sim_wait_regs_1 (rtx *x, void *data)
16288 subrtx_var_iterator::array_type array;
16289 FOR_EACH_SUBRTX_VAR (iter, array, *x, NONCONST)
16291 mips_sim_wait_reg ((struct mips_sim *) data, mips_sim_insn, *iter);
16294 /* Advance simulation state STATE until all of INSN's register
16295 dependencies are satisfied. */
16298 mips_sim_wait_regs (struct mips_sim *state, rtx_insn *insn)
16300 mips_sim_insn = insn;
16301 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
16304 /* Advance simulation state STATE until the units required by
16305 instruction INSN are available. */
16308 mips_sim_wait_units (struct mips_sim *state, rtx_insn *insn)
16312 tmp_state = alloca (state_size ());
16313 while (state->insns_left == 0
16314 || (memcpy (tmp_state, state->dfa_state, state_size ()),
16315 state_transition (tmp_state, insn) >= 0))
16316 mips_sim_next_cycle (state);
16319 /* Advance simulation state STATE until INSN is ready to issue. */
16322 mips_sim_wait_insn (struct mips_sim *state, rtx_insn *insn)
16324 mips_sim_wait_regs (state, insn);
16325 mips_sim_wait_units (state, insn);
16328 /* mips_sim_insn has just set X. Update the LAST_SET array
16329 in simulation state DATA. */
16332 mips_sim_record_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
16334 struct mips_sim *state;
16336 state = (struct mips_sim *) data;
16339 unsigned int regno, end_regno;
16341 end_regno = END_REGNO (x);
16342 for (regno = REGNO (x); regno < end_regno; regno++)
16344 state->last_set[regno].insn = mips_sim_insn;
16345 state->last_set[regno].time = state->time;
16350 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
16351 can issue immediately (i.e., that mips_sim_wait_insn has already
16355 mips_sim_issue_insn (struct mips_sim *state, rtx_insn *insn)
16357 curr_state = state->dfa_state;
16359 state_transition (curr_state, insn);
16360 state->insns_left = targetm.sched.variable_issue (0, false, insn,
16361 state->insns_left);
16363 mips_sim_insn = insn;
16364 note_stores (PATTERN (insn), mips_sim_record_set, state);
16367 /* Simulate issuing a NOP in state STATE. */
16370 mips_sim_issue_nop (struct mips_sim *state)
16372 if (state->insns_left == 0)
16373 mips_sim_next_cycle (state);
16374 state->insns_left--;
16377 /* Update simulation state STATE so that it's ready to accept the instruction
16378 after INSN. INSN should be part of the main rtl chain, not a member of a
16382 mips_sim_finish_insn (struct mips_sim *state, rtx_insn *insn)
16384 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
16386 mips_sim_issue_nop (state);
16388 switch (GET_CODE (SEQ_BEGIN (insn)))
16392 /* We can't predict the processor state after a call or label. */
16393 mips_sim_reset (state);
16397 /* The delay slots of branch likely instructions are only executed
16398 when the branch is taken. Therefore, if the caller has simulated
16399 the delay slot instruction, STATE does not really reflect the state
16400 of the pipeline for the instruction after the delay slot. Also,
16401 branch likely instructions tend to incur a penalty when not taken,
16402 so there will probably be an extra delay between the branch and
16403 the instruction after the delay slot. */
16404 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
16405 mips_sim_reset (state);
16413 /* Use simulator state STATE to calculate the execution time of
16414 instruction sequence SEQ. */
16416 static unsigned int
16417 mips_seq_time (struct mips_sim *state, rtx_insn *seq)
16419 mips_sim_reset (state);
16420 for (rtx_insn *insn = seq; insn; insn = NEXT_INSN (insn))
16422 mips_sim_wait_insn (state, insn);
16423 mips_sim_issue_insn (state, insn);
16425 return state->time;
16428 /* Return the execution-time cost of mips_tuning_info.fast_mult_zero_zero_p
16429 setting SETTING, using STATE to simulate instruction sequences. */
16431 static unsigned int
16432 mips_mult_zero_zero_cost (struct mips_sim *state, bool setting)
16434 mips_tuning_info.fast_mult_zero_zero_p = setting;
16437 machine_mode dword_mode = TARGET_64BIT ? TImode : DImode;
16438 rtx hilo = gen_rtx_REG (dword_mode, MD_REG_FIRST);
16439 mips_emit_move_or_split (hilo, const0_rtx, SPLIT_FOR_SPEED);
16441 /* If the target provides mulsidi3_32bit then that's the most likely
16442 consumer of the result. Test for bypasses. */
16443 if (dword_mode == DImode && HAVE_maddsidi4)
16445 rtx gpr = gen_rtx_REG (SImode, GP_REG_FIRST + 4);
16446 emit_insn (gen_maddsidi4 (hilo, gpr, gpr, hilo));
16449 unsigned int time = mips_seq_time (state, get_insns ());
16454 /* Check the relative speeds of "MULT $0,$0" and "MTLO $0; MTHI $0"
16455 and set up mips_tuning_info.fast_mult_zero_zero_p accordingly.
16456 Prefer MULT -- which is shorter -- in the event of a tie. */
16459 mips_set_fast_mult_zero_zero_p (struct mips_sim *state)
16461 if (TARGET_MIPS16 || !ISA_HAS_HILO)
16462 /* No MTLO or MTHI available for MIPS16. Also, when there are no HI or LO
16463 registers then there is no reason to zero them, arbitrarily choose to
16464 say that "MULT $0,$0" would be faster. */
16465 mips_tuning_info.fast_mult_zero_zero_p = true;
16468 unsigned int true_time = mips_mult_zero_zero_cost (state, true);
16469 unsigned int false_time = mips_mult_zero_zero_cost (state, false);
16470 mips_tuning_info.fast_mult_zero_zero_p = (true_time <= false_time);
16474 /* Set up costs based on the current architecture and tuning settings. */
16477 mips_set_tuning_info (void)
16479 if (mips_tuning_info.initialized_p
16480 && mips_tuning_info.arch == mips_arch
16481 && mips_tuning_info.tune == mips_tune
16482 && mips_tuning_info.mips16_p == TARGET_MIPS16)
16485 mips_tuning_info.arch = mips_arch;
16486 mips_tuning_info.tune = mips_tune;
16487 mips_tuning_info.mips16_p = TARGET_MIPS16;
16488 mips_tuning_info.initialized_p = true;
16492 struct mips_sim state;
16493 mips_sim_init (&state, alloca (state_size ()));
16495 mips_set_fast_mult_zero_zero_p (&state);
16500 /* Implement TARGET_EXPAND_TO_RTL_HOOK. */
16503 mips_expand_to_rtl_hook (void)
16505 /* We need to call this at a point where we can safely create sequences
16506 of instructions, so TARGET_OVERRIDE_OPTIONS is too early. We also
16507 need to call it at a point where the DFA infrastructure is not
16508 already in use, so we can't just call it lazily on demand.
16510 At present, mips_tuning_info is only needed during post-expand
16511 RTL passes such as split_insns, so this hook should be early enough.
16512 We may need to move the call elsewhere if mips_tuning_info starts
16513 to be used for other things (such as rtx_costs, or expanders that
16514 could be called during gimple optimization). */
16515 mips_set_tuning_info ();
16518 /* The VR4130 pipeline issues aligned pairs of instructions together,
16519 but it stalls the second instruction if it depends on the first.
16520 In order to cut down the amount of logic required, this dependence
16521 check is not based on a full instruction decode. Instead, any non-SPECIAL
16522 instruction is assumed to modify the register specified by bits 20-16
16523 (which is usually the "rt" field).
16525 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
16526 input, so we can end up with a false dependence between the branch
16527 and its delay slot. If this situation occurs in instruction INSN,
16528 try to avoid it by swapping rs and rt. */
16531 vr4130_avoid_branch_rt_conflict (rtx_insn *insn)
16533 rtx_insn *first, *second;
16535 first = SEQ_BEGIN (insn);
16536 second = SEQ_END (insn);
16538 && NONJUMP_INSN_P (second)
16539 && GET_CODE (PATTERN (first)) == SET
16540 && GET_CODE (SET_DEST (PATTERN (first))) == PC
16541 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
16543 /* Check for the right kind of condition. */
16544 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
16545 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
16546 && REG_P (XEXP (cond, 0))
16547 && REG_P (XEXP (cond, 1))
16548 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
16549 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
16551 /* SECOND mentions the rt register but not the rs register. */
16552 rtx tmp = XEXP (cond, 0);
16553 XEXP (cond, 0) = XEXP (cond, 1);
16554 XEXP (cond, 1) = tmp;
16559 /* Implement -mvr4130-align. Go through each basic block and simulate the
16560 processor pipeline. If we find that a pair of instructions could execute
16561 in parallel, and the first of those instructions is not 8-byte aligned,
16562 insert a nop to make it aligned. */
16565 vr4130_align_insns (void)
16567 struct mips_sim state;
16568 rtx_insn *insn, *subinsn, *last, *last2, *next;
16573 /* LAST is the last instruction before INSN to have a nonzero length.
16574 LAST2 is the last such instruction before LAST. */
16578 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
16581 mips_sim_init (&state, alloca (state_size ()));
16582 for (insn = get_insns (); insn != 0; insn = next)
16584 unsigned int length;
16586 next = NEXT_INSN (insn);
16588 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
16589 This isn't really related to the alignment pass, but we do it on
16590 the fly to avoid a separate instruction walk. */
16591 vr4130_avoid_branch_rt_conflict (insn);
16593 length = get_attr_length (insn);
16594 if (length > 0 && USEFUL_INSN_P (insn))
16595 FOR_EACH_SUBINSN (subinsn, insn)
16597 mips_sim_wait_insn (&state, subinsn);
16599 /* If we want this instruction to issue in parallel with the
16600 previous one, make sure that the previous instruction is
16601 aligned. There are several reasons why this isn't worthwhile
16602 when the second instruction is a call:
16604 - Calls are less likely to be performance critical,
16605 - There's a good chance that the delay slot can execute
16606 in parallel with the call.
16607 - The return address would then be unaligned.
16609 In general, if we're going to insert a nop between instructions
16610 X and Y, it's better to insert it immediately after X. That
16611 way, if the nop makes Y aligned, it will also align any labels
16612 between X and Y. */
16613 if (state.insns_left != state.issue_rate
16614 && !CALL_P (subinsn))
16616 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
16618 /* SUBINSN is the first instruction in INSN and INSN is
16619 aligned. We want to align the previous instruction
16620 instead, so insert a nop between LAST2 and LAST.
16622 Note that LAST could be either a single instruction
16623 or a branch with a delay slot. In the latter case,
16624 LAST, like INSN, is already aligned, but the delay
16625 slot must have some extra delay that stops it from
16626 issuing at the same time as the branch. We therefore
16627 insert a nop before the branch in order to align its
16629 gcc_assert (last2);
16630 emit_insn_after (gen_nop (), last2);
16633 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
16635 /* SUBINSN is the delay slot of INSN, but INSN is
16636 currently unaligned. Insert a nop between
16637 LAST and INSN to align it. */
16639 emit_insn_after (gen_nop (), last);
16643 mips_sim_issue_insn (&state, subinsn);
16645 mips_sim_finish_insn (&state, insn);
16647 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
16648 length = get_attr_length (insn);
16651 /* If the instruction is an asm statement or multi-instruction
16652 mips.md patern, the length is only an estimate. Insert an
16653 8 byte alignment after it so that the following instructions
16654 can be handled correctly. */
16655 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
16656 && (recog_memoized (insn) < 0 || length >= 8))
16658 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
16659 next = NEXT_INSN (next);
16660 mips_sim_next_cycle (&state);
16663 else if (length & 4)
16664 aligned_p = !aligned_p;
16669 /* See whether INSN is an aligned label. */
16670 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
16676 /* This structure records that the current function has a LO_SUM
16677 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
16678 the largest offset applied to BASE by all such LO_SUMs. */
16679 struct mips_lo_sum_offset {
16681 HOST_WIDE_INT offset;
16684 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
16687 mips_hash_base (rtx base)
16689 int do_not_record_p;
16691 return hash_rtx (base, GET_MODE (base), &do_not_record_p, NULL, false);
16694 /* Hashtable helpers. */
16696 struct mips_lo_sum_offset_hasher : free_ptr_hash <mips_lo_sum_offset>
16698 typedef rtx_def *compare_type;
16699 static inline hashval_t hash (const mips_lo_sum_offset *);
16700 static inline bool equal (const mips_lo_sum_offset *, const rtx_def *);
16703 /* Hash-table callbacks for mips_lo_sum_offsets. */
16706 mips_lo_sum_offset_hasher::hash (const mips_lo_sum_offset *entry)
16708 return mips_hash_base (entry->base);
16712 mips_lo_sum_offset_hasher::equal (const mips_lo_sum_offset *entry,
16713 const rtx_def *value)
16715 return rtx_equal_p (entry->base, value);
16718 typedef hash_table<mips_lo_sum_offset_hasher> mips_offset_table;
16720 /* Look up symbolic constant X in HTAB, which is a hash table of
16721 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
16722 paired with a recorded LO_SUM, otherwise record X in the table. */
16725 mips_lo_sum_offset_lookup (mips_offset_table *htab, rtx x,
16726 enum insert_option option)
16729 mips_lo_sum_offset **slot;
16730 struct mips_lo_sum_offset *entry;
16732 /* Split X into a base and offset. */
16733 split_const (x, &base, &offset);
16734 if (UNSPEC_ADDRESS_P (base))
16735 base = UNSPEC_ADDRESS (base);
16737 /* Look up the base in the hash table. */
16738 slot = htab->find_slot_with_hash (base, mips_hash_base (base), option);
16742 entry = (struct mips_lo_sum_offset *) *slot;
16743 if (option == INSERT)
16747 entry = XNEW (struct mips_lo_sum_offset);
16748 entry->base = base;
16749 entry->offset = INTVAL (offset);
16754 if (INTVAL (offset) > entry->offset)
16755 entry->offset = INTVAL (offset);
16758 return INTVAL (offset) <= entry->offset;
16761 /* Search X for LO_SUMs and record them in HTAB. */
16764 mips_record_lo_sums (const_rtx x, mips_offset_table *htab)
16766 subrtx_iterator::array_type array;
16767 FOR_EACH_SUBRTX (iter, array, x, NONCONST)
16768 if (GET_CODE (*iter) == LO_SUM)
16769 mips_lo_sum_offset_lookup (htab, XEXP (*iter, 1), INSERT);
16772 /* Return true if INSN is a SET of an orphaned high-part relocation.
16773 HTAB is a hash table of mips_lo_sum_offsets that describes all the
16774 LO_SUMs in the current function. */
16777 mips_orphaned_high_part_p (mips_offset_table *htab, rtx_insn *insn)
16779 enum mips_symbol_type type;
16782 set = single_set (insn);
16785 /* Check for %his. */
16787 if (GET_CODE (x) == HIGH
16788 && absolute_symbolic_operand (XEXP (x, 0), VOIDmode))
16789 return !mips_lo_sum_offset_lookup (htab, XEXP (x, 0), NO_INSERT);
16791 /* Check for local %gots (and %got_pages, which is redundant but OK). */
16792 if (GET_CODE (x) == UNSPEC
16793 && XINT (x, 1) == UNSPEC_LOAD_GOT
16794 && mips_symbolic_constant_p (XVECEXP (x, 0, 1),
16795 SYMBOL_CONTEXT_LEA, &type)
16796 && type == SYMBOL_GOTOFF_PAGE)
16797 return !mips_lo_sum_offset_lookup (htab, XVECEXP (x, 0, 1), NO_INSERT);
16802 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
16803 INSN and a previous instruction, avoid it by inserting nops after
16806 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
16807 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
16808 before using the value of that register. *HILO_DELAY counts the
16809 number of instructions since the last hilo hazard (that is,
16810 the number of instructions since the last MFLO or MFHI).
16812 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
16813 for the next instruction.
16815 LO_REG is an rtx for the LO register, used in dependence checking. */
16818 mips_avoid_hazard (rtx_insn *after, rtx_insn *insn, int *hilo_delay,
16819 rtx *delayed_reg, rtx lo_reg, bool *fs_delay)
16824 pattern = PATTERN (insn);
16826 /* Do not put the whole function in .set noreorder if it contains
16827 an asm statement. We don't know whether there will be hazards
16828 between the asm statement and the gcc-generated code. */
16829 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
16830 cfun->machine->all_noreorder_p = false;
16832 /* Ignore zero-length instructions (barriers and the like). */
16833 ninsns = get_attr_length (insn) / 4;
16837 /* Work out how many nops are needed. Note that we only care about
16838 registers that are explicitly mentioned in the instruction's pattern.
16839 It doesn't matter that calls use the argument registers or that they
16840 clobber hi and lo. */
16841 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
16842 nops = 2 - *hilo_delay;
16843 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
16845 /* If processing a forbidden slot hazard then a NOP is required if the
16846 branch instruction was not in a sequence (as the sequence would
16847 imply it is not actually a compact branch anyway) and the current
16848 insn is not an inline asm, and can't go in a delay slot. */
16849 else if (*fs_delay && get_attr_can_delay (insn) == CAN_DELAY_NO
16850 && GET_CODE (PATTERN (after)) != SEQUENCE
16851 && GET_CODE (pattern) != ASM_INPUT
16852 && asm_noperands (pattern) < 0)
16857 /* Insert the nops between this instruction and the previous one.
16858 Each new nop takes us further from the last hilo hazard. */
16859 *hilo_delay += nops;
16861 emit_insn_after (gen_hazard_nop (), after);
16863 /* Set up the state for the next instruction. */
16864 *hilo_delay += ninsns;
16867 if (INSN_CODE (insn) >= 0)
16868 switch (get_attr_hazard (insn))
16873 case HAZARD_FORBIDDEN_SLOT:
16874 if (TARGET_CB_MAYBE)
16883 set = single_set (insn);
16885 *delayed_reg = SET_DEST (set);
16890 /* A SEQUENCE is breakable iff the branch inside it has a compact form
16891 and the target has compact branches. */
16894 mips_breakable_sequence_p (rtx_insn *insn)
16896 return (insn && GET_CODE (PATTERN (insn)) == SEQUENCE
16898 && get_attr_compact_form (SEQ_BEGIN (insn)) != COMPACT_FORM_NEVER);
16901 /* Remove a SEQUENCE and replace it with the delay slot instruction
16902 followed by the branch and return the instruction in the delay slot.
16903 Return the first of the two new instructions.
16904 Subroutine of mips_reorg_process_insns. */
16907 mips_break_sequence (rtx_insn *insn)
16909 rtx_insn *before = PREV_INSN (insn);
16910 rtx_insn *branch = SEQ_BEGIN (insn);
16911 rtx_insn *ds = SEQ_END (insn);
16912 remove_insn (insn);
16913 add_insn_after (ds, before, NULL);
16914 add_insn_after (branch, ds, NULL);
16918 /* Go through the instruction stream and insert nops where necessary.
16919 Also delete any high-part relocations whose partnering low parts
16920 are now all dead. See if the whole function can then be put into
16921 .set noreorder and .set nomacro. */
16924 mips_reorg_process_insns (void)
16926 rtx_insn *insn, *last_insn, *subinsn, *next_insn;
16927 rtx lo_reg, delayed_reg;
16931 /* Force all instructions to be split into their final form. */
16932 split_all_insns_noflow ();
16934 /* Recalculate instruction lengths without taking nops into account. */
16935 cfun->machine->ignore_hazard_length_p = true;
16936 shorten_branches (get_insns ());
16938 cfun->machine->all_noreorder_p = true;
16940 /* We don't track MIPS16 PC-relative offsets closely enough to make
16941 a good job of "set .noreorder" code in MIPS16 mode. */
16943 cfun->machine->all_noreorder_p = false;
16945 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
16946 if (!TARGET_EXPLICIT_RELOCS)
16947 cfun->machine->all_noreorder_p = false;
16949 /* Profiled functions can't be all noreorder because the profiler
16950 support uses assembler macros. */
16952 cfun->machine->all_noreorder_p = false;
16954 /* Code compiled with -mfix-vr4120, -mfix-rm7000 or -mfix-24k can't be
16955 all noreorder because we rely on the assembler to work around some
16956 errata. The R5900 too has several bugs. */
16957 if (TARGET_FIX_VR4120
16958 || TARGET_FIX_RM7000
16960 || TARGET_MIPS5900)
16961 cfun->machine->all_noreorder_p = false;
16963 /* The same is true for -mfix-vr4130 if we might generate MFLO or
16964 MFHI instructions. Note that we avoid using MFLO and MFHI if
16965 the VR4130 MACC and DMACC instructions are available instead;
16966 see the *mfhilo_{si,di}_macc patterns. */
16967 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
16968 cfun->machine->all_noreorder_p = false;
16970 mips_offset_table htab (37);
16972 /* Make a first pass over the instructions, recording all the LO_SUMs. */
16973 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
16974 FOR_EACH_SUBINSN (subinsn, insn)
16975 if (USEFUL_INSN_P (subinsn))
16977 rtx body = PATTERN (insn);
16978 int noperands = asm_noperands (body);
16979 if (noperands >= 0)
16981 rtx *ops = XALLOCAVEC (rtx, noperands);
16982 bool *used = XALLOCAVEC (bool, noperands);
16983 const char *string = decode_asm_operands (body, ops, NULL, NULL,
16985 get_referenced_operands (string, used, noperands);
16986 for (int i = 0; i < noperands; ++i)
16988 mips_record_lo_sums (ops[i], &htab);
16991 mips_record_lo_sums (PATTERN (subinsn), &htab);
16997 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
17000 /* Make a second pass over the instructions. Delete orphaned
17001 high-part relocations or turn them into NOPs. Avoid hazards
17002 by inserting NOPs. */
17003 for (insn = get_insns (); insn != 0; insn = next_insn)
17005 next_insn = NEXT_INSN (insn);
17006 if (USEFUL_INSN_P (insn))
17008 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
17010 rtx_insn *next_active = next_active_insn (insn);
17011 /* Undo delay slots to avoid bubbles if the next instruction can
17012 be placed in a forbidden slot or the cost of adding an
17013 explicit NOP in a forbidden slot is OK and if the SEQUENCE is
17014 safely breakable. */
17015 if (TARGET_CB_MAYBE
17016 && mips_breakable_sequence_p (insn)
17017 && INSN_P (SEQ_BEGIN (insn))
17018 && INSN_P (SEQ_END (insn))
17020 && INSN_P (next_active)
17021 && GET_CODE (PATTERN (next_active)) != SEQUENCE
17022 && get_attr_can_delay (next_active) == CAN_DELAY_YES)
17023 || !optimize_size))
17025 /* To hide a potential pipeline bubble, if we scan backwards
17026 from the current SEQUENCE and find that there is a load
17027 of a value that is used in the CTI and there are no
17028 dependencies between the CTI and instruction in the delay
17029 slot, break the sequence so the load delay is hidden. */
17031 CLEAR_HARD_REG_SET (uses);
17032 note_uses (&PATTERN (SEQ_BEGIN (insn)), record_hard_reg_uses,
17034 HARD_REG_SET delay_sets;
17035 CLEAR_HARD_REG_SET (delay_sets);
17036 note_stores (PATTERN (SEQ_END (insn)), record_hard_reg_sets,
17039 rtx_insn *prev = prev_active_insn (insn);
17041 && GET_CODE (PATTERN (prev)) == SET
17042 && MEM_P (SET_SRC (PATTERN (prev))))
17045 CLEAR_HARD_REG_SET (sets);
17046 note_stores (PATTERN (prev), record_hard_reg_sets,
17049 /* Re-order if safe. */
17050 if (!hard_reg_set_intersect_p (delay_sets, uses)
17051 && hard_reg_set_intersect_p (uses, sets))
17053 next_insn = mips_break_sequence (insn);
17054 /* Need to process the hazards of the newly
17055 introduced instructions. */
17060 /* If we find an orphaned high-part relocation in a delay
17061 slot then we can convert to a compact branch and get
17062 the orphaned high part deleted. */
17063 if (mips_orphaned_high_part_p (&htab, SEQ_END (insn)))
17065 next_insn = mips_break_sequence (insn);
17066 /* Need to process the hazards of the newly
17067 introduced instructions. */
17072 /* If we find an orphaned high-part relocation in a delay
17073 slot, it's easier to turn that instruction into a NOP than
17074 to delete it. The delay slot will be a NOP either way. */
17075 FOR_EACH_SUBINSN (subinsn, insn)
17076 if (INSN_P (subinsn))
17078 if (mips_orphaned_high_part_p (&htab, subinsn))
17080 PATTERN (subinsn) = gen_nop ();
17081 INSN_CODE (subinsn) = CODE_FOR_nop;
17083 mips_avoid_hazard (last_insn, subinsn, &hilo_delay,
17084 &delayed_reg, lo_reg, &fs_delay);
17090 /* INSN is a single instruction. Delete it if it's an
17091 orphaned high-part relocation. */
17092 if (mips_orphaned_high_part_p (&htab, insn))
17093 delete_insn (insn);
17094 /* Also delete cache barriers if the last instruction
17095 was an annulled branch. INSN will not be speculatively
17097 else if (recog_memoized (insn) == CODE_FOR_r10k_cache_barrier
17099 && JUMP_P (SEQ_BEGIN (last_insn))
17100 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn)))
17101 delete_insn (insn);
17104 mips_avoid_hazard (last_insn, insn, &hilo_delay,
17105 &delayed_reg, lo_reg, &fs_delay);
17106 /* When a compact branch introduces a forbidden slot hazard
17107 and the next useful instruction is a SEQUENCE of a jump
17108 and a non-nop instruction in the delay slot, remove the
17109 sequence and replace it with the delay slot instruction
17110 then the jump to clear the forbidden slot hazard. */
17114 /* Search onwards from the current position looking for
17115 a SEQUENCE. We are looking for pipeline hazards here
17116 and do not need to worry about labels or barriers as
17117 the optimization only undoes delay slot filling which
17118 only affects the order of the branch and its delay
17120 rtx_insn *next = next_active_insn (insn);
17122 && USEFUL_INSN_P (next)
17123 && GET_CODE (PATTERN (next)) == SEQUENCE
17124 && mips_breakable_sequence_p (next))
17127 next_insn = mips_break_sequence (next);
17128 /* Need to process the hazards of the newly
17129 introduced instructions. */
17140 /* Return true if the function has a long branch instruction. */
17143 mips_has_long_branch_p (void)
17145 rtx_insn *insn, *subinsn;
17148 /* We need up-to-date instruction lengths. */
17149 shorten_branches (get_insns ());
17151 /* Look for a branch that is longer than normal. The normal length for
17152 non-MIPS16 branches is 8, because the length includes the delay slot.
17153 It is 4 for MIPS16, because MIPS16 branches are extended instructions,
17154 but they have no delay slot. */
17155 normal_length = (TARGET_MIPS16 ? 4 : 8);
17156 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
17157 FOR_EACH_SUBINSN (subinsn, insn)
17158 if (JUMP_P (subinsn)
17159 && get_attr_length (subinsn) > normal_length
17160 && (any_condjump_p (subinsn) || any_uncondjump_p (subinsn)))
17166 /* If we are using a GOT, but have not decided to use a global pointer yet,
17167 see whether we need one to implement long branches. Convert the ghost
17168 global-pointer instructions into real ones if so. */
17171 mips_expand_ghost_gp_insns (void)
17173 /* Quick exit if we already know that we will or won't need a
17175 if (!TARGET_USE_GOT
17176 || cfun->machine->global_pointer == INVALID_REGNUM
17177 || mips_must_initialize_gp_p ())
17180 /* Run a full check for long branches. */
17181 if (!mips_has_long_branch_p ())
17184 /* We've now established that we need $gp. */
17185 cfun->machine->must_initialize_gp_p = true;
17186 split_all_insns_noflow ();
17191 /* Subroutine of mips_reorg to manage passes that require DF. */
17194 mips_df_reorg (void)
17196 /* Create def-use chains. */
17197 df_set_flags (DF_EQ_NOTES);
17198 df_chain_add_problem (DF_UD_CHAIN);
17201 if (TARGET_RELAX_PIC_CALLS)
17202 mips_annotate_pic_calls ();
17204 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE)
17205 r10k_insert_cache_barriers ();
17207 df_finish_pass (false);
17210 /* Emit code to load LABEL_REF SRC into MIPS16 register DEST. This is
17211 called very late in mips_reorg, but the caller is required to run
17212 mips16_lay_out_constants on the result. */
17215 mips16_load_branch_target (rtx dest, rtx src)
17217 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
17221 if (mips_cfun_has_cprestore_slot_p ())
17222 mips_emit_move (dest, mips_cprestore_slot (dest, true));
17224 mips_emit_move (dest, pic_offset_table_rtx);
17225 page = mips_unspec_address (src, SYMBOL_GOTOFF_PAGE);
17226 low = mips_unspec_address (src, SYMBOL_GOT_PAGE_OFST);
17227 emit_insn (gen_rtx_SET (dest,
17228 PMODE_INSN (gen_unspec_got, (dest, page))));
17229 emit_insn (gen_rtx_SET (dest, gen_rtx_LO_SUM (Pmode, dest, low)));
17233 src = mips_unspec_address (src, SYMBOL_ABSOLUTE);
17234 mips_emit_move (dest, src);
17238 /* If we're compiling a MIPS16 function, look for and split any long branches.
17239 This must be called after all other instruction modifications in
17243 mips16_split_long_branches (void)
17245 bool something_changed;
17247 if (!TARGET_MIPS16)
17250 /* Loop until the alignments for all targets are sufficient. */
17254 rtx_jump_insn *jump_insn;
17256 shorten_branches (get_insns ());
17257 something_changed = false;
17258 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
17259 if ((jump_insn = dyn_cast <rtx_jump_insn *> (insn))
17260 && get_attr_length (jump_insn) > 4
17261 && (any_condjump_p (jump_insn) || any_uncondjump_p (jump_insn)))
17263 rtx old_label, temp, saved_temp;
17264 rtx_code_label *new_label;
17266 rtx_insn *jump, *jump_sequence;
17270 /* Free up a MIPS16 register by saving it in $1. */
17271 saved_temp = gen_rtx_REG (Pmode, AT_REGNUM);
17272 temp = gen_rtx_REG (Pmode, GP_REG_FIRST + 2);
17273 emit_move_insn (saved_temp, temp);
17275 /* Load the branch target into TEMP. */
17276 old_label = JUMP_LABEL (jump_insn);
17277 target = gen_rtx_LABEL_REF (Pmode, old_label);
17278 mips16_load_branch_target (temp, target);
17280 /* Jump to the target and restore the register's
17282 jump = emit_jump_insn (PMODE_INSN (gen_indirect_jump_and_restore,
17283 (temp, temp, saved_temp)));
17284 JUMP_LABEL (jump) = old_label;
17285 LABEL_NUSES (old_label)++;
17287 /* Rewrite any symbolic references that are supposed to use
17288 a PC-relative constant pool. */
17289 mips16_lay_out_constants (false);
17291 if (simplejump_p (jump_insn))
17292 /* We're going to replace INSN with a longer form. */
17296 /* Create a branch-around label for the original
17298 new_label = gen_label_rtx ();
17299 emit_label (new_label);
17302 jump_sequence = get_insns ();
17305 emit_insn_after (jump_sequence, jump_insn);
17307 invert_jump (jump_insn, new_label, false);
17309 delete_insn (jump_insn);
17310 something_changed = true;
17313 while (something_changed);
17316 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
17321 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during
17322 insn splitting in mips16_lay_out_constants, DF insn info is only kept up
17323 to date if the CFG is available. */
17324 if (mips_cfg_in_reorg ())
17325 compute_bb_for_insn ();
17326 mips16_lay_out_constants (true);
17327 if (mips_cfg_in_reorg ())
17330 free_bb_for_insn ();
17334 /* We use a machine specific pass to do a second machine dependent reorg
17335 pass after delay branch scheduling. */
17337 static unsigned int
17338 mips_machine_reorg2 (void)
17340 mips_reorg_process_insns ();
17342 && TARGET_EXPLICIT_RELOCS
17344 && TARGET_VR4130_ALIGN)
17345 vr4130_align_insns ();
17346 if (mips_expand_ghost_gp_insns ())
17347 /* The expansion could invalidate some of the VR4130 alignment
17348 optimizations, but this should be an extremely rare case anyhow. */
17349 mips_reorg_process_insns ();
17350 mips16_split_long_branches ();
17356 const pass_data pass_data_mips_machine_reorg2 =
17358 RTL_PASS, /* type */
17359 "mach2", /* name */
17360 OPTGROUP_NONE, /* optinfo_flags */
17361 TV_MACH_DEP, /* tv_id */
17362 0, /* properties_required */
17363 0, /* properties_provided */
17364 0, /* properties_destroyed */
17365 0, /* todo_flags_start */
17366 0, /* todo_flags_finish */
17369 class pass_mips_machine_reorg2 : public rtl_opt_pass
17372 pass_mips_machine_reorg2(gcc::context *ctxt)
17373 : rtl_opt_pass(pass_data_mips_machine_reorg2, ctxt)
17376 /* opt_pass methods: */
17377 virtual unsigned int execute (function *) { return mips_machine_reorg2 (); }
17379 }; // class pass_mips_machine_reorg2
17381 } // anon namespace
17384 make_pass_mips_machine_reorg2 (gcc::context *ctxt)
17386 return new pass_mips_machine_reorg2 (ctxt);
17390 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
17391 in order to avoid duplicating too much logic from elsewhere. */
17394 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
17395 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
17398 rtx this_rtx, temp1, temp2, fnaddr;
17400 bool use_sibcall_p;
17402 /* Pretend to be a post-reload pass while generating rtl. */
17403 reload_completed = 1;
17405 /* Mark the end of the (empty) prologue. */
17406 emit_note (NOTE_INSN_PROLOGUE_END);
17408 /* Determine if we can use a sibcall to call FUNCTION directly. */
17409 fnaddr = XEXP (DECL_RTL (function), 0);
17410 use_sibcall_p = (mips_function_ok_for_sibcall (function, NULL)
17411 && const_call_insn_operand (fnaddr, Pmode));
17413 /* Determine if we need to load FNADDR from the GOT. */
17415 && (mips_got_symbol_type_p
17416 (mips_classify_symbol (fnaddr, SYMBOL_CONTEXT_LEA))))
17418 /* Pick a global pointer. Use a call-clobbered register if
17419 TARGET_CALL_SAVED_GP. */
17420 cfun->machine->global_pointer
17421 = TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM;
17422 cfun->machine->must_initialize_gp_p = true;
17423 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
17425 /* Set up the global pointer for n32 or n64 abicalls. */
17426 mips_emit_loadgp ();
17429 /* We need two temporary registers in some cases. */
17430 temp1 = gen_rtx_REG (Pmode, 2);
17431 temp2 = gen_rtx_REG (Pmode, 3);
17433 /* Find out which register contains the "this" pointer. */
17434 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
17435 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
17437 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST);
17439 /* Add DELTA to THIS_RTX. */
17442 rtx offset = GEN_INT (delta);
17443 if (!SMALL_OPERAND (delta))
17445 mips_emit_move (temp1, offset);
17448 emit_insn (gen_add3_insn (this_rtx, this_rtx, offset));
17451 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
17452 if (vcall_offset != 0)
17456 /* Set TEMP1 to *THIS_RTX. */
17457 mips_emit_move (temp1, gen_rtx_MEM (Pmode, this_rtx));
17459 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
17460 addr = mips_add_offset (temp2, temp1, vcall_offset);
17462 /* Load the offset and add it to THIS_RTX. */
17463 mips_emit_move (temp1, gen_rtx_MEM (Pmode, addr));
17464 emit_insn (gen_add3_insn (this_rtx, this_rtx, temp1));
17467 /* Jump to the target function. Use a sibcall if direct jumps are
17468 allowed, otherwise load the address into a register first. */
17471 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
17472 SIBLING_CALL_P (insn) = 1;
17476 /* This is messy. GAS treats "la $25,foo" as part of a call
17477 sequence and may allow a global "foo" to be lazily bound.
17478 The general move patterns therefore reject this combination.
17480 In this context, lazy binding would actually be OK
17481 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
17482 TARGET_CALL_SAVED_GP; see mips_load_call_address.
17483 We must therefore load the address via a temporary
17484 register if mips_dangerous_for_la25_p.
17486 If we jump to the temporary register rather than $25,
17487 the assembler can use the move insn to fill the jump's
17490 We can use the same technique for MIPS16 code, where $25
17491 is not a valid JR register. */
17492 if (TARGET_USE_PIC_FN_ADDR_REG
17494 && !mips_dangerous_for_la25_p (fnaddr))
17495 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
17496 mips_load_call_address (MIPS_CALL_SIBCALL, temp1, fnaddr);
17498 if (TARGET_USE_PIC_FN_ADDR_REG
17499 && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
17500 mips_emit_move (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
17501 emit_jump_insn (gen_indirect_jump (temp1));
17504 /* Run just enough of rest_of_compilation. This sequence was
17505 "borrowed" from alpha.c. */
17506 insn = get_insns ();
17507 split_all_insns_noflow ();
17508 mips16_lay_out_constants (true);
17509 shorten_branches (insn);
17510 final_start_function (insn, file, 1);
17511 final (insn, file, 1);
17512 final_end_function ();
17514 /* Clean up the vars set above. Note that final_end_function resets
17515 the global pointer for us. */
17516 reload_completed = 0;
17520 /* The last argument passed to mips_set_compression_mode,
17521 or negative if the function hasn't been called yet. */
17522 static unsigned int old_compression_mode = -1;
17524 /* Set up the target-dependent global state for ISA mode COMPRESSION_MODE,
17525 which is either MASK_MIPS16 or MASK_MICROMIPS. */
17528 mips_set_compression_mode (unsigned int compression_mode)
17531 if (compression_mode == old_compression_mode)
17534 /* Restore base settings of various flags. */
17535 target_flags = mips_base_target_flags;
17536 flag_schedule_insns = mips_base_schedule_insns;
17537 flag_reorder_blocks_and_partition = mips_base_reorder_blocks_and_partition;
17538 flag_move_loop_invariants = mips_base_move_loop_invariants;
17539 align_loops = mips_base_align_loops;
17540 align_jumps = mips_base_align_jumps;
17541 align_functions = mips_base_align_functions;
17542 target_flags &= ~(MASK_MIPS16 | MASK_MICROMIPS);
17543 target_flags |= compression_mode;
17545 if (compression_mode & MASK_MIPS16)
17547 /* Switch to MIPS16 mode. */
17548 target_flags |= MASK_MIPS16;
17550 /* Turn off SYNCI if it was on, MIPS16 doesn't support it. */
17551 target_flags &= ~MASK_SYNCI;
17553 /* Don't run the scheduler before reload, since it tends to
17554 increase register pressure. */
17555 flag_schedule_insns = 0;
17557 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
17558 the whole function to be in a single section. */
17559 flag_reorder_blocks_and_partition = 0;
17561 /* Don't move loop invariants, because it tends to increase
17562 register pressure. It also introduces an extra move in cases
17563 where the constant is the first operand in a two-operand binary
17564 instruction, or when it forms a register argument to a functon
17566 flag_move_loop_invariants = 0;
17568 target_flags |= MASK_EXPLICIT_RELOCS;
17570 /* Experiments suggest we get the best overall section-anchor
17571 results from using the range of an unextended LW or SW. Code
17572 that makes heavy use of byte or short accesses can do better
17573 with ranges of 0...31 and 0...63 respectively, but most code is
17574 sensitive to the range of LW and SW instead. */
17575 targetm.min_anchor_offset = 0;
17576 targetm.max_anchor_offset = 127;
17578 targetm.const_anchor = 0;
17580 /* MIPS16 has no BAL instruction. */
17581 target_flags &= ~MASK_RELAX_PIC_CALLS;
17583 /* The R4000 errata don't apply to any known MIPS16 cores.
17584 It's simpler to make the R4000 fixes and MIPS16 mode
17585 mutually exclusive. */
17586 target_flags &= ~MASK_FIX_R4000;
17588 if (flag_pic && !TARGET_OLDABI)
17589 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
17592 sorry ("MIPS16 -mxgot code");
17594 if (TARGET_HARD_FLOAT_ABI && !TARGET_OLDABI)
17595 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
17599 /* Switch to microMIPS or the standard encoding. */
17601 if (TARGET_MICROMIPS)
17602 /* Avoid branch likely. */
17603 target_flags &= ~MASK_BRANCHLIKELY;
17605 /* Provide default values for align_* for 64-bit targets. */
17608 if (align_loops == 0)
17610 if (align_jumps == 0)
17612 if (align_functions == 0)
17613 align_functions = 8;
17616 targetm.min_anchor_offset = -32768;
17617 targetm.max_anchor_offset = 32767;
17619 targetm.const_anchor = 0x8000;
17622 /* (Re)initialize MIPS target internals for new ISA. */
17623 mips_init_relocs ();
17625 if (compression_mode & MASK_MIPS16)
17627 if (!mips16_globals)
17628 mips16_globals = save_target_globals_default_opts ();
17630 restore_target_globals (mips16_globals);
17632 else if (compression_mode & MASK_MICROMIPS)
17634 if (!micromips_globals)
17635 micromips_globals = save_target_globals_default_opts ();
17637 restore_target_globals (micromips_globals);
17640 restore_target_globals (&default_target_globals);
17642 old_compression_mode = compression_mode;
17645 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
17646 function should use the MIPS16 or microMIPS ISA and switch modes
17650 mips_set_current_function (tree fndecl)
17652 mips_set_compression_mode (mips_get_compress_mode (fndecl));
17655 /* Allocate a chunk of memory for per-function machine-dependent data. */
17657 static struct machine_function *
17658 mips_init_machine_status (void)
17660 return ggc_cleared_alloc<machine_function> ();
17663 /* Return the processor associated with the given ISA level, or null
17664 if the ISA isn't valid. */
17666 static const struct mips_cpu_info *
17667 mips_cpu_info_from_isa (int isa)
17671 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
17672 if (mips_cpu_info_table[i].isa == isa)
17673 return mips_cpu_info_table + i;
17678 /* Return a mips_cpu_info entry determined by an option valued
17681 static const struct mips_cpu_info *
17682 mips_cpu_info_from_opt (int opt)
17686 case MIPS_ARCH_OPTION_FROM_ABI:
17687 /* 'from-abi' selects the most compatible architecture for the
17688 given ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit
17689 ABIs. For the EABIs, we have to decide whether we're using
17690 the 32-bit or 64-bit version. */
17691 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
17692 : ABI_NEEDS_64BIT_REGS ? 3
17693 : (TARGET_64BIT ? 3 : 1));
17695 case MIPS_ARCH_OPTION_NATIVE:
17696 gcc_unreachable ();
17699 return &mips_cpu_info_table[opt];
17703 /* Return a default mips_cpu_info entry, given that no -march= option
17704 was explicitly specified. */
17706 static const struct mips_cpu_info *
17707 mips_default_arch (void)
17709 #if defined (MIPS_CPU_STRING_DEFAULT)
17711 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
17712 if (strcmp (mips_cpu_info_table[i].name, MIPS_CPU_STRING_DEFAULT) == 0)
17713 return mips_cpu_info_table + i;
17714 gcc_unreachable ();
17715 #elif defined (MIPS_ISA_DEFAULT)
17716 return mips_cpu_info_from_isa (MIPS_ISA_DEFAULT);
17718 /* 'from-abi' makes a good default: you get whatever the ABI
17720 return mips_cpu_info_from_opt (MIPS_ARCH_OPTION_FROM_ABI);
17724 /* Set up globals to generate code for the ISA or processor
17725 described by INFO. */
17728 mips_set_architecture (const struct mips_cpu_info *info)
17732 mips_arch_info = info;
17733 mips_arch = info->cpu;
17734 mips_isa = info->isa;
17738 mips_isa_rev = (mips_isa & 31) + 1;
17742 /* Likewise for tuning. */
17745 mips_set_tune (const struct mips_cpu_info *info)
17749 mips_tune_info = info;
17750 mips_tune = info->cpu;
17754 /* Implement TARGET_OPTION_OVERRIDE. */
17757 mips_option_override (void)
17759 int i, start, regno, mode;
17761 if (global_options_set.x_mips_isa_option)
17762 mips_isa_option_info = &mips_cpu_info_table[mips_isa_option];
17764 #ifdef SUBTARGET_OVERRIDE_OPTIONS
17765 SUBTARGET_OVERRIDE_OPTIONS;
17768 /* MIPS16 and microMIPS cannot coexist. */
17769 if (TARGET_MICROMIPS && TARGET_MIPS16)
17770 error ("unsupported combination: %s", "-mips16 -mmicromips");
17772 /* Save the base compression state and process flags as though we
17773 were generating uncompressed code. */
17774 mips_base_compression_flags = TARGET_COMPRESSION;
17775 target_flags &= ~TARGET_COMPRESSION;
17777 /* -mno-float overrides -mhard-float and -msoft-float. */
17778 if (TARGET_NO_FLOAT)
17780 target_flags |= MASK_SOFT_FLOAT_ABI;
17781 target_flags_explicit |= MASK_SOFT_FLOAT_ABI;
17784 if (TARGET_FLIP_MIPS16)
17785 TARGET_INTERLINK_COMPRESSED = 1;
17787 /* Set the small data limit. */
17788 mips_small_data_threshold = (global_options_set.x_g_switch_value
17790 : MIPS_DEFAULT_GVALUE);
17792 /* The following code determines the architecture and register size.
17793 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
17794 The GAS and GCC code should be kept in sync as much as possible. */
17796 if (global_options_set.x_mips_arch_option)
17797 mips_set_architecture (mips_cpu_info_from_opt (mips_arch_option));
17799 if (mips_isa_option_info != 0)
17801 if (mips_arch_info == 0)
17802 mips_set_architecture (mips_isa_option_info);
17803 else if (mips_arch_info->isa != mips_isa_option_info->isa)
17804 error ("%<-%s%> conflicts with the other architecture options, "
17805 "which specify a %s processor",
17806 mips_isa_option_info->name,
17807 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
17810 if (mips_arch_info == 0)
17811 mips_set_architecture (mips_default_arch ());
17813 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
17814 error ("%<-march=%s%> is not compatible with the selected ABI",
17815 mips_arch_info->name);
17817 /* Optimize for mips_arch, unless -mtune selects a different processor. */
17818 if (global_options_set.x_mips_tune_option)
17819 mips_set_tune (mips_cpu_info_from_opt (mips_tune_option));
17821 if (mips_tune_info == 0)
17822 mips_set_tune (mips_arch_info);
17824 if ((target_flags_explicit & MASK_64BIT) != 0)
17826 /* The user specified the size of the integer registers. Make sure
17827 it agrees with the ABI and ISA. */
17828 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
17829 error ("%<-mgp64%> used with a 32-bit processor");
17830 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
17831 error ("%<-mgp32%> used with a 64-bit ABI");
17832 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
17833 error ("%<-mgp64%> used with a 32-bit ABI");
17837 /* Infer the integer register size from the ABI and processor.
17838 Restrict ourselves to 32-bit registers if that's all the
17839 processor has, or if the ABI cannot handle 64-bit registers. */
17840 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
17841 target_flags &= ~MASK_64BIT;
17843 target_flags |= MASK_64BIT;
17846 if ((target_flags_explicit & MASK_FLOAT64) != 0)
17848 if (mips_isa_rev >= 6 && !TARGET_FLOAT64)
17849 error ("the %qs architecture does not support %<-mfp32%>",
17850 mips_arch_info->name);
17851 else if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
17852 error ("unsupported combination: %s", "-mfp64 -msingle-float");
17853 else if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
17854 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
17855 else if (!TARGET_64BIT && TARGET_FLOAT64)
17857 if (!ISA_HAS_MXHC1)
17858 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
17859 " the target supports the mfhc1 and mthc1 instructions");
17860 else if (mips_abi != ABI_32)
17861 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
17867 /* -msingle-float selects 32-bit float registers. On r6 and later,
17868 -mdouble-float selects 64-bit float registers, since the old paired
17869 register model is not supported. In other cases the float registers
17870 should be the same size as the integer ones. */
17871 if (mips_isa_rev >= 6 && TARGET_DOUBLE_FLOAT && !TARGET_FLOATXX)
17872 target_flags |= MASK_FLOAT64;
17873 else if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
17874 target_flags |= MASK_FLOAT64;
17876 target_flags &= ~MASK_FLOAT64;
17879 if (mips_abi != ABI_32 && TARGET_FLOATXX)
17880 error ("%<-mfpxx%> can only be used with the o32 ABI");
17881 else if (TARGET_FLOAT64 && TARGET_FLOATXX)
17882 error ("unsupported combination: %s", "-mfp64 -mfpxx");
17883 else if (ISA_MIPS1 && !TARGET_FLOAT32)
17884 error ("%<-march=%s%> requires %<-mfp32%>", mips_arch_info->name);
17885 else if (TARGET_FLOATXX && !mips_lra_flag)
17886 error ("%<-mfpxx%> requires %<-mlra%>");
17888 /* End of code shared with GAS. */
17890 /* The R5900 FPU only supports single precision. */
17891 if (TARGET_MIPS5900 && TARGET_HARD_FLOAT_ABI && TARGET_DOUBLE_FLOAT)
17892 error ("unsupported combination: %s",
17893 "-march=r5900 -mhard-float -mdouble-float");
17895 /* If a -mlong* option was given, check that it matches the ABI,
17896 otherwise infer the -mlong* setting from the other options. */
17897 if ((target_flags_explicit & MASK_LONG64) != 0)
17901 if (mips_abi == ABI_N32)
17902 error ("%qs is incompatible with %qs", "-mabi=n32", "-mlong64");
17903 else if (mips_abi == ABI_32)
17904 error ("%qs is incompatible with %qs", "-mabi=32", "-mlong64");
17905 else if (mips_abi == ABI_O64 && TARGET_ABICALLS)
17906 /* We have traditionally allowed non-abicalls code to use
17907 an LP64 form of o64. However, it would take a bit more
17908 effort to support the combination of 32-bit GOT entries
17909 and 64-bit pointers, so we treat the abicalls case as
17911 error ("the combination of %qs and %qs is incompatible with %qs",
17912 "-mabi=o64", "-mabicalls", "-mlong64");
17916 if (mips_abi == ABI_64)
17917 error ("%qs is incompatible with %qs", "-mabi=64", "-mlong32");
17922 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
17923 target_flags |= MASK_LONG64;
17925 target_flags &= ~MASK_LONG64;
17928 if (!TARGET_OLDABI)
17929 flag_pcc_struct_return = 0;
17931 /* Decide which rtx_costs structure to use. */
17933 mips_cost = &mips_rtx_cost_optimize_size;
17935 mips_cost = &mips_rtx_cost_data[mips_tune];
17937 /* If the user hasn't specified a branch cost, use the processor's
17939 if (mips_branch_cost == 0)
17940 mips_branch_cost = mips_cost->branch_cost;
17942 /* If neither -mbranch-likely nor -mno-branch-likely was given
17943 on the command line, set MASK_BRANCHLIKELY based on the target
17944 architecture and tuning flags. Annulled delay slots are a
17945 size win, so we only consider the processor-specific tuning
17946 for !optimize_size. */
17947 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
17949 if (ISA_HAS_BRANCHLIKELY
17951 || (mips_tune_info->tune_flags & PTF_AVOID_BRANCHLIKELY) == 0))
17952 target_flags |= MASK_BRANCHLIKELY;
17954 target_flags &= ~MASK_BRANCHLIKELY;
17956 else if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
17957 warning (0, "the %qs architecture does not support branch-likely"
17958 " instructions", mips_arch_info->name);
17960 /* If the user hasn't specified -mimadd or -mno-imadd set
17961 MASK_IMADD based on the target architecture and tuning
17963 if ((target_flags_explicit & MASK_IMADD) == 0)
17965 if (ISA_HAS_MADD_MSUB &&
17966 (mips_tune_info->tune_flags & PTF_AVOID_IMADD) == 0)
17967 target_flags |= MASK_IMADD;
17969 target_flags &= ~MASK_IMADD;
17971 else if (TARGET_IMADD && !ISA_HAS_MADD_MSUB)
17972 warning (0, "the %qs architecture does not support madd or msub"
17973 " instructions", mips_arch_info->name);
17975 /* If neither -modd-spreg nor -mno-odd-spreg was given on the command
17976 line, set MASK_ODD_SPREG based on the ISA and ABI. */
17977 if ((target_flags_explicit & MASK_ODD_SPREG) == 0)
17979 /* Disable TARGET_ODD_SPREG when using the o32 FPXX ABI. */
17980 if (!ISA_HAS_ODD_SPREG || TARGET_FLOATXX)
17981 target_flags &= ~MASK_ODD_SPREG;
17983 target_flags |= MASK_ODD_SPREG;
17985 else if (TARGET_ODD_SPREG && !ISA_HAS_ODD_SPREG)
17986 warning (0, "the %qs architecture does not support odd single-precision"
17987 " registers", mips_arch_info->name);
17989 if (!TARGET_ODD_SPREG && TARGET_64BIT)
17991 error ("unsupported combination: %s", "-mgp64 -mno-odd-spreg");
17992 /* Allow compilation to continue further even though invalid output
17993 will be produced. */
17994 target_flags |= MASK_ODD_SPREG;
17997 if (!ISA_HAS_COMPACT_BRANCHES && mips_cb == MIPS_CB_ALWAYS)
17999 error ("unsupported combination: %qs%s %s",
18000 mips_arch_info->name, TARGET_MICROMIPS ? " -mmicromips" : "",
18001 "-mcompact-branches=always");
18003 else if (!ISA_HAS_DELAY_SLOTS && mips_cb == MIPS_CB_NEVER)
18005 error ("unsupported combination: %qs%s %s",
18006 mips_arch_info->name, TARGET_MICROMIPS ? " -mmicromips" : "",
18007 "-mcompact-branches=never");
18010 /* Require explicit relocs for MIPS R6 onwards. This enables simplification
18011 of the compact branch and jump support through the backend. */
18012 if (!TARGET_EXPLICIT_RELOCS && mips_isa_rev >= 6)
18014 error ("unsupported combination: %qs %s",
18015 mips_arch_info->name, "-mno-explicit-relocs");
18018 /* The effect of -mabicalls isn't defined for the EABI. */
18019 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
18021 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
18022 target_flags &= ~MASK_ABICALLS;
18025 /* PIC requires -mabicalls. */
18028 if (mips_abi == ABI_EABI)
18029 error ("cannot generate position-independent code for %qs",
18031 else if (!TARGET_ABICALLS)
18032 error ("position-independent code requires %qs", "-mabicalls");
18035 if (TARGET_ABICALLS_PIC2)
18036 /* We need to set flag_pic for executables as well as DSOs
18037 because we may reference symbols that are not defined in
18038 the final executable. (MIPS does not use things like
18039 copy relocs, for example.)
18041 There is a body of code that uses __PIC__ to distinguish
18042 between -mabicalls and -mno-abicalls code. The non-__PIC__
18043 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
18044 long as any indirect jumps use $25. */
18047 /* -mvr4130-align is a "speed over size" optimization: it usually produces
18048 faster code, but at the expense of more nops. Enable it at -O3 and
18050 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
18051 target_flags |= MASK_VR4130_ALIGN;
18053 /* Prefer a call to memcpy over inline code when optimizing for size,
18054 though see MOVE_RATIO in mips.h. */
18055 if (optimize_size && (target_flags_explicit & MASK_MEMCPY) == 0)
18056 target_flags |= MASK_MEMCPY;
18058 /* If we have a nonzero small-data limit, check that the -mgpopt
18059 setting is consistent with the other target flags. */
18060 if (mips_small_data_threshold > 0)
18064 if (!TARGET_EXPLICIT_RELOCS)
18065 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
18067 TARGET_LOCAL_SDATA = false;
18068 TARGET_EXTERN_SDATA = false;
18072 if (TARGET_VXWORKS_RTP)
18073 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
18075 if (TARGET_ABICALLS)
18076 warning (0, "cannot use small-data accesses for %qs",
18081 /* Set NaN and ABS defaults. */
18082 if (mips_nan == MIPS_IEEE_754_DEFAULT && !ISA_HAS_IEEE_754_LEGACY)
18083 mips_nan = MIPS_IEEE_754_2008;
18084 if (mips_abs == MIPS_IEEE_754_DEFAULT && !ISA_HAS_IEEE_754_LEGACY)
18085 mips_abs = MIPS_IEEE_754_2008;
18087 /* Check for IEEE 754 legacy/2008 support. */
18088 if ((mips_nan == MIPS_IEEE_754_LEGACY
18089 || mips_abs == MIPS_IEEE_754_LEGACY)
18090 && !ISA_HAS_IEEE_754_LEGACY)
18091 warning (0, "the %qs architecture does not support %<-m%s=legacy%>",
18092 mips_arch_info->name,
18093 mips_nan == MIPS_IEEE_754_LEGACY ? "nan" : "abs");
18095 if ((mips_nan == MIPS_IEEE_754_2008
18096 || mips_abs == MIPS_IEEE_754_2008)
18097 && !ISA_HAS_IEEE_754_2008)
18098 warning (0, "the %qs architecture does not support %<-m%s=2008%>",
18099 mips_arch_info->name,
18100 mips_nan == MIPS_IEEE_754_2008 ? "nan" : "abs");
18102 /* Pre-IEEE 754-2008 MIPS hardware has a quirky almost-IEEE format
18103 for all its floating point. */
18104 if (mips_nan != MIPS_IEEE_754_2008)
18106 REAL_MODE_FORMAT (SFmode) = &mips_single_format;
18107 REAL_MODE_FORMAT (DFmode) = &mips_double_format;
18108 REAL_MODE_FORMAT (TFmode) = &mips_quad_format;
18111 /* Make sure that the user didn't turn off paired single support when
18112 MIPS-3D support is requested. */
18114 && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
18115 && !TARGET_PAIRED_SINGLE_FLOAT)
18116 error ("%<-mips3d%> requires %<-mpaired-single%>");
18118 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
18120 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
18122 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
18123 and TARGET_HARD_FLOAT_ABI are both true. */
18124 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT_ABI))
18126 error ("%qs must be used with %qs",
18127 TARGET_MIPS3D ? "-mips3d" : "-mpaired-single",
18128 TARGET_HARD_FLOAT_ABI ? "-mfp64" : "-mhard-float");
18129 target_flags &= ~MASK_PAIRED_SINGLE_FLOAT;
18133 /* Make sure that -mpaired-single is only used on ISAs that support it.
18134 We must disable it otherwise since it relies on other ISA properties
18135 like ISA_HAS_8CC having their normal values. */
18136 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_HAS_PAIRED_SINGLE)
18138 error ("the %qs architecture does not support paired-single"
18139 " instructions", mips_arch_info->name);
18140 target_flags &= ~MASK_PAIRED_SINGLE_FLOAT;
18144 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
18145 && !TARGET_CACHE_BUILTIN)
18147 error ("%qs requires a target that provides the %qs instruction",
18148 "-mr10k-cache-barrier", "cache");
18149 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE;
18152 /* If TARGET_DSPR2, enable TARGET_DSP. */
18156 if (TARGET_DSP && mips_isa_rev >= 6)
18158 error ("the %qs architecture does not support DSP instructions",
18159 mips_arch_info->name);
18160 TARGET_DSP = false;
18161 TARGET_DSPR2 = false;
18164 /* .eh_frame addresses should be the same width as a C pointer.
18165 Most MIPS ABIs support only one pointer size, so the assembler
18166 will usually know exactly how big an .eh_frame address is.
18168 Unfortunately, this is not true of the 64-bit EABI. The ABI was
18169 originally defined to use 64-bit pointers (i.e. it is LP64), and
18170 this is still the default mode. However, we also support an n32-like
18171 ILP32 mode, which is selected by -mlong32. The problem is that the
18172 assembler has traditionally not had an -mlong option, so it has
18173 traditionally not known whether we're using the ILP32 or LP64 form.
18175 As it happens, gas versions up to and including 2.19 use _32-bit_
18176 addresses for EABI64 .cfi_* directives. This is wrong for the
18177 default LP64 mode, so we can't use the directives by default.
18178 Moreover, since gas's current behavior is at odds with gcc's
18179 default behavior, it seems unwise to rely on future versions
18180 of gas behaving the same way. We therefore avoid using .cfi
18181 directives for -mlong32 as well. */
18182 if (mips_abi == ABI_EABI && TARGET_64BIT)
18183 flag_dwarf2_cfi_asm = 0;
18185 /* .cfi_* directives generate a read-only section, so fall back on
18186 manual .eh_frame creation if we need the section to be writable. */
18187 if (TARGET_WRITABLE_EH_FRAME)
18188 flag_dwarf2_cfi_asm = 0;
18190 mips_init_print_operand_punct ();
18192 /* Set up array to map GCC register number to debug register number.
18193 Ignore the special purpose register numbers. */
18195 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
18197 mips_dbx_regno[i] = IGNORED_DWARF_REGNUM;
18198 if (GP_REG_P (i) || FP_REG_P (i) || ALL_COP_REG_P (i))
18199 mips_dwarf_regno[i] = i;
18201 mips_dwarf_regno[i] = INVALID_REGNUM;
18204 start = GP_DBX_FIRST - GP_REG_FIRST;
18205 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
18206 mips_dbx_regno[i] = i + start;
18208 start = FP_DBX_FIRST - FP_REG_FIRST;
18209 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
18210 mips_dbx_regno[i] = i + start;
18212 /* Accumulator debug registers use big-endian ordering. */
18213 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
18214 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
18215 mips_dwarf_regno[HI_REGNUM] = MD_REG_FIRST + 0;
18216 mips_dwarf_regno[LO_REGNUM] = MD_REG_FIRST + 1;
18217 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
18219 mips_dwarf_regno[i + TARGET_LITTLE_ENDIAN] = i;
18220 mips_dwarf_regno[i + TARGET_BIG_ENDIAN] = i + 1;
18223 /* Set up mips_hard_regno_mode_ok. */
18224 for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
18225 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
18226 mips_hard_regno_mode_ok[mode][regno]
18227 = mips_hard_regno_mode_ok_p (regno, (machine_mode) mode);
18229 /* Function to allocate machine-dependent function status. */
18230 init_machine_status = &mips_init_machine_status;
18232 /* Default to working around R4000 errata only if the processor
18233 was selected explicitly. */
18234 if ((target_flags_explicit & MASK_FIX_R4000) == 0
18235 && strcmp (mips_arch_info->name, "r4000") == 0)
18236 target_flags |= MASK_FIX_R4000;
18238 /* Default to working around R4400 errata only if the processor
18239 was selected explicitly. */
18240 if ((target_flags_explicit & MASK_FIX_R4400) == 0
18241 && strcmp (mips_arch_info->name, "r4400") == 0)
18242 target_flags |= MASK_FIX_R4400;
18244 /* Default to working around R10000 errata only if the processor
18245 was selected explicitly. */
18246 if ((target_flags_explicit & MASK_FIX_R10000) == 0
18247 && strcmp (mips_arch_info->name, "r10000") == 0)
18248 target_flags |= MASK_FIX_R10000;
18250 /* Make sure that branch-likely instructions available when using
18251 -mfix-r10000. The instructions are not available if either:
18253 1. -mno-branch-likely was passed.
18254 2. The selected ISA does not support branch-likely and
18255 the command line does not include -mbranch-likely. */
18256 if (TARGET_FIX_R10000
18257 && ((target_flags_explicit & MASK_BRANCHLIKELY) == 0
18258 ? !ISA_HAS_BRANCHLIKELY
18259 : !TARGET_BRANCHLIKELY))
18260 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
18262 if (TARGET_SYNCI && !ISA_HAS_SYNCI)
18264 warning (0, "the %qs architecture does not support the synci "
18265 "instruction", mips_arch_info->name);
18266 target_flags &= ~MASK_SYNCI;
18269 /* Only optimize PIC indirect calls if they are actually required. */
18270 if (!TARGET_USE_GOT || !TARGET_EXPLICIT_RELOCS)
18271 target_flags &= ~MASK_RELAX_PIC_CALLS;
18273 /* Save base state of options. */
18274 mips_base_target_flags = target_flags;
18275 mips_base_schedule_insns = flag_schedule_insns;
18276 mips_base_reorder_blocks_and_partition = flag_reorder_blocks_and_partition;
18277 mips_base_move_loop_invariants = flag_move_loop_invariants;
18278 mips_base_align_loops = align_loops;
18279 mips_base_align_jumps = align_jumps;
18280 mips_base_align_functions = align_functions;
18282 /* Now select the ISA mode.
18284 Do all CPP-sensitive stuff in uncompressed mode; we'll switch modes
18285 later if required. */
18286 mips_set_compression_mode (0);
18288 /* We register a second machine specific reorg pass after delay slot
18289 filling. Registering the pass must be done at start up. It's
18290 convenient to do it here. */
18291 opt_pass *new_pass = make_pass_mips_machine_reorg2 (g);
18292 struct register_pass_info insert_pass_mips_machine_reorg2 =
18294 new_pass, /* pass */
18295 "dbr", /* reference_pass_name */
18296 1, /* ref_pass_instance_number */
18297 PASS_POS_INSERT_AFTER /* po_op */
18299 register_pass (&insert_pass_mips_machine_reorg2);
18301 if (TARGET_HARD_FLOAT_ABI && TARGET_MIPS5900)
18302 REAL_MODE_FORMAT (SFmode) = &spu_single_format;
18304 mips_register_frame_header_opt ();
18307 /* Swap the register information for registers I and I + 1, which
18308 currently have the wrong endianness. Note that the registers'
18309 fixedness and call-clobberedness might have been set on the
18313 mips_swap_registers (unsigned int i)
18318 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
18319 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
18321 SWAP_INT (fixed_regs[i], fixed_regs[i + 1]);
18322 SWAP_INT (call_used_regs[i], call_used_regs[i + 1]);
18323 SWAP_INT (call_really_used_regs[i], call_really_used_regs[i + 1]);
18324 SWAP_STRING (reg_names[i], reg_names[i + 1]);
18330 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
18333 mips_conditional_register_usage (void)
18338 /* These DSP control register fields are global. */
18339 global_regs[CCDSP_PO_REGNUM] = 1;
18340 global_regs[CCDSP_SC_REGNUM] = 1;
18343 AND_COMPL_HARD_REG_SET (accessible_reg_set,
18344 reg_class_contents[(int) DSP_ACC_REGS]);
18347 AND_COMPL_HARD_REG_SET (accessible_reg_set,
18348 reg_class_contents[(int) MD_REGS]);
18350 if (!TARGET_HARD_FLOAT)
18352 AND_COMPL_HARD_REG_SET (accessible_reg_set,
18353 reg_class_contents[(int) FP_REGS]);
18354 AND_COMPL_HARD_REG_SET (accessible_reg_set,
18355 reg_class_contents[(int) ST_REGS]);
18357 else if (!ISA_HAS_8CC)
18359 /* We only have a single condition-code register. We implement
18360 this by fixing all the condition-code registers and generating
18361 RTL that refers directly to ST_REG_FIRST. */
18362 AND_COMPL_HARD_REG_SET (accessible_reg_set,
18363 reg_class_contents[(int) ST_REGS]);
18365 SET_HARD_REG_BIT (accessible_reg_set, FPSW_REGNUM);
18366 fixed_regs[FPSW_REGNUM] = call_used_regs[FPSW_REGNUM] = 1;
18370 /* In MIPS16 mode, we prohibit the unused $s registers, since they
18371 are call-saved, and saving them via a MIPS16 register would
18372 probably waste more time than just reloading the value.
18374 We permit the $t temporary registers when optimizing for speed
18375 but not when optimizing for space because using them results in
18376 code that is larger (but faster) then not using them. We do
18377 allow $24 (t8) because it is used in CMP and CMPI instructions
18378 and $25 (t9) because it is used as the function call address in
18381 fixed_regs[18] = call_used_regs[18] = 1;
18382 fixed_regs[19] = call_used_regs[19] = 1;
18383 fixed_regs[20] = call_used_regs[20] = 1;
18384 fixed_regs[21] = call_used_regs[21] = 1;
18385 fixed_regs[22] = call_used_regs[22] = 1;
18386 fixed_regs[23] = call_used_regs[23] = 1;
18387 fixed_regs[26] = call_used_regs[26] = 1;
18388 fixed_regs[27] = call_used_regs[27] = 1;
18389 fixed_regs[30] = call_used_regs[30] = 1;
18392 fixed_regs[8] = call_used_regs[8] = 1;
18393 fixed_regs[9] = call_used_regs[9] = 1;
18394 fixed_regs[10] = call_used_regs[10] = 1;
18395 fixed_regs[11] = call_used_regs[11] = 1;
18396 fixed_regs[12] = call_used_regs[12] = 1;
18397 fixed_regs[13] = call_used_regs[13] = 1;
18398 fixed_regs[14] = call_used_regs[14] = 1;
18399 fixed_regs[15] = call_used_regs[15] = 1;
18402 /* Do not allow HI and LO to be treated as register operands.
18403 There are no MTHI or MTLO instructions (or any real need
18404 for them) and one-way registers cannot easily be reloaded. */
18405 AND_COMPL_HARD_REG_SET (operand_reg_set,
18406 reg_class_contents[(int) MD_REGS]);
18408 /* $f20-$f23 are call-clobbered for n64. */
18409 if (mips_abi == ABI_64)
18412 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
18413 call_really_used_regs[regno] = call_used_regs[regno] = 1;
18415 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
18416 for n32 and o32 FP64. */
18417 if (mips_abi == ABI_N32
18418 || (mips_abi == ABI_32
18419 && TARGET_FLOAT64))
18422 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
18423 call_really_used_regs[regno] = call_used_regs[regno] = 1;
18425 /* Make sure that double-register accumulator values are correctly
18426 ordered for the current endianness. */
18427 if (TARGET_LITTLE_ENDIAN)
18429 unsigned int regno;
18431 mips_swap_registers (MD_REG_FIRST);
18432 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno += 2)
18433 mips_swap_registers (regno);
18437 /* Implement EH_USES. */
18440 mips_eh_uses (unsigned int regno)
18442 if (reload_completed && !TARGET_ABSOLUTE_JUMPS)
18444 /* We need to force certain registers to be live in order to handle
18445 PIC long branches correctly. See mips_must_initialize_gp_p for
18447 if (mips_cfun_has_cprestore_slot_p ())
18449 if (regno == CPRESTORE_SLOT_REGNUM)
18454 if (cfun->machine->global_pointer == regno)
18462 /* Implement EPILOGUE_USES. */
18465 mips_epilogue_uses (unsigned int regno)
18467 /* Say that the epilogue uses the return address register. Note that
18468 in the case of sibcalls, the values "used by the epilogue" are
18469 considered live at the start of the called function. */
18470 if (regno == RETURN_ADDR_REGNUM)
18473 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
18474 See the comment above load_call<mode> for details. */
18475 if (TARGET_USE_GOT && (regno) == GOT_VERSION_REGNUM)
18478 /* An interrupt handler must preserve some registers that are
18479 ordinarily call-clobbered. */
18480 if (cfun->machine->interrupt_handler_p
18481 && mips_interrupt_extra_call_saved_reg_p (regno))
18487 /* Return true if INSN needs to be wrapped in ".set noat".
18488 INSN has NOPERANDS operands, stored in OPVEC. */
18491 mips_need_noat_wrapper_p (rtx_insn *insn, rtx *opvec, int noperands)
18493 if (recog_memoized (insn) >= 0)
18495 subrtx_iterator::array_type array;
18496 for (int i = 0; i < noperands; i++)
18497 FOR_EACH_SUBRTX (iter, array, opvec[i], NONCONST)
18498 if (REG_P (*iter) && REGNO (*iter) == AT_REGNUM)
18504 /* Implement FINAL_PRESCAN_INSN. */
18507 mips_final_prescan_insn (rtx_insn *insn, rtx *opvec, int noperands)
18509 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
18510 mips_push_asm_switch (&mips_noat);
18513 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */
18516 mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED, rtx_insn *insn,
18517 rtx *opvec, int noperands)
18519 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
18520 mips_pop_asm_switch (&mips_noat);
18523 /* Return the function that is used to expand the <u>mulsidi3 pattern.
18524 EXT_CODE is the code of the extension used. Return NULL if widening
18525 multiplication shouldn't be used. */
18528 mips_mulsidi3_gen_fn (enum rtx_code ext_code)
18532 signed_p = ext_code == SIGN_EXTEND;
18535 /* Don't use widening multiplication with MULT when we have DMUL. Even
18536 with the extension of its input operands DMUL is faster. Note that
18537 the extension is not needed for signed multiplication. In order to
18538 ensure that we always remove the redundant sign-extension in this
18539 case we still expand mulsidi3 for DMUL. */
18540 if (ISA_HAS_R6DMUL)
18541 return signed_p ? gen_mulsidi3_64bit_r6dmul : NULL;
18543 return signed_p ? gen_mulsidi3_64bit_dmul : NULL;
18546 ? gen_mulsidi3_64bit_mips16
18547 : gen_umulsidi3_64bit_mips16);
18548 if (TARGET_FIX_R4000)
18550 return signed_p ? gen_mulsidi3_64bit : gen_umulsidi3_64bit;
18555 return (signed_p ? gen_mulsidi3_32bit_r6 : gen_umulsidi3_32bit_r6);
18558 ? gen_mulsidi3_32bit_mips16
18559 : gen_umulsidi3_32bit_mips16);
18560 if (TARGET_FIX_R4000 && !ISA_HAS_DSP)
18561 return signed_p ? gen_mulsidi3_32bit_r4000 : gen_umulsidi3_32bit_r4000;
18562 return signed_p ? gen_mulsidi3_32bit : gen_umulsidi3_32bit;
18566 /* Return true if PATTERN matches the kind of instruction generated by
18567 umips_build_save_restore. SAVE_P is true for store. */
18570 umips_save_restore_pattern_p (bool save_p, rtx pattern)
18574 HOST_WIDE_INT first_offset = 0;
18575 rtx first_base = 0;
18576 unsigned int regmask = 0;
18578 for (n = 0; n < XVECLEN (pattern, 0); n++)
18580 rtx set, reg, mem, this_base;
18581 HOST_WIDE_INT this_offset;
18583 /* Check that we have a SET. */
18584 set = XVECEXP (pattern, 0, n);
18585 if (GET_CODE (set) != SET)
18588 /* Check that the SET is a load (if restoring) or a store
18590 mem = save_p ? SET_DEST (set) : SET_SRC (set);
18591 if (!MEM_P (mem) || MEM_VOLATILE_P (mem))
18594 /* Check that the address is the sum of base and a possibly-zero
18595 constant offset. Determine if the offset is in range. */
18596 mips_split_plus (XEXP (mem, 0), &this_base, &this_offset);
18597 if (!REG_P (this_base))
18602 if (!UMIPS_12BIT_OFFSET_P (this_offset))
18604 first_base = this_base;
18605 first_offset = this_offset;
18609 /* Check that the save slots are consecutive. */
18610 if (REGNO (this_base) != REGNO (first_base)
18611 || this_offset != first_offset + UNITS_PER_WORD * n)
18615 /* Check that SET's other operand is a register. */
18616 reg = save_p ? SET_SRC (set) : SET_DEST (set);
18620 regmask |= 1 << REGNO (reg);
18623 for (i = 0; i < ARRAY_SIZE (umips_swm_mask); i++)
18624 if (regmask == umips_swm_mask[i])
18630 /* Return the assembly instruction for microMIPS LWM or SWM.
18631 SAVE_P and PATTERN are as for umips_save_restore_pattern_p. */
18634 umips_output_save_restore (bool save_p, rtx pattern)
18636 static char buffer[300];
18639 HOST_WIDE_INT offset;
18640 rtx base, mem, set, last_set, last_reg;
18642 /* Parse the pattern. */
18643 gcc_assert (umips_save_restore_pattern_p (save_p, pattern));
18645 s = strcpy (buffer, save_p ? "swm\t" : "lwm\t");
18647 n = XVECLEN (pattern, 0);
18649 set = XVECEXP (pattern, 0, 0);
18650 mem = save_p ? SET_DEST (set) : SET_SRC (set);
18651 mips_split_plus (XEXP (mem, 0), &base, &offset);
18653 last_set = XVECEXP (pattern, 0, n - 1);
18654 last_reg = save_p ? SET_SRC (last_set) : SET_DEST (last_set);
18656 if (REGNO (last_reg) == 31)
18659 gcc_assert (n <= 9);
18663 s += sprintf (s, "%s,", reg_names[16]);
18665 s += sprintf (s, "%s-%s,", reg_names[16], reg_names[15 + n]);
18667 s += sprintf (s, "%s-%s,%s,", reg_names[16], reg_names[23],
18670 if (REGNO (last_reg) == 31)
18671 s += sprintf (s, "%s,", reg_names[31]);
18673 s += sprintf (s, "%d(%s)", (int)offset, reg_names[REGNO (base)]);
18677 /* Return true if MEM1 and MEM2 use the same base register, and the
18678 offset of MEM2 equals the offset of MEM1 plus 4. FIRST_REG is the
18679 register into (from) which the contents of MEM1 will be loaded
18680 (stored), depending on the value of LOAD_P.
18681 SWAP_P is true when the 1st and 2nd instructions are swapped. */
18684 umips_load_store_pair_p_1 (bool load_p, bool swap_p,
18685 rtx first_reg, rtx mem1, rtx mem2)
18688 HOST_WIDE_INT offset1, offset2;
18690 if (!MEM_P (mem1) || !MEM_P (mem2))
18693 mips_split_plus (XEXP (mem1, 0), &base1, &offset1);
18694 mips_split_plus (XEXP (mem2, 0), &base2, &offset2);
18696 if (!REG_P (base1) || !rtx_equal_p (base1, base2))
18699 /* Avoid invalid load pair instructions. */
18700 if (load_p && REGNO (first_reg) == REGNO (base1))
18703 /* We must avoid this case for anti-dependence.
18706 first_reg is $2, but the base is $3. */
18709 && REGNO (first_reg) + 1 == REGNO (base1))
18712 if (offset2 != offset1 + 4)
18715 if (!UMIPS_12BIT_OFFSET_P (offset1))
18722 mips_load_store_bonding_p (rtx *operands, machine_mode mode, bool load_p)
18724 rtx reg1, reg2, mem1, mem2, base1, base2;
18725 enum reg_class rc1, rc2;
18726 HOST_WIDE_INT offset1, offset2;
18730 reg1 = operands[0];
18731 reg2 = operands[2];
18732 mem1 = operands[1];
18733 mem2 = operands[3];
18737 reg1 = operands[1];
18738 reg2 = operands[3];
18739 mem1 = operands[0];
18740 mem2 = operands[2];
18743 if (mips_address_insns (XEXP (mem1, 0), mode, false) == 0
18744 || mips_address_insns (XEXP (mem2, 0), mode, false) == 0)
18747 mips_split_plus (XEXP (mem1, 0), &base1, &offset1);
18748 mips_split_plus (XEXP (mem2, 0), &base2, &offset2);
18750 /* Base regs do not match. */
18751 if (!REG_P (base1) || !rtx_equal_p (base1, base2))
18754 /* Either of the loads is clobbering base register. It is legitimate to bond
18755 loads if second load clobbers base register. However, hardware does not
18756 support such bonding. */
18758 && (REGNO (reg1) == REGNO (base1)
18759 || (REGNO (reg2) == REGNO (base1))))
18762 /* Loading in same registers. */
18764 && REGNO (reg1) == REGNO (reg2))
18767 /* The loads/stores are not of same type. */
18768 rc1 = REGNO_REG_CLASS (REGNO (reg1));
18769 rc2 = REGNO_REG_CLASS (REGNO (reg2));
18771 && !reg_class_subset_p (rc1, rc2)
18772 && !reg_class_subset_p (rc2, rc1))
18775 if (abs (offset1 - offset2) != GET_MODE_SIZE (mode))
18781 /* OPERANDS describes the operands to a pair of SETs, in the order
18782 dest1, src1, dest2, src2. Return true if the operands can be used
18783 in an LWP or SWP instruction; LOAD_P says which. */
18786 umips_load_store_pair_p (bool load_p, rtx *operands)
18788 rtx reg1, reg2, mem1, mem2;
18792 reg1 = operands[0];
18793 reg2 = operands[2];
18794 mem1 = operands[1];
18795 mem2 = operands[3];
18799 reg1 = operands[1];
18800 reg2 = operands[3];
18801 mem1 = operands[0];
18802 mem2 = operands[2];
18805 if (REGNO (reg2) == REGNO (reg1) + 1)
18806 return umips_load_store_pair_p_1 (load_p, false, reg1, mem1, mem2);
18808 if (REGNO (reg1) == REGNO (reg2) + 1)
18809 return umips_load_store_pair_p_1 (load_p, true, reg2, mem2, mem1);
18814 /* Return the assembly instruction for a microMIPS LWP or SWP in which
18815 the first register is REG and the first memory slot is MEM.
18816 LOAD_P is true for LWP. */
18819 umips_output_load_store_pair_1 (bool load_p, rtx reg, rtx mem)
18821 rtx ops[] = {reg, mem};
18824 output_asm_insn ("lwp\t%0,%1", ops);
18826 output_asm_insn ("swp\t%0,%1", ops);
18829 /* Output the assembly instruction for a microMIPS LWP or SWP instruction.
18830 LOAD_P and OPERANDS are as for umips_load_store_pair_p. */
18833 umips_output_load_store_pair (bool load_p, rtx *operands)
18835 rtx reg1, reg2, mem1, mem2;
18838 reg1 = operands[0];
18839 reg2 = operands[2];
18840 mem1 = operands[1];
18841 mem2 = operands[3];
18845 reg1 = operands[1];
18846 reg2 = operands[3];
18847 mem1 = operands[0];
18848 mem2 = operands[2];
18851 if (REGNO (reg2) == REGNO (reg1) + 1)
18853 umips_output_load_store_pair_1 (load_p, reg1, mem1);
18857 gcc_assert (REGNO (reg1) == REGNO (reg2) + 1);
18858 umips_output_load_store_pair_1 (load_p, reg2, mem2);
18861 /* Return true if REG1 and REG2 match the criteria for a movep insn. */
18864 umips_movep_target_p (rtx reg1, rtx reg2)
18866 int regno1, regno2, pair;
18868 static const int match[8] = {
18869 0x00000060, /* 5, 6 */
18870 0x000000a0, /* 5, 7 */
18871 0x000000c0, /* 6, 7 */
18872 0x00200010, /* 4, 21 */
18873 0x00400010, /* 4, 22 */
18874 0x00000030, /* 4, 5 */
18875 0x00000050, /* 4, 6 */
18876 0x00000090 /* 4, 7 */
18879 if (!REG_P (reg1) || !REG_P (reg2))
18882 regno1 = REGNO (reg1);
18883 regno2 = REGNO (reg2);
18885 if (!GP_REG_P (regno1) || !GP_REG_P (regno2))
18888 pair = (1 << regno1) | (1 << regno2);
18890 for (i = 0; i < ARRAY_SIZE (match); i++)
18891 if (pair == match[i])
18897 /* Return the size in bytes of the trampoline code, padded to
18898 TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target
18899 function address immediately follow. */
18902 mips_trampoline_code_size (void)
18904 if (TARGET_USE_PIC_FN_ADDR_REG)
18906 else if (ptr_mode == DImode)
18908 else if (ISA_HAS_LOAD_DELAY)
18914 /* Implement TARGET_TRAMPOLINE_INIT. */
18917 mips_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
18919 rtx addr, end_addr, high, low, opcode, mem;
18922 HOST_WIDE_INT end_addr_offset, static_chain_offset, target_function_offset;
18924 /* Work out the offsets of the pointers from the start of the
18925 trampoline code. */
18926 end_addr_offset = mips_trampoline_code_size ();
18927 static_chain_offset = end_addr_offset;
18928 target_function_offset = static_chain_offset + GET_MODE_SIZE (ptr_mode);
18930 /* Get pointers to the beginning and end of the code block. */
18931 addr = force_reg (Pmode, XEXP (m_tramp, 0));
18932 end_addr = mips_force_binary (Pmode, PLUS, addr, GEN_INT (end_addr_offset));
18934 #define OP(X) gen_int_mode (X, SImode)
18936 /* Build up the code in TRAMPOLINE. */
18938 if (TARGET_USE_PIC_FN_ADDR_REG)
18940 /* $25 contains the address of the trampoline. Emit code of the form:
18942 l[wd] $1, target_function_offset($25)
18943 l[wd] $static_chain, static_chain_offset($25)
18946 trampoline[i++] = OP (MIPS_LOAD_PTR (AT_REGNUM,
18947 target_function_offset,
18948 PIC_FUNCTION_ADDR_REGNUM));
18949 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
18950 static_chain_offset,
18951 PIC_FUNCTION_ADDR_REGNUM));
18952 trampoline[i++] = OP (MIPS_JR (AT_REGNUM));
18953 trampoline[i++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM, AT_REGNUM));
18955 else if (ptr_mode == DImode)
18957 /* It's too cumbersome to create the full 64-bit address, so let's
18963 1: l[wd] $25, target_function_offset - 12($31)
18964 l[wd] $static_chain, static_chain_offset - 12($31)
18968 where 12 is the offset of "1:" from the start of the code block. */
18969 trampoline[i++] = OP (MIPS_MOVE (AT_REGNUM, RETURN_ADDR_REGNUM));
18970 trampoline[i++] = OP (MIPS_BAL (1));
18971 trampoline[i++] = OP (MIPS_NOP);
18972 trampoline[i++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
18973 target_function_offset - 12,
18974 RETURN_ADDR_REGNUM));
18975 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
18976 static_chain_offset - 12,
18977 RETURN_ADDR_REGNUM));
18978 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
18979 trampoline[i++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM, AT_REGNUM));
18983 /* If the target has load delays, emit:
18985 lui $1, %hi(end_addr)
18986 lw $25, %lo(end_addr + ...)($1)
18987 lw $static_chain, %lo(end_addr + ...)($1)
18993 lui $1, %hi(end_addr)
18994 lw $25, %lo(end_addr + ...)($1)
18996 lw $static_chain, %lo(end_addr + ...)($1). */
18998 /* Split END_ADDR into %hi and %lo values. Trampolines are aligned
18999 to 64 bits, so the %lo value will have the bottom 3 bits clear. */
19000 high = expand_simple_binop (SImode, PLUS, end_addr, GEN_INT (0x8000),
19001 NULL, false, OPTAB_WIDEN);
19002 high = expand_simple_binop (SImode, LSHIFTRT, high, GEN_INT (16),
19003 NULL, false, OPTAB_WIDEN);
19004 low = convert_to_mode (SImode, gen_lowpart (HImode, end_addr), true);
19006 /* Emit the LUI. */
19007 opcode = OP (MIPS_LUI (AT_REGNUM, 0));
19008 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, high,
19009 NULL, false, OPTAB_WIDEN);
19011 /* Emit the load of the target function. */
19012 opcode = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
19013 target_function_offset - end_addr_offset,
19015 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
19016 NULL, false, OPTAB_WIDEN);
19018 /* Emit the JR here, if we can. */
19019 if (!ISA_HAS_LOAD_DELAY)
19020 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
19022 /* Emit the load of the static chain register. */
19023 opcode = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
19024 static_chain_offset - end_addr_offset,
19026 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
19027 NULL, false, OPTAB_WIDEN);
19029 /* Emit the JR, if we couldn't above. */
19030 if (ISA_HAS_LOAD_DELAY)
19032 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
19033 trampoline[i++] = OP (MIPS_NOP);
19039 /* If we are using compact branches we don't have delay slots so
19040 place the instruction that was in the delay slot before the JRC
19043 if (TARGET_CB_ALWAYS)
19046 temp = trampoline[i-2];
19047 trampoline[i-2] = trampoline[i-1];
19048 trampoline[i-1] = temp;
19051 /* Copy the trampoline code. Leave any padding uninitialized. */
19052 for (j = 0; j < i; j++)
19054 mem = adjust_address (m_tramp, SImode, j * GET_MODE_SIZE (SImode));
19055 mips_emit_move (mem, trampoline[j]);
19058 /* Set up the static chain pointer field. */
19059 mem = adjust_address (m_tramp, ptr_mode, static_chain_offset);
19060 mips_emit_move (mem, chain_value);
19062 /* Set up the target function field. */
19063 mem = adjust_address (m_tramp, ptr_mode, target_function_offset);
19064 mips_emit_move (mem, XEXP (DECL_RTL (fndecl), 0));
19066 /* Flush the code part of the trampoline. */
19067 emit_insn (gen_add3_insn (end_addr, addr, GEN_INT (TRAMPOLINE_SIZE)));
19068 emit_insn (gen_clear_cache (addr, end_addr));
19071 /* Implement FUNCTION_PROFILER. */
19073 void mips_function_profiler (FILE *file)
19076 sorry ("mips16 function profiling");
19077 if (TARGET_LONG_CALLS)
19079 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */
19080 if (Pmode == DImode)
19081 fprintf (file, "\tdla\t%s,_mcount\n", reg_names[3]);
19083 fprintf (file, "\tla\t%s,_mcount\n", reg_names[3]);
19085 mips_push_asm_switch (&mips_noat);
19086 fprintf (file, "\tmove\t%s,%s\t\t# save current return address\n",
19087 reg_names[AT_REGNUM], reg_names[RETURN_ADDR_REGNUM]);
19088 /* _mcount treats $2 as the static chain register. */
19089 if (cfun->static_chain_decl != NULL)
19090 fprintf (file, "\tmove\t%s,%s\n", reg_names[2],
19091 reg_names[STATIC_CHAIN_REGNUM]);
19092 if (TARGET_MCOUNT_RA_ADDRESS)
19094 /* If TARGET_MCOUNT_RA_ADDRESS load $12 with the address of the
19095 ra save location. */
19096 if (cfun->machine->frame.ra_fp_offset == 0)
19097 /* ra not saved, pass zero. */
19098 fprintf (file, "\tmove\t%s,%s\n", reg_names[12], reg_names[0]);
19100 fprintf (file, "\t%s\t%s," HOST_WIDE_INT_PRINT_DEC "(%s)\n",
19101 Pmode == DImode ? "dla" : "la", reg_names[12],
19102 cfun->machine->frame.ra_fp_offset,
19103 reg_names[STACK_POINTER_REGNUM]);
19105 if (!TARGET_NEWABI)
19107 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n",
19108 TARGET_64BIT ? "dsubu" : "subu",
19109 reg_names[STACK_POINTER_REGNUM],
19110 reg_names[STACK_POINTER_REGNUM],
19111 Pmode == DImode ? 16 : 8);
19113 if (TARGET_LONG_CALLS)
19114 fprintf (file, "\tjalr\t%s\n", reg_names[3]);
19116 fprintf (file, "\tjal\t_mcount\n");
19117 mips_pop_asm_switch (&mips_noat);
19118 /* _mcount treats $2 as the static chain register. */
19119 if (cfun->static_chain_decl != NULL)
19120 fprintf (file, "\tmove\t%s,%s\n", reg_names[STATIC_CHAIN_REGNUM],
19124 /* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default
19125 behavior of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even
19126 when TARGET_LOONGSON_VECTORS is true. */
19128 static unsigned HOST_WIDE_INT
19129 mips_shift_truncation_mask (machine_mode mode)
19131 if (TARGET_LOONGSON_VECTORS && VECTOR_MODE_P (mode))
19134 return GET_MODE_BITSIZE (mode) - 1;
19137 /* Implement TARGET_PREPARE_PCH_SAVE. */
19140 mips_prepare_pch_save (void)
19142 /* We are called in a context where the current MIPS16 vs. non-MIPS16
19143 setting should be irrelevant. The question then is: which setting
19144 makes most sense at load time?
19146 The PCH is loaded before the first token is read. We should never
19147 have switched into MIPS16 mode by that point, and thus should not
19148 have populated mips16_globals. Nor can we load the entire contents
19149 of mips16_globals from the PCH file, because mips16_globals contains
19150 a combination of GGC and non-GGC data.
19152 There is therefore no point in trying save the GGC part of
19153 mips16_globals to the PCH file, or to preserve MIPS16ness across
19154 the PCH save and load. The loading compiler would not have access
19155 to the non-GGC parts of mips16_globals (either from the PCH file,
19156 or from a copy that the loading compiler generated itself) and would
19157 have to call target_reinit anyway.
19159 It therefore seems best to switch back to non-MIPS16 mode at
19160 save time, and to ensure that mips16_globals remains null after
19162 mips_set_compression_mode (0);
19163 mips16_globals = 0;
19166 /* Generate or test for an insn that supports a constant permutation. */
19168 #define MAX_VECT_LEN 8
19170 struct expand_vec_perm_d
19172 rtx target, op0, op1;
19173 unsigned char perm[MAX_VECT_LEN];
19174 machine_mode vmode;
19175 unsigned char nelt;
19180 /* Construct (set target (vec_select op0 (parallel perm))) and
19181 return true if that's a valid instruction in the active ISA. */
19184 mips_expand_vselect (rtx target, rtx op0,
19185 const unsigned char *perm, unsigned nelt)
19187 rtx rperm[MAX_VECT_LEN], x;
19191 for (i = 0; i < nelt; ++i)
19192 rperm[i] = GEN_INT (perm[i]);
19194 x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (nelt, rperm));
19195 x = gen_rtx_VEC_SELECT (GET_MODE (target), op0, x);
19196 x = gen_rtx_SET (target, x);
19198 insn = emit_insn (x);
19199 if (recog_memoized (insn) < 0)
19201 remove_insn (insn);
19207 /* Similar, but generate a vec_concat from op0 and op1 as well. */
19210 mips_expand_vselect_vconcat (rtx target, rtx op0, rtx op1,
19211 const unsigned char *perm, unsigned nelt)
19213 machine_mode v2mode;
19216 v2mode = GET_MODE_2XWIDER_MODE (GET_MODE (op0));
19217 x = gen_rtx_VEC_CONCAT (v2mode, op0, op1);
19218 return mips_expand_vselect (target, x, perm, nelt);
19221 /* Recognize patterns for even-odd extraction. */
19224 mips_expand_vpc_loongson_even_odd (struct expand_vec_perm_d *d)
19226 unsigned i, odd, nelt = d->nelt;
19227 rtx t0, t1, t2, t3;
19229 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
19231 /* Even-odd for V2SI/V2SFmode is matched by interleave directly. */
19238 for (i = 1; i < nelt; ++i)
19239 if (d->perm[i] != i * 2 + odd)
19245 /* We need 2*log2(N)-1 operations to achieve odd/even with interleave. */
19246 t0 = gen_reg_rtx (d->vmode);
19247 t1 = gen_reg_rtx (d->vmode);
19251 emit_insn (gen_loongson_punpckhhw (t0, d->op0, d->op1));
19252 emit_insn (gen_loongson_punpcklhw (t1, d->op0, d->op1));
19254 emit_insn (gen_loongson_punpckhhw (d->target, t1, t0));
19256 emit_insn (gen_loongson_punpcklhw (d->target, t1, t0));
19260 t2 = gen_reg_rtx (d->vmode);
19261 t3 = gen_reg_rtx (d->vmode);
19262 emit_insn (gen_loongson_punpckhbh (t0, d->op0, d->op1));
19263 emit_insn (gen_loongson_punpcklbh (t1, d->op0, d->op1));
19264 emit_insn (gen_loongson_punpckhbh (t2, t1, t0));
19265 emit_insn (gen_loongson_punpcklbh (t3, t1, t0));
19267 emit_insn (gen_loongson_punpckhbh (d->target, t3, t2));
19269 emit_insn (gen_loongson_punpcklbh (d->target, t3, t2));
19273 gcc_unreachable ();
19278 /* Recognize patterns for the Loongson PSHUFH instruction. */
19281 mips_expand_vpc_loongson_pshufh (struct expand_vec_perm_d *d)
19286 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
19288 if (d->vmode != V4HImode)
19293 /* Convert the selector into the packed 8-bit form for pshufh. */
19294 /* Recall that loongson is little-endian only. No big-endian
19295 adjustment required. */
19296 for (i = mask = 0; i < 4; i++)
19297 mask |= (d->perm[i] & 3) << (i * 2);
19298 rmask = force_reg (SImode, GEN_INT (mask));
19300 if (d->one_vector_p)
19301 emit_insn (gen_loongson_pshufh (d->target, d->op0, rmask));
19304 rtx t0, t1, x, merge, rmerge[4];
19306 t0 = gen_reg_rtx (V4HImode);
19307 t1 = gen_reg_rtx (V4HImode);
19308 emit_insn (gen_loongson_pshufh (t1, d->op1, rmask));
19309 emit_insn (gen_loongson_pshufh (t0, d->op0, rmask));
19311 for (i = 0; i < 4; ++i)
19312 rmerge[i] = (d->perm[i] & 4 ? constm1_rtx : const0_rtx);
19313 merge = gen_rtx_CONST_VECTOR (V4HImode, gen_rtvec_v (4, rmerge));
19314 merge = force_reg (V4HImode, merge);
19316 x = gen_rtx_AND (V4HImode, merge, t1);
19317 emit_insn (gen_rtx_SET (t1, x));
19319 x = gen_rtx_NOT (V4HImode, merge);
19320 x = gen_rtx_AND (V4HImode, x, t0);
19321 emit_insn (gen_rtx_SET (t0, x));
19323 x = gen_rtx_IOR (V4HImode, t0, t1);
19324 emit_insn (gen_rtx_SET (d->target, x));
19330 /* Recognize broadcast patterns for the Loongson. */
19333 mips_expand_vpc_loongson_bcast (struct expand_vec_perm_d *d)
19338 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
19340 /* Note that we've already matched V2SI via punpck and V4HI via pshufh. */
19341 if (d->vmode != V8QImode)
19343 if (!d->one_vector_p)
19347 for (i = 1; i < 8; ++i)
19348 if (d->perm[i] != elt)
19354 /* With one interleave we put two of the desired element adjacent. */
19355 t0 = gen_reg_rtx (V8QImode);
19357 emit_insn (gen_loongson_punpcklbh (t0, d->op0, d->op0));
19359 emit_insn (gen_loongson_punpckhbh (t0, d->op0, d->op0));
19361 /* Shuffle that one HImode element into all locations. */
19364 t1 = gen_reg_rtx (V4HImode);
19365 emit_insn (gen_loongson_pshufh (t1, gen_lowpart (V4HImode, t0),
19366 force_reg (SImode, GEN_INT (elt))));
19368 emit_move_insn (d->target, gen_lowpart (V8QImode, t1));
19373 mips_expand_vec_perm_const_1 (struct expand_vec_perm_d *d)
19375 unsigned int i, nelt = d->nelt;
19376 unsigned char perm2[MAX_VECT_LEN];
19378 if (d->one_vector_p)
19380 /* Try interleave with alternating operands. */
19381 memcpy (perm2, d->perm, sizeof(perm2));
19382 for (i = 1; i < nelt; i += 2)
19384 if (mips_expand_vselect_vconcat (d->target, d->op0, d->op1, perm2, nelt))
19389 if (mips_expand_vselect_vconcat (d->target, d->op0, d->op1,
19393 /* Try again with swapped operands. */
19394 for (i = 0; i < nelt; ++i)
19395 perm2[i] = (d->perm[i] + nelt) & (2 * nelt - 1);
19396 if (mips_expand_vselect_vconcat (d->target, d->op1, d->op0, perm2, nelt))
19400 if (mips_expand_vpc_loongson_even_odd (d))
19402 if (mips_expand_vpc_loongson_pshufh (d))
19404 if (mips_expand_vpc_loongson_bcast (d))
19409 /* Expand a vec_perm_const pattern. */
19412 mips_expand_vec_perm_const (rtx operands[4])
19414 struct expand_vec_perm_d d;
19415 int i, nelt, which;
19416 unsigned char orig_perm[MAX_VECT_LEN];
19420 d.target = operands[0];
19421 d.op0 = operands[1];
19422 d.op1 = operands[2];
19425 d.vmode = GET_MODE (d.target);
19426 gcc_assert (VECTOR_MODE_P (d.vmode));
19427 d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
19428 d.testing_p = false;
19430 for (i = which = 0; i < nelt; ++i)
19432 rtx e = XVECEXP (sel, 0, i);
19433 int ei = INTVAL (e) & (2 * nelt - 1);
19434 which |= (ei < nelt ? 1 : 2);
19437 memcpy (d.perm, orig_perm, MAX_VECT_LEN);
19445 d.one_vector_p = false;
19446 if (!rtx_equal_p (d.op0, d.op1))
19451 for (i = 0; i < nelt; ++i)
19452 d.perm[i] &= nelt - 1;
19454 d.one_vector_p = true;
19459 d.one_vector_p = true;
19463 ok = mips_expand_vec_perm_const_1 (&d);
19465 /* If we were given a two-vector permutation which just happened to
19466 have both input vectors equal, we folded this into a one-vector
19467 permutation. There are several loongson patterns that are matched
19468 via direct vec_select+vec_concat expansion, but we do not have
19469 support in mips_expand_vec_perm_const_1 to guess the adjustment
19470 that should be made for a single operand. Just try again with
19471 the original permutation. */
19472 if (!ok && which == 3)
19474 d.op0 = operands[1];
19475 d.op1 = operands[2];
19476 d.one_vector_p = false;
19477 memcpy (d.perm, orig_perm, MAX_VECT_LEN);
19478 ok = mips_expand_vec_perm_const_1 (&d);
19484 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST_OK. */
19487 mips_vectorize_vec_perm_const_ok (machine_mode vmode,
19488 const unsigned char *sel)
19490 struct expand_vec_perm_d d;
19491 unsigned int i, nelt, which;
19495 d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
19496 d.testing_p = true;
19497 memcpy (d.perm, sel, nelt);
19499 /* Categorize the set of elements in the selector. */
19500 for (i = which = 0; i < nelt; ++i)
19502 unsigned char e = d.perm[i];
19503 gcc_assert (e < 2 * nelt);
19504 which |= (e < nelt ? 1 : 2);
19507 /* For all elements from second vector, fold the elements to first. */
19509 for (i = 0; i < nelt; ++i)
19512 /* Check whether the mask can be applied to the vector type. */
19513 d.one_vector_p = (which != 3);
19515 d.target = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 1);
19516 d.op1 = d.op0 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 2);
19517 if (!d.one_vector_p)
19518 d.op1 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 3);
19521 ret = mips_expand_vec_perm_const_1 (&d);
19527 /* Expand an integral vector unpack operation. */
19530 mips_expand_vec_unpack (rtx operands[2], bool unsigned_p, bool high_p)
19532 machine_mode imode = GET_MODE (operands[1]);
19533 rtx (*unpack) (rtx, rtx, rtx);
19534 rtx (*cmpgt) (rtx, rtx, rtx);
19535 rtx tmp, dest, zero;
19541 unpack = gen_loongson_punpckhbh;
19543 unpack = gen_loongson_punpcklbh;
19544 cmpgt = gen_loongson_pcmpgtb;
19548 unpack = gen_loongson_punpckhhw;
19550 unpack = gen_loongson_punpcklhw;
19551 cmpgt = gen_loongson_pcmpgth;
19554 gcc_unreachable ();
19557 zero = force_reg (imode, CONST0_RTX (imode));
19562 tmp = gen_reg_rtx (imode);
19563 emit_insn (cmpgt (tmp, zero, operands[1]));
19566 dest = gen_reg_rtx (imode);
19567 emit_insn (unpack (dest, operands[1], tmp));
19569 emit_move_insn (operands[0], gen_lowpart (GET_MODE (operands[0]), dest));
19572 /* A subroutine of mips_expand_vec_init, match constant vector elements. */
19575 mips_constant_elt_p (rtx x)
19577 return CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE;
19580 /* A subroutine of mips_expand_vec_init, expand via broadcast. */
19583 mips_expand_vi_broadcast (machine_mode vmode, rtx target, rtx elt)
19585 struct expand_vec_perm_d d;
19589 if (elt != const0_rtx)
19590 elt = force_reg (GET_MODE_INNER (vmode), elt);
19592 elt = gen_lowpart (DImode, elt);
19594 t1 = gen_reg_rtx (vmode);
19598 emit_insn (gen_loongson_vec_init1_v8qi (t1, elt));
19601 emit_insn (gen_loongson_vec_init1_v4hi (t1, elt));
19604 gcc_unreachable ();
19607 memset (&d, 0, sizeof (d));
19612 d.nelt = GET_MODE_NUNITS (vmode);
19613 d.one_vector_p = true;
19615 ok = mips_expand_vec_perm_const_1 (&d);
19619 /* A subroutine of mips_expand_vec_init, replacing all of the non-constant
19620 elements of VALS with zeros, copy the constant vector to TARGET. */
19623 mips_expand_vi_constant (machine_mode vmode, unsigned nelt,
19624 rtx target, rtx vals)
19626 rtvec vec = shallow_copy_rtvec (XVEC (vals, 0));
19629 for (i = 0; i < nelt; ++i)
19631 if (!mips_constant_elt_p (RTVEC_ELT (vec, i)))
19632 RTVEC_ELT (vec, i) = const0_rtx;
19635 emit_move_insn (target, gen_rtx_CONST_VECTOR (vmode, vec));
19639 /* A subroutine of mips_expand_vec_init, expand via pinsrh. */
19642 mips_expand_vi_loongson_one_pinsrh (rtx target, rtx vals, unsigned one_var)
19644 mips_expand_vi_constant (V4HImode, 4, target, vals);
19646 emit_insn (gen_vec_setv4hi (target, target, XVECEXP (vals, 0, one_var),
19647 GEN_INT (one_var)));
19650 /* A subroutine of mips_expand_vec_init, expand anything via memory. */
19653 mips_expand_vi_general (machine_mode vmode, machine_mode imode,
19654 unsigned nelt, unsigned nvar, rtx target, rtx vals)
19656 rtx mem = assign_stack_temp (vmode, GET_MODE_SIZE (vmode));
19657 unsigned int i, isize = GET_MODE_SIZE (imode);
19660 mips_expand_vi_constant (vmode, nelt, mem, vals);
19662 for (i = 0; i < nelt; ++i)
19664 rtx x = XVECEXP (vals, 0, i);
19665 if (!mips_constant_elt_p (x))
19666 emit_move_insn (adjust_address (mem, imode, i * isize), x);
19669 emit_move_insn (target, mem);
19672 /* Expand a vector initialization. */
19675 mips_expand_vector_init (rtx target, rtx vals)
19677 machine_mode vmode = GET_MODE (target);
19678 machine_mode imode = GET_MODE_INNER (vmode);
19679 unsigned i, nelt = GET_MODE_NUNITS (vmode);
19680 unsigned nvar = 0, one_var = -1u;
19681 bool all_same = true;
19684 for (i = 0; i < nelt; ++i)
19686 x = XVECEXP (vals, 0, i);
19687 if (!mips_constant_elt_p (x))
19688 nvar++, one_var = i;
19689 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
19693 /* Load constants from the pool, or whatever's handy. */
19696 emit_move_insn (target, gen_rtx_CONST_VECTOR (vmode, XVEC (vals, 0)));
19700 /* For two-part initialization, always use CONCAT. */
19703 rtx op0 = force_reg (imode, XVECEXP (vals, 0, 0));
19704 rtx op1 = force_reg (imode, XVECEXP (vals, 0, 1));
19705 x = gen_rtx_VEC_CONCAT (vmode, op0, op1);
19706 emit_insn (gen_rtx_SET (target, x));
19710 /* Loongson is the only cpu with vectors with more elements. */
19711 gcc_assert (TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS);
19713 /* If all values are identical, broadcast the value. */
19716 mips_expand_vi_broadcast (vmode, target, XVECEXP (vals, 0, 0));
19720 /* If we've only got one non-variable V4HImode, use PINSRH. */
19721 if (nvar == 1 && vmode == V4HImode)
19723 mips_expand_vi_loongson_one_pinsrh (target, vals, one_var);
19727 mips_expand_vi_general (vmode, imode, nelt, nvar, target, vals);
19730 /* Expand a vector reduction. */
19733 mips_expand_vec_reduc (rtx target, rtx in, rtx (*gen)(rtx, rtx, rtx))
19735 machine_mode vmode = GET_MODE (in);
19736 unsigned char perm2[2];
19737 rtx last, next, fold, x;
19741 fold = gen_reg_rtx (vmode);
19745 /* Use PUL/PLU to produce { L, H } op { H, L }.
19746 By reversing the pair order, rather than a pure interleave high,
19747 we avoid erroneous exceptional conditions that we might otherwise
19748 produce from the computation of H op H. */
19751 ok = mips_expand_vselect_vconcat (fold, last, last, perm2, 2);
19756 /* Use interleave to produce { H, L } op { H, H }. */
19757 emit_insn (gen_loongson_punpckhwd (fold, last, last));
19761 /* Perform the first reduction with interleave,
19762 and subsequent reductions with shifts. */
19763 emit_insn (gen_loongson_punpckhwd_hi (fold, last, last));
19765 next = gen_reg_rtx (vmode);
19766 emit_insn (gen (next, last, fold));
19769 fold = gen_reg_rtx (vmode);
19770 x = force_reg (SImode, GEN_INT (16));
19771 emit_insn (gen_vec_shr_v4hi (fold, last, x));
19775 emit_insn (gen_loongson_punpckhwd_qi (fold, last, last));
19777 next = gen_reg_rtx (vmode);
19778 emit_insn (gen (next, last, fold));
19781 fold = gen_reg_rtx (vmode);
19782 x = force_reg (SImode, GEN_INT (16));
19783 emit_insn (gen_vec_shr_v8qi (fold, last, x));
19785 next = gen_reg_rtx (vmode);
19786 emit_insn (gen (next, last, fold));
19789 fold = gen_reg_rtx (vmode);
19790 x = force_reg (SImode, GEN_INT (8));
19791 emit_insn (gen_vec_shr_v8qi (fold, last, x));
19795 gcc_unreachable ();
19798 emit_insn (gen (target, last, fold));
19801 /* Expand a vector minimum/maximum. */
19804 mips_expand_vec_minmax (rtx target, rtx op0, rtx op1,
19805 rtx (*cmp) (rtx, rtx, rtx), bool min_p)
19807 machine_mode vmode = GET_MODE (target);
19810 tc = gen_reg_rtx (vmode);
19811 t0 = gen_reg_rtx (vmode);
19812 t1 = gen_reg_rtx (vmode);
19815 emit_insn (cmp (tc, op0, op1));
19817 x = gen_rtx_AND (vmode, tc, (min_p ? op1 : op0));
19818 emit_insn (gen_rtx_SET (t0, x));
19820 x = gen_rtx_NOT (vmode, tc);
19821 x = gen_rtx_AND (vmode, x, (min_p ? op0 : op1));
19822 emit_insn (gen_rtx_SET (t1, x));
19824 x = gen_rtx_IOR (vmode, t0, t1);
19825 emit_insn (gen_rtx_SET (target, x));
19828 /* Implement HARD_REGNO_CALLER_SAVE_MODE. */
19831 mips_hard_regno_caller_save_mode (unsigned int regno,
19832 unsigned int nregs,
19835 /* For performance, avoid saving/restoring upper parts of a register
19836 by returning MODE as save mode when the mode is known. */
19837 if (mode == VOIDmode)
19838 return choose_hard_reg_mode (regno, nregs, false);
19843 /* Implement TARGET_CASE_VALUES_THRESHOLD. */
19846 mips_case_values_threshold (void)
19848 /* In MIPS16 mode using a larger case threshold generates smaller code. */
19849 if (TARGET_MIPS16 && optimize_size)
19852 return default_case_values_threshold ();
19855 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
19858 mips_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
19860 if (!TARGET_HARD_FLOAT_ABI)
19862 tree exceptions_var = create_tmp_var (MIPS_ATYPE_USI);
19863 tree fcsr_orig_var = create_tmp_var (MIPS_ATYPE_USI);
19864 tree fcsr_mod_var = create_tmp_var (MIPS_ATYPE_USI);
19865 tree get_fcsr = mips_builtin_decls[MIPS_GET_FCSR];
19866 tree set_fcsr = mips_builtin_decls[MIPS_SET_FCSR];
19867 tree get_fcsr_hold_call = build_call_expr (get_fcsr, 0);
19868 tree hold_assign_orig = build2 (MODIFY_EXPR, MIPS_ATYPE_USI,
19869 fcsr_orig_var, get_fcsr_hold_call);
19870 tree hold_mod_val = build2 (BIT_AND_EXPR, MIPS_ATYPE_USI, fcsr_orig_var,
19871 build_int_cst (MIPS_ATYPE_USI, 0xfffff003));
19872 tree hold_assign_mod = build2 (MODIFY_EXPR, MIPS_ATYPE_USI,
19873 fcsr_mod_var, hold_mod_val);
19874 tree set_fcsr_hold_call = build_call_expr (set_fcsr, 1, fcsr_mod_var);
19875 tree hold_all = build2 (COMPOUND_EXPR, MIPS_ATYPE_USI,
19876 hold_assign_orig, hold_assign_mod);
19877 *hold = build2 (COMPOUND_EXPR, void_type_node, hold_all,
19878 set_fcsr_hold_call);
19880 *clear = build_call_expr (set_fcsr, 1, fcsr_mod_var);
19882 tree get_fcsr_update_call = build_call_expr (get_fcsr, 0);
19883 *update = build2 (MODIFY_EXPR, MIPS_ATYPE_USI,
19884 exceptions_var, get_fcsr_update_call);
19885 tree set_fcsr_update_call = build_call_expr (set_fcsr, 1, fcsr_orig_var);
19886 *update = build2 (COMPOUND_EXPR, void_type_node, *update,
19887 set_fcsr_update_call);
19888 tree atomic_feraiseexcept
19889 = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT);
19890 tree int_exceptions_var = fold_convert (integer_type_node,
19892 tree atomic_feraiseexcept_call = build_call_expr (atomic_feraiseexcept,
19893 1, int_exceptions_var);
19894 *update = build2 (COMPOUND_EXPR, void_type_node, *update,
19895 atomic_feraiseexcept_call);
19898 /* Implement TARGET_SPILL_CLASS. */
19901 mips_spill_class (reg_class_t rclass ATTRIBUTE_UNUSED,
19902 machine_mode mode ATTRIBUTE_UNUSED)
19909 /* Implement TARGET_LRA_P. */
19914 return mips_lra_flag;
19917 /* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS. */
19920 mips_ira_change_pseudo_allocno_class (int regno, reg_class_t allocno_class,
19921 reg_class_t best_class ATTRIBUTE_UNUSED)
19923 /* LRA will allocate an FPR for an integer mode pseudo instead of spilling
19924 to memory if an FPR is present in the allocno class. It is rare that
19925 we actually need to place an integer mode value in an FPR so where
19926 possible limit the allocation to GR_REGS. This will slightly pessimize
19927 code that involves integer to/from float conversions as these will have
19928 to reload into FPRs in LRA. Such reloads are sometimes eliminated and
19929 sometimes only partially eliminated. We choose to take this penalty
19930 in order to eliminate usage of FPRs in code that does not use floating
19933 This change has a similar effect to increasing the cost of FPR->GPR
19934 register moves for integer modes so that they are higher than the cost
19935 of memory but changing the allocno class is more reliable.
19937 This is also similar to forbidding integer mode values in FPRs entirely
19938 but this would lead to an inconsistency in the integer to/from float
19939 instructions that say integer mode values must be placed in FPRs. */
19940 if (INTEGRAL_MODE_P (PSEUDO_REGNO_MODE (regno)) && allocno_class == ALL_REGS)
19942 return allocno_class;
19945 /* Implement TARGET_PROMOTE_FUNCTION_MODE */
19947 /* This function is equivalent to default_promote_function_mode_always_promote
19948 except that it returns a promoted mode even if type is NULL_TREE. This is
19949 needed by libcalls which have no type (only a mode) such as fixed conversion
19950 routines that take a signed or unsigned char/short argument and convert it
19951 to a fixed type. */
19953 static machine_mode
19954 mips_promote_function_mode (const_tree type ATTRIBUTE_UNUSED,
19956 int *punsignedp ATTRIBUTE_UNUSED,
19957 const_tree fntype ATTRIBUTE_UNUSED,
19958 int for_return ATTRIBUTE_UNUSED)
19962 if (type != NULL_TREE)
19963 return promote_mode (type, mode, punsignedp);
19965 unsignedp = *punsignedp;
19966 PROMOTE_MODE (mode, unsignedp, type);
19967 *punsignedp = unsignedp;
19971 /* Initialize the GCC target structure. */
19972 #undef TARGET_ASM_ALIGNED_HI_OP
19973 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
19974 #undef TARGET_ASM_ALIGNED_SI_OP
19975 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
19976 #undef TARGET_ASM_ALIGNED_DI_OP
19977 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
19979 #undef TARGET_OPTION_OVERRIDE
19980 #define TARGET_OPTION_OVERRIDE mips_option_override
19982 #undef TARGET_LEGITIMIZE_ADDRESS
19983 #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
19985 #undef TARGET_ASM_FUNCTION_PROLOGUE
19986 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
19987 #undef TARGET_ASM_FUNCTION_EPILOGUE
19988 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
19989 #undef TARGET_ASM_SELECT_RTX_SECTION
19990 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
19991 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
19992 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
19994 #undef TARGET_SCHED_INIT
19995 #define TARGET_SCHED_INIT mips_sched_init
19996 #undef TARGET_SCHED_REORDER
19997 #define TARGET_SCHED_REORDER mips_sched_reorder
19998 #undef TARGET_SCHED_REORDER2
19999 #define TARGET_SCHED_REORDER2 mips_sched_reorder2
20000 #undef TARGET_SCHED_VARIABLE_ISSUE
20001 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
20002 #undef TARGET_SCHED_ADJUST_COST
20003 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
20004 #undef TARGET_SCHED_ISSUE_RATE
20005 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
20006 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
20007 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
20008 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
20009 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
20010 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
20011 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
20012 mips_multipass_dfa_lookahead
20013 #undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
20014 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
20015 mips_small_register_classes_for_mode_p
20017 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
20018 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
20020 #undef TARGET_INSERT_ATTRIBUTES
20021 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
20022 #undef TARGET_MERGE_DECL_ATTRIBUTES
20023 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
20024 #undef TARGET_CAN_INLINE_P
20025 #define TARGET_CAN_INLINE_P mips_can_inline_p
20026 #undef TARGET_SET_CURRENT_FUNCTION
20027 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
20029 #undef TARGET_VALID_POINTER_MODE
20030 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
20031 #undef TARGET_REGISTER_MOVE_COST
20032 #define TARGET_REGISTER_MOVE_COST mips_register_move_cost
20033 #undef TARGET_REGISTER_PRIORITY
20034 #define TARGET_REGISTER_PRIORITY mips_register_priority
20035 #undef TARGET_MEMORY_MOVE_COST
20036 #define TARGET_MEMORY_MOVE_COST mips_memory_move_cost
20037 #undef TARGET_RTX_COSTS
20038 #define TARGET_RTX_COSTS mips_rtx_costs
20039 #undef TARGET_ADDRESS_COST
20040 #define TARGET_ADDRESS_COST mips_address_cost
20042 #undef TARGET_NO_SPECULATION_IN_DELAY_SLOTS_P
20043 #define TARGET_NO_SPECULATION_IN_DELAY_SLOTS_P mips_no_speculation_in_delay_slots_p
20045 #undef TARGET_IN_SMALL_DATA_P
20046 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
20048 #undef TARGET_MACHINE_DEPENDENT_REORG
20049 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
20051 #undef TARGET_PREFERRED_RELOAD_CLASS
20052 #define TARGET_PREFERRED_RELOAD_CLASS mips_preferred_reload_class
20054 #undef TARGET_EXPAND_TO_RTL_HOOK
20055 #define TARGET_EXPAND_TO_RTL_HOOK mips_expand_to_rtl_hook
20056 #undef TARGET_ASM_FILE_START
20057 #define TARGET_ASM_FILE_START mips_file_start
20058 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
20059 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
20060 #undef TARGET_ASM_CODE_END
20061 #define TARGET_ASM_CODE_END mips_code_end
20063 #undef TARGET_INIT_LIBFUNCS
20064 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
20066 #undef TARGET_BUILD_BUILTIN_VA_LIST
20067 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
20068 #undef TARGET_EXPAND_BUILTIN_VA_START
20069 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
20070 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
20071 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
20073 #undef TARGET_PROMOTE_FUNCTION_MODE
20074 #define TARGET_PROMOTE_FUNCTION_MODE mips_promote_function_mode
20075 #undef TARGET_FUNCTION_VALUE
20076 #define TARGET_FUNCTION_VALUE mips_function_value
20077 #undef TARGET_LIBCALL_VALUE
20078 #define TARGET_LIBCALL_VALUE mips_libcall_value
20079 #undef TARGET_FUNCTION_VALUE_REGNO_P
20080 #define TARGET_FUNCTION_VALUE_REGNO_P mips_function_value_regno_p
20081 #undef TARGET_RETURN_IN_MEMORY
20082 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
20083 #undef TARGET_RETURN_IN_MSB
20084 #define TARGET_RETURN_IN_MSB mips_return_in_msb
20086 #undef TARGET_ASM_OUTPUT_MI_THUNK
20087 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
20088 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
20089 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
20091 #undef TARGET_PRINT_OPERAND
20092 #define TARGET_PRINT_OPERAND mips_print_operand
20093 #undef TARGET_PRINT_OPERAND_ADDRESS
20094 #define TARGET_PRINT_OPERAND_ADDRESS mips_print_operand_address
20095 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
20096 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mips_print_operand_punct_valid_p
20098 #undef TARGET_SETUP_INCOMING_VARARGS
20099 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
20100 #undef TARGET_STRICT_ARGUMENT_NAMING
20101 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
20102 #undef TARGET_MUST_PASS_IN_STACK
20103 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
20104 #undef TARGET_PASS_BY_REFERENCE
20105 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
20106 #undef TARGET_CALLEE_COPIES
20107 #define TARGET_CALLEE_COPIES mips_callee_copies
20108 #undef TARGET_ARG_PARTIAL_BYTES
20109 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
20110 #undef TARGET_FUNCTION_ARG
20111 #define TARGET_FUNCTION_ARG mips_function_arg
20112 #undef TARGET_FUNCTION_ARG_ADVANCE
20113 #define TARGET_FUNCTION_ARG_ADVANCE mips_function_arg_advance
20114 #undef TARGET_FUNCTION_ARG_BOUNDARY
20115 #define TARGET_FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
20116 #undef TARGET_GET_RAW_RESULT_MODE
20117 #define TARGET_GET_RAW_RESULT_MODE mips_get_reg_raw_mode
20118 #undef TARGET_GET_RAW_ARG_MODE
20119 #define TARGET_GET_RAW_ARG_MODE mips_get_reg_raw_mode
20121 #undef TARGET_MODE_REP_EXTENDED
20122 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
20124 #undef TARGET_VECTOR_MODE_SUPPORTED_P
20125 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
20127 #undef TARGET_SCALAR_MODE_SUPPORTED_P
20128 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
20130 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
20131 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE mips_preferred_simd_mode
20133 #undef TARGET_INIT_BUILTINS
20134 #define TARGET_INIT_BUILTINS mips_init_builtins
20135 #undef TARGET_BUILTIN_DECL
20136 #define TARGET_BUILTIN_DECL mips_builtin_decl
20137 #undef TARGET_EXPAND_BUILTIN
20138 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
20140 #undef TARGET_HAVE_TLS
20141 #define TARGET_HAVE_TLS HAVE_AS_TLS
20143 #undef TARGET_CANNOT_FORCE_CONST_MEM
20144 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
20146 #undef TARGET_LEGITIMATE_CONSTANT_P
20147 #define TARGET_LEGITIMATE_CONSTANT_P mips_legitimate_constant_p
20149 #undef TARGET_ENCODE_SECTION_INFO
20150 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
20152 #undef TARGET_ATTRIBUTE_TABLE
20153 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
20154 /* All our function attributes are related to how out-of-line copies should
20155 be compiled or called. They don't in themselves prevent inlining. */
20156 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
20157 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
20159 #undef TARGET_EXTRA_LIVE_ON_ENTRY
20160 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
20162 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
20163 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
20164 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
20165 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
20167 #undef TARGET_COMP_TYPE_ATTRIBUTES
20168 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
20170 #ifdef HAVE_AS_DTPRELWORD
20171 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
20172 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
20174 #undef TARGET_DWARF_REGISTER_SPAN
20175 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
20176 #undef TARGET_DWARF_FRAME_REG_MODE
20177 #define TARGET_DWARF_FRAME_REG_MODE mips_dwarf_frame_reg_mode
20179 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
20180 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
20182 #undef TARGET_LEGITIMATE_ADDRESS_P
20183 #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p
20185 #undef TARGET_FRAME_POINTER_REQUIRED
20186 #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required
20188 #undef TARGET_CAN_ELIMINATE
20189 #define TARGET_CAN_ELIMINATE mips_can_eliminate
20191 #undef TARGET_CONDITIONAL_REGISTER_USAGE
20192 #define TARGET_CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage
20194 #undef TARGET_TRAMPOLINE_INIT
20195 #define TARGET_TRAMPOLINE_INIT mips_trampoline_init
20197 #undef TARGET_ASM_OUTPUT_SOURCE_FILENAME
20198 #define TARGET_ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
20200 #undef TARGET_SHIFT_TRUNCATION_MASK
20201 #define TARGET_SHIFT_TRUNCATION_MASK mips_shift_truncation_mask
20203 #undef TARGET_PREPARE_PCH_SAVE
20204 #define TARGET_PREPARE_PCH_SAVE mips_prepare_pch_save
20206 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
20207 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK mips_vectorize_vec_perm_const_ok
20209 #undef TARGET_CASE_VALUES_THRESHOLD
20210 #define TARGET_CASE_VALUES_THRESHOLD mips_case_values_threshold
20212 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
20213 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV mips_atomic_assign_expand_fenv
20215 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
20216 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
20218 #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
20219 #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
20220 mips_use_by_pieces_infrastructure_p
20222 #undef TARGET_SPILL_CLASS
20223 #define TARGET_SPILL_CLASS mips_spill_class
20224 #undef TARGET_LRA_P
20225 #define TARGET_LRA_P mips_lra_p
20226 #undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
20227 #define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS mips_ira_change_pseudo_allocno_class
20229 #undef TARGET_HARD_REGNO_SCRATCH_OK
20230 #define TARGET_HARD_REGNO_SCRATCH_OK mips_hard_regno_scratch_ok
20232 struct gcc_target targetm = TARGET_INITIALIZER;
20234 #include "gt-mips.h"