1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
5 Free Software Foundation, Inc.
6 Contributed by A. Lichnewsky, lich@inria.inria.fr.
7 Changes by Michael Meissner, meissner@osf.org.
8 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
9 Brendan Eich, brendan@microunity.com.
11 This file is part of GCC.
13 GCC is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GCC is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GCC; see the file COPYING3. If not see
25 <http://www.gnu.org/licenses/>. */
29 #include "coretypes.h"
33 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
36 #include "insn-attr.h"
52 #include "target-def.h"
53 #include "integrate.h"
54 #include "langhooks.h"
55 #include "cfglayout.h"
56 #include "sched-int.h"
59 #include "diagnostic.h"
60 #include "target-globals.h"
63 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
64 #define UNSPEC_ADDRESS_P(X) \
65 (GET_CODE (X) == UNSPEC \
66 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
67 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
69 /* Extract the symbol or label from UNSPEC wrapper X. */
70 #define UNSPEC_ADDRESS(X) \
73 /* Extract the symbol type from UNSPEC wrapper X. */
74 #define UNSPEC_ADDRESS_TYPE(X) \
75 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
77 /* The maximum distance between the top of the stack frame and the
78 value $sp has when we save and restore registers.
80 The value for normal-mode code must be a SMALL_OPERAND and must
81 preserve the maximum stack alignment. We therefore use a value
82 of 0x7ff0 in this case.
84 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
85 up to 0x7f8 bytes and can usually save or restore all the registers
86 that we need to save or restore. (Note that we can only use these
87 instructions for o32, for which the stack alignment is 8 bytes.)
89 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
90 RESTORE are not available. We can then use unextended instructions
91 to save and restore registers, and to allocate and deallocate the top
93 #define MIPS_MAX_FIRST_STACK_STEP \
94 (!TARGET_MIPS16 ? 0x7ff0 \
95 : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
96 : TARGET_64BIT ? 0x100 : 0x400)
98 /* True if INSN is a mips.md pattern or asm statement. */
99 #define USEFUL_INSN_P(INSN) \
100 (NONDEBUG_INSN_P (INSN) \
101 && GET_CODE (PATTERN (INSN)) != USE \
102 && GET_CODE (PATTERN (INSN)) != CLOBBER \
103 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
104 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
106 /* If INSN is a delayed branch sequence, return the first instruction
107 in the sequence, otherwise return INSN itself. */
108 #define SEQ_BEGIN(INSN) \
109 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
110 ? XVECEXP (PATTERN (INSN), 0, 0) \
113 /* Likewise for the last instruction in a delayed branch sequence. */
114 #define SEQ_END(INSN) \
115 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
116 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
119 /* Execute the following loop body with SUBINSN set to each instruction
120 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
121 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
122 for ((SUBINSN) = SEQ_BEGIN (INSN); \
123 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
124 (SUBINSN) = NEXT_INSN (SUBINSN))
126 /* True if bit BIT is set in VALUE. */
127 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
129 /* Return the opcode for a ptr_mode load of the form:
131 l[wd] DEST, OFFSET(BASE). */
132 #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \
133 (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \
138 /* Return the opcode to move register SRC into register DEST. */
139 #define MIPS_MOVE(DEST, SRC) \
140 ((TARGET_64BIT ? 0x2d : 0x21) \
144 /* Return the opcode for:
147 #define MIPS_LUI(DEST, VALUE) \
148 ((0xf << 26) | ((DEST) << 16) | (VALUE))
150 /* Return the opcode to jump to register DEST. */
151 #define MIPS_JR(DEST) \
152 (((DEST) << 21) | 0x8)
154 /* Return the opcode for:
156 bal . + (1 + OFFSET) * 4. */
157 #define MIPS_BAL(OFFSET) \
158 ((0x1 << 26) | (0x11 << 16) | (OFFSET))
160 /* Return the usual opcode for a nop. */
163 /* Classifies an address.
166 A natural register + offset address. The register satisfies
167 mips_valid_base_register_p and the offset is a const_arith_operand.
170 A LO_SUM rtx. The first operand is a valid base register and
171 the second operand is a symbolic address.
174 A signed 16-bit constant address.
177 A constant symbolic address. */
178 enum mips_address_type {
185 /* Macros to create an enumeration identifier for a function prototype. */
186 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
187 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
188 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
189 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
191 /* Classifies the prototype of a built-in function. */
192 enum mips_function_type {
193 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
194 #include "config/mips/mips-ftypes.def"
195 #undef DEF_MIPS_FTYPE
199 /* Specifies how a built-in function should be converted into rtl. */
200 enum mips_builtin_type {
201 /* The function corresponds directly to an .md pattern. The return
202 value is mapped to operand 0 and the arguments are mapped to
203 operands 1 and above. */
206 /* The function corresponds directly to an .md pattern. There is no return
207 value and the arguments are mapped to operands 0 and above. */
208 MIPS_BUILTIN_DIRECT_NO_TARGET,
210 /* The function corresponds to a comparison instruction followed by
211 a mips_cond_move_tf_ps pattern. The first two arguments are the
212 values to compare and the second two arguments are the vector
213 operands for the movt.ps or movf.ps instruction (in assembly order). */
217 /* The function corresponds to a V2SF comparison instruction. Operand 0
218 of this instruction is the result of the comparison, which has mode
219 CCV2 or CCV4. The function arguments are mapped to operands 1 and
220 above. The function's return value is an SImode boolean that is
221 true under the following conditions:
223 MIPS_BUILTIN_CMP_ANY: one of the registers is true
224 MIPS_BUILTIN_CMP_ALL: all of the registers are true
225 MIPS_BUILTIN_CMP_LOWER: the first register is true
226 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
227 MIPS_BUILTIN_CMP_ANY,
228 MIPS_BUILTIN_CMP_ALL,
229 MIPS_BUILTIN_CMP_UPPER,
230 MIPS_BUILTIN_CMP_LOWER,
232 /* As above, but the instruction only sets a single $fcc register. */
233 MIPS_BUILTIN_CMP_SINGLE,
235 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
236 MIPS_BUILTIN_BPOSGE32
239 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
240 #define MIPS_FP_CONDITIONS(MACRO) \
258 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
259 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
260 enum mips_fp_condition {
261 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
264 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
265 #define STRINGIFY(X) #X
266 static const char *const mips_fp_conditions[] = {
267 MIPS_FP_CONDITIONS (STRINGIFY)
270 /* Information about a function's frame layout. */
271 struct GTY(()) mips_frame_info {
272 /* The size of the frame in bytes. */
273 HOST_WIDE_INT total_size;
275 /* The number of bytes allocated to variables. */
276 HOST_WIDE_INT var_size;
278 /* The number of bytes allocated to outgoing function arguments. */
279 HOST_WIDE_INT args_size;
281 /* The number of bytes allocated to the .cprestore slot, or 0 if there
283 HOST_WIDE_INT cprestore_size;
285 /* Bit X is set if the function saves or restores GPR X. */
288 /* Likewise FPR X. */
291 /* Likewise doubleword accumulator X ($acX). */
292 unsigned int acc_mask;
294 /* The number of GPRs, FPRs, doubleword accumulators and COP0
298 unsigned int num_acc;
299 unsigned int num_cop0_regs;
301 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
302 save slots from the top of the frame, or zero if no such slots are
304 HOST_WIDE_INT gp_save_offset;
305 HOST_WIDE_INT fp_save_offset;
306 HOST_WIDE_INT acc_save_offset;
307 HOST_WIDE_INT cop0_save_offset;
309 /* Likewise, but giving offsets from the bottom of the frame. */
310 HOST_WIDE_INT gp_sp_offset;
311 HOST_WIDE_INT fp_sp_offset;
312 HOST_WIDE_INT acc_sp_offset;
313 HOST_WIDE_INT cop0_sp_offset;
315 /* Similar, but the value passed to _mcount. */
316 HOST_WIDE_INT ra_fp_offset;
318 /* The offset of arg_pointer_rtx from the bottom of the frame. */
319 HOST_WIDE_INT arg_pointer_offset;
321 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
322 HOST_WIDE_INT hard_frame_pointer_offset;
325 struct GTY(()) machine_function {
326 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
327 rtx mips16_gp_pseudo_rtx;
329 /* The number of extra stack bytes taken up by register varargs.
330 This area is allocated by the callee at the very top of the frame. */
333 /* The current frame information, calculated by mips_compute_frame_info. */
334 struct mips_frame_info frame;
336 /* The register to use as the function's global pointer, or INVALID_REGNUM
337 if the function doesn't need one. */
338 unsigned int global_pointer;
340 /* How many instructions it takes to load a label into $AT, or 0 if
341 this property hasn't yet been calculated. */
342 unsigned int load_label_num_insns;
344 /* True if mips_adjust_insn_length should ignore an instruction's
346 bool ignore_hazard_length_p;
348 /* True if the whole function is suitable for .set noreorder and
350 bool all_noreorder_p;
352 /* True if the function has "inflexible" and "flexible" references
353 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
354 and mips_cfun_has_flexible_gp_ref_p for details. */
355 bool has_inflexible_gp_insn_p;
356 bool has_flexible_gp_insn_p;
358 /* True if the function's prologue must load the global pointer
359 value into pic_offset_table_rtx and store the same value in
360 the function's cprestore slot (if any). Even if this value
361 is currently false, we may decide to set it to true later;
362 see mips_must_initialize_gp_p () for details. */
363 bool must_initialize_gp_p;
365 /* True if the current function must restore $gp after any potential
366 clobber. This value is only meaningful during the first post-epilogue
367 split_insns pass; see mips_must_initialize_gp_p () for details. */
368 bool must_restore_gp_when_clobbered_p;
370 /* True if this is an interrupt handler. */
371 bool interrupt_handler_p;
373 /* True if this is an interrupt handler that uses shadow registers. */
374 bool use_shadow_register_set_p;
376 /* True if this is an interrupt handler that should keep interrupts
378 bool keep_interrupts_masked_p;
380 /* True if this is an interrupt handler that should use DERET
382 bool use_debug_exception_return_p;
385 /* Information about a single argument. */
386 struct mips_arg_info {
387 /* True if the argument is passed in a floating-point register, or
388 would have been if we hadn't run out of registers. */
391 /* The number of words passed in registers, rounded up. */
392 unsigned int reg_words;
394 /* For EABI, the offset of the first register from GP_ARG_FIRST or
395 FP_ARG_FIRST. For other ABIs, the offset of the first register from
396 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
397 comment for details).
399 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
401 unsigned int reg_offset;
403 /* The number of words that must be passed on the stack, rounded up. */
404 unsigned int stack_words;
406 /* The offset from the start of the stack overflow area of the argument's
407 first stack word. Only meaningful when STACK_WORDS is nonzero. */
408 unsigned int stack_offset;
411 /* Information about an address described by mips_address_type.
417 REG is the base register and OFFSET is the constant offset.
420 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
421 is the type of symbol it references.
424 SYMBOL_TYPE is the type of symbol that the address references. */
425 struct mips_address_info {
426 enum mips_address_type type;
429 enum mips_symbol_type symbol_type;
432 /* One stage in a constant building sequence. These sequences have
436 A = A CODE[1] VALUE[1]
437 A = A CODE[2] VALUE[2]
440 where A is an accumulator, each CODE[i] is a binary rtl operation
441 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
442 struct mips_integer_op {
444 unsigned HOST_WIDE_INT value;
447 /* The largest number of operations needed to load an integer constant.
448 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
449 When the lowest bit is clear, we can try, but reject a sequence with
450 an extra SLL at the end. */
451 #define MIPS_MAX_INTEGER_OPS 7
453 /* Information about a MIPS16e SAVE or RESTORE instruction. */
454 struct mips16e_save_restore_info {
455 /* The number of argument registers saved by a SAVE instruction.
456 0 for RESTORE instructions. */
459 /* Bit X is set if the instruction saves or restores GPR X. */
462 /* The total number of bytes to allocate. */
466 /* Costs of various operations on the different architectures. */
468 struct mips_rtx_cost_data
470 unsigned short fp_add;
471 unsigned short fp_mult_sf;
472 unsigned short fp_mult_df;
473 unsigned short fp_div_sf;
474 unsigned short fp_div_df;
475 unsigned short int_mult_si;
476 unsigned short int_mult_di;
477 unsigned short int_div_si;
478 unsigned short int_div_di;
479 unsigned short branch_cost;
480 unsigned short memory_latency;
483 /* Global variables for machine-dependent things. */
485 /* The -G setting, or the configuration's default small-data limit if
486 no -G option is given. */
487 static unsigned int mips_small_data_threshold;
489 /* The number of file directives written by mips_output_filename. */
490 int num_source_filenames;
492 /* The name that appeared in the last .file directive written by
493 mips_output_filename, or "" if mips_output_filename hasn't
494 written anything yet. */
495 const char *current_function_file = "";
497 /* A label counter used by PUT_SDB_BLOCK_START and PUT_SDB_BLOCK_END. */
500 /* Arrays that map GCC register numbers to debugger register numbers. */
501 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
502 int mips_dwarf_regno[FIRST_PSEUDO_REGISTER];
504 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
505 struct mips_asm_switch mips_noreorder = { "reorder", 0 };
506 struct mips_asm_switch mips_nomacro = { "macro", 0 };
507 struct mips_asm_switch mips_noat = { "at", 0 };
509 /* True if we're writing out a branch-likely instruction rather than a
511 static bool mips_branch_likely;
513 /* The current instruction-set architecture. */
514 enum processor mips_arch;
515 const struct mips_cpu_info *mips_arch_info;
517 /* The processor that we should tune the code for. */
518 enum processor mips_tune;
519 const struct mips_cpu_info *mips_tune_info;
521 /* The ISA level associated with mips_arch. */
524 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
525 static const struct mips_cpu_info *mips_isa_option_info;
527 /* Which cost information to use. */
528 static const struct mips_rtx_cost_data *mips_cost;
530 /* The ambient target flags, excluding MASK_MIPS16. */
531 static int mips_base_target_flags;
533 /* True if MIPS16 is the default mode. */
534 bool mips_base_mips16;
536 /* The ambient values of other global variables. */
537 static int mips_base_schedule_insns; /* flag_schedule_insns */
538 static int mips_base_reorder_blocks_and_partition; /* flag_reorder... */
539 static int mips_base_move_loop_invariants; /* flag_move_loop_invariants */
540 static int mips_base_align_loops; /* align_loops */
541 static int mips_base_align_jumps; /* align_jumps */
542 static int mips_base_align_functions; /* align_functions */
544 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
545 bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
547 /* Index C is true if character C is a valid PRINT_OPERAND punctation
549 static bool mips_print_operand_punct[256];
551 static GTY (()) int mips_output_filename_first_time = 1;
553 /* mips_split_p[X] is true if symbols of type X can be split by
554 mips_split_symbol. */
555 bool mips_split_p[NUM_SYMBOL_TYPES];
557 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
558 can be split by mips_split_symbol. */
559 bool mips_split_hi_p[NUM_SYMBOL_TYPES];
561 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
562 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
563 if they are matched by a special .md file pattern. */
564 static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
566 /* Likewise for HIGHs. */
567 static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
569 /* Target state for MIPS16. */
570 struct target_globals *mips16_globals;
572 /* Cached value of can_issue_more. This is cached in mips_variable_issue hook
573 and returned from mips_sched_reorder2. */
574 static int cached_can_issue_more;
576 /* Index R is the smallest register class that contains register R. */
577 const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = {
578 LEA_REGS, LEA_REGS, M16_REGS, V1_REG,
579 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
580 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
581 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
582 M16_REGS, M16_REGS, LEA_REGS, LEA_REGS,
583 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
584 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
585 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
586 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
587 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
588 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
589 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
590 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
591 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
592 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
593 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
594 MD0_REG, MD1_REG, NO_REGS, ST_REGS,
595 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
596 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
597 NO_REGS, FRAME_REGS, FRAME_REGS, NO_REGS,
598 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
599 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
600 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
601 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
602 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
603 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
604 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
605 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
606 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
607 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
608 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
609 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
610 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
611 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
612 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
613 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
614 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
615 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
616 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
617 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
618 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
619 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
620 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
621 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
622 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
623 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
624 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
627 /* The value of TARGET_ATTRIBUTE_TABLE. */
628 static const struct attribute_spec mips_attribute_table[] = {
629 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
631 { "long_call", 0, 0, false, true, true, NULL, false },
632 { "far", 0, 0, false, true, true, NULL, false },
633 { "near", 0, 0, false, true, true, NULL, false },
634 /* We would really like to treat "mips16" and "nomips16" as type
635 attributes, but GCC doesn't provide the hooks we need to support
636 the right conversion rules. As declaration attributes, they affect
637 code generation but don't carry other semantics. */
638 { "mips16", 0, 0, true, false, false, NULL, false },
639 { "nomips16", 0, 0, true, false, false, NULL, false },
640 /* Allow functions to be specified as interrupt handlers */
641 { "interrupt", 0, 0, false, true, true, NULL, false },
642 { "use_shadow_register_set", 0, 0, false, true, true, NULL, false },
643 { "keep_interrupts_masked", 0, 0, false, true, true, NULL, false },
644 { "use_debug_exception_return", 0, 0, false, true, true, NULL, false },
645 { NULL, 0, 0, false, false, false, NULL, false }
648 /* A table describing all the processors GCC knows about; see
649 mips-cpus.def for details. */
650 static const struct mips_cpu_info mips_cpu_info_table[] = {
651 #define MIPS_CPU(NAME, CPU, ISA, FLAGS) \
652 { NAME, CPU, ISA, FLAGS },
653 #include "mips-cpus.def"
657 /* Default costs. If these are used for a processor we should look
658 up the actual costs. */
659 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
660 COSTS_N_INSNS (7), /* fp_mult_sf */ \
661 COSTS_N_INSNS (8), /* fp_mult_df */ \
662 COSTS_N_INSNS (23), /* fp_div_sf */ \
663 COSTS_N_INSNS (36), /* fp_div_df */ \
664 COSTS_N_INSNS (10), /* int_mult_si */ \
665 COSTS_N_INSNS (10), /* int_mult_di */ \
666 COSTS_N_INSNS (69), /* int_div_si */ \
667 COSTS_N_INSNS (69), /* int_div_di */ \
668 2, /* branch_cost */ \
669 4 /* memory_latency */
671 /* Floating-point costs for processors without an FPU. Just assume that
672 all floating-point libcalls are very expensive. */
673 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
674 COSTS_N_INSNS (256), /* fp_mult_sf */ \
675 COSTS_N_INSNS (256), /* fp_mult_df */ \
676 COSTS_N_INSNS (256), /* fp_div_sf */ \
677 COSTS_N_INSNS (256) /* fp_div_df */
679 /* Costs to use when optimizing for size. */
680 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size = {
681 COSTS_N_INSNS (1), /* fp_add */
682 COSTS_N_INSNS (1), /* fp_mult_sf */
683 COSTS_N_INSNS (1), /* fp_mult_df */
684 COSTS_N_INSNS (1), /* fp_div_sf */
685 COSTS_N_INSNS (1), /* fp_div_df */
686 COSTS_N_INSNS (1), /* int_mult_si */
687 COSTS_N_INSNS (1), /* int_mult_di */
688 COSTS_N_INSNS (1), /* int_div_si */
689 COSTS_N_INSNS (1), /* int_div_di */
691 4 /* memory_latency */
694 /* Costs to use when optimizing for speed, indexed by processor. */
695 static const struct mips_rtx_cost_data
696 mips_rtx_cost_data[NUM_PROCESSOR_VALUES] = {
698 COSTS_N_INSNS (2), /* fp_add */
699 COSTS_N_INSNS (4), /* fp_mult_sf */
700 COSTS_N_INSNS (5), /* fp_mult_df */
701 COSTS_N_INSNS (12), /* fp_div_sf */
702 COSTS_N_INSNS (19), /* fp_div_df */
703 COSTS_N_INSNS (12), /* int_mult_si */
704 COSTS_N_INSNS (12), /* int_mult_di */
705 COSTS_N_INSNS (35), /* int_div_si */
706 COSTS_N_INSNS (35), /* int_div_di */
708 4 /* memory_latency */
712 COSTS_N_INSNS (6), /* int_mult_si */
713 COSTS_N_INSNS (6), /* int_mult_di */
714 COSTS_N_INSNS (36), /* int_div_si */
715 COSTS_N_INSNS (36), /* int_div_di */
717 4 /* memory_latency */
721 COSTS_N_INSNS (36), /* int_mult_si */
722 COSTS_N_INSNS (36), /* int_mult_di */
723 COSTS_N_INSNS (37), /* int_div_si */
724 COSTS_N_INSNS (37), /* int_div_di */
726 4 /* memory_latency */
730 COSTS_N_INSNS (4), /* int_mult_si */
731 COSTS_N_INSNS (11), /* int_mult_di */
732 COSTS_N_INSNS (36), /* int_div_si */
733 COSTS_N_INSNS (68), /* int_div_di */
735 4 /* memory_latency */
738 COSTS_N_INSNS (4), /* fp_add */
739 COSTS_N_INSNS (4), /* fp_mult_sf */
740 COSTS_N_INSNS (5), /* fp_mult_df */
741 COSTS_N_INSNS (17), /* fp_div_sf */
742 COSTS_N_INSNS (32), /* fp_div_df */
743 COSTS_N_INSNS (4), /* int_mult_si */
744 COSTS_N_INSNS (11), /* int_mult_di */
745 COSTS_N_INSNS (36), /* int_div_si */
746 COSTS_N_INSNS (68), /* int_div_di */
748 4 /* memory_latency */
751 COSTS_N_INSNS (4), /* fp_add */
752 COSTS_N_INSNS (4), /* fp_mult_sf */
753 COSTS_N_INSNS (5), /* fp_mult_df */
754 COSTS_N_INSNS (17), /* fp_div_sf */
755 COSTS_N_INSNS (32), /* fp_div_df */
756 COSTS_N_INSNS (4), /* int_mult_si */
757 COSTS_N_INSNS (7), /* int_mult_di */
758 COSTS_N_INSNS (42), /* int_div_si */
759 COSTS_N_INSNS (72), /* int_div_di */
761 4 /* memory_latency */
765 COSTS_N_INSNS (5), /* int_mult_si */
766 COSTS_N_INSNS (5), /* int_mult_di */
767 COSTS_N_INSNS (41), /* int_div_si */
768 COSTS_N_INSNS (41), /* int_div_di */
770 4 /* memory_latency */
773 COSTS_N_INSNS (8), /* fp_add */
774 COSTS_N_INSNS (8), /* fp_mult_sf */
775 COSTS_N_INSNS (10), /* fp_mult_df */
776 COSTS_N_INSNS (34), /* fp_div_sf */
777 COSTS_N_INSNS (64), /* fp_div_df */
778 COSTS_N_INSNS (5), /* int_mult_si */
779 COSTS_N_INSNS (5), /* int_mult_di */
780 COSTS_N_INSNS (41), /* int_div_si */
781 COSTS_N_INSNS (41), /* int_div_di */
783 4 /* memory_latency */
786 COSTS_N_INSNS (4), /* fp_add */
787 COSTS_N_INSNS (4), /* fp_mult_sf */
788 COSTS_N_INSNS (5), /* fp_mult_df */
789 COSTS_N_INSNS (17), /* fp_div_sf */
790 COSTS_N_INSNS (32), /* fp_div_df */
791 COSTS_N_INSNS (5), /* int_mult_si */
792 COSTS_N_INSNS (5), /* int_mult_di */
793 COSTS_N_INSNS (41), /* int_div_si */
794 COSTS_N_INSNS (41), /* int_div_di */
796 4 /* memory_latency */
800 COSTS_N_INSNS (5), /* int_mult_si */
801 COSTS_N_INSNS (5), /* int_mult_di */
802 COSTS_N_INSNS (41), /* int_div_si */
803 COSTS_N_INSNS (41), /* int_div_di */
805 4 /* memory_latency */
808 COSTS_N_INSNS (8), /* fp_add */
809 COSTS_N_INSNS (8), /* fp_mult_sf */
810 COSTS_N_INSNS (10), /* fp_mult_df */
811 COSTS_N_INSNS (34), /* fp_div_sf */
812 COSTS_N_INSNS (64), /* fp_div_df */
813 COSTS_N_INSNS (5), /* int_mult_si */
814 COSTS_N_INSNS (5), /* int_mult_di */
815 COSTS_N_INSNS (41), /* int_div_si */
816 COSTS_N_INSNS (41), /* int_div_di */
818 4 /* memory_latency */
821 COSTS_N_INSNS (4), /* fp_add */
822 COSTS_N_INSNS (4), /* fp_mult_sf */
823 COSTS_N_INSNS (5), /* fp_mult_df */
824 COSTS_N_INSNS (17), /* fp_div_sf */
825 COSTS_N_INSNS (32), /* fp_div_df */
826 COSTS_N_INSNS (5), /* int_mult_si */
827 COSTS_N_INSNS (5), /* int_mult_di */
828 COSTS_N_INSNS (41), /* int_div_si */
829 COSTS_N_INSNS (41), /* int_div_di */
831 4 /* memory_latency */
834 COSTS_N_INSNS (6), /* fp_add */
835 COSTS_N_INSNS (6), /* fp_mult_sf */
836 COSTS_N_INSNS (7), /* fp_mult_df */
837 COSTS_N_INSNS (25), /* fp_div_sf */
838 COSTS_N_INSNS (48), /* fp_div_df */
839 COSTS_N_INSNS (5), /* int_mult_si */
840 COSTS_N_INSNS (5), /* int_mult_di */
841 COSTS_N_INSNS (41), /* int_div_si */
842 COSTS_N_INSNS (41), /* int_div_di */
844 4 /* memory_latency */
861 COSTS_N_INSNS (5), /* int_mult_si */
862 COSTS_N_INSNS (5), /* int_mult_di */
863 COSTS_N_INSNS (72), /* int_div_si */
864 COSTS_N_INSNS (72), /* int_div_di */
866 4 /* memory_latency */
869 COSTS_N_INSNS (2), /* fp_add */
870 COSTS_N_INSNS (4), /* fp_mult_sf */
871 COSTS_N_INSNS (5), /* fp_mult_df */
872 COSTS_N_INSNS (12), /* fp_div_sf */
873 COSTS_N_INSNS (19), /* fp_div_df */
874 COSTS_N_INSNS (2), /* int_mult_si */
875 COSTS_N_INSNS (2), /* int_mult_di */
876 COSTS_N_INSNS (35), /* int_div_si */
877 COSTS_N_INSNS (35), /* int_div_di */
879 4 /* memory_latency */
882 COSTS_N_INSNS (3), /* fp_add */
883 COSTS_N_INSNS (5), /* fp_mult_sf */
884 COSTS_N_INSNS (6), /* fp_mult_df */
885 COSTS_N_INSNS (15), /* fp_div_sf */
886 COSTS_N_INSNS (16), /* fp_div_df */
887 COSTS_N_INSNS (17), /* int_mult_si */
888 COSTS_N_INSNS (17), /* int_mult_di */
889 COSTS_N_INSNS (38), /* int_div_si */
890 COSTS_N_INSNS (38), /* int_div_di */
892 6 /* memory_latency */
895 COSTS_N_INSNS (6), /* fp_add */
896 COSTS_N_INSNS (7), /* fp_mult_sf */
897 COSTS_N_INSNS (8), /* fp_mult_df */
898 COSTS_N_INSNS (23), /* fp_div_sf */
899 COSTS_N_INSNS (36), /* fp_div_df */
900 COSTS_N_INSNS (10), /* int_mult_si */
901 COSTS_N_INSNS (10), /* int_mult_di */
902 COSTS_N_INSNS (69), /* int_div_si */
903 COSTS_N_INSNS (69), /* int_div_di */
905 6 /* memory_latency */
917 /* The only costs that appear to be updated here are
918 integer multiplication. */
920 COSTS_N_INSNS (4), /* int_mult_si */
921 COSTS_N_INSNS (6), /* int_mult_di */
922 COSTS_N_INSNS (69), /* int_div_si */
923 COSTS_N_INSNS (69), /* int_div_di */
925 4 /* memory_latency */
937 COSTS_N_INSNS (6), /* fp_add */
938 COSTS_N_INSNS (4), /* fp_mult_sf */
939 COSTS_N_INSNS (5), /* fp_mult_df */
940 COSTS_N_INSNS (23), /* fp_div_sf */
941 COSTS_N_INSNS (36), /* fp_div_df */
942 COSTS_N_INSNS (5), /* int_mult_si */
943 COSTS_N_INSNS (5), /* int_mult_di */
944 COSTS_N_INSNS (36), /* int_div_si */
945 COSTS_N_INSNS (36), /* int_div_di */
947 4 /* memory_latency */
950 COSTS_N_INSNS (6), /* fp_add */
951 COSTS_N_INSNS (5), /* fp_mult_sf */
952 COSTS_N_INSNS (6), /* fp_mult_df */
953 COSTS_N_INSNS (30), /* fp_div_sf */
954 COSTS_N_INSNS (59), /* fp_div_df */
955 COSTS_N_INSNS (3), /* int_mult_si */
956 COSTS_N_INSNS (4), /* int_mult_di */
957 COSTS_N_INSNS (42), /* int_div_si */
958 COSTS_N_INSNS (74), /* int_div_di */
960 4 /* memory_latency */
963 COSTS_N_INSNS (6), /* fp_add */
964 COSTS_N_INSNS (5), /* fp_mult_sf */
965 COSTS_N_INSNS (6), /* fp_mult_df */
966 COSTS_N_INSNS (30), /* fp_div_sf */
967 COSTS_N_INSNS (59), /* fp_div_df */
968 COSTS_N_INSNS (5), /* int_mult_si */
969 COSTS_N_INSNS (9), /* int_mult_di */
970 COSTS_N_INSNS (42), /* int_div_si */
971 COSTS_N_INSNS (74), /* int_div_di */
973 4 /* memory_latency */
976 /* The only costs that are changed here are
977 integer multiplication. */
978 COSTS_N_INSNS (6), /* fp_add */
979 COSTS_N_INSNS (7), /* fp_mult_sf */
980 COSTS_N_INSNS (8), /* fp_mult_df */
981 COSTS_N_INSNS (23), /* fp_div_sf */
982 COSTS_N_INSNS (36), /* fp_div_df */
983 COSTS_N_INSNS (5), /* int_mult_si */
984 COSTS_N_INSNS (9), /* int_mult_di */
985 COSTS_N_INSNS (69), /* int_div_si */
986 COSTS_N_INSNS (69), /* int_div_di */
988 4 /* memory_latency */
994 /* The only costs that are changed here are
995 integer multiplication. */
996 COSTS_N_INSNS (6), /* fp_add */
997 COSTS_N_INSNS (7), /* fp_mult_sf */
998 COSTS_N_INSNS (8), /* fp_mult_df */
999 COSTS_N_INSNS (23), /* fp_div_sf */
1000 COSTS_N_INSNS (36), /* fp_div_df */
1001 COSTS_N_INSNS (3), /* int_mult_si */
1002 COSTS_N_INSNS (8), /* int_mult_di */
1003 COSTS_N_INSNS (69), /* int_div_si */
1004 COSTS_N_INSNS (69), /* int_div_di */
1005 1, /* branch_cost */
1006 4 /* memory_latency */
1009 COSTS_N_INSNS (2), /* fp_add */
1010 COSTS_N_INSNS (2), /* fp_mult_sf */
1011 COSTS_N_INSNS (2), /* fp_mult_df */
1012 COSTS_N_INSNS (12), /* fp_div_sf */
1013 COSTS_N_INSNS (19), /* fp_div_df */
1014 COSTS_N_INSNS (5), /* int_mult_si */
1015 COSTS_N_INSNS (9), /* int_mult_di */
1016 COSTS_N_INSNS (34), /* int_div_si */
1017 COSTS_N_INSNS (66), /* int_div_di */
1018 1, /* branch_cost */
1019 4 /* memory_latency */
1022 /* These costs are the same as the SB-1A below. */
1023 COSTS_N_INSNS (4), /* fp_add */
1024 COSTS_N_INSNS (4), /* fp_mult_sf */
1025 COSTS_N_INSNS (4), /* fp_mult_df */
1026 COSTS_N_INSNS (24), /* fp_div_sf */
1027 COSTS_N_INSNS (32), /* fp_div_df */
1028 COSTS_N_INSNS (3), /* int_mult_si */
1029 COSTS_N_INSNS (4), /* int_mult_di */
1030 COSTS_N_INSNS (36), /* int_div_si */
1031 COSTS_N_INSNS (68), /* int_div_di */
1032 1, /* branch_cost */
1033 4 /* memory_latency */
1036 /* These costs are the same as the SB-1 above. */
1037 COSTS_N_INSNS (4), /* fp_add */
1038 COSTS_N_INSNS (4), /* fp_mult_sf */
1039 COSTS_N_INSNS (4), /* fp_mult_df */
1040 COSTS_N_INSNS (24), /* fp_div_sf */
1041 COSTS_N_INSNS (32), /* fp_div_df */
1042 COSTS_N_INSNS (3), /* int_mult_si */
1043 COSTS_N_INSNS (4), /* int_mult_di */
1044 COSTS_N_INSNS (36), /* int_div_si */
1045 COSTS_N_INSNS (68), /* int_div_di */
1046 1, /* branch_cost */
1047 4 /* memory_latency */
1054 COSTS_N_INSNS (8), /* int_mult_si */
1055 COSTS_N_INSNS (8), /* int_mult_di */
1056 COSTS_N_INSNS (72), /* int_div_si */
1057 COSTS_N_INSNS (72), /* int_div_di */
1058 1, /* branch_cost */
1059 4 /* memory_latency */
1063 static rtx mips_find_pic_call_symbol (rtx, rtx, bool);
1064 static int mips_register_move_cost (enum machine_mode, reg_class_t,
1066 static unsigned int mips_function_arg_boundary (enum machine_mode, const_tree);
1068 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1069 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1070 struct GTY (()) mflip_mips16_entry {
1074 static GTY ((param_is (struct mflip_mips16_entry))) htab_t mflip_mips16_htab;
1076 /* Hash table callbacks for mflip_mips16_htab. */
1079 mflip_mips16_htab_hash (const void *entry)
1081 return htab_hash_string (((const struct mflip_mips16_entry *) entry)->name);
1085 mflip_mips16_htab_eq (const void *entry, const void *name)
1087 return strcmp (((const struct mflip_mips16_entry *) entry)->name,
1088 (const char *) name) == 0;
1091 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1092 mode, false if it should next add an attribute for the opposite mode. */
1093 static GTY(()) bool mips16_flipper;
1095 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1096 for -mflip-mips16. Return true if it should use "mips16" and false if
1097 it should use "nomips16". */
1100 mflip_mips16_use_mips16_p (tree decl)
1102 struct mflip_mips16_entry *entry;
1107 /* Use the opposite of the command-line setting for anonymous decls. */
1108 if (!DECL_NAME (decl))
1109 return !mips_base_mips16;
1111 if (!mflip_mips16_htab)
1112 mflip_mips16_htab = htab_create_ggc (37, mflip_mips16_htab_hash,
1113 mflip_mips16_htab_eq, NULL);
1115 name = IDENTIFIER_POINTER (DECL_NAME (decl));
1116 hash = htab_hash_string (name);
1117 slot = htab_find_slot_with_hash (mflip_mips16_htab, name, hash, INSERT);
1118 entry = (struct mflip_mips16_entry *) *slot;
1121 mips16_flipper = !mips16_flipper;
1122 entry = ggc_alloc_mflip_mips16_entry ();
1124 entry->mips16_p = mips16_flipper ? !mips_base_mips16 : mips_base_mips16;
1127 return entry->mips16_p;
1130 /* Predicates to test for presence of "near" and "far"/"long_call"
1131 attributes on the given TYPE. */
1134 mips_near_type_p (const_tree type)
1136 return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL;
1140 mips_far_type_p (const_tree type)
1142 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL
1143 || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL);
1146 /* Similar predicates for "mips16"/"nomips16" function attributes. */
1149 mips_mips16_decl_p (const_tree decl)
1151 return lookup_attribute ("mips16", DECL_ATTRIBUTES (decl)) != NULL;
1155 mips_nomips16_decl_p (const_tree decl)
1157 return lookup_attribute ("nomips16", DECL_ATTRIBUTES (decl)) != NULL;
1160 /* Check if the interrupt attribute is set for a function. */
1163 mips_interrupt_type_p (tree type)
1165 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type)) != NULL;
1168 /* Check if the attribute to use shadow register set is set for a function. */
1171 mips_use_shadow_register_set_p (tree type)
1173 return lookup_attribute ("use_shadow_register_set",
1174 TYPE_ATTRIBUTES (type)) != NULL;
1177 /* Check if the attribute to keep interrupts masked is set for a function. */
1180 mips_keep_interrupts_masked_p (tree type)
1182 return lookup_attribute ("keep_interrupts_masked",
1183 TYPE_ATTRIBUTES (type)) != NULL;
1186 /* Check if the attribute to use debug exception return is set for
1190 mips_use_debug_exception_return_p (tree type)
1192 return lookup_attribute ("use_debug_exception_return",
1193 TYPE_ATTRIBUTES (type)) != NULL;
1196 /* Return true if function DECL is a MIPS16 function. Return the ambient
1197 setting if DECL is null. */
1200 mips_use_mips16_mode_p (tree decl)
1204 /* Nested functions must use the same frame pointer as their
1205 parent and must therefore use the same ISA mode. */
1206 tree parent = decl_function_context (decl);
1209 if (mips_mips16_decl_p (decl))
1211 if (mips_nomips16_decl_p (decl))
1214 return mips_base_mips16;
1217 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1220 mips_comp_type_attributes (const_tree type1, const_tree type2)
1222 /* Disallow mixed near/far attributes. */
1223 if (mips_far_type_p (type1) && mips_near_type_p (type2))
1225 if (mips_near_type_p (type1) && mips_far_type_p (type2))
1230 /* Implement TARGET_INSERT_ATTRIBUTES. */
1233 mips_insert_attributes (tree decl, tree *attributes)
1236 bool mips16_p, nomips16_p;
1238 /* Check for "mips16" and "nomips16" attributes. */
1239 mips16_p = lookup_attribute ("mips16", *attributes) != NULL;
1240 nomips16_p = lookup_attribute ("nomips16", *attributes) != NULL;
1241 if (TREE_CODE (decl) != FUNCTION_DECL)
1244 error ("%qs attribute only applies to functions", "mips16");
1246 error ("%qs attribute only applies to functions", "nomips16");
1250 mips16_p |= mips_mips16_decl_p (decl);
1251 nomips16_p |= mips_nomips16_decl_p (decl);
1252 if (mips16_p || nomips16_p)
1254 /* DECL cannot be simultaneously "mips16" and "nomips16". */
1255 if (mips16_p && nomips16_p)
1256 error ("%qE cannot have both %<mips16%> and "
1257 "%<nomips16%> attributes",
1260 else if (TARGET_FLIP_MIPS16 && !DECL_ARTIFICIAL (decl))
1262 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1263 "mips16" attribute, arbitrarily pick one. We must pick the same
1264 setting for duplicate declarations of a function. */
1265 name = mflip_mips16_use_mips16_p (decl) ? "mips16" : "nomips16";
1266 *attributes = tree_cons (get_identifier (name), NULL, *attributes);
1271 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1274 mips_merge_decl_attributes (tree olddecl, tree newdecl)
1276 /* The decls' "mips16" and "nomips16" attributes must match exactly. */
1277 if (mips_mips16_decl_p (olddecl) != mips_mips16_decl_p (newdecl))
1278 error ("%qE redeclared with conflicting %qs attributes",
1279 DECL_NAME (newdecl), "mips16");
1280 if (mips_nomips16_decl_p (olddecl) != mips_nomips16_decl_p (newdecl))
1281 error ("%qE redeclared with conflicting %qs attributes",
1282 DECL_NAME (newdecl), "nomips16");
1284 return merge_attributes (DECL_ATTRIBUTES (olddecl),
1285 DECL_ATTRIBUTES (newdecl));
1288 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1289 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1292 mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr)
1294 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
1296 *base_ptr = XEXP (x, 0);
1297 *offset_ptr = INTVAL (XEXP (x, 1));
1306 static unsigned int mips_build_integer (struct mips_integer_op *,
1307 unsigned HOST_WIDE_INT);
1309 /* A subroutine of mips_build_integer, with the same interface.
1310 Assume that the final action in the sequence should be a left shift. */
1313 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1315 unsigned int i, shift;
1317 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1318 since signed numbers are easier to load than unsigned ones. */
1320 while ((value & 1) == 0)
1321 value /= 2, shift++;
1323 i = mips_build_integer (codes, value);
1324 codes[i].code = ASHIFT;
1325 codes[i].value = shift;
1329 /* As for mips_build_shift, but assume that the final action will be
1330 an IOR or PLUS operation. */
1333 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1335 unsigned HOST_WIDE_INT high;
1338 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1339 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
1341 /* The constant is too complex to load with a simple LUI/ORI pair,
1342 so we want to give the recursive call as many trailing zeros as
1343 possible. In this case, we know bit 16 is set and that the
1344 low 16 bits form a negative number. If we subtract that number
1345 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1346 i = mips_build_integer (codes, CONST_HIGH_PART (value));
1347 codes[i].code = PLUS;
1348 codes[i].value = CONST_LOW_PART (value);
1352 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1353 bits gives a value with at least 17 trailing zeros. */
1354 i = mips_build_integer (codes, high);
1355 codes[i].code = IOR;
1356 codes[i].value = value & 0xffff;
1361 /* Fill CODES with a sequence of rtl operations to load VALUE.
1362 Return the number of operations needed. */
1365 mips_build_integer (struct mips_integer_op *codes,
1366 unsigned HOST_WIDE_INT value)
1368 if (SMALL_OPERAND (value)
1369 || SMALL_OPERAND_UNSIGNED (value)
1370 || LUI_OPERAND (value))
1372 /* The value can be loaded with a single instruction. */
1373 codes[0].code = UNKNOWN;
1374 codes[0].value = value;
1377 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
1379 /* Either the constant is a simple LUI/ORI combination or its
1380 lowest bit is set. We don't want to shift in this case. */
1381 return mips_build_lower (codes, value);
1383 else if ((value & 0xffff) == 0)
1385 /* The constant will need at least three actions. The lowest
1386 16 bits are clear, so the final action will be a shift. */
1387 return mips_build_shift (codes, value);
1391 /* The final action could be a shift, add or inclusive OR.
1392 Rather than use a complex condition to select the best
1393 approach, try both mips_build_shift and mips_build_lower
1394 and pick the one that gives the shortest sequence.
1395 Note that this case is only used once per constant. */
1396 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1397 unsigned int cost, alt_cost;
1399 cost = mips_build_shift (codes, value);
1400 alt_cost = mips_build_lower (alt_codes, value);
1401 if (alt_cost < cost)
1403 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
1410 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
1413 mips_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
1415 return mips_const_insns (x) > 0;
1418 /* Return true if symbols of type TYPE require a GOT access. */
1421 mips_got_symbol_type_p (enum mips_symbol_type type)
1425 case SYMBOL_GOT_PAGE_OFST:
1426 case SYMBOL_GOT_DISP:
1434 /* Return true if X is a thread-local symbol. */
1437 mips_tls_symbol_p (rtx x)
1439 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1442 /* Return true if SYMBOL_REF X is associated with a global symbol
1443 (in the STB_GLOBAL sense). */
1446 mips_global_symbol_p (const_rtx x)
1448 const_tree decl = SYMBOL_REF_DECL (x);
1451 return !SYMBOL_REF_LOCAL_P (x) || SYMBOL_REF_EXTERNAL_P (x);
1453 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1454 or weak symbols. Relocations in the object file will be against
1455 the target symbol, so it's that symbol's binding that matters here. */
1456 return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl));
1459 /* Return true if function X is a libgcc MIPS16 stub function. */
1462 mips16_stub_function_p (const_rtx x)
1464 return (GET_CODE (x) == SYMBOL_REF
1465 && strncmp (XSTR (x, 0), "__mips16_", 9) == 0);
1468 /* Return true if function X is a locally-defined and locally-binding
1472 mips16_local_function_p (const_rtx x)
1474 return (GET_CODE (x) == SYMBOL_REF
1475 && SYMBOL_REF_LOCAL_P (x)
1476 && !SYMBOL_REF_EXTERNAL_P (x)
1477 && mips_use_mips16_mode_p (SYMBOL_REF_DECL (x)));
1480 /* Return true if SYMBOL_REF X binds locally. */
1483 mips_symbol_binds_local_p (const_rtx x)
1485 return (SYMBOL_REF_DECL (x)
1486 ? targetm.binds_local_p (SYMBOL_REF_DECL (x))
1487 : SYMBOL_REF_LOCAL_P (x));
1490 /* Return true if rtx constants of mode MODE should be put into a small
1494 mips_rtx_constant_in_small_data_p (enum machine_mode mode)
1496 return (!TARGET_EMBEDDED_DATA
1497 && TARGET_LOCAL_SDATA
1498 && GET_MODE_SIZE (mode) <= mips_small_data_threshold);
1501 /* Return true if X should not be moved directly into register $25.
1502 We need this because many versions of GAS will treat "la $25,foo" as
1503 part of a call sequence and so allow a global "foo" to be lazily bound. */
1506 mips_dangerous_for_la25_p (rtx x)
1508 return (!TARGET_EXPLICIT_RELOCS
1510 && GET_CODE (x) == SYMBOL_REF
1511 && mips_global_symbol_p (x));
1514 /* Return true if calls to X might need $25 to be valid on entry. */
1517 mips_use_pic_fn_addr_reg_p (const_rtx x)
1519 if (!TARGET_USE_PIC_FN_ADDR_REG)
1522 /* MIPS16 stub functions are guaranteed not to use $25. */
1523 if (mips16_stub_function_p (x))
1526 if (GET_CODE (x) == SYMBOL_REF)
1528 /* If PLTs and copy relocations are available, the static linker
1529 will make sure that $25 is valid on entry to the target function. */
1530 if (TARGET_ABICALLS_PIC0)
1533 /* Locally-defined functions use absolute accesses to set up
1534 the global pointer. */
1535 if (TARGET_ABSOLUTE_ABICALLS
1536 && mips_symbol_binds_local_p (x)
1537 && !SYMBOL_REF_EXTERNAL_P (x))
1544 /* Return the method that should be used to access SYMBOL_REF or
1545 LABEL_REF X in context CONTEXT. */
1547 static enum mips_symbol_type
1548 mips_classify_symbol (const_rtx x, enum mips_symbol_context context)
1551 return SYMBOL_GOT_DISP;
1553 if (GET_CODE (x) == LABEL_REF)
1555 /* Only return SYMBOL_PC_RELATIVE if we are generating MIPS16
1556 code and if we know that the label is in the current function's
1557 text section. LABEL_REFs are used for jump tables as well as
1558 text labels, so we must check whether jump tables live in the
1560 if (TARGET_MIPS16_SHORT_JUMP_TABLES
1561 && !LABEL_REF_NONLOCAL_P (x))
1562 return SYMBOL_PC_RELATIVE;
1564 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1565 return SYMBOL_GOT_PAGE_OFST;
1567 return SYMBOL_ABSOLUTE;
1570 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1572 if (SYMBOL_REF_TLS_MODEL (x))
1575 if (CONSTANT_POOL_ADDRESS_P (x))
1577 if (TARGET_MIPS16_TEXT_LOADS)
1578 return SYMBOL_PC_RELATIVE;
1580 if (TARGET_MIPS16_PCREL_LOADS && context == SYMBOL_CONTEXT_MEM)
1581 return SYMBOL_PC_RELATIVE;
1583 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x)))
1584 return SYMBOL_GP_RELATIVE;
1587 /* Do not use small-data accesses for weak symbols; they may end up
1589 if (TARGET_GPOPT && SYMBOL_REF_SMALL_P (x) && !SYMBOL_REF_WEAK (x))
1590 return SYMBOL_GP_RELATIVE;
1592 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1594 if (TARGET_ABICALLS_PIC2
1595 && !(TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x)))
1597 /* There are three cases to consider:
1599 - o32 PIC (either with or without explicit relocs)
1600 - n32/n64 PIC without explicit relocs
1601 - n32/n64 PIC with explicit relocs
1603 In the first case, both local and global accesses will use an
1604 R_MIPS_GOT16 relocation. We must correctly predict which of
1605 the two semantics (local or global) the assembler and linker
1606 will apply. The choice depends on the symbol's binding rather
1607 than its visibility.
1609 In the second case, the assembler will not use R_MIPS_GOT16
1610 relocations, but it chooses between local and global accesses
1611 in the same way as for o32 PIC.
1613 In the third case we have more freedom since both forms of
1614 access will work for any kind of symbol. However, there seems
1615 little point in doing things differently. */
1616 if (mips_global_symbol_p (x))
1617 return SYMBOL_GOT_DISP;
1619 return SYMBOL_GOT_PAGE_OFST;
1622 if (TARGET_MIPS16_PCREL_LOADS && context != SYMBOL_CONTEXT_CALL)
1623 return SYMBOL_FORCE_TO_MEM;
1625 return SYMBOL_ABSOLUTE;
1628 /* Classify the base of symbolic expression X, given that X appears in
1631 static enum mips_symbol_type
1632 mips_classify_symbolic_expression (rtx x, enum mips_symbol_context context)
1636 split_const (x, &x, &offset);
1637 if (UNSPEC_ADDRESS_P (x))
1638 return UNSPEC_ADDRESS_TYPE (x);
1640 return mips_classify_symbol (x, context);
1643 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1644 is the alignment in bytes of SYMBOL_REF X. */
1647 mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset)
1649 HOST_WIDE_INT align;
1651 align = SYMBOL_REF_DECL (x) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x)) : 1;
1652 return IN_RANGE (offset, 0, align - 1);
1655 /* Return true if X is a symbolic constant that can be used in context
1656 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1659 mips_symbolic_constant_p (rtx x, enum mips_symbol_context context,
1660 enum mips_symbol_type *symbol_type)
1664 split_const (x, &x, &offset);
1665 if (UNSPEC_ADDRESS_P (x))
1667 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1668 x = UNSPEC_ADDRESS (x);
1670 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1672 *symbol_type = mips_classify_symbol (x, context);
1673 if (*symbol_type == SYMBOL_TLS)
1679 if (offset == const0_rtx)
1682 /* Check whether a nonzero offset is valid for the underlying
1684 switch (*symbol_type)
1686 case SYMBOL_ABSOLUTE:
1687 case SYMBOL_FORCE_TO_MEM:
1688 case SYMBOL_32_HIGH:
1689 case SYMBOL_64_HIGH:
1692 /* If the target has 64-bit pointers and the object file only
1693 supports 32-bit symbols, the values of those symbols will be
1694 sign-extended. In this case we can't allow an arbitrary offset
1695 in case the 32-bit value X + OFFSET has a different sign from X. */
1696 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1697 return offset_within_block_p (x, INTVAL (offset));
1699 /* In other cases the relocations can handle any offset. */
1702 case SYMBOL_PC_RELATIVE:
1703 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1704 In this case, we no longer have access to the underlying constant,
1705 but the original symbol-based access was known to be valid. */
1706 if (GET_CODE (x) == LABEL_REF)
1711 case SYMBOL_GP_RELATIVE:
1712 /* Make sure that the offset refers to something within the
1713 same object block. This should guarantee that the final
1714 PC- or GP-relative offset is within the 16-bit limit. */
1715 return offset_within_block_p (x, INTVAL (offset));
1717 case SYMBOL_GOT_PAGE_OFST:
1718 case SYMBOL_GOTOFF_PAGE:
1719 /* If the symbol is global, the GOT entry will contain the symbol's
1720 address, and we will apply a 16-bit offset after loading it.
1721 If the symbol is local, the linker should provide enough local
1722 GOT entries for a 16-bit offset, but larger offsets may lead
1724 return SMALL_INT (offset);
1728 /* There is no carry between the HI and LO REL relocations, so the
1729 offset is only valid if we know it won't lead to such a carry. */
1730 return mips_offset_within_alignment_p (x, INTVAL (offset));
1732 case SYMBOL_GOT_DISP:
1733 case SYMBOL_GOTOFF_DISP:
1734 case SYMBOL_GOTOFF_CALL:
1735 case SYMBOL_GOTOFF_LOADGP:
1738 case SYMBOL_GOTTPREL:
1746 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
1747 single instruction. We rely on the fact that, in the worst case,
1748 all instructions involved in a MIPS16 address calculation are usually
1752 mips_symbol_insns_1 (enum mips_symbol_type type, enum machine_mode mode)
1756 case SYMBOL_ABSOLUTE:
1757 /* When using 64-bit symbols, we need 5 preparatory instructions,
1760 lui $at,%highest(symbol)
1761 daddiu $at,$at,%higher(symbol)
1763 daddiu $at,$at,%hi(symbol)
1766 The final address is then $at + %lo(symbol). With 32-bit
1767 symbols we just need a preparatory LUI for normal mode and
1768 a preparatory LI and SLL for MIPS16. */
1769 return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2;
1771 case SYMBOL_GP_RELATIVE:
1772 /* Treat GP-relative accesses as taking a single instruction on
1773 MIPS16 too; the copy of $gp can often be shared. */
1776 case SYMBOL_PC_RELATIVE:
1777 /* PC-relative constants can be only be used with ADDIUPC,
1778 DADDIUPC, LWPC and LDPC. */
1779 if (mode == MAX_MACHINE_MODE
1780 || GET_MODE_SIZE (mode) == 4
1781 || GET_MODE_SIZE (mode) == 8)
1784 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
1787 case SYMBOL_FORCE_TO_MEM:
1788 /* LEAs will be converted into constant-pool references by
1790 if (mode == MAX_MACHINE_MODE)
1793 /* The constant must be loaded and then dereferenced. */
1796 case SYMBOL_GOT_DISP:
1797 /* The constant will have to be loaded from the GOT before it
1798 is used in an address. */
1799 if (mode != MAX_MACHINE_MODE)
1804 case SYMBOL_GOT_PAGE_OFST:
1805 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
1806 local/global classification is accurate. The worst cases are:
1808 (1) For local symbols when generating o32 or o64 code. The assembler
1814 ...and the final address will be $at + %lo(symbol).
1816 (2) For global symbols when -mxgot. The assembler will use:
1818 lui $at,%got_hi(symbol)
1821 ...and the final address will be $at + %got_lo(symbol). */
1824 case SYMBOL_GOTOFF_PAGE:
1825 case SYMBOL_GOTOFF_DISP:
1826 case SYMBOL_GOTOFF_CALL:
1827 case SYMBOL_GOTOFF_LOADGP:
1828 case SYMBOL_32_HIGH:
1829 case SYMBOL_64_HIGH:
1835 case SYMBOL_GOTTPREL:
1838 /* A 16-bit constant formed by a single relocation, or a 32-bit
1839 constant formed from a high 16-bit relocation and a low 16-bit
1840 relocation. Use mips_split_p to determine which. 32-bit
1841 constants need an "lui; addiu" sequence for normal mode and
1842 an "li; sll; addiu" sequence for MIPS16 mode. */
1843 return !mips_split_p[type] ? 1 : TARGET_MIPS16 ? 3 : 2;
1846 /* We don't treat a bare TLS symbol as a constant. */
1852 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
1853 to load symbols of type TYPE into a register. Return 0 if the given
1854 type of symbol cannot be used as an immediate operand.
1856 Otherwise, return the number of instructions needed to load or store
1857 values of mode MODE to or from addresses of type TYPE. Return 0 if
1858 the given type of symbol is not valid in addresses.
1860 In both cases, treat extended MIPS16 instructions as two instructions. */
1863 mips_symbol_insns (enum mips_symbol_type type, enum machine_mode mode)
1865 return mips_symbol_insns_1 (type, mode) * (TARGET_MIPS16 ? 2 : 1);
1868 /* A for_each_rtx callback. Stop the search if *X references a
1869 thread-local symbol. */
1872 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1874 return mips_tls_symbol_p (*x);
1877 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1880 mips_cannot_force_const_mem (enum machine_mode mode, rtx x)
1882 enum mips_symbol_type type;
1885 /* There is no assembler syntax for expressing an address-sized
1887 if (GET_CODE (x) == HIGH)
1890 /* As an optimization, reject constants that mips_legitimize_move
1893 Suppose we have a multi-instruction sequence that loads constant C
1894 into register R. If R does not get allocated a hard register, and
1895 R is used in an operand that allows both registers and memory
1896 references, reload will consider forcing C into memory and using
1897 one of the instruction's memory alternatives. Returning false
1898 here will force it to use an input reload instead. */
1899 if (CONST_INT_P (x) && mips_legitimate_constant_p (mode, x))
1902 split_const (x, &base, &offset);
1903 if (mips_symbolic_constant_p (base, SYMBOL_CONTEXT_LEA, &type)
1904 && type != SYMBOL_FORCE_TO_MEM)
1906 /* The same optimization as for CONST_INT. */
1907 if (SMALL_INT (offset) && mips_symbol_insns (type, MAX_MACHINE_MODE) > 0)
1910 /* If MIPS16 constant pools live in the text section, they should
1911 not refer to anything that might need run-time relocation. */
1912 if (TARGET_MIPS16_PCREL_LOADS && mips_got_symbol_type_p (type))
1916 /* TLS symbols must be computed by mips_legitimize_move. */
1917 if (for_each_rtx (&x, &mips_tls_symbol_ref_1, NULL))
1923 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
1924 constants when we're using a per-function constant pool. */
1927 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
1928 const_rtx x ATTRIBUTE_UNUSED)
1930 return !TARGET_MIPS16_PCREL_LOADS;
1933 /* Return true if register REGNO is a valid base register for mode MODE.
1934 STRICT_P is true if REG_OK_STRICT is in effect. */
1937 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode,
1940 if (!HARD_REGISTER_NUM_P (regno))
1944 regno = reg_renumber[regno];
1947 /* These fake registers will be eliminated to either the stack or
1948 hard frame pointer, both of which are usually valid base registers.
1949 Reload deals with the cases where the eliminated form isn't valid. */
1950 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
1953 /* In MIPS16 mode, the stack pointer can only address word and doubleword
1954 values, nothing smaller. There are two problems here:
1956 (a) Instantiating virtual registers can introduce new uses of the
1957 stack pointer. If these virtual registers are valid addresses,
1958 the stack pointer should be too.
1960 (b) Most uses of the stack pointer are not made explicit until
1961 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
1962 We don't know until that stage whether we'll be eliminating to the
1963 stack pointer (which needs the restriction) or the hard frame
1964 pointer (which doesn't).
1966 All in all, it seems more consistent to only enforce this restriction
1967 during and after reload. */
1968 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
1969 return !strict_p || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1971 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
1974 /* Return true if X is a valid base register for mode MODE.
1975 STRICT_P is true if REG_OK_STRICT is in effect. */
1978 mips_valid_base_register_p (rtx x, enum machine_mode mode, bool strict_p)
1980 if (!strict_p && GET_CODE (x) == SUBREG)
1984 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p));
1987 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
1988 can address a value of mode MODE. */
1991 mips_valid_offset_p (rtx x, enum machine_mode mode)
1993 /* Check that X is a signed 16-bit number. */
1994 if (!const_arith_operand (x, Pmode))
1997 /* We may need to split multiword moves, so make sure that every word
1999 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2000 && !SMALL_OPERAND (INTVAL (x) + GET_MODE_SIZE (mode) - UNITS_PER_WORD))
2006 /* Return true if a LO_SUM can address a value of mode MODE when the
2007 LO_SUM symbol has type SYMBOL_TYPE. */
2010 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type, enum machine_mode mode)
2012 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2014 if (mips_symbol_insns (symbol_type, mode) == 0)
2017 /* Check that there is a known low-part relocation. */
2018 if (mips_lo_relocs[symbol_type] == NULL)
2021 /* We may need to split multiword moves, so make sure that each word
2022 can be accessed without inducing a carry. This is mainly needed
2023 for o64, which has historically only guaranteed 64-bit alignment
2024 for 128-bit types. */
2025 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2026 && GET_MODE_BITSIZE (mode) > GET_MODE_ALIGNMENT (mode))
2032 /* Return true if X is a valid address for machine mode MODE. If it is,
2033 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2037 mips_classify_address (struct mips_address_info *info, rtx x,
2038 enum machine_mode mode, bool strict_p)
2040 switch (GET_CODE (x))
2044 info->type = ADDRESS_REG;
2046 info->offset = const0_rtx;
2047 return mips_valid_base_register_p (info->reg, mode, strict_p);
2050 info->type = ADDRESS_REG;
2051 info->reg = XEXP (x, 0);
2052 info->offset = XEXP (x, 1);
2053 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2054 && mips_valid_offset_p (info->offset, mode));
2057 info->type = ADDRESS_LO_SUM;
2058 info->reg = XEXP (x, 0);
2059 info->offset = XEXP (x, 1);
2060 /* We have to trust the creator of the LO_SUM to do something vaguely
2061 sane. Target-independent code that creates a LO_SUM should also
2062 create and verify the matching HIGH. Target-independent code that
2063 adds an offset to a LO_SUM must prove that the offset will not
2064 induce a carry. Failure to do either of these things would be
2065 a bug, and we are not required to check for it here. The MIPS
2066 backend itself should only create LO_SUMs for valid symbolic
2067 constants, with the high part being either a HIGH or a copy
2070 = mips_classify_symbolic_expression (info->offset, SYMBOL_CONTEXT_MEM);
2071 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2072 && mips_valid_lo_sum_p (info->symbol_type, mode));
2075 /* Small-integer addresses don't occur very often, but they
2076 are legitimate if $0 is a valid base register. */
2077 info->type = ADDRESS_CONST_INT;
2078 return !TARGET_MIPS16 && SMALL_INT (x);
2083 info->type = ADDRESS_SYMBOLIC;
2084 return (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_MEM,
2086 && mips_symbol_insns (info->symbol_type, mode) > 0
2087 && !mips_split_p[info->symbol_type]);
2094 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2097 mips_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
2099 struct mips_address_info addr;
2101 return mips_classify_address (&addr, x, mode, strict_p);
2104 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
2107 mips_stack_address_p (rtx x, enum machine_mode mode)
2109 struct mips_address_info addr;
2111 return (mips_classify_address (&addr, x, mode, false)
2112 && addr.type == ADDRESS_REG
2113 && addr.reg == stack_pointer_rtx);
2116 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2117 address instruction. Note that such addresses are not considered
2118 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2119 is so restricted. */
2122 mips_lwxs_address_p (rtx addr)
2125 && GET_CODE (addr) == PLUS
2126 && REG_P (XEXP (addr, 1)))
2128 rtx offset = XEXP (addr, 0);
2129 if (GET_CODE (offset) == MULT
2130 && REG_P (XEXP (offset, 0))
2131 && CONST_INT_P (XEXP (offset, 1))
2132 && INTVAL (XEXP (offset, 1)) == 4)
2138 /* Return true if a value at OFFSET bytes from base register BASE can be
2139 accessed using an unextended MIPS16 instruction. MODE is the mode of
2142 Usually the offset in an unextended instruction is a 5-bit field.
2143 The offset is unsigned and shifted left once for LH and SH, twice
2144 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2145 an 8-bit immediate field that's shifted left twice. */
2148 mips16_unextended_reference_p (enum machine_mode mode, rtx base,
2149 unsigned HOST_WIDE_INT offset)
2151 if (offset % GET_MODE_SIZE (mode) == 0)
2153 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
2154 return offset < 256U * GET_MODE_SIZE (mode);
2155 return offset < 32U * GET_MODE_SIZE (mode);
2160 /* Return the number of instructions needed to load or store a value
2161 of mode MODE at address X. Return 0 if X isn't valid for MODE.
2162 Assume that multiword moves may need to be split into word moves
2163 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2166 For MIPS16 code, count extended instructions as two instructions. */
2169 mips_address_insns (rtx x, enum machine_mode mode, bool might_split_p)
2171 struct mips_address_info addr;
2174 /* BLKmode is used for single unaligned loads and stores and should
2175 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2176 meaningless, so we have to single it out as a special case one way
2178 if (mode != BLKmode && might_split_p)
2179 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2183 if (mips_classify_address (&addr, x, mode, false))
2188 && !mips16_unextended_reference_p (mode, addr.reg,
2189 UINTVAL (addr.offset)))
2193 case ADDRESS_LO_SUM:
2194 return TARGET_MIPS16 ? factor * 2 : factor;
2196 case ADDRESS_CONST_INT:
2199 case ADDRESS_SYMBOLIC:
2200 return factor * mips_symbol_insns (addr.symbol_type, mode);
2205 /* Return the number of instructions needed to load constant X.
2206 Return 0 if X isn't a valid constant. */
2209 mips_const_insns (rtx x)
2211 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2212 enum mips_symbol_type symbol_type;
2215 switch (GET_CODE (x))
2218 if (!mips_symbolic_constant_p (XEXP (x, 0), SYMBOL_CONTEXT_LEA,
2220 || !mips_split_p[symbol_type])
2223 /* This is simply an LUI for normal mode. It is an extended
2224 LI followed by an extended SLL for MIPS16. */
2225 return TARGET_MIPS16 ? 4 : 1;
2229 /* Unsigned 8-bit constants can be loaded using an unextended
2230 LI instruction. Unsigned 16-bit constants can be loaded
2231 using an extended LI. Negative constants must be loaded
2232 using LI and then negated. */
2233 return (IN_RANGE (INTVAL (x), 0, 255) ? 1
2234 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
2235 : IN_RANGE (-INTVAL (x), 0, 255) ? 2
2236 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
2239 return mips_build_integer (codes, INTVAL (x));
2243 /* Allow zeros for normal mode, where we can use $0. */
2244 return !TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0;
2250 /* See if we can refer to X directly. */
2251 if (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_LEA, &symbol_type))
2252 return mips_symbol_insns (symbol_type, MAX_MACHINE_MODE);
2254 /* Otherwise try splitting the constant into a base and offset.
2255 If the offset is a 16-bit value, we can load the base address
2256 into a register and then use (D)ADDIU to add in the offset.
2257 If the offset is larger, we can load the base and offset
2258 into separate registers and add them together with (D)ADDU.
2259 However, the latter is only possible before reload; during
2260 and after reload, we must have the option of forcing the
2261 constant into the pool instead. */
2262 split_const (x, &x, &offset);
2265 int n = mips_const_insns (x);
2268 if (SMALL_INT (offset))
2270 else if (!targetm.cannot_force_const_mem (GET_MODE (x), x))
2271 return n + 1 + mips_build_integer (codes, INTVAL (offset));
2278 return mips_symbol_insns (mips_classify_symbol (x, SYMBOL_CONTEXT_LEA),
2286 /* X is a doubleword constant that can be handled by splitting it into
2287 two words and loading each word separately. Return the number of
2288 instructions required to do this. */
2291 mips_split_const_insns (rtx x)
2293 unsigned int low, high;
2295 low = mips_const_insns (mips_subword (x, false));
2296 high = mips_const_insns (mips_subword (x, true));
2297 gcc_assert (low > 0 && high > 0);
2301 /* Return the number of instructions needed to implement INSN,
2302 given that it loads from or stores to MEM. Count extended
2303 MIPS16 instructions as two instructions. */
2306 mips_load_store_insns (rtx mem, rtx insn)
2308 enum machine_mode mode;
2312 gcc_assert (MEM_P (mem));
2313 mode = GET_MODE (mem);
2315 /* Try to prove that INSN does not need to be split. */
2316 might_split_p = true;
2317 if (GET_MODE_BITSIZE (mode) == 64)
2319 set = single_set (insn);
2320 if (set && !mips_split_64bit_move_p (SET_DEST (set), SET_SRC (set)))
2321 might_split_p = false;
2324 return mips_address_insns (XEXP (mem, 0), mode, might_split_p);
2327 /* Return the number of instructions needed for an integer division. */
2330 mips_idiv_insns (void)
2335 if (TARGET_CHECK_ZERO_DIV)
2337 if (GENERATE_DIVIDE_TRAPS)
2343 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
2348 /* Emit a move from SRC to DEST. Assume that the move expanders can
2349 handle all moves if !can_create_pseudo_p (). The distinction is
2350 important because, unlike emit_move_insn, the move expanders know
2351 how to force Pmode objects into the constant pool even when the
2352 constant pool address is not itself legitimate. */
2355 mips_emit_move (rtx dest, rtx src)
2357 return (can_create_pseudo_p ()
2358 ? emit_move_insn (dest, src)
2359 : emit_move_insn_1 (dest, src));
2362 /* Emit an instruction of the form (set TARGET (CODE OP0)). */
2365 mips_emit_unary (enum rtx_code code, rtx target, rtx op0)
2367 emit_insn (gen_rtx_SET (VOIDmode, target,
2368 gen_rtx_fmt_e (code, GET_MODE (op0), op0)));
2371 /* Compute (CODE OP0) and store the result in a new register of mode MODE.
2372 Return that new register. */
2375 mips_force_unary (enum machine_mode mode, enum rtx_code code, rtx op0)
2379 reg = gen_reg_rtx (mode);
2380 mips_emit_unary (code, reg, op0);
2384 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2387 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
2389 emit_insn (gen_rtx_SET (VOIDmode, target,
2390 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
2393 /* Compute (CODE OP0 OP1) and store the result in a new register
2394 of mode MODE. Return that new register. */
2397 mips_force_binary (enum machine_mode mode, enum rtx_code code, rtx op0, rtx op1)
2401 reg = gen_reg_rtx (mode);
2402 mips_emit_binary (code, reg, op0, op1);
2406 /* Copy VALUE to a register and return that register. If new pseudos
2407 are allowed, copy it into a new register, otherwise use DEST. */
2410 mips_force_temporary (rtx dest, rtx value)
2412 if (can_create_pseudo_p ())
2413 return force_reg (Pmode, value);
2416 mips_emit_move (dest, value);
2421 /* Emit a call sequence with call pattern PATTERN and return the call
2422 instruction itself (which is not necessarily the last instruction
2423 emitted). ORIG_ADDR is the original, unlegitimized address,
2424 ADDR is the legitimized form, and LAZY_P is true if the call
2425 address is lazily-bound. */
2428 mips_emit_call_insn (rtx pattern, rtx orig_addr, rtx addr, bool lazy_p)
2432 insn = emit_call_insn (pattern);
2434 if (TARGET_MIPS16 && mips_use_pic_fn_addr_reg_p (orig_addr))
2436 /* MIPS16 JALRs only take MIPS16 registers. If the target
2437 function requires $25 to be valid on entry, we must copy it
2438 there separately. The move instruction can be put in the
2439 call's delay slot. */
2440 reg = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
2441 emit_insn_before (gen_move_insn (reg, addr), insn);
2442 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
2446 /* Lazy-binding stubs require $gp to be valid on entry. */
2447 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
2451 /* See the comment above load_call<mode> for details. */
2452 use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
2453 gen_rtx_REG (Pmode, GOT_VERSION_REGNUM));
2454 emit_insn (gen_update_got_version ());
2459 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2460 then add CONST_INT OFFSET to the result. */
2463 mips_unspec_address_offset (rtx base, rtx offset,
2464 enum mips_symbol_type symbol_type)
2466 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
2467 UNSPEC_ADDRESS_FIRST + symbol_type);
2468 if (offset != const0_rtx)
2469 base = gen_rtx_PLUS (Pmode, base, offset);
2470 return gen_rtx_CONST (Pmode, base);
2473 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2474 type SYMBOL_TYPE. */
2477 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
2481 split_const (address, &base, &offset);
2482 return mips_unspec_address_offset (base, offset, symbol_type);
2485 /* If OP is an UNSPEC address, return the address to which it refers,
2486 otherwise return OP itself. */
2489 mips_strip_unspec_address (rtx op)
2493 split_const (op, &base, &offset);
2494 if (UNSPEC_ADDRESS_P (base))
2495 op = plus_constant (UNSPEC_ADDRESS (base), INTVAL (offset));
2499 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2500 high part to BASE and return the result. Just return BASE otherwise.
2501 TEMP is as for mips_force_temporary.
2503 The returned expression can be used as the first operand to a LO_SUM. */
2506 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
2507 enum mips_symbol_type symbol_type)
2509 if (mips_split_p[symbol_type])
2511 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
2512 addr = mips_force_temporary (temp, addr);
2513 base = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
2518 /* Return an instruction that copies $gp into register REG. We want
2519 GCC to treat the register's value as constant, so that its value
2520 can be rematerialized on demand. */
2523 gen_load_const_gp (rtx reg)
2525 return (Pmode == SImode
2526 ? gen_load_const_gp_si (reg)
2527 : gen_load_const_gp_di (reg));
2530 /* Return a pseudo register that contains the value of $gp throughout
2531 the current function. Such registers are needed by MIPS16 functions,
2532 for which $gp itself is not a valid base register or addition operand. */
2535 mips16_gp_pseudo_reg (void)
2537 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
2541 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
2543 push_topmost_sequence ();
2545 scan = get_insns ();
2546 while (NEXT_INSN (scan) && !INSN_P (NEXT_INSN (scan)))
2547 scan = NEXT_INSN (scan);
2549 insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
2550 emit_insn_after (insn, scan);
2552 pop_topmost_sequence ();
2555 return cfun->machine->mips16_gp_pseudo_rtx;
2558 /* Return a base register that holds pic_offset_table_rtx.
2559 TEMP, if nonnull, is a scratch Pmode base register. */
2562 mips_pic_base_register (rtx temp)
2565 return pic_offset_table_rtx;
2567 if (currently_expanding_to_rtl)
2568 return mips16_gp_pseudo_reg ();
2570 if (can_create_pseudo_p ())
2571 temp = gen_reg_rtx (Pmode);
2574 /* The first post-reload split exposes all references to $gp
2575 (both uses and definitions). All references must remain
2576 explicit after that point.
2578 It is safe to introduce uses of $gp at any time, so for
2579 simplicity, we do that before the split too. */
2580 mips_emit_move (temp, pic_offset_table_rtx);
2582 emit_insn (gen_load_const_gp (temp));
2586 /* Return the RHS of a load_call<mode> insn. */
2589 mips_unspec_call (rtx reg, rtx symbol)
2593 vec = gen_rtvec (3, reg, symbol, gen_rtx_REG (SImode, GOT_VERSION_REGNUM));
2594 return gen_rtx_UNSPEC (Pmode, vec, UNSPEC_LOAD_CALL);
2597 /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol
2598 reference. Return NULL_RTX otherwise. */
2601 mips_strip_unspec_call (rtx src)
2603 if (GET_CODE (src) == UNSPEC && XINT (src, 1) == UNSPEC_LOAD_CALL)
2604 return mips_strip_unspec_address (XVECEXP (src, 0, 1));
2608 /* Create and return a GOT reference of type TYPE for address ADDR.
2609 TEMP, if nonnull, is a scratch Pmode base register. */
2612 mips_got_load (rtx temp, rtx addr, enum mips_symbol_type type)
2614 rtx base, high, lo_sum_symbol;
2616 base = mips_pic_base_register (temp);
2618 /* If we used the temporary register to load $gp, we can't use
2619 it for the high part as well. */
2620 if (temp != NULL && reg_overlap_mentioned_p (base, temp))
2623 high = mips_unspec_offset_high (temp, base, addr, type);
2624 lo_sum_symbol = mips_unspec_address (addr, type);
2626 if (type == SYMBOL_GOTOFF_CALL)
2627 return mips_unspec_call (high, lo_sum_symbol);
2629 return (Pmode == SImode
2630 ? gen_unspec_gotsi (high, lo_sum_symbol)
2631 : gen_unspec_gotdi (high, lo_sum_symbol));
2634 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2635 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2636 constant in that context and can be split into high and low parts.
2637 If so, and if LOW_OUT is nonnull, emit the high part and store the
2638 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
2640 TEMP is as for mips_force_temporary and is used to load the high
2641 part into a register.
2643 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
2644 a legitimize SET_SRC for an .md pattern, otherwise the low part
2645 is guaranteed to be a legitimate address for mode MODE. */
2648 mips_split_symbol (rtx temp, rtx addr, enum machine_mode mode, rtx *low_out)
2650 enum mips_symbol_context context;
2651 enum mips_symbol_type symbol_type;
2654 context = (mode == MAX_MACHINE_MODE
2655 ? SYMBOL_CONTEXT_LEA
2656 : SYMBOL_CONTEXT_MEM);
2657 if (GET_CODE (addr) == HIGH && context == SYMBOL_CONTEXT_LEA)
2659 addr = XEXP (addr, 0);
2660 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2661 && mips_symbol_insns (symbol_type, mode) > 0
2662 && mips_split_hi_p[symbol_type])
2665 switch (symbol_type)
2667 case SYMBOL_GOT_PAGE_OFST:
2668 /* The high part of a page/ofst pair is loaded from the GOT. */
2669 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_PAGE);
2680 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2681 && mips_symbol_insns (symbol_type, mode) > 0
2682 && mips_split_p[symbol_type])
2685 switch (symbol_type)
2687 case SYMBOL_GOT_DISP:
2688 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
2689 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_DISP);
2692 case SYMBOL_GP_RELATIVE:
2693 high = mips_pic_base_register (temp);
2694 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2698 high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
2699 high = mips_force_temporary (temp, high);
2700 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2709 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2710 mips_force_temporary; it is only needed when OFFSET is not a
2714 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
2716 if (!SMALL_OPERAND (offset))
2722 /* Load the full offset into a register so that we can use
2723 an unextended instruction for the address itself. */
2724 high = GEN_INT (offset);
2729 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
2730 The addition inside the macro CONST_HIGH_PART may cause an
2731 overflow, so we need to force a sign-extension check. */
2732 high = gen_int_mode (CONST_HIGH_PART (offset), Pmode);
2733 offset = CONST_LOW_PART (offset);
2735 high = mips_force_temporary (temp, high);
2736 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
2738 return plus_constant (reg, offset);
2741 /* The __tls_get_attr symbol. */
2742 static GTY(()) rtx mips_tls_symbol;
2744 /* Return an instruction sequence that calls __tls_get_addr. SYM is
2745 the TLS symbol we are referencing and TYPE is the symbol type to use
2746 (either global dynamic or local dynamic). V0 is an RTX for the
2747 return value location. */
2750 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
2754 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
2756 if (!mips_tls_symbol)
2757 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
2759 loc = mips_unspec_address (sym, type);
2763 emit_insn (gen_rtx_SET (Pmode, a0,
2764 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
2765 insn = mips_expand_call (MIPS_CALL_NORMAL, v0, mips_tls_symbol,
2766 const0_rtx, NULL_RTX, false);
2767 RTL_CONST_CALL_P (insn) = 1;
2768 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
2769 insn = get_insns ();
2776 /* Return a pseudo register that contains the current thread pointer. */
2783 tp = gen_reg_rtx (Pmode);
2784 if (Pmode == DImode)
2785 emit_insn (gen_tls_get_tp_di (tp));
2787 emit_insn (gen_tls_get_tp_si (tp));
2791 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
2792 its address. The return value will be both a valid address and a valid
2793 SET_SRC (either a REG or a LO_SUM). */
2796 mips_legitimize_tls_address (rtx loc)
2798 rtx dest, insn, v0, tp, tmp1, tmp2, eqv;
2799 enum tls_model model;
2803 sorry ("MIPS16 TLS");
2804 return gen_reg_rtx (Pmode);
2807 model = SYMBOL_REF_TLS_MODEL (loc);
2808 /* Only TARGET_ABICALLS code can have more than one module; other
2809 code must be be static and should not use a GOT. All TLS models
2810 reduce to local exec in this situation. */
2811 if (!TARGET_ABICALLS)
2812 model = TLS_MODEL_LOCAL_EXEC;
2816 case TLS_MODEL_GLOBAL_DYNAMIC:
2817 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2818 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
2819 dest = gen_reg_rtx (Pmode);
2820 emit_libcall_block (insn, dest, v0, loc);
2823 case TLS_MODEL_LOCAL_DYNAMIC:
2824 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2825 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
2826 tmp1 = gen_reg_rtx (Pmode);
2828 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2829 share the LDM result with other LD model accesses. */
2830 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2832 emit_libcall_block (insn, tmp1, v0, eqv);
2834 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
2835 dest = gen_rtx_LO_SUM (Pmode, tmp2,
2836 mips_unspec_address (loc, SYMBOL_DTPREL));
2839 case TLS_MODEL_INITIAL_EXEC:
2840 tp = mips_get_tp ();
2841 tmp1 = gen_reg_rtx (Pmode);
2842 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
2843 if (Pmode == DImode)
2844 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
2846 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
2847 dest = gen_reg_rtx (Pmode);
2848 emit_insn (gen_add3_insn (dest, tmp1, tp));
2851 case TLS_MODEL_LOCAL_EXEC:
2852 tp = mips_get_tp ();
2853 tmp1 = mips_unspec_offset_high (NULL, tp, loc, SYMBOL_TPREL);
2854 dest = gen_rtx_LO_SUM (Pmode, tmp1,
2855 mips_unspec_address (loc, SYMBOL_TPREL));
2864 /* If X is not a valid address for mode MODE, force it into a register. */
2867 mips_force_address (rtx x, enum machine_mode mode)
2869 if (!mips_legitimate_address_p (mode, x, false))
2870 x = force_reg (Pmode, x);
2874 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
2875 be legitimized in a way that the generic machinery might not expect,
2876 return a new address, otherwise return NULL. MODE is the mode of
2877 the memory being accessed. */
2880 mips_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
2881 enum machine_mode mode)
2884 HOST_WIDE_INT offset;
2886 if (mips_tls_symbol_p (x))
2887 return mips_legitimize_tls_address (x);
2889 /* See if the address can split into a high part and a LO_SUM. */
2890 if (mips_split_symbol (NULL, x, mode, &addr))
2891 return mips_force_address (addr, mode);
2893 /* Handle BASE + OFFSET using mips_add_offset. */
2894 mips_split_plus (x, &base, &offset);
2897 if (!mips_valid_base_register_p (base, mode, false))
2898 base = copy_to_mode_reg (Pmode, base);
2899 addr = mips_add_offset (NULL, base, offset);
2900 return mips_force_address (addr, mode);
2906 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
2909 mips_move_integer (rtx temp, rtx dest, unsigned HOST_WIDE_INT value)
2911 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2912 enum machine_mode mode;
2913 unsigned int i, num_ops;
2916 mode = GET_MODE (dest);
2917 num_ops = mips_build_integer (codes, value);
2919 /* Apply each binary operation to X. Invariant: X is a legitimate
2920 source operand for a SET pattern. */
2921 x = GEN_INT (codes[0].value);
2922 for (i = 1; i < num_ops; i++)
2924 if (!can_create_pseudo_p ())
2926 emit_insn (gen_rtx_SET (VOIDmode, temp, x));
2930 x = force_reg (mode, x);
2931 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
2934 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
2937 /* Subroutine of mips_legitimize_move. Move constant SRC into register
2938 DEST given that SRC satisfies immediate_operand but doesn't satisfy
2942 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
2946 /* Split moves of big integers into smaller pieces. */
2947 if (splittable_const_int_operand (src, mode))
2949 mips_move_integer (dest, dest, INTVAL (src));
2953 /* Split moves of symbolic constants into high/low pairs. */
2954 if (mips_split_symbol (dest, src, MAX_MACHINE_MODE, &src))
2956 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
2960 /* Generate the appropriate access sequences for TLS symbols. */
2961 if (mips_tls_symbol_p (src))
2963 mips_emit_move (dest, mips_legitimize_tls_address (src));
2967 /* If we have (const (plus symbol offset)), and that expression cannot
2968 be forced into memory, load the symbol first and add in the offset.
2969 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
2970 forced into memory, as it usually produces better code. */
2971 split_const (src, &base, &offset);
2972 if (offset != const0_rtx
2973 && (targetm.cannot_force_const_mem (mode, src)
2974 || (!TARGET_MIPS16 && can_create_pseudo_p ())))
2976 base = mips_force_temporary (dest, base);
2977 mips_emit_move (dest, mips_add_offset (NULL, base, INTVAL (offset)));
2981 src = force_const_mem (mode, src);
2983 /* When using explicit relocs, constant pool references are sometimes
2984 not legitimate addresses. */
2985 mips_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0));
2986 mips_emit_move (dest, src);
2989 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
2990 sequence that is valid. */
2993 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
2995 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
2997 mips_emit_move (dest, force_reg (mode, src));
3001 /* We need to deal with constants that would be legitimate
3002 immediate_operands but aren't legitimate move_operands. */
3003 if (CONSTANT_P (src) && !move_operand (src, mode))
3005 mips_legitimize_const_move (mode, dest, src);
3006 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
3012 /* Return true if value X in context CONTEXT is a small-data address
3013 that can be rewritten as a LO_SUM. */
3016 mips_rewrite_small_data_p (rtx x, enum mips_symbol_context context)
3018 enum mips_symbol_type symbol_type;
3020 return (mips_lo_relocs[SYMBOL_GP_RELATIVE]
3021 && !mips_split_p[SYMBOL_GP_RELATIVE]
3022 && mips_symbolic_constant_p (x, context, &symbol_type)
3023 && symbol_type == SYMBOL_GP_RELATIVE);
3026 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
3027 containing MEM, or null if none. */
3030 mips_small_data_pattern_1 (rtx *loc, void *data)
3032 enum mips_symbol_context context;
3034 if (GET_CODE (*loc) == LO_SUM)
3039 if (for_each_rtx (&XEXP (*loc, 0), mips_small_data_pattern_1, *loc))
3044 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3045 return mips_rewrite_small_data_p (*loc, context);
3048 /* Return true if OP refers to small data symbols directly, not through
3052 mips_small_data_pattern_p (rtx op)
3054 return for_each_rtx (&op, mips_small_data_pattern_1, NULL);
3057 /* A for_each_rtx callback, used by mips_rewrite_small_data.
3058 DATA is the containing MEM, or null if none. */
3061 mips_rewrite_small_data_1 (rtx *loc, void *data)
3063 enum mips_symbol_context context;
3067 for_each_rtx (&XEXP (*loc, 0), mips_rewrite_small_data_1, *loc);
3071 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3072 if (mips_rewrite_small_data_p (*loc, context))
3073 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
3075 if (GET_CODE (*loc) == LO_SUM)
3081 /* Rewrite instruction pattern PATTERN so that it refers to small data
3082 using explicit relocations. */
3085 mips_rewrite_small_data (rtx pattern)
3087 pattern = copy_insn (pattern);
3088 for_each_rtx (&pattern, mips_rewrite_small_data_1, NULL);
3092 /* We need a lot of little routines to check the range of MIPS16 immediate
3096 m16_check_op (rtx op, int low, int high, int mask)
3098 return (CONST_INT_P (op)
3099 && IN_RANGE (INTVAL (op), low, high)
3100 && (INTVAL (op) & mask) == 0);
3104 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3106 return m16_check_op (op, 0x1, 0x8, 0);
3110 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3112 return m16_check_op (op, -0x8, 0x7, 0);
3116 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3118 return m16_check_op (op, -0x7, 0x8, 0);
3122 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3124 return m16_check_op (op, -0x10, 0xf, 0);
3128 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3130 return m16_check_op (op, -0xf, 0x10, 0);
3134 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3136 return m16_check_op (op, -0x10 << 2, 0xf << 2, 3);
3140 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3142 return m16_check_op (op, -0xf << 2, 0x10 << 2, 3);
3146 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3148 return m16_check_op (op, -0x80, 0x7f, 0);
3152 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3154 return m16_check_op (op, -0x7f, 0x80, 0);
3158 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3160 return m16_check_op (op, 0x0, 0xff, 0);
3164 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3166 return m16_check_op (op, -0xff, 0x0, 0);
3170 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3172 return m16_check_op (op, -0x1, 0xfe, 0);
3176 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3178 return m16_check_op (op, 0x0, 0xff << 2, 3);
3182 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3184 return m16_check_op (op, -0xff << 2, 0x0, 3);
3188 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3190 return m16_check_op (op, -0x80 << 3, 0x7f << 3, 7);
3194 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3196 return m16_check_op (op, -0x7f << 3, 0x80 << 3, 7);
3199 /* The cost of loading values from the constant pool. It should be
3200 larger than the cost of any constant we want to synthesize inline. */
3201 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3203 /* Return the cost of X when used as an operand to the MIPS16 instruction
3204 that implements CODE. Return -1 if there is no such instruction, or if
3205 X is not a valid immediate operand for it. */
3208 mips16_constant_cost (int code, HOST_WIDE_INT x)
3215 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3216 other shifts are extended. The shift patterns truncate the shift
3217 count to the right size, so there are no out-of-range values. */
3218 if (IN_RANGE (x, 1, 8))
3220 return COSTS_N_INSNS (1);
3223 if (IN_RANGE (x, -128, 127))
3225 if (SMALL_OPERAND (x))
3226 return COSTS_N_INSNS (1);
3230 /* Like LE, but reject the always-true case. */
3234 /* We add 1 to the immediate and use SLT. */
3237 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3240 if (IN_RANGE (x, 0, 255))
3242 if (SMALL_OPERAND_UNSIGNED (x))
3243 return COSTS_N_INSNS (1);
3248 /* Equality comparisons with 0 are cheap. */
3258 /* Return true if there is a non-MIPS16 instruction that implements CODE
3259 and if that instruction accepts X as an immediate operand. */
3262 mips_immediate_operand_p (int code, HOST_WIDE_INT x)
3269 /* All shift counts are truncated to a valid constant. */
3274 /* Likewise rotates, if the target supports rotates at all. */
3280 /* These instructions take 16-bit unsigned immediates. */
3281 return SMALL_OPERAND_UNSIGNED (x);
3286 /* These instructions take 16-bit signed immediates. */
3287 return SMALL_OPERAND (x);
3293 /* The "immediate" forms of these instructions are really
3294 implemented as comparisons with register 0. */
3299 /* Likewise, meaning that the only valid immediate operand is 1. */
3303 /* We add 1 to the immediate and use SLT. */
3304 return SMALL_OPERAND (x + 1);
3307 /* Likewise SLTU, but reject the always-true case. */
3308 return SMALL_OPERAND (x + 1) && x + 1 != 0;
3312 /* The bit position and size are immediate operands. */
3313 return ISA_HAS_EXT_INS;
3316 /* By default assume that $0 can be used for 0. */
3321 /* Return the cost of binary operation X, given that the instruction
3322 sequence for a word-sized or smaller operation has cost SINGLE_COST
3323 and that the sequence of a double-word operation has cost DOUBLE_COST.
3324 If SPEED is true, optimize for speed otherwise optimize for size. */
3327 mips_binary_cost (rtx x, int single_cost, int double_cost, bool speed)
3331 if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2)
3336 + rtx_cost (XEXP (x, 0), SET, speed)
3337 + rtx_cost (XEXP (x, 1), GET_CODE (x), speed));
3340 /* Return the cost of floating-point multiplications of mode MODE. */
3343 mips_fp_mult_cost (enum machine_mode mode)
3345 return mode == DFmode ? mips_cost->fp_mult_df : mips_cost->fp_mult_sf;
3348 /* Return the cost of floating-point divisions of mode MODE. */
3351 mips_fp_div_cost (enum machine_mode mode)
3353 return mode == DFmode ? mips_cost->fp_div_df : mips_cost->fp_div_sf;
3356 /* Return the cost of sign-extending OP to mode MODE, not including the
3357 cost of OP itself. */
3360 mips_sign_extend_cost (enum machine_mode mode, rtx op)
3363 /* Extended loads are as cheap as unextended ones. */
3366 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3367 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3370 if (ISA_HAS_SEB_SEH || GENERATE_MIPS16E)
3371 /* We can use SEB or SEH. */
3372 return COSTS_N_INSNS (1);
3374 /* We need to use a shift left and a shift right. */
3375 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3378 /* Return the cost of zero-extending OP to mode MODE, not including the
3379 cost of OP itself. */
3382 mips_zero_extend_cost (enum machine_mode mode, rtx op)
3385 /* Extended loads are as cheap as unextended ones. */
3388 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3389 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3390 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3392 if (GENERATE_MIPS16E)
3393 /* We can use ZEB or ZEH. */
3394 return COSTS_N_INSNS (1);
3397 /* We need to load 0xff or 0xffff into a register and use AND. */
3398 return COSTS_N_INSNS (GET_MODE (op) == QImode ? 2 : 3);
3400 /* We can use ANDI. */
3401 return COSTS_N_INSNS (1);
3404 /* Implement TARGET_RTX_COSTS. */
3407 mips_rtx_costs (rtx x, int code, int outer_code, int *total, bool speed)
3409 enum machine_mode mode = GET_MODE (x);
3410 bool float_mode_p = FLOAT_MODE_P (mode);
3414 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3415 appear in the instruction stream, and the cost of a comparison is
3416 really the cost of the branch or scc condition. At the time of
3417 writing, GCC only uses an explicit outer COMPARE code when optabs
3418 is testing whether a constant is expensive enough to force into a
3419 register. We want optabs to pass such constants through the MIPS
3420 expanders instead, so make all constants very cheap here. */
3421 if (outer_code == COMPARE)
3423 gcc_assert (CONSTANT_P (x));
3431 /* Treat *clear_upper32-style ANDs as having zero cost in the
3432 second operand. The cost is entirely in the first operand.
3434 ??? This is needed because we would otherwise try to CSE
3435 the constant operand. Although that's the right thing for
3436 instructions that continue to be a register operation throughout
3437 compilation, it is disastrous for instructions that could
3438 later be converted into a memory operation. */
3440 && outer_code == AND
3441 && UINTVAL (x) == 0xffffffff)
3449 cost = mips16_constant_cost (outer_code, INTVAL (x));
3458 /* When not optimizing for size, we care more about the cost
3459 of hot code, and hot code is often in a loop. If a constant
3460 operand needs to be forced into a register, we will often be
3461 able to hoist the constant load out of the loop, so the load
3462 should not contribute to the cost. */
3463 if (speed || mips_immediate_operand_p (outer_code, INTVAL (x)))
3475 if (force_to_mem_operand (x, VOIDmode))
3477 *total = COSTS_N_INSNS (1);
3480 cost = mips_const_insns (x);
3483 /* If the constant is likely to be stored in a GPR, SETs of
3484 single-insn constants are as cheap as register sets; we
3485 never want to CSE them.
3487 Don't reduce the cost of storing a floating-point zero in
3488 FPRs. If we have a zero in an FPR for other reasons, we
3489 can get better cfg-cleanup and delayed-branch results by
3490 using it consistently, rather than using $0 sometimes and
3491 an FPR at other times. Also, moves between floating-point
3492 registers are sometimes cheaper than (D)MTC1 $0. */
3494 && outer_code == SET
3495 && !(float_mode_p && TARGET_HARD_FLOAT))
3497 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3498 want to CSE the constant itself. It is usually better to
3499 have N copies of the last operation in the sequence and one
3500 shared copy of the other operations. (Note that this is
3501 not true for MIPS16 code, where the final operation in the
3502 sequence is often an extended instruction.)
3504 Also, if we have a CONST_INT, we don't know whether it is
3505 for a word or doubleword operation, so we cannot rely on
3506 the result of mips_build_integer. */
3507 else if (!TARGET_MIPS16
3508 && (outer_code == SET || mode == VOIDmode))
3510 *total = COSTS_N_INSNS (cost);
3513 /* The value will need to be fetched from the constant pool. */
3514 *total = CONSTANT_POOL_COST;
3518 /* If the address is legitimate, return the number of
3519 instructions it needs. */
3521 cost = mips_address_insns (addr, mode, true);
3524 *total = COSTS_N_INSNS (cost + 1);
3527 /* Check for a scaled indexed address. */
3528 if (mips_lwxs_address_p (addr))
3530 *total = COSTS_N_INSNS (2);
3533 /* Otherwise use the default handling. */
3537 *total = COSTS_N_INSNS (6);
3541 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1);
3545 /* Check for a *clear_upper32 pattern and treat it like a zero
3546 extension. See the pattern's comment for details. */
3549 && CONST_INT_P (XEXP (x, 1))
3550 && UINTVAL (XEXP (x, 1)) == 0xffffffff)
3552 *total = (mips_zero_extend_cost (mode, XEXP (x, 0))
3553 + rtx_cost (XEXP (x, 0), SET, speed));
3560 /* Double-word operations use two single-word operations. */
3561 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (2),
3570 if (CONSTANT_P (XEXP (x, 1)))
3571 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3574 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (12),
3580 *total = mips_cost->fp_add;
3582 *total = COSTS_N_INSNS (4);
3586 /* Low-part immediates need an extended MIPS16 instruction. */
3587 *total = (COSTS_N_INSNS (TARGET_MIPS16 ? 2 : 1)
3588 + rtx_cost (XEXP (x, 0), SET, speed));
3603 /* Branch comparisons have VOIDmode, so use the first operand's
3605 mode = GET_MODE (XEXP (x, 0));
3606 if (FLOAT_MODE_P (mode))
3608 *total = mips_cost->fp_add;
3611 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3617 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3618 && TARGET_FUSED_MADD
3619 && !HONOR_NANS (mode)
3620 && !HONOR_SIGNED_ZEROS (mode))
3622 /* See if we can use NMADD or NMSUB. See mips.md for the
3623 associated patterns. */
3624 rtx op0 = XEXP (x, 0);
3625 rtx op1 = XEXP (x, 1);
3626 if (GET_CODE (op0) == MULT && GET_CODE (XEXP (op0, 0)) == NEG)
3628 *total = (mips_fp_mult_cost (mode)
3629 + rtx_cost (XEXP (XEXP (op0, 0), 0), SET, speed)
3630 + rtx_cost (XEXP (op0, 1), SET, speed)
3631 + rtx_cost (op1, SET, speed));
3634 if (GET_CODE (op1) == MULT)
3636 *total = (mips_fp_mult_cost (mode)
3637 + rtx_cost (op0, SET, speed)
3638 + rtx_cost (XEXP (op1, 0), SET, speed)
3639 + rtx_cost (XEXP (op1, 1), SET, speed));
3648 /* If this is part of a MADD or MSUB, treat the PLUS as
3651 && TARGET_FUSED_MADD
3652 && GET_CODE (XEXP (x, 0)) == MULT)
3655 *total = mips_cost->fp_add;
3659 /* Double-word operations require three single-word operations and
3660 an SLTU. The MIPS16 version then needs to move the result of
3661 the SLTU from $24 to a MIPS16 register. */
3662 *total = mips_binary_cost (x, COSTS_N_INSNS (1),
3663 COSTS_N_INSNS (TARGET_MIPS16 ? 5 : 4),
3669 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3670 && TARGET_FUSED_MADD
3671 && !HONOR_NANS (mode)
3672 && HONOR_SIGNED_ZEROS (mode))
3674 /* See if we can use NMADD or NMSUB. See mips.md for the
3675 associated patterns. */
3676 rtx op = XEXP (x, 0);
3677 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
3678 && GET_CODE (XEXP (op, 0)) == MULT)
3680 *total = (mips_fp_mult_cost (mode)
3681 + rtx_cost (XEXP (XEXP (op, 0), 0), SET, speed)
3682 + rtx_cost (XEXP (XEXP (op, 0), 1), SET, speed)
3683 + rtx_cost (XEXP (op, 1), SET, speed));
3689 *total = mips_cost->fp_add;
3691 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1);
3696 *total = mips_fp_mult_cost (mode);
3697 else if (mode == DImode && !TARGET_64BIT)
3698 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
3699 where the mulsidi3 always includes an MFHI and an MFLO. */
3701 ? mips_cost->int_mult_si * 3 + 6
3702 : COSTS_N_INSNS (ISA_HAS_MUL3 ? 7 : 9));
3704 *total = (ISA_HAS_MUL3 ? 1 : 2);
3705 else if (mode == DImode)
3706 *total = mips_cost->int_mult_di;
3708 *total = mips_cost->int_mult_si;
3712 /* Check for a reciprocal. */
3715 && flag_unsafe_math_optimizations
3716 && XEXP (x, 0) == CONST1_RTX (mode))
3718 if (outer_code == SQRT || GET_CODE (XEXP (x, 1)) == SQRT)
3719 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
3720 division as being free. */
3721 *total = rtx_cost (XEXP (x, 1), SET, speed);
3723 *total = (mips_fp_div_cost (mode)
3724 + rtx_cost (XEXP (x, 1), SET, speed));
3733 *total = mips_fp_div_cost (mode);
3742 /* It is our responsibility to make division by a power of 2
3743 as cheap as 2 register additions if we want the division
3744 expanders to be used for such operations; see the setting
3745 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
3746 should always produce shorter code than using
3747 expand_sdiv2_pow2. */
3749 && CONST_INT_P (XEXP (x, 1))
3750 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
3752 *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), SET, speed);
3755 *total = COSTS_N_INSNS (mips_idiv_insns ());
3757 else if (mode == DImode)
3758 *total = mips_cost->int_div_di;
3760 *total = mips_cost->int_div_si;
3764 *total = mips_sign_extend_cost (mode, XEXP (x, 0));
3768 *total = mips_zero_extend_cost (mode, XEXP (x, 0));
3772 case UNSIGNED_FLOAT:
3775 case FLOAT_TRUNCATE:
3776 *total = mips_cost->fp_add;
3784 /* Implement TARGET_ADDRESS_COST. */
3787 mips_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED)
3789 return mips_address_insns (addr, SImode, false);
3792 /* Information about a single instruction in a multi-instruction
3794 struct mips_multi_member {
3795 /* True if this is a label, false if it is code. */
3798 /* The output_asm_insn format of the instruction. */
3801 /* The operands to the instruction. */
3802 rtx operands[MAX_RECOG_OPERANDS];
3804 typedef struct mips_multi_member mips_multi_member;
3806 /* Vector definitions for the above. */
3807 DEF_VEC_O(mips_multi_member);
3808 DEF_VEC_ALLOC_O(mips_multi_member, heap);
3810 /* The instructions that make up the current multi-insn sequence. */
3811 static VEC (mips_multi_member, heap) *mips_multi_members;
3813 /* How many instructions (as opposed to labels) are in the current
3814 multi-insn sequence. */
3815 static unsigned int mips_multi_num_insns;
3817 /* Start a new multi-insn sequence. */
3820 mips_multi_start (void)
3822 VEC_truncate (mips_multi_member, mips_multi_members, 0);
3823 mips_multi_num_insns = 0;
3826 /* Add a new, uninitialized member to the current multi-insn sequence. */
3828 static struct mips_multi_member *
3829 mips_multi_add (void)
3831 return VEC_safe_push (mips_multi_member, heap, mips_multi_members, 0);
3834 /* Add a normal insn with the given asm format to the current multi-insn
3835 sequence. The other arguments are a null-terminated list of operands. */
3838 mips_multi_add_insn (const char *format, ...)
3840 struct mips_multi_member *member;
3845 member = mips_multi_add ();
3846 member->is_label_p = false;
3847 member->format = format;
3848 va_start (ap, format);
3850 while ((op = va_arg (ap, rtx)))
3851 member->operands[i++] = op;
3853 mips_multi_num_insns++;
3856 /* Add the given label definition to the current multi-insn sequence.
3857 The definition should include the colon. */
3860 mips_multi_add_label (const char *label)
3862 struct mips_multi_member *member;
3864 member = mips_multi_add ();
3865 member->is_label_p = true;
3866 member->format = label;
3869 /* Return the index of the last member of the current multi-insn sequence. */
3872 mips_multi_last_index (void)
3874 return VEC_length (mips_multi_member, mips_multi_members) - 1;
3877 /* Add a copy of an existing instruction to the current multi-insn
3878 sequence. I is the index of the instruction that should be copied. */
3881 mips_multi_copy_insn (unsigned int i)
3883 struct mips_multi_member *member;
3885 member = mips_multi_add ();
3886 memcpy (member, VEC_index (mips_multi_member, mips_multi_members, i),
3888 gcc_assert (!member->is_label_p);
3891 /* Change the operand of an existing instruction in the current
3892 multi-insn sequence. I is the index of the instruction,
3893 OP is the index of the operand, and X is the new value. */
3896 mips_multi_set_operand (unsigned int i, unsigned int op, rtx x)
3898 VEC_index (mips_multi_member, mips_multi_members, i)->operands[op] = x;
3901 /* Write out the asm code for the current multi-insn sequence. */
3904 mips_multi_write (void)
3906 struct mips_multi_member *member;
3909 FOR_EACH_VEC_ELT (mips_multi_member, mips_multi_members, i, member)
3910 if (member->is_label_p)
3911 fprintf (asm_out_file, "%s\n", member->format);
3913 output_asm_insn (member->format, member->operands);
3916 /* Return one word of double-word value OP, taking into account the fixed
3917 endianness of certain registers. HIGH_P is true to select the high part,
3918 false to select the low part. */
3921 mips_subword (rtx op, bool high_p)
3923 unsigned int byte, offset;
3924 enum machine_mode mode;
3926 mode = GET_MODE (op);
3927 if (mode == VOIDmode)
3928 mode = TARGET_64BIT ? TImode : DImode;
3930 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
3931 byte = UNITS_PER_WORD;
3935 if (FP_REG_RTX_P (op))
3937 /* Paired FPRs are always ordered little-endian. */
3938 offset = (UNITS_PER_WORD < UNITS_PER_HWFPVALUE ? high_p : byte != 0);
3939 return gen_rtx_REG (word_mode, REGNO (op) + offset);
3943 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
3945 return simplify_gen_subreg (word_mode, op, mode, byte);
3948 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
3951 mips_split_64bit_move_p (rtx dest, rtx src)
3956 /* FPR-to-FPR moves can be done in a single instruction, if they're
3958 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
3961 /* Check for floating-point loads and stores. */
3962 if (ISA_HAS_LDC1_SDC1)
3964 if (FP_REG_RTX_P (dest) && MEM_P (src))
3966 if (FP_REG_RTX_P (src) && MEM_P (dest))
3972 /* Split a doubleword move from SRC to DEST. On 32-bit targets,
3973 this function handles 64-bit moves for which mips_split_64bit_move_p
3974 holds. For 64-bit targets, this function handles 128-bit moves. */
3977 mips_split_doubleword_move (rtx dest, rtx src)
3981 if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src))
3983 if (!TARGET_64BIT && GET_MODE (dest) == DImode)
3984 emit_insn (gen_move_doubleword_fprdi (dest, src));
3985 else if (!TARGET_64BIT && GET_MODE (dest) == DFmode)
3986 emit_insn (gen_move_doubleword_fprdf (dest, src));
3987 else if (!TARGET_64BIT && GET_MODE (dest) == V2SFmode)
3988 emit_insn (gen_move_doubleword_fprv2sf (dest, src));
3989 else if (!TARGET_64BIT && GET_MODE (dest) == V2SImode)
3990 emit_insn (gen_move_doubleword_fprv2si (dest, src));
3991 else if (!TARGET_64BIT && GET_MODE (dest) == V4HImode)
3992 emit_insn (gen_move_doubleword_fprv4hi (dest, src));
3993 else if (!TARGET_64BIT && GET_MODE (dest) == V8QImode)
3994 emit_insn (gen_move_doubleword_fprv8qi (dest, src));
3995 else if (TARGET_64BIT && GET_MODE (dest) == TFmode)
3996 emit_insn (gen_move_doubleword_fprtf (dest, src));
4000 else if (REG_P (dest) && REGNO (dest) == MD_REG_FIRST)
4002 low_dest = mips_subword (dest, false);
4003 mips_emit_move (low_dest, mips_subword (src, false));
4005 emit_insn (gen_mthidi_ti (dest, mips_subword (src, true), low_dest));
4007 emit_insn (gen_mthisi_di (dest, mips_subword (src, true), low_dest));
4009 else if (REG_P (src) && REGNO (src) == MD_REG_FIRST)
4011 mips_emit_move (mips_subword (dest, false), mips_subword (src, false));
4013 emit_insn (gen_mfhidi_ti (mips_subword (dest, true), src));
4015 emit_insn (gen_mfhisi_di (mips_subword (dest, true), src));
4019 /* The operation can be split into two normal moves. Decide in
4020 which order to do them. */
4021 low_dest = mips_subword (dest, false);
4022 if (REG_P (low_dest)
4023 && reg_overlap_mentioned_p (low_dest, src))
4025 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4026 mips_emit_move (low_dest, mips_subword (src, false));
4030 mips_emit_move (low_dest, mips_subword (src, false));
4031 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4036 /* Return the appropriate instructions to move SRC into DEST. Assume
4037 that SRC is operand 1 and DEST is operand 0. */
4040 mips_output_move (rtx dest, rtx src)
4042 enum rtx_code dest_code, src_code;
4043 enum machine_mode mode;
4044 enum mips_symbol_type symbol_type;
4047 dest_code = GET_CODE (dest);
4048 src_code = GET_CODE (src);
4049 mode = GET_MODE (dest);
4050 dbl_p = (GET_MODE_SIZE (mode) == 8);
4052 if (dbl_p && mips_split_64bit_move_p (dest, src))
4055 if ((src_code == REG && GP_REG_P (REGNO (src)))
4056 || (!TARGET_MIPS16 && src == CONST0_RTX (mode)))
4058 if (dest_code == REG)
4060 if (GP_REG_P (REGNO (dest)))
4061 return "move\t%0,%z1";
4063 /* Moves to HI are handled by special .md insns. */
4064 if (REGNO (dest) == LO_REGNUM)
4067 if (DSP_ACC_REG_P (REGNO (dest)))
4069 static char retval[] = "mt__\t%z1,%q0";
4071 retval[2] = reg_names[REGNO (dest)][4];
4072 retval[3] = reg_names[REGNO (dest)][5];
4076 if (FP_REG_P (REGNO (dest)))
4077 return dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
4079 if (ALL_COP_REG_P (REGNO (dest)))
4081 static char retval[] = "dmtc_\t%z1,%0";
4083 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4084 return dbl_p ? retval : retval + 1;
4087 if (dest_code == MEM)
4088 switch (GET_MODE_SIZE (mode))
4090 case 1: return "sb\t%z1,%0";
4091 case 2: return "sh\t%z1,%0";
4092 case 4: return "sw\t%z1,%0";
4093 case 8: return "sd\t%z1,%0";
4096 if (dest_code == REG && GP_REG_P (REGNO (dest)))
4098 if (src_code == REG)
4100 /* Moves from HI are handled by special .md insns. */
4101 if (REGNO (src) == LO_REGNUM)
4103 /* When generating VR4120 or VR4130 code, we use MACC and
4104 DMACC instead of MFLO. This avoids both the normal
4105 MIPS III HI/LO hazards and the errata related to
4108 return dbl_p ? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
4112 if (DSP_ACC_REG_P (REGNO (src)))
4114 static char retval[] = "mf__\t%0,%q1";
4116 retval[2] = reg_names[REGNO (src)][4];
4117 retval[3] = reg_names[REGNO (src)][5];
4121 if (FP_REG_P (REGNO (src)))
4122 return dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
4124 if (ALL_COP_REG_P (REGNO (src)))
4126 static char retval[] = "dmfc_\t%0,%1";
4128 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4129 return dbl_p ? retval : retval + 1;
4132 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
4133 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
4136 if (src_code == MEM)
4137 switch (GET_MODE_SIZE (mode))
4139 case 1: return "lbu\t%0,%1";
4140 case 2: return "lhu\t%0,%1";
4141 case 4: return "lw\t%0,%1";
4142 case 8: return "ld\t%0,%1";
4145 if (src_code == CONST_INT)
4147 /* Don't use the X format for the operand itself, because that
4148 will give out-of-range numbers for 64-bit hosts and 32-bit
4151 return "li\t%0,%1\t\t\t# %X1";
4153 if (SMALL_OPERAND_UNSIGNED (INTVAL (src)))
4156 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src)))
4160 if (src_code == HIGH)
4161 return TARGET_MIPS16 ? "#" : "lui\t%0,%h1";
4163 if (CONST_GP_P (src))
4164 return "move\t%0,%1";
4166 if (mips_symbolic_constant_p (src, SYMBOL_CONTEXT_LEA, &symbol_type)
4167 && mips_lo_relocs[symbol_type] != 0)
4169 /* A signed 16-bit constant formed by applying a relocation
4170 operator to a symbolic address. */
4171 gcc_assert (!mips_split_p[symbol_type]);
4172 return "li\t%0,%R1";
4175 if (symbolic_operand (src, VOIDmode))
4177 gcc_assert (TARGET_MIPS16
4178 ? TARGET_MIPS16_TEXT_LOADS
4179 : !TARGET_EXPLICIT_RELOCS);
4180 return dbl_p ? "dla\t%0,%1" : "la\t%0,%1";
4183 if (src_code == REG && FP_REG_P (REGNO (src)))
4185 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4187 if (GET_MODE (dest) == V2SFmode)
4188 return "mov.ps\t%0,%1";
4190 return dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1";
4193 if (dest_code == MEM)
4194 return dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0";
4196 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4198 if (src_code == MEM)
4199 return dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1";
4201 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
4203 static char retval[] = "l_c_\t%0,%1";
4205 retval[1] = (dbl_p ? 'd' : 'w');
4206 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4209 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
4211 static char retval[] = "s_c_\t%1,%0";
4213 retval[1] = (dbl_p ? 'd' : 'w');
4214 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4220 /* Return true if CMP1 is a suitable second operand for integer ordering
4221 test CODE. See also the *sCC patterns in mips.md. */
4224 mips_int_order_operand_ok_p (enum rtx_code code, rtx cmp1)
4230 return reg_or_0_operand (cmp1, VOIDmode);
4234 return !TARGET_MIPS16 && cmp1 == const1_rtx;
4238 return arith_operand (cmp1, VOIDmode);
4241 return sle_operand (cmp1, VOIDmode);
4244 return sleu_operand (cmp1, VOIDmode);
4251 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4252 integer ordering test *CODE, or if an equivalent combination can
4253 be formed by adjusting *CODE and *CMP1. When returning true, update
4254 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4258 mips_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1,
4259 enum machine_mode mode)
4261 HOST_WIDE_INT plus_one;
4263 if (mips_int_order_operand_ok_p (*code, *cmp1))
4266 if (CONST_INT_P (*cmp1))
4270 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4271 if (INTVAL (*cmp1) < plus_one)
4274 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4280 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4284 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4295 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4296 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4297 is nonnull, it's OK to set TARGET to the inverse of the result and
4298 flip *INVERT_PTR instead. */
4301 mips_emit_int_order_test (enum rtx_code code, bool *invert_ptr,
4302 rtx target, rtx cmp0, rtx cmp1)
4304 enum machine_mode mode;
4306 /* First see if there is a MIPS instruction that can do this operation.
4307 If not, try doing the same for the inverse operation. If that also
4308 fails, force CMP1 into a register and try again. */
4309 mode = GET_MODE (cmp0);
4310 if (mips_canonicalize_int_order_test (&code, &cmp1, mode))
4311 mips_emit_binary (code, target, cmp0, cmp1);
4314 enum rtx_code inv_code = reverse_condition (code);
4315 if (!mips_canonicalize_int_order_test (&inv_code, &cmp1, mode))
4317 cmp1 = force_reg (mode, cmp1);
4318 mips_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1);
4320 else if (invert_ptr == 0)
4324 inv_target = mips_force_binary (GET_MODE (target),
4325 inv_code, cmp0, cmp1);
4326 mips_emit_binary (XOR, target, inv_target, const1_rtx);
4330 *invert_ptr = !*invert_ptr;
4331 mips_emit_binary (inv_code, target, cmp0, cmp1);
4336 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4337 The register will have the same mode as CMP0. */
4340 mips_zero_if_equal (rtx cmp0, rtx cmp1)
4342 if (cmp1 == const0_rtx)
4345 if (uns_arith_operand (cmp1, VOIDmode))
4346 return expand_binop (GET_MODE (cmp0), xor_optab,
4347 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4349 return expand_binop (GET_MODE (cmp0), sub_optab,
4350 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4353 /* Convert *CODE into a code that can be used in a floating-point
4354 scc instruction (C.cond.fmt). Return true if the values of
4355 the condition code registers will be inverted, with 0 indicating
4356 that the condition holds. */
4359 mips_reversed_fp_cond (enum rtx_code *code)
4366 *code = reverse_condition_maybe_unordered (*code);
4374 /* Convert a comparison into something that can be used in a branch or
4375 conditional move. On entry, *OP0 and *OP1 are the values being
4376 compared and *CODE is the code used to compare them.
4378 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
4379 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
4380 otherwise any standard branch condition can be used. The standard branch
4383 - EQ or NE between two registers.
4384 - any comparison between a register and zero. */
4387 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
4392 if (GET_MODE_CLASS (GET_MODE (*op0)) == MODE_INT)
4394 if (!need_eq_ne_p && *op1 == const0_rtx)
4396 else if (*code == EQ || *code == NE)
4400 *op0 = mips_zero_if_equal (cmp_op0, cmp_op1);
4404 *op1 = force_reg (GET_MODE (cmp_op0), cmp_op1);
4408 /* The comparison needs a separate scc instruction. Store the
4409 result of the scc in *OP0 and compare it against zero. */
4410 bool invert = false;
4411 *op0 = gen_reg_rtx (GET_MODE (cmp_op0));
4412 mips_emit_int_order_test (*code, &invert, *op0, cmp_op0, cmp_op1);
4413 *code = (invert ? EQ : NE);
4417 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0)))
4419 *op0 = gen_rtx_REG (CCDSPmode, CCDSP_CC_REGNUM);
4420 mips_emit_binary (*code, *op0, cmp_op0, cmp_op1);
4426 enum rtx_code cmp_code;
4428 /* Floating-point tests use a separate C.cond.fmt comparison to
4429 set a condition code register. The branch or conditional move
4430 will then compare that register against zero.
4432 Set CMP_CODE to the code of the comparison instruction and
4433 *CODE to the code that the branch or move should use. */
4435 *code = mips_reversed_fp_cond (&cmp_code) ? EQ : NE;
4437 ? gen_reg_rtx (CCmode)
4438 : gen_rtx_REG (CCmode, FPSW_REGNUM));
4440 mips_emit_binary (cmp_code, *op0, cmp_op0, cmp_op1);
4444 /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2]
4445 and OPERAND[3]. Store the result in OPERANDS[0].
4447 On 64-bit targets, the mode of the comparison and target will always be
4448 SImode, thus possibly narrower than that of the comparison's operands. */
4451 mips_expand_scc (rtx operands[])
4453 rtx target = operands[0];
4454 enum rtx_code code = GET_CODE (operands[1]);
4455 rtx op0 = operands[2];
4456 rtx op1 = operands[3];
4458 gcc_assert (GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT);
4460 if (code == EQ || code == NE)
4463 && reg_imm10_operand (op1, GET_MODE (op1)))
4464 mips_emit_binary (code, target, op0, op1);
4467 rtx zie = mips_zero_if_equal (op0, op1);
4468 mips_emit_binary (code, target, zie, const0_rtx);
4472 mips_emit_int_order_test (code, 0, target, op0, op1);
4475 /* Compare OPERANDS[1] with OPERANDS[2] using comparison code
4476 CODE and jump to OPERANDS[3] if the condition holds. */
4479 mips_expand_conditional_branch (rtx *operands)
4481 enum rtx_code code = GET_CODE (operands[0]);
4482 rtx op0 = operands[1];
4483 rtx op1 = operands[2];
4486 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
4487 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
4488 emit_jump_insn (gen_condjump (condition, operands[3]));
4493 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
4494 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
4497 mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
4498 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
4503 reversed_p = mips_reversed_fp_cond (&cond);
4504 cmp_result = gen_reg_rtx (CCV2mode);
4505 emit_insn (gen_scc_ps (cmp_result,
4506 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
4508 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
4511 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
4515 /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0]
4516 if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
4519 mips_expand_conditional_move (rtx *operands)
4522 enum rtx_code code = GET_CODE (operands[1]);
4523 rtx op0 = XEXP (operands[1], 0);
4524 rtx op1 = XEXP (operands[1], 1);
4526 mips_emit_compare (&code, &op0, &op1, true);
4527 cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
4528 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
4529 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), cond,
4530 operands[2], operands[3])));
4533 /* Perform the comparison in COMPARISON, then trap if the condition holds. */
4536 mips_expand_conditional_trap (rtx comparison)
4539 enum machine_mode mode;
4542 /* MIPS conditional trap instructions don't have GT or LE flavors,
4543 so we must swap the operands and convert to LT and GE respectively. */
4544 code = GET_CODE (comparison);
4551 code = swap_condition (code);
4552 op0 = XEXP (comparison, 1);
4553 op1 = XEXP (comparison, 0);
4557 op0 = XEXP (comparison, 0);
4558 op1 = XEXP (comparison, 1);
4562 mode = GET_MODE (XEXP (comparison, 0));
4563 op0 = force_reg (mode, op0);
4564 if (!arith_operand (op1, mode))
4565 op1 = force_reg (mode, op1);
4567 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
4568 gen_rtx_fmt_ee (code, mode, op0, op1),
4572 /* Initialize *CUM for a call to a function of type FNTYPE. */
4575 mips_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype)
4577 memset (cum, 0, sizeof (*cum));
4578 cum->prototype = (fntype && prototype_p (fntype));
4579 cum->gp_reg_found = (cum->prototype && stdarg_p (fntype));
4582 /* Fill INFO with information about a single argument. CUM is the
4583 cumulative state for earlier arguments. MODE is the mode of this
4584 argument and TYPE is its type (if known). NAMED is true if this
4585 is a named (fixed) argument rather than a variable one. */
4588 mips_get_arg_info (struct mips_arg_info *info, const CUMULATIVE_ARGS *cum,
4589 enum machine_mode mode, const_tree type, bool named)
4591 bool doubleword_aligned_p;
4592 unsigned int num_bytes, num_words, max_regs;
4594 /* Work out the size of the argument. */
4595 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
4596 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4598 /* Decide whether it should go in a floating-point register, assuming
4599 one is free. Later code checks for availability.
4601 The checks against UNITS_PER_FPVALUE handle the soft-float and
4602 single-float cases. */
4606 /* The EABI conventions have traditionally been defined in terms
4607 of TYPE_MODE, regardless of the actual type. */
4608 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
4609 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4610 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4615 /* Only leading floating-point scalars are passed in
4616 floating-point registers. We also handle vector floats the same
4617 say, which is OK because they are not covered by the standard ABI. */
4618 info->fpr_p = (!cum->gp_reg_found
4619 && cum->arg_number < 2
4621 || SCALAR_FLOAT_TYPE_P (type)
4622 || VECTOR_FLOAT_TYPE_P (type))
4623 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4624 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4625 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4630 /* Scalar, complex and vector floating-point types are passed in
4631 floating-point registers, as long as this is a named rather
4632 than a variable argument. */
4633 info->fpr_p = (named
4634 && (type == 0 || FLOAT_TYPE_P (type))
4635 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4636 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4637 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4638 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
4640 /* ??? According to the ABI documentation, the real and imaginary
4641 parts of complex floats should be passed in individual registers.
4642 The real and imaginary parts of stack arguments are supposed
4643 to be contiguous and there should be an extra word of padding
4646 This has two problems. First, it makes it impossible to use a
4647 single "void *" va_list type, since register and stack arguments
4648 are passed differently. (At the time of writing, MIPSpro cannot
4649 handle complex float varargs correctly.) Second, it's unclear
4650 what should happen when there is only one register free.
4652 For now, we assume that named complex floats should go into FPRs
4653 if there are two FPRs free, otherwise they should be passed in the
4654 same way as a struct containing two floats. */
4656 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4657 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
4659 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
4660 info->fpr_p = false;
4670 /* See whether the argument has doubleword alignment. */
4671 doubleword_aligned_p = (mips_function_arg_boundary (mode, type)
4674 /* Set REG_OFFSET to the register count we're interested in.
4675 The EABI allocates the floating-point registers separately,
4676 but the other ABIs allocate them like integer registers. */
4677 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
4681 /* Advance to an even register if the argument is doubleword-aligned. */
4682 if (doubleword_aligned_p)
4683 info->reg_offset += info->reg_offset & 1;
4685 /* Work out the offset of a stack argument. */
4686 info->stack_offset = cum->stack_words;
4687 if (doubleword_aligned_p)
4688 info->stack_offset += info->stack_offset & 1;
4690 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
4692 /* Partition the argument between registers and stack. */
4693 info->reg_words = MIN (num_words, max_regs);
4694 info->stack_words = num_words - info->reg_words;
4697 /* INFO describes a register argument that has the normal format for the
4698 argument's mode. Return the register it uses, assuming that FPRs are
4699 available if HARD_FLOAT_P. */
4702 mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p)
4704 if (!info->fpr_p || !hard_float_p)
4705 return GP_ARG_FIRST + info->reg_offset;
4706 else if (mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info->reg_offset > 0)
4707 /* In o32, the second argument is always passed in $f14
4708 for TARGET_DOUBLE_FLOAT, regardless of whether the
4709 first argument was a word or doubleword. */
4710 return FP_ARG_FIRST + 2;
4712 return FP_ARG_FIRST + info->reg_offset;
4715 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
4718 mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
4720 return !TARGET_OLDABI;
4723 /* Implement TARGET_FUNCTION_ARG. */
4726 mips_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4727 const_tree type, bool named)
4729 struct mips_arg_info info;
4731 /* We will be called with a mode of VOIDmode after the last argument
4732 has been seen. Whatever we return will be passed to the call expander.
4733 If we need a MIPS16 fp_code, return a REG with the code stored as
4735 if (mode == VOIDmode)
4737 if (TARGET_MIPS16 && cum->fp_code != 0)
4738 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
4743 mips_get_arg_info (&info, cum, mode, type, named);
4745 /* Return straight away if the whole argument is passed on the stack. */
4746 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
4749 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
4750 contains a double in its entirety, then that 64-bit chunk is passed
4751 in a floating-point register. */
4753 && TARGET_HARD_FLOAT
4756 && TREE_CODE (type) == RECORD_TYPE
4757 && TYPE_SIZE_UNIT (type)
4758 && host_integerp (TYPE_SIZE_UNIT (type), 1))
4762 /* First check to see if there is any such field. */
4763 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
4764 if (TREE_CODE (field) == FIELD_DECL
4765 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
4766 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
4767 && host_integerp (bit_position (field), 0)
4768 && int_bit_position (field) % BITS_PER_WORD == 0)
4773 /* Now handle the special case by returning a PARALLEL
4774 indicating where each 64-bit chunk goes. INFO.REG_WORDS
4775 chunks are passed in registers. */
4777 HOST_WIDE_INT bitpos;
4780 /* assign_parms checks the mode of ENTRY_PARM, so we must
4781 use the actual mode here. */
4782 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
4785 field = TYPE_FIELDS (type);
4786 for (i = 0; i < info.reg_words; i++)
4790 for (; field; field = DECL_CHAIN (field))
4791 if (TREE_CODE (field) == FIELD_DECL
4792 && int_bit_position (field) >= bitpos)
4796 && int_bit_position (field) == bitpos
4797 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
4798 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
4799 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
4801 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
4804 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4805 GEN_INT (bitpos / BITS_PER_UNIT));
4807 bitpos += BITS_PER_WORD;
4813 /* Handle the n32/n64 conventions for passing complex floating-point
4814 arguments in FPR pairs. The real part goes in the lower register
4815 and the imaginary part goes in the upper register. */
4818 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4821 enum machine_mode inner;
4824 inner = GET_MODE_INNER (mode);
4825 regno = FP_ARG_FIRST + info.reg_offset;
4826 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
4828 /* Real part in registers, imaginary part on stack. */
4829 gcc_assert (info.stack_words == info.reg_words);
4830 return gen_rtx_REG (inner, regno);
4834 gcc_assert (info.stack_words == 0);
4835 real = gen_rtx_EXPR_LIST (VOIDmode,
4836 gen_rtx_REG (inner, regno),
4838 imag = gen_rtx_EXPR_LIST (VOIDmode,
4840 regno + info.reg_words / 2),
4841 GEN_INT (GET_MODE_SIZE (inner)));
4842 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
4846 return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT));
4849 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
4852 mips_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4853 const_tree type, bool named)
4855 struct mips_arg_info info;
4857 mips_get_arg_info (&info, cum, mode, type, named);
4860 cum->gp_reg_found = true;
4862 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
4863 an explanation of what this code does. It assumes that we're using
4864 either the o32 or the o64 ABI, both of which pass at most 2 arguments
4866 if (cum->arg_number < 2 && info.fpr_p)
4867 cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2);
4869 /* Advance the register count. This has the effect of setting
4870 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
4871 argument required us to skip the final GPR and pass the whole
4872 argument on the stack. */
4873 if (mips_abi != ABI_EABI || !info.fpr_p)
4874 cum->num_gprs = info.reg_offset + info.reg_words;
4875 else if (info.reg_words > 0)
4876 cum->num_fprs += MAX_FPRS_PER_FMT;
4878 /* Advance the stack word count. */
4879 if (info.stack_words > 0)
4880 cum->stack_words = info.stack_offset + info.stack_words;
4885 /* Implement TARGET_ARG_PARTIAL_BYTES. */
4888 mips_arg_partial_bytes (CUMULATIVE_ARGS *cum,
4889 enum machine_mode mode, tree type, bool named)
4891 struct mips_arg_info info;
4893 mips_get_arg_info (&info, cum, mode, type, named);
4894 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
4897 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
4898 least PARM_BOUNDARY bits of alignment, but will be given anything up
4899 to STACK_BOUNDARY bits if the type requires it. */
4902 mips_function_arg_boundary (enum machine_mode mode, const_tree type)
4904 unsigned int alignment;
4906 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
4907 if (alignment < PARM_BOUNDARY)
4908 alignment = PARM_BOUNDARY;
4909 if (alignment > STACK_BOUNDARY)
4910 alignment = STACK_BOUNDARY;
4914 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
4915 upward rather than downward. In other words, return true if the
4916 first byte of the stack slot has useful data, false if the last
4920 mips_pad_arg_upward (enum machine_mode mode, const_tree type)
4922 /* On little-endian targets, the first byte of every stack argument
4923 is passed in the first byte of the stack slot. */
4924 if (!BYTES_BIG_ENDIAN)
4927 /* Otherwise, integral types are padded downward: the last byte of a
4928 stack argument is passed in the last byte of the stack slot. */
4930 ? (INTEGRAL_TYPE_P (type)
4931 || POINTER_TYPE_P (type)
4932 || FIXED_POINT_TYPE_P (type))
4933 : (SCALAR_INT_MODE_P (mode)
4934 || ALL_SCALAR_FIXED_POINT_MODE_P (mode)))
4937 /* Big-endian o64 pads floating-point arguments downward. */
4938 if (mips_abi == ABI_O64)
4939 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4942 /* Other types are padded upward for o32, o64, n32 and n64. */
4943 if (mips_abi != ABI_EABI)
4946 /* Arguments smaller than a stack slot are padded downward. */
4947 if (mode != BLKmode)
4948 return GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY;
4950 return int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT);
4953 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
4954 if the least significant byte of the register has useful data. Return
4955 the opposite if the most significant byte does. */
4958 mips_pad_reg_upward (enum machine_mode mode, tree type)
4960 /* No shifting is required for floating-point arguments. */
4961 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4962 return !BYTES_BIG_ENDIAN;
4964 /* Otherwise, apply the same padding to register arguments as we do
4965 to stack arguments. */
4966 return mips_pad_arg_upward (mode, type);
4969 /* Return nonzero when an argument must be passed by reference. */
4972 mips_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
4973 enum machine_mode mode, const_tree type,
4974 bool named ATTRIBUTE_UNUSED)
4976 if (mips_abi == ABI_EABI)
4980 /* ??? How should SCmode be handled? */
4981 if (mode == DImode || mode == DFmode
4982 || mode == DQmode || mode == UDQmode
4983 || mode == DAmode || mode == UDAmode)
4986 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
4987 return size == -1 || size > UNITS_PER_WORD;
4991 /* If we have a variable-sized parameter, we have no choice. */
4992 return targetm.calls.must_pass_in_stack (mode, type);
4996 /* Implement TARGET_CALLEE_COPIES. */
4999 mips_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5000 enum machine_mode mode ATTRIBUTE_UNUSED,
5001 const_tree type ATTRIBUTE_UNUSED, bool named)
5003 return mips_abi == ABI_EABI && named;
5006 /* See whether VALTYPE is a record whose fields should be returned in
5007 floating-point registers. If so, return the number of fields and
5008 list them in FIELDS (which should have two elements). Return 0
5011 For n32 & n64, a structure with one or two fields is returned in
5012 floating-point registers as long as every field has a floating-point
5016 mips_fpr_return_fields (const_tree valtype, tree *fields)
5024 if (TREE_CODE (valtype) != RECORD_TYPE)
5028 for (field = TYPE_FIELDS (valtype); field != 0; field = DECL_CHAIN (field))
5030 if (TREE_CODE (field) != FIELD_DECL)
5033 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)))
5039 fields[i++] = field;
5044 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
5045 a value in the most significant part of $2/$3 if:
5047 - the target is big-endian;
5049 - the value has a structure or union type (we generalize this to
5050 cover aggregates from other languages too); and
5052 - the structure is not returned in floating-point registers. */
5055 mips_return_in_msb (const_tree valtype)
5059 return (TARGET_NEWABI
5060 && TARGET_BIG_ENDIAN
5061 && AGGREGATE_TYPE_P (valtype)
5062 && mips_fpr_return_fields (valtype, fields) == 0);
5065 /* Return true if the function return value MODE will get returned in a
5066 floating-point register. */
5069 mips_return_mode_in_fpr_p (enum machine_mode mode)
5071 return ((GET_MODE_CLASS (mode) == MODE_FLOAT
5072 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT
5073 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5074 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE);
5077 /* Return the representation of an FPR return register when the
5078 value being returned in FP_RETURN has mode VALUE_MODE and the
5079 return type itself has mode TYPE_MODE. On NewABI targets,
5080 the two modes may be different for structures like:
5082 struct __attribute__((packed)) foo { float f; }
5084 where we return the SFmode value of "f" in FP_RETURN, but where
5085 the structure itself has mode BLKmode. */
5088 mips_return_fpr_single (enum machine_mode type_mode,
5089 enum machine_mode value_mode)
5093 x = gen_rtx_REG (value_mode, FP_RETURN);
5094 if (type_mode != value_mode)
5096 x = gen_rtx_EXPR_LIST (VOIDmode, x, const0_rtx);
5097 x = gen_rtx_PARALLEL (type_mode, gen_rtvec (1, x));
5102 /* Return a composite value in a pair of floating-point registers.
5103 MODE1 and OFFSET1 are the mode and byte offset for the first value,
5104 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
5107 For n32 & n64, $f0 always holds the first value and $f2 the second.
5108 Otherwise the values are packed together as closely as possible. */
5111 mips_return_fpr_pair (enum machine_mode mode,
5112 enum machine_mode mode1, HOST_WIDE_INT offset1,
5113 enum machine_mode mode2, HOST_WIDE_INT offset2)
5117 inc = (TARGET_NEWABI ? 2 : MAX_FPRS_PER_FMT);
5118 return gen_rtx_PARALLEL
5121 gen_rtx_EXPR_LIST (VOIDmode,
5122 gen_rtx_REG (mode1, FP_RETURN),
5124 gen_rtx_EXPR_LIST (VOIDmode,
5125 gen_rtx_REG (mode2, FP_RETURN + inc),
5126 GEN_INT (offset2))));
5130 /* Implement TARGET_FUNCTION_VALUE and TARGET_LIBCALL_VALUE.
5131 For normal calls, VALTYPE is the return type and MODE is VOIDmode.
5132 For libcalls, VALTYPE is null and MODE is the mode of the return value. */
5135 mips_function_value_1 (const_tree valtype, const_tree fn_decl_or_type,
5136 enum machine_mode mode)
5144 if (fn_decl_or_type && DECL_P (fn_decl_or_type))
5145 func = fn_decl_or_type;
5149 mode = TYPE_MODE (valtype);
5150 unsigned_p = TYPE_UNSIGNED (valtype);
5152 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
5153 return values, promote the mode here too. */
5154 mode = promote_function_mode (valtype, mode, &unsigned_p, func, 1);
5156 /* Handle structures whose fields are returned in $f0/$f2. */
5157 switch (mips_fpr_return_fields (valtype, fields))
5160 return mips_return_fpr_single (mode,
5161 TYPE_MODE (TREE_TYPE (fields[0])));
5164 return mips_return_fpr_pair (mode,
5165 TYPE_MODE (TREE_TYPE (fields[0])),
5166 int_byte_position (fields[0]),
5167 TYPE_MODE (TREE_TYPE (fields[1])),
5168 int_byte_position (fields[1]));
5171 /* If a value is passed in the most significant part of a register, see
5172 whether we have to round the mode up to a whole number of words. */
5173 if (mips_return_in_msb (valtype))
5175 HOST_WIDE_INT size = int_size_in_bytes (valtype);
5176 if (size % UNITS_PER_WORD != 0)
5178 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
5179 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
5183 /* For EABI, the class of return register depends entirely on MODE.
5184 For example, "struct { some_type x; }" and "union { some_type x; }"
5185 are returned in the same way as a bare "some_type" would be.
5186 Other ABIs only use FPRs for scalar, complex or vector types. */
5187 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
5188 return gen_rtx_REG (mode, GP_RETURN);
5193 /* Handle long doubles for n32 & n64. */
5195 return mips_return_fpr_pair (mode,
5197 DImode, GET_MODE_SIZE (mode) / 2);
5199 if (mips_return_mode_in_fpr_p (mode))
5201 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5202 return mips_return_fpr_pair (mode,
5203 GET_MODE_INNER (mode), 0,
5204 GET_MODE_INNER (mode),
5205 GET_MODE_SIZE (mode) / 2);
5207 return gen_rtx_REG (mode, FP_RETURN);
5211 return gen_rtx_REG (mode, GP_RETURN);
5214 /* Implement TARGET_FUNCTION_VALUE. */
5217 mips_function_value (const_tree valtype, const_tree fn_decl_or_type,
5218 bool outgoing ATTRIBUTE_UNUSED)
5220 return mips_function_value_1 (valtype, fn_decl_or_type, VOIDmode);
5223 /* Implement TARGET_LIBCALL_VALUE. */
5226 mips_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
5228 return mips_function_value_1 (NULL_TREE, NULL_TREE, mode);
5231 /* Implement TARGET_FUNCTION_VALUE_REGNO_P.
5233 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
5234 Currently, R2 and F0 are only implemented here (C has no complex type). */
5237 mips_function_value_regno_p (const unsigned int regno)
5239 if (regno == GP_RETURN
5240 || regno == FP_RETURN
5241 || (LONG_DOUBLE_TYPE_SIZE == 128
5242 && FP_RETURN != GP_RETURN
5243 && regno == FP_RETURN + 2))
5249 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
5250 all BLKmode objects are returned in memory. Under the n32, n64
5251 and embedded ABIs, small structures are returned in a register.
5252 Objects with varying size must still be returned in memory, of
5256 mips_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
5258 return (TARGET_OLDABI
5259 ? TYPE_MODE (type) == BLKmode
5260 : !IN_RANGE (int_size_in_bytes (type), 0, 2 * UNITS_PER_WORD));
5263 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
5266 mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5267 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5270 CUMULATIVE_ARGS local_cum;
5271 int gp_saved, fp_saved;
5273 /* The caller has advanced CUM up to, but not beyond, the last named
5274 argument. Advance a local copy of CUM past the last "real" named
5275 argument, to find out how many registers are left over. */
5277 mips_function_arg_advance (&local_cum, mode, type, true);
5279 /* Found out how many registers we need to save. */
5280 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
5281 fp_saved = (EABI_FLOAT_VARARGS_P
5282 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
5291 ptr = plus_constant (virtual_incoming_args_rtx,
5292 REG_PARM_STACK_SPACE (cfun->decl)
5293 - gp_saved * UNITS_PER_WORD);
5294 mem = gen_frame_mem (BLKmode, ptr);
5295 set_mem_alias_set (mem, get_varargs_alias_set ());
5297 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
5302 /* We can't use move_block_from_reg, because it will use
5304 enum machine_mode mode;
5307 /* Set OFF to the offset from virtual_incoming_args_rtx of
5308 the first float register. The FP save area lies below
5309 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
5310 off = (-gp_saved * UNITS_PER_WORD) & -UNITS_PER_FPVALUE;
5311 off -= fp_saved * UNITS_PER_FPREG;
5313 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
5315 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS;
5316 i += MAX_FPRS_PER_FMT)
5320 ptr = plus_constant (virtual_incoming_args_rtx, off);
5321 mem = gen_frame_mem (mode, ptr);
5322 set_mem_alias_set (mem, get_varargs_alias_set ());
5323 mips_emit_move (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
5324 off += UNITS_PER_HWFPVALUE;
5328 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
5329 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
5330 + fp_saved * UNITS_PER_FPREG);
5333 /* Implement TARGET_BUILTIN_VA_LIST. */
5336 mips_build_builtin_va_list (void)
5338 if (EABI_FLOAT_VARARGS_P)
5340 /* We keep 3 pointers, and two offsets.
5342 Two pointers are to the overflow area, which starts at the CFA.
5343 One of these is constant, for addressing into the GPR save area
5344 below it. The other is advanced up the stack through the
5347 The third pointer is to the bottom of the GPR save area.
5348 Since the FPR save area is just below it, we can address
5349 FPR slots off this pointer.
5351 We also keep two one-byte offsets, which are to be subtracted
5352 from the constant pointers to yield addresses in the GPR and
5353 FPR save areas. These are downcounted as float or non-float
5354 arguments are used, and when they get to zero, the argument
5355 must be obtained from the overflow region. */
5356 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
5359 record = lang_hooks.types.make_type (RECORD_TYPE);
5361 f_ovfl = build_decl (BUILTINS_LOCATION,
5362 FIELD_DECL, get_identifier ("__overflow_argptr"),
5364 f_gtop = build_decl (BUILTINS_LOCATION,
5365 FIELD_DECL, get_identifier ("__gpr_top"),
5367 f_ftop = build_decl (BUILTINS_LOCATION,
5368 FIELD_DECL, get_identifier ("__fpr_top"),
5370 f_goff = build_decl (BUILTINS_LOCATION,
5371 FIELD_DECL, get_identifier ("__gpr_offset"),
5372 unsigned_char_type_node);
5373 f_foff = build_decl (BUILTINS_LOCATION,
5374 FIELD_DECL, get_identifier ("__fpr_offset"),
5375 unsigned_char_type_node);
5376 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
5377 warn on every user file. */
5378 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
5379 array = build_array_type (unsigned_char_type_node,
5380 build_index_type (index));
5381 f_res = build_decl (BUILTINS_LOCATION,
5382 FIELD_DECL, get_identifier ("__reserved"), array);
5384 DECL_FIELD_CONTEXT (f_ovfl) = record;
5385 DECL_FIELD_CONTEXT (f_gtop) = record;
5386 DECL_FIELD_CONTEXT (f_ftop) = record;
5387 DECL_FIELD_CONTEXT (f_goff) = record;
5388 DECL_FIELD_CONTEXT (f_foff) = record;
5389 DECL_FIELD_CONTEXT (f_res) = record;
5391 TYPE_FIELDS (record) = f_ovfl;
5392 DECL_CHAIN (f_ovfl) = f_gtop;
5393 DECL_CHAIN (f_gtop) = f_ftop;
5394 DECL_CHAIN (f_ftop) = f_goff;
5395 DECL_CHAIN (f_goff) = f_foff;
5396 DECL_CHAIN (f_foff) = f_res;
5398 layout_type (record);
5401 else if (TARGET_IRIX6)
5402 /* On IRIX 6, this type is 'char *'. */
5403 return build_pointer_type (char_type_node);
5405 /* Otherwise, we use 'void *'. */
5406 return ptr_type_node;
5409 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
5412 mips_va_start (tree valist, rtx nextarg)
5414 if (EABI_FLOAT_VARARGS_P)
5416 const CUMULATIVE_ARGS *cum;
5417 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5418 tree ovfl, gtop, ftop, goff, foff;
5420 int gpr_save_area_size;
5421 int fpr_save_area_size;
5424 cum = &crtl->args.info;
5426 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
5428 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
5430 f_ovfl = TYPE_FIELDS (va_list_type_node);
5431 f_gtop = DECL_CHAIN (f_ovfl);
5432 f_ftop = DECL_CHAIN (f_gtop);
5433 f_goff = DECL_CHAIN (f_ftop);
5434 f_foff = DECL_CHAIN (f_goff);
5436 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5438 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
5440 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
5442 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
5444 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
5447 /* Emit code to initialize OVFL, which points to the next varargs
5448 stack argument. CUM->STACK_WORDS gives the number of stack
5449 words used by named arguments. */
5450 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
5451 if (cum->stack_words > 0)
5452 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl), t,
5453 size_int (cum->stack_words * UNITS_PER_WORD));
5454 t = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
5455 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5457 /* Emit code to initialize GTOP, the top of the GPR save area. */
5458 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
5459 t = build2 (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
5460 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5462 /* Emit code to initialize FTOP, the top of the FPR save area.
5463 This address is gpr_save_area_bytes below GTOP, rounded
5464 down to the next fp-aligned boundary. */
5465 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
5466 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
5467 fpr_offset &= -UNITS_PER_FPVALUE;
5469 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ftop), t,
5470 size_int (-fpr_offset));
5471 t = build2 (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
5472 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5474 /* Emit code to initialize GOFF, the offset from GTOP of the
5475 next GPR argument. */
5476 t = build2 (MODIFY_EXPR, TREE_TYPE (goff), goff,
5477 build_int_cst (TREE_TYPE (goff), gpr_save_area_size));
5478 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5480 /* Likewise emit code to initialize FOFF, the offset from FTOP
5481 of the next FPR argument. */
5482 t = build2 (MODIFY_EXPR, TREE_TYPE (foff), foff,
5483 build_int_cst (TREE_TYPE (foff), fpr_save_area_size));
5484 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5488 nextarg = plus_constant (nextarg, -cfun->machine->varargs_size);
5489 std_expand_builtin_va_start (valist, nextarg);
5493 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
5496 mips_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
5502 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
5504 type = build_pointer_type (type);
5506 if (!EABI_FLOAT_VARARGS_P)
5507 addr = std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5510 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5511 tree ovfl, top, off, align;
5512 HOST_WIDE_INT size, rsize, osize;
5515 f_ovfl = TYPE_FIELDS (va_list_type_node);
5516 f_gtop = DECL_CHAIN (f_ovfl);
5517 f_ftop = DECL_CHAIN (f_gtop);
5518 f_goff = DECL_CHAIN (f_ftop);
5519 f_foff = DECL_CHAIN (f_goff);
5523 TOP be the top of the GPR or FPR save area;
5524 OFF be the offset from TOP of the next register;
5525 ADDR_RTX be the address of the argument;
5526 SIZE be the number of bytes in the argument type;
5527 RSIZE be the number of bytes used to store the argument
5528 when it's in the register save area; and
5529 OSIZE be the number of bytes used to store it when it's
5530 in the stack overflow area.
5532 The code we want is:
5534 1: off &= -rsize; // round down
5537 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
5542 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
5543 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
5547 [1] and [9] can sometimes be optimized away. */
5549 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5551 size = int_size_in_bytes (type);
5553 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
5554 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
5556 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop),
5557 unshare_expr (valist), f_ftop, NULL_TREE);
5558 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff),
5559 unshare_expr (valist), f_foff, NULL_TREE);
5561 /* When va_start saves FPR arguments to the stack, each slot
5562 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
5563 argument's precision. */
5564 rsize = UNITS_PER_HWFPVALUE;
5566 /* Overflow arguments are padded to UNITS_PER_WORD bytes
5567 (= PARM_BOUNDARY bits). This can be different from RSIZE
5570 (1) On 32-bit targets when TYPE is a structure such as:
5572 struct s { float f; };
5574 Such structures are passed in paired FPRs, so RSIZE
5575 will be 8 bytes. However, the structure only takes
5576 up 4 bytes of memory, so OSIZE will only be 4.
5578 (2) In combinations such as -mgp64 -msingle-float
5579 -fshort-double. Doubles passed in registers will then take
5580 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
5581 stack take up UNITS_PER_WORD bytes. */
5582 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
5586 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop),
5587 unshare_expr (valist), f_gtop, NULL_TREE);
5588 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff),
5589 unshare_expr (valist), f_goff, NULL_TREE);
5590 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
5591 if (rsize > UNITS_PER_WORD)
5593 /* [1] Emit code for: off &= -rsize. */
5594 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), unshare_expr (off),
5595 build_int_cst (TREE_TYPE (off), -rsize));
5596 gimplify_assign (unshare_expr (off), t, pre_p);
5601 /* [2] Emit code to branch if off == 0. */
5602 t = build2 (NE_EXPR, boolean_type_node, off,
5603 build_int_cst (TREE_TYPE (off), 0));
5604 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
5606 /* [5] Emit code for: off -= rsize. We do this as a form of
5607 post-decrement not available to C. */
5608 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
5609 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
5611 /* [4] Emit code for:
5612 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
5613 t = fold_convert (sizetype, t);
5614 t = fold_build1 (NEGATE_EXPR, sizetype, t);
5615 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (top), top, t);
5616 if (BYTES_BIG_ENDIAN && rsize > size)
5618 u = size_int (rsize - size);
5619 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
5621 COND_EXPR_THEN (addr) = t;
5623 if (osize > UNITS_PER_WORD)
5625 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
5626 u = size_int (osize - 1);
5627 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl),
5628 unshare_expr (ovfl), u);
5629 t = fold_convert (sizetype, t);
5630 u = size_int (-osize);
5631 t = build2 (BIT_AND_EXPR, sizetype, t, u);
5632 t = fold_convert (TREE_TYPE (ovfl), t);
5633 align = build2 (MODIFY_EXPR, TREE_TYPE (ovfl),
5634 unshare_expr (ovfl), t);
5639 /* [10, 11] Emit code for:
5640 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
5642 u = fold_convert (TREE_TYPE (ovfl), build_int_cst (NULL_TREE, osize));
5643 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
5644 if (BYTES_BIG_ENDIAN && osize > size)
5646 u = size_int (osize - size);
5647 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
5650 /* String [9] and [10, 11] together. */
5652 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
5653 COND_EXPR_ELSE (addr) = t;
5655 addr = fold_convert (build_pointer_type (type), addr);
5656 addr = build_va_arg_indirect_ref (addr);
5660 addr = build_va_arg_indirect_ref (addr);
5665 /* Start a definition of function NAME. MIPS16_P indicates whether the
5666 function contains MIPS16 code. */
5669 mips_start_function_definition (const char *name, bool mips16_p)
5672 fprintf (asm_out_file, "\t.set\tmips16\n");
5674 fprintf (asm_out_file, "\t.set\tnomips16\n");
5676 if (!flag_inhibit_size_directive)
5678 fputs ("\t.ent\t", asm_out_file);
5679 assemble_name (asm_out_file, name);
5680 fputs ("\n", asm_out_file);
5683 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, name, "function");
5685 /* Start the definition proper. */
5686 assemble_name (asm_out_file, name);
5687 fputs (":\n", asm_out_file);
5690 /* End a function definition started by mips_start_function_definition. */
5693 mips_end_function_definition (const char *name)
5695 if (!flag_inhibit_size_directive)
5697 fputs ("\t.end\t", asm_out_file);
5698 assemble_name (asm_out_file, name);
5699 fputs ("\n", asm_out_file);
5703 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
5706 mips_ok_for_lazy_binding_p (rtx x)
5708 return (TARGET_USE_GOT
5709 && GET_CODE (x) == SYMBOL_REF
5710 && !SYMBOL_REF_BIND_NOW_P (x)
5711 && !mips_symbol_binds_local_p (x));
5714 /* Load function address ADDR into register DEST. TYPE is as for
5715 mips_expand_call. Return true if we used an explicit lazy-binding
5719 mips_load_call_address (enum mips_call_type type, rtx dest, rtx addr)
5721 /* If we're generating PIC, and this call is to a global function,
5722 try to allow its address to be resolved lazily. This isn't
5723 possible for sibcalls when $gp is call-saved because the value
5724 of $gp on entry to the stub would be our caller's gp, not ours. */
5725 if (TARGET_EXPLICIT_RELOCS
5726 && !(type == MIPS_CALL_SIBCALL && TARGET_CALL_SAVED_GP)
5727 && mips_ok_for_lazy_binding_p (addr))
5729 addr = mips_got_load (dest, addr, SYMBOL_GOTOFF_CALL);
5730 emit_insn (gen_rtx_SET (VOIDmode, dest, addr));
5735 mips_emit_move (dest, addr);
5740 /* Each locally-defined hard-float MIPS16 function has a local symbol
5741 associated with it. This hash table maps the function symbol (FUNC)
5742 to the local symbol (LOCAL). */
5743 struct GTY(()) mips16_local_alias {
5747 static GTY ((param_is (struct mips16_local_alias))) htab_t mips16_local_aliases;
5749 /* Hash table callbacks for mips16_local_aliases. */
5752 mips16_local_aliases_hash (const void *entry)
5754 const struct mips16_local_alias *alias;
5756 alias = (const struct mips16_local_alias *) entry;
5757 return htab_hash_string (XSTR (alias->func, 0));
5761 mips16_local_aliases_eq (const void *entry1, const void *entry2)
5763 const struct mips16_local_alias *alias1, *alias2;
5765 alias1 = (const struct mips16_local_alias *) entry1;
5766 alias2 = (const struct mips16_local_alias *) entry2;
5767 return rtx_equal_p (alias1->func, alias2->func);
5770 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
5771 Return a local alias for it, creating a new one if necessary. */
5774 mips16_local_alias (rtx func)
5776 struct mips16_local_alias *alias, tmp_alias;
5779 /* Create the hash table if this is the first call. */
5780 if (mips16_local_aliases == NULL)
5781 mips16_local_aliases = htab_create_ggc (37, mips16_local_aliases_hash,
5782 mips16_local_aliases_eq, NULL);
5784 /* Look up the function symbol, creating a new entry if need be. */
5785 tmp_alias.func = func;
5786 slot = htab_find_slot (mips16_local_aliases, &tmp_alias, INSERT);
5787 gcc_assert (slot != NULL);
5789 alias = (struct mips16_local_alias *) *slot;
5792 const char *func_name, *local_name;
5795 /* Create a new SYMBOL_REF for the local symbol. The choice of
5796 __fn_local_* is based on the __fn_stub_* names that we've
5797 traditionally used for the non-MIPS16 stub. */
5798 func_name = targetm.strip_name_encoding (XSTR (func, 0));
5799 local_name = ACONCAT (("__fn_local_", func_name, NULL));
5800 local = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (local_name));
5801 SYMBOL_REF_FLAGS (local) = SYMBOL_REF_FLAGS (func) | SYMBOL_FLAG_LOCAL;
5803 /* Create a new structure to represent the mapping. */
5804 alias = ggc_alloc_mips16_local_alias ();
5806 alias->local = local;
5809 return alias->local;
5812 /* A chained list of functions for which mips16_build_call_stub has already
5813 generated a stub. NAME is the name of the function and FP_RET_P is true
5814 if the function returns a value in floating-point registers. */
5815 struct mips16_stub {
5816 struct mips16_stub *next;
5820 static struct mips16_stub *mips16_stubs;
5822 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
5825 mips16_stub_function (const char *name)
5829 x = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
5830 SYMBOL_REF_FLAGS (x) |= (SYMBOL_FLAG_EXTERNAL | SYMBOL_FLAG_FUNCTION);
5834 /* Return the two-character string that identifies floating-point
5835 return mode MODE in the name of a MIPS16 function stub. */
5838 mips16_call_stub_mode_suffix (enum machine_mode mode)
5842 else if (mode == DFmode)
5844 else if (mode == SCmode)
5846 else if (mode == DCmode)
5848 else if (mode == V2SFmode)
5854 /* Write instructions to move a 32-bit value between general register
5855 GPREG and floating-point register FPREG. DIRECTION is 't' to move
5856 from GPREG to FPREG and 'f' to move in the opposite direction. */
5859 mips_output_32bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
5861 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5862 reg_names[gpreg], reg_names[fpreg]);
5865 /* Likewise for 64-bit values. */
5868 mips_output_64bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
5871 fprintf (asm_out_file, "\tdm%cc1\t%s,%s\n", direction,
5872 reg_names[gpreg], reg_names[fpreg]);
5873 else if (TARGET_FLOAT64)
5875 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5876 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
5877 fprintf (asm_out_file, "\tm%chc1\t%s,%s\n", direction,
5878 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg]);
5882 /* Move the least-significant word. */
5883 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5884 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
5885 /* ...then the most significant word. */
5886 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5887 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg + 1]);
5891 /* Write out code to move floating-point arguments into or out of
5892 general registers. FP_CODE is the code describing which arguments
5893 are present (see the comment above the definition of CUMULATIVE_ARGS
5894 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
5897 mips_output_args_xfer (int fp_code, char direction)
5899 unsigned int gparg, fparg, f;
5900 CUMULATIVE_ARGS cum;
5902 /* This code only works for o32 and o64. */
5903 gcc_assert (TARGET_OLDABI);
5905 mips_init_cumulative_args (&cum, NULL);
5907 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
5909 enum machine_mode mode;
5910 struct mips_arg_info info;
5914 else if ((f & 3) == 2)
5919 mips_get_arg_info (&info, &cum, mode, NULL, true);
5920 gparg = mips_arg_regno (&info, false);
5921 fparg = mips_arg_regno (&info, true);
5924 mips_output_32bit_xfer (direction, gparg, fparg);
5926 mips_output_64bit_xfer (direction, gparg, fparg);
5928 mips_function_arg_advance (&cum, mode, NULL, true);
5932 /* Write a MIPS16 stub for the current function. This stub is used
5933 for functions which take arguments in the floating-point registers.
5934 It is normal-mode code that moves the floating-point arguments
5935 into the general registers and then jumps to the MIPS16 code. */
5938 mips16_build_function_stub (void)
5940 const char *fnname, *alias_name, *separator;
5941 char *secname, *stubname;
5946 /* Create the name of the stub, and its unique section. */
5947 symbol = XEXP (DECL_RTL (current_function_decl), 0);
5948 alias = mips16_local_alias (symbol);
5950 fnname = targetm.strip_name_encoding (XSTR (symbol, 0));
5951 alias_name = targetm.strip_name_encoding (XSTR (alias, 0));
5952 secname = ACONCAT ((".mips16.fn.", fnname, NULL));
5953 stubname = ACONCAT (("__fn_stub_", fnname, NULL));
5955 /* Build a decl for the stub. */
5956 stubdecl = build_decl (BUILTINS_LOCATION,
5957 FUNCTION_DECL, get_identifier (stubname),
5958 build_function_type_list (void_type_node, NULL_TREE));
5959 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
5960 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
5961 RESULT_DECL, NULL_TREE, void_type_node);
5963 /* Output a comment. */
5964 fprintf (asm_out_file, "\t# Stub function for %s (",
5965 current_function_name ());
5967 for (f = (unsigned int) crtl->args.info.fp_code; f != 0; f >>= 2)
5969 fprintf (asm_out_file, "%s%s", separator,
5970 (f & 3) == 1 ? "float" : "double");
5973 fprintf (asm_out_file, ")\n");
5975 /* Start the function definition. */
5976 assemble_start_function (stubdecl, stubname);
5977 mips_start_function_definition (stubname, false);
5979 /* If generating pic2 code, either set up the global pointer or
5981 if (TARGET_ABICALLS_PIC2)
5983 if (TARGET_ABSOLUTE_ABICALLS)
5984 fprintf (asm_out_file, "\t.option\tpic0\n");
5987 output_asm_insn ("%(.cpload\t%^%)", NULL);
5988 /* Emit an R_MIPS_NONE relocation to tell the linker what the
5989 target function is. Use a local GOT access when loading the
5990 symbol, to cut down on the number of unnecessary GOT entries
5991 for stubs that aren't needed. */
5992 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol);
5997 /* Load the address of the MIPS16 function into $25. Do this first so
5998 that targets with coprocessor interlocks can use an MFC1 to fill the
6000 output_asm_insn ("la\t%^,%0", &symbol);
6002 /* Move the arguments from floating-point registers to general registers. */
6003 mips_output_args_xfer (crtl->args.info.fp_code, 'f');
6005 /* Jump to the MIPS16 function. */
6006 output_asm_insn ("jr\t%^", NULL);
6008 if (TARGET_ABICALLS_PIC2 && TARGET_ABSOLUTE_ABICALLS)
6009 fprintf (asm_out_file, "\t.option\tpic2\n");
6011 mips_end_function_definition (stubname);
6013 /* If the linker needs to create a dynamic symbol for the target
6014 function, it will associate the symbol with the stub (which,
6015 unlike the target function, follows the proper calling conventions).
6016 It is therefore useful to have a local alias for the target function,
6017 so that it can still be identified as MIPS16 code. As an optimization,
6018 this symbol can also be used for indirect MIPS16 references from
6019 within this file. */
6020 ASM_OUTPUT_DEF (asm_out_file, alias_name, fnname);
6022 switch_to_section (function_section (current_function_decl));
6025 /* The current function is a MIPS16 function that returns a value in an FPR.
6026 Copy the return value from its soft-float to its hard-float location.
6027 libgcc2 has special non-MIPS16 helper functions for each case. */
6030 mips16_copy_fpr_return_value (void)
6032 rtx fn, insn, retval;
6034 enum machine_mode return_mode;
6037 return_type = DECL_RESULT (current_function_decl);
6038 return_mode = DECL_MODE (return_type);
6040 name = ACONCAT (("__mips16_ret_",
6041 mips16_call_stub_mode_suffix (return_mode),
6043 fn = mips16_stub_function (name);
6045 /* The function takes arguments in $2 (and possibly $3), so calls
6046 to it cannot be lazily bound. */
6047 SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_BIND_NOW;
6049 /* Model the call as something that takes the GPR return value as
6050 argument and returns an "updated" value. */
6051 retval = gen_rtx_REG (return_mode, GP_RETURN);
6052 insn = mips_expand_call (MIPS_CALL_EPILOGUE, retval, fn,
6053 const0_rtx, NULL_RTX, false);
6054 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), retval);
6057 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
6058 RETVAL is the location of the return value, or null if this is
6059 a "call" rather than a "call_value". ARGS_SIZE is the size of the
6060 arguments and FP_CODE is the code built by mips_function_arg;
6061 see the comment before the fp_code field in CUMULATIVE_ARGS for details.
6063 There are three alternatives:
6065 - If a stub was needed, emit the call and return the call insn itself.
6067 - If we can avoid using a stub by redirecting the call, set *FN_PTR
6068 to the new target and return null.
6070 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
6073 A stub is needed for calls to functions that, in normal mode,
6074 receive arguments in FPRs or return values in FPRs. The stub
6075 copies the arguments from their soft-float positions to their
6076 hard-float positions, calls the real function, then copies the
6077 return value from its hard-float position to its soft-float
6080 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
6081 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
6082 automatically redirects the JAL to the stub, otherwise the JAL
6083 continues to call FN directly. */
6086 mips16_build_call_stub (rtx retval, rtx *fn_ptr, rtx args_size, int fp_code)
6090 struct mips16_stub *l;
6093 /* We don't need to do anything if we aren't in MIPS16 mode, or if
6094 we were invoked with the -msoft-float option. */
6095 if (!TARGET_MIPS16 || TARGET_SOFT_FLOAT_ABI)
6098 /* Figure out whether the value might come back in a floating-point
6100 fp_ret_p = retval && mips_return_mode_in_fpr_p (GET_MODE (retval));
6102 /* We don't need to do anything if there were no floating-point
6103 arguments and the value will not be returned in a floating-point
6105 if (fp_code == 0 && !fp_ret_p)
6108 /* We don't need to do anything if this is a call to a special
6109 MIPS16 support function. */
6111 if (mips16_stub_function_p (fn))
6114 /* This code will only work for o32 and o64 abis. The other ABI's
6115 require more sophisticated support. */
6116 gcc_assert (TARGET_OLDABI);
6118 /* If we're calling via a function pointer, use one of the magic
6119 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
6120 Each stub expects the function address to arrive in register $2. */
6121 if (GET_CODE (fn) != SYMBOL_REF
6122 || !call_insn_operand (fn, VOIDmode))
6125 rtx stub_fn, insn, addr;
6128 /* If this is a locally-defined and locally-binding function,
6129 avoid the stub by calling the local alias directly. */
6130 if (mips16_local_function_p (fn))
6132 *fn_ptr = mips16_local_alias (fn);
6136 /* Create a SYMBOL_REF for the libgcc.a function. */
6138 sprintf (buf, "__mips16_call_stub_%s_%d",
6139 mips16_call_stub_mode_suffix (GET_MODE (retval)),
6142 sprintf (buf, "__mips16_call_stub_%d", fp_code);
6143 stub_fn = mips16_stub_function (buf);
6145 /* The function uses $2 as an argument, so calls to it
6146 cannot be lazily bound. */
6147 SYMBOL_REF_FLAGS (stub_fn) |= SYMBOL_FLAG_BIND_NOW;
6149 /* Load the target function into $2. */
6150 addr = gen_rtx_REG (Pmode, GP_REG_FIRST + 2);
6151 lazy_p = mips_load_call_address (MIPS_CALL_NORMAL, addr, fn);
6153 /* Emit the call. */
6154 insn = mips_expand_call (MIPS_CALL_NORMAL, retval, stub_fn,
6155 args_size, NULL_RTX, lazy_p);
6157 /* Tell GCC that this call does indeed use the value of $2. */
6158 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), addr);
6160 /* If we are handling a floating-point return value, we need to
6161 save $18 in the function prologue. Putting a note on the
6162 call will mean that df_regs_ever_live_p ($18) will be true if the
6163 call is not eliminated, and we can check that in the prologue
6166 CALL_INSN_FUNCTION_USAGE (insn) =
6167 gen_rtx_EXPR_LIST (VOIDmode,
6168 gen_rtx_CLOBBER (VOIDmode,
6169 gen_rtx_REG (word_mode, 18)),
6170 CALL_INSN_FUNCTION_USAGE (insn));
6175 /* We know the function we are going to call. If we have already
6176 built a stub, we don't need to do anything further. */
6177 fnname = targetm.strip_name_encoding (XSTR (fn, 0));
6178 for (l = mips16_stubs; l != NULL; l = l->next)
6179 if (strcmp (l->name, fnname) == 0)
6184 const char *separator;
6185 char *secname, *stubname;
6186 tree stubid, stubdecl;
6189 /* If the function does not return in FPRs, the special stub
6193 If the function does return in FPRs, the stub section is named
6194 .mips16.call.fp.FNNAME
6196 Build a decl for the stub. */
6197 secname = ACONCAT ((".mips16.call.", fp_ret_p ? "fp." : "",
6199 stubname = ACONCAT (("__call_stub_", fp_ret_p ? "fp_" : "",
6201 stubid = get_identifier (stubname);
6202 stubdecl = build_decl (BUILTINS_LOCATION,
6203 FUNCTION_DECL, stubid,
6204 build_function_type_list (void_type_node,
6206 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
6207 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
6208 RESULT_DECL, NULL_TREE,
6211 /* Output a comment. */
6212 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
6214 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
6218 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
6220 fprintf (asm_out_file, "%s%s", separator,
6221 (f & 3) == 1 ? "float" : "double");
6224 fprintf (asm_out_file, ")\n");
6226 /* Start the function definition. */
6227 assemble_start_function (stubdecl, stubname);
6228 mips_start_function_definition (stubname, false);
6232 /* Load the address of the MIPS16 function into $25. Do this
6233 first so that targets with coprocessor interlocks can use
6234 an MFC1 to fill the delay slot. */
6235 if (TARGET_EXPLICIT_RELOCS)
6237 output_asm_insn ("lui\t%^,%%hi(%0)", &fn);
6238 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn);
6241 output_asm_insn ("la\t%^,%0", &fn);
6244 /* Move the arguments from general registers to floating-point
6246 mips_output_args_xfer (fp_code, 't');
6250 /* Jump to the previously-loaded address. */
6251 output_asm_insn ("jr\t%^", NULL);
6255 /* Save the return address in $18 and call the non-MIPS16 function.
6256 The stub's caller knows that $18 might be clobbered, even though
6257 $18 is usually a call-saved register. */
6258 fprintf (asm_out_file, "\tmove\t%s,%s\n",
6259 reg_names[GP_REG_FIRST + 18], reg_names[RETURN_ADDR_REGNUM]);
6260 output_asm_insn (MIPS_CALL ("jal", &fn, 0, -1), &fn);
6262 /* Move the result from floating-point registers to
6263 general registers. */
6264 switch (GET_MODE (retval))
6267 mips_output_32bit_xfer ('f', GP_RETURN + TARGET_BIG_ENDIAN,
6269 ? FP_REG_FIRST + MAX_FPRS_PER_FMT
6271 mips_output_32bit_xfer ('f', GP_RETURN + TARGET_LITTLE_ENDIAN,
6272 TARGET_LITTLE_ENDIAN
6273 ? FP_REG_FIRST + MAX_FPRS_PER_FMT
6275 if (GET_MODE (retval) == SCmode && TARGET_64BIT)
6277 /* On 64-bit targets, complex floats are returned in
6278 a single GPR, such that "sd" on a suitably-aligned
6279 target would store the value correctly. */
6280 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
6281 reg_names[GP_RETURN + TARGET_BIG_ENDIAN],
6282 reg_names[GP_RETURN + TARGET_BIG_ENDIAN]);
6283 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
6284 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN],
6285 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN]);
6286 fprintf (asm_out_file, "\tdsrl\t%s,%s,32\n",
6287 reg_names[GP_RETURN + TARGET_BIG_ENDIAN],
6288 reg_names[GP_RETURN + TARGET_BIG_ENDIAN]);
6289 fprintf (asm_out_file, "\tor\t%s,%s,%s\n",
6290 reg_names[GP_RETURN],
6291 reg_names[GP_RETURN],
6292 reg_names[GP_RETURN + 1]);
6297 mips_output_32bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6301 mips_output_64bit_xfer ('f', GP_RETURN + (8 / UNITS_PER_WORD),
6302 FP_REG_FIRST + MAX_FPRS_PER_FMT);
6306 mips_output_64bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6312 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 18]);
6315 #ifdef ASM_DECLARE_FUNCTION_SIZE
6316 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
6319 mips_end_function_definition (stubname);
6321 /* Record this stub. */
6322 l = XNEW (struct mips16_stub);
6323 l->name = xstrdup (fnname);
6324 l->fp_ret_p = fp_ret_p;
6325 l->next = mips16_stubs;
6329 /* If we expect a floating-point return value, but we've built a
6330 stub which does not expect one, then we're in trouble. We can't
6331 use the existing stub, because it won't handle the floating-point
6332 value. We can't build a new stub, because the linker won't know
6333 which stub to use for the various calls in this object file.
6334 Fortunately, this case is illegal, since it means that a function
6335 was declared in two different ways in a single compilation. */
6336 if (fp_ret_p && !l->fp_ret_p)
6337 error ("cannot handle inconsistent calls to %qs", fnname);
6339 if (retval == NULL_RTX)
6340 insn = gen_call_internal_direct (fn, args_size);
6342 insn = gen_call_value_internal_direct (retval, fn, args_size);
6343 insn = mips_emit_call_insn (insn, fn, fn, false);
6345 /* If we are calling a stub which handles a floating-point return
6346 value, we need to arrange to save $18 in the prologue. We do this
6347 by marking the function call as using the register. The prologue
6348 will later see that it is used, and emit code to save it. */
6350 CALL_INSN_FUNCTION_USAGE (insn) =
6351 gen_rtx_EXPR_LIST (VOIDmode,
6352 gen_rtx_CLOBBER (VOIDmode,
6353 gen_rtx_REG (word_mode, 18)),
6354 CALL_INSN_FUNCTION_USAGE (insn));
6359 /* Expand a call of type TYPE. RESULT is where the result will go (null
6360 for "call"s and "sibcall"s), ADDR is the address of the function,
6361 ARGS_SIZE is the size of the arguments and AUX is the value passed
6362 to us by mips_function_arg. LAZY_P is true if this call already
6363 involves a lazily-bound function address (such as when calling
6364 functions through a MIPS16 hard-float stub).
6366 Return the call itself. */
6369 mips_expand_call (enum mips_call_type type, rtx result, rtx addr,
6370 rtx args_size, rtx aux, bool lazy_p)
6372 rtx orig_addr, pattern, insn;
6375 fp_code = aux == 0 ? 0 : (int) GET_MODE (aux);
6376 insn = mips16_build_call_stub (result, &addr, args_size, fp_code);
6379 gcc_assert (!lazy_p && type == MIPS_CALL_NORMAL);
6384 if (!call_insn_operand (addr, VOIDmode))
6386 if (type == MIPS_CALL_EPILOGUE)
6387 addr = MIPS_EPILOGUE_TEMP (Pmode);
6389 addr = gen_reg_rtx (Pmode);
6390 lazy_p |= mips_load_call_address (type, addr, orig_addr);
6395 rtx (*fn) (rtx, rtx);
6397 if (type == MIPS_CALL_SIBCALL)
6398 fn = gen_sibcall_internal;
6400 fn = gen_call_internal;
6402 pattern = fn (addr, args_size);
6404 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
6406 /* Handle return values created by mips_return_fpr_pair. */
6407 rtx (*fn) (rtx, rtx, rtx, rtx);
6410 if (type == MIPS_CALL_SIBCALL)
6411 fn = gen_sibcall_value_multiple_internal;
6413 fn = gen_call_value_multiple_internal;
6415 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
6416 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
6417 pattern = fn (reg1, addr, args_size, reg2);
6421 rtx (*fn) (rtx, rtx, rtx);
6423 if (type == MIPS_CALL_SIBCALL)
6424 fn = gen_sibcall_value_internal;
6426 fn = gen_call_value_internal;
6428 /* Handle return values created by mips_return_fpr_single. */
6429 if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 1)
6430 result = XEXP (XVECEXP (result, 0, 0), 0);
6431 pattern = fn (result, addr, args_size);
6434 return mips_emit_call_insn (pattern, orig_addr, addr, lazy_p);
6437 /* Split call instruction INSN into a $gp-clobbering call and
6438 (where necessary) an instruction to restore $gp from its save slot.
6439 CALL_PATTERN is the pattern of the new call. */
6442 mips_split_call (rtx insn, rtx call_pattern)
6444 emit_call_insn (call_pattern);
6445 if (!find_reg_note (insn, REG_NORETURN, 0))
6446 /* Pick a temporary register that is suitable for both MIPS16 and
6447 non-MIPS16 code. $4 and $5 are used for returning complex double
6448 values in soft-float code, so $6 is the first suitable candidate. */
6449 mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode, GP_ARG_FIRST + 2));
6452 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
6455 mips_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
6457 if (!TARGET_SIBCALLS)
6460 /* Interrupt handlers need special epilogue code and therefore can't
6462 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
6465 /* We can't do a sibcall if the called function is a MIPS16 function
6466 because there is no direct "jx" instruction equivalent to "jalx" to
6467 switch the ISA mode. We only care about cases where the sibling
6468 and normal calls would both be direct. */
6470 && mips_use_mips16_mode_p (decl)
6471 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
6474 /* When -minterlink-mips16 is in effect, assume that non-locally-binding
6475 functions could be MIPS16 ones unless an attribute explicitly tells
6477 if (TARGET_INTERLINK_MIPS16
6479 && (DECL_EXTERNAL (decl) || !targetm.binds_local_p (decl))
6480 && !mips_nomips16_decl_p (decl)
6481 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
6488 /* Emit code to move general operand SRC into condition-code
6489 register DEST given that SCRATCH is a scratch TFmode FPR.
6496 where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */
6499 mips_expand_fcc_reload (rtx dest, rtx src, rtx scratch)
6503 /* Change the source to SFmode. */
6505 src = adjust_address (src, SFmode, 0);
6506 else if (REG_P (src) || GET_CODE (src) == SUBREG)
6507 src = gen_rtx_REG (SFmode, true_regnum (src));
6509 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
6510 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + MAX_FPRS_PER_FMT);
6512 mips_emit_move (copy_rtx (fp1), src);
6513 mips_emit_move (copy_rtx (fp2), CONST0_RTX (SFmode));
6514 emit_insn (gen_slt_sf (dest, fp2, fp1));
6517 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
6518 Assume that the areas do not overlap. */
6521 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
6523 HOST_WIDE_INT offset, delta;
6524 unsigned HOST_WIDE_INT bits;
6526 enum machine_mode mode;
6529 /* Work out how many bits to move at a time. If both operands have
6530 half-word alignment, it is usually better to move in half words.
6531 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
6532 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
6533 Otherwise move word-sized chunks. */
6534 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
6535 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
6536 bits = BITS_PER_WORD / 2;
6538 bits = BITS_PER_WORD;
6540 mode = mode_for_size (bits, MODE_INT, 0);
6541 delta = bits / BITS_PER_UNIT;
6543 /* Allocate a buffer for the temporary registers. */
6544 regs = XALLOCAVEC (rtx, length / delta);
6546 /* Load as many BITS-sized chunks as possible. Use a normal load if
6547 the source has enough alignment, otherwise use left/right pairs. */
6548 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
6550 regs[i] = gen_reg_rtx (mode);
6551 if (MEM_ALIGN (src) >= bits)
6552 mips_emit_move (regs[i], adjust_address (src, mode, offset));
6555 rtx part = adjust_address (src, BLKmode, offset);
6556 if (!mips_expand_ext_as_unaligned_load (regs[i], part, bits, 0))
6561 /* Copy the chunks to the destination. */
6562 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
6563 if (MEM_ALIGN (dest) >= bits)
6564 mips_emit_move (adjust_address (dest, mode, offset), regs[i]);
6567 rtx part = adjust_address (dest, BLKmode, offset);
6568 if (!mips_expand_ins_as_unaligned_store (part, regs[i], bits, 0))
6572 /* Mop up any left-over bytes. */
6573 if (offset < length)
6575 src = adjust_address (src, BLKmode, offset);
6576 dest = adjust_address (dest, BLKmode, offset);
6577 move_by_pieces (dest, src, length - offset,
6578 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
6582 /* Helper function for doing a loop-based block operation on memory
6583 reference MEM. Each iteration of the loop will operate on LENGTH
6586 Create a new base register for use within the loop and point it to
6587 the start of MEM. Create a new memory reference that uses this
6588 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
6591 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
6592 rtx *loop_reg, rtx *loop_mem)
6594 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
6596 /* Although the new mem does not refer to a known location,
6597 it does keep up to LENGTH bytes of alignment. */
6598 *loop_mem = change_address (mem, BLKmode, *loop_reg);
6599 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
6602 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
6603 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
6604 the memory regions do not overlap. */
6607 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length,
6608 HOST_WIDE_INT bytes_per_iter)
6610 rtx label, src_reg, dest_reg, final_src, test;
6611 HOST_WIDE_INT leftover;
6613 leftover = length % bytes_per_iter;
6616 /* Create registers and memory references for use within the loop. */
6617 mips_adjust_block_mem (src, bytes_per_iter, &src_reg, &src);
6618 mips_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest);
6620 /* Calculate the value that SRC_REG should have after the last iteration
6622 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
6625 /* Emit the start of the loop. */
6626 label = gen_label_rtx ();
6629 /* Emit the loop body. */
6630 mips_block_move_straight (dest, src, bytes_per_iter);
6632 /* Move on to the next block. */
6633 mips_emit_move (src_reg, plus_constant (src_reg, bytes_per_iter));
6634 mips_emit_move (dest_reg, plus_constant (dest_reg, bytes_per_iter));
6636 /* Emit the loop condition. */
6637 test = gen_rtx_NE (VOIDmode, src_reg, final_src);
6638 if (Pmode == DImode)
6639 emit_jump_insn (gen_cbranchdi4 (test, src_reg, final_src, label));
6641 emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label));
6643 /* Mop up any left-over bytes. */
6645 mips_block_move_straight (dest, src, leftover);
6648 /* Expand a movmemsi instruction, which copies LENGTH bytes from
6649 memory reference SRC to memory reference DEST. */
6652 mips_expand_block_move (rtx dest, rtx src, rtx length)
6654 if (CONST_INT_P (length))
6656 if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)
6658 mips_block_move_straight (dest, src, INTVAL (length));
6663 mips_block_move_loop (dest, src, INTVAL (length),
6664 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER);
6671 /* Expand a loop of synci insns for the address range [BEGIN, END). */
6674 mips_expand_synci_loop (rtx begin, rtx end)
6676 rtx inc, label, end_label, cmp_result, mask, length;
6678 /* Create end_label. */
6679 end_label = gen_label_rtx ();
6681 /* Check if begin equals end. */
6682 cmp_result = gen_rtx_EQ (VOIDmode, begin, end);
6683 emit_jump_insn (gen_condjump (cmp_result, end_label));
6685 /* Load INC with the cache line size (rdhwr INC,$1). */
6686 inc = gen_reg_rtx (Pmode);
6687 emit_insn (Pmode == SImode
6688 ? gen_rdhwr_synci_step_si (inc)
6689 : gen_rdhwr_synci_step_di (inc));
6691 /* Check if inc is 0. */
6692 cmp_result = gen_rtx_EQ (VOIDmode, inc, const0_rtx);
6693 emit_jump_insn (gen_condjump (cmp_result, end_label));
6695 /* Calculate mask. */
6696 mask = mips_force_unary (Pmode, NEG, inc);
6698 /* Mask out begin by mask. */
6699 begin = mips_force_binary (Pmode, AND, begin, mask);
6701 /* Calculate length. */
6702 length = mips_force_binary (Pmode, MINUS, end, begin);
6704 /* Loop back to here. */
6705 label = gen_label_rtx ();
6708 emit_insn (gen_synci (begin));
6710 /* Update length. */
6711 mips_emit_binary (MINUS, length, length, inc);
6714 mips_emit_binary (PLUS, begin, begin, inc);
6716 /* Check if length is greater than 0. */
6717 cmp_result = gen_rtx_GT (VOIDmode, length, const0_rtx);
6718 emit_jump_insn (gen_condjump (cmp_result, label));
6720 emit_label (end_label);
6723 /* Expand a QI or HI mode atomic memory operation.
6725 GENERATOR contains a pointer to the gen_* function that generates
6726 the SI mode underlying atomic operation using masks that we
6729 RESULT is the return register for the operation. Its value is NULL
6732 MEM is the location of the atomic access.
6734 OLDVAL is the first operand for the operation.
6736 NEWVAL is the optional second operand for the operation. Its value
6737 is NULL if unused. */
6740 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator,
6741 rtx result, rtx mem, rtx oldval, rtx newval)
6743 rtx orig_addr, memsi_addr, memsi, shift, shiftsi, unshifted_mask;
6744 rtx unshifted_mask_reg, mask, inverted_mask, si_op;
6746 enum machine_mode mode;
6748 mode = GET_MODE (mem);
6750 /* Compute the address of the containing SImode value. */
6751 orig_addr = force_reg (Pmode, XEXP (mem, 0));
6752 memsi_addr = mips_force_binary (Pmode, AND, orig_addr,
6753 force_reg (Pmode, GEN_INT (-4)));
6755 /* Create a memory reference for it. */
6756 memsi = gen_rtx_MEM (SImode, memsi_addr);
6757 set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER);
6758 MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem);
6760 /* Work out the byte offset of the QImode or HImode value,
6761 counting from the least significant byte. */
6762 shift = mips_force_binary (Pmode, AND, orig_addr, GEN_INT (3));
6763 if (TARGET_BIG_ENDIAN)
6764 mips_emit_binary (XOR, shift, shift, GEN_INT (mode == QImode ? 3 : 2));
6766 /* Multiply by eight to convert the shift value from bytes to bits. */
6767 mips_emit_binary (ASHIFT, shift, shift, GEN_INT (3));
6769 /* Make the final shift an SImode value, so that it can be used in
6770 SImode operations. */
6771 shiftsi = force_reg (SImode, gen_lowpart (SImode, shift));
6773 /* Set MASK to an inclusive mask of the QImode or HImode value. */
6774 unshifted_mask = GEN_INT (GET_MODE_MASK (mode));
6775 unshifted_mask_reg = force_reg (SImode, unshifted_mask);
6776 mask = mips_force_binary (SImode, ASHIFT, unshifted_mask_reg, shiftsi);
6778 /* Compute the equivalent exclusive mask. */
6779 inverted_mask = gen_reg_rtx (SImode);
6780 emit_insn (gen_rtx_SET (VOIDmode, inverted_mask,
6781 gen_rtx_NOT (SImode, mask)));
6783 /* Shift the old value into place. */
6784 if (oldval != const0_rtx)
6786 oldval = convert_modes (SImode, mode, oldval, true);
6787 oldval = force_reg (SImode, oldval);
6788 oldval = mips_force_binary (SImode, ASHIFT, oldval, shiftsi);
6791 /* Do the same for the new value. */
6792 if (newval && newval != const0_rtx)
6794 newval = convert_modes (SImode, mode, newval, true);
6795 newval = force_reg (SImode, newval);
6796 newval = mips_force_binary (SImode, ASHIFT, newval, shiftsi);
6799 /* Do the SImode atomic access. */
6801 res = gen_reg_rtx (SImode);
6803 si_op = generator.fn_6 (res, memsi, mask, inverted_mask, oldval, newval);
6805 si_op = generator.fn_5 (res, memsi, mask, inverted_mask, oldval);
6807 si_op = generator.fn_4 (memsi, mask, inverted_mask, oldval);
6813 /* Shift and convert the result. */
6814 mips_emit_binary (AND, res, res, mask);
6815 mips_emit_binary (LSHIFTRT, res, res, shiftsi);
6816 mips_emit_move (result, gen_lowpart (GET_MODE (result), res));
6820 /* Return true if it is possible to use left/right accesses for a
6821 bitfield of WIDTH bits starting BITPOS bits into *OP. When
6822 returning true, update *OP, *LEFT and *RIGHT as follows:
6824 *OP is a BLKmode reference to the whole field.
6826 *LEFT is a QImode reference to the first byte if big endian or
6827 the last byte if little endian. This address can be used in the
6828 left-side instructions (LWL, SWL, LDL, SDL).
6830 *RIGHT is a QImode reference to the opposite end of the field and
6831 can be used in the patterning right-side instruction. */
6834 mips_get_unaligned_mem (rtx *op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos,
6835 rtx *left, rtx *right)
6839 /* Check that the operand really is a MEM. Not all the extv and
6840 extzv predicates are checked. */
6844 /* Check that the size is valid. */
6845 if (width != 32 && (!TARGET_64BIT || width != 64))
6848 /* We can only access byte-aligned values. Since we are always passed
6849 a reference to the first byte of the field, it is not necessary to
6850 do anything with BITPOS after this check. */
6851 if (bitpos % BITS_PER_UNIT != 0)
6854 /* Reject aligned bitfields: we want to use a normal load or store
6855 instead of a left/right pair. */
6856 if (MEM_ALIGN (*op) >= width)
6859 /* Adjust *OP to refer to the whole field. This also has the effect
6860 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
6861 *op = adjust_address (*op, BLKmode, 0);
6862 set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
6864 /* Get references to both ends of the field. We deliberately don't
6865 use the original QImode *OP for FIRST since the new BLKmode one
6866 might have a simpler address. */
6867 first = adjust_address (*op, QImode, 0);
6868 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
6870 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
6871 correspond to the MSB and RIGHT to the LSB. */
6872 if (TARGET_BIG_ENDIAN)
6873 *left = first, *right = last;
6875 *left = last, *right = first;
6880 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
6881 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
6882 the operation is the equivalent of:
6884 (set DEST (*_extract SRC WIDTH BITPOS))
6886 Return true on success. */
6889 mips_expand_ext_as_unaligned_load (rtx dest, rtx src, HOST_WIDE_INT width,
6890 HOST_WIDE_INT bitpos)
6892 rtx left, right, temp;
6894 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
6895 be a paradoxical word_mode subreg. This is the only case in which
6896 we allow the destination to be larger than the source. */
6897 if (GET_CODE (dest) == SUBREG
6898 && GET_MODE (dest) == DImode
6899 && GET_MODE (SUBREG_REG (dest)) == SImode)
6900 dest = SUBREG_REG (dest);
6902 /* After the above adjustment, the destination must be the same
6903 width as the source. */
6904 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
6907 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
6910 temp = gen_reg_rtx (GET_MODE (dest));
6911 if (GET_MODE (dest) == DImode)
6913 emit_insn (gen_mov_ldl (temp, src, left));
6914 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
6918 emit_insn (gen_mov_lwl (temp, src, left));
6919 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
6924 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
6925 BITPOS and SRC are the operands passed to the expander; the operation
6926 is the equivalent of:
6928 (set (zero_extract DEST WIDTH BITPOS) SRC)
6930 Return true on success. */
6933 mips_expand_ins_as_unaligned_store (rtx dest, rtx src, HOST_WIDE_INT width,
6934 HOST_WIDE_INT bitpos)
6937 enum machine_mode mode;
6939 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
6942 mode = mode_for_size (width, MODE_INT, 0);
6943 src = gen_lowpart (mode, src);
6946 emit_insn (gen_mov_sdl (dest, src, left));
6947 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
6951 emit_insn (gen_mov_swl (dest, src, left));
6952 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
6957 /* Return true if X is a MEM with the same size as MODE. */
6960 mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
6967 size = MEM_SIZE (x);
6968 return size && INTVAL (size) == GET_MODE_SIZE (mode);
6971 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
6972 source of an "ext" instruction or the destination of an "ins"
6973 instruction. OP must be a register operand and the following
6974 conditions must hold:
6976 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
6977 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
6978 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
6980 Also reject lengths equal to a word as they are better handled
6981 by the move patterns. */
6984 mips_use_ins_ext_p (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos)
6986 if (!ISA_HAS_EXT_INS
6987 || !register_operand (op, VOIDmode)
6988 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
6991 if (!IN_RANGE (width, 1, GET_MODE_BITSIZE (GET_MODE (op)) - 1))
6994 if (bitpos < 0 || bitpos + width > GET_MODE_BITSIZE (GET_MODE (op)))
7000 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
7001 operation if MAXLEN is the maxium length of consecutive bits that
7002 can make up MASK. MODE is the mode of the operation. See
7003 mask_low_and_shift_len for the actual definition. */
7006 mask_low_and_shift_p (enum machine_mode mode, rtx mask, rtx shift, int maxlen)
7008 return IN_RANGE (mask_low_and_shift_len (mode, mask, shift), 1, maxlen);
7011 /* Return true iff OP1 and OP2 are valid operands together for the
7012 *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider,
7013 see the table in the comment before the pattern. */
7016 and_operands_ok (enum machine_mode mode, rtx op1, rtx op2)
7018 return (memory_operand (op1, mode)
7019 ? and_load_operand (op2, mode)
7020 : and_reg_operand (op2, mode));
7023 /* The canonical form of a mask-low-and-shift-left operation is
7024 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
7025 cleared. Thus we need to shift MASK to the right before checking if it
7026 is a valid mask value. MODE is the mode of the operation. If true
7027 return the length of the mask, otherwise return -1. */
7030 mask_low_and_shift_len (enum machine_mode mode, rtx mask, rtx shift)
7032 HOST_WIDE_INT shval;
7034 shval = INTVAL (shift) & (GET_MODE_BITSIZE (mode) - 1);
7035 return exact_log2 ((UINTVAL (mask) >> shval) + 1);
7038 /* Return true if -msplit-addresses is selected and should be honored.
7040 -msplit-addresses is a half-way house between explicit relocations
7041 and the traditional assembler macros. It can split absolute 32-bit
7042 symbolic constants into a high/lo_sum pair but uses macros for other
7045 Like explicit relocation support for REL targets, it relies
7046 on GNU extensions in the assembler and the linker.
7048 Although this code should work for -O0, it has traditionally
7049 been treated as an optimization. */
7052 mips_split_addresses_p (void)
7054 return (TARGET_SPLIT_ADDRESSES
7058 && !ABI_HAS_64BIT_SYMBOLS);
7061 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
7064 mips_init_relocs (void)
7066 memset (mips_split_p, '\0', sizeof (mips_split_p));
7067 memset (mips_split_hi_p, '\0', sizeof (mips_split_hi_p));
7068 memset (mips_hi_relocs, '\0', sizeof (mips_hi_relocs));
7069 memset (mips_lo_relocs, '\0', sizeof (mips_lo_relocs));
7071 if (ABI_HAS_64BIT_SYMBOLS)
7073 if (TARGET_EXPLICIT_RELOCS)
7075 mips_split_p[SYMBOL_64_HIGH] = true;
7076 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
7077 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
7079 mips_split_p[SYMBOL_64_MID] = true;
7080 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
7081 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
7083 mips_split_p[SYMBOL_64_LOW] = true;
7084 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
7085 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
7087 mips_split_p[SYMBOL_ABSOLUTE] = true;
7088 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
7093 if (TARGET_EXPLICIT_RELOCS || mips_split_addresses_p () || TARGET_MIPS16)
7095 mips_split_p[SYMBOL_ABSOLUTE] = true;
7096 mips_hi_relocs[SYMBOL_ABSOLUTE] = "%hi(";
7097 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
7099 mips_lo_relocs[SYMBOL_32_HIGH] = "%hi(";
7105 /* The high part is provided by a pseudo copy of $gp. */
7106 mips_split_p[SYMBOL_GP_RELATIVE] = true;
7107 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gprel(";
7109 else if (TARGET_EXPLICIT_RELOCS)
7110 /* Small data constants are kept whole until after reload,
7111 then lowered by mips_rewrite_small_data. */
7112 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gp_rel(";
7114 if (TARGET_EXPLICIT_RELOCS)
7116 mips_split_p[SYMBOL_GOT_PAGE_OFST] = true;
7119 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
7120 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%got_ofst(";
7124 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
7125 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%lo(";
7128 /* Expose the use of $28 as soon as possible. */
7129 mips_split_hi_p[SYMBOL_GOT_PAGE_OFST] = true;
7133 /* The HIGH and LO_SUM are matched by special .md patterns. */
7134 mips_split_p[SYMBOL_GOT_DISP] = true;
7136 mips_split_p[SYMBOL_GOTOFF_DISP] = true;
7137 mips_hi_relocs[SYMBOL_GOTOFF_DISP] = "%got_hi(";
7138 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_lo(";
7140 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
7141 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
7142 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
7147 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_disp(";
7149 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got(";
7150 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
7152 /* Expose the use of $28 as soon as possible. */
7153 mips_split_p[SYMBOL_GOT_DISP] = true;
7159 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
7160 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
7161 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
7164 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
7165 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
7167 mips_split_p[SYMBOL_DTPREL] = true;
7168 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
7169 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
7171 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
7173 mips_split_p[SYMBOL_TPREL] = true;
7174 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
7175 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
7177 mips_lo_relocs[SYMBOL_HALF] = "%half(";
7180 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
7181 in context CONTEXT. RELOCS is the array of relocations to use. */
7184 mips_print_operand_reloc (FILE *file, rtx op, enum mips_symbol_context context,
7185 const char **relocs)
7187 enum mips_symbol_type symbol_type;
7190 symbol_type = mips_classify_symbolic_expression (op, context);
7191 gcc_assert (relocs[symbol_type]);
7193 fputs (relocs[symbol_type], file);
7194 output_addr_const (file, mips_strip_unspec_address (op));
7195 for (p = relocs[symbol_type]; *p != 0; p++)
7200 /* Start a new block with the given asm switch enabled. If we need
7201 to print a directive, emit PREFIX before it and SUFFIX after it. */
7204 mips_push_asm_switch_1 (struct mips_asm_switch *asm_switch,
7205 const char *prefix, const char *suffix)
7207 if (asm_switch->nesting_level == 0)
7208 fprintf (asm_out_file, "%s.set\tno%s%s", prefix, asm_switch->name, suffix);
7209 asm_switch->nesting_level++;
7212 /* Likewise, but end a block. */
7215 mips_pop_asm_switch_1 (struct mips_asm_switch *asm_switch,
7216 const char *prefix, const char *suffix)
7218 gcc_assert (asm_switch->nesting_level);
7219 asm_switch->nesting_level--;
7220 if (asm_switch->nesting_level == 0)
7221 fprintf (asm_out_file, "%s.set\t%s%s", prefix, asm_switch->name, suffix);
7224 /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1
7225 that either print a complete line or print nothing. */
7228 mips_push_asm_switch (struct mips_asm_switch *asm_switch)
7230 mips_push_asm_switch_1 (asm_switch, "\t", "\n");
7234 mips_pop_asm_switch (struct mips_asm_switch *asm_switch)
7236 mips_pop_asm_switch_1 (asm_switch, "\t", "\n");
7239 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
7240 The punctuation characters are:
7242 '(' Start a nested ".set noreorder" block.
7243 ')' End a nested ".set noreorder" block.
7244 '[' Start a nested ".set noat" block.
7245 ']' End a nested ".set noat" block.
7246 '<' Start a nested ".set nomacro" block.
7247 '>' End a nested ".set nomacro" block.
7248 '*' Behave like %(%< if generating a delayed-branch sequence.
7249 '#' Print a nop if in a ".set noreorder" block.
7250 '/' Like '#', but do nothing within a delayed-branch sequence.
7251 '?' Print "l" if mips_branch_likely is true
7252 '~' Print a nop if mips_branch_likely is true
7253 '.' Print the name of the register with a hard-wired zero (zero or $0).
7254 '@' Print the name of the assembler temporary register (at or $1).
7255 '^' Print the name of the pic call-through register (t9 or $25).
7256 '+' Print the name of the gp register (usually gp or $28).
7257 '$' Print the name of the stack pointer register (sp or $29).
7259 See also mips_init_print_operand_pucnt. */
7262 mips_print_operand_punctuation (FILE *file, int ch)
7267 mips_push_asm_switch_1 (&mips_noreorder, "", "\n\t");
7271 mips_pop_asm_switch_1 (&mips_noreorder, "\n\t", "");
7275 mips_push_asm_switch_1 (&mips_noat, "", "\n\t");
7279 mips_pop_asm_switch_1 (&mips_noat, "\n\t", "");
7283 mips_push_asm_switch_1 (&mips_nomacro, "", "\n\t");
7287 mips_pop_asm_switch_1 (&mips_nomacro, "\n\t", "");
7291 if (final_sequence != 0)
7293 mips_print_operand_punctuation (file, '(');
7294 mips_print_operand_punctuation (file, '<');
7299 if (mips_noreorder.nesting_level > 0)
7300 fputs ("\n\tnop", file);
7304 /* Print an extra newline so that the delayed insn is separated
7305 from the following ones. This looks neater and is consistent
7306 with non-nop delayed sequences. */
7307 if (mips_noreorder.nesting_level > 0 && final_sequence == 0)
7308 fputs ("\n\tnop\n", file);
7312 if (mips_branch_likely)
7317 if (mips_branch_likely)
7318 fputs ("\n\tnop", file);
7322 fputs (reg_names[GP_REG_FIRST + 0], file);
7326 fputs (reg_names[AT_REGNUM], file);
7330 fputs (reg_names[PIC_FUNCTION_ADDR_REGNUM], file);
7334 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
7338 fputs (reg_names[STACK_POINTER_REGNUM], file);
7347 /* Initialize mips_print_operand_punct. */
7350 mips_init_print_operand_punct (void)
7354 for (p = "()[]<>*#/?~.@^+$"; *p; p++)
7355 mips_print_operand_punct[(unsigned char) *p] = true;
7358 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
7359 associated with condition CODE. Print the condition part of the
7363 mips_print_int_branch_condition (FILE *file, enum rtx_code code, int letter)
7377 /* Conveniently, the MIPS names for these conditions are the same
7378 as their RTL equivalents. */
7379 fputs (GET_RTX_NAME (code), file);
7383 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
7388 /* Likewise floating-point branches. */
7391 mips_print_float_branch_condition (FILE *file, enum rtx_code code, int letter)
7396 fputs ("c1f", file);
7400 fputs ("c1t", file);
7404 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
7409 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
7412 mips_print_operand_punct_valid_p (unsigned char code)
7414 return mips_print_operand_punct[code];
7417 /* Implement TARGET_PRINT_OPERAND. The MIPS-specific operand codes are:
7419 'X' Print CONST_INT OP in hexadecimal format.
7420 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
7421 'd' Print CONST_INT OP in decimal.
7422 'm' Print one less than CONST_INT OP in decimal.
7423 'h' Print the high-part relocation associated with OP, after stripping
7425 'R' Print the low-part relocation associated with OP.
7426 'C' Print the integer branch condition for comparison OP.
7427 'N' Print the inverse of the integer branch condition for comparison OP.
7428 'F' Print the FPU branch condition for comparison OP.
7429 'W' Print the inverse of the FPU branch condition for comparison OP.
7430 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
7431 'z' for (eq:?I ...), 'n' for (ne:?I ...).
7432 't' Like 'T', but with the EQ/NE cases reversed
7433 'Y' Print mips_fp_conditions[INTVAL (OP)]
7434 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
7435 'q' Print a DSP accumulator register.
7436 'D' Print the second part of a double-word register or memory operand.
7437 'L' Print the low-order register in a double-word register operand.
7438 'M' Print high-order register in a double-word register operand.
7439 'z' Print $0 if OP is zero, otherwise print OP normally. */
7442 mips_print_operand (FILE *file, rtx op, int letter)
7446 if (mips_print_operand_punct_valid_p (letter))
7448 mips_print_operand_punctuation (file, letter);
7453 code = GET_CODE (op);
7458 if (CONST_INT_P (op))
7459 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
7461 output_operand_lossage ("invalid use of '%%%c'", letter);
7465 if (CONST_INT_P (op))
7466 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op) & 0xffff);
7468 output_operand_lossage ("invalid use of '%%%c'", letter);
7472 if (CONST_INT_P (op))
7473 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op));
7475 output_operand_lossage ("invalid use of '%%%c'", letter);
7479 if (CONST_INT_P (op))
7480 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op) - 1);
7482 output_operand_lossage ("invalid use of '%%%c'", letter);
7488 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_hi_relocs);
7492 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_lo_relocs);
7496 mips_print_int_branch_condition (file, code, letter);
7500 mips_print_int_branch_condition (file, reverse_condition (code), letter);
7504 mips_print_float_branch_condition (file, code, letter);
7508 mips_print_float_branch_condition (file, reverse_condition (code),
7515 int truth = (code == NE) == (letter == 'T');
7516 fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
7521 if (code == CONST_INT && UINTVAL (op) < ARRAY_SIZE (mips_fp_conditions))
7522 fputs (mips_fp_conditions[UINTVAL (op)], file);
7524 output_operand_lossage ("'%%%c' is not a valid operand prefix",
7531 mips_print_operand (file, op, 0);
7537 if (code == REG && MD_REG_P (REGNO (op)))
7538 fprintf (file, "$ac0");
7539 else if (code == REG && DSP_ACC_REG_P (REGNO (op)))
7540 fprintf (file, "$ac%c", reg_names[REGNO (op)][3]);
7542 output_operand_lossage ("invalid use of '%%%c'", letter);
7550 unsigned int regno = REGNO (op);
7551 if ((letter == 'M' && TARGET_LITTLE_ENDIAN)
7552 || (letter == 'L' && TARGET_BIG_ENDIAN)
7555 else if (letter && letter != 'z' && letter != 'M' && letter != 'L')
7556 output_operand_lossage ("invalid use of '%%%c'", letter);
7557 /* We need to print $0 .. $31 for COP0 registers. */
7558 if (COP0_REG_P (regno))
7559 fprintf (file, "$%s", ®_names[regno][4]);
7561 fprintf (file, "%s", reg_names[regno]);
7567 output_address (plus_constant (XEXP (op, 0), 4));
7568 else if (letter && letter != 'z')
7569 output_operand_lossage ("invalid use of '%%%c'", letter);
7571 output_address (XEXP (op, 0));
7575 if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
7576 fputs (reg_names[GP_REG_FIRST], file);
7577 else if (letter && letter != 'z')
7578 output_operand_lossage ("invalid use of '%%%c'", letter);
7579 else if (CONST_GP_P (op))
7580 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
7582 output_addr_const (file, mips_strip_unspec_address (op));
7588 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
7591 mips_print_operand_address (FILE *file, rtx x)
7593 struct mips_address_info addr;
7595 if (mips_classify_address (&addr, x, word_mode, true))
7599 mips_print_operand (file, addr.offset, 0);
7600 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
7603 case ADDRESS_LO_SUM:
7604 mips_print_operand_reloc (file, addr.offset, SYMBOL_CONTEXT_MEM,
7606 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
7609 case ADDRESS_CONST_INT:
7610 output_addr_const (file, x);
7611 fprintf (file, "(%s)", reg_names[GP_REG_FIRST]);
7614 case ADDRESS_SYMBOLIC:
7615 output_addr_const (file, mips_strip_unspec_address (x));
7621 /* Implement TARGET_ENCODE_SECTION_INFO. */
7624 mips_encode_section_info (tree decl, rtx rtl, int first)
7626 default_encode_section_info (decl, rtl, first);
7628 if (TREE_CODE (decl) == FUNCTION_DECL)
7630 rtx symbol = XEXP (rtl, 0);
7631 tree type = TREE_TYPE (decl);
7633 /* Encode whether the symbol is short or long. */
7634 if ((TARGET_LONG_CALLS && !mips_near_type_p (type))
7635 || mips_far_type_p (type))
7636 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
7640 /* Implement TARGET_SELECT_RTX_SECTION. */
7643 mips_select_rtx_section (enum machine_mode mode, rtx x,
7644 unsigned HOST_WIDE_INT align)
7646 /* ??? Consider using mergeable small data sections. */
7647 if (mips_rtx_constant_in_small_data_p (mode))
7648 return get_named_section (NULL, ".sdata", 0);
7650 return default_elf_select_rtx_section (mode, x, align);
7653 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
7655 The complication here is that, with the combination TARGET_ABICALLS
7656 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
7657 absolute addresses, and should therefore not be included in the
7658 read-only part of a DSO. Handle such cases by selecting a normal
7659 data section instead of a read-only one. The logic apes that in
7660 default_function_rodata_section. */
7663 mips_function_rodata_section (tree decl)
7665 if (!TARGET_ABICALLS || TARGET_ABSOLUTE_ABICALLS || TARGET_GPWORD)
7666 return default_function_rodata_section (decl);
7668 if (decl && DECL_SECTION_NAME (decl))
7670 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7671 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
7673 char *rname = ASTRDUP (name);
7675 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
7677 else if (flag_function_sections
7678 && flag_data_sections
7679 && strncmp (name, ".text.", 6) == 0)
7681 char *rname = ASTRDUP (name);
7682 memcpy (rname + 1, "data", 4);
7683 return get_section (rname, SECTION_WRITE, decl);
7686 return data_section;
7689 /* Implement TARGET_IN_SMALL_DATA_P. */
7692 mips_in_small_data_p (const_tree decl)
7694 unsigned HOST_WIDE_INT size;
7696 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
7699 /* We don't yet generate small-data references for -mabicalls
7700 or VxWorks RTP code. See the related -G handling in
7701 mips_option_override. */
7702 if (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
7705 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
7709 /* Reject anything that isn't in a known small-data section. */
7710 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7711 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
7714 /* If a symbol is defined externally, the assembler will use the
7715 usual -G rules when deciding how to implement macros. */
7716 if (mips_lo_relocs[SYMBOL_GP_RELATIVE] || !DECL_EXTERNAL (decl))
7719 else if (TARGET_EMBEDDED_DATA)
7721 /* Don't put constants into the small data section: we want them
7722 to be in ROM rather than RAM. */
7723 if (TREE_CODE (decl) != VAR_DECL)
7726 if (TREE_READONLY (decl)
7727 && !TREE_SIDE_EFFECTS (decl)
7728 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
7732 /* Enforce -mlocal-sdata. */
7733 if (!TARGET_LOCAL_SDATA && !TREE_PUBLIC (decl))
7736 /* Enforce -mextern-sdata. */
7737 if (!TARGET_EXTERN_SDATA && DECL_P (decl))
7739 if (DECL_EXTERNAL (decl))
7741 if (DECL_COMMON (decl) && DECL_INITIAL (decl) == NULL)
7745 /* We have traditionally not treated zero-sized objects as small data,
7746 so this is now effectively part of the ABI. */
7747 size = int_size_in_bytes (TREE_TYPE (decl));
7748 return size > 0 && size <= mips_small_data_threshold;
7751 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
7752 anchors for small data: the GP register acts as an anchor in that
7753 case. We also don't want to use them for PC-relative accesses,
7754 where the PC acts as an anchor. */
7757 mips_use_anchors_for_symbol_p (const_rtx symbol)
7759 switch (mips_classify_symbol (symbol, SYMBOL_CONTEXT_MEM))
7761 case SYMBOL_PC_RELATIVE:
7762 case SYMBOL_GP_RELATIVE:
7766 return default_use_anchors_for_symbol_p (symbol);
7770 /* The MIPS debug format wants all automatic variables and arguments
7771 to be in terms of the virtual frame pointer (stack pointer before
7772 any adjustment in the function), while the MIPS 3.0 linker wants
7773 the frame pointer to be the stack pointer after the initial
7774 adjustment. So, we do the adjustment here. The arg pointer (which
7775 is eliminated) points to the virtual frame pointer, while the frame
7776 pointer (which may be eliminated) points to the stack pointer after
7777 the initial adjustments. */
7780 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
7782 rtx offset2 = const0_rtx;
7783 rtx reg = eliminate_constant_term (addr, &offset2);
7786 offset = INTVAL (offset2);
7788 if (reg == stack_pointer_rtx
7789 || reg == frame_pointer_rtx
7790 || reg == hard_frame_pointer_rtx)
7792 offset -= cfun->machine->frame.total_size;
7793 if (reg == hard_frame_pointer_rtx)
7794 offset += cfun->machine->frame.hard_frame_pointer_offset;
7797 /* sdbout_parms does not want this to crash for unrecognized cases. */
7799 else if (reg != arg_pointer_rtx)
7800 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
7807 /* Implement ASM_OUTPUT_EXTERNAL. */
7810 mips_output_external (FILE *file, tree decl, const char *name)
7812 default_elf_asm_output_external (file, decl, name);
7814 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
7815 set in order to avoid putting out names that are never really
7817 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
7819 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
7821 /* When using assembler macros, emit .extern directives for
7822 all small-data externs so that the assembler knows how
7825 In most cases it would be safe (though pointless) to emit
7826 .externs for other symbols too. One exception is when an
7827 object is within the -G limit but declared by the user to
7828 be in a section other than .sbss or .sdata. */
7829 fputs ("\t.extern\t", file);
7830 assemble_name (file, name);
7831 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n",
7832 int_size_in_bytes (TREE_TYPE (decl)));
7837 /* Implement TARGET_ASM_OUTPUT_SOURCE_FILENAME. */
7840 mips_output_filename (FILE *stream, const char *name)
7842 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
7844 if (write_symbols == DWARF2_DEBUG)
7846 else if (mips_output_filename_first_time)
7848 mips_output_filename_first_time = 0;
7849 num_source_filenames += 1;
7850 current_function_file = name;
7851 fprintf (stream, "\t.file\t%d ", num_source_filenames);
7852 output_quoted_string (stream, name);
7853 putc ('\n', stream);
7855 /* If we are emitting stabs, let dbxout.c handle this (except for
7856 the mips_output_filename_first_time case). */
7857 else if (write_symbols == DBX_DEBUG)
7859 else if (name != current_function_file
7860 && strcmp (name, current_function_file) != 0)
7862 num_source_filenames += 1;
7863 current_function_file = name;
7864 fprintf (stream, "\t.file\t%d ", num_source_filenames);
7865 output_quoted_string (stream, name);
7866 putc ('\n', stream);
7870 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
7872 static void ATTRIBUTE_UNUSED
7873 mips_output_dwarf_dtprel (FILE *file, int size, rtx x)
7878 fputs ("\t.dtprelword\t", file);
7882 fputs ("\t.dtpreldword\t", file);
7888 output_addr_const (file, x);
7889 fputs ("+0x8000", file);
7892 /* Implement TARGET_DWARF_REGISTER_SPAN. */
7895 mips_dwarf_register_span (rtx reg)
7898 enum machine_mode mode;
7900 /* By default, GCC maps increasing register numbers to increasing
7901 memory locations, but paired FPRs are always little-endian,
7902 regardless of the prevailing endianness. */
7903 mode = GET_MODE (reg);
7904 if (FP_REG_P (REGNO (reg))
7905 && TARGET_BIG_ENDIAN
7906 && MAX_FPRS_PER_FMT > 1
7907 && GET_MODE_SIZE (mode) > UNITS_PER_FPREG)
7909 gcc_assert (GET_MODE_SIZE (mode) == UNITS_PER_HWFPVALUE);
7910 high = mips_subword (reg, true);
7911 low = mips_subword (reg, false);
7912 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, high, low));
7918 /* Implement ASM_OUTPUT_ASCII. */
7921 mips_output_ascii (FILE *stream, const char *string, size_t len)
7927 fprintf (stream, "\t.ascii\t\"");
7928 for (i = 0; i < len; i++)
7932 c = (unsigned char) string[i];
7935 if (c == '\\' || c == '\"')
7937 putc ('\\', stream);
7945 fprintf (stream, "\\%03o", c);
7949 if (cur_pos > 72 && i+1 < len)
7952 fprintf (stream, "\"\n\t.ascii\t\"");
7955 fprintf (stream, "\"\n");
7958 /* Emit either a label, .comm, or .lcomm directive. When using assembler
7959 macros, mark the symbol as written so that mips_asm_output_external
7960 won't emit an .extern for it. STREAM is the output file, NAME is the
7961 name of the symbol, INIT_STRING is the string that should be written
7962 before the symbol and FINAL_STRING is the string that should be
7963 written after it. FINAL_STRING is a printf format that consumes the
7964 remaining arguments. */
7967 mips_declare_object (FILE *stream, const char *name, const char *init_string,
7968 const char *final_string, ...)
7972 fputs (init_string, stream);
7973 assemble_name (stream, name);
7974 va_start (ap, final_string);
7975 vfprintf (stream, final_string, ap);
7978 if (!TARGET_EXPLICIT_RELOCS)
7980 tree name_tree = get_identifier (name);
7981 TREE_ASM_WRITTEN (name_tree) = 1;
7985 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
7986 NAME is the name of the object and ALIGN is the required alignment
7987 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
7988 alignment argument. */
7991 mips_declare_common_object (FILE *stream, const char *name,
7992 const char *init_string,
7993 unsigned HOST_WIDE_INT size,
7994 unsigned int align, bool takes_alignment_p)
7996 if (!takes_alignment_p)
7998 size += (align / BITS_PER_UNIT) - 1;
7999 size -= size % (align / BITS_PER_UNIT);
8000 mips_declare_object (stream, name, init_string,
8001 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
8004 mips_declare_object (stream, name, init_string,
8005 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
8006 size, align / BITS_PER_UNIT);
8009 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
8010 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
8013 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
8014 unsigned HOST_WIDE_INT size,
8017 /* If the target wants uninitialized const declarations in
8018 .rdata then don't put them in .comm. */
8019 if (TARGET_EMBEDDED_DATA
8020 && TARGET_UNINIT_CONST_IN_RODATA
8021 && TREE_CODE (decl) == VAR_DECL
8022 && TREE_READONLY (decl)
8023 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
8025 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
8026 targetm.asm_out.globalize_label (stream, name);
8028 switch_to_section (readonly_data_section);
8029 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
8030 mips_declare_object (stream, name, "",
8031 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
8035 mips_declare_common_object (stream, name, "\n\t.comm\t",
8039 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8040 extern int size_directive_output;
8042 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
8043 definitions except that it uses mips_declare_object to emit the label. */
8046 mips_declare_object_name (FILE *stream, const char *name,
8047 tree decl ATTRIBUTE_UNUSED)
8049 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8050 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
8053 size_directive_output = 0;
8054 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
8058 size_directive_output = 1;
8059 size = int_size_in_bytes (TREE_TYPE (decl));
8060 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8063 mips_declare_object (stream, name, "", ":\n");
8066 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
8069 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
8073 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
8074 if (!flag_inhibit_size_directive
8075 && DECL_SIZE (decl) != 0
8078 && DECL_INITIAL (decl) == error_mark_node
8079 && !size_directive_output)
8083 size_directive_output = 1;
8084 size = int_size_in_bytes (TREE_TYPE (decl));
8085 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8090 /* Return the FOO in the name of the ".mdebug.FOO" section associated
8091 with the current ABI. */
8094 mips_mdebug_abi_name (void)
8107 return TARGET_64BIT ? "eabi64" : "eabi32";
8113 /* Implement TARGET_ASM_FILE_START. */
8116 mips_file_start (void)
8118 default_file_start ();
8120 /* Generate a special section to describe the ABI switches used to
8121 produce the resultant binary. This is unnecessary on IRIX and
8122 causes unwanted warnings from the native linker. */
8125 /* Record the ABI itself. Modern versions of binutils encode
8126 this information in the ELF header flags, but GDB needs the
8127 information in order to correctly debug binaries produced by
8128 older binutils. See the function mips_gdbarch_init in
8130 fprintf (asm_out_file, "\t.section .mdebug.%s\n\t.previous\n",
8131 mips_mdebug_abi_name ());
8133 /* There is no ELF header flag to distinguish long32 forms of the
8134 EABI from long64 forms. Emit a special section to help tools
8135 such as GDB. Do the same for o64, which is sometimes used with
8137 if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
8138 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n"
8139 "\t.previous\n", TARGET_LONG64 ? 64 : 32);
8141 #ifdef HAVE_AS_GNU_ATTRIBUTE
8145 /* No floating-point operations, -mno-float. */
8146 if (TARGET_NO_FLOAT)
8148 /* Soft-float code, -msoft-float. */
8149 else if (!TARGET_HARD_FLOAT_ABI)
8151 /* Single-float code, -msingle-float. */
8152 else if (!TARGET_DOUBLE_FLOAT)
8154 /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64. */
8155 else if (!TARGET_64BIT && TARGET_FLOAT64)
8157 /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */
8161 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n", attr);
8166 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
8167 if (TARGET_ABICALLS)
8169 fprintf (asm_out_file, "\t.abicalls\n");
8170 if (TARGET_ABICALLS_PIC0)
8171 fprintf (asm_out_file, "\t.option\tpic0\n");
8174 if (flag_verbose_asm)
8175 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
8177 mips_small_data_threshold, mips_arch_info->name, mips_isa);
8180 /* Make the last instruction frame-related and note that it performs
8181 the operation described by FRAME_PATTERN. */
8184 mips_set_frame_expr (rtx frame_pattern)
8188 insn = get_last_insn ();
8189 RTX_FRAME_RELATED_P (insn) = 1;
8190 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
8195 /* Return a frame-related rtx that stores REG at MEM.
8196 REG must be a single register. */
8199 mips_frame_set (rtx mem, rtx reg)
8203 /* If we're saving the return address register and the DWARF return
8204 address column differs from the hard register number, adjust the
8205 note reg to refer to the former. */
8206 if (REGNO (reg) == RETURN_ADDR_REGNUM
8207 && DWARF_FRAME_RETURN_COLUMN != RETURN_ADDR_REGNUM)
8208 reg = gen_rtx_REG (GET_MODE (reg), DWARF_FRAME_RETURN_COLUMN);
8210 set = gen_rtx_SET (VOIDmode, mem, reg);
8211 RTX_FRAME_RELATED_P (set) = 1;
8216 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
8217 mips16e_s2_s8_regs[X], it must also save the registers in indexes
8218 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
8219 static const unsigned char mips16e_s2_s8_regs[] = {
8220 30, 23, 22, 21, 20, 19, 18
8222 static const unsigned char mips16e_a0_a3_regs[] = {
8226 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
8227 ordered from the uppermost in memory to the lowest in memory. */
8228 static const unsigned char mips16e_save_restore_regs[] = {
8229 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
8232 /* Return the index of the lowest X in the range [0, SIZE) for which
8233 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
8236 mips16e_find_first_register (unsigned int mask, const unsigned char *regs,
8241 for (i = 0; i < size; i++)
8242 if (BITSET_P (mask, regs[i]))
8248 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
8249 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
8250 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
8251 is true for all indexes (X, SIZE). */
8254 mips16e_mask_registers (unsigned int *mask_ptr, const unsigned char *regs,
8255 unsigned int size, unsigned int *num_regs_ptr)
8259 i = mips16e_find_first_register (*mask_ptr, regs, size);
8260 for (i++; i < size; i++)
8261 if (!BITSET_P (*mask_ptr, regs[i]))
8264 *mask_ptr |= 1 << regs[i];
8268 /* Return a simplified form of X using the register values in REG_VALUES.
8269 REG_VALUES[R] is the last value assigned to hard register R, or null
8270 if R has not been modified.
8272 This function is rather limited, but is good enough for our purposes. */
8275 mips16e_collect_propagate_value (rtx x, rtx *reg_values)
8277 x = avoid_constant_pool_reference (x);
8281 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
8282 return simplify_gen_unary (GET_CODE (x), GET_MODE (x),
8283 x0, GET_MODE (XEXP (x, 0)));
8286 if (ARITHMETIC_P (x))
8288 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
8289 rtx x1 = mips16e_collect_propagate_value (XEXP (x, 1), reg_values);
8290 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), x0, x1);
8294 && reg_values[REGNO (x)]
8295 && !rtx_unstable_p (reg_values[REGNO (x)]))
8296 return reg_values[REGNO (x)];
8301 /* Return true if (set DEST SRC) stores an argument register into its
8302 caller-allocated save slot, storing the number of that argument
8303 register in *REGNO_PTR if so. REG_VALUES is as for
8304 mips16e_collect_propagate_value. */
8307 mips16e_collect_argument_save_p (rtx dest, rtx src, rtx *reg_values,
8308 unsigned int *regno_ptr)
8310 unsigned int argno, regno;
8311 HOST_WIDE_INT offset, required_offset;
8314 /* Check that this is a word-mode store. */
8315 if (!MEM_P (dest) || !REG_P (src) || GET_MODE (dest) != word_mode)
8318 /* Check that the register being saved is an unmodified argument
8320 regno = REGNO (src);
8321 if (!IN_RANGE (regno, GP_ARG_FIRST, GP_ARG_LAST) || reg_values[regno])
8323 argno = regno - GP_ARG_FIRST;
8325 /* Check whether the address is an appropriate stack-pointer or
8326 frame-pointer access. */
8327 addr = mips16e_collect_propagate_value (XEXP (dest, 0), reg_values);
8328 mips_split_plus (addr, &base, &offset);
8329 required_offset = cfun->machine->frame.total_size + argno * UNITS_PER_WORD;
8330 if (base == hard_frame_pointer_rtx)
8331 required_offset -= cfun->machine->frame.hard_frame_pointer_offset;
8332 else if (base != stack_pointer_rtx)
8334 if (offset != required_offset)
8341 /* A subroutine of mips_expand_prologue, called only when generating
8342 MIPS16e SAVE instructions. Search the start of the function for any
8343 instructions that save argument registers into their caller-allocated
8344 save slots. Delete such instructions and return a value N such that
8345 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
8346 instructions redundant. */
8349 mips16e_collect_argument_saves (void)
8351 rtx reg_values[FIRST_PSEUDO_REGISTER];
8352 rtx insn, next, set, dest, src;
8353 unsigned int nargs, regno;
8355 push_topmost_sequence ();
8357 memset (reg_values, 0, sizeof (reg_values));
8358 for (insn = get_insns (); insn; insn = next)
8360 next = NEXT_INSN (insn);
8361 if (NOTE_P (insn) || DEBUG_INSN_P (insn))
8367 set = PATTERN (insn);
8368 if (GET_CODE (set) != SET)
8371 dest = SET_DEST (set);
8372 src = SET_SRC (set);
8373 if (mips16e_collect_argument_save_p (dest, src, reg_values, ®no))
8375 if (!BITSET_P (cfun->machine->frame.mask, regno))
8378 nargs = MAX (nargs, (regno - GP_ARG_FIRST) + 1);
8381 else if (REG_P (dest) && GET_MODE (dest) == word_mode)
8382 reg_values[REGNO (dest)]
8383 = mips16e_collect_propagate_value (src, reg_values);
8387 pop_topmost_sequence ();
8392 /* Return a move between register REGNO and memory location SP + OFFSET.
8393 Make the move a load if RESTORE_P, otherwise make it a frame-related
8397 mips16e_save_restore_reg (bool restore_p, HOST_WIDE_INT offset,
8402 mem = gen_frame_mem (SImode, plus_constant (stack_pointer_rtx, offset));
8403 reg = gen_rtx_REG (SImode, regno);
8405 ? gen_rtx_SET (VOIDmode, reg, mem)
8406 : mips_frame_set (mem, reg));
8409 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
8410 The instruction must:
8412 - Allocate or deallocate SIZE bytes in total; SIZE is known
8415 - Save or restore as many registers in *MASK_PTR as possible.
8416 The instruction saves the first registers at the top of the
8417 allocated area, with the other registers below it.
8419 - Save NARGS argument registers above the allocated area.
8421 (NARGS is always zero if RESTORE_P.)
8423 The SAVE and RESTORE instructions cannot save and restore all general
8424 registers, so there may be some registers left over for the caller to
8425 handle. Destructively modify *MASK_PTR so that it contains the registers
8426 that still need to be saved or restored. The caller can save these
8427 registers in the memory immediately below *OFFSET_PTR, which is a
8428 byte offset from the bottom of the allocated stack area. */
8431 mips16e_build_save_restore (bool restore_p, unsigned int *mask_ptr,
8432 HOST_WIDE_INT *offset_ptr, unsigned int nargs,
8436 HOST_WIDE_INT offset, top_offset;
8437 unsigned int i, regno;
8440 gcc_assert (cfun->machine->frame.num_fp == 0);
8442 /* Calculate the number of elements in the PARALLEL. We need one element
8443 for the stack adjustment, one for each argument register save, and one
8444 for each additional register move. */
8446 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
8447 if (BITSET_P (*mask_ptr, mips16e_save_restore_regs[i]))
8450 /* Create the final PARALLEL. */
8451 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (n));
8454 /* Add the stack pointer adjustment. */
8455 set = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8456 plus_constant (stack_pointer_rtx,
8457 restore_p ? size : -size));
8458 RTX_FRAME_RELATED_P (set) = 1;
8459 XVECEXP (pattern, 0, n++) = set;
8461 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8462 top_offset = restore_p ? size : 0;
8464 /* Save the arguments. */
8465 for (i = 0; i < nargs; i++)
8467 offset = top_offset + i * UNITS_PER_WORD;
8468 set = mips16e_save_restore_reg (restore_p, offset, GP_ARG_FIRST + i);
8469 XVECEXP (pattern, 0, n++) = set;
8472 /* Then fill in the other register moves. */
8473 offset = top_offset;
8474 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
8476 regno = mips16e_save_restore_regs[i];
8477 if (BITSET_P (*mask_ptr, regno))
8479 offset -= UNITS_PER_WORD;
8480 set = mips16e_save_restore_reg (restore_p, offset, regno);
8481 XVECEXP (pattern, 0, n++) = set;
8482 *mask_ptr &= ~(1 << regno);
8486 /* Tell the caller what offset it should use for the remaining registers. */
8487 *offset_ptr = size + (offset - top_offset);
8489 gcc_assert (n == XVECLEN (pattern, 0));
8494 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
8495 pointer. Return true if PATTERN matches the kind of instruction
8496 generated by mips16e_build_save_restore. If INFO is nonnull,
8497 initialize it when returning true. */
8500 mips16e_save_restore_pattern_p (rtx pattern, HOST_WIDE_INT adjust,
8501 struct mips16e_save_restore_info *info)
8503 unsigned int i, nargs, mask, extra;
8504 HOST_WIDE_INT top_offset, save_offset, offset;
8505 rtx set, reg, mem, base;
8508 if (!GENERATE_MIPS16E_SAVE_RESTORE)
8511 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8512 top_offset = adjust > 0 ? adjust : 0;
8514 /* Interpret all other members of the PARALLEL. */
8515 save_offset = top_offset - UNITS_PER_WORD;
8519 for (n = 1; n < XVECLEN (pattern, 0); n++)
8521 /* Check that we have a SET. */
8522 set = XVECEXP (pattern, 0, n);
8523 if (GET_CODE (set) != SET)
8526 /* Check that the SET is a load (if restoring) or a store
8528 mem = adjust > 0 ? SET_SRC (set) : SET_DEST (set);
8532 /* Check that the address is the sum of the stack pointer and a
8533 possibly-zero constant offset. */
8534 mips_split_plus (XEXP (mem, 0), &base, &offset);
8535 if (base != stack_pointer_rtx)
8538 /* Check that SET's other operand is a register. */
8539 reg = adjust > 0 ? SET_DEST (set) : SET_SRC (set);
8543 /* Check for argument saves. */
8544 if (offset == top_offset + nargs * UNITS_PER_WORD
8545 && REGNO (reg) == GP_ARG_FIRST + nargs)
8547 else if (offset == save_offset)
8549 while (mips16e_save_restore_regs[i++] != REGNO (reg))
8550 if (i == ARRAY_SIZE (mips16e_save_restore_regs))
8553 mask |= 1 << REGNO (reg);
8554 save_offset -= UNITS_PER_WORD;
8560 /* Check that the restrictions on register ranges are met. */
8562 mips16e_mask_registers (&mask, mips16e_s2_s8_regs,
8563 ARRAY_SIZE (mips16e_s2_s8_regs), &extra);
8564 mips16e_mask_registers (&mask, mips16e_a0_a3_regs,
8565 ARRAY_SIZE (mips16e_a0_a3_regs), &extra);
8569 /* Make sure that the topmost argument register is not saved twice.
8570 The checks above ensure that the same is then true for the other
8571 argument registers. */
8572 if (nargs > 0 && BITSET_P (mask, GP_ARG_FIRST + nargs - 1))
8575 /* Pass back information, if requested. */
8578 info->nargs = nargs;
8580 info->size = (adjust > 0 ? adjust : -adjust);
8586 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
8587 for the register range [MIN_REG, MAX_REG]. Return a pointer to
8588 the null terminator. */
8591 mips16e_add_register_range (char *s, unsigned int min_reg,
8592 unsigned int max_reg)
8594 if (min_reg != max_reg)
8595 s += sprintf (s, ",%s-%s", reg_names[min_reg], reg_names[max_reg]);
8597 s += sprintf (s, ",%s", reg_names[min_reg]);
8601 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
8602 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
8605 mips16e_output_save_restore (rtx pattern, HOST_WIDE_INT adjust)
8607 static char buffer[300];
8609 struct mips16e_save_restore_info info;
8610 unsigned int i, end;
8613 /* Parse the pattern. */
8614 if (!mips16e_save_restore_pattern_p (pattern, adjust, &info))
8617 /* Add the mnemonic. */
8618 s = strcpy (buffer, adjust > 0 ? "restore\t" : "save\t");
8621 /* Save the arguments. */
8623 s += sprintf (s, "%s-%s,", reg_names[GP_ARG_FIRST],
8624 reg_names[GP_ARG_FIRST + info.nargs - 1]);
8625 else if (info.nargs == 1)
8626 s += sprintf (s, "%s,", reg_names[GP_ARG_FIRST]);
8628 /* Emit the amount of stack space to allocate or deallocate. */
8629 s += sprintf (s, "%d", (int) info.size);
8631 /* Save or restore $16. */
8632 if (BITSET_P (info.mask, 16))
8633 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 16]);
8635 /* Save or restore $17. */
8636 if (BITSET_P (info.mask, 17))
8637 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 17]);
8639 /* Save or restore registers in the range $s2...$s8, which
8640 mips16e_s2_s8_regs lists in decreasing order. Note that this
8641 is a software register range; the hardware registers are not
8642 numbered consecutively. */
8643 end = ARRAY_SIZE (mips16e_s2_s8_regs);
8644 i = mips16e_find_first_register (info.mask, mips16e_s2_s8_regs, end);
8646 s = mips16e_add_register_range (s, mips16e_s2_s8_regs[end - 1],
8647 mips16e_s2_s8_regs[i]);
8649 /* Save or restore registers in the range $a0...$a3. */
8650 end = ARRAY_SIZE (mips16e_a0_a3_regs);
8651 i = mips16e_find_first_register (info.mask, mips16e_a0_a3_regs, end);
8653 s = mips16e_add_register_range (s, mips16e_a0_a3_regs[i],
8654 mips16e_a0_a3_regs[end - 1]);
8656 /* Save or restore $31. */
8657 if (BITSET_P (info.mask, RETURN_ADDR_REGNUM))
8658 s += sprintf (s, ",%s", reg_names[RETURN_ADDR_REGNUM]);
8663 /* Return true if the current function returns its value in a floating-point
8664 register in MIPS16 mode. */
8667 mips16_cfun_returns_in_fpr_p (void)
8669 tree return_type = DECL_RESULT (current_function_decl);
8670 return (TARGET_MIPS16
8671 && TARGET_HARD_FLOAT_ABI
8672 && !aggregate_value_p (return_type, current_function_decl)
8673 && mips_return_mode_in_fpr_p (DECL_MODE (return_type)));
8676 /* Return true if predicate PRED is true for at least one instruction.
8677 Cache the result in *CACHE, and assume that the result is true
8678 if *CACHE is already true. */
8681 mips_find_gp_ref (bool *cache, bool (*pred) (rtx))
8687 push_topmost_sequence ();
8688 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8689 if (USEFUL_INSN_P (insn) && pred (insn))
8694 pop_topmost_sequence ();
8699 /* Return true if INSN refers to the global pointer in an "inflexible" way.
8700 See mips_cfun_has_inflexible_gp_ref_p for details. */
8703 mips_insn_has_inflexible_gp_ref_p (rtx insn)
8705 /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE
8706 indicate that the target could be a traditional MIPS
8707 lazily-binding stub. */
8708 return find_reg_fusage (insn, USE, pic_offset_table_rtx);
8711 /* Return true if the current function refers to the global pointer
8712 in a way that forces $28 to be valid. This means that we can't
8713 change the choice of global pointer, even for NewABI code.
8715 One example of this (and one which needs several checks) is that
8716 $28 must be valid when calling traditional MIPS lazy-binding stubs.
8717 (This restriction does not apply to PLTs.) */
8720 mips_cfun_has_inflexible_gp_ref_p (void)
8722 /* If the function has a nonlocal goto, $28 must hold the correct
8723 global pointer for the target function. That is, the target
8724 of the goto implicitly uses $28. */
8725 if (crtl->has_nonlocal_goto)
8728 if (TARGET_ABICALLS_PIC2)
8730 /* Symbolic accesses implicitly use the global pointer unless
8731 -mexplicit-relocs is in effect. JAL macros to symbolic addresses
8732 might go to traditional MIPS lazy-binding stubs. */
8733 if (!TARGET_EXPLICIT_RELOCS)
8736 /* FUNCTION_PROFILER includes a JAL to _mcount, which again
8737 can be lazily-bound. */
8741 /* MIPS16 functions that return in FPRs need to call an
8742 external libgcc routine. This call is only made explict
8743 during mips_expand_epilogue, and it too might be lazily bound. */
8744 if (mips16_cfun_returns_in_fpr_p ())
8748 return mips_find_gp_ref (&cfun->machine->has_inflexible_gp_insn_p,
8749 mips_insn_has_inflexible_gp_ref_p);
8752 /* Return true if INSN refers to the global pointer in a "flexible" way.
8753 See mips_cfun_has_flexible_gp_ref_p for details. */
8756 mips_insn_has_flexible_gp_ref_p (rtx insn)
8758 return (get_attr_got (insn) != GOT_UNSET
8759 || mips_small_data_pattern_p (PATTERN (insn))
8760 || reg_overlap_mentioned_p (pic_offset_table_rtx, PATTERN (insn)));
8763 /* Return true if the current function references the global pointer,
8764 but if those references do not inherently require the global pointer
8765 to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */
8768 mips_cfun_has_flexible_gp_ref_p (void)
8770 /* Reload can sometimes introduce constant pool references
8771 into a function that otherwise didn't need them. For example,
8772 suppose we have an instruction like:
8774 (set (reg:DF R1) (float:DF (reg:SI R2)))
8776 If R2 turns out to be a constant such as 1, the instruction may
8777 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
8778 the option of using this constant if R2 doesn't get allocated
8781 In cases like these, reload will have added the constant to the
8782 pool but no instruction will yet refer to it. */
8783 if (TARGET_ABICALLS_PIC2 && !reload_completed && crtl->uses_const_pool)
8786 return mips_find_gp_ref (&cfun->machine->has_flexible_gp_insn_p,
8787 mips_insn_has_flexible_gp_ref_p);
8790 /* Return the register that should be used as the global pointer
8791 within this function. Return INVALID_REGNUM if the function
8792 doesn't need a global pointer. */
8795 mips_global_pointer (void)
8799 /* $gp is always available unless we're using a GOT. */
8800 if (!TARGET_USE_GOT)
8801 return GLOBAL_POINTER_REGNUM;
8803 /* If there are inflexible references to $gp, we must use the
8804 standard register. */
8805 if (mips_cfun_has_inflexible_gp_ref_p ())
8806 return GLOBAL_POINTER_REGNUM;
8808 /* If there are no current references to $gp, then the only uses
8809 we can introduce later are those involved in long branches. */
8810 if (TARGET_ABSOLUTE_JUMPS && !mips_cfun_has_flexible_gp_ref_p ())
8811 return INVALID_REGNUM;
8813 /* If the global pointer is call-saved, try to use a call-clobbered
8815 if (TARGET_CALL_SAVED_GP && current_function_is_leaf)
8816 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
8817 if (!df_regs_ever_live_p (regno)
8818 && call_really_used_regs[regno]
8819 && !fixed_regs[regno]
8820 && regno != PIC_FUNCTION_ADDR_REGNUM)
8823 return GLOBAL_POINTER_REGNUM;
8826 /* Return true if the current function's prologue must load the global
8827 pointer value into pic_offset_table_rtx and store the same value in
8828 the function's cprestore slot (if any).
8830 One problem we have to deal with is that, when emitting GOT-based
8831 position independent code, long-branch sequences will need to load
8832 the address of the branch target from the GOT. We don't know until
8833 the very end of compilation whether (and where) the function needs
8834 long branches, so we must ensure that _any_ branch can access the
8835 global pointer in some form. However, we do not want to pessimize
8836 the usual case in which all branches are short.
8838 We handle this as follows:
8840 (1) During reload, we set cfun->machine->global_pointer to
8841 INVALID_REGNUM if we _know_ that the current function
8842 doesn't need a global pointer. This is only valid if
8843 long branches don't need the GOT.
8845 Otherwise, we assume that we might need a global pointer
8846 and pick an appropriate register.
8848 (2) If cfun->machine->global_pointer != INVALID_REGNUM,
8849 we ensure that the global pointer is available at every
8850 block boundary bar entry and exit. We do this in one of two ways:
8852 - If the function has a cprestore slot, we ensure that this
8853 slot is valid at every branch. However, as explained in
8854 point (6) below, there is no guarantee that pic_offset_table_rtx
8855 itself is valid if new uses of the global pointer are introduced
8856 after the first post-epilogue split.
8858 We guarantee that the cprestore slot is valid by loading it
8859 into a fake register, CPRESTORE_SLOT_REGNUM. We then make
8860 this register live at every block boundary bar function entry
8861 and exit. It is then invalid to move the load (and thus the
8862 preceding store) across a block boundary.
8864 - If the function has no cprestore slot, we guarantee that
8865 pic_offset_table_rtx itself is valid at every branch.
8867 See mips_eh_uses for the handling of the register liveness.
8869 (3) During prologue and epilogue generation, we emit "ghost"
8870 placeholder instructions to manipulate the global pointer.
8872 (4) During prologue generation, we set cfun->machine->must_initialize_gp_p
8873 and cfun->machine->must_restore_gp_when_clobbered_p if we already know
8874 that the function needs a global pointer. (There is no need to set
8875 them earlier than this, and doing it as late as possible leads to
8876 fewer false positives.)
8878 (5) If cfun->machine->must_initialize_gp_p is true during a
8879 split_insns pass, we split the ghost instructions into real
8880 instructions. These split instructions can then be optimized in
8881 the usual way. Otherwise, we keep the ghost instructions intact,
8882 and optimize for the case where they aren't needed. We still
8883 have the option of splitting them later, if we need to introduce
8884 new uses of the global pointer.
8886 For example, the scheduler ignores a ghost instruction that
8887 stores $28 to the stack, but it handles the split form of
8888 the ghost instruction as an ordinary store.
8890 (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p
8891 is true during the first post-epilogue split_insns pass, we split
8892 calls and restore_gp patterns into instructions that explicitly
8893 load pic_offset_table_rtx from the cprestore slot. Otherwise,
8894 we split these patterns into instructions that _don't_ load from
8897 If cfun->machine->must_restore_gp_when_clobbered_p is true at the
8898 time of the split, then any instructions that exist at that time
8899 can make free use of pic_offset_table_rtx. However, if we want
8900 to introduce new uses of the global pointer after the split,
8901 we must explicitly load the value from the cprestore slot, since
8902 pic_offset_table_rtx itself might not be valid at a given point
8905 The idea is that we want to be able to delete redundant
8906 loads from the cprestore slot in the usual case where no
8907 long branches are needed.
8909 (7) If cfun->machine->must_initialize_gp_p is still false at the end
8910 of md_reorg, we decide whether the global pointer is needed for
8911 long branches. If so, we set cfun->machine->must_initialize_gp_p
8912 to true and split the ghost instructions into real instructions
8915 Note that the ghost instructions must have a zero length for three reasons:
8917 - Giving the length of the underlying $gp sequence might cause
8918 us to use long branches in cases where they aren't really needed.
8920 - They would perturb things like alignment calculations.
8922 - More importantly, the hazard detection in md_reorg relies on
8923 empty instructions having a zero length.
8925 If we find a long branch and split the ghost instructions at the
8926 end of md_reorg, the split could introduce more long branches.
8927 That isn't a problem though, because we still do the split before
8928 the final shorten_branches pass.
8930 This is extremely ugly, but it seems like the best compromise between
8931 correctness and efficiency. */
8934 mips_must_initialize_gp_p (void)
8936 return cfun->machine->must_initialize_gp_p;
8939 /* Return true if REGNO is a register that is ordinarily call-clobbered
8940 but must nevertheless be preserved by an interrupt handler. */
8943 mips_interrupt_extra_call_saved_reg_p (unsigned int regno)
8945 if (MD_REG_P (regno))
8948 if (TARGET_DSP && DSP_ACC_REG_P (regno))
8951 if (GP_REG_P (regno) && !cfun->machine->use_shadow_register_set_p)
8953 /* $0 is hard-wired. */
8954 if (regno == GP_REG_FIRST)
8957 /* The interrupt handler can treat kernel registers as
8958 scratch registers. */
8959 if (KERNEL_REG_P (regno))
8962 /* The function will return the stack pointer to its original value
8964 if (regno == STACK_POINTER_REGNUM)
8967 /* Otherwise, return true for registers that aren't ordinarily
8969 return call_really_used_regs[regno];
8975 /* Return true if the current function should treat register REGNO
8979 mips_cfun_call_saved_reg_p (unsigned int regno)
8981 /* If the user makes an ordinarily-call-saved register global,
8982 that register is no longer call-saved. */
8983 if (global_regs[regno])
8986 /* Interrupt handlers need to save extra registers. */
8987 if (cfun->machine->interrupt_handler_p
8988 && mips_interrupt_extra_call_saved_reg_p (regno))
8991 /* call_insns preserve $28 unless they explicitly say otherwise,
8992 so call_really_used_regs[] treats $28 as call-saved. However,
8993 we want the ABI property rather than the default call_insn
8995 return (regno == GLOBAL_POINTER_REGNUM
8996 ? TARGET_CALL_SAVED_GP
8997 : !call_really_used_regs[regno]);
9000 /* Return true if the function body might clobber register REGNO.
9001 We know that REGNO is call-saved. */
9004 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno)
9006 /* Some functions should be treated as clobbering all call-saved
9008 if (crtl->saves_all_registers)
9011 /* DF handles cases where a register is explicitly referenced in
9012 the rtl. Incoming values are passed in call-clobbered registers,
9013 so we can assume that any live call-saved register is set within
9015 if (df_regs_ever_live_p (regno))
9018 /* Check for registers that are clobbered by FUNCTION_PROFILER.
9019 These clobbers are not explicit in the rtl. */
9020 if (crtl->profile && MIPS_SAVE_REG_FOR_PROFILING_P (regno))
9023 /* If we're using a call-saved global pointer, the function's
9024 prologue will need to set it up. */
9025 if (cfun->machine->global_pointer == regno)
9028 /* The function's prologue will need to set the frame pointer if
9029 frame_pointer_needed. */
9030 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
9033 /* If a MIPS16 function returns a value in FPRs, its epilogue
9034 will need to call an external libgcc routine. This yet-to-be
9035 generated call_insn will clobber $31. */
9036 if (regno == RETURN_ADDR_REGNUM && mips16_cfun_returns_in_fpr_p ())
9039 /* If REGNO is ordinarily call-clobbered, we must assume that any
9040 called function could modify it. */
9041 if (cfun->machine->interrupt_handler_p
9042 && !current_function_is_leaf
9043 && mips_interrupt_extra_call_saved_reg_p (regno))
9049 /* Return true if the current function must save register REGNO. */
9052 mips_save_reg_p (unsigned int regno)
9054 if (mips_cfun_call_saved_reg_p (regno))
9056 if (mips_cfun_might_clobber_call_saved_reg_p (regno))
9059 /* Save both registers in an FPR pair if either one is used. This is
9060 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
9061 register to be used without the even register. */
9062 if (FP_REG_P (regno)
9063 && MAX_FPRS_PER_FMT == 2
9064 && mips_cfun_might_clobber_call_saved_reg_p (regno + 1))
9068 /* We need to save the incoming return address if __builtin_eh_return
9069 is being used to set a different return address. */
9070 if (regno == RETURN_ADDR_REGNUM && crtl->calls_eh_return)
9076 /* Populate the current function's mips_frame_info structure.
9078 MIPS stack frames look like:
9080 +-------------------------------+
9082 | incoming stack arguments |
9084 +-------------------------------+
9086 | caller-allocated save area |
9087 A | for register arguments |
9089 +-------------------------------+ <-- incoming stack pointer
9091 | callee-allocated save area |
9092 B | for arguments that are |
9093 | split between registers and |
9096 +-------------------------------+ <-- arg_pointer_rtx
9098 C | callee-allocated save area |
9099 | for register varargs |
9101 +-------------------------------+ <-- frame_pointer_rtx
9102 | | + cop0_sp_offset
9103 | COP0 reg save area | + UNITS_PER_WORD
9105 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
9106 | | + UNITS_PER_WORD
9107 | accumulator save area |
9109 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
9110 | | + UNITS_PER_HWFPVALUE
9113 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset
9114 | | + UNITS_PER_WORD
9117 +-------------------------------+ <-- frame_pointer_rtx with
9118 | | \ -fstack-protector
9119 | local variables | | var_size
9121 +-------------------------------+
9123 | $gp save area | | cprestore_size
9125 P +-------------------------------+ <-- hard_frame_pointer_rtx for
9127 | outgoing stack arguments | |
9129 +-------------------------------+ | args_size
9131 | caller-allocated save area | |
9132 | for register arguments | |
9134 +-------------------------------+ <-- stack_pointer_rtx
9135 frame_pointer_rtx without
9137 hard_frame_pointer_rtx for
9140 At least two of A, B and C will be empty.
9142 Dynamic stack allocations such as alloca insert data at point P.
9143 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
9144 hard_frame_pointer_rtx unchanged. */
9147 mips_compute_frame_info (void)
9149 struct mips_frame_info *frame;
9150 HOST_WIDE_INT offset, size;
9151 unsigned int regno, i;
9153 /* Set this function's interrupt properties. */
9154 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
9157 error ("the %<interrupt%> attribute requires a MIPS32r2 processor");
9158 else if (TARGET_HARD_FLOAT)
9159 error ("the %<interrupt%> attribute requires %<-msoft-float%>");
9160 else if (TARGET_MIPS16)
9161 error ("interrupt handlers cannot be MIPS16 functions");
9164 cfun->machine->interrupt_handler_p = true;
9165 cfun->machine->use_shadow_register_set_p =
9166 mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl));
9167 cfun->machine->keep_interrupts_masked_p =
9168 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl));
9169 cfun->machine->use_debug_exception_return_p =
9170 mips_use_debug_exception_return_p (TREE_TYPE
9171 (current_function_decl));
9175 frame = &cfun->machine->frame;
9176 memset (frame, 0, sizeof (*frame));
9177 size = get_frame_size ();
9179 cfun->machine->global_pointer = mips_global_pointer ();
9181 /* The first two blocks contain the outgoing argument area and the $gp save
9182 slot. This area isn't needed in leaf functions, but if the
9183 target-independent frame size is nonzero, we have already committed to
9184 allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */
9185 if ((size == 0 || FRAME_GROWS_DOWNWARD) && current_function_is_leaf)
9187 /* The MIPS 3.0 linker does not like functions that dynamically
9188 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
9189 looks like we are trying to create a second frame pointer to the
9190 function, so allocate some stack space to make it happy. */
9191 if (cfun->calls_alloca)
9192 frame->args_size = REG_PARM_STACK_SPACE (cfun->decl);
9194 frame->args_size = 0;
9195 frame->cprestore_size = 0;
9199 frame->args_size = crtl->outgoing_args_size;
9200 frame->cprestore_size = MIPS_GP_SAVE_AREA_SIZE;
9202 offset = frame->args_size + frame->cprestore_size;
9204 /* Move above the local variables. */
9205 frame->var_size = MIPS_STACK_ALIGN (size);
9206 offset += frame->var_size;
9208 /* Find out which GPRs we need to save. */
9209 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
9210 if (mips_save_reg_p (regno))
9213 frame->mask |= 1 << (regno - GP_REG_FIRST);
9216 /* If this function calls eh_return, we must also save and restore the
9217 EH data registers. */
9218 if (crtl->calls_eh_return)
9219 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; i++)
9222 frame->mask |= 1 << (EH_RETURN_DATA_REGNO (i) - GP_REG_FIRST);
9225 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
9226 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
9227 save all later registers too. */
9228 if (GENERATE_MIPS16E_SAVE_RESTORE)
9230 mips16e_mask_registers (&frame->mask, mips16e_s2_s8_regs,
9231 ARRAY_SIZE (mips16e_s2_s8_regs), &frame->num_gp);
9232 mips16e_mask_registers (&frame->mask, mips16e_a0_a3_regs,
9233 ARRAY_SIZE (mips16e_a0_a3_regs), &frame->num_gp);
9236 /* Move above the GPR save area. */
9237 if (frame->num_gp > 0)
9239 offset += MIPS_STACK_ALIGN (frame->num_gp * UNITS_PER_WORD);
9240 frame->gp_sp_offset = offset - UNITS_PER_WORD;
9243 /* Find out which FPRs we need to save. This loop must iterate over
9244 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
9245 if (TARGET_HARD_FLOAT)
9246 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += MAX_FPRS_PER_FMT)
9247 if (mips_save_reg_p (regno))
9249 frame->num_fp += MAX_FPRS_PER_FMT;
9250 frame->fmask |= ~(~0 << MAX_FPRS_PER_FMT) << (regno - FP_REG_FIRST);
9253 /* Move above the FPR save area. */
9254 if (frame->num_fp > 0)
9256 offset += MIPS_STACK_ALIGN (frame->num_fp * UNITS_PER_FPREG);
9257 frame->fp_sp_offset = offset - UNITS_PER_HWFPVALUE;
9260 /* Add in space for the interrupt context information. */
9261 if (cfun->machine->interrupt_handler_p)
9264 if (mips_save_reg_p (LO_REGNUM) || mips_save_reg_p (HI_REGNUM))
9267 frame->acc_mask |= (1 << 0);
9270 /* Check accumulators 1, 2, 3. */
9271 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
9272 if (mips_save_reg_p (i) || mips_save_reg_p (i + 1))
9275 frame->acc_mask |= 1 << (((i - DSP_ACC_REG_FIRST) / 2) + 1);
9278 /* All interrupt context functions need space to preserve STATUS. */
9279 frame->num_cop0_regs++;
9281 /* If we don't keep interrupts masked, we need to save EPC. */
9282 if (!cfun->machine->keep_interrupts_masked_p)
9283 frame->num_cop0_regs++;
9286 /* Move above the accumulator save area. */
9287 if (frame->num_acc > 0)
9289 /* Each accumulator needs 2 words. */
9290 offset += frame->num_acc * 2 * UNITS_PER_WORD;
9291 frame->acc_sp_offset = offset - UNITS_PER_WORD;
9294 /* Move above the COP0 register save area. */
9295 if (frame->num_cop0_regs > 0)
9297 offset += frame->num_cop0_regs * UNITS_PER_WORD;
9298 frame->cop0_sp_offset = offset - UNITS_PER_WORD;
9301 /* Move above the callee-allocated varargs save area. */
9302 offset += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
9303 frame->arg_pointer_offset = offset;
9305 /* Move above the callee-allocated area for pretend stack arguments. */
9306 offset += crtl->args.pretend_args_size;
9307 frame->total_size = offset;
9309 /* Work out the offsets of the save areas from the top of the frame. */
9310 if (frame->gp_sp_offset > 0)
9311 frame->gp_save_offset = frame->gp_sp_offset - offset;
9312 if (frame->fp_sp_offset > 0)
9313 frame->fp_save_offset = frame->fp_sp_offset - offset;
9314 if (frame->acc_sp_offset > 0)
9315 frame->acc_save_offset = frame->acc_sp_offset - offset;
9316 if (frame->num_cop0_regs > 0)
9317 frame->cop0_save_offset = frame->cop0_sp_offset - offset;
9319 /* MIPS16 code offsets the frame pointer by the size of the outgoing
9320 arguments. This tends to increase the chances of using unextended
9321 instructions for local variables and incoming arguments. */
9323 frame->hard_frame_pointer_offset = frame->args_size;
9326 /* Return the style of GP load sequence that is being used for the
9327 current function. */
9329 enum mips_loadgp_style
9330 mips_current_loadgp_style (void)
9332 if (!TARGET_USE_GOT || cfun->machine->global_pointer == INVALID_REGNUM)
9338 if (TARGET_ABSOLUTE_ABICALLS)
9339 return LOADGP_ABSOLUTE;
9341 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
9344 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
9347 mips_frame_pointer_required (void)
9349 /* If the function contains dynamic stack allocations, we need to
9350 use the frame pointer to access the static parts of the frame. */
9351 if (cfun->calls_alloca)
9354 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
9355 reload may be unable to compute the address of a local variable,
9356 since there is no way to add a large constant to the stack pointer
9357 without using a second temporary register. */
9360 mips_compute_frame_info ();
9361 if (!SMALL_OPERAND (cfun->machine->frame.total_size))
9368 /* Make sure that we're not trying to eliminate to the wrong hard frame
9372 mips_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
9374 return (to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM);
9377 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
9378 or argument pointer. TO is either the stack pointer or hard frame
9382 mips_initial_elimination_offset (int from, int to)
9384 HOST_WIDE_INT offset;
9386 mips_compute_frame_info ();
9388 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */
9391 case FRAME_POINTER_REGNUM:
9392 if (FRAME_GROWS_DOWNWARD)
9393 offset = (cfun->machine->frame.args_size
9394 + cfun->machine->frame.cprestore_size
9395 + cfun->machine->frame.var_size);
9400 case ARG_POINTER_REGNUM:
9401 offset = cfun->machine->frame.arg_pointer_offset;
9408 if (to == HARD_FRAME_POINTER_REGNUM)
9409 offset -= cfun->machine->frame.hard_frame_pointer_offset;
9414 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
9417 mips_extra_live_on_entry (bitmap regs)
9421 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
9422 the global pointer. */
9423 if (!TARGET_ABSOLUTE_ABICALLS)
9424 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
9426 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
9427 the global pointer. */
9429 bitmap_set_bit (regs, MIPS16_PIC_TEMP_REGNUM);
9431 /* See the comment above load_call<mode> for details. */
9432 bitmap_set_bit (regs, GOT_VERSION_REGNUM);
9436 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
9440 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
9445 return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);
9448 /* Emit code to change the current function's return address to
9449 ADDRESS. SCRATCH is available as a scratch register, if needed.
9450 ADDRESS and SCRATCH are both word-mode GPRs. */
9453 mips_set_return_address (rtx address, rtx scratch)
9457 gcc_assert (BITSET_P (cfun->machine->frame.mask, RETURN_ADDR_REGNUM));
9458 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
9459 cfun->machine->frame.gp_sp_offset);
9460 mips_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address);
9463 /* Return true if the current function has a cprestore slot. */
9466 mips_cfun_has_cprestore_slot_p (void)
9468 return (cfun->machine->global_pointer != INVALID_REGNUM
9469 && cfun->machine->frame.cprestore_size > 0);
9472 /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the
9473 cprestore slot. LOAD_P is true if the caller wants to load from
9474 the cprestore slot; it is false if the caller wants to store to
9478 mips_get_cprestore_base_and_offset (rtx *base, HOST_WIDE_INT *offset,
9481 const struct mips_frame_info *frame;
9483 frame = &cfun->machine->frame;
9484 /* .cprestore always uses the stack pointer instead of the frame pointer.
9485 We have a free choice for direct stores for non-MIPS16 functions,
9486 and for MIPS16 functions whose cprestore slot is in range of the
9487 stack pointer. Using the stack pointer would sometimes give more
9488 (early) scheduling freedom, but using the frame pointer would
9489 sometimes give more (late) scheduling freedom. It's hard to
9490 predict which applies to a given function, so let's keep things
9493 Loads must always use the frame pointer in functions that call
9494 alloca, and there's little benefit to using the stack pointer
9496 if (frame_pointer_needed && !(TARGET_CPRESTORE_DIRECTIVE && !load_p))
9498 *base = hard_frame_pointer_rtx;
9499 *offset = frame->args_size - frame->hard_frame_pointer_offset;
9503 *base = stack_pointer_rtx;
9504 *offset = frame->args_size;
9508 /* Return true if X is the load or store address of the cprestore slot;
9509 LOAD_P says which. */
9512 mips_cprestore_address_p (rtx x, bool load_p)
9514 rtx given_base, required_base;
9515 HOST_WIDE_INT given_offset, required_offset;
9517 mips_split_plus (x, &given_base, &given_offset);
9518 mips_get_cprestore_base_and_offset (&required_base, &required_offset, load_p);
9519 return given_base == required_base && given_offset == required_offset;
9522 /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are
9523 going to load from it, false if we are going to store to it.
9524 Use TEMP as a temporary register if need be. */
9527 mips_cprestore_slot (rtx temp, bool load_p)
9530 HOST_WIDE_INT offset;
9532 mips_get_cprestore_base_and_offset (&base, &offset, load_p);
9533 return gen_frame_mem (Pmode, mips_add_offset (temp, base, offset));
9536 /* Emit instructions to save global pointer value GP into cprestore
9537 slot MEM. OFFSET is the offset that MEM applies to the base register.
9539 MEM may not be a legitimate address. If it isn't, TEMP is a
9540 temporary register that can be used, otherwise it is a SCRATCH. */
9543 mips_save_gp_to_cprestore_slot (rtx mem, rtx offset, rtx gp, rtx temp)
9545 if (TARGET_CPRESTORE_DIRECTIVE)
9547 gcc_assert (gp == pic_offset_table_rtx);
9548 emit_insn (gen_cprestore (mem, offset));
9551 mips_emit_move (mips_cprestore_slot (temp, false), gp);
9554 /* Restore $gp from its save slot, using TEMP as a temporary base register
9555 if need be. This function is for o32 and o64 abicalls only.
9557 See mips_must_initialize_gp_p for details about how we manage the
9561 mips_restore_gp_from_cprestore_slot (rtx temp)
9563 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI && epilogue_completed);
9565 if (!cfun->machine->must_restore_gp_when_clobbered_p)
9567 emit_note (NOTE_INSN_DELETED);
9573 mips_emit_move (temp, mips_cprestore_slot (temp, true));
9574 mips_emit_move (pic_offset_table_rtx, temp);
9577 mips_emit_move (pic_offset_table_rtx, mips_cprestore_slot (temp, true));
9578 if (!TARGET_EXPLICIT_RELOCS)
9579 emit_insn (gen_blockage ());
9582 /* A function to save or store a register. The first argument is the
9583 register and the second is the stack slot. */
9584 typedef void (*mips_save_restore_fn) (rtx, rtx);
9586 /* Use FN to save or restore register REGNO. MODE is the register's
9587 mode and OFFSET is the offset of its save slot from the current
9591 mips_save_restore_reg (enum machine_mode mode, int regno,
9592 HOST_WIDE_INT offset, mips_save_restore_fn fn)
9596 mem = gen_frame_mem (mode, plus_constant (stack_pointer_rtx, offset));
9597 fn (gen_rtx_REG (mode, regno), mem);
9600 /* Call FN for each accumlator that is saved by the current function.
9601 SP_OFFSET is the offset of the current stack pointer from the start
9605 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
9607 HOST_WIDE_INT offset;
9610 offset = cfun->machine->frame.acc_sp_offset - sp_offset;
9611 if (BITSET_P (cfun->machine->frame.acc_mask, 0))
9613 mips_save_restore_reg (word_mode, LO_REGNUM, offset, fn);
9614 offset -= UNITS_PER_WORD;
9615 mips_save_restore_reg (word_mode, HI_REGNUM, offset, fn);
9616 offset -= UNITS_PER_WORD;
9619 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
9620 if (BITSET_P (cfun->machine->frame.acc_mask,
9621 ((regno - DSP_ACC_REG_FIRST) / 2) + 1))
9623 mips_save_restore_reg (word_mode, regno, offset, fn);
9624 offset -= UNITS_PER_WORD;
9628 /* Call FN for each register that is saved by the current function.
9629 SP_OFFSET is the offset of the current stack pointer from the start
9633 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset,
9634 mips_save_restore_fn fn)
9636 enum machine_mode fpr_mode;
9637 HOST_WIDE_INT offset;
9640 /* Save registers starting from high to low. The debuggers prefer at least
9641 the return register be stored at func+4, and also it allows us not to
9642 need a nop in the epilogue if at least one register is reloaded in
9643 addition to return address. */
9644 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
9645 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
9646 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
9648 /* Record the ra offset for use by mips_function_profiler. */
9649 if (regno == RETURN_ADDR_REGNUM)
9650 cfun->machine->frame.ra_fp_offset = offset + sp_offset;
9651 mips_save_restore_reg (word_mode, regno, offset, fn);
9652 offset -= UNITS_PER_WORD;
9655 /* This loop must iterate over the same space as its companion in
9656 mips_compute_frame_info. */
9657 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
9658 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
9659 for (regno = FP_REG_LAST - MAX_FPRS_PER_FMT + 1;
9660 regno >= FP_REG_FIRST;
9661 regno -= MAX_FPRS_PER_FMT)
9662 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
9664 mips_save_restore_reg (fpr_mode, regno, offset, fn);
9665 offset -= GET_MODE_SIZE (fpr_mode);
9669 /* Return true if a move between register REGNO and its save slot (MEM)
9670 can be done in a single move. LOAD_P is true if we are loading
9671 from the slot, false if we are storing to it. */
9674 mips_direct_save_slot_move_p (unsigned int regno, rtx mem, bool load_p)
9676 /* There is a specific MIPS16 instruction for saving $31 to the stack. */
9677 if (TARGET_MIPS16 && !load_p && regno == RETURN_ADDR_REGNUM)
9680 return mips_secondary_reload_class (REGNO_REG_CLASS (regno),
9681 GET_MODE (mem), mem, load_p) == NO_REGS;
9684 /* Emit a move from SRC to DEST, given that one of them is a register
9685 save slot and that the other is a register. TEMP is a temporary
9686 GPR of the same mode that is available if need be. */
9689 mips_emit_save_slot_move (rtx dest, rtx src, rtx temp)
9696 regno = REGNO (src);
9701 regno = REGNO (dest);
9705 if (regno == cfun->machine->global_pointer && !mips_must_initialize_gp_p ())
9707 /* We don't yet know whether we'll need this instruction or not.
9708 Postpone the decision by emitting a ghost move. This move
9709 is specifically not frame-related; only the split version is. */
9711 emit_insn (gen_move_gpdi (dest, src));
9713 emit_insn (gen_move_gpsi (dest, src));
9717 if (regno == HI_REGNUM)
9721 mips_emit_move (temp, src);
9723 emit_insn (gen_mthisi_di (gen_rtx_REG (TImode, MD_REG_FIRST),
9724 temp, gen_rtx_REG (DImode, LO_REGNUM)));
9726 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode, MD_REG_FIRST),
9727 temp, gen_rtx_REG (SImode, LO_REGNUM)));
9732 emit_insn (gen_mfhidi_ti (temp,
9733 gen_rtx_REG (TImode, MD_REG_FIRST)));
9735 emit_insn (gen_mfhisi_di (temp,
9736 gen_rtx_REG (DImode, MD_REG_FIRST)));
9737 mips_emit_move (dest, temp);
9740 else if (mips_direct_save_slot_move_p (regno, mem, mem == src))
9741 mips_emit_move (dest, src);
9744 gcc_assert (!reg_overlap_mentioned_p (dest, temp));
9745 mips_emit_move (temp, src);
9746 mips_emit_move (dest, temp);
9749 mips_set_frame_expr (mips_frame_set (dest, src));
9752 /* If we're generating n32 or n64 abicalls, and the current function
9753 does not use $28 as its global pointer, emit a cplocal directive.
9754 Use pic_offset_table_rtx as the argument to the directive. */
9757 mips_output_cplocal (void)
9759 if (!TARGET_EXPLICIT_RELOCS
9760 && mips_must_initialize_gp_p ()
9761 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
9762 output_asm_insn (".cplocal %+", 0);
9765 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
9768 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9772 #ifdef SDB_DEBUGGING_INFO
9773 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
9774 SDB_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
9777 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
9778 floating-point arguments. */
9780 && TARGET_HARD_FLOAT_ABI
9781 && crtl->args.info.fp_code != 0)
9782 mips16_build_function_stub ();
9784 /* Get the function name the same way that toplev.c does before calling
9785 assemble_start_function. This is needed so that the name used here
9786 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
9787 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
9788 mips_start_function_definition (fnname, TARGET_MIPS16);
9790 /* Output MIPS-specific frame information. */
9791 if (!flag_inhibit_size_directive)
9793 const struct mips_frame_info *frame;
9795 frame = &cfun->machine->frame;
9797 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
9799 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
9800 "# vars= " HOST_WIDE_INT_PRINT_DEC
9802 ", args= " HOST_WIDE_INT_PRINT_DEC
9803 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
9804 reg_names[frame_pointer_needed
9805 ? HARD_FRAME_POINTER_REGNUM
9806 : STACK_POINTER_REGNUM],
9807 (frame_pointer_needed
9808 ? frame->total_size - frame->hard_frame_pointer_offset
9809 : frame->total_size),
9810 reg_names[RETURN_ADDR_REGNUM],
9812 frame->num_gp, frame->num_fp,
9814 frame->cprestore_size);
9816 /* .mask MASK, OFFSET. */
9817 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
9818 frame->mask, frame->gp_save_offset);
9820 /* .fmask MASK, OFFSET. */
9821 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
9822 frame->fmask, frame->fp_save_offset);
9825 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
9826 Also emit the ".set noreorder; .set nomacro" sequence for functions
9828 if (mips_must_initialize_gp_p ()
9829 && mips_current_loadgp_style () == LOADGP_OLDABI)
9833 /* This is a fixed-form sequence. The position of the
9834 first two instructions is important because of the
9835 way _gp_disp is defined. */
9836 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
9837 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
9838 output_asm_insn ("sll\t$2,16", 0);
9839 output_asm_insn ("addu\t$2,$3", 0);
9843 /* .cpload must be in a .set noreorder but not a
9844 .set nomacro block. */
9845 mips_push_asm_switch (&mips_noreorder);
9846 output_asm_insn (".cpload\t%^", 0);
9847 if (!cfun->machine->all_noreorder_p)
9848 mips_pop_asm_switch (&mips_noreorder);
9850 mips_push_asm_switch (&mips_nomacro);
9853 else if (cfun->machine->all_noreorder_p)
9855 mips_push_asm_switch (&mips_noreorder);
9856 mips_push_asm_switch (&mips_nomacro);
9859 /* Tell the assembler which register we're using as the global
9860 pointer. This is needed for thunks, since they can use either
9861 explicit relocs or assembler macros. */
9862 mips_output_cplocal ();
9865 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
9868 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
9869 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9873 /* Reinstate the normal $gp. */
9874 SET_REGNO (pic_offset_table_rtx, GLOBAL_POINTER_REGNUM);
9875 mips_output_cplocal ();
9877 if (cfun->machine->all_noreorder_p)
9879 mips_pop_asm_switch (&mips_nomacro);
9880 mips_pop_asm_switch (&mips_noreorder);
9883 /* Get the function name the same way that toplev.c does before calling
9884 assemble_start_function. This is needed so that the name used here
9885 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
9886 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
9887 mips_end_function_definition (fnname);
9890 /* Save register REG to MEM. Make the instruction frame-related. */
9893 mips_save_reg (rtx reg, rtx mem)
9895 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
9899 if (mips_split_64bit_move_p (mem, reg))
9900 mips_split_doubleword_move (mem, reg);
9902 mips_emit_move (mem, reg);
9904 x1 = mips_frame_set (mips_subword (mem, false),
9905 mips_subword (reg, false));
9906 x2 = mips_frame_set (mips_subword (mem, true),
9907 mips_subword (reg, true));
9908 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
9911 mips_emit_save_slot_move (mem, reg, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
9914 /* The __gnu_local_gp symbol. */
9916 static GTY(()) rtx mips_gnu_local_gp;
9918 /* If we're generating n32 or n64 abicalls, emit instructions
9919 to set up the global pointer. */
9922 mips_emit_loadgp (void)
9924 rtx addr, offset, incoming_address, base, index, pic_reg;
9926 pic_reg = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
9927 switch (mips_current_loadgp_style ())
9929 case LOADGP_ABSOLUTE:
9930 if (mips_gnu_local_gp == NULL)
9932 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
9933 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
9935 emit_insn (Pmode == SImode
9936 ? gen_loadgp_absolute_si (pic_reg, mips_gnu_local_gp)
9937 : gen_loadgp_absolute_di (pic_reg, mips_gnu_local_gp));
9941 /* Added by mips_output_function_prologue. */
9945 addr = XEXP (DECL_RTL (current_function_decl), 0);
9946 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
9947 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
9948 emit_insn (Pmode == SImode
9949 ? gen_loadgp_newabi_si (pic_reg, offset, incoming_address)
9950 : gen_loadgp_newabi_di (pic_reg, offset, incoming_address));
9954 base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE));
9955 index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX));
9956 emit_insn (Pmode == SImode
9957 ? gen_loadgp_rtp_si (pic_reg, base, index)
9958 : gen_loadgp_rtp_di (pic_reg, base, index));
9966 emit_insn (gen_copygp_mips16 (pic_offset_table_rtx, pic_reg));
9968 /* Emit a blockage if there are implicit uses of the GP register.
9969 This includes profiled functions, because FUNCTION_PROFILE uses
9971 if (!TARGET_EXPLICIT_RELOCS || crtl->profile)
9972 emit_insn (gen_loadgp_blockage ());
9975 /* A for_each_rtx callback. Stop the search if *X is a kernel register. */
9978 mips_kernel_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
9980 return REG_P (*x) && KERNEL_REG_P (REGNO (*x));
9983 /* Expand the "prologue" pattern. */
9986 mips_expand_prologue (void)
9988 const struct mips_frame_info *frame;
9993 if (cfun->machine->global_pointer != INVALID_REGNUM)
9995 /* Check whether an insn uses pic_offset_table_rtx, either explicitly
9996 or implicitly. If so, we can commit to using a global pointer
9997 straight away, otherwise we need to defer the decision. */
9998 if (mips_cfun_has_inflexible_gp_ref_p ()
9999 || mips_cfun_has_flexible_gp_ref_p ())
10001 cfun->machine->must_initialize_gp_p = true;
10002 cfun->machine->must_restore_gp_when_clobbered_p = true;
10005 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
10008 frame = &cfun->machine->frame;
10009 size = frame->total_size;
10011 if (flag_stack_usage_info)
10012 current_function_static_stack_size = size;
10014 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
10015 bytes beforehand; this is enough to cover the register save area
10016 without going out of range. */
10017 if (((frame->mask | frame->fmask | frame->acc_mask) != 0)
10018 || frame->num_cop0_regs > 0)
10020 HOST_WIDE_INT step1;
10022 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
10023 if (GENERATE_MIPS16E_SAVE_RESTORE)
10025 HOST_WIDE_INT offset;
10026 unsigned int mask, regno;
10028 /* Try to merge argument stores into the save instruction. */
10029 nargs = mips16e_collect_argument_saves ();
10031 /* Build the save instruction. */
10032 mask = frame->mask;
10033 insn = mips16e_build_save_restore (false, &mask, &offset,
10035 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10038 /* Check if we need to save other registers. */
10039 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
10040 if (BITSET_P (mask, regno - GP_REG_FIRST))
10042 offset -= UNITS_PER_WORD;
10043 mips_save_restore_reg (word_mode, regno,
10044 offset, mips_save_reg);
10049 if (cfun->machine->interrupt_handler_p)
10051 HOST_WIDE_INT offset;
10054 /* If this interrupt is using a shadow register set, we need to
10055 get the stack pointer from the previous register set. */
10056 if (cfun->machine->use_shadow_register_set_p)
10057 emit_insn (gen_mips_rdpgpr (stack_pointer_rtx,
10058 stack_pointer_rtx));
10060 if (!cfun->machine->keep_interrupts_masked_p)
10062 /* Move from COP0 Cause to K0. */
10063 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K0_REG_NUM),
10064 gen_rtx_REG (SImode,
10065 COP0_CAUSE_REG_NUM)));
10066 /* Move from COP0 EPC to K1. */
10067 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
10068 gen_rtx_REG (SImode,
10069 COP0_EPC_REG_NUM)));
10072 /* Allocate the first part of the frame. */
10073 insn = gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx,
10075 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10078 /* Start at the uppermost location for saving. */
10079 offset = frame->cop0_sp_offset - size;
10080 if (!cfun->machine->keep_interrupts_masked_p)
10082 /* Push EPC into its stack slot. */
10083 mem = gen_frame_mem (word_mode,
10084 plus_constant (stack_pointer_rtx,
10086 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
10087 offset -= UNITS_PER_WORD;
10090 /* Move from COP0 Status to K1. */
10091 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
10092 gen_rtx_REG (SImode,
10093 COP0_STATUS_REG_NUM)));
10095 /* Right justify the RIPL in k0. */
10096 if (!cfun->machine->keep_interrupts_masked_p)
10097 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode, K0_REG_NUM),
10098 gen_rtx_REG (SImode, K0_REG_NUM),
10099 GEN_INT (CAUSE_IPL)));
10101 /* Push Status into its stack slot. */
10102 mem = gen_frame_mem (word_mode,
10103 plus_constant (stack_pointer_rtx, offset));
10104 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
10105 offset -= UNITS_PER_WORD;
10107 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
10108 if (!cfun->machine->keep_interrupts_masked_p)
10109 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
10112 gen_rtx_REG (SImode, K0_REG_NUM)));
10114 if (!cfun->machine->keep_interrupts_masked_p)
10115 /* Enable interrupts by clearing the KSU ERL and EXL bits.
10116 IE is already the correct value, so we don't have to do
10117 anything explicit. */
10118 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
10121 gen_rtx_REG (SImode, GP_REG_FIRST)));
10123 /* Disable interrupts by clearing the KSU, ERL, EXL,
10125 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
10128 gen_rtx_REG (SImode, GP_REG_FIRST)));
10132 insn = gen_add3_insn (stack_pointer_rtx,
10135 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10138 mips_for_each_saved_acc (size, mips_save_reg);
10139 mips_for_each_saved_gpr_and_fpr (size, mips_save_reg);
10143 /* Allocate the rest of the frame. */
10146 if (SMALL_OPERAND (-size))
10147 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
10149 GEN_INT (-size)))) = 1;
10152 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
10155 /* There are no instructions to add or subtract registers
10156 from the stack pointer, so use the frame pointer as a
10157 temporary. We should always be using a frame pointer
10158 in this case anyway. */
10159 gcc_assert (frame_pointer_needed);
10160 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
10161 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
10162 hard_frame_pointer_rtx,
10163 MIPS_PROLOGUE_TEMP (Pmode)));
10164 mips_emit_move (stack_pointer_rtx, hard_frame_pointer_rtx);
10167 emit_insn (gen_sub3_insn (stack_pointer_rtx,
10169 MIPS_PROLOGUE_TEMP (Pmode)));
10171 /* Describe the combined effect of the previous instructions. */
10172 mips_set_frame_expr
10173 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
10174 plus_constant (stack_pointer_rtx, -size)));
10178 /* Set up the frame pointer, if we're using one. */
10179 if (frame_pointer_needed)
10181 HOST_WIDE_INT offset;
10183 offset = frame->hard_frame_pointer_offset;
10186 insn = mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
10187 RTX_FRAME_RELATED_P (insn) = 1;
10189 else if (SMALL_OPERAND (offset))
10191 insn = gen_add3_insn (hard_frame_pointer_rtx,
10192 stack_pointer_rtx, GEN_INT (offset));
10193 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10197 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (offset));
10198 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
10199 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
10200 hard_frame_pointer_rtx,
10201 MIPS_PROLOGUE_TEMP (Pmode)));
10202 mips_set_frame_expr
10203 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
10204 plus_constant (stack_pointer_rtx, offset)));
10208 mips_emit_loadgp ();
10210 /* Initialize the $gp save slot. */
10211 if (mips_cfun_has_cprestore_slot_p ())
10213 rtx base, mem, gp, temp;
10214 HOST_WIDE_INT offset;
10216 mips_get_cprestore_base_and_offset (&base, &offset, false);
10217 mem = gen_frame_mem (Pmode, plus_constant (base, offset));
10218 gp = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
10219 temp = (SMALL_OPERAND (offset)
10220 ? gen_rtx_SCRATCH (Pmode)
10221 : MIPS_PROLOGUE_TEMP (Pmode));
10222 emit_insn (gen_potential_cprestore (mem, GEN_INT (offset), gp, temp));
10224 mips_get_cprestore_base_and_offset (&base, &offset, true);
10225 mem = gen_frame_mem (Pmode, plus_constant (base, offset));
10226 emit_insn (gen_use_cprestore (mem));
10229 /* We need to search back to the last use of K0 or K1. */
10230 if (cfun->machine->interrupt_handler_p)
10232 for (insn = get_last_insn (); insn != NULL_RTX; insn = PREV_INSN (insn))
10234 && for_each_rtx (&PATTERN (insn), mips_kernel_reg_p, NULL))
10236 /* Emit a move from K1 to COP0 Status after insn. */
10237 gcc_assert (insn != NULL_RTX);
10238 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
10239 gen_rtx_REG (SImode, K1_REG_NUM)),
10243 /* If we are profiling, make sure no instructions are scheduled before
10244 the call to mcount. */
10246 emit_insn (gen_blockage ());
10249 /* Emit instructions to restore register REG from slot MEM. */
10252 mips_restore_reg (rtx reg, rtx mem)
10254 /* There's no MIPS16 instruction to load $31 directly. Load into
10255 $7 instead and adjust the return insn appropriately. */
10256 if (TARGET_MIPS16 && REGNO (reg) == RETURN_ADDR_REGNUM)
10257 reg = gen_rtx_REG (GET_MODE (reg), GP_REG_FIRST + 7);
10259 mips_emit_save_slot_move (reg, mem, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
10262 /* Emit any instructions needed before a return. */
10265 mips_expand_before_return (void)
10267 /* When using a call-clobbered gp, we start out with unified call
10268 insns that include instructions to restore the gp. We then split
10269 these unified calls after reload. These split calls explicitly
10270 clobber gp, so there is no need to define
10271 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
10273 For consistency, we should also insert an explicit clobber of $28
10274 before return insns, so that the post-reload optimizers know that
10275 the register is not live on exit. */
10276 if (TARGET_CALL_CLOBBERED_GP)
10277 emit_clobber (pic_offset_table_rtx);
10280 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
10284 mips_expand_epilogue (bool sibcall_p)
10286 const struct mips_frame_info *frame;
10287 HOST_WIDE_INT step1, step2;
10288 rtx base, target, insn;
10290 if (!sibcall_p && mips_can_use_return_insn ())
10292 emit_jump_insn (gen_return ());
10296 /* In MIPS16 mode, if the return value should go into a floating-point
10297 register, we need to call a helper routine to copy it over. */
10298 if (mips16_cfun_returns_in_fpr_p ())
10299 mips16_copy_fpr_return_value ();
10301 /* Split the frame into two. STEP1 is the amount of stack we should
10302 deallocate before restoring the registers. STEP2 is the amount we
10303 should deallocate afterwards.
10305 Start off by assuming that no registers need to be restored. */
10306 frame = &cfun->machine->frame;
10307 step1 = frame->total_size;
10310 /* Work out which register holds the frame address. */
10311 if (!frame_pointer_needed)
10312 base = stack_pointer_rtx;
10315 base = hard_frame_pointer_rtx;
10316 step1 -= frame->hard_frame_pointer_offset;
10319 /* If we need to restore registers, deallocate as much stack as
10320 possible in the second step without going out of range. */
10321 if ((frame->mask | frame->fmask | frame->acc_mask) != 0
10322 || frame->num_cop0_regs > 0)
10324 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
10328 /* Set TARGET to BASE + STEP1. */
10334 /* Get an rtx for STEP1 that we can add to BASE. */
10335 adjust = GEN_INT (step1);
10336 if (!SMALL_OPERAND (step1))
10338 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), adjust);
10339 adjust = MIPS_EPILOGUE_TEMP (Pmode);
10342 /* Normal mode code can copy the result straight into $sp. */
10343 if (!TARGET_MIPS16)
10344 target = stack_pointer_rtx;
10346 emit_insn (gen_add3_insn (target, base, adjust));
10349 /* Copy TARGET into the stack pointer. */
10350 if (target != stack_pointer_rtx)
10351 mips_emit_move (stack_pointer_rtx, target);
10353 /* If we're using addressing macros, $gp is implicitly used by all
10354 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
10356 if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS)
10357 emit_insn (gen_blockage ());
10359 if (GENERATE_MIPS16E_SAVE_RESTORE && frame->mask != 0)
10361 unsigned int regno, mask;
10362 HOST_WIDE_INT offset;
10365 /* Generate the restore instruction. */
10366 mask = frame->mask;
10367 restore = mips16e_build_save_restore (true, &mask, &offset, 0, step2);
10369 /* Restore any other registers manually. */
10370 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
10371 if (BITSET_P (mask, regno - GP_REG_FIRST))
10373 offset -= UNITS_PER_WORD;
10374 mips_save_restore_reg (word_mode, regno, offset, mips_restore_reg);
10377 /* Restore the remaining registers and deallocate the final bit
10379 emit_insn (restore);
10383 /* Restore the registers. */
10384 mips_for_each_saved_acc (frame->total_size - step2, mips_restore_reg);
10385 mips_for_each_saved_gpr_and_fpr (frame->total_size - step2,
10388 if (cfun->machine->interrupt_handler_p)
10390 HOST_WIDE_INT offset;
10393 offset = frame->cop0_sp_offset - (frame->total_size - step2);
10394 if (!cfun->machine->keep_interrupts_masked_p)
10396 /* Restore the original EPC. */
10397 mem = gen_frame_mem (word_mode,
10398 plus_constant (stack_pointer_rtx, offset));
10399 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
10400 offset -= UNITS_PER_WORD;
10402 /* Move to COP0 EPC. */
10403 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_EPC_REG_NUM),
10404 gen_rtx_REG (SImode, K0_REG_NUM)));
10407 /* Restore the original Status. */
10408 mem = gen_frame_mem (word_mode,
10409 plus_constant (stack_pointer_rtx, offset));
10410 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
10411 offset -= UNITS_PER_WORD;
10413 /* If we don't use shoadow register set, we need to update SP. */
10414 if (!cfun->machine->use_shadow_register_set_p && step2 > 0)
10415 emit_insn (gen_add3_insn (stack_pointer_rtx,
10419 /* Move to COP0 Status. */
10420 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
10421 gen_rtx_REG (SImode, K0_REG_NUM)));
10425 /* Deallocate the final bit of the frame. */
10427 emit_insn (gen_add3_insn (stack_pointer_rtx,
10433 /* Add in the __builtin_eh_return stack adjustment. We need to
10434 use a temporary in MIPS16 code. */
10435 if (crtl->calls_eh_return)
10439 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
10440 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
10441 MIPS_EPILOGUE_TEMP (Pmode),
10442 EH_RETURN_STACKADJ_RTX));
10443 mips_emit_move (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
10446 emit_insn (gen_add3_insn (stack_pointer_rtx,
10448 EH_RETURN_STACKADJ_RTX));
10453 mips_expand_before_return ();
10454 if (cfun->machine->interrupt_handler_p)
10456 /* Interrupt handlers generate eret or deret. */
10457 if (cfun->machine->use_debug_exception_return_p)
10458 emit_jump_insn (gen_mips_deret ());
10460 emit_jump_insn (gen_mips_eret ());
10464 unsigned int regno;
10466 /* When generating MIPS16 code, the normal
10467 mips_for_each_saved_gpr_and_fpr path will restore the return
10468 address into $7 rather than $31. */
10470 && !GENERATE_MIPS16E_SAVE_RESTORE
10471 && BITSET_P (frame->mask, RETURN_ADDR_REGNUM))
10472 regno = GP_REG_FIRST + 7;
10474 regno = RETURN_ADDR_REGNUM;
10475 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, regno)));
10479 /* Search from the beginning to the first use of K0 or K1. */
10480 if (cfun->machine->interrupt_handler_p
10481 && !cfun->machine->keep_interrupts_masked_p)
10483 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
10485 && for_each_rtx (&PATTERN(insn), mips_kernel_reg_p, NULL))
10487 gcc_assert (insn != NULL_RTX);
10488 /* Insert disable interrupts before the first use of K0 or K1. */
10489 emit_insn_before (gen_mips_di (), insn);
10490 emit_insn_before (gen_mips_ehb (), insn);
10494 /* Return nonzero if this function is known to have a null epilogue.
10495 This allows the optimizer to omit jumps to jumps if no stack
10499 mips_can_use_return_insn (void)
10501 /* Interrupt handlers need to go through the epilogue. */
10502 if (cfun->machine->interrupt_handler_p)
10505 if (!reload_completed)
10511 /* In MIPS16 mode, a function that returns a floating-point value
10512 needs to arrange to copy the return value into the floating-point
10514 if (mips16_cfun_returns_in_fpr_p ())
10517 return cfun->machine->frame.total_size == 0;
10520 /* Return true if register REGNO can store a value of mode MODE.
10521 The result of this function is cached in mips_hard_regno_mode_ok. */
10524 mips_hard_regno_mode_ok_p (unsigned int regno, enum machine_mode mode)
10527 enum mode_class mclass;
10529 if (mode == CCV2mode)
10530 return (ISA_HAS_8CC
10531 && ST_REG_P (regno)
10532 && (regno - ST_REG_FIRST) % 2 == 0);
10534 if (mode == CCV4mode)
10535 return (ISA_HAS_8CC
10536 && ST_REG_P (regno)
10537 && (regno - ST_REG_FIRST) % 4 == 0);
10539 if (mode == CCmode)
10542 return regno == FPSW_REGNUM;
10544 return (ST_REG_P (regno)
10545 || GP_REG_P (regno)
10546 || FP_REG_P (regno));
10549 size = GET_MODE_SIZE (mode);
10550 mclass = GET_MODE_CLASS (mode);
10552 if (GP_REG_P (regno))
10553 return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD;
10555 if (FP_REG_P (regno)
10556 && (((regno - FP_REG_FIRST) % MAX_FPRS_PER_FMT) == 0
10557 || (MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG)))
10559 /* Allow TFmode for CCmode reloads. */
10560 if (mode == TFmode && ISA_HAS_8CC)
10563 /* Allow 64-bit vector modes for Loongson-2E/2F. */
10564 if (TARGET_LOONGSON_VECTORS
10565 && (mode == V2SImode
10566 || mode == V4HImode
10567 || mode == V8QImode
10568 || mode == DImode))
10571 if (mclass == MODE_FLOAT
10572 || mclass == MODE_COMPLEX_FLOAT
10573 || mclass == MODE_VECTOR_FLOAT)
10574 return size <= UNITS_PER_FPVALUE;
10576 /* Allow integer modes that fit into a single register. We need
10577 to put integers into FPRs when using instructions like CVT
10578 and TRUNC. There's no point allowing sizes smaller than a word,
10579 because the FPU has no appropriate load/store instructions. */
10580 if (mclass == MODE_INT)
10581 return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG;
10584 if (ACC_REG_P (regno)
10585 && (INTEGRAL_MODE_P (mode) || ALL_FIXED_POINT_MODE_P (mode)))
10587 if (MD_REG_P (regno))
10589 /* After a multiplication or division, clobbering HI makes
10590 the value of LO unpredictable, and vice versa. This means
10591 that, for all interesting cases, HI and LO are effectively
10594 We model this by requiring that any value that uses HI
10596 if (size <= UNITS_PER_WORD * 2)
10597 return regno == (size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST);
10601 /* DSP accumulators do not have the same restrictions as
10602 HI and LO, so we can treat them as normal doubleword
10604 if (size <= UNITS_PER_WORD)
10607 if (size <= UNITS_PER_WORD * 2
10608 && ((regno - DSP_ACC_REG_FIRST) & 1) == 0)
10613 if (ALL_COP_REG_P (regno))
10614 return mclass == MODE_INT && size <= UNITS_PER_WORD;
10616 if (regno == GOT_VERSION_REGNUM)
10617 return mode == SImode;
10622 /* Implement HARD_REGNO_NREGS. */
10625 mips_hard_regno_nregs (int regno, enum machine_mode mode)
10627 if (ST_REG_P (regno))
10628 /* The size of FP status registers is always 4, because they only hold
10629 CCmode values, and CCmode is always considered to be 4 bytes wide. */
10630 return (GET_MODE_SIZE (mode) + 3) / 4;
10632 if (FP_REG_P (regno))
10633 return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG;
10635 /* All other registers are word-sized. */
10636 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
10639 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
10640 in mips_hard_regno_nregs. */
10643 mips_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
10649 COPY_HARD_REG_SET (left, reg_class_contents[(int) rclass]);
10650 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS]))
10652 size = MIN (size, 4);
10653 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) ST_REGS]);
10655 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS]))
10657 size = MIN (size, UNITS_PER_FPREG);
10658 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]);
10660 if (!hard_reg_set_empty_p (left))
10661 size = MIN (size, UNITS_PER_WORD);
10662 return (GET_MODE_SIZE (mode) + size - 1) / size;
10665 /* Implement CANNOT_CHANGE_MODE_CLASS. */
10668 mips_cannot_change_mode_class (enum machine_mode from ATTRIBUTE_UNUSED,
10669 enum machine_mode to ATTRIBUTE_UNUSED,
10670 enum reg_class rclass)
10672 /* There are several problems with changing the modes of values in
10673 floating-point registers:
10675 - When a multi-word value is stored in paired floating-point
10676 registers, the first register always holds the low word. We
10677 therefore can't allow FPRs to change between single-word and
10678 multi-word modes on big-endian targets.
10680 - GCC assumes that each word of a multiword register can be
10681 accessed individually using SUBREGs. This is not true for
10682 floating-point registers if they are bigger than a word.
10684 - Loading a 32-bit value into a 64-bit floating-point register
10685 will not sign-extend the value, despite what LOAD_EXTEND_OP
10686 says. We can't allow FPRs to change from SImode to a wider
10687 mode on 64-bit targets.
10689 - If the FPU has already interpreted a value in one format, we
10690 must not ask it to treat the value as having a different
10693 We therefore disallow all mode changes involving FPRs. */
10694 return reg_classes_intersect_p (FP_REGS, rclass);
10697 /* Implement target hook small_register_classes_for_mode_p. */
10700 mips_small_register_classes_for_mode_p (enum machine_mode mode
10703 return TARGET_MIPS16;
10706 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
10709 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode)
10714 return TARGET_HARD_FLOAT;
10717 return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT;
10720 return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT;
10727 /* Implement MODES_TIEABLE_P. */
10730 mips_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
10732 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
10733 prefer to put one of them in FPRs. */
10734 return (mode1 == mode2
10735 || (!mips_mode_ok_for_mov_fmt_p (mode1)
10736 && !mips_mode_ok_for_mov_fmt_p (mode2)));
10739 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
10742 mips_preferred_reload_class (rtx x, reg_class_t rclass)
10744 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, rclass))
10747 if (reg_class_subset_p (FP_REGS, rclass)
10748 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x)))
10751 if (reg_class_subset_p (GR_REGS, rclass))
10754 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, rclass))
10760 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
10761 Return a "canonical" class to represent it in later calculations. */
10764 mips_canonicalize_move_class (reg_class_t rclass)
10766 /* All moves involving accumulator registers have the same cost. */
10767 if (reg_class_subset_p (rclass, ACC_REGS))
10770 /* Likewise promote subclasses of general registers to the most
10771 interesting containing class. */
10772 if (TARGET_MIPS16 && reg_class_subset_p (rclass, M16_REGS))
10774 else if (reg_class_subset_p (rclass, GENERAL_REGS))
10775 rclass = GENERAL_REGS;
10780 /* Return the cost of moving a value of mode MODE from a register of
10781 class FROM to a GPR. Return 0 for classes that are unions of other
10782 classes handled by this function. */
10785 mips_move_to_gpr_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
10791 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
10795 /* MFLO and MFHI. */
10803 /* LUI followed by MOVF. */
10809 /* This choice of value is historical. */
10817 /* Return the cost of moving a value of mode MODE from a GPR to a
10818 register of class TO. Return 0 for classes that are unions of
10819 other classes handled by this function. */
10822 mips_move_from_gpr_cost (enum machine_mode mode, reg_class_t to)
10827 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
10831 /* MTLO and MTHI. */
10839 /* A secondary reload through an FPR scratch. */
10840 return (mips_register_move_cost (mode, GENERAL_REGS, FP_REGS)
10841 + mips_register_move_cost (mode, FP_REGS, ST_REGS));
10846 /* This choice of value is historical. */
10854 /* Implement TARGET_REGISTER_MOVE_COST. Return 0 for classes that are the
10855 maximum of the move costs for subclasses; regclass will work out
10856 the maximum for us. */
10859 mips_register_move_cost (enum machine_mode mode,
10860 reg_class_t from, reg_class_t to)
10865 from = mips_canonicalize_move_class (from);
10866 to = mips_canonicalize_move_class (to);
10868 /* Handle moves that can be done without using general-purpose registers. */
10869 if (from == FP_REGS)
10871 if (to == FP_REGS && mips_mode_ok_for_mov_fmt_p (mode))
10875 /* The sequence generated by mips_expand_fcc_reload. */
10879 /* Handle cases in which only one class deviates from the ideal. */
10880 dregs = TARGET_MIPS16 ? M16_REGS : GENERAL_REGS;
10882 return mips_move_from_gpr_cost (mode, to);
10884 return mips_move_to_gpr_cost (mode, from);
10886 /* Handles cases that require a GPR temporary. */
10887 cost1 = mips_move_to_gpr_cost (mode, from);
10890 cost2 = mips_move_from_gpr_cost (mode, to);
10892 return cost1 + cost2;
10898 /* Implement TARGET_MEMORY_MOVE_COST. */
10901 mips_memory_move_cost (enum machine_mode mode, reg_class_t rclass, bool in)
10903 return (mips_cost->memory_latency
10904 + memory_move_secondary_cost (mode, rclass, in));
10907 /* Return the register class required for a secondary register when
10908 copying between one of the registers in RCLASS and value X, which
10909 has mode MODE. X is the source of the move if IN_P, otherwise it
10910 is the destination. Return NO_REGS if no secondary register is
10914 mips_secondary_reload_class (enum reg_class rclass,
10915 enum machine_mode mode, rtx x, bool in_p)
10919 /* If X is a constant that cannot be loaded into $25, it must be loaded
10920 into some other GPR. No other register class allows a direct move. */
10921 if (mips_dangerous_for_la25_p (x))
10922 return reg_class_subset_p (rclass, LEA_REGS) ? NO_REGS : LEA_REGS;
10924 regno = true_regnum (x);
10927 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
10928 if (!reg_class_subset_p (rclass, M16_REGS) && !M16_REG_P (regno))
10934 /* Copying from accumulator registers to anywhere other than a general
10935 register requires a temporary general register. */
10936 if (reg_class_subset_p (rclass, ACC_REGS))
10937 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
10938 if (ACC_REG_P (regno))
10939 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
10941 /* We can only copy a value to a condition code register from a
10942 floating-point register, and even then we require a scratch
10943 floating-point register. We can only copy a value out of a
10944 condition-code register into a general register. */
10945 if (reg_class_subset_p (rclass, ST_REGS))
10949 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
10951 if (ST_REG_P (regno))
10955 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
10958 if (reg_class_subset_p (rclass, FP_REGS))
10961 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8))
10962 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
10963 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
10966 if (GP_REG_P (regno) || x == CONST0_RTX (mode))
10967 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
10970 if (CONSTANT_P (x) && !targetm.cannot_force_const_mem (mode, x))
10971 /* We can force the constant to memory and use lwc1
10972 and ldc1. As above, we will use pairs of lwc1s if
10973 ldc1 is not supported. */
10976 if (FP_REG_P (regno) && mips_mode_ok_for_mov_fmt_p (mode))
10977 /* In this case we can use mov.fmt. */
10980 /* Otherwise, we need to reload through an integer register. */
10983 if (FP_REG_P (regno))
10984 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
10989 /* Implement TARGET_MODE_REP_EXTENDED. */
10992 mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
10994 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
10995 if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
10996 return SIGN_EXTEND;
11001 /* Implement TARGET_VALID_POINTER_MODE. */
11004 mips_valid_pointer_mode (enum machine_mode mode)
11006 return mode == SImode || (TARGET_64BIT && mode == DImode);
11009 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
11012 mips_vector_mode_supported_p (enum machine_mode mode)
11017 return TARGET_PAIRED_SINGLE_FLOAT;
11032 return TARGET_LOONGSON_VECTORS;
11039 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
11042 mips_scalar_mode_supported_p (enum machine_mode mode)
11044 if (ALL_FIXED_POINT_MODE_P (mode)
11045 && GET_MODE_PRECISION (mode) <= 2 * BITS_PER_WORD)
11048 return default_scalar_mode_supported_p (mode);
11051 /* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
11053 static enum machine_mode
11054 mips_preferred_simd_mode (enum machine_mode mode ATTRIBUTE_UNUSED)
11056 if (TARGET_PAIRED_SINGLE_FLOAT
11062 /* Implement TARGET_INIT_LIBFUNCS. */
11065 mips_init_libfuncs (void)
11067 if (TARGET_FIX_VR4120)
11069 /* Register the special divsi3 and modsi3 functions needed to work
11070 around VR4120 division errata. */
11071 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
11072 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
11075 if (TARGET_MIPS16 && TARGET_HARD_FLOAT_ABI)
11077 /* Register the MIPS16 -mhard-float stubs. */
11078 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
11079 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
11080 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
11081 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
11083 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
11084 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
11085 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
11086 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
11087 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
11088 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
11089 set_optab_libfunc (unord_optab, SFmode, "__mips16_unordsf2");
11091 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
11092 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
11093 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__mips16_floatunsisf");
11095 if (TARGET_DOUBLE_FLOAT)
11097 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
11098 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
11099 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
11100 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
11102 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
11103 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
11104 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
11105 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
11106 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
11107 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
11108 set_optab_libfunc (unord_optab, DFmode, "__mips16_unorddf2");
11110 set_conv_libfunc (sext_optab, DFmode, SFmode,
11111 "__mips16_extendsfdf2");
11112 set_conv_libfunc (trunc_optab, SFmode, DFmode,
11113 "__mips16_truncdfsf2");
11114 set_conv_libfunc (sfix_optab, SImode, DFmode,
11115 "__mips16_fix_truncdfsi");
11116 set_conv_libfunc (sfloat_optab, DFmode, SImode,
11117 "__mips16_floatsidf");
11118 set_conv_libfunc (ufloat_optab, DFmode, SImode,
11119 "__mips16_floatunsidf");
11123 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
11124 on an external non-MIPS16 routine to implement __sync_synchronize. */
11126 synchronize_libfunc = init_one_libfunc ("__sync_synchronize");
11129 /* Build up a multi-insn sequence that loads label TARGET into $AT. */
11132 mips_process_load_label (rtx target)
11134 rtx base, gp, intop;
11135 HOST_WIDE_INT offset;
11137 mips_multi_start ();
11141 mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target, 0);
11142 mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target, 0);
11146 mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target, 0);
11147 mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target, 0);
11151 gp = pic_offset_table_rtx;
11152 if (mips_cfun_has_cprestore_slot_p ())
11154 gp = gen_rtx_REG (Pmode, AT_REGNUM);
11155 mips_get_cprestore_base_and_offset (&base, &offset, true);
11156 if (!SMALL_OPERAND (offset))
11158 intop = GEN_INT (CONST_HIGH_PART (offset));
11159 mips_multi_add_insn ("lui\t%0,%1", gp, intop, 0);
11160 mips_multi_add_insn ("addu\t%0,%0,%1", gp, base, 0);
11163 offset = CONST_LOW_PART (offset);
11165 intop = GEN_INT (offset);
11166 if (ISA_HAS_LOAD_DELAY)
11167 mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp, intop, base, 0);
11169 mips_multi_add_insn ("lw\t%0,%1(%2)", gp, intop, base, 0);
11171 if (ISA_HAS_LOAD_DELAY)
11172 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target, gp, 0);
11174 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target, gp, 0);
11175 mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target, 0);
11180 /* Return the number of instructions needed to load a label into $AT. */
11182 static unsigned int
11183 mips_load_label_num_insns (void)
11185 if (cfun->machine->load_label_num_insns == 0)
11187 mips_process_load_label (pc_rtx);
11188 cfun->machine->load_label_num_insns = mips_multi_num_insns;
11190 return cfun->machine->load_label_num_insns;
11193 /* Emit an asm sequence to start a noat block and load the address
11194 of a label into $1. */
11197 mips_output_load_label (rtx target)
11199 mips_push_asm_switch (&mips_noat);
11200 if (TARGET_EXPLICIT_RELOCS)
11202 mips_process_load_label (target);
11203 mips_multi_write ();
11207 if (Pmode == DImode)
11208 output_asm_insn ("dla\t%@,%0", &target);
11210 output_asm_insn ("la\t%@,%0", &target);
11214 /* Return the length of INSN. LENGTH is the initial length computed by
11215 attributes in the machine-description file. */
11218 mips_adjust_insn_length (rtx insn, int length)
11220 /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length
11221 of a PIC long-branch sequence. Substitute the correct value. */
11222 if (length == MAX_PIC_BRANCH_LENGTH
11223 && INSN_CODE (insn) >= 0
11224 && get_attr_type (insn) == TYPE_BRANCH)
11226 /* Add the branch-over instruction and its delay slot, if this
11227 is a conditional branch. */
11228 length = simplejump_p (insn) ? 0 : 8;
11230 /* Load the label into $AT and jump to it. Ignore the delay
11231 slot of the jump. */
11232 length += 4 * mips_load_label_num_insns() + 4;
11235 /* A unconditional jump has an unfilled delay slot if it is not part
11236 of a sequence. A conditional jump normally has a delay slot, but
11237 does not on MIPS16. */
11238 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
11241 /* See how many nops might be needed to avoid hardware hazards. */
11242 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
11243 switch (get_attr_hazard (insn))
11257 /* In order to make it easier to share MIPS16 and non-MIPS16 patterns,
11258 the .md file length attributes are 4-based for both modes.
11259 Adjust the MIPS16 ones here. */
11266 /* Return the assembly code for INSN, which has the operands given by
11267 OPERANDS, and which branches to OPERANDS[0] if some condition is true.
11268 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0]
11269 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
11270 version of BRANCH_IF_TRUE. */
11273 mips_output_conditional_branch (rtx insn, rtx *operands,
11274 const char *branch_if_true,
11275 const char *branch_if_false)
11277 unsigned int length;
11278 rtx taken, not_taken;
11280 gcc_assert (LABEL_P (operands[0]));
11282 length = get_attr_length (insn);
11285 /* Just a simple conditional branch. */
11286 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
11287 return branch_if_true;
11290 /* Generate a reversed branch around a direct jump. This fallback does
11291 not use branch-likely instructions. */
11292 mips_branch_likely = false;
11293 not_taken = gen_label_rtx ();
11294 taken = operands[0];
11296 /* Generate the reversed branch to NOT_TAKEN. */
11297 operands[0] = not_taken;
11298 output_asm_insn (branch_if_false, operands);
11300 /* If INSN has a delay slot, we must provide delay slots for both the
11301 branch to NOT_TAKEN and the conditional jump. We must also ensure
11302 that INSN's delay slot is executed in the appropriate cases. */
11303 if (final_sequence)
11305 /* This first delay slot will always be executed, so use INSN's
11306 delay slot if is not annulled. */
11307 if (!INSN_ANNULLED_BRANCH_P (insn))
11309 final_scan_insn (XVECEXP (final_sequence, 0, 1),
11310 asm_out_file, optimize, 1, NULL);
11311 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
11314 output_asm_insn ("nop", 0);
11315 fprintf (asm_out_file, "\n");
11318 /* Output the unconditional branch to TAKEN. */
11319 if (TARGET_ABSOLUTE_JUMPS)
11320 output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken);
11323 mips_output_load_label (taken);
11324 output_asm_insn ("jr\t%@%]%/", 0);
11327 /* Now deal with its delay slot; see above. */
11328 if (final_sequence)
11330 /* This delay slot will only be executed if the branch is taken.
11331 Use INSN's delay slot if is annulled. */
11332 if (INSN_ANNULLED_BRANCH_P (insn))
11334 final_scan_insn (XVECEXP (final_sequence, 0, 1),
11335 asm_out_file, optimize, 1, NULL);
11336 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
11339 output_asm_insn ("nop", 0);
11340 fprintf (asm_out_file, "\n");
11343 /* Output NOT_TAKEN. */
11344 targetm.asm_out.internal_label (asm_out_file, "L",
11345 CODE_LABEL_NUMBER (not_taken));
11349 /* Return the assembly code for INSN, which branches to OPERANDS[0]
11350 if some ordering condition is true. The condition is given by
11351 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
11352 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
11353 its second is always zero. */
11356 mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
11358 const char *branch[2];
11360 /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true.
11361 Make BRANCH[0] branch on the inverse condition. */
11362 switch (GET_CODE (operands[1]))
11364 /* These cases are equivalent to comparisons against zero. */
11366 inverted_p = !inverted_p;
11367 /* Fall through. */
11369 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%0");
11370 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%0");
11373 /* These cases are always true or always false. */
11375 inverted_p = !inverted_p;
11376 /* Fall through. */
11378 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%0");
11379 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%0");
11383 branch[!inverted_p] = MIPS_BRANCH ("b%C1z", "%2,%0");
11384 branch[inverted_p] = MIPS_BRANCH ("b%N1z", "%2,%0");
11387 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
11390 /* Start a block of code that needs access to the LL, SC and SYNC
11394 mips_start_ll_sc_sync_block (void)
11396 if (!ISA_HAS_LL_SC)
11398 output_asm_insn (".set\tpush", 0);
11399 output_asm_insn (".set\tmips2", 0);
11403 /* End a block started by mips_start_ll_sc_sync_block. */
11406 mips_end_ll_sc_sync_block (void)
11408 if (!ISA_HAS_LL_SC)
11409 output_asm_insn (".set\tpop", 0);
11412 /* Output and/or return the asm template for a sync instruction. */
11415 mips_output_sync (void)
11417 mips_start_ll_sc_sync_block ();
11418 output_asm_insn ("sync", 0);
11419 mips_end_ll_sc_sync_block ();
11423 /* Return the asm template associated with sync_insn1 value TYPE.
11424 IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */
11426 static const char *
11427 mips_sync_insn1_template (enum attr_sync_insn1 type, bool is_64bit_p)
11431 case SYNC_INSN1_MOVE:
11432 return "move\t%0,%z2";
11433 case SYNC_INSN1_LI:
11434 return "li\t%0,%2";
11435 case SYNC_INSN1_ADDU:
11436 return is_64bit_p ? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2";
11437 case SYNC_INSN1_ADDIU:
11438 return is_64bit_p ? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2";
11439 case SYNC_INSN1_SUBU:
11440 return is_64bit_p ? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2";
11441 case SYNC_INSN1_AND:
11442 return "and\t%0,%1,%z2";
11443 case SYNC_INSN1_ANDI:
11444 return "andi\t%0,%1,%2";
11445 case SYNC_INSN1_OR:
11446 return "or\t%0,%1,%z2";
11447 case SYNC_INSN1_ORI:
11448 return "ori\t%0,%1,%2";
11449 case SYNC_INSN1_XOR:
11450 return "xor\t%0,%1,%z2";
11451 case SYNC_INSN1_XORI:
11452 return "xori\t%0,%1,%2";
11454 gcc_unreachable ();
11457 /* Return the asm template associated with sync_insn2 value TYPE. */
11459 static const char *
11460 mips_sync_insn2_template (enum attr_sync_insn2 type)
11464 case SYNC_INSN2_NOP:
11465 gcc_unreachable ();
11466 case SYNC_INSN2_AND:
11467 return "and\t%0,%1,%z2";
11468 case SYNC_INSN2_XOR:
11469 return "xor\t%0,%1,%z2";
11470 case SYNC_INSN2_NOT:
11471 return "nor\t%0,%1,%.";
11473 gcc_unreachable ();
11476 /* OPERANDS are the operands to a sync loop instruction and INDEX is
11477 the value of the one of the sync_* attributes. Return the operand
11478 referred to by the attribute, or DEFAULT_VALUE if the insn doesn't
11479 have the associated attribute. */
11482 mips_get_sync_operand (rtx *operands, int index, rtx default_value)
11485 default_value = operands[index - 1];
11486 return default_value;
11489 /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn
11490 sequence for it. */
11493 mips_process_sync_loop (rtx insn, rtx *operands)
11495 rtx at, mem, oldval, newval, inclusive_mask, exclusive_mask;
11496 rtx required_oldval, insn1_op2, tmp1, tmp2, tmp3;
11497 unsigned int tmp3_insn;
11498 enum attr_sync_insn1 insn1;
11499 enum attr_sync_insn2 insn2;
11502 /* Read an operand from the sync_WHAT attribute and store it in
11503 variable WHAT. DEFAULT is the default value if no attribute
11505 #define READ_OPERAND(WHAT, DEFAULT) \
11506 WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \
11509 /* Read the memory. */
11510 READ_OPERAND (mem, 0);
11512 is_64bit_p = (GET_MODE_BITSIZE (GET_MODE (mem)) == 64);
11514 /* Read the other attributes. */
11515 at = gen_rtx_REG (GET_MODE (mem), AT_REGNUM);
11516 READ_OPERAND (oldval, at);
11517 READ_OPERAND (newval, at);
11518 READ_OPERAND (inclusive_mask, 0);
11519 READ_OPERAND (exclusive_mask, 0);
11520 READ_OPERAND (required_oldval, 0);
11521 READ_OPERAND (insn1_op2, 0);
11522 insn1 = get_attr_sync_insn1 (insn);
11523 insn2 = get_attr_sync_insn2 (insn);
11525 mips_multi_start ();
11527 /* Output the release side of the memory barrier. */
11528 if (get_attr_sync_release_barrier (insn) == SYNC_RELEASE_BARRIER_YES)
11530 if (required_oldval == 0 && TARGET_OCTEON)
11532 /* Octeon doesn't reorder reads, so a full barrier can be
11533 created by using SYNCW to order writes combined with the
11534 write from the following SC. When the SC successfully
11535 completes, we know that all preceding writes are also
11536 committed to the coherent memory system. It is possible
11537 for a single SYNCW to fail, but a pair of them will never
11538 fail, so we use two. */
11539 mips_multi_add_insn ("syncw", NULL);
11540 mips_multi_add_insn ("syncw", NULL);
11543 mips_multi_add_insn ("sync", NULL);
11546 /* Output the branch-back label. */
11547 mips_multi_add_label ("1:");
11549 /* OLDVAL = *MEM. */
11550 mips_multi_add_insn (is_64bit_p ? "lld\t%0,%1" : "ll\t%0,%1",
11551 oldval, mem, NULL);
11553 /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */
11554 if (required_oldval)
11556 if (inclusive_mask == 0)
11560 gcc_assert (oldval != at);
11561 mips_multi_add_insn ("and\t%0,%1,%2",
11562 at, oldval, inclusive_mask, NULL);
11565 mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1, required_oldval, NULL);
11568 /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */
11569 if (exclusive_mask == 0)
11573 gcc_assert (oldval != at);
11574 mips_multi_add_insn ("and\t%0,%1,%z2",
11575 at, oldval, exclusive_mask, NULL);
11579 /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2).
11581 We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit
11582 at least one instruction in that case. */
11583 if (insn1 == SYNC_INSN1_MOVE
11584 && (tmp1 != const0_rtx || insn2 != SYNC_INSN2_NOP))
11588 mips_multi_add_insn (mips_sync_insn1_template (insn1, is_64bit_p),
11589 newval, oldval, insn1_op2, NULL);
11593 /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */
11594 if (insn2 == SYNC_INSN2_NOP)
11598 mips_multi_add_insn (mips_sync_insn2_template (insn2),
11599 newval, tmp2, inclusive_mask, NULL);
11602 tmp3_insn = mips_multi_last_index ();
11604 /* $AT = $TMP1 | $TMP3. */
11605 if (tmp1 == const0_rtx || tmp3 == const0_rtx)
11607 mips_multi_set_operand (tmp3_insn, 0, at);
11612 gcc_assert (tmp1 != tmp3);
11613 mips_multi_add_insn ("or\t%0,%1,%2", at, tmp1, tmp3, NULL);
11616 /* if (!commit (*MEM = $AT)) goto 1.
11618 This will sometimes be a delayed branch; see the write code below
11620 mips_multi_add_insn (is_64bit_p ? "scd\t%0,%1" : "sc\t%0,%1", at, mem, NULL);
11621 mips_multi_add_insn ("beq%?\t%0,%.,1b", at, NULL);
11623 /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */
11624 if (insn1 != SYNC_INSN1_MOVE && insn1 != SYNC_INSN1_LI && tmp3 != newval)
11626 mips_multi_copy_insn (tmp3_insn);
11627 mips_multi_set_operand (mips_multi_last_index (), 0, newval);
11630 mips_multi_add_insn ("nop", NULL);
11632 /* Output the acquire side of the memory barrier. */
11633 if (TARGET_SYNC_AFTER_SC)
11634 mips_multi_add_insn ("sync", NULL);
11636 /* Output the exit label, if needed. */
11637 if (required_oldval)
11638 mips_multi_add_label ("2:");
11640 #undef READ_OPERAND
11643 /* Output and/or return the asm template for sync loop INSN, which has
11644 the operands given by OPERANDS. */
11647 mips_output_sync_loop (rtx insn, rtx *operands)
11649 mips_process_sync_loop (insn, operands);
11651 /* Use branch-likely instructions to work around the LL/SC R10000
11653 mips_branch_likely = TARGET_FIX_R10000;
11655 mips_push_asm_switch (&mips_noreorder);
11656 mips_push_asm_switch (&mips_nomacro);
11657 mips_push_asm_switch (&mips_noat);
11658 mips_start_ll_sc_sync_block ();
11660 mips_multi_write ();
11662 mips_end_ll_sc_sync_block ();
11663 mips_pop_asm_switch (&mips_noat);
11664 mips_pop_asm_switch (&mips_nomacro);
11665 mips_pop_asm_switch (&mips_noreorder);
11670 /* Return the number of individual instructions in sync loop INSN,
11671 which has the operands given by OPERANDS. */
11674 mips_sync_loop_insns (rtx insn, rtx *operands)
11676 mips_process_sync_loop (insn, operands);
11677 return mips_multi_num_insns;
11680 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
11681 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
11683 When working around R4000 and R4400 errata, we need to make sure that
11684 the division is not immediately followed by a shift[1][2]. We also
11685 need to stop the division from being put into a branch delay slot[3].
11686 The easiest way to avoid both problems is to add a nop after the
11687 division. When a divide-by-zero check is needed, this nop can be
11688 used to fill the branch delay slot.
11690 [1] If a double-word or a variable shift executes immediately
11691 after starting an integer division, the shift may give an
11692 incorrect result. See quotations of errata #16 and #28 from
11693 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
11694 in mips.md for details.
11696 [2] A similar bug to [1] exists for all revisions of the
11697 R4000 and the R4400 when run in an MC configuration.
11698 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
11700 "19. In this following sequence:
11702 ddiv (or ddivu or div or divu)
11703 dsll32 (or dsrl32, dsra32)
11705 if an MPT stall occurs, while the divide is slipping the cpu
11706 pipeline, then the following double shift would end up with an
11709 Workaround: The compiler needs to avoid generating any
11710 sequence with divide followed by extended double shift."
11712 This erratum is also present in "MIPS R4400MC Errata, Processor
11713 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
11714 & 3.0" as errata #10 and #4, respectively.
11716 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
11717 (also valid for MIPS R4000MC processors):
11719 "52. R4000SC: This bug does not apply for the R4000PC.
11721 There are two flavors of this bug:
11723 1) If the instruction just after divide takes an RF exception
11724 (tlb-refill, tlb-invalid) and gets an instruction cache
11725 miss (both primary and secondary) and the line which is
11726 currently in secondary cache at this index had the first
11727 data word, where the bits 5..2 are set, then R4000 would
11728 get a wrong result for the div.
11733 ------------------- # end-of page. -tlb-refill
11738 ------------------- # end-of page. -tlb-invalid
11741 2) If the divide is in the taken branch delay slot, where the
11742 target takes RF exception and gets an I-cache miss for the
11743 exception vector or where I-cache miss occurs for the
11744 target address, under the above mentioned scenarios, the
11745 div would get wrong results.
11748 j r2 # to next page mapped or unmapped
11749 div r8,r9 # this bug would be there as long
11750 # as there is an ICache miss and
11751 nop # the "data pattern" is present
11754 beq r0, r0, NextPage # to Next page
11758 This bug is present for div, divu, ddiv, and ddivu
11761 Workaround: For item 1), OS could make sure that the next page
11762 after the divide instruction is also mapped. For item 2), the
11763 compiler could make sure that the divide instruction is not in
11764 the branch delay slot."
11766 These processors have PRId values of 0x00004220 and 0x00004300 for
11767 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
11770 mips_output_division (const char *division, rtx *operands)
11775 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
11777 output_asm_insn (s, operands);
11780 if (TARGET_CHECK_ZERO_DIV)
11784 output_asm_insn (s, operands);
11785 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
11787 else if (GENERATE_DIVIDE_TRAPS)
11789 /* Avoid long replay penalty on load miss by putting the trap before
11792 output_asm_insn ("teq\t%2,%.,7", operands);
11795 output_asm_insn (s, operands);
11796 s = "teq\t%2,%.,7";
11801 output_asm_insn ("%(bne\t%2,%.,1f", operands);
11802 output_asm_insn (s, operands);
11803 s = "break\t7%)\n1:";
11809 /* Return true if IN_INSN is a multiply-add or multiply-subtract
11810 instruction and if OUT_INSN assigns to the accumulator operand. */
11813 mips_linked_madd_p (rtx out_insn, rtx in_insn)
11817 x = single_set (in_insn);
11823 if (GET_CODE (x) == PLUS
11824 && GET_CODE (XEXP (x, 0)) == MULT
11825 && reg_set_p (XEXP (x, 1), out_insn))
11828 if (GET_CODE (x) == MINUS
11829 && GET_CODE (XEXP (x, 1)) == MULT
11830 && reg_set_p (XEXP (x, 0), out_insn))
11836 /* True if the dependency between OUT_INSN and IN_INSN is on the store
11837 data rather than the address. We need this because the cprestore
11838 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
11839 which causes the default routine to abort. We just return false
11843 mips_store_data_bypass_p (rtx out_insn, rtx in_insn)
11845 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
11848 return !store_data_bypass_p (out_insn, in_insn);
11852 /* Variables and flags used in scheduler hooks when tuning for
11856 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
11859 /* If true, then next ALU1/2 instruction will go to ALU1. */
11862 /* If true, then next FALU1/2 unstruction will go to FALU1. */
11865 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
11866 int alu1_core_unit_code;
11867 int alu2_core_unit_code;
11868 int falu1_core_unit_code;
11869 int falu2_core_unit_code;
11871 /* True if current cycle has a multi instruction.
11872 This flag is used in mips_ls2_dfa_post_advance_cycle. */
11873 bool cycle_has_multi_p;
11875 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
11876 These are used in mips_ls2_dfa_post_advance_cycle to initialize
11878 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
11879 instruction to go ALU1. */
11880 rtx alu1_turn_enabled_insn;
11881 rtx alu2_turn_enabled_insn;
11882 rtx falu1_turn_enabled_insn;
11883 rtx falu2_turn_enabled_insn;
11886 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
11887 dependencies have no cost, except on the 20Kc where output-dependence
11888 is treated like input-dependence. */
11891 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
11892 rtx dep ATTRIBUTE_UNUSED, int cost)
11894 if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT
11897 if (REG_NOTE_KIND (link) != 0)
11902 /* Return the number of instructions that can be issued per cycle. */
11905 mips_issue_rate (void)
11909 case PROCESSOR_74KC:
11910 case PROCESSOR_74KF2_1:
11911 case PROCESSOR_74KF1_1:
11912 case PROCESSOR_74KF3_2:
11913 /* The 74k is not strictly quad-issue cpu, but can be seen as one
11914 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
11915 but in reality only a maximum of 3 insns can be issued as
11916 floating-point loads and stores also require a slot in the
11918 case PROCESSOR_R10000:
11919 /* All R10K Processors are quad-issue (being the first MIPS
11920 processors to support this feature). */
11923 case PROCESSOR_20KC:
11924 case PROCESSOR_R4130:
11925 case PROCESSOR_R5400:
11926 case PROCESSOR_R5500:
11927 case PROCESSOR_R7000:
11928 case PROCESSOR_R9000:
11929 case PROCESSOR_OCTEON:
11932 case PROCESSOR_SB1:
11933 case PROCESSOR_SB1A:
11934 /* This is actually 4, but we get better performance if we claim 3.
11935 This is partly because of unwanted speculative code motion with the
11936 larger number, and partly because in most common cases we can't
11937 reach the theoretical max of 4. */
11940 case PROCESSOR_LOONGSON_2E:
11941 case PROCESSOR_LOONGSON_2F:
11942 case PROCESSOR_LOONGSON_3A:
11950 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
11953 mips_ls2_init_dfa_post_cycle_insn (void)
11956 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
11957 mips_ls2.alu1_turn_enabled_insn = get_insns ();
11961 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
11962 mips_ls2.alu2_turn_enabled_insn = get_insns ();
11966 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
11967 mips_ls2.falu1_turn_enabled_insn = get_insns ();
11971 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
11972 mips_ls2.falu2_turn_enabled_insn = get_insns ();
11975 mips_ls2.alu1_core_unit_code = get_cpu_unit_code ("ls2_alu1_core");
11976 mips_ls2.alu2_core_unit_code = get_cpu_unit_code ("ls2_alu2_core");
11977 mips_ls2.falu1_core_unit_code = get_cpu_unit_code ("ls2_falu1_core");
11978 mips_ls2.falu2_core_unit_code = get_cpu_unit_code ("ls2_falu2_core");
11981 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
11982 Init data used in mips_dfa_post_advance_cycle. */
11985 mips_init_dfa_post_cycle_insn (void)
11987 if (TUNE_LOONGSON_2EF)
11988 mips_ls2_init_dfa_post_cycle_insn ();
11991 /* Initialize STATE when scheduling for Loongson 2E/2F.
11992 Support round-robin dispatch scheme by enabling only one of
11993 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
11997 mips_ls2_dfa_post_advance_cycle (state_t state)
11999 if (cpu_unit_reservation_p (state, mips_ls2.alu1_core_unit_code))
12001 /* Though there are no non-pipelined ALU1 insns,
12002 we can get an instruction of type 'multi' before reload. */
12003 gcc_assert (mips_ls2.cycle_has_multi_p);
12004 mips_ls2.alu1_turn_p = false;
12007 mips_ls2.cycle_has_multi_p = false;
12009 if (cpu_unit_reservation_p (state, mips_ls2.alu2_core_unit_code))
12010 /* We have a non-pipelined alu instruction in the core,
12011 adjust round-robin counter. */
12012 mips_ls2.alu1_turn_p = true;
12014 if (mips_ls2.alu1_turn_p)
12016 if (state_transition (state, mips_ls2.alu1_turn_enabled_insn) >= 0)
12017 gcc_unreachable ();
12021 if (state_transition (state, mips_ls2.alu2_turn_enabled_insn) >= 0)
12022 gcc_unreachable ();
12025 if (cpu_unit_reservation_p (state, mips_ls2.falu1_core_unit_code))
12027 /* There are no non-pipelined FALU1 insns. */
12028 gcc_unreachable ();
12029 mips_ls2.falu1_turn_p = false;
12032 if (cpu_unit_reservation_p (state, mips_ls2.falu2_core_unit_code))
12033 /* We have a non-pipelined falu instruction in the core,
12034 adjust round-robin counter. */
12035 mips_ls2.falu1_turn_p = true;
12037 if (mips_ls2.falu1_turn_p)
12039 if (state_transition (state, mips_ls2.falu1_turn_enabled_insn) >= 0)
12040 gcc_unreachable ();
12044 if (state_transition (state, mips_ls2.falu2_turn_enabled_insn) >= 0)
12045 gcc_unreachable ();
12049 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
12050 This hook is being called at the start of each cycle. */
12053 mips_dfa_post_advance_cycle (void)
12055 if (TUNE_LOONGSON_2EF)
12056 mips_ls2_dfa_post_advance_cycle (curr_state);
12059 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
12060 be as wide as the scheduling freedom in the DFA. */
12063 mips_multipass_dfa_lookahead (void)
12065 /* Can schedule up to 4 of the 6 function units in any one cycle. */
12069 if (TUNE_LOONGSON_2EF || TUNE_LOONGSON_3A)
12078 /* Remove the instruction at index LOWER from ready queue READY and
12079 reinsert it in front of the instruction at index HIGHER. LOWER must
12083 mips_promote_ready (rtx *ready, int lower, int higher)
12088 new_head = ready[lower];
12089 for (i = lower; i < higher; i++)
12090 ready[i] = ready[i + 1];
12091 ready[i] = new_head;
12094 /* If the priority of the instruction at POS2 in the ready queue READY
12095 is within LIMIT units of that of the instruction at POS1, swap the
12096 instructions if POS2 is not already less than POS1. */
12099 mips_maybe_swap_ready (rtx *ready, int pos1, int pos2, int limit)
12102 && INSN_PRIORITY (ready[pos1]) + limit >= INSN_PRIORITY (ready[pos2]))
12106 temp = ready[pos1];
12107 ready[pos1] = ready[pos2];
12108 ready[pos2] = temp;
12112 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
12113 that may clobber hi or lo. */
12114 static rtx mips_macc_chains_last_hilo;
12116 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
12117 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
12120 mips_macc_chains_record (rtx insn)
12122 if (get_attr_may_clobber_hilo (insn))
12123 mips_macc_chains_last_hilo = insn;
12126 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
12127 has NREADY elements, looking for a multiply-add or multiply-subtract
12128 instruction that is cumulative with mips_macc_chains_last_hilo.
12129 If there is one, promote it ahead of anything else that might
12130 clobber hi or lo. */
12133 mips_macc_chains_reorder (rtx *ready, int nready)
12137 if (mips_macc_chains_last_hilo != 0)
12138 for (i = nready - 1; i >= 0; i--)
12139 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
12141 for (j = nready - 1; j > i; j--)
12142 if (recog_memoized (ready[j]) >= 0
12143 && get_attr_may_clobber_hilo (ready[j]))
12145 mips_promote_ready (ready, i, j);
12152 /* The last instruction to be scheduled. */
12153 static rtx vr4130_last_insn;
12155 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
12156 points to an rtx that is initially an instruction. Nullify the rtx
12157 if the instruction uses the value of register X. */
12160 vr4130_true_reg_dependence_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
12165 insn_ptr = (rtx *) data;
12168 && reg_referenced_p (x, PATTERN (*insn_ptr)))
12172 /* Return true if there is true register dependence between vr4130_last_insn
12176 vr4130_true_reg_dependence_p (rtx insn)
12178 note_stores (PATTERN (vr4130_last_insn),
12179 vr4130_true_reg_dependence_p_1, &insn);
12183 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
12184 the ready queue and that INSN2 is the instruction after it, return
12185 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
12186 in which INSN1 and INSN2 can probably issue in parallel, but for
12187 which (INSN2, INSN1) should be less sensitive to instruction
12188 alignment than (INSN1, INSN2). See 4130.md for more details. */
12191 vr4130_swap_insns_p (rtx insn1, rtx insn2)
12193 sd_iterator_def sd_it;
12196 /* Check for the following case:
12198 1) there is some other instruction X with an anti dependence on INSN1;
12199 2) X has a higher priority than INSN2; and
12200 3) X is an arithmetic instruction (and thus has no unit restrictions).
12202 If INSN1 is the last instruction blocking X, it would better to
12203 choose (INSN1, X) over (INSN2, INSN1). */
12204 FOR_EACH_DEP (insn1, SD_LIST_FORW, sd_it, dep)
12205 if (DEP_TYPE (dep) == REG_DEP_ANTI
12206 && INSN_PRIORITY (DEP_CON (dep)) > INSN_PRIORITY (insn2)
12207 && recog_memoized (DEP_CON (dep)) >= 0
12208 && get_attr_vr4130_class (DEP_CON (dep)) == VR4130_CLASS_ALU)
12211 if (vr4130_last_insn != 0
12212 && recog_memoized (insn1) >= 0
12213 && recog_memoized (insn2) >= 0)
12215 /* See whether INSN1 and INSN2 use different execution units,
12216 or if they are both ALU-type instructions. If so, they can
12217 probably execute in parallel. */
12218 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
12219 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
12220 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
12222 /* If only one of the instructions has a dependence on
12223 vr4130_last_insn, prefer to schedule the other one first. */
12224 bool dep1_p = vr4130_true_reg_dependence_p (insn1);
12225 bool dep2_p = vr4130_true_reg_dependence_p (insn2);
12226 if (dep1_p != dep2_p)
12229 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
12230 is not an ALU-type instruction and if INSN1 uses the same
12231 execution unit. (Note that if this condition holds, we already
12232 know that INSN2 uses a different execution unit.) */
12233 if (class1 != VR4130_CLASS_ALU
12234 && recog_memoized (vr4130_last_insn) >= 0
12235 && class1 == get_attr_vr4130_class (vr4130_last_insn))
12242 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
12243 queue with at least two instructions. Swap the first two if
12244 vr4130_swap_insns_p says that it could be worthwhile. */
12247 vr4130_reorder (rtx *ready, int nready)
12249 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
12250 mips_promote_ready (ready, nready - 2, nready - 1);
12253 /* Record whether last 74k AGEN instruction was a load or store. */
12254 static enum attr_type mips_last_74k_agen_insn = TYPE_UNKNOWN;
12256 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
12257 resets to TYPE_UNKNOWN state. */
12260 mips_74k_agen_init (rtx insn)
12262 if (!insn || CALL_P (insn) || JUMP_P (insn))
12263 mips_last_74k_agen_insn = TYPE_UNKNOWN;
12266 enum attr_type type = get_attr_type (insn);
12267 if (type == TYPE_LOAD || type == TYPE_STORE)
12268 mips_last_74k_agen_insn = type;
12272 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
12273 loads to be grouped together, and multiple stores to be grouped
12274 together. Swap things around in the ready queue to make this happen. */
12277 mips_74k_agen_reorder (rtx *ready, int nready)
12280 int store_pos, load_pos;
12285 for (i = nready - 1; i >= 0; i--)
12287 rtx insn = ready[i];
12288 if (USEFUL_INSN_P (insn))
12289 switch (get_attr_type (insn))
12292 if (store_pos == -1)
12297 if (load_pos == -1)
12306 if (load_pos == -1 || store_pos == -1)
12309 switch (mips_last_74k_agen_insn)
12312 /* Prefer to schedule loads since they have a higher latency. */
12314 /* Swap loads to the front of the queue. */
12315 mips_maybe_swap_ready (ready, load_pos, store_pos, 4);
12318 /* Swap stores to the front of the queue. */
12319 mips_maybe_swap_ready (ready, store_pos, load_pos, 4);
12326 /* Implement TARGET_SCHED_INIT. */
12329 mips_sched_init (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12330 int max_ready ATTRIBUTE_UNUSED)
12332 mips_macc_chains_last_hilo = 0;
12333 vr4130_last_insn = 0;
12334 mips_74k_agen_init (NULL_RTX);
12336 /* When scheduling for Loongson2, branch instructions go to ALU1,
12337 therefore basic block is most likely to start with round-robin counter
12338 pointed to ALU2. */
12339 mips_ls2.alu1_turn_p = false;
12340 mips_ls2.falu1_turn_p = true;
12343 /* Subroutine used by TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
12346 mips_sched_reorder_1 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12347 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
12349 if (!reload_completed
12350 && TUNE_MACC_CHAINS
12352 mips_macc_chains_reorder (ready, *nreadyp);
12354 if (reload_completed
12356 && !TARGET_VR4130_ALIGN
12358 vr4130_reorder (ready, *nreadyp);
12361 mips_74k_agen_reorder (ready, *nreadyp);
12364 /* Implement TARGET_SCHED_REORDER. */
12367 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12368 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
12370 mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle);
12371 return mips_issue_rate ();
12374 /* Implement TARGET_SCHED_REORDER2. */
12377 mips_sched_reorder2 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12378 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
12380 mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle);
12381 return cached_can_issue_more;
12384 /* Update round-robin counters for ALU1/2 and FALU1/2. */
12387 mips_ls2_variable_issue (rtx insn)
12389 if (mips_ls2.alu1_turn_p)
12391 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu1_core_unit_code))
12392 mips_ls2.alu1_turn_p = false;
12396 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu2_core_unit_code))
12397 mips_ls2.alu1_turn_p = true;
12400 if (mips_ls2.falu1_turn_p)
12402 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu1_core_unit_code))
12403 mips_ls2.falu1_turn_p = false;
12407 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu2_core_unit_code))
12408 mips_ls2.falu1_turn_p = true;
12411 if (recog_memoized (insn) >= 0)
12412 mips_ls2.cycle_has_multi_p |= (get_attr_type (insn) == TYPE_MULTI);
12415 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
12418 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12419 rtx insn, int more)
12421 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
12422 if (USEFUL_INSN_P (insn))
12424 if (get_attr_type (insn) != TYPE_GHOST)
12426 if (!reload_completed && TUNE_MACC_CHAINS)
12427 mips_macc_chains_record (insn);
12428 vr4130_last_insn = insn;
12430 mips_74k_agen_init (insn);
12431 else if (TUNE_LOONGSON_2EF)
12432 mips_ls2_variable_issue (insn);
12435 /* Instructions of type 'multi' should all be split before
12436 the second scheduling pass. */
12437 gcc_assert (!reload_completed
12438 || recog_memoized (insn) < 0
12439 || get_attr_type (insn) != TYPE_MULTI);
12441 cached_can_issue_more = more;
12445 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
12446 return the first operand of the associated PREF or PREFX insn. */
12449 mips_prefetch_cookie (rtx write, rtx locality)
12451 /* store_streamed / load_streamed. */
12452 if (INTVAL (locality) <= 0)
12453 return GEN_INT (INTVAL (write) + 4);
12455 /* store / load. */
12456 if (INTVAL (locality) <= 2)
12459 /* store_retained / load_retained. */
12460 return GEN_INT (INTVAL (write) + 6);
12463 /* Flags that indicate when a built-in function is available.
12465 BUILTIN_AVAIL_NON_MIPS16
12466 The function is available on the current target, but only
12467 in non-MIPS16 mode. */
12468 #define BUILTIN_AVAIL_NON_MIPS16 1
12470 /* Declare an availability predicate for built-in functions that
12471 require non-MIPS16 mode and also require COND to be true.
12472 NAME is the main part of the predicate's name. */
12473 #define AVAIL_NON_MIPS16(NAME, COND) \
12474 static unsigned int \
12475 mips_builtin_avail_##NAME (void) \
12477 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
12480 /* This structure describes a single built-in function. */
12481 struct mips_builtin_description {
12482 /* The code of the main .md file instruction. See mips_builtin_type
12483 for more information. */
12484 enum insn_code icode;
12486 /* The floating-point comparison code to use with ICODE, if any. */
12487 enum mips_fp_condition cond;
12489 /* The name of the built-in function. */
12492 /* Specifies how the function should be expanded. */
12493 enum mips_builtin_type builtin_type;
12495 /* The function's prototype. */
12496 enum mips_function_type function_type;
12498 /* Whether the function is available. */
12499 unsigned int (*avail) (void);
12502 AVAIL_NON_MIPS16 (paired_single, TARGET_PAIRED_SINGLE_FLOAT)
12503 AVAIL_NON_MIPS16 (sb1_paired_single, TARGET_SB1 && TARGET_PAIRED_SINGLE_FLOAT)
12504 AVAIL_NON_MIPS16 (mips3d, TARGET_MIPS3D)
12505 AVAIL_NON_MIPS16 (dsp, TARGET_DSP)
12506 AVAIL_NON_MIPS16 (dspr2, TARGET_DSPR2)
12507 AVAIL_NON_MIPS16 (dsp_32, !TARGET_64BIT && TARGET_DSP)
12508 AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2)
12509 AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS)
12510 AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
12512 /* Construct a mips_builtin_description from the given arguments.
12514 INSN is the name of the associated instruction pattern, without the
12515 leading CODE_FOR_mips_.
12517 CODE is the floating-point condition code associated with the
12518 function. It can be 'f' if the field is not applicable.
12520 NAME is the name of the function itself, without the leading
12523 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
12525 AVAIL is the name of the availability predicate, without the leading
12526 mips_builtin_avail_. */
12527 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
12528 FUNCTION_TYPE, AVAIL) \
12529 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
12530 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
12531 mips_builtin_avail_ ## AVAIL }
12533 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
12534 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
12535 are as for MIPS_BUILTIN. */
12536 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
12537 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
12539 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
12540 are subject to mips_builtin_avail_<AVAIL>. */
12541 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
12542 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
12543 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
12544 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
12545 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
12547 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
12548 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
12549 while the any and all forms are subject to mips_builtin_avail_mips3d. */
12550 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
12551 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
12552 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
12554 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
12555 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
12557 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
12558 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
12560 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
12561 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
12564 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
12565 are subject to mips_builtin_avail_mips3d. */
12566 #define CMP_4S_BUILTINS(INSN, COND) \
12567 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
12568 MIPS_BUILTIN_CMP_ANY, \
12569 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
12570 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
12571 MIPS_BUILTIN_CMP_ALL, \
12572 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
12574 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
12575 instruction requires mips_builtin_avail_<AVAIL>. */
12576 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
12577 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
12578 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
12580 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
12581 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
12584 /* Define all the built-in functions related to C.cond.fmt condition COND. */
12585 #define CMP_BUILTINS(COND) \
12586 MOVTF_BUILTINS (c, COND, paired_single), \
12587 MOVTF_BUILTINS (cabs, COND, mips3d), \
12588 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
12589 CMP_PS_BUILTINS (c, COND, paired_single), \
12590 CMP_PS_BUILTINS (cabs, COND, mips3d), \
12591 CMP_4S_BUILTINS (c, COND), \
12592 CMP_4S_BUILTINS (cabs, COND)
12594 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
12595 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
12596 and AVAIL are as for MIPS_BUILTIN. */
12597 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
12598 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
12599 FUNCTION_TYPE, AVAIL)
12601 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
12602 branch instruction. AVAIL is as for MIPS_BUILTIN. */
12603 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
12604 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
12605 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
12607 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
12608 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
12609 builtin_description field. */
12610 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
12611 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
12612 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
12613 FUNCTION_TYPE, mips_builtin_avail_loongson }
12615 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
12616 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
12617 builtin_description field. */
12618 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
12619 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
12621 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
12622 We use functions of this form when the same insn can be usefully applied
12623 to more than one datatype. */
12624 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
12625 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
12627 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
12628 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
12629 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
12630 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
12631 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
12632 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
12633 #define CODE_FOR_mips_mult CODE_FOR_mulsidi3_32bit
12634 #define CODE_FOR_mips_multu CODE_FOR_umulsidi3_32bit
12636 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
12637 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
12638 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
12639 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
12640 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
12641 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
12642 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
12643 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
12644 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
12645 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
12646 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
12647 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
12648 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
12649 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
12650 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
12651 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
12652 #define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3
12653 #define CODE_FOR_loongson_psllh CODE_FOR_ashlv4hi3
12654 #define CODE_FOR_loongson_psllw CODE_FOR_ashlv2si3
12655 #define CODE_FOR_loongson_psrlh CODE_FOR_lshrv4hi3
12656 #define CODE_FOR_loongson_psrlw CODE_FOR_lshrv2si3
12657 #define CODE_FOR_loongson_psrah CODE_FOR_ashrv4hi3
12658 #define CODE_FOR_loongson_psraw CODE_FOR_ashrv2si3
12659 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
12660 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
12661 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
12662 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
12663 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
12664 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
12665 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
12666 #define CODE_FOR_loongson_punpckhbh CODE_FOR_vec_interleave_highv8qi
12667 #define CODE_FOR_loongson_punpckhhw CODE_FOR_vec_interleave_highv4hi
12668 #define CODE_FOR_loongson_punpckhwd CODE_FOR_vec_interleave_highv2si
12669 #define CODE_FOR_loongson_punpcklbh CODE_FOR_vec_interleave_lowv8qi
12670 #define CODE_FOR_loongson_punpcklhw CODE_FOR_vec_interleave_lowv4hi
12671 #define CODE_FOR_loongson_punpcklwd CODE_FOR_vec_interleave_lowv2si
12673 static const struct mips_builtin_description mips_builtins[] = {
12674 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
12675 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
12676 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
12677 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
12678 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, paired_single),
12679 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, paired_single),
12680 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, paired_single),
12681 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, paired_single),
12683 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT, paired_single),
12684 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
12685 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
12686 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
12687 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, mips3d),
12689 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, mips3d),
12690 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, mips3d),
12691 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
12692 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
12693 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
12694 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
12696 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, mips3d),
12697 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, mips3d),
12698 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
12699 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
12700 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
12701 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
12703 MIPS_FP_CONDITIONS (CMP_BUILTINS),
12705 /* Built-in functions for the SB-1 processor. */
12706 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, sb1_paired_single),
12708 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
12709 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12710 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12711 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
12712 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12713 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12714 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12715 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12716 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
12717 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12718 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12719 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, dsp),
12720 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, dsp),
12721 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, dsp),
12722 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, dsp),
12723 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, dsp),
12724 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, dsp),
12725 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
12726 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
12727 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
12728 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
12729 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, dsp),
12730 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, dsp),
12731 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
12732 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
12733 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
12734 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
12735 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
12736 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
12737 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
12738 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
12739 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
12740 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
12741 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
12742 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
12743 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
12744 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
12745 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
12746 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, dsp),
12747 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
12748 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
12749 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12750 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
12751 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
12752 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, dsp),
12753 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, dsp),
12754 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, dsp),
12755 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, dsp),
12756 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
12757 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
12758 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
12759 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
12760 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
12761 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
12762 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
12763 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
12764 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
12765 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12766 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12767 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12768 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, dsp),
12769 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, dsp),
12770 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_POINTER_SI, dsp),
12771 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_POINTER_SI, dsp),
12772 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_POINTER_SI, dsp),
12773 BPOSGE_BUILTIN (32, dsp),
12775 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
12776 DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, dspr2),
12777 DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12778 DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12779 DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
12780 DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
12781 DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
12782 DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
12783 DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
12784 DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
12785 DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
12786 DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12787 DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12788 DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12789 DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12790 DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12791 DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dspr2),
12792 DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
12793 DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
12794 DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
12795 DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
12796 DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
12797 DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, dspr2),
12798 DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12799 DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12800 DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
12801 DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
12802 DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12803 DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12804 DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12805 DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12806 DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12807 DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12808 DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12809 DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12811 /* Built-in functions for the DSP ASE (32-bit only). */
12812 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
12813 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
12814 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
12815 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
12816 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12817 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12818 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12819 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
12820 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
12821 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12822 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12823 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12824 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12825 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
12826 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
12827 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
12828 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, dsp_32),
12829 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, dsp_32),
12830 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, dsp_32),
12831 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, dsp_32),
12832 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, dsp_32),
12833 DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
12834 DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32),
12835 DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
12836 DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32),
12837 DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, dsp_32),
12838 DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, dsp_32),
12840 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
12841 DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12842 DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12843 DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12844 DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12845 DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12846 DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12847 DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12848 DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12849 DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12851 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
12852 LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI),
12853 LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI),
12854 LOONGSON_BUILTIN (packushb, MIPS_UV8QI_FTYPE_UV4HI_UV4HI),
12855 LOONGSON_BUILTIN_SUFFIX (paddw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12856 LOONGSON_BUILTIN_SUFFIX (paddh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12857 LOONGSON_BUILTIN_SUFFIX (paddb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12858 LOONGSON_BUILTIN_SUFFIX (paddw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
12859 LOONGSON_BUILTIN_SUFFIX (paddh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12860 LOONGSON_BUILTIN_SUFFIX (paddb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
12861 LOONGSON_BUILTIN_SUFFIX (paddd, u, MIPS_UDI_FTYPE_UDI_UDI),
12862 LOONGSON_BUILTIN_SUFFIX (paddd, s, MIPS_DI_FTYPE_DI_DI),
12863 LOONGSON_BUILTIN (paddsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12864 LOONGSON_BUILTIN (paddsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
12865 LOONGSON_BUILTIN (paddush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12866 LOONGSON_BUILTIN (paddusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12867 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_ud, MIPS_UDI_FTYPE_UDI_UDI),
12868 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_uw, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12869 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_uh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12870 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_ub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12871 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_sd, MIPS_DI_FTYPE_DI_DI),
12872 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_sw, MIPS_V2SI_FTYPE_V2SI_V2SI),
12873 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_sh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12874 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_sb, MIPS_V8QI_FTYPE_V8QI_V8QI),
12875 LOONGSON_BUILTIN (pavgh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12876 LOONGSON_BUILTIN (pavgb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12877 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12878 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12879 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12880 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
12881 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12882 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
12883 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12884 LOONGSON_BUILTIN_SUFFIX (pcmpgth, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12885 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12886 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
12887 LOONGSON_BUILTIN_SUFFIX (pcmpgth, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12888 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
12889 LOONGSON_BUILTIN_SUFFIX (pextrh, u, MIPS_UV4HI_FTYPE_UV4HI_USI),
12890 LOONGSON_BUILTIN_SUFFIX (pextrh, s, MIPS_V4HI_FTYPE_V4HI_USI),
12891 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12892 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12893 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12894 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12895 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12896 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12897 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12898 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12899 LOONGSON_BUILTIN (pmaddhw, MIPS_V2SI_FTYPE_V4HI_V4HI),
12900 LOONGSON_BUILTIN (pmaxsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12901 LOONGSON_BUILTIN (pmaxub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12902 LOONGSON_BUILTIN (pminsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12903 LOONGSON_BUILTIN (pminub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12904 LOONGSON_BUILTIN_SUFFIX (pmovmskb, u, MIPS_UV8QI_FTYPE_UV8QI),
12905 LOONGSON_BUILTIN_SUFFIX (pmovmskb, s, MIPS_V8QI_FTYPE_V8QI),
12906 LOONGSON_BUILTIN (pmulhuh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12907 LOONGSON_BUILTIN (pmulhh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12908 LOONGSON_BUILTIN (pmullh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12909 LOONGSON_BUILTIN (pmuluw, MIPS_UDI_FTYPE_UV2SI_UV2SI),
12910 LOONGSON_BUILTIN (pasubub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12911 LOONGSON_BUILTIN (biadd, MIPS_UV4HI_FTYPE_UV8QI),
12912 LOONGSON_BUILTIN (psadbh, MIPS_UV4HI_FTYPE_UV8QI_UV8QI),
12913 LOONGSON_BUILTIN_SUFFIX (pshufh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI_UQI),
12914 LOONGSON_BUILTIN_SUFFIX (pshufh, s, MIPS_V4HI_FTYPE_V4HI_V4HI_UQI),
12915 LOONGSON_BUILTIN_SUFFIX (psllh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
12916 LOONGSON_BUILTIN_SUFFIX (psllh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
12917 LOONGSON_BUILTIN_SUFFIX (psllw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
12918 LOONGSON_BUILTIN_SUFFIX (psllw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
12919 LOONGSON_BUILTIN_SUFFIX (psrah, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
12920 LOONGSON_BUILTIN_SUFFIX (psrah, s, MIPS_V4HI_FTYPE_V4HI_UQI),
12921 LOONGSON_BUILTIN_SUFFIX (psraw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
12922 LOONGSON_BUILTIN_SUFFIX (psraw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
12923 LOONGSON_BUILTIN_SUFFIX (psrlh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
12924 LOONGSON_BUILTIN_SUFFIX (psrlh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
12925 LOONGSON_BUILTIN_SUFFIX (psrlw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
12926 LOONGSON_BUILTIN_SUFFIX (psrlw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
12927 LOONGSON_BUILTIN_SUFFIX (psubw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12928 LOONGSON_BUILTIN_SUFFIX (psubh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12929 LOONGSON_BUILTIN_SUFFIX (psubb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12930 LOONGSON_BUILTIN_SUFFIX (psubw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
12931 LOONGSON_BUILTIN_SUFFIX (psubh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12932 LOONGSON_BUILTIN_SUFFIX (psubb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
12933 LOONGSON_BUILTIN_SUFFIX (psubd, u, MIPS_UDI_FTYPE_UDI_UDI),
12934 LOONGSON_BUILTIN_SUFFIX (psubd, s, MIPS_DI_FTYPE_DI_DI),
12935 LOONGSON_BUILTIN (psubsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12936 LOONGSON_BUILTIN (psubsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
12937 LOONGSON_BUILTIN (psubush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12938 LOONGSON_BUILTIN (psubusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12939 LOONGSON_BUILTIN_SUFFIX (punpckhbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12940 LOONGSON_BUILTIN_SUFFIX (punpckhhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12941 LOONGSON_BUILTIN_SUFFIX (punpckhwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12942 LOONGSON_BUILTIN_SUFFIX (punpckhbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
12943 LOONGSON_BUILTIN_SUFFIX (punpckhhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12944 LOONGSON_BUILTIN_SUFFIX (punpckhwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
12945 LOONGSON_BUILTIN_SUFFIX (punpcklbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12946 LOONGSON_BUILTIN_SUFFIX (punpcklhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12947 LOONGSON_BUILTIN_SUFFIX (punpcklwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12948 LOONGSON_BUILTIN_SUFFIX (punpcklbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
12949 LOONGSON_BUILTIN_SUFFIX (punpcklhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12950 LOONGSON_BUILTIN_SUFFIX (punpcklwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
12952 /* Sundry other built-in functions. */
12953 DIRECT_NO_TARGET_BUILTIN (cache, MIPS_VOID_FTYPE_SI_CVPOINTER, cache)
12956 /* Index I is the function declaration for mips_builtins[I], or null if the
12957 function isn't defined on this target. */
12958 static GTY(()) tree mips_builtin_decls[ARRAY_SIZE (mips_builtins)];
12960 /* MODE is a vector mode whose elements have type TYPE. Return the type
12961 of the vector itself. */
12964 mips_builtin_vector_type (tree type, enum machine_mode mode)
12966 static tree types[2 * (int) MAX_MACHINE_MODE];
12969 mode_index = (int) mode;
12971 if (TREE_CODE (type) == INTEGER_TYPE && TYPE_UNSIGNED (type))
12972 mode_index += MAX_MACHINE_MODE;
12974 if (types[mode_index] == NULL_TREE)
12975 types[mode_index] = build_vector_type_for_mode (type, mode);
12976 return types[mode_index];
12979 /* Return a type for 'const volatile void *'. */
12982 mips_build_cvpointer_type (void)
12986 if (cache == NULL_TREE)
12987 cache = build_pointer_type (build_qualified_type
12989 TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE));
12993 /* Source-level argument types. */
12994 #define MIPS_ATYPE_VOID void_type_node
12995 #define MIPS_ATYPE_INT integer_type_node
12996 #define MIPS_ATYPE_POINTER ptr_type_node
12997 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
12999 /* Standard mode-based argument types. */
13000 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
13001 #define MIPS_ATYPE_SI intSI_type_node
13002 #define MIPS_ATYPE_USI unsigned_intSI_type_node
13003 #define MIPS_ATYPE_DI intDI_type_node
13004 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
13005 #define MIPS_ATYPE_SF float_type_node
13006 #define MIPS_ATYPE_DF double_type_node
13008 /* Vector argument types. */
13009 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
13010 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
13011 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
13012 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
13013 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
13014 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
13015 #define MIPS_ATYPE_UV2SI \
13016 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
13017 #define MIPS_ATYPE_UV4HI \
13018 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
13019 #define MIPS_ATYPE_UV8QI \
13020 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
13022 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
13023 their associated MIPS_ATYPEs. */
13024 #define MIPS_FTYPE_ATYPES1(A, B) \
13025 MIPS_ATYPE_##A, MIPS_ATYPE_##B
13027 #define MIPS_FTYPE_ATYPES2(A, B, C) \
13028 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
13030 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
13031 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
13033 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
13034 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
13037 /* Return the function type associated with function prototype TYPE. */
13040 mips_build_function_type (enum mips_function_type type)
13042 static tree types[(int) MIPS_MAX_FTYPE_MAX];
13044 if (types[(int) type] == NULL_TREE)
13047 #define DEF_MIPS_FTYPE(NUM, ARGS) \
13048 case MIPS_FTYPE_NAME##NUM ARGS: \
13049 types[(int) type] \
13050 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
13053 #include "config/mips/mips-ftypes.def"
13054 #undef DEF_MIPS_FTYPE
13056 gcc_unreachable ();
13059 return types[(int) type];
13062 /* Implement TARGET_INIT_BUILTINS. */
13065 mips_init_builtins (void)
13067 const struct mips_builtin_description *d;
13070 /* Iterate through all of the bdesc arrays, initializing all of the
13071 builtin functions. */
13072 for (i = 0; i < ARRAY_SIZE (mips_builtins); i++)
13074 d = &mips_builtins[i];
13076 mips_builtin_decls[i]
13077 = add_builtin_function (d->name,
13078 mips_build_function_type (d->function_type),
13079 i, BUILT_IN_MD, NULL, NULL);
13083 /* Implement TARGET_BUILTIN_DECL. */
13086 mips_builtin_decl (unsigned int code, bool initialize_p ATTRIBUTE_UNUSED)
13088 if (code >= ARRAY_SIZE (mips_builtins))
13089 return error_mark_node;
13090 return mips_builtin_decls[code];
13093 /* Take argument ARGNO from EXP's argument list and convert it into
13094 an expand operand. Store the operand in *OP. */
13097 mips_prepare_builtin_arg (struct expand_operand *op, tree exp,
13098 unsigned int argno)
13103 arg = CALL_EXPR_ARG (exp, argno);
13104 value = expand_normal (arg);
13105 create_input_operand (op, value, TYPE_MODE (TREE_TYPE (arg)));
13108 /* Expand instruction ICODE as part of a built-in function sequence.
13109 Use the first NOPS elements of OPS as the instruction's operands.
13110 HAS_TARGET_P is true if operand 0 is a target; it is false if the
13111 instruction has no target.
13113 Return the target rtx if HAS_TARGET_P, otherwise return const0_rtx. */
13116 mips_expand_builtin_insn (enum insn_code icode, unsigned int nops,
13117 struct expand_operand *ops, bool has_target_p)
13119 if (!maybe_expand_insn (icode, nops, ops))
13121 error ("invalid argument to built-in function");
13122 return has_target_p ? gen_reg_rtx (ops[0].mode) : const0_rtx;
13124 return has_target_p ? ops[0].value : const0_rtx;
13127 /* Expand a floating-point comparison for built-in function call EXP.
13128 The first NARGS arguments are the values to be compared. ICODE is
13129 the .md pattern that does the comparison and COND is the condition
13130 that is being tested. Return an rtx for the result. */
13133 mips_expand_builtin_compare_1 (enum insn_code icode,
13134 enum mips_fp_condition cond,
13135 tree exp, int nargs)
13137 struct expand_operand ops[MAX_RECOG_OPERANDS];
13140 /* The instruction should have a target operand, an operand for each
13141 argument, and an operand for COND. */
13142 gcc_assert (nargs + 2 == insn_data[(int) icode].n_generator_args);
13145 create_output_operand (&ops[opno++], NULL_RTX,
13146 insn_data[(int) icode].operand[0].mode);
13147 for (argno = 0; argno < nargs; argno++)
13148 mips_prepare_builtin_arg (&ops[opno++], exp, argno);
13149 create_integer_operand (&ops[opno++], (int) cond);
13150 return mips_expand_builtin_insn (icode, opno, ops, true);
13153 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
13154 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
13155 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
13156 suggests a good place to put the result. */
13159 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
13162 struct expand_operand ops[MAX_RECOG_OPERANDS];
13165 /* Map any target to operand 0. */
13168 create_output_operand (&ops[opno++], target, TYPE_MODE (TREE_TYPE (exp)));
13170 /* Map the arguments to the other operands. */
13171 gcc_assert (opno + call_expr_nargs (exp)
13172 == insn_data[icode].n_generator_args);
13173 for (argno = 0; argno < call_expr_nargs (exp); argno++)
13174 mips_prepare_builtin_arg (&ops[opno++], exp, argno);
13176 return mips_expand_builtin_insn (icode, opno, ops, has_target_p);
13179 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
13180 function; TYPE says which. EXP is the CALL_EXPR that calls the
13181 function, ICODE is the instruction that should be used to compare
13182 the first two arguments, and COND is the condition it should test.
13183 TARGET, if nonnull, suggests a good place to put the result. */
13186 mips_expand_builtin_movtf (enum mips_builtin_type type,
13187 enum insn_code icode, enum mips_fp_condition cond,
13188 rtx target, tree exp)
13190 struct expand_operand ops[4];
13193 cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp, 2);
13194 create_output_operand (&ops[0], target, TYPE_MODE (TREE_TYPE (exp)));
13195 if (type == MIPS_BUILTIN_MOVT)
13197 mips_prepare_builtin_arg (&ops[2], exp, 2);
13198 mips_prepare_builtin_arg (&ops[1], exp, 3);
13202 mips_prepare_builtin_arg (&ops[1], exp, 2);
13203 mips_prepare_builtin_arg (&ops[2], exp, 3);
13205 create_fixed_operand (&ops[3], cmp_result);
13206 return mips_expand_builtin_insn (CODE_FOR_mips_cond_move_tf_ps,
13210 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
13211 into TARGET otherwise. Return TARGET. */
13214 mips_builtin_branch_and_move (rtx condition, rtx target,
13215 rtx value_if_true, rtx value_if_false)
13217 rtx true_label, done_label;
13219 true_label = gen_label_rtx ();
13220 done_label = gen_label_rtx ();
13222 /* First assume that CONDITION is false. */
13223 mips_emit_move (target, value_if_false);
13225 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
13226 emit_jump_insn (gen_condjump (condition, true_label));
13227 emit_jump_insn (gen_jump (done_label));
13230 /* Fix TARGET if CONDITION is true. */
13231 emit_label (true_label);
13232 mips_emit_move (target, value_if_true);
13234 emit_label (done_label);
13238 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
13239 the CALL_EXPR that calls the function, ICODE is the code of the
13240 comparison instruction, and COND is the condition it should test.
13241 TARGET, if nonnull, suggests a good place to put the boolean result. */
13244 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
13245 enum insn_code icode, enum mips_fp_condition cond,
13246 rtx target, tree exp)
13248 rtx offset, condition, cmp_result;
13250 if (target == 0 || GET_MODE (target) != SImode)
13251 target = gen_reg_rtx (SImode);
13252 cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp,
13253 call_expr_nargs (exp));
13255 /* If the comparison sets more than one register, we define the result
13256 to be 0 if all registers are false and -1 if all registers are true.
13257 The value of the complete result is indeterminate otherwise. */
13258 switch (builtin_type)
13260 case MIPS_BUILTIN_CMP_ALL:
13261 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
13262 return mips_builtin_branch_and_move (condition, target,
13263 const0_rtx, const1_rtx);
13265 case MIPS_BUILTIN_CMP_UPPER:
13266 case MIPS_BUILTIN_CMP_LOWER:
13267 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
13268 condition = gen_single_cc (cmp_result, offset);
13269 return mips_builtin_branch_and_move (condition, target,
13270 const1_rtx, const0_rtx);
13273 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
13274 return mips_builtin_branch_and_move (condition, target,
13275 const1_rtx, const0_rtx);
13279 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
13280 if nonnull, suggests a good place to put the boolean result. */
13283 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
13285 rtx condition, cmp_result;
13288 if (target == 0 || GET_MODE (target) != SImode)
13289 target = gen_reg_rtx (SImode);
13291 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
13293 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
13298 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
13299 return mips_builtin_branch_and_move (condition, target,
13300 const1_rtx, const0_rtx);
13303 /* Implement TARGET_EXPAND_BUILTIN. */
13306 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
13307 enum machine_mode mode, int ignore)
13310 unsigned int fcode, avail;
13311 const struct mips_builtin_description *d;
13313 fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
13314 fcode = DECL_FUNCTION_CODE (fndecl);
13315 gcc_assert (fcode < ARRAY_SIZE (mips_builtins));
13316 d = &mips_builtins[fcode];
13317 avail = d->avail ();
13318 gcc_assert (avail != 0);
13321 error ("built-in function %qE not supported for MIPS16",
13322 DECL_NAME (fndecl));
13323 return ignore ? const0_rtx : CONST0_RTX (mode);
13325 switch (d->builtin_type)
13327 case MIPS_BUILTIN_DIRECT:
13328 return mips_expand_builtin_direct (d->icode, target, exp, true);
13330 case MIPS_BUILTIN_DIRECT_NO_TARGET:
13331 return mips_expand_builtin_direct (d->icode, target, exp, false);
13333 case MIPS_BUILTIN_MOVT:
13334 case MIPS_BUILTIN_MOVF:
13335 return mips_expand_builtin_movtf (d->builtin_type, d->icode,
13336 d->cond, target, exp);
13338 case MIPS_BUILTIN_CMP_ANY:
13339 case MIPS_BUILTIN_CMP_ALL:
13340 case MIPS_BUILTIN_CMP_UPPER:
13341 case MIPS_BUILTIN_CMP_LOWER:
13342 case MIPS_BUILTIN_CMP_SINGLE:
13343 return mips_expand_builtin_compare (d->builtin_type, d->icode,
13344 d->cond, target, exp);
13346 case MIPS_BUILTIN_BPOSGE32:
13347 return mips_expand_builtin_bposge (d->builtin_type, target);
13349 gcc_unreachable ();
13352 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
13353 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
13354 struct mips16_constant {
13355 struct mips16_constant *next;
13358 enum machine_mode mode;
13361 /* Information about an incomplete MIPS16 constant pool. FIRST is the
13362 first constant, HIGHEST_ADDRESS is the highest address that the first
13363 byte of the pool can have, and INSN_ADDRESS is the current instruction
13365 struct mips16_constant_pool {
13366 struct mips16_constant *first;
13367 int highest_address;
13371 /* Add constant VALUE to POOL and return its label. MODE is the
13372 value's mode (used for CONST_INTs, etc.). */
13375 mips16_add_constant (struct mips16_constant_pool *pool,
13376 rtx value, enum machine_mode mode)
13378 struct mips16_constant **p, *c;
13379 bool first_of_size_p;
13381 /* See whether the constant is already in the pool. If so, return the
13382 existing label, otherwise leave P pointing to the place where the
13383 constant should be added.
13385 Keep the pool sorted in increasing order of mode size so that we can
13386 reduce the number of alignments needed. */
13387 first_of_size_p = true;
13388 for (p = &pool->first; *p != 0; p = &(*p)->next)
13390 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
13391 return (*p)->label;
13392 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
13394 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
13395 first_of_size_p = false;
13398 /* In the worst case, the constant needed by the earliest instruction
13399 will end up at the end of the pool. The entire pool must then be
13400 accessible from that instruction.
13402 When adding the first constant, set the pool's highest address to
13403 the address of the first out-of-range byte. Adjust this address
13404 downwards each time a new constant is added. */
13405 if (pool->first == 0)
13406 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
13407 of the instruction with the lowest two bits clear. The base PC
13408 value for LDPC has the lowest three bits clear. Assume the worst
13409 case here; namely that the PC-relative instruction occupies the
13410 last 2 bytes in an aligned word. */
13411 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
13412 pool->highest_address -= GET_MODE_SIZE (mode);
13413 if (first_of_size_p)
13414 /* Take into account the worst possible padding due to alignment. */
13415 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
13417 /* Create a new entry. */
13418 c = XNEW (struct mips16_constant);
13421 c->label = gen_label_rtx ();
13428 /* Output constant VALUE after instruction INSN and return the last
13429 instruction emitted. MODE is the mode of the constant. */
13432 mips16_emit_constants_1 (enum machine_mode mode, rtx value, rtx insn)
13434 if (SCALAR_INT_MODE_P (mode) || ALL_SCALAR_FIXED_POINT_MODE_P (mode))
13436 rtx size = GEN_INT (GET_MODE_SIZE (mode));
13437 return emit_insn_after (gen_consttable_int (value, size), insn);
13440 if (SCALAR_FLOAT_MODE_P (mode))
13441 return emit_insn_after (gen_consttable_float (value), insn);
13443 if (VECTOR_MODE_P (mode))
13447 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
13448 insn = mips16_emit_constants_1 (GET_MODE_INNER (mode),
13449 CONST_VECTOR_ELT (value, i), insn);
13453 gcc_unreachable ();
13456 /* Dump out the constants in CONSTANTS after INSN. */
13459 mips16_emit_constants (struct mips16_constant *constants, rtx insn)
13461 struct mips16_constant *c, *next;
13465 for (c = constants; c != NULL; c = next)
13467 /* If necessary, increase the alignment of PC. */
13468 if (align < GET_MODE_SIZE (c->mode))
13470 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
13471 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
13473 align = GET_MODE_SIZE (c->mode);
13475 insn = emit_label_after (c->label, insn);
13476 insn = mips16_emit_constants_1 (c->mode, c->value, insn);
13482 emit_barrier_after (insn);
13485 /* Return the length of instruction INSN. */
13488 mips16_insn_length (rtx insn)
13492 rtx body = PATTERN (insn);
13493 if (GET_CODE (body) == ADDR_VEC)
13494 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
13495 if (GET_CODE (body) == ADDR_DIFF_VEC)
13496 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
13498 return get_attr_length (insn);
13501 /* If *X is a symbolic constant that refers to the constant pool, add
13502 the constant to POOL and rewrite *X to use the constant's label. */
13505 mips16_rewrite_pool_constant (struct mips16_constant_pool *pool, rtx *x)
13507 rtx base, offset, label;
13509 split_const (*x, &base, &offset);
13510 if (GET_CODE (base) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (base))
13512 label = mips16_add_constant (pool, get_pool_constant (base),
13513 get_pool_mode (base));
13514 base = gen_rtx_LABEL_REF (Pmode, label);
13515 *x = mips_unspec_address_offset (base, offset, SYMBOL_PC_RELATIVE);
13519 /* This structure is used to communicate with mips16_rewrite_pool_refs.
13520 INSN is the instruction we're rewriting and POOL points to the current
13522 struct mips16_rewrite_pool_refs_info {
13524 struct mips16_constant_pool *pool;
13527 /* Rewrite *X so that constant pool references refer to the constant's
13528 label instead. DATA points to a mips16_rewrite_pool_refs_info
13532 mips16_rewrite_pool_refs (rtx *x, void *data)
13534 struct mips16_rewrite_pool_refs_info *info =
13535 (struct mips16_rewrite_pool_refs_info *) data;
13537 if (force_to_mem_operand (*x, Pmode))
13539 rtx mem = force_const_mem (GET_MODE (*x), *x);
13540 validate_change (info->insn, x, mem, false);
13545 mips16_rewrite_pool_constant (info->pool, &XEXP (*x, 0));
13549 if (TARGET_MIPS16_TEXT_LOADS)
13550 mips16_rewrite_pool_constant (info->pool, x);
13552 return GET_CODE (*x) == CONST ? -1 : 0;
13555 /* Return whether CFG is used in mips_reorg. */
13558 mips_cfg_in_reorg (void)
13560 return (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
13561 || TARGET_RELAX_PIC_CALLS);
13564 /* Build MIPS16 constant pools. */
13567 mips16_lay_out_constants (void)
13569 struct mips16_constant_pool pool;
13570 struct mips16_rewrite_pool_refs_info info;
13573 if (!TARGET_MIPS16_PCREL_LOADS)
13576 if (mips_cfg_in_reorg ())
13577 split_all_insns ();
13579 split_all_insns_noflow ();
13581 memset (&pool, 0, sizeof (pool));
13582 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
13584 /* Rewrite constant pool references in INSN. */
13585 if (USEFUL_INSN_P (insn))
13589 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &info);
13592 pool.insn_address += mips16_insn_length (insn);
13594 if (pool.first != NULL)
13596 /* If there are no natural barriers between the first user of
13597 the pool and the highest acceptable address, we'll need to
13598 create a new instruction to jump around the constant pool.
13599 In the worst case, this instruction will be 4 bytes long.
13601 If it's too late to do this transformation after INSN,
13602 do it immediately before INSN. */
13603 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
13607 label = gen_label_rtx ();
13609 jump = emit_jump_insn_before (gen_jump (label), insn);
13610 JUMP_LABEL (jump) = label;
13611 LABEL_NUSES (label) = 1;
13612 barrier = emit_barrier_after (jump);
13614 emit_label_after (label, barrier);
13615 pool.insn_address += 4;
13618 /* See whether the constant pool is now out of range of the first
13619 user. If so, output the constants after the previous barrier.
13620 Note that any instructions between BARRIER and INSN (inclusive)
13621 will use negative offsets to refer to the pool. */
13622 if (pool.insn_address > pool.highest_address)
13624 mips16_emit_constants (pool.first, barrier);
13628 else if (BARRIER_P (insn))
13632 mips16_emit_constants (pool.first, get_last_insn ());
13635 /* Return true if it is worth r10k_simplify_address's while replacing
13636 an address with X. We are looking for constants, and for addresses
13637 at a known offset from the incoming stack pointer. */
13640 r10k_simplified_address_p (rtx x)
13642 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
13644 return x == virtual_incoming_args_rtx || CONSTANT_P (x);
13647 /* X is an expression that appears in INSN. Try to use the UD chains
13648 to simplify it, returning the simplified form on success and the
13649 original form otherwise. Replace the incoming value of $sp with
13650 virtual_incoming_args_rtx (which should never occur in X otherwise). */
13653 r10k_simplify_address (rtx x, rtx insn)
13655 rtx newx, op0, op1, set, def_insn, note;
13657 struct df_link *defs;
13662 op0 = r10k_simplify_address (XEXP (x, 0), insn);
13663 if (op0 != XEXP (x, 0))
13664 newx = simplify_gen_unary (GET_CODE (x), GET_MODE (x),
13665 op0, GET_MODE (XEXP (x, 0)));
13667 else if (BINARY_P (x))
13669 op0 = r10k_simplify_address (XEXP (x, 0), insn);
13670 op1 = r10k_simplify_address (XEXP (x, 1), insn);
13671 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
13672 newx = simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
13674 else if (GET_CODE (x) == LO_SUM)
13676 /* LO_SUMs can be offset from HIGHs, if we know they won't
13677 overflow. See mips_classify_address for the rationale behind
13679 op0 = r10k_simplify_address (XEXP (x, 0), insn);
13680 if (GET_CODE (op0) == HIGH)
13681 newx = XEXP (x, 1);
13683 else if (REG_P (x))
13685 /* Uses are recorded by regno_reg_rtx, not X itself. */
13686 use = df_find_use (insn, regno_reg_rtx[REGNO (x)]);
13688 defs = DF_REF_CHAIN (use);
13690 /* Require a single definition. */
13691 if (defs && defs->next == NULL)
13694 if (DF_REF_IS_ARTIFICIAL (def))
13696 /* Replace the incoming value of $sp with
13697 virtual_incoming_args_rtx. */
13698 if (x == stack_pointer_rtx
13699 && DF_REF_BB (def) == ENTRY_BLOCK_PTR)
13700 newx = virtual_incoming_args_rtx;
13702 else if (dominated_by_p (CDI_DOMINATORS, DF_REF_BB (use),
13705 /* Make sure that DEF_INSN is a single set of REG. */
13706 def_insn = DF_REF_INSN (def);
13707 if (NONJUMP_INSN_P (def_insn))
13709 set = single_set (def_insn);
13710 if (set && rtx_equal_p (SET_DEST (set), x))
13712 /* Prefer to use notes, since the def-use chains
13713 are often shorter. */
13714 note = find_reg_equal_equiv_note (def_insn);
13716 newx = XEXP (note, 0);
13718 newx = SET_SRC (set);
13719 newx = r10k_simplify_address (newx, def_insn);
13725 if (newx && r10k_simplified_address_p (newx))
13730 /* Return true if ADDRESS is known to be an uncached address
13731 on R10K systems. */
13734 r10k_uncached_address_p (unsigned HOST_WIDE_INT address)
13736 unsigned HOST_WIDE_INT upper;
13738 /* Check for KSEG1. */
13739 if (address + 0x60000000 < 0x20000000)
13742 /* Check for uncached XKPHYS addresses. */
13743 if (Pmode == DImode)
13745 upper = (address >> 40) & 0xf9ffff;
13746 if (upper == 0x900000 || upper == 0xb80000)
13752 /* Return true if we can prove that an access to address X in instruction
13753 INSN would be safe from R10K speculation. This X is a general
13754 expression; it might not be a legitimate address. */
13757 r10k_safe_address_p (rtx x, rtx insn)
13760 HOST_WIDE_INT offset_val;
13762 x = r10k_simplify_address (x, insn);
13764 /* Check for references to the stack frame. It doesn't really matter
13765 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
13766 allows us to assume that accesses to any part of the eventual frame
13767 is safe from speculation at any point in the function. */
13768 mips_split_plus (x, &base, &offset_val);
13769 if (base == virtual_incoming_args_rtx
13770 && offset_val >= -cfun->machine->frame.total_size
13771 && offset_val < cfun->machine->frame.args_size)
13774 /* Check for uncached addresses. */
13775 if (CONST_INT_P (x))
13776 return r10k_uncached_address_p (INTVAL (x));
13778 /* Check for accesses to a static object. */
13779 split_const (x, &base, &offset);
13780 return offset_within_block_p (base, INTVAL (offset));
13783 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
13784 an in-range access to an automatic variable, or to an object with
13785 a link-time-constant address. */
13788 r10k_safe_mem_expr_p (tree expr, rtx offset)
13790 if (expr == NULL_TREE
13791 || offset == NULL_RTX
13792 || !CONST_INT_P (offset)
13793 || INTVAL (offset) < 0
13794 || INTVAL (offset) >= int_size_in_bytes (TREE_TYPE (expr)))
13797 while (TREE_CODE (expr) == COMPONENT_REF)
13799 expr = TREE_OPERAND (expr, 0);
13800 if (expr == NULL_TREE)
13804 return DECL_P (expr);
13807 /* A for_each_rtx callback for which DATA points to the instruction
13808 containing *X. Stop the search if we find a MEM that is not safe
13809 from R10K speculation. */
13812 r10k_needs_protection_p_1 (rtx *loc, void *data)
13820 if (r10k_safe_mem_expr_p (MEM_EXPR (mem), MEM_OFFSET (mem)))
13823 if (r10k_safe_address_p (XEXP (mem, 0), (rtx) data))
13829 /* A note_stores callback for which DATA points to an instruction pointer.
13830 If *DATA is nonnull, make it null if it X contains a MEM that is not
13831 safe from R10K speculation. */
13834 r10k_needs_protection_p_store (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
13839 insn_ptr = (rtx *) data;
13840 if (*insn_ptr && for_each_rtx (&x, r10k_needs_protection_p_1, *insn_ptr))
13841 *insn_ptr = NULL_RTX;
13844 /* A for_each_rtx callback that iterates over the pattern of a CALL_INSN.
13845 Return nonzero if the call is not to a declared function. */
13848 r10k_needs_protection_p_call (rtx *loc, void *data ATTRIBUTE_UNUSED)
13857 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DECL (x))
13863 /* Return true if instruction INSN needs to be protected by an R10K
13867 r10k_needs_protection_p (rtx insn)
13870 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_call, NULL);
13872 if (mips_r10k_cache_barrier == R10K_CACHE_BARRIER_STORE)
13874 note_stores (PATTERN (insn), r10k_needs_protection_p_store, &insn);
13875 return insn == NULL_RTX;
13878 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_1, insn);
13881 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
13882 edge is unconditional. */
13885 r10k_protected_bb_p (basic_block bb, sbitmap protected_bbs)
13890 FOR_EACH_EDGE (e, ei, bb->preds)
13891 if (!single_succ_p (e->src)
13892 || !TEST_BIT (protected_bbs, e->src->index)
13893 || (e->flags & EDGE_COMPLEX) != 0)
13898 /* Implement -mr10k-cache-barrier= for the current function. */
13901 r10k_insert_cache_barriers (void)
13903 int *rev_post_order;
13906 sbitmap protected_bbs;
13907 rtx insn, end, unprotected_region;
13911 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
13915 /* Calculate dominators. */
13916 calculate_dominance_info (CDI_DOMINATORS);
13918 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
13919 X is protected by a cache barrier. */
13920 protected_bbs = sbitmap_alloc (last_basic_block);
13921 sbitmap_zero (protected_bbs);
13923 /* Iterate over the basic blocks in reverse post-order. */
13924 rev_post_order = XNEWVEC (int, last_basic_block);
13925 n = pre_and_rev_post_order_compute (NULL, rev_post_order, false);
13926 for (i = 0; i < n; i++)
13928 bb = BASIC_BLOCK (rev_post_order[i]);
13930 /* If this block is only reached by unconditional edges, and if the
13931 source of every edge is protected, the beginning of the block is
13933 if (r10k_protected_bb_p (bb, protected_bbs))
13934 unprotected_region = NULL_RTX;
13936 unprotected_region = pc_rtx;
13937 end = NEXT_INSN (BB_END (bb));
13939 /* UNPROTECTED_REGION is:
13941 - null if we are processing a protected region,
13942 - pc_rtx if we are processing an unprotected region but have
13943 not yet found the first instruction in it
13944 - the first instruction in an unprotected region otherwise. */
13945 for (insn = BB_HEAD (bb); insn != end; insn = NEXT_INSN (insn))
13947 if (unprotected_region && USEFUL_INSN_P (insn))
13949 if (recog_memoized (insn) == CODE_FOR_mips_cache)
13950 /* This CACHE instruction protects the following code. */
13951 unprotected_region = NULL_RTX;
13954 /* See if INSN is the first instruction in this
13955 unprotected region. */
13956 if (unprotected_region == pc_rtx)
13957 unprotected_region = insn;
13959 /* See if INSN needs to be protected. If so,
13960 we must insert a cache barrier somewhere between
13961 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
13962 clear which position is better performance-wise,
13963 but as a tie-breaker, we assume that it is better
13964 to allow delay slots to be back-filled where
13965 possible, and that it is better not to insert
13966 barriers in the middle of already-scheduled code.
13967 We therefore insert the barrier at the beginning
13969 if (r10k_needs_protection_p (insn))
13971 emit_insn_before (gen_r10k_cache_barrier (),
13972 unprotected_region);
13973 unprotected_region = NULL_RTX;
13979 /* The called function is not required to protect the exit path.
13980 The code that follows a call is therefore unprotected. */
13981 unprotected_region = pc_rtx;
13984 /* Record whether the end of this block is protected. */
13985 if (unprotected_region == NULL_RTX)
13986 SET_BIT (protected_bbs, bb->index);
13988 XDELETEVEC (rev_post_order);
13990 sbitmap_free (protected_bbs);
13992 free_dominance_info (CDI_DOMINATORS);
13995 /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX
13996 otherwise. If INSN has two call rtx, then store the second one in
14000 mips_call_expr_from_insn (rtx insn, rtx *second_call)
14005 if (!CALL_P (insn))
14008 x = PATTERN (insn);
14009 if (GET_CODE (x) == PARALLEL)
14011 /* Calls returning complex values have two CALL rtx. Look for the second
14012 one here, and return it via the SECOND_CALL arg. */
14013 x2 = XVECEXP (x, 0, 1);
14014 if (GET_CODE (x2) == SET)
14016 if (GET_CODE (x2) == CALL)
14019 x = XVECEXP (x, 0, 0);
14021 if (GET_CODE (x) == SET)
14023 gcc_assert (GET_CODE (x) == CALL);
14028 /* REG is set in DEF. See if the definition is one of the ways we load a
14029 register with a symbol address for a mips_use_pic_fn_addr_reg_p call.
14030 If it is, return the symbol reference of the function, otherwise return
14033 If RECURSE_P is true, use mips_find_pic_call_symbol to interpret
14034 the values of source registers, otherwise treat such registers as
14035 having an unknown value. */
14038 mips_pic_call_symbol_from_set (df_ref def, rtx reg, bool recurse_p)
14042 if (DF_REF_IS_ARTIFICIAL (def))
14045 def_insn = DF_REF_INSN (def);
14046 set = single_set (def_insn);
14047 if (set && rtx_equal_p (SET_DEST (set), reg))
14049 rtx note, src, symbol;
14051 /* First, look at REG_EQUAL/EQUIV notes. */
14052 note = find_reg_equal_equiv_note (def_insn);
14053 if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF)
14054 return XEXP (note, 0);
14056 /* For %call16 references we don't have REG_EQUAL. */
14057 src = SET_SRC (set);
14058 symbol = mips_strip_unspec_call (src);
14061 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
14065 /* Follow at most one simple register copy. Such copies are
14066 interesting in cases like:
14070 locally_binding_fn (...);
14075 locally_binding_fn (...);
14077 locally_binding_fn (...);
14079 where the load of locally_binding_fn can legitimately be
14080 hoisted or shared. However, we do not expect to see complex
14081 chains of copies, so a full worklist solution to the problem
14082 would probably be overkill. */
14083 if (recurse_p && REG_P (src))
14084 return mips_find_pic_call_symbol (def_insn, src, false);
14090 /* Find the definition of the use of REG in INSN. See if the definition
14091 is one of the ways we load a register with a symbol address for a
14092 mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference
14093 of the function, otherwise return NULL_RTX. RECURSE_P is as for
14094 mips_pic_call_symbol_from_set. */
14097 mips_find_pic_call_symbol (rtx insn, rtx reg, bool recurse_p)
14100 struct df_link *defs;
14103 use = df_find_use (insn, regno_reg_rtx[REGNO (reg)]);
14106 defs = DF_REF_CHAIN (use);
14109 symbol = mips_pic_call_symbol_from_set (defs->ref, reg, recurse_p);
14113 /* If we have more than one definition, they need to be identical. */
14114 for (defs = defs->next; defs; defs = defs->next)
14118 other = mips_pic_call_symbol_from_set (defs->ref, reg, recurse_p);
14119 if (!rtx_equal_p (symbol, other))
14126 /* Replace the args_size operand of the call expression CALL with the
14127 call-attribute UNSPEC and fill in SYMBOL as the function symbol. */
14130 mips_annotate_pic_call_expr (rtx call, rtx symbol)
14134 args_size = XEXP (call, 1);
14135 XEXP (call, 1) = gen_rtx_UNSPEC (GET_MODE (args_size),
14136 gen_rtvec (2, args_size, symbol),
14140 /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See
14141 if instead of the arg_size argument it contains the call attributes. If
14142 yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function
14143 symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is
14147 mips_get_pic_call_symbol (rtx *operands, int args_size_opno)
14149 rtx args_size, symbol;
14151 if (!TARGET_RELAX_PIC_CALLS || args_size_opno == -1)
14154 args_size = operands[args_size_opno];
14155 if (GET_CODE (args_size) != UNSPEC)
14157 gcc_assert (XINT (args_size, 1) == UNSPEC_CALL_ATTR);
14159 symbol = XVECEXP (args_size, 0, 1);
14160 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
14162 operands[args_size_opno] = symbol;
14166 /* Use DF to annotate PIC indirect calls with the function symbol they
14170 mips_annotate_pic_calls (void)
14176 FOR_BB_INSNS (bb, insn)
14178 rtx call, reg, symbol, second_call;
14181 call = mips_call_expr_from_insn (insn, &second_call);
14184 gcc_assert (MEM_P (XEXP (call, 0)));
14185 reg = XEXP (XEXP (call, 0), 0);
14189 symbol = mips_find_pic_call_symbol (insn, reg, true);
14192 mips_annotate_pic_call_expr (call, symbol);
14194 mips_annotate_pic_call_expr (second_call, symbol);
14199 /* A temporary variable used by for_each_rtx callbacks, etc. */
14200 static rtx mips_sim_insn;
14202 /* A structure representing the state of the processor pipeline.
14203 Used by the mips_sim_* family of functions. */
14205 /* The maximum number of instructions that can be issued in a cycle.
14206 (Caches mips_issue_rate.) */
14207 unsigned int issue_rate;
14209 /* The current simulation time. */
14212 /* How many more instructions can be issued in the current cycle. */
14213 unsigned int insns_left;
14215 /* LAST_SET[X].INSN is the last instruction to set register X.
14216 LAST_SET[X].TIME is the time at which that instruction was issued.
14217 INSN is null if no instruction has yet set register X. */
14221 } last_set[FIRST_PSEUDO_REGISTER];
14223 /* The pipeline's current DFA state. */
14227 /* Reset STATE to the initial simulation state. */
14230 mips_sim_reset (struct mips_sim *state)
14233 state->insns_left = state->issue_rate;
14234 memset (&state->last_set, 0, sizeof (state->last_set));
14235 state_reset (state->dfa_state);
14238 /* Initialize STATE before its first use. DFA_STATE points to an
14239 allocated but uninitialized DFA state. */
14242 mips_sim_init (struct mips_sim *state, state_t dfa_state)
14244 state->issue_rate = mips_issue_rate ();
14245 state->dfa_state = dfa_state;
14246 mips_sim_reset (state);
14249 /* Advance STATE by one clock cycle. */
14252 mips_sim_next_cycle (struct mips_sim *state)
14255 state->insns_left = state->issue_rate;
14256 state_transition (state->dfa_state, 0);
14259 /* Advance simulation state STATE until instruction INSN can read
14263 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
14265 unsigned int regno, end_regno;
14267 end_regno = END_REGNO (reg);
14268 for (regno = REGNO (reg); regno < end_regno; regno++)
14269 if (state->last_set[regno].insn != 0)
14273 t = (state->last_set[regno].time
14274 + insn_latency (state->last_set[regno].insn, insn));
14275 while (state->time < t)
14276 mips_sim_next_cycle (state);
14280 /* A for_each_rtx callback. If *X is a register, advance simulation state
14281 DATA until mips_sim_insn can read the register's value. */
14284 mips_sim_wait_regs_2 (rtx *x, void *data)
14287 mips_sim_wait_reg ((struct mips_sim *) data, mips_sim_insn, *x);
14291 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
14294 mips_sim_wait_regs_1 (rtx *x, void *data)
14296 for_each_rtx (x, mips_sim_wait_regs_2, data);
14299 /* Advance simulation state STATE until all of INSN's register
14300 dependencies are satisfied. */
14303 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
14305 mips_sim_insn = insn;
14306 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
14309 /* Advance simulation state STATE until the units required by
14310 instruction INSN are available. */
14313 mips_sim_wait_units (struct mips_sim *state, rtx insn)
14317 tmp_state = alloca (state_size ());
14318 while (state->insns_left == 0
14319 || (memcpy (tmp_state, state->dfa_state, state_size ()),
14320 state_transition (tmp_state, insn) >= 0))
14321 mips_sim_next_cycle (state);
14324 /* Advance simulation state STATE until INSN is ready to issue. */
14327 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
14329 mips_sim_wait_regs (state, insn);
14330 mips_sim_wait_units (state, insn);
14333 /* mips_sim_insn has just set X. Update the LAST_SET array
14334 in simulation state DATA. */
14337 mips_sim_record_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
14339 struct mips_sim *state;
14341 state = (struct mips_sim *) data;
14344 unsigned int regno, end_regno;
14346 end_regno = END_REGNO (x);
14347 for (regno = REGNO (x); regno < end_regno; regno++)
14349 state->last_set[regno].insn = mips_sim_insn;
14350 state->last_set[regno].time = state->time;
14355 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
14356 can issue immediately (i.e., that mips_sim_wait_insn has already
14360 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
14362 state_transition (state->dfa_state, insn);
14363 state->insns_left--;
14365 mips_sim_insn = insn;
14366 note_stores (PATTERN (insn), mips_sim_record_set, state);
14369 /* Simulate issuing a NOP in state STATE. */
14372 mips_sim_issue_nop (struct mips_sim *state)
14374 if (state->insns_left == 0)
14375 mips_sim_next_cycle (state);
14376 state->insns_left--;
14379 /* Update simulation state STATE so that it's ready to accept the instruction
14380 after INSN. INSN should be part of the main rtl chain, not a member of a
14384 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
14386 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
14388 mips_sim_issue_nop (state);
14390 switch (GET_CODE (SEQ_BEGIN (insn)))
14394 /* We can't predict the processor state after a call or label. */
14395 mips_sim_reset (state);
14399 /* The delay slots of branch likely instructions are only executed
14400 when the branch is taken. Therefore, if the caller has simulated
14401 the delay slot instruction, STATE does not really reflect the state
14402 of the pipeline for the instruction after the delay slot. Also,
14403 branch likely instructions tend to incur a penalty when not taken,
14404 so there will probably be an extra delay between the branch and
14405 the instruction after the delay slot. */
14406 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
14407 mips_sim_reset (state);
14415 /* The VR4130 pipeline issues aligned pairs of instructions together,
14416 but it stalls the second instruction if it depends on the first.
14417 In order to cut down the amount of logic required, this dependence
14418 check is not based on a full instruction decode. Instead, any non-SPECIAL
14419 instruction is assumed to modify the register specified by bits 20-16
14420 (which is usually the "rt" field).
14422 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
14423 input, so we can end up with a false dependence between the branch
14424 and its delay slot. If this situation occurs in instruction INSN,
14425 try to avoid it by swapping rs and rt. */
14428 vr4130_avoid_branch_rt_conflict (rtx insn)
14432 first = SEQ_BEGIN (insn);
14433 second = SEQ_END (insn);
14435 && NONJUMP_INSN_P (second)
14436 && GET_CODE (PATTERN (first)) == SET
14437 && GET_CODE (SET_DEST (PATTERN (first))) == PC
14438 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
14440 /* Check for the right kind of condition. */
14441 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
14442 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
14443 && REG_P (XEXP (cond, 0))
14444 && REG_P (XEXP (cond, 1))
14445 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
14446 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
14448 /* SECOND mentions the rt register but not the rs register. */
14449 rtx tmp = XEXP (cond, 0);
14450 XEXP (cond, 0) = XEXP (cond, 1);
14451 XEXP (cond, 1) = tmp;
14456 /* Implement -mvr4130-align. Go through each basic block and simulate the
14457 processor pipeline. If we find that a pair of instructions could execute
14458 in parallel, and the first of those instructions is not 8-byte aligned,
14459 insert a nop to make it aligned. */
14462 vr4130_align_insns (void)
14464 struct mips_sim state;
14465 rtx insn, subinsn, last, last2, next;
14470 /* LAST is the last instruction before INSN to have a nonzero length.
14471 LAST2 is the last such instruction before LAST. */
14475 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
14478 mips_sim_init (&state, alloca (state_size ()));
14479 for (insn = get_insns (); insn != 0; insn = next)
14481 unsigned int length;
14483 next = NEXT_INSN (insn);
14485 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
14486 This isn't really related to the alignment pass, but we do it on
14487 the fly to avoid a separate instruction walk. */
14488 vr4130_avoid_branch_rt_conflict (insn);
14490 if (USEFUL_INSN_P (insn))
14491 FOR_EACH_SUBINSN (subinsn, insn)
14493 mips_sim_wait_insn (&state, subinsn);
14495 /* If we want this instruction to issue in parallel with the
14496 previous one, make sure that the previous instruction is
14497 aligned. There are several reasons why this isn't worthwhile
14498 when the second instruction is a call:
14500 - Calls are less likely to be performance critical,
14501 - There's a good chance that the delay slot can execute
14502 in parallel with the call.
14503 - The return address would then be unaligned.
14505 In general, if we're going to insert a nop between instructions
14506 X and Y, it's better to insert it immediately after X. That
14507 way, if the nop makes Y aligned, it will also align any labels
14508 between X and Y. */
14509 if (state.insns_left != state.issue_rate
14510 && !CALL_P (subinsn))
14512 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
14514 /* SUBINSN is the first instruction in INSN and INSN is
14515 aligned. We want to align the previous instruction
14516 instead, so insert a nop between LAST2 and LAST.
14518 Note that LAST could be either a single instruction
14519 or a branch with a delay slot. In the latter case,
14520 LAST, like INSN, is already aligned, but the delay
14521 slot must have some extra delay that stops it from
14522 issuing at the same time as the branch. We therefore
14523 insert a nop before the branch in order to align its
14525 emit_insn_after (gen_nop (), last2);
14528 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
14530 /* SUBINSN is the delay slot of INSN, but INSN is
14531 currently unaligned. Insert a nop between
14532 LAST and INSN to align it. */
14533 emit_insn_after (gen_nop (), last);
14537 mips_sim_issue_insn (&state, subinsn);
14539 mips_sim_finish_insn (&state, insn);
14541 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
14542 length = get_attr_length (insn);
14545 /* If the instruction is an asm statement or multi-instruction
14546 mips.md patern, the length is only an estimate. Insert an
14547 8 byte alignment after it so that the following instructions
14548 can be handled correctly. */
14549 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
14550 && (recog_memoized (insn) < 0 || length >= 8))
14552 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
14553 next = NEXT_INSN (next);
14554 mips_sim_next_cycle (&state);
14557 else if (length & 4)
14558 aligned_p = !aligned_p;
14563 /* See whether INSN is an aligned label. */
14564 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
14570 /* This structure records that the current function has a LO_SUM
14571 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
14572 the largest offset applied to BASE by all such LO_SUMs. */
14573 struct mips_lo_sum_offset {
14575 HOST_WIDE_INT offset;
14578 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
14581 mips_hash_base (rtx base)
14583 int do_not_record_p;
14585 return hash_rtx (base, GET_MODE (base), &do_not_record_p, NULL, false);
14588 /* Hash-table callbacks for mips_lo_sum_offsets. */
14591 mips_lo_sum_offset_hash (const void *entry)
14593 return mips_hash_base (((const struct mips_lo_sum_offset *) entry)->base);
14597 mips_lo_sum_offset_eq (const void *entry, const void *value)
14599 return rtx_equal_p (((const struct mips_lo_sum_offset *) entry)->base,
14600 (const_rtx) value);
14603 /* Look up symbolic constant X in HTAB, which is a hash table of
14604 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
14605 paired with a recorded LO_SUM, otherwise record X in the table. */
14608 mips_lo_sum_offset_lookup (htab_t htab, rtx x, enum insert_option option)
14612 struct mips_lo_sum_offset *entry;
14614 /* Split X into a base and offset. */
14615 split_const (x, &base, &offset);
14616 if (UNSPEC_ADDRESS_P (base))
14617 base = UNSPEC_ADDRESS (base);
14619 /* Look up the base in the hash table. */
14620 slot = htab_find_slot_with_hash (htab, base, mips_hash_base (base), option);
14624 entry = (struct mips_lo_sum_offset *) *slot;
14625 if (option == INSERT)
14629 entry = XNEW (struct mips_lo_sum_offset);
14630 entry->base = base;
14631 entry->offset = INTVAL (offset);
14636 if (INTVAL (offset) > entry->offset)
14637 entry->offset = INTVAL (offset);
14640 return INTVAL (offset) <= entry->offset;
14643 /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table.
14644 Record every LO_SUM in *LOC. */
14647 mips_record_lo_sum (rtx *loc, void *data)
14649 if (GET_CODE (*loc) == LO_SUM)
14650 mips_lo_sum_offset_lookup ((htab_t) data, XEXP (*loc, 1), INSERT);
14654 /* Return true if INSN is a SET of an orphaned high-part relocation.
14655 HTAB is a hash table of mips_lo_sum_offsets that describes all the
14656 LO_SUMs in the current function. */
14659 mips_orphaned_high_part_p (htab_t htab, rtx insn)
14661 enum mips_symbol_type type;
14664 set = single_set (insn);
14667 /* Check for %his. */
14669 if (GET_CODE (x) == HIGH
14670 && absolute_symbolic_operand (XEXP (x, 0), VOIDmode))
14671 return !mips_lo_sum_offset_lookup (htab, XEXP (x, 0), NO_INSERT);
14673 /* Check for local %gots (and %got_pages, which is redundant but OK). */
14674 if (GET_CODE (x) == UNSPEC
14675 && XINT (x, 1) == UNSPEC_LOAD_GOT
14676 && mips_symbolic_constant_p (XVECEXP (x, 0, 1),
14677 SYMBOL_CONTEXT_LEA, &type)
14678 && type == SYMBOL_GOTOFF_PAGE)
14679 return !mips_lo_sum_offset_lookup (htab, XVECEXP (x, 0, 1), NO_INSERT);
14684 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
14685 INSN and a previous instruction, avoid it by inserting nops after
14688 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
14689 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
14690 before using the value of that register. *HILO_DELAY counts the
14691 number of instructions since the last hilo hazard (that is,
14692 the number of instructions since the last MFLO or MFHI).
14694 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
14695 for the next instruction.
14697 LO_REG is an rtx for the LO register, used in dependence checking. */
14700 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
14701 rtx *delayed_reg, rtx lo_reg)
14706 pattern = PATTERN (insn);
14708 /* Do not put the whole function in .set noreorder if it contains
14709 an asm statement. We don't know whether there will be hazards
14710 between the asm statement and the gcc-generated code. */
14711 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
14712 cfun->machine->all_noreorder_p = false;
14714 /* Ignore zero-length instructions (barriers and the like). */
14715 ninsns = get_attr_length (insn) / 4;
14719 /* Work out how many nops are needed. Note that we only care about
14720 registers that are explicitly mentioned in the instruction's pattern.
14721 It doesn't matter that calls use the argument registers or that they
14722 clobber hi and lo. */
14723 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
14724 nops = 2 - *hilo_delay;
14725 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
14730 /* Insert the nops between this instruction and the previous one.
14731 Each new nop takes us further from the last hilo hazard. */
14732 *hilo_delay += nops;
14734 emit_insn_after (gen_hazard_nop (), after);
14736 /* Set up the state for the next instruction. */
14737 *hilo_delay += ninsns;
14739 if (INSN_CODE (insn) >= 0)
14740 switch (get_attr_hazard (insn))
14750 set = single_set (insn);
14752 *delayed_reg = SET_DEST (set);
14757 /* Go through the instruction stream and insert nops where necessary.
14758 Also delete any high-part relocations whose partnering low parts
14759 are now all dead. See if the whole function can then be put into
14760 .set noreorder and .set nomacro. */
14763 mips_reorg_process_insns (void)
14765 rtx insn, last_insn, subinsn, next_insn, lo_reg, delayed_reg;
14769 /* Force all instructions to be split into their final form. */
14770 split_all_insns_noflow ();
14772 /* Recalculate instruction lengths without taking nops into account. */
14773 cfun->machine->ignore_hazard_length_p = true;
14774 shorten_branches (get_insns ());
14776 cfun->machine->all_noreorder_p = true;
14778 /* We don't track MIPS16 PC-relative offsets closely enough to make
14779 a good job of "set .noreorder" code in MIPS16 mode. */
14781 cfun->machine->all_noreorder_p = false;
14783 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
14784 if (!TARGET_EXPLICIT_RELOCS)
14785 cfun->machine->all_noreorder_p = false;
14787 /* Profiled functions can't be all noreorder because the profiler
14788 support uses assembler macros. */
14790 cfun->machine->all_noreorder_p = false;
14792 /* Code compiled with -mfix-vr4120 or -mfix-24k can't be all noreorder
14793 because we rely on the assembler to work around some errata. */
14794 if (TARGET_FIX_VR4120 || TARGET_FIX_24K)
14795 cfun->machine->all_noreorder_p = false;
14797 /* The same is true for -mfix-vr4130 if we might generate MFLO or
14798 MFHI instructions. Note that we avoid using MFLO and MFHI if
14799 the VR4130 MACC and DMACC instructions are available instead;
14800 see the *mfhilo_{si,di}_macc patterns. */
14801 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
14802 cfun->machine->all_noreorder_p = false;
14804 htab = htab_create (37, mips_lo_sum_offset_hash,
14805 mips_lo_sum_offset_eq, free);
14807 /* Make a first pass over the instructions, recording all the LO_SUMs. */
14808 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
14809 FOR_EACH_SUBINSN (subinsn, insn)
14810 if (USEFUL_INSN_P (subinsn))
14811 for_each_rtx (&PATTERN (subinsn), mips_record_lo_sum, htab);
14816 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
14818 /* Make a second pass over the instructions. Delete orphaned
14819 high-part relocations or turn them into NOPs. Avoid hazards
14820 by inserting NOPs. */
14821 for (insn = get_insns (); insn != 0; insn = next_insn)
14823 next_insn = NEXT_INSN (insn);
14824 if (USEFUL_INSN_P (insn))
14826 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
14828 /* If we find an orphaned high-part relocation in a delay
14829 slot, it's easier to turn that instruction into a NOP than
14830 to delete it. The delay slot will be a NOP either way. */
14831 FOR_EACH_SUBINSN (subinsn, insn)
14832 if (INSN_P (subinsn))
14834 if (mips_orphaned_high_part_p (htab, subinsn))
14836 PATTERN (subinsn) = gen_nop ();
14837 INSN_CODE (subinsn) = CODE_FOR_nop;
14839 mips_avoid_hazard (last_insn, subinsn, &hilo_delay,
14840 &delayed_reg, lo_reg);
14846 /* INSN is a single instruction. Delete it if it's an
14847 orphaned high-part relocation. */
14848 if (mips_orphaned_high_part_p (htab, insn))
14849 delete_insn (insn);
14850 /* Also delete cache barriers if the last instruction
14851 was an annulled branch. INSN will not be speculatively
14853 else if (recog_memoized (insn) == CODE_FOR_r10k_cache_barrier
14855 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn)))
14856 delete_insn (insn);
14859 mips_avoid_hazard (last_insn, insn, &hilo_delay,
14860 &delayed_reg, lo_reg);
14867 htab_delete (htab);
14870 /* If we are using a GOT, but have not decided to use a global pointer yet,
14871 see whether we need one to implement long branches. Convert the ghost
14872 global-pointer instructions into real ones if so. */
14875 mips_expand_ghost_gp_insns (void)
14880 /* Quick exit if we already know that we will or won't need a
14882 if (!TARGET_USE_GOT
14883 || cfun->machine->global_pointer == INVALID_REGNUM
14884 || mips_must_initialize_gp_p ())
14887 shorten_branches (get_insns ());
14889 /* Look for a branch that is longer than normal. The normal length for
14890 non-MIPS16 branches is 8, because the length includes the delay slot.
14891 It is 4 for MIPS16, because MIPS16 branches are extended instructions,
14892 but they have no delay slot. */
14893 normal_length = (TARGET_MIPS16 ? 4 : 8);
14894 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
14896 && USEFUL_INSN_P (insn)
14897 && get_attr_length (insn) > normal_length)
14900 if (insn == NULL_RTX)
14903 /* We've now established that we need $gp. */
14904 cfun->machine->must_initialize_gp_p = true;
14905 split_all_insns_noflow ();
14910 /* Subroutine of mips_reorg to manage passes that require DF. */
14913 mips_df_reorg (void)
14915 /* Create def-use chains. */
14916 df_set_flags (DF_EQ_NOTES);
14917 df_chain_add_problem (DF_UD_CHAIN);
14920 if (TARGET_RELAX_PIC_CALLS)
14921 mips_annotate_pic_calls ();
14923 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE)
14924 r10k_insert_cache_barriers ();
14926 df_finish_pass (false);
14929 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
14934 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during
14935 insn splitting in mips16_lay_out_constants, DF insn info is only kept up
14936 to date if the CFG is available. */
14937 if (mips_cfg_in_reorg ())
14938 compute_bb_for_insn ();
14939 mips16_lay_out_constants ();
14940 if (mips_cfg_in_reorg ())
14943 free_bb_for_insn ();
14946 if (optimize > 0 && flag_delayed_branch)
14947 dbr_schedule (get_insns ());
14948 mips_reorg_process_insns ();
14950 && TARGET_EXPLICIT_RELOCS
14952 && TARGET_VR4130_ALIGN)
14953 vr4130_align_insns ();
14954 if (mips_expand_ghost_gp_insns ())
14955 /* The expansion could invalidate some of the VR4130 alignment
14956 optimizations, but this should be an extremely rare case anyhow. */
14957 mips_reorg_process_insns ();
14960 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
14961 in order to avoid duplicating too much logic from elsewhere. */
14964 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
14965 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
14968 rtx this_rtx, temp1, temp2, insn, fnaddr;
14969 bool use_sibcall_p;
14971 /* Pretend to be a post-reload pass while generating rtl. */
14972 reload_completed = 1;
14974 /* Mark the end of the (empty) prologue. */
14975 emit_note (NOTE_INSN_PROLOGUE_END);
14977 /* Determine if we can use a sibcall to call FUNCTION directly. */
14978 fnaddr = XEXP (DECL_RTL (function), 0);
14979 use_sibcall_p = (mips_function_ok_for_sibcall (function, NULL)
14980 && const_call_insn_operand (fnaddr, Pmode));
14982 /* Determine if we need to load FNADDR from the GOT. */
14984 && (mips_got_symbol_type_p
14985 (mips_classify_symbol (fnaddr, SYMBOL_CONTEXT_LEA))))
14987 /* Pick a global pointer. Use a call-clobbered register if
14988 TARGET_CALL_SAVED_GP. */
14989 cfun->machine->global_pointer
14990 = TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM;
14991 cfun->machine->must_initialize_gp_p = true;
14992 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
14994 /* Set up the global pointer for n32 or n64 abicalls. */
14995 mips_emit_loadgp ();
14998 /* We need two temporary registers in some cases. */
14999 temp1 = gen_rtx_REG (Pmode, 2);
15000 temp2 = gen_rtx_REG (Pmode, 3);
15002 /* Find out which register contains the "this" pointer. */
15003 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
15004 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
15006 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST);
15008 /* Add DELTA to THIS_RTX. */
15011 rtx offset = GEN_INT (delta);
15012 if (!SMALL_OPERAND (delta))
15014 mips_emit_move (temp1, offset);
15017 emit_insn (gen_add3_insn (this_rtx, this_rtx, offset));
15020 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
15021 if (vcall_offset != 0)
15025 /* Set TEMP1 to *THIS_RTX. */
15026 mips_emit_move (temp1, gen_rtx_MEM (Pmode, this_rtx));
15028 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
15029 addr = mips_add_offset (temp2, temp1, vcall_offset);
15031 /* Load the offset and add it to THIS_RTX. */
15032 mips_emit_move (temp1, gen_rtx_MEM (Pmode, addr));
15033 emit_insn (gen_add3_insn (this_rtx, this_rtx, temp1));
15036 /* Jump to the target function. Use a sibcall if direct jumps are
15037 allowed, otherwise load the address into a register first. */
15040 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
15041 SIBLING_CALL_P (insn) = 1;
15045 /* This is messy. GAS treats "la $25,foo" as part of a call
15046 sequence and may allow a global "foo" to be lazily bound.
15047 The general move patterns therefore reject this combination.
15049 In this context, lazy binding would actually be OK
15050 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
15051 TARGET_CALL_SAVED_GP; see mips_load_call_address.
15052 We must therefore load the address via a temporary
15053 register if mips_dangerous_for_la25_p.
15055 If we jump to the temporary register rather than $25,
15056 the assembler can use the move insn to fill the jump's
15059 We can use the same technique for MIPS16 code, where $25
15060 is not a valid JR register. */
15061 if (TARGET_USE_PIC_FN_ADDR_REG
15063 && !mips_dangerous_for_la25_p (fnaddr))
15064 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
15065 mips_load_call_address (MIPS_CALL_SIBCALL, temp1, fnaddr);
15067 if (TARGET_USE_PIC_FN_ADDR_REG
15068 && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
15069 mips_emit_move (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
15070 emit_jump_insn (gen_indirect_jump (temp1));
15073 /* Run just enough of rest_of_compilation. This sequence was
15074 "borrowed" from alpha.c. */
15075 insn = get_insns ();
15076 insn_locators_alloc ();
15077 split_all_insns_noflow ();
15078 mips16_lay_out_constants ();
15079 shorten_branches (insn);
15080 final_start_function (insn, file, 1);
15081 final (insn, file, 1);
15082 final_end_function ();
15084 /* Clean up the vars set above. Note that final_end_function resets
15085 the global pointer for us. */
15086 reload_completed = 0;
15089 /* The last argument passed to mips_set_mips16_mode, or negative if the
15090 function hasn't been called yet.
15092 There are two copies of this information. One is saved and restored
15093 by the PCH process while the other is specific to this compiler
15094 invocation. The information calculated by mips_set_mips16_mode
15095 is invalid unless the two variables are the same. */
15096 static int was_mips16_p = -1;
15097 static GTY(()) int was_mips16_pch_p = -1;
15099 /* Set up the target-dependent global state so that it matches the
15100 current function's ISA mode. */
15103 mips_set_mips16_mode (int mips16_p)
15105 if (mips16_p == was_mips16_p
15106 && mips16_p == was_mips16_pch_p)
15109 /* Restore base settings of various flags. */
15110 target_flags = mips_base_target_flags;
15111 flag_schedule_insns = mips_base_schedule_insns;
15112 flag_reorder_blocks_and_partition = mips_base_reorder_blocks_and_partition;
15113 flag_move_loop_invariants = mips_base_move_loop_invariants;
15114 align_loops = mips_base_align_loops;
15115 align_jumps = mips_base_align_jumps;
15116 align_functions = mips_base_align_functions;
15120 /* Switch to MIPS16 mode. */
15121 target_flags |= MASK_MIPS16;
15123 /* Don't run the scheduler before reload, since it tends to
15124 increase register pressure. */
15125 flag_schedule_insns = 0;
15127 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
15128 the whole function to be in a single section. */
15129 flag_reorder_blocks_and_partition = 0;
15131 /* Don't move loop invariants, because it tends to increase
15132 register pressure. It also introduces an extra move in cases
15133 where the constant is the first operand in a two-operand binary
15134 instruction, or when it forms a register argument to a functon
15136 flag_move_loop_invariants = 0;
15138 target_flags |= MASK_EXPLICIT_RELOCS;
15140 /* Experiments suggest we get the best overall section-anchor
15141 results from using the range of an unextended LW or SW. Code
15142 that makes heavy use of byte or short accesses can do better
15143 with ranges of 0...31 and 0...63 respectively, but most code is
15144 sensitive to the range of LW and SW instead. */
15145 targetm.min_anchor_offset = 0;
15146 targetm.max_anchor_offset = 127;
15148 targetm.const_anchor = 0;
15150 /* MIPS16 has no BAL instruction. */
15151 target_flags &= ~MASK_RELAX_PIC_CALLS;
15153 if (flag_pic && !TARGET_OLDABI)
15154 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
15157 sorry ("MIPS16 -mxgot code");
15159 if (TARGET_HARD_FLOAT_ABI && !TARGET_OLDABI)
15160 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
15164 /* Switch to normal (non-MIPS16) mode. */
15165 target_flags &= ~MASK_MIPS16;
15167 /* Provide default values for align_* for 64-bit targets. */
15170 if (align_loops == 0)
15172 if (align_jumps == 0)
15174 if (align_functions == 0)
15175 align_functions = 8;
15178 targetm.min_anchor_offset = -32768;
15179 targetm.max_anchor_offset = 32767;
15181 targetm.const_anchor = 0x8000;
15184 /* (Re)initialize MIPS target internals for new ISA. */
15185 mips_init_relocs ();
15189 if (!mips16_globals)
15190 mips16_globals = save_target_globals ();
15192 restore_target_globals (mips16_globals);
15195 restore_target_globals (&default_target_globals);
15197 was_mips16_p = mips16_p;
15198 was_mips16_pch_p = mips16_p;
15201 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
15202 function should use the MIPS16 ISA and switch modes accordingly. */
15205 mips_set_current_function (tree fndecl)
15207 mips_set_mips16_mode (mips_use_mips16_mode_p (fndecl));
15210 /* Allocate a chunk of memory for per-function machine-dependent data. */
15212 static struct machine_function *
15213 mips_init_machine_status (void)
15215 return ggc_alloc_cleared_machine_function ();
15218 /* Return the processor associated with the given ISA level, or null
15219 if the ISA isn't valid. */
15221 static const struct mips_cpu_info *
15222 mips_cpu_info_from_isa (int isa)
15226 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
15227 if (mips_cpu_info_table[i].isa == isa)
15228 return mips_cpu_info_table + i;
15233 /* Return a mips_cpu_info entry determined by an option valued
15236 static const struct mips_cpu_info *
15237 mips_cpu_info_from_opt (int opt)
15241 case MIPS_ARCH_OPTION_FROM_ABI:
15242 /* 'from-abi' selects the most compatible architecture for the
15243 given ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit
15244 ABIs. For the EABIs, we have to decide whether we're using
15245 the 32-bit or 64-bit version. */
15246 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
15247 : ABI_NEEDS_64BIT_REGS ? 3
15248 : (TARGET_64BIT ? 3 : 1));
15250 case MIPS_ARCH_OPTION_NATIVE:
15251 gcc_unreachable ();
15254 return &mips_cpu_info_table[opt];
15258 /* Return a default mips_cpu_info entry, given that no -march= option
15259 was explicitly specified. */
15261 static const struct mips_cpu_info *
15262 mips_default_arch (void)
15264 #if defined (MIPS_CPU_STRING_DEFAULT)
15266 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
15267 if (strcmp (mips_cpu_info_table[i].name, MIPS_CPU_STRING_DEFAULT) == 0)
15268 return mips_cpu_info_table + i;
15269 gcc_unreachable ();
15270 #elif defined (MIPS_ISA_DEFAULT)
15271 return mips_cpu_info_from_isa (MIPS_ISA_DEFAULT);
15273 /* 'from-abi' makes a good default: you get whatever the ABI
15275 return mips_cpu_info_from_opt (MIPS_ARCH_OPTION_FROM_ABI);
15279 /* Set up globals to generate code for the ISA or processor
15280 described by INFO. */
15283 mips_set_architecture (const struct mips_cpu_info *info)
15287 mips_arch_info = info;
15288 mips_arch = info->cpu;
15289 mips_isa = info->isa;
15293 /* Likewise for tuning. */
15296 mips_set_tune (const struct mips_cpu_info *info)
15300 mips_tune_info = info;
15301 mips_tune = info->cpu;
15305 /* Implement TARGET_HANDLE_OPTION. */
15308 mips_handle_option (struct gcc_options *opts,
15309 struct gcc_options *opts_set ATTRIBUTE_UNUSED,
15310 const struct cl_decoded_option *decoded,
15311 location_t loc ATTRIBUTE_UNUSED)
15313 size_t code = decoded->opt_index;
15317 case OPT_mno_flush_func:
15318 opts->x_mips_cache_flush_func = NULL;
15326 /* Implement TARGET_OPTION_OVERRIDE. */
15329 mips_option_override (void)
15331 int i, start, regno, mode;
15333 if (global_options_set.x_mips_isa_option)
15334 mips_isa_option_info = &mips_cpu_info_table[mips_isa_option];
15336 /* Process flags as though we were generating non-MIPS16 code. */
15337 mips_base_mips16 = TARGET_MIPS16;
15338 target_flags &= ~MASK_MIPS16;
15340 #ifdef SUBTARGET_OVERRIDE_OPTIONS
15341 SUBTARGET_OVERRIDE_OPTIONS;
15344 /* -mno-float overrides -mhard-float and -msoft-float. */
15345 if (TARGET_NO_FLOAT)
15347 target_flags |= MASK_SOFT_FLOAT_ABI;
15348 target_flags_explicit |= MASK_SOFT_FLOAT_ABI;
15351 if (TARGET_FLIP_MIPS16)
15352 TARGET_INTERLINK_MIPS16 = 1;
15354 /* Set the small data limit. */
15355 mips_small_data_threshold = (global_options_set.x_g_switch_value
15357 : MIPS_DEFAULT_GVALUE);
15359 /* The following code determines the architecture and register size.
15360 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
15361 The GAS and GCC code should be kept in sync as much as possible. */
15363 if (global_options_set.x_mips_arch_option)
15364 mips_set_architecture (mips_cpu_info_from_opt (mips_arch_option));
15366 if (mips_isa_option_info != 0)
15368 if (mips_arch_info == 0)
15369 mips_set_architecture (mips_isa_option_info);
15370 else if (mips_arch_info->isa != mips_isa_option_info->isa)
15371 error ("%<-%s%> conflicts with the other architecture options, "
15372 "which specify a %s processor",
15373 mips_isa_option_info->name,
15374 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
15377 if (mips_arch_info == 0)
15378 mips_set_architecture (mips_default_arch ());
15380 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
15381 error ("%<-march=%s%> is not compatible with the selected ABI",
15382 mips_arch_info->name);
15384 /* Optimize for mips_arch, unless -mtune selects a different processor. */
15385 if (global_options_set.x_mips_tune_option)
15386 mips_set_tune (mips_cpu_info_from_opt (mips_tune_option));
15388 if (mips_tune_info == 0)
15389 mips_set_tune (mips_arch_info);
15391 if ((target_flags_explicit & MASK_64BIT) != 0)
15393 /* The user specified the size of the integer registers. Make sure
15394 it agrees with the ABI and ISA. */
15395 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
15396 error ("%<-mgp64%> used with a 32-bit processor");
15397 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
15398 error ("%<-mgp32%> used with a 64-bit ABI");
15399 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
15400 error ("%<-mgp64%> used with a 32-bit ABI");
15404 /* Infer the integer register size from the ABI and processor.
15405 Restrict ourselves to 32-bit registers if that's all the
15406 processor has, or if the ABI cannot handle 64-bit registers. */
15407 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
15408 target_flags &= ~MASK_64BIT;
15410 target_flags |= MASK_64BIT;
15413 if ((target_flags_explicit & MASK_FLOAT64) != 0)
15415 if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
15416 error ("unsupported combination: %s", "-mfp64 -msingle-float");
15417 else if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
15418 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
15419 else if (!TARGET_64BIT && TARGET_FLOAT64)
15421 if (!ISA_HAS_MXHC1)
15422 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
15423 " the target supports the mfhc1 and mthc1 instructions");
15424 else if (mips_abi != ABI_32)
15425 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
15431 /* -msingle-float selects 32-bit float registers. Otherwise the
15432 float registers should be the same size as the integer ones. */
15433 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
15434 target_flags |= MASK_FLOAT64;
15436 target_flags &= ~MASK_FLOAT64;
15439 /* End of code shared with GAS. */
15441 /* If no -mlong* option was given, infer it from the other options. */
15442 if ((target_flags_explicit & MASK_LONG64) == 0)
15444 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
15445 target_flags |= MASK_LONG64;
15447 target_flags &= ~MASK_LONG64;
15450 if (!TARGET_OLDABI)
15451 flag_pcc_struct_return = 0;
15453 /* Decide which rtx_costs structure to use. */
15455 mips_cost = &mips_rtx_cost_optimize_size;
15457 mips_cost = &mips_rtx_cost_data[mips_tune];
15459 /* If the user hasn't specified a branch cost, use the processor's
15461 if (mips_branch_cost == 0)
15462 mips_branch_cost = mips_cost->branch_cost;
15464 /* If neither -mbranch-likely nor -mno-branch-likely was given
15465 on the command line, set MASK_BRANCHLIKELY based on the target
15466 architecture and tuning flags. Annulled delay slots are a
15467 size win, so we only consider the processor-specific tuning
15468 for !optimize_size. */
15469 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
15471 if (ISA_HAS_BRANCHLIKELY
15473 || (mips_tune_info->tune_flags & PTF_AVOID_BRANCHLIKELY) == 0))
15474 target_flags |= MASK_BRANCHLIKELY;
15476 target_flags &= ~MASK_BRANCHLIKELY;
15478 else if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
15479 warning (0, "the %qs architecture does not support branch-likely"
15480 " instructions", mips_arch_info->name);
15482 /* The effect of -mabicalls isn't defined for the EABI. */
15483 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
15485 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
15486 target_flags &= ~MASK_ABICALLS;
15489 if (TARGET_ABICALLS_PIC2)
15490 /* We need to set flag_pic for executables as well as DSOs
15491 because we may reference symbols that are not defined in
15492 the final executable. (MIPS does not use things like
15493 copy relocs, for example.)
15495 There is a body of code that uses __PIC__ to distinguish
15496 between -mabicalls and -mno-abicalls code. The non-__PIC__
15497 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
15498 long as any indirect jumps use $25. */
15501 /* -mvr4130-align is a "speed over size" optimization: it usually produces
15502 faster code, but at the expense of more nops. Enable it at -O3 and
15504 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
15505 target_flags |= MASK_VR4130_ALIGN;
15507 /* Prefer a call to memcpy over inline code when optimizing for size,
15508 though see MOVE_RATIO in mips.h. */
15509 if (optimize_size && (target_flags_explicit & MASK_MEMCPY) == 0)
15510 target_flags |= MASK_MEMCPY;
15512 /* If we have a nonzero small-data limit, check that the -mgpopt
15513 setting is consistent with the other target flags. */
15514 if (mips_small_data_threshold > 0)
15518 if (!TARGET_EXPLICIT_RELOCS)
15519 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
15521 TARGET_LOCAL_SDATA = false;
15522 TARGET_EXTERN_SDATA = false;
15526 if (TARGET_VXWORKS_RTP)
15527 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
15529 if (TARGET_ABICALLS)
15530 warning (0, "cannot use small-data accesses for %qs",
15535 #ifdef MIPS_TFMODE_FORMAT
15536 REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
15539 /* Make sure that the user didn't turn off paired single support when
15540 MIPS-3D support is requested. */
15542 && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
15543 && !TARGET_PAIRED_SINGLE_FLOAT)
15544 error ("%<-mips3d%> requires %<-mpaired-single%>");
15546 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
15548 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
15550 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
15551 and TARGET_HARD_FLOAT_ABI are both true. */
15552 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT_ABI))
15553 error ("%qs must be used with %qs",
15554 TARGET_MIPS3D ? "-mips3d" : "-mpaired-single",
15555 TARGET_HARD_FLOAT_ABI ? "-mfp64" : "-mhard-float");
15557 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
15559 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_HAS_PAIRED_SINGLE)
15560 warning (0, "the %qs architecture does not support paired-single"
15561 " instructions", mips_arch_info->name);
15563 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
15564 && !TARGET_CACHE_BUILTIN)
15566 error ("%qs requires a target that provides the %qs instruction",
15567 "-mr10k-cache-barrier", "cache");
15568 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE;
15571 /* If TARGET_DSPR2, enable MASK_DSP. */
15573 target_flags |= MASK_DSP;
15575 /* .eh_frame addresses should be the same width as a C pointer.
15576 Most MIPS ABIs support only one pointer size, so the assembler
15577 will usually know exactly how big an .eh_frame address is.
15579 Unfortunately, this is not true of the 64-bit EABI. The ABI was
15580 originally defined to use 64-bit pointers (i.e. it is LP64), and
15581 this is still the default mode. However, we also support an n32-like
15582 ILP32 mode, which is selected by -mlong32. The problem is that the
15583 assembler has traditionally not had an -mlong option, so it has
15584 traditionally not known whether we're using the ILP32 or LP64 form.
15586 As it happens, gas versions up to and including 2.19 use _32-bit_
15587 addresses for EABI64 .cfi_* directives. This is wrong for the
15588 default LP64 mode, so we can't use the directives by default.
15589 Moreover, since gas's current behavior is at odds with gcc's
15590 default behavior, it seems unwise to rely on future versions
15591 of gas behaving the same way. We therefore avoid using .cfi
15592 directives for -mlong32 as well. */
15593 if (mips_abi == ABI_EABI && TARGET_64BIT)
15594 flag_dwarf2_cfi_asm = 0;
15596 /* .cfi_* directives generate a read-only section, so fall back on
15597 manual .eh_frame creation if we need the section to be writable. */
15598 if (TARGET_WRITABLE_EH_FRAME)
15599 flag_dwarf2_cfi_asm = 0;
15601 mips_init_print_operand_punct ();
15603 /* Set up array to map GCC register number to debug register number.
15604 Ignore the special purpose register numbers. */
15606 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
15608 mips_dbx_regno[i] = INVALID_REGNUM;
15609 if (GP_REG_P (i) || FP_REG_P (i) || ALL_COP_REG_P (i))
15610 mips_dwarf_regno[i] = i;
15612 mips_dwarf_regno[i] = INVALID_REGNUM;
15615 start = GP_DBX_FIRST - GP_REG_FIRST;
15616 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
15617 mips_dbx_regno[i] = i + start;
15619 start = FP_DBX_FIRST - FP_REG_FIRST;
15620 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
15621 mips_dbx_regno[i] = i + start;
15623 /* Accumulator debug registers use big-endian ordering. */
15624 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
15625 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
15626 mips_dwarf_regno[HI_REGNUM] = MD_REG_FIRST + 0;
15627 mips_dwarf_regno[LO_REGNUM] = MD_REG_FIRST + 1;
15628 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
15630 mips_dwarf_regno[i + TARGET_LITTLE_ENDIAN] = i;
15631 mips_dwarf_regno[i + TARGET_BIG_ENDIAN] = i + 1;
15634 /* Set up mips_hard_regno_mode_ok. */
15635 for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
15636 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
15637 mips_hard_regno_mode_ok[mode][regno]
15638 = mips_hard_regno_mode_ok_p (regno, (enum machine_mode) mode);
15640 /* Function to allocate machine-dependent function status. */
15641 init_machine_status = &mips_init_machine_status;
15643 /* Default to working around R4000 errata only if the processor
15644 was selected explicitly. */
15645 if ((target_flags_explicit & MASK_FIX_R4000) == 0
15646 && strcmp (mips_arch_info->name, "r4000") == 0)
15647 target_flags |= MASK_FIX_R4000;
15649 /* Default to working around R4400 errata only if the processor
15650 was selected explicitly. */
15651 if ((target_flags_explicit & MASK_FIX_R4400) == 0
15652 && strcmp (mips_arch_info->name, "r4400") == 0)
15653 target_flags |= MASK_FIX_R4400;
15655 /* Default to working around R10000 errata only if the processor
15656 was selected explicitly. */
15657 if ((target_flags_explicit & MASK_FIX_R10000) == 0
15658 && strcmp (mips_arch_info->name, "r10000") == 0)
15659 target_flags |= MASK_FIX_R10000;
15661 /* Make sure that branch-likely instructions available when using
15662 -mfix-r10000. The instructions are not available if either:
15664 1. -mno-branch-likely was passed.
15665 2. The selected ISA does not support branch-likely and
15666 the command line does not include -mbranch-likely. */
15667 if (TARGET_FIX_R10000
15668 && ((target_flags_explicit & MASK_BRANCHLIKELY) == 0
15669 ? !ISA_HAS_BRANCHLIKELY
15670 : !TARGET_BRANCHLIKELY))
15671 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
15673 if (TARGET_SYNCI && !ISA_HAS_SYNCI)
15675 warning (0, "the %qs architecture does not support the synci "
15676 "instruction", mips_arch_info->name);
15677 target_flags &= ~MASK_SYNCI;
15680 /* Only optimize PIC indirect calls if they are actually required. */
15681 if (!TARGET_USE_GOT || !TARGET_EXPLICIT_RELOCS)
15682 target_flags &= ~MASK_RELAX_PIC_CALLS;
15684 /* Save base state of options. */
15685 mips_base_target_flags = target_flags;
15686 mips_base_schedule_insns = flag_schedule_insns;
15687 mips_base_reorder_blocks_and_partition = flag_reorder_blocks_and_partition;
15688 mips_base_move_loop_invariants = flag_move_loop_invariants;
15689 mips_base_align_loops = align_loops;
15690 mips_base_align_jumps = align_jumps;
15691 mips_base_align_functions = align_functions;
15693 /* Now select the ISA mode.
15695 Do all CPP-sensitive stuff in non-MIPS16 mode; we'll switch to
15696 MIPS16 mode afterwards if need be. */
15697 mips_set_mips16_mode (false);
15700 /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
15701 static const struct default_options mips_option_optimization_table[] =
15703 { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
15704 { OPT_LEVELS_NONE, 0, NULL, 0 }
15707 /* Swap the register information for registers I and I + 1, which
15708 currently have the wrong endianness. Note that the registers'
15709 fixedness and call-clobberedness might have been set on the
15713 mips_swap_registers (unsigned int i)
15718 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
15719 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
15721 SWAP_INT (fixed_regs[i], fixed_regs[i + 1]);
15722 SWAP_INT (call_used_regs[i], call_used_regs[i + 1]);
15723 SWAP_INT (call_really_used_regs[i], call_really_used_regs[i + 1]);
15724 SWAP_STRING (reg_names[i], reg_names[i + 1]);
15730 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
15733 mips_conditional_register_usage (void)
15738 /* These DSP control register fields are global. */
15739 global_regs[CCDSP_PO_REGNUM] = 1;
15740 global_regs[CCDSP_SC_REGNUM] = 1;
15746 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
15747 fixed_regs[regno] = call_used_regs[regno] = 1;
15749 if (!TARGET_HARD_FLOAT)
15753 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
15754 fixed_regs[regno] = call_used_regs[regno] = 1;
15755 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
15756 fixed_regs[regno] = call_used_regs[regno] = 1;
15758 else if (! ISA_HAS_8CC)
15762 /* We only have a single condition-code register. We implement
15763 this by fixing all the condition-code registers and generating
15764 RTL that refers directly to ST_REG_FIRST. */
15765 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
15766 fixed_regs[regno] = call_used_regs[regno] = 1;
15768 /* In MIPS16 mode, we permit the $t temporary registers to be used
15769 for reload. We prohibit the unused $s registers, since they
15770 are call-saved, and saving them via a MIPS16 register would
15771 probably waste more time than just reloading the value. */
15774 fixed_regs[18] = call_used_regs[18] = 1;
15775 fixed_regs[19] = call_used_regs[19] = 1;
15776 fixed_regs[20] = call_used_regs[20] = 1;
15777 fixed_regs[21] = call_used_regs[21] = 1;
15778 fixed_regs[22] = call_used_regs[22] = 1;
15779 fixed_regs[23] = call_used_regs[23] = 1;
15780 fixed_regs[26] = call_used_regs[26] = 1;
15781 fixed_regs[27] = call_used_regs[27] = 1;
15782 fixed_regs[30] = call_used_regs[30] = 1;
15784 /* $f20-$f23 are call-clobbered for n64. */
15785 if (mips_abi == ABI_64)
15788 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
15789 call_really_used_regs[regno] = call_used_regs[regno] = 1;
15791 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
15793 if (mips_abi == ABI_N32)
15796 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
15797 call_really_used_regs[regno] = call_used_regs[regno] = 1;
15799 /* Make sure that double-register accumulator values are correctly
15800 ordered for the current endianness. */
15801 if (TARGET_LITTLE_ENDIAN)
15803 unsigned int regno;
15805 mips_swap_registers (MD_REG_FIRST);
15806 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno += 2)
15807 mips_swap_registers (regno);
15811 /* Initialize vector TARGET to VALS. */
15814 mips_expand_vector_init (rtx target, rtx vals)
15816 enum machine_mode mode;
15817 enum machine_mode inner;
15818 unsigned int i, n_elts;
15821 mode = GET_MODE (target);
15822 inner = GET_MODE_INNER (mode);
15823 n_elts = GET_MODE_NUNITS (mode);
15825 gcc_assert (VECTOR_MODE_P (mode));
15827 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
15828 for (i = 0; i < n_elts; i++)
15829 emit_move_insn (adjust_address_nv (mem, inner, i * GET_MODE_SIZE (inner)),
15830 XVECEXP (vals, 0, i));
15832 emit_move_insn (target, mem);
15835 /* When generating MIPS16 code, we want to allocate $24 (T_REG) before
15836 other registers for instructions for which it is possible. This
15837 encourages the compiler to use CMP in cases where an XOR would
15838 require some register shuffling. */
15841 mips_order_regs_for_local_alloc (void)
15845 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
15846 reg_alloc_order[i] = i;
15850 /* It really doesn't matter where we put register 0, since it is
15851 a fixed register anyhow. */
15852 reg_alloc_order[0] = 24;
15853 reg_alloc_order[24] = 0;
15857 /* Implement EH_USES. */
15860 mips_eh_uses (unsigned int regno)
15862 if (reload_completed && !TARGET_ABSOLUTE_JUMPS)
15864 /* We need to force certain registers to be live in order to handle
15865 PIC long branches correctly. See mips_must_initialize_gp_p for
15867 if (mips_cfun_has_cprestore_slot_p ())
15869 if (regno == CPRESTORE_SLOT_REGNUM)
15874 if (cfun->machine->global_pointer == regno)
15882 /* Implement EPILOGUE_USES. */
15885 mips_epilogue_uses (unsigned int regno)
15887 /* Say that the epilogue uses the return address register. Note that
15888 in the case of sibcalls, the values "used by the epilogue" are
15889 considered live at the start of the called function. */
15890 if (regno == RETURN_ADDR_REGNUM)
15893 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
15894 See the comment above load_call<mode> for details. */
15895 if (TARGET_USE_GOT && (regno) == GOT_VERSION_REGNUM)
15898 /* An interrupt handler must preserve some registers that are
15899 ordinarily call-clobbered. */
15900 if (cfun->machine->interrupt_handler_p
15901 && mips_interrupt_extra_call_saved_reg_p (regno))
15907 /* A for_each_rtx callback. Stop the search if *X is an AT register. */
15910 mips_at_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
15912 return REG_P (*x) && REGNO (*x) == AT_REGNUM;
15915 /* Return true if INSN needs to be wrapped in ".set noat".
15916 INSN has NOPERANDS operands, stored in OPVEC. */
15919 mips_need_noat_wrapper_p (rtx insn, rtx *opvec, int noperands)
15923 if (recog_memoized (insn) >= 0)
15924 for (i = 0; i < noperands; i++)
15925 if (for_each_rtx (&opvec[i], mips_at_reg_p, NULL))
15930 /* Implement FINAL_PRESCAN_INSN. */
15933 mips_final_prescan_insn (rtx insn, rtx *opvec, int noperands)
15935 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
15936 mips_push_asm_switch (&mips_noat);
15939 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */
15942 mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED, rtx insn,
15943 rtx *opvec, int noperands)
15945 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
15946 mips_pop_asm_switch (&mips_noat);
15949 /* Return the function that is used to expand the <u>mulsidi3 pattern.
15950 EXT_CODE is the code of the extension used. Return NULL if widening
15951 multiplication shouldn't be used. */
15954 mips_mulsidi3_gen_fn (enum rtx_code ext_code)
15958 signed_p = ext_code == SIGN_EXTEND;
15961 /* Don't use widening multiplication with MULT when we have DMUL. Even
15962 with the extension of its input operands DMUL is faster. Note that
15963 the extension is not needed for signed multiplication. In order to
15964 ensure that we always remove the redundant sign-extension in this
15965 case we still expand mulsidi3 for DMUL. */
15967 return signed_p ? gen_mulsidi3_64bit_dmul : NULL;
15968 if (TARGET_FIX_R4000)
15970 return signed_p ? gen_mulsidi3_64bit : gen_umulsidi3_64bit;
15974 if (TARGET_FIX_R4000 && !ISA_HAS_DSP)
15975 return signed_p ? gen_mulsidi3_32bit_r4000 : gen_umulsidi3_32bit_r4000;
15976 return signed_p ? gen_mulsidi3_32bit : gen_umulsidi3_32bit;
15980 /* Return the size in bytes of the trampoline code, padded to
15981 TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target
15982 function address immediately follow. */
15985 mips_trampoline_code_size (void)
15987 if (TARGET_USE_PIC_FN_ADDR_REG)
15989 else if (ptr_mode == DImode)
15991 else if (ISA_HAS_LOAD_DELAY)
15997 /* Implement TARGET_TRAMPOLINE_INIT. */
16000 mips_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
16002 rtx addr, end_addr, high, low, opcode, mem;
16005 HOST_WIDE_INT end_addr_offset, static_chain_offset, target_function_offset;
16007 /* Work out the offsets of the pointers from the start of the
16008 trampoline code. */
16009 end_addr_offset = mips_trampoline_code_size ();
16010 static_chain_offset = end_addr_offset;
16011 target_function_offset = static_chain_offset + GET_MODE_SIZE (ptr_mode);
16013 /* Get pointers to the beginning and end of the code block. */
16014 addr = force_reg (Pmode, XEXP (m_tramp, 0));
16015 end_addr = mips_force_binary (Pmode, PLUS, addr, GEN_INT (end_addr_offset));
16017 #define OP(X) gen_int_mode (X, SImode)
16019 /* Build up the code in TRAMPOLINE. */
16021 if (TARGET_USE_PIC_FN_ADDR_REG)
16023 /* $25 contains the address of the trampoline. Emit code of the form:
16025 l[wd] $1, target_function_offset($25)
16026 l[wd] $static_chain, static_chain_offset($25)
16029 trampoline[i++] = OP (MIPS_LOAD_PTR (AT_REGNUM,
16030 target_function_offset,
16031 PIC_FUNCTION_ADDR_REGNUM));
16032 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
16033 static_chain_offset,
16034 PIC_FUNCTION_ADDR_REGNUM));
16035 trampoline[i++] = OP (MIPS_JR (AT_REGNUM));
16036 trampoline[i++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM, AT_REGNUM));
16038 else if (ptr_mode == DImode)
16040 /* It's too cumbersome to create the full 64-bit address, so let's
16046 1: l[wd] $25, target_function_offset - 12($31)
16047 l[wd] $static_chain, static_chain_offset - 12($31)
16051 where 12 is the offset of "1:" from the start of the code block. */
16052 trampoline[i++] = OP (MIPS_MOVE (AT_REGNUM, RETURN_ADDR_REGNUM));
16053 trampoline[i++] = OP (MIPS_BAL (1));
16054 trampoline[i++] = OP (MIPS_NOP);
16055 trampoline[i++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
16056 target_function_offset - 12,
16057 RETURN_ADDR_REGNUM));
16058 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
16059 static_chain_offset - 12,
16060 RETURN_ADDR_REGNUM));
16061 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
16062 trampoline[i++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM, AT_REGNUM));
16066 /* If the target has load delays, emit:
16068 lui $1, %hi(end_addr)
16069 lw $25, %lo(end_addr + ...)($1)
16070 lw $static_chain, %lo(end_addr + ...)($1)
16076 lui $1, %hi(end_addr)
16077 lw $25, %lo(end_addr + ...)($1)
16079 lw $static_chain, %lo(end_addr + ...)($1). */
16081 /* Split END_ADDR into %hi and %lo values. Trampolines are aligned
16082 to 64 bits, so the %lo value will have the bottom 3 bits clear. */
16083 high = expand_simple_binop (SImode, PLUS, end_addr, GEN_INT (0x8000),
16084 NULL, false, OPTAB_WIDEN);
16085 high = expand_simple_binop (SImode, LSHIFTRT, high, GEN_INT (16),
16086 NULL, false, OPTAB_WIDEN);
16087 low = convert_to_mode (SImode, gen_lowpart (HImode, end_addr), true);
16089 /* Emit the LUI. */
16090 opcode = OP (MIPS_LUI (AT_REGNUM, 0));
16091 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, high,
16092 NULL, false, OPTAB_WIDEN);
16094 /* Emit the load of the target function. */
16095 opcode = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
16096 target_function_offset - end_addr_offset,
16098 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
16099 NULL, false, OPTAB_WIDEN);
16101 /* Emit the JR here, if we can. */
16102 if (!ISA_HAS_LOAD_DELAY)
16103 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
16105 /* Emit the load of the static chain register. */
16106 opcode = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
16107 static_chain_offset - end_addr_offset,
16109 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
16110 NULL, false, OPTAB_WIDEN);
16112 /* Emit the JR, if we couldn't above. */
16113 if (ISA_HAS_LOAD_DELAY)
16115 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
16116 trampoline[i++] = OP (MIPS_NOP);
16122 /* Copy the trampoline code. Leave any padding uninitialized. */
16123 for (j = 0; j < i; j++)
16125 mem = adjust_address (m_tramp, SImode, j * GET_MODE_SIZE (SImode));
16126 mips_emit_move (mem, trampoline[j]);
16129 /* Set up the static chain pointer field. */
16130 mem = adjust_address (m_tramp, ptr_mode, static_chain_offset);
16131 mips_emit_move (mem, chain_value);
16133 /* Set up the target function field. */
16134 mem = adjust_address (m_tramp, ptr_mode, target_function_offset);
16135 mips_emit_move (mem, XEXP (DECL_RTL (fndecl), 0));
16137 /* Flush the code part of the trampoline. */
16138 emit_insn (gen_add3_insn (end_addr, addr, GEN_INT (TRAMPOLINE_SIZE)));
16139 emit_insn (gen_clear_cache (addr, end_addr));
16142 /* Implement FUNCTION_PROFILER. */
16144 void mips_function_profiler (FILE *file)
16147 sorry ("mips16 function profiling");
16148 if (TARGET_LONG_CALLS)
16150 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */
16151 if (Pmode == DImode)
16152 fprintf (file, "\tdla\t%s,_mcount\n", reg_names[3]);
16154 fprintf (file, "\tla\t%s,_mcount\n", reg_names[3]);
16156 mips_push_asm_switch (&mips_noat);
16157 fprintf (file, "\tmove\t%s,%s\t\t# save current return address\n",
16158 reg_names[AT_REGNUM], reg_names[RETURN_ADDR_REGNUM]);
16159 /* _mcount treats $2 as the static chain register. */
16160 if (cfun->static_chain_decl != NULL)
16161 fprintf (file, "\tmove\t%s,%s\n", reg_names[2],
16162 reg_names[STATIC_CHAIN_REGNUM]);
16163 if (TARGET_MCOUNT_RA_ADDRESS)
16165 /* If TARGET_MCOUNT_RA_ADDRESS load $12 with the address of the
16166 ra save location. */
16167 if (cfun->machine->frame.ra_fp_offset == 0)
16168 /* ra not saved, pass zero. */
16169 fprintf (file, "\tmove\t%s,%s\n", reg_names[12], reg_names[0]);
16171 fprintf (file, "\t%s\t%s," HOST_WIDE_INT_PRINT_DEC "(%s)\n",
16172 Pmode == DImode ? "dla" : "la", reg_names[12],
16173 cfun->machine->frame.ra_fp_offset,
16174 reg_names[STACK_POINTER_REGNUM]);
16176 if (!TARGET_NEWABI)
16178 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n",
16179 TARGET_64BIT ? "dsubu" : "subu",
16180 reg_names[STACK_POINTER_REGNUM],
16181 reg_names[STACK_POINTER_REGNUM],
16182 Pmode == DImode ? 16 : 8);
16184 if (TARGET_LONG_CALLS)
16185 fprintf (file, "\tjalr\t%s\n", reg_names[3]);
16187 fprintf (file, "\tjal\t_mcount\n");
16188 mips_pop_asm_switch (&mips_noat);
16189 /* _mcount treats $2 as the static chain register. */
16190 if (cfun->static_chain_decl != NULL)
16191 fprintf (file, "\tmove\t%s,%s\n", reg_names[STATIC_CHAIN_REGNUM],
16195 /* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default
16196 behaviour of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even
16197 when TARGET_LOONGSON_VECTORS is true. */
16199 static unsigned HOST_WIDE_INT
16200 mips_shift_truncation_mask (enum machine_mode mode)
16202 if (TARGET_LOONGSON_VECTORS && VECTOR_MODE_P (mode))
16205 return GET_MODE_BITSIZE (mode) - 1;
16209 /* Initialize the GCC target structure. */
16210 #undef TARGET_ASM_ALIGNED_HI_OP
16211 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
16212 #undef TARGET_ASM_ALIGNED_SI_OP
16213 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
16214 #undef TARGET_ASM_ALIGNED_DI_OP
16215 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
16217 #undef TARGET_OPTION_OVERRIDE
16218 #define TARGET_OPTION_OVERRIDE mips_option_override
16219 #undef TARGET_OPTION_OPTIMIZATION_TABLE
16220 #define TARGET_OPTION_OPTIMIZATION_TABLE mips_option_optimization_table
16222 #undef TARGET_LEGITIMIZE_ADDRESS
16223 #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
16225 #undef TARGET_ASM_FUNCTION_PROLOGUE
16226 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
16227 #undef TARGET_ASM_FUNCTION_EPILOGUE
16228 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
16229 #undef TARGET_ASM_SELECT_RTX_SECTION
16230 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
16231 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
16232 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
16234 #undef TARGET_SCHED_INIT
16235 #define TARGET_SCHED_INIT mips_sched_init
16236 #undef TARGET_SCHED_REORDER
16237 #define TARGET_SCHED_REORDER mips_sched_reorder
16238 #undef TARGET_SCHED_REORDER2
16239 #define TARGET_SCHED_REORDER2 mips_sched_reorder2
16240 #undef TARGET_SCHED_VARIABLE_ISSUE
16241 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
16242 #undef TARGET_SCHED_ADJUST_COST
16243 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
16244 #undef TARGET_SCHED_ISSUE_RATE
16245 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
16246 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
16247 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
16248 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
16249 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
16250 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
16251 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
16252 mips_multipass_dfa_lookahead
16253 #undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
16254 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
16255 mips_small_register_classes_for_mode_p
16257 #undef TARGET_DEFAULT_TARGET_FLAGS
16258 #define TARGET_DEFAULT_TARGET_FLAGS \
16260 | TARGET_CPU_DEFAULT \
16261 | TARGET_ENDIAN_DEFAULT \
16262 | TARGET_FP_EXCEPTIONS_DEFAULT \
16263 | MASK_CHECK_ZERO_DIV \
16265 #undef TARGET_HANDLE_OPTION
16266 #define TARGET_HANDLE_OPTION mips_handle_option
16268 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
16269 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
16271 #undef TARGET_INSERT_ATTRIBUTES
16272 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
16273 #undef TARGET_MERGE_DECL_ATTRIBUTES
16274 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
16275 #undef TARGET_SET_CURRENT_FUNCTION
16276 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
16278 #undef TARGET_VALID_POINTER_MODE
16279 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
16280 #undef TARGET_REGISTER_MOVE_COST
16281 #define TARGET_REGISTER_MOVE_COST mips_register_move_cost
16282 #undef TARGET_MEMORY_MOVE_COST
16283 #define TARGET_MEMORY_MOVE_COST mips_memory_move_cost
16284 #undef TARGET_RTX_COSTS
16285 #define TARGET_RTX_COSTS mips_rtx_costs
16286 #undef TARGET_ADDRESS_COST
16287 #define TARGET_ADDRESS_COST mips_address_cost
16289 #undef TARGET_IN_SMALL_DATA_P
16290 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
16292 #undef TARGET_MACHINE_DEPENDENT_REORG
16293 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
16295 #undef TARGET_PREFERRED_RELOAD_CLASS
16296 #define TARGET_PREFERRED_RELOAD_CLASS mips_preferred_reload_class
16298 #undef TARGET_ASM_FILE_START
16299 #define TARGET_ASM_FILE_START mips_file_start
16300 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
16301 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
16303 #undef TARGET_INIT_LIBFUNCS
16304 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
16306 #undef TARGET_BUILD_BUILTIN_VA_LIST
16307 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
16308 #undef TARGET_EXPAND_BUILTIN_VA_START
16309 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
16310 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
16311 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
16313 #undef TARGET_PROMOTE_FUNCTION_MODE
16314 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
16315 #undef TARGET_PROMOTE_PROTOTYPES
16316 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
16318 #undef TARGET_FUNCTION_VALUE
16319 #define TARGET_FUNCTION_VALUE mips_function_value
16320 #undef TARGET_LIBCALL_VALUE
16321 #define TARGET_LIBCALL_VALUE mips_libcall_value
16322 #undef TARGET_FUNCTION_VALUE_REGNO_P
16323 #define TARGET_FUNCTION_VALUE_REGNO_P mips_function_value_regno_p
16324 #undef TARGET_RETURN_IN_MEMORY
16325 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
16326 #undef TARGET_RETURN_IN_MSB
16327 #define TARGET_RETURN_IN_MSB mips_return_in_msb
16329 #undef TARGET_ASM_OUTPUT_MI_THUNK
16330 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
16331 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
16332 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
16334 #undef TARGET_PRINT_OPERAND
16335 #define TARGET_PRINT_OPERAND mips_print_operand
16336 #undef TARGET_PRINT_OPERAND_ADDRESS
16337 #define TARGET_PRINT_OPERAND_ADDRESS mips_print_operand_address
16338 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
16339 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mips_print_operand_punct_valid_p
16341 #undef TARGET_SETUP_INCOMING_VARARGS
16342 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
16343 #undef TARGET_STRICT_ARGUMENT_NAMING
16344 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
16345 #undef TARGET_MUST_PASS_IN_STACK
16346 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
16347 #undef TARGET_PASS_BY_REFERENCE
16348 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
16349 #undef TARGET_CALLEE_COPIES
16350 #define TARGET_CALLEE_COPIES mips_callee_copies
16351 #undef TARGET_ARG_PARTIAL_BYTES
16352 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
16353 #undef TARGET_FUNCTION_ARG
16354 #define TARGET_FUNCTION_ARG mips_function_arg
16355 #undef TARGET_FUNCTION_ARG_ADVANCE
16356 #define TARGET_FUNCTION_ARG_ADVANCE mips_function_arg_advance
16357 #undef TARGET_FUNCTION_ARG_BOUNDARY
16358 #define TARGET_FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
16360 #undef TARGET_MODE_REP_EXTENDED
16361 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
16363 #undef TARGET_VECTOR_MODE_SUPPORTED_P
16364 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
16366 #undef TARGET_SCALAR_MODE_SUPPORTED_P
16367 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
16369 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
16370 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE mips_preferred_simd_mode
16372 #undef TARGET_INIT_BUILTINS
16373 #define TARGET_INIT_BUILTINS mips_init_builtins
16374 #undef TARGET_BUILTIN_DECL
16375 #define TARGET_BUILTIN_DECL mips_builtin_decl
16376 #undef TARGET_EXPAND_BUILTIN
16377 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
16379 #undef TARGET_HAVE_TLS
16380 #define TARGET_HAVE_TLS HAVE_AS_TLS
16382 #undef TARGET_CANNOT_FORCE_CONST_MEM
16383 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
16385 #undef TARGET_LEGITIMATE_CONSTANT_P
16386 #define TARGET_LEGITIMATE_CONSTANT_P mips_legitimate_constant_p
16388 #undef TARGET_ENCODE_SECTION_INFO
16389 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
16391 #undef TARGET_ATTRIBUTE_TABLE
16392 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
16393 /* All our function attributes are related to how out-of-line copies should
16394 be compiled or called. They don't in themselves prevent inlining. */
16395 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
16396 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
16398 #undef TARGET_EXTRA_LIVE_ON_ENTRY
16399 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
16401 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
16402 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
16403 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
16404 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
16406 #undef TARGET_COMP_TYPE_ATTRIBUTES
16407 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
16409 #ifdef HAVE_AS_DTPRELWORD
16410 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
16411 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
16413 #undef TARGET_DWARF_REGISTER_SPAN
16414 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
16416 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
16417 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
16419 #undef TARGET_LEGITIMATE_ADDRESS_P
16420 #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p
16422 #undef TARGET_FRAME_POINTER_REQUIRED
16423 #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required
16425 #undef TARGET_CAN_ELIMINATE
16426 #define TARGET_CAN_ELIMINATE mips_can_eliminate
16428 #undef TARGET_CONDITIONAL_REGISTER_USAGE
16429 #define TARGET_CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage
16431 #undef TARGET_TRAMPOLINE_INIT
16432 #define TARGET_TRAMPOLINE_INIT mips_trampoline_init
16434 #undef TARGET_ASM_OUTPUT_SOURCE_FILENAME
16435 #define TARGET_ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
16437 #undef TARGET_SHIFT_TRUNCATION_MASK
16438 #define TARGET_SHIFT_TRUNCATION_MASK mips_shift_truncation_mask
16440 struct gcc_target targetm = TARGET_INITIALIZER;
16442 #include "gt-mips.h"