1 /* Output routines for Motorola MCore processor
2 Copyright (C) 1993, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008,
3 2009, 2010 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
30 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
34 #include "insn-attr.h"
42 #include "diagnostic-core.h"
44 #include "target-def.h"
47 /* For dumping information about frame sizes. */
48 char * mcore_current_function_name = 0;
49 long mcore_current_compilation_timestamp = 0;
51 /* Global variables for machine-dependent things. */
53 /* Provides the class number of the smallest class containing
55 const enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER] =
57 GENERAL_REGS, ONLYR1_REGS, LRW_REGS, LRW_REGS,
58 LRW_REGS, LRW_REGS, LRW_REGS, LRW_REGS,
59 LRW_REGS, LRW_REGS, LRW_REGS, LRW_REGS,
60 LRW_REGS, LRW_REGS, LRW_REGS, GENERAL_REGS,
61 GENERAL_REGS, C_REGS, NO_REGS, NO_REGS,
66 int arg_size; /* Stdarg spills (bytes). */
67 int reg_size; /* Non-volatile reg saves (bytes). */
68 int reg_mask; /* Non-volatile reg saves. */
69 int local_size; /* Locals. */
70 int outbound_size; /* Arg overflow on calls out. */
74 /* Describe the steps we'll use to grow it. */
75 #define MAX_STACK_GROWS 4 /* Gives us some spare space. */
76 int growth[MAX_STACK_GROWS];
94 static void output_stack_adjust (int, int);
95 static int calc_live_regs (int *);
96 static int try_constant_tricks (long, HOST_WIDE_INT *, HOST_WIDE_INT *);
97 static const char * output_inline_const (enum machine_mode, rtx *);
98 static void layout_mcore_frame (struct mcore_frame *);
99 static void mcore_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode, tree, int *, int);
100 static cond_type is_cond_candidate (rtx);
101 static rtx emit_new_cond_insn (rtx, int);
102 static rtx conditionalize_block (rtx);
103 static void conditionalize_optimization (void);
104 static void mcore_reorg (void);
105 static rtx handle_structs_in_regs (enum machine_mode, const_tree, int);
106 static void mcore_mark_dllexport (tree);
107 static void mcore_mark_dllimport (tree);
108 static int mcore_dllexport_p (tree);
109 static int mcore_dllimport_p (tree);
110 static tree mcore_handle_naked_attribute (tree *, tree, tree, int, bool *);
111 #ifdef OBJECT_FORMAT_ELF
112 static void mcore_asm_named_section (const char *,
115 static void mcore_print_operand (FILE *, rtx, int);
116 static void mcore_print_operand_address (FILE *, rtx);
117 static bool mcore_print_operand_punct_valid_p (unsigned char code);
118 static void mcore_unique_section (tree, int);
119 static void mcore_encode_section_info (tree, rtx, int);
120 static const char *mcore_strip_name_encoding (const char *);
121 static int mcore_const_costs (rtx, RTX_CODE);
122 static int mcore_and_cost (rtx);
123 static int mcore_ior_cost (rtx);
124 static bool mcore_rtx_costs (rtx, int, int, int *, bool);
125 static void mcore_external_libcall (rtx);
126 static bool mcore_return_in_memory (const_tree, const_tree);
127 static int mcore_arg_partial_bytes (CUMULATIVE_ARGS *,
130 static rtx mcore_function_arg (CUMULATIVE_ARGS *,
133 static void mcore_function_arg_advance (CUMULATIVE_ARGS *,
136 static unsigned int mcore_function_arg_boundary (enum machine_mode,
138 static void mcore_asm_trampoline_template (FILE *);
139 static void mcore_trampoline_init (rtx, tree, rtx);
140 static void mcore_option_override (void);
141 static bool mcore_legitimate_constant_p (enum machine_mode, rtx);
143 /* MCore specific attributes. */
145 static const struct attribute_spec mcore_attribute_table[] =
147 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
148 affects_type_identity } */
149 { "dllexport", 0, 0, true, false, false, NULL, false },
150 { "dllimport", 0, 0, true, false, false, NULL, false },
151 { "naked", 0, 0, true, false, false, mcore_handle_naked_attribute,
153 { NULL, 0, 0, false, false, false, NULL, false }
156 /* What options are we going to default to specific settings when
157 -O* happens; the user can subsequently override these settings.
159 Omitting the frame pointer is a very good idea on the MCore.
160 Scheduling isn't worth anything on the current MCore implementation. */
162 static const struct default_options mcore_option_optimization_table[] =
164 { OPT_LEVELS_1_PLUS, OPT_ffunction_cse, NULL, 0 },
165 { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
166 { OPT_LEVELS_ALL, OPT_fcaller_saves, NULL, 0 },
167 { OPT_LEVELS_ALL, OPT_fschedule_insns, NULL, 0 },
168 { OPT_LEVELS_ALL, OPT_fschedule_insns2, NULL, 0 },
169 { OPT_LEVELS_SIZE, OPT_mhardlit, NULL, 0 },
170 { OPT_LEVELS_NONE, 0, NULL, 0 }
173 /* Initialize the GCC target structure. */
174 #undef TARGET_ASM_EXTERNAL_LIBCALL
175 #define TARGET_ASM_EXTERNAL_LIBCALL mcore_external_libcall
177 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
178 #undef TARGET_MERGE_DECL_ATTRIBUTES
179 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
182 #ifdef OBJECT_FORMAT_ELF
183 #undef TARGET_ASM_UNALIGNED_HI_OP
184 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
185 #undef TARGET_ASM_UNALIGNED_SI_OP
186 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
189 #undef TARGET_PRINT_OPERAND
190 #define TARGET_PRINT_OPERAND mcore_print_operand
191 #undef TARGET_PRINT_OPERAND_ADDRESS
192 #define TARGET_PRINT_OPERAND_ADDRESS mcore_print_operand_address
193 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
194 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mcore_print_operand_punct_valid_p
196 #undef TARGET_ATTRIBUTE_TABLE
197 #define TARGET_ATTRIBUTE_TABLE mcore_attribute_table
198 #undef TARGET_ASM_UNIQUE_SECTION
199 #define TARGET_ASM_UNIQUE_SECTION mcore_unique_section
200 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
201 #define TARGET_ASM_FUNCTION_RODATA_SECTION default_no_function_rodata_section
202 #undef TARGET_DEFAULT_TARGET_FLAGS
203 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
204 #undef TARGET_ENCODE_SECTION_INFO
205 #define TARGET_ENCODE_SECTION_INFO mcore_encode_section_info
206 #undef TARGET_STRIP_NAME_ENCODING
207 #define TARGET_STRIP_NAME_ENCODING mcore_strip_name_encoding
208 #undef TARGET_RTX_COSTS
209 #define TARGET_RTX_COSTS mcore_rtx_costs
210 #undef TARGET_ADDRESS_COST
211 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0
212 #undef TARGET_MACHINE_DEPENDENT_REORG
213 #define TARGET_MACHINE_DEPENDENT_REORG mcore_reorg
215 #undef TARGET_PROMOTE_FUNCTION_MODE
216 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
217 #undef TARGET_PROMOTE_PROTOTYPES
218 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
220 #undef TARGET_RETURN_IN_MEMORY
221 #define TARGET_RETURN_IN_MEMORY mcore_return_in_memory
222 #undef TARGET_MUST_PASS_IN_STACK
223 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
224 #undef TARGET_PASS_BY_REFERENCE
225 #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack
226 #undef TARGET_ARG_PARTIAL_BYTES
227 #define TARGET_ARG_PARTIAL_BYTES mcore_arg_partial_bytes
228 #undef TARGET_FUNCTION_ARG
229 #define TARGET_FUNCTION_ARG mcore_function_arg
230 #undef TARGET_FUNCTION_ARG_ADVANCE
231 #define TARGET_FUNCTION_ARG_ADVANCE mcore_function_arg_advance
232 #undef TARGET_FUNCTION_ARG_BOUNDARY
233 #define TARGET_FUNCTION_ARG_BOUNDARY mcore_function_arg_boundary
235 #undef TARGET_SETUP_INCOMING_VARARGS
236 #define TARGET_SETUP_INCOMING_VARARGS mcore_setup_incoming_varargs
238 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
239 #define TARGET_ASM_TRAMPOLINE_TEMPLATE mcore_asm_trampoline_template
240 #undef TARGET_TRAMPOLINE_INIT
241 #define TARGET_TRAMPOLINE_INIT mcore_trampoline_init
243 #undef TARGET_OPTION_OVERRIDE
244 #define TARGET_OPTION_OVERRIDE mcore_option_override
245 #undef TARGET_OPTION_OPTIMIZATION_TABLE
246 #define TARGET_OPTION_OPTIMIZATION_TABLE mcore_option_optimization_table
248 #undef TARGET_EXCEPT_UNWIND_INFO
249 #define TARGET_EXCEPT_UNWIND_INFO sjlj_except_unwind_info
251 #undef TARGET_LEGITIMATE_CONSTANT_P
252 #define TARGET_LEGITIMATE_CONSTANT_P mcore_legitimate_constant_p
254 struct gcc_target targetm = TARGET_INITIALIZER;
256 /* Adjust the stack and return the number of bytes taken to do it. */
258 output_stack_adjust (int direction, int size)
260 /* If extending stack a lot, we do it incrementally. */
261 if (direction < 0 && size > mcore_stack_increment && mcore_stack_increment > 0)
263 rtx tmp = gen_rtx_REG (SImode, 1);
266 emit_insn (gen_movsi (tmp, GEN_INT (mcore_stack_increment)));
269 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, tmp));
270 memref = gen_rtx_MEM (SImode, stack_pointer_rtx);
271 MEM_VOLATILE_P (memref) = 1;
272 emit_insn (gen_movsi (memref, stack_pointer_rtx));
273 size -= mcore_stack_increment;
275 while (size > mcore_stack_increment);
277 /* SIZE is now the residual for the last adjustment,
278 which doesn't require a probe. */
284 rtx val = GEN_INT (size);
288 rtx nval = gen_rtx_REG (SImode, 1);
289 emit_insn (gen_movsi (nval, val));
294 insn = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, val);
296 insn = gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, val);
302 /* Work out the registers which need to be saved,
303 both as a mask and a count. */
306 calc_live_regs (int * count)
309 int live_regs_mask = 0;
313 for (reg = 0; reg < FIRST_PSEUDO_REGISTER; reg++)
315 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
318 live_regs_mask |= (1 << reg);
322 return live_regs_mask;
325 /* Print the operand address in x to the stream. */
328 mcore_print_operand_address (FILE * stream, rtx x)
330 switch (GET_CODE (x))
333 fprintf (stream, "(%s)", reg_names[REGNO (x)]);
338 rtx base = XEXP (x, 0);
339 rtx index = XEXP (x, 1);
341 if (GET_CODE (base) != REG)
343 /* Ensure that BASE is a register (one of them must be). */
349 switch (GET_CODE (index))
352 fprintf (stream, "(%s," HOST_WIDE_INT_PRINT_DEC ")",
353 reg_names[REGNO(base)], INTVAL (index));
364 output_addr_const (stream, x);
370 mcore_print_operand_punct_valid_p (unsigned char code)
372 return (code == '.' || code == '#' || code == '*' || code == '^'
376 /* Print operand x (an rtx) in assembler syntax to file stream
377 according to modifier code.
379 'R' print the next register or memory location along, i.e. the lsw in
381 'O' print a constant without the #
382 'M' print a constant as its negative
383 'P' print log2 of a power of two
384 'Q' print log2 of an inverse of a power of two
385 'U' print register for ldm/stm instruction
386 'X' print byte number for xtrbN instruction. */
389 mcore_print_operand (FILE * stream, rtx x, int code)
395 fprintf (asm_out_file, "32");
397 fprintf (asm_out_file, "%d", exact_log2 (INTVAL (x) + 1));
400 fprintf (asm_out_file, "%d", exact_log2 (INTVAL (x) & 0xffffffff));
403 fprintf (asm_out_file, "%d", exact_log2 (~INTVAL (x)));
406 fprintf (asm_out_file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
409 fprintf (asm_out_file, HOST_WIDE_INT_PRINT_DEC, - INTVAL (x));
412 /* Next location along in memory or register. */
413 switch (GET_CODE (x))
416 fputs (reg_names[REGNO (x) + 1], (stream));
419 mcore_print_operand_address
420 (stream, XEXP (adjust_address (x, SImode, 4), 0));
427 fprintf (asm_out_file, "%s-%s", reg_names[REGNO (x)],
428 reg_names[REGNO (x) + 3]);
431 fprintf (asm_out_file, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
434 fprintf (asm_out_file, HOST_WIDE_INT_PRINT_DEC, 3 - INTVAL (x) / 8);
438 switch (GET_CODE (x))
441 fputs (reg_names[REGNO (x)], (stream));
444 output_address (XEXP (x, 0));
447 output_addr_const (stream, x);
454 /* What does a constant cost ? */
457 mcore_const_costs (rtx exp, enum rtx_code code)
459 HOST_WIDE_INT val = INTVAL (exp);
461 /* Easy constants. */
462 if ( CONST_OK_FOR_I (val)
463 || CONST_OK_FOR_M (val)
464 || CONST_OK_FOR_N (val)
465 || (code == PLUS && CONST_OK_FOR_L (val)))
468 && ( CONST_OK_FOR_M (~val)
469 || CONST_OK_FOR_N (~val)))
471 else if (code == PLUS
472 && ( CONST_OK_FOR_I (-val)
473 || CONST_OK_FOR_M (-val)
474 || CONST_OK_FOR_N (-val)))
480 /* What does an and instruction cost - we do this b/c immediates may
481 have been relaxed. We want to ensure that cse will cse relaxed immeds
482 out. Otherwise we'll get bad code (multiple reloads of the same const). */
485 mcore_and_cost (rtx x)
489 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
492 val = INTVAL (XEXP (x, 1));
494 /* Do it directly. */
495 if (CONST_OK_FOR_K (val) || CONST_OK_FOR_M (~val))
497 /* Takes one instruction to load. */
498 else if (const_ok_for_mcore (val))
500 /* Takes two instructions to load. */
501 else if (TARGET_HARDLIT && mcore_const_ok_for_inline (val))
504 /* Takes a lrw to load. */
508 /* What does an or cost - see and_cost(). */
511 mcore_ior_cost (rtx x)
515 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
518 val = INTVAL (XEXP (x, 1));
520 /* Do it directly with bclri. */
521 if (CONST_OK_FOR_M (val))
523 /* Takes one instruction to load. */
524 else if (const_ok_for_mcore (val))
526 /* Takes two instructions to load. */
527 else if (TARGET_HARDLIT && mcore_const_ok_for_inline (val))
530 /* Takes a lrw to load. */
535 mcore_rtx_costs (rtx x, int code, int outer_code, int * total,
536 bool speed ATTRIBUTE_UNUSED)
541 *total = mcore_const_costs (x, (enum rtx_code) outer_code);
553 *total = COSTS_N_INSNS (mcore_and_cost (x));
557 *total = COSTS_N_INSNS (mcore_ior_cost (x));
566 *total = COSTS_N_INSNS (100);
574 /* Prepare the operands for a comparison. Return whether the branch/setcc
575 should reverse the operands. */
578 mcore_gen_compare (enum rtx_code code, rtx op0, rtx op1)
580 rtx cc_reg = gen_rtx_REG (CCmode, CC_REG);
583 if (GET_CODE (op1) == CONST_INT)
585 HOST_WIDE_INT val = INTVAL (op1);
590 /* Unsigned > 0 is the same as != 0; everything else is converted
591 below to LEU (reversed cmphs). */
596 /* Check whether (LE A imm) can become (LT A imm + 1),
597 or (GT A imm) can become (GE A imm + 1). */
600 if (CONST_OK_FOR_J (val + 1))
602 op1 = GEN_INT (val + 1);
603 code = code == LE ? LT : GE;
612 if (CONSTANT_P (op1) && GET_CODE (op1) != CONST_INT)
613 op1 = force_reg (SImode, op1);
615 /* cmpnei: 0-31 (K immediate)
616 cmplti: 1-32 (J immediate, 0 using btsti x,31). */
620 case EQ: /* Use inverted condition, cmpne. */
625 case NE: /* Use normal condition, cmpne. */
626 if (GET_CODE (op1) == CONST_INT && ! CONST_OK_FOR_K (INTVAL (op1)))
627 op1 = force_reg (SImode, op1);
630 case LE: /* Use inverted condition, reversed cmplt. */
635 case GT: /* Use normal condition, reversed cmplt. */
636 if (GET_CODE (op1) == CONST_INT)
637 op1 = force_reg (SImode, op1);
640 case GE: /* Use inverted condition, cmplt. */
645 case LT: /* Use normal condition, cmplt. */
646 if (GET_CODE (op1) == CONST_INT &&
647 /* covered by btsti x,31. */
649 ! CONST_OK_FOR_J (INTVAL (op1)))
650 op1 = force_reg (SImode, op1);
653 case GTU: /* Use inverted condition, cmple. */
654 /* We coped with unsigned > 0 above. */
655 gcc_assert (GET_CODE (op1) != CONST_INT || INTVAL (op1) != 0);
660 case LEU: /* Use normal condition, reversed cmphs. */
661 if (GET_CODE (op1) == CONST_INT && INTVAL (op1) != 0)
662 op1 = force_reg (SImode, op1);
665 case LTU: /* Use inverted condition, cmphs. */
670 case GEU: /* Use normal condition, cmphs. */
671 if (GET_CODE (op1) == CONST_INT && INTVAL (op1) != 0)
672 op1 = force_reg (SImode, op1);
679 emit_insn (gen_rtx_SET (VOIDmode,
681 gen_rtx_fmt_ee (code, CCmode, op0, op1)));
686 mcore_symbolic_address_p (rtx x)
688 switch (GET_CODE (x))
695 return ( (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
696 || GET_CODE (XEXP (x, 0)) == LABEL_REF)
697 && GET_CODE (XEXP (x, 1)) == CONST_INT);
703 /* Functions to output assembly code for a function call. */
706 mcore_output_call (rtx operands[], int index)
708 static char buffer[20];
709 rtx addr = operands [index];
715 gcc_assert (mcore_current_function_name);
717 ASM_OUTPUT_CG_EDGE (asm_out_file, mcore_current_function_name,
721 sprintf (buffer, "jsr\t%%%d", index);
727 gcc_assert (mcore_current_function_name);
728 gcc_assert (GET_CODE (addr) == SYMBOL_REF);
730 ASM_OUTPUT_CG_EDGE (asm_out_file, mcore_current_function_name,
734 sprintf (buffer, "jbsr\t%%%d", index);
740 /* Can we load a constant with a single instruction ? */
743 const_ok_for_mcore (HOST_WIDE_INT value)
745 if (value >= 0 && value <= 127)
748 /* Try exact power of two. */
749 if (CONST_OK_FOR_M (value))
752 /* Try exact power of two - 1. */
753 if (CONST_OK_FOR_N (value) && value != -1)
759 /* Can we load a constant inline with up to 2 instructions ? */
762 mcore_const_ok_for_inline (HOST_WIDE_INT value)
766 return try_constant_tricks (value, & x, & y) > 0;
769 /* Are we loading the constant using a not ? */
772 mcore_const_trick_uses_not (HOST_WIDE_INT value)
776 return try_constant_tricks (value, & x, & y) == 2;
779 /* Try tricks to load a constant inline and return the trick number if
780 success (0 is non-inlinable).
783 1: single instruction (do the usual thing)
784 2: single insn followed by a 'not'
785 3: single insn followed by a subi
786 4: single insn followed by an addi
787 5: single insn followed by rsubi
788 6: single insn followed by bseti
789 7: single insn followed by bclri
790 8: single insn followed by rotli
791 9: single insn followed by lsli
792 10: single insn followed by ixh
793 11: single insn followed by ixw. */
796 try_constant_tricks (HOST_WIDE_INT value, HOST_WIDE_INT * x, HOST_WIDE_INT * y)
799 unsigned HOST_WIDE_INT bit, shf, rot;
801 if (const_ok_for_mcore (value))
802 return 1; /* Do the usual thing. */
804 if (! TARGET_HARDLIT)
807 if (const_ok_for_mcore (~value))
813 for (i = 1; i <= 32; i++)
815 if (const_ok_for_mcore (value - i))
823 if (const_ok_for_mcore (value + i))
834 for (i = 0; i <= 31; i++)
836 if (const_ok_for_mcore (i - value))
844 if (const_ok_for_mcore (value & ~bit))
851 if (const_ok_for_mcore (value | bit))
865 for (i = 1; i < 31; i++)
869 /* MCore has rotate left. */
873 rot |= c; /* Simulate rotate. */
875 if (const_ok_for_mcore (rot))
884 shf = 0; /* Can't use logical shift, low order bit is one. */
888 if (shf != 0 && const_ok_for_mcore (shf))
897 if ((value % 3) == 0 && const_ok_for_mcore (value / 3))
904 if ((value % 5) == 0 && const_ok_for_mcore (value / 5))
914 /* Check whether reg is dead at first. This is done by searching ahead
915 for either the next use (i.e., reg is live), a death note, or a set of
916 reg. Don't just use dead_or_set_p() since reload does not always mark
917 deaths (especially if PRESERVE_DEATH_NOTES_REGNO_P is not defined). We
918 can ignore subregs by extracting the actual register. BRC */
921 mcore_is_dead (rtx first, rtx reg)
925 /* For mcore, subregs can't live independently of their parent regs. */
926 if (GET_CODE (reg) == SUBREG)
927 reg = SUBREG_REG (reg);
929 /* Dies immediately. */
930 if (dead_or_set_p (first, reg))
933 /* Look for conclusive evidence of live/death, otherwise we have
934 to assume that it is live. */
935 for (insn = NEXT_INSN (first); insn; insn = NEXT_INSN (insn))
937 if (GET_CODE (insn) == JUMP_INSN)
938 return 0; /* We lose track, assume it is alive. */
940 else if (GET_CODE(insn) == CALL_INSN)
942 /* Call's might use it for target or register parms. */
943 if (reg_referenced_p (reg, PATTERN (insn))
944 || find_reg_fusage (insn, USE, reg))
946 else if (dead_or_set_p (insn, reg))
949 else if (GET_CODE (insn) == INSN)
951 if (reg_referenced_p (reg, PATTERN (insn)))
953 else if (dead_or_set_p (insn, reg))
958 /* No conclusive evidence either way, we cannot take the chance
959 that control flow hid the use from us -- "I'm not dead yet". */
963 /* Count the number of ones in mask. */
966 mcore_num_ones (HOST_WIDE_INT mask)
968 /* A trick to count set bits recently posted on comp.compilers. */
969 mask = (mask >> 1 & 0x55555555) + (mask & 0x55555555);
970 mask = ((mask >> 2) & 0x33333333) + (mask & 0x33333333);
971 mask = ((mask >> 4) + mask) & 0x0f0f0f0f;
972 mask = ((mask >> 8) + mask);
974 return (mask + (mask >> 16)) & 0xff;
977 /* Count the number of zeros in mask. */
980 mcore_num_zeros (HOST_WIDE_INT mask)
982 return 32 - mcore_num_ones (mask);
985 /* Determine byte being masked. */
988 mcore_byte_offset (unsigned int mask)
990 if (mask == 0x00ffffffL)
992 else if (mask == 0xff00ffffL)
994 else if (mask == 0xffff00ffL)
996 else if (mask == 0xffffff00L)
1002 /* Determine halfword being masked. */
1005 mcore_halfword_offset (unsigned int mask)
1007 if (mask == 0x0000ffffL)
1009 else if (mask == 0xffff0000L)
1015 /* Output a series of bseti's corresponding to mask. */
1018 mcore_output_bseti (rtx dst, int mask)
1020 rtx out_operands[2];
1023 out_operands[0] = dst;
1025 for (bit = 0; bit < 32; bit++)
1027 if ((mask & 0x1) == 0x1)
1029 out_operands[1] = GEN_INT (bit);
1031 output_asm_insn ("bseti\t%0,%1", out_operands);
1039 /* Output a series of bclri's corresponding to mask. */
1042 mcore_output_bclri (rtx dst, int mask)
1044 rtx out_operands[2];
1047 out_operands[0] = dst;
1049 for (bit = 0; bit < 32; bit++)
1051 if ((mask & 0x1) == 0x0)
1053 out_operands[1] = GEN_INT (bit);
1055 output_asm_insn ("bclri\t%0,%1", out_operands);
1064 /* Output a conditional move of two constants that are +/- 1 within each
1065 other. See the "movtK" patterns in mcore.md. I'm not sure this is
1066 really worth the effort. */
1069 mcore_output_cmov (rtx operands[], int cmp_t, const char * test)
1071 HOST_WIDE_INT load_value;
1072 HOST_WIDE_INT adjust_value;
1073 rtx out_operands[4];
1075 out_operands[0] = operands[0];
1077 /* Check to see which constant is loadable. */
1078 if (const_ok_for_mcore (INTVAL (operands[1])))
1080 out_operands[1] = operands[1];
1081 out_operands[2] = operands[2];
1083 else if (const_ok_for_mcore (INTVAL (operands[2])))
1085 out_operands[1] = operands[2];
1086 out_operands[2] = operands[1];
1088 /* Complement test since constants are swapped. */
1089 cmp_t = (cmp_t == 0);
1091 load_value = INTVAL (out_operands[1]);
1092 adjust_value = INTVAL (out_operands[2]);
1094 /* First output the test if folded into the pattern. */
1097 output_asm_insn (test, operands);
1099 /* Load the constant - for now, only support constants that can be
1100 generated with a single instruction. maybe add general inlinable
1101 constants later (this will increase the # of patterns since the
1102 instruction sequence has a different length attribute). */
1103 if (load_value >= 0 && load_value <= 127)
1104 output_asm_insn ("movi\t%0,%1", out_operands);
1105 else if (CONST_OK_FOR_M (load_value))
1106 output_asm_insn ("bgeni\t%0,%P1", out_operands);
1107 else if (CONST_OK_FOR_N (load_value))
1108 output_asm_insn ("bmaski\t%0,%N1", out_operands);
1110 /* Output the constant adjustment. */
1111 if (load_value > adjust_value)
1114 output_asm_insn ("decf\t%0", out_operands);
1116 output_asm_insn ("dect\t%0", out_operands);
1121 output_asm_insn ("incf\t%0", out_operands);
1123 output_asm_insn ("inct\t%0", out_operands);
1129 /* Outputs the peephole for moving a constant that gets not'ed followed
1130 by an and (i.e. combine the not and the and into andn). BRC */
1133 mcore_output_andn (rtx insn ATTRIBUTE_UNUSED, rtx operands[])
1136 rtx out_operands[3];
1137 const char * load_op;
1141 trick_no = try_constant_tricks (INTVAL (operands[1]), &x, &y);
1142 gcc_assert (trick_no == 2);
1144 out_operands[0] = operands[0];
1145 out_operands[1] = GEN_INT (x);
1146 out_operands[2] = operands[2];
1148 if (x >= 0 && x <= 127)
1149 load_op = "movi\t%0,%1";
1151 /* Try exact power of two. */
1152 else if (CONST_OK_FOR_M (x))
1153 load_op = "bgeni\t%0,%P1";
1155 /* Try exact power of two - 1. */
1156 else if (CONST_OK_FOR_N (x))
1157 load_op = "bmaski\t%0,%N1";
1161 load_op = "BADMOVI-andn\t%0, %1";
1165 sprintf (buf, "%s\n\tandn\t%%2,%%0", load_op);
1166 output_asm_insn (buf, out_operands);
1171 /* Output an inline constant. */
1174 output_inline_const (enum machine_mode mode, rtx operands[])
1176 HOST_WIDE_INT x = 0, y = 0;
1178 rtx out_operands[3];
1181 const char *dst_fmt;
1182 HOST_WIDE_INT value;
1184 value = INTVAL (operands[1]);
1186 trick_no = try_constant_tricks (value, &x, &y);
1187 /* lrw's are handled separately: Large inlinable constants never get
1188 turned into lrw's. Our caller uses try_constant_tricks to back
1189 off to an lrw rather than calling this routine. */
1190 gcc_assert (trick_no != 0);
1195 /* operands: 0 = dst, 1 = load immed., 2 = immed. adjustment. */
1196 out_operands[0] = operands[0];
1197 out_operands[1] = GEN_INT (x);
1200 out_operands[2] = GEN_INT (y);
1202 /* Select dst format based on mode. */
1203 if (mode == DImode && (! TARGET_LITTLE_END))
1208 if (x >= 0 && x <= 127)
1209 sprintf (load_op, "movi\t%s,%%1", dst_fmt);
1211 /* Try exact power of two. */
1212 else if (CONST_OK_FOR_M (x))
1213 sprintf (load_op, "bgeni\t%s,%%P1", dst_fmt);
1215 /* Try exact power of two - 1. */
1216 else if (CONST_OK_FOR_N (x))
1217 sprintf (load_op, "bmaski\t%s,%%N1", dst_fmt);
1221 sprintf (load_op, "BADMOVI-inline_const %s, %%1", dst_fmt);
1228 strcpy (buf, load_op);
1231 sprintf (buf, "%s\n\tnot\t%s\t// %ld 0x%lx", load_op, dst_fmt, value, value);
1234 sprintf (buf, "%s\n\taddi\t%s,%%2\t// %ld 0x%lx", load_op, dst_fmt, value, value);
1237 sprintf (buf, "%s\n\tsubi\t%s,%%2\t// %ld 0x%lx", load_op, dst_fmt, value, value);
1240 /* Never happens unless -mrsubi, see try_constant_tricks(). */
1241 sprintf (buf, "%s\n\trsubi\t%s,%%2\t// %ld 0x%lx", load_op, dst_fmt, value, value);
1244 sprintf (buf, "%s\n\tbseti\t%s,%%P2\t// %ld 0x%lx", load_op, dst_fmt, value, value);
1247 sprintf (buf, "%s\n\tbclri\t%s,%%Q2\t// %ld 0x%lx", load_op, dst_fmt, value, value);
1250 sprintf (buf, "%s\n\trotli\t%s,%%2\t// %ld 0x%lx", load_op, dst_fmt, value, value);
1253 sprintf (buf, "%s\n\tlsli\t%s,%%2\t// %ld 0x%lx", load_op, dst_fmt, value, value);
1256 sprintf (buf, "%s\n\tixh\t%s,%s\t// %ld 0x%lx", load_op, dst_fmt, dst_fmt, value, value);
1259 sprintf (buf, "%s\n\tixw\t%s,%s\t// %ld 0x%lx", load_op, dst_fmt, dst_fmt, value, value);
1265 output_asm_insn (buf, out_operands);
1270 /* Output a move of a word or less value. */
1273 mcore_output_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
1274 enum machine_mode mode ATTRIBUTE_UNUSED)
1276 rtx dst = operands[0];
1277 rtx src = operands[1];
1279 if (GET_CODE (dst) == REG)
1281 if (GET_CODE (src) == REG)
1283 if (REGNO (src) == CC_REG) /* r-c */
1286 return "mov\t%0,%1"; /* r-r*/
1288 else if (GET_CODE (src) == MEM)
1290 if (GET_CODE (XEXP (src, 0)) == LABEL_REF)
1291 return "lrw\t%0,[%1]"; /* a-R */
1293 switch (GET_MODE (src)) /* r-m */
1296 return "ldw\t%0,%1";
1298 return "ld.h\t%0,%1";
1300 return "ld.b\t%0,%1";
1305 else if (GET_CODE (src) == CONST_INT)
1309 if (CONST_OK_FOR_I (INTVAL (src))) /* r-I */
1310 return "movi\t%0,%1";
1311 else if (CONST_OK_FOR_M (INTVAL (src))) /* r-M */
1312 return "bgeni\t%0,%P1\t// %1 %x1";
1313 else if (CONST_OK_FOR_N (INTVAL (src))) /* r-N */
1314 return "bmaski\t%0,%N1\t// %1 %x1";
1315 else if (try_constant_tricks (INTVAL (src), &x, &y)) /* R-P */
1316 return output_inline_const (SImode, operands); /* 1-2 insns */
1318 return "lrw\t%0,%x1\t// %1"; /* Get it from literal pool. */
1321 return "lrw\t%0, %1"; /* Into the literal pool. */
1323 else if (GET_CODE (dst) == MEM) /* m-r */
1324 switch (GET_MODE (dst))
1327 return "stw\t%1,%0";
1329 return "st.h\t%1,%0";
1331 return "st.b\t%1,%0";
1339 /* Return a sequence of instructions to perform DI or DF move.
1340 Since the MCORE cannot move a DI or DF in one instruction, we have
1341 to take care when we see overlapping source and dest registers. */
1344 mcore_output_movedouble (rtx operands[], enum machine_mode mode ATTRIBUTE_UNUSED)
1346 rtx dst = operands[0];
1347 rtx src = operands[1];
1349 if (GET_CODE (dst) == REG)
1351 if (GET_CODE (src) == REG)
1353 int dstreg = REGNO (dst);
1354 int srcreg = REGNO (src);
1356 /* Ensure the second source not overwritten. */
1357 if (srcreg + 1 == dstreg)
1358 return "mov %R0,%R1\n\tmov %0,%1";
1360 return "mov %0,%1\n\tmov %R0,%R1";
1362 else if (GET_CODE (src) == MEM)
1364 rtx memexp = memexp = XEXP (src, 0);
1365 int dstreg = REGNO (dst);
1368 if (GET_CODE (memexp) == LABEL_REF)
1369 return "lrw\t%0,[%1]\n\tlrw\t%R0,[%R1]";
1370 else if (GET_CODE (memexp) == REG)
1371 basereg = REGNO (memexp);
1372 else if (GET_CODE (memexp) == PLUS)
1374 if (GET_CODE (XEXP (memexp, 0)) == REG)
1375 basereg = REGNO (XEXP (memexp, 0));
1376 else if (GET_CODE (XEXP (memexp, 1)) == REG)
1377 basereg = REGNO (XEXP (memexp, 1));
1384 /* ??? length attribute is wrong here. */
1385 if (dstreg == basereg)
1387 /* Just load them in reverse order. */
1388 return "ldw\t%R0,%R1\n\tldw\t%0,%1";
1390 /* XXX: alternative: move basereg to basereg+1
1391 and then fall through. */
1394 return "ldw\t%0,%1\n\tldw\t%R0,%R1";
1396 else if (GET_CODE (src) == CONST_INT)
1398 if (TARGET_LITTLE_END)
1400 if (CONST_OK_FOR_I (INTVAL (src)))
1401 output_asm_insn ("movi %0,%1", operands);
1402 else if (CONST_OK_FOR_M (INTVAL (src)))
1403 output_asm_insn ("bgeni %0,%P1", operands);
1404 else if (CONST_OK_FOR_N (INTVAL (src)))
1405 output_asm_insn ("bmaski %0,%N1", operands);
1409 if (INTVAL (src) < 0)
1410 return "bmaski %R0,32";
1412 return "movi %R0,0";
1416 if (CONST_OK_FOR_I (INTVAL (src)))
1417 output_asm_insn ("movi %R0,%1", operands);
1418 else if (CONST_OK_FOR_M (INTVAL (src)))
1419 output_asm_insn ("bgeni %R0,%P1", operands);
1420 else if (CONST_OK_FOR_N (INTVAL (src)))
1421 output_asm_insn ("bmaski %R0,%N1", operands);
1425 if (INTVAL (src) < 0)
1426 return "bmaski %0,32";
1434 else if (GET_CODE (dst) == MEM && GET_CODE (src) == REG)
1435 return "stw\t%1,%0\n\tstw\t%R1,%R0";
1440 /* Predicates used by the templates. */
1443 mcore_arith_S_operand (rtx op)
1445 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_M (~INTVAL (op)))
1451 /* Expand insert bit field. BRC */
1454 mcore_expand_insv (rtx operands[])
1456 int width = INTVAL (operands[1]);
1457 int posn = INTVAL (operands[2]);
1459 rtx mreg, sreg, ereg;
1461 /* To get width 1 insv, the test in store_bit_field() (expmed.c, line 191)
1462 for width==1 must be removed. Look around line 368. This is something
1463 we really want the md part to do. */
1464 if (width == 1 && GET_CODE (operands[3]) == CONST_INT)
1466 /* Do directly with bseti or bclri. */
1467 /* RBE: 2/97 consider only low bit of constant. */
1468 if ((INTVAL (operands[3]) & 1) == 0)
1470 mask = ~(1 << posn);
1471 emit_insn (gen_rtx_SET (SImode, operands[0],
1472 gen_rtx_AND (SImode, operands[0], GEN_INT (mask))));
1477 emit_insn (gen_rtx_SET (SImode, operands[0],
1478 gen_rtx_IOR (SImode, operands[0], GEN_INT (mask))));
1484 /* Look at some bit-field placements that we aren't interested
1485 in handling ourselves, unless specifically directed to do so. */
1486 if (! TARGET_W_FIELD)
1487 return 0; /* Generally, give up about now. */
1489 if (width == 8 && posn % 8 == 0)
1490 /* Byte sized and aligned; let caller break it up. */
1493 if (width == 16 && posn % 16 == 0)
1494 /* Short sized and aligned; let caller break it up. */
1497 /* The general case - we can do this a little bit better than what the
1498 machine independent part tries. This will get rid of all the subregs
1499 that mess up constant folding in combine when working with relaxed
1502 /* If setting the entire field, do it directly. */
1503 if (GET_CODE (operands[3]) == CONST_INT
1504 && INTVAL (operands[3]) == ((1 << width) - 1))
1506 mreg = force_reg (SImode, GEN_INT (INTVAL (operands[3]) << posn));
1507 emit_insn (gen_rtx_SET (SImode, operands[0],
1508 gen_rtx_IOR (SImode, operands[0], mreg)));
1512 /* Generate the clear mask. */
1513 mreg = force_reg (SImode, GEN_INT (~(((1 << width) - 1) << posn)));
1515 /* Clear the field, to overlay it later with the source. */
1516 emit_insn (gen_rtx_SET (SImode, operands[0],
1517 gen_rtx_AND (SImode, operands[0], mreg)));
1519 /* If the source is constant 0, we've nothing to add back. */
1520 if (GET_CODE (operands[3]) == CONST_INT && INTVAL (operands[3]) == 0)
1523 /* XXX: Should we worry about more games with constant values?
1524 We've covered the high profile: set/clear single-bit and many-bit
1525 fields. How often do we see "arbitrary bit pattern" constants? */
1526 sreg = copy_to_mode_reg (SImode, operands[3]);
1528 /* Extract src as same width as dst (needed for signed values). We
1529 always have to do this since we widen everything to SImode.
1530 We don't have to mask if we're shifting this up against the
1531 MSB of the register (e.g., the shift will push out any hi-order
1533 if (width + posn != (int) GET_MODE_SIZE (SImode))
1535 ereg = force_reg (SImode, GEN_INT ((1 << width) - 1));
1536 emit_insn (gen_rtx_SET (SImode, sreg,
1537 gen_rtx_AND (SImode, sreg, ereg)));
1540 /* Insert source value in dest. */
1542 emit_insn (gen_rtx_SET (SImode, sreg,
1543 gen_rtx_ASHIFT (SImode, sreg, GEN_INT (posn))));
1545 emit_insn (gen_rtx_SET (SImode, operands[0],
1546 gen_rtx_IOR (SImode, operands[0], sreg)));
1551 /* ??? Block move stuff stolen from m88k. This code has not been
1552 verified for correctness. */
1554 /* Emit code to perform a block move. Choose the best method.
1556 OPERANDS[0] is the destination.
1557 OPERANDS[1] is the source.
1558 OPERANDS[2] is the size.
1559 OPERANDS[3] is the alignment safe to use. */
1561 /* Emit code to perform a block move with an offset sequence of ldw/st
1562 instructions (..., ldw 0, stw 1, ldw 1, stw 0, ...). SIZE and ALIGN are
1563 known constants. DEST and SRC are registers. OFFSET is the known
1564 starting point for the output pattern. */
1566 static const enum machine_mode mode_from_align[] =
1568 VOIDmode, QImode, HImode, VOIDmode, SImode,
1572 block_move_sequence (rtx dst_mem, rtx src_mem, int size, int align)
1575 enum machine_mode mode[2];
1584 x = XEXP (dst_mem, 0);
1587 x = force_reg (Pmode, x);
1588 dst_mem = replace_equiv_address (dst_mem, x);
1591 x = XEXP (src_mem, 0);
1594 x = force_reg (Pmode, x);
1595 src_mem = replace_equiv_address (src_mem, x);
1598 active[0] = active[1] = false;
1609 next_amount = (size >= 4 ? 4 : (size >= 2 ? 2 : 1));
1610 next_amount = MIN (next_amount, align);
1612 amount[next] = next_amount;
1613 mode[next] = mode_from_align[next_amount];
1614 temp[next] = gen_reg_rtx (mode[next]);
1616 x = adjust_address (src_mem, mode[next], offset_ld);
1617 emit_insn (gen_rtx_SET (VOIDmode, temp[next], x));
1619 offset_ld += next_amount;
1620 size -= next_amount;
1621 active[next] = true;
1626 active[phase] = false;
1628 x = adjust_address (dst_mem, mode[phase], offset_st);
1629 emit_insn (gen_rtx_SET (VOIDmode, x, temp[phase]));
1631 offset_st += amount[phase];
1634 while (active[next]);
1638 mcore_expand_block_move (rtx *operands)
1640 HOST_WIDE_INT align, bytes, max;
1642 if (GET_CODE (operands[2]) != CONST_INT)
1645 bytes = INTVAL (operands[2]);
1646 align = INTVAL (operands[3]);
1675 block_move_sequence (operands[0], operands[1], bytes, align);
1683 /* Code to generate prologue and epilogue sequences. */
1684 static int number_of_regs_before_varargs;
1686 /* Set by TARGET_SETUP_INCOMING_VARARGS to indicate to prolog that this is
1687 for a varargs function. */
1688 static int current_function_anonymous_args;
1690 #define STACK_BYTES (STACK_BOUNDARY/BITS_PER_UNIT)
1691 #define STORE_REACH (64) /* Maximum displace of word store + 4. */
1692 #define ADDI_REACH (32) /* Maximum addi operand. */
1695 layout_mcore_frame (struct mcore_frame * infp)
1703 unsigned int growths;
1706 /* Might have to spill bytes to re-assemble a big argument that
1707 was passed partially in registers and partially on the stack. */
1708 nbytes = crtl->args.pretend_args_size;
1710 /* Determine how much space for spilled anonymous args (e.g., stdarg). */
1711 if (current_function_anonymous_args)
1712 nbytes += (NPARM_REGS - number_of_regs_before_varargs) * UNITS_PER_WORD;
1714 infp->arg_size = nbytes;
1716 /* How much space to save non-volatile registers we stomp. */
1717 infp->reg_mask = calc_live_regs (& n);
1718 infp->reg_size = n * 4;
1720 /* And the rest of it... locals and space for overflowed outbounds. */
1721 infp->local_size = get_frame_size ();
1722 infp->outbound_size = crtl->outgoing_args_size;
1724 /* Make sure we have a whole number of words for the locals. */
1725 if (infp->local_size % STACK_BYTES)
1726 infp->local_size = (infp->local_size + STACK_BYTES - 1) & ~ (STACK_BYTES -1);
1728 /* Only thing we know we have to pad is the outbound space, since
1729 we've aligned our locals assuming that base of locals is aligned. */
1730 infp->pad_local = 0;
1732 infp->pad_outbound = 0;
1733 if (infp->outbound_size % STACK_BYTES)
1734 infp->pad_outbound = STACK_BYTES - (infp->outbound_size % STACK_BYTES);
1736 /* Now we see how we want to stage the prologue so that it does
1737 the most appropriate stack growth and register saves to either:
1739 (2) reduce instruction space, or
1740 (3) reduce stack space. */
1741 for (i = 0; i < ARRAY_SIZE (infp->growth); i++)
1742 infp->growth[i] = 0;
1744 regarg = infp->reg_size + infp->arg_size;
1745 localregarg = infp->local_size + regarg;
1746 outbounds = infp->outbound_size + infp->pad_outbound;
1749 /* XXX: Consider one where we consider localregarg + outbound too! */
1751 /* Frame of <= 32 bytes and using stm would get <= 2 registers.
1752 use stw's with offsets and buy the frame in one shot. */
1753 if (localregarg <= ADDI_REACH
1754 && (infp->reg_size <= 8 || (infp->reg_mask & 0xc000) != 0xc000))
1756 /* Make sure we'll be aligned. */
1757 if (localregarg % STACK_BYTES)
1758 infp->pad_reg = STACK_BYTES - (localregarg % STACK_BYTES);
1760 step = localregarg + infp->pad_reg;
1761 infp->reg_offset = infp->local_size;
1763 if (outbounds + step <= ADDI_REACH && !frame_pointer_needed)
1766 infp->reg_offset += outbounds;
1770 infp->arg_offset = step - 4;
1771 infp->growth[growths++] = step;
1772 infp->reg_growth = growths;
1773 infp->local_growth = growths;
1775 /* If we haven't already folded it in. */
1777 infp->growth[growths++] = outbounds;
1782 /* Frame can't be done with a single subi, but can be done with 2
1783 insns. If the 'stm' is getting <= 2 registers, we use stw's and
1784 shift some of the stack purchase into the first subi, so both are
1785 single instructions. */
1786 if (localregarg <= STORE_REACH
1787 && (infp->local_size > ADDI_REACH)
1788 && (infp->reg_size <= 8 || (infp->reg_mask & 0xc000) != 0xc000))
1792 /* Make sure we'll be aligned; use either pad_reg or pad_local. */
1793 if (localregarg % STACK_BYTES)
1794 infp->pad_reg = STACK_BYTES - (localregarg % STACK_BYTES);
1796 all = localregarg + infp->pad_reg + infp->pad_local;
1797 step = ADDI_REACH; /* As much up front as we can. */
1801 /* XXX: Consider whether step will still be aligned; we believe so. */
1802 infp->arg_offset = step - 4;
1803 infp->growth[growths++] = step;
1804 infp->reg_growth = growths;
1805 infp->reg_offset = step - infp->pad_reg - infp->reg_size;
1808 /* Can we fold in any space required for outbounds? */
1809 if (outbounds + all <= ADDI_REACH && !frame_pointer_needed)
1815 /* Get the rest of the locals in place. */
1817 infp->growth[growths++] = step;
1818 infp->local_growth = growths;
1821 gcc_assert (all == 0);
1823 /* Finish off if we need to do so. */
1825 infp->growth[growths++] = outbounds;
1830 /* Registers + args is nicely aligned, so we'll buy that in one shot.
1831 Then we buy the rest of the frame in 1 or 2 steps depending on
1832 whether we need a frame pointer. */
1833 if ((regarg % STACK_BYTES) == 0)
1835 infp->growth[growths++] = regarg;
1836 infp->reg_growth = growths;
1837 infp->arg_offset = regarg - 4;
1838 infp->reg_offset = 0;
1840 if (infp->local_size % STACK_BYTES)
1841 infp->pad_local = STACK_BYTES - (infp->local_size % STACK_BYTES);
1843 step = infp->local_size + infp->pad_local;
1845 if (!frame_pointer_needed)
1851 infp->growth[growths++] = step;
1852 infp->local_growth = growths;
1854 /* If there's any left to be done. */
1856 infp->growth[growths++] = outbounds;
1861 /* XXX: optimizations that we'll want to play with....
1862 -- regarg is not aligned, but it's a small number of registers;
1863 use some of localsize so that regarg is aligned and then
1864 save the registers. */
1866 /* Simple encoding; plods down the stack buying the pieces as it goes.
1867 -- does not optimize space consumption.
1868 -- does not attempt to optimize instruction counts.
1869 -- but it is safe for all alignments. */
1870 if (regarg % STACK_BYTES != 0)
1871 infp->pad_reg = STACK_BYTES - (regarg % STACK_BYTES);
1873 infp->growth[growths++] = infp->arg_size + infp->reg_size + infp->pad_reg;
1874 infp->reg_growth = growths;
1875 infp->arg_offset = infp->growth[0] - 4;
1876 infp->reg_offset = 0;
1878 if (frame_pointer_needed)
1880 if (infp->local_size % STACK_BYTES != 0)
1881 infp->pad_local = STACK_BYTES - (infp->local_size % STACK_BYTES);
1883 infp->growth[growths++] = infp->local_size + infp->pad_local;
1884 infp->local_growth = growths;
1886 infp->growth[growths++] = outbounds;
1890 if ((infp->local_size + outbounds) % STACK_BYTES != 0)
1891 infp->pad_local = STACK_BYTES - ((infp->local_size + outbounds) % STACK_BYTES);
1893 infp->growth[growths++] = infp->local_size + infp->pad_local + outbounds;
1894 infp->local_growth = growths;
1897 /* Anything else that we've forgotten?, plus a few consistency checks. */
1899 gcc_assert (infp->reg_offset >= 0);
1900 gcc_assert (growths <= MAX_STACK_GROWS);
1902 for (i = 0; i < growths; i++)
1903 gcc_assert (!(infp->growth[i] % STACK_BYTES));
1906 /* Define the offset between two registers, one to be eliminated, and
1907 the other its replacement, at the start of a routine. */
1910 mcore_initial_elimination_offset (int from, int to)
1914 struct mcore_frame fi;
1916 layout_mcore_frame (& fi);
1919 above_frame = fi.local_size + fi.pad_local + fi.reg_size + fi.pad_reg;
1921 below_frame = fi.outbound_size + fi.pad_outbound;
1923 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
1926 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
1927 return above_frame + below_frame;
1929 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
1935 /* Keep track of some information about varargs for the prolog. */
1938 mcore_setup_incoming_varargs (CUMULATIVE_ARGS *args_so_far,
1939 enum machine_mode mode, tree type,
1940 int * ptr_pretend_size ATTRIBUTE_UNUSED,
1941 int second_time ATTRIBUTE_UNUSED)
1943 current_function_anonymous_args = 1;
1945 /* We need to know how many argument registers are used before
1946 the varargs start, so that we can push the remaining argument
1947 registers during the prologue. */
1948 number_of_regs_before_varargs = *args_so_far + mcore_num_arg_regs (mode, type);
1950 /* There is a bug somewhere in the arg handling code.
1951 Until I can find it this workaround always pushes the
1952 last named argument onto the stack. */
1953 number_of_regs_before_varargs = *args_so_far;
1955 /* The last named argument may be split between argument registers
1956 and the stack. Allow for this here. */
1957 if (number_of_regs_before_varargs > NPARM_REGS)
1958 number_of_regs_before_varargs = NPARM_REGS;
1962 mcore_expand_prolog (void)
1964 struct mcore_frame fi;
1965 int space_allocated = 0;
1968 /* Find out what we're doing. */
1969 layout_mcore_frame (&fi);
1971 space_allocated = fi.arg_size + fi.reg_size + fi.local_size +
1972 fi.outbound_size + fi.pad_outbound + fi.pad_local + fi.pad_reg;
1976 /* Emit a symbol for this routine's frame size. */
1979 x = DECL_RTL (current_function_decl);
1981 gcc_assert (GET_CODE (x) == MEM);
1985 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1987 free (mcore_current_function_name);
1989 mcore_current_function_name = xstrdup (XSTR (x, 0));
1991 ASM_OUTPUT_CG_NODE (asm_out_file, mcore_current_function_name, space_allocated);
1993 if (cfun->calls_alloca)
1994 ASM_OUTPUT_CG_EDGE (asm_out_file, mcore_current_function_name, "alloca", 1);
1997 We're looking at how the 8byte alignment affects stack layout
1998 and where we had to pad things. This emits information we can
1999 extract which tells us about frame sizes and the like. */
2000 fprintf (asm_out_file,
2001 "\t.equ\t__$frame$info$_%s_$_%d_%d_x%x_%d_%d_%d,0\n",
2002 mcore_current_function_name,
2003 fi.arg_size, fi.reg_size, fi.reg_mask,
2004 fi.local_size, fi.outbound_size,
2005 frame_pointer_needed);
2008 if (mcore_naked_function_p ())
2011 /* Handle stdarg+regsaves in one shot: can't be more than 64 bytes. */
2012 output_stack_adjust (-1, fi.growth[growth++]); /* Grows it. */
2014 /* If we have a parameter passed partially in regs and partially in memory,
2015 the registers will have been stored to memory already in function.c. So
2016 we only need to do something here for varargs functions. */
2017 if (fi.arg_size != 0 && crtl->args.pretend_args_size == 0)
2020 int rn = FIRST_PARM_REG + NPARM_REGS - 1;
2021 int remaining = fi.arg_size;
2023 for (offset = fi.arg_offset; remaining >= 4; offset -= 4, rn--, remaining -= 4)
2025 emit_insn (gen_movsi
2026 (gen_rtx_MEM (SImode,
2027 plus_constant (stack_pointer_rtx, offset)),
2028 gen_rtx_REG (SImode, rn)));
2032 /* Do we need another stack adjustment before we do the register saves? */
2033 if (growth < fi.reg_growth)
2034 output_stack_adjust (-1, fi.growth[growth++]); /* Grows it. */
2036 if (fi.reg_size != 0)
2039 int offs = fi.reg_offset;
2041 for (i = 15; i >= 0; i--)
2043 if (offs == 0 && i == 15 && ((fi.reg_mask & 0xc000) == 0xc000))
2047 while (fi.reg_mask & (1 << first_reg))
2051 emit_insn (gen_store_multiple (gen_rtx_MEM (SImode, stack_pointer_rtx),
2052 gen_rtx_REG (SImode, first_reg),
2053 GEN_INT (16 - first_reg)));
2055 i -= (15 - first_reg);
2056 offs += (16 - first_reg) * 4;
2058 else if (fi.reg_mask & (1 << i))
2060 emit_insn (gen_movsi
2061 (gen_rtx_MEM (SImode,
2062 plus_constant (stack_pointer_rtx, offs)),
2063 gen_rtx_REG (SImode, i)));
2069 /* Figure the locals + outbounds. */
2070 if (frame_pointer_needed)
2072 /* If we haven't already purchased to 'fp'. */
2073 if (growth < fi.local_growth)
2074 output_stack_adjust (-1, fi.growth[growth++]); /* Grows it. */
2076 emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx));
2078 /* ... and then go any remaining distance for outbounds, etc. */
2079 if (fi.growth[growth])
2080 output_stack_adjust (-1, fi.growth[growth++]);
2084 if (growth < fi.local_growth)
2085 output_stack_adjust (-1, fi.growth[growth++]); /* Grows it. */
2086 if (fi.growth[growth])
2087 output_stack_adjust (-1, fi.growth[growth++]);
2092 mcore_expand_epilog (void)
2094 struct mcore_frame fi;
2097 int growth = MAX_STACK_GROWS - 1 ;
2100 /* Find out what we're doing. */
2101 layout_mcore_frame(&fi);
2103 if (mcore_naked_function_p ())
2106 /* If we had a frame pointer, restore the sp from that. */
2107 if (frame_pointer_needed)
2109 emit_insn (gen_movsi (stack_pointer_rtx, frame_pointer_rtx));
2110 growth = fi.local_growth - 1;
2114 /* XXX: while loop should accumulate and do a single sell. */
2115 while (growth >= fi.local_growth)
2117 if (fi.growth[growth] != 0)
2118 output_stack_adjust (1, fi.growth[growth]);
2123 /* Make sure we've shrunk stack back to the point where the registers
2124 were laid down. This is typically 0/1 iterations. Then pull the
2125 register save information back off the stack. */
2126 while (growth >= fi.reg_growth)
2127 output_stack_adjust ( 1, fi.growth[growth--]);
2129 offs = fi.reg_offset;
2131 for (i = 15; i >= 0; i--)
2133 if (offs == 0 && i == 15 && ((fi.reg_mask & 0xc000) == 0xc000))
2137 /* Find the starting register. */
2140 while (fi.reg_mask & (1 << first_reg))
2145 emit_insn (gen_load_multiple (gen_rtx_REG (SImode, first_reg),
2146 gen_rtx_MEM (SImode, stack_pointer_rtx),
2147 GEN_INT (16 - first_reg)));
2149 i -= (15 - first_reg);
2150 offs += (16 - first_reg) * 4;
2152 else if (fi.reg_mask & (1 << i))
2154 emit_insn (gen_movsi
2155 (gen_rtx_REG (SImode, i),
2156 gen_rtx_MEM (SImode,
2157 plus_constant (stack_pointer_rtx, offs))));
2162 /* Give back anything else. */
2163 /* XXX: Should accumulate total and then give it back. */
2165 output_stack_adjust ( 1, fi.growth[growth--]);
2168 /* This code is borrowed from the SH port. */
2170 /* The MCORE cannot load a large constant into a register, constants have to
2171 come from a pc relative load. The reference of a pc relative load
2172 instruction must be less than 1k in front of the instruction. This
2173 means that we often have to dump a constant inside a function, and
2174 generate code to branch around it.
2176 It is important to minimize this, since the branches will slow things
2177 down and make things bigger.
2179 Worst case code looks like:
2195 We fix this by performing a scan before scheduling, which notices which
2196 instructions need to have their operands fetched from the constant table
2197 and builds the table.
2201 scan, find an instruction which needs a pcrel move. Look forward, find the
2202 last barrier which is within MAX_COUNT bytes of the requirement.
2203 If there isn't one, make one. Process all the instructions between
2204 the find and the barrier.
2206 In the above example, we can tell that L3 is within 1k of L1, so
2207 the first move can be shrunk from the 2 insn+constant sequence into
2208 just 1 insn, and the constant moved to L3 to make:
2218 Then the second move becomes the target for the shortening process. */
2222 rtx value; /* Value in table. */
2223 rtx label; /* Label of value. */
2226 /* The maximum number of constants that can fit into one pool, since
2227 the pc relative range is 0...1020 bytes and constants are at least 4
2228 bytes long. We subtract 4 from the range to allow for the case where
2229 we need to add a branch/align before the constant pool. */
2231 #define MAX_COUNT 1016
2232 #define MAX_POOL_SIZE (MAX_COUNT/4)
2233 static pool_node pool_vector[MAX_POOL_SIZE];
2234 static int pool_size;
2236 /* Dump out any constants accumulated in the final pass. These
2237 will only be labels. */
2240 mcore_output_jump_label_table (void)
2246 fprintf (asm_out_file, "\t.align 2\n");
2248 for (i = 0; i < pool_size; i++)
2250 pool_node * p = pool_vector + i;
2252 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (p->label));
2254 output_asm_insn (".long %0", &p->value);
2263 /* Check whether insn is a candidate for a conditional. */
2266 is_cond_candidate (rtx insn)
2268 /* The only things we conditionalize are those that can be directly
2269 changed into a conditional. Only bother with SImode items. If
2270 we wanted to be a little more aggressive, we could also do other
2271 modes such as DImode with reg-reg move or load 0. */
2272 if (GET_CODE (insn) == INSN)
2274 rtx pat = PATTERN (insn);
2277 if (GET_CODE (pat) != SET)
2280 dst = XEXP (pat, 0);
2282 if ((GET_CODE (dst) != REG &&
2283 GET_CODE (dst) != SUBREG) ||
2284 GET_MODE (dst) != SImode)
2287 src = XEXP (pat, 1);
2289 if ((GET_CODE (src) == REG ||
2290 (GET_CODE (src) == SUBREG &&
2291 GET_CODE (SUBREG_REG (src)) == REG)) &&
2292 GET_MODE (src) == SImode)
2293 return COND_MOV_INSN;
2294 else if (GET_CODE (src) == CONST_INT &&
2296 return COND_CLR_INSN;
2297 else if (GET_CODE (src) == PLUS &&
2298 (GET_CODE (XEXP (src, 0)) == REG ||
2299 (GET_CODE (XEXP (src, 0)) == SUBREG &&
2300 GET_CODE (SUBREG_REG (XEXP (src, 0))) == REG)) &&
2301 GET_MODE (XEXP (src, 0)) == SImode &&
2302 GET_CODE (XEXP (src, 1)) == CONST_INT &&
2303 INTVAL (XEXP (src, 1)) == 1)
2304 return COND_INC_INSN;
2305 else if (((GET_CODE (src) == MINUS &&
2306 GET_CODE (XEXP (src, 1)) == CONST_INT &&
2307 INTVAL( XEXP (src, 1)) == 1) ||
2308 (GET_CODE (src) == PLUS &&
2309 GET_CODE (XEXP (src, 1)) == CONST_INT &&
2310 INTVAL (XEXP (src, 1)) == -1)) &&
2311 (GET_CODE (XEXP (src, 0)) == REG ||
2312 (GET_CODE (XEXP (src, 0)) == SUBREG &&
2313 GET_CODE (SUBREG_REG (XEXP (src, 0))) == REG)) &&
2314 GET_MODE (XEXP (src, 0)) == SImode)
2315 return COND_DEC_INSN;
2317 /* Some insns that we don't bother with:
2318 (set (rx:DI) (ry:DI))
2319 (set (rx:DI) (const_int 0))
2323 else if (GET_CODE (insn) == JUMP_INSN &&
2324 GET_CODE (PATTERN (insn)) == SET &&
2325 GET_CODE (XEXP (PATTERN (insn), 1)) == LABEL_REF)
2326 return COND_BRANCH_INSN;
2331 /* Emit a conditional version of insn and replace the old insn with the
2332 new one. Return the new insn if emitted. */
2335 emit_new_cond_insn (rtx insn, int cond)
2341 if ((num = is_cond_candidate (insn)) == COND_NO)
2344 pat = PATTERN (insn);
2346 if (GET_CODE (insn) == INSN)
2348 dst = SET_DEST (pat);
2349 src = SET_SRC (pat);
2353 dst = JUMP_LABEL (insn);
2362 c_insn = gen_movt0 (dst, src, dst);
2364 c_insn = gen_movt0 (dst, dst, src);
2369 c_insn = gen_incscc (dst, dst);
2371 c_insn = gen_incscc_false (dst, dst);
2376 c_insn = gen_decscc (dst, dst);
2378 c_insn = gen_decscc_false (dst, dst);
2381 case COND_BRANCH_INSN:
2383 c_insn = gen_branch_true (dst);
2385 c_insn = gen_branch_false (dst);
2392 /* Only copy the notes if they exist. */
2393 if (rtx_length [GET_CODE (c_insn)] >= 7 && rtx_length [GET_CODE (insn)] >= 7)
2395 /* We really don't need to bother with the notes and links at this
2396 point, but go ahead and save the notes. This will help is_dead()
2397 when applying peepholes (links don't matter since they are not
2398 used any more beyond this point for the mcore). */
2399 REG_NOTES (c_insn) = REG_NOTES (insn);
2402 if (num == COND_BRANCH_INSN)
2404 /* For jumps, we need to be a little bit careful and emit the new jump
2405 before the old one and to update the use count for the target label.
2406 This way, the barrier following the old (uncond) jump will get
2407 deleted, but the label won't. */
2408 c_insn = emit_jump_insn_before (c_insn, insn);
2410 ++ LABEL_NUSES (dst);
2412 JUMP_LABEL (c_insn) = dst;
2415 c_insn = emit_insn_after (c_insn, insn);
2422 /* Attempt to change a basic block into a series of conditional insns. This
2423 works by taking the branch at the end of the 1st block and scanning for the
2424 end of the 2nd block. If all instructions in the 2nd block have cond.
2425 versions and the label at the start of block 3 is the same as the target
2426 from the branch at block 1, then conditionalize all insn in block 2 using
2427 the inverse condition of the branch at block 1. (Note I'm bending the
2428 definition of basic block here.)
2432 bt L2 <-- end of block 1 (delete)
2435 br L3 <-- end of block 2
2437 L2: ... <-- start of block 3 (NUSES==1)
2448 we can delete the L2 label if NUSES==1 and re-apply the optimization
2449 starting at the last instruction of block 2. This may allow an entire
2450 if-then-else statement to be conditionalized. BRC */
2452 conditionalize_block (rtx first)
2456 rtx end_blk_1_br = 0;
2457 rtx end_blk_2_insn = 0;
2458 rtx start_blk_3_lab = 0;
2464 /* Check that the first insn is a candidate conditional jump. This is
2465 the one that we'll eliminate. If not, advance to the next insn to
2467 if (GET_CODE (first) != JUMP_INSN ||
2468 GET_CODE (PATTERN (first)) != SET ||
2469 GET_CODE (XEXP (PATTERN (first), 1)) != IF_THEN_ELSE)
2470 return NEXT_INSN (first);
2472 /* Extract some information we need. */
2473 end_blk_1_br = first;
2474 br_pat = PATTERN (end_blk_1_br);
2476 /* Complement the condition since we use the reverse cond. for the insns. */
2477 cond = (GET_CODE (XEXP (XEXP (br_pat, 1), 0)) == EQ);
2479 /* Determine what kind of branch we have. */
2480 if (GET_CODE (XEXP (XEXP (br_pat, 1), 1)) == LABEL_REF)
2482 /* A normal branch, so extract label out of first arm. */
2483 br_lab_num = CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (br_pat, 1), 1), 0));
2487 /* An inverse branch, so extract the label out of the 2nd arm
2488 and complement the condition. */
2490 br_lab_num = CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (br_pat, 1), 2), 0));
2493 /* Scan forward for the start of block 2: it must start with a
2494 label and that label must be the same as the branch target
2495 label from block 1. We don't care about whether block 2 actually
2496 ends with a branch or a label (an uncond. branch is
2497 conditionalizable). */
2498 for (insn = NEXT_INSN (first); insn; insn = NEXT_INSN (insn))
2502 code = GET_CODE (insn);
2504 /* Look for the label at the start of block 3. */
2505 if (code == CODE_LABEL && CODE_LABEL_NUMBER (insn) == br_lab_num)
2508 /* Skip barriers, notes, and conditionalizable insns. If the
2509 insn is not conditionalizable or makes this optimization fail,
2510 just return the next insn so we can start over from that point. */
2511 if (code != BARRIER && code != NOTE && !is_cond_candidate (insn))
2512 return NEXT_INSN (insn);
2514 /* Remember the last real insn before the label (i.e. end of block 2). */
2515 if (code == JUMP_INSN || code == INSN)
2518 end_blk_2_insn = insn;
2525 /* It is possible for this optimization to slow performance if the blocks
2526 are long. This really depends upon whether the branch is likely taken
2527 or not. If the branch is taken, we slow performance in many cases. But,
2528 if the branch is not taken, we always help performance (for a single
2529 block, but for a double block (i.e. when the optimization is re-applied)
2530 this is not true since the 'right thing' depends on the overall length of
2531 the collapsed block). As a compromise, don't apply this optimization on
2532 blocks larger than size 2 (unlikely for the mcore) when speed is important.
2533 the best threshold depends on the latencies of the instructions (i.e.,
2534 the branch penalty). */
2535 if (optimize > 1 && blk_size > 2)
2538 /* At this point, we've found the start of block 3 and we know that
2539 it is the destination of the branch from block 1. Also, all
2540 instructions in the block 2 are conditionalizable. So, apply the
2541 conditionalization and delete the branch. */
2542 start_blk_3_lab = insn;
2544 for (insn = NEXT_INSN (end_blk_1_br); insn != start_blk_3_lab;
2545 insn = NEXT_INSN (insn))
2549 if (INSN_DELETED_P (insn))
2552 /* Try to form a conditional variant of the instruction and emit it. */
2553 if ((newinsn = emit_new_cond_insn (insn, cond)))
2555 if (end_blk_2_insn == insn)
2556 end_blk_2_insn = newinsn;
2562 /* Note whether we will delete the label starting blk 3 when the jump
2563 gets deleted. If so, we want to re-apply this optimization at the
2564 last real instruction right before the label. */
2565 if (LABEL_NUSES (start_blk_3_lab) == 1)
2567 start_blk_3_lab = 0;
2570 /* ??? we probably should redistribute the death notes for this insn, esp.
2571 the death of cc, but it doesn't really matter this late in the game.
2572 The peepholes all use is_dead() which will find the correct death
2573 regardless of whether there is a note. */
2574 delete_insn (end_blk_1_br);
2576 if (! start_blk_3_lab)
2577 return end_blk_2_insn;
2579 /* Return the insn right after the label at the start of block 3. */
2580 return NEXT_INSN (start_blk_3_lab);
2583 /* Apply the conditionalization of blocks optimization. This is the
2584 outer loop that traverses through the insns scanning for a branch
2585 that signifies an opportunity to apply the optimization. Note that
2586 this optimization is applied late. If we could apply it earlier,
2587 say before cse 2, it may expose more optimization opportunities.
2588 but, the pay back probably isn't really worth the effort (we'd have
2589 to update all reg/flow/notes/links/etc to make it work - and stick it
2590 in before cse 2). */
2593 conditionalize_optimization (void)
2597 for (insn = get_insns (); insn; insn = conditionalize_block (insn))
2601 static int saved_warn_return_type = -1;
2602 static int saved_warn_return_type_count = 0;
2604 /* This is to handle loads from the constant pool. */
2609 /* Reset this variable. */
2610 current_function_anonymous_args = 0;
2612 /* Restore the warn_return_type if it has been altered. */
2613 if (saved_warn_return_type != -1)
2615 /* Only restore the value if we have reached another function.
2616 The test of warn_return_type occurs in final_function () in
2617 c-decl.c a long time after the code for the function is generated,
2618 so we need a counter to tell us when we have finished parsing that
2619 function and can restore the flag. */
2620 if (--saved_warn_return_type_count == 0)
2622 warn_return_type = saved_warn_return_type;
2623 saved_warn_return_type = -1;
2630 /* Conditionalize blocks where we can. */
2631 conditionalize_optimization ();
2633 /* Literal pool generation is now pushed off until the assembler. */
2637 /* Return true if X is something that can be moved directly into r15. */
2640 mcore_r15_operand_p (rtx x)
2642 switch (GET_CODE (x))
2645 return mcore_const_ok_for_inline (INTVAL (x));
2657 /* Implement SECONDARY_RELOAD_CLASS. If RCLASS contains r15, and we can't
2658 directly move X into it, use r1-r14 as a temporary. */
2661 mcore_secondary_reload_class (enum reg_class rclass,
2662 enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
2664 if (TEST_HARD_REG_BIT (reg_class_contents[rclass], 15)
2665 && !mcore_r15_operand_p (x))
2670 /* Return the reg_class to use when reloading the rtx X into the class
2671 RCLASS. If X is too complex to move directly into r15, prefer to
2672 use LRW_REGS instead. */
2675 mcore_reload_class (rtx x, enum reg_class rclass)
2677 if (reg_class_subset_p (LRW_REGS, rclass) && !mcore_r15_operand_p (x))
2683 /* Tell me if a pair of reg/subreg rtx's actually refer to the same
2684 register. Note that the current version doesn't worry about whether
2685 they are the same mode or note (e.g., a QImode in r2 matches an HImode
2686 in r2 matches an SImode in r2. Might think in the future about whether
2687 we want to be able to say something about modes. */
2690 mcore_is_same_reg (rtx x, rtx y)
2692 /* Strip any and all of the subreg wrappers. */
2693 while (GET_CODE (x) == SUBREG)
2696 while (GET_CODE (y) == SUBREG)
2699 if (GET_CODE(x) == REG && GET_CODE(y) == REG && REGNO(x) == REGNO(y))
2706 mcore_option_override (void)
2708 /* Only the m340 supports little endian code. */
2709 if (TARGET_LITTLE_END && ! TARGET_M340)
2710 target_flags |= MASK_M340;
2714 /* Compute the number of word sized registers needed to
2715 hold a function argument of mode MODE and type TYPE. */
2718 mcore_num_arg_regs (enum machine_mode mode, const_tree type)
2722 if (targetm.calls.must_pass_in_stack (mode, type))
2725 if (type && mode == BLKmode)
2726 size = int_size_in_bytes (type);
2728 size = GET_MODE_SIZE (mode);
2730 return ROUND_ADVANCE (size);
2734 handle_structs_in_regs (enum machine_mode mode, const_tree type, int reg)
2738 /* The MCore ABI defines that a structure whose size is not a whole multiple
2739 of bytes is passed packed into registers (or spilled onto the stack if
2740 not enough registers are available) with the last few bytes of the
2741 structure being packed, left-justified, into the last register/stack slot.
2742 GCC handles this correctly if the last word is in a stack slot, but we
2743 have to generate a special, PARALLEL RTX if the last word is in an
2744 argument register. */
2746 && TYPE_MODE (type) == BLKmode
2747 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
2748 && (size = int_size_in_bytes (type)) > UNITS_PER_WORD
2749 && (size % UNITS_PER_WORD != 0)
2750 && (reg + mcore_num_arg_regs (mode, type) <= (FIRST_PARM_REG + NPARM_REGS)))
2752 rtx arg_regs [NPARM_REGS];
2757 for (nregs = 0; size > 0; size -= UNITS_PER_WORD)
2760 gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, reg ++),
2761 GEN_INT (nregs * UNITS_PER_WORD));
2765 /* We assume here that NPARM_REGS == 6. The assert checks this. */
2766 gcc_assert (ARRAY_SIZE (arg_regs) == 6);
2767 rtvec = gen_rtvec (nregs, arg_regs[0], arg_regs[1], arg_regs[2],
2768 arg_regs[3], arg_regs[4], arg_regs[5]);
2770 result = gen_rtx_PARALLEL (mode, rtvec);
2774 return gen_rtx_REG (mode, reg);
2778 mcore_function_value (const_tree valtype, const_tree func)
2780 enum machine_mode mode;
2783 mode = TYPE_MODE (valtype);
2785 /* Since we promote return types, we must promote the mode here too. */
2786 mode = promote_function_mode (valtype, mode, &unsigned_p, func, 1);
2788 return handle_structs_in_regs (mode, valtype, FIRST_RET_REG);
2791 /* Define where to put the arguments to a function.
2792 Value is zero to push the argument on the stack,
2793 or a hard register in which to store the argument.
2795 MODE is the argument's machine mode.
2796 TYPE is the data type of the argument (as a tree).
2797 This is null for libcalls where that information may
2799 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2800 the preceding args and about the function being called.
2801 NAMED is nonzero if this argument is a named parameter
2802 (otherwise it is an extra parameter matching an ellipsis).
2804 On MCore the first args are normally in registers
2805 and the rest are pushed. Any arg that starts within the first
2806 NPARM_REGS words is at least partially passed in a register unless
2807 its data type forbids. */
2810 mcore_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
2811 const_tree type, bool named)
2815 if (! named || mode == VOIDmode)
2818 if (targetm.calls.must_pass_in_stack (mode, type))
2821 arg_reg = ROUND_REG (*cum, mode);
2823 if (arg_reg < NPARM_REGS)
2824 return handle_structs_in_regs (mode, type, FIRST_PARM_REG + arg_reg);
2830 mcore_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
2831 const_tree type, bool named ATTRIBUTE_UNUSED)
2833 *cum = (ROUND_REG (*cum, mode)
2834 + (int)named * mcore_num_arg_regs (mode, type));
2838 mcore_function_arg_boundary (enum machine_mode mode,
2839 const_tree type ATTRIBUTE_UNUSED)
2841 /* Doubles must be aligned to an 8 byte boundary. */
2842 return (mode != BLKmode && GET_MODE_SIZE (mode) == 8
2847 /* Returns the number of bytes of argument registers required to hold *part*
2848 of a parameter of machine mode MODE and type TYPE (which may be NULL if
2849 the type is not known). If the argument fits entirely in the argument
2850 registers, or entirely on the stack, then 0 is returned. CUM is the
2851 number of argument registers already used by earlier parameters to
2855 mcore_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
2856 tree type, bool named)
2858 int reg = ROUND_REG (*cum, mode);
2863 if (targetm.calls.must_pass_in_stack (mode, type))
2866 /* REG is not the *hardware* register number of the register that holds
2867 the argument, it is the *argument* register number. So for example,
2868 the first argument to a function goes in argument register 0, which
2869 translates (for the MCore) into hardware register 2. The second
2870 argument goes into argument register 1, which translates into hardware
2871 register 3, and so on. NPARM_REGS is the number of argument registers
2872 supported by the target, not the maximum hardware register number of
2874 if (reg >= NPARM_REGS)
2877 /* If the argument fits entirely in registers, return 0. */
2878 if (reg + mcore_num_arg_regs (mode, type) <= NPARM_REGS)
2881 /* The argument overflows the number of available argument registers.
2882 Compute how many argument registers have not yet been assigned to
2883 hold an argument. */
2884 reg = NPARM_REGS - reg;
2886 /* Return partially in registers and partially on the stack. */
2887 return reg * UNITS_PER_WORD;
2890 /* Return nonzero if SYMBOL is marked as being dllexport'd. */
2893 mcore_dllexport_name_p (const char * symbol)
2895 return symbol[0] == '@' && symbol[1] == 'e' && symbol[2] == '.';
2898 /* Return nonzero if SYMBOL is marked as being dllimport'd. */
2901 mcore_dllimport_name_p (const char * symbol)
2903 return symbol[0] == '@' && symbol[1] == 'i' && symbol[2] == '.';
2906 /* Mark a DECL as being dllexport'd. */
2909 mcore_mark_dllexport (tree decl)
2911 const char * oldname;
2916 rtlname = XEXP (DECL_RTL (decl), 0);
2918 if (GET_CODE (rtlname) == MEM)
2919 rtlname = XEXP (rtlname, 0);
2920 gcc_assert (GET_CODE (rtlname) == SYMBOL_REF);
2921 oldname = XSTR (rtlname, 0);
2923 if (mcore_dllexport_name_p (oldname))
2924 return; /* Already done. */
2926 newname = XALLOCAVEC (char, strlen (oldname) + 4);
2927 sprintf (newname, "@e.%s", oldname);
2929 /* We pass newname through get_identifier to ensure it has a unique
2930 address. RTL processing can sometimes peek inside the symbol ref
2931 and compare the string's addresses to see if two symbols are
2933 /* ??? At least I think that's why we do this. */
2934 idp = get_identifier (newname);
2936 XEXP (DECL_RTL (decl), 0) =
2937 gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (idp));
2940 /* Mark a DECL as being dllimport'd. */
2943 mcore_mark_dllimport (tree decl)
2945 const char * oldname;
2951 rtlname = XEXP (DECL_RTL (decl), 0);
2953 if (GET_CODE (rtlname) == MEM)
2954 rtlname = XEXP (rtlname, 0);
2955 gcc_assert (GET_CODE (rtlname) == SYMBOL_REF);
2956 oldname = XSTR (rtlname, 0);
2958 gcc_assert (!mcore_dllexport_name_p (oldname));
2959 if (mcore_dllimport_name_p (oldname))
2960 return; /* Already done. */
2962 /* ??? One can well ask why we're making these checks here,
2963 and that would be a good question. */
2965 /* Imported variables can't be initialized. */
2966 if (TREE_CODE (decl) == VAR_DECL
2967 && !DECL_VIRTUAL_P (decl)
2968 && DECL_INITIAL (decl))
2970 error ("initialized variable %q+D is marked dllimport", decl);
2974 /* `extern' needn't be specified with dllimport.
2975 Specify `extern' now and hope for the best. Sigh. */
2976 if (TREE_CODE (decl) == VAR_DECL
2977 /* ??? Is this test for vtables needed? */
2978 && !DECL_VIRTUAL_P (decl))
2980 DECL_EXTERNAL (decl) = 1;
2981 TREE_PUBLIC (decl) = 1;
2984 newname = XALLOCAVEC (char, strlen (oldname) + 11);
2985 sprintf (newname, "@i.__imp_%s", oldname);
2987 /* We pass newname through get_identifier to ensure it has a unique
2988 address. RTL processing can sometimes peek inside the symbol ref
2989 and compare the string's addresses to see if two symbols are
2991 /* ??? At least I think that's why we do this. */
2992 idp = get_identifier (newname);
2994 newrtl = gen_rtx_MEM (Pmode,
2995 gen_rtx_SYMBOL_REF (Pmode,
2996 IDENTIFIER_POINTER (idp)));
2997 XEXP (DECL_RTL (decl), 0) = newrtl;
3001 mcore_dllexport_p (tree decl)
3003 if ( TREE_CODE (decl) != VAR_DECL
3004 && TREE_CODE (decl) != FUNCTION_DECL)
3007 return lookup_attribute ("dllexport", DECL_ATTRIBUTES (decl)) != 0;
3011 mcore_dllimport_p (tree decl)
3013 if ( TREE_CODE (decl) != VAR_DECL
3014 && TREE_CODE (decl) != FUNCTION_DECL)
3017 return lookup_attribute ("dllimport", DECL_ATTRIBUTES (decl)) != 0;
3020 /* We must mark dll symbols specially. Definitions of dllexport'd objects
3021 install some info in the .drective (PE) or .exports (ELF) sections. */
3024 mcore_encode_section_info (tree decl, rtx rtl ATTRIBUTE_UNUSED, int first ATTRIBUTE_UNUSED)
3026 /* Mark the decl so we can tell from the rtl whether the object is
3027 dllexport'd or dllimport'd. */
3028 if (mcore_dllexport_p (decl))
3029 mcore_mark_dllexport (decl);
3030 else if (mcore_dllimport_p (decl))
3031 mcore_mark_dllimport (decl);
3033 /* It might be that DECL has already been marked as dllimport, but
3034 a subsequent definition nullified that. The attribute is gone
3035 but DECL_RTL still has @i.__imp_foo. We need to remove that. */
3036 else if ((TREE_CODE (decl) == FUNCTION_DECL
3037 || TREE_CODE (decl) == VAR_DECL)
3038 && DECL_RTL (decl) != NULL_RTX
3039 && GET_CODE (DECL_RTL (decl)) == MEM
3040 && GET_CODE (XEXP (DECL_RTL (decl), 0)) == MEM
3041 && GET_CODE (XEXP (XEXP (DECL_RTL (decl), 0), 0)) == SYMBOL_REF
3042 && mcore_dllimport_name_p (XSTR (XEXP (XEXP (DECL_RTL (decl), 0), 0), 0)))
3044 const char * oldname = XSTR (XEXP (XEXP (DECL_RTL (decl), 0), 0), 0);
3045 tree idp = get_identifier (oldname + 9);
3046 rtx newrtl = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (idp));
3048 XEXP (DECL_RTL (decl), 0) = newrtl;
3050 /* We previously set TREE_PUBLIC and DECL_EXTERNAL.
3051 ??? We leave these alone for now. */
3055 /* Undo the effects of the above. */
3058 mcore_strip_name_encoding (const char * str)
3060 return str + (str[0] == '@' ? 3 : 0);
3063 /* MCore specific attribute support.
3064 dllexport - for exporting a function/variable that will live in a dll
3065 dllimport - for importing a function/variable from a dll
3066 naked - do not create a function prologue/epilogue. */
3068 /* Handle a "naked" attribute; arguments as in
3069 struct attribute_spec.handler. */
3072 mcore_handle_naked_attribute (tree * node, tree name, tree args ATTRIBUTE_UNUSED,
3073 int flags ATTRIBUTE_UNUSED, bool * no_add_attrs)
3075 if (TREE_CODE (*node) == FUNCTION_DECL)
3077 /* PR14310 - don't complain about lack of return statement
3078 in naked functions. The solution here is a gross hack
3079 but this is the only way to solve the problem without
3080 adding a new feature to GCC. I did try submitting a patch
3081 that would add such a new feature, but it was (rightfully)
3082 rejected on the grounds that it was creeping featurism,
3083 so hence this code. */
3084 if (warn_return_type)
3086 saved_warn_return_type = warn_return_type;
3087 warn_return_type = 0;
3088 saved_warn_return_type_count = 2;
3090 else if (saved_warn_return_type_count)
3091 saved_warn_return_type_count = 2;
3095 warning (OPT_Wattributes, "%qE attribute only applies to functions",
3097 *no_add_attrs = true;
3103 /* ??? It looks like this is PE specific? Oh well, this is what the
3104 old code did as well. */
3107 mcore_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
3112 const char * prefix;
3114 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
3116 /* Strip off any encoding in name. */
3117 name = (* targetm.strip_name_encoding) (name);
3119 /* The object is put in, for example, section .text$foo.
3120 The linker will then ultimately place them in .text
3121 (everything from the $ on is stripped). */
3122 if (TREE_CODE (decl) == FUNCTION_DECL)
3124 /* For compatibility with EPOC, we ignore the fact that the
3125 section might have relocs against it. */
3126 else if (decl_readonly_section (decl, 0))
3131 len = strlen (name) + strlen (prefix);
3132 string = XALLOCAVEC (char, len + 1);
3134 sprintf (string, "%s%s", prefix, name);
3136 DECL_SECTION_NAME (decl) = build_string (len, string);
3140 mcore_naked_function_p (void)
3142 return lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl)) != NULL_TREE;
3145 #ifdef OBJECT_FORMAT_ELF
3147 mcore_asm_named_section (const char *name,
3148 unsigned int flags ATTRIBUTE_UNUSED,
3149 tree decl ATTRIBUTE_UNUSED)
3151 fprintf (asm_out_file, "\t.section %s\n", name);
3153 #endif /* OBJECT_FORMAT_ELF */
3155 /* Worker function for TARGET_ASM_EXTERNAL_LIBCALL. */
3158 mcore_external_libcall (rtx fun)
3160 fprintf (asm_out_file, "\t.import\t");
3161 assemble_name (asm_out_file, XSTR (fun, 0));
3162 fprintf (asm_out_file, "\n");
3165 /* Worker function for TARGET_RETURN_IN_MEMORY. */
3168 mcore_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
3170 const HOST_WIDE_INT size = int_size_in_bytes (type);
3171 return (size == -1 || size > 2 * UNITS_PER_WORD);
3174 /* Worker function for TARGET_ASM_TRAMPOLINE_TEMPLATE.
3175 Output assembler code for a block containing the constant parts
3176 of a trampoline, leaving space for the variable parts.
3178 On the MCore, the trampoline looks like:
3186 mcore_asm_trampoline_template (FILE *f)
3188 fprintf (f, "\t.short 0x7102\n");
3189 fprintf (f, "\t.short 0x7d02\n");
3190 fprintf (f, "\t.short 0x00cd\n");
3191 fprintf (f, "\t.short 0x1e00\n");
3192 fprintf (f, "\t.long 0\n");
3193 fprintf (f, "\t.long 0\n");
3196 /* Worker function for TARGET_TRAMPOLINE_INIT. */
3199 mcore_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
3201 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
3204 emit_block_move (m_tramp, assemble_trampoline_template (),
3205 GEN_INT (2*UNITS_PER_WORD), BLOCK_OP_NORMAL);
3207 mem = adjust_address (m_tramp, SImode, 8);
3208 emit_move_insn (mem, chain_value);
3209 mem = adjust_address (m_tramp, SImode, 12);
3210 emit_move_insn (mem, fnaddr);
3213 /* Implement TARGET_LEGITIMATE_CONSTANT_P
3215 On the MCore, allow anything but a double. */
3218 mcore_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
3220 return GET_CODE (x) != CONST_DOUBLE;