1 /* Definitions of target machine for GNU compiler.
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008,
4 Free Software Foundation, Inc.
5 Contributed by James E. Wilson <wilson@cygnus.com> and
6 David Mosberger <davidm@hpl.hp.com>.
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
43 #include "basic-block.h"
45 #include "diagnostic-core.h"
46 #include "sched-int.h"
49 #include "target-def.h"
50 #include "common/common-target.h"
53 #include "langhooks.h"
60 #include "tm-constrs.h"
61 #include "sel-sched.h"
66 /* This is used for communication between ASM_OUTPUT_LABEL and
67 ASM_OUTPUT_LABELREF. */
68 int ia64_asm_output_label = 0;
70 /* Register names for ia64_expand_prologue. */
71 static const char * const ia64_reg_numbers[96] =
72 { "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
73 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
74 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
75 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
76 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
77 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
78 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
79 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
80 "r96", "r97", "r98", "r99", "r100","r101","r102","r103",
81 "r104","r105","r106","r107","r108","r109","r110","r111",
82 "r112","r113","r114","r115","r116","r117","r118","r119",
83 "r120","r121","r122","r123","r124","r125","r126","r127"};
85 /* ??? These strings could be shared with REGISTER_NAMES. */
86 static const char * const ia64_input_reg_names[8] =
87 { "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7" };
89 /* ??? These strings could be shared with REGISTER_NAMES. */
90 static const char * const ia64_local_reg_names[80] =
91 { "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7",
92 "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15",
93 "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23",
94 "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31",
95 "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39",
96 "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47",
97 "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55",
98 "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63",
99 "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71",
100 "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79" };
102 /* ??? These strings could be shared with REGISTER_NAMES. */
103 static const char * const ia64_output_reg_names[8] =
104 { "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7" };
106 /* Variables which are this size or smaller are put in the sdata/sbss
109 unsigned int ia64_section_threshold;
111 /* The following variable is used by the DFA insn scheduler. The value is
112 TRUE if we do insn bundling instead of insn scheduling. */
124 number_of_ia64_frame_regs
127 /* Structure to be filled in by ia64_compute_frame_size with register
128 save masks and offsets for the current function. */
130 struct ia64_frame_info
132 HOST_WIDE_INT total_size; /* size of the stack frame, not including
133 the caller's scratch area. */
134 HOST_WIDE_INT spill_cfa_off; /* top of the reg spill area from the cfa. */
135 HOST_WIDE_INT spill_size; /* size of the gr/br/fr spill area. */
136 HOST_WIDE_INT extra_spill_size; /* size of spill area for others. */
137 HARD_REG_SET mask; /* mask of saved registers. */
138 unsigned int gr_used_mask; /* mask of registers in use as gr spill
139 registers or long-term scratches. */
140 int n_spilled; /* number of spilled registers. */
141 int r[number_of_ia64_frame_regs]; /* Frame related registers. */
142 int n_input_regs; /* number of input registers used. */
143 int n_local_regs; /* number of local registers used. */
144 int n_output_regs; /* number of output registers used. */
145 int n_rotate_regs; /* number of rotating registers used. */
147 char need_regstk; /* true if a .regstk directive needed. */
148 char initialized; /* true if the data is finalized. */
151 /* Current frame information calculated by ia64_compute_frame_size. */
152 static struct ia64_frame_info current_frame_info;
153 /* The actual registers that are emitted. */
154 static int emitted_frame_related_regs[number_of_ia64_frame_regs];
156 static int ia64_first_cycle_multipass_dfa_lookahead (void);
157 static void ia64_dependencies_evaluation_hook (rtx, rtx);
158 static void ia64_init_dfa_pre_cycle_insn (void);
159 static rtx ia64_dfa_pre_cycle_insn (void);
160 static int ia64_first_cycle_multipass_dfa_lookahead_guard (rtx);
161 static bool ia64_first_cycle_multipass_dfa_lookahead_guard_spec (const_rtx);
162 static int ia64_dfa_new_cycle (FILE *, int, rtx, int, int, int *);
163 static void ia64_h_i_d_extended (void);
164 static void * ia64_alloc_sched_context (void);
165 static void ia64_init_sched_context (void *, bool);
166 static void ia64_set_sched_context (void *);
167 static void ia64_clear_sched_context (void *);
168 static void ia64_free_sched_context (void *);
169 static int ia64_mode_to_int (enum machine_mode);
170 static void ia64_set_sched_flags (spec_info_t);
171 static ds_t ia64_get_insn_spec_ds (rtx);
172 static ds_t ia64_get_insn_checked_ds (rtx);
173 static bool ia64_skip_rtx_p (const_rtx);
174 static int ia64_speculate_insn (rtx, ds_t, rtx *);
175 static bool ia64_needs_block_p (int);
176 static rtx ia64_gen_spec_check (rtx, rtx, ds_t);
177 static int ia64_spec_check_p (rtx);
178 static int ia64_spec_check_src_p (rtx);
179 static rtx gen_tls_get_addr (void);
180 static rtx gen_thread_pointer (void);
181 static int find_gr_spill (enum ia64_frame_regs, int);
182 static int next_scratch_gr_reg (void);
183 static void mark_reg_gr_used_mask (rtx, void *);
184 static void ia64_compute_frame_size (HOST_WIDE_INT);
185 static void setup_spill_pointers (int, rtx, HOST_WIDE_INT);
186 static void finish_spill_pointers (void);
187 static rtx spill_restore_mem (rtx, HOST_WIDE_INT);
188 static void do_spill (rtx (*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT, rtx);
189 static void do_restore (rtx (*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT);
190 static rtx gen_movdi_x (rtx, rtx, rtx);
191 static rtx gen_fr_spill_x (rtx, rtx, rtx);
192 static rtx gen_fr_restore_x (rtx, rtx, rtx);
194 static void ia64_option_override (void);
195 static bool ia64_can_eliminate (const int, const int);
196 static enum machine_mode hfa_element_mode (const_tree, bool);
197 static void ia64_setup_incoming_varargs (cumulative_args_t, enum machine_mode,
199 static int ia64_arg_partial_bytes (cumulative_args_t, enum machine_mode,
201 static rtx ia64_function_arg_1 (cumulative_args_t, enum machine_mode,
202 const_tree, bool, bool);
203 static rtx ia64_function_arg (cumulative_args_t, enum machine_mode,
205 static rtx ia64_function_incoming_arg (cumulative_args_t,
206 enum machine_mode, const_tree, bool);
207 static void ia64_function_arg_advance (cumulative_args_t, enum machine_mode,
209 static unsigned int ia64_function_arg_boundary (enum machine_mode,
211 static bool ia64_function_ok_for_sibcall (tree, tree);
212 static bool ia64_return_in_memory (const_tree, const_tree);
213 static rtx ia64_function_value (const_tree, const_tree, bool);
214 static rtx ia64_libcall_value (enum machine_mode, const_rtx);
215 static bool ia64_function_value_regno_p (const unsigned int);
216 static int ia64_register_move_cost (enum machine_mode, reg_class_t,
218 static int ia64_memory_move_cost (enum machine_mode mode, reg_class_t,
220 static bool ia64_rtx_costs (rtx, int, int, int, int *, bool);
221 static int ia64_unspec_may_trap_p (const_rtx, unsigned);
222 static void fix_range (const char *);
223 static struct machine_function * ia64_init_machine_status (void);
224 static void emit_insn_group_barriers (FILE *);
225 static void emit_all_insn_group_barriers (FILE *);
226 static void final_emit_insn_group_barriers (FILE *);
227 static void emit_predicate_relation_info (void);
228 static void ia64_reorg (void);
229 static bool ia64_in_small_data_p (const_tree);
230 static void process_epilogue (FILE *, rtx, bool, bool);
232 static bool ia64_assemble_integer (rtx, unsigned int, int);
233 static void ia64_output_function_prologue (FILE *, HOST_WIDE_INT);
234 static void ia64_output_function_epilogue (FILE *, HOST_WIDE_INT);
235 static void ia64_output_function_end_prologue (FILE *);
237 static void ia64_print_operand (FILE *, rtx, int);
238 static void ia64_print_operand_address (FILE *, rtx);
239 static bool ia64_print_operand_punct_valid_p (unsigned char code);
241 static int ia64_issue_rate (void);
242 static int ia64_adjust_cost_2 (rtx, int, rtx, int, dw_t);
243 static void ia64_sched_init (FILE *, int, int);
244 static void ia64_sched_init_global (FILE *, int, int);
245 static void ia64_sched_finish_global (FILE *, int);
246 static void ia64_sched_finish (FILE *, int);
247 static int ia64_dfa_sched_reorder (FILE *, int, rtx *, int *, int, int);
248 static int ia64_sched_reorder (FILE *, int, rtx *, int *, int);
249 static int ia64_sched_reorder2 (FILE *, int, rtx *, int *, int);
250 static int ia64_variable_issue (FILE *, int, rtx, int);
252 static void ia64_asm_unwind_emit (FILE *, rtx);
253 static void ia64_asm_emit_except_personality (rtx);
254 static void ia64_asm_init_sections (void);
256 static enum unwind_info_type ia64_debug_unwind_info (void);
258 static struct bundle_state *get_free_bundle_state (void);
259 static void free_bundle_state (struct bundle_state *);
260 static void initiate_bundle_states (void);
261 static void finish_bundle_states (void);
262 static unsigned bundle_state_hash (const void *);
263 static int bundle_state_eq_p (const void *, const void *);
264 static int insert_bundle_state (struct bundle_state *);
265 static void initiate_bundle_state_table (void);
266 static void finish_bundle_state_table (void);
267 static int try_issue_nops (struct bundle_state *, int);
268 static int try_issue_insn (struct bundle_state *, rtx);
269 static void issue_nops_and_insn (struct bundle_state *, int, rtx, int, int);
270 static int get_max_pos (state_t);
271 static int get_template (state_t, int);
273 static rtx get_next_important_insn (rtx, rtx);
274 static bool important_for_bundling_p (rtx);
275 static bool unknown_for_bundling_p (rtx);
276 static void bundling (FILE *, int, rtx, rtx);
278 static void ia64_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
279 HOST_WIDE_INT, tree);
280 static void ia64_file_start (void);
281 static void ia64_globalize_decl_name (FILE *, tree);
283 static int ia64_hpux_reloc_rw_mask (void) ATTRIBUTE_UNUSED;
284 static int ia64_reloc_rw_mask (void) ATTRIBUTE_UNUSED;
285 static section *ia64_select_rtx_section (enum machine_mode, rtx,
286 unsigned HOST_WIDE_INT);
287 static void ia64_output_dwarf_dtprel (FILE *, int, rtx)
289 static unsigned int ia64_section_type_flags (tree, const char *, int);
290 static void ia64_init_libfuncs (void)
292 static void ia64_hpux_init_libfuncs (void)
294 static void ia64_sysv4_init_libfuncs (void)
296 static void ia64_vms_init_libfuncs (void)
298 static void ia64_soft_fp_init_libfuncs (void)
300 static bool ia64_vms_valid_pointer_mode (enum machine_mode mode)
302 static tree ia64_vms_common_object_attribute (tree *, tree, tree, int, bool *)
305 static tree ia64_handle_model_attribute (tree *, tree, tree, int, bool *);
306 static tree ia64_handle_version_id_attribute (tree *, tree, tree, int, bool *);
307 static void ia64_encode_section_info (tree, rtx, int);
308 static rtx ia64_struct_value_rtx (tree, int);
309 static tree ia64_gimplify_va_arg (tree, tree, gimple_seq *, gimple_seq *);
310 static bool ia64_scalar_mode_supported_p (enum machine_mode mode);
311 static bool ia64_vector_mode_supported_p (enum machine_mode mode);
312 static bool ia64_legitimate_constant_p (enum machine_mode, rtx);
313 static bool ia64_legitimate_address_p (enum machine_mode, rtx, bool);
314 static bool ia64_cannot_force_const_mem (enum machine_mode, rtx);
315 static const char *ia64_mangle_type (const_tree);
316 static const char *ia64_invalid_conversion (const_tree, const_tree);
317 static const char *ia64_invalid_unary_op (int, const_tree);
318 static const char *ia64_invalid_binary_op (int, const_tree, const_tree);
319 static enum machine_mode ia64_c_mode_for_suffix (char);
320 static void ia64_trampoline_init (rtx, tree, rtx);
321 static void ia64_override_options_after_change (void);
322 static bool ia64_member_type_forces_blk (const_tree, enum machine_mode);
324 static tree ia64_builtin_decl (unsigned, bool);
326 static reg_class_t ia64_preferred_reload_class (rtx, reg_class_t);
327 static enum machine_mode ia64_get_reg_raw_mode (int regno);
328 static section * ia64_hpux_function_section (tree, enum node_frequency,
331 static bool ia64_vectorize_vec_perm_const_ok (enum machine_mode vmode,
332 const unsigned char *sel);
334 #define MAX_VECT_LEN 8
336 struct expand_vec_perm_d
338 rtx target, op0, op1;
339 unsigned char perm[MAX_VECT_LEN];
340 enum machine_mode vmode;
346 static bool ia64_expand_vec_perm_const_1 (struct expand_vec_perm_d *d);
349 /* Table of valid machine attributes. */
350 static const struct attribute_spec ia64_attribute_table[] =
352 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
353 affects_type_identity } */
354 { "syscall_linkage", 0, 0, false, true, true, NULL, false },
355 { "model", 1, 1, true, false, false, ia64_handle_model_attribute,
357 #if TARGET_ABI_OPEN_VMS
358 { "common_object", 1, 1, true, false, false,
359 ia64_vms_common_object_attribute, false },
361 { "version_id", 1, 1, true, false, false,
362 ia64_handle_version_id_attribute, false },
363 { NULL, 0, 0, false, false, false, NULL, false }
366 /* Initialize the GCC target structure. */
367 #undef TARGET_ATTRIBUTE_TABLE
368 #define TARGET_ATTRIBUTE_TABLE ia64_attribute_table
370 #undef TARGET_INIT_BUILTINS
371 #define TARGET_INIT_BUILTINS ia64_init_builtins
373 #undef TARGET_EXPAND_BUILTIN
374 #define TARGET_EXPAND_BUILTIN ia64_expand_builtin
376 #undef TARGET_BUILTIN_DECL
377 #define TARGET_BUILTIN_DECL ia64_builtin_decl
379 #undef TARGET_ASM_BYTE_OP
380 #define TARGET_ASM_BYTE_OP "\tdata1\t"
381 #undef TARGET_ASM_ALIGNED_HI_OP
382 #define TARGET_ASM_ALIGNED_HI_OP "\tdata2\t"
383 #undef TARGET_ASM_ALIGNED_SI_OP
384 #define TARGET_ASM_ALIGNED_SI_OP "\tdata4\t"
385 #undef TARGET_ASM_ALIGNED_DI_OP
386 #define TARGET_ASM_ALIGNED_DI_OP "\tdata8\t"
387 #undef TARGET_ASM_UNALIGNED_HI_OP
388 #define TARGET_ASM_UNALIGNED_HI_OP "\tdata2.ua\t"
389 #undef TARGET_ASM_UNALIGNED_SI_OP
390 #define TARGET_ASM_UNALIGNED_SI_OP "\tdata4.ua\t"
391 #undef TARGET_ASM_UNALIGNED_DI_OP
392 #define TARGET_ASM_UNALIGNED_DI_OP "\tdata8.ua\t"
393 #undef TARGET_ASM_INTEGER
394 #define TARGET_ASM_INTEGER ia64_assemble_integer
396 #undef TARGET_OPTION_OVERRIDE
397 #define TARGET_OPTION_OVERRIDE ia64_option_override
399 #undef TARGET_ASM_FUNCTION_PROLOGUE
400 #define TARGET_ASM_FUNCTION_PROLOGUE ia64_output_function_prologue
401 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
402 #define TARGET_ASM_FUNCTION_END_PROLOGUE ia64_output_function_end_prologue
403 #undef TARGET_ASM_FUNCTION_EPILOGUE
404 #define TARGET_ASM_FUNCTION_EPILOGUE ia64_output_function_epilogue
406 #undef TARGET_PRINT_OPERAND
407 #define TARGET_PRINT_OPERAND ia64_print_operand
408 #undef TARGET_PRINT_OPERAND_ADDRESS
409 #define TARGET_PRINT_OPERAND_ADDRESS ia64_print_operand_address
410 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
411 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ia64_print_operand_punct_valid_p
413 #undef TARGET_IN_SMALL_DATA_P
414 #define TARGET_IN_SMALL_DATA_P ia64_in_small_data_p
416 #undef TARGET_SCHED_ADJUST_COST_2
417 #define TARGET_SCHED_ADJUST_COST_2 ia64_adjust_cost_2
418 #undef TARGET_SCHED_ISSUE_RATE
419 #define TARGET_SCHED_ISSUE_RATE ia64_issue_rate
420 #undef TARGET_SCHED_VARIABLE_ISSUE
421 #define TARGET_SCHED_VARIABLE_ISSUE ia64_variable_issue
422 #undef TARGET_SCHED_INIT
423 #define TARGET_SCHED_INIT ia64_sched_init
424 #undef TARGET_SCHED_FINISH
425 #define TARGET_SCHED_FINISH ia64_sched_finish
426 #undef TARGET_SCHED_INIT_GLOBAL
427 #define TARGET_SCHED_INIT_GLOBAL ia64_sched_init_global
428 #undef TARGET_SCHED_FINISH_GLOBAL
429 #define TARGET_SCHED_FINISH_GLOBAL ia64_sched_finish_global
430 #undef TARGET_SCHED_REORDER
431 #define TARGET_SCHED_REORDER ia64_sched_reorder
432 #undef TARGET_SCHED_REORDER2
433 #define TARGET_SCHED_REORDER2 ia64_sched_reorder2
435 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
436 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK ia64_dependencies_evaluation_hook
438 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
439 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD ia64_first_cycle_multipass_dfa_lookahead
441 #undef TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN
442 #define TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN ia64_init_dfa_pre_cycle_insn
443 #undef TARGET_SCHED_DFA_PRE_CYCLE_INSN
444 #define TARGET_SCHED_DFA_PRE_CYCLE_INSN ia64_dfa_pre_cycle_insn
446 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
447 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD\
448 ia64_first_cycle_multipass_dfa_lookahead_guard
450 #undef TARGET_SCHED_DFA_NEW_CYCLE
451 #define TARGET_SCHED_DFA_NEW_CYCLE ia64_dfa_new_cycle
453 #undef TARGET_SCHED_H_I_D_EXTENDED
454 #define TARGET_SCHED_H_I_D_EXTENDED ia64_h_i_d_extended
456 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
457 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT ia64_alloc_sched_context
459 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
460 #define TARGET_SCHED_INIT_SCHED_CONTEXT ia64_init_sched_context
462 #undef TARGET_SCHED_SET_SCHED_CONTEXT
463 #define TARGET_SCHED_SET_SCHED_CONTEXT ia64_set_sched_context
465 #undef TARGET_SCHED_CLEAR_SCHED_CONTEXT
466 #define TARGET_SCHED_CLEAR_SCHED_CONTEXT ia64_clear_sched_context
468 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
469 #define TARGET_SCHED_FREE_SCHED_CONTEXT ia64_free_sched_context
471 #undef TARGET_SCHED_SET_SCHED_FLAGS
472 #define TARGET_SCHED_SET_SCHED_FLAGS ia64_set_sched_flags
474 #undef TARGET_SCHED_GET_INSN_SPEC_DS
475 #define TARGET_SCHED_GET_INSN_SPEC_DS ia64_get_insn_spec_ds
477 #undef TARGET_SCHED_GET_INSN_CHECKED_DS
478 #define TARGET_SCHED_GET_INSN_CHECKED_DS ia64_get_insn_checked_ds
480 #undef TARGET_SCHED_SPECULATE_INSN
481 #define TARGET_SCHED_SPECULATE_INSN ia64_speculate_insn
483 #undef TARGET_SCHED_NEEDS_BLOCK_P
484 #define TARGET_SCHED_NEEDS_BLOCK_P ia64_needs_block_p
486 #undef TARGET_SCHED_GEN_SPEC_CHECK
487 #define TARGET_SCHED_GEN_SPEC_CHECK ia64_gen_spec_check
489 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD_SPEC
490 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD_SPEC\
491 ia64_first_cycle_multipass_dfa_lookahead_guard_spec
493 #undef TARGET_SCHED_SKIP_RTX_P
494 #define TARGET_SCHED_SKIP_RTX_P ia64_skip_rtx_p
496 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
497 #define TARGET_FUNCTION_OK_FOR_SIBCALL ia64_function_ok_for_sibcall
498 #undef TARGET_ARG_PARTIAL_BYTES
499 #define TARGET_ARG_PARTIAL_BYTES ia64_arg_partial_bytes
500 #undef TARGET_FUNCTION_ARG
501 #define TARGET_FUNCTION_ARG ia64_function_arg
502 #undef TARGET_FUNCTION_INCOMING_ARG
503 #define TARGET_FUNCTION_INCOMING_ARG ia64_function_incoming_arg
504 #undef TARGET_FUNCTION_ARG_ADVANCE
505 #define TARGET_FUNCTION_ARG_ADVANCE ia64_function_arg_advance
506 #undef TARGET_FUNCTION_ARG_BOUNDARY
507 #define TARGET_FUNCTION_ARG_BOUNDARY ia64_function_arg_boundary
509 #undef TARGET_ASM_OUTPUT_MI_THUNK
510 #define TARGET_ASM_OUTPUT_MI_THUNK ia64_output_mi_thunk
511 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
512 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
514 #undef TARGET_ASM_FILE_START
515 #define TARGET_ASM_FILE_START ia64_file_start
517 #undef TARGET_ASM_GLOBALIZE_DECL_NAME
518 #define TARGET_ASM_GLOBALIZE_DECL_NAME ia64_globalize_decl_name
520 #undef TARGET_REGISTER_MOVE_COST
521 #define TARGET_REGISTER_MOVE_COST ia64_register_move_cost
522 #undef TARGET_MEMORY_MOVE_COST
523 #define TARGET_MEMORY_MOVE_COST ia64_memory_move_cost
524 #undef TARGET_RTX_COSTS
525 #define TARGET_RTX_COSTS ia64_rtx_costs
526 #undef TARGET_ADDRESS_COST
527 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0
529 #undef TARGET_UNSPEC_MAY_TRAP_P
530 #define TARGET_UNSPEC_MAY_TRAP_P ia64_unspec_may_trap_p
532 #undef TARGET_MACHINE_DEPENDENT_REORG
533 #define TARGET_MACHINE_DEPENDENT_REORG ia64_reorg
535 #undef TARGET_ENCODE_SECTION_INFO
536 #define TARGET_ENCODE_SECTION_INFO ia64_encode_section_info
538 #undef TARGET_SECTION_TYPE_FLAGS
539 #define TARGET_SECTION_TYPE_FLAGS ia64_section_type_flags
542 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
543 #define TARGET_ASM_OUTPUT_DWARF_DTPREL ia64_output_dwarf_dtprel
546 /* ??? Investigate. */
548 #undef TARGET_PROMOTE_PROTOTYPES
549 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
552 #undef TARGET_FUNCTION_VALUE
553 #define TARGET_FUNCTION_VALUE ia64_function_value
554 #undef TARGET_LIBCALL_VALUE
555 #define TARGET_LIBCALL_VALUE ia64_libcall_value
556 #undef TARGET_FUNCTION_VALUE_REGNO_P
557 #define TARGET_FUNCTION_VALUE_REGNO_P ia64_function_value_regno_p
559 #undef TARGET_STRUCT_VALUE_RTX
560 #define TARGET_STRUCT_VALUE_RTX ia64_struct_value_rtx
561 #undef TARGET_RETURN_IN_MEMORY
562 #define TARGET_RETURN_IN_MEMORY ia64_return_in_memory
563 #undef TARGET_SETUP_INCOMING_VARARGS
564 #define TARGET_SETUP_INCOMING_VARARGS ia64_setup_incoming_varargs
565 #undef TARGET_STRICT_ARGUMENT_NAMING
566 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
567 #undef TARGET_MUST_PASS_IN_STACK
568 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
569 #undef TARGET_GET_RAW_RESULT_MODE
570 #define TARGET_GET_RAW_RESULT_MODE ia64_get_reg_raw_mode
571 #undef TARGET_GET_RAW_ARG_MODE
572 #define TARGET_GET_RAW_ARG_MODE ia64_get_reg_raw_mode
574 #undef TARGET_MEMBER_TYPE_FORCES_BLK
575 #define TARGET_MEMBER_TYPE_FORCES_BLK ia64_member_type_forces_blk
577 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
578 #define TARGET_GIMPLIFY_VA_ARG_EXPR ia64_gimplify_va_arg
580 #undef TARGET_ASM_UNWIND_EMIT
581 #define TARGET_ASM_UNWIND_EMIT ia64_asm_unwind_emit
582 #undef TARGET_ASM_EMIT_EXCEPT_PERSONALITY
583 #define TARGET_ASM_EMIT_EXCEPT_PERSONALITY ia64_asm_emit_except_personality
584 #undef TARGET_ASM_INIT_SECTIONS
585 #define TARGET_ASM_INIT_SECTIONS ia64_asm_init_sections
587 #undef TARGET_DEBUG_UNWIND_INFO
588 #define TARGET_DEBUG_UNWIND_INFO ia64_debug_unwind_info
590 #undef TARGET_SCALAR_MODE_SUPPORTED_P
591 #define TARGET_SCALAR_MODE_SUPPORTED_P ia64_scalar_mode_supported_p
592 #undef TARGET_VECTOR_MODE_SUPPORTED_P
593 #define TARGET_VECTOR_MODE_SUPPORTED_P ia64_vector_mode_supported_p
595 /* ia64 architecture manual 4.4.7: ... reads, writes, and flushes may occur
596 in an order different from the specified program order. */
597 #undef TARGET_RELAXED_ORDERING
598 #define TARGET_RELAXED_ORDERING true
600 #undef TARGET_LEGITIMATE_CONSTANT_P
601 #define TARGET_LEGITIMATE_CONSTANT_P ia64_legitimate_constant_p
602 #undef TARGET_LEGITIMATE_ADDRESS_P
603 #define TARGET_LEGITIMATE_ADDRESS_P ia64_legitimate_address_p
605 #undef TARGET_CANNOT_FORCE_CONST_MEM
606 #define TARGET_CANNOT_FORCE_CONST_MEM ia64_cannot_force_const_mem
608 #undef TARGET_MANGLE_TYPE
609 #define TARGET_MANGLE_TYPE ia64_mangle_type
611 #undef TARGET_INVALID_CONVERSION
612 #define TARGET_INVALID_CONVERSION ia64_invalid_conversion
613 #undef TARGET_INVALID_UNARY_OP
614 #define TARGET_INVALID_UNARY_OP ia64_invalid_unary_op
615 #undef TARGET_INVALID_BINARY_OP
616 #define TARGET_INVALID_BINARY_OP ia64_invalid_binary_op
618 #undef TARGET_C_MODE_FOR_SUFFIX
619 #define TARGET_C_MODE_FOR_SUFFIX ia64_c_mode_for_suffix
621 #undef TARGET_CAN_ELIMINATE
622 #define TARGET_CAN_ELIMINATE ia64_can_eliminate
624 #undef TARGET_TRAMPOLINE_INIT
625 #define TARGET_TRAMPOLINE_INIT ia64_trampoline_init
627 #undef TARGET_INVALID_WITHIN_DOLOOP
628 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_null
630 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
631 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE ia64_override_options_after_change
633 #undef TARGET_PREFERRED_RELOAD_CLASS
634 #define TARGET_PREFERRED_RELOAD_CLASS ia64_preferred_reload_class
636 #undef TARGET_DELAY_SCHED2
637 #define TARGET_DELAY_SCHED2 true
639 /* Variable tracking should be run after all optimizations which
640 change order of insns. It also needs a valid CFG. */
641 #undef TARGET_DELAY_VARTRACK
642 #define TARGET_DELAY_VARTRACK true
644 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
645 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK ia64_vectorize_vec_perm_const_ok
647 struct gcc_target targetm = TARGET_INITIALIZER;
651 ADDR_AREA_NORMAL, /* normal address area */
652 ADDR_AREA_SMALL /* addressable by "addl" (-2MB < addr < 2MB) */
656 static GTY(()) tree small_ident1;
657 static GTY(()) tree small_ident2;
662 if (small_ident1 == 0)
664 small_ident1 = get_identifier ("small");
665 small_ident2 = get_identifier ("__small__");
669 /* Retrieve the address area that has been chosen for the given decl. */
671 static ia64_addr_area
672 ia64_get_addr_area (tree decl)
676 model_attr = lookup_attribute ("model", DECL_ATTRIBUTES (decl));
682 id = TREE_VALUE (TREE_VALUE (model_attr));
683 if (id == small_ident1 || id == small_ident2)
684 return ADDR_AREA_SMALL;
686 return ADDR_AREA_NORMAL;
690 ia64_handle_model_attribute (tree *node, tree name, tree args,
691 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
693 ia64_addr_area addr_area = ADDR_AREA_NORMAL;
695 tree arg, decl = *node;
698 arg = TREE_VALUE (args);
699 if (arg == small_ident1 || arg == small_ident2)
701 addr_area = ADDR_AREA_SMALL;
705 warning (OPT_Wattributes, "invalid argument of %qE attribute",
707 *no_add_attrs = true;
710 switch (TREE_CODE (decl))
713 if ((DECL_CONTEXT (decl) && TREE_CODE (DECL_CONTEXT (decl))
715 && !TREE_STATIC (decl))
717 error_at (DECL_SOURCE_LOCATION (decl),
718 "an address area attribute cannot be specified for "
720 *no_add_attrs = true;
722 area = ia64_get_addr_area (decl);
723 if (area != ADDR_AREA_NORMAL && addr_area != area)
725 error ("address area of %q+D conflicts with previous "
726 "declaration", decl);
727 *no_add_attrs = true;
732 error_at (DECL_SOURCE_LOCATION (decl),
733 "address area attribute cannot be specified for "
735 *no_add_attrs = true;
739 warning (OPT_Wattributes, "%qE attribute ignored",
741 *no_add_attrs = true;
748 /* Part of the low level implementation of DEC Ada pragma Common_Object which
749 enables the shared use of variables stored in overlaid linker areas
750 corresponding to the use of Fortran COMMON. */
753 ia64_vms_common_object_attribute (tree *node, tree name, tree args,
754 int flags ATTRIBUTE_UNUSED,
760 gcc_assert (DECL_P (decl));
762 DECL_COMMON (decl) = 1;
763 id = TREE_VALUE (args);
764 if (TREE_CODE (id) != IDENTIFIER_NODE && TREE_CODE (id) != STRING_CST)
766 error ("%qE attribute requires a string constant argument", name);
767 *no_add_attrs = true;
773 /* Part of the low level implementation of DEC Ada pragma Common_Object. */
776 ia64_vms_output_aligned_decl_common (FILE *file, tree decl, const char *name,
777 unsigned HOST_WIDE_INT size,
780 tree attr = DECL_ATTRIBUTES (decl);
783 attr = lookup_attribute ("common_object", attr);
786 tree id = TREE_VALUE (TREE_VALUE (attr));
789 if (TREE_CODE (id) == IDENTIFIER_NODE)
790 name = IDENTIFIER_POINTER (id);
791 else if (TREE_CODE (id) == STRING_CST)
792 name = TREE_STRING_POINTER (id);
796 fprintf (file, "\t.vms_common\t\"%s\",", name);
799 fprintf (file, "%s", COMMON_ASM_OP);
801 /* Code from elfos.h. */
802 assemble_name (file, name);
803 fprintf (file, ","HOST_WIDE_INT_PRINT_UNSIGNED",%u",
804 size, align / BITS_PER_UNIT);
810 ia64_encode_addr_area (tree decl, rtx symbol)
814 flags = SYMBOL_REF_FLAGS (symbol);
815 switch (ia64_get_addr_area (decl))
817 case ADDR_AREA_NORMAL: break;
818 case ADDR_AREA_SMALL: flags |= SYMBOL_FLAG_SMALL_ADDR; break;
819 default: gcc_unreachable ();
821 SYMBOL_REF_FLAGS (symbol) = flags;
825 ia64_encode_section_info (tree decl, rtx rtl, int first)
827 default_encode_section_info (decl, rtl, first);
829 /* Careful not to prod global register variables. */
830 if (TREE_CODE (decl) == VAR_DECL
831 && GET_CODE (DECL_RTL (decl)) == MEM
832 && GET_CODE (XEXP (DECL_RTL (decl), 0)) == SYMBOL_REF
833 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
834 ia64_encode_addr_area (decl, XEXP (rtl, 0));
837 /* Return 1 if the operands of a move are ok. */
840 ia64_move_ok (rtx dst, rtx src)
842 /* If we're under init_recog_no_volatile, we'll not be able to use
843 memory_operand. So check the code directly and don't worry about
844 the validity of the underlying address, which should have been
845 checked elsewhere anyway. */
846 if (GET_CODE (dst) != MEM)
848 if (GET_CODE (src) == MEM)
850 if (register_operand (src, VOIDmode))
853 /* Otherwise, this must be a constant, and that either 0 or 0.0 or 1.0. */
854 if (INTEGRAL_MODE_P (GET_MODE (dst)))
855 return src == const0_rtx;
857 return satisfies_constraint_G (src);
860 /* Return 1 if the operands are ok for a floating point load pair. */
863 ia64_load_pair_ok (rtx dst, rtx src)
865 /* ??? There is a thinko in the implementation of the "x" constraint and the
866 FP_REGS class. The constraint will also reject (reg f30:TI) so we must
867 also return false for it. */
868 if (GET_CODE (dst) != REG
869 || !(FP_REGNO_P (REGNO (dst)) && FP_REGNO_P (REGNO (dst) + 1)))
871 if (GET_CODE (src) != MEM || MEM_VOLATILE_P (src))
873 switch (GET_CODE (XEXP (src, 0)))
882 rtx adjust = XEXP (XEXP (XEXP (src, 0), 1), 1);
884 if (GET_CODE (adjust) != CONST_INT
885 || INTVAL (adjust) != GET_MODE_SIZE (GET_MODE (src)))
896 addp4_optimize_ok (rtx op1, rtx op2)
898 return (basereg_operand (op1, GET_MODE(op1)) !=
899 basereg_operand (op2, GET_MODE(op2)));
902 /* Check if OP is a mask suitable for use with SHIFT in a dep.z instruction.
903 Return the length of the field, or <= 0 on failure. */
906 ia64_depz_field_mask (rtx rop, rtx rshift)
908 unsigned HOST_WIDE_INT op = INTVAL (rop);
909 unsigned HOST_WIDE_INT shift = INTVAL (rshift);
911 /* Get rid of the zero bits we're shifting in. */
914 /* We must now have a solid block of 1's at bit 0. */
915 return exact_log2 (op + 1);
918 /* Return the TLS model to use for ADDR. */
920 static enum tls_model
921 tls_symbolic_operand_type (rtx addr)
923 enum tls_model tls_kind = TLS_MODEL_NONE;
925 if (GET_CODE (addr) == CONST)
927 if (GET_CODE (XEXP (addr, 0)) == PLUS
928 && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF)
929 tls_kind = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (addr, 0), 0));
931 else if (GET_CODE (addr) == SYMBOL_REF)
932 tls_kind = SYMBOL_REF_TLS_MODEL (addr);
937 /* Returns true if REG (assumed to be a `reg' RTX) is valid for use
938 as a base register. */
941 ia64_reg_ok_for_base_p (const_rtx reg, bool strict)
944 && REGNO_OK_FOR_BASE_P (REGNO (reg)))
947 && (GENERAL_REGNO_P (REGNO (reg))
948 || !HARD_REGISTER_P (reg)))
955 ia64_legitimate_address_reg (const_rtx reg, bool strict)
957 if ((REG_P (reg) && ia64_reg_ok_for_base_p (reg, strict))
958 || (GET_CODE (reg) == SUBREG && REG_P (XEXP (reg, 0))
959 && ia64_reg_ok_for_base_p (XEXP (reg, 0), strict)))
966 ia64_legitimate_address_disp (const_rtx reg, const_rtx disp, bool strict)
968 if (GET_CODE (disp) == PLUS
969 && rtx_equal_p (reg, XEXP (disp, 0))
970 && (ia64_legitimate_address_reg (XEXP (disp, 1), strict)
971 || (CONST_INT_P (XEXP (disp, 1))
972 && IN_RANGE (INTVAL (XEXP (disp, 1)), -256, 255))))
978 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
981 ia64_legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
984 if (ia64_legitimate_address_reg (x, strict))
986 else if ((GET_CODE (x) == POST_INC || GET_CODE (x) == POST_DEC)
987 && ia64_legitimate_address_reg (XEXP (x, 0), strict)
988 && XEXP (x, 0) != arg_pointer_rtx)
990 else if (GET_CODE (x) == POST_MODIFY
991 && ia64_legitimate_address_reg (XEXP (x, 0), strict)
992 && XEXP (x, 0) != arg_pointer_rtx
993 && ia64_legitimate_address_disp (XEXP (x, 0), XEXP (x, 1), strict))
999 /* Return true if X is a constant that is valid for some immediate
1000 field in an instruction. */
1003 ia64_legitimate_constant_p (enum machine_mode mode, rtx x)
1005 switch (GET_CODE (x))
1012 if (GET_MODE (x) == VOIDmode || mode == SFmode || mode == DFmode)
1014 return satisfies_constraint_G (x);
1018 /* ??? Short term workaround for PR 28490. We must make the code here
1019 match the code in ia64_expand_move and move_operand, even though they
1020 are both technically wrong. */
1021 if (tls_symbolic_operand_type (x) == 0)
1023 HOST_WIDE_INT addend = 0;
1026 if (GET_CODE (op) == CONST
1027 && GET_CODE (XEXP (op, 0)) == PLUS
1028 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
1030 addend = INTVAL (XEXP (XEXP (op, 0), 1));
1031 op = XEXP (XEXP (op, 0), 0);
1034 if (any_offset_symbol_operand (op, mode)
1035 || function_operand (op, mode))
1037 if (aligned_offset_symbol_operand (op, mode))
1038 return (addend & 0x3fff) == 0;
1044 if (mode == V2SFmode)
1045 return satisfies_constraint_Y (x);
1047 return (GET_MODE_CLASS (mode) == MODE_VECTOR_INT
1048 && GET_MODE_SIZE (mode) <= 8);
1055 /* Don't allow TLS addresses to get spilled to memory. */
1058 ia64_cannot_force_const_mem (enum machine_mode mode, rtx x)
1062 return tls_symbolic_operand_type (x) != 0;
1065 /* Expand a symbolic constant load. */
1068 ia64_expand_load_address (rtx dest, rtx src)
1070 gcc_assert (GET_CODE (dest) == REG);
1072 /* ILP32 mode still loads 64-bits of data from the GOT. This avoids
1073 having to pointer-extend the value afterward. Other forms of address
1074 computation below are also more natural to compute as 64-bit quantities.
1075 If we've been given an SImode destination register, change it. */
1076 if (GET_MODE (dest) != Pmode)
1077 dest = gen_rtx_REG_offset (dest, Pmode, REGNO (dest),
1078 byte_lowpart_offset (Pmode, GET_MODE (dest)));
1082 if (small_addr_symbolic_operand (src, VOIDmode))
1085 if (TARGET_AUTO_PIC)
1086 emit_insn (gen_load_gprel64 (dest, src));
1087 else if (GET_CODE (src) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (src))
1088 emit_insn (gen_load_fptr (dest, src));
1089 else if (sdata_symbolic_operand (src, VOIDmode))
1090 emit_insn (gen_load_gprel (dest, src));
1093 HOST_WIDE_INT addend = 0;
1096 /* We did split constant offsets in ia64_expand_move, and we did try
1097 to keep them split in move_operand, but we also allowed reload to
1098 rematerialize arbitrary constants rather than spill the value to
1099 the stack and reload it. So we have to be prepared here to split
1100 them apart again. */
1101 if (GET_CODE (src) == CONST)
1103 HOST_WIDE_INT hi, lo;
1105 hi = INTVAL (XEXP (XEXP (src, 0), 1));
1106 lo = ((hi & 0x3fff) ^ 0x2000) - 0x2000;
1112 src = plus_constant (Pmode, XEXP (XEXP (src, 0), 0), hi);
1116 tmp = gen_rtx_HIGH (Pmode, src);
1117 tmp = gen_rtx_PLUS (Pmode, tmp, pic_offset_table_rtx);
1118 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
1120 tmp = gen_rtx_LO_SUM (Pmode, gen_const_mem (Pmode, dest), src);
1121 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
1125 tmp = gen_rtx_PLUS (Pmode, dest, GEN_INT (addend));
1126 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
1133 static GTY(()) rtx gen_tls_tga;
1135 gen_tls_get_addr (void)
1138 gen_tls_tga = init_one_libfunc ("__tls_get_addr");
1142 static GTY(()) rtx thread_pointer_rtx;
1144 gen_thread_pointer (void)
1146 if (!thread_pointer_rtx)
1147 thread_pointer_rtx = gen_rtx_REG (Pmode, 13);
1148 return thread_pointer_rtx;
1152 ia64_expand_tls_address (enum tls_model tls_kind, rtx op0, rtx op1,
1153 rtx orig_op1, HOST_WIDE_INT addend)
1155 rtx tga_op1, tga_op2, tga_ret, tga_eqv, tmp, insns;
1157 HOST_WIDE_INT addend_lo, addend_hi;
1161 case TLS_MODEL_GLOBAL_DYNAMIC:
1164 tga_op1 = gen_reg_rtx (Pmode);
1165 emit_insn (gen_load_dtpmod (tga_op1, op1));
1167 tga_op2 = gen_reg_rtx (Pmode);
1168 emit_insn (gen_load_dtprel (tga_op2, op1));
1170 tga_ret = emit_library_call_value (gen_tls_get_addr (), NULL_RTX,
1171 LCT_CONST, Pmode, 2, tga_op1,
1172 Pmode, tga_op2, Pmode);
1174 insns = get_insns ();
1177 if (GET_MODE (op0) != Pmode)
1179 emit_libcall_block (insns, op0, tga_ret, op1);
1182 case TLS_MODEL_LOCAL_DYNAMIC:
1183 /* ??? This isn't the completely proper way to do local-dynamic
1184 If the call to __tls_get_addr is used only by a single symbol,
1185 then we should (somehow) move the dtprel to the second arg
1186 to avoid the extra add. */
1189 tga_op1 = gen_reg_rtx (Pmode);
1190 emit_insn (gen_load_dtpmod (tga_op1, op1));
1192 tga_op2 = const0_rtx;
1194 tga_ret = emit_library_call_value (gen_tls_get_addr (), NULL_RTX,
1195 LCT_CONST, Pmode, 2, tga_op1,
1196 Pmode, tga_op2, Pmode);
1198 insns = get_insns ();
1201 tga_eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
1203 tmp = gen_reg_rtx (Pmode);
1204 emit_libcall_block (insns, tmp, tga_ret, tga_eqv);
1206 if (!register_operand (op0, Pmode))
1207 op0 = gen_reg_rtx (Pmode);
1210 emit_insn (gen_load_dtprel (op0, op1));
1211 emit_insn (gen_adddi3 (op0, tmp, op0));
1214 emit_insn (gen_add_dtprel (op0, op1, tmp));
1217 case TLS_MODEL_INITIAL_EXEC:
1218 addend_lo = ((addend & 0x3fff) ^ 0x2000) - 0x2000;
1219 addend_hi = addend - addend_lo;
1221 op1 = plus_constant (Pmode, op1, addend_hi);
1224 tmp = gen_reg_rtx (Pmode);
1225 emit_insn (gen_load_tprel (tmp, op1));
1227 if (!register_operand (op0, Pmode))
1228 op0 = gen_reg_rtx (Pmode);
1229 emit_insn (gen_adddi3 (op0, tmp, gen_thread_pointer ()));
1232 case TLS_MODEL_LOCAL_EXEC:
1233 if (!register_operand (op0, Pmode))
1234 op0 = gen_reg_rtx (Pmode);
1240 emit_insn (gen_load_tprel (op0, op1));
1241 emit_insn (gen_adddi3 (op0, op0, gen_thread_pointer ()));
1244 emit_insn (gen_add_tprel (op0, op1, gen_thread_pointer ()));
1252 op0 = expand_simple_binop (Pmode, PLUS, op0, GEN_INT (addend),
1253 orig_op0, 1, OPTAB_DIRECT);
1254 if (orig_op0 == op0)
1256 if (GET_MODE (orig_op0) == Pmode)
1258 return gen_lowpart (GET_MODE (orig_op0), op0);
1262 ia64_expand_move (rtx op0, rtx op1)
1264 enum machine_mode mode = GET_MODE (op0);
1266 if (!reload_in_progress && !reload_completed && !ia64_move_ok (op0, op1))
1267 op1 = force_reg (mode, op1);
1269 if ((mode == Pmode || mode == ptr_mode) && symbolic_operand (op1, VOIDmode))
1271 HOST_WIDE_INT addend = 0;
1272 enum tls_model tls_kind;
1275 if (GET_CODE (op1) == CONST
1276 && GET_CODE (XEXP (op1, 0)) == PLUS
1277 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT)
1279 addend = INTVAL (XEXP (XEXP (op1, 0), 1));
1280 sym = XEXP (XEXP (op1, 0), 0);
1283 tls_kind = tls_symbolic_operand_type (sym);
1285 return ia64_expand_tls_address (tls_kind, op0, sym, op1, addend);
1287 if (any_offset_symbol_operand (sym, mode))
1289 else if (aligned_offset_symbol_operand (sym, mode))
1291 HOST_WIDE_INT addend_lo, addend_hi;
1293 addend_lo = ((addend & 0x3fff) ^ 0x2000) - 0x2000;
1294 addend_hi = addend - addend_lo;
1298 op1 = plus_constant (mode, sym, addend_hi);
1307 if (reload_completed)
1309 /* We really should have taken care of this offset earlier. */
1310 gcc_assert (addend == 0);
1311 if (ia64_expand_load_address (op0, op1))
1317 rtx subtarget = !can_create_pseudo_p () ? op0 : gen_reg_rtx (mode);
1319 emit_insn (gen_rtx_SET (VOIDmode, subtarget, op1));
1321 op1 = expand_simple_binop (mode, PLUS, subtarget,
1322 GEN_INT (addend), op0, 1, OPTAB_DIRECT);
1331 /* Split a move from OP1 to OP0 conditional on COND. */
1334 ia64_emit_cond_move (rtx op0, rtx op1, rtx cond)
1336 rtx insn, first = get_last_insn ();
1338 emit_move_insn (op0, op1);
1340 for (insn = get_last_insn (); insn != first; insn = PREV_INSN (insn))
1342 PATTERN (insn) = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond),
1346 /* Split a post-reload TImode or TFmode reference into two DImode
1347 components. This is made extra difficult by the fact that we do
1348 not get any scratch registers to work with, because reload cannot
1349 be prevented from giving us a scratch that overlaps the register
1350 pair involved. So instead, when addressing memory, we tweak the
1351 pointer register up and back down with POST_INCs. Or up and not
1352 back down when we can get away with it.
1354 REVERSED is true when the loads must be done in reversed order
1355 (high word first) for correctness. DEAD is true when the pointer
1356 dies with the second insn we generate and therefore the second
1357 address must not carry a postmodify.
1359 May return an insn which is to be emitted after the moves. */
1362 ia64_split_tmode (rtx out[2], rtx in, bool reversed, bool dead)
1366 switch (GET_CODE (in))
1369 out[reversed] = gen_rtx_REG (DImode, REGNO (in));
1370 out[!reversed] = gen_rtx_REG (DImode, REGNO (in) + 1);
1375 /* Cannot occur reversed. */
1376 gcc_assert (!reversed);
1378 if (GET_MODE (in) != TFmode)
1379 split_double (in, &out[0], &out[1]);
1381 /* split_double does not understand how to split a TFmode
1382 quantity into a pair of DImode constants. */
1385 unsigned HOST_WIDE_INT p[2];
1386 long l[4]; /* TFmode is 128 bits */
1388 REAL_VALUE_FROM_CONST_DOUBLE (r, in);
1389 real_to_target (l, &r, TFmode);
1391 if (FLOAT_WORDS_BIG_ENDIAN)
1393 p[0] = (((unsigned HOST_WIDE_INT) l[0]) << 32) + l[1];
1394 p[1] = (((unsigned HOST_WIDE_INT) l[2]) << 32) + l[3];
1398 p[0] = (((unsigned HOST_WIDE_INT) l[1]) << 32) + l[0];
1399 p[1] = (((unsigned HOST_WIDE_INT) l[3]) << 32) + l[2];
1401 out[0] = GEN_INT (p[0]);
1402 out[1] = GEN_INT (p[1]);
1408 rtx base = XEXP (in, 0);
1411 switch (GET_CODE (base))
1416 out[0] = adjust_automodify_address
1417 (in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
1418 out[1] = adjust_automodify_address
1419 (in, DImode, dead ? 0 : gen_rtx_POST_DEC (Pmode, base), 8);
1423 /* Reversal requires a pre-increment, which can only
1424 be done as a separate insn. */
1425 emit_insn (gen_adddi3 (base, base, GEN_INT (8)));
1426 out[0] = adjust_automodify_address
1427 (in, DImode, gen_rtx_POST_DEC (Pmode, base), 8);
1428 out[1] = adjust_address (in, DImode, 0);
1433 gcc_assert (!reversed && !dead);
1435 /* Just do the increment in two steps. */
1436 out[0] = adjust_automodify_address (in, DImode, 0, 0);
1437 out[1] = adjust_automodify_address (in, DImode, 0, 8);
1441 gcc_assert (!reversed && !dead);
1443 /* Add 8, subtract 24. */
1444 base = XEXP (base, 0);
1445 out[0] = adjust_automodify_address
1446 (in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
1447 out[1] = adjust_automodify_address
1449 gen_rtx_POST_MODIFY (Pmode, base,
1450 plus_constant (Pmode, base, -24)),
1455 gcc_assert (!reversed && !dead);
1457 /* Extract and adjust the modification. This case is
1458 trickier than the others, because we might have an
1459 index register, or we might have a combined offset that
1460 doesn't fit a signed 9-bit displacement field. We can
1461 assume the incoming expression is already legitimate. */
1462 offset = XEXP (base, 1);
1463 base = XEXP (base, 0);
1465 out[0] = adjust_automodify_address
1466 (in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
1468 if (GET_CODE (XEXP (offset, 1)) == REG)
1470 /* Can't adjust the postmodify to match. Emit the
1471 original, then a separate addition insn. */
1472 out[1] = adjust_automodify_address (in, DImode, 0, 8);
1473 fixup = gen_adddi3 (base, base, GEN_INT (-8));
1477 gcc_assert (GET_CODE (XEXP (offset, 1)) == CONST_INT);
1478 if (INTVAL (XEXP (offset, 1)) < -256 + 8)
1480 /* Again the postmodify cannot be made to match,
1481 but in this case it's more efficient to get rid
1482 of the postmodify entirely and fix up with an
1484 out[1] = adjust_automodify_address (in, DImode, base, 8);
1486 (base, base, GEN_INT (INTVAL (XEXP (offset, 1)) - 8));
1490 /* Combined offset still fits in the displacement field.
1491 (We cannot overflow it at the high end.) */
1492 out[1] = adjust_automodify_address
1493 (in, DImode, gen_rtx_POST_MODIFY
1494 (Pmode, base, gen_rtx_PLUS
1496 GEN_INT (INTVAL (XEXP (offset, 1)) - 8))),
1515 /* Split a TImode or TFmode move instruction after reload.
1516 This is used by *movtf_internal and *movti_internal. */
1518 ia64_split_tmode_move (rtx operands[])
1520 rtx in[2], out[2], insn;
1523 bool reversed = false;
1525 /* It is possible for reload to decide to overwrite a pointer with
1526 the value it points to. In that case we have to do the loads in
1527 the appropriate order so that the pointer is not destroyed too
1528 early. Also we must not generate a postmodify for that second
1529 load, or rws_access_regno will die. */
1530 if (GET_CODE (operands[1]) == MEM
1531 && reg_overlap_mentioned_p (operands[0], operands[1]))
1533 rtx base = XEXP (operands[1], 0);
1534 while (GET_CODE (base) != REG)
1535 base = XEXP (base, 0);
1537 if (REGNO (base) == REGNO (operands[0]))
1541 /* Another reason to do the moves in reversed order is if the first
1542 element of the target register pair is also the second element of
1543 the source register pair. */
1544 if (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG
1545 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
1548 fixup[0] = ia64_split_tmode (in, operands[1], reversed, dead);
1549 fixup[1] = ia64_split_tmode (out, operands[0], reversed, dead);
1551 #define MAYBE_ADD_REG_INC_NOTE(INSN, EXP) \
1552 if (GET_CODE (EXP) == MEM \
1553 && (GET_CODE (XEXP (EXP, 0)) == POST_MODIFY \
1554 || GET_CODE (XEXP (EXP, 0)) == POST_INC \
1555 || GET_CODE (XEXP (EXP, 0)) == POST_DEC)) \
1556 add_reg_note (insn, REG_INC, XEXP (XEXP (EXP, 0), 0))
1558 insn = emit_insn (gen_rtx_SET (VOIDmode, out[0], in[0]));
1559 MAYBE_ADD_REG_INC_NOTE (insn, in[0]);
1560 MAYBE_ADD_REG_INC_NOTE (insn, out[0]);
1562 insn = emit_insn (gen_rtx_SET (VOIDmode, out[1], in[1]));
1563 MAYBE_ADD_REG_INC_NOTE (insn, in[1]);
1564 MAYBE_ADD_REG_INC_NOTE (insn, out[1]);
1567 emit_insn (fixup[0]);
1569 emit_insn (fixup[1]);
1571 #undef MAYBE_ADD_REG_INC_NOTE
1574 /* ??? Fixing GR->FR XFmode moves during reload is hard. You need to go
1575 through memory plus an extra GR scratch register. Except that you can
1576 either get the first from SECONDARY_MEMORY_NEEDED or the second from
1577 SECONDARY_RELOAD_CLASS, but not both.
1579 We got into problems in the first place by allowing a construct like
1580 (subreg:XF (reg:TI)), which we got from a union containing a long double.
1581 This solution attempts to prevent this situation from occurring. When
1582 we see something like the above, we spill the inner register to memory. */
1585 spill_xfmode_rfmode_operand (rtx in, int force, enum machine_mode mode)
1587 if (GET_CODE (in) == SUBREG
1588 && GET_MODE (SUBREG_REG (in)) == TImode
1589 && GET_CODE (SUBREG_REG (in)) == REG)
1591 rtx memt = assign_stack_temp (TImode, 16);
1592 emit_move_insn (memt, SUBREG_REG (in));
1593 return adjust_address (memt, mode, 0);
1595 else if (force && GET_CODE (in) == REG)
1597 rtx memx = assign_stack_temp (mode, 16);
1598 emit_move_insn (memx, in);
1605 /* Expand the movxf or movrf pattern (MODE says which) with the given
1606 OPERANDS, returning true if the pattern should then invoke
1610 ia64_expand_movxf_movrf (enum machine_mode mode, rtx operands[])
1612 rtx op0 = operands[0];
1614 if (GET_CODE (op0) == SUBREG)
1615 op0 = SUBREG_REG (op0);
1617 /* We must support XFmode loads into general registers for stdarg/vararg,
1618 unprototyped calls, and a rare case where a long double is passed as
1619 an argument after a float HFA fills the FP registers. We split them into
1620 DImode loads for convenience. We also need to support XFmode stores
1621 for the last case. This case does not happen for stdarg/vararg routines,
1622 because we do a block store to memory of unnamed arguments. */
1624 if (GET_CODE (op0) == REG && GR_REGNO_P (REGNO (op0)))
1628 /* We're hoping to transform everything that deals with XFmode
1629 quantities and GR registers early in the compiler. */
1630 gcc_assert (can_create_pseudo_p ());
1632 /* Struct to register can just use TImode instead. */
1633 if ((GET_CODE (operands[1]) == SUBREG
1634 && GET_MODE (SUBREG_REG (operands[1])) == TImode)
1635 || (GET_CODE (operands[1]) == REG
1636 && GR_REGNO_P (REGNO (operands[1]))))
1638 rtx op1 = operands[1];
1640 if (GET_CODE (op1) == SUBREG)
1641 op1 = SUBREG_REG (op1);
1643 op1 = gen_rtx_REG (TImode, REGNO (op1));
1645 emit_move_insn (gen_rtx_REG (TImode, REGNO (op0)), op1);
1649 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1651 /* Don't word-swap when reading in the constant. */
1652 emit_move_insn (gen_rtx_REG (DImode, REGNO (op0)),
1653 operand_subword (operands[1], WORDS_BIG_ENDIAN,
1655 emit_move_insn (gen_rtx_REG (DImode, REGNO (op0) + 1),
1656 operand_subword (operands[1], !WORDS_BIG_ENDIAN,
1661 /* If the quantity is in a register not known to be GR, spill it. */
1662 if (register_operand (operands[1], mode))
1663 operands[1] = spill_xfmode_rfmode_operand (operands[1], 1, mode);
1665 gcc_assert (GET_CODE (operands[1]) == MEM);
1667 /* Don't word-swap when reading in the value. */
1668 out[0] = gen_rtx_REG (DImode, REGNO (op0));
1669 out[1] = gen_rtx_REG (DImode, REGNO (op0) + 1);
1671 emit_move_insn (out[0], adjust_address (operands[1], DImode, 0));
1672 emit_move_insn (out[1], adjust_address (operands[1], DImode, 8));
1676 if (GET_CODE (operands[1]) == REG && GR_REGNO_P (REGNO (operands[1])))
1678 /* We're hoping to transform everything that deals with XFmode
1679 quantities and GR registers early in the compiler. */
1680 gcc_assert (can_create_pseudo_p ());
1682 /* Op0 can't be a GR_REG here, as that case is handled above.
1683 If op0 is a register, then we spill op1, so that we now have a
1684 MEM operand. This requires creating an XFmode subreg of a TImode reg
1685 to force the spill. */
1686 if (register_operand (operands[0], mode))
1688 rtx op1 = gen_rtx_REG (TImode, REGNO (operands[1]));
1689 op1 = gen_rtx_SUBREG (mode, op1, 0);
1690 operands[1] = spill_xfmode_rfmode_operand (op1, 0, mode);
1697 gcc_assert (GET_CODE (operands[0]) == MEM);
1699 /* Don't word-swap when writing out the value. */
1700 in[0] = gen_rtx_REG (DImode, REGNO (operands[1]));
1701 in[1] = gen_rtx_REG (DImode, REGNO (operands[1]) + 1);
1703 emit_move_insn (adjust_address (operands[0], DImode, 0), in[0]);
1704 emit_move_insn (adjust_address (operands[0], DImode, 8), in[1]);
1709 if (!reload_in_progress && !reload_completed)
1711 operands[1] = spill_xfmode_rfmode_operand (operands[1], 0, mode);
1713 if (GET_MODE (op0) == TImode && GET_CODE (op0) == REG)
1715 rtx memt, memx, in = operands[1];
1716 if (CONSTANT_P (in))
1717 in = validize_mem (force_const_mem (mode, in));
1718 if (GET_CODE (in) == MEM)
1719 memt = adjust_address (in, TImode, 0);
1722 memt = assign_stack_temp (TImode, 16);
1723 memx = adjust_address (memt, mode, 0);
1724 emit_move_insn (memx, in);
1726 emit_move_insn (op0, memt);
1730 if (!ia64_move_ok (operands[0], operands[1]))
1731 operands[1] = force_reg (mode, operands[1]);
1737 /* Emit comparison instruction if necessary, replacing *EXPR, *OP0, *OP1
1738 with the expression that holds the compare result (in VOIDmode). */
1740 static GTY(()) rtx cmptf_libfunc;
1743 ia64_expand_compare (rtx *expr, rtx *op0, rtx *op1)
1745 enum rtx_code code = GET_CODE (*expr);
1748 /* If we have a BImode input, then we already have a compare result, and
1749 do not need to emit another comparison. */
1750 if (GET_MODE (*op0) == BImode)
1752 gcc_assert ((code == NE || code == EQ) && *op1 == const0_rtx);
1755 /* HPUX TFmode compare requires a library call to _U_Qfcmp, which takes a
1756 magic number as its third argument, that indicates what to do.
1757 The return value is an integer to be compared against zero. */
1758 else if (TARGET_HPUX && GET_MODE (*op0) == TFmode)
1761 QCMP_INV = 1, /* Raise FP_INVALID on SNaN as a side effect. */
1768 enum rtx_code ncode;
1771 gcc_assert (cmptf_libfunc && GET_MODE (*op1) == TFmode);
1774 /* 1 = equal, 0 = not equal. Equality operators do
1775 not raise FP_INVALID when given an SNaN operand. */
1776 case EQ: magic = QCMP_EQ; ncode = NE; break;
1777 case NE: magic = QCMP_EQ; ncode = EQ; break;
1778 /* isunordered() from C99. */
1779 case UNORDERED: magic = QCMP_UNORD; ncode = NE; break;
1780 case ORDERED: magic = QCMP_UNORD; ncode = EQ; break;
1781 /* Relational operators raise FP_INVALID when given
1783 case LT: magic = QCMP_LT |QCMP_INV; ncode = NE; break;
1784 case LE: magic = QCMP_LT|QCMP_EQ|QCMP_INV; ncode = NE; break;
1785 case GT: magic = QCMP_GT |QCMP_INV; ncode = NE; break;
1786 case GE: magic = QCMP_GT|QCMP_EQ|QCMP_INV; ncode = NE; break;
1787 /* FUTURE: Implement UNEQ, UNLT, UNLE, UNGT, UNGE, LTGT.
1788 Expanders for buneq etc. weuld have to be added to ia64.md
1789 for this to be useful. */
1790 default: gcc_unreachable ();
1795 ret = emit_library_call_value (cmptf_libfunc, 0, LCT_CONST, DImode, 3,
1796 *op0, TFmode, *op1, TFmode,
1797 GEN_INT (magic), DImode);
1798 cmp = gen_reg_rtx (BImode);
1799 emit_insn (gen_rtx_SET (VOIDmode, cmp,
1800 gen_rtx_fmt_ee (ncode, BImode,
1803 insns = get_insns ();
1806 emit_libcall_block (insns, cmp, cmp,
1807 gen_rtx_fmt_ee (code, BImode, *op0, *op1));
1812 cmp = gen_reg_rtx (BImode);
1813 emit_insn (gen_rtx_SET (VOIDmode, cmp,
1814 gen_rtx_fmt_ee (code, BImode, *op0, *op1)));
1818 *expr = gen_rtx_fmt_ee (code, VOIDmode, cmp, const0_rtx);
1823 /* Generate an integral vector comparison. Return true if the condition has
1824 been reversed, and so the sense of the comparison should be inverted. */
1827 ia64_expand_vecint_compare (enum rtx_code code, enum machine_mode mode,
1828 rtx dest, rtx op0, rtx op1)
1830 bool negate = false;
1833 /* Canonicalize the comparison to EQ, GT, GTU. */
1844 code = reverse_condition (code);
1850 code = reverse_condition (code);
1856 code = swap_condition (code);
1857 x = op0, op0 = op1, op1 = x;
1864 /* Unsigned parallel compare is not supported by the hardware. Play some
1865 tricks to turn this into a signed comparison against 0. */
1874 /* Subtract (-(INT MAX) - 1) from both operands to make
1876 mask = GEN_INT (0x80000000);
1877 mask = gen_rtx_CONST_VECTOR (V2SImode, gen_rtvec (2, mask, mask));
1878 mask = force_reg (mode, mask);
1879 t1 = gen_reg_rtx (mode);
1880 emit_insn (gen_subv2si3 (t1, op0, mask));
1881 t2 = gen_reg_rtx (mode);
1882 emit_insn (gen_subv2si3 (t2, op1, mask));
1891 /* Perform a parallel unsigned saturating subtraction. */
1892 x = gen_reg_rtx (mode);
1893 emit_insn (gen_rtx_SET (VOIDmode, x,
1894 gen_rtx_US_MINUS (mode, op0, op1)));
1898 op1 = CONST0_RTX (mode);
1907 x = gen_rtx_fmt_ee (code, mode, op0, op1);
1908 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
1913 /* Emit an integral vector conditional move. */
1916 ia64_expand_vecint_cmov (rtx operands[])
1918 enum machine_mode mode = GET_MODE (operands[0]);
1919 enum rtx_code code = GET_CODE (operands[3]);
1923 cmp = gen_reg_rtx (mode);
1924 negate = ia64_expand_vecint_compare (code, mode, cmp,
1925 operands[4], operands[5]);
1927 ot = operands[1+negate];
1928 of = operands[2-negate];
1930 if (ot == CONST0_RTX (mode))
1932 if (of == CONST0_RTX (mode))
1934 emit_move_insn (operands[0], ot);
1938 x = gen_rtx_NOT (mode, cmp);
1939 x = gen_rtx_AND (mode, x, of);
1940 emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
1942 else if (of == CONST0_RTX (mode))
1944 x = gen_rtx_AND (mode, cmp, ot);
1945 emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
1951 t = gen_reg_rtx (mode);
1952 x = gen_rtx_AND (mode, cmp, operands[1+negate]);
1953 emit_insn (gen_rtx_SET (VOIDmode, t, x));
1955 f = gen_reg_rtx (mode);
1956 x = gen_rtx_NOT (mode, cmp);
1957 x = gen_rtx_AND (mode, x, operands[2-negate]);
1958 emit_insn (gen_rtx_SET (VOIDmode, f, x));
1960 x = gen_rtx_IOR (mode, t, f);
1961 emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
1965 /* Emit an integral vector min or max operation. Return true if all done. */
1968 ia64_expand_vecint_minmax (enum rtx_code code, enum machine_mode mode,
1973 /* These four combinations are supported directly. */
1974 if (mode == V8QImode && (code == UMIN || code == UMAX))
1976 if (mode == V4HImode && (code == SMIN || code == SMAX))
1979 /* This combination can be implemented with only saturating subtraction. */
1980 if (mode == V4HImode && code == UMAX)
1982 rtx x, tmp = gen_reg_rtx (mode);
1984 x = gen_rtx_US_MINUS (mode, operands[1], operands[2]);
1985 emit_insn (gen_rtx_SET (VOIDmode, tmp, x));
1987 emit_insn (gen_addv4hi3 (operands[0], tmp, operands[2]));
1991 /* Everything else implemented via vector comparisons. */
1992 xops[0] = operands[0];
1993 xops[4] = xops[1] = operands[1];
1994 xops[5] = xops[2] = operands[2];
2013 xops[3] = gen_rtx_fmt_ee (code, VOIDmode, operands[1], operands[2]);
2015 ia64_expand_vecint_cmov (xops);
2019 /* The vectors LO and HI each contain N halves of a double-wide vector.
2020 Reassemble either the first N/2 or the second N/2 elements. */
2023 ia64_unpack_assemble (rtx out, rtx lo, rtx hi, bool highp)
2025 enum machine_mode vmode = GET_MODE (lo);
2026 unsigned int i, high, nelt = GET_MODE_NUNITS (vmode);
2027 struct expand_vec_perm_d d;
2030 d.target = gen_lowpart (vmode, out);
2031 d.op0 = (TARGET_BIG_ENDIAN ? hi : lo);
2032 d.op1 = (TARGET_BIG_ENDIAN ? lo : hi);
2035 d.one_operand_p = false;
2036 d.testing_p = false;
2038 high = (highp ? nelt / 2 : 0);
2039 for (i = 0; i < nelt / 2; ++i)
2041 d.perm[i * 2] = i + high;
2042 d.perm[i * 2 + 1] = i + high + nelt;
2045 ok = ia64_expand_vec_perm_const_1 (&d);
2049 /* Return a vector of the sign-extension of VEC. */
2052 ia64_unpack_sign (rtx vec, bool unsignedp)
2054 enum machine_mode mode = GET_MODE (vec);
2055 rtx zero = CONST0_RTX (mode);
2061 rtx sign = gen_reg_rtx (mode);
2064 neg = ia64_expand_vecint_compare (LT, mode, sign, vec, zero);
2071 /* Emit an integral vector unpack operation. */
2074 ia64_expand_unpack (rtx operands[3], bool unsignedp, bool highp)
2076 rtx sign = ia64_unpack_sign (operands[1], unsignedp);
2077 ia64_unpack_assemble (operands[0], operands[1], sign, highp);
2080 /* Emit an integral vector widening sum operations. */
2083 ia64_expand_widen_sum (rtx operands[3], bool unsignedp)
2085 enum machine_mode wmode;
2088 sign = ia64_unpack_sign (operands[1], unsignedp);
2090 wmode = GET_MODE (operands[0]);
2091 l = gen_reg_rtx (wmode);
2092 h = gen_reg_rtx (wmode);
2094 ia64_unpack_assemble (l, operands[1], sign, false);
2095 ia64_unpack_assemble (h, operands[1], sign, true);
2097 t = expand_binop (wmode, add_optab, l, operands[2], NULL, 0, OPTAB_DIRECT);
2098 t = expand_binop (wmode, add_optab, h, t, operands[0], 0, OPTAB_DIRECT);
2099 if (t != operands[0])
2100 emit_move_insn (operands[0], t);
2103 /* Emit the appropriate sequence for a call. */
2106 ia64_expand_call (rtx retval, rtx addr, rtx nextarg ATTRIBUTE_UNUSED,
2111 addr = XEXP (addr, 0);
2112 addr = convert_memory_address (DImode, addr);
2113 b0 = gen_rtx_REG (DImode, R_BR (0));
2115 /* ??? Should do this for functions known to bind local too. */
2116 if (TARGET_NO_PIC || TARGET_AUTO_PIC)
2119 insn = gen_sibcall_nogp (addr);
2121 insn = gen_call_nogp (addr, b0);
2123 insn = gen_call_value_nogp (retval, addr, b0);
2124 insn = emit_call_insn (insn);
2129 insn = gen_sibcall_gp (addr);
2131 insn = gen_call_gp (addr, b0);
2133 insn = gen_call_value_gp (retval, addr, b0);
2134 insn = emit_call_insn (insn);
2136 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
2140 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), b0);
2142 if (TARGET_ABI_OPEN_VMS)
2143 use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
2144 gen_rtx_REG (DImode, GR_REG (25)));
2148 reg_emitted (enum ia64_frame_regs r)
2150 if (emitted_frame_related_regs[r] == 0)
2151 emitted_frame_related_regs[r] = current_frame_info.r[r];
2153 gcc_assert (emitted_frame_related_regs[r] == current_frame_info.r[r]);
2157 get_reg (enum ia64_frame_regs r)
2160 return current_frame_info.r[r];
2164 is_emitted (int regno)
2168 for (r = reg_fp; r < number_of_ia64_frame_regs; r++)
2169 if (emitted_frame_related_regs[r] == regno)
2175 ia64_reload_gp (void)
2179 if (current_frame_info.r[reg_save_gp])
2181 tmp = gen_rtx_REG (DImode, get_reg (reg_save_gp));
2185 HOST_WIDE_INT offset;
2188 offset = (current_frame_info.spill_cfa_off
2189 + current_frame_info.spill_size);
2190 if (frame_pointer_needed)
2192 tmp = hard_frame_pointer_rtx;
2197 tmp = stack_pointer_rtx;
2198 offset = current_frame_info.total_size - offset;
2201 offset_r = GEN_INT (offset);
2202 if (satisfies_constraint_I (offset_r))
2203 emit_insn (gen_adddi3 (pic_offset_table_rtx, tmp, offset_r));
2206 emit_move_insn (pic_offset_table_rtx, offset_r);
2207 emit_insn (gen_adddi3 (pic_offset_table_rtx,
2208 pic_offset_table_rtx, tmp));
2211 tmp = gen_rtx_MEM (DImode, pic_offset_table_rtx);
2214 emit_move_insn (pic_offset_table_rtx, tmp);
2218 ia64_split_call (rtx retval, rtx addr, rtx retaddr, rtx scratch_r,
2219 rtx scratch_b, int noreturn_p, int sibcall_p)
2222 bool is_desc = false;
2224 /* If we find we're calling through a register, then we're actually
2225 calling through a descriptor, so load up the values. */
2226 if (REG_P (addr) && GR_REGNO_P (REGNO (addr)))
2231 /* ??? We are currently constrained to *not* use peep2, because
2232 we can legitimately change the global lifetime of the GP
2233 (in the form of killing where previously live). This is
2234 because a call through a descriptor doesn't use the previous
2235 value of the GP, while a direct call does, and we do not
2236 commit to either form until the split here.
2238 That said, this means that we lack precise life info for
2239 whether ADDR is dead after this call. This is not terribly
2240 important, since we can fix things up essentially for free
2241 with the POST_DEC below, but it's nice to not use it when we
2242 can immediately tell it's not necessary. */
2243 addr_dead_p = ((noreturn_p || sibcall_p
2244 || TEST_HARD_REG_BIT (regs_invalidated_by_call,
2246 && !FUNCTION_ARG_REGNO_P (REGNO (addr)));
2248 /* Load the code address into scratch_b. */
2249 tmp = gen_rtx_POST_INC (Pmode, addr);
2250 tmp = gen_rtx_MEM (Pmode, tmp);
2251 emit_move_insn (scratch_r, tmp);
2252 emit_move_insn (scratch_b, scratch_r);
2254 /* Load the GP address. If ADDR is not dead here, then we must
2255 revert the change made above via the POST_INCREMENT. */
2257 tmp = gen_rtx_POST_DEC (Pmode, addr);
2260 tmp = gen_rtx_MEM (Pmode, tmp);
2261 emit_move_insn (pic_offset_table_rtx, tmp);
2268 insn = gen_sibcall_nogp (addr);
2270 insn = gen_call_value_nogp (retval, addr, retaddr);
2272 insn = gen_call_nogp (addr, retaddr);
2273 emit_call_insn (insn);
2275 if ((!TARGET_CONST_GP || is_desc) && !noreturn_p && !sibcall_p)
2279 /* Expand an atomic operation. We want to perform MEM <CODE>= VAL atomically.
2281 This differs from the generic code in that we know about the zero-extending
2282 properties of cmpxchg, and the zero-extending requirements of ar.ccv. We
2283 also know that ld.acq+cmpxchg.rel equals a full barrier.
2285 The loop we want to generate looks like
2290 new_reg = cmp_reg op val;
2291 cmp_reg = compare-and-swap(mem, old_reg, new_reg)
2292 if (cmp_reg != old_reg)
2295 Note that we only do the plain load from memory once. Subsequent
2296 iterations use the value loaded by the compare-and-swap pattern. */
2299 ia64_expand_atomic_op (enum rtx_code code, rtx mem, rtx val,
2300 rtx old_dst, rtx new_dst, enum memmodel model)
2302 enum machine_mode mode = GET_MODE (mem);
2303 rtx old_reg, new_reg, cmp_reg, ar_ccv, label;
2304 enum insn_code icode;
2306 /* Special case for using fetchadd. */
2307 if ((mode == SImode || mode == DImode)
2308 && (code == PLUS || code == MINUS)
2309 && fetchadd_operand (val, mode))
2312 val = GEN_INT (-INTVAL (val));
2315 old_dst = gen_reg_rtx (mode);
2319 case MEMMODEL_ACQ_REL:
2320 case MEMMODEL_SEQ_CST:
2321 emit_insn (gen_memory_barrier ());
2323 case MEMMODEL_RELAXED:
2324 case MEMMODEL_ACQUIRE:
2325 case MEMMODEL_CONSUME:
2327 icode = CODE_FOR_fetchadd_acq_si;
2329 icode = CODE_FOR_fetchadd_acq_di;
2331 case MEMMODEL_RELEASE:
2333 icode = CODE_FOR_fetchadd_rel_si;
2335 icode = CODE_FOR_fetchadd_rel_di;
2342 emit_insn (GEN_FCN (icode) (old_dst, mem, val));
2346 new_reg = expand_simple_binop (mode, PLUS, old_dst, val, new_dst,
2348 if (new_reg != new_dst)
2349 emit_move_insn (new_dst, new_reg);
2354 /* Because of the volatile mem read, we get an ld.acq, which is the
2355 front half of the full barrier. The end half is the cmpxchg.rel.
2356 For relaxed and release memory models, we don't need this. But we
2357 also don't bother trying to prevent it either. */
2358 gcc_assert (model == MEMMODEL_RELAXED
2359 || model == MEMMODEL_RELEASE
2360 || MEM_VOLATILE_P (mem));
2362 old_reg = gen_reg_rtx (DImode);
2363 cmp_reg = gen_reg_rtx (DImode);
2364 label = gen_label_rtx ();
2368 val = simplify_gen_subreg (DImode, val, mode, 0);
2369 emit_insn (gen_extend_insn (cmp_reg, mem, DImode, mode, 1));
2372 emit_move_insn (cmp_reg, mem);
2376 ar_ccv = gen_rtx_REG (DImode, AR_CCV_REGNUM);
2377 emit_move_insn (old_reg, cmp_reg);
2378 emit_move_insn (ar_ccv, cmp_reg);
2381 emit_move_insn (old_dst, gen_lowpart (mode, cmp_reg));
2386 new_reg = expand_simple_binop (DImode, AND, new_reg, val, NULL_RTX,
2387 true, OPTAB_DIRECT);
2388 new_reg = expand_simple_unop (DImode, code, new_reg, NULL_RTX, true);
2391 new_reg = expand_simple_binop (DImode, code, new_reg, val, NULL_RTX,
2392 true, OPTAB_DIRECT);
2395 new_reg = gen_lowpart (mode, new_reg);
2397 emit_move_insn (new_dst, new_reg);
2401 case MEMMODEL_RELAXED:
2402 case MEMMODEL_ACQUIRE:
2403 case MEMMODEL_CONSUME:
2406 case QImode: icode = CODE_FOR_cmpxchg_acq_qi; break;
2407 case HImode: icode = CODE_FOR_cmpxchg_acq_hi; break;
2408 case SImode: icode = CODE_FOR_cmpxchg_acq_si; break;
2409 case DImode: icode = CODE_FOR_cmpxchg_acq_di; break;
2415 case MEMMODEL_RELEASE:
2416 case MEMMODEL_ACQ_REL:
2417 case MEMMODEL_SEQ_CST:
2420 case QImode: icode = CODE_FOR_cmpxchg_rel_qi; break;
2421 case HImode: icode = CODE_FOR_cmpxchg_rel_hi; break;
2422 case SImode: icode = CODE_FOR_cmpxchg_rel_si; break;
2423 case DImode: icode = CODE_FOR_cmpxchg_rel_di; break;
2433 emit_insn (GEN_FCN (icode) (cmp_reg, mem, ar_ccv, new_reg));
2435 emit_cmp_and_jump_insns (cmp_reg, old_reg, NE, NULL, DImode, true, label);
2438 /* Begin the assembly file. */
2441 ia64_file_start (void)
2443 default_file_start ();
2444 emit_safe_across_calls ();
2448 emit_safe_across_calls (void)
2450 unsigned int rs, re;
2457 while (rs < 64 && call_used_regs[PR_REG (rs)])
2461 for (re = rs + 1; re < 64 && ! call_used_regs[PR_REG (re)]; re++)
2465 fputs ("\t.pred.safe_across_calls ", asm_out_file);
2469 fputc (',', asm_out_file);
2471 fprintf (asm_out_file, "p%u", rs);
2473 fprintf (asm_out_file, "p%u-p%u", rs, re - 1);
2477 fputc ('\n', asm_out_file);
2480 /* Globalize a declaration. */
2483 ia64_globalize_decl_name (FILE * stream, tree decl)
2485 const char *name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
2486 tree version_attr = lookup_attribute ("version_id", DECL_ATTRIBUTES (decl));
2489 tree v = TREE_VALUE (TREE_VALUE (version_attr));
2490 const char *p = TREE_STRING_POINTER (v);
2491 fprintf (stream, "\t.alias %s#, \"%s{%s}\"\n", name, name, p);
2493 targetm.asm_out.globalize_label (stream, name);
2494 if (TREE_CODE (decl) == FUNCTION_DECL)
2495 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "function");
2498 /* Helper function for ia64_compute_frame_size: find an appropriate general
2499 register to spill some special register to. SPECIAL_SPILL_MASK contains
2500 bits in GR0 to GR31 that have already been allocated by this routine.
2501 TRY_LOCALS is true if we should attempt to locate a local regnum. */
2504 find_gr_spill (enum ia64_frame_regs r, int try_locals)
2508 if (emitted_frame_related_regs[r] != 0)
2510 regno = emitted_frame_related_regs[r];
2511 if (regno >= LOC_REG (0) && regno < LOC_REG (80 - frame_pointer_needed)
2512 && current_frame_info.n_local_regs < regno - LOC_REG (0) + 1)
2513 current_frame_info.n_local_regs = regno - LOC_REG (0) + 1;
2514 else if (crtl->is_leaf
2515 && regno >= GR_REG (1) && regno <= GR_REG (31))
2516 current_frame_info.gr_used_mask |= 1 << regno;
2521 /* If this is a leaf function, first try an otherwise unused
2522 call-clobbered register. */
2525 for (regno = GR_REG (1); regno <= GR_REG (31); regno++)
2526 if (! df_regs_ever_live_p (regno)
2527 && call_used_regs[regno]
2528 && ! fixed_regs[regno]
2529 && ! global_regs[regno]
2530 && ((current_frame_info.gr_used_mask >> regno) & 1) == 0
2531 && ! is_emitted (regno))
2533 current_frame_info.gr_used_mask |= 1 << regno;
2540 regno = current_frame_info.n_local_regs;
2541 /* If there is a frame pointer, then we can't use loc79, because
2542 that is HARD_FRAME_POINTER_REGNUM. In particular, see the
2543 reg_name switching code in ia64_expand_prologue. */
2544 while (regno < (80 - frame_pointer_needed))
2545 if (! is_emitted (LOC_REG (regno++)))
2547 current_frame_info.n_local_regs = regno;
2548 return LOC_REG (regno - 1);
2552 /* Failed to find a general register to spill to. Must use stack. */
2556 /* In order to make for nice schedules, we try to allocate every temporary
2557 to a different register. We must of course stay away from call-saved,
2558 fixed, and global registers. We must also stay away from registers
2559 allocated in current_frame_info.gr_used_mask, since those include regs
2560 used all through the prologue.
2562 Any register allocated here must be used immediately. The idea is to
2563 aid scheduling, not to solve data flow problems. */
2565 static int last_scratch_gr_reg;
2568 next_scratch_gr_reg (void)
2572 for (i = 0; i < 32; ++i)
2574 regno = (last_scratch_gr_reg + i + 1) & 31;
2575 if (call_used_regs[regno]
2576 && ! fixed_regs[regno]
2577 && ! global_regs[regno]
2578 && ((current_frame_info.gr_used_mask >> regno) & 1) == 0)
2580 last_scratch_gr_reg = regno;
2585 /* There must be _something_ available. */
2589 /* Helper function for ia64_compute_frame_size, called through
2590 diddle_return_value. Mark REG in current_frame_info.gr_used_mask. */
2593 mark_reg_gr_used_mask (rtx reg, void *data ATTRIBUTE_UNUSED)
2595 unsigned int regno = REGNO (reg);
2598 unsigned int i, n = hard_regno_nregs[regno][GET_MODE (reg)];
2599 for (i = 0; i < n; ++i)
2600 current_frame_info.gr_used_mask |= 1 << (regno + i);
2605 /* Returns the number of bytes offset between the frame pointer and the stack
2606 pointer for the current function. SIZE is the number of bytes of space
2607 needed for local variables. */
2610 ia64_compute_frame_size (HOST_WIDE_INT size)
2612 HOST_WIDE_INT total_size;
2613 HOST_WIDE_INT spill_size = 0;
2614 HOST_WIDE_INT extra_spill_size = 0;
2615 HOST_WIDE_INT pretend_args_size;
2618 int spilled_gr_p = 0;
2619 int spilled_fr_p = 0;
2625 if (current_frame_info.initialized)
2628 memset (¤t_frame_info, 0, sizeof current_frame_info);
2629 CLEAR_HARD_REG_SET (mask);
2631 /* Don't allocate scratches to the return register. */
2632 diddle_return_value (mark_reg_gr_used_mask, NULL);
2634 /* Don't allocate scratches to the EH scratch registers. */
2635 if (cfun->machine->ia64_eh_epilogue_sp)
2636 mark_reg_gr_used_mask (cfun->machine->ia64_eh_epilogue_sp, NULL);
2637 if (cfun->machine->ia64_eh_epilogue_bsp)
2638 mark_reg_gr_used_mask (cfun->machine->ia64_eh_epilogue_bsp, NULL);
2640 /* Static stack checking uses r2 and r3. */
2641 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK)
2642 current_frame_info.gr_used_mask |= 0xc;
2644 /* Find the size of the register stack frame. We have only 80 local
2645 registers, because we reserve 8 for the inputs and 8 for the
2648 /* Skip HARD_FRAME_POINTER_REGNUM (loc79) when frame_pointer_needed,
2649 since we'll be adjusting that down later. */
2650 regno = LOC_REG (78) + ! frame_pointer_needed;
2651 for (; regno >= LOC_REG (0); regno--)
2652 if (df_regs_ever_live_p (regno) && !is_emitted (regno))
2654 current_frame_info.n_local_regs = regno - LOC_REG (0) + 1;
2656 /* For functions marked with the syscall_linkage attribute, we must mark
2657 all eight input registers as in use, so that locals aren't visible to
2660 if (cfun->machine->n_varargs > 0
2661 || lookup_attribute ("syscall_linkage",
2662 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
2663 current_frame_info.n_input_regs = 8;
2666 for (regno = IN_REG (7); regno >= IN_REG (0); regno--)
2667 if (df_regs_ever_live_p (regno))
2669 current_frame_info.n_input_regs = regno - IN_REG (0) + 1;
2672 for (regno = OUT_REG (7); regno >= OUT_REG (0); regno--)
2673 if (df_regs_ever_live_p (regno))
2675 i = regno - OUT_REG (0) + 1;
2677 #ifndef PROFILE_HOOK
2678 /* When -p profiling, we need one output register for the mcount argument.
2679 Likewise for -a profiling for the bb_init_func argument. For -ax
2680 profiling, we need two output registers for the two bb_init_trace_func
2685 current_frame_info.n_output_regs = i;
2687 /* ??? No rotating register support yet. */
2688 current_frame_info.n_rotate_regs = 0;
2690 /* Discover which registers need spilling, and how much room that
2691 will take. Begin with floating point and general registers,
2692 which will always wind up on the stack. */
2694 for (regno = FR_REG (2); regno <= FR_REG (127); regno++)
2695 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
2697 SET_HARD_REG_BIT (mask, regno);
2703 for (regno = GR_REG (1); regno <= GR_REG (31); regno++)
2704 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
2706 SET_HARD_REG_BIT (mask, regno);
2712 for (regno = BR_REG (1); regno <= BR_REG (7); regno++)
2713 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
2715 SET_HARD_REG_BIT (mask, regno);
2720 /* Now come all special registers that might get saved in other
2721 general registers. */
2723 if (frame_pointer_needed)
2725 current_frame_info.r[reg_fp] = find_gr_spill (reg_fp, 1);
2726 /* If we did not get a register, then we take LOC79. This is guaranteed
2727 to be free, even if regs_ever_live is already set, because this is
2728 HARD_FRAME_POINTER_REGNUM. This requires incrementing n_local_regs,
2729 as we don't count loc79 above. */
2730 if (current_frame_info.r[reg_fp] == 0)
2732 current_frame_info.r[reg_fp] = LOC_REG (79);
2733 current_frame_info.n_local_regs = LOC_REG (79) - LOC_REG (0) + 1;
2737 if (! crtl->is_leaf)
2739 /* Emit a save of BR0 if we call other functions. Do this even
2740 if this function doesn't return, as EH depends on this to be
2741 able to unwind the stack. */
2742 SET_HARD_REG_BIT (mask, BR_REG (0));
2744 current_frame_info.r[reg_save_b0] = find_gr_spill (reg_save_b0, 1);
2745 if (current_frame_info.r[reg_save_b0] == 0)
2747 extra_spill_size += 8;
2751 /* Similarly for ar.pfs. */
2752 SET_HARD_REG_BIT (mask, AR_PFS_REGNUM);
2753 current_frame_info.r[reg_save_ar_pfs] = find_gr_spill (reg_save_ar_pfs, 1);
2754 if (current_frame_info.r[reg_save_ar_pfs] == 0)
2756 extra_spill_size += 8;
2760 /* Similarly for gp. Note that if we're calling setjmp, the stacked
2761 registers are clobbered, so we fall back to the stack. */
2762 current_frame_info.r[reg_save_gp]
2763 = (cfun->calls_setjmp ? 0 : find_gr_spill (reg_save_gp, 1));
2764 if (current_frame_info.r[reg_save_gp] == 0)
2766 SET_HARD_REG_BIT (mask, GR_REG (1));
2773 if (df_regs_ever_live_p (BR_REG (0)) && ! call_used_regs[BR_REG (0)])
2775 SET_HARD_REG_BIT (mask, BR_REG (0));
2776 extra_spill_size += 8;
2780 if (df_regs_ever_live_p (AR_PFS_REGNUM))
2782 SET_HARD_REG_BIT (mask, AR_PFS_REGNUM);
2783 current_frame_info.r[reg_save_ar_pfs]
2784 = find_gr_spill (reg_save_ar_pfs, 1);
2785 if (current_frame_info.r[reg_save_ar_pfs] == 0)
2787 extra_spill_size += 8;
2793 /* Unwind descriptor hackery: things are most efficient if we allocate
2794 consecutive GR save registers for RP, PFS, FP in that order. However,
2795 it is absolutely critical that FP get the only hard register that's
2796 guaranteed to be free, so we allocated it first. If all three did
2797 happen to be allocated hard regs, and are consecutive, rearrange them
2798 into the preferred order now.
2800 If we have already emitted code for any of those registers,
2801 then it's already too late to change. */
2802 min_regno = MIN (current_frame_info.r[reg_fp],
2803 MIN (current_frame_info.r[reg_save_b0],
2804 current_frame_info.r[reg_save_ar_pfs]));
2805 max_regno = MAX (current_frame_info.r[reg_fp],
2806 MAX (current_frame_info.r[reg_save_b0],
2807 current_frame_info.r[reg_save_ar_pfs]));
2809 && min_regno + 2 == max_regno
2810 && (current_frame_info.r[reg_fp] == min_regno + 1
2811 || current_frame_info.r[reg_save_b0] == min_regno + 1
2812 || current_frame_info.r[reg_save_ar_pfs] == min_regno + 1)
2813 && (emitted_frame_related_regs[reg_save_b0] == 0
2814 || emitted_frame_related_regs[reg_save_b0] == min_regno)
2815 && (emitted_frame_related_regs[reg_save_ar_pfs] == 0
2816 || emitted_frame_related_regs[reg_save_ar_pfs] == min_regno + 1)
2817 && (emitted_frame_related_regs[reg_fp] == 0
2818 || emitted_frame_related_regs[reg_fp] == min_regno + 2))
2820 current_frame_info.r[reg_save_b0] = min_regno;
2821 current_frame_info.r[reg_save_ar_pfs] = min_regno + 1;
2822 current_frame_info.r[reg_fp] = min_regno + 2;
2825 /* See if we need to store the predicate register block. */
2826 for (regno = PR_REG (0); regno <= PR_REG (63); regno++)
2827 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
2829 if (regno <= PR_REG (63))
2831 SET_HARD_REG_BIT (mask, PR_REG (0));
2832 current_frame_info.r[reg_save_pr] = find_gr_spill (reg_save_pr, 1);
2833 if (current_frame_info.r[reg_save_pr] == 0)
2835 extra_spill_size += 8;
2839 /* ??? Mark them all as used so that register renaming and such
2840 are free to use them. */
2841 for (regno = PR_REG (0); regno <= PR_REG (63); regno++)
2842 df_set_regs_ever_live (regno, true);
2845 /* If we're forced to use st8.spill, we're forced to save and restore
2846 ar.unat as well. The check for existing liveness allows inline asm
2847 to touch ar.unat. */
2848 if (spilled_gr_p || cfun->machine->n_varargs
2849 || df_regs_ever_live_p (AR_UNAT_REGNUM))
2851 df_set_regs_ever_live (AR_UNAT_REGNUM, true);
2852 SET_HARD_REG_BIT (mask, AR_UNAT_REGNUM);
2853 current_frame_info.r[reg_save_ar_unat]
2854 = find_gr_spill (reg_save_ar_unat, spill_size == 0);
2855 if (current_frame_info.r[reg_save_ar_unat] == 0)
2857 extra_spill_size += 8;
2862 if (df_regs_ever_live_p (AR_LC_REGNUM))
2864 SET_HARD_REG_BIT (mask, AR_LC_REGNUM);
2865 current_frame_info.r[reg_save_ar_lc]
2866 = find_gr_spill (reg_save_ar_lc, spill_size == 0);
2867 if (current_frame_info.r[reg_save_ar_lc] == 0)
2869 extra_spill_size += 8;
2874 /* If we have an odd number of words of pretend arguments written to
2875 the stack, then the FR save area will be unaligned. We round the
2876 size of this area up to keep things 16 byte aligned. */
2878 pretend_args_size = IA64_STACK_ALIGN (crtl->args.pretend_args_size);
2880 pretend_args_size = crtl->args.pretend_args_size;
2882 total_size = (spill_size + extra_spill_size + size + pretend_args_size
2883 + crtl->outgoing_args_size);
2884 total_size = IA64_STACK_ALIGN (total_size);
2886 /* We always use the 16-byte scratch area provided by the caller, but
2887 if we are a leaf function, there's no one to which we need to provide
2890 total_size = MAX (0, total_size - 16);
2892 current_frame_info.total_size = total_size;
2893 current_frame_info.spill_cfa_off = pretend_args_size - 16;
2894 current_frame_info.spill_size = spill_size;
2895 current_frame_info.extra_spill_size = extra_spill_size;
2896 COPY_HARD_REG_SET (current_frame_info.mask, mask);
2897 current_frame_info.n_spilled = n_spilled;
2898 current_frame_info.initialized = reload_completed;
2901 /* Worker function for TARGET_CAN_ELIMINATE. */
2904 ia64_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
2906 return (to == BR_REG (0) ? crtl->is_leaf : true);
2909 /* Compute the initial difference between the specified pair of registers. */
2912 ia64_initial_elimination_offset (int from, int to)
2914 HOST_WIDE_INT offset;
2916 ia64_compute_frame_size (get_frame_size ());
2919 case FRAME_POINTER_REGNUM:
2922 case HARD_FRAME_POINTER_REGNUM:
2924 offset = -current_frame_info.total_size;
2926 offset = -(current_frame_info.total_size
2927 - crtl->outgoing_args_size - 16);
2930 case STACK_POINTER_REGNUM:
2934 offset = 16 + crtl->outgoing_args_size;
2942 case ARG_POINTER_REGNUM:
2943 /* Arguments start above the 16 byte save area, unless stdarg
2944 in which case we store through the 16 byte save area. */
2947 case HARD_FRAME_POINTER_REGNUM:
2948 offset = 16 - crtl->args.pretend_args_size;
2951 case STACK_POINTER_REGNUM:
2952 offset = (current_frame_info.total_size
2953 + 16 - crtl->args.pretend_args_size);
2968 /* If there are more than a trivial number of register spills, we use
2969 two interleaved iterators so that we can get two memory references
2972 In order to simplify things in the prologue and epilogue expanders,
2973 we use helper functions to fix up the memory references after the
2974 fact with the appropriate offsets to a POST_MODIFY memory mode.
2975 The following data structure tracks the state of the two iterators
2976 while insns are being emitted. */
2978 struct spill_fill_data
2980 rtx init_after; /* point at which to emit initializations */
2981 rtx init_reg[2]; /* initial base register */
2982 rtx iter_reg[2]; /* the iterator registers */
2983 rtx *prev_addr[2]; /* address of last memory use */
2984 rtx prev_insn[2]; /* the insn corresponding to prev_addr */
2985 HOST_WIDE_INT prev_off[2]; /* last offset */
2986 int n_iter; /* number of iterators in use */
2987 int next_iter; /* next iterator to use */
2988 unsigned int save_gr_used_mask;
2991 static struct spill_fill_data spill_fill_data;
2994 setup_spill_pointers (int n_spills, rtx init_reg, HOST_WIDE_INT cfa_off)
2998 spill_fill_data.init_after = get_last_insn ();
2999 spill_fill_data.init_reg[0] = init_reg;
3000 spill_fill_data.init_reg[1] = init_reg;
3001 spill_fill_data.prev_addr[0] = NULL;
3002 spill_fill_data.prev_addr[1] = NULL;
3003 spill_fill_data.prev_insn[0] = NULL;
3004 spill_fill_data.prev_insn[1] = NULL;
3005 spill_fill_data.prev_off[0] = cfa_off;
3006 spill_fill_data.prev_off[1] = cfa_off;
3007 spill_fill_data.next_iter = 0;
3008 spill_fill_data.save_gr_used_mask = current_frame_info.gr_used_mask;
3010 spill_fill_data.n_iter = 1 + (n_spills > 2);
3011 for (i = 0; i < spill_fill_data.n_iter; ++i)
3013 int regno = next_scratch_gr_reg ();
3014 spill_fill_data.iter_reg[i] = gen_rtx_REG (DImode, regno);
3015 current_frame_info.gr_used_mask |= 1 << regno;
3020 finish_spill_pointers (void)
3022 current_frame_info.gr_used_mask = spill_fill_data.save_gr_used_mask;
3026 spill_restore_mem (rtx reg, HOST_WIDE_INT cfa_off)
3028 int iter = spill_fill_data.next_iter;
3029 HOST_WIDE_INT disp = spill_fill_data.prev_off[iter] - cfa_off;
3030 rtx disp_rtx = GEN_INT (disp);
3033 if (spill_fill_data.prev_addr[iter])
3035 if (satisfies_constraint_N (disp_rtx))
3037 *spill_fill_data.prev_addr[iter]
3038 = gen_rtx_POST_MODIFY (DImode, spill_fill_data.iter_reg[iter],
3039 gen_rtx_PLUS (DImode,
3040 spill_fill_data.iter_reg[iter],
3042 add_reg_note (spill_fill_data.prev_insn[iter],
3043 REG_INC, spill_fill_data.iter_reg[iter]);
3047 /* ??? Could use register post_modify for loads. */
3048 if (!satisfies_constraint_I (disp_rtx))
3050 rtx tmp = gen_rtx_REG (DImode, next_scratch_gr_reg ());
3051 emit_move_insn (tmp, disp_rtx);
3054 emit_insn (gen_adddi3 (spill_fill_data.iter_reg[iter],
3055 spill_fill_data.iter_reg[iter], disp_rtx));
3058 /* Micro-optimization: if we've created a frame pointer, it's at
3059 CFA 0, which may allow the real iterator to be initialized lower,
3060 slightly increasing parallelism. Also, if there are few saves
3061 it may eliminate the iterator entirely. */
3063 && spill_fill_data.init_reg[iter] == stack_pointer_rtx
3064 && frame_pointer_needed)
3066 mem = gen_rtx_MEM (GET_MODE (reg), hard_frame_pointer_rtx);
3067 set_mem_alias_set (mem, get_varargs_alias_set ());
3075 seq = gen_movdi (spill_fill_data.iter_reg[iter],
3076 spill_fill_data.init_reg[iter]);
3081 if (!satisfies_constraint_I (disp_rtx))
3083 rtx tmp = gen_rtx_REG (DImode, next_scratch_gr_reg ());
3084 emit_move_insn (tmp, disp_rtx);
3088 emit_insn (gen_adddi3 (spill_fill_data.iter_reg[iter],
3089 spill_fill_data.init_reg[iter],
3096 /* Careful for being the first insn in a sequence. */
3097 if (spill_fill_data.init_after)
3098 insn = emit_insn_after (seq, spill_fill_data.init_after);
3101 rtx first = get_insns ();
3103 insn = emit_insn_before (seq, first);
3105 insn = emit_insn (seq);
3107 spill_fill_data.init_after = insn;
3110 mem = gen_rtx_MEM (GET_MODE (reg), spill_fill_data.iter_reg[iter]);
3112 /* ??? Not all of the spills are for varargs, but some of them are.
3113 The rest of the spills belong in an alias set of their own. But
3114 it doesn't actually hurt to include them here. */
3115 set_mem_alias_set (mem, get_varargs_alias_set ());
3117 spill_fill_data.prev_addr[iter] = &XEXP (mem, 0);
3118 spill_fill_data.prev_off[iter] = cfa_off;
3120 if (++iter >= spill_fill_data.n_iter)
3122 spill_fill_data.next_iter = iter;
3128 do_spill (rtx (*move_fn) (rtx, rtx, rtx), rtx reg, HOST_WIDE_INT cfa_off,
3131 int iter = spill_fill_data.next_iter;
3134 mem = spill_restore_mem (reg, cfa_off);
3135 insn = emit_insn ((*move_fn) (mem, reg, GEN_INT (cfa_off)));
3136 spill_fill_data.prev_insn[iter] = insn;
3143 RTX_FRAME_RELATED_P (insn) = 1;
3145 /* Don't even pretend that the unwind code can intuit its way
3146 through a pair of interleaved post_modify iterators. Just
3147 provide the correct answer. */
3149 if (frame_pointer_needed)
3151 base = hard_frame_pointer_rtx;
3156 base = stack_pointer_rtx;
3157 off = current_frame_info.total_size - cfa_off;
3160 add_reg_note (insn, REG_CFA_OFFSET,
3161 gen_rtx_SET (VOIDmode,
3162 gen_rtx_MEM (GET_MODE (reg),
3163 plus_constant (Pmode,
3170 do_restore (rtx (*move_fn) (rtx, rtx, rtx), rtx reg, HOST_WIDE_INT cfa_off)
3172 int iter = spill_fill_data.next_iter;
3175 insn = emit_insn ((*move_fn) (reg, spill_restore_mem (reg, cfa_off),
3176 GEN_INT (cfa_off)));
3177 spill_fill_data.prev_insn[iter] = insn;
3180 /* Wrapper functions that discards the CONST_INT spill offset. These
3181 exist so that we can give gr_spill/gr_fill the offset they need and
3182 use a consistent function interface. */
3185 gen_movdi_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED)
3187 return gen_movdi (dest, src);
3191 gen_fr_spill_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED)
3193 return gen_fr_spill (dest, src);
3197 gen_fr_restore_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED)
3199 return gen_fr_restore (dest, src);
3202 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
3204 /* See Table 6.2 of the IA-64 Software Developer Manual, Volume 2. */
3205 #define BACKING_STORE_SIZE(N) ((N) > 0 ? ((N) + (N)/63 + 1) * 8 : 0)
3207 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
3208 inclusive. These are offsets from the current stack pointer. SOL is the
3209 size of local registers. ??? This clobbers r2 and r3. */
3212 ia64_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size, int sol)
3214 /* On the IA-64 there is a second stack in memory, namely the Backing Store
3215 of the Register Stack Engine. We also need to probe it after checking
3216 that the 2 stacks don't overlap. */
3217 const int bs_size = BACKING_STORE_SIZE (sol);
3218 rtx r2 = gen_rtx_REG (Pmode, GR_REG (2));
3219 rtx r3 = gen_rtx_REG (Pmode, GR_REG (3));
3221 /* Detect collision of the 2 stacks if necessary. */
3222 if (bs_size > 0 || size > 0)
3224 rtx p6 = gen_rtx_REG (BImode, PR_REG (6));
3226 emit_insn (gen_bsp_value (r3));
3227 emit_move_insn (r2, GEN_INT (-(first + size)));
3229 /* Compare current value of BSP and SP registers. */
3230 emit_insn (gen_rtx_SET (VOIDmode, p6,
3231 gen_rtx_fmt_ee (LTU, BImode,
3232 r3, stack_pointer_rtx)));
3234 /* Compute the address of the probe for the Backing Store (which grows
3235 towards higher addresses). We probe only at the first offset of
3236 the next page because some OS (eg Linux/ia64) only extend the
3237 backing store when this specific address is hit (but generate a SEGV
3238 on other address). Page size is the worst case (4KB). The reserve
3239 size is at least 4096 - (96 + 2) * 8 = 3312 bytes, which is enough.
3240 Also compute the address of the last probe for the memory stack
3241 (which grows towards lower addresses). */
3242 emit_insn (gen_rtx_SET (VOIDmode, r3, plus_constant (Pmode, r3, 4095)));
3243 emit_insn (gen_rtx_SET (VOIDmode, r2,
3244 gen_rtx_PLUS (Pmode, stack_pointer_rtx, r2)));
3246 /* Compare them and raise SEGV if the former has topped the latter. */
3247 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
3248 gen_rtx_fmt_ee (NE, VOIDmode, p6,
3250 gen_rtx_SET (VOIDmode, p6,
3251 gen_rtx_fmt_ee (GEU, BImode,
3253 emit_insn (gen_rtx_SET (VOIDmode,
3254 gen_rtx_ZERO_EXTRACT (DImode, r3, GEN_INT (12),
3257 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
3258 gen_rtx_fmt_ee (NE, VOIDmode, p6,
3260 gen_rtx_TRAP_IF (VOIDmode, const1_rtx,
3264 /* Probe the Backing Store if necessary. */
3266 emit_stack_probe (r3);
3268 /* Probe the memory stack if necessary. */
3272 /* See if we have a constant small number of probes to generate. If so,
3273 that's the easy case. */
3274 else if (size <= PROBE_INTERVAL)
3275 emit_stack_probe (r2);
3277 /* The run-time loop is made up of 8 insns in the generic case while this
3278 compile-time loop is made up of 5+2*(n-2) insns for n # of intervals. */
3279 else if (size <= 4 * PROBE_INTERVAL)
3283 emit_move_insn (r2, GEN_INT (-(first + PROBE_INTERVAL)));
3284 emit_insn (gen_rtx_SET (VOIDmode, r2,
3285 gen_rtx_PLUS (Pmode, stack_pointer_rtx, r2)));
3286 emit_stack_probe (r2);
3288 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
3289 it exceeds SIZE. If only two probes are needed, this will not
3290 generate any code. Then probe at FIRST + SIZE. */
3291 for (i = 2 * PROBE_INTERVAL; i < size; i += PROBE_INTERVAL)
3293 emit_insn (gen_rtx_SET (VOIDmode, r2,
3294 plus_constant (Pmode, r2, -PROBE_INTERVAL)));
3295 emit_stack_probe (r2);
3298 emit_insn (gen_rtx_SET (VOIDmode, r2,
3299 plus_constant (Pmode, r2,
3300 (i - PROBE_INTERVAL) - size)));
3301 emit_stack_probe (r2);
3304 /* Otherwise, do the same as above, but in a loop. Note that we must be
3305 extra careful with variables wrapping around because we might be at
3306 the very top (or the very bottom) of the address space and we have
3307 to be able to handle this case properly; in particular, we use an
3308 equality test for the loop condition. */
3311 HOST_WIDE_INT rounded_size;
3313 emit_move_insn (r2, GEN_INT (-first));
3316 /* Step 1: round SIZE to the previous multiple of the interval. */
3318 rounded_size = size & -PROBE_INTERVAL;
3321 /* Step 2: compute initial and final value of the loop counter. */
3323 /* TEST_ADDR = SP + FIRST. */
3324 emit_insn (gen_rtx_SET (VOIDmode, r2,
3325 gen_rtx_PLUS (Pmode, stack_pointer_rtx, r2)));
3327 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
3328 if (rounded_size > (1 << 21))
3330 emit_move_insn (r3, GEN_INT (-rounded_size));
3331 emit_insn (gen_rtx_SET (VOIDmode, r3, gen_rtx_PLUS (Pmode, r2, r3)));
3334 emit_insn (gen_rtx_SET (VOIDmode, r3,
3335 gen_rtx_PLUS (Pmode, r2,
3336 GEN_INT (-rounded_size))));
3341 while (TEST_ADDR != LAST_ADDR)
3343 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
3347 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
3348 until it is equal to ROUNDED_SIZE. */
3350 emit_insn (gen_probe_stack_range (r2, r2, r3));
3353 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
3354 that SIZE is equal to ROUNDED_SIZE. */
3356 /* TEMP = SIZE - ROUNDED_SIZE. */
3357 if (size != rounded_size)
3359 emit_insn (gen_rtx_SET (VOIDmode, r2,
3360 plus_constant (Pmode, r2,
3361 rounded_size - size)));
3362 emit_stack_probe (r2);
3366 /* Make sure nothing is scheduled before we are done. */
3367 emit_insn (gen_blockage ());
3370 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
3371 absolute addresses. */
3374 output_probe_stack_range (rtx reg1, rtx reg2)
3376 static int labelno = 0;
3377 char loop_lab[32], end_lab[32];
3380 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno);
3381 ASM_GENERATE_INTERNAL_LABEL (end_lab, "LPSRE", labelno++);
3383 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
3385 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
3388 xops[2] = gen_rtx_REG (BImode, PR_REG (6));
3389 output_asm_insn ("cmp.eq %2, %I2 = %0, %1", xops);
3390 fprintf (asm_out_file, "\t(%s) br.cond.dpnt ", reg_names [REGNO (xops[2])]);
3391 assemble_name_raw (asm_out_file, end_lab);
3392 fputc ('\n', asm_out_file);
3394 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
3395 xops[1] = GEN_INT (-PROBE_INTERVAL);
3396 output_asm_insn ("addl %0 = %1, %0", xops);
3397 fputs ("\t;;\n", asm_out_file);
3399 /* Probe at TEST_ADDR and branch. */
3400 output_asm_insn ("probe.w.fault %0, 0", xops);
3401 fprintf (asm_out_file, "\tbr ");
3402 assemble_name_raw (asm_out_file, loop_lab);
3403 fputc ('\n', asm_out_file);
3405 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, end_lab);
3410 /* Called after register allocation to add any instructions needed for the
3411 prologue. Using a prologue insn is favored compared to putting all of the
3412 instructions in output_function_prologue(), since it allows the scheduler
3413 to intermix instructions with the saves of the caller saved registers. In
3414 some cases, it might be necessary to emit a barrier instruction as the last
3415 insn to prevent such scheduling.
3417 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
3418 so that the debug info generation code can handle them properly.
3420 The register save area is laid out like so:
3422 [ varargs spill area ]
3423 [ fr register spill area ]
3424 [ br register spill area ]
3425 [ ar register spill area ]
3426 [ pr register spill area ]
3427 [ gr register spill area ] */
3429 /* ??? Get inefficient code when the frame size is larger than can fit in an
3430 adds instruction. */
3433 ia64_expand_prologue (void)
3435 rtx insn, ar_pfs_save_reg, ar_unat_save_reg;
3436 int i, epilogue_p, regno, alt_regno, cfa_off, n_varargs;
3439 ia64_compute_frame_size (get_frame_size ());
3440 last_scratch_gr_reg = 15;
3442 if (flag_stack_usage_info)
3443 current_function_static_stack_size = current_frame_info.total_size;
3445 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK)
3446 ia64_emit_probe_stack_range (STACK_CHECK_PROTECT,
3447 current_frame_info.total_size,
3448 current_frame_info.n_input_regs
3449 + current_frame_info.n_local_regs);
3453 fprintf (dump_file, "ia64 frame related registers "
3454 "recorded in current_frame_info.r[]:\n");
3455 #define PRINTREG(a) if (current_frame_info.r[a]) \
3456 fprintf(dump_file, "%s = %d\n", #a, current_frame_info.r[a])
3458 PRINTREG(reg_save_b0);
3459 PRINTREG(reg_save_pr);
3460 PRINTREG(reg_save_ar_pfs);
3461 PRINTREG(reg_save_ar_unat);
3462 PRINTREG(reg_save_ar_lc);
3463 PRINTREG(reg_save_gp);
3467 /* If there is no epilogue, then we don't need some prologue insns.
3468 We need to avoid emitting the dead prologue insns, because flow
3469 will complain about them. */
3475 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
3476 if ((e->flags & EDGE_FAKE) == 0
3477 && (e->flags & EDGE_FALLTHRU) != 0)
3479 epilogue_p = (e != NULL);
3484 /* Set the local, input, and output register names. We need to do this
3485 for GNU libc, which creates crti.S/crtn.S by splitting initfini.c in
3486 half. If we use in/loc/out register names, then we get assembler errors
3487 in crtn.S because there is no alloc insn or regstk directive in there. */
3488 if (! TARGET_REG_NAMES)
3490 int inputs = current_frame_info.n_input_regs;
3491 int locals = current_frame_info.n_local_regs;
3492 int outputs = current_frame_info.n_output_regs;
3494 for (i = 0; i < inputs; i++)
3495 reg_names[IN_REG (i)] = ia64_reg_numbers[i];
3496 for (i = 0; i < locals; i++)
3497 reg_names[LOC_REG (i)] = ia64_reg_numbers[inputs + i];
3498 for (i = 0; i < outputs; i++)
3499 reg_names[OUT_REG (i)] = ia64_reg_numbers[inputs + locals + i];
3502 /* Set the frame pointer register name. The regnum is logically loc79,
3503 but of course we'll not have allocated that many locals. Rather than
3504 worrying about renumbering the existing rtxs, we adjust the name. */
3505 /* ??? This code means that we can never use one local register when
3506 there is a frame pointer. loc79 gets wasted in this case, as it is
3507 renamed to a register that will never be used. See also the try_locals
3508 code in find_gr_spill. */
3509 if (current_frame_info.r[reg_fp])
3511 const char *tmp = reg_names[HARD_FRAME_POINTER_REGNUM];
3512 reg_names[HARD_FRAME_POINTER_REGNUM]
3513 = reg_names[current_frame_info.r[reg_fp]];
3514 reg_names[current_frame_info.r[reg_fp]] = tmp;
3517 /* We don't need an alloc instruction if we've used no outputs or locals. */
3518 if (current_frame_info.n_local_regs == 0
3519 && current_frame_info.n_output_regs == 0
3520 && current_frame_info.n_input_regs <= crtl->args.info.int_regs
3521 && !TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM))
3523 /* If there is no alloc, but there are input registers used, then we
3524 need a .regstk directive. */
3525 current_frame_info.need_regstk = (TARGET_REG_NAMES != 0);
3526 ar_pfs_save_reg = NULL_RTX;
3530 current_frame_info.need_regstk = 0;
3532 if (current_frame_info.r[reg_save_ar_pfs])
3534 regno = current_frame_info.r[reg_save_ar_pfs];
3535 reg_emitted (reg_save_ar_pfs);
3538 regno = next_scratch_gr_reg ();
3539 ar_pfs_save_reg = gen_rtx_REG (DImode, regno);
3541 insn = emit_insn (gen_alloc (ar_pfs_save_reg,
3542 GEN_INT (current_frame_info.n_input_regs),
3543 GEN_INT (current_frame_info.n_local_regs),
3544 GEN_INT (current_frame_info.n_output_regs),
3545 GEN_INT (current_frame_info.n_rotate_regs)));
3546 if (current_frame_info.r[reg_save_ar_pfs])
3548 RTX_FRAME_RELATED_P (insn) = 1;
3549 add_reg_note (insn, REG_CFA_REGISTER,
3550 gen_rtx_SET (VOIDmode,
3552 gen_rtx_REG (DImode, AR_PFS_REGNUM)));
3556 /* Set up frame pointer, stack pointer, and spill iterators. */
3558 n_varargs = cfun->machine->n_varargs;
3559 setup_spill_pointers (current_frame_info.n_spilled + n_varargs,
3560 stack_pointer_rtx, 0);
3562 if (frame_pointer_needed)
3564 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
3565 RTX_FRAME_RELATED_P (insn) = 1;
3567 /* Force the unwind info to recognize this as defining a new CFA,
3568 rather than some temp register setup. */
3569 add_reg_note (insn, REG_CFA_ADJUST_CFA, NULL_RTX);
3572 if (current_frame_info.total_size != 0)
3574 rtx frame_size_rtx = GEN_INT (- current_frame_info.total_size);
3577 if (satisfies_constraint_I (frame_size_rtx))
3578 offset = frame_size_rtx;
3581 regno = next_scratch_gr_reg ();
3582 offset = gen_rtx_REG (DImode, regno);
3583 emit_move_insn (offset, frame_size_rtx);
3586 insn = emit_insn (gen_adddi3 (stack_pointer_rtx,
3587 stack_pointer_rtx, offset));
3589 if (! frame_pointer_needed)
3591 RTX_FRAME_RELATED_P (insn) = 1;
3592 add_reg_note (insn, REG_CFA_ADJUST_CFA,
3593 gen_rtx_SET (VOIDmode,
3595 gen_rtx_PLUS (DImode,
3600 /* ??? At this point we must generate a magic insn that appears to
3601 modify the stack pointer, the frame pointer, and all spill
3602 iterators. This would allow the most scheduling freedom. For
3603 now, just hard stop. */
3604 emit_insn (gen_blockage ());
3607 /* Must copy out ar.unat before doing any integer spills. */
3608 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
3610 if (current_frame_info.r[reg_save_ar_unat])
3613 = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_unat]);
3614 reg_emitted (reg_save_ar_unat);
3618 alt_regno = next_scratch_gr_reg ();
3619 ar_unat_save_reg = gen_rtx_REG (DImode, alt_regno);
3620 current_frame_info.gr_used_mask |= 1 << alt_regno;
3623 reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
3624 insn = emit_move_insn (ar_unat_save_reg, reg);
3625 if (current_frame_info.r[reg_save_ar_unat])
3627 RTX_FRAME_RELATED_P (insn) = 1;
3628 add_reg_note (insn, REG_CFA_REGISTER, NULL_RTX);
3631 /* Even if we're not going to generate an epilogue, we still
3632 need to save the register so that EH works. */
3633 if (! epilogue_p && current_frame_info.r[reg_save_ar_unat])
3634 emit_insn (gen_prologue_use (ar_unat_save_reg));
3637 ar_unat_save_reg = NULL_RTX;
3639 /* Spill all varargs registers. Do this before spilling any GR registers,
3640 since we want the UNAT bits for the GR registers to override the UNAT
3641 bits from varargs, which we don't care about. */
3644 for (regno = GR_ARG_FIRST + 7; n_varargs > 0; --n_varargs, --regno)
3646 reg = gen_rtx_REG (DImode, regno);
3647 do_spill (gen_gr_spill, reg, cfa_off += 8, NULL_RTX);
3650 /* Locate the bottom of the register save area. */
3651 cfa_off = (current_frame_info.spill_cfa_off
3652 + current_frame_info.spill_size
3653 + current_frame_info.extra_spill_size);
3655 /* Save the predicate register block either in a register or in memory. */
3656 if (TEST_HARD_REG_BIT (current_frame_info.mask, PR_REG (0)))
3658 reg = gen_rtx_REG (DImode, PR_REG (0));
3659 if (current_frame_info.r[reg_save_pr] != 0)
3661 alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_pr]);
3662 reg_emitted (reg_save_pr);
3663 insn = emit_move_insn (alt_reg, reg);
3665 /* ??? Denote pr spill/fill by a DImode move that modifies all
3666 64 hard registers. */
3667 RTX_FRAME_RELATED_P (insn) = 1;
3668 add_reg_note (insn, REG_CFA_REGISTER, NULL_RTX);
3670 /* Even if we're not going to generate an epilogue, we still
3671 need to save the register so that EH works. */
3673 emit_insn (gen_prologue_use (alt_reg));
3677 alt_regno = next_scratch_gr_reg ();
3678 alt_reg = gen_rtx_REG (DImode, alt_regno);
3679 insn = emit_move_insn (alt_reg, reg);
3680 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
3685 /* Handle AR regs in numerical order. All of them get special handling. */
3686 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM)
3687 && current_frame_info.r[reg_save_ar_unat] == 0)
3689 reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
3690 do_spill (gen_movdi_x, ar_unat_save_reg, cfa_off, reg);
3694 /* The alloc insn already copied ar.pfs into a general register. The
3695 only thing we have to do now is copy that register to a stack slot
3696 if we'd not allocated a local register for the job. */
3697 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM)
3698 && current_frame_info.r[reg_save_ar_pfs] == 0)
3700 reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
3701 do_spill (gen_movdi_x, ar_pfs_save_reg, cfa_off, reg);
3705 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_LC_REGNUM))
3707 reg = gen_rtx_REG (DImode, AR_LC_REGNUM);
3708 if (current_frame_info.r[reg_save_ar_lc] != 0)
3710 alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_lc]);
3711 reg_emitted (reg_save_ar_lc);
3712 insn = emit_move_insn (alt_reg, reg);
3713 RTX_FRAME_RELATED_P (insn) = 1;
3714 add_reg_note (insn, REG_CFA_REGISTER, NULL_RTX);
3716 /* Even if we're not going to generate an epilogue, we still
3717 need to save the register so that EH works. */
3719 emit_insn (gen_prologue_use (alt_reg));
3723 alt_regno = next_scratch_gr_reg ();
3724 alt_reg = gen_rtx_REG (DImode, alt_regno);
3725 emit_move_insn (alt_reg, reg);
3726 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
3731 /* Save the return pointer. */
3732 if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
3734 reg = gen_rtx_REG (DImode, BR_REG (0));
3735 if (current_frame_info.r[reg_save_b0] != 0)
3737 alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_b0]);
3738 reg_emitted (reg_save_b0);
3739 insn = emit_move_insn (alt_reg, reg);
3740 RTX_FRAME_RELATED_P (insn) = 1;
3741 add_reg_note (insn, REG_CFA_REGISTER,
3742 gen_rtx_SET (VOIDmode, alt_reg, pc_rtx));
3744 /* Even if we're not going to generate an epilogue, we still
3745 need to save the register so that EH works. */
3747 emit_insn (gen_prologue_use (alt_reg));
3751 alt_regno = next_scratch_gr_reg ();
3752 alt_reg = gen_rtx_REG (DImode, alt_regno);
3753 emit_move_insn (alt_reg, reg);
3754 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
3759 if (current_frame_info.r[reg_save_gp])
3761 reg_emitted (reg_save_gp);
3762 insn = emit_move_insn (gen_rtx_REG (DImode,
3763 current_frame_info.r[reg_save_gp]),
3764 pic_offset_table_rtx);
3767 /* We should now be at the base of the gr/br/fr spill area. */
3768 gcc_assert (cfa_off == (current_frame_info.spill_cfa_off
3769 + current_frame_info.spill_size));
3771 /* Spill all general registers. */
3772 for (regno = GR_REG (1); regno <= GR_REG (31); ++regno)
3773 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3775 reg = gen_rtx_REG (DImode, regno);
3776 do_spill (gen_gr_spill, reg, cfa_off, reg);
3780 /* Spill the rest of the BR registers. */
3781 for (regno = BR_REG (1); regno <= BR_REG (7); ++regno)
3782 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3784 alt_regno = next_scratch_gr_reg ();
3785 alt_reg = gen_rtx_REG (DImode, alt_regno);
3786 reg = gen_rtx_REG (DImode, regno);
3787 emit_move_insn (alt_reg, reg);
3788 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
3792 /* Align the frame and spill all FR registers. */
3793 for (regno = FR_REG (2); regno <= FR_REG (127); ++regno)
3794 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3796 gcc_assert (!(cfa_off & 15));
3797 reg = gen_rtx_REG (XFmode, regno);
3798 do_spill (gen_fr_spill_x, reg, cfa_off, reg);
3802 gcc_assert (cfa_off == current_frame_info.spill_cfa_off);
3804 finish_spill_pointers ();
3807 /* Output the textual info surrounding the prologue. */
3810 ia64_start_function (FILE *file, const char *fnname,
3811 tree decl ATTRIBUTE_UNUSED)
3813 #if TARGET_ABI_OPEN_VMS
3814 vms_start_function (fnname);
3817 fputs ("\t.proc ", file);
3818 assemble_name (file, fnname);
3820 ASM_OUTPUT_LABEL (file, fnname);
3823 /* Called after register allocation to add any instructions needed for the
3824 epilogue. Using an epilogue insn is favored compared to putting all of the
3825 instructions in output_function_prologue(), since it allows the scheduler
3826 to intermix instructions with the saves of the caller saved registers. In
3827 some cases, it might be necessary to emit a barrier instruction as the last
3828 insn to prevent such scheduling. */
3831 ia64_expand_epilogue (int sibcall_p)
3833 rtx insn, reg, alt_reg, ar_unat_save_reg;
3834 int regno, alt_regno, cfa_off;
3836 ia64_compute_frame_size (get_frame_size ());
3838 /* If there is a frame pointer, then we use it instead of the stack
3839 pointer, so that the stack pointer does not need to be valid when
3840 the epilogue starts. See EXIT_IGNORE_STACK. */
3841 if (frame_pointer_needed)
3842 setup_spill_pointers (current_frame_info.n_spilled,
3843 hard_frame_pointer_rtx, 0);
3845 setup_spill_pointers (current_frame_info.n_spilled, stack_pointer_rtx,
3846 current_frame_info.total_size);
3848 if (current_frame_info.total_size != 0)
3850 /* ??? At this point we must generate a magic insn that appears to
3851 modify the spill iterators and the frame pointer. This would
3852 allow the most scheduling freedom. For now, just hard stop. */
3853 emit_insn (gen_blockage ());
3856 /* Locate the bottom of the register save area. */
3857 cfa_off = (current_frame_info.spill_cfa_off
3858 + current_frame_info.spill_size
3859 + current_frame_info.extra_spill_size);
3861 /* Restore the predicate registers. */
3862 if (TEST_HARD_REG_BIT (current_frame_info.mask, PR_REG (0)))
3864 if (current_frame_info.r[reg_save_pr] != 0)
3866 alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_pr]);
3867 reg_emitted (reg_save_pr);
3871 alt_regno = next_scratch_gr_reg ();
3872 alt_reg = gen_rtx_REG (DImode, alt_regno);
3873 do_restore (gen_movdi_x, alt_reg, cfa_off);
3876 reg = gen_rtx_REG (DImode, PR_REG (0));
3877 emit_move_insn (reg, alt_reg);
3880 /* Restore the application registers. */
3882 /* Load the saved unat from the stack, but do not restore it until
3883 after the GRs have been restored. */
3884 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
3886 if (current_frame_info.r[reg_save_ar_unat] != 0)
3889 = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_unat]);
3890 reg_emitted (reg_save_ar_unat);
3894 alt_regno = next_scratch_gr_reg ();
3895 ar_unat_save_reg = gen_rtx_REG (DImode, alt_regno);
3896 current_frame_info.gr_used_mask |= 1 << alt_regno;
3897 do_restore (gen_movdi_x, ar_unat_save_reg, cfa_off);
3902 ar_unat_save_reg = NULL_RTX;
3904 if (current_frame_info.r[reg_save_ar_pfs] != 0)
3906 reg_emitted (reg_save_ar_pfs);
3907 alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_pfs]);
3908 reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
3909 emit_move_insn (reg, alt_reg);
3911 else if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM))
3913 alt_regno = next_scratch_gr_reg ();
3914 alt_reg = gen_rtx_REG (DImode, alt_regno);
3915 do_restore (gen_movdi_x, alt_reg, cfa_off);
3917 reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
3918 emit_move_insn (reg, alt_reg);
3921 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_LC_REGNUM))
3923 if (current_frame_info.r[reg_save_ar_lc] != 0)
3925 alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_lc]);
3926 reg_emitted (reg_save_ar_lc);
3930 alt_regno = next_scratch_gr_reg ();
3931 alt_reg = gen_rtx_REG (DImode, alt_regno);
3932 do_restore (gen_movdi_x, alt_reg, cfa_off);
3935 reg = gen_rtx_REG (DImode, AR_LC_REGNUM);
3936 emit_move_insn (reg, alt_reg);
3939 /* Restore the return pointer. */
3940 if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
3942 if (current_frame_info.r[reg_save_b0] != 0)
3944 alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_b0]);
3945 reg_emitted (reg_save_b0);
3949 alt_regno = next_scratch_gr_reg ();
3950 alt_reg = gen_rtx_REG (DImode, alt_regno);
3951 do_restore (gen_movdi_x, alt_reg, cfa_off);
3954 reg = gen_rtx_REG (DImode, BR_REG (0));
3955 emit_move_insn (reg, alt_reg);
3958 /* We should now be at the base of the gr/br/fr spill area. */
3959 gcc_assert (cfa_off == (current_frame_info.spill_cfa_off
3960 + current_frame_info.spill_size));
3962 /* The GP may be stored on the stack in the prologue, but it's
3963 never restored in the epilogue. Skip the stack slot. */
3964 if (TEST_HARD_REG_BIT (current_frame_info.mask, GR_REG (1)))
3967 /* Restore all general registers. */
3968 for (regno = GR_REG (2); regno <= GR_REG (31); ++regno)
3969 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3971 reg = gen_rtx_REG (DImode, regno);
3972 do_restore (gen_gr_restore, reg, cfa_off);
3976 /* Restore the branch registers. */
3977 for (regno = BR_REG (1); regno <= BR_REG (7); ++regno)
3978 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3980 alt_regno = next_scratch_gr_reg ();
3981 alt_reg = gen_rtx_REG (DImode, alt_regno);
3982 do_restore (gen_movdi_x, alt_reg, cfa_off);
3984 reg = gen_rtx_REG (DImode, regno);
3985 emit_move_insn (reg, alt_reg);
3988 /* Restore floating point registers. */
3989 for (regno = FR_REG (2); regno <= FR_REG (127); ++regno)
3990 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3992 gcc_assert (!(cfa_off & 15));
3993 reg = gen_rtx_REG (XFmode, regno);
3994 do_restore (gen_fr_restore_x, reg, cfa_off);
3998 /* Restore ar.unat for real. */
3999 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
4001 reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
4002 emit_move_insn (reg, ar_unat_save_reg);
4005 gcc_assert (cfa_off == current_frame_info.spill_cfa_off);
4007 finish_spill_pointers ();
4009 if (current_frame_info.total_size
4010 || cfun->machine->ia64_eh_epilogue_sp
4011 || frame_pointer_needed)
4013 /* ??? At this point we must generate a magic insn that appears to
4014 modify the spill iterators, the stack pointer, and the frame
4015 pointer. This would allow the most scheduling freedom. For now,
4017 emit_insn (gen_blockage ());
4020 if (cfun->machine->ia64_eh_epilogue_sp)
4021 emit_move_insn (stack_pointer_rtx, cfun->machine->ia64_eh_epilogue_sp);
4022 else if (frame_pointer_needed)
4024 insn = emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
4025 RTX_FRAME_RELATED_P (insn) = 1;
4026 add_reg_note (insn, REG_CFA_ADJUST_CFA, NULL);
4028 else if (current_frame_info.total_size)
4030 rtx offset, frame_size_rtx;
4032 frame_size_rtx = GEN_INT (current_frame_info.total_size);
4033 if (satisfies_constraint_I (frame_size_rtx))
4034 offset = frame_size_rtx;
4037 regno = next_scratch_gr_reg ();
4038 offset = gen_rtx_REG (DImode, regno);
4039 emit_move_insn (offset, frame_size_rtx);
4042 insn = emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
4045 RTX_FRAME_RELATED_P (insn) = 1;
4046 add_reg_note (insn, REG_CFA_ADJUST_CFA,
4047 gen_rtx_SET (VOIDmode,
4049 gen_rtx_PLUS (DImode,
4054 if (cfun->machine->ia64_eh_epilogue_bsp)
4055 emit_insn (gen_set_bsp (cfun->machine->ia64_eh_epilogue_bsp));
4058 emit_jump_insn (gen_return_internal (gen_rtx_REG (DImode, BR_REG (0))));
4061 int fp = GR_REG (2);
4062 /* We need a throw away register here, r0 and r1 are reserved,
4063 so r2 is the first available call clobbered register. If
4064 there was a frame_pointer register, we may have swapped the
4065 names of r2 and HARD_FRAME_POINTER_REGNUM, so we have to make
4066 sure we're using the string "r2" when emitting the register
4067 name for the assembler. */
4068 if (current_frame_info.r[reg_fp]
4069 && current_frame_info.r[reg_fp] == GR_REG (2))
4070 fp = HARD_FRAME_POINTER_REGNUM;
4072 /* We must emit an alloc to force the input registers to become output
4073 registers. Otherwise, if the callee tries to pass its parameters
4074 through to another call without an intervening alloc, then these
4076 /* ??? We don't need to preserve all input registers. We only need to
4077 preserve those input registers used as arguments to the sibling call.
4078 It is unclear how to compute that number here. */
4079 if (current_frame_info.n_input_regs != 0)
4081 rtx n_inputs = GEN_INT (current_frame_info.n_input_regs);
4083 insn = emit_insn (gen_alloc (gen_rtx_REG (DImode, fp),
4084 const0_rtx, const0_rtx,
4085 n_inputs, const0_rtx));
4086 RTX_FRAME_RELATED_P (insn) = 1;
4088 /* ??? We need to mark the alloc as frame-related so that it gets
4089 passed into ia64_asm_unwind_emit for ia64-specific unwinding.
4090 But there's nothing dwarf2 related to be done wrt the register
4091 windows. If we do nothing, dwarf2out will abort on the UNSPEC;
4092 the empty parallel means dwarf2out will not see anything. */
4093 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
4094 gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (0)));
4099 /* Return 1 if br.ret can do all the work required to return from a
4103 ia64_direct_return (void)
4105 if (reload_completed && ! frame_pointer_needed)
4107 ia64_compute_frame_size (get_frame_size ());
4109 return (current_frame_info.total_size == 0
4110 && current_frame_info.n_spilled == 0
4111 && current_frame_info.r[reg_save_b0] == 0
4112 && current_frame_info.r[reg_save_pr] == 0
4113 && current_frame_info.r[reg_save_ar_pfs] == 0
4114 && current_frame_info.r[reg_save_ar_unat] == 0
4115 && current_frame_info.r[reg_save_ar_lc] == 0);
4120 /* Return the magic cookie that we use to hold the return address
4121 during early compilation. */
4124 ia64_return_addr_rtx (HOST_WIDE_INT count, rtx frame ATTRIBUTE_UNUSED)
4128 return gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_RET_ADDR);
4131 /* Split this value after reload, now that we know where the return
4132 address is saved. */
4135 ia64_split_return_addr_rtx (rtx dest)
4139 if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
4141 if (current_frame_info.r[reg_save_b0] != 0)
4143 src = gen_rtx_REG (DImode, current_frame_info.r[reg_save_b0]);
4144 reg_emitted (reg_save_b0);
4152 /* Compute offset from CFA for BR0. */
4153 /* ??? Must be kept in sync with ia64_expand_prologue. */
4154 off = (current_frame_info.spill_cfa_off
4155 + current_frame_info.spill_size);
4156 for (regno = GR_REG (1); regno <= GR_REG (31); ++regno)
4157 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
4160 /* Convert CFA offset to a register based offset. */
4161 if (frame_pointer_needed)
4162 src = hard_frame_pointer_rtx;
4165 src = stack_pointer_rtx;
4166 off += current_frame_info.total_size;
4169 /* Load address into scratch register. */
4170 off_r = GEN_INT (off);
4171 if (satisfies_constraint_I (off_r))
4172 emit_insn (gen_adddi3 (dest, src, off_r));
4175 emit_move_insn (dest, off_r);
4176 emit_insn (gen_adddi3 (dest, src, dest));
4179 src = gen_rtx_MEM (Pmode, dest);
4183 src = gen_rtx_REG (DImode, BR_REG (0));
4185 emit_move_insn (dest, src);
4189 ia64_hard_regno_rename_ok (int from, int to)
4191 /* Don't clobber any of the registers we reserved for the prologue. */
4194 for (r = reg_fp; r <= reg_save_ar_lc; r++)
4195 if (to == current_frame_info.r[r]
4196 || from == current_frame_info.r[r]
4197 || to == emitted_frame_related_regs[r]
4198 || from == emitted_frame_related_regs[r])
4201 /* Don't use output registers outside the register frame. */
4202 if (OUT_REGNO_P (to) && to >= OUT_REG (current_frame_info.n_output_regs))
4205 /* Retain even/oddness on predicate register pairs. */
4206 if (PR_REGNO_P (from) && PR_REGNO_P (to))
4207 return (from & 1) == (to & 1);
4212 /* Target hook for assembling integer objects. Handle word-sized
4213 aligned objects and detect the cases when @fptr is needed. */
4216 ia64_assemble_integer (rtx x, unsigned int size, int aligned_p)
4218 if (size == POINTER_SIZE / BITS_PER_UNIT
4219 && !(TARGET_NO_PIC || TARGET_AUTO_PIC)
4220 && GET_CODE (x) == SYMBOL_REF
4221 && SYMBOL_REF_FUNCTION_P (x))
4223 static const char * const directive[2][2] = {
4224 /* 64-bit pointer */ /* 32-bit pointer */
4225 { "\tdata8.ua\t@fptr(", "\tdata4.ua\t@fptr("}, /* unaligned */
4226 { "\tdata8\t@fptr(", "\tdata4\t@fptr("} /* aligned */
4228 fputs (directive[(aligned_p != 0)][POINTER_SIZE == 32], asm_out_file);
4229 output_addr_const (asm_out_file, x);
4230 fputs (")\n", asm_out_file);
4233 return default_assemble_integer (x, size, aligned_p);
4236 /* Emit the function prologue. */
4239 ia64_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
4241 int mask, grsave, grsave_prev;
4243 if (current_frame_info.need_regstk)
4244 fprintf (file, "\t.regstk %d, %d, %d, %d\n",
4245 current_frame_info.n_input_regs,
4246 current_frame_info.n_local_regs,
4247 current_frame_info.n_output_regs,
4248 current_frame_info.n_rotate_regs);
4250 if (ia64_except_unwind_info (&global_options) != UI_TARGET)
4253 /* Emit the .prologue directive. */
4256 grsave = grsave_prev = 0;
4257 if (current_frame_info.r[reg_save_b0] != 0)
4260 grsave = grsave_prev = current_frame_info.r[reg_save_b0];
4262 if (current_frame_info.r[reg_save_ar_pfs] != 0
4263 && (grsave_prev == 0
4264 || current_frame_info.r[reg_save_ar_pfs] == grsave_prev + 1))
4267 if (grsave_prev == 0)
4268 grsave = current_frame_info.r[reg_save_ar_pfs];
4269 grsave_prev = current_frame_info.r[reg_save_ar_pfs];
4271 if (current_frame_info.r[reg_fp] != 0
4272 && (grsave_prev == 0
4273 || current_frame_info.r[reg_fp] == grsave_prev + 1))
4276 if (grsave_prev == 0)
4277 grsave = HARD_FRAME_POINTER_REGNUM;
4278 grsave_prev = current_frame_info.r[reg_fp];
4280 if (current_frame_info.r[reg_save_pr] != 0
4281 && (grsave_prev == 0
4282 || current_frame_info.r[reg_save_pr] == grsave_prev + 1))
4285 if (grsave_prev == 0)
4286 grsave = current_frame_info.r[reg_save_pr];
4289 if (mask && TARGET_GNU_AS)
4290 fprintf (file, "\t.prologue %d, %d\n", mask,
4291 ia64_dbx_register_number (grsave));
4293 fputs ("\t.prologue\n", file);
4295 /* Emit a .spill directive, if necessary, to relocate the base of
4296 the register spill area. */
4297 if (current_frame_info.spill_cfa_off != -16)
4298 fprintf (file, "\t.spill %ld\n",
4299 (long) (current_frame_info.spill_cfa_off
4300 + current_frame_info.spill_size));
4303 /* Emit the .body directive at the scheduled end of the prologue. */
4306 ia64_output_function_end_prologue (FILE *file)
4308 if (ia64_except_unwind_info (&global_options) != UI_TARGET)
4311 fputs ("\t.body\n", file);
4314 /* Emit the function epilogue. */
4317 ia64_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
4318 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
4322 if (current_frame_info.r[reg_fp])
4324 const char *tmp = reg_names[HARD_FRAME_POINTER_REGNUM];
4325 reg_names[HARD_FRAME_POINTER_REGNUM]
4326 = reg_names[current_frame_info.r[reg_fp]];
4327 reg_names[current_frame_info.r[reg_fp]] = tmp;
4328 reg_emitted (reg_fp);
4330 if (! TARGET_REG_NAMES)
4332 for (i = 0; i < current_frame_info.n_input_regs; i++)
4333 reg_names[IN_REG (i)] = ia64_input_reg_names[i];
4334 for (i = 0; i < current_frame_info.n_local_regs; i++)
4335 reg_names[LOC_REG (i)] = ia64_local_reg_names[i];
4336 for (i = 0; i < current_frame_info.n_output_regs; i++)
4337 reg_names[OUT_REG (i)] = ia64_output_reg_names[i];
4340 current_frame_info.initialized = 0;
4344 ia64_dbx_register_number (int regno)
4346 /* In ia64_expand_prologue we quite literally renamed the frame pointer
4347 from its home at loc79 to something inside the register frame. We
4348 must perform the same renumbering here for the debug info. */
4349 if (current_frame_info.r[reg_fp])
4351 if (regno == HARD_FRAME_POINTER_REGNUM)
4352 regno = current_frame_info.r[reg_fp];
4353 else if (regno == current_frame_info.r[reg_fp])
4354 regno = HARD_FRAME_POINTER_REGNUM;
4357 if (IN_REGNO_P (regno))
4358 return 32 + regno - IN_REG (0);
4359 else if (LOC_REGNO_P (regno))
4360 return 32 + current_frame_info.n_input_regs + regno - LOC_REG (0);
4361 else if (OUT_REGNO_P (regno))
4362 return (32 + current_frame_info.n_input_regs
4363 + current_frame_info.n_local_regs + regno - OUT_REG (0));
4368 /* Implement TARGET_TRAMPOLINE_INIT.
4370 The trampoline should set the static chain pointer to value placed
4371 into the trampoline and should branch to the specified routine.
4372 To make the normal indirect-subroutine calling convention work,
4373 the trampoline must look like a function descriptor; the first
4374 word being the target address and the second being the target's
4377 We abuse the concept of a global pointer by arranging for it
4378 to point to the data we need to load. The complete trampoline
4379 has the following form:
4381 +-------------------+ \
4382 TRAMP: | __ia64_trampoline | |
4383 +-------------------+ > fake function descriptor
4385 +-------------------+ /
4386 | target descriptor |
4387 +-------------------+
4389 +-------------------+
4393 ia64_trampoline_init (rtx m_tramp, tree fndecl, rtx static_chain)
4395 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
4396 rtx addr, addr_reg, tramp, eight = GEN_INT (8);
4398 /* The Intel assembler requires that the global __ia64_trampoline symbol
4399 be declared explicitly */
4402 static bool declared_ia64_trampoline = false;
4404 if (!declared_ia64_trampoline)
4406 declared_ia64_trampoline = true;
4407 (*targetm.asm_out.globalize_label) (asm_out_file,
4408 "__ia64_trampoline");
4412 /* Make sure addresses are Pmode even if we are in ILP32 mode. */
4413 addr = convert_memory_address (Pmode, XEXP (m_tramp, 0));
4414 fnaddr = convert_memory_address (Pmode, fnaddr);
4415 static_chain = convert_memory_address (Pmode, static_chain);
4417 /* Load up our iterator. */
4418 addr_reg = copy_to_reg (addr);
4419 m_tramp = adjust_automodify_address (m_tramp, Pmode, addr_reg, 0);
4421 /* The first two words are the fake descriptor:
4422 __ia64_trampoline, ADDR+16. */
4423 tramp = gen_rtx_SYMBOL_REF (Pmode, "__ia64_trampoline");
4424 if (TARGET_ABI_OPEN_VMS)
4426 /* HP decided to break the ELF ABI on VMS (to deal with an ambiguity
4427 in the Macro-32 compiler) and changed the semantics of the LTOFF22
4428 relocation against function symbols to make it identical to the
4429 LTOFF_FPTR22 relocation. Emit the latter directly to stay within
4430 strict ELF and dereference to get the bare code address. */
4431 rtx reg = gen_reg_rtx (Pmode);
4432 SYMBOL_REF_FLAGS (tramp) |= SYMBOL_FLAG_FUNCTION;
4433 emit_move_insn (reg, tramp);
4434 emit_move_insn (reg, gen_rtx_MEM (Pmode, reg));
4437 emit_move_insn (m_tramp, tramp);
4438 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
4439 m_tramp = adjust_automodify_address (m_tramp, VOIDmode, NULL, 8);
4441 emit_move_insn (m_tramp, force_reg (Pmode, plus_constant (Pmode, addr, 16)));
4442 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
4443 m_tramp = adjust_automodify_address (m_tramp, VOIDmode, NULL, 8);
4445 /* The third word is the target descriptor. */
4446 emit_move_insn (m_tramp, force_reg (Pmode, fnaddr));
4447 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
4448 m_tramp = adjust_automodify_address (m_tramp, VOIDmode, NULL, 8);
4450 /* The fourth word is the static chain. */
4451 emit_move_insn (m_tramp, static_chain);
4454 /* Do any needed setup for a variadic function. CUM has not been updated
4455 for the last named argument which has type TYPE and mode MODE.
4457 We generate the actual spill instructions during prologue generation. */
4460 ia64_setup_incoming_varargs (cumulative_args_t cum, enum machine_mode mode,
4461 tree type, int * pretend_size,
4462 int second_time ATTRIBUTE_UNUSED)
4464 CUMULATIVE_ARGS next_cum = *get_cumulative_args (cum);
4466 /* Skip the current argument. */
4467 ia64_function_arg_advance (pack_cumulative_args (&next_cum), mode, type, 1);
4469 if (next_cum.words < MAX_ARGUMENT_SLOTS)
4471 int n = MAX_ARGUMENT_SLOTS - next_cum.words;
4472 *pretend_size = n * UNITS_PER_WORD;
4473 cfun->machine->n_varargs = n;
4477 /* Check whether TYPE is a homogeneous floating point aggregate. If
4478 it is, return the mode of the floating point type that appears
4479 in all leafs. If it is not, return VOIDmode.
4481 An aggregate is a homogeneous floating point aggregate is if all
4482 fields/elements in it have the same floating point type (e.g,
4483 SFmode). 128-bit quad-precision floats are excluded.
4485 Variable sized aggregates should never arrive here, since we should
4486 have already decided to pass them by reference. Top-level zero-sized
4487 aggregates are excluded because our parallels crash the middle-end. */
4489 static enum machine_mode
4490 hfa_element_mode (const_tree type, bool nested)
4492 enum machine_mode element_mode = VOIDmode;
4493 enum machine_mode mode;
4494 enum tree_code code = TREE_CODE (type);
4495 int know_element_mode = 0;
4498 if (!nested && (!TYPE_SIZE (type) || integer_zerop (TYPE_SIZE (type))))
4503 case VOID_TYPE: case INTEGER_TYPE: case ENUMERAL_TYPE:
4504 case BOOLEAN_TYPE: case POINTER_TYPE:
4505 case OFFSET_TYPE: case REFERENCE_TYPE: case METHOD_TYPE:
4506 case LANG_TYPE: case FUNCTION_TYPE:
4509 /* Fortran complex types are supposed to be HFAs, so we need to handle
4510 gcc's COMPLEX_TYPEs as HFAs. We need to exclude the integral complex
4513 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_COMPLEX_FLOAT
4514 && TYPE_MODE (type) != TCmode)
4515 return GET_MODE_INNER (TYPE_MODE (type));
4520 /* We want to return VOIDmode for raw REAL_TYPEs, but the actual
4521 mode if this is contained within an aggregate. */
4522 if (nested && TYPE_MODE (type) != TFmode)
4523 return TYPE_MODE (type);
4528 return hfa_element_mode (TREE_TYPE (type), 1);
4532 case QUAL_UNION_TYPE:
4533 for (t = TYPE_FIELDS (type); t; t = DECL_CHAIN (t))
4535 if (TREE_CODE (t) != FIELD_DECL)
4538 mode = hfa_element_mode (TREE_TYPE (t), 1);
4539 if (know_element_mode)
4541 if (mode != element_mode)
4544 else if (GET_MODE_CLASS (mode) != MODE_FLOAT)
4548 know_element_mode = 1;
4549 element_mode = mode;
4552 return element_mode;
4555 /* If we reach here, we probably have some front-end specific type
4556 that the backend doesn't know about. This can happen via the
4557 aggregate_value_p call in init_function_start. All we can do is
4558 ignore unknown tree types. */
4565 /* Return the number of words required to hold a quantity of TYPE and MODE
4566 when passed as an argument. */
4568 ia64_function_arg_words (const_tree type, enum machine_mode mode)
4572 if (mode == BLKmode)
4573 words = int_size_in_bytes (type);
4575 words = GET_MODE_SIZE (mode);
4577 return (words + UNITS_PER_WORD - 1) / UNITS_PER_WORD; /* round up */
4580 /* Return the number of registers that should be skipped so the current
4581 argument (described by TYPE and WORDS) will be properly aligned.
4583 Integer and float arguments larger than 8 bytes start at the next
4584 even boundary. Aggregates larger than 8 bytes start at the next
4585 even boundary if the aggregate has 16 byte alignment. Note that
4586 in the 32-bit ABI, TImode and TFmode have only 8-byte alignment
4587 but are still to be aligned in registers.
4589 ??? The ABI does not specify how to handle aggregates with
4590 alignment from 9 to 15 bytes, or greater than 16. We handle them
4591 all as if they had 16 byte alignment. Such aggregates can occur
4592 only if gcc extensions are used. */
4594 ia64_function_arg_offset (const CUMULATIVE_ARGS *cum,
4595 const_tree type, int words)
4597 /* No registers are skipped on VMS. */
4598 if (TARGET_ABI_OPEN_VMS || (cum->words & 1) == 0)
4602 && TREE_CODE (type) != INTEGER_TYPE
4603 && TREE_CODE (type) != REAL_TYPE)
4604 return TYPE_ALIGN (type) > 8 * BITS_PER_UNIT;
4609 /* Return rtx for register where argument is passed, or zero if it is passed
4611 /* ??? 128-bit quad-precision floats are always passed in general
4615 ia64_function_arg_1 (cumulative_args_t cum_v, enum machine_mode mode,
4616 const_tree type, bool named, bool incoming)
4618 const CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
4620 int basereg = (incoming ? GR_ARG_FIRST : AR_ARG_FIRST);
4621 int words = ia64_function_arg_words (type, mode);
4622 int offset = ia64_function_arg_offset (cum, type, words);
4623 enum machine_mode hfa_mode = VOIDmode;
4625 /* For OPEN VMS, emit the instruction setting up the argument register here,
4626 when we know this will be together with the other arguments setup related
4627 insns. This is not the conceptually best place to do this, but this is
4628 the easiest as we have convenient access to cumulative args info. */
4630 if (TARGET_ABI_OPEN_VMS && mode == VOIDmode && type == void_type_node
4633 unsigned HOST_WIDE_INT regval = cum->words;
4636 for (i = 0; i < 8; i++)
4637 regval |= ((int) cum->atypes[i]) << (i * 3 + 8);
4639 emit_move_insn (gen_rtx_REG (DImode, GR_REG (25)),
4643 /* If all argument slots are used, then it must go on the stack. */
4644 if (cum->words + offset >= MAX_ARGUMENT_SLOTS)
4647 /* On OpenVMS argument is either in Rn or Fn. */
4648 if (TARGET_ABI_OPEN_VMS)
4650 if (FLOAT_MODE_P (mode))
4651 return gen_rtx_REG (mode, FR_ARG_FIRST + cum->words);
4653 return gen_rtx_REG (mode, basereg + cum->words);
4656 /* Check for and handle homogeneous FP aggregates. */
4658 hfa_mode = hfa_element_mode (type, 0);
4660 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
4661 and unprototyped hfas are passed specially. */
4662 if (hfa_mode != VOIDmode && (! cum->prototype || named))
4666 int fp_regs = cum->fp_regs;
4667 int int_regs = cum->words + offset;
4668 int hfa_size = GET_MODE_SIZE (hfa_mode);
4672 /* If prototyped, pass it in FR regs then GR regs.
4673 If not prototyped, pass it in both FR and GR regs.
4675 If this is an SFmode aggregate, then it is possible to run out of
4676 FR regs while GR regs are still left. In that case, we pass the
4677 remaining part in the GR regs. */
4679 /* Fill the FP regs. We do this always. We stop if we reach the end
4680 of the argument, the last FP register, or the last argument slot. */
4682 byte_size = ((mode == BLKmode)
4683 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
4684 args_byte_size = int_regs * UNITS_PER_WORD;
4686 for (; (offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS
4687 && args_byte_size < (MAX_ARGUMENT_SLOTS * UNITS_PER_WORD)); i++)
4689 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
4690 gen_rtx_REG (hfa_mode, (FR_ARG_FIRST
4694 args_byte_size += hfa_size;
4698 /* If no prototype, then the whole thing must go in GR regs. */
4699 if (! cum->prototype)
4701 /* If this is an SFmode aggregate, then we might have some left over
4702 that needs to go in GR regs. */
4703 else if (byte_size != offset)
4704 int_regs += offset / UNITS_PER_WORD;
4706 /* Fill in the GR regs. We must use DImode here, not the hfa mode. */
4708 for (; offset < byte_size && int_regs < MAX_ARGUMENT_SLOTS; i++)
4710 enum machine_mode gr_mode = DImode;
4711 unsigned int gr_size;
4713 /* If we have an odd 4 byte hunk because we ran out of FR regs,
4714 then this goes in a GR reg left adjusted/little endian, right
4715 adjusted/big endian. */
4716 /* ??? Currently this is handled wrong, because 4-byte hunks are
4717 always right adjusted/little endian. */
4720 /* If we have an even 4 byte hunk because the aggregate is a
4721 multiple of 4 bytes in size, then this goes in a GR reg right
4722 adjusted/little endian. */
4723 else if (byte_size - offset == 4)
4726 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
4727 gen_rtx_REG (gr_mode, (basereg
4731 gr_size = GET_MODE_SIZE (gr_mode);
4733 if (gr_size == UNITS_PER_WORD
4734 || (gr_size < UNITS_PER_WORD && offset % UNITS_PER_WORD == 0))
4736 else if (gr_size > UNITS_PER_WORD)
4737 int_regs += gr_size / UNITS_PER_WORD;
4739 return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
4742 /* Integral and aggregates go in general registers. If we have run out of
4743 FR registers, then FP values must also go in general registers. This can
4744 happen when we have a SFmode HFA. */
4745 else if (mode == TFmode || mode == TCmode
4746 || (! FLOAT_MODE_P (mode) || cum->fp_regs == MAX_ARGUMENT_SLOTS))
4748 int byte_size = ((mode == BLKmode)
4749 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
4750 if (BYTES_BIG_ENDIAN
4751 && (mode == BLKmode || (type && AGGREGATE_TYPE_P (type)))
4752 && byte_size < UNITS_PER_WORD
4755 rtx gr_reg = gen_rtx_EXPR_LIST (VOIDmode,
4756 gen_rtx_REG (DImode,
4757 (basereg + cum->words
4760 return gen_rtx_PARALLEL (mode, gen_rtvec (1, gr_reg));
4763 return gen_rtx_REG (mode, basereg + cum->words + offset);
4767 /* If there is a prototype, then FP values go in a FR register when
4768 named, and in a GR register when unnamed. */
4769 else if (cum->prototype)
4772 return gen_rtx_REG (mode, FR_ARG_FIRST + cum->fp_regs);
4773 /* In big-endian mode, an anonymous SFmode value must be represented
4774 as (parallel:SF [(expr_list (reg:DI n) (const_int 0))]) to force
4775 the value into the high half of the general register. */
4776 else if (BYTES_BIG_ENDIAN && mode == SFmode)
4777 return gen_rtx_PARALLEL (mode,
4779 gen_rtx_EXPR_LIST (VOIDmode,
4780 gen_rtx_REG (DImode, basereg + cum->words + offset),
4783 return gen_rtx_REG (mode, basereg + cum->words + offset);
4785 /* If there is no prototype, then FP values go in both FR and GR
4789 /* See comment above. */
4790 enum machine_mode inner_mode =
4791 (BYTES_BIG_ENDIAN && mode == SFmode) ? DImode : mode;
4793 rtx fp_reg = gen_rtx_EXPR_LIST (VOIDmode,
4794 gen_rtx_REG (mode, (FR_ARG_FIRST
4797 rtx gr_reg = gen_rtx_EXPR_LIST (VOIDmode,
4798 gen_rtx_REG (inner_mode,
4799 (basereg + cum->words
4803 return gen_rtx_PARALLEL (mode, gen_rtvec (2, fp_reg, gr_reg));
4807 /* Implement TARGET_FUNCION_ARG target hook. */
4810 ia64_function_arg (cumulative_args_t cum, enum machine_mode mode,
4811 const_tree type, bool named)
4813 return ia64_function_arg_1 (cum, mode, type, named, false);
4816 /* Implement TARGET_FUNCION_INCOMING_ARG target hook. */
4819 ia64_function_incoming_arg (cumulative_args_t cum,
4820 enum machine_mode mode,
4821 const_tree type, bool named)
4823 return ia64_function_arg_1 (cum, mode, type, named, true);
4826 /* Return number of bytes, at the beginning of the argument, that must be
4827 put in registers. 0 is the argument is entirely in registers or entirely
4831 ia64_arg_partial_bytes (cumulative_args_t cum_v, enum machine_mode mode,
4832 tree type, bool named ATTRIBUTE_UNUSED)
4834 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
4836 int words = ia64_function_arg_words (type, mode);
4837 int offset = ia64_function_arg_offset (cum, type, words);
4839 /* If all argument slots are used, then it must go on the stack. */
4840 if (cum->words + offset >= MAX_ARGUMENT_SLOTS)
4843 /* It doesn't matter whether the argument goes in FR or GR regs. If
4844 it fits within the 8 argument slots, then it goes entirely in
4845 registers. If it extends past the last argument slot, then the rest
4846 goes on the stack. */
4848 if (words + cum->words + offset <= MAX_ARGUMENT_SLOTS)
4851 return (MAX_ARGUMENT_SLOTS - cum->words - offset) * UNITS_PER_WORD;
4854 /* Return ivms_arg_type based on machine_mode. */
4856 static enum ivms_arg_type
4857 ia64_arg_type (enum machine_mode mode)
4870 /* Update CUM to point after this argument. This is patterned after
4871 ia64_function_arg. */
4874 ia64_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
4875 const_tree type, bool named)
4877 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
4878 int words = ia64_function_arg_words (type, mode);
4879 int offset = ia64_function_arg_offset (cum, type, words);
4880 enum machine_mode hfa_mode = VOIDmode;
4882 /* If all arg slots are already full, then there is nothing to do. */
4883 if (cum->words >= MAX_ARGUMENT_SLOTS)
4885 cum->words += words + offset;
4889 cum->atypes[cum->words] = ia64_arg_type (mode);
4890 cum->words += words + offset;
4892 /* On OpenVMS argument is either in Rn or Fn. */
4893 if (TARGET_ABI_OPEN_VMS)
4895 cum->int_regs = cum->words;
4896 cum->fp_regs = cum->words;
4900 /* Check for and handle homogeneous FP aggregates. */
4902 hfa_mode = hfa_element_mode (type, 0);
4904 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
4905 and unprototyped hfas are passed specially. */
4906 if (hfa_mode != VOIDmode && (! cum->prototype || named))
4908 int fp_regs = cum->fp_regs;
4909 /* This is the original value of cum->words + offset. */
4910 int int_regs = cum->words - words;
4911 int hfa_size = GET_MODE_SIZE (hfa_mode);
4915 /* If prototyped, pass it in FR regs then GR regs.
4916 If not prototyped, pass it in both FR and GR regs.
4918 If this is an SFmode aggregate, then it is possible to run out of
4919 FR regs while GR regs are still left. In that case, we pass the
4920 remaining part in the GR regs. */
4922 /* Fill the FP regs. We do this always. We stop if we reach the end
4923 of the argument, the last FP register, or the last argument slot. */
4925 byte_size = ((mode == BLKmode)
4926 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
4927 args_byte_size = int_regs * UNITS_PER_WORD;
4929 for (; (offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS
4930 && args_byte_size < (MAX_ARGUMENT_SLOTS * UNITS_PER_WORD));)
4933 args_byte_size += hfa_size;
4937 cum->fp_regs = fp_regs;
4940 /* Integral and aggregates go in general registers. So do TFmode FP values.
4941 If we have run out of FR registers, then other FP values must also go in
4942 general registers. This can happen when we have a SFmode HFA. */
4943 else if (mode == TFmode || mode == TCmode
4944 || (! FLOAT_MODE_P (mode) || cum->fp_regs == MAX_ARGUMENT_SLOTS))
4945 cum->int_regs = cum->words;
4947 /* If there is a prototype, then FP values go in a FR register when
4948 named, and in a GR register when unnamed. */
4949 else if (cum->prototype)
4952 cum->int_regs = cum->words;
4954 /* ??? Complex types should not reach here. */
4955 cum->fp_regs += (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT ? 2 : 1);
4957 /* If there is no prototype, then FP values go in both FR and GR
4961 /* ??? Complex types should not reach here. */
4962 cum->fp_regs += (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT ? 2 : 1);
4963 cum->int_regs = cum->words;
4967 /* Arguments with alignment larger than 8 bytes start at the next even
4968 boundary. On ILP32 HPUX, TFmode arguments start on next even boundary
4969 even though their normal alignment is 8 bytes. See ia64_function_arg. */
4972 ia64_function_arg_boundary (enum machine_mode mode, const_tree type)
4974 if (mode == TFmode && TARGET_HPUX && TARGET_ILP32)
4975 return PARM_BOUNDARY * 2;
4979 if (TYPE_ALIGN (type) > PARM_BOUNDARY)
4980 return PARM_BOUNDARY * 2;
4982 return PARM_BOUNDARY;
4985 if (GET_MODE_BITSIZE (mode) > PARM_BOUNDARY)
4986 return PARM_BOUNDARY * 2;
4988 return PARM_BOUNDARY;
4991 /* True if it is OK to do sibling call optimization for the specified
4992 call expression EXP. DECL will be the called function, or NULL if
4993 this is an indirect call. */
4995 ia64_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
4997 /* We can't perform a sibcall if the current function has the syscall_linkage
4999 if (lookup_attribute ("syscall_linkage",
5000 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
5003 /* We must always return with our current GP. This means we can
5004 only sibcall to functions defined in the current module unless
5005 TARGET_CONST_GP is set to true. */
5006 return (decl && (*targetm.binds_local_p) (decl)) || TARGET_CONST_GP;
5010 /* Implement va_arg. */
5013 ia64_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
5016 /* Variable sized types are passed by reference. */
5017 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
5019 tree ptrtype = build_pointer_type (type);
5020 tree addr = std_gimplify_va_arg_expr (valist, ptrtype, pre_p, post_p);
5021 return build_va_arg_indirect_ref (addr);
5024 /* Aggregate arguments with alignment larger than 8 bytes start at
5025 the next even boundary. Integer and floating point arguments
5026 do so if they are larger than 8 bytes, whether or not they are
5027 also aligned larger than 8 bytes. */
5028 if ((TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == INTEGER_TYPE)
5029 ? int_size_in_bytes (type) > 8 : TYPE_ALIGN (type) > 8 * BITS_PER_UNIT)
5031 tree t = fold_build_pointer_plus_hwi (valist, 2 * UNITS_PER_WORD - 1);
5032 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
5033 build_int_cst (TREE_TYPE (t), -2 * UNITS_PER_WORD));
5034 gimplify_assign (unshare_expr (valist), t, pre_p);
5037 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5040 /* Return 1 if function return value returned in memory. Return 0 if it is
5044 ia64_return_in_memory (const_tree valtype, const_tree fntype ATTRIBUTE_UNUSED)
5046 enum machine_mode mode;
5047 enum machine_mode hfa_mode;
5048 HOST_WIDE_INT byte_size;
5050 mode = TYPE_MODE (valtype);
5051 byte_size = GET_MODE_SIZE (mode);
5052 if (mode == BLKmode)
5054 byte_size = int_size_in_bytes (valtype);
5059 /* Hfa's with up to 8 elements are returned in the FP argument registers. */
5061 hfa_mode = hfa_element_mode (valtype, 0);
5062 if (hfa_mode != VOIDmode)
5064 int hfa_size = GET_MODE_SIZE (hfa_mode);
5066 if (byte_size / hfa_size > MAX_ARGUMENT_SLOTS)
5071 else if (byte_size > UNITS_PER_WORD * MAX_INT_RETURN_SLOTS)
5077 /* Return rtx for register that holds the function return value. */
5080 ia64_function_value (const_tree valtype,
5081 const_tree fn_decl_or_type,
5082 bool outgoing ATTRIBUTE_UNUSED)
5084 enum machine_mode mode;
5085 enum machine_mode hfa_mode;
5087 const_tree func = fn_decl_or_type;
5090 && !DECL_P (fn_decl_or_type))
5093 mode = TYPE_MODE (valtype);
5094 hfa_mode = hfa_element_mode (valtype, 0);
5096 if (hfa_mode != VOIDmode)
5104 hfa_size = GET_MODE_SIZE (hfa_mode);
5105 byte_size = ((mode == BLKmode)
5106 ? int_size_in_bytes (valtype) : GET_MODE_SIZE (mode));
5108 for (i = 0; offset < byte_size; i++)
5110 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
5111 gen_rtx_REG (hfa_mode, FR_ARG_FIRST + i),
5115 return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
5117 else if (FLOAT_TYPE_P (valtype) && mode != TFmode && mode != TCmode)
5118 return gen_rtx_REG (mode, FR_ARG_FIRST);
5121 bool need_parallel = false;
5123 /* In big-endian mode, we need to manage the layout of aggregates
5124 in the registers so that we get the bits properly aligned in
5125 the highpart of the registers. */
5126 if (BYTES_BIG_ENDIAN
5127 && (mode == BLKmode || (valtype && AGGREGATE_TYPE_P (valtype))))
5128 need_parallel = true;
5130 /* Something like struct S { long double x; char a[0] } is not an
5131 HFA structure, and therefore doesn't go in fp registers. But
5132 the middle-end will give it XFmode anyway, and XFmode values
5133 don't normally fit in integer registers. So we need to smuggle
5134 the value inside a parallel. */
5135 else if (mode == XFmode || mode == XCmode || mode == RFmode)
5136 need_parallel = true;
5146 bytesize = int_size_in_bytes (valtype);
5147 /* An empty PARALLEL is invalid here, but the return value
5148 doesn't matter for empty structs. */
5150 return gen_rtx_REG (mode, GR_RET_FIRST);
5151 for (i = 0; offset < bytesize; i++)
5153 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
5154 gen_rtx_REG (DImode,
5157 offset += UNITS_PER_WORD;
5159 return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
5162 mode = promote_function_mode (valtype, mode, &unsignedp,
5163 func ? TREE_TYPE (func) : NULL_TREE,
5166 return gen_rtx_REG (mode, GR_RET_FIRST);
5170 /* Worker function for TARGET_LIBCALL_VALUE. */
5173 ia64_libcall_value (enum machine_mode mode,
5174 const_rtx fun ATTRIBUTE_UNUSED)
5176 return gen_rtx_REG (mode,
5177 (((GET_MODE_CLASS (mode) == MODE_FLOAT
5178 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5179 && (mode) != TFmode)
5180 ? FR_RET_FIRST : GR_RET_FIRST));
5183 /* Worker function for FUNCTION_VALUE_REGNO_P. */
5186 ia64_function_value_regno_p (const unsigned int regno)
5188 return ((regno >= GR_RET_FIRST && regno <= GR_RET_LAST)
5189 || (regno >= FR_RET_FIRST && regno <= FR_RET_LAST));
5192 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
5193 We need to emit DTP-relative relocations. */
5196 ia64_output_dwarf_dtprel (FILE *file, int size, rtx x)
5198 gcc_assert (size == 4 || size == 8);
5200 fputs ("\tdata4.ua\t@dtprel(", file);
5202 fputs ("\tdata8.ua\t@dtprel(", file);
5203 output_addr_const (file, x);
5207 /* Print a memory address as an operand to reference that memory location. */
5209 /* ??? Do we need this? It gets used only for 'a' operands. We could perhaps
5210 also call this from ia64_print_operand for memory addresses. */
5213 ia64_print_operand_address (FILE * stream ATTRIBUTE_UNUSED,
5214 rtx address ATTRIBUTE_UNUSED)
5218 /* Print an operand to an assembler instruction.
5219 C Swap and print a comparison operator.
5220 D Print an FP comparison operator.
5221 E Print 32 - constant, for SImode shifts as extract.
5222 e Print 64 - constant, for DImode rotates.
5223 F A floating point constant 0.0 emitted as f0, or 1.0 emitted as f1, or
5224 a floating point register emitted normally.
5225 G A floating point constant.
5226 I Invert a predicate register by adding 1.
5227 J Select the proper predicate register for a condition.
5228 j Select the inverse predicate register for a condition.
5229 O Append .acq for volatile load.
5230 P Postincrement of a MEM.
5231 Q Append .rel for volatile store.
5232 R Print .s .d or nothing for a single, double or no truncation.
5233 S Shift amount for shladd instruction.
5234 T Print an 8-bit sign extended number (K) as a 32-bit unsigned number
5235 for Intel assembler.
5236 U Print an 8-bit sign extended number (K) as a 64-bit unsigned number
5237 for Intel assembler.
5238 X A pair of floating point registers.
5239 r Print register name, or constant 0 as r0. HP compatibility for
5241 v Print vector constant value as an 8-byte integer value. */
5244 ia64_print_operand (FILE * file, rtx x, int code)
5251 /* Handled below. */
5256 enum rtx_code c = swap_condition (GET_CODE (x));
5257 fputs (GET_RTX_NAME (c), file);
5262 switch (GET_CODE (x))
5286 str = GET_RTX_NAME (GET_CODE (x));
5293 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - INTVAL (x));
5297 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - INTVAL (x));
5301 if (x == CONST0_RTX (GET_MODE (x)))
5302 str = reg_names [FR_REG (0)];
5303 else if (x == CONST1_RTX (GET_MODE (x)))
5304 str = reg_names [FR_REG (1)];
5307 gcc_assert (GET_CODE (x) == REG);
5308 str = reg_names [REGNO (x)];
5317 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
5318 real_to_target (val, &rv, GET_MODE (x));
5319 if (GET_MODE (x) == SFmode)
5320 fprintf (file, "0x%08lx", val[0] & 0xffffffff);
5321 else if (GET_MODE (x) == DFmode)
5322 fprintf (file, "0x%08lx%08lx", (WORDS_BIG_ENDIAN ? val[0] : val[1])
5324 (WORDS_BIG_ENDIAN ? val[1] : val[0])
5327 output_operand_lossage ("invalid %%G mode");
5332 fputs (reg_names [REGNO (x) + 1], file);
5338 unsigned int regno = REGNO (XEXP (x, 0));
5339 if (GET_CODE (x) == EQ)
5343 fputs (reg_names [regno], file);
5348 if (MEM_VOLATILE_P (x))
5349 fputs(".acq", file);
5354 HOST_WIDE_INT value;
5356 switch (GET_CODE (XEXP (x, 0)))
5362 x = XEXP (XEXP (XEXP (x, 0), 1), 1);
5363 if (GET_CODE (x) == CONST_INT)
5367 gcc_assert (GET_CODE (x) == REG);
5368 fprintf (file, ", %s", reg_names[REGNO (x)]);
5374 value = GET_MODE_SIZE (GET_MODE (x));
5378 value = - (HOST_WIDE_INT) GET_MODE_SIZE (GET_MODE (x));
5382 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC, value);
5387 if (MEM_VOLATILE_P (x))
5388 fputs(".rel", file);
5392 if (x == CONST0_RTX (GET_MODE (x)))
5394 else if (x == CONST1_RTX (GET_MODE (x)))
5396 else if (x == CONST2_RTX (GET_MODE (x)))
5399 output_operand_lossage ("invalid %%R value");
5403 fprintf (file, "%d", exact_log2 (INTVAL (x)));
5407 if (! TARGET_GNU_AS && GET_CODE (x) == CONST_INT)
5409 fprintf (file, "0x%x", (int) INTVAL (x) & 0xffffffff);
5415 if (! TARGET_GNU_AS && GET_CODE (x) == CONST_INT)
5417 const char *prefix = "0x";
5418 if (INTVAL (x) & 0x80000000)
5420 fprintf (file, "0xffffffff");
5423 fprintf (file, "%s%x", prefix, (int) INTVAL (x) & 0xffffffff);
5430 unsigned int regno = REGNO (x);
5431 fprintf (file, "%s, %s", reg_names [regno], reg_names [regno + 1]);
5436 /* If this operand is the constant zero, write it as register zero.
5437 Any register, zero, or CONST_INT value is OK here. */
5438 if (GET_CODE (x) == REG)
5439 fputs (reg_names[REGNO (x)], file);
5440 else if (x == CONST0_RTX (GET_MODE (x)))
5442 else if (GET_CODE (x) == CONST_INT)
5443 output_addr_const (file, x);
5445 output_operand_lossage ("invalid %%r value");
5449 gcc_assert (GET_CODE (x) == CONST_VECTOR);
5450 x = simplify_subreg (DImode, x, GET_MODE (x), 0);
5457 /* For conditional branches, returns or calls, substitute
5458 sptk, dptk, dpnt, or spnt for %s. */
5459 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
5462 int pred_val = INTVAL (XEXP (x, 0));
5464 /* Guess top and bottom 10% statically predicted. */
5465 if (pred_val < REG_BR_PROB_BASE / 50
5466 && br_prob_note_reliable_p (x))
5468 else if (pred_val < REG_BR_PROB_BASE / 2)
5470 else if (pred_val < REG_BR_PROB_BASE / 100 * 98
5471 || !br_prob_note_reliable_p (x))
5476 else if (GET_CODE (current_output_insn) == CALL_INSN)
5481 fputs (which, file);
5486 x = current_insn_predicate;
5489 unsigned int regno = REGNO (XEXP (x, 0));
5490 if (GET_CODE (x) == EQ)
5492 fprintf (file, "(%s) ", reg_names [regno]);
5497 output_operand_lossage ("ia64_print_operand: unknown code");
5501 switch (GET_CODE (x))
5503 /* This happens for the spill/restore instructions. */
5508 /* ... fall through ... */
5511 fputs (reg_names [REGNO (x)], file);
5516 rtx addr = XEXP (x, 0);
5517 if (GET_RTX_CLASS (GET_CODE (addr)) == RTX_AUTOINC)
5518 addr = XEXP (addr, 0);
5519 fprintf (file, "[%s]", reg_names [REGNO (addr)]);
5524 output_addr_const (file, x);
5531 /* Worker function for TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
5534 ia64_print_operand_punct_valid_p (unsigned char code)
5536 return (code == '+' || code == ',');
5539 /* Compute a (partial) cost for rtx X. Return true if the complete
5540 cost has been computed, and false if subexpressions should be
5541 scanned. In either case, *TOTAL contains the cost result. */
5542 /* ??? This is incomplete. */
5545 ia64_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
5546 int *total, bool speed ATTRIBUTE_UNUSED)
5554 *total = satisfies_constraint_J (x) ? 0 : COSTS_N_INSNS (1);
5557 if (satisfies_constraint_I (x))
5559 else if (satisfies_constraint_J (x))
5562 *total = COSTS_N_INSNS (1);
5565 if (satisfies_constraint_K (x) || satisfies_constraint_L (x))
5568 *total = COSTS_N_INSNS (1);
5573 *total = COSTS_N_INSNS (1);
5579 *total = COSTS_N_INSNS (3);
5583 *total = COSTS_N_INSNS (4);
5587 /* For multiplies wider than HImode, we have to go to the FPU,
5588 which normally involves copies. Plus there's the latency
5589 of the multiply itself, and the latency of the instructions to
5590 transfer integer regs to FP regs. */
5591 if (FLOAT_MODE_P (GET_MODE (x)))
5592 *total = COSTS_N_INSNS (4);
5593 else if (GET_MODE_SIZE (GET_MODE (x)) > 2)
5594 *total = COSTS_N_INSNS (10);
5596 *total = COSTS_N_INSNS (2);
5601 if (FLOAT_MODE_P (GET_MODE (x)))
5603 *total = COSTS_N_INSNS (4);
5611 *total = COSTS_N_INSNS (1);
5618 /* We make divide expensive, so that divide-by-constant will be
5619 optimized to a multiply. */
5620 *total = COSTS_N_INSNS (60);
5628 /* Calculate the cost of moving data from a register in class FROM to
5629 one in class TO, using MODE. */
5632 ia64_register_move_cost (enum machine_mode mode, reg_class_t from,
5635 /* ADDL_REGS is the same as GR_REGS for movement purposes. */
5636 if (to == ADDL_REGS)
5638 if (from == ADDL_REGS)
5641 /* All costs are symmetric, so reduce cases by putting the
5642 lower number class as the destination. */
5645 reg_class_t tmp = to;
5646 to = from, from = tmp;
5649 /* Moving from FR<->GR in XFmode must be more expensive than 2,
5650 so that we get secondary memory reloads. Between FR_REGS,
5651 we have to make this at least as expensive as memory_move_cost
5652 to avoid spectacularly poor register class preferencing. */
5653 if (mode == XFmode || mode == RFmode)
5655 if (to != GR_REGS || from != GR_REGS)
5656 return memory_move_cost (mode, to, false);
5664 /* Moving between PR registers takes two insns. */
5665 if (from == PR_REGS)
5667 /* Moving between PR and anything but GR is impossible. */
5668 if (from != GR_REGS)
5669 return memory_move_cost (mode, to, false);
5673 /* Moving between BR and anything but GR is impossible. */
5674 if (from != GR_REGS && from != GR_AND_BR_REGS)
5675 return memory_move_cost (mode, to, false);
5680 /* Moving between AR and anything but GR is impossible. */
5681 if (from != GR_REGS)
5682 return memory_move_cost (mode, to, false);
5688 case GR_AND_FR_REGS:
5689 case GR_AND_BR_REGS:
5700 /* Calculate the cost of moving data of MODE from a register to or from
5704 ia64_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
5706 bool in ATTRIBUTE_UNUSED)
5708 if (rclass == GENERAL_REGS
5709 || rclass == FR_REGS
5710 || rclass == FP_REGS
5711 || rclass == GR_AND_FR_REGS)
5717 /* Implement TARGET_PREFERRED_RELOAD_CLASS. Place additional restrictions
5718 on RCLASS to use when copying X into that class. */
5721 ia64_preferred_reload_class (rtx x, reg_class_t rclass)
5727 /* Don't allow volatile mem reloads into floating point registers.
5728 This is defined to force reload to choose the r/m case instead
5729 of the f/f case when reloading (set (reg fX) (mem/v)). */
5730 if (MEM_P (x) && MEM_VOLATILE_P (x))
5733 /* Force all unrecognized constants into the constant pool. */
5751 /* This function returns the register class required for a secondary
5752 register when copying between one of the registers in RCLASS, and X,
5753 using MODE. A return value of NO_REGS means that no secondary register
5757 ia64_secondary_reload_class (enum reg_class rclass,
5758 enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
5762 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
5763 regno = true_regnum (x);
5770 /* ??? BR<->BR register copies can happen due to a bad gcse/cse/global
5771 interaction. We end up with two pseudos with overlapping lifetimes
5772 both of which are equiv to the same constant, and both which need
5773 to be in BR_REGS. This seems to be a cse bug. cse_basic_block_end
5774 changes depending on the path length, which means the qty_first_reg
5775 check in make_regs_eqv can give different answers at different times.
5776 At some point I'll probably need a reload_indi pattern to handle
5779 We can also get GR_AND_FR_REGS to BR_REGS/AR_REGS copies, where we
5780 wound up with a FP register from GR_AND_FR_REGS. Extend that to all
5781 non-general registers for good measure. */
5782 if (regno >= 0 && ! GENERAL_REGNO_P (regno))
5785 /* This is needed if a pseudo used as a call_operand gets spilled to a
5787 if (GET_CODE (x) == MEM)
5793 /* Need to go through general registers to get to other class regs. */
5794 if (regno >= 0 && ! (FR_REGNO_P (regno) || GENERAL_REGNO_P (regno)))
5797 /* This can happen when a paradoxical subreg is an operand to the
5799 /* ??? This shouldn't be necessary after instruction scheduling is
5800 enabled, because paradoxical subregs are not accepted by
5801 register_operand when INSN_SCHEDULING is defined. Or alternatively,
5802 stop the paradoxical subreg stupidity in the *_operand functions
5804 if (GET_CODE (x) == MEM
5805 && (GET_MODE (x) == SImode || GET_MODE (x) == HImode
5806 || GET_MODE (x) == QImode))
5809 /* This can happen because of the ior/and/etc patterns that accept FP
5810 registers as operands. If the third operand is a constant, then it
5811 needs to be reloaded into a FP register. */
5812 if (GET_CODE (x) == CONST_INT)
5815 /* This can happen because of register elimination in a muldi3 insn.
5816 E.g. `26107 * (unsigned long)&u'. */
5817 if (GET_CODE (x) == PLUS)
5822 /* ??? This happens if we cse/gcse a BImode value across a call,
5823 and the function has a nonlocal goto. This is because global
5824 does not allocate call crossing pseudos to hard registers when
5825 crtl->has_nonlocal_goto is true. This is relatively
5826 common for C++ programs that use exceptions. To reproduce,
5827 return NO_REGS and compile libstdc++. */
5828 if (GET_CODE (x) == MEM)
5831 /* This can happen when we take a BImode subreg of a DImode value,
5832 and that DImode value winds up in some non-GR register. */
5833 if (regno >= 0 && ! GENERAL_REGNO_P (regno) && ! PR_REGNO_P (regno))
5845 /* Implement targetm.unspec_may_trap_p hook. */
5847 ia64_unspec_may_trap_p (const_rtx x, unsigned flags)
5849 if (GET_CODE (x) == UNSPEC)
5851 switch (XINT (x, 1))
5857 case UNSPEC_CHKACLR:
5859 /* These unspecs are just wrappers. */
5860 return may_trap_p_1 (XVECEXP (x, 0, 0), flags);
5864 return default_unspec_may_trap_p (x, flags);
5868 /* Parse the -mfixed-range= option string. */
5871 fix_range (const char *const_str)
5874 char *str, *dash, *comma;
5876 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
5877 REG2 are either register names or register numbers. The effect
5878 of this option is to mark the registers in the range from REG1 to
5879 REG2 as ``fixed'' so they won't be used by the compiler. This is
5880 used, e.g., to ensure that kernel mode code doesn't use f32-f127. */
5882 i = strlen (const_str);
5883 str = (char *) alloca (i + 1);
5884 memcpy (str, const_str, i + 1);
5888 dash = strchr (str, '-');
5891 warning (0, "value of -mfixed-range must have form REG1-REG2");
5896 comma = strchr (dash + 1, ',');
5900 first = decode_reg_name (str);
5903 warning (0, "unknown register name: %s", str);
5907 last = decode_reg_name (dash + 1);
5910 warning (0, "unknown register name: %s", dash + 1);
5918 warning (0, "%s-%s is an empty range", str, dash + 1);
5922 for (i = first; i <= last; ++i)
5923 fixed_regs[i] = call_used_regs[i] = 1;
5933 /* Implement TARGET_OPTION_OVERRIDE. */
5936 ia64_option_override (void)
5939 cl_deferred_option *opt;
5940 VEC(cl_deferred_option,heap) *vec
5941 = (VEC(cl_deferred_option,heap) *) ia64_deferred_options;
5943 FOR_EACH_VEC_ELT (cl_deferred_option, vec, i, opt)
5945 switch (opt->opt_index)
5947 case OPT_mfixed_range_:
5948 fix_range (opt->arg);
5956 if (TARGET_AUTO_PIC)
5957 target_flags |= MASK_CONST_GP;
5959 /* Numerous experiment shows that IRA based loop pressure
5960 calculation works better for RTL loop invariant motion on targets
5961 with enough (>= 32) registers. It is an expensive optimization.
5962 So it is on only for peak performance. */
5964 flag_ira_loop_pressure = 1;
5967 ia64_section_threshold = (global_options_set.x_g_switch_value
5969 : IA64_DEFAULT_GVALUE);
5971 init_machine_status = ia64_init_machine_status;
5973 if (align_functions <= 0)
5974 align_functions = 64;
5975 if (align_loops <= 0)
5977 if (TARGET_ABI_OPEN_VMS)
5980 ia64_override_options_after_change();
5983 /* Implement targetm.override_options_after_change. */
5986 ia64_override_options_after_change (void)
5989 && !global_options_set.x_flag_selective_scheduling
5990 && !global_options_set.x_flag_selective_scheduling2)
5992 flag_selective_scheduling2 = 1;
5993 flag_sel_sched_pipelining = 1;
5995 if (mflag_sched_control_spec == 2)
5997 /* Control speculation is on by default for the selective scheduler,
5998 but not for the Haifa scheduler. */
5999 mflag_sched_control_spec = flag_selective_scheduling2 ? 1 : 0;
6001 if (flag_sel_sched_pipelining && flag_auto_inc_dec)
6003 /* FIXME: remove this when we'd implement breaking autoinsns as
6004 a transformation. */
6005 flag_auto_inc_dec = 0;
6009 /* Initialize the record of emitted frame related registers. */
6011 void ia64_init_expanders (void)
6013 memset (&emitted_frame_related_regs, 0, sizeof (emitted_frame_related_regs));
6016 static struct machine_function *
6017 ia64_init_machine_status (void)
6019 return ggc_alloc_cleared_machine_function ();
6022 static enum attr_itanium_class ia64_safe_itanium_class (rtx);
6023 static enum attr_type ia64_safe_type (rtx);
6025 static enum attr_itanium_class
6026 ia64_safe_itanium_class (rtx insn)
6028 if (recog_memoized (insn) >= 0)
6029 return get_attr_itanium_class (insn);
6030 else if (DEBUG_INSN_P (insn))
6031 return ITANIUM_CLASS_IGNORE;
6033 return ITANIUM_CLASS_UNKNOWN;
6036 static enum attr_type
6037 ia64_safe_type (rtx insn)
6039 if (recog_memoized (insn) >= 0)
6040 return get_attr_type (insn);
6042 return TYPE_UNKNOWN;
6045 /* The following collection of routines emit instruction group stop bits as
6046 necessary to avoid dependencies. */
6048 /* Need to track some additional registers as far as serialization is
6049 concerned so we can properly handle br.call and br.ret. We could
6050 make these registers visible to gcc, but since these registers are
6051 never explicitly used in gcc generated code, it seems wasteful to
6052 do so (plus it would make the call and return patterns needlessly
6054 #define REG_RP (BR_REG (0))
6055 #define REG_AR_CFM (FIRST_PSEUDO_REGISTER + 1)
6056 /* This is used for volatile asms which may require a stop bit immediately
6057 before and after them. */
6058 #define REG_VOLATILE (FIRST_PSEUDO_REGISTER + 2)
6059 #define AR_UNAT_BIT_0 (FIRST_PSEUDO_REGISTER + 3)
6060 #define NUM_REGS (AR_UNAT_BIT_0 + 64)
6062 /* For each register, we keep track of how it has been written in the
6063 current instruction group.
6065 If a register is written unconditionally (no qualifying predicate),
6066 WRITE_COUNT is set to 2 and FIRST_PRED is ignored.
6068 If a register is written if its qualifying predicate P is true, we
6069 set WRITE_COUNT to 1 and FIRST_PRED to P. Later on, the same register
6070 may be written again by the complement of P (P^1) and when this happens,
6071 WRITE_COUNT gets set to 2.
6073 The result of this is that whenever an insn attempts to write a register
6074 whose WRITE_COUNT is two, we need to issue an insn group barrier first.
6076 If a predicate register is written by a floating-point insn, we set
6077 WRITTEN_BY_FP to true.
6079 If a predicate register is written by an AND.ORCM we set WRITTEN_BY_AND
6080 to true; if it was written by an OR.ANDCM we set WRITTEN_BY_OR to true. */
6082 #if GCC_VERSION >= 4000
6083 #define RWS_FIELD_TYPE __extension__ unsigned short
6085 #define RWS_FIELD_TYPE unsigned int
6087 struct reg_write_state
6089 RWS_FIELD_TYPE write_count : 2;
6090 RWS_FIELD_TYPE first_pred : 10;
6091 RWS_FIELD_TYPE written_by_fp : 1;
6092 RWS_FIELD_TYPE written_by_and : 1;
6093 RWS_FIELD_TYPE written_by_or : 1;
6096 /* Cumulative info for the current instruction group. */
6097 struct reg_write_state rws_sum[NUM_REGS];
6098 #ifdef ENABLE_CHECKING
6099 /* Bitmap whether a register has been written in the current insn. */
6100 HARD_REG_ELT_TYPE rws_insn[(NUM_REGS + HOST_BITS_PER_WIDEST_FAST_INT - 1)
6101 / HOST_BITS_PER_WIDEST_FAST_INT];
6104 rws_insn_set (int regno)
6106 gcc_assert (!TEST_HARD_REG_BIT (rws_insn, regno));
6107 SET_HARD_REG_BIT (rws_insn, regno);
6111 rws_insn_test (int regno)
6113 return TEST_HARD_REG_BIT (rws_insn, regno);
6116 /* When not checking, track just REG_AR_CFM and REG_VOLATILE. */
6117 unsigned char rws_insn[2];
6120 rws_insn_set (int regno)
6122 if (regno == REG_AR_CFM)
6124 else if (regno == REG_VOLATILE)
6129 rws_insn_test (int regno)
6131 if (regno == REG_AR_CFM)
6133 if (regno == REG_VOLATILE)
6139 /* Indicates whether this is the first instruction after a stop bit,
6140 in which case we don't need another stop bit. Without this,
6141 ia64_variable_issue will die when scheduling an alloc. */
6142 static int first_instruction;
6144 /* Misc flags needed to compute RAW/WAW dependencies while we are traversing
6145 RTL for one instruction. */
6148 unsigned int is_write : 1; /* Is register being written? */
6149 unsigned int is_fp : 1; /* Is register used as part of an fp op? */
6150 unsigned int is_branch : 1; /* Is register used as part of a branch? */
6151 unsigned int is_and : 1; /* Is register used as part of and.orcm? */
6152 unsigned int is_or : 1; /* Is register used as part of or.andcm? */
6153 unsigned int is_sibcall : 1; /* Is this a sibling or normal call? */
6156 static void rws_update (int, struct reg_flags, int);
6157 static int rws_access_regno (int, struct reg_flags, int);
6158 static int rws_access_reg (rtx, struct reg_flags, int);
6159 static void update_set_flags (rtx, struct reg_flags *);
6160 static int set_src_needs_barrier (rtx, struct reg_flags, int);
6161 static int rtx_needs_barrier (rtx, struct reg_flags, int);
6162 static void init_insn_group_barriers (void);
6163 static int group_barrier_needed (rtx);
6164 static int safe_group_barrier_needed (rtx);
6165 static int in_safe_group_barrier;
6167 /* Update *RWS for REGNO, which is being written by the current instruction,
6168 with predicate PRED, and associated register flags in FLAGS. */
6171 rws_update (int regno, struct reg_flags flags, int pred)
6174 rws_sum[regno].write_count++;
6176 rws_sum[regno].write_count = 2;
6177 rws_sum[regno].written_by_fp |= flags.is_fp;
6178 /* ??? Not tracking and/or across differing predicates. */
6179 rws_sum[regno].written_by_and = flags.is_and;
6180 rws_sum[regno].written_by_or = flags.is_or;
6181 rws_sum[regno].first_pred = pred;
6184 /* Handle an access to register REGNO of type FLAGS using predicate register
6185 PRED. Update rws_sum array. Return 1 if this access creates
6186 a dependency with an earlier instruction in the same group. */
6189 rws_access_regno (int regno, struct reg_flags flags, int pred)
6191 int need_barrier = 0;
6193 gcc_assert (regno < NUM_REGS);
6195 if (! PR_REGNO_P (regno))
6196 flags.is_and = flags.is_or = 0;
6202 rws_insn_set (regno);
6203 write_count = rws_sum[regno].write_count;
6205 switch (write_count)
6208 /* The register has not been written yet. */
6209 if (!in_safe_group_barrier)
6210 rws_update (regno, flags, pred);
6214 /* The register has been written via a predicate. Treat
6215 it like a unconditional write and do not try to check
6216 for complementary pred reg in earlier write. */
6217 if (flags.is_and && rws_sum[regno].written_by_and)
6219 else if (flags.is_or && rws_sum[regno].written_by_or)
6223 if (!in_safe_group_barrier)
6224 rws_update (regno, flags, pred);
6228 /* The register has been unconditionally written already. We
6230 if (flags.is_and && rws_sum[regno].written_by_and)
6232 else if (flags.is_or && rws_sum[regno].written_by_or)
6236 if (!in_safe_group_barrier)
6238 rws_sum[regno].written_by_and = flags.is_and;
6239 rws_sum[regno].written_by_or = flags.is_or;
6249 if (flags.is_branch)
6251 /* Branches have several RAW exceptions that allow to avoid
6254 if (REGNO_REG_CLASS (regno) == BR_REGS || regno == AR_PFS_REGNUM)
6255 /* RAW dependencies on branch regs are permissible as long
6256 as the writer is a non-branch instruction. Since we
6257 never generate code that uses a branch register written
6258 by a branch instruction, handling this case is
6262 if (REGNO_REG_CLASS (regno) == PR_REGS
6263 && ! rws_sum[regno].written_by_fp)
6264 /* The predicates of a branch are available within the
6265 same insn group as long as the predicate was written by
6266 something other than a floating-point instruction. */
6270 if (flags.is_and && rws_sum[regno].written_by_and)
6272 if (flags.is_or && rws_sum[regno].written_by_or)
6275 switch (rws_sum[regno].write_count)
6278 /* The register has not been written yet. */
6282 /* The register has been written via a predicate, assume we
6283 need a barrier (don't check for complementary regs). */
6288 /* The register has been unconditionally written already. We
6298 return need_barrier;
6302 rws_access_reg (rtx reg, struct reg_flags flags, int pred)
6304 int regno = REGNO (reg);
6305 int n = HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg));
6308 return rws_access_regno (regno, flags, pred);
6311 int need_barrier = 0;
6313 need_barrier |= rws_access_regno (regno + n, flags, pred);
6314 return need_barrier;
6318 /* Examine X, which is a SET rtx, and update the flags, the predicate, and
6319 the condition, stored in *PFLAGS, *PPRED and *PCOND. */
6322 update_set_flags (rtx x, struct reg_flags *pflags)
6324 rtx src = SET_SRC (x);
6326 switch (GET_CODE (src))
6332 /* There are four cases here:
6333 (1) The destination is (pc), in which case this is a branch,
6334 nothing here applies.
6335 (2) The destination is ar.lc, in which case this is a
6336 doloop_end_internal,
6337 (3) The destination is an fp register, in which case this is
6338 an fselect instruction.
6339 (4) The condition has (unspec [(reg)] UNSPEC_LDC), in which case
6340 this is a check load.
6341 In all cases, nothing we do in this function applies. */
6345 if (COMPARISON_P (src)
6346 && SCALAR_FLOAT_MODE_P (GET_MODE (XEXP (src, 0))))
6347 /* Set pflags->is_fp to 1 so that we know we're dealing
6348 with a floating point comparison when processing the
6349 destination of the SET. */
6352 /* Discover if this is a parallel comparison. We only handle
6353 and.orcm and or.andcm at present, since we must retain a
6354 strict inverse on the predicate pair. */
6355 else if (GET_CODE (src) == AND)
6357 else if (GET_CODE (src) == IOR)
6364 /* Subroutine of rtx_needs_barrier; this function determines whether the
6365 source of a given SET rtx found in X needs a barrier. FLAGS and PRED
6366 are as in rtx_needs_barrier. COND is an rtx that holds the condition
6370 set_src_needs_barrier (rtx x, struct reg_flags flags, int pred)
6372 int need_barrier = 0;
6374 rtx src = SET_SRC (x);
6376 if (GET_CODE (src) == CALL)
6377 /* We don't need to worry about the result registers that
6378 get written by subroutine call. */
6379 return rtx_needs_barrier (src, flags, pred);
6380 else if (SET_DEST (x) == pc_rtx)
6382 /* X is a conditional branch. */
6383 /* ??? This seems redundant, as the caller sets this bit for
6385 if (!ia64_spec_check_src_p (src))
6386 flags.is_branch = 1;
6387 return rtx_needs_barrier (src, flags, pred);
6390 if (ia64_spec_check_src_p (src))
6391 /* Avoid checking one register twice (in condition
6392 and in 'then' section) for ldc pattern. */
6394 gcc_assert (REG_P (XEXP (src, 2)));
6395 need_barrier = rtx_needs_barrier (XEXP (src, 2), flags, pred);
6397 /* We process MEM below. */
6398 src = XEXP (src, 1);
6401 need_barrier |= rtx_needs_barrier (src, flags, pred);
6404 if (GET_CODE (dst) == ZERO_EXTRACT)
6406 need_barrier |= rtx_needs_barrier (XEXP (dst, 1), flags, pred);
6407 need_barrier |= rtx_needs_barrier (XEXP (dst, 2), flags, pred);
6409 return need_barrier;
6412 /* Handle an access to rtx X of type FLAGS using predicate register
6413 PRED. Return 1 if this access creates a dependency with an earlier
6414 instruction in the same group. */
6417 rtx_needs_barrier (rtx x, struct reg_flags flags, int pred)
6420 int is_complemented = 0;
6421 int need_barrier = 0;
6422 const char *format_ptr;
6423 struct reg_flags new_flags;
6431 switch (GET_CODE (x))
6434 update_set_flags (x, &new_flags);
6435 need_barrier = set_src_needs_barrier (x, new_flags, pred);
6436 if (GET_CODE (SET_SRC (x)) != CALL)
6438 new_flags.is_write = 1;
6439 need_barrier |= rtx_needs_barrier (SET_DEST (x), new_flags, pred);
6444 new_flags.is_write = 0;
6445 need_barrier |= rws_access_regno (AR_EC_REGNUM, new_flags, pred);
6447 /* Avoid multiple register writes, in case this is a pattern with
6448 multiple CALL rtx. This avoids a failure in rws_access_reg. */
6449 if (! flags.is_sibcall && ! rws_insn_test (REG_AR_CFM))
6451 new_flags.is_write = 1;
6452 need_barrier |= rws_access_regno (REG_RP, new_flags, pred);
6453 need_barrier |= rws_access_regno (AR_PFS_REGNUM, new_flags, pred);
6454 need_barrier |= rws_access_regno (REG_AR_CFM, new_flags, pred);
6459 /* X is a predicated instruction. */
6461 cond = COND_EXEC_TEST (x);
6463 need_barrier = rtx_needs_barrier (cond, flags, 0);
6465 if (GET_CODE (cond) == EQ)
6466 is_complemented = 1;
6467 cond = XEXP (cond, 0);
6468 gcc_assert (GET_CODE (cond) == REG
6469 && REGNO_REG_CLASS (REGNO (cond)) == PR_REGS);
6470 pred = REGNO (cond);
6471 if (is_complemented)
6474 need_barrier |= rtx_needs_barrier (COND_EXEC_CODE (x), flags, pred);
6475 return need_barrier;
6479 /* Clobber & use are for earlier compiler-phases only. */
6484 /* We always emit stop bits for traditional asms. We emit stop bits
6485 for volatile extended asms if TARGET_VOL_ASM_STOP is true. */
6486 if (GET_CODE (x) != ASM_OPERANDS
6487 || (MEM_VOLATILE_P (x) && TARGET_VOL_ASM_STOP))
6489 /* Avoid writing the register multiple times if we have multiple
6490 asm outputs. This avoids a failure in rws_access_reg. */
6491 if (! rws_insn_test (REG_VOLATILE))
6493 new_flags.is_write = 1;
6494 rws_access_regno (REG_VOLATILE, new_flags, pred);
6499 /* For all ASM_OPERANDS, we must traverse the vector of input operands.
6500 We cannot just fall through here since then we would be confused
6501 by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate
6502 traditional asms unlike their normal usage. */
6504 for (i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; --i)
6505 if (rtx_needs_barrier (ASM_OPERANDS_INPUT (x, i), flags, pred))
6510 for (i = XVECLEN (x, 0) - 1; i >= 0; --i)
6512 rtx pat = XVECEXP (x, 0, i);
6513 switch (GET_CODE (pat))
6516 update_set_flags (pat, &new_flags);
6517 need_barrier |= set_src_needs_barrier (pat, new_flags, pred);
6523 need_barrier |= rtx_needs_barrier (pat, flags, pred);
6527 if (REG_P (XEXP (pat, 0))
6528 && extract_asm_operands (x) != NULL_RTX
6529 && REGNO (XEXP (pat, 0)) != AR_UNAT_REGNUM)
6531 new_flags.is_write = 1;
6532 need_barrier |= rtx_needs_barrier (XEXP (pat, 0),
6545 for (i = XVECLEN (x, 0) - 1; i >= 0; --i)
6547 rtx pat = XVECEXP (x, 0, i);
6548 if (GET_CODE (pat) == SET)
6550 if (GET_CODE (SET_SRC (pat)) != CALL)
6552 new_flags.is_write = 1;
6553 need_barrier |= rtx_needs_barrier (SET_DEST (pat), new_flags,
6557 else if (GET_CODE (pat) == CLOBBER || GET_CODE (pat) == RETURN)
6558 need_barrier |= rtx_needs_barrier (pat, flags, pred);
6563 need_barrier |= rtx_needs_barrier (SUBREG_REG (x), flags, pred);
6566 if (REGNO (x) == AR_UNAT_REGNUM)
6568 for (i = 0; i < 64; ++i)
6569 need_barrier |= rws_access_regno (AR_UNAT_BIT_0 + i, flags, pred);
6572 need_barrier = rws_access_reg (x, flags, pred);
6576 /* Find the regs used in memory address computation. */
6577 new_flags.is_write = 0;
6578 need_barrier = rtx_needs_barrier (XEXP (x, 0), new_flags, pred);
6581 case CONST_INT: case CONST_DOUBLE: case CONST_VECTOR:
6582 case SYMBOL_REF: case LABEL_REF: case CONST:
6585 /* Operators with side-effects. */
6586 case POST_INC: case POST_DEC:
6587 gcc_assert (GET_CODE (XEXP (x, 0)) == REG);
6589 new_flags.is_write = 0;
6590 need_barrier = rws_access_reg (XEXP (x, 0), new_flags, pred);
6591 new_flags.is_write = 1;
6592 need_barrier |= rws_access_reg (XEXP (x, 0), new_flags, pred);
6596 gcc_assert (GET_CODE (XEXP (x, 0)) == REG);
6598 new_flags.is_write = 0;
6599 need_barrier = rws_access_reg (XEXP (x, 0), new_flags, pred);
6600 need_barrier |= rtx_needs_barrier (XEXP (x, 1), new_flags, pred);
6601 new_flags.is_write = 1;
6602 need_barrier |= rws_access_reg (XEXP (x, 0), new_flags, pred);
6605 /* Handle common unary and binary ops for efficiency. */
6606 case COMPARE: case PLUS: case MINUS: case MULT: case DIV:
6607 case MOD: case UDIV: case UMOD: case AND: case IOR:
6608 case XOR: case ASHIFT: case ROTATE: case ASHIFTRT: case LSHIFTRT:
6609 case ROTATERT: case SMIN: case SMAX: case UMIN: case UMAX:
6610 case NE: case EQ: case GE: case GT: case LE:
6611 case LT: case GEU: case GTU: case LEU: case LTU:
6612 need_barrier = rtx_needs_barrier (XEXP (x, 0), new_flags, pred);
6613 need_barrier |= rtx_needs_barrier (XEXP (x, 1), new_flags, pred);
6616 case NEG: case NOT: case SIGN_EXTEND: case ZERO_EXTEND:
6617 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: case FLOAT:
6618 case FIX: case UNSIGNED_FLOAT: case UNSIGNED_FIX: case ABS:
6619 case SQRT: case FFS: case POPCOUNT:
6620 need_barrier = rtx_needs_barrier (XEXP (x, 0), flags, pred);
6624 /* VEC_SELECT's second argument is a PARALLEL with integers that
6625 describe the elements selected. On ia64, those integers are
6626 always constants. Avoid walking the PARALLEL so that we don't
6627 get confused with "normal" parallels and then die. */
6628 need_barrier = rtx_needs_barrier (XEXP (x, 0), flags, pred);
6632 switch (XINT (x, 1))
6634 case UNSPEC_LTOFF_DTPMOD:
6635 case UNSPEC_LTOFF_DTPREL:
6637 case UNSPEC_LTOFF_TPREL:
6639 case UNSPEC_PRED_REL_MUTEX:
6640 case UNSPEC_PIC_CALL:
6642 case UNSPEC_FETCHADD_ACQ:
6643 case UNSPEC_FETCHADD_REL:
6644 case UNSPEC_BSP_VALUE:
6645 case UNSPEC_FLUSHRS:
6646 case UNSPEC_BUNDLE_SELECTOR:
6649 case UNSPEC_GR_SPILL:
6650 case UNSPEC_GR_RESTORE:
6652 HOST_WIDE_INT offset = INTVAL (XVECEXP (x, 0, 1));
6653 HOST_WIDE_INT bit = (offset >> 3) & 63;
6655 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
6656 new_flags.is_write = (XINT (x, 1) == UNSPEC_GR_SPILL);
6657 need_barrier |= rws_access_regno (AR_UNAT_BIT_0 + bit,
6662 case UNSPEC_FR_SPILL:
6663 case UNSPEC_FR_RESTORE:
6664 case UNSPEC_GETF_EXP:
6665 case UNSPEC_SETF_EXP:
6667 case UNSPEC_FR_SQRT_RECIP_APPROX:
6668 case UNSPEC_FR_SQRT_RECIP_APPROX_RES:
6673 case UNSPEC_CHKACLR:
6675 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
6678 case UNSPEC_FR_RECIP_APPROX:
6680 case UNSPEC_COPYSIGN:
6681 case UNSPEC_FR_RECIP_APPROX_RES:
6682 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
6683 need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred);
6686 case UNSPEC_CMPXCHG_ACQ:
6687 case UNSPEC_CMPXCHG_REL:
6688 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred);
6689 need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 2), flags, pred);
6697 case UNSPEC_VOLATILE:
6698 switch (XINT (x, 1))
6701 /* Alloc must always be the first instruction of a group.
6702 We force this by always returning true. */
6703 /* ??? We might get better scheduling if we explicitly check for
6704 input/local/output register dependencies, and modify the
6705 scheduler so that alloc is always reordered to the start of
6706 the current group. We could then eliminate all of the
6707 first_instruction code. */
6708 rws_access_regno (AR_PFS_REGNUM, flags, pred);
6710 new_flags.is_write = 1;
6711 rws_access_regno (REG_AR_CFM, new_flags, pred);
6714 case UNSPECV_SET_BSP:
6715 case UNSPECV_PROBE_STACK_RANGE:
6719 case UNSPECV_BLOCKAGE:
6720 case UNSPECV_INSN_GROUP_BARRIER:
6722 case UNSPECV_PSAC_ALL:
6723 case UNSPECV_PSAC_NORMAL:
6726 case UNSPECV_PROBE_STACK_ADDRESS:
6727 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
6736 new_flags.is_write = 0;
6737 need_barrier = rws_access_regno (REG_RP, flags, pred);
6738 need_barrier |= rws_access_regno (AR_PFS_REGNUM, flags, pred);
6740 new_flags.is_write = 1;
6741 need_barrier |= rws_access_regno (AR_EC_REGNUM, new_flags, pred);
6742 need_barrier |= rws_access_regno (REG_AR_CFM, new_flags, pred);
6746 format_ptr = GET_RTX_FORMAT (GET_CODE (x));
6747 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
6748 switch (format_ptr[i])
6750 case '0': /* unused field */
6751 case 'i': /* integer */
6752 case 'n': /* note */
6753 case 'w': /* wide integer */
6754 case 's': /* pointer to string */
6755 case 'S': /* optional pointer to string */
6759 if (rtx_needs_barrier (XEXP (x, i), flags, pred))
6764 for (j = XVECLEN (x, i) - 1; j >= 0; --j)
6765 if (rtx_needs_barrier (XVECEXP (x, i, j), flags, pred))
6774 return need_barrier;
6777 /* Clear out the state for group_barrier_needed at the start of a
6778 sequence of insns. */
6781 init_insn_group_barriers (void)
6783 memset (rws_sum, 0, sizeof (rws_sum));
6784 first_instruction = 1;
6787 /* Given the current state, determine whether a group barrier (a stop bit) is
6788 necessary before INSN. Return nonzero if so. This modifies the state to
6789 include the effects of INSN as a side-effect. */
6792 group_barrier_needed (rtx insn)
6795 int need_barrier = 0;
6796 struct reg_flags flags;
6798 memset (&flags, 0, sizeof (flags));
6799 switch (GET_CODE (insn))
6806 /* A barrier doesn't imply an instruction group boundary. */
6810 memset (rws_insn, 0, sizeof (rws_insn));
6814 flags.is_branch = 1;
6815 flags.is_sibcall = SIBLING_CALL_P (insn);
6816 memset (rws_insn, 0, sizeof (rws_insn));
6818 /* Don't bundle a call following another call. */
6819 if ((pat = prev_active_insn (insn))
6820 && GET_CODE (pat) == CALL_INSN)
6826 need_barrier = rtx_needs_barrier (PATTERN (insn), flags, 0);
6830 if (!ia64_spec_check_p (insn))
6831 flags.is_branch = 1;
6833 /* Don't bundle a jump following a call. */
6834 if ((pat = prev_active_insn (insn))
6835 && GET_CODE (pat) == CALL_INSN)
6843 if (GET_CODE (PATTERN (insn)) == USE
6844 || GET_CODE (PATTERN (insn)) == CLOBBER)
6845 /* Don't care about USE and CLOBBER "insns"---those are used to
6846 indicate to the optimizer that it shouldn't get rid of
6847 certain operations. */
6850 pat = PATTERN (insn);
6852 /* Ug. Hack hacks hacked elsewhere. */
6853 switch (recog_memoized (insn))
6855 /* We play dependency tricks with the epilogue in order
6856 to get proper schedules. Undo this for dv analysis. */
6857 case CODE_FOR_epilogue_deallocate_stack:
6858 case CODE_FOR_prologue_allocate_stack:
6859 pat = XVECEXP (pat, 0, 0);
6862 /* The pattern we use for br.cloop confuses the code above.
6863 The second element of the vector is representative. */
6864 case CODE_FOR_doloop_end_internal:
6865 pat = XVECEXP (pat, 0, 1);
6868 /* Doesn't generate code. */
6869 case CODE_FOR_pred_rel_mutex:
6870 case CODE_FOR_prologue_use:
6877 memset (rws_insn, 0, sizeof (rws_insn));
6878 need_barrier = rtx_needs_barrier (pat, flags, 0);
6880 /* Check to see if the previous instruction was a volatile
6883 need_barrier = rws_access_regno (REG_VOLATILE, flags, 0);
6891 if (first_instruction && important_for_bundling_p (insn))
6894 first_instruction = 0;
6897 return need_barrier;
6900 /* Like group_barrier_needed, but do not clobber the current state. */
6903 safe_group_barrier_needed (rtx insn)
6905 int saved_first_instruction;
6908 saved_first_instruction = first_instruction;
6909 in_safe_group_barrier = 1;
6911 t = group_barrier_needed (insn);
6913 first_instruction = saved_first_instruction;
6914 in_safe_group_barrier = 0;
6919 /* Scan the current function and insert stop bits as necessary to
6920 eliminate dependencies. This function assumes that a final
6921 instruction scheduling pass has been run which has already
6922 inserted most of the necessary stop bits. This function only
6923 inserts new ones at basic block boundaries, since these are
6924 invisible to the scheduler. */
6927 emit_insn_group_barriers (FILE *dump)
6931 int insns_since_last_label = 0;
6933 init_insn_group_barriers ();
6935 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6937 if (GET_CODE (insn) == CODE_LABEL)
6939 if (insns_since_last_label)
6941 insns_since_last_label = 0;
6943 else if (GET_CODE (insn) == NOTE
6944 && NOTE_KIND (insn) == NOTE_INSN_BASIC_BLOCK)
6946 if (insns_since_last_label)
6948 insns_since_last_label = 0;
6950 else if (GET_CODE (insn) == INSN
6951 && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
6952 && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER)
6954 init_insn_group_barriers ();
6957 else if (NONDEBUG_INSN_P (insn))
6959 insns_since_last_label = 1;
6961 if (group_barrier_needed (insn))
6966 fprintf (dump, "Emitting stop before label %d\n",
6967 INSN_UID (last_label));
6968 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), last_label);
6971 init_insn_group_barriers ();
6979 /* Like emit_insn_group_barriers, but run if no final scheduling pass was run.
6980 This function has to emit all necessary group barriers. */
6983 emit_all_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED)
6987 init_insn_group_barriers ();
6989 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6991 if (GET_CODE (insn) == BARRIER)
6993 rtx last = prev_active_insn (insn);
6997 if (GET_CODE (last) == JUMP_INSN
6998 && GET_CODE (PATTERN (last)) == ADDR_DIFF_VEC)
6999 last = prev_active_insn (last);
7000 if (recog_memoized (last) != CODE_FOR_insn_group_barrier)
7001 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last);
7003 init_insn_group_barriers ();
7005 else if (NONDEBUG_INSN_P (insn))
7007 if (recog_memoized (insn) == CODE_FOR_insn_group_barrier)
7008 init_insn_group_barriers ();
7009 else if (group_barrier_needed (insn))
7011 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn);
7012 init_insn_group_barriers ();
7013 group_barrier_needed (insn);
7021 /* Instruction scheduling support. */
7023 #define NR_BUNDLES 10
7025 /* A list of names of all available bundles. */
7027 static const char *bundle_name [NR_BUNDLES] =
7033 #if NR_BUNDLES == 10
7043 /* Nonzero if we should insert stop bits into the schedule. */
7045 int ia64_final_schedule = 0;
7047 /* Codes of the corresponding queried units: */
7049 static int _0mii_, _0mmi_, _0mfi_, _0mmf_;
7050 static int _0bbb_, _0mbb_, _0mib_, _0mmb_, _0mfb_, _0mlx_;
7052 static int _1mii_, _1mmi_, _1mfi_, _1mmf_;
7053 static int _1bbb_, _1mbb_, _1mib_, _1mmb_, _1mfb_, _1mlx_;
7055 static int pos_1, pos_2, pos_3, pos_4, pos_5, pos_6;
7057 /* The following variable value is an insn group barrier. */
7059 static rtx dfa_stop_insn;
7061 /* The following variable value is the last issued insn. */
7063 static rtx last_scheduled_insn;
7065 /* The following variable value is pointer to a DFA state used as
7066 temporary variable. */
7068 static state_t temp_dfa_state = NULL;
7070 /* The following variable value is DFA state after issuing the last
7073 static state_t prev_cycle_state = NULL;
7075 /* The following array element values are TRUE if the corresponding
7076 insn requires to add stop bits before it. */
7078 static char *stops_p = NULL;
7080 /* The following variable is used to set up the mentioned above array. */
7082 static int stop_before_p = 0;
7084 /* The following variable value is length of the arrays `clocks' and
7087 static int clocks_length;
7089 /* The following variable value is number of data speculations in progress. */
7090 static int pending_data_specs = 0;
7092 /* Number of memory references on current and three future processor cycles. */
7093 static char mem_ops_in_group[4];
7095 /* Number of current processor cycle (from scheduler's point of view). */
7096 static int current_cycle;
7098 static rtx ia64_single_set (rtx);
7099 static void ia64_emit_insn_before (rtx, rtx);
7101 /* Map a bundle number to its pseudo-op. */
7104 get_bundle_name (int b)
7106 return bundle_name[b];
7110 /* Return the maximum number of instructions a cpu can issue. */
7113 ia64_issue_rate (void)
7118 /* Helper function - like single_set, but look inside COND_EXEC. */
7121 ia64_single_set (rtx insn)
7123 rtx x = PATTERN (insn), ret;
7124 if (GET_CODE (x) == COND_EXEC)
7125 x = COND_EXEC_CODE (x);
7126 if (GET_CODE (x) == SET)
7129 /* Special case here prologue_allocate_stack and epilogue_deallocate_stack.
7130 Although they are not classical single set, the second set is there just
7131 to protect it from moving past FP-relative stack accesses. */
7132 switch (recog_memoized (insn))
7134 case CODE_FOR_prologue_allocate_stack:
7135 case CODE_FOR_epilogue_deallocate_stack:
7136 ret = XVECEXP (x, 0, 0);
7140 ret = single_set_2 (insn, x);
7147 /* Adjust the cost of a scheduling dependency.
7148 Return the new cost of a dependency of type DEP_TYPE or INSN on DEP_INSN.
7149 COST is the current cost, DW is dependency weakness. */
7151 ia64_adjust_cost_2 (rtx insn, int dep_type1, rtx dep_insn, int cost, dw_t dw)
7153 enum reg_note dep_type = (enum reg_note) dep_type1;
7154 enum attr_itanium_class dep_class;
7155 enum attr_itanium_class insn_class;
7157 insn_class = ia64_safe_itanium_class (insn);
7158 dep_class = ia64_safe_itanium_class (dep_insn);
7160 /* Treat true memory dependencies separately. Ignore apparent true
7161 dependence between store and call (call has a MEM inside a SYMBOL_REF). */
7162 if (dep_type == REG_DEP_TRUE
7163 && (dep_class == ITANIUM_CLASS_ST || dep_class == ITANIUM_CLASS_STF)
7164 && (insn_class == ITANIUM_CLASS_BR || insn_class == ITANIUM_CLASS_SCALL))
7167 if (dw == MIN_DEP_WEAK)
7168 /* Store and load are likely to alias, use higher cost to avoid stall. */
7169 return PARAM_VALUE (PARAM_SCHED_MEM_TRUE_DEP_COST);
7170 else if (dw > MIN_DEP_WEAK)
7172 /* Store and load are less likely to alias. */
7173 if (mflag_sched_fp_mem_deps_zero_cost && dep_class == ITANIUM_CLASS_STF)
7174 /* Assume there will be no cache conflict for floating-point data.
7175 For integer data, L1 conflict penalty is huge (17 cycles), so we
7176 never assume it will not cause a conflict. */
7182 if (dep_type != REG_DEP_OUTPUT)
7185 if (dep_class == ITANIUM_CLASS_ST || dep_class == ITANIUM_CLASS_STF
7186 || insn_class == ITANIUM_CLASS_ST || insn_class == ITANIUM_CLASS_STF)
7192 /* Like emit_insn_before, but skip cycle_display notes.
7193 ??? When cycle display notes are implemented, update this. */
7196 ia64_emit_insn_before (rtx insn, rtx before)
7198 emit_insn_before (insn, before);
7201 /* The following function marks insns who produce addresses for load
7202 and store insns. Such insns will be placed into M slots because it
7203 decrease latency time for Itanium1 (see function
7204 `ia64_produce_address_p' and the DFA descriptions). */
7207 ia64_dependencies_evaluation_hook (rtx head, rtx tail)
7209 rtx insn, next, next_tail;
7211 /* Before reload, which_alternative is not set, which means that
7212 ia64_safe_itanium_class will produce wrong results for (at least)
7213 move instructions. */
7214 if (!reload_completed)
7217 next_tail = NEXT_INSN (tail);
7218 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
7221 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
7223 && ia64_safe_itanium_class (insn) == ITANIUM_CLASS_IALU)
7225 sd_iterator_def sd_it;
7227 bool has_mem_op_consumer_p = false;
7229 FOR_EACH_DEP (insn, SD_LIST_FORW, sd_it, dep)
7231 enum attr_itanium_class c;
7233 if (DEP_TYPE (dep) != REG_DEP_TRUE)
7236 next = DEP_CON (dep);
7237 c = ia64_safe_itanium_class (next);
7238 if ((c == ITANIUM_CLASS_ST
7239 || c == ITANIUM_CLASS_STF)
7240 && ia64_st_address_bypass_p (insn, next))
7242 has_mem_op_consumer_p = true;
7245 else if ((c == ITANIUM_CLASS_LD
7246 || c == ITANIUM_CLASS_FLD
7247 || c == ITANIUM_CLASS_FLDP)
7248 && ia64_ld_address_bypass_p (insn, next))
7250 has_mem_op_consumer_p = true;
7255 insn->call = has_mem_op_consumer_p;
7259 /* We're beginning a new block. Initialize data structures as necessary. */
7262 ia64_sched_init (FILE *dump ATTRIBUTE_UNUSED,
7263 int sched_verbose ATTRIBUTE_UNUSED,
7264 int max_ready ATTRIBUTE_UNUSED)
7266 #ifdef ENABLE_CHECKING
7269 if (!sel_sched_p () && reload_completed)
7270 for (insn = NEXT_INSN (current_sched_info->prev_head);
7271 insn != current_sched_info->next_tail;
7272 insn = NEXT_INSN (insn))
7273 gcc_assert (!SCHED_GROUP_P (insn));
7275 last_scheduled_insn = NULL_RTX;
7276 init_insn_group_barriers ();
7279 memset (mem_ops_in_group, 0, sizeof (mem_ops_in_group));
7282 /* We're beginning a scheduling pass. Check assertion. */
7285 ia64_sched_init_global (FILE *dump ATTRIBUTE_UNUSED,
7286 int sched_verbose ATTRIBUTE_UNUSED,
7287 int max_ready ATTRIBUTE_UNUSED)
7289 gcc_assert (pending_data_specs == 0);
7292 /* Scheduling pass is now finished. Free/reset static variable. */
7294 ia64_sched_finish_global (FILE *dump ATTRIBUTE_UNUSED,
7295 int sched_verbose ATTRIBUTE_UNUSED)
7297 gcc_assert (pending_data_specs == 0);
7300 /* Return TRUE if INSN is a load (either normal or speculative, but not a
7301 speculation check), FALSE otherwise. */
7303 is_load_p (rtx insn)
7305 enum attr_itanium_class insn_class = ia64_safe_itanium_class (insn);
7308 ((insn_class == ITANIUM_CLASS_LD || insn_class == ITANIUM_CLASS_FLD)
7309 && get_attr_check_load (insn) == CHECK_LOAD_NO);
7312 /* If INSN is a memory reference, memoize it in MEM_OPS_IN_GROUP global array
7313 (taking account for 3-cycle cache reference postponing for stores: Intel
7314 Itanium 2 Reference Manual for Software Development and Optimization,
7317 record_memory_reference (rtx insn)
7319 enum attr_itanium_class insn_class = ia64_safe_itanium_class (insn);
7321 switch (insn_class) {
7322 case ITANIUM_CLASS_FLD:
7323 case ITANIUM_CLASS_LD:
7324 mem_ops_in_group[current_cycle % 4]++;
7326 case ITANIUM_CLASS_STF:
7327 case ITANIUM_CLASS_ST:
7328 mem_ops_in_group[(current_cycle + 3) % 4]++;
7334 /* We are about to being issuing insns for this clock cycle.
7335 Override the default sort algorithm to better slot instructions. */
7338 ia64_dfa_sched_reorder (FILE *dump, int sched_verbose, rtx *ready,
7339 int *pn_ready, int clock_var,
7343 int n_ready = *pn_ready;
7344 rtx *e_ready = ready + n_ready;
7348 fprintf (dump, "// ia64_dfa_sched_reorder (type %d):\n", reorder_type);
7350 if (reorder_type == 0)
7352 /* First, move all USEs, CLOBBERs and other crud out of the way. */
7354 for (insnp = ready; insnp < e_ready; insnp++)
7355 if (insnp < e_ready)
7358 enum attr_type t = ia64_safe_type (insn);
7359 if (t == TYPE_UNKNOWN)
7361 if (GET_CODE (PATTERN (insn)) == ASM_INPUT
7362 || asm_noperands (PATTERN (insn)) >= 0)
7364 rtx lowest = ready[n_asms];
7365 ready[n_asms] = insn;
7371 rtx highest = ready[n_ready - 1];
7372 ready[n_ready - 1] = insn;
7379 if (n_asms < n_ready)
7381 /* Some normal insns to process. Skip the asms. */
7385 else if (n_ready > 0)
7389 if (ia64_final_schedule)
7392 int nr_need_stop = 0;
7394 for (insnp = ready; insnp < e_ready; insnp++)
7395 if (safe_group_barrier_needed (*insnp))
7398 if (reorder_type == 1 && n_ready == nr_need_stop)
7400 if (reorder_type == 0)
7403 /* Move down everything that needs a stop bit, preserving
7405 while (insnp-- > ready + deleted)
7406 while (insnp >= ready + deleted)
7409 if (! safe_group_barrier_needed (insn))
7411 memmove (ready + 1, ready, (insnp - ready) * sizeof (rtx));
7419 current_cycle = clock_var;
7420 if (reload_completed && mem_ops_in_group[clock_var % 4] >= ia64_max_memory_insns)
7425 /* Move down loads/stores, preserving relative order. */
7426 while (insnp-- > ready + moved)
7427 while (insnp >= ready + moved)
7430 if (! is_load_p (insn))
7432 memmove (ready + 1, ready, (insnp - ready) * sizeof (rtx));
7443 /* We are about to being issuing insns for this clock cycle. Override
7444 the default sort algorithm to better slot instructions. */
7447 ia64_sched_reorder (FILE *dump, int sched_verbose, rtx *ready, int *pn_ready,
7450 return ia64_dfa_sched_reorder (dump, sched_verbose, ready,
7451 pn_ready, clock_var, 0);
7454 /* Like ia64_sched_reorder, but called after issuing each insn.
7455 Override the default sort algorithm to better slot instructions. */
7458 ia64_sched_reorder2 (FILE *dump ATTRIBUTE_UNUSED,
7459 int sched_verbose ATTRIBUTE_UNUSED, rtx *ready,
7460 int *pn_ready, int clock_var)
7462 return ia64_dfa_sched_reorder (dump, sched_verbose, ready, pn_ready,
7466 /* We are about to issue INSN. Return the number of insns left on the
7467 ready queue that can be issued this cycle. */
7470 ia64_variable_issue (FILE *dump ATTRIBUTE_UNUSED,
7471 int sched_verbose ATTRIBUTE_UNUSED,
7472 rtx insn ATTRIBUTE_UNUSED,
7473 int can_issue_more ATTRIBUTE_UNUSED)
7475 if (sched_deps_info->generate_spec_deps && !sel_sched_p ())
7476 /* Modulo scheduling does not extend h_i_d when emitting
7477 new instructions. Don't use h_i_d, if we don't have to. */
7479 if (DONE_SPEC (insn) & BEGIN_DATA)
7480 pending_data_specs++;
7481 if (CHECK_SPEC (insn) & BEGIN_DATA)
7482 pending_data_specs--;
7485 if (DEBUG_INSN_P (insn))
7488 last_scheduled_insn = insn;
7489 memcpy (prev_cycle_state, curr_state, dfa_state_size);
7490 if (reload_completed)
7492 int needed = group_barrier_needed (insn);
7494 gcc_assert (!needed);
7495 if (GET_CODE (insn) == CALL_INSN)
7496 init_insn_group_barriers ();
7497 stops_p [INSN_UID (insn)] = stop_before_p;
7500 record_memory_reference (insn);
7505 /* We are choosing insn from the ready queue. Return nonzero if INSN
7509 ia64_first_cycle_multipass_dfa_lookahead_guard (rtx insn)
7511 gcc_assert (insn && INSN_P (insn));
7512 return ((!reload_completed
7513 || !safe_group_barrier_needed (insn))
7514 && ia64_first_cycle_multipass_dfa_lookahead_guard_spec (insn)
7515 && (!mflag_sched_mem_insns_hard_limit
7516 || !is_load_p (insn)
7517 || mem_ops_in_group[current_cycle % 4] < ia64_max_memory_insns));
7520 /* We are choosing insn from the ready queue. Return nonzero if INSN
7524 ia64_first_cycle_multipass_dfa_lookahead_guard_spec (const_rtx insn)
7526 gcc_assert (insn && INSN_P (insn));
7527 /* Size of ALAT is 32. As far as we perform conservative data speculation,
7528 we keep ALAT half-empty. */
7529 return (pending_data_specs < 16
7530 || !(TODO_SPEC (insn) & BEGIN_DATA));
7533 /* The following variable value is pseudo-insn used by the DFA insn
7534 scheduler to change the DFA state when the simulated clock is
7537 static rtx dfa_pre_cycle_insn;
7539 /* Returns 1 when a meaningful insn was scheduled between the last group
7540 barrier and LAST. */
7542 scheduled_good_insn (rtx last)
7544 if (last && recog_memoized (last) >= 0)
7548 last != NULL && !NOTE_INSN_BASIC_BLOCK_P (last)
7549 && !stops_p[INSN_UID (last)];
7550 last = PREV_INSN (last))
7551 /* We could hit a NOTE_INSN_DELETED here which is actually outside
7552 the ebb we're scheduling. */
7553 if (INSN_P (last) && recog_memoized (last) >= 0)
7559 /* We are about to being issuing INSN. Return nonzero if we cannot
7560 issue it on given cycle CLOCK and return zero if we should not sort
7561 the ready queue on the next clock start. */
7564 ia64_dfa_new_cycle (FILE *dump, int verbose, rtx insn, int last_clock,
7565 int clock, int *sort_p)
7567 gcc_assert (insn && INSN_P (insn));
7569 if (DEBUG_INSN_P (insn))
7572 /* When a group barrier is needed for insn, last_scheduled_insn
7574 gcc_assert (!(reload_completed && safe_group_barrier_needed (insn))
7575 || last_scheduled_insn);
7577 if ((reload_completed
7578 && (safe_group_barrier_needed (insn)
7579 || (mflag_sched_stop_bits_after_every_cycle
7580 && last_clock != clock
7581 && last_scheduled_insn
7582 && scheduled_good_insn (last_scheduled_insn))))
7583 || (last_scheduled_insn
7584 && (GET_CODE (last_scheduled_insn) == CALL_INSN
7585 || unknown_for_bundling_p (last_scheduled_insn))))
7587 init_insn_group_barriers ();
7589 if (verbose && dump)
7590 fprintf (dump, "// Stop should be before %d%s\n", INSN_UID (insn),
7591 last_clock == clock ? " + cycle advance" : "");
7594 current_cycle = clock;
7595 mem_ops_in_group[current_cycle % 4] = 0;
7597 if (last_clock == clock)
7599 state_transition (curr_state, dfa_stop_insn);
7600 if (TARGET_EARLY_STOP_BITS)
7601 *sort_p = (last_scheduled_insn == NULL_RTX
7602 || GET_CODE (last_scheduled_insn) != CALL_INSN);
7608 if (last_scheduled_insn)
7610 if (unknown_for_bundling_p (last_scheduled_insn))
7611 state_reset (curr_state);
7614 memcpy (curr_state, prev_cycle_state, dfa_state_size);
7615 state_transition (curr_state, dfa_stop_insn);
7616 state_transition (curr_state, dfa_pre_cycle_insn);
7617 state_transition (curr_state, NULL);
7624 /* Implement targetm.sched.h_i_d_extended hook.
7625 Extend internal data structures. */
7627 ia64_h_i_d_extended (void)
7629 if (stops_p != NULL)
7631 int new_clocks_length = get_max_uid () * 3 / 2;
7632 stops_p = (char *) xrecalloc (stops_p, new_clocks_length, clocks_length, 1);
7633 clocks_length = new_clocks_length;
7638 /* This structure describes the data used by the backend to guide scheduling.
7639 When the current scheduling point is switched, this data should be saved
7640 and restored later, if the scheduler returns to this point. */
7641 struct _ia64_sched_context
7643 state_t prev_cycle_state;
7644 rtx last_scheduled_insn;
7645 struct reg_write_state rws_sum[NUM_REGS];
7646 struct reg_write_state rws_insn[NUM_REGS];
7647 int first_instruction;
7648 int pending_data_specs;
7650 char mem_ops_in_group[4];
7652 typedef struct _ia64_sched_context *ia64_sched_context_t;
7654 /* Allocates a scheduling context. */
7656 ia64_alloc_sched_context (void)
7658 return xmalloc (sizeof (struct _ia64_sched_context));
7661 /* Initializes the _SC context with clean data, if CLEAN_P, and from
7662 the global context otherwise. */
7664 ia64_init_sched_context (void *_sc, bool clean_p)
7666 ia64_sched_context_t sc = (ia64_sched_context_t) _sc;
7668 sc->prev_cycle_state = xmalloc (dfa_state_size);
7671 state_reset (sc->prev_cycle_state);
7672 sc->last_scheduled_insn = NULL_RTX;
7673 memset (sc->rws_sum, 0, sizeof (rws_sum));
7674 memset (sc->rws_insn, 0, sizeof (rws_insn));
7675 sc->first_instruction = 1;
7676 sc->pending_data_specs = 0;
7677 sc->current_cycle = 0;
7678 memset (sc->mem_ops_in_group, 0, sizeof (mem_ops_in_group));
7682 memcpy (sc->prev_cycle_state, prev_cycle_state, dfa_state_size);
7683 sc->last_scheduled_insn = last_scheduled_insn;
7684 memcpy (sc->rws_sum, rws_sum, sizeof (rws_sum));
7685 memcpy (sc->rws_insn, rws_insn, sizeof (rws_insn));
7686 sc->first_instruction = first_instruction;
7687 sc->pending_data_specs = pending_data_specs;
7688 sc->current_cycle = current_cycle;
7689 memcpy (sc->mem_ops_in_group, mem_ops_in_group, sizeof (mem_ops_in_group));
7693 /* Sets the global scheduling context to the one pointed to by _SC. */
7695 ia64_set_sched_context (void *_sc)
7697 ia64_sched_context_t sc = (ia64_sched_context_t) _sc;
7699 gcc_assert (sc != NULL);
7701 memcpy (prev_cycle_state, sc->prev_cycle_state, dfa_state_size);
7702 last_scheduled_insn = sc->last_scheduled_insn;
7703 memcpy (rws_sum, sc->rws_sum, sizeof (rws_sum));
7704 memcpy (rws_insn, sc->rws_insn, sizeof (rws_insn));
7705 first_instruction = sc->first_instruction;
7706 pending_data_specs = sc->pending_data_specs;
7707 current_cycle = sc->current_cycle;
7708 memcpy (mem_ops_in_group, sc->mem_ops_in_group, sizeof (mem_ops_in_group));
7711 /* Clears the data in the _SC scheduling context. */
7713 ia64_clear_sched_context (void *_sc)
7715 ia64_sched_context_t sc = (ia64_sched_context_t) _sc;
7717 free (sc->prev_cycle_state);
7718 sc->prev_cycle_state = NULL;
7721 /* Frees the _SC scheduling context. */
7723 ia64_free_sched_context (void *_sc)
7725 gcc_assert (_sc != NULL);
7730 typedef rtx (* gen_func_t) (rtx, rtx);
7732 /* Return a function that will generate a load of mode MODE_NO
7733 with speculation types TS. */
7735 get_spec_load_gen_function (ds_t ts, int mode_no)
7737 static gen_func_t gen_ld_[] = {
7747 gen_zero_extendqidi2,
7748 gen_zero_extendhidi2,
7749 gen_zero_extendsidi2,
7752 static gen_func_t gen_ld_a[] = {
7762 gen_zero_extendqidi2_advanced,
7763 gen_zero_extendhidi2_advanced,
7764 gen_zero_extendsidi2_advanced,
7766 static gen_func_t gen_ld_s[] = {
7767 gen_movbi_speculative,
7768 gen_movqi_speculative,
7769 gen_movhi_speculative,
7770 gen_movsi_speculative,
7771 gen_movdi_speculative,
7772 gen_movsf_speculative,
7773 gen_movdf_speculative,
7774 gen_movxf_speculative,
7775 gen_movti_speculative,
7776 gen_zero_extendqidi2_speculative,
7777 gen_zero_extendhidi2_speculative,
7778 gen_zero_extendsidi2_speculative,
7780 static gen_func_t gen_ld_sa[] = {
7781 gen_movbi_speculative_advanced,
7782 gen_movqi_speculative_advanced,
7783 gen_movhi_speculative_advanced,
7784 gen_movsi_speculative_advanced,
7785 gen_movdi_speculative_advanced,
7786 gen_movsf_speculative_advanced,
7787 gen_movdf_speculative_advanced,
7788 gen_movxf_speculative_advanced,
7789 gen_movti_speculative_advanced,
7790 gen_zero_extendqidi2_speculative_advanced,
7791 gen_zero_extendhidi2_speculative_advanced,
7792 gen_zero_extendsidi2_speculative_advanced,
7794 static gen_func_t gen_ld_s_a[] = {
7795 gen_movbi_speculative_a,
7796 gen_movqi_speculative_a,
7797 gen_movhi_speculative_a,
7798 gen_movsi_speculative_a,
7799 gen_movdi_speculative_a,
7800 gen_movsf_speculative_a,
7801 gen_movdf_speculative_a,
7802 gen_movxf_speculative_a,
7803 gen_movti_speculative_a,
7804 gen_zero_extendqidi2_speculative_a,
7805 gen_zero_extendhidi2_speculative_a,
7806 gen_zero_extendsidi2_speculative_a,
7811 if (ts & BEGIN_DATA)
7813 if (ts & BEGIN_CONTROL)
7818 else if (ts & BEGIN_CONTROL)
7820 if ((spec_info->flags & SEL_SCHED_SPEC_DONT_CHECK_CONTROL)
7821 || ia64_needs_block_p (ts))
7824 gen_ld = gen_ld_s_a;
7831 return gen_ld[mode_no];
7834 /* Constants that help mapping 'enum machine_mode' to int. */
7837 SPEC_MODE_INVALID = -1,
7838 SPEC_MODE_FIRST = 0,
7839 SPEC_MODE_FOR_EXTEND_FIRST = 1,
7840 SPEC_MODE_FOR_EXTEND_LAST = 3,
7846 /* Offset to reach ZERO_EXTEND patterns. */
7847 SPEC_GEN_EXTEND_OFFSET = SPEC_MODE_LAST - SPEC_MODE_FOR_EXTEND_FIRST + 1
7850 /* Return index of the MODE. */
7852 ia64_mode_to_int (enum machine_mode mode)
7856 case BImode: return 0; /* SPEC_MODE_FIRST */
7857 case QImode: return 1; /* SPEC_MODE_FOR_EXTEND_FIRST */
7858 case HImode: return 2;
7859 case SImode: return 3; /* SPEC_MODE_FOR_EXTEND_LAST */
7860 case DImode: return 4;
7861 case SFmode: return 5;
7862 case DFmode: return 6;
7863 case XFmode: return 7;
7865 /* ??? This mode needs testing. Bypasses for ldfp8 instruction are not
7866 mentioned in itanium[12].md. Predicate fp_register_operand also
7867 needs to be defined. Bottom line: better disable for now. */
7868 return SPEC_MODE_INVALID;
7869 default: return SPEC_MODE_INVALID;
7873 /* Provide information about speculation capabilities. */
7875 ia64_set_sched_flags (spec_info_t spec_info)
7877 unsigned int *flags = &(current_sched_info->flags);
7879 if (*flags & SCHED_RGN
7880 || *flags & SCHED_EBB
7881 || *flags & SEL_SCHED)
7885 if ((mflag_sched_br_data_spec && !reload_completed && optimize > 0)
7886 || (mflag_sched_ar_data_spec && reload_completed))
7891 && ((mflag_sched_br_in_data_spec && !reload_completed)
7892 || (mflag_sched_ar_in_data_spec && reload_completed)))
7896 if (mflag_sched_control_spec
7898 || reload_completed))
7900 mask |= BEGIN_CONTROL;
7902 if (!sel_sched_p () && mflag_sched_in_control_spec)
7903 mask |= BE_IN_CONTROL;
7906 spec_info->mask = mask;
7910 *flags |= USE_DEPS_LIST | DO_SPECULATION;
7912 if (mask & BE_IN_SPEC)
7915 spec_info->flags = 0;
7917 if ((mask & DATA_SPEC) && mflag_sched_prefer_non_data_spec_insns)
7918 spec_info->flags |= PREFER_NON_DATA_SPEC;
7920 if (mask & CONTROL_SPEC)
7922 if (mflag_sched_prefer_non_control_spec_insns)
7923 spec_info->flags |= PREFER_NON_CONTROL_SPEC;
7925 if (sel_sched_p () && mflag_sel_sched_dont_check_control_spec)
7926 spec_info->flags |= SEL_SCHED_SPEC_DONT_CHECK_CONTROL;
7929 if (sched_verbose >= 1)
7930 spec_info->dump = sched_dump;
7932 spec_info->dump = 0;
7934 if (mflag_sched_count_spec_in_critical_path)
7935 spec_info->flags |= COUNT_SPEC_IN_CRITICAL_PATH;
7939 spec_info->mask = 0;
7942 /* If INSN is an appropriate load return its mode.
7943 Return -1 otherwise. */
7945 get_mode_no_for_insn (rtx insn)
7947 rtx reg, mem, mode_rtx;
7951 extract_insn_cached (insn);
7953 /* We use WHICH_ALTERNATIVE only after reload. This will
7954 guarantee that reload won't touch a speculative insn. */
7956 if (recog_data.n_operands != 2)
7959 reg = recog_data.operand[0];
7960 mem = recog_data.operand[1];
7962 /* We should use MEM's mode since REG's mode in presence of
7963 ZERO_EXTEND will always be DImode. */
7964 if (get_attr_speculable1 (insn) == SPECULABLE1_YES)
7965 /* Process non-speculative ld. */
7967 if (!reload_completed)
7969 /* Do not speculate into regs like ar.lc. */
7970 if (!REG_P (reg) || AR_REGNO_P (REGNO (reg)))
7977 rtx mem_reg = XEXP (mem, 0);
7979 if (!REG_P (mem_reg))
7985 else if (get_attr_speculable2 (insn) == SPECULABLE2_YES)
7987 gcc_assert (REG_P (reg) && MEM_P (mem));
7993 else if (get_attr_data_speculative (insn) == DATA_SPECULATIVE_YES
7994 || get_attr_control_speculative (insn) == CONTROL_SPECULATIVE_YES
7995 || get_attr_check_load (insn) == CHECK_LOAD_YES)
7996 /* Process speculative ld or ld.c. */
7998 gcc_assert (REG_P (reg) && MEM_P (mem));
8003 enum attr_itanium_class attr_class = get_attr_itanium_class (insn);
8005 if (attr_class == ITANIUM_CLASS_CHK_A
8006 || attr_class == ITANIUM_CLASS_CHK_S_I
8007 || attr_class == ITANIUM_CLASS_CHK_S_F)
8014 mode_no = ia64_mode_to_int (GET_MODE (mode_rtx));
8016 if (mode_no == SPEC_MODE_INVALID)
8019 extend_p = (GET_MODE (reg) != GET_MODE (mode_rtx));
8023 if (!(SPEC_MODE_FOR_EXTEND_FIRST <= mode_no
8024 && mode_no <= SPEC_MODE_FOR_EXTEND_LAST))
8027 mode_no += SPEC_GEN_EXTEND_OFFSET;
8033 /* If X is an unspec part of a speculative load, return its code.
8034 Return -1 otherwise. */
8036 get_spec_unspec_code (const_rtx x)
8038 if (GET_CODE (x) != UNSPEC)
8060 /* Implement skip_rtx_p hook. */
8062 ia64_skip_rtx_p (const_rtx x)
8064 return get_spec_unspec_code (x) != -1;
8067 /* If INSN is a speculative load, return its UNSPEC code.
8068 Return -1 otherwise. */
8070 get_insn_spec_code (const_rtx insn)
8074 pat = PATTERN (insn);
8076 if (GET_CODE (pat) == COND_EXEC)
8077 pat = COND_EXEC_CODE (pat);
8079 if (GET_CODE (pat) != SET)
8082 reg = SET_DEST (pat);
8086 mem = SET_SRC (pat);
8087 if (GET_CODE (mem) == ZERO_EXTEND)
8088 mem = XEXP (mem, 0);
8090 return get_spec_unspec_code (mem);
8093 /* If INSN is a speculative load, return a ds with the speculation types.
8094 Otherwise [if INSN is a normal instruction] return 0. */
8096 ia64_get_insn_spec_ds (rtx insn)
8098 int code = get_insn_spec_code (insn);
8107 return BEGIN_CONTROL;
8110 return BEGIN_DATA | BEGIN_CONTROL;
8117 /* If INSN is a speculative load return a ds with the speculation types that
8119 Otherwise [if INSN is a normal instruction] return 0. */
8121 ia64_get_insn_checked_ds (rtx insn)
8123 int code = get_insn_spec_code (insn);
8128 return BEGIN_DATA | BEGIN_CONTROL;
8131 return BEGIN_CONTROL;
8135 return BEGIN_DATA | BEGIN_CONTROL;
8142 /* If GEN_P is true, calculate the index of needed speculation check and return
8143 speculative pattern for INSN with speculative mode TS, machine mode
8144 MODE_NO and with ZERO_EXTEND (if EXTEND_P is true).
8145 If GEN_P is false, just calculate the index of needed speculation check. */
8147 ia64_gen_spec_load (rtx insn, ds_t ts, int mode_no)
8150 gen_func_t gen_load;
8152 gen_load = get_spec_load_gen_function (ts, mode_no);
8154 new_pat = gen_load (copy_rtx (recog_data.operand[0]),
8155 copy_rtx (recog_data.operand[1]));
8157 pat = PATTERN (insn);
8158 if (GET_CODE (pat) == COND_EXEC)
8159 new_pat = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (COND_EXEC_TEST (pat)),
8166 insn_can_be_in_speculative_p (rtx insn ATTRIBUTE_UNUSED,
8167 ds_t ds ATTRIBUTE_UNUSED)
8172 /* Implement targetm.sched.speculate_insn hook.
8173 Check if the INSN can be TS speculative.
8174 If 'no' - return -1.
8175 If 'yes' - generate speculative pattern in the NEW_PAT and return 1.
8176 If current pattern of the INSN already provides TS speculation,
8179 ia64_speculate_insn (rtx insn, ds_t ts, rtx *new_pat)
8184 gcc_assert (!(ts & ~SPECULATIVE));
8186 if (ia64_spec_check_p (insn))
8189 if ((ts & BE_IN_SPEC)
8190 && !insn_can_be_in_speculative_p (insn, ts))
8193 mode_no = get_mode_no_for_insn (insn);
8195 if (mode_no != SPEC_MODE_INVALID)
8197 if (ia64_get_insn_spec_ds (insn) == ds_get_speculation_types (ts))
8202 *new_pat = ia64_gen_spec_load (insn, ts, mode_no);
8211 /* Return a function that will generate a check for speculation TS with mode
8213 If simple check is needed, pass true for SIMPLE_CHECK_P.
8214 If clearing check is needed, pass true for CLEARING_CHECK_P. */
8216 get_spec_check_gen_function (ds_t ts, int mode_no,
8217 bool simple_check_p, bool clearing_check_p)
8219 static gen_func_t gen_ld_c_clr[] = {
8229 gen_zero_extendqidi2_clr,
8230 gen_zero_extendhidi2_clr,
8231 gen_zero_extendsidi2_clr,
8233 static gen_func_t gen_ld_c_nc[] = {
8243 gen_zero_extendqidi2_nc,
8244 gen_zero_extendhidi2_nc,
8245 gen_zero_extendsidi2_nc,
8247 static gen_func_t gen_chk_a_clr[] = {
8248 gen_advanced_load_check_clr_bi,
8249 gen_advanced_load_check_clr_qi,
8250 gen_advanced_load_check_clr_hi,
8251 gen_advanced_load_check_clr_si,
8252 gen_advanced_load_check_clr_di,
8253 gen_advanced_load_check_clr_sf,
8254 gen_advanced_load_check_clr_df,
8255 gen_advanced_load_check_clr_xf,
8256 gen_advanced_load_check_clr_ti,
8257 gen_advanced_load_check_clr_di,
8258 gen_advanced_load_check_clr_di,
8259 gen_advanced_load_check_clr_di,
8261 static gen_func_t gen_chk_a_nc[] = {
8262 gen_advanced_load_check_nc_bi,
8263 gen_advanced_load_check_nc_qi,
8264 gen_advanced_load_check_nc_hi,
8265 gen_advanced_load_check_nc_si,
8266 gen_advanced_load_check_nc_di,
8267 gen_advanced_load_check_nc_sf,
8268 gen_advanced_load_check_nc_df,
8269 gen_advanced_load_check_nc_xf,
8270 gen_advanced_load_check_nc_ti,
8271 gen_advanced_load_check_nc_di,
8272 gen_advanced_load_check_nc_di,
8273 gen_advanced_load_check_nc_di,
8275 static gen_func_t gen_chk_s[] = {
8276 gen_speculation_check_bi,
8277 gen_speculation_check_qi,
8278 gen_speculation_check_hi,
8279 gen_speculation_check_si,
8280 gen_speculation_check_di,
8281 gen_speculation_check_sf,
8282 gen_speculation_check_df,
8283 gen_speculation_check_xf,
8284 gen_speculation_check_ti,
8285 gen_speculation_check_di,
8286 gen_speculation_check_di,
8287 gen_speculation_check_di,
8290 gen_func_t *gen_check;
8292 if (ts & BEGIN_DATA)
8294 /* We don't need recovery because even if this is ld.sa
8295 ALAT entry will be allocated only if NAT bit is set to zero.
8296 So it is enough to use ld.c here. */
8300 gcc_assert (mflag_sched_spec_ldc);
8302 if (clearing_check_p)
8303 gen_check = gen_ld_c_clr;
8305 gen_check = gen_ld_c_nc;
8309 if (clearing_check_p)
8310 gen_check = gen_chk_a_clr;
8312 gen_check = gen_chk_a_nc;
8315 else if (ts & BEGIN_CONTROL)
8318 /* We might want to use ld.sa -> ld.c instead of
8321 gcc_assert (!ia64_needs_block_p (ts));
8323 if (clearing_check_p)
8324 gen_check = gen_ld_c_clr;
8326 gen_check = gen_ld_c_nc;
8330 gen_check = gen_chk_s;
8336 gcc_assert (mode_no >= 0);
8337 return gen_check[mode_no];
8340 /* Return nonzero, if INSN needs branchy recovery check. */
8342 ia64_needs_block_p (ds_t ts)
8344 if (ts & BEGIN_DATA)
8345 return !mflag_sched_spec_ldc;
8347 gcc_assert ((ts & BEGIN_CONTROL) != 0);
8349 return !(mflag_sched_spec_control_ldc && mflag_sched_spec_ldc);
8352 /* Generate (or regenerate, if (MUTATE_P)) recovery check for INSN.
8353 If (LABEL != 0 || MUTATE_P), generate branchy recovery check.
8354 Otherwise, generate a simple check. */
8356 ia64_gen_spec_check (rtx insn, rtx label, ds_t ds)
8358 rtx op1, pat, check_pat;
8359 gen_func_t gen_check;
8362 mode_no = get_mode_no_for_insn (insn);
8363 gcc_assert (mode_no >= 0);
8369 gcc_assert (!ia64_needs_block_p (ds));
8370 op1 = copy_rtx (recog_data.operand[1]);
8373 gen_check = get_spec_check_gen_function (ds, mode_no, label == NULL_RTX,
8376 check_pat = gen_check (copy_rtx (recog_data.operand[0]), op1);
8378 pat = PATTERN (insn);
8379 if (GET_CODE (pat) == COND_EXEC)
8380 check_pat = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (COND_EXEC_TEST (pat)),
8386 /* Return nonzero, if X is branchy recovery check. */
8388 ia64_spec_check_p (rtx x)
8391 if (GET_CODE (x) == COND_EXEC)
8392 x = COND_EXEC_CODE (x);
8393 if (GET_CODE (x) == SET)
8394 return ia64_spec_check_src_p (SET_SRC (x));
8398 /* Return nonzero, if SRC belongs to recovery check. */
8400 ia64_spec_check_src_p (rtx src)
8402 if (GET_CODE (src) == IF_THEN_ELSE)
8407 if (GET_CODE (t) == NE)
8411 if (GET_CODE (t) == UNSPEC)
8417 if (code == UNSPEC_LDCCLR
8418 || code == UNSPEC_LDCNC
8419 || code == UNSPEC_CHKACLR
8420 || code == UNSPEC_CHKANC
8421 || code == UNSPEC_CHKS)
8423 gcc_assert (code != 0);
8433 /* The following page contains abstract data `bundle states' which are
8434 used for bundling insns (inserting nops and template generation). */
8436 /* The following describes state of insn bundling. */
8440 /* Unique bundle state number to identify them in the debugging
8443 rtx insn; /* corresponding insn, NULL for the 1st and the last state */
8444 /* number nops before and after the insn */
8445 short before_nops_num, after_nops_num;
8446 int insn_num; /* insn number (0 - for initial state, 1 - for the 1st
8448 int cost; /* cost of the state in cycles */
8449 int accumulated_insns_num; /* number of all previous insns including
8450 nops. L is considered as 2 insns */
8451 int branch_deviation; /* deviation of previous branches from 3rd slots */
8452 int middle_bundle_stops; /* number of stop bits in the middle of bundles */
8453 struct bundle_state *next; /* next state with the same insn_num */
8454 struct bundle_state *originator; /* originator (previous insn state) */
8455 /* All bundle states are in the following chain. */
8456 struct bundle_state *allocated_states_chain;
8457 /* The DFA State after issuing the insn and the nops. */
8461 /* The following is map insn number to the corresponding bundle state. */
8463 static struct bundle_state **index_to_bundle_states;
8465 /* The unique number of next bundle state. */
8467 static int bundle_states_num;
8469 /* All allocated bundle states are in the following chain. */
8471 static struct bundle_state *allocated_bundle_states_chain;
8473 /* All allocated but not used bundle states are in the following
8476 static struct bundle_state *free_bundle_state_chain;
8479 /* The following function returns a free bundle state. */
8481 static struct bundle_state *
8482 get_free_bundle_state (void)
8484 struct bundle_state *result;
8486 if (free_bundle_state_chain != NULL)
8488 result = free_bundle_state_chain;
8489 free_bundle_state_chain = result->next;
8493 result = XNEW (struct bundle_state);
8494 result->dfa_state = xmalloc (dfa_state_size);
8495 result->allocated_states_chain = allocated_bundle_states_chain;
8496 allocated_bundle_states_chain = result;
8498 result->unique_num = bundle_states_num++;
8503 /* The following function frees given bundle state. */
8506 free_bundle_state (struct bundle_state *state)
8508 state->next = free_bundle_state_chain;
8509 free_bundle_state_chain = state;
8512 /* Start work with abstract data `bundle states'. */
8515 initiate_bundle_states (void)
8517 bundle_states_num = 0;
8518 free_bundle_state_chain = NULL;
8519 allocated_bundle_states_chain = NULL;
8522 /* Finish work with abstract data `bundle states'. */
8525 finish_bundle_states (void)
8527 struct bundle_state *curr_state, *next_state;
8529 for (curr_state = allocated_bundle_states_chain;
8531 curr_state = next_state)
8533 next_state = curr_state->allocated_states_chain;
8534 free (curr_state->dfa_state);
8539 /* Hash table of the bundle states. The key is dfa_state and insn_num
8540 of the bundle states. */
8542 static htab_t bundle_state_table;
8544 /* The function returns hash of BUNDLE_STATE. */
8547 bundle_state_hash (const void *bundle_state)
8549 const struct bundle_state *const state
8550 = (const struct bundle_state *) bundle_state;
8553 for (result = i = 0; i < dfa_state_size; i++)
8554 result += (((unsigned char *) state->dfa_state) [i]
8555 << ((i % CHAR_BIT) * 3 + CHAR_BIT));
8556 return result + state->insn_num;
8559 /* The function returns nonzero if the bundle state keys are equal. */
8562 bundle_state_eq_p (const void *bundle_state_1, const void *bundle_state_2)
8564 const struct bundle_state *const state1
8565 = (const struct bundle_state *) bundle_state_1;
8566 const struct bundle_state *const state2
8567 = (const struct bundle_state *) bundle_state_2;
8569 return (state1->insn_num == state2->insn_num
8570 && memcmp (state1->dfa_state, state2->dfa_state,
8571 dfa_state_size) == 0);
8574 /* The function inserts the BUNDLE_STATE into the hash table. The
8575 function returns nonzero if the bundle has been inserted into the
8576 table. The table contains the best bundle state with given key. */
8579 insert_bundle_state (struct bundle_state *bundle_state)
8583 entry_ptr = htab_find_slot (bundle_state_table, bundle_state, INSERT);
8584 if (*entry_ptr == NULL)
8586 bundle_state->next = index_to_bundle_states [bundle_state->insn_num];
8587 index_to_bundle_states [bundle_state->insn_num] = bundle_state;
8588 *entry_ptr = (void *) bundle_state;
8591 else if (bundle_state->cost < ((struct bundle_state *) *entry_ptr)->cost
8592 || (bundle_state->cost == ((struct bundle_state *) *entry_ptr)->cost
8593 && (((struct bundle_state *)*entry_ptr)->accumulated_insns_num
8594 > bundle_state->accumulated_insns_num
8595 || (((struct bundle_state *)
8596 *entry_ptr)->accumulated_insns_num
8597 == bundle_state->accumulated_insns_num
8598 && (((struct bundle_state *)
8599 *entry_ptr)->branch_deviation
8600 > bundle_state->branch_deviation
8601 || (((struct bundle_state *)
8602 *entry_ptr)->branch_deviation
8603 == bundle_state->branch_deviation
8604 && ((struct bundle_state *)
8605 *entry_ptr)->middle_bundle_stops
8606 > bundle_state->middle_bundle_stops))))))
8609 struct bundle_state temp;
8611 temp = *(struct bundle_state *) *entry_ptr;
8612 *(struct bundle_state *) *entry_ptr = *bundle_state;
8613 ((struct bundle_state *) *entry_ptr)->next = temp.next;
8614 *bundle_state = temp;
8619 /* Start work with the hash table. */
8622 initiate_bundle_state_table (void)
8624 bundle_state_table = htab_create (50, bundle_state_hash, bundle_state_eq_p,
8628 /* Finish work with the hash table. */
8631 finish_bundle_state_table (void)
8633 htab_delete (bundle_state_table);
8638 /* The following variable is a insn `nop' used to check bundle states
8639 with different number of inserted nops. */
8641 static rtx ia64_nop;
8643 /* The following function tries to issue NOPS_NUM nops for the current
8644 state without advancing processor cycle. If it failed, the
8645 function returns FALSE and frees the current state. */
8648 try_issue_nops (struct bundle_state *curr_state, int nops_num)
8652 for (i = 0; i < nops_num; i++)
8653 if (state_transition (curr_state->dfa_state, ia64_nop) >= 0)
8655 free_bundle_state (curr_state);
8661 /* The following function tries to issue INSN for the current
8662 state without advancing processor cycle. If it failed, the
8663 function returns FALSE and frees the current state. */
8666 try_issue_insn (struct bundle_state *curr_state, rtx insn)
8668 if (insn && state_transition (curr_state->dfa_state, insn) >= 0)
8670 free_bundle_state (curr_state);
8676 /* The following function tries to issue BEFORE_NOPS_NUM nops and INSN
8677 starting with ORIGINATOR without advancing processor cycle. If
8678 TRY_BUNDLE_END_P is TRUE, the function also/only (if
8679 ONLY_BUNDLE_END_P is TRUE) tries to issue nops to fill all bundle.
8680 If it was successful, the function creates new bundle state and
8681 insert into the hash table and into `index_to_bundle_states'. */
8684 issue_nops_and_insn (struct bundle_state *originator, int before_nops_num,
8685 rtx insn, int try_bundle_end_p, int only_bundle_end_p)
8687 struct bundle_state *curr_state;
8689 curr_state = get_free_bundle_state ();
8690 memcpy (curr_state->dfa_state, originator->dfa_state, dfa_state_size);
8691 curr_state->insn = insn;
8692 curr_state->insn_num = originator->insn_num + 1;
8693 curr_state->cost = originator->cost;
8694 curr_state->originator = originator;
8695 curr_state->before_nops_num = before_nops_num;
8696 curr_state->after_nops_num = 0;
8697 curr_state->accumulated_insns_num
8698 = originator->accumulated_insns_num + before_nops_num;
8699 curr_state->branch_deviation = originator->branch_deviation;
8700 curr_state->middle_bundle_stops = originator->middle_bundle_stops;
8702 if (INSN_CODE (insn) == CODE_FOR_insn_group_barrier)
8704 gcc_assert (GET_MODE (insn) != TImode);
8705 if (!try_issue_nops (curr_state, before_nops_num))
8707 if (!try_issue_insn (curr_state, insn))
8709 memcpy (temp_dfa_state, curr_state->dfa_state, dfa_state_size);
8710 if (curr_state->accumulated_insns_num % 3 != 0)
8711 curr_state->middle_bundle_stops++;
8712 if (state_transition (temp_dfa_state, dfa_pre_cycle_insn) >= 0
8713 && curr_state->accumulated_insns_num % 3 != 0)
8715 free_bundle_state (curr_state);
8719 else if (GET_MODE (insn) != TImode)
8721 if (!try_issue_nops (curr_state, before_nops_num))
8723 if (!try_issue_insn (curr_state, insn))
8725 curr_state->accumulated_insns_num++;
8726 gcc_assert (!unknown_for_bundling_p (insn));
8728 if (ia64_safe_type (insn) == TYPE_L)
8729 curr_state->accumulated_insns_num++;
8733 /* If this is an insn that must be first in a group, then don't allow
8734 nops to be emitted before it. Currently, alloc is the only such
8735 supported instruction. */
8736 /* ??? The bundling automatons should handle this for us, but they do
8737 not yet have support for the first_insn attribute. */
8738 if (before_nops_num > 0 && get_attr_first_insn (insn) == FIRST_INSN_YES)
8740 free_bundle_state (curr_state);
8744 state_transition (curr_state->dfa_state, dfa_pre_cycle_insn);
8745 state_transition (curr_state->dfa_state, NULL);
8747 if (!try_issue_nops (curr_state, before_nops_num))
8749 if (!try_issue_insn (curr_state, insn))
8751 curr_state->accumulated_insns_num++;
8752 if (unknown_for_bundling_p (insn))
8754 /* Finish bundle containing asm insn. */
8755 curr_state->after_nops_num
8756 = 3 - curr_state->accumulated_insns_num % 3;
8757 curr_state->accumulated_insns_num
8758 += 3 - curr_state->accumulated_insns_num % 3;
8760 else if (ia64_safe_type (insn) == TYPE_L)
8761 curr_state->accumulated_insns_num++;
8763 if (ia64_safe_type (insn) == TYPE_B)
8764 curr_state->branch_deviation
8765 += 2 - (curr_state->accumulated_insns_num - 1) % 3;
8766 if (try_bundle_end_p && curr_state->accumulated_insns_num % 3 != 0)
8768 if (!only_bundle_end_p && insert_bundle_state (curr_state))
8771 struct bundle_state *curr_state1;
8772 struct bundle_state *allocated_states_chain;
8774 curr_state1 = get_free_bundle_state ();
8775 dfa_state = curr_state1->dfa_state;
8776 allocated_states_chain = curr_state1->allocated_states_chain;
8777 *curr_state1 = *curr_state;
8778 curr_state1->dfa_state = dfa_state;
8779 curr_state1->allocated_states_chain = allocated_states_chain;
8780 memcpy (curr_state1->dfa_state, curr_state->dfa_state,
8782 curr_state = curr_state1;
8784 if (!try_issue_nops (curr_state,
8785 3 - curr_state->accumulated_insns_num % 3))
8787 curr_state->after_nops_num
8788 = 3 - curr_state->accumulated_insns_num % 3;
8789 curr_state->accumulated_insns_num
8790 += 3 - curr_state->accumulated_insns_num % 3;
8792 if (!insert_bundle_state (curr_state))
8793 free_bundle_state (curr_state);
8797 /* The following function returns position in the two window bundle
8801 get_max_pos (state_t state)
8803 if (cpu_unit_reservation_p (state, pos_6))
8805 else if (cpu_unit_reservation_p (state, pos_5))
8807 else if (cpu_unit_reservation_p (state, pos_4))
8809 else if (cpu_unit_reservation_p (state, pos_3))
8811 else if (cpu_unit_reservation_p (state, pos_2))
8813 else if (cpu_unit_reservation_p (state, pos_1))
8819 /* The function returns code of a possible template for given position
8820 and state. The function should be called only with 2 values of
8821 position equal to 3 or 6. We avoid generating F NOPs by putting
8822 templates containing F insns at the end of the template search
8823 because undocumented anomaly in McKinley derived cores which can
8824 cause stalls if an F-unit insn (including a NOP) is issued within a
8825 six-cycle window after reading certain application registers (such
8826 as ar.bsp). Furthermore, power-considerations also argue against
8827 the use of F-unit instructions unless they're really needed. */
8830 get_template (state_t state, int pos)
8835 if (cpu_unit_reservation_p (state, _0mmi_))
8837 else if (cpu_unit_reservation_p (state, _0mii_))
8839 else if (cpu_unit_reservation_p (state, _0mmb_))
8841 else if (cpu_unit_reservation_p (state, _0mib_))
8843 else if (cpu_unit_reservation_p (state, _0mbb_))
8845 else if (cpu_unit_reservation_p (state, _0bbb_))
8847 else if (cpu_unit_reservation_p (state, _0mmf_))
8849 else if (cpu_unit_reservation_p (state, _0mfi_))
8851 else if (cpu_unit_reservation_p (state, _0mfb_))
8853 else if (cpu_unit_reservation_p (state, _0mlx_))
8858 if (cpu_unit_reservation_p (state, _1mmi_))
8860 else if (cpu_unit_reservation_p (state, _1mii_))
8862 else if (cpu_unit_reservation_p (state, _1mmb_))
8864 else if (cpu_unit_reservation_p (state, _1mib_))
8866 else if (cpu_unit_reservation_p (state, _1mbb_))
8868 else if (cpu_unit_reservation_p (state, _1bbb_))
8870 else if (_1mmf_ >= 0 && cpu_unit_reservation_p (state, _1mmf_))
8872 else if (cpu_unit_reservation_p (state, _1mfi_))
8874 else if (cpu_unit_reservation_p (state, _1mfb_))
8876 else if (cpu_unit_reservation_p (state, _1mlx_))
8885 /* True when INSN is important for bundling. */
8888 important_for_bundling_p (rtx insn)
8890 return (INSN_P (insn)
8891 && ia64_safe_itanium_class (insn) != ITANIUM_CLASS_IGNORE
8892 && GET_CODE (PATTERN (insn)) != USE
8893 && GET_CODE (PATTERN (insn)) != CLOBBER);
8896 /* The following function returns an insn important for insn bundling
8897 followed by INSN and before TAIL. */
8900 get_next_important_insn (rtx insn, rtx tail)
8902 for (; insn && insn != tail; insn = NEXT_INSN (insn))
8903 if (important_for_bundling_p (insn))
8908 /* True when INSN is unknown, but important, for bundling. */
8911 unknown_for_bundling_p (rtx insn)
8913 return (INSN_P (insn)
8914 && ia64_safe_itanium_class (insn) == ITANIUM_CLASS_UNKNOWN
8915 && GET_CODE (PATTERN (insn)) != USE
8916 && GET_CODE (PATTERN (insn)) != CLOBBER);
8919 /* Add a bundle selector TEMPLATE0 before INSN. */
8922 ia64_add_bundle_selector_before (int template0, rtx insn)
8924 rtx b = gen_bundle_selector (GEN_INT (template0));
8926 ia64_emit_insn_before (b, insn);
8927 #if NR_BUNDLES == 10
8928 if ((template0 == 4 || template0 == 5)
8929 && ia64_except_unwind_info (&global_options) == UI_TARGET)
8932 rtx note = NULL_RTX;
8934 /* In .mbb and .bbb bundles, check if CALL_INSN isn't in the
8935 first or second slot. If it is and has REG_EH_NOTE set, copy it
8936 to following nops, as br.call sets rp to the address of following
8937 bundle and therefore an EH region end must be on a bundle
8939 insn = PREV_INSN (insn);
8940 for (i = 0; i < 3; i++)
8943 insn = next_active_insn (insn);
8944 while (GET_CODE (insn) == INSN
8945 && get_attr_empty (insn) == EMPTY_YES);
8946 if (GET_CODE (insn) == CALL_INSN)
8947 note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8952 gcc_assert ((code = recog_memoized (insn)) == CODE_FOR_nop
8953 || code == CODE_FOR_nop_b);
8954 if (find_reg_note (insn, REG_EH_REGION, NULL_RTX))
8957 add_reg_note (insn, REG_EH_REGION, XEXP (note, 0));
8964 /* The following function does insn bundling. Bundling means
8965 inserting templates and nop insns to fit insn groups into permitted
8966 templates. Instruction scheduling uses NDFA (non-deterministic
8967 finite automata) encoding informations about the templates and the
8968 inserted nops. Nondeterminism of the automata permits follows
8969 all possible insn sequences very fast.
8971 Unfortunately it is not possible to get information about inserting
8972 nop insns and used templates from the automata states. The
8973 automata only says that we can issue an insn possibly inserting
8974 some nops before it and using some template. Therefore insn
8975 bundling in this function is implemented by using DFA
8976 (deterministic finite automata). We follow all possible insn
8977 sequences by inserting 0-2 nops (that is what the NDFA describe for
8978 insn scheduling) before/after each insn being bundled. We know the
8979 start of simulated processor cycle from insn scheduling (insn
8980 starting a new cycle has TImode).
8982 Simple implementation of insn bundling would create enormous
8983 number of possible insn sequences satisfying information about new
8984 cycle ticks taken from the insn scheduling. To make the algorithm
8985 practical we use dynamic programming. Each decision (about
8986 inserting nops and implicitly about previous decisions) is described
8987 by structure bundle_state (see above). If we generate the same
8988 bundle state (key is automaton state after issuing the insns and
8989 nops for it), we reuse already generated one. As consequence we
8990 reject some decisions which cannot improve the solution and
8991 reduce memory for the algorithm.
8993 When we reach the end of EBB (extended basic block), we choose the
8994 best sequence and then, moving back in EBB, insert templates for
8995 the best alternative. The templates are taken from querying
8996 automaton state for each insn in chosen bundle states.
8998 So the algorithm makes two (forward and backward) passes through
9002 bundling (FILE *dump, int verbose, rtx prev_head_insn, rtx tail)
9004 struct bundle_state *curr_state, *next_state, *best_state;
9005 rtx insn, next_insn;
9007 int i, bundle_end_p, only_bundle_end_p, asm_p;
9008 int pos = 0, max_pos, template0, template1;
9011 enum attr_type type;
9014 /* Count insns in the EBB. */
9015 for (insn = NEXT_INSN (prev_head_insn);
9016 insn && insn != tail;
9017 insn = NEXT_INSN (insn))
9023 dfa_clean_insn_cache ();
9024 initiate_bundle_state_table ();
9025 index_to_bundle_states = XNEWVEC (struct bundle_state *, insn_num + 2);
9026 /* First (forward) pass -- generation of bundle states. */
9027 curr_state = get_free_bundle_state ();
9028 curr_state->insn = NULL;
9029 curr_state->before_nops_num = 0;
9030 curr_state->after_nops_num = 0;
9031 curr_state->insn_num = 0;
9032 curr_state->cost = 0;
9033 curr_state->accumulated_insns_num = 0;
9034 curr_state->branch_deviation = 0;
9035 curr_state->middle_bundle_stops = 0;
9036 curr_state->next = NULL;
9037 curr_state->originator = NULL;
9038 state_reset (curr_state->dfa_state);
9039 index_to_bundle_states [0] = curr_state;
9041 /* Shift cycle mark if it is put on insn which could be ignored. */
9042 for (insn = NEXT_INSN (prev_head_insn);
9044 insn = NEXT_INSN (insn))
9046 && !important_for_bundling_p (insn)
9047 && GET_MODE (insn) == TImode)
9049 PUT_MODE (insn, VOIDmode);
9050 for (next_insn = NEXT_INSN (insn);
9052 next_insn = NEXT_INSN (next_insn))
9053 if (important_for_bundling_p (next_insn)
9054 && INSN_CODE (next_insn) != CODE_FOR_insn_group_barrier)
9056 PUT_MODE (next_insn, TImode);
9060 /* Forward pass: generation of bundle states. */
9061 for (insn = get_next_important_insn (NEXT_INSN (prev_head_insn), tail);
9065 gcc_assert (important_for_bundling_p (insn));
9066 type = ia64_safe_type (insn);
9067 next_insn = get_next_important_insn (NEXT_INSN (insn), tail);
9069 index_to_bundle_states [insn_num] = NULL;
9070 for (curr_state = index_to_bundle_states [insn_num - 1];
9072 curr_state = next_state)
9074 pos = curr_state->accumulated_insns_num % 3;
9075 next_state = curr_state->next;
9076 /* We must fill up the current bundle in order to start a
9077 subsequent asm insn in a new bundle. Asm insn is always
9078 placed in a separate bundle. */
9080 = (next_insn != NULL_RTX
9081 && INSN_CODE (insn) == CODE_FOR_insn_group_barrier
9082 && unknown_for_bundling_p (next_insn));
9083 /* We may fill up the current bundle if it is the cycle end
9084 without a group barrier. */
9086 = (only_bundle_end_p || next_insn == NULL_RTX
9087 || (GET_MODE (next_insn) == TImode
9088 && INSN_CODE (insn) != CODE_FOR_insn_group_barrier));
9089 if (type == TYPE_F || type == TYPE_B || type == TYPE_L
9091 issue_nops_and_insn (curr_state, 2, insn, bundle_end_p,
9093 issue_nops_and_insn (curr_state, 1, insn, bundle_end_p,
9095 issue_nops_and_insn (curr_state, 0, insn, bundle_end_p,
9098 gcc_assert (index_to_bundle_states [insn_num]);
9099 for (curr_state = index_to_bundle_states [insn_num];
9101 curr_state = curr_state->next)
9102 if (verbose >= 2 && dump)
9104 /* This structure is taken from generated code of the
9105 pipeline hazard recognizer (see file insn-attrtab.c).
9106 Please don't forget to change the structure if a new
9107 automaton is added to .md file. */
9110 unsigned short one_automaton_state;
9111 unsigned short oneb_automaton_state;
9112 unsigned short two_automaton_state;
9113 unsigned short twob_automaton_state;
9118 "// Bundle state %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, mid.stops %d state %d) for %d\n",
9119 curr_state->unique_num,
9120 (curr_state->originator == NULL
9121 ? -1 : curr_state->originator->unique_num),
9123 curr_state->before_nops_num, curr_state->after_nops_num,
9124 curr_state->accumulated_insns_num, curr_state->branch_deviation,
9125 curr_state->middle_bundle_stops,
9126 ((struct DFA_chip *) curr_state->dfa_state)->twob_automaton_state,
9131 /* We should find a solution because the 2nd insn scheduling has
9133 gcc_assert (index_to_bundle_states [insn_num]);
9134 /* Find a state corresponding to the best insn sequence. */
9136 for (curr_state = index_to_bundle_states [insn_num];
9138 curr_state = curr_state->next)
9139 /* We are just looking at the states with fully filled up last
9140 bundle. The first we prefer insn sequences with minimal cost
9141 then with minimal inserted nops and finally with branch insns
9142 placed in the 3rd slots. */
9143 if (curr_state->accumulated_insns_num % 3 == 0
9144 && (best_state == NULL || best_state->cost > curr_state->cost
9145 || (best_state->cost == curr_state->cost
9146 && (curr_state->accumulated_insns_num
9147 < best_state->accumulated_insns_num
9148 || (curr_state->accumulated_insns_num
9149 == best_state->accumulated_insns_num
9150 && (curr_state->branch_deviation
9151 < best_state->branch_deviation
9152 || (curr_state->branch_deviation
9153 == best_state->branch_deviation
9154 && curr_state->middle_bundle_stops
9155 < best_state->middle_bundle_stops)))))))
9156 best_state = curr_state;
9157 /* Second (backward) pass: adding nops and templates. */
9158 gcc_assert (best_state);
9159 insn_num = best_state->before_nops_num;
9160 template0 = template1 = -1;
9161 for (curr_state = best_state;
9162 curr_state->originator != NULL;
9163 curr_state = curr_state->originator)
9165 insn = curr_state->insn;
9166 asm_p = unknown_for_bundling_p (insn);
9168 if (verbose >= 2 && dump)
9172 unsigned short one_automaton_state;
9173 unsigned short oneb_automaton_state;
9174 unsigned short two_automaton_state;
9175 unsigned short twob_automaton_state;
9180 "// Best %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, mid.stops %d, state %d) for %d\n",
9181 curr_state->unique_num,
9182 (curr_state->originator == NULL
9183 ? -1 : curr_state->originator->unique_num),
9185 curr_state->before_nops_num, curr_state->after_nops_num,
9186 curr_state->accumulated_insns_num, curr_state->branch_deviation,
9187 curr_state->middle_bundle_stops,
9188 ((struct DFA_chip *) curr_state->dfa_state)->twob_automaton_state,
9191 /* Find the position in the current bundle window. The window can
9192 contain at most two bundles. Two bundle window means that
9193 the processor will make two bundle rotation. */
9194 max_pos = get_max_pos (curr_state->dfa_state);
9196 /* The following (negative template number) means that the
9197 processor did one bundle rotation. */
9198 || (max_pos == 3 && template0 < 0))
9200 /* We are at the end of the window -- find template(s) for
9204 template0 = get_template (curr_state->dfa_state, 3);
9207 template1 = get_template (curr_state->dfa_state, 3);
9208 template0 = get_template (curr_state->dfa_state, 6);
9211 if (max_pos > 3 && template1 < 0)
9212 /* It may happen when we have the stop inside a bundle. */
9214 gcc_assert (pos <= 3);
9215 template1 = get_template (curr_state->dfa_state, 3);
9219 /* Emit nops after the current insn. */
9220 for (i = 0; i < curr_state->after_nops_num; i++)
9223 emit_insn_after (nop, insn);
9225 gcc_assert (pos >= 0);
9228 /* We are at the start of a bundle: emit the template
9229 (it should be defined). */
9230 gcc_assert (template0 >= 0);
9231 ia64_add_bundle_selector_before (template0, nop);
9232 /* If we have two bundle window, we make one bundle
9233 rotation. Otherwise template0 will be undefined
9234 (negative value). */
9235 template0 = template1;
9239 /* Move the position backward in the window. Group barrier has
9240 no slot. Asm insn takes all bundle. */
9241 if (INSN_CODE (insn) != CODE_FOR_insn_group_barrier
9242 && !unknown_for_bundling_p (insn))
9244 /* Long insn takes 2 slots. */
9245 if (ia64_safe_type (insn) == TYPE_L)
9247 gcc_assert (pos >= 0);
9249 && INSN_CODE (insn) != CODE_FOR_insn_group_barrier
9250 && !unknown_for_bundling_p (insn))
9252 /* The current insn is at the bundle start: emit the
9254 gcc_assert (template0 >= 0);
9255 ia64_add_bundle_selector_before (template0, insn);
9256 b = PREV_INSN (insn);
9258 /* See comment above in analogous place for emitting nops
9260 template0 = template1;
9263 /* Emit nops after the current insn. */
9264 for (i = 0; i < curr_state->before_nops_num; i++)
9267 ia64_emit_insn_before (nop, insn);
9268 nop = PREV_INSN (insn);
9271 gcc_assert (pos >= 0);
9274 /* See comment above in analogous place for emitting nops
9276 gcc_assert (template0 >= 0);
9277 ia64_add_bundle_selector_before (template0, insn);
9278 b = PREV_INSN (insn);
9280 template0 = template1;
9286 #ifdef ENABLE_CHECKING
9288 /* Assert right calculation of middle_bundle_stops. */
9289 int num = best_state->middle_bundle_stops;
9290 bool start_bundle = true, end_bundle = false;
9292 for (insn = NEXT_INSN (prev_head_insn);
9293 insn && insn != tail;
9294 insn = NEXT_INSN (insn))
9298 if (recog_memoized (insn) == CODE_FOR_bundle_selector)
9299 start_bundle = true;
9304 for (next_insn = NEXT_INSN (insn);
9305 next_insn && next_insn != tail;
9306 next_insn = NEXT_INSN (next_insn))
9307 if (INSN_P (next_insn)
9308 && (ia64_safe_itanium_class (next_insn)
9309 != ITANIUM_CLASS_IGNORE
9310 || recog_memoized (next_insn)
9311 == CODE_FOR_bundle_selector)
9312 && GET_CODE (PATTERN (next_insn)) != USE
9313 && GET_CODE (PATTERN (next_insn)) != CLOBBER)
9316 end_bundle = next_insn == NULL_RTX
9317 || next_insn == tail
9318 || (INSN_P (next_insn)
9319 && recog_memoized (next_insn)
9320 == CODE_FOR_bundle_selector);
9321 if (recog_memoized (insn) == CODE_FOR_insn_group_barrier
9322 && !start_bundle && !end_bundle
9324 && !unknown_for_bundling_p (next_insn))
9327 start_bundle = false;
9331 gcc_assert (num == 0);
9335 free (index_to_bundle_states);
9336 finish_bundle_state_table ();
9338 dfa_clean_insn_cache ();
9341 /* The following function is called at the end of scheduling BB or
9342 EBB. After reload, it inserts stop bits and does insn bundling. */
9345 ia64_sched_finish (FILE *dump, int sched_verbose)
9348 fprintf (dump, "// Finishing schedule.\n");
9349 if (!reload_completed)
9351 if (reload_completed)
9353 final_emit_insn_group_barriers (dump);
9354 bundling (dump, sched_verbose, current_sched_info->prev_head,
9355 current_sched_info->next_tail);
9356 if (sched_verbose && dump)
9357 fprintf (dump, "// finishing %d-%d\n",
9358 INSN_UID (NEXT_INSN (current_sched_info->prev_head)),
9359 INSN_UID (PREV_INSN (current_sched_info->next_tail)));
9365 /* The following function inserts stop bits in scheduled BB or EBB. */
9368 final_emit_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED)
9371 int need_barrier_p = 0;
9372 int seen_good_insn = 0;
9374 init_insn_group_barriers ();
9376 for (insn = NEXT_INSN (current_sched_info->prev_head);
9377 insn != current_sched_info->next_tail;
9378 insn = NEXT_INSN (insn))
9380 if (GET_CODE (insn) == BARRIER)
9382 rtx last = prev_active_insn (insn);
9386 if (GET_CODE (last) == JUMP_INSN
9387 && GET_CODE (PATTERN (last)) == ADDR_DIFF_VEC)
9388 last = prev_active_insn (last);
9389 if (recog_memoized (last) != CODE_FOR_insn_group_barrier)
9390 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last);
9392 init_insn_group_barriers ();
9396 else if (NONDEBUG_INSN_P (insn))
9398 if (recog_memoized (insn) == CODE_FOR_insn_group_barrier)
9400 init_insn_group_barriers ();
9404 else if (need_barrier_p || group_barrier_needed (insn)
9405 || (mflag_sched_stop_bits_after_every_cycle
9406 && GET_MODE (insn) == TImode
9409 if (TARGET_EARLY_STOP_BITS)
9414 last != current_sched_info->prev_head;
9415 last = PREV_INSN (last))
9416 if (INSN_P (last) && GET_MODE (last) == TImode
9417 && stops_p [INSN_UID (last)])
9419 if (last == current_sched_info->prev_head)
9421 last = prev_active_insn (last);
9423 && recog_memoized (last) != CODE_FOR_insn_group_barrier)
9424 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)),
9426 init_insn_group_barriers ();
9427 for (last = NEXT_INSN (last);
9429 last = NEXT_INSN (last))
9432 group_barrier_needed (last);
9433 if (recog_memoized (last) >= 0
9434 && important_for_bundling_p (last))
9440 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
9442 init_insn_group_barriers ();
9445 group_barrier_needed (insn);
9446 if (recog_memoized (insn) >= 0
9447 && important_for_bundling_p (insn))
9450 else if (recog_memoized (insn) >= 0
9451 && important_for_bundling_p (insn))
9453 need_barrier_p = (GET_CODE (insn) == CALL_INSN
9454 || unknown_for_bundling_p (insn));
9461 /* If the following function returns TRUE, we will use the DFA
9465 ia64_first_cycle_multipass_dfa_lookahead (void)
9467 return (reload_completed ? 6 : 4);
9470 /* The following function initiates variable `dfa_pre_cycle_insn'. */
9473 ia64_init_dfa_pre_cycle_insn (void)
9475 if (temp_dfa_state == NULL)
9477 dfa_state_size = state_size ();
9478 temp_dfa_state = xmalloc (dfa_state_size);
9479 prev_cycle_state = xmalloc (dfa_state_size);
9481 dfa_pre_cycle_insn = make_insn_raw (gen_pre_cycle ());
9482 PREV_INSN (dfa_pre_cycle_insn) = NEXT_INSN (dfa_pre_cycle_insn) = NULL_RTX;
9483 recog_memoized (dfa_pre_cycle_insn);
9484 dfa_stop_insn = make_insn_raw (gen_insn_group_barrier (GEN_INT (3)));
9485 PREV_INSN (dfa_stop_insn) = NEXT_INSN (dfa_stop_insn) = NULL_RTX;
9486 recog_memoized (dfa_stop_insn);
9489 /* The following function returns the pseudo insn DFA_PRE_CYCLE_INSN
9490 used by the DFA insn scheduler. */
9493 ia64_dfa_pre_cycle_insn (void)
9495 return dfa_pre_cycle_insn;
9498 /* The following function returns TRUE if PRODUCER (of type ilog or
9499 ld) produces address for CONSUMER (of type st or stf). */
9502 ia64_st_address_bypass_p (rtx producer, rtx consumer)
9506 gcc_assert (producer && consumer);
9507 dest = ia64_single_set (producer);
9509 reg = SET_DEST (dest);
9511 if (GET_CODE (reg) == SUBREG)
9512 reg = SUBREG_REG (reg);
9513 gcc_assert (GET_CODE (reg) == REG);
9515 dest = ia64_single_set (consumer);
9517 mem = SET_DEST (dest);
9518 gcc_assert (mem && GET_CODE (mem) == MEM);
9519 return reg_mentioned_p (reg, mem);
9522 /* The following function returns TRUE if PRODUCER (of type ilog or
9523 ld) produces address for CONSUMER (of type ld or fld). */
9526 ia64_ld_address_bypass_p (rtx producer, rtx consumer)
9528 rtx dest, src, reg, mem;
9530 gcc_assert (producer && consumer);
9531 dest = ia64_single_set (producer);
9533 reg = SET_DEST (dest);
9535 if (GET_CODE (reg) == SUBREG)
9536 reg = SUBREG_REG (reg);
9537 gcc_assert (GET_CODE (reg) == REG);
9539 src = ia64_single_set (consumer);
9541 mem = SET_SRC (src);
9544 if (GET_CODE (mem) == UNSPEC && XVECLEN (mem, 0) > 0)
9545 mem = XVECEXP (mem, 0, 0);
9546 else if (GET_CODE (mem) == IF_THEN_ELSE)
9547 /* ??? Is this bypass necessary for ld.c? */
9549 gcc_assert (XINT (XEXP (XEXP (mem, 0), 0), 1) == UNSPEC_LDCCLR);
9550 mem = XEXP (mem, 1);
9553 while (GET_CODE (mem) == SUBREG || GET_CODE (mem) == ZERO_EXTEND)
9554 mem = XEXP (mem, 0);
9556 if (GET_CODE (mem) == UNSPEC)
9558 int c = XINT (mem, 1);
9560 gcc_assert (c == UNSPEC_LDA || c == UNSPEC_LDS || c == UNSPEC_LDS_A
9561 || c == UNSPEC_LDSA);
9562 mem = XVECEXP (mem, 0, 0);
9565 /* Note that LO_SUM is used for GOT loads. */
9566 gcc_assert (GET_CODE (mem) == LO_SUM || GET_CODE (mem) == MEM);
9568 return reg_mentioned_p (reg, mem);
9571 /* The following function returns TRUE if INSN produces address for a
9572 load/store insn. We will place such insns into M slot because it
9573 decreases its latency time. */
9576 ia64_produce_address_p (rtx insn)
9582 /* Emit pseudo-ops for the assembler to describe predicate relations.
9583 At present this assumes that we only consider predicate pairs to
9584 be mutex, and that the assembler can deduce proper values from
9585 straight-line code. */
9588 emit_predicate_relation_info (void)
9592 FOR_EACH_BB_REVERSE (bb)
9595 rtx head = BB_HEAD (bb);
9597 /* We only need such notes at code labels. */
9598 if (GET_CODE (head) != CODE_LABEL)
9600 if (NOTE_INSN_BASIC_BLOCK_P (NEXT_INSN (head)))
9601 head = NEXT_INSN (head);
9603 /* Skip p0, which may be thought to be live due to (reg:DI p0)
9604 grabbing the entire block of predicate registers. */
9605 for (r = PR_REG (2); r < PR_REG (64); r += 2)
9606 if (REGNO_REG_SET_P (df_get_live_in (bb), r))
9608 rtx p = gen_rtx_REG (BImode, r);
9609 rtx n = emit_insn_after (gen_pred_rel_mutex (p), head);
9610 if (head == BB_END (bb))
9616 /* Look for conditional calls that do not return, and protect predicate
9617 relations around them. Otherwise the assembler will assume the call
9618 returns, and complain about uses of call-clobbered predicates after
9620 FOR_EACH_BB_REVERSE (bb)
9622 rtx insn = BB_HEAD (bb);
9626 if (GET_CODE (insn) == CALL_INSN
9627 && GET_CODE (PATTERN (insn)) == COND_EXEC
9628 && find_reg_note (insn, REG_NORETURN, NULL_RTX))
9630 rtx b = emit_insn_before (gen_safe_across_calls_all (), insn);
9631 rtx a = emit_insn_after (gen_safe_across_calls_normal (), insn);
9632 if (BB_HEAD (bb) == insn)
9634 if (BB_END (bb) == insn)
9638 if (insn == BB_END (bb))
9640 insn = NEXT_INSN (insn);
9645 /* Perform machine dependent operations on the rtl chain INSNS. */
9650 /* We are freeing block_for_insn in the toplev to keep compatibility
9651 with old MDEP_REORGS that are not CFG based. Recompute it now. */
9652 compute_bb_for_insn ();
9654 /* If optimizing, we'll have split before scheduling. */
9658 if (optimize && flag_schedule_insns_after_reload
9659 && dbg_cnt (ia64_sched2))
9662 timevar_push (TV_SCHED2);
9663 ia64_final_schedule = 1;
9665 /* We can't let modulo-sched prevent us from scheduling any bbs,
9666 since we need the final schedule to produce bundle information. */
9668 bb->flags &= ~BB_DISABLE_SCHEDULE;
9670 initiate_bundle_states ();
9671 ia64_nop = make_insn_raw (gen_nop ());
9672 PREV_INSN (ia64_nop) = NEXT_INSN (ia64_nop) = NULL_RTX;
9673 recog_memoized (ia64_nop);
9674 clocks_length = get_max_uid () + 1;
9675 stops_p = XCNEWVEC (char, clocks_length);
9677 if (ia64_tune == PROCESSOR_ITANIUM2)
9679 pos_1 = get_cpu_unit_code ("2_1");
9680 pos_2 = get_cpu_unit_code ("2_2");
9681 pos_3 = get_cpu_unit_code ("2_3");
9682 pos_4 = get_cpu_unit_code ("2_4");
9683 pos_5 = get_cpu_unit_code ("2_5");
9684 pos_6 = get_cpu_unit_code ("2_6");
9685 _0mii_ = get_cpu_unit_code ("2b_0mii.");
9686 _0mmi_ = get_cpu_unit_code ("2b_0mmi.");
9687 _0mfi_ = get_cpu_unit_code ("2b_0mfi.");
9688 _0mmf_ = get_cpu_unit_code ("2b_0mmf.");
9689 _0bbb_ = get_cpu_unit_code ("2b_0bbb.");
9690 _0mbb_ = get_cpu_unit_code ("2b_0mbb.");
9691 _0mib_ = get_cpu_unit_code ("2b_0mib.");
9692 _0mmb_ = get_cpu_unit_code ("2b_0mmb.");
9693 _0mfb_ = get_cpu_unit_code ("2b_0mfb.");
9694 _0mlx_ = get_cpu_unit_code ("2b_0mlx.");
9695 _1mii_ = get_cpu_unit_code ("2b_1mii.");
9696 _1mmi_ = get_cpu_unit_code ("2b_1mmi.");
9697 _1mfi_ = get_cpu_unit_code ("2b_1mfi.");
9698 _1mmf_ = get_cpu_unit_code ("2b_1mmf.");
9699 _1bbb_ = get_cpu_unit_code ("2b_1bbb.");
9700 _1mbb_ = get_cpu_unit_code ("2b_1mbb.");
9701 _1mib_ = get_cpu_unit_code ("2b_1mib.");
9702 _1mmb_ = get_cpu_unit_code ("2b_1mmb.");
9703 _1mfb_ = get_cpu_unit_code ("2b_1mfb.");
9704 _1mlx_ = get_cpu_unit_code ("2b_1mlx.");
9708 pos_1 = get_cpu_unit_code ("1_1");
9709 pos_2 = get_cpu_unit_code ("1_2");
9710 pos_3 = get_cpu_unit_code ("1_3");
9711 pos_4 = get_cpu_unit_code ("1_4");
9712 pos_5 = get_cpu_unit_code ("1_5");
9713 pos_6 = get_cpu_unit_code ("1_6");
9714 _0mii_ = get_cpu_unit_code ("1b_0mii.");
9715 _0mmi_ = get_cpu_unit_code ("1b_0mmi.");
9716 _0mfi_ = get_cpu_unit_code ("1b_0mfi.");
9717 _0mmf_ = get_cpu_unit_code ("1b_0mmf.");
9718 _0bbb_ = get_cpu_unit_code ("1b_0bbb.");
9719 _0mbb_ = get_cpu_unit_code ("1b_0mbb.");
9720 _0mib_ = get_cpu_unit_code ("1b_0mib.");
9721 _0mmb_ = get_cpu_unit_code ("1b_0mmb.");
9722 _0mfb_ = get_cpu_unit_code ("1b_0mfb.");
9723 _0mlx_ = get_cpu_unit_code ("1b_0mlx.");
9724 _1mii_ = get_cpu_unit_code ("1b_1mii.");
9725 _1mmi_ = get_cpu_unit_code ("1b_1mmi.");
9726 _1mfi_ = get_cpu_unit_code ("1b_1mfi.");
9727 _1mmf_ = get_cpu_unit_code ("1b_1mmf.");
9728 _1bbb_ = get_cpu_unit_code ("1b_1bbb.");
9729 _1mbb_ = get_cpu_unit_code ("1b_1mbb.");
9730 _1mib_ = get_cpu_unit_code ("1b_1mib.");
9731 _1mmb_ = get_cpu_unit_code ("1b_1mmb.");
9732 _1mfb_ = get_cpu_unit_code ("1b_1mfb.");
9733 _1mlx_ = get_cpu_unit_code ("1b_1mlx.");
9736 if (flag_selective_scheduling2
9737 && !maybe_skip_selective_scheduling ())
9738 run_selective_scheduling ();
9742 /* Redo alignment computation, as it might gone wrong. */
9743 compute_alignments ();
9745 /* We cannot reuse this one because it has been corrupted by the
9747 finish_bundle_states ();
9750 emit_insn_group_barriers (dump_file);
9752 ia64_final_schedule = 0;
9753 timevar_pop (TV_SCHED2);
9756 emit_all_insn_group_barriers (dump_file);
9760 /* A call must not be the last instruction in a function, so that the
9761 return address is still within the function, so that unwinding works
9762 properly. Note that IA-64 differs from dwarf2 on this point. */
9763 if (ia64_except_unwind_info (&global_options) == UI_TARGET)
9768 insn = get_last_insn ();
9769 if (! INSN_P (insn))
9770 insn = prev_active_insn (insn);
9773 /* Skip over insns that expand to nothing. */
9774 while (GET_CODE (insn) == INSN
9775 && get_attr_empty (insn) == EMPTY_YES)
9777 if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
9778 && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER)
9780 insn = prev_active_insn (insn);
9782 if (GET_CODE (insn) == CALL_INSN)
9785 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
9786 emit_insn (gen_break_f ());
9787 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
9792 emit_predicate_relation_info ();
9794 if (flag_var_tracking)
9796 timevar_push (TV_VAR_TRACKING);
9797 variable_tracking_main ();
9798 timevar_pop (TV_VAR_TRACKING);
9800 df_finish_pass (false);
9803 /* Return true if REGNO is used by the epilogue. */
9806 ia64_epilogue_uses (int regno)
9811 /* With a call to a function in another module, we will write a new
9812 value to "gp". After returning from such a call, we need to make
9813 sure the function restores the original gp-value, even if the
9814 function itself does not use the gp anymore. */
9815 return !(TARGET_AUTO_PIC || TARGET_NO_PIC);
9817 case IN_REG (0): case IN_REG (1): case IN_REG (2): case IN_REG (3):
9818 case IN_REG (4): case IN_REG (5): case IN_REG (6): case IN_REG (7):
9819 /* For functions defined with the syscall_linkage attribute, all
9820 input registers are marked as live at all function exits. This
9821 prevents the register allocator from using the input registers,
9822 which in turn makes it possible to restart a system call after
9823 an interrupt without having to save/restore the input registers.
9824 This also prevents kernel data from leaking to application code. */
9825 return lookup_attribute ("syscall_linkage",
9826 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))) != NULL;
9829 /* Conditional return patterns can't represent the use of `b0' as
9830 the return address, so we force the value live this way. */
9834 /* Likewise for ar.pfs, which is used by br.ret. */
9842 /* Return true if REGNO is used by the frame unwinder. */
9845 ia64_eh_uses (int regno)
9849 if (! reload_completed)
9855 for (r = reg_save_b0; r <= reg_save_ar_lc; r++)
9856 if (regno == current_frame_info.r[r]
9857 || regno == emitted_frame_related_regs[r])
9863 /* Return true if this goes in small data/bss. */
9865 /* ??? We could also support own long data here. Generating movl/add/ld8
9866 instead of addl,ld8/ld8. This makes the code bigger, but should make the
9867 code faster because there is one less load. This also includes incomplete
9868 types which can't go in sdata/sbss. */
9871 ia64_in_small_data_p (const_tree exp)
9873 if (TARGET_NO_SDATA)
9876 /* We want to merge strings, so we never consider them small data. */
9877 if (TREE_CODE (exp) == STRING_CST)
9880 /* Functions are never small data. */
9881 if (TREE_CODE (exp) == FUNCTION_DECL)
9884 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
9886 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
9888 if (strcmp (section, ".sdata") == 0
9889 || strncmp (section, ".sdata.", 7) == 0
9890 || strncmp (section, ".gnu.linkonce.s.", 16) == 0
9891 || strcmp (section, ".sbss") == 0
9892 || strncmp (section, ".sbss.", 6) == 0
9893 || strncmp (section, ".gnu.linkonce.sb.", 17) == 0)
9898 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
9900 /* If this is an incomplete type with size 0, then we can't put it
9901 in sdata because it might be too big when completed. */
9902 if (size > 0 && size <= ia64_section_threshold)
9909 /* Output assembly directives for prologue regions. */
9911 /* The current basic block number. */
9913 static bool last_block;
9915 /* True if we need a copy_state command at the start of the next block. */
9917 static bool need_copy_state;
9919 #ifndef MAX_ARTIFICIAL_LABEL_BYTES
9920 # define MAX_ARTIFICIAL_LABEL_BYTES 30
9923 /* The function emits unwind directives for the start of an epilogue. */
9926 process_epilogue (FILE *asm_out_file, rtx insn ATTRIBUTE_UNUSED,
9927 bool unwind, bool frame ATTRIBUTE_UNUSED)
9929 /* If this isn't the last block of the function, then we need to label the
9930 current state, and copy it back in at the start of the next block. */
9935 fprintf (asm_out_file, "\t.label_state %d\n",
9936 ++cfun->machine->state_num);
9937 need_copy_state = true;
9941 fprintf (asm_out_file, "\t.restore sp\n");
9944 /* This function processes a SET pattern for REG_CFA_ADJUST_CFA. */
9947 process_cfa_adjust_cfa (FILE *asm_out_file, rtx pat, rtx insn,
9948 bool unwind, bool frame)
9950 rtx dest = SET_DEST (pat);
9951 rtx src = SET_SRC (pat);
9953 if (dest == stack_pointer_rtx)
9955 if (GET_CODE (src) == PLUS)
9957 rtx op0 = XEXP (src, 0);
9958 rtx op1 = XEXP (src, 1);
9960 gcc_assert (op0 == dest && GET_CODE (op1) == CONST_INT);
9962 if (INTVAL (op1) < 0)
9964 gcc_assert (!frame_pointer_needed);
9966 fprintf (asm_out_file,
9967 "\t.fframe "HOST_WIDE_INT_PRINT_DEC"\n",
9971 process_epilogue (asm_out_file, insn, unwind, frame);
9975 gcc_assert (src == hard_frame_pointer_rtx);
9976 process_epilogue (asm_out_file, insn, unwind, frame);
9979 else if (dest == hard_frame_pointer_rtx)
9981 gcc_assert (src == stack_pointer_rtx);
9982 gcc_assert (frame_pointer_needed);
9985 fprintf (asm_out_file, "\t.vframe r%d\n",
9986 ia64_dbx_register_number (REGNO (dest)));
9992 /* This function processes a SET pattern for REG_CFA_REGISTER. */
9995 process_cfa_register (FILE *asm_out_file, rtx pat, bool unwind)
9997 rtx dest = SET_DEST (pat);
9998 rtx src = SET_SRC (pat);
9999 int dest_regno = REGNO (dest);
10004 /* Saving return address pointer. */
10006 fprintf (asm_out_file, "\t.save rp, r%d\n",
10007 ia64_dbx_register_number (dest_regno));
10011 src_regno = REGNO (src);
10016 gcc_assert (dest_regno == current_frame_info.r[reg_save_pr]);
10018 fprintf (asm_out_file, "\t.save pr, r%d\n",
10019 ia64_dbx_register_number (dest_regno));
10022 case AR_UNAT_REGNUM:
10023 gcc_assert (dest_regno == current_frame_info.r[reg_save_ar_unat]);
10025 fprintf (asm_out_file, "\t.save ar.unat, r%d\n",
10026 ia64_dbx_register_number (dest_regno));
10030 gcc_assert (dest_regno == current_frame_info.r[reg_save_ar_lc]);
10032 fprintf (asm_out_file, "\t.save ar.lc, r%d\n",
10033 ia64_dbx_register_number (dest_regno));
10037 /* Everything else should indicate being stored to memory. */
10038 gcc_unreachable ();
10042 /* This function processes a SET pattern for REG_CFA_OFFSET. */
10045 process_cfa_offset (FILE *asm_out_file, rtx pat, bool unwind)
10047 rtx dest = SET_DEST (pat);
10048 rtx src = SET_SRC (pat);
10049 int src_regno = REGNO (src);
10050 const char *saveop;
10054 gcc_assert (MEM_P (dest));
10055 if (GET_CODE (XEXP (dest, 0)) == REG)
10057 base = XEXP (dest, 0);
10062 gcc_assert (GET_CODE (XEXP (dest, 0)) == PLUS
10063 && GET_CODE (XEXP (XEXP (dest, 0), 1)) == CONST_INT);
10064 base = XEXP (XEXP (dest, 0), 0);
10065 off = INTVAL (XEXP (XEXP (dest, 0), 1));
10068 if (base == hard_frame_pointer_rtx)
10070 saveop = ".savepsp";
10075 gcc_assert (base == stack_pointer_rtx);
10076 saveop = ".savesp";
10079 src_regno = REGNO (src);
10083 gcc_assert (!current_frame_info.r[reg_save_b0]);
10085 fprintf (asm_out_file, "\t%s rp, " HOST_WIDE_INT_PRINT_DEC "\n",
10090 gcc_assert (!current_frame_info.r[reg_save_pr]);
10092 fprintf (asm_out_file, "\t%s pr, " HOST_WIDE_INT_PRINT_DEC "\n",
10097 gcc_assert (!current_frame_info.r[reg_save_ar_lc]);
10099 fprintf (asm_out_file, "\t%s ar.lc, " HOST_WIDE_INT_PRINT_DEC "\n",
10103 case AR_PFS_REGNUM:
10104 gcc_assert (!current_frame_info.r[reg_save_ar_pfs]);
10106 fprintf (asm_out_file, "\t%s ar.pfs, " HOST_WIDE_INT_PRINT_DEC "\n",
10110 case AR_UNAT_REGNUM:
10111 gcc_assert (!current_frame_info.r[reg_save_ar_unat]);
10113 fprintf (asm_out_file, "\t%s ar.unat, " HOST_WIDE_INT_PRINT_DEC "\n",
10122 fprintf (asm_out_file, "\t.save.g 0x%x\n",
10123 1 << (src_regno - GR_REG (4)));
10132 fprintf (asm_out_file, "\t.save.b 0x%x\n",
10133 1 << (src_regno - BR_REG (1)));
10141 fprintf (asm_out_file, "\t.save.f 0x%x\n",
10142 1 << (src_regno - FR_REG (2)));
10145 case FR_REG (16): case FR_REG (17): case FR_REG (18): case FR_REG (19):
10146 case FR_REG (20): case FR_REG (21): case FR_REG (22): case FR_REG (23):
10147 case FR_REG (24): case FR_REG (25): case FR_REG (26): case FR_REG (27):
10148 case FR_REG (28): case FR_REG (29): case FR_REG (30): case FR_REG (31):
10150 fprintf (asm_out_file, "\t.save.gf 0x0, 0x%x\n",
10151 1 << (src_regno - FR_REG (12)));
10155 /* ??? For some reason we mark other general registers, even those
10156 we can't represent in the unwind info. Ignore them. */
10161 /* This function looks at a single insn and emits any directives
10162 required to unwind this insn. */
10165 ia64_asm_unwind_emit (FILE *asm_out_file, rtx insn)
10167 bool unwind = ia64_except_unwind_info (&global_options) == UI_TARGET;
10168 bool frame = dwarf2out_do_frame ();
10172 if (!unwind && !frame)
10175 if (NOTE_INSN_BASIC_BLOCK_P (insn))
10177 last_block = NOTE_BASIC_BLOCK (insn)->next_bb == EXIT_BLOCK_PTR;
10179 /* Restore unwind state from immediately before the epilogue. */
10180 if (need_copy_state)
10184 fprintf (asm_out_file, "\t.body\n");
10185 fprintf (asm_out_file, "\t.copy_state %d\n",
10186 cfun->machine->state_num);
10188 need_copy_state = false;
10192 if (GET_CODE (insn) == NOTE || ! RTX_FRAME_RELATED_P (insn))
10195 /* Look for the ALLOC insn. */
10196 if (INSN_CODE (insn) == CODE_FOR_alloc)
10198 rtx dest = SET_DEST (XVECEXP (PATTERN (insn), 0, 0));
10199 int dest_regno = REGNO (dest);
10201 /* If this is the final destination for ar.pfs, then this must
10202 be the alloc in the prologue. */
10203 if (dest_regno == current_frame_info.r[reg_save_ar_pfs])
10206 fprintf (asm_out_file, "\t.save ar.pfs, r%d\n",
10207 ia64_dbx_register_number (dest_regno));
10211 /* This must be an alloc before a sibcall. We must drop the
10212 old frame info. The easiest way to drop the old frame
10213 info is to ensure we had a ".restore sp" directive
10214 followed by a new prologue. If the procedure doesn't
10215 have a memory-stack frame, we'll issue a dummy ".restore
10217 if (current_frame_info.total_size == 0 && !frame_pointer_needed)
10218 /* if haven't done process_epilogue() yet, do it now */
10219 process_epilogue (asm_out_file, insn, unwind, frame);
10221 fprintf (asm_out_file, "\t.prologue\n");
10226 handled_one = false;
10227 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
10228 switch (REG_NOTE_KIND (note))
10230 case REG_CFA_ADJUST_CFA:
10231 pat = XEXP (note, 0);
10233 pat = PATTERN (insn);
10234 process_cfa_adjust_cfa (asm_out_file, pat, insn, unwind, frame);
10235 handled_one = true;
10238 case REG_CFA_OFFSET:
10239 pat = XEXP (note, 0);
10241 pat = PATTERN (insn);
10242 process_cfa_offset (asm_out_file, pat, unwind);
10243 handled_one = true;
10246 case REG_CFA_REGISTER:
10247 pat = XEXP (note, 0);
10249 pat = PATTERN (insn);
10250 process_cfa_register (asm_out_file, pat, unwind);
10251 handled_one = true;
10254 case REG_FRAME_RELATED_EXPR:
10255 case REG_CFA_DEF_CFA:
10256 case REG_CFA_EXPRESSION:
10257 case REG_CFA_RESTORE:
10258 case REG_CFA_SET_VDRAP:
10259 /* Not used in the ia64 port. */
10260 gcc_unreachable ();
10263 /* Not a frame-related note. */
10267 /* All REG_FRAME_RELATED_P insns, besides ALLOC, are marked with the
10268 explicit action to take. No guessing required. */
10269 gcc_assert (handled_one);
10272 /* Implement TARGET_ASM_EMIT_EXCEPT_PERSONALITY. */
10275 ia64_asm_emit_except_personality (rtx personality)
10277 fputs ("\t.personality\t", asm_out_file);
10278 output_addr_const (asm_out_file, personality);
10279 fputc ('\n', asm_out_file);
10282 /* Implement TARGET_ASM_INITIALIZE_SECTIONS. */
10285 ia64_asm_init_sections (void)
10287 exception_section = get_unnamed_section (0, output_section_asm_op,
10291 /* Implement TARGET_DEBUG_UNWIND_INFO. */
10293 static enum unwind_info_type
10294 ia64_debug_unwind_info (void)
10302 IA64_BUILTIN_COPYSIGNQ,
10303 IA64_BUILTIN_FABSQ,
10304 IA64_BUILTIN_FLUSHRS,
10306 IA64_BUILTIN_HUGE_VALQ,
10310 static GTY(()) tree ia64_builtins[(int) IA64_BUILTIN_max];
10313 ia64_init_builtins (void)
10319 /* The __fpreg type. */
10320 fpreg_type = make_node (REAL_TYPE);
10321 TYPE_PRECISION (fpreg_type) = 82;
10322 layout_type (fpreg_type);
10323 (*lang_hooks.types.register_builtin_type) (fpreg_type, "__fpreg");
10325 /* The __float80 type. */
10326 float80_type = make_node (REAL_TYPE);
10327 TYPE_PRECISION (float80_type) = 80;
10328 layout_type (float80_type);
10329 (*lang_hooks.types.register_builtin_type) (float80_type, "__float80");
10331 /* The __float128 type. */
10335 tree float128_type = make_node (REAL_TYPE);
10337 TYPE_PRECISION (float128_type) = 128;
10338 layout_type (float128_type);
10339 (*lang_hooks.types.register_builtin_type) (float128_type, "__float128");
10341 /* TFmode support builtins. */
10342 ftype = build_function_type_list (float128_type, NULL_TREE);
10343 decl = add_builtin_function ("__builtin_infq", ftype,
10344 IA64_BUILTIN_INFQ, BUILT_IN_MD,
10346 ia64_builtins[IA64_BUILTIN_INFQ] = decl;
10348 decl = add_builtin_function ("__builtin_huge_valq", ftype,
10349 IA64_BUILTIN_HUGE_VALQ, BUILT_IN_MD,
10351 ia64_builtins[IA64_BUILTIN_HUGE_VALQ] = decl;
10353 ftype = build_function_type_list (float128_type,
10356 decl = add_builtin_function ("__builtin_fabsq", ftype,
10357 IA64_BUILTIN_FABSQ, BUILT_IN_MD,
10358 "__fabstf2", NULL_TREE);
10359 TREE_READONLY (decl) = 1;
10360 ia64_builtins[IA64_BUILTIN_FABSQ] = decl;
10362 ftype = build_function_type_list (float128_type,
10366 decl = add_builtin_function ("__builtin_copysignq", ftype,
10367 IA64_BUILTIN_COPYSIGNQ, BUILT_IN_MD,
10368 "__copysigntf3", NULL_TREE);
10369 TREE_READONLY (decl) = 1;
10370 ia64_builtins[IA64_BUILTIN_COPYSIGNQ] = decl;
10373 /* Under HPUX, this is a synonym for "long double". */
10374 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
10377 /* Fwrite on VMS is non-standard. */
10378 #if TARGET_ABI_OPEN_VMS
10379 vms_patch_builtins ();
10382 #define def_builtin(name, type, code) \
10383 add_builtin_function ((name), (type), (code), BUILT_IN_MD, \
10386 decl = def_builtin ("__builtin_ia64_bsp",
10387 build_function_type_list (ptr_type_node, NULL_TREE),
10389 ia64_builtins[IA64_BUILTIN_BSP] = decl;
10391 decl = def_builtin ("__builtin_ia64_flushrs",
10392 build_function_type_list (void_type_node, NULL_TREE),
10393 IA64_BUILTIN_FLUSHRS);
10394 ia64_builtins[IA64_BUILTIN_FLUSHRS] = decl;
10400 if ((decl = builtin_decl_explicit (BUILT_IN_FINITE)) != NULL_TREE)
10401 set_user_assembler_name (decl, "_Isfinite");
10402 if ((decl = builtin_decl_explicit (BUILT_IN_FINITEF)) != NULL_TREE)
10403 set_user_assembler_name (decl, "_Isfinitef");
10404 if ((decl = builtin_decl_explicit (BUILT_IN_FINITEL)) != NULL_TREE)
10405 set_user_assembler_name (decl, "_Isfinitef128");
10410 ia64_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
10411 enum machine_mode mode ATTRIBUTE_UNUSED,
10412 int ignore ATTRIBUTE_UNUSED)
10414 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10415 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10419 case IA64_BUILTIN_BSP:
10420 if (! target || ! register_operand (target, DImode))
10421 target = gen_reg_rtx (DImode);
10422 emit_insn (gen_bsp_value (target));
10423 #ifdef POINTERS_EXTEND_UNSIGNED
10424 target = convert_memory_address (ptr_mode, target);
10428 case IA64_BUILTIN_FLUSHRS:
10429 emit_insn (gen_flushrs ());
10432 case IA64_BUILTIN_INFQ:
10433 case IA64_BUILTIN_HUGE_VALQ:
10435 enum machine_mode target_mode = TYPE_MODE (TREE_TYPE (exp));
10436 REAL_VALUE_TYPE inf;
10440 tmp = CONST_DOUBLE_FROM_REAL_VALUE (inf, target_mode);
10442 tmp = validize_mem (force_const_mem (target_mode, tmp));
10445 target = gen_reg_rtx (target_mode);
10447 emit_move_insn (target, tmp);
10451 case IA64_BUILTIN_FABSQ:
10452 case IA64_BUILTIN_COPYSIGNQ:
10453 return expand_call (exp, target, ignore);
10456 gcc_unreachable ();
10462 /* Return the ia64 builtin for CODE. */
10465 ia64_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
10467 if (code >= IA64_BUILTIN_max)
10468 return error_mark_node;
10470 return ia64_builtins[code];
10473 /* For the HP-UX IA64 aggregate parameters are passed stored in the
10474 most significant bits of the stack slot. */
10477 ia64_hpux_function_arg_padding (enum machine_mode mode, const_tree type)
10479 /* Exception to normal case for structures/unions/etc. */
10481 if (type && AGGREGATE_TYPE_P (type)
10482 && int_size_in_bytes (type) < UNITS_PER_WORD)
10485 /* Fall back to the default. */
10486 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
10489 /* Emit text to declare externally defined variables and functions, because
10490 the Intel assembler does not support undefined externals. */
10493 ia64_asm_output_external (FILE *file, tree decl, const char *name)
10495 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
10496 set in order to avoid putting out names that are never really
10498 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
10500 /* maybe_assemble_visibility will return 1 if the assembler
10501 visibility directive is output. */
10502 int need_visibility = ((*targetm.binds_local_p) (decl)
10503 && maybe_assemble_visibility (decl));
10505 /* GNU as does not need anything here, but the HP linker does
10506 need something for external functions. */
10507 if ((TARGET_HPUX_LD || !TARGET_GNU_AS)
10508 && TREE_CODE (decl) == FUNCTION_DECL)
10509 (*targetm.asm_out.globalize_decl_name) (file, decl);
10510 else if (need_visibility && !TARGET_GNU_AS)
10511 (*targetm.asm_out.globalize_label) (file, name);
10515 /* Set SImode div/mod functions, init_integral_libfuncs only initializes
10516 modes of word_mode and larger. Rename the TFmode libfuncs using the
10517 HPUX conventions. __divtf3 is used for XFmode. We need to keep it for
10518 backward compatibility. */
10521 ia64_init_libfuncs (void)
10523 set_optab_libfunc (sdiv_optab, SImode, "__divsi3");
10524 set_optab_libfunc (udiv_optab, SImode, "__udivsi3");
10525 set_optab_libfunc (smod_optab, SImode, "__modsi3");
10526 set_optab_libfunc (umod_optab, SImode, "__umodsi3");
10528 set_optab_libfunc (add_optab, TFmode, "_U_Qfadd");
10529 set_optab_libfunc (sub_optab, TFmode, "_U_Qfsub");
10530 set_optab_libfunc (smul_optab, TFmode, "_U_Qfmpy");
10531 set_optab_libfunc (sdiv_optab, TFmode, "_U_Qfdiv");
10532 set_optab_libfunc (neg_optab, TFmode, "_U_Qfneg");
10534 set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad");
10535 set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad");
10536 set_conv_libfunc (sext_optab, TFmode, XFmode, "_U_Qfcnvff_f80_to_quad");
10537 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl");
10538 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl");
10539 set_conv_libfunc (trunc_optab, XFmode, TFmode, "_U_Qfcnvff_quad_to_f80");
10541 set_conv_libfunc (sfix_optab, SImode, TFmode, "_U_Qfcnvfxt_quad_to_sgl");
10542 set_conv_libfunc (sfix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_dbl");
10543 set_conv_libfunc (sfix_optab, TImode, TFmode, "_U_Qfcnvfxt_quad_to_quad");
10544 set_conv_libfunc (ufix_optab, SImode, TFmode, "_U_Qfcnvfxut_quad_to_sgl");
10545 set_conv_libfunc (ufix_optab, DImode, TFmode, "_U_Qfcnvfxut_quad_to_dbl");
10547 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_U_Qfcnvxf_sgl_to_quad");
10548 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_U_Qfcnvxf_dbl_to_quad");
10549 set_conv_libfunc (sfloat_optab, TFmode, TImode, "_U_Qfcnvxf_quad_to_quad");
10550 /* HP-UX 11.23 libc does not have a function for unsigned
10551 SImode-to-TFmode conversion. */
10552 set_conv_libfunc (ufloat_optab, TFmode, DImode, "_U_Qfcnvxuf_dbl_to_quad");
10555 /* Rename all the TFmode libfuncs using the HPUX conventions. */
10558 ia64_hpux_init_libfuncs (void)
10560 ia64_init_libfuncs ();
10562 /* The HP SI millicode division and mod functions expect DI arguments.
10563 By turning them off completely we avoid using both libgcc and the
10564 non-standard millicode routines and use the HP DI millicode routines
10567 set_optab_libfunc (sdiv_optab, SImode, 0);
10568 set_optab_libfunc (udiv_optab, SImode, 0);
10569 set_optab_libfunc (smod_optab, SImode, 0);
10570 set_optab_libfunc (umod_optab, SImode, 0);
10572 set_optab_libfunc (sdiv_optab, DImode, "__milli_divI");
10573 set_optab_libfunc (udiv_optab, DImode, "__milli_divU");
10574 set_optab_libfunc (smod_optab, DImode, "__milli_remI");
10575 set_optab_libfunc (umod_optab, DImode, "__milli_remU");
10577 /* HP-UX libc has TF min/max/abs routines in it. */
10578 set_optab_libfunc (smin_optab, TFmode, "_U_Qfmin");
10579 set_optab_libfunc (smax_optab, TFmode, "_U_Qfmax");
10580 set_optab_libfunc (abs_optab, TFmode, "_U_Qfabs");
10582 /* ia64_expand_compare uses this. */
10583 cmptf_libfunc = init_one_libfunc ("_U_Qfcmp");
10585 /* These should never be used. */
10586 set_optab_libfunc (eq_optab, TFmode, 0);
10587 set_optab_libfunc (ne_optab, TFmode, 0);
10588 set_optab_libfunc (gt_optab, TFmode, 0);
10589 set_optab_libfunc (ge_optab, TFmode, 0);
10590 set_optab_libfunc (lt_optab, TFmode, 0);
10591 set_optab_libfunc (le_optab, TFmode, 0);
10594 /* Rename the division and modulus functions in VMS. */
10597 ia64_vms_init_libfuncs (void)
10599 set_optab_libfunc (sdiv_optab, SImode, "OTS$DIV_I");
10600 set_optab_libfunc (sdiv_optab, DImode, "OTS$DIV_L");
10601 set_optab_libfunc (udiv_optab, SImode, "OTS$DIV_UI");
10602 set_optab_libfunc (udiv_optab, DImode, "OTS$DIV_UL");
10603 set_optab_libfunc (smod_optab, SImode, "OTS$REM_I");
10604 set_optab_libfunc (smod_optab, DImode, "OTS$REM_L");
10605 set_optab_libfunc (umod_optab, SImode, "OTS$REM_UI");
10606 set_optab_libfunc (umod_optab, DImode, "OTS$REM_UL");
10607 abort_libfunc = init_one_libfunc ("decc$abort");
10608 memcmp_libfunc = init_one_libfunc ("decc$memcmp");
10609 #ifdef MEM_LIBFUNCS_INIT
10614 /* Rename the TFmode libfuncs available from soft-fp in glibc using
10615 the HPUX conventions. */
10618 ia64_sysv4_init_libfuncs (void)
10620 ia64_init_libfuncs ();
10622 /* These functions are not part of the HPUX TFmode interface. We
10623 use them instead of _U_Qfcmp, which doesn't work the way we
10625 set_optab_libfunc (eq_optab, TFmode, "_U_Qfeq");
10626 set_optab_libfunc (ne_optab, TFmode, "_U_Qfne");
10627 set_optab_libfunc (gt_optab, TFmode, "_U_Qfgt");
10628 set_optab_libfunc (ge_optab, TFmode, "_U_Qfge");
10629 set_optab_libfunc (lt_optab, TFmode, "_U_Qflt");
10630 set_optab_libfunc (le_optab, TFmode, "_U_Qfle");
10632 /* We leave out _U_Qfmin, _U_Qfmax and _U_Qfabs since soft-fp in
10633 glibc doesn't have them. */
10639 ia64_soft_fp_init_libfuncs (void)
10644 ia64_vms_valid_pointer_mode (enum machine_mode mode)
10646 return (mode == SImode || mode == DImode);
10649 /* For HPUX, it is illegal to have relocations in shared segments. */
10652 ia64_hpux_reloc_rw_mask (void)
10657 /* For others, relax this so that relocations to local data goes in
10658 read-only segments, but we still cannot allow global relocations
10659 in read-only segments. */
10662 ia64_reloc_rw_mask (void)
10664 return flag_pic ? 3 : 2;
10667 /* Return the section to use for X. The only special thing we do here
10668 is to honor small data. */
10671 ia64_select_rtx_section (enum machine_mode mode, rtx x,
10672 unsigned HOST_WIDE_INT align)
10674 if (GET_MODE_SIZE (mode) > 0
10675 && GET_MODE_SIZE (mode) <= ia64_section_threshold
10676 && !TARGET_NO_SDATA)
10677 return sdata_section;
10679 return default_elf_select_rtx_section (mode, x, align);
10682 static unsigned int
10683 ia64_section_type_flags (tree decl, const char *name, int reloc)
10685 unsigned int flags = 0;
10687 if (strcmp (name, ".sdata") == 0
10688 || strncmp (name, ".sdata.", 7) == 0
10689 || strncmp (name, ".gnu.linkonce.s.", 16) == 0
10690 || strncmp (name, ".sdata2.", 8) == 0
10691 || strncmp (name, ".gnu.linkonce.s2.", 17) == 0
10692 || strcmp (name, ".sbss") == 0
10693 || strncmp (name, ".sbss.", 6) == 0
10694 || strncmp (name, ".gnu.linkonce.sb.", 17) == 0)
10695 flags = SECTION_SMALL;
10697 flags |= default_section_type_flags (decl, name, reloc);
10701 /* Returns true if FNTYPE (a FUNCTION_TYPE or a METHOD_TYPE) returns a
10702 structure type and that the address of that type should be passed
10703 in out0, rather than in r8. */
10706 ia64_struct_retval_addr_is_first_parm_p (tree fntype)
10708 tree ret_type = TREE_TYPE (fntype);
10710 /* The Itanium C++ ABI requires that out0, rather than r8, be used
10711 as the structure return address parameter, if the return value
10712 type has a non-trivial copy constructor or destructor. It is not
10713 clear if this same convention should be used for other
10714 programming languages. Until G++ 3.4, we incorrectly used r8 for
10715 these return values. */
10716 return (abi_version_at_least (2)
10718 && TYPE_MODE (ret_type) == BLKmode
10719 && TREE_ADDRESSABLE (ret_type)
10720 && strcmp (lang_hooks.name, "GNU C++") == 0);
10723 /* Output the assembler code for a thunk function. THUNK_DECL is the
10724 declaration for the thunk function itself, FUNCTION is the decl for
10725 the target function. DELTA is an immediate constant offset to be
10726 added to THIS. If VCALL_OFFSET is nonzero, the word at
10727 *(*this + vcall_offset) should be added to THIS. */
10730 ia64_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
10731 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
10734 rtx this_rtx, insn, funexp;
10735 unsigned int this_parmno;
10736 unsigned int this_regno;
10739 reload_completed = 1;
10740 epilogue_completed = 1;
10742 /* Set things up as ia64_expand_prologue might. */
10743 last_scratch_gr_reg = 15;
10745 memset (¤t_frame_info, 0, sizeof (current_frame_info));
10746 current_frame_info.spill_cfa_off = -16;
10747 current_frame_info.n_input_regs = 1;
10748 current_frame_info.need_regstk = (TARGET_REG_NAMES != 0);
10750 /* Mark the end of the (empty) prologue. */
10751 emit_note (NOTE_INSN_PROLOGUE_END);
10753 /* Figure out whether "this" will be the first parameter (the
10754 typical case) or the second parameter (as happens when the
10755 virtual function returns certain class objects). */
10757 = (ia64_struct_retval_addr_is_first_parm_p (TREE_TYPE (thunk))
10759 this_regno = IN_REG (this_parmno);
10760 if (!TARGET_REG_NAMES)
10761 reg_names[this_regno] = ia64_reg_numbers[this_parmno];
10763 this_rtx = gen_rtx_REG (Pmode, this_regno);
10765 /* Apply the constant offset, if required. */
10766 delta_rtx = GEN_INT (delta);
10769 rtx tmp = gen_rtx_REG (ptr_mode, this_regno);
10770 REG_POINTER (tmp) = 1;
10771 if (delta && satisfies_constraint_I (delta_rtx))
10773 emit_insn (gen_ptr_extend_plus_imm (this_rtx, tmp, delta_rtx));
10777 emit_insn (gen_ptr_extend (this_rtx, tmp));
10781 if (!satisfies_constraint_I (delta_rtx))
10783 rtx tmp = gen_rtx_REG (Pmode, 2);
10784 emit_move_insn (tmp, delta_rtx);
10787 emit_insn (gen_adddi3 (this_rtx, this_rtx, delta_rtx));
10790 /* Apply the offset from the vtable, if required. */
10793 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
10794 rtx tmp = gen_rtx_REG (Pmode, 2);
10798 rtx t = gen_rtx_REG (ptr_mode, 2);
10799 REG_POINTER (t) = 1;
10800 emit_move_insn (t, gen_rtx_MEM (ptr_mode, this_rtx));
10801 if (satisfies_constraint_I (vcall_offset_rtx))
10803 emit_insn (gen_ptr_extend_plus_imm (tmp, t, vcall_offset_rtx));
10807 emit_insn (gen_ptr_extend (tmp, t));
10810 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this_rtx));
10814 if (!satisfies_constraint_J (vcall_offset_rtx))
10816 rtx tmp2 = gen_rtx_REG (Pmode, next_scratch_gr_reg ());
10817 emit_move_insn (tmp2, vcall_offset_rtx);
10818 vcall_offset_rtx = tmp2;
10820 emit_insn (gen_adddi3 (tmp, tmp, vcall_offset_rtx));
10824 emit_insn (gen_zero_extendsidi2 (tmp, gen_rtx_MEM (ptr_mode, tmp)));
10826 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
10828 emit_insn (gen_adddi3 (this_rtx, this_rtx, tmp));
10831 /* Generate a tail call to the target function. */
10832 if (! TREE_USED (function))
10834 assemble_external (function);
10835 TREE_USED (function) = 1;
10837 funexp = XEXP (DECL_RTL (function), 0);
10838 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
10839 ia64_expand_call (NULL_RTX, funexp, NULL_RTX, 1);
10840 insn = get_last_insn ();
10841 SIBLING_CALL_P (insn) = 1;
10843 /* Code generation for calls relies on splitting. */
10844 reload_completed = 1;
10845 epilogue_completed = 1;
10846 try_split (PATTERN (insn), insn, 0);
10850 /* Run just enough of rest_of_compilation to get the insns emitted.
10851 There's not really enough bulk here to make other passes such as
10852 instruction scheduling worth while. Note that use_thunk calls
10853 assemble_start_function and assemble_end_function. */
10855 insn_locators_alloc ();
10856 emit_all_insn_group_barriers (NULL);
10857 insn = get_insns ();
10858 shorten_branches (insn);
10859 final_start_function (insn, file, 1);
10860 final (insn, file, 1);
10861 final_end_function ();
10863 reload_completed = 0;
10864 epilogue_completed = 0;
10867 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
10870 ia64_struct_value_rtx (tree fntype,
10871 int incoming ATTRIBUTE_UNUSED)
10873 if (TARGET_ABI_OPEN_VMS ||
10874 (fntype && ia64_struct_retval_addr_is_first_parm_p (fntype)))
10876 return gen_rtx_REG (Pmode, GR_REG (8));
10880 ia64_scalar_mode_supported_p (enum machine_mode mode)
10906 ia64_vector_mode_supported_p (enum machine_mode mode)
10923 /* Implement the FUNCTION_PROFILER macro. */
10926 ia64_output_function_profiler (FILE *file, int labelno)
10928 bool indirect_call;
10930 /* If the function needs a static chain and the static chain
10931 register is r15, we use an indirect call so as to bypass
10932 the PLT stub in case the executable is dynamically linked,
10933 because the stub clobbers r15 as per 5.3.6 of the psABI.
10934 We don't need to do that in non canonical PIC mode. */
10936 if (cfun->static_chain_decl && !TARGET_NO_PIC && !TARGET_AUTO_PIC)
10938 gcc_assert (STATIC_CHAIN_REGNUM == 15);
10939 indirect_call = true;
10942 indirect_call = false;
10945 fputs ("\t.prologue 4, r40\n", file);
10947 fputs ("\t.prologue\n\t.save ar.pfs, r40\n", file);
10948 fputs ("\talloc out0 = ar.pfs, 8, 0, 4, 0\n", file);
10950 if (NO_PROFILE_COUNTERS)
10951 fputs ("\tmov out3 = r0\n", file);
10955 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
10957 if (TARGET_AUTO_PIC)
10958 fputs ("\tmovl out3 = @gprel(", file);
10960 fputs ("\taddl out3 = @ltoff(", file);
10961 assemble_name (file, buf);
10962 if (TARGET_AUTO_PIC)
10963 fputs (")\n", file);
10965 fputs ("), r1\n", file);
10969 fputs ("\taddl r14 = @ltoff(@fptr(_mcount)), r1\n", file);
10970 fputs ("\t;;\n", file);
10972 fputs ("\t.save rp, r42\n", file);
10973 fputs ("\tmov out2 = b0\n", file);
10975 fputs ("\tld8 r14 = [r14]\n\t;;\n", file);
10976 fputs ("\t.body\n", file);
10977 fputs ("\tmov out1 = r1\n", file);
10980 fputs ("\tld8 r16 = [r14], 8\n\t;;\n", file);
10981 fputs ("\tmov b6 = r16\n", file);
10982 fputs ("\tld8 r1 = [r14]\n", file);
10983 fputs ("\tbr.call.sptk.many b0 = b6\n\t;;\n", file);
10986 fputs ("\tbr.call.sptk.many b0 = _mcount\n\t;;\n", file);
10989 static GTY(()) rtx mcount_func_rtx;
10991 gen_mcount_func_rtx (void)
10993 if (!mcount_func_rtx)
10994 mcount_func_rtx = init_one_libfunc ("_mcount");
10995 return mcount_func_rtx;
10999 ia64_profile_hook (int labelno)
11003 if (NO_PROFILE_COUNTERS)
11004 label = const0_rtx;
11008 const char *label_name;
11009 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
11010 label_name = ggc_strdup ((*targetm.strip_name_encoding) (buf));
11011 label = gen_rtx_SYMBOL_REF (Pmode, label_name);
11012 SYMBOL_REF_FLAGS (label) = SYMBOL_FLAG_LOCAL;
11014 ip = gen_reg_rtx (Pmode);
11015 emit_insn (gen_ip_value (ip));
11016 emit_library_call (gen_mcount_func_rtx (), LCT_NORMAL,
11018 gen_rtx_REG (Pmode, BR_REG (0)), Pmode,
11023 /* Return the mangling of TYPE if it is an extended fundamental type. */
11025 static const char *
11026 ia64_mangle_type (const_tree type)
11028 type = TYPE_MAIN_VARIANT (type);
11030 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
11031 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
11034 /* On HP-UX, "long double" is mangled as "e" so __float128 is
11036 if (!TARGET_HPUX && TYPE_MODE (type) == TFmode)
11038 /* On HP-UX, "e" is not available as a mangling of __float80 so use
11039 an extended mangling. Elsewhere, "e" is available since long
11040 double is 80 bits. */
11041 if (TYPE_MODE (type) == XFmode)
11042 return TARGET_HPUX ? "u9__float80" : "e";
11043 if (TYPE_MODE (type) == RFmode)
11044 return "u7__fpreg";
11048 /* Return the diagnostic message string if conversion from FROMTYPE to
11049 TOTYPE is not allowed, NULL otherwise. */
11050 static const char *
11051 ia64_invalid_conversion (const_tree fromtype, const_tree totype)
11053 /* Reject nontrivial conversion to or from __fpreg. */
11054 if (TYPE_MODE (fromtype) == RFmode
11055 && TYPE_MODE (totype) != RFmode
11056 && TYPE_MODE (totype) != VOIDmode)
11057 return N_("invalid conversion from %<__fpreg%>");
11058 if (TYPE_MODE (totype) == RFmode
11059 && TYPE_MODE (fromtype) != RFmode)
11060 return N_("invalid conversion to %<__fpreg%>");
11064 /* Return the diagnostic message string if the unary operation OP is
11065 not permitted on TYPE, NULL otherwise. */
11066 static const char *
11067 ia64_invalid_unary_op (int op, const_tree type)
11069 /* Reject operations on __fpreg other than unary + or &. */
11070 if (TYPE_MODE (type) == RFmode
11071 && op != CONVERT_EXPR
11072 && op != ADDR_EXPR)
11073 return N_("invalid operation on %<__fpreg%>");
11077 /* Return the diagnostic message string if the binary operation OP is
11078 not permitted on TYPE1 and TYPE2, NULL otherwise. */
11079 static const char *
11080 ia64_invalid_binary_op (int op ATTRIBUTE_UNUSED, const_tree type1, const_tree type2)
11082 /* Reject operations on __fpreg. */
11083 if (TYPE_MODE (type1) == RFmode || TYPE_MODE (type2) == RFmode)
11084 return N_("invalid operation on %<__fpreg%>");
11088 /* HP-UX version_id attribute.
11089 For object foo, if the version_id is set to 1234 put out an alias
11090 of '.alias foo "foo{1234}" We can't use "foo{1234}" in anything
11091 other than an alias statement because it is an illegal symbol name. */
11094 ia64_handle_version_id_attribute (tree *node ATTRIBUTE_UNUSED,
11095 tree name ATTRIBUTE_UNUSED,
11097 int flags ATTRIBUTE_UNUSED,
11098 bool *no_add_attrs)
11100 tree arg = TREE_VALUE (args);
11102 if (TREE_CODE (arg) != STRING_CST)
11104 error("version attribute is not a string");
11105 *no_add_attrs = true;
11111 /* Target hook for c_mode_for_suffix. */
11113 static enum machine_mode
11114 ia64_c_mode_for_suffix (char suffix)
11124 static GTY(()) rtx ia64_dconst_0_5_rtx;
11127 ia64_dconst_0_5 (void)
11129 if (! ia64_dconst_0_5_rtx)
11131 REAL_VALUE_TYPE rv;
11132 real_from_string (&rv, "0.5");
11133 ia64_dconst_0_5_rtx = const_double_from_real_value (rv, DFmode);
11135 return ia64_dconst_0_5_rtx;
11138 static GTY(()) rtx ia64_dconst_0_375_rtx;
11141 ia64_dconst_0_375 (void)
11143 if (! ia64_dconst_0_375_rtx)
11145 REAL_VALUE_TYPE rv;
11146 real_from_string (&rv, "0.375");
11147 ia64_dconst_0_375_rtx = const_double_from_real_value (rv, DFmode);
11149 return ia64_dconst_0_375_rtx;
11152 static enum machine_mode
11153 ia64_get_reg_raw_mode (int regno)
11155 if (FR_REGNO_P (regno))
11157 return default_get_reg_raw_mode(regno);
11160 /* Implement TARGET_MEMBER_TYPE_FORCES_BLK. ??? Might not be needed
11164 ia64_member_type_forces_blk (const_tree, enum machine_mode mode)
11166 return TARGET_HPUX && mode == TFmode;
11169 /* Always default to .text section until HP-UX linker is fixed. */
11171 ATTRIBUTE_UNUSED static section *
11172 ia64_hpux_function_section (tree decl ATTRIBUTE_UNUSED,
11173 enum node_frequency freq ATTRIBUTE_UNUSED,
11174 bool startup ATTRIBUTE_UNUSED,
11175 bool exit ATTRIBUTE_UNUSED)
11180 /* Construct (set target (vec_select op0 (parallel perm))) and
11181 return true if that's a valid instruction in the active ISA. */
11184 expand_vselect (rtx target, rtx op0, const unsigned char *perm, unsigned nelt)
11186 rtx rperm[MAX_VECT_LEN], x;
11189 for (i = 0; i < nelt; ++i)
11190 rperm[i] = GEN_INT (perm[i]);
11192 x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (nelt, rperm));
11193 x = gen_rtx_VEC_SELECT (GET_MODE (target), op0, x);
11194 x = gen_rtx_SET (VOIDmode, target, x);
11197 if (recog_memoized (x) < 0)
11205 /* Similar, but generate a vec_concat from op0 and op1 as well. */
11208 expand_vselect_vconcat (rtx target, rtx op0, rtx op1,
11209 const unsigned char *perm, unsigned nelt)
11211 enum machine_mode v2mode;
11214 v2mode = GET_MODE_2XWIDER_MODE (GET_MODE (op0));
11215 x = gen_rtx_VEC_CONCAT (v2mode, op0, op1);
11216 return expand_vselect (target, x, perm, nelt);
11219 /* Try to expand a no-op permutation. */
11222 expand_vec_perm_identity (struct expand_vec_perm_d *d)
11224 unsigned i, nelt = d->nelt;
11226 for (i = 0; i < nelt; ++i)
11227 if (d->perm[i] != i)
11231 emit_move_insn (d->target, d->op0);
11236 /* Try to expand D via a shrp instruction. */
11239 expand_vec_perm_shrp (struct expand_vec_perm_d *d)
11241 unsigned i, nelt = d->nelt, shift, mask;
11244 /* ??? Don't force V2SFmode into the integer registers. */
11245 if (d->vmode == V2SFmode)
11248 mask = (d->one_operand_p ? nelt - 1 : 2 * nelt - 1);
11250 shift = d->perm[0];
11251 if (BYTES_BIG_ENDIAN && shift > nelt)
11254 for (i = 1; i < nelt; ++i)
11255 if (d->perm[i] != ((shift + i) & mask))
11261 hi = shift < nelt ? d->op1 : d->op0;
11262 lo = shift < nelt ? d->op0 : d->op1;
11266 shift *= GET_MODE_UNIT_SIZE (d->vmode) * BITS_PER_UNIT;
11268 /* We've eliminated the shift 0 case via expand_vec_perm_identity. */
11269 gcc_assert (IN_RANGE (shift, 1, 63));
11271 /* Recall that big-endian elements are numbered starting at the top of
11272 the register. Ideally we'd have a shift-left-pair. But since we
11273 don't, convert to a shift the other direction. */
11274 if (BYTES_BIG_ENDIAN)
11275 shift = 64 - shift;
11277 tmp = gen_reg_rtx (DImode);
11278 hi = gen_lowpart (DImode, hi);
11279 lo = gen_lowpart (DImode, lo);
11280 emit_insn (gen_shrp (tmp, hi, lo, GEN_INT (shift)));
11282 emit_move_insn (d->target, gen_lowpart (d->vmode, tmp));
11286 /* Try to instantiate D in a single instruction. */
11289 expand_vec_perm_1 (struct expand_vec_perm_d *d)
11291 unsigned i, nelt = d->nelt;
11292 unsigned char perm2[MAX_VECT_LEN];
11294 /* Try single-operand selections. */
11295 if (d->one_operand_p)
11297 if (expand_vec_perm_identity (d))
11299 if (expand_vselect (d->target, d->op0, d->perm, nelt))
11303 /* Try two operand selections. */
11304 if (expand_vselect_vconcat (d->target, d->op0, d->op1, d->perm, nelt))
11307 /* Recognize interleave style patterns with reversed operands. */
11308 if (!d->one_operand_p)
11310 for (i = 0; i < nelt; ++i)
11312 unsigned e = d->perm[i];
11320 if (expand_vselect_vconcat (d->target, d->op1, d->op0, perm2, nelt))
11324 if (expand_vec_perm_shrp (d))
11327 /* ??? Look for deposit-like permutations where most of the result
11328 comes from one vector unchanged and the rest comes from a
11329 sequential hunk of the other vector. */
11334 /* Pattern match broadcast permutations. */
11337 expand_vec_perm_broadcast (struct expand_vec_perm_d *d)
11339 unsigned i, elt, nelt = d->nelt;
11340 unsigned char perm2[2];
11344 if (!d->one_operand_p)
11348 for (i = 1; i < nelt; ++i)
11349 if (d->perm[i] != elt)
11356 /* Implementable by interleave. */
11358 perm2[1] = elt + 2;
11359 ok = expand_vselect_vconcat (d->target, d->op0, d->op0, perm2, 2);
11364 /* Implementable by extract + broadcast. */
11365 if (BYTES_BIG_ENDIAN)
11367 elt *= BITS_PER_UNIT;
11368 temp = gen_reg_rtx (DImode);
11369 emit_insn (gen_extzv (temp, gen_lowpart (DImode, d->op0),
11370 GEN_INT (8), GEN_INT (elt)));
11371 emit_insn (gen_mux1_brcst_qi (d->target, gen_lowpart (QImode, temp)));
11375 /* Should have been matched directly by vec_select. */
11377 gcc_unreachable ();
11383 /* A subroutine of ia64_expand_vec_perm_const_1. Try to simplify a
11384 two vector permutation into a single vector permutation by using
11385 an interleave operation to merge the vectors. */
11388 expand_vec_perm_interleave_2 (struct expand_vec_perm_d *d)
11390 struct expand_vec_perm_d dremap, dfinal;
11391 unsigned char remap[2 * MAX_VECT_LEN];
11392 unsigned contents, i, nelt, nelt2;
11393 unsigned h0, h1, h2, h3;
11397 if (d->one_operand_p)
11403 /* Examine from whence the elements come. */
11405 for (i = 0; i < nelt; ++i)
11406 contents |= 1u << d->perm[i];
11408 memset (remap, 0xff, sizeof (remap));
11411 h0 = (1u << nelt2) - 1;
11414 h3 = h0 << (nelt + nelt2);
11416 if ((contents & (h0 | h2)) == contents) /* punpck even halves */
11418 for (i = 0; i < nelt; ++i)
11420 unsigned which = i / 2 + (i & 1 ? nelt : 0);
11422 dremap.perm[i] = which;
11425 else if ((contents & (h1 | h3)) == contents) /* punpck odd halves */
11427 for (i = 0; i < nelt; ++i)
11429 unsigned which = i / 2 + nelt2 + (i & 1 ? nelt : 0);
11431 dremap.perm[i] = which;
11434 else if ((contents & 0x5555) == contents) /* mix even elements */
11436 for (i = 0; i < nelt; ++i)
11438 unsigned which = (i & ~1) + (i & 1 ? nelt : 0);
11440 dremap.perm[i] = which;
11443 else if ((contents & 0xaaaa) == contents) /* mix odd elements */
11445 for (i = 0; i < nelt; ++i)
11447 unsigned which = (i | 1) + (i & 1 ? nelt : 0);
11449 dremap.perm[i] = which;
11452 else if (floor_log2 (contents) - ctz_hwi (contents) < (int)nelt) /* shrp */
11454 unsigned shift = ctz_hwi (contents);
11455 for (i = 0; i < nelt; ++i)
11457 unsigned which = (i + shift) & (2 * nelt - 1);
11459 dremap.perm[i] = which;
11465 /* Use the remapping array set up above to move the elements from their
11466 swizzled locations into their final destinations. */
11468 for (i = 0; i < nelt; ++i)
11470 unsigned e = remap[d->perm[i]];
11471 gcc_assert (e < nelt);
11472 dfinal.perm[i] = e;
11474 dfinal.op0 = gen_reg_rtx (dfinal.vmode);
11475 dfinal.op1 = dfinal.op0;
11476 dfinal.one_operand_p = true;
11477 dremap.target = dfinal.op0;
11479 /* Test if the final remap can be done with a single insn. For V4HImode
11480 this *will* succeed. For V8QImode or V2SImode it may not. */
11482 ok = expand_vec_perm_1 (&dfinal);
11483 seq = get_insns ();
11490 ok = expand_vec_perm_1 (&dremap);
11497 /* A subroutine of ia64_expand_vec_perm_const_1. Emit a full V4HImode
11498 constant permutation via two mux2 and a merge. */
11501 expand_vec_perm_v4hi_5 (struct expand_vec_perm_d *d)
11503 unsigned char perm2[4];
11506 rtx t0, t1, mask, x;
11509 if (d->vmode != V4HImode || d->one_operand_p)
11514 for (i = 0; i < 4; ++i)
11516 perm2[i] = d->perm[i] & 3;
11517 rmask[i] = (d->perm[i] & 4 ? const0_rtx : constm1_rtx);
11519 mask = gen_rtx_CONST_VECTOR (V4HImode, gen_rtvec_v (4, rmask));
11520 mask = force_reg (V4HImode, mask);
11522 t0 = gen_reg_rtx (V4HImode);
11523 t1 = gen_reg_rtx (V4HImode);
11525 ok = expand_vselect (t0, d->op0, perm2, 4);
11527 ok = expand_vselect (t1, d->op1, perm2, 4);
11530 x = gen_rtx_AND (V4HImode, mask, t0);
11531 emit_insn (gen_rtx_SET (VOIDmode, t0, x));
11533 x = gen_rtx_NOT (V4HImode, mask);
11534 x = gen_rtx_AND (V4HImode, x, t1);
11535 emit_insn (gen_rtx_SET (VOIDmode, t1, x));
11537 x = gen_rtx_IOR (V4HImode, t0, t1);
11538 emit_insn (gen_rtx_SET (VOIDmode, d->target, x));
11543 /* The guts of ia64_expand_vec_perm_const, also used by the ok hook.
11544 With all of the interface bits taken care of, perform the expansion
11545 in D and return true on success. */
11548 ia64_expand_vec_perm_const_1 (struct expand_vec_perm_d *d)
11550 if (expand_vec_perm_1 (d))
11552 if (expand_vec_perm_broadcast (d))
11554 if (expand_vec_perm_interleave_2 (d))
11556 if (expand_vec_perm_v4hi_5 (d))
11562 ia64_expand_vec_perm_const (rtx operands[4])
11564 struct expand_vec_perm_d d;
11565 unsigned char perm[MAX_VECT_LEN];
11566 int i, nelt, which;
11569 d.target = operands[0];
11570 d.op0 = operands[1];
11571 d.op1 = operands[2];
11574 d.vmode = GET_MODE (d.target);
11575 gcc_assert (VECTOR_MODE_P (d.vmode));
11576 d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
11577 d.testing_p = false;
11579 gcc_assert (GET_CODE (sel) == CONST_VECTOR);
11580 gcc_assert (XVECLEN (sel, 0) == nelt);
11581 gcc_checking_assert (sizeof (d.perm) == sizeof (perm));
11583 for (i = which = 0; i < nelt; ++i)
11585 rtx e = XVECEXP (sel, 0, i);
11586 int ei = INTVAL (e) & (2 * nelt - 1);
11588 which |= (ei < nelt ? 1 : 2);
11599 if (!rtx_equal_p (d.op0, d.op1))
11601 d.one_operand_p = false;
11605 /* The elements of PERM do not suggest that only the first operand
11606 is used, but both operands are identical. Allow easier matching
11607 of the permutation by folding the permutation into the single
11609 for (i = 0; i < nelt; ++i)
11610 if (d.perm[i] >= nelt)
11616 d.one_operand_p = true;
11620 for (i = 0; i < nelt; ++i)
11623 d.one_operand_p = true;
11627 if (ia64_expand_vec_perm_const_1 (&d))
11630 /* If the mask says both arguments are needed, but they are the same,
11631 the above tried to expand with one_operand_p true. If that didn't
11632 work, retry with one_operand_p false, as that's what we used in _ok. */
11633 if (which == 3 && d.one_operand_p)
11635 memcpy (d.perm, perm, sizeof (perm));
11636 d.one_operand_p = false;
11637 return ia64_expand_vec_perm_const_1 (&d);
11643 /* Implement targetm.vectorize.vec_perm_const_ok. */
11646 ia64_vectorize_vec_perm_const_ok (enum machine_mode vmode,
11647 const unsigned char *sel)
11649 struct expand_vec_perm_d d;
11650 unsigned int i, nelt, which;
11654 d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
11655 d.testing_p = true;
11657 /* Extract the values from the vector CST into the permutation
11659 memcpy (d.perm, sel, nelt);
11660 for (i = which = 0; i < nelt; ++i)
11662 unsigned char e = d.perm[i];
11663 gcc_assert (e < 2 * nelt);
11664 which |= (e < nelt ? 1 : 2);
11667 /* For all elements from second vector, fold the elements to first. */
11669 for (i = 0; i < nelt; ++i)
11672 /* Check whether the mask can be applied to the vector type. */
11673 d.one_operand_p = (which != 3);
11675 /* Otherwise we have to go through the motions and see if we can
11676 figure out how to generate the requested permutation. */
11677 d.target = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 1);
11678 d.op1 = d.op0 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 2);
11679 if (!d.one_operand_p)
11680 d.op1 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 3);
11683 ret = ia64_expand_vec_perm_const_1 (&d);
11690 ia64_expand_vec_setv2sf (rtx operands[3])
11692 struct expand_vec_perm_d d;
11693 unsigned int which;
11696 d.target = operands[0];
11697 d.op0 = operands[0];
11698 d.op1 = gen_reg_rtx (V2SFmode);
11699 d.vmode = V2SFmode;
11701 d.one_operand_p = false;
11702 d.testing_p = false;
11704 which = INTVAL (operands[2]);
11705 gcc_assert (which <= 1);
11706 d.perm[0] = 1 - which;
11707 d.perm[1] = which + 2;
11709 emit_insn (gen_fpack (d.op1, operands[1], CONST0_RTX (SFmode)));
11711 ok = ia64_expand_vec_perm_const_1 (&d);
11716 ia64_expand_vec_perm_even_odd (rtx target, rtx op0, rtx op1, int odd)
11718 struct expand_vec_perm_d d;
11719 enum machine_mode vmode = GET_MODE (target);
11720 unsigned int i, nelt = GET_MODE_NUNITS (vmode);
11728 d.one_operand_p = false;
11729 d.testing_p = false;
11731 for (i = 0; i < nelt; ++i)
11732 d.perm[i] = i * 2 + odd;
11734 ok = ia64_expand_vec_perm_const_1 (&d);
11738 #include "gt-ia64.h"