1 /* Copyright (C) 2002, 2003 Free Software Foundation, Inc.
3 This file is part of GNU CC.
5 GNU CC is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2, or (at your option)
10 GNU CC is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with GNU CC; see the file COPYING. If not, write to
17 the Free Software Foundation, 59 Temple Place - Suite 330,
18 Boston, MA 02111-1307, USA. */
20 /* As a special exception, if you include this header file into source
21 files compiled by GCC, this header file does not by itself cause
22 the resulting executable to be covered by the GNU General Public
23 License. This exception does not however invalidate any other
24 reasons why the executable file might be covered by the GNU General
27 /* Implemented from the specification included in the Intel C++ Compiler
28 User Guide and Reference, version 8.0. */
30 #ifndef _XMMINTRIN_H_INCLUDED
31 #define _XMMINTRIN_H_INCLUDED
34 # error "SSE instruction set not enabled"
37 /* We need type definitions from the MMX header file. */
40 /* The data type intended for user use. */
41 typedef int __m128 __attribute__ ((__mode__(__V4SF__)));
43 /* Internal data types for implementing the intrinsics. */
44 typedef int __v4sf __attribute__ ((__mode__(__V4SF__)));
45 typedef int __v4si __attribute__ ((__mode__(__V4SI__)));
47 /* Create a selector for use with the SHUFPS instruction. */
48 #define _MM_SHUFFLE(fp3,fp2,fp1,fp0) \
49 (((fp3) << 6) | ((fp2) << 4) | ((fp1) << 2) | (fp0))
51 /* Constants for use with _mm_prefetch. */
60 /* Bits in the MXCSR. */
61 #define _MM_EXCEPT_MASK 0x003f
62 #define _MM_EXCEPT_INVALID 0x0001
63 #define _MM_EXCEPT_DENORM 0x0002
64 #define _MM_EXCEPT_DIV_ZERO 0x0004
65 #define _MM_EXCEPT_OVERFLOW 0x0008
66 #define _MM_EXCEPT_UNDERFLOW 0x0010
67 #define _MM_EXCEPT_INEXACT 0x0020
69 #define _MM_MASK_MASK 0x1f80
70 #define _MM_MASK_INVALID 0x0080
71 #define _MM_MASK_DENORM 0x0100
72 #define _MM_MASK_DIV_ZERO 0x0200
73 #define _MM_MASK_OVERFLOW 0x0400
74 #define _MM_MASK_UNDERFLOW 0x0800
75 #define _MM_MASK_INEXACT 0x1000
77 #define _MM_ROUND_MASK 0x6000
78 #define _MM_ROUND_NEAREST 0x0000
79 #define _MM_ROUND_DOWN 0x2000
80 #define _MM_ROUND_UP 0x4000
81 #define _MM_ROUND_TOWARD_ZERO 0x6000
83 #define _MM_FLUSH_ZERO_MASK 0x8000
84 #define _MM_FLUSH_ZERO_ON 0x8000
85 #define _MM_FLUSH_ZERO_OFF 0x0000
87 /* Perform the respective operation on the lower SPFP (single-precision
88 floating-point) values of A and B; the upper three SPFP values are
89 passed through from A. */
91 static __inline __m128
92 _mm_add_ss (__m128 __A, __m128 __B)
94 return (__m128) __builtin_ia32_addss ((__v4sf)__A, (__v4sf)__B);
97 static __inline __m128
98 _mm_sub_ss (__m128 __A, __m128 __B)
100 return (__m128) __builtin_ia32_subss ((__v4sf)__A, (__v4sf)__B);
103 static __inline __m128
104 _mm_mul_ss (__m128 __A, __m128 __B)
106 return (__m128) __builtin_ia32_mulss ((__v4sf)__A, (__v4sf)__B);
109 static __inline __m128
110 _mm_div_ss (__m128 __A, __m128 __B)
112 return (__m128) __builtin_ia32_divss ((__v4sf)__A, (__v4sf)__B);
115 static __inline __m128
116 _mm_sqrt_ss (__m128 __A)
118 return (__m128) __builtin_ia32_sqrtss ((__v4sf)__A);
121 static __inline __m128
122 _mm_rcp_ss (__m128 __A)
124 return (__m128) __builtin_ia32_rcpss ((__v4sf)__A);
127 static __inline __m128
128 _mm_rsqrt_ss (__m128 __A)
130 return (__m128) __builtin_ia32_rsqrtss ((__v4sf)__A);
133 static __inline __m128
134 _mm_min_ss (__m128 __A, __m128 __B)
136 return (__m128) __builtin_ia32_minss ((__v4sf)__A, (__v4sf)__B);
139 static __inline __m128
140 _mm_max_ss (__m128 __A, __m128 __B)
142 return (__m128) __builtin_ia32_maxss ((__v4sf)__A, (__v4sf)__B);
145 /* Perform the respective operation on the four SPFP values in A and B. */
147 static __inline __m128
148 _mm_add_ps (__m128 __A, __m128 __B)
150 return (__m128) __builtin_ia32_addps ((__v4sf)__A, (__v4sf)__B);
153 static __inline __m128
154 _mm_sub_ps (__m128 __A, __m128 __B)
156 return (__m128) __builtin_ia32_subps ((__v4sf)__A, (__v4sf)__B);
159 static __inline __m128
160 _mm_mul_ps (__m128 __A, __m128 __B)
162 return (__m128) __builtin_ia32_mulps ((__v4sf)__A, (__v4sf)__B);
165 static __inline __m128
166 _mm_div_ps (__m128 __A, __m128 __B)
168 return (__m128) __builtin_ia32_divps ((__v4sf)__A, (__v4sf)__B);
171 static __inline __m128
172 _mm_sqrt_ps (__m128 __A)
174 return (__m128) __builtin_ia32_sqrtps ((__v4sf)__A);
177 static __inline __m128
178 _mm_rcp_ps (__m128 __A)
180 return (__m128) __builtin_ia32_rcpps ((__v4sf)__A);
183 static __inline __m128
184 _mm_rsqrt_ps (__m128 __A)
186 return (__m128) __builtin_ia32_rsqrtps ((__v4sf)__A);
189 static __inline __m128
190 _mm_min_ps (__m128 __A, __m128 __B)
192 return (__m128) __builtin_ia32_minps ((__v4sf)__A, (__v4sf)__B);
195 static __inline __m128
196 _mm_max_ps (__m128 __A, __m128 __B)
198 return (__m128) __builtin_ia32_maxps ((__v4sf)__A, (__v4sf)__B);
201 /* Perform logical bit-wise operations on 128-bit values. */
203 static __inline __m128
204 _mm_and_ps (__m128 __A, __m128 __B)
206 return __builtin_ia32_andps (__A, __B);
209 static __inline __m128
210 _mm_andnot_ps (__m128 __A, __m128 __B)
212 return __builtin_ia32_andnps (__A, __B);
215 static __inline __m128
216 _mm_or_ps (__m128 __A, __m128 __B)
218 return __builtin_ia32_orps (__A, __B);
221 static __inline __m128
222 _mm_xor_ps (__m128 __A, __m128 __B)
224 return __builtin_ia32_xorps (__A, __B);
227 /* Perform a comparison on the lower SPFP values of A and B. If the
228 comparison is true, place a mask of all ones in the result, otherwise a
229 mask of zeros. The upper three SPFP values are passed through from A. */
231 static __inline __m128
232 _mm_cmpeq_ss (__m128 __A, __m128 __B)
234 return (__m128) __builtin_ia32_cmpeqss ((__v4sf)__A, (__v4sf)__B);
237 static __inline __m128
238 _mm_cmplt_ss (__m128 __A, __m128 __B)
240 return (__m128) __builtin_ia32_cmpltss ((__v4sf)__A, (__v4sf)__B);
243 static __inline __m128
244 _mm_cmple_ss (__m128 __A, __m128 __B)
246 return (__m128) __builtin_ia32_cmpless ((__v4sf)__A, (__v4sf)__B);
249 static __inline __m128
250 _mm_cmpgt_ss (__m128 __A, __m128 __B)
252 return (__m128) __builtin_ia32_movss ((__v4sf) __A,
254 __builtin_ia32_cmpltss ((__v4sf) __B,
259 static __inline __m128
260 _mm_cmpge_ss (__m128 __A, __m128 __B)
262 return (__m128) __builtin_ia32_movss ((__v4sf) __A,
264 __builtin_ia32_cmpless ((__v4sf) __B,
269 static __inline __m128
270 _mm_cmpneq_ss (__m128 __A, __m128 __B)
272 return (__m128) __builtin_ia32_cmpneqss ((__v4sf)__A, (__v4sf)__B);
275 static __inline __m128
276 _mm_cmpnlt_ss (__m128 __A, __m128 __B)
278 return (__m128) __builtin_ia32_cmpnltss ((__v4sf)__A, (__v4sf)__B);
281 static __inline __m128
282 _mm_cmpnle_ss (__m128 __A, __m128 __B)
284 return (__m128) __builtin_ia32_cmpnless ((__v4sf)__A, (__v4sf)__B);
287 static __inline __m128
288 _mm_cmpngt_ss (__m128 __A, __m128 __B)
290 return (__m128) __builtin_ia32_movss ((__v4sf) __A,
292 __builtin_ia32_cmpnltss ((__v4sf) __B,
297 static __inline __m128
298 _mm_cmpnge_ss (__m128 __A, __m128 __B)
300 return (__m128) __builtin_ia32_movss ((__v4sf) __A,
302 __builtin_ia32_cmpnless ((__v4sf) __B,
307 static __inline __m128
308 _mm_cmpord_ss (__m128 __A, __m128 __B)
310 return (__m128) __builtin_ia32_cmpordss ((__v4sf)__A, (__v4sf)__B);
313 static __inline __m128
314 _mm_cmpunord_ss (__m128 __A, __m128 __B)
316 return (__m128) __builtin_ia32_cmpunordss ((__v4sf)__A, (__v4sf)__B);
319 /* Perform a comparison on the four SPFP values of A and B. For each
320 element, if the comparison is true, place a mask of all ones in the
321 result, otherwise a mask of zeros. */
323 static __inline __m128
324 _mm_cmpeq_ps (__m128 __A, __m128 __B)
326 return (__m128) __builtin_ia32_cmpeqps ((__v4sf)__A, (__v4sf)__B);
329 static __inline __m128
330 _mm_cmplt_ps (__m128 __A, __m128 __B)
332 return (__m128) __builtin_ia32_cmpltps ((__v4sf)__A, (__v4sf)__B);
335 static __inline __m128
336 _mm_cmple_ps (__m128 __A, __m128 __B)
338 return (__m128) __builtin_ia32_cmpleps ((__v4sf)__A, (__v4sf)__B);
341 static __inline __m128
342 _mm_cmpgt_ps (__m128 __A, __m128 __B)
344 return (__m128) __builtin_ia32_cmpgtps ((__v4sf)__A, (__v4sf)__B);
347 static __inline __m128
348 _mm_cmpge_ps (__m128 __A, __m128 __B)
350 return (__m128) __builtin_ia32_cmpgeps ((__v4sf)__A, (__v4sf)__B);
353 static __inline __m128
354 _mm_cmpneq_ps (__m128 __A, __m128 __B)
356 return (__m128) __builtin_ia32_cmpneqps ((__v4sf)__A, (__v4sf)__B);
359 static __inline __m128
360 _mm_cmpnlt_ps (__m128 __A, __m128 __B)
362 return (__m128) __builtin_ia32_cmpnltps ((__v4sf)__A, (__v4sf)__B);
365 static __inline __m128
366 _mm_cmpnle_ps (__m128 __A, __m128 __B)
368 return (__m128) __builtin_ia32_cmpnleps ((__v4sf)__A, (__v4sf)__B);
371 static __inline __m128
372 _mm_cmpngt_ps (__m128 __A, __m128 __B)
374 return (__m128) __builtin_ia32_cmpngtps ((__v4sf)__A, (__v4sf)__B);
377 static __inline __m128
378 _mm_cmpnge_ps (__m128 __A, __m128 __B)
380 return (__m128) __builtin_ia32_cmpngeps ((__v4sf)__A, (__v4sf)__B);
383 static __inline __m128
384 _mm_cmpord_ps (__m128 __A, __m128 __B)
386 return (__m128) __builtin_ia32_cmpordps ((__v4sf)__A, (__v4sf)__B);
389 static __inline __m128
390 _mm_cmpunord_ps (__m128 __A, __m128 __B)
392 return (__m128) __builtin_ia32_cmpunordps ((__v4sf)__A, (__v4sf)__B);
395 /* Compare the lower SPFP values of A and B and return 1 if true
399 _mm_comieq_ss (__m128 __A, __m128 __B)
401 return __builtin_ia32_comieq ((__v4sf)__A, (__v4sf)__B);
405 _mm_comilt_ss (__m128 __A, __m128 __B)
407 return __builtin_ia32_comilt ((__v4sf)__A, (__v4sf)__B);
411 _mm_comile_ss (__m128 __A, __m128 __B)
413 return __builtin_ia32_comile ((__v4sf)__A, (__v4sf)__B);
417 _mm_comigt_ss (__m128 __A, __m128 __B)
419 return __builtin_ia32_comigt ((__v4sf)__A, (__v4sf)__B);
423 _mm_comige_ss (__m128 __A, __m128 __B)
425 return __builtin_ia32_comige ((__v4sf)__A, (__v4sf)__B);
429 _mm_comineq_ss (__m128 __A, __m128 __B)
431 return __builtin_ia32_comineq ((__v4sf)__A, (__v4sf)__B);
435 _mm_ucomieq_ss (__m128 __A, __m128 __B)
437 return __builtin_ia32_ucomieq ((__v4sf)__A, (__v4sf)__B);
441 _mm_ucomilt_ss (__m128 __A, __m128 __B)
443 return __builtin_ia32_ucomilt ((__v4sf)__A, (__v4sf)__B);
447 _mm_ucomile_ss (__m128 __A, __m128 __B)
449 return __builtin_ia32_ucomile ((__v4sf)__A, (__v4sf)__B);
453 _mm_ucomigt_ss (__m128 __A, __m128 __B)
455 return __builtin_ia32_ucomigt ((__v4sf)__A, (__v4sf)__B);
459 _mm_ucomige_ss (__m128 __A, __m128 __B)
461 return __builtin_ia32_ucomige ((__v4sf)__A, (__v4sf)__B);
465 _mm_ucomineq_ss (__m128 __A, __m128 __B)
467 return __builtin_ia32_ucomineq ((__v4sf)__A, (__v4sf)__B);
470 /* Convert the lower SPFP value to a 32-bit integer according to the current
473 _mm_cvtss_si32 (__m128 __A)
475 return __builtin_ia32_cvtss2si ((__v4sf) __A);
479 _mm_cvt_ss2si (__m128 __A)
481 return _mm_cvtss_si32 (__A);
485 /* Convert the lower SPFP value to a 32-bit integer according to the current
487 static __inline long long
488 _mm_cvtss_si64x (__m128 __A)
490 return __builtin_ia32_cvtss2si64 ((__v4sf) __A);
494 /* Convert the two lower SPFP values to 32-bit integers according to the
495 current rounding mode. Return the integers in packed form. */
496 static __inline __m64
497 _mm_cvtps_pi32 (__m128 __A)
499 return (__m64) __builtin_ia32_cvtps2pi ((__v4sf) __A);
502 static __inline __m64
503 _mm_cvt_ps2pi (__m128 __A)
505 return _mm_cvtps_pi32 (__A);
508 /* Truncate the lower SPFP value to a 32-bit integer. */
510 _mm_cvttss_si32 (__m128 __A)
512 return __builtin_ia32_cvttss2si ((__v4sf) __A);
516 _mm_cvtt_ss2si (__m128 __A)
518 return _mm_cvttss_si32 (__A);
522 /* Truncate the lower SPFP value to a 32-bit integer. */
523 static __inline long long
524 _mm_cvttss_si64x (__m128 __A)
526 return __builtin_ia32_cvttss2si64 ((__v4sf) __A);
530 /* Truncate the two lower SPFP values to 32-bit integers. Return the
531 integers in packed form. */
532 static __inline __m64
533 _mm_cvttps_pi32 (__m128 __A)
535 return (__m64) __builtin_ia32_cvttps2pi ((__v4sf) __A);
538 static __inline __m64
539 _mm_cvtt_ps2pi (__m128 __A)
541 return _mm_cvttps_pi32 (__A);
544 /* Convert B to a SPFP value and insert it as element zero in A. */
545 static __inline __m128
546 _mm_cvtsi32_ss (__m128 __A, int __B)
548 return (__m128) __builtin_ia32_cvtsi2ss ((__v4sf) __A, __B);
551 static __inline __m128
552 _mm_cvt_si2ss (__m128 __A, int __B)
554 return _mm_cvtsi32_ss (__A, __B);
558 /* Convert B to a SPFP value and insert it as element zero in A. */
559 static __inline __m128
560 _mm_cvtsi64x_ss (__m128 __A, long long __B)
562 return (__m128) __builtin_ia32_cvtsi642ss ((__v4sf) __A, __B);
566 /* Convert the two 32-bit values in B to SPFP form and insert them
567 as the two lower elements in A. */
568 static __inline __m128
569 _mm_cvtpi32_ps (__m128 __A, __m64 __B)
571 return (__m128) __builtin_ia32_cvtpi2ps ((__v4sf) __A, (__v2si)__B);
574 static __inline __m128
575 _mm_cvt_pi2ps (__m128 __A, __m64 __B)
577 return _mm_cvtpi32_ps (__A, __B);
580 /* Convert the four signed 16-bit values in A to SPFP form. */
581 static __inline __m128
582 _mm_cvtpi16_ps (__m64 __A)
585 __v2si __hisi, __losi;
588 /* This comparison against zero gives us a mask that can be used to
589 fill in the missing sign bits in the unpack operations below, so
590 that we get signed values after unpacking. */
591 __sign = (__v4hi) __builtin_ia32_mmx_zero ();
592 __sign = __builtin_ia32_pcmpgtw (__sign, (__v4hi)__A);
594 /* Convert the four words to doublewords. */
595 __hisi = (__v2si) __builtin_ia32_punpckhwd ((__v4hi)__A, __sign);
596 __losi = (__v2si) __builtin_ia32_punpcklwd ((__v4hi)__A, __sign);
598 /* Convert the doublewords to floating point two at a time. */
599 __r = (__v4sf) __builtin_ia32_setzerops ();
600 __r = __builtin_ia32_cvtpi2ps (__r, __hisi);
601 __r = __builtin_ia32_movlhps (__r, __r);
602 __r = __builtin_ia32_cvtpi2ps (__r, __losi);
607 /* Convert the four unsigned 16-bit values in A to SPFP form. */
608 static __inline __m128
609 _mm_cvtpu16_ps (__m64 __A)
611 __v4hi __zero = (__v4hi) __builtin_ia32_mmx_zero ();
612 __v2si __hisi, __losi;
615 /* Convert the four words to doublewords. */
616 __hisi = (__v2si) __builtin_ia32_punpckhwd ((__v4hi)__A, __zero);
617 __losi = (__v2si) __builtin_ia32_punpcklwd ((__v4hi)__A, __zero);
619 /* Convert the doublewords to floating point two at a time. */
620 __r = (__v4sf) __builtin_ia32_setzerops ();
621 __r = __builtin_ia32_cvtpi2ps (__r, __hisi);
622 __r = __builtin_ia32_movlhps (__r, __r);
623 __r = __builtin_ia32_cvtpi2ps (__r, __losi);
628 /* Convert the low four signed 8-bit values in A to SPFP form. */
629 static __inline __m128
630 _mm_cvtpi8_ps (__m64 __A)
634 /* This comparison against zero gives us a mask that can be used to
635 fill in the missing sign bits in the unpack operations below, so
636 that we get signed values after unpacking. */
637 __sign = (__v8qi) __builtin_ia32_mmx_zero ();
638 __sign = __builtin_ia32_pcmpgtb (__sign, (__v8qi)__A);
640 /* Convert the four low bytes to words. */
641 __A = (__m64) __builtin_ia32_punpcklbw ((__v8qi)__A, __sign);
643 return _mm_cvtpi16_ps(__A);
646 /* Convert the low four unsigned 8-bit values in A to SPFP form. */
647 static __inline __m128
648 _mm_cvtpu8_ps(__m64 __A)
650 __v8qi __zero = (__v8qi) __builtin_ia32_mmx_zero ();
651 __A = (__m64) __builtin_ia32_punpcklbw ((__v8qi)__A, __zero);
652 return _mm_cvtpu16_ps(__A);
655 /* Convert the four signed 32-bit values in A and B to SPFP form. */
656 static __inline __m128
657 _mm_cvtpi32x2_ps(__m64 __A, __m64 __B)
659 __v4sf __zero = (__v4sf) __builtin_ia32_setzerops ();
660 __v4sf __sfa = __builtin_ia32_cvtpi2ps (__zero, (__v2si)__A);
661 __v4sf __sfb = __builtin_ia32_cvtpi2ps (__zero, (__v2si)__B);
662 return (__m128) __builtin_ia32_movlhps (__sfa, __sfb);
665 /* Convert the four SPFP values in A to four signed 16-bit integers. */
666 static __inline __m64
667 _mm_cvtps_pi16(__m128 __A)
669 __v4sf __hisf = (__v4sf)__A;
670 __v4sf __losf = __builtin_ia32_movhlps (__hisf, __hisf);
671 __v2si __hisi = __builtin_ia32_cvtps2pi (__hisf);
672 __v2si __losi = __builtin_ia32_cvtps2pi (__losf);
673 return (__m64) __builtin_ia32_packssdw (__hisi, __losi);
676 /* Convert the four SPFP values in A to four signed 8-bit integers. */
677 static __inline __m64
678 _mm_cvtps_pi8(__m128 __A)
680 __v4hi __tmp = (__v4hi) _mm_cvtps_pi16 (__A);
681 __v4hi __zero = (__v4hi) __builtin_ia32_mmx_zero ();
682 return (__m64) __builtin_ia32_packsswb (__tmp, __zero);
685 /* Selects four specific SPFP values from A and B based on MASK. */
687 static __inline __m128
688 _mm_shuffle_ps (__m128 __A, __m128 __B, int __mask)
690 return (__m128) __builtin_ia32_shufps ((__v4sf)__A, (__v4sf)__B, __mask);
693 #define _mm_shuffle_ps(A, B, MASK) \
694 ((__m128) __builtin_ia32_shufps ((__v4sf)(A), (__v4sf)(B), (MASK)))
698 /* Selects and interleaves the upper two SPFP values from A and B. */
699 static __inline __m128
700 _mm_unpackhi_ps (__m128 __A, __m128 __B)
702 return (__m128) __builtin_ia32_unpckhps ((__v4sf)__A, (__v4sf)__B);
705 /* Selects and interleaves the lower two SPFP values from A and B. */
706 static __inline __m128
707 _mm_unpacklo_ps (__m128 __A, __m128 __B)
709 return (__m128) __builtin_ia32_unpcklps ((__v4sf)__A, (__v4sf)__B);
712 /* Sets the upper two SPFP values with 64-bits of data loaded from P;
713 the lower two values are passed through from A. */
714 static __inline __m128
715 _mm_loadh_pi (__m128 __A, __m64 const *__P)
717 return (__m128) __builtin_ia32_loadhps ((__v4sf)__A, (__v2si *)__P);
720 /* Stores the upper two SPFP values of A into P. */
722 _mm_storeh_pi (__m64 *__P, __m128 __A)
724 __builtin_ia32_storehps ((__v2si *)__P, (__v4sf)__A);
727 /* Moves the upper two values of B into the lower two values of A. */
728 static __inline __m128
729 _mm_movehl_ps (__m128 __A, __m128 __B)
731 return (__m128) __builtin_ia32_movhlps ((__v4sf)__A, (__v4sf)__B);
734 /* Moves the lower two values of B into the upper two values of A. */
735 static __inline __m128
736 _mm_movelh_ps (__m128 __A, __m128 __B)
738 return (__m128) __builtin_ia32_movlhps ((__v4sf)__A, (__v4sf)__B);
741 /* Sets the lower two SPFP values with 64-bits of data loaded from P;
742 the upper two values are passed through from A. */
743 static __inline __m128
744 _mm_loadl_pi (__m128 __A, __m64 const *__P)
746 return (__m128) __builtin_ia32_loadlps ((__v4sf)__A, (__v2si *)__P);
749 /* Stores the lower two SPFP values of A into P. */
751 _mm_storel_pi (__m64 *__P, __m128 __A)
753 __builtin_ia32_storelps ((__v2si *)__P, (__v4sf)__A);
756 /* Creates a 4-bit mask from the most significant bits of the SPFP values. */
758 _mm_movemask_ps (__m128 __A)
760 return __builtin_ia32_movmskps ((__v4sf)__A);
763 /* Return the contents of the control register. */
764 static __inline unsigned int
767 return __builtin_ia32_stmxcsr ();
770 /* Read exception bits from the control register. */
771 static __inline unsigned int
772 _MM_GET_EXCEPTION_STATE (void)
774 return _mm_getcsr() & _MM_EXCEPT_MASK;
777 static __inline unsigned int
778 _MM_GET_EXCEPTION_MASK (void)
780 return _mm_getcsr() & _MM_MASK_MASK;
783 static __inline unsigned int
784 _MM_GET_ROUNDING_MODE (void)
786 return _mm_getcsr() & _MM_ROUND_MASK;
789 static __inline unsigned int
790 _MM_GET_FLUSH_ZERO_MODE (void)
792 return _mm_getcsr() & _MM_FLUSH_ZERO_MASK;
795 /* Set the control register to I. */
797 _mm_setcsr (unsigned int __I)
799 __builtin_ia32_ldmxcsr (__I);
802 /* Set exception bits in the control register. */
804 _MM_SET_EXCEPTION_STATE(unsigned int __mask)
806 _mm_setcsr((_mm_getcsr() & ~_MM_EXCEPT_MASK) | __mask);
810 _MM_SET_EXCEPTION_MASK (unsigned int __mask)
812 _mm_setcsr((_mm_getcsr() & ~_MM_MASK_MASK) | __mask);
816 _MM_SET_ROUNDING_MODE (unsigned int __mode)
818 _mm_setcsr((_mm_getcsr() & ~_MM_ROUND_MASK) | __mode);
822 _MM_SET_FLUSH_ZERO_MODE (unsigned int __mode)
824 _mm_setcsr((_mm_getcsr() & ~_MM_FLUSH_ZERO_MASK) | __mode);
827 /* Create a vector with element 0 as *P and the rest zero. */
828 static __inline __m128
829 _mm_load_ss (float const *__P)
831 return (__m128) __builtin_ia32_loadss (__P);
834 /* Create a vector with all four elements equal to *P. */
835 static __inline __m128
836 _mm_load1_ps (float const *__P)
838 __v4sf __tmp = __builtin_ia32_loadss (__P);
839 return (__m128) __builtin_ia32_shufps (__tmp, __tmp, _MM_SHUFFLE (0,0,0,0));
842 static __inline __m128
843 _mm_load_ps1 (float const *__P)
845 return _mm_load1_ps (__P);
848 /* Load four SPFP values from P. The address must be 16-byte aligned. */
849 static __inline __m128
850 _mm_load_ps (float const *__P)
852 return (__m128) __builtin_ia32_loadaps (__P);
855 /* Load four SPFP values from P. The address need not be 16-byte aligned. */
856 static __inline __m128
857 _mm_loadu_ps (float const *__P)
859 return (__m128) __builtin_ia32_loadups (__P);
862 /* Load four SPFP values in reverse order. The address must be aligned. */
863 static __inline __m128
864 _mm_loadr_ps (float const *__P)
866 __v4sf __tmp = __builtin_ia32_loadaps (__P);
867 return (__m128) __builtin_ia32_shufps (__tmp, __tmp, _MM_SHUFFLE (0,1,2,3));
870 /* Create a vector with element 0 as F and the rest zero. */
871 static __inline __m128
872 _mm_set_ss (float __F)
874 return (__m128) __builtin_ia32_loadss (&__F);
877 /* Create a vector with all four elements equal to F. */
878 static __inline __m128
879 _mm_set1_ps (float __F)
881 __v4sf __tmp = __builtin_ia32_loadss (&__F);
882 return (__m128) __builtin_ia32_shufps (__tmp, __tmp, _MM_SHUFFLE (0,0,0,0));
885 static __inline __m128
886 _mm_set_ps1 (float __F)
888 return _mm_set1_ps (__F);
891 /* Create the vector [Z Y X W]. */
892 static __inline __m128
893 _mm_set_ps (float __Z, float __Y, float __X, float __W)
908 /* Create the vector [W X Y Z]. */
909 static __inline __m128
910 _mm_setr_ps (float __Z, float __Y, float __X, float __W)
912 return _mm_set_ps (__W, __X, __Y, __Z);
915 /* Create a vector of zeros. */
916 static __inline __m128
917 _mm_setzero_ps (void)
919 return (__m128) __builtin_ia32_setzerops ();
922 /* Stores the lower SPFP value. */
924 _mm_store_ss (float *__P, __m128 __A)
926 __builtin_ia32_storess (__P, (__v4sf)__A);
929 /* Store the lower SPFP value across four words. */
931 _mm_store1_ps (float *__P, __m128 __A)
933 __v4sf __va = (__v4sf)__A;
934 __v4sf __tmp = __builtin_ia32_shufps (__va, __va, _MM_SHUFFLE (0,0,0,0));
935 __builtin_ia32_storeaps (__P, __tmp);
939 _mm_store_ps1 (float *__P, __m128 __A)
941 _mm_store1_ps (__P, __A);
944 /* Store four SPFP values. The address must be 16-byte aligned. */
946 _mm_store_ps (float *__P, __m128 __A)
948 __builtin_ia32_storeaps (__P, (__v4sf)__A);
951 /* Store four SPFP values. The address need not be 16-byte aligned. */
953 _mm_storeu_ps (float *__P, __m128 __A)
955 __builtin_ia32_storeups (__P, (__v4sf)__A);
958 /* Store four SPFP values in reverse order. The address must be aligned. */
960 _mm_storer_ps (float *__P, __m128 __A)
962 __v4sf __va = (__v4sf)__A;
963 __v4sf __tmp = __builtin_ia32_shufps (__va, __va, _MM_SHUFFLE (0,1,2,3));
964 __builtin_ia32_storeaps (__P, __tmp);
967 /* Sets the low SPFP value of A from the low value of B. */
968 static __inline __m128
969 _mm_move_ss (__m128 __A, __m128 __B)
971 return (__m128) __builtin_ia32_movss ((__v4sf)__A, (__v4sf)__B);
974 /* Extracts one of the four words of A. The selector N must be immediate. */
977 _mm_extract_pi16 (__m64 __A, int __N)
979 return __builtin_ia32_pextrw ((__v4hi)__A, __N);
983 _m_pextrw (__m64 __A, int __N)
985 return _mm_extract_pi16 (__A, __N);
988 #define _mm_extract_pi16(A, N) \
989 __builtin_ia32_pextrw ((__v4hi)(A), (N))
990 #define _m_pextrw(A, N) _mm_extract_pi16((A), (N))
993 /* Inserts word D into one of four words of A. The selector N must be
996 static __inline __m64
997 _mm_insert_pi16 (__m64 __A, int __D, int __N)
999 return (__m64)__builtin_ia32_pinsrw ((__v4hi)__A, __D, __N);
1002 static __inline __m64
1003 _m_pinsrw (__m64 __A, int __D, int __N)
1005 return _mm_insert_pi16 (__A, __D, __N);
1008 #define _mm_insert_pi16(A, D, N) \
1009 ((__m64) __builtin_ia32_pinsrw ((__v4hi)(A), (D), (N)))
1010 #define _m_pinsrw(A, D, N) _mm_insert_pi16((A), (D), (N))
1013 /* Compute the element-wise maximum of signed 16-bit values. */
1014 static __inline __m64
1015 _mm_max_pi16 (__m64 __A, __m64 __B)
1017 return (__m64) __builtin_ia32_pmaxsw ((__v4hi)__A, (__v4hi)__B);
1020 static __inline __m64
1021 _m_pmaxsw (__m64 __A, __m64 __B)
1023 return _mm_max_pi16 (__A, __B);
1026 /* Compute the element-wise maximum of unsigned 8-bit values. */
1027 static __inline __m64
1028 _mm_max_pu8 (__m64 __A, __m64 __B)
1030 return (__m64) __builtin_ia32_pmaxub ((__v8qi)__A, (__v8qi)__B);
1033 static __inline __m64
1034 _m_pmaxub (__m64 __A, __m64 __B)
1036 return _mm_max_pu8 (__A, __B);
1039 /* Compute the element-wise minimum of signed 16-bit values. */
1040 static __inline __m64
1041 _mm_min_pi16 (__m64 __A, __m64 __B)
1043 return (__m64) __builtin_ia32_pminsw ((__v4hi)__A, (__v4hi)__B);
1046 static __inline __m64
1047 _m_pminsw (__m64 __A, __m64 __B)
1049 return _mm_min_pi16 (__A, __B);
1052 /* Compute the element-wise minimum of unsigned 8-bit values. */
1053 static __inline __m64
1054 _mm_min_pu8 (__m64 __A, __m64 __B)
1056 return (__m64) __builtin_ia32_pminub ((__v8qi)__A, (__v8qi)__B);
1059 static __inline __m64
1060 _m_pminub (__m64 __A, __m64 __B)
1062 return _mm_min_pu8 (__A, __B);
1065 /* Create an 8-bit mask of the signs of 8-bit values. */
1067 _mm_movemask_pi8 (__m64 __A)
1069 return __builtin_ia32_pmovmskb ((__v8qi)__A);
1073 _m_pmovmskb (__m64 __A)
1075 return _mm_movemask_pi8 (__A);
1078 /* Multiply four unsigned 16-bit values in A by four unsigned 16-bit values
1079 in B and produce the high 16 bits of the 32-bit results. */
1080 static __inline __m64
1081 _mm_mulhi_pu16 (__m64 __A, __m64 __B)
1083 return (__m64) __builtin_ia32_pmulhuw ((__v4hi)__A, (__v4hi)__B);
1086 static __inline __m64
1087 _m_pmulhuw (__m64 __A, __m64 __B)
1089 return _mm_mulhi_pu16 (__A, __B);
1092 /* Return a combination of the four 16-bit values in A. The selector
1093 must be an immediate. */
1095 static __inline __m64
1096 _mm_shuffle_pi16 (__m64 __A, int __N)
1098 return (__m64) __builtin_ia32_pshufw ((__v4hi)__A, __N);
1101 static __inline __m64
1102 _m_pshufw (__m64 __A, int __N)
1104 return _mm_shuffle_pi16 (__A, __N);
1107 #define _mm_shuffle_pi16(A, N) \
1108 ((__m64) __builtin_ia32_pshufw ((__v4hi)(A), (N)))
1109 #define _m_pshufw(A, N) _mm_shuffle_pi16 ((A), (N))
1112 /* Conditionally store byte elements of A into P. The high bit of each
1113 byte in the selector N determines whether the corresponding byte from
1115 static __inline void
1116 _mm_maskmove_si64 (__m64 __A, __m64 __N, char *__P)
1118 __builtin_ia32_maskmovq ((__v8qi)__A, (__v8qi)__N, __P);
1121 static __inline void
1122 _m_maskmovq (__m64 __A, __m64 __N, char *__P)
1124 _mm_maskmove_si64 (__A, __N, __P);
1127 /* Compute the rounded averages of the unsigned 8-bit values in A and B. */
1128 static __inline __m64
1129 _mm_avg_pu8 (__m64 __A, __m64 __B)
1131 return (__m64) __builtin_ia32_pavgb ((__v8qi)__A, (__v8qi)__B);
1134 static __inline __m64
1135 _m_pavgb (__m64 __A, __m64 __B)
1137 return _mm_avg_pu8 (__A, __B);
1140 /* Compute the rounded averages of the unsigned 16-bit values in A and B. */
1141 static __inline __m64
1142 _mm_avg_pu16 (__m64 __A, __m64 __B)
1144 return (__m64) __builtin_ia32_pavgw ((__v4hi)__A, (__v4hi)__B);
1147 static __inline __m64
1148 _m_pavgw (__m64 __A, __m64 __B)
1150 return _mm_avg_pu16 (__A, __B);
1153 /* Compute the sum of the absolute differences of the unsigned 8-bit
1154 values in A and B. Return the value in the lower 16-bit word; the
1155 upper words are cleared. */
1156 static __inline __m64
1157 _mm_sad_pu8 (__m64 __A, __m64 __B)
1159 return (__m64) __builtin_ia32_psadbw ((__v8qi)__A, (__v8qi)__B);
1162 static __inline __m64
1163 _m_psadbw (__m64 __A, __m64 __B)
1165 return _mm_sad_pu8 (__A, __B);
1168 /* Loads one cache line from address P to a location "closer" to the
1169 processor. The selector I specifies the type of prefetch operation. */
1171 static __inline void
1172 _mm_prefetch (void *__P, enum _mm_hint __I)
1174 __builtin_prefetch (__P, 0, __I);
1177 #define _mm_prefetch(P, I) \
1178 __builtin_prefetch ((P), 0, (I))
1181 /* Stores the data in A to the address P without polluting the caches. */
1182 static __inline void
1183 _mm_stream_pi (__m64 *__P, __m64 __A)
1185 __builtin_ia32_movntq ((unsigned long long *)__P, (unsigned long long)__A);
1188 /* Likewise. The address must be 16-byte aligned. */
1189 static __inline void
1190 _mm_stream_ps (float *__P, __m128 __A)
1192 __builtin_ia32_movntps (__P, (__v4sf)__A);
1195 /* Guarantees that every preceding store is globally visible before
1196 any subsequent store. */
1197 static __inline void
1200 __builtin_ia32_sfence ();
1203 /* The execution of the next instruction is delayed by an implementation
1204 specific amount of time. The instruction does not modify the
1205 architectural state. */
1206 static __inline void
1209 __asm__ __volatile__ ("rep; nop" : : );
1212 /* Transpose the 4x4 matrix composed of row[0-3]. */
1213 #define _MM_TRANSPOSE4_PS(row0, row1, row2, row3) \
1215 __v4sf __r0 = (row0), __r1 = (row1), __r2 = (row2), __r3 = (row3); \
1216 __v4sf __t0 = __builtin_ia32_shufps (__r0, __r1, 0x44); \
1217 __v4sf __t2 = __builtin_ia32_shufps (__r0, __r1, 0xEE); \
1218 __v4sf __t1 = __builtin_ia32_shufps (__r2, __r3, 0x44); \
1219 __v4sf __t3 = __builtin_ia32_shufps (__r2, __r3, 0xEE); \
1220 (row0) = __builtin_ia32_shufps (__t0, __t1, 0x88); \
1221 (row1) = __builtin_ia32_shufps (__t0, __t1, 0xDD); \
1222 (row2) = __builtin_ia32_shufps (__t2, __t3, 0x88); \
1223 (row3) = __builtin_ia32_shufps (__t2, __t3, 0xDD); \
1226 /* For backward source compatibility. */
1227 #include <emmintrin.h>
1229 #endif /* __SSE__ */
1230 #endif /* _XMMINTRIN_H_INCLUDED */