1 ;; Predicate definitions for IA-32 and x86-64.
2 ;; Copyright (C) 2004-2015 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 ;; Return true if OP is either a i387 or SSE fp register.
21 (define_predicate "any_fp_register_operand"
22 (and (match_code "reg")
23 (match_test "ANY_FP_REGNO_P (REGNO (op))")))
25 ;; Return true if OP is an i387 fp register.
26 (define_predicate "fp_register_operand"
27 (and (match_code "reg")
28 (match_test "STACK_REGNO_P (REGNO (op))")))
30 ;; Return true if OP is a non-fp register_operand.
31 (define_predicate "register_and_not_any_fp_reg_operand"
32 (and (match_code "reg")
33 (not (match_test "ANY_FP_REGNO_P (REGNO (op))"))))
35 ;; True if the operand is a GENERAL class register.
36 (define_predicate "general_reg_operand"
37 (and (match_code "reg")
38 (match_test "GENERAL_REGNO_P (REGNO (op))")))
40 ;; True if the operand is a nonimmediate operand with GENERAL class register.
41 (define_predicate "nonimmediate_gr_operand"
42 (if_then_else (match_code "reg")
43 (match_test "GENERAL_REGNO_P (REGNO (op))")
44 (match_operand 0 "nonimmediate_operand")))
46 ;; Return true if OP is a register operand other than an i387 fp register.
47 (define_predicate "register_and_not_fp_reg_operand"
48 (and (match_code "reg")
49 (not (match_test "STACK_REGNO_P (REGNO (op))"))))
51 ;; True if the operand is an MMX register.
52 (define_predicate "mmx_reg_operand"
53 (and (match_code "reg")
54 (match_test "MMX_REGNO_P (REGNO (op))")))
56 ;; True if the operand is an SSE register.
57 (define_predicate "sse_reg_operand"
58 (and (match_code "reg")
59 (match_test "SSE_REGNO_P (REGNO (op))")))
61 ;; True if the operand is an AVX-512 new register.
62 (define_predicate "ext_sse_reg_operand"
63 (and (match_code "reg")
64 (match_test "EXT_REX_SSE_REGNO_P (REGNO (op))")))
66 ;; True if the operand is an AVX-512 mask register.
67 (define_predicate "mask_reg_operand"
68 (and (match_code "reg")
69 (match_test "MASK_REGNO_P (REGNO (op))")))
71 ;; Return true if op is a QImode register.
72 (define_predicate "any_QIreg_operand"
73 (and (match_code "reg")
74 (match_test "ANY_QI_REGNO_P (REGNO (op))")))
76 ;; Return true if op is one of QImode registers: %[abcd][hl].
77 (define_predicate "QIreg_operand"
78 (and (match_code "reg")
79 (match_test "QI_REGNO_P (REGNO (op))")))
81 ;; Return true if op is a QImode register operand other than %[abcd][hl].
82 (define_predicate "ext_QIreg_operand"
83 (and (match_test "TARGET_64BIT")
85 (not (match_test "QI_REGNO_P (REGNO (op))"))))
87 ;; Return true if op is the AX register.
88 (define_predicate "ax_reg_operand"
89 (and (match_code "reg")
90 (match_test "REGNO (op) == AX_REG")))
92 ;; Return true if op is the flags register.
93 (define_predicate "flags_reg_operand"
94 (and (match_code "reg")
95 (match_test "REGNO (op) == FLAGS_REG")))
97 ;; Match an SI or HImode register for a zero_extract.
98 (define_special_predicate "ext_register_operand"
99 (match_operand 0 "register_operand")
101 if ((!TARGET_64BIT || GET_MODE (op) != DImode)
102 && GET_MODE (op) != SImode && GET_MODE (op) != HImode)
105 op = SUBREG_REG (op);
107 /* Be careful to accept only registers having upper parts. */
109 && (REGNO (op) > LAST_VIRTUAL_REGISTER || QI_REGNO_P (REGNO (op))));
112 ;; Match nonimmediate operands, but exclude memory operands on 64bit targets.
113 (define_predicate "nonimmediate_x64nomem_operand"
114 (if_then_else (match_test "TARGET_64BIT")
115 (match_operand 0 "register_operand")
116 (match_operand 0 "nonimmediate_operand")))
118 ;; Match general operands, but exclude memory operands on 64bit targets.
119 (define_predicate "general_x64nomem_operand"
120 (if_then_else (match_test "TARGET_64BIT")
121 (match_operand 0 "nonmemory_operand")
122 (match_operand 0 "general_operand")))
124 ;; Match register operands, include memory operand for TARGET_MIX_SSE_I387.
125 (define_predicate "register_mixssei387nonimm_operand"
126 (if_then_else (match_test "TARGET_MIX_SSE_I387")
127 (match_operand 0 "nonimmediate_operand")
128 (match_operand 0 "register_operand")))
130 ;; Match register operands, include memory operand for TARGET_SSE4_1.
131 (define_predicate "register_sse4nonimm_operand"
132 (if_then_else (match_test "TARGET_SSE4_1")
133 (match_operand 0 "nonimmediate_operand")
134 (match_operand 0 "register_operand")))
136 ;; Return true if VALUE is symbol reference
137 (define_predicate "symbol_operand"
138 (match_code "symbol_ref"))
140 ;; Return true if VALUE can be stored in a sign extended immediate field.
141 (define_predicate "x86_64_immediate_operand"
142 (match_code "const_int,symbol_ref,label_ref,const")
145 return immediate_operand (op, mode);
147 switch (GET_CODE (op))
151 HOST_WIDE_INT val = trunc_int_for_mode (INTVAL (op), DImode);
152 return trunc_int_for_mode (val, SImode) == val;
155 /* For certain code models, the symbolic references are known to fit.
156 in CM_SMALL_PIC model we know it fits if it is local to the shared
157 library. Don't count TLS SYMBOL_REFs here, since they should fit
158 only if inside of UNSPEC handled below. */
159 /* TLS symbols are not constant. */
160 if (SYMBOL_REF_TLS_MODEL (op))
162 return (ix86_cmodel == CM_SMALL || ix86_cmodel == CM_KERNEL
163 || (ix86_cmodel == CM_MEDIUM && !SYMBOL_REF_FAR_ADDR_P (op)));
166 /* For certain code models, the code is near as well. */
167 return (ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM
168 || ix86_cmodel == CM_KERNEL);
171 /* We also may accept the offsetted memory references in certain
173 if (GET_CODE (XEXP (op, 0)) == UNSPEC)
174 switch (XINT (XEXP (op, 0), 1))
176 case UNSPEC_GOTPCREL:
178 case UNSPEC_GOTNTPOFF:
185 if (GET_CODE (XEXP (op, 0)) == PLUS)
187 rtx op1 = XEXP (XEXP (op, 0), 0);
188 rtx op2 = XEXP (XEXP (op, 0), 1);
189 HOST_WIDE_INT offset;
191 if (ix86_cmodel == CM_LARGE)
193 if (!CONST_INT_P (op2))
195 offset = trunc_int_for_mode (INTVAL (op2), DImode);
196 switch (GET_CODE (op1))
199 /* TLS symbols are not constant. */
200 if (SYMBOL_REF_TLS_MODEL (op1))
202 /* For CM_SMALL assume that latest object is 16MB before
203 end of 31bits boundary. We may also accept pretty
204 large negative constants knowing that all objects are
205 in the positive half of address space. */
206 if ((ix86_cmodel == CM_SMALL
207 || (ix86_cmodel == CM_MEDIUM
208 && !SYMBOL_REF_FAR_ADDR_P (op1)))
209 && offset < 16*1024*1024
210 && trunc_int_for_mode (offset, SImode) == offset)
212 /* For CM_KERNEL we know that all object resist in the
213 negative half of 32bits address space. We may not
214 accept negative offsets, since they may be just off
215 and we may accept pretty large positive ones. */
216 if (ix86_cmodel == CM_KERNEL
218 && trunc_int_for_mode (offset, SImode) == offset)
223 /* These conditions are similar to SYMBOL_REF ones, just the
224 constraints for code models differ. */
225 if ((ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM)
226 && offset < 16*1024*1024
227 && trunc_int_for_mode (offset, SImode) == offset)
229 if (ix86_cmodel == CM_KERNEL
231 && trunc_int_for_mode (offset, SImode) == offset)
236 switch (XINT (op1, 1))
240 if (trunc_int_for_mode (offset, SImode) == offset)
258 ;; Return true if VALUE can be stored in the zero extended immediate field.
259 (define_predicate "x86_64_zext_immediate_operand"
260 (match_code "const_int,symbol_ref,label_ref,const")
262 switch (GET_CODE (op))
265 return !(INTVAL (op) & ~(HOST_WIDE_INT) 0xffffffff);
268 /* For certain code models, the symbolic references are known to fit. */
269 /* TLS symbols are not constant. */
270 if (SYMBOL_REF_TLS_MODEL (op))
272 return (ix86_cmodel == CM_SMALL
273 || (ix86_cmodel == CM_MEDIUM
274 && !SYMBOL_REF_FAR_ADDR_P (op)));
277 /* For certain code models, the code is near as well. */
278 return ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM;
281 /* We also may accept the offsetted memory references in certain
283 if (GET_CODE (XEXP (op, 0)) == PLUS)
285 rtx op1 = XEXP (XEXP (op, 0), 0);
286 rtx op2 = XEXP (XEXP (op, 0), 1);
288 if (ix86_cmodel == CM_LARGE)
290 switch (GET_CODE (op1))
293 /* TLS symbols are not constant. */
294 if (SYMBOL_REF_TLS_MODEL (op1))
296 /* For small code model we may accept pretty large positive
297 offsets, since one bit is available for free. Negative
298 offsets are limited by the size of NULL pointer area
299 specified by the ABI. */
300 if ((ix86_cmodel == CM_SMALL
301 || (ix86_cmodel == CM_MEDIUM
302 && !SYMBOL_REF_FAR_ADDR_P (op1)))
304 && trunc_int_for_mode (INTVAL (op2), DImode) > -0x10000
305 && trunc_int_for_mode (INTVAL (op2), SImode) == INTVAL (op2))
307 /* ??? For the kernel, we may accept adjustment of
308 -0x10000000, since we know that it will just convert
309 negative address space to positive, but perhaps this
310 is not worthwhile. */
314 /* These conditions are similar to SYMBOL_REF ones, just the
315 constraints for code models differ. */
316 if ((ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM)
318 && trunc_int_for_mode (INTVAL (op2), DImode) > -0x10000
319 && trunc_int_for_mode (INTVAL (op2), SImode) == INTVAL (op2))
335 ;; Return true if size of VALUE can be stored in a sign
336 ;; extended immediate field.
337 (define_predicate "x86_64_immediate_size_operand"
338 (and (match_code "symbol_ref")
339 (ior (not (match_test "TARGET_64BIT"))
340 (match_test "ix86_cmodel == CM_SMALL")
341 (match_test "ix86_cmodel == CM_KERNEL"))))
343 ;; Return true if OP is general operand representable on x86_64.
344 (define_predicate "x86_64_general_operand"
345 (if_then_else (match_test "TARGET_64BIT")
346 (ior (match_operand 0 "nonimmediate_operand")
347 (match_operand 0 "x86_64_immediate_operand"))
348 (match_operand 0 "general_operand")))
350 ;; Return true if OP is non-VOIDmode general operand representable
351 ;; on x86_64. This predicate is used in sign-extending conversion
352 ;; operations that require non-VOIDmode immediate operands.
353 (define_predicate "x86_64_sext_operand"
354 (and (match_test "GET_MODE (op) != VOIDmode")
355 (match_operand 0 "x86_64_general_operand")))
357 ;; Return true if OP is non-VOIDmode general operand. This predicate
358 ;; is used in sign-extending conversion operations that require
359 ;; non-VOIDmode immediate operands.
360 (define_predicate "sext_operand"
361 (and (match_test "GET_MODE (op) != VOIDmode")
362 (match_operand 0 "general_operand")))
364 ;; Return true if OP is representable on x86_64 as zero-extended operand.
365 ;; This predicate is used in zero-extending conversion operations that
366 ;; require non-VOIDmode immediate operands.
367 (define_predicate "x86_64_zext_operand"
368 (if_then_else (match_test "TARGET_64BIT")
369 (ior (match_operand 0 "nonimmediate_operand")
370 (and (match_operand 0 "x86_64_zext_immediate_operand")
371 (match_test "GET_MODE (op) != VOIDmode")))
372 (match_operand 0 "nonimmediate_operand")))
374 ;; Return true if OP is general operand representable on x86_64
375 ;; as either sign extended or zero extended constant.
376 (define_predicate "x86_64_szext_general_operand"
377 (if_then_else (match_test "TARGET_64BIT")
378 (ior (match_operand 0 "nonimmediate_operand")
379 (match_operand 0 "x86_64_immediate_operand")
380 (match_operand 0 "x86_64_zext_immediate_operand"))
381 (match_operand 0 "general_operand")))
383 ;; Return true if OP is nonmemory operand representable on x86_64.
384 (define_predicate "x86_64_nonmemory_operand"
385 (if_then_else (match_test "TARGET_64BIT")
386 (ior (match_operand 0 "register_operand")
387 (match_operand 0 "x86_64_immediate_operand"))
388 (match_operand 0 "nonmemory_operand")))
390 ;; Return true if OP is nonmemory operand representable on x86_64.
391 (define_predicate "x86_64_szext_nonmemory_operand"
392 (if_then_else (match_test "TARGET_64BIT")
393 (ior (match_operand 0 "register_operand")
394 (match_operand 0 "x86_64_immediate_operand")
395 (match_operand 0 "x86_64_zext_immediate_operand"))
396 (match_operand 0 "nonmemory_operand")))
398 ;; Return true when operand is PIC expression that can be computed by lea
400 (define_predicate "pic_32bit_operand"
401 (match_code "const,symbol_ref,label_ref")
406 /* Rule out relocations that translate into 64bit constants. */
407 if (TARGET_64BIT && GET_CODE (op) == CONST)
410 if (GET_CODE (op) == PLUS && CONST_INT_P (XEXP (op, 1)))
412 if (GET_CODE (op) == UNSPEC
413 && (XINT (op, 1) == UNSPEC_GOTOFF
414 || XINT (op, 1) == UNSPEC_GOT))
418 return symbolic_operand (op, mode);
421 ;; Return true if OP is nonmemory operand acceptable by movabs patterns.
422 (define_predicate "x86_64_movabs_operand"
423 (and (match_operand 0 "nonmemory_operand")
424 (not (match_operand 0 "pic_32bit_operand"))))
426 ;; Return true if OP is either a symbol reference or a sum of a symbol
427 ;; reference and a constant.
428 (define_predicate "symbolic_operand"
429 (match_code "symbol_ref,label_ref,const")
431 switch (GET_CODE (op))
439 if (GET_CODE (op) == SYMBOL_REF
440 || GET_CODE (op) == LABEL_REF
441 || (GET_CODE (op) == UNSPEC
442 && (XINT (op, 1) == UNSPEC_GOT
443 || XINT (op, 1) == UNSPEC_GOTOFF
444 || XINT (op, 1) == UNSPEC_PCREL
445 || XINT (op, 1) == UNSPEC_GOTPCREL)))
447 if (GET_CODE (op) != PLUS
448 || !CONST_INT_P (XEXP (op, 1)))
452 if (GET_CODE (op) == SYMBOL_REF
453 || GET_CODE (op) == LABEL_REF)
455 /* Only @GOTOFF gets offsets. */
456 if (GET_CODE (op) != UNSPEC
457 || XINT (op, 1) != UNSPEC_GOTOFF)
460 op = XVECEXP (op, 0, 0);
461 if (GET_CODE (op) == SYMBOL_REF
462 || GET_CODE (op) == LABEL_REF)
471 ;; Return true if OP is a symbolic operand that resolves locally.
472 (define_predicate "local_symbolic_operand"
473 (match_code "const,label_ref,symbol_ref")
475 if (GET_CODE (op) == CONST
476 && GET_CODE (XEXP (op, 0)) == PLUS
477 && CONST_INT_P (XEXP (XEXP (op, 0), 1)))
478 op = XEXP (XEXP (op, 0), 0);
480 if (GET_CODE (op) == LABEL_REF)
483 if (GET_CODE (op) != SYMBOL_REF)
486 if (SYMBOL_REF_TLS_MODEL (op))
489 /* Dll-imported symbols are always external. */
490 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES && SYMBOL_REF_DLLIMPORT_P (op))
492 if (SYMBOL_REF_LOCAL_P (op))
495 /* There is, however, a not insubstantial body of code in the rest of
496 the compiler that assumes it can just stick the results of
497 ASM_GENERATE_INTERNAL_LABEL in a symbol_ref and have done. */
498 /* ??? This is a hack. Should update the body of the compiler to
499 always create a DECL an invoke targetm.encode_section_info. */
500 if (strncmp (XSTR (op, 0), internal_label_prefix,
501 internal_label_prefix_len) == 0)
507 ;; Test for a legitimate @GOTOFF operand.
509 ;; VxWorks does not impose a fixed gap between segments; the run-time
510 ;; gap can be different from the object-file gap. We therefore can't
511 ;; use @GOTOFF unless we are absolutely sure that the symbol is in the
512 ;; same segment as the GOT. Unfortunately, the flexibility of linker
513 ;; scripts means that we can't be sure of that in general, so assume
514 ;; that @GOTOFF is never valid on VxWorks.
515 (define_predicate "gotoff_operand"
516 (and (not (match_test "TARGET_VXWORKS_RTP"))
517 (match_operand 0 "local_symbolic_operand")))
519 ;; Test for various thread-local symbols.
520 (define_special_predicate "tls_symbolic_operand"
521 (and (match_code "symbol_ref")
522 (match_test "SYMBOL_REF_TLS_MODEL (op)")))
524 (define_special_predicate "tls_modbase_operand"
525 (and (match_code "symbol_ref")
526 (match_test "op == ix86_tls_module_base ()")))
528 ;; Test for a pc-relative call operand
529 (define_predicate "constant_call_address_operand"
530 (match_code "symbol_ref")
532 if (ix86_cmodel == CM_LARGE || ix86_cmodel == CM_LARGE_PIC)
534 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES && SYMBOL_REF_DLLIMPORT_P (op))
539 ;; P6 processors will jump to the address after the decrement when %esp
540 ;; is used as a call operand, so they will execute return address as a code.
541 ;; See Pentium Pro errata 70, Pentium 2 errata A33 and Pentium 3 errata E17.
543 (define_predicate "call_register_no_elim_operand"
544 (match_operand 0 "register_operand")
547 op = SUBREG_REG (op);
549 if (!TARGET_64BIT && op == stack_pointer_rtx)
552 return register_no_elim_operand (op, mode);
555 ;; True for any non-virtual or eliminable register. Used in places where
556 ;; instantiation of such a register may cause the pattern to not be recognized.
557 (define_predicate "register_no_elim_operand"
558 (match_operand 0 "register_operand")
561 op = SUBREG_REG (op);
562 return !(op == arg_pointer_rtx
563 || op == frame_pointer_rtx
564 || IN_RANGE (REGNO (op),
565 FIRST_PSEUDO_REGISTER, LAST_VIRTUAL_REGISTER));
568 ;; Similarly, but include the stack pointer. This is used to prevent esp
569 ;; from being used as an index reg.
570 (define_predicate "index_register_operand"
571 (match_operand 0 "register_operand")
574 op = SUBREG_REG (op);
575 if (reload_completed)
576 return REG_OK_FOR_INDEX_STRICT_P (op);
578 return REG_OK_FOR_INDEX_NONSTRICT_P (op);
581 ;; Return false if this is any eliminable register. Otherwise general_operand.
582 (define_predicate "general_no_elim_operand"
583 (if_then_else (match_code "reg,subreg")
584 (match_operand 0 "register_no_elim_operand")
585 (match_operand 0 "general_operand")))
587 ;; Return false if this is any eliminable register. Otherwise
588 ;; register_operand or a constant.
589 (define_predicate "nonmemory_no_elim_operand"
590 (ior (match_operand 0 "register_no_elim_operand")
591 (match_operand 0 "immediate_operand")))
593 ;; Test for a valid operand for indirect branch.
594 (define_predicate "indirect_branch_operand"
595 (ior (match_operand 0 "register_operand")
596 (and (not (match_test "TARGET_X32"))
597 (match_operand 0 "memory_operand"))))
599 ;; Return true if OP is a memory operands that can be used in sibcalls.
600 (define_predicate "sibcall_memory_operand"
601 (and (match_operand 0 "memory_operand")
602 (match_test "CONSTANT_P (XEXP (op, 0))
603 || (GET_CODE (XEXP (op, 0)) == PLUS
604 && REG_P (XEXP (XEXP (op, 0), 0))
605 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST
606 && GET_CODE (XEXP (XEXP (XEXP (op, 0), 1), 0)) == UNSPEC
607 && XINT (XEXP (XEXP (XEXP (op, 0), 1), 0), 1) == UNSPEC_GOT)")))
609 ;; Test for a valid operand for a call instruction.
610 ;; Allow constant call address operands in Pmode only.
611 (define_special_predicate "call_insn_operand"
612 (ior (match_test "constant_call_address_operand
613 (op, mode == VOIDmode ? mode : Pmode)")
614 (match_operand 0 "call_register_no_elim_operand")
615 (and (not (match_test "TARGET_X32"))
616 (match_operand 0 "memory_operand"))))
618 ;; Similarly, but for tail calls, in which we cannot allow memory references.
619 (define_special_predicate "sibcall_insn_operand"
620 (ior (match_test "constant_call_address_operand
621 (op, mode == VOIDmode ? mode : Pmode)")
622 (match_operand 0 "register_no_elim_operand")
623 (and (not (match_test "TARGET_X32"))
624 (match_operand 0 "sibcall_memory_operand"))))
626 ;; Return true if OP is a GOT memory operand.
627 (define_predicate "GOT_memory_operand"
628 (match_operand 0 "memory_operand")
631 return (GET_CODE (op) == CONST
632 && GET_CODE (XEXP (op, 0)) == UNSPEC
633 && XINT (XEXP (op, 0), 1) == UNSPEC_GOTPCREL);
636 ;; Match exactly zero.
637 (define_predicate "const0_operand"
638 (match_code "const_int,const_wide_int,const_double,const_vector")
640 if (mode == VOIDmode)
641 mode = GET_MODE (op);
642 return op == CONST0_RTX (mode);
646 (define_predicate "constm1_operand"
647 (match_code "const_int,const_wide_int,const_double,const_vector")
649 if (mode == VOIDmode)
650 mode = GET_MODE (op);
651 return op == CONSTM1_RTX (mode);
654 ;; Match one or vector filled with ones.
655 (define_predicate "const1_operand"
656 (match_code "const_int,const_wide_int,const_double,const_vector")
658 if (mode == VOIDmode)
659 mode = GET_MODE (op);
660 return op == CONST1_RTX (mode);
663 ;; Match exactly eight.
664 (define_predicate "const8_operand"
665 (and (match_code "const_int")
666 (match_test "INTVAL (op) == 8")))
668 ;; Match exactly 128.
669 (define_predicate "const128_operand"
670 (and (match_code "const_int")
671 (match_test "INTVAL (op) == 128")))
673 ;; Match exactly 0x0FFFFFFFF in anddi as a zero-extension operation
674 (define_predicate "const_32bit_mask"
675 (and (match_code "const_int")
676 (match_test "trunc_int_for_mode (INTVAL (op), DImode)
677 == (HOST_WIDE_INT) 0xffffffff")))
679 ;; Match 2, 4, or 8. Used for leal multiplicands.
680 (define_predicate "const248_operand"
681 (match_code "const_int")
683 HOST_WIDE_INT i = INTVAL (op);
684 return i == 2 || i == 4 || i == 8;
687 ;; Match 2, 3, 6, or 7
688 (define_predicate "const2367_operand"
689 (match_code "const_int")
691 HOST_WIDE_INT i = INTVAL (op);
692 return i == 2 || i == 3 || i == 6 || i == 7;
695 ;; Match 1, 2, 4, or 8
696 (define_predicate "const1248_operand"
697 (match_code "const_int")
699 HOST_WIDE_INT i = INTVAL (op);
700 return i == 1 || i == 2 || i == 4 || i == 8;
703 ;; Match 3, 5, or 9. Used for leal multiplicands.
704 (define_predicate "const359_operand"
705 (match_code "const_int")
707 HOST_WIDE_INT i = INTVAL (op);
708 return i == 3 || i == 5 || i == 9;
711 ;; Match 4 or 8 to 11. Used for embeded rounding.
712 (define_predicate "const_4_or_8_to_11_operand"
713 (match_code "const_int")
715 HOST_WIDE_INT i = INTVAL (op);
716 return i == 4 || (i >= 8 && i <= 11);
719 ;; Match 4 or 8. Used for SAE.
720 (define_predicate "const48_operand"
721 (match_code "const_int")
723 HOST_WIDE_INT i = INTVAL (op);
724 return i == 4 || i == 8;
728 (define_predicate "const_0_to_1_operand"
729 (and (match_code "const_int")
730 (ior (match_test "op == const0_rtx")
731 (match_test "op == const1_rtx"))))
734 (define_predicate "const_0_to_3_operand"
735 (and (match_code "const_int")
736 (match_test "IN_RANGE (INTVAL (op), 0, 3)")))
739 (define_predicate "const_0_to_4_operand"
740 (and (match_code "const_int")
741 (match_test "IN_RANGE (INTVAL (op), 0, 4)")))
744 (define_predicate "const_0_to_5_operand"
745 (and (match_code "const_int")
746 (match_test "IN_RANGE (INTVAL (op), 0, 5)")))
749 (define_predicate "const_0_to_7_operand"
750 (and (match_code "const_int")
751 (match_test "IN_RANGE (INTVAL (op), 0, 7)")))
754 (define_predicate "const_0_to_15_operand"
755 (and (match_code "const_int")
756 (match_test "IN_RANGE (INTVAL (op), 0, 15)")))
759 (define_predicate "const_0_to_31_operand"
760 (and (match_code "const_int")
761 (match_test "IN_RANGE (INTVAL (op), 0, 31)")))
764 (define_predicate "const_0_to_63_operand"
765 (and (match_code "const_int")
766 (match_test "IN_RANGE (INTVAL (op), 0, 63)")))
769 (define_predicate "const_0_to_255_operand"
770 (and (match_code "const_int")
771 (match_test "IN_RANGE (INTVAL (op), 0, 255)")))
773 ;; Match (0 to 255) * 8
774 (define_predicate "const_0_to_255_mul_8_operand"
775 (match_code "const_int")
777 unsigned HOST_WIDE_INT val = INTVAL (op);
778 return val <= 255*8 && val % 8 == 0;
781 ;; Return true if OP is CONST_INT >= 1 and <= 31 (a valid operand
782 ;; for shift & compare patterns, as shifting by 0 does not change flags).
783 (define_predicate "const_1_to_31_operand"
784 (and (match_code "const_int")
785 (match_test "IN_RANGE (INTVAL (op), 1, 31)")))
787 ;; Return true if OP is CONST_INT >= 1 and <= 63 (a valid operand
788 ;; for 64bit shift & compare patterns, as shifting by 0 does not change flags).
789 (define_predicate "const_1_to_63_operand"
790 (and (match_code "const_int")
791 (match_test "IN_RANGE (INTVAL (op), 1, 63)")))
794 (define_predicate "const_2_to_3_operand"
795 (and (match_code "const_int")
796 (match_test "IN_RANGE (INTVAL (op), 2, 3)")))
799 (define_predicate "const_4_to_5_operand"
800 (and (match_code "const_int")
801 (match_test "IN_RANGE (INTVAL (op), 4, 5)")))
804 (define_predicate "const_4_to_7_operand"
805 (and (match_code "const_int")
806 (match_test "IN_RANGE (INTVAL (op), 4, 7)")))
809 (define_predicate "const_6_to_7_operand"
810 (and (match_code "const_int")
811 (match_test "IN_RANGE (INTVAL (op), 6, 7)")))
814 (define_predicate "const_8_to_9_operand"
815 (and (match_code "const_int")
816 (match_test "IN_RANGE (INTVAL (op), 8, 9)")))
819 (define_predicate "const_8_to_11_operand"
820 (and (match_code "const_int")
821 (match_test "IN_RANGE (INTVAL (op), 8, 11)")))
824 (define_predicate "const_8_to_15_operand"
825 (and (match_code "const_int")
826 (match_test "IN_RANGE (INTVAL (op), 8, 15)")))
829 (define_predicate "const_10_to_11_operand"
830 (and (match_code "const_int")
831 (match_test "IN_RANGE (INTVAL (op), 10, 11)")))
834 (define_predicate "const_12_to_13_operand"
835 (and (match_code "const_int")
836 (match_test "IN_RANGE (INTVAL (op), 12, 13)")))
839 (define_predicate "const_12_to_15_operand"
840 (and (match_code "const_int")
841 (match_test "IN_RANGE (INTVAL (op), 12, 15)")))
844 (define_predicate "const_14_to_15_operand"
845 (and (match_code "const_int")
846 (match_test "IN_RANGE (INTVAL (op), 14, 15)")))
849 (define_predicate "const_16_to_19_operand"
850 (and (match_code "const_int")
851 (match_test "IN_RANGE (INTVAL (op), 16, 19)")))
854 (define_predicate "const_16_to_31_operand"
855 (and (match_code "const_int")
856 (match_test "IN_RANGE (INTVAL (op), 16, 31)")))
859 (define_predicate "const_20_to_23_operand"
860 (and (match_code "const_int")
861 (match_test "IN_RANGE (INTVAL (op), 20, 23)")))
864 (define_predicate "const_24_to_27_operand"
865 (and (match_code "const_int")
866 (match_test "IN_RANGE (INTVAL (op), 24, 27)")))
869 (define_predicate "const_28_to_31_operand"
870 (and (match_code "const_int")
871 (match_test "IN_RANGE (INTVAL (op), 28, 31)")))
873 ;; True if this is a constant appropriate for an increment or decrement.
874 (define_predicate "incdec_operand"
875 (match_code "const_int")
877 /* On Pentium4, the inc and dec operations causes extra dependency on flag
878 registers, since carry flag is not set. */
879 if (!TARGET_USE_INCDEC && !optimize_insn_for_size_p ())
881 return op == const1_rtx || op == constm1_rtx;
884 ;; True for registers, or 1 or -1. Used to optimize double-word shifts.
885 (define_predicate "reg_or_pm1_operand"
886 (ior (match_operand 0 "register_operand")
887 (and (match_code "const_int")
888 (ior (match_test "op == const1_rtx")
889 (match_test "op == constm1_rtx")))))
891 ;; True if OP is acceptable as operand of DImode shift expander.
892 (define_predicate "shiftdi_operand"
893 (if_then_else (match_test "TARGET_64BIT")
894 (match_operand 0 "nonimmediate_operand")
895 (match_operand 0 "register_operand")))
897 (define_predicate "ashldi_input_operand"
898 (if_then_else (match_test "TARGET_64BIT")
899 (match_operand 0 "nonimmediate_operand")
900 (match_operand 0 "reg_or_pm1_operand")))
902 ;; Return true if OP is a vector load from the constant pool with just
903 ;; the first element nonzero.
904 (define_predicate "zero_extended_scalar_load_operand"
908 op = maybe_get_pool_constant (op);
910 if (!(op && GET_CODE (op) == CONST_VECTOR))
913 n_elts = CONST_VECTOR_NUNITS (op);
915 for (n_elts--; n_elts > 0; n_elts--)
917 rtx elt = CONST_VECTOR_ELT (op, n_elts);
918 if (elt != CONST0_RTX (GET_MODE_INNER (GET_MODE (op))))
924 /* Return true if operand is a vector constant that is all ones. */
925 (define_predicate "vector_all_ones_operand"
926 (and (match_code "const_vector")
927 (match_test "INTEGRAL_MODE_P (GET_MODE (op))")
928 (match_test "op == CONSTM1_RTX (GET_MODE (op))")))
930 ; Return true when OP is operand acceptable for standard SSE move.
931 (define_predicate "vector_move_operand"
932 (ior (match_operand 0 "nonimmediate_operand")
933 (match_operand 0 "const0_operand")))
935 ;; Return true when OP is either nonimmediate operand, or any
937 (define_predicate "nonimmediate_or_const_vector_operand"
938 (ior (match_operand 0 "nonimmediate_operand")
939 (match_code "const_vector")))
941 ;; Return true when OP is nonimmediate or standard SSE constant.
942 (define_predicate "nonimmediate_or_sse_const_operand"
943 (match_operand 0 "general_operand")
945 if (nonimmediate_operand (op, mode))
947 if (standard_sse_constant_p (op) > 0)
952 ;; Return true if OP is a register or a zero.
953 (define_predicate "reg_or_0_operand"
954 (ior (match_operand 0 "register_operand")
955 (match_operand 0 "const0_operand")))
957 ;; Return true for RTX codes that force SImode address.
958 (define_predicate "SImode_address_operand"
959 (match_code "subreg,zero_extend,and"))
961 ;; Return true if op if a valid address for LEA, and does not contain
962 ;; a segment override. Defined as a special predicate to allow
963 ;; mode-less const_int operands pass to address_operand.
964 (define_special_predicate "address_no_seg_operand"
965 (match_test "address_operand (op, VOIDmode)")
967 struct ix86_address parts;
970 if (!CONST_INT_P (op)
972 && GET_MODE (op) != mode)
975 ok = ix86_decompose_address (op, &parts);
977 return parts.seg == SEG_DEFAULT;
980 ;; Return true if op if a valid base register, displacement or
981 ;; sum of base register and displacement for VSIB addressing.
982 (define_predicate "vsib_address_operand"
983 (match_test "address_operand (op, VOIDmode)")
985 struct ix86_address parts;
989 ok = ix86_decompose_address (op, &parts);
991 if (parts.index || parts.seg != SEG_DEFAULT)
994 /* VSIB addressing doesn't support (%rip). */
998 if (GET_CODE (disp) == CONST)
1000 disp = XEXP (disp, 0);
1001 if (GET_CODE (disp) == PLUS)
1002 disp = XEXP (disp, 0);
1003 if (GET_CODE (disp) == UNSPEC)
1004 switch (XINT (disp, 1))
1006 case UNSPEC_GOTPCREL:
1008 case UNSPEC_GOTNTPOFF:
1014 && (GET_CODE (disp) == SYMBOL_REF
1015 || GET_CODE (disp) == LABEL_REF))
1022 ;; Return true if op is valid MPX address operand without base
1023 (define_predicate "address_mpx_no_base_operand"
1024 (match_test "address_operand (op, VOIDmode)")
1026 struct ix86_address parts;
1029 ok = ix86_decompose_address (op, &parts);
1032 if (parts.index && parts.base)
1035 if (parts.seg != SEG_DEFAULT)
1038 /* Do not support (%rip). */
1039 if (parts.disp && flag_pic && TARGET_64BIT
1040 && SYMBOLIC_CONST (parts.disp))
1042 if (GET_CODE (parts.disp) != CONST
1043 || GET_CODE (XEXP (parts.disp, 0)) != PLUS
1044 || GET_CODE (XEXP (XEXP (parts.disp, 0), 0)) != UNSPEC
1045 || !CONST_INT_P (XEXP (XEXP (parts.disp, 0), 1))
1046 || (XINT (XEXP (XEXP (parts.disp, 0), 0), 1) != UNSPEC_DTPOFF
1047 && XINT (XEXP (XEXP (parts.disp, 0), 0), 1) != UNSPEC_NTPOFF))
1054 ;; Return true if op is valid MPX address operand without index
1055 (define_predicate "address_mpx_no_index_operand"
1056 (match_test "address_operand (op, VOIDmode)")
1058 struct ix86_address parts;
1061 ok = ix86_decompose_address (op, &parts);
1067 if (parts.seg != SEG_DEFAULT)
1070 /* Do not support (%rip). */
1071 if (parts.disp && flag_pic && TARGET_64BIT
1072 && SYMBOLIC_CONST (parts.disp)
1073 && (GET_CODE (parts.disp) != CONST
1074 || GET_CODE (XEXP (parts.disp, 0)) != PLUS
1075 || GET_CODE (XEXP (XEXP (parts.disp, 0), 0)) != UNSPEC
1076 || !CONST_INT_P (XEXP (XEXP (parts.disp, 0), 1))
1077 || (XINT (XEXP (XEXP (parts.disp, 0), 0), 1) != UNSPEC_DTPOFF
1078 && XINT (XEXP (XEXP (parts.disp, 0), 0), 1) != UNSPEC_NTPOFF)))
1084 (define_predicate "vsib_mem_operator"
1087 (define_predicate "bnd_mem_operator"
1090 ;; Return true if the rtx is known to be at least 32 bits aligned.
1091 (define_predicate "aligned_operand"
1092 (match_operand 0 "general_operand")
1094 struct ix86_address parts;
1097 /* Registers and immediate operands are always "aligned". */
1101 /* All patterns using aligned_operand on memory operands ends up
1102 in promoting memory operand to 64bit and thus causing memory mismatch. */
1103 if (TARGET_MEMORY_MISMATCH_STALL && !optimize_insn_for_size_p ())
1106 /* Don't even try to do any aligned optimizations with volatiles. */
1107 if (MEM_VOLATILE_P (op))
1110 if (MEM_ALIGN (op) >= 32)
1115 /* Pushes and pops are only valid on the stack pointer. */
1116 if (GET_CODE (op) == PRE_DEC
1117 || GET_CODE (op) == POST_INC)
1120 /* Decode the address. */
1121 ok = ix86_decompose_address (op, &parts);
1124 if (parts.base && SUBREG_P (parts.base))
1125 parts.base = SUBREG_REG (parts.base);
1126 if (parts.index && SUBREG_P (parts.index))
1127 parts.index = SUBREG_REG (parts.index);
1129 /* Look for some component that isn't known to be aligned. */
1132 if (REGNO_POINTER_ALIGN (REGNO (parts.index)) * parts.scale < 32)
1137 if (REGNO_POINTER_ALIGN (REGNO (parts.base)) < 32)
1142 if (!CONST_INT_P (parts.disp)
1143 || (INTVAL (parts.disp) & 3))
1147 /* Didn't find one -- this must be an aligned address. */
1151 ;; Return true if OP is memory operand with a displacement.
1152 (define_predicate "memory_displacement_operand"
1153 (match_operand 0 "memory_operand")
1155 struct ix86_address parts;
1158 ok = ix86_decompose_address (XEXP (op, 0), &parts);
1160 return parts.disp != NULL_RTX;
1163 ;; Return true if OP is memory operand with a displacement only.
1164 (define_predicate "memory_displacement_only_operand"
1165 (match_operand 0 "memory_operand")
1167 struct ix86_address parts;
1173 ok = ix86_decompose_address (XEXP (op, 0), &parts);
1176 if (parts.base || parts.index)
1179 return parts.disp != NULL_RTX;
1182 ;; Return true if OP is memory operand that cannot be represented
1183 ;; by the modRM array.
1184 (define_predicate "long_memory_operand"
1185 (and (match_operand 0 "memory_operand")
1186 (match_test "memory_address_length (op, false)")))
1188 ;; Return true if OP is a comparison operator that can be issued by fcmov.
1189 (define_predicate "fcmov_comparison_operator"
1190 (match_operand 0 "comparison_operator")
1192 machine_mode inmode = GET_MODE (XEXP (op, 0));
1193 enum rtx_code code = GET_CODE (op);
1195 if (inmode == CCFPmode || inmode == CCFPUmode)
1197 if (!ix86_trivial_fp_comparison_operator (op, mode))
1199 code = ix86_fp_compare_code_to_integer (code);
1201 /* i387 supports just limited amount of conditional codes. */
1204 case LTU: case GTU: case LEU: case GEU:
1205 if (inmode == CCmode || inmode == CCFPmode || inmode == CCFPUmode
1206 || inmode == CCCmode)
1209 case ORDERED: case UNORDERED:
1217 ;; Return true if OP is a comparison that can be used in the CMPSS/CMPPS insns.
1218 ;; The first set are supported directly; the second set can't be done with
1219 ;; full IEEE support, i.e. NaNs.
1221 (define_predicate "sse_comparison_operator"
1222 (ior (match_code "eq,ne,lt,le,unordered,unge,ungt,ordered")
1223 (and (match_test "TARGET_AVX")
1224 (match_code "ge,gt,uneq,unle,unlt,ltgt"))))
1226 (define_predicate "ix86_comparison_int_operator"
1227 (match_code "ne,eq,ge,gt,le,lt"))
1229 (define_predicate "ix86_comparison_uns_operator"
1230 (match_code "ne,eq,geu,gtu,leu,ltu"))
1232 (define_predicate "bt_comparison_operator"
1233 (match_code "ne,eq"))
1235 ;; Return true if OP is a valid comparison operator in valid mode.
1236 (define_predicate "ix86_comparison_operator"
1237 (match_operand 0 "comparison_operator")
1239 machine_mode inmode = GET_MODE (XEXP (op, 0));
1240 enum rtx_code code = GET_CODE (op);
1242 if (inmode == CCFPmode || inmode == CCFPUmode)
1243 return ix86_trivial_fp_comparison_operator (op, mode);
1250 if (inmode == CCmode || inmode == CCGCmode
1251 || inmode == CCGOCmode || inmode == CCNOmode)
1254 case LTU: case GTU: case LEU: case GEU:
1255 if (inmode == CCmode || inmode == CCCmode)
1258 case ORDERED: case UNORDERED:
1259 if (inmode == CCmode)
1263 if (inmode == CCmode || inmode == CCGCmode || inmode == CCNOmode)
1271 ;; Return true if OP is a valid comparison operator
1272 ;; testing carry flag to be set.
1273 (define_predicate "ix86_carry_flag_operator"
1274 (match_code "ltu,lt,unlt,gtu,gt,ungt,le,unle,ge,unge,ltgt,uneq")
1276 machine_mode inmode = GET_MODE (XEXP (op, 0));
1277 enum rtx_code code = GET_CODE (op);
1279 if (inmode == CCFPmode || inmode == CCFPUmode)
1281 if (!ix86_trivial_fp_comparison_operator (op, mode))
1283 code = ix86_fp_compare_code_to_integer (code);
1285 else if (inmode == CCCmode)
1286 return code == LTU || code == GTU;
1287 else if (inmode != CCmode)
1293 ;; Return true if this comparison only requires testing one flag bit.
1294 (define_predicate "ix86_trivial_fp_comparison_operator"
1295 (match_code "gt,ge,unlt,unle,uneq,ltgt,ordered,unordered"))
1297 ;; Return true if we know how to do this comparison. Others require
1298 ;; testing more than one flag bit, and we let the generic middle-end
1300 (define_predicate "ix86_fp_comparison_operator"
1301 (if_then_else (match_test "ix86_fp_comparison_strategy (GET_CODE (op))
1302 == IX86_FPCMP_ARITH")
1303 (match_operand 0 "comparison_operator")
1304 (match_operand 0 "ix86_trivial_fp_comparison_operator")))
1306 ;; Same as above, but for swapped comparison used in *jcc<fp>_<int>_i387.
1307 (define_predicate "ix86_swapped_fp_comparison_operator"
1308 (match_operand 0 "comparison_operator")
1310 enum rtx_code code = GET_CODE (op);
1313 PUT_CODE (op, swap_condition (code));
1314 ret = ix86_fp_comparison_operator (op, mode);
1315 PUT_CODE (op, code);
1319 ;; Nearly general operand, but accept any const_double, since we wish
1320 ;; to be able to drop them into memory rather than have them get pulled
1322 (define_predicate "cmp_fp_expander_operand"
1323 (ior (match_code "const_double")
1324 (match_operand 0 "general_operand")))
1326 ;; Return true if this is a valid binary floating-point operation.
1327 (define_predicate "binary_fp_operator"
1328 (match_code "plus,minus,mult,div"))
1330 ;; Return true if this is a multiply operation.
1331 (define_predicate "mult_operator"
1332 (match_code "mult"))
1334 ;; Return true if this is a division operation.
1335 (define_predicate "div_operator"
1338 ;; Return true if this is a plus, minus, and, ior or xor operation.
1339 (define_predicate "plusminuslogic_operator"
1340 (match_code "plus,minus,and,ior,xor"))
1342 ;; Return true if this is a float extend operation.
1343 (define_predicate "float_operator"
1344 (match_code "float"))
1346 ;; Return true for ARITHMETIC_P.
1347 (define_predicate "arith_or_logical_operator"
1348 (match_code "plus,mult,and,ior,xor,smin,smax,umin,umax,compare,minus,div,
1349 mod,udiv,umod,ashift,rotate,ashiftrt,lshiftrt,rotatert"))
1351 ;; Return true for COMMUTATIVE_P.
1352 (define_predicate "commutative_operator"
1353 (match_code "plus,mult,and,ior,xor,smin,smax,umin,umax"))
1355 ;; Return true if OP is a binary operator that can be promoted to wider mode.
1356 (define_predicate "promotable_binary_operator"
1357 (ior (match_code "plus,minus,and,ior,xor,ashift")
1358 (and (match_code "mult")
1359 (match_test "TARGET_TUNE_PROMOTE_HIMODE_IMUL"))))
1361 (define_predicate "compare_operator"
1362 (match_code "compare"))
1364 (define_predicate "absneg_operator"
1365 (match_code "abs,neg"))
1367 ;; Return true if OP is misaligned memory operand
1368 (define_predicate "misaligned_operand"
1369 (and (match_code "mem")
1370 (match_test "MEM_ALIGN (op) < GET_MODE_ALIGNMENT (mode)")))
1372 ;; Return true if OP is a emms operation, known to be a PARALLEL.
1373 (define_predicate "emms_operation"
1374 (match_code "parallel")
1378 if (XVECLEN (op, 0) != 17)
1381 for (i = 0; i < 8; i++)
1383 rtx elt = XVECEXP (op, 0, i+1);
1385 if (GET_CODE (elt) != CLOBBER
1386 || GET_CODE (SET_DEST (elt)) != REG
1387 || GET_MODE (SET_DEST (elt)) != XFmode
1388 || REGNO (SET_DEST (elt)) != FIRST_STACK_REG + i)
1391 elt = XVECEXP (op, 0, i+9);
1393 if (GET_CODE (elt) != CLOBBER
1394 || GET_CODE (SET_DEST (elt)) != REG
1395 || GET_MODE (SET_DEST (elt)) != DImode
1396 || REGNO (SET_DEST (elt)) != FIRST_MMX_REG + i)
1402 ;; Return true if OP is a vzeroall operation, known to be a PARALLEL.
1403 (define_predicate "vzeroall_operation"
1404 (match_code "parallel")
1406 unsigned i, nregs = TARGET_64BIT ? 16 : 8;
1408 if ((unsigned) XVECLEN (op, 0) != 1 + nregs)
1411 for (i = 0; i < nregs; i++)
1413 rtx elt = XVECEXP (op, 0, i+1);
1415 if (GET_CODE (elt) != SET
1416 || GET_CODE (SET_DEST (elt)) != REG
1417 || GET_MODE (SET_DEST (elt)) != V8SImode
1418 || REGNO (SET_DEST (elt)) != SSE_REGNO (i)
1419 || SET_SRC (elt) != CONST0_RTX (V8SImode))
1425 ;; return true if OP is a vzeroupper operation.
1426 (define_predicate "vzeroupper_operation"
1427 (and (match_code "unspec_volatile")
1428 (match_test "XINT (op, 1) == UNSPECV_VZEROUPPER")))
1430 ;; Return true if OP is an addsub vec_merge operation
1431 (define_predicate "addsub_vm_operator"
1432 (match_code "vec_merge")
1443 if (GET_CODE (op0) == MINUS && GET_CODE (op1) == PLUS)
1445 else if (GET_CODE (op0) == PLUS && GET_CODE (op1) == MINUS)
1450 mask = INTVAL (XEXP (op, 2));
1451 nunits = GET_MODE_NUNITS (mode);
1453 for (elt = 0; elt < nunits; elt++)
1455 /* bit clear: take from op0, set: take from op1 */
1456 int bit = !(mask & (HOST_WIDE_INT_1U << elt));
1458 if (bit != ((elt & 1) ^ swapped))
1465 ;; Return true if OP is an addsub vec_select/vec_concat operation
1466 (define_predicate "addsub_vs_operator"
1467 (and (match_code "vec_select")
1468 (match_code "vec_concat" "0"))
1474 op0 = XEXP (XEXP (op, 0), 0);
1475 op1 = XEXP (XEXP (op, 0), 1);
1478 if (GET_CODE (op0) == MINUS && GET_CODE (op1) == PLUS)
1480 else if (GET_CODE (op0) == PLUS && GET_CODE (op1) == MINUS)
1485 nunits = GET_MODE_NUNITS (mode);
1486 if (XVECLEN (XEXP (op, 1), 0) != nunits)
1489 /* We already checked that permutation is suitable for addsub,
1490 so only look at the first element of the parallel. */
1491 elt = INTVAL (XVECEXP (XEXP (op, 1), 0, 0));
1493 return elt == (swapped ? nunits : 0);
1496 ;; Return true if OP is a parallel for an addsub vec_select.
1497 (define_predicate "addsub_vs_parallel"
1498 (and (match_code "parallel")
1499 (match_code "const_int" "a"))
1501 int nelt = XVECLEN (op, 0);
1507 /* Check that the permutation is suitable for addsub.
1508 For example, { 0 9 2 11 4 13 6 15 } or { 8 1 10 3 12 5 14 7 }. */
1509 elt = INTVAL (XVECEXP (op, 0, 0));
1512 for (i = 1; i < nelt; ++i)
1513 if (INTVAL (XVECEXP (op, 0, i)) != (i + (i & 1) * nelt))
1516 else if (elt == nelt)
1518 for (i = 1; i < nelt; ++i)
1519 if (INTVAL (XVECEXP (op, 0, i)) != (elt + i - (i & 1) * nelt))
1528 ;; Return true if OP is a parallel for a vbroadcast permute.
1529 (define_predicate "avx_vbroadcast_operand"
1530 (and (match_code "parallel")
1531 (match_code "const_int" "a"))
1533 rtx elt = XVECEXP (op, 0, 0);
1534 int i, nelt = XVECLEN (op, 0);
1536 /* Don't bother checking there are the right number of operands,
1537 merely that they're all identical. */
1538 for (i = 1; i < nelt; ++i)
1539 if (XVECEXP (op, 0, i) != elt)
1544 ;; Return true if OP is a parallel for a palignr permute.
1545 (define_predicate "palignr_operand"
1546 (and (match_code "parallel")
1547 (match_code "const_int" "a"))
1549 int elt = INTVAL (XVECEXP (op, 0, 0));
1550 int i, nelt = XVECLEN (op, 0);
1552 /* Check that an order in the permutation is suitable for palignr.
1553 For example, {5 6 7 0 1 2 3 4} is "palignr 5, xmm, xmm". */
1554 for (i = 1; i < nelt; ++i)
1555 if (INTVAL (XVECEXP (op, 0, i)) != ((elt + i) % nelt))
1560 ;; Return true if OP is a proper third operand to vpblendw256.
1561 (define_predicate "avx2_pblendw_operand"
1562 (match_code "const_int")
1564 HOST_WIDE_INT val = INTVAL (op);
1565 HOST_WIDE_INT low = val & 0xff;
1566 return val == ((low << 8) | low);
1569 ;; Return true if OP is nonimmediate_operand or CONST_VECTOR.
1570 (define_predicate "general_vector_operand"
1571 (ior (match_operand 0 "nonimmediate_operand")
1572 (match_code "const_vector")))
1574 ;; Return true if OP is either -1 constant or stored in register.
1575 (define_predicate "register_or_constm1_operand"
1576 (ior (match_operand 0 "register_operand")
1577 (and (match_code "const_int")
1578 (match_test "op == constm1_rtx"))))