1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20 Boston, MA 02110-1301, USA. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-codes.h"
36 #include "insn-attr.h"
44 #include "basic-block.h"
47 #include "target-def.h"
48 #include "langhooks.h"
50 #include "tree-gimple.h"
52 #include "tm-constrs.h"
55 #ifndef CHECK_STACK_LIMIT
56 #define CHECK_STACK_LIMIT (-1)
59 /* Return index of given mode in mult and division cost tables. */
60 #define MODE_INDEX(mode) \
61 ((mode) == QImode ? 0 \
62 : (mode) == HImode ? 1 \
63 : (mode) == SImode ? 2 \
64 : (mode) == DImode ? 3 \
67 /* Processor costs (relative to an add) */
68 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
69 #define COSTS_N_BYTES(N) ((N) * 2)
71 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall}}}
74 struct processor_costs size_cost = { /* costs for tuning for size */
75 COSTS_N_BYTES (2), /* cost of an add instruction */
76 COSTS_N_BYTES (3), /* cost of a lea instruction */
77 COSTS_N_BYTES (2), /* variable shift costs */
78 COSTS_N_BYTES (3), /* constant shift costs */
79 {COSTS_N_BYTES (3), /* cost of starting multiply for QI */
80 COSTS_N_BYTES (3), /* HI */
81 COSTS_N_BYTES (3), /* SI */
82 COSTS_N_BYTES (3), /* DI */
83 COSTS_N_BYTES (5)}, /* other */
84 0, /* cost of multiply per each bit set */
85 {COSTS_N_BYTES (3), /* cost of a divide/mod for QI */
86 COSTS_N_BYTES (3), /* HI */
87 COSTS_N_BYTES (3), /* SI */
88 COSTS_N_BYTES (3), /* DI */
89 COSTS_N_BYTES (5)}, /* other */
90 COSTS_N_BYTES (3), /* cost of movsx */
91 COSTS_N_BYTES (3), /* cost of movzx */
94 2, /* cost for loading QImode using movzbl */
95 {2, 2, 2}, /* cost of loading integer registers
96 in QImode, HImode and SImode.
97 Relative to reg-reg move (2). */
98 {2, 2, 2}, /* cost of storing integer registers */
99 2, /* cost of reg,reg fld/fst */
100 {2, 2, 2}, /* cost of loading fp registers
101 in SFmode, DFmode and XFmode */
102 {2, 2, 2}, /* cost of storing fp registers
103 in SFmode, DFmode and XFmode */
104 3, /* cost of moving MMX register */
105 {3, 3}, /* cost of loading MMX registers
106 in SImode and DImode */
107 {3, 3}, /* cost of storing MMX registers
108 in SImode and DImode */
109 3, /* cost of moving SSE register */
110 {3, 3, 3}, /* cost of loading SSE registers
111 in SImode, DImode and TImode */
112 {3, 3, 3}, /* cost of storing SSE registers
113 in SImode, DImode and TImode */
114 3, /* MMX or SSE register to integer */
115 0, /* size of prefetch block */
116 0, /* number of parallel prefetches */
118 COSTS_N_BYTES (2), /* cost of FADD and FSUB insns. */
119 COSTS_N_BYTES (2), /* cost of FMUL instruction. */
120 COSTS_N_BYTES (2), /* cost of FDIV instruction. */
121 COSTS_N_BYTES (2), /* cost of FABS instruction. */
122 COSTS_N_BYTES (2), /* cost of FCHS instruction. */
123 COSTS_N_BYTES (2), /* cost of FSQRT instruction. */
124 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
125 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
126 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
127 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}}
130 /* Processor costs (relative to an add) */
132 struct processor_costs i386_cost = { /* 386 specific costs */
133 COSTS_N_INSNS (1), /* cost of an add instruction */
134 COSTS_N_INSNS (1), /* cost of a lea instruction */
135 COSTS_N_INSNS (3), /* variable shift costs */
136 COSTS_N_INSNS (2), /* constant shift costs */
137 {COSTS_N_INSNS (6), /* cost of starting multiply for QI */
138 COSTS_N_INSNS (6), /* HI */
139 COSTS_N_INSNS (6), /* SI */
140 COSTS_N_INSNS (6), /* DI */
141 COSTS_N_INSNS (6)}, /* other */
142 COSTS_N_INSNS (1), /* cost of multiply per each bit set */
143 {COSTS_N_INSNS (23), /* cost of a divide/mod for QI */
144 COSTS_N_INSNS (23), /* HI */
145 COSTS_N_INSNS (23), /* SI */
146 COSTS_N_INSNS (23), /* DI */
147 COSTS_N_INSNS (23)}, /* other */
148 COSTS_N_INSNS (3), /* cost of movsx */
149 COSTS_N_INSNS (2), /* cost of movzx */
150 15, /* "large" insn */
152 4, /* cost for loading QImode using movzbl */
153 {2, 4, 2}, /* cost of loading integer registers
154 in QImode, HImode and SImode.
155 Relative to reg-reg move (2). */
156 {2, 4, 2}, /* cost of storing integer registers */
157 2, /* cost of reg,reg fld/fst */
158 {8, 8, 8}, /* cost of loading fp registers
159 in SFmode, DFmode and XFmode */
160 {8, 8, 8}, /* cost of storing fp registers
161 in SFmode, DFmode and XFmode */
162 2, /* cost of moving MMX register */
163 {4, 8}, /* cost of loading MMX registers
164 in SImode and DImode */
165 {4, 8}, /* cost of storing MMX registers
166 in SImode and DImode */
167 2, /* cost of moving SSE register */
168 {4, 8, 16}, /* cost of loading SSE registers
169 in SImode, DImode and TImode */
170 {4, 8, 16}, /* cost of storing SSE registers
171 in SImode, DImode and TImode */
172 3, /* MMX or SSE register to integer */
173 0, /* size of prefetch block */
174 0, /* number of parallel prefetches */
176 COSTS_N_INSNS (23), /* cost of FADD and FSUB insns. */
177 COSTS_N_INSNS (27), /* cost of FMUL instruction. */
178 COSTS_N_INSNS (88), /* cost of FDIV instruction. */
179 COSTS_N_INSNS (22), /* cost of FABS instruction. */
180 COSTS_N_INSNS (24), /* cost of FCHS instruction. */
181 COSTS_N_INSNS (122), /* cost of FSQRT instruction. */
182 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
183 DUMMY_STRINGOP_ALGS},
184 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
185 DUMMY_STRINGOP_ALGS},
189 struct processor_costs i486_cost = { /* 486 specific costs */
190 COSTS_N_INSNS (1), /* cost of an add instruction */
191 COSTS_N_INSNS (1), /* cost of a lea instruction */
192 COSTS_N_INSNS (3), /* variable shift costs */
193 COSTS_N_INSNS (2), /* constant shift costs */
194 {COSTS_N_INSNS (12), /* cost of starting multiply for QI */
195 COSTS_N_INSNS (12), /* HI */
196 COSTS_N_INSNS (12), /* SI */
197 COSTS_N_INSNS (12), /* DI */
198 COSTS_N_INSNS (12)}, /* other */
199 1, /* cost of multiply per each bit set */
200 {COSTS_N_INSNS (40), /* cost of a divide/mod for QI */
201 COSTS_N_INSNS (40), /* HI */
202 COSTS_N_INSNS (40), /* SI */
203 COSTS_N_INSNS (40), /* DI */
204 COSTS_N_INSNS (40)}, /* other */
205 COSTS_N_INSNS (3), /* cost of movsx */
206 COSTS_N_INSNS (2), /* cost of movzx */
207 15, /* "large" insn */
209 4, /* cost for loading QImode using movzbl */
210 {2, 4, 2}, /* cost of loading integer registers
211 in QImode, HImode and SImode.
212 Relative to reg-reg move (2). */
213 {2, 4, 2}, /* cost of storing integer registers */
214 2, /* cost of reg,reg fld/fst */
215 {8, 8, 8}, /* cost of loading fp registers
216 in SFmode, DFmode and XFmode */
217 {8, 8, 8}, /* cost of storing fp registers
218 in SFmode, DFmode and XFmode */
219 2, /* cost of moving MMX register */
220 {4, 8}, /* cost of loading MMX registers
221 in SImode and DImode */
222 {4, 8}, /* cost of storing MMX registers
223 in SImode and DImode */
224 2, /* cost of moving SSE register */
225 {4, 8, 16}, /* cost of loading SSE registers
226 in SImode, DImode and TImode */
227 {4, 8, 16}, /* cost of storing SSE registers
228 in SImode, DImode and TImode */
229 3, /* MMX or SSE register to integer */
230 0, /* size of prefetch block */
231 0, /* number of parallel prefetches */
233 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
234 COSTS_N_INSNS (16), /* cost of FMUL instruction. */
235 COSTS_N_INSNS (73), /* cost of FDIV instruction. */
236 COSTS_N_INSNS (3), /* cost of FABS instruction. */
237 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
238 COSTS_N_INSNS (83), /* cost of FSQRT instruction. */
239 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
240 DUMMY_STRINGOP_ALGS},
241 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
246 struct processor_costs pentium_cost = {
247 COSTS_N_INSNS (1), /* cost of an add instruction */
248 COSTS_N_INSNS (1), /* cost of a lea instruction */
249 COSTS_N_INSNS (4), /* variable shift costs */
250 COSTS_N_INSNS (1), /* constant shift costs */
251 {COSTS_N_INSNS (11), /* cost of starting multiply for QI */
252 COSTS_N_INSNS (11), /* HI */
253 COSTS_N_INSNS (11), /* SI */
254 COSTS_N_INSNS (11), /* DI */
255 COSTS_N_INSNS (11)}, /* other */
256 0, /* cost of multiply per each bit set */
257 {COSTS_N_INSNS (25), /* cost of a divide/mod for QI */
258 COSTS_N_INSNS (25), /* HI */
259 COSTS_N_INSNS (25), /* SI */
260 COSTS_N_INSNS (25), /* DI */
261 COSTS_N_INSNS (25)}, /* other */
262 COSTS_N_INSNS (3), /* cost of movsx */
263 COSTS_N_INSNS (2), /* cost of movzx */
264 8, /* "large" insn */
266 6, /* cost for loading QImode using movzbl */
267 {2, 4, 2}, /* cost of loading integer registers
268 in QImode, HImode and SImode.
269 Relative to reg-reg move (2). */
270 {2, 4, 2}, /* cost of storing integer registers */
271 2, /* cost of reg,reg fld/fst */
272 {2, 2, 6}, /* cost of loading fp registers
273 in SFmode, DFmode and XFmode */
274 {4, 4, 6}, /* cost of storing fp registers
275 in SFmode, DFmode and XFmode */
276 8, /* cost of moving MMX register */
277 {8, 8}, /* cost of loading MMX registers
278 in SImode and DImode */
279 {8, 8}, /* cost of storing MMX registers
280 in SImode and DImode */
281 2, /* cost of moving SSE register */
282 {4, 8, 16}, /* cost of loading SSE registers
283 in SImode, DImode and TImode */
284 {4, 8, 16}, /* cost of storing SSE registers
285 in SImode, DImode and TImode */
286 3, /* MMX or SSE register to integer */
287 0, /* size of prefetch block */
288 0, /* number of parallel prefetches */
290 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
291 COSTS_N_INSNS (3), /* cost of FMUL instruction. */
292 COSTS_N_INSNS (39), /* cost of FDIV instruction. */
293 COSTS_N_INSNS (1), /* cost of FABS instruction. */
294 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
295 COSTS_N_INSNS (70), /* cost of FSQRT instruction. */
296 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
297 DUMMY_STRINGOP_ALGS},
298 {{libcall, {{-1, rep_prefix_4_byte}}},
303 struct processor_costs pentiumpro_cost = {
304 COSTS_N_INSNS (1), /* cost of an add instruction */
305 COSTS_N_INSNS (1), /* cost of a lea instruction */
306 COSTS_N_INSNS (1), /* variable shift costs */
307 COSTS_N_INSNS (1), /* constant shift costs */
308 {COSTS_N_INSNS (4), /* cost of starting multiply for QI */
309 COSTS_N_INSNS (4), /* HI */
310 COSTS_N_INSNS (4), /* SI */
311 COSTS_N_INSNS (4), /* DI */
312 COSTS_N_INSNS (4)}, /* other */
313 0, /* cost of multiply per each bit set */
314 {COSTS_N_INSNS (17), /* cost of a divide/mod for QI */
315 COSTS_N_INSNS (17), /* HI */
316 COSTS_N_INSNS (17), /* SI */
317 COSTS_N_INSNS (17), /* DI */
318 COSTS_N_INSNS (17)}, /* other */
319 COSTS_N_INSNS (1), /* cost of movsx */
320 COSTS_N_INSNS (1), /* cost of movzx */
321 8, /* "large" insn */
323 2, /* cost for loading QImode using movzbl */
324 {4, 4, 4}, /* cost of loading integer registers
325 in QImode, HImode and SImode.
326 Relative to reg-reg move (2). */
327 {2, 2, 2}, /* cost of storing integer registers */
328 2, /* cost of reg,reg fld/fst */
329 {2, 2, 6}, /* cost of loading fp registers
330 in SFmode, DFmode and XFmode */
331 {4, 4, 6}, /* cost of storing fp registers
332 in SFmode, DFmode and XFmode */
333 2, /* cost of moving MMX register */
334 {2, 2}, /* cost of loading MMX registers
335 in SImode and DImode */
336 {2, 2}, /* cost of storing MMX registers
337 in SImode and DImode */
338 2, /* cost of moving SSE register */
339 {2, 2, 8}, /* cost of loading SSE registers
340 in SImode, DImode and TImode */
341 {2, 2, 8}, /* cost of storing SSE registers
342 in SImode, DImode and TImode */
343 3, /* MMX or SSE register to integer */
344 32, /* size of prefetch block */
345 6, /* number of parallel prefetches */
347 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
348 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
349 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
350 COSTS_N_INSNS (2), /* cost of FABS instruction. */
351 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
352 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
353 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes (we ensure
354 the alignment). For small blocks inline loop is still a noticeable win, for bigger
355 blocks either rep movsl or rep movsb is way to go. Rep movsb has apparently
356 more expensive startup time in CPU, but after 4K the difference is down in the noise.
358 {{rep_prefix_4_byte, {{128, loop}, {1024, unrolled_loop},
359 {8192, rep_prefix_4_byte}, {-1, rep_prefix_1_byte}}},
360 DUMMY_STRINGOP_ALGS},
361 {{rep_prefix_4_byte, {{1024, unrolled_loop},
362 {8192, rep_prefix_4_byte}, {-1, libcall}}},
367 struct processor_costs geode_cost = {
368 COSTS_N_INSNS (1), /* cost of an add instruction */
369 COSTS_N_INSNS (1), /* cost of a lea instruction */
370 COSTS_N_INSNS (2), /* variable shift costs */
371 COSTS_N_INSNS (1), /* constant shift costs */
372 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
373 COSTS_N_INSNS (4), /* HI */
374 COSTS_N_INSNS (7), /* SI */
375 COSTS_N_INSNS (7), /* DI */
376 COSTS_N_INSNS (7)}, /* other */
377 0, /* cost of multiply per each bit set */
378 {COSTS_N_INSNS (15), /* cost of a divide/mod for QI */
379 COSTS_N_INSNS (23), /* HI */
380 COSTS_N_INSNS (39), /* SI */
381 COSTS_N_INSNS (39), /* DI */
382 COSTS_N_INSNS (39)}, /* other */
383 COSTS_N_INSNS (1), /* cost of movsx */
384 COSTS_N_INSNS (1), /* cost of movzx */
385 8, /* "large" insn */
387 1, /* cost for loading QImode using movzbl */
388 {1, 1, 1}, /* cost of loading integer registers
389 in QImode, HImode and SImode.
390 Relative to reg-reg move (2). */
391 {1, 1, 1}, /* cost of storing integer registers */
392 1, /* cost of reg,reg fld/fst */
393 {1, 1, 1}, /* cost of loading fp registers
394 in SFmode, DFmode and XFmode */
395 {4, 6, 6}, /* cost of storing fp registers
396 in SFmode, DFmode and XFmode */
398 1, /* cost of moving MMX register */
399 {1, 1}, /* cost of loading MMX registers
400 in SImode and DImode */
401 {1, 1}, /* cost of storing MMX registers
402 in SImode and DImode */
403 1, /* cost of moving SSE register */
404 {1, 1, 1}, /* cost of loading SSE registers
405 in SImode, DImode and TImode */
406 {1, 1, 1}, /* cost of storing SSE registers
407 in SImode, DImode and TImode */
408 1, /* MMX or SSE register to integer */
409 32, /* size of prefetch block */
410 1, /* number of parallel prefetches */
412 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
413 COSTS_N_INSNS (11), /* cost of FMUL instruction. */
414 COSTS_N_INSNS (47), /* cost of FDIV instruction. */
415 COSTS_N_INSNS (1), /* cost of FABS instruction. */
416 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
417 COSTS_N_INSNS (54), /* cost of FSQRT instruction. */
418 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
419 DUMMY_STRINGOP_ALGS},
420 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
425 struct processor_costs k6_cost = {
426 COSTS_N_INSNS (1), /* cost of an add instruction */
427 COSTS_N_INSNS (2), /* cost of a lea instruction */
428 COSTS_N_INSNS (1), /* variable shift costs */
429 COSTS_N_INSNS (1), /* constant shift costs */
430 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
431 COSTS_N_INSNS (3), /* HI */
432 COSTS_N_INSNS (3), /* SI */
433 COSTS_N_INSNS (3), /* DI */
434 COSTS_N_INSNS (3)}, /* other */
435 0, /* cost of multiply per each bit set */
436 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
437 COSTS_N_INSNS (18), /* HI */
438 COSTS_N_INSNS (18), /* SI */
439 COSTS_N_INSNS (18), /* DI */
440 COSTS_N_INSNS (18)}, /* other */
441 COSTS_N_INSNS (2), /* cost of movsx */
442 COSTS_N_INSNS (2), /* cost of movzx */
443 8, /* "large" insn */
445 3, /* cost for loading QImode using movzbl */
446 {4, 5, 4}, /* cost of loading integer registers
447 in QImode, HImode and SImode.
448 Relative to reg-reg move (2). */
449 {2, 3, 2}, /* cost of storing integer registers */
450 4, /* cost of reg,reg fld/fst */
451 {6, 6, 6}, /* cost of loading fp registers
452 in SFmode, DFmode and XFmode */
453 {4, 4, 4}, /* cost of storing fp registers
454 in SFmode, DFmode and XFmode */
455 2, /* cost of moving MMX register */
456 {2, 2}, /* cost of loading MMX registers
457 in SImode and DImode */
458 {2, 2}, /* cost of storing MMX registers
459 in SImode and DImode */
460 2, /* cost of moving SSE register */
461 {2, 2, 8}, /* cost of loading SSE registers
462 in SImode, DImode and TImode */
463 {2, 2, 8}, /* cost of storing SSE registers
464 in SImode, DImode and TImode */
465 6, /* MMX or SSE register to integer */
466 32, /* size of prefetch block */
467 1, /* number of parallel prefetches */
469 COSTS_N_INSNS (2), /* cost of FADD and FSUB insns. */
470 COSTS_N_INSNS (2), /* cost of FMUL instruction. */
471 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
472 COSTS_N_INSNS (2), /* cost of FABS instruction. */
473 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
474 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
475 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
476 DUMMY_STRINGOP_ALGS},
477 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
482 struct processor_costs athlon_cost = {
483 COSTS_N_INSNS (1), /* cost of an add instruction */
484 COSTS_N_INSNS (2), /* cost of a lea instruction */
485 COSTS_N_INSNS (1), /* variable shift costs */
486 COSTS_N_INSNS (1), /* constant shift costs */
487 {COSTS_N_INSNS (5), /* cost of starting multiply for QI */
488 COSTS_N_INSNS (5), /* HI */
489 COSTS_N_INSNS (5), /* SI */
490 COSTS_N_INSNS (5), /* DI */
491 COSTS_N_INSNS (5)}, /* other */
492 0, /* cost of multiply per each bit set */
493 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
494 COSTS_N_INSNS (26), /* HI */
495 COSTS_N_INSNS (42), /* SI */
496 COSTS_N_INSNS (74), /* DI */
497 COSTS_N_INSNS (74)}, /* other */
498 COSTS_N_INSNS (1), /* cost of movsx */
499 COSTS_N_INSNS (1), /* cost of movzx */
500 8, /* "large" insn */
502 4, /* cost for loading QImode using movzbl */
503 {3, 4, 3}, /* cost of loading integer registers
504 in QImode, HImode and SImode.
505 Relative to reg-reg move (2). */
506 {3, 4, 3}, /* cost of storing integer registers */
507 4, /* cost of reg,reg fld/fst */
508 {4, 4, 12}, /* cost of loading fp registers
509 in SFmode, DFmode and XFmode */
510 {6, 6, 8}, /* cost of storing fp registers
511 in SFmode, DFmode and XFmode */
512 2, /* cost of moving MMX register */
513 {4, 4}, /* cost of loading MMX registers
514 in SImode and DImode */
515 {4, 4}, /* cost of storing MMX registers
516 in SImode and DImode */
517 2, /* cost of moving SSE register */
518 {4, 4, 6}, /* cost of loading SSE registers
519 in SImode, DImode and TImode */
520 {4, 4, 5}, /* cost of storing SSE registers
521 in SImode, DImode and TImode */
522 5, /* MMX or SSE register to integer */
523 64, /* size of prefetch block */
524 6, /* number of parallel prefetches */
526 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
527 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
528 COSTS_N_INSNS (24), /* cost of FDIV instruction. */
529 COSTS_N_INSNS (2), /* cost of FABS instruction. */
530 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
531 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
532 /* For some reason, Athlon deals better with REP prefix (relative to loops)
533 compared to K8. Alignment becomes important after 8 bytes for memcpy and
534 128 bytes for memset. */
535 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
536 DUMMY_STRINGOP_ALGS},
537 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
542 struct processor_costs k8_cost = {
543 COSTS_N_INSNS (1), /* cost of an add instruction */
544 COSTS_N_INSNS (2), /* cost of a lea instruction */
545 COSTS_N_INSNS (1), /* variable shift costs */
546 COSTS_N_INSNS (1), /* constant shift costs */
547 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
548 COSTS_N_INSNS (4), /* HI */
549 COSTS_N_INSNS (3), /* SI */
550 COSTS_N_INSNS (4), /* DI */
551 COSTS_N_INSNS (5)}, /* other */
552 0, /* cost of multiply per each bit set */
553 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
554 COSTS_N_INSNS (26), /* HI */
555 COSTS_N_INSNS (42), /* SI */
556 COSTS_N_INSNS (74), /* DI */
557 COSTS_N_INSNS (74)}, /* other */
558 COSTS_N_INSNS (1), /* cost of movsx */
559 COSTS_N_INSNS (1), /* cost of movzx */
560 8, /* "large" insn */
562 4, /* cost for loading QImode using movzbl */
563 {3, 4, 3}, /* cost of loading integer registers
564 in QImode, HImode and SImode.
565 Relative to reg-reg move (2). */
566 {3, 4, 3}, /* cost of storing integer registers */
567 4, /* cost of reg,reg fld/fst */
568 {4, 4, 12}, /* cost of loading fp registers
569 in SFmode, DFmode and XFmode */
570 {6, 6, 8}, /* cost of storing fp registers
571 in SFmode, DFmode and XFmode */
572 2, /* cost of moving MMX register */
573 {3, 3}, /* cost of loading MMX registers
574 in SImode and DImode */
575 {4, 4}, /* cost of storing MMX registers
576 in SImode and DImode */
577 2, /* cost of moving SSE register */
578 {4, 3, 6}, /* cost of loading SSE registers
579 in SImode, DImode and TImode */
580 {4, 4, 5}, /* cost of storing SSE registers
581 in SImode, DImode and TImode */
582 5, /* MMX or SSE register to integer */
583 64, /* size of prefetch block */
584 /* New AMD processors never drop prefetches; if they cannot be performed
585 immediately, they are queued. We set number of simultaneous prefetches
586 to a large constant to reflect this (it probably is not a good idea not
587 to limit number of prefetches at all, as their execution also takes some
589 100, /* number of parallel prefetches */
591 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
592 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
593 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
594 COSTS_N_INSNS (2), /* cost of FABS instruction. */
595 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
596 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
597 /* K8 has optimized REP instruction for medium sized blocks, but for very small
598 blocks it is better to use loop. For large blocks, libcall can do
599 nontemporary accesses and beat inline considerably. */
600 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
601 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
602 {{libcall, {{8, loop}, {24, unrolled_loop},
603 {2048, rep_prefix_4_byte}, {-1, libcall}}},
604 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}}
608 struct processor_costs pentium4_cost = {
609 COSTS_N_INSNS (1), /* cost of an add instruction */
610 COSTS_N_INSNS (3), /* cost of a lea instruction */
611 COSTS_N_INSNS (4), /* variable shift costs */
612 COSTS_N_INSNS (4), /* constant shift costs */
613 {COSTS_N_INSNS (15), /* cost of starting multiply for QI */
614 COSTS_N_INSNS (15), /* HI */
615 COSTS_N_INSNS (15), /* SI */
616 COSTS_N_INSNS (15), /* DI */
617 COSTS_N_INSNS (15)}, /* other */
618 0, /* cost of multiply per each bit set */
619 {COSTS_N_INSNS (56), /* cost of a divide/mod for QI */
620 COSTS_N_INSNS (56), /* HI */
621 COSTS_N_INSNS (56), /* SI */
622 COSTS_N_INSNS (56), /* DI */
623 COSTS_N_INSNS (56)}, /* other */
624 COSTS_N_INSNS (1), /* cost of movsx */
625 COSTS_N_INSNS (1), /* cost of movzx */
626 16, /* "large" insn */
628 2, /* cost for loading QImode using movzbl */
629 {4, 5, 4}, /* cost of loading integer registers
630 in QImode, HImode and SImode.
631 Relative to reg-reg move (2). */
632 {2, 3, 2}, /* cost of storing integer registers */
633 2, /* cost of reg,reg fld/fst */
634 {2, 2, 6}, /* cost of loading fp registers
635 in SFmode, DFmode and XFmode */
636 {4, 4, 6}, /* cost of storing fp registers
637 in SFmode, DFmode and XFmode */
638 2, /* cost of moving MMX register */
639 {2, 2}, /* cost of loading MMX registers
640 in SImode and DImode */
641 {2, 2}, /* cost of storing MMX registers
642 in SImode and DImode */
643 12, /* cost of moving SSE register */
644 {12, 12, 12}, /* cost of loading SSE registers
645 in SImode, DImode and TImode */
646 {2, 2, 8}, /* cost of storing SSE registers
647 in SImode, DImode and TImode */
648 10, /* MMX or SSE register to integer */
649 64, /* size of prefetch block */
650 6, /* number of parallel prefetches */
652 COSTS_N_INSNS (5), /* cost of FADD and FSUB insns. */
653 COSTS_N_INSNS (7), /* cost of FMUL instruction. */
654 COSTS_N_INSNS (43), /* cost of FDIV instruction. */
655 COSTS_N_INSNS (2), /* cost of FABS instruction. */
656 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
657 COSTS_N_INSNS (43), /* cost of FSQRT instruction. */
658 {{libcall, {{12, loop_1_byte}, {64, loop}, {-1, rep_prefix_4_byte}}},
659 DUMMY_STRINGOP_ALGS},
660 {{libcall, {{6, loop_1_byte}, {64, loop}, {20480, rep_prefix_4_byte},
662 DUMMY_STRINGOP_ALGS},
666 struct processor_costs nocona_cost = {
667 COSTS_N_INSNS (1), /* cost of an add instruction */
668 COSTS_N_INSNS (1), /* cost of a lea instruction */
669 COSTS_N_INSNS (1), /* variable shift costs */
670 COSTS_N_INSNS (1), /* constant shift costs */
671 {COSTS_N_INSNS (10), /* cost of starting multiply for QI */
672 COSTS_N_INSNS (10), /* HI */
673 COSTS_N_INSNS (10), /* SI */
674 COSTS_N_INSNS (10), /* DI */
675 COSTS_N_INSNS (10)}, /* other */
676 0, /* cost of multiply per each bit set */
677 {COSTS_N_INSNS (66), /* cost of a divide/mod for QI */
678 COSTS_N_INSNS (66), /* HI */
679 COSTS_N_INSNS (66), /* SI */
680 COSTS_N_INSNS (66), /* DI */
681 COSTS_N_INSNS (66)}, /* other */
682 COSTS_N_INSNS (1), /* cost of movsx */
683 COSTS_N_INSNS (1), /* cost of movzx */
684 16, /* "large" insn */
686 4, /* cost for loading QImode using movzbl */
687 {4, 4, 4}, /* cost of loading integer registers
688 in QImode, HImode and SImode.
689 Relative to reg-reg move (2). */
690 {4, 4, 4}, /* cost of storing integer registers */
691 3, /* cost of reg,reg fld/fst */
692 {12, 12, 12}, /* cost of loading fp registers
693 in SFmode, DFmode and XFmode */
694 {4, 4, 4}, /* cost of storing fp registers
695 in SFmode, DFmode and XFmode */
696 6, /* cost of moving MMX register */
697 {12, 12}, /* cost of loading MMX registers
698 in SImode and DImode */
699 {12, 12}, /* cost of storing MMX registers
700 in SImode and DImode */
701 6, /* cost of moving SSE register */
702 {12, 12, 12}, /* cost of loading SSE registers
703 in SImode, DImode and TImode */
704 {12, 12, 12}, /* cost of storing SSE registers
705 in SImode, DImode and TImode */
706 8, /* MMX or SSE register to integer */
707 128, /* size of prefetch block */
708 8, /* number of parallel prefetches */
710 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
711 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
712 COSTS_N_INSNS (40), /* cost of FDIV instruction. */
713 COSTS_N_INSNS (3), /* cost of FABS instruction. */
714 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
715 COSTS_N_INSNS (44), /* cost of FSQRT instruction. */
716 {{libcall, {{12, loop_1_byte}, {64, loop}, {-1, rep_prefix_4_byte}}},
717 {libcall, {{32, loop}, {20000, rep_prefix_8_byte},
718 {100000, unrolled_loop}, {-1, libcall}}}},
719 {{libcall, {{6, loop_1_byte}, {64, loop}, {20480, rep_prefix_4_byte},
721 {libcall, {{24, loop}, {64, unrolled_loop},
722 {8192, rep_prefix_8_byte}, {-1, libcall}}}}
726 struct processor_costs core2_cost = {
727 COSTS_N_INSNS (1), /* cost of an add instruction */
728 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
729 COSTS_N_INSNS (1), /* variable shift costs */
730 COSTS_N_INSNS (1), /* constant shift costs */
731 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
732 COSTS_N_INSNS (3), /* HI */
733 COSTS_N_INSNS (3), /* SI */
734 COSTS_N_INSNS (3), /* DI */
735 COSTS_N_INSNS (3)}, /* other */
736 0, /* cost of multiply per each bit set */
737 {COSTS_N_INSNS (22), /* cost of a divide/mod for QI */
738 COSTS_N_INSNS (22), /* HI */
739 COSTS_N_INSNS (22), /* SI */
740 COSTS_N_INSNS (22), /* DI */
741 COSTS_N_INSNS (22)}, /* other */
742 COSTS_N_INSNS (1), /* cost of movsx */
743 COSTS_N_INSNS (1), /* cost of movzx */
744 8, /* "large" insn */
746 2, /* cost for loading QImode using movzbl */
747 {6, 6, 6}, /* cost of loading integer registers
748 in QImode, HImode and SImode.
749 Relative to reg-reg move (2). */
750 {4, 4, 4}, /* cost of storing integer registers */
751 2, /* cost of reg,reg fld/fst */
752 {6, 6, 6}, /* cost of loading fp registers
753 in SFmode, DFmode and XFmode */
754 {4, 4, 4}, /* cost of loading integer registers */
755 2, /* cost of moving MMX register */
756 {6, 6}, /* cost of loading MMX registers
757 in SImode and DImode */
758 {4, 4}, /* cost of storing MMX registers
759 in SImode and DImode */
760 2, /* cost of moving SSE register */
761 {6, 6, 6}, /* cost of loading SSE registers
762 in SImode, DImode and TImode */
763 {4, 4, 4}, /* cost of storing SSE registers
764 in SImode, DImode and TImode */
765 2, /* MMX or SSE register to integer */
766 128, /* size of prefetch block */
767 8, /* number of parallel prefetches */
769 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
770 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
771 COSTS_N_INSNS (32), /* cost of FDIV instruction. */
772 COSTS_N_INSNS (1), /* cost of FABS instruction. */
773 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
774 COSTS_N_INSNS (58), /* cost of FSQRT instruction. */
775 {{libcall, {{11, loop}, {-1, rep_prefix_4_byte}}},
776 {libcall, {{32, loop}, {64, rep_prefix_4_byte},
777 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
778 {{libcall, {{8, loop}, {15, unrolled_loop},
779 {2048, rep_prefix_4_byte}, {-1, libcall}}},
780 {libcall, {{24, loop}, {32, unrolled_loop},
781 {8192, rep_prefix_8_byte}, {-1, libcall}}}}
784 /* Generic64 should produce code tuned for Nocona and K8. */
786 struct processor_costs generic64_cost = {
787 COSTS_N_INSNS (1), /* cost of an add instruction */
788 /* On all chips taken into consideration lea is 2 cycles and more. With
789 this cost however our current implementation of synth_mult results in
790 use of unnecessary temporary registers causing regression on several
791 SPECfp benchmarks. */
792 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
793 COSTS_N_INSNS (1), /* variable shift costs */
794 COSTS_N_INSNS (1), /* constant shift costs */
795 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
796 COSTS_N_INSNS (4), /* HI */
797 COSTS_N_INSNS (3), /* SI */
798 COSTS_N_INSNS (4), /* DI */
799 COSTS_N_INSNS (2)}, /* other */
800 0, /* cost of multiply per each bit set */
801 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
802 COSTS_N_INSNS (26), /* HI */
803 COSTS_N_INSNS (42), /* SI */
804 COSTS_N_INSNS (74), /* DI */
805 COSTS_N_INSNS (74)}, /* other */
806 COSTS_N_INSNS (1), /* cost of movsx */
807 COSTS_N_INSNS (1), /* cost of movzx */
808 8, /* "large" insn */
810 4, /* cost for loading QImode using movzbl */
811 {4, 4, 4}, /* cost of loading integer registers
812 in QImode, HImode and SImode.
813 Relative to reg-reg move (2). */
814 {4, 4, 4}, /* cost of storing integer registers */
815 4, /* cost of reg,reg fld/fst */
816 {12, 12, 12}, /* cost of loading fp registers
817 in SFmode, DFmode and XFmode */
818 {6, 6, 8}, /* cost of storing fp registers
819 in SFmode, DFmode and XFmode */
820 2, /* cost of moving MMX register */
821 {8, 8}, /* cost of loading MMX registers
822 in SImode and DImode */
823 {8, 8}, /* cost of storing MMX registers
824 in SImode and DImode */
825 2, /* cost of moving SSE register */
826 {8, 8, 8}, /* cost of loading SSE registers
827 in SImode, DImode and TImode */
828 {8, 8, 8}, /* cost of storing SSE registers
829 in SImode, DImode and TImode */
830 5, /* MMX or SSE register to integer */
831 64, /* size of prefetch block */
832 6, /* number of parallel prefetches */
833 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this value
834 is increased to perhaps more appropriate value of 5. */
836 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
837 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
838 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
839 COSTS_N_INSNS (8), /* cost of FABS instruction. */
840 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
841 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
842 {DUMMY_STRINGOP_ALGS,
843 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
844 {DUMMY_STRINGOP_ALGS,
845 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}}
848 /* Generic32 should produce code tuned for Athlon, PPro, Pentium4, Nocona and K8. */
850 struct processor_costs generic32_cost = {
851 COSTS_N_INSNS (1), /* cost of an add instruction */
852 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
853 COSTS_N_INSNS (1), /* variable shift costs */
854 COSTS_N_INSNS (1), /* constant shift costs */
855 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
856 COSTS_N_INSNS (4), /* HI */
857 COSTS_N_INSNS (3), /* SI */
858 COSTS_N_INSNS (4), /* DI */
859 COSTS_N_INSNS (2)}, /* other */
860 0, /* cost of multiply per each bit set */
861 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
862 COSTS_N_INSNS (26), /* HI */
863 COSTS_N_INSNS (42), /* SI */
864 COSTS_N_INSNS (74), /* DI */
865 COSTS_N_INSNS (74)}, /* other */
866 COSTS_N_INSNS (1), /* cost of movsx */
867 COSTS_N_INSNS (1), /* cost of movzx */
868 8, /* "large" insn */
870 4, /* cost for loading QImode using movzbl */
871 {4, 4, 4}, /* cost of loading integer registers
872 in QImode, HImode and SImode.
873 Relative to reg-reg move (2). */
874 {4, 4, 4}, /* cost of storing integer registers */
875 4, /* cost of reg,reg fld/fst */
876 {12, 12, 12}, /* cost of loading fp registers
877 in SFmode, DFmode and XFmode */
878 {6, 6, 8}, /* cost of storing fp registers
879 in SFmode, DFmode and XFmode */
880 2, /* cost of moving MMX register */
881 {8, 8}, /* cost of loading MMX registers
882 in SImode and DImode */
883 {8, 8}, /* cost of storing MMX registers
884 in SImode and DImode */
885 2, /* cost of moving SSE register */
886 {8, 8, 8}, /* cost of loading SSE registers
887 in SImode, DImode and TImode */
888 {8, 8, 8}, /* cost of storing SSE registers
889 in SImode, DImode and TImode */
890 5, /* MMX or SSE register to integer */
891 64, /* size of prefetch block */
892 6, /* number of parallel prefetches */
894 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
895 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
896 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
897 COSTS_N_INSNS (8), /* cost of FABS instruction. */
898 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
899 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
900 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
901 DUMMY_STRINGOP_ALGS},
902 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
903 DUMMY_STRINGOP_ALGS},
906 const struct processor_costs *ix86_cost = &pentium_cost;
908 /* Processor feature/optimization bitmasks. */
909 #define m_386 (1<<PROCESSOR_I386)
910 #define m_486 (1<<PROCESSOR_I486)
911 #define m_PENT (1<<PROCESSOR_PENTIUM)
912 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
913 #define m_GEODE (1<<PROCESSOR_GEODE)
914 #define m_K6_GEODE (m_K6 | m_GEODE)
915 #define m_K6 (1<<PROCESSOR_K6)
916 #define m_ATHLON (1<<PROCESSOR_ATHLON)
917 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
918 #define m_K8 (1<<PROCESSOR_K8)
919 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
920 #define m_NOCONA (1<<PROCESSOR_NOCONA)
921 #define m_CORE2 (1<<PROCESSOR_CORE2)
922 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
923 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
924 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
926 /* Generic instruction choice should be common subset of supported CPUs
927 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
929 /* Leave is not affecting Nocona SPEC2000 results negatively, so enabling for
930 Generic64 seems like good code size tradeoff. We can't enable it for 32bit
931 generic because it is not working well with PPro base chips. */
932 const int x86_use_leave = m_386 | m_K6_GEODE | m_ATHLON_K8 | m_CORE2 | m_GENERIC64;
933 const int x86_push_memory = m_386 | m_K6_GEODE | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
934 const int x86_zero_extend_with_and = m_486 | m_PENT;
935 const int x86_movx = m_ATHLON_K8 | m_PPRO | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC | m_GEODE /* m_386 | m_K6 */;
936 const int x86_double_with_add = ~m_386;
937 const int x86_use_bit_test = m_386;
938 const int x86_unroll_strlen = m_486 | m_PENT | m_PPRO | m_ATHLON_K8 | m_K6 | m_CORE2 | m_GENERIC;
939 const int x86_cmove = m_PPRO | m_GEODE | m_ATHLON_K8 | m_PENT4 | m_NOCONA;
940 const int x86_3dnow_a = m_ATHLON_K8;
941 const int x86_deep_branch = m_PPRO | m_K6_GEODE | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
942 /* Branch hints were put in P4 based on simulation result. But
943 after P4 was made, no performance benefit was observed with
944 branch hints. It also increases the code size. As the result,
945 icc never generates branch hints. */
946 const int x86_branch_hints = 0;
947 const int x86_use_sahf = m_PPRO | m_K6_GEODE | m_PENT4 | m_NOCONA | m_GENERIC32; /*m_GENERIC | m_ATHLON_K8 ? */
948 /* We probably ought to watch for partial register stalls on Generic32
949 compilation setting as well. However in current implementation the
950 partial register stalls are not eliminated very well - they can
951 be introduced via subregs synthesized by combine and can happen
952 in caller/callee saving sequences.
953 Because this option pays back little on PPro based chips and is in conflict
954 with partial reg. dependencies used by Athlon/P4 based chips, it is better
955 to leave it off for generic32 for now. */
956 const int x86_partial_reg_stall = m_PPRO;
957 const int x86_partial_flag_reg_stall = m_CORE2 | m_GENERIC;
958 const int x86_use_himode_fiop = m_386 | m_486 | m_K6_GEODE;
959 const int x86_use_simode_fiop = ~(m_PPRO | m_ATHLON_K8 | m_PENT | m_CORE2 | m_GENERIC);
960 const int x86_use_mov0 = m_K6;
961 const int x86_use_cltd = ~(m_PENT | m_K6 | m_CORE2 | m_GENERIC);
962 const int x86_read_modify_write = ~m_PENT;
963 const int x86_read_modify = ~(m_PENT | m_PPRO);
964 const int x86_split_long_moves = m_PPRO;
965 const int x86_promote_QImode = m_K6_GEODE | m_PENT | m_386 | m_486 | m_ATHLON_K8 | m_CORE2 | m_GENERIC; /* m_PENT4 ? */
966 const int x86_fast_prefix = ~(m_PENT | m_486 | m_386);
967 const int x86_single_stringop = m_386 | m_PENT4 | m_NOCONA;
968 const int x86_qimode_math = ~(0);
969 const int x86_promote_qi_regs = 0;
970 /* On PPro this flag is meant to avoid partial register stalls. Just like
971 the x86_partial_reg_stall this option might be considered for Generic32
972 if our scheme for avoiding partial stalls was more effective. */
973 const int x86_himode_math = ~(m_PPRO);
974 const int x86_promote_hi_regs = m_PPRO;
975 const int x86_sub_esp_4 = m_ATHLON_K8 | m_PPRO | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
976 const int x86_sub_esp_8 = m_ATHLON_K8 | m_PPRO | m_386 | m_486 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
977 const int x86_add_esp_4 = m_ATHLON_K8 | m_K6_GEODE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
978 const int x86_add_esp_8 = m_ATHLON_K8 | m_PPRO | m_K6_GEODE | m_386 | m_486 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
979 const int x86_integer_DFmode_moves = ~(m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC | m_GEODE);
980 const int x86_partial_reg_dependency = m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
981 const int x86_memory_mismatch_stall = m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
982 const int x86_accumulate_outgoing_args = m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC;
983 const int x86_prologue_using_move = m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC;
984 const int x86_epilogue_using_move = m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC;
985 const int x86_shift1 = ~m_486;
986 const int x86_arch_always_fancy_math_387 = m_PENT | m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
987 /* In Generic model we have an conflict here in between PPro/Pentium4 based chips
988 that thread 128bit SSE registers as single units versus K8 based chips that
989 divide SSE registers to two 64bit halves.
990 x86_sse_partial_reg_dependency promote all store destinations to be 128bit
991 to allow register renaming on 128bit SSE units, but usually results in one
992 extra microop on 64bit SSE units. Experimental results shows that disabling
993 this option on P4 brings over 20% SPECfp regression, while enabling it on
994 K8 brings roughly 2.4% regression that can be partly masked by careful scheduling
996 const int x86_sse_partial_reg_dependency = m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC;
997 /* Set for machines where the type and dependencies are resolved on SSE
998 register parts instead of whole registers, so we may maintain just
999 lower part of scalar values in proper format leaving the upper part
1001 const int x86_sse_split_regs = m_ATHLON_K8;
1002 const int x86_sse_typeless_stores = m_ATHLON_K8;
1003 const int x86_sse_load0_by_pxor = m_PPRO | m_PENT4 | m_NOCONA;
1004 const int x86_use_ffreep = m_ATHLON_K8;
1005 const int x86_use_incdec = ~(m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC);
1007 /* ??? Allowing interunit moves makes it all too easy for the compiler to put
1008 integer data in xmm registers. Which results in pretty abysmal code. */
1009 const int x86_inter_unit_moves = 0 /* ~(m_ATHLON_K8) */;
1011 const int x86_ext_80387_constants = m_K6_GEODE | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC;
1012 /* Some CPU cores are not able to predict more than 4 branch instructions in
1013 the 16 byte window. */
1014 const int x86_four_jump_limit = m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
1015 const int x86_schedule = m_PPRO | m_ATHLON_K8 | m_K6_GEODE | m_PENT | m_CORE2 | m_GENERIC;
1016 const int x86_use_bt = m_ATHLON_K8;
1017 /* Compare and exchange was added for 80486. */
1018 const int x86_cmpxchg = ~m_386;
1019 /* Compare and exchange 8 bytes was added for pentium. */
1020 const int x86_cmpxchg8b = ~(m_386 | m_486);
1021 /* Compare and exchange 16 bytes was added for nocona. */
1022 const int x86_cmpxchg16b = m_NOCONA;
1023 /* Exchange and add was added for 80486. */
1024 const int x86_xadd = ~m_386;
1025 /* Byteswap was added for 80486. */
1026 const int x86_bswap = ~m_386;
1027 const int x86_pad_returns = m_ATHLON_K8 | m_CORE2 | m_GENERIC;
1029 static enum stringop_alg stringop_alg = no_stringop;
1031 /* In case the average insn count for single function invocation is
1032 lower than this constant, emit fast (but longer) prologue and
1034 #define FAST_PROLOGUE_INSN_COUNT 20
1036 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
1037 static const char *const qi_reg_name[] = QI_REGISTER_NAMES;
1038 static const char *const qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
1039 static const char *const hi_reg_name[] = HI_REGISTER_NAMES;
1041 /* Array of the smallest class containing reg number REGNO, indexed by
1042 REGNO. Used by REGNO_REG_CLASS in i386.h. */
1044 enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] =
1046 /* ax, dx, cx, bx */
1047 AREG, DREG, CREG, BREG,
1048 /* si, di, bp, sp */
1049 SIREG, DIREG, NON_Q_REGS, NON_Q_REGS,
1051 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
1052 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
1055 /* flags, fpsr, fpcr, dirflag, frame */
1056 NO_REGS, NO_REGS, NO_REGS, NO_REGS, NON_Q_REGS,
1057 SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1059 MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS,
1061 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1062 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1063 SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1067 /* The "default" register map used in 32bit mode. */
1069 int const dbx_register_map[FIRST_PSEUDO_REGISTER] =
1071 0, 2, 1, 3, 6, 7, 4, 5, /* general regs */
1072 12, 13, 14, 15, 16, 17, 18, 19, /* fp regs */
1073 -1, -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, dir, frame */
1074 21, 22, 23, 24, 25, 26, 27, 28, /* SSE */
1075 29, 30, 31, 32, 33, 34, 35, 36, /* MMX */
1076 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1077 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1080 static int const x86_64_int_parameter_registers[6] =
1082 5 /*RDI*/, 4 /*RSI*/, 1 /*RDX*/, 2 /*RCX*/,
1083 FIRST_REX_INT_REG /*R8 */, FIRST_REX_INT_REG + 1 /*R9 */
1086 static int const x86_64_int_return_registers[4] =
1088 0 /*RAX*/, 1 /*RDI*/, 5 /*RDI*/, 4 /*RSI*/
1091 /* The "default" register map used in 64bit mode. */
1092 int const dbx64_register_map[FIRST_PSEUDO_REGISTER] =
1094 0, 1, 2, 3, 4, 5, 6, 7, /* general regs */
1095 33, 34, 35, 36, 37, 38, 39, 40, /* fp regs */
1096 -1, -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, dir, frame */
1097 17, 18, 19, 20, 21, 22, 23, 24, /* SSE */
1098 41, 42, 43, 44, 45, 46, 47, 48, /* MMX */
1099 8,9,10,11,12,13,14,15, /* extended integer registers */
1100 25, 26, 27, 28, 29, 30, 31, 32, /* extended SSE registers */
1103 /* Define the register numbers to be used in Dwarf debugging information.
1104 The SVR4 reference port C compiler uses the following register numbers
1105 in its Dwarf output code:
1106 0 for %eax (gcc regno = 0)
1107 1 for %ecx (gcc regno = 2)
1108 2 for %edx (gcc regno = 1)
1109 3 for %ebx (gcc regno = 3)
1110 4 for %esp (gcc regno = 7)
1111 5 for %ebp (gcc regno = 6)
1112 6 for %esi (gcc regno = 4)
1113 7 for %edi (gcc regno = 5)
1114 The following three DWARF register numbers are never generated by
1115 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
1116 believes these numbers have these meanings.
1117 8 for %eip (no gcc equivalent)
1118 9 for %eflags (gcc regno = 17)
1119 10 for %trapno (no gcc equivalent)
1120 It is not at all clear how we should number the FP stack registers
1121 for the x86 architecture. If the version of SDB on x86/svr4 were
1122 a bit less brain dead with respect to floating-point then we would
1123 have a precedent to follow with respect to DWARF register numbers
1124 for x86 FP registers, but the SDB on x86/svr4 is so completely
1125 broken with respect to FP registers that it is hardly worth thinking
1126 of it as something to strive for compatibility with.
1127 The version of x86/svr4 SDB I have at the moment does (partially)
1128 seem to believe that DWARF register number 11 is associated with
1129 the x86 register %st(0), but that's about all. Higher DWARF
1130 register numbers don't seem to be associated with anything in
1131 particular, and even for DWARF regno 11, SDB only seems to under-
1132 stand that it should say that a variable lives in %st(0) (when
1133 asked via an `=' command) if we said it was in DWARF regno 11,
1134 but SDB still prints garbage when asked for the value of the
1135 variable in question (via a `/' command).
1136 (Also note that the labels SDB prints for various FP stack regs
1137 when doing an `x' command are all wrong.)
1138 Note that these problems generally don't affect the native SVR4
1139 C compiler because it doesn't allow the use of -O with -g and
1140 because when it is *not* optimizing, it allocates a memory
1141 location for each floating-point variable, and the memory
1142 location is what gets described in the DWARF AT_location
1143 attribute for the variable in question.
1144 Regardless of the severe mental illness of the x86/svr4 SDB, we
1145 do something sensible here and we use the following DWARF
1146 register numbers. Note that these are all stack-top-relative
1148 11 for %st(0) (gcc regno = 8)
1149 12 for %st(1) (gcc regno = 9)
1150 13 for %st(2) (gcc regno = 10)
1151 14 for %st(3) (gcc regno = 11)
1152 15 for %st(4) (gcc regno = 12)
1153 16 for %st(5) (gcc regno = 13)
1154 17 for %st(6) (gcc regno = 14)
1155 18 for %st(7) (gcc regno = 15)
1157 int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER] =
1159 0, 2, 1, 3, 6, 7, 5, 4, /* general regs */
1160 11, 12, 13, 14, 15, 16, 17, 18, /* fp regs */
1161 -1, 9, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, dir, frame */
1162 21, 22, 23, 24, 25, 26, 27, 28, /* SSE registers */
1163 29, 30, 31, 32, 33, 34, 35, 36, /* MMX registers */
1164 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1165 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1168 /* Test and compare insns in i386.md store the information needed to
1169 generate branch and scc insns here. */
1171 rtx ix86_compare_op0 = NULL_RTX;
1172 rtx ix86_compare_op1 = NULL_RTX;
1173 rtx ix86_compare_emitted = NULL_RTX;
1175 /* Size of the register save area. */
1176 #define X86_64_VARARGS_SIZE (REGPARM_MAX * UNITS_PER_WORD + SSE_REGPARM_MAX * 16)
1178 /* Define the structure for the machine field in struct function. */
1180 struct stack_local_entry GTY(())
1182 unsigned short mode;
1185 struct stack_local_entry *next;
1188 /* Structure describing stack frame layout.
1189 Stack grows downward:
1195 saved frame pointer if frame_pointer_needed
1196 <- HARD_FRAME_POINTER
1201 [va_arg registers] (
1202 > to_allocate <- FRAME_POINTER
1212 HOST_WIDE_INT frame;
1214 int outgoing_arguments_size;
1217 HOST_WIDE_INT to_allocate;
1218 /* The offsets relative to ARG_POINTER. */
1219 HOST_WIDE_INT frame_pointer_offset;
1220 HOST_WIDE_INT hard_frame_pointer_offset;
1221 HOST_WIDE_INT stack_pointer_offset;
1223 /* When save_regs_using_mov is set, emit prologue using
1224 move instead of push instructions. */
1225 bool save_regs_using_mov;
1228 /* Code model option. */
1229 enum cmodel ix86_cmodel;
1231 enum asm_dialect ix86_asm_dialect = ASM_ATT;
1233 enum tls_dialect ix86_tls_dialect = TLS_DIALECT_GNU;
1235 /* Which unit we are generating floating point math for. */
1236 enum fpmath_unit ix86_fpmath;
1238 /* Which cpu are we scheduling for. */
1239 enum processor_type ix86_tune;
1240 /* Which instruction set architecture to use. */
1241 enum processor_type ix86_arch;
1243 /* true if sse prefetch instruction is not NOOP. */
1244 int x86_prefetch_sse;
1246 /* ix86_regparm_string as a number */
1247 static int ix86_regparm;
1249 /* -mstackrealign option */
1250 extern int ix86_force_align_arg_pointer;
1251 static const char ix86_force_align_arg_pointer_string[] = "force_align_arg_pointer";
1253 /* Preferred alignment for stack boundary in bits. */
1254 unsigned int ix86_preferred_stack_boundary;
1256 /* Values 1-5: see jump.c */
1257 int ix86_branch_cost;
1259 /* Variables which are this size or smaller are put in the data/bss
1260 or ldata/lbss sections. */
1262 int ix86_section_threshold = 65536;
1264 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
1265 char internal_label_prefix[16];
1266 int internal_label_prefix_len;
1268 static bool ix86_handle_option (size_t, const char *, int);
1269 static void output_pic_addr_const (FILE *, rtx, int);
1270 static void put_condition_code (enum rtx_code, enum machine_mode,
1272 static const char *get_some_local_dynamic_name (void);
1273 static int get_some_local_dynamic_name_1 (rtx *, void *);
1274 static rtx ix86_expand_int_compare (enum rtx_code, rtx, rtx);
1275 static enum rtx_code ix86_prepare_fp_compare_args (enum rtx_code, rtx *,
1277 static bool ix86_fixed_condition_code_regs (unsigned int *, unsigned int *);
1278 static enum machine_mode ix86_cc_modes_compatible (enum machine_mode,
1280 static rtx get_thread_pointer (int);
1281 static rtx legitimize_tls_address (rtx, enum tls_model, int);
1282 static void get_pc_thunk_name (char [32], unsigned int);
1283 static rtx gen_push (rtx);
1284 static int ix86_flags_dependent (rtx, rtx, enum attr_type);
1285 static int ix86_agi_dependent (rtx, rtx, enum attr_type);
1286 static struct machine_function * ix86_init_machine_status (void);
1287 static int ix86_split_to_parts (rtx, rtx *, enum machine_mode);
1288 static int ix86_nsaved_regs (void);
1289 static void ix86_emit_save_regs (void);
1290 static void ix86_emit_save_regs_using_mov (rtx, HOST_WIDE_INT);
1291 static void ix86_emit_restore_regs_using_mov (rtx, HOST_WIDE_INT, int);
1292 static void ix86_output_function_epilogue (FILE *, HOST_WIDE_INT);
1293 static HOST_WIDE_INT ix86_GOT_alias_set (void);
1294 static void ix86_adjust_counter (rtx, HOST_WIDE_INT);
1295 static void ix86_expand_strlensi_unroll_1 (rtx, rtx, rtx);
1296 static int ix86_issue_rate (void);
1297 static int ix86_adjust_cost (rtx, rtx, rtx, int);
1298 static int ia32_multipass_dfa_lookahead (void);
1299 static void ix86_init_mmx_sse_builtins (void);
1300 static rtx x86_this_parameter (tree);
1301 static void x86_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
1302 HOST_WIDE_INT, tree);
1303 static bool x86_can_output_mi_thunk (tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
1304 static void x86_file_start (void);
1305 static void ix86_reorg (void);
1306 static bool ix86_expand_carry_flag_compare (enum rtx_code, rtx, rtx, rtx*);
1307 static tree ix86_build_builtin_va_list (void);
1308 static void ix86_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
1310 static tree ix86_gimplify_va_arg (tree, tree, tree *, tree *);
1311 static bool ix86_scalar_mode_supported_p (enum machine_mode);
1312 static bool ix86_vector_mode_supported_p (enum machine_mode);
1314 static int ix86_address_cost (rtx);
1315 static bool ix86_cannot_force_const_mem (rtx);
1316 static rtx ix86_delegitimize_address (rtx);
1318 static void i386_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
1320 struct builtin_description;
1321 static rtx ix86_expand_sse_comi (const struct builtin_description *,
1323 static rtx ix86_expand_sse_compare (const struct builtin_description *,
1325 static rtx ix86_expand_unop1_builtin (enum insn_code, tree, rtx);
1326 static rtx ix86_expand_unop_builtin (enum insn_code, tree, rtx, int);
1327 static rtx ix86_expand_binop_builtin (enum insn_code, tree, rtx);
1328 static rtx ix86_expand_store_builtin (enum insn_code, tree);
1329 static rtx safe_vector_operand (rtx, enum machine_mode);
1330 static rtx ix86_expand_fp_compare (enum rtx_code, rtx, rtx, rtx, rtx *, rtx *);
1331 static int ix86_fp_comparison_arithmetics_cost (enum rtx_code code);
1332 static int ix86_fp_comparison_fcomi_cost (enum rtx_code code);
1333 static int ix86_fp_comparison_sahf_cost (enum rtx_code code);
1334 static int ix86_fp_comparison_cost (enum rtx_code code);
1335 static unsigned int ix86_select_alt_pic_regnum (void);
1336 static int ix86_save_reg (unsigned int, int);
1337 static void ix86_compute_frame_layout (struct ix86_frame *);
1338 static int ix86_comp_type_attributes (tree, tree);
1339 static int ix86_function_regparm (tree, tree);
1340 const struct attribute_spec ix86_attribute_table[];
1341 static bool ix86_function_ok_for_sibcall (tree, tree);
1342 static tree ix86_handle_cconv_attribute (tree *, tree, tree, int, bool *);
1343 static int ix86_value_regno (enum machine_mode, tree, tree);
1344 static bool contains_128bit_aligned_vector_p (tree);
1345 static rtx ix86_struct_value_rtx (tree, int);
1346 static bool ix86_ms_bitfield_layout_p (tree);
1347 static tree ix86_handle_struct_attribute (tree *, tree, tree, int, bool *);
1348 static int extended_reg_mentioned_1 (rtx *, void *);
1349 static bool ix86_rtx_costs (rtx, int, int, int *);
1350 static int min_insn_size (rtx);
1351 static tree ix86_md_asm_clobbers (tree outputs, tree inputs, tree clobbers);
1352 static bool ix86_must_pass_in_stack (enum machine_mode mode, tree type);
1353 static bool ix86_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
1355 static void ix86_init_builtins (void);
1356 static rtx ix86_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
1357 static const char *ix86_mangle_fundamental_type (tree);
1358 static tree ix86_stack_protect_fail (void);
1359 static rtx ix86_internal_arg_pointer (void);
1360 static void ix86_dwarf_handle_frame_unspec (const char *, rtx, int);
1362 /* This function is only used on Solaris. */
1363 static void i386_solaris_elf_named_section (const char *, unsigned int, tree)
1366 /* Register class used for passing given 64bit part of the argument.
1367 These represent classes as documented by the PS ABI, with the exception
1368 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
1369 use SF or DFmode move instead of DImode to avoid reformatting penalties.
1371 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
1372 whenever possible (upper half does contain padding).
1374 enum x86_64_reg_class
1377 X86_64_INTEGER_CLASS,
1378 X86_64_INTEGERSI_CLASS,
1385 X86_64_COMPLEX_X87_CLASS,
1388 static const char * const x86_64_reg_class_name[] = {
1389 "no", "integer", "integerSI", "sse", "sseSF", "sseDF",
1390 "sseup", "x87", "x87up", "cplx87", "no"
1393 #define MAX_CLASSES 4
1395 /* Table of constants used by fldpi, fldln2, etc.... */
1396 static REAL_VALUE_TYPE ext_80387_constants_table [5];
1397 static bool ext_80387_constants_init = 0;
1398 static void init_ext_80387_constants (void);
1399 static bool ix86_in_large_data_p (tree) ATTRIBUTE_UNUSED;
1400 static void ix86_encode_section_info (tree, rtx, int) ATTRIBUTE_UNUSED;
1401 static void x86_64_elf_unique_section (tree decl, int reloc) ATTRIBUTE_UNUSED;
1402 static section *x86_64_elf_select_section (tree decl, int reloc,
1403 unsigned HOST_WIDE_INT align)
1406 /* Initialize the GCC target structure. */
1407 #undef TARGET_ATTRIBUTE_TABLE
1408 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
1409 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
1410 # undef TARGET_MERGE_DECL_ATTRIBUTES
1411 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
1414 #undef TARGET_COMP_TYPE_ATTRIBUTES
1415 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
1417 #undef TARGET_INIT_BUILTINS
1418 #define TARGET_INIT_BUILTINS ix86_init_builtins
1419 #undef TARGET_EXPAND_BUILTIN
1420 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
1422 #undef TARGET_ASM_FUNCTION_EPILOGUE
1423 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
1425 #undef TARGET_ENCODE_SECTION_INFO
1426 #ifndef SUBTARGET_ENCODE_SECTION_INFO
1427 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
1429 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
1432 #undef TARGET_ASM_OPEN_PAREN
1433 #define TARGET_ASM_OPEN_PAREN ""
1434 #undef TARGET_ASM_CLOSE_PAREN
1435 #define TARGET_ASM_CLOSE_PAREN ""
1437 #undef TARGET_ASM_ALIGNED_HI_OP
1438 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
1439 #undef TARGET_ASM_ALIGNED_SI_OP
1440 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
1442 #undef TARGET_ASM_ALIGNED_DI_OP
1443 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
1446 #undef TARGET_ASM_UNALIGNED_HI_OP
1447 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
1448 #undef TARGET_ASM_UNALIGNED_SI_OP
1449 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
1450 #undef TARGET_ASM_UNALIGNED_DI_OP
1451 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
1453 #undef TARGET_SCHED_ADJUST_COST
1454 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
1455 #undef TARGET_SCHED_ISSUE_RATE
1456 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
1457 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1458 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
1459 ia32_multipass_dfa_lookahead
1461 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1462 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
1465 #undef TARGET_HAVE_TLS
1466 #define TARGET_HAVE_TLS true
1468 #undef TARGET_CANNOT_FORCE_CONST_MEM
1469 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
1470 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1471 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_rtx_true
1473 #undef TARGET_DELEGITIMIZE_ADDRESS
1474 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
1476 #undef TARGET_MS_BITFIELD_LAYOUT_P
1477 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
1480 #undef TARGET_BINDS_LOCAL_P
1481 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1484 #undef TARGET_ASM_OUTPUT_MI_THUNK
1485 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
1486 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1487 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
1489 #undef TARGET_ASM_FILE_START
1490 #define TARGET_ASM_FILE_START x86_file_start
1492 #undef TARGET_DEFAULT_TARGET_FLAGS
1493 #define TARGET_DEFAULT_TARGET_FLAGS \
1495 | TARGET_64BIT_DEFAULT \
1496 | TARGET_SUBTARGET_DEFAULT \
1497 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
1499 #undef TARGET_HANDLE_OPTION
1500 #define TARGET_HANDLE_OPTION ix86_handle_option
1502 #undef TARGET_RTX_COSTS
1503 #define TARGET_RTX_COSTS ix86_rtx_costs
1504 #undef TARGET_ADDRESS_COST
1505 #define TARGET_ADDRESS_COST ix86_address_cost
1507 #undef TARGET_FIXED_CONDITION_CODE_REGS
1508 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
1509 #undef TARGET_CC_MODES_COMPATIBLE
1510 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
1512 #undef TARGET_MACHINE_DEPENDENT_REORG
1513 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
1515 #undef TARGET_BUILD_BUILTIN_VA_LIST
1516 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
1518 #undef TARGET_MD_ASM_CLOBBERS
1519 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
1521 #undef TARGET_PROMOTE_PROTOTYPES
1522 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
1523 #undef TARGET_STRUCT_VALUE_RTX
1524 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
1525 #undef TARGET_SETUP_INCOMING_VARARGS
1526 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
1527 #undef TARGET_MUST_PASS_IN_STACK
1528 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
1529 #undef TARGET_PASS_BY_REFERENCE
1530 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
1531 #undef TARGET_INTERNAL_ARG_POINTER
1532 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
1533 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
1534 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC ix86_dwarf_handle_frame_unspec
1536 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1537 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
1539 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1540 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
1542 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1543 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
1546 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1547 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
1550 #ifdef SUBTARGET_INSERT_ATTRIBUTES
1551 #undef TARGET_INSERT_ATTRIBUTES
1552 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
1555 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
1556 #define TARGET_MANGLE_FUNDAMENTAL_TYPE ix86_mangle_fundamental_type
1558 #undef TARGET_STACK_PROTECT_FAIL
1559 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
1561 #undef TARGET_FUNCTION_VALUE
1562 #define TARGET_FUNCTION_VALUE ix86_function_value
1564 struct gcc_target targetm = TARGET_INITIALIZER;
1567 /* The svr4 ABI for the i386 says that records and unions are returned
1569 #ifndef DEFAULT_PCC_STRUCT_RETURN
1570 #define DEFAULT_PCC_STRUCT_RETURN 1
1573 /* Implement TARGET_HANDLE_OPTION. */
1576 ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
1583 target_flags &= ~MASK_3DNOW_A;
1584 target_flags_explicit |= MASK_3DNOW_A;
1591 target_flags &= ~(MASK_3DNOW | MASK_3DNOW_A);
1592 target_flags_explicit |= MASK_3DNOW | MASK_3DNOW_A;
1599 target_flags &= ~(MASK_SSE2 | MASK_SSE3);
1600 target_flags_explicit |= MASK_SSE2 | MASK_SSE3;
1607 target_flags &= ~MASK_SSE3;
1608 target_flags_explicit |= MASK_SSE3;
1617 /* Sometimes certain combinations of command options do not make
1618 sense on a particular target machine. You can define a macro
1619 `OVERRIDE_OPTIONS' to take account of this. This macro, if
1620 defined, is executed once just after all the command options have
1623 Don't use this macro to turn on various extra optimizations for
1624 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
1627 override_options (void)
1630 int ix86_tune_defaulted = 0;
1632 /* Comes from final.c -- no real reason to change it. */
1633 #define MAX_CODE_ALIGN 16
1637 const struct processor_costs *cost; /* Processor costs */
1638 const int target_enable; /* Target flags to enable. */
1639 const int target_disable; /* Target flags to disable. */
1640 const int align_loop; /* Default alignments. */
1641 const int align_loop_max_skip;
1642 const int align_jump;
1643 const int align_jump_max_skip;
1644 const int align_func;
1646 const processor_target_table[PROCESSOR_max] =
1648 {&i386_cost, 0, 0, 4, 3, 4, 3, 4},
1649 {&i486_cost, 0, 0, 16, 15, 16, 15, 16},
1650 {&pentium_cost, 0, 0, 16, 7, 16, 7, 16},
1651 {&pentiumpro_cost, 0, 0, 16, 15, 16, 7, 16},
1652 {&geode_cost, 0, 0, 0, 0, 0, 0, 0},
1653 {&k6_cost, 0, 0, 32, 7, 32, 7, 32},
1654 {&athlon_cost, 0, 0, 16, 7, 16, 7, 16},
1655 {&pentium4_cost, 0, 0, 0, 0, 0, 0, 0},
1656 {&k8_cost, 0, 0, 16, 7, 16, 7, 16},
1657 {&nocona_cost, 0, 0, 0, 0, 0, 0, 0},
1658 {&core2_cost, 0, 0, 16, 7, 16, 7, 16},
1659 {&generic32_cost, 0, 0, 16, 7, 16, 7, 16},
1660 {&generic64_cost, 0, 0, 16, 7, 16, 7, 16}
1663 static const char * const cpu_names[] = TARGET_CPU_DEFAULT_NAMES;
1666 const char *const name; /* processor name or nickname. */
1667 const enum processor_type processor;
1668 const enum pta_flags
1674 PTA_PREFETCH_SSE = 16,
1681 const processor_alias_table[] =
1683 {"i386", PROCESSOR_I386, 0},
1684 {"i486", PROCESSOR_I486, 0},
1685 {"i586", PROCESSOR_PENTIUM, 0},
1686 {"pentium", PROCESSOR_PENTIUM, 0},
1687 {"pentium-mmx", PROCESSOR_PENTIUM, PTA_MMX},
1688 {"winchip-c6", PROCESSOR_I486, PTA_MMX},
1689 {"winchip2", PROCESSOR_I486, PTA_MMX | PTA_3DNOW},
1690 {"c3", PROCESSOR_I486, PTA_MMX | PTA_3DNOW},
1691 {"c3-2", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_PREFETCH_SSE | PTA_SSE},
1692 {"i686", PROCESSOR_PENTIUMPRO, 0},
1693 {"pentiumpro", PROCESSOR_PENTIUMPRO, 0},
1694 {"pentium2", PROCESSOR_PENTIUMPRO, PTA_MMX},
1695 {"pentium3", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_PREFETCH_SSE},
1696 {"pentium3m", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_PREFETCH_SSE},
1697 {"pentium-m", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_PREFETCH_SSE | PTA_SSE2},
1698 {"pentium4", PROCESSOR_PENTIUM4, PTA_SSE | PTA_SSE2
1699 | PTA_MMX | PTA_PREFETCH_SSE},
1700 {"pentium4m", PROCESSOR_PENTIUM4, PTA_SSE | PTA_SSE2
1701 | PTA_MMX | PTA_PREFETCH_SSE},
1702 {"prescott", PROCESSOR_NOCONA, PTA_SSE | PTA_SSE2 | PTA_SSE3
1703 | PTA_MMX | PTA_PREFETCH_SSE},
1704 {"nocona", PROCESSOR_NOCONA, PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_64BIT
1705 | PTA_MMX | PTA_PREFETCH_SSE},
1706 {"core2", PROCESSOR_CORE2, PTA_SSE | PTA_SSE2 | PTA_SSE3
1707 | PTA_64BIT | PTA_MMX
1708 | PTA_PREFETCH_SSE},
1709 {"geode", PROCESSOR_GEODE, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1711 {"k6", PROCESSOR_K6, PTA_MMX},
1712 {"k6-2", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
1713 {"k6-3", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
1714 {"athlon", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1716 {"athlon-tbird", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE
1717 | PTA_3DNOW | PTA_3DNOW_A},
1718 {"athlon-4", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1719 | PTA_3DNOW_A | PTA_SSE},
1720 {"athlon-xp", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1721 | PTA_3DNOW_A | PTA_SSE},
1722 {"athlon-mp", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1723 | PTA_3DNOW_A | PTA_SSE},
1724 {"x86-64", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_64BIT
1725 | PTA_SSE | PTA_SSE2 },
1726 {"k8", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
1727 | PTA_3DNOW_A | PTA_SSE | PTA_SSE2},
1728 {"opteron", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
1729 | PTA_3DNOW_A | PTA_SSE | PTA_SSE2},
1730 {"athlon64", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
1731 | PTA_3DNOW_A | PTA_SSE | PTA_SSE2},
1732 {"athlon-fx", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
1733 | PTA_3DNOW_A | PTA_SSE | PTA_SSE2},
1734 {"generic32", PROCESSOR_GENERIC32, 0 /* flags are only used for -march switch. */ },
1735 {"generic64", PROCESSOR_GENERIC64, PTA_64BIT /* flags are only used for -march switch. */ },
1738 int const pta_size = ARRAY_SIZE (processor_alias_table);
1740 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1741 SUBTARGET_OVERRIDE_OPTIONS;
1744 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1745 SUBSUBTARGET_OVERRIDE_OPTIONS;
1748 /* -fPIC is the default for x86_64. */
1749 if (TARGET_MACHO && TARGET_64BIT)
1752 /* Set the default values for switches whose default depends on TARGET_64BIT
1753 in case they weren't overwritten by command line options. */
1756 /* Mach-O doesn't support omitting the frame pointer for now. */
1757 if (flag_omit_frame_pointer == 2)
1758 flag_omit_frame_pointer = (TARGET_MACHO ? 0 : 1);
1759 if (flag_asynchronous_unwind_tables == 2)
1760 flag_asynchronous_unwind_tables = 1;
1761 if (flag_pcc_struct_return == 2)
1762 flag_pcc_struct_return = 0;
1766 if (flag_omit_frame_pointer == 2)
1767 flag_omit_frame_pointer = 0;
1768 if (flag_asynchronous_unwind_tables == 2)
1769 flag_asynchronous_unwind_tables = 0;
1770 if (flag_pcc_struct_return == 2)
1771 flag_pcc_struct_return = DEFAULT_PCC_STRUCT_RETURN;
1774 /* Need to check -mtune=generic first. */
1775 if (ix86_tune_string)
1777 if (!strcmp (ix86_tune_string, "generic")
1778 || !strcmp (ix86_tune_string, "i686")
1779 /* As special support for cross compilers we read -mtune=native
1780 as -mtune=generic. With native compilers we won't see the
1781 -mtune=native, as it was changed by the driver. */
1782 || !strcmp (ix86_tune_string, "native"))
1785 ix86_tune_string = "generic64";
1787 ix86_tune_string = "generic32";
1789 else if (!strncmp (ix86_tune_string, "generic", 7))
1790 error ("bad value (%s) for -mtune= switch", ix86_tune_string);
1794 if (ix86_arch_string)
1795 ix86_tune_string = ix86_arch_string;
1796 if (!ix86_tune_string)
1798 ix86_tune_string = cpu_names [TARGET_CPU_DEFAULT];
1799 ix86_tune_defaulted = 1;
1802 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
1803 need to use a sensible tune option. */
1804 if (!strcmp (ix86_tune_string, "generic")
1805 || !strcmp (ix86_tune_string, "x86-64")
1806 || !strcmp (ix86_tune_string, "i686"))
1809 ix86_tune_string = "generic64";
1811 ix86_tune_string = "generic32";
1814 if (ix86_stringop_string)
1816 if (!strcmp (ix86_stringop_string, "rep_byte"))
1817 stringop_alg = rep_prefix_1_byte;
1818 else if (!strcmp (ix86_stringop_string, "libcall"))
1819 stringop_alg = libcall;
1820 else if (!strcmp (ix86_stringop_string, "rep_4byte"))
1821 stringop_alg = rep_prefix_4_byte;
1822 else if (!strcmp (ix86_stringop_string, "rep_8byte"))
1823 stringop_alg = rep_prefix_8_byte;
1824 else if (!strcmp (ix86_stringop_string, "byte_loop"))
1825 stringop_alg = loop_1_byte;
1826 else if (!strcmp (ix86_stringop_string, "loop"))
1827 stringop_alg = loop;
1828 else if (!strcmp (ix86_stringop_string, "unrolled_loop"))
1829 stringop_alg = unrolled_loop;
1831 error ("bad value (%s) for -mstringop-strategy= switch", ix86_stringop_string);
1833 if (!strcmp (ix86_tune_string, "x86-64"))
1834 warning (OPT_Wdeprecated, "-mtune=x86-64 is deprecated. Use -mtune=k8 or "
1835 "-mtune=generic instead as appropriate.");
1837 if (!ix86_arch_string)
1838 ix86_arch_string = TARGET_64BIT ? "x86-64" : "i386";
1839 if (!strcmp (ix86_arch_string, "generic"))
1840 error ("generic CPU can be used only for -mtune= switch");
1841 if (!strncmp (ix86_arch_string, "generic", 7))
1842 error ("bad value (%s) for -march= switch", ix86_arch_string);
1844 if (ix86_cmodel_string != 0)
1846 if (!strcmp (ix86_cmodel_string, "small"))
1847 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
1848 else if (!strcmp (ix86_cmodel_string, "medium"))
1849 ix86_cmodel = flag_pic ? CM_MEDIUM_PIC : CM_MEDIUM;
1851 sorry ("code model %s not supported in PIC mode", ix86_cmodel_string);
1852 else if (!strcmp (ix86_cmodel_string, "32"))
1853 ix86_cmodel = CM_32;
1854 else if (!strcmp (ix86_cmodel_string, "kernel") && !flag_pic)
1855 ix86_cmodel = CM_KERNEL;
1856 else if (!strcmp (ix86_cmodel_string, "large") && !flag_pic)
1857 ix86_cmodel = CM_LARGE;
1859 error ("bad value (%s) for -mcmodel= switch", ix86_cmodel_string);
1863 ix86_cmodel = CM_32;
1865 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
1867 if (ix86_asm_string != 0)
1870 && !strcmp (ix86_asm_string, "intel"))
1871 ix86_asm_dialect = ASM_INTEL;
1872 else if (!strcmp (ix86_asm_string, "att"))
1873 ix86_asm_dialect = ASM_ATT;
1875 error ("bad value (%s) for -masm= switch", ix86_asm_string);
1877 if ((TARGET_64BIT == 0) != (ix86_cmodel == CM_32))
1878 error ("code model %qs not supported in the %s bit mode",
1879 ix86_cmodel_string, TARGET_64BIT ? "64" : "32");
1880 if (ix86_cmodel == CM_LARGE)
1881 sorry ("code model %<large%> not supported yet");
1882 if ((TARGET_64BIT != 0) != ((target_flags & MASK_64BIT) != 0))
1883 sorry ("%i-bit mode not compiled in",
1884 (target_flags & MASK_64BIT) ? 64 : 32);
1886 for (i = 0; i < pta_size; i++)
1887 if (! strcmp (ix86_arch_string, processor_alias_table[i].name))
1889 ix86_arch = processor_alias_table[i].processor;
1890 /* Default cpu tuning to the architecture. */
1891 ix86_tune = ix86_arch;
1892 if (processor_alias_table[i].flags & PTA_MMX
1893 && !(target_flags_explicit & MASK_MMX))
1894 target_flags |= MASK_MMX;
1895 if (processor_alias_table[i].flags & PTA_3DNOW
1896 && !(target_flags_explicit & MASK_3DNOW))
1897 target_flags |= MASK_3DNOW;
1898 if (processor_alias_table[i].flags & PTA_3DNOW_A
1899 && !(target_flags_explicit & MASK_3DNOW_A))
1900 target_flags |= MASK_3DNOW_A;
1901 if (processor_alias_table[i].flags & PTA_SSE
1902 && !(target_flags_explicit & MASK_SSE))
1903 target_flags |= MASK_SSE;
1904 if (processor_alias_table[i].flags & PTA_SSE2
1905 && !(target_flags_explicit & MASK_SSE2))
1906 target_flags |= MASK_SSE2;
1907 if (processor_alias_table[i].flags & PTA_SSE3
1908 && !(target_flags_explicit & MASK_SSE3))
1909 target_flags |= MASK_SSE3;
1910 if (processor_alias_table[i].flags & PTA_SSSE3
1911 && !(target_flags_explicit & MASK_SSSE3))
1912 target_flags |= MASK_SSSE3;
1913 if (processor_alias_table[i].flags & PTA_PREFETCH_SSE)
1914 x86_prefetch_sse = true;
1915 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
1916 error ("CPU you selected does not support x86-64 "
1922 error ("bad value (%s) for -march= switch", ix86_arch_string);
1924 for (i = 0; i < pta_size; i++)
1925 if (! strcmp (ix86_tune_string, processor_alias_table[i].name))
1927 ix86_tune = processor_alias_table[i].processor;
1928 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
1930 if (ix86_tune_defaulted)
1932 ix86_tune_string = "x86-64";
1933 for (i = 0; i < pta_size; i++)
1934 if (! strcmp (ix86_tune_string,
1935 processor_alias_table[i].name))
1937 ix86_tune = processor_alias_table[i].processor;
1940 error ("CPU you selected does not support x86-64 "
1943 /* Intel CPUs have always interpreted SSE prefetch instructions as
1944 NOPs; so, we can enable SSE prefetch instructions even when
1945 -mtune (rather than -march) points us to a processor that has them.
1946 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
1947 higher processors. */
1948 if (TARGET_CMOVE && (processor_alias_table[i].flags & PTA_PREFETCH_SSE))
1949 x86_prefetch_sse = true;
1953 error ("bad value (%s) for -mtune= switch", ix86_tune_string);
1956 ix86_cost = &size_cost;
1958 ix86_cost = processor_target_table[ix86_tune].cost;
1959 target_flags |= processor_target_table[ix86_tune].target_enable;
1960 target_flags &= ~processor_target_table[ix86_tune].target_disable;
1962 /* Arrange to set up i386_stack_locals for all functions. */
1963 init_machine_status = ix86_init_machine_status;
1965 /* Validate -mregparm= value. */
1966 if (ix86_regparm_string)
1968 i = atoi (ix86_regparm_string);
1969 if (i < 0 || i > REGPARM_MAX)
1970 error ("-mregparm=%d is not between 0 and %d", i, REGPARM_MAX);
1976 ix86_regparm = REGPARM_MAX;
1978 /* If the user has provided any of the -malign-* options,
1979 warn and use that value only if -falign-* is not set.
1980 Remove this code in GCC 3.2 or later. */
1981 if (ix86_align_loops_string)
1983 warning (0, "-malign-loops is obsolete, use -falign-loops");
1984 if (align_loops == 0)
1986 i = atoi (ix86_align_loops_string);
1987 if (i < 0 || i > MAX_CODE_ALIGN)
1988 error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
1990 align_loops = 1 << i;
1994 if (ix86_align_jumps_string)
1996 warning (0, "-malign-jumps is obsolete, use -falign-jumps");
1997 if (align_jumps == 0)
1999 i = atoi (ix86_align_jumps_string);
2000 if (i < 0 || i > MAX_CODE_ALIGN)
2001 error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
2003 align_jumps = 1 << i;
2007 if (ix86_align_funcs_string)
2009 warning (0, "-malign-functions is obsolete, use -falign-functions");
2010 if (align_functions == 0)
2012 i = atoi (ix86_align_funcs_string);
2013 if (i < 0 || i > MAX_CODE_ALIGN)
2014 error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
2016 align_functions = 1 << i;
2020 /* Default align_* from the processor table. */
2021 if (align_loops == 0)
2023 align_loops = processor_target_table[ix86_tune].align_loop;
2024 align_loops_max_skip = processor_target_table[ix86_tune].align_loop_max_skip;
2026 if (align_jumps == 0)
2028 align_jumps = processor_target_table[ix86_tune].align_jump;
2029 align_jumps_max_skip = processor_target_table[ix86_tune].align_jump_max_skip;
2031 if (align_functions == 0)
2033 align_functions = processor_target_table[ix86_tune].align_func;
2036 /* Validate -mbranch-cost= value, or provide default. */
2037 ix86_branch_cost = ix86_cost->branch_cost;
2038 if (ix86_branch_cost_string)
2040 i = atoi (ix86_branch_cost_string);
2042 error ("-mbranch-cost=%d is not between 0 and 5", i);
2044 ix86_branch_cost = i;
2046 if (ix86_section_threshold_string)
2048 i = atoi (ix86_section_threshold_string);
2050 error ("-mlarge-data-threshold=%d is negative", i);
2052 ix86_section_threshold = i;
2055 if (ix86_tls_dialect_string)
2057 if (strcmp (ix86_tls_dialect_string, "gnu") == 0)
2058 ix86_tls_dialect = TLS_DIALECT_GNU;
2059 else if (strcmp (ix86_tls_dialect_string, "gnu2") == 0)
2060 ix86_tls_dialect = TLS_DIALECT_GNU2;
2061 else if (strcmp (ix86_tls_dialect_string, "sun") == 0)
2062 ix86_tls_dialect = TLS_DIALECT_SUN;
2064 error ("bad value (%s) for -mtls-dialect= switch",
2065 ix86_tls_dialect_string);
2068 /* Keep nonleaf frame pointers. */
2069 if (flag_omit_frame_pointer)
2070 target_flags &= ~MASK_OMIT_LEAF_FRAME_POINTER;
2071 else if (TARGET_OMIT_LEAF_FRAME_POINTER)
2072 flag_omit_frame_pointer = 1;
2074 /* If we're doing fast math, we don't care about comparison order
2075 wrt NaNs. This lets us use a shorter comparison sequence. */
2076 if (flag_finite_math_only)
2077 target_flags &= ~MASK_IEEE_FP;
2079 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
2080 since the insns won't need emulation. */
2081 if (x86_arch_always_fancy_math_387 & (1 << ix86_arch))
2082 target_flags &= ~MASK_NO_FANCY_MATH_387;
2084 /* Likewise, if the target doesn't have a 387, or we've specified
2085 software floating point, don't use 387 inline intrinsics. */
2087 target_flags |= MASK_NO_FANCY_MATH_387;
2089 /* Turn on SSE3 builtins for -mssse3. */
2091 target_flags |= MASK_SSE3;
2093 /* Turn on SSE2 builtins for -msse3. */
2095 target_flags |= MASK_SSE2;
2097 /* Turn on SSE builtins for -msse2. */
2099 target_flags |= MASK_SSE;
2101 /* Turn on MMX builtins for -msse. */
2104 target_flags |= MASK_MMX & ~target_flags_explicit;
2105 x86_prefetch_sse = true;
2108 /* Turn on MMX builtins for 3Dnow. */
2110 target_flags |= MASK_MMX;
2114 if (TARGET_ALIGN_DOUBLE)
2115 error ("-malign-double makes no sense in the 64bit mode");
2117 error ("-mrtd calling convention not supported in the 64bit mode");
2119 /* Enable by default the SSE and MMX builtins. Do allow the user to
2120 explicitly disable any of these. In particular, disabling SSE and
2121 MMX for kernel code is extremely useful. */
2123 |= ((MASK_SSE2 | MASK_SSE | MASK_MMX | MASK_128BIT_LONG_DOUBLE)
2124 & ~target_flags_explicit);
2128 /* i386 ABI does not specify red zone. It still makes sense to use it
2129 when programmer takes care to stack from being destroyed. */
2130 if (!(target_flags_explicit & MASK_NO_RED_ZONE))
2131 target_flags |= MASK_NO_RED_ZONE;
2134 /* Validate -mpreferred-stack-boundary= value, or provide default.
2135 The default of 128 bits is for Pentium III's SSE __m128. We can't
2136 change it because of optimize_size. Otherwise, we can't mix object
2137 files compiled with -Os and -On. */
2138 ix86_preferred_stack_boundary = 128;
2139 if (ix86_preferred_stack_boundary_string)
2141 i = atoi (ix86_preferred_stack_boundary_string);
2142 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
2143 error ("-mpreferred-stack-boundary=%d is not between %d and 12", i,
2144 TARGET_64BIT ? 4 : 2);
2146 ix86_preferred_stack_boundary = (1 << i) * BITS_PER_UNIT;
2149 /* Accept -mx87regparm only if 80387 support is enabled. */
2150 if (TARGET_X87REGPARM
2152 error ("-mx87regparm used without 80387 enabled");
2154 /* Accept -msseregparm only if at least SSE support is enabled. */
2155 if (TARGET_SSEREGPARM
2157 error ("-msseregparm used without SSE enabled");
2159 ix86_fpmath = TARGET_FPMATH_DEFAULT;
2161 if (ix86_fpmath_string != 0)
2163 if (! strcmp (ix86_fpmath_string, "387"))
2164 ix86_fpmath = FPMATH_387;
2165 else if (! strcmp (ix86_fpmath_string, "sse"))
2169 warning (0, "SSE instruction set disabled, using 387 arithmetics");
2170 ix86_fpmath = FPMATH_387;
2173 ix86_fpmath = FPMATH_SSE;
2175 else if (! strcmp (ix86_fpmath_string, "387,sse")
2176 || ! strcmp (ix86_fpmath_string, "sse,387"))
2180 warning (0, "SSE instruction set disabled, using 387 arithmetics");
2181 ix86_fpmath = FPMATH_387;
2183 else if (!TARGET_80387)
2185 warning (0, "387 instruction set disabled, using SSE arithmetics");
2186 ix86_fpmath = FPMATH_SSE;
2189 ix86_fpmath = FPMATH_SSE | FPMATH_387;
2192 error ("bad value (%s) for -mfpmath= switch", ix86_fpmath_string);
2195 /* If the i387 is disabled, then do not return values in it. */
2197 target_flags &= ~MASK_FLOAT_RETURNS;
2199 if ((x86_accumulate_outgoing_args & TUNEMASK)
2200 && !(target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
2202 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
2204 /* ??? Unwind info is not correct around the CFG unless either a frame
2205 pointer is present or M_A_O_A is set. Fixing this requires rewriting
2206 unwind info generation to be aware of the CFG and propagating states
2208 if ((flag_unwind_tables || flag_asynchronous_unwind_tables
2209 || flag_exceptions || flag_non_call_exceptions)
2210 && flag_omit_frame_pointer
2211 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
2213 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
2214 warning (0, "unwind tables currently require either a frame pointer "
2215 "or -maccumulate-outgoing-args for correctness");
2216 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
2219 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
2222 ASM_GENERATE_INTERNAL_LABEL (internal_label_prefix, "LX", 0);
2223 p = strchr (internal_label_prefix, 'X');
2224 internal_label_prefix_len = p - internal_label_prefix;
2228 /* When scheduling description is not available, disable scheduler pass
2229 so it won't slow down the compilation and make x87 code slower. */
2230 if (!TARGET_SCHEDULE)
2231 flag_schedule_insns_after_reload = flag_schedule_insns = 0;
2233 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
2234 set_param_value ("simultaneous-prefetches",
2235 ix86_cost->simultaneous_prefetches);
2236 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE))
2237 set_param_value ("l1-cache-line-size", ix86_cost->prefetch_block);
2240 /* switch to the appropriate section for output of DECL.
2241 DECL is either a `VAR_DECL' node or a constant of some sort.
2242 RELOC indicates whether forming the initial value of DECL requires
2243 link-time relocations. */
2246 x86_64_elf_select_section (tree decl, int reloc,
2247 unsigned HOST_WIDE_INT align)
2249 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2250 && ix86_in_large_data_p (decl))
2252 const char *sname = NULL;
2253 unsigned int flags = SECTION_WRITE;
2254 switch (categorize_decl_for_section (decl, reloc, flag_pic))
2259 case SECCAT_DATA_REL:
2260 sname = ".ldata.rel";
2262 case SECCAT_DATA_REL_LOCAL:
2263 sname = ".ldata.rel.local";
2265 case SECCAT_DATA_REL_RO:
2266 sname = ".ldata.rel.ro";
2268 case SECCAT_DATA_REL_RO_LOCAL:
2269 sname = ".ldata.rel.ro.local";
2273 flags |= SECTION_BSS;
2276 case SECCAT_RODATA_MERGE_STR:
2277 case SECCAT_RODATA_MERGE_STR_INIT:
2278 case SECCAT_RODATA_MERGE_CONST:
2282 case SECCAT_SRODATA:
2289 /* We don't split these for medium model. Place them into
2290 default sections and hope for best. */
2295 /* We might get called with string constants, but get_named_section
2296 doesn't like them as they are not DECLs. Also, we need to set
2297 flags in that case. */
2299 return get_section (sname, flags, NULL);
2300 return get_named_section (decl, sname, reloc);
2303 return default_elf_select_section (decl, reloc, align);
2306 /* Build up a unique section name, expressed as a
2307 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
2308 RELOC indicates whether the initial value of EXP requires
2309 link-time relocations. */
2312 x86_64_elf_unique_section (tree decl, int reloc)
2314 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2315 && ix86_in_large_data_p (decl))
2317 const char *prefix = NULL;
2318 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
2319 bool one_only = DECL_ONE_ONLY (decl) && !HAVE_COMDAT_GROUP;
2321 switch (categorize_decl_for_section (decl, reloc, flag_pic))
2324 case SECCAT_DATA_REL:
2325 case SECCAT_DATA_REL_LOCAL:
2326 case SECCAT_DATA_REL_RO:
2327 case SECCAT_DATA_REL_RO_LOCAL:
2328 prefix = one_only ? ".gnu.linkonce.ld." : ".ldata.";
2331 prefix = one_only ? ".gnu.linkonce.lb." : ".lbss.";
2334 case SECCAT_RODATA_MERGE_STR:
2335 case SECCAT_RODATA_MERGE_STR_INIT:
2336 case SECCAT_RODATA_MERGE_CONST:
2337 prefix = one_only ? ".gnu.linkonce.lr." : ".lrodata.";
2339 case SECCAT_SRODATA:
2346 /* We don't split these for medium model. Place them into
2347 default sections and hope for best. */
2355 plen = strlen (prefix);
2357 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
2358 name = targetm.strip_name_encoding (name);
2359 nlen = strlen (name);
2361 string = alloca (nlen + plen + 1);
2362 memcpy (string, prefix, plen);
2363 memcpy (string + plen, name, nlen + 1);
2365 DECL_SECTION_NAME (decl) = build_string (nlen + plen, string);
2369 default_unique_section (decl, reloc);
2372 #ifdef COMMON_ASM_OP
2373 /* This says how to output assembler code to declare an
2374 uninitialized external linkage data object.
2376 For medium model x86-64 we need to use .largecomm opcode for
2379 x86_elf_aligned_common (FILE *file,
2380 const char *name, unsigned HOST_WIDE_INT size,
2383 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2384 && size > (unsigned int)ix86_section_threshold)
2385 fprintf (file, ".largecomm\t");
2387 fprintf (file, "%s", COMMON_ASM_OP);
2388 assemble_name (file, name);
2389 fprintf (file, ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n",
2390 size, align / BITS_PER_UNIT);
2393 /* Utility function for targets to use in implementing
2394 ASM_OUTPUT_ALIGNED_BSS. */
2397 x86_output_aligned_bss (FILE *file, tree decl ATTRIBUTE_UNUSED,
2398 const char *name, unsigned HOST_WIDE_INT size,
2401 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2402 && size > (unsigned int)ix86_section_threshold)
2403 switch_to_section (get_named_section (decl, ".lbss", 0));
2405 switch_to_section (bss_section);
2406 ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT));
2407 #ifdef ASM_DECLARE_OBJECT_NAME
2408 last_assemble_variable_decl = decl;
2409 ASM_DECLARE_OBJECT_NAME (file, name, decl);
2411 /* Standard thing is just output label for the object. */
2412 ASM_OUTPUT_LABEL (file, name);
2413 #endif /* ASM_DECLARE_OBJECT_NAME */
2414 ASM_OUTPUT_SKIP (file, size ? size : 1);
2419 optimization_options (int level, int size ATTRIBUTE_UNUSED)
2421 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
2422 make the problem with not enough registers even worse. */
2423 #ifdef INSN_SCHEDULING
2425 flag_schedule_insns = 0;
2429 /* The Darwin libraries never set errno, so we might as well
2430 avoid calling them when that's the only reason we would. */
2431 flag_errno_math = 0;
2433 /* The default values of these switches depend on the TARGET_64BIT
2434 that is not known at this moment. Mark these values with 2 and
2435 let user the to override these. In case there is no command line option
2436 specifying them, we will set the defaults in override_options. */
2438 flag_omit_frame_pointer = 2;
2439 flag_pcc_struct_return = 2;
2440 flag_asynchronous_unwind_tables = 2;
2441 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
2442 SUBTARGET_OPTIMIZATION_OPTIONS;
2446 /* Table of valid machine attributes. */
2447 const struct attribute_spec ix86_attribute_table[] =
2449 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2450 /* Stdcall attribute says callee is responsible for popping arguments
2451 if they are not variable. */
2452 { "stdcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
2453 /* Fastcall attribute says callee is responsible for popping arguments
2454 if they are not variable. */
2455 { "fastcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
2456 /* Cdecl attribute says the callee is a normal C declaration */
2457 { "cdecl", 0, 0, false, true, true, ix86_handle_cconv_attribute },
2458 /* Regparm attribute specifies how many integer arguments are to be
2459 passed in registers. */
2460 { "regparm", 1, 1, false, true, true, ix86_handle_cconv_attribute },
2461 /* X87regparm attribute says we are passing floating point arguments
2462 in 80387 registers. */
2463 { "x87regparm", 0, 0, false, true, true, ix86_handle_cconv_attribute },
2464 /* Sseregparm attribute says we are using x86_64 calling conventions
2465 for FP arguments. */
2466 { "sseregparm", 0, 0, false, true, true, ix86_handle_cconv_attribute },
2467 /* force_align_arg_pointer says this function realigns the stack at entry. */
2468 { (const char *)&ix86_force_align_arg_pointer_string, 0, 0,
2469 false, true, true, ix86_handle_cconv_attribute },
2470 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
2471 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
2472 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
2473 { "shared", 0, 0, true, false, false, ix86_handle_shared_attribute },
2475 { "ms_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
2476 { "gcc_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
2477 #ifdef SUBTARGET_ATTRIBUTE_TABLE
2478 SUBTARGET_ATTRIBUTE_TABLE,
2480 { NULL, 0, 0, false, false, false, NULL }
2483 /* Decide whether we can make a sibling call to a function. DECL is the
2484 declaration of the function being targeted by the call and EXP is the
2485 CALL_EXPR representing the call. */
2488 ix86_function_ok_for_sibcall (tree decl, tree exp)
2493 /* If we are generating position-independent code, we cannot sibcall
2494 optimize any indirect call, or a direct call to a global function,
2495 as the PLT requires %ebx be live. */
2496 if (!TARGET_64BIT && flag_pic && (!decl || !targetm.binds_local_p (decl)))
2503 func = TREE_TYPE (TREE_OPERAND (exp, 0));
2504 if (POINTER_TYPE_P (func))
2505 func = TREE_TYPE (func);
2508 /* Check that the return value locations are the same. Like
2509 if we are returning floats on the 80387 register stack, we cannot
2510 make a sibcall from a function that doesn't return a float to a
2511 function that does or, conversely, from a function that does return
2512 a float to a function that doesn't; the necessary stack adjustment
2513 would not be executed. This is also the place we notice
2514 differences in the return value ABI. Note that it is ok for one
2515 of the functions to have void return type as long as the return
2516 value of the other is passed in a register. */
2517 a = ix86_function_value (TREE_TYPE (exp), func, false);
2518 b = ix86_function_value (TREE_TYPE (DECL_RESULT (cfun->decl)),
2520 if (STACK_REG_P (a) || STACK_REG_P (b))
2522 if (!rtx_equal_p (a, b))
2525 else if (VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl))))
2527 else if (!rtx_equal_p (a, b))
2530 /* If this call is indirect, we'll need to be able to use a call-clobbered
2531 register for the address of the target function. Make sure that all
2532 such registers are not used for passing parameters. */
2533 if (!decl && !TARGET_64BIT)
2537 /* We're looking at the CALL_EXPR, we need the type of the function. */
2538 type = TREE_OPERAND (exp, 0); /* pointer expression */
2539 type = TREE_TYPE (type); /* pointer type */
2540 type = TREE_TYPE (type); /* function type */
2542 if (ix86_function_regparm (type, NULL) >= 3)
2544 /* ??? Need to count the actual number of registers to be used,
2545 not the possible number of registers. Fix later. */
2550 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
2551 /* Dllimport'd functions are also called indirectly. */
2552 if (decl && DECL_DLLIMPORT_P (decl)
2553 && ix86_function_regparm (TREE_TYPE (decl), NULL) >= 3)
2557 /* If we forced aligned the stack, then sibcalling would unalign the
2558 stack, which may break the called function. */
2559 if (cfun->machine->force_align_arg_pointer)
2562 /* Otherwise okay. That also includes certain types of indirect calls. */
2566 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "x87regparm"
2567 and "sseregparm" calling convention attributes;
2568 arguments as in struct attribute_spec.handler. */
2571 ix86_handle_cconv_attribute (tree *node, tree name,
2573 int flags ATTRIBUTE_UNUSED,
2576 if (TREE_CODE (*node) != FUNCTION_TYPE
2577 && TREE_CODE (*node) != METHOD_TYPE
2578 && TREE_CODE (*node) != FIELD_DECL
2579 && TREE_CODE (*node) != TYPE_DECL)
2581 warning (OPT_Wattributes, "%qs attribute only applies to functions",
2582 IDENTIFIER_POINTER (name));
2583 *no_add_attrs = true;
2587 /* Can combine regparm with all attributes but fastcall. */
2588 if (is_attribute_p ("regparm", name))
2592 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
2594 error ("fastcall and regparm attributes are not compatible");
2597 cst = TREE_VALUE (args);
2598 if (TREE_CODE (cst) != INTEGER_CST)
2600 warning (OPT_Wattributes,
2601 "%qs attribute requires an integer constant argument",
2602 IDENTIFIER_POINTER (name));
2603 *no_add_attrs = true;
2605 else if (compare_tree_int (cst, REGPARM_MAX) > 0)
2607 warning (OPT_Wattributes, "argument to %qs attribute larger than %d",
2608 IDENTIFIER_POINTER (name), REGPARM_MAX);
2609 *no_add_attrs = true;
2613 && lookup_attribute (ix86_force_align_arg_pointer_string,
2614 TYPE_ATTRIBUTES (*node))
2615 && compare_tree_int (cst, REGPARM_MAX-1))
2617 error ("%s functions limited to %d register parameters",
2618 ix86_force_align_arg_pointer_string, REGPARM_MAX-1);
2626 warning (OPT_Wattributes, "%qs attribute ignored",
2627 IDENTIFIER_POINTER (name));
2628 *no_add_attrs = true;
2632 /* Can combine fastcall with stdcall (redundant), x87regparm
2634 if (is_attribute_p ("fastcall", name))
2636 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
2638 error ("fastcall and cdecl attributes are not compatible");
2640 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
2642 error ("fastcall and stdcall attributes are not compatible");
2644 if (lookup_attribute ("regparm", TYPE_ATTRIBUTES (*node)))
2646 error ("fastcall and regparm attributes are not compatible");
2650 /* Can combine stdcall with fastcall (redundant), regparm,
2651 x87regparm and sseregparm. */
2652 else if (is_attribute_p ("stdcall", name))
2654 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
2656 error ("stdcall and cdecl attributes are not compatible");
2658 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
2660 error ("stdcall and fastcall attributes are not compatible");
2664 /* Can combine cdecl with regparm, x87regparm and sseregparm. */
2665 else if (is_attribute_p ("cdecl", name))
2667 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
2669 error ("stdcall and cdecl attributes are not compatible");
2671 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
2673 error ("fastcall and cdecl attributes are not compatible");
2677 /* Can combine x87regparm or sseregparm with all attributes. */
2682 /* Return 0 if the attributes for two types are incompatible, 1 if they
2683 are compatible, and 2 if they are nearly compatible (which causes a
2684 warning to be generated). */
2687 ix86_comp_type_attributes (tree type1, tree type2)
2689 /* Check for mismatch of non-default calling convention. */
2690 const char *const rtdstr = TARGET_RTD ? "cdecl" : "stdcall";
2692 if (TREE_CODE (type1) != FUNCTION_TYPE)
2695 /* Check for mismatched fastcall/regparm types. */
2696 if ((!lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type1))
2697 != !lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type2)))
2698 || (ix86_function_regparm (type1, NULL)
2699 != ix86_function_regparm (type2, NULL)))
2702 /* Check for mismatched x87regparm types. */
2703 if (!lookup_attribute ("x87regparm", TYPE_ATTRIBUTES (type1))
2704 != !lookup_attribute ("x87regparm", TYPE_ATTRIBUTES (type2)))
2707 /* Check for mismatched sseregparm types. */
2708 if (!lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type1))
2709 != !lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type2)))
2712 /* Check for mismatched return types (cdecl vs stdcall). */
2713 if (!lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type1))
2714 != !lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type2)))
2720 /* Return the regparm value for a function with the indicated TYPE and DECL.
2721 DECL may be NULL when calling function indirectly
2722 or considering a libcall. */
2725 ix86_function_regparm (tree type, tree decl)
2728 int regparm = ix86_regparm;
2729 bool user_convention = false;
2733 attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (type));
2736 regparm = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
2737 user_convention = true;
2740 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
2743 user_convention = true;
2746 /* Use register calling convention for local functions when possible. */
2747 if (!TARGET_64BIT && !user_convention && decl
2748 && flag_unit_at_a_time && !profile_flag)
2750 struct cgraph_local_info *i = cgraph_local_info (decl);
2753 int local_regparm, globals = 0, regno;
2755 /* Make sure no regparm register is taken by a global register
2757 for (local_regparm = 0; local_regparm < 3; local_regparm++)
2758 if (global_regs[local_regparm])
2760 /* We can't use regparm(3) for nested functions as these use
2761 static chain pointer in third argument. */
2762 if (local_regparm == 3
2763 && decl_function_context (decl)
2764 && !DECL_NO_STATIC_CHAIN (decl))
2766 /* If the function realigns its stackpointer, the
2767 prologue will clobber %ecx. If we've already
2768 generated code for the callee, the callee
2769 DECL_STRUCT_FUNCTION is gone, so we fall back to
2770 scanning the attributes for the self-realigning
2772 if ((DECL_STRUCT_FUNCTION (decl)
2773 && DECL_STRUCT_FUNCTION (decl)->machine->force_align_arg_pointer)
2774 || (!DECL_STRUCT_FUNCTION (decl)
2775 && lookup_attribute (ix86_force_align_arg_pointer_string,
2776 TYPE_ATTRIBUTES (TREE_TYPE (decl)))))
2778 /* Each global register variable increases register preassure,
2779 so the more global reg vars there are, the smaller regparm
2780 optimization use, unless requested by the user explicitly. */
2781 for (regno = 0; regno < 6; regno++)
2782 if (global_regs[regno])
2785 = globals < local_regparm ? local_regparm - globals : 0;
2787 if (local_regparm > regparm)
2788 regparm = local_regparm;
2795 /* Return 1 if we can pass up to X87_REGPARM_MAX floating point
2796 arguments in x87 registers for a function with the indicated
2797 TYPE and DECL. DECL may be NULL when calling function indirectly
2798 or considering a libcall. For local functions, return 2.
2799 Otherwise return 0. */
2802 ix86_function_x87regparm (tree type, tree decl)
2804 /* Use x87 registers to pass floating point arguments if requested
2805 by the x87regparm attribute. */
2806 if (TARGET_X87REGPARM
2808 && lookup_attribute ("x87regparm", TYPE_ATTRIBUTES (type))))
2813 error ("Calling %qD with attribute x87regparm without "
2814 "80387 enabled", decl);
2816 error ("Calling %qT with attribute x87regparm without "
2817 "80387 enabled", type);
2824 /* For local functions, pass up to X87_REGPARM_MAX floating point
2825 arguments in x87 registers. */
2826 if (!TARGET_64BIT && decl
2827 && flag_unit_at_a_time && !profile_flag)
2829 struct cgraph_local_info *i = cgraph_local_info (decl);
2837 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
2838 DFmode (2) arguments in SSE registers for a function with the
2839 indicated TYPE and DECL. DECL may be NULL when calling function
2840 indirectly or considering a libcall. Otherwise return 0. */
2843 ix86_function_sseregparm (tree type, tree decl)
2845 /* Use SSE registers to pass SFmode and DFmode arguments if requested
2846 by the sseregparm attribute. */
2847 if (TARGET_SSEREGPARM
2849 && lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type))))
2854 error ("Calling %qD with attribute sseregparm without "
2855 "SSE/SSE2 enabled", decl);
2857 error ("Calling %qT with attribute sseregparm without "
2858 "SSE/SSE2 enabled", type);
2865 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
2866 (and DFmode for SSE2) arguments in SSE registers,
2867 even for 32-bit targets. */
2868 if (!TARGET_64BIT && decl
2869 && TARGET_SSE_MATH && flag_unit_at_a_time && !profile_flag)
2871 struct cgraph_local_info *i = cgraph_local_info (decl);
2873 return TARGET_SSE2 ? 2 : 1;
2879 /* Return true if EAX is live at the start of the function. Used by
2880 ix86_expand_prologue to determine if we need special help before
2881 calling allocate_stack_worker. */
2884 ix86_eax_live_at_start_p (void)
2886 /* Cheat. Don't bother working forward from ix86_function_regparm
2887 to the function type to whether an actual argument is located in
2888 eax. Instead just look at cfg info, which is still close enough
2889 to correct at this point. This gives false positives for broken
2890 functions that might use uninitialized data that happens to be
2891 allocated in eax, but who cares? */
2892 return REGNO_REG_SET_P (ENTRY_BLOCK_PTR->il.rtl->global_live_at_end, 0);
2895 /* Value is the number of bytes of arguments automatically
2896 popped when returning from a subroutine call.
2897 FUNDECL is the declaration node of the function (as a tree),
2898 FUNTYPE is the data type of the function (as a tree),
2899 or for a library call it is an identifier node for the subroutine name.
2900 SIZE is the number of bytes of arguments passed on the stack.
2902 On the 80386, the RTD insn may be used to pop them if the number
2903 of args is fixed, but if the number is variable then the caller
2904 must pop them all. RTD can't be used for library calls now
2905 because the library is compiled with the Unix compiler.
2906 Use of RTD is a selectable option, since it is incompatible with
2907 standard Unix calling sequences. If the option is not selected,
2908 the caller must always pop the args.
2910 The attribute stdcall is equivalent to RTD on a per module basis. */
2913 ix86_return_pops_args (tree fundecl, tree funtype, int size)
2915 int rtd = TARGET_RTD && (!fundecl || TREE_CODE (fundecl) != IDENTIFIER_NODE);
2917 /* Cdecl functions override -mrtd, and never pop the stack. */
2918 if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype))) {
2920 /* Stdcall and fastcall functions will pop the stack if not
2922 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype))
2923 || lookup_attribute ("fastcall", TYPE_ATTRIBUTES (funtype)))
2927 && (TYPE_ARG_TYPES (funtype) == NULL_TREE
2928 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (funtype)))
2929 == void_type_node)))
2933 /* Lose any fake structure return argument if it is passed on the stack. */
2934 if (aggregate_value_p (TREE_TYPE (funtype), fundecl)
2936 && !KEEP_AGGREGATE_RETURN_POINTER)
2938 int nregs = ix86_function_regparm (funtype, fundecl);
2941 return GET_MODE_SIZE (Pmode);
2947 /* Argument support functions. */
2949 /* Return true when register may be used to pass function parameters. */
2951 ix86_function_arg_regno_p (int regno)
2955 return (regno < REGPARM_MAX
2956 || (TARGET_80387 && FP_REGNO_P (regno)
2957 && (regno < FIRST_FLOAT_REG + X87_REGPARM_MAX))
2958 || (TARGET_MMX && MMX_REGNO_P (regno)
2959 && (regno < FIRST_MMX_REG + MMX_REGPARM_MAX))
2960 || (TARGET_SSE && SSE_REGNO_P (regno)
2961 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX)));
2963 if (TARGET_SSE && SSE_REGNO_P (regno)
2964 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX))
2966 /* RAX is used as hidden argument to va_arg functions. */
2969 for (i = 0; i < REGPARM_MAX; i++)
2970 if (regno == x86_64_int_parameter_registers[i])
2975 /* Return if we do not know how to pass TYPE solely in registers. */
2978 ix86_must_pass_in_stack (enum machine_mode mode, tree type)
2980 if (must_pass_in_stack_var_size_or_pad (mode, type))
2983 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
2984 The layout_type routine is crafty and tries to trick us into passing
2985 currently unsupported vector types on the stack by using TImode. */
2986 return (!TARGET_64BIT && mode == TImode
2987 && type && TREE_CODE (type) != VECTOR_TYPE);
2990 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2991 for a call to a function whose data type is FNTYPE.
2992 For a library call, FNTYPE is 0. */
2995 init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument info to initialize */
2996 tree fntype, /* tree ptr for function decl */
2997 rtx libname, /* SYMBOL_REF of library name or 0 */
3000 static CUMULATIVE_ARGS zero_cum;
3001 tree param, next_param;
3003 if (TARGET_DEBUG_ARG)
3005 fprintf (stderr, "\ninit_cumulative_args (");
3007 fprintf (stderr, "fntype code = %s, ret code = %s",
3008 tree_code_name[(int) TREE_CODE (fntype)],
3009 tree_code_name[(int) TREE_CODE (TREE_TYPE (fntype))]);
3011 fprintf (stderr, "no fntype");
3014 fprintf (stderr, ", libname = %s", XSTR (libname, 0));
3019 /* Set up the number of registers to use for passing arguments. */
3020 cum->nregs = ix86_regparm;
3022 cum->x87_nregs = X87_REGPARM_MAX;
3024 cum->sse_nregs = SSE_REGPARM_MAX;
3026 cum->mmx_nregs = MMX_REGPARM_MAX;
3027 cum->warn_sse = true;
3028 cum->warn_mmx = true;
3029 cum->maybe_vaarg = false;
3031 /* Use ecx and edx registers if function has fastcall attribute,
3032 else look for regparm information. */
3033 if (fntype && !TARGET_64BIT)
3035 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (fntype)))
3041 cum->nregs = ix86_function_regparm (fntype, fndecl);
3044 /* Set up the number of 80387 registers used for passing
3045 floating point arguments. Warn for mismatching ABI. */
3046 cum->float_in_x87 = ix86_function_x87regparm (fntype, fndecl);
3048 /* Set up the number of SSE registers used for passing SFmode
3049 and DFmode arguments. Warn for mismatching ABI. */
3050 cum->float_in_sse = ix86_function_sseregparm (fntype, fndecl);
3052 /* Determine if this function has variable arguments. This is
3053 indicated by the last argument being 'void_type_mode' if there
3054 are no variable arguments. If there are variable arguments, then
3055 we won't pass anything in registers in 32-bit mode. */
3057 if (cum->nregs || cum->mmx_nregs
3058 || cum->x87_nregs || cum->sse_nregs)
3060 for (param = (fntype) ? TYPE_ARG_TYPES (fntype) : 0;
3061 param != 0; param = next_param)
3063 next_param = TREE_CHAIN (param);
3064 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
3075 cum->float_in_x87 = 0;
3076 cum->float_in_sse = 0;
3078 cum->maybe_vaarg = true;
3082 if ((!fntype && !libname)
3083 || (fntype && !TYPE_ARG_TYPES (fntype)))
3084 cum->maybe_vaarg = true;
3086 if (TARGET_DEBUG_ARG)
3087 fprintf (stderr, ", nregs=%d )\n", cum->nregs);
3092 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
3093 But in the case of vector types, it is some vector mode.
3095 When we have only some of our vector isa extensions enabled, then there
3096 are some modes for which vector_mode_supported_p is false. For these
3097 modes, the generic vector support in gcc will choose some non-vector mode
3098 in order to implement the type. By computing the natural mode, we'll
3099 select the proper ABI location for the operand and not depend on whatever
3100 the middle-end decides to do with these vector types. */
3102 static enum machine_mode
3103 type_natural_mode (tree type)
3105 enum machine_mode mode = TYPE_MODE (type);
3107 if (TREE_CODE (type) == VECTOR_TYPE && !VECTOR_MODE_P (mode))
3109 HOST_WIDE_INT size = int_size_in_bytes (type);
3110 if ((size == 8 || size == 16)
3111 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
3112 && TYPE_VECTOR_SUBPARTS (type) > 1)
3114 enum machine_mode innermode = TYPE_MODE (TREE_TYPE (type));
3116 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
3117 mode = MIN_MODE_VECTOR_FLOAT;
3119 mode = MIN_MODE_VECTOR_INT;
3121 /* Get the mode which has this inner mode and number of units. */
3122 for (; mode != VOIDmode; mode = GET_MODE_WIDER_MODE (mode))
3123 if (GET_MODE_NUNITS (mode) == TYPE_VECTOR_SUBPARTS (type)
3124 && GET_MODE_INNER (mode) == innermode)
3134 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
3135 this may not agree with the mode that the type system has chosen for the
3136 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
3137 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
3140 gen_reg_or_parallel (enum machine_mode mode, enum machine_mode orig_mode,
3145 if (orig_mode != BLKmode)
3146 tmp = gen_rtx_REG (orig_mode, regno);
3149 tmp = gen_rtx_REG (mode, regno);
3150 tmp = gen_rtx_EXPR_LIST (VOIDmode, tmp, const0_rtx);
3151 tmp = gen_rtx_PARALLEL (orig_mode, gen_rtvec (1, tmp));
3157 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
3158 of this code is to classify each 8bytes of incoming argument by the register
3159 class and assign registers accordingly. */
3161 /* Return the union class of CLASS1 and CLASS2.
3162 See the x86-64 PS ABI for details. */
3164 static enum x86_64_reg_class
3165 merge_classes (enum x86_64_reg_class class1, enum x86_64_reg_class class2)
3167 /* Rule #1: If both classes are equal, this is the resulting class. */
3168 if (class1 == class2)
3171 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
3173 if (class1 == X86_64_NO_CLASS)
3175 if (class2 == X86_64_NO_CLASS)
3178 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
3179 if (class1 == X86_64_MEMORY_CLASS || class2 == X86_64_MEMORY_CLASS)
3180 return X86_64_MEMORY_CLASS;
3182 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
3183 if ((class1 == X86_64_INTEGERSI_CLASS && class2 == X86_64_SSESF_CLASS)
3184 || (class2 == X86_64_INTEGERSI_CLASS && class1 == X86_64_SSESF_CLASS))
3185 return X86_64_INTEGERSI_CLASS;
3186 if (class1 == X86_64_INTEGER_CLASS || class1 == X86_64_INTEGERSI_CLASS
3187 || class2 == X86_64_INTEGER_CLASS || class2 == X86_64_INTEGERSI_CLASS)
3188 return X86_64_INTEGER_CLASS;
3190 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
3192 if (class1 == X86_64_X87_CLASS
3193 || class1 == X86_64_X87UP_CLASS
3194 || class1 == X86_64_COMPLEX_X87_CLASS
3195 || class2 == X86_64_X87_CLASS
3196 || class2 == X86_64_X87UP_CLASS
3197 || class2 == X86_64_COMPLEX_X87_CLASS)
3198 return X86_64_MEMORY_CLASS;
3200 /* Rule #6: Otherwise class SSE is used. */
3201 return X86_64_SSE_CLASS;
3204 /* Classify the argument of type TYPE and mode MODE.
3205 CLASSES will be filled by the register class used to pass each word
3206 of the operand. The number of words is returned. In case the parameter
3207 should be passed in memory, 0 is returned. As a special case for zero
3208 sized containers, classes[0] will be NO_CLASS and 1 is returned.
3210 BIT_OFFSET is used internally for handling records and specifies offset
3211 of the offset in bits modulo 256 to avoid overflow cases.
3213 See the x86-64 PS ABI for details.
3217 classify_argument (enum machine_mode mode, tree type,
3218 enum x86_64_reg_class classes[MAX_CLASSES], int bit_offset)
3220 HOST_WIDE_INT bytes =
3221 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
3222 int words = (bytes + (bit_offset % 64) / 8 + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3224 /* Variable sized entities are always passed/returned in memory. */
3228 if (mode != VOIDmode
3229 && targetm.calls.must_pass_in_stack (mode, type))
3232 if (type && AGGREGATE_TYPE_P (type))
3236 enum x86_64_reg_class subclasses[MAX_CLASSES];
3238 /* On x86-64 we pass structures larger than 16 bytes on the stack. */
3242 for (i = 0; i < words; i++)
3243 classes[i] = X86_64_NO_CLASS;
3245 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
3246 signalize memory class, so handle it as special case. */
3249 classes[0] = X86_64_NO_CLASS;
3253 /* Classify each field of record and merge classes. */
3254 switch (TREE_CODE (type))
3257 /* And now merge the fields of structure. */
3258 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3260 if (TREE_CODE (field) == FIELD_DECL)
3264 if (TREE_TYPE (field) == error_mark_node)
3267 /* Bitfields are always classified as integer. Handle them
3268 early, since later code would consider them to be
3269 misaligned integers. */
3270 if (DECL_BIT_FIELD (field))
3272 for (i = (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
3273 i < ((int_bit_position (field) + (bit_offset % 64))
3274 + tree_low_cst (DECL_SIZE (field), 0)
3277 merge_classes (X86_64_INTEGER_CLASS,
3282 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
3283 TREE_TYPE (field), subclasses,
3284 (int_bit_position (field)
3285 + bit_offset) % 256);
3288 for (i = 0; i < num; i++)
3291 (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
3293 merge_classes (subclasses[i], classes[i + pos]);
3301 /* Arrays are handled as small records. */
3304 num = classify_argument (TYPE_MODE (TREE_TYPE (type)),
3305 TREE_TYPE (type), subclasses, bit_offset);
3309 /* The partial classes are now full classes. */
3310 if (subclasses[0] == X86_64_SSESF_CLASS && bytes != 4)
3311 subclasses[0] = X86_64_SSE_CLASS;
3312 if (subclasses[0] == X86_64_INTEGERSI_CLASS && bytes != 4)
3313 subclasses[0] = X86_64_INTEGER_CLASS;
3315 for (i = 0; i < words; i++)
3316 classes[i] = subclasses[i % num];
3321 case QUAL_UNION_TYPE:
3322 /* Unions are similar to RECORD_TYPE but offset is always 0.
3324 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3326 if (TREE_CODE (field) == FIELD_DECL)
3330 if (TREE_TYPE (field) == error_mark_node)
3333 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
3334 TREE_TYPE (field), subclasses,
3338 for (i = 0; i < num; i++)
3339 classes[i] = merge_classes (subclasses[i], classes[i]);
3348 /* Final merger cleanup. */
3349 for (i = 0; i < words; i++)
3351 /* If one class is MEMORY, everything should be passed in
3353 if (classes[i] == X86_64_MEMORY_CLASS)
3356 /* The X86_64_SSEUP_CLASS should be always preceded by
3357 X86_64_SSE_CLASS. */
3358 if (classes[i] == X86_64_SSEUP_CLASS
3359 && (i == 0 || classes[i - 1] != X86_64_SSE_CLASS))
3360 classes[i] = X86_64_SSE_CLASS;
3362 /* X86_64_X87UP_CLASS should be preceded by X86_64_X87_CLASS. */
3363 if (classes[i] == X86_64_X87UP_CLASS
3364 && (i == 0 || classes[i - 1] != X86_64_X87_CLASS))
3365 classes[i] = X86_64_SSE_CLASS;
3370 /* Compute alignment needed. We align all types to natural boundaries with
3371 exception of XFmode that is aligned to 64bits. */
3372 if (mode != VOIDmode && mode != BLKmode)
3374 int mode_alignment = GET_MODE_BITSIZE (mode);
3377 mode_alignment = 128;
3378 else if (mode == XCmode)
3379 mode_alignment = 256;
3380 if (COMPLEX_MODE_P (mode))
3381 mode_alignment /= 2;
3382 /* Misaligned fields are always returned in memory. */
3383 if (bit_offset % mode_alignment)
3387 /* for V1xx modes, just use the base mode */
3388 if (VECTOR_MODE_P (mode)
3389 && GET_MODE_SIZE (GET_MODE_INNER (mode)) == bytes)
3390 mode = GET_MODE_INNER (mode);
3392 /* Classification of atomic types. */
3397 classes[0] = X86_64_SSE_CLASS;
3400 classes[0] = X86_64_SSE_CLASS;
3401 classes[1] = X86_64_SSEUP_CLASS;
3410 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
3411 classes[0] = X86_64_INTEGERSI_CLASS;
3413 classes[0] = X86_64_INTEGER_CLASS;
3417 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
3422 if (!(bit_offset % 64))
3423 classes[0] = X86_64_SSESF_CLASS;
3425 classes[0] = X86_64_SSE_CLASS;
3428 classes[0] = X86_64_SSEDF_CLASS;
3431 classes[0] = X86_64_X87_CLASS;
3432 classes[1] = X86_64_X87UP_CLASS;
3435 classes[0] = X86_64_SSE_CLASS;
3436 classes[1] = X86_64_SSEUP_CLASS;
3439 classes[0] = X86_64_SSE_CLASS;
3442 classes[0] = X86_64_SSEDF_CLASS;
3443 classes[1] = X86_64_SSEDF_CLASS;
3446 classes[0] = X86_64_COMPLEX_X87_CLASS;
3449 /* This modes is larger than 16 bytes. */
3457 classes[0] = X86_64_SSE_CLASS;
3458 classes[1] = X86_64_SSEUP_CLASS;
3464 classes[0] = X86_64_SSE_CLASS;
3470 gcc_assert (VECTOR_MODE_P (mode));
3475 gcc_assert (GET_MODE_CLASS (GET_MODE_INNER (mode)) == MODE_INT);
3477 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
3478 classes[0] = X86_64_INTEGERSI_CLASS;
3480 classes[0] = X86_64_INTEGER_CLASS;
3481 classes[1] = X86_64_INTEGER_CLASS;
3482 return 1 + (bytes > 8);
3486 /* Examine the argument and return set number of register required in each
3487 class. Return 0 iff parameter should be passed in memory. */
3489 examine_argument (enum machine_mode mode, tree type, int in_return,
3490 int *int_nregs, int *sse_nregs)
3492 enum x86_64_reg_class class[MAX_CLASSES];
3493 int n = classify_argument (mode, type, class, 0);
3499 for (n--; n >= 0; n--)
3502 case X86_64_INTEGER_CLASS:
3503 case X86_64_INTEGERSI_CLASS:
3506 case X86_64_SSE_CLASS:
3507 case X86_64_SSESF_CLASS:
3508 case X86_64_SSEDF_CLASS:
3511 case X86_64_NO_CLASS:
3512 case X86_64_SSEUP_CLASS:
3514 case X86_64_X87_CLASS:
3515 case X86_64_X87UP_CLASS:
3519 case X86_64_COMPLEX_X87_CLASS:
3520 return in_return ? 2 : 0;
3521 case X86_64_MEMORY_CLASS:
3527 /* Construct container for the argument used by GCC interface. See
3528 FUNCTION_ARG for the detailed description. */
3531 construct_container (enum machine_mode mode, enum machine_mode orig_mode,
3532 tree type, int in_return, int nintregs, int nsseregs,
3533 const int *intreg, int sse_regno)
3535 /* The following variables hold the static issued_error state. */
3536 static bool issued_sse_arg_error;
3537 static bool issued_sse_ret_error;
3538 static bool issued_x87_ret_error;
3540 enum machine_mode tmpmode;
3542 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
3543 enum x86_64_reg_class class[MAX_CLASSES];
3547 int needed_sseregs, needed_intregs;
3548 rtx exp[MAX_CLASSES];
3551 n = classify_argument (mode, type, class, 0);
3552 if (TARGET_DEBUG_ARG)
3555 fprintf (stderr, "Memory class\n");
3558 fprintf (stderr, "Classes:");
3559 for (i = 0; i < n; i++)
3561 fprintf (stderr, " %s", x86_64_reg_class_name[class[i]]);
3563 fprintf (stderr, "\n");
3568 if (!examine_argument (mode, type, in_return, &needed_intregs,
3571 if (needed_intregs > nintregs || needed_sseregs > nsseregs)
3574 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
3575 some less clueful developer tries to use floating-point anyway. */
3576 if (needed_sseregs && !TARGET_SSE)
3580 if (!issued_sse_ret_error)
3582 error ("SSE register return with SSE disabled");
3583 issued_sse_ret_error = true;
3586 else if (!issued_sse_arg_error)
3588 error ("SSE register argument with SSE disabled");
3589 issued_sse_arg_error = true;
3594 /* Likewise, error if the ABI requires us to return values in the
3595 x87 registers and the user specified -mno-80387. */
3596 if (!TARGET_80387 && in_return)
3597 for (i = 0; i < n; i++)
3598 if (class[i] == X86_64_X87_CLASS
3599 || class[i] == X86_64_X87UP_CLASS
3600 || class[i] == X86_64_COMPLEX_X87_CLASS)
3602 if (!issued_x87_ret_error)
3604 error ("x87 register return with x87 disabled");
3605 issued_x87_ret_error = true;
3610 /* First construct simple cases. Avoid SCmode, since we want to use
3611 single register to pass this type. */
3612 if (n == 1 && mode != SCmode)
3615 case X86_64_INTEGER_CLASS:
3616 case X86_64_INTEGERSI_CLASS:
3617 return gen_rtx_REG (mode, intreg[0]);
3618 case X86_64_SSE_CLASS:
3619 case X86_64_SSESF_CLASS:
3620 case X86_64_SSEDF_CLASS:
3621 return gen_reg_or_parallel (mode, orig_mode, SSE_REGNO (sse_regno));
3622 case X86_64_X87_CLASS:
3623 case X86_64_COMPLEX_X87_CLASS:
3624 return gen_rtx_REG (mode, FIRST_STACK_REG);
3625 case X86_64_NO_CLASS:
3626 /* Zero sized array, struct or class. */
3631 if (n == 2 && class[0] == X86_64_SSE_CLASS && class[1] == X86_64_SSEUP_CLASS
3633 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
3635 && class[0] == X86_64_X87_CLASS && class[1] == X86_64_X87UP_CLASS)
3636 return gen_rtx_REG (XFmode, FIRST_STACK_REG);
3637 if (n == 2 && class[0] == X86_64_INTEGER_CLASS
3638 && class[1] == X86_64_INTEGER_CLASS
3639 && (mode == CDImode || mode == TImode || mode == TFmode)
3640 && intreg[0] + 1 == intreg[1])
3641 return gen_rtx_REG (mode, intreg[0]);
3643 /* Otherwise figure out the entries of the PARALLEL. */
3644 for (i = 0; i < n; i++)
3648 case X86_64_NO_CLASS:
3650 case X86_64_INTEGER_CLASS:
3651 case X86_64_INTEGERSI_CLASS:
3652 /* Merge TImodes on aligned occasions here too. */
3653 if (i * 8 + 8 > bytes)
3654 tmpmode = mode_for_size ((bytes - i * 8) * BITS_PER_UNIT, MODE_INT, 0);
3655 else if (class[i] == X86_64_INTEGERSI_CLASS)
3659 /* We've requested 24 bytes we don't have mode for. Use DImode. */
3660 if (tmpmode == BLKmode)
3662 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
3663 gen_rtx_REG (tmpmode, *intreg),
3667 case X86_64_SSESF_CLASS:
3668 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
3669 gen_rtx_REG (SFmode,
3670 SSE_REGNO (sse_regno)),
3674 case X86_64_SSEDF_CLASS:
3675 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
3676 gen_rtx_REG (DFmode,
3677 SSE_REGNO (sse_regno)),
3681 case X86_64_SSE_CLASS:
3682 if (i < n - 1 && class[i + 1] == X86_64_SSEUP_CLASS)
3686 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
3687 gen_rtx_REG (tmpmode,
3688 SSE_REGNO (sse_regno)),
3690 if (tmpmode == TImode)
3699 /* Empty aligned struct, union or class. */
3703 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nexps));
3704 for (i = 0; i < nexps; i++)
3705 XVECEXP (ret, 0, i) = exp [i];
3709 /* Update the data in CUM to advance over an argument
3710 of mode MODE and data type TYPE.
3711 (TYPE is null for libcalls where that information may not be available.) */
3714 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3715 tree type, int named)
3718 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
3719 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3722 mode = type_natural_mode (type);
3724 if (TARGET_DEBUG_ARG)
3725 fprintf (stderr, "function_adv (sz=%d, wds=%2d, nregs=%d, ssenregs=%d, "
3726 "mode=%s, named=%d)\n\n",
3727 words, cum->words, cum->nregs, cum->sse_nregs,
3728 GET_MODE_NAME (mode), named);
3732 int int_nregs, sse_nregs;
3733 if (!examine_argument (mode, type, 0, &int_nregs, &sse_nregs))
3734 cum->words += words;
3735 else if (sse_nregs <= cum->sse_nregs && int_nregs <= cum->nregs)
3737 cum->nregs -= int_nregs;
3738 cum->sse_nregs -= sse_nregs;
3739 cum->regno += int_nregs;
3740 cum->sse_regno += sse_nregs;
3743 cum->words += words;
3761 cum->words += words;
3762 cum->nregs -= words;
3763 cum->regno += words;
3765 if (cum->nregs <= 0)
3773 if (cum->float_in_sse > 0)
3777 if (cum->float_in_sse > 1)
3780 /* Because no inherent XFmode->DFmode and XFmode->SFmode
3781 rounding takes place when values are passed in x87
3782 registers, pass DFmode and SFmode types to local functions
3783 only when flag_unsafe_math_optimizations is set. */
3784 if (!cum->float_in_x87
3785 || (cum->float_in_x87 == 2
3786 && !flag_unsafe_math_optimizations))
3790 if (!cum->float_in_x87)
3793 if (!type || !AGGREGATE_TYPE_P (type))
3795 cum->x87_nregs -= 1;
3796 cum->x87_regno += 1;
3797 if (cum->x87_nregs <= 0)
3814 if (!type || !AGGREGATE_TYPE_P (type))
3816 cum->sse_nregs -= 1;
3817 cum->sse_regno += 1;
3818 if (cum->sse_nregs <= 0)
3830 if (!type || !AGGREGATE_TYPE_P (type))
3832 cum->mmx_nregs -= 1;
3833 cum->mmx_regno += 1;
3834 if (cum->mmx_nregs <= 0)
3845 /* Define where to put the arguments to a function.
3846 Value is zero to push the argument on the stack,
3847 or a hard register in which to store the argument.
3849 MODE is the argument's machine mode.
3850 TYPE is the data type of the argument (as a tree).
3851 This is null for libcalls where that information may
3853 CUM is a variable of type CUMULATIVE_ARGS which gives info about
3854 the preceding args and about the function being called.
3855 NAMED is nonzero if this argument is a named parameter
3856 (otherwise it is an extra parameter matching an ellipsis). */
3859 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode orig_mode,
3860 tree type, int named)
3862 enum machine_mode mode = orig_mode;
3865 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
3866 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3867 static bool warnedsse, warnedmmx;
3869 /* To simplify the code below, represent vector types with a vector mode
3870 even if MMX/SSE are not active. */
3871 if (type && TREE_CODE (type) == VECTOR_TYPE)
3872 mode = type_natural_mode (type);
3874 /* Handle a hidden AL argument containing number of registers for varargs
3875 x86-64 functions. For i386 ABI just return constm1_rtx to avoid
3877 if (mode == VOIDmode)
3880 return GEN_INT (cum->maybe_vaarg
3881 ? (cum->sse_nregs < 0
3889 ret = construct_container (mode, orig_mode, type, 0, cum->nregs,
3891 &x86_64_int_parameter_registers [cum->regno],
3907 if (words <= cum->nregs)
3909 int regno = cum->regno;
3911 /* Fastcall allocates the first two DWORD (SImode) or
3912 smaller arguments to ECX and EDX. */
3915 if (mode == BLKmode || mode == DImode)
3918 /* ECX not EAX is the first allocated register. */
3922 ret = gen_rtx_REG (mode, regno);
3927 if (cum->float_in_sse > 0)
3931 if (cum->float_in_sse > 1)
3934 /* Because no inherent XFmode->DFmode and XFmode->SFmode
3935 rounding takes place when values are passed in x87
3936 registers, pass DFmode and SFmode types to local functions
3937 only when flag_unsafe_math_optimizations is set. */
3938 if (!cum->float_in_x87
3939 || (cum->float_in_x87 == 2
3940 && !flag_unsafe_math_optimizations))
3944 if (!cum->float_in_x87)
3947 if (!type || !AGGREGATE_TYPE_P (type))
3949 ret = gen_rtx_REG (mode, cum->x87_regno + FIRST_FLOAT_REG);
3961 if (!type || !AGGREGATE_TYPE_P (type))
3963 if (!TARGET_SSE && !warnedsse && cum->warn_sse)
3966 warning (0, "SSE vector argument without SSE enabled "
3970 ret = gen_reg_or_parallel (mode, orig_mode,
3971 cum->sse_regno + FIRST_SSE_REG);
3978 if (!type || !AGGREGATE_TYPE_P (type))
3980 if (!TARGET_MMX && !warnedmmx && cum->warn_mmx)
3983 warning (0, "MMX vector argument without MMX enabled "
3987 ret = gen_reg_or_parallel (mode, orig_mode,
3988 cum->mmx_regno + FIRST_MMX_REG);
3993 if (TARGET_DEBUG_ARG)
3996 "function_arg (size=%d, wds=%2d, nregs=%d, mode=%4s, named=%d, ",
3997 words, cum->words, cum->nregs, GET_MODE_NAME (mode), named);
4000 print_simple_rtl (stderr, ret);
4002 fprintf (stderr, ", stack");
4004 fprintf (stderr, " )\n");
4010 /* A C expression that indicates when an argument must be passed by
4011 reference. If nonzero for an argument, a copy of that argument is
4012 made in memory and a pointer to the argument is passed instead of
4013 the argument itself. The pointer is passed in whatever way is
4014 appropriate for passing a pointer to that type. */
4017 ix86_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
4018 enum machine_mode mode ATTRIBUTE_UNUSED,
4019 tree type, bool named ATTRIBUTE_UNUSED)
4024 if (type && int_size_in_bytes (type) == -1)
4026 if (TARGET_DEBUG_ARG)
4027 fprintf (stderr, "function_arg_pass_by_reference\n");
4034 /* Return true when TYPE should be 128bit aligned for 32bit argument passing
4035 ABI. Only called if TARGET_SSE. */
4037 contains_128bit_aligned_vector_p (tree type)
4039 enum machine_mode mode = TYPE_MODE (type);
4040 if (SSE_REG_MODE_P (mode)
4041 && (!TYPE_USER_ALIGN (type) || TYPE_ALIGN (type) > 128))
4043 if (TYPE_ALIGN (type) < 128)
4046 if (AGGREGATE_TYPE_P (type))
4048 /* Walk the aggregates recursively. */
4049 switch (TREE_CODE (type))
4053 case QUAL_UNION_TYPE:
4057 /* Walk all the structure fields. */
4058 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4060 if (TREE_CODE (field) == FIELD_DECL
4061 && contains_128bit_aligned_vector_p (TREE_TYPE (field)))
4068 /* Just for use if some languages passes arrays by value. */
4069 if (contains_128bit_aligned_vector_p (TREE_TYPE (type)))
4080 /* Gives the alignment boundary, in bits, of an argument with the
4081 specified mode and type. */
4084 ix86_function_arg_boundary (enum machine_mode mode, tree type)
4088 align = TYPE_ALIGN (type);
4090 align = GET_MODE_ALIGNMENT (mode);
4091 if (align < PARM_BOUNDARY)
4092 align = PARM_BOUNDARY;
4095 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
4096 make an exception for SSE modes since these require 128bit
4099 The handling here differs from field_alignment. ICC aligns MMX
4100 arguments to 4 byte boundaries, while structure fields are aligned
4101 to 8 byte boundaries. */
4103 align = PARM_BOUNDARY;
4106 if (!SSE_REG_MODE_P (mode))
4107 align = PARM_BOUNDARY;
4111 if (!contains_128bit_aligned_vector_p (type))
4112 align = PARM_BOUNDARY;
4120 /* Return true if N is a possible register number of function value. */
4122 ix86_function_value_regno_p (int regno)
4125 || (regno == FIRST_FLOAT_REG && TARGET_FLOAT_RETURNS_IN_80387)
4126 || (regno == FIRST_SSE_REG && TARGET_SSE))
4130 && (regno == FIRST_MMX_REG && TARGET_MMX))
4136 /* Define how to find the value returned by a function.
4137 VALTYPE is the data type of the value (as a tree).
4138 If the precise function being called is known, FUNC is its FUNCTION_DECL;
4139 otherwise, FUNC is 0. */
4141 ix86_function_value (tree valtype, tree fntype_or_decl,
4142 bool outgoing ATTRIBUTE_UNUSED)
4144 enum machine_mode natmode = type_natural_mode (valtype);
4148 rtx ret = construct_container (natmode, TYPE_MODE (valtype), valtype,
4149 1, REGPARM_MAX, SSE_REGPARM_MAX,
4150 x86_64_int_return_registers, 0);
4151 /* For zero sized structures, construct_container return NULL, but we
4152 need to keep rest of compiler happy by returning meaningful value. */
4154 ret = gen_rtx_REG (TYPE_MODE (valtype), 0);
4159 tree fn = NULL_TREE, fntype;
4161 && DECL_P (fntype_or_decl))
4162 fn = fntype_or_decl;
4163 fntype = fn ? TREE_TYPE (fn) : fntype_or_decl;
4164 return gen_rtx_REG (TYPE_MODE (valtype),
4165 ix86_value_regno (natmode, fn, fntype));
4169 /* Return true iff type is returned in memory. */
4171 ix86_return_in_memory (tree type)
4173 int needed_intregs, needed_sseregs, size;
4174 enum machine_mode mode = type_natural_mode (type);
4177 return !examine_argument (mode, type, 1, &needed_intregs, &needed_sseregs);
4179 if (mode == BLKmode)
4182 size = int_size_in_bytes (type);
4184 if (MS_AGGREGATE_RETURN && AGGREGATE_TYPE_P (type) && size <= 8)
4187 if (VECTOR_MODE_P (mode) || mode == TImode)
4189 /* User-created vectors small enough to fit in EAX. */
4193 /* MMX/3dNow values are returned in MM0,
4194 except when it doesn't exits. */
4196 return (TARGET_MMX ? 0 : 1);
4198 /* SSE values are returned in XMM0, except when it doesn't exist. */
4200 return (TARGET_SSE ? 0 : 1);
4214 /* When returning SSE vector types, we have a choice of either
4215 (1) being abi incompatible with a -march switch, or
4216 (2) generating an error.
4217 Given no good solution, I think the safest thing is one warning.
4218 The user won't be able to use -Werror, but....
4220 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
4221 called in response to actually generating a caller or callee that
4222 uses such a type. As opposed to RETURN_IN_MEMORY, which is called
4223 via aggregate_value_p for general type probing from tree-ssa. */
4226 ix86_struct_value_rtx (tree type, int incoming ATTRIBUTE_UNUSED)
4228 static bool warnedsse, warnedmmx;
4232 /* Look at the return type of the function, not the function type. */
4233 enum machine_mode mode = TYPE_MODE (TREE_TYPE (type));
4235 if (!TARGET_SSE && !warnedsse)
4238 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
4241 warning (0, "SSE vector return without SSE enabled "
4246 if (!TARGET_MMX && !warnedmmx)
4248 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
4251 warning (0, "MMX vector return without MMX enabled "
4260 /* Define how to find the value returned by a library function
4261 assuming the value has mode MODE. */
4263 ix86_libcall_value (enum machine_mode mode)
4277 return gen_rtx_REG (mode, FIRST_SSE_REG);
4280 return gen_rtx_REG (mode, FIRST_FLOAT_REG);
4284 return gen_rtx_REG (mode, 0);
4288 return gen_rtx_REG (mode, ix86_value_regno (mode, NULL, NULL));
4291 /* Given a mode, return the register to use for a return value. */
4294 ix86_value_regno (enum machine_mode mode, tree func, tree fntype)
4296 gcc_assert (!TARGET_64BIT);
4298 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
4299 we normally prevent this case when mmx is not available. However
4300 some ABIs may require the result to be returned like DImode. */
4301 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
4302 return TARGET_MMX ? FIRST_MMX_REG : 0;
4304 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
4305 we prevent this case when sse is not available. However some ABIs
4306 may require the result to be returned like integer TImode. */
4307 if (mode == TImode || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
4308 return TARGET_SSE ? FIRST_SSE_REG : 0;
4310 /* Decimal floating point values can go in %eax, unlike other float modes. */
4311 if (DECIMAL_FLOAT_MODE_P (mode))
4314 /* Most things go in %eax, except (unless -mno-fp-ret-in-387) fp values. */
4315 if (!SCALAR_FLOAT_MODE_P (mode) || !TARGET_FLOAT_RETURNS_IN_80387)
4318 /* Floating point return values in %st(0), except for local functions when
4319 SSE math is enabled or for functions with sseregparm attribute. */
4320 if ((func || fntype)
4321 && (mode == SFmode || mode == DFmode))
4323 int sse_level = ix86_function_sseregparm (fntype, func);
4324 if ((sse_level >= 1 && mode == SFmode)
4325 || (sse_level == 2 && mode == DFmode))
4326 return FIRST_SSE_REG;
4329 return FIRST_FLOAT_REG;
4332 /* Create the va_list data type. */
4335 ix86_build_builtin_va_list (void)
4337 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
4339 /* For i386 we use plain pointer to argument area. */
4341 return build_pointer_type (char_type_node);
4343 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
4344 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
4346 f_gpr = build_decl (FIELD_DECL, get_identifier ("gp_offset"),
4347 unsigned_type_node);
4348 f_fpr = build_decl (FIELD_DECL, get_identifier ("fp_offset"),
4349 unsigned_type_node);
4350 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
4352 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
4355 va_list_gpr_counter_field = f_gpr;
4356 va_list_fpr_counter_field = f_fpr;
4358 DECL_FIELD_CONTEXT (f_gpr) = record;
4359 DECL_FIELD_CONTEXT (f_fpr) = record;
4360 DECL_FIELD_CONTEXT (f_ovf) = record;
4361 DECL_FIELD_CONTEXT (f_sav) = record;
4363 TREE_CHAIN (record) = type_decl;
4364 TYPE_NAME (record) = type_decl;
4365 TYPE_FIELDS (record) = f_gpr;
4366 TREE_CHAIN (f_gpr) = f_fpr;
4367 TREE_CHAIN (f_fpr) = f_ovf;
4368 TREE_CHAIN (f_ovf) = f_sav;
4370 layout_type (record);
4372 /* The correct type is an array type of one element. */
4373 return build_array_type (record, build_index_type (size_zero_node));
4376 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
4379 ix86_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4380 tree type, int *pretend_size ATTRIBUTE_UNUSED,
4383 CUMULATIVE_ARGS next_cum;
4384 rtx save_area = NULL_RTX, mem;
4397 if (! cfun->va_list_gpr_size && ! cfun->va_list_fpr_size)
4400 /* Indicate to allocate space on the stack for varargs save area. */
4401 ix86_save_varrargs_registers = 1;
4403 cfun->stack_alignment_needed = 128;
4405 fntype = TREE_TYPE (current_function_decl);
4406 stdarg_p = (TYPE_ARG_TYPES (fntype) != 0
4407 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4408 != void_type_node));
4410 /* For varargs, we do not want to skip the dummy va_dcl argument.
4411 For stdargs, we do want to skip the last named argument. */
4414 function_arg_advance (&next_cum, mode, type, 1);
4417 save_area = frame_pointer_rtx;
4419 set = get_varargs_alias_set ();
4421 for (i = next_cum.regno;
4423 && i < next_cum.regno + cfun->va_list_gpr_size / UNITS_PER_WORD;
4426 mem = gen_rtx_MEM (Pmode,
4427 plus_constant (save_area, i * UNITS_PER_WORD));
4428 MEM_NOTRAP_P (mem) = 1;
4429 set_mem_alias_set (mem, set);
4430 emit_move_insn (mem, gen_rtx_REG (Pmode,
4431 x86_64_int_parameter_registers[i]));
4434 if (next_cum.sse_nregs && cfun->va_list_fpr_size)
4436 /* Now emit code to save SSE registers. The AX parameter contains number
4437 of SSE parameter registers used to call this function. We use
4438 sse_prologue_save insn template that produces computed jump across
4439 SSE saves. We need some preparation work to get this working. */
4441 label = gen_label_rtx ();
4442 label_ref = gen_rtx_LABEL_REF (Pmode, label);
4444 /* Compute address to jump to :
4445 label - 5*eax + nnamed_sse_arguments*5 */
4446 tmp_reg = gen_reg_rtx (Pmode);
4447 nsse_reg = gen_reg_rtx (Pmode);
4448 emit_insn (gen_zero_extendqidi2 (nsse_reg, gen_rtx_REG (QImode, 0)));
4449 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
4450 gen_rtx_MULT (Pmode, nsse_reg,
4452 if (next_cum.sse_regno)
4455 gen_rtx_CONST (DImode,
4456 gen_rtx_PLUS (DImode,
4458 GEN_INT (next_cum.sse_regno * 4))));
4460 emit_move_insn (nsse_reg, label_ref);
4461 emit_insn (gen_subdi3 (nsse_reg, nsse_reg, tmp_reg));
4463 /* Compute address of memory block we save into. We always use pointer
4464 pointing 127 bytes after first byte to store - this is needed to keep
4465 instruction size limited by 4 bytes. */
4466 tmp_reg = gen_reg_rtx (Pmode);
4467 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
4468 plus_constant (save_area,
4469 8 * REGPARM_MAX + 127)));
4470 mem = gen_rtx_MEM (BLKmode, plus_constant (tmp_reg, -127));
4471 MEM_NOTRAP_P (mem) = 1;
4472 set_mem_alias_set (mem, set);
4473 set_mem_align (mem, BITS_PER_WORD);
4475 /* And finally do the dirty job! */
4476 emit_insn (gen_sse_prologue_save (mem, nsse_reg,
4477 GEN_INT (next_cum.sse_regno), label));
4482 /* Implement va_start. */
4485 ix86_va_start (tree valist, rtx nextarg)
4487 HOST_WIDE_INT words, n_gpr, n_fpr;
4488 tree f_gpr, f_fpr, f_ovf, f_sav;
4489 tree gpr, fpr, ovf, sav, t;
4492 /* Only 64bit target needs something special. */
4495 std_expand_builtin_va_start (valist, nextarg);
4499 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
4500 f_fpr = TREE_CHAIN (f_gpr);
4501 f_ovf = TREE_CHAIN (f_fpr);
4502 f_sav = TREE_CHAIN (f_ovf);
4504 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
4505 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
4506 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
4507 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
4508 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
4510 /* Count number of gp and fp argument registers used. */
4511 words = current_function_args_info.words;
4512 n_gpr = current_function_args_info.regno;
4513 n_fpr = current_function_args_info.sse_regno;
4515 if (TARGET_DEBUG_ARG)
4516 fprintf (stderr, "va_start: words = %d, n_gpr = %d, n_fpr = %d\n",
4517 (int) words, (int) n_gpr, (int) n_fpr);
4519 if (cfun->va_list_gpr_size)
4521 type = TREE_TYPE (gpr);
4522 t = build2 (MODIFY_EXPR, type, gpr,
4523 build_int_cst (type, n_gpr * 8));
4524 TREE_SIDE_EFFECTS (t) = 1;
4525 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4528 if (cfun->va_list_fpr_size)
4530 type = TREE_TYPE (fpr);
4531 t = build2 (MODIFY_EXPR, type, fpr,
4532 build_int_cst (type, n_fpr * 16 + 8*REGPARM_MAX));
4533 TREE_SIDE_EFFECTS (t) = 1;
4534 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4537 /* Find the overflow area. */
4538 type = TREE_TYPE (ovf);
4539 t = make_tree (type, virtual_incoming_args_rtx);
4541 t = build2 (PLUS_EXPR, type, t,
4542 build_int_cst (type, words * UNITS_PER_WORD));
4543 t = build2 (MODIFY_EXPR, type, ovf, t);
4544 TREE_SIDE_EFFECTS (t) = 1;
4545 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4547 if (cfun->va_list_gpr_size || cfun->va_list_fpr_size)
4549 /* Find the register save area.
4550 Prologue of the function save it right above stack frame. */
4551 type = TREE_TYPE (sav);
4552 t = make_tree (type, frame_pointer_rtx);
4553 t = build2 (MODIFY_EXPR, type, sav, t);
4554 TREE_SIDE_EFFECTS (t) = 1;
4555 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4559 /* Implement va_arg. */
4562 ix86_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
4564 static const int intreg[6] = { 0, 1, 2, 3, 4, 5 };
4565 tree f_gpr, f_fpr, f_ovf, f_sav;
4566 tree gpr, fpr, ovf, sav, t;
4568 tree lab_false, lab_over = NULL_TREE;
4573 enum machine_mode nat_mode;
4575 /* Only 64bit target needs something special. */
4577 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
4579 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
4580 f_fpr = TREE_CHAIN (f_gpr);
4581 f_ovf = TREE_CHAIN (f_fpr);
4582 f_sav = TREE_CHAIN (f_ovf);
4584 valist = build_va_arg_indirect_ref (valist);
4585 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
4586 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
4587 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
4588 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
4590 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, false);
4592 type = build_pointer_type (type);
4593 size = int_size_in_bytes (type);
4594 rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4596 nat_mode = type_natural_mode (type);
4597 container = construct_container (nat_mode, TYPE_MODE (type), type, 0,
4598 REGPARM_MAX, SSE_REGPARM_MAX, intreg, 0);
4600 /* Pull the value out of the saved registers. */
4602 addr = create_tmp_var (ptr_type_node, "addr");
4603 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
4607 int needed_intregs, needed_sseregs;
4609 tree int_addr, sse_addr;
4611 lab_false = create_artificial_label ();
4612 lab_over = create_artificial_label ();
4614 examine_argument (nat_mode, type, 0, &needed_intregs, &needed_sseregs);
4616 need_temp = (!REG_P (container)
4617 && ((needed_intregs && TYPE_ALIGN (type) > 64)
4618 || TYPE_ALIGN (type) > 128));
4620 /* In case we are passing structure, verify that it is consecutive block
4621 on the register save area. If not we need to do moves. */
4622 if (!need_temp && !REG_P (container))
4624 /* Verify that all registers are strictly consecutive */
4625 if (SSE_REGNO_P (REGNO (XEXP (XVECEXP (container, 0, 0), 0))))
4629 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
4631 rtx slot = XVECEXP (container, 0, i);
4632 if (REGNO (XEXP (slot, 0)) != FIRST_SSE_REG + (unsigned int) i
4633 || INTVAL (XEXP (slot, 1)) != i * 16)
4641 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
4643 rtx slot = XVECEXP (container, 0, i);
4644 if (REGNO (XEXP (slot, 0)) != (unsigned int) i
4645 || INTVAL (XEXP (slot, 1)) != i * 8)
4657 int_addr = create_tmp_var (ptr_type_node, "int_addr");
4658 DECL_POINTER_ALIAS_SET (int_addr) = get_varargs_alias_set ();
4659 sse_addr = create_tmp_var (ptr_type_node, "sse_addr");
4660 DECL_POINTER_ALIAS_SET (sse_addr) = get_varargs_alias_set ();
4663 /* First ensure that we fit completely in registers. */
4666 t = build_int_cst (TREE_TYPE (gpr),
4667 (REGPARM_MAX - needed_intregs + 1) * 8);
4668 t = build2 (GE_EXPR, boolean_type_node, gpr, t);
4669 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
4670 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
4671 gimplify_and_add (t, pre_p);
4675 t = build_int_cst (TREE_TYPE (fpr),
4676 (SSE_REGPARM_MAX - needed_sseregs + 1) * 16
4678 t = build2 (GE_EXPR, boolean_type_node, fpr, t);
4679 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
4680 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
4681 gimplify_and_add (t, pre_p);
4684 /* Compute index to start of area used for integer regs. */
4687 /* int_addr = gpr + sav; */
4688 t = fold_convert (ptr_type_node, gpr);
4689 t = build2 (PLUS_EXPR, ptr_type_node, sav, t);
4690 t = build2 (MODIFY_EXPR, void_type_node, int_addr, t);
4691 gimplify_and_add (t, pre_p);
4695 /* sse_addr = fpr + sav; */
4696 t = fold_convert (ptr_type_node, fpr);
4697 t = build2 (PLUS_EXPR, ptr_type_node, sav, t);
4698 t = build2 (MODIFY_EXPR, void_type_node, sse_addr, t);
4699 gimplify_and_add (t, pre_p);
4704 tree temp = create_tmp_var (type, "va_arg_tmp");
4707 t = build1 (ADDR_EXPR, build_pointer_type (type), temp);
4708 t = build2 (MODIFY_EXPR, void_type_node, addr, t);
4709 gimplify_and_add (t, pre_p);
4711 for (i = 0; i < XVECLEN (container, 0); i++)
4713 rtx slot = XVECEXP (container, 0, i);
4714 rtx reg = XEXP (slot, 0);
4715 enum machine_mode mode = GET_MODE (reg);
4716 tree piece_type = lang_hooks.types.type_for_mode (mode, 1);
4717 tree addr_type = build_pointer_type (piece_type);
4720 tree dest_addr, dest;
4722 if (SSE_REGNO_P (REGNO (reg)))
4724 src_addr = sse_addr;
4725 src_offset = (REGNO (reg) - FIRST_SSE_REG) * 16;
4729 src_addr = int_addr;
4730 src_offset = REGNO (reg) * 8;
4732 src_addr = fold_convert (addr_type, src_addr);
4733 src_addr = fold (build2 (PLUS_EXPR, addr_type, src_addr,
4734 size_int (src_offset)));
4735 src = build_va_arg_indirect_ref (src_addr);
4737 dest_addr = fold_convert (addr_type, addr);
4738 dest_addr = fold (build2 (PLUS_EXPR, addr_type, dest_addr,
4739 size_int (INTVAL (XEXP (slot, 1)))));
4740 dest = build_va_arg_indirect_ref (dest_addr);
4742 t = build2 (MODIFY_EXPR, void_type_node, dest, src);
4743 gimplify_and_add (t, pre_p);
4749 t = build2 (PLUS_EXPR, TREE_TYPE (gpr), gpr,
4750 build_int_cst (TREE_TYPE (gpr), needed_intregs * 8));
4751 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr, t);
4752 gimplify_and_add (t, pre_p);
4756 t = build2 (PLUS_EXPR, TREE_TYPE (fpr), fpr,
4757 build_int_cst (TREE_TYPE (fpr), needed_sseregs * 16));
4758 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr, t);
4759 gimplify_and_add (t, pre_p);
4762 t = build1 (GOTO_EXPR, void_type_node, lab_over);
4763 gimplify_and_add (t, pre_p);
4765 t = build1 (LABEL_EXPR, void_type_node, lab_false);
4766 append_to_statement_list (t, pre_p);
4769 /* ... otherwise out of the overflow area. */
4771 /* Care for on-stack alignment if needed. */
4772 if (FUNCTION_ARG_BOUNDARY (VOIDmode, type) <= 64
4773 || integer_zerop (TYPE_SIZE (type)))
4777 HOST_WIDE_INT align = FUNCTION_ARG_BOUNDARY (VOIDmode, type) / 8;
4778 t = build2 (PLUS_EXPR, TREE_TYPE (ovf), ovf,
4779 build_int_cst (TREE_TYPE (ovf), align - 1));
4780 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
4781 build_int_cst (TREE_TYPE (t), -align));
4783 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
4785 t2 = build2 (MODIFY_EXPR, void_type_node, addr, t);
4786 gimplify_and_add (t2, pre_p);
4788 t = build2 (PLUS_EXPR, TREE_TYPE (t), t,
4789 build_int_cst (TREE_TYPE (t), rsize * UNITS_PER_WORD));
4790 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
4791 gimplify_and_add (t, pre_p);
4795 t = build1 (LABEL_EXPR, void_type_node, lab_over);
4796 append_to_statement_list (t, pre_p);
4799 ptrtype = build_pointer_type (type);
4800 addr = fold_convert (ptrtype, addr);
4803 addr = build_va_arg_indirect_ref (addr);
4804 return build_va_arg_indirect_ref (addr);
4807 /* Return nonzero if OPNUM's MEM should be matched
4808 in movabs* patterns. */
4811 ix86_check_movabs (rtx insn, int opnum)
4815 set = PATTERN (insn);
4816 if (GET_CODE (set) == PARALLEL)
4817 set = XVECEXP (set, 0, 0);
4818 gcc_assert (GET_CODE (set) == SET);
4819 mem = XEXP (set, opnum);
4820 while (GET_CODE (mem) == SUBREG)
4821 mem = SUBREG_REG (mem);
4822 gcc_assert (GET_CODE (mem) == MEM);
4823 return (volatile_ok || !MEM_VOLATILE_P (mem));
4826 /* Initialize the table of extra 80387 mathematical constants. */
4829 init_ext_80387_constants (void)
4831 static const char * cst[5] =
4833 "0.3010299956639811952256464283594894482", /* 0: fldlg2 */
4834 "0.6931471805599453094286904741849753009", /* 1: fldln2 */
4835 "1.4426950408889634073876517827983434472", /* 2: fldl2e */
4836 "3.3219280948873623478083405569094566090", /* 3: fldl2t */
4837 "3.1415926535897932385128089594061862044", /* 4: fldpi */
4841 for (i = 0; i < 5; i++)
4843 real_from_string (&ext_80387_constants_table[i], cst[i]);
4844 /* Ensure each constant is rounded to XFmode precision. */
4845 real_convert (&ext_80387_constants_table[i],
4846 XFmode, &ext_80387_constants_table[i]);
4849 ext_80387_constants_init = 1;
4852 /* Return true if the constant is something that can be loaded with
4853 a special instruction. */
4856 standard_80387_constant_p (rtx x)
4860 if (GET_CODE (x) != CONST_DOUBLE || !FLOAT_MODE_P (GET_MODE (x)))
4863 if (x == CONST0_RTX (GET_MODE (x)))
4865 if (x == CONST1_RTX (GET_MODE (x)))
4868 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
4870 /* For XFmode constants, try to find a special 80387 instruction when
4871 optimizing for size or on those CPUs that benefit from them. */
4872 if (GET_MODE (x) == XFmode
4873 && (optimize_size || x86_ext_80387_constants & TUNEMASK))
4877 if (! ext_80387_constants_init)
4878 init_ext_80387_constants ();
4880 for (i = 0; i < 5; i++)
4881 if (real_identical (&r, &ext_80387_constants_table[i]))
4885 /* Load of the constant -0.0 or -1.0 will be split as
4886 fldz;fchs or fld1;fchs sequence. */
4887 if (real_isnegzero (&r))
4889 if (real_identical (&r, &dconstm1))
4895 /* Return the opcode of the special instruction to be used to load
4899 standard_80387_constant_opcode (rtx x)
4901 switch (standard_80387_constant_p (x))
4925 /* Return the CONST_DOUBLE representing the 80387 constant that is
4926 loaded by the specified special instruction. The argument IDX
4927 matches the return value from standard_80387_constant_p. */
4930 standard_80387_constant_rtx (int idx)
4934 if (! ext_80387_constants_init)
4935 init_ext_80387_constants ();
4951 return CONST_DOUBLE_FROM_REAL_VALUE (ext_80387_constants_table[i],
4955 /* Return 1 if mode is a valid mode for sse. */
4957 standard_sse_mode_p (enum machine_mode mode)
4974 /* Return 1 if X is FP constant we can load to SSE register w/o using memory.
4977 standard_sse_constant_p (rtx x)
4979 enum machine_mode mode = GET_MODE (x);
4981 if (x == const0_rtx || x == CONST0_RTX (GET_MODE (x)))
4983 if (vector_all_ones_operand (x, mode)
4984 && standard_sse_mode_p (mode))
4985 return TARGET_SSE2 ? 2 : -1;
4990 /* Return the opcode of the special instruction to be used to load
4994 standard_sse_constant_opcode (rtx insn, rtx x)
4996 switch (standard_sse_constant_p (x))
4999 if (get_attr_mode (insn) == MODE_V4SF)
5000 return "xorps\t%0, %0";
5001 else if (get_attr_mode (insn) == MODE_V2DF)
5002 return "xorpd\t%0, %0";
5004 return "pxor\t%0, %0";
5006 return "pcmpeqd\t%0, %0";
5011 /* Returns 1 if OP contains a symbol reference */
5014 symbolic_reference_mentioned_p (rtx op)
5019 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
5022 fmt = GET_RTX_FORMAT (GET_CODE (op));
5023 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
5029 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
5030 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
5034 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
5041 /* Return 1 if it is appropriate to emit `ret' instructions in the
5042 body of a function. Do this only if the epilogue is simple, needing a
5043 couple of insns. Prior to reloading, we can't tell how many registers
5044 must be saved, so return 0 then. Return 0 if there is no frame
5045 marker to de-allocate. */
5048 ix86_can_use_return_insn_p (void)
5050 struct ix86_frame frame;
5052 if (! reload_completed || frame_pointer_needed)
5055 /* Don't allow more than 32 pop, since that's all we can do
5056 with one instruction. */
5057 if (current_function_pops_args
5058 && current_function_args_size >= 32768)
5061 ix86_compute_frame_layout (&frame);
5062 return frame.to_allocate == 0 && frame.nregs == 0;
5065 /* Value should be nonzero if functions must have frame pointers.
5066 Zero means the frame pointer need not be set up (and parms may
5067 be accessed via the stack pointer) in functions that seem suitable. */
5070 ix86_frame_pointer_required (void)
5072 /* If we accessed previous frames, then the generated code expects
5073 to be able to access the saved ebp value in our frame. */
5074 if (cfun->machine->accesses_prev_frame)
5077 /* Several x86 os'es need a frame pointer for other reasons,
5078 usually pertaining to setjmp. */
5079 if (SUBTARGET_FRAME_POINTER_REQUIRED)
5082 /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
5083 the frame pointer by default. Turn it back on now if we've not
5084 got a leaf function. */
5085 if (TARGET_OMIT_LEAF_FRAME_POINTER
5086 && (!current_function_is_leaf
5087 || ix86_current_function_calls_tls_descriptor))
5090 if (current_function_profile)
5096 /* Record that the current function accesses previous call frames. */
5099 ix86_setup_frame_addresses (void)
5101 cfun->machine->accesses_prev_frame = 1;
5104 #if (defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)) || TARGET_MACHO
5105 # define USE_HIDDEN_LINKONCE 1
5107 # define USE_HIDDEN_LINKONCE 0
5110 static int pic_labels_used;
5112 /* Fills in the label name that should be used for a pc thunk for
5113 the given register. */
5116 get_pc_thunk_name (char name[32], unsigned int regno)
5118 gcc_assert (!TARGET_64BIT);
5120 if (USE_HIDDEN_LINKONCE)
5121 sprintf (name, "__i686.get_pc_thunk.%s", reg_names[regno]);
5123 ASM_GENERATE_INTERNAL_LABEL (name, "LPR", regno);
5127 /* This function generates code for -fpic that loads %ebx with
5128 the return address of the caller and then returns. */
5131 ix86_file_end (void)
5136 for (regno = 0; regno < 8; ++regno)
5140 if (! ((pic_labels_used >> regno) & 1))
5143 get_pc_thunk_name (name, regno);
5148 switch_to_section (darwin_sections[text_coal_section]);
5149 fputs ("\t.weak_definition\t", asm_out_file);
5150 assemble_name (asm_out_file, name);
5151 fputs ("\n\t.private_extern\t", asm_out_file);
5152 assemble_name (asm_out_file, name);
5153 fputs ("\n", asm_out_file);
5154 ASM_OUTPUT_LABEL (asm_out_file, name);
5158 if (USE_HIDDEN_LINKONCE)
5162 decl = build_decl (FUNCTION_DECL, get_identifier (name),
5164 TREE_PUBLIC (decl) = 1;
5165 TREE_STATIC (decl) = 1;
5166 DECL_ONE_ONLY (decl) = 1;
5168 (*targetm.asm_out.unique_section) (decl, 0);
5169 switch_to_section (get_named_section (decl, NULL, 0));
5171 (*targetm.asm_out.globalize_label) (asm_out_file, name);
5172 fputs ("\t.hidden\t", asm_out_file);
5173 assemble_name (asm_out_file, name);
5174 fputc ('\n', asm_out_file);
5175 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
5179 switch_to_section (text_section);
5180 ASM_OUTPUT_LABEL (asm_out_file, name);
5183 xops[0] = gen_rtx_REG (SImode, regno);
5184 xops[1] = gen_rtx_MEM (SImode, stack_pointer_rtx);
5185 output_asm_insn ("mov{l}\t{%1, %0|%0, %1}", xops);
5186 output_asm_insn ("ret", xops);
5189 if (NEED_INDICATE_EXEC_STACK)
5190 file_end_indicate_exec_stack ();
5193 /* Emit code for the SET_GOT patterns. */
5196 output_set_got (rtx dest, rtx label ATTRIBUTE_UNUSED)
5201 xops[1] = gen_rtx_SYMBOL_REF (Pmode, GOT_SYMBOL_NAME);
5203 if (! TARGET_DEEP_BRANCH_PREDICTION || !flag_pic)
5205 xops[2] = gen_rtx_LABEL_REF (Pmode, label ? label : gen_label_rtx ());
5208 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops);
5210 output_asm_insn ("call\t%a2", xops);
5213 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
5214 is what will be referenced by the Mach-O PIC subsystem. */
5216 ASM_OUTPUT_LABEL (asm_out_file, machopic_function_base_name ());
5219 (*targetm.asm_out.internal_label) (asm_out_file, "L",
5220 CODE_LABEL_NUMBER (XEXP (xops[2], 0)));
5223 output_asm_insn ("pop{l}\t%0", xops);
5228 get_pc_thunk_name (name, REGNO (dest));
5229 pic_labels_used |= 1 << REGNO (dest);
5231 xops[2] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
5232 xops[2] = gen_rtx_MEM (QImode, xops[2]);
5233 output_asm_insn ("call\t%X2", xops);
5234 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
5235 is what will be referenced by the Mach-O PIC subsystem. */
5238 ASM_OUTPUT_LABEL (asm_out_file, machopic_function_base_name ());
5240 targetm.asm_out.internal_label (asm_out_file, "L",
5241 CODE_LABEL_NUMBER (label));
5248 if (!flag_pic || TARGET_DEEP_BRANCH_PREDICTION)
5249 output_asm_insn ("add{l}\t{%1, %0|%0, %1}", xops);
5251 output_asm_insn ("add{l}\t{%1+[.-%a2], %0|%0, %1+(.-%a2)}", xops);
5256 /* Generate an "push" pattern for input ARG. */
5261 return gen_rtx_SET (VOIDmode,
5263 gen_rtx_PRE_DEC (Pmode,
5264 stack_pointer_rtx)),
5268 /* Return >= 0 if there is an unused call-clobbered register available
5269 for the entire function. */
5272 ix86_select_alt_pic_regnum (void)
5274 if (current_function_is_leaf && !current_function_profile
5275 && !ix86_current_function_calls_tls_descriptor)
5278 for (i = 2; i >= 0; --i)
5279 if (!regs_ever_live[i])
5283 return INVALID_REGNUM;
5286 /* Return 1 if we need to save REGNO. */
5288 ix86_save_reg (unsigned int regno, int maybe_eh_return)
5290 if (pic_offset_table_rtx
5291 && regno == REAL_PIC_OFFSET_TABLE_REGNUM
5292 && (regs_ever_live[REAL_PIC_OFFSET_TABLE_REGNUM]
5293 || current_function_profile
5294 || current_function_calls_eh_return
5295 || current_function_uses_const_pool))
5297 if (ix86_select_alt_pic_regnum () != INVALID_REGNUM)
5302 if (current_function_calls_eh_return && maybe_eh_return)
5307 unsigned test = EH_RETURN_DATA_REGNO (i);
5308 if (test == INVALID_REGNUM)
5315 if (cfun->machine->force_align_arg_pointer
5316 && regno == REGNO (cfun->machine->force_align_arg_pointer))
5319 return (regs_ever_live[regno]
5320 && !call_used_regs[regno]
5321 && !fixed_regs[regno]
5322 && (regno != HARD_FRAME_POINTER_REGNUM || !frame_pointer_needed));
5325 /* Return number of registers to be saved on the stack. */
5328 ix86_nsaved_regs (void)
5333 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno--)
5334 if (ix86_save_reg (regno, true))
5339 /* Return the offset between two registers, one to be eliminated, and the other
5340 its replacement, at the start of a routine. */
5343 ix86_initial_elimination_offset (int from, int to)
5345 struct ix86_frame frame;
5346 ix86_compute_frame_layout (&frame);
5348 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
5349 return frame.hard_frame_pointer_offset;
5350 else if (from == FRAME_POINTER_REGNUM
5351 && to == HARD_FRAME_POINTER_REGNUM)
5352 return frame.hard_frame_pointer_offset - frame.frame_pointer_offset;
5355 gcc_assert (to == STACK_POINTER_REGNUM);
5357 if (from == ARG_POINTER_REGNUM)
5358 return frame.stack_pointer_offset;
5360 gcc_assert (from == FRAME_POINTER_REGNUM);
5361 return frame.stack_pointer_offset - frame.frame_pointer_offset;
5365 /* Fill structure ix86_frame about frame of currently computed function. */
5368 ix86_compute_frame_layout (struct ix86_frame *frame)
5370 HOST_WIDE_INT total_size;
5371 unsigned int stack_alignment_needed;
5372 HOST_WIDE_INT offset;
5373 unsigned int preferred_alignment;
5374 HOST_WIDE_INT size = get_frame_size ();
5376 frame->nregs = ix86_nsaved_regs ();
5379 stack_alignment_needed = cfun->stack_alignment_needed / BITS_PER_UNIT;
5380 preferred_alignment = cfun->preferred_stack_boundary / BITS_PER_UNIT;
5382 /* During reload iteration the amount of registers saved can change.
5383 Recompute the value as needed. Do not recompute when amount of registers
5384 didn't change as reload does multiple calls to the function and does not
5385 expect the decision to change within single iteration. */
5387 && cfun->machine->use_fast_prologue_epilogue_nregs != frame->nregs)
5389 int count = frame->nregs;
5391 cfun->machine->use_fast_prologue_epilogue_nregs = count;
5392 /* The fast prologue uses move instead of push to save registers. This
5393 is significantly longer, but also executes faster as modern hardware
5394 can execute the moves in parallel, but can't do that for push/pop.
5396 Be careful about choosing what prologue to emit: When function takes
5397 many instructions to execute we may use slow version as well as in
5398 case function is known to be outside hot spot (this is known with
5399 feedback only). Weight the size of function by number of registers
5400 to save as it is cheap to use one or two push instructions but very
5401 slow to use many of them. */
5403 count = (count - 1) * FAST_PROLOGUE_INSN_COUNT;
5404 if (cfun->function_frequency < FUNCTION_FREQUENCY_NORMAL
5405 || (flag_branch_probabilities
5406 && cfun->function_frequency < FUNCTION_FREQUENCY_HOT))
5407 cfun->machine->use_fast_prologue_epilogue = false;
5409 cfun->machine->use_fast_prologue_epilogue
5410 = !expensive_function_p (count);
5412 if (TARGET_PROLOGUE_USING_MOVE
5413 && cfun->machine->use_fast_prologue_epilogue)
5414 frame->save_regs_using_mov = true;
5416 frame->save_regs_using_mov = false;
5419 /* Skip return address and saved base pointer. */
5420 offset = frame_pointer_needed ? UNITS_PER_WORD * 2 : UNITS_PER_WORD;
5422 frame->hard_frame_pointer_offset = offset;
5424 /* Do some sanity checking of stack_alignment_needed and
5425 preferred_alignment, since i386 port is the only using those features
5426 that may break easily. */
5428 gcc_assert (!size || stack_alignment_needed);
5429 gcc_assert (preferred_alignment >= STACK_BOUNDARY / BITS_PER_UNIT);
5430 gcc_assert (preferred_alignment <= PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT);
5431 gcc_assert (stack_alignment_needed
5432 <= PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT);
5434 if (stack_alignment_needed < STACK_BOUNDARY / BITS_PER_UNIT)
5435 stack_alignment_needed = STACK_BOUNDARY / BITS_PER_UNIT;
5437 /* Register save area */
5438 offset += frame->nregs * UNITS_PER_WORD;
5441 if (ix86_save_varrargs_registers)
5443 offset += X86_64_VARARGS_SIZE;
5444 frame->va_arg_size = X86_64_VARARGS_SIZE;
5447 frame->va_arg_size = 0;
5449 /* Align start of frame for local function. */
5450 frame->padding1 = ((offset + stack_alignment_needed - 1)
5451 & -stack_alignment_needed) - offset;
5453 offset += frame->padding1;
5455 /* Frame pointer points here. */
5456 frame->frame_pointer_offset = offset;
5460 /* Add outgoing arguments area. Can be skipped if we eliminated
5461 all the function calls as dead code.
5462 Skipping is however impossible when function calls alloca. Alloca
5463 expander assumes that last current_function_outgoing_args_size
5464 of stack frame are unused. */
5465 if (ACCUMULATE_OUTGOING_ARGS
5466 && (!current_function_is_leaf || current_function_calls_alloca
5467 || ix86_current_function_calls_tls_descriptor))
5469 offset += current_function_outgoing_args_size;
5470 frame->outgoing_arguments_size = current_function_outgoing_args_size;
5473 frame->outgoing_arguments_size = 0;
5475 /* Align stack boundary. Only needed if we're calling another function
5477 if (!current_function_is_leaf || current_function_calls_alloca
5478 || ix86_current_function_calls_tls_descriptor)
5479 frame->padding2 = ((offset + preferred_alignment - 1)
5480 & -preferred_alignment) - offset;
5482 frame->padding2 = 0;
5484 offset += frame->padding2;
5486 /* We've reached end of stack frame. */
5487 frame->stack_pointer_offset = offset;
5489 /* Size prologue needs to allocate. */
5490 frame->to_allocate =
5491 (size + frame->padding1 + frame->padding2
5492 + frame->outgoing_arguments_size + frame->va_arg_size);
5494 if ((!frame->to_allocate && frame->nregs <= 1)
5495 || (TARGET_64BIT && frame->to_allocate >= (HOST_WIDE_INT) 0x80000000))
5496 frame->save_regs_using_mov = false;
5498 if (TARGET_RED_ZONE && current_function_sp_is_unchanging
5499 && current_function_is_leaf
5500 && !ix86_current_function_calls_tls_descriptor)
5502 frame->red_zone_size = frame->to_allocate;
5503 if (frame->save_regs_using_mov)
5504 frame->red_zone_size += frame->nregs * UNITS_PER_WORD;
5505 if (frame->red_zone_size > RED_ZONE_SIZE - RED_ZONE_RESERVE)
5506 frame->red_zone_size = RED_ZONE_SIZE - RED_ZONE_RESERVE;
5509 frame->red_zone_size = 0;
5510 frame->to_allocate -= frame->red_zone_size;
5511 frame->stack_pointer_offset -= frame->red_zone_size;
5513 fprintf (stderr, "nregs: %i\n", frame->nregs);
5514 fprintf (stderr, "size: %i\n", size);
5515 fprintf (stderr, "alignment1: %i\n", stack_alignment_needed);
5516 fprintf (stderr, "padding1: %i\n", frame->padding1);
5517 fprintf (stderr, "va_arg: %i\n", frame->va_arg_size);
5518 fprintf (stderr, "padding2: %i\n", frame->padding2);
5519 fprintf (stderr, "to_allocate: %i\n", frame->to_allocate);
5520 fprintf (stderr, "red_zone_size: %i\n", frame->red_zone_size);
5521 fprintf (stderr, "frame_pointer_offset: %i\n", frame->frame_pointer_offset);
5522 fprintf (stderr, "hard_frame_pointer_offset: %i\n",
5523 frame->hard_frame_pointer_offset);
5524 fprintf (stderr, "stack_pointer_offset: %i\n", frame->stack_pointer_offset);
5528 /* Emit code to save registers in the prologue. */
5531 ix86_emit_save_regs (void)
5536 for (regno = FIRST_PSEUDO_REGISTER; regno-- > 0; )
5537 if (ix86_save_reg (regno, true))
5539 insn = emit_insn (gen_push (gen_rtx_REG (Pmode, regno)));
5540 RTX_FRAME_RELATED_P (insn) = 1;
5544 /* Emit code to save registers using MOV insns. First register
5545 is restored from POINTER + OFFSET. */
5547 ix86_emit_save_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
5552 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
5553 if (ix86_save_reg (regno, true))
5555 insn = emit_move_insn (adjust_address (gen_rtx_MEM (Pmode, pointer),
5557 gen_rtx_REG (Pmode, regno));
5558 RTX_FRAME_RELATED_P (insn) = 1;
5559 offset += UNITS_PER_WORD;
5563 /* Expand prologue or epilogue stack adjustment.
5564 The pattern exist to put a dependency on all ebp-based memory accesses.
5565 STYLE should be negative if instructions should be marked as frame related,
5566 zero if %r11 register is live and cannot be freely used and positive
5570 pro_epilogue_adjust_stack (rtx dest, rtx src, rtx offset, int style)
5575 insn = emit_insn (gen_pro_epilogue_adjust_stack_1 (dest, src, offset));
5576 else if (x86_64_immediate_operand (offset, DImode))
5577 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64 (dest, src, offset));
5581 /* r11 is used by indirect sibcall return as well, set before the
5582 epilogue and used after the epilogue. ATM indirect sibcall
5583 shouldn't be used together with huge frame sizes in one
5584 function because of the frame_size check in sibcall.c. */
5586 r11 = gen_rtx_REG (DImode, R11_REG);
5587 insn = emit_insn (gen_rtx_SET (DImode, r11, offset));
5589 RTX_FRAME_RELATED_P (insn) = 1;
5590 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64_2 (dest, src, r11,
5594 RTX_FRAME_RELATED_P (insn) = 1;
5597 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
5600 ix86_internal_arg_pointer (void)
5602 bool has_force_align_arg_pointer =
5603 (0 != lookup_attribute (ix86_force_align_arg_pointer_string,
5604 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))));
5605 if ((FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN
5606 && DECL_NAME (current_function_decl)
5607 && MAIN_NAME_P (DECL_NAME (current_function_decl))
5608 && DECL_FILE_SCOPE_P (current_function_decl))
5609 || ix86_force_align_arg_pointer
5610 || has_force_align_arg_pointer)
5612 /* Nested functions can't realign the stack due to a register
5614 if (DECL_CONTEXT (current_function_decl)
5615 && TREE_CODE (DECL_CONTEXT (current_function_decl)) == FUNCTION_DECL)
5617 if (ix86_force_align_arg_pointer)
5618 warning (0, "-mstackrealign ignored for nested functions");
5619 if (has_force_align_arg_pointer)
5620 error ("%s not supported for nested functions",
5621 ix86_force_align_arg_pointer_string);
5622 return virtual_incoming_args_rtx;
5624 cfun->machine->force_align_arg_pointer = gen_rtx_REG (Pmode, 2);
5625 return copy_to_reg (cfun->machine->force_align_arg_pointer);
5628 return virtual_incoming_args_rtx;
5631 /* Handle the TARGET_DWARF_HANDLE_FRAME_UNSPEC hook.
5632 This is called from dwarf2out.c to emit call frame instructions
5633 for frame-related insns containing UNSPECs and UNSPEC_VOLATILEs. */
5635 ix86_dwarf_handle_frame_unspec (const char *label, rtx pattern, int index)
5637 rtx unspec = SET_SRC (pattern);
5638 gcc_assert (GET_CODE (unspec) == UNSPEC);
5642 case UNSPEC_REG_SAVE:
5643 dwarf2out_reg_save_reg (label, XVECEXP (unspec, 0, 0),
5644 SET_DEST (pattern));
5646 case UNSPEC_DEF_CFA:
5647 dwarf2out_def_cfa (label, REGNO (SET_DEST (pattern)),
5648 INTVAL (XVECEXP (unspec, 0, 0)));
5655 /* Expand the prologue into a bunch of separate insns. */
5658 ix86_expand_prologue (void)
5662 struct ix86_frame frame;
5663 HOST_WIDE_INT allocate;
5665 ix86_compute_frame_layout (&frame);
5667 if (cfun->machine->force_align_arg_pointer)
5671 /* Grab the argument pointer. */
5672 x = plus_constant (stack_pointer_rtx, 4);
5673 y = cfun->machine->force_align_arg_pointer;
5674 insn = emit_insn (gen_rtx_SET (VOIDmode, y, x));
5675 RTX_FRAME_RELATED_P (insn) = 1;
5677 /* The unwind info consists of two parts: install the fafp as the cfa,
5678 and record the fafp as the "save register" of the stack pointer.
5679 The later is there in order that the unwinder can see where it
5680 should restore the stack pointer across the and insn. */
5681 x = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx), UNSPEC_DEF_CFA);
5682 x = gen_rtx_SET (VOIDmode, y, x);
5683 RTX_FRAME_RELATED_P (x) = 1;
5684 y = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, stack_pointer_rtx),
5686 y = gen_rtx_SET (VOIDmode, cfun->machine->force_align_arg_pointer, y);
5687 RTX_FRAME_RELATED_P (y) = 1;
5688 x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x, y));
5689 x = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, x, NULL);
5690 REG_NOTES (insn) = x;
5692 /* Align the stack. */
5693 emit_insn (gen_andsi3 (stack_pointer_rtx, stack_pointer_rtx,
5696 /* And here we cheat like madmen with the unwind info. We force the
5697 cfa register back to sp+4, which is exactly what it was at the
5698 start of the function. Re-pushing the return address results in
5699 the return at the same spot relative to the cfa, and thus is
5700 correct wrt the unwind info. */
5701 x = cfun->machine->force_align_arg_pointer;
5702 x = gen_frame_mem (Pmode, plus_constant (x, -4));
5703 insn = emit_insn (gen_push (x));
5704 RTX_FRAME_RELATED_P (insn) = 1;
5707 x = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, x), UNSPEC_DEF_CFA);
5708 x = gen_rtx_SET (VOIDmode, stack_pointer_rtx, x);
5709 x = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, x, NULL);
5710 REG_NOTES (insn) = x;
5713 /* Note: AT&T enter does NOT have reversed args. Enter is probably
5714 slower on all targets. Also sdb doesn't like it. */
5716 if (frame_pointer_needed)
5718 insn = emit_insn (gen_push (hard_frame_pointer_rtx));
5719 RTX_FRAME_RELATED_P (insn) = 1;
5721 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
5722 RTX_FRAME_RELATED_P (insn) = 1;
5725 allocate = frame.to_allocate;
5727 if (!frame.save_regs_using_mov)
5728 ix86_emit_save_regs ();
5730 allocate += frame.nregs * UNITS_PER_WORD;
5732 /* When using red zone we may start register saving before allocating
5733 the stack frame saving one cycle of the prologue. */
5734 if (TARGET_RED_ZONE && frame.save_regs_using_mov)
5735 ix86_emit_save_regs_using_mov (frame_pointer_needed ? hard_frame_pointer_rtx
5736 : stack_pointer_rtx,
5737 -frame.nregs * UNITS_PER_WORD);
5741 else if (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)
5742 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
5743 GEN_INT (-allocate), -1);
5746 /* Only valid for Win32. */
5747 rtx eax = gen_rtx_REG (SImode, 0);
5748 bool eax_live = ix86_eax_live_at_start_p ();
5751 gcc_assert (!TARGET_64BIT);
5755 emit_insn (gen_push (eax));
5759 emit_move_insn (eax, GEN_INT (allocate));
5761 insn = emit_insn (gen_allocate_stack_worker (eax));
5762 RTX_FRAME_RELATED_P (insn) = 1;
5763 t = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-allocate));
5764 t = gen_rtx_SET (VOIDmode, stack_pointer_rtx, t);
5765 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
5766 t, REG_NOTES (insn));
5770 if (frame_pointer_needed)
5771 t = plus_constant (hard_frame_pointer_rtx,
5774 - frame.nregs * UNITS_PER_WORD);
5776 t = plus_constant (stack_pointer_rtx, allocate);
5777 emit_move_insn (eax, gen_rtx_MEM (SImode, t));
5781 if (frame.save_regs_using_mov && !TARGET_RED_ZONE)
5783 if (!frame_pointer_needed || !frame.to_allocate)
5784 ix86_emit_save_regs_using_mov (stack_pointer_rtx, frame.to_allocate);
5786 ix86_emit_save_regs_using_mov (hard_frame_pointer_rtx,
5787 -frame.nregs * UNITS_PER_WORD);
5790 pic_reg_used = false;
5791 if (pic_offset_table_rtx
5792 && (regs_ever_live[REAL_PIC_OFFSET_TABLE_REGNUM]
5793 || current_function_profile))
5795 unsigned int alt_pic_reg_used = ix86_select_alt_pic_regnum ();
5797 if (alt_pic_reg_used != INVALID_REGNUM)
5798 REGNO (pic_offset_table_rtx) = alt_pic_reg_used;
5800 pic_reg_used = true;
5806 insn = emit_insn (gen_set_got_rex64 (pic_offset_table_rtx));
5808 insn = emit_insn (gen_set_got (pic_offset_table_rtx));
5810 /* Even with accurate pre-reload life analysis, we can wind up
5811 deleting all references to the pic register after reload.
5812 Consider if cross-jumping unifies two sides of a branch
5813 controlled by a comparison vs the only read from a global.
5814 In which case, allow the set_got to be deleted, though we're
5815 too late to do anything about the ebx save in the prologue. */
5816 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, const0_rtx, NULL);
5819 /* Prevent function calls from be scheduled before the call to mcount.
5820 In the pic_reg_used case, make sure that the got load isn't deleted. */
5821 if (current_function_profile)
5822 emit_insn (gen_blockage (pic_reg_used ? pic_offset_table_rtx : const0_rtx));
5825 /* Emit code to restore saved registers using MOV insns. First register
5826 is restored from POINTER + OFFSET. */
5828 ix86_emit_restore_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
5829 int maybe_eh_return)
5832 rtx base_address = gen_rtx_MEM (Pmode, pointer);
5834 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
5835 if (ix86_save_reg (regno, maybe_eh_return))
5837 /* Ensure that adjust_address won't be forced to produce pointer
5838 out of range allowed by x86-64 instruction set. */
5839 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
5843 r11 = gen_rtx_REG (DImode, R11_REG);
5844 emit_move_insn (r11, GEN_INT (offset));
5845 emit_insn (gen_adddi3 (r11, r11, pointer));
5846 base_address = gen_rtx_MEM (Pmode, r11);
5849 emit_move_insn (gen_rtx_REG (Pmode, regno),
5850 adjust_address (base_address, Pmode, offset));
5851 offset += UNITS_PER_WORD;
5855 /* Restore function stack, frame, and registers. */
5858 ix86_expand_epilogue (int style)
5861 int sp_valid = !frame_pointer_needed || current_function_sp_is_unchanging;
5862 struct ix86_frame frame;
5863 HOST_WIDE_INT offset;
5865 ix86_compute_frame_layout (&frame);
5867 /* Calculate start of saved registers relative to ebp. Special care
5868 must be taken for the normal return case of a function using
5869 eh_return: the eax and edx registers are marked as saved, but not
5870 restored along this path. */
5871 offset = frame.nregs;
5872 if (current_function_calls_eh_return && style != 2)
5874 offset *= -UNITS_PER_WORD;
5876 /* If we're only restoring one register and sp is not valid then
5877 using a move instruction to restore the register since it's
5878 less work than reloading sp and popping the register.
5880 The default code result in stack adjustment using add/lea instruction,
5881 while this code results in LEAVE instruction (or discrete equivalent),
5882 so it is profitable in some other cases as well. Especially when there
5883 are no registers to restore. We also use this code when TARGET_USE_LEAVE
5884 and there is exactly one register to pop. This heuristic may need some
5885 tuning in future. */
5886 if ((!sp_valid && frame.nregs <= 1)
5887 || (TARGET_EPILOGUE_USING_MOVE
5888 && cfun->machine->use_fast_prologue_epilogue
5889 && (frame.nregs > 1 || frame.to_allocate))
5890 || (frame_pointer_needed && !frame.nregs && frame.to_allocate)
5891 || (frame_pointer_needed && TARGET_USE_LEAVE
5892 && cfun->machine->use_fast_prologue_epilogue
5893 && frame.nregs == 1)
5894 || current_function_calls_eh_return)
5896 /* Restore registers. We can use ebp or esp to address the memory
5897 locations. If both are available, default to ebp, since offsets
5898 are known to be small. Only exception is esp pointing directly to the
5899 end of block of saved registers, where we may simplify addressing
5902 if (!frame_pointer_needed || (sp_valid && !frame.to_allocate))
5903 ix86_emit_restore_regs_using_mov (stack_pointer_rtx,
5904 frame.to_allocate, style == 2);
5906 ix86_emit_restore_regs_using_mov (hard_frame_pointer_rtx,
5907 offset, style == 2);
5909 /* eh_return epilogues need %ecx added to the stack pointer. */
5912 rtx tmp, sa = EH_RETURN_STACKADJ_RTX;
5914 if (frame_pointer_needed)
5916 tmp = gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx, sa);
5917 tmp = plus_constant (tmp, UNITS_PER_WORD);
5918 emit_insn (gen_rtx_SET (VOIDmode, sa, tmp));
5920 tmp = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
5921 emit_move_insn (hard_frame_pointer_rtx, tmp);
5923 pro_epilogue_adjust_stack (stack_pointer_rtx, sa,
5928 tmp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, sa);
5929 tmp = plus_constant (tmp, (frame.to_allocate
5930 + frame.nregs * UNITS_PER_WORD));
5931 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx, tmp));
5934 else if (!frame_pointer_needed)
5935 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
5936 GEN_INT (frame.to_allocate
5937 + frame.nregs * UNITS_PER_WORD),
5939 /* If not an i386, mov & pop is faster than "leave". */
5940 else if (TARGET_USE_LEAVE || optimize_size
5941 || !cfun->machine->use_fast_prologue_epilogue)
5942 emit_insn (TARGET_64BIT ? gen_leave_rex64 () : gen_leave ());
5945 pro_epilogue_adjust_stack (stack_pointer_rtx,
5946 hard_frame_pointer_rtx,
5949 emit_insn (gen_popdi1 (hard_frame_pointer_rtx));
5951 emit_insn (gen_popsi1 (hard_frame_pointer_rtx));
5956 /* First step is to deallocate the stack frame so that we can
5957 pop the registers. */
5960 gcc_assert (frame_pointer_needed);
5961 pro_epilogue_adjust_stack (stack_pointer_rtx,
5962 hard_frame_pointer_rtx,
5963 GEN_INT (offset), style);
5965 else if (frame.to_allocate)
5966 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
5967 GEN_INT (frame.to_allocate), style);
5969 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
5970 if (ix86_save_reg (regno, false))
5973 emit_insn (gen_popdi1 (gen_rtx_REG (Pmode, regno)));
5975 emit_insn (gen_popsi1 (gen_rtx_REG (Pmode, regno)));
5977 if (frame_pointer_needed)
5979 /* Leave results in shorter dependency chains on CPUs that are
5980 able to grok it fast. */
5981 if (TARGET_USE_LEAVE)
5982 emit_insn (TARGET_64BIT ? gen_leave_rex64 () : gen_leave ());
5983 else if (TARGET_64BIT)
5984 emit_insn (gen_popdi1 (hard_frame_pointer_rtx));
5986 emit_insn (gen_popsi1 (hard_frame_pointer_rtx));
5990 if (cfun->machine->force_align_arg_pointer)
5992 emit_insn (gen_addsi3 (stack_pointer_rtx,
5993 cfun->machine->force_align_arg_pointer,
5997 /* Sibcall epilogues don't want a return instruction. */
6001 if (current_function_pops_args && current_function_args_size)
6003 rtx popc = GEN_INT (current_function_pops_args);
6005 /* i386 can only pop 64K bytes. If asked to pop more, pop
6006 return address, do explicit add, and jump indirectly to the
6009 if (current_function_pops_args >= 65536)
6011 rtx ecx = gen_rtx_REG (SImode, 2);
6013 /* There is no "pascal" calling convention in 64bit ABI. */
6014 gcc_assert (!TARGET_64BIT);
6016 emit_insn (gen_popsi1 (ecx));
6017 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, popc));
6018 emit_jump_insn (gen_return_indirect_internal (ecx));
6021 emit_jump_insn (gen_return_pop_internal (popc));
6024 emit_jump_insn (gen_return_internal ());
6027 /* Reset from the function's potential modifications. */
6030 ix86_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
6031 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6033 if (pic_offset_table_rtx)
6034 REGNO (pic_offset_table_rtx) = REAL_PIC_OFFSET_TABLE_REGNUM;
6036 /* Mach-O doesn't support labels at the end of objects, so if
6037 it looks like we might want one, insert a NOP. */
6039 rtx insn = get_last_insn ();
6042 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL)
6043 insn = PREV_INSN (insn);
6047 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL)))
6048 fputs ("\tnop\n", file);
6054 /* Extract the parts of an RTL expression that is a valid memory address
6055 for an instruction. Return 0 if the structure of the address is
6056 grossly off. Return -1 if the address contains ASHIFT, so it is not
6057 strictly valid, but still used for computing length of lea instruction. */
6060 ix86_decompose_address (rtx addr, struct ix86_address *out)
6062 rtx base = NULL_RTX, index = NULL_RTX, disp = NULL_RTX;
6063 rtx base_reg, index_reg;
6064 HOST_WIDE_INT scale = 1;
6065 rtx scale_rtx = NULL_RTX;
6067 enum ix86_address_seg seg = SEG_DEFAULT;
6069 if (GET_CODE (addr) == REG || GET_CODE (addr) == SUBREG)
6071 else if (GET_CODE (addr) == PLUS)
6081 addends[n++] = XEXP (op, 1);
6084 while (GET_CODE (op) == PLUS);
6089 for (i = n; i >= 0; --i)
6092 switch (GET_CODE (op))
6097 index = XEXP (op, 0);
6098 scale_rtx = XEXP (op, 1);
6102 if (XINT (op, 1) == UNSPEC_TP
6103 && TARGET_TLS_DIRECT_SEG_REFS
6104 && seg == SEG_DEFAULT)
6105 seg = TARGET_64BIT ? SEG_FS : SEG_GS;
6134 else if (GET_CODE (addr) == MULT)
6136 index = XEXP (addr, 0); /* index*scale */
6137 scale_rtx = XEXP (addr, 1);
6139 else if (GET_CODE (addr) == ASHIFT)
6143 /* We're called for lea too, which implements ashift on occasion. */
6144 index = XEXP (addr, 0);
6145 tmp = XEXP (addr, 1);
6146 if (GET_CODE (tmp) != CONST_INT)
6148 scale = INTVAL (tmp);
6149 if ((unsigned HOST_WIDE_INT) scale > 3)
6155 disp = addr; /* displacement */
6157 /* Extract the integral value of scale. */
6160 if (GET_CODE (scale_rtx) != CONST_INT)
6162 scale = INTVAL (scale_rtx);
6165 base_reg = base && GET_CODE (base) == SUBREG ? SUBREG_REG (base) : base;
6166 index_reg = index && GET_CODE (index) == SUBREG ? SUBREG_REG (index) : index;
6168 /* Allow arg pointer and stack pointer as index if there is not scaling. */
6169 if (base_reg && index_reg && scale == 1
6170 && (index_reg == arg_pointer_rtx
6171 || index_reg == frame_pointer_rtx
6172 || (REG_P (index_reg) && REGNO (index_reg) == STACK_POINTER_REGNUM)))
6175 tmp = base, base = index, index = tmp;
6176 tmp = base_reg, base_reg = index_reg, index_reg = tmp;
6179 /* Special case: %ebp cannot be encoded as a base without a displacement. */
6180 if ((base_reg == hard_frame_pointer_rtx
6181 || base_reg == frame_pointer_rtx
6182 || base_reg == arg_pointer_rtx) && !disp)
6185 /* Special case: on K6, [%esi] makes the instruction vector decoded.
6186 Avoid this by transforming to [%esi+0]. */
6187 if (ix86_tune == PROCESSOR_K6 && !optimize_size
6188 && base_reg && !index_reg && !disp
6190 && REGNO_REG_CLASS (REGNO (base_reg)) == SIREG)
6193 /* Special case: encode reg+reg instead of reg*2. */
6194 if (!base && index && scale && scale == 2)
6195 base = index, base_reg = index_reg, scale = 1;
6197 /* Special case: scaling cannot be encoded without base or displacement. */
6198 if (!base && !disp && index && scale != 1)
6210 /* Return cost of the memory address x.
6211 For i386, it is better to use a complex address than let gcc copy
6212 the address into a reg and make a new pseudo. But not if the address
6213 requires to two regs - that would mean more pseudos with longer
6216 ix86_address_cost (rtx x)
6218 struct ix86_address parts;
6220 int ok = ix86_decompose_address (x, &parts);
6224 if (parts.base && GET_CODE (parts.base) == SUBREG)
6225 parts.base = SUBREG_REG (parts.base);
6226 if (parts.index && GET_CODE (parts.index) == SUBREG)
6227 parts.index = SUBREG_REG (parts.index);
6229 /* More complex memory references are better. */
6230 if (parts.disp && parts.disp != const0_rtx)
6232 if (parts.seg != SEG_DEFAULT)
6235 /* Attempt to minimize number of registers in the address. */
6237 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER))
6239 && (!REG_P (parts.index)
6240 || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)))
6244 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER)
6246 && (!REG_P (parts.index) || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)
6247 && parts.base != parts.index)
6250 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
6251 since it's predecode logic can't detect the length of instructions
6252 and it degenerates to vector decoded. Increase cost of such
6253 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
6254 to split such addresses or even refuse such addresses at all.
6256 Following addressing modes are affected:
6261 The first and last case may be avoidable by explicitly coding the zero in
6262 memory address, but I don't have AMD-K6 machine handy to check this
6266 && ((!parts.disp && parts.base && parts.index && parts.scale != 1)
6267 || (parts.disp && !parts.base && parts.index && parts.scale != 1)
6268 || (!parts.disp && parts.base && parts.index && parts.scale == 1)))
6274 /* If X is a machine specific address (i.e. a symbol or label being
6275 referenced as a displacement from the GOT implemented using an
6276 UNSPEC), then return the base term. Otherwise return X. */
6279 ix86_find_base_term (rtx x)
6285 if (GET_CODE (x) != CONST)
6288 if (GET_CODE (term) == PLUS
6289 && (GET_CODE (XEXP (term, 1)) == CONST_INT
6290 || GET_CODE (XEXP (term, 1)) == CONST_DOUBLE))
6291 term = XEXP (term, 0);
6292 if (GET_CODE (term) != UNSPEC
6293 || XINT (term, 1) != UNSPEC_GOTPCREL)
6296 term = XVECEXP (term, 0, 0);
6298 if (GET_CODE (term) != SYMBOL_REF
6299 && GET_CODE (term) != LABEL_REF)
6305 term = ix86_delegitimize_address (x);
6307 if (GET_CODE (term) != SYMBOL_REF
6308 && GET_CODE (term) != LABEL_REF)
6314 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
6315 this is used for to form addresses to local data when -fPIC is in
6319 darwin_local_data_pic (rtx disp)
6321 if (GET_CODE (disp) == MINUS)
6323 if (GET_CODE (XEXP (disp, 0)) == LABEL_REF
6324 || GET_CODE (XEXP (disp, 0)) == SYMBOL_REF)
6325 if (GET_CODE (XEXP (disp, 1)) == SYMBOL_REF)
6327 const char *sym_name = XSTR (XEXP (disp, 1), 0);
6328 if (! strcmp (sym_name, "<pic base>"))
6336 /* Determine if a given RTX is a valid constant. We already know this
6337 satisfies CONSTANT_P. */
6340 legitimate_constant_p (rtx x)
6342 switch (GET_CODE (x))
6347 if (GET_CODE (x) == PLUS)
6349 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6354 if (TARGET_MACHO && darwin_local_data_pic (x))
6357 /* Only some unspecs are valid as "constants". */
6358 if (GET_CODE (x) == UNSPEC)
6359 switch (XINT (x, 1))
6362 return TARGET_64BIT;
6365 x = XVECEXP (x, 0, 0);
6366 return (GET_CODE (x) == SYMBOL_REF
6367 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
6369 x = XVECEXP (x, 0, 0);
6370 return (GET_CODE (x) == SYMBOL_REF
6371 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC);
6376 /* We must have drilled down to a symbol. */
6377 if (GET_CODE (x) == LABEL_REF)
6379 if (GET_CODE (x) != SYMBOL_REF)
6384 /* TLS symbols are never valid. */
6385 if (SYMBOL_REF_TLS_MODEL (x))
6390 if (GET_MODE (x) == TImode
6391 && x != CONST0_RTX (TImode)
6397 if (x == CONST0_RTX (GET_MODE (x)))
6405 /* Otherwise we handle everything else in the move patterns. */
6409 /* Determine if it's legal to put X into the constant pool. This
6410 is not possible for the address of thread-local symbols, which
6411 is checked above. */
6414 ix86_cannot_force_const_mem (rtx x)
6416 /* We can always put integral constants and vectors in memory. */
6417 switch (GET_CODE (x))
6427 return !legitimate_constant_p (x);
6430 /* Determine if a given RTX is a valid constant address. */
6433 constant_address_p (rtx x)
6435 return CONSTANT_P (x) && legitimate_address_p (Pmode, x, 1);
6438 /* Nonzero if the constant value X is a legitimate general operand
6439 when generating PIC code. It is given that flag_pic is on and
6440 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
6443 legitimate_pic_operand_p (rtx x)
6447 switch (GET_CODE (x))
6450 inner = XEXP (x, 0);
6451 if (GET_CODE (inner) == PLUS
6452 && GET_CODE (XEXP (inner, 1)) == CONST_INT)
6453 inner = XEXP (inner, 0);
6455 /* Only some unspecs are valid as "constants". */
6456 if (GET_CODE (inner) == UNSPEC)
6457 switch (XINT (inner, 1))
6460 return TARGET_64BIT;
6462 x = XVECEXP (inner, 0, 0);
6463 return (GET_CODE (x) == SYMBOL_REF
6464 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
6472 return legitimate_pic_address_disp_p (x);
6479 /* Determine if a given CONST RTX is a valid memory displacement
6483 legitimate_pic_address_disp_p (rtx disp)
6487 /* In 64bit mode we can allow direct addresses of symbols and labels
6488 when they are not dynamic symbols. */
6491 rtx op0 = disp, op1;
6493 switch (GET_CODE (disp))
6499 if (GET_CODE (XEXP (disp, 0)) != PLUS)
6501 op0 = XEXP (XEXP (disp, 0), 0);
6502 op1 = XEXP (XEXP (disp, 0), 1);
6503 if (GET_CODE (op1) != CONST_INT
6504 || INTVAL (op1) >= 16*1024*1024
6505 || INTVAL (op1) < -16*1024*1024)
6507 if (GET_CODE (op0) == LABEL_REF)
6509 if (GET_CODE (op0) != SYMBOL_REF)
6514 /* TLS references should always be enclosed in UNSPEC. */
6515 if (SYMBOL_REF_TLS_MODEL (op0))
6517 if (!SYMBOL_REF_FAR_ADDR_P (op0) && SYMBOL_REF_LOCAL_P (op0))
6525 if (GET_CODE (disp) != CONST)
6527 disp = XEXP (disp, 0);
6531 /* We are unsafe to allow PLUS expressions. This limit allowed distance
6532 of GOT tables. We should not need these anyway. */
6533 if (GET_CODE (disp) != UNSPEC
6534 || (XINT (disp, 1) != UNSPEC_GOTPCREL
6535 && XINT (disp, 1) != UNSPEC_GOTOFF))
6538 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
6539 && GET_CODE (XVECEXP (disp, 0, 0)) != LABEL_REF)
6545 if (GET_CODE (disp) == PLUS)
6547 if (GET_CODE (XEXP (disp, 1)) != CONST_INT)
6549 disp = XEXP (disp, 0);
6553 if (TARGET_MACHO && darwin_local_data_pic (disp))
6556 if (GET_CODE (disp) != UNSPEC)
6559 switch (XINT (disp, 1))
6564 return GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF;
6566 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
6567 While ABI specify also 32bit relocation but we don't produce it in
6568 small PIC model at all. */
6569 if ((GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
6570 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF)
6572 return local_symbolic_operand (XVECEXP (disp, 0, 0), Pmode);
6574 case UNSPEC_GOTTPOFF:
6575 case UNSPEC_GOTNTPOFF:
6576 case UNSPEC_INDNTPOFF:
6579 disp = XVECEXP (disp, 0, 0);
6580 return (GET_CODE (disp) == SYMBOL_REF
6581 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_INITIAL_EXEC);
6583 disp = XVECEXP (disp, 0, 0);
6584 return (GET_CODE (disp) == SYMBOL_REF
6585 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_EXEC);
6587 disp = XVECEXP (disp, 0, 0);
6588 return (GET_CODE (disp) == SYMBOL_REF
6589 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_DYNAMIC);
6595 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid
6596 memory address for an instruction. The MODE argument is the machine mode
6597 for the MEM expression that wants to use this address.
6599 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
6600 convert common non-canonical forms to canonical form so that they will
6604 legitimate_address_p (enum machine_mode mode, rtx addr, int strict)
6606 struct ix86_address parts;
6607 rtx base, index, disp;
6608 HOST_WIDE_INT scale;
6609 const char *reason = NULL;
6610 rtx reason_rtx = NULL_RTX;
6612 if (TARGET_DEBUG_ADDR)
6615 "\n======\nGO_IF_LEGITIMATE_ADDRESS, mode = %s, strict = %d\n",
6616 GET_MODE_NAME (mode), strict);
6620 if (ix86_decompose_address (addr, &parts) <= 0)
6622 reason = "decomposition failed";
6627 index = parts.index;
6629 scale = parts.scale;
6631 /* Validate base register.
6633 Don't allow SUBREG's that span more than a word here. It can lead to spill
6634 failures when the base is one word out of a two word structure, which is
6635 represented internally as a DImode int. */
6644 else if (GET_CODE (base) == SUBREG
6645 && REG_P (SUBREG_REG (base))
6646 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (base)))
6648 reg = SUBREG_REG (base);
6651 reason = "base is not a register";
6655 if (GET_MODE (base) != Pmode)
6657 reason = "base is not in Pmode";
6661 if ((strict && ! REG_OK_FOR_BASE_STRICT_P (reg))
6662 || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (reg)))
6664 reason = "base is not valid";
6669 /* Validate index register.
6671 Don't allow SUBREG's that span more than a word here -- same as above. */
6680 else if (GET_CODE (index) == SUBREG
6681 && REG_P (SUBREG_REG (index))
6682 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (index)))
6684 reg = SUBREG_REG (index);
6687 reason = "index is not a register";
6691 if (GET_MODE (index) != Pmode)
6693 reason = "index is not in Pmode";
6697 if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (reg))
6698 || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (reg)))
6700 reason = "index is not valid";
6705 /* Validate scale factor. */
6708 reason_rtx = GEN_INT (scale);
6711 reason = "scale without index";
6715 if (scale != 2 && scale != 4 && scale != 8)
6717 reason = "scale is not a valid multiplier";
6722 /* Validate displacement. */
6727 if (GET_CODE (disp) == CONST
6728 && GET_CODE (XEXP (disp, 0)) == UNSPEC)
6729 switch (XINT (XEXP (disp, 0), 1))
6731 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
6732 used. While ABI specify also 32bit relocations, we don't produce
6733 them at all and use IP relative instead. */
6736 gcc_assert (flag_pic);
6738 goto is_legitimate_pic;
6739 reason = "64bit address unspec";
6742 case UNSPEC_GOTPCREL:
6743 gcc_assert (flag_pic);
6744 goto is_legitimate_pic;
6746 case UNSPEC_GOTTPOFF:
6747 case UNSPEC_GOTNTPOFF:
6748 case UNSPEC_INDNTPOFF:
6754 reason = "invalid address unspec";
6758 else if (SYMBOLIC_CONST (disp)
6762 && MACHOPIC_INDIRECT
6763 && !machopic_operand_p (disp)
6769 if (TARGET_64BIT && (index || base))
6771 /* foo@dtpoff(%rX) is ok. */
6772 if (GET_CODE (disp) != CONST
6773 || GET_CODE (XEXP (disp, 0)) != PLUS
6774 || GET_CODE (XEXP (XEXP (disp, 0), 0)) != UNSPEC
6775 || GET_CODE (XEXP (XEXP (disp, 0), 1)) != CONST_INT
6776 || (XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_DTPOFF
6777 && XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_NTPOFF))
6779 reason = "non-constant pic memory reference";
6783 else if (! legitimate_pic_address_disp_p (disp))
6785 reason = "displacement is an invalid pic construct";
6789 /* This code used to verify that a symbolic pic displacement
6790 includes the pic_offset_table_rtx register.
6792 While this is good idea, unfortunately these constructs may
6793 be created by "adds using lea" optimization for incorrect
6802 This code is nonsensical, but results in addressing
6803 GOT table with pic_offset_table_rtx base. We can't
6804 just refuse it easily, since it gets matched by
6805 "addsi3" pattern, that later gets split to lea in the
6806 case output register differs from input. While this
6807 can be handled by separate addsi pattern for this case
6808 that never results in lea, this seems to be easier and
6809 correct fix for crash to disable this test. */
6811 else if (GET_CODE (disp) != LABEL_REF
6812 && GET_CODE (disp) != CONST_INT
6813 && (GET_CODE (disp) != CONST
6814 || !legitimate_constant_p (disp))
6815 && (GET_CODE (disp) != SYMBOL_REF
6816 || !legitimate_constant_p (disp)))
6818 reason = "displacement is not constant";
6821 else if (TARGET_64BIT
6822 && !x86_64_immediate_operand (disp, VOIDmode))
6824 reason = "displacement is out of range";
6829 /* Everything looks valid. */
6830 if (TARGET_DEBUG_ADDR)
6831 fprintf (stderr, "Success.\n");
6835 if (TARGET_DEBUG_ADDR)
6837 fprintf (stderr, "Error: %s\n", reason);
6838 debug_rtx (reason_rtx);
6843 /* Return a unique alias set for the GOT. */
6845 static HOST_WIDE_INT
6846 ix86_GOT_alias_set (void)
6848 static HOST_WIDE_INT set = -1;
6850 set = new_alias_set ();
6854 /* Return a legitimate reference for ORIG (an address) using the
6855 register REG. If REG is 0, a new pseudo is generated.
6857 There are two types of references that must be handled:
6859 1. Global data references must load the address from the GOT, via
6860 the PIC reg. An insn is emitted to do this load, and the reg is
6863 2. Static data references, constant pool addresses, and code labels
6864 compute the address as an offset from the GOT, whose base is in
6865 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
6866 differentiate them from global data objects. The returned
6867 address is the PIC reg + an unspec constant.
6869 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
6870 reg also appears in the address. */
6873 legitimize_pic_address (rtx orig, rtx reg)
6880 if (TARGET_MACHO && !TARGET_64BIT)
6883 reg = gen_reg_rtx (Pmode);
6884 /* Use the generic Mach-O PIC machinery. */
6885 return machopic_legitimize_pic_address (orig, GET_MODE (orig), reg);
6889 if (TARGET_64BIT && legitimate_pic_address_disp_p (addr))
6891 else if (TARGET_64BIT
6892 && ix86_cmodel != CM_SMALL_PIC
6893 && local_symbolic_operand (addr, Pmode))
6896 /* This symbol may be referenced via a displacement from the PIC
6897 base address (@GOTOFF). */
6899 if (reload_in_progress)
6900 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
6901 if (GET_CODE (addr) == CONST)
6902 addr = XEXP (addr, 0);
6903 if (GET_CODE (addr) == PLUS)
6905 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)), UNSPEC_GOTOFF);
6906 new = gen_rtx_PLUS (Pmode, new, XEXP (addr, 1));
6909 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
6910 new = gen_rtx_CONST (Pmode, new);
6912 tmpreg = gen_reg_rtx (Pmode);
6915 emit_move_insn (tmpreg, new);
6919 new = expand_simple_binop (Pmode, PLUS, reg, pic_offset_table_rtx,
6920 tmpreg, 1, OPTAB_DIRECT);
6923 else new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, tmpreg);
6925 else if (!TARGET_64BIT && local_symbolic_operand (addr, Pmode))
6927 /* This symbol may be referenced via a displacement from the PIC
6928 base address (@GOTOFF). */
6930 if (reload_in_progress)
6931 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
6932 if (GET_CODE (addr) == CONST)
6933 addr = XEXP (addr, 0);
6934 if (GET_CODE (addr) == PLUS)
6936 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)), UNSPEC_GOTOFF);
6937 new = gen_rtx_PLUS (Pmode, new, XEXP (addr, 1));
6940 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
6941 new = gen_rtx_CONST (Pmode, new);
6942 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
6946 emit_move_insn (reg, new);
6950 else if (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (addr) == 0)
6954 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTPCREL);
6955 new = gen_rtx_CONST (Pmode, new);
6956 new = gen_const_mem (Pmode, new);
6957 set_mem_alias_set (new, ix86_GOT_alias_set ());
6960 reg = gen_reg_rtx (Pmode);
6961 /* Use directly gen_movsi, otherwise the address is loaded
6962 into register for CSE. We don't want to CSE this addresses,
6963 instead we CSE addresses from the GOT table, so skip this. */
6964 emit_insn (gen_movsi (reg, new));
6969 /* This symbol must be referenced via a load from the
6970 Global Offset Table (@GOT). */
6972 if (reload_in_progress)
6973 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
6974 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
6975 new = gen_rtx_CONST (Pmode, new);
6976 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
6977 new = gen_const_mem (Pmode, new);
6978 set_mem_alias_set (new, ix86_GOT_alias_set ());
6981 reg = gen_reg_rtx (Pmode);
6982 emit_move_insn (reg, new);
6988 if (GET_CODE (addr) == CONST_INT
6989 && !x86_64_immediate_operand (addr, VOIDmode))
6993 emit_move_insn (reg, addr);
6997 new = force_reg (Pmode, addr);
6999 else if (GET_CODE (addr) == CONST)
7001 addr = XEXP (addr, 0);
7003 /* We must match stuff we generate before. Assume the only
7004 unspecs that can get here are ours. Not that we could do
7005 anything with them anyway.... */
7006 if (GET_CODE (addr) == UNSPEC
7007 || (GET_CODE (addr) == PLUS
7008 && GET_CODE (XEXP (addr, 0)) == UNSPEC))
7010 gcc_assert (GET_CODE (addr) == PLUS);
7012 if (GET_CODE (addr) == PLUS)
7014 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
7016 /* Check first to see if this is a constant offset from a @GOTOFF
7017 symbol reference. */
7018 if (local_symbolic_operand (op0, Pmode)
7019 && GET_CODE (op1) == CONST_INT)
7023 if (reload_in_progress)
7024 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
7025 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
7027 new = gen_rtx_PLUS (Pmode, new, op1);
7028 new = gen_rtx_CONST (Pmode, new);
7029 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
7033 emit_move_insn (reg, new);
7039 if (INTVAL (op1) < -16*1024*1024
7040 || INTVAL (op1) >= 16*1024*1024)
7042 if (!x86_64_immediate_operand (op1, Pmode))
7043 op1 = force_reg (Pmode, op1);
7044 new = gen_rtx_PLUS (Pmode, force_reg (Pmode, op0), op1);
7050 base = legitimize_pic_address (XEXP (addr, 0), reg);
7051 new = legitimize_pic_address (XEXP (addr, 1),
7052 base == reg ? NULL_RTX : reg);
7054 if (GET_CODE (new) == CONST_INT)
7055 new = plus_constant (base, INTVAL (new));
7058 if (GET_CODE (new) == PLUS && CONSTANT_P (XEXP (new, 1)))
7060 base = gen_rtx_PLUS (Pmode, base, XEXP (new, 0));
7061 new = XEXP (new, 1);
7063 new = gen_rtx_PLUS (Pmode, base, new);
7071 /* Load the thread pointer. If TO_REG is true, force it into a register. */
7074 get_thread_pointer (int to_reg)
7078 tp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TP);
7082 reg = gen_reg_rtx (Pmode);
7083 insn = gen_rtx_SET (VOIDmode, reg, tp);
7084 insn = emit_insn (insn);
7089 /* A subroutine of legitimize_address and ix86_expand_move. FOR_MOV is
7090 false if we expect this to be used for a memory address and true if
7091 we expect to load the address into a register. */
7094 legitimize_tls_address (rtx x, enum tls_model model, int for_mov)
7096 rtx dest, base, off, pic, tp;
7101 case TLS_MODEL_GLOBAL_DYNAMIC:
7102 dest = gen_reg_rtx (Pmode);
7103 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
7105 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
7107 rtx rax = gen_rtx_REG (Pmode, 0), insns;
7110 emit_call_insn (gen_tls_global_dynamic_64 (rax, x));
7111 insns = get_insns ();
7114 emit_libcall_block (insns, dest, rax, x);
7116 else if (TARGET_64BIT && TARGET_GNU2_TLS)
7117 emit_insn (gen_tls_global_dynamic_64 (dest, x));
7119 emit_insn (gen_tls_global_dynamic_32 (dest, x));
7121 if (TARGET_GNU2_TLS)
7123 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tp, dest));
7125 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
7129 case TLS_MODEL_LOCAL_DYNAMIC:
7130 base = gen_reg_rtx (Pmode);
7131 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
7133 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
7135 rtx rax = gen_rtx_REG (Pmode, 0), insns, note;
7138 emit_call_insn (gen_tls_local_dynamic_base_64 (rax));
7139 insns = get_insns ();
7142 note = gen_rtx_EXPR_LIST (VOIDmode, const0_rtx, NULL);
7143 note = gen_rtx_EXPR_LIST (VOIDmode, ix86_tls_get_addr (), note);
7144 emit_libcall_block (insns, base, rax, note);
7146 else if (TARGET_64BIT && TARGET_GNU2_TLS)
7147 emit_insn (gen_tls_local_dynamic_base_64 (base));
7149 emit_insn (gen_tls_local_dynamic_base_32 (base));
7151 if (TARGET_GNU2_TLS)
7153 rtx x = ix86_tls_module_base ();
7155 set_unique_reg_note (get_last_insn (), REG_EQUIV,
7156 gen_rtx_MINUS (Pmode, x, tp));
7159 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPOFF);
7160 off = gen_rtx_CONST (Pmode, off);
7162 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, off));
7164 if (TARGET_GNU2_TLS)
7166 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, dest, tp));
7168 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
7173 case TLS_MODEL_INITIAL_EXEC:
7177 type = UNSPEC_GOTNTPOFF;
7181 if (reload_in_progress)
7182 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
7183 pic = pic_offset_table_rtx;
7184 type = TARGET_ANY_GNU_TLS ? UNSPEC_GOTNTPOFF : UNSPEC_GOTTPOFF;
7186 else if (!TARGET_ANY_GNU_TLS)
7188 pic = gen_reg_rtx (Pmode);
7189 emit_insn (gen_set_got (pic));
7190 type = UNSPEC_GOTTPOFF;
7195 type = UNSPEC_INDNTPOFF;
7198 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), type);
7199 off = gen_rtx_CONST (Pmode, off);
7201 off = gen_rtx_PLUS (Pmode, pic, off);
7202 off = gen_const_mem (Pmode, off);
7203 set_mem_alias_set (off, ix86_GOT_alias_set ());
7205 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
7207 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
7208 off = force_reg (Pmode, off);
7209 return gen_rtx_PLUS (Pmode, base, off);
7213 base = get_thread_pointer (true);
7214 dest = gen_reg_rtx (Pmode);
7215 emit_insn (gen_subsi3 (dest, base, off));
7219 case TLS_MODEL_LOCAL_EXEC:
7220 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x),
7221 (TARGET_64BIT || TARGET_ANY_GNU_TLS)
7222 ? UNSPEC_NTPOFF : UNSPEC_TPOFF);
7223 off = gen_rtx_CONST (Pmode, off);
7225 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
7227 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
7228 return gen_rtx_PLUS (Pmode, base, off);
7232 base = get_thread_pointer (true);
7233 dest = gen_reg_rtx (Pmode);
7234 emit_insn (gen_subsi3 (dest, base, off));
7245 /* Try machine-dependent ways of modifying an illegitimate address
7246 to be legitimate. If we find one, return the new, valid address.
7247 This macro is used in only one place: `memory_address' in explow.c.
7249 OLDX is the address as it was before break_out_memory_refs was called.
7250 In some cases it is useful to look at this to decide what needs to be done.
7252 MODE and WIN are passed so that this macro can use
7253 GO_IF_LEGITIMATE_ADDRESS.
7255 It is always safe for this macro to do nothing. It exists to recognize
7256 opportunities to optimize the output.
7258 For the 80386, we handle X+REG by loading X into a register R and
7259 using R+REG. R will go in a general reg and indexing will be used.
7260 However, if REG is a broken-out memory address or multiplication,
7261 nothing needs to be done because REG can certainly go in a general reg.
7263 When -fpic is used, special handling is needed for symbolic references.
7264 See comments by legitimize_pic_address in i386.c for details. */
7267 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
7272 if (TARGET_DEBUG_ADDR)
7274 fprintf (stderr, "\n==========\nLEGITIMIZE_ADDRESS, mode = %s\n",
7275 GET_MODE_NAME (mode));
7279 log = GET_CODE (x) == SYMBOL_REF ? SYMBOL_REF_TLS_MODEL (x) : 0;
7281 return legitimize_tls_address (x, log, false);
7282 if (GET_CODE (x) == CONST
7283 && GET_CODE (XEXP (x, 0)) == PLUS
7284 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
7285 && (log = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0))))
7287 rtx t = legitimize_tls_address (XEXP (XEXP (x, 0), 0), log, false);
7288 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
7291 if (flag_pic && SYMBOLIC_CONST (x))
7292 return legitimize_pic_address (x, 0);
7294 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
7295 if (GET_CODE (x) == ASHIFT
7296 && GET_CODE (XEXP (x, 1)) == CONST_INT
7297 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) < 4)
7300 log = INTVAL (XEXP (x, 1));
7301 x = gen_rtx_MULT (Pmode, force_reg (Pmode, XEXP (x, 0)),
7302 GEN_INT (1 << log));
7305 if (GET_CODE (x) == PLUS)
7307 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
7309 if (GET_CODE (XEXP (x, 0)) == ASHIFT
7310 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7311 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 0), 1)) < 4)
7314 log = INTVAL (XEXP (XEXP (x, 0), 1));
7315 XEXP (x, 0) = gen_rtx_MULT (Pmode,
7316 force_reg (Pmode, XEXP (XEXP (x, 0), 0)),
7317 GEN_INT (1 << log));
7320 if (GET_CODE (XEXP (x, 1)) == ASHIFT
7321 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
7322 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 1), 1)) < 4)
7325 log = INTVAL (XEXP (XEXP (x, 1), 1));
7326 XEXP (x, 1) = gen_rtx_MULT (Pmode,
7327 force_reg (Pmode, XEXP (XEXP (x, 1), 0)),
7328 GEN_INT (1 << log));
7331 /* Put multiply first if it isn't already. */
7332 if (GET_CODE (XEXP (x, 1)) == MULT)
7334 rtx tmp = XEXP (x, 0);
7335 XEXP (x, 0) = XEXP (x, 1);
7340 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
7341 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
7342 created by virtual register instantiation, register elimination, and
7343 similar optimizations. */
7344 if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS)
7347 x = gen_rtx_PLUS (Pmode,
7348 gen_rtx_PLUS (Pmode, XEXP (x, 0),
7349 XEXP (XEXP (x, 1), 0)),
7350 XEXP (XEXP (x, 1), 1));
7354 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
7355 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
7356 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
7357 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
7358 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
7359 && CONSTANT_P (XEXP (x, 1)))
7362 rtx other = NULL_RTX;
7364 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
7366 constant = XEXP (x, 1);
7367 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
7369 else if (GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 1)) == CONST_INT)
7371 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
7372 other = XEXP (x, 1);
7380 x = gen_rtx_PLUS (Pmode,
7381 gen_rtx_PLUS (Pmode, XEXP (XEXP (x, 0), 0),
7382 XEXP (XEXP (XEXP (x, 0), 1), 0)),
7383 plus_constant (other, INTVAL (constant)));
7387 if (changed && legitimate_address_p (mode, x, FALSE))
7390 if (GET_CODE (XEXP (x, 0)) == MULT)
7393 XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
7396 if (GET_CODE (XEXP (x, 1)) == MULT)
7399 XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
7403 && GET_CODE (XEXP (x, 1)) == REG
7404 && GET_CODE (XEXP (x, 0)) == REG)
7407 if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1)))
7410 x = legitimize_pic_address (x, 0);
7413 if (changed && legitimate_address_p (mode, x, FALSE))
7416 if (GET_CODE (XEXP (x, 0)) == REG)
7418 rtx temp = gen_reg_rtx (Pmode);
7419 rtx val = force_operand (XEXP (x, 1), temp);
7421 emit_move_insn (temp, val);
7427 else if (GET_CODE (XEXP (x, 1)) == REG)
7429 rtx temp = gen_reg_rtx (Pmode);
7430 rtx val = force_operand (XEXP (x, 0), temp);
7432 emit_move_insn (temp, val);
7442 /* Print an integer constant expression in assembler syntax. Addition
7443 and subtraction are the only arithmetic that may appear in these
7444 expressions. FILE is the stdio stream to write to, X is the rtx, and
7445 CODE is the operand print code from the output string. */
7448 output_pic_addr_const (FILE *file, rtx x, int code)
7452 switch (GET_CODE (x))
7455 gcc_assert (flag_pic);
7460 output_addr_const (file, x);
7461 if (!TARGET_MACHO && code == 'P' && ! SYMBOL_REF_LOCAL_P (x))
7462 fputs ("@PLT", file);
7469 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
7470 assemble_name (asm_out_file, buf);
7474 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
7478 /* This used to output parentheses around the expression,
7479 but that does not work on the 386 (either ATT or BSD assembler). */
7480 output_pic_addr_const (file, XEXP (x, 0), code);
7484 if (GET_MODE (x) == VOIDmode)
7486 /* We can use %d if the number is <32 bits and positive. */
7487 if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
7488 fprintf (file, "0x%lx%08lx",
7489 (unsigned long) CONST_DOUBLE_HIGH (x),
7490 (unsigned long) CONST_DOUBLE_LOW (x));
7492 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x));
7495 /* We can't handle floating point constants;
7496 PRINT_OPERAND must handle them. */
7497 output_operand_lossage ("floating constant misused");
7501 /* Some assemblers need integer constants to appear first. */
7502 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
7504 output_pic_addr_const (file, XEXP (x, 0), code);
7506 output_pic_addr_const (file, XEXP (x, 1), code);
7510 gcc_assert (GET_CODE (XEXP (x, 1)) == CONST_INT);
7511 output_pic_addr_const (file, XEXP (x, 1), code);
7513 output_pic_addr_const (file, XEXP (x, 0), code);
7519 putc (ASSEMBLER_DIALECT == ASM_INTEL ? '(' : '[', file);
7520 output_pic_addr_const (file, XEXP (x, 0), code);
7522 output_pic_addr_const (file, XEXP (x, 1), code);
7524 putc (ASSEMBLER_DIALECT == ASM_INTEL ? ')' : ']', file);
7528 gcc_assert (XVECLEN (x, 0) == 1);
7529 output_pic_addr_const (file, XVECEXP (x, 0, 0), code);
7530 switch (XINT (x, 1))
7533 fputs ("@GOT", file);
7536 fputs ("@GOTOFF", file);
7538 case UNSPEC_GOTPCREL:
7539 fputs ("@GOTPCREL(%rip)", file);
7541 case UNSPEC_GOTTPOFF:
7542 /* FIXME: This might be @TPOFF in Sun ld too. */
7543 fputs ("@GOTTPOFF", file);
7546 fputs ("@TPOFF", file);
7550 fputs ("@TPOFF", file);
7552 fputs ("@NTPOFF", file);
7555 fputs ("@DTPOFF", file);
7557 case UNSPEC_GOTNTPOFF:
7559 fputs ("@GOTTPOFF(%rip)", file);
7561 fputs ("@GOTNTPOFF", file);
7563 case UNSPEC_INDNTPOFF:
7564 fputs ("@INDNTPOFF", file);
7567 output_operand_lossage ("invalid UNSPEC as operand");
7573 output_operand_lossage ("invalid expression as operand");
7577 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
7578 We need to emit DTP-relative relocations. */
7581 i386_output_dwarf_dtprel (FILE *file, int size, rtx x)
7583 fputs (ASM_LONG, file);
7584 output_addr_const (file, x);
7585 fputs ("@DTPOFF", file);
7591 fputs (", 0", file);
7598 /* In the name of slightly smaller debug output, and to cater to
7599 general assembler lossage, recognize PIC+GOTOFF and turn it back
7600 into a direct symbol reference.
7602 On Darwin, this is necessary to avoid a crash, because Darwin
7603 has a different PIC label for each routine but the DWARF debugging
7604 information is not associated with any particular routine, so it's
7605 necessary to remove references to the PIC label from RTL stored by
7606 the DWARF output code. */
7609 ix86_delegitimize_address (rtx orig_x)
7612 /* reg_addend is NULL or a multiple of some register. */
7613 rtx reg_addend = NULL_RTX;
7614 /* const_addend is NULL or a const_int. */
7615 rtx const_addend = NULL_RTX;
7616 /* This is the result, or NULL. */
7617 rtx result = NULL_RTX;
7619 if (GET_CODE (x) == MEM)
7624 if (GET_CODE (x) != CONST
7625 || GET_CODE (XEXP (x, 0)) != UNSPEC
7626 || XINT (XEXP (x, 0), 1) != UNSPEC_GOTPCREL
7627 || GET_CODE (orig_x) != MEM)
7629 return XVECEXP (XEXP (x, 0), 0, 0);
7632 if (GET_CODE (x) != PLUS
7633 || GET_CODE (XEXP (x, 1)) != CONST)
7636 if (GET_CODE (XEXP (x, 0)) == REG
7637 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
7638 /* %ebx + GOT/GOTOFF */
7640 else if (GET_CODE (XEXP (x, 0)) == PLUS)
7642 /* %ebx + %reg * scale + GOT/GOTOFF */
7643 reg_addend = XEXP (x, 0);
7644 if (GET_CODE (XEXP (reg_addend, 0)) == REG
7645 && REGNO (XEXP (reg_addend, 0)) == PIC_OFFSET_TABLE_REGNUM)
7646 reg_addend = XEXP (reg_addend, 1);
7647 else if (GET_CODE (XEXP (reg_addend, 1)) == REG
7648 && REGNO (XEXP (reg_addend, 1)) == PIC_OFFSET_TABLE_REGNUM)
7649 reg_addend = XEXP (reg_addend, 0);
7652 if (GET_CODE (reg_addend) != REG
7653 && GET_CODE (reg_addend) != MULT
7654 && GET_CODE (reg_addend) != ASHIFT)
7660 x = XEXP (XEXP (x, 1), 0);
7661 if (GET_CODE (x) == PLUS
7662 && GET_CODE (XEXP (x, 1)) == CONST_INT)
7664 const_addend = XEXP (x, 1);
7668 if (GET_CODE (x) == UNSPEC
7669 && ((XINT (x, 1) == UNSPEC_GOT && GET_CODE (orig_x) == MEM)
7670 || (XINT (x, 1) == UNSPEC_GOTOFF && GET_CODE (orig_x) != MEM)))
7671 result = XVECEXP (x, 0, 0);
7673 if (TARGET_MACHO && darwin_local_data_pic (x)
7674 && GET_CODE (orig_x) != MEM)
7675 result = XEXP (x, 0);
7681 result = gen_rtx_PLUS (Pmode, result, const_addend);
7683 result = gen_rtx_PLUS (Pmode, reg_addend, result);
7688 put_condition_code (enum rtx_code code, enum machine_mode mode, int reverse,
7693 if (mode == CCFPmode || mode == CCFPUmode)
7695 enum rtx_code second_code, bypass_code;
7696 ix86_fp_comparison_codes (code, &bypass_code, &code, &second_code);
7697 gcc_assert (bypass_code == UNKNOWN && second_code == UNKNOWN);
7698 code = ix86_fp_compare_code_to_integer (code);
7702 code = reverse_condition (code);
7713 gcc_assert (mode == CCmode || mode == CCNOmode || mode == CCGCmode);
7717 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
7718 Those same assemblers have the same but opposite lossage on cmov. */
7719 gcc_assert (mode == CCmode);
7720 suffix = fp ? "nbe" : "a";
7740 gcc_assert (mode == CCmode);
7762 gcc_assert (mode == CCmode);
7763 suffix = fp ? "nb" : "ae";
7766 gcc_assert (mode == CCmode || mode == CCGCmode || mode == CCNOmode);
7770 gcc_assert (mode == CCmode);
7774 suffix = fp ? "u" : "p";
7777 suffix = fp ? "nu" : "np";
7782 fputs (suffix, file);
7785 /* Print the name of register X to FILE based on its machine mode and number.
7786 If CODE is 'w', pretend the mode is HImode.
7787 If CODE is 'b', pretend the mode is QImode.
7788 If CODE is 'k', pretend the mode is SImode.
7789 If CODE is 'q', pretend the mode is DImode.
7790 If CODE is 'h', pretend the reg is the 'high' byte register.
7791 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */
7794 print_reg (rtx x, int code, FILE *file)
7796 gcc_assert (REGNO (x) != ARG_POINTER_REGNUM
7797 && REGNO (x) != FRAME_POINTER_REGNUM
7798 && REGNO (x) != FLAGS_REG
7799 && REGNO (x) != FPSR_REG
7800 && REGNO (x) != FPCR_REG);
7802 if (ASSEMBLER_DIALECT == ASM_ATT || USER_LABEL_PREFIX[0] == 0)
7805 if (code == 'w' || MMX_REG_P (x))
7807 else if (code == 'b')
7809 else if (code == 'k')
7811 else if (code == 'q')
7813 else if (code == 'y')
7815 else if (code == 'h')
7818 code = GET_MODE_SIZE (GET_MODE (x));
7820 /* Irritatingly, AMD extended registers use different naming convention
7821 from the normal registers. */
7822 if (REX_INT_REG_P (x))
7824 gcc_assert (TARGET_64BIT);
7828 error ("extended registers have no high halves");
7831 fprintf (file, "r%ib", REGNO (x) - FIRST_REX_INT_REG + 8);
7834 fprintf (file, "r%iw", REGNO (x) - FIRST_REX_INT_REG + 8);
7837 fprintf (file, "r%id", REGNO (x) - FIRST_REX_INT_REG + 8);
7840 fprintf (file, "r%i", REGNO (x) - FIRST_REX_INT_REG + 8);
7843 error ("unsupported operand size for extended register");
7851 if (STACK_TOP_P (x))
7853 fputs ("st(0)", file);
7860 if (! ANY_FP_REG_P (x))
7861 putc (code == 8 && TARGET_64BIT ? 'r' : 'e', file);
7866 fputs (hi_reg_name[REGNO (x)], file);
7869 if (REGNO (x) >= ARRAY_SIZE (qi_reg_name))
7871 fputs (qi_reg_name[REGNO (x)], file);
7874 if (REGNO (x) >= ARRAY_SIZE (qi_high_reg_name))
7876 fputs (qi_high_reg_name[REGNO (x)], file);
7883 /* Locate some local-dynamic symbol still in use by this function
7884 so that we can print its name in some tls_local_dynamic_base
7888 get_some_local_dynamic_name (void)
7892 if (cfun->machine->some_ld_name)
7893 return cfun->machine->some_ld_name;
7895 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
7897 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
7898 return cfun->machine->some_ld_name;
7904 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
7908 if (GET_CODE (x) == SYMBOL_REF
7909 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
7911 cfun->machine->some_ld_name = XSTR (x, 0);
7919 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
7920 C -- print opcode suffix for set/cmov insn.
7921 c -- like C, but print reversed condition
7922 F,f -- likewise, but for floating-point.
7923 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
7925 R -- print the prefix for register names.
7926 z -- print the opcode suffix for the size of the current operand.
7927 * -- print a star (in certain assembler syntax)
7928 A -- print an absolute memory reference.
7929 w -- print the operand as if it's a "word" (HImode) even if it isn't.
7930 s -- print a shift double count, followed by the assemblers argument
7932 b -- print the QImode name of the register for the indicated operand.
7933 %b0 would print %al if operands[0] is reg 0.
7934 w -- likewise, print the HImode name of the register.
7935 k -- likewise, print the SImode name of the register.
7936 q -- likewise, print the DImode name of the register.
7937 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
7938 y -- print "st(0)" instead of "st" as a register.
7939 D -- print condition for SSE cmp instruction.
7940 P -- if PIC, print an @PLT suffix.
7941 X -- don't print any sort of PIC '@' suffix for a symbol.
7942 & -- print some in-use local-dynamic symbol name.
7943 H -- print a memory address offset by 8; used for sse high-parts
7947 print_operand (FILE *file, rtx x, int code)
7954 if (ASSEMBLER_DIALECT == ASM_ATT)
7959 assemble_name (file, get_some_local_dynamic_name ());
7963 switch (ASSEMBLER_DIALECT)
7970 /* Intel syntax. For absolute addresses, registers should not
7971 be surrounded by braces. */
7972 if (GET_CODE (x) != REG)
7975 PRINT_OPERAND (file, x, 0);
7985 PRINT_OPERAND (file, x, 0);
7990 if (ASSEMBLER_DIALECT == ASM_ATT)
7995 if (ASSEMBLER_DIALECT == ASM_ATT)
8000 if (ASSEMBLER_DIALECT == ASM_ATT)
8005 if (ASSEMBLER_DIALECT == ASM_ATT)
8010 if (ASSEMBLER_DIALECT == ASM_ATT)
8015 if (ASSEMBLER_DIALECT == ASM_ATT)
8020 /* 387 opcodes don't get size suffixes if the operands are
8022 if (STACK_REG_P (x))
8025 /* Likewise if using Intel opcodes. */
8026 if (ASSEMBLER_DIALECT == ASM_INTEL)
8029 /* This is the size of op from size of operand. */
8030 switch (GET_MODE_SIZE (GET_MODE (x)))
8033 #ifdef HAVE_GAS_FILDS_FISTS
8039 if (GET_MODE (x) == SFmode)
8054 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
8056 #ifdef GAS_MNEMONICS
8082 if (GET_CODE (x) == CONST_INT || ! SHIFT_DOUBLE_OMITS_COUNT)
8084 PRINT_OPERAND (file, x, 0);
8090 /* Little bit of braindamage here. The SSE compare instructions
8091 does use completely different names for the comparisons that the
8092 fp conditional moves. */
8093 switch (GET_CODE (x))
8108 fputs ("unord", file);
8112 fputs ("neq", file);
8116 fputs ("nlt", file);
8120 fputs ("nle", file);
8123 fputs ("ord", file);
8130 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
8131 if (ASSEMBLER_DIALECT == ASM_ATT)
8133 switch (GET_MODE (x))
8135 case HImode: putc ('w', file); break;
8137 case SFmode: putc ('l', file); break;
8139 case DFmode: putc ('q', file); break;
8140 default: gcc_unreachable ();
8147 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 0, file);
8150 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
8151 if (ASSEMBLER_DIALECT == ASM_ATT)
8154 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 1, file);
8157 /* Like above, but reverse condition */
8159 /* Check to see if argument to %c is really a constant
8160 and not a condition code which needs to be reversed. */
8161 if (!COMPARISON_P (x))
8163 output_operand_lossage ("operand is neither a constant nor a condition code, invalid operand code 'c'");
8166 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 0, file);
8169 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
8170 if (ASSEMBLER_DIALECT == ASM_ATT)
8173 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 1, file);
8177 /* It doesn't actually matter what mode we use here, as we're
8178 only going to use this for printing. */
8179 x = adjust_address_nv (x, DImode, 8);
8186 if (!optimize || optimize_size || !TARGET_BRANCH_PREDICTION_HINTS)
8189 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
8192 int pred_val = INTVAL (XEXP (x, 0));
8194 if (pred_val < REG_BR_PROB_BASE * 45 / 100
8195 || pred_val > REG_BR_PROB_BASE * 55 / 100)
8197 int taken = pred_val > REG_BR_PROB_BASE / 2;
8198 int cputaken = final_forward_branch_p (current_output_insn) == 0;
8200 /* Emit hints only in the case default branch prediction
8201 heuristics would fail. */
8202 if (taken != cputaken)
8204 /* We use 3e (DS) prefix for taken branches and
8205 2e (CS) prefix for not taken branches. */
8207 fputs ("ds ; ", file);
8209 fputs ("cs ; ", file);
8216 output_operand_lossage ("invalid operand code '%c'", code);
8220 if (GET_CODE (x) == REG)
8221 print_reg (x, code, file);
8223 else if (GET_CODE (x) == MEM)
8225 /* No `byte ptr' prefix for call instructions. */
8226 if (ASSEMBLER_DIALECT == ASM_INTEL && code != 'X' && code != 'P')
8229 switch (GET_MODE_SIZE (GET_MODE (x)))
8231 case 1: size = "BYTE"; break;
8232 case 2: size = "WORD"; break;
8233 case 4: size = "DWORD"; break;
8234 case 8: size = "QWORD"; break;
8235 case 12: size = "XWORD"; break;
8236 case 16: size = "XMMWORD"; break;
8241 /* Check for explicit size override (codes 'b', 'w' and 'k') */
8244 else if (code == 'w')
8246 else if (code == 'k')
8250 fputs (" PTR ", file);
8254 /* Avoid (%rip) for call operands. */
8255 if (CONSTANT_ADDRESS_P (x) && code == 'P'
8256 && GET_CODE (x) != CONST_INT)
8257 output_addr_const (file, x);
8258 else if (this_is_asm_operands && ! address_operand (x, VOIDmode))
8259 output_operand_lossage ("invalid constraints for operand");
8264 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
8269 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
8270 REAL_VALUE_TO_TARGET_SINGLE (r, l);
8272 if (ASSEMBLER_DIALECT == ASM_ATT)
8274 fprintf (file, "0x%08lx", l);
8277 /* These float cases don't actually occur as immediate operands. */
8278 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
8282 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
8283 fprintf (file, "%s", dstr);
8286 else if (GET_CODE (x) == CONST_DOUBLE
8287 && GET_MODE (x) == XFmode)
8291 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
8292 fprintf (file, "%s", dstr);
8297 /* We have patterns that allow zero sets of memory, for instance.
8298 In 64-bit mode, we should probably support all 8-byte vectors,
8299 since we can in fact encode that into an immediate. */
8300 if (GET_CODE (x) == CONST_VECTOR)
8302 gcc_assert (x == CONST0_RTX (GET_MODE (x)));
8308 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
8310 if (ASSEMBLER_DIALECT == ASM_ATT)
8313 else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
8314 || GET_CODE (x) == LABEL_REF)
8316 if (ASSEMBLER_DIALECT == ASM_ATT)
8319 fputs ("OFFSET FLAT:", file);
8322 if (GET_CODE (x) == CONST_INT)
8323 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
8325 output_pic_addr_const (file, x, code);
8327 output_addr_const (file, x);
8331 /* Print a memory operand whose address is ADDR. */
8334 print_operand_address (FILE *file, rtx addr)
8336 struct ix86_address parts;
8337 rtx base, index, disp;
8339 int ok = ix86_decompose_address (addr, &parts);
8344 index = parts.index;
8346 scale = parts.scale;
8354 if (USER_LABEL_PREFIX[0] == 0)
8356 fputs ((parts.seg == SEG_FS ? "fs:" : "gs:"), file);
8362 if (!base && !index)
8364 /* Displacement only requires special attention. */
8366 if (GET_CODE (disp) == CONST_INT)
8368 if (ASSEMBLER_DIALECT == ASM_INTEL && parts.seg == SEG_DEFAULT)
8370 if (USER_LABEL_PREFIX[0] == 0)
8372 fputs ("ds:", file);
8374 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (disp));
8377 output_pic_addr_const (file, disp, 0);
8379 output_addr_const (file, disp);
8381 /* Use one byte shorter RIP relative addressing for 64bit mode. */
8384 if (GET_CODE (disp) == CONST
8385 && GET_CODE (XEXP (disp, 0)) == PLUS
8386 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
8387 disp = XEXP (XEXP (disp, 0), 0);
8388 if (GET_CODE (disp) == LABEL_REF
8389 || (GET_CODE (disp) == SYMBOL_REF
8390 && SYMBOL_REF_TLS_MODEL (disp) == 0))
8391 fputs ("(%rip)", file);
8396 if (ASSEMBLER_DIALECT == ASM_ATT)
8401 output_pic_addr_const (file, disp, 0);
8402 else if (GET_CODE (disp) == LABEL_REF)
8403 output_asm_label (disp);
8405 output_addr_const (file, disp);
8410 print_reg (base, 0, file);
8414 print_reg (index, 0, file);
8416 fprintf (file, ",%d", scale);
8422 rtx offset = NULL_RTX;
8426 /* Pull out the offset of a symbol; print any symbol itself. */
8427 if (GET_CODE (disp) == CONST
8428 && GET_CODE (XEXP (disp, 0)) == PLUS
8429 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
8431 offset = XEXP (XEXP (disp, 0), 1);
8432 disp = gen_rtx_CONST (VOIDmode,
8433 XEXP (XEXP (disp, 0), 0));
8437 output_pic_addr_const (file, disp, 0);
8438 else if (GET_CODE (disp) == LABEL_REF)
8439 output_asm_label (disp);
8440 else if (GET_CODE (disp) == CONST_INT)
8443 output_addr_const (file, disp);
8449 print_reg (base, 0, file);
8452 if (INTVAL (offset) >= 0)
8454 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
8458 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
8465 print_reg (index, 0, file);
8467 fprintf (file, "*%d", scale);
8475 output_addr_const_extra (FILE *file, rtx x)
8479 if (GET_CODE (x) != UNSPEC)
8482 op = XVECEXP (x, 0, 0);
8483 switch (XINT (x, 1))
8485 case UNSPEC_GOTTPOFF:
8486 output_addr_const (file, op);
8487 /* FIXME: This might be @TPOFF in Sun ld. */
8488 fputs ("@GOTTPOFF", file);
8491 output_addr_const (file, op);
8492 fputs ("@TPOFF", file);
8495 output_addr_const (file, op);
8497 fputs ("@TPOFF", file);
8499 fputs ("@NTPOFF", file);
8502 output_addr_const (file, op);
8503 fputs ("@DTPOFF", file);
8505 case UNSPEC_GOTNTPOFF:
8506 output_addr_const (file, op);
8508 fputs ("@GOTTPOFF(%rip)", file);
8510 fputs ("@GOTNTPOFF", file);
8512 case UNSPEC_INDNTPOFF:
8513 output_addr_const (file, op);
8514 fputs ("@INDNTPOFF", file);
8524 /* Split one or more DImode RTL references into pairs of SImode
8525 references. The RTL can be REG, offsettable MEM, integer constant, or
8526 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
8527 split and "num" is its length. lo_half and hi_half are output arrays
8528 that parallel "operands". */
8531 split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
8535 rtx op = operands[num];
8537 /* simplify_subreg refuse to split volatile memory addresses,
8538 but we still have to handle it. */
8539 if (GET_CODE (op) == MEM)
8541 lo_half[num] = adjust_address (op, SImode, 0);
8542 hi_half[num] = adjust_address (op, SImode, 4);
8546 lo_half[num] = simplify_gen_subreg (SImode, op,
8547 GET_MODE (op) == VOIDmode
8548 ? DImode : GET_MODE (op), 0);
8549 hi_half[num] = simplify_gen_subreg (SImode, op,
8550 GET_MODE (op) == VOIDmode
8551 ? DImode : GET_MODE (op), 4);
8555 /* Split one or more TImode RTL references into pairs of DImode
8556 references. The RTL can be REG, offsettable MEM, integer constant, or
8557 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
8558 split and "num" is its length. lo_half and hi_half are output arrays
8559 that parallel "operands". */
8562 split_ti (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
8566 rtx op = operands[num];
8568 /* simplify_subreg refuse to split volatile memory addresses, but we
8569 still have to handle it. */
8570 if (GET_CODE (op) == MEM)
8572 lo_half[num] = adjust_address (op, DImode, 0);
8573 hi_half[num] = adjust_address (op, DImode, 8);
8577 lo_half[num] = simplify_gen_subreg (DImode, op, TImode, 0);
8578 hi_half[num] = simplify_gen_subreg (DImode, op, TImode, 8);
8583 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
8584 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
8585 is the expression of the binary operation. The output may either be
8586 emitted here, or returned to the caller, like all output_* functions.
8588 There is no guarantee that the operands are the same mode, as they
8589 might be within FLOAT or FLOAT_EXTEND expressions. */
8591 #ifndef SYSV386_COMPAT
8592 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
8593 wants to fix the assemblers because that causes incompatibility
8594 with gcc. No-one wants to fix gcc because that causes
8595 incompatibility with assemblers... You can use the option of
8596 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
8597 #define SYSV386_COMPAT 1
8601 output_387_binary_op (rtx insn, rtx *operands)
8603 static char buf[30];
8606 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]) || SSE_REG_P (operands[2]);
8608 #ifdef ENABLE_CHECKING
8609 /* Even if we do not want to check the inputs, this documents input
8610 constraints. Which helps in understanding the following code. */
8611 if (STACK_REG_P (operands[0])
8612 && ((REG_P (operands[1])
8613 && REGNO (operands[0]) == REGNO (operands[1])
8614 && (STACK_REG_P (operands[2]) || GET_CODE (operands[2]) == MEM))
8615 || (REG_P (operands[2])
8616 && REGNO (operands[0]) == REGNO (operands[2])
8617 && (STACK_REG_P (operands[1]) || GET_CODE (operands[1]) == MEM)))
8618 && (STACK_TOP_P (operands[1]) || STACK_TOP_P (operands[2])))
8621 gcc_assert (is_sse);
8624 switch (GET_CODE (operands[3]))
8627 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
8628 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
8636 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
8637 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
8645 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
8646 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
8654 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
8655 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
8669 if (GET_MODE (operands[0]) == SFmode)
8670 strcat (buf, "ss\t{%2, %0|%0, %2}");
8672 strcat (buf, "sd\t{%2, %0|%0, %2}");
8677 switch (GET_CODE (operands[3]))
8681 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
8683 rtx temp = operands[2];
8684 operands[2] = operands[1];
8688 /* know operands[0] == operands[1]. */
8690 if (GET_CODE (operands[2]) == MEM)
8696 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
8698 if (STACK_TOP_P (operands[0]))
8699 /* How is it that we are storing to a dead operand[2]?
8700 Well, presumably operands[1] is dead too. We can't
8701 store the result to st(0) as st(0) gets popped on this
8702 instruction. Instead store to operands[2] (which I
8703 think has to be st(1)). st(1) will be popped later.
8704 gcc <= 2.8.1 didn't have this check and generated
8705 assembly code that the Unixware assembler rejected. */
8706 p = "p\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
8708 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
8712 if (STACK_TOP_P (operands[0]))
8713 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
8715 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
8720 if (GET_CODE (operands[1]) == MEM)
8726 if (GET_CODE (operands[2]) == MEM)
8732 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
8735 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
8736 derived assemblers, confusingly reverse the direction of
8737 the operation for fsub{r} and fdiv{r} when the
8738 destination register is not st(0). The Intel assembler
8739 doesn't have this brain damage. Read !SYSV386_COMPAT to
8740 figure out what the hardware really does. */
8741 if (STACK_TOP_P (operands[0]))
8742 p = "{p\t%0, %2|rp\t%2, %0}";
8744 p = "{rp\t%2, %0|p\t%0, %2}";
8746 if (STACK_TOP_P (operands[0]))
8747 /* As above for fmul/fadd, we can't store to st(0). */
8748 p = "rp\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
8750 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
8755 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
8758 if (STACK_TOP_P (operands[0]))
8759 p = "{rp\t%0, %1|p\t%1, %0}";
8761 p = "{p\t%1, %0|rp\t%0, %1}";
8763 if (STACK_TOP_P (operands[0]))
8764 p = "p\t{%0, %1|%1, %0}"; /* st(1) = st(1) op st(0); pop */
8766 p = "rp\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2); pop */
8771 if (STACK_TOP_P (operands[0]))
8773 if (STACK_TOP_P (operands[1]))
8774 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
8776 p = "r\t{%y1, %0|%0, %y1}"; /* st(0) = st(r1) op st(0) */
8779 else if (STACK_TOP_P (operands[1]))
8782 p = "{\t%1, %0|r\t%0, %1}";
8784 p = "r\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2) */
8790 p = "{r\t%2, %0|\t%0, %2}";
8792 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
8805 /* Return needed mode for entity in optimize_mode_switching pass. */
8808 ix86_mode_needed (int entity, rtx insn)
8810 enum attr_i387_cw mode;
8812 /* The mode UNINITIALIZED is used to store control word after a
8813 function call or ASM pattern. The mode ANY specify that function
8814 has no requirements on the control word and make no changes in the
8815 bits we are interested in. */
8818 || (NONJUMP_INSN_P (insn)
8819 && (asm_noperands (PATTERN (insn)) >= 0
8820 || GET_CODE (PATTERN (insn)) == ASM_INPUT)))
8821 return I387_CW_UNINITIALIZED;
8823 if (recog_memoized (insn) < 0)
8826 mode = get_attr_i387_cw (insn);
8831 if (mode == I387_CW_TRUNC)
8836 if (mode == I387_CW_FLOOR)
8841 if (mode == I387_CW_CEIL)
8846 if (mode == I387_CW_MASK_PM)
8857 /* Output code to initialize control word copies used by trunc?f?i and
8858 rounding patterns. CURRENT_MODE is set to current control word,
8859 while NEW_MODE is set to new control word. */
8862 emit_i387_cw_initialization (int mode)
8864 rtx stored_mode = assign_386_stack_local (HImode, SLOT_CW_STORED);
8869 rtx reg = gen_reg_rtx (HImode);
8871 emit_insn (gen_x86_fnstcw_1 (stored_mode));
8872 emit_move_insn (reg, copy_rtx (stored_mode));
8874 if (TARGET_64BIT || TARGET_PARTIAL_REG_STALL || optimize_size)
8879 /* round toward zero (truncate) */
8880 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0c00)));
8881 slot = SLOT_CW_TRUNC;
8885 /* round down toward -oo */
8886 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
8887 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0400)));
8888 slot = SLOT_CW_FLOOR;
8892 /* round up toward +oo */
8893 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
8894 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0800)));
8895 slot = SLOT_CW_CEIL;
8898 case I387_CW_MASK_PM:
8899 /* mask precision exception for nearbyint() */
8900 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
8901 slot = SLOT_CW_MASK_PM;
8913 /* round toward zero (truncate) */
8914 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0xc)));
8915 slot = SLOT_CW_TRUNC;
8919 /* round down toward -oo */
8920 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x4)));
8921 slot = SLOT_CW_FLOOR;
8925 /* round up toward +oo */
8926 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x8)));
8927 slot = SLOT_CW_CEIL;
8930 case I387_CW_MASK_PM:
8931 /* mask precision exception for nearbyint() */
8932 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
8933 slot = SLOT_CW_MASK_PM;
8941 gcc_assert (slot < MAX_386_STACK_LOCALS);
8943 new_mode = assign_386_stack_local (HImode, slot);
8944 emit_move_insn (new_mode, reg);
8947 /* Output code for INSN to convert a float to a signed int. OPERANDS
8948 are the insn operands. The output may be [HSD]Imode and the input
8949 operand may be [SDX]Fmode. */
8952 output_fix_trunc (rtx insn, rtx *operands, int fisttp)
8954 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
8955 int dimode_p = GET_MODE (operands[0]) == DImode;
8956 int round_mode = get_attr_i387_cw (insn);
8958 /* Jump through a hoop or two for DImode, since the hardware has no
8959 non-popping instruction. We used to do this a different way, but
8960 that was somewhat fragile and broke with post-reload splitters. */
8961 if ((dimode_p || fisttp) && !stack_top_dies)
8962 output_asm_insn ("fld\t%y1", operands);
8964 gcc_assert (STACK_TOP_P (operands[1]));
8965 gcc_assert (GET_CODE (operands[0]) == MEM);
8968 output_asm_insn ("fisttp%z0\t%0", operands);
8971 if (round_mode != I387_CW_ANY)
8972 output_asm_insn ("fldcw\t%3", operands);
8973 if (stack_top_dies || dimode_p)
8974 output_asm_insn ("fistp%z0\t%0", operands);
8976 output_asm_insn ("fist%z0\t%0", operands);
8977 if (round_mode != I387_CW_ANY)
8978 output_asm_insn ("fldcw\t%2", operands);
8984 /* Output code for x87 ffreep insn. The OPNO argument, which may only
8985 have the values zero or one, indicates the ffreep insn's operand
8986 from the OPERANDS array. */
8989 output_387_ffreep (rtx *operands ATTRIBUTE_UNUSED, int opno)
8991 if (TARGET_USE_FFREEP)
8992 #if HAVE_AS_IX86_FFREEP
8993 return opno ? "ffreep\t%y1" : "ffreep\t%y0";
8996 static char retval[] = ".word\t0xc_df";
8997 int regno = REGNO (operands[opno]);
8999 gcc_assert (FP_REGNO_P (regno));
9001 retval[9] = '0' + (regno - FIRST_STACK_REG);
9006 return opno ? "fstp\t%y1" : "fstp\t%y0";
9010 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
9011 should be used. UNORDERED_P is true when fucom should be used. */
9014 output_fp_compare (rtx insn, rtx *operands, int eflags_p, int unordered_p)
9017 rtx cmp_op0, cmp_op1;
9018 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]);
9022 cmp_op0 = operands[0];
9023 cmp_op1 = operands[1];
9027 cmp_op0 = operands[1];
9028 cmp_op1 = operands[2];
9033 if (GET_MODE (operands[0]) == SFmode)
9035 return "ucomiss\t{%1, %0|%0, %1}";
9037 return "comiss\t{%1, %0|%0, %1}";
9040 return "ucomisd\t{%1, %0|%0, %1}";
9042 return "comisd\t{%1, %0|%0, %1}";
9045 gcc_assert (STACK_TOP_P (cmp_op0));
9047 stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
9049 if (cmp_op1 == CONST0_RTX (GET_MODE (cmp_op1)))
9053 output_asm_insn ("ftst\n\tfnstsw\t%0", operands);
9054 return output_387_ffreep (operands, 1);
9057 return "ftst\n\tfnstsw\t%0";
9060 if (STACK_REG_P (cmp_op1)
9062 && find_regno_note (insn, REG_DEAD, REGNO (cmp_op1))
9063 && REGNO (cmp_op1) != FIRST_STACK_REG)
9065 /* If both the top of the 387 stack dies, and the other operand
9066 is also a stack register that dies, then this must be a
9067 `fcompp' float compare */
9071 /* There is no double popping fcomi variant. Fortunately,
9072 eflags is immune from the fstp's cc clobbering. */
9074 output_asm_insn ("fucomip\t{%y1, %0|%0, %y1}", operands);
9076 output_asm_insn ("fcomip\t{%y1, %0|%0, %y1}", operands);
9077 return output_387_ffreep (operands, 0);
9082 return "fucompp\n\tfnstsw\t%0";
9084 return "fcompp\n\tfnstsw\t%0";
9089 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
9091 static const char * const alt[16] =
9093 "fcom%z2\t%y2\n\tfnstsw\t%0",
9094 "fcomp%z2\t%y2\n\tfnstsw\t%0",
9095 "fucom%z2\t%y2\n\tfnstsw\t%0",
9096 "fucomp%z2\t%y2\n\tfnstsw\t%0",
9098 "ficom%z2\t%y2\n\tfnstsw\t%0",
9099 "ficomp%z2\t%y2\n\tfnstsw\t%0",
9103 "fcomi\t{%y1, %0|%0, %y1}",
9104 "fcomip\t{%y1, %0|%0, %y1}",
9105 "fucomi\t{%y1, %0|%0, %y1}",
9106 "fucomip\t{%y1, %0|%0, %y1}",
9117 mask = eflags_p << 3;
9118 mask |= (GET_MODE_CLASS (GET_MODE (cmp_op1)) == MODE_INT) << 2;
9119 mask |= unordered_p << 1;
9120 mask |= stack_top_dies;
9122 gcc_assert (mask < 16);
9131 ix86_output_addr_vec_elt (FILE *file, int value)
9133 const char *directive = ASM_LONG;
9137 directive = ASM_QUAD;
9139 gcc_assert (!TARGET_64BIT);
9142 fprintf (file, "%s%s%d\n", directive, LPREFIX, value);
9146 ix86_output_addr_diff_elt (FILE *file, int value, int rel)
9149 fprintf (file, "%s%s%d-%s%d\n",
9150 ASM_LONG, LPREFIX, value, LPREFIX, rel);
9151 else if (HAVE_AS_GOTOFF_IN_DATA)
9152 fprintf (file, "%s%s%d@GOTOFF\n", ASM_LONG, LPREFIX, value);
9154 else if (TARGET_MACHO)
9156 fprintf (file, "%s%s%d-", ASM_LONG, LPREFIX, value);
9157 machopic_output_function_base_name (file);
9158 fprintf(file, "\n");
9162 asm_fprintf (file, "%s%U%s+[.-%s%d]\n",
9163 ASM_LONG, GOT_SYMBOL_NAME, LPREFIX, value);
9166 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
9170 ix86_expand_clear (rtx dest)
9174 /* We play register width games, which are only valid after reload. */
9175 gcc_assert (reload_completed);
9177 /* Avoid HImode and its attendant prefix byte. */
9178 if (GET_MODE_SIZE (GET_MODE (dest)) < 4)
9179 dest = gen_rtx_REG (SImode, REGNO (dest));
9181 tmp = gen_rtx_SET (VOIDmode, dest, const0_rtx);
9183 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
9184 if (reload_completed && (!TARGET_USE_MOV0 || optimize_size))
9186 rtx clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, 17));
9187 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, clob));
9193 /* X is an unchanging MEM. If it is a constant pool reference, return
9194 the constant pool rtx, else NULL. */
9197 maybe_get_pool_constant (rtx x)
9199 x = ix86_delegitimize_address (XEXP (x, 0));
9201 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
9202 return get_pool_constant (x);
9208 ix86_expand_move (enum machine_mode mode, rtx operands[])
9210 int strict = (reload_in_progress || reload_completed);
9212 enum tls_model model;
9217 if (GET_CODE (op1) == SYMBOL_REF)
9219 model = SYMBOL_REF_TLS_MODEL (op1);
9222 op1 = legitimize_tls_address (op1, model, true);
9223 op1 = force_operand (op1, op0);
9228 else if (GET_CODE (op1) == CONST
9229 && GET_CODE (XEXP (op1, 0)) == PLUS
9230 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SYMBOL_REF)
9232 model = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (op1, 0), 0));
9235 rtx addend = XEXP (XEXP (op1, 0), 1);
9236 op1 = legitimize_tls_address (XEXP (XEXP (op1, 0), 0), model, true);
9237 op1 = force_operand (op1, NULL);
9238 op1 = expand_simple_binop (Pmode, PLUS, op1, addend,
9239 op0, 1, OPTAB_DIRECT);
9245 if (flag_pic && mode == Pmode && symbolic_operand (op1, Pmode))
9247 if (TARGET_MACHO && !TARGET_64BIT)
9252 rtx temp = ((reload_in_progress
9253 || ((op0 && GET_CODE (op0) == REG)
9255 ? op0 : gen_reg_rtx (Pmode));
9256 op1 = machopic_indirect_data_reference (op1, temp);
9257 op1 = machopic_legitimize_pic_address (op1, mode,
9258 temp == op1 ? 0 : temp);
9260 else if (MACHOPIC_INDIRECT)
9261 op1 = machopic_indirect_data_reference (op1, 0);
9268 if (GET_CODE (op0) == MEM)
9269 op1 = force_reg (Pmode, op1);
9271 op1 = legitimize_address (op1, op1, Pmode);
9276 if (GET_CODE (op0) == MEM
9277 && (PUSH_ROUNDING (GET_MODE_SIZE (mode)) != GET_MODE_SIZE (mode)
9278 || !push_operand (op0, mode))
9279 && GET_CODE (op1) == MEM)
9280 op1 = force_reg (mode, op1);
9282 if (push_operand (op0, mode)
9283 && ! general_no_elim_operand (op1, mode))
9284 op1 = copy_to_mode_reg (mode, op1);
9286 /* Force large constants in 64bit compilation into register
9287 to get them CSEed. */
9288 if (TARGET_64BIT && mode == DImode
9289 && immediate_operand (op1, mode)
9290 && !x86_64_zext_immediate_operand (op1, VOIDmode)
9291 && !register_operand (op0, mode)
9292 && optimize && !reload_completed && !reload_in_progress)
9293 op1 = copy_to_mode_reg (mode, op1);
9295 if (FLOAT_MODE_P (mode))
9297 /* If we are loading a floating point constant to a register,
9298 force the value to memory now, since we'll get better code
9299 out the back end. */
9303 else if (GET_CODE (op1) == CONST_DOUBLE)
9305 op1 = validize_mem (force_const_mem (mode, op1));
9306 if (!register_operand (op0, mode))
9308 rtx temp = gen_reg_rtx (mode);
9309 emit_insn (gen_rtx_SET (VOIDmode, temp, op1));
9310 emit_move_insn (op0, temp);
9317 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
9321 ix86_expand_vector_move (enum machine_mode mode, rtx operands[])
9323 rtx op0 = operands[0], op1 = operands[1];
9325 /* Force constants other than zero into memory. We do not know how
9326 the instructions used to build constants modify the upper 64 bits
9327 of the register, once we have that information we may be able
9328 to handle some of them more efficiently. */
9329 if ((reload_in_progress | reload_completed) == 0
9330 && register_operand (op0, mode)
9332 && standard_sse_constant_p (op1) <= 0)
9333 op1 = validize_mem (force_const_mem (mode, op1));
9335 /* Make operand1 a register if it isn't already. */
9337 && !register_operand (op0, mode)
9338 && !register_operand (op1, mode))
9340 emit_move_insn (op0, force_reg (GET_MODE (op0), op1));
9344 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
9347 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
9348 straight to ix86_expand_vector_move. */
9351 ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[])
9360 /* If we're optimizing for size, movups is the smallest. */
9363 op0 = gen_lowpart (V4SFmode, op0);
9364 op1 = gen_lowpart (V4SFmode, op1);
9365 emit_insn (gen_sse_movups (op0, op1));
9369 /* ??? If we have typed data, then it would appear that using
9370 movdqu is the only way to get unaligned data loaded with
9372 if (TARGET_SSE2 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
9374 op0 = gen_lowpart (V16QImode, op0);
9375 op1 = gen_lowpart (V16QImode, op1);
9376 emit_insn (gen_sse2_movdqu (op0, op1));
9380 if (TARGET_SSE2 && mode == V2DFmode)
9384 /* When SSE registers are split into halves, we can avoid
9385 writing to the top half twice. */
9386 if (TARGET_SSE_SPLIT_REGS)
9388 emit_insn (gen_rtx_CLOBBER (VOIDmode, op0));
9393 /* ??? Not sure about the best option for the Intel chips.
9394 The following would seem to satisfy; the register is
9395 entirely cleared, breaking the dependency chain. We
9396 then store to the upper half, with a dependency depth
9397 of one. A rumor has it that Intel recommends two movsd
9398 followed by an unpacklpd, but this is unconfirmed. And
9399 given that the dependency depth of the unpacklpd would
9400 still be one, I'm not sure why this would be better. */
9401 zero = CONST0_RTX (V2DFmode);
9404 m = adjust_address (op1, DFmode, 0);
9405 emit_insn (gen_sse2_loadlpd (op0, zero, m));
9406 m = adjust_address (op1, DFmode, 8);
9407 emit_insn (gen_sse2_loadhpd (op0, op0, m));
9411 if (TARGET_SSE_PARTIAL_REG_DEPENDENCY)
9412 emit_move_insn (op0, CONST0_RTX (mode));
9414 emit_insn (gen_rtx_CLOBBER (VOIDmode, op0));
9416 if (mode != V4SFmode)
9417 op0 = gen_lowpart (V4SFmode, op0);
9418 m = adjust_address (op1, V2SFmode, 0);
9419 emit_insn (gen_sse_loadlps (op0, op0, m));
9420 m = adjust_address (op1, V2SFmode, 8);
9421 emit_insn (gen_sse_loadhps (op0, op0, m));
9424 else if (MEM_P (op0))
9426 /* If we're optimizing for size, movups is the smallest. */
9429 op0 = gen_lowpart (V4SFmode, op0);
9430 op1 = gen_lowpart (V4SFmode, op1);
9431 emit_insn (gen_sse_movups (op0, op1));
9435 /* ??? Similar to above, only less clear because of quote
9436 typeless stores unquote. */
9437 if (TARGET_SSE2 && !TARGET_SSE_TYPELESS_STORES
9438 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
9440 op0 = gen_lowpart (V16QImode, op0);
9441 op1 = gen_lowpart (V16QImode, op1);
9442 emit_insn (gen_sse2_movdqu (op0, op1));
9446 if (TARGET_SSE2 && mode == V2DFmode)
9448 m = adjust_address (op0, DFmode, 0);
9449 emit_insn (gen_sse2_storelpd (m, op1));
9450 m = adjust_address (op0, DFmode, 8);
9451 emit_insn (gen_sse2_storehpd (m, op1));
9455 if (mode != V4SFmode)
9456 op1 = gen_lowpart (V4SFmode, op1);
9457 m = adjust_address (op0, V2SFmode, 0);
9458 emit_insn (gen_sse_storelps (m, op1));
9459 m = adjust_address (op0, V2SFmode, 8);
9460 emit_insn (gen_sse_storehps (m, op1));
9467 /* Expand a push in MODE. This is some mode for which we do not support
9468 proper push instructions, at least from the registers that we expect
9469 the value to live in. */
9472 ix86_expand_push (enum machine_mode mode, rtx x)
9476 tmp = expand_simple_binop (Pmode, PLUS, stack_pointer_rtx,
9477 GEN_INT (-GET_MODE_SIZE (mode)),
9478 stack_pointer_rtx, 1, OPTAB_DIRECT);
9479 if (tmp != stack_pointer_rtx)
9480 emit_move_insn (stack_pointer_rtx, tmp);
9482 tmp = gen_rtx_MEM (mode, stack_pointer_rtx);
9483 emit_move_insn (tmp, x);
9486 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
9487 destination to use for the operation. If different from the true
9488 destination in operands[0], a copy operation will be required. */
9491 ix86_fixup_binary_operands (enum rtx_code code, enum machine_mode mode,
9494 int matching_memory;
9495 rtx src1, src2, dst;
9501 /* Recognize <var1> = <value> <op> <var1> for commutative operators */
9502 if (GET_RTX_CLASS (code) == RTX_COMM_ARITH
9503 && (rtx_equal_p (dst, src2)
9504 || immediate_operand (src1, mode)))
9511 /* If the destination is memory, and we do not have matching source
9512 operands, do things in registers. */
9513 matching_memory = 0;
9514 if (GET_CODE (dst) == MEM)
9516 if (rtx_equal_p (dst, src1))
9517 matching_memory = 1;
9518 else if (GET_RTX_CLASS (code) == RTX_COMM_ARITH
9519 && rtx_equal_p (dst, src2))
9520 matching_memory = 2;
9522 dst = gen_reg_rtx (mode);
9525 /* Both source operands cannot be in memory. */
9526 if (GET_CODE (src1) == MEM && GET_CODE (src2) == MEM)
9528 if (matching_memory != 2)
9529 src2 = force_reg (mode, src2);
9531 src1 = force_reg (mode, src1);
9534 /* If the operation is not commutable, source 1 cannot be a constant
9535 or non-matching memory. */
9536 if ((CONSTANT_P (src1)
9537 || (!matching_memory && GET_CODE (src1) == MEM))
9538 && GET_RTX_CLASS (code) != RTX_COMM_ARITH)
9539 src1 = force_reg (mode, src1);
9541 src1 = operands[1] = src1;
9542 src2 = operands[2] = src2;
9546 /* Similarly, but assume that the destination has already been
9550 ix86_fixup_binary_operands_no_copy (enum rtx_code code,
9551 enum machine_mode mode, rtx operands[])
9553 rtx dst = ix86_fixup_binary_operands (code, mode, operands);
9554 gcc_assert (dst == operands[0]);
9557 /* Attempt to expand a binary operator. Make the expansion closer to the
9558 actual machine, then just general_operand, which will allow 3 separate
9559 memory references (one output, two input) in a single insn. */
9562 ix86_expand_binary_operator (enum rtx_code code, enum machine_mode mode,
9565 rtx src1, src2, dst, op, clob;
9567 dst = ix86_fixup_binary_operands (code, mode, operands);
9571 /* Emit the instruction. */
9573 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, mode, src1, src2));
9574 if (reload_in_progress)
9576 /* Reload doesn't know about the flags register, and doesn't know that
9577 it doesn't want to clobber it. We can only do this with PLUS. */
9578 gcc_assert (code == PLUS);
9583 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
9584 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
9587 /* Fix up the destination if needed. */
9588 if (dst != operands[0])
9589 emit_move_insn (operands[0], dst);
9592 /* Return TRUE or FALSE depending on whether the binary operator meets the
9593 appropriate constraints. */
9596 ix86_binary_operator_ok (enum rtx_code code,
9597 enum machine_mode mode ATTRIBUTE_UNUSED,
9600 /* Both source operands cannot be in memory. */
9601 if (GET_CODE (operands[1]) == MEM && GET_CODE (operands[2]) == MEM)
9603 /* If the operation is not commutable, source 1 cannot be a constant. */
9604 if (CONSTANT_P (operands[1]) && GET_RTX_CLASS (code) != RTX_COMM_ARITH)
9606 /* If the destination is memory, we must have a matching source operand. */
9607 if (GET_CODE (operands[0]) == MEM
9608 && ! (rtx_equal_p (operands[0], operands[1])
9609 || (GET_RTX_CLASS (code) == RTX_COMM_ARITH
9610 && rtx_equal_p (operands[0], operands[2]))))
9612 /* If the operation is not commutable and the source 1 is memory, we must
9613 have a matching destination. */
9614 if (GET_CODE (operands[1]) == MEM
9615 && GET_RTX_CLASS (code) != RTX_COMM_ARITH
9616 && ! rtx_equal_p (operands[0], operands[1]))
9621 /* Attempt to expand a unary operator. Make the expansion closer to the
9622 actual machine, then just general_operand, which will allow 2 separate
9623 memory references (one output, one input) in a single insn. */
9626 ix86_expand_unary_operator (enum rtx_code code, enum machine_mode mode,
9629 int matching_memory;
9630 rtx src, dst, op, clob;
9635 /* If the destination is memory, and we do not have matching source
9636 operands, do things in registers. */
9637 matching_memory = 0;
9640 if (rtx_equal_p (dst, src))
9641 matching_memory = 1;
9643 dst = gen_reg_rtx (mode);
9646 /* When source operand is memory, destination must match. */
9647 if (MEM_P (src) && !matching_memory)
9648 src = force_reg (mode, src);
9650 /* Emit the instruction. */
9652 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_e (code, mode, src));
9653 if (reload_in_progress || code == NOT)
9655 /* Reload doesn't know about the flags register, and doesn't know that
9656 it doesn't want to clobber it. */
9657 gcc_assert (code == NOT);
9662 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
9663 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
9666 /* Fix up the destination if needed. */
9667 if (dst != operands[0])
9668 emit_move_insn (operands[0], dst);
9671 /* Return TRUE or FALSE depending on whether the unary operator meets the
9672 appropriate constraints. */
9675 ix86_unary_operator_ok (enum rtx_code code ATTRIBUTE_UNUSED,
9676 enum machine_mode mode ATTRIBUTE_UNUSED,
9677 rtx operands[2] ATTRIBUTE_UNUSED)
9679 /* If one of operands is memory, source and destination must match. */
9680 if ((GET_CODE (operands[0]) == MEM
9681 || GET_CODE (operands[1]) == MEM)
9682 && ! rtx_equal_p (operands[0], operands[1]))
9687 /* A subroutine of ix86_expand_fp_absneg_operator and copysign expanders.
9688 Create a mask for the sign bit in MODE for an SSE register. If VECT is
9689 true, then replicate the mask for all elements of the vector register.
9690 If INVERT is true, then create a mask excluding the sign bit. */
9693 ix86_build_signbit_mask (enum machine_mode mode, bool vect, bool invert)
9695 enum machine_mode vec_mode;
9696 HOST_WIDE_INT hi, lo;
9701 /* Find the sign bit, sign extended to 2*HWI. */
9703 lo = 0x80000000, hi = lo < 0;
9704 else if (HOST_BITS_PER_WIDE_INT >= 64)
9705 lo = (HOST_WIDE_INT)1 << shift, hi = -1;
9707 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
9712 /* Force this value into the low part of a fp vector constant. */
9713 mask = immed_double_const (lo, hi, mode == SFmode ? SImode : DImode);
9714 mask = gen_lowpart (mode, mask);
9719 v = gen_rtvec (4, mask, mask, mask, mask);
9721 v = gen_rtvec (4, mask, CONST0_RTX (SFmode),
9722 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
9723 vec_mode = V4SFmode;
9728 v = gen_rtvec (2, mask, mask);
9730 v = gen_rtvec (2, mask, CONST0_RTX (DFmode));
9731 vec_mode = V2DFmode;
9734 return force_reg (vec_mode, gen_rtx_CONST_VECTOR (vec_mode, v));
9737 /* Generate code for floating point ABS or NEG. */
9740 ix86_expand_fp_absneg_operator (enum rtx_code code, enum machine_mode mode,
9743 rtx mask, set, use, clob, dst, src;
9744 bool matching_memory;
9745 bool use_sse = false;
9746 bool vector_mode = VECTOR_MODE_P (mode);
9747 enum machine_mode elt_mode = mode;
9751 elt_mode = GET_MODE_INNER (mode);
9754 else if (TARGET_SSE_MATH)
9755 use_sse = SSE_FLOAT_MODE_P (mode);
9757 /* NEG and ABS performed with SSE use bitwise mask operations.
9758 Create the appropriate mask now. */
9760 mask = ix86_build_signbit_mask (elt_mode, vector_mode, code == ABS);
9767 /* If the destination is memory, and we don't have matching source
9768 operands or we're using the x87, do things in registers. */
9769 matching_memory = false;
9772 if (use_sse && rtx_equal_p (dst, src))
9773 matching_memory = true;
9775 dst = gen_reg_rtx (mode);
9777 if (MEM_P (src) && !matching_memory)
9778 src = force_reg (mode, src);
9782 set = gen_rtx_fmt_ee (code == NEG ? XOR : AND, mode, src, mask);
9783 set = gen_rtx_SET (VOIDmode, dst, set);
9788 set = gen_rtx_fmt_e (code, mode, src);
9789 set = gen_rtx_SET (VOIDmode, dst, set);
9792 use = gen_rtx_USE (VOIDmode, mask);
9793 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
9794 emit_insn (gen_rtx_PARALLEL (VOIDmode,
9795 gen_rtvec (3, set, use, clob)));
9801 if (dst != operands[0])
9802 emit_move_insn (operands[0], dst);
9805 /* Expand a copysign operation. Special case operand 0 being a constant. */
9808 ix86_expand_copysign (rtx operands[])
9810 enum machine_mode mode, vmode;
9811 rtx dest, op0, op1, mask, nmask;
9817 mode = GET_MODE (dest);
9818 vmode = mode == SFmode ? V4SFmode : V2DFmode;
9820 if (GET_CODE (op0) == CONST_DOUBLE)
9824 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0)))
9825 op0 = simplify_unary_operation (ABS, mode, op0, mode);
9827 if (op0 == CONST0_RTX (mode))
9828 op0 = CONST0_RTX (vmode);
9832 v = gen_rtvec (4, op0, CONST0_RTX (SFmode),
9833 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
9835 v = gen_rtvec (2, op0, CONST0_RTX (DFmode));
9836 op0 = force_reg (vmode, gen_rtx_CONST_VECTOR (vmode, v));
9839 mask = ix86_build_signbit_mask (mode, 0, 0);
9842 emit_insn (gen_copysignsf3_const (dest, op0, op1, mask));
9844 emit_insn (gen_copysigndf3_const (dest, op0, op1, mask));
9848 nmask = ix86_build_signbit_mask (mode, 0, 1);
9849 mask = ix86_build_signbit_mask (mode, 0, 0);
9852 emit_insn (gen_copysignsf3_var (dest, NULL, op0, op1, nmask, mask));
9854 emit_insn (gen_copysigndf3_var (dest, NULL, op0, op1, nmask, mask));
9858 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
9859 be a constant, and so has already been expanded into a vector constant. */
9862 ix86_split_copysign_const (rtx operands[])
9864 enum machine_mode mode, vmode;
9865 rtx dest, op0, op1, mask, x;
9872 mode = GET_MODE (dest);
9873 vmode = GET_MODE (mask);
9875 dest = simplify_gen_subreg (vmode, dest, mode, 0);
9876 x = gen_rtx_AND (vmode, dest, mask);
9877 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
9879 if (op0 != CONST0_RTX (vmode))
9881 x = gen_rtx_IOR (vmode, dest, op0);
9882 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
9886 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
9887 so we have to do two masks. */
9890 ix86_split_copysign_var (rtx operands[])
9892 enum machine_mode mode, vmode;
9893 rtx dest, scratch, op0, op1, mask, nmask, x;
9896 scratch = operands[1];
9899 nmask = operands[4];
9902 mode = GET_MODE (dest);
9903 vmode = GET_MODE (mask);
9905 if (rtx_equal_p (op0, op1))
9907 /* Shouldn't happen often (it's useless, obviously), but when it does
9908 we'd generate incorrect code if we continue below. */
9909 emit_move_insn (dest, op0);
9913 if (REG_P (mask) && REGNO (dest) == REGNO (mask)) /* alternative 0 */
9915 gcc_assert (REGNO (op1) == REGNO (scratch));
9917 x = gen_rtx_AND (vmode, scratch, mask);
9918 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
9921 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
9922 x = gen_rtx_NOT (vmode, dest);
9923 x = gen_rtx_AND (vmode, x, op0);
9924 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
9928 if (REGNO (op1) == REGNO (scratch)) /* alternative 1,3 */
9930 x = gen_rtx_AND (vmode, scratch, mask);
9932 else /* alternative 2,4 */
9934 gcc_assert (REGNO (mask) == REGNO (scratch));
9935 op1 = simplify_gen_subreg (vmode, op1, mode, 0);
9936 x = gen_rtx_AND (vmode, scratch, op1);
9938 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
9940 if (REGNO (op0) == REGNO (dest)) /* alternative 1,2 */
9942 dest = simplify_gen_subreg (vmode, op0, mode, 0);
9943 x = gen_rtx_AND (vmode, dest, nmask);
9945 else /* alternative 3,4 */
9947 gcc_assert (REGNO (nmask) == REGNO (dest));
9949 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
9950 x = gen_rtx_AND (vmode, dest, op0);
9952 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
9955 x = gen_rtx_IOR (vmode, dest, scratch);
9956 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
9959 /* Return TRUE or FALSE depending on whether the first SET in INSN
9960 has source and destination with matching CC modes, and that the
9961 CC mode is at least as constrained as REQ_MODE. */
9964 ix86_match_ccmode (rtx insn, enum machine_mode req_mode)
9967 enum machine_mode set_mode;
9969 set = PATTERN (insn);
9970 if (GET_CODE (set) == PARALLEL)
9971 set = XVECEXP (set, 0, 0);
9972 gcc_assert (GET_CODE (set) == SET);
9973 gcc_assert (GET_CODE (SET_SRC (set)) == COMPARE);
9975 set_mode = GET_MODE (SET_DEST (set));
9979 if (req_mode != CCNOmode
9980 && (req_mode != CCmode
9981 || XEXP (SET_SRC (set), 1) != const0_rtx))
9985 if (req_mode == CCGCmode)
9989 if (req_mode == CCGOCmode || req_mode == CCNOmode)
9993 if (req_mode == CCZmode)
10000 gcc_unreachable ();
10003 return (GET_MODE (SET_SRC (set)) == set_mode);
10006 /* Generate insn patterns to do an integer compare of OPERANDS. */
10009 ix86_expand_int_compare (enum rtx_code code, rtx op0, rtx op1)
10011 enum machine_mode cmpmode;
10014 cmpmode = SELECT_CC_MODE (code, op0, op1);
10015 flags = gen_rtx_REG (cmpmode, FLAGS_REG);
10017 /* This is very simple, but making the interface the same as in the
10018 FP case makes the rest of the code easier. */
10019 tmp = gen_rtx_COMPARE (cmpmode, op0, op1);
10020 emit_insn (gen_rtx_SET (VOIDmode, flags, tmp));
10022 /* Return the test that should be put into the flags user, i.e.
10023 the bcc, scc, or cmov instruction. */
10024 return gen_rtx_fmt_ee (code, VOIDmode, flags, const0_rtx);
10027 /* Figure out whether to use ordered or unordered fp comparisons.
10028 Return the appropriate mode to use. */
10031 ix86_fp_compare_mode (enum rtx_code code ATTRIBUTE_UNUSED)
10033 /* ??? In order to make all comparisons reversible, we do all comparisons
10034 non-trapping when compiling for IEEE. Once gcc is able to distinguish
10035 all forms trapping and nontrapping comparisons, we can make inequality
10036 comparisons trapping again, since it results in better code when using
10037 FCOM based compares. */
10038 return TARGET_IEEE_FP ? CCFPUmode : CCFPmode;
10042 ix86_cc_mode (enum rtx_code code, rtx op0, rtx op1)
10044 if (SCALAR_FLOAT_MODE_P (GET_MODE (op0)))
10045 return ix86_fp_compare_mode (code);
10048 /* Only zero flag is needed. */
10049 case EQ: /* ZF=0 */
10050 case NE: /* ZF!=0 */
10052 /* Codes needing carry flag. */
10053 case GEU: /* CF=0 */
10054 case GTU: /* CF=0 & ZF=0 */
10055 case LTU: /* CF=1 */
10056 case LEU: /* CF=1 | ZF=1 */
10058 /* Codes possibly doable only with sign flag when
10059 comparing against zero. */
10060 case GE: /* SF=OF or SF=0 */
10061 case LT: /* SF<>OF or SF=1 */
10062 if (op1 == const0_rtx)
10065 /* For other cases Carry flag is not required. */
10067 /* Codes doable only with sign flag when comparing
10068 against zero, but we miss jump instruction for it
10069 so we need to use relational tests against overflow
10070 that thus needs to be zero. */
10071 case GT: /* ZF=0 & SF=OF */
10072 case LE: /* ZF=1 | SF<>OF */
10073 if (op1 == const0_rtx)
10077 /* strcmp pattern do (use flags) and combine may ask us for proper
10082 gcc_unreachable ();
10086 /* Return the fixed registers used for condition codes. */
10089 ix86_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
10096 /* If two condition code modes are compatible, return a condition code
10097 mode which is compatible with both. Otherwise, return
10100 static enum machine_mode
10101 ix86_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
10106 if (GET_MODE_CLASS (m1) != MODE_CC || GET_MODE_CLASS (m2) != MODE_CC)
10109 if ((m1 == CCGCmode && m2 == CCGOCmode)
10110 || (m1 == CCGOCmode && m2 == CCGCmode))
10116 gcc_unreachable ();
10138 /* These are only compatible with themselves, which we already
10144 /* Return true if we should use an FCOMI instruction for this fp comparison. */
10147 ix86_use_fcomi_compare (enum rtx_code code ATTRIBUTE_UNUSED)
10149 enum rtx_code swapped_code = swap_condition (code);
10150 return ((ix86_fp_comparison_cost (code) == ix86_fp_comparison_fcomi_cost (code))
10151 || (ix86_fp_comparison_cost (swapped_code)
10152 == ix86_fp_comparison_fcomi_cost (swapped_code)));
10155 /* Swap, force into registers, or otherwise massage the two operands
10156 to a fp comparison. The operands are updated in place; the new
10157 comparison code is returned. */
10159 static enum rtx_code
10160 ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1)
10162 enum machine_mode fpcmp_mode = ix86_fp_compare_mode (code);
10163 rtx op0 = *pop0, op1 = *pop1;
10164 enum machine_mode op_mode = GET_MODE (op0);
10165 int is_sse = TARGET_SSE_MATH && SSE_FLOAT_MODE_P (op_mode);
10167 /* All of the unordered compare instructions only work on registers.
10168 The same is true of the fcomi compare instructions. The XFmode
10169 compare instructions require registers except when comparing
10170 against zero or when converting operand 1 from fixed point to
10174 && (fpcmp_mode == CCFPUmode
10175 || (op_mode == XFmode
10176 && ! (standard_80387_constant_p (op0) == 1
10177 || standard_80387_constant_p (op1) == 1)
10178 && GET_CODE (op1) != FLOAT)
10179 || ix86_use_fcomi_compare (code)))
10181 op0 = force_reg (op_mode, op0);
10182 op1 = force_reg (op_mode, op1);
10186 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
10187 things around if they appear profitable, otherwise force op0
10188 into a register. */
10190 if (standard_80387_constant_p (op0) == 0
10191 || (GET_CODE (op0) == MEM
10192 && ! (standard_80387_constant_p (op1) == 0
10193 || GET_CODE (op1) == MEM)))
10196 tmp = op0, op0 = op1, op1 = tmp;
10197 code = swap_condition (code);
10200 if (GET_CODE (op0) != REG)
10201 op0 = force_reg (op_mode, op0);
10203 if (CONSTANT_P (op1))
10205 int tmp = standard_80387_constant_p (op1);
10207 op1 = validize_mem (force_const_mem (op_mode, op1));
10211 op1 = force_reg (op_mode, op1);
10214 op1 = force_reg (op_mode, op1);
10218 /* Try to rearrange the comparison to make it cheaper. */
10219 if (ix86_fp_comparison_cost (code)
10220 > ix86_fp_comparison_cost (swap_condition (code))
10221 && (GET_CODE (op1) == REG || !no_new_pseudos))
10224 tmp = op0, op0 = op1, op1 = tmp;
10225 code = swap_condition (code);
10226 if (GET_CODE (op0) != REG)
10227 op0 = force_reg (op_mode, op0);
10235 /* Convert comparison codes we use to represent FP comparison to integer
10236 code that will result in proper branch. Return UNKNOWN if no such code
10240 ix86_fp_compare_code_to_integer (enum rtx_code code)
10269 /* Split comparison code CODE into comparisons we can do using branch
10270 instructions. BYPASS_CODE is comparison code for branch that will
10271 branch around FIRST_CODE and SECOND_CODE. If some of branches
10272 is not required, set value to UNKNOWN.
10273 We never require more than two branches. */
10276 ix86_fp_comparison_codes (enum rtx_code code, enum rtx_code *bypass_code,
10277 enum rtx_code *first_code,
10278 enum rtx_code *second_code)
10280 *first_code = code;
10281 *bypass_code = UNKNOWN;
10282 *second_code = UNKNOWN;
10284 /* The fcomi comparison sets flags as follows:
10294 case GT: /* GTU - CF=0 & ZF=0 */
10295 case GE: /* GEU - CF=0 */
10296 case ORDERED: /* PF=0 */
10297 case UNORDERED: /* PF=1 */
10298 case UNEQ: /* EQ - ZF=1 */
10299 case UNLT: /* LTU - CF=1 */
10300 case UNLE: /* LEU - CF=1 | ZF=1 */
10301 case LTGT: /* EQ - ZF=0 */
10303 case LT: /* LTU - CF=1 - fails on unordered */
10304 *first_code = UNLT;
10305 *bypass_code = UNORDERED;
10307 case LE: /* LEU - CF=1 | ZF=1 - fails on unordered */
10308 *first_code = UNLE;
10309 *bypass_code = UNORDERED;
10311 case EQ: /* EQ - ZF=1 - fails on unordered */
10312 *first_code = UNEQ;
10313 *bypass_code = UNORDERED;
10315 case NE: /* NE - ZF=0 - fails on unordered */
10316 *first_code = LTGT;
10317 *second_code = UNORDERED;
10319 case UNGE: /* GEU - CF=0 - fails on unordered */
10321 *second_code = UNORDERED;
10323 case UNGT: /* GTU - CF=0 & ZF=0 - fails on unordered */
10325 *second_code = UNORDERED;
10328 gcc_unreachable ();
10330 if (!TARGET_IEEE_FP)
10332 *second_code = UNKNOWN;
10333 *bypass_code = UNKNOWN;
10337 /* Return cost of comparison done fcom + arithmetics operations on AX.
10338 All following functions do use number of instructions as a cost metrics.
10339 In future this should be tweaked to compute bytes for optimize_size and
10340 take into account performance of various instructions on various CPUs. */
10342 ix86_fp_comparison_arithmetics_cost (enum rtx_code code)
10344 if (!TARGET_IEEE_FP)
10346 /* The cost of code output by ix86_expand_fp_compare. */
10370 gcc_unreachable ();
10374 /* Return cost of comparison done using fcomi operation.
10375 See ix86_fp_comparison_arithmetics_cost for the metrics. */
10377 ix86_fp_comparison_fcomi_cost (enum rtx_code code)
10379 enum rtx_code bypass_code, first_code, second_code;
10380 /* Return arbitrarily high cost when instruction is not supported - this
10381 prevents gcc from using it. */
10384 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
10385 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 2;
10388 /* Return cost of comparison done using sahf operation.
10389 See ix86_fp_comparison_arithmetics_cost for the metrics. */
10391 ix86_fp_comparison_sahf_cost (enum rtx_code code)
10393 enum rtx_code bypass_code, first_code, second_code;
10394 /* Return arbitrarily high cost when instruction is not preferred - this
10395 avoids gcc from using it. */
10396 if (!TARGET_USE_SAHF && !optimize_size)
10398 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
10399 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 3;
10402 /* Compute cost of the comparison done using any method.
10403 See ix86_fp_comparison_arithmetics_cost for the metrics. */
10405 ix86_fp_comparison_cost (enum rtx_code code)
10407 int fcomi_cost, sahf_cost, arithmetics_cost = 1024;
10410 fcomi_cost = ix86_fp_comparison_fcomi_cost (code);
10411 sahf_cost = ix86_fp_comparison_sahf_cost (code);
10413 min = arithmetics_cost = ix86_fp_comparison_arithmetics_cost (code);
10414 if (min > sahf_cost)
10416 if (min > fcomi_cost)
10421 /* Generate insn patterns to do a floating point compare of OPERANDS. */
10424 ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch,
10425 rtx *second_test, rtx *bypass_test)
10427 enum machine_mode fpcmp_mode, intcmp_mode;
10429 int cost = ix86_fp_comparison_cost (code);
10430 enum rtx_code bypass_code, first_code, second_code;
10432 fpcmp_mode = ix86_fp_compare_mode (code);
10433 code = ix86_prepare_fp_compare_args (code, &op0, &op1);
10436 *second_test = NULL_RTX;
10438 *bypass_test = NULL_RTX;
10440 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
10442 /* Do fcomi/sahf based test when profitable. */
10443 if ((bypass_code == UNKNOWN || bypass_test)
10444 && (second_code == UNKNOWN || second_test)
10445 && ix86_fp_comparison_arithmetics_cost (code) > cost)
10449 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
10450 tmp = gen_rtx_SET (VOIDmode, gen_rtx_REG (fpcmp_mode, FLAGS_REG),
10456 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
10457 tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW);
10459 scratch = gen_reg_rtx (HImode);
10460 emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
10461 emit_insn (gen_x86_sahf_1 (scratch));
10464 /* The FP codes work out to act like unsigned. */
10465 intcmp_mode = fpcmp_mode;
10467 if (bypass_code != UNKNOWN)
10468 *bypass_test = gen_rtx_fmt_ee (bypass_code, VOIDmode,
10469 gen_rtx_REG (intcmp_mode, FLAGS_REG),
10471 if (second_code != UNKNOWN)
10472 *second_test = gen_rtx_fmt_ee (second_code, VOIDmode,
10473 gen_rtx_REG (intcmp_mode, FLAGS_REG),
10478 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
10479 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
10480 tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW);
10482 scratch = gen_reg_rtx (HImode);
10483 emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
10485 /* In the unordered case, we have to check C2 for NaN's, which
10486 doesn't happen to work out to anything nice combination-wise.
10487 So do some bit twiddling on the value we've got in AH to come
10488 up with an appropriate set of condition codes. */
10490 intcmp_mode = CCNOmode;
10495 if (code == GT || !TARGET_IEEE_FP)
10497 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
10502 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
10503 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
10504 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x44)));
10505 intcmp_mode = CCmode;
10511 if (code == LT && TARGET_IEEE_FP)
10513 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
10514 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x01)));
10515 intcmp_mode = CCmode;
10520 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x01)));
10526 if (code == GE || !TARGET_IEEE_FP)
10528 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x05)));
10533 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
10534 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
10541 if (code == LE && TARGET_IEEE_FP)
10543 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
10544 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
10545 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
10546 intcmp_mode = CCmode;
10551 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
10557 if (code == EQ && TARGET_IEEE_FP)
10559 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
10560 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
10561 intcmp_mode = CCmode;
10566 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
10573 if (code == NE && TARGET_IEEE_FP)
10575 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
10576 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
10582 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
10588 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
10592 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
10597 gcc_unreachable ();
10601 /* Return the test that should be put into the flags user, i.e.
10602 the bcc, scc, or cmov instruction. */
10603 return gen_rtx_fmt_ee (code, VOIDmode,
10604 gen_rtx_REG (intcmp_mode, FLAGS_REG),
10609 ix86_expand_compare (enum rtx_code code, rtx *second_test, rtx *bypass_test)
10612 op0 = ix86_compare_op0;
10613 op1 = ix86_compare_op1;
10616 *second_test = NULL_RTX;
10618 *bypass_test = NULL_RTX;
10620 if (ix86_compare_emitted)
10622 ret = gen_rtx_fmt_ee (code, VOIDmode, ix86_compare_emitted, const0_rtx);
10623 ix86_compare_emitted = NULL_RTX;
10625 else if (SCALAR_FLOAT_MODE_P (GET_MODE (op0)))
10626 ret = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
10627 second_test, bypass_test);
10629 ret = ix86_expand_int_compare (code, op0, op1);
10634 /* Return true if the CODE will result in nontrivial jump sequence. */
10636 ix86_fp_jump_nontrivial_p (enum rtx_code code)
10638 enum rtx_code bypass_code, first_code, second_code;
10641 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
10642 return bypass_code != UNKNOWN || second_code != UNKNOWN;
10646 ix86_expand_branch (enum rtx_code code, rtx label)
10650 /* If we have emitted a compare insn, go straight to simple.
10651 ix86_expand_compare won't emit anything if ix86_compare_emitted
10653 if (ix86_compare_emitted)
10656 switch (GET_MODE (ix86_compare_op0))
10662 tmp = ix86_expand_compare (code, NULL, NULL);
10663 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
10664 gen_rtx_LABEL_REF (VOIDmode, label),
10666 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
10675 enum rtx_code bypass_code, first_code, second_code;
10677 code = ix86_prepare_fp_compare_args (code, &ix86_compare_op0,
10678 &ix86_compare_op1);
10680 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
10682 /* Check whether we will use the natural sequence with one jump. If
10683 so, we can expand jump early. Otherwise delay expansion by
10684 creating compound insn to not confuse optimizers. */
10685 if (bypass_code == UNKNOWN && second_code == UNKNOWN
10688 ix86_split_fp_branch (code, ix86_compare_op0, ix86_compare_op1,
10689 gen_rtx_LABEL_REF (VOIDmode, label),
10690 pc_rtx, NULL_RTX, NULL_RTX);
10694 tmp = gen_rtx_fmt_ee (code, VOIDmode,
10695 ix86_compare_op0, ix86_compare_op1);
10696 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
10697 gen_rtx_LABEL_REF (VOIDmode, label),
10699 tmp = gen_rtx_SET (VOIDmode, pc_rtx, tmp);
10701 use_fcomi = ix86_use_fcomi_compare (code);
10702 vec = rtvec_alloc (3 + !use_fcomi);
10703 RTVEC_ELT (vec, 0) = tmp;
10705 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, 18));
10707 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, 17));
10710 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (HImode));
10712 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, vec));
10721 /* Expand DImode branch into multiple compare+branch. */
10723 rtx lo[2], hi[2], label2;
10724 enum rtx_code code1, code2, code3;
10725 enum machine_mode submode;
10727 if (CONSTANT_P (ix86_compare_op0) && ! CONSTANT_P (ix86_compare_op1))
10729 tmp = ix86_compare_op0;
10730 ix86_compare_op0 = ix86_compare_op1;
10731 ix86_compare_op1 = tmp;
10732 code = swap_condition (code);
10734 if (GET_MODE (ix86_compare_op0) == DImode)
10736 split_di (&ix86_compare_op0, 1, lo+0, hi+0);
10737 split_di (&ix86_compare_op1, 1, lo+1, hi+1);
10742 split_ti (&ix86_compare_op0, 1, lo+0, hi+0);
10743 split_ti (&ix86_compare_op1, 1, lo+1, hi+1);
10747 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
10748 avoid two branches. This costs one extra insn, so disable when
10749 optimizing for size. */
10751 if ((code == EQ || code == NE)
10753 || hi[1] == const0_rtx || lo[1] == const0_rtx))
10758 if (hi[1] != const0_rtx)
10759 xor1 = expand_binop (submode, xor_optab, xor1, hi[1],
10760 NULL_RTX, 0, OPTAB_WIDEN);
10763 if (lo[1] != const0_rtx)
10764 xor0 = expand_binop (submode, xor_optab, xor0, lo[1],
10765 NULL_RTX, 0, OPTAB_WIDEN);
10767 tmp = expand_binop (submode, ior_optab, xor1, xor0,
10768 NULL_RTX, 0, OPTAB_WIDEN);
10770 ix86_compare_op0 = tmp;
10771 ix86_compare_op1 = const0_rtx;
10772 ix86_expand_branch (code, label);
10776 /* Otherwise, if we are doing less-than or greater-or-equal-than,
10777 op1 is a constant and the low word is zero, then we can just
10778 examine the high word. */
10780 if (GET_CODE (hi[1]) == CONST_INT && lo[1] == const0_rtx)
10783 case LT: case LTU: case GE: case GEU:
10784 ix86_compare_op0 = hi[0];
10785 ix86_compare_op1 = hi[1];
10786 ix86_expand_branch (code, label);
10792 /* Otherwise, we need two or three jumps. */
10794 label2 = gen_label_rtx ();
10797 code2 = swap_condition (code);
10798 code3 = unsigned_condition (code);
10802 case LT: case GT: case LTU: case GTU:
10805 case LE: code1 = LT; code2 = GT; break;
10806 case GE: code1 = GT; code2 = LT; break;
10807 case LEU: code1 = LTU; code2 = GTU; break;
10808 case GEU: code1 = GTU; code2 = LTU; break;
10810 case EQ: code1 = UNKNOWN; code2 = NE; break;
10811 case NE: code2 = UNKNOWN; break;
10814 gcc_unreachable ();
10819 * if (hi(a) < hi(b)) goto true;
10820 * if (hi(a) > hi(b)) goto false;
10821 * if (lo(a) < lo(b)) goto true;
10825 ix86_compare_op0 = hi[0];
10826 ix86_compare_op1 = hi[1];
10828 if (code1 != UNKNOWN)
10829 ix86_expand_branch (code1, label);
10830 if (code2 != UNKNOWN)
10831 ix86_expand_branch (code2, label2);
10833 ix86_compare_op0 = lo[0];
10834 ix86_compare_op1 = lo[1];
10835 ix86_expand_branch (code3, label);
10837 if (code2 != UNKNOWN)
10838 emit_label (label2);
10843 gcc_unreachable ();
10847 /* Split branch based on floating point condition. */
10849 ix86_split_fp_branch (enum rtx_code code, rtx op1, rtx op2,
10850 rtx target1, rtx target2, rtx tmp, rtx pushed)
10852 rtx second, bypass;
10853 rtx label = NULL_RTX;
10855 int bypass_probability = -1, second_probability = -1, probability = -1;
10858 if (target2 != pc_rtx)
10861 code = reverse_condition_maybe_unordered (code);
10866 condition = ix86_expand_fp_compare (code, op1, op2,
10867 tmp, &second, &bypass);
10869 /* Remove pushed operand from stack. */
10871 ix86_free_from_memory (GET_MODE (pushed));
10873 if (split_branch_probability >= 0)
10875 /* Distribute the probabilities across the jumps.
10876 Assume the BYPASS and SECOND to be always test
10878 probability = split_branch_probability;
10880 /* Value of 1 is low enough to make no need for probability
10881 to be updated. Later we may run some experiments and see
10882 if unordered values are more frequent in practice. */
10884 bypass_probability = 1;
10886 second_probability = 1;
10888 if (bypass != NULL_RTX)
10890 label = gen_label_rtx ();
10891 i = emit_jump_insn (gen_rtx_SET
10893 gen_rtx_IF_THEN_ELSE (VOIDmode,
10895 gen_rtx_LABEL_REF (VOIDmode,
10898 if (bypass_probability >= 0)
10900 = gen_rtx_EXPR_LIST (REG_BR_PROB,
10901 GEN_INT (bypass_probability),
10904 i = emit_jump_insn (gen_rtx_SET
10906 gen_rtx_IF_THEN_ELSE (VOIDmode,
10907 condition, target1, target2)));
10908 if (probability >= 0)
10910 = gen_rtx_EXPR_LIST (REG_BR_PROB,
10911 GEN_INT (probability),
10913 if (second != NULL_RTX)
10915 i = emit_jump_insn (gen_rtx_SET
10917 gen_rtx_IF_THEN_ELSE (VOIDmode, second, target1,
10919 if (second_probability >= 0)
10921 = gen_rtx_EXPR_LIST (REG_BR_PROB,
10922 GEN_INT (second_probability),
10925 if (label != NULL_RTX)
10926 emit_label (label);
10930 ix86_expand_setcc (enum rtx_code code, rtx dest)
10932 rtx ret, tmp, tmpreg, equiv;
10933 rtx second_test, bypass_test;
10935 if (GET_MODE (ix86_compare_op0) == (TARGET_64BIT ? TImode : DImode))
10936 return 0; /* FAIL */
10938 gcc_assert (GET_MODE (dest) == QImode);
10940 ret = ix86_expand_compare (code, &second_test, &bypass_test);
10941 PUT_MODE (ret, QImode);
10946 emit_insn (gen_rtx_SET (VOIDmode, tmp, ret));
10947 if (bypass_test || second_test)
10949 rtx test = second_test;
10951 rtx tmp2 = gen_reg_rtx (QImode);
10954 gcc_assert (!second_test);
10955 test = bypass_test;
10957 PUT_CODE (test, reverse_condition_maybe_unordered (GET_CODE (test)));
10959 PUT_MODE (test, QImode);
10960 emit_insn (gen_rtx_SET (VOIDmode, tmp2, test));
10963 emit_insn (gen_andqi3 (tmp, tmpreg, tmp2));
10965 emit_insn (gen_iorqi3 (tmp, tmpreg, tmp2));
10968 /* Attach a REG_EQUAL note describing the comparison result. */
10969 if (ix86_compare_op0 && ix86_compare_op1)
10971 equiv = simplify_gen_relational (code, QImode,
10972 GET_MODE (ix86_compare_op0),
10973 ix86_compare_op0, ix86_compare_op1);
10974 set_unique_reg_note (get_last_insn (), REG_EQUAL, equiv);
10977 return 1; /* DONE */
10980 /* Expand comparison setting or clearing carry flag. Return true when
10981 successful and set pop for the operation. */
10983 ix86_expand_carry_flag_compare (enum rtx_code code, rtx op0, rtx op1, rtx *pop)
10985 enum machine_mode mode =
10986 GET_MODE (op0) != VOIDmode ? GET_MODE (op0) : GET_MODE (op1);
10988 /* Do not handle DImode compares that go through special path. Also we can't
10989 deal with FP compares yet. This is possible to add. */
10990 if (mode == (TARGET_64BIT ? TImode : DImode))
10992 if (FLOAT_MODE_P (mode))
10994 rtx second_test = NULL, bypass_test = NULL;
10995 rtx compare_op, compare_seq;
10997 /* Shortcut: following common codes never translate into carry flag compares. */
10998 if (code == EQ || code == NE || code == UNEQ || code == LTGT
10999 || code == ORDERED || code == UNORDERED)
11002 /* These comparisons require zero flag; swap operands so they won't. */
11003 if ((code == GT || code == UNLE || code == LE || code == UNGT)
11004 && !TARGET_IEEE_FP)
11009 code = swap_condition (code);
11012 /* Try to expand the comparison and verify that we end up with carry flag
11013 based comparison. This is fails to be true only when we decide to expand
11014 comparison using arithmetic that is not too common scenario. */
11016 compare_op = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
11017 &second_test, &bypass_test);
11018 compare_seq = get_insns ();
11021 if (second_test || bypass_test)
11023 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
11024 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
11025 code = ix86_fp_compare_code_to_integer (GET_CODE (compare_op));
11027 code = GET_CODE (compare_op);
11028 if (code != LTU && code != GEU)
11030 emit_insn (compare_seq);
11034 if (!INTEGRAL_MODE_P (mode))
11042 /* Convert a==0 into (unsigned)a<1. */
11045 if (op1 != const0_rtx)
11048 code = (code == EQ ? LTU : GEU);
11051 /* Convert a>b into b<a or a>=b-1. */
11054 if (GET_CODE (op1) == CONST_INT)
11056 op1 = gen_int_mode (INTVAL (op1) + 1, GET_MODE (op0));
11057 /* Bail out on overflow. We still can swap operands but that
11058 would force loading of the constant into register. */
11059 if (op1 == const0_rtx
11060 || !x86_64_immediate_operand (op1, GET_MODE (op1)))
11062 code = (code == GTU ? GEU : LTU);
11069 code = (code == GTU ? LTU : GEU);
11073 /* Convert a>=0 into (unsigned)a<0x80000000. */
11076 if (mode == DImode || op1 != const0_rtx)
11078 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
11079 code = (code == LT ? GEU : LTU);
11083 if (mode == DImode || op1 != constm1_rtx)
11085 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
11086 code = (code == LE ? GEU : LTU);
11092 /* Swapping operands may cause constant to appear as first operand. */
11093 if (!nonimmediate_operand (op0, VOIDmode))
11095 if (no_new_pseudos)
11097 op0 = force_reg (mode, op0);
11099 ix86_compare_op0 = op0;
11100 ix86_compare_op1 = op1;
11101 *pop = ix86_expand_compare (code, NULL, NULL);
11102 gcc_assert (GET_CODE (*pop) == LTU || GET_CODE (*pop) == GEU);
11107 ix86_expand_int_movcc (rtx operands[])
11109 enum rtx_code code = GET_CODE (operands[1]), compare_code;
11110 rtx compare_seq, compare_op;
11111 rtx second_test, bypass_test;
11112 enum machine_mode mode = GET_MODE (operands[0]);
11113 bool sign_bit_compare_p = false;;
11116 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
11117 compare_seq = get_insns ();
11120 compare_code = GET_CODE (compare_op);
11122 if ((ix86_compare_op1 == const0_rtx && (code == GE || code == LT))
11123 || (ix86_compare_op1 == constm1_rtx && (code == GT || code == LE)))
11124 sign_bit_compare_p = true;
11126 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
11127 HImode insns, we'd be swallowed in word prefix ops. */
11129 if ((mode != HImode || TARGET_FAST_PREFIX)
11130 && (mode != (TARGET_64BIT ? TImode : DImode))
11131 && GET_CODE (operands[2]) == CONST_INT
11132 && GET_CODE (operands[3]) == CONST_INT)
11134 rtx out = operands[0];
11135 HOST_WIDE_INT ct = INTVAL (operands[2]);
11136 HOST_WIDE_INT cf = INTVAL (operands[3]);
11137 HOST_WIDE_INT diff;
11140 /* Sign bit compares are better done using shifts than we do by using
11142 if (sign_bit_compare_p
11143 || ix86_expand_carry_flag_compare (code, ix86_compare_op0,
11144 ix86_compare_op1, &compare_op))
11146 /* Detect overlap between destination and compare sources. */
11149 if (!sign_bit_compare_p)
11151 bool fpcmp = false;
11153 compare_code = GET_CODE (compare_op);
11155 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
11156 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
11159 compare_code = ix86_fp_compare_code_to_integer (compare_code);
11162 /* To simplify rest of code, restrict to the GEU case. */
11163 if (compare_code == LTU)
11165 HOST_WIDE_INT tmp = ct;
11168 compare_code = reverse_condition (compare_code);
11169 code = reverse_condition (code);
11174 PUT_CODE (compare_op,
11175 reverse_condition_maybe_unordered
11176 (GET_CODE (compare_op)));
11178 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
11182 if (reg_overlap_mentioned_p (out, ix86_compare_op0)
11183 || reg_overlap_mentioned_p (out, ix86_compare_op1))
11184 tmp = gen_reg_rtx (mode);
11186 if (mode == DImode)
11187 emit_insn (gen_x86_movdicc_0_m1_rex64 (tmp, compare_op));
11189 emit_insn (gen_x86_movsicc_0_m1 (gen_lowpart (SImode, tmp), compare_op));
11193 if (code == GT || code == GE)
11194 code = reverse_condition (code);
11197 HOST_WIDE_INT tmp = ct;
11202 tmp = emit_store_flag (tmp, code, ix86_compare_op0,
11203 ix86_compare_op1, VOIDmode, 0, -1);
11216 tmp = expand_simple_binop (mode, PLUS,
11218 copy_rtx (tmp), 1, OPTAB_DIRECT);
11229 tmp = expand_simple_binop (mode, IOR,
11231 copy_rtx (tmp), 1, OPTAB_DIRECT);
11233 else if (diff == -1 && ct)
11243 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
11245 tmp = expand_simple_binop (mode, PLUS,
11246 copy_rtx (tmp), GEN_INT (cf),
11247 copy_rtx (tmp), 1, OPTAB_DIRECT);
11255 * andl cf - ct, dest
11265 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
11268 tmp = expand_simple_binop (mode, AND,
11270 gen_int_mode (cf - ct, mode),
11271 copy_rtx (tmp), 1, OPTAB_DIRECT);
11273 tmp = expand_simple_binop (mode, PLUS,
11274 copy_rtx (tmp), GEN_INT (ct),
11275 copy_rtx (tmp), 1, OPTAB_DIRECT);
11278 if (!rtx_equal_p (tmp, out))
11279 emit_move_insn (copy_rtx (out), copy_rtx (tmp));
11281 return 1; /* DONE */
11287 tmp = ct, ct = cf, cf = tmp;
11289 if (FLOAT_MODE_P (GET_MODE (ix86_compare_op0)))
11291 /* We may be reversing unordered compare to normal compare, that
11292 is not valid in general (we may convert non-trapping condition
11293 to trapping one), however on i386 we currently emit all
11294 comparisons unordered. */
11295 compare_code = reverse_condition_maybe_unordered (compare_code);
11296 code = reverse_condition_maybe_unordered (code);
11300 compare_code = reverse_condition (compare_code);
11301 code = reverse_condition (code);
11305 compare_code = UNKNOWN;
11306 if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_INT
11307 && GET_CODE (ix86_compare_op1) == CONST_INT)
11309 if (ix86_compare_op1 == const0_rtx
11310 && (code == LT || code == GE))
11311 compare_code = code;
11312 else if (ix86_compare_op1 == constm1_rtx)
11316 else if (code == GT)
11321 /* Optimize dest = (op0 < 0) ? -1 : cf. */
11322 if (compare_code != UNKNOWN
11323 && GET_MODE (ix86_compare_op0) == GET_MODE (out)
11324 && (cf == -1 || ct == -1))
11326 /* If lea code below could be used, only optimize
11327 if it results in a 2 insn sequence. */
11329 if (! (diff == 1 || diff == 2 || diff == 4 || diff == 8
11330 || diff == 3 || diff == 5 || diff == 9)
11331 || (compare_code == LT && ct == -1)
11332 || (compare_code == GE && cf == -1))
11335 * notl op1 (if necessary)
11343 code = reverse_condition (code);
11346 out = emit_store_flag (out, code, ix86_compare_op0,
11347 ix86_compare_op1, VOIDmode, 0, -1);
11349 out = expand_simple_binop (mode, IOR,
11351 out, 1, OPTAB_DIRECT);
11352 if (out != operands[0])
11353 emit_move_insn (operands[0], out);
11355 return 1; /* DONE */
11360 if ((diff == 1 || diff == 2 || diff == 4 || diff == 8
11361 || diff == 3 || diff == 5 || diff == 9)
11362 && ((mode != QImode && mode != HImode) || !TARGET_PARTIAL_REG_STALL)
11364 || x86_64_immediate_operand (GEN_INT (cf), VOIDmode)))
11370 * lea cf(dest*(ct-cf)),dest
11374 * This also catches the degenerate setcc-only case.
11380 out = emit_store_flag (out, code, ix86_compare_op0,
11381 ix86_compare_op1, VOIDmode, 0, 1);
11384 /* On x86_64 the lea instruction operates on Pmode, so we need
11385 to get arithmetics done in proper mode to match. */
11387 tmp = copy_rtx (out);
11391 out1 = copy_rtx (out);
11392 tmp = gen_rtx_MULT (mode, out1, GEN_INT (diff & ~1));
11396 tmp = gen_rtx_PLUS (mode, tmp, out1);
11402 tmp = gen_rtx_PLUS (mode, tmp, GEN_INT (cf));
11405 if (!rtx_equal_p (tmp, out))
11408 out = force_operand (tmp, copy_rtx (out));
11410 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (out), copy_rtx (tmp)));
11412 if (!rtx_equal_p (out, operands[0]))
11413 emit_move_insn (operands[0], copy_rtx (out));
11415 return 1; /* DONE */
11419 * General case: Jumpful:
11420 * xorl dest,dest cmpl op1, op2
11421 * cmpl op1, op2 movl ct, dest
11422 * setcc dest jcc 1f
11423 * decl dest movl cf, dest
11424 * andl (cf-ct),dest 1:
11427 * Size 20. Size 14.
11429 * This is reasonably steep, but branch mispredict costs are
11430 * high on modern cpus, so consider failing only if optimizing
11434 if ((!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
11435 && BRANCH_COST >= 2)
11441 if (FLOAT_MODE_P (GET_MODE (ix86_compare_op0)))
11442 /* We may be reversing unordered compare to normal compare,
11443 that is not valid in general (we may convert non-trapping
11444 condition to trapping one), however on i386 we currently
11445 emit all comparisons unordered. */
11446 code = reverse_condition_maybe_unordered (code);
11449 code = reverse_condition (code);
11450 if (compare_code != UNKNOWN)
11451 compare_code = reverse_condition (compare_code);
11455 if (compare_code != UNKNOWN)
11457 /* notl op1 (if needed)
11462 For x < 0 (resp. x <= -1) there will be no notl,
11463 so if possible swap the constants to get rid of the
11465 True/false will be -1/0 while code below (store flag
11466 followed by decrement) is 0/-1, so the constants need
11467 to be exchanged once more. */
11469 if (compare_code == GE || !cf)
11471 code = reverse_condition (code);
11476 HOST_WIDE_INT tmp = cf;
11481 out = emit_store_flag (out, code, ix86_compare_op0,
11482 ix86_compare_op1, VOIDmode, 0, -1);
11486 out = emit_store_flag (out, code, ix86_compare_op0,
11487 ix86_compare_op1, VOIDmode, 0, 1);
11489 out = expand_simple_binop (mode, PLUS, copy_rtx (out), constm1_rtx,
11490 copy_rtx (out), 1, OPTAB_DIRECT);
11493 out = expand_simple_binop (mode, AND, copy_rtx (out),
11494 gen_int_mode (cf - ct, mode),
11495 copy_rtx (out), 1, OPTAB_DIRECT);
11497 out = expand_simple_binop (mode, PLUS, copy_rtx (out), GEN_INT (ct),
11498 copy_rtx (out), 1, OPTAB_DIRECT);
11499 if (!rtx_equal_p (out, operands[0]))
11500 emit_move_insn (operands[0], copy_rtx (out));
11502 return 1; /* DONE */
11506 if (!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
11508 /* Try a few things more with specific constants and a variable. */
11511 rtx var, orig_out, out, tmp;
11513 if (BRANCH_COST <= 2)
11514 return 0; /* FAIL */
11516 /* If one of the two operands is an interesting constant, load a
11517 constant with the above and mask it in with a logical operation. */
11519 if (GET_CODE (operands[2]) == CONST_INT)
11522 if (INTVAL (operands[2]) == 0 && operands[3] != constm1_rtx)
11523 operands[3] = constm1_rtx, op = and_optab;
11524 else if (INTVAL (operands[2]) == -1 && operands[3] != const0_rtx)
11525 operands[3] = const0_rtx, op = ior_optab;
11527 return 0; /* FAIL */
11529 else if (GET_CODE (operands[3]) == CONST_INT)
11532 if (INTVAL (operands[3]) == 0 && operands[2] != constm1_rtx)
11533 operands[2] = constm1_rtx, op = and_optab;
11534 else if (INTVAL (operands[3]) == -1 && operands[3] != const0_rtx)
11535 operands[2] = const0_rtx, op = ior_optab;
11537 return 0; /* FAIL */
11540 return 0; /* FAIL */
11542 orig_out = operands[0];
11543 tmp = gen_reg_rtx (mode);
11546 /* Recurse to get the constant loaded. */
11547 if (ix86_expand_int_movcc (operands) == 0)
11548 return 0; /* FAIL */
11550 /* Mask in the interesting variable. */
11551 out = expand_binop (mode, op, var, tmp, orig_out, 0,
11553 if (!rtx_equal_p (out, orig_out))
11554 emit_move_insn (copy_rtx (orig_out), copy_rtx (out));
11556 return 1; /* DONE */
11560 * For comparison with above,
11570 if (! nonimmediate_operand (operands[2], mode))
11571 operands[2] = force_reg (mode, operands[2]);
11572 if (! nonimmediate_operand (operands[3], mode))
11573 operands[3] = force_reg (mode, operands[3]);
11575 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
11577 rtx tmp = gen_reg_rtx (mode);
11578 emit_move_insn (tmp, operands[3]);
11581 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
11583 rtx tmp = gen_reg_rtx (mode);
11584 emit_move_insn (tmp, operands[2]);
11588 if (! register_operand (operands[2], VOIDmode)
11590 || ! register_operand (operands[3], VOIDmode)))
11591 operands[2] = force_reg (mode, operands[2]);
11594 && ! register_operand (operands[3], VOIDmode))
11595 operands[3] = force_reg (mode, operands[3]);
11597 emit_insn (compare_seq);
11598 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
11599 gen_rtx_IF_THEN_ELSE (mode,
11600 compare_op, operands[2],
11603 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
11604 gen_rtx_IF_THEN_ELSE (mode,
11606 copy_rtx (operands[3]),
11607 copy_rtx (operands[0]))));
11609 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
11610 gen_rtx_IF_THEN_ELSE (mode,
11612 copy_rtx (operands[2]),
11613 copy_rtx (operands[0]))));
11615 return 1; /* DONE */
11618 /* Swap, force into registers, or otherwise massage the two operands
11619 to an sse comparison with a mask result. Thus we differ a bit from
11620 ix86_prepare_fp_compare_args which expects to produce a flags result.
11622 The DEST operand exists to help determine whether to commute commutative
11623 operators. The POP0/POP1 operands are updated in place. The new
11624 comparison code is returned, or UNKNOWN if not implementable. */
11626 static enum rtx_code
11627 ix86_prepare_sse_fp_compare_args (rtx dest, enum rtx_code code,
11628 rtx *pop0, rtx *pop1)
11636 /* We have no LTGT as an operator. We could implement it with
11637 NE & ORDERED, but this requires an extra temporary. It's
11638 not clear that it's worth it. */
11645 /* These are supported directly. */
11652 /* For commutative operators, try to canonicalize the destination
11653 operand to be first in the comparison - this helps reload to
11654 avoid extra moves. */
11655 if (!dest || !rtx_equal_p (dest, *pop1))
11663 /* These are not supported directly. Swap the comparison operands
11664 to transform into something that is supported. */
11668 code = swap_condition (code);
11672 gcc_unreachable ();
11678 /* Detect conditional moves that exactly match min/max operational
11679 semantics. Note that this is IEEE safe, as long as we don't
11680 interchange the operands.
11682 Returns FALSE if this conditional move doesn't match a MIN/MAX,
11683 and TRUE if the operation is successful and instructions are emitted. */
11686 ix86_expand_sse_fp_minmax (rtx dest, enum rtx_code code, rtx cmp_op0,
11687 rtx cmp_op1, rtx if_true, rtx if_false)
11689 enum machine_mode mode;
11695 else if (code == UNGE)
11698 if_true = if_false;
11704 if (rtx_equal_p (cmp_op0, if_true) && rtx_equal_p (cmp_op1, if_false))
11706 else if (rtx_equal_p (cmp_op1, if_true) && rtx_equal_p (cmp_op0, if_false))
11711 mode = GET_MODE (dest);
11713 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
11714 but MODE may be a vector mode and thus not appropriate. */
11715 if (!flag_finite_math_only || !flag_unsafe_math_optimizations)
11717 int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX;
11720 if_true = force_reg (mode, if_true);
11721 v = gen_rtvec (2, if_true, if_false);
11722 tmp = gen_rtx_UNSPEC (mode, v, u);
11726 code = is_min ? SMIN : SMAX;
11727 tmp = gen_rtx_fmt_ee (code, mode, if_true, if_false);
11730 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
11734 /* Expand an sse vector comparison. Return the register with the result. */
11737 ix86_expand_sse_cmp (rtx dest, enum rtx_code code, rtx cmp_op0, rtx cmp_op1,
11738 rtx op_true, rtx op_false)
11740 enum machine_mode mode = GET_MODE (dest);
11743 cmp_op0 = force_reg (mode, cmp_op0);
11744 if (!nonimmediate_operand (cmp_op1, mode))
11745 cmp_op1 = force_reg (mode, cmp_op1);
11748 || reg_overlap_mentioned_p (dest, op_true)
11749 || reg_overlap_mentioned_p (dest, op_false))
11750 dest = gen_reg_rtx (mode);
11752 x = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
11753 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
11758 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
11759 operations. This is used for both scalar and vector conditional moves. */
11762 ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false)
11764 enum machine_mode mode = GET_MODE (dest);
11767 if (op_false == CONST0_RTX (mode))
11769 op_true = force_reg (mode, op_true);
11770 x = gen_rtx_AND (mode, cmp, op_true);
11771 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
11773 else if (op_true == CONST0_RTX (mode))
11775 op_false = force_reg (mode, op_false);
11776 x = gen_rtx_NOT (mode, cmp);
11777 x = gen_rtx_AND (mode, x, op_false);
11778 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
11782 op_true = force_reg (mode, op_true);
11783 op_false = force_reg (mode, op_false);
11785 t2 = gen_reg_rtx (mode);
11787 t3 = gen_reg_rtx (mode);
11791 x = gen_rtx_AND (mode, op_true, cmp);
11792 emit_insn (gen_rtx_SET (VOIDmode, t2, x));
11794 x = gen_rtx_NOT (mode, cmp);
11795 x = gen_rtx_AND (mode, x, op_false);
11796 emit_insn (gen_rtx_SET (VOIDmode, t3, x));
11798 x = gen_rtx_IOR (mode, t3, t2);
11799 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
11803 /* Expand a floating-point conditional move. Return true if successful. */
11806 ix86_expand_fp_movcc (rtx operands[])
11808 enum machine_mode mode = GET_MODE (operands[0]);
11809 enum rtx_code code = GET_CODE (operands[1]);
11810 rtx tmp, compare_op, second_test, bypass_test;
11812 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
11814 enum machine_mode cmode;
11816 /* Since we've no cmove for sse registers, don't force bad register
11817 allocation just to gain access to it. Deny movcc when the
11818 comparison mode doesn't match the move mode. */
11819 cmode = GET_MODE (ix86_compare_op0);
11820 if (cmode == VOIDmode)
11821 cmode = GET_MODE (ix86_compare_op1);
11825 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
11827 &ix86_compare_op1);
11828 if (code == UNKNOWN)
11831 if (ix86_expand_sse_fp_minmax (operands[0], code, ix86_compare_op0,
11832 ix86_compare_op1, operands[2],
11836 tmp = ix86_expand_sse_cmp (operands[0], code, ix86_compare_op0,
11837 ix86_compare_op1, operands[2], operands[3]);
11838 ix86_expand_sse_movcc (operands[0], tmp, operands[2], operands[3]);
11842 /* The floating point conditional move instructions don't directly
11843 support conditions resulting from a signed integer comparison. */
11845 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
11847 /* The floating point conditional move instructions don't directly
11848 support signed integer comparisons. */
11850 if (!fcmov_comparison_operator (compare_op, VOIDmode))
11852 gcc_assert (!second_test && !bypass_test);
11853 tmp = gen_reg_rtx (QImode);
11854 ix86_expand_setcc (code, tmp);
11856 ix86_compare_op0 = tmp;
11857 ix86_compare_op1 = const0_rtx;
11858 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
11860 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
11862 tmp = gen_reg_rtx (mode);
11863 emit_move_insn (tmp, operands[3]);
11866 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
11868 tmp = gen_reg_rtx (mode);
11869 emit_move_insn (tmp, operands[2]);
11873 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
11874 gen_rtx_IF_THEN_ELSE (mode, compare_op,
11875 operands[2], operands[3])));
11877 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
11878 gen_rtx_IF_THEN_ELSE (mode, bypass_test,
11879 operands[3], operands[0])));
11881 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
11882 gen_rtx_IF_THEN_ELSE (mode, second_test,
11883 operands[2], operands[0])));
11888 /* Expand a floating-point vector conditional move; a vcond operation
11889 rather than a movcc operation. */
11892 ix86_expand_fp_vcond (rtx operands[])
11894 enum rtx_code code = GET_CODE (operands[3]);
11897 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
11898 &operands[4], &operands[5]);
11899 if (code == UNKNOWN)
11902 if (ix86_expand_sse_fp_minmax (operands[0], code, operands[4],
11903 operands[5], operands[1], operands[2]))
11906 cmp = ix86_expand_sse_cmp (operands[0], code, operands[4], operands[5],
11907 operands[1], operands[2]);
11908 ix86_expand_sse_movcc (operands[0], cmp, operands[1], operands[2]);
11912 /* Expand a signed integral vector conditional move. */
11915 ix86_expand_int_vcond (rtx operands[])
11917 enum machine_mode mode = GET_MODE (operands[0]);
11918 enum rtx_code code = GET_CODE (operands[3]);
11919 bool negate = false;
11922 cop0 = operands[4];
11923 cop1 = operands[5];
11925 /* Canonicalize the comparison to EQ, GT, GTU. */
11936 code = reverse_condition (code);
11942 code = reverse_condition (code);
11948 code = swap_condition (code);
11949 x = cop0, cop0 = cop1, cop1 = x;
11953 gcc_unreachable ();
11956 /* Unsigned parallel compare is not supported by the hardware. Play some
11957 tricks to turn this into a signed comparison against 0. */
11960 cop0 = force_reg (mode, cop0);
11968 /* Perform a parallel modulo subtraction. */
11969 t1 = gen_reg_rtx (mode);
11970 emit_insn (gen_subv4si3 (t1, cop0, cop1));
11972 /* Extract the original sign bit of op0. */
11973 mask = GEN_INT (-0x80000000);
11974 mask = gen_rtx_CONST_VECTOR (mode,
11975 gen_rtvec (4, mask, mask, mask, mask));
11976 mask = force_reg (mode, mask);
11977 t2 = gen_reg_rtx (mode);
11978 emit_insn (gen_andv4si3 (t2, cop0, mask));
11980 /* XOR it back into the result of the subtraction. This results
11981 in the sign bit set iff we saw unsigned underflow. */
11982 x = gen_reg_rtx (mode);
11983 emit_insn (gen_xorv4si3 (x, t1, t2));
11991 /* Perform a parallel unsigned saturating subtraction. */
11992 x = gen_reg_rtx (mode);
11993 emit_insn (gen_rtx_SET (VOIDmode, x,
11994 gen_rtx_US_MINUS (mode, cop0, cop1)));
12001 gcc_unreachable ();
12005 cop1 = CONST0_RTX (mode);
12008 x = ix86_expand_sse_cmp (operands[0], code, cop0, cop1,
12009 operands[1+negate], operands[2-negate]);
12011 ix86_expand_sse_movcc (operands[0], x, operands[1+negate],
12012 operands[2-negate]);
12016 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
12017 true if we should do zero extension, else sign extension. HIGH_P is
12018 true if we want the N/2 high elements, else the low elements. */
12021 ix86_expand_sse_unpack (rtx operands[2], bool unsigned_p, bool high_p)
12023 enum machine_mode imode = GET_MODE (operands[1]);
12024 rtx (*unpack)(rtx, rtx, rtx);
12031 unpack = gen_vec_interleave_highv16qi;
12033 unpack = gen_vec_interleave_lowv16qi;
12037 unpack = gen_vec_interleave_highv8hi;
12039 unpack = gen_vec_interleave_lowv8hi;
12043 unpack = gen_vec_interleave_highv4si;
12045 unpack = gen_vec_interleave_lowv4si;
12048 gcc_unreachable ();
12051 dest = gen_lowpart (imode, operands[0]);
12054 se = force_reg (imode, CONST0_RTX (imode));
12056 se = ix86_expand_sse_cmp (gen_reg_rtx (imode), GT, CONST0_RTX (imode),
12057 operands[1], pc_rtx, pc_rtx);
12059 emit_insn (unpack (dest, operands[1], se));
12062 /* Expand conditional increment or decrement using adb/sbb instructions.
12063 The default case using setcc followed by the conditional move can be
12064 done by generic code. */
12066 ix86_expand_int_addcc (rtx operands[])
12068 enum rtx_code code = GET_CODE (operands[1]);
12070 rtx val = const0_rtx;
12071 bool fpcmp = false;
12072 enum machine_mode mode = GET_MODE (operands[0]);
12074 if (operands[3] != const1_rtx
12075 && operands[3] != constm1_rtx)
12077 if (!ix86_expand_carry_flag_compare (code, ix86_compare_op0,
12078 ix86_compare_op1, &compare_op))
12080 code = GET_CODE (compare_op);
12082 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
12083 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
12086 code = ix86_fp_compare_code_to_integer (code);
12093 PUT_CODE (compare_op,
12094 reverse_condition_maybe_unordered
12095 (GET_CODE (compare_op)));
12097 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
12099 PUT_MODE (compare_op, mode);
12101 /* Construct either adc or sbb insn. */
12102 if ((code == LTU) == (operands[3] == constm1_rtx))
12104 switch (GET_MODE (operands[0]))
12107 emit_insn (gen_subqi3_carry (operands[0], operands[2], val, compare_op));
12110 emit_insn (gen_subhi3_carry (operands[0], operands[2], val, compare_op));
12113 emit_insn (gen_subsi3_carry (operands[0], operands[2], val, compare_op));
12116 emit_insn (gen_subdi3_carry_rex64 (operands[0], operands[2], val, compare_op));
12119 gcc_unreachable ();
12124 switch (GET_MODE (operands[0]))
12127 emit_insn (gen_addqi3_carry (operands[0], operands[2], val, compare_op));
12130 emit_insn (gen_addhi3_carry (operands[0], operands[2], val, compare_op));
12133 emit_insn (gen_addsi3_carry (operands[0], operands[2], val, compare_op));
12136 emit_insn (gen_adddi3_carry_rex64 (operands[0], operands[2], val, compare_op));
12139 gcc_unreachable ();
12142 return 1; /* DONE */
12146 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
12147 works for floating pointer parameters and nonoffsetable memories.
12148 For pushes, it returns just stack offsets; the values will be saved
12149 in the right order. Maximally three parts are generated. */
12152 ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode)
12157 size = mode==XFmode ? 3 : GET_MODE_SIZE (mode) / 4;
12159 size = (GET_MODE_SIZE (mode) + 4) / 8;
12161 gcc_assert (GET_CODE (operand) != REG || !MMX_REGNO_P (REGNO (operand)));
12162 gcc_assert (size >= 2 && size <= 3);
12164 /* Optimize constant pool reference to immediates. This is used by fp
12165 moves, that force all constants to memory to allow combining. */
12166 if (GET_CODE (operand) == MEM && MEM_READONLY_P (operand))
12168 rtx tmp = maybe_get_pool_constant (operand);
12173 if (GET_CODE (operand) == MEM && !offsettable_memref_p (operand))
12175 /* The only non-offsetable memories we handle are pushes. */
12176 int ok = push_operand (operand, VOIDmode);
12180 operand = copy_rtx (operand);
12181 PUT_MODE (operand, Pmode);
12182 parts[0] = parts[1] = parts[2] = operand;
12186 if (GET_CODE (operand) == CONST_VECTOR)
12188 enum machine_mode imode = int_mode_for_mode (mode);
12189 /* Caution: if we looked through a constant pool memory above,
12190 the operand may actually have a different mode now. That's
12191 ok, since we want to pun this all the way back to an integer. */
12192 operand = simplify_subreg (imode, operand, GET_MODE (operand), 0);
12193 gcc_assert (operand != NULL);
12199 if (mode == DImode)
12200 split_di (&operand, 1, &parts[0], &parts[1]);
12203 if (REG_P (operand))
12205 gcc_assert (reload_completed);
12206 parts[0] = gen_rtx_REG (SImode, REGNO (operand) + 0);
12207 parts[1] = gen_rtx_REG (SImode, REGNO (operand) + 1);
12209 parts[2] = gen_rtx_REG (SImode, REGNO (operand) + 2);
12211 else if (offsettable_memref_p (operand))
12213 operand = adjust_address (operand, SImode, 0);
12214 parts[0] = operand;
12215 parts[1] = adjust_address (operand, SImode, 4);
12217 parts[2] = adjust_address (operand, SImode, 8);
12219 else if (GET_CODE (operand) == CONST_DOUBLE)
12224 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
12228 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
12229 parts[2] = gen_int_mode (l[2], SImode);
12232 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
12235 gcc_unreachable ();
12237 parts[1] = gen_int_mode (l[1], SImode);
12238 parts[0] = gen_int_mode (l[0], SImode);
12241 gcc_unreachable ();
12246 if (mode == TImode)
12247 split_ti (&operand, 1, &parts[0], &parts[1]);
12248 if (mode == XFmode || mode == TFmode)
12250 enum machine_mode upper_mode = mode==XFmode ? SImode : DImode;
12251 if (REG_P (operand))
12253 gcc_assert (reload_completed);
12254 parts[0] = gen_rtx_REG (DImode, REGNO (operand) + 0);
12255 parts[1] = gen_rtx_REG (upper_mode, REGNO (operand) + 1);
12257 else if (offsettable_memref_p (operand))
12259 operand = adjust_address (operand, DImode, 0);
12260 parts[0] = operand;
12261 parts[1] = adjust_address (operand, upper_mode, 8);
12263 else if (GET_CODE (operand) == CONST_DOUBLE)
12268 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
12269 real_to_target (l, &r, mode);
12271 /* Do not use shift by 32 to avoid warning on 32bit systems. */
12272 if (HOST_BITS_PER_WIDE_INT >= 64)
12275 ((l[0] & (((HOST_WIDE_INT) 2 << 31) - 1))
12276 + ((((HOST_WIDE_INT) l[1]) << 31) << 1),
12279 parts[0] = immed_double_const (l[0], l[1], DImode);
12281 if (upper_mode == SImode)
12282 parts[1] = gen_int_mode (l[2], SImode);
12283 else if (HOST_BITS_PER_WIDE_INT >= 64)
12286 ((l[2] & (((HOST_WIDE_INT) 2 << 31) - 1))
12287 + ((((HOST_WIDE_INT) l[3]) << 31) << 1),
12290 parts[1] = immed_double_const (l[2], l[3], DImode);
12293 gcc_unreachable ();
12300 /* Emit insns to perform a move or push of DI, DF, and XF values.
12301 Return false when normal moves are needed; true when all required
12302 insns have been emitted. Operands 2-4 contain the input values
12303 int the correct order; operands 5-7 contain the output values. */
12306 ix86_split_long_move (rtx operands[])
12311 int collisions = 0;
12312 enum machine_mode mode = GET_MODE (operands[0]);
12314 /* The DFmode expanders may ask us to move double.
12315 For 64bit target this is single move. By hiding the fact
12316 here we simplify i386.md splitters. */
12317 if (GET_MODE_SIZE (GET_MODE (operands[0])) == 8 && TARGET_64BIT)
12319 /* Optimize constant pool reference to immediates. This is used by
12320 fp moves, that force all constants to memory to allow combining. */
12322 if (GET_CODE (operands[1]) == MEM
12323 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
12324 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0)))
12325 operands[1] = get_pool_constant (XEXP (operands[1], 0));
12326 if (push_operand (operands[0], VOIDmode))
12328 operands[0] = copy_rtx (operands[0]);
12329 PUT_MODE (operands[0], Pmode);
12332 operands[0] = gen_lowpart (DImode, operands[0]);
12333 operands[1] = gen_lowpart (DImode, operands[1]);
12334 emit_move_insn (operands[0], operands[1]);
12338 /* The only non-offsettable memory we handle is push. */
12339 if (push_operand (operands[0], VOIDmode))
12342 gcc_assert (GET_CODE (operands[0]) != MEM
12343 || offsettable_memref_p (operands[0]));
12345 nparts = ix86_split_to_parts (operands[1], part[1], GET_MODE (operands[0]));
12346 ix86_split_to_parts (operands[0], part[0], GET_MODE (operands[0]));
12348 /* When emitting push, take care for source operands on the stack. */
12349 if (push && GET_CODE (operands[1]) == MEM
12350 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
12353 part[1][1] = change_address (part[1][1], GET_MODE (part[1][1]),
12354 XEXP (part[1][2], 0));
12355 part[1][0] = change_address (part[1][0], GET_MODE (part[1][0]),
12356 XEXP (part[1][1], 0));
12359 /* We need to do copy in the right order in case an address register
12360 of the source overlaps the destination. */
12361 if (REG_P (part[0][0]) && GET_CODE (part[1][0]) == MEM)
12363 if (reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0)))
12365 if (reg_overlap_mentioned_p (part[0][1], XEXP (part[1][0], 0)))
12368 && reg_overlap_mentioned_p (part[0][2], XEXP (part[1][0], 0)))
12371 /* Collision in the middle part can be handled by reordering. */
12372 if (collisions == 1 && nparts == 3
12373 && reg_overlap_mentioned_p (part[0][1], XEXP (part[1][0], 0)))
12376 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
12377 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
12380 /* If there are more collisions, we can't handle it by reordering.
12381 Do an lea to the last part and use only one colliding move. */
12382 else if (collisions > 1)
12388 base = part[0][nparts - 1];
12390 /* Handle the case when the last part isn't valid for lea.
12391 Happens in 64-bit mode storing the 12-byte XFmode. */
12392 if (GET_MODE (base) != Pmode)
12393 base = gen_rtx_REG (Pmode, REGNO (base));
12395 emit_insn (gen_rtx_SET (VOIDmode, base, XEXP (part[1][0], 0)));
12396 part[1][0] = replace_equiv_address (part[1][0], base);
12397 part[1][1] = replace_equiv_address (part[1][1],
12398 plus_constant (base, UNITS_PER_WORD));
12400 part[1][2] = replace_equiv_address (part[1][2],
12401 plus_constant (base, 8));
12411 if (TARGET_128BIT_LONG_DOUBLE && mode == XFmode)
12412 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, GEN_INT (-4)));
12413 emit_move_insn (part[0][2], part[1][2]);
12418 /* In 64bit mode we don't have 32bit push available. In case this is
12419 register, it is OK - we will just use larger counterpart. We also
12420 retype memory - these comes from attempt to avoid REX prefix on
12421 moving of second half of TFmode value. */
12422 if (GET_MODE (part[1][1]) == SImode)
12424 switch (GET_CODE (part[1][1]))
12427 part[1][1] = adjust_address (part[1][1], DImode, 0);
12431 part[1][1] = gen_rtx_REG (DImode, REGNO (part[1][1]));
12435 gcc_unreachable ();
12438 if (GET_MODE (part[1][0]) == SImode)
12439 part[1][0] = part[1][1];
12442 emit_move_insn (part[0][1], part[1][1]);
12443 emit_move_insn (part[0][0], part[1][0]);
12447 /* Choose correct order to not overwrite the source before it is copied. */
12448 if ((REG_P (part[0][0])
12449 && REG_P (part[1][1])
12450 && (REGNO (part[0][0]) == REGNO (part[1][1])
12452 && REGNO (part[0][0]) == REGNO (part[1][2]))))
12454 && reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0))))
12458 operands[2] = part[0][2];
12459 operands[3] = part[0][1];
12460 operands[4] = part[0][0];
12461 operands[5] = part[1][2];
12462 operands[6] = part[1][1];
12463 operands[7] = part[1][0];
12467 operands[2] = part[0][1];
12468 operands[3] = part[0][0];
12469 operands[5] = part[1][1];
12470 operands[6] = part[1][0];
12477 operands[2] = part[0][0];
12478 operands[3] = part[0][1];
12479 operands[4] = part[0][2];
12480 operands[5] = part[1][0];
12481 operands[6] = part[1][1];
12482 operands[7] = part[1][2];
12486 operands[2] = part[0][0];
12487 operands[3] = part[0][1];
12488 operands[5] = part[1][0];
12489 operands[6] = part[1][1];
12493 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
12496 if (GET_CODE (operands[5]) == CONST_INT
12497 && operands[5] != const0_rtx
12498 && REG_P (operands[2]))
12500 if (GET_CODE (operands[6]) == CONST_INT
12501 && INTVAL (operands[6]) == INTVAL (operands[5]))
12502 operands[6] = operands[2];
12505 && GET_CODE (operands[7]) == CONST_INT
12506 && INTVAL (operands[7]) == INTVAL (operands[5]))
12507 operands[7] = operands[2];
12511 && GET_CODE (operands[6]) == CONST_INT
12512 && operands[6] != const0_rtx
12513 && REG_P (operands[3])
12514 && GET_CODE (operands[7]) == CONST_INT
12515 && INTVAL (operands[7]) == INTVAL (operands[6]))
12516 operands[7] = operands[3];
12519 emit_move_insn (operands[2], operands[5]);
12520 emit_move_insn (operands[3], operands[6]);
12522 emit_move_insn (operands[4], operands[7]);
12527 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
12528 left shift by a constant, either using a single shift or
12529 a sequence of add instructions. */
12532 ix86_expand_ashl_const (rtx operand, int count, enum machine_mode mode)
12536 emit_insn ((mode == DImode
12538 : gen_adddi3) (operand, operand, operand));
12540 else if (!optimize_size
12541 && count * ix86_cost->add <= ix86_cost->shift_const)
12544 for (i=0; i<count; i++)
12546 emit_insn ((mode == DImode
12548 : gen_adddi3) (operand, operand, operand));
12552 emit_insn ((mode == DImode
12554 : gen_ashldi3) (operand, operand, GEN_INT (count)));
12558 ix86_split_ashl (rtx *operands, rtx scratch, enum machine_mode mode)
12560 rtx low[2], high[2];
12562 const int single_width = mode == DImode ? 32 : 64;
12564 if (GET_CODE (operands[2]) == CONST_INT)
12566 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
12567 count = INTVAL (operands[2]) & (single_width * 2 - 1);
12569 if (count >= single_width)
12571 emit_move_insn (high[0], low[1]);
12572 emit_move_insn (low[0], const0_rtx);
12574 if (count > single_width)
12575 ix86_expand_ashl_const (high[0], count - single_width, mode);
12579 if (!rtx_equal_p (operands[0], operands[1]))
12580 emit_move_insn (operands[0], operands[1]);
12581 emit_insn ((mode == DImode
12583 : gen_x86_64_shld) (high[0], low[0], GEN_INT (count)));
12584 ix86_expand_ashl_const (low[0], count, mode);
12589 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
12591 if (operands[1] == const1_rtx)
12593 /* Assuming we've chosen a QImode capable registers, then 1 << N
12594 can be done with two 32/64-bit shifts, no branches, no cmoves. */
12595 if (ANY_QI_REG_P (low[0]) && ANY_QI_REG_P (high[0]))
12597 rtx s, d, flags = gen_rtx_REG (CCZmode, FLAGS_REG);
12599 ix86_expand_clear (low[0]);
12600 ix86_expand_clear (high[0]);
12601 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (single_width)));
12603 d = gen_lowpart (QImode, low[0]);
12604 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
12605 s = gen_rtx_EQ (QImode, flags, const0_rtx);
12606 emit_insn (gen_rtx_SET (VOIDmode, d, s));
12608 d = gen_lowpart (QImode, high[0]);
12609 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
12610 s = gen_rtx_NE (QImode, flags, const0_rtx);
12611 emit_insn (gen_rtx_SET (VOIDmode, d, s));
12614 /* Otherwise, we can get the same results by manually performing
12615 a bit extract operation on bit 5/6, and then performing the two
12616 shifts. The two methods of getting 0/1 into low/high are exactly
12617 the same size. Avoiding the shift in the bit extract case helps
12618 pentium4 a bit; no one else seems to care much either way. */
12623 if (TARGET_PARTIAL_REG_STALL && !optimize_size)
12624 x = gen_rtx_ZERO_EXTEND (mode == DImode ? SImode : DImode, operands[2]);
12626 x = gen_lowpart (mode == DImode ? SImode : DImode, operands[2]);
12627 emit_insn (gen_rtx_SET (VOIDmode, high[0], x));
12629 emit_insn ((mode == DImode
12631 : gen_lshrdi3) (high[0], high[0], GEN_INT (mode == DImode ? 5 : 6)));
12632 emit_insn ((mode == DImode
12634 : gen_anddi3) (high[0], high[0], GEN_INT (1)));
12635 emit_move_insn (low[0], high[0]);
12636 emit_insn ((mode == DImode
12638 : gen_xordi3) (low[0], low[0], GEN_INT (1)));
12641 emit_insn ((mode == DImode
12643 : gen_ashldi3) (low[0], low[0], operands[2]));
12644 emit_insn ((mode == DImode
12646 : gen_ashldi3) (high[0], high[0], operands[2]));
12650 if (operands[1] == constm1_rtx)
12652 /* For -1 << N, we can avoid the shld instruction, because we
12653 know that we're shifting 0...31/63 ones into a -1. */
12654 emit_move_insn (low[0], constm1_rtx);
12656 emit_move_insn (high[0], low[0]);
12658 emit_move_insn (high[0], constm1_rtx);
12662 if (!rtx_equal_p (operands[0], operands[1]))
12663 emit_move_insn (operands[0], operands[1]);
12665 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
12666 emit_insn ((mode == DImode
12668 : gen_x86_64_shld) (high[0], low[0], operands[2]));
12671 emit_insn ((mode == DImode ? gen_ashlsi3 : gen_ashldi3) (low[0], low[0], operands[2]));
12673 if (TARGET_CMOVE && scratch)
12675 ix86_expand_clear (scratch);
12676 emit_insn ((mode == DImode
12677 ? gen_x86_shift_adj_1
12678 : gen_x86_64_shift_adj) (high[0], low[0], operands[2], scratch));
12681 emit_insn (gen_x86_shift_adj_2 (high[0], low[0], operands[2]));
12685 ix86_split_ashr (rtx *operands, rtx scratch, enum machine_mode mode)
12687 rtx low[2], high[2];
12689 const int single_width = mode == DImode ? 32 : 64;
12691 if (GET_CODE (operands[2]) == CONST_INT)
12693 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
12694 count = INTVAL (operands[2]) & (single_width * 2 - 1);
12696 if (count == single_width * 2 - 1)
12698 emit_move_insn (high[0], high[1]);
12699 emit_insn ((mode == DImode
12701 : gen_ashrdi3) (high[0], high[0],
12702 GEN_INT (single_width - 1)));
12703 emit_move_insn (low[0], high[0]);
12706 else if (count >= single_width)
12708 emit_move_insn (low[0], high[1]);
12709 emit_move_insn (high[0], low[0]);
12710 emit_insn ((mode == DImode
12712 : gen_ashrdi3) (high[0], high[0],
12713 GEN_INT (single_width - 1)));
12714 if (count > single_width)
12715 emit_insn ((mode == DImode
12717 : gen_ashrdi3) (low[0], low[0],
12718 GEN_INT (count - single_width)));
12722 if (!rtx_equal_p (operands[0], operands[1]))
12723 emit_move_insn (operands[0], operands[1]);
12724 emit_insn ((mode == DImode
12726 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
12727 emit_insn ((mode == DImode
12729 : gen_ashrdi3) (high[0], high[0], GEN_INT (count)));
12734 if (!rtx_equal_p (operands[0], operands[1]))
12735 emit_move_insn (operands[0], operands[1]);
12737 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
12739 emit_insn ((mode == DImode
12741 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
12742 emit_insn ((mode == DImode
12744 : gen_ashrdi3) (high[0], high[0], operands[2]));
12746 if (TARGET_CMOVE && scratch)
12748 emit_move_insn (scratch, high[0]);
12749 emit_insn ((mode == DImode
12751 : gen_ashrdi3) (scratch, scratch,
12752 GEN_INT (single_width - 1)));
12753 emit_insn ((mode == DImode
12754 ? gen_x86_shift_adj_1
12755 : gen_x86_64_shift_adj) (low[0], high[0], operands[2],
12759 emit_insn (gen_x86_shift_adj_3 (low[0], high[0], operands[2]));
12764 ix86_split_lshr (rtx *operands, rtx scratch, enum machine_mode mode)
12766 rtx low[2], high[2];
12768 const int single_width = mode == DImode ? 32 : 64;
12770 if (GET_CODE (operands[2]) == CONST_INT)
12772 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
12773 count = INTVAL (operands[2]) & (single_width * 2 - 1);
12775 if (count >= single_width)
12777 emit_move_insn (low[0], high[1]);
12778 ix86_expand_clear (high[0]);
12780 if (count > single_width)
12781 emit_insn ((mode == DImode
12783 : gen_lshrdi3) (low[0], low[0],
12784 GEN_INT (count - single_width)));
12788 if (!rtx_equal_p (operands[0], operands[1]))
12789 emit_move_insn (operands[0], operands[1]);
12790 emit_insn ((mode == DImode
12792 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
12793 emit_insn ((mode == DImode
12795 : gen_lshrdi3) (high[0], high[0], GEN_INT (count)));
12800 if (!rtx_equal_p (operands[0], operands[1]))
12801 emit_move_insn (operands[0], operands[1]);
12803 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
12805 emit_insn ((mode == DImode
12807 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
12808 emit_insn ((mode == DImode
12810 : gen_lshrdi3) (high[0], high[0], operands[2]));
12812 /* Heh. By reversing the arguments, we can reuse this pattern. */
12813 if (TARGET_CMOVE && scratch)
12815 ix86_expand_clear (scratch);
12816 emit_insn ((mode == DImode
12817 ? gen_x86_shift_adj_1
12818 : gen_x86_64_shift_adj) (low[0], high[0], operands[2],
12822 emit_insn (gen_x86_shift_adj_2 (low[0], high[0], operands[2]));
12826 /* Predict just emitted jump instruction to be taken with probability PROB. */
12828 predict_jump (int prob)
12830 rtx insn = get_last_insn ();
12831 gcc_assert (GET_CODE (insn) == JUMP_INSN);
12833 = gen_rtx_EXPR_LIST (REG_BR_PROB,
12838 /* Helper function for the string operations below. Dest VARIABLE whether
12839 it is aligned to VALUE bytes. If true, jump to the label. */
12841 ix86_expand_aligntest (rtx variable, int value, bool epilogue)
12843 rtx label = gen_label_rtx ();
12844 rtx tmpcount = gen_reg_rtx (GET_MODE (variable));
12845 if (GET_MODE (variable) == DImode)
12846 emit_insn (gen_anddi3 (tmpcount, variable, GEN_INT (value)));
12848 emit_insn (gen_andsi3 (tmpcount, variable, GEN_INT (value)));
12849 emit_cmp_and_jump_insns (tmpcount, const0_rtx, EQ, 0, GET_MODE (variable),
12852 predict_jump (REG_BR_PROB_BASE * 50 / 100);
12854 predict_jump (REG_BR_PROB_BASE * 90 / 100);
12858 /* Adjust COUNTER by the VALUE. */
12860 ix86_adjust_counter (rtx countreg, HOST_WIDE_INT value)
12862 if (GET_MODE (countreg) == DImode)
12863 emit_insn (gen_adddi3 (countreg, countreg, GEN_INT (-value)));
12865 emit_insn (gen_addsi3 (countreg, countreg, GEN_INT (-value)));
12868 /* Zero extend possibly SImode EXP to Pmode register. */
12870 ix86_zero_extend_to_Pmode (rtx exp)
12873 if (GET_MODE (exp) == VOIDmode)
12874 return force_reg (Pmode, exp);
12875 if (GET_MODE (exp) == Pmode)
12876 return copy_to_mode_reg (Pmode, exp);
12877 r = gen_reg_rtx (Pmode);
12878 emit_insn (gen_zero_extendsidi2 (r, exp));
12882 /* Divide COUNTREG by SCALE. */
12884 scale_counter (rtx countreg, int scale)
12887 rtx piece_size_mask;
12891 if (GET_CODE (countreg) == CONST_INT)
12892 return GEN_INT (INTVAL (countreg) / scale);
12893 gcc_assert (REG_P (countreg));
12895 piece_size_mask = GEN_INT (scale - 1);
12896 sc = expand_simple_binop (GET_MODE (countreg), LSHIFTRT, countreg,
12897 GEN_INT (exact_log2 (scale)),
12898 NULL, 1, OPTAB_DIRECT);
12902 /* When SRCPTR is non-NULL, output simple loop to move memory
12903 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
12904 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
12905 equivalent loop to set memory by VALUE (supposed to be in MODE).
12907 The size is rounded down to whole number of chunk size moved at once.
12908 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
12912 expand_set_or_movmem_via_loop (rtx destmem, rtx srcmem,
12913 rtx destptr, rtx srcptr, rtx value,
12914 rtx count, enum machine_mode mode, int unroll,
12917 rtx out_label, top_label, iter, tmp;
12918 enum machine_mode iter_mode;
12919 rtx piece_size = GEN_INT (GET_MODE_SIZE (mode) * unroll);
12920 rtx piece_size_mask = GEN_INT (~((GET_MODE_SIZE (mode) * unroll) - 1));
12926 iter_mode = GET_MODE (count);
12927 if (iter_mode == VOIDmode)
12928 iter_mode = word_mode;
12930 top_label = gen_label_rtx ();
12931 out_label = gen_label_rtx ();
12932 iter = gen_reg_rtx (iter_mode);
12934 size = expand_simple_binop (iter_mode, AND, count, piece_size_mask,
12935 NULL, 1, OPTAB_DIRECT);
12936 /* Those two should combine. */
12937 if (piece_size == const1_rtx)
12939 emit_cmp_and_jump_insns (size, const0_rtx, EQ, NULL_RTX, iter_mode,
12941 predict_jump (REG_BR_PROB_BASE * 10 / 100);
12943 emit_move_insn (iter, const0_rtx);
12945 emit_label (top_label);
12947 tmp = convert_modes (Pmode, iter_mode, iter, true);
12948 x_addr = gen_rtx_PLUS (Pmode, destptr, tmp);
12949 destmem = change_address (destmem, mode, x_addr);
12953 y_addr = gen_rtx_PLUS (Pmode, srcptr, copy_rtx (tmp));
12954 srcmem = change_address (srcmem, mode, y_addr);
12956 /* When unrolling for chips that reorder memory reads and writes,
12957 we can save registers by using single temporary.
12958 Also using 4 temporaries is overkill in 32bit mode. */
12959 if (!TARGET_64BIT && 0)
12961 for (i = 0; i < unroll; i++)
12966 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
12968 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
12970 emit_move_insn (destmem, srcmem);
12976 gcc_assert (unroll <= 4);
12977 for (i = 0; i < unroll; i++)
12979 tmpreg[i] = gen_reg_rtx (mode);
12983 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
12985 emit_move_insn (tmpreg[i], srcmem);
12987 for (i = 0; i < unroll; i++)
12992 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
12994 emit_move_insn (destmem, tmpreg[i]);
12999 for (i = 0; i < unroll; i++)
13003 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
13004 emit_move_insn (destmem, value);
13007 tmp = expand_simple_binop (iter_mode, PLUS, iter, piece_size, iter,
13008 true, OPTAB_LIB_WIDEN);
13010 emit_move_insn (iter, tmp);
13012 emit_cmp_and_jump_insns (iter, size, LT, NULL_RTX, iter_mode,
13014 if (expected_size != -1)
13016 expected_size /= GET_MODE_SIZE (mode) * unroll;
13017 if (expected_size == 0)
13019 else if (expected_size > REG_BR_PROB_BASE)
13020 predict_jump (REG_BR_PROB_BASE - 1);
13022 predict_jump (REG_BR_PROB_BASE - (REG_BR_PROB_BASE + expected_size / 2) / expected_size);
13025 predict_jump (REG_BR_PROB_BASE * 80 / 100);
13026 iter = ix86_zero_extend_to_Pmode (iter);
13027 tmp = expand_simple_binop (Pmode, PLUS, destptr, iter, destptr,
13028 true, OPTAB_LIB_WIDEN);
13029 if (tmp != destptr)
13030 emit_move_insn (destptr, tmp);
13033 tmp = expand_simple_binop (Pmode, PLUS, srcptr, iter, srcptr,
13034 true, OPTAB_LIB_WIDEN);
13036 emit_move_insn (srcptr, tmp);
13038 emit_label (out_label);
13041 /* Output "rep; mov" instruction.
13042 Arguments have same meaning as for previous function */
13044 expand_movmem_via_rep_mov (rtx destmem, rtx srcmem,
13045 rtx destptr, rtx srcptr,
13047 enum machine_mode mode)
13053 /* If the size is known, it is shorter to use rep movs. */
13054 if (mode == QImode && GET_CODE (count) == CONST_INT
13055 && !(INTVAL (count) & 3))
13058 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
13059 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
13060 if (srcptr != XEXP (srcmem, 0) || GET_MODE (srcmem) != BLKmode)
13061 srcmem = adjust_automodify_address_nv (srcmem, BLKmode, srcptr, 0);
13062 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
13063 if (mode != QImode)
13065 destexp = gen_rtx_ASHIFT (Pmode, countreg,
13066 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
13067 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
13068 srcexp = gen_rtx_ASHIFT (Pmode, countreg,
13069 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
13070 srcexp = gen_rtx_PLUS (Pmode, srcexp, srcptr);
13074 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
13075 srcexp = gen_rtx_PLUS (Pmode, srcptr, countreg);
13077 emit_insn (gen_rep_mov (destptr, destmem, srcptr, srcmem, countreg,
13081 /* Output "rep; stos" instruction.
13082 Arguments have same meaning as for previous function */
13084 expand_setmem_via_rep_stos (rtx destmem, rtx destptr, rtx value,
13086 enum machine_mode mode)
13091 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
13092 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
13093 value = force_reg (mode, gen_lowpart (mode, value));
13094 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
13095 if (mode != QImode)
13097 destexp = gen_rtx_ASHIFT (Pmode, countreg,
13098 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
13099 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
13102 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
13103 emit_insn (gen_rep_stos (destptr, countreg, destmem, value, destexp));
13107 emit_strmov (rtx destmem, rtx srcmem,
13108 rtx destptr, rtx srcptr, enum machine_mode mode, int offset)
13110 rtx src = adjust_automodify_address_nv (srcmem, mode, srcptr, offset);
13111 rtx dest = adjust_automodify_address_nv (destmem, mode, destptr, offset);
13112 emit_insn (gen_strmov (destptr, dest, srcptr, src));
13115 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
13117 expand_movmem_epilogue (rtx destmem, rtx srcmem,
13118 rtx destptr, rtx srcptr, rtx count, int max_size)
13121 if (GET_CODE (count) == CONST_INT)
13123 HOST_WIDE_INT countval = INTVAL (count);
13126 if ((countval & 0x16) && max_size > 16)
13130 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
13131 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset + 8);
13134 gcc_unreachable ();
13137 if ((countval & 0x08) && max_size > 8)
13140 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
13143 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
13144 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset + 4);
13148 if ((countval & 0x04) && max_size > 4)
13150 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
13153 if ((countval & 0x02) && max_size > 2)
13155 emit_strmov (destmem, srcmem, destptr, srcptr, HImode, offset);
13158 if ((countval & 0x01) && max_size > 1)
13160 emit_strmov (destmem, srcmem, destptr, srcptr, QImode, offset);
13167 count = expand_simple_binop (GET_MODE (count), AND, count, GEN_INT (max_size - 1),
13168 count, 1, OPTAB_DIRECT);
13169 expand_set_or_movmem_via_loop (destmem, srcmem, destptr, srcptr, NULL,
13170 count, QImode, 1, 4);
13174 /* When there are stringops, we can cheaply increase dest and src pointers.
13175 Otherwise we save code size by maintaining offset (zero is readily
13176 available from preceding rep operation) and using x86 addressing modes.
13178 if (TARGET_SINGLE_STRINGOP)
13182 rtx label = ix86_expand_aligntest (count, 4, true);
13183 src = change_address (srcmem, SImode, srcptr);
13184 dest = change_address (destmem, SImode, destptr);
13185 emit_insn (gen_strmov (destptr, dest, srcptr, src));
13186 emit_label (label);
13187 LABEL_NUSES (label) = 1;
13191 rtx label = ix86_expand_aligntest (count, 2, true);
13192 src = change_address (srcmem, HImode, srcptr);
13193 dest = change_address (destmem, HImode, destptr);
13194 emit_insn (gen_strmov (destptr, dest, srcptr, src));
13195 emit_label (label);
13196 LABEL_NUSES (label) = 1;
13200 rtx label = ix86_expand_aligntest (count, 1, true);
13201 src = change_address (srcmem, QImode, srcptr);
13202 dest = change_address (destmem, QImode, destptr);
13203 emit_insn (gen_strmov (destptr, dest, srcptr, src));
13204 emit_label (label);
13205 LABEL_NUSES (label) = 1;
13210 rtx offset = force_reg (Pmode, const0_rtx);
13215 rtx label = ix86_expand_aligntest (count, 4, true);
13216 src = change_address (srcmem, SImode, srcptr);
13217 dest = change_address (destmem, SImode, destptr);
13218 emit_move_insn (dest, src);
13219 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (4), NULL,
13220 true, OPTAB_LIB_WIDEN);
13222 emit_move_insn (offset, tmp);
13223 emit_label (label);
13224 LABEL_NUSES (label) = 1;
13228 rtx label = ix86_expand_aligntest (count, 2, true);
13229 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
13230 src = change_address (srcmem, HImode, tmp);
13231 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
13232 dest = change_address (destmem, HImode, tmp);
13233 emit_move_insn (dest, src);
13234 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (2), tmp,
13235 true, OPTAB_LIB_WIDEN);
13237 emit_move_insn (offset, tmp);
13238 emit_label (label);
13239 LABEL_NUSES (label) = 1;
13243 rtx label = ix86_expand_aligntest (count, 1, true);
13244 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
13245 src = change_address (srcmem, QImode, tmp);
13246 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
13247 dest = change_address (destmem, QImode, tmp);
13248 emit_move_insn (dest, src);
13249 emit_label (label);
13250 LABEL_NUSES (label) = 1;
13255 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
13257 expand_setmem_epilogue_via_loop (rtx destmem, rtx destptr, rtx value,
13258 rtx count, int max_size)
13261 expand_simple_binop (GET_MODE (count), AND, count, GEN_INT (max_size - 1),
13262 count, 1, OPTAB_DIRECT);
13263 expand_set_or_movmem_via_loop (destmem, NULL, destptr, NULL,
13264 gen_lowpart (QImode, value), count, QImode,
13268 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
13270 expand_setmem_epilogue (rtx destmem, rtx destptr, rtx value, rtx count, int max_size)
13273 if (GET_CODE (count) == CONST_INT)
13275 HOST_WIDE_INT countval = INTVAL (count);
13278 if ((countval & 0x16) && max_size > 16)
13282 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
13283 emit_insn (gen_strset (destptr, dest, value));
13284 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset + 8);
13285 emit_insn (gen_strset (destptr, dest, value));
13288 gcc_unreachable ();
13291 if ((countval & 0x08) && max_size > 8)
13295 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
13296 emit_insn (gen_strset (destptr, dest, value));
13300 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
13301 emit_insn (gen_strset (destptr, dest, value));
13302 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset + 4);
13303 emit_insn (gen_strset (destptr, dest, value));
13307 if ((countval & 0x04) && max_size > 4)
13309 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
13310 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
13313 if ((countval & 0x02) && max_size > 2)
13315 dest = adjust_automodify_address_nv (destmem, HImode, destptr, offset);
13316 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
13319 if ((countval & 0x01) && max_size > 1)
13321 dest = adjust_automodify_address_nv (destmem, QImode, destptr, offset);
13322 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
13329 expand_setmem_epilogue_via_loop (destmem, destptr, value, count, max_size);
13334 rtx label = ix86_expand_aligntest (count, 16, true);
13337 dest = change_address (destmem, DImode, destptr);
13338 emit_insn (gen_strset (destptr, dest, value));
13339 emit_insn (gen_strset (destptr, dest, value));
13343 dest = change_address (destmem, SImode, destptr);
13344 emit_insn (gen_strset (destptr, dest, value));
13345 emit_insn (gen_strset (destptr, dest, value));
13346 emit_insn (gen_strset (destptr, dest, value));
13347 emit_insn (gen_strset (destptr, dest, value));
13349 emit_label (label);
13350 LABEL_NUSES (label) = 1;
13354 rtx label = ix86_expand_aligntest (count, 8, true);
13357 dest = change_address (destmem, DImode, destptr);
13358 emit_insn (gen_strset (destptr, dest, value));
13362 dest = change_address (destmem, SImode, destptr);
13363 emit_insn (gen_strset (destptr, dest, value));
13364 emit_insn (gen_strset (destptr, dest, value));
13366 emit_label (label);
13367 LABEL_NUSES (label) = 1;
13371 rtx label = ix86_expand_aligntest (count, 4, true);
13372 dest = change_address (destmem, SImode, destptr);
13373 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
13374 emit_label (label);
13375 LABEL_NUSES (label) = 1;
13379 rtx label = ix86_expand_aligntest (count, 2, true);
13380 dest = change_address (destmem, HImode, destptr);
13381 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
13382 emit_label (label);
13383 LABEL_NUSES (label) = 1;
13387 rtx label = ix86_expand_aligntest (count, 1, true);
13388 dest = change_address (destmem, QImode, destptr);
13389 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
13390 emit_label (label);
13391 LABEL_NUSES (label) = 1;
13395 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
13396 DESIRED_ALIGNMENT. */
13398 expand_movmem_prologue (rtx destmem, rtx srcmem,
13399 rtx destptr, rtx srcptr, rtx count,
13400 int align, int desired_alignment)
13402 if (align <= 1 && desired_alignment > 1)
13404 rtx label = ix86_expand_aligntest (destptr, 1, false);
13405 srcmem = change_address (srcmem, QImode, srcptr);
13406 destmem = change_address (destmem, QImode, destptr);
13407 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
13408 ix86_adjust_counter (count, 1);
13409 emit_label (label);
13410 LABEL_NUSES (label) = 1;
13412 if (align <= 2 && desired_alignment > 2)
13414 rtx label = ix86_expand_aligntest (destptr, 2, false);
13415 srcmem = change_address (srcmem, HImode, srcptr);
13416 destmem = change_address (destmem, HImode, destptr);
13417 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
13418 ix86_adjust_counter (count, 2);
13419 emit_label (label);
13420 LABEL_NUSES (label) = 1;
13422 if (align <= 4 && desired_alignment > 4)
13424 rtx label = ix86_expand_aligntest (destptr, 4, false);
13425 srcmem = change_address (srcmem, SImode, srcptr);
13426 destmem = change_address (destmem, SImode, destptr);
13427 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
13428 ix86_adjust_counter (count, 4);
13429 emit_label (label);
13430 LABEL_NUSES (label) = 1;
13432 gcc_assert (desired_alignment <= 8);
13435 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
13436 DESIRED_ALIGNMENT. */
13438 expand_setmem_prologue (rtx destmem, rtx destptr, rtx value, rtx count,
13439 int align, int desired_alignment)
13441 if (align <= 1 && desired_alignment > 1)
13443 rtx label = ix86_expand_aligntest (destptr, 1, false);
13444 destmem = change_address (destmem, QImode, destptr);
13445 emit_insn (gen_strset (destptr, destmem, gen_lowpart (QImode, value)));
13446 ix86_adjust_counter (count, 1);
13447 emit_label (label);
13448 LABEL_NUSES (label) = 1;
13450 if (align <= 2 && desired_alignment > 2)
13452 rtx label = ix86_expand_aligntest (destptr, 2, false);
13453 destmem = change_address (destmem, HImode, destptr);
13454 emit_insn (gen_strset (destptr, destmem, gen_lowpart (HImode, value)));
13455 ix86_adjust_counter (count, 2);
13456 emit_label (label);
13457 LABEL_NUSES (label) = 1;
13459 if (align <= 4 && desired_alignment > 4)
13461 rtx label = ix86_expand_aligntest (destptr, 4, false);
13462 destmem = change_address (destmem, SImode, destptr);
13463 emit_insn (gen_strset (destptr, destmem, gen_lowpart (SImode, value)));
13464 ix86_adjust_counter (count, 4);
13465 emit_label (label);
13466 LABEL_NUSES (label) = 1;
13468 gcc_assert (desired_alignment <= 8);
13471 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
13472 static enum stringop_alg
13473 decide_alg (HOST_WIDE_INT count, HOST_WIDE_INT expected_size, bool memset,
13474 int *dynamic_check)
13476 const struct stringop_algs * algs;
13478 *dynamic_check = -1;
13480 algs = &ix86_cost->memset[TARGET_64BIT != 0];
13482 algs = &ix86_cost->memcpy[TARGET_64BIT != 0];
13483 if (stringop_alg != no_stringop)
13484 return stringop_alg;
13485 /* rep; movq or rep; movl is the smallest variant. */
13486 else if (optimize_size)
13488 if (!count || (count & 3))
13489 return rep_prefix_1_byte;
13491 return rep_prefix_4_byte;
13493 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
13495 else if (expected_size != -1 && expected_size < 4)
13496 return loop_1_byte;
13497 else if (expected_size != -1)
13500 enum stringop_alg alg = libcall;
13501 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
13503 gcc_assert (algs->size[i].max);
13504 if (algs->size[i].max >= expected_size || algs->size[i].max == -1)
13506 if (algs->size[i].alg != libcall)
13507 alg = algs->size[i].alg;
13508 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
13509 last non-libcall inline algorithm. */
13510 if (TARGET_INLINE_ALL_STRINGOPS)
13512 /* When the current size is best to be copied by a libcall,
13513 but we are still forced to inline, run the heuristic bellow
13514 that will pick code for medium sized blocks. */
13515 if (alg != libcall)
13520 return algs->size[i].alg;
13523 gcc_assert (TARGET_INLINE_ALL_STRINGOPS);
13525 /* When asked to inline the call anyway, try to pick meaningful choice.
13526 We look for maximal size of block that is faster to copy by hand and
13527 take blocks of at most of that size guessing that average size will
13528 be roughly half of the block.
13530 If this turns out to be bad, we might simply specify the preferred
13531 choice in ix86_costs. */
13532 if ((TARGET_INLINE_ALL_STRINGOPS || TARGET_INLINE_STRINGOPS_DYNAMICALLY)
13533 && algs->unknown_size == libcall)
13536 enum stringop_alg alg;
13539 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
13540 if (algs->size[i].alg != libcall && algs->size[i].alg)
13541 max = algs->size[i].max;
13544 alg = decide_alg (count, max / 2, memset, dynamic_check);
13545 gcc_assert (*dynamic_check == -1);
13546 gcc_assert (alg != libcall);
13547 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
13548 *dynamic_check = max;
13551 return algs->unknown_size;
13554 /* Decide on alignment. We know that the operand is already aligned to ALIGN
13555 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
13557 decide_alignment (int align,
13558 enum stringop_alg alg,
13561 int desired_align = 0;
13565 gcc_unreachable ();
13567 case unrolled_loop:
13568 desired_align = GET_MODE_SIZE (Pmode);
13570 case rep_prefix_8_byte:
13573 case rep_prefix_4_byte:
13574 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
13575 copying whole cacheline at once. */
13576 if (TARGET_PENTIUMPRO)
13581 case rep_prefix_1_byte:
13582 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
13583 copying whole cacheline at once. */
13584 if (TARGET_PENTIUMPRO)
13598 if (desired_align < align)
13599 desired_align = align;
13600 if (expected_size != -1 && expected_size < 4)
13601 desired_align = align;
13602 return desired_align;
13605 /* Expand string move (memcpy) operation. Use i386 string operations when
13606 profitable. expand_clrmem contains similar code. */
13608 ix86_expand_movmem (rtx dst, rtx src, rtx count_exp, rtx align_exp,
13609 rtx expected_align_exp, rtx expected_size_exp)
13615 rtx jump_around_label = NULL;
13616 HOST_WIDE_INT align = 1;
13617 unsigned HOST_WIDE_INT count = 0;
13618 HOST_WIDE_INT expected_size = -1;
13619 int size_needed = 0;
13620 int desired_align = 0;
13621 enum stringop_alg alg;
13623 /* Precise placement on cld depends whether stringops will be emit in
13624 prologue, main copying body or epilogue. This variable keeps track
13625 if cld was already needed. */
13626 bool cld_done = false;
13628 if (GET_CODE (align_exp) == CONST_INT)
13629 align = INTVAL (align_exp);
13630 /* i386 can do misaligned access on reasonably increased cost. */
13631 if (GET_CODE (expected_align_exp) == CONST_INT
13632 && INTVAL (expected_align_exp) > align)
13633 align = INTVAL (expected_align_exp);
13634 if (GET_CODE (count_exp) == CONST_INT)
13635 count = expected_size = INTVAL (count_exp);
13636 if (GET_CODE (expected_size_exp) == CONST_INT && count == 0)
13638 expected_size = INTVAL (expected_size_exp);
13641 alg = decide_alg (count, expected_size, false, &dynamic_check);
13642 desired_align = decide_alignment (align, alg, expected_size);
13644 if (!TARGET_ALIGN_STRINGOPS)
13645 align = desired_align;
13647 if (alg == libcall)
13649 gcc_assert (alg != no_stringop);
13651 count_exp = copy_to_mode_reg (GET_MODE (count_exp), count_exp);
13652 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
13653 srcreg = copy_to_mode_reg (Pmode, XEXP (src, 0));
13658 gcc_unreachable ();
13660 size_needed = GET_MODE_SIZE (Pmode);
13662 case unrolled_loop:
13663 size_needed = GET_MODE_SIZE (Pmode) * (TARGET_64BIT ? 4 : 2);
13665 case rep_prefix_8_byte:
13668 case rep_prefix_4_byte:
13671 case rep_prefix_1_byte:
13677 /* Alignment code needs count to be in register. */
13678 if (GET_CODE (count_exp) == CONST_INT && desired_align > align)
13680 enum machine_mode mode = SImode;
13681 if (TARGET_64BIT && (count & ~0xffffffff))
13683 count_exp = force_reg (mode, count_exp);
13685 gcc_assert (desired_align >= 1 && align >= 1);
13686 /* Ensure that alignment prologue won't copy past end of block. */
13687 if ((size_needed > 1 || (desired_align > 1 && desired_align > align))
13690 int size = MAX (size_needed - 1, desired_align - align);
13691 if (TARGET_SINGLE_STRINGOP)
13692 emit_insn (gen_cld ()), cld_done = true;
13693 label = gen_label_rtx ();
13694 emit_cmp_and_jump_insns (count_exp,
13696 LEU, 0, GET_MODE (count_exp), 1, label);
13697 if (expected_size == -1 || expected_size < size)
13698 predict_jump (REG_BR_PROB_BASE * 60 / 100);
13700 predict_jump (REG_BR_PROB_BASE * 20 / 100);
13702 /* Emit code to decide on runtime whether library call or inline should be
13704 if (dynamic_check != -1)
13706 rtx hot_label = gen_label_rtx ();
13707 jump_around_label = gen_label_rtx ();
13708 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
13709 LEU, 0, GET_MODE (count_exp), 1, hot_label);
13710 predict_jump (REG_BR_PROB_BASE * 90 / 100);
13711 emit_block_move_via_libcall (dst, src, count_exp, false);
13712 emit_jump (jump_around_label);
13713 emit_label (hot_label);
13717 /* Alignment prologue. */
13718 if (desired_align > align)
13720 /* Except for the first move in epilogue, we no longer know
13721 constant offset in aliasing info. It don't seems to worth
13722 the pain to maintain it for the first move, so throw away
13724 src = change_address (src, BLKmode, srcreg);
13725 dst = change_address (dst, BLKmode, destreg);
13726 if (TARGET_SINGLE_STRINGOP && !cld_done)
13727 emit_insn (gen_cld ()), cld_done = true;
13728 expand_movmem_prologue (dst, src, destreg, srcreg, count_exp, align,
13731 if (label && size_needed == 1)
13733 emit_label (label);
13734 LABEL_NUSES (label) = 1;
13743 gcc_unreachable ();
13745 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
13746 count_exp, QImode, 1, expected_size);
13749 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
13750 count_exp, Pmode, 1, expected_size);
13752 case unrolled_loop:
13753 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
13754 registers for 4 temporaries anyway. */
13755 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
13756 count_exp, Pmode, TARGET_64BIT ? 4 : 2,
13759 case rep_prefix_8_byte:
13761 emit_insn (gen_cld ()), cld_done = true;
13762 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
13765 case rep_prefix_4_byte:
13767 emit_insn (gen_cld ()), cld_done = true;
13768 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
13771 case rep_prefix_1_byte:
13773 emit_insn (gen_cld ()), cld_done = true;
13774 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
13778 /* Adjust properly the offset of src and dest memory for aliasing. */
13779 if (GET_CODE (count_exp) == CONST_INT)
13781 src = adjust_automodify_address_nv (src, BLKmode, srcreg,
13782 (count / size_needed) * size_needed);
13783 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
13784 (count / size_needed) * size_needed);
13788 src = change_address (src, BLKmode, srcreg);
13789 dst = change_address (dst, BLKmode, destreg);
13792 /* Epilogue to copy the remaining bytes. */
13795 if (size_needed < desired_align - align)
13798 expand_simple_binop (GET_MODE (count_exp), AND, count_exp,
13799 GEN_INT (size_needed - 1), count_exp, 1,
13801 size_needed = desired_align - align + 1;
13802 if (tmp != count_exp)
13803 emit_move_insn (count_exp, tmp);
13805 emit_label (label);
13806 LABEL_NUSES (label) = 1;
13808 if (count_exp != const0_rtx && size_needed > 1)
13810 if (TARGET_SINGLE_STRINGOP && !cld_done)
13811 emit_insn (gen_cld ()), cld_done = true;
13812 expand_movmem_epilogue (dst, src, destreg, srcreg, count_exp,
13815 if (jump_around_label)
13816 emit_label (jump_around_label);
13820 /* Helper function for memcpy. For QImode value 0xXY produce
13821 0xXYXYXYXY of wide specified by MODE. This is essentially
13822 a * 0x10101010, but we can do slightly better than
13823 synth_mult by unwinding the sequence by hand on CPUs with
13826 promote_duplicated_reg (enum machine_mode mode, rtx val)
13828 enum machine_mode valmode = GET_MODE (val);
13830 int nops = mode == DImode ? 3 : 2;
13832 gcc_assert (mode == SImode || mode == DImode);
13833 if (val == const0_rtx)
13834 return copy_to_mode_reg (mode, const0_rtx);
13835 if (GET_CODE (val) == CONST_INT)
13837 HOST_WIDE_INT v = INTVAL (val) & 255;
13841 if (mode == DImode)
13842 v |= (v << 16) << 16;
13843 return copy_to_mode_reg (mode, gen_int_mode (v, mode));
13846 if (valmode == VOIDmode)
13848 if (valmode != QImode)
13849 val = gen_lowpart (QImode, val);
13850 if (mode == QImode)
13852 if (!TARGET_PARTIAL_REG_STALL)
13854 if (ix86_cost->mult_init[mode == DImode ? 3 : 2]
13855 + ix86_cost->mult_bit * (mode == DImode ? 8 : 4)
13856 <= (ix86_cost->shift_const + ix86_cost->add) * nops
13857 + (COSTS_N_INSNS (TARGET_PARTIAL_REG_STALL == 0)))
13859 rtx reg = convert_modes (mode, QImode, val, true);
13860 tmp = promote_duplicated_reg (mode, const1_rtx);
13861 return expand_simple_binop (mode, MULT, reg, tmp, NULL, 1,
13866 rtx reg = convert_modes (mode, QImode, val, true);
13868 if (!TARGET_PARTIAL_REG_STALL)
13869 if (mode == SImode)
13870 emit_insn (gen_movsi_insv_1 (reg, reg));
13872 emit_insn (gen_movdi_insv_1_rex64 (reg, reg));
13875 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (8),
13876 NULL, 1, OPTAB_DIRECT);
13878 expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
13880 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (16),
13881 NULL, 1, OPTAB_DIRECT);
13882 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
13883 if (mode == SImode)
13885 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (32),
13886 NULL, 1, OPTAB_DIRECT);
13887 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
13892 /* Expand string clear operation (bzero). Use i386 string operations when
13893 profitable. expand_movmem contains similar code. */
13895 ix86_expand_setmem (rtx dst, rtx count_exp, rtx val_exp, rtx align_exp,
13896 rtx expected_align_exp, rtx expected_size_exp)
13901 rtx jump_around_label = NULL;
13902 HOST_WIDE_INT align = 1;
13903 unsigned HOST_WIDE_INT count = 0;
13904 HOST_WIDE_INT expected_size = -1;
13905 int size_needed = 0;
13906 int desired_align = 0;
13907 enum stringop_alg alg;
13908 /* Precise placement on cld depends whether stringops will be emit in
13909 prologue, main copying body or epilogue. This variable keeps track
13910 if cld was already needed. */
13911 bool cld_done = false;
13912 rtx promoted_val = val_exp;
13913 bool force_loopy_epilogue = false;
13916 if (GET_CODE (align_exp) == CONST_INT)
13917 align = INTVAL (align_exp);
13918 /* i386 can do misaligned access on reasonably increased cost. */
13919 if (GET_CODE (expected_align_exp) == CONST_INT
13920 && INTVAL (expected_align_exp) > align)
13921 align = INTVAL (expected_align_exp);
13922 if (GET_CODE (count_exp) == CONST_INT)
13923 count = expected_size = INTVAL (count_exp);
13924 if (GET_CODE (expected_size_exp) == CONST_INT && count == 0)
13925 expected_size = INTVAL (expected_size_exp);
13927 alg = decide_alg (count, expected_size, true, &dynamic_check);
13928 desired_align = decide_alignment (align, alg, expected_size);
13930 if (!TARGET_ALIGN_STRINGOPS)
13931 align = desired_align;
13933 if (alg == libcall)
13935 gcc_assert (alg != no_stringop);
13937 count_exp = copy_to_mode_reg (GET_MODE (count_exp), count_exp);
13938 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
13943 gcc_unreachable ();
13945 size_needed = GET_MODE_SIZE (Pmode);
13947 case unrolled_loop:
13948 size_needed = GET_MODE_SIZE (Pmode) * 4;
13950 case rep_prefix_8_byte:
13953 case rep_prefix_4_byte:
13956 case rep_prefix_1_byte:
13961 /* Alignment code needs count to be in register. */
13962 if (GET_CODE (count_exp) == CONST_INT && desired_align > align)
13964 enum machine_mode mode = SImode;
13965 if (TARGET_64BIT && (count & ~0xffffffff))
13967 count_exp = force_reg (mode, count_exp);
13969 /* Ensure that alignment prologue won't copy past end of block. */
13970 if ((size_needed > 1 || (desired_align > 1 && desired_align > align))
13973 int size = MAX (size_needed - 1, desired_align - align);
13974 /* To improve performance of small blocks, we jump around the promoting
13975 code, so we need to use QImode accesses in epilogue. */
13976 if (GET_CODE (val_exp) != CONST_INT && size_needed > 1)
13977 force_loopy_epilogue = true;
13978 else if (TARGET_SINGLE_STRINGOP)
13979 emit_insn (gen_cld ()), cld_done = true;
13980 label = gen_label_rtx ();
13981 emit_cmp_and_jump_insns (count_exp,
13983 LEU, 0, GET_MODE (count_exp), 1, label);
13984 if (expected_size == -1 || expected_size <= size)
13985 predict_jump (REG_BR_PROB_BASE * 60 / 100);
13987 predict_jump (REG_BR_PROB_BASE * 20 / 100);
13989 if (dynamic_check != -1)
13991 rtx hot_label = gen_label_rtx ();
13992 jump_around_label = gen_label_rtx ();
13993 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
13994 LEU, 0, GET_MODE (count_exp), 1, hot_label);
13995 predict_jump (REG_BR_PROB_BASE * 90 / 100);
13996 set_storage_via_libcall (dst, count_exp, val_exp, false);
13997 emit_jump (jump_around_label);
13998 emit_label (hot_label);
14001 && (size_needed > 4 || (desired_align > align && desired_align > 4)))
14002 promoted_val = promote_duplicated_reg (DImode, val_exp);
14003 else if (size_needed > 2 || (desired_align > align && desired_align > 2))
14004 promoted_val = promote_duplicated_reg (SImode, val_exp);
14005 else if (size_needed > 1 || (desired_align > align && desired_align > 1))
14006 promoted_val = promote_duplicated_reg (HImode, val_exp);
14008 promoted_val = val_exp;
14009 gcc_assert (desired_align >= 1 && align >= 1);
14010 if ((size_needed > 1 || (desired_align > 1 && desired_align > align))
14011 && !count && !label)
14013 int size = MAX (size_needed - 1, desired_align - align);
14014 if (TARGET_SINGLE_STRINGOP)
14015 emit_insn (gen_cld ()), cld_done = true;
14016 label = gen_label_rtx ();
14017 emit_cmp_and_jump_insns (count_exp,
14019 LEU, 0, GET_MODE (count_exp), 1, label);
14020 if (expected_size == -1 || expected_size <= size)
14021 predict_jump (REG_BR_PROB_BASE * 60 / 100);
14023 predict_jump (REG_BR_PROB_BASE * 20 / 100);
14025 if (desired_align > align)
14027 /* Except for the first move in epilogue, we no longer know
14028 constant offset in aliasing info. It don't seems to worth
14029 the pain to maintain it for the first move, so throw away
14031 dst = change_address (dst, BLKmode, destreg);
14032 if (TARGET_SINGLE_STRINGOP && !cld_done)
14033 emit_insn (gen_cld ()), cld_done = true;
14034 expand_setmem_prologue (dst, destreg, promoted_val, count_exp, align,
14037 if (label && size_needed == 1)
14039 emit_label (label);
14040 LABEL_NUSES (label) = 1;
14047 gcc_unreachable ();
14049 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
14050 count_exp, QImode, 1, expected_size);
14053 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
14054 count_exp, Pmode, 1, expected_size);
14056 case unrolled_loop:
14057 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
14058 count_exp, Pmode, 4, expected_size);
14060 case rep_prefix_8_byte:
14062 emit_insn (gen_cld ()), cld_done = true;
14063 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
14066 case rep_prefix_4_byte:
14068 emit_insn (gen_cld ()), cld_done = true;
14069 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
14072 case rep_prefix_1_byte:
14074 emit_insn (gen_cld ()), cld_done = true;
14075 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
14079 /* Adjust properly the offset of src and dest memory for aliasing. */
14080 if (GET_CODE (count_exp) == CONST_INT)
14081 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
14082 (count / size_needed) * size_needed);
14084 dst = change_address (dst, BLKmode, destreg);
14088 if (size_needed < desired_align - align)
14091 expand_simple_binop (GET_MODE (count_exp), AND, count_exp,
14092 GEN_INT (size_needed - 1), count_exp, 1,
14094 size_needed = desired_align - align + 1;
14095 if (tmp != count_exp)
14096 emit_move_insn (count_exp, tmp);
14098 emit_label (label);
14099 LABEL_NUSES (label) = 1;
14101 if (count_exp != const0_rtx && size_needed > 1)
14103 if (force_loopy_epilogue)
14104 expand_setmem_epilogue_via_loop (dst, destreg, val_exp, count_exp,
14108 if (TARGET_SINGLE_STRINGOP && !cld_done)
14109 emit_insn (gen_cld ()), cld_done = true;
14110 expand_setmem_epilogue (dst, destreg, promoted_val, count_exp,
14114 if (jump_around_label)
14115 emit_label (jump_around_label);
14119 /* Expand strlen. */
14121 ix86_expand_strlen (rtx out, rtx src, rtx eoschar, rtx align)
14123 rtx addr, scratch1, scratch2, scratch3, scratch4;
14125 /* The generic case of strlen expander is long. Avoid it's
14126 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
14128 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
14129 && !TARGET_INLINE_ALL_STRINGOPS
14131 && (GET_CODE (align) != CONST_INT || INTVAL (align) < 4))
14134 addr = force_reg (Pmode, XEXP (src, 0));
14135 scratch1 = gen_reg_rtx (Pmode);
14137 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
14140 /* Well it seems that some optimizer does not combine a call like
14141 foo(strlen(bar), strlen(bar));
14142 when the move and the subtraction is done here. It does calculate
14143 the length just once when these instructions are done inside of
14144 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
14145 often used and I use one fewer register for the lifetime of
14146 output_strlen_unroll() this is better. */
14148 emit_move_insn (out, addr);
14150 ix86_expand_strlensi_unroll_1 (out, src, align);
14152 /* strlensi_unroll_1 returns the address of the zero at the end of
14153 the string, like memchr(), so compute the length by subtracting
14154 the start address. */
14156 emit_insn (gen_subdi3 (out, out, addr));
14158 emit_insn (gen_subsi3 (out, out, addr));
14163 scratch2 = gen_reg_rtx (Pmode);
14164 scratch3 = gen_reg_rtx (Pmode);
14165 scratch4 = force_reg (Pmode, constm1_rtx);
14167 emit_move_insn (scratch3, addr);
14168 eoschar = force_reg (QImode, eoschar);
14170 emit_insn (gen_cld ());
14171 src = replace_equiv_address_nv (src, scratch3);
14173 /* If .md starts supporting :P, this can be done in .md. */
14174 unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (4, src, eoschar, align,
14175 scratch4), UNSPEC_SCAS);
14176 emit_insn (gen_strlenqi_1 (scratch1, scratch3, unspec));
14179 emit_insn (gen_one_cmpldi2 (scratch2, scratch1));
14180 emit_insn (gen_adddi3 (out, scratch2, constm1_rtx));
14184 emit_insn (gen_one_cmplsi2 (scratch2, scratch1));
14185 emit_insn (gen_addsi3 (out, scratch2, constm1_rtx));
14191 /* Expand the appropriate insns for doing strlen if not just doing
14194 out = result, initialized with the start address
14195 align_rtx = alignment of the address.
14196 scratch = scratch register, initialized with the startaddress when
14197 not aligned, otherwise undefined
14199 This is just the body. It needs the initializations mentioned above and
14200 some address computing at the end. These things are done in i386.md. */
14203 ix86_expand_strlensi_unroll_1 (rtx out, rtx src, rtx align_rtx)
14207 rtx align_2_label = NULL_RTX;
14208 rtx align_3_label = NULL_RTX;
14209 rtx align_4_label = gen_label_rtx ();
14210 rtx end_0_label = gen_label_rtx ();
14212 rtx tmpreg = gen_reg_rtx (SImode);
14213 rtx scratch = gen_reg_rtx (SImode);
14217 if (GET_CODE (align_rtx) == CONST_INT)
14218 align = INTVAL (align_rtx);
14220 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
14222 /* Is there a known alignment and is it less than 4? */
14225 rtx scratch1 = gen_reg_rtx (Pmode);
14226 emit_move_insn (scratch1, out);
14227 /* Is there a known alignment and is it not 2? */
14230 align_3_label = gen_label_rtx (); /* Label when aligned to 3-byte */
14231 align_2_label = gen_label_rtx (); /* Label when aligned to 2-byte */
14233 /* Leave just the 3 lower bits. */
14234 align_rtx = expand_binop (Pmode, and_optab, scratch1, GEN_INT (3),
14235 NULL_RTX, 0, OPTAB_WIDEN);
14237 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
14238 Pmode, 1, align_4_label);
14239 emit_cmp_and_jump_insns (align_rtx, const2_rtx, EQ, NULL,
14240 Pmode, 1, align_2_label);
14241 emit_cmp_and_jump_insns (align_rtx, const2_rtx, GTU, NULL,
14242 Pmode, 1, align_3_label);
14246 /* Since the alignment is 2, we have to check 2 or 0 bytes;
14247 check if is aligned to 4 - byte. */
14249 align_rtx = expand_binop (Pmode, and_optab, scratch1, const2_rtx,
14250 NULL_RTX, 0, OPTAB_WIDEN);
14252 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
14253 Pmode, 1, align_4_label);
14256 mem = change_address (src, QImode, out);
14258 /* Now compare the bytes. */
14260 /* Compare the first n unaligned byte on a byte per byte basis. */
14261 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL,
14262 QImode, 1, end_0_label);
14264 /* Increment the address. */
14266 emit_insn (gen_adddi3 (out, out, const1_rtx));
14268 emit_insn (gen_addsi3 (out, out, const1_rtx));
14270 /* Not needed with an alignment of 2 */
14273 emit_label (align_2_label);
14275 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
14279 emit_insn (gen_adddi3 (out, out, const1_rtx));
14281 emit_insn (gen_addsi3 (out, out, const1_rtx));
14283 emit_label (align_3_label);
14286 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
14290 emit_insn (gen_adddi3 (out, out, const1_rtx));
14292 emit_insn (gen_addsi3 (out, out, const1_rtx));
14295 /* Generate loop to check 4 bytes at a time. It is not a good idea to
14296 align this loop. It gives only huge programs, but does not help to
14298 emit_label (align_4_label);
14300 mem = change_address (src, SImode, out);
14301 emit_move_insn (scratch, mem);
14303 emit_insn (gen_adddi3 (out, out, GEN_INT (4)));
14305 emit_insn (gen_addsi3 (out, out, GEN_INT (4)));
14307 /* This formula yields a nonzero result iff one of the bytes is zero.
14308 This saves three branches inside loop and many cycles. */
14310 emit_insn (gen_addsi3 (tmpreg, scratch, GEN_INT (-0x01010101)));
14311 emit_insn (gen_one_cmplsi2 (scratch, scratch));
14312 emit_insn (gen_andsi3 (tmpreg, tmpreg, scratch));
14313 emit_insn (gen_andsi3 (tmpreg, tmpreg,
14314 gen_int_mode (0x80808080, SImode)));
14315 emit_cmp_and_jump_insns (tmpreg, const0_rtx, EQ, 0, SImode, 1,
14320 rtx reg = gen_reg_rtx (SImode);
14321 rtx reg2 = gen_reg_rtx (Pmode);
14322 emit_move_insn (reg, tmpreg);
14323 emit_insn (gen_lshrsi3 (reg, reg, GEN_INT (16)));
14325 /* If zero is not in the first two bytes, move two bytes forward. */
14326 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
14327 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
14328 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
14329 emit_insn (gen_rtx_SET (VOIDmode, tmpreg,
14330 gen_rtx_IF_THEN_ELSE (SImode, tmp,
14333 /* Emit lea manually to avoid clobbering of flags. */
14334 emit_insn (gen_rtx_SET (SImode, reg2,
14335 gen_rtx_PLUS (Pmode, out, const2_rtx)));
14337 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
14338 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
14339 emit_insn (gen_rtx_SET (VOIDmode, out,
14340 gen_rtx_IF_THEN_ELSE (Pmode, tmp,
14347 rtx end_2_label = gen_label_rtx ();
14348 /* Is zero in the first two bytes? */
14350 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
14351 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
14352 tmp = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
14353 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
14354 gen_rtx_LABEL_REF (VOIDmode, end_2_label),
14356 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
14357 JUMP_LABEL (tmp) = end_2_label;
14359 /* Not in the first two. Move two bytes forward. */
14360 emit_insn (gen_lshrsi3 (tmpreg, tmpreg, GEN_INT (16)));
14362 emit_insn (gen_adddi3 (out, out, const2_rtx));
14364 emit_insn (gen_addsi3 (out, out, const2_rtx));
14366 emit_label (end_2_label);
14370 /* Avoid branch in fixing the byte. */
14371 tmpreg = gen_lowpart (QImode, tmpreg);
14372 emit_insn (gen_addqi3_cc (tmpreg, tmpreg, tmpreg));
14373 cmp = gen_rtx_LTU (Pmode, gen_rtx_REG (CCmode, 17), const0_rtx);
14375 emit_insn (gen_subdi3_carry_rex64 (out, out, GEN_INT (3), cmp));
14377 emit_insn (gen_subsi3_carry (out, out, GEN_INT (3), cmp));
14379 emit_label (end_0_label);
14383 ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
14384 rtx callarg2 ATTRIBUTE_UNUSED,
14385 rtx pop, int sibcall)
14387 rtx use = NULL, call;
14389 if (pop == const0_rtx)
14391 gcc_assert (!TARGET_64BIT || !pop);
14393 if (TARGET_MACHO && !TARGET_64BIT)
14396 if (flag_pic && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF)
14397 fnaddr = machopic_indirect_call_target (fnaddr);
14402 /* Static functions and indirect calls don't need the pic register. */
14403 if (! TARGET_64BIT && flag_pic
14404 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
14405 && ! SYMBOL_REF_LOCAL_P (XEXP (fnaddr, 0)))
14406 use_reg (&use, pic_offset_table_rtx);
14409 if (TARGET_64BIT && INTVAL (callarg2) >= 0)
14411 rtx al = gen_rtx_REG (QImode, 0);
14412 emit_move_insn (al, callarg2);
14413 use_reg (&use, al);
14416 if (! call_insn_operand (XEXP (fnaddr, 0), Pmode))
14418 fnaddr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
14419 fnaddr = gen_rtx_MEM (QImode, fnaddr);
14421 if (sibcall && TARGET_64BIT
14422 && !constant_call_address_operand (XEXP (fnaddr, 0), Pmode))
14425 addr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
14426 fnaddr = gen_rtx_REG (Pmode, R11_REG);
14427 emit_move_insn (fnaddr, addr);
14428 fnaddr = gen_rtx_MEM (QImode, fnaddr);
14431 call = gen_rtx_CALL (VOIDmode, fnaddr, callarg1);
14433 call = gen_rtx_SET (VOIDmode, retval, call);
14436 pop = gen_rtx_PLUS (Pmode, stack_pointer_rtx, pop);
14437 pop = gen_rtx_SET (VOIDmode, stack_pointer_rtx, pop);
14438 call = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, call, pop));
14441 call = emit_call_insn (call);
14443 CALL_INSN_FUNCTION_USAGE (call) = use;
14447 /* Clear stack slot assignments remembered from previous functions.
14448 This is called from INIT_EXPANDERS once before RTL is emitted for each
14451 static struct machine_function *
14452 ix86_init_machine_status (void)
14454 struct machine_function *f;
14456 f = ggc_alloc_cleared (sizeof (struct machine_function));
14457 f->use_fast_prologue_epilogue_nregs = -1;
14458 f->tls_descriptor_call_expanded_p = 0;
14463 /* Return a MEM corresponding to a stack slot with mode MODE.
14464 Allocate a new slot if necessary.
14466 The RTL for a function can have several slots available: N is
14467 which slot to use. */
14470 assign_386_stack_local (enum machine_mode mode, enum ix86_stack_slot n)
14472 struct stack_local_entry *s;
14474 gcc_assert (n < MAX_386_STACK_LOCALS);
14476 for (s = ix86_stack_locals; s; s = s->next)
14477 if (s->mode == mode && s->n == n)
14478 return copy_rtx (s->rtl);
14480 s = (struct stack_local_entry *)
14481 ggc_alloc (sizeof (struct stack_local_entry));
14484 s->rtl = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
14486 s->next = ix86_stack_locals;
14487 ix86_stack_locals = s;
14491 /* Construct the SYMBOL_REF for the tls_get_addr function. */
14493 static GTY(()) rtx ix86_tls_symbol;
14495 ix86_tls_get_addr (void)
14498 if (!ix86_tls_symbol)
14500 ix86_tls_symbol = gen_rtx_SYMBOL_REF (Pmode,
14501 (TARGET_ANY_GNU_TLS
14503 ? "___tls_get_addr"
14504 : "__tls_get_addr");
14507 return ix86_tls_symbol;
14510 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
14512 static GTY(()) rtx ix86_tls_module_base_symbol;
14514 ix86_tls_module_base (void)
14517 if (!ix86_tls_module_base_symbol)
14519 ix86_tls_module_base_symbol = gen_rtx_SYMBOL_REF (Pmode,
14520 "_TLS_MODULE_BASE_");
14521 SYMBOL_REF_FLAGS (ix86_tls_module_base_symbol)
14522 |= TLS_MODEL_GLOBAL_DYNAMIC << SYMBOL_FLAG_TLS_SHIFT;
14525 return ix86_tls_module_base_symbol;
14528 /* Calculate the length of the memory address in the instruction
14529 encoding. Does not include the one-byte modrm, opcode, or prefix. */
14532 memory_address_length (rtx addr)
14534 struct ix86_address parts;
14535 rtx base, index, disp;
14539 if (GET_CODE (addr) == PRE_DEC
14540 || GET_CODE (addr) == POST_INC
14541 || GET_CODE (addr) == PRE_MODIFY
14542 || GET_CODE (addr) == POST_MODIFY)
14545 ok = ix86_decompose_address (addr, &parts);
14548 if (parts.base && GET_CODE (parts.base) == SUBREG)
14549 parts.base = SUBREG_REG (parts.base);
14550 if (parts.index && GET_CODE (parts.index) == SUBREG)
14551 parts.index = SUBREG_REG (parts.index);
14554 index = parts.index;
14559 - esp as the base always wants an index,
14560 - ebp as the base always wants a displacement. */
14562 /* Register Indirect. */
14563 if (base && !index && !disp)
14565 /* esp (for its index) and ebp (for its displacement) need
14566 the two-byte modrm form. */
14567 if (addr == stack_pointer_rtx
14568 || addr == arg_pointer_rtx
14569 || addr == frame_pointer_rtx
14570 || addr == hard_frame_pointer_rtx)
14574 /* Direct Addressing. */
14575 else if (disp && !base && !index)
14580 /* Find the length of the displacement constant. */
14583 if (base && satisfies_constraint_K (disp))
14588 /* ebp always wants a displacement. */
14589 else if (base == hard_frame_pointer_rtx)
14592 /* An index requires the two-byte modrm form.... */
14594 /* ...like esp, which always wants an index. */
14595 || base == stack_pointer_rtx
14596 || base == arg_pointer_rtx
14597 || base == frame_pointer_rtx)
14604 /* Compute default value for "length_immediate" attribute. When SHORTFORM
14605 is set, expect that insn have 8bit immediate alternative. */
14607 ix86_attr_length_immediate_default (rtx insn, int shortform)
14611 extract_insn_cached (insn);
14612 for (i = recog_data.n_operands - 1; i >= 0; --i)
14613 if (CONSTANT_P (recog_data.operand[i]))
14616 if (shortform && satisfies_constraint_K (recog_data.operand[i]))
14620 switch (get_attr_mode (insn))
14631 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
14636 fatal_insn ("unknown insn mode", insn);
14642 /* Compute default value for "length_address" attribute. */
14644 ix86_attr_length_address_default (rtx insn)
14648 if (get_attr_type (insn) == TYPE_LEA)
14650 rtx set = PATTERN (insn);
14652 if (GET_CODE (set) == PARALLEL)
14653 set = XVECEXP (set, 0, 0);
14655 gcc_assert (GET_CODE (set) == SET);
14657 return memory_address_length (SET_SRC (set));
14660 extract_insn_cached (insn);
14661 for (i = recog_data.n_operands - 1; i >= 0; --i)
14662 if (GET_CODE (recog_data.operand[i]) == MEM)
14664 return memory_address_length (XEXP (recog_data.operand[i], 0));
14670 /* Return the maximum number of instructions a cpu can issue. */
14673 ix86_issue_rate (void)
14677 case PROCESSOR_PENTIUM:
14681 case PROCESSOR_PENTIUMPRO:
14682 case PROCESSOR_PENTIUM4:
14683 case PROCESSOR_ATHLON:
14685 case PROCESSOR_NOCONA:
14686 case PROCESSOR_GENERIC32:
14687 case PROCESSOR_GENERIC64:
14690 case PROCESSOR_CORE2:
14698 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
14699 by DEP_INSN and nothing set by DEP_INSN. */
14702 ix86_flags_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
14706 /* Simplify the test for uninteresting insns. */
14707 if (insn_type != TYPE_SETCC
14708 && insn_type != TYPE_ICMOV
14709 && insn_type != TYPE_FCMOV
14710 && insn_type != TYPE_IBR)
14713 if ((set = single_set (dep_insn)) != 0)
14715 set = SET_DEST (set);
14718 else if (GET_CODE (PATTERN (dep_insn)) == PARALLEL
14719 && XVECLEN (PATTERN (dep_insn), 0) == 2
14720 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 0)) == SET
14721 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 1)) == SET)
14723 set = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
14724 set2 = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
14729 if (GET_CODE (set) != REG || REGNO (set) != FLAGS_REG)
14732 /* This test is true if the dependent insn reads the flags but
14733 not any other potentially set register. */
14734 if (!reg_overlap_mentioned_p (set, PATTERN (insn)))
14737 if (set2 && reg_overlap_mentioned_p (set2, PATTERN (insn)))
14743 /* A subroutine of ix86_adjust_cost -- return true iff INSN has a memory
14744 address with operands set by DEP_INSN. */
14747 ix86_agi_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
14751 if (insn_type == TYPE_LEA
14754 addr = PATTERN (insn);
14756 if (GET_CODE (addr) == PARALLEL)
14757 addr = XVECEXP (addr, 0, 0);
14759 gcc_assert (GET_CODE (addr) == SET);
14761 addr = SET_SRC (addr);
14766 extract_insn_cached (insn);
14767 for (i = recog_data.n_operands - 1; i >= 0; --i)
14768 if (GET_CODE (recog_data.operand[i]) == MEM)
14770 addr = XEXP (recog_data.operand[i], 0);
14777 return modified_in_p (addr, dep_insn);
14781 ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
14783 enum attr_type insn_type, dep_insn_type;
14784 enum attr_memory memory;
14786 int dep_insn_code_number;
14788 /* Anti and output dependencies have zero cost on all CPUs. */
14789 if (REG_NOTE_KIND (link) != 0)
14792 dep_insn_code_number = recog_memoized (dep_insn);
14794 /* If we can't recognize the insns, we can't really do anything. */
14795 if (dep_insn_code_number < 0 || recog_memoized (insn) < 0)
14798 insn_type = get_attr_type (insn);
14799 dep_insn_type = get_attr_type (dep_insn);
14803 case PROCESSOR_PENTIUM:
14804 /* Address Generation Interlock adds a cycle of latency. */
14805 if (ix86_agi_dependent (insn, dep_insn, insn_type))
14808 /* ??? Compares pair with jump/setcc. */
14809 if (ix86_flags_dependent (insn, dep_insn, insn_type))
14812 /* Floating point stores require value to be ready one cycle earlier. */
14813 if (insn_type == TYPE_FMOV
14814 && get_attr_memory (insn) == MEMORY_STORE
14815 && !ix86_agi_dependent (insn, dep_insn, insn_type))
14819 case PROCESSOR_PENTIUMPRO:
14820 memory = get_attr_memory (insn);
14822 /* INT->FP conversion is expensive. */
14823 if (get_attr_fp_int_src (dep_insn))
14826 /* There is one cycle extra latency between an FP op and a store. */
14827 if (insn_type == TYPE_FMOV
14828 && (set = single_set (dep_insn)) != NULL_RTX
14829 && (set2 = single_set (insn)) != NULL_RTX
14830 && rtx_equal_p (SET_DEST (set), SET_SRC (set2))
14831 && GET_CODE (SET_DEST (set2)) == MEM)
14834 /* Show ability of reorder buffer to hide latency of load by executing
14835 in parallel with previous instruction in case
14836 previous instruction is not needed to compute the address. */
14837 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
14838 && !ix86_agi_dependent (insn, dep_insn, insn_type))
14840 /* Claim moves to take one cycle, as core can issue one load
14841 at time and the next load can start cycle later. */
14842 if (dep_insn_type == TYPE_IMOV
14843 || dep_insn_type == TYPE_FMOV)
14851 memory = get_attr_memory (insn);
14853 /* The esp dependency is resolved before the instruction is really
14855 if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
14856 && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
14859 /* INT->FP conversion is expensive. */
14860 if (get_attr_fp_int_src (dep_insn))
14863 /* Show ability of reorder buffer to hide latency of load by executing
14864 in parallel with previous instruction in case
14865 previous instruction is not needed to compute the address. */
14866 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
14867 && !ix86_agi_dependent (insn, dep_insn, insn_type))
14869 /* Claim moves to take one cycle, as core can issue one load
14870 at time and the next load can start cycle later. */
14871 if (dep_insn_type == TYPE_IMOV
14872 || dep_insn_type == TYPE_FMOV)
14881 case PROCESSOR_ATHLON:
14883 case PROCESSOR_GENERIC32:
14884 case PROCESSOR_GENERIC64:
14885 memory = get_attr_memory (insn);
14887 /* Show ability of reorder buffer to hide latency of load by executing
14888 in parallel with previous instruction in case
14889 previous instruction is not needed to compute the address. */
14890 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
14891 && !ix86_agi_dependent (insn, dep_insn, insn_type))
14893 enum attr_unit unit = get_attr_unit (insn);
14896 /* Because of the difference between the length of integer and
14897 floating unit pipeline preparation stages, the memory operands
14898 for floating point are cheaper.
14900 ??? For Athlon it the difference is most probably 2. */
14901 if (unit == UNIT_INTEGER || unit == UNIT_UNKNOWN)
14904 loadcost = TARGET_ATHLON ? 2 : 0;
14906 if (cost >= loadcost)
14919 /* How many alternative schedules to try. This should be as wide as the
14920 scheduling freedom in the DFA, but no wider. Making this value too
14921 large results extra work for the scheduler. */
14924 ia32_multipass_dfa_lookahead (void)
14926 if (ix86_tune == PROCESSOR_PENTIUM)
14929 if (ix86_tune == PROCESSOR_PENTIUMPRO
14930 || ix86_tune == PROCESSOR_K6)
14938 /* Compute the alignment given to a constant that is being placed in memory.
14939 EXP is the constant and ALIGN is the alignment that the object would
14941 The value of this function is used instead of that alignment to align
14945 ix86_constant_alignment (tree exp, int align)
14947 if (TREE_CODE (exp) == REAL_CST)
14949 if (TYPE_MODE (TREE_TYPE (exp)) == DFmode && align < 64)
14951 else if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (exp))) && align < 128)
14954 else if (!optimize_size && TREE_CODE (exp) == STRING_CST
14955 && TREE_STRING_LENGTH (exp) >= 31 && align < BITS_PER_WORD)
14956 return BITS_PER_WORD;
14961 /* Compute the alignment for a static variable.
14962 TYPE is the data type, and ALIGN is the alignment that
14963 the object would ordinarily have. The value of this function is used
14964 instead of that alignment to align the object. */
14967 ix86_data_alignment (tree type, int align)
14969 int max_align = optimize_size ? BITS_PER_WORD : 256;
14971 if (AGGREGATE_TYPE_P (type)
14972 && TYPE_SIZE (type)
14973 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
14974 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= (unsigned) max_align
14975 || TREE_INT_CST_HIGH (TYPE_SIZE (type)))
14976 && align < max_align)
14979 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
14980 to 16byte boundary. */
14983 if (AGGREGATE_TYPE_P (type)
14984 && TYPE_SIZE (type)
14985 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
14986 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 128
14987 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
14991 if (TREE_CODE (type) == ARRAY_TYPE)
14993 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
14995 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
14998 else if (TREE_CODE (type) == COMPLEX_TYPE)
15001 if (TYPE_MODE (type) == DCmode && align < 64)
15003 if (TYPE_MODE (type) == XCmode && align < 128)
15006 else if ((TREE_CODE (type) == RECORD_TYPE
15007 || TREE_CODE (type) == UNION_TYPE
15008 || TREE_CODE (type) == QUAL_UNION_TYPE)
15009 && TYPE_FIELDS (type))
15011 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
15013 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
15016 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
15017 || TREE_CODE (type) == INTEGER_TYPE)
15019 if (TYPE_MODE (type) == DFmode && align < 64)
15021 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
15028 /* Compute the alignment for a local variable.
15029 TYPE is the data type, and ALIGN is the alignment that
15030 the object would ordinarily have. The value of this macro is used
15031 instead of that alignment to align the object. */
15034 ix86_local_alignment (tree type, int align)
15036 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
15037 to 16byte boundary. */
15040 if (AGGREGATE_TYPE_P (type)
15041 && TYPE_SIZE (type)
15042 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
15043 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 16
15044 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
15047 if (TREE_CODE (type) == ARRAY_TYPE)
15049 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
15051 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
15054 else if (TREE_CODE (type) == COMPLEX_TYPE)
15056 if (TYPE_MODE (type) == DCmode && align < 64)
15058 if (TYPE_MODE (type) == XCmode && align < 128)
15061 else if ((TREE_CODE (type) == RECORD_TYPE
15062 || TREE_CODE (type) == UNION_TYPE
15063 || TREE_CODE (type) == QUAL_UNION_TYPE)
15064 && TYPE_FIELDS (type))
15066 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
15068 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
15071 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
15072 || TREE_CODE (type) == INTEGER_TYPE)
15075 if (TYPE_MODE (type) == DFmode && align < 64)
15077 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
15083 /* Emit RTL insns to initialize the variable parts of a trampoline.
15084 FNADDR is an RTX for the address of the function's pure code.
15085 CXT is an RTX for the static chain value for the function. */
15087 x86_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
15091 /* Compute offset from the end of the jmp to the target function. */
15092 rtx disp = expand_binop (SImode, sub_optab, fnaddr,
15093 plus_constant (tramp, 10),
15094 NULL_RTX, 1, OPTAB_DIRECT);
15095 emit_move_insn (gen_rtx_MEM (QImode, tramp),
15096 gen_int_mode (0xb9, QImode));
15097 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 1)), cxt);
15098 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, 5)),
15099 gen_int_mode (0xe9, QImode));
15100 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 6)), disp);
15105 /* Try to load address using shorter movl instead of movabs.
15106 We may want to support movq for kernel mode, but kernel does not use
15107 trampolines at the moment. */
15108 if (x86_64_zext_immediate_operand (fnaddr, VOIDmode))
15110 fnaddr = copy_to_mode_reg (DImode, fnaddr);
15111 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
15112 gen_int_mode (0xbb41, HImode));
15113 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, offset + 2)),
15114 gen_lowpart (SImode, fnaddr));
15119 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
15120 gen_int_mode (0xbb49, HImode));
15121 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
15125 /* Load static chain using movabs to r10. */
15126 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
15127 gen_int_mode (0xba49, HImode));
15128 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
15131 /* Jump to the r11 */
15132 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
15133 gen_int_mode (0xff49, HImode));
15134 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, offset+2)),
15135 gen_int_mode (0xe3, QImode));
15137 gcc_assert (offset <= TRAMPOLINE_SIZE);
15140 #ifdef ENABLE_EXECUTE_STACK
15141 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
15142 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
15146 /* Codes for all the SSE/MMX builtins. */
15149 IX86_BUILTIN_ADDPS,
15150 IX86_BUILTIN_ADDSS,
15151 IX86_BUILTIN_DIVPS,
15152 IX86_BUILTIN_DIVSS,
15153 IX86_BUILTIN_MULPS,
15154 IX86_BUILTIN_MULSS,
15155 IX86_BUILTIN_SUBPS,
15156 IX86_BUILTIN_SUBSS,
15158 IX86_BUILTIN_CMPEQPS,
15159 IX86_BUILTIN_CMPLTPS,
15160 IX86_BUILTIN_CMPLEPS,
15161 IX86_BUILTIN_CMPGTPS,
15162 IX86_BUILTIN_CMPGEPS,
15163 IX86_BUILTIN_CMPNEQPS,
15164 IX86_BUILTIN_CMPNLTPS,
15165 IX86_BUILTIN_CMPNLEPS,
15166 IX86_BUILTIN_CMPNGTPS,
15167 IX86_BUILTIN_CMPNGEPS,
15168 IX86_BUILTIN_CMPORDPS,
15169 IX86_BUILTIN_CMPUNORDPS,
15170 IX86_BUILTIN_CMPEQSS,
15171 IX86_BUILTIN_CMPLTSS,
15172 IX86_BUILTIN_CMPLESS,
15173 IX86_BUILTIN_CMPNEQSS,
15174 IX86_BUILTIN_CMPNLTSS,
15175 IX86_BUILTIN_CMPNLESS,
15176 IX86_BUILTIN_CMPNGTSS,
15177 IX86_BUILTIN_CMPNGESS,
15178 IX86_BUILTIN_CMPORDSS,
15179 IX86_BUILTIN_CMPUNORDSS,
15181 IX86_BUILTIN_COMIEQSS,
15182 IX86_BUILTIN_COMILTSS,
15183 IX86_BUILTIN_COMILESS,
15184 IX86_BUILTIN_COMIGTSS,
15185 IX86_BUILTIN_COMIGESS,
15186 IX86_BUILTIN_COMINEQSS,
15187 IX86_BUILTIN_UCOMIEQSS,
15188 IX86_BUILTIN_UCOMILTSS,
15189 IX86_BUILTIN_UCOMILESS,
15190 IX86_BUILTIN_UCOMIGTSS,
15191 IX86_BUILTIN_UCOMIGESS,
15192 IX86_BUILTIN_UCOMINEQSS,
15194 IX86_BUILTIN_CVTPI2PS,
15195 IX86_BUILTIN_CVTPS2PI,
15196 IX86_BUILTIN_CVTSI2SS,
15197 IX86_BUILTIN_CVTSI642SS,
15198 IX86_BUILTIN_CVTSS2SI,
15199 IX86_BUILTIN_CVTSS2SI64,
15200 IX86_BUILTIN_CVTTPS2PI,
15201 IX86_BUILTIN_CVTTSS2SI,
15202 IX86_BUILTIN_CVTTSS2SI64,
15204 IX86_BUILTIN_MAXPS,
15205 IX86_BUILTIN_MAXSS,
15206 IX86_BUILTIN_MINPS,
15207 IX86_BUILTIN_MINSS,
15209 IX86_BUILTIN_LOADUPS,
15210 IX86_BUILTIN_STOREUPS,
15211 IX86_BUILTIN_MOVSS,
15213 IX86_BUILTIN_MOVHLPS,
15214 IX86_BUILTIN_MOVLHPS,
15215 IX86_BUILTIN_LOADHPS,
15216 IX86_BUILTIN_LOADLPS,
15217 IX86_BUILTIN_STOREHPS,
15218 IX86_BUILTIN_STORELPS,
15220 IX86_BUILTIN_MASKMOVQ,
15221 IX86_BUILTIN_MOVMSKPS,
15222 IX86_BUILTIN_PMOVMSKB,
15224 IX86_BUILTIN_MOVNTPS,
15225 IX86_BUILTIN_MOVNTQ,
15227 IX86_BUILTIN_LOADDQU,
15228 IX86_BUILTIN_STOREDQU,
15230 IX86_BUILTIN_PACKSSWB,
15231 IX86_BUILTIN_PACKSSDW,
15232 IX86_BUILTIN_PACKUSWB,
15234 IX86_BUILTIN_PADDB,
15235 IX86_BUILTIN_PADDW,
15236 IX86_BUILTIN_PADDD,
15237 IX86_BUILTIN_PADDQ,
15238 IX86_BUILTIN_PADDSB,
15239 IX86_BUILTIN_PADDSW,
15240 IX86_BUILTIN_PADDUSB,
15241 IX86_BUILTIN_PADDUSW,
15242 IX86_BUILTIN_PSUBB,
15243 IX86_BUILTIN_PSUBW,
15244 IX86_BUILTIN_PSUBD,
15245 IX86_BUILTIN_PSUBQ,
15246 IX86_BUILTIN_PSUBSB,
15247 IX86_BUILTIN_PSUBSW,
15248 IX86_BUILTIN_PSUBUSB,
15249 IX86_BUILTIN_PSUBUSW,
15252 IX86_BUILTIN_PANDN,
15256 IX86_BUILTIN_PAVGB,
15257 IX86_BUILTIN_PAVGW,
15259 IX86_BUILTIN_PCMPEQB,
15260 IX86_BUILTIN_PCMPEQW,
15261 IX86_BUILTIN_PCMPEQD,
15262 IX86_BUILTIN_PCMPGTB,
15263 IX86_BUILTIN_PCMPGTW,
15264 IX86_BUILTIN_PCMPGTD,
15266 IX86_BUILTIN_PMADDWD,
15268 IX86_BUILTIN_PMAXSW,
15269 IX86_BUILTIN_PMAXUB,
15270 IX86_BUILTIN_PMINSW,
15271 IX86_BUILTIN_PMINUB,
15273 IX86_BUILTIN_PMULHUW,
15274 IX86_BUILTIN_PMULHW,
15275 IX86_BUILTIN_PMULLW,
15277 IX86_BUILTIN_PSADBW,
15278 IX86_BUILTIN_PSHUFW,
15280 IX86_BUILTIN_PSLLW,
15281 IX86_BUILTIN_PSLLD,
15282 IX86_BUILTIN_PSLLQ,
15283 IX86_BUILTIN_PSRAW,
15284 IX86_BUILTIN_PSRAD,
15285 IX86_BUILTIN_PSRLW,
15286 IX86_BUILTIN_PSRLD,
15287 IX86_BUILTIN_PSRLQ,
15288 IX86_BUILTIN_PSLLWI,
15289 IX86_BUILTIN_PSLLDI,
15290 IX86_BUILTIN_PSLLQI,
15291 IX86_BUILTIN_PSRAWI,
15292 IX86_BUILTIN_PSRADI,
15293 IX86_BUILTIN_PSRLWI,
15294 IX86_BUILTIN_PSRLDI,
15295 IX86_BUILTIN_PSRLQI,
15297 IX86_BUILTIN_PUNPCKHBW,
15298 IX86_BUILTIN_PUNPCKHWD,
15299 IX86_BUILTIN_PUNPCKHDQ,
15300 IX86_BUILTIN_PUNPCKLBW,
15301 IX86_BUILTIN_PUNPCKLWD,
15302 IX86_BUILTIN_PUNPCKLDQ,
15304 IX86_BUILTIN_SHUFPS,
15306 IX86_BUILTIN_RCPPS,
15307 IX86_BUILTIN_RCPSS,
15308 IX86_BUILTIN_RSQRTPS,
15309 IX86_BUILTIN_RSQRTSS,
15310 IX86_BUILTIN_SQRTPS,
15311 IX86_BUILTIN_SQRTSS,
15313 IX86_BUILTIN_UNPCKHPS,
15314 IX86_BUILTIN_UNPCKLPS,
15316 IX86_BUILTIN_ANDPS,
15317 IX86_BUILTIN_ANDNPS,
15319 IX86_BUILTIN_XORPS,
15322 IX86_BUILTIN_LDMXCSR,
15323 IX86_BUILTIN_STMXCSR,
15324 IX86_BUILTIN_SFENCE,
15326 /* 3DNow! Original */
15327 IX86_BUILTIN_FEMMS,
15328 IX86_BUILTIN_PAVGUSB,
15329 IX86_BUILTIN_PF2ID,
15330 IX86_BUILTIN_PFACC,
15331 IX86_BUILTIN_PFADD,
15332 IX86_BUILTIN_PFCMPEQ,
15333 IX86_BUILTIN_PFCMPGE,
15334 IX86_BUILTIN_PFCMPGT,
15335 IX86_BUILTIN_PFMAX,
15336 IX86_BUILTIN_PFMIN,
15337 IX86_BUILTIN_PFMUL,
15338 IX86_BUILTIN_PFRCP,
15339 IX86_BUILTIN_PFRCPIT1,
15340 IX86_BUILTIN_PFRCPIT2,
15341 IX86_BUILTIN_PFRSQIT1,
15342 IX86_BUILTIN_PFRSQRT,
15343 IX86_BUILTIN_PFSUB,
15344 IX86_BUILTIN_PFSUBR,
15345 IX86_BUILTIN_PI2FD,
15346 IX86_BUILTIN_PMULHRW,
15348 /* 3DNow! Athlon Extensions */
15349 IX86_BUILTIN_PF2IW,
15350 IX86_BUILTIN_PFNACC,
15351 IX86_BUILTIN_PFPNACC,
15352 IX86_BUILTIN_PI2FW,
15353 IX86_BUILTIN_PSWAPDSI,
15354 IX86_BUILTIN_PSWAPDSF,
15357 IX86_BUILTIN_ADDPD,
15358 IX86_BUILTIN_ADDSD,
15359 IX86_BUILTIN_DIVPD,
15360 IX86_BUILTIN_DIVSD,
15361 IX86_BUILTIN_MULPD,
15362 IX86_BUILTIN_MULSD,
15363 IX86_BUILTIN_SUBPD,
15364 IX86_BUILTIN_SUBSD,
15366 IX86_BUILTIN_CMPEQPD,
15367 IX86_BUILTIN_CMPLTPD,
15368 IX86_BUILTIN_CMPLEPD,
15369 IX86_BUILTIN_CMPGTPD,
15370 IX86_BUILTIN_CMPGEPD,
15371 IX86_BUILTIN_CMPNEQPD,
15372 IX86_BUILTIN_CMPNLTPD,
15373 IX86_BUILTIN_CMPNLEPD,
15374 IX86_BUILTIN_CMPNGTPD,
15375 IX86_BUILTIN_CMPNGEPD,
15376 IX86_BUILTIN_CMPORDPD,
15377 IX86_BUILTIN_CMPUNORDPD,
15378 IX86_BUILTIN_CMPNEPD,
15379 IX86_BUILTIN_CMPEQSD,
15380 IX86_BUILTIN_CMPLTSD,
15381 IX86_BUILTIN_CMPLESD,
15382 IX86_BUILTIN_CMPNEQSD,
15383 IX86_BUILTIN_CMPNLTSD,
15384 IX86_BUILTIN_CMPNLESD,
15385 IX86_BUILTIN_CMPORDSD,
15386 IX86_BUILTIN_CMPUNORDSD,
15387 IX86_BUILTIN_CMPNESD,
15389 IX86_BUILTIN_COMIEQSD,
15390 IX86_BUILTIN_COMILTSD,
15391 IX86_BUILTIN_COMILESD,
15392 IX86_BUILTIN_COMIGTSD,
15393 IX86_BUILTIN_COMIGESD,
15394 IX86_BUILTIN_COMINEQSD,
15395 IX86_BUILTIN_UCOMIEQSD,
15396 IX86_BUILTIN_UCOMILTSD,
15397 IX86_BUILTIN_UCOMILESD,
15398 IX86_BUILTIN_UCOMIGTSD,
15399 IX86_BUILTIN_UCOMIGESD,
15400 IX86_BUILTIN_UCOMINEQSD,
15402 IX86_BUILTIN_MAXPD,
15403 IX86_BUILTIN_MAXSD,
15404 IX86_BUILTIN_MINPD,
15405 IX86_BUILTIN_MINSD,
15407 IX86_BUILTIN_ANDPD,
15408 IX86_BUILTIN_ANDNPD,
15410 IX86_BUILTIN_XORPD,
15412 IX86_BUILTIN_SQRTPD,
15413 IX86_BUILTIN_SQRTSD,
15415 IX86_BUILTIN_UNPCKHPD,
15416 IX86_BUILTIN_UNPCKLPD,
15418 IX86_BUILTIN_SHUFPD,
15420 IX86_BUILTIN_LOADUPD,
15421 IX86_BUILTIN_STOREUPD,
15422 IX86_BUILTIN_MOVSD,
15424 IX86_BUILTIN_LOADHPD,
15425 IX86_BUILTIN_LOADLPD,
15427 IX86_BUILTIN_CVTDQ2PD,
15428 IX86_BUILTIN_CVTDQ2PS,
15430 IX86_BUILTIN_CVTPD2DQ,
15431 IX86_BUILTIN_CVTPD2PI,
15432 IX86_BUILTIN_CVTPD2PS,
15433 IX86_BUILTIN_CVTTPD2DQ,
15434 IX86_BUILTIN_CVTTPD2PI,
15436 IX86_BUILTIN_CVTPI2PD,
15437 IX86_BUILTIN_CVTSI2SD,
15438 IX86_BUILTIN_CVTSI642SD,
15440 IX86_BUILTIN_CVTSD2SI,
15441 IX86_BUILTIN_CVTSD2SI64,
15442 IX86_BUILTIN_CVTSD2SS,
15443 IX86_BUILTIN_CVTSS2SD,
15444 IX86_BUILTIN_CVTTSD2SI,
15445 IX86_BUILTIN_CVTTSD2SI64,
15447 IX86_BUILTIN_CVTPS2DQ,
15448 IX86_BUILTIN_CVTPS2PD,
15449 IX86_BUILTIN_CVTTPS2DQ,
15451 IX86_BUILTIN_MOVNTI,
15452 IX86_BUILTIN_MOVNTPD,
15453 IX86_BUILTIN_MOVNTDQ,
15456 IX86_BUILTIN_MASKMOVDQU,
15457 IX86_BUILTIN_MOVMSKPD,
15458 IX86_BUILTIN_PMOVMSKB128,
15460 IX86_BUILTIN_PACKSSWB128,
15461 IX86_BUILTIN_PACKSSDW128,
15462 IX86_BUILTIN_PACKUSWB128,
15464 IX86_BUILTIN_PADDB128,
15465 IX86_BUILTIN_PADDW128,
15466 IX86_BUILTIN_PADDD128,
15467 IX86_BUILTIN_PADDQ128,
15468 IX86_BUILTIN_PADDSB128,
15469 IX86_BUILTIN_PADDSW128,
15470 IX86_BUILTIN_PADDUSB128,
15471 IX86_BUILTIN_PADDUSW128,
15472 IX86_BUILTIN_PSUBB128,
15473 IX86_BUILTIN_PSUBW128,
15474 IX86_BUILTIN_PSUBD128,
15475 IX86_BUILTIN_PSUBQ128,
15476 IX86_BUILTIN_PSUBSB128,
15477 IX86_BUILTIN_PSUBSW128,
15478 IX86_BUILTIN_PSUBUSB128,
15479 IX86_BUILTIN_PSUBUSW128,
15481 IX86_BUILTIN_PAND128,
15482 IX86_BUILTIN_PANDN128,
15483 IX86_BUILTIN_POR128,
15484 IX86_BUILTIN_PXOR128,
15486 IX86_BUILTIN_PAVGB128,
15487 IX86_BUILTIN_PAVGW128,
15489 IX86_BUILTIN_PCMPEQB128,
15490 IX86_BUILTIN_PCMPEQW128,
15491 IX86_BUILTIN_PCMPEQD128,
15492 IX86_BUILTIN_PCMPGTB128,
15493 IX86_BUILTIN_PCMPGTW128,
15494 IX86_BUILTIN_PCMPGTD128,
15496 IX86_BUILTIN_PMADDWD128,
15498 IX86_BUILTIN_PMAXSW128,
15499 IX86_BUILTIN_PMAXUB128,
15500 IX86_BUILTIN_PMINSW128,
15501 IX86_BUILTIN_PMINUB128,
15503 IX86_BUILTIN_PMULUDQ,
15504 IX86_BUILTIN_PMULUDQ128,
15505 IX86_BUILTIN_PMULHUW128,
15506 IX86_BUILTIN_PMULHW128,
15507 IX86_BUILTIN_PMULLW128,
15509 IX86_BUILTIN_PSADBW128,
15510 IX86_BUILTIN_PSHUFHW,
15511 IX86_BUILTIN_PSHUFLW,
15512 IX86_BUILTIN_PSHUFD,
15514 IX86_BUILTIN_PSLLW128,
15515 IX86_BUILTIN_PSLLD128,
15516 IX86_BUILTIN_PSLLQ128,
15517 IX86_BUILTIN_PSRAW128,
15518 IX86_BUILTIN_PSRAD128,
15519 IX86_BUILTIN_PSRLW128,
15520 IX86_BUILTIN_PSRLD128,
15521 IX86_BUILTIN_PSRLQ128,
15522 IX86_BUILTIN_PSLLDQI128,
15523 IX86_BUILTIN_PSLLWI128,
15524 IX86_BUILTIN_PSLLDI128,
15525 IX86_BUILTIN_PSLLQI128,
15526 IX86_BUILTIN_PSRAWI128,
15527 IX86_BUILTIN_PSRADI128,
15528 IX86_BUILTIN_PSRLDQI128,
15529 IX86_BUILTIN_PSRLWI128,
15530 IX86_BUILTIN_PSRLDI128,
15531 IX86_BUILTIN_PSRLQI128,
15533 IX86_BUILTIN_PUNPCKHBW128,
15534 IX86_BUILTIN_PUNPCKHWD128,
15535 IX86_BUILTIN_PUNPCKHDQ128,
15536 IX86_BUILTIN_PUNPCKHQDQ128,
15537 IX86_BUILTIN_PUNPCKLBW128,
15538 IX86_BUILTIN_PUNPCKLWD128,
15539 IX86_BUILTIN_PUNPCKLDQ128,
15540 IX86_BUILTIN_PUNPCKLQDQ128,
15542 IX86_BUILTIN_CLFLUSH,
15543 IX86_BUILTIN_MFENCE,
15544 IX86_BUILTIN_LFENCE,
15546 /* Prescott New Instructions. */
15547 IX86_BUILTIN_ADDSUBPS,
15548 IX86_BUILTIN_HADDPS,
15549 IX86_BUILTIN_HSUBPS,
15550 IX86_BUILTIN_MOVSHDUP,
15551 IX86_BUILTIN_MOVSLDUP,
15552 IX86_BUILTIN_ADDSUBPD,
15553 IX86_BUILTIN_HADDPD,
15554 IX86_BUILTIN_HSUBPD,
15555 IX86_BUILTIN_LDDQU,
15557 IX86_BUILTIN_MONITOR,
15558 IX86_BUILTIN_MWAIT,
15561 IX86_BUILTIN_PHADDW,
15562 IX86_BUILTIN_PHADDD,
15563 IX86_BUILTIN_PHADDSW,
15564 IX86_BUILTIN_PHSUBW,
15565 IX86_BUILTIN_PHSUBD,
15566 IX86_BUILTIN_PHSUBSW,
15567 IX86_BUILTIN_PMADDUBSW,
15568 IX86_BUILTIN_PMULHRSW,
15569 IX86_BUILTIN_PSHUFB,
15570 IX86_BUILTIN_PSIGNB,
15571 IX86_BUILTIN_PSIGNW,
15572 IX86_BUILTIN_PSIGND,
15573 IX86_BUILTIN_PALIGNR,
15574 IX86_BUILTIN_PABSB,
15575 IX86_BUILTIN_PABSW,
15576 IX86_BUILTIN_PABSD,
15578 IX86_BUILTIN_PHADDW128,
15579 IX86_BUILTIN_PHADDD128,
15580 IX86_BUILTIN_PHADDSW128,
15581 IX86_BUILTIN_PHSUBW128,
15582 IX86_BUILTIN_PHSUBD128,
15583 IX86_BUILTIN_PHSUBSW128,
15584 IX86_BUILTIN_PMADDUBSW128,
15585 IX86_BUILTIN_PMULHRSW128,
15586 IX86_BUILTIN_PSHUFB128,
15587 IX86_BUILTIN_PSIGNB128,
15588 IX86_BUILTIN_PSIGNW128,
15589 IX86_BUILTIN_PSIGND128,
15590 IX86_BUILTIN_PALIGNR128,
15591 IX86_BUILTIN_PABSB128,
15592 IX86_BUILTIN_PABSW128,
15593 IX86_BUILTIN_PABSD128,
15595 IX86_BUILTIN_VEC_INIT_V2SI,
15596 IX86_BUILTIN_VEC_INIT_V4HI,
15597 IX86_BUILTIN_VEC_INIT_V8QI,
15598 IX86_BUILTIN_VEC_EXT_V2DF,
15599 IX86_BUILTIN_VEC_EXT_V2DI,
15600 IX86_BUILTIN_VEC_EXT_V4SF,
15601 IX86_BUILTIN_VEC_EXT_V4SI,
15602 IX86_BUILTIN_VEC_EXT_V8HI,
15603 IX86_BUILTIN_VEC_EXT_V2SI,
15604 IX86_BUILTIN_VEC_EXT_V4HI,
15605 IX86_BUILTIN_VEC_SET_V8HI,
15606 IX86_BUILTIN_VEC_SET_V4HI,
15611 /* Table for the ix86 builtin decls. */
15612 static GTY(()) tree ix86_builtins[(int) IX86_BUILTIN_MAX];
15614 /* Add a ix86 target builtin function with CODE, NAME and TYPE. Do so,
15615 * if the target_flags include one of MASK. Stores the function decl
15616 * in the ix86_builtins array.
15617 * Returns the function decl or NULL_TREE, if the builtin was not added. */
15620 def_builtin (int mask, const char *name, tree type, enum ix86_builtins code)
15622 tree decl = NULL_TREE;
15624 if (mask & target_flags
15625 && (!(mask & MASK_64BIT) || TARGET_64BIT))
15627 decl = add_builtin_function (name, type, code, BUILT_IN_MD,
15629 ix86_builtins[(int) code] = decl;
15635 /* Like def_builtin, but also marks the function decl "const". */
15638 def_builtin_const (int mask, const char *name, tree type,
15639 enum ix86_builtins code)
15641 tree decl = def_builtin (mask, name, type, code);
15643 TREE_READONLY (decl) = 1;
15647 /* Bits for builtin_description.flag. */
15649 /* Set when we don't support the comparison natively, and should
15650 swap_comparison in order to support it. */
15651 #define BUILTIN_DESC_SWAP_OPERANDS 1
15653 struct builtin_description
15655 const unsigned int mask;
15656 const enum insn_code icode;
15657 const char *const name;
15658 const enum ix86_builtins code;
15659 const enum rtx_code comparison;
15660 const unsigned int flag;
15663 static const struct builtin_description bdesc_comi[] =
15665 { MASK_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
15666 { MASK_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
15667 { MASK_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
15668 { MASK_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
15669 { MASK_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
15670 { MASK_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
15671 { MASK_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
15672 { MASK_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
15673 { MASK_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
15674 { MASK_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
15675 { MASK_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
15676 { MASK_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
15677 { MASK_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
15678 { MASK_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
15679 { MASK_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
15680 { MASK_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
15681 { MASK_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
15682 { MASK_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
15683 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
15684 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
15685 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
15686 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
15687 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
15688 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
15691 static const struct builtin_description bdesc_2arg[] =
15694 { MASK_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, 0, 0 },
15695 { MASK_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, 0, 0 },
15696 { MASK_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, 0, 0 },
15697 { MASK_SSE, CODE_FOR_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, 0, 0 },
15698 { MASK_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, 0, 0 },
15699 { MASK_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, 0, 0 },
15700 { MASK_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, 0, 0 },
15701 { MASK_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, 0, 0 },
15703 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, 0 },
15704 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, 0 },
15705 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, 0 },
15706 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT,
15707 BUILTIN_DESC_SWAP_OPERANDS },
15708 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE,
15709 BUILTIN_DESC_SWAP_OPERANDS },
15710 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, 0 },
15711 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, 0 },
15712 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, 0 },
15713 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, 0 },
15714 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE,
15715 BUILTIN_DESC_SWAP_OPERANDS },
15716 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT,
15717 BUILTIN_DESC_SWAP_OPERANDS },
15718 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, 0 },
15719 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, 0 },
15720 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, 0 },
15721 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, 0 },
15722 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, 0 },
15723 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, 0 },
15724 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, 0 },
15725 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, 0 },
15726 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE,
15727 BUILTIN_DESC_SWAP_OPERANDS },
15728 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT,
15729 BUILTIN_DESC_SWAP_OPERANDS },
15730 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, UNORDERED, 0 },
15732 { MASK_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, 0, 0 },
15733 { MASK_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, 0, 0 },
15734 { MASK_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, 0, 0 },
15735 { MASK_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, 0, 0 },
15737 { MASK_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, 0, 0 },
15738 { MASK_SSE, CODE_FOR_sse_nandv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, 0, 0 },
15739 { MASK_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, 0, 0 },
15740 { MASK_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, 0, 0 },
15742 { MASK_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, 0, 0 },
15743 { MASK_SSE, CODE_FOR_sse_movhlps, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, 0, 0 },
15744 { MASK_SSE, CODE_FOR_sse_movlhps, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, 0, 0 },
15745 { MASK_SSE, CODE_FOR_sse_unpckhps, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, 0, 0 },
15746 { MASK_SSE, CODE_FOR_sse_unpcklps, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, 0, 0 },
15749 { MASK_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, 0, 0 },
15750 { MASK_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, 0, 0 },
15751 { MASK_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, 0, 0 },
15752 { MASK_SSE2, CODE_FOR_mmx_adddi3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, 0, 0 },
15753 { MASK_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, 0, 0 },
15754 { MASK_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, 0, 0 },
15755 { MASK_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, 0, 0 },
15756 { MASK_SSE2, CODE_FOR_mmx_subdi3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, 0, 0 },
15758 { MASK_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, 0, 0 },
15759 { MASK_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, 0, 0 },
15760 { MASK_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, 0, 0 },
15761 { MASK_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, 0, 0 },
15762 { MASK_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, 0, 0 },
15763 { MASK_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, 0, 0 },
15764 { MASK_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, 0, 0 },
15765 { MASK_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, 0, 0 },
15767 { MASK_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, 0, 0 },
15768 { MASK_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, 0, 0 },
15769 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, 0, 0 },
15771 { MASK_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, 0, 0 },
15772 { MASK_MMX, CODE_FOR_mmx_nandv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, 0, 0 },
15773 { MASK_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, 0, 0 },
15774 { MASK_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, 0, 0 },
15776 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, 0, 0 },
15777 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, 0, 0 },
15779 { MASK_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, 0, 0 },
15780 { MASK_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, 0, 0 },
15781 { MASK_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, 0, 0 },
15782 { MASK_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, 0, 0 },
15783 { MASK_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, 0, 0 },
15784 { MASK_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, 0, 0 },
15786 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, 0, 0 },
15787 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, 0, 0 },
15788 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, 0, 0 },
15789 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, 0, 0 },
15791 { MASK_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, 0, 0 },
15792 { MASK_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, 0, 0 },
15793 { MASK_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, 0, 0 },
15794 { MASK_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, 0, 0 },
15795 { MASK_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, 0, 0 },
15796 { MASK_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, 0, 0 },
15799 { MASK_MMX, CODE_FOR_mmx_packsswb, 0, IX86_BUILTIN_PACKSSWB, 0, 0 },
15800 { MASK_MMX, CODE_FOR_mmx_packssdw, 0, IX86_BUILTIN_PACKSSDW, 0, 0 },
15801 { MASK_MMX, CODE_FOR_mmx_packuswb, 0, IX86_BUILTIN_PACKUSWB, 0, 0 },
15803 { MASK_SSE, CODE_FOR_sse_cvtpi2ps, 0, IX86_BUILTIN_CVTPI2PS, 0, 0 },
15804 { MASK_SSE, CODE_FOR_sse_cvtsi2ss, 0, IX86_BUILTIN_CVTSI2SS, 0, 0 },
15805 { MASK_SSE | MASK_64BIT, CODE_FOR_sse_cvtsi2ssq, 0, IX86_BUILTIN_CVTSI642SS, 0, 0 },
15807 { MASK_MMX, CODE_FOR_mmx_ashlv4hi3, 0, IX86_BUILTIN_PSLLW, 0, 0 },
15808 { MASK_MMX, CODE_FOR_mmx_ashlv4hi3, 0, IX86_BUILTIN_PSLLWI, 0, 0 },
15809 { MASK_MMX, CODE_FOR_mmx_ashlv2si3, 0, IX86_BUILTIN_PSLLD, 0, 0 },
15810 { MASK_MMX, CODE_FOR_mmx_ashlv2si3, 0, IX86_BUILTIN_PSLLDI, 0, 0 },
15811 { MASK_MMX, CODE_FOR_mmx_ashldi3, 0, IX86_BUILTIN_PSLLQ, 0, 0 },
15812 { MASK_MMX, CODE_FOR_mmx_ashldi3, 0, IX86_BUILTIN_PSLLQI, 0, 0 },
15814 { MASK_MMX, CODE_FOR_mmx_lshrv4hi3, 0, IX86_BUILTIN_PSRLW, 0, 0 },
15815 { MASK_MMX, CODE_FOR_mmx_lshrv4hi3, 0, IX86_BUILTIN_PSRLWI, 0, 0 },
15816 { MASK_MMX, CODE_FOR_mmx_lshrv2si3, 0, IX86_BUILTIN_PSRLD, 0, 0 },
15817 { MASK_MMX, CODE_FOR_mmx_lshrv2si3, 0, IX86_BUILTIN_PSRLDI, 0, 0 },
15818 { MASK_MMX, CODE_FOR_mmx_lshrdi3, 0, IX86_BUILTIN_PSRLQ, 0, 0 },
15819 { MASK_MMX, CODE_FOR_mmx_lshrdi3, 0, IX86_BUILTIN_PSRLQI, 0, 0 },
15821 { MASK_MMX, CODE_FOR_mmx_ashrv4hi3, 0, IX86_BUILTIN_PSRAW, 0, 0 },
15822 { MASK_MMX, CODE_FOR_mmx_ashrv4hi3, 0, IX86_BUILTIN_PSRAWI, 0, 0 },
15823 { MASK_MMX, CODE_FOR_mmx_ashrv2si3, 0, IX86_BUILTIN_PSRAD, 0, 0 },
15824 { MASK_MMX, CODE_FOR_mmx_ashrv2si3, 0, IX86_BUILTIN_PSRADI, 0, 0 },
15826 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_psadbw, 0, IX86_BUILTIN_PSADBW, 0, 0 },
15827 { MASK_MMX, CODE_FOR_mmx_pmaddwd, 0, IX86_BUILTIN_PMADDWD, 0, 0 },
15830 { MASK_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, 0, 0 },
15831 { MASK_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, 0, 0 },
15832 { MASK_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, 0, 0 },
15833 { MASK_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, 0, 0 },
15834 { MASK_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, 0, 0 },
15835 { MASK_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, 0, 0 },
15836 { MASK_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, 0, 0 },
15837 { MASK_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, 0, 0 },
15839 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, 0 },
15840 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, 0 },
15841 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, 0 },
15842 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT,
15843 BUILTIN_DESC_SWAP_OPERANDS },
15844 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE,
15845 BUILTIN_DESC_SWAP_OPERANDS },
15846 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, 0 },
15847 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, 0 },
15848 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, 0 },
15849 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, 0 },
15850 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE,
15851 BUILTIN_DESC_SWAP_OPERANDS },
15852 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT,
15853 BUILTIN_DESC_SWAP_OPERANDS },
15854 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, 0 },
15855 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, 0 },
15856 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, 0 },
15857 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, 0 },
15858 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, 0 },
15859 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, 0 },
15860 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, 0 },
15861 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, 0 },
15862 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, 0 },
15864 { MASK_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, 0, 0 },
15865 { MASK_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, 0, 0 },
15866 { MASK_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, 0, 0 },
15867 { MASK_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, 0, 0 },
15869 { MASK_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, 0, 0 },
15870 { MASK_SSE2, CODE_FOR_sse2_nandv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, 0, 0 },
15871 { MASK_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, 0, 0 },
15872 { MASK_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, 0, 0 },
15874 { MASK_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, 0, 0 },
15875 { MASK_SSE2, CODE_FOR_sse2_unpckhpd, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, 0, 0 },
15876 { MASK_SSE2, CODE_FOR_sse2_unpcklpd, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, 0, 0 },
15879 { MASK_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, 0, 0 },
15880 { MASK_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, 0, 0 },
15881 { MASK_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, 0, 0 },
15882 { MASK_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, 0, 0 },
15883 { MASK_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, 0, 0 },
15884 { MASK_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, 0, 0 },
15885 { MASK_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, 0, 0 },
15886 { MASK_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, 0, 0 },
15888 { MASK_MMX, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, 0, 0 },
15889 { MASK_MMX, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, 0, 0 },
15890 { MASK_MMX, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, 0, 0 },
15891 { MASK_MMX, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, 0, 0 },
15892 { MASK_MMX, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, 0, 0 },
15893 { MASK_MMX, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, 0, 0 },
15894 { MASK_MMX, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, 0, 0 },
15895 { MASK_MMX, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, 0, 0 },
15897 { MASK_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, 0, 0 },
15898 { MASK_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, 0, 0 },
15900 { MASK_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, 0, 0 },
15901 { MASK_SSE2, CODE_FOR_sse2_nandv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, 0, 0 },
15902 { MASK_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, 0, 0 },
15903 { MASK_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, 0, 0 },
15905 { MASK_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, 0, 0 },
15906 { MASK_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, 0, 0 },
15908 { MASK_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, 0, 0 },
15909 { MASK_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, 0, 0 },
15910 { MASK_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, 0, 0 },
15911 { MASK_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, 0, 0 },
15912 { MASK_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, 0, 0 },
15913 { MASK_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, 0, 0 },
15915 { MASK_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, 0, 0 },
15916 { MASK_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, 0, 0 },
15917 { MASK_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, 0, 0 },
15918 { MASK_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, 0, 0 },
15920 { MASK_SSE2, CODE_FOR_sse2_punpckhbw, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, 0, 0 },
15921 { MASK_SSE2, CODE_FOR_sse2_punpckhwd, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, 0, 0 },
15922 { MASK_SSE2, CODE_FOR_sse2_punpckhdq, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, 0, 0 },
15923 { MASK_SSE2, CODE_FOR_sse2_punpckhqdq, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, 0, 0 },
15924 { MASK_SSE2, CODE_FOR_sse2_punpcklbw, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, 0, 0 },
15925 { MASK_SSE2, CODE_FOR_sse2_punpcklwd, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, 0, 0 },
15926 { MASK_SSE2, CODE_FOR_sse2_punpckldq, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, 0, 0 },
15927 { MASK_SSE2, CODE_FOR_sse2_punpcklqdq, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, 0, 0 },
15929 { MASK_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, 0, 0 },
15930 { MASK_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, 0, 0 },
15931 { MASK_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, 0, 0 },
15933 { MASK_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, 0, 0 },
15934 { MASK_SSE2, CODE_FOR_sse2_psadbw, 0, IX86_BUILTIN_PSADBW128, 0, 0 },
15936 { MASK_SSE2, CODE_FOR_sse2_umulsidi3, 0, IX86_BUILTIN_PMULUDQ, 0, 0 },
15937 { MASK_SSE2, CODE_FOR_sse2_umulv2siv2di3, 0, IX86_BUILTIN_PMULUDQ128, 0, 0 },
15939 { MASK_SSE2, CODE_FOR_ashlv8hi3, 0, IX86_BUILTIN_PSLLWI128, 0, 0 },
15940 { MASK_SSE2, CODE_FOR_ashlv4si3, 0, IX86_BUILTIN_PSLLDI128, 0, 0 },
15941 { MASK_SSE2, CODE_FOR_ashlv2di3, 0, IX86_BUILTIN_PSLLQI128, 0, 0 },
15943 { MASK_SSE2, CODE_FOR_lshrv8hi3, 0, IX86_BUILTIN_PSRLWI128, 0, 0 },
15944 { MASK_SSE2, CODE_FOR_lshrv4si3, 0, IX86_BUILTIN_PSRLDI128, 0, 0 },
15945 { MASK_SSE2, CODE_FOR_lshrv2di3, 0, IX86_BUILTIN_PSRLQI128, 0, 0 },
15947 { MASK_SSE2, CODE_FOR_ashrv8hi3, 0, IX86_BUILTIN_PSRAWI128, 0, 0 },
15948 { MASK_SSE2, CODE_FOR_ashrv4si3, 0, IX86_BUILTIN_PSRADI128, 0, 0 },
15950 { MASK_SSE2, CODE_FOR_sse2_pmaddwd, 0, IX86_BUILTIN_PMADDWD128, 0, 0 },
15952 { MASK_SSE2, CODE_FOR_sse2_cvtsi2sd, 0, IX86_BUILTIN_CVTSI2SD, 0, 0 },
15953 { MASK_SSE2 | MASK_64BIT, CODE_FOR_sse2_cvtsi2sdq, 0, IX86_BUILTIN_CVTSI642SD, 0, 0 },
15954 { MASK_SSE2, CODE_FOR_sse2_cvtsd2ss, 0, IX86_BUILTIN_CVTSD2SS, 0, 0 },
15955 { MASK_SSE2, CODE_FOR_sse2_cvtss2sd, 0, IX86_BUILTIN_CVTSS2SD, 0, 0 },
15958 { MASK_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, 0, 0 },
15959 { MASK_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, 0, 0 },
15960 { MASK_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, 0, 0 },
15961 { MASK_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, 0, 0 },
15962 { MASK_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, 0, 0 },
15963 { MASK_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, 0, 0 },
15966 { MASK_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, 0, 0 },
15967 { MASK_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, 0, 0 },
15968 { MASK_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, 0, 0 },
15969 { MASK_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, 0, 0 },
15970 { MASK_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, 0, 0 },
15971 { MASK_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, 0, 0 },
15972 { MASK_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, 0, 0 },
15973 { MASK_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, 0, 0 },
15974 { MASK_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, 0, 0 },
15975 { MASK_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, 0, 0 },
15976 { MASK_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, 0, 0 },
15977 { MASK_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, 0, 0 },
15978 { MASK_SSSE3, CODE_FOR_ssse3_pmaddubswv8hi3, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, 0, 0 },
15979 { MASK_SSSE3, CODE_FOR_ssse3_pmaddubswv4hi3, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, 0, 0 },
15980 { MASK_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, 0, 0 },
15981 { MASK_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, 0, 0 },
15982 { MASK_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, 0, 0 },
15983 { MASK_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, 0, 0 },
15984 { MASK_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, 0, 0 },
15985 { MASK_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, 0, 0 },
15986 { MASK_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, 0, 0 },
15987 { MASK_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, 0, 0 },
15988 { MASK_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, 0, 0 },
15989 { MASK_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, 0, 0 }
15992 static const struct builtin_description bdesc_1arg[] =
15994 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_pmovmskb, 0, IX86_BUILTIN_PMOVMSKB, 0, 0 },
15995 { MASK_SSE, CODE_FOR_sse_movmskps, 0, IX86_BUILTIN_MOVMSKPS, 0, 0 },
15997 { MASK_SSE, CODE_FOR_sqrtv4sf2, 0, IX86_BUILTIN_SQRTPS, 0, 0 },
15998 { MASK_SSE, CODE_FOR_sse_rsqrtv4sf2, 0, IX86_BUILTIN_RSQRTPS, 0, 0 },
15999 { MASK_SSE, CODE_FOR_sse_rcpv4sf2, 0, IX86_BUILTIN_RCPPS, 0, 0 },
16001 { MASK_SSE, CODE_FOR_sse_cvtps2pi, 0, IX86_BUILTIN_CVTPS2PI, 0, 0 },
16002 { MASK_SSE, CODE_FOR_sse_cvtss2si, 0, IX86_BUILTIN_CVTSS2SI, 0, 0 },
16003 { MASK_SSE | MASK_64BIT, CODE_FOR_sse_cvtss2siq, 0, IX86_BUILTIN_CVTSS2SI64, 0, 0 },
16004 { MASK_SSE, CODE_FOR_sse_cvttps2pi, 0, IX86_BUILTIN_CVTTPS2PI, 0, 0 },
16005 { MASK_SSE, CODE_FOR_sse_cvttss2si, 0, IX86_BUILTIN_CVTTSS2SI, 0, 0 },
16006 { MASK_SSE | MASK_64BIT, CODE_FOR_sse_cvttss2siq, 0, IX86_BUILTIN_CVTTSS2SI64, 0, 0 },
16008 { MASK_SSE2, CODE_FOR_sse2_pmovmskb, 0, IX86_BUILTIN_PMOVMSKB128, 0, 0 },
16009 { MASK_SSE2, CODE_FOR_sse2_movmskpd, 0, IX86_BUILTIN_MOVMSKPD, 0, 0 },
16011 { MASK_SSE2, CODE_FOR_sqrtv2df2, 0, IX86_BUILTIN_SQRTPD, 0, 0 },
16013 { MASK_SSE2, CODE_FOR_sse2_cvtdq2pd, 0, IX86_BUILTIN_CVTDQ2PD, 0, 0 },
16014 { MASK_SSE2, CODE_FOR_sse2_cvtdq2ps, 0, IX86_BUILTIN_CVTDQ2PS, 0, 0 },
16016 { MASK_SSE2, CODE_FOR_sse2_cvtpd2dq, 0, IX86_BUILTIN_CVTPD2DQ, 0, 0 },
16017 { MASK_SSE2, CODE_FOR_sse2_cvtpd2pi, 0, IX86_BUILTIN_CVTPD2PI, 0, 0 },
16018 { MASK_SSE2, CODE_FOR_sse2_cvtpd2ps, 0, IX86_BUILTIN_CVTPD2PS, 0, 0 },
16019 { MASK_SSE2, CODE_FOR_sse2_cvttpd2dq, 0, IX86_BUILTIN_CVTTPD2DQ, 0, 0 },
16020 { MASK_SSE2, CODE_FOR_sse2_cvttpd2pi, 0, IX86_BUILTIN_CVTTPD2PI, 0, 0 },
16022 { MASK_SSE2, CODE_FOR_sse2_cvtpi2pd, 0, IX86_BUILTIN_CVTPI2PD, 0, 0 },
16024 { MASK_SSE2, CODE_FOR_sse2_cvtsd2si, 0, IX86_BUILTIN_CVTSD2SI, 0, 0 },
16025 { MASK_SSE2, CODE_FOR_sse2_cvttsd2si, 0, IX86_BUILTIN_CVTTSD2SI, 0, 0 },
16026 { MASK_SSE2 | MASK_64BIT, CODE_FOR_sse2_cvtsd2siq, 0, IX86_BUILTIN_CVTSD2SI64, 0, 0 },
16027 { MASK_SSE2 | MASK_64BIT, CODE_FOR_sse2_cvttsd2siq, 0, IX86_BUILTIN_CVTTSD2SI64, 0, 0 },
16029 { MASK_SSE2, CODE_FOR_sse2_cvtps2dq, 0, IX86_BUILTIN_CVTPS2DQ, 0, 0 },
16030 { MASK_SSE2, CODE_FOR_sse2_cvtps2pd, 0, IX86_BUILTIN_CVTPS2PD, 0, 0 },
16031 { MASK_SSE2, CODE_FOR_sse2_cvttps2dq, 0, IX86_BUILTIN_CVTTPS2DQ, 0, 0 },
16034 { MASK_SSE3, CODE_FOR_sse3_movshdup, 0, IX86_BUILTIN_MOVSHDUP, 0, 0 },
16035 { MASK_SSE3, CODE_FOR_sse3_movsldup, 0, IX86_BUILTIN_MOVSLDUP, 0, 0 },
16038 { MASK_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, 0, 0 },
16039 { MASK_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, 0, 0 },
16040 { MASK_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, 0, 0 },
16041 { MASK_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, 0, 0 },
16042 { MASK_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, 0, 0 },
16043 { MASK_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, 0, 0 },
16047 ix86_init_builtins (void)
16050 ix86_init_mmx_sse_builtins ();
16053 /* Set up all the MMX/SSE builtins. This is not called if TARGET_MMX
16054 is zero. Otherwise, if TARGET_SSE is not set, only expand the MMX
16057 ix86_init_mmx_sse_builtins (void)
16059 const struct builtin_description * d;
16062 tree V16QI_type_node = build_vector_type_for_mode (intQI_type_node, V16QImode);
16063 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
16064 tree V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
16065 tree V2DI_type_node
16066 = build_vector_type_for_mode (long_long_integer_type_node, V2DImode);
16067 tree V2DF_type_node = build_vector_type_for_mode (double_type_node, V2DFmode);
16068 tree V4SF_type_node = build_vector_type_for_mode (float_type_node, V4SFmode);
16069 tree V4SI_type_node = build_vector_type_for_mode (intSI_type_node, V4SImode);
16070 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
16071 tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode);
16072 tree V8HI_type_node = build_vector_type_for_mode (intHI_type_node, V8HImode);
16074 tree pchar_type_node = build_pointer_type (char_type_node);
16075 tree pcchar_type_node = build_pointer_type (
16076 build_type_variant (char_type_node, 1, 0));
16077 tree pfloat_type_node = build_pointer_type (float_type_node);
16078 tree pcfloat_type_node = build_pointer_type (
16079 build_type_variant (float_type_node, 1, 0));
16080 tree pv2si_type_node = build_pointer_type (V2SI_type_node);
16081 tree pv2di_type_node = build_pointer_type (V2DI_type_node);
16082 tree pdi_type_node = build_pointer_type (long_long_unsigned_type_node);
16085 tree int_ftype_v4sf_v4sf
16086 = build_function_type_list (integer_type_node,
16087 V4SF_type_node, V4SF_type_node, NULL_TREE);
16088 tree v4si_ftype_v4sf_v4sf
16089 = build_function_type_list (V4SI_type_node,
16090 V4SF_type_node, V4SF_type_node, NULL_TREE);
16091 /* MMX/SSE/integer conversions. */
16092 tree int_ftype_v4sf
16093 = build_function_type_list (integer_type_node,
16094 V4SF_type_node, NULL_TREE);
16095 tree int64_ftype_v4sf
16096 = build_function_type_list (long_long_integer_type_node,
16097 V4SF_type_node, NULL_TREE);
16098 tree int_ftype_v8qi
16099 = build_function_type_list (integer_type_node, V8QI_type_node, NULL_TREE);
16100 tree v4sf_ftype_v4sf_int
16101 = build_function_type_list (V4SF_type_node,
16102 V4SF_type_node, integer_type_node, NULL_TREE);
16103 tree v4sf_ftype_v4sf_int64
16104 = build_function_type_list (V4SF_type_node,
16105 V4SF_type_node, long_long_integer_type_node,
16107 tree v4sf_ftype_v4sf_v2si
16108 = build_function_type_list (V4SF_type_node,
16109 V4SF_type_node, V2SI_type_node, NULL_TREE);
16111 /* Miscellaneous. */
16112 tree v8qi_ftype_v4hi_v4hi
16113 = build_function_type_list (V8QI_type_node,
16114 V4HI_type_node, V4HI_type_node, NULL_TREE);
16115 tree v4hi_ftype_v2si_v2si
16116 = build_function_type_list (V4HI_type_node,
16117 V2SI_type_node, V2SI_type_node, NULL_TREE);
16118 tree v4sf_ftype_v4sf_v4sf_int
16119 = build_function_type_list (V4SF_type_node,
16120 V4SF_type_node, V4SF_type_node,
16121 integer_type_node, NULL_TREE);
16122 tree v2si_ftype_v4hi_v4hi
16123 = build_function_type_list (V2SI_type_node,
16124 V4HI_type_node, V4HI_type_node, NULL_TREE);
16125 tree v4hi_ftype_v4hi_int
16126 = build_function_type_list (V4HI_type_node,
16127 V4HI_type_node, integer_type_node, NULL_TREE);
16128 tree v4hi_ftype_v4hi_di
16129 = build_function_type_list (V4HI_type_node,
16130 V4HI_type_node, long_long_unsigned_type_node,
16132 tree v2si_ftype_v2si_di
16133 = build_function_type_list (V2SI_type_node,
16134 V2SI_type_node, long_long_unsigned_type_node,
16136 tree void_ftype_void
16137 = build_function_type (void_type_node, void_list_node);
16138 tree void_ftype_unsigned
16139 = build_function_type_list (void_type_node, unsigned_type_node, NULL_TREE);
16140 tree void_ftype_unsigned_unsigned
16141 = build_function_type_list (void_type_node, unsigned_type_node,
16142 unsigned_type_node, NULL_TREE);
16143 tree void_ftype_pcvoid_unsigned_unsigned
16144 = build_function_type_list (void_type_node, const_ptr_type_node,
16145 unsigned_type_node, unsigned_type_node,
16147 tree unsigned_ftype_void
16148 = build_function_type (unsigned_type_node, void_list_node);
16149 tree v2si_ftype_v4sf
16150 = build_function_type_list (V2SI_type_node, V4SF_type_node, NULL_TREE);
16151 /* Loads/stores. */
16152 tree void_ftype_v8qi_v8qi_pchar
16153 = build_function_type_list (void_type_node,
16154 V8QI_type_node, V8QI_type_node,
16155 pchar_type_node, NULL_TREE);
16156 tree v4sf_ftype_pcfloat
16157 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
16158 /* @@@ the type is bogus */
16159 tree v4sf_ftype_v4sf_pv2si
16160 = build_function_type_list (V4SF_type_node,
16161 V4SF_type_node, pv2si_type_node, NULL_TREE);
16162 tree void_ftype_pv2si_v4sf
16163 = build_function_type_list (void_type_node,
16164 pv2si_type_node, V4SF_type_node, NULL_TREE);
16165 tree void_ftype_pfloat_v4sf
16166 = build_function_type_list (void_type_node,
16167 pfloat_type_node, V4SF_type_node, NULL_TREE);
16168 tree void_ftype_pdi_di
16169 = build_function_type_list (void_type_node,
16170 pdi_type_node, long_long_unsigned_type_node,
16172 tree void_ftype_pv2di_v2di
16173 = build_function_type_list (void_type_node,
16174 pv2di_type_node, V2DI_type_node, NULL_TREE);
16175 /* Normal vector unops. */
16176 tree v4sf_ftype_v4sf
16177 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
16178 tree v16qi_ftype_v16qi
16179 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
16180 tree v8hi_ftype_v8hi
16181 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
16182 tree v4si_ftype_v4si
16183 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
16184 tree v8qi_ftype_v8qi
16185 = build_function_type_list (V8QI_type_node, V8QI_type_node, NULL_TREE);
16186 tree v4hi_ftype_v4hi
16187 = build_function_type_list (V4HI_type_node, V4HI_type_node, NULL_TREE);
16189 /* Normal vector binops. */
16190 tree v4sf_ftype_v4sf_v4sf
16191 = build_function_type_list (V4SF_type_node,
16192 V4SF_type_node, V4SF_type_node, NULL_TREE);
16193 tree v8qi_ftype_v8qi_v8qi
16194 = build_function_type_list (V8QI_type_node,
16195 V8QI_type_node, V8QI_type_node, NULL_TREE);
16196 tree v4hi_ftype_v4hi_v4hi
16197 = build_function_type_list (V4HI_type_node,
16198 V4HI_type_node, V4HI_type_node, NULL_TREE);
16199 tree v2si_ftype_v2si_v2si
16200 = build_function_type_list (V2SI_type_node,
16201 V2SI_type_node, V2SI_type_node, NULL_TREE);
16202 tree di_ftype_di_di
16203 = build_function_type_list (long_long_unsigned_type_node,
16204 long_long_unsigned_type_node,
16205 long_long_unsigned_type_node, NULL_TREE);
16207 tree di_ftype_di_di_int
16208 = build_function_type_list (long_long_unsigned_type_node,
16209 long_long_unsigned_type_node,
16210 long_long_unsigned_type_node,
16211 integer_type_node, NULL_TREE);
16213 tree v2si_ftype_v2sf
16214 = build_function_type_list (V2SI_type_node, V2SF_type_node, NULL_TREE);
16215 tree v2sf_ftype_v2si
16216 = build_function_type_list (V2SF_type_node, V2SI_type_node, NULL_TREE);
16217 tree v2si_ftype_v2si
16218 = build_function_type_list (V2SI_type_node, V2SI_type_node, NULL_TREE);
16219 tree v2sf_ftype_v2sf
16220 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
16221 tree v2sf_ftype_v2sf_v2sf
16222 = build_function_type_list (V2SF_type_node,
16223 V2SF_type_node, V2SF_type_node, NULL_TREE);
16224 tree v2si_ftype_v2sf_v2sf
16225 = build_function_type_list (V2SI_type_node,
16226 V2SF_type_node, V2SF_type_node, NULL_TREE);
16227 tree pint_type_node = build_pointer_type (integer_type_node);
16228 tree pdouble_type_node = build_pointer_type (double_type_node);
16229 tree pcdouble_type_node = build_pointer_type (
16230 build_type_variant (double_type_node, 1, 0));
16231 tree int_ftype_v2df_v2df
16232 = build_function_type_list (integer_type_node,
16233 V2DF_type_node, V2DF_type_node, NULL_TREE);
16235 tree void_ftype_pcvoid
16236 = build_function_type_list (void_type_node, const_ptr_type_node, NULL_TREE);
16237 tree v4sf_ftype_v4si
16238 = build_function_type_list (V4SF_type_node, V4SI_type_node, NULL_TREE);
16239 tree v4si_ftype_v4sf
16240 = build_function_type_list (V4SI_type_node, V4SF_type_node, NULL_TREE);
16241 tree v2df_ftype_v4si
16242 = build_function_type_list (V2DF_type_node, V4SI_type_node, NULL_TREE);
16243 tree v4si_ftype_v2df
16244 = build_function_type_list (V4SI_type_node, V2DF_type_node, NULL_TREE);
16245 tree v2si_ftype_v2df
16246 = build_function_type_list (V2SI_type_node, V2DF_type_node, NULL_TREE);
16247 tree v4sf_ftype_v2df
16248 = build_function_type_list (V4SF_type_node, V2DF_type_node, NULL_TREE);
16249 tree v2df_ftype_v2si
16250 = build_function_type_list (V2DF_type_node, V2SI_type_node, NULL_TREE);
16251 tree v2df_ftype_v4sf
16252 = build_function_type_list (V2DF_type_node, V4SF_type_node, NULL_TREE);
16253 tree int_ftype_v2df
16254 = build_function_type_list (integer_type_node, V2DF_type_node, NULL_TREE);
16255 tree int64_ftype_v2df
16256 = build_function_type_list (long_long_integer_type_node,
16257 V2DF_type_node, NULL_TREE);
16258 tree v2df_ftype_v2df_int
16259 = build_function_type_list (V2DF_type_node,
16260 V2DF_type_node, integer_type_node, NULL_TREE);
16261 tree v2df_ftype_v2df_int64
16262 = build_function_type_list (V2DF_type_node,
16263 V2DF_type_node, long_long_integer_type_node,
16265 tree v4sf_ftype_v4sf_v2df
16266 = build_function_type_list (V4SF_type_node,
16267 V4SF_type_node, V2DF_type_node, NULL_TREE);
16268 tree v2df_ftype_v2df_v4sf
16269 = build_function_type_list (V2DF_type_node,
16270 V2DF_type_node, V4SF_type_node, NULL_TREE);
16271 tree v2df_ftype_v2df_v2df_int
16272 = build_function_type_list (V2DF_type_node,
16273 V2DF_type_node, V2DF_type_node,
16276 tree v2df_ftype_v2df_pcdouble
16277 = build_function_type_list (V2DF_type_node,
16278 V2DF_type_node, pcdouble_type_node, NULL_TREE);
16279 tree void_ftype_pdouble_v2df
16280 = build_function_type_list (void_type_node,
16281 pdouble_type_node, V2DF_type_node, NULL_TREE);
16282 tree void_ftype_pint_int
16283 = build_function_type_list (void_type_node,
16284 pint_type_node, integer_type_node, NULL_TREE);
16285 tree void_ftype_v16qi_v16qi_pchar
16286 = build_function_type_list (void_type_node,
16287 V16QI_type_node, V16QI_type_node,
16288 pchar_type_node, NULL_TREE);
16289 tree v2df_ftype_pcdouble
16290 = build_function_type_list (V2DF_type_node, pcdouble_type_node, NULL_TREE);
16291 tree v2df_ftype_v2df_v2df
16292 = build_function_type_list (V2DF_type_node,
16293 V2DF_type_node, V2DF_type_node, NULL_TREE);
16294 tree v16qi_ftype_v16qi_v16qi
16295 = build_function_type_list (V16QI_type_node,
16296 V16QI_type_node, V16QI_type_node, NULL_TREE);
16297 tree v8hi_ftype_v8hi_v8hi
16298 = build_function_type_list (V8HI_type_node,
16299 V8HI_type_node, V8HI_type_node, NULL_TREE);
16300 tree v4si_ftype_v4si_v4si
16301 = build_function_type_list (V4SI_type_node,
16302 V4SI_type_node, V4SI_type_node, NULL_TREE);
16303 tree v2di_ftype_v2di_v2di
16304 = build_function_type_list (V2DI_type_node,
16305 V2DI_type_node, V2DI_type_node, NULL_TREE);
16306 tree v2di_ftype_v2df_v2df
16307 = build_function_type_list (V2DI_type_node,
16308 V2DF_type_node, V2DF_type_node, NULL_TREE);
16309 tree v2df_ftype_v2df
16310 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
16311 tree v2di_ftype_v2di_int
16312 = build_function_type_list (V2DI_type_node,
16313 V2DI_type_node, integer_type_node, NULL_TREE);
16314 tree v2di_ftype_v2di_v2di_int
16315 = build_function_type_list (V2DI_type_node, V2DI_type_node,
16316 V2DI_type_node, integer_type_node, NULL_TREE);
16317 tree v4si_ftype_v4si_int
16318 = build_function_type_list (V4SI_type_node,
16319 V4SI_type_node, integer_type_node, NULL_TREE);
16320 tree v8hi_ftype_v8hi_int
16321 = build_function_type_list (V8HI_type_node,
16322 V8HI_type_node, integer_type_node, NULL_TREE);
16323 tree v8hi_ftype_v8hi_v2di
16324 = build_function_type_list (V8HI_type_node,
16325 V8HI_type_node, V2DI_type_node, NULL_TREE);
16326 tree v4si_ftype_v4si_v2di
16327 = build_function_type_list (V4SI_type_node,
16328 V4SI_type_node, V2DI_type_node, NULL_TREE);
16329 tree v4si_ftype_v8hi_v8hi
16330 = build_function_type_list (V4SI_type_node,
16331 V8HI_type_node, V8HI_type_node, NULL_TREE);
16332 tree di_ftype_v8qi_v8qi
16333 = build_function_type_list (long_long_unsigned_type_node,
16334 V8QI_type_node, V8QI_type_node, NULL_TREE);
16335 tree di_ftype_v2si_v2si
16336 = build_function_type_list (long_long_unsigned_type_node,
16337 V2SI_type_node, V2SI_type_node, NULL_TREE);
16338 tree v2di_ftype_v16qi_v16qi
16339 = build_function_type_list (V2DI_type_node,
16340 V16QI_type_node, V16QI_type_node, NULL_TREE);
16341 tree v2di_ftype_v4si_v4si
16342 = build_function_type_list (V2DI_type_node,
16343 V4SI_type_node, V4SI_type_node, NULL_TREE);
16344 tree int_ftype_v16qi
16345 = build_function_type_list (integer_type_node, V16QI_type_node, NULL_TREE);
16346 tree v16qi_ftype_pcchar
16347 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
16348 tree void_ftype_pchar_v16qi
16349 = build_function_type_list (void_type_node,
16350 pchar_type_node, V16QI_type_node, NULL_TREE);
16353 tree float128_type;
16356 /* The __float80 type. */
16357 if (TYPE_MODE (long_double_type_node) == XFmode)
16358 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
16362 /* The __float80 type. */
16363 float80_type = make_node (REAL_TYPE);
16364 TYPE_PRECISION (float80_type) = 80;
16365 layout_type (float80_type);
16366 (*lang_hooks.types.register_builtin_type) (float80_type, "__float80");
16371 float128_type = make_node (REAL_TYPE);
16372 TYPE_PRECISION (float128_type) = 128;
16373 layout_type (float128_type);
16374 (*lang_hooks.types.register_builtin_type) (float128_type, "__float128");
16377 /* Add all builtins that are more or less simple operations on two
16379 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
16381 /* Use one of the operands; the target can have a different mode for
16382 mask-generating compares. */
16383 enum machine_mode mode;
16388 mode = insn_data[d->icode].operand[1].mode;
16393 type = v16qi_ftype_v16qi_v16qi;
16396 type = v8hi_ftype_v8hi_v8hi;
16399 type = v4si_ftype_v4si_v4si;
16402 type = v2di_ftype_v2di_v2di;
16405 type = v2df_ftype_v2df_v2df;
16408 type = v4sf_ftype_v4sf_v4sf;
16411 type = v8qi_ftype_v8qi_v8qi;
16414 type = v4hi_ftype_v4hi_v4hi;
16417 type = v2si_ftype_v2si_v2si;
16420 type = di_ftype_di_di;
16424 gcc_unreachable ();
16427 /* Override for comparisons. */
16428 if (d->icode == CODE_FOR_sse_maskcmpv4sf3
16429 || d->icode == CODE_FOR_sse_vmmaskcmpv4sf3)
16430 type = v4si_ftype_v4sf_v4sf;
16432 if (d->icode == CODE_FOR_sse2_maskcmpv2df3
16433 || d->icode == CODE_FOR_sse2_vmmaskcmpv2df3)
16434 type = v2di_ftype_v2df_v2df;
16436 def_builtin (d->mask, d->name, type, d->code);
16439 /* Add all builtins that are more or less simple operations on 1 operand. */
16440 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
16442 enum machine_mode mode;
16447 mode = insn_data[d->icode].operand[1].mode;
16452 type = v16qi_ftype_v16qi;
16455 type = v8hi_ftype_v8hi;
16458 type = v4si_ftype_v4si;
16461 type = v2df_ftype_v2df;
16464 type = v4sf_ftype_v4sf;
16467 type = v8qi_ftype_v8qi;
16470 type = v4hi_ftype_v4hi;
16473 type = v2si_ftype_v2si;
16480 def_builtin (d->mask, d->name, type, d->code);
16483 /* Add the remaining MMX insns with somewhat more complicated types. */
16484 def_builtin (MASK_MMX, "__builtin_ia32_emms", void_ftype_void, IX86_BUILTIN_EMMS);
16485 def_builtin (MASK_MMX, "__builtin_ia32_psllw", v4hi_ftype_v4hi_di, IX86_BUILTIN_PSLLW);
16486 def_builtin (MASK_MMX, "__builtin_ia32_pslld", v2si_ftype_v2si_di, IX86_BUILTIN_PSLLD);
16487 def_builtin (MASK_MMX, "__builtin_ia32_psllq", di_ftype_di_di, IX86_BUILTIN_PSLLQ);
16489 def_builtin (MASK_MMX, "__builtin_ia32_psrlw", v4hi_ftype_v4hi_di, IX86_BUILTIN_PSRLW);
16490 def_builtin (MASK_MMX, "__builtin_ia32_psrld", v2si_ftype_v2si_di, IX86_BUILTIN_PSRLD);
16491 def_builtin (MASK_MMX, "__builtin_ia32_psrlq", di_ftype_di_di, IX86_BUILTIN_PSRLQ);
16493 def_builtin (MASK_MMX, "__builtin_ia32_psraw", v4hi_ftype_v4hi_di, IX86_BUILTIN_PSRAW);
16494 def_builtin (MASK_MMX, "__builtin_ia32_psrad", v2si_ftype_v2si_di, IX86_BUILTIN_PSRAD);
16496 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_pshufw", v4hi_ftype_v4hi_int, IX86_BUILTIN_PSHUFW);
16497 def_builtin (MASK_MMX, "__builtin_ia32_pmaddwd", v2si_ftype_v4hi_v4hi, IX86_BUILTIN_PMADDWD);
16499 /* comi/ucomi insns. */
16500 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
16501 if (d->mask == MASK_SSE2)
16502 def_builtin (d->mask, d->name, int_ftype_v2df_v2df, d->code);
16504 def_builtin (d->mask, d->name, int_ftype_v4sf_v4sf, d->code);
16506 def_builtin (MASK_MMX, "__builtin_ia32_packsswb", v8qi_ftype_v4hi_v4hi, IX86_BUILTIN_PACKSSWB);
16507 def_builtin (MASK_MMX, "__builtin_ia32_packssdw", v4hi_ftype_v2si_v2si, IX86_BUILTIN_PACKSSDW);
16508 def_builtin (MASK_MMX, "__builtin_ia32_packuswb", v8qi_ftype_v4hi_v4hi, IX86_BUILTIN_PACKUSWB);
16510 def_builtin (MASK_SSE, "__builtin_ia32_ldmxcsr", void_ftype_unsigned, IX86_BUILTIN_LDMXCSR);
16511 def_builtin (MASK_SSE, "__builtin_ia32_stmxcsr", unsigned_ftype_void, IX86_BUILTIN_STMXCSR);
16512 def_builtin_const (MASK_SSE, "__builtin_ia32_cvtpi2ps", v4sf_ftype_v4sf_v2si, IX86_BUILTIN_CVTPI2PS);
16513 def_builtin_const (MASK_SSE, "__builtin_ia32_cvtps2pi", v2si_ftype_v4sf, IX86_BUILTIN_CVTPS2PI);
16514 def_builtin_const (MASK_SSE, "__builtin_ia32_cvtsi2ss", v4sf_ftype_v4sf_int, IX86_BUILTIN_CVTSI2SS);
16515 def_builtin_const (MASK_SSE | MASK_64BIT, "__builtin_ia32_cvtsi642ss", v4sf_ftype_v4sf_int64, IX86_BUILTIN_CVTSI642SS);
16516 def_builtin_const (MASK_SSE, "__builtin_ia32_cvtss2si", int_ftype_v4sf, IX86_BUILTIN_CVTSS2SI);
16517 def_builtin_const (MASK_SSE | MASK_64BIT, "__builtin_ia32_cvtss2si64", int64_ftype_v4sf, IX86_BUILTIN_CVTSS2SI64);
16518 def_builtin_const (MASK_SSE, "__builtin_ia32_cvttps2pi", v2si_ftype_v4sf, IX86_BUILTIN_CVTTPS2PI);
16519 def_builtin_const (MASK_SSE, "__builtin_ia32_cvttss2si", int_ftype_v4sf, IX86_BUILTIN_CVTTSS2SI);
16520 def_builtin_const (MASK_SSE | MASK_64BIT, "__builtin_ia32_cvttss2si64", int64_ftype_v4sf, IX86_BUILTIN_CVTTSS2SI64);
16522 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_maskmovq", void_ftype_v8qi_v8qi_pchar, IX86_BUILTIN_MASKMOVQ);
16524 def_builtin (MASK_SSE, "__builtin_ia32_loadups", v4sf_ftype_pcfloat, IX86_BUILTIN_LOADUPS);
16525 def_builtin (MASK_SSE, "__builtin_ia32_storeups", void_ftype_pfloat_v4sf, IX86_BUILTIN_STOREUPS);
16527 def_builtin (MASK_SSE, "__builtin_ia32_loadhps", v4sf_ftype_v4sf_pv2si, IX86_BUILTIN_LOADHPS);
16528 def_builtin (MASK_SSE, "__builtin_ia32_loadlps", v4sf_ftype_v4sf_pv2si, IX86_BUILTIN_LOADLPS);
16529 def_builtin (MASK_SSE, "__builtin_ia32_storehps", void_ftype_pv2si_v4sf, IX86_BUILTIN_STOREHPS);
16530 def_builtin (MASK_SSE, "__builtin_ia32_storelps", void_ftype_pv2si_v4sf, IX86_BUILTIN_STORELPS);
16532 def_builtin (MASK_SSE, "__builtin_ia32_movmskps", int_ftype_v4sf, IX86_BUILTIN_MOVMSKPS);
16533 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_pmovmskb", int_ftype_v8qi, IX86_BUILTIN_PMOVMSKB);
16534 def_builtin (MASK_SSE, "__builtin_ia32_movntps", void_ftype_pfloat_v4sf, IX86_BUILTIN_MOVNTPS);
16535 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_movntq", void_ftype_pdi_di, IX86_BUILTIN_MOVNTQ);
16537 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_sfence", void_ftype_void, IX86_BUILTIN_SFENCE);
16539 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_psadbw", di_ftype_v8qi_v8qi, IX86_BUILTIN_PSADBW);
16541 def_builtin (MASK_SSE, "__builtin_ia32_rcpps", v4sf_ftype_v4sf, IX86_BUILTIN_RCPPS);
16542 def_builtin (MASK_SSE, "__builtin_ia32_rcpss", v4sf_ftype_v4sf, IX86_BUILTIN_RCPSS);
16543 def_builtin (MASK_SSE, "__builtin_ia32_rsqrtps", v4sf_ftype_v4sf, IX86_BUILTIN_RSQRTPS);
16544 def_builtin (MASK_SSE, "__builtin_ia32_rsqrtss", v4sf_ftype_v4sf, IX86_BUILTIN_RSQRTSS);
16545 def_builtin_const (MASK_SSE, "__builtin_ia32_sqrtps", v4sf_ftype_v4sf, IX86_BUILTIN_SQRTPS);
16546 def_builtin_const (MASK_SSE, "__builtin_ia32_sqrtss", v4sf_ftype_v4sf, IX86_BUILTIN_SQRTSS);
16548 def_builtin (MASK_SSE, "__builtin_ia32_shufps", v4sf_ftype_v4sf_v4sf_int, IX86_BUILTIN_SHUFPS);
16550 /* Original 3DNow! */
16551 def_builtin (MASK_3DNOW, "__builtin_ia32_femms", void_ftype_void, IX86_BUILTIN_FEMMS);
16552 def_builtin (MASK_3DNOW, "__builtin_ia32_pavgusb", v8qi_ftype_v8qi_v8qi, IX86_BUILTIN_PAVGUSB);
16553 def_builtin (MASK_3DNOW, "__builtin_ia32_pf2id", v2si_ftype_v2sf, IX86_BUILTIN_PF2ID);
16554 def_builtin (MASK_3DNOW, "__builtin_ia32_pfacc", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFACC);
16555 def_builtin (MASK_3DNOW, "__builtin_ia32_pfadd", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFADD);
16556 def_builtin (MASK_3DNOW, "__builtin_ia32_pfcmpeq", v2si_ftype_v2sf_v2sf, IX86_BUILTIN_PFCMPEQ);
16557 def_builtin (MASK_3DNOW, "__builtin_ia32_pfcmpge", v2si_ftype_v2sf_v2sf, IX86_BUILTIN_PFCMPGE);
16558 def_builtin (MASK_3DNOW, "__builtin_ia32_pfcmpgt", v2si_ftype_v2sf_v2sf, IX86_BUILTIN_PFCMPGT);
16559 def_builtin (MASK_3DNOW, "__builtin_ia32_pfmax", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFMAX);
16560 def_builtin (MASK_3DNOW, "__builtin_ia32_pfmin", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFMIN);
16561 def_builtin (MASK_3DNOW, "__builtin_ia32_pfmul", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFMUL);
16562 def_builtin (MASK_3DNOW, "__builtin_ia32_pfrcp", v2sf_ftype_v2sf, IX86_BUILTIN_PFRCP);
16563 def_builtin (MASK_3DNOW, "__builtin_ia32_pfrcpit1", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFRCPIT1);
16564 def_builtin (MASK_3DNOW, "__builtin_ia32_pfrcpit2", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFRCPIT2);
16565 def_builtin (MASK_3DNOW, "__builtin_ia32_pfrsqrt", v2sf_ftype_v2sf, IX86_BUILTIN_PFRSQRT);
16566 def_builtin (MASK_3DNOW, "__builtin_ia32_pfrsqit1", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFRSQIT1);
16567 def_builtin (MASK_3DNOW, "__builtin_ia32_pfsub", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFSUB);
16568 def_builtin (MASK_3DNOW, "__builtin_ia32_pfsubr", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFSUBR);
16569 def_builtin (MASK_3DNOW, "__builtin_ia32_pi2fd", v2sf_ftype_v2si, IX86_BUILTIN_PI2FD);
16570 def_builtin (MASK_3DNOW, "__builtin_ia32_pmulhrw", v4hi_ftype_v4hi_v4hi, IX86_BUILTIN_PMULHRW);
16572 /* 3DNow! extension as used in the Athlon CPU. */
16573 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pf2iw", v2si_ftype_v2sf, IX86_BUILTIN_PF2IW);
16574 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pfnacc", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFNACC);
16575 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pfpnacc", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFPNACC);
16576 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pi2fw", v2sf_ftype_v2si, IX86_BUILTIN_PI2FW);
16577 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pswapdsf", v2sf_ftype_v2sf, IX86_BUILTIN_PSWAPDSF);
16578 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pswapdsi", v2si_ftype_v2si, IX86_BUILTIN_PSWAPDSI);
16581 def_builtin (MASK_SSE2, "__builtin_ia32_maskmovdqu", void_ftype_v16qi_v16qi_pchar, IX86_BUILTIN_MASKMOVDQU);
16583 def_builtin (MASK_SSE2, "__builtin_ia32_loadupd", v2df_ftype_pcdouble, IX86_BUILTIN_LOADUPD);
16584 def_builtin (MASK_SSE2, "__builtin_ia32_storeupd", void_ftype_pdouble_v2df, IX86_BUILTIN_STOREUPD);
16586 def_builtin (MASK_SSE2, "__builtin_ia32_loadhpd", v2df_ftype_v2df_pcdouble, IX86_BUILTIN_LOADHPD);
16587 def_builtin (MASK_SSE2, "__builtin_ia32_loadlpd", v2df_ftype_v2df_pcdouble, IX86_BUILTIN_LOADLPD);
16589 def_builtin (MASK_SSE2, "__builtin_ia32_movmskpd", int_ftype_v2df, IX86_BUILTIN_MOVMSKPD);
16590 def_builtin (MASK_SSE2, "__builtin_ia32_pmovmskb128", int_ftype_v16qi, IX86_BUILTIN_PMOVMSKB128);
16591 def_builtin (MASK_SSE2, "__builtin_ia32_movnti", void_ftype_pint_int, IX86_BUILTIN_MOVNTI);
16592 def_builtin (MASK_SSE2, "__builtin_ia32_movntpd", void_ftype_pdouble_v2df, IX86_BUILTIN_MOVNTPD);
16593 def_builtin (MASK_SSE2, "__builtin_ia32_movntdq", void_ftype_pv2di_v2di, IX86_BUILTIN_MOVNTDQ);
16595 def_builtin (MASK_SSE2, "__builtin_ia32_pshufd", v4si_ftype_v4si_int, IX86_BUILTIN_PSHUFD);
16596 def_builtin (MASK_SSE2, "__builtin_ia32_pshuflw", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSHUFLW);
16597 def_builtin (MASK_SSE2, "__builtin_ia32_pshufhw", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSHUFHW);
16598 def_builtin (MASK_SSE2, "__builtin_ia32_psadbw128", v2di_ftype_v16qi_v16qi, IX86_BUILTIN_PSADBW128);
16600 def_builtin_const (MASK_SSE2, "__builtin_ia32_sqrtpd", v2df_ftype_v2df, IX86_BUILTIN_SQRTPD);
16601 def_builtin_const (MASK_SSE2, "__builtin_ia32_sqrtsd", v2df_ftype_v2df, IX86_BUILTIN_SQRTSD);
16603 def_builtin (MASK_SSE2, "__builtin_ia32_shufpd", v2df_ftype_v2df_v2df_int, IX86_BUILTIN_SHUFPD);
16605 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvtdq2pd", v2df_ftype_v4si, IX86_BUILTIN_CVTDQ2PD);
16606 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvtdq2ps", v4sf_ftype_v4si, IX86_BUILTIN_CVTDQ2PS);
16608 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvtpd2dq", v4si_ftype_v2df, IX86_BUILTIN_CVTPD2DQ);
16609 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvtpd2pi", v2si_ftype_v2df, IX86_BUILTIN_CVTPD2PI);
16610 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvtpd2ps", v4sf_ftype_v2df, IX86_BUILTIN_CVTPD2PS);
16611 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvttpd2dq", v4si_ftype_v2df, IX86_BUILTIN_CVTTPD2DQ);
16612 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvttpd2pi", v2si_ftype_v2df, IX86_BUILTIN_CVTTPD2PI);
16614 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvtpi2pd", v2df_ftype_v2si, IX86_BUILTIN_CVTPI2PD);
16616 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvtsd2si", int_ftype_v2df, IX86_BUILTIN_CVTSD2SI);
16617 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvttsd2si", int_ftype_v2df, IX86_BUILTIN_CVTTSD2SI);
16618 def_builtin_const (MASK_SSE2 | MASK_64BIT, "__builtin_ia32_cvtsd2si64", int64_ftype_v2df, IX86_BUILTIN_CVTSD2SI64);
16619 def_builtin_const (MASK_SSE2 | MASK_64BIT, "__builtin_ia32_cvttsd2si64", int64_ftype_v2df, IX86_BUILTIN_CVTTSD2SI64);
16621 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvtps2dq", v4si_ftype_v4sf, IX86_BUILTIN_CVTPS2DQ);
16622 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvtps2pd", v2df_ftype_v4sf, IX86_BUILTIN_CVTPS2PD);
16623 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvttps2dq", v4si_ftype_v4sf, IX86_BUILTIN_CVTTPS2DQ);
16625 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvtsi2sd", v2df_ftype_v2df_int, IX86_BUILTIN_CVTSI2SD);
16626 def_builtin_const (MASK_SSE2 | MASK_64BIT, "__builtin_ia32_cvtsi642sd", v2df_ftype_v2df_int64, IX86_BUILTIN_CVTSI642SD);
16627 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvtsd2ss", v4sf_ftype_v4sf_v2df, IX86_BUILTIN_CVTSD2SS);
16628 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvtss2sd", v2df_ftype_v2df_v4sf, IX86_BUILTIN_CVTSS2SD);
16630 def_builtin (MASK_SSE2, "__builtin_ia32_clflush", void_ftype_pcvoid, IX86_BUILTIN_CLFLUSH);
16631 def_builtin (MASK_SSE2, "__builtin_ia32_lfence", void_ftype_void, IX86_BUILTIN_LFENCE);
16632 def_builtin (MASK_SSE2, "__builtin_ia32_mfence", void_ftype_void, IX86_BUILTIN_MFENCE);
16634 def_builtin (MASK_SSE2, "__builtin_ia32_loaddqu", v16qi_ftype_pcchar, IX86_BUILTIN_LOADDQU);
16635 def_builtin (MASK_SSE2, "__builtin_ia32_storedqu", void_ftype_pchar_v16qi, IX86_BUILTIN_STOREDQU);
16637 def_builtin (MASK_SSE2, "__builtin_ia32_pmuludq", di_ftype_v2si_v2si, IX86_BUILTIN_PMULUDQ);
16638 def_builtin (MASK_SSE2, "__builtin_ia32_pmuludq128", v2di_ftype_v4si_v4si, IX86_BUILTIN_PMULUDQ128);
16640 def_builtin (MASK_SSE2, "__builtin_ia32_psllw128", v8hi_ftype_v8hi_v2di, IX86_BUILTIN_PSLLW128);
16641 def_builtin (MASK_SSE2, "__builtin_ia32_pslld128", v4si_ftype_v4si_v2di, IX86_BUILTIN_PSLLD128);
16642 def_builtin (MASK_SSE2, "__builtin_ia32_psllq128", v2di_ftype_v2di_v2di, IX86_BUILTIN_PSLLQ128);
16644 def_builtin (MASK_SSE2, "__builtin_ia32_psrlw128", v8hi_ftype_v8hi_v2di, IX86_BUILTIN_PSRLW128);
16645 def_builtin (MASK_SSE2, "__builtin_ia32_psrld128", v4si_ftype_v4si_v2di, IX86_BUILTIN_PSRLD128);
16646 def_builtin (MASK_SSE2, "__builtin_ia32_psrlq128", v2di_ftype_v2di_v2di, IX86_BUILTIN_PSRLQ128);
16648 def_builtin (MASK_SSE2, "__builtin_ia32_psraw128", v8hi_ftype_v8hi_v2di, IX86_BUILTIN_PSRAW128);
16649 def_builtin (MASK_SSE2, "__builtin_ia32_psrad128", v4si_ftype_v4si_v2di, IX86_BUILTIN_PSRAD128);
16651 def_builtin (MASK_SSE2, "__builtin_ia32_pslldqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSLLDQI128);
16652 def_builtin (MASK_SSE2, "__builtin_ia32_psllwi128", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSLLWI128);
16653 def_builtin (MASK_SSE2, "__builtin_ia32_pslldi128", v4si_ftype_v4si_int, IX86_BUILTIN_PSLLDI128);
16654 def_builtin (MASK_SSE2, "__builtin_ia32_psllqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSLLQI128);
16656 def_builtin (MASK_SSE2, "__builtin_ia32_psrldqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSRLDQI128);
16657 def_builtin (MASK_SSE2, "__builtin_ia32_psrlwi128", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSRLWI128);
16658 def_builtin (MASK_SSE2, "__builtin_ia32_psrldi128", v4si_ftype_v4si_int, IX86_BUILTIN_PSRLDI128);
16659 def_builtin (MASK_SSE2, "__builtin_ia32_psrlqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSRLQI128);
16661 def_builtin (MASK_SSE2, "__builtin_ia32_psrawi128", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSRAWI128);
16662 def_builtin (MASK_SSE2, "__builtin_ia32_psradi128", v4si_ftype_v4si_int, IX86_BUILTIN_PSRADI128);
16664 def_builtin (MASK_SSE2, "__builtin_ia32_pmaddwd128", v4si_ftype_v8hi_v8hi, IX86_BUILTIN_PMADDWD128);
16666 /* Prescott New Instructions. */
16667 def_builtin (MASK_SSE3, "__builtin_ia32_monitor",
16668 void_ftype_pcvoid_unsigned_unsigned,
16669 IX86_BUILTIN_MONITOR);
16670 def_builtin (MASK_SSE3, "__builtin_ia32_mwait",
16671 void_ftype_unsigned_unsigned,
16672 IX86_BUILTIN_MWAIT);
16673 def_builtin (MASK_SSE3, "__builtin_ia32_movshdup",
16675 IX86_BUILTIN_MOVSHDUP);
16676 def_builtin (MASK_SSE3, "__builtin_ia32_movsldup",
16678 IX86_BUILTIN_MOVSLDUP);
16679 def_builtin (MASK_SSE3, "__builtin_ia32_lddqu",
16680 v16qi_ftype_pcchar, IX86_BUILTIN_LDDQU);
16683 def_builtin (MASK_SSSE3, "__builtin_ia32_palignr128",
16684 v2di_ftype_v2di_v2di_int, IX86_BUILTIN_PALIGNR128);
16685 def_builtin (MASK_SSSE3, "__builtin_ia32_palignr", di_ftype_di_di_int,
16686 IX86_BUILTIN_PALIGNR);
16688 /* Access to the vec_init patterns. */
16689 ftype = build_function_type_list (V2SI_type_node, integer_type_node,
16690 integer_type_node, NULL_TREE);
16691 def_builtin (MASK_MMX, "__builtin_ia32_vec_init_v2si",
16692 ftype, IX86_BUILTIN_VEC_INIT_V2SI);
16694 ftype = build_function_type_list (V4HI_type_node, short_integer_type_node,
16695 short_integer_type_node,
16696 short_integer_type_node,
16697 short_integer_type_node, NULL_TREE);
16698 def_builtin (MASK_MMX, "__builtin_ia32_vec_init_v4hi",
16699 ftype, IX86_BUILTIN_VEC_INIT_V4HI);
16701 ftype = build_function_type_list (V8QI_type_node, char_type_node,
16702 char_type_node, char_type_node,
16703 char_type_node, char_type_node,
16704 char_type_node, char_type_node,
16705 char_type_node, NULL_TREE);
16706 def_builtin (MASK_MMX, "__builtin_ia32_vec_init_v8qi",
16707 ftype, IX86_BUILTIN_VEC_INIT_V8QI);
16709 /* Access to the vec_extract patterns. */
16710 ftype = build_function_type_list (double_type_node, V2DF_type_node,
16711 integer_type_node, NULL_TREE);
16712 def_builtin (MASK_SSE, "__builtin_ia32_vec_ext_v2df",
16713 ftype, IX86_BUILTIN_VEC_EXT_V2DF);
16715 ftype = build_function_type_list (long_long_integer_type_node,
16716 V2DI_type_node, integer_type_node,
16718 def_builtin (MASK_SSE, "__builtin_ia32_vec_ext_v2di",
16719 ftype, IX86_BUILTIN_VEC_EXT_V2DI);
16721 ftype = build_function_type_list (float_type_node, V4SF_type_node,
16722 integer_type_node, NULL_TREE);
16723 def_builtin (MASK_SSE, "__builtin_ia32_vec_ext_v4sf",
16724 ftype, IX86_BUILTIN_VEC_EXT_V4SF);
16726 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
16727 integer_type_node, NULL_TREE);
16728 def_builtin (MASK_SSE, "__builtin_ia32_vec_ext_v4si",
16729 ftype, IX86_BUILTIN_VEC_EXT_V4SI);
16731 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
16732 integer_type_node, NULL_TREE);
16733 def_builtin (MASK_SSE, "__builtin_ia32_vec_ext_v8hi",
16734 ftype, IX86_BUILTIN_VEC_EXT_V8HI);
16736 ftype = build_function_type_list (intHI_type_node, V4HI_type_node,
16737 integer_type_node, NULL_TREE);
16738 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_vec_ext_v4hi",
16739 ftype, IX86_BUILTIN_VEC_EXT_V4HI);
16741 ftype = build_function_type_list (intSI_type_node, V2SI_type_node,
16742 integer_type_node, NULL_TREE);
16743 def_builtin (MASK_MMX, "__builtin_ia32_vec_ext_v2si",
16744 ftype, IX86_BUILTIN_VEC_EXT_V2SI);
16746 /* Access to the vec_set patterns. */
16747 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
16749 integer_type_node, NULL_TREE);
16750 def_builtin (MASK_SSE, "__builtin_ia32_vec_set_v8hi",
16751 ftype, IX86_BUILTIN_VEC_SET_V8HI);
16753 ftype = build_function_type_list (V4HI_type_node, V4HI_type_node,
16755 integer_type_node, NULL_TREE);
16756 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_vec_set_v4hi",
16757 ftype, IX86_BUILTIN_VEC_SET_V4HI);
16760 /* Errors in the source file can cause expand_expr to return const0_rtx
16761 where we expect a vector. To avoid crashing, use one of the vector
16762 clear instructions. */
16764 safe_vector_operand (rtx x, enum machine_mode mode)
16766 if (x == const0_rtx)
16767 x = CONST0_RTX (mode);
16771 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
16774 ix86_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
16777 tree arg0 = TREE_VALUE (arglist);
16778 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
16779 rtx op0 = expand_normal (arg0);
16780 rtx op1 = expand_normal (arg1);
16781 enum machine_mode tmode = insn_data[icode].operand[0].mode;
16782 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
16783 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
16785 if (VECTOR_MODE_P (mode0))
16786 op0 = safe_vector_operand (op0, mode0);
16787 if (VECTOR_MODE_P (mode1))
16788 op1 = safe_vector_operand (op1, mode1);
16790 if (optimize || !target
16791 || GET_MODE (target) != tmode
16792 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
16793 target = gen_reg_rtx (tmode);
16795 if (GET_MODE (op1) == SImode && mode1 == TImode)
16797 rtx x = gen_reg_rtx (V4SImode);
16798 emit_insn (gen_sse2_loadd (x, op1));
16799 op1 = gen_lowpart (TImode, x);
16802 /* The insn must want input operands in the same modes as the
16804 gcc_assert ((GET_MODE (op0) == mode0 || GET_MODE (op0) == VOIDmode)
16805 && (GET_MODE (op1) == mode1 || GET_MODE (op1) == VOIDmode));
16807 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
16808 op0 = copy_to_mode_reg (mode0, op0);
16809 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
16810 op1 = copy_to_mode_reg (mode1, op1);
16812 /* ??? Using ix86_fixup_binary_operands is problematic when
16813 we've got mismatched modes. Fake it. */
16819 if (tmode == mode0 && tmode == mode1)
16821 target = ix86_fixup_binary_operands (UNKNOWN, tmode, xops);
16825 else if (optimize || !ix86_binary_operator_ok (UNKNOWN, tmode, xops))
16827 op0 = force_reg (mode0, op0);
16828 op1 = force_reg (mode1, op1);
16829 target = gen_reg_rtx (tmode);
16832 pat = GEN_FCN (icode) (target, op0, op1);
16839 /* Subroutine of ix86_expand_builtin to take care of stores. */
16842 ix86_expand_store_builtin (enum insn_code icode, tree arglist)
16845 tree arg0 = TREE_VALUE (arglist);
16846 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
16847 rtx op0 = expand_normal (arg0);
16848 rtx op1 = expand_normal (arg1);
16849 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
16850 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
16852 if (VECTOR_MODE_P (mode1))
16853 op1 = safe_vector_operand (op1, mode1);
16855 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
16856 op1 = copy_to_mode_reg (mode1, op1);
16858 pat = GEN_FCN (icode) (op0, op1);
16864 /* Subroutine of ix86_expand_builtin to take care of unop insns. */
16867 ix86_expand_unop_builtin (enum insn_code icode, tree arglist,
16868 rtx target, int do_load)
16871 tree arg0 = TREE_VALUE (arglist);
16872 rtx op0 = expand_normal (arg0);
16873 enum machine_mode tmode = insn_data[icode].operand[0].mode;
16874 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
16876 if (optimize || !target
16877 || GET_MODE (target) != tmode
16878 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
16879 target = gen_reg_rtx (tmode);
16881 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
16884 if (VECTOR_MODE_P (mode0))
16885 op0 = safe_vector_operand (op0, mode0);
16887 if ((optimize && !register_operand (op0, mode0))
16888 || ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
16889 op0 = copy_to_mode_reg (mode0, op0);
16892 pat = GEN_FCN (icode) (target, op0);
16899 /* Subroutine of ix86_expand_builtin to take care of three special unop insns:
16900 sqrtss, rsqrtss, rcpss. */
16903 ix86_expand_unop1_builtin (enum insn_code icode, tree arglist, rtx target)
16906 tree arg0 = TREE_VALUE (arglist);
16907 rtx op1, op0 = expand_normal (arg0);
16908 enum machine_mode tmode = insn_data[icode].operand[0].mode;
16909 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
16911 if (optimize || !target
16912 || GET_MODE (target) != tmode
16913 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
16914 target = gen_reg_rtx (tmode);
16916 if (VECTOR_MODE_P (mode0))
16917 op0 = safe_vector_operand (op0, mode0);
16919 if ((optimize && !register_operand (op0, mode0))
16920 || ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
16921 op0 = copy_to_mode_reg (mode0, op0);
16924 if (! (*insn_data[icode].operand[2].predicate) (op1, mode0))
16925 op1 = copy_to_mode_reg (mode0, op1);
16927 pat = GEN_FCN (icode) (target, op0, op1);
16934 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
16937 ix86_expand_sse_compare (const struct builtin_description *d, tree arglist,
16941 tree arg0 = TREE_VALUE (arglist);
16942 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
16943 rtx op0 = expand_normal (arg0);
16944 rtx op1 = expand_normal (arg1);
16946 enum machine_mode tmode = insn_data[d->icode].operand[0].mode;
16947 enum machine_mode mode0 = insn_data[d->icode].operand[1].mode;
16948 enum machine_mode mode1 = insn_data[d->icode].operand[2].mode;
16949 enum rtx_code comparison = d->comparison;
16951 if (VECTOR_MODE_P (mode0))
16952 op0 = safe_vector_operand (op0, mode0);
16953 if (VECTOR_MODE_P (mode1))
16954 op1 = safe_vector_operand (op1, mode1);
16956 /* Swap operands if we have a comparison that isn't available in
16958 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
16960 rtx tmp = gen_reg_rtx (mode1);
16961 emit_move_insn (tmp, op1);
16966 if (optimize || !target
16967 || GET_MODE (target) != tmode
16968 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode))
16969 target = gen_reg_rtx (tmode);
16971 if ((optimize && !register_operand (op0, mode0))
16972 || ! (*insn_data[d->icode].operand[1].predicate) (op0, mode0))
16973 op0 = copy_to_mode_reg (mode0, op0);
16974 if ((optimize && !register_operand (op1, mode1))
16975 || ! (*insn_data[d->icode].operand[2].predicate) (op1, mode1))
16976 op1 = copy_to_mode_reg (mode1, op1);
16978 op2 = gen_rtx_fmt_ee (comparison, mode0, op0, op1);
16979 pat = GEN_FCN (d->icode) (target, op0, op1, op2);
16986 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
16989 ix86_expand_sse_comi (const struct builtin_description *d, tree arglist,
16993 tree arg0 = TREE_VALUE (arglist);
16994 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
16995 rtx op0 = expand_normal (arg0);
16996 rtx op1 = expand_normal (arg1);
16998 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
16999 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
17000 enum rtx_code comparison = d->comparison;
17002 if (VECTOR_MODE_P (mode0))
17003 op0 = safe_vector_operand (op0, mode0);
17004 if (VECTOR_MODE_P (mode1))
17005 op1 = safe_vector_operand (op1, mode1);
17007 /* Swap operands if we have a comparison that isn't available in
17009 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
17016 target = gen_reg_rtx (SImode);
17017 emit_move_insn (target, const0_rtx);
17018 target = gen_rtx_SUBREG (QImode, target, 0);
17020 if ((optimize && !register_operand (op0, mode0))
17021 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
17022 op0 = copy_to_mode_reg (mode0, op0);
17023 if ((optimize && !register_operand (op1, mode1))
17024 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
17025 op1 = copy_to_mode_reg (mode1, op1);
17027 op2 = gen_rtx_fmt_ee (comparison, mode0, op0, op1);
17028 pat = GEN_FCN (d->icode) (op0, op1);
17032 emit_insn (gen_rtx_SET (VOIDmode,
17033 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
17034 gen_rtx_fmt_ee (comparison, QImode,
17038 return SUBREG_REG (target);
17041 /* Return the integer constant in ARG. Constrain it to be in the range
17042 of the subparts of VEC_TYPE; issue an error if not. */
17045 get_element_number (tree vec_type, tree arg)
17047 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
17049 if (!host_integerp (arg, 1)
17050 || (elt = tree_low_cst (arg, 1), elt > max))
17052 error ("selector must be an integer constant in the range 0..%wi", max);
17059 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
17060 ix86_expand_vector_init. We DO have language-level syntax for this, in
17061 the form of (type){ init-list }. Except that since we can't place emms
17062 instructions from inside the compiler, we can't allow the use of MMX
17063 registers unless the user explicitly asks for it. So we do *not* define
17064 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
17065 we have builtins invoked by mmintrin.h that gives us license to emit
17066 these sorts of instructions. */
17069 ix86_expand_vec_init_builtin (tree type, tree arglist, rtx target)
17071 enum machine_mode tmode = TYPE_MODE (type);
17072 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
17073 int i, n_elt = GET_MODE_NUNITS (tmode);
17074 rtvec v = rtvec_alloc (n_elt);
17076 gcc_assert (VECTOR_MODE_P (tmode));
17078 for (i = 0; i < n_elt; ++i, arglist = TREE_CHAIN (arglist))
17080 rtx x = expand_normal (TREE_VALUE (arglist));
17081 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
17084 gcc_assert (arglist == NULL);
17086 if (!target || !register_operand (target, tmode))
17087 target = gen_reg_rtx (tmode);
17089 ix86_expand_vector_init (true, target, gen_rtx_PARALLEL (tmode, v));
17093 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
17094 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
17095 had a language-level syntax for referencing vector elements. */
17098 ix86_expand_vec_ext_builtin (tree arglist, rtx target)
17100 enum machine_mode tmode, mode0;
17105 arg0 = TREE_VALUE (arglist);
17106 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
17108 op0 = expand_normal (arg0);
17109 elt = get_element_number (TREE_TYPE (arg0), arg1);
17111 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
17112 mode0 = TYPE_MODE (TREE_TYPE (arg0));
17113 gcc_assert (VECTOR_MODE_P (mode0));
17115 op0 = force_reg (mode0, op0);
17117 if (optimize || !target || !register_operand (target, tmode))
17118 target = gen_reg_rtx (tmode);
17120 ix86_expand_vector_extract (true, target, op0, elt);
17125 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
17126 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
17127 a language-level syntax for referencing vector elements. */
17130 ix86_expand_vec_set_builtin (tree arglist)
17132 enum machine_mode tmode, mode1;
17133 tree arg0, arg1, arg2;
17137 arg0 = TREE_VALUE (arglist);
17138 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
17139 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
17141 tmode = TYPE_MODE (TREE_TYPE (arg0));
17142 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
17143 gcc_assert (VECTOR_MODE_P (tmode));
17145 op0 = expand_expr (arg0, NULL_RTX, tmode, 0);
17146 op1 = expand_expr (arg1, NULL_RTX, mode1, 0);
17147 elt = get_element_number (TREE_TYPE (arg0), arg2);
17149 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
17150 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
17152 op0 = force_reg (tmode, op0);
17153 op1 = force_reg (mode1, op1);
17155 ix86_expand_vector_set (true, op0, op1, elt);
17160 /* Expand an expression EXP that calls a built-in function,
17161 with result going to TARGET if that's convenient
17162 (and in mode MODE if that's convenient).
17163 SUBTARGET may be used as the target for computing one of EXP's operands.
17164 IGNORE is nonzero if the value is to be ignored. */
17167 ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
17168 enum machine_mode mode ATTRIBUTE_UNUSED,
17169 int ignore ATTRIBUTE_UNUSED)
17171 const struct builtin_description *d;
17173 enum insn_code icode;
17174 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
17175 tree arglist = TREE_OPERAND (exp, 1);
17176 tree arg0, arg1, arg2;
17177 rtx op0, op1, op2, pat;
17178 enum machine_mode tmode, mode0, mode1, mode2, mode3;
17179 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
17183 case IX86_BUILTIN_EMMS:
17184 emit_insn (gen_mmx_emms ());
17187 case IX86_BUILTIN_SFENCE:
17188 emit_insn (gen_sse_sfence ());
17191 case IX86_BUILTIN_MASKMOVQ:
17192 case IX86_BUILTIN_MASKMOVDQU:
17193 icode = (fcode == IX86_BUILTIN_MASKMOVQ
17194 ? CODE_FOR_mmx_maskmovq
17195 : CODE_FOR_sse2_maskmovdqu);
17196 /* Note the arg order is different from the operand order. */
17197 arg1 = TREE_VALUE (arglist);
17198 arg2 = TREE_VALUE (TREE_CHAIN (arglist));
17199 arg0 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
17200 op0 = expand_normal (arg0);
17201 op1 = expand_normal (arg1);
17202 op2 = expand_normal (arg2);
17203 mode0 = insn_data[icode].operand[0].mode;
17204 mode1 = insn_data[icode].operand[1].mode;
17205 mode2 = insn_data[icode].operand[2].mode;
17207 op0 = force_reg (Pmode, op0);
17208 op0 = gen_rtx_MEM (mode1, op0);
17210 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
17211 op0 = copy_to_mode_reg (mode0, op0);
17212 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
17213 op1 = copy_to_mode_reg (mode1, op1);
17214 if (! (*insn_data[icode].operand[2].predicate) (op2, mode2))
17215 op2 = copy_to_mode_reg (mode2, op2);
17216 pat = GEN_FCN (icode) (op0, op1, op2);
17222 case IX86_BUILTIN_SQRTSS:
17223 return ix86_expand_unop1_builtin (CODE_FOR_sse_vmsqrtv4sf2, arglist, target);
17224 case IX86_BUILTIN_RSQRTSS:
17225 return ix86_expand_unop1_builtin (CODE_FOR_sse_vmrsqrtv4sf2, arglist, target);
17226 case IX86_BUILTIN_RCPSS:
17227 return ix86_expand_unop1_builtin (CODE_FOR_sse_vmrcpv4sf2, arglist, target);
17229 case IX86_BUILTIN_LOADUPS:
17230 return ix86_expand_unop_builtin (CODE_FOR_sse_movups, arglist, target, 1);
17232 case IX86_BUILTIN_STOREUPS:
17233 return ix86_expand_store_builtin (CODE_FOR_sse_movups, arglist);
17235 case IX86_BUILTIN_LOADHPS:
17236 case IX86_BUILTIN_LOADLPS:
17237 case IX86_BUILTIN_LOADHPD:
17238 case IX86_BUILTIN_LOADLPD:
17239 icode = (fcode == IX86_BUILTIN_LOADHPS ? CODE_FOR_sse_loadhps
17240 : fcode == IX86_BUILTIN_LOADLPS ? CODE_FOR_sse_loadlps
17241 : fcode == IX86_BUILTIN_LOADHPD ? CODE_FOR_sse2_loadhpd
17242 : CODE_FOR_sse2_loadlpd);
17243 arg0 = TREE_VALUE (arglist);
17244 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
17245 op0 = expand_normal (arg0);
17246 op1 = expand_normal (arg1);
17247 tmode = insn_data[icode].operand[0].mode;
17248 mode0 = insn_data[icode].operand[1].mode;
17249 mode1 = insn_data[icode].operand[2].mode;
17251 op0 = force_reg (mode0, op0);
17252 op1 = gen_rtx_MEM (mode1, copy_to_mode_reg (Pmode, op1));
17253 if (optimize || target == 0
17254 || GET_MODE (target) != tmode
17255 || !register_operand (target, tmode))
17256 target = gen_reg_rtx (tmode);
17257 pat = GEN_FCN (icode) (target, op0, op1);
17263 case IX86_BUILTIN_STOREHPS:
17264 case IX86_BUILTIN_STORELPS:
17265 icode = (fcode == IX86_BUILTIN_STOREHPS ? CODE_FOR_sse_storehps
17266 : CODE_FOR_sse_storelps);
17267 arg0 = TREE_VALUE (arglist);
17268 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
17269 op0 = expand_normal (arg0);
17270 op1 = expand_normal (arg1);
17271 mode0 = insn_data[icode].operand[0].mode;
17272 mode1 = insn_data[icode].operand[1].mode;
17274 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
17275 op1 = force_reg (mode1, op1);
17277 pat = GEN_FCN (icode) (op0, op1);
17283 case IX86_BUILTIN_MOVNTPS:
17284 return ix86_expand_store_builtin (CODE_FOR_sse_movntv4sf, arglist);
17285 case IX86_BUILTIN_MOVNTQ:
17286 return ix86_expand_store_builtin (CODE_FOR_sse_movntdi, arglist);
17288 case IX86_BUILTIN_LDMXCSR:
17289 op0 = expand_normal (TREE_VALUE (arglist));
17290 target = assign_386_stack_local (SImode, SLOT_TEMP);
17291 emit_move_insn (target, op0);
17292 emit_insn (gen_sse_ldmxcsr (target));
17295 case IX86_BUILTIN_STMXCSR:
17296 target = assign_386_stack_local (SImode, SLOT_TEMP);
17297 emit_insn (gen_sse_stmxcsr (target));
17298 return copy_to_mode_reg (SImode, target);
17300 case IX86_BUILTIN_SHUFPS:
17301 case IX86_BUILTIN_SHUFPD:
17302 icode = (fcode == IX86_BUILTIN_SHUFPS
17303 ? CODE_FOR_sse_shufps
17304 : CODE_FOR_sse2_shufpd);
17305 arg0 = TREE_VALUE (arglist);
17306 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
17307 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
17308 op0 = expand_normal (arg0);
17309 op1 = expand_normal (arg1);
17310 op2 = expand_normal (arg2);
17311 tmode = insn_data[icode].operand[0].mode;
17312 mode0 = insn_data[icode].operand[1].mode;
17313 mode1 = insn_data[icode].operand[2].mode;
17314 mode2 = insn_data[icode].operand[3].mode;
17316 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
17317 op0 = copy_to_mode_reg (mode0, op0);
17318 if ((optimize && !register_operand (op1, mode1))
17319 || !(*insn_data[icode].operand[2].predicate) (op1, mode1))
17320 op1 = copy_to_mode_reg (mode1, op1);
17321 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
17323 /* @@@ better error message */
17324 error ("mask must be an immediate");
17325 return gen_reg_rtx (tmode);
17327 if (optimize || target == 0
17328 || GET_MODE (target) != tmode
17329 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
17330 target = gen_reg_rtx (tmode);
17331 pat = GEN_FCN (icode) (target, op0, op1, op2);
17337 case IX86_BUILTIN_PSHUFW:
17338 case IX86_BUILTIN_PSHUFD:
17339 case IX86_BUILTIN_PSHUFHW:
17340 case IX86_BUILTIN_PSHUFLW:
17341 icode = ( fcode == IX86_BUILTIN_PSHUFHW ? CODE_FOR_sse2_pshufhw
17342 : fcode == IX86_BUILTIN_PSHUFLW ? CODE_FOR_sse2_pshuflw
17343 : fcode == IX86_BUILTIN_PSHUFD ? CODE_FOR_sse2_pshufd
17344 : CODE_FOR_mmx_pshufw);
17345 arg0 = TREE_VALUE (arglist);
17346 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
17347 op0 = expand_normal (arg0);
17348 op1 = expand_normal (arg1);
17349 tmode = insn_data[icode].operand[0].mode;
17350 mode1 = insn_data[icode].operand[1].mode;
17351 mode2 = insn_data[icode].operand[2].mode;
17353 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
17354 op0 = copy_to_mode_reg (mode1, op0);
17355 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
17357 /* @@@ better error message */
17358 error ("mask must be an immediate");
17362 || GET_MODE (target) != tmode
17363 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
17364 target = gen_reg_rtx (tmode);
17365 pat = GEN_FCN (icode) (target, op0, op1);
17371 case IX86_BUILTIN_PSLLDQI128:
17372 case IX86_BUILTIN_PSRLDQI128:
17373 icode = ( fcode == IX86_BUILTIN_PSLLDQI128 ? CODE_FOR_sse2_ashlti3
17374 : CODE_FOR_sse2_lshrti3);
17375 arg0 = TREE_VALUE (arglist);
17376 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
17377 op0 = expand_normal (arg0);
17378 op1 = expand_normal (arg1);
17379 tmode = insn_data[icode].operand[0].mode;
17380 mode1 = insn_data[icode].operand[1].mode;
17381 mode2 = insn_data[icode].operand[2].mode;
17383 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
17385 op0 = copy_to_reg (op0);
17386 op0 = simplify_gen_subreg (mode1, op0, GET_MODE (op0), 0);
17388 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
17390 error ("shift must be an immediate");
17393 target = gen_reg_rtx (V2DImode);
17394 pat = GEN_FCN (icode) (simplify_gen_subreg (tmode, target, V2DImode, 0), op0, op1);
17400 case IX86_BUILTIN_FEMMS:
17401 emit_insn (gen_mmx_femms ());
17404 case IX86_BUILTIN_PAVGUSB:
17405 return ix86_expand_binop_builtin (CODE_FOR_mmx_uavgv8qi3, arglist, target);
17407 case IX86_BUILTIN_PF2ID:
17408 return ix86_expand_unop_builtin (CODE_FOR_mmx_pf2id, arglist, target, 0);
17410 case IX86_BUILTIN_PFACC:
17411 return ix86_expand_binop_builtin (CODE_FOR_mmx_haddv2sf3, arglist, target);
17413 case IX86_BUILTIN_PFADD:
17414 return ix86_expand_binop_builtin (CODE_FOR_mmx_addv2sf3, arglist, target);
17416 case IX86_BUILTIN_PFCMPEQ:
17417 return ix86_expand_binop_builtin (CODE_FOR_mmx_eqv2sf3, arglist, target);
17419 case IX86_BUILTIN_PFCMPGE:
17420 return ix86_expand_binop_builtin (CODE_FOR_mmx_gev2sf3, arglist, target);
17422 case IX86_BUILTIN_PFCMPGT:
17423 return ix86_expand_binop_builtin (CODE_FOR_mmx_gtv2sf3, arglist, target);
17425 case IX86_BUILTIN_PFMAX:
17426 return ix86_expand_binop_builtin (CODE_FOR_mmx_smaxv2sf3, arglist, target);
17428 case IX86_BUILTIN_PFMIN:
17429 return ix86_expand_binop_builtin (CODE_FOR_mmx_sminv2sf3, arglist, target);
17431 case IX86_BUILTIN_PFMUL:
17432 return ix86_expand_binop_builtin (CODE_FOR_mmx_mulv2sf3, arglist, target);
17434 case IX86_BUILTIN_PFRCP:
17435 return ix86_expand_unop_builtin (CODE_FOR_mmx_rcpv2sf2, arglist, target, 0);
17437 case IX86_BUILTIN_PFRCPIT1:
17438 return ix86_expand_binop_builtin (CODE_FOR_mmx_rcpit1v2sf3, arglist, target);
17440 case IX86_BUILTIN_PFRCPIT2:
17441 return ix86_expand_binop_builtin (CODE_FOR_mmx_rcpit2v2sf3, arglist, target);
17443 case IX86_BUILTIN_PFRSQIT1:
17444 return ix86_expand_binop_builtin (CODE_FOR_mmx_rsqit1v2sf3, arglist, target);
17446 case IX86_BUILTIN_PFRSQRT:
17447 return ix86_expand_unop_builtin (CODE_FOR_mmx_rsqrtv2sf2, arglist, target, 0);
17449 case IX86_BUILTIN_PFSUB:
17450 return ix86_expand_binop_builtin (CODE_FOR_mmx_subv2sf3, arglist, target);
17452 case IX86_BUILTIN_PFSUBR:
17453 return ix86_expand_binop_builtin (CODE_FOR_mmx_subrv2sf3, arglist, target);
17455 case IX86_BUILTIN_PI2FD:
17456 return ix86_expand_unop_builtin (CODE_FOR_mmx_floatv2si2, arglist, target, 0);
17458 case IX86_BUILTIN_PMULHRW:
17459 return ix86_expand_binop_builtin (CODE_FOR_mmx_pmulhrwv4hi3, arglist, target);
17461 case IX86_BUILTIN_PF2IW:
17462 return ix86_expand_unop_builtin (CODE_FOR_mmx_pf2iw, arglist, target, 0);
17464 case IX86_BUILTIN_PFNACC:
17465 return ix86_expand_binop_builtin (CODE_FOR_mmx_hsubv2sf3, arglist, target);
17467 case IX86_BUILTIN_PFPNACC:
17468 return ix86_expand_binop_builtin (CODE_FOR_mmx_addsubv2sf3, arglist, target);
17470 case IX86_BUILTIN_PI2FW:
17471 return ix86_expand_unop_builtin (CODE_FOR_mmx_pi2fw, arglist, target, 0);
17473 case IX86_BUILTIN_PSWAPDSI:
17474 return ix86_expand_unop_builtin (CODE_FOR_mmx_pswapdv2si2, arglist, target, 0);
17476 case IX86_BUILTIN_PSWAPDSF:
17477 return ix86_expand_unop_builtin (CODE_FOR_mmx_pswapdv2sf2, arglist, target, 0);
17479 case IX86_BUILTIN_SQRTSD:
17480 return ix86_expand_unop1_builtin (CODE_FOR_sse2_vmsqrtv2df2, arglist, target);
17481 case IX86_BUILTIN_LOADUPD:
17482 return ix86_expand_unop_builtin (CODE_FOR_sse2_movupd, arglist, target, 1);
17483 case IX86_BUILTIN_STOREUPD:
17484 return ix86_expand_store_builtin (CODE_FOR_sse2_movupd, arglist);
17486 case IX86_BUILTIN_MFENCE:
17487 emit_insn (gen_sse2_mfence ());
17489 case IX86_BUILTIN_LFENCE:
17490 emit_insn (gen_sse2_lfence ());
17493 case IX86_BUILTIN_CLFLUSH:
17494 arg0 = TREE_VALUE (arglist);
17495 op0 = expand_normal (arg0);
17496 icode = CODE_FOR_sse2_clflush;
17497 if (! (*insn_data[icode].operand[0].predicate) (op0, Pmode))
17498 op0 = copy_to_mode_reg (Pmode, op0);
17500 emit_insn (gen_sse2_clflush (op0));
17503 case IX86_BUILTIN_MOVNTPD:
17504 return ix86_expand_store_builtin (CODE_FOR_sse2_movntv2df, arglist);
17505 case IX86_BUILTIN_MOVNTDQ:
17506 return ix86_expand_store_builtin (CODE_FOR_sse2_movntv2di, arglist);
17507 case IX86_BUILTIN_MOVNTI:
17508 return ix86_expand_store_builtin (CODE_FOR_sse2_movntsi, arglist);
17510 case IX86_BUILTIN_LOADDQU:
17511 return ix86_expand_unop_builtin (CODE_FOR_sse2_movdqu, arglist, target, 1);
17512 case IX86_BUILTIN_STOREDQU:
17513 return ix86_expand_store_builtin (CODE_FOR_sse2_movdqu, arglist);
17515 case IX86_BUILTIN_MONITOR:
17516 arg0 = TREE_VALUE (arglist);
17517 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
17518 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
17519 op0 = expand_normal (arg0);
17520 op1 = expand_normal (arg1);
17521 op2 = expand_normal (arg2);
17523 op0 = copy_to_mode_reg (Pmode, op0);
17525 op1 = copy_to_mode_reg (SImode, op1);
17527 op2 = copy_to_mode_reg (SImode, op2);
17529 emit_insn (gen_sse3_monitor (op0, op1, op2));
17531 emit_insn (gen_sse3_monitor64 (op0, op1, op2));
17534 case IX86_BUILTIN_MWAIT:
17535 arg0 = TREE_VALUE (arglist);
17536 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
17537 op0 = expand_normal (arg0);
17538 op1 = expand_normal (arg1);
17540 op0 = copy_to_mode_reg (SImode, op0);
17542 op1 = copy_to_mode_reg (SImode, op1);
17543 emit_insn (gen_sse3_mwait (op0, op1));
17546 case IX86_BUILTIN_LDDQU:
17547 return ix86_expand_unop_builtin (CODE_FOR_sse3_lddqu, arglist,
17550 case IX86_BUILTIN_PALIGNR:
17551 case IX86_BUILTIN_PALIGNR128:
17552 if (fcode == IX86_BUILTIN_PALIGNR)
17554 icode = CODE_FOR_ssse3_palignrdi;
17559 icode = CODE_FOR_ssse3_palignrti;
17562 arg0 = TREE_VALUE (arglist);
17563 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
17564 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
17565 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
17566 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
17567 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
17568 tmode = insn_data[icode].operand[0].mode;
17569 mode1 = insn_data[icode].operand[1].mode;
17570 mode2 = insn_data[icode].operand[2].mode;
17571 mode3 = insn_data[icode].operand[3].mode;
17573 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
17575 op0 = copy_to_reg (op0);
17576 op0 = simplify_gen_subreg (mode1, op0, GET_MODE (op0), 0);
17578 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
17580 op1 = copy_to_reg (op1);
17581 op1 = simplify_gen_subreg (mode2, op1, GET_MODE (op1), 0);
17583 if (! (*insn_data[icode].operand[3].predicate) (op2, mode3))
17585 error ("shift must be an immediate");
17588 target = gen_reg_rtx (mode);
17589 pat = GEN_FCN (icode) (simplify_gen_subreg (tmode, target, mode, 0),
17596 case IX86_BUILTIN_VEC_INIT_V2SI:
17597 case IX86_BUILTIN_VEC_INIT_V4HI:
17598 case IX86_BUILTIN_VEC_INIT_V8QI:
17599 return ix86_expand_vec_init_builtin (TREE_TYPE (exp), arglist, target);
17601 case IX86_BUILTIN_VEC_EXT_V2DF:
17602 case IX86_BUILTIN_VEC_EXT_V2DI:
17603 case IX86_BUILTIN_VEC_EXT_V4SF:
17604 case IX86_BUILTIN_VEC_EXT_V4SI:
17605 case IX86_BUILTIN_VEC_EXT_V8HI:
17606 case IX86_BUILTIN_VEC_EXT_V2SI:
17607 case IX86_BUILTIN_VEC_EXT_V4HI:
17608 return ix86_expand_vec_ext_builtin (arglist, target);
17610 case IX86_BUILTIN_VEC_SET_V8HI:
17611 case IX86_BUILTIN_VEC_SET_V4HI:
17612 return ix86_expand_vec_set_builtin (arglist);
17618 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
17619 if (d->code == fcode)
17621 /* Compares are treated specially. */
17622 if (d->icode == CODE_FOR_sse_maskcmpv4sf3
17623 || d->icode == CODE_FOR_sse_vmmaskcmpv4sf3
17624 || d->icode == CODE_FOR_sse2_maskcmpv2df3
17625 || d->icode == CODE_FOR_sse2_vmmaskcmpv2df3)
17626 return ix86_expand_sse_compare (d, arglist, target);
17628 return ix86_expand_binop_builtin (d->icode, arglist, target);
17631 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
17632 if (d->code == fcode)
17633 return ix86_expand_unop_builtin (d->icode, arglist, target, 0);
17635 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
17636 if (d->code == fcode)
17637 return ix86_expand_sse_comi (d, arglist, target);
17639 gcc_unreachable ();
17642 /* Store OPERAND to the memory after reload is completed. This means
17643 that we can't easily use assign_stack_local. */
17645 ix86_force_to_memory (enum machine_mode mode, rtx operand)
17649 gcc_assert (reload_completed);
17650 if (TARGET_RED_ZONE)
17652 result = gen_rtx_MEM (mode,
17653 gen_rtx_PLUS (Pmode,
17655 GEN_INT (-RED_ZONE_SIZE)));
17656 emit_move_insn (result, operand);
17658 else if (!TARGET_RED_ZONE && TARGET_64BIT)
17664 operand = gen_lowpart (DImode, operand);
17668 gen_rtx_SET (VOIDmode,
17669 gen_rtx_MEM (DImode,
17670 gen_rtx_PRE_DEC (DImode,
17671 stack_pointer_rtx)),
17675 gcc_unreachable ();
17677 result = gen_rtx_MEM (mode, stack_pointer_rtx);
17686 split_di (&operand, 1, operands, operands + 1);
17688 gen_rtx_SET (VOIDmode,
17689 gen_rtx_MEM (SImode,
17690 gen_rtx_PRE_DEC (Pmode,
17691 stack_pointer_rtx)),
17694 gen_rtx_SET (VOIDmode,
17695 gen_rtx_MEM (SImode,
17696 gen_rtx_PRE_DEC (Pmode,
17697 stack_pointer_rtx)),
17702 /* Store HImodes as SImodes. */
17703 operand = gen_lowpart (SImode, operand);
17707 gen_rtx_SET (VOIDmode,
17708 gen_rtx_MEM (GET_MODE (operand),
17709 gen_rtx_PRE_DEC (SImode,
17710 stack_pointer_rtx)),
17714 gcc_unreachable ();
17716 result = gen_rtx_MEM (mode, stack_pointer_rtx);
17721 /* Free operand from the memory. */
17723 ix86_free_from_memory (enum machine_mode mode)
17725 if (!TARGET_RED_ZONE)
17729 if (mode == DImode || TARGET_64BIT)
17733 /* Use LEA to deallocate stack space. In peephole2 it will be converted
17734 to pop or add instruction if registers are available. */
17735 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
17736 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
17741 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
17742 QImode must go into class Q_REGS.
17743 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
17744 movdf to do mem-to-mem moves through integer regs. */
17746 ix86_preferred_reload_class (rtx x, enum reg_class class)
17748 enum machine_mode mode = GET_MODE (x);
17750 /* We're only allowed to return a subclass of CLASS. Many of the
17751 following checks fail for NO_REGS, so eliminate that early. */
17752 if (class == NO_REGS)
17755 /* All classes can load zeros. */
17756 if (x == CONST0_RTX (mode))
17759 /* Force constants into memory if we are loading a (nonzero) constant into
17760 an MMX or SSE register. This is because there are no MMX/SSE instructions
17761 to load from a constant. */
17763 && (MAYBE_MMX_CLASS_P (class) || MAYBE_SSE_CLASS_P (class)))
17766 /* Prefer SSE regs only, if we can use them for math. */
17767 if (TARGET_SSE_MATH && !TARGET_MIX_SSE_I387 && SSE_FLOAT_MODE_P (mode))
17768 return SSE_CLASS_P (class) ? class : NO_REGS;
17770 /* Floating-point constants need more complex checks. */
17771 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != VOIDmode)
17773 /* General regs can load everything. */
17774 if (reg_class_subset_p (class, GENERAL_REGS))
17777 /* Floats can load 0 and 1 plus some others. Note that we eliminated
17778 zero above. We only want to wind up preferring 80387 registers if
17779 we plan on doing computation with them. */
17781 && standard_80387_constant_p (x))
17783 /* Limit class to non-sse. */
17784 if (class == FLOAT_SSE_REGS)
17786 if (class == FP_TOP_SSE_REGS)
17788 if (class == FP_SECOND_SSE_REGS)
17789 return FP_SECOND_REG;
17790 if (class == FLOAT_INT_REGS || class == FLOAT_REGS)
17797 /* Generally when we see PLUS here, it's the function invariant
17798 (plus soft-fp const_int). Which can only be computed into general
17800 if (GET_CODE (x) == PLUS)
17801 return reg_class_subset_p (class, GENERAL_REGS) ? class : NO_REGS;
17803 /* QImode constants are easy to load, but non-constant QImode data
17804 must go into Q_REGS. */
17805 if (GET_MODE (x) == QImode && !CONSTANT_P (x))
17807 if (reg_class_subset_p (class, Q_REGS))
17809 if (reg_class_subset_p (Q_REGS, class))
17817 /* Discourage putting floating-point values in SSE registers unless
17818 SSE math is being used, and likewise for the 387 registers. */
17820 ix86_preferred_output_reload_class (rtx x, enum reg_class class)
17822 enum machine_mode mode = GET_MODE (x);
17824 /* Restrict the output reload class to the register bank that we are doing
17825 math on. If we would like not to return a subset of CLASS, reject this
17826 alternative: if reload cannot do this, it will still use its choice. */
17827 mode = GET_MODE (x);
17828 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
17829 return MAYBE_SSE_CLASS_P (class) ? SSE_REGS : NO_REGS;
17831 if (TARGET_80387 && SCALAR_FLOAT_MODE_P (mode))
17833 if (class == FP_TOP_SSE_REGS)
17835 else if (class == FP_SECOND_SSE_REGS)
17836 return FP_SECOND_REG;
17838 return FLOAT_CLASS_P (class) ? class : NO_REGS;
17844 /* If we are copying between general and FP registers, we need a memory
17845 location. The same is true for SSE and MMX registers.
17847 The macro can't work reliably when one of the CLASSES is class containing
17848 registers from multiple units (SSE, MMX, integer). We avoid this by never
17849 combining those units in single alternative in the machine description.
17850 Ensure that this constraint holds to avoid unexpected surprises.
17852 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
17853 enforce these sanity checks. */
17856 ix86_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
17857 enum machine_mode mode, int strict)
17859 if (MAYBE_FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class1)
17860 || MAYBE_FLOAT_CLASS_P (class2) != FLOAT_CLASS_P (class2)
17861 || MAYBE_SSE_CLASS_P (class1) != SSE_CLASS_P (class1)
17862 || MAYBE_SSE_CLASS_P (class2) != SSE_CLASS_P (class2)
17863 || MAYBE_MMX_CLASS_P (class1) != MMX_CLASS_P (class1)
17864 || MAYBE_MMX_CLASS_P (class2) != MMX_CLASS_P (class2))
17866 gcc_assert (!strict);
17870 if (FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class2))
17873 /* ??? This is a lie. We do have moves between mmx/general, and for
17874 mmx/sse2. But by saying we need secondary memory we discourage the
17875 register allocator from using the mmx registers unless needed. */
17876 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2))
17879 if (SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
17881 /* SSE1 doesn't have any direct moves from other classes. */
17885 /* If the target says that inter-unit moves are more expensive
17886 than moving through memory, then don't generate them. */
17887 if (!TARGET_INTER_UNIT_MOVES && !optimize_size)
17890 /* Between SSE and general, we have moves no larger than word size. */
17891 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
17894 /* ??? For the cost of one register reformat penalty, we could use
17895 the same instructions to move SFmode and DFmode data, but the
17896 relevant move patterns don't support those alternatives. */
17897 if (mode == SFmode || mode == DFmode)
17904 /* Return true if the registers in CLASS cannot represent the change from
17905 modes FROM to TO. */
17908 ix86_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
17909 enum reg_class class)
17914 /* x87 registers can't do subreg at all, as all values are reformatted
17915 to extended precision. */
17916 if (MAYBE_FLOAT_CLASS_P (class))
17919 if (MAYBE_SSE_CLASS_P (class) || MAYBE_MMX_CLASS_P (class))
17921 /* Vector registers do not support QI or HImode loads. If we don't
17922 disallow a change to these modes, reload will assume it's ok to
17923 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
17924 the vec_dupv4hi pattern. */
17925 if (GET_MODE_SIZE (from) < 4)
17928 /* Vector registers do not support subreg with nonzero offsets, which
17929 are otherwise valid for integer registers. Since we can't see
17930 whether we have a nonzero offset from here, prohibit all
17931 nonparadoxical subregs changing size. */
17932 if (GET_MODE_SIZE (to) < GET_MODE_SIZE (from))
17939 /* Return the cost of moving data from a register in class CLASS1 to
17940 one in class CLASS2.
17942 It is not required that the cost always equal 2 when FROM is the same as TO;
17943 on some machines it is expensive to move between registers if they are not
17944 general registers. */
17947 ix86_register_move_cost (enum machine_mode mode, enum reg_class class1,
17948 enum reg_class class2)
17950 /* In case we require secondary memory, compute cost of the store followed
17951 by load. In order to avoid bad register allocation choices, we need
17952 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
17954 if (ix86_secondary_memory_needed (class1, class2, mode, 0))
17958 cost += MAX (MEMORY_MOVE_COST (mode, class1, 0),
17959 MEMORY_MOVE_COST (mode, class1, 1));
17960 cost += MAX (MEMORY_MOVE_COST (mode, class2, 0),
17961 MEMORY_MOVE_COST (mode, class2, 1));
17963 /* In case of copying from general_purpose_register we may emit multiple
17964 stores followed by single load causing memory size mismatch stall.
17965 Count this as arbitrarily high cost of 20. */
17966 if (CLASS_MAX_NREGS (class1, mode) > CLASS_MAX_NREGS (class2, mode))
17969 /* In the case of FP/MMX moves, the registers actually overlap, and we
17970 have to switch modes in order to treat them differently. */
17971 if ((MMX_CLASS_P (class1) && MAYBE_FLOAT_CLASS_P (class2))
17972 || (MMX_CLASS_P (class2) && MAYBE_FLOAT_CLASS_P (class1)))
17978 /* Moves between SSE/MMX and integer unit are expensive. */
17979 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2)
17980 || SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
17981 return ix86_cost->mmxsse_to_integer;
17982 if (MAYBE_FLOAT_CLASS_P (class1))
17983 return ix86_cost->fp_move;
17984 if (MAYBE_SSE_CLASS_P (class1))
17985 return ix86_cost->sse_move;
17986 if (MAYBE_MMX_CLASS_P (class1))
17987 return ix86_cost->mmx_move;
17991 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
17994 ix86_hard_regno_mode_ok (int regno, enum machine_mode mode)
17996 /* Flags and only flags can only hold CCmode values. */
17997 if (CC_REGNO_P (regno))
17998 return GET_MODE_CLASS (mode) == MODE_CC;
17999 if (GET_MODE_CLASS (mode) == MODE_CC
18000 || GET_MODE_CLASS (mode) == MODE_RANDOM
18001 || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
18003 if (FP_REGNO_P (regno))
18004 return VALID_FP_MODE_P (mode);
18005 if (SSE_REGNO_P (regno))
18007 /* We implement the move patterns for all vector modes into and
18008 out of SSE registers, even when no operation instructions
18010 return (VALID_SSE_REG_MODE (mode)
18011 || VALID_SSE2_REG_MODE (mode)
18012 || VALID_MMX_REG_MODE (mode)
18013 || VALID_MMX_REG_MODE_3DNOW (mode));
18015 if (MMX_REGNO_P (regno))
18017 /* We implement the move patterns for 3DNOW modes even in MMX mode,
18018 so if the register is available at all, then we can move data of
18019 the given mode into or out of it. */
18020 return (VALID_MMX_REG_MODE (mode)
18021 || VALID_MMX_REG_MODE_3DNOW (mode));
18024 if (mode == QImode)
18026 /* Take care for QImode values - they can be in non-QI regs,
18027 but then they do cause partial register stalls. */
18028 if (regno < 4 || TARGET_64BIT)
18030 if (!TARGET_PARTIAL_REG_STALL)
18032 return reload_in_progress || reload_completed;
18034 /* We handle both integer and floats in the general purpose registers. */
18035 else if (VALID_INT_MODE_P (mode))
18037 else if (VALID_FP_MODE_P (mode))
18039 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
18040 on to use that value in smaller contexts, this can easily force a
18041 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
18042 supporting DImode, allow it. */
18043 else if (VALID_MMX_REG_MODE_3DNOW (mode) || VALID_MMX_REG_MODE (mode))
18049 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
18050 tieable integer mode. */
18053 ix86_tieable_integer_mode_p (enum machine_mode mode)
18062 return TARGET_64BIT || !TARGET_PARTIAL_REG_STALL;
18065 return TARGET_64BIT;
18072 /* Return true if MODE1 is accessible in a register that can hold MODE2
18073 without copying. That is, all register classes that can hold MODE2
18074 can also hold MODE1. */
18077 ix86_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
18079 if (mode1 == mode2)
18082 if (ix86_tieable_integer_mode_p (mode1)
18083 && ix86_tieable_integer_mode_p (mode2))
18086 /* MODE2 being XFmode implies fp stack or general regs, which means we
18087 can tie any smaller floating point modes to it. Note that we do not
18088 tie this with TFmode. */
18089 if (mode2 == XFmode)
18090 return mode1 == SFmode || mode1 == DFmode;
18092 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
18093 that we can tie it with SFmode. */
18094 if (mode2 == DFmode)
18095 return mode1 == SFmode;
18097 /* If MODE2 is only appropriate for an SSE register, then tie with
18098 any other mode acceptable to SSE registers. */
18099 if (GET_MODE_SIZE (mode2) >= 8
18100 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode2))
18101 return ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode1);
18103 /* If MODE2 is appropriate for an MMX (or SSE) register, then tie
18104 with any other mode acceptable to MMX registers. */
18105 if (GET_MODE_SIZE (mode2) == 8
18106 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode2))
18107 return ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode1);
18112 /* Return the cost of moving data of mode M between a
18113 register and memory. A value of 2 is the default; this cost is
18114 relative to those in `REGISTER_MOVE_COST'.
18116 If moving between registers and memory is more expensive than
18117 between two registers, you should define this macro to express the
18120 Model also increased moving costs of QImode registers in non
18124 ix86_memory_move_cost (enum machine_mode mode, enum reg_class class, int in)
18126 if (FLOAT_CLASS_P (class))
18143 return in ? ix86_cost->fp_load [index] : ix86_cost->fp_store [index];
18145 if (SSE_CLASS_P (class))
18148 switch (GET_MODE_SIZE (mode))
18162 return in ? ix86_cost->sse_load [index] : ix86_cost->sse_store [index];
18164 if (MMX_CLASS_P (class))
18167 switch (GET_MODE_SIZE (mode))
18178 return in ? ix86_cost->mmx_load [index] : ix86_cost->mmx_store [index];
18180 switch (GET_MODE_SIZE (mode))
18184 return (Q_CLASS_P (class) ? ix86_cost->int_load[0]
18185 : ix86_cost->movzbl_load);
18187 return (Q_CLASS_P (class) ? ix86_cost->int_store[0]
18188 : ix86_cost->int_store[0] + 4);
18191 return in ? ix86_cost->int_load[1] : ix86_cost->int_store[1];
18193 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
18194 if (mode == TFmode)
18196 return ((in ? ix86_cost->int_load[2] : ix86_cost->int_store[2])
18197 * (((int) GET_MODE_SIZE (mode)
18198 + UNITS_PER_WORD - 1) / UNITS_PER_WORD));
18202 /* Compute a (partial) cost for rtx X. Return true if the complete
18203 cost has been computed, and false if subexpressions should be
18204 scanned. In either case, *TOTAL contains the cost result. */
18207 ix86_rtx_costs (rtx x, int code, int outer_code, int *total)
18209 enum machine_mode mode = GET_MODE (x);
18217 if (TARGET_64BIT && !x86_64_immediate_operand (x, VOIDmode))
18219 else if (TARGET_64BIT && !x86_64_zext_immediate_operand (x, VOIDmode))
18221 else if (flag_pic && SYMBOLIC_CONST (x)
18223 || (!GET_CODE (x) != LABEL_REF
18224 && (GET_CODE (x) != SYMBOL_REF
18225 || !SYMBOL_REF_LOCAL_P (x)))))
18232 if (mode == VOIDmode)
18235 switch (standard_80387_constant_p (x))
18240 default: /* Other constants */
18245 /* Start with (MEM (SYMBOL_REF)), since that's where
18246 it'll probably end up. Add a penalty for size. */
18247 *total = (COSTS_N_INSNS (1)
18248 + (flag_pic != 0 && !TARGET_64BIT)
18249 + (mode == SFmode ? 0 : mode == DFmode ? 1 : 2));
18255 /* The zero extensions is often completely free on x86_64, so make
18256 it as cheap as possible. */
18257 if (TARGET_64BIT && mode == DImode
18258 && GET_MODE (XEXP (x, 0)) == SImode)
18260 else if (TARGET_ZERO_EXTEND_WITH_AND)
18261 *total = ix86_cost->add;
18263 *total = ix86_cost->movzx;
18267 *total = ix86_cost->movsx;
18271 if (GET_CODE (XEXP (x, 1)) == CONST_INT
18272 && (GET_MODE (XEXP (x, 0)) != DImode || TARGET_64BIT))
18274 HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
18277 *total = ix86_cost->add;
18280 if ((value == 2 || value == 3)
18281 && ix86_cost->lea <= ix86_cost->shift_const)
18283 *total = ix86_cost->lea;
18293 if (!TARGET_64BIT && GET_MODE (XEXP (x, 0)) == DImode)
18295 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
18297 if (INTVAL (XEXP (x, 1)) > 32)
18298 *total = ix86_cost->shift_const + COSTS_N_INSNS (2);
18300 *total = ix86_cost->shift_const * 2;
18304 if (GET_CODE (XEXP (x, 1)) == AND)
18305 *total = ix86_cost->shift_var * 2;
18307 *total = ix86_cost->shift_var * 6 + COSTS_N_INSNS (2);
18312 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
18313 *total = ix86_cost->shift_const;
18315 *total = ix86_cost->shift_var;
18320 if (FLOAT_MODE_P (mode))
18322 *total = ix86_cost->fmul;
18327 rtx op0 = XEXP (x, 0);
18328 rtx op1 = XEXP (x, 1);
18330 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
18332 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
18333 for (nbits = 0; value != 0; value &= value - 1)
18337 /* This is arbitrary. */
18340 /* Compute costs correctly for widening multiplication. */
18341 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op1) == ZERO_EXTEND)
18342 && GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))) * 2
18343 == GET_MODE_SIZE (mode))
18345 int is_mulwiden = 0;
18346 enum machine_mode inner_mode = GET_MODE (op0);
18348 if (GET_CODE (op0) == GET_CODE (op1))
18349 is_mulwiden = 1, op1 = XEXP (op1, 0);
18350 else if (GET_CODE (op1) == CONST_INT)
18352 if (GET_CODE (op0) == SIGN_EXTEND)
18353 is_mulwiden = trunc_int_for_mode (INTVAL (op1), inner_mode)
18356 is_mulwiden = !(INTVAL (op1) & ~GET_MODE_MASK (inner_mode));
18360 op0 = XEXP (op0, 0), mode = GET_MODE (op0);
18363 *total = (ix86_cost->mult_init[MODE_INDEX (mode)]
18364 + nbits * ix86_cost->mult_bit
18365 + rtx_cost (op0, outer_code) + rtx_cost (op1, outer_code));
18374 if (FLOAT_MODE_P (mode))
18375 *total = ix86_cost->fdiv;
18377 *total = ix86_cost->divide[MODE_INDEX (mode)];
18381 if (FLOAT_MODE_P (mode))
18382 *total = ix86_cost->fadd;
18383 else if (GET_MODE_CLASS (mode) == MODE_INT
18384 && GET_MODE_BITSIZE (mode) <= GET_MODE_BITSIZE (Pmode))
18386 if (GET_CODE (XEXP (x, 0)) == PLUS
18387 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
18388 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
18389 && CONSTANT_P (XEXP (x, 1)))
18391 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1));
18392 if (val == 2 || val == 4 || val == 8)
18394 *total = ix86_cost->lea;
18395 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code);
18396 *total += rtx_cost (XEXP (XEXP (XEXP (x, 0), 0), 0),
18398 *total += rtx_cost (XEXP (x, 1), outer_code);
18402 else if (GET_CODE (XEXP (x, 0)) == MULT
18403 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
18405 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (x, 0), 1));
18406 if (val == 2 || val == 4 || val == 8)
18408 *total = ix86_cost->lea;
18409 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code);
18410 *total += rtx_cost (XEXP (x, 1), outer_code);
18414 else if (GET_CODE (XEXP (x, 0)) == PLUS)
18416 *total = ix86_cost->lea;
18417 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code);
18418 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code);
18419 *total += rtx_cost (XEXP (x, 1), outer_code);
18426 if (FLOAT_MODE_P (mode))
18428 *total = ix86_cost->fadd;
18436 if (!TARGET_64BIT && mode == DImode)
18438 *total = (ix86_cost->add * 2
18439 + (rtx_cost (XEXP (x, 0), outer_code)
18440 << (GET_MODE (XEXP (x, 0)) != DImode))
18441 + (rtx_cost (XEXP (x, 1), outer_code)
18442 << (GET_MODE (XEXP (x, 1)) != DImode)));
18448 if (FLOAT_MODE_P (mode))
18450 *total = ix86_cost->fchs;
18456 if (!TARGET_64BIT && mode == DImode)
18457 *total = ix86_cost->add * 2;
18459 *total = ix86_cost->add;
18463 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTRACT
18464 && XEXP (XEXP (x, 0), 1) == const1_rtx
18465 && GET_CODE (XEXP (XEXP (x, 0), 2)) == CONST_INT
18466 && XEXP (x, 1) == const0_rtx)
18468 /* This kind of construct is implemented using test[bwl].
18469 Treat it as if we had an AND. */
18470 *total = (ix86_cost->add
18471 + rtx_cost (XEXP (XEXP (x, 0), 0), outer_code)
18472 + rtx_cost (const1_rtx, outer_code));
18478 if (!TARGET_SSE_MATH
18480 || (mode == DFmode && !TARGET_SSE2))
18485 if (FLOAT_MODE_P (mode))
18486 *total = ix86_cost->fabs;
18490 if (FLOAT_MODE_P (mode))
18491 *total = ix86_cost->fsqrt;
18495 if (XINT (x, 1) == UNSPEC_TP)
18506 static int current_machopic_label_num;
18508 /* Given a symbol name and its associated stub, write out the
18509 definition of the stub. */
18512 machopic_output_stub (FILE *file, const char *symb, const char *stub)
18514 unsigned int length;
18515 char *binder_name, *symbol_name, lazy_ptr_name[32];
18516 int label = ++current_machopic_label_num;
18518 /* For 64-bit we shouldn't get here. */
18519 gcc_assert (!TARGET_64BIT);
18521 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
18522 symb = (*targetm.strip_name_encoding) (symb);
18524 length = strlen (stub);
18525 binder_name = alloca (length + 32);
18526 GEN_BINDER_NAME_FOR_STUB (binder_name, stub, length);
18528 length = strlen (symb);
18529 symbol_name = alloca (length + 32);
18530 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
18532 sprintf (lazy_ptr_name, "L%d$lz", label);
18535 switch_to_section (darwin_sections[machopic_picsymbol_stub_section]);
18537 switch_to_section (darwin_sections[machopic_symbol_stub_section]);
18539 fprintf (file, "%s:\n", stub);
18540 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
18544 fprintf (file, "\tcall\tLPC$%d\nLPC$%d:\tpopl\t%%eax\n", label, label);
18545 fprintf (file, "\tmovl\t%s-LPC$%d(%%eax),%%edx\n", lazy_ptr_name, label);
18546 fprintf (file, "\tjmp\t*%%edx\n");
18549 fprintf (file, "\tjmp\t*%s\n", lazy_ptr_name);
18551 fprintf (file, "%s:\n", binder_name);
18555 fprintf (file, "\tlea\t%s-LPC$%d(%%eax),%%eax\n", lazy_ptr_name, label);
18556 fprintf (file, "\tpushl\t%%eax\n");
18559 fprintf (file, "\tpushl\t$%s\n", lazy_ptr_name);
18561 fprintf (file, "\tjmp\tdyld_stub_binding_helper\n");
18563 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
18564 fprintf (file, "%s:\n", lazy_ptr_name);
18565 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
18566 fprintf (file, "\t.long %s\n", binder_name);
18570 darwin_x86_file_end (void)
18572 darwin_file_end ();
18575 #endif /* TARGET_MACHO */
18577 /* Order the registers for register allocator. */
18580 x86_order_regs_for_local_alloc (void)
18585 /* First allocate the local general purpose registers. */
18586 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
18587 if (GENERAL_REGNO_P (i) && call_used_regs[i])
18588 reg_alloc_order [pos++] = i;
18590 /* Global general purpose registers. */
18591 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
18592 if (GENERAL_REGNO_P (i) && !call_used_regs[i])
18593 reg_alloc_order [pos++] = i;
18595 /* x87 registers come first in case we are doing FP math
18597 if (!TARGET_SSE_MATH)
18598 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
18599 reg_alloc_order [pos++] = i;
18601 /* SSE registers. */
18602 for (i = FIRST_SSE_REG; i <= LAST_SSE_REG; i++)
18603 reg_alloc_order [pos++] = i;
18604 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
18605 reg_alloc_order [pos++] = i;
18607 /* x87 registers. */
18608 if (TARGET_SSE_MATH)
18609 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
18610 reg_alloc_order [pos++] = i;
18612 for (i = FIRST_MMX_REG; i <= LAST_MMX_REG; i++)
18613 reg_alloc_order [pos++] = i;
18615 /* Initialize the rest of array as we do not allocate some registers
18617 while (pos < FIRST_PSEUDO_REGISTER)
18618 reg_alloc_order [pos++] = 0;
18621 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
18622 struct attribute_spec.handler. */
18624 ix86_handle_struct_attribute (tree *node, tree name,
18625 tree args ATTRIBUTE_UNUSED,
18626 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
18629 if (DECL_P (*node))
18631 if (TREE_CODE (*node) == TYPE_DECL)
18632 type = &TREE_TYPE (*node);
18637 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
18638 || TREE_CODE (*type) == UNION_TYPE)))
18640 warning (OPT_Wattributes, "%qs attribute ignored",
18641 IDENTIFIER_POINTER (name));
18642 *no_add_attrs = true;
18645 else if ((is_attribute_p ("ms_struct", name)
18646 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
18647 || ((is_attribute_p ("gcc_struct", name)
18648 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
18650 warning (OPT_Wattributes, "%qs incompatible attribute ignored",
18651 IDENTIFIER_POINTER (name));
18652 *no_add_attrs = true;
18659 ix86_ms_bitfield_layout_p (tree record_type)
18661 return (TARGET_MS_BITFIELD_LAYOUT &&
18662 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
18663 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
18666 /* Returns an expression indicating where the this parameter is
18667 located on entry to the FUNCTION. */
18670 x86_this_parameter (tree function)
18672 tree type = TREE_TYPE (function);
18676 int n = aggregate_value_p (TREE_TYPE (type), type) != 0;
18677 return gen_rtx_REG (DImode, x86_64_int_parameter_registers[n]);
18680 if (ix86_function_regparm (type, function) > 0)
18684 parm = TYPE_ARG_TYPES (type);
18685 /* Figure out whether or not the function has a variable number of
18687 for (; parm; parm = TREE_CHAIN (parm))
18688 if (TREE_VALUE (parm) == void_type_node)
18690 /* If not, the this parameter is in the first argument. */
18694 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
18696 return gen_rtx_REG (SImode, regno);
18700 if (aggregate_value_p (TREE_TYPE (type), type))
18701 return gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, 8));
18703 return gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, 4));
18706 /* Determine whether x86_output_mi_thunk can succeed. */
18709 x86_can_output_mi_thunk (tree thunk ATTRIBUTE_UNUSED,
18710 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
18711 HOST_WIDE_INT vcall_offset, tree function)
18713 /* 64-bit can handle anything. */
18717 /* For 32-bit, everything's fine if we have one free register. */
18718 if (ix86_function_regparm (TREE_TYPE (function), function) < 3)
18721 /* Need a free register for vcall_offset. */
18725 /* Need a free register for GOT references. */
18726 if (flag_pic && !(*targetm.binds_local_p) (function))
18729 /* Otherwise ok. */
18733 /* Output the assembler code for a thunk function. THUNK_DECL is the
18734 declaration for the thunk function itself, FUNCTION is the decl for
18735 the target function. DELTA is an immediate constant offset to be
18736 added to THIS. If VCALL_OFFSET is nonzero, the word at
18737 *(*this + vcall_offset) should be added to THIS. */
18740 x86_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED,
18741 tree thunk ATTRIBUTE_UNUSED, HOST_WIDE_INT delta,
18742 HOST_WIDE_INT vcall_offset, tree function)
18745 rtx this = x86_this_parameter (function);
18748 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
18749 pull it in now and let DELTA benefit. */
18752 else if (vcall_offset)
18754 /* Put the this parameter into %eax. */
18756 xops[1] = this_reg = gen_rtx_REG (Pmode, 0);
18757 output_asm_insn ("mov{l}\t{%0, %1|%1, %0}", xops);
18760 this_reg = NULL_RTX;
18762 /* Adjust the this parameter by a fixed constant. */
18765 xops[0] = GEN_INT (delta);
18766 xops[1] = this_reg ? this_reg : this;
18769 if (!x86_64_general_operand (xops[0], DImode))
18771 tmp = gen_rtx_REG (DImode, R10_REG);
18773 output_asm_insn ("mov{q}\t{%1, %0|%0, %1}", xops);
18777 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
18780 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
18783 /* Adjust the this parameter by a value stored in the vtable. */
18787 tmp = gen_rtx_REG (DImode, R10_REG);
18790 int tmp_regno = 2 /* ECX */;
18791 if (lookup_attribute ("fastcall",
18792 TYPE_ATTRIBUTES (TREE_TYPE (function))))
18793 tmp_regno = 0 /* EAX */;
18794 tmp = gen_rtx_REG (SImode, tmp_regno);
18797 xops[0] = gen_rtx_MEM (Pmode, this_reg);
18800 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
18802 output_asm_insn ("mov{l}\t{%0, %1|%1, %0}", xops);
18804 /* Adjust the this parameter. */
18805 xops[0] = gen_rtx_MEM (Pmode, plus_constant (tmp, vcall_offset));
18806 if (TARGET_64BIT && !memory_operand (xops[0], Pmode))
18808 rtx tmp2 = gen_rtx_REG (DImode, R11_REG);
18809 xops[0] = GEN_INT (vcall_offset);
18811 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
18812 xops[0] = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, tmp, tmp2));
18814 xops[1] = this_reg;
18816 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
18818 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
18821 /* If necessary, drop THIS back to its stack slot. */
18822 if (this_reg && this_reg != this)
18824 xops[0] = this_reg;
18826 output_asm_insn ("mov{l}\t{%0, %1|%1, %0}", xops);
18829 xops[0] = XEXP (DECL_RTL (function), 0);
18832 if (!flag_pic || (*targetm.binds_local_p) (function))
18833 output_asm_insn ("jmp\t%P0", xops);
18836 tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, xops[0]), UNSPEC_GOTPCREL);
18837 tmp = gen_rtx_CONST (Pmode, tmp);
18838 tmp = gen_rtx_MEM (QImode, tmp);
18840 output_asm_insn ("jmp\t%A0", xops);
18845 if (!flag_pic || (*targetm.binds_local_p) (function))
18846 output_asm_insn ("jmp\t%P0", xops);
18851 rtx sym_ref = XEXP (DECL_RTL (function), 0);
18852 tmp = (gen_rtx_SYMBOL_REF
18854 machopic_indirection_name (sym_ref, /*stub_p=*/true)));
18855 tmp = gen_rtx_MEM (QImode, tmp);
18857 output_asm_insn ("jmp\t%0", xops);
18860 #endif /* TARGET_MACHO */
18862 tmp = gen_rtx_REG (SImode, 2 /* ECX */);
18863 output_set_got (tmp, NULL_RTX);
18866 output_asm_insn ("mov{l}\t{%0@GOT(%1), %1|%1, %0@GOT[%1]}", xops);
18867 output_asm_insn ("jmp\t{*}%1", xops);
18873 x86_file_start (void)
18875 default_file_start ();
18877 darwin_file_start ();
18879 if (X86_FILE_START_VERSION_DIRECTIVE)
18880 fputs ("\t.version\t\"01.01\"\n", asm_out_file);
18881 if (X86_FILE_START_FLTUSED)
18882 fputs ("\t.global\t__fltused\n", asm_out_file);
18883 if (ix86_asm_dialect == ASM_INTEL)
18884 fputs ("\t.intel_syntax\n", asm_out_file);
18888 x86_field_alignment (tree field, int computed)
18890 enum machine_mode mode;
18891 tree type = TREE_TYPE (field);
18893 if (TARGET_64BIT || TARGET_ALIGN_DOUBLE)
18895 mode = TYPE_MODE (TREE_CODE (type) == ARRAY_TYPE
18896 ? get_inner_array_type (type) : type);
18897 if (mode == DFmode || mode == DCmode
18898 || GET_MODE_CLASS (mode) == MODE_INT
18899 || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
18900 return MIN (32, computed);
18904 /* Output assembler code to FILE to increment profiler label # LABELNO
18905 for profiling a function entry. */
18907 x86_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED)
18912 #ifndef NO_PROFILE_COUNTERS
18913 fprintf (file, "\tleaq\t%sP%d@(%%rip),%%r11\n", LPREFIX, labelno);
18915 fprintf (file, "\tcall\t*%s@GOTPCREL(%%rip)\n", MCOUNT_NAME);
18919 #ifndef NO_PROFILE_COUNTERS
18920 fprintf (file, "\tmovq\t$%sP%d,%%r11\n", LPREFIX, labelno);
18922 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
18926 #ifndef NO_PROFILE_COUNTERS
18927 fprintf (file, "\tleal\t%sP%d@GOTOFF(%%ebx),%%%s\n",
18928 LPREFIX, labelno, PROFILE_COUNT_REGISTER);
18930 fprintf (file, "\tcall\t*%s@GOT(%%ebx)\n", MCOUNT_NAME);
18934 #ifndef NO_PROFILE_COUNTERS
18935 fprintf (file, "\tmovl\t$%sP%d,%%%s\n", LPREFIX, labelno,
18936 PROFILE_COUNT_REGISTER);
18938 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
18942 /* We don't have exact information about the insn sizes, but we may assume
18943 quite safely that we are informed about all 1 byte insns and memory
18944 address sizes. This is enough to eliminate unnecessary padding in
18948 min_insn_size (rtx insn)
18952 if (!INSN_P (insn) || !active_insn_p (insn))
18955 /* Discard alignments we've emit and jump instructions. */
18956 if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
18957 && XINT (PATTERN (insn), 1) == UNSPECV_ALIGN)
18959 if (GET_CODE (insn) == JUMP_INSN
18960 && (GET_CODE (PATTERN (insn)) == ADDR_VEC
18961 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC))
18964 /* Important case - calls are always 5 bytes.
18965 It is common to have many calls in the row. */
18966 if (GET_CODE (insn) == CALL_INSN
18967 && symbolic_reference_mentioned_p (PATTERN (insn))
18968 && !SIBLING_CALL_P (insn))
18970 if (get_attr_length (insn) <= 1)
18973 /* For normal instructions we may rely on the sizes of addresses
18974 and the presence of symbol to require 4 bytes of encoding.
18975 This is not the case for jumps where references are PC relative. */
18976 if (GET_CODE (insn) != JUMP_INSN)
18978 l = get_attr_length_address (insn);
18979 if (l < 4 && symbolic_reference_mentioned_p (PATTERN (insn)))
18988 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
18992 ix86_avoid_jump_misspredicts (void)
18994 rtx insn, start = get_insns ();
18995 int nbytes = 0, njumps = 0;
18998 /* Look for all minimal intervals of instructions containing 4 jumps.
18999 The intervals are bounded by START and INSN. NBYTES is the total
19000 size of instructions in the interval including INSN and not including
19001 START. When the NBYTES is smaller than 16 bytes, it is possible
19002 that the end of START and INSN ends up in the same 16byte page.
19004 The smallest offset in the page INSN can start is the case where START
19005 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
19006 We add p2align to 16byte window with maxskip 17 - NBYTES + sizeof (INSN).
19008 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
19011 nbytes += min_insn_size (insn);
19013 fprintf(dump_file, "Insn %i estimated to %i bytes\n",
19014 INSN_UID (insn), min_insn_size (insn));
19015 if ((GET_CODE (insn) == JUMP_INSN
19016 && GET_CODE (PATTERN (insn)) != ADDR_VEC
19017 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
19018 || GET_CODE (insn) == CALL_INSN)
19025 start = NEXT_INSN (start);
19026 if ((GET_CODE (start) == JUMP_INSN
19027 && GET_CODE (PATTERN (start)) != ADDR_VEC
19028 && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
19029 || GET_CODE (start) == CALL_INSN)
19030 njumps--, isjump = 1;
19033 nbytes -= min_insn_size (start);
19035 gcc_assert (njumps >= 0);
19037 fprintf (dump_file, "Interval %i to %i has %i bytes\n",
19038 INSN_UID (start), INSN_UID (insn), nbytes);
19040 if (njumps == 3 && isjump && nbytes < 16)
19042 int padsize = 15 - nbytes + min_insn_size (insn);
19045 fprintf (dump_file, "Padding insn %i by %i bytes!\n",
19046 INSN_UID (insn), padsize);
19047 emit_insn_before (gen_align (GEN_INT (padsize)), insn);
19052 /* AMD Athlon works faster
19053 when RET is not destination of conditional jump or directly preceded
19054 by other jump instruction. We avoid the penalty by inserting NOP just
19055 before the RET instructions in such cases. */
19057 ix86_pad_returns (void)
19062 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
19064 basic_block bb = e->src;
19065 rtx ret = BB_END (bb);
19067 bool replace = false;
19069 if (GET_CODE (ret) != JUMP_INSN || GET_CODE (PATTERN (ret)) != RETURN
19070 || !maybe_hot_bb_p (bb))
19072 for (prev = PREV_INSN (ret); prev; prev = PREV_INSN (prev))
19073 if (active_insn_p (prev) || GET_CODE (prev) == CODE_LABEL)
19075 if (prev && GET_CODE (prev) == CODE_LABEL)
19080 FOR_EACH_EDGE (e, ei, bb->preds)
19081 if (EDGE_FREQUENCY (e) && e->src->index >= 0
19082 && !(e->flags & EDGE_FALLTHRU))
19087 prev = prev_active_insn (ret);
19089 && ((GET_CODE (prev) == JUMP_INSN && any_condjump_p (prev))
19090 || GET_CODE (prev) == CALL_INSN))
19092 /* Empty functions get branch mispredict even when the jump destination
19093 is not visible to us. */
19094 if (!prev && cfun->function_frequency > FUNCTION_FREQUENCY_UNLIKELY_EXECUTED)
19099 emit_insn_before (gen_return_internal_long (), ret);
19105 /* Implement machine specific optimizations. We implement padding of returns
19106 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
19110 if (TARGET_PAD_RETURNS && optimize && !optimize_size)
19111 ix86_pad_returns ();
19112 if (TARGET_FOUR_JUMP_LIMIT && optimize && !optimize_size)
19113 ix86_avoid_jump_misspredicts ();
19116 /* Return nonzero when QImode register that must be represented via REX prefix
19119 x86_extended_QIreg_mentioned_p (rtx insn)
19122 extract_insn_cached (insn);
19123 for (i = 0; i < recog_data.n_operands; i++)
19124 if (REG_P (recog_data.operand[i])
19125 && REGNO (recog_data.operand[i]) >= 4)
19130 /* Return nonzero when P points to register encoded via REX prefix.
19131 Called via for_each_rtx. */
19133 extended_reg_mentioned_1 (rtx *p, void *data ATTRIBUTE_UNUSED)
19135 unsigned int regno;
19138 regno = REGNO (*p);
19139 return REX_INT_REGNO_P (regno) || REX_SSE_REGNO_P (regno);
19142 /* Return true when INSN mentions register that must be encoded using REX
19145 x86_extended_reg_mentioned_p (rtx insn)
19147 return for_each_rtx (&PATTERN (insn), extended_reg_mentioned_1, NULL);
19150 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
19151 optabs would emit if we didn't have TFmode patterns. */
19154 x86_emit_floatuns (rtx operands[2])
19156 rtx neglab, donelab, i0, i1, f0, in, out;
19157 enum machine_mode mode, inmode;
19159 inmode = GET_MODE (operands[1]);
19160 gcc_assert (inmode == SImode || inmode == DImode);
19163 in = force_reg (inmode, operands[1]);
19164 mode = GET_MODE (out);
19165 neglab = gen_label_rtx ();
19166 donelab = gen_label_rtx ();
19167 i1 = gen_reg_rtx (Pmode);
19168 f0 = gen_reg_rtx (mode);
19170 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, Pmode, 0, neglab);
19172 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
19173 emit_jump_insn (gen_jump (donelab));
19176 emit_label (neglab);
19178 i0 = expand_simple_binop (Pmode, LSHIFTRT, in, const1_rtx, NULL, 1, OPTAB_DIRECT);
19179 i1 = expand_simple_binop (Pmode, AND, in, const1_rtx, NULL, 1, OPTAB_DIRECT);
19180 i0 = expand_simple_binop (Pmode, IOR, i0, i1, i0, 1, OPTAB_DIRECT);
19181 expand_float (f0, i0, 0);
19182 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
19184 emit_label (donelab);
19187 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
19188 with all elements equal to VAR. Return true if successful. */
19191 ix86_expand_vector_init_duplicate (bool mmx_ok, enum machine_mode mode,
19192 rtx target, rtx val)
19194 enum machine_mode smode, wsmode, wvmode;
19209 val = force_reg (GET_MODE_INNER (mode), val);
19210 x = gen_rtx_VEC_DUPLICATE (mode, val);
19211 emit_insn (gen_rtx_SET (VOIDmode, target, x));
19217 if (TARGET_SSE || TARGET_3DNOW_A)
19219 val = gen_lowpart (SImode, val);
19220 x = gen_rtx_TRUNCATE (HImode, val);
19221 x = gen_rtx_VEC_DUPLICATE (mode, x);
19222 emit_insn (gen_rtx_SET (VOIDmode, target, x));
19244 /* Extend HImode to SImode using a paradoxical SUBREG. */
19245 tmp1 = gen_reg_rtx (SImode);
19246 emit_move_insn (tmp1, gen_lowpart (SImode, val));
19247 /* Insert the SImode value as low element of V4SImode vector. */
19248 tmp2 = gen_reg_rtx (V4SImode);
19249 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
19250 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
19251 CONST0_RTX (V4SImode),
19253 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
19254 /* Cast the V4SImode vector back to a V8HImode vector. */
19255 tmp1 = gen_reg_rtx (V8HImode);
19256 emit_move_insn (tmp1, gen_lowpart (V8HImode, tmp2));
19257 /* Duplicate the low short through the whole low SImode word. */
19258 emit_insn (gen_sse2_punpcklwd (tmp1, tmp1, tmp1));
19259 /* Cast the V8HImode vector back to a V4SImode vector. */
19260 tmp2 = gen_reg_rtx (V4SImode);
19261 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
19262 /* Replicate the low element of the V4SImode vector. */
19263 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
19264 /* Cast the V2SImode back to V8HImode, and store in target. */
19265 emit_move_insn (target, gen_lowpart (V8HImode, tmp2));
19276 /* Extend QImode to SImode using a paradoxical SUBREG. */
19277 tmp1 = gen_reg_rtx (SImode);
19278 emit_move_insn (tmp1, gen_lowpart (SImode, val));
19279 /* Insert the SImode value as low element of V4SImode vector. */
19280 tmp2 = gen_reg_rtx (V4SImode);
19281 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
19282 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
19283 CONST0_RTX (V4SImode),
19285 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
19286 /* Cast the V4SImode vector back to a V16QImode vector. */
19287 tmp1 = gen_reg_rtx (V16QImode);
19288 emit_move_insn (tmp1, gen_lowpart (V16QImode, tmp2));
19289 /* Duplicate the low byte through the whole low SImode word. */
19290 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
19291 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
19292 /* Cast the V16QImode vector back to a V4SImode vector. */
19293 tmp2 = gen_reg_rtx (V4SImode);
19294 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
19295 /* Replicate the low element of the V4SImode vector. */
19296 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
19297 /* Cast the V2SImode back to V16QImode, and store in target. */
19298 emit_move_insn (target, gen_lowpart (V16QImode, tmp2));
19306 /* Replicate the value once into the next wider mode and recurse. */
19307 val = convert_modes (wsmode, smode, val, true);
19308 x = expand_simple_binop (wsmode, ASHIFT, val,
19309 GEN_INT (GET_MODE_BITSIZE (smode)),
19310 NULL_RTX, 1, OPTAB_LIB_WIDEN);
19311 val = expand_simple_binop (wsmode, IOR, val, x, x, 1, OPTAB_LIB_WIDEN);
19313 x = gen_reg_rtx (wvmode);
19314 if (!ix86_expand_vector_init_duplicate (mmx_ok, wvmode, x, val))
19315 gcc_unreachable ();
19316 emit_move_insn (target, gen_lowpart (mode, x));
19324 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
19325 whose ONE_VAR element is VAR, and other elements are zero. Return true
19329 ix86_expand_vector_init_one_nonzero (bool mmx_ok, enum machine_mode mode,
19330 rtx target, rtx var, int one_var)
19332 enum machine_mode vsimode;
19348 var = force_reg (GET_MODE_INNER (mode), var);
19349 x = gen_rtx_VEC_CONCAT (mode, var, CONST0_RTX (GET_MODE_INNER (mode)));
19350 emit_insn (gen_rtx_SET (VOIDmode, target, x));
19355 if (!REG_P (target) || REGNO (target) < FIRST_PSEUDO_REGISTER)
19356 new_target = gen_reg_rtx (mode);
19358 new_target = target;
19359 var = force_reg (GET_MODE_INNER (mode), var);
19360 x = gen_rtx_VEC_DUPLICATE (mode, var);
19361 x = gen_rtx_VEC_MERGE (mode, x, CONST0_RTX (mode), const1_rtx);
19362 emit_insn (gen_rtx_SET (VOIDmode, new_target, x));
19365 /* We need to shuffle the value to the correct position, so
19366 create a new pseudo to store the intermediate result. */
19368 /* With SSE2, we can use the integer shuffle insns. */
19369 if (mode != V4SFmode && TARGET_SSE2)
19371 emit_insn (gen_sse2_pshufd_1 (new_target, new_target,
19373 GEN_INT (one_var == 1 ? 0 : 1),
19374 GEN_INT (one_var == 2 ? 0 : 1),
19375 GEN_INT (one_var == 3 ? 0 : 1)));
19376 if (target != new_target)
19377 emit_move_insn (target, new_target);
19381 /* Otherwise convert the intermediate result to V4SFmode and
19382 use the SSE1 shuffle instructions. */
19383 if (mode != V4SFmode)
19385 tmp = gen_reg_rtx (V4SFmode);
19386 emit_move_insn (tmp, gen_lowpart (V4SFmode, new_target));
19391 emit_insn (gen_sse_shufps_1 (tmp, tmp, tmp,
19393 GEN_INT (one_var == 1 ? 0 : 1),
19394 GEN_INT (one_var == 2 ? 0+4 : 1+4),
19395 GEN_INT (one_var == 3 ? 0+4 : 1+4)));
19397 if (mode != V4SFmode)
19398 emit_move_insn (target, gen_lowpart (V4SImode, tmp));
19399 else if (tmp != target)
19400 emit_move_insn (target, tmp);
19402 else if (target != new_target)
19403 emit_move_insn (target, new_target);
19408 vsimode = V4SImode;
19414 vsimode = V2SImode;
19420 /* Zero extend the variable element to SImode and recurse. */
19421 var = convert_modes (SImode, GET_MODE_INNER (mode), var, true);
19423 x = gen_reg_rtx (vsimode);
19424 if (!ix86_expand_vector_init_one_nonzero (mmx_ok, vsimode, x,
19426 gcc_unreachable ();
19428 emit_move_insn (target, gen_lowpart (mode, x));
19436 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
19437 consisting of the values in VALS. It is known that all elements
19438 except ONE_VAR are constants. Return true if successful. */
19441 ix86_expand_vector_init_one_var (bool mmx_ok, enum machine_mode mode,
19442 rtx target, rtx vals, int one_var)
19444 rtx var = XVECEXP (vals, 0, one_var);
19445 enum machine_mode wmode;
19448 const_vec = copy_rtx (vals);
19449 XVECEXP (const_vec, 0, one_var) = CONST0_RTX (GET_MODE_INNER (mode));
19450 const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (const_vec, 0));
19458 /* For the two element vectors, it's just as easy to use
19459 the general case. */
19475 /* There's no way to set one QImode entry easily. Combine
19476 the variable value with its adjacent constant value, and
19477 promote to an HImode set. */
19478 x = XVECEXP (vals, 0, one_var ^ 1);
19481 var = convert_modes (HImode, QImode, var, true);
19482 var = expand_simple_binop (HImode, ASHIFT, var, GEN_INT (8),
19483 NULL_RTX, 1, OPTAB_LIB_WIDEN);
19484 x = GEN_INT (INTVAL (x) & 0xff);
19488 var = convert_modes (HImode, QImode, var, true);
19489 x = gen_int_mode (INTVAL (x) << 8, HImode);
19491 if (x != const0_rtx)
19492 var = expand_simple_binop (HImode, IOR, var, x, var,
19493 1, OPTAB_LIB_WIDEN);
19495 x = gen_reg_rtx (wmode);
19496 emit_move_insn (x, gen_lowpart (wmode, const_vec));
19497 ix86_expand_vector_set (mmx_ok, x, var, one_var >> 1);
19499 emit_move_insn (target, gen_lowpart (mode, x));
19506 emit_move_insn (target, const_vec);
19507 ix86_expand_vector_set (mmx_ok, target, var, one_var);
19511 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
19512 all values variable, and none identical. */
19515 ix86_expand_vector_init_general (bool mmx_ok, enum machine_mode mode,
19516 rtx target, rtx vals)
19518 enum machine_mode half_mode = GET_MODE_INNER (mode);
19519 rtx op0 = NULL, op1 = NULL;
19520 bool use_vec_concat = false;
19526 if (!mmx_ok && !TARGET_SSE)
19532 /* For the two element vectors, we always implement VEC_CONCAT. */
19533 op0 = XVECEXP (vals, 0, 0);
19534 op1 = XVECEXP (vals, 0, 1);
19535 use_vec_concat = true;
19539 half_mode = V2SFmode;
19542 half_mode = V2SImode;
19548 /* For V4SF and V4SI, we implement a concat of two V2 vectors.
19549 Recurse to load the two halves. */
19551 op0 = gen_reg_rtx (half_mode);
19552 v = gen_rtvec (2, XVECEXP (vals, 0, 0), XVECEXP (vals, 0, 1));
19553 ix86_expand_vector_init (false, op0, gen_rtx_PARALLEL (half_mode, v));
19555 op1 = gen_reg_rtx (half_mode);
19556 v = gen_rtvec (2, XVECEXP (vals, 0, 2), XVECEXP (vals, 0, 3));
19557 ix86_expand_vector_init (false, op1, gen_rtx_PARALLEL (half_mode, v));
19559 use_vec_concat = true;
19570 gcc_unreachable ();
19573 if (use_vec_concat)
19575 if (!register_operand (op0, half_mode))
19576 op0 = force_reg (half_mode, op0);
19577 if (!register_operand (op1, half_mode))
19578 op1 = force_reg (half_mode, op1);
19580 emit_insn (gen_rtx_SET (VOIDmode, target,
19581 gen_rtx_VEC_CONCAT (mode, op0, op1)));
19585 int i, j, n_elts, n_words, n_elt_per_word;
19586 enum machine_mode inner_mode;
19587 rtx words[4], shift;
19589 inner_mode = GET_MODE_INNER (mode);
19590 n_elts = GET_MODE_NUNITS (mode);
19591 n_words = GET_MODE_SIZE (mode) / UNITS_PER_WORD;
19592 n_elt_per_word = n_elts / n_words;
19593 shift = GEN_INT (GET_MODE_BITSIZE (inner_mode));
19595 for (i = 0; i < n_words; ++i)
19597 rtx word = NULL_RTX;
19599 for (j = 0; j < n_elt_per_word; ++j)
19601 rtx elt = XVECEXP (vals, 0, (i+1)*n_elt_per_word - j - 1);
19602 elt = convert_modes (word_mode, inner_mode, elt, true);
19608 word = expand_simple_binop (word_mode, ASHIFT, word, shift,
19609 word, 1, OPTAB_LIB_WIDEN);
19610 word = expand_simple_binop (word_mode, IOR, word, elt,
19611 word, 1, OPTAB_LIB_WIDEN);
19619 emit_move_insn (target, gen_lowpart (mode, words[0]));
19620 else if (n_words == 2)
19622 rtx tmp = gen_reg_rtx (mode);
19623 emit_insn (gen_rtx_CLOBBER (VOIDmode, tmp));
19624 emit_move_insn (gen_lowpart (word_mode, tmp), words[0]);
19625 emit_move_insn (gen_highpart (word_mode, tmp), words[1]);
19626 emit_move_insn (target, tmp);
19628 else if (n_words == 4)
19630 rtx tmp = gen_reg_rtx (V4SImode);
19631 vals = gen_rtx_PARALLEL (V4SImode, gen_rtvec_v (4, words));
19632 ix86_expand_vector_init_general (false, V4SImode, tmp, vals);
19633 emit_move_insn (target, gen_lowpart (mode, tmp));
19636 gcc_unreachable ();
19640 /* Initialize vector TARGET via VALS. Suppress the use of MMX
19641 instructions unless MMX_OK is true. */
19644 ix86_expand_vector_init (bool mmx_ok, rtx target, rtx vals)
19646 enum machine_mode mode = GET_MODE (target);
19647 enum machine_mode inner_mode = GET_MODE_INNER (mode);
19648 int n_elts = GET_MODE_NUNITS (mode);
19649 int n_var = 0, one_var = -1;
19650 bool all_same = true, all_const_zero = true;
19654 for (i = 0; i < n_elts; ++i)
19656 x = XVECEXP (vals, 0, i);
19657 if (!CONSTANT_P (x))
19658 n_var++, one_var = i;
19659 else if (x != CONST0_RTX (inner_mode))
19660 all_const_zero = false;
19661 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
19665 /* Constants are best loaded from the constant pool. */
19668 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
19672 /* If all values are identical, broadcast the value. */
19674 && ix86_expand_vector_init_duplicate (mmx_ok, mode, target,
19675 XVECEXP (vals, 0, 0)))
19678 /* Values where only one field is non-constant are best loaded from
19679 the pool and overwritten via move later. */
19683 && ix86_expand_vector_init_one_nonzero (mmx_ok, mode, target,
19684 XVECEXP (vals, 0, one_var),
19688 if (ix86_expand_vector_init_one_var (mmx_ok, mode, target, vals, one_var))
19692 ix86_expand_vector_init_general (mmx_ok, mode, target, vals);
19696 ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt)
19698 enum machine_mode mode = GET_MODE (target);
19699 enum machine_mode inner_mode = GET_MODE_INNER (mode);
19700 bool use_vec_merge = false;
19709 tmp = gen_reg_rtx (GET_MODE_INNER (mode));
19710 ix86_expand_vector_extract (true, tmp, target, 1 - elt);
19712 tmp = gen_rtx_VEC_CONCAT (mode, tmp, val);
19714 tmp = gen_rtx_VEC_CONCAT (mode, val, tmp);
19715 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
19725 /* For the two element vectors, we implement a VEC_CONCAT with
19726 the extraction of the other element. */
19728 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (1 - elt)));
19729 tmp = gen_rtx_VEC_SELECT (inner_mode, target, tmp);
19732 op0 = val, op1 = tmp;
19734 op0 = tmp, op1 = val;
19736 tmp = gen_rtx_VEC_CONCAT (mode, op0, op1);
19737 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
19745 use_vec_merge = true;
19749 /* tmp = target = A B C D */
19750 tmp = copy_to_reg (target);
19751 /* target = A A B B */
19752 emit_insn (gen_sse_unpcklps (target, target, target));
19753 /* target = X A B B */
19754 ix86_expand_vector_set (false, target, val, 0);
19755 /* target = A X C D */
19756 emit_insn (gen_sse_shufps_1 (target, target, tmp,
19757 GEN_INT (1), GEN_INT (0),
19758 GEN_INT (2+4), GEN_INT (3+4)));
19762 /* tmp = target = A B C D */
19763 tmp = copy_to_reg (target);
19764 /* tmp = X B C D */
19765 ix86_expand_vector_set (false, tmp, val, 0);
19766 /* target = A B X D */
19767 emit_insn (gen_sse_shufps_1 (target, target, tmp,
19768 GEN_INT (0), GEN_INT (1),
19769 GEN_INT (0+4), GEN_INT (3+4)));
19773 /* tmp = target = A B C D */
19774 tmp = copy_to_reg (target);
19775 /* tmp = X B C D */
19776 ix86_expand_vector_set (false, tmp, val, 0);
19777 /* target = A B X D */
19778 emit_insn (gen_sse_shufps_1 (target, target, tmp,
19779 GEN_INT (0), GEN_INT (1),
19780 GEN_INT (2+4), GEN_INT (0+4)));
19784 gcc_unreachable ();
19789 /* Element 0 handled by vec_merge below. */
19792 use_vec_merge = true;
19798 /* With SSE2, use integer shuffles to swap element 0 and ELT,
19799 store into element 0, then shuffle them back. */
19803 order[0] = GEN_INT (elt);
19804 order[1] = const1_rtx;
19805 order[2] = const2_rtx;
19806 order[3] = GEN_INT (3);
19807 order[elt] = const0_rtx;
19809 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
19810 order[1], order[2], order[3]));
19812 ix86_expand_vector_set (false, target, val, 0);
19814 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
19815 order[1], order[2], order[3]));
19819 /* For SSE1, we have to reuse the V4SF code. */
19820 ix86_expand_vector_set (false, gen_lowpart (V4SFmode, target),
19821 gen_lowpart (SFmode, val), elt);
19826 use_vec_merge = TARGET_SSE2;
19829 use_vec_merge = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
19840 tmp = gen_rtx_VEC_DUPLICATE (mode, val);
19841 tmp = gen_rtx_VEC_MERGE (mode, tmp, target, GEN_INT (1 << elt));
19842 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
19846 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
19848 emit_move_insn (mem, target);
19850 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
19851 emit_move_insn (tmp, val);
19853 emit_move_insn (target, mem);
19858 ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt)
19860 enum machine_mode mode = GET_MODE (vec);
19861 enum machine_mode inner_mode = GET_MODE_INNER (mode);
19862 bool use_vec_extr = false;
19875 use_vec_extr = true;
19887 tmp = gen_reg_rtx (mode);
19888 emit_insn (gen_sse_shufps_1 (tmp, vec, vec,
19889 GEN_INT (elt), GEN_INT (elt),
19890 GEN_INT (elt+4), GEN_INT (elt+4)));
19894 tmp = gen_reg_rtx (mode);
19895 emit_insn (gen_sse_unpckhps (tmp, vec, vec));
19899 gcc_unreachable ();
19902 use_vec_extr = true;
19917 tmp = gen_reg_rtx (mode);
19918 emit_insn (gen_sse2_pshufd_1 (tmp, vec,
19919 GEN_INT (elt), GEN_INT (elt),
19920 GEN_INT (elt), GEN_INT (elt)));
19924 tmp = gen_reg_rtx (mode);
19925 emit_insn (gen_sse2_punpckhdq (tmp, vec, vec));
19929 gcc_unreachable ();
19932 use_vec_extr = true;
19937 /* For SSE1, we have to reuse the V4SF code. */
19938 ix86_expand_vector_extract (false, gen_lowpart (SFmode, target),
19939 gen_lowpart (V4SFmode, vec), elt);
19945 use_vec_extr = TARGET_SSE2;
19948 use_vec_extr = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
19953 /* ??? Could extract the appropriate HImode element and shift. */
19960 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (elt)));
19961 tmp = gen_rtx_VEC_SELECT (inner_mode, vec, tmp);
19963 /* Let the rtl optimizers know about the zero extension performed. */
19964 if (inner_mode == HImode)
19966 tmp = gen_rtx_ZERO_EXTEND (SImode, tmp);
19967 target = gen_lowpart (SImode, target);
19970 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
19974 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
19976 emit_move_insn (mem, vec);
19978 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
19979 emit_move_insn (target, tmp);
19983 /* Expand a vector reduction on V4SFmode for SSE1. FN is the binary
19984 pattern to reduce; DEST is the destination; IN is the input vector. */
19987 ix86_expand_reduc_v4sf (rtx (*fn) (rtx, rtx, rtx), rtx dest, rtx in)
19989 rtx tmp1, tmp2, tmp3;
19991 tmp1 = gen_reg_rtx (V4SFmode);
19992 tmp2 = gen_reg_rtx (V4SFmode);
19993 tmp3 = gen_reg_rtx (V4SFmode);
19995 emit_insn (gen_sse_movhlps (tmp1, in, in));
19996 emit_insn (fn (tmp2, tmp1, in));
19998 emit_insn (gen_sse_shufps_1 (tmp3, tmp2, tmp2,
19999 GEN_INT (1), GEN_INT (1),
20000 GEN_INT (1+4), GEN_INT (1+4)));
20001 emit_insn (fn (dest, tmp2, tmp3));
20004 /* Target hook for scalar_mode_supported_p. */
20006 ix86_scalar_mode_supported_p (enum machine_mode mode)
20008 if (DECIMAL_FLOAT_MODE_P (mode))
20011 return default_scalar_mode_supported_p (mode);
20014 /* Implements target hook vector_mode_supported_p. */
20016 ix86_vector_mode_supported_p (enum machine_mode mode)
20018 if (TARGET_SSE && VALID_SSE_REG_MODE (mode))
20020 if (TARGET_SSE2 && VALID_SSE2_REG_MODE (mode))
20022 if (TARGET_MMX && VALID_MMX_REG_MODE (mode))
20024 if (TARGET_3DNOW && VALID_MMX_REG_MODE_3DNOW (mode))
20029 /* Worker function for TARGET_MD_ASM_CLOBBERS.
20031 We do this in the new i386 backend to maintain source compatibility
20032 with the old cc0-based compiler. */
20035 ix86_md_asm_clobbers (tree outputs ATTRIBUTE_UNUSED,
20036 tree inputs ATTRIBUTE_UNUSED,
20039 clobbers = tree_cons (NULL_TREE, build_string (5, "flags"),
20041 clobbers = tree_cons (NULL_TREE, build_string (4, "fpsr"),
20043 clobbers = tree_cons (NULL_TREE, build_string (7, "dirflag"),
20048 /* Return true if this goes in small data/bss. */
20051 ix86_in_large_data_p (tree exp)
20053 if (ix86_cmodel != CM_MEDIUM && ix86_cmodel != CM_MEDIUM_PIC)
20056 /* Functions are never large data. */
20057 if (TREE_CODE (exp) == FUNCTION_DECL)
20060 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
20062 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
20063 if (strcmp (section, ".ldata") == 0
20064 || strcmp (section, ".lbss") == 0)
20070 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
20072 /* If this is an incomplete type with size 0, then we can't put it
20073 in data because it might be too big when completed. */
20074 if (!size || size > ix86_section_threshold)
20081 ix86_encode_section_info (tree decl, rtx rtl, int first)
20083 default_encode_section_info (decl, rtl, first);
20085 if (TREE_CODE (decl) == VAR_DECL
20086 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
20087 && ix86_in_large_data_p (decl))
20088 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FAR_ADDR;
20091 /* Worker function for REVERSE_CONDITION. */
20094 ix86_reverse_condition (enum rtx_code code, enum machine_mode mode)
20096 return (mode != CCFPmode && mode != CCFPUmode
20097 ? reverse_condition (code)
20098 : reverse_condition_maybe_unordered (code));
20101 /* Output code to perform an x87 FP register move, from OPERANDS[1]
20105 output_387_reg_move (rtx insn, rtx *operands)
20107 if (REG_P (operands[1])
20108 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
20110 if (REGNO (operands[0]) == FIRST_STACK_REG)
20111 return output_387_ffreep (operands, 0);
20112 return "fstp\t%y0";
20114 if (STACK_TOP_P (operands[0]))
20115 return "fld%z1\t%y1";
20119 /* Output code to perform a conditional jump to LABEL, if C2 flag in
20120 FP status register is set. */
20123 ix86_emit_fp_unordered_jump (rtx label)
20125 rtx reg = gen_reg_rtx (HImode);
20128 emit_insn (gen_x86_fnstsw_1 (reg));
20130 if (TARGET_USE_SAHF)
20132 emit_insn (gen_x86_sahf_1 (reg));
20134 temp = gen_rtx_REG (CCmode, FLAGS_REG);
20135 temp = gen_rtx_UNORDERED (VOIDmode, temp, const0_rtx);
20139 emit_insn (gen_testqi_ext_ccno_0 (reg, GEN_INT (0x04)));
20141 temp = gen_rtx_REG (CCNOmode, FLAGS_REG);
20142 temp = gen_rtx_NE (VOIDmode, temp, const0_rtx);
20145 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
20146 gen_rtx_LABEL_REF (VOIDmode, label),
20148 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
20149 emit_jump_insn (temp);
20152 /* Output code to perform a log1p XFmode calculation. */
20154 void ix86_emit_i387_log1p (rtx op0, rtx op1)
20156 rtx label1 = gen_label_rtx ();
20157 rtx label2 = gen_label_rtx ();
20159 rtx tmp = gen_reg_rtx (XFmode);
20160 rtx tmp2 = gen_reg_rtx (XFmode);
20162 emit_insn (gen_absxf2 (tmp, op1));
20163 emit_insn (gen_cmpxf (tmp,
20164 CONST_DOUBLE_FROM_REAL_VALUE (
20165 REAL_VALUE_ATOF ("0.29289321881345247561810596348408353", XFmode),
20167 emit_jump_insn (gen_bge (label1));
20169 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
20170 emit_insn (gen_fyl2xp1_xf3 (op0, tmp2, op1));
20171 emit_jump (label2);
20173 emit_label (label1);
20174 emit_move_insn (tmp, CONST1_RTX (XFmode));
20175 emit_insn (gen_addxf3 (tmp, op1, tmp));
20176 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
20177 emit_insn (gen_fyl2x_xf3 (op0, tmp2, tmp));
20179 emit_label (label2);
20182 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
20185 i386_solaris_elf_named_section (const char *name, unsigned int flags,
20188 /* With Binutils 2.15, the "@unwind" marker must be specified on
20189 every occurrence of the ".eh_frame" section, not just the first
20192 && strcmp (name, ".eh_frame") == 0)
20194 fprintf (asm_out_file, "\t.section\t%s,\"%s\",@unwind\n", name,
20195 flags & SECTION_WRITE ? "aw" : "a");
20198 default_elf_asm_named_section (name, flags, decl);
20201 /* Return the mangling of TYPE if it is an extended fundamental type. */
20203 static const char *
20204 ix86_mangle_fundamental_type (tree type)
20206 switch (TYPE_MODE (type))
20209 /* __float128 is "g". */
20212 /* "long double" or __float80 is "e". */
20219 /* For 32-bit code we can save PIC register setup by using
20220 __stack_chk_fail_local hidden function instead of calling
20221 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
20222 register, so it is better to call __stack_chk_fail directly. */
20225 ix86_stack_protect_fail (void)
20227 return TARGET_64BIT
20228 ? default_external_stack_protect_fail ()
20229 : default_hidden_stack_protect_fail ();
20232 /* Select a format to encode pointers in exception handling data. CODE
20233 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
20234 true if the symbol may be affected by dynamic relocations.
20236 ??? All x86 object file formats are capable of representing this.
20237 After all, the relocation needed is the same as for the call insn.
20238 Whether or not a particular assembler allows us to enter such, I
20239 guess we'll have to see. */
20241 asm_preferred_eh_data_format (int code, int global)
20245 int type = DW_EH_PE_sdata8;
20247 || ix86_cmodel == CM_SMALL_PIC
20248 || (ix86_cmodel == CM_MEDIUM_PIC && (global || code)))
20249 type = DW_EH_PE_sdata4;
20250 return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | type;
20252 if (ix86_cmodel == CM_SMALL
20253 || (ix86_cmodel == CM_MEDIUM && code))
20254 return DW_EH_PE_udata4;
20255 return DW_EH_PE_absptr;
20258 /* Expand copysign from SIGN to the positive value ABS_VALUE
20259 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
20262 ix86_sse_copysign_to_positive (rtx result, rtx abs_value, rtx sign, rtx mask)
20264 enum machine_mode mode = GET_MODE (sign);
20265 rtx sgn = gen_reg_rtx (mode);
20266 if (mask == NULL_RTX)
20268 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), false);
20269 if (!VECTOR_MODE_P (mode))
20271 /* We need to generate a scalar mode mask in this case. */
20272 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
20273 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
20274 mask = gen_reg_rtx (mode);
20275 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
20279 mask = gen_rtx_NOT (mode, mask);
20280 emit_insn (gen_rtx_SET (VOIDmode, sgn,
20281 gen_rtx_AND (mode, mask, sign)));
20282 emit_insn (gen_rtx_SET (VOIDmode, result,
20283 gen_rtx_IOR (mode, abs_value, sgn)));
20286 /* Expand fabs (OP0) and return a new rtx that holds the result. The
20287 mask for masking out the sign-bit is stored in *SMASK, if that is
20290 ix86_expand_sse_fabs (rtx op0, rtx *smask)
20292 enum machine_mode mode = GET_MODE (op0);
20295 xa = gen_reg_rtx (mode);
20296 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), true);
20297 if (!VECTOR_MODE_P (mode))
20299 /* We need to generate a scalar mode mask in this case. */
20300 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
20301 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
20302 mask = gen_reg_rtx (mode);
20303 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
20305 emit_insn (gen_rtx_SET (VOIDmode, xa,
20306 gen_rtx_AND (mode, op0, mask)));
20314 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
20315 swapping the operands if SWAP_OPERANDS is true. The expanded
20316 code is a forward jump to a newly created label in case the
20317 comparison is true. The generated label rtx is returned. */
20319 ix86_expand_sse_compare_and_jump (enum rtx_code code, rtx op0, rtx op1,
20320 bool swap_operands)
20331 label = gen_label_rtx ();
20332 tmp = gen_rtx_REG (CCFPUmode, FLAGS_REG);
20333 emit_insn (gen_rtx_SET (VOIDmode, tmp,
20334 gen_rtx_COMPARE (CCFPUmode, op0, op1)));
20335 tmp = gen_rtx_fmt_ee (code, VOIDmode, tmp, const0_rtx);
20336 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
20337 gen_rtx_LABEL_REF (VOIDmode, label), pc_rtx);
20338 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
20339 JUMP_LABEL (tmp) = label;
20344 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
20345 using comparison code CODE. Operands are swapped for the comparison if
20346 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
20348 ix86_expand_sse_compare_mask (enum rtx_code code, rtx op0, rtx op1,
20349 bool swap_operands)
20351 enum machine_mode mode = GET_MODE (op0);
20352 rtx mask = gen_reg_rtx (mode);
20361 if (mode == DFmode)
20362 emit_insn (gen_sse2_maskcmpdf3 (mask, op0, op1,
20363 gen_rtx_fmt_ee (code, mode, op0, op1)));
20365 emit_insn (gen_sse_maskcmpsf3 (mask, op0, op1,
20366 gen_rtx_fmt_ee (code, mode, op0, op1)));
20371 /* Generate and return a rtx of mode MODE for 2**n where n is the number
20372 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
20374 ix86_gen_TWO52 (enum machine_mode mode)
20376 REAL_VALUE_TYPE TWO52r;
20379 real_ldexp (&TWO52r, &dconst1, mode == DFmode ? 52 : 23);
20380 TWO52 = const_double_from_real_value (TWO52r, mode);
20381 TWO52 = force_reg (mode, TWO52);
20386 /* Expand SSE sequence for computing lround from OP1 storing
20389 ix86_expand_lround (rtx op0, rtx op1)
20391 /* C code for the stuff we're doing below:
20392 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
20395 enum machine_mode mode = GET_MODE (op1);
20396 const struct real_format *fmt;
20397 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
20400 /* load nextafter (0.5, 0.0) */
20401 fmt = REAL_MODE_FORMAT (mode);
20402 real_2expN (&half_minus_pred_half, -(fmt->p) - 1);
20403 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
20405 /* adj = copysign (0.5, op1) */
20406 adj = force_reg (mode, const_double_from_real_value (pred_half, mode));
20407 ix86_sse_copysign_to_positive (adj, adj, force_reg (mode, op1), NULL_RTX);
20409 /* adj = op1 + adj */
20410 adj = expand_simple_binop (mode, PLUS, adj, op1, NULL_RTX, 0, OPTAB_DIRECT);
20412 /* op0 = (imode)adj */
20413 expand_fix (op0, adj, 0);
20416 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
20419 ix86_expand_lfloorceil (rtx op0, rtx op1, bool do_floor)
20421 /* C code for the stuff we're doing below (for do_floor):
20423 xi -= (double)xi > op1 ? 1 : 0;
20426 enum machine_mode fmode = GET_MODE (op1);
20427 enum machine_mode imode = GET_MODE (op0);
20428 rtx ireg, freg, label, tmp;
20430 /* reg = (long)op1 */
20431 ireg = gen_reg_rtx (imode);
20432 expand_fix (ireg, op1, 0);
20434 /* freg = (double)reg */
20435 freg = gen_reg_rtx (fmode);
20436 expand_float (freg, ireg, 0);
20438 /* ireg = (freg > op1) ? ireg - 1 : ireg */
20439 label = ix86_expand_sse_compare_and_jump (UNLE,
20440 freg, op1, !do_floor);
20441 tmp = expand_simple_binop (imode, do_floor ? MINUS : PLUS,
20442 ireg, const1_rtx, NULL_RTX, 0, OPTAB_DIRECT);
20443 emit_move_insn (ireg, tmp);
20445 emit_label (label);
20446 LABEL_NUSES (label) = 1;
20448 emit_move_insn (op0, ireg);
20451 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
20452 result in OPERAND0. */
20454 ix86_expand_rint (rtx operand0, rtx operand1)
20456 /* C code for the stuff we're doing below:
20457 xa = fabs (operand1);
20458 if (!isless (xa, 2**52))
20460 xa = xa + 2**52 - 2**52;
20461 return copysign (xa, operand1);
20463 enum machine_mode mode = GET_MODE (operand0);
20464 rtx res, xa, label, TWO52, mask;
20466 res = gen_reg_rtx (mode);
20467 emit_move_insn (res, operand1);
20469 /* xa = abs (operand1) */
20470 xa = ix86_expand_sse_fabs (res, &mask);
20472 /* if (!isless (xa, TWO52)) goto label; */
20473 TWO52 = ix86_gen_TWO52 (mode);
20474 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
20476 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
20477 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
20479 ix86_sse_copysign_to_positive (res, xa, res, mask);
20481 emit_label (label);
20482 LABEL_NUSES (label) = 1;
20484 emit_move_insn (operand0, res);
20487 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
20490 ix86_expand_floorceildf_32 (rtx operand0, rtx operand1, bool do_floor)
20492 /* C code for the stuff we expand below.
20493 double xa = fabs (x), x2;
20494 if (!isless (xa, TWO52))
20496 xa = xa + TWO52 - TWO52;
20497 x2 = copysign (xa, x);
20506 enum machine_mode mode = GET_MODE (operand0);
20507 rtx xa, TWO52, tmp, label, one, res, mask;
20509 TWO52 = ix86_gen_TWO52 (mode);
20511 /* Temporary for holding the result, initialized to the input
20512 operand to ease control flow. */
20513 res = gen_reg_rtx (mode);
20514 emit_move_insn (res, operand1);
20516 /* xa = abs (operand1) */
20517 xa = ix86_expand_sse_fabs (res, &mask);
20519 /* if (!isless (xa, TWO52)) goto label; */
20520 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
20522 /* xa = xa + TWO52 - TWO52; */
20523 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
20524 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
20526 /* xa = copysign (xa, operand1) */
20527 ix86_sse_copysign_to_positive (xa, xa, res, mask);
20529 /* generate 1.0 or -1.0 */
20530 one = force_reg (mode,
20531 const_double_from_real_value (do_floor
20532 ? dconst1 : dconstm1, mode));
20534 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
20535 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
20536 emit_insn (gen_rtx_SET (VOIDmode, tmp,
20537 gen_rtx_AND (mode, one, tmp)));
20538 /* We always need to subtract here to preserve signed zero. */
20539 tmp = expand_simple_binop (mode, MINUS,
20540 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
20541 emit_move_insn (res, tmp);
20543 emit_label (label);
20544 LABEL_NUSES (label) = 1;
20546 emit_move_insn (operand0, res);
20549 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
20552 ix86_expand_floorceil (rtx operand0, rtx operand1, bool do_floor)
20554 /* C code for the stuff we expand below.
20555 double xa = fabs (x), x2;
20556 if (!isless (xa, TWO52))
20558 x2 = (double)(long)x;
20565 if (HONOR_SIGNED_ZEROS (mode))
20566 return copysign (x2, x);
20569 enum machine_mode mode = GET_MODE (operand0);
20570 rtx xa, xi, TWO52, tmp, label, one, res, mask;
20572 TWO52 = ix86_gen_TWO52 (mode);
20574 /* Temporary for holding the result, initialized to the input
20575 operand to ease control flow. */
20576 res = gen_reg_rtx (mode);
20577 emit_move_insn (res, operand1);
20579 /* xa = abs (operand1) */
20580 xa = ix86_expand_sse_fabs (res, &mask);
20582 /* if (!isless (xa, TWO52)) goto label; */
20583 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
20585 /* xa = (double)(long)x */
20586 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
20587 expand_fix (xi, res, 0);
20588 expand_float (xa, xi, 0);
20591 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
20593 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
20594 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
20595 emit_insn (gen_rtx_SET (VOIDmode, tmp,
20596 gen_rtx_AND (mode, one, tmp)));
20597 tmp = expand_simple_binop (mode, do_floor ? MINUS : PLUS,
20598 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
20599 emit_move_insn (res, tmp);
20601 if (HONOR_SIGNED_ZEROS (mode))
20602 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
20604 emit_label (label);
20605 LABEL_NUSES (label) = 1;
20607 emit_move_insn (operand0, res);
20610 /* Expand SSE sequence for computing round from OPERAND1 storing
20611 into OPERAND0. Sequence that works without relying on DImode truncation
20612 via cvttsd2siq that is only available on 64bit targets. */
20614 ix86_expand_rounddf_32 (rtx operand0, rtx operand1)
20616 /* C code for the stuff we expand below.
20617 double xa = fabs (x), xa2, x2;
20618 if (!isless (xa, TWO52))
20620 Using the absolute value and copying back sign makes
20621 -0.0 -> -0.0 correct.
20622 xa2 = xa + TWO52 - TWO52;
20627 else if (dxa > 0.5)
20629 x2 = copysign (xa2, x);
20632 enum machine_mode mode = GET_MODE (operand0);
20633 rtx xa, xa2, dxa, TWO52, tmp, label, half, mhalf, one, res, mask;
20635 TWO52 = ix86_gen_TWO52 (mode);
20637 /* Temporary for holding the result, initialized to the input
20638 operand to ease control flow. */
20639 res = gen_reg_rtx (mode);
20640 emit_move_insn (res, operand1);
20642 /* xa = abs (operand1) */
20643 xa = ix86_expand_sse_fabs (res, &mask);
20645 /* if (!isless (xa, TWO52)) goto label; */
20646 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
20648 /* xa2 = xa + TWO52 - TWO52; */
20649 xa2 = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
20650 xa2 = expand_simple_binop (mode, MINUS, xa2, TWO52, xa2, 0, OPTAB_DIRECT);
20652 /* dxa = xa2 - xa; */
20653 dxa = expand_simple_binop (mode, MINUS, xa2, xa, NULL_RTX, 0, OPTAB_DIRECT);
20655 /* generate 0.5, 1.0 and -0.5 */
20656 half = force_reg (mode, const_double_from_real_value (dconsthalf, mode));
20657 one = expand_simple_binop (mode, PLUS, half, half, NULL_RTX, 0, OPTAB_DIRECT);
20658 mhalf = expand_simple_binop (mode, MINUS, half, one, NULL_RTX,
20662 tmp = gen_reg_rtx (mode);
20663 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
20664 tmp = ix86_expand_sse_compare_mask (UNGT, dxa, half, false);
20665 emit_insn (gen_rtx_SET (VOIDmode, tmp,
20666 gen_rtx_AND (mode, one, tmp)));
20667 xa2 = expand_simple_binop (mode, MINUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
20668 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
20669 tmp = ix86_expand_sse_compare_mask (UNGE, mhalf, dxa, false);
20670 emit_insn (gen_rtx_SET (VOIDmode, tmp,
20671 gen_rtx_AND (mode, one, tmp)));
20672 xa2 = expand_simple_binop (mode, PLUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
20674 /* res = copysign (xa2, operand1) */
20675 ix86_sse_copysign_to_positive (res, xa2, force_reg (mode, operand1), mask);
20677 emit_label (label);
20678 LABEL_NUSES (label) = 1;
20680 emit_move_insn (operand0, res);
20683 /* Expand SSE sequence for computing trunc from OPERAND1 storing
20686 ix86_expand_trunc (rtx operand0, rtx operand1)
20688 /* C code for SSE variant we expand below.
20689 double xa = fabs (x), x2;
20690 if (!isless (xa, TWO52))
20692 x2 = (double)(long)x;
20693 if (HONOR_SIGNED_ZEROS (mode))
20694 return copysign (x2, x);
20697 enum machine_mode mode = GET_MODE (operand0);
20698 rtx xa, xi, TWO52, label, res, mask;
20700 TWO52 = ix86_gen_TWO52 (mode);
20702 /* Temporary for holding the result, initialized to the input
20703 operand to ease control flow. */
20704 res = gen_reg_rtx (mode);
20705 emit_move_insn (res, operand1);
20707 /* xa = abs (operand1) */
20708 xa = ix86_expand_sse_fabs (res, &mask);
20710 /* if (!isless (xa, TWO52)) goto label; */
20711 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
20713 /* x = (double)(long)x */
20714 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
20715 expand_fix (xi, res, 0);
20716 expand_float (res, xi, 0);
20718 if (HONOR_SIGNED_ZEROS (mode))
20719 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
20721 emit_label (label);
20722 LABEL_NUSES (label) = 1;
20724 emit_move_insn (operand0, res);
20727 /* Expand SSE sequence for computing trunc from OPERAND1 storing
20730 ix86_expand_truncdf_32 (rtx operand0, rtx operand1)
20732 enum machine_mode mode = GET_MODE (operand0);
20733 rtx xa, mask, TWO52, label, one, res, smask, tmp;
20735 /* C code for SSE variant we expand below.
20736 double xa = fabs (x), x2;
20737 if (!isless (xa, TWO52))
20739 xa2 = xa + TWO52 - TWO52;
20743 x2 = copysign (xa2, x);
20747 TWO52 = ix86_gen_TWO52 (mode);
20749 /* Temporary for holding the result, initialized to the input
20750 operand to ease control flow. */
20751 res = gen_reg_rtx (mode);
20752 emit_move_insn (res, operand1);
20754 /* xa = abs (operand1) */
20755 xa = ix86_expand_sse_fabs (res, &smask);
20757 /* if (!isless (xa, TWO52)) goto label; */
20758 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
20760 /* res = xa + TWO52 - TWO52; */
20761 tmp = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
20762 tmp = expand_simple_binop (mode, MINUS, tmp, TWO52, tmp, 0, OPTAB_DIRECT);
20763 emit_move_insn (res, tmp);
20766 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
20768 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
20769 mask = ix86_expand_sse_compare_mask (UNGT, res, xa, false);
20770 emit_insn (gen_rtx_SET (VOIDmode, mask,
20771 gen_rtx_AND (mode, mask, one)));
20772 tmp = expand_simple_binop (mode, MINUS,
20773 res, mask, NULL_RTX, 0, OPTAB_DIRECT);
20774 emit_move_insn (res, tmp);
20776 /* res = copysign (res, operand1) */
20777 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), smask);
20779 emit_label (label);
20780 LABEL_NUSES (label) = 1;
20782 emit_move_insn (operand0, res);
20785 /* Expand SSE sequence for computing round from OPERAND1 storing
20788 ix86_expand_round (rtx operand0, rtx operand1)
20790 /* C code for the stuff we're doing below:
20791 double xa = fabs (x);
20792 if (!isless (xa, TWO52))
20794 xa = (double)(long)(xa + nextafter (0.5, 0.0));
20795 return copysign (xa, x);
20797 enum machine_mode mode = GET_MODE (operand0);
20798 rtx res, TWO52, xa, label, xi, half, mask;
20799 const struct real_format *fmt;
20800 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
20802 /* Temporary for holding the result, initialized to the input
20803 operand to ease control flow. */
20804 res = gen_reg_rtx (mode);
20805 emit_move_insn (res, operand1);
20807 TWO52 = ix86_gen_TWO52 (mode);
20808 xa = ix86_expand_sse_fabs (res, &mask);
20809 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
20811 /* load nextafter (0.5, 0.0) */
20812 fmt = REAL_MODE_FORMAT (mode);
20813 real_2expN (&half_minus_pred_half, -(fmt->p) - 1);
20814 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
20816 /* xa = xa + 0.5 */
20817 half = force_reg (mode, const_double_from_real_value (pred_half, mode));
20818 xa = expand_simple_binop (mode, PLUS, xa, half, NULL_RTX, 0, OPTAB_DIRECT);
20820 /* xa = (double)(int64_t)xa */
20821 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
20822 expand_fix (xi, xa, 0);
20823 expand_float (xa, xi, 0);
20825 /* res = copysign (xa, operand1) */
20826 ix86_sse_copysign_to_positive (res, xa, force_reg (mode, operand1), mask);
20828 emit_label (label);
20829 LABEL_NUSES (label) = 1;
20831 emit_move_insn (operand0, res);
20834 #include "gt-i386.h"
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